From c6807cc80b2ae8bdda24a1dd976e7c29ae803305 Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Mon, 12 Oct 2020 19:03:29 +0500 Subject: [PATCH] Aligner Updated --- el2_ifu_aln_ctl.fir | 2085 +++++++++-------- el2_ifu_aln_ctl.v | 794 ++++--- src/main/scala/ifu/el2_ifu_aln_ctl.scala | 159 +- src/main/scala/lsu/el2_lsu.scala | 5 - .../chisel-module-template.kotlin_module | Bin 0 -> 16 bytes .../classes/ifu/el2_ifu_aln_ctl.class | Bin 175707 -> 175650 bytes target/scala-2.12/classes/ifu/ifu_aln$.class | Bin 3875 -> 3875 bytes .../ifu/ifu_aln$delayedInit$body.class | Bin 736 -> 736 bytes target/scala-2.12/classes/lsu/el2_lsu.class | Bin 500 -> 0 bytes 9 files changed, 1616 insertions(+), 1427 deletions(-) delete mode 100644 src/main/scala/lsu/el2_lsu.scala create mode 100644 target/scala-2.12/classes/META-INF/chisel-module-template.kotlin_module delete mode 100644 target/scala-2.12/classes/lsu/el2_lsu.class diff --git a/el2_ifu_aln_ctl.fir b/el2_ifu_aln_ctl.fir index c554f7dc..8a723c3c 100644 --- a/el2_ifu_aln_ctl.fir +++ b/el2_ifu_aln_ctl.fir @@ -1996,7 +1996,7 @@ circuit el2_ifu_aln_ctl : module el2_ifu_aln_ctl : input clock : Clock input reset : UInt<1> - output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<32>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<32>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<32>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<7>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}} + output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<32>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<32>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<7>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}} wire error_stall_in : UInt<1> error_stall_in <= UInt<1>("h00") @@ -2056,1035 +2056,1086 @@ circuit el2_ifu_aln_ctl : brdata0 <= UInt<1>("h00") wire brdata2 : UInt<12> brdata2 <= UInt<1>("h00") - reg error_stall : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 89:54] - error_stall <= error_stall_in @[el2_ifu_aln_ctl.scala 89:54] - reg f0val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 90:48] - f0val <= f0val_in @[el2_ifu_aln_ctl.scala 90:48] - node _T = or(error_stall, io.ifu_async_error_start) @[el2_ifu_aln_ctl.scala 91:34] - node _T_1 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 91:64] - node _T_2 = and(_T, _T_1) @[el2_ifu_aln_ctl.scala 91:62] - error_stall_in <= _T_2 @[el2_ifu_aln_ctl.scala 91:18] - node _T_3 = not(error_stall) @[el2_ifu_aln_ctl.scala 93:39] - node i0_shift = and(io.dec_i0_decode_d, _T_3) @[el2_ifu_aln_ctl.scala 93:37] - io.ifu_pmu_instr_aligned <= i0_shift @[el2_ifu_aln_ctl.scala 95:28] - node _T_4 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 97:34] - node _T_5 = bits(_T_4, 0, 0) @[el2_ifu_aln_ctl.scala 97:38] - node _T_6 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 97:64] - node _T_7 = not(_T_6) @[el2_ifu_aln_ctl.scala 97:58] - node _T_8 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 97:75] - node _T_9 = and(_T_7, _T_8) @[el2_ifu_aln_ctl.scala 97:68] - node _T_10 = bits(_T_9, 0, 0) @[el2_ifu_aln_ctl.scala 97:80] - node _T_11 = cat(q1final, q0final) @[Cat.scala 29:58] - node _T_12 = mux(_T_5, q0final, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_13 = mux(_T_10, _T_11, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_14 = or(_T_12, _T_13) @[Mux.scala 27:72] - wire aligndata : UInt<32> @[Mux.scala 27:72] - aligndata <= _T_14 @[Mux.scala 27:72] - inst decompressed of el2_ifu_compress_ctl @[el2_ifu_aln_ctl.scala 99:28] - decompressed.clock <= clock - decompressed.reset <= reset - decompressed.io.din <= aligndata @[el2_ifu_aln_ctl.scala 101:23] - io.ifu_i0_instr <= decompressed.io.dout @[el2_ifu_aln_ctl.scala 103:20] - node _T_15 = bits(aligndata, 15, 0) @[el2_ifu_aln_ctl.scala 106:31] - io.ifu_i0_cinst <= _T_15 @[el2_ifu_aln_ctl.scala 106:19] - wire first4B : UInt<1> - first4B <= UInt<1>("h00") - node first2B = not(first4B) @[el2_ifu_aln_ctl.scala 111:17] - node _T_16 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 112:34] - node _T_17 = bits(_T_16, 0, 0) @[el2_ifu_aln_ctl.scala 112:38] - node _T_18 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 112:63] - node _T_19 = not(_T_18) @[el2_ifu_aln_ctl.scala 112:57] - node _T_20 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 112:74] - node _T_21 = and(_T_19, _T_20) @[el2_ifu_aln_ctl.scala 112:67] - node _T_22 = bits(_T_21, 0, 0) @[el2_ifu_aln_ctl.scala 112:79] - node _T_23 = cat(f1icaf, f0icaf) @[Cat.scala 29:58] - node _T_24 = mux(_T_17, f0icaf, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_25 = mux(_T_22, _T_23, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_26 = or(_T_24, _T_25) @[Mux.scala 27:72] - wire alignicaf : UInt<2> @[Mux.scala 27:72] - alignicaf <= _T_26 @[Mux.scala 27:72] - node _T_27 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 114:39] - node _T_28 = orr(alignicaf) @[el2_ifu_aln_ctl.scala 114:59] - node _T_29 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 114:72] - node _T_30 = bits(alignicaf, 0, 0) @[el2_ifu_aln_ctl.scala 114:91] - node _T_31 = mux(_T_27, _T_28, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_32 = mux(_T_29, _T_30, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_33 = or(_T_31, _T_32) @[Mux.scala 27:72] - wire _T_34 : UInt<1> @[Mux.scala 27:72] - _T_34 <= _T_33 @[Mux.scala 27:72] - io.ifu_i0_icaf <= _T_34 @[el2_ifu_aln_ctl.scala 114:18] - node _T_35 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 115:40] - node _T_36 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 115:58] - node _T_37 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 115:71] - node _T_38 = bits(alignval, 0, 0) @[el2_ifu_aln_ctl.scala 115:89] - node _T_39 = mux(_T_35, _T_36, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_40 = mux(_T_37, _T_38, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_41 = or(_T_39, _T_40) @[Mux.scala 27:72] - wire _T_42 : UInt<1> @[Mux.scala 27:72] - _T_42 <= _T_41 @[Mux.scala 27:72] - io.ifu_i0_valid <= _T_42 @[el2_ifu_aln_ctl.scala 115:19] - io.ifu_i0_pc4 <= first4B @[el2_ifu_aln_ctl.scala 116:17] - node shift_2B = and(i0_shift, first2B) @[el2_ifu_aln_ctl.scala 118:27] - node shift_4B = and(i0_shift, first4B) @[el2_ifu_aln_ctl.scala 119:27] - node _T_43 = bits(shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 120:40] - node _T_44 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 120:55] - node _T_45 = bits(shift_4B, 0, 0) @[el2_ifu_aln_ctl.scala 120:69] - node _T_46 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 120:86] - node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 120:80] - node _T_48 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 120:97] - node _T_49 = and(_T_47, _T_48) @[el2_ifu_aln_ctl.scala 120:90] - node _T_50 = mux(_T_43, _T_44, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_51 = mux(_T_45, _T_49, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_52 = or(_T_50, _T_51) @[Mux.scala 27:72] - wire f0_shift_2B : UInt<1> @[Mux.scala 27:72] - f0_shift_2B <= _T_52 @[Mux.scala 27:72] - node _T_53 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 121:27] - node _T_54 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 121:39] - node _T_55 = eq(_T_54, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 121:33] - node _T_56 = and(_T_53, _T_55) @[el2_ifu_aln_ctl.scala 121:31] - node f1_shift_2B = and(_T_56, shift_4B) @[el2_ifu_aln_ctl.scala 121:43] - reg wrptr : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 123:48] - wrptr <= wrptr_in @[el2_ifu_aln_ctl.scala 123:48] - reg rdptr : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 124:48] - rdptr <= wrptr_in @[el2_ifu_aln_ctl.scala 124:48] - reg f2val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 126:48] - f2val <= f2val_in @[el2_ifu_aln_ctl.scala 126:48] - reg f1val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 127:48] - f1val <= f1val_in @[el2_ifu_aln_ctl.scala 127:48] - reg q2off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 130:48] - q2off <= q2off_in @[el2_ifu_aln_ctl.scala 130:48] - reg q1off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 131:48] - q1off <= q1off_in @[el2_ifu_aln_ctl.scala 131:48] - reg q0off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 132:48] - q0off <= q0off_in @[el2_ifu_aln_ctl.scala 132:48] - node _T_57 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 134:29] - node _T_58 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 134:42] - node _T_59 = and(_T_57, _T_58) @[el2_ifu_aln_ctl.scala 134:40] - node _T_60 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 134:55] - node _T_61 = and(_T_59, _T_60) @[el2_ifu_aln_ctl.scala 134:53] - node fetch_to_f0 = and(_T_61, ifvalid) @[el2_ifu_aln_ctl.scala 134:65] - node _T_62 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 135:29] - node _T_63 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 135:42] - node _T_64 = and(_T_62, _T_63) @[el2_ifu_aln_ctl.scala 135:40] - node _T_65 = and(_T_64, f2_valid) @[el2_ifu_aln_ctl.scala 135:53] - node _T_66 = and(_T_65, ifvalid) @[el2_ifu_aln_ctl.scala 135:65] - node _T_67 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 136:29] - node _T_68 = and(_T_67, sf1_valid) @[el2_ifu_aln_ctl.scala 136:40] - node _T_69 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 136:55] - node _T_70 = and(_T_68, _T_69) @[el2_ifu_aln_ctl.scala 136:53] - node _T_71 = and(_T_70, ifvalid) @[el2_ifu_aln_ctl.scala 136:65] - node _T_72 = or(_T_66, _T_71) @[el2_ifu_aln_ctl.scala 135:77] - node _T_73 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 137:42] - node _T_74 = and(sf0_valid, _T_73) @[el2_ifu_aln_ctl.scala 137:40] - node _T_75 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 137:55] - node _T_76 = and(_T_74, _T_75) @[el2_ifu_aln_ctl.scala 137:53] - node _T_77 = and(_T_76, ifvalid) @[el2_ifu_aln_ctl.scala 137:65] - node fetch_to_f1 = or(_T_72, _T_77) @[el2_ifu_aln_ctl.scala 136:77] - node _T_78 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 139:29] - node _T_79 = and(_T_78, sf1_valid) @[el2_ifu_aln_ctl.scala 139:40] - node _T_80 = and(_T_79, f2_valid) @[el2_ifu_aln_ctl.scala 139:53] - node _T_81 = and(_T_80, ifvalid) @[el2_ifu_aln_ctl.scala 139:65] - node _T_82 = and(sf0_valid, sf1_valid) @[el2_ifu_aln_ctl.scala 140:40] - node _T_83 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 140:55] - node _T_84 = and(_T_82, _T_83) @[el2_ifu_aln_ctl.scala 140:53] - node _T_85 = and(_T_84, ifvalid) @[el2_ifu_aln_ctl.scala 140:65] - node f2_wr_en = or(_T_81, _T_85) @[el2_ifu_aln_ctl.scala 139:77] - node _T_86 = or(fetch_to_f1, shift_f2_f1) @[el2_ifu_aln_ctl.scala 143:36] - node f1_shift_wr_en = or(_T_86, f1_shift_2B) @[el2_ifu_aln_ctl.scala 143:50] - node _T_87 = or(fetch_to_f0, shift_f2_f0) @[el2_ifu_aln_ctl.scala 144:36] - node _T_88 = or(_T_87, shift_f1_f0) @[el2_ifu_aln_ctl.scala 144:50] - node _T_89 = or(_T_88, shift_2B) @[el2_ifu_aln_ctl.scala 144:64] - node f0_shift_wr_en = or(_T_89, shift_4B) @[el2_ifu_aln_ctl.scala 144:75] - node _T_90 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 146:24] - node _T_91 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 146:39] - node _T_92 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 146:54] - node _T_93 = cat(_T_90, _T_91) @[Cat.scala 29:58] - node qren = cat(_T_93, _T_92) @[Cat.scala 29:58] - node _T_94 = eq(wrptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 147:24] - node _T_95 = and(_T_94, ifvalid) @[el2_ifu_aln_ctl.scala 147:32] - node _T_96 = eq(wrptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 147:49] - node _T_97 = and(_T_96, ifvalid) @[el2_ifu_aln_ctl.scala 147:57] - node _T_98 = eq(wrptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 147:74] - node _T_99 = and(_T_98, ifvalid) @[el2_ifu_aln_ctl.scala 147:82] - node _T_100 = cat(_T_95, _T_97) @[Cat.scala 29:58] - node qwen = cat(_T_100, _T_99) @[Cat.scala 29:58] - node _T_101 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 149:30] - node _T_102 = and(_T_101, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 149:34] - node _T_103 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 149:57] - node _T_104 = and(_T_102, _T_103) @[el2_ifu_aln_ctl.scala 149:55] - node _T_105 = bits(_T_104, 0, 0) @[el2_ifu_aln_ctl.scala 149:78] - node _T_106 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 150:30] - node _T_107 = and(_T_106, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 150:34] - node _T_108 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 150:57] - node _T_109 = and(_T_107, _T_108) @[el2_ifu_aln_ctl.scala 150:55] - node _T_110 = bits(_T_109, 0, 0) @[el2_ifu_aln_ctl.scala 150:78] - node _T_111 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 151:30] - node _T_112 = and(_T_111, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 151:34] - node _T_113 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 151:57] - node _T_114 = and(_T_112, _T_113) @[el2_ifu_aln_ctl.scala 151:55] - node _T_115 = bits(_T_114, 0, 0) @[el2_ifu_aln_ctl.scala 151:78] - node _T_116 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 152:30] - node _T_117 = and(_T_116, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 152:34] - node _T_118 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 152:57] - node _T_119 = and(_T_117, _T_118) @[el2_ifu_aln_ctl.scala 152:55] - node _T_120 = bits(_T_119, 0, 0) @[el2_ifu_aln_ctl.scala 152:78] - node _T_121 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 153:30] - node _T_122 = and(_T_121, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 153:34] - node _T_123 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 153:57] - node _T_124 = and(_T_122, _T_123) @[el2_ifu_aln_ctl.scala 153:55] - node _T_125 = bits(_T_124, 0, 0) @[el2_ifu_aln_ctl.scala 153:78] - node _T_126 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 154:30] - node _T_127 = and(_T_126, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 154:34] - node _T_128 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 154:57] - node _T_129 = and(_T_127, _T_128) @[el2_ifu_aln_ctl.scala 154:55] - node _T_130 = bits(_T_129, 0, 0) @[el2_ifu_aln_ctl.scala 154:78] - node _T_131 = eq(io.ifu_fb_consume1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 155:26] - node _T_132 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 155:48] - node _T_133 = and(_T_131, _T_132) @[el2_ifu_aln_ctl.scala 155:46] - node _T_134 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 155:70] - node _T_135 = and(_T_133, _T_134) @[el2_ifu_aln_ctl.scala 155:68] - node _T_136 = bits(_T_135, 0, 0) @[el2_ifu_aln_ctl.scala 155:91] - node _T_137 = mux(_T_105, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_138 = mux(_T_110, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_139 = mux(_T_115, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_140 = mux(_T_120, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_141 = mux(_T_125, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_142 = mux(_T_130, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_143 = mux(_T_136, rdptr, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_144 = or(_T_137, _T_138) @[Mux.scala 27:72] - node _T_145 = or(_T_144, _T_139) @[Mux.scala 27:72] - node _T_146 = or(_T_145, _T_140) @[Mux.scala 27:72] - node _T_147 = or(_T_146, _T_141) @[Mux.scala 27:72] - node _T_148 = or(_T_147, _T_142) @[Mux.scala 27:72] - node _T_149 = or(_T_148, _T_143) @[Mux.scala 27:72] - wire _T_150 : UInt @[Mux.scala 27:72] - _T_150 <= _T_149 @[Mux.scala 27:72] - rdptr_in <= _T_150 @[el2_ifu_aln_ctl.scala 149:12] - node _T_151 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 157:30] - node _T_152 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 157:36] - node _T_153 = and(_T_151, _T_152) @[el2_ifu_aln_ctl.scala 157:34] - node _T_154 = bits(_T_153, 0, 0) @[el2_ifu_aln_ctl.scala 157:57] - node _T_155 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 158:30] - node _T_156 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 158:36] - node _T_157 = and(_T_155, _T_156) @[el2_ifu_aln_ctl.scala 158:34] - node _T_158 = bits(_T_157, 0, 0) @[el2_ifu_aln_ctl.scala 158:57] - node _T_159 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 159:30] - node _T_160 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 159:36] - node _T_161 = and(_T_159, _T_160) @[el2_ifu_aln_ctl.scala 159:34] - node _T_162 = bits(_T_161, 0, 0) @[el2_ifu_aln_ctl.scala 159:57] - node _T_163 = eq(ifvalid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 160:26] - node _T_164 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 160:37] - node _T_165 = and(_T_163, _T_164) @[el2_ifu_aln_ctl.scala 160:35] - node _T_166 = bits(_T_165, 0, 0) @[el2_ifu_aln_ctl.scala 160:58] - node _T_167 = mux(_T_154, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_168 = mux(_T_158, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_169 = mux(_T_162, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_170 = mux(_T_166, wrptr, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_171 = or(_T_167, _T_168) @[Mux.scala 27:72] - node _T_172 = or(_T_171, _T_169) @[Mux.scala 27:72] - node _T_173 = or(_T_172, _T_170) @[Mux.scala 27:72] - wire _T_174 : UInt @[Mux.scala 27:72] - _T_174 <= _T_173 @[Mux.scala 27:72] - wrptr_in <= _T_174 @[el2_ifu_aln_ctl.scala 157:12] - node _T_175 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 162:31] - node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 162:26] - node _T_177 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 162:43] - node _T_178 = and(_T_176, _T_177) @[el2_ifu_aln_ctl.scala 162:35] - node _T_179 = bits(_T_178, 0, 0) @[el2_ifu_aln_ctl.scala 162:52] - node _T_180 = or(q2off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 162:74] - node _T_181 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 163:31] - node _T_182 = eq(_T_181, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 163:26] - node _T_183 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 163:43] - node _T_184 = and(_T_182, _T_183) @[el2_ifu_aln_ctl.scala 163:35] - node _T_185 = bits(_T_184, 0, 0) @[el2_ifu_aln_ctl.scala 163:52] - node _T_186 = or(q2off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 163:74] - node _T_187 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 164:31] - node _T_188 = eq(_T_187, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 164:26] - node _T_189 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 164:43] - node _T_190 = and(_T_188, _T_189) @[el2_ifu_aln_ctl.scala 164:35] - node _T_191 = bits(_T_190, 0, 0) @[el2_ifu_aln_ctl.scala 164:52] - node _T_192 = mux(_T_179, _T_180, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_193 = mux(_T_185, _T_186, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_194 = mux(_T_191, q2off, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_195 = or(_T_192, _T_193) @[Mux.scala 27:72] - node _T_196 = or(_T_195, _T_194) @[Mux.scala 27:72] - wire _T_197 : UInt @[Mux.scala 27:72] - _T_197 <= _T_196 @[Mux.scala 27:72] - q2off_in <= _T_197 @[el2_ifu_aln_ctl.scala 162:12] - node _T_198 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 166:31] - node _T_199 = eq(_T_198, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 166:26] - node _T_200 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 166:43] - node _T_201 = and(_T_199, _T_200) @[el2_ifu_aln_ctl.scala 166:35] - node _T_202 = bits(_T_201, 0, 0) @[el2_ifu_aln_ctl.scala 166:52] - node _T_203 = or(q1off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 166:74] - node _T_204 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 167:31] - node _T_205 = eq(_T_204, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 167:26] - node _T_206 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 167:43] - node _T_207 = and(_T_205, _T_206) @[el2_ifu_aln_ctl.scala 167:35] - node _T_208 = bits(_T_207, 0, 0) @[el2_ifu_aln_ctl.scala 167:52] - node _T_209 = or(q1off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 167:74] - node _T_210 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 168:31] - node _T_211 = eq(_T_210, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 168:26] - node _T_212 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 168:43] - node _T_213 = and(_T_211, _T_212) @[el2_ifu_aln_ctl.scala 168:35] - node _T_214 = bits(_T_213, 0, 0) @[el2_ifu_aln_ctl.scala 168:52] - node _T_215 = mux(_T_202, _T_203, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_216 = mux(_T_208, _T_209, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_217 = mux(_T_214, q1off, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_218 = or(_T_215, _T_216) @[Mux.scala 27:72] - node _T_219 = or(_T_218, _T_217) @[Mux.scala 27:72] - wire _T_220 : UInt @[Mux.scala 27:72] - _T_220 <= _T_219 @[Mux.scala 27:72] - q1off_in <= _T_220 @[el2_ifu_aln_ctl.scala 166:12] - node _T_221 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 170:31] - node _T_222 = eq(_T_221, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 170:26] - node _T_223 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 170:43] - node _T_224 = and(_T_222, _T_223) @[el2_ifu_aln_ctl.scala 170:35] - node _T_225 = bits(_T_224, 0, 0) @[el2_ifu_aln_ctl.scala 170:52] - node _T_226 = or(q0off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 170:76] - node _T_227 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 171:31] - node _T_228 = eq(_T_227, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 171:26] - node _T_229 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 171:43] - node _T_230 = and(_T_228, _T_229) @[el2_ifu_aln_ctl.scala 171:35] - node _T_231 = bits(_T_230, 0, 0) @[el2_ifu_aln_ctl.scala 171:52] - node _T_232 = or(q0off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 171:76] - node _T_233 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 172:31] - node _T_234 = eq(_T_233, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 172:26] - node _T_235 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 172:43] - node _T_236 = and(_T_234, _T_235) @[el2_ifu_aln_ctl.scala 172:35] - node _T_237 = bits(_T_236, 0, 0) @[el2_ifu_aln_ctl.scala 172:52] - node _T_238 = mux(_T_225, _T_226, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_239 = mux(_T_231, _T_232, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_240 = mux(_T_237, q0off, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_241 = or(_T_238, _T_239) @[Mux.scala 27:72] - node _T_242 = or(_T_241, _T_240) @[Mux.scala 27:72] - wire _T_243 : UInt @[Mux.scala 27:72] - _T_243 <= _T_242 @[Mux.scala 27:72] - q0off_in <= _T_243 @[el2_ifu_aln_ctl.scala 170:12] - node _T_244 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 174:31] - node _T_245 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 175:31] - node _T_246 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 176:31] - node _T_247 = mux(_T_244, q0off, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_248 = mux(_T_245, q1off, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_249 = mux(_T_246, q2off, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_250 = or(_T_247, _T_248) @[Mux.scala 27:72] - node _T_251 = or(_T_250, _T_249) @[Mux.scala 27:72] - wire q0ptr : UInt @[Mux.scala 27:72] - q0ptr <= _T_251 @[Mux.scala 27:72] - node _T_252 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 178:32] - node _T_253 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 178:57] - node _T_254 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 178:83] - node _T_255 = mux(_T_252, q1off, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_256 = mux(_T_253, q2off, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_257 = mux(_T_254, q0off, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_258 = or(_T_255, _T_256) @[Mux.scala 27:72] - node _T_259 = or(_T_258, _T_257) @[Mux.scala 27:72] - wire q1ptr : UInt @[Mux.scala 27:72] - q1ptr <= _T_259 @[Mux.scala 27:72] - node _T_260 = eq(q0ptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 180:26] - node q0sel = cat(q0ptr, _T_260) @[Cat.scala 29:58] - node _T_261 = eq(q1ptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 182:26] - node q1sel = cat(q1ptr, _T_261) @[Cat.scala 29:58] - node _T_262 = bits(io.ifu_bp_btb_target_f, 31, 1) @[el2_ifu_aln_ctl.scala 185:48] - node _T_263 = cat(_T_262, io.ifu_bp_poffset_f) @[Cat.scala 29:58] - node _T_264 = cat(_T_263, io.ifu_bp_fghr_f) @[Cat.scala 29:58] - node _T_265 = cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f) @[Cat.scala 29:58] - node _T_266 = cat(_T_265, io.ic_access_fault_type_f) @[Cat.scala 29:58] - node misc_data_in = cat(_T_266, _T_264) @[Cat.scala 29:58] - node _T_267 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 187:31] - node _T_268 = bits(_T_267, 0, 0) @[el2_ifu_aln_ctl.scala 187:41] - node _T_269 = cat(misc1, misc0) @[Cat.scala 29:58] - node _T_270 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 188:27] - node _T_271 = bits(_T_270, 0, 0) @[el2_ifu_aln_ctl.scala 188:37] - node _T_272 = cat(misc2, misc1) @[Cat.scala 29:58] - node _T_273 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 189:27] - node _T_274 = bits(_T_273, 0, 0) @[el2_ifu_aln_ctl.scala 189:37] - node _T_275 = cat(misc0, misc2) @[Cat.scala 29:58] - node _T_276 = mux(_T_268, _T_269, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_277 = mux(_T_271, _T_272, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_278 = mux(_T_274, _T_275, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_279 = or(_T_276, _T_277) @[Mux.scala 27:72] - node _T_280 = or(_T_279, _T_278) @[Mux.scala 27:72] - wire misceff : UInt<108> @[Mux.scala 27:72] - misceff <= _T_280 @[Mux.scala 27:72] - node misc1eff = bits(misceff, 107, 55) @[el2_ifu_aln_ctl.scala 191:25] - node misc0eff = bits(misceff, 54, 0) @[el2_ifu_aln_ctl.scala 192:25] - node f1dbecc = bits(misc1eff, 52, 52) @[el2_ifu_aln_ctl.scala 194:25] - node _T_281 = bits(misc1eff, 51, 51) @[el2_ifu_aln_ctl.scala 195:21] - f1icaf <= _T_281 @[el2_ifu_aln_ctl.scala 195:10] - node f1ictype = bits(misc1eff, 50, 49) @[el2_ifu_aln_ctl.scala 196:26] - node f1prett = bits(misc1eff, 48, 18) @[el2_ifu_aln_ctl.scala 197:25] - node f1poffset = bits(misc1eff, 19, 8) @[el2_ifu_aln_ctl.scala 198:27] - node f1fghr = bits(misc1eff, 7, 0) @[el2_ifu_aln_ctl.scala 199:24] - node f0dbecc = bits(misc0eff, 54, 54) @[el2_ifu_aln_ctl.scala 201:25] - node _T_282 = bits(misc0eff, 53, 53) @[el2_ifu_aln_ctl.scala 202:21] - f0icaf <= _T_282 @[el2_ifu_aln_ctl.scala 202:10] - node f0ictype = bits(misc0eff, 52, 51) @[el2_ifu_aln_ctl.scala 203:26] - node f0prett = bits(misc0eff, 50, 20) @[el2_ifu_aln_ctl.scala 204:25] - node f0poffset = bits(misc0eff, 19, 8) @[el2_ifu_aln_ctl.scala 205:27] - node f0fghr = bits(misc0eff, 7, 0) @[el2_ifu_aln_ctl.scala 206:24] - node _T_283 = bits(io.ifu_bp_hist1_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:40] - node _T_284 = bits(io.ifu_bp_hist0_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:61] - node _T_285 = bits(io.ifu_bp_pc4_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:80] - node _T_286 = bits(io.ifu_bp_way_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:99] - node _T_287 = bits(io.ifu_bp_valid_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:120] - node _T_288 = bits(io.ifu_bp_ret_f, 1, 1) @[el2_ifu_aln_ctl.scala 209:20] - node _T_289 = bits(io.ifu_bp_hist1_f, 0, 0) @[el2_ifu_aln_ctl.scala 209:42] - node _T_290 = bits(io.ifu_bp_hist0_f, 0, 0) @[el2_ifu_aln_ctl.scala 209:63] - node _T_291 = bits(io.ifu_bp_pc4_f, 0, 0) @[el2_ifu_aln_ctl.scala 209:82] - node _T_292 = bits(io.ifu_bp_way_f, 0, 0) @[el2_ifu_aln_ctl.scala 209:101] - node _T_293 = bits(io.ifu_bp_valid_f, 0, 0) @[el2_ifu_aln_ctl.scala 210:22] - node _T_294 = bits(io.ifu_bp_ret_f, 0, 0) @[el2_ifu_aln_ctl.scala 210:41] - node _T_295 = cat(_T_292, _T_293) @[Cat.scala 29:58] - node _T_296 = cat(_T_295, _T_294) @[Cat.scala 29:58] - node _T_297 = cat(_T_289, _T_290) @[Cat.scala 29:58] - node _T_298 = cat(_T_297, _T_291) @[Cat.scala 29:58] - node _T_299 = cat(_T_298, _T_296) @[Cat.scala 29:58] - node _T_300 = cat(_T_286, _T_287) @[Cat.scala 29:58] - node _T_301 = cat(_T_300, _T_288) @[Cat.scala 29:58] - node _T_302 = cat(_T_283, _T_284) @[Cat.scala 29:58] - node _T_303 = cat(_T_302, _T_285) @[Cat.scala 29:58] - node _T_304 = cat(_T_303, _T_301) @[Cat.scala 29:58] - node brdata_in = cat(_T_304, _T_299) @[Cat.scala 29:58] - node _T_305 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 212:33] - node _T_306 = bits(_T_305, 0, 0) @[el2_ifu_aln_ctl.scala 212:37] - node _T_307 = cat(brdata1, brdata0) @[Cat.scala 29:58] - node _T_308 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 213:33] - node _T_309 = bits(_T_308, 0, 0) @[el2_ifu_aln_ctl.scala 213:37] - node _T_310 = cat(brdata2, brdata1) @[Cat.scala 29:58] - node _T_311 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 214:33] - node _T_312 = bits(_T_311, 0, 0) @[el2_ifu_aln_ctl.scala 214:37] - node _T_313 = cat(brdata0, brdata2) @[Cat.scala 29:58] - node _T_314 = mux(_T_306, _T_307, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_315 = mux(_T_309, _T_310, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_316 = mux(_T_312, _T_313, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_317 = or(_T_314, _T_315) @[Mux.scala 27:72] - node _T_318 = or(_T_317, _T_316) @[Mux.scala 27:72] - wire brdataeff : UInt<24> @[Mux.scala 27:72] - brdataeff <= _T_318 @[Mux.scala 27:72] - node brdata0eff = bits(brdataeff, 11, 0) @[el2_ifu_aln_ctl.scala 216:43] - node brdata1eff = bits(brdataeff, 23, 12) @[el2_ifu_aln_ctl.scala 216:61] wire q0 : UInt<32> q0 <= UInt<1>("h00") wire q1 : UInt<32> q1 <= UInt<1>("h00") wire q2 : UInt<32> q2 <= UInt<1>("h00") - node _T_319 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 222:28] - node _T_320 = bits(_T_319, 0, 0) @[el2_ifu_aln_ctl.scala 222:32] - node _T_321 = cat(q1, q0) @[Cat.scala 29:58] - node _T_322 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 223:27] - node _T_323 = bits(_T_322, 0, 0) @[el2_ifu_aln_ctl.scala 223:31] - node _T_324 = cat(q2, q1) @[Cat.scala 29:58] - node _T_325 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 224:27] - node _T_326 = bits(_T_325, 0, 0) @[el2_ifu_aln_ctl.scala 224:31] - node _T_327 = cat(q0, q2) @[Cat.scala 29:58] - node _T_328 = mux(_T_320, _T_321, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_329 = mux(_T_323, _T_324, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_330 = mux(_T_326, _T_327, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_331 = or(_T_328, _T_329) @[Mux.scala 27:72] - node _T_332 = or(_T_331, _T_330) @[Mux.scala 27:72] - wire qeff : UInt<64> @[Mux.scala 27:72] - qeff <= _T_332 @[Mux.scala 27:72] - node q1eff = bits(qeff, 63, 32) @[el2_ifu_aln_ctl.scala 225:29] - node q0eff = bits(qeff, 31, 0) @[el2_ifu_aln_ctl.scala 225:42] - node _T_333 = bits(q0sel, 0, 0) @[el2_ifu_aln_ctl.scala 226:37] - node _T_334 = bits(_T_333, 0, 0) @[el2_ifu_aln_ctl.scala 226:41] - node _T_335 = bits(q0sel, 1, 1) @[el2_ifu_aln_ctl.scala 226:68] - node _T_336 = bits(_T_335, 0, 0) @[el2_ifu_aln_ctl.scala 226:72] - node _T_337 = bits(brdata0eff, 11, 6) @[el2_ifu_aln_ctl.scala 226:92] - node _T_338 = mux(_T_334, brdata0eff, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_339 = mux(_T_336, _T_337, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_340 = or(_T_338, _T_339) @[Mux.scala 27:72] + wire f1pc_in : UInt<31> + f1pc_in <= UInt<1>("h00") + wire f0pc_in : UInt<31> + f0pc_in <= UInt<1>("h00") + wire error_stall : UInt<1> + error_stall <= UInt<1>("h00") + wire f2_wr_en : UInt<1> + f2_wr_en <= UInt<1>("h00") + wire shift_4B : UInt<1> + shift_4B <= UInt<1>("h00") + wire f1_shift_wr_en : UInt<1> + f1_shift_wr_en <= UInt<1>("h00") + wire f0_shift_wr_en : UInt<1> + f0_shift_wr_en <= UInt<1>("h00") + wire qwen : UInt<3> + qwen <= UInt<1>("h00") + wire brdata_in : UInt<12> + brdata_in <= UInt<1>("h00") + wire misc_data_in : UInt<55> + misc_data_in <= UInt<1>("h00") + wire fetch_to_f0 : UInt<1> + fetch_to_f0 <= UInt<1>("h00") + wire fetch_to_f1 : UInt<1> + fetch_to_f1 <= UInt<1>("h00") + wire fetch_to_f2 : UInt<1> + fetch_to_f2 <= UInt<1>("h00") + wire f1_shift_2B : UInt<1> + f1_shift_2B <= UInt<1>("h00") + wire first4B : UInt<1> + first4B <= UInt<1>("h00") + wire shift_2B : UInt<1> + shift_2B <= UInt<1>("h00") + wire f0_shift_2B : UInt<1> + f0_shift_2B <= UInt<1>("h00") + node _T = or(error_stall, io.ifu_async_error_start) @[el2_ifu_aln_ctl.scala 110:34] + node _T_1 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 110:64] + node _T_2 = and(_T, _T_1) @[el2_ifu_aln_ctl.scala 110:62] + error_stall_in <= _T_2 @[el2_ifu_aln_ctl.scala 110:18] + reg _T_3 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 112:51] + _T_3 <= error_stall_in @[el2_ifu_aln_ctl.scala 112:51] + error_stall <= _T_3 @[el2_ifu_aln_ctl.scala 112:15] + reg wrptr : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 113:48] + wrptr <= wrptr_in @[el2_ifu_aln_ctl.scala 113:48] + reg rdptr : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 114:48] + rdptr <= rdptr_in @[el2_ifu_aln_ctl.scala 114:48] + reg f2val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 116:48] + f2val <= f2val_in @[el2_ifu_aln_ctl.scala 116:48] + reg f1val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 117:48] + f1val <= f1val_in @[el2_ifu_aln_ctl.scala 117:48] + reg f0val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 118:48] + f0val <= f0val_in @[el2_ifu_aln_ctl.scala 118:48] + reg q2off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 120:48] + q2off <= q2off_in @[el2_ifu_aln_ctl.scala 120:48] + reg q1off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 121:48] + q1off <= q1off_in @[el2_ifu_aln_ctl.scala 121:48] + reg q0off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 122:48] + q0off <= q0off_in @[el2_ifu_aln_ctl.scala 122:48] + node _T_4 = bits(f2_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 124:55] + reg f2pc : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4 : @[Reg.scala 28:19] + f2pc <= io.ifu_fetch_pc @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_5 = bits(f1_shift_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 125:53] + reg f1pc : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_5 : @[Reg.scala 28:19] + f1pc <= f1pc_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_6 = bits(f0_shift_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 126:53] + reg f0pc : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_6 : @[Reg.scala 28:19] + f0pc <= f0pc_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_7 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 128:44] + reg _T_8 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_7 : @[Reg.scala 28:19] + _T_8 <= brdata_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + brdata2 <= _T_8 @[el2_ifu_aln_ctl.scala 128:11] + node _T_9 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 129:44] + reg _T_10 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_9 : @[Reg.scala 28:19] + _T_10 <= brdata_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + brdata1 <= _T_10 @[el2_ifu_aln_ctl.scala 129:11] + node _T_11 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 130:44] + reg _T_12 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_11 : @[Reg.scala 28:19] + _T_12 <= brdata_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + brdata0 <= _T_12 @[el2_ifu_aln_ctl.scala 130:11] + node _T_13 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 132:45] + reg _T_14 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_13 : @[Reg.scala 28:19] + _T_14 <= misc_data_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + misc2 <= _T_14 @[el2_ifu_aln_ctl.scala 132:9] + node _T_15 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 133:45] + reg _T_16 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_15 : @[Reg.scala 28:19] + _T_16 <= misc_data_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + misc1 <= _T_16 @[el2_ifu_aln_ctl.scala 133:9] + node _T_17 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 134:45] + reg _T_18 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_17 : @[Reg.scala 28:19] + _T_18 <= misc_data_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + misc0 <= _T_18 @[el2_ifu_aln_ctl.scala 134:9] + node _T_19 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 136:49] + reg _T_20 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_19 : @[Reg.scala 28:19] + _T_20 <= io.ifu_fetch_data_f @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + q2 <= _T_20 @[el2_ifu_aln_ctl.scala 136:6] + node _T_21 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 137:49] + reg _T_22 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_21 : @[Reg.scala 28:19] + _T_22 <= io.ifu_fetch_data_f @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + q1 <= _T_22 @[el2_ifu_aln_ctl.scala 137:6] + node _T_23 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 138:49] + reg _T_24 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_23 : @[Reg.scala 28:19] + _T_24 <= io.ifu_fetch_data_f @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + q0 <= _T_24 @[el2_ifu_aln_ctl.scala 138:6] + f2_wr_en <= fetch_to_f2 @[el2_ifu_aln_ctl.scala 140:18] + node _T_25 = or(fetch_to_f1, shift_f2_f1) @[el2_ifu_aln_ctl.scala 141:33] + node _T_26 = or(_T_25, f1_shift_2B) @[el2_ifu_aln_ctl.scala 141:47] + f1_shift_wr_en <= _T_26 @[el2_ifu_aln_ctl.scala 141:18] + node _T_27 = or(fetch_to_f0, shift_f2_f0) @[el2_ifu_aln_ctl.scala 142:33] + node _T_28 = or(_T_27, shift_f1_f0) @[el2_ifu_aln_ctl.scala 142:47] + node _T_29 = or(_T_28, shift_2B) @[el2_ifu_aln_ctl.scala 142:61] + node _T_30 = or(_T_29, shift_4B) @[el2_ifu_aln_ctl.scala 142:72] + f0_shift_wr_en <= _T_30 @[el2_ifu_aln_ctl.scala 142:18] + node _T_31 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 144:24] + node _T_32 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 144:39] + node _T_33 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 144:54] + node _T_34 = cat(_T_31, _T_32) @[Cat.scala 29:58] + node qren = cat(_T_34, _T_33) @[Cat.scala 29:58] + node _T_35 = eq(wrptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 145:21] + node _T_36 = and(_T_35, ifvalid) @[el2_ifu_aln_ctl.scala 145:29] + node _T_37 = eq(wrptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 145:46] + node _T_38 = and(_T_37, ifvalid) @[el2_ifu_aln_ctl.scala 145:54] + node _T_39 = eq(wrptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 145:71] + node _T_40 = and(_T_39, ifvalid) @[el2_ifu_aln_ctl.scala 145:79] + node _T_41 = cat(_T_36, _T_38) @[Cat.scala 29:58] + node _T_42 = cat(_T_41, _T_40) @[Cat.scala 29:58] + qwen <= _T_42 @[el2_ifu_aln_ctl.scala 145:8] + node _T_43 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 147:30] + node _T_44 = and(_T_43, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 147:34] + node _T_45 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 147:57] + node _T_46 = and(_T_44, _T_45) @[el2_ifu_aln_ctl.scala 147:55] + node _T_47 = bits(_T_46, 0, 0) @[el2_ifu_aln_ctl.scala 147:78] + node _T_48 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 148:10] + node _T_49 = and(_T_48, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 148:14] + node _T_50 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 148:37] + node _T_51 = and(_T_49, _T_50) @[el2_ifu_aln_ctl.scala 148:35] + node _T_52 = bits(_T_51, 0, 0) @[el2_ifu_aln_ctl.scala 148:58] + node _T_53 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 149:10] + node _T_54 = and(_T_53, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 149:14] + node _T_55 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 149:37] + node _T_56 = and(_T_54, _T_55) @[el2_ifu_aln_ctl.scala 149:35] + node _T_57 = bits(_T_56, 0, 0) @[el2_ifu_aln_ctl.scala 149:58] + node _T_58 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 150:10] + node _T_59 = and(_T_58, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 150:14] + node _T_60 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 150:37] + node _T_61 = and(_T_59, _T_60) @[el2_ifu_aln_ctl.scala 150:35] + node _T_62 = bits(_T_61, 0, 0) @[el2_ifu_aln_ctl.scala 150:58] + node _T_63 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 151:10] + node _T_64 = and(_T_63, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 151:14] + node _T_65 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 151:37] + node _T_66 = and(_T_64, _T_65) @[el2_ifu_aln_ctl.scala 151:35] + node _T_67 = bits(_T_66, 0, 0) @[el2_ifu_aln_ctl.scala 151:58] + node _T_68 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 152:10] + node _T_69 = and(_T_68, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 152:14] + node _T_70 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 152:37] + node _T_71 = and(_T_69, _T_70) @[el2_ifu_aln_ctl.scala 152:35] + node _T_72 = bits(_T_71, 0, 0) @[el2_ifu_aln_ctl.scala 152:58] + node _T_73 = eq(io.ifu_fb_consume1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 153:6] + node _T_74 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 153:28] + node _T_75 = and(_T_73, _T_74) @[el2_ifu_aln_ctl.scala 153:26] + node _T_76 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 153:50] + node _T_77 = and(_T_75, _T_76) @[el2_ifu_aln_ctl.scala 153:48] + node _T_78 = bits(_T_77, 0, 0) @[el2_ifu_aln_ctl.scala 153:71] + node _T_79 = mux(_T_47, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_80 = mux(_T_52, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_81 = mux(_T_57, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_82 = mux(_T_62, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_83 = mux(_T_67, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_84 = mux(_T_72, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_85 = mux(_T_78, rdptr, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_86 = or(_T_79, _T_80) @[Mux.scala 27:72] + node _T_87 = or(_T_86, _T_81) @[Mux.scala 27:72] + node _T_88 = or(_T_87, _T_82) @[Mux.scala 27:72] + node _T_89 = or(_T_88, _T_83) @[Mux.scala 27:72] + node _T_90 = or(_T_89, _T_84) @[Mux.scala 27:72] + node _T_91 = or(_T_90, _T_85) @[Mux.scala 27:72] + wire _T_92 : UInt @[Mux.scala 27:72] + _T_92 <= _T_91 @[Mux.scala 27:72] + rdptr_in <= _T_92 @[el2_ifu_aln_ctl.scala 147:12] + node _T_93 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 155:30] + node _T_94 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 155:36] + node _T_95 = and(_T_93, _T_94) @[el2_ifu_aln_ctl.scala 155:34] + node _T_96 = bits(_T_95, 0, 0) @[el2_ifu_aln_ctl.scala 155:57] + node _T_97 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 156:10] + node _T_98 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 156:16] + node _T_99 = and(_T_97, _T_98) @[el2_ifu_aln_ctl.scala 156:14] + node _T_100 = bits(_T_99, 0, 0) @[el2_ifu_aln_ctl.scala 156:37] + node _T_101 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 157:10] + node _T_102 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 157:16] + node _T_103 = and(_T_101, _T_102) @[el2_ifu_aln_ctl.scala 157:14] + node _T_104 = bits(_T_103, 0, 0) @[el2_ifu_aln_ctl.scala 157:37] + node _T_105 = eq(ifvalid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 158:6] + node _T_106 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 158:17] + node _T_107 = and(_T_105, _T_106) @[el2_ifu_aln_ctl.scala 158:15] + node _T_108 = bits(_T_107, 0, 0) @[el2_ifu_aln_ctl.scala 158:38] + node _T_109 = mux(_T_96, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_110 = mux(_T_100, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_111 = mux(_T_104, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_112 = mux(_T_108, wrptr, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_113 = or(_T_109, _T_110) @[Mux.scala 27:72] + node _T_114 = or(_T_113, _T_111) @[Mux.scala 27:72] + node _T_115 = or(_T_114, _T_112) @[Mux.scala 27:72] + wire _T_116 : UInt @[Mux.scala 27:72] + _T_116 <= _T_115 @[Mux.scala 27:72] + wrptr_in <= _T_116 @[el2_ifu_aln_ctl.scala 155:12] + node _T_117 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 160:31] + node _T_118 = eq(_T_117, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 160:26] + node _T_119 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 160:43] + node _T_120 = and(_T_118, _T_119) @[el2_ifu_aln_ctl.scala 160:35] + node _T_121 = bits(_T_120, 0, 0) @[el2_ifu_aln_ctl.scala 160:52] + node _T_122 = or(q2off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 160:74] + node _T_123 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 161:11] + node _T_124 = eq(_T_123, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 161:6] + node _T_125 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 161:23] + node _T_126 = and(_T_124, _T_125) @[el2_ifu_aln_ctl.scala 161:15] + node _T_127 = bits(_T_126, 0, 0) @[el2_ifu_aln_ctl.scala 161:32] + node _T_128 = or(q2off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 161:54] + node _T_129 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 162:11] + node _T_130 = eq(_T_129, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 162:6] + node _T_131 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 162:23] + node _T_132 = and(_T_130, _T_131) @[el2_ifu_aln_ctl.scala 162:15] + node _T_133 = bits(_T_132, 0, 0) @[el2_ifu_aln_ctl.scala 162:32] + node _T_134 = mux(_T_121, _T_122, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_135 = mux(_T_127, _T_128, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_136 = mux(_T_133, q2off, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_137 = or(_T_134, _T_135) @[Mux.scala 27:72] + node _T_138 = or(_T_137, _T_136) @[Mux.scala 27:72] + wire _T_139 : UInt @[Mux.scala 27:72] + _T_139 <= _T_138 @[Mux.scala 27:72] + q2off_in <= _T_139 @[el2_ifu_aln_ctl.scala 160:12] + node _T_140 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 164:31] + node _T_141 = eq(_T_140, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 164:26] + node _T_142 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 164:43] + node _T_143 = and(_T_141, _T_142) @[el2_ifu_aln_ctl.scala 164:35] + node _T_144 = bits(_T_143, 0, 0) @[el2_ifu_aln_ctl.scala 164:52] + node _T_145 = or(q1off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 164:74] + node _T_146 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 165:11] + node _T_147 = eq(_T_146, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 165:6] + node _T_148 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 165:23] + node _T_149 = and(_T_147, _T_148) @[el2_ifu_aln_ctl.scala 165:15] + node _T_150 = bits(_T_149, 0, 0) @[el2_ifu_aln_ctl.scala 165:32] + node _T_151 = or(q1off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 165:54] + node _T_152 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 166:11] + node _T_153 = eq(_T_152, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 166:6] + node _T_154 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 166:23] + node _T_155 = and(_T_153, _T_154) @[el2_ifu_aln_ctl.scala 166:15] + node _T_156 = bits(_T_155, 0, 0) @[el2_ifu_aln_ctl.scala 166:32] + node _T_157 = mux(_T_144, _T_145, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_158 = mux(_T_150, _T_151, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_159 = mux(_T_156, q1off, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_160 = or(_T_157, _T_158) @[Mux.scala 27:72] + node _T_161 = or(_T_160, _T_159) @[Mux.scala 27:72] + wire _T_162 : UInt @[Mux.scala 27:72] + _T_162 <= _T_161 @[Mux.scala 27:72] + q1off_in <= _T_162 @[el2_ifu_aln_ctl.scala 164:12] + node _T_163 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 168:31] + node _T_164 = eq(_T_163, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 168:26] + node _T_165 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 168:43] + node _T_166 = and(_T_164, _T_165) @[el2_ifu_aln_ctl.scala 168:35] + node _T_167 = bits(_T_166, 0, 0) @[el2_ifu_aln_ctl.scala 168:52] + node _T_168 = or(q0off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 168:76] + node _T_169 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 169:11] + node _T_170 = eq(_T_169, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 169:6] + node _T_171 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 169:23] + node _T_172 = and(_T_170, _T_171) @[el2_ifu_aln_ctl.scala 169:15] + node _T_173 = bits(_T_172, 0, 0) @[el2_ifu_aln_ctl.scala 169:32] + node _T_174 = or(q0off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 169:56] + node _T_175 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 170:11] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 170:6] + node _T_177 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 170:23] + node _T_178 = and(_T_176, _T_177) @[el2_ifu_aln_ctl.scala 170:15] + node _T_179 = bits(_T_178, 0, 0) @[el2_ifu_aln_ctl.scala 170:32] + node _T_180 = mux(_T_167, _T_168, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_181 = mux(_T_173, _T_174, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_182 = mux(_T_179, q0off, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_183 = or(_T_180, _T_181) @[Mux.scala 27:72] + node _T_184 = or(_T_183, _T_182) @[Mux.scala 27:72] + wire _T_185 : UInt @[Mux.scala 27:72] + _T_185 <= _T_184 @[Mux.scala 27:72] + q0off_in <= _T_185 @[el2_ifu_aln_ctl.scala 168:12] + node _T_186 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 172:31] + node _T_187 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 173:11] + node _T_188 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 174:11] + node _T_189 = mux(_T_186, q0off, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_190 = mux(_T_187, q1off, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_191 = mux(_T_188, q2off, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_192 = or(_T_189, _T_190) @[Mux.scala 27:72] + node _T_193 = or(_T_192, _T_191) @[Mux.scala 27:72] + wire q0ptr : UInt @[Mux.scala 27:72] + q0ptr <= _T_193 @[Mux.scala 27:72] + node _T_194 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 176:32] + node _T_195 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 176:57] + node _T_196 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 176:83] + node _T_197 = mux(_T_194, q1off, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_198 = mux(_T_195, q2off, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_199 = mux(_T_196, q0off, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_200 = or(_T_197, _T_198) @[Mux.scala 27:72] + node _T_201 = or(_T_200, _T_199) @[Mux.scala 27:72] + wire q1ptr : UInt @[Mux.scala 27:72] + q1ptr <= _T_201 @[Mux.scala 27:72] + node _T_202 = eq(q0ptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 178:26] + node q0sel = cat(q0ptr, _T_202) @[Cat.scala 29:58] + node _T_203 = eq(q1ptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 180:26] + node q1sel = cat(q1ptr, _T_203) @[Cat.scala 29:58] + node _T_204 = bits(io.ifu_bp_btb_target_f, 31, 1) @[el2_ifu_aln_ctl.scala 183:27] + node _T_205 = cat(_T_204, io.ifu_bp_poffset_f) @[Cat.scala 29:58] + node _T_206 = cat(_T_205, io.ifu_bp_fghr_f) @[Cat.scala 29:58] + node _T_207 = cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f) @[Cat.scala 29:58] + node _T_208 = cat(_T_207, io.ic_access_fault_type_f) @[Cat.scala 29:58] + node _T_209 = cat(_T_208, _T_206) @[Cat.scala 29:58] + misc_data_in <= _T_209 @[el2_ifu_aln_ctl.scala 182:16] + node _T_210 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 185:31] + node _T_211 = bits(_T_210, 0, 0) @[el2_ifu_aln_ctl.scala 185:41] + node _T_212 = cat(misc1, misc0) @[Cat.scala 29:58] + node _T_213 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 186:9] + node _T_214 = bits(_T_213, 0, 0) @[el2_ifu_aln_ctl.scala 186:19] + node _T_215 = cat(misc2, misc1) @[Cat.scala 29:58] + node _T_216 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 187:9] + node _T_217 = bits(_T_216, 0, 0) @[el2_ifu_aln_ctl.scala 187:19] + node _T_218 = cat(misc0, misc2) @[Cat.scala 29:58] + node _T_219 = mux(_T_211, _T_212, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_220 = mux(_T_214, _T_215, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_221 = mux(_T_217, _T_218, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_222 = or(_T_219, _T_220) @[Mux.scala 27:72] + node _T_223 = or(_T_222, _T_221) @[Mux.scala 27:72] + wire misceff : UInt<108> @[Mux.scala 27:72] + misceff <= _T_223 @[Mux.scala 27:72] + node misc1eff = bits(misceff, 107, 55) @[el2_ifu_aln_ctl.scala 189:25] + node misc0eff = bits(misceff, 54, 0) @[el2_ifu_aln_ctl.scala 190:25] + node f1dbecc = bits(misc1eff, 52, 52) @[el2_ifu_aln_ctl.scala 193:25] + node _T_224 = bits(misc1eff, 51, 51) @[el2_ifu_aln_ctl.scala 194:21] + f1icaf <= _T_224 @[el2_ifu_aln_ctl.scala 194:10] + node f1ictype = bits(misc1eff, 50, 49) @[el2_ifu_aln_ctl.scala 195:26] + node f1prett = bits(misc1eff, 48, 18) @[el2_ifu_aln_ctl.scala 196:25] + node f1poffset = bits(misc1eff, 19, 8) @[el2_ifu_aln_ctl.scala 197:27] + node f1fghr = bits(misc1eff, 7, 0) @[el2_ifu_aln_ctl.scala 198:24] + node f0dbecc = bits(misc0eff, 54, 54) @[el2_ifu_aln_ctl.scala 200:25] + node _T_225 = bits(misc0eff, 53, 53) @[el2_ifu_aln_ctl.scala 201:21] + f0icaf <= _T_225 @[el2_ifu_aln_ctl.scala 201:10] + node f0ictype = bits(misc0eff, 52, 51) @[el2_ifu_aln_ctl.scala 202:26] + node f0prett = bits(misc0eff, 50, 20) @[el2_ifu_aln_ctl.scala 203:25] + node f0poffset = bits(misc0eff, 19, 8) @[el2_ifu_aln_ctl.scala 204:27] + node f0fghr = bits(misc0eff, 7, 0) @[el2_ifu_aln_ctl.scala 205:24] + node _T_226 = bits(io.ifu_bp_hist1_f, 1, 1) @[el2_ifu_aln_ctl.scala 207:37] + node _T_227 = bits(io.ifu_bp_hist0_f, 1, 1) @[el2_ifu_aln_ctl.scala 207:58] + node _T_228 = bits(io.ifu_bp_pc4_f, 1, 1) @[el2_ifu_aln_ctl.scala 207:77] + node _T_229 = bits(io.ifu_bp_way_f, 1, 1) @[el2_ifu_aln_ctl.scala 207:96] + node _T_230 = bits(io.ifu_bp_valid_f, 1, 1) @[el2_ifu_aln_ctl.scala 207:117] + node _T_231 = bits(io.ifu_bp_ret_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:20] + node _T_232 = bits(io.ifu_bp_hist1_f, 0, 0) @[el2_ifu_aln_ctl.scala 208:42] + node _T_233 = bits(io.ifu_bp_hist0_f, 0, 0) @[el2_ifu_aln_ctl.scala 208:63] + node _T_234 = bits(io.ifu_bp_pc4_f, 0, 0) @[el2_ifu_aln_ctl.scala 208:82] + node _T_235 = bits(io.ifu_bp_way_f, 0, 0) @[el2_ifu_aln_ctl.scala 208:101] + node _T_236 = bits(io.ifu_bp_valid_f, 0, 0) @[el2_ifu_aln_ctl.scala 209:22] + node _T_237 = bits(io.ifu_bp_ret_f, 0, 0) @[el2_ifu_aln_ctl.scala 209:41] + node _T_238 = cat(_T_235, _T_236) @[Cat.scala 29:58] + node _T_239 = cat(_T_238, _T_237) @[Cat.scala 29:58] + node _T_240 = cat(_T_232, _T_233) @[Cat.scala 29:58] + node _T_241 = cat(_T_240, _T_234) @[Cat.scala 29:58] + node _T_242 = cat(_T_241, _T_239) @[Cat.scala 29:58] + node _T_243 = cat(_T_229, _T_230) @[Cat.scala 29:58] + node _T_244 = cat(_T_243, _T_231) @[Cat.scala 29:58] + node _T_245 = cat(_T_226, _T_227) @[Cat.scala 29:58] + node _T_246 = cat(_T_245, _T_228) @[Cat.scala 29:58] + node _T_247 = cat(_T_246, _T_244) @[Cat.scala 29:58] + node _T_248 = cat(_T_247, _T_242) @[Cat.scala 29:58] + brdata_in <= _T_248 @[el2_ifu_aln_ctl.scala 207:13] + node _T_249 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 211:33] + node _T_250 = bits(_T_249, 0, 0) @[el2_ifu_aln_ctl.scala 211:37] + node _T_251 = cat(brdata1, brdata0) @[Cat.scala 29:58] + node _T_252 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 212:9] + node _T_253 = bits(_T_252, 0, 0) @[el2_ifu_aln_ctl.scala 212:13] + node _T_254 = cat(brdata2, brdata1) @[Cat.scala 29:58] + node _T_255 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 213:9] + node _T_256 = bits(_T_255, 0, 0) @[el2_ifu_aln_ctl.scala 213:13] + node _T_257 = cat(brdata0, brdata2) @[Cat.scala 29:58] + node _T_258 = mux(_T_250, _T_251, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_259 = mux(_T_253, _T_254, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_260 = mux(_T_256, _T_257, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_261 = or(_T_258, _T_259) @[Mux.scala 27:72] + node _T_262 = or(_T_261, _T_260) @[Mux.scala 27:72] + wire brdataeff : UInt<24> @[Mux.scala 27:72] + brdataeff <= _T_262 @[Mux.scala 27:72] + node brdata0eff = bits(brdataeff, 11, 0) @[el2_ifu_aln_ctl.scala 215:43] + node brdata1eff = bits(brdataeff, 23, 12) @[el2_ifu_aln_ctl.scala 215:61] + node _T_263 = bits(q0sel, 0, 0) @[el2_ifu_aln_ctl.scala 217:37] + node _T_264 = bits(_T_263, 0, 0) @[el2_ifu_aln_ctl.scala 217:41] + node _T_265 = bits(q0sel, 1, 1) @[el2_ifu_aln_ctl.scala 217:68] + node _T_266 = bits(_T_265, 0, 0) @[el2_ifu_aln_ctl.scala 217:72] + node _T_267 = bits(brdata0eff, 11, 6) @[el2_ifu_aln_ctl.scala 217:92] + node _T_268 = mux(_T_264, brdata0eff, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_269 = mux(_T_266, _T_267, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_270 = or(_T_268, _T_269) @[Mux.scala 27:72] wire brdata0final : UInt<12> @[Mux.scala 27:72] - brdata0final <= _T_340 @[Mux.scala 27:72] - node _T_341 = bits(q1sel, 0, 0) @[el2_ifu_aln_ctl.scala 228:37] - node _T_342 = bits(_T_341, 0, 0) @[el2_ifu_aln_ctl.scala 228:41] - node _T_343 = bits(q1sel, 1, 1) @[el2_ifu_aln_ctl.scala 228:68] - node _T_344 = bits(_T_343, 0, 0) @[el2_ifu_aln_ctl.scala 228:72] - node _T_345 = bits(brdata1eff, 11, 6) @[el2_ifu_aln_ctl.scala 228:92] - node _T_346 = mux(_T_342, brdata1eff, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_347 = mux(_T_344, _T_345, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_348 = or(_T_346, _T_347) @[Mux.scala 27:72] + brdata0final <= _T_270 @[Mux.scala 27:72] + node _T_271 = bits(q1sel, 0, 0) @[el2_ifu_aln_ctl.scala 218:37] + node _T_272 = bits(_T_271, 0, 0) @[el2_ifu_aln_ctl.scala 218:41] + node _T_273 = bits(q1sel, 1, 1) @[el2_ifu_aln_ctl.scala 218:68] + node _T_274 = bits(_T_273, 0, 0) @[el2_ifu_aln_ctl.scala 218:72] + node _T_275 = bits(brdata1eff, 11, 6) @[el2_ifu_aln_ctl.scala 218:92] + node _T_276 = mux(_T_272, brdata1eff, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_277 = mux(_T_274, _T_275, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_278 = or(_T_276, _T_277) @[Mux.scala 27:72] wire brdata1final : UInt<12> @[Mux.scala 27:72] - brdata1final <= _T_348 @[Mux.scala 27:72] - node _T_349 = bits(brdata0final, 6, 6) @[el2_ifu_aln_ctl.scala 230:31] - node _T_350 = bits(brdata0final, 0, 0) @[el2_ifu_aln_ctl.scala 230:47] - node f0ret = cat(_T_349, _T_350) @[Cat.scala 29:58] - node _T_351 = bits(brdata0final, 7, 7) @[el2_ifu_aln_ctl.scala 231:33] - node _T_352 = bits(brdata0final, 1, 1) @[el2_ifu_aln_ctl.scala 231:49] - node f0brend = cat(_T_351, _T_352) @[Cat.scala 29:58] - node _T_353 = bits(brdata0final, 8, 8) @[el2_ifu_aln_ctl.scala 232:31] - node _T_354 = bits(brdata0final, 2, 2) @[el2_ifu_aln_ctl.scala 232:47] - node f0way = cat(_T_353, _T_354) @[Cat.scala 29:58] - node _T_355 = bits(brdata0final, 9, 9) @[el2_ifu_aln_ctl.scala 233:31] - node _T_356 = bits(brdata0final, 3, 3) @[el2_ifu_aln_ctl.scala 233:47] - node f0pc4 = cat(_T_355, _T_356) @[Cat.scala 29:58] - node _T_357 = bits(brdata0final, 10, 10) @[el2_ifu_aln_ctl.scala 234:33] - node _T_358 = bits(brdata0final, 4, 4) @[el2_ifu_aln_ctl.scala 234:50] - node f0hist0 = cat(_T_357, _T_358) @[Cat.scala 29:58] - node _T_359 = bits(brdata0final, 11, 11) @[el2_ifu_aln_ctl.scala 235:33] - node _T_360 = bits(brdata0final, 5, 5) @[el2_ifu_aln_ctl.scala 235:50] - node f0hist1 = cat(_T_359, _T_360) @[Cat.scala 29:58] - node _T_361 = bits(brdata1final, 6, 6) @[el2_ifu_aln_ctl.scala 237:31] - node _T_362 = bits(brdata1final, 0, 0) @[el2_ifu_aln_ctl.scala 237:47] - node f1ret = cat(_T_361, _T_362) @[Cat.scala 29:58] - node _T_363 = bits(brdata1final, 7, 7) @[el2_ifu_aln_ctl.scala 238:33] - node _T_364 = bits(brdata1final, 1, 1) @[el2_ifu_aln_ctl.scala 238:49] - node f1brend = cat(_T_363, _T_364) @[Cat.scala 29:58] - node _T_365 = bits(brdata1final, 8, 8) @[el2_ifu_aln_ctl.scala 239:31] - node _T_366 = bits(brdata1final, 2, 2) @[el2_ifu_aln_ctl.scala 239:47] - node f1way = cat(_T_365, _T_366) @[Cat.scala 29:58] - node _T_367 = bits(brdata1final, 9, 9) @[el2_ifu_aln_ctl.scala 240:31] - node _T_368 = bits(brdata1final, 3, 3) @[el2_ifu_aln_ctl.scala 240:47] - node f1pc4 = cat(_T_367, _T_368) @[Cat.scala 29:58] - node _T_369 = bits(brdata1final, 10, 10) @[el2_ifu_aln_ctl.scala 241:33] - node _T_370 = bits(brdata1final, 4, 4) @[el2_ifu_aln_ctl.scala 241:50] - node f1hist0 = cat(_T_369, _T_370) @[Cat.scala 29:58] - node _T_371 = bits(brdata1final, 11, 11) @[el2_ifu_aln_ctl.scala 242:33] - node _T_372 = bits(brdata1final, 5, 5) @[el2_ifu_aln_ctl.scala 242:50] - node f1hist1 = cat(_T_371, _T_372) @[Cat.scala 29:58] - node _T_373 = bits(f2val, 0, 0) @[el2_ifu_aln_ctl.scala 246:20] - f2_valid <= _T_373 @[el2_ifu_aln_ctl.scala 246:12] - node _T_374 = bits(sf1val, 0, 0) @[el2_ifu_aln_ctl.scala 247:22] - sf1_valid <= _T_374 @[el2_ifu_aln_ctl.scala 247:13] - node _T_375 = bits(sf0val, 0, 0) @[el2_ifu_aln_ctl.scala 248:22] - sf0_valid <= _T_375 @[el2_ifu_aln_ctl.scala 248:13] - node _T_376 = bits(sf0val, 0, 0) @[el2_ifu_aln_ctl.scala 250:28] - node _T_377 = eq(_T_376, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 250:21] - node _T_378 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 250:39] - node consume_fb0 = and(_T_377, _T_378) @[el2_ifu_aln_ctl.scala 250:32] - node _T_379 = bits(sf1val, 0, 0) @[el2_ifu_aln_ctl.scala 251:28] - node _T_380 = eq(_T_379, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 251:21] - node _T_381 = bits(f1val, 0, 0) @[el2_ifu_aln_ctl.scala 251:39] - node consume_fb1 = and(_T_380, _T_381) @[el2_ifu_aln_ctl.scala 251:32] - node _T_382 = eq(consume_fb1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 253:39] - node _T_383 = and(consume_fb0, _T_382) @[el2_ifu_aln_ctl.scala 253:37] - node _T_384 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 253:54] - node _T_385 = and(_T_383, _T_384) @[el2_ifu_aln_ctl.scala 253:52] - io.ifu_fb_consume1 <= _T_385 @[el2_ifu_aln_ctl.scala 253:22] - node _T_386 = and(consume_fb0, consume_fb1) @[el2_ifu_aln_ctl.scala 254:37] - node _T_387 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 254:54] - node _T_388 = and(_T_386, _T_387) @[el2_ifu_aln_ctl.scala 254:52] - io.ifu_fb_consume2 <= _T_388 @[el2_ifu_aln_ctl.scala 254:22] - node _T_389 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_aln_ctl.scala 256:30] - ifvalid <= _T_389 @[el2_ifu_aln_ctl.scala 256:11] - node _T_390 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 258:18] - node _T_391 = and(_T_390, sf1_valid) @[el2_ifu_aln_ctl.scala 258:29] - shift_f1_f0 <= _T_391 @[el2_ifu_aln_ctl.scala 258:15] - node _T_392 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 259:18] - node _T_393 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 259:31] - node _T_394 = and(_T_392, _T_393) @[el2_ifu_aln_ctl.scala 259:29] - node _T_395 = and(_T_394, f2_valid) @[el2_ifu_aln_ctl.scala 259:42] - shift_f2_f0 <= _T_395 @[el2_ifu_aln_ctl.scala 259:15] - node _T_396 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 260:18] - node _T_397 = and(_T_396, sf1_valid) @[el2_ifu_aln_ctl.scala 260:29] - node _T_398 = and(_T_397, f2_valid) @[el2_ifu_aln_ctl.scala 260:42] - shift_f2_f1 <= _T_398 @[el2_ifu_aln_ctl.scala 260:15] - wire f0pc : UInt<31> - f0pc <= UInt<1>("h00") - wire f2pc : UInt<31> - f2pc <= UInt<1>("h00") - node _T_399 = add(f0pc, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 265:25] - node f0pc_plus1 = tail(_T_399, 1) @[el2_ifu_aln_ctl.scala 265:25] - node _T_400 = bits(f1_shift_2B, 0, 0) @[Bitwise.scala 72:15] - node _T_401 = mux(_T_400, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] - node _T_402 = and(_T_401, f0pc_plus1) @[el2_ifu_aln_ctl.scala 267:38] - node _T_403 = eq(f1_shift_2B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 267:64] - node _T_404 = bits(_T_403, 0, 0) @[Bitwise.scala 72:15] - node _T_405 = mux(_T_404, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] - node _T_406 = and(_T_405, f0pc) @[el2_ifu_aln_ctl.scala 267:78] - node sf1pc = or(_T_402, _T_406) @[el2_ifu_aln_ctl.scala 267:52] - node _T_407 = bits(fetch_to_f1, 0, 0) @[el2_ifu_aln_ctl.scala 269:39] - node _T_408 = bits(shift_f2_f1, 0, 0) @[el2_ifu_aln_ctl.scala 270:39] - node _T_409 = eq(fetch_to_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 271:28] - node _T_410 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 271:43] - node _T_411 = and(_T_409, _T_410) @[el2_ifu_aln_ctl.scala 271:41] - node _T_412 = bits(_T_411, 0, 0) @[el2_ifu_aln_ctl.scala 271:57] - node _T_413 = mux(_T_407, io.ifu_fetch_pc, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_414 = mux(_T_408, f2pc, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_415 = mux(_T_412, sf1pc, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_416 = or(_T_413, _T_414) @[Mux.scala 27:72] - node _T_417 = or(_T_416, _T_415) @[Mux.scala 27:72] - wire f1pc_in : UInt<32> @[Mux.scala 27:72] - f1pc_in <= _T_417 @[Mux.scala 27:72] - node _T_418 = bits(fetch_to_f0, 0, 0) @[el2_ifu_aln_ctl.scala 273:39] - node _T_419 = bits(shift_f2_f0, 0, 0) @[el2_ifu_aln_ctl.scala 274:39] - node _T_420 = bits(shift_f1_f0, 0, 0) @[el2_ifu_aln_ctl.scala 275:39] - node _T_421 = eq(fetch_to_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 276:28] - node _T_422 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 276:43] - node _T_423 = and(_T_421, _T_422) @[el2_ifu_aln_ctl.scala 276:41] - node _T_424 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 276:58] - node _T_425 = and(_T_423, _T_424) @[el2_ifu_aln_ctl.scala 276:56] - node _T_426 = bits(_T_425, 0, 0) @[el2_ifu_aln_ctl.scala 276:72] - node _T_427 = mux(_T_418, io.ifu_fetch_pc, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_428 = mux(_T_419, f2pc, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_429 = mux(_T_420, sf1pc, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_430 = mux(_T_426, f0pc_plus1, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_431 = or(_T_427, _T_428) @[Mux.scala 27:72] - node _T_432 = or(_T_431, _T_429) @[Mux.scala 27:72] - node _T_433 = or(_T_432, _T_430) @[Mux.scala 27:72] - wire f0pc_in : UInt<32> @[Mux.scala 27:72] - f0pc_in <= _T_433 @[Mux.scala 27:72] - node _T_434 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 278:40] - node _T_435 = and(f2_wr_en, _T_434) @[el2_ifu_aln_ctl.scala 278:38] - node _T_436 = bits(_T_435, 0, 0) @[el2_ifu_aln_ctl.scala 278:61] - node _T_437 = eq(f2_wr_en, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 279:6] - node _T_438 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 279:21] - node _T_439 = and(_T_437, _T_438) @[el2_ifu_aln_ctl.scala 279:19] - node _T_440 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 279:36] - node _T_441 = and(_T_439, _T_440) @[el2_ifu_aln_ctl.scala 279:34] - node _T_442 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 279:51] - node _T_443 = and(_T_441, _T_442) @[el2_ifu_aln_ctl.scala 279:49] - node _T_444 = bits(_T_443, 0, 0) @[el2_ifu_aln_ctl.scala 279:72] - node _T_445 = mux(_T_436, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_446 = mux(_T_444, f2val, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_447 = or(_T_445, _T_446) @[Mux.scala 27:72] - wire _T_448 : UInt @[Mux.scala 27:72] - _T_448 <= _T_447 @[Mux.scala 27:72] - f2val_in <= _T_448 @[el2_ifu_aln_ctl.scala 278:12] - node _T_449 = bits(f1_shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 281:35] - node _T_450 = bits(f1val, 1, 1) @[el2_ifu_aln_ctl.scala 281:48] - node _T_451 = bits(f1_shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 281:66] - node _T_452 = eq(_T_451, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 281:53] - node _T_453 = mux(_T_449, _T_450, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_454 = mux(_T_452, f1val, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_455 = or(_T_453, _T_454) @[Mux.scala 27:72] - wire _T_456 : UInt @[Mux.scala 27:72] - _T_456 <= _T_455 @[Mux.scala 27:72] - sf1val <= _T_456 @[el2_ifu_aln_ctl.scala 281:10] - node _T_457 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 283:40] - node _T_458 = and(fetch_to_f1, _T_457) @[el2_ifu_aln_ctl.scala 283:38] - node _T_459 = bits(_T_458, 0, 0) @[el2_ifu_aln_ctl.scala 283:61] - node _T_460 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 284:40] - node _T_461 = and(shift_f2_f1, _T_460) @[el2_ifu_aln_ctl.scala 284:38] - node _T_462 = bits(_T_461, 0, 0) @[el2_ifu_aln_ctl.scala 284:61] - node _T_463 = eq(fetch_to_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 285:26] - node _T_464 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 285:41] - node _T_465 = and(_T_463, _T_464) @[el2_ifu_aln_ctl.scala 285:39] - node _T_466 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 285:56] - node _T_467 = and(_T_465, _T_466) @[el2_ifu_aln_ctl.scala 285:54] - node _T_468 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 285:71] - node _T_469 = and(_T_467, _T_468) @[el2_ifu_aln_ctl.scala 285:69] - node _T_470 = bits(_T_469, 0, 0) @[el2_ifu_aln_ctl.scala 285:92] - node _T_471 = mux(_T_459, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_472 = mux(_T_462, f2val, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_473 = mux(_T_470, sf1val, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_474 = or(_T_471, _T_472) @[Mux.scala 27:72] - node _T_475 = or(_T_474, _T_473) @[Mux.scala 27:72] - wire _T_476 : UInt @[Mux.scala 27:72] - _T_476 <= _T_475 @[Mux.scala 27:72] - f1val_in <= _T_476 @[el2_ifu_aln_ctl.scala 283:12] - node _T_477 = bits(shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 287:31] - node _T_478 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 287:46] - node _T_479 = eq(shift_2B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 287:52] - node _T_480 = eq(shift_4B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 287:64] - node _T_481 = and(_T_479, _T_480) @[el2_ifu_aln_ctl.scala 287:62] - node _T_482 = bits(_T_481, 0, 0) @[el2_ifu_aln_ctl.scala 287:75] - node _T_483 = mux(_T_477, _T_478, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_484 = mux(_T_482, f0val, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_485 = or(_T_483, _T_484) @[Mux.scala 27:72] - wire _T_486 : UInt @[Mux.scala 27:72] - _T_486 <= _T_485 @[Mux.scala 27:72] - f0val <= _T_486 @[el2_ifu_aln_ctl.scala 287:9] - node _T_487 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 289:40] - node _T_488 = and(fetch_to_f0, _T_487) @[el2_ifu_aln_ctl.scala 289:38] - node _T_489 = bits(_T_488, 0, 0) @[el2_ifu_aln_ctl.scala 289:61] - node _T_490 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 290:40] - node _T_491 = and(shift_f2_f0, _T_490) @[el2_ifu_aln_ctl.scala 290:38] - node _T_492 = bits(_T_491, 0, 0) @[el2_ifu_aln_ctl.scala 290:61] - node _T_493 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 291:40] - node _T_494 = and(shift_f1_f0, _T_493) @[el2_ifu_aln_ctl.scala 291:38] - node _T_495 = bits(_T_494, 0, 0) @[el2_ifu_aln_ctl.scala 291:67] - node _T_496 = eq(fetch_to_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 292:26] - node _T_497 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 292:41] - node _T_498 = and(_T_496, _T_497) @[el2_ifu_aln_ctl.scala 292:39] - node _T_499 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 292:56] - node _T_500 = and(_T_498, _T_499) @[el2_ifu_aln_ctl.scala 292:54] - node _T_501 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 292:71] - node _T_502 = and(_T_500, _T_501) @[el2_ifu_aln_ctl.scala 292:69] - node _T_503 = bits(_T_502, 0, 0) @[el2_ifu_aln_ctl.scala 292:92] - node _T_504 = mux(_T_489, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_505 = mux(_T_492, f2val, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_506 = mux(_T_495, sf1val, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_507 = mux(_T_503, sf0val, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_508 = or(_T_504, _T_505) @[Mux.scala 27:72] - node _T_509 = or(_T_508, _T_506) @[Mux.scala 27:72] - node _T_510 = or(_T_509, _T_507) @[Mux.scala 27:72] - wire _T_511 : UInt @[Mux.scala 27:72] - _T_511 <= _T_510 @[Mux.scala 27:72] - f0val_in <= _T_511 @[el2_ifu_aln_ctl.scala 289:12] - node _T_512 = bits(q0sel, 0, 0) @[el2_ifu_aln_ctl.scala 294:29] - node _T_513 = bits(_T_512, 0, 0) @[el2_ifu_aln_ctl.scala 294:33] - node _T_514 = bits(q0sel, 1, 1) @[el2_ifu_aln_ctl.scala 294:53] - node _T_515 = bits(_T_514, 0, 0) @[el2_ifu_aln_ctl.scala 294:57] - node _T_516 = bits(q0eff, 31, 16) @[el2_ifu_aln_ctl.scala 294:70] - node _T_517 = mux(_T_513, q0eff, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_518 = mux(_T_515, _T_516, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_519 = or(_T_517, _T_518) @[Mux.scala 27:72] - wire _T_520 : UInt<32> @[Mux.scala 27:72] - _T_520 <= _T_519 @[Mux.scala 27:72] - q0final <= _T_520 @[el2_ifu_aln_ctl.scala 294:11] - node _T_521 = bits(q1sel, 0, 0) @[el2_ifu_aln_ctl.scala 296:29] - node _T_522 = bits(_T_521, 0, 0) @[el2_ifu_aln_ctl.scala 296:33] - node _T_523 = bits(q1eff, 15, 0) @[el2_ifu_aln_ctl.scala 296:46] - node _T_524 = bits(q1sel, 1, 1) @[el2_ifu_aln_ctl.scala 296:59] - node _T_525 = bits(_T_524, 0, 0) @[el2_ifu_aln_ctl.scala 296:63] - node _T_526 = bits(q1eff, 31, 16) @[el2_ifu_aln_ctl.scala 296:76] - node _T_527 = mux(_T_522, _T_523, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_528 = mux(_T_525, _T_526, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_529 = or(_T_527, _T_528) @[Mux.scala 27:72] - wire _T_530 : UInt<16> @[Mux.scala 27:72] - _T_530 <= _T_529 @[Mux.scala 27:72] - q1final <= _T_530 @[el2_ifu_aln_ctl.scala 296:11] - node _T_531 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 298:30] - node _T_532 = bits(_T_531, 0, 0) @[el2_ifu_aln_ctl.scala 298:34] - node _T_533 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 298:54] - node _T_534 = eq(_T_533, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 298:48] - node _T_535 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 298:65] - node _T_536 = and(_T_534, _T_535) @[el2_ifu_aln_ctl.scala 298:58] - node _T_537 = bits(f1val, 0, 0) @[el2_ifu_aln_ctl.scala 298:82] - node _T_538 = cat(_T_537, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_539 = mux(_T_532, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_540 = mux(_T_536, _T_538, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_541 = or(_T_539, _T_540) @[Mux.scala 27:72] - wire _T_542 : UInt<2> @[Mux.scala 27:72] - _T_542 <= _T_541 @[Mux.scala 27:72] - alignval <= _T_542 @[el2_ifu_aln_ctl.scala 298:12] - node _T_543 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 300:35] - node _T_544 = bits(_T_543, 0, 0) @[el2_ifu_aln_ctl.scala 300:39] - node _T_545 = bits(f0dbecc, 0, 0) @[Bitwise.scala 72:15] - node _T_546 = mux(_T_545, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_547 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 300:73] - node _T_548 = eq(_T_547, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 300:67] - node _T_549 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 300:84] - node _T_550 = and(_T_548, _T_549) @[el2_ifu_aln_ctl.scala 300:77] - node _T_551 = bits(_T_550, 0, 0) @[el2_ifu_aln_ctl.scala 300:89] - node _T_552 = cat(f1dbecc, f0dbecc) @[Cat.scala 29:58] - node _T_553 = mux(_T_544, _T_546, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_554 = mux(_T_551, _T_552, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_555 = or(_T_553, _T_554) @[Mux.scala 27:72] + brdata1final <= _T_278 @[Mux.scala 27:72] + node _T_279 = bits(brdata0final, 6, 6) @[el2_ifu_aln_ctl.scala 220:31] + node _T_280 = bits(brdata0final, 0, 0) @[el2_ifu_aln_ctl.scala 220:47] + node f0ret = cat(_T_279, _T_280) @[Cat.scala 29:58] + node _T_281 = bits(brdata0final, 7, 7) @[el2_ifu_aln_ctl.scala 221:33] + node _T_282 = bits(brdata0final, 1, 1) @[el2_ifu_aln_ctl.scala 221:49] + node f0brend = cat(_T_281, _T_282) @[Cat.scala 29:58] + node _T_283 = bits(brdata0final, 8, 8) @[el2_ifu_aln_ctl.scala 222:31] + node _T_284 = bits(brdata0final, 2, 2) @[el2_ifu_aln_ctl.scala 222:47] + node f0way = cat(_T_283, _T_284) @[Cat.scala 29:58] + node _T_285 = bits(brdata0final, 9, 9) @[el2_ifu_aln_ctl.scala 223:31] + node _T_286 = bits(brdata0final, 3, 3) @[el2_ifu_aln_ctl.scala 223:47] + node f0pc4 = cat(_T_285, _T_286) @[Cat.scala 29:58] + node _T_287 = bits(brdata0final, 10, 10) @[el2_ifu_aln_ctl.scala 224:33] + node _T_288 = bits(brdata0final, 4, 4) @[el2_ifu_aln_ctl.scala 224:50] + node f0hist0 = cat(_T_287, _T_288) @[Cat.scala 29:58] + node _T_289 = bits(brdata0final, 11, 11) @[el2_ifu_aln_ctl.scala 225:33] + node _T_290 = bits(brdata0final, 5, 5) @[el2_ifu_aln_ctl.scala 225:50] + node f0hist1 = cat(_T_289, _T_290) @[Cat.scala 29:58] + node _T_291 = bits(brdata1final, 6, 6) @[el2_ifu_aln_ctl.scala 227:31] + node _T_292 = bits(brdata1final, 0, 0) @[el2_ifu_aln_ctl.scala 227:47] + node f1ret = cat(_T_291, _T_292) @[Cat.scala 29:58] + node _T_293 = bits(brdata1final, 7, 7) @[el2_ifu_aln_ctl.scala 228:33] + node _T_294 = bits(brdata1final, 1, 1) @[el2_ifu_aln_ctl.scala 228:49] + node f1brend = cat(_T_293, _T_294) @[Cat.scala 29:58] + node _T_295 = bits(brdata1final, 8, 8) @[el2_ifu_aln_ctl.scala 229:31] + node _T_296 = bits(brdata1final, 2, 2) @[el2_ifu_aln_ctl.scala 229:47] + node f1way = cat(_T_295, _T_296) @[Cat.scala 29:58] + node _T_297 = bits(brdata1final, 9, 9) @[el2_ifu_aln_ctl.scala 230:31] + node _T_298 = bits(brdata1final, 3, 3) @[el2_ifu_aln_ctl.scala 230:47] + node f1pc4 = cat(_T_297, _T_298) @[Cat.scala 29:58] + node _T_299 = bits(brdata1final, 10, 10) @[el2_ifu_aln_ctl.scala 231:33] + node _T_300 = bits(brdata1final, 4, 4) @[el2_ifu_aln_ctl.scala 231:50] + node f1hist0 = cat(_T_299, _T_300) @[Cat.scala 29:58] + node _T_301 = bits(brdata1final, 11, 11) @[el2_ifu_aln_ctl.scala 232:33] + node _T_302 = bits(brdata1final, 5, 5) @[el2_ifu_aln_ctl.scala 232:50] + node f1hist1 = cat(_T_301, _T_302) @[Cat.scala 29:58] + node _T_303 = bits(f2val, 0, 0) @[el2_ifu_aln_ctl.scala 235:20] + f2_valid <= _T_303 @[el2_ifu_aln_ctl.scala 235:12] + node _T_304 = bits(sf1val, 0, 0) @[el2_ifu_aln_ctl.scala 236:22] + sf1_valid <= _T_304 @[el2_ifu_aln_ctl.scala 236:13] + node _T_305 = bits(sf0val, 0, 0) @[el2_ifu_aln_ctl.scala 237:22] + sf0_valid <= _T_305 @[el2_ifu_aln_ctl.scala 237:13] + node _T_306 = bits(sf0val, 0, 0) @[el2_ifu_aln_ctl.scala 239:28] + node _T_307 = eq(_T_306, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 239:21] + node _T_308 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 239:39] + node consume_fb0 = and(_T_307, _T_308) @[el2_ifu_aln_ctl.scala 239:32] + node _T_309 = bits(sf1val, 0, 0) @[el2_ifu_aln_ctl.scala 240:28] + node _T_310 = eq(_T_309, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 240:21] + node _T_311 = bits(f1val, 0, 0) @[el2_ifu_aln_ctl.scala 240:39] + node consume_fb1 = and(_T_310, _T_311) @[el2_ifu_aln_ctl.scala 240:32] + node _T_312 = eq(consume_fb1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 242:39] + node _T_313 = and(consume_fb0, _T_312) @[el2_ifu_aln_ctl.scala 242:37] + node _T_314 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 242:54] + node _T_315 = and(_T_313, _T_314) @[el2_ifu_aln_ctl.scala 242:52] + io.ifu_fb_consume1 <= _T_315 @[el2_ifu_aln_ctl.scala 242:22] + node _T_316 = and(consume_fb0, consume_fb1) @[el2_ifu_aln_ctl.scala 243:37] + node _T_317 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 243:54] + node _T_318 = and(_T_316, _T_317) @[el2_ifu_aln_ctl.scala 243:52] + io.ifu_fb_consume2 <= _T_318 @[el2_ifu_aln_ctl.scala 243:22] + node _T_319 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_aln_ctl.scala 245:30] + ifvalid <= _T_319 @[el2_ifu_aln_ctl.scala 245:11] + node _T_320 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 247:18] + node _T_321 = and(_T_320, sf1_valid) @[el2_ifu_aln_ctl.scala 247:29] + shift_f1_f0 <= _T_321 @[el2_ifu_aln_ctl.scala 247:15] + node _T_322 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 248:18] + node _T_323 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 248:31] + node _T_324 = and(_T_322, _T_323) @[el2_ifu_aln_ctl.scala 248:29] + node _T_325 = and(_T_324, f2_valid) @[el2_ifu_aln_ctl.scala 248:42] + shift_f2_f0 <= _T_325 @[el2_ifu_aln_ctl.scala 248:15] + node _T_326 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 249:18] + node _T_327 = and(_T_326, sf1_valid) @[el2_ifu_aln_ctl.scala 249:29] + node _T_328 = and(_T_327, f2_valid) @[el2_ifu_aln_ctl.scala 249:42] + shift_f2_f1 <= _T_328 @[el2_ifu_aln_ctl.scala 249:15] + node _T_329 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 251:26] + node _T_330 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 251:39] + node _T_331 = and(_T_329, _T_330) @[el2_ifu_aln_ctl.scala 251:37] + node _T_332 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 251:52] + node _T_333 = and(_T_331, _T_332) @[el2_ifu_aln_ctl.scala 251:50] + node _T_334 = and(_T_333, ifvalid) @[el2_ifu_aln_ctl.scala 251:62] + fetch_to_f0 <= _T_334 @[el2_ifu_aln_ctl.scala 251:22] + node _T_335 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 252:26] + node _T_336 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 252:39] + node _T_337 = and(_T_335, _T_336) @[el2_ifu_aln_ctl.scala 252:37] + node _T_338 = and(_T_337, f2_valid) @[el2_ifu_aln_ctl.scala 252:50] + node _T_339 = and(_T_338, ifvalid) @[el2_ifu_aln_ctl.scala 252:62] + node _T_340 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 253:6] + node _T_341 = and(_T_340, sf1_valid) @[el2_ifu_aln_ctl.scala 253:17] + node _T_342 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 253:32] + node _T_343 = and(_T_341, _T_342) @[el2_ifu_aln_ctl.scala 253:30] + node _T_344 = and(_T_343, ifvalid) @[el2_ifu_aln_ctl.scala 253:42] + node _T_345 = or(_T_339, _T_344) @[el2_ifu_aln_ctl.scala 252:74] + node _T_346 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 254:19] + node _T_347 = and(sf0_valid, _T_346) @[el2_ifu_aln_ctl.scala 254:17] + node _T_348 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 254:32] + node _T_349 = and(_T_347, _T_348) @[el2_ifu_aln_ctl.scala 254:30] + node _T_350 = and(_T_349, ifvalid) @[el2_ifu_aln_ctl.scala 254:42] + node _T_351 = or(_T_345, _T_350) @[el2_ifu_aln_ctl.scala 253:54] + fetch_to_f1 <= _T_351 @[el2_ifu_aln_ctl.scala 252:22] + node _T_352 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 256:26] + node _T_353 = and(_T_352, sf1_valid) @[el2_ifu_aln_ctl.scala 256:37] + node _T_354 = and(_T_353, f2_valid) @[el2_ifu_aln_ctl.scala 256:50] + node _T_355 = and(_T_354, ifvalid) @[el2_ifu_aln_ctl.scala 256:62] + node _T_356 = and(sf0_valid, sf1_valid) @[el2_ifu_aln_ctl.scala 257:17] + node _T_357 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 257:32] + node _T_358 = and(_T_356, _T_357) @[el2_ifu_aln_ctl.scala 257:30] + node _T_359 = and(_T_358, ifvalid) @[el2_ifu_aln_ctl.scala 257:42] + node _T_360 = or(_T_355, _T_359) @[el2_ifu_aln_ctl.scala 256:74] + fetch_to_f2 <= _T_360 @[el2_ifu_aln_ctl.scala 256:22] + node _T_361 = add(f0pc, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 259:25] + node f0pc_plus1 = tail(_T_361, 1) @[el2_ifu_aln_ctl.scala 259:25] + node _T_362 = add(f1pc, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 261:25] + node f1pc_plus1 = tail(_T_362, 1) @[el2_ifu_aln_ctl.scala 261:25] + node _T_363 = bits(f1_shift_2B, 0, 0) @[Bitwise.scala 72:15] + node _T_364 = mux(_T_363, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] + node _T_365 = and(_T_364, f0pc_plus1) @[el2_ifu_aln_ctl.scala 263:38] + node _T_366 = eq(f1_shift_2B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 263:64] + node _T_367 = bits(_T_366, 0, 0) @[Bitwise.scala 72:15] + node _T_368 = mux(_T_367, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] + node _T_369 = and(_T_368, f0pc) @[el2_ifu_aln_ctl.scala 263:78] + node sf1pc = or(_T_365, _T_369) @[el2_ifu_aln_ctl.scala 263:52] + node _T_370 = bits(fetch_to_f1, 0, 0) @[el2_ifu_aln_ctl.scala 265:36] + node _T_371 = bits(shift_f2_f1, 0, 0) @[el2_ifu_aln_ctl.scala 266:17] + node _T_372 = eq(fetch_to_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 267:6] + node _T_373 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 267:21] + node _T_374 = and(_T_372, _T_373) @[el2_ifu_aln_ctl.scala 267:19] + node _T_375 = bits(_T_374, 0, 0) @[el2_ifu_aln_ctl.scala 267:35] + node _T_376 = mux(_T_370, io.ifu_fetch_pc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_377 = mux(_T_371, f2pc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_378 = mux(_T_375, sf1pc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_379 = or(_T_376, _T_377) @[Mux.scala 27:72] + node _T_380 = or(_T_379, _T_378) @[Mux.scala 27:72] + wire _T_381 : UInt @[Mux.scala 27:72] + _T_381 <= _T_380 @[Mux.scala 27:72] + f1pc_in <= _T_381 @[el2_ifu_aln_ctl.scala 265:11] + node _T_382 = bits(fetch_to_f0, 0, 0) @[el2_ifu_aln_ctl.scala 269:36] + node _T_383 = bits(shift_f2_f0, 0, 0) @[el2_ifu_aln_ctl.scala 270:36] + node _T_384 = bits(shift_f1_f0, 0, 0) @[el2_ifu_aln_ctl.scala 271:36] + node _T_385 = eq(fetch_to_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 272:24] + node _T_386 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 272:39] + node _T_387 = and(_T_385, _T_386) @[el2_ifu_aln_ctl.scala 272:37] + node _T_388 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 272:54] + node _T_389 = and(_T_387, _T_388) @[el2_ifu_aln_ctl.scala 272:52] + node _T_390 = bits(_T_389, 0, 0) @[el2_ifu_aln_ctl.scala 272:68] + node _T_391 = mux(_T_382, io.ifu_fetch_pc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_392 = mux(_T_383, f2pc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_393 = mux(_T_384, sf1pc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_394 = mux(_T_390, f0pc_plus1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_395 = or(_T_391, _T_392) @[Mux.scala 27:72] + node _T_396 = or(_T_395, _T_393) @[Mux.scala 27:72] + node _T_397 = or(_T_396, _T_394) @[Mux.scala 27:72] + wire _T_398 : UInt @[Mux.scala 27:72] + _T_398 <= _T_397 @[Mux.scala 27:72] + f0pc_in <= _T_398 @[el2_ifu_aln_ctl.scala 269:11] + node _T_399 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 274:40] + node _T_400 = and(fetch_to_f2, _T_399) @[el2_ifu_aln_ctl.scala 274:38] + node _T_401 = bits(_T_400, 0, 0) @[el2_ifu_aln_ctl.scala 274:61] + node _T_402 = eq(fetch_to_f2, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 275:6] + node _T_403 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 275:21] + node _T_404 = and(_T_402, _T_403) @[el2_ifu_aln_ctl.scala 275:19] + node _T_405 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 275:36] + node _T_406 = and(_T_404, _T_405) @[el2_ifu_aln_ctl.scala 275:34] + node _T_407 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 275:51] + node _T_408 = and(_T_406, _T_407) @[el2_ifu_aln_ctl.scala 275:49] + node _T_409 = bits(_T_408, 0, 0) @[el2_ifu_aln_ctl.scala 275:72] + node _T_410 = mux(_T_401, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_411 = mux(_T_409, f2val, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_412 = or(_T_410, _T_411) @[Mux.scala 27:72] + wire _T_413 : UInt @[Mux.scala 27:72] + _T_413 <= _T_412 @[Mux.scala 27:72] + f2val_in <= _T_413 @[el2_ifu_aln_ctl.scala 274:12] + node _T_414 = bits(f1_shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 277:35] + node _T_415 = bits(f1val, 1, 1) @[el2_ifu_aln_ctl.scala 277:48] + node _T_416 = bits(f1_shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 277:66] + node _T_417 = eq(_T_416, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 277:53] + node _T_418 = mux(_T_414, _T_415, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_419 = mux(_T_417, f1val, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_420 = or(_T_418, _T_419) @[Mux.scala 27:72] + wire _T_421 : UInt @[Mux.scala 27:72] + _T_421 <= _T_420 @[Mux.scala 27:72] + sf1val <= _T_421 @[el2_ifu_aln_ctl.scala 277:10] + node _T_422 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 279:40] + node _T_423 = and(fetch_to_f1, _T_422) @[el2_ifu_aln_ctl.scala 279:38] + node _T_424 = bits(_T_423, 0, 0) @[el2_ifu_aln_ctl.scala 279:61] + node _T_425 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 280:20] + node _T_426 = and(shift_f2_f1, _T_425) @[el2_ifu_aln_ctl.scala 280:18] + node _T_427 = bits(_T_426, 0, 0) @[el2_ifu_aln_ctl.scala 280:41] + node _T_428 = eq(fetch_to_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 281:6] + node _T_429 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 281:21] + node _T_430 = and(_T_428, _T_429) @[el2_ifu_aln_ctl.scala 281:19] + node _T_431 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 281:36] + node _T_432 = and(_T_430, _T_431) @[el2_ifu_aln_ctl.scala 281:34] + node _T_433 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 281:51] + node _T_434 = and(_T_432, _T_433) @[el2_ifu_aln_ctl.scala 281:49] + node _T_435 = bits(_T_434, 0, 0) @[el2_ifu_aln_ctl.scala 281:72] + node _T_436 = mux(_T_424, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_437 = mux(_T_427, f2val, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_438 = mux(_T_435, sf1val, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_439 = or(_T_436, _T_437) @[Mux.scala 27:72] + node _T_440 = or(_T_439, _T_438) @[Mux.scala 27:72] + wire _T_441 : UInt @[Mux.scala 27:72] + _T_441 <= _T_440 @[Mux.scala 27:72] + f1val_in <= _T_441 @[el2_ifu_aln_ctl.scala 279:12] + node _T_442 = bits(shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 283:32] + node _T_443 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 283:54] + node _T_444 = cat(UInt<1>("h00"), _T_443) @[Cat.scala 29:58] + node _T_445 = eq(shift_2B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 284:6] + node _T_446 = eq(shift_4B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 284:18] + node _T_447 = and(_T_445, _T_446) @[el2_ifu_aln_ctl.scala 284:16] + node _T_448 = bits(_T_447, 0, 0) @[el2_ifu_aln_ctl.scala 284:29] + node _T_449 = mux(_T_442, _T_444, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_450 = mux(_T_448, f1val, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_451 = or(_T_449, _T_450) @[Mux.scala 27:72] + wire _T_452 : UInt @[Mux.scala 27:72] + _T_452 <= _T_451 @[Mux.scala 27:72] + sf0val <= _T_452 @[el2_ifu_aln_ctl.scala 283:10] + node _T_453 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 286:40] + node _T_454 = and(fetch_to_f0, _T_453) @[el2_ifu_aln_ctl.scala 286:38] + node _T_455 = bits(_T_454, 0, 0) @[el2_ifu_aln_ctl.scala 286:61] + node _T_456 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 287:20] + node _T_457 = and(shift_f2_f0, _T_456) @[el2_ifu_aln_ctl.scala 287:18] + node _T_458 = bits(_T_457, 0, 0) @[el2_ifu_aln_ctl.scala 287:41] + node _T_459 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 288:20] + node _T_460 = and(shift_f1_f0, _T_459) @[el2_ifu_aln_ctl.scala 288:18] + node _T_461 = bits(_T_460, 0, 0) @[el2_ifu_aln_ctl.scala 288:47] + node _T_462 = eq(fetch_to_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 289:6] + node _T_463 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 289:21] + node _T_464 = and(_T_462, _T_463) @[el2_ifu_aln_ctl.scala 289:19] + node _T_465 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 289:36] + node _T_466 = and(_T_464, _T_465) @[el2_ifu_aln_ctl.scala 289:34] + node _T_467 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 289:51] + node _T_468 = and(_T_466, _T_467) @[el2_ifu_aln_ctl.scala 289:49] + node _T_469 = bits(_T_468, 0, 0) @[el2_ifu_aln_ctl.scala 289:72] + node _T_470 = mux(_T_455, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_471 = mux(_T_458, f2val, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_472 = mux(_T_461, sf1val, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_473 = mux(_T_469, sf0val, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_474 = or(_T_470, _T_471) @[Mux.scala 27:72] + node _T_475 = or(_T_474, _T_472) @[Mux.scala 27:72] + node _T_476 = or(_T_475, _T_473) @[Mux.scala 27:72] + wire _T_477 : UInt @[Mux.scala 27:72] + _T_477 <= _T_476 @[Mux.scala 27:72] + f0val_in <= _T_477 @[el2_ifu_aln_ctl.scala 286:12] + node _T_478 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 291:28] + node _T_479 = bits(_T_478, 0, 0) @[el2_ifu_aln_ctl.scala 291:32] + node _T_480 = cat(q1, q0) @[Cat.scala 29:58] + node _T_481 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 292:9] + node _T_482 = bits(_T_481, 0, 0) @[el2_ifu_aln_ctl.scala 292:13] + node _T_483 = cat(q2, q1) @[Cat.scala 29:58] + node _T_484 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 293:9] + node _T_485 = bits(_T_484, 0, 0) @[el2_ifu_aln_ctl.scala 293:13] + node _T_486 = cat(q0, q2) @[Cat.scala 29:58] + node _T_487 = mux(_T_479, _T_480, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_488 = mux(_T_482, _T_483, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_489 = mux(_T_485, _T_486, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_490 = or(_T_487, _T_488) @[Mux.scala 27:72] + node _T_491 = or(_T_490, _T_489) @[Mux.scala 27:72] + wire qeff : UInt<64> @[Mux.scala 27:72] + qeff <= _T_491 @[Mux.scala 27:72] + node q1eff = bits(qeff, 63, 32) @[el2_ifu_aln_ctl.scala 294:29] + node q0eff = bits(qeff, 31, 0) @[el2_ifu_aln_ctl.scala 294:42] + node _T_492 = bits(q0sel, 0, 0) @[el2_ifu_aln_ctl.scala 296:29] + node _T_493 = bits(_T_492, 0, 0) @[el2_ifu_aln_ctl.scala 296:33] + node _T_494 = bits(q0sel, 1, 1) @[el2_ifu_aln_ctl.scala 296:53] + node _T_495 = bits(_T_494, 0, 0) @[el2_ifu_aln_ctl.scala 296:57] + node _T_496 = bits(q0eff, 31, 16) @[el2_ifu_aln_ctl.scala 296:70] + node _T_497 = mux(_T_493, q0eff, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_498 = mux(_T_495, _T_496, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_499 = or(_T_497, _T_498) @[Mux.scala 27:72] + wire _T_500 : UInt<32> @[Mux.scala 27:72] + _T_500 <= _T_499 @[Mux.scala 27:72] + q0final <= _T_500 @[el2_ifu_aln_ctl.scala 296:11] + node _T_501 = bits(q1sel, 0, 0) @[el2_ifu_aln_ctl.scala 298:29] + node _T_502 = bits(_T_501, 0, 0) @[el2_ifu_aln_ctl.scala 298:33] + node _T_503 = bits(q1eff, 15, 0) @[el2_ifu_aln_ctl.scala 298:46] + node _T_504 = bits(q1sel, 1, 1) @[el2_ifu_aln_ctl.scala 298:59] + node _T_505 = bits(_T_504, 0, 0) @[el2_ifu_aln_ctl.scala 298:63] + node _T_506 = bits(q1eff, 31, 16) @[el2_ifu_aln_ctl.scala 298:76] + node _T_507 = mux(_T_502, _T_503, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_508 = mux(_T_505, _T_506, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_509 = or(_T_507, _T_508) @[Mux.scala 27:72] + wire _T_510 : UInt<16> @[Mux.scala 27:72] + _T_510 <= _T_509 @[Mux.scala 27:72] + q1final <= _T_510 @[el2_ifu_aln_ctl.scala 298:11] + node _T_511 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 300:34] + node _T_512 = bits(_T_511, 0, 0) @[el2_ifu_aln_ctl.scala 300:38] + node _T_513 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 300:64] + node _T_514 = not(_T_513) @[el2_ifu_aln_ctl.scala 300:58] + node _T_515 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 300:75] + node _T_516 = and(_T_514, _T_515) @[el2_ifu_aln_ctl.scala 300:68] + node _T_517 = bits(_T_516, 0, 0) @[el2_ifu_aln_ctl.scala 300:80] + node _T_518 = cat(q1final, q0final) @[Cat.scala 29:58] + node _T_519 = mux(_T_512, q0final, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_520 = mux(_T_517, _T_518, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_521 = or(_T_519, _T_520) @[Mux.scala 27:72] + wire aligndata : UInt<32> @[Mux.scala 27:72] + aligndata <= _T_521 @[Mux.scala 27:72] + node _T_522 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 302:30] + node _T_523 = bits(_T_522, 0, 0) @[el2_ifu_aln_ctl.scala 302:34] + node _T_524 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 302:54] + node _T_525 = eq(_T_524, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 302:48] + node _T_526 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 302:65] + node _T_527 = and(_T_525, _T_526) @[el2_ifu_aln_ctl.scala 302:58] + node _T_528 = bits(f1val, 0, 0) @[el2_ifu_aln_ctl.scala 302:82] + node _T_529 = cat(_T_528, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_530 = mux(_T_523, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_531 = mux(_T_527, _T_529, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_532 = or(_T_530, _T_531) @[Mux.scala 27:72] + wire _T_533 : UInt<2> @[Mux.scala 27:72] + _T_533 <= _T_532 @[Mux.scala 27:72] + alignval <= _T_533 @[el2_ifu_aln_ctl.scala 302:12] + node _T_534 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 304:34] + node _T_535 = bits(_T_534, 0, 0) @[el2_ifu_aln_ctl.scala 304:38] + node _T_536 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 304:63] + node _T_537 = not(_T_536) @[el2_ifu_aln_ctl.scala 304:57] + node _T_538 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 304:74] + node _T_539 = and(_T_537, _T_538) @[el2_ifu_aln_ctl.scala 304:67] + node _T_540 = bits(_T_539, 0, 0) @[el2_ifu_aln_ctl.scala 304:79] + node _T_541 = cat(f1icaf, f0icaf) @[Cat.scala 29:58] + node _T_542 = mux(_T_535, f0icaf, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_543 = mux(_T_540, _T_541, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_544 = or(_T_542, _T_543) @[Mux.scala 27:72] + wire alignicaf : UInt<2> @[Mux.scala 27:72] + alignicaf <= _T_544 @[Mux.scala 27:72] + node _T_545 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 306:35] + node _T_546 = bits(_T_545, 0, 0) @[el2_ifu_aln_ctl.scala 306:39] + node _T_547 = bits(f0dbecc, 0, 0) @[Bitwise.scala 72:15] + node _T_548 = mux(_T_547, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_549 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 306:73] + node _T_550 = eq(_T_549, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 306:67] + node _T_551 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 306:84] + node _T_552 = and(_T_550, _T_551) @[el2_ifu_aln_ctl.scala 306:77] + node _T_553 = bits(_T_552, 0, 0) @[el2_ifu_aln_ctl.scala 306:89] + node _T_554 = cat(f1dbecc, f0dbecc) @[Cat.scala 29:58] + node _T_555 = mux(_T_546, _T_548, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_556 = mux(_T_553, _T_554, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_557 = or(_T_555, _T_556) @[Mux.scala 27:72] wire aligndbecc : UInt<2> @[Mux.scala 27:72] - aligndbecc <= _T_555 @[Mux.scala 27:72] - node _T_556 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 302:35] - node _T_557 = bits(_T_556, 0, 0) @[el2_ifu_aln_ctl.scala 302:45] - node _T_558 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 302:65] - node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 302:59] - node _T_560 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 302:76] - node _T_561 = and(_T_559, _T_560) @[el2_ifu_aln_ctl.scala 302:69] - node _T_562 = bits(_T_561, 0, 0) @[el2_ifu_aln_ctl.scala 302:81] - node _T_563 = bits(f1brend, 0, 0) @[el2_ifu_aln_ctl.scala 302:100] - node _T_564 = bits(f0brend, 0, 0) @[el2_ifu_aln_ctl.scala 302:111] - node _T_565 = cat(_T_563, _T_564) @[Cat.scala 29:58] - node _T_566 = mux(_T_557, f0brend, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_567 = mux(_T_562, _T_565, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_568 = or(_T_566, _T_567) @[Mux.scala 27:72] + aligndbecc <= _T_557 @[Mux.scala 27:72] + node _T_558 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 308:35] + node _T_559 = bits(_T_558, 0, 0) @[el2_ifu_aln_ctl.scala 308:45] + node _T_560 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 308:65] + node _T_561 = eq(_T_560, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 308:59] + node _T_562 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 308:76] + node _T_563 = and(_T_561, _T_562) @[el2_ifu_aln_ctl.scala 308:69] + node _T_564 = bits(_T_563, 0, 0) @[el2_ifu_aln_ctl.scala 308:81] + node _T_565 = bits(f1brend, 0, 0) @[el2_ifu_aln_ctl.scala 308:100] + node _T_566 = bits(f0brend, 0, 0) @[el2_ifu_aln_ctl.scala 308:111] + node _T_567 = cat(_T_565, _T_566) @[Cat.scala 29:58] + node _T_568 = mux(_T_559, f0brend, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_569 = mux(_T_564, _T_567, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_570 = or(_T_568, _T_569) @[Mux.scala 27:72] wire alignbrend : UInt<2> @[Mux.scala 27:72] - alignbrend <= _T_568 @[Mux.scala 27:72] - node _T_569 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 304:33] - node _T_570 = bits(_T_569, 0, 0) @[el2_ifu_aln_ctl.scala 304:43] - node _T_571 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 304:61] - node _T_572 = eq(_T_571, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 304:55] - node _T_573 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 304:72] - node _T_574 = and(_T_572, _T_573) @[el2_ifu_aln_ctl.scala 304:65] - node _T_575 = bits(_T_574, 0, 0) @[el2_ifu_aln_ctl.scala 304:77] - node _T_576 = bits(f1pc4, 0, 0) @[el2_ifu_aln_ctl.scala 304:94] - node _T_577 = bits(f0pc4, 0, 0) @[el2_ifu_aln_ctl.scala 304:103] - node _T_578 = cat(_T_576, _T_577) @[Cat.scala 29:58] - node _T_579 = mux(_T_570, f0pc4, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_580 = mux(_T_575, _T_578, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_581 = or(_T_579, _T_580) @[Mux.scala 27:72] + alignbrend <= _T_570 @[Mux.scala 27:72] + node _T_571 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 310:33] + node _T_572 = bits(_T_571, 0, 0) @[el2_ifu_aln_ctl.scala 310:43] + node _T_573 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 310:61] + node _T_574 = eq(_T_573, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 310:55] + node _T_575 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 310:72] + node _T_576 = and(_T_574, _T_575) @[el2_ifu_aln_ctl.scala 310:65] + node _T_577 = bits(_T_576, 0, 0) @[el2_ifu_aln_ctl.scala 310:77] + node _T_578 = bits(f1pc4, 0, 0) @[el2_ifu_aln_ctl.scala 310:94] + node _T_579 = bits(f0pc4, 0, 0) @[el2_ifu_aln_ctl.scala 310:103] + node _T_580 = cat(_T_578, _T_579) @[Cat.scala 29:58] + node _T_581 = mux(_T_572, f0pc4, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_582 = mux(_T_577, _T_580, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_583 = or(_T_581, _T_582) @[Mux.scala 27:72] wire alignpc4 : UInt<2> @[Mux.scala 27:72] - alignpc4 <= _T_581 @[Mux.scala 27:72] - node _T_582 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 306:33] - node _T_583 = bits(_T_582, 0, 0) @[el2_ifu_aln_ctl.scala 306:43] - node _T_584 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 306:61] - node _T_585 = eq(_T_584, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 306:55] - node _T_586 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 306:72] - node _T_587 = and(_T_585, _T_586) @[el2_ifu_aln_ctl.scala 306:65] - node _T_588 = bits(_T_587, 0, 0) @[el2_ifu_aln_ctl.scala 306:77] - node _T_589 = bits(f1ret, 0, 0) @[el2_ifu_aln_ctl.scala 306:94] - node _T_590 = bits(f0ret, 0, 0) @[el2_ifu_aln_ctl.scala 306:103] - node _T_591 = cat(_T_589, _T_590) @[Cat.scala 29:58] - node _T_592 = mux(_T_583, f0ret, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_593 = mux(_T_588, _T_591, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_594 = or(_T_592, _T_593) @[Mux.scala 27:72] + alignpc4 <= _T_583 @[Mux.scala 27:72] + node _T_584 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 312:33] + node _T_585 = bits(_T_584, 0, 0) @[el2_ifu_aln_ctl.scala 312:43] + node _T_586 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 312:61] + node _T_587 = eq(_T_586, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 312:55] + node _T_588 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 312:72] + node _T_589 = and(_T_587, _T_588) @[el2_ifu_aln_ctl.scala 312:65] + node _T_590 = bits(_T_589, 0, 0) @[el2_ifu_aln_ctl.scala 312:77] + node _T_591 = bits(f1ret, 0, 0) @[el2_ifu_aln_ctl.scala 312:94] + node _T_592 = bits(f0ret, 0, 0) @[el2_ifu_aln_ctl.scala 312:103] + node _T_593 = cat(_T_591, _T_592) @[Cat.scala 29:58] + node _T_594 = mux(_T_585, f0ret, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_595 = mux(_T_590, _T_593, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_596 = or(_T_594, _T_595) @[Mux.scala 27:72] wire alignret : UInt<2> @[Mux.scala 27:72] - alignret <= _T_594 @[Mux.scala 27:72] - node _T_595 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 308:33] - node _T_596 = bits(_T_595, 0, 0) @[el2_ifu_aln_ctl.scala 308:43] - node _T_597 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 308:61] - node _T_598 = eq(_T_597, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 308:55] - node _T_599 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 308:72] - node _T_600 = and(_T_598, _T_599) @[el2_ifu_aln_ctl.scala 308:65] - node _T_601 = bits(_T_600, 0, 0) @[el2_ifu_aln_ctl.scala 308:77] - node _T_602 = bits(f1way, 0, 0) @[el2_ifu_aln_ctl.scala 308:94] - node _T_603 = bits(f0way, 0, 0) @[el2_ifu_aln_ctl.scala 308:103] - node _T_604 = cat(_T_602, _T_603) @[Cat.scala 29:58] - node _T_605 = mux(_T_596, f0way, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_606 = mux(_T_601, _T_604, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_607 = or(_T_605, _T_606) @[Mux.scala 27:72] + alignret <= _T_596 @[Mux.scala 27:72] + node _T_597 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 314:33] + node _T_598 = bits(_T_597, 0, 0) @[el2_ifu_aln_ctl.scala 314:43] + node _T_599 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 314:61] + node _T_600 = eq(_T_599, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 314:55] + node _T_601 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 314:72] + node _T_602 = and(_T_600, _T_601) @[el2_ifu_aln_ctl.scala 314:65] + node _T_603 = bits(_T_602, 0, 0) @[el2_ifu_aln_ctl.scala 314:77] + node _T_604 = bits(f1way, 0, 0) @[el2_ifu_aln_ctl.scala 314:94] + node _T_605 = bits(f0way, 0, 0) @[el2_ifu_aln_ctl.scala 314:103] + node _T_606 = cat(_T_604, _T_605) @[Cat.scala 29:58] + node _T_607 = mux(_T_598, f0way, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_608 = mux(_T_603, _T_606, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_609 = or(_T_607, _T_608) @[Mux.scala 27:72] wire alignway : UInt<2> @[Mux.scala 27:72] - alignway <= _T_607 @[Mux.scala 27:72] - node _T_608 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 310:35] - node _T_609 = bits(_T_608, 0, 0) @[el2_ifu_aln_ctl.scala 310:45] - node _T_610 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 310:65] - node _T_611 = eq(_T_610, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 310:59] - node _T_612 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 310:76] - node _T_613 = and(_T_611, _T_612) @[el2_ifu_aln_ctl.scala 310:69] - node _T_614 = bits(_T_613, 0, 0) @[el2_ifu_aln_ctl.scala 310:81] - node _T_615 = bits(f1hist1, 0, 0) @[el2_ifu_aln_ctl.scala 310:100] - node _T_616 = bits(f0hist1, 0, 0) @[el2_ifu_aln_ctl.scala 310:111] - node _T_617 = cat(_T_615, _T_616) @[Cat.scala 29:58] - node _T_618 = mux(_T_609, f0hist1, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_619 = mux(_T_614, _T_617, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_620 = or(_T_618, _T_619) @[Mux.scala 27:72] + alignway <= _T_609 @[Mux.scala 27:72] + node _T_610 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 316:35] + node _T_611 = bits(_T_610, 0, 0) @[el2_ifu_aln_ctl.scala 316:45] + node _T_612 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 316:65] + node _T_613 = eq(_T_612, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 316:59] + node _T_614 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 316:76] + node _T_615 = and(_T_613, _T_614) @[el2_ifu_aln_ctl.scala 316:69] + node _T_616 = bits(_T_615, 0, 0) @[el2_ifu_aln_ctl.scala 316:81] + node _T_617 = bits(f1hist1, 0, 0) @[el2_ifu_aln_ctl.scala 316:100] + node _T_618 = bits(f0hist1, 0, 0) @[el2_ifu_aln_ctl.scala 316:111] + node _T_619 = cat(_T_617, _T_618) @[Cat.scala 29:58] + node _T_620 = mux(_T_611, f0hist1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_621 = mux(_T_616, _T_619, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_622 = or(_T_620, _T_621) @[Mux.scala 27:72] wire alignhist1 : UInt<2> @[Mux.scala 27:72] - alignhist1 <= _T_620 @[Mux.scala 27:72] - node _T_621 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 312:35] - node _T_622 = bits(_T_621, 0, 0) @[el2_ifu_aln_ctl.scala 312:45] - node _T_623 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 312:65] - node _T_624 = eq(_T_623, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 312:59] - node _T_625 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 312:76] - node _T_626 = and(_T_624, _T_625) @[el2_ifu_aln_ctl.scala 312:69] - node _T_627 = bits(_T_626, 0, 0) @[el2_ifu_aln_ctl.scala 312:81] - node _T_628 = bits(f1hist0, 0, 0) @[el2_ifu_aln_ctl.scala 312:100] - node _T_629 = bits(f0hist0, 0, 0) @[el2_ifu_aln_ctl.scala 312:111] - node _T_630 = cat(_T_628, _T_629) @[Cat.scala 29:58] - node _T_631 = mux(_T_622, f0hist0, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_632 = mux(_T_627, _T_630, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_633 = or(_T_631, _T_632) @[Mux.scala 27:72] + alignhist1 <= _T_622 @[Mux.scala 27:72] + node _T_623 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 318:35] + node _T_624 = bits(_T_623, 0, 0) @[el2_ifu_aln_ctl.scala 318:45] + node _T_625 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 318:65] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 318:59] + node _T_627 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 318:76] + node _T_628 = and(_T_626, _T_627) @[el2_ifu_aln_ctl.scala 318:69] + node _T_629 = bits(_T_628, 0, 0) @[el2_ifu_aln_ctl.scala 318:81] + node _T_630 = bits(f1hist0, 0, 0) @[el2_ifu_aln_ctl.scala 318:100] + node _T_631 = bits(f0hist0, 0, 0) @[el2_ifu_aln_ctl.scala 318:111] + node _T_632 = cat(_T_630, _T_631) @[Cat.scala 29:58] + node _T_633 = mux(_T_624, f0hist0, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_634 = mux(_T_629, _T_632, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_635 = or(_T_633, _T_634) @[Mux.scala 27:72] wire alignhist0 : UInt<2> @[Mux.scala 27:72] - alignhist0 <= _T_633 @[Mux.scala 27:72] - node _T_634 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 314:27] - node _T_635 = eq(_T_634, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 314:21] - node _T_636 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 314:38] - node alignfromf1 = and(_T_635, _T_636) @[el2_ifu_aln_ctl.scala 314:31] - wire f1pc : UInt<31> - f1pc <= UInt<1>("h00") - node _T_637 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 318:33] - node _T_638 = bits(_T_637, 0, 0) @[el2_ifu_aln_ctl.scala 318:43] - node _T_639 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 318:67] - node _T_640 = eq(_T_639, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 318:61] - node _T_641 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 318:78] - node _T_642 = and(_T_640, _T_641) @[el2_ifu_aln_ctl.scala 318:71] - node _T_643 = bits(_T_642, 0, 0) @[el2_ifu_aln_ctl.scala 318:83] - node _T_644 = mux(_T_638, f0pc_plus1, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_645 = mux(_T_643, f1pc, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_646 = or(_T_644, _T_645) @[Mux.scala 27:72] - wire secondpc : UInt<31> @[Mux.scala 27:72] - secondpc <= _T_646 @[Mux.scala 27:72] - io.ifu_i0_pc <= f0pc @[el2_ifu_aln_ctl.scala 320:16] - node _T_647 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 324:47] - node _T_648 = eq(_T_647, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 324:41] - node _T_649 = and(first4B, _T_648) @[el2_ifu_aln_ctl.scala 324:39] - node _T_650 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 324:58] - node _T_651 = and(_T_649, _T_650) @[el2_ifu_aln_ctl.scala 324:51] - node _T_652 = bits(alignicaf, 0, 0) @[el2_ifu_aln_ctl.scala 324:74] - node _T_653 = eq(_T_652, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 324:64] - node _T_654 = and(_T_651, _T_653) @[el2_ifu_aln_ctl.scala 324:62] - node _T_655 = bits(aligndbecc, 0, 0) @[el2_ifu_aln_ctl.scala 324:91] - node _T_656 = eq(_T_655, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 324:80] - node _T_657 = and(_T_654, _T_656) @[el2_ifu_aln_ctl.scala 324:78] - node _T_658 = bits(_T_657, 0, 0) @[el2_ifu_aln_ctl.scala 324:96] - node _T_659 = mux(_T_658, f1ictype, f0ictype) @[el2_ifu_aln_ctl.scala 324:29] - io.ifu_i0_icaf_type <= _T_659 @[el2_ifu_aln_ctl.scala 324:23] - node _T_660 = bits(alignicaf, 1, 1) @[el2_ifu_aln_ctl.scala 326:27] - node _T_661 = bits(aligndbecc, 1, 1) @[el2_ifu_aln_ctl.scala 326:43] - node icaf_eff = or(_T_660, _T_661) @[el2_ifu_aln_ctl.scala 326:31] - node _T_662 = and(first4B, icaf_eff) @[el2_ifu_aln_ctl.scala 328:32] - node _T_663 = and(_T_662, alignfromf1) @[el2_ifu_aln_ctl.scala 328:43] - io.ifu_i0_icaf_f1 <= _T_663 @[el2_ifu_aln_ctl.scala 328:21] - node _T_664 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 330:40] - node _T_665 = orr(aligndbecc) @[el2_ifu_aln_ctl.scala 330:59] - node _T_666 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 330:72] - node _T_667 = bits(aligndbecc, 0, 0) @[el2_ifu_aln_ctl.scala 330:90] - node _T_668 = mux(_T_664, _T_665, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_669 = mux(_T_666, _T_667, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_670 = or(_T_668, _T_669) @[Mux.scala 27:72] - wire _T_671 : UInt<1> @[Mux.scala 27:72] - _T_671 <= _T_670 @[Mux.scala 27:72] - io.ifu_i0_dbecc <= _T_671 @[el2_ifu_aln_ctl.scala 330:19] - node _T_672 = bits(f0pc, 8, 1) @[el2_lib.scala 191:12] - node _T_673 = bits(f0pc, 16, 9) @[el2_lib.scala 191:50] - node _T_674 = xor(_T_672, _T_673) @[el2_lib.scala 191:46] - node _T_675 = bits(f0pc, 24, 17) @[el2_lib.scala 191:88] - node firstpc_hash = xor(_T_674, _T_675) @[el2_lib.scala 191:84] - node _T_676 = bits(secondpc, 8, 1) @[el2_lib.scala 191:12] - node _T_677 = bits(secondpc, 16, 9) @[el2_lib.scala 191:50] - node _T_678 = xor(_T_676, _T_677) @[el2_lib.scala 191:46] - node _T_679 = bits(secondpc, 24, 17) @[el2_lib.scala 191:88] - node secondpc_hash = xor(_T_678, _T_679) @[el2_lib.scala 191:84] - node _T_680 = bits(f0pc, 13, 9) @[el2_lib.scala 182:32] - node _T_681 = bits(f0pc, 18, 14) @[el2_lib.scala 182:32] - node _T_682 = bits(f0pc, 23, 19) @[el2_lib.scala 182:32] - wire _T_683 : UInt<5>[3] @[el2_lib.scala 182:24] - _T_683[0] <= _T_680 @[el2_lib.scala 182:24] - _T_683[1] <= _T_681 @[el2_lib.scala 182:24] - _T_683[2] <= _T_682 @[el2_lib.scala 182:24] - node _T_684 = xor(_T_683[0], _T_683[1]) @[el2_lib.scala 182:111] - node firstbrtag_hash = xor(_T_684, _T_683[2]) @[el2_lib.scala 182:111] - node _T_685 = bits(secondpc, 13, 9) @[el2_lib.scala 182:32] - node _T_686 = bits(secondpc, 18, 14) @[el2_lib.scala 182:32] - node _T_687 = bits(secondpc, 23, 19) @[el2_lib.scala 182:32] - wire _T_688 : UInt<5>[3] @[el2_lib.scala 182:24] - _T_688[0] <= _T_685 @[el2_lib.scala 182:24] - _T_688[1] <= _T_686 @[el2_lib.scala 182:24] - _T_688[2] <= _T_687 @[el2_lib.scala 182:24] - node _T_689 = xor(_T_688[0], _T_688[1]) @[el2_lib.scala 182:111] - node secondbrtag_hash = xor(_T_689, _T_688[2]) @[el2_lib.scala 182:111] - node _T_690 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 340:42] - node _T_691 = and(first2B, _T_690) @[el2_ifu_aln_ctl.scala 340:30] - node _T_692 = bits(alignbrend, 1, 1) @[el2_ifu_aln_ctl.scala 340:70] - node _T_693 = and(first4B, _T_692) @[el2_ifu_aln_ctl.scala 340:58] - node _T_694 = or(_T_691, _T_693) @[el2_ifu_aln_ctl.scala 340:47] - node _T_695 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 340:96] - node _T_696 = and(first4B, _T_695) @[el2_ifu_aln_ctl.scala 340:86] - node _T_697 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 340:112] - node _T_698 = and(_T_696, _T_697) @[el2_ifu_aln_ctl.scala 340:100] - node _T_699 = or(_T_694, _T_698) @[el2_ifu_aln_ctl.scala 340:75] - io.i0_brp.valid <= _T_699 @[el2_ifu_aln_ctl.scala 340:19] - node _T_700 = bits(alignret, 0, 0) @[el2_ifu_aln_ctl.scala 342:39] - node _T_701 = and(first2B, _T_700) @[el2_ifu_aln_ctl.scala 342:29] - node _T_702 = bits(alignret, 1, 1) @[el2_ifu_aln_ctl.scala 342:65] - node _T_703 = and(first4B, _T_702) @[el2_ifu_aln_ctl.scala 342:55] - node _T_704 = or(_T_701, _T_703) @[el2_ifu_aln_ctl.scala 342:44] - io.i0_brp.ret <= _T_704 @[el2_ifu_aln_ctl.scala 342:17] - node _T_705 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 344:45] - node _T_706 = or(first2B, _T_705) @[el2_ifu_aln_ctl.scala 344:33] - node _T_707 = bits(_T_706, 0, 0) @[el2_ifu_aln_ctl.scala 344:50] - node _T_708 = bits(alignway, 0, 0) @[el2_ifu_aln_ctl.scala 344:66] - node _T_709 = bits(alignway, 1, 1) @[el2_ifu_aln_ctl.scala 344:80] - node _T_710 = mux(_T_707, _T_708, _T_709) @[el2_ifu_aln_ctl.scala 344:23] - io.i0_brp.way <= _T_710 @[el2_ifu_aln_ctl.scala 344:17] - node _T_711 = bits(alignhist1, 0, 0) @[el2_ifu_aln_ctl.scala 345:46] - node _T_712 = and(first2B, _T_711) @[el2_ifu_aln_ctl.scala 345:34] - node _T_713 = bits(alignhist1, 1, 1) @[el2_ifu_aln_ctl.scala 345:74] - node _T_714 = and(first4B, _T_713) @[el2_ifu_aln_ctl.scala 345:62] - node _T_715 = or(_T_712, _T_714) @[el2_ifu_aln_ctl.scala 345:51] - node _T_716 = bits(alignhist0, 0, 0) @[el2_ifu_aln_ctl.scala 346:26] - node _T_717 = and(first2B, _T_716) @[el2_ifu_aln_ctl.scala 346:14] - node _T_718 = bits(alignhist0, 1, 1) @[el2_ifu_aln_ctl.scala 346:54] - node _T_719 = and(first4B, _T_718) @[el2_ifu_aln_ctl.scala 346:42] - node _T_720 = or(_T_717, _T_719) @[el2_ifu_aln_ctl.scala 346:31] - node _T_721 = cat(_T_715, _T_720) @[Cat.scala 29:58] - io.i0_brp.hist <= _T_721 @[el2_ifu_aln_ctl.scala 345:18] - node _T_722 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 348:37] - node _T_723 = bits(_T_722, 0, 0) @[el2_ifu_aln_ctl.scala 348:52] - node _T_724 = mux(_T_723, f1poffset, f0poffset) @[el2_ifu_aln_ctl.scala 348:27] - io.i0_brp.toffset <= _T_724 @[el2_ifu_aln_ctl.scala 348:21] - node _T_725 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 350:35] - node _T_726 = bits(_T_725, 0, 0) @[el2_ifu_aln_ctl.scala 350:50] - node _T_727 = mux(_T_726, f1prett, f0prett) @[el2_ifu_aln_ctl.scala 350:25] - io.i0_brp.prett <= _T_727 @[el2_ifu_aln_ctl.scala 350:19] - node _T_728 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 352:51] - node _T_729 = and(first4B, _T_728) @[el2_ifu_aln_ctl.scala 352:41] - node _T_730 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 352:67] - node _T_731 = and(_T_729, _T_730) @[el2_ifu_aln_ctl.scala 352:55] - io.i0_brp.br_start_error <= _T_731 @[el2_ifu_aln_ctl.scala 352:29] - node _T_732 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 354:57] - node _T_733 = or(first2B, _T_732) @[el2_ifu_aln_ctl.scala 354:45] - node _T_734 = bits(_T_733, 0, 0) @[el2_ifu_aln_ctl.scala 354:62] - node _T_735 = bits(f0pc, 1, 1) @[el2_ifu_aln_ctl.scala 354:77] - node _T_736 = bits(secondpc, 1, 1) @[el2_ifu_aln_ctl.scala 354:90] - node _T_737 = mux(_T_734, _T_735, _T_736) @[el2_ifu_aln_ctl.scala 354:35] - io.i0_brp.bank <= _T_737 @[el2_ifu_aln_ctl.scala 354:29] - node _T_738 = bits(alignpc4, 0, 0) @[el2_ifu_aln_ctl.scala 356:39] - node _T_739 = and(first2B, _T_738) @[el2_ifu_aln_ctl.scala 356:29] - node _T_740 = bits(alignpc4, 1, 1) @[el2_ifu_aln_ctl.scala 356:65] - node _T_741 = and(first4B, _T_740) @[el2_ifu_aln_ctl.scala 356:55] - node i0_brp_pc4 = or(_T_739, _T_741) @[el2_ifu_aln_ctl.scala 356:44] - node _T_742 = and(io.i0_brp.valid, i0_brp_pc4) @[el2_ifu_aln_ctl.scala 358:42] - node _T_743 = and(_T_742, first2B) @[el2_ifu_aln_ctl.scala 358:56] - node _T_744 = not(i0_brp_pc4) @[el2_ifu_aln_ctl.scala 358:89] - node _T_745 = and(io.i0_brp.valid, _T_744) @[el2_ifu_aln_ctl.scala 358:87] - node _T_746 = and(_T_745, first4B) @[el2_ifu_aln_ctl.scala 358:101] - node _T_747 = or(_T_743, _T_746) @[el2_ifu_aln_ctl.scala 358:68] - io.i0_brp.br_error <= _T_747 @[el2_ifu_aln_ctl.scala 358:22] - node _T_748 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 361:50] - node _T_749 = or(first2B, _T_748) @[el2_ifu_aln_ctl.scala 361:38] - node _T_750 = bits(_T_749, 0, 0) @[el2_ifu_aln_ctl.scala 361:55] - node _T_751 = mux(_T_750, firstpc_hash, secondpc_hash) @[el2_ifu_aln_ctl.scala 361:28] - io.ifu_i0_bp_index <= _T_751 @[el2_ifu_aln_ctl.scala 361:22] - node _T_752 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 363:37] - node _T_753 = bits(_T_752, 0, 0) @[el2_ifu_aln_ctl.scala 363:52] - node _T_754 = mux(_T_753, f1fghr, f0fghr) @[el2_ifu_aln_ctl.scala 363:27] - io.ifu_i0_bp_fghr <= _T_754 @[el2_ifu_aln_ctl.scala 363:21] - node _T_755 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 365:49] - node _T_756 = or(first2B, _T_755) @[el2_ifu_aln_ctl.scala 365:37] - node _T_757 = bits(_T_756, 0, 0) @[el2_ifu_aln_ctl.scala 365:54] - node _T_758 = mux(_T_757, firstbrtag_hash, secondbrtag_hash) @[el2_ifu_aln_ctl.scala 365:27] - io.ifu_i0_bp_btag <= _T_758 @[el2_ifu_aln_ctl.scala 365:21] - node _T_759 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 367:44] - reg _T_760 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_759 : @[Reg.scala 28:19] - _T_760 <= brdata_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - brdata2 <= _T_760 @[el2_ifu_aln_ctl.scala 367:11] - node _T_761 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 368:44] - reg _T_762 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_761 : @[Reg.scala 28:19] - _T_762 <= brdata_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - brdata1 <= _T_762 @[el2_ifu_aln_ctl.scala 368:11] - node _T_763 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 369:44] - reg _T_764 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_763 : @[Reg.scala 28:19] - _T_764 <= brdata_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - brdata0 <= _T_764 @[el2_ifu_aln_ctl.scala 369:11] - node _T_765 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 371:45] - reg _T_766 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_765 : @[Reg.scala 28:19] - _T_766 <= misc_data_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - misc2 <= _T_766 @[el2_ifu_aln_ctl.scala 371:9] - node _T_767 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 372:45] - reg _T_768 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_767 : @[Reg.scala 28:19] - _T_768 <= misc_data_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - misc1 <= _T_768 @[el2_ifu_aln_ctl.scala 372:9] - node _T_769 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 373:45] - reg _T_770 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_769 : @[Reg.scala 28:19] - _T_770 <= misc_data_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - misc0 <= _T_770 @[el2_ifu_aln_ctl.scala 373:9] - node _T_771 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 375:49] - reg _T_772 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_771 : @[Reg.scala 28:19] - _T_772 <= io.ifu_fetch_data_f @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - q2 <= _T_772 @[el2_ifu_aln_ctl.scala 375:6] - node _T_773 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 376:49] - reg _T_774 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_773 : @[Reg.scala 28:19] - _T_774 <= io.ifu_fetch_data_f @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - q1 <= _T_774 @[el2_ifu_aln_ctl.scala 376:6] - node _T_775 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 377:49] - reg _T_776 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_775 : @[Reg.scala 28:19] - _T_776 <= io.ifu_fetch_data_f @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - q0 <= _T_776 @[el2_ifu_aln_ctl.scala 377:6] - node _T_777 = bits(f2_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 379:52] - reg _T_778 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_777 : @[Reg.scala 28:19] - _T_778 <= io.ifu_fetch_pc @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - f2pc <= _T_778 @[el2_ifu_aln_ctl.scala 379:8] - node _T_779 = bits(f1_shift_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 380:50] - reg _T_780 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_779 : @[Reg.scala 28:19] - _T_780 <= f1pc_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - f2pc <= _T_780 @[el2_ifu_aln_ctl.scala 380:8] - node _T_781 = bits(f0_shift_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 381:50] - reg _T_782 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_781 : @[Reg.scala 28:19] - _T_782 <= f0pc_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - f2pc <= _T_782 @[el2_ifu_aln_ctl.scala 381:8] + alignhist0 <= _T_635 @[Mux.scala 27:72] + node _T_636 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 320:27] + node _T_637 = eq(_T_636, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 320:21] + node _T_638 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 320:38] + node alignfromf1 = and(_T_637, _T_638) @[el2_ifu_aln_ctl.scala 320:31] + node _T_639 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 322:33] + node _T_640 = bits(_T_639, 0, 0) @[el2_ifu_aln_ctl.scala 322:43] + node _T_641 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 322:67] + node _T_642 = eq(_T_641, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 322:61] + node _T_643 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 322:78] + node _T_644 = and(_T_642, _T_643) @[el2_ifu_aln_ctl.scala 322:71] + node _T_645 = bits(_T_644, 0, 0) @[el2_ifu_aln_ctl.scala 322:83] + node _T_646 = mux(_T_640, f0pc_plus1, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_647 = mux(_T_645, f1pc, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_648 = or(_T_646, _T_647) @[Mux.scala 27:72] + wire secondpc : UInt @[Mux.scala 27:72] + secondpc <= _T_648 @[Mux.scala 27:72] + io.ifu_i0_pc <= f0pc @[el2_ifu_aln_ctl.scala 324:16] + io.ifu_i0_pc4 <= first4B @[el2_ifu_aln_ctl.scala 328:17] + node _T_649 = bits(aligndata, 15, 0) @[el2_ifu_aln_ctl.scala 330:31] + io.ifu_i0_cinst <= _T_649 @[el2_ifu_aln_ctl.scala 330:19] + node _T_650 = bits(aligndata, 1, 0) @[el2_ifu_aln_ctl.scala 332:23] + node _T_651 = eq(_T_650, UInt<2>("h03")) @[el2_ifu_aln_ctl.scala 332:29] + first4B <= _T_651 @[el2_ifu_aln_ctl.scala 332:11] + node first2B = not(first4B) @[el2_ifu_aln_ctl.scala 334:17] + node _T_652 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 336:40] + node _T_653 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 336:58] + node _T_654 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 336:71] + node _T_655 = bits(alignval, 0, 0) @[el2_ifu_aln_ctl.scala 336:89] + node _T_656 = mux(_T_652, _T_653, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_657 = mux(_T_654, _T_655, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_658 = or(_T_656, _T_657) @[Mux.scala 27:72] + wire _T_659 : UInt<1> @[Mux.scala 27:72] + _T_659 <= _T_658 @[Mux.scala 27:72] + io.ifu_i0_valid <= _T_659 @[el2_ifu_aln_ctl.scala 336:19] + node _T_660 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 338:39] + node _T_661 = orr(alignicaf) @[el2_ifu_aln_ctl.scala 338:59] + node _T_662 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 338:72] + node _T_663 = bits(alignicaf, 0, 0) @[el2_ifu_aln_ctl.scala 338:91] + node _T_664 = mux(_T_660, _T_661, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_665 = mux(_T_662, _T_663, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_666 = or(_T_664, _T_665) @[Mux.scala 27:72] + wire _T_667 : UInt<1> @[Mux.scala 27:72] + _T_667 <= _T_666 @[Mux.scala 27:72] + io.ifu_i0_icaf <= _T_667 @[el2_ifu_aln_ctl.scala 338:18] + node _T_668 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 340:47] + node _T_669 = eq(_T_668, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 340:41] + node _T_670 = and(first4B, _T_669) @[el2_ifu_aln_ctl.scala 340:39] + node _T_671 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 340:58] + node _T_672 = and(_T_670, _T_671) @[el2_ifu_aln_ctl.scala 340:51] + node _T_673 = bits(alignicaf, 0, 0) @[el2_ifu_aln_ctl.scala 340:74] + node _T_674 = eq(_T_673, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 340:64] + node _T_675 = and(_T_672, _T_674) @[el2_ifu_aln_ctl.scala 340:62] + node _T_676 = bits(aligndbecc, 0, 0) @[el2_ifu_aln_ctl.scala 340:91] + node _T_677 = eq(_T_676, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 340:80] + node _T_678 = and(_T_675, _T_677) @[el2_ifu_aln_ctl.scala 340:78] + node _T_679 = bits(_T_678, 0, 0) @[el2_ifu_aln_ctl.scala 340:96] + node _T_680 = mux(_T_679, f1ictype, f0ictype) @[el2_ifu_aln_ctl.scala 340:29] + io.ifu_i0_icaf_type <= _T_680 @[el2_ifu_aln_ctl.scala 340:23] + node _T_681 = bits(alignicaf, 1, 1) @[el2_ifu_aln_ctl.scala 342:27] + node _T_682 = bits(aligndbecc, 1, 1) @[el2_ifu_aln_ctl.scala 342:43] + node icaf_eff = or(_T_681, _T_682) @[el2_ifu_aln_ctl.scala 342:31] + node _T_683 = and(first4B, icaf_eff) @[el2_ifu_aln_ctl.scala 344:32] + node _T_684 = and(_T_683, alignfromf1) @[el2_ifu_aln_ctl.scala 344:43] + io.ifu_i0_icaf_f1 <= _T_684 @[el2_ifu_aln_ctl.scala 344:21] + node _T_685 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 346:40] + node _T_686 = orr(aligndbecc) @[el2_ifu_aln_ctl.scala 346:59] + node _T_687 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 346:72] + node _T_688 = bits(aligndbecc, 0, 0) @[el2_ifu_aln_ctl.scala 346:90] + node _T_689 = mux(_T_685, _T_686, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_690 = mux(_T_687, _T_688, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_691 = or(_T_689, _T_690) @[Mux.scala 27:72] + wire _T_692 : UInt<1> @[Mux.scala 27:72] + _T_692 <= _T_691 @[Mux.scala 27:72] + io.ifu_i0_dbecc <= _T_692 @[el2_ifu_aln_ctl.scala 346:19] + inst decompressed of el2_ifu_compress_ctl @[el2_ifu_aln_ctl.scala 350:28] + decompressed.clock <= clock + decompressed.reset <= reset + node _T_693 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 352:40] + node _T_694 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 352:66] + node _T_695 = mux(_T_693, aligndata, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_696 = mux(_T_694, decompressed.io.dout, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_697 = or(_T_695, _T_696) @[Mux.scala 27:72] + wire _T_698 : UInt<32> @[Mux.scala 27:72] + _T_698 <= _T_697 @[Mux.scala 27:72] + io.ifu_i0_instr <= _T_698 @[el2_ifu_aln_ctl.scala 352:19] + node _T_699 = bits(f0pc, 8, 1) @[el2_lib.scala 191:12] + node _T_700 = bits(f0pc, 16, 9) @[el2_lib.scala 191:50] + node _T_701 = xor(_T_699, _T_700) @[el2_lib.scala 191:46] + node _T_702 = bits(f0pc, 24, 17) @[el2_lib.scala 191:88] + node firstpc_hash = xor(_T_701, _T_702) @[el2_lib.scala 191:84] + node _T_703 = bits(secondpc, 8, 1) @[el2_lib.scala 191:12] + node _T_704 = bits(secondpc, 16, 9) @[el2_lib.scala 191:50] + node _T_705 = xor(_T_703, _T_704) @[el2_lib.scala 191:46] + node _T_706 = bits(secondpc, 24, 17) @[el2_lib.scala 191:88] + node secondpc_hash = xor(_T_705, _T_706) @[el2_lib.scala 191:84] + node _T_707 = bits(f0pc, 13, 9) @[el2_lib.scala 182:32] + node _T_708 = bits(f0pc, 18, 14) @[el2_lib.scala 182:32] + node _T_709 = bits(f0pc, 23, 19) @[el2_lib.scala 182:32] + wire _T_710 : UInt<5>[3] @[el2_lib.scala 182:24] + _T_710[0] <= _T_707 @[el2_lib.scala 182:24] + _T_710[1] <= _T_708 @[el2_lib.scala 182:24] + _T_710[2] <= _T_709 @[el2_lib.scala 182:24] + node _T_711 = xor(_T_710[0], _T_710[1]) @[el2_lib.scala 182:111] + node firstbrtag_hash = xor(_T_711, _T_710[2]) @[el2_lib.scala 182:111] + node _T_712 = bits(secondpc, 13, 9) @[el2_lib.scala 182:32] + node _T_713 = bits(secondpc, 18, 14) @[el2_lib.scala 182:32] + node _T_714 = bits(secondpc, 23, 19) @[el2_lib.scala 182:32] + wire _T_715 : UInt<5>[3] @[el2_lib.scala 182:24] + _T_715[0] <= _T_712 @[el2_lib.scala 182:24] + _T_715[1] <= _T_713 @[el2_lib.scala 182:24] + _T_715[2] <= _T_714 @[el2_lib.scala 182:24] + node _T_716 = xor(_T_715[0], _T_715[1]) @[el2_lib.scala 182:111] + node secondbrtag_hash = xor(_T_716, _T_715[2]) @[el2_lib.scala 182:111] + node _T_717 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 362:42] + node _T_718 = and(first2B, _T_717) @[el2_ifu_aln_ctl.scala 362:30] + node _T_719 = bits(alignbrend, 1, 1) @[el2_ifu_aln_ctl.scala 362:70] + node _T_720 = and(first4B, _T_719) @[el2_ifu_aln_ctl.scala 362:58] + node _T_721 = or(_T_718, _T_720) @[el2_ifu_aln_ctl.scala 362:47] + node _T_722 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 362:96] + node _T_723 = and(first4B, _T_722) @[el2_ifu_aln_ctl.scala 362:86] + node _T_724 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 362:112] + node _T_725 = and(_T_723, _T_724) @[el2_ifu_aln_ctl.scala 362:100] + node _T_726 = or(_T_721, _T_725) @[el2_ifu_aln_ctl.scala 362:75] + io.i0_brp.valid <= _T_726 @[el2_ifu_aln_ctl.scala 362:19] + node _T_727 = bits(alignret, 0, 0) @[el2_ifu_aln_ctl.scala 364:39] + node _T_728 = and(first2B, _T_727) @[el2_ifu_aln_ctl.scala 364:29] + node _T_729 = bits(alignret, 1, 1) @[el2_ifu_aln_ctl.scala 364:65] + node _T_730 = and(first4B, _T_729) @[el2_ifu_aln_ctl.scala 364:55] + node _T_731 = or(_T_728, _T_730) @[el2_ifu_aln_ctl.scala 364:44] + io.i0_brp.ret <= _T_731 @[el2_ifu_aln_ctl.scala 364:17] + node _T_732 = bits(alignpc4, 0, 0) @[el2_ifu_aln_ctl.scala 366:39] + node _T_733 = and(first2B, _T_732) @[el2_ifu_aln_ctl.scala 366:29] + node _T_734 = bits(alignpc4, 1, 1) @[el2_ifu_aln_ctl.scala 366:65] + node _T_735 = and(first4B, _T_734) @[el2_ifu_aln_ctl.scala 366:55] + node i0_brp_pc4 = or(_T_733, _T_735) @[el2_ifu_aln_ctl.scala 366:44] + node _T_736 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 368:45] + node _T_737 = or(first2B, _T_736) @[el2_ifu_aln_ctl.scala 368:33] + node _T_738 = bits(_T_737, 0, 0) @[el2_ifu_aln_ctl.scala 368:50] + node _T_739 = bits(alignway, 0, 0) @[el2_ifu_aln_ctl.scala 368:66] + node _T_740 = bits(alignway, 1, 1) @[el2_ifu_aln_ctl.scala 368:80] + node _T_741 = mux(_T_738, _T_739, _T_740) @[el2_ifu_aln_ctl.scala 368:23] + io.i0_brp.way <= _T_741 @[el2_ifu_aln_ctl.scala 368:17] + node _T_742 = bits(alignhist1, 0, 0) @[el2_ifu_aln_ctl.scala 370:46] + node _T_743 = and(first2B, _T_742) @[el2_ifu_aln_ctl.scala 370:34] + node _T_744 = bits(alignhist1, 1, 1) @[el2_ifu_aln_ctl.scala 370:74] + node _T_745 = and(first4B, _T_744) @[el2_ifu_aln_ctl.scala 370:62] + node _T_746 = or(_T_743, _T_745) @[el2_ifu_aln_ctl.scala 370:51] + node _T_747 = bits(alignhist0, 0, 0) @[el2_ifu_aln_ctl.scala 371:26] + node _T_748 = and(first2B, _T_747) @[el2_ifu_aln_ctl.scala 371:14] + node _T_749 = bits(alignhist0, 1, 1) @[el2_ifu_aln_ctl.scala 371:54] + node _T_750 = and(first4B, _T_749) @[el2_ifu_aln_ctl.scala 371:42] + node _T_751 = or(_T_748, _T_750) @[el2_ifu_aln_ctl.scala 371:31] + node _T_752 = cat(_T_746, _T_751) @[Cat.scala 29:58] + io.i0_brp.hist <= _T_752 @[el2_ifu_aln_ctl.scala 370:18] + node i0_ends_f1 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 373:28] + node _T_753 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 374:39] + node _T_754 = mux(_T_753, f1poffset, f0poffset) @[el2_ifu_aln_ctl.scala 374:27] + io.i0_brp.toffset <= _T_754 @[el2_ifu_aln_ctl.scala 374:21] + node _T_755 = bits(i0_ends_f1, 0, 0) @[el2_ifu_aln_ctl.scala 376:37] + node _T_756 = mux(_T_755, f1prett, f0prett) @[el2_ifu_aln_ctl.scala 376:25] + io.i0_brp.prett <= _T_756 @[el2_ifu_aln_ctl.scala 376:19] + node _T_757 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 378:51] + node _T_758 = and(first4B, _T_757) @[el2_ifu_aln_ctl.scala 378:41] + node _T_759 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 378:67] + node _T_760 = and(_T_758, _T_759) @[el2_ifu_aln_ctl.scala 378:55] + io.i0_brp.br_start_error <= _T_760 @[el2_ifu_aln_ctl.scala 378:29] + node _T_761 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 380:57] + node _T_762 = or(first2B, _T_761) @[el2_ifu_aln_ctl.scala 380:45] + node _T_763 = bits(_T_762, 0, 0) @[el2_ifu_aln_ctl.scala 380:62] + node _T_764 = bits(f0pc, 1, 1) @[el2_ifu_aln_ctl.scala 380:77] + node _T_765 = bits(secondpc, 1, 1) @[el2_ifu_aln_ctl.scala 380:90] + node _T_766 = mux(_T_763, _T_764, _T_765) @[el2_ifu_aln_ctl.scala 380:35] + io.i0_brp.bank <= _T_766 @[el2_ifu_aln_ctl.scala 380:29] + node _T_767 = and(io.i0_brp.valid, i0_brp_pc4) @[el2_ifu_aln_ctl.scala 382:42] + node _T_768 = and(_T_767, first2B) @[el2_ifu_aln_ctl.scala 382:56] + node _T_769 = eq(i0_brp_pc4, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 382:89] + node _T_770 = and(io.i0_brp.valid, _T_769) @[el2_ifu_aln_ctl.scala 382:87] + node _T_771 = and(_T_770, first4B) @[el2_ifu_aln_ctl.scala 382:101] + node _T_772 = or(_T_768, _T_771) @[el2_ifu_aln_ctl.scala 382:68] + io.i0_brp.br_error <= _T_772 @[el2_ifu_aln_ctl.scala 382:22] + node _T_773 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 384:50] + node _T_774 = or(first2B, _T_773) @[el2_ifu_aln_ctl.scala 384:38] + node _T_775 = bits(_T_774, 0, 0) @[el2_ifu_aln_ctl.scala 384:55] + node _T_776 = mux(_T_775, firstpc_hash, secondpc_hash) @[el2_ifu_aln_ctl.scala 384:28] + io.ifu_i0_bp_index <= _T_776 @[el2_ifu_aln_ctl.scala 384:22] + node _T_777 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 386:37] + node _T_778 = bits(_T_777, 0, 0) @[el2_ifu_aln_ctl.scala 386:52] + node _T_779 = mux(_T_778, f1fghr, f0fghr) @[el2_ifu_aln_ctl.scala 386:27] + io.ifu_i0_bp_fghr <= _T_779 @[el2_ifu_aln_ctl.scala 386:21] + node _T_780 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 388:49] + node _T_781 = or(first2B, _T_780) @[el2_ifu_aln_ctl.scala 388:37] + node _T_782 = bits(_T_781, 0, 0) @[el2_ifu_aln_ctl.scala 388:54] + node _T_783 = mux(_T_782, firstbrtag_hash, secondbrtag_hash) @[el2_ifu_aln_ctl.scala 388:27] + io.ifu_i0_bp_btag <= _T_783 @[el2_ifu_aln_ctl.scala 388:21] + decompressed.io.din <= aligndata @[el2_ifu_aln_ctl.scala 390:23] + node _T_784 = not(error_stall) @[el2_ifu_aln_ctl.scala 392:39] + node i0_shift = and(io.dec_i0_decode_d, _T_784) @[el2_ifu_aln_ctl.scala 392:37] + io.ifu_pmu_instr_aligned <= i0_shift @[el2_ifu_aln_ctl.scala 394:28] + node _T_785 = and(i0_shift, first2B) @[el2_ifu_aln_ctl.scala 396:24] + shift_2B <= _T_785 @[el2_ifu_aln_ctl.scala 396:12] + node _T_786 = and(i0_shift, first4B) @[el2_ifu_aln_ctl.scala 397:24] + shift_4B <= _T_786 @[el2_ifu_aln_ctl.scala 397:12] + node _T_787 = bits(shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 399:37] + node _T_788 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 399:52] + node _T_789 = bits(shift_4B, 0, 0) @[el2_ifu_aln_ctl.scala 399:66] + node _T_790 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 399:83] + node _T_791 = eq(_T_790, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 399:77] + node _T_792 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 399:94] + node _T_793 = and(_T_791, _T_792) @[el2_ifu_aln_ctl.scala 399:87] + node _T_794 = mux(_T_787, _T_788, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_795 = mux(_T_789, _T_793, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_796 = or(_T_794, _T_795) @[Mux.scala 27:72] + wire _T_797 : UInt<1> @[Mux.scala 27:72] + _T_797 <= _T_796 @[Mux.scala 27:72] + f0_shift_2B <= _T_797 @[el2_ifu_aln_ctl.scala 399:15] + node _T_798 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 400:24] + node _T_799 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 400:36] + node _T_800 = eq(_T_799, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 400:30] + node _T_801 = and(_T_798, _T_800) @[el2_ifu_aln_ctl.scala 400:28] + node _T_802 = and(_T_801, shift_4B) @[el2_ifu_aln_ctl.scala 400:40] + f1_shift_2B <= _T_802 @[el2_ifu_aln_ctl.scala 400:15] diff --git a/el2_ifu_aln_ctl.v b/el2_ifu_aln_ctl.v index a4465583..d9bf4ed6 100644 --- a/el2_ifu_aln_ctl.v +++ b/el2_ifu_aln_ctl.v @@ -529,7 +529,7 @@ module el2_ifu_aln_ctl( input io_dec_i0_decode_d, input [31:0] io_ifu_fetch_data_f, input [1:0] io_ifu_fetch_val, - input [31:0] io_ifu_fetch_pc, + input [30:0] io_ifu_fetch_pc, output io_ifu_i0_valid, output io_ifu_i0_icaf, output [1:0] io_ifu_i0_icaf_type, @@ -565,189 +565,287 @@ module el2_ifu_aln_ctl( reg [31:0] _RAND_6; reg [31:0] _RAND_7; reg [31:0] _RAND_8; - reg [63:0] _RAND_9; - reg [63:0] _RAND_10; - reg [63:0] _RAND_11; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; reg [31:0] _RAND_12; reg [31:0] _RAND_13; reg [31:0] _RAND_14; reg [31:0] _RAND_15; reg [31:0] _RAND_16; reg [31:0] _RAND_17; + reg [63:0] _RAND_18; + reg [63:0] _RAND_19; + reg [63:0] _RAND_20; `endif // RANDOMIZE_REG_INIT - wire [15:0] decompressed_io_din; // @[el2_ifu_aln_ctl.scala 99:28] - wire [31:0] decompressed_io_dout; // @[el2_ifu_aln_ctl.scala 99:28] - reg error_stall; // @[el2_ifu_aln_ctl.scala 89:54] - reg [1:0] f0val; // @[el2_ifu_aln_ctl.scala 90:48] - wire _T = error_stall | io_ifu_async_error_start; // @[el2_ifu_aln_ctl.scala 91:34] - wire _T_1 = ~io_exu_flush_final; // @[el2_ifu_aln_ctl.scala 91:64] - wire error_stall_in = _T & _T_1; // @[el2_ifu_aln_ctl.scala 91:62] - wire _T_3 = ~error_stall; // @[el2_ifu_aln_ctl.scala 93:39] - wire i0_shift = io_dec_i0_decode_d & _T_3; // @[el2_ifu_aln_ctl.scala 93:37] - wire _T_7 = ~f0val[1]; // @[el2_ifu_aln_ctl.scala 97:58] - wire _T_9 = _T_7 & f0val[0]; // @[el2_ifu_aln_ctl.scala 97:68] - reg [1:0] rdptr; // @[el2_ifu_aln_ctl.scala 124:48] - wire _T_252 = rdptr == 2'h0; // @[el2_ifu_aln_ctl.scala 178:32] - reg q1off; // @[el2_ifu_aln_ctl.scala 131:48] - wire _T_255 = _T_252 & q1off; // @[Mux.scala 27:72] - wire _T_253 = rdptr == 2'h1; // @[el2_ifu_aln_ctl.scala 178:57] - reg q2off; // @[el2_ifu_aln_ctl.scala 130:48] - wire _T_256 = _T_253 & q2off; // @[Mux.scala 27:72] - wire _T_258 = _T_255 | _T_256; // @[Mux.scala 27:72] - wire _T_254 = rdptr == 2'h2; // @[el2_ifu_aln_ctl.scala 178:83] - reg q0off; // @[el2_ifu_aln_ctl.scala 132:48] - wire _T_257 = _T_254 & q0off; // @[Mux.scala 27:72] - wire q1ptr = _T_258 | _T_257; // @[Mux.scala 27:72] - wire _T_261 = ~q1ptr; // @[el2_ifu_aln_ctl.scala 182:26] - wire [1:0] q1sel = {q1ptr,_T_261}; // @[Cat.scala 29:58] - wire [2:0] qren = {_T_254,_T_253,_T_252}; // @[Cat.scala 29:58] + wire [15:0] decompressed_io_din; // @[el2_ifu_aln_ctl.scala 350:28] + wire [31:0] decompressed_io_dout; // @[el2_ifu_aln_ctl.scala 350:28] + reg error_stall; // @[el2_ifu_aln_ctl.scala 112:51] + wire _T = error_stall | io_ifu_async_error_start; // @[el2_ifu_aln_ctl.scala 110:34] + wire _T_1 = ~io_exu_flush_final; // @[el2_ifu_aln_ctl.scala 110:64] + wire error_stall_in = _T & _T_1; // @[el2_ifu_aln_ctl.scala 110:62] + reg [1:0] wrptr; // @[el2_ifu_aln_ctl.scala 113:48] + reg [1:0] rdptr; // @[el2_ifu_aln_ctl.scala 114:48] + reg [1:0] f2val; // @[el2_ifu_aln_ctl.scala 116:48] + reg [1:0] f1val; // @[el2_ifu_aln_ctl.scala 117:48] + reg [1:0] f0val; // @[el2_ifu_aln_ctl.scala 118:48] + reg q2off; // @[el2_ifu_aln_ctl.scala 120:48] + reg q1off; // @[el2_ifu_aln_ctl.scala 121:48] + reg q0off; // @[el2_ifu_aln_ctl.scala 122:48] + wire _T_784 = ~error_stall; // @[el2_ifu_aln_ctl.scala 392:39] + wire i0_shift = io_dec_i0_decode_d & _T_784; // @[el2_ifu_aln_ctl.scala 392:37] + wire _T_186 = rdptr == 2'h0; // @[el2_ifu_aln_ctl.scala 172:31] + wire _T_189 = _T_186 & q0off; // @[Mux.scala 27:72] + wire _T_187 = rdptr == 2'h1; // @[el2_ifu_aln_ctl.scala 173:11] + wire _T_190 = _T_187 & q1off; // @[Mux.scala 27:72] + wire _T_192 = _T_189 | _T_190; // @[Mux.scala 27:72] + wire _T_188 = rdptr == 2'h2; // @[el2_ifu_aln_ctl.scala 174:11] + wire _T_191 = _T_188 & q2off; // @[Mux.scala 27:72] + wire q0ptr = _T_192 | _T_191; // @[Mux.scala 27:72] + wire _T_202 = ~q0ptr; // @[el2_ifu_aln_ctl.scala 178:26] + wire [1:0] q0sel = {q0ptr,_T_202}; // @[Cat.scala 29:58] + wire [2:0] qren = {_T_188,_T_187,_T_186}; // @[Cat.scala 29:58] reg [31:0] q1; // @[Reg.scala 27:20] reg [31:0] q0; // @[Reg.scala 27:20] - wire [63:0] _T_321 = {q1,q0}; // @[Cat.scala 29:58] - wire [63:0] _T_328 = qren[0] ? _T_321 : 64'h0; // @[Mux.scala 27:72] + wire [63:0] _T_480 = {q1,q0}; // @[Cat.scala 29:58] + wire [63:0] _T_487 = qren[0] ? _T_480 : 64'h0; // @[Mux.scala 27:72] reg [31:0] q2; // @[Reg.scala 27:20] - wire [63:0] _T_324 = {q2,q1}; // @[Cat.scala 29:58] - wire [63:0] _T_329 = qren[1] ? _T_324 : 64'h0; // @[Mux.scala 27:72] - wire [63:0] _T_331 = _T_328 | _T_329; // @[Mux.scala 27:72] - wire [63:0] _T_327 = {q0,q2}; // @[Cat.scala 29:58] - wire [63:0] _T_330 = qren[2] ? _T_327 : 64'h0; // @[Mux.scala 27:72] - wire [63:0] qeff = _T_331 | _T_330; // @[Mux.scala 27:72] - wire [31:0] q1eff = qeff[63:32]; // @[el2_ifu_aln_ctl.scala 225:29] - wire [15:0] _T_527 = q1sel[0] ? q1eff[15:0] : 16'h0; // @[Mux.scala 27:72] - wire [15:0] _T_528 = q1sel[1] ? q1eff[31:16] : 16'h0; // @[Mux.scala 27:72] - wire [15:0] q1final = _T_527 | _T_528; // @[Mux.scala 27:72] - wire _T_247 = _T_252 & q0off; // @[Mux.scala 27:72] - wire _T_248 = _T_253 & q1off; // @[Mux.scala 27:72] - wire _T_250 = _T_247 | _T_248; // @[Mux.scala 27:72] - wire _T_249 = _T_254 & q2off; // @[Mux.scala 27:72] - wire q0ptr = _T_250 | _T_249; // @[Mux.scala 27:72] - wire _T_260 = ~q0ptr; // @[el2_ifu_aln_ctl.scala 180:26] - wire [1:0] q0sel = {q0ptr,_T_260}; // @[Cat.scala 29:58] - wire [31:0] q0eff = qeff[31:0]; // @[el2_ifu_aln_ctl.scala 225:42] - wire [31:0] _T_517 = q0sel[0] ? q0eff : 32'h0; // @[Mux.scala 27:72] - wire [15:0] _T_518 = q0sel[1] ? q0eff[31:16] : 16'h0; // @[Mux.scala 27:72] - wire [31:0] _GEN_12 = {{16'd0}, _T_518}; // @[Mux.scala 27:72] - wire [31:0] _T_519 = _T_517 | _GEN_12; // @[Mux.scala 27:72] - wire [15:0] q0final = _T_519[15:0]; // @[el2_ifu_aln_ctl.scala 294:11] - wire [31:0] _T_11 = {q1final,q0final}; // @[Cat.scala 29:58] - wire [15:0] _T_12 = f0val[0] ? q0final : 16'h0; // @[Mux.scala 27:72] - wire [31:0] _T_13 = _T_9 ? _T_11 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _GEN_13 = {{16'd0}, _T_12}; // @[Mux.scala 27:72] - wire [31:0] aligndata = _GEN_13 | _T_13; // @[Mux.scala 27:72] - reg [54:0] _T_768; // @[Reg.scala 27:20] - wire [53:0] misc1 = _T_768[53:0]; // @[el2_ifu_aln_ctl.scala 372:9] - reg [54:0] _T_770; // @[Reg.scala 27:20] - wire [53:0] misc0 = _T_770[53:0]; // @[el2_ifu_aln_ctl.scala 373:9] - wire [107:0] _T_269 = {misc1,misc0}; // @[Cat.scala 29:58] - wire [107:0] _T_276 = qren[0] ? _T_269 : 108'h0; // @[Mux.scala 27:72] - reg [54:0] _T_766; // @[Reg.scala 27:20] - wire [53:0] misc2 = _T_766[53:0]; // @[el2_ifu_aln_ctl.scala 371:9] - wire [107:0] _T_272 = {misc2,misc1}; // @[Cat.scala 29:58] - wire [107:0] _T_277 = qren[1] ? _T_272 : 108'h0; // @[Mux.scala 27:72] - wire [107:0] _T_279 = _T_276 | _T_277; // @[Mux.scala 27:72] - wire [107:0] _T_275 = {misc0,misc2}; // @[Cat.scala 29:58] - wire [107:0] _T_278 = qren[2] ? _T_275 : 108'h0; // @[Mux.scala 27:72] - wire [107:0] misceff = _T_279 | _T_278; // @[Mux.scala 27:72] - wire [52:0] misc1eff = misceff[107:55]; // @[el2_ifu_aln_ctl.scala 191:25] - wire f1icaf = misc1eff[51]; // @[el2_ifu_aln_ctl.scala 195:21] - wire [54:0] misc0eff = misceff[54:0]; // @[el2_ifu_aln_ctl.scala 192:25] - wire f0icaf = misc0eff[53]; // @[el2_ifu_aln_ctl.scala 202:21] - wire [1:0] _T_23 = {f1icaf,f0icaf}; // @[Cat.scala 29:58] - wire _T_24 = f0val[1] & f0icaf; // @[Mux.scala 27:72] - wire [1:0] _T_25 = _T_9 ? _T_23 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _GEN_14 = {{1'd0}, _T_24}; // @[Mux.scala 27:72] - wire [1:0] alignicaf = _GEN_14 | _T_25; // @[Mux.scala 27:72] - wire [1:0] _T_539 = f0val[1] ? 2'h3 : 2'h0; // @[Mux.scala 27:72] - reg [1:0] f1val; // @[el2_ifu_aln_ctl.scala 127:48] - wire [1:0] _T_538 = {f1val[0],1'h1}; // @[Cat.scala 29:58] - wire [1:0] _T_540 = _T_9 ? _T_538 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] alignval = _T_539 | _T_540; // @[Mux.scala 27:72] - wire f0_shift_2B = i0_shift & f0val[0]; // @[Mux.scala 27:72] - reg [1:0] wrptr; // @[el2_ifu_aln_ctl.scala 123:48] - reg [1:0] f2val; // @[el2_ifu_aln_ctl.scala 126:48] - wire _T_58 = ~f1val[0]; // @[el2_ifu_aln_ctl.scala 134:42] - wire f2_valid = f2val[0]; // @[el2_ifu_aln_ctl.scala 246:20] - wire _T_60 = ~f2_valid; // @[el2_ifu_aln_ctl.scala 134:55] - wire ifvalid = io_ifu_fetch_val[0]; // @[el2_ifu_aln_ctl.scala 256:30] - wire _T_65 = _T_58 & f2_valid; // @[el2_ifu_aln_ctl.scala 135:53] - wire _T_66 = _T_65 & ifvalid; // @[el2_ifu_aln_ctl.scala 135:65] - wire _T_70 = f1val[0] & _T_60; // @[el2_ifu_aln_ctl.scala 136:53] - wire _T_71 = _T_70 & ifvalid; // @[el2_ifu_aln_ctl.scala 136:65] - wire fetch_to_f1 = _T_66 | _T_71; // @[el2_ifu_aln_ctl.scala 135:77] - wire _T_80 = f1val[0] & f2_valid; // @[el2_ifu_aln_ctl.scala 139:53] - wire f2_wr_en = _T_80 & ifvalid; // @[el2_ifu_aln_ctl.scala 139:65] - wire _T_94 = wrptr == 2'h2; // @[el2_ifu_aln_ctl.scala 147:24] - wire _T_95 = _T_94 & ifvalid; // @[el2_ifu_aln_ctl.scala 147:32] - wire _T_96 = wrptr == 2'h1; // @[el2_ifu_aln_ctl.scala 147:49] - wire _T_97 = _T_96 & ifvalid; // @[el2_ifu_aln_ctl.scala 147:57] - wire _T_98 = wrptr == 2'h0; // @[el2_ifu_aln_ctl.scala 147:74] - wire _T_99 = _T_98 & ifvalid; // @[el2_ifu_aln_ctl.scala 147:82] - wire [2:0] qwen = {_T_95,_T_97,_T_99}; // @[Cat.scala 29:58] - wire _T_153 = qwen[0] & _T_1; // @[el2_ifu_aln_ctl.scala 157:34] - wire _T_157 = qwen[1] & _T_1; // @[el2_ifu_aln_ctl.scala 158:34] - wire _T_163 = ~ifvalid; // @[el2_ifu_aln_ctl.scala 160:26] - wire _T_165 = _T_163 & _T_1; // @[el2_ifu_aln_ctl.scala 160:35] - wire [1:0] _T_168 = _T_157 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_170 = _T_165 ? wrptr : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _GEN_17 = {{1'd0}, _T_153}; // @[Mux.scala 27:72] - wire [1:0] _T_171 = _GEN_17 | _T_168; // @[Mux.scala 27:72] - wire [1:0] wrptr_in = _T_171 | _T_170; // @[Mux.scala 27:72] - wire _T_176 = ~qwen[2]; // @[el2_ifu_aln_ctl.scala 162:26] - wire _T_178 = _T_176 & _T_254; // @[el2_ifu_aln_ctl.scala 162:35] - wire _T_180 = q2off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 162:74] - wire _T_184 = _T_176 & _T_253; // @[el2_ifu_aln_ctl.scala 163:35] - wire _T_190 = _T_176 & _T_252; // @[el2_ifu_aln_ctl.scala 164:35] - wire _T_192 = _T_178 & _T_180; // @[Mux.scala 27:72] - wire _T_193 = _T_184 & q2off; // @[Mux.scala 27:72] - wire _T_194 = _T_190 & q2off; // @[Mux.scala 27:72] - wire _T_195 = _T_192 | _T_193; // @[Mux.scala 27:72] - wire q2off_in = _T_195 | _T_194; // @[Mux.scala 27:72] - wire _T_199 = ~qwen[1]; // @[el2_ifu_aln_ctl.scala 166:26] - wire _T_201 = _T_199 & _T_253; // @[el2_ifu_aln_ctl.scala 166:35] - wire _T_203 = q1off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 166:74] - wire _T_207 = _T_199 & _T_252; // @[el2_ifu_aln_ctl.scala 167:35] - wire _T_213 = _T_199 & _T_254; // @[el2_ifu_aln_ctl.scala 168:35] - wire _T_215 = _T_201 & _T_203; // @[Mux.scala 27:72] - wire _T_216 = _T_207 & q1off; // @[Mux.scala 27:72] - wire _T_217 = _T_213 & q1off; // @[Mux.scala 27:72] - wire _T_218 = _T_215 | _T_216; // @[Mux.scala 27:72] - wire q1off_in = _T_218 | _T_217; // @[Mux.scala 27:72] - wire _T_222 = ~qwen[0]; // @[el2_ifu_aln_ctl.scala 170:26] - wire _T_224 = _T_222 & _T_252; // @[el2_ifu_aln_ctl.scala 170:35] - wire _T_226 = q0off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 170:76] - wire _T_230 = _T_222 & _T_254; // @[el2_ifu_aln_ctl.scala 171:35] - wire _T_236 = _T_222 & _T_253; // @[el2_ifu_aln_ctl.scala 172:35] - wire _T_238 = _T_224 & _T_226; // @[Mux.scala 27:72] - wire _T_239 = _T_230 & q0off; // @[Mux.scala 27:72] - wire _T_240 = _T_236 & q0off; // @[Mux.scala 27:72] - wire _T_241 = _T_238 | _T_239; // @[Mux.scala 27:72] - wire q0off_in = _T_241 | _T_240; // @[Mux.scala 27:72] - wire [54:0] misc_data_in = {io_iccm_rd_ecc_double_err,io_ic_access_fault_f,io_ic_access_fault_type_f,io_ifu_bp_btb_target_f[31:1],io_ifu_bp_poffset_f,io_ifu_bp_fghr_f}; // @[Cat.scala 29:58] - wire f1dbecc = misc1eff[52]; // @[el2_ifu_aln_ctl.scala 194:25] - wire f0dbecc = misc0eff[54]; // @[el2_ifu_aln_ctl.scala 201:25] - wire [5:0] _T_299 = {io_ifu_bp_hist1_f[0],io_ifu_bp_hist0_f[0],io_ifu_bp_pc4_f[0],io_ifu_bp_way_f[0],io_ifu_bp_valid_f[0],io_ifu_bp_ret_f[0]}; // @[Cat.scala 29:58] - wire [11:0] brdata_in = {io_ifu_bp_hist1_f[1],io_ifu_bp_hist0_f[1],io_ifu_bp_pc4_f[1],io_ifu_bp_way_f[1],io_ifu_bp_valid_f[1],io_ifu_bp_ret_f[1],_T_299}; // @[Cat.scala 29:58] + wire [63:0] _T_483 = {q2,q1}; // @[Cat.scala 29:58] + wire [63:0] _T_488 = qren[1] ? _T_483 : 64'h0; // @[Mux.scala 27:72] + wire [63:0] _T_490 = _T_487 | _T_488; // @[Mux.scala 27:72] + wire [63:0] _T_486 = {q0,q2}; // @[Cat.scala 29:58] + wire [63:0] _T_489 = qren[2] ? _T_486 : 64'h0; // @[Mux.scala 27:72] + wire [63:0] qeff = _T_490 | _T_489; // @[Mux.scala 27:72] + wire [31:0] q0eff = qeff[31:0]; // @[el2_ifu_aln_ctl.scala 294:42] + wire [31:0] _T_497 = q0sel[0] ? q0eff : 32'h0; // @[Mux.scala 27:72] + wire [15:0] _T_498 = q0sel[1] ? q0eff[31:16] : 16'h0; // @[Mux.scala 27:72] + wire [31:0] _GEN_12 = {{16'd0}, _T_498}; // @[Mux.scala 27:72] + wire [31:0] _T_499 = _T_497 | _GEN_12; // @[Mux.scala 27:72] + wire [15:0] q0final = _T_499[15:0]; // @[el2_ifu_aln_ctl.scala 296:11] + wire [15:0] _T_519 = f0val[0] ? q0final : 16'h0; // @[Mux.scala 27:72] + wire _T_514 = ~f0val[1]; // @[el2_ifu_aln_ctl.scala 300:58] + wire _T_516 = _T_514 & f0val[0]; // @[el2_ifu_aln_ctl.scala 300:68] + wire _T_197 = _T_186 & q1off; // @[Mux.scala 27:72] + wire _T_198 = _T_187 & q2off; // @[Mux.scala 27:72] + wire _T_200 = _T_197 | _T_198; // @[Mux.scala 27:72] + wire _T_199 = _T_188 & q0off; // @[Mux.scala 27:72] + wire q1ptr = _T_200 | _T_199; // @[Mux.scala 27:72] + wire _T_203 = ~q1ptr; // @[el2_ifu_aln_ctl.scala 180:26] + wire [1:0] q1sel = {q1ptr,_T_203}; // @[Cat.scala 29:58] + wire [31:0] q1eff = qeff[63:32]; // @[el2_ifu_aln_ctl.scala 294:29] + wire [15:0] _T_507 = q1sel[0] ? q1eff[15:0] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] _T_508 = q1sel[1] ? q1eff[31:16] : 16'h0; // @[Mux.scala 27:72] + wire [15:0] q1final = _T_507 | _T_508; // @[Mux.scala 27:72] + wire [31:0] _T_518 = {q1final,q0final}; // @[Cat.scala 29:58] + wire [31:0] _T_520 = _T_516 ? _T_518 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _GEN_13 = {{16'd0}, _T_519}; // @[Mux.scala 27:72] + wire [31:0] aligndata = _GEN_13 | _T_520; // @[Mux.scala 27:72] + wire first4B = aligndata[1:0] == 2'h3; // @[el2_ifu_aln_ctl.scala 332:29] + wire first2B = ~first4B; // @[el2_ifu_aln_ctl.scala 334:17] + wire shift_2B = i0_shift & first2B; // @[el2_ifu_aln_ctl.scala 396:24] + wire [1:0] _T_444 = {1'h0,f0val[1]}; // @[Cat.scala 29:58] + wire [1:0] _T_449 = shift_2B ? _T_444 : 2'h0; // @[Mux.scala 27:72] + wire _T_445 = ~shift_2B; // @[el2_ifu_aln_ctl.scala 284:6] + wire shift_4B = i0_shift & first4B; // @[el2_ifu_aln_ctl.scala 397:24] + wire _T_446 = ~shift_4B; // @[el2_ifu_aln_ctl.scala 284:18] + wire _T_447 = _T_445 & _T_446; // @[el2_ifu_aln_ctl.scala 284:16] + wire [1:0] _T_450 = _T_447 ? f1val : 2'h0; // @[Mux.scala 27:72] + wire [1:0] sf0val = _T_449 | _T_450; // @[Mux.scala 27:72] + wire sf0_valid = sf0val[0]; // @[el2_ifu_aln_ctl.scala 237:22] + wire _T_352 = ~sf0_valid; // @[el2_ifu_aln_ctl.scala 256:26] + wire _T_801 = f0val[0] & _T_514; // @[el2_ifu_aln_ctl.scala 400:28] + wire f1_shift_2B = _T_801 & shift_4B; // @[el2_ifu_aln_ctl.scala 400:40] + wire _T_418 = f1_shift_2B & f1val[1]; // @[Mux.scala 27:72] + wire _T_417 = ~f1_shift_2B; // @[el2_ifu_aln_ctl.scala 277:53] + wire [1:0] _T_419 = _T_417 ? f1val : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_14 = {{1'd0}, _T_418}; // @[Mux.scala 27:72] + wire [1:0] sf1val = _GEN_14 | _T_419; // @[Mux.scala 27:72] + wire sf1_valid = sf1val[0]; // @[el2_ifu_aln_ctl.scala 236:22] + wire _T_353 = _T_352 & sf1_valid; // @[el2_ifu_aln_ctl.scala 256:37] + wire f2_valid = f2val[0]; // @[el2_ifu_aln_ctl.scala 235:20] + wire _T_354 = _T_353 & f2_valid; // @[el2_ifu_aln_ctl.scala 256:50] + wire ifvalid = io_ifu_fetch_val[0]; // @[el2_ifu_aln_ctl.scala 245:30] + wire _T_355 = _T_354 & ifvalid; // @[el2_ifu_aln_ctl.scala 256:62] + wire _T_356 = sf0_valid & sf1_valid; // @[el2_ifu_aln_ctl.scala 257:17] + wire _T_357 = ~f2_valid; // @[el2_ifu_aln_ctl.scala 257:32] + wire _T_358 = _T_356 & _T_357; // @[el2_ifu_aln_ctl.scala 257:30] + wire _T_359 = _T_358 & ifvalid; // @[el2_ifu_aln_ctl.scala 257:42] + wire fetch_to_f2 = _T_355 | _T_359; // @[el2_ifu_aln_ctl.scala 256:74] + reg [30:0] f2pc; // @[Reg.scala 27:20] + wire _T_336 = ~sf1_valid; // @[el2_ifu_aln_ctl.scala 252:39] + wire _T_337 = _T_352 & _T_336; // @[el2_ifu_aln_ctl.scala 252:37] + wire _T_338 = _T_337 & f2_valid; // @[el2_ifu_aln_ctl.scala 252:50] + wire _T_339 = _T_338 & ifvalid; // @[el2_ifu_aln_ctl.scala 252:62] + wire _T_343 = _T_353 & _T_357; // @[el2_ifu_aln_ctl.scala 253:30] + wire _T_344 = _T_343 & ifvalid; // @[el2_ifu_aln_ctl.scala 253:42] + wire _T_345 = _T_339 | _T_344; // @[el2_ifu_aln_ctl.scala 252:74] + wire _T_347 = sf0_valid & _T_336; // @[el2_ifu_aln_ctl.scala 254:17] + wire _T_349 = _T_347 & _T_357; // @[el2_ifu_aln_ctl.scala 254:30] + wire _T_350 = _T_349 & ifvalid; // @[el2_ifu_aln_ctl.scala 254:42] + wire fetch_to_f1 = _T_345 | _T_350; // @[el2_ifu_aln_ctl.scala 253:54] + wire _T_25 = fetch_to_f1 | _T_354; // @[el2_ifu_aln_ctl.scala 141:33] + wire f1_shift_wr_en = _T_25 | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 141:47] + reg [30:0] f1pc; // @[Reg.scala 27:20] + wire [30:0] _T_376 = fetch_to_f1 ? io_ifu_fetch_pc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_377 = _T_354 ? f2pc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_379 = _T_376 | _T_377; // @[Mux.scala 27:72] + wire _T_372 = ~fetch_to_f1; // @[el2_ifu_aln_ctl.scala 267:6] + wire _T_373 = ~_T_354; // @[el2_ifu_aln_ctl.scala 267:21] + wire _T_374 = _T_372 & _T_373; // @[el2_ifu_aln_ctl.scala 267:19] + wire [30:0] _T_364 = f1_shift_2B ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12] + reg [30:0] f0pc; // @[Reg.scala 27:20] + wire [30:0] f0pc_plus1 = f0pc + 31'h1; // @[el2_ifu_aln_ctl.scala 259:25] + wire [30:0] _T_365 = _T_364 & f0pc_plus1; // @[el2_ifu_aln_ctl.scala 263:38] + wire [30:0] _T_368 = _T_417 ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12] + wire [30:0] _T_369 = _T_368 & f0pc; // @[el2_ifu_aln_ctl.scala 263:78] + wire [30:0] sf1pc = _T_365 | _T_369; // @[el2_ifu_aln_ctl.scala 263:52] + wire [30:0] _T_378 = _T_374 ? sf1pc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] f1pc_in = _T_379 | _T_378; // @[Mux.scala 27:72] + wire _T_333 = _T_337 & _T_357; // @[el2_ifu_aln_ctl.scala 251:50] + wire fetch_to_f0 = _T_333 & ifvalid; // @[el2_ifu_aln_ctl.scala 251:62] + wire _T_27 = fetch_to_f0 | _T_338; // @[el2_ifu_aln_ctl.scala 142:33] + wire _T_28 = _T_27 | _T_353; // @[el2_ifu_aln_ctl.scala 142:47] + wire _T_29 = _T_28 | shift_2B; // @[el2_ifu_aln_ctl.scala 142:61] + wire f0_shift_wr_en = _T_29 | shift_4B; // @[el2_ifu_aln_ctl.scala 142:72] + wire [30:0] _T_391 = fetch_to_f0 ? io_ifu_fetch_pc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_392 = _T_338 ? f2pc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_395 = _T_391 | _T_392; // @[Mux.scala 27:72] + wire [30:0] _T_393 = _T_353 ? sf1pc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_396 = _T_395 | _T_393; // @[Mux.scala 27:72] + wire _T_385 = ~fetch_to_f0; // @[el2_ifu_aln_ctl.scala 272:24] + wire _T_386 = ~_T_338; // @[el2_ifu_aln_ctl.scala 272:39] + wire _T_387 = _T_385 & _T_386; // @[el2_ifu_aln_ctl.scala 272:37] + wire _T_388 = ~_T_353; // @[el2_ifu_aln_ctl.scala 272:54] + wire _T_389 = _T_387 & _T_388; // @[el2_ifu_aln_ctl.scala 272:52] + wire [30:0] _T_394 = _T_389 ? f0pc_plus1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] f0pc_in = _T_396 | _T_394; // @[Mux.scala 27:72] + wire _T_35 = wrptr == 2'h2; // @[el2_ifu_aln_ctl.scala 145:21] + wire _T_36 = _T_35 & ifvalid; // @[el2_ifu_aln_ctl.scala 145:29] + wire _T_37 = wrptr == 2'h1; // @[el2_ifu_aln_ctl.scala 145:46] + wire _T_38 = _T_37 & ifvalid; // @[el2_ifu_aln_ctl.scala 145:54] + wire _T_39 = wrptr == 2'h0; // @[el2_ifu_aln_ctl.scala 145:71] + wire _T_40 = _T_39 & ifvalid; // @[el2_ifu_aln_ctl.scala 145:79] + wire [2:0] qwen = {_T_36,_T_38,_T_40}; // @[Cat.scala 29:58] + reg [11:0] brdata2; // @[Reg.scala 27:20] + wire [5:0] _T_242 = {io_ifu_bp_hist1_f[0],io_ifu_bp_hist0_f[0],io_ifu_bp_pc4_f[0],io_ifu_bp_way_f[0],io_ifu_bp_valid_f[0],io_ifu_bp_ret_f[0]}; // @[Cat.scala 29:58] + wire [11:0] brdata_in = {io_ifu_bp_hist1_f[1],io_ifu_bp_hist0_f[1],io_ifu_bp_pc4_f[1],io_ifu_bp_way_f[1],io_ifu_bp_valid_f[1],io_ifu_bp_ret_f[1],_T_242}; // @[Cat.scala 29:58] reg [11:0] brdata1; // @[Reg.scala 27:20] reg [11:0] brdata0; // @[Reg.scala 27:20] - wire [23:0] _T_307 = {brdata1,brdata0}; // @[Cat.scala 29:58] - reg [11:0] brdata2; // @[Reg.scala 27:20] - wire [23:0] _T_310 = {brdata2,brdata1}; // @[Cat.scala 29:58] - wire [23:0] _T_313 = {brdata0,brdata2}; // @[Cat.scala 29:58] - wire [23:0] _T_314 = qren[0] ? _T_307 : 24'h0; // @[Mux.scala 27:72] - wire [23:0] _T_315 = qren[1] ? _T_310 : 24'h0; // @[Mux.scala 27:72] - wire [23:0] _T_316 = qren[2] ? _T_313 : 24'h0; // @[Mux.scala 27:72] - wire [23:0] _T_317 = _T_314 | _T_315; // @[Mux.scala 27:72] - wire [23:0] brdataeff = _T_317 | _T_316; // @[Mux.scala 27:72] - wire [11:0] brdata0eff = brdataeff[11:0]; // @[el2_ifu_aln_ctl.scala 216:43] - wire [11:0] brdata1eff = brdataeff[23:12]; // @[el2_ifu_aln_ctl.scala 216:61] - wire [11:0] _T_338 = q0sel[0] ? brdata0eff : 12'h0; // @[Mux.scala 27:72] - wire [5:0] _T_339 = q0sel[1] ? brdata0eff[11:6] : 6'h0; // @[Mux.scala 27:72] - wire [11:0] _GEN_18 = {{6'd0}, _T_339}; // @[Mux.scala 27:72] - wire [11:0] brdata0final = _T_338 | _GEN_18; // @[Mux.scala 27:72] - wire [11:0] _T_346 = q1sel[0] ? brdata1eff : 12'h0; // @[Mux.scala 27:72] - wire [5:0] _T_347 = q1sel[1] ? brdata1eff[11:6] : 6'h0; // @[Mux.scala 27:72] - wire [11:0] _GEN_19 = {{6'd0}, _T_347}; // @[Mux.scala 27:72] - wire [11:0] brdata1final = _T_346 | _GEN_19; // @[Mux.scala 27:72] + reg [54:0] _T_14; // @[Reg.scala 27:20] + wire [54:0] misc_data_in = {io_iccm_rd_ecc_double_err,io_ic_access_fault_f,io_ic_access_fault_type_f,io_ifu_bp_btb_target_f[31:1],io_ifu_bp_poffset_f,io_ifu_bp_fghr_f}; // @[Cat.scala 29:58] + reg [54:0] _T_16; // @[Reg.scala 27:20] + reg [54:0] _T_18; // @[Reg.scala 27:20] + wire _T_44 = qren[0] & io_ifu_fb_consume1; // @[el2_ifu_aln_ctl.scala 147:34] + wire _T_46 = _T_44 & _T_1; // @[el2_ifu_aln_ctl.scala 147:55] + wire _T_49 = qren[1] & io_ifu_fb_consume1; // @[el2_ifu_aln_ctl.scala 148:14] + wire _T_51 = _T_49 & _T_1; // @[el2_ifu_aln_ctl.scala 148:35] + wire _T_59 = qren[0] & io_ifu_fb_consume2; // @[el2_ifu_aln_ctl.scala 150:14] + wire _T_61 = _T_59 & _T_1; // @[el2_ifu_aln_ctl.scala 150:35] + wire _T_69 = qren[2] & io_ifu_fb_consume2; // @[el2_ifu_aln_ctl.scala 152:14] + wire _T_71 = _T_69 & _T_1; // @[el2_ifu_aln_ctl.scala 152:35] + wire _T_73 = ~io_ifu_fb_consume1; // @[el2_ifu_aln_ctl.scala 153:6] + wire _T_74 = ~io_ifu_fb_consume2; // @[el2_ifu_aln_ctl.scala 153:28] + wire _T_75 = _T_73 & _T_74; // @[el2_ifu_aln_ctl.scala 153:26] + wire _T_77 = _T_75 & _T_1; // @[el2_ifu_aln_ctl.scala 153:48] + wire [1:0] _T_80 = _T_51 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_82 = _T_61 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_85 = _T_77 ? rdptr : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_15 = {{1'd0}, _T_46}; // @[Mux.scala 27:72] + wire [1:0] _T_86 = _GEN_15 | _T_80; // @[Mux.scala 27:72] + wire [1:0] _T_88 = _T_86 | _T_82; // @[Mux.scala 27:72] + wire [1:0] _GEN_16 = {{1'd0}, _T_71}; // @[Mux.scala 27:72] + wire [1:0] _T_90 = _T_88 | _GEN_16; // @[Mux.scala 27:72] + wire [1:0] rdptr_in = _T_90 | _T_85; // @[Mux.scala 27:72] + wire _T_95 = qwen[0] & _T_1; // @[el2_ifu_aln_ctl.scala 155:34] + wire _T_99 = qwen[1] & _T_1; // @[el2_ifu_aln_ctl.scala 156:14] + wire _T_105 = ~ifvalid; // @[el2_ifu_aln_ctl.scala 158:6] + wire _T_107 = _T_105 & _T_1; // @[el2_ifu_aln_ctl.scala 158:15] + wire [1:0] _T_110 = _T_99 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_112 = _T_107 ? wrptr : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_17 = {{1'd0}, _T_95}; // @[Mux.scala 27:72] + wire [1:0] _T_113 = _GEN_17 | _T_110; // @[Mux.scala 27:72] + wire [1:0] wrptr_in = _T_113 | _T_112; // @[Mux.scala 27:72] + wire _T_118 = ~qwen[2]; // @[el2_ifu_aln_ctl.scala 160:26] + wire _T_120 = _T_118 & _T_188; // @[el2_ifu_aln_ctl.scala 160:35] + wire _T_794 = shift_2B & f0val[0]; // @[Mux.scala 27:72] + wire _T_791 = ~f0val[0]; // @[el2_ifu_aln_ctl.scala 399:77] + wire _T_793 = _T_791 & f0val[0]; // @[el2_ifu_aln_ctl.scala 399:87] + wire _T_795 = shift_4B & _T_793; // @[Mux.scala 27:72] + wire f0_shift_2B = _T_794 | _T_795; // @[Mux.scala 27:72] + wire _T_122 = q2off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 160:74] + wire _T_126 = _T_118 & _T_187; // @[el2_ifu_aln_ctl.scala 161:15] + wire _T_128 = q2off | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 161:54] + wire _T_132 = _T_118 & _T_186; // @[el2_ifu_aln_ctl.scala 162:15] + wire _T_134 = _T_120 & _T_122; // @[Mux.scala 27:72] + wire _T_135 = _T_126 & _T_128; // @[Mux.scala 27:72] + wire _T_136 = _T_132 & q2off; // @[Mux.scala 27:72] + wire _T_137 = _T_134 | _T_135; // @[Mux.scala 27:72] + wire q2off_in = _T_137 | _T_136; // @[Mux.scala 27:72] + wire _T_141 = ~qwen[1]; // @[el2_ifu_aln_ctl.scala 164:26] + wire _T_143 = _T_141 & _T_187; // @[el2_ifu_aln_ctl.scala 164:35] + wire _T_145 = q1off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 164:74] + wire _T_149 = _T_141 & _T_186; // @[el2_ifu_aln_ctl.scala 165:15] + wire _T_151 = q1off | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 165:54] + wire _T_155 = _T_141 & _T_188; // @[el2_ifu_aln_ctl.scala 166:15] + wire _T_157 = _T_143 & _T_145; // @[Mux.scala 27:72] + wire _T_158 = _T_149 & _T_151; // @[Mux.scala 27:72] + wire _T_159 = _T_155 & q1off; // @[Mux.scala 27:72] + wire _T_160 = _T_157 | _T_158; // @[Mux.scala 27:72] + wire q1off_in = _T_160 | _T_159; // @[Mux.scala 27:72] + wire _T_164 = ~qwen[0]; // @[el2_ifu_aln_ctl.scala 168:26] + wire _T_166 = _T_164 & _T_186; // @[el2_ifu_aln_ctl.scala 168:35] + wire _T_168 = q0off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 168:76] + wire _T_172 = _T_164 & _T_188; // @[el2_ifu_aln_ctl.scala 169:15] + wire _T_174 = q0off | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 169:56] + wire _T_178 = _T_164 & _T_187; // @[el2_ifu_aln_ctl.scala 170:15] + wire _T_180 = _T_166 & _T_168; // @[Mux.scala 27:72] + wire _T_181 = _T_172 & _T_174; // @[Mux.scala 27:72] + wire _T_182 = _T_178 & q0off; // @[Mux.scala 27:72] + wire _T_183 = _T_180 | _T_181; // @[Mux.scala 27:72] + wire q0off_in = _T_183 | _T_182; // @[Mux.scala 27:72] + wire [53:0] misc1 = _T_16[53:0]; // @[el2_ifu_aln_ctl.scala 133:9] + wire [53:0] misc0 = _T_18[53:0]; // @[el2_ifu_aln_ctl.scala 134:9] + wire [107:0] _T_212 = {misc1,misc0}; // @[Cat.scala 29:58] + wire [53:0] misc2 = _T_14[53:0]; // @[el2_ifu_aln_ctl.scala 132:9] + wire [107:0] _T_215 = {misc2,misc1}; // @[Cat.scala 29:58] + wire [107:0] _T_218 = {misc0,misc2}; // @[Cat.scala 29:58] + wire [107:0] _T_219 = qren[0] ? _T_212 : 108'h0; // @[Mux.scala 27:72] + wire [107:0] _T_220 = qren[1] ? _T_215 : 108'h0; // @[Mux.scala 27:72] + wire [107:0] _T_221 = qren[2] ? _T_218 : 108'h0; // @[Mux.scala 27:72] + wire [107:0] _T_222 = _T_219 | _T_220; // @[Mux.scala 27:72] + wire [107:0] misceff = _T_222 | _T_221; // @[Mux.scala 27:72] + wire [52:0] misc1eff = misceff[107:55]; // @[el2_ifu_aln_ctl.scala 189:25] + wire [54:0] misc0eff = misceff[54:0]; // @[el2_ifu_aln_ctl.scala 190:25] + wire f1dbecc = misc1eff[52]; // @[el2_ifu_aln_ctl.scala 193:25] + wire f1icaf = misc1eff[51]; // @[el2_ifu_aln_ctl.scala 194:21] + wire [1:0] f1ictype = misc1eff[50:49]; // @[el2_ifu_aln_ctl.scala 195:26] + wire [30:0] f1prett = misc1eff[48:18]; // @[el2_ifu_aln_ctl.scala 196:25] + wire [11:0] f1poffset = misc1eff[19:8]; // @[el2_ifu_aln_ctl.scala 197:27] + wire [7:0] f1fghr = misc1eff[7:0]; // @[el2_ifu_aln_ctl.scala 198:24] + wire f0dbecc = misc0eff[54]; // @[el2_ifu_aln_ctl.scala 200:25] + wire f0icaf = misc0eff[53]; // @[el2_ifu_aln_ctl.scala 201:21] + wire [1:0] f0ictype = misc0eff[52:51]; // @[el2_ifu_aln_ctl.scala 202:26] + wire [30:0] f0prett = misc0eff[50:20]; // @[el2_ifu_aln_ctl.scala 203:25] + wire [11:0] f0poffset = misc0eff[19:8]; // @[el2_ifu_aln_ctl.scala 204:27] + wire [7:0] f0fghr = misc0eff[7:0]; // @[el2_ifu_aln_ctl.scala 205:24] + wire [23:0] _T_251 = {brdata1,brdata0}; // @[Cat.scala 29:58] + wire [23:0] _T_254 = {brdata2,brdata1}; // @[Cat.scala 29:58] + wire [23:0] _T_257 = {brdata0,brdata2}; // @[Cat.scala 29:58] + wire [23:0] _T_258 = qren[0] ? _T_251 : 24'h0; // @[Mux.scala 27:72] + wire [23:0] _T_259 = qren[1] ? _T_254 : 24'h0; // @[Mux.scala 27:72] + wire [23:0] _T_260 = qren[2] ? _T_257 : 24'h0; // @[Mux.scala 27:72] + wire [23:0] _T_261 = _T_258 | _T_259; // @[Mux.scala 27:72] + wire [23:0] brdataeff = _T_261 | _T_260; // @[Mux.scala 27:72] + wire [11:0] brdata0eff = brdataeff[11:0]; // @[el2_ifu_aln_ctl.scala 215:43] + wire [11:0] brdata1eff = brdataeff[23:12]; // @[el2_ifu_aln_ctl.scala 215:61] + wire [11:0] _T_268 = q0sel[0] ? brdata0eff : 12'h0; // @[Mux.scala 27:72] + wire [5:0] _T_269 = q0sel[1] ? brdata0eff[11:6] : 6'h0; // @[Mux.scala 27:72] + wire [11:0] _GEN_18 = {{6'd0}, _T_269}; // @[Mux.scala 27:72] + wire [11:0] brdata0final = _T_268 | _GEN_18; // @[Mux.scala 27:72] + wire [11:0] _T_276 = q1sel[0] ? brdata1eff : 12'h0; // @[Mux.scala 27:72] + wire [5:0] _T_277 = q1sel[1] ? brdata1eff[11:6] : 6'h0; // @[Mux.scala 27:72] + wire [11:0] _GEN_19 = {{6'd0}, _T_277}; // @[Mux.scala 27:72] + wire [11:0] brdata1final = _T_276 | _GEN_19; // @[Mux.scala 27:72] wire [1:0] f0ret = {brdata0final[6],brdata0final[0]}; // @[Cat.scala 29:58] wire [1:0] f0brend = {brdata0final[7],brdata0final[1]}; // @[Cat.scala 29:58] wire [1:0] f0way = {brdata0final[8],brdata0final[2]}; // @[Cat.scala 29:58] @@ -760,95 +858,158 @@ module el2_ifu_aln_ctl( wire [1:0] f1pc4 = {brdata1final[9],brdata1final[3]}; // @[Cat.scala 29:58] wire [1:0] f1hist0 = {brdata1final[10],brdata1final[4]}; // @[Cat.scala 29:58] wire [1:0] f1hist1 = {brdata1final[11],brdata1final[5]}; // @[Cat.scala 29:58] - wire consume_fb1 = _T_58 & f1val[0]; // @[el2_ifu_aln_ctl.scala 251:32] - wire _T_382 = ~consume_fb1; // @[el2_ifu_aln_ctl.scala 253:39] - wire _T_383 = f0val[0] & _T_382; // @[el2_ifu_aln_ctl.scala 253:37] - wire _T_386 = f0val[0] & consume_fb1; // @[el2_ifu_aln_ctl.scala 254:37] - wire _T_409 = ~fetch_to_f1; // @[el2_ifu_aln_ctl.scala 271:28] - wire _T_410 = ~_T_80; // @[el2_ifu_aln_ctl.scala 271:43] - wire _T_411 = _T_409 & _T_410; // @[el2_ifu_aln_ctl.scala 271:41] - wire _T_422 = ~_T_65; // @[el2_ifu_aln_ctl.scala 276:43] - wire _T_435 = f2_wr_en & _T_1; // @[el2_ifu_aln_ctl.scala 278:38] - wire _T_437 = ~f2_wr_en; // @[el2_ifu_aln_ctl.scala 279:6] - wire _T_439 = _T_437 & _T_410; // @[el2_ifu_aln_ctl.scala 279:19] - wire _T_441 = _T_439 & _T_422; // @[el2_ifu_aln_ctl.scala 279:34] - wire _T_443 = _T_441 & _T_1; // @[el2_ifu_aln_ctl.scala 279:49] - wire [1:0] _T_445 = _T_435 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_446 = _T_443 ? f2val : 2'h0; // @[Mux.scala 27:72] - wire [1:0] f2val_in = _T_445 | _T_446; // @[Mux.scala 27:72] - wire _T_458 = fetch_to_f1 & _T_1; // @[el2_ifu_aln_ctl.scala 283:38] - wire _T_461 = _T_80 & _T_1; // @[el2_ifu_aln_ctl.scala 284:38] - wire _T_467 = _T_411 & _T_58; // @[el2_ifu_aln_ctl.scala 285:54] - wire _T_469 = _T_467 & _T_1; // @[el2_ifu_aln_ctl.scala 285:69] - wire [1:0] _T_471 = _T_458 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_472 = _T_461 ? f2val : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_473 = _T_469 ? f1val : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_474 = _T_471 | _T_472; // @[Mux.scala 27:72] - wire [1:0] f1val_in = _T_474 | _T_473; // @[Mux.scala 27:72] - wire _T_479 = ~i0_shift; // @[el2_ifu_aln_ctl.scala 287:52] - wire _T_483 = i0_shift & f0val[1]; // @[Mux.scala 27:72] - wire [1:0] _T_484 = _T_479 ? f0val : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _GEN_23 = {{1'd0}, _T_483}; // @[Mux.scala 27:72] - wire [1:0] _T_485 = _GEN_23 | _T_484; // @[Mux.scala 27:72] - wire [1:0] _T_546 = f0dbecc ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_552 = {f1dbecc,f0dbecc}; // @[Cat.scala 29:58] - wire [1:0] _T_553 = f0val[1] ? _T_546 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_554 = _T_9 ? _T_552 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] aligndbecc = _T_553 | _T_554; // @[Mux.scala 27:72] - wire [1:0] _T_565 = {f1brend[0],f0brend[0]}; // @[Cat.scala 29:58] - wire [1:0] _T_566 = f0val[1] ? f0brend : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_567 = _T_9 ? _T_565 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] alignbrend = _T_566 | _T_567; // @[Mux.scala 27:72] - wire [1:0] _T_578 = {f1pc4[0],f0pc4[0]}; // @[Cat.scala 29:58] - wire [1:0] _T_579 = f0val[1] ? f0pc4 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_580 = _T_9 ? _T_578 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] alignpc4 = _T_579 | _T_580; // @[Mux.scala 27:72] - wire [1:0] _T_591 = {f1ret[0],f0ret[0]}; // @[Cat.scala 29:58] - wire [1:0] _T_592 = f0val[1] ? f0ret : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_593 = _T_9 ? _T_591 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] alignret = _T_592 | _T_593; // @[Mux.scala 27:72] - wire [1:0] _T_604 = {f1way[0],f0way[0]}; // @[Cat.scala 29:58] - wire [1:0] _T_605 = f0val[1] ? f0way : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_606 = _T_9 ? _T_604 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] alignway = _T_605 | _T_606; // @[Mux.scala 27:72] - wire [1:0] _T_617 = {f1hist1[0],f0hist1[0]}; // @[Cat.scala 29:58] - wire [1:0] _T_618 = f0val[1] ? f0hist1 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_619 = _T_9 ? _T_617 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] alignhist1 = _T_618 | _T_619; // @[Mux.scala 27:72] - wire [1:0] _T_630 = {f1hist0[0],f0hist0[0]}; // @[Cat.scala 29:58] - wire [1:0] _T_631 = f0val[1] ? f0hist0 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_632 = _T_9 ? _T_630 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] alignhist0 = _T_631 | _T_632; // @[Mux.scala 27:72] - wire i0_brp_pc4 = alignpc4[0]; // @[el2_ifu_aln_ctl.scala 356:39] - el2_ifu_compress_ctl decompressed ( // @[el2_ifu_aln_ctl.scala 99:28] + wire consume_fb0 = _T_352 & f0val[0]; // @[el2_ifu_aln_ctl.scala 239:32] + wire consume_fb1 = _T_336 & f1val[0]; // @[el2_ifu_aln_ctl.scala 240:32] + wire _T_312 = ~consume_fb1; // @[el2_ifu_aln_ctl.scala 242:39] + wire _T_313 = consume_fb0 & _T_312; // @[el2_ifu_aln_ctl.scala 242:37] + wire _T_316 = consume_fb0 & consume_fb1; // @[el2_ifu_aln_ctl.scala 243:37] + wire _T_400 = fetch_to_f2 & _T_1; // @[el2_ifu_aln_ctl.scala 274:38] + wire _T_402 = ~fetch_to_f2; // @[el2_ifu_aln_ctl.scala 275:6] + wire _T_404 = _T_402 & _T_373; // @[el2_ifu_aln_ctl.scala 275:19] + wire _T_406 = _T_404 & _T_386; // @[el2_ifu_aln_ctl.scala 275:34] + wire _T_408 = _T_406 & _T_1; // @[el2_ifu_aln_ctl.scala 275:49] + wire [1:0] _T_410 = _T_400 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_411 = _T_408 ? f2val : 2'h0; // @[Mux.scala 27:72] + wire [1:0] f2val_in = _T_410 | _T_411; // @[Mux.scala 27:72] + wire _T_423 = fetch_to_f1 & _T_1; // @[el2_ifu_aln_ctl.scala 279:38] + wire _T_426 = _T_354 & _T_1; // @[el2_ifu_aln_ctl.scala 280:18] + wire _T_432 = _T_374 & _T_388; // @[el2_ifu_aln_ctl.scala 281:34] + wire _T_434 = _T_432 & _T_1; // @[el2_ifu_aln_ctl.scala 281:49] + wire [1:0] _T_436 = _T_423 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_437 = _T_426 ? f2val : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_438 = _T_434 ? sf1val : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_439 = _T_436 | _T_437; // @[Mux.scala 27:72] + wire [1:0] f1val_in = _T_439 | _T_438; // @[Mux.scala 27:72] + wire _T_454 = fetch_to_f0 & _T_1; // @[el2_ifu_aln_ctl.scala 286:38] + wire _T_457 = _T_338 & _T_1; // @[el2_ifu_aln_ctl.scala 287:18] + wire _T_460 = _T_353 & _T_1; // @[el2_ifu_aln_ctl.scala 288:18] + wire _T_468 = _T_389 & _T_1; // @[el2_ifu_aln_ctl.scala 289:49] + wire [1:0] _T_470 = _T_454 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_471 = _T_457 ? f2val : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_472 = _T_460 ? sf1val : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_473 = _T_468 ? sf0val : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_474 = _T_470 | _T_471; // @[Mux.scala 27:72] + wire [1:0] _T_475 = _T_474 | _T_472; // @[Mux.scala 27:72] + wire [1:0] f0val_in = _T_475 | _T_473; // @[Mux.scala 27:72] + wire [1:0] _T_529 = {f1val[0],1'h1}; // @[Cat.scala 29:58] + wire [1:0] _T_530 = f0val[1] ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_531 = _T_516 ? _T_529 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] alignval = _T_530 | _T_531; // @[Mux.scala 27:72] + wire [1:0] _T_541 = {f1icaf,f0icaf}; // @[Cat.scala 29:58] + wire _T_542 = f0val[1] & f0icaf; // @[Mux.scala 27:72] + wire [1:0] _T_543 = _T_516 ? _T_541 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_20 = {{1'd0}, _T_542}; // @[Mux.scala 27:72] + wire [1:0] alignicaf = _GEN_20 | _T_543; // @[Mux.scala 27:72] + wire [1:0] _T_548 = f0dbecc ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_554 = {f1dbecc,f0dbecc}; // @[Cat.scala 29:58] + wire [1:0] _T_555 = f0val[1] ? _T_548 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_556 = _T_516 ? _T_554 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] aligndbecc = _T_555 | _T_556; // @[Mux.scala 27:72] + wire [1:0] _T_567 = {f1brend[0],f0brend[0]}; // @[Cat.scala 29:58] + wire [1:0] _T_568 = f0val[1] ? f0brend : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_569 = _T_516 ? _T_567 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] alignbrend = _T_568 | _T_569; // @[Mux.scala 27:72] + wire [1:0] _T_580 = {f1pc4[0],f0pc4[0]}; // @[Cat.scala 29:58] + wire [1:0] _T_581 = f0val[1] ? f0pc4 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_582 = _T_516 ? _T_580 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] alignpc4 = _T_581 | _T_582; // @[Mux.scala 27:72] + wire [1:0] _T_593 = {f1ret[0],f0ret[0]}; // @[Cat.scala 29:58] + wire [1:0] _T_594 = f0val[1] ? f0ret : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_595 = _T_516 ? _T_593 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] alignret = _T_594 | _T_595; // @[Mux.scala 27:72] + wire [1:0] _T_606 = {f1way[0],f0way[0]}; // @[Cat.scala 29:58] + wire [1:0] _T_607 = f0val[1] ? f0way : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_608 = _T_516 ? _T_606 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] alignway = _T_607 | _T_608; // @[Mux.scala 27:72] + wire [1:0] _T_619 = {f1hist1[0],f0hist1[0]}; // @[Cat.scala 29:58] + wire [1:0] _T_620 = f0val[1] ? f0hist1 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_621 = _T_516 ? _T_619 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] alignhist1 = _T_620 | _T_621; // @[Mux.scala 27:72] + wire [1:0] _T_632 = {f1hist0[0],f0hist0[0]}; // @[Cat.scala 29:58] + wire [1:0] _T_633 = f0val[1] ? f0hist0 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_634 = _T_516 ? _T_632 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] alignhist0 = _T_633 | _T_634; // @[Mux.scala 27:72] + wire [30:0] _T_646 = f0val[1] ? f0pc_plus1 : 31'h0; // @[Mux.scala 27:72] + wire [30:0] _T_647 = _T_516 ? f1pc : 31'h0; // @[Mux.scala 27:72] + wire [30:0] secondpc = _T_646 | _T_647; // @[Mux.scala 27:72] + wire _T_656 = first4B & alignval[1]; // @[Mux.scala 27:72] + wire _T_657 = first2B & alignval[0]; // @[Mux.scala 27:72] + wire _T_661 = |alignicaf; // @[el2_ifu_aln_ctl.scala 338:59] + wire _T_664 = first4B & _T_661; // @[Mux.scala 27:72] + wire _T_665 = first2B & alignicaf[0]; // @[Mux.scala 27:72] + wire _T_670 = first4B & _T_514; // @[el2_ifu_aln_ctl.scala 340:39] + wire _T_672 = _T_670 & f0val[0]; // @[el2_ifu_aln_ctl.scala 340:51] + wire _T_674 = ~alignicaf[0]; // @[el2_ifu_aln_ctl.scala 340:64] + wire _T_675 = _T_672 & _T_674; // @[el2_ifu_aln_ctl.scala 340:62] + wire _T_677 = ~aligndbecc[0]; // @[el2_ifu_aln_ctl.scala 340:80] + wire _T_678 = _T_675 & _T_677; // @[el2_ifu_aln_ctl.scala 340:78] + wire icaf_eff = alignicaf[1] | aligndbecc[1]; // @[el2_ifu_aln_ctl.scala 342:31] + wire _T_683 = first4B & icaf_eff; // @[el2_ifu_aln_ctl.scala 344:32] + wire _T_686 = |aligndbecc; // @[el2_ifu_aln_ctl.scala 346:59] + wire _T_689 = first4B & _T_686; // @[Mux.scala 27:72] + wire _T_690 = first2B & aligndbecc[0]; // @[Mux.scala 27:72] + wire [31:0] _T_695 = first4B ? aligndata : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_696 = first2B ? decompressed_io_dout : 32'h0; // @[Mux.scala 27:72] + wire [7:0] _T_701 = f0pc[8:1] ^ f0pc[16:9]; // @[el2_lib.scala 191:46] + wire [7:0] firstpc_hash = _T_701 ^ f0pc[24:17]; // @[el2_lib.scala 191:84] + wire [7:0] _T_705 = secondpc[8:1] ^ secondpc[16:9]; // @[el2_lib.scala 191:46] + wire [7:0] secondpc_hash = _T_705 ^ secondpc[24:17]; // @[el2_lib.scala 191:84] + wire [4:0] _T_711 = f0pc[13:9] ^ f0pc[18:14]; // @[el2_lib.scala 182:111] + wire [4:0] firstbrtag_hash = _T_711 ^ f0pc[23:19]; // @[el2_lib.scala 182:111] + wire [4:0] _T_716 = secondpc[13:9] ^ secondpc[18:14]; // @[el2_lib.scala 182:111] + wire [4:0] secondbrtag_hash = _T_716 ^ secondpc[23:19]; // @[el2_lib.scala 182:111] + wire _T_718 = first2B & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 362:30] + wire _T_720 = first4B & alignbrend[1]; // @[el2_ifu_aln_ctl.scala 362:58] + wire _T_721 = _T_718 | _T_720; // @[el2_ifu_aln_ctl.scala 362:47] + wire _T_725 = _T_656 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 362:100] + wire _T_728 = first2B & alignret[0]; // @[el2_ifu_aln_ctl.scala 364:29] + wire _T_730 = first4B & alignret[1]; // @[el2_ifu_aln_ctl.scala 364:55] + wire _T_733 = first2B & alignpc4[0]; // @[el2_ifu_aln_ctl.scala 366:29] + wire _T_735 = first4B & alignpc4[1]; // @[el2_ifu_aln_ctl.scala 366:55] + wire i0_brp_pc4 = _T_733 | _T_735; // @[el2_ifu_aln_ctl.scala 366:44] + wire _T_737 = first2B | alignbrend[0]; // @[el2_ifu_aln_ctl.scala 368:33] + wire _T_743 = first2B & alignhist1[0]; // @[el2_ifu_aln_ctl.scala 370:34] + wire _T_745 = first4B & alignhist1[1]; // @[el2_ifu_aln_ctl.scala 370:62] + wire _T_746 = _T_743 | _T_745; // @[el2_ifu_aln_ctl.scala 370:51] + wire _T_748 = first2B & alignhist0[0]; // @[el2_ifu_aln_ctl.scala 371:14] + wire _T_750 = first4B & alignhist0[1]; // @[el2_ifu_aln_ctl.scala 371:42] + wire _T_751 = _T_748 | _T_750; // @[el2_ifu_aln_ctl.scala 371:31] + wire i0_ends_f1 = first4B & _T_516; // @[el2_ifu_aln_ctl.scala 373:28] + wire _T_767 = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 382:42] + wire _T_768 = _T_767 & first2B; // @[el2_ifu_aln_ctl.scala 382:56] + wire _T_769 = ~i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 382:89] + wire _T_770 = io_i0_brp_valid & _T_769; // @[el2_ifu_aln_ctl.scala 382:87] + wire _T_771 = _T_770 & first4B; // @[el2_ifu_aln_ctl.scala 382:101] + wire [7:0] _T_776 = _T_737 ? firstpc_hash : secondpc_hash; // @[el2_ifu_aln_ctl.scala 384:28] + el2_ifu_compress_ctl decompressed ( // @[el2_ifu_aln_ctl.scala 350:28] .io_din(decompressed_io_din), .io_dout(decompressed_io_dout) ); - assign io_ifu_i0_valid = alignval[0]; // @[el2_ifu_aln_ctl.scala 115:19] - assign io_ifu_i0_icaf = alignicaf[0]; // @[el2_ifu_aln_ctl.scala 114:18] - assign io_ifu_i0_icaf_type = misc0eff[52:51]; // @[el2_ifu_aln_ctl.scala 324:23] - assign io_ifu_i0_icaf_f1 = 1'h0; // @[el2_ifu_aln_ctl.scala 328:21] - assign io_ifu_i0_dbecc = aligndbecc[0]; // @[el2_ifu_aln_ctl.scala 330:19] - assign io_ifu_i0_instr = decompressed_io_dout; // @[el2_ifu_aln_ctl.scala 103:20] - assign io_ifu_i0_pc = 32'h0; // @[el2_ifu_aln_ctl.scala 320:16] - assign io_ifu_i0_pc4 = 1'h0; // @[el2_ifu_aln_ctl.scala 116:17] - assign io_ifu_fb_consume1 = _T_383 & _T_1; // @[el2_ifu_aln_ctl.scala 253:22] - assign io_ifu_fb_consume2 = _T_386 & _T_1; // @[el2_ifu_aln_ctl.scala 254:22] - assign io_ifu_i0_bp_index = 7'h0; // @[el2_ifu_aln_ctl.scala 361:22] - assign io_ifu_i0_bp_fghr = misc0eff[7:0]; // @[el2_ifu_aln_ctl.scala 363:21] - assign io_ifu_i0_bp_btag = 5'h0; // @[el2_ifu_aln_ctl.scala 365:21] - assign io_ifu_pmu_instr_aligned = io_dec_i0_decode_d & _T_3; // @[el2_ifu_aln_ctl.scala 95:28] - assign io_ifu_i0_cinst = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 106:19] - assign io_i0_brp_valid = alignbrend[0]; // @[el2_ifu_aln_ctl.scala 340:19] - assign io_i0_brp_toffset = misc0eff[19:8]; // @[el2_ifu_aln_ctl.scala 348:21] - assign io_i0_brp_hist = {alignhist1[0],alignhist0[0]}; // @[el2_ifu_aln_ctl.scala 345:18] - assign io_i0_brp_br_error = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 358:22] - assign io_i0_brp_br_start_error = 1'h0; // @[el2_ifu_aln_ctl.scala 352:29] - assign io_i0_brp_bank = 1'h0; // @[el2_ifu_aln_ctl.scala 354:29] - assign io_i0_brp_prett = misc0eff[50:20]; // @[el2_ifu_aln_ctl.scala 350:19] - assign io_i0_brp_way = alignway[0]; // @[el2_ifu_aln_ctl.scala 344:17] - assign io_i0_brp_ret = alignret[0]; // @[el2_ifu_aln_ctl.scala 342:17] - assign decompressed_io_din = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 101:23] + assign io_ifu_i0_valid = _T_656 | _T_657; // @[el2_ifu_aln_ctl.scala 336:19] + assign io_ifu_i0_icaf = _T_664 | _T_665; // @[el2_ifu_aln_ctl.scala 338:18] + assign io_ifu_i0_icaf_type = _T_678 ? f1ictype : f0ictype; // @[el2_ifu_aln_ctl.scala 340:23] + assign io_ifu_i0_icaf_f1 = _T_683 & _T_516; // @[el2_ifu_aln_ctl.scala 344:21] + assign io_ifu_i0_dbecc = _T_689 | _T_690; // @[el2_ifu_aln_ctl.scala 346:19] + assign io_ifu_i0_instr = _T_695 | _T_696; // @[el2_ifu_aln_ctl.scala 352:19] + assign io_ifu_i0_pc = {{1'd0}, f0pc}; // @[el2_ifu_aln_ctl.scala 324:16] + assign io_ifu_i0_pc4 = aligndata[1:0] == 2'h3; // @[el2_ifu_aln_ctl.scala 328:17] + assign io_ifu_fb_consume1 = _T_313 & _T_1; // @[el2_ifu_aln_ctl.scala 242:22] + assign io_ifu_fb_consume2 = _T_316 & _T_1; // @[el2_ifu_aln_ctl.scala 243:22] + assign io_ifu_i0_bp_index = _T_776[6:0]; // @[el2_ifu_aln_ctl.scala 384:22] + assign io_ifu_i0_bp_fghr = i0_ends_f1 ? f1fghr : f0fghr; // @[el2_ifu_aln_ctl.scala 386:21] + assign io_ifu_i0_bp_btag = _T_737 ? firstbrtag_hash : secondbrtag_hash; // @[el2_ifu_aln_ctl.scala 388:21] + assign io_ifu_pmu_instr_aligned = io_dec_i0_decode_d & _T_784; // @[el2_ifu_aln_ctl.scala 394:28] + assign io_ifu_i0_cinst = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 330:19] + assign io_i0_brp_valid = _T_721 | _T_725; // @[el2_ifu_aln_ctl.scala 362:19] + assign io_i0_brp_toffset = i0_ends_f1 ? f1poffset : f0poffset; // @[el2_ifu_aln_ctl.scala 374:21] + assign io_i0_brp_hist = {_T_746,_T_751}; // @[el2_ifu_aln_ctl.scala 370:18] + assign io_i0_brp_br_error = _T_768 | _T_771; // @[el2_ifu_aln_ctl.scala 382:22] + assign io_i0_brp_br_start_error = _T_656 & alignbrend[0]; // @[el2_ifu_aln_ctl.scala 378:29] + assign io_i0_brp_bank = _T_737 ? f0pc[1] : secondpc[1]; // @[el2_ifu_aln_ctl.scala 380:29] + assign io_i0_brp_prett = i0_ends_f1 ? f1prett : f0prett; // @[el2_ifu_aln_ctl.scala 376:19] + assign io_i0_brp_way = _T_737 ? alignway[0] : alignway[1]; // @[el2_ifu_aln_ctl.scala 368:17] + assign io_i0_brp_ret = _T_728 | _T_730; // @[el2_ifu_aln_ctl.scala 364:17] + assign decompressed_io_din = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 390:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -887,39 +1048,45 @@ initial begin _RAND_0 = {1{`RANDOM}}; error_stall = _RAND_0[0:0]; _RAND_1 = {1{`RANDOM}}; - f0val = _RAND_1[1:0]; + wrptr = _RAND_1[1:0]; _RAND_2 = {1{`RANDOM}}; rdptr = _RAND_2[1:0]; _RAND_3 = {1{`RANDOM}}; - q1off = _RAND_3[0:0]; + f2val = _RAND_3[1:0]; _RAND_4 = {1{`RANDOM}}; - q2off = _RAND_4[0:0]; + f1val = _RAND_4[1:0]; _RAND_5 = {1{`RANDOM}}; - q0off = _RAND_5[0:0]; + f0val = _RAND_5[1:0]; _RAND_6 = {1{`RANDOM}}; - q1 = _RAND_6[31:0]; + q2off = _RAND_6[0:0]; _RAND_7 = {1{`RANDOM}}; - q0 = _RAND_7[31:0]; + q1off = _RAND_7[0:0]; _RAND_8 = {1{`RANDOM}}; - q2 = _RAND_8[31:0]; - _RAND_9 = {2{`RANDOM}}; - _T_768 = _RAND_9[54:0]; - _RAND_10 = {2{`RANDOM}}; - _T_770 = _RAND_10[54:0]; - _RAND_11 = {2{`RANDOM}}; - _T_766 = _RAND_11[54:0]; + q0off = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + q1 = _RAND_9[31:0]; + _RAND_10 = {1{`RANDOM}}; + q0 = _RAND_10[31:0]; + _RAND_11 = {1{`RANDOM}}; + q2 = _RAND_11[31:0]; _RAND_12 = {1{`RANDOM}}; - f1val = _RAND_12[1:0]; + f2pc = _RAND_12[30:0]; _RAND_13 = {1{`RANDOM}}; - wrptr = _RAND_13[1:0]; + f1pc = _RAND_13[30:0]; _RAND_14 = {1{`RANDOM}}; - f2val = _RAND_14[1:0]; + f0pc = _RAND_14[30:0]; _RAND_15 = {1{`RANDOM}}; - brdata1 = _RAND_15[11:0]; + brdata2 = _RAND_15[11:0]; _RAND_16 = {1{`RANDOM}}; - brdata0 = _RAND_16[11:0]; + brdata1 = _RAND_16[11:0]; _RAND_17 = {1{`RANDOM}}; - brdata2 = _RAND_17[11:0]; + brdata0 = _RAND_17[11:0]; + _RAND_18 = {2{`RANDOM}}; + _T_14 = _RAND_18[54:0]; + _RAND_19 = {2{`RANDOM}}; + _T_16 = _RAND_19[54:0]; + _RAND_20 = {2{`RANDOM}}; + _T_18 = _RAND_20[54:0]; `endif // RANDOMIZE_REG_INIT `endif // RANDOMIZE end // initial @@ -934,29 +1101,19 @@ end // initial error_stall <= error_stall_in; end if (reset) begin - f0val <= 2'h0; + wrptr <= 2'h0; end else begin - f0val <= _T_485; + wrptr <= wrptr_in; end if (reset) begin rdptr <= 2'h0; end else begin - rdptr <= wrptr_in; + rdptr <= rdptr_in; end if (reset) begin - q1off <= 1'h0; + f2val <= 2'h0; end else begin - q1off <= q1off_in; - end - if (reset) begin - q2off <= 1'h0; - end else begin - q2off <= q2off_in; - end - if (reset) begin - q0off <= 1'h0; - end else begin - q0off <= q0off_in; + f2val <= f2val_in; end if (reset) begin f1val <= 2'h0; @@ -964,14 +1121,24 @@ end // initial f1val <= f1val_in; end if (reset) begin - wrptr <= 2'h0; + f0val <= 2'h0; end else begin - wrptr <= wrptr_in; + f0val <= f0val_in; end if (reset) begin - f2val <= 2'h0; + q2off <= 1'h0; end else begin - f2val <= f2val_in; + q2off <= q2off_in; + end + if (reset) begin + q1off <= 1'h0; + end else begin + q1off <= q1off_in; + end + if (reset) begin + q0off <= 1'h0; + end else begin + q0off <= q0off_in; end end always @(posedge clock) begin @@ -991,19 +1158,24 @@ end // initial q2 <= io_ifu_fetch_data_f; end if (reset) begin - _T_768 <= 55'h0; - end else if (qwen[1]) begin - _T_768 <= misc_data_in; + f2pc <= 31'h0; + end else if (fetch_to_f2) begin + f2pc <= io_ifu_fetch_pc; end if (reset) begin - _T_770 <= 55'h0; - end else if (qwen[0]) begin - _T_770 <= misc_data_in; + f1pc <= 31'h0; + end else if (f1_shift_wr_en) begin + f1pc <= f1pc_in; end if (reset) begin - _T_766 <= 55'h0; + f0pc <= 31'h0; + end else if (f0_shift_wr_en) begin + f0pc <= f0pc_in; + end + if (reset) begin + brdata2 <= 12'h0; end else if (qwen[2]) begin - _T_766 <= misc_data_in; + brdata2 <= brdata_in; end if (reset) begin brdata1 <= 12'h0; @@ -1016,9 +1188,19 @@ end // initial brdata0 <= brdata_in; end if (reset) begin - brdata2 <= 12'h0; + _T_14 <= 55'h0; end else if (qwen[2]) begin - brdata2 <= brdata_in; + _T_14 <= misc_data_in; + end + if (reset) begin + _T_16 <= 55'h0; + end else if (qwen[1]) begin + _T_16 <= misc_data_in; + end + if (reset) begin + _T_18 <= 55'h0; + end else if (qwen[0]) begin + _T_18 <= misc_data_in; end end endmodule diff --git a/src/main/scala/ifu/el2_ifu_aln_ctl.scala b/src/main/scala/ifu/el2_ifu_aln_ctl.scala index 7d09f76d..21883867 100644 --- a/src/main/scala/ifu/el2_ifu_aln_ctl.scala +++ b/src/main/scala/ifu/el2_ifu_aln_ctl.scala @@ -92,12 +92,21 @@ class el2_ifu_aln_ctl extends Module with el2_lib { val f0pc_in = WireInit(UInt(31.W), 0.U) val error_stall = WireInit(Bool(), 0.U) val f2_wr_en = WireInit(Bool(), 0.U) + val shift_4B = WireInit(Bool(), 0.U) val f1_shift_wr_en = WireInit(Bool(), 0.U) val f0_shift_wr_en = WireInit(Bool(), 0.U) val qwen = WireInit(UInt(3.W), 0.U) val brdata_in = WireInit(UInt(BRDATA_SIZE.W), 0.U) val misc_data_in = WireInit(UInt((MHI+1).W), 0.U) + val fetch_to_f0 = WireInit(Bool(), 0.U) + val fetch_to_f1 = WireInit(Bool(), 0.U) + val fetch_to_f2 = WireInit(Bool(), 0.U) + val f1_shift_2B = WireInit(Bool(), 0.U) + val first4B = WireInit(Bool(), 0.U) + val shift_2B = WireInit(Bool(), 0.U) + val f0_shift_2B = WireInit(Bool(), 0.U) + error_stall_in := (error_stall | io.ifu_async_error_start) & !io.exu_flush_final error_stall := withClock(io.active_clk) {RegNext(error_stall_in, init = 0.U)} @@ -170,7 +179,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib { val q1sel = Cat(q1ptr, !q1ptr) - val misc_data_in = Cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f, io.ic_access_fault_type_f, + misc_data_in := Cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f, io.ic_access_fault_type_f, io.ifu_bp_btb_target_f(31,1), io.ifu_bp_poffset_f, io.ifu_bp_fghr_f) val misceff = Mux1H(Seq(qren(0).asBool() -> Cat(misc1, misc0), @@ -205,6 +214,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib { val (brdata0eff,brdata1eff) = (brdataeff(11,0) , brdataeff(23,12)) + val brdata0final = Mux1H(Seq(q0sel(0).asBool -> brdata0eff, q0sel(1).asBool -> brdata0eff(11,6))) val brdata1final = Mux1H(Seq(q1sel(0).asBool -> brdata1eff, q1sel(1).asBool -> brdata1eff(11,6))) val f0ret = Cat(brdata0final(6),brdata0final(0)) @@ -238,12 +248,12 @@ class el2_ifu_aln_ctl extends Module with el2_lib { shift_f2_f0 := !sf0_valid & !sf1_valid & f2_valid shift_f2_f1 := !sf0_valid & sf1_valid & f2_valid - val fetch_to_f0 = !sf0_valid & !sf1_valid & !f2_valid & ifvalid - val fetch_to_f1 = (!sf0_valid & !sf1_valid & f2_valid & ifvalid) | + fetch_to_f0 := !sf0_valid & !sf1_valid & !f2_valid & ifvalid + fetch_to_f1 := (!sf0_valid & !sf1_valid & f2_valid & ifvalid) | (!sf0_valid & sf1_valid & !f2_valid & ifvalid) | ( sf0_valid & !sf1_valid & !f2_valid & ifvalid) - val fetch_to_f2 = (!sf0_valid & sf1_valid & f2_valid & ifvalid) | + fetch_to_f2 := (!sf0_valid & sf1_valid & f2_valid & ifvalid) | ( sf0_valid & sf1_valid & !f2_valid & ifvalid) val f0pc_plus1 = f0pc + 1.U @@ -270,102 +280,29 @@ class el2_ifu_aln_ctl extends Module with el2_lib { (shift_f2_f1 & !io.exu_flush_final).asBool->f2val, (!fetch_to_f1 & !shift_f2_f1 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf1val)) - sf0val := Mux1H(Seq(shift_2B.asBool->Cat(0.U, f0val(1),))) - - - - - - - - - - - - - - - - - - - - - - - - - - - val i0_shift = io.dec_i0_decode_d & ~error_stall - - io.ifu_pmu_instr_aligned := i0_shift - - val aligndata = Mux1H(Seq(f0val(0).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final,q0final))) - - val decompressed = Module(new el2_ifu_compress_ctl()) - - decompressed.io.din := aligndata - - io.ifu_i0_instr := decompressed.io.dout - - // 16-bit compressed instruction from the aligner to the dec for tracer - io.ifu_i0_cinst := aligndata(15,0) - - // Checking if its a 32-bit instruction or not - //val first4B = decompressed.io.rvc - val first4B = WireInit(Bool(), 0.U) - val first2B = ~first4B - val alignicaf = Mux1H(Seq(f0val(1).asBool -> f0icaf, (~f0val(1) & f0val(0)).asBool -> Cat(f1icaf,f0icaf))) - - io.ifu_i0_icaf := Mux1H(Seq(first4B.asBool -> alignicaf.orR, first2B.asBool -> alignicaf(0))) - io.ifu_i0_valid := Mux1H(Seq(first4B.asBool -> alignval(1), first2B.asBool -> alignval(0))) - io.ifu_i0_pc4 := first4B - - val shift_2B = i0_shift & first2B - val shift_4B = i0_shift & first4B - val f0_shift_2B = Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (!f0val(0) & f0val(0)))) - val f1_shift_2B = f0val(0) & !f0val(1) & shift_4B - - - - val qeff = Mux1H(Seq(qren(0).asBool->Cat(q1,q0), - qren(1).asBool->Cat(q2,q1), - qren(2).asBool->Cat(q0,q2))) - val (q1eff, q0eff) = (qeff(63,32), qeff(31,0)) - val brdata0final = Mux1H(Seq(q0sel(0).asBool -> brdata0eff, q0sel(1).asBool -> brdata0eff(11,6))) - - - - - - - - - //val f0pc = WireInit(UInt(31.W), 0.U) - // val f2pc = WireInit(UInt(31.W), 0.U) - - - - - - - - - - f0val := Mux1H(Seq(shift_2B.asBool -> f0val(1), (!shift_2B & !shift_4B).asBool -> f0val)) + sf0val := Mux1H(Seq(shift_2B.asBool->Cat(0.U, f0val(1)), + (!shift_2B & !shift_4B).asBool->f1val)) f0val_in := Mux1H(Seq((fetch_to_f0 & !io.exu_flush_final).asBool->io.ifu_fetch_val, - (shift_f2_f0 & !io.exu_flush_final).asBool->f2val, - (shift_f1_f0 & !io.exu_flush_final).asBool()->sf1val, - (!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf0val)) + (shift_f2_f0 & !io.exu_flush_final).asBool->f2val, + (shift_f1_f0 & !io.exu_flush_final).asBool()->sf1val, + (!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf0val)) + + val qeff = Mux1H(Seq(qren(0).asBool->Cat(q1,q0), + qren(1).asBool->Cat(q2,q1), + qren(2).asBool->Cat(q0,q2))) + val (q1eff, q0eff) = (qeff(63,32), qeff(31,0)) q0final := Mux1H(Seq(q0sel(0).asBool->q0eff, q0sel(1).asBool->q0eff(31,16))) q1final := Mux1H(Seq(q1sel(0).asBool->q1eff(15,0), q1sel(1).asBool->q1eff(31,16))) + val aligndata = Mux1H(Seq(f0val(0).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final,q0final))) + alignval := Mux1H(Seq(f0val(1).asBool->3.U, (!f0val(1) & f0val(0)) -> Cat(f1val(0),1.U))) + val alignicaf = Mux1H(Seq(f0val(1).asBool -> f0icaf, (~f0val(1) & f0val(0)).asBool -> Cat(f1icaf,f0icaf))) + val aligndbecc = Mux1H(Seq(f0val(1).asBool -> Fill(2,f0dbecc), (!f0val(1) & f0val(0)).asBool -> Cat(f1dbecc,f0dbecc))) val alignbrend = Mux1H(Seq(f0val(1).asBool()->f0brend, (!f0val(1) & f0val(0)).asBool->Cat(f1brend(0),f0brend(0)))) @@ -382,14 +319,24 @@ class el2_ifu_aln_ctl extends Module with el2_lib { val alignfromf1 = !f0val(1) & f0val(0) - //val f1pc = WireInit(UInt(31.W), init = 0.U) - val secondpc = Mux1H(Seq(f0val(1).asBool()->f0pc_plus1 , (!f0val(1) & f0val(0)).asBool->f1pc)) io.ifu_i0_pc := f0pc val firstpc = f0pc + io.ifu_i0_pc4 := first4B + + io.ifu_i0_cinst := aligndata(15,0) + + first4B := aligndata(1,0) === 3.U + + val first2B = ~first4B + + io.ifu_i0_valid := Mux1H(Seq(first4B.asBool -> alignval(1), first2B.asBool -> alignval(0))) + + io.ifu_i0_icaf := Mux1H(Seq(first4B.asBool -> alignicaf.orR, first2B.asBool -> alignicaf(0))) + io.ifu_i0_icaf_type := Mux((first4B & !f0val(1) & f0val(0) & !alignicaf(0) & !aligndbecc(0)).asBool, f1ictype, f0ictype) val icaf_eff = alignicaf(1) | aligndbecc(1) @@ -398,6 +345,12 @@ class el2_ifu_aln_ctl extends Module with el2_lib { io.ifu_i0_dbecc := Mux1H(Seq(first4B.asBool->aligndbecc.orR, first2B.asBool->aligndbecc(0))) + val ifirst = aligndata + + val decompressed = Module(new el2_ifu_compress_ctl()) + + io.ifu_i0_instr := Mux1H(Seq(first4B.asBool -> ifirst, first2B.asBool -> decompressed.io.dout)) + val firstpc_hash = el2_btb_addr_hash(f0pc) val secondpc_hash = el2_btb_addr_hash(secondpc) @@ -410,22 +363,23 @@ class el2_ifu_aln_ctl extends Module with el2_lib { io.i0_brp.ret := (first2B & alignret(0)) | (first4B & alignret(1)) + val i0_brp_pc4 = (first2B & alignpc4(0)) | (first4B & alignpc4(1)) + io.i0_brp.way := Mux((first2B | alignbrend(0)).asBool, alignway(0), alignway(1)) + io.i0_brp.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)), (first2B & alignhist0(0)) | (first4B & alignhist0(1))) - io.i0_brp.toffset := Mux((first4B & alignfromf1).asBool, f1poffset, f0poffset) + val i0_ends_f1 = first4B & alignfromf1 + io.i0_brp.toffset := Mux(i0_ends_f1.asBool, f1poffset, f0poffset) - io.i0_brp.prett := Mux((first4B & alignfromf1).asBool, f1prett, f0prett) + io.i0_brp.prett := Mux(i0_ends_f1.asBool, f1prett, f0prett) io.i0_brp.br_start_error := (first4B & alignval(1) & alignbrend(0)) io.i0_brp.bank := Mux((first2B | alignbrend(0)).asBool, firstpc(1), secondpc(1)) - val i0_brp_pc4 = (first2B & alignpc4(0)) | (first4B & alignpc4(1)) - - io.i0_brp.br_error := (io.i0_brp.valid & i0_brp_pc4 & first2B) | (io.i0_brp.valid & ~i0_brp_pc4 & first4B) - + io.i0_brp.br_error := (io.i0_brp.valid & i0_brp_pc4 & first2B) | (io.i0_brp.valid & !i0_brp_pc4 & first4B) io.ifu_i0_bp_index := Mux((first2B | alignbrend(0)).asBool, firstpc_hash, secondpc_hash) @@ -433,10 +387,17 @@ class el2_ifu_aln_ctl extends Module with el2_lib { io.ifu_i0_bp_btag := Mux((first2B | alignbrend(0)).asBool, firstbrtag_hash, secondbrtag_hash) + decompressed.io.din := aligndata + val i0_shift = io.dec_i0_decode_d & ~error_stall + io.ifu_pmu_instr_aligned := i0_shift + shift_2B := i0_shift & first2B + shift_4B := i0_shift & first4B + f0_shift_2B := Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (!f0val(0) & f0val(0)))) + f1_shift_2B := f0val(0) & !f0val(1) & shift_4B } object ifu_aln extends App { diff --git a/src/main/scala/lsu/el2_lsu.scala b/src/main/scala/lsu/el2_lsu.scala deleted file mode 100644 index dba9130d..00000000 --- a/src/main/scala/lsu/el2_lsu.scala +++ /dev/null @@ -1,5 +0,0 @@ -package lsu - -class el2_lsu { - -} diff --git a/target/scala-2.12/classes/META-INF/chisel-module-template.kotlin_module b/target/scala-2.12/classes/META-INF/chisel-module-template.kotlin_module new file mode 100644 index 0000000000000000000000000000000000000000..a49347afef10a9b5f95305e1058ba36adec7d6dd GIT binary patch literal 16 RcmZQzU|?ooU|@t|0RRA102TlM literal 0 HcmV?d00001 diff --git a/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class index bd4d7f18f9a27e20bd7c9449e531350b022236fb..ec89fc237f8f9b45afbef516ead529308503610c 100644 GIT binary patch literal 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