From c6879c2b933c92c54ee3c3c6b688fa16f2b2f0b7 Mon Sep 17 00:00:00 2001
From: waleed-lm <waleed.ehsan@lampromellon.com>
Date: Wed, 14 Oct 2020 11:25:12 +0500
Subject: [PATCH] Aligner Updated

---
 el2_ifu_ic_mem.fir                            |  16 ++++++++--------
 el2_ifu_ic_mem.v                              |  16 +++++++---------
 src/main/scala/ifu/el2_ifu_ic_mem.scala       |   4 ++--
 .../classes/ifu/el2_ifu_ic_mem$$anon$1.class  | Bin 5236 -> 5268 bytes
 target/scala-2.12/classes/ifu/ifu_ic$.class   | Bin 3860 -> 3868 bytes
 5 files changed, 17 insertions(+), 19 deletions(-)

diff --git a/el2_ifu_ic_mem.fir b/el2_ifu_ic_mem.fir
index f859420e..c736e942 100644
--- a/el2_ifu_ic_mem.fir
+++ b/el2_ifu_ic_mem.fir
@@ -3,13 +3,13 @@ circuit el2_ifu_ic_mem :
   module el2_ifu_ic_mem : 
     input clock : Clock
     input reset : UInt<1>
-    output io : {flip clk : UInt<1>, flip rst_l : UInt<1>, flip clk_override : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip ic_rw_addr : UInt<31>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, ic_debug_rd_data : UInt<71>, ictag_debug_rd_data : UInt<26>, flip ic_debug_wr_data : UInt<71>, ic_eccerr : UInt<2>, ic_parerr : UInt<2>, flip ic_tag_valid : UInt<2>, ic_rd_hit : UInt<2>, ic_tag_perr : UInt<1>, flip scan_mode : UInt<1>}
+    output io : {flip clk_override : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip ic_rw_addr : UInt<31>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, ic_debug_rd_data : UInt<71>, ictag_debug_rd_data : UInt<26>, flip ic_debug_wr_data : UInt<71>, ic_eccerr : UInt<2>, ic_parerr : UInt<2>, flip ic_tag_valid : UInt<2>, ic_rd_hit : UInt<2>, ic_tag_perr : UInt<1>, flip scan_mode : UInt<1>}
     
-    io.ic_tag_perr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 34:18]
-    io.ic_rd_hit <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 35:16]
-    io.ic_parerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 36:16]
-    io.ic_eccerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 37:16]
-    io.ictag_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 38:26]
-    io.ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 39:23]
-    io.ic_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 40:17]
+    io.ic_tag_perr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 32:18]
+    io.ic_rd_hit <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 33:16]
+    io.ic_parerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 34:16]
+    io.ic_eccerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 35:16]
+    io.ictag_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 36:26]
+    io.ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 37:23]
+    io.ic_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 38:17]
     
diff --git a/el2_ifu_ic_mem.v b/el2_ifu_ic_mem.v
index 6c5fcd82..96b8459a 100644
--- a/el2_ifu_ic_mem.v
+++ b/el2_ifu_ic_mem.v
@@ -1,8 +1,6 @@
 module el2_ifu_ic_mem(
   input         clock,
   input         reset,
-  input         io_clk,
-  input         io_rst_l,
   input         io_clk_override,
   input         io_dec_tlu_core_ecc_disable,
   input  [30:0] io_ic_rw_addr,
@@ -28,11 +26,11 @@ module el2_ifu_ic_mem(
   output        io_ic_tag_perr,
   input         io_scan_mode
 );
-  assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 40:17]
-  assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 39:23]
-  assign io_ictag_debug_rd_data = 26'h0; // @[el2_ifu_ic_mem.scala 38:26]
-  assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 37:16]
-  assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 36:16]
-  assign io_ic_rd_hit = 2'h0; // @[el2_ifu_ic_mem.scala 35:16]
-  assign io_ic_tag_perr = 1'h0; // @[el2_ifu_ic_mem.scala 34:18]
+  assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 38:17]
+  assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 37:23]
+  assign io_ictag_debug_rd_data = 26'h0; // @[el2_ifu_ic_mem.scala 36:26]
+  assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 35:16]
+  assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 34:16]
+  assign io_ic_rd_hit = 2'h0; // @[el2_ifu_ic_mem.scala 33:16]
+  assign io_ic_tag_perr = 1'h0; // @[el2_ifu_ic_mem.scala 32:18]
 endmodule
diff --git a/src/main/scala/ifu/el2_ifu_ic_mem.scala b/src/main/scala/ifu/el2_ifu_ic_mem.scala
index e113821f..c3da481d 100644
--- a/src/main/scala/ifu/el2_ifu_ic_mem.scala
+++ b/src/main/scala/ifu/el2_ifu_ic_mem.scala
@@ -17,7 +17,7 @@ class el2_ifu_ic_mem extends Module with param{
     val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
     val ic_premux_data = Input(UInt(64.W))
     val ic_sel_premux_data = Input(Bool())
-    val ic_wr_data = Vec(ICACHE_BANKS_WAY, Input(UInt(71.W)))
+    val ic_wr_data = Input(Vec(ICACHE_BANKS_WAY, Input(UInt(71.W))))
     val ic_rd_data = Output(UInt(64.W))
     val ic_debug_rd_data = Output(UInt(71.W))
     val ictag_debug_rd_data = Output(UInt(26.W))
@@ -230,5 +230,5 @@ class EL2_IC_DATA extends Module with el2_lib {
 }
 
 object ifu_ic extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new EL2_IC_TAG()))
+  println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ic_mem()))
 }
\ No newline at end of file
diff --git a/target/scala-2.12/classes/ifu/el2_ifu_ic_mem$$anon$1.class b/target/scala-2.12/classes/ifu/el2_ifu_ic_mem$$anon$1.class
index 0d81cdd866259d055b077c8070a41df43984d3da..d1a35a7b00d407b33733f43cd7e301b2143c5603 100644
GIT binary patch
delta 1505
zcmaKr&ubGw6vw~2X_{p7JDaBYS*tc`qcKYT{evnfQWeBXTZ)L55Nb47f3(t*5D-Q1
zQl|$&^yI0hCTX^{+BU6K!Gr&Tc=6yt5WETEbZ0`-*+rHeX5RbE_q}=Z=J$@tPUZ98
z`9%Qx@TsIs+0Qz&*Yo#sg|1A0E^EV#1aIANVQlpF*l33hngsuO!Ftq%5zIL-i#G}#
z9!Ut2<)&aoa@ZwlfhfvQ$6AyOB>Dl?)C>+y(}|2FIyUP@J8I;YOHCzkfUZUSn20+V
zPQEJ52JLPUR=9RMj+<zo6mciRZJSvt<eD?&UQg7;#kQD=ofgI19N%hst}`O;VL0)*
zjOXeRVK3KCnrfdDaUa8N+gRpg!qs>#Klg6u-Y*-x0o@xh)cT?rL}fA~o#>_aE8b(D
zhzC)lE#P8(fx|dLR}1u)af#Y?nbvqf6lq~GQ)yFtP{czFf95fk__D~ha_Nkz^c4{g
zGu*a^7qRGREOCT;_j2#z25*#lzj=%$&Wb@|Jf|+xoN^)_XE?d#HJ*1^gcDqQziCV5
zMZAsS>J8jvw{0mwp)*(#l|SBbNqRu;_|vC0&0@NYyBh9msMIHqYp7PymnvhvjHhKx
z_)ch;)bL!xi#qeRhL=?gtTCi55J|H2V8foMaSsUw(mh;rr-msbp{rh9SNRV$MBM(Q
zHLGXf_s7~<206C3sNrEls!ysICPiP^o-gSwyhOZecmE1nr0)pH3R>me2+O^Q$m590
zuMm@05tn};VX>gi5{FHH3?WuO{upQ_QNTO;7?!D~RYJk%gB2^}wR%u}Pfbm98?dSe
PwBiH#sTQpt=?eb<n3gZK

delta 1478
zcma)*%}*0S7{;I7vb5c9+g-L4+EV;TQ7FW!_yK+d4F_XHjTkh9AR$eo)h42X@n%Sj
zUPy=;4kktq9yu6n>7pP=6)#?lCl4O{7d&t?F%CPU)Y&C5n@o0Qe(y8S`_8;GZR@S-
zr(cUJ01n{eD|Ob_9nN0M-^mp^Gv_D9$0o*8Ud&4{`h?Y^8g9b!ql^WW4i6<nNTnuH
zs`L9KX^AA%(bQWint?<=KuOP|YmWZNSf*pGz39UV`4TYGNgSec5kDs4euk4DYOO=N
zM}$?by&cD0v`>n7fZ^U9%nG>`hz2)}YJ7Jm6C*GG*$vveF^8v9;vpgKDdn2)X%P=I
zoLteI`JNGBoonxM&G)Q`8w~gE<{5q0s`IVmVy&)5FNk6$!~5FMPw!W}#{m(KVB@)I
z>|LN6N9b(Hei|3)S_gOZJXr0ho*q#NI%_;AibuKiJ+5^a67dFxlXD?wjfX|Jk!$aD
z)gBS?7{k5$ct)Q?)fvUP*nU^BtSFY?c&96#6Y(a7llx(3UROmp$+Zu<UUy!^n;C9i
z#|?Jfo)_@bKX^hVO}{6RM@D;BYyopc+_rGnLaB^_bP=zMm@4A2e!{|xg(nuC{sG>s
z;#nD&HyAQ)#5&k~uqr0LMa)o|Oc}|3JAQbRZ?`bJMa0N|QKO{UXi>7ZqcJ@ZXO40#
zcGALwzt)N0Y>}2p#_YLNLcR1AQRycd<ZWn_dl8fKh|AMR$YnIi-;k8o(d-GrYqvm@
w6^*w5EguS4q%H7{HiIIepzBbuO4iK7W`!=*&@kY=-6;w_kWge&S)()j2J?9(`v3p{

diff --git a/target/scala-2.12/classes/ifu/ifu_ic$.class b/target/scala-2.12/classes/ifu/ifu_ic$.class
index 5239241fc5b20595c130ffa3cf9a6bdc40bfef1e..a4f398066a29ee92dce7f717e3f14ca6d5948aac 100644
GIT binary patch
delta 57
vcmbOtH%D&66&4*a4NafSv{L=l9HV$39iN#TpPQO%&B!2xDZ2RwiwqY4HCz+B

delta 48
rcmbOuH$`s46&4jC4NafSv{HRnAES6r=lBpucWXulK2(uStTJ2xWH$|`