diff --git a/ifu_bp_ctl.fir b/ifu_bp_ctl.fir
index 8ab8e7bd..eaf72a1e 100644
--- a/ifu_bp_ctl.fir
+++ b/ifu_bp_ctl.fir
@@ -13275,7 +13275,7 @@ circuit ifu_bp_ctl :
   module ifu_bp_ctl : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip active_clk : Clock, flip ic_hit_f : UInt<1>, flip exu_flush_final : UInt<1>, flip ifc_fetch_addr_f : UInt<31>, flip ifc_fetch_req_f : UInt<1>, dec_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}, flip dec_tlu_flush_lower_wb : UInt<1>, flip exu_bp : {exu_i0_br_index_r : UInt<8>, exu_i0_br_fghr_r : UInt<8>, exu_i0_br_way_r : UInt<1>, exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, exu_mp_eghr : UInt<8>, exu_mp_fghr : UInt<8>, exu_mp_index : UInt<8>, exu_mp_btag : UInt<5>}, flip dec_fa_error_index : UInt<9>, ifu_bp_hit_taken_f : UInt<1>, ifu_bp_btb_target_f : UInt<31>, ifu_bp_inst_mask_f : UInt<1>, ifu_bp_fghr_f : UInt<8>, ifu_bp_way_f : UInt<2>, ifu_bp_ret_f : UInt<2>, ifu_bp_hist1_f : UInt<2>, ifu_bp_hist0_f : UInt<2>, ifu_bp_pc4_f : UInt<2>, ifu_bp_valid_f : UInt<2>, ifu_bp_poffset_f : UInt<12>, ifu_bp_fa_index_f : UInt<9>[2], flip scan_mode : UInt<1>}
+    output io : {flip active_clk : Clock, flip ic_hit_f : UInt<1>, flip exu_flush_final : UInt<1>, flip ifc_fetch_addr_f : UInt<31>, flip ifc_fetch_req_f : UInt<1>, dec_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}, flip dec_tlu_flush_lower_wb : UInt<1>, flip exu_bp : {exu_i0_br_index_r : UInt<8>, exu_i0_br_fghr_r : UInt<8>, exu_i0_br_way_r : UInt<1>, exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, exu_mp_eghr : UInt<8>, exu_mp_fghr : UInt<8>, exu_mp_index : UInt<8>, exu_mp_btag : UInt<5>}, flip dec_fa_error_index : UInt<4>, ifu_bp_hit_taken_f : UInt<1>, ifu_bp_btb_target_f : UInt<31>, ifu_bp_inst_mask_f : UInt<1>, ifu_bp_fghr_f : UInt<8>, ifu_bp_way_f : UInt<2>, ifu_bp_ret_f : UInt<2>, ifu_bp_hist1_f : UInt<2>, ifu_bp_hist0_f : UInt<2>, ifu_bp_pc4_f : UInt<2>, ifu_bp_valid_f : UInt<2>, ifu_bp_poffset_f : UInt<12>, ifu_bp_fa_index_f : UInt<4>[2], flip scan_mode : UInt<1>}
     
     io.ifu_bp_fa_index_f[0] <= UInt<1>("h00") @[ifu_bp_ctl.scala 35:24]
     io.ifu_bp_fa_index_f[1] <= UInt<1>("h00") @[ifu_bp_ctl.scala 35:24]
diff --git a/ifu_bp_ctl.v b/ifu_bp_ctl.v
index 541bdcb0..e3654622 100644
--- a/ifu_bp_ctl.v
+++ b/ifu_bp_ctl.v
@@ -54,7 +54,7 @@ module ifu_bp_ctl(
   input  [7:0]  io_exu_bp_exu_mp_fghr,
   input  [7:0]  io_exu_bp_exu_mp_index,
   input  [4:0]  io_exu_bp_exu_mp_btag,
-  input  [8:0]  io_dec_fa_error_index,
+  input  [3:0]  io_dec_fa_error_index,
   output        io_ifu_bp_hit_taken_f,
   output [30:0] io_ifu_bp_btb_target_f,
   output        io_ifu_bp_inst_mask_f,
@@ -66,8 +66,8 @@ module ifu_bp_ctl(
   output [1:0]  io_ifu_bp_pc4_f,
   output [1:0]  io_ifu_bp_valid_f,
   output [11:0] io_ifu_bp_poffset_f,
-  output [8:0]  io_ifu_bp_fa_index_f_0,
-  output [8:0]  io_ifu_bp_fa_index_f_1,
+  output [3:0]  io_ifu_bp_fa_index_f_0,
+  output [3:0]  io_ifu_bp_fa_index_f_1,
   input         io_scan_mode
 );
 `ifdef RANDOMIZE_REG_INIT
@@ -12784,8 +12784,8 @@ module ifu_bp_ctl(
   assign io_ifu_bp_pc4_f = 2'h0; // @[ifu_bp_ctl.scala 346:19]
   assign io_ifu_bp_valid_f = vwayhit_f & _T_351; // @[ifu_bp_ctl.scala 348:21]
   assign io_ifu_bp_poffset_f = 12'h0; // @[ifu_bp_ctl.scala 361:23]
-  assign io_ifu_bp_fa_index_f_0 = 9'h0; // @[ifu_bp_ctl.scala 35:24]
-  assign io_ifu_bp_fa_index_f_1 = 9'h0; // @[ifu_bp_ctl.scala 35:24]
+  assign io_ifu_bp_fa_index_f_0 = 4'h0; // @[ifu_bp_ctl.scala 35:24]
+  assign io_ifu_bp_fa_index_f_1 = 4'h0; // @[ifu_bp_ctl.scala 35:24]
   assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18]
   assign rvclkhdr_io_en = io_ifc_fetch_req_f | exu_mp_valid; // @[lib.scala 402:17]
   assign rvclkhdr_1_io_clk = clock; // @[lib.scala 401:18]
diff --git a/src/main/scala/lib/param.scala b/src/main/scala/lib/param.scala
index dcb00436..ca21d26b 100644
--- a/src/main/scala/lib/param.scala
+++ b/src/main/scala/lib/param.scala
@@ -7,7 +7,7 @@ trait param {
   val BHT_ARRAY_DEPTH        = 	0x100
   val BHT_GHR_HASH_1         = 	0x0
   val BHT_GHR_SIZE           = 	0x8
-  val BHT_SIZE               = 	0x200
+  val BHT_SIZE               = 	0x010
   val BTB_ADDR_HI            = 	0x09
   val BTB_ADDR_LO            = 	0x2
   val BTB_ARRAY_DEPTH        = 	0x100
@@ -20,7 +20,7 @@ trait param {
   val BTB_INDEX2_LO          = 	0x0A
   val BTB_INDEX3_HI          = 	0x19
   val BTB_INDEX3_LO          = 	0x12
-  val BTB_SIZE               = 	0x200
+  val BTB_SIZE               = 	0x010
   val BUILD_AHB_LITE         = 	0x0
   val BUILD_AXI4             = 	0x1
   val BUILD_AXI_NATIVE       = 	0x1
diff --git a/target/scala-2.12/classes/lib/param.class b/target/scala-2.12/classes/lib/param.class
index e50bfbf9..2ea839cb 100644
Binary files a/target/scala-2.12/classes/lib/param.class and b/target/scala-2.12/classes/lib/param.class differ