diff --git a/quasar_wrapper.fir b/quasar_wrapper.fir index 91774f39..c4e30559 100644 --- a/quasar_wrapper.fir +++ b/quasar_wrapper.fir @@ -2322,7 +2322,7 @@ circuit quasar_wrapper : module ifu_mem_ctl : input clock : Clock input reset : AsyncReset - output io : {flip free_clk : Clock, flip active_clk : Clock, flip exu_flush_final : UInt<1>, dec_mem_ctrl : {flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, flip ifc_fetch_addr_bf : UInt<31>, flip ifc_fetch_uncacheable_bf : UInt<1>, flip ifc_fetch_req_bf : UInt<1>, flip ifc_fetch_req_bf_raw : UInt<1>, flip ifc_iccm_access_bf : UInt<1>, flip ifc_region_acc_fault_bf : UInt<1>, flip ifc_dma_access_ok : UInt<1>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_inst_mask_f : UInt<1>, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip ifu_bus_clk_en : UInt<1>, dma_mem_ctl : {flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>}, iccm : {rw_addr : UInt<15>, buf_correct_ecc : UInt<1>, correction_state : UInt<1>, wren : UInt<1>, rden : UInt<1>, wr_size : UInt<3>, wr_data : UInt<78>, flip rd_data : UInt<64>, flip rd_data_ecc : UInt<78>}, ic : {rw_addr : UInt<31>, tag_valid : UInt<2>, wr_en : UInt<2>, rd_en : UInt<1>, wr_data : UInt<71>[2], debug_wr_data : UInt<71>, debug_addr : UInt<10>, flip rd_data : UInt<64>, flip debug_rd_data : UInt<71>, flip tag_debug_rd_data : UInt<26>, flip eccerr : UInt<2>, flip parerr : UInt<2>, flip rd_hit : UInt<2>, flip tag_perr : UInt<1>, debug_rd_en : UInt<1>, debug_wr_en : UInt<1>, debug_tag_array : UInt<1>, debug_way : UInt<2>, premux_data : UInt<64>, sel_premux_data : UInt<1>}, flip ifu_fetch_val : UInt<2>, ifu_ic_mb_empty : UInt<1>, ic_dma_active : UInt<1>, ic_write_stall : UInt<1>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, iccm_rd_ecc_double_err : UInt<1>, iccm_dma_sb_error : UInt<1>, ic_hit_f : UInt<1>, ic_access_fault_f : UInt<1>, ic_access_fault_type_f : UInt<2>, ifu_async_error_start : UInt<1>, ic_fetch_val_f : UInt<2>, ic_data_f : UInt<32>, flip scan_mode : UInt<1>} + output io : {flip free_clk : Clock, flip active_clk : Clock, flip exu_flush_final : UInt<1>, dec_mem_ctrl : {flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, flip ifc_fetch_addr_bf : UInt<31>, flip ifc_fetch_uncacheable_bf : UInt<1>, flip ifc_fetch_req_bf : UInt<1>, flip ifc_fetch_req_bf_raw : UInt<1>, flip ifc_iccm_access_bf : UInt<1>, flip ifc_region_acc_fault_bf : UInt<1>, flip ifc_dma_access_ok : UInt<1>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_inst_mask_f : UInt<1>, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip ifu_bus_clk_en : UInt<1>, dma_mem_ctl : {flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>}, iccm : {rw_addr : UInt<15>, buf_correct_ecc : UInt<1>, correction_state : UInt<1>, wren : UInt<1>, rden : UInt<1>, wr_size : UInt<3>, wr_data : UInt<78>, flip rd_data : UInt<64>, flip rd_data_ecc : UInt<78>}, ic : {rw_addr : UInt<31>, tag_valid : UInt<2>, wr_en : UInt<2>, rd_en : UInt<1>, wr_data : UInt<71>[2], debug_wr_data : UInt<71>, debug_addr : UInt<10>, flip rd_data : UInt<64>, flip debug_rd_data : UInt<71>, flip tag_debug_rd_data : UInt<26>, flip eccerr : UInt<2>, flip parerr : UInt<2>, flip rd_hit : UInt<2>, flip tag_perr : UInt<1>, debug_rd_en : UInt<1>, debug_wr_en : UInt<1>, debug_tag_array : UInt<1>, debug_way : UInt<2>, premux_data : UInt<64>, sel_premux_data : UInt<1>}, flip ifu_fetch_val : UInt<2>, ifu_ic_mb_empty : UInt<1>, ic_dma_active : UInt<1>, ic_write_stall : UInt<1>, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, iccm_rd_ecc_double_err : UInt<1>, iccm_dma_sb_error : UInt<1>, ic_hit_f : UInt<1>, ic_access_fault_f : UInt<1>, ic_access_fault_type_f : UInt<2>, ifu_async_error_start : UInt<1>, ic_fetch_val_f : UInt<2>, ic_data_f : UInt<32>, flip scan_mode : UInt<1>} io.ifu_axi.w.valid <= UInt<1>("h00") @[ifu_mem_ctl.scala 57:22] io.ifu_axi.w.bits.data <= UInt<1>("h00") @[ifu_mem_ctl.scala 58:26] @@ -6133,21 +6133,21 @@ circuit quasar_wrapper : node _T_2512 = eq(UInt<3>("h01"), perr_state) @[Conditional.scala 37:30] when _T_2512 : @[Conditional.scala 39:67] perr_nxtstate <= UInt<3>("h00") @[ifu_mem_ctl.scala 422:21] - node _T_2513 = or(io.dec_mem_ctrl.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 423:63] + node _T_2513 = or(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 423:50] perr_state_en <= _T_2513 @[ifu_mem_ctl.scala 423:21] - node _T_2514 = and(io.dec_mem_ctrl.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_flush_err_wb) @[ifu_mem_ctl.scala 424:69] + node _T_2514 = and(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_flush_err_wb) @[ifu_mem_ctl.scala 424:56] perr_sel_invalidate <= _T_2514 @[ifu_mem_ctl.scala 424:27] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2515 = eq(UInt<3>("h02"), perr_state) @[Conditional.scala 37:30] when _T_2515 : @[Conditional.scala 39:67] node _T_2516 = eq(io.dec_mem_ctrl.dec_tlu_flush_err_wb, UInt<1>("h00")) @[ifu_mem_ctl.scala 427:30] - node _T_2517 = and(_T_2516, io.dec_mem_ctrl.dec_tlu_flush_lower_wb) @[ifu_mem_ctl.scala 427:68] - node _T_2518 = or(_T_2517, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 427:111] - node _T_2519 = bits(_T_2518, 0, 0) @[ifu_mem_ctl.scala 427:155] + node _T_2517 = and(_T_2516, io.dec_tlu_flush_lower_wb) @[ifu_mem_ctl.scala 427:68] + node _T_2518 = or(_T_2517, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 427:98] + node _T_2519 = bits(_T_2518, 0, 0) @[ifu_mem_ctl.scala 427:142] node _T_2520 = mux(_T_2519, UInt<3>("h00"), UInt<3>("h03")) @[ifu_mem_ctl.scala 427:27] perr_nxtstate <= _T_2520 @[ifu_mem_ctl.scala 427:21] - node _T_2521 = or(io.dec_mem_ctrl.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 428:63] + node _T_2521 = or(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 428:50] perr_state_en <= _T_2521 @[ifu_mem_ctl.scala 428:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] @@ -6185,9 +6185,9 @@ circuit quasar_wrapper : else : @[Conditional.scala 39:67] node _T_2531 = eq(UInt<2>("h01"), err_stop_state) @[Conditional.scala 37:30] when _T_2531 : @[Conditional.scala 39:67] - node _T_2532 = or(io.dec_mem_ctrl.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 450:72] - node _T_2533 = or(_T_2532, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 450:112] - node _T_2534 = bits(_T_2533, 0, 0) @[ifu_mem_ctl.scala 450:156] + node _T_2532 = or(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 450:59] + node _T_2533 = or(_T_2532, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 450:99] + node _T_2534 = bits(_T_2533, 0, 0) @[ifu_mem_ctl.scala 450:143] node _T_2535 = eq(io.ifu_fetch_val, UInt<2>("h03")) @[ifu_mem_ctl.scala 451:31] node _T_2536 = bits(io.ifu_fetch_val, 0, 0) @[ifu_mem_ctl.scala 451:56] node _T_2537 = and(_T_2536, two_byte_instr) @[ifu_mem_ctl.scala 451:59] @@ -6199,11 +6199,11 @@ circuit quasar_wrapper : node _T_2543 = mux(_T_2539, UInt<2>("h03"), _T_2542) @[ifu_mem_ctl.scala 451:12] node _T_2544 = mux(_T_2534, UInt<2>("h00"), _T_2543) @[ifu_mem_ctl.scala 450:31] err_stop_nxtstate <= _T_2544 @[ifu_mem_ctl.scala 450:25] - node _T_2545 = or(io.dec_mem_ctrl.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 453:67] - node _T_2546 = bits(io.ifu_fetch_val, 0, 0) @[ifu_mem_ctl.scala 453:125] - node _T_2547 = or(_T_2545, _T_2546) @[ifu_mem_ctl.scala 453:107] - node _T_2548 = or(_T_2547, ifu_bp_hit_taken_q_f) @[ifu_mem_ctl.scala 453:129] - node _T_2549 = or(_T_2548, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 453:152] + node _T_2545 = or(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 453:54] + node _T_2546 = bits(io.ifu_fetch_val, 0, 0) @[ifu_mem_ctl.scala 453:112] + node _T_2547 = or(_T_2545, _T_2546) @[ifu_mem_ctl.scala 453:94] + node _T_2548 = or(_T_2547, ifu_bp_hit_taken_q_f) @[ifu_mem_ctl.scala 453:116] + node _T_2549 = or(_T_2548, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 453:139] err_stop_state_en <= _T_2549 @[ifu_mem_ctl.scala 453:25] node _T_2550 = bits(io.ifu_fetch_val, 1, 0) @[ifu_mem_ctl.scala 454:43] node _T_2551 = eq(_T_2550, UInt<2>("h03")) @[ifu_mem_ctl.scala 454:48] @@ -6219,18 +6219,18 @@ circuit quasar_wrapper : else : @[Conditional.scala 39:67] node _T_2558 = eq(UInt<2>("h02"), err_stop_state) @[Conditional.scala 37:30] when _T_2558 : @[Conditional.scala 39:67] - node _T_2559 = or(io.dec_mem_ctrl.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 458:72] - node _T_2560 = or(_T_2559, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 458:112] - node _T_2561 = bits(_T_2560, 0, 0) @[ifu_mem_ctl.scala 458:150] + node _T_2559 = or(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 458:59] + node _T_2560 = or(_T_2559, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 458:99] + node _T_2561 = bits(_T_2560, 0, 0) @[ifu_mem_ctl.scala 458:137] node _T_2562 = bits(io.ifu_fetch_val, 0, 0) @[ifu_mem_ctl.scala 459:46] node _T_2563 = bits(_T_2562, 0, 0) @[ifu_mem_ctl.scala 459:50] node _T_2564 = mux(_T_2563, UInt<2>("h03"), UInt<2>("h02")) @[ifu_mem_ctl.scala 459:29] node _T_2565 = mux(_T_2561, UInt<2>("h00"), _T_2564) @[ifu_mem_ctl.scala 458:31] err_stop_nxtstate <= _T_2565 @[ifu_mem_ctl.scala 458:25] - node _T_2566 = or(io.dec_mem_ctrl.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 460:67] - node _T_2567 = bits(io.ifu_fetch_val, 0, 0) @[ifu_mem_ctl.scala 460:125] - node _T_2568 = or(_T_2566, _T_2567) @[ifu_mem_ctl.scala 460:107] - node _T_2569 = or(_T_2568, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 460:129] + node _T_2566 = or(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 460:54] + node _T_2567 = bits(io.ifu_fetch_val, 0, 0) @[ifu_mem_ctl.scala 460:112] + node _T_2568 = or(_T_2566, _T_2567) @[ifu_mem_ctl.scala 460:94] + node _T_2569 = or(_T_2568, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 460:116] err_stop_state_en <= _T_2569 @[ifu_mem_ctl.scala 460:25] node _T_2570 = bits(io.ifu_fetch_val, 0, 0) @[ifu_mem_ctl.scala 461:41] node _T_2571 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_mem_ctl.scala 461:47] @@ -6243,17 +6243,17 @@ circuit quasar_wrapper : else : @[Conditional.scala 39:67] node _T_2575 = eq(UInt<2>("h03"), err_stop_state) @[Conditional.scala 37:30] when _T_2575 : @[Conditional.scala 39:67] - node _T_2576 = eq(io.dec_mem_ctrl.dec_tlu_flush_err_wb, UInt<1>("h00")) @[ifu_mem_ctl.scala 465:75] - node _T_2577 = and(io.dec_mem_ctrl.dec_tlu_flush_lower_wb, _T_2576) @[ifu_mem_ctl.scala 465:73] - node _T_2578 = or(_T_2577, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 465:114] - node _T_2579 = or(_T_2578, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 465:154] - node _T_2580 = bits(_T_2579, 0, 0) @[ifu_mem_ctl.scala 465:192] + node _T_2576 = eq(io.dec_mem_ctrl.dec_tlu_flush_err_wb, UInt<1>("h00")) @[ifu_mem_ctl.scala 465:62] + node _T_2577 = and(io.dec_tlu_flush_lower_wb, _T_2576) @[ifu_mem_ctl.scala 465:60] + node _T_2578 = or(_T_2577, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 465:101] + node _T_2579 = or(_T_2578, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 465:141] + node _T_2580 = bits(_T_2579, 0, 0) @[ifu_mem_ctl.scala 465:179] node _T_2581 = bits(io.dec_mem_ctrl.dec_tlu_flush_err_wb, 0, 0) @[ifu_mem_ctl.scala 466:73] node _T_2582 = mux(_T_2581, UInt<2>("h01"), UInt<2>("h03")) @[ifu_mem_ctl.scala 466:29] node _T_2583 = mux(_T_2580, UInt<2>("h00"), _T_2582) @[ifu_mem_ctl.scala 465:31] err_stop_nxtstate <= _T_2583 @[ifu_mem_ctl.scala 465:25] - node _T_2584 = or(io.dec_mem_ctrl.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 467:67] - node _T_2585 = or(_T_2584, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 467:107] + node _T_2584 = or(io.dec_tlu_flush_lower_wb, io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) @[ifu_mem_ctl.scala 467:54] + node _T_2585 = or(_T_2584, io.dec_mem_ctrl.dec_tlu_force_halt) @[ifu_mem_ctl.scala 467:94] err_stop_state_en <= _T_2585 @[ifu_mem_ctl.scala 467:25] err_stop_fetch <= UInt<1>("h01") @[ifu_mem_ctl.scala 468:22] io.iccm.correction_state <= UInt<1>("h01") @[ifu_mem_ctl.scala 469:32] @@ -29106,7 +29106,7 @@ circuit quasar_wrapper : module ifu_bp_ctl : input clock : Clock input reset : AsyncReset - output io : {flip active_clk : Clock, flip ic_hit_f : UInt<1>, flip exu_flush_final : UInt<1>, flip ifc_fetch_addr_f : UInt<31>, flip ifc_fetch_req_f : UInt<1>, dec_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}, flip exu_bp : {exu_i0_br_index_r : UInt<8>, exu_i0_br_fghr_r : UInt<8>, exu_i0_br_way_r : UInt<1>, exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, exu_mp_eghr : UInt<8>, exu_mp_fghr : UInt<8>, exu_mp_index : UInt<8>, exu_mp_btag : UInt<5>}, ifu_bp_hit_taken_f : UInt<1>, ifu_bp_btb_target_f : UInt<31>, ifu_bp_inst_mask_f : UInt<1>, ifu_bp_fghr_f : UInt<8>, ifu_bp_way_f : UInt<2>, ifu_bp_ret_f : UInt<2>, ifu_bp_hist1_f : UInt<2>, ifu_bp_hist0_f : UInt<2>, ifu_bp_pc4_f : UInt<2>, ifu_bp_valid_f : UInt<2>, ifu_bp_poffset_f : UInt<12>, flip scan_mode : UInt<1>} + output io : {flip active_clk : Clock, flip ic_hit_f : UInt<1>, flip exu_flush_final : UInt<1>, flip ifc_fetch_addr_f : UInt<31>, flip ifc_fetch_req_f : UInt<1>, dec_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}, flip dec_tlu_flush_lower_wb : UInt<1>, flip exu_bp : {exu_i0_br_index_r : UInt<8>, exu_i0_br_fghr_r : UInt<8>, exu_i0_br_way_r : UInt<1>, exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, exu_mp_eghr : UInt<8>, exu_mp_fghr : UInt<8>, exu_mp_index : UInt<8>, exu_mp_btag : UInt<5>}, ifu_bp_hit_taken_f : UInt<1>, ifu_bp_btb_target_f : UInt<31>, ifu_bp_inst_mask_f : UInt<1>, ifu_bp_fghr_f : UInt<8>, ifu_bp_way_f : UInt<2>, ifu_bp_ret_f : UInt<2>, ifu_bp_hist1_f : UInt<2>, ifu_bp_hist0_f : UInt<2>, ifu_bp_pc4_f : UInt<2>, ifu_bp_valid_f : UInt<2>, ifu_bp_poffset_f : UInt<12>, flip scan_mode : UInt<1>} wire leak_one_f : UInt<1> leak_one_f <= UInt<1>("h00") @@ -29130,40 +29130,40 @@ circuit quasar_wrapper : btb_lru_b0_f <= UInt<1>("h00") wire dec_tlu_way_wb : UInt<1> dec_tlu_way_wb <= UInt<1>("h00") - node _T = eq(leak_one_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 59:58] - node exu_mp_valid = and(io.exu_bp.exu_mp_pkt.bits.misp, _T) @[ifu_bp_ctl.scala 59:56] - node _T_1 = or(io.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error, io.dec_bp.dec_tlu_br0_r_pkt.bits.br_error) @[ifu_bp_ctl.scala 81:50] - dec_tlu_error_wb <= _T_1 @[ifu_bp_ctl.scala 81:20] - btb_error_addr_wb <= io.exu_bp.exu_i0_br_index_r @[ifu_bp_ctl.scala 82:21] - dec_tlu_way_wb <= io.dec_bp.dec_tlu_br0_r_pkt.bits.way @[ifu_bp_ctl.scala 83:18] + node _T = eq(leak_one_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 60:58] + node exu_mp_valid = and(io.exu_bp.exu_mp_pkt.bits.misp, _T) @[ifu_bp_ctl.scala 60:56] + node _T_1 = or(io.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error, io.dec_bp.dec_tlu_br0_r_pkt.bits.br_error) @[ifu_bp_ctl.scala 82:50] + dec_tlu_error_wb <= _T_1 @[ifu_bp_ctl.scala 82:20] + btb_error_addr_wb <= io.exu_bp.exu_i0_br_index_r @[ifu_bp_ctl.scala 83:21] + dec_tlu_way_wb <= io.dec_bp.dec_tlu_br0_r_pkt.bits.way @[ifu_bp_ctl.scala 84:18] node _T_2 = bits(io.ifc_fetch_addr_f, 8, 1) @[lib.scala 35:13] node _T_3 = bits(io.ifc_fetch_addr_f, 16, 9) @[lib.scala 35:51] node _T_4 = xor(_T_2, _T_3) @[lib.scala 35:47] node _T_5 = bits(io.ifc_fetch_addr_f, 24, 17) @[lib.scala 35:89] node btb_rd_addr_f = xor(_T_4, _T_5) @[lib.scala 35:85] - node _T_6 = bits(io.ifc_fetch_addr_f, 30, 1) @[ifu_bp_ctl.scala 89:44] - node _T_7 = add(_T_6, UInt<1>("h01")) @[ifu_bp_ctl.scala 89:51] - node fetch_addr_p1_f = tail(_T_7, 1) @[ifu_bp_ctl.scala 89:51] + node _T_6 = bits(io.ifc_fetch_addr_f, 30, 1) @[ifu_bp_ctl.scala 90:44] + node _T_7 = add(_T_6, UInt<1>("h01")) @[ifu_bp_ctl.scala 90:51] + node fetch_addr_p1_f = tail(_T_7, 1) @[ifu_bp_ctl.scala 90:51] node _T_8 = cat(fetch_addr_p1_f, UInt<1>("h00")) @[Cat.scala 29:58] node _T_9 = bits(_T_8, 8, 1) @[lib.scala 35:13] node _T_10 = bits(_T_8, 16, 9) @[lib.scala 35:51] node _T_11 = xor(_T_9, _T_10) @[lib.scala 35:47] node _T_12 = bits(_T_8, 24, 17) @[lib.scala 35:89] node btb_rd_addr_p1_f = xor(_T_11, _T_12) @[lib.scala 35:85] - node _T_13 = bits(bht_dir_f, 0, 0) @[ifu_bp_ctl.scala 95:33] - node _T_14 = not(_T_13) @[ifu_bp_ctl.scala 95:23] - node _T_15 = bits(bht_dir_f, 0, 0) @[ifu_bp_ctl.scala 95:46] + node _T_13 = bits(bht_dir_f, 0, 0) @[ifu_bp_ctl.scala 96:33] + node _T_14 = not(_T_13) @[ifu_bp_ctl.scala 96:23] + node _T_15 = bits(bht_dir_f, 0, 0) @[ifu_bp_ctl.scala 96:46] node btb_sel_f = cat(_T_14, _T_15) @[Cat.scala 29:58] - node _T_16 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 98:46] - node _T_17 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 98:70] - node _T_18 = not(_T_17) @[ifu_bp_ctl.scala 98:50] + node _T_16 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 99:46] + node _T_17 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 99:70] + node _T_18 = not(_T_17) @[ifu_bp_ctl.scala 99:50] node fetch_start_f = cat(_T_16, _T_18) @[Cat.scala 29:58] - node _T_19 = eq(btb_error_addr_wb, btb_rd_addr_f) @[ifu_bp_ctl.scala 101:72] - node branch_error_collision_f = and(dec_tlu_error_wb, _T_19) @[ifu_bp_ctl.scala 101:51] - node _T_20 = eq(btb_error_addr_wb, btb_rd_addr_p1_f) @[ifu_bp_ctl.scala 102:75] - node branch_error_collision_p1_f = and(dec_tlu_error_wb, _T_20) @[ifu_bp_ctl.scala 102:54] - node branch_error_bank_conflict_f = and(branch_error_collision_f, dec_tlu_error_wb) @[ifu_bp_ctl.scala 105:63] - node branch_error_bank_conflict_p1_f = and(branch_error_collision_p1_f, dec_tlu_error_wb) @[ifu_bp_ctl.scala 106:69] + node _T_19 = eq(btb_error_addr_wb, btb_rd_addr_f) @[ifu_bp_ctl.scala 102:72] + node branch_error_collision_f = and(dec_tlu_error_wb, _T_19) @[ifu_bp_ctl.scala 102:51] + node _T_20 = eq(btb_error_addr_wb, btb_rd_addr_p1_f) @[ifu_bp_ctl.scala 103:75] + node branch_error_collision_p1_f = and(dec_tlu_error_wb, _T_20) @[ifu_bp_ctl.scala 103:54] + node branch_error_bank_conflict_f = and(branch_error_collision_f, dec_tlu_error_wb) @[ifu_bp_ctl.scala 106:63] + node branch_error_bank_conflict_p1_f = and(branch_error_collision_p1_f, dec_tlu_error_wb) @[ifu_bp_ctl.scala 107:69] node _T_21 = bits(io.ifc_fetch_addr_f, 13, 9) @[lib.scala 26:32] node _T_22 = bits(io.ifc_fetch_addr_f, 18, 14) @[lib.scala 26:32] node _T_23 = bits(io.ifc_fetch_addr_f, 23, 19) @[lib.scala 26:32] @@ -29183,167 +29183,167 @@ circuit quasar_wrapper : _T_30[2] <= _T_29 @[lib.scala 26:24] node _T_31 = xor(_T_30[0], _T_30[1]) @[lib.scala 26:111] node fetch_rd_tag_p1_f = xor(_T_31, _T_30[2]) @[lib.scala 26:111] - node _T_32 = eq(io.exu_bp.exu_mp_btag, fetch_rd_tag_f) @[ifu_bp_ctl.scala 113:53] - node _T_33 = and(_T_32, exu_mp_valid) @[ifu_bp_ctl.scala 113:73] - node _T_34 = and(_T_33, io.ifc_fetch_req_f) @[ifu_bp_ctl.scala 113:88] - node _T_35 = eq(io.exu_bp.exu_mp_index, btb_rd_addr_f) @[ifu_bp_ctl.scala 113:124] - node fetch_mp_collision_f = and(_T_34, _T_35) @[ifu_bp_ctl.scala 113:109] - node _T_36 = eq(io.exu_bp.exu_mp_btag, fetch_rd_tag_p1_f) @[ifu_bp_ctl.scala 114:56] - node _T_37 = and(_T_36, exu_mp_valid) @[ifu_bp_ctl.scala 114:79] - node _T_38 = and(_T_37, io.ifc_fetch_req_f) @[ifu_bp_ctl.scala 114:94] - node _T_39 = eq(io.exu_bp.exu_mp_index, btb_rd_addr_p1_f) @[ifu_bp_ctl.scala 114:130] - node fetch_mp_collision_p1_f = and(_T_38, _T_39) @[ifu_bp_ctl.scala 114:115] - reg leak_one_f_d1 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_bp_ctl.scala 116:56] - leak_one_f_d1 <= leak_one_f @[ifu_bp_ctl.scala 116:56] - reg dec_tlu_way_wb_f : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_bp_ctl.scala 117:59] - dec_tlu_way_wb_f <= dec_tlu_way_wb @[ifu_bp_ctl.scala 117:59] - reg exu_mp_way_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_bp_ctl.scala 118:55] - exu_mp_way_f <= io.exu_bp.exu_mp_pkt.bits.way @[ifu_bp_ctl.scala 118:55] - reg exu_flush_final_d1 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_bp_ctl.scala 119:61] - exu_flush_final_d1 <= io.exu_flush_final @[ifu_bp_ctl.scala 119:61] - node _T_40 = and(io.dec_bp.dec_tlu_flush_leak_one_wb, io.dec_bp.dec_tlu_flush_lower_wb) @[ifu_bp_ctl.scala 122:54] - node _T_41 = eq(io.dec_bp.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[ifu_bp_ctl.scala 122:109] - node _T_42 = and(leak_one_f_d1, _T_41) @[ifu_bp_ctl.scala 122:107] - node _T_43 = or(_T_40, _T_42) @[ifu_bp_ctl.scala 122:90] - leak_one_f <= _T_43 @[ifu_bp_ctl.scala 122:14] - node _T_44 = bits(btb_bank0_rd_data_way0_f, 0, 0) @[ifu_bp_ctl.scala 126:50] - node _T_45 = bits(btb_bank0_rd_data_way0_f, 21, 17) @[ifu_bp_ctl.scala 126:82] - node _T_46 = eq(_T_45, fetch_rd_tag_f) @[ifu_bp_ctl.scala 126:97] - node _T_47 = and(_T_44, _T_46) @[ifu_bp_ctl.scala 126:55] - node _T_48 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[ifu_bp_ctl.scala 127:44] - node _T_49 = eq(_T_48, UInt<1>("h00")) @[ifu_bp_ctl.scala 127:25] - node _T_50 = and(_T_47, _T_49) @[ifu_bp_ctl.scala 126:117] - node _T_51 = and(_T_50, io.ifc_fetch_req_f) @[ifu_bp_ctl.scala 127:76] - node _T_52 = eq(leak_one_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 127:99] - node tag_match_way0_f = and(_T_51, _T_52) @[ifu_bp_ctl.scala 127:97] - node _T_53 = bits(btb_bank0_rd_data_way1_f, 0, 0) @[ifu_bp_ctl.scala 130:50] - node _T_54 = bits(btb_bank0_rd_data_way1_f, 21, 17) @[ifu_bp_ctl.scala 130:82] - node _T_55 = eq(_T_54, fetch_rd_tag_f) @[ifu_bp_ctl.scala 130:97] - node _T_56 = and(_T_53, _T_55) @[ifu_bp_ctl.scala 130:55] - node _T_57 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[ifu_bp_ctl.scala 131:44] - node _T_58 = eq(_T_57, UInt<1>("h00")) @[ifu_bp_ctl.scala 131:25] - node _T_59 = and(_T_56, _T_58) @[ifu_bp_ctl.scala 130:117] - node _T_60 = and(_T_59, io.ifc_fetch_req_f) @[ifu_bp_ctl.scala 131:76] - node _T_61 = eq(leak_one_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 131:99] - node tag_match_way1_f = and(_T_60, _T_61) @[ifu_bp_ctl.scala 131:97] - node _T_62 = bits(btb_bank0_rd_data_way0_p1_f, 0, 0) @[ifu_bp_ctl.scala 134:56] - node _T_63 = bits(btb_bank0_rd_data_way0_p1_f, 21, 17) @[ifu_bp_ctl.scala 134:91] - node _T_64 = eq(_T_63, fetch_rd_tag_p1_f) @[ifu_bp_ctl.scala 134:106] - node _T_65 = and(_T_62, _T_64) @[ifu_bp_ctl.scala 134:61] - node _T_66 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_p1_f) @[ifu_bp_ctl.scala 135:24] - node _T_67 = eq(_T_66, UInt<1>("h00")) @[ifu_bp_ctl.scala 135:5] - node _T_68 = and(_T_65, _T_67) @[ifu_bp_ctl.scala 134:129] - node _T_69 = and(_T_68, io.ifc_fetch_req_f) @[ifu_bp_ctl.scala 135:59] - node _T_70 = eq(leak_one_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 135:82] - node tag_match_way0_p1_f = and(_T_69, _T_70) @[ifu_bp_ctl.scala 135:80] - node _T_71 = bits(btb_bank0_rd_data_way1_p1_f, 0, 0) @[ifu_bp_ctl.scala 137:56] - node _T_72 = bits(btb_bank0_rd_data_way1_p1_f, 21, 17) @[ifu_bp_ctl.scala 137:91] - node _T_73 = eq(_T_72, fetch_rd_tag_p1_f) @[ifu_bp_ctl.scala 137:106] - node _T_74 = and(_T_71, _T_73) @[ifu_bp_ctl.scala 137:61] - node _T_75 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_p1_f) @[ifu_bp_ctl.scala 138:24] - node _T_76 = eq(_T_75, UInt<1>("h00")) @[ifu_bp_ctl.scala 138:5] - node _T_77 = and(_T_74, _T_76) @[ifu_bp_ctl.scala 137:129] - node _T_78 = and(_T_77, io.ifc_fetch_req_f) @[ifu_bp_ctl.scala 138:59] - node _T_79 = eq(leak_one_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 138:82] - node tag_match_way1_p1_f = and(_T_78, _T_79) @[ifu_bp_ctl.scala 138:80] - node _T_80 = bits(btb_bank0_rd_data_way0_f, 3, 3) @[ifu_bp_ctl.scala 141:84] - node _T_81 = bits(btb_bank0_rd_data_way0_f, 4, 4) @[ifu_bp_ctl.scala 141:117] - node _T_82 = xor(_T_80, _T_81) @[ifu_bp_ctl.scala 141:91] - node _T_83 = and(tag_match_way0_f, _T_82) @[ifu_bp_ctl.scala 141:56] - node _T_84 = bits(btb_bank0_rd_data_way0_f, 3, 3) @[ifu_bp_ctl.scala 142:84] - node _T_85 = bits(btb_bank0_rd_data_way0_f, 4, 4) @[ifu_bp_ctl.scala 142:117] - node _T_86 = xor(_T_84, _T_85) @[ifu_bp_ctl.scala 142:91] - node _T_87 = eq(_T_86, UInt<1>("h00")) @[ifu_bp_ctl.scala 142:58] - node _T_88 = and(tag_match_way0_f, _T_87) @[ifu_bp_ctl.scala 142:56] + node _T_32 = eq(io.exu_bp.exu_mp_btag, fetch_rd_tag_f) @[ifu_bp_ctl.scala 114:53] + node _T_33 = and(_T_32, exu_mp_valid) @[ifu_bp_ctl.scala 114:73] + node _T_34 = and(_T_33, io.ifc_fetch_req_f) @[ifu_bp_ctl.scala 114:88] + node _T_35 = eq(io.exu_bp.exu_mp_index, btb_rd_addr_f) @[ifu_bp_ctl.scala 114:124] + node fetch_mp_collision_f = and(_T_34, _T_35) @[ifu_bp_ctl.scala 114:109] + node _T_36 = eq(io.exu_bp.exu_mp_btag, fetch_rd_tag_p1_f) @[ifu_bp_ctl.scala 115:56] + node _T_37 = and(_T_36, exu_mp_valid) @[ifu_bp_ctl.scala 115:79] + node _T_38 = and(_T_37, io.ifc_fetch_req_f) @[ifu_bp_ctl.scala 115:94] + node _T_39 = eq(io.exu_bp.exu_mp_index, btb_rd_addr_p1_f) @[ifu_bp_ctl.scala 115:130] + node fetch_mp_collision_p1_f = and(_T_38, _T_39) @[ifu_bp_ctl.scala 115:115] + reg leak_one_f_d1 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_bp_ctl.scala 117:56] + leak_one_f_d1 <= leak_one_f @[ifu_bp_ctl.scala 117:56] + reg dec_tlu_way_wb_f : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_bp_ctl.scala 118:59] + dec_tlu_way_wb_f <= dec_tlu_way_wb @[ifu_bp_ctl.scala 118:59] + reg exu_mp_way_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_bp_ctl.scala 119:55] + exu_mp_way_f <= io.exu_bp.exu_mp_pkt.bits.way @[ifu_bp_ctl.scala 119:55] + reg exu_flush_final_d1 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_bp_ctl.scala 120:61] + exu_flush_final_d1 <= io.exu_flush_final @[ifu_bp_ctl.scala 120:61] + node _T_40 = and(io.dec_bp.dec_tlu_flush_leak_one_wb, io.dec_tlu_flush_lower_wb) @[ifu_bp_ctl.scala 123:54] + node _T_41 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[ifu_bp_ctl.scala 123:102] + node _T_42 = and(leak_one_f_d1, _T_41) @[ifu_bp_ctl.scala 123:100] + node _T_43 = or(_T_40, _T_42) @[ifu_bp_ctl.scala 123:83] + leak_one_f <= _T_43 @[ifu_bp_ctl.scala 123:14] + node _T_44 = bits(btb_bank0_rd_data_way0_f, 0, 0) @[ifu_bp_ctl.scala 127:50] + node _T_45 = bits(btb_bank0_rd_data_way0_f, 21, 17) @[ifu_bp_ctl.scala 127:82] + node _T_46 = eq(_T_45, fetch_rd_tag_f) @[ifu_bp_ctl.scala 127:97] + node _T_47 = and(_T_44, _T_46) @[ifu_bp_ctl.scala 127:55] + node _T_48 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[ifu_bp_ctl.scala 128:44] + node _T_49 = eq(_T_48, UInt<1>("h00")) @[ifu_bp_ctl.scala 128:25] + node _T_50 = and(_T_47, _T_49) @[ifu_bp_ctl.scala 127:117] + node _T_51 = and(_T_50, io.ifc_fetch_req_f) @[ifu_bp_ctl.scala 128:76] + node _T_52 = eq(leak_one_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 128:99] + node tag_match_way0_f = and(_T_51, _T_52) @[ifu_bp_ctl.scala 128:97] + node _T_53 = bits(btb_bank0_rd_data_way1_f, 0, 0) @[ifu_bp_ctl.scala 131:50] + node _T_54 = bits(btb_bank0_rd_data_way1_f, 21, 17) @[ifu_bp_ctl.scala 131:82] + node _T_55 = eq(_T_54, fetch_rd_tag_f) @[ifu_bp_ctl.scala 131:97] + node _T_56 = and(_T_53, _T_55) @[ifu_bp_ctl.scala 131:55] + node _T_57 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[ifu_bp_ctl.scala 132:44] + node _T_58 = eq(_T_57, UInt<1>("h00")) @[ifu_bp_ctl.scala 132:25] + node _T_59 = and(_T_56, _T_58) @[ifu_bp_ctl.scala 131:117] + node _T_60 = and(_T_59, io.ifc_fetch_req_f) @[ifu_bp_ctl.scala 132:76] + node _T_61 = eq(leak_one_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 132:99] + node tag_match_way1_f = and(_T_60, _T_61) @[ifu_bp_ctl.scala 132:97] + node _T_62 = bits(btb_bank0_rd_data_way0_p1_f, 0, 0) @[ifu_bp_ctl.scala 135:56] + node _T_63 = bits(btb_bank0_rd_data_way0_p1_f, 21, 17) @[ifu_bp_ctl.scala 135:91] + node _T_64 = eq(_T_63, fetch_rd_tag_p1_f) @[ifu_bp_ctl.scala 135:106] + node _T_65 = and(_T_62, _T_64) @[ifu_bp_ctl.scala 135:61] + node _T_66 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_p1_f) @[ifu_bp_ctl.scala 136:24] + node _T_67 = eq(_T_66, UInt<1>("h00")) @[ifu_bp_ctl.scala 136:5] + node _T_68 = and(_T_65, _T_67) @[ifu_bp_ctl.scala 135:129] + node _T_69 = and(_T_68, io.ifc_fetch_req_f) @[ifu_bp_ctl.scala 136:59] + node _T_70 = eq(leak_one_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 136:82] + node tag_match_way0_p1_f = and(_T_69, _T_70) @[ifu_bp_ctl.scala 136:80] + node _T_71 = bits(btb_bank0_rd_data_way1_p1_f, 0, 0) @[ifu_bp_ctl.scala 138:56] + node _T_72 = bits(btb_bank0_rd_data_way1_p1_f, 21, 17) @[ifu_bp_ctl.scala 138:91] + node _T_73 = eq(_T_72, fetch_rd_tag_p1_f) @[ifu_bp_ctl.scala 138:106] + node _T_74 = and(_T_71, _T_73) @[ifu_bp_ctl.scala 138:61] + node _T_75 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_p1_f) @[ifu_bp_ctl.scala 139:24] + node _T_76 = eq(_T_75, UInt<1>("h00")) @[ifu_bp_ctl.scala 139:5] + node _T_77 = and(_T_74, _T_76) @[ifu_bp_ctl.scala 138:129] + node _T_78 = and(_T_77, io.ifc_fetch_req_f) @[ifu_bp_ctl.scala 139:59] + node _T_79 = eq(leak_one_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 139:82] + node tag_match_way1_p1_f = and(_T_78, _T_79) @[ifu_bp_ctl.scala 139:80] + node _T_80 = bits(btb_bank0_rd_data_way0_f, 3, 3) @[ifu_bp_ctl.scala 142:84] + node _T_81 = bits(btb_bank0_rd_data_way0_f, 4, 4) @[ifu_bp_ctl.scala 142:117] + node _T_82 = xor(_T_80, _T_81) @[ifu_bp_ctl.scala 142:91] + node _T_83 = and(tag_match_way0_f, _T_82) @[ifu_bp_ctl.scala 142:56] + node _T_84 = bits(btb_bank0_rd_data_way0_f, 3, 3) @[ifu_bp_ctl.scala 143:84] + node _T_85 = bits(btb_bank0_rd_data_way0_f, 4, 4) @[ifu_bp_ctl.scala 143:117] + node _T_86 = xor(_T_84, _T_85) @[ifu_bp_ctl.scala 143:91] + node _T_87 = eq(_T_86, UInt<1>("h00")) @[ifu_bp_ctl.scala 143:58] + node _T_88 = and(tag_match_way0_f, _T_87) @[ifu_bp_ctl.scala 143:56] node tag_match_way0_expanded_f = cat(_T_83, _T_88) @[Cat.scala 29:58] - node _T_89 = bits(btb_bank0_rd_data_way1_f, 3, 3) @[ifu_bp_ctl.scala 144:84] - node _T_90 = bits(btb_bank0_rd_data_way1_f, 4, 4) @[ifu_bp_ctl.scala 144:117] - node _T_91 = xor(_T_89, _T_90) @[ifu_bp_ctl.scala 144:91] - node _T_92 = and(tag_match_way1_f, _T_91) @[ifu_bp_ctl.scala 144:56] - node _T_93 = bits(btb_bank0_rd_data_way1_f, 3, 3) @[ifu_bp_ctl.scala 145:84] - node _T_94 = bits(btb_bank0_rd_data_way1_f, 4, 4) @[ifu_bp_ctl.scala 145:117] - node _T_95 = xor(_T_93, _T_94) @[ifu_bp_ctl.scala 145:91] - node _T_96 = eq(_T_95, UInt<1>("h00")) @[ifu_bp_ctl.scala 145:58] - node _T_97 = and(tag_match_way1_f, _T_96) @[ifu_bp_ctl.scala 145:56] + node _T_89 = bits(btb_bank0_rd_data_way1_f, 3, 3) @[ifu_bp_ctl.scala 145:84] + node _T_90 = bits(btb_bank0_rd_data_way1_f, 4, 4) @[ifu_bp_ctl.scala 145:117] + node _T_91 = xor(_T_89, _T_90) @[ifu_bp_ctl.scala 145:91] + node _T_92 = and(tag_match_way1_f, _T_91) @[ifu_bp_ctl.scala 145:56] + node _T_93 = bits(btb_bank0_rd_data_way1_f, 3, 3) @[ifu_bp_ctl.scala 146:84] + node _T_94 = bits(btb_bank0_rd_data_way1_f, 4, 4) @[ifu_bp_ctl.scala 146:117] + node _T_95 = xor(_T_93, _T_94) @[ifu_bp_ctl.scala 146:91] + node _T_96 = eq(_T_95, UInt<1>("h00")) @[ifu_bp_ctl.scala 146:58] + node _T_97 = and(tag_match_way1_f, _T_96) @[ifu_bp_ctl.scala 146:56] node tag_match_way1_expanded_f = cat(_T_92, _T_97) @[Cat.scala 29:58] - node _T_98 = bits(btb_bank0_rd_data_way0_p1_f, 3, 3) @[ifu_bp_ctl.scala 147:93] - node _T_99 = bits(btb_bank0_rd_data_way0_p1_f, 4, 4) @[ifu_bp_ctl.scala 147:129] - node _T_100 = xor(_T_98, _T_99) @[ifu_bp_ctl.scala 147:100] - node _T_101 = and(tag_match_way0_p1_f, _T_100) @[ifu_bp_ctl.scala 147:62] - node _T_102 = bits(btb_bank0_rd_data_way0_p1_f, 3, 3) @[ifu_bp_ctl.scala 148:93] - node _T_103 = bits(btb_bank0_rd_data_way0_p1_f, 4, 4) @[ifu_bp_ctl.scala 148:129] - node _T_104 = xor(_T_102, _T_103) @[ifu_bp_ctl.scala 148:100] - node _T_105 = eq(_T_104, UInt<1>("h00")) @[ifu_bp_ctl.scala 148:64] - node _T_106 = and(tag_match_way0_p1_f, _T_105) @[ifu_bp_ctl.scala 148:62] + node _T_98 = bits(btb_bank0_rd_data_way0_p1_f, 3, 3) @[ifu_bp_ctl.scala 148:93] + node _T_99 = bits(btb_bank0_rd_data_way0_p1_f, 4, 4) @[ifu_bp_ctl.scala 148:129] + node _T_100 = xor(_T_98, _T_99) @[ifu_bp_ctl.scala 148:100] + node _T_101 = and(tag_match_way0_p1_f, _T_100) @[ifu_bp_ctl.scala 148:62] + node _T_102 = bits(btb_bank0_rd_data_way0_p1_f, 3, 3) @[ifu_bp_ctl.scala 149:93] + node _T_103 = bits(btb_bank0_rd_data_way0_p1_f, 4, 4) @[ifu_bp_ctl.scala 149:129] + node _T_104 = xor(_T_102, _T_103) @[ifu_bp_ctl.scala 149:100] + node _T_105 = eq(_T_104, UInt<1>("h00")) @[ifu_bp_ctl.scala 149:64] + node _T_106 = and(tag_match_way0_p1_f, _T_105) @[ifu_bp_ctl.scala 149:62] node tag_match_way0_expanded_p1_f = cat(_T_101, _T_106) @[Cat.scala 29:58] - node _T_107 = bits(btb_bank0_rd_data_way1_p1_f, 3, 3) @[ifu_bp_ctl.scala 150:93] - node _T_108 = bits(btb_bank0_rd_data_way1_p1_f, 4, 4) @[ifu_bp_ctl.scala 150:129] - node _T_109 = xor(_T_107, _T_108) @[ifu_bp_ctl.scala 150:100] - node _T_110 = and(tag_match_way1_p1_f, _T_109) @[ifu_bp_ctl.scala 150:62] - node _T_111 = bits(btb_bank0_rd_data_way1_p1_f, 3, 3) @[ifu_bp_ctl.scala 151:93] - node _T_112 = bits(btb_bank0_rd_data_way1_p1_f, 4, 4) @[ifu_bp_ctl.scala 151:129] - node _T_113 = xor(_T_111, _T_112) @[ifu_bp_ctl.scala 151:100] - node _T_114 = eq(_T_113, UInt<1>("h00")) @[ifu_bp_ctl.scala 151:64] - node _T_115 = and(tag_match_way1_p1_f, _T_114) @[ifu_bp_ctl.scala 151:62] + node _T_107 = bits(btb_bank0_rd_data_way1_p1_f, 3, 3) @[ifu_bp_ctl.scala 151:93] + node _T_108 = bits(btb_bank0_rd_data_way1_p1_f, 4, 4) @[ifu_bp_ctl.scala 151:129] + node _T_109 = xor(_T_107, _T_108) @[ifu_bp_ctl.scala 151:100] + node _T_110 = and(tag_match_way1_p1_f, _T_109) @[ifu_bp_ctl.scala 151:62] + node _T_111 = bits(btb_bank0_rd_data_way1_p1_f, 3, 3) @[ifu_bp_ctl.scala 152:93] + node _T_112 = bits(btb_bank0_rd_data_way1_p1_f, 4, 4) @[ifu_bp_ctl.scala 152:129] + node _T_113 = xor(_T_111, _T_112) @[ifu_bp_ctl.scala 152:100] + node _T_114 = eq(_T_113, UInt<1>("h00")) @[ifu_bp_ctl.scala 152:64] + node _T_115 = and(tag_match_way1_p1_f, _T_114) @[ifu_bp_ctl.scala 152:62] node tag_match_way1_expanded_p1_f = cat(_T_110, _T_115) @[Cat.scala 29:58] - node wayhit_f = or(tag_match_way0_expanded_f, tag_match_way1_expanded_f) @[ifu_bp_ctl.scala 154:44] - node wayhit_p1_f = or(tag_match_way0_expanded_p1_f, tag_match_way1_expanded_p1_f) @[ifu_bp_ctl.scala 156:50] - node _T_116 = bits(tag_match_way0_expanded_f, 0, 0) @[ifu_bp_ctl.scala 160:65] - node _T_117 = bits(_T_116, 0, 0) @[ifu_bp_ctl.scala 160:69] - node _T_118 = bits(tag_match_way1_expanded_f, 0, 0) @[ifu_bp_ctl.scala 161:65] - node _T_119 = bits(_T_118, 0, 0) @[ifu_bp_ctl.scala 161:69] + node wayhit_f = or(tag_match_way0_expanded_f, tag_match_way1_expanded_f) @[ifu_bp_ctl.scala 155:44] + node wayhit_p1_f = or(tag_match_way0_expanded_p1_f, tag_match_way1_expanded_p1_f) @[ifu_bp_ctl.scala 157:50] + node _T_116 = bits(tag_match_way0_expanded_f, 0, 0) @[ifu_bp_ctl.scala 161:65] + node _T_117 = bits(_T_116, 0, 0) @[ifu_bp_ctl.scala 161:69] + node _T_118 = bits(tag_match_way1_expanded_f, 0, 0) @[ifu_bp_ctl.scala 162:65] + node _T_119 = bits(_T_118, 0, 0) @[ifu_bp_ctl.scala 162:69] node _T_120 = mux(_T_117, btb_bank0_rd_data_way0_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_121 = mux(_T_119, btb_bank0_rd_data_way1_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_122 = or(_T_120, _T_121) @[Mux.scala 27:72] wire btb_bank0e_rd_data_f : UInt<22> @[Mux.scala 27:72] btb_bank0e_rd_data_f <= _T_122 @[Mux.scala 27:72] - node _T_123 = bits(tag_match_way0_expanded_f, 1, 1) @[ifu_bp_ctl.scala 163:65] - node _T_124 = bits(_T_123, 0, 0) @[ifu_bp_ctl.scala 163:69] - node _T_125 = bits(tag_match_way1_expanded_f, 1, 1) @[ifu_bp_ctl.scala 164:65] - node _T_126 = bits(_T_125, 0, 0) @[ifu_bp_ctl.scala 164:69] + node _T_123 = bits(tag_match_way0_expanded_f, 1, 1) @[ifu_bp_ctl.scala 164:65] + node _T_124 = bits(_T_123, 0, 0) @[ifu_bp_ctl.scala 164:69] + node _T_125 = bits(tag_match_way1_expanded_f, 1, 1) @[ifu_bp_ctl.scala 165:65] + node _T_126 = bits(_T_125, 0, 0) @[ifu_bp_ctl.scala 165:69] node _T_127 = mux(_T_124, btb_bank0_rd_data_way0_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_128 = mux(_T_126, btb_bank0_rd_data_way1_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_129 = or(_T_127, _T_128) @[Mux.scala 27:72] wire btb_bank0o_rd_data_f : UInt<22> @[Mux.scala 27:72] btb_bank0o_rd_data_f <= _T_129 @[Mux.scala 27:72] - node _T_130 = bits(tag_match_way0_expanded_p1_f, 0, 0) @[ifu_bp_ctl.scala 166:71] - node _T_131 = bits(_T_130, 0, 0) @[ifu_bp_ctl.scala 166:75] - node _T_132 = bits(tag_match_way1_expanded_p1_f, 0, 0) @[ifu_bp_ctl.scala 167:71] - node _T_133 = bits(_T_132, 0, 0) @[ifu_bp_ctl.scala 167:75] + node _T_130 = bits(tag_match_way0_expanded_p1_f, 0, 0) @[ifu_bp_ctl.scala 167:71] + node _T_131 = bits(_T_130, 0, 0) @[ifu_bp_ctl.scala 167:75] + node _T_132 = bits(tag_match_way1_expanded_p1_f, 0, 0) @[ifu_bp_ctl.scala 168:71] + node _T_133 = bits(_T_132, 0, 0) @[ifu_bp_ctl.scala 168:75] node _T_134 = mux(_T_131, btb_bank0_rd_data_way0_p1_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_135 = mux(_T_133, btb_bank0_rd_data_way1_p1_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_136 = or(_T_134, _T_135) @[Mux.scala 27:72] wire btb_bank0e_rd_data_p1_f : UInt<22> @[Mux.scala 27:72] btb_bank0e_rd_data_p1_f <= _T_136 @[Mux.scala 27:72] - node _T_137 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 171:60] - node _T_138 = eq(_T_137, UInt<1>("h00")) @[ifu_bp_ctl.scala 171:40] - node _T_139 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 172:60] + node _T_137 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 172:60] + node _T_138 = eq(_T_137, UInt<1>("h00")) @[ifu_bp_ctl.scala 172:40] + node _T_139 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 173:60] node _T_140 = mux(_T_138, btb_bank0e_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_141 = mux(_T_139, btb_bank0o_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_142 = or(_T_140, _T_141) @[Mux.scala 27:72] wire btb_vbank0_rd_data_f : UInt<22> @[Mux.scala 27:72] btb_vbank0_rd_data_f <= _T_142 @[Mux.scala 27:72] - node _T_143 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 173:60] - node _T_144 = eq(_T_143, UInt<1>("h00")) @[ifu_bp_ctl.scala 173:40] - node _T_145 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 174:60] + node _T_143 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 174:60] + node _T_144 = eq(_T_143, UInt<1>("h00")) @[ifu_bp_ctl.scala 174:40] + node _T_145 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 175:60] node _T_146 = mux(_T_144, btb_bank0o_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_147 = mux(_T_145, btb_bank0e_rd_data_p1_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_148 = or(_T_146, _T_147) @[Mux.scala 27:72] wire btb_vbank1_rd_data_f : UInt<22> @[Mux.scala 27:72] btb_vbank1_rd_data_f <= _T_148 @[Mux.scala 27:72] - node mp_wrindex_dec = dshl(UInt<1>("h01"), io.exu_bp.exu_mp_index) @[ifu_bp_ctl.scala 190:28] - node fetch_wrindex_dec = dshl(UInt<1>("h01"), btb_rd_addr_f) @[ifu_bp_ctl.scala 193:31] - node fetch_wrindex_p1_dec = dshl(UInt<1>("h01"), btb_rd_addr_p1_f) @[ifu_bp_ctl.scala 196:34] + node mp_wrindex_dec = dshl(UInt<1>("h01"), io.exu_bp.exu_mp_index) @[ifu_bp_ctl.scala 191:28] + node fetch_wrindex_dec = dshl(UInt<1>("h01"), btb_rd_addr_f) @[ifu_bp_ctl.scala 194:31] + node fetch_wrindex_p1_dec = dshl(UInt<1>("h01"), btb_rd_addr_p1_f) @[ifu_bp_ctl.scala 197:34] node _T_149 = bits(exu_mp_valid, 0, 0) @[Bitwise.scala 72:15] node _T_150 = mux(_T_149, UInt<256>("h0ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff"), UInt<256>("h00")) @[Bitwise.scala 72:12] - node mp_wrlru_b0 = and(mp_wrindex_dec, _T_150) @[ifu_bp_ctl.scala 199:36] - node _T_151 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 201:49] - node _T_152 = bits(_T_151, 0, 0) @[ifu_bp_ctl.scala 201:53] - node _T_153 = eq(_T_152, UInt<1>("h00")) @[ifu_bp_ctl.scala 201:29] - node _T_154 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 202:24] - node _T_155 = bits(_T_154, 0, 0) @[ifu_bp_ctl.scala 202:28] - node _T_156 = bits(wayhit_p1_f, 0, 0) @[ifu_bp_ctl.scala 202:51] - node _T_157 = bits(wayhit_f, 1, 1) @[ifu_bp_ctl.scala 202:64] + node mp_wrlru_b0 = and(mp_wrindex_dec, _T_150) @[ifu_bp_ctl.scala 200:36] + node _T_151 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 202:49] + node _T_152 = bits(_T_151, 0, 0) @[ifu_bp_ctl.scala 202:53] + node _T_153 = eq(_T_152, UInt<1>("h00")) @[ifu_bp_ctl.scala 202:29] + node _T_154 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 203:24] + node _T_155 = bits(_T_154, 0, 0) @[ifu_bp_ctl.scala 203:28] + node _T_156 = bits(wayhit_p1_f, 0, 0) @[ifu_bp_ctl.scala 203:51] + node _T_157 = bits(wayhit_f, 1, 1) @[ifu_bp_ctl.scala 203:64] node _T_158 = cat(_T_156, _T_157) @[Cat.scala 29:58] node _T_159 = mux(_T_153, wayhit_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_160 = mux(_T_155, _T_158, UInt<1>("h00")) @[Mux.scala 27:72] @@ -29351,26 +29351,26 @@ circuit quasar_wrapper : wire _T_162 : UInt<2> @[Mux.scala 27:72] _T_162 <= _T_161 @[Mux.scala 27:72] node _T_163 = cat(eoc_mask, UInt<1>("h01")) @[Cat.scala 29:58] - node bht_valid_f = and(_T_162, _T_163) @[ifu_bp_ctl.scala 202:71] - node _T_164 = bits(bht_valid_f, 0, 0) @[ifu_bp_ctl.scala 205:38] - node _T_165 = bits(bht_valid_f, 1, 1) @[ifu_bp_ctl.scala 205:53] - node _T_166 = or(_T_164, _T_165) @[ifu_bp_ctl.scala 205:42] - node _T_167 = and(_T_166, io.ifc_fetch_req_f) @[ifu_bp_ctl.scala 205:58] - node _T_168 = eq(leak_one_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 205:81] - node lru_update_valid_f = and(_T_167, _T_168) @[ifu_bp_ctl.scala 205:79] + node bht_valid_f = and(_T_162, _T_163) @[ifu_bp_ctl.scala 203:71] + node _T_164 = bits(bht_valid_f, 0, 0) @[ifu_bp_ctl.scala 206:38] + node _T_165 = bits(bht_valid_f, 1, 1) @[ifu_bp_ctl.scala 206:53] + node _T_166 = or(_T_164, _T_165) @[ifu_bp_ctl.scala 206:42] + node _T_167 = and(_T_166, io.ifc_fetch_req_f) @[ifu_bp_ctl.scala 206:58] + node _T_168 = eq(leak_one_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 206:81] + node lru_update_valid_f = and(_T_167, _T_168) @[ifu_bp_ctl.scala 206:79] node _T_169 = bits(lru_update_valid_f, 0, 0) @[Bitwise.scala 72:15] node _T_170 = mux(_T_169, UInt<256>("h0ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff"), UInt<256>("h00")) @[Bitwise.scala 72:12] - node fetch_wrlru_b0 = and(fetch_wrindex_dec, _T_170) @[ifu_bp_ctl.scala 207:42] + node fetch_wrlru_b0 = and(fetch_wrindex_dec, _T_170) @[ifu_bp_ctl.scala 208:42] node _T_171 = bits(lru_update_valid_f, 0, 0) @[Bitwise.scala 72:15] node _T_172 = mux(_T_171, UInt<256>("h0ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff"), UInt<256>("h00")) @[Bitwise.scala 72:12] - node fetch_wrlru_p1_b0 = and(fetch_wrindex_p1_dec, _T_172) @[ifu_bp_ctl.scala 208:48] - node _T_173 = not(mp_wrlru_b0) @[ifu_bp_ctl.scala 210:25] - node _T_174 = not(fetch_wrlru_b0) @[ifu_bp_ctl.scala 210:40] - node btb_lru_b0_hold = and(_T_173, _T_174) @[ifu_bp_ctl.scala 210:38] - node _T_175 = bits(io.exu_bp.exu_mp_pkt.bits.way, 0, 0) @[ifu_bp_ctl.scala 217:52] - node _T_176 = eq(_T_175, UInt<1>("h00")) @[ifu_bp_ctl.scala 217:40] - node _T_177 = bits(tag_match_way0_f, 0, 0) @[ifu_bp_ctl.scala 218:51] - node _T_178 = bits(tag_match_way0_p1_f, 0, 0) @[ifu_bp_ctl.scala 219:54] + node fetch_wrlru_p1_b0 = and(fetch_wrindex_p1_dec, _T_172) @[ifu_bp_ctl.scala 209:48] + node _T_173 = not(mp_wrlru_b0) @[ifu_bp_ctl.scala 211:25] + node _T_174 = not(fetch_wrlru_b0) @[ifu_bp_ctl.scala 211:40] + node btb_lru_b0_hold = and(_T_173, _T_174) @[ifu_bp_ctl.scala 211:38] + node _T_175 = bits(io.exu_bp.exu_mp_pkt.bits.way, 0, 0) @[ifu_bp_ctl.scala 218:52] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[ifu_bp_ctl.scala 218:40] + node _T_177 = bits(tag_match_way0_f, 0, 0) @[ifu_bp_ctl.scala 219:51] + node _T_178 = bits(tag_match_way0_p1_f, 0, 0) @[ifu_bp_ctl.scala 220:54] node _T_179 = mux(_T_176, mp_wrlru_b0, UInt<1>("h00")) @[Mux.scala 27:72] node _T_180 = mux(_T_177, fetch_wrlru_b0, UInt<1>("h00")) @[Mux.scala 27:72] node _T_181 = mux(_T_178, fetch_wrlru_p1_b0, UInt<1>("h00")) @[Mux.scala 27:72] @@ -29378,46 +29378,46 @@ circuit quasar_wrapper : node _T_183 = or(_T_182, _T_181) @[Mux.scala 27:72] wire _T_184 : UInt<256> @[Mux.scala 27:72] _T_184 <= _T_183 @[Mux.scala 27:72] - node _T_185 = and(btb_lru_b0_hold, btb_lru_b0_f) @[ifu_bp_ctl.scala 219:102] - node btb_lru_b0_ns = or(_T_184, _T_185) @[ifu_bp_ctl.scala 219:84] - node _T_186 = bits(fetch_mp_collision_f, 0, 0) @[ifu_bp_ctl.scala 222:37] - node _T_187 = and(fetch_wrindex_dec, btb_lru_b0_f) @[ifu_bp_ctl.scala 222:78] - node _T_188 = orr(_T_187) @[ifu_bp_ctl.scala 222:94] - node btb_lru_rd_f = mux(_T_186, exu_mp_way_f, _T_188) @[ifu_bp_ctl.scala 222:25] - node _T_189 = bits(fetch_mp_collision_p1_f, 0, 0) @[ifu_bp_ctl.scala 224:43] - node _T_190 = and(fetch_wrindex_p1_dec, btb_lru_b0_f) @[ifu_bp_ctl.scala 224:87] - node _T_191 = orr(_T_190) @[ifu_bp_ctl.scala 224:103] - node btb_lru_rd_p1_f = mux(_T_189, exu_mp_way_f, _T_191) @[ifu_bp_ctl.scala 224:28] - node _T_192 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 227:53] - node _T_193 = eq(_T_192, UInt<1>("h00")) @[ifu_bp_ctl.scala 227:33] + node _T_185 = and(btb_lru_b0_hold, btb_lru_b0_f) @[ifu_bp_ctl.scala 220:102] + node btb_lru_b0_ns = or(_T_184, _T_185) @[ifu_bp_ctl.scala 220:84] + node _T_186 = bits(fetch_mp_collision_f, 0, 0) @[ifu_bp_ctl.scala 223:37] + node _T_187 = and(fetch_wrindex_dec, btb_lru_b0_f) @[ifu_bp_ctl.scala 223:78] + node _T_188 = orr(_T_187) @[ifu_bp_ctl.scala 223:94] + node btb_lru_rd_f = mux(_T_186, exu_mp_way_f, _T_188) @[ifu_bp_ctl.scala 223:25] + node _T_189 = bits(fetch_mp_collision_p1_f, 0, 0) @[ifu_bp_ctl.scala 225:43] + node _T_190 = and(fetch_wrindex_p1_dec, btb_lru_b0_f) @[ifu_bp_ctl.scala 225:87] + node _T_191 = orr(_T_190) @[ifu_bp_ctl.scala 225:103] + node btb_lru_rd_p1_f = mux(_T_189, exu_mp_way_f, _T_191) @[ifu_bp_ctl.scala 225:28] + node _T_192 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 228:53] + node _T_193 = eq(_T_192, UInt<1>("h00")) @[ifu_bp_ctl.scala 228:33] node _T_194 = cat(btb_lru_rd_f, btb_lru_rd_f) @[Cat.scala 29:58] - node _T_195 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 228:53] - node _T_196 = bits(_T_195, 0, 0) @[ifu_bp_ctl.scala 228:57] + node _T_195 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 229:53] + node _T_196 = bits(_T_195, 0, 0) @[ifu_bp_ctl.scala 229:57] node _T_197 = cat(btb_lru_rd_p1_f, btb_lru_rd_f) @[Cat.scala 29:58] node _T_198 = mux(_T_193, _T_194, UInt<1>("h00")) @[Mux.scala 27:72] node _T_199 = mux(_T_196, _T_197, UInt<1>("h00")) @[Mux.scala 27:72] node _T_200 = or(_T_198, _T_199) @[Mux.scala 27:72] wire btb_vlru_rd_f : UInt @[Mux.scala 27:72] btb_vlru_rd_f <= _T_200 @[Mux.scala 27:72] - node _T_201 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 231:66] - node _T_202 = bits(_T_201, 0, 0) @[ifu_bp_ctl.scala 231:70] - node _T_203 = eq(_T_202, UInt<1>("h00")) @[ifu_bp_ctl.scala 231:46] - node _T_204 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 232:42] - node _T_205 = bits(_T_204, 0, 0) @[ifu_bp_ctl.scala 232:46] - node _T_206 = bits(tag_match_way1_expanded_p1_f, 0, 0) @[ifu_bp_ctl.scala 232:86] - node _T_207 = bits(tag_match_way1_expanded_f, 1, 1) @[ifu_bp_ctl.scala 232:115] + node _T_201 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 232:66] + node _T_202 = bits(_T_201, 0, 0) @[ifu_bp_ctl.scala 232:70] + node _T_203 = eq(_T_202, UInt<1>("h00")) @[ifu_bp_ctl.scala 232:46] + node _T_204 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 233:42] + node _T_205 = bits(_T_204, 0, 0) @[ifu_bp_ctl.scala 233:46] + node _T_206 = bits(tag_match_way1_expanded_p1_f, 0, 0) @[ifu_bp_ctl.scala 233:86] + node _T_207 = bits(tag_match_way1_expanded_f, 1, 1) @[ifu_bp_ctl.scala 233:115] node _T_208 = cat(_T_206, _T_207) @[Cat.scala 29:58] node _T_209 = mux(_T_203, tag_match_way1_expanded_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_210 = mux(_T_205, _T_208, UInt<1>("h00")) @[Mux.scala 27:72] node _T_211 = or(_T_209, _T_210) @[Mux.scala 27:72] wire tag_match_vway1_expanded_f : UInt<2> @[Mux.scala 27:72] tag_match_vway1_expanded_f <= _T_211 @[Mux.scala 27:72] - node _T_212 = not(bht_valid_f) @[ifu_bp_ctl.scala 234:52] - node _T_213 = and(_T_212, btb_vlru_rd_f) @[ifu_bp_ctl.scala 234:63] - node _T_214 = or(tag_match_vway1_expanded_f, _T_213) @[ifu_bp_ctl.scala 234:49] - io.ifu_bp_way_f <= _T_214 @[ifu_bp_ctl.scala 234:19] - node _T_215 = or(io.ifc_fetch_req_f, exu_mp_valid) @[ifu_bp_ctl.scala 237:60] - node _T_216 = bits(_T_215, 0, 0) @[ifu_bp_ctl.scala 237:75] + node _T_212 = not(bht_valid_f) @[ifu_bp_ctl.scala 235:52] + node _T_213 = and(_T_212, btb_vlru_rd_f) @[ifu_bp_ctl.scala 235:63] + node _T_214 = or(tag_match_vway1_expanded_f, _T_213) @[ifu_bp_ctl.scala 235:49] + io.ifu_bp_way_f <= _T_214 @[ifu_bp_ctl.scala 235:19] + node _T_215 = or(io.ifc_fetch_req_f, exu_mp_valid) @[ifu_bp_ctl.scala 238:60] + node _T_216 = bits(_T_215, 0, 0) @[ifu_bp_ctl.scala 238:75] inst rvclkhdr of rvclkhdr_94 @[lib.scala 352:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -29426,49 +29426,49 @@ circuit quasar_wrapper : rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_217 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_217 <= btb_lru_b0_ns @[lib.scala 358:16] - btb_lru_b0_f <= _T_217 @[ifu_bp_ctl.scala 237:16] - node _T_218 = bits(io.ifc_fetch_addr_f, 4, 2) @[ifu_bp_ctl.scala 240:37] - node eoc_near = andr(_T_218) @[ifu_bp_ctl.scala 240:64] - node _T_219 = eq(eoc_near, UInt<1>("h00")) @[ifu_bp_ctl.scala 243:15] - node _T_220 = bits(io.ifc_fetch_addr_f, 1, 0) @[ifu_bp_ctl.scala 243:48] - node _T_221 = not(_T_220) @[ifu_bp_ctl.scala 243:28] - node _T_222 = orr(_T_221) @[ifu_bp_ctl.scala 243:58] - node _T_223 = or(_T_219, _T_222) @[ifu_bp_ctl.scala 243:25] - eoc_mask <= _T_223 @[ifu_bp_ctl.scala 243:12] + btb_lru_b0_f <= _T_217 @[ifu_bp_ctl.scala 238:16] + node _T_218 = bits(io.ifc_fetch_addr_f, 4, 2) @[ifu_bp_ctl.scala 241:37] + node eoc_near = andr(_T_218) @[ifu_bp_ctl.scala 241:64] + node _T_219 = eq(eoc_near, UInt<1>("h00")) @[ifu_bp_ctl.scala 244:15] + node _T_220 = bits(io.ifc_fetch_addr_f, 1, 0) @[ifu_bp_ctl.scala 244:48] + node _T_221 = not(_T_220) @[ifu_bp_ctl.scala 244:28] + node _T_222 = orr(_T_221) @[ifu_bp_ctl.scala 244:58] + node _T_223 = or(_T_219, _T_222) @[ifu_bp_ctl.scala 244:25] + eoc_mask <= _T_223 @[ifu_bp_ctl.scala 244:12] wire btb_sel_data_f : UInt<16> btb_sel_data_f <= UInt<1>("h00") wire hist1_raw : UInt<2> hist1_raw <= UInt<1>("h00") - node btb_rd_tgt_f = bits(btb_sel_data_f, 15, 4) @[ifu_bp_ctl.scala 250:36] - node btb_rd_pc4_f = bits(btb_sel_data_f, 3, 3) @[ifu_bp_ctl.scala 251:36] - node btb_rd_call_f = bits(btb_sel_data_f, 1, 1) @[ifu_bp_ctl.scala 252:37] - node btb_rd_ret_f = bits(btb_sel_data_f, 0, 0) @[ifu_bp_ctl.scala 253:36] - node _T_224 = bits(btb_sel_f, 1, 1) @[ifu_bp_ctl.scala 256:40] - node _T_225 = bits(_T_224, 0, 0) @[ifu_bp_ctl.scala 256:44] - node _T_226 = bits(btb_vbank1_rd_data_f, 16, 1) @[ifu_bp_ctl.scala 256:73] - node _T_227 = bits(btb_sel_f, 0, 0) @[ifu_bp_ctl.scala 257:40] - node _T_228 = bits(_T_227, 0, 0) @[ifu_bp_ctl.scala 257:44] - node _T_229 = bits(btb_vbank0_rd_data_f, 16, 1) @[ifu_bp_ctl.scala 257:73] + node btb_rd_tgt_f = bits(btb_sel_data_f, 15, 4) @[ifu_bp_ctl.scala 251:36] + node btb_rd_pc4_f = bits(btb_sel_data_f, 3, 3) @[ifu_bp_ctl.scala 252:36] + node btb_rd_call_f = bits(btb_sel_data_f, 1, 1) @[ifu_bp_ctl.scala 253:37] + node btb_rd_ret_f = bits(btb_sel_data_f, 0, 0) @[ifu_bp_ctl.scala 254:36] + node _T_224 = bits(btb_sel_f, 1, 1) @[ifu_bp_ctl.scala 257:40] + node _T_225 = bits(_T_224, 0, 0) @[ifu_bp_ctl.scala 257:44] + node _T_226 = bits(btb_vbank1_rd_data_f, 16, 1) @[ifu_bp_ctl.scala 257:73] + node _T_227 = bits(btb_sel_f, 0, 0) @[ifu_bp_ctl.scala 258:40] + node _T_228 = bits(_T_227, 0, 0) @[ifu_bp_ctl.scala 258:44] + node _T_229 = bits(btb_vbank0_rd_data_f, 16, 1) @[ifu_bp_ctl.scala 258:73] node _T_230 = mux(_T_225, _T_226, UInt<1>("h00")) @[Mux.scala 27:72] node _T_231 = mux(_T_228, _T_229, UInt<1>("h00")) @[Mux.scala 27:72] node _T_232 = or(_T_230, _T_231) @[Mux.scala 27:72] wire _T_233 : UInt<16> @[Mux.scala 27:72] _T_233 <= _T_232 @[Mux.scala 27:72] - btb_sel_data_f <= _T_233 @[ifu_bp_ctl.scala 256:18] - node _T_234 = and(bht_valid_f, hist1_raw) @[ifu_bp_ctl.scala 260:39] - node _T_235 = orr(_T_234) @[ifu_bp_ctl.scala 260:52] - node _T_236 = and(_T_235, io.ifc_fetch_req_f) @[ifu_bp_ctl.scala 260:56] - node _T_237 = eq(leak_one_f_d1, UInt<1>("h00")) @[ifu_bp_ctl.scala 260:79] - node _T_238 = and(_T_236, _T_237) @[ifu_bp_ctl.scala 260:77] - node _T_239 = eq(io.dec_bp.dec_tlu_bpred_disable, UInt<1>("h00")) @[ifu_bp_ctl.scala 260:96] - node _T_240 = and(_T_238, _T_239) @[ifu_bp_ctl.scala 260:94] - io.ifu_bp_hit_taken_f <= _T_240 @[ifu_bp_ctl.scala 260:25] - node _T_241 = bits(btb_vbank1_rd_data_f, 2, 2) @[ifu_bp_ctl.scala 263:52] - node _T_242 = bits(btb_vbank1_rd_data_f, 1, 1) @[ifu_bp_ctl.scala 263:81] - node _T_243 = or(_T_241, _T_242) @[ifu_bp_ctl.scala 263:59] - node _T_244 = bits(btb_vbank0_rd_data_f, 2, 2) @[ifu_bp_ctl.scala 264:52] - node _T_245 = bits(btb_vbank0_rd_data_f, 1, 1) @[ifu_bp_ctl.scala 264:81] - node _T_246 = or(_T_244, _T_245) @[ifu_bp_ctl.scala 264:59] + btb_sel_data_f <= _T_233 @[ifu_bp_ctl.scala 257:18] + node _T_234 = and(bht_valid_f, hist1_raw) @[ifu_bp_ctl.scala 261:39] + node _T_235 = orr(_T_234) @[ifu_bp_ctl.scala 261:52] + node _T_236 = and(_T_235, io.ifc_fetch_req_f) @[ifu_bp_ctl.scala 261:56] + node _T_237 = eq(leak_one_f_d1, UInt<1>("h00")) @[ifu_bp_ctl.scala 261:79] + node _T_238 = and(_T_236, _T_237) @[ifu_bp_ctl.scala 261:77] + node _T_239 = eq(io.dec_bp.dec_tlu_bpred_disable, UInt<1>("h00")) @[ifu_bp_ctl.scala 261:96] + node _T_240 = and(_T_238, _T_239) @[ifu_bp_ctl.scala 261:94] + io.ifu_bp_hit_taken_f <= _T_240 @[ifu_bp_ctl.scala 261:25] + node _T_241 = bits(btb_vbank1_rd_data_f, 2, 2) @[ifu_bp_ctl.scala 264:52] + node _T_242 = bits(btb_vbank1_rd_data_f, 1, 1) @[ifu_bp_ctl.scala 264:81] + node _T_243 = or(_T_241, _T_242) @[ifu_bp_ctl.scala 264:59] + node _T_244 = bits(btb_vbank0_rd_data_f, 2, 2) @[ifu_bp_ctl.scala 265:52] + node _T_245 = bits(btb_vbank0_rd_data_f, 1, 1) @[ifu_bp_ctl.scala 265:81] + node _T_246 = or(_T_244, _T_245) @[ifu_bp_ctl.scala 265:59] node bht_force_taken_f = cat(_T_243, _T_246) @[Cat.scala 29:58] wire bht_bank1_rd_data_f : UInt<2> bht_bank1_rd_data_f <= UInt<1>("h00") @@ -29476,90 +29476,90 @@ circuit quasar_wrapper : bht_bank0_rd_data_f <= UInt<1>("h00") wire bht_bank0_rd_data_p1_f : UInt<2> bht_bank0_rd_data_p1_f <= UInt<1>("h00") - node _T_247 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 273:60] - node _T_248 = bits(_T_247, 0, 0) @[ifu_bp_ctl.scala 273:64] - node _T_249 = eq(_T_248, UInt<1>("h00")) @[ifu_bp_ctl.scala 273:40] - node _T_250 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 274:60] - node _T_251 = bits(_T_250, 0, 0) @[ifu_bp_ctl.scala 274:64] + node _T_247 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 274:60] + node _T_248 = bits(_T_247, 0, 0) @[ifu_bp_ctl.scala 274:64] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[ifu_bp_ctl.scala 274:40] + node _T_250 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 275:60] + node _T_251 = bits(_T_250, 0, 0) @[ifu_bp_ctl.scala 275:64] node _T_252 = mux(_T_249, bht_bank0_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_253 = mux(_T_251, bht_bank1_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_254 = or(_T_252, _T_253) @[Mux.scala 27:72] wire bht_vbank0_rd_data_f : UInt<2> @[Mux.scala 27:72] bht_vbank0_rd_data_f <= _T_254 @[Mux.scala 27:72] - node _T_255 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 276:60] - node _T_256 = bits(_T_255, 0, 0) @[ifu_bp_ctl.scala 276:64] - node _T_257 = eq(_T_256, UInt<1>("h00")) @[ifu_bp_ctl.scala 276:40] - node _T_258 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 277:60] - node _T_259 = bits(_T_258, 0, 0) @[ifu_bp_ctl.scala 277:64] + node _T_255 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 277:60] + node _T_256 = bits(_T_255, 0, 0) @[ifu_bp_ctl.scala 277:64] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[ifu_bp_ctl.scala 277:40] + node _T_258 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 278:60] + node _T_259 = bits(_T_258, 0, 0) @[ifu_bp_ctl.scala 278:64] node _T_260 = mux(_T_257, bht_bank1_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_261 = mux(_T_259, bht_bank0_rd_data_p1_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_262 = or(_T_260, _T_261) @[Mux.scala 27:72] wire bht_vbank1_rd_data_f : UInt<2> @[Mux.scala 27:72] bht_vbank1_rd_data_f <= _T_262 @[Mux.scala 27:72] - node _T_263 = bits(bht_force_taken_f, 1, 1) @[ifu_bp_ctl.scala 280:38] - node _T_264 = bits(bht_vbank1_rd_data_f, 1, 1) @[ifu_bp_ctl.scala 280:64] - node _T_265 = or(_T_263, _T_264) @[ifu_bp_ctl.scala 280:42] - node _T_266 = bits(bht_valid_f, 1, 1) @[ifu_bp_ctl.scala 280:82] - node _T_267 = and(_T_265, _T_266) @[ifu_bp_ctl.scala 280:69] - node _T_268 = bits(bht_force_taken_f, 0, 0) @[ifu_bp_ctl.scala 281:41] - node _T_269 = bits(bht_vbank0_rd_data_f, 1, 1) @[ifu_bp_ctl.scala 281:67] - node _T_270 = or(_T_268, _T_269) @[ifu_bp_ctl.scala 281:45] - node _T_271 = bits(bht_valid_f, 0, 0) @[ifu_bp_ctl.scala 281:85] - node _T_272 = and(_T_270, _T_271) @[ifu_bp_ctl.scala 281:72] + node _T_263 = bits(bht_force_taken_f, 1, 1) @[ifu_bp_ctl.scala 281:38] + node _T_264 = bits(bht_vbank1_rd_data_f, 1, 1) @[ifu_bp_ctl.scala 281:64] + node _T_265 = or(_T_263, _T_264) @[ifu_bp_ctl.scala 281:42] + node _T_266 = bits(bht_valid_f, 1, 1) @[ifu_bp_ctl.scala 281:82] + node _T_267 = and(_T_265, _T_266) @[ifu_bp_ctl.scala 281:69] + node _T_268 = bits(bht_force_taken_f, 0, 0) @[ifu_bp_ctl.scala 282:41] + node _T_269 = bits(bht_vbank0_rd_data_f, 1, 1) @[ifu_bp_ctl.scala 282:67] + node _T_270 = or(_T_268, _T_269) @[ifu_bp_ctl.scala 282:45] + node _T_271 = bits(bht_valid_f, 0, 0) @[ifu_bp_ctl.scala 282:85] + node _T_272 = and(_T_270, _T_271) @[ifu_bp_ctl.scala 282:72] node _T_273 = cat(_T_267, _T_272) @[Cat.scala 29:58] - bht_dir_f <= _T_273 @[ifu_bp_ctl.scala 280:13] - node _T_274 = bits(btb_sel_f, 1, 1) @[ifu_bp_ctl.scala 284:62] - node _T_275 = and(io.ifu_bp_hit_taken_f, _T_274) @[ifu_bp_ctl.scala 284:51] - node _T_276 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 284:69] - node _T_277 = or(_T_275, _T_276) @[ifu_bp_ctl.scala 284:67] - io.ifu_bp_inst_mask_f <= _T_277 @[ifu_bp_ctl.scala 284:25] - node _T_278 = bits(bht_vbank1_rd_data_f, 1, 1) @[ifu_bp_ctl.scala 287:60] - node _T_279 = bits(bht_vbank0_rd_data_f, 1, 1) @[ifu_bp_ctl.scala 287:85] + bht_dir_f <= _T_273 @[ifu_bp_ctl.scala 281:13] + node _T_274 = bits(btb_sel_f, 1, 1) @[ifu_bp_ctl.scala 285:62] + node _T_275 = and(io.ifu_bp_hit_taken_f, _T_274) @[ifu_bp_ctl.scala 285:51] + node _T_276 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 285:69] + node _T_277 = or(_T_275, _T_276) @[ifu_bp_ctl.scala 285:67] + io.ifu_bp_inst_mask_f <= _T_277 @[ifu_bp_ctl.scala 285:25] + node _T_278 = bits(bht_vbank1_rd_data_f, 1, 1) @[ifu_bp_ctl.scala 288:60] + node _T_279 = bits(bht_vbank0_rd_data_f, 1, 1) @[ifu_bp_ctl.scala 288:85] node _T_280 = cat(_T_278, _T_279) @[Cat.scala 29:58] - node _T_281 = or(bht_force_taken_f, _T_280) @[ifu_bp_ctl.scala 287:34] - hist1_raw <= _T_281 @[ifu_bp_ctl.scala 287:13] - node _T_282 = bits(bht_vbank1_rd_data_f, 0, 0) @[ifu_bp_ctl.scala 290:43] - node _T_283 = bits(bht_vbank0_rd_data_f, 0, 0) @[ifu_bp_ctl.scala 290:68] + node _T_281 = or(bht_force_taken_f, _T_280) @[ifu_bp_ctl.scala 288:34] + hist1_raw <= _T_281 @[ifu_bp_ctl.scala 288:13] + node _T_282 = bits(bht_vbank1_rd_data_f, 0, 0) @[ifu_bp_ctl.scala 291:43] + node _T_283 = bits(bht_vbank0_rd_data_f, 0, 0) @[ifu_bp_ctl.scala 291:68] node hist0_raw = cat(_T_282, _T_283) @[Cat.scala 29:58] - node _T_284 = bits(bht_valid_f, 1, 1) @[ifu_bp_ctl.scala 293:30] - node _T_285 = bits(btb_vbank1_rd_data_f, 4, 4) @[ifu_bp_ctl.scala 293:56] - node _T_286 = and(_T_284, _T_285) @[ifu_bp_ctl.scala 293:34] - node _T_287 = bits(bht_valid_f, 0, 0) @[ifu_bp_ctl.scala 294:30] - node _T_288 = bits(btb_vbank0_rd_data_f, 4, 4) @[ifu_bp_ctl.scala 294:56] - node _T_289 = and(_T_287, _T_288) @[ifu_bp_ctl.scala 294:34] + node _T_284 = bits(bht_valid_f, 1, 1) @[ifu_bp_ctl.scala 294:30] + node _T_285 = bits(btb_vbank1_rd_data_f, 4, 4) @[ifu_bp_ctl.scala 294:56] + node _T_286 = and(_T_284, _T_285) @[ifu_bp_ctl.scala 294:34] + node _T_287 = bits(bht_valid_f, 0, 0) @[ifu_bp_ctl.scala 295:30] + node _T_288 = bits(btb_vbank0_rd_data_f, 4, 4) @[ifu_bp_ctl.scala 295:56] + node _T_289 = and(_T_287, _T_288) @[ifu_bp_ctl.scala 295:34] node pc4_raw = cat(_T_286, _T_289) @[Cat.scala 29:58] - node _T_290 = bits(bht_valid_f, 1, 1) @[ifu_bp_ctl.scala 297:31] - node _T_291 = bits(btb_vbank1_rd_data_f, 2, 2) @[ifu_bp_ctl.scala 297:58] - node _T_292 = eq(_T_291, UInt<1>("h00")) @[ifu_bp_ctl.scala 297:37] - node _T_293 = and(_T_290, _T_292) @[ifu_bp_ctl.scala 297:35] - node _T_294 = bits(btb_vbank1_rd_data_f, 1, 1) @[ifu_bp_ctl.scala 297:87] - node _T_295 = and(_T_293, _T_294) @[ifu_bp_ctl.scala 297:65] - node _T_296 = bits(bht_valid_f, 0, 0) @[ifu_bp_ctl.scala 298:31] - node _T_297 = bits(btb_vbank0_rd_data_f, 2, 2) @[ifu_bp_ctl.scala 298:58] - node _T_298 = eq(_T_297, UInt<1>("h00")) @[ifu_bp_ctl.scala 298:37] - node _T_299 = and(_T_296, _T_298) @[ifu_bp_ctl.scala 298:35] - node _T_300 = bits(btb_vbank0_rd_data_f, 1, 1) @[ifu_bp_ctl.scala 298:87] - node _T_301 = and(_T_299, _T_300) @[ifu_bp_ctl.scala 298:65] + node _T_290 = bits(bht_valid_f, 1, 1) @[ifu_bp_ctl.scala 298:31] + node _T_291 = bits(btb_vbank1_rd_data_f, 2, 2) @[ifu_bp_ctl.scala 298:58] + node _T_292 = eq(_T_291, UInt<1>("h00")) @[ifu_bp_ctl.scala 298:37] + node _T_293 = and(_T_290, _T_292) @[ifu_bp_ctl.scala 298:35] + node _T_294 = bits(btb_vbank1_rd_data_f, 1, 1) @[ifu_bp_ctl.scala 298:87] + node _T_295 = and(_T_293, _T_294) @[ifu_bp_ctl.scala 298:65] + node _T_296 = bits(bht_valid_f, 0, 0) @[ifu_bp_ctl.scala 299:31] + node _T_297 = bits(btb_vbank0_rd_data_f, 2, 2) @[ifu_bp_ctl.scala 299:58] + node _T_298 = eq(_T_297, UInt<1>("h00")) @[ifu_bp_ctl.scala 299:37] + node _T_299 = and(_T_296, _T_298) @[ifu_bp_ctl.scala 299:35] + node _T_300 = bits(btb_vbank0_rd_data_f, 1, 1) @[ifu_bp_ctl.scala 299:87] + node _T_301 = and(_T_299, _T_300) @[ifu_bp_ctl.scala 299:65] node pret_raw = cat(_T_295, _T_301) @[Cat.scala 29:58] - node _T_302 = bits(bht_valid_f, 1, 1) @[ifu_bp_ctl.scala 301:31] - node _T_303 = bits(bht_valid_f, 0, 0) @[ifu_bp_ctl.scala 301:49] - node num_valids = add(_T_302, _T_303) @[ifu_bp_ctl.scala 301:35] - node _T_304 = and(btb_sel_f, bht_dir_f) @[ifu_bp_ctl.scala 304:28] - node final_h = orr(_T_304) @[ifu_bp_ctl.scala 304:41] + node _T_302 = bits(bht_valid_f, 1, 1) @[ifu_bp_ctl.scala 302:31] + node _T_303 = bits(bht_valid_f, 0, 0) @[ifu_bp_ctl.scala 302:49] + node num_valids = add(_T_302, _T_303) @[ifu_bp_ctl.scala 302:35] + node _T_304 = and(btb_sel_f, bht_dir_f) @[ifu_bp_ctl.scala 305:28] + node final_h = orr(_T_304) @[ifu_bp_ctl.scala 305:41] wire fghr : UInt<8> fghr <= UInt<1>("h00") - node _T_305 = eq(num_valids, UInt<2>("h02")) @[ifu_bp_ctl.scala 308:41] - node _T_306 = bits(_T_305, 0, 0) @[ifu_bp_ctl.scala 308:49] - node _T_307 = bits(fghr, 5, 0) @[ifu_bp_ctl.scala 308:65] + node _T_305 = eq(num_valids, UInt<2>("h02")) @[ifu_bp_ctl.scala 309:41] + node _T_306 = bits(_T_305, 0, 0) @[ifu_bp_ctl.scala 309:49] + node _T_307 = bits(fghr, 5, 0) @[ifu_bp_ctl.scala 309:65] node _T_308 = cat(_T_307, UInt<1>("h00")) @[Cat.scala 29:58] node _T_309 = cat(_T_308, final_h) @[Cat.scala 29:58] - node _T_310 = eq(num_valids, UInt<1>("h01")) @[ifu_bp_ctl.scala 309:41] - node _T_311 = bits(_T_310, 0, 0) @[ifu_bp_ctl.scala 309:49] - node _T_312 = bits(fghr, 6, 0) @[ifu_bp_ctl.scala 309:65] + node _T_310 = eq(num_valids, UInt<1>("h01")) @[ifu_bp_ctl.scala 310:41] + node _T_311 = bits(_T_310, 0, 0) @[ifu_bp_ctl.scala 310:49] + node _T_312 = bits(fghr, 6, 0) @[ifu_bp_ctl.scala 310:65] node _T_313 = cat(_T_312, final_h) @[Cat.scala 29:58] - node _T_314 = eq(num_valids, UInt<1>("h00")) @[ifu_bp_ctl.scala 310:41] - node _T_315 = bits(_T_314, 0, 0) @[ifu_bp_ctl.scala 310:49] - node _T_316 = bits(fghr, 7, 0) @[ifu_bp_ctl.scala 310:65] + node _T_314 = eq(num_valids, UInt<1>("h00")) @[ifu_bp_ctl.scala 311:41] + node _T_315 = bits(_T_314, 0, 0) @[ifu_bp_ctl.scala 311:49] + node _T_316 = bits(fghr, 7, 0) @[ifu_bp_ctl.scala 311:65] node _T_317 = mux(_T_306, _T_309, UInt<1>("h00")) @[Mux.scala 27:72] node _T_318 = mux(_T_311, _T_313, UInt<1>("h00")) @[Mux.scala 27:72] node _T_319 = mux(_T_315, _T_316, UInt<1>("h00")) @[Mux.scala 27:72] @@ -29567,21 +29567,21 @@ circuit quasar_wrapper : node _T_321 = or(_T_320, _T_319) @[Mux.scala 27:72] wire merged_ghr : UInt<8> @[Mux.scala 27:72] merged_ghr <= _T_321 @[Mux.scala 27:72] - wire fghr_ns : UInt<8> @[ifu_bp_ctl.scala 313:21] - node _T_322 = bits(exu_flush_final_d1, 0, 0) @[ifu_bp_ctl.scala 318:43] - node _T_323 = eq(exu_flush_final_d1, UInt<1>("h00")) @[ifu_bp_ctl.scala 319:27] - node _T_324 = and(_T_323, io.ifc_fetch_req_f) @[ifu_bp_ctl.scala 319:47] - node _T_325 = and(_T_324, io.ic_hit_f) @[ifu_bp_ctl.scala 319:70] - node _T_326 = eq(leak_one_f_d1, UInt<1>("h00")) @[ifu_bp_ctl.scala 319:86] - node _T_327 = and(_T_325, _T_326) @[ifu_bp_ctl.scala 319:84] - node _T_328 = bits(_T_327, 0, 0) @[ifu_bp_ctl.scala 319:102] - node _T_329 = eq(exu_flush_final_d1, UInt<1>("h00")) @[ifu_bp_ctl.scala 320:27] - node _T_330 = and(io.ifc_fetch_req_f, io.ic_hit_f) @[ifu_bp_ctl.scala 320:70] - node _T_331 = eq(leak_one_f_d1, UInt<1>("h00")) @[ifu_bp_ctl.scala 320:86] - node _T_332 = and(_T_330, _T_331) @[ifu_bp_ctl.scala 320:84] - node _T_333 = eq(_T_332, UInt<1>("h00")) @[ifu_bp_ctl.scala 320:49] - node _T_334 = and(_T_329, _T_333) @[ifu_bp_ctl.scala 320:47] - node _T_335 = bits(_T_334, 0, 0) @[ifu_bp_ctl.scala 320:103] + wire fghr_ns : UInt<8> @[ifu_bp_ctl.scala 314:21] + node _T_322 = bits(exu_flush_final_d1, 0, 0) @[ifu_bp_ctl.scala 319:43] + node _T_323 = eq(exu_flush_final_d1, UInt<1>("h00")) @[ifu_bp_ctl.scala 320:27] + node _T_324 = and(_T_323, io.ifc_fetch_req_f) @[ifu_bp_ctl.scala 320:47] + node _T_325 = and(_T_324, io.ic_hit_f) @[ifu_bp_ctl.scala 320:70] + node _T_326 = eq(leak_one_f_d1, UInt<1>("h00")) @[ifu_bp_ctl.scala 320:86] + node _T_327 = and(_T_325, _T_326) @[ifu_bp_ctl.scala 320:84] + node _T_328 = bits(_T_327, 0, 0) @[ifu_bp_ctl.scala 320:102] + node _T_329 = eq(exu_flush_final_d1, UInt<1>("h00")) @[ifu_bp_ctl.scala 321:27] + node _T_330 = and(io.ifc_fetch_req_f, io.ic_hit_f) @[ifu_bp_ctl.scala 321:70] + node _T_331 = eq(leak_one_f_d1, UInt<1>("h00")) @[ifu_bp_ctl.scala 321:86] + node _T_332 = and(_T_330, _T_331) @[ifu_bp_ctl.scala 321:84] + node _T_333 = eq(_T_332, UInt<1>("h00")) @[ifu_bp_ctl.scala 321:49] + node _T_334 = and(_T_329, _T_333) @[ifu_bp_ctl.scala 321:47] + node _T_335 = bits(_T_334, 0, 0) @[ifu_bp_ctl.scala 321:103] node _T_336 = mux(_T_322, io.exu_bp.exu_mp_fghr, UInt<1>("h00")) @[Mux.scala 27:72] node _T_337 = mux(_T_328, merged_ghr, UInt<1>("h00")) @[Mux.scala 27:72] node _T_338 = mux(_T_335, fghr, UInt<1>("h00")) @[Mux.scala 27:72] @@ -29589,56 +29589,56 @@ circuit quasar_wrapper : node _T_340 = or(_T_339, _T_338) @[Mux.scala 27:72] wire _T_341 : UInt<8> @[Mux.scala 27:72] _T_341 <= _T_340 @[Mux.scala 27:72] - fghr_ns <= _T_341 @[ifu_bp_ctl.scala 318:11] - reg _T_342 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_bp_ctl.scala 322:44] - _T_342 <= fghr_ns @[ifu_bp_ctl.scala 322:44] - fghr <= _T_342 @[ifu_bp_ctl.scala 322:8] - io.ifu_bp_fghr_f <= fghr @[ifu_bp_ctl.scala 324:20] - io.ifu_bp_hist1_f <= hist1_raw @[ifu_bp_ctl.scala 325:21] - io.ifu_bp_hist0_f <= hist0_raw @[ifu_bp_ctl.scala 326:21] - io.ifu_bp_pc4_f <= pc4_raw @[ifu_bp_ctl.scala 327:19] + fghr_ns <= _T_341 @[ifu_bp_ctl.scala 319:11] + reg _T_342 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_bp_ctl.scala 323:44] + _T_342 <= fghr_ns @[ifu_bp_ctl.scala 323:44] + fghr <= _T_342 @[ifu_bp_ctl.scala 323:8] + io.ifu_bp_fghr_f <= fghr @[ifu_bp_ctl.scala 325:20] + io.ifu_bp_hist1_f <= hist1_raw @[ifu_bp_ctl.scala 326:21] + io.ifu_bp_hist0_f <= hist0_raw @[ifu_bp_ctl.scala 327:21] + io.ifu_bp_pc4_f <= pc4_raw @[ifu_bp_ctl.scala 328:19] node _T_343 = bits(io.dec_bp.dec_tlu_bpred_disable, 0, 0) @[Bitwise.scala 72:15] node _T_344 = mux(_T_343, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_345 = not(_T_344) @[ifu_bp_ctl.scala 329:36] - node _T_346 = and(bht_valid_f, _T_345) @[ifu_bp_ctl.scala 329:34] - io.ifu_bp_valid_f <= _T_346 @[ifu_bp_ctl.scala 329:21] - io.ifu_bp_ret_f <= pret_raw @[ifu_bp_ctl.scala 330:19] - node _T_347 = bits(bht_dir_f, 0, 0) @[ifu_bp_ctl.scala 333:30] - node _T_348 = bits(fetch_start_f, 0, 0) @[ifu_bp_ctl.scala 333:50] - node _T_349 = eq(_T_348, UInt<1>("h00")) @[ifu_bp_ctl.scala 333:36] - node _T_350 = and(_T_347, _T_349) @[ifu_bp_ctl.scala 333:34] - node _T_351 = bits(bht_dir_f, 0, 0) @[ifu_bp_ctl.scala 333:68] - node _T_352 = eq(_T_351, UInt<1>("h00")) @[ifu_bp_ctl.scala 333:58] - node _T_353 = bits(fetch_start_f, 0, 0) @[ifu_bp_ctl.scala 333:87] - node _T_354 = and(_T_352, _T_353) @[ifu_bp_ctl.scala 333:72] - node _T_355 = or(_T_350, _T_354) @[ifu_bp_ctl.scala 333:55] - node _T_356 = bits(bht_dir_f, 0, 0) @[ifu_bp_ctl.scala 334:30] - node _T_357 = bits(fetch_start_f, 0, 0) @[ifu_bp_ctl.scala 334:49] - node _T_358 = and(_T_356, _T_357) @[ifu_bp_ctl.scala 334:34] - node _T_359 = bits(bht_dir_f, 0, 0) @[ifu_bp_ctl.scala 334:67] - node _T_360 = eq(_T_359, UInt<1>("h00")) @[ifu_bp_ctl.scala 334:57] - node _T_361 = bits(fetch_start_f, 0, 0) @[ifu_bp_ctl.scala 334:87] - node _T_362 = eq(_T_361, UInt<1>("h00")) @[ifu_bp_ctl.scala 334:73] - node _T_363 = and(_T_360, _T_362) @[ifu_bp_ctl.scala 334:71] - node _T_364 = or(_T_358, _T_363) @[ifu_bp_ctl.scala 334:54] + node _T_345 = not(_T_344) @[ifu_bp_ctl.scala 330:36] + node _T_346 = and(bht_valid_f, _T_345) @[ifu_bp_ctl.scala 330:34] + io.ifu_bp_valid_f <= _T_346 @[ifu_bp_ctl.scala 330:21] + io.ifu_bp_ret_f <= pret_raw @[ifu_bp_ctl.scala 331:19] + node _T_347 = bits(bht_dir_f, 0, 0) @[ifu_bp_ctl.scala 334:30] + node _T_348 = bits(fetch_start_f, 0, 0) @[ifu_bp_ctl.scala 334:50] + node _T_349 = eq(_T_348, UInt<1>("h00")) @[ifu_bp_ctl.scala 334:36] + node _T_350 = and(_T_347, _T_349) @[ifu_bp_ctl.scala 334:34] + node _T_351 = bits(bht_dir_f, 0, 0) @[ifu_bp_ctl.scala 334:68] + node _T_352 = eq(_T_351, UInt<1>("h00")) @[ifu_bp_ctl.scala 334:58] + node _T_353 = bits(fetch_start_f, 0, 0) @[ifu_bp_ctl.scala 334:87] + node _T_354 = and(_T_352, _T_353) @[ifu_bp_ctl.scala 334:72] + node _T_355 = or(_T_350, _T_354) @[ifu_bp_ctl.scala 334:55] + node _T_356 = bits(bht_dir_f, 0, 0) @[ifu_bp_ctl.scala 335:30] + node _T_357 = bits(fetch_start_f, 0, 0) @[ifu_bp_ctl.scala 335:49] + node _T_358 = and(_T_356, _T_357) @[ifu_bp_ctl.scala 335:34] + node _T_359 = bits(bht_dir_f, 0, 0) @[ifu_bp_ctl.scala 335:67] + node _T_360 = eq(_T_359, UInt<1>("h00")) @[ifu_bp_ctl.scala 335:57] + node _T_361 = bits(fetch_start_f, 0, 0) @[ifu_bp_ctl.scala 335:87] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[ifu_bp_ctl.scala 335:73] + node _T_363 = and(_T_360, _T_362) @[ifu_bp_ctl.scala 335:71] + node _T_364 = or(_T_358, _T_363) @[ifu_bp_ctl.scala 335:54] node bloc_f = cat(_T_355, _T_364) @[Cat.scala 29:58] - node _T_365 = bits(bht_dir_f, 0, 0) @[ifu_bp_ctl.scala 336:31] - node _T_366 = eq(_T_365, UInt<1>("h00")) @[ifu_bp_ctl.scala 336:21] - node _T_367 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 336:56] - node _T_368 = and(_T_366, _T_367) @[ifu_bp_ctl.scala 336:35] - node _T_369 = eq(btb_rd_pc4_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 336:62] - node use_fa_plus = and(_T_368, _T_369) @[ifu_bp_ctl.scala 336:60] - node _T_370 = bits(fetch_start_f, 0, 0) @[ifu_bp_ctl.scala 338:40] - node _T_371 = bits(btb_sel_f, 0, 0) @[ifu_bp_ctl.scala 338:55] - node _T_372 = and(_T_370, _T_371) @[ifu_bp_ctl.scala 338:44] - node btb_fg_crossing_f = and(_T_372, btb_rd_pc4_f) @[ifu_bp_ctl.scala 338:59] - node _T_373 = bits(bloc_f, 1, 1) @[ifu_bp_ctl.scala 339:40] - node bp_total_branch_offset_f = xor(_T_373, btb_rd_pc4_f) @[ifu_bp_ctl.scala 339:43] - node _T_374 = bits(io.ifc_fetch_addr_f, 30, 1) @[ifu_bp_ctl.scala 341:57] - node _T_375 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 341:87] - node _T_376 = and(io.ifc_fetch_req_f, _T_375) @[ifu_bp_ctl.scala 341:85] - node _T_377 = and(_T_376, io.ic_hit_f) @[ifu_bp_ctl.scala 341:110] - node _T_378 = bits(_T_377, 0, 0) @[ifu_bp_ctl.scala 341:125] + node _T_365 = bits(bht_dir_f, 0, 0) @[ifu_bp_ctl.scala 337:31] + node _T_366 = eq(_T_365, UInt<1>("h00")) @[ifu_bp_ctl.scala 337:21] + node _T_367 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_bp_ctl.scala 337:56] + node _T_368 = and(_T_366, _T_367) @[ifu_bp_ctl.scala 337:35] + node _T_369 = eq(btb_rd_pc4_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 337:62] + node use_fa_plus = and(_T_368, _T_369) @[ifu_bp_ctl.scala 337:60] + node _T_370 = bits(fetch_start_f, 0, 0) @[ifu_bp_ctl.scala 339:40] + node _T_371 = bits(btb_sel_f, 0, 0) @[ifu_bp_ctl.scala 339:55] + node _T_372 = and(_T_370, _T_371) @[ifu_bp_ctl.scala 339:44] + node btb_fg_crossing_f = and(_T_372, btb_rd_pc4_f) @[ifu_bp_ctl.scala 339:59] + node _T_373 = bits(bloc_f, 1, 1) @[ifu_bp_ctl.scala 340:40] + node bp_total_branch_offset_f = xor(_T_373, btb_rd_pc4_f) @[ifu_bp_ctl.scala 340:43] + node _T_374 = bits(io.ifc_fetch_addr_f, 30, 1) @[ifu_bp_ctl.scala 342:57] + node _T_375 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 342:87] + node _T_376 = and(io.ifc_fetch_req_f, _T_375) @[ifu_bp_ctl.scala 342:85] + node _T_377 = and(_T_376, io.ic_hit_f) @[ifu_bp_ctl.scala 342:110] + node _T_378 = bits(_T_377, 0, 0) @[ifu_bp_ctl.scala 342:125] inst rvclkhdr_1 of rvclkhdr_95 @[lib.scala 352:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -29647,14 +29647,14 @@ circuit quasar_wrapper : rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg ifc_fetch_adder_prior : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] ifc_fetch_adder_prior <= _T_374 @[lib.scala 358:16] - io.ifu_bp_poffset_f <= btb_rd_tgt_f @[ifu_bp_ctl.scala 343:23] - node _T_379 = bits(use_fa_plus, 0, 0) @[ifu_bp_ctl.scala 345:45] - node _T_380 = bits(btb_fg_crossing_f, 0, 0) @[ifu_bp_ctl.scala 346:51] - node _T_381 = eq(btb_fg_crossing_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 347:32] - node _T_382 = eq(use_fa_plus, UInt<1>("h00")) @[ifu_bp_ctl.scala 347:53] - node _T_383 = and(_T_381, _T_382) @[ifu_bp_ctl.scala 347:51] - node _T_384 = bits(_T_383, 0, 0) @[ifu_bp_ctl.scala 347:67] - node _T_385 = bits(io.ifc_fetch_addr_f, 30, 1) @[ifu_bp_ctl.scala 347:95] + io.ifu_bp_poffset_f <= btb_rd_tgt_f @[ifu_bp_ctl.scala 344:23] + node _T_379 = bits(use_fa_plus, 0, 0) @[ifu_bp_ctl.scala 346:45] + node _T_380 = bits(btb_fg_crossing_f, 0, 0) @[ifu_bp_ctl.scala 347:51] + node _T_381 = eq(btb_fg_crossing_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 348:32] + node _T_382 = eq(use_fa_plus, UInt<1>("h00")) @[ifu_bp_ctl.scala 348:53] + node _T_383 = and(_T_381, _T_382) @[ifu_bp_ctl.scala 348:51] + node _T_384 = bits(_T_383, 0, 0) @[ifu_bp_ctl.scala 348:67] + node _T_385 = bits(io.ifc_fetch_addr_f, 30, 1) @[ifu_bp_ctl.scala 348:95] node _T_386 = mux(_T_379, fetch_addr_p1_f, UInt<1>("h00")) @[Mux.scala 27:72] node _T_387 = mux(_T_380, ifc_fetch_adder_prior, UInt<1>("h00")) @[Mux.scala 27:72] node _T_388 = mux(_T_384, _T_385, UInt<1>("h00")) @[Mux.scala 27:72] @@ -29662,7 +29662,7 @@ circuit quasar_wrapper : node _T_390 = or(_T_389, _T_388) @[Mux.scala 27:72] wire adder_pc_in_f : UInt @[Mux.scala 27:72] adder_pc_in_f <= _T_390 @[Mux.scala 27:72] - node _T_391 = bits(adder_pc_in_f, 29, 0) @[ifu_bp_ctl.scala 350:58] + node _T_391 = bits(adder_pc_in_f, 29, 0) @[ifu_bp_ctl.scala 351:58] node _T_392 = cat(_T_391, bp_total_branch_offset_f) @[Cat.scala 29:58] node _T_393 = cat(_T_392, UInt<1>("h00")) @[Cat.scala 29:58] node _T_394 = cat(btb_rd_tgt_f, UInt<1>("h00")) @[Cat.scala 29:58] @@ -29699,29 +29699,29 @@ circuit quasar_wrapper : node _T_424 = bits(_T_397, 11, 0) @[lib.scala 58:94] node _T_425 = cat(_T_423, _T_424) @[Cat.scala 29:58] node bp_btb_target_adder_f = cat(_T_425, UInt<1>("h00")) @[Cat.scala 29:58] - wire rets_out : UInt<32>[8] @[ifu_bp_ctl.scala 352:22] - rets_out[0] <= UInt<1>("h00") @[ifu_bp_ctl.scala 353:12] - rets_out[1] <= UInt<1>("h00") @[ifu_bp_ctl.scala 353:12] - rets_out[2] <= UInt<1>("h00") @[ifu_bp_ctl.scala 353:12] - rets_out[3] <= UInt<1>("h00") @[ifu_bp_ctl.scala 353:12] - rets_out[4] <= UInt<1>("h00") @[ifu_bp_ctl.scala 353:12] - rets_out[5] <= UInt<1>("h00") @[ifu_bp_ctl.scala 353:12] - rets_out[6] <= UInt<1>("h00") @[ifu_bp_ctl.scala 353:12] - rets_out[7] <= UInt<1>("h00") @[ifu_bp_ctl.scala 353:12] - node _T_426 = eq(btb_rd_call_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 356:49] - node _T_427 = and(btb_rd_ret_f, _T_426) @[ifu_bp_ctl.scala 356:47] - node _T_428 = bits(rets_out[0], 0, 0) @[ifu_bp_ctl.scala 356:77] - node _T_429 = and(_T_427, _T_428) @[ifu_bp_ctl.scala 356:64] - node _T_430 = bits(_T_429, 0, 0) @[ifu_bp_ctl.scala 356:82] - node _T_431 = bits(rets_out[0], 31, 1) @[ifu_bp_ctl.scala 357:46] - node _T_432 = bits(bp_btb_target_adder_f, 31, 1) @[ifu_bp_ctl.scala 357:74] - node _T_433 = mux(_T_430, _T_431, _T_432) @[ifu_bp_ctl.scala 356:32] - io.ifu_bp_btb_target_f <= _T_433 @[ifu_bp_ctl.scala 356:26] - node _T_434 = bits(adder_pc_in_f, 29, 0) @[ifu_bp_ctl.scala 360:56] + wire rets_out : UInt<32>[8] @[ifu_bp_ctl.scala 353:22] + rets_out[0] <= UInt<1>("h00") @[ifu_bp_ctl.scala 354:12] + rets_out[1] <= UInt<1>("h00") @[ifu_bp_ctl.scala 354:12] + rets_out[2] <= UInt<1>("h00") @[ifu_bp_ctl.scala 354:12] + rets_out[3] <= UInt<1>("h00") @[ifu_bp_ctl.scala 354:12] + rets_out[4] <= UInt<1>("h00") @[ifu_bp_ctl.scala 354:12] + rets_out[5] <= UInt<1>("h00") @[ifu_bp_ctl.scala 354:12] + rets_out[6] <= UInt<1>("h00") @[ifu_bp_ctl.scala 354:12] + rets_out[7] <= UInt<1>("h00") @[ifu_bp_ctl.scala 354:12] + node _T_426 = eq(btb_rd_call_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 357:49] + node _T_427 = and(btb_rd_ret_f, _T_426) @[ifu_bp_ctl.scala 357:47] + node _T_428 = bits(rets_out[0], 0, 0) @[ifu_bp_ctl.scala 357:77] + node _T_429 = and(_T_427, _T_428) @[ifu_bp_ctl.scala 357:64] + node _T_430 = bits(_T_429, 0, 0) @[ifu_bp_ctl.scala 357:82] + node _T_431 = bits(rets_out[0], 31, 1) @[ifu_bp_ctl.scala 358:46] + node _T_432 = bits(bp_btb_target_adder_f, 31, 1) @[ifu_bp_ctl.scala 358:74] + node _T_433 = mux(_T_430, _T_431, _T_432) @[ifu_bp_ctl.scala 357:32] + io.ifu_bp_btb_target_f <= _T_433 @[ifu_bp_ctl.scala 357:26] + node _T_434 = bits(adder_pc_in_f, 29, 0) @[ifu_bp_ctl.scala 361:56] node _T_435 = cat(_T_434, bp_total_branch_offset_f) @[Cat.scala 29:58] node _T_436 = cat(_T_435, UInt<1>("h00")) @[Cat.scala 29:58] node _T_437 = mux(UInt<1>("h00"), UInt<11>("h07ff"), UInt<11>("h00")) @[Bitwise.scala 72:12] - node _T_438 = not(btb_rd_pc4_f) @[ifu_bp_ctl.scala 360:113] + node _T_438 = not(btb_rd_pc4_f) @[ifu_bp_ctl.scala 361:113] node _T_439 = cat(_T_437, _T_438) @[Cat.scala 29:58] node _T_440 = cat(_T_439, UInt<1>("h00")) @[Cat.scala 29:58] node _T_441 = bits(_T_436, 12, 1) @[lib.scala 52:24] @@ -29757,74 +29757,74 @@ circuit quasar_wrapper : node _T_470 = bits(_T_443, 11, 0) @[lib.scala 58:94] node _T_471 = cat(_T_469, _T_470) @[Cat.scala 29:58] node bp_rs_call_target_f = cat(_T_471, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_472 = eq(btb_rd_ret_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 362:33] - node _T_473 = and(btb_rd_call_f, _T_472) @[ifu_bp_ctl.scala 362:31] - node rs_push = and(_T_473, io.ifu_bp_hit_taken_f) @[ifu_bp_ctl.scala 362:47] - node _T_474 = eq(btb_rd_call_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 363:31] - node _T_475 = and(btb_rd_ret_f, _T_474) @[ifu_bp_ctl.scala 363:29] - node rs_pop = and(_T_475, io.ifu_bp_hit_taken_f) @[ifu_bp_ctl.scala 363:46] - node _T_476 = eq(rs_push, UInt<1>("h00")) @[ifu_bp_ctl.scala 364:17] - node _T_477 = eq(rs_pop, UInt<1>("h00")) @[ifu_bp_ctl.scala 364:28] - node rs_hold = and(_T_476, _T_477) @[ifu_bp_ctl.scala 364:26] - node rsenable_0 = eq(rs_hold, UInt<1>("h00")) @[ifu_bp_ctl.scala 366:60] - node rsenable_1 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 366:119] - node rsenable_2 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 366:119] - node rsenable_3 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 366:119] - node rsenable_4 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 366:119] - node rsenable_5 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 366:119] - node rsenable_6 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 366:119] - node _T_478 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 370:23] - node _T_479 = bits(bp_rs_call_target_f, 31, 1) @[ifu_bp_ctl.scala 370:56] + node _T_472 = eq(btb_rd_ret_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 363:33] + node _T_473 = and(btb_rd_call_f, _T_472) @[ifu_bp_ctl.scala 363:31] + node rs_push = and(_T_473, io.ifu_bp_hit_taken_f) @[ifu_bp_ctl.scala 363:47] + node _T_474 = eq(btb_rd_call_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 364:31] + node _T_475 = and(btb_rd_ret_f, _T_474) @[ifu_bp_ctl.scala 364:29] + node rs_pop = and(_T_475, io.ifu_bp_hit_taken_f) @[ifu_bp_ctl.scala 364:46] + node _T_476 = eq(rs_push, UInt<1>("h00")) @[ifu_bp_ctl.scala 365:17] + node _T_477 = eq(rs_pop, UInt<1>("h00")) @[ifu_bp_ctl.scala 365:28] + node rs_hold = and(_T_476, _T_477) @[ifu_bp_ctl.scala 365:26] + node rsenable_0 = eq(rs_hold, UInt<1>("h00")) @[ifu_bp_ctl.scala 367:60] + node rsenable_1 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 367:119] + node rsenable_2 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 367:119] + node rsenable_3 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 367:119] + node rsenable_4 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 367:119] + node rsenable_5 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 367:119] + node rsenable_6 = or(rs_push, rs_pop) @[ifu_bp_ctl.scala 367:119] + node _T_478 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 371:23] + node _T_479 = bits(bp_rs_call_target_f, 31, 1) @[ifu_bp_ctl.scala 371:56] node _T_480 = cat(_T_479, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_481 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 371:22] + node _T_481 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 372:22] node _T_482 = mux(_T_478, _T_480, UInt<1>("h00")) @[Mux.scala 27:72] node _T_483 = mux(_T_481, rets_out[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_484 = or(_T_482, _T_483) @[Mux.scala 27:72] wire rets_in_0 : UInt<32> @[Mux.scala 27:72] rets_in_0 <= _T_484 @[Mux.scala 27:72] - node _T_485 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 373:28] - node _T_486 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 374:27] + node _T_485 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 374:28] + node _T_486 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 375:27] node _T_487 = mux(_T_485, rets_out[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_488 = mux(_T_486, rets_out[2], UInt<1>("h00")) @[Mux.scala 27:72] node _T_489 = or(_T_487, _T_488) @[Mux.scala 27:72] wire rets_in_1 : UInt<32> @[Mux.scala 27:72] rets_in_1 <= _T_489 @[Mux.scala 27:72] - node _T_490 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 373:28] - node _T_491 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 374:27] + node _T_490 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 374:28] + node _T_491 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 375:27] node _T_492 = mux(_T_490, rets_out[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_493 = mux(_T_491, rets_out[3], UInt<1>("h00")) @[Mux.scala 27:72] node _T_494 = or(_T_492, _T_493) @[Mux.scala 27:72] wire rets_in_2 : UInt<32> @[Mux.scala 27:72] rets_in_2 <= _T_494 @[Mux.scala 27:72] - node _T_495 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 373:28] - node _T_496 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 374:27] + node _T_495 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 374:28] + node _T_496 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 375:27] node _T_497 = mux(_T_495, rets_out[2], UInt<1>("h00")) @[Mux.scala 27:72] node _T_498 = mux(_T_496, rets_out[4], UInt<1>("h00")) @[Mux.scala 27:72] node _T_499 = or(_T_497, _T_498) @[Mux.scala 27:72] wire rets_in_3 : UInt<32> @[Mux.scala 27:72] rets_in_3 <= _T_499 @[Mux.scala 27:72] - node _T_500 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 373:28] - node _T_501 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 374:27] + node _T_500 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 374:28] + node _T_501 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 375:27] node _T_502 = mux(_T_500, rets_out[3], UInt<1>("h00")) @[Mux.scala 27:72] node _T_503 = mux(_T_501, rets_out[5], UInt<1>("h00")) @[Mux.scala 27:72] node _T_504 = or(_T_502, _T_503) @[Mux.scala 27:72] wire rets_in_4 : UInt<32> @[Mux.scala 27:72] rets_in_4 <= _T_504 @[Mux.scala 27:72] - node _T_505 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 373:28] - node _T_506 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 374:27] + node _T_505 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 374:28] + node _T_506 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 375:27] node _T_507 = mux(_T_505, rets_out[4], UInt<1>("h00")) @[Mux.scala 27:72] node _T_508 = mux(_T_506, rets_out[6], UInt<1>("h00")) @[Mux.scala 27:72] node _T_509 = or(_T_507, _T_508) @[Mux.scala 27:72] wire rets_in_5 : UInt<32> @[Mux.scala 27:72] rets_in_5 <= _T_509 @[Mux.scala 27:72] - node _T_510 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 373:28] - node _T_511 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 374:27] + node _T_510 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 374:28] + node _T_511 = bits(rs_pop, 0, 0) @[ifu_bp_ctl.scala 375:27] node _T_512 = mux(_T_510, rets_out[5], UInt<1>("h00")) @[Mux.scala 27:72] node _T_513 = mux(_T_511, rets_out[7], UInt<1>("h00")) @[Mux.scala 27:72] node _T_514 = or(_T_512, _T_513) @[Mux.scala 27:72] wire rets_in_6 : UInt<32> @[Mux.scala 27:72] rets_in_6 <= _T_514 @[Mux.scala 27:72] - node _T_515 = bits(rsenable_0, 0, 0) @[ifu_bp_ctl.scala 377:78] + node _T_515 = bits(rsenable_0, 0, 0) @[ifu_bp_ctl.scala 378:78] inst rvclkhdr_2 of rvclkhdr_96 @[lib.scala 352:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -29833,7 +29833,7 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_516 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_516 <= rets_in_0 @[lib.scala 358:16] - node _T_517 = bits(rsenable_1, 0, 0) @[ifu_bp_ctl.scala 377:78] + node _T_517 = bits(rsenable_1, 0, 0) @[ifu_bp_ctl.scala 378:78] inst rvclkhdr_3 of rvclkhdr_97 @[lib.scala 352:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -29842,7 +29842,7 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_518 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_518 <= rets_in_1 @[lib.scala 358:16] - node _T_519 = bits(rsenable_2, 0, 0) @[ifu_bp_ctl.scala 377:78] + node _T_519 = bits(rsenable_2, 0, 0) @[ifu_bp_ctl.scala 378:78] inst rvclkhdr_4 of rvclkhdr_98 @[lib.scala 352:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -29851,7 +29851,7 @@ circuit quasar_wrapper : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_520 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_520 <= rets_in_2 @[lib.scala 358:16] - node _T_521 = bits(rsenable_3, 0, 0) @[ifu_bp_ctl.scala 377:78] + node _T_521 = bits(rsenable_3, 0, 0) @[ifu_bp_ctl.scala 378:78] inst rvclkhdr_5 of rvclkhdr_99 @[lib.scala 352:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -29860,7 +29860,7 @@ circuit quasar_wrapper : rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_522 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_522 <= rets_in_3 @[lib.scala 358:16] - node _T_523 = bits(rsenable_4, 0, 0) @[ifu_bp_ctl.scala 377:78] + node _T_523 = bits(rsenable_4, 0, 0) @[ifu_bp_ctl.scala 378:78] inst rvclkhdr_6 of rvclkhdr_100 @[lib.scala 352:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset @@ -29869,7 +29869,7 @@ circuit quasar_wrapper : rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_524 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_524 <= rets_in_4 @[lib.scala 358:16] - node _T_525 = bits(rsenable_5, 0, 0) @[ifu_bp_ctl.scala 377:78] + node _T_525 = bits(rsenable_5, 0, 0) @[ifu_bp_ctl.scala 378:78] inst rvclkhdr_7 of rvclkhdr_101 @[lib.scala 352:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset @@ -29878,7 +29878,7 @@ circuit quasar_wrapper : rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_526 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_526 <= rets_in_5 @[lib.scala 358:16] - node _T_527 = bits(rsenable_6, 0, 0) @[ifu_bp_ctl.scala 377:78] + node _T_527 = bits(rsenable_6, 0, 0) @[ifu_bp_ctl.scala 378:78] inst rvclkhdr_8 of rvclkhdr_102 @[lib.scala 352:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset @@ -29887,7 +29887,7 @@ circuit quasar_wrapper : rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_528 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_528 <= rets_in_6 @[lib.scala 358:16] - node _T_529 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 377:78] + node _T_529 = bits(rs_push, 0, 0) @[ifu_bp_ctl.scala 378:78] inst rvclkhdr_9 of rvclkhdr_103 @[lib.scala 352:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset @@ -29896,56 +29896,56 @@ circuit quasar_wrapper : rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_530 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_530 <= rets_out[6] @[lib.scala 358:16] - rets_out[0] <= _T_516 @[ifu_bp_ctl.scala 377:12] - rets_out[1] <= _T_518 @[ifu_bp_ctl.scala 377:12] - rets_out[2] <= _T_520 @[ifu_bp_ctl.scala 377:12] - rets_out[3] <= _T_522 @[ifu_bp_ctl.scala 377:12] - rets_out[4] <= _T_524 @[ifu_bp_ctl.scala 377:12] - rets_out[5] <= _T_526 @[ifu_bp_ctl.scala 377:12] - rets_out[6] <= _T_528 @[ifu_bp_ctl.scala 377:12] - rets_out[7] <= _T_530 @[ifu_bp_ctl.scala 377:12] - node _T_531 = eq(dec_tlu_error_wb, UInt<1>("h00")) @[ifu_bp_ctl.scala 379:35] - node btb_valid = and(exu_mp_valid, _T_531) @[ifu_bp_ctl.scala 379:32] - node _T_532 = or(io.exu_bp.exu_mp_pkt.bits.pcall, io.exu_bp.exu_mp_pkt.bits.pja) @[ifu_bp_ctl.scala 383:89] - node _T_533 = or(io.exu_bp.exu_mp_pkt.bits.pret, io.exu_bp.exu_mp_pkt.bits.pja) @[ifu_bp_ctl.scala 383:113] + rets_out[0] <= _T_516 @[ifu_bp_ctl.scala 378:12] + rets_out[1] <= _T_518 @[ifu_bp_ctl.scala 378:12] + rets_out[2] <= _T_520 @[ifu_bp_ctl.scala 378:12] + rets_out[3] <= _T_522 @[ifu_bp_ctl.scala 378:12] + rets_out[4] <= _T_524 @[ifu_bp_ctl.scala 378:12] + rets_out[5] <= _T_526 @[ifu_bp_ctl.scala 378:12] + rets_out[6] <= _T_528 @[ifu_bp_ctl.scala 378:12] + rets_out[7] <= _T_530 @[ifu_bp_ctl.scala 378:12] + node _T_531 = eq(dec_tlu_error_wb, UInt<1>("h00")) @[ifu_bp_ctl.scala 380:35] + node btb_valid = and(exu_mp_valid, _T_531) @[ifu_bp_ctl.scala 380:32] + node _T_532 = or(io.exu_bp.exu_mp_pkt.bits.pcall, io.exu_bp.exu_mp_pkt.bits.pja) @[ifu_bp_ctl.scala 384:89] + node _T_533 = or(io.exu_bp.exu_mp_pkt.bits.pret, io.exu_bp.exu_mp_pkt.bits.pja) @[ifu_bp_ctl.scala 384:113] node _T_534 = cat(_T_532, _T_533) @[Cat.scala 29:58] node _T_535 = cat(_T_534, btb_valid) @[Cat.scala 29:58] node _T_536 = cat(io.exu_bp.exu_mp_pkt.bits.pc4, io.exu_bp.exu_mp_pkt.bits.boffset) @[Cat.scala 29:58] node _T_537 = cat(io.exu_bp.exu_mp_btag, io.exu_bp.exu_mp_pkt.bits.toffset) @[Cat.scala 29:58] node _T_538 = cat(_T_537, _T_536) @[Cat.scala 29:58] node btb_wr_data = cat(_T_538, _T_535) @[Cat.scala 29:58] - node exu_mp_valid_write = and(exu_mp_valid, io.exu_bp.exu_mp_pkt.bits.ataken) @[ifu_bp_ctl.scala 384:41] - node _T_539 = eq(io.exu_bp.exu_mp_pkt.bits.way, UInt<1>("h00")) @[ifu_bp_ctl.scala 387:26] - node _T_540 = and(_T_539, exu_mp_valid_write) @[ifu_bp_ctl.scala 387:39] - node _T_541 = eq(dec_tlu_error_wb, UInt<1>("h00")) @[ifu_bp_ctl.scala 387:63] - node _T_542 = and(_T_540, _T_541) @[ifu_bp_ctl.scala 387:60] - node _T_543 = eq(dec_tlu_way_wb, UInt<1>("h00")) @[ifu_bp_ctl.scala 387:87] - node _T_544 = and(_T_543, dec_tlu_error_wb) @[ifu_bp_ctl.scala 387:104] - node btb_wr_en_way0 = or(_T_542, _T_544) @[ifu_bp_ctl.scala 387:83] - node _T_545 = and(io.exu_bp.exu_mp_pkt.bits.way, exu_mp_valid_write) @[ifu_bp_ctl.scala 388:36] - node _T_546 = eq(dec_tlu_error_wb, UInt<1>("h00")) @[ifu_bp_ctl.scala 388:60] - node _T_547 = and(_T_545, _T_546) @[ifu_bp_ctl.scala 388:57] - node _T_548 = and(dec_tlu_way_wb, dec_tlu_error_wb) @[ifu_bp_ctl.scala 388:98] - node btb_wr_en_way1 = or(_T_547, _T_548) @[ifu_bp_ctl.scala 388:80] - node _T_549 = bits(dec_tlu_error_wb, 0, 0) @[ifu_bp_ctl.scala 391:42] - node btb_wr_addr = mux(_T_549, btb_error_addr_wb, io.exu_bp.exu_mp_index) @[ifu_bp_ctl.scala 391:24] - node middle_of_bank = xor(io.exu_bp.exu_mp_pkt.bits.pc4, io.exu_bp.exu_mp_pkt.bits.boffset) @[ifu_bp_ctl.scala 392:35] - node _T_550 = eq(io.exu_bp.exu_mp_pkt.bits.pcall, UInt<1>("h00")) @[ifu_bp_ctl.scala 395:43] - node _T_551 = and(exu_mp_valid, _T_550) @[ifu_bp_ctl.scala 395:41] - node _T_552 = eq(io.exu_bp.exu_mp_pkt.bits.pret, UInt<1>("h00")) @[ifu_bp_ctl.scala 395:58] - node _T_553 = and(_T_551, _T_552) @[ifu_bp_ctl.scala 395:56] - node _T_554 = eq(io.exu_bp.exu_mp_pkt.bits.pja, UInt<1>("h00")) @[ifu_bp_ctl.scala 395:72] - node _T_555 = and(_T_553, _T_554) @[ifu_bp_ctl.scala 395:70] + node exu_mp_valid_write = and(exu_mp_valid, io.exu_bp.exu_mp_pkt.bits.ataken) @[ifu_bp_ctl.scala 385:41] + node _T_539 = eq(io.exu_bp.exu_mp_pkt.bits.way, UInt<1>("h00")) @[ifu_bp_ctl.scala 388:26] + node _T_540 = and(_T_539, exu_mp_valid_write) @[ifu_bp_ctl.scala 388:39] + node _T_541 = eq(dec_tlu_error_wb, UInt<1>("h00")) @[ifu_bp_ctl.scala 388:63] + node _T_542 = and(_T_540, _T_541) @[ifu_bp_ctl.scala 388:60] + node _T_543 = eq(dec_tlu_way_wb, UInt<1>("h00")) @[ifu_bp_ctl.scala 388:87] + node _T_544 = and(_T_543, dec_tlu_error_wb) @[ifu_bp_ctl.scala 388:104] + node btb_wr_en_way0 = or(_T_542, _T_544) @[ifu_bp_ctl.scala 388:83] + node _T_545 = and(io.exu_bp.exu_mp_pkt.bits.way, exu_mp_valid_write) @[ifu_bp_ctl.scala 389:36] + node _T_546 = eq(dec_tlu_error_wb, UInt<1>("h00")) @[ifu_bp_ctl.scala 389:60] + node _T_547 = and(_T_545, _T_546) @[ifu_bp_ctl.scala 389:57] + node _T_548 = and(dec_tlu_way_wb, dec_tlu_error_wb) @[ifu_bp_ctl.scala 389:98] + node btb_wr_en_way1 = or(_T_547, _T_548) @[ifu_bp_ctl.scala 389:80] + node _T_549 = bits(dec_tlu_error_wb, 0, 0) @[ifu_bp_ctl.scala 392:42] + node btb_wr_addr = mux(_T_549, btb_error_addr_wb, io.exu_bp.exu_mp_index) @[ifu_bp_ctl.scala 392:24] + node middle_of_bank = xor(io.exu_bp.exu_mp_pkt.bits.pc4, io.exu_bp.exu_mp_pkt.bits.boffset) @[ifu_bp_ctl.scala 393:35] + node _T_550 = eq(io.exu_bp.exu_mp_pkt.bits.pcall, UInt<1>("h00")) @[ifu_bp_ctl.scala 396:43] + node _T_551 = and(exu_mp_valid, _T_550) @[ifu_bp_ctl.scala 396:41] + node _T_552 = eq(io.exu_bp.exu_mp_pkt.bits.pret, UInt<1>("h00")) @[ifu_bp_ctl.scala 396:58] + node _T_553 = and(_T_551, _T_552) @[ifu_bp_ctl.scala 396:56] + node _T_554 = eq(io.exu_bp.exu_mp_pkt.bits.pja, UInt<1>("h00")) @[ifu_bp_ctl.scala 396:72] + node _T_555 = and(_T_553, _T_554) @[ifu_bp_ctl.scala 396:70] node _T_556 = bits(_T_555, 0, 0) @[Bitwise.scala 72:15] node _T_557 = mux(_T_556, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_558 = not(middle_of_bank) @[ifu_bp_ctl.scala 395:106] + node _T_558 = not(middle_of_bank) @[ifu_bp_ctl.scala 396:106] node _T_559 = cat(middle_of_bank, _T_558) @[Cat.scala 29:58] - node bht_wr_en0 = and(_T_557, _T_559) @[ifu_bp_ctl.scala 395:84] + node bht_wr_en0 = and(_T_557, _T_559) @[ifu_bp_ctl.scala 396:84] node _T_560 = bits(io.dec_bp.dec_tlu_br0_r_pkt.valid, 0, 0) @[Bitwise.scala 72:15] node _T_561 = mux(_T_560, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_562 = not(io.dec_bp.dec_tlu_br0_r_pkt.bits.middle) @[ifu_bp_ctl.scala 396:75] + node _T_562 = not(io.dec_bp.dec_tlu_br0_r_pkt.bits.middle) @[ifu_bp_ctl.scala 397:75] node _T_563 = cat(io.dec_bp.dec_tlu_br0_r_pkt.bits.middle, _T_562) @[Cat.scala 29:58] - node bht_wr_en2 = and(_T_561, _T_563) @[ifu_bp_ctl.scala 396:46] + node bht_wr_en2 = and(_T_561, _T_563) @[ifu_bp_ctl.scala 397:46] node _T_564 = cat(io.exu_bp.exu_mp_index, UInt<2>("h00")) @[Cat.scala 29:58] node _T_565 = bits(_T_564, 9, 2) @[lib.scala 40:16] node _T_566 = bits(io.exu_bp.exu_mp_eghr, 7, 0) @[lib.scala 40:40] @@ -29962,9 +29962,9 @@ circuit quasar_wrapper : node _T_574 = bits(_T_573, 9, 2) @[lib.scala 40:16] node _T_575 = bits(fghr, 7, 0) @[lib.scala 40:40] node bht_rd_addr_hashed_p1_f = xor(_T_574, _T_575) @[lib.scala 40:35] - node _T_576 = eq(btb_wr_addr, UInt<1>("h00")) @[ifu_bp_ctl.scala 414:95] - node _T_577 = and(_T_576, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_578 = bits(_T_577, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_576 = eq(btb_wr_addr, UInt<1>("h00")) @[ifu_bp_ctl.scala 415:95] + node _T_577 = and(_T_576, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_578 = bits(_T_577, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_10 of rvclkhdr_104 @[lib.scala 352:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset @@ -29973,9 +29973,9 @@ circuit quasar_wrapper : rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_0 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_0 <= btb_wr_data @[lib.scala 358:16] - node _T_579 = eq(btb_wr_addr, UInt<1>("h01")) @[ifu_bp_ctl.scala 414:95] - node _T_580 = and(_T_579, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_581 = bits(_T_580, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_579 = eq(btb_wr_addr, UInt<1>("h01")) @[ifu_bp_ctl.scala 415:95] + node _T_580 = and(_T_579, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_581 = bits(_T_580, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_11 of rvclkhdr_105 @[lib.scala 352:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset @@ -29984,9 +29984,9 @@ circuit quasar_wrapper : rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_1 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_1 <= btb_wr_data @[lib.scala 358:16] - node _T_582 = eq(btb_wr_addr, UInt<2>("h02")) @[ifu_bp_ctl.scala 414:95] - node _T_583 = and(_T_582, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_584 = bits(_T_583, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_582 = eq(btb_wr_addr, UInt<2>("h02")) @[ifu_bp_ctl.scala 415:95] + node _T_583 = and(_T_582, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_584 = bits(_T_583, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_12 of rvclkhdr_106 @[lib.scala 352:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset @@ -29995,9 +29995,9 @@ circuit quasar_wrapper : rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_2 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_2 <= btb_wr_data @[lib.scala 358:16] - node _T_585 = eq(btb_wr_addr, UInt<2>("h03")) @[ifu_bp_ctl.scala 414:95] - node _T_586 = and(_T_585, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_587 = bits(_T_586, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_585 = eq(btb_wr_addr, UInt<2>("h03")) @[ifu_bp_ctl.scala 415:95] + node _T_586 = and(_T_585, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_587 = bits(_T_586, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_13 of rvclkhdr_107 @[lib.scala 352:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset @@ -30006,9 +30006,9 @@ circuit quasar_wrapper : rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_3 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_3 <= btb_wr_data @[lib.scala 358:16] - node _T_588 = eq(btb_wr_addr, UInt<3>("h04")) @[ifu_bp_ctl.scala 414:95] - node _T_589 = and(_T_588, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_590 = bits(_T_589, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_588 = eq(btb_wr_addr, UInt<3>("h04")) @[ifu_bp_ctl.scala 415:95] + node _T_589 = and(_T_588, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_590 = bits(_T_589, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_14 of rvclkhdr_108 @[lib.scala 352:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset @@ -30017,9 +30017,9 @@ circuit quasar_wrapper : rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_4 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_4 <= btb_wr_data @[lib.scala 358:16] - node _T_591 = eq(btb_wr_addr, UInt<3>("h05")) @[ifu_bp_ctl.scala 414:95] - node _T_592 = and(_T_591, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_593 = bits(_T_592, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_591 = eq(btb_wr_addr, UInt<3>("h05")) @[ifu_bp_ctl.scala 415:95] + node _T_592 = and(_T_591, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_593 = bits(_T_592, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_15 of rvclkhdr_109 @[lib.scala 352:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset @@ -30028,9 +30028,9 @@ circuit quasar_wrapper : rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_5 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_5 <= btb_wr_data @[lib.scala 358:16] - node _T_594 = eq(btb_wr_addr, UInt<3>("h06")) @[ifu_bp_ctl.scala 414:95] - node _T_595 = and(_T_594, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_596 = bits(_T_595, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_594 = eq(btb_wr_addr, UInt<3>("h06")) @[ifu_bp_ctl.scala 415:95] + node _T_595 = and(_T_594, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_596 = bits(_T_595, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_16 of rvclkhdr_110 @[lib.scala 352:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset @@ -30039,9 +30039,9 @@ circuit quasar_wrapper : rvclkhdr_16.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_6 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_6 <= btb_wr_data @[lib.scala 358:16] - node _T_597 = eq(btb_wr_addr, UInt<3>("h07")) @[ifu_bp_ctl.scala 414:95] - node _T_598 = and(_T_597, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_599 = bits(_T_598, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_597 = eq(btb_wr_addr, UInt<3>("h07")) @[ifu_bp_ctl.scala 415:95] + node _T_598 = and(_T_597, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_599 = bits(_T_598, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_17 of rvclkhdr_111 @[lib.scala 352:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset @@ -30050,9 +30050,9 @@ circuit quasar_wrapper : rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_7 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_7 <= btb_wr_data @[lib.scala 358:16] - node _T_600 = eq(btb_wr_addr, UInt<4>("h08")) @[ifu_bp_ctl.scala 414:95] - node _T_601 = and(_T_600, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_602 = bits(_T_601, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_600 = eq(btb_wr_addr, UInt<4>("h08")) @[ifu_bp_ctl.scala 415:95] + node _T_601 = and(_T_600, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_602 = bits(_T_601, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_18 of rvclkhdr_112 @[lib.scala 352:23] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset @@ -30061,9 +30061,9 @@ circuit quasar_wrapper : rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_8 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_8 <= btb_wr_data @[lib.scala 358:16] - node _T_603 = eq(btb_wr_addr, UInt<4>("h09")) @[ifu_bp_ctl.scala 414:95] - node _T_604 = and(_T_603, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_605 = bits(_T_604, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_603 = eq(btb_wr_addr, UInt<4>("h09")) @[ifu_bp_ctl.scala 415:95] + node _T_604 = and(_T_603, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_605 = bits(_T_604, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_19 of rvclkhdr_113 @[lib.scala 352:23] rvclkhdr_19.clock <= clock rvclkhdr_19.reset <= reset @@ -30072,9 +30072,9 @@ circuit quasar_wrapper : rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_9 : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_9 <= btb_wr_data @[lib.scala 358:16] - node _T_606 = eq(btb_wr_addr, UInt<4>("h0a")) @[ifu_bp_ctl.scala 414:95] - node _T_607 = and(_T_606, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_608 = bits(_T_607, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_606 = eq(btb_wr_addr, UInt<4>("h0a")) @[ifu_bp_ctl.scala 415:95] + node _T_607 = and(_T_606, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_608 = bits(_T_607, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_20 of rvclkhdr_114 @[lib.scala 352:23] rvclkhdr_20.clock <= clock rvclkhdr_20.reset <= reset @@ -30083,9 +30083,9 @@ circuit quasar_wrapper : rvclkhdr_20.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_10 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_10 <= btb_wr_data @[lib.scala 358:16] - node _T_609 = eq(btb_wr_addr, UInt<4>("h0b")) @[ifu_bp_ctl.scala 414:95] - node _T_610 = and(_T_609, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_611 = bits(_T_610, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_609 = eq(btb_wr_addr, UInt<4>("h0b")) @[ifu_bp_ctl.scala 415:95] + node _T_610 = and(_T_609, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_611 = bits(_T_610, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_21 of rvclkhdr_115 @[lib.scala 352:23] rvclkhdr_21.clock <= clock rvclkhdr_21.reset <= reset @@ -30094,9 +30094,9 @@ circuit quasar_wrapper : rvclkhdr_21.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_11 : UInt, rvclkhdr_21.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_11 <= btb_wr_data @[lib.scala 358:16] - node _T_612 = eq(btb_wr_addr, UInt<4>("h0c")) @[ifu_bp_ctl.scala 414:95] - node _T_613 = and(_T_612, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_614 = bits(_T_613, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_612 = eq(btb_wr_addr, UInt<4>("h0c")) @[ifu_bp_ctl.scala 415:95] + node _T_613 = and(_T_612, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_614 = bits(_T_613, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_22 of rvclkhdr_116 @[lib.scala 352:23] rvclkhdr_22.clock <= clock rvclkhdr_22.reset <= reset @@ -30105,9 +30105,9 @@ circuit quasar_wrapper : rvclkhdr_22.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_12 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_12 <= btb_wr_data @[lib.scala 358:16] - node _T_615 = eq(btb_wr_addr, UInt<4>("h0d")) @[ifu_bp_ctl.scala 414:95] - node _T_616 = and(_T_615, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_617 = bits(_T_616, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_615 = eq(btb_wr_addr, UInt<4>("h0d")) @[ifu_bp_ctl.scala 415:95] + node _T_616 = and(_T_615, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_617 = bits(_T_616, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_23 of rvclkhdr_117 @[lib.scala 352:23] rvclkhdr_23.clock <= clock rvclkhdr_23.reset <= reset @@ -30116,9 +30116,9 @@ circuit quasar_wrapper : rvclkhdr_23.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_13 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_13 <= btb_wr_data @[lib.scala 358:16] - node _T_618 = eq(btb_wr_addr, UInt<4>("h0e")) @[ifu_bp_ctl.scala 414:95] - node _T_619 = and(_T_618, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_620 = bits(_T_619, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_618 = eq(btb_wr_addr, UInt<4>("h0e")) @[ifu_bp_ctl.scala 415:95] + node _T_619 = and(_T_618, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_620 = bits(_T_619, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_24 of rvclkhdr_118 @[lib.scala 352:23] rvclkhdr_24.clock <= clock rvclkhdr_24.reset <= reset @@ -30127,9 +30127,9 @@ circuit quasar_wrapper : rvclkhdr_24.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_14 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_14 <= btb_wr_data @[lib.scala 358:16] - node _T_621 = eq(btb_wr_addr, UInt<4>("h0f")) @[ifu_bp_ctl.scala 414:95] - node _T_622 = and(_T_621, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_623 = bits(_T_622, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_621 = eq(btb_wr_addr, UInt<4>("h0f")) @[ifu_bp_ctl.scala 415:95] + node _T_622 = and(_T_621, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_623 = bits(_T_622, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_25 of rvclkhdr_119 @[lib.scala 352:23] rvclkhdr_25.clock <= clock rvclkhdr_25.reset <= reset @@ -30138,9 +30138,9 @@ circuit quasar_wrapper : rvclkhdr_25.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_15 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_15 <= btb_wr_data @[lib.scala 358:16] - node _T_624 = eq(btb_wr_addr, UInt<5>("h010")) @[ifu_bp_ctl.scala 414:95] - node _T_625 = and(_T_624, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_626 = bits(_T_625, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_624 = eq(btb_wr_addr, UInt<5>("h010")) @[ifu_bp_ctl.scala 415:95] + node _T_625 = and(_T_624, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_626 = bits(_T_625, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_26 of rvclkhdr_120 @[lib.scala 352:23] rvclkhdr_26.clock <= clock rvclkhdr_26.reset <= reset @@ -30149,9 +30149,9 @@ circuit quasar_wrapper : rvclkhdr_26.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_16 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_16 <= btb_wr_data @[lib.scala 358:16] - node _T_627 = eq(btb_wr_addr, UInt<5>("h011")) @[ifu_bp_ctl.scala 414:95] - node _T_628 = and(_T_627, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_629 = bits(_T_628, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_627 = eq(btb_wr_addr, UInt<5>("h011")) @[ifu_bp_ctl.scala 415:95] + node _T_628 = and(_T_627, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_629 = bits(_T_628, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_27 of rvclkhdr_121 @[lib.scala 352:23] rvclkhdr_27.clock <= clock rvclkhdr_27.reset <= reset @@ -30160,9 +30160,9 @@ circuit quasar_wrapper : rvclkhdr_27.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_17 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_17 <= btb_wr_data @[lib.scala 358:16] - node _T_630 = eq(btb_wr_addr, UInt<5>("h012")) @[ifu_bp_ctl.scala 414:95] - node _T_631 = and(_T_630, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_632 = bits(_T_631, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_630 = eq(btb_wr_addr, UInt<5>("h012")) @[ifu_bp_ctl.scala 415:95] + node _T_631 = and(_T_630, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_632 = bits(_T_631, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_28 of rvclkhdr_122 @[lib.scala 352:23] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset @@ -30171,9 +30171,9 @@ circuit quasar_wrapper : rvclkhdr_28.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_18 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_18 <= btb_wr_data @[lib.scala 358:16] - node _T_633 = eq(btb_wr_addr, UInt<5>("h013")) @[ifu_bp_ctl.scala 414:95] - node _T_634 = and(_T_633, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_635 = bits(_T_634, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_633 = eq(btb_wr_addr, UInt<5>("h013")) @[ifu_bp_ctl.scala 415:95] + node _T_634 = and(_T_633, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_635 = bits(_T_634, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_29 of rvclkhdr_123 @[lib.scala 352:23] rvclkhdr_29.clock <= clock rvclkhdr_29.reset <= reset @@ -30182,9 +30182,9 @@ circuit quasar_wrapper : rvclkhdr_29.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_19 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_19 <= btb_wr_data @[lib.scala 358:16] - node _T_636 = eq(btb_wr_addr, UInt<5>("h014")) @[ifu_bp_ctl.scala 414:95] - node _T_637 = and(_T_636, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_638 = bits(_T_637, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_636 = eq(btb_wr_addr, UInt<5>("h014")) @[ifu_bp_ctl.scala 415:95] + node _T_637 = and(_T_636, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_638 = bits(_T_637, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_30 of rvclkhdr_124 @[lib.scala 352:23] rvclkhdr_30.clock <= clock rvclkhdr_30.reset <= reset @@ -30193,9 +30193,9 @@ circuit quasar_wrapper : rvclkhdr_30.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_20 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_20 <= btb_wr_data @[lib.scala 358:16] - node _T_639 = eq(btb_wr_addr, UInt<5>("h015")) @[ifu_bp_ctl.scala 414:95] - node _T_640 = and(_T_639, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_641 = bits(_T_640, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_639 = eq(btb_wr_addr, UInt<5>("h015")) @[ifu_bp_ctl.scala 415:95] + node _T_640 = and(_T_639, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_641 = bits(_T_640, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_31 of rvclkhdr_125 @[lib.scala 352:23] rvclkhdr_31.clock <= clock rvclkhdr_31.reset <= reset @@ -30204,9 +30204,9 @@ circuit quasar_wrapper : rvclkhdr_31.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_21 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_21 <= btb_wr_data @[lib.scala 358:16] - node _T_642 = eq(btb_wr_addr, UInt<5>("h016")) @[ifu_bp_ctl.scala 414:95] - node _T_643 = and(_T_642, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_644 = bits(_T_643, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_642 = eq(btb_wr_addr, UInt<5>("h016")) @[ifu_bp_ctl.scala 415:95] + node _T_643 = and(_T_642, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_644 = bits(_T_643, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_32 of rvclkhdr_126 @[lib.scala 352:23] rvclkhdr_32.clock <= clock rvclkhdr_32.reset <= reset @@ -30215,9 +30215,9 @@ circuit quasar_wrapper : rvclkhdr_32.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_22 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_22 <= btb_wr_data @[lib.scala 358:16] - node _T_645 = eq(btb_wr_addr, UInt<5>("h017")) @[ifu_bp_ctl.scala 414:95] - node _T_646 = and(_T_645, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_647 = bits(_T_646, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_645 = eq(btb_wr_addr, UInt<5>("h017")) @[ifu_bp_ctl.scala 415:95] + node _T_646 = and(_T_645, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_647 = bits(_T_646, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_33 of rvclkhdr_127 @[lib.scala 352:23] rvclkhdr_33.clock <= clock rvclkhdr_33.reset <= reset @@ -30226,9 +30226,9 @@ circuit quasar_wrapper : rvclkhdr_33.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_23 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_23 <= btb_wr_data @[lib.scala 358:16] - node _T_648 = eq(btb_wr_addr, UInt<5>("h018")) @[ifu_bp_ctl.scala 414:95] - node _T_649 = and(_T_648, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_650 = bits(_T_649, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_648 = eq(btb_wr_addr, UInt<5>("h018")) @[ifu_bp_ctl.scala 415:95] + node _T_649 = and(_T_648, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_650 = bits(_T_649, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_34 of rvclkhdr_128 @[lib.scala 352:23] rvclkhdr_34.clock <= clock rvclkhdr_34.reset <= reset @@ -30237,9 +30237,9 @@ circuit quasar_wrapper : rvclkhdr_34.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_24 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_24 <= btb_wr_data @[lib.scala 358:16] - node _T_651 = eq(btb_wr_addr, UInt<5>("h019")) @[ifu_bp_ctl.scala 414:95] - node _T_652 = and(_T_651, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_653 = bits(_T_652, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_651 = eq(btb_wr_addr, UInt<5>("h019")) @[ifu_bp_ctl.scala 415:95] + node _T_652 = and(_T_651, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_653 = bits(_T_652, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_35 of rvclkhdr_129 @[lib.scala 352:23] rvclkhdr_35.clock <= clock rvclkhdr_35.reset <= reset @@ -30248,9 +30248,9 @@ circuit quasar_wrapper : rvclkhdr_35.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_25 : UInt, rvclkhdr_35.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_25 <= btb_wr_data @[lib.scala 358:16] - node _T_654 = eq(btb_wr_addr, UInt<5>("h01a")) @[ifu_bp_ctl.scala 414:95] - node _T_655 = and(_T_654, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_656 = bits(_T_655, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_654 = eq(btb_wr_addr, UInt<5>("h01a")) @[ifu_bp_ctl.scala 415:95] + node _T_655 = and(_T_654, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_656 = bits(_T_655, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_36 of rvclkhdr_130 @[lib.scala 352:23] rvclkhdr_36.clock <= clock rvclkhdr_36.reset <= reset @@ -30259,9 +30259,9 @@ circuit quasar_wrapper : rvclkhdr_36.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_26 : UInt, rvclkhdr_36.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_26 <= btb_wr_data @[lib.scala 358:16] - node _T_657 = eq(btb_wr_addr, UInt<5>("h01b")) @[ifu_bp_ctl.scala 414:95] - node _T_658 = and(_T_657, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_659 = bits(_T_658, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_657 = eq(btb_wr_addr, UInt<5>("h01b")) @[ifu_bp_ctl.scala 415:95] + node _T_658 = and(_T_657, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_659 = bits(_T_658, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_37 of rvclkhdr_131 @[lib.scala 352:23] rvclkhdr_37.clock <= clock rvclkhdr_37.reset <= reset @@ -30270,9 +30270,9 @@ circuit quasar_wrapper : rvclkhdr_37.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_27 : UInt, rvclkhdr_37.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_27 <= btb_wr_data @[lib.scala 358:16] - node _T_660 = eq(btb_wr_addr, UInt<5>("h01c")) @[ifu_bp_ctl.scala 414:95] - node _T_661 = and(_T_660, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_662 = bits(_T_661, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_660 = eq(btb_wr_addr, UInt<5>("h01c")) @[ifu_bp_ctl.scala 415:95] + node _T_661 = and(_T_660, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_662 = bits(_T_661, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_38 of rvclkhdr_132 @[lib.scala 352:23] rvclkhdr_38.clock <= clock rvclkhdr_38.reset <= reset @@ -30281,9 +30281,9 @@ circuit quasar_wrapper : rvclkhdr_38.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_28 : UInt, rvclkhdr_38.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_28 <= btb_wr_data @[lib.scala 358:16] - node _T_663 = eq(btb_wr_addr, UInt<5>("h01d")) @[ifu_bp_ctl.scala 414:95] - node _T_664 = and(_T_663, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_665 = bits(_T_664, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_663 = eq(btb_wr_addr, UInt<5>("h01d")) @[ifu_bp_ctl.scala 415:95] + node _T_664 = and(_T_663, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_665 = bits(_T_664, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_39 of rvclkhdr_133 @[lib.scala 352:23] rvclkhdr_39.clock <= clock rvclkhdr_39.reset <= reset @@ -30292,9 +30292,9 @@ circuit quasar_wrapper : rvclkhdr_39.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_29 : UInt, rvclkhdr_39.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_29 <= btb_wr_data @[lib.scala 358:16] - node _T_666 = eq(btb_wr_addr, UInt<5>("h01e")) @[ifu_bp_ctl.scala 414:95] - node _T_667 = and(_T_666, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_668 = bits(_T_667, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_666 = eq(btb_wr_addr, UInt<5>("h01e")) @[ifu_bp_ctl.scala 415:95] + node _T_667 = and(_T_666, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_668 = bits(_T_667, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_40 of rvclkhdr_134 @[lib.scala 352:23] rvclkhdr_40.clock <= clock rvclkhdr_40.reset <= reset @@ -30303,9 +30303,9 @@ circuit quasar_wrapper : rvclkhdr_40.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_30 : UInt, rvclkhdr_40.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_30 <= btb_wr_data @[lib.scala 358:16] - node _T_669 = eq(btb_wr_addr, UInt<5>("h01f")) @[ifu_bp_ctl.scala 414:95] - node _T_670 = and(_T_669, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_671 = bits(_T_670, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_669 = eq(btb_wr_addr, UInt<5>("h01f")) @[ifu_bp_ctl.scala 415:95] + node _T_670 = and(_T_669, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_671 = bits(_T_670, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_41 of rvclkhdr_135 @[lib.scala 352:23] rvclkhdr_41.clock <= clock rvclkhdr_41.reset <= reset @@ -30314,9 +30314,9 @@ circuit quasar_wrapper : rvclkhdr_41.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_31 : UInt, rvclkhdr_41.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_31 <= btb_wr_data @[lib.scala 358:16] - node _T_672 = eq(btb_wr_addr, UInt<6>("h020")) @[ifu_bp_ctl.scala 414:95] - node _T_673 = and(_T_672, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_674 = bits(_T_673, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_672 = eq(btb_wr_addr, UInt<6>("h020")) @[ifu_bp_ctl.scala 415:95] + node _T_673 = and(_T_672, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_674 = bits(_T_673, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_42 of rvclkhdr_136 @[lib.scala 352:23] rvclkhdr_42.clock <= clock rvclkhdr_42.reset <= reset @@ -30325,9 +30325,9 @@ circuit quasar_wrapper : rvclkhdr_42.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_32 : UInt, rvclkhdr_42.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_32 <= btb_wr_data @[lib.scala 358:16] - node _T_675 = eq(btb_wr_addr, UInt<6>("h021")) @[ifu_bp_ctl.scala 414:95] - node _T_676 = and(_T_675, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_677 = bits(_T_676, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_675 = eq(btb_wr_addr, UInt<6>("h021")) @[ifu_bp_ctl.scala 415:95] + node _T_676 = and(_T_675, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_677 = bits(_T_676, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_43 of rvclkhdr_137 @[lib.scala 352:23] rvclkhdr_43.clock <= clock rvclkhdr_43.reset <= reset @@ -30336,9 +30336,9 @@ circuit quasar_wrapper : rvclkhdr_43.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_33 : UInt, rvclkhdr_43.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_33 <= btb_wr_data @[lib.scala 358:16] - node _T_678 = eq(btb_wr_addr, UInt<6>("h022")) @[ifu_bp_ctl.scala 414:95] - node _T_679 = and(_T_678, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_680 = bits(_T_679, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_678 = eq(btb_wr_addr, UInt<6>("h022")) @[ifu_bp_ctl.scala 415:95] + node _T_679 = and(_T_678, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_680 = bits(_T_679, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_44 of rvclkhdr_138 @[lib.scala 352:23] rvclkhdr_44.clock <= clock rvclkhdr_44.reset <= reset @@ -30347,9 +30347,9 @@ circuit quasar_wrapper : rvclkhdr_44.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_34 : UInt, rvclkhdr_44.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_34 <= btb_wr_data @[lib.scala 358:16] - node _T_681 = eq(btb_wr_addr, UInt<6>("h023")) @[ifu_bp_ctl.scala 414:95] - node _T_682 = and(_T_681, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_683 = bits(_T_682, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_681 = eq(btb_wr_addr, UInt<6>("h023")) @[ifu_bp_ctl.scala 415:95] + node _T_682 = and(_T_681, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_683 = bits(_T_682, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_45 of rvclkhdr_139 @[lib.scala 352:23] rvclkhdr_45.clock <= clock rvclkhdr_45.reset <= reset @@ -30358,9 +30358,9 @@ circuit quasar_wrapper : rvclkhdr_45.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_35 : UInt, rvclkhdr_45.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_35 <= btb_wr_data @[lib.scala 358:16] - node _T_684 = eq(btb_wr_addr, UInt<6>("h024")) @[ifu_bp_ctl.scala 414:95] - node _T_685 = and(_T_684, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_686 = bits(_T_685, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_684 = eq(btb_wr_addr, UInt<6>("h024")) @[ifu_bp_ctl.scala 415:95] + node _T_685 = and(_T_684, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_686 = bits(_T_685, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_46 of rvclkhdr_140 @[lib.scala 352:23] rvclkhdr_46.clock <= clock rvclkhdr_46.reset <= reset @@ -30369,9 +30369,9 @@ circuit quasar_wrapper : rvclkhdr_46.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_36 : UInt, rvclkhdr_46.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_36 <= btb_wr_data @[lib.scala 358:16] - node _T_687 = eq(btb_wr_addr, UInt<6>("h025")) @[ifu_bp_ctl.scala 414:95] - node _T_688 = and(_T_687, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_689 = bits(_T_688, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_687 = eq(btb_wr_addr, UInt<6>("h025")) @[ifu_bp_ctl.scala 415:95] + node _T_688 = and(_T_687, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_689 = bits(_T_688, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_47 of rvclkhdr_141 @[lib.scala 352:23] rvclkhdr_47.clock <= clock rvclkhdr_47.reset <= reset @@ -30380,9 +30380,9 @@ circuit quasar_wrapper : rvclkhdr_47.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_37 : UInt, rvclkhdr_47.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_37 <= btb_wr_data @[lib.scala 358:16] - node _T_690 = eq(btb_wr_addr, UInt<6>("h026")) @[ifu_bp_ctl.scala 414:95] - node _T_691 = and(_T_690, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_692 = bits(_T_691, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_690 = eq(btb_wr_addr, UInt<6>("h026")) @[ifu_bp_ctl.scala 415:95] + node _T_691 = and(_T_690, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_692 = bits(_T_691, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_48 of rvclkhdr_142 @[lib.scala 352:23] rvclkhdr_48.clock <= clock rvclkhdr_48.reset <= reset @@ -30391,9 +30391,9 @@ circuit quasar_wrapper : rvclkhdr_48.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_38 : UInt, rvclkhdr_48.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_38 <= btb_wr_data @[lib.scala 358:16] - node _T_693 = eq(btb_wr_addr, UInt<6>("h027")) @[ifu_bp_ctl.scala 414:95] - node _T_694 = and(_T_693, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_695 = bits(_T_694, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_693 = eq(btb_wr_addr, UInt<6>("h027")) @[ifu_bp_ctl.scala 415:95] + node _T_694 = and(_T_693, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_695 = bits(_T_694, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_49 of rvclkhdr_143 @[lib.scala 352:23] rvclkhdr_49.clock <= clock rvclkhdr_49.reset <= reset @@ -30402,9 +30402,9 @@ circuit quasar_wrapper : rvclkhdr_49.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_39 : UInt, rvclkhdr_49.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_39 <= btb_wr_data @[lib.scala 358:16] - node _T_696 = eq(btb_wr_addr, UInt<6>("h028")) @[ifu_bp_ctl.scala 414:95] - node _T_697 = and(_T_696, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_698 = bits(_T_697, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_696 = eq(btb_wr_addr, UInt<6>("h028")) @[ifu_bp_ctl.scala 415:95] + node _T_697 = and(_T_696, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_698 = bits(_T_697, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_50 of rvclkhdr_144 @[lib.scala 352:23] rvclkhdr_50.clock <= clock rvclkhdr_50.reset <= reset @@ -30413,9 +30413,9 @@ circuit quasar_wrapper : rvclkhdr_50.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_40 : UInt, rvclkhdr_50.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_40 <= btb_wr_data @[lib.scala 358:16] - node _T_699 = eq(btb_wr_addr, UInt<6>("h029")) @[ifu_bp_ctl.scala 414:95] - node _T_700 = and(_T_699, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_701 = bits(_T_700, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_699 = eq(btb_wr_addr, UInt<6>("h029")) @[ifu_bp_ctl.scala 415:95] + node _T_700 = and(_T_699, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_701 = bits(_T_700, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_51 of rvclkhdr_145 @[lib.scala 352:23] rvclkhdr_51.clock <= clock rvclkhdr_51.reset <= reset @@ -30424,9 +30424,9 @@ circuit quasar_wrapper : rvclkhdr_51.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_41 : UInt, rvclkhdr_51.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_41 <= btb_wr_data @[lib.scala 358:16] - node _T_702 = eq(btb_wr_addr, UInt<6>("h02a")) @[ifu_bp_ctl.scala 414:95] - node _T_703 = and(_T_702, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_704 = bits(_T_703, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_702 = eq(btb_wr_addr, UInt<6>("h02a")) @[ifu_bp_ctl.scala 415:95] + node _T_703 = and(_T_702, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_704 = bits(_T_703, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_52 of rvclkhdr_146 @[lib.scala 352:23] rvclkhdr_52.clock <= clock rvclkhdr_52.reset <= reset @@ -30435,9 +30435,9 @@ circuit quasar_wrapper : rvclkhdr_52.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_42 : UInt, rvclkhdr_52.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_42 <= btb_wr_data @[lib.scala 358:16] - node _T_705 = eq(btb_wr_addr, UInt<6>("h02b")) @[ifu_bp_ctl.scala 414:95] - node _T_706 = and(_T_705, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_707 = bits(_T_706, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_705 = eq(btb_wr_addr, UInt<6>("h02b")) @[ifu_bp_ctl.scala 415:95] + node _T_706 = and(_T_705, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_707 = bits(_T_706, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_53 of rvclkhdr_147 @[lib.scala 352:23] rvclkhdr_53.clock <= clock rvclkhdr_53.reset <= reset @@ -30446,9 +30446,9 @@ circuit quasar_wrapper : rvclkhdr_53.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_43 : UInt, rvclkhdr_53.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_43 <= btb_wr_data @[lib.scala 358:16] - node _T_708 = eq(btb_wr_addr, UInt<6>("h02c")) @[ifu_bp_ctl.scala 414:95] - node _T_709 = and(_T_708, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_710 = bits(_T_709, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_708 = eq(btb_wr_addr, UInt<6>("h02c")) @[ifu_bp_ctl.scala 415:95] + node _T_709 = and(_T_708, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_710 = bits(_T_709, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_54 of rvclkhdr_148 @[lib.scala 352:23] rvclkhdr_54.clock <= clock rvclkhdr_54.reset <= reset @@ -30457,9 +30457,9 @@ circuit quasar_wrapper : rvclkhdr_54.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_44 : UInt, rvclkhdr_54.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_44 <= btb_wr_data @[lib.scala 358:16] - node _T_711 = eq(btb_wr_addr, UInt<6>("h02d")) @[ifu_bp_ctl.scala 414:95] - node _T_712 = and(_T_711, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_713 = bits(_T_712, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_711 = eq(btb_wr_addr, UInt<6>("h02d")) @[ifu_bp_ctl.scala 415:95] + node _T_712 = and(_T_711, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_713 = bits(_T_712, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_55 of rvclkhdr_149 @[lib.scala 352:23] rvclkhdr_55.clock <= clock rvclkhdr_55.reset <= reset @@ -30468,9 +30468,9 @@ circuit quasar_wrapper : rvclkhdr_55.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_45 : UInt, rvclkhdr_55.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_45 <= btb_wr_data @[lib.scala 358:16] - node _T_714 = eq(btb_wr_addr, UInt<6>("h02e")) @[ifu_bp_ctl.scala 414:95] - node _T_715 = and(_T_714, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_716 = bits(_T_715, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_714 = eq(btb_wr_addr, UInt<6>("h02e")) @[ifu_bp_ctl.scala 415:95] + node _T_715 = and(_T_714, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_716 = bits(_T_715, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_56 of rvclkhdr_150 @[lib.scala 352:23] rvclkhdr_56.clock <= clock rvclkhdr_56.reset <= reset @@ -30479,9 +30479,9 @@ circuit quasar_wrapper : rvclkhdr_56.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_46 : UInt, rvclkhdr_56.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_46 <= btb_wr_data @[lib.scala 358:16] - node _T_717 = eq(btb_wr_addr, UInt<6>("h02f")) @[ifu_bp_ctl.scala 414:95] - node _T_718 = and(_T_717, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_719 = bits(_T_718, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_717 = eq(btb_wr_addr, UInt<6>("h02f")) @[ifu_bp_ctl.scala 415:95] + node _T_718 = and(_T_717, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_719 = bits(_T_718, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_57 of rvclkhdr_151 @[lib.scala 352:23] rvclkhdr_57.clock <= clock rvclkhdr_57.reset <= reset @@ -30490,9 +30490,9 @@ circuit quasar_wrapper : rvclkhdr_57.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_47 : UInt, rvclkhdr_57.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_47 <= btb_wr_data @[lib.scala 358:16] - node _T_720 = eq(btb_wr_addr, UInt<6>("h030")) @[ifu_bp_ctl.scala 414:95] - node _T_721 = and(_T_720, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_722 = bits(_T_721, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_720 = eq(btb_wr_addr, UInt<6>("h030")) @[ifu_bp_ctl.scala 415:95] + node _T_721 = and(_T_720, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_722 = bits(_T_721, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_58 of rvclkhdr_152 @[lib.scala 352:23] rvclkhdr_58.clock <= clock rvclkhdr_58.reset <= reset @@ -30501,9 +30501,9 @@ circuit quasar_wrapper : rvclkhdr_58.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_48 : UInt, rvclkhdr_58.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_48 <= btb_wr_data @[lib.scala 358:16] - node _T_723 = eq(btb_wr_addr, UInt<6>("h031")) @[ifu_bp_ctl.scala 414:95] - node _T_724 = and(_T_723, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_725 = bits(_T_724, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_723 = eq(btb_wr_addr, UInt<6>("h031")) @[ifu_bp_ctl.scala 415:95] + node _T_724 = and(_T_723, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_725 = bits(_T_724, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_59 of rvclkhdr_153 @[lib.scala 352:23] rvclkhdr_59.clock <= clock rvclkhdr_59.reset <= reset @@ -30512,9 +30512,9 @@ circuit quasar_wrapper : rvclkhdr_59.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_49 : UInt, rvclkhdr_59.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_49 <= btb_wr_data @[lib.scala 358:16] - node _T_726 = eq(btb_wr_addr, UInt<6>("h032")) @[ifu_bp_ctl.scala 414:95] - node _T_727 = and(_T_726, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_728 = bits(_T_727, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_726 = eq(btb_wr_addr, UInt<6>("h032")) @[ifu_bp_ctl.scala 415:95] + node _T_727 = and(_T_726, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_728 = bits(_T_727, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_60 of rvclkhdr_154 @[lib.scala 352:23] rvclkhdr_60.clock <= clock rvclkhdr_60.reset <= reset @@ -30523,9 +30523,9 @@ circuit quasar_wrapper : rvclkhdr_60.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_50 : UInt, rvclkhdr_60.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_50 <= btb_wr_data @[lib.scala 358:16] - node _T_729 = eq(btb_wr_addr, UInt<6>("h033")) @[ifu_bp_ctl.scala 414:95] - node _T_730 = and(_T_729, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_731 = bits(_T_730, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_729 = eq(btb_wr_addr, UInt<6>("h033")) @[ifu_bp_ctl.scala 415:95] + node _T_730 = and(_T_729, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_731 = bits(_T_730, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_61 of rvclkhdr_155 @[lib.scala 352:23] rvclkhdr_61.clock <= clock rvclkhdr_61.reset <= reset @@ -30534,9 +30534,9 @@ circuit quasar_wrapper : rvclkhdr_61.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_51 : UInt, rvclkhdr_61.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_51 <= btb_wr_data @[lib.scala 358:16] - node _T_732 = eq(btb_wr_addr, UInt<6>("h034")) @[ifu_bp_ctl.scala 414:95] - node _T_733 = and(_T_732, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_734 = bits(_T_733, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_732 = eq(btb_wr_addr, UInt<6>("h034")) @[ifu_bp_ctl.scala 415:95] + node _T_733 = and(_T_732, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_734 = bits(_T_733, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_62 of rvclkhdr_156 @[lib.scala 352:23] rvclkhdr_62.clock <= clock rvclkhdr_62.reset <= reset @@ -30545,9 +30545,9 @@ circuit quasar_wrapper : rvclkhdr_62.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_52 : UInt, rvclkhdr_62.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_52 <= btb_wr_data @[lib.scala 358:16] - node _T_735 = eq(btb_wr_addr, UInt<6>("h035")) @[ifu_bp_ctl.scala 414:95] - node _T_736 = and(_T_735, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_737 = bits(_T_736, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_735 = eq(btb_wr_addr, UInt<6>("h035")) @[ifu_bp_ctl.scala 415:95] + node _T_736 = and(_T_735, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_737 = bits(_T_736, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_63 of rvclkhdr_157 @[lib.scala 352:23] rvclkhdr_63.clock <= clock rvclkhdr_63.reset <= reset @@ -30556,9 +30556,9 @@ circuit quasar_wrapper : rvclkhdr_63.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_53 : UInt, rvclkhdr_63.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_53 <= btb_wr_data @[lib.scala 358:16] - node _T_738 = eq(btb_wr_addr, UInt<6>("h036")) @[ifu_bp_ctl.scala 414:95] - node _T_739 = and(_T_738, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_740 = bits(_T_739, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_738 = eq(btb_wr_addr, UInt<6>("h036")) @[ifu_bp_ctl.scala 415:95] + node _T_739 = and(_T_738, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_740 = bits(_T_739, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_64 of rvclkhdr_158 @[lib.scala 352:23] rvclkhdr_64.clock <= clock rvclkhdr_64.reset <= reset @@ -30567,9 +30567,9 @@ circuit quasar_wrapper : rvclkhdr_64.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_54 : UInt, rvclkhdr_64.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_54 <= btb_wr_data @[lib.scala 358:16] - node _T_741 = eq(btb_wr_addr, UInt<6>("h037")) @[ifu_bp_ctl.scala 414:95] - node _T_742 = and(_T_741, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_743 = bits(_T_742, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_741 = eq(btb_wr_addr, UInt<6>("h037")) @[ifu_bp_ctl.scala 415:95] + node _T_742 = and(_T_741, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_743 = bits(_T_742, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_65 of rvclkhdr_159 @[lib.scala 352:23] rvclkhdr_65.clock <= clock rvclkhdr_65.reset <= reset @@ -30578,9 +30578,9 @@ circuit quasar_wrapper : rvclkhdr_65.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_55 : UInt, rvclkhdr_65.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_55 <= btb_wr_data @[lib.scala 358:16] - node _T_744 = eq(btb_wr_addr, UInt<6>("h038")) @[ifu_bp_ctl.scala 414:95] - node _T_745 = and(_T_744, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_746 = bits(_T_745, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_744 = eq(btb_wr_addr, UInt<6>("h038")) @[ifu_bp_ctl.scala 415:95] + node _T_745 = and(_T_744, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_746 = bits(_T_745, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_66 of rvclkhdr_160 @[lib.scala 352:23] rvclkhdr_66.clock <= clock rvclkhdr_66.reset <= reset @@ -30589,9 +30589,9 @@ circuit quasar_wrapper : rvclkhdr_66.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_56 : UInt, rvclkhdr_66.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_56 <= btb_wr_data @[lib.scala 358:16] - node _T_747 = eq(btb_wr_addr, UInt<6>("h039")) @[ifu_bp_ctl.scala 414:95] - node _T_748 = and(_T_747, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_749 = bits(_T_748, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_747 = eq(btb_wr_addr, UInt<6>("h039")) @[ifu_bp_ctl.scala 415:95] + node _T_748 = and(_T_747, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_749 = bits(_T_748, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_67 of rvclkhdr_161 @[lib.scala 352:23] rvclkhdr_67.clock <= clock rvclkhdr_67.reset <= reset @@ -30600,9 +30600,9 @@ circuit quasar_wrapper : rvclkhdr_67.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_57 : UInt, rvclkhdr_67.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_57 <= btb_wr_data @[lib.scala 358:16] - node _T_750 = eq(btb_wr_addr, UInt<6>("h03a")) @[ifu_bp_ctl.scala 414:95] - node _T_751 = and(_T_750, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_752 = bits(_T_751, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_750 = eq(btb_wr_addr, UInt<6>("h03a")) @[ifu_bp_ctl.scala 415:95] + node _T_751 = and(_T_750, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_752 = bits(_T_751, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_68 of rvclkhdr_162 @[lib.scala 352:23] rvclkhdr_68.clock <= clock rvclkhdr_68.reset <= reset @@ -30611,9 +30611,9 @@ circuit quasar_wrapper : rvclkhdr_68.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_58 : UInt, rvclkhdr_68.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_58 <= btb_wr_data @[lib.scala 358:16] - node _T_753 = eq(btb_wr_addr, UInt<6>("h03b")) @[ifu_bp_ctl.scala 414:95] - node _T_754 = and(_T_753, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_755 = bits(_T_754, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_753 = eq(btb_wr_addr, UInt<6>("h03b")) @[ifu_bp_ctl.scala 415:95] + node _T_754 = and(_T_753, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_755 = bits(_T_754, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_69 of rvclkhdr_163 @[lib.scala 352:23] rvclkhdr_69.clock <= clock rvclkhdr_69.reset <= reset @@ -30622,9 +30622,9 @@ circuit quasar_wrapper : rvclkhdr_69.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_59 : UInt, rvclkhdr_69.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_59 <= btb_wr_data @[lib.scala 358:16] - node _T_756 = eq(btb_wr_addr, UInt<6>("h03c")) @[ifu_bp_ctl.scala 414:95] - node _T_757 = and(_T_756, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_758 = bits(_T_757, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_756 = eq(btb_wr_addr, UInt<6>("h03c")) @[ifu_bp_ctl.scala 415:95] + node _T_757 = and(_T_756, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_758 = bits(_T_757, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_70 of rvclkhdr_164 @[lib.scala 352:23] rvclkhdr_70.clock <= clock rvclkhdr_70.reset <= reset @@ -30633,9 +30633,9 @@ circuit quasar_wrapper : rvclkhdr_70.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_60 : UInt, rvclkhdr_70.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_60 <= btb_wr_data @[lib.scala 358:16] - node _T_759 = eq(btb_wr_addr, UInt<6>("h03d")) @[ifu_bp_ctl.scala 414:95] - node _T_760 = and(_T_759, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_761 = bits(_T_760, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_759 = eq(btb_wr_addr, UInt<6>("h03d")) @[ifu_bp_ctl.scala 415:95] + node _T_760 = and(_T_759, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_761 = bits(_T_760, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_71 of rvclkhdr_165 @[lib.scala 352:23] rvclkhdr_71.clock <= clock rvclkhdr_71.reset <= reset @@ -30644,9 +30644,9 @@ circuit quasar_wrapper : rvclkhdr_71.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_61 : UInt, rvclkhdr_71.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_61 <= btb_wr_data @[lib.scala 358:16] - node _T_762 = eq(btb_wr_addr, UInt<6>("h03e")) @[ifu_bp_ctl.scala 414:95] - node _T_763 = and(_T_762, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_764 = bits(_T_763, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_762 = eq(btb_wr_addr, UInt<6>("h03e")) @[ifu_bp_ctl.scala 415:95] + node _T_763 = and(_T_762, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_764 = bits(_T_763, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_72 of rvclkhdr_166 @[lib.scala 352:23] rvclkhdr_72.clock <= clock rvclkhdr_72.reset <= reset @@ -30655,9 +30655,9 @@ circuit quasar_wrapper : rvclkhdr_72.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_62 : UInt, rvclkhdr_72.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_62 <= btb_wr_data @[lib.scala 358:16] - node _T_765 = eq(btb_wr_addr, UInt<6>("h03f")) @[ifu_bp_ctl.scala 414:95] - node _T_766 = and(_T_765, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_767 = bits(_T_766, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_765 = eq(btb_wr_addr, UInt<6>("h03f")) @[ifu_bp_ctl.scala 415:95] + node _T_766 = and(_T_765, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_767 = bits(_T_766, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_73 of rvclkhdr_167 @[lib.scala 352:23] rvclkhdr_73.clock <= clock rvclkhdr_73.reset <= reset @@ -30666,9 +30666,9 @@ circuit quasar_wrapper : rvclkhdr_73.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_63 : UInt, rvclkhdr_73.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_63 <= btb_wr_data @[lib.scala 358:16] - node _T_768 = eq(btb_wr_addr, UInt<7>("h040")) @[ifu_bp_ctl.scala 414:95] - node _T_769 = and(_T_768, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_770 = bits(_T_769, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_768 = eq(btb_wr_addr, UInt<7>("h040")) @[ifu_bp_ctl.scala 415:95] + node _T_769 = and(_T_768, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_770 = bits(_T_769, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_74 of rvclkhdr_168 @[lib.scala 352:23] rvclkhdr_74.clock <= clock rvclkhdr_74.reset <= reset @@ -30677,9 +30677,9 @@ circuit quasar_wrapper : rvclkhdr_74.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_64 : UInt, rvclkhdr_74.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_64 <= btb_wr_data @[lib.scala 358:16] - node _T_771 = eq(btb_wr_addr, UInt<7>("h041")) @[ifu_bp_ctl.scala 414:95] - node _T_772 = and(_T_771, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_773 = bits(_T_772, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_771 = eq(btb_wr_addr, UInt<7>("h041")) @[ifu_bp_ctl.scala 415:95] + node _T_772 = and(_T_771, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_773 = bits(_T_772, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_75 of rvclkhdr_169 @[lib.scala 352:23] rvclkhdr_75.clock <= clock rvclkhdr_75.reset <= reset @@ -30688,9 +30688,9 @@ circuit quasar_wrapper : rvclkhdr_75.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_65 : UInt, rvclkhdr_75.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_65 <= btb_wr_data @[lib.scala 358:16] - node _T_774 = eq(btb_wr_addr, UInt<7>("h042")) @[ifu_bp_ctl.scala 414:95] - node _T_775 = and(_T_774, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_776 = bits(_T_775, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_774 = eq(btb_wr_addr, UInt<7>("h042")) @[ifu_bp_ctl.scala 415:95] + node _T_775 = and(_T_774, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_776 = bits(_T_775, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_76 of rvclkhdr_170 @[lib.scala 352:23] rvclkhdr_76.clock <= clock rvclkhdr_76.reset <= reset @@ -30699,9 +30699,9 @@ circuit quasar_wrapper : rvclkhdr_76.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_66 : UInt, rvclkhdr_76.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_66 <= btb_wr_data @[lib.scala 358:16] - node _T_777 = eq(btb_wr_addr, UInt<7>("h043")) @[ifu_bp_ctl.scala 414:95] - node _T_778 = and(_T_777, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_779 = bits(_T_778, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_777 = eq(btb_wr_addr, UInt<7>("h043")) @[ifu_bp_ctl.scala 415:95] + node _T_778 = and(_T_777, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_779 = bits(_T_778, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_77 of rvclkhdr_171 @[lib.scala 352:23] rvclkhdr_77.clock <= clock rvclkhdr_77.reset <= reset @@ -30710,9 +30710,9 @@ circuit quasar_wrapper : rvclkhdr_77.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_67 : UInt, rvclkhdr_77.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_67 <= btb_wr_data @[lib.scala 358:16] - node _T_780 = eq(btb_wr_addr, UInt<7>("h044")) @[ifu_bp_ctl.scala 414:95] - node _T_781 = and(_T_780, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_782 = bits(_T_781, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_780 = eq(btb_wr_addr, UInt<7>("h044")) @[ifu_bp_ctl.scala 415:95] + node _T_781 = and(_T_780, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_782 = bits(_T_781, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_78 of rvclkhdr_172 @[lib.scala 352:23] rvclkhdr_78.clock <= clock rvclkhdr_78.reset <= reset @@ -30721,9 +30721,9 @@ circuit quasar_wrapper : rvclkhdr_78.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_68 : UInt, rvclkhdr_78.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_68 <= btb_wr_data @[lib.scala 358:16] - node _T_783 = eq(btb_wr_addr, UInt<7>("h045")) @[ifu_bp_ctl.scala 414:95] - node _T_784 = and(_T_783, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_785 = bits(_T_784, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_783 = eq(btb_wr_addr, UInt<7>("h045")) @[ifu_bp_ctl.scala 415:95] + node _T_784 = and(_T_783, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_785 = bits(_T_784, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_79 of rvclkhdr_173 @[lib.scala 352:23] rvclkhdr_79.clock <= clock rvclkhdr_79.reset <= reset @@ -30732,9 +30732,9 @@ circuit quasar_wrapper : rvclkhdr_79.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_69 : UInt, rvclkhdr_79.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_69 <= btb_wr_data @[lib.scala 358:16] - node _T_786 = eq(btb_wr_addr, UInt<7>("h046")) @[ifu_bp_ctl.scala 414:95] - node _T_787 = and(_T_786, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_788 = bits(_T_787, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_786 = eq(btb_wr_addr, UInt<7>("h046")) @[ifu_bp_ctl.scala 415:95] + node _T_787 = and(_T_786, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_788 = bits(_T_787, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_80 of rvclkhdr_174 @[lib.scala 352:23] rvclkhdr_80.clock <= clock rvclkhdr_80.reset <= reset @@ -30743,9 +30743,9 @@ circuit quasar_wrapper : rvclkhdr_80.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_70 : UInt, rvclkhdr_80.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_70 <= btb_wr_data @[lib.scala 358:16] - node _T_789 = eq(btb_wr_addr, UInt<7>("h047")) @[ifu_bp_ctl.scala 414:95] - node _T_790 = and(_T_789, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_791 = bits(_T_790, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_789 = eq(btb_wr_addr, UInt<7>("h047")) @[ifu_bp_ctl.scala 415:95] + node _T_790 = and(_T_789, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_791 = bits(_T_790, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_81 of rvclkhdr_175 @[lib.scala 352:23] rvclkhdr_81.clock <= clock rvclkhdr_81.reset <= reset @@ -30754,9 +30754,9 @@ circuit quasar_wrapper : rvclkhdr_81.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_71 : UInt, rvclkhdr_81.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_71 <= btb_wr_data @[lib.scala 358:16] - node _T_792 = eq(btb_wr_addr, UInt<7>("h048")) @[ifu_bp_ctl.scala 414:95] - node _T_793 = and(_T_792, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_794 = bits(_T_793, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_792 = eq(btb_wr_addr, UInt<7>("h048")) @[ifu_bp_ctl.scala 415:95] + node _T_793 = and(_T_792, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_794 = bits(_T_793, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_82 of rvclkhdr_176 @[lib.scala 352:23] rvclkhdr_82.clock <= clock rvclkhdr_82.reset <= reset @@ -30765,9 +30765,9 @@ circuit quasar_wrapper : rvclkhdr_82.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_72 : UInt, rvclkhdr_82.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_72 <= btb_wr_data @[lib.scala 358:16] - node _T_795 = eq(btb_wr_addr, UInt<7>("h049")) @[ifu_bp_ctl.scala 414:95] - node _T_796 = and(_T_795, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_797 = bits(_T_796, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_795 = eq(btb_wr_addr, UInt<7>("h049")) @[ifu_bp_ctl.scala 415:95] + node _T_796 = and(_T_795, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_797 = bits(_T_796, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_83 of rvclkhdr_177 @[lib.scala 352:23] rvclkhdr_83.clock <= clock rvclkhdr_83.reset <= reset @@ -30776,9 +30776,9 @@ circuit quasar_wrapper : rvclkhdr_83.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_73 : UInt, rvclkhdr_83.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_73 <= btb_wr_data @[lib.scala 358:16] - node _T_798 = eq(btb_wr_addr, UInt<7>("h04a")) @[ifu_bp_ctl.scala 414:95] - node _T_799 = and(_T_798, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_800 = bits(_T_799, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_798 = eq(btb_wr_addr, UInt<7>("h04a")) @[ifu_bp_ctl.scala 415:95] + node _T_799 = and(_T_798, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_800 = bits(_T_799, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_84 of rvclkhdr_178 @[lib.scala 352:23] rvclkhdr_84.clock <= clock rvclkhdr_84.reset <= reset @@ -30787,9 +30787,9 @@ circuit quasar_wrapper : rvclkhdr_84.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_74 : UInt, rvclkhdr_84.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_74 <= btb_wr_data @[lib.scala 358:16] - node _T_801 = eq(btb_wr_addr, UInt<7>("h04b")) @[ifu_bp_ctl.scala 414:95] - node _T_802 = and(_T_801, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_803 = bits(_T_802, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_801 = eq(btb_wr_addr, UInt<7>("h04b")) @[ifu_bp_ctl.scala 415:95] + node _T_802 = and(_T_801, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_803 = bits(_T_802, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_85 of rvclkhdr_179 @[lib.scala 352:23] rvclkhdr_85.clock <= clock rvclkhdr_85.reset <= reset @@ -30798,9 +30798,9 @@ circuit quasar_wrapper : rvclkhdr_85.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_75 : UInt, rvclkhdr_85.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_75 <= btb_wr_data @[lib.scala 358:16] - node _T_804 = eq(btb_wr_addr, UInt<7>("h04c")) @[ifu_bp_ctl.scala 414:95] - node _T_805 = and(_T_804, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_806 = bits(_T_805, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_804 = eq(btb_wr_addr, UInt<7>("h04c")) @[ifu_bp_ctl.scala 415:95] + node _T_805 = and(_T_804, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_806 = bits(_T_805, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_86 of rvclkhdr_180 @[lib.scala 352:23] rvclkhdr_86.clock <= clock rvclkhdr_86.reset <= reset @@ -30809,9 +30809,9 @@ circuit quasar_wrapper : rvclkhdr_86.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_76 : UInt, rvclkhdr_86.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_76 <= btb_wr_data @[lib.scala 358:16] - node _T_807 = eq(btb_wr_addr, UInt<7>("h04d")) @[ifu_bp_ctl.scala 414:95] - node _T_808 = and(_T_807, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_809 = bits(_T_808, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_807 = eq(btb_wr_addr, UInt<7>("h04d")) @[ifu_bp_ctl.scala 415:95] + node _T_808 = and(_T_807, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_809 = bits(_T_808, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_87 of rvclkhdr_181 @[lib.scala 352:23] rvclkhdr_87.clock <= clock rvclkhdr_87.reset <= reset @@ -30820,9 +30820,9 @@ circuit quasar_wrapper : rvclkhdr_87.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_77 : UInt, rvclkhdr_87.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_77 <= btb_wr_data @[lib.scala 358:16] - node _T_810 = eq(btb_wr_addr, UInt<7>("h04e")) @[ifu_bp_ctl.scala 414:95] - node _T_811 = and(_T_810, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_812 = bits(_T_811, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_810 = eq(btb_wr_addr, UInt<7>("h04e")) @[ifu_bp_ctl.scala 415:95] + node _T_811 = and(_T_810, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_812 = bits(_T_811, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_88 of rvclkhdr_182 @[lib.scala 352:23] rvclkhdr_88.clock <= clock rvclkhdr_88.reset <= reset @@ -30831,9 +30831,9 @@ circuit quasar_wrapper : rvclkhdr_88.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_78 : UInt, rvclkhdr_88.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_78 <= btb_wr_data @[lib.scala 358:16] - node _T_813 = eq(btb_wr_addr, UInt<7>("h04f")) @[ifu_bp_ctl.scala 414:95] - node _T_814 = and(_T_813, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_815 = bits(_T_814, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_813 = eq(btb_wr_addr, UInt<7>("h04f")) @[ifu_bp_ctl.scala 415:95] + node _T_814 = and(_T_813, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_815 = bits(_T_814, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_89 of rvclkhdr_183 @[lib.scala 352:23] rvclkhdr_89.clock <= clock rvclkhdr_89.reset <= reset @@ -30842,9 +30842,9 @@ circuit quasar_wrapper : rvclkhdr_89.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_79 : UInt, rvclkhdr_89.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_79 <= btb_wr_data @[lib.scala 358:16] - node _T_816 = eq(btb_wr_addr, UInt<7>("h050")) @[ifu_bp_ctl.scala 414:95] - node _T_817 = and(_T_816, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_818 = bits(_T_817, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_816 = eq(btb_wr_addr, UInt<7>("h050")) @[ifu_bp_ctl.scala 415:95] + node _T_817 = and(_T_816, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_818 = bits(_T_817, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_90 of rvclkhdr_184 @[lib.scala 352:23] rvclkhdr_90.clock <= clock rvclkhdr_90.reset <= reset @@ -30853,9 +30853,9 @@ circuit quasar_wrapper : rvclkhdr_90.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_80 : UInt, rvclkhdr_90.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_80 <= btb_wr_data @[lib.scala 358:16] - node _T_819 = eq(btb_wr_addr, UInt<7>("h051")) @[ifu_bp_ctl.scala 414:95] - node _T_820 = and(_T_819, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_821 = bits(_T_820, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_819 = eq(btb_wr_addr, UInt<7>("h051")) @[ifu_bp_ctl.scala 415:95] + node _T_820 = and(_T_819, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_821 = bits(_T_820, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_91 of rvclkhdr_185 @[lib.scala 352:23] rvclkhdr_91.clock <= clock rvclkhdr_91.reset <= reset @@ -30864,9 +30864,9 @@ circuit quasar_wrapper : rvclkhdr_91.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_81 : UInt, rvclkhdr_91.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_81 <= btb_wr_data @[lib.scala 358:16] - node _T_822 = eq(btb_wr_addr, UInt<7>("h052")) @[ifu_bp_ctl.scala 414:95] - node _T_823 = and(_T_822, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_824 = bits(_T_823, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_822 = eq(btb_wr_addr, UInt<7>("h052")) @[ifu_bp_ctl.scala 415:95] + node _T_823 = and(_T_822, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_824 = bits(_T_823, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_92 of rvclkhdr_186 @[lib.scala 352:23] rvclkhdr_92.clock <= clock rvclkhdr_92.reset <= reset @@ -30875,9 +30875,9 @@ circuit quasar_wrapper : rvclkhdr_92.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_82 : UInt, rvclkhdr_92.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_82 <= btb_wr_data @[lib.scala 358:16] - node _T_825 = eq(btb_wr_addr, UInt<7>("h053")) @[ifu_bp_ctl.scala 414:95] - node _T_826 = and(_T_825, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_827 = bits(_T_826, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_825 = eq(btb_wr_addr, UInt<7>("h053")) @[ifu_bp_ctl.scala 415:95] + node _T_826 = and(_T_825, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_827 = bits(_T_826, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_93 of rvclkhdr_187 @[lib.scala 352:23] rvclkhdr_93.clock <= clock rvclkhdr_93.reset <= reset @@ -30886,9 +30886,9 @@ circuit quasar_wrapper : rvclkhdr_93.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_83 : UInt, rvclkhdr_93.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_83 <= btb_wr_data @[lib.scala 358:16] - node _T_828 = eq(btb_wr_addr, UInt<7>("h054")) @[ifu_bp_ctl.scala 414:95] - node _T_829 = and(_T_828, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_830 = bits(_T_829, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_828 = eq(btb_wr_addr, UInt<7>("h054")) @[ifu_bp_ctl.scala 415:95] + node _T_829 = and(_T_828, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_830 = bits(_T_829, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_94 of rvclkhdr_188 @[lib.scala 352:23] rvclkhdr_94.clock <= clock rvclkhdr_94.reset <= reset @@ -30897,9 +30897,9 @@ circuit quasar_wrapper : rvclkhdr_94.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_84 : UInt, rvclkhdr_94.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_84 <= btb_wr_data @[lib.scala 358:16] - node _T_831 = eq(btb_wr_addr, UInt<7>("h055")) @[ifu_bp_ctl.scala 414:95] - node _T_832 = and(_T_831, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_833 = bits(_T_832, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_831 = eq(btb_wr_addr, UInt<7>("h055")) @[ifu_bp_ctl.scala 415:95] + node _T_832 = and(_T_831, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_833 = bits(_T_832, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_95 of rvclkhdr_189 @[lib.scala 352:23] rvclkhdr_95.clock <= clock rvclkhdr_95.reset <= reset @@ -30908,9 +30908,9 @@ circuit quasar_wrapper : rvclkhdr_95.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_85 : UInt, rvclkhdr_95.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_85 <= btb_wr_data @[lib.scala 358:16] - node _T_834 = eq(btb_wr_addr, UInt<7>("h056")) @[ifu_bp_ctl.scala 414:95] - node _T_835 = and(_T_834, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_836 = bits(_T_835, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_834 = eq(btb_wr_addr, UInt<7>("h056")) @[ifu_bp_ctl.scala 415:95] + node _T_835 = and(_T_834, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_836 = bits(_T_835, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_96 of rvclkhdr_190 @[lib.scala 352:23] rvclkhdr_96.clock <= clock rvclkhdr_96.reset <= reset @@ -30919,9 +30919,9 @@ circuit quasar_wrapper : rvclkhdr_96.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_86 : UInt, rvclkhdr_96.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_86 <= btb_wr_data @[lib.scala 358:16] - node _T_837 = eq(btb_wr_addr, UInt<7>("h057")) @[ifu_bp_ctl.scala 414:95] - node _T_838 = and(_T_837, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_839 = bits(_T_838, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_837 = eq(btb_wr_addr, UInt<7>("h057")) @[ifu_bp_ctl.scala 415:95] + node _T_838 = and(_T_837, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_839 = bits(_T_838, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_97 of rvclkhdr_191 @[lib.scala 352:23] rvclkhdr_97.clock <= clock rvclkhdr_97.reset <= reset @@ -30930,9 +30930,9 @@ circuit quasar_wrapper : rvclkhdr_97.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_87 : UInt, rvclkhdr_97.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_87 <= btb_wr_data @[lib.scala 358:16] - node _T_840 = eq(btb_wr_addr, UInt<7>("h058")) @[ifu_bp_ctl.scala 414:95] - node _T_841 = and(_T_840, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_842 = bits(_T_841, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_840 = eq(btb_wr_addr, UInt<7>("h058")) @[ifu_bp_ctl.scala 415:95] + node _T_841 = and(_T_840, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_842 = bits(_T_841, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_98 of rvclkhdr_192 @[lib.scala 352:23] rvclkhdr_98.clock <= clock rvclkhdr_98.reset <= reset @@ -30941,9 +30941,9 @@ circuit quasar_wrapper : rvclkhdr_98.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_88 : UInt, rvclkhdr_98.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_88 <= btb_wr_data @[lib.scala 358:16] - node _T_843 = eq(btb_wr_addr, UInt<7>("h059")) @[ifu_bp_ctl.scala 414:95] - node _T_844 = and(_T_843, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_845 = bits(_T_844, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_843 = eq(btb_wr_addr, UInt<7>("h059")) @[ifu_bp_ctl.scala 415:95] + node _T_844 = and(_T_843, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_845 = bits(_T_844, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_99 of rvclkhdr_193 @[lib.scala 352:23] rvclkhdr_99.clock <= clock rvclkhdr_99.reset <= reset @@ -30952,9 +30952,9 @@ circuit quasar_wrapper : rvclkhdr_99.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_89 : UInt, rvclkhdr_99.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_89 <= btb_wr_data @[lib.scala 358:16] - node _T_846 = eq(btb_wr_addr, UInt<7>("h05a")) @[ifu_bp_ctl.scala 414:95] - node _T_847 = and(_T_846, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_848 = bits(_T_847, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_846 = eq(btb_wr_addr, UInt<7>("h05a")) @[ifu_bp_ctl.scala 415:95] + node _T_847 = and(_T_846, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_848 = bits(_T_847, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_100 of rvclkhdr_194 @[lib.scala 352:23] rvclkhdr_100.clock <= clock rvclkhdr_100.reset <= reset @@ -30963,9 +30963,9 @@ circuit quasar_wrapper : rvclkhdr_100.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_90 : UInt, rvclkhdr_100.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_90 <= btb_wr_data @[lib.scala 358:16] - node _T_849 = eq(btb_wr_addr, UInt<7>("h05b")) @[ifu_bp_ctl.scala 414:95] - node _T_850 = and(_T_849, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_851 = bits(_T_850, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_849 = eq(btb_wr_addr, UInt<7>("h05b")) @[ifu_bp_ctl.scala 415:95] + node _T_850 = and(_T_849, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_851 = bits(_T_850, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_101 of rvclkhdr_195 @[lib.scala 352:23] rvclkhdr_101.clock <= clock rvclkhdr_101.reset <= reset @@ -30974,9 +30974,9 @@ circuit quasar_wrapper : rvclkhdr_101.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_91 : UInt, rvclkhdr_101.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_91 <= btb_wr_data @[lib.scala 358:16] - node _T_852 = eq(btb_wr_addr, UInt<7>("h05c")) @[ifu_bp_ctl.scala 414:95] - node _T_853 = and(_T_852, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_854 = bits(_T_853, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_852 = eq(btb_wr_addr, UInt<7>("h05c")) @[ifu_bp_ctl.scala 415:95] + node _T_853 = and(_T_852, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_854 = bits(_T_853, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_102 of rvclkhdr_196 @[lib.scala 352:23] rvclkhdr_102.clock <= clock rvclkhdr_102.reset <= reset @@ -30985,9 +30985,9 @@ circuit quasar_wrapper : rvclkhdr_102.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_92 : UInt, rvclkhdr_102.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_92 <= btb_wr_data @[lib.scala 358:16] - node _T_855 = eq(btb_wr_addr, UInt<7>("h05d")) @[ifu_bp_ctl.scala 414:95] - node _T_856 = and(_T_855, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_857 = bits(_T_856, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_855 = eq(btb_wr_addr, UInt<7>("h05d")) @[ifu_bp_ctl.scala 415:95] + node _T_856 = and(_T_855, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_857 = bits(_T_856, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_103 of rvclkhdr_197 @[lib.scala 352:23] rvclkhdr_103.clock <= clock rvclkhdr_103.reset <= reset @@ -30996,9 +30996,9 @@ circuit quasar_wrapper : rvclkhdr_103.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_93 : UInt, rvclkhdr_103.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_93 <= btb_wr_data @[lib.scala 358:16] - node _T_858 = eq(btb_wr_addr, UInt<7>("h05e")) @[ifu_bp_ctl.scala 414:95] - node _T_859 = and(_T_858, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_860 = bits(_T_859, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_858 = eq(btb_wr_addr, UInt<7>("h05e")) @[ifu_bp_ctl.scala 415:95] + node _T_859 = and(_T_858, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_860 = bits(_T_859, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_104 of rvclkhdr_198 @[lib.scala 352:23] rvclkhdr_104.clock <= clock rvclkhdr_104.reset <= reset @@ -31007,9 +31007,9 @@ circuit quasar_wrapper : rvclkhdr_104.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_94 : UInt, rvclkhdr_104.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_94 <= btb_wr_data @[lib.scala 358:16] - node _T_861 = eq(btb_wr_addr, UInt<7>("h05f")) @[ifu_bp_ctl.scala 414:95] - node _T_862 = and(_T_861, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_863 = bits(_T_862, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_861 = eq(btb_wr_addr, UInt<7>("h05f")) @[ifu_bp_ctl.scala 415:95] + node _T_862 = and(_T_861, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_863 = bits(_T_862, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_105 of rvclkhdr_199 @[lib.scala 352:23] rvclkhdr_105.clock <= clock rvclkhdr_105.reset <= reset @@ -31018,9 +31018,9 @@ circuit quasar_wrapper : rvclkhdr_105.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_95 : UInt, rvclkhdr_105.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_95 <= btb_wr_data @[lib.scala 358:16] - node _T_864 = eq(btb_wr_addr, UInt<7>("h060")) @[ifu_bp_ctl.scala 414:95] - node _T_865 = and(_T_864, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_866 = bits(_T_865, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_864 = eq(btb_wr_addr, UInt<7>("h060")) @[ifu_bp_ctl.scala 415:95] + node _T_865 = and(_T_864, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_866 = bits(_T_865, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_106 of rvclkhdr_200 @[lib.scala 352:23] rvclkhdr_106.clock <= clock rvclkhdr_106.reset <= reset @@ -31029,9 +31029,9 @@ circuit quasar_wrapper : rvclkhdr_106.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_96 : UInt, rvclkhdr_106.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_96 <= btb_wr_data @[lib.scala 358:16] - node _T_867 = eq(btb_wr_addr, UInt<7>("h061")) @[ifu_bp_ctl.scala 414:95] - node _T_868 = and(_T_867, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_869 = bits(_T_868, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_867 = eq(btb_wr_addr, UInt<7>("h061")) @[ifu_bp_ctl.scala 415:95] + node _T_868 = and(_T_867, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_869 = bits(_T_868, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_107 of rvclkhdr_201 @[lib.scala 352:23] rvclkhdr_107.clock <= clock rvclkhdr_107.reset <= reset @@ -31040,9 +31040,9 @@ circuit quasar_wrapper : rvclkhdr_107.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_97 : UInt, rvclkhdr_107.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_97 <= btb_wr_data @[lib.scala 358:16] - node _T_870 = eq(btb_wr_addr, UInt<7>("h062")) @[ifu_bp_ctl.scala 414:95] - node _T_871 = and(_T_870, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_872 = bits(_T_871, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_870 = eq(btb_wr_addr, UInt<7>("h062")) @[ifu_bp_ctl.scala 415:95] + node _T_871 = and(_T_870, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_872 = bits(_T_871, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_108 of rvclkhdr_202 @[lib.scala 352:23] rvclkhdr_108.clock <= clock rvclkhdr_108.reset <= reset @@ -31051,9 +31051,9 @@ circuit quasar_wrapper : rvclkhdr_108.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_98 : UInt, rvclkhdr_108.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_98 <= btb_wr_data @[lib.scala 358:16] - node _T_873 = eq(btb_wr_addr, UInt<7>("h063")) @[ifu_bp_ctl.scala 414:95] - node _T_874 = and(_T_873, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_875 = bits(_T_874, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_873 = eq(btb_wr_addr, UInt<7>("h063")) @[ifu_bp_ctl.scala 415:95] + node _T_874 = and(_T_873, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_875 = bits(_T_874, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_109 of rvclkhdr_203 @[lib.scala 352:23] rvclkhdr_109.clock <= clock rvclkhdr_109.reset <= reset @@ -31062,9 +31062,9 @@ circuit quasar_wrapper : rvclkhdr_109.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_99 : UInt, rvclkhdr_109.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_99 <= btb_wr_data @[lib.scala 358:16] - node _T_876 = eq(btb_wr_addr, UInt<7>("h064")) @[ifu_bp_ctl.scala 414:95] - node _T_877 = and(_T_876, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_878 = bits(_T_877, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_876 = eq(btb_wr_addr, UInt<7>("h064")) @[ifu_bp_ctl.scala 415:95] + node _T_877 = and(_T_876, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_878 = bits(_T_877, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_110 of rvclkhdr_204 @[lib.scala 352:23] rvclkhdr_110.clock <= clock rvclkhdr_110.reset <= reset @@ -31073,9 +31073,9 @@ circuit quasar_wrapper : rvclkhdr_110.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_100 : UInt, rvclkhdr_110.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_100 <= btb_wr_data @[lib.scala 358:16] - node _T_879 = eq(btb_wr_addr, UInt<7>("h065")) @[ifu_bp_ctl.scala 414:95] - node _T_880 = and(_T_879, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_881 = bits(_T_880, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_879 = eq(btb_wr_addr, UInt<7>("h065")) @[ifu_bp_ctl.scala 415:95] + node _T_880 = and(_T_879, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_881 = bits(_T_880, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_111 of rvclkhdr_205 @[lib.scala 352:23] rvclkhdr_111.clock <= clock rvclkhdr_111.reset <= reset @@ -31084,9 +31084,9 @@ circuit quasar_wrapper : rvclkhdr_111.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_101 : UInt, rvclkhdr_111.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_101 <= btb_wr_data @[lib.scala 358:16] - node _T_882 = eq(btb_wr_addr, UInt<7>("h066")) @[ifu_bp_ctl.scala 414:95] - node _T_883 = and(_T_882, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_884 = bits(_T_883, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_882 = eq(btb_wr_addr, UInt<7>("h066")) @[ifu_bp_ctl.scala 415:95] + node _T_883 = and(_T_882, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_884 = bits(_T_883, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_112 of rvclkhdr_206 @[lib.scala 352:23] rvclkhdr_112.clock <= clock rvclkhdr_112.reset <= reset @@ -31095,9 +31095,9 @@ circuit quasar_wrapper : rvclkhdr_112.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_102 : UInt, rvclkhdr_112.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_102 <= btb_wr_data @[lib.scala 358:16] - node _T_885 = eq(btb_wr_addr, UInt<7>("h067")) @[ifu_bp_ctl.scala 414:95] - node _T_886 = and(_T_885, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_887 = bits(_T_886, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_885 = eq(btb_wr_addr, UInt<7>("h067")) @[ifu_bp_ctl.scala 415:95] + node _T_886 = and(_T_885, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_887 = bits(_T_886, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_113 of rvclkhdr_207 @[lib.scala 352:23] rvclkhdr_113.clock <= clock rvclkhdr_113.reset <= reset @@ -31106,9 +31106,9 @@ circuit quasar_wrapper : rvclkhdr_113.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_103 : UInt, rvclkhdr_113.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_103 <= btb_wr_data @[lib.scala 358:16] - node _T_888 = eq(btb_wr_addr, UInt<7>("h068")) @[ifu_bp_ctl.scala 414:95] - node _T_889 = and(_T_888, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_890 = bits(_T_889, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_888 = eq(btb_wr_addr, UInt<7>("h068")) @[ifu_bp_ctl.scala 415:95] + node _T_889 = and(_T_888, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_890 = bits(_T_889, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_114 of rvclkhdr_208 @[lib.scala 352:23] rvclkhdr_114.clock <= clock rvclkhdr_114.reset <= reset @@ -31117,9 +31117,9 @@ circuit quasar_wrapper : rvclkhdr_114.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_104 : UInt, rvclkhdr_114.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_104 <= btb_wr_data @[lib.scala 358:16] - node _T_891 = eq(btb_wr_addr, UInt<7>("h069")) @[ifu_bp_ctl.scala 414:95] - node _T_892 = and(_T_891, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_893 = bits(_T_892, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_891 = eq(btb_wr_addr, UInt<7>("h069")) @[ifu_bp_ctl.scala 415:95] + node _T_892 = and(_T_891, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_893 = bits(_T_892, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_115 of rvclkhdr_209 @[lib.scala 352:23] rvclkhdr_115.clock <= clock rvclkhdr_115.reset <= reset @@ -31128,9 +31128,9 @@ circuit quasar_wrapper : rvclkhdr_115.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_105 : UInt, rvclkhdr_115.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_105 <= btb_wr_data @[lib.scala 358:16] - node _T_894 = eq(btb_wr_addr, UInt<7>("h06a")) @[ifu_bp_ctl.scala 414:95] - node _T_895 = and(_T_894, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_896 = bits(_T_895, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_894 = eq(btb_wr_addr, UInt<7>("h06a")) @[ifu_bp_ctl.scala 415:95] + node _T_895 = and(_T_894, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_896 = bits(_T_895, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_116 of rvclkhdr_210 @[lib.scala 352:23] rvclkhdr_116.clock <= clock rvclkhdr_116.reset <= reset @@ -31139,9 +31139,9 @@ circuit quasar_wrapper : rvclkhdr_116.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_106 : UInt, rvclkhdr_116.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_106 <= btb_wr_data @[lib.scala 358:16] - node _T_897 = eq(btb_wr_addr, UInt<7>("h06b")) @[ifu_bp_ctl.scala 414:95] - node _T_898 = and(_T_897, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_899 = bits(_T_898, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_897 = eq(btb_wr_addr, UInt<7>("h06b")) @[ifu_bp_ctl.scala 415:95] + node _T_898 = and(_T_897, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_899 = bits(_T_898, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_117 of rvclkhdr_211 @[lib.scala 352:23] rvclkhdr_117.clock <= clock rvclkhdr_117.reset <= reset @@ -31150,9 +31150,9 @@ circuit quasar_wrapper : rvclkhdr_117.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_107 : UInt, rvclkhdr_117.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_107 <= btb_wr_data @[lib.scala 358:16] - node _T_900 = eq(btb_wr_addr, UInt<7>("h06c")) @[ifu_bp_ctl.scala 414:95] - node _T_901 = and(_T_900, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_902 = bits(_T_901, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_900 = eq(btb_wr_addr, UInt<7>("h06c")) @[ifu_bp_ctl.scala 415:95] + node _T_901 = and(_T_900, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_902 = bits(_T_901, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_118 of rvclkhdr_212 @[lib.scala 352:23] rvclkhdr_118.clock <= clock rvclkhdr_118.reset <= reset @@ -31161,9 +31161,9 @@ circuit quasar_wrapper : rvclkhdr_118.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_108 : UInt, rvclkhdr_118.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_108 <= btb_wr_data @[lib.scala 358:16] - node _T_903 = eq(btb_wr_addr, UInt<7>("h06d")) @[ifu_bp_ctl.scala 414:95] - node _T_904 = and(_T_903, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_905 = bits(_T_904, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_903 = eq(btb_wr_addr, UInt<7>("h06d")) @[ifu_bp_ctl.scala 415:95] + node _T_904 = and(_T_903, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_905 = bits(_T_904, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_119 of rvclkhdr_213 @[lib.scala 352:23] rvclkhdr_119.clock <= clock rvclkhdr_119.reset <= reset @@ -31172,9 +31172,9 @@ circuit quasar_wrapper : rvclkhdr_119.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_109 : UInt, rvclkhdr_119.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_109 <= btb_wr_data @[lib.scala 358:16] - node _T_906 = eq(btb_wr_addr, UInt<7>("h06e")) @[ifu_bp_ctl.scala 414:95] - node _T_907 = and(_T_906, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_908 = bits(_T_907, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_906 = eq(btb_wr_addr, UInt<7>("h06e")) @[ifu_bp_ctl.scala 415:95] + node _T_907 = and(_T_906, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_908 = bits(_T_907, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_120 of rvclkhdr_214 @[lib.scala 352:23] rvclkhdr_120.clock <= clock rvclkhdr_120.reset <= reset @@ -31183,9 +31183,9 @@ circuit quasar_wrapper : rvclkhdr_120.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_110 : UInt, rvclkhdr_120.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_110 <= btb_wr_data @[lib.scala 358:16] - node _T_909 = eq(btb_wr_addr, UInt<7>("h06f")) @[ifu_bp_ctl.scala 414:95] - node _T_910 = and(_T_909, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_911 = bits(_T_910, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_909 = eq(btb_wr_addr, UInt<7>("h06f")) @[ifu_bp_ctl.scala 415:95] + node _T_910 = and(_T_909, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_911 = bits(_T_910, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_121 of rvclkhdr_215 @[lib.scala 352:23] rvclkhdr_121.clock <= clock rvclkhdr_121.reset <= reset @@ -31194,9 +31194,9 @@ circuit quasar_wrapper : rvclkhdr_121.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_111 : UInt, rvclkhdr_121.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_111 <= btb_wr_data @[lib.scala 358:16] - node _T_912 = eq(btb_wr_addr, UInt<7>("h070")) @[ifu_bp_ctl.scala 414:95] - node _T_913 = and(_T_912, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_914 = bits(_T_913, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_912 = eq(btb_wr_addr, UInt<7>("h070")) @[ifu_bp_ctl.scala 415:95] + node _T_913 = and(_T_912, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_914 = bits(_T_913, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_122 of rvclkhdr_216 @[lib.scala 352:23] rvclkhdr_122.clock <= clock rvclkhdr_122.reset <= reset @@ -31205,9 +31205,9 @@ circuit quasar_wrapper : rvclkhdr_122.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_112 : UInt, rvclkhdr_122.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_112 <= btb_wr_data @[lib.scala 358:16] - node _T_915 = eq(btb_wr_addr, UInt<7>("h071")) @[ifu_bp_ctl.scala 414:95] - node _T_916 = and(_T_915, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_917 = bits(_T_916, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_915 = eq(btb_wr_addr, UInt<7>("h071")) @[ifu_bp_ctl.scala 415:95] + node _T_916 = and(_T_915, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_917 = bits(_T_916, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_123 of rvclkhdr_217 @[lib.scala 352:23] rvclkhdr_123.clock <= clock rvclkhdr_123.reset <= reset @@ -31216,9 +31216,9 @@ circuit quasar_wrapper : rvclkhdr_123.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_113 : UInt, rvclkhdr_123.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_113 <= btb_wr_data @[lib.scala 358:16] - node _T_918 = eq(btb_wr_addr, UInt<7>("h072")) @[ifu_bp_ctl.scala 414:95] - node _T_919 = and(_T_918, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_920 = bits(_T_919, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_918 = eq(btb_wr_addr, UInt<7>("h072")) @[ifu_bp_ctl.scala 415:95] + node _T_919 = and(_T_918, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_920 = bits(_T_919, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_124 of rvclkhdr_218 @[lib.scala 352:23] rvclkhdr_124.clock <= clock rvclkhdr_124.reset <= reset @@ -31227,9 +31227,9 @@ circuit quasar_wrapper : rvclkhdr_124.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_114 : UInt, rvclkhdr_124.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_114 <= btb_wr_data @[lib.scala 358:16] - node _T_921 = eq(btb_wr_addr, UInt<7>("h073")) @[ifu_bp_ctl.scala 414:95] - node _T_922 = and(_T_921, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_923 = bits(_T_922, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_921 = eq(btb_wr_addr, UInt<7>("h073")) @[ifu_bp_ctl.scala 415:95] + node _T_922 = and(_T_921, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_923 = bits(_T_922, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_125 of rvclkhdr_219 @[lib.scala 352:23] rvclkhdr_125.clock <= clock rvclkhdr_125.reset <= reset @@ -31238,9 +31238,9 @@ circuit quasar_wrapper : rvclkhdr_125.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_115 : UInt, rvclkhdr_125.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_115 <= btb_wr_data @[lib.scala 358:16] - node _T_924 = eq(btb_wr_addr, UInt<7>("h074")) @[ifu_bp_ctl.scala 414:95] - node _T_925 = and(_T_924, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_926 = bits(_T_925, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_924 = eq(btb_wr_addr, UInt<7>("h074")) @[ifu_bp_ctl.scala 415:95] + node _T_925 = and(_T_924, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_926 = bits(_T_925, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_126 of rvclkhdr_220 @[lib.scala 352:23] rvclkhdr_126.clock <= clock rvclkhdr_126.reset <= reset @@ -31249,9 +31249,9 @@ circuit quasar_wrapper : rvclkhdr_126.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_116 : UInt, rvclkhdr_126.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_116 <= btb_wr_data @[lib.scala 358:16] - node _T_927 = eq(btb_wr_addr, UInt<7>("h075")) @[ifu_bp_ctl.scala 414:95] - node _T_928 = and(_T_927, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_929 = bits(_T_928, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_927 = eq(btb_wr_addr, UInt<7>("h075")) @[ifu_bp_ctl.scala 415:95] + node _T_928 = and(_T_927, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_929 = bits(_T_928, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_127 of rvclkhdr_221 @[lib.scala 352:23] rvclkhdr_127.clock <= clock rvclkhdr_127.reset <= reset @@ -31260,9 +31260,9 @@ circuit quasar_wrapper : rvclkhdr_127.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_117 : UInt, rvclkhdr_127.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_117 <= btb_wr_data @[lib.scala 358:16] - node _T_930 = eq(btb_wr_addr, UInt<7>("h076")) @[ifu_bp_ctl.scala 414:95] - node _T_931 = and(_T_930, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_932 = bits(_T_931, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_930 = eq(btb_wr_addr, UInt<7>("h076")) @[ifu_bp_ctl.scala 415:95] + node _T_931 = and(_T_930, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_932 = bits(_T_931, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_128 of rvclkhdr_222 @[lib.scala 352:23] rvclkhdr_128.clock <= clock rvclkhdr_128.reset <= reset @@ -31271,9 +31271,9 @@ circuit quasar_wrapper : rvclkhdr_128.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_118 : UInt, rvclkhdr_128.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_118 <= btb_wr_data @[lib.scala 358:16] - node _T_933 = eq(btb_wr_addr, UInt<7>("h077")) @[ifu_bp_ctl.scala 414:95] - node _T_934 = and(_T_933, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_935 = bits(_T_934, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_933 = eq(btb_wr_addr, UInt<7>("h077")) @[ifu_bp_ctl.scala 415:95] + node _T_934 = and(_T_933, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_935 = bits(_T_934, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_129 of rvclkhdr_223 @[lib.scala 352:23] rvclkhdr_129.clock <= clock rvclkhdr_129.reset <= reset @@ -31282,9 +31282,9 @@ circuit quasar_wrapper : rvclkhdr_129.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_119 : UInt, rvclkhdr_129.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_119 <= btb_wr_data @[lib.scala 358:16] - node _T_936 = eq(btb_wr_addr, UInt<7>("h078")) @[ifu_bp_ctl.scala 414:95] - node _T_937 = and(_T_936, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_938 = bits(_T_937, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_936 = eq(btb_wr_addr, UInt<7>("h078")) @[ifu_bp_ctl.scala 415:95] + node _T_937 = and(_T_936, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_938 = bits(_T_937, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_130 of rvclkhdr_224 @[lib.scala 352:23] rvclkhdr_130.clock <= clock rvclkhdr_130.reset <= reset @@ -31293,9 +31293,9 @@ circuit quasar_wrapper : rvclkhdr_130.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_120 : UInt, rvclkhdr_130.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_120 <= btb_wr_data @[lib.scala 358:16] - node _T_939 = eq(btb_wr_addr, UInt<7>("h079")) @[ifu_bp_ctl.scala 414:95] - node _T_940 = and(_T_939, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_941 = bits(_T_940, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_939 = eq(btb_wr_addr, UInt<7>("h079")) @[ifu_bp_ctl.scala 415:95] + node _T_940 = and(_T_939, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_941 = bits(_T_940, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_131 of rvclkhdr_225 @[lib.scala 352:23] rvclkhdr_131.clock <= clock rvclkhdr_131.reset <= reset @@ -31304,9 +31304,9 @@ circuit quasar_wrapper : rvclkhdr_131.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_121 : UInt, rvclkhdr_131.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_121 <= btb_wr_data @[lib.scala 358:16] - node _T_942 = eq(btb_wr_addr, UInt<7>("h07a")) @[ifu_bp_ctl.scala 414:95] - node _T_943 = and(_T_942, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_944 = bits(_T_943, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_942 = eq(btb_wr_addr, UInt<7>("h07a")) @[ifu_bp_ctl.scala 415:95] + node _T_943 = and(_T_942, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_944 = bits(_T_943, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_132 of rvclkhdr_226 @[lib.scala 352:23] rvclkhdr_132.clock <= clock rvclkhdr_132.reset <= reset @@ -31315,9 +31315,9 @@ circuit quasar_wrapper : rvclkhdr_132.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_122 : UInt, rvclkhdr_132.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_122 <= btb_wr_data @[lib.scala 358:16] - node _T_945 = eq(btb_wr_addr, UInt<7>("h07b")) @[ifu_bp_ctl.scala 414:95] - node _T_946 = and(_T_945, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_947 = bits(_T_946, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_945 = eq(btb_wr_addr, UInt<7>("h07b")) @[ifu_bp_ctl.scala 415:95] + node _T_946 = and(_T_945, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_947 = bits(_T_946, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_133 of rvclkhdr_227 @[lib.scala 352:23] rvclkhdr_133.clock <= clock rvclkhdr_133.reset <= reset @@ -31326,9 +31326,9 @@ circuit quasar_wrapper : rvclkhdr_133.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_123 : UInt, rvclkhdr_133.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_123 <= btb_wr_data @[lib.scala 358:16] - node _T_948 = eq(btb_wr_addr, UInt<7>("h07c")) @[ifu_bp_ctl.scala 414:95] - node _T_949 = and(_T_948, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_950 = bits(_T_949, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_948 = eq(btb_wr_addr, UInt<7>("h07c")) @[ifu_bp_ctl.scala 415:95] + node _T_949 = and(_T_948, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_950 = bits(_T_949, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_134 of rvclkhdr_228 @[lib.scala 352:23] rvclkhdr_134.clock <= clock rvclkhdr_134.reset <= reset @@ -31337,9 +31337,9 @@ circuit quasar_wrapper : rvclkhdr_134.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_124 : UInt, rvclkhdr_134.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_124 <= btb_wr_data @[lib.scala 358:16] - node _T_951 = eq(btb_wr_addr, UInt<7>("h07d")) @[ifu_bp_ctl.scala 414:95] - node _T_952 = and(_T_951, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_953 = bits(_T_952, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_951 = eq(btb_wr_addr, UInt<7>("h07d")) @[ifu_bp_ctl.scala 415:95] + node _T_952 = and(_T_951, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_953 = bits(_T_952, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_135 of rvclkhdr_229 @[lib.scala 352:23] rvclkhdr_135.clock <= clock rvclkhdr_135.reset <= reset @@ -31348,9 +31348,9 @@ circuit quasar_wrapper : rvclkhdr_135.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_125 : UInt, rvclkhdr_135.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_125 <= btb_wr_data @[lib.scala 358:16] - node _T_954 = eq(btb_wr_addr, UInt<7>("h07e")) @[ifu_bp_ctl.scala 414:95] - node _T_955 = and(_T_954, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_956 = bits(_T_955, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_954 = eq(btb_wr_addr, UInt<7>("h07e")) @[ifu_bp_ctl.scala 415:95] + node _T_955 = and(_T_954, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_956 = bits(_T_955, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_136 of rvclkhdr_230 @[lib.scala 352:23] rvclkhdr_136.clock <= clock rvclkhdr_136.reset <= reset @@ -31359,9 +31359,9 @@ circuit quasar_wrapper : rvclkhdr_136.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_126 : UInt, rvclkhdr_136.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_126 <= btb_wr_data @[lib.scala 358:16] - node _T_957 = eq(btb_wr_addr, UInt<7>("h07f")) @[ifu_bp_ctl.scala 414:95] - node _T_958 = and(_T_957, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_959 = bits(_T_958, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_957 = eq(btb_wr_addr, UInt<7>("h07f")) @[ifu_bp_ctl.scala 415:95] + node _T_958 = and(_T_957, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_959 = bits(_T_958, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_137 of rvclkhdr_231 @[lib.scala 352:23] rvclkhdr_137.clock <= clock rvclkhdr_137.reset <= reset @@ -31370,9 +31370,9 @@ circuit quasar_wrapper : rvclkhdr_137.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_127 : UInt, rvclkhdr_137.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_127 <= btb_wr_data @[lib.scala 358:16] - node _T_960 = eq(btb_wr_addr, UInt<8>("h080")) @[ifu_bp_ctl.scala 414:95] - node _T_961 = and(_T_960, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_962 = bits(_T_961, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_960 = eq(btb_wr_addr, UInt<8>("h080")) @[ifu_bp_ctl.scala 415:95] + node _T_961 = and(_T_960, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_962 = bits(_T_961, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_138 of rvclkhdr_232 @[lib.scala 352:23] rvclkhdr_138.clock <= clock rvclkhdr_138.reset <= reset @@ -31381,9 +31381,9 @@ circuit quasar_wrapper : rvclkhdr_138.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_128 : UInt, rvclkhdr_138.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_128 <= btb_wr_data @[lib.scala 358:16] - node _T_963 = eq(btb_wr_addr, UInt<8>("h081")) @[ifu_bp_ctl.scala 414:95] - node _T_964 = and(_T_963, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_965 = bits(_T_964, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_963 = eq(btb_wr_addr, UInt<8>("h081")) @[ifu_bp_ctl.scala 415:95] + node _T_964 = and(_T_963, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_965 = bits(_T_964, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_139 of rvclkhdr_233 @[lib.scala 352:23] rvclkhdr_139.clock <= clock rvclkhdr_139.reset <= reset @@ -31392,9 +31392,9 @@ circuit quasar_wrapper : rvclkhdr_139.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_129 : UInt, rvclkhdr_139.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_129 <= btb_wr_data @[lib.scala 358:16] - node _T_966 = eq(btb_wr_addr, UInt<8>("h082")) @[ifu_bp_ctl.scala 414:95] - node _T_967 = and(_T_966, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_968 = bits(_T_967, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_966 = eq(btb_wr_addr, UInt<8>("h082")) @[ifu_bp_ctl.scala 415:95] + node _T_967 = and(_T_966, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_968 = bits(_T_967, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_140 of rvclkhdr_234 @[lib.scala 352:23] rvclkhdr_140.clock <= clock rvclkhdr_140.reset <= reset @@ -31403,9 +31403,9 @@ circuit quasar_wrapper : rvclkhdr_140.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_130 : UInt, rvclkhdr_140.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_130 <= btb_wr_data @[lib.scala 358:16] - node _T_969 = eq(btb_wr_addr, UInt<8>("h083")) @[ifu_bp_ctl.scala 414:95] - node _T_970 = and(_T_969, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_971 = bits(_T_970, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_969 = eq(btb_wr_addr, UInt<8>("h083")) @[ifu_bp_ctl.scala 415:95] + node _T_970 = and(_T_969, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_971 = bits(_T_970, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_141 of rvclkhdr_235 @[lib.scala 352:23] rvclkhdr_141.clock <= clock rvclkhdr_141.reset <= reset @@ -31414,9 +31414,9 @@ circuit quasar_wrapper : rvclkhdr_141.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_131 : UInt, rvclkhdr_141.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_131 <= btb_wr_data @[lib.scala 358:16] - node _T_972 = eq(btb_wr_addr, UInt<8>("h084")) @[ifu_bp_ctl.scala 414:95] - node _T_973 = and(_T_972, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_974 = bits(_T_973, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_972 = eq(btb_wr_addr, UInt<8>("h084")) @[ifu_bp_ctl.scala 415:95] + node _T_973 = and(_T_972, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_974 = bits(_T_973, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_142 of rvclkhdr_236 @[lib.scala 352:23] rvclkhdr_142.clock <= clock rvclkhdr_142.reset <= reset @@ -31425,9 +31425,9 @@ circuit quasar_wrapper : rvclkhdr_142.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_132 : UInt, rvclkhdr_142.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_132 <= btb_wr_data @[lib.scala 358:16] - node _T_975 = eq(btb_wr_addr, UInt<8>("h085")) @[ifu_bp_ctl.scala 414:95] - node _T_976 = and(_T_975, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_977 = bits(_T_976, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_975 = eq(btb_wr_addr, UInt<8>("h085")) @[ifu_bp_ctl.scala 415:95] + node _T_976 = and(_T_975, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_977 = bits(_T_976, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_143 of rvclkhdr_237 @[lib.scala 352:23] rvclkhdr_143.clock <= clock rvclkhdr_143.reset <= reset @@ -31436,9 +31436,9 @@ circuit quasar_wrapper : rvclkhdr_143.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_133 : UInt, rvclkhdr_143.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_133 <= btb_wr_data @[lib.scala 358:16] - node _T_978 = eq(btb_wr_addr, UInt<8>("h086")) @[ifu_bp_ctl.scala 414:95] - node _T_979 = and(_T_978, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_980 = bits(_T_979, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_978 = eq(btb_wr_addr, UInt<8>("h086")) @[ifu_bp_ctl.scala 415:95] + node _T_979 = and(_T_978, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_980 = bits(_T_979, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_144 of rvclkhdr_238 @[lib.scala 352:23] rvclkhdr_144.clock <= clock rvclkhdr_144.reset <= reset @@ -31447,9 +31447,9 @@ circuit quasar_wrapper : rvclkhdr_144.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_134 : UInt, rvclkhdr_144.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_134 <= btb_wr_data @[lib.scala 358:16] - node _T_981 = eq(btb_wr_addr, UInt<8>("h087")) @[ifu_bp_ctl.scala 414:95] - node _T_982 = and(_T_981, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_983 = bits(_T_982, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_981 = eq(btb_wr_addr, UInt<8>("h087")) @[ifu_bp_ctl.scala 415:95] + node _T_982 = and(_T_981, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_983 = bits(_T_982, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_145 of rvclkhdr_239 @[lib.scala 352:23] rvclkhdr_145.clock <= clock rvclkhdr_145.reset <= reset @@ -31458,9 +31458,9 @@ circuit quasar_wrapper : rvclkhdr_145.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_135 : UInt, rvclkhdr_145.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_135 <= btb_wr_data @[lib.scala 358:16] - node _T_984 = eq(btb_wr_addr, UInt<8>("h088")) @[ifu_bp_ctl.scala 414:95] - node _T_985 = and(_T_984, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_986 = bits(_T_985, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_984 = eq(btb_wr_addr, UInt<8>("h088")) @[ifu_bp_ctl.scala 415:95] + node _T_985 = and(_T_984, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_986 = bits(_T_985, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_146 of rvclkhdr_240 @[lib.scala 352:23] rvclkhdr_146.clock <= clock rvclkhdr_146.reset <= reset @@ -31469,9 +31469,9 @@ circuit quasar_wrapper : rvclkhdr_146.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_136 : UInt, rvclkhdr_146.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_136 <= btb_wr_data @[lib.scala 358:16] - node _T_987 = eq(btb_wr_addr, UInt<8>("h089")) @[ifu_bp_ctl.scala 414:95] - node _T_988 = and(_T_987, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_989 = bits(_T_988, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_987 = eq(btb_wr_addr, UInt<8>("h089")) @[ifu_bp_ctl.scala 415:95] + node _T_988 = and(_T_987, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_989 = bits(_T_988, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_147 of rvclkhdr_241 @[lib.scala 352:23] rvclkhdr_147.clock <= clock rvclkhdr_147.reset <= reset @@ -31480,9 +31480,9 @@ circuit quasar_wrapper : rvclkhdr_147.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_137 : UInt, rvclkhdr_147.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_137 <= btb_wr_data @[lib.scala 358:16] - node _T_990 = eq(btb_wr_addr, UInt<8>("h08a")) @[ifu_bp_ctl.scala 414:95] - node _T_991 = and(_T_990, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_992 = bits(_T_991, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_990 = eq(btb_wr_addr, UInt<8>("h08a")) @[ifu_bp_ctl.scala 415:95] + node _T_991 = and(_T_990, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_992 = bits(_T_991, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_148 of rvclkhdr_242 @[lib.scala 352:23] rvclkhdr_148.clock <= clock rvclkhdr_148.reset <= reset @@ -31491,9 +31491,9 @@ circuit quasar_wrapper : rvclkhdr_148.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_138 : UInt, rvclkhdr_148.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_138 <= btb_wr_data @[lib.scala 358:16] - node _T_993 = eq(btb_wr_addr, UInt<8>("h08b")) @[ifu_bp_ctl.scala 414:95] - node _T_994 = and(_T_993, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_995 = bits(_T_994, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_993 = eq(btb_wr_addr, UInt<8>("h08b")) @[ifu_bp_ctl.scala 415:95] + node _T_994 = and(_T_993, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_995 = bits(_T_994, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_149 of rvclkhdr_243 @[lib.scala 352:23] rvclkhdr_149.clock <= clock rvclkhdr_149.reset <= reset @@ -31502,9 +31502,9 @@ circuit quasar_wrapper : rvclkhdr_149.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_139 : UInt, rvclkhdr_149.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_139 <= btb_wr_data @[lib.scala 358:16] - node _T_996 = eq(btb_wr_addr, UInt<8>("h08c")) @[ifu_bp_ctl.scala 414:95] - node _T_997 = and(_T_996, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_998 = bits(_T_997, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_996 = eq(btb_wr_addr, UInt<8>("h08c")) @[ifu_bp_ctl.scala 415:95] + node _T_997 = and(_T_996, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_998 = bits(_T_997, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_150 of rvclkhdr_244 @[lib.scala 352:23] rvclkhdr_150.clock <= clock rvclkhdr_150.reset <= reset @@ -31513,9 +31513,9 @@ circuit quasar_wrapper : rvclkhdr_150.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_140 : UInt, rvclkhdr_150.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_140 <= btb_wr_data @[lib.scala 358:16] - node _T_999 = eq(btb_wr_addr, UInt<8>("h08d")) @[ifu_bp_ctl.scala 414:95] - node _T_1000 = and(_T_999, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1001 = bits(_T_1000, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_999 = eq(btb_wr_addr, UInt<8>("h08d")) @[ifu_bp_ctl.scala 415:95] + node _T_1000 = and(_T_999, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1001 = bits(_T_1000, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_151 of rvclkhdr_245 @[lib.scala 352:23] rvclkhdr_151.clock <= clock rvclkhdr_151.reset <= reset @@ -31524,9 +31524,9 @@ circuit quasar_wrapper : rvclkhdr_151.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_141 : UInt, rvclkhdr_151.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_141 <= btb_wr_data @[lib.scala 358:16] - node _T_1002 = eq(btb_wr_addr, UInt<8>("h08e")) @[ifu_bp_ctl.scala 414:95] - node _T_1003 = and(_T_1002, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1004 = bits(_T_1003, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1002 = eq(btb_wr_addr, UInt<8>("h08e")) @[ifu_bp_ctl.scala 415:95] + node _T_1003 = and(_T_1002, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1004 = bits(_T_1003, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_152 of rvclkhdr_246 @[lib.scala 352:23] rvclkhdr_152.clock <= clock rvclkhdr_152.reset <= reset @@ -31535,9 +31535,9 @@ circuit quasar_wrapper : rvclkhdr_152.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_142 : UInt, rvclkhdr_152.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_142 <= btb_wr_data @[lib.scala 358:16] - node _T_1005 = eq(btb_wr_addr, UInt<8>("h08f")) @[ifu_bp_ctl.scala 414:95] - node _T_1006 = and(_T_1005, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1007 = bits(_T_1006, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1005 = eq(btb_wr_addr, UInt<8>("h08f")) @[ifu_bp_ctl.scala 415:95] + node _T_1006 = and(_T_1005, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1007 = bits(_T_1006, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_153 of rvclkhdr_247 @[lib.scala 352:23] rvclkhdr_153.clock <= clock rvclkhdr_153.reset <= reset @@ -31546,9 +31546,9 @@ circuit quasar_wrapper : rvclkhdr_153.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_143 : UInt, rvclkhdr_153.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_143 <= btb_wr_data @[lib.scala 358:16] - node _T_1008 = eq(btb_wr_addr, UInt<8>("h090")) @[ifu_bp_ctl.scala 414:95] - node _T_1009 = and(_T_1008, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1010 = bits(_T_1009, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1008 = eq(btb_wr_addr, UInt<8>("h090")) @[ifu_bp_ctl.scala 415:95] + node _T_1009 = and(_T_1008, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1010 = bits(_T_1009, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_154 of rvclkhdr_248 @[lib.scala 352:23] rvclkhdr_154.clock <= clock rvclkhdr_154.reset <= reset @@ -31557,9 +31557,9 @@ circuit quasar_wrapper : rvclkhdr_154.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_144 : UInt, rvclkhdr_154.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_144 <= btb_wr_data @[lib.scala 358:16] - node _T_1011 = eq(btb_wr_addr, UInt<8>("h091")) @[ifu_bp_ctl.scala 414:95] - node _T_1012 = and(_T_1011, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1013 = bits(_T_1012, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1011 = eq(btb_wr_addr, UInt<8>("h091")) @[ifu_bp_ctl.scala 415:95] + node _T_1012 = and(_T_1011, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1013 = bits(_T_1012, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_155 of rvclkhdr_249 @[lib.scala 352:23] rvclkhdr_155.clock <= clock rvclkhdr_155.reset <= reset @@ -31568,9 +31568,9 @@ circuit quasar_wrapper : rvclkhdr_155.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_145 : UInt, rvclkhdr_155.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_145 <= btb_wr_data @[lib.scala 358:16] - node _T_1014 = eq(btb_wr_addr, UInt<8>("h092")) @[ifu_bp_ctl.scala 414:95] - node _T_1015 = and(_T_1014, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1016 = bits(_T_1015, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1014 = eq(btb_wr_addr, UInt<8>("h092")) @[ifu_bp_ctl.scala 415:95] + node _T_1015 = and(_T_1014, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1016 = bits(_T_1015, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_156 of rvclkhdr_250 @[lib.scala 352:23] rvclkhdr_156.clock <= clock rvclkhdr_156.reset <= reset @@ -31579,9 +31579,9 @@ circuit quasar_wrapper : rvclkhdr_156.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_146 : UInt, rvclkhdr_156.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_146 <= btb_wr_data @[lib.scala 358:16] - node _T_1017 = eq(btb_wr_addr, UInt<8>("h093")) @[ifu_bp_ctl.scala 414:95] - node _T_1018 = and(_T_1017, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1019 = bits(_T_1018, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1017 = eq(btb_wr_addr, UInt<8>("h093")) @[ifu_bp_ctl.scala 415:95] + node _T_1018 = and(_T_1017, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1019 = bits(_T_1018, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_157 of rvclkhdr_251 @[lib.scala 352:23] rvclkhdr_157.clock <= clock rvclkhdr_157.reset <= reset @@ -31590,9 +31590,9 @@ circuit quasar_wrapper : rvclkhdr_157.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_147 : UInt, rvclkhdr_157.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_147 <= btb_wr_data @[lib.scala 358:16] - node _T_1020 = eq(btb_wr_addr, UInt<8>("h094")) @[ifu_bp_ctl.scala 414:95] - node _T_1021 = and(_T_1020, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1022 = bits(_T_1021, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1020 = eq(btb_wr_addr, UInt<8>("h094")) @[ifu_bp_ctl.scala 415:95] + node _T_1021 = and(_T_1020, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1022 = bits(_T_1021, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_158 of rvclkhdr_252 @[lib.scala 352:23] rvclkhdr_158.clock <= clock rvclkhdr_158.reset <= reset @@ -31601,9 +31601,9 @@ circuit quasar_wrapper : rvclkhdr_158.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_148 : UInt, rvclkhdr_158.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_148 <= btb_wr_data @[lib.scala 358:16] - node _T_1023 = eq(btb_wr_addr, UInt<8>("h095")) @[ifu_bp_ctl.scala 414:95] - node _T_1024 = and(_T_1023, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1025 = bits(_T_1024, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1023 = eq(btb_wr_addr, UInt<8>("h095")) @[ifu_bp_ctl.scala 415:95] + node _T_1024 = and(_T_1023, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1025 = bits(_T_1024, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_159 of rvclkhdr_253 @[lib.scala 352:23] rvclkhdr_159.clock <= clock rvclkhdr_159.reset <= reset @@ -31612,9 +31612,9 @@ circuit quasar_wrapper : rvclkhdr_159.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_149 : UInt, rvclkhdr_159.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_149 <= btb_wr_data @[lib.scala 358:16] - node _T_1026 = eq(btb_wr_addr, UInt<8>("h096")) @[ifu_bp_ctl.scala 414:95] - node _T_1027 = and(_T_1026, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1028 = bits(_T_1027, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1026 = eq(btb_wr_addr, UInt<8>("h096")) @[ifu_bp_ctl.scala 415:95] + node _T_1027 = and(_T_1026, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1028 = bits(_T_1027, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_160 of rvclkhdr_254 @[lib.scala 352:23] rvclkhdr_160.clock <= clock rvclkhdr_160.reset <= reset @@ -31623,9 +31623,9 @@ circuit quasar_wrapper : rvclkhdr_160.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_150 : UInt, rvclkhdr_160.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_150 <= btb_wr_data @[lib.scala 358:16] - node _T_1029 = eq(btb_wr_addr, UInt<8>("h097")) @[ifu_bp_ctl.scala 414:95] - node _T_1030 = and(_T_1029, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1031 = bits(_T_1030, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1029 = eq(btb_wr_addr, UInt<8>("h097")) @[ifu_bp_ctl.scala 415:95] + node _T_1030 = and(_T_1029, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1031 = bits(_T_1030, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_161 of rvclkhdr_255 @[lib.scala 352:23] rvclkhdr_161.clock <= clock rvclkhdr_161.reset <= reset @@ -31634,9 +31634,9 @@ circuit quasar_wrapper : rvclkhdr_161.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_151 : UInt, rvclkhdr_161.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_151 <= btb_wr_data @[lib.scala 358:16] - node _T_1032 = eq(btb_wr_addr, UInt<8>("h098")) @[ifu_bp_ctl.scala 414:95] - node _T_1033 = and(_T_1032, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1034 = bits(_T_1033, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1032 = eq(btb_wr_addr, UInt<8>("h098")) @[ifu_bp_ctl.scala 415:95] + node _T_1033 = and(_T_1032, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1034 = bits(_T_1033, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_162 of rvclkhdr_256 @[lib.scala 352:23] rvclkhdr_162.clock <= clock rvclkhdr_162.reset <= reset @@ -31645,9 +31645,9 @@ circuit quasar_wrapper : rvclkhdr_162.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_152 : UInt, rvclkhdr_162.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_152 <= btb_wr_data @[lib.scala 358:16] - node _T_1035 = eq(btb_wr_addr, UInt<8>("h099")) @[ifu_bp_ctl.scala 414:95] - node _T_1036 = and(_T_1035, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1037 = bits(_T_1036, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1035 = eq(btb_wr_addr, UInt<8>("h099")) @[ifu_bp_ctl.scala 415:95] + node _T_1036 = and(_T_1035, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1037 = bits(_T_1036, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_163 of rvclkhdr_257 @[lib.scala 352:23] rvclkhdr_163.clock <= clock rvclkhdr_163.reset <= reset @@ -31656,9 +31656,9 @@ circuit quasar_wrapper : rvclkhdr_163.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_153 : UInt, rvclkhdr_163.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_153 <= btb_wr_data @[lib.scala 358:16] - node _T_1038 = eq(btb_wr_addr, UInt<8>("h09a")) @[ifu_bp_ctl.scala 414:95] - node _T_1039 = and(_T_1038, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1040 = bits(_T_1039, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1038 = eq(btb_wr_addr, UInt<8>("h09a")) @[ifu_bp_ctl.scala 415:95] + node _T_1039 = and(_T_1038, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1040 = bits(_T_1039, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_164 of rvclkhdr_258 @[lib.scala 352:23] rvclkhdr_164.clock <= clock rvclkhdr_164.reset <= reset @@ -31667,9 +31667,9 @@ circuit quasar_wrapper : rvclkhdr_164.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_154 : UInt, rvclkhdr_164.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_154 <= btb_wr_data @[lib.scala 358:16] - node _T_1041 = eq(btb_wr_addr, UInt<8>("h09b")) @[ifu_bp_ctl.scala 414:95] - node _T_1042 = and(_T_1041, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1043 = bits(_T_1042, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1041 = eq(btb_wr_addr, UInt<8>("h09b")) @[ifu_bp_ctl.scala 415:95] + node _T_1042 = and(_T_1041, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1043 = bits(_T_1042, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_165 of rvclkhdr_259 @[lib.scala 352:23] rvclkhdr_165.clock <= clock rvclkhdr_165.reset <= reset @@ -31678,9 +31678,9 @@ circuit quasar_wrapper : rvclkhdr_165.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_155 : UInt, rvclkhdr_165.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_155 <= btb_wr_data @[lib.scala 358:16] - node _T_1044 = eq(btb_wr_addr, UInt<8>("h09c")) @[ifu_bp_ctl.scala 414:95] - node _T_1045 = and(_T_1044, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1046 = bits(_T_1045, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1044 = eq(btb_wr_addr, UInt<8>("h09c")) @[ifu_bp_ctl.scala 415:95] + node _T_1045 = and(_T_1044, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1046 = bits(_T_1045, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_166 of rvclkhdr_260 @[lib.scala 352:23] rvclkhdr_166.clock <= clock rvclkhdr_166.reset <= reset @@ -31689,9 +31689,9 @@ circuit quasar_wrapper : rvclkhdr_166.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_156 : UInt, rvclkhdr_166.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_156 <= btb_wr_data @[lib.scala 358:16] - node _T_1047 = eq(btb_wr_addr, UInt<8>("h09d")) @[ifu_bp_ctl.scala 414:95] - node _T_1048 = and(_T_1047, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1049 = bits(_T_1048, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1047 = eq(btb_wr_addr, UInt<8>("h09d")) @[ifu_bp_ctl.scala 415:95] + node _T_1048 = and(_T_1047, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1049 = bits(_T_1048, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_167 of rvclkhdr_261 @[lib.scala 352:23] rvclkhdr_167.clock <= clock rvclkhdr_167.reset <= reset @@ -31700,9 +31700,9 @@ circuit quasar_wrapper : rvclkhdr_167.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_157 : UInt, rvclkhdr_167.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_157 <= btb_wr_data @[lib.scala 358:16] - node _T_1050 = eq(btb_wr_addr, UInt<8>("h09e")) @[ifu_bp_ctl.scala 414:95] - node _T_1051 = and(_T_1050, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1052 = bits(_T_1051, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1050 = eq(btb_wr_addr, UInt<8>("h09e")) @[ifu_bp_ctl.scala 415:95] + node _T_1051 = and(_T_1050, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1052 = bits(_T_1051, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_168 of rvclkhdr_262 @[lib.scala 352:23] rvclkhdr_168.clock <= clock rvclkhdr_168.reset <= reset @@ -31711,9 +31711,9 @@ circuit quasar_wrapper : rvclkhdr_168.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_158 : UInt, rvclkhdr_168.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_158 <= btb_wr_data @[lib.scala 358:16] - node _T_1053 = eq(btb_wr_addr, UInt<8>("h09f")) @[ifu_bp_ctl.scala 414:95] - node _T_1054 = and(_T_1053, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1055 = bits(_T_1054, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1053 = eq(btb_wr_addr, UInt<8>("h09f")) @[ifu_bp_ctl.scala 415:95] + node _T_1054 = and(_T_1053, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1055 = bits(_T_1054, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_169 of rvclkhdr_263 @[lib.scala 352:23] rvclkhdr_169.clock <= clock rvclkhdr_169.reset <= reset @@ -31722,9 +31722,9 @@ circuit quasar_wrapper : rvclkhdr_169.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_159 : UInt, rvclkhdr_169.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_159 <= btb_wr_data @[lib.scala 358:16] - node _T_1056 = eq(btb_wr_addr, UInt<8>("h0a0")) @[ifu_bp_ctl.scala 414:95] - node _T_1057 = and(_T_1056, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1058 = bits(_T_1057, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1056 = eq(btb_wr_addr, UInt<8>("h0a0")) @[ifu_bp_ctl.scala 415:95] + node _T_1057 = and(_T_1056, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1058 = bits(_T_1057, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_170 of rvclkhdr_264 @[lib.scala 352:23] rvclkhdr_170.clock <= clock rvclkhdr_170.reset <= reset @@ -31733,9 +31733,9 @@ circuit quasar_wrapper : rvclkhdr_170.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_160 : UInt, rvclkhdr_170.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_160 <= btb_wr_data @[lib.scala 358:16] - node _T_1059 = eq(btb_wr_addr, UInt<8>("h0a1")) @[ifu_bp_ctl.scala 414:95] - node _T_1060 = and(_T_1059, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1061 = bits(_T_1060, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1059 = eq(btb_wr_addr, UInt<8>("h0a1")) @[ifu_bp_ctl.scala 415:95] + node _T_1060 = and(_T_1059, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1061 = bits(_T_1060, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_171 of rvclkhdr_265 @[lib.scala 352:23] rvclkhdr_171.clock <= clock rvclkhdr_171.reset <= reset @@ -31744,9 +31744,9 @@ circuit quasar_wrapper : rvclkhdr_171.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_161 : UInt, rvclkhdr_171.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_161 <= btb_wr_data @[lib.scala 358:16] - node _T_1062 = eq(btb_wr_addr, UInt<8>("h0a2")) @[ifu_bp_ctl.scala 414:95] - node _T_1063 = and(_T_1062, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1064 = bits(_T_1063, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1062 = eq(btb_wr_addr, UInt<8>("h0a2")) @[ifu_bp_ctl.scala 415:95] + node _T_1063 = and(_T_1062, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1064 = bits(_T_1063, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_172 of rvclkhdr_266 @[lib.scala 352:23] rvclkhdr_172.clock <= clock rvclkhdr_172.reset <= reset @@ -31755,9 +31755,9 @@ circuit quasar_wrapper : rvclkhdr_172.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_162 : UInt, rvclkhdr_172.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_162 <= btb_wr_data @[lib.scala 358:16] - node _T_1065 = eq(btb_wr_addr, UInt<8>("h0a3")) @[ifu_bp_ctl.scala 414:95] - node _T_1066 = and(_T_1065, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1067 = bits(_T_1066, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1065 = eq(btb_wr_addr, UInt<8>("h0a3")) @[ifu_bp_ctl.scala 415:95] + node _T_1066 = and(_T_1065, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1067 = bits(_T_1066, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_173 of rvclkhdr_267 @[lib.scala 352:23] rvclkhdr_173.clock <= clock rvclkhdr_173.reset <= reset @@ -31766,9 +31766,9 @@ circuit quasar_wrapper : rvclkhdr_173.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_163 : UInt, rvclkhdr_173.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_163 <= btb_wr_data @[lib.scala 358:16] - node _T_1068 = eq(btb_wr_addr, UInt<8>("h0a4")) @[ifu_bp_ctl.scala 414:95] - node _T_1069 = and(_T_1068, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1070 = bits(_T_1069, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1068 = eq(btb_wr_addr, UInt<8>("h0a4")) @[ifu_bp_ctl.scala 415:95] + node _T_1069 = and(_T_1068, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1070 = bits(_T_1069, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_174 of rvclkhdr_268 @[lib.scala 352:23] rvclkhdr_174.clock <= clock rvclkhdr_174.reset <= reset @@ -31777,9 +31777,9 @@ circuit quasar_wrapper : rvclkhdr_174.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_164 : UInt, rvclkhdr_174.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_164 <= btb_wr_data @[lib.scala 358:16] - node _T_1071 = eq(btb_wr_addr, UInt<8>("h0a5")) @[ifu_bp_ctl.scala 414:95] - node _T_1072 = and(_T_1071, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1073 = bits(_T_1072, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1071 = eq(btb_wr_addr, UInt<8>("h0a5")) @[ifu_bp_ctl.scala 415:95] + node _T_1072 = and(_T_1071, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1073 = bits(_T_1072, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_175 of rvclkhdr_269 @[lib.scala 352:23] rvclkhdr_175.clock <= clock rvclkhdr_175.reset <= reset @@ -31788,9 +31788,9 @@ circuit quasar_wrapper : rvclkhdr_175.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_165 : UInt, rvclkhdr_175.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_165 <= btb_wr_data @[lib.scala 358:16] - node _T_1074 = eq(btb_wr_addr, UInt<8>("h0a6")) @[ifu_bp_ctl.scala 414:95] - node _T_1075 = and(_T_1074, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1076 = bits(_T_1075, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1074 = eq(btb_wr_addr, UInt<8>("h0a6")) @[ifu_bp_ctl.scala 415:95] + node _T_1075 = and(_T_1074, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1076 = bits(_T_1075, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_176 of rvclkhdr_270 @[lib.scala 352:23] rvclkhdr_176.clock <= clock rvclkhdr_176.reset <= reset @@ -31799,9 +31799,9 @@ circuit quasar_wrapper : rvclkhdr_176.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_166 : UInt, rvclkhdr_176.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_166 <= btb_wr_data @[lib.scala 358:16] - node _T_1077 = eq(btb_wr_addr, UInt<8>("h0a7")) @[ifu_bp_ctl.scala 414:95] - node _T_1078 = and(_T_1077, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1079 = bits(_T_1078, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1077 = eq(btb_wr_addr, UInt<8>("h0a7")) @[ifu_bp_ctl.scala 415:95] + node _T_1078 = and(_T_1077, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1079 = bits(_T_1078, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_177 of rvclkhdr_271 @[lib.scala 352:23] rvclkhdr_177.clock <= clock rvclkhdr_177.reset <= reset @@ -31810,9 +31810,9 @@ circuit quasar_wrapper : rvclkhdr_177.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_167 : UInt, rvclkhdr_177.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_167 <= btb_wr_data @[lib.scala 358:16] - node _T_1080 = eq(btb_wr_addr, UInt<8>("h0a8")) @[ifu_bp_ctl.scala 414:95] - node _T_1081 = and(_T_1080, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1082 = bits(_T_1081, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1080 = eq(btb_wr_addr, UInt<8>("h0a8")) @[ifu_bp_ctl.scala 415:95] + node _T_1081 = and(_T_1080, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1082 = bits(_T_1081, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_178 of rvclkhdr_272 @[lib.scala 352:23] rvclkhdr_178.clock <= clock rvclkhdr_178.reset <= reset @@ -31821,9 +31821,9 @@ circuit quasar_wrapper : rvclkhdr_178.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_168 : UInt, rvclkhdr_178.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_168 <= btb_wr_data @[lib.scala 358:16] - node _T_1083 = eq(btb_wr_addr, UInt<8>("h0a9")) @[ifu_bp_ctl.scala 414:95] - node _T_1084 = and(_T_1083, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1085 = bits(_T_1084, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1083 = eq(btb_wr_addr, UInt<8>("h0a9")) @[ifu_bp_ctl.scala 415:95] + node _T_1084 = and(_T_1083, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1085 = bits(_T_1084, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_179 of rvclkhdr_273 @[lib.scala 352:23] rvclkhdr_179.clock <= clock rvclkhdr_179.reset <= reset @@ -31832,9 +31832,9 @@ circuit quasar_wrapper : rvclkhdr_179.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_169 : UInt, rvclkhdr_179.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_169 <= btb_wr_data @[lib.scala 358:16] - node _T_1086 = eq(btb_wr_addr, UInt<8>("h0aa")) @[ifu_bp_ctl.scala 414:95] - node _T_1087 = and(_T_1086, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1088 = bits(_T_1087, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1086 = eq(btb_wr_addr, UInt<8>("h0aa")) @[ifu_bp_ctl.scala 415:95] + node _T_1087 = and(_T_1086, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1088 = bits(_T_1087, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_180 of rvclkhdr_274 @[lib.scala 352:23] rvclkhdr_180.clock <= clock rvclkhdr_180.reset <= reset @@ -31843,9 +31843,9 @@ circuit quasar_wrapper : rvclkhdr_180.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_170 : UInt, rvclkhdr_180.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_170 <= btb_wr_data @[lib.scala 358:16] - node _T_1089 = eq(btb_wr_addr, UInt<8>("h0ab")) @[ifu_bp_ctl.scala 414:95] - node _T_1090 = and(_T_1089, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1091 = bits(_T_1090, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1089 = eq(btb_wr_addr, UInt<8>("h0ab")) @[ifu_bp_ctl.scala 415:95] + node _T_1090 = and(_T_1089, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1091 = bits(_T_1090, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_181 of rvclkhdr_275 @[lib.scala 352:23] rvclkhdr_181.clock <= clock rvclkhdr_181.reset <= reset @@ -31854,9 +31854,9 @@ circuit quasar_wrapper : rvclkhdr_181.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_171 : UInt, rvclkhdr_181.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_171 <= btb_wr_data @[lib.scala 358:16] - node _T_1092 = eq(btb_wr_addr, UInt<8>("h0ac")) @[ifu_bp_ctl.scala 414:95] - node _T_1093 = and(_T_1092, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1094 = bits(_T_1093, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1092 = eq(btb_wr_addr, UInt<8>("h0ac")) @[ifu_bp_ctl.scala 415:95] + node _T_1093 = and(_T_1092, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1094 = bits(_T_1093, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_182 of rvclkhdr_276 @[lib.scala 352:23] rvclkhdr_182.clock <= clock rvclkhdr_182.reset <= reset @@ -31865,9 +31865,9 @@ circuit quasar_wrapper : rvclkhdr_182.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_172 : UInt, rvclkhdr_182.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_172 <= btb_wr_data @[lib.scala 358:16] - node _T_1095 = eq(btb_wr_addr, UInt<8>("h0ad")) @[ifu_bp_ctl.scala 414:95] - node _T_1096 = and(_T_1095, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1097 = bits(_T_1096, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1095 = eq(btb_wr_addr, UInt<8>("h0ad")) @[ifu_bp_ctl.scala 415:95] + node _T_1096 = and(_T_1095, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1097 = bits(_T_1096, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_183 of rvclkhdr_277 @[lib.scala 352:23] rvclkhdr_183.clock <= clock rvclkhdr_183.reset <= reset @@ -31876,9 +31876,9 @@ circuit quasar_wrapper : rvclkhdr_183.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_173 : UInt, rvclkhdr_183.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_173 <= btb_wr_data @[lib.scala 358:16] - node _T_1098 = eq(btb_wr_addr, UInt<8>("h0ae")) @[ifu_bp_ctl.scala 414:95] - node _T_1099 = and(_T_1098, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1100 = bits(_T_1099, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1098 = eq(btb_wr_addr, UInt<8>("h0ae")) @[ifu_bp_ctl.scala 415:95] + node _T_1099 = and(_T_1098, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1100 = bits(_T_1099, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_184 of rvclkhdr_278 @[lib.scala 352:23] rvclkhdr_184.clock <= clock rvclkhdr_184.reset <= reset @@ -31887,9 +31887,9 @@ circuit quasar_wrapper : rvclkhdr_184.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_174 : UInt, rvclkhdr_184.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_174 <= btb_wr_data @[lib.scala 358:16] - node _T_1101 = eq(btb_wr_addr, UInt<8>("h0af")) @[ifu_bp_ctl.scala 414:95] - node _T_1102 = and(_T_1101, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1103 = bits(_T_1102, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1101 = eq(btb_wr_addr, UInt<8>("h0af")) @[ifu_bp_ctl.scala 415:95] + node _T_1102 = and(_T_1101, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1103 = bits(_T_1102, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_185 of rvclkhdr_279 @[lib.scala 352:23] rvclkhdr_185.clock <= clock rvclkhdr_185.reset <= reset @@ -31898,9 +31898,9 @@ circuit quasar_wrapper : rvclkhdr_185.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_175 : UInt, rvclkhdr_185.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_175 <= btb_wr_data @[lib.scala 358:16] - node _T_1104 = eq(btb_wr_addr, UInt<8>("h0b0")) @[ifu_bp_ctl.scala 414:95] - node _T_1105 = and(_T_1104, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1106 = bits(_T_1105, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1104 = eq(btb_wr_addr, UInt<8>("h0b0")) @[ifu_bp_ctl.scala 415:95] + node _T_1105 = and(_T_1104, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1106 = bits(_T_1105, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_186 of rvclkhdr_280 @[lib.scala 352:23] rvclkhdr_186.clock <= clock rvclkhdr_186.reset <= reset @@ -31909,9 +31909,9 @@ circuit quasar_wrapper : rvclkhdr_186.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_176 : UInt, rvclkhdr_186.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_176 <= btb_wr_data @[lib.scala 358:16] - node _T_1107 = eq(btb_wr_addr, UInt<8>("h0b1")) @[ifu_bp_ctl.scala 414:95] - node _T_1108 = and(_T_1107, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1109 = bits(_T_1108, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1107 = eq(btb_wr_addr, UInt<8>("h0b1")) @[ifu_bp_ctl.scala 415:95] + node _T_1108 = and(_T_1107, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1109 = bits(_T_1108, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_187 of rvclkhdr_281 @[lib.scala 352:23] rvclkhdr_187.clock <= clock rvclkhdr_187.reset <= reset @@ -31920,9 +31920,9 @@ circuit quasar_wrapper : rvclkhdr_187.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_177 : UInt, rvclkhdr_187.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_177 <= btb_wr_data @[lib.scala 358:16] - node _T_1110 = eq(btb_wr_addr, UInt<8>("h0b2")) @[ifu_bp_ctl.scala 414:95] - node _T_1111 = and(_T_1110, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1112 = bits(_T_1111, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1110 = eq(btb_wr_addr, UInt<8>("h0b2")) @[ifu_bp_ctl.scala 415:95] + node _T_1111 = and(_T_1110, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1112 = bits(_T_1111, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_188 of rvclkhdr_282 @[lib.scala 352:23] rvclkhdr_188.clock <= clock rvclkhdr_188.reset <= reset @@ -31931,9 +31931,9 @@ circuit quasar_wrapper : rvclkhdr_188.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_178 : UInt, rvclkhdr_188.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_178 <= btb_wr_data @[lib.scala 358:16] - node _T_1113 = eq(btb_wr_addr, UInt<8>("h0b3")) @[ifu_bp_ctl.scala 414:95] - node _T_1114 = and(_T_1113, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1115 = bits(_T_1114, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1113 = eq(btb_wr_addr, UInt<8>("h0b3")) @[ifu_bp_ctl.scala 415:95] + node _T_1114 = and(_T_1113, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1115 = bits(_T_1114, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_189 of rvclkhdr_283 @[lib.scala 352:23] rvclkhdr_189.clock <= clock rvclkhdr_189.reset <= reset @@ -31942,9 +31942,9 @@ circuit quasar_wrapper : rvclkhdr_189.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_179 : UInt, rvclkhdr_189.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_179 <= btb_wr_data @[lib.scala 358:16] - node _T_1116 = eq(btb_wr_addr, UInt<8>("h0b4")) @[ifu_bp_ctl.scala 414:95] - node _T_1117 = and(_T_1116, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1118 = bits(_T_1117, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1116 = eq(btb_wr_addr, UInt<8>("h0b4")) @[ifu_bp_ctl.scala 415:95] + node _T_1117 = and(_T_1116, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1118 = bits(_T_1117, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_190 of rvclkhdr_284 @[lib.scala 352:23] rvclkhdr_190.clock <= clock rvclkhdr_190.reset <= reset @@ -31953,9 +31953,9 @@ circuit quasar_wrapper : rvclkhdr_190.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_180 : UInt, rvclkhdr_190.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_180 <= btb_wr_data @[lib.scala 358:16] - node _T_1119 = eq(btb_wr_addr, UInt<8>("h0b5")) @[ifu_bp_ctl.scala 414:95] - node _T_1120 = and(_T_1119, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1121 = bits(_T_1120, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1119 = eq(btb_wr_addr, UInt<8>("h0b5")) @[ifu_bp_ctl.scala 415:95] + node _T_1120 = and(_T_1119, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1121 = bits(_T_1120, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_191 of rvclkhdr_285 @[lib.scala 352:23] rvclkhdr_191.clock <= clock rvclkhdr_191.reset <= reset @@ -31964,9 +31964,9 @@ circuit quasar_wrapper : rvclkhdr_191.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_181 : UInt, rvclkhdr_191.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_181 <= btb_wr_data @[lib.scala 358:16] - node _T_1122 = eq(btb_wr_addr, UInt<8>("h0b6")) @[ifu_bp_ctl.scala 414:95] - node _T_1123 = and(_T_1122, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1124 = bits(_T_1123, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1122 = eq(btb_wr_addr, UInt<8>("h0b6")) @[ifu_bp_ctl.scala 415:95] + node _T_1123 = and(_T_1122, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1124 = bits(_T_1123, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_192 of rvclkhdr_286 @[lib.scala 352:23] rvclkhdr_192.clock <= clock rvclkhdr_192.reset <= reset @@ -31975,9 +31975,9 @@ circuit quasar_wrapper : rvclkhdr_192.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_182 : UInt, rvclkhdr_192.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_182 <= btb_wr_data @[lib.scala 358:16] - node _T_1125 = eq(btb_wr_addr, UInt<8>("h0b7")) @[ifu_bp_ctl.scala 414:95] - node _T_1126 = and(_T_1125, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1127 = bits(_T_1126, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1125 = eq(btb_wr_addr, UInt<8>("h0b7")) @[ifu_bp_ctl.scala 415:95] + node _T_1126 = and(_T_1125, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1127 = bits(_T_1126, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_193 of rvclkhdr_287 @[lib.scala 352:23] rvclkhdr_193.clock <= clock rvclkhdr_193.reset <= reset @@ -31986,9 +31986,9 @@ circuit quasar_wrapper : rvclkhdr_193.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_183 : UInt, rvclkhdr_193.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_183 <= btb_wr_data @[lib.scala 358:16] - node _T_1128 = eq(btb_wr_addr, UInt<8>("h0b8")) @[ifu_bp_ctl.scala 414:95] - node _T_1129 = and(_T_1128, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1130 = bits(_T_1129, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1128 = eq(btb_wr_addr, UInt<8>("h0b8")) @[ifu_bp_ctl.scala 415:95] + node _T_1129 = and(_T_1128, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1130 = bits(_T_1129, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_194 of rvclkhdr_288 @[lib.scala 352:23] rvclkhdr_194.clock <= clock rvclkhdr_194.reset <= reset @@ -31997,9 +31997,9 @@ circuit quasar_wrapper : rvclkhdr_194.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_184 : UInt, rvclkhdr_194.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_184 <= btb_wr_data @[lib.scala 358:16] - node _T_1131 = eq(btb_wr_addr, UInt<8>("h0b9")) @[ifu_bp_ctl.scala 414:95] - node _T_1132 = and(_T_1131, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1133 = bits(_T_1132, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1131 = eq(btb_wr_addr, UInt<8>("h0b9")) @[ifu_bp_ctl.scala 415:95] + node _T_1132 = and(_T_1131, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1133 = bits(_T_1132, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_195 of rvclkhdr_289 @[lib.scala 352:23] rvclkhdr_195.clock <= clock rvclkhdr_195.reset <= reset @@ -32008,9 +32008,9 @@ circuit quasar_wrapper : rvclkhdr_195.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_185 : UInt, rvclkhdr_195.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_185 <= btb_wr_data @[lib.scala 358:16] - node _T_1134 = eq(btb_wr_addr, UInt<8>("h0ba")) @[ifu_bp_ctl.scala 414:95] - node _T_1135 = and(_T_1134, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1136 = bits(_T_1135, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1134 = eq(btb_wr_addr, UInt<8>("h0ba")) @[ifu_bp_ctl.scala 415:95] + node _T_1135 = and(_T_1134, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1136 = bits(_T_1135, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_196 of rvclkhdr_290 @[lib.scala 352:23] rvclkhdr_196.clock <= clock rvclkhdr_196.reset <= reset @@ -32019,9 +32019,9 @@ circuit quasar_wrapper : rvclkhdr_196.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_186 : UInt, rvclkhdr_196.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_186 <= btb_wr_data @[lib.scala 358:16] - node _T_1137 = eq(btb_wr_addr, UInt<8>("h0bb")) @[ifu_bp_ctl.scala 414:95] - node _T_1138 = and(_T_1137, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1139 = bits(_T_1138, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1137 = eq(btb_wr_addr, UInt<8>("h0bb")) @[ifu_bp_ctl.scala 415:95] + node _T_1138 = and(_T_1137, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1139 = bits(_T_1138, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_197 of rvclkhdr_291 @[lib.scala 352:23] rvclkhdr_197.clock <= clock rvclkhdr_197.reset <= reset @@ -32030,9 +32030,9 @@ circuit quasar_wrapper : rvclkhdr_197.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_187 : UInt, rvclkhdr_197.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_187 <= btb_wr_data @[lib.scala 358:16] - node _T_1140 = eq(btb_wr_addr, UInt<8>("h0bc")) @[ifu_bp_ctl.scala 414:95] - node _T_1141 = and(_T_1140, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1142 = bits(_T_1141, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1140 = eq(btb_wr_addr, UInt<8>("h0bc")) @[ifu_bp_ctl.scala 415:95] + node _T_1141 = and(_T_1140, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1142 = bits(_T_1141, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_198 of rvclkhdr_292 @[lib.scala 352:23] rvclkhdr_198.clock <= clock rvclkhdr_198.reset <= reset @@ -32041,9 +32041,9 @@ circuit quasar_wrapper : rvclkhdr_198.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_188 : UInt, rvclkhdr_198.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_188 <= btb_wr_data @[lib.scala 358:16] - node _T_1143 = eq(btb_wr_addr, UInt<8>("h0bd")) @[ifu_bp_ctl.scala 414:95] - node _T_1144 = and(_T_1143, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1145 = bits(_T_1144, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1143 = eq(btb_wr_addr, UInt<8>("h0bd")) @[ifu_bp_ctl.scala 415:95] + node _T_1144 = and(_T_1143, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1145 = bits(_T_1144, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_199 of rvclkhdr_293 @[lib.scala 352:23] rvclkhdr_199.clock <= clock rvclkhdr_199.reset <= reset @@ -32052,9 +32052,9 @@ circuit quasar_wrapper : rvclkhdr_199.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_189 : UInt, rvclkhdr_199.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_189 <= btb_wr_data @[lib.scala 358:16] - node _T_1146 = eq(btb_wr_addr, UInt<8>("h0be")) @[ifu_bp_ctl.scala 414:95] - node _T_1147 = and(_T_1146, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1148 = bits(_T_1147, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1146 = eq(btb_wr_addr, UInt<8>("h0be")) @[ifu_bp_ctl.scala 415:95] + node _T_1147 = and(_T_1146, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1148 = bits(_T_1147, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_200 of rvclkhdr_294 @[lib.scala 352:23] rvclkhdr_200.clock <= clock rvclkhdr_200.reset <= reset @@ -32063,9 +32063,9 @@ circuit quasar_wrapper : rvclkhdr_200.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_190 : UInt, rvclkhdr_200.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_190 <= btb_wr_data @[lib.scala 358:16] - node _T_1149 = eq(btb_wr_addr, UInt<8>("h0bf")) @[ifu_bp_ctl.scala 414:95] - node _T_1150 = and(_T_1149, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1151 = bits(_T_1150, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1149 = eq(btb_wr_addr, UInt<8>("h0bf")) @[ifu_bp_ctl.scala 415:95] + node _T_1150 = and(_T_1149, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1151 = bits(_T_1150, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_201 of rvclkhdr_295 @[lib.scala 352:23] rvclkhdr_201.clock <= clock rvclkhdr_201.reset <= reset @@ -32074,9 +32074,9 @@ circuit quasar_wrapper : rvclkhdr_201.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_191 : UInt, rvclkhdr_201.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_191 <= btb_wr_data @[lib.scala 358:16] - node _T_1152 = eq(btb_wr_addr, UInt<8>("h0c0")) @[ifu_bp_ctl.scala 414:95] - node _T_1153 = and(_T_1152, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1154 = bits(_T_1153, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1152 = eq(btb_wr_addr, UInt<8>("h0c0")) @[ifu_bp_ctl.scala 415:95] + node _T_1153 = and(_T_1152, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1154 = bits(_T_1153, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_202 of rvclkhdr_296 @[lib.scala 352:23] rvclkhdr_202.clock <= clock rvclkhdr_202.reset <= reset @@ -32085,9 +32085,9 @@ circuit quasar_wrapper : rvclkhdr_202.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_192 : UInt, rvclkhdr_202.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_192 <= btb_wr_data @[lib.scala 358:16] - node _T_1155 = eq(btb_wr_addr, UInt<8>("h0c1")) @[ifu_bp_ctl.scala 414:95] - node _T_1156 = and(_T_1155, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1157 = bits(_T_1156, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1155 = eq(btb_wr_addr, UInt<8>("h0c1")) @[ifu_bp_ctl.scala 415:95] + node _T_1156 = and(_T_1155, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1157 = bits(_T_1156, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_203 of rvclkhdr_297 @[lib.scala 352:23] rvclkhdr_203.clock <= clock rvclkhdr_203.reset <= reset @@ -32096,9 +32096,9 @@ circuit quasar_wrapper : rvclkhdr_203.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_193 : UInt, rvclkhdr_203.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_193 <= btb_wr_data @[lib.scala 358:16] - node _T_1158 = eq(btb_wr_addr, UInt<8>("h0c2")) @[ifu_bp_ctl.scala 414:95] - node _T_1159 = and(_T_1158, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1160 = bits(_T_1159, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1158 = eq(btb_wr_addr, UInt<8>("h0c2")) @[ifu_bp_ctl.scala 415:95] + node _T_1159 = and(_T_1158, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1160 = bits(_T_1159, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_204 of rvclkhdr_298 @[lib.scala 352:23] rvclkhdr_204.clock <= clock rvclkhdr_204.reset <= reset @@ -32107,9 +32107,9 @@ circuit quasar_wrapper : rvclkhdr_204.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_194 : UInt, rvclkhdr_204.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_194 <= btb_wr_data @[lib.scala 358:16] - node _T_1161 = eq(btb_wr_addr, UInt<8>("h0c3")) @[ifu_bp_ctl.scala 414:95] - node _T_1162 = and(_T_1161, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1163 = bits(_T_1162, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1161 = eq(btb_wr_addr, UInt<8>("h0c3")) @[ifu_bp_ctl.scala 415:95] + node _T_1162 = and(_T_1161, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1163 = bits(_T_1162, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_205 of rvclkhdr_299 @[lib.scala 352:23] rvclkhdr_205.clock <= clock rvclkhdr_205.reset <= reset @@ -32118,9 +32118,9 @@ circuit quasar_wrapper : rvclkhdr_205.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_195 : UInt, rvclkhdr_205.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_195 <= btb_wr_data @[lib.scala 358:16] - node _T_1164 = eq(btb_wr_addr, UInt<8>("h0c4")) @[ifu_bp_ctl.scala 414:95] - node _T_1165 = and(_T_1164, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1166 = bits(_T_1165, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1164 = eq(btb_wr_addr, UInt<8>("h0c4")) @[ifu_bp_ctl.scala 415:95] + node _T_1165 = and(_T_1164, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1166 = bits(_T_1165, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_206 of rvclkhdr_300 @[lib.scala 352:23] rvclkhdr_206.clock <= clock rvclkhdr_206.reset <= reset @@ -32129,9 +32129,9 @@ circuit quasar_wrapper : rvclkhdr_206.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_196 : UInt, rvclkhdr_206.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_196 <= btb_wr_data @[lib.scala 358:16] - node _T_1167 = eq(btb_wr_addr, UInt<8>("h0c5")) @[ifu_bp_ctl.scala 414:95] - node _T_1168 = and(_T_1167, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1169 = bits(_T_1168, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1167 = eq(btb_wr_addr, UInt<8>("h0c5")) @[ifu_bp_ctl.scala 415:95] + node _T_1168 = and(_T_1167, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1169 = bits(_T_1168, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_207 of rvclkhdr_301 @[lib.scala 352:23] rvclkhdr_207.clock <= clock rvclkhdr_207.reset <= reset @@ -32140,9 +32140,9 @@ circuit quasar_wrapper : rvclkhdr_207.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_197 : UInt, rvclkhdr_207.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_197 <= btb_wr_data @[lib.scala 358:16] - node _T_1170 = eq(btb_wr_addr, UInt<8>("h0c6")) @[ifu_bp_ctl.scala 414:95] - node _T_1171 = and(_T_1170, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1172 = bits(_T_1171, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1170 = eq(btb_wr_addr, UInt<8>("h0c6")) @[ifu_bp_ctl.scala 415:95] + node _T_1171 = and(_T_1170, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1172 = bits(_T_1171, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_208 of rvclkhdr_302 @[lib.scala 352:23] rvclkhdr_208.clock <= clock rvclkhdr_208.reset <= reset @@ -32151,9 +32151,9 @@ circuit quasar_wrapper : rvclkhdr_208.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_198 : UInt, rvclkhdr_208.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_198 <= btb_wr_data @[lib.scala 358:16] - node _T_1173 = eq(btb_wr_addr, UInt<8>("h0c7")) @[ifu_bp_ctl.scala 414:95] - node _T_1174 = and(_T_1173, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1175 = bits(_T_1174, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1173 = eq(btb_wr_addr, UInt<8>("h0c7")) @[ifu_bp_ctl.scala 415:95] + node _T_1174 = and(_T_1173, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1175 = bits(_T_1174, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_209 of rvclkhdr_303 @[lib.scala 352:23] rvclkhdr_209.clock <= clock rvclkhdr_209.reset <= reset @@ -32162,9 +32162,9 @@ circuit quasar_wrapper : rvclkhdr_209.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_199 : UInt, rvclkhdr_209.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_199 <= btb_wr_data @[lib.scala 358:16] - node _T_1176 = eq(btb_wr_addr, UInt<8>("h0c8")) @[ifu_bp_ctl.scala 414:95] - node _T_1177 = and(_T_1176, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1178 = bits(_T_1177, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1176 = eq(btb_wr_addr, UInt<8>("h0c8")) @[ifu_bp_ctl.scala 415:95] + node _T_1177 = and(_T_1176, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1178 = bits(_T_1177, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_210 of rvclkhdr_304 @[lib.scala 352:23] rvclkhdr_210.clock <= clock rvclkhdr_210.reset <= reset @@ -32173,9 +32173,9 @@ circuit quasar_wrapper : rvclkhdr_210.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_200 : UInt, rvclkhdr_210.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_200 <= btb_wr_data @[lib.scala 358:16] - node _T_1179 = eq(btb_wr_addr, UInt<8>("h0c9")) @[ifu_bp_ctl.scala 414:95] - node _T_1180 = and(_T_1179, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1181 = bits(_T_1180, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1179 = eq(btb_wr_addr, UInt<8>("h0c9")) @[ifu_bp_ctl.scala 415:95] + node _T_1180 = and(_T_1179, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1181 = bits(_T_1180, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_211 of rvclkhdr_305 @[lib.scala 352:23] rvclkhdr_211.clock <= clock rvclkhdr_211.reset <= reset @@ -32184,9 +32184,9 @@ circuit quasar_wrapper : rvclkhdr_211.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_201 : UInt, rvclkhdr_211.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_201 <= btb_wr_data @[lib.scala 358:16] - node _T_1182 = eq(btb_wr_addr, UInt<8>("h0ca")) @[ifu_bp_ctl.scala 414:95] - node _T_1183 = and(_T_1182, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1184 = bits(_T_1183, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1182 = eq(btb_wr_addr, UInt<8>("h0ca")) @[ifu_bp_ctl.scala 415:95] + node _T_1183 = and(_T_1182, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1184 = bits(_T_1183, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_212 of rvclkhdr_306 @[lib.scala 352:23] rvclkhdr_212.clock <= clock rvclkhdr_212.reset <= reset @@ -32195,9 +32195,9 @@ circuit quasar_wrapper : rvclkhdr_212.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_202 : UInt, rvclkhdr_212.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_202 <= btb_wr_data @[lib.scala 358:16] - node _T_1185 = eq(btb_wr_addr, UInt<8>("h0cb")) @[ifu_bp_ctl.scala 414:95] - node _T_1186 = and(_T_1185, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1187 = bits(_T_1186, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1185 = eq(btb_wr_addr, UInt<8>("h0cb")) @[ifu_bp_ctl.scala 415:95] + node _T_1186 = and(_T_1185, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1187 = bits(_T_1186, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_213 of rvclkhdr_307 @[lib.scala 352:23] rvclkhdr_213.clock <= clock rvclkhdr_213.reset <= reset @@ -32206,9 +32206,9 @@ circuit quasar_wrapper : rvclkhdr_213.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_203 : UInt, rvclkhdr_213.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_203 <= btb_wr_data @[lib.scala 358:16] - node _T_1188 = eq(btb_wr_addr, UInt<8>("h0cc")) @[ifu_bp_ctl.scala 414:95] - node _T_1189 = and(_T_1188, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1190 = bits(_T_1189, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1188 = eq(btb_wr_addr, UInt<8>("h0cc")) @[ifu_bp_ctl.scala 415:95] + node _T_1189 = and(_T_1188, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1190 = bits(_T_1189, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_214 of rvclkhdr_308 @[lib.scala 352:23] rvclkhdr_214.clock <= clock rvclkhdr_214.reset <= reset @@ -32217,9 +32217,9 @@ circuit quasar_wrapper : rvclkhdr_214.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_204 : UInt, rvclkhdr_214.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_204 <= btb_wr_data @[lib.scala 358:16] - node _T_1191 = eq(btb_wr_addr, UInt<8>("h0cd")) @[ifu_bp_ctl.scala 414:95] - node _T_1192 = and(_T_1191, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1193 = bits(_T_1192, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1191 = eq(btb_wr_addr, UInt<8>("h0cd")) @[ifu_bp_ctl.scala 415:95] + node _T_1192 = and(_T_1191, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1193 = bits(_T_1192, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_215 of rvclkhdr_309 @[lib.scala 352:23] rvclkhdr_215.clock <= clock rvclkhdr_215.reset <= reset @@ -32228,9 +32228,9 @@ circuit quasar_wrapper : rvclkhdr_215.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_205 : UInt, rvclkhdr_215.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_205 <= btb_wr_data @[lib.scala 358:16] - node _T_1194 = eq(btb_wr_addr, UInt<8>("h0ce")) @[ifu_bp_ctl.scala 414:95] - node _T_1195 = and(_T_1194, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1196 = bits(_T_1195, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1194 = eq(btb_wr_addr, UInt<8>("h0ce")) @[ifu_bp_ctl.scala 415:95] + node _T_1195 = and(_T_1194, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1196 = bits(_T_1195, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_216 of rvclkhdr_310 @[lib.scala 352:23] rvclkhdr_216.clock <= clock rvclkhdr_216.reset <= reset @@ -32239,9 +32239,9 @@ circuit quasar_wrapper : rvclkhdr_216.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_206 : UInt, rvclkhdr_216.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_206 <= btb_wr_data @[lib.scala 358:16] - node _T_1197 = eq(btb_wr_addr, UInt<8>("h0cf")) @[ifu_bp_ctl.scala 414:95] - node _T_1198 = and(_T_1197, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1199 = bits(_T_1198, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1197 = eq(btb_wr_addr, UInt<8>("h0cf")) @[ifu_bp_ctl.scala 415:95] + node _T_1198 = and(_T_1197, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1199 = bits(_T_1198, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_217 of rvclkhdr_311 @[lib.scala 352:23] rvclkhdr_217.clock <= clock rvclkhdr_217.reset <= reset @@ -32250,9 +32250,9 @@ circuit quasar_wrapper : rvclkhdr_217.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_207 : UInt, rvclkhdr_217.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_207 <= btb_wr_data @[lib.scala 358:16] - node _T_1200 = eq(btb_wr_addr, UInt<8>("h0d0")) @[ifu_bp_ctl.scala 414:95] - node _T_1201 = and(_T_1200, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1202 = bits(_T_1201, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1200 = eq(btb_wr_addr, UInt<8>("h0d0")) @[ifu_bp_ctl.scala 415:95] + node _T_1201 = and(_T_1200, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1202 = bits(_T_1201, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_218 of rvclkhdr_312 @[lib.scala 352:23] rvclkhdr_218.clock <= clock rvclkhdr_218.reset <= reset @@ -32261,9 +32261,9 @@ circuit quasar_wrapper : rvclkhdr_218.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_208 : UInt, rvclkhdr_218.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_208 <= btb_wr_data @[lib.scala 358:16] - node _T_1203 = eq(btb_wr_addr, UInt<8>("h0d1")) @[ifu_bp_ctl.scala 414:95] - node _T_1204 = and(_T_1203, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1205 = bits(_T_1204, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1203 = eq(btb_wr_addr, UInt<8>("h0d1")) @[ifu_bp_ctl.scala 415:95] + node _T_1204 = and(_T_1203, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1205 = bits(_T_1204, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_219 of rvclkhdr_313 @[lib.scala 352:23] rvclkhdr_219.clock <= clock rvclkhdr_219.reset <= reset @@ -32272,9 +32272,9 @@ circuit quasar_wrapper : rvclkhdr_219.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_209 : UInt, rvclkhdr_219.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_209 <= btb_wr_data @[lib.scala 358:16] - node _T_1206 = eq(btb_wr_addr, UInt<8>("h0d2")) @[ifu_bp_ctl.scala 414:95] - node _T_1207 = and(_T_1206, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1208 = bits(_T_1207, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1206 = eq(btb_wr_addr, UInt<8>("h0d2")) @[ifu_bp_ctl.scala 415:95] + node _T_1207 = and(_T_1206, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1208 = bits(_T_1207, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_220 of rvclkhdr_314 @[lib.scala 352:23] rvclkhdr_220.clock <= clock rvclkhdr_220.reset <= reset @@ -32283,9 +32283,9 @@ circuit quasar_wrapper : rvclkhdr_220.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_210 : UInt, rvclkhdr_220.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_210 <= btb_wr_data @[lib.scala 358:16] - node _T_1209 = eq(btb_wr_addr, UInt<8>("h0d3")) @[ifu_bp_ctl.scala 414:95] - node _T_1210 = and(_T_1209, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1211 = bits(_T_1210, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1209 = eq(btb_wr_addr, UInt<8>("h0d3")) @[ifu_bp_ctl.scala 415:95] + node _T_1210 = and(_T_1209, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1211 = bits(_T_1210, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_221 of rvclkhdr_315 @[lib.scala 352:23] rvclkhdr_221.clock <= clock rvclkhdr_221.reset <= reset @@ -32294,9 +32294,9 @@ circuit quasar_wrapper : rvclkhdr_221.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_211 : UInt, rvclkhdr_221.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_211 <= btb_wr_data @[lib.scala 358:16] - node _T_1212 = eq(btb_wr_addr, UInt<8>("h0d4")) @[ifu_bp_ctl.scala 414:95] - node _T_1213 = and(_T_1212, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1214 = bits(_T_1213, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1212 = eq(btb_wr_addr, UInt<8>("h0d4")) @[ifu_bp_ctl.scala 415:95] + node _T_1213 = and(_T_1212, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1214 = bits(_T_1213, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_222 of rvclkhdr_316 @[lib.scala 352:23] rvclkhdr_222.clock <= clock rvclkhdr_222.reset <= reset @@ -32305,9 +32305,9 @@ circuit quasar_wrapper : rvclkhdr_222.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_212 : UInt, rvclkhdr_222.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_212 <= btb_wr_data @[lib.scala 358:16] - node _T_1215 = eq(btb_wr_addr, UInt<8>("h0d5")) @[ifu_bp_ctl.scala 414:95] - node _T_1216 = and(_T_1215, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1217 = bits(_T_1216, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1215 = eq(btb_wr_addr, UInt<8>("h0d5")) @[ifu_bp_ctl.scala 415:95] + node _T_1216 = and(_T_1215, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1217 = bits(_T_1216, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_223 of rvclkhdr_317 @[lib.scala 352:23] rvclkhdr_223.clock <= clock rvclkhdr_223.reset <= reset @@ -32316,9 +32316,9 @@ circuit quasar_wrapper : rvclkhdr_223.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_213 : UInt, rvclkhdr_223.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_213 <= btb_wr_data @[lib.scala 358:16] - node _T_1218 = eq(btb_wr_addr, UInt<8>("h0d6")) @[ifu_bp_ctl.scala 414:95] - node _T_1219 = and(_T_1218, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1220 = bits(_T_1219, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1218 = eq(btb_wr_addr, UInt<8>("h0d6")) @[ifu_bp_ctl.scala 415:95] + node _T_1219 = and(_T_1218, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1220 = bits(_T_1219, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_224 of rvclkhdr_318 @[lib.scala 352:23] rvclkhdr_224.clock <= clock rvclkhdr_224.reset <= reset @@ -32327,9 +32327,9 @@ circuit quasar_wrapper : rvclkhdr_224.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_214 : UInt, rvclkhdr_224.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_214 <= btb_wr_data @[lib.scala 358:16] - node _T_1221 = eq(btb_wr_addr, UInt<8>("h0d7")) @[ifu_bp_ctl.scala 414:95] - node _T_1222 = and(_T_1221, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1223 = bits(_T_1222, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1221 = eq(btb_wr_addr, UInt<8>("h0d7")) @[ifu_bp_ctl.scala 415:95] + node _T_1222 = and(_T_1221, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1223 = bits(_T_1222, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_225 of rvclkhdr_319 @[lib.scala 352:23] rvclkhdr_225.clock <= clock rvclkhdr_225.reset <= reset @@ -32338,9 +32338,9 @@ circuit quasar_wrapper : rvclkhdr_225.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_215 : UInt, rvclkhdr_225.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_215 <= btb_wr_data @[lib.scala 358:16] - node _T_1224 = eq(btb_wr_addr, UInt<8>("h0d8")) @[ifu_bp_ctl.scala 414:95] - node _T_1225 = and(_T_1224, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1226 = bits(_T_1225, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1224 = eq(btb_wr_addr, UInt<8>("h0d8")) @[ifu_bp_ctl.scala 415:95] + node _T_1225 = and(_T_1224, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1226 = bits(_T_1225, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_226 of rvclkhdr_320 @[lib.scala 352:23] rvclkhdr_226.clock <= clock rvclkhdr_226.reset <= reset @@ -32349,9 +32349,9 @@ circuit quasar_wrapper : rvclkhdr_226.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_216 : UInt, rvclkhdr_226.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_216 <= btb_wr_data @[lib.scala 358:16] - node _T_1227 = eq(btb_wr_addr, UInt<8>("h0d9")) @[ifu_bp_ctl.scala 414:95] - node _T_1228 = and(_T_1227, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1229 = bits(_T_1228, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1227 = eq(btb_wr_addr, UInt<8>("h0d9")) @[ifu_bp_ctl.scala 415:95] + node _T_1228 = and(_T_1227, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1229 = bits(_T_1228, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_227 of rvclkhdr_321 @[lib.scala 352:23] rvclkhdr_227.clock <= clock rvclkhdr_227.reset <= reset @@ -32360,9 +32360,9 @@ circuit quasar_wrapper : rvclkhdr_227.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_217 : UInt, rvclkhdr_227.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_217 <= btb_wr_data @[lib.scala 358:16] - node _T_1230 = eq(btb_wr_addr, UInt<8>("h0da")) @[ifu_bp_ctl.scala 414:95] - node _T_1231 = and(_T_1230, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1232 = bits(_T_1231, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1230 = eq(btb_wr_addr, UInt<8>("h0da")) @[ifu_bp_ctl.scala 415:95] + node _T_1231 = and(_T_1230, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1232 = bits(_T_1231, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_228 of rvclkhdr_322 @[lib.scala 352:23] rvclkhdr_228.clock <= clock rvclkhdr_228.reset <= reset @@ -32371,9 +32371,9 @@ circuit quasar_wrapper : rvclkhdr_228.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_218 : UInt, rvclkhdr_228.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_218 <= btb_wr_data @[lib.scala 358:16] - node _T_1233 = eq(btb_wr_addr, UInt<8>("h0db")) @[ifu_bp_ctl.scala 414:95] - node _T_1234 = and(_T_1233, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1235 = bits(_T_1234, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1233 = eq(btb_wr_addr, UInt<8>("h0db")) @[ifu_bp_ctl.scala 415:95] + node _T_1234 = and(_T_1233, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1235 = bits(_T_1234, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_229 of rvclkhdr_323 @[lib.scala 352:23] rvclkhdr_229.clock <= clock rvclkhdr_229.reset <= reset @@ -32382,9 +32382,9 @@ circuit quasar_wrapper : rvclkhdr_229.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_219 : UInt, rvclkhdr_229.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_219 <= btb_wr_data @[lib.scala 358:16] - node _T_1236 = eq(btb_wr_addr, UInt<8>("h0dc")) @[ifu_bp_ctl.scala 414:95] - node _T_1237 = and(_T_1236, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1238 = bits(_T_1237, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1236 = eq(btb_wr_addr, UInt<8>("h0dc")) @[ifu_bp_ctl.scala 415:95] + node _T_1237 = and(_T_1236, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1238 = bits(_T_1237, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_230 of rvclkhdr_324 @[lib.scala 352:23] rvclkhdr_230.clock <= clock rvclkhdr_230.reset <= reset @@ -32393,9 +32393,9 @@ circuit quasar_wrapper : rvclkhdr_230.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_220 : UInt, rvclkhdr_230.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_220 <= btb_wr_data @[lib.scala 358:16] - node _T_1239 = eq(btb_wr_addr, UInt<8>("h0dd")) @[ifu_bp_ctl.scala 414:95] - node _T_1240 = and(_T_1239, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1241 = bits(_T_1240, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1239 = eq(btb_wr_addr, UInt<8>("h0dd")) @[ifu_bp_ctl.scala 415:95] + node _T_1240 = and(_T_1239, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1241 = bits(_T_1240, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_231 of rvclkhdr_325 @[lib.scala 352:23] rvclkhdr_231.clock <= clock rvclkhdr_231.reset <= reset @@ -32404,9 +32404,9 @@ circuit quasar_wrapper : rvclkhdr_231.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_221 : UInt, rvclkhdr_231.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_221 <= btb_wr_data @[lib.scala 358:16] - node _T_1242 = eq(btb_wr_addr, UInt<8>("h0de")) @[ifu_bp_ctl.scala 414:95] - node _T_1243 = and(_T_1242, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1244 = bits(_T_1243, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1242 = eq(btb_wr_addr, UInt<8>("h0de")) @[ifu_bp_ctl.scala 415:95] + node _T_1243 = and(_T_1242, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1244 = bits(_T_1243, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_232 of rvclkhdr_326 @[lib.scala 352:23] rvclkhdr_232.clock <= clock rvclkhdr_232.reset <= reset @@ -32415,9 +32415,9 @@ circuit quasar_wrapper : rvclkhdr_232.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_222 : UInt, rvclkhdr_232.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_222 <= btb_wr_data @[lib.scala 358:16] - node _T_1245 = eq(btb_wr_addr, UInt<8>("h0df")) @[ifu_bp_ctl.scala 414:95] - node _T_1246 = and(_T_1245, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1247 = bits(_T_1246, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1245 = eq(btb_wr_addr, UInt<8>("h0df")) @[ifu_bp_ctl.scala 415:95] + node _T_1246 = and(_T_1245, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1247 = bits(_T_1246, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_233 of rvclkhdr_327 @[lib.scala 352:23] rvclkhdr_233.clock <= clock rvclkhdr_233.reset <= reset @@ -32426,9 +32426,9 @@ circuit quasar_wrapper : rvclkhdr_233.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_223 : UInt, rvclkhdr_233.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_223 <= btb_wr_data @[lib.scala 358:16] - node _T_1248 = eq(btb_wr_addr, UInt<8>("h0e0")) @[ifu_bp_ctl.scala 414:95] - node _T_1249 = and(_T_1248, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1250 = bits(_T_1249, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1248 = eq(btb_wr_addr, UInt<8>("h0e0")) @[ifu_bp_ctl.scala 415:95] + node _T_1249 = and(_T_1248, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1250 = bits(_T_1249, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_234 of rvclkhdr_328 @[lib.scala 352:23] rvclkhdr_234.clock <= clock rvclkhdr_234.reset <= reset @@ -32437,9 +32437,9 @@ circuit quasar_wrapper : rvclkhdr_234.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_224 : UInt, rvclkhdr_234.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_224 <= btb_wr_data @[lib.scala 358:16] - node _T_1251 = eq(btb_wr_addr, UInt<8>("h0e1")) @[ifu_bp_ctl.scala 414:95] - node _T_1252 = and(_T_1251, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1253 = bits(_T_1252, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1251 = eq(btb_wr_addr, UInt<8>("h0e1")) @[ifu_bp_ctl.scala 415:95] + node _T_1252 = and(_T_1251, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1253 = bits(_T_1252, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_235 of rvclkhdr_329 @[lib.scala 352:23] rvclkhdr_235.clock <= clock rvclkhdr_235.reset <= reset @@ -32448,9 +32448,9 @@ circuit quasar_wrapper : rvclkhdr_235.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_225 : UInt, rvclkhdr_235.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_225 <= btb_wr_data @[lib.scala 358:16] - node _T_1254 = eq(btb_wr_addr, UInt<8>("h0e2")) @[ifu_bp_ctl.scala 414:95] - node _T_1255 = and(_T_1254, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1256 = bits(_T_1255, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1254 = eq(btb_wr_addr, UInt<8>("h0e2")) @[ifu_bp_ctl.scala 415:95] + node _T_1255 = and(_T_1254, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1256 = bits(_T_1255, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_236 of rvclkhdr_330 @[lib.scala 352:23] rvclkhdr_236.clock <= clock rvclkhdr_236.reset <= reset @@ -32459,9 +32459,9 @@ circuit quasar_wrapper : rvclkhdr_236.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_226 : UInt, rvclkhdr_236.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_226 <= btb_wr_data @[lib.scala 358:16] - node _T_1257 = eq(btb_wr_addr, UInt<8>("h0e3")) @[ifu_bp_ctl.scala 414:95] - node _T_1258 = and(_T_1257, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1259 = bits(_T_1258, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1257 = eq(btb_wr_addr, UInt<8>("h0e3")) @[ifu_bp_ctl.scala 415:95] + node _T_1258 = and(_T_1257, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1259 = bits(_T_1258, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_237 of rvclkhdr_331 @[lib.scala 352:23] rvclkhdr_237.clock <= clock rvclkhdr_237.reset <= reset @@ -32470,9 +32470,9 @@ circuit quasar_wrapper : rvclkhdr_237.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_227 : UInt, rvclkhdr_237.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_227 <= btb_wr_data @[lib.scala 358:16] - node _T_1260 = eq(btb_wr_addr, UInt<8>("h0e4")) @[ifu_bp_ctl.scala 414:95] - node _T_1261 = and(_T_1260, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1262 = bits(_T_1261, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1260 = eq(btb_wr_addr, UInt<8>("h0e4")) @[ifu_bp_ctl.scala 415:95] + node _T_1261 = and(_T_1260, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1262 = bits(_T_1261, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_238 of rvclkhdr_332 @[lib.scala 352:23] rvclkhdr_238.clock <= clock rvclkhdr_238.reset <= reset @@ -32481,9 +32481,9 @@ circuit quasar_wrapper : rvclkhdr_238.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_228 : UInt, rvclkhdr_238.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_228 <= btb_wr_data @[lib.scala 358:16] - node _T_1263 = eq(btb_wr_addr, UInt<8>("h0e5")) @[ifu_bp_ctl.scala 414:95] - node _T_1264 = and(_T_1263, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1265 = bits(_T_1264, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1263 = eq(btb_wr_addr, UInt<8>("h0e5")) @[ifu_bp_ctl.scala 415:95] + node _T_1264 = and(_T_1263, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1265 = bits(_T_1264, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_239 of rvclkhdr_333 @[lib.scala 352:23] rvclkhdr_239.clock <= clock rvclkhdr_239.reset <= reset @@ -32492,9 +32492,9 @@ circuit quasar_wrapper : rvclkhdr_239.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_229 : UInt, rvclkhdr_239.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_229 <= btb_wr_data @[lib.scala 358:16] - node _T_1266 = eq(btb_wr_addr, UInt<8>("h0e6")) @[ifu_bp_ctl.scala 414:95] - node _T_1267 = and(_T_1266, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1268 = bits(_T_1267, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1266 = eq(btb_wr_addr, UInt<8>("h0e6")) @[ifu_bp_ctl.scala 415:95] + node _T_1267 = and(_T_1266, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1268 = bits(_T_1267, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_240 of rvclkhdr_334 @[lib.scala 352:23] rvclkhdr_240.clock <= clock rvclkhdr_240.reset <= reset @@ -32503,9 +32503,9 @@ circuit quasar_wrapper : rvclkhdr_240.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_230 : UInt, rvclkhdr_240.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_230 <= btb_wr_data @[lib.scala 358:16] - node _T_1269 = eq(btb_wr_addr, UInt<8>("h0e7")) @[ifu_bp_ctl.scala 414:95] - node _T_1270 = and(_T_1269, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1271 = bits(_T_1270, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1269 = eq(btb_wr_addr, UInt<8>("h0e7")) @[ifu_bp_ctl.scala 415:95] + node _T_1270 = and(_T_1269, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1271 = bits(_T_1270, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_241 of rvclkhdr_335 @[lib.scala 352:23] rvclkhdr_241.clock <= clock rvclkhdr_241.reset <= reset @@ -32514,9 +32514,9 @@ circuit quasar_wrapper : rvclkhdr_241.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_231 : UInt, rvclkhdr_241.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_231 <= btb_wr_data @[lib.scala 358:16] - node _T_1272 = eq(btb_wr_addr, UInt<8>("h0e8")) @[ifu_bp_ctl.scala 414:95] - node _T_1273 = and(_T_1272, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1274 = bits(_T_1273, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1272 = eq(btb_wr_addr, UInt<8>("h0e8")) @[ifu_bp_ctl.scala 415:95] + node _T_1273 = and(_T_1272, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1274 = bits(_T_1273, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_242 of rvclkhdr_336 @[lib.scala 352:23] rvclkhdr_242.clock <= clock rvclkhdr_242.reset <= reset @@ -32525,9 +32525,9 @@ circuit quasar_wrapper : rvclkhdr_242.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_232 : UInt, rvclkhdr_242.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_232 <= btb_wr_data @[lib.scala 358:16] - node _T_1275 = eq(btb_wr_addr, UInt<8>("h0e9")) @[ifu_bp_ctl.scala 414:95] - node _T_1276 = and(_T_1275, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1277 = bits(_T_1276, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1275 = eq(btb_wr_addr, UInt<8>("h0e9")) @[ifu_bp_ctl.scala 415:95] + node _T_1276 = and(_T_1275, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1277 = bits(_T_1276, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_243 of rvclkhdr_337 @[lib.scala 352:23] rvclkhdr_243.clock <= clock rvclkhdr_243.reset <= reset @@ -32536,9 +32536,9 @@ circuit quasar_wrapper : rvclkhdr_243.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_233 : UInt, rvclkhdr_243.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_233 <= btb_wr_data @[lib.scala 358:16] - node _T_1278 = eq(btb_wr_addr, UInt<8>("h0ea")) @[ifu_bp_ctl.scala 414:95] - node _T_1279 = and(_T_1278, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1280 = bits(_T_1279, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1278 = eq(btb_wr_addr, UInt<8>("h0ea")) @[ifu_bp_ctl.scala 415:95] + node _T_1279 = and(_T_1278, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1280 = bits(_T_1279, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_244 of rvclkhdr_338 @[lib.scala 352:23] rvclkhdr_244.clock <= clock rvclkhdr_244.reset <= reset @@ -32547,9 +32547,9 @@ circuit quasar_wrapper : rvclkhdr_244.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_234 : UInt, rvclkhdr_244.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_234 <= btb_wr_data @[lib.scala 358:16] - node _T_1281 = eq(btb_wr_addr, UInt<8>("h0eb")) @[ifu_bp_ctl.scala 414:95] - node _T_1282 = and(_T_1281, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1283 = bits(_T_1282, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1281 = eq(btb_wr_addr, UInt<8>("h0eb")) @[ifu_bp_ctl.scala 415:95] + node _T_1282 = and(_T_1281, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1283 = bits(_T_1282, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_245 of rvclkhdr_339 @[lib.scala 352:23] rvclkhdr_245.clock <= clock rvclkhdr_245.reset <= reset @@ -32558,9 +32558,9 @@ circuit quasar_wrapper : rvclkhdr_245.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_235 : UInt, rvclkhdr_245.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_235 <= btb_wr_data @[lib.scala 358:16] - node _T_1284 = eq(btb_wr_addr, UInt<8>("h0ec")) @[ifu_bp_ctl.scala 414:95] - node _T_1285 = and(_T_1284, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1286 = bits(_T_1285, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1284 = eq(btb_wr_addr, UInt<8>("h0ec")) @[ifu_bp_ctl.scala 415:95] + node _T_1285 = and(_T_1284, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1286 = bits(_T_1285, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_246 of rvclkhdr_340 @[lib.scala 352:23] rvclkhdr_246.clock <= clock rvclkhdr_246.reset <= reset @@ -32569,9 +32569,9 @@ circuit quasar_wrapper : rvclkhdr_246.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_236 : UInt, rvclkhdr_246.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_236 <= btb_wr_data @[lib.scala 358:16] - node _T_1287 = eq(btb_wr_addr, UInt<8>("h0ed")) @[ifu_bp_ctl.scala 414:95] - node _T_1288 = and(_T_1287, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1289 = bits(_T_1288, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1287 = eq(btb_wr_addr, UInt<8>("h0ed")) @[ifu_bp_ctl.scala 415:95] + node _T_1288 = and(_T_1287, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1289 = bits(_T_1288, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_247 of rvclkhdr_341 @[lib.scala 352:23] rvclkhdr_247.clock <= clock rvclkhdr_247.reset <= reset @@ -32580,9 +32580,9 @@ circuit quasar_wrapper : rvclkhdr_247.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_237 : UInt, rvclkhdr_247.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_237 <= btb_wr_data @[lib.scala 358:16] - node _T_1290 = eq(btb_wr_addr, UInt<8>("h0ee")) @[ifu_bp_ctl.scala 414:95] - node _T_1291 = and(_T_1290, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1292 = bits(_T_1291, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1290 = eq(btb_wr_addr, UInt<8>("h0ee")) @[ifu_bp_ctl.scala 415:95] + node _T_1291 = and(_T_1290, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1292 = bits(_T_1291, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_248 of rvclkhdr_342 @[lib.scala 352:23] rvclkhdr_248.clock <= clock rvclkhdr_248.reset <= reset @@ -32591,9 +32591,9 @@ circuit quasar_wrapper : rvclkhdr_248.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_238 : UInt, rvclkhdr_248.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_238 <= btb_wr_data @[lib.scala 358:16] - node _T_1293 = eq(btb_wr_addr, UInt<8>("h0ef")) @[ifu_bp_ctl.scala 414:95] - node _T_1294 = and(_T_1293, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1295 = bits(_T_1294, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1293 = eq(btb_wr_addr, UInt<8>("h0ef")) @[ifu_bp_ctl.scala 415:95] + node _T_1294 = and(_T_1293, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1295 = bits(_T_1294, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_249 of rvclkhdr_343 @[lib.scala 352:23] rvclkhdr_249.clock <= clock rvclkhdr_249.reset <= reset @@ -32602,9 +32602,9 @@ circuit quasar_wrapper : rvclkhdr_249.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_239 : UInt, rvclkhdr_249.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_239 <= btb_wr_data @[lib.scala 358:16] - node _T_1296 = eq(btb_wr_addr, UInt<8>("h0f0")) @[ifu_bp_ctl.scala 414:95] - node _T_1297 = and(_T_1296, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1298 = bits(_T_1297, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1296 = eq(btb_wr_addr, UInt<8>("h0f0")) @[ifu_bp_ctl.scala 415:95] + node _T_1297 = and(_T_1296, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1298 = bits(_T_1297, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_250 of rvclkhdr_344 @[lib.scala 352:23] rvclkhdr_250.clock <= clock rvclkhdr_250.reset <= reset @@ -32613,9 +32613,9 @@ circuit quasar_wrapper : rvclkhdr_250.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_240 : UInt, rvclkhdr_250.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_240 <= btb_wr_data @[lib.scala 358:16] - node _T_1299 = eq(btb_wr_addr, UInt<8>("h0f1")) @[ifu_bp_ctl.scala 414:95] - node _T_1300 = and(_T_1299, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1301 = bits(_T_1300, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1299 = eq(btb_wr_addr, UInt<8>("h0f1")) @[ifu_bp_ctl.scala 415:95] + node _T_1300 = and(_T_1299, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1301 = bits(_T_1300, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_251 of rvclkhdr_345 @[lib.scala 352:23] rvclkhdr_251.clock <= clock rvclkhdr_251.reset <= reset @@ -32624,9 +32624,9 @@ circuit quasar_wrapper : rvclkhdr_251.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_241 : UInt, rvclkhdr_251.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_241 <= btb_wr_data @[lib.scala 358:16] - node _T_1302 = eq(btb_wr_addr, UInt<8>("h0f2")) @[ifu_bp_ctl.scala 414:95] - node _T_1303 = and(_T_1302, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1304 = bits(_T_1303, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1302 = eq(btb_wr_addr, UInt<8>("h0f2")) @[ifu_bp_ctl.scala 415:95] + node _T_1303 = and(_T_1302, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1304 = bits(_T_1303, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_252 of rvclkhdr_346 @[lib.scala 352:23] rvclkhdr_252.clock <= clock rvclkhdr_252.reset <= reset @@ -32635,9 +32635,9 @@ circuit quasar_wrapper : rvclkhdr_252.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_242 : UInt, rvclkhdr_252.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_242 <= btb_wr_data @[lib.scala 358:16] - node _T_1305 = eq(btb_wr_addr, UInt<8>("h0f3")) @[ifu_bp_ctl.scala 414:95] - node _T_1306 = and(_T_1305, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1307 = bits(_T_1306, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1305 = eq(btb_wr_addr, UInt<8>("h0f3")) @[ifu_bp_ctl.scala 415:95] + node _T_1306 = and(_T_1305, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1307 = bits(_T_1306, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_253 of rvclkhdr_347 @[lib.scala 352:23] rvclkhdr_253.clock <= clock rvclkhdr_253.reset <= reset @@ -32646,9 +32646,9 @@ circuit quasar_wrapper : rvclkhdr_253.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_243 : UInt, rvclkhdr_253.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_243 <= btb_wr_data @[lib.scala 358:16] - node _T_1308 = eq(btb_wr_addr, UInt<8>("h0f4")) @[ifu_bp_ctl.scala 414:95] - node _T_1309 = and(_T_1308, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1310 = bits(_T_1309, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1308 = eq(btb_wr_addr, UInt<8>("h0f4")) @[ifu_bp_ctl.scala 415:95] + node _T_1309 = and(_T_1308, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1310 = bits(_T_1309, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_254 of rvclkhdr_348 @[lib.scala 352:23] rvclkhdr_254.clock <= clock rvclkhdr_254.reset <= reset @@ -32657,9 +32657,9 @@ circuit quasar_wrapper : rvclkhdr_254.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_244 : UInt, rvclkhdr_254.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_244 <= btb_wr_data @[lib.scala 358:16] - node _T_1311 = eq(btb_wr_addr, UInt<8>("h0f5")) @[ifu_bp_ctl.scala 414:95] - node _T_1312 = and(_T_1311, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1313 = bits(_T_1312, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1311 = eq(btb_wr_addr, UInt<8>("h0f5")) @[ifu_bp_ctl.scala 415:95] + node _T_1312 = and(_T_1311, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1313 = bits(_T_1312, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_255 of rvclkhdr_349 @[lib.scala 352:23] rvclkhdr_255.clock <= clock rvclkhdr_255.reset <= reset @@ -32668,9 +32668,9 @@ circuit quasar_wrapper : rvclkhdr_255.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_245 : UInt, rvclkhdr_255.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_245 <= btb_wr_data @[lib.scala 358:16] - node _T_1314 = eq(btb_wr_addr, UInt<8>("h0f6")) @[ifu_bp_ctl.scala 414:95] - node _T_1315 = and(_T_1314, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1316 = bits(_T_1315, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1314 = eq(btb_wr_addr, UInt<8>("h0f6")) @[ifu_bp_ctl.scala 415:95] + node _T_1315 = and(_T_1314, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1316 = bits(_T_1315, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_256 of rvclkhdr_350 @[lib.scala 352:23] rvclkhdr_256.clock <= clock rvclkhdr_256.reset <= reset @@ -32679,9 +32679,9 @@ circuit quasar_wrapper : rvclkhdr_256.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_246 : UInt, rvclkhdr_256.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_246 <= btb_wr_data @[lib.scala 358:16] - node _T_1317 = eq(btb_wr_addr, UInt<8>("h0f7")) @[ifu_bp_ctl.scala 414:95] - node _T_1318 = and(_T_1317, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1319 = bits(_T_1318, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1317 = eq(btb_wr_addr, UInt<8>("h0f7")) @[ifu_bp_ctl.scala 415:95] + node _T_1318 = and(_T_1317, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1319 = bits(_T_1318, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_257 of rvclkhdr_351 @[lib.scala 352:23] rvclkhdr_257.clock <= clock rvclkhdr_257.reset <= reset @@ -32690,9 +32690,9 @@ circuit quasar_wrapper : rvclkhdr_257.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_247 : UInt, rvclkhdr_257.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_247 <= btb_wr_data @[lib.scala 358:16] - node _T_1320 = eq(btb_wr_addr, UInt<8>("h0f8")) @[ifu_bp_ctl.scala 414:95] - node _T_1321 = and(_T_1320, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1322 = bits(_T_1321, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1320 = eq(btb_wr_addr, UInt<8>("h0f8")) @[ifu_bp_ctl.scala 415:95] + node _T_1321 = and(_T_1320, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1322 = bits(_T_1321, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_258 of rvclkhdr_352 @[lib.scala 352:23] rvclkhdr_258.clock <= clock rvclkhdr_258.reset <= reset @@ -32701,9 +32701,9 @@ circuit quasar_wrapper : rvclkhdr_258.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_248 : UInt, rvclkhdr_258.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_248 <= btb_wr_data @[lib.scala 358:16] - node _T_1323 = eq(btb_wr_addr, UInt<8>("h0f9")) @[ifu_bp_ctl.scala 414:95] - node _T_1324 = and(_T_1323, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1325 = bits(_T_1324, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1323 = eq(btb_wr_addr, UInt<8>("h0f9")) @[ifu_bp_ctl.scala 415:95] + node _T_1324 = and(_T_1323, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1325 = bits(_T_1324, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_259 of rvclkhdr_353 @[lib.scala 352:23] rvclkhdr_259.clock <= clock rvclkhdr_259.reset <= reset @@ -32712,9 +32712,9 @@ circuit quasar_wrapper : rvclkhdr_259.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_249 : UInt, rvclkhdr_259.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_249 <= btb_wr_data @[lib.scala 358:16] - node _T_1326 = eq(btb_wr_addr, UInt<8>("h0fa")) @[ifu_bp_ctl.scala 414:95] - node _T_1327 = and(_T_1326, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1328 = bits(_T_1327, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1326 = eq(btb_wr_addr, UInt<8>("h0fa")) @[ifu_bp_ctl.scala 415:95] + node _T_1327 = and(_T_1326, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1328 = bits(_T_1327, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_260 of rvclkhdr_354 @[lib.scala 352:23] rvclkhdr_260.clock <= clock rvclkhdr_260.reset <= reset @@ -32723,9 +32723,9 @@ circuit quasar_wrapper : rvclkhdr_260.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_250 : UInt, rvclkhdr_260.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_250 <= btb_wr_data @[lib.scala 358:16] - node _T_1329 = eq(btb_wr_addr, UInt<8>("h0fb")) @[ifu_bp_ctl.scala 414:95] - node _T_1330 = and(_T_1329, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1331 = bits(_T_1330, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1329 = eq(btb_wr_addr, UInt<8>("h0fb")) @[ifu_bp_ctl.scala 415:95] + node _T_1330 = and(_T_1329, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1331 = bits(_T_1330, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_261 of rvclkhdr_355 @[lib.scala 352:23] rvclkhdr_261.clock <= clock rvclkhdr_261.reset <= reset @@ -32734,9 +32734,9 @@ circuit quasar_wrapper : rvclkhdr_261.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_251 : UInt, rvclkhdr_261.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_251 <= btb_wr_data @[lib.scala 358:16] - node _T_1332 = eq(btb_wr_addr, UInt<8>("h0fc")) @[ifu_bp_ctl.scala 414:95] - node _T_1333 = and(_T_1332, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1334 = bits(_T_1333, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1332 = eq(btb_wr_addr, UInt<8>("h0fc")) @[ifu_bp_ctl.scala 415:95] + node _T_1333 = and(_T_1332, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1334 = bits(_T_1333, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_262 of rvclkhdr_356 @[lib.scala 352:23] rvclkhdr_262.clock <= clock rvclkhdr_262.reset <= reset @@ -32745,9 +32745,9 @@ circuit quasar_wrapper : rvclkhdr_262.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_252 : UInt, rvclkhdr_262.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_252 <= btb_wr_data @[lib.scala 358:16] - node _T_1335 = eq(btb_wr_addr, UInt<8>("h0fd")) @[ifu_bp_ctl.scala 414:95] - node _T_1336 = and(_T_1335, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1337 = bits(_T_1336, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1335 = eq(btb_wr_addr, UInt<8>("h0fd")) @[ifu_bp_ctl.scala 415:95] + node _T_1336 = and(_T_1335, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1337 = bits(_T_1336, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_263 of rvclkhdr_357 @[lib.scala 352:23] rvclkhdr_263.clock <= clock rvclkhdr_263.reset <= reset @@ -32756,9 +32756,9 @@ circuit quasar_wrapper : rvclkhdr_263.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_253 : UInt, rvclkhdr_263.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_253 <= btb_wr_data @[lib.scala 358:16] - node _T_1338 = eq(btb_wr_addr, UInt<8>("h0fe")) @[ifu_bp_ctl.scala 414:95] - node _T_1339 = and(_T_1338, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1340 = bits(_T_1339, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1338 = eq(btb_wr_addr, UInt<8>("h0fe")) @[ifu_bp_ctl.scala 415:95] + node _T_1339 = and(_T_1338, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1340 = bits(_T_1339, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_264 of rvclkhdr_358 @[lib.scala 352:23] rvclkhdr_264.clock <= clock rvclkhdr_264.reset <= reset @@ -32767,9 +32767,9 @@ circuit quasar_wrapper : rvclkhdr_264.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_254 : UInt, rvclkhdr_264.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_254 <= btb_wr_data @[lib.scala 358:16] - node _T_1341 = eq(btb_wr_addr, UInt<8>("h0ff")) @[ifu_bp_ctl.scala 414:95] - node _T_1342 = and(_T_1341, btb_wr_en_way0) @[ifu_bp_ctl.scala 414:103] - node _T_1343 = bits(_T_1342, 0, 0) @[ifu_bp_ctl.scala 414:121] + node _T_1341 = eq(btb_wr_addr, UInt<8>("h0ff")) @[ifu_bp_ctl.scala 415:95] + node _T_1342 = and(_T_1341, btb_wr_en_way0) @[ifu_bp_ctl.scala 415:103] + node _T_1343 = bits(_T_1342, 0, 0) @[ifu_bp_ctl.scala 415:121] inst rvclkhdr_265 of rvclkhdr_359 @[lib.scala 352:23] rvclkhdr_265.clock <= clock rvclkhdr_265.reset <= reset @@ -32778,9 +32778,9 @@ circuit quasar_wrapper : rvclkhdr_265.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way0_out_255 : UInt, rvclkhdr_265.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way0_out_255 <= btb_wr_data @[lib.scala 358:16] - node _T_1344 = eq(btb_wr_addr, UInt<1>("h00")) @[ifu_bp_ctl.scala 415:95] - node _T_1345 = and(_T_1344, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1346 = bits(_T_1345, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1344 = eq(btb_wr_addr, UInt<1>("h00")) @[ifu_bp_ctl.scala 416:95] + node _T_1345 = and(_T_1344, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1346 = bits(_T_1345, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_266 of rvclkhdr_360 @[lib.scala 352:23] rvclkhdr_266.clock <= clock rvclkhdr_266.reset <= reset @@ -32789,9 +32789,9 @@ circuit quasar_wrapper : rvclkhdr_266.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_0 : UInt, rvclkhdr_266.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_0 <= btb_wr_data @[lib.scala 358:16] - node _T_1347 = eq(btb_wr_addr, UInt<1>("h01")) @[ifu_bp_ctl.scala 415:95] - node _T_1348 = and(_T_1347, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1349 = bits(_T_1348, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1347 = eq(btb_wr_addr, UInt<1>("h01")) @[ifu_bp_ctl.scala 416:95] + node _T_1348 = and(_T_1347, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1349 = bits(_T_1348, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_267 of rvclkhdr_361 @[lib.scala 352:23] rvclkhdr_267.clock <= clock rvclkhdr_267.reset <= reset @@ -32800,9 +32800,9 @@ circuit quasar_wrapper : rvclkhdr_267.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_1 : UInt, rvclkhdr_267.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_1 <= btb_wr_data @[lib.scala 358:16] - node _T_1350 = eq(btb_wr_addr, UInt<2>("h02")) @[ifu_bp_ctl.scala 415:95] - node _T_1351 = and(_T_1350, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1352 = bits(_T_1351, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1350 = eq(btb_wr_addr, UInt<2>("h02")) @[ifu_bp_ctl.scala 416:95] + node _T_1351 = and(_T_1350, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1352 = bits(_T_1351, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_268 of rvclkhdr_362 @[lib.scala 352:23] rvclkhdr_268.clock <= clock rvclkhdr_268.reset <= reset @@ -32811,9 +32811,9 @@ circuit quasar_wrapper : rvclkhdr_268.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_2 : UInt, rvclkhdr_268.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_2 <= btb_wr_data @[lib.scala 358:16] - node _T_1353 = eq(btb_wr_addr, UInt<2>("h03")) @[ifu_bp_ctl.scala 415:95] - node _T_1354 = and(_T_1353, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1355 = bits(_T_1354, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1353 = eq(btb_wr_addr, UInt<2>("h03")) @[ifu_bp_ctl.scala 416:95] + node _T_1354 = and(_T_1353, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1355 = bits(_T_1354, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_269 of rvclkhdr_363 @[lib.scala 352:23] rvclkhdr_269.clock <= clock rvclkhdr_269.reset <= reset @@ -32822,9 +32822,9 @@ circuit quasar_wrapper : rvclkhdr_269.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_3 : UInt, rvclkhdr_269.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_3 <= btb_wr_data @[lib.scala 358:16] - node _T_1356 = eq(btb_wr_addr, UInt<3>("h04")) @[ifu_bp_ctl.scala 415:95] - node _T_1357 = and(_T_1356, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1358 = bits(_T_1357, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1356 = eq(btb_wr_addr, UInt<3>("h04")) @[ifu_bp_ctl.scala 416:95] + node _T_1357 = and(_T_1356, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1358 = bits(_T_1357, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_270 of rvclkhdr_364 @[lib.scala 352:23] rvclkhdr_270.clock <= clock rvclkhdr_270.reset <= reset @@ -32833,9 +32833,9 @@ circuit quasar_wrapper : rvclkhdr_270.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_4 : UInt, rvclkhdr_270.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_4 <= btb_wr_data @[lib.scala 358:16] - node _T_1359 = eq(btb_wr_addr, UInt<3>("h05")) @[ifu_bp_ctl.scala 415:95] - node _T_1360 = and(_T_1359, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1361 = bits(_T_1360, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1359 = eq(btb_wr_addr, UInt<3>("h05")) @[ifu_bp_ctl.scala 416:95] + node _T_1360 = and(_T_1359, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1361 = bits(_T_1360, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_271 of rvclkhdr_365 @[lib.scala 352:23] rvclkhdr_271.clock <= clock rvclkhdr_271.reset <= reset @@ -32844,9 +32844,9 @@ circuit quasar_wrapper : rvclkhdr_271.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_5 : UInt, rvclkhdr_271.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_5 <= btb_wr_data @[lib.scala 358:16] - node _T_1362 = eq(btb_wr_addr, UInt<3>("h06")) @[ifu_bp_ctl.scala 415:95] - node _T_1363 = and(_T_1362, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1364 = bits(_T_1363, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1362 = eq(btb_wr_addr, UInt<3>("h06")) @[ifu_bp_ctl.scala 416:95] + node _T_1363 = and(_T_1362, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1364 = bits(_T_1363, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_272 of rvclkhdr_366 @[lib.scala 352:23] rvclkhdr_272.clock <= clock rvclkhdr_272.reset <= reset @@ -32855,9 +32855,9 @@ circuit quasar_wrapper : rvclkhdr_272.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_6 : UInt, rvclkhdr_272.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_6 <= btb_wr_data @[lib.scala 358:16] - node _T_1365 = eq(btb_wr_addr, UInt<3>("h07")) @[ifu_bp_ctl.scala 415:95] - node _T_1366 = and(_T_1365, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1367 = bits(_T_1366, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1365 = eq(btb_wr_addr, UInt<3>("h07")) @[ifu_bp_ctl.scala 416:95] + node _T_1366 = and(_T_1365, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1367 = bits(_T_1366, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_273 of rvclkhdr_367 @[lib.scala 352:23] rvclkhdr_273.clock <= clock rvclkhdr_273.reset <= reset @@ -32866,9 +32866,9 @@ circuit quasar_wrapper : rvclkhdr_273.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_7 : UInt, rvclkhdr_273.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_7 <= btb_wr_data @[lib.scala 358:16] - node _T_1368 = eq(btb_wr_addr, UInt<4>("h08")) @[ifu_bp_ctl.scala 415:95] - node _T_1369 = and(_T_1368, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1370 = bits(_T_1369, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1368 = eq(btb_wr_addr, UInt<4>("h08")) @[ifu_bp_ctl.scala 416:95] + node _T_1369 = and(_T_1368, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1370 = bits(_T_1369, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_274 of rvclkhdr_368 @[lib.scala 352:23] rvclkhdr_274.clock <= clock rvclkhdr_274.reset <= reset @@ -32877,9 +32877,9 @@ circuit quasar_wrapper : rvclkhdr_274.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_8 : UInt, rvclkhdr_274.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_8 <= btb_wr_data @[lib.scala 358:16] - node _T_1371 = eq(btb_wr_addr, UInt<4>("h09")) @[ifu_bp_ctl.scala 415:95] - node _T_1372 = and(_T_1371, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1373 = bits(_T_1372, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1371 = eq(btb_wr_addr, UInt<4>("h09")) @[ifu_bp_ctl.scala 416:95] + node _T_1372 = and(_T_1371, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1373 = bits(_T_1372, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_275 of rvclkhdr_369 @[lib.scala 352:23] rvclkhdr_275.clock <= clock rvclkhdr_275.reset <= reset @@ -32888,9 +32888,9 @@ circuit quasar_wrapper : rvclkhdr_275.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_9 : UInt, rvclkhdr_275.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_9 <= btb_wr_data @[lib.scala 358:16] - node _T_1374 = eq(btb_wr_addr, UInt<4>("h0a")) @[ifu_bp_ctl.scala 415:95] - node _T_1375 = and(_T_1374, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1376 = bits(_T_1375, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1374 = eq(btb_wr_addr, UInt<4>("h0a")) @[ifu_bp_ctl.scala 416:95] + node _T_1375 = and(_T_1374, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1376 = bits(_T_1375, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_276 of rvclkhdr_370 @[lib.scala 352:23] rvclkhdr_276.clock <= clock rvclkhdr_276.reset <= reset @@ -32899,9 +32899,9 @@ circuit quasar_wrapper : rvclkhdr_276.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_10 : UInt, rvclkhdr_276.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_10 <= btb_wr_data @[lib.scala 358:16] - node _T_1377 = eq(btb_wr_addr, UInt<4>("h0b")) @[ifu_bp_ctl.scala 415:95] - node _T_1378 = and(_T_1377, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1379 = bits(_T_1378, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1377 = eq(btb_wr_addr, UInt<4>("h0b")) @[ifu_bp_ctl.scala 416:95] + node _T_1378 = and(_T_1377, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1379 = bits(_T_1378, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_277 of rvclkhdr_371 @[lib.scala 352:23] rvclkhdr_277.clock <= clock rvclkhdr_277.reset <= reset @@ -32910,9 +32910,9 @@ circuit quasar_wrapper : rvclkhdr_277.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_11 : UInt, rvclkhdr_277.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_11 <= btb_wr_data @[lib.scala 358:16] - node _T_1380 = eq(btb_wr_addr, UInt<4>("h0c")) @[ifu_bp_ctl.scala 415:95] - node _T_1381 = and(_T_1380, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1382 = bits(_T_1381, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1380 = eq(btb_wr_addr, UInt<4>("h0c")) @[ifu_bp_ctl.scala 416:95] + node _T_1381 = and(_T_1380, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1382 = bits(_T_1381, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_278 of rvclkhdr_372 @[lib.scala 352:23] rvclkhdr_278.clock <= clock rvclkhdr_278.reset <= reset @@ -32921,9 +32921,9 @@ circuit quasar_wrapper : rvclkhdr_278.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_12 : UInt, rvclkhdr_278.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_12 <= btb_wr_data @[lib.scala 358:16] - node _T_1383 = eq(btb_wr_addr, UInt<4>("h0d")) @[ifu_bp_ctl.scala 415:95] - node _T_1384 = and(_T_1383, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1385 = bits(_T_1384, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1383 = eq(btb_wr_addr, UInt<4>("h0d")) @[ifu_bp_ctl.scala 416:95] + node _T_1384 = and(_T_1383, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1385 = bits(_T_1384, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_279 of rvclkhdr_373 @[lib.scala 352:23] rvclkhdr_279.clock <= clock rvclkhdr_279.reset <= reset @@ -32932,9 +32932,9 @@ circuit quasar_wrapper : rvclkhdr_279.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_13 : UInt, rvclkhdr_279.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_13 <= btb_wr_data @[lib.scala 358:16] - node _T_1386 = eq(btb_wr_addr, UInt<4>("h0e")) @[ifu_bp_ctl.scala 415:95] - node _T_1387 = and(_T_1386, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1388 = bits(_T_1387, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1386 = eq(btb_wr_addr, UInt<4>("h0e")) @[ifu_bp_ctl.scala 416:95] + node _T_1387 = and(_T_1386, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1388 = bits(_T_1387, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_280 of rvclkhdr_374 @[lib.scala 352:23] rvclkhdr_280.clock <= clock rvclkhdr_280.reset <= reset @@ -32943,9 +32943,9 @@ circuit quasar_wrapper : rvclkhdr_280.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_14 : UInt, rvclkhdr_280.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_14 <= btb_wr_data @[lib.scala 358:16] - node _T_1389 = eq(btb_wr_addr, UInt<4>("h0f")) @[ifu_bp_ctl.scala 415:95] - node _T_1390 = and(_T_1389, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1391 = bits(_T_1390, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1389 = eq(btb_wr_addr, UInt<4>("h0f")) @[ifu_bp_ctl.scala 416:95] + node _T_1390 = and(_T_1389, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1391 = bits(_T_1390, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_281 of rvclkhdr_375 @[lib.scala 352:23] rvclkhdr_281.clock <= clock rvclkhdr_281.reset <= reset @@ -32954,9 +32954,9 @@ circuit quasar_wrapper : rvclkhdr_281.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_15 : UInt, rvclkhdr_281.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_15 <= btb_wr_data @[lib.scala 358:16] - node _T_1392 = eq(btb_wr_addr, UInt<5>("h010")) @[ifu_bp_ctl.scala 415:95] - node _T_1393 = and(_T_1392, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1394 = bits(_T_1393, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1392 = eq(btb_wr_addr, UInt<5>("h010")) @[ifu_bp_ctl.scala 416:95] + node _T_1393 = and(_T_1392, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1394 = bits(_T_1393, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_282 of rvclkhdr_376 @[lib.scala 352:23] rvclkhdr_282.clock <= clock rvclkhdr_282.reset <= reset @@ -32965,9 +32965,9 @@ circuit quasar_wrapper : rvclkhdr_282.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_16 : UInt, rvclkhdr_282.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_16 <= btb_wr_data @[lib.scala 358:16] - node _T_1395 = eq(btb_wr_addr, UInt<5>("h011")) @[ifu_bp_ctl.scala 415:95] - node _T_1396 = and(_T_1395, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1397 = bits(_T_1396, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1395 = eq(btb_wr_addr, UInt<5>("h011")) @[ifu_bp_ctl.scala 416:95] + node _T_1396 = and(_T_1395, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1397 = bits(_T_1396, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_283 of rvclkhdr_377 @[lib.scala 352:23] rvclkhdr_283.clock <= clock rvclkhdr_283.reset <= reset @@ -32976,9 +32976,9 @@ circuit quasar_wrapper : rvclkhdr_283.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_17 : UInt, rvclkhdr_283.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_17 <= btb_wr_data @[lib.scala 358:16] - node _T_1398 = eq(btb_wr_addr, UInt<5>("h012")) @[ifu_bp_ctl.scala 415:95] - node _T_1399 = and(_T_1398, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1400 = bits(_T_1399, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1398 = eq(btb_wr_addr, UInt<5>("h012")) @[ifu_bp_ctl.scala 416:95] + node _T_1399 = and(_T_1398, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1400 = bits(_T_1399, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_284 of rvclkhdr_378 @[lib.scala 352:23] rvclkhdr_284.clock <= clock rvclkhdr_284.reset <= reset @@ -32987,9 +32987,9 @@ circuit quasar_wrapper : rvclkhdr_284.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_18 : UInt, rvclkhdr_284.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_18 <= btb_wr_data @[lib.scala 358:16] - node _T_1401 = eq(btb_wr_addr, UInt<5>("h013")) @[ifu_bp_ctl.scala 415:95] - node _T_1402 = and(_T_1401, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1403 = bits(_T_1402, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1401 = eq(btb_wr_addr, UInt<5>("h013")) @[ifu_bp_ctl.scala 416:95] + node _T_1402 = and(_T_1401, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1403 = bits(_T_1402, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_285 of rvclkhdr_379 @[lib.scala 352:23] rvclkhdr_285.clock <= clock rvclkhdr_285.reset <= reset @@ -32998,9 +32998,9 @@ circuit quasar_wrapper : rvclkhdr_285.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_19 : UInt, rvclkhdr_285.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_19 <= btb_wr_data @[lib.scala 358:16] - node _T_1404 = eq(btb_wr_addr, UInt<5>("h014")) @[ifu_bp_ctl.scala 415:95] - node _T_1405 = and(_T_1404, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1406 = bits(_T_1405, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1404 = eq(btb_wr_addr, UInt<5>("h014")) @[ifu_bp_ctl.scala 416:95] + node _T_1405 = and(_T_1404, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1406 = bits(_T_1405, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_286 of rvclkhdr_380 @[lib.scala 352:23] rvclkhdr_286.clock <= clock rvclkhdr_286.reset <= reset @@ -33009,9 +33009,9 @@ circuit quasar_wrapper : rvclkhdr_286.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_20 : UInt, rvclkhdr_286.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_20 <= btb_wr_data @[lib.scala 358:16] - node _T_1407 = eq(btb_wr_addr, UInt<5>("h015")) @[ifu_bp_ctl.scala 415:95] - node _T_1408 = and(_T_1407, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1409 = bits(_T_1408, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1407 = eq(btb_wr_addr, UInt<5>("h015")) @[ifu_bp_ctl.scala 416:95] + node _T_1408 = and(_T_1407, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1409 = bits(_T_1408, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_287 of rvclkhdr_381 @[lib.scala 352:23] rvclkhdr_287.clock <= clock rvclkhdr_287.reset <= reset @@ -33020,9 +33020,9 @@ circuit quasar_wrapper : rvclkhdr_287.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_21 : UInt, rvclkhdr_287.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_21 <= btb_wr_data @[lib.scala 358:16] - node _T_1410 = eq(btb_wr_addr, UInt<5>("h016")) @[ifu_bp_ctl.scala 415:95] - node _T_1411 = and(_T_1410, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1412 = bits(_T_1411, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1410 = eq(btb_wr_addr, UInt<5>("h016")) @[ifu_bp_ctl.scala 416:95] + node _T_1411 = and(_T_1410, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1412 = bits(_T_1411, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_288 of rvclkhdr_382 @[lib.scala 352:23] rvclkhdr_288.clock <= clock rvclkhdr_288.reset <= reset @@ -33031,9 +33031,9 @@ circuit quasar_wrapper : rvclkhdr_288.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_22 : UInt, rvclkhdr_288.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_22 <= btb_wr_data @[lib.scala 358:16] - node _T_1413 = eq(btb_wr_addr, UInt<5>("h017")) @[ifu_bp_ctl.scala 415:95] - node _T_1414 = and(_T_1413, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1415 = bits(_T_1414, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1413 = eq(btb_wr_addr, UInt<5>("h017")) @[ifu_bp_ctl.scala 416:95] + node _T_1414 = and(_T_1413, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1415 = bits(_T_1414, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_289 of rvclkhdr_383 @[lib.scala 352:23] rvclkhdr_289.clock <= clock rvclkhdr_289.reset <= reset @@ -33042,9 +33042,9 @@ circuit quasar_wrapper : rvclkhdr_289.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_23 : UInt, rvclkhdr_289.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_23 <= btb_wr_data @[lib.scala 358:16] - node _T_1416 = eq(btb_wr_addr, UInt<5>("h018")) @[ifu_bp_ctl.scala 415:95] - node _T_1417 = and(_T_1416, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1418 = bits(_T_1417, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1416 = eq(btb_wr_addr, UInt<5>("h018")) @[ifu_bp_ctl.scala 416:95] + node _T_1417 = and(_T_1416, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1418 = bits(_T_1417, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_290 of rvclkhdr_384 @[lib.scala 352:23] rvclkhdr_290.clock <= clock rvclkhdr_290.reset <= reset @@ -33053,9 +33053,9 @@ circuit quasar_wrapper : rvclkhdr_290.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_24 : UInt, rvclkhdr_290.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_24 <= btb_wr_data @[lib.scala 358:16] - node _T_1419 = eq(btb_wr_addr, UInt<5>("h019")) @[ifu_bp_ctl.scala 415:95] - node _T_1420 = and(_T_1419, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1421 = bits(_T_1420, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1419 = eq(btb_wr_addr, UInt<5>("h019")) @[ifu_bp_ctl.scala 416:95] + node _T_1420 = and(_T_1419, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1421 = bits(_T_1420, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_291 of rvclkhdr_385 @[lib.scala 352:23] rvclkhdr_291.clock <= clock rvclkhdr_291.reset <= reset @@ -33064,9 +33064,9 @@ circuit quasar_wrapper : rvclkhdr_291.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_25 : UInt, rvclkhdr_291.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_25 <= btb_wr_data @[lib.scala 358:16] - node _T_1422 = eq(btb_wr_addr, UInt<5>("h01a")) @[ifu_bp_ctl.scala 415:95] - node _T_1423 = and(_T_1422, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1424 = bits(_T_1423, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1422 = eq(btb_wr_addr, UInt<5>("h01a")) @[ifu_bp_ctl.scala 416:95] + node _T_1423 = and(_T_1422, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1424 = bits(_T_1423, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_292 of rvclkhdr_386 @[lib.scala 352:23] rvclkhdr_292.clock <= clock rvclkhdr_292.reset <= reset @@ -33075,9 +33075,9 @@ circuit quasar_wrapper : rvclkhdr_292.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_26 : UInt, rvclkhdr_292.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_26 <= btb_wr_data @[lib.scala 358:16] - node _T_1425 = eq(btb_wr_addr, UInt<5>("h01b")) @[ifu_bp_ctl.scala 415:95] - node _T_1426 = and(_T_1425, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1427 = bits(_T_1426, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1425 = eq(btb_wr_addr, UInt<5>("h01b")) @[ifu_bp_ctl.scala 416:95] + node _T_1426 = and(_T_1425, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1427 = bits(_T_1426, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_293 of rvclkhdr_387 @[lib.scala 352:23] rvclkhdr_293.clock <= clock rvclkhdr_293.reset <= reset @@ -33086,9 +33086,9 @@ circuit quasar_wrapper : rvclkhdr_293.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_27 : UInt, rvclkhdr_293.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_27 <= btb_wr_data @[lib.scala 358:16] - node _T_1428 = eq(btb_wr_addr, UInt<5>("h01c")) @[ifu_bp_ctl.scala 415:95] - node _T_1429 = and(_T_1428, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1430 = bits(_T_1429, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1428 = eq(btb_wr_addr, UInt<5>("h01c")) @[ifu_bp_ctl.scala 416:95] + node _T_1429 = and(_T_1428, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1430 = bits(_T_1429, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_294 of rvclkhdr_388 @[lib.scala 352:23] rvclkhdr_294.clock <= clock rvclkhdr_294.reset <= reset @@ -33097,9 +33097,9 @@ circuit quasar_wrapper : rvclkhdr_294.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_28 : UInt, rvclkhdr_294.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_28 <= btb_wr_data @[lib.scala 358:16] - node _T_1431 = eq(btb_wr_addr, UInt<5>("h01d")) @[ifu_bp_ctl.scala 415:95] - node _T_1432 = and(_T_1431, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1433 = bits(_T_1432, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1431 = eq(btb_wr_addr, UInt<5>("h01d")) @[ifu_bp_ctl.scala 416:95] + node _T_1432 = and(_T_1431, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1433 = bits(_T_1432, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_295 of rvclkhdr_389 @[lib.scala 352:23] rvclkhdr_295.clock <= clock rvclkhdr_295.reset <= reset @@ -33108,9 +33108,9 @@ circuit quasar_wrapper : rvclkhdr_295.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_29 : UInt, rvclkhdr_295.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_29 <= btb_wr_data @[lib.scala 358:16] - node _T_1434 = eq(btb_wr_addr, UInt<5>("h01e")) @[ifu_bp_ctl.scala 415:95] - node _T_1435 = and(_T_1434, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1436 = bits(_T_1435, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1434 = eq(btb_wr_addr, UInt<5>("h01e")) @[ifu_bp_ctl.scala 416:95] + node _T_1435 = and(_T_1434, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1436 = bits(_T_1435, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_296 of rvclkhdr_390 @[lib.scala 352:23] rvclkhdr_296.clock <= clock rvclkhdr_296.reset <= reset @@ -33119,9 +33119,9 @@ circuit quasar_wrapper : rvclkhdr_296.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_30 : UInt, rvclkhdr_296.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_30 <= btb_wr_data @[lib.scala 358:16] - node _T_1437 = eq(btb_wr_addr, UInt<5>("h01f")) @[ifu_bp_ctl.scala 415:95] - node _T_1438 = and(_T_1437, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1439 = bits(_T_1438, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1437 = eq(btb_wr_addr, UInt<5>("h01f")) @[ifu_bp_ctl.scala 416:95] + node _T_1438 = and(_T_1437, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1439 = bits(_T_1438, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_297 of rvclkhdr_391 @[lib.scala 352:23] rvclkhdr_297.clock <= clock rvclkhdr_297.reset <= reset @@ -33130,9 +33130,9 @@ circuit quasar_wrapper : rvclkhdr_297.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_31 : UInt, rvclkhdr_297.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_31 <= btb_wr_data @[lib.scala 358:16] - node _T_1440 = eq(btb_wr_addr, UInt<6>("h020")) @[ifu_bp_ctl.scala 415:95] - node _T_1441 = and(_T_1440, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1442 = bits(_T_1441, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1440 = eq(btb_wr_addr, UInt<6>("h020")) @[ifu_bp_ctl.scala 416:95] + node _T_1441 = and(_T_1440, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1442 = bits(_T_1441, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_298 of rvclkhdr_392 @[lib.scala 352:23] rvclkhdr_298.clock <= clock rvclkhdr_298.reset <= reset @@ -33141,9 +33141,9 @@ circuit quasar_wrapper : rvclkhdr_298.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_32 : UInt, rvclkhdr_298.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_32 <= btb_wr_data @[lib.scala 358:16] - node _T_1443 = eq(btb_wr_addr, UInt<6>("h021")) @[ifu_bp_ctl.scala 415:95] - node _T_1444 = and(_T_1443, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1445 = bits(_T_1444, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1443 = eq(btb_wr_addr, UInt<6>("h021")) @[ifu_bp_ctl.scala 416:95] + node _T_1444 = and(_T_1443, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1445 = bits(_T_1444, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_299 of rvclkhdr_393 @[lib.scala 352:23] rvclkhdr_299.clock <= clock rvclkhdr_299.reset <= reset @@ -33152,9 +33152,9 @@ circuit quasar_wrapper : rvclkhdr_299.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_33 : UInt, rvclkhdr_299.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_33 <= btb_wr_data @[lib.scala 358:16] - node _T_1446 = eq(btb_wr_addr, UInt<6>("h022")) @[ifu_bp_ctl.scala 415:95] - node _T_1447 = and(_T_1446, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1448 = bits(_T_1447, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1446 = eq(btb_wr_addr, UInt<6>("h022")) @[ifu_bp_ctl.scala 416:95] + node _T_1447 = and(_T_1446, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1448 = bits(_T_1447, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_300 of rvclkhdr_394 @[lib.scala 352:23] rvclkhdr_300.clock <= clock rvclkhdr_300.reset <= reset @@ -33163,9 +33163,9 @@ circuit quasar_wrapper : rvclkhdr_300.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_34 : UInt, rvclkhdr_300.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_34 <= btb_wr_data @[lib.scala 358:16] - node _T_1449 = eq(btb_wr_addr, UInt<6>("h023")) @[ifu_bp_ctl.scala 415:95] - node _T_1450 = and(_T_1449, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1451 = bits(_T_1450, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1449 = eq(btb_wr_addr, UInt<6>("h023")) @[ifu_bp_ctl.scala 416:95] + node _T_1450 = and(_T_1449, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1451 = bits(_T_1450, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_301 of rvclkhdr_395 @[lib.scala 352:23] rvclkhdr_301.clock <= clock rvclkhdr_301.reset <= reset @@ -33174,9 +33174,9 @@ circuit quasar_wrapper : rvclkhdr_301.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_35 : UInt, rvclkhdr_301.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_35 <= btb_wr_data @[lib.scala 358:16] - node _T_1452 = eq(btb_wr_addr, UInt<6>("h024")) @[ifu_bp_ctl.scala 415:95] - node _T_1453 = and(_T_1452, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1454 = bits(_T_1453, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1452 = eq(btb_wr_addr, UInt<6>("h024")) @[ifu_bp_ctl.scala 416:95] + node _T_1453 = and(_T_1452, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1454 = bits(_T_1453, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_302 of rvclkhdr_396 @[lib.scala 352:23] rvclkhdr_302.clock <= clock rvclkhdr_302.reset <= reset @@ -33185,9 +33185,9 @@ circuit quasar_wrapper : rvclkhdr_302.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_36 : UInt, rvclkhdr_302.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_36 <= btb_wr_data @[lib.scala 358:16] - node _T_1455 = eq(btb_wr_addr, UInt<6>("h025")) @[ifu_bp_ctl.scala 415:95] - node _T_1456 = and(_T_1455, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1457 = bits(_T_1456, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1455 = eq(btb_wr_addr, UInt<6>("h025")) @[ifu_bp_ctl.scala 416:95] + node _T_1456 = and(_T_1455, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1457 = bits(_T_1456, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_303 of rvclkhdr_397 @[lib.scala 352:23] rvclkhdr_303.clock <= clock rvclkhdr_303.reset <= reset @@ -33196,9 +33196,9 @@ circuit quasar_wrapper : rvclkhdr_303.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_37 : UInt, rvclkhdr_303.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_37 <= btb_wr_data @[lib.scala 358:16] - node _T_1458 = eq(btb_wr_addr, UInt<6>("h026")) @[ifu_bp_ctl.scala 415:95] - node _T_1459 = and(_T_1458, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1460 = bits(_T_1459, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1458 = eq(btb_wr_addr, UInt<6>("h026")) @[ifu_bp_ctl.scala 416:95] + node _T_1459 = and(_T_1458, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1460 = bits(_T_1459, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_304 of rvclkhdr_398 @[lib.scala 352:23] rvclkhdr_304.clock <= clock rvclkhdr_304.reset <= reset @@ -33207,9 +33207,9 @@ circuit quasar_wrapper : rvclkhdr_304.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_38 : UInt, rvclkhdr_304.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_38 <= btb_wr_data @[lib.scala 358:16] - node _T_1461 = eq(btb_wr_addr, UInt<6>("h027")) @[ifu_bp_ctl.scala 415:95] - node _T_1462 = and(_T_1461, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1463 = bits(_T_1462, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1461 = eq(btb_wr_addr, UInt<6>("h027")) @[ifu_bp_ctl.scala 416:95] + node _T_1462 = and(_T_1461, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1463 = bits(_T_1462, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_305 of rvclkhdr_399 @[lib.scala 352:23] rvclkhdr_305.clock <= clock rvclkhdr_305.reset <= reset @@ -33218,9 +33218,9 @@ circuit quasar_wrapper : rvclkhdr_305.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_39 : UInt, rvclkhdr_305.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_39 <= btb_wr_data @[lib.scala 358:16] - node _T_1464 = eq(btb_wr_addr, UInt<6>("h028")) @[ifu_bp_ctl.scala 415:95] - node _T_1465 = and(_T_1464, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1466 = bits(_T_1465, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1464 = eq(btb_wr_addr, UInt<6>("h028")) @[ifu_bp_ctl.scala 416:95] + node _T_1465 = and(_T_1464, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1466 = bits(_T_1465, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_306 of rvclkhdr_400 @[lib.scala 352:23] rvclkhdr_306.clock <= clock rvclkhdr_306.reset <= reset @@ -33229,9 +33229,9 @@ circuit quasar_wrapper : rvclkhdr_306.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_40 : UInt, rvclkhdr_306.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_40 <= btb_wr_data @[lib.scala 358:16] - node _T_1467 = eq(btb_wr_addr, UInt<6>("h029")) @[ifu_bp_ctl.scala 415:95] - node _T_1468 = and(_T_1467, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1469 = bits(_T_1468, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1467 = eq(btb_wr_addr, UInt<6>("h029")) @[ifu_bp_ctl.scala 416:95] + node _T_1468 = and(_T_1467, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1469 = bits(_T_1468, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_307 of rvclkhdr_401 @[lib.scala 352:23] rvclkhdr_307.clock <= clock rvclkhdr_307.reset <= reset @@ -33240,9 +33240,9 @@ circuit quasar_wrapper : rvclkhdr_307.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_41 : UInt, rvclkhdr_307.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_41 <= btb_wr_data @[lib.scala 358:16] - node _T_1470 = eq(btb_wr_addr, UInt<6>("h02a")) @[ifu_bp_ctl.scala 415:95] - node _T_1471 = and(_T_1470, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1472 = bits(_T_1471, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1470 = eq(btb_wr_addr, UInt<6>("h02a")) @[ifu_bp_ctl.scala 416:95] + node _T_1471 = and(_T_1470, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1472 = bits(_T_1471, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_308 of rvclkhdr_402 @[lib.scala 352:23] rvclkhdr_308.clock <= clock rvclkhdr_308.reset <= reset @@ -33251,9 +33251,9 @@ circuit quasar_wrapper : rvclkhdr_308.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_42 : UInt, rvclkhdr_308.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_42 <= btb_wr_data @[lib.scala 358:16] - node _T_1473 = eq(btb_wr_addr, UInt<6>("h02b")) @[ifu_bp_ctl.scala 415:95] - node _T_1474 = and(_T_1473, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1475 = bits(_T_1474, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1473 = eq(btb_wr_addr, UInt<6>("h02b")) @[ifu_bp_ctl.scala 416:95] + node _T_1474 = and(_T_1473, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1475 = bits(_T_1474, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_309 of rvclkhdr_403 @[lib.scala 352:23] rvclkhdr_309.clock <= clock rvclkhdr_309.reset <= reset @@ -33262,9 +33262,9 @@ circuit quasar_wrapper : rvclkhdr_309.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_43 : UInt, rvclkhdr_309.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_43 <= btb_wr_data @[lib.scala 358:16] - node _T_1476 = eq(btb_wr_addr, UInt<6>("h02c")) @[ifu_bp_ctl.scala 415:95] - node _T_1477 = and(_T_1476, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1478 = bits(_T_1477, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1476 = eq(btb_wr_addr, UInt<6>("h02c")) @[ifu_bp_ctl.scala 416:95] + node _T_1477 = and(_T_1476, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1478 = bits(_T_1477, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_310 of rvclkhdr_404 @[lib.scala 352:23] rvclkhdr_310.clock <= clock rvclkhdr_310.reset <= reset @@ -33273,9 +33273,9 @@ circuit quasar_wrapper : rvclkhdr_310.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_44 : UInt, rvclkhdr_310.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_44 <= btb_wr_data @[lib.scala 358:16] - node _T_1479 = eq(btb_wr_addr, UInt<6>("h02d")) @[ifu_bp_ctl.scala 415:95] - node _T_1480 = and(_T_1479, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1481 = bits(_T_1480, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1479 = eq(btb_wr_addr, UInt<6>("h02d")) @[ifu_bp_ctl.scala 416:95] + node _T_1480 = and(_T_1479, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1481 = bits(_T_1480, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_311 of rvclkhdr_405 @[lib.scala 352:23] rvclkhdr_311.clock <= clock rvclkhdr_311.reset <= reset @@ -33284,9 +33284,9 @@ circuit quasar_wrapper : rvclkhdr_311.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_45 : UInt, rvclkhdr_311.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_45 <= btb_wr_data @[lib.scala 358:16] - node _T_1482 = eq(btb_wr_addr, UInt<6>("h02e")) @[ifu_bp_ctl.scala 415:95] - node _T_1483 = and(_T_1482, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1484 = bits(_T_1483, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1482 = eq(btb_wr_addr, UInt<6>("h02e")) @[ifu_bp_ctl.scala 416:95] + node _T_1483 = and(_T_1482, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1484 = bits(_T_1483, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_312 of rvclkhdr_406 @[lib.scala 352:23] rvclkhdr_312.clock <= clock rvclkhdr_312.reset <= reset @@ -33295,9 +33295,9 @@ circuit quasar_wrapper : rvclkhdr_312.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_46 : UInt, rvclkhdr_312.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_46 <= btb_wr_data @[lib.scala 358:16] - node _T_1485 = eq(btb_wr_addr, UInt<6>("h02f")) @[ifu_bp_ctl.scala 415:95] - node _T_1486 = and(_T_1485, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1487 = bits(_T_1486, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1485 = eq(btb_wr_addr, UInt<6>("h02f")) @[ifu_bp_ctl.scala 416:95] + node _T_1486 = and(_T_1485, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1487 = bits(_T_1486, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_313 of rvclkhdr_407 @[lib.scala 352:23] rvclkhdr_313.clock <= clock rvclkhdr_313.reset <= reset @@ -33306,9 +33306,9 @@ circuit quasar_wrapper : rvclkhdr_313.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_47 : UInt, rvclkhdr_313.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_47 <= btb_wr_data @[lib.scala 358:16] - node _T_1488 = eq(btb_wr_addr, UInt<6>("h030")) @[ifu_bp_ctl.scala 415:95] - node _T_1489 = and(_T_1488, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1490 = bits(_T_1489, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1488 = eq(btb_wr_addr, UInt<6>("h030")) @[ifu_bp_ctl.scala 416:95] + node _T_1489 = and(_T_1488, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1490 = bits(_T_1489, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_314 of rvclkhdr_408 @[lib.scala 352:23] rvclkhdr_314.clock <= clock rvclkhdr_314.reset <= reset @@ -33317,9 +33317,9 @@ circuit quasar_wrapper : rvclkhdr_314.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_48 : UInt, rvclkhdr_314.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_48 <= btb_wr_data @[lib.scala 358:16] - node _T_1491 = eq(btb_wr_addr, UInt<6>("h031")) @[ifu_bp_ctl.scala 415:95] - node _T_1492 = and(_T_1491, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1493 = bits(_T_1492, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1491 = eq(btb_wr_addr, UInt<6>("h031")) @[ifu_bp_ctl.scala 416:95] + node _T_1492 = and(_T_1491, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1493 = bits(_T_1492, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_315 of rvclkhdr_409 @[lib.scala 352:23] rvclkhdr_315.clock <= clock rvclkhdr_315.reset <= reset @@ -33328,9 +33328,9 @@ circuit quasar_wrapper : rvclkhdr_315.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_49 : UInt, rvclkhdr_315.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_49 <= btb_wr_data @[lib.scala 358:16] - node _T_1494 = eq(btb_wr_addr, UInt<6>("h032")) @[ifu_bp_ctl.scala 415:95] - node _T_1495 = and(_T_1494, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1496 = bits(_T_1495, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1494 = eq(btb_wr_addr, UInt<6>("h032")) @[ifu_bp_ctl.scala 416:95] + node _T_1495 = and(_T_1494, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1496 = bits(_T_1495, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_316 of rvclkhdr_410 @[lib.scala 352:23] rvclkhdr_316.clock <= clock rvclkhdr_316.reset <= reset @@ -33339,9 +33339,9 @@ circuit quasar_wrapper : rvclkhdr_316.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_50 : UInt, rvclkhdr_316.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_50 <= btb_wr_data @[lib.scala 358:16] - node _T_1497 = eq(btb_wr_addr, UInt<6>("h033")) @[ifu_bp_ctl.scala 415:95] - node _T_1498 = and(_T_1497, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1499 = bits(_T_1498, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1497 = eq(btb_wr_addr, UInt<6>("h033")) @[ifu_bp_ctl.scala 416:95] + node _T_1498 = and(_T_1497, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1499 = bits(_T_1498, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_317 of rvclkhdr_411 @[lib.scala 352:23] rvclkhdr_317.clock <= clock rvclkhdr_317.reset <= reset @@ -33350,9 +33350,9 @@ circuit quasar_wrapper : rvclkhdr_317.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_51 : UInt, rvclkhdr_317.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_51 <= btb_wr_data @[lib.scala 358:16] - node _T_1500 = eq(btb_wr_addr, UInt<6>("h034")) @[ifu_bp_ctl.scala 415:95] - node _T_1501 = and(_T_1500, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1502 = bits(_T_1501, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1500 = eq(btb_wr_addr, UInt<6>("h034")) @[ifu_bp_ctl.scala 416:95] + node _T_1501 = and(_T_1500, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1502 = bits(_T_1501, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_318 of rvclkhdr_412 @[lib.scala 352:23] rvclkhdr_318.clock <= clock rvclkhdr_318.reset <= reset @@ -33361,9 +33361,9 @@ circuit quasar_wrapper : rvclkhdr_318.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_52 : UInt, rvclkhdr_318.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_52 <= btb_wr_data @[lib.scala 358:16] - node _T_1503 = eq(btb_wr_addr, UInt<6>("h035")) @[ifu_bp_ctl.scala 415:95] - node _T_1504 = and(_T_1503, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1505 = bits(_T_1504, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1503 = eq(btb_wr_addr, UInt<6>("h035")) @[ifu_bp_ctl.scala 416:95] + node _T_1504 = and(_T_1503, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1505 = bits(_T_1504, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_319 of rvclkhdr_413 @[lib.scala 352:23] rvclkhdr_319.clock <= clock rvclkhdr_319.reset <= reset @@ -33372,9 +33372,9 @@ circuit quasar_wrapper : rvclkhdr_319.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_53 : UInt, rvclkhdr_319.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_53 <= btb_wr_data @[lib.scala 358:16] - node _T_1506 = eq(btb_wr_addr, UInt<6>("h036")) @[ifu_bp_ctl.scala 415:95] - node _T_1507 = and(_T_1506, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1508 = bits(_T_1507, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1506 = eq(btb_wr_addr, UInt<6>("h036")) @[ifu_bp_ctl.scala 416:95] + node _T_1507 = and(_T_1506, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1508 = bits(_T_1507, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_320 of rvclkhdr_414 @[lib.scala 352:23] rvclkhdr_320.clock <= clock rvclkhdr_320.reset <= reset @@ -33383,9 +33383,9 @@ circuit quasar_wrapper : rvclkhdr_320.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_54 : UInt, rvclkhdr_320.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_54 <= btb_wr_data @[lib.scala 358:16] - node _T_1509 = eq(btb_wr_addr, UInt<6>("h037")) @[ifu_bp_ctl.scala 415:95] - node _T_1510 = and(_T_1509, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1511 = bits(_T_1510, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1509 = eq(btb_wr_addr, UInt<6>("h037")) @[ifu_bp_ctl.scala 416:95] + node _T_1510 = and(_T_1509, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1511 = bits(_T_1510, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_321 of rvclkhdr_415 @[lib.scala 352:23] rvclkhdr_321.clock <= clock rvclkhdr_321.reset <= reset @@ -33394,9 +33394,9 @@ circuit quasar_wrapper : rvclkhdr_321.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_55 : UInt, rvclkhdr_321.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_55 <= btb_wr_data @[lib.scala 358:16] - node _T_1512 = eq(btb_wr_addr, UInt<6>("h038")) @[ifu_bp_ctl.scala 415:95] - node _T_1513 = and(_T_1512, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1514 = bits(_T_1513, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1512 = eq(btb_wr_addr, UInt<6>("h038")) @[ifu_bp_ctl.scala 416:95] + node _T_1513 = and(_T_1512, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1514 = bits(_T_1513, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_322 of rvclkhdr_416 @[lib.scala 352:23] rvclkhdr_322.clock <= clock rvclkhdr_322.reset <= reset @@ -33405,9 +33405,9 @@ circuit quasar_wrapper : rvclkhdr_322.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_56 : UInt, rvclkhdr_322.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_56 <= btb_wr_data @[lib.scala 358:16] - node _T_1515 = eq(btb_wr_addr, UInt<6>("h039")) @[ifu_bp_ctl.scala 415:95] - node _T_1516 = and(_T_1515, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1517 = bits(_T_1516, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1515 = eq(btb_wr_addr, UInt<6>("h039")) @[ifu_bp_ctl.scala 416:95] + node _T_1516 = and(_T_1515, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1517 = bits(_T_1516, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_323 of rvclkhdr_417 @[lib.scala 352:23] rvclkhdr_323.clock <= clock rvclkhdr_323.reset <= reset @@ -33416,9 +33416,9 @@ circuit quasar_wrapper : rvclkhdr_323.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_57 : UInt, rvclkhdr_323.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_57 <= btb_wr_data @[lib.scala 358:16] - node _T_1518 = eq(btb_wr_addr, UInt<6>("h03a")) @[ifu_bp_ctl.scala 415:95] - node _T_1519 = and(_T_1518, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1520 = bits(_T_1519, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1518 = eq(btb_wr_addr, UInt<6>("h03a")) @[ifu_bp_ctl.scala 416:95] + node _T_1519 = and(_T_1518, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1520 = bits(_T_1519, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_324 of rvclkhdr_418 @[lib.scala 352:23] rvclkhdr_324.clock <= clock rvclkhdr_324.reset <= reset @@ -33427,9 +33427,9 @@ circuit quasar_wrapper : rvclkhdr_324.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_58 : UInt, rvclkhdr_324.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_58 <= btb_wr_data @[lib.scala 358:16] - node _T_1521 = eq(btb_wr_addr, UInt<6>("h03b")) @[ifu_bp_ctl.scala 415:95] - node _T_1522 = and(_T_1521, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1523 = bits(_T_1522, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1521 = eq(btb_wr_addr, UInt<6>("h03b")) @[ifu_bp_ctl.scala 416:95] + node _T_1522 = and(_T_1521, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1523 = bits(_T_1522, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_325 of rvclkhdr_419 @[lib.scala 352:23] rvclkhdr_325.clock <= clock rvclkhdr_325.reset <= reset @@ -33438,9 +33438,9 @@ circuit quasar_wrapper : rvclkhdr_325.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_59 : UInt, rvclkhdr_325.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_59 <= btb_wr_data @[lib.scala 358:16] - node _T_1524 = eq(btb_wr_addr, UInt<6>("h03c")) @[ifu_bp_ctl.scala 415:95] - node _T_1525 = and(_T_1524, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1526 = bits(_T_1525, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1524 = eq(btb_wr_addr, UInt<6>("h03c")) @[ifu_bp_ctl.scala 416:95] + node _T_1525 = and(_T_1524, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1526 = bits(_T_1525, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_326 of rvclkhdr_420 @[lib.scala 352:23] rvclkhdr_326.clock <= clock rvclkhdr_326.reset <= reset @@ -33449,9 +33449,9 @@ circuit quasar_wrapper : rvclkhdr_326.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_60 : UInt, rvclkhdr_326.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_60 <= btb_wr_data @[lib.scala 358:16] - node _T_1527 = eq(btb_wr_addr, UInt<6>("h03d")) @[ifu_bp_ctl.scala 415:95] - node _T_1528 = and(_T_1527, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1529 = bits(_T_1528, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1527 = eq(btb_wr_addr, UInt<6>("h03d")) @[ifu_bp_ctl.scala 416:95] + node _T_1528 = and(_T_1527, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1529 = bits(_T_1528, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_327 of rvclkhdr_421 @[lib.scala 352:23] rvclkhdr_327.clock <= clock rvclkhdr_327.reset <= reset @@ -33460,9 +33460,9 @@ circuit quasar_wrapper : rvclkhdr_327.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_61 : UInt, rvclkhdr_327.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_61 <= btb_wr_data @[lib.scala 358:16] - node _T_1530 = eq(btb_wr_addr, UInt<6>("h03e")) @[ifu_bp_ctl.scala 415:95] - node _T_1531 = and(_T_1530, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1532 = bits(_T_1531, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1530 = eq(btb_wr_addr, UInt<6>("h03e")) @[ifu_bp_ctl.scala 416:95] + node _T_1531 = and(_T_1530, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1532 = bits(_T_1531, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_328 of rvclkhdr_422 @[lib.scala 352:23] rvclkhdr_328.clock <= clock rvclkhdr_328.reset <= reset @@ -33471,9 +33471,9 @@ circuit quasar_wrapper : rvclkhdr_328.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_62 : UInt, rvclkhdr_328.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_62 <= btb_wr_data @[lib.scala 358:16] - node _T_1533 = eq(btb_wr_addr, UInt<6>("h03f")) @[ifu_bp_ctl.scala 415:95] - node _T_1534 = and(_T_1533, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1535 = bits(_T_1534, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1533 = eq(btb_wr_addr, UInt<6>("h03f")) @[ifu_bp_ctl.scala 416:95] + node _T_1534 = and(_T_1533, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1535 = bits(_T_1534, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_329 of rvclkhdr_423 @[lib.scala 352:23] rvclkhdr_329.clock <= clock rvclkhdr_329.reset <= reset @@ -33482,9 +33482,9 @@ circuit quasar_wrapper : rvclkhdr_329.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_63 : UInt, rvclkhdr_329.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_63 <= btb_wr_data @[lib.scala 358:16] - node _T_1536 = eq(btb_wr_addr, UInt<7>("h040")) @[ifu_bp_ctl.scala 415:95] - node _T_1537 = and(_T_1536, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1538 = bits(_T_1537, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1536 = eq(btb_wr_addr, UInt<7>("h040")) @[ifu_bp_ctl.scala 416:95] + node _T_1537 = and(_T_1536, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1538 = bits(_T_1537, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_330 of rvclkhdr_424 @[lib.scala 352:23] rvclkhdr_330.clock <= clock rvclkhdr_330.reset <= reset @@ -33493,9 +33493,9 @@ circuit quasar_wrapper : rvclkhdr_330.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_64 : UInt, rvclkhdr_330.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_64 <= btb_wr_data @[lib.scala 358:16] - node _T_1539 = eq(btb_wr_addr, UInt<7>("h041")) @[ifu_bp_ctl.scala 415:95] - node _T_1540 = and(_T_1539, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1541 = bits(_T_1540, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1539 = eq(btb_wr_addr, UInt<7>("h041")) @[ifu_bp_ctl.scala 416:95] + node _T_1540 = and(_T_1539, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1541 = bits(_T_1540, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_331 of rvclkhdr_425 @[lib.scala 352:23] rvclkhdr_331.clock <= clock rvclkhdr_331.reset <= reset @@ -33504,9 +33504,9 @@ circuit quasar_wrapper : rvclkhdr_331.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_65 : UInt, rvclkhdr_331.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_65 <= btb_wr_data @[lib.scala 358:16] - node _T_1542 = eq(btb_wr_addr, UInt<7>("h042")) @[ifu_bp_ctl.scala 415:95] - node _T_1543 = and(_T_1542, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1544 = bits(_T_1543, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1542 = eq(btb_wr_addr, UInt<7>("h042")) @[ifu_bp_ctl.scala 416:95] + node _T_1543 = and(_T_1542, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1544 = bits(_T_1543, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_332 of rvclkhdr_426 @[lib.scala 352:23] rvclkhdr_332.clock <= clock rvclkhdr_332.reset <= reset @@ -33515,9 +33515,9 @@ circuit quasar_wrapper : rvclkhdr_332.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_66 : UInt, rvclkhdr_332.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_66 <= btb_wr_data @[lib.scala 358:16] - node _T_1545 = eq(btb_wr_addr, UInt<7>("h043")) @[ifu_bp_ctl.scala 415:95] - node _T_1546 = and(_T_1545, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1547 = bits(_T_1546, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1545 = eq(btb_wr_addr, UInt<7>("h043")) @[ifu_bp_ctl.scala 416:95] + node _T_1546 = and(_T_1545, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1547 = bits(_T_1546, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_333 of rvclkhdr_427 @[lib.scala 352:23] rvclkhdr_333.clock <= clock rvclkhdr_333.reset <= reset @@ -33526,9 +33526,9 @@ circuit quasar_wrapper : rvclkhdr_333.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_67 : UInt, rvclkhdr_333.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_67 <= btb_wr_data @[lib.scala 358:16] - node _T_1548 = eq(btb_wr_addr, UInt<7>("h044")) @[ifu_bp_ctl.scala 415:95] - node _T_1549 = and(_T_1548, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1550 = bits(_T_1549, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1548 = eq(btb_wr_addr, UInt<7>("h044")) @[ifu_bp_ctl.scala 416:95] + node _T_1549 = and(_T_1548, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1550 = bits(_T_1549, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_334 of rvclkhdr_428 @[lib.scala 352:23] rvclkhdr_334.clock <= clock rvclkhdr_334.reset <= reset @@ -33537,9 +33537,9 @@ circuit quasar_wrapper : rvclkhdr_334.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_68 : UInt, rvclkhdr_334.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_68 <= btb_wr_data @[lib.scala 358:16] - node _T_1551 = eq(btb_wr_addr, UInt<7>("h045")) @[ifu_bp_ctl.scala 415:95] - node _T_1552 = and(_T_1551, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1553 = bits(_T_1552, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1551 = eq(btb_wr_addr, UInt<7>("h045")) @[ifu_bp_ctl.scala 416:95] + node _T_1552 = and(_T_1551, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1553 = bits(_T_1552, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_335 of rvclkhdr_429 @[lib.scala 352:23] rvclkhdr_335.clock <= clock rvclkhdr_335.reset <= reset @@ -33548,9 +33548,9 @@ circuit quasar_wrapper : rvclkhdr_335.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_69 : UInt, rvclkhdr_335.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_69 <= btb_wr_data @[lib.scala 358:16] - node _T_1554 = eq(btb_wr_addr, UInt<7>("h046")) @[ifu_bp_ctl.scala 415:95] - node _T_1555 = and(_T_1554, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1556 = bits(_T_1555, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1554 = eq(btb_wr_addr, UInt<7>("h046")) @[ifu_bp_ctl.scala 416:95] + node _T_1555 = and(_T_1554, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1556 = bits(_T_1555, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_336 of rvclkhdr_430 @[lib.scala 352:23] rvclkhdr_336.clock <= clock rvclkhdr_336.reset <= reset @@ -33559,9 +33559,9 @@ circuit quasar_wrapper : rvclkhdr_336.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_70 : UInt, rvclkhdr_336.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_70 <= btb_wr_data @[lib.scala 358:16] - node _T_1557 = eq(btb_wr_addr, UInt<7>("h047")) @[ifu_bp_ctl.scala 415:95] - node _T_1558 = and(_T_1557, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1559 = bits(_T_1558, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1557 = eq(btb_wr_addr, UInt<7>("h047")) @[ifu_bp_ctl.scala 416:95] + node _T_1558 = and(_T_1557, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1559 = bits(_T_1558, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_337 of rvclkhdr_431 @[lib.scala 352:23] rvclkhdr_337.clock <= clock rvclkhdr_337.reset <= reset @@ -33570,9 +33570,9 @@ circuit quasar_wrapper : rvclkhdr_337.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_71 : UInt, rvclkhdr_337.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_71 <= btb_wr_data @[lib.scala 358:16] - node _T_1560 = eq(btb_wr_addr, UInt<7>("h048")) @[ifu_bp_ctl.scala 415:95] - node _T_1561 = and(_T_1560, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1562 = bits(_T_1561, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1560 = eq(btb_wr_addr, UInt<7>("h048")) @[ifu_bp_ctl.scala 416:95] + node _T_1561 = and(_T_1560, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1562 = bits(_T_1561, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_338 of rvclkhdr_432 @[lib.scala 352:23] rvclkhdr_338.clock <= clock rvclkhdr_338.reset <= reset @@ -33581,9 +33581,9 @@ circuit quasar_wrapper : rvclkhdr_338.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_72 : UInt, rvclkhdr_338.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_72 <= btb_wr_data @[lib.scala 358:16] - node _T_1563 = eq(btb_wr_addr, UInt<7>("h049")) @[ifu_bp_ctl.scala 415:95] - node _T_1564 = and(_T_1563, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1565 = bits(_T_1564, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1563 = eq(btb_wr_addr, UInt<7>("h049")) @[ifu_bp_ctl.scala 416:95] + node _T_1564 = and(_T_1563, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1565 = bits(_T_1564, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_339 of rvclkhdr_433 @[lib.scala 352:23] rvclkhdr_339.clock <= clock rvclkhdr_339.reset <= reset @@ -33592,9 +33592,9 @@ circuit quasar_wrapper : rvclkhdr_339.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_73 : UInt, rvclkhdr_339.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_73 <= btb_wr_data @[lib.scala 358:16] - node _T_1566 = eq(btb_wr_addr, UInt<7>("h04a")) @[ifu_bp_ctl.scala 415:95] - node _T_1567 = and(_T_1566, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1568 = bits(_T_1567, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1566 = eq(btb_wr_addr, UInt<7>("h04a")) @[ifu_bp_ctl.scala 416:95] + node _T_1567 = and(_T_1566, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1568 = bits(_T_1567, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_340 of rvclkhdr_434 @[lib.scala 352:23] rvclkhdr_340.clock <= clock rvclkhdr_340.reset <= reset @@ -33603,9 +33603,9 @@ circuit quasar_wrapper : rvclkhdr_340.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_74 : UInt, rvclkhdr_340.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_74 <= btb_wr_data @[lib.scala 358:16] - node _T_1569 = eq(btb_wr_addr, UInt<7>("h04b")) @[ifu_bp_ctl.scala 415:95] - node _T_1570 = and(_T_1569, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1571 = bits(_T_1570, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1569 = eq(btb_wr_addr, UInt<7>("h04b")) @[ifu_bp_ctl.scala 416:95] + node _T_1570 = and(_T_1569, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1571 = bits(_T_1570, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_341 of rvclkhdr_435 @[lib.scala 352:23] rvclkhdr_341.clock <= clock rvclkhdr_341.reset <= reset @@ -33614,9 +33614,9 @@ circuit quasar_wrapper : rvclkhdr_341.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_75 : UInt, rvclkhdr_341.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_75 <= btb_wr_data @[lib.scala 358:16] - node _T_1572 = eq(btb_wr_addr, UInt<7>("h04c")) @[ifu_bp_ctl.scala 415:95] - node _T_1573 = and(_T_1572, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1574 = bits(_T_1573, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1572 = eq(btb_wr_addr, UInt<7>("h04c")) @[ifu_bp_ctl.scala 416:95] + node _T_1573 = and(_T_1572, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1574 = bits(_T_1573, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_342 of rvclkhdr_436 @[lib.scala 352:23] rvclkhdr_342.clock <= clock rvclkhdr_342.reset <= reset @@ -33625,9 +33625,9 @@ circuit quasar_wrapper : rvclkhdr_342.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_76 : UInt, rvclkhdr_342.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_76 <= btb_wr_data @[lib.scala 358:16] - node _T_1575 = eq(btb_wr_addr, UInt<7>("h04d")) @[ifu_bp_ctl.scala 415:95] - node _T_1576 = and(_T_1575, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1577 = bits(_T_1576, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1575 = eq(btb_wr_addr, UInt<7>("h04d")) @[ifu_bp_ctl.scala 416:95] + node _T_1576 = and(_T_1575, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1577 = bits(_T_1576, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_343 of rvclkhdr_437 @[lib.scala 352:23] rvclkhdr_343.clock <= clock rvclkhdr_343.reset <= reset @@ -33636,9 +33636,9 @@ circuit quasar_wrapper : rvclkhdr_343.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_77 : UInt, rvclkhdr_343.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_77 <= btb_wr_data @[lib.scala 358:16] - node _T_1578 = eq(btb_wr_addr, UInt<7>("h04e")) @[ifu_bp_ctl.scala 415:95] - node _T_1579 = and(_T_1578, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1580 = bits(_T_1579, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1578 = eq(btb_wr_addr, UInt<7>("h04e")) @[ifu_bp_ctl.scala 416:95] + node _T_1579 = and(_T_1578, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1580 = bits(_T_1579, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_344 of rvclkhdr_438 @[lib.scala 352:23] rvclkhdr_344.clock <= clock rvclkhdr_344.reset <= reset @@ -33647,9 +33647,9 @@ circuit quasar_wrapper : rvclkhdr_344.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_78 : UInt, rvclkhdr_344.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_78 <= btb_wr_data @[lib.scala 358:16] - node _T_1581 = eq(btb_wr_addr, UInt<7>("h04f")) @[ifu_bp_ctl.scala 415:95] - node _T_1582 = and(_T_1581, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1583 = bits(_T_1582, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1581 = eq(btb_wr_addr, UInt<7>("h04f")) @[ifu_bp_ctl.scala 416:95] + node _T_1582 = and(_T_1581, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1583 = bits(_T_1582, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_345 of rvclkhdr_439 @[lib.scala 352:23] rvclkhdr_345.clock <= clock rvclkhdr_345.reset <= reset @@ -33658,9 +33658,9 @@ circuit quasar_wrapper : rvclkhdr_345.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_79 : UInt, rvclkhdr_345.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_79 <= btb_wr_data @[lib.scala 358:16] - node _T_1584 = eq(btb_wr_addr, UInt<7>("h050")) @[ifu_bp_ctl.scala 415:95] - node _T_1585 = and(_T_1584, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1586 = bits(_T_1585, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1584 = eq(btb_wr_addr, UInt<7>("h050")) @[ifu_bp_ctl.scala 416:95] + node _T_1585 = and(_T_1584, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1586 = bits(_T_1585, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_346 of rvclkhdr_440 @[lib.scala 352:23] rvclkhdr_346.clock <= clock rvclkhdr_346.reset <= reset @@ -33669,9 +33669,9 @@ circuit quasar_wrapper : rvclkhdr_346.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_80 : UInt, rvclkhdr_346.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_80 <= btb_wr_data @[lib.scala 358:16] - node _T_1587 = eq(btb_wr_addr, UInt<7>("h051")) @[ifu_bp_ctl.scala 415:95] - node _T_1588 = and(_T_1587, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1589 = bits(_T_1588, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1587 = eq(btb_wr_addr, UInt<7>("h051")) @[ifu_bp_ctl.scala 416:95] + node _T_1588 = and(_T_1587, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1589 = bits(_T_1588, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_347 of rvclkhdr_441 @[lib.scala 352:23] rvclkhdr_347.clock <= clock rvclkhdr_347.reset <= reset @@ -33680,9 +33680,9 @@ circuit quasar_wrapper : rvclkhdr_347.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_81 : UInt, rvclkhdr_347.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_81 <= btb_wr_data @[lib.scala 358:16] - node _T_1590 = eq(btb_wr_addr, UInt<7>("h052")) @[ifu_bp_ctl.scala 415:95] - node _T_1591 = and(_T_1590, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1592 = bits(_T_1591, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1590 = eq(btb_wr_addr, UInt<7>("h052")) @[ifu_bp_ctl.scala 416:95] + node _T_1591 = and(_T_1590, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1592 = bits(_T_1591, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_348 of rvclkhdr_442 @[lib.scala 352:23] rvclkhdr_348.clock <= clock rvclkhdr_348.reset <= reset @@ -33691,9 +33691,9 @@ circuit quasar_wrapper : rvclkhdr_348.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_82 : UInt, rvclkhdr_348.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_82 <= btb_wr_data @[lib.scala 358:16] - node _T_1593 = eq(btb_wr_addr, UInt<7>("h053")) @[ifu_bp_ctl.scala 415:95] - node _T_1594 = and(_T_1593, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1595 = bits(_T_1594, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1593 = eq(btb_wr_addr, UInt<7>("h053")) @[ifu_bp_ctl.scala 416:95] + node _T_1594 = and(_T_1593, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1595 = bits(_T_1594, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_349 of rvclkhdr_443 @[lib.scala 352:23] rvclkhdr_349.clock <= clock rvclkhdr_349.reset <= reset @@ -33702,9 +33702,9 @@ circuit quasar_wrapper : rvclkhdr_349.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_83 : UInt, rvclkhdr_349.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_83 <= btb_wr_data @[lib.scala 358:16] - node _T_1596 = eq(btb_wr_addr, UInt<7>("h054")) @[ifu_bp_ctl.scala 415:95] - node _T_1597 = and(_T_1596, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1598 = bits(_T_1597, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1596 = eq(btb_wr_addr, UInt<7>("h054")) @[ifu_bp_ctl.scala 416:95] + node _T_1597 = and(_T_1596, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1598 = bits(_T_1597, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_350 of rvclkhdr_444 @[lib.scala 352:23] rvclkhdr_350.clock <= clock rvclkhdr_350.reset <= reset @@ -33713,9 +33713,9 @@ circuit quasar_wrapper : rvclkhdr_350.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_84 : UInt, rvclkhdr_350.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_84 <= btb_wr_data @[lib.scala 358:16] - node _T_1599 = eq(btb_wr_addr, UInt<7>("h055")) @[ifu_bp_ctl.scala 415:95] - node _T_1600 = and(_T_1599, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1601 = bits(_T_1600, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1599 = eq(btb_wr_addr, UInt<7>("h055")) @[ifu_bp_ctl.scala 416:95] + node _T_1600 = and(_T_1599, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1601 = bits(_T_1600, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_351 of rvclkhdr_445 @[lib.scala 352:23] rvclkhdr_351.clock <= clock rvclkhdr_351.reset <= reset @@ -33724,9 +33724,9 @@ circuit quasar_wrapper : rvclkhdr_351.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_85 : UInt, rvclkhdr_351.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_85 <= btb_wr_data @[lib.scala 358:16] - node _T_1602 = eq(btb_wr_addr, UInt<7>("h056")) @[ifu_bp_ctl.scala 415:95] - node _T_1603 = and(_T_1602, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1604 = bits(_T_1603, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1602 = eq(btb_wr_addr, UInt<7>("h056")) @[ifu_bp_ctl.scala 416:95] + node _T_1603 = and(_T_1602, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1604 = bits(_T_1603, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_352 of rvclkhdr_446 @[lib.scala 352:23] rvclkhdr_352.clock <= clock rvclkhdr_352.reset <= reset @@ -33735,9 +33735,9 @@ circuit quasar_wrapper : rvclkhdr_352.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_86 : UInt, rvclkhdr_352.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_86 <= btb_wr_data @[lib.scala 358:16] - node _T_1605 = eq(btb_wr_addr, UInt<7>("h057")) @[ifu_bp_ctl.scala 415:95] - node _T_1606 = and(_T_1605, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1607 = bits(_T_1606, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1605 = eq(btb_wr_addr, UInt<7>("h057")) @[ifu_bp_ctl.scala 416:95] + node _T_1606 = and(_T_1605, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1607 = bits(_T_1606, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_353 of rvclkhdr_447 @[lib.scala 352:23] rvclkhdr_353.clock <= clock rvclkhdr_353.reset <= reset @@ -33746,9 +33746,9 @@ circuit quasar_wrapper : rvclkhdr_353.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_87 : UInt, rvclkhdr_353.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_87 <= btb_wr_data @[lib.scala 358:16] - node _T_1608 = eq(btb_wr_addr, UInt<7>("h058")) @[ifu_bp_ctl.scala 415:95] - node _T_1609 = and(_T_1608, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1610 = bits(_T_1609, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1608 = eq(btb_wr_addr, UInt<7>("h058")) @[ifu_bp_ctl.scala 416:95] + node _T_1609 = and(_T_1608, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1610 = bits(_T_1609, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_354 of rvclkhdr_448 @[lib.scala 352:23] rvclkhdr_354.clock <= clock rvclkhdr_354.reset <= reset @@ -33757,9 +33757,9 @@ circuit quasar_wrapper : rvclkhdr_354.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_88 : UInt, rvclkhdr_354.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_88 <= btb_wr_data @[lib.scala 358:16] - node _T_1611 = eq(btb_wr_addr, UInt<7>("h059")) @[ifu_bp_ctl.scala 415:95] - node _T_1612 = and(_T_1611, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1613 = bits(_T_1612, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1611 = eq(btb_wr_addr, UInt<7>("h059")) @[ifu_bp_ctl.scala 416:95] + node _T_1612 = and(_T_1611, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1613 = bits(_T_1612, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_355 of rvclkhdr_449 @[lib.scala 352:23] rvclkhdr_355.clock <= clock rvclkhdr_355.reset <= reset @@ -33768,9 +33768,9 @@ circuit quasar_wrapper : rvclkhdr_355.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_89 : UInt, rvclkhdr_355.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_89 <= btb_wr_data @[lib.scala 358:16] - node _T_1614 = eq(btb_wr_addr, UInt<7>("h05a")) @[ifu_bp_ctl.scala 415:95] - node _T_1615 = and(_T_1614, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1616 = bits(_T_1615, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1614 = eq(btb_wr_addr, UInt<7>("h05a")) @[ifu_bp_ctl.scala 416:95] + node _T_1615 = and(_T_1614, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1616 = bits(_T_1615, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_356 of rvclkhdr_450 @[lib.scala 352:23] rvclkhdr_356.clock <= clock rvclkhdr_356.reset <= reset @@ -33779,9 +33779,9 @@ circuit quasar_wrapper : rvclkhdr_356.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_90 : UInt, rvclkhdr_356.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_90 <= btb_wr_data @[lib.scala 358:16] - node _T_1617 = eq(btb_wr_addr, UInt<7>("h05b")) @[ifu_bp_ctl.scala 415:95] - node _T_1618 = and(_T_1617, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1619 = bits(_T_1618, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1617 = eq(btb_wr_addr, UInt<7>("h05b")) @[ifu_bp_ctl.scala 416:95] + node _T_1618 = and(_T_1617, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1619 = bits(_T_1618, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_357 of rvclkhdr_451 @[lib.scala 352:23] rvclkhdr_357.clock <= clock rvclkhdr_357.reset <= reset @@ -33790,9 +33790,9 @@ circuit quasar_wrapper : rvclkhdr_357.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_91 : UInt, rvclkhdr_357.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_91 <= btb_wr_data @[lib.scala 358:16] - node _T_1620 = eq(btb_wr_addr, UInt<7>("h05c")) @[ifu_bp_ctl.scala 415:95] - node _T_1621 = and(_T_1620, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1622 = bits(_T_1621, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1620 = eq(btb_wr_addr, UInt<7>("h05c")) @[ifu_bp_ctl.scala 416:95] + node _T_1621 = and(_T_1620, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1622 = bits(_T_1621, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_358 of rvclkhdr_452 @[lib.scala 352:23] rvclkhdr_358.clock <= clock rvclkhdr_358.reset <= reset @@ -33801,9 +33801,9 @@ circuit quasar_wrapper : rvclkhdr_358.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_92 : UInt, rvclkhdr_358.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_92 <= btb_wr_data @[lib.scala 358:16] - node _T_1623 = eq(btb_wr_addr, UInt<7>("h05d")) @[ifu_bp_ctl.scala 415:95] - node _T_1624 = and(_T_1623, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1625 = bits(_T_1624, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1623 = eq(btb_wr_addr, UInt<7>("h05d")) @[ifu_bp_ctl.scala 416:95] + node _T_1624 = and(_T_1623, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1625 = bits(_T_1624, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_359 of rvclkhdr_453 @[lib.scala 352:23] rvclkhdr_359.clock <= clock rvclkhdr_359.reset <= reset @@ -33812,9 +33812,9 @@ circuit quasar_wrapper : rvclkhdr_359.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_93 : UInt, rvclkhdr_359.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_93 <= btb_wr_data @[lib.scala 358:16] - node _T_1626 = eq(btb_wr_addr, UInt<7>("h05e")) @[ifu_bp_ctl.scala 415:95] - node _T_1627 = and(_T_1626, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1628 = bits(_T_1627, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1626 = eq(btb_wr_addr, UInt<7>("h05e")) @[ifu_bp_ctl.scala 416:95] + node _T_1627 = and(_T_1626, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1628 = bits(_T_1627, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_360 of rvclkhdr_454 @[lib.scala 352:23] rvclkhdr_360.clock <= clock rvclkhdr_360.reset <= reset @@ -33823,9 +33823,9 @@ circuit quasar_wrapper : rvclkhdr_360.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_94 : UInt, rvclkhdr_360.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_94 <= btb_wr_data @[lib.scala 358:16] - node _T_1629 = eq(btb_wr_addr, UInt<7>("h05f")) @[ifu_bp_ctl.scala 415:95] - node _T_1630 = and(_T_1629, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1631 = bits(_T_1630, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1629 = eq(btb_wr_addr, UInt<7>("h05f")) @[ifu_bp_ctl.scala 416:95] + node _T_1630 = and(_T_1629, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1631 = bits(_T_1630, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_361 of rvclkhdr_455 @[lib.scala 352:23] rvclkhdr_361.clock <= clock rvclkhdr_361.reset <= reset @@ -33834,9 +33834,9 @@ circuit quasar_wrapper : rvclkhdr_361.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_95 : UInt, rvclkhdr_361.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_95 <= btb_wr_data @[lib.scala 358:16] - node _T_1632 = eq(btb_wr_addr, UInt<7>("h060")) @[ifu_bp_ctl.scala 415:95] - node _T_1633 = and(_T_1632, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1634 = bits(_T_1633, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1632 = eq(btb_wr_addr, UInt<7>("h060")) @[ifu_bp_ctl.scala 416:95] + node _T_1633 = and(_T_1632, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1634 = bits(_T_1633, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_362 of rvclkhdr_456 @[lib.scala 352:23] rvclkhdr_362.clock <= clock rvclkhdr_362.reset <= reset @@ -33845,9 +33845,9 @@ circuit quasar_wrapper : rvclkhdr_362.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_96 : UInt, rvclkhdr_362.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_96 <= btb_wr_data @[lib.scala 358:16] - node _T_1635 = eq(btb_wr_addr, UInt<7>("h061")) @[ifu_bp_ctl.scala 415:95] - node _T_1636 = and(_T_1635, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1637 = bits(_T_1636, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1635 = eq(btb_wr_addr, UInt<7>("h061")) @[ifu_bp_ctl.scala 416:95] + node _T_1636 = and(_T_1635, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1637 = bits(_T_1636, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_363 of rvclkhdr_457 @[lib.scala 352:23] rvclkhdr_363.clock <= clock rvclkhdr_363.reset <= reset @@ -33856,9 +33856,9 @@ circuit quasar_wrapper : rvclkhdr_363.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_97 : UInt, rvclkhdr_363.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_97 <= btb_wr_data @[lib.scala 358:16] - node _T_1638 = eq(btb_wr_addr, UInt<7>("h062")) @[ifu_bp_ctl.scala 415:95] - node _T_1639 = and(_T_1638, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1640 = bits(_T_1639, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1638 = eq(btb_wr_addr, UInt<7>("h062")) @[ifu_bp_ctl.scala 416:95] + node _T_1639 = and(_T_1638, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1640 = bits(_T_1639, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_364 of rvclkhdr_458 @[lib.scala 352:23] rvclkhdr_364.clock <= clock rvclkhdr_364.reset <= reset @@ -33867,9 +33867,9 @@ circuit quasar_wrapper : rvclkhdr_364.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_98 : UInt, rvclkhdr_364.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_98 <= btb_wr_data @[lib.scala 358:16] - node _T_1641 = eq(btb_wr_addr, UInt<7>("h063")) @[ifu_bp_ctl.scala 415:95] - node _T_1642 = and(_T_1641, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1643 = bits(_T_1642, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1641 = eq(btb_wr_addr, UInt<7>("h063")) @[ifu_bp_ctl.scala 416:95] + node _T_1642 = and(_T_1641, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1643 = bits(_T_1642, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_365 of rvclkhdr_459 @[lib.scala 352:23] rvclkhdr_365.clock <= clock rvclkhdr_365.reset <= reset @@ -33878,9 +33878,9 @@ circuit quasar_wrapper : rvclkhdr_365.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_99 : UInt, rvclkhdr_365.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_99 <= btb_wr_data @[lib.scala 358:16] - node _T_1644 = eq(btb_wr_addr, UInt<7>("h064")) @[ifu_bp_ctl.scala 415:95] - node _T_1645 = and(_T_1644, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1646 = bits(_T_1645, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1644 = eq(btb_wr_addr, UInt<7>("h064")) @[ifu_bp_ctl.scala 416:95] + node _T_1645 = and(_T_1644, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1646 = bits(_T_1645, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_366 of rvclkhdr_460 @[lib.scala 352:23] rvclkhdr_366.clock <= clock rvclkhdr_366.reset <= reset @@ -33889,9 +33889,9 @@ circuit quasar_wrapper : rvclkhdr_366.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_100 : UInt, rvclkhdr_366.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_100 <= btb_wr_data @[lib.scala 358:16] - node _T_1647 = eq(btb_wr_addr, UInt<7>("h065")) @[ifu_bp_ctl.scala 415:95] - node _T_1648 = and(_T_1647, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1649 = bits(_T_1648, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1647 = eq(btb_wr_addr, UInt<7>("h065")) @[ifu_bp_ctl.scala 416:95] + node _T_1648 = and(_T_1647, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1649 = bits(_T_1648, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_367 of rvclkhdr_461 @[lib.scala 352:23] rvclkhdr_367.clock <= clock rvclkhdr_367.reset <= reset @@ -33900,9 +33900,9 @@ circuit quasar_wrapper : rvclkhdr_367.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_101 : UInt, rvclkhdr_367.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_101 <= btb_wr_data @[lib.scala 358:16] - node _T_1650 = eq(btb_wr_addr, UInt<7>("h066")) @[ifu_bp_ctl.scala 415:95] - node _T_1651 = and(_T_1650, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1652 = bits(_T_1651, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1650 = eq(btb_wr_addr, UInt<7>("h066")) @[ifu_bp_ctl.scala 416:95] + node _T_1651 = and(_T_1650, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1652 = bits(_T_1651, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_368 of rvclkhdr_462 @[lib.scala 352:23] rvclkhdr_368.clock <= clock rvclkhdr_368.reset <= reset @@ -33911,9 +33911,9 @@ circuit quasar_wrapper : rvclkhdr_368.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_102 : UInt, rvclkhdr_368.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_102 <= btb_wr_data @[lib.scala 358:16] - node _T_1653 = eq(btb_wr_addr, UInt<7>("h067")) @[ifu_bp_ctl.scala 415:95] - node _T_1654 = and(_T_1653, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1655 = bits(_T_1654, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1653 = eq(btb_wr_addr, UInt<7>("h067")) @[ifu_bp_ctl.scala 416:95] + node _T_1654 = and(_T_1653, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1655 = bits(_T_1654, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_369 of rvclkhdr_463 @[lib.scala 352:23] rvclkhdr_369.clock <= clock rvclkhdr_369.reset <= reset @@ -33922,9 +33922,9 @@ circuit quasar_wrapper : rvclkhdr_369.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_103 : UInt, rvclkhdr_369.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_103 <= btb_wr_data @[lib.scala 358:16] - node _T_1656 = eq(btb_wr_addr, UInt<7>("h068")) @[ifu_bp_ctl.scala 415:95] - node _T_1657 = and(_T_1656, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1658 = bits(_T_1657, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1656 = eq(btb_wr_addr, UInt<7>("h068")) @[ifu_bp_ctl.scala 416:95] + node _T_1657 = and(_T_1656, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1658 = bits(_T_1657, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_370 of rvclkhdr_464 @[lib.scala 352:23] rvclkhdr_370.clock <= clock rvclkhdr_370.reset <= reset @@ -33933,9 +33933,9 @@ circuit quasar_wrapper : rvclkhdr_370.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_104 : UInt, rvclkhdr_370.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_104 <= btb_wr_data @[lib.scala 358:16] - node _T_1659 = eq(btb_wr_addr, UInt<7>("h069")) @[ifu_bp_ctl.scala 415:95] - node _T_1660 = and(_T_1659, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1661 = bits(_T_1660, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1659 = eq(btb_wr_addr, UInt<7>("h069")) @[ifu_bp_ctl.scala 416:95] + node _T_1660 = and(_T_1659, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1661 = bits(_T_1660, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_371 of rvclkhdr_465 @[lib.scala 352:23] rvclkhdr_371.clock <= clock rvclkhdr_371.reset <= reset @@ -33944,9 +33944,9 @@ circuit quasar_wrapper : rvclkhdr_371.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_105 : UInt, rvclkhdr_371.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_105 <= btb_wr_data @[lib.scala 358:16] - node _T_1662 = eq(btb_wr_addr, UInt<7>("h06a")) @[ifu_bp_ctl.scala 415:95] - node _T_1663 = and(_T_1662, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1664 = bits(_T_1663, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1662 = eq(btb_wr_addr, UInt<7>("h06a")) @[ifu_bp_ctl.scala 416:95] + node _T_1663 = and(_T_1662, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1664 = bits(_T_1663, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_372 of rvclkhdr_466 @[lib.scala 352:23] rvclkhdr_372.clock <= clock rvclkhdr_372.reset <= reset @@ -33955,9 +33955,9 @@ circuit quasar_wrapper : rvclkhdr_372.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_106 : UInt, rvclkhdr_372.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_106 <= btb_wr_data @[lib.scala 358:16] - node _T_1665 = eq(btb_wr_addr, UInt<7>("h06b")) @[ifu_bp_ctl.scala 415:95] - node _T_1666 = and(_T_1665, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1667 = bits(_T_1666, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1665 = eq(btb_wr_addr, UInt<7>("h06b")) @[ifu_bp_ctl.scala 416:95] + node _T_1666 = and(_T_1665, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1667 = bits(_T_1666, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_373 of rvclkhdr_467 @[lib.scala 352:23] rvclkhdr_373.clock <= clock rvclkhdr_373.reset <= reset @@ -33966,9 +33966,9 @@ circuit quasar_wrapper : rvclkhdr_373.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_107 : UInt, rvclkhdr_373.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_107 <= btb_wr_data @[lib.scala 358:16] - node _T_1668 = eq(btb_wr_addr, UInt<7>("h06c")) @[ifu_bp_ctl.scala 415:95] - node _T_1669 = and(_T_1668, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1670 = bits(_T_1669, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1668 = eq(btb_wr_addr, UInt<7>("h06c")) @[ifu_bp_ctl.scala 416:95] + node _T_1669 = and(_T_1668, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1670 = bits(_T_1669, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_374 of rvclkhdr_468 @[lib.scala 352:23] rvclkhdr_374.clock <= clock rvclkhdr_374.reset <= reset @@ -33977,9 +33977,9 @@ circuit quasar_wrapper : rvclkhdr_374.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_108 : UInt, rvclkhdr_374.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_108 <= btb_wr_data @[lib.scala 358:16] - node _T_1671 = eq(btb_wr_addr, UInt<7>("h06d")) @[ifu_bp_ctl.scala 415:95] - node _T_1672 = and(_T_1671, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1673 = bits(_T_1672, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1671 = eq(btb_wr_addr, UInt<7>("h06d")) @[ifu_bp_ctl.scala 416:95] + node _T_1672 = and(_T_1671, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1673 = bits(_T_1672, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_375 of rvclkhdr_469 @[lib.scala 352:23] rvclkhdr_375.clock <= clock rvclkhdr_375.reset <= reset @@ -33988,9 +33988,9 @@ circuit quasar_wrapper : rvclkhdr_375.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_109 : UInt, rvclkhdr_375.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_109 <= btb_wr_data @[lib.scala 358:16] - node _T_1674 = eq(btb_wr_addr, UInt<7>("h06e")) @[ifu_bp_ctl.scala 415:95] - node _T_1675 = and(_T_1674, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1676 = bits(_T_1675, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1674 = eq(btb_wr_addr, UInt<7>("h06e")) @[ifu_bp_ctl.scala 416:95] + node _T_1675 = and(_T_1674, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1676 = bits(_T_1675, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_376 of rvclkhdr_470 @[lib.scala 352:23] rvclkhdr_376.clock <= clock rvclkhdr_376.reset <= reset @@ -33999,9 +33999,9 @@ circuit quasar_wrapper : rvclkhdr_376.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_110 : UInt, rvclkhdr_376.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_110 <= btb_wr_data @[lib.scala 358:16] - node _T_1677 = eq(btb_wr_addr, UInt<7>("h06f")) @[ifu_bp_ctl.scala 415:95] - node _T_1678 = and(_T_1677, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1679 = bits(_T_1678, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1677 = eq(btb_wr_addr, UInt<7>("h06f")) @[ifu_bp_ctl.scala 416:95] + node _T_1678 = and(_T_1677, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1679 = bits(_T_1678, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_377 of rvclkhdr_471 @[lib.scala 352:23] rvclkhdr_377.clock <= clock rvclkhdr_377.reset <= reset @@ -34010,9 +34010,9 @@ circuit quasar_wrapper : rvclkhdr_377.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_111 : UInt, rvclkhdr_377.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_111 <= btb_wr_data @[lib.scala 358:16] - node _T_1680 = eq(btb_wr_addr, UInt<7>("h070")) @[ifu_bp_ctl.scala 415:95] - node _T_1681 = and(_T_1680, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1682 = bits(_T_1681, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1680 = eq(btb_wr_addr, UInt<7>("h070")) @[ifu_bp_ctl.scala 416:95] + node _T_1681 = and(_T_1680, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1682 = bits(_T_1681, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_378 of rvclkhdr_472 @[lib.scala 352:23] rvclkhdr_378.clock <= clock rvclkhdr_378.reset <= reset @@ -34021,9 +34021,9 @@ circuit quasar_wrapper : rvclkhdr_378.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_112 : UInt, rvclkhdr_378.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_112 <= btb_wr_data @[lib.scala 358:16] - node _T_1683 = eq(btb_wr_addr, UInt<7>("h071")) @[ifu_bp_ctl.scala 415:95] - node _T_1684 = and(_T_1683, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1685 = bits(_T_1684, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1683 = eq(btb_wr_addr, UInt<7>("h071")) @[ifu_bp_ctl.scala 416:95] + node _T_1684 = and(_T_1683, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1685 = bits(_T_1684, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_379 of rvclkhdr_473 @[lib.scala 352:23] rvclkhdr_379.clock <= clock rvclkhdr_379.reset <= reset @@ -34032,9 +34032,9 @@ circuit quasar_wrapper : rvclkhdr_379.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_113 : UInt, rvclkhdr_379.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_113 <= btb_wr_data @[lib.scala 358:16] - node _T_1686 = eq(btb_wr_addr, UInt<7>("h072")) @[ifu_bp_ctl.scala 415:95] - node _T_1687 = and(_T_1686, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1688 = bits(_T_1687, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1686 = eq(btb_wr_addr, UInt<7>("h072")) @[ifu_bp_ctl.scala 416:95] + node _T_1687 = and(_T_1686, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1688 = bits(_T_1687, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_380 of rvclkhdr_474 @[lib.scala 352:23] rvclkhdr_380.clock <= clock rvclkhdr_380.reset <= reset @@ -34043,9 +34043,9 @@ circuit quasar_wrapper : rvclkhdr_380.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_114 : UInt, rvclkhdr_380.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_114 <= btb_wr_data @[lib.scala 358:16] - node _T_1689 = eq(btb_wr_addr, UInt<7>("h073")) @[ifu_bp_ctl.scala 415:95] - node _T_1690 = and(_T_1689, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1691 = bits(_T_1690, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1689 = eq(btb_wr_addr, UInt<7>("h073")) @[ifu_bp_ctl.scala 416:95] + node _T_1690 = and(_T_1689, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1691 = bits(_T_1690, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_381 of rvclkhdr_475 @[lib.scala 352:23] rvclkhdr_381.clock <= clock rvclkhdr_381.reset <= reset @@ -34054,9 +34054,9 @@ circuit quasar_wrapper : rvclkhdr_381.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_115 : UInt, rvclkhdr_381.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_115 <= btb_wr_data @[lib.scala 358:16] - node _T_1692 = eq(btb_wr_addr, UInt<7>("h074")) @[ifu_bp_ctl.scala 415:95] - node _T_1693 = and(_T_1692, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1694 = bits(_T_1693, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1692 = eq(btb_wr_addr, UInt<7>("h074")) @[ifu_bp_ctl.scala 416:95] + node _T_1693 = and(_T_1692, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1694 = bits(_T_1693, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_382 of rvclkhdr_476 @[lib.scala 352:23] rvclkhdr_382.clock <= clock rvclkhdr_382.reset <= reset @@ -34065,9 +34065,9 @@ circuit quasar_wrapper : rvclkhdr_382.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_116 : UInt, rvclkhdr_382.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_116 <= btb_wr_data @[lib.scala 358:16] - node _T_1695 = eq(btb_wr_addr, UInt<7>("h075")) @[ifu_bp_ctl.scala 415:95] - node _T_1696 = and(_T_1695, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1697 = bits(_T_1696, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1695 = eq(btb_wr_addr, UInt<7>("h075")) @[ifu_bp_ctl.scala 416:95] + node _T_1696 = and(_T_1695, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1697 = bits(_T_1696, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_383 of rvclkhdr_477 @[lib.scala 352:23] rvclkhdr_383.clock <= clock rvclkhdr_383.reset <= reset @@ -34076,9 +34076,9 @@ circuit quasar_wrapper : rvclkhdr_383.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_117 : UInt, rvclkhdr_383.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_117 <= btb_wr_data @[lib.scala 358:16] - node _T_1698 = eq(btb_wr_addr, UInt<7>("h076")) @[ifu_bp_ctl.scala 415:95] - node _T_1699 = and(_T_1698, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1700 = bits(_T_1699, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1698 = eq(btb_wr_addr, UInt<7>("h076")) @[ifu_bp_ctl.scala 416:95] + node _T_1699 = and(_T_1698, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1700 = bits(_T_1699, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_384 of rvclkhdr_478 @[lib.scala 352:23] rvclkhdr_384.clock <= clock rvclkhdr_384.reset <= reset @@ -34087,9 +34087,9 @@ circuit quasar_wrapper : rvclkhdr_384.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_118 : UInt, rvclkhdr_384.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_118 <= btb_wr_data @[lib.scala 358:16] - node _T_1701 = eq(btb_wr_addr, UInt<7>("h077")) @[ifu_bp_ctl.scala 415:95] - node _T_1702 = and(_T_1701, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1703 = bits(_T_1702, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1701 = eq(btb_wr_addr, UInt<7>("h077")) @[ifu_bp_ctl.scala 416:95] + node _T_1702 = and(_T_1701, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1703 = bits(_T_1702, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_385 of rvclkhdr_479 @[lib.scala 352:23] rvclkhdr_385.clock <= clock rvclkhdr_385.reset <= reset @@ -34098,9 +34098,9 @@ circuit quasar_wrapper : rvclkhdr_385.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_119 : UInt, rvclkhdr_385.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_119 <= btb_wr_data @[lib.scala 358:16] - node _T_1704 = eq(btb_wr_addr, UInt<7>("h078")) @[ifu_bp_ctl.scala 415:95] - node _T_1705 = and(_T_1704, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1706 = bits(_T_1705, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1704 = eq(btb_wr_addr, UInt<7>("h078")) @[ifu_bp_ctl.scala 416:95] + node _T_1705 = and(_T_1704, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1706 = bits(_T_1705, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_386 of rvclkhdr_480 @[lib.scala 352:23] rvclkhdr_386.clock <= clock rvclkhdr_386.reset <= reset @@ -34109,9 +34109,9 @@ circuit quasar_wrapper : rvclkhdr_386.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_120 : UInt, rvclkhdr_386.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_120 <= btb_wr_data @[lib.scala 358:16] - node _T_1707 = eq(btb_wr_addr, UInt<7>("h079")) @[ifu_bp_ctl.scala 415:95] - node _T_1708 = and(_T_1707, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1709 = bits(_T_1708, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1707 = eq(btb_wr_addr, UInt<7>("h079")) @[ifu_bp_ctl.scala 416:95] + node _T_1708 = and(_T_1707, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1709 = bits(_T_1708, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_387 of rvclkhdr_481 @[lib.scala 352:23] rvclkhdr_387.clock <= clock rvclkhdr_387.reset <= reset @@ -34120,9 +34120,9 @@ circuit quasar_wrapper : rvclkhdr_387.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_121 : UInt, rvclkhdr_387.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_121 <= btb_wr_data @[lib.scala 358:16] - node _T_1710 = eq(btb_wr_addr, UInt<7>("h07a")) @[ifu_bp_ctl.scala 415:95] - node _T_1711 = and(_T_1710, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1712 = bits(_T_1711, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1710 = eq(btb_wr_addr, UInt<7>("h07a")) @[ifu_bp_ctl.scala 416:95] + node _T_1711 = and(_T_1710, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1712 = bits(_T_1711, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_388 of rvclkhdr_482 @[lib.scala 352:23] rvclkhdr_388.clock <= clock rvclkhdr_388.reset <= reset @@ -34131,9 +34131,9 @@ circuit quasar_wrapper : rvclkhdr_388.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_122 : UInt, rvclkhdr_388.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_122 <= btb_wr_data @[lib.scala 358:16] - node _T_1713 = eq(btb_wr_addr, UInt<7>("h07b")) @[ifu_bp_ctl.scala 415:95] - node _T_1714 = and(_T_1713, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1715 = bits(_T_1714, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1713 = eq(btb_wr_addr, UInt<7>("h07b")) @[ifu_bp_ctl.scala 416:95] + node _T_1714 = and(_T_1713, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1715 = bits(_T_1714, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_389 of rvclkhdr_483 @[lib.scala 352:23] rvclkhdr_389.clock <= clock rvclkhdr_389.reset <= reset @@ -34142,9 +34142,9 @@ circuit quasar_wrapper : rvclkhdr_389.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_123 : UInt, rvclkhdr_389.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_123 <= btb_wr_data @[lib.scala 358:16] - node _T_1716 = eq(btb_wr_addr, UInt<7>("h07c")) @[ifu_bp_ctl.scala 415:95] - node _T_1717 = and(_T_1716, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1718 = bits(_T_1717, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1716 = eq(btb_wr_addr, UInt<7>("h07c")) @[ifu_bp_ctl.scala 416:95] + node _T_1717 = and(_T_1716, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1718 = bits(_T_1717, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_390 of rvclkhdr_484 @[lib.scala 352:23] rvclkhdr_390.clock <= clock rvclkhdr_390.reset <= reset @@ -34153,9 +34153,9 @@ circuit quasar_wrapper : rvclkhdr_390.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_124 : UInt, rvclkhdr_390.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_124 <= btb_wr_data @[lib.scala 358:16] - node _T_1719 = eq(btb_wr_addr, UInt<7>("h07d")) @[ifu_bp_ctl.scala 415:95] - node _T_1720 = and(_T_1719, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1721 = bits(_T_1720, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1719 = eq(btb_wr_addr, UInt<7>("h07d")) @[ifu_bp_ctl.scala 416:95] + node _T_1720 = and(_T_1719, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1721 = bits(_T_1720, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_391 of rvclkhdr_485 @[lib.scala 352:23] rvclkhdr_391.clock <= clock rvclkhdr_391.reset <= reset @@ -34164,9 +34164,9 @@ circuit quasar_wrapper : rvclkhdr_391.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_125 : UInt, rvclkhdr_391.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_125 <= btb_wr_data @[lib.scala 358:16] - node _T_1722 = eq(btb_wr_addr, UInt<7>("h07e")) @[ifu_bp_ctl.scala 415:95] - node _T_1723 = and(_T_1722, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1724 = bits(_T_1723, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1722 = eq(btb_wr_addr, UInt<7>("h07e")) @[ifu_bp_ctl.scala 416:95] + node _T_1723 = and(_T_1722, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1724 = bits(_T_1723, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_392 of rvclkhdr_486 @[lib.scala 352:23] rvclkhdr_392.clock <= clock rvclkhdr_392.reset <= reset @@ -34175,9 +34175,9 @@ circuit quasar_wrapper : rvclkhdr_392.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_126 : UInt, rvclkhdr_392.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_126 <= btb_wr_data @[lib.scala 358:16] - node _T_1725 = eq(btb_wr_addr, UInt<7>("h07f")) @[ifu_bp_ctl.scala 415:95] - node _T_1726 = and(_T_1725, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1727 = bits(_T_1726, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1725 = eq(btb_wr_addr, UInt<7>("h07f")) @[ifu_bp_ctl.scala 416:95] + node _T_1726 = and(_T_1725, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1727 = bits(_T_1726, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_393 of rvclkhdr_487 @[lib.scala 352:23] rvclkhdr_393.clock <= clock rvclkhdr_393.reset <= reset @@ -34186,9 +34186,9 @@ circuit quasar_wrapper : rvclkhdr_393.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_127 : UInt, rvclkhdr_393.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_127 <= btb_wr_data @[lib.scala 358:16] - node _T_1728 = eq(btb_wr_addr, UInt<8>("h080")) @[ifu_bp_ctl.scala 415:95] - node _T_1729 = and(_T_1728, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1730 = bits(_T_1729, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1728 = eq(btb_wr_addr, UInt<8>("h080")) @[ifu_bp_ctl.scala 416:95] + node _T_1729 = and(_T_1728, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1730 = bits(_T_1729, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_394 of rvclkhdr_488 @[lib.scala 352:23] rvclkhdr_394.clock <= clock rvclkhdr_394.reset <= reset @@ -34197,9 +34197,9 @@ circuit quasar_wrapper : rvclkhdr_394.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_128 : UInt, rvclkhdr_394.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_128 <= btb_wr_data @[lib.scala 358:16] - node _T_1731 = eq(btb_wr_addr, UInt<8>("h081")) @[ifu_bp_ctl.scala 415:95] - node _T_1732 = and(_T_1731, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1733 = bits(_T_1732, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1731 = eq(btb_wr_addr, UInt<8>("h081")) @[ifu_bp_ctl.scala 416:95] + node _T_1732 = and(_T_1731, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1733 = bits(_T_1732, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_395 of rvclkhdr_489 @[lib.scala 352:23] rvclkhdr_395.clock <= clock rvclkhdr_395.reset <= reset @@ -34208,9 +34208,9 @@ circuit quasar_wrapper : rvclkhdr_395.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_129 : UInt, rvclkhdr_395.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_129 <= btb_wr_data @[lib.scala 358:16] - node _T_1734 = eq(btb_wr_addr, UInt<8>("h082")) @[ifu_bp_ctl.scala 415:95] - node _T_1735 = and(_T_1734, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1736 = bits(_T_1735, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1734 = eq(btb_wr_addr, UInt<8>("h082")) @[ifu_bp_ctl.scala 416:95] + node _T_1735 = and(_T_1734, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1736 = bits(_T_1735, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_396 of rvclkhdr_490 @[lib.scala 352:23] rvclkhdr_396.clock <= clock rvclkhdr_396.reset <= reset @@ -34219,9 +34219,9 @@ circuit quasar_wrapper : rvclkhdr_396.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_130 : UInt, rvclkhdr_396.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_130 <= btb_wr_data @[lib.scala 358:16] - node _T_1737 = eq(btb_wr_addr, UInt<8>("h083")) @[ifu_bp_ctl.scala 415:95] - node _T_1738 = and(_T_1737, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1739 = bits(_T_1738, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1737 = eq(btb_wr_addr, UInt<8>("h083")) @[ifu_bp_ctl.scala 416:95] + node _T_1738 = and(_T_1737, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1739 = bits(_T_1738, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_397 of rvclkhdr_491 @[lib.scala 352:23] rvclkhdr_397.clock <= clock rvclkhdr_397.reset <= reset @@ -34230,9 +34230,9 @@ circuit quasar_wrapper : rvclkhdr_397.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_131 : UInt, rvclkhdr_397.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_131 <= btb_wr_data @[lib.scala 358:16] - node _T_1740 = eq(btb_wr_addr, UInt<8>("h084")) @[ifu_bp_ctl.scala 415:95] - node _T_1741 = and(_T_1740, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1742 = bits(_T_1741, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1740 = eq(btb_wr_addr, UInt<8>("h084")) @[ifu_bp_ctl.scala 416:95] + node _T_1741 = and(_T_1740, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1742 = bits(_T_1741, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_398 of rvclkhdr_492 @[lib.scala 352:23] rvclkhdr_398.clock <= clock rvclkhdr_398.reset <= reset @@ -34241,9 +34241,9 @@ circuit quasar_wrapper : rvclkhdr_398.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_132 : UInt, rvclkhdr_398.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_132 <= btb_wr_data @[lib.scala 358:16] - node _T_1743 = eq(btb_wr_addr, UInt<8>("h085")) @[ifu_bp_ctl.scala 415:95] - node _T_1744 = and(_T_1743, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1745 = bits(_T_1744, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1743 = eq(btb_wr_addr, UInt<8>("h085")) @[ifu_bp_ctl.scala 416:95] + node _T_1744 = and(_T_1743, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1745 = bits(_T_1744, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_399 of rvclkhdr_493 @[lib.scala 352:23] rvclkhdr_399.clock <= clock rvclkhdr_399.reset <= reset @@ -34252,9 +34252,9 @@ circuit quasar_wrapper : rvclkhdr_399.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_133 : UInt, rvclkhdr_399.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_133 <= btb_wr_data @[lib.scala 358:16] - node _T_1746 = eq(btb_wr_addr, UInt<8>("h086")) @[ifu_bp_ctl.scala 415:95] - node _T_1747 = and(_T_1746, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1748 = bits(_T_1747, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1746 = eq(btb_wr_addr, UInt<8>("h086")) @[ifu_bp_ctl.scala 416:95] + node _T_1747 = and(_T_1746, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1748 = bits(_T_1747, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_400 of rvclkhdr_494 @[lib.scala 352:23] rvclkhdr_400.clock <= clock rvclkhdr_400.reset <= reset @@ -34263,9 +34263,9 @@ circuit quasar_wrapper : rvclkhdr_400.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_134 : UInt, rvclkhdr_400.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_134 <= btb_wr_data @[lib.scala 358:16] - node _T_1749 = eq(btb_wr_addr, UInt<8>("h087")) @[ifu_bp_ctl.scala 415:95] - node _T_1750 = and(_T_1749, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1751 = bits(_T_1750, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1749 = eq(btb_wr_addr, UInt<8>("h087")) @[ifu_bp_ctl.scala 416:95] + node _T_1750 = and(_T_1749, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1751 = bits(_T_1750, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_401 of rvclkhdr_495 @[lib.scala 352:23] rvclkhdr_401.clock <= clock rvclkhdr_401.reset <= reset @@ -34274,9 +34274,9 @@ circuit quasar_wrapper : rvclkhdr_401.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_135 : UInt, rvclkhdr_401.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_135 <= btb_wr_data @[lib.scala 358:16] - node _T_1752 = eq(btb_wr_addr, UInt<8>("h088")) @[ifu_bp_ctl.scala 415:95] - node _T_1753 = and(_T_1752, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1754 = bits(_T_1753, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1752 = eq(btb_wr_addr, UInt<8>("h088")) @[ifu_bp_ctl.scala 416:95] + node _T_1753 = and(_T_1752, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1754 = bits(_T_1753, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_402 of rvclkhdr_496 @[lib.scala 352:23] rvclkhdr_402.clock <= clock rvclkhdr_402.reset <= reset @@ -34285,9 +34285,9 @@ circuit quasar_wrapper : rvclkhdr_402.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_136 : UInt, rvclkhdr_402.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_136 <= btb_wr_data @[lib.scala 358:16] - node _T_1755 = eq(btb_wr_addr, UInt<8>("h089")) @[ifu_bp_ctl.scala 415:95] - node _T_1756 = and(_T_1755, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1757 = bits(_T_1756, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1755 = eq(btb_wr_addr, UInt<8>("h089")) @[ifu_bp_ctl.scala 416:95] + node _T_1756 = and(_T_1755, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1757 = bits(_T_1756, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_403 of rvclkhdr_497 @[lib.scala 352:23] rvclkhdr_403.clock <= clock rvclkhdr_403.reset <= reset @@ -34296,9 +34296,9 @@ circuit quasar_wrapper : rvclkhdr_403.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_137 : UInt, rvclkhdr_403.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_137 <= btb_wr_data @[lib.scala 358:16] - node _T_1758 = eq(btb_wr_addr, UInt<8>("h08a")) @[ifu_bp_ctl.scala 415:95] - node _T_1759 = and(_T_1758, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1760 = bits(_T_1759, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1758 = eq(btb_wr_addr, UInt<8>("h08a")) @[ifu_bp_ctl.scala 416:95] + node _T_1759 = and(_T_1758, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1760 = bits(_T_1759, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_404 of rvclkhdr_498 @[lib.scala 352:23] rvclkhdr_404.clock <= clock rvclkhdr_404.reset <= reset @@ -34307,9 +34307,9 @@ circuit quasar_wrapper : rvclkhdr_404.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_138 : UInt, rvclkhdr_404.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_138 <= btb_wr_data @[lib.scala 358:16] - node _T_1761 = eq(btb_wr_addr, UInt<8>("h08b")) @[ifu_bp_ctl.scala 415:95] - node _T_1762 = and(_T_1761, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1763 = bits(_T_1762, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1761 = eq(btb_wr_addr, UInt<8>("h08b")) @[ifu_bp_ctl.scala 416:95] + node _T_1762 = and(_T_1761, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1763 = bits(_T_1762, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_405 of rvclkhdr_499 @[lib.scala 352:23] rvclkhdr_405.clock <= clock rvclkhdr_405.reset <= reset @@ -34318,9 +34318,9 @@ circuit quasar_wrapper : rvclkhdr_405.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_139 : UInt, rvclkhdr_405.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_139 <= btb_wr_data @[lib.scala 358:16] - node _T_1764 = eq(btb_wr_addr, UInt<8>("h08c")) @[ifu_bp_ctl.scala 415:95] - node _T_1765 = and(_T_1764, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1766 = bits(_T_1765, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1764 = eq(btb_wr_addr, UInt<8>("h08c")) @[ifu_bp_ctl.scala 416:95] + node _T_1765 = and(_T_1764, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1766 = bits(_T_1765, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_406 of rvclkhdr_500 @[lib.scala 352:23] rvclkhdr_406.clock <= clock rvclkhdr_406.reset <= reset @@ -34329,9 +34329,9 @@ circuit quasar_wrapper : rvclkhdr_406.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_140 : UInt, rvclkhdr_406.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_140 <= btb_wr_data @[lib.scala 358:16] - node _T_1767 = eq(btb_wr_addr, UInt<8>("h08d")) @[ifu_bp_ctl.scala 415:95] - node _T_1768 = and(_T_1767, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1769 = bits(_T_1768, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1767 = eq(btb_wr_addr, UInt<8>("h08d")) @[ifu_bp_ctl.scala 416:95] + node _T_1768 = and(_T_1767, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1769 = bits(_T_1768, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_407 of rvclkhdr_501 @[lib.scala 352:23] rvclkhdr_407.clock <= clock rvclkhdr_407.reset <= reset @@ -34340,9 +34340,9 @@ circuit quasar_wrapper : rvclkhdr_407.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_141 : UInt, rvclkhdr_407.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_141 <= btb_wr_data @[lib.scala 358:16] - node _T_1770 = eq(btb_wr_addr, UInt<8>("h08e")) @[ifu_bp_ctl.scala 415:95] - node _T_1771 = and(_T_1770, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1772 = bits(_T_1771, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1770 = eq(btb_wr_addr, UInt<8>("h08e")) @[ifu_bp_ctl.scala 416:95] + node _T_1771 = and(_T_1770, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1772 = bits(_T_1771, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_408 of rvclkhdr_502 @[lib.scala 352:23] rvclkhdr_408.clock <= clock rvclkhdr_408.reset <= reset @@ -34351,9 +34351,9 @@ circuit quasar_wrapper : rvclkhdr_408.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_142 : UInt, rvclkhdr_408.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_142 <= btb_wr_data @[lib.scala 358:16] - node _T_1773 = eq(btb_wr_addr, UInt<8>("h08f")) @[ifu_bp_ctl.scala 415:95] - node _T_1774 = and(_T_1773, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1775 = bits(_T_1774, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1773 = eq(btb_wr_addr, UInt<8>("h08f")) @[ifu_bp_ctl.scala 416:95] + node _T_1774 = and(_T_1773, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1775 = bits(_T_1774, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_409 of rvclkhdr_503 @[lib.scala 352:23] rvclkhdr_409.clock <= clock rvclkhdr_409.reset <= reset @@ -34362,9 +34362,9 @@ circuit quasar_wrapper : rvclkhdr_409.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_143 : UInt, rvclkhdr_409.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_143 <= btb_wr_data @[lib.scala 358:16] - node _T_1776 = eq(btb_wr_addr, UInt<8>("h090")) @[ifu_bp_ctl.scala 415:95] - node _T_1777 = and(_T_1776, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1778 = bits(_T_1777, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1776 = eq(btb_wr_addr, UInt<8>("h090")) @[ifu_bp_ctl.scala 416:95] + node _T_1777 = and(_T_1776, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1778 = bits(_T_1777, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_410 of rvclkhdr_504 @[lib.scala 352:23] rvclkhdr_410.clock <= clock rvclkhdr_410.reset <= reset @@ -34373,9 +34373,9 @@ circuit quasar_wrapper : rvclkhdr_410.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_144 : UInt, rvclkhdr_410.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_144 <= btb_wr_data @[lib.scala 358:16] - node _T_1779 = eq(btb_wr_addr, UInt<8>("h091")) @[ifu_bp_ctl.scala 415:95] - node _T_1780 = and(_T_1779, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1781 = bits(_T_1780, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1779 = eq(btb_wr_addr, UInt<8>("h091")) @[ifu_bp_ctl.scala 416:95] + node _T_1780 = and(_T_1779, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1781 = bits(_T_1780, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_411 of rvclkhdr_505 @[lib.scala 352:23] rvclkhdr_411.clock <= clock rvclkhdr_411.reset <= reset @@ -34384,9 +34384,9 @@ circuit quasar_wrapper : rvclkhdr_411.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_145 : UInt, rvclkhdr_411.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_145 <= btb_wr_data @[lib.scala 358:16] - node _T_1782 = eq(btb_wr_addr, UInt<8>("h092")) @[ifu_bp_ctl.scala 415:95] - node _T_1783 = and(_T_1782, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1784 = bits(_T_1783, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1782 = eq(btb_wr_addr, UInt<8>("h092")) @[ifu_bp_ctl.scala 416:95] + node _T_1783 = and(_T_1782, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1784 = bits(_T_1783, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_412 of rvclkhdr_506 @[lib.scala 352:23] rvclkhdr_412.clock <= clock rvclkhdr_412.reset <= reset @@ -34395,9 +34395,9 @@ circuit quasar_wrapper : rvclkhdr_412.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_146 : UInt, rvclkhdr_412.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_146 <= btb_wr_data @[lib.scala 358:16] - node _T_1785 = eq(btb_wr_addr, UInt<8>("h093")) @[ifu_bp_ctl.scala 415:95] - node _T_1786 = and(_T_1785, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1787 = bits(_T_1786, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1785 = eq(btb_wr_addr, UInt<8>("h093")) @[ifu_bp_ctl.scala 416:95] + node _T_1786 = and(_T_1785, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1787 = bits(_T_1786, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_413 of rvclkhdr_507 @[lib.scala 352:23] rvclkhdr_413.clock <= clock rvclkhdr_413.reset <= reset @@ -34406,9 +34406,9 @@ circuit quasar_wrapper : rvclkhdr_413.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_147 : UInt, rvclkhdr_413.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_147 <= btb_wr_data @[lib.scala 358:16] - node _T_1788 = eq(btb_wr_addr, UInt<8>("h094")) @[ifu_bp_ctl.scala 415:95] - node _T_1789 = and(_T_1788, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1790 = bits(_T_1789, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1788 = eq(btb_wr_addr, UInt<8>("h094")) @[ifu_bp_ctl.scala 416:95] + node _T_1789 = and(_T_1788, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1790 = bits(_T_1789, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_414 of rvclkhdr_508 @[lib.scala 352:23] rvclkhdr_414.clock <= clock rvclkhdr_414.reset <= reset @@ -34417,9 +34417,9 @@ circuit quasar_wrapper : rvclkhdr_414.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_148 : UInt, rvclkhdr_414.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_148 <= btb_wr_data @[lib.scala 358:16] - node _T_1791 = eq(btb_wr_addr, UInt<8>("h095")) @[ifu_bp_ctl.scala 415:95] - node _T_1792 = and(_T_1791, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1793 = bits(_T_1792, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1791 = eq(btb_wr_addr, UInt<8>("h095")) @[ifu_bp_ctl.scala 416:95] + node _T_1792 = and(_T_1791, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1793 = bits(_T_1792, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_415 of rvclkhdr_509 @[lib.scala 352:23] rvclkhdr_415.clock <= clock rvclkhdr_415.reset <= reset @@ -34428,9 +34428,9 @@ circuit quasar_wrapper : rvclkhdr_415.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_149 : UInt, rvclkhdr_415.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_149 <= btb_wr_data @[lib.scala 358:16] - node _T_1794 = eq(btb_wr_addr, UInt<8>("h096")) @[ifu_bp_ctl.scala 415:95] - node _T_1795 = and(_T_1794, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1796 = bits(_T_1795, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1794 = eq(btb_wr_addr, UInt<8>("h096")) @[ifu_bp_ctl.scala 416:95] + node _T_1795 = and(_T_1794, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1796 = bits(_T_1795, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_416 of rvclkhdr_510 @[lib.scala 352:23] rvclkhdr_416.clock <= clock rvclkhdr_416.reset <= reset @@ -34439,9 +34439,9 @@ circuit quasar_wrapper : rvclkhdr_416.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_150 : UInt, rvclkhdr_416.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_150 <= btb_wr_data @[lib.scala 358:16] - node _T_1797 = eq(btb_wr_addr, UInt<8>("h097")) @[ifu_bp_ctl.scala 415:95] - node _T_1798 = and(_T_1797, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1799 = bits(_T_1798, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1797 = eq(btb_wr_addr, UInt<8>("h097")) @[ifu_bp_ctl.scala 416:95] + node _T_1798 = and(_T_1797, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1799 = bits(_T_1798, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_417 of rvclkhdr_511 @[lib.scala 352:23] rvclkhdr_417.clock <= clock rvclkhdr_417.reset <= reset @@ -34450,9 +34450,9 @@ circuit quasar_wrapper : rvclkhdr_417.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_151 : UInt, rvclkhdr_417.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_151 <= btb_wr_data @[lib.scala 358:16] - node _T_1800 = eq(btb_wr_addr, UInt<8>("h098")) @[ifu_bp_ctl.scala 415:95] - node _T_1801 = and(_T_1800, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1802 = bits(_T_1801, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1800 = eq(btb_wr_addr, UInt<8>("h098")) @[ifu_bp_ctl.scala 416:95] + node _T_1801 = and(_T_1800, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1802 = bits(_T_1801, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_418 of rvclkhdr_512 @[lib.scala 352:23] rvclkhdr_418.clock <= clock rvclkhdr_418.reset <= reset @@ -34461,9 +34461,9 @@ circuit quasar_wrapper : rvclkhdr_418.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_152 : UInt, rvclkhdr_418.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_152 <= btb_wr_data @[lib.scala 358:16] - node _T_1803 = eq(btb_wr_addr, UInt<8>("h099")) @[ifu_bp_ctl.scala 415:95] - node _T_1804 = and(_T_1803, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1805 = bits(_T_1804, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1803 = eq(btb_wr_addr, UInt<8>("h099")) @[ifu_bp_ctl.scala 416:95] + node _T_1804 = and(_T_1803, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1805 = bits(_T_1804, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_419 of rvclkhdr_513 @[lib.scala 352:23] rvclkhdr_419.clock <= clock rvclkhdr_419.reset <= reset @@ -34472,9 +34472,9 @@ circuit quasar_wrapper : rvclkhdr_419.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_153 : UInt, rvclkhdr_419.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_153 <= btb_wr_data @[lib.scala 358:16] - node _T_1806 = eq(btb_wr_addr, UInt<8>("h09a")) @[ifu_bp_ctl.scala 415:95] - node _T_1807 = and(_T_1806, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1808 = bits(_T_1807, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1806 = eq(btb_wr_addr, UInt<8>("h09a")) @[ifu_bp_ctl.scala 416:95] + node _T_1807 = and(_T_1806, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1808 = bits(_T_1807, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_420 of rvclkhdr_514 @[lib.scala 352:23] rvclkhdr_420.clock <= clock rvclkhdr_420.reset <= reset @@ -34483,9 +34483,9 @@ circuit quasar_wrapper : rvclkhdr_420.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_154 : UInt, rvclkhdr_420.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_154 <= btb_wr_data @[lib.scala 358:16] - node _T_1809 = eq(btb_wr_addr, UInt<8>("h09b")) @[ifu_bp_ctl.scala 415:95] - node _T_1810 = and(_T_1809, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1811 = bits(_T_1810, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1809 = eq(btb_wr_addr, UInt<8>("h09b")) @[ifu_bp_ctl.scala 416:95] + node _T_1810 = and(_T_1809, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1811 = bits(_T_1810, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_421 of rvclkhdr_515 @[lib.scala 352:23] rvclkhdr_421.clock <= clock rvclkhdr_421.reset <= reset @@ -34494,9 +34494,9 @@ circuit quasar_wrapper : rvclkhdr_421.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_155 : UInt, rvclkhdr_421.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_155 <= btb_wr_data @[lib.scala 358:16] - node _T_1812 = eq(btb_wr_addr, UInt<8>("h09c")) @[ifu_bp_ctl.scala 415:95] - node _T_1813 = and(_T_1812, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1814 = bits(_T_1813, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1812 = eq(btb_wr_addr, UInt<8>("h09c")) @[ifu_bp_ctl.scala 416:95] + node _T_1813 = and(_T_1812, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1814 = bits(_T_1813, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_422 of rvclkhdr_516 @[lib.scala 352:23] rvclkhdr_422.clock <= clock rvclkhdr_422.reset <= reset @@ -34505,9 +34505,9 @@ circuit quasar_wrapper : rvclkhdr_422.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_156 : UInt, rvclkhdr_422.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_156 <= btb_wr_data @[lib.scala 358:16] - node _T_1815 = eq(btb_wr_addr, UInt<8>("h09d")) @[ifu_bp_ctl.scala 415:95] - node _T_1816 = and(_T_1815, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1817 = bits(_T_1816, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1815 = eq(btb_wr_addr, UInt<8>("h09d")) @[ifu_bp_ctl.scala 416:95] + node _T_1816 = and(_T_1815, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1817 = bits(_T_1816, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_423 of rvclkhdr_517 @[lib.scala 352:23] rvclkhdr_423.clock <= clock rvclkhdr_423.reset <= reset @@ -34516,9 +34516,9 @@ circuit quasar_wrapper : rvclkhdr_423.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_157 : UInt, rvclkhdr_423.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_157 <= btb_wr_data @[lib.scala 358:16] - node _T_1818 = eq(btb_wr_addr, UInt<8>("h09e")) @[ifu_bp_ctl.scala 415:95] - node _T_1819 = and(_T_1818, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1820 = bits(_T_1819, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1818 = eq(btb_wr_addr, UInt<8>("h09e")) @[ifu_bp_ctl.scala 416:95] + node _T_1819 = and(_T_1818, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1820 = bits(_T_1819, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_424 of rvclkhdr_518 @[lib.scala 352:23] rvclkhdr_424.clock <= clock rvclkhdr_424.reset <= reset @@ -34527,9 +34527,9 @@ circuit quasar_wrapper : rvclkhdr_424.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_158 : UInt, rvclkhdr_424.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_158 <= btb_wr_data @[lib.scala 358:16] - node _T_1821 = eq(btb_wr_addr, UInt<8>("h09f")) @[ifu_bp_ctl.scala 415:95] - node _T_1822 = and(_T_1821, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1823 = bits(_T_1822, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1821 = eq(btb_wr_addr, UInt<8>("h09f")) @[ifu_bp_ctl.scala 416:95] + node _T_1822 = and(_T_1821, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1823 = bits(_T_1822, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_425 of rvclkhdr_519 @[lib.scala 352:23] rvclkhdr_425.clock <= clock rvclkhdr_425.reset <= reset @@ -34538,9 +34538,9 @@ circuit quasar_wrapper : rvclkhdr_425.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_159 : UInt, rvclkhdr_425.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_159 <= btb_wr_data @[lib.scala 358:16] - node _T_1824 = eq(btb_wr_addr, UInt<8>("h0a0")) @[ifu_bp_ctl.scala 415:95] - node _T_1825 = and(_T_1824, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1826 = bits(_T_1825, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1824 = eq(btb_wr_addr, UInt<8>("h0a0")) @[ifu_bp_ctl.scala 416:95] + node _T_1825 = and(_T_1824, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1826 = bits(_T_1825, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_426 of rvclkhdr_520 @[lib.scala 352:23] rvclkhdr_426.clock <= clock rvclkhdr_426.reset <= reset @@ -34549,9 +34549,9 @@ circuit quasar_wrapper : rvclkhdr_426.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_160 : UInt, rvclkhdr_426.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_160 <= btb_wr_data @[lib.scala 358:16] - node _T_1827 = eq(btb_wr_addr, UInt<8>("h0a1")) @[ifu_bp_ctl.scala 415:95] - node _T_1828 = and(_T_1827, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1829 = bits(_T_1828, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1827 = eq(btb_wr_addr, UInt<8>("h0a1")) @[ifu_bp_ctl.scala 416:95] + node _T_1828 = and(_T_1827, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1829 = bits(_T_1828, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_427 of rvclkhdr_521 @[lib.scala 352:23] rvclkhdr_427.clock <= clock rvclkhdr_427.reset <= reset @@ -34560,9 +34560,9 @@ circuit quasar_wrapper : rvclkhdr_427.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_161 : UInt, rvclkhdr_427.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_161 <= btb_wr_data @[lib.scala 358:16] - node _T_1830 = eq(btb_wr_addr, UInt<8>("h0a2")) @[ifu_bp_ctl.scala 415:95] - node _T_1831 = and(_T_1830, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1832 = bits(_T_1831, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1830 = eq(btb_wr_addr, UInt<8>("h0a2")) @[ifu_bp_ctl.scala 416:95] + node _T_1831 = and(_T_1830, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1832 = bits(_T_1831, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_428 of rvclkhdr_522 @[lib.scala 352:23] rvclkhdr_428.clock <= clock rvclkhdr_428.reset <= reset @@ -34571,9 +34571,9 @@ circuit quasar_wrapper : rvclkhdr_428.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_162 : UInt, rvclkhdr_428.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_162 <= btb_wr_data @[lib.scala 358:16] - node _T_1833 = eq(btb_wr_addr, UInt<8>("h0a3")) @[ifu_bp_ctl.scala 415:95] - node _T_1834 = and(_T_1833, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1835 = bits(_T_1834, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1833 = eq(btb_wr_addr, UInt<8>("h0a3")) @[ifu_bp_ctl.scala 416:95] + node _T_1834 = and(_T_1833, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1835 = bits(_T_1834, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_429 of rvclkhdr_523 @[lib.scala 352:23] rvclkhdr_429.clock <= clock rvclkhdr_429.reset <= reset @@ -34582,9 +34582,9 @@ circuit quasar_wrapper : rvclkhdr_429.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_163 : UInt, rvclkhdr_429.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_163 <= btb_wr_data @[lib.scala 358:16] - node _T_1836 = eq(btb_wr_addr, UInt<8>("h0a4")) @[ifu_bp_ctl.scala 415:95] - node _T_1837 = and(_T_1836, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1838 = bits(_T_1837, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1836 = eq(btb_wr_addr, UInt<8>("h0a4")) @[ifu_bp_ctl.scala 416:95] + node _T_1837 = and(_T_1836, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1838 = bits(_T_1837, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_430 of rvclkhdr_524 @[lib.scala 352:23] rvclkhdr_430.clock <= clock rvclkhdr_430.reset <= reset @@ -34593,9 +34593,9 @@ circuit quasar_wrapper : rvclkhdr_430.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_164 : UInt, rvclkhdr_430.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_164 <= btb_wr_data @[lib.scala 358:16] - node _T_1839 = eq(btb_wr_addr, UInt<8>("h0a5")) @[ifu_bp_ctl.scala 415:95] - node _T_1840 = and(_T_1839, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1841 = bits(_T_1840, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1839 = eq(btb_wr_addr, UInt<8>("h0a5")) @[ifu_bp_ctl.scala 416:95] + node _T_1840 = and(_T_1839, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1841 = bits(_T_1840, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_431 of rvclkhdr_525 @[lib.scala 352:23] rvclkhdr_431.clock <= clock rvclkhdr_431.reset <= reset @@ -34604,9 +34604,9 @@ circuit quasar_wrapper : rvclkhdr_431.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_165 : UInt, rvclkhdr_431.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_165 <= btb_wr_data @[lib.scala 358:16] - node _T_1842 = eq(btb_wr_addr, UInt<8>("h0a6")) @[ifu_bp_ctl.scala 415:95] - node _T_1843 = and(_T_1842, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1844 = bits(_T_1843, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1842 = eq(btb_wr_addr, UInt<8>("h0a6")) @[ifu_bp_ctl.scala 416:95] + node _T_1843 = and(_T_1842, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1844 = bits(_T_1843, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_432 of rvclkhdr_526 @[lib.scala 352:23] rvclkhdr_432.clock <= clock rvclkhdr_432.reset <= reset @@ -34615,9 +34615,9 @@ circuit quasar_wrapper : rvclkhdr_432.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_166 : UInt, rvclkhdr_432.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_166 <= btb_wr_data @[lib.scala 358:16] - node _T_1845 = eq(btb_wr_addr, UInt<8>("h0a7")) @[ifu_bp_ctl.scala 415:95] - node _T_1846 = and(_T_1845, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1847 = bits(_T_1846, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1845 = eq(btb_wr_addr, UInt<8>("h0a7")) @[ifu_bp_ctl.scala 416:95] + node _T_1846 = and(_T_1845, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1847 = bits(_T_1846, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_433 of rvclkhdr_527 @[lib.scala 352:23] rvclkhdr_433.clock <= clock rvclkhdr_433.reset <= reset @@ -34626,9 +34626,9 @@ circuit quasar_wrapper : rvclkhdr_433.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_167 : UInt, rvclkhdr_433.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_167 <= btb_wr_data @[lib.scala 358:16] - node _T_1848 = eq(btb_wr_addr, UInt<8>("h0a8")) @[ifu_bp_ctl.scala 415:95] - node _T_1849 = and(_T_1848, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1850 = bits(_T_1849, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1848 = eq(btb_wr_addr, UInt<8>("h0a8")) @[ifu_bp_ctl.scala 416:95] + node _T_1849 = and(_T_1848, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1850 = bits(_T_1849, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_434 of rvclkhdr_528 @[lib.scala 352:23] rvclkhdr_434.clock <= clock rvclkhdr_434.reset <= reset @@ -34637,9 +34637,9 @@ circuit quasar_wrapper : rvclkhdr_434.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_168 : UInt, rvclkhdr_434.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_168 <= btb_wr_data @[lib.scala 358:16] - node _T_1851 = eq(btb_wr_addr, UInt<8>("h0a9")) @[ifu_bp_ctl.scala 415:95] - node _T_1852 = and(_T_1851, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1853 = bits(_T_1852, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1851 = eq(btb_wr_addr, UInt<8>("h0a9")) @[ifu_bp_ctl.scala 416:95] + node _T_1852 = and(_T_1851, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1853 = bits(_T_1852, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_435 of rvclkhdr_529 @[lib.scala 352:23] rvclkhdr_435.clock <= clock rvclkhdr_435.reset <= reset @@ -34648,9 +34648,9 @@ circuit quasar_wrapper : rvclkhdr_435.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_169 : UInt, rvclkhdr_435.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_169 <= btb_wr_data @[lib.scala 358:16] - node _T_1854 = eq(btb_wr_addr, UInt<8>("h0aa")) @[ifu_bp_ctl.scala 415:95] - node _T_1855 = and(_T_1854, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1856 = bits(_T_1855, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1854 = eq(btb_wr_addr, UInt<8>("h0aa")) @[ifu_bp_ctl.scala 416:95] + node _T_1855 = and(_T_1854, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1856 = bits(_T_1855, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_436 of rvclkhdr_530 @[lib.scala 352:23] rvclkhdr_436.clock <= clock rvclkhdr_436.reset <= reset @@ -34659,9 +34659,9 @@ circuit quasar_wrapper : rvclkhdr_436.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_170 : UInt, rvclkhdr_436.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_170 <= btb_wr_data @[lib.scala 358:16] - node _T_1857 = eq(btb_wr_addr, UInt<8>("h0ab")) @[ifu_bp_ctl.scala 415:95] - node _T_1858 = and(_T_1857, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1859 = bits(_T_1858, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1857 = eq(btb_wr_addr, UInt<8>("h0ab")) @[ifu_bp_ctl.scala 416:95] + node _T_1858 = and(_T_1857, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1859 = bits(_T_1858, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_437 of rvclkhdr_531 @[lib.scala 352:23] rvclkhdr_437.clock <= clock rvclkhdr_437.reset <= reset @@ -34670,9 +34670,9 @@ circuit quasar_wrapper : rvclkhdr_437.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_171 : UInt, rvclkhdr_437.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_171 <= btb_wr_data @[lib.scala 358:16] - node _T_1860 = eq(btb_wr_addr, UInt<8>("h0ac")) @[ifu_bp_ctl.scala 415:95] - node _T_1861 = and(_T_1860, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1862 = bits(_T_1861, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1860 = eq(btb_wr_addr, UInt<8>("h0ac")) @[ifu_bp_ctl.scala 416:95] + node _T_1861 = and(_T_1860, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1862 = bits(_T_1861, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_438 of rvclkhdr_532 @[lib.scala 352:23] rvclkhdr_438.clock <= clock rvclkhdr_438.reset <= reset @@ -34681,9 +34681,9 @@ circuit quasar_wrapper : rvclkhdr_438.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_172 : UInt, rvclkhdr_438.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_172 <= btb_wr_data @[lib.scala 358:16] - node _T_1863 = eq(btb_wr_addr, UInt<8>("h0ad")) @[ifu_bp_ctl.scala 415:95] - node _T_1864 = and(_T_1863, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1865 = bits(_T_1864, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1863 = eq(btb_wr_addr, UInt<8>("h0ad")) @[ifu_bp_ctl.scala 416:95] + node _T_1864 = and(_T_1863, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1865 = bits(_T_1864, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_439 of rvclkhdr_533 @[lib.scala 352:23] rvclkhdr_439.clock <= clock rvclkhdr_439.reset <= reset @@ -34692,9 +34692,9 @@ circuit quasar_wrapper : rvclkhdr_439.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_173 : UInt, rvclkhdr_439.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_173 <= btb_wr_data @[lib.scala 358:16] - node _T_1866 = eq(btb_wr_addr, UInt<8>("h0ae")) @[ifu_bp_ctl.scala 415:95] - node _T_1867 = and(_T_1866, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1868 = bits(_T_1867, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1866 = eq(btb_wr_addr, UInt<8>("h0ae")) @[ifu_bp_ctl.scala 416:95] + node _T_1867 = and(_T_1866, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1868 = bits(_T_1867, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_440 of rvclkhdr_534 @[lib.scala 352:23] rvclkhdr_440.clock <= clock rvclkhdr_440.reset <= reset @@ -34703,9 +34703,9 @@ circuit quasar_wrapper : rvclkhdr_440.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_174 : UInt, rvclkhdr_440.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_174 <= btb_wr_data @[lib.scala 358:16] - node _T_1869 = eq(btb_wr_addr, UInt<8>("h0af")) @[ifu_bp_ctl.scala 415:95] - node _T_1870 = and(_T_1869, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1871 = bits(_T_1870, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1869 = eq(btb_wr_addr, UInt<8>("h0af")) @[ifu_bp_ctl.scala 416:95] + node _T_1870 = and(_T_1869, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1871 = bits(_T_1870, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_441 of rvclkhdr_535 @[lib.scala 352:23] rvclkhdr_441.clock <= clock rvclkhdr_441.reset <= reset @@ -34714,9 +34714,9 @@ circuit quasar_wrapper : rvclkhdr_441.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_175 : UInt, rvclkhdr_441.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_175 <= btb_wr_data @[lib.scala 358:16] - node _T_1872 = eq(btb_wr_addr, UInt<8>("h0b0")) @[ifu_bp_ctl.scala 415:95] - node _T_1873 = and(_T_1872, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1874 = bits(_T_1873, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1872 = eq(btb_wr_addr, UInt<8>("h0b0")) @[ifu_bp_ctl.scala 416:95] + node _T_1873 = and(_T_1872, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1874 = bits(_T_1873, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_442 of rvclkhdr_536 @[lib.scala 352:23] rvclkhdr_442.clock <= clock rvclkhdr_442.reset <= reset @@ -34725,9 +34725,9 @@ circuit quasar_wrapper : rvclkhdr_442.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_176 : UInt, rvclkhdr_442.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_176 <= btb_wr_data @[lib.scala 358:16] - node _T_1875 = eq(btb_wr_addr, UInt<8>("h0b1")) @[ifu_bp_ctl.scala 415:95] - node _T_1876 = and(_T_1875, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1877 = bits(_T_1876, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1875 = eq(btb_wr_addr, UInt<8>("h0b1")) @[ifu_bp_ctl.scala 416:95] + node _T_1876 = and(_T_1875, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1877 = bits(_T_1876, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_443 of rvclkhdr_537 @[lib.scala 352:23] rvclkhdr_443.clock <= clock rvclkhdr_443.reset <= reset @@ -34736,9 +34736,9 @@ circuit quasar_wrapper : rvclkhdr_443.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_177 : UInt, rvclkhdr_443.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_177 <= btb_wr_data @[lib.scala 358:16] - node _T_1878 = eq(btb_wr_addr, UInt<8>("h0b2")) @[ifu_bp_ctl.scala 415:95] - node _T_1879 = and(_T_1878, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1880 = bits(_T_1879, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1878 = eq(btb_wr_addr, UInt<8>("h0b2")) @[ifu_bp_ctl.scala 416:95] + node _T_1879 = and(_T_1878, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1880 = bits(_T_1879, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_444 of rvclkhdr_538 @[lib.scala 352:23] rvclkhdr_444.clock <= clock rvclkhdr_444.reset <= reset @@ -34747,9 +34747,9 @@ circuit quasar_wrapper : rvclkhdr_444.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_178 : UInt, rvclkhdr_444.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_178 <= btb_wr_data @[lib.scala 358:16] - node _T_1881 = eq(btb_wr_addr, UInt<8>("h0b3")) @[ifu_bp_ctl.scala 415:95] - node _T_1882 = and(_T_1881, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1883 = bits(_T_1882, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1881 = eq(btb_wr_addr, UInt<8>("h0b3")) @[ifu_bp_ctl.scala 416:95] + node _T_1882 = and(_T_1881, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1883 = bits(_T_1882, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_445 of rvclkhdr_539 @[lib.scala 352:23] rvclkhdr_445.clock <= clock rvclkhdr_445.reset <= reset @@ -34758,9 +34758,9 @@ circuit quasar_wrapper : rvclkhdr_445.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_179 : UInt, rvclkhdr_445.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_179 <= btb_wr_data @[lib.scala 358:16] - node _T_1884 = eq(btb_wr_addr, UInt<8>("h0b4")) @[ifu_bp_ctl.scala 415:95] - node _T_1885 = and(_T_1884, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1886 = bits(_T_1885, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1884 = eq(btb_wr_addr, UInt<8>("h0b4")) @[ifu_bp_ctl.scala 416:95] + node _T_1885 = and(_T_1884, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1886 = bits(_T_1885, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_446 of rvclkhdr_540 @[lib.scala 352:23] rvclkhdr_446.clock <= clock rvclkhdr_446.reset <= reset @@ -34769,9 +34769,9 @@ circuit quasar_wrapper : rvclkhdr_446.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_180 : UInt, rvclkhdr_446.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_180 <= btb_wr_data @[lib.scala 358:16] - node _T_1887 = eq(btb_wr_addr, UInt<8>("h0b5")) @[ifu_bp_ctl.scala 415:95] - node _T_1888 = and(_T_1887, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1889 = bits(_T_1888, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1887 = eq(btb_wr_addr, UInt<8>("h0b5")) @[ifu_bp_ctl.scala 416:95] + node _T_1888 = and(_T_1887, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1889 = bits(_T_1888, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_447 of rvclkhdr_541 @[lib.scala 352:23] rvclkhdr_447.clock <= clock rvclkhdr_447.reset <= reset @@ -34780,9 +34780,9 @@ circuit quasar_wrapper : rvclkhdr_447.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_181 : UInt, rvclkhdr_447.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_181 <= btb_wr_data @[lib.scala 358:16] - node _T_1890 = eq(btb_wr_addr, UInt<8>("h0b6")) @[ifu_bp_ctl.scala 415:95] - node _T_1891 = and(_T_1890, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1892 = bits(_T_1891, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1890 = eq(btb_wr_addr, UInt<8>("h0b6")) @[ifu_bp_ctl.scala 416:95] + node _T_1891 = and(_T_1890, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1892 = bits(_T_1891, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_448 of rvclkhdr_542 @[lib.scala 352:23] rvclkhdr_448.clock <= clock rvclkhdr_448.reset <= reset @@ -34791,9 +34791,9 @@ circuit quasar_wrapper : rvclkhdr_448.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_182 : UInt, rvclkhdr_448.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_182 <= btb_wr_data @[lib.scala 358:16] - node _T_1893 = eq(btb_wr_addr, UInt<8>("h0b7")) @[ifu_bp_ctl.scala 415:95] - node _T_1894 = and(_T_1893, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1895 = bits(_T_1894, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1893 = eq(btb_wr_addr, UInt<8>("h0b7")) @[ifu_bp_ctl.scala 416:95] + node _T_1894 = and(_T_1893, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1895 = bits(_T_1894, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_449 of rvclkhdr_543 @[lib.scala 352:23] rvclkhdr_449.clock <= clock rvclkhdr_449.reset <= reset @@ -34802,9 +34802,9 @@ circuit quasar_wrapper : rvclkhdr_449.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_183 : UInt, rvclkhdr_449.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_183 <= btb_wr_data @[lib.scala 358:16] - node _T_1896 = eq(btb_wr_addr, UInt<8>("h0b8")) @[ifu_bp_ctl.scala 415:95] - node _T_1897 = and(_T_1896, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1898 = bits(_T_1897, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1896 = eq(btb_wr_addr, UInt<8>("h0b8")) @[ifu_bp_ctl.scala 416:95] + node _T_1897 = and(_T_1896, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1898 = bits(_T_1897, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_450 of rvclkhdr_544 @[lib.scala 352:23] rvclkhdr_450.clock <= clock rvclkhdr_450.reset <= reset @@ -34813,9 +34813,9 @@ circuit quasar_wrapper : rvclkhdr_450.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_184 : UInt, rvclkhdr_450.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_184 <= btb_wr_data @[lib.scala 358:16] - node _T_1899 = eq(btb_wr_addr, UInt<8>("h0b9")) @[ifu_bp_ctl.scala 415:95] - node _T_1900 = and(_T_1899, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1901 = bits(_T_1900, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1899 = eq(btb_wr_addr, UInt<8>("h0b9")) @[ifu_bp_ctl.scala 416:95] + node _T_1900 = and(_T_1899, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1901 = bits(_T_1900, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_451 of rvclkhdr_545 @[lib.scala 352:23] rvclkhdr_451.clock <= clock rvclkhdr_451.reset <= reset @@ -34824,9 +34824,9 @@ circuit quasar_wrapper : rvclkhdr_451.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_185 : UInt, rvclkhdr_451.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_185 <= btb_wr_data @[lib.scala 358:16] - node _T_1902 = eq(btb_wr_addr, UInt<8>("h0ba")) @[ifu_bp_ctl.scala 415:95] - node _T_1903 = and(_T_1902, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1904 = bits(_T_1903, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1902 = eq(btb_wr_addr, UInt<8>("h0ba")) @[ifu_bp_ctl.scala 416:95] + node _T_1903 = and(_T_1902, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1904 = bits(_T_1903, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_452 of rvclkhdr_546 @[lib.scala 352:23] rvclkhdr_452.clock <= clock rvclkhdr_452.reset <= reset @@ -34835,9 +34835,9 @@ circuit quasar_wrapper : rvclkhdr_452.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_186 : UInt, rvclkhdr_452.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_186 <= btb_wr_data @[lib.scala 358:16] - node _T_1905 = eq(btb_wr_addr, UInt<8>("h0bb")) @[ifu_bp_ctl.scala 415:95] - node _T_1906 = and(_T_1905, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1907 = bits(_T_1906, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1905 = eq(btb_wr_addr, UInt<8>("h0bb")) @[ifu_bp_ctl.scala 416:95] + node _T_1906 = and(_T_1905, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1907 = bits(_T_1906, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_453 of rvclkhdr_547 @[lib.scala 352:23] rvclkhdr_453.clock <= clock rvclkhdr_453.reset <= reset @@ -34846,9 +34846,9 @@ circuit quasar_wrapper : rvclkhdr_453.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_187 : UInt, rvclkhdr_453.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_187 <= btb_wr_data @[lib.scala 358:16] - node _T_1908 = eq(btb_wr_addr, UInt<8>("h0bc")) @[ifu_bp_ctl.scala 415:95] - node _T_1909 = and(_T_1908, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1910 = bits(_T_1909, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1908 = eq(btb_wr_addr, UInt<8>("h0bc")) @[ifu_bp_ctl.scala 416:95] + node _T_1909 = and(_T_1908, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1910 = bits(_T_1909, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_454 of rvclkhdr_548 @[lib.scala 352:23] rvclkhdr_454.clock <= clock rvclkhdr_454.reset <= reset @@ -34857,9 +34857,9 @@ circuit quasar_wrapper : rvclkhdr_454.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_188 : UInt, rvclkhdr_454.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_188 <= btb_wr_data @[lib.scala 358:16] - node _T_1911 = eq(btb_wr_addr, UInt<8>("h0bd")) @[ifu_bp_ctl.scala 415:95] - node _T_1912 = and(_T_1911, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1913 = bits(_T_1912, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1911 = eq(btb_wr_addr, UInt<8>("h0bd")) @[ifu_bp_ctl.scala 416:95] + node _T_1912 = and(_T_1911, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1913 = bits(_T_1912, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_455 of rvclkhdr_549 @[lib.scala 352:23] rvclkhdr_455.clock <= clock rvclkhdr_455.reset <= reset @@ -34868,9 +34868,9 @@ circuit quasar_wrapper : rvclkhdr_455.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_189 : UInt, rvclkhdr_455.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_189 <= btb_wr_data @[lib.scala 358:16] - node _T_1914 = eq(btb_wr_addr, UInt<8>("h0be")) @[ifu_bp_ctl.scala 415:95] - node _T_1915 = and(_T_1914, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1916 = bits(_T_1915, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1914 = eq(btb_wr_addr, UInt<8>("h0be")) @[ifu_bp_ctl.scala 416:95] + node _T_1915 = and(_T_1914, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1916 = bits(_T_1915, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_456 of rvclkhdr_550 @[lib.scala 352:23] rvclkhdr_456.clock <= clock rvclkhdr_456.reset <= reset @@ -34879,9 +34879,9 @@ circuit quasar_wrapper : rvclkhdr_456.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_190 : UInt, rvclkhdr_456.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_190 <= btb_wr_data @[lib.scala 358:16] - node _T_1917 = eq(btb_wr_addr, UInt<8>("h0bf")) @[ifu_bp_ctl.scala 415:95] - node _T_1918 = and(_T_1917, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1919 = bits(_T_1918, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1917 = eq(btb_wr_addr, UInt<8>("h0bf")) @[ifu_bp_ctl.scala 416:95] + node _T_1918 = and(_T_1917, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1919 = bits(_T_1918, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_457 of rvclkhdr_551 @[lib.scala 352:23] rvclkhdr_457.clock <= clock rvclkhdr_457.reset <= reset @@ -34890,9 +34890,9 @@ circuit quasar_wrapper : rvclkhdr_457.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_191 : UInt, rvclkhdr_457.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_191 <= btb_wr_data @[lib.scala 358:16] - node _T_1920 = eq(btb_wr_addr, UInt<8>("h0c0")) @[ifu_bp_ctl.scala 415:95] - node _T_1921 = and(_T_1920, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1922 = bits(_T_1921, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1920 = eq(btb_wr_addr, UInt<8>("h0c0")) @[ifu_bp_ctl.scala 416:95] + node _T_1921 = and(_T_1920, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1922 = bits(_T_1921, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_458 of rvclkhdr_552 @[lib.scala 352:23] rvclkhdr_458.clock <= clock rvclkhdr_458.reset <= reset @@ -34901,9 +34901,9 @@ circuit quasar_wrapper : rvclkhdr_458.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_192 : UInt, rvclkhdr_458.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_192 <= btb_wr_data @[lib.scala 358:16] - node _T_1923 = eq(btb_wr_addr, UInt<8>("h0c1")) @[ifu_bp_ctl.scala 415:95] - node _T_1924 = and(_T_1923, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1925 = bits(_T_1924, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1923 = eq(btb_wr_addr, UInt<8>("h0c1")) @[ifu_bp_ctl.scala 416:95] + node _T_1924 = and(_T_1923, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1925 = bits(_T_1924, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_459 of rvclkhdr_553 @[lib.scala 352:23] rvclkhdr_459.clock <= clock rvclkhdr_459.reset <= reset @@ -34912,9 +34912,9 @@ circuit quasar_wrapper : rvclkhdr_459.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_193 : UInt, rvclkhdr_459.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_193 <= btb_wr_data @[lib.scala 358:16] - node _T_1926 = eq(btb_wr_addr, UInt<8>("h0c2")) @[ifu_bp_ctl.scala 415:95] - node _T_1927 = and(_T_1926, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1928 = bits(_T_1927, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1926 = eq(btb_wr_addr, UInt<8>("h0c2")) @[ifu_bp_ctl.scala 416:95] + node _T_1927 = and(_T_1926, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1928 = bits(_T_1927, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_460 of rvclkhdr_554 @[lib.scala 352:23] rvclkhdr_460.clock <= clock rvclkhdr_460.reset <= reset @@ -34923,9 +34923,9 @@ circuit quasar_wrapper : rvclkhdr_460.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_194 : UInt, rvclkhdr_460.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_194 <= btb_wr_data @[lib.scala 358:16] - node _T_1929 = eq(btb_wr_addr, UInt<8>("h0c3")) @[ifu_bp_ctl.scala 415:95] - node _T_1930 = and(_T_1929, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1931 = bits(_T_1930, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1929 = eq(btb_wr_addr, UInt<8>("h0c3")) @[ifu_bp_ctl.scala 416:95] + node _T_1930 = and(_T_1929, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1931 = bits(_T_1930, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_461 of rvclkhdr_555 @[lib.scala 352:23] rvclkhdr_461.clock <= clock rvclkhdr_461.reset <= reset @@ -34934,9 +34934,9 @@ circuit quasar_wrapper : rvclkhdr_461.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_195 : UInt, rvclkhdr_461.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_195 <= btb_wr_data @[lib.scala 358:16] - node _T_1932 = eq(btb_wr_addr, UInt<8>("h0c4")) @[ifu_bp_ctl.scala 415:95] - node _T_1933 = and(_T_1932, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1934 = bits(_T_1933, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1932 = eq(btb_wr_addr, UInt<8>("h0c4")) @[ifu_bp_ctl.scala 416:95] + node _T_1933 = and(_T_1932, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1934 = bits(_T_1933, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_462 of rvclkhdr_556 @[lib.scala 352:23] rvclkhdr_462.clock <= clock rvclkhdr_462.reset <= reset @@ -34945,9 +34945,9 @@ circuit quasar_wrapper : rvclkhdr_462.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_196 : UInt, rvclkhdr_462.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_196 <= btb_wr_data @[lib.scala 358:16] - node _T_1935 = eq(btb_wr_addr, UInt<8>("h0c5")) @[ifu_bp_ctl.scala 415:95] - node _T_1936 = and(_T_1935, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1937 = bits(_T_1936, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1935 = eq(btb_wr_addr, UInt<8>("h0c5")) @[ifu_bp_ctl.scala 416:95] + node _T_1936 = and(_T_1935, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1937 = bits(_T_1936, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_463 of rvclkhdr_557 @[lib.scala 352:23] rvclkhdr_463.clock <= clock rvclkhdr_463.reset <= reset @@ -34956,9 +34956,9 @@ circuit quasar_wrapper : rvclkhdr_463.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_197 : UInt, rvclkhdr_463.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_197 <= btb_wr_data @[lib.scala 358:16] - node _T_1938 = eq(btb_wr_addr, UInt<8>("h0c6")) @[ifu_bp_ctl.scala 415:95] - node _T_1939 = and(_T_1938, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1940 = bits(_T_1939, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1938 = eq(btb_wr_addr, UInt<8>("h0c6")) @[ifu_bp_ctl.scala 416:95] + node _T_1939 = and(_T_1938, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1940 = bits(_T_1939, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_464 of rvclkhdr_558 @[lib.scala 352:23] rvclkhdr_464.clock <= clock rvclkhdr_464.reset <= reset @@ -34967,9 +34967,9 @@ circuit quasar_wrapper : rvclkhdr_464.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_198 : UInt, rvclkhdr_464.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_198 <= btb_wr_data @[lib.scala 358:16] - node _T_1941 = eq(btb_wr_addr, UInt<8>("h0c7")) @[ifu_bp_ctl.scala 415:95] - node _T_1942 = and(_T_1941, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1943 = bits(_T_1942, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1941 = eq(btb_wr_addr, UInt<8>("h0c7")) @[ifu_bp_ctl.scala 416:95] + node _T_1942 = and(_T_1941, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1943 = bits(_T_1942, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_465 of rvclkhdr_559 @[lib.scala 352:23] rvclkhdr_465.clock <= clock rvclkhdr_465.reset <= reset @@ -34978,9 +34978,9 @@ circuit quasar_wrapper : rvclkhdr_465.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_199 : UInt, rvclkhdr_465.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_199 <= btb_wr_data @[lib.scala 358:16] - node _T_1944 = eq(btb_wr_addr, UInt<8>("h0c8")) @[ifu_bp_ctl.scala 415:95] - node _T_1945 = and(_T_1944, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1946 = bits(_T_1945, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1944 = eq(btb_wr_addr, UInt<8>("h0c8")) @[ifu_bp_ctl.scala 416:95] + node _T_1945 = and(_T_1944, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1946 = bits(_T_1945, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_466 of rvclkhdr_560 @[lib.scala 352:23] rvclkhdr_466.clock <= clock rvclkhdr_466.reset <= reset @@ -34989,9 +34989,9 @@ circuit quasar_wrapper : rvclkhdr_466.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_200 : UInt, rvclkhdr_466.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_200 <= btb_wr_data @[lib.scala 358:16] - node _T_1947 = eq(btb_wr_addr, UInt<8>("h0c9")) @[ifu_bp_ctl.scala 415:95] - node _T_1948 = and(_T_1947, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1949 = bits(_T_1948, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1947 = eq(btb_wr_addr, UInt<8>("h0c9")) @[ifu_bp_ctl.scala 416:95] + node _T_1948 = and(_T_1947, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1949 = bits(_T_1948, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_467 of rvclkhdr_561 @[lib.scala 352:23] rvclkhdr_467.clock <= clock rvclkhdr_467.reset <= reset @@ -35000,9 +35000,9 @@ circuit quasar_wrapper : rvclkhdr_467.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_201 : UInt, rvclkhdr_467.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_201 <= btb_wr_data @[lib.scala 358:16] - node _T_1950 = eq(btb_wr_addr, UInt<8>("h0ca")) @[ifu_bp_ctl.scala 415:95] - node _T_1951 = and(_T_1950, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1952 = bits(_T_1951, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1950 = eq(btb_wr_addr, UInt<8>("h0ca")) @[ifu_bp_ctl.scala 416:95] + node _T_1951 = and(_T_1950, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1952 = bits(_T_1951, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_468 of rvclkhdr_562 @[lib.scala 352:23] rvclkhdr_468.clock <= clock rvclkhdr_468.reset <= reset @@ -35011,9 +35011,9 @@ circuit quasar_wrapper : rvclkhdr_468.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_202 : UInt, rvclkhdr_468.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_202 <= btb_wr_data @[lib.scala 358:16] - node _T_1953 = eq(btb_wr_addr, UInt<8>("h0cb")) @[ifu_bp_ctl.scala 415:95] - node _T_1954 = and(_T_1953, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1955 = bits(_T_1954, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1953 = eq(btb_wr_addr, UInt<8>("h0cb")) @[ifu_bp_ctl.scala 416:95] + node _T_1954 = and(_T_1953, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1955 = bits(_T_1954, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_469 of rvclkhdr_563 @[lib.scala 352:23] rvclkhdr_469.clock <= clock rvclkhdr_469.reset <= reset @@ -35022,9 +35022,9 @@ circuit quasar_wrapper : rvclkhdr_469.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_203 : UInt, rvclkhdr_469.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_203 <= btb_wr_data @[lib.scala 358:16] - node _T_1956 = eq(btb_wr_addr, UInt<8>("h0cc")) @[ifu_bp_ctl.scala 415:95] - node _T_1957 = and(_T_1956, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1958 = bits(_T_1957, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1956 = eq(btb_wr_addr, UInt<8>("h0cc")) @[ifu_bp_ctl.scala 416:95] + node _T_1957 = and(_T_1956, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1958 = bits(_T_1957, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_470 of rvclkhdr_564 @[lib.scala 352:23] rvclkhdr_470.clock <= clock rvclkhdr_470.reset <= reset @@ -35033,9 +35033,9 @@ circuit quasar_wrapper : rvclkhdr_470.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_204 : UInt, rvclkhdr_470.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_204 <= btb_wr_data @[lib.scala 358:16] - node _T_1959 = eq(btb_wr_addr, UInt<8>("h0cd")) @[ifu_bp_ctl.scala 415:95] - node _T_1960 = and(_T_1959, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1961 = bits(_T_1960, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1959 = eq(btb_wr_addr, UInt<8>("h0cd")) @[ifu_bp_ctl.scala 416:95] + node _T_1960 = and(_T_1959, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1961 = bits(_T_1960, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_471 of rvclkhdr_565 @[lib.scala 352:23] rvclkhdr_471.clock <= clock rvclkhdr_471.reset <= reset @@ -35044,9 +35044,9 @@ circuit quasar_wrapper : rvclkhdr_471.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_205 : UInt, rvclkhdr_471.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_205 <= btb_wr_data @[lib.scala 358:16] - node _T_1962 = eq(btb_wr_addr, UInt<8>("h0ce")) @[ifu_bp_ctl.scala 415:95] - node _T_1963 = and(_T_1962, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1964 = bits(_T_1963, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1962 = eq(btb_wr_addr, UInt<8>("h0ce")) @[ifu_bp_ctl.scala 416:95] + node _T_1963 = and(_T_1962, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1964 = bits(_T_1963, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_472 of rvclkhdr_566 @[lib.scala 352:23] rvclkhdr_472.clock <= clock rvclkhdr_472.reset <= reset @@ -35055,9 +35055,9 @@ circuit quasar_wrapper : rvclkhdr_472.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_206 : UInt, rvclkhdr_472.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_206 <= btb_wr_data @[lib.scala 358:16] - node _T_1965 = eq(btb_wr_addr, UInt<8>("h0cf")) @[ifu_bp_ctl.scala 415:95] - node _T_1966 = and(_T_1965, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1967 = bits(_T_1966, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1965 = eq(btb_wr_addr, UInt<8>("h0cf")) @[ifu_bp_ctl.scala 416:95] + node _T_1966 = and(_T_1965, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1967 = bits(_T_1966, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_473 of rvclkhdr_567 @[lib.scala 352:23] rvclkhdr_473.clock <= clock rvclkhdr_473.reset <= reset @@ -35066,9 +35066,9 @@ circuit quasar_wrapper : rvclkhdr_473.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_207 : UInt, rvclkhdr_473.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_207 <= btb_wr_data @[lib.scala 358:16] - node _T_1968 = eq(btb_wr_addr, UInt<8>("h0d0")) @[ifu_bp_ctl.scala 415:95] - node _T_1969 = and(_T_1968, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1970 = bits(_T_1969, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1968 = eq(btb_wr_addr, UInt<8>("h0d0")) @[ifu_bp_ctl.scala 416:95] + node _T_1969 = and(_T_1968, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1970 = bits(_T_1969, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_474 of rvclkhdr_568 @[lib.scala 352:23] rvclkhdr_474.clock <= clock rvclkhdr_474.reset <= reset @@ -35077,9 +35077,9 @@ circuit quasar_wrapper : rvclkhdr_474.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_208 : UInt, rvclkhdr_474.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_208 <= btb_wr_data @[lib.scala 358:16] - node _T_1971 = eq(btb_wr_addr, UInt<8>("h0d1")) @[ifu_bp_ctl.scala 415:95] - node _T_1972 = and(_T_1971, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1973 = bits(_T_1972, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1971 = eq(btb_wr_addr, UInt<8>("h0d1")) @[ifu_bp_ctl.scala 416:95] + node _T_1972 = and(_T_1971, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1973 = bits(_T_1972, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_475 of rvclkhdr_569 @[lib.scala 352:23] rvclkhdr_475.clock <= clock rvclkhdr_475.reset <= reset @@ -35088,9 +35088,9 @@ circuit quasar_wrapper : rvclkhdr_475.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_209 : UInt, rvclkhdr_475.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_209 <= btb_wr_data @[lib.scala 358:16] - node _T_1974 = eq(btb_wr_addr, UInt<8>("h0d2")) @[ifu_bp_ctl.scala 415:95] - node _T_1975 = and(_T_1974, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1976 = bits(_T_1975, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1974 = eq(btb_wr_addr, UInt<8>("h0d2")) @[ifu_bp_ctl.scala 416:95] + node _T_1975 = and(_T_1974, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1976 = bits(_T_1975, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_476 of rvclkhdr_570 @[lib.scala 352:23] rvclkhdr_476.clock <= clock rvclkhdr_476.reset <= reset @@ -35099,9 +35099,9 @@ circuit quasar_wrapper : rvclkhdr_476.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_210 : UInt, rvclkhdr_476.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_210 <= btb_wr_data @[lib.scala 358:16] - node _T_1977 = eq(btb_wr_addr, UInt<8>("h0d3")) @[ifu_bp_ctl.scala 415:95] - node _T_1978 = and(_T_1977, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1979 = bits(_T_1978, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1977 = eq(btb_wr_addr, UInt<8>("h0d3")) @[ifu_bp_ctl.scala 416:95] + node _T_1978 = and(_T_1977, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1979 = bits(_T_1978, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_477 of rvclkhdr_571 @[lib.scala 352:23] rvclkhdr_477.clock <= clock rvclkhdr_477.reset <= reset @@ -35110,9 +35110,9 @@ circuit quasar_wrapper : rvclkhdr_477.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_211 : UInt, rvclkhdr_477.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_211 <= btb_wr_data @[lib.scala 358:16] - node _T_1980 = eq(btb_wr_addr, UInt<8>("h0d4")) @[ifu_bp_ctl.scala 415:95] - node _T_1981 = and(_T_1980, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1982 = bits(_T_1981, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1980 = eq(btb_wr_addr, UInt<8>("h0d4")) @[ifu_bp_ctl.scala 416:95] + node _T_1981 = and(_T_1980, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1982 = bits(_T_1981, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_478 of rvclkhdr_572 @[lib.scala 352:23] rvclkhdr_478.clock <= clock rvclkhdr_478.reset <= reset @@ -35121,9 +35121,9 @@ circuit quasar_wrapper : rvclkhdr_478.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_212 : UInt, rvclkhdr_478.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_212 <= btb_wr_data @[lib.scala 358:16] - node _T_1983 = eq(btb_wr_addr, UInt<8>("h0d5")) @[ifu_bp_ctl.scala 415:95] - node _T_1984 = and(_T_1983, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1985 = bits(_T_1984, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1983 = eq(btb_wr_addr, UInt<8>("h0d5")) @[ifu_bp_ctl.scala 416:95] + node _T_1984 = and(_T_1983, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1985 = bits(_T_1984, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_479 of rvclkhdr_573 @[lib.scala 352:23] rvclkhdr_479.clock <= clock rvclkhdr_479.reset <= reset @@ -35132,9 +35132,9 @@ circuit quasar_wrapper : rvclkhdr_479.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_213 : UInt, rvclkhdr_479.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_213 <= btb_wr_data @[lib.scala 358:16] - node _T_1986 = eq(btb_wr_addr, UInt<8>("h0d6")) @[ifu_bp_ctl.scala 415:95] - node _T_1987 = and(_T_1986, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1988 = bits(_T_1987, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1986 = eq(btb_wr_addr, UInt<8>("h0d6")) @[ifu_bp_ctl.scala 416:95] + node _T_1987 = and(_T_1986, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1988 = bits(_T_1987, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_480 of rvclkhdr_574 @[lib.scala 352:23] rvclkhdr_480.clock <= clock rvclkhdr_480.reset <= reset @@ -35143,9 +35143,9 @@ circuit quasar_wrapper : rvclkhdr_480.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_214 : UInt, rvclkhdr_480.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_214 <= btb_wr_data @[lib.scala 358:16] - node _T_1989 = eq(btb_wr_addr, UInt<8>("h0d7")) @[ifu_bp_ctl.scala 415:95] - node _T_1990 = and(_T_1989, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1991 = bits(_T_1990, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1989 = eq(btb_wr_addr, UInt<8>("h0d7")) @[ifu_bp_ctl.scala 416:95] + node _T_1990 = and(_T_1989, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1991 = bits(_T_1990, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_481 of rvclkhdr_575 @[lib.scala 352:23] rvclkhdr_481.clock <= clock rvclkhdr_481.reset <= reset @@ -35154,9 +35154,9 @@ circuit quasar_wrapper : rvclkhdr_481.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_215 : UInt, rvclkhdr_481.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_215 <= btb_wr_data @[lib.scala 358:16] - node _T_1992 = eq(btb_wr_addr, UInt<8>("h0d8")) @[ifu_bp_ctl.scala 415:95] - node _T_1993 = and(_T_1992, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1994 = bits(_T_1993, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1992 = eq(btb_wr_addr, UInt<8>("h0d8")) @[ifu_bp_ctl.scala 416:95] + node _T_1993 = and(_T_1992, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1994 = bits(_T_1993, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_482 of rvclkhdr_576 @[lib.scala 352:23] rvclkhdr_482.clock <= clock rvclkhdr_482.reset <= reset @@ -35165,9 +35165,9 @@ circuit quasar_wrapper : rvclkhdr_482.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_216 : UInt, rvclkhdr_482.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_216 <= btb_wr_data @[lib.scala 358:16] - node _T_1995 = eq(btb_wr_addr, UInt<8>("h0d9")) @[ifu_bp_ctl.scala 415:95] - node _T_1996 = and(_T_1995, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_1997 = bits(_T_1996, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1995 = eq(btb_wr_addr, UInt<8>("h0d9")) @[ifu_bp_ctl.scala 416:95] + node _T_1996 = and(_T_1995, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_1997 = bits(_T_1996, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_483 of rvclkhdr_577 @[lib.scala 352:23] rvclkhdr_483.clock <= clock rvclkhdr_483.reset <= reset @@ -35176,9 +35176,9 @@ circuit quasar_wrapper : rvclkhdr_483.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_217 : UInt, rvclkhdr_483.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_217 <= btb_wr_data @[lib.scala 358:16] - node _T_1998 = eq(btb_wr_addr, UInt<8>("h0da")) @[ifu_bp_ctl.scala 415:95] - node _T_1999 = and(_T_1998, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2000 = bits(_T_1999, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_1998 = eq(btb_wr_addr, UInt<8>("h0da")) @[ifu_bp_ctl.scala 416:95] + node _T_1999 = and(_T_1998, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2000 = bits(_T_1999, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_484 of rvclkhdr_578 @[lib.scala 352:23] rvclkhdr_484.clock <= clock rvclkhdr_484.reset <= reset @@ -35187,9 +35187,9 @@ circuit quasar_wrapper : rvclkhdr_484.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_218 : UInt, rvclkhdr_484.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_218 <= btb_wr_data @[lib.scala 358:16] - node _T_2001 = eq(btb_wr_addr, UInt<8>("h0db")) @[ifu_bp_ctl.scala 415:95] - node _T_2002 = and(_T_2001, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2003 = bits(_T_2002, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2001 = eq(btb_wr_addr, UInt<8>("h0db")) @[ifu_bp_ctl.scala 416:95] + node _T_2002 = and(_T_2001, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2003 = bits(_T_2002, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_485 of rvclkhdr_579 @[lib.scala 352:23] rvclkhdr_485.clock <= clock rvclkhdr_485.reset <= reset @@ -35198,9 +35198,9 @@ circuit quasar_wrapper : rvclkhdr_485.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_219 : UInt, rvclkhdr_485.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_219 <= btb_wr_data @[lib.scala 358:16] - node _T_2004 = eq(btb_wr_addr, UInt<8>("h0dc")) @[ifu_bp_ctl.scala 415:95] - node _T_2005 = and(_T_2004, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2006 = bits(_T_2005, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2004 = eq(btb_wr_addr, UInt<8>("h0dc")) @[ifu_bp_ctl.scala 416:95] + node _T_2005 = and(_T_2004, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2006 = bits(_T_2005, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_486 of rvclkhdr_580 @[lib.scala 352:23] rvclkhdr_486.clock <= clock rvclkhdr_486.reset <= reset @@ -35209,9 +35209,9 @@ circuit quasar_wrapper : rvclkhdr_486.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_220 : UInt, rvclkhdr_486.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_220 <= btb_wr_data @[lib.scala 358:16] - node _T_2007 = eq(btb_wr_addr, UInt<8>("h0dd")) @[ifu_bp_ctl.scala 415:95] - node _T_2008 = and(_T_2007, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2009 = bits(_T_2008, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2007 = eq(btb_wr_addr, UInt<8>("h0dd")) @[ifu_bp_ctl.scala 416:95] + node _T_2008 = and(_T_2007, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2009 = bits(_T_2008, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_487 of rvclkhdr_581 @[lib.scala 352:23] rvclkhdr_487.clock <= clock rvclkhdr_487.reset <= reset @@ -35220,9 +35220,9 @@ circuit quasar_wrapper : rvclkhdr_487.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_221 : UInt, rvclkhdr_487.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_221 <= btb_wr_data @[lib.scala 358:16] - node _T_2010 = eq(btb_wr_addr, UInt<8>("h0de")) @[ifu_bp_ctl.scala 415:95] - node _T_2011 = and(_T_2010, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2012 = bits(_T_2011, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2010 = eq(btb_wr_addr, UInt<8>("h0de")) @[ifu_bp_ctl.scala 416:95] + node _T_2011 = and(_T_2010, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2012 = bits(_T_2011, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_488 of rvclkhdr_582 @[lib.scala 352:23] rvclkhdr_488.clock <= clock rvclkhdr_488.reset <= reset @@ -35231,9 +35231,9 @@ circuit quasar_wrapper : rvclkhdr_488.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_222 : UInt, rvclkhdr_488.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_222 <= btb_wr_data @[lib.scala 358:16] - node _T_2013 = eq(btb_wr_addr, UInt<8>("h0df")) @[ifu_bp_ctl.scala 415:95] - node _T_2014 = and(_T_2013, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2015 = bits(_T_2014, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2013 = eq(btb_wr_addr, UInt<8>("h0df")) @[ifu_bp_ctl.scala 416:95] + node _T_2014 = and(_T_2013, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2015 = bits(_T_2014, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_489 of rvclkhdr_583 @[lib.scala 352:23] rvclkhdr_489.clock <= clock rvclkhdr_489.reset <= reset @@ -35242,9 +35242,9 @@ circuit quasar_wrapper : rvclkhdr_489.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_223 : UInt, rvclkhdr_489.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_223 <= btb_wr_data @[lib.scala 358:16] - node _T_2016 = eq(btb_wr_addr, UInt<8>("h0e0")) @[ifu_bp_ctl.scala 415:95] - node _T_2017 = and(_T_2016, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2018 = bits(_T_2017, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2016 = eq(btb_wr_addr, UInt<8>("h0e0")) @[ifu_bp_ctl.scala 416:95] + node _T_2017 = and(_T_2016, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2018 = bits(_T_2017, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_490 of rvclkhdr_584 @[lib.scala 352:23] rvclkhdr_490.clock <= clock rvclkhdr_490.reset <= reset @@ -35253,9 +35253,9 @@ circuit quasar_wrapper : rvclkhdr_490.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_224 : UInt, rvclkhdr_490.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_224 <= btb_wr_data @[lib.scala 358:16] - node _T_2019 = eq(btb_wr_addr, UInt<8>("h0e1")) @[ifu_bp_ctl.scala 415:95] - node _T_2020 = and(_T_2019, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2021 = bits(_T_2020, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2019 = eq(btb_wr_addr, UInt<8>("h0e1")) @[ifu_bp_ctl.scala 416:95] + node _T_2020 = and(_T_2019, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2021 = bits(_T_2020, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_491 of rvclkhdr_585 @[lib.scala 352:23] rvclkhdr_491.clock <= clock rvclkhdr_491.reset <= reset @@ -35264,9 +35264,9 @@ circuit quasar_wrapper : rvclkhdr_491.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_225 : UInt, rvclkhdr_491.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_225 <= btb_wr_data @[lib.scala 358:16] - node _T_2022 = eq(btb_wr_addr, UInt<8>("h0e2")) @[ifu_bp_ctl.scala 415:95] - node _T_2023 = and(_T_2022, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2024 = bits(_T_2023, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2022 = eq(btb_wr_addr, UInt<8>("h0e2")) @[ifu_bp_ctl.scala 416:95] + node _T_2023 = and(_T_2022, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2024 = bits(_T_2023, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_492 of rvclkhdr_586 @[lib.scala 352:23] rvclkhdr_492.clock <= clock rvclkhdr_492.reset <= reset @@ -35275,9 +35275,9 @@ circuit quasar_wrapper : rvclkhdr_492.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_226 : UInt, rvclkhdr_492.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_226 <= btb_wr_data @[lib.scala 358:16] - node _T_2025 = eq(btb_wr_addr, UInt<8>("h0e3")) @[ifu_bp_ctl.scala 415:95] - node _T_2026 = and(_T_2025, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2027 = bits(_T_2026, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2025 = eq(btb_wr_addr, UInt<8>("h0e3")) @[ifu_bp_ctl.scala 416:95] + node _T_2026 = and(_T_2025, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2027 = bits(_T_2026, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_493 of rvclkhdr_587 @[lib.scala 352:23] rvclkhdr_493.clock <= clock rvclkhdr_493.reset <= reset @@ -35286,9 +35286,9 @@ circuit quasar_wrapper : rvclkhdr_493.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_227 : UInt, rvclkhdr_493.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_227 <= btb_wr_data @[lib.scala 358:16] - node _T_2028 = eq(btb_wr_addr, UInt<8>("h0e4")) @[ifu_bp_ctl.scala 415:95] - node _T_2029 = and(_T_2028, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2030 = bits(_T_2029, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2028 = eq(btb_wr_addr, UInt<8>("h0e4")) @[ifu_bp_ctl.scala 416:95] + node _T_2029 = and(_T_2028, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2030 = bits(_T_2029, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_494 of rvclkhdr_588 @[lib.scala 352:23] rvclkhdr_494.clock <= clock rvclkhdr_494.reset <= reset @@ -35297,9 +35297,9 @@ circuit quasar_wrapper : rvclkhdr_494.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_228 : UInt, rvclkhdr_494.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_228 <= btb_wr_data @[lib.scala 358:16] - node _T_2031 = eq(btb_wr_addr, UInt<8>("h0e5")) @[ifu_bp_ctl.scala 415:95] - node _T_2032 = and(_T_2031, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2033 = bits(_T_2032, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2031 = eq(btb_wr_addr, UInt<8>("h0e5")) @[ifu_bp_ctl.scala 416:95] + node _T_2032 = and(_T_2031, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2033 = bits(_T_2032, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_495 of rvclkhdr_589 @[lib.scala 352:23] rvclkhdr_495.clock <= clock rvclkhdr_495.reset <= reset @@ -35308,9 +35308,9 @@ circuit quasar_wrapper : rvclkhdr_495.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_229 : UInt, rvclkhdr_495.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_229 <= btb_wr_data @[lib.scala 358:16] - node _T_2034 = eq(btb_wr_addr, UInt<8>("h0e6")) @[ifu_bp_ctl.scala 415:95] - node _T_2035 = and(_T_2034, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2036 = bits(_T_2035, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2034 = eq(btb_wr_addr, UInt<8>("h0e6")) @[ifu_bp_ctl.scala 416:95] + node _T_2035 = and(_T_2034, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2036 = bits(_T_2035, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_496 of rvclkhdr_590 @[lib.scala 352:23] rvclkhdr_496.clock <= clock rvclkhdr_496.reset <= reset @@ -35319,9 +35319,9 @@ circuit quasar_wrapper : rvclkhdr_496.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_230 : UInt, rvclkhdr_496.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_230 <= btb_wr_data @[lib.scala 358:16] - node _T_2037 = eq(btb_wr_addr, UInt<8>("h0e7")) @[ifu_bp_ctl.scala 415:95] - node _T_2038 = and(_T_2037, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2039 = bits(_T_2038, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2037 = eq(btb_wr_addr, UInt<8>("h0e7")) @[ifu_bp_ctl.scala 416:95] + node _T_2038 = and(_T_2037, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2039 = bits(_T_2038, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_497 of rvclkhdr_591 @[lib.scala 352:23] rvclkhdr_497.clock <= clock rvclkhdr_497.reset <= reset @@ -35330,9 +35330,9 @@ circuit quasar_wrapper : rvclkhdr_497.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_231 : UInt, rvclkhdr_497.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_231 <= btb_wr_data @[lib.scala 358:16] - node _T_2040 = eq(btb_wr_addr, UInt<8>("h0e8")) @[ifu_bp_ctl.scala 415:95] - node _T_2041 = and(_T_2040, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2042 = bits(_T_2041, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2040 = eq(btb_wr_addr, UInt<8>("h0e8")) @[ifu_bp_ctl.scala 416:95] + node _T_2041 = and(_T_2040, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2042 = bits(_T_2041, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_498 of rvclkhdr_592 @[lib.scala 352:23] rvclkhdr_498.clock <= clock rvclkhdr_498.reset <= reset @@ -35341,9 +35341,9 @@ circuit quasar_wrapper : rvclkhdr_498.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_232 : UInt, rvclkhdr_498.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_232 <= btb_wr_data @[lib.scala 358:16] - node _T_2043 = eq(btb_wr_addr, UInt<8>("h0e9")) @[ifu_bp_ctl.scala 415:95] - node _T_2044 = and(_T_2043, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2045 = bits(_T_2044, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2043 = eq(btb_wr_addr, UInt<8>("h0e9")) @[ifu_bp_ctl.scala 416:95] + node _T_2044 = and(_T_2043, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2045 = bits(_T_2044, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_499 of rvclkhdr_593 @[lib.scala 352:23] rvclkhdr_499.clock <= clock rvclkhdr_499.reset <= reset @@ -35352,9 +35352,9 @@ circuit quasar_wrapper : rvclkhdr_499.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_233 : UInt, rvclkhdr_499.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_233 <= btb_wr_data @[lib.scala 358:16] - node _T_2046 = eq(btb_wr_addr, UInt<8>("h0ea")) @[ifu_bp_ctl.scala 415:95] - node _T_2047 = and(_T_2046, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2048 = bits(_T_2047, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2046 = eq(btb_wr_addr, UInt<8>("h0ea")) @[ifu_bp_ctl.scala 416:95] + node _T_2047 = and(_T_2046, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2048 = bits(_T_2047, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_500 of rvclkhdr_594 @[lib.scala 352:23] rvclkhdr_500.clock <= clock rvclkhdr_500.reset <= reset @@ -35363,9 +35363,9 @@ circuit quasar_wrapper : rvclkhdr_500.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_234 : UInt, rvclkhdr_500.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_234 <= btb_wr_data @[lib.scala 358:16] - node _T_2049 = eq(btb_wr_addr, UInt<8>("h0eb")) @[ifu_bp_ctl.scala 415:95] - node _T_2050 = and(_T_2049, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2051 = bits(_T_2050, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2049 = eq(btb_wr_addr, UInt<8>("h0eb")) @[ifu_bp_ctl.scala 416:95] + node _T_2050 = and(_T_2049, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2051 = bits(_T_2050, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_501 of rvclkhdr_595 @[lib.scala 352:23] rvclkhdr_501.clock <= clock rvclkhdr_501.reset <= reset @@ -35374,9 +35374,9 @@ circuit quasar_wrapper : rvclkhdr_501.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_235 : UInt, rvclkhdr_501.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_235 <= btb_wr_data @[lib.scala 358:16] - node _T_2052 = eq(btb_wr_addr, UInt<8>("h0ec")) @[ifu_bp_ctl.scala 415:95] - node _T_2053 = and(_T_2052, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2054 = bits(_T_2053, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2052 = eq(btb_wr_addr, UInt<8>("h0ec")) @[ifu_bp_ctl.scala 416:95] + node _T_2053 = and(_T_2052, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2054 = bits(_T_2053, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_502 of rvclkhdr_596 @[lib.scala 352:23] rvclkhdr_502.clock <= clock rvclkhdr_502.reset <= reset @@ -35385,9 +35385,9 @@ circuit quasar_wrapper : rvclkhdr_502.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_236 : UInt, rvclkhdr_502.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_236 <= btb_wr_data @[lib.scala 358:16] - node _T_2055 = eq(btb_wr_addr, UInt<8>("h0ed")) @[ifu_bp_ctl.scala 415:95] - node _T_2056 = and(_T_2055, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2057 = bits(_T_2056, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2055 = eq(btb_wr_addr, UInt<8>("h0ed")) @[ifu_bp_ctl.scala 416:95] + node _T_2056 = and(_T_2055, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2057 = bits(_T_2056, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_503 of rvclkhdr_597 @[lib.scala 352:23] rvclkhdr_503.clock <= clock rvclkhdr_503.reset <= reset @@ -35396,9 +35396,9 @@ circuit quasar_wrapper : rvclkhdr_503.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_237 : UInt, rvclkhdr_503.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_237 <= btb_wr_data @[lib.scala 358:16] - node _T_2058 = eq(btb_wr_addr, UInt<8>("h0ee")) @[ifu_bp_ctl.scala 415:95] - node _T_2059 = and(_T_2058, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2060 = bits(_T_2059, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2058 = eq(btb_wr_addr, UInt<8>("h0ee")) @[ifu_bp_ctl.scala 416:95] + node _T_2059 = and(_T_2058, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2060 = bits(_T_2059, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_504 of rvclkhdr_598 @[lib.scala 352:23] rvclkhdr_504.clock <= clock rvclkhdr_504.reset <= reset @@ -35407,9 +35407,9 @@ circuit quasar_wrapper : rvclkhdr_504.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_238 : UInt, rvclkhdr_504.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_238 <= btb_wr_data @[lib.scala 358:16] - node _T_2061 = eq(btb_wr_addr, UInt<8>("h0ef")) @[ifu_bp_ctl.scala 415:95] - node _T_2062 = and(_T_2061, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2063 = bits(_T_2062, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2061 = eq(btb_wr_addr, UInt<8>("h0ef")) @[ifu_bp_ctl.scala 416:95] + node _T_2062 = and(_T_2061, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2063 = bits(_T_2062, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_505 of rvclkhdr_599 @[lib.scala 352:23] rvclkhdr_505.clock <= clock rvclkhdr_505.reset <= reset @@ -35418,9 +35418,9 @@ circuit quasar_wrapper : rvclkhdr_505.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_239 : UInt, rvclkhdr_505.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_239 <= btb_wr_data @[lib.scala 358:16] - node _T_2064 = eq(btb_wr_addr, UInt<8>("h0f0")) @[ifu_bp_ctl.scala 415:95] - node _T_2065 = and(_T_2064, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2066 = bits(_T_2065, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2064 = eq(btb_wr_addr, UInt<8>("h0f0")) @[ifu_bp_ctl.scala 416:95] + node _T_2065 = and(_T_2064, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2066 = bits(_T_2065, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_506 of rvclkhdr_600 @[lib.scala 352:23] rvclkhdr_506.clock <= clock rvclkhdr_506.reset <= reset @@ -35429,9 +35429,9 @@ circuit quasar_wrapper : rvclkhdr_506.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_240 : UInt, rvclkhdr_506.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_240 <= btb_wr_data @[lib.scala 358:16] - node _T_2067 = eq(btb_wr_addr, UInt<8>("h0f1")) @[ifu_bp_ctl.scala 415:95] - node _T_2068 = and(_T_2067, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2069 = bits(_T_2068, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2067 = eq(btb_wr_addr, UInt<8>("h0f1")) @[ifu_bp_ctl.scala 416:95] + node _T_2068 = and(_T_2067, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2069 = bits(_T_2068, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_507 of rvclkhdr_601 @[lib.scala 352:23] rvclkhdr_507.clock <= clock rvclkhdr_507.reset <= reset @@ -35440,9 +35440,9 @@ circuit quasar_wrapper : rvclkhdr_507.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_241 : UInt, rvclkhdr_507.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_241 <= btb_wr_data @[lib.scala 358:16] - node _T_2070 = eq(btb_wr_addr, UInt<8>("h0f2")) @[ifu_bp_ctl.scala 415:95] - node _T_2071 = and(_T_2070, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2072 = bits(_T_2071, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2070 = eq(btb_wr_addr, UInt<8>("h0f2")) @[ifu_bp_ctl.scala 416:95] + node _T_2071 = and(_T_2070, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2072 = bits(_T_2071, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_508 of rvclkhdr_602 @[lib.scala 352:23] rvclkhdr_508.clock <= clock rvclkhdr_508.reset <= reset @@ -35451,9 +35451,9 @@ circuit quasar_wrapper : rvclkhdr_508.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_242 : UInt, rvclkhdr_508.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_242 <= btb_wr_data @[lib.scala 358:16] - node _T_2073 = eq(btb_wr_addr, UInt<8>("h0f3")) @[ifu_bp_ctl.scala 415:95] - node _T_2074 = and(_T_2073, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2075 = bits(_T_2074, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2073 = eq(btb_wr_addr, UInt<8>("h0f3")) @[ifu_bp_ctl.scala 416:95] + node _T_2074 = and(_T_2073, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2075 = bits(_T_2074, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_509 of rvclkhdr_603 @[lib.scala 352:23] rvclkhdr_509.clock <= clock rvclkhdr_509.reset <= reset @@ -35462,9 +35462,9 @@ circuit quasar_wrapper : rvclkhdr_509.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_243 : UInt, rvclkhdr_509.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_243 <= btb_wr_data @[lib.scala 358:16] - node _T_2076 = eq(btb_wr_addr, UInt<8>("h0f4")) @[ifu_bp_ctl.scala 415:95] - node _T_2077 = and(_T_2076, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2078 = bits(_T_2077, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2076 = eq(btb_wr_addr, UInt<8>("h0f4")) @[ifu_bp_ctl.scala 416:95] + node _T_2077 = and(_T_2076, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2078 = bits(_T_2077, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_510 of rvclkhdr_604 @[lib.scala 352:23] rvclkhdr_510.clock <= clock rvclkhdr_510.reset <= reset @@ -35473,9 +35473,9 @@ circuit quasar_wrapper : rvclkhdr_510.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_244 : UInt, rvclkhdr_510.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_244 <= btb_wr_data @[lib.scala 358:16] - node _T_2079 = eq(btb_wr_addr, UInt<8>("h0f5")) @[ifu_bp_ctl.scala 415:95] - node _T_2080 = and(_T_2079, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2081 = bits(_T_2080, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2079 = eq(btb_wr_addr, UInt<8>("h0f5")) @[ifu_bp_ctl.scala 416:95] + node _T_2080 = and(_T_2079, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2081 = bits(_T_2080, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_511 of rvclkhdr_605 @[lib.scala 352:23] rvclkhdr_511.clock <= clock rvclkhdr_511.reset <= reset @@ -35484,9 +35484,9 @@ circuit quasar_wrapper : rvclkhdr_511.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_245 : UInt, rvclkhdr_511.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_245 <= btb_wr_data @[lib.scala 358:16] - node _T_2082 = eq(btb_wr_addr, UInt<8>("h0f6")) @[ifu_bp_ctl.scala 415:95] - node _T_2083 = and(_T_2082, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2084 = bits(_T_2083, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2082 = eq(btb_wr_addr, UInt<8>("h0f6")) @[ifu_bp_ctl.scala 416:95] + node _T_2083 = and(_T_2082, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2084 = bits(_T_2083, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_512 of rvclkhdr_606 @[lib.scala 352:23] rvclkhdr_512.clock <= clock rvclkhdr_512.reset <= reset @@ -35495,9 +35495,9 @@ circuit quasar_wrapper : rvclkhdr_512.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_246 : UInt, rvclkhdr_512.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_246 <= btb_wr_data @[lib.scala 358:16] - node _T_2085 = eq(btb_wr_addr, UInt<8>("h0f7")) @[ifu_bp_ctl.scala 415:95] - node _T_2086 = and(_T_2085, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2087 = bits(_T_2086, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2085 = eq(btb_wr_addr, UInt<8>("h0f7")) @[ifu_bp_ctl.scala 416:95] + node _T_2086 = and(_T_2085, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2087 = bits(_T_2086, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_513 of rvclkhdr_607 @[lib.scala 352:23] rvclkhdr_513.clock <= clock rvclkhdr_513.reset <= reset @@ -35506,9 +35506,9 @@ circuit quasar_wrapper : rvclkhdr_513.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_247 : UInt, rvclkhdr_513.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_247 <= btb_wr_data @[lib.scala 358:16] - node _T_2088 = eq(btb_wr_addr, UInt<8>("h0f8")) @[ifu_bp_ctl.scala 415:95] - node _T_2089 = and(_T_2088, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2090 = bits(_T_2089, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2088 = eq(btb_wr_addr, UInt<8>("h0f8")) @[ifu_bp_ctl.scala 416:95] + node _T_2089 = and(_T_2088, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2090 = bits(_T_2089, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_514 of rvclkhdr_608 @[lib.scala 352:23] rvclkhdr_514.clock <= clock rvclkhdr_514.reset <= reset @@ -35517,9 +35517,9 @@ circuit quasar_wrapper : rvclkhdr_514.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_248 : UInt, rvclkhdr_514.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_248 <= btb_wr_data @[lib.scala 358:16] - node _T_2091 = eq(btb_wr_addr, UInt<8>("h0f9")) @[ifu_bp_ctl.scala 415:95] - node _T_2092 = and(_T_2091, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2093 = bits(_T_2092, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2091 = eq(btb_wr_addr, UInt<8>("h0f9")) @[ifu_bp_ctl.scala 416:95] + node _T_2092 = and(_T_2091, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2093 = bits(_T_2092, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_515 of rvclkhdr_609 @[lib.scala 352:23] rvclkhdr_515.clock <= clock rvclkhdr_515.reset <= reset @@ -35528,9 +35528,9 @@ circuit quasar_wrapper : rvclkhdr_515.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_249 : UInt, rvclkhdr_515.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_249 <= btb_wr_data @[lib.scala 358:16] - node _T_2094 = eq(btb_wr_addr, UInt<8>("h0fa")) @[ifu_bp_ctl.scala 415:95] - node _T_2095 = and(_T_2094, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2096 = bits(_T_2095, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2094 = eq(btb_wr_addr, UInt<8>("h0fa")) @[ifu_bp_ctl.scala 416:95] + node _T_2095 = and(_T_2094, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2096 = bits(_T_2095, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_516 of rvclkhdr_610 @[lib.scala 352:23] rvclkhdr_516.clock <= clock rvclkhdr_516.reset <= reset @@ -35539,9 +35539,9 @@ circuit quasar_wrapper : rvclkhdr_516.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_250 : UInt, rvclkhdr_516.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_250 <= btb_wr_data @[lib.scala 358:16] - node _T_2097 = eq(btb_wr_addr, UInt<8>("h0fb")) @[ifu_bp_ctl.scala 415:95] - node _T_2098 = and(_T_2097, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2099 = bits(_T_2098, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2097 = eq(btb_wr_addr, UInt<8>("h0fb")) @[ifu_bp_ctl.scala 416:95] + node _T_2098 = and(_T_2097, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2099 = bits(_T_2098, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_517 of rvclkhdr_611 @[lib.scala 352:23] rvclkhdr_517.clock <= clock rvclkhdr_517.reset <= reset @@ -35550,9 +35550,9 @@ circuit quasar_wrapper : rvclkhdr_517.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_251 : UInt, rvclkhdr_517.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_251 <= btb_wr_data @[lib.scala 358:16] - node _T_2100 = eq(btb_wr_addr, UInt<8>("h0fc")) @[ifu_bp_ctl.scala 415:95] - node _T_2101 = and(_T_2100, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2102 = bits(_T_2101, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2100 = eq(btb_wr_addr, UInt<8>("h0fc")) @[ifu_bp_ctl.scala 416:95] + node _T_2101 = and(_T_2100, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2102 = bits(_T_2101, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_518 of rvclkhdr_612 @[lib.scala 352:23] rvclkhdr_518.clock <= clock rvclkhdr_518.reset <= reset @@ -35561,9 +35561,9 @@ circuit quasar_wrapper : rvclkhdr_518.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_252 : UInt, rvclkhdr_518.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_252 <= btb_wr_data @[lib.scala 358:16] - node _T_2103 = eq(btb_wr_addr, UInt<8>("h0fd")) @[ifu_bp_ctl.scala 415:95] - node _T_2104 = and(_T_2103, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2105 = bits(_T_2104, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2103 = eq(btb_wr_addr, UInt<8>("h0fd")) @[ifu_bp_ctl.scala 416:95] + node _T_2104 = and(_T_2103, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2105 = bits(_T_2104, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_519 of rvclkhdr_613 @[lib.scala 352:23] rvclkhdr_519.clock <= clock rvclkhdr_519.reset <= reset @@ -35572,9 +35572,9 @@ circuit quasar_wrapper : rvclkhdr_519.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_253 : UInt, rvclkhdr_519.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_253 <= btb_wr_data @[lib.scala 358:16] - node _T_2106 = eq(btb_wr_addr, UInt<8>("h0fe")) @[ifu_bp_ctl.scala 415:95] - node _T_2107 = and(_T_2106, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2108 = bits(_T_2107, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2106 = eq(btb_wr_addr, UInt<8>("h0fe")) @[ifu_bp_ctl.scala 416:95] + node _T_2107 = and(_T_2106, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2108 = bits(_T_2107, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_520 of rvclkhdr_614 @[lib.scala 352:23] rvclkhdr_520.clock <= clock rvclkhdr_520.reset <= reset @@ -35583,9 +35583,9 @@ circuit quasar_wrapper : rvclkhdr_520.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_254 : UInt, rvclkhdr_520.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_254 <= btb_wr_data @[lib.scala 358:16] - node _T_2109 = eq(btb_wr_addr, UInt<8>("h0ff")) @[ifu_bp_ctl.scala 415:95] - node _T_2110 = and(_T_2109, btb_wr_en_way1) @[ifu_bp_ctl.scala 415:103] - node _T_2111 = bits(_T_2110, 0, 0) @[ifu_bp_ctl.scala 415:121] + node _T_2109 = eq(btb_wr_addr, UInt<8>("h0ff")) @[ifu_bp_ctl.scala 416:95] + node _T_2110 = and(_T_2109, btb_wr_en_way1) @[ifu_bp_ctl.scala 416:103] + node _T_2111 = bits(_T_2110, 0, 0) @[ifu_bp_ctl.scala 416:121] inst rvclkhdr_521 of rvclkhdr_615 @[lib.scala 352:23] rvclkhdr_521.clock <= clock rvclkhdr_521.reset <= reset @@ -35594,518 +35594,518 @@ circuit quasar_wrapper : rvclkhdr_521.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg btb_bank0_rd_data_way1_out_255 : UInt, rvclkhdr_521.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] btb_bank0_rd_data_way1_out_255 <= btb_wr_data @[lib.scala 358:16] - node _T_2112 = eq(btb_rd_addr_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 417:77] - node _T_2113 = bits(_T_2112, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2114 = eq(btb_rd_addr_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 417:77] - node _T_2115 = bits(_T_2114, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2116 = eq(btb_rd_addr_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 417:77] - node _T_2117 = bits(_T_2116, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2118 = eq(btb_rd_addr_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 417:77] - node _T_2119 = bits(_T_2118, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2120 = eq(btb_rd_addr_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 417:77] - node _T_2121 = bits(_T_2120, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2122 = eq(btb_rd_addr_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 417:77] - node _T_2123 = bits(_T_2122, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2124 = eq(btb_rd_addr_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 417:77] - node _T_2125 = bits(_T_2124, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2126 = eq(btb_rd_addr_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 417:77] - node _T_2127 = bits(_T_2126, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2128 = eq(btb_rd_addr_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 417:77] - node _T_2129 = bits(_T_2128, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2130 = eq(btb_rd_addr_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 417:77] - node _T_2131 = bits(_T_2130, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2132 = eq(btb_rd_addr_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 417:77] - node _T_2133 = bits(_T_2132, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2134 = eq(btb_rd_addr_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 417:77] - node _T_2135 = bits(_T_2134, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2136 = eq(btb_rd_addr_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 417:77] - node _T_2137 = bits(_T_2136, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2138 = eq(btb_rd_addr_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 417:77] - node _T_2139 = bits(_T_2138, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2140 = eq(btb_rd_addr_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 417:77] - node _T_2141 = bits(_T_2140, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2142 = eq(btb_rd_addr_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 417:77] - node _T_2143 = bits(_T_2142, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2144 = eq(btb_rd_addr_f, UInt<5>("h010")) @[ifu_bp_ctl.scala 417:77] - node _T_2145 = bits(_T_2144, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2146 = eq(btb_rd_addr_f, UInt<5>("h011")) @[ifu_bp_ctl.scala 417:77] - node _T_2147 = bits(_T_2146, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2148 = eq(btb_rd_addr_f, UInt<5>("h012")) @[ifu_bp_ctl.scala 417:77] - node _T_2149 = bits(_T_2148, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2150 = eq(btb_rd_addr_f, UInt<5>("h013")) @[ifu_bp_ctl.scala 417:77] - node _T_2151 = bits(_T_2150, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2152 = eq(btb_rd_addr_f, UInt<5>("h014")) @[ifu_bp_ctl.scala 417:77] - node _T_2153 = bits(_T_2152, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2154 = eq(btb_rd_addr_f, UInt<5>("h015")) @[ifu_bp_ctl.scala 417:77] - node _T_2155 = bits(_T_2154, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2156 = eq(btb_rd_addr_f, UInt<5>("h016")) @[ifu_bp_ctl.scala 417:77] - node _T_2157 = bits(_T_2156, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2158 = eq(btb_rd_addr_f, UInt<5>("h017")) @[ifu_bp_ctl.scala 417:77] - node _T_2159 = bits(_T_2158, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2160 = eq(btb_rd_addr_f, UInt<5>("h018")) @[ifu_bp_ctl.scala 417:77] - node _T_2161 = bits(_T_2160, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2162 = eq(btb_rd_addr_f, UInt<5>("h019")) @[ifu_bp_ctl.scala 417:77] - node _T_2163 = bits(_T_2162, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2164 = eq(btb_rd_addr_f, UInt<5>("h01a")) @[ifu_bp_ctl.scala 417:77] - node _T_2165 = bits(_T_2164, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2166 = eq(btb_rd_addr_f, UInt<5>("h01b")) @[ifu_bp_ctl.scala 417:77] - node _T_2167 = bits(_T_2166, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2168 = eq(btb_rd_addr_f, UInt<5>("h01c")) @[ifu_bp_ctl.scala 417:77] - node _T_2169 = bits(_T_2168, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2170 = eq(btb_rd_addr_f, UInt<5>("h01d")) @[ifu_bp_ctl.scala 417:77] - node _T_2171 = bits(_T_2170, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2172 = eq(btb_rd_addr_f, UInt<5>("h01e")) @[ifu_bp_ctl.scala 417:77] - node _T_2173 = bits(_T_2172, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2174 = eq(btb_rd_addr_f, UInt<5>("h01f")) @[ifu_bp_ctl.scala 417:77] - node _T_2175 = bits(_T_2174, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2176 = eq(btb_rd_addr_f, UInt<6>("h020")) @[ifu_bp_ctl.scala 417:77] - node _T_2177 = bits(_T_2176, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2178 = eq(btb_rd_addr_f, UInt<6>("h021")) @[ifu_bp_ctl.scala 417:77] - node _T_2179 = bits(_T_2178, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2180 = eq(btb_rd_addr_f, UInt<6>("h022")) @[ifu_bp_ctl.scala 417:77] - node _T_2181 = bits(_T_2180, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2182 = eq(btb_rd_addr_f, UInt<6>("h023")) @[ifu_bp_ctl.scala 417:77] - node _T_2183 = bits(_T_2182, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2184 = eq(btb_rd_addr_f, UInt<6>("h024")) @[ifu_bp_ctl.scala 417:77] - node _T_2185 = bits(_T_2184, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2186 = eq(btb_rd_addr_f, UInt<6>("h025")) @[ifu_bp_ctl.scala 417:77] - node _T_2187 = bits(_T_2186, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2188 = eq(btb_rd_addr_f, UInt<6>("h026")) @[ifu_bp_ctl.scala 417:77] - node _T_2189 = bits(_T_2188, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2190 = eq(btb_rd_addr_f, UInt<6>("h027")) @[ifu_bp_ctl.scala 417:77] - node _T_2191 = bits(_T_2190, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2192 = eq(btb_rd_addr_f, UInt<6>("h028")) @[ifu_bp_ctl.scala 417:77] - node _T_2193 = bits(_T_2192, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2194 = eq(btb_rd_addr_f, UInt<6>("h029")) @[ifu_bp_ctl.scala 417:77] - node _T_2195 = bits(_T_2194, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2196 = eq(btb_rd_addr_f, UInt<6>("h02a")) @[ifu_bp_ctl.scala 417:77] - node _T_2197 = bits(_T_2196, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2198 = eq(btb_rd_addr_f, UInt<6>("h02b")) @[ifu_bp_ctl.scala 417:77] - node _T_2199 = bits(_T_2198, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2200 = eq(btb_rd_addr_f, UInt<6>("h02c")) @[ifu_bp_ctl.scala 417:77] - node _T_2201 = bits(_T_2200, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2202 = eq(btb_rd_addr_f, UInt<6>("h02d")) @[ifu_bp_ctl.scala 417:77] - node _T_2203 = bits(_T_2202, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2204 = eq(btb_rd_addr_f, UInt<6>("h02e")) @[ifu_bp_ctl.scala 417:77] - node _T_2205 = bits(_T_2204, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2206 = eq(btb_rd_addr_f, UInt<6>("h02f")) @[ifu_bp_ctl.scala 417:77] - node _T_2207 = bits(_T_2206, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2208 = eq(btb_rd_addr_f, UInt<6>("h030")) @[ifu_bp_ctl.scala 417:77] - node _T_2209 = bits(_T_2208, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2210 = eq(btb_rd_addr_f, UInt<6>("h031")) @[ifu_bp_ctl.scala 417:77] - node _T_2211 = bits(_T_2210, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2212 = eq(btb_rd_addr_f, UInt<6>("h032")) @[ifu_bp_ctl.scala 417:77] - node _T_2213 = bits(_T_2212, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2214 = eq(btb_rd_addr_f, UInt<6>("h033")) @[ifu_bp_ctl.scala 417:77] - node _T_2215 = bits(_T_2214, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2216 = eq(btb_rd_addr_f, UInt<6>("h034")) @[ifu_bp_ctl.scala 417:77] - node _T_2217 = bits(_T_2216, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2218 = eq(btb_rd_addr_f, UInt<6>("h035")) @[ifu_bp_ctl.scala 417:77] - node _T_2219 = bits(_T_2218, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2220 = eq(btb_rd_addr_f, UInt<6>("h036")) @[ifu_bp_ctl.scala 417:77] - node _T_2221 = bits(_T_2220, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2222 = eq(btb_rd_addr_f, UInt<6>("h037")) @[ifu_bp_ctl.scala 417:77] - node _T_2223 = bits(_T_2222, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2224 = eq(btb_rd_addr_f, UInt<6>("h038")) @[ifu_bp_ctl.scala 417:77] - node _T_2225 = bits(_T_2224, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2226 = eq(btb_rd_addr_f, UInt<6>("h039")) @[ifu_bp_ctl.scala 417:77] - node _T_2227 = bits(_T_2226, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2228 = eq(btb_rd_addr_f, UInt<6>("h03a")) @[ifu_bp_ctl.scala 417:77] - node _T_2229 = bits(_T_2228, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2230 = eq(btb_rd_addr_f, UInt<6>("h03b")) @[ifu_bp_ctl.scala 417:77] - node _T_2231 = bits(_T_2230, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2232 = eq(btb_rd_addr_f, UInt<6>("h03c")) @[ifu_bp_ctl.scala 417:77] - node _T_2233 = bits(_T_2232, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2234 = eq(btb_rd_addr_f, UInt<6>("h03d")) @[ifu_bp_ctl.scala 417:77] - node _T_2235 = bits(_T_2234, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2236 = eq(btb_rd_addr_f, UInt<6>("h03e")) @[ifu_bp_ctl.scala 417:77] - node _T_2237 = bits(_T_2236, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2238 = eq(btb_rd_addr_f, UInt<6>("h03f")) @[ifu_bp_ctl.scala 417:77] - node _T_2239 = bits(_T_2238, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2240 = eq(btb_rd_addr_f, UInt<7>("h040")) @[ifu_bp_ctl.scala 417:77] - node _T_2241 = bits(_T_2240, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2242 = eq(btb_rd_addr_f, UInt<7>("h041")) @[ifu_bp_ctl.scala 417:77] - node _T_2243 = bits(_T_2242, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2244 = eq(btb_rd_addr_f, UInt<7>("h042")) @[ifu_bp_ctl.scala 417:77] - node _T_2245 = bits(_T_2244, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2246 = eq(btb_rd_addr_f, UInt<7>("h043")) @[ifu_bp_ctl.scala 417:77] - node _T_2247 = bits(_T_2246, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2248 = eq(btb_rd_addr_f, UInt<7>("h044")) @[ifu_bp_ctl.scala 417:77] - node _T_2249 = bits(_T_2248, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2250 = eq(btb_rd_addr_f, UInt<7>("h045")) @[ifu_bp_ctl.scala 417:77] - node _T_2251 = bits(_T_2250, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2252 = eq(btb_rd_addr_f, UInt<7>("h046")) @[ifu_bp_ctl.scala 417:77] - node _T_2253 = bits(_T_2252, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2254 = eq(btb_rd_addr_f, UInt<7>("h047")) @[ifu_bp_ctl.scala 417:77] - node _T_2255 = bits(_T_2254, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2256 = eq(btb_rd_addr_f, UInt<7>("h048")) @[ifu_bp_ctl.scala 417:77] - node _T_2257 = bits(_T_2256, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2258 = eq(btb_rd_addr_f, UInt<7>("h049")) @[ifu_bp_ctl.scala 417:77] - node _T_2259 = bits(_T_2258, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2260 = eq(btb_rd_addr_f, UInt<7>("h04a")) @[ifu_bp_ctl.scala 417:77] - node _T_2261 = bits(_T_2260, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2262 = eq(btb_rd_addr_f, UInt<7>("h04b")) @[ifu_bp_ctl.scala 417:77] - node _T_2263 = bits(_T_2262, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2264 = eq(btb_rd_addr_f, UInt<7>("h04c")) @[ifu_bp_ctl.scala 417:77] - node _T_2265 = bits(_T_2264, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2266 = eq(btb_rd_addr_f, UInt<7>("h04d")) @[ifu_bp_ctl.scala 417:77] - node _T_2267 = bits(_T_2266, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2268 = eq(btb_rd_addr_f, UInt<7>("h04e")) @[ifu_bp_ctl.scala 417:77] - node _T_2269 = bits(_T_2268, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2270 = eq(btb_rd_addr_f, UInt<7>("h04f")) @[ifu_bp_ctl.scala 417:77] - node _T_2271 = bits(_T_2270, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2272 = eq(btb_rd_addr_f, UInt<7>("h050")) @[ifu_bp_ctl.scala 417:77] - node _T_2273 = bits(_T_2272, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2274 = eq(btb_rd_addr_f, UInt<7>("h051")) @[ifu_bp_ctl.scala 417:77] - node _T_2275 = bits(_T_2274, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2276 = eq(btb_rd_addr_f, UInt<7>("h052")) @[ifu_bp_ctl.scala 417:77] - node _T_2277 = bits(_T_2276, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2278 = eq(btb_rd_addr_f, UInt<7>("h053")) @[ifu_bp_ctl.scala 417:77] - node _T_2279 = bits(_T_2278, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2280 = eq(btb_rd_addr_f, UInt<7>("h054")) @[ifu_bp_ctl.scala 417:77] - node _T_2281 = bits(_T_2280, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2282 = eq(btb_rd_addr_f, UInt<7>("h055")) @[ifu_bp_ctl.scala 417:77] - node _T_2283 = bits(_T_2282, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2284 = eq(btb_rd_addr_f, UInt<7>("h056")) @[ifu_bp_ctl.scala 417:77] - node _T_2285 = bits(_T_2284, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2286 = eq(btb_rd_addr_f, UInt<7>("h057")) @[ifu_bp_ctl.scala 417:77] - node _T_2287 = bits(_T_2286, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2288 = eq(btb_rd_addr_f, UInt<7>("h058")) @[ifu_bp_ctl.scala 417:77] - node _T_2289 = bits(_T_2288, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2290 = eq(btb_rd_addr_f, UInt<7>("h059")) @[ifu_bp_ctl.scala 417:77] - node _T_2291 = bits(_T_2290, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2292 = eq(btb_rd_addr_f, UInt<7>("h05a")) @[ifu_bp_ctl.scala 417:77] - node _T_2293 = bits(_T_2292, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2294 = eq(btb_rd_addr_f, UInt<7>("h05b")) @[ifu_bp_ctl.scala 417:77] - node _T_2295 = bits(_T_2294, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2296 = eq(btb_rd_addr_f, UInt<7>("h05c")) @[ifu_bp_ctl.scala 417:77] - node _T_2297 = bits(_T_2296, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2298 = eq(btb_rd_addr_f, UInt<7>("h05d")) @[ifu_bp_ctl.scala 417:77] - node _T_2299 = bits(_T_2298, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2300 = eq(btb_rd_addr_f, UInt<7>("h05e")) @[ifu_bp_ctl.scala 417:77] - node _T_2301 = bits(_T_2300, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2302 = eq(btb_rd_addr_f, UInt<7>("h05f")) @[ifu_bp_ctl.scala 417:77] - node _T_2303 = bits(_T_2302, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2304 = eq(btb_rd_addr_f, UInt<7>("h060")) @[ifu_bp_ctl.scala 417:77] - node _T_2305 = bits(_T_2304, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2306 = eq(btb_rd_addr_f, UInt<7>("h061")) @[ifu_bp_ctl.scala 417:77] - node _T_2307 = bits(_T_2306, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2308 = eq(btb_rd_addr_f, UInt<7>("h062")) @[ifu_bp_ctl.scala 417:77] - node _T_2309 = bits(_T_2308, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2310 = eq(btb_rd_addr_f, UInt<7>("h063")) @[ifu_bp_ctl.scala 417:77] - node _T_2311 = bits(_T_2310, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2312 = eq(btb_rd_addr_f, UInt<7>("h064")) @[ifu_bp_ctl.scala 417:77] - node _T_2313 = bits(_T_2312, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2314 = eq(btb_rd_addr_f, UInt<7>("h065")) @[ifu_bp_ctl.scala 417:77] - node _T_2315 = bits(_T_2314, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2316 = eq(btb_rd_addr_f, UInt<7>("h066")) @[ifu_bp_ctl.scala 417:77] - node _T_2317 = bits(_T_2316, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2318 = eq(btb_rd_addr_f, UInt<7>("h067")) @[ifu_bp_ctl.scala 417:77] - node _T_2319 = bits(_T_2318, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2320 = eq(btb_rd_addr_f, UInt<7>("h068")) @[ifu_bp_ctl.scala 417:77] - node _T_2321 = bits(_T_2320, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2322 = eq(btb_rd_addr_f, UInt<7>("h069")) @[ifu_bp_ctl.scala 417:77] - node _T_2323 = bits(_T_2322, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2324 = eq(btb_rd_addr_f, UInt<7>("h06a")) @[ifu_bp_ctl.scala 417:77] - node _T_2325 = bits(_T_2324, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2326 = eq(btb_rd_addr_f, UInt<7>("h06b")) @[ifu_bp_ctl.scala 417:77] - node _T_2327 = bits(_T_2326, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2328 = eq(btb_rd_addr_f, UInt<7>("h06c")) @[ifu_bp_ctl.scala 417:77] - node _T_2329 = bits(_T_2328, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2330 = eq(btb_rd_addr_f, UInt<7>("h06d")) @[ifu_bp_ctl.scala 417:77] - node _T_2331 = bits(_T_2330, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2332 = eq(btb_rd_addr_f, UInt<7>("h06e")) @[ifu_bp_ctl.scala 417:77] - node _T_2333 = bits(_T_2332, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2334 = eq(btb_rd_addr_f, UInt<7>("h06f")) @[ifu_bp_ctl.scala 417:77] - node _T_2335 = bits(_T_2334, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2336 = eq(btb_rd_addr_f, UInt<7>("h070")) @[ifu_bp_ctl.scala 417:77] - node _T_2337 = bits(_T_2336, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2338 = eq(btb_rd_addr_f, UInt<7>("h071")) @[ifu_bp_ctl.scala 417:77] - node _T_2339 = bits(_T_2338, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2340 = eq(btb_rd_addr_f, UInt<7>("h072")) @[ifu_bp_ctl.scala 417:77] - node _T_2341 = bits(_T_2340, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2342 = eq(btb_rd_addr_f, UInt<7>("h073")) @[ifu_bp_ctl.scala 417:77] - node _T_2343 = bits(_T_2342, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2344 = eq(btb_rd_addr_f, UInt<7>("h074")) @[ifu_bp_ctl.scala 417:77] - node _T_2345 = bits(_T_2344, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2346 = eq(btb_rd_addr_f, UInt<7>("h075")) @[ifu_bp_ctl.scala 417:77] - node _T_2347 = bits(_T_2346, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2348 = eq(btb_rd_addr_f, UInt<7>("h076")) @[ifu_bp_ctl.scala 417:77] - node _T_2349 = bits(_T_2348, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2350 = eq(btb_rd_addr_f, UInt<7>("h077")) @[ifu_bp_ctl.scala 417:77] - node _T_2351 = bits(_T_2350, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2352 = eq(btb_rd_addr_f, UInt<7>("h078")) @[ifu_bp_ctl.scala 417:77] - node _T_2353 = bits(_T_2352, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2354 = eq(btb_rd_addr_f, UInt<7>("h079")) @[ifu_bp_ctl.scala 417:77] - node _T_2355 = bits(_T_2354, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2356 = eq(btb_rd_addr_f, UInt<7>("h07a")) @[ifu_bp_ctl.scala 417:77] - node _T_2357 = bits(_T_2356, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2358 = eq(btb_rd_addr_f, UInt<7>("h07b")) @[ifu_bp_ctl.scala 417:77] - node _T_2359 = bits(_T_2358, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2360 = eq(btb_rd_addr_f, UInt<7>("h07c")) @[ifu_bp_ctl.scala 417:77] - node _T_2361 = bits(_T_2360, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2362 = eq(btb_rd_addr_f, UInt<7>("h07d")) @[ifu_bp_ctl.scala 417:77] - node _T_2363 = bits(_T_2362, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2364 = eq(btb_rd_addr_f, UInt<7>("h07e")) @[ifu_bp_ctl.scala 417:77] - node _T_2365 = bits(_T_2364, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2366 = eq(btb_rd_addr_f, UInt<7>("h07f")) @[ifu_bp_ctl.scala 417:77] - node _T_2367 = bits(_T_2366, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2368 = eq(btb_rd_addr_f, UInt<8>("h080")) @[ifu_bp_ctl.scala 417:77] - node _T_2369 = bits(_T_2368, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2370 = eq(btb_rd_addr_f, UInt<8>("h081")) @[ifu_bp_ctl.scala 417:77] - node _T_2371 = bits(_T_2370, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2372 = eq(btb_rd_addr_f, UInt<8>("h082")) @[ifu_bp_ctl.scala 417:77] - node _T_2373 = bits(_T_2372, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2374 = eq(btb_rd_addr_f, UInt<8>("h083")) @[ifu_bp_ctl.scala 417:77] - node _T_2375 = bits(_T_2374, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2376 = eq(btb_rd_addr_f, UInt<8>("h084")) @[ifu_bp_ctl.scala 417:77] - node _T_2377 = bits(_T_2376, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2378 = eq(btb_rd_addr_f, UInt<8>("h085")) @[ifu_bp_ctl.scala 417:77] - node _T_2379 = bits(_T_2378, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2380 = eq(btb_rd_addr_f, UInt<8>("h086")) @[ifu_bp_ctl.scala 417:77] - node _T_2381 = bits(_T_2380, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2382 = eq(btb_rd_addr_f, UInt<8>("h087")) @[ifu_bp_ctl.scala 417:77] - node _T_2383 = bits(_T_2382, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2384 = eq(btb_rd_addr_f, UInt<8>("h088")) @[ifu_bp_ctl.scala 417:77] - node _T_2385 = bits(_T_2384, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2386 = eq(btb_rd_addr_f, UInt<8>("h089")) @[ifu_bp_ctl.scala 417:77] - node _T_2387 = bits(_T_2386, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2388 = eq(btb_rd_addr_f, UInt<8>("h08a")) @[ifu_bp_ctl.scala 417:77] - node _T_2389 = bits(_T_2388, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2390 = eq(btb_rd_addr_f, UInt<8>("h08b")) @[ifu_bp_ctl.scala 417:77] - node _T_2391 = bits(_T_2390, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2392 = eq(btb_rd_addr_f, UInt<8>("h08c")) @[ifu_bp_ctl.scala 417:77] - node _T_2393 = bits(_T_2392, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2394 = eq(btb_rd_addr_f, UInt<8>("h08d")) @[ifu_bp_ctl.scala 417:77] - node _T_2395 = bits(_T_2394, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2396 = eq(btb_rd_addr_f, UInt<8>("h08e")) @[ifu_bp_ctl.scala 417:77] - node _T_2397 = bits(_T_2396, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2398 = eq(btb_rd_addr_f, UInt<8>("h08f")) @[ifu_bp_ctl.scala 417:77] - node _T_2399 = bits(_T_2398, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2400 = eq(btb_rd_addr_f, UInt<8>("h090")) @[ifu_bp_ctl.scala 417:77] - node _T_2401 = bits(_T_2400, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2402 = eq(btb_rd_addr_f, UInt<8>("h091")) @[ifu_bp_ctl.scala 417:77] - node _T_2403 = bits(_T_2402, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2404 = eq(btb_rd_addr_f, UInt<8>("h092")) @[ifu_bp_ctl.scala 417:77] - node _T_2405 = bits(_T_2404, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2406 = eq(btb_rd_addr_f, UInt<8>("h093")) @[ifu_bp_ctl.scala 417:77] - node _T_2407 = bits(_T_2406, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2408 = eq(btb_rd_addr_f, UInt<8>("h094")) @[ifu_bp_ctl.scala 417:77] - node _T_2409 = bits(_T_2408, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2410 = eq(btb_rd_addr_f, UInt<8>("h095")) @[ifu_bp_ctl.scala 417:77] - node _T_2411 = bits(_T_2410, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2412 = eq(btb_rd_addr_f, UInt<8>("h096")) @[ifu_bp_ctl.scala 417:77] - node _T_2413 = bits(_T_2412, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2414 = eq(btb_rd_addr_f, UInt<8>("h097")) @[ifu_bp_ctl.scala 417:77] - node _T_2415 = bits(_T_2414, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2416 = eq(btb_rd_addr_f, UInt<8>("h098")) @[ifu_bp_ctl.scala 417:77] - node _T_2417 = bits(_T_2416, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2418 = eq(btb_rd_addr_f, UInt<8>("h099")) @[ifu_bp_ctl.scala 417:77] - node _T_2419 = bits(_T_2418, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2420 = eq(btb_rd_addr_f, UInt<8>("h09a")) @[ifu_bp_ctl.scala 417:77] - node _T_2421 = bits(_T_2420, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2422 = eq(btb_rd_addr_f, UInt<8>("h09b")) @[ifu_bp_ctl.scala 417:77] - node _T_2423 = bits(_T_2422, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2424 = eq(btb_rd_addr_f, UInt<8>("h09c")) @[ifu_bp_ctl.scala 417:77] - node _T_2425 = bits(_T_2424, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2426 = eq(btb_rd_addr_f, UInt<8>("h09d")) @[ifu_bp_ctl.scala 417:77] - node _T_2427 = bits(_T_2426, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2428 = eq(btb_rd_addr_f, UInt<8>("h09e")) @[ifu_bp_ctl.scala 417:77] - node _T_2429 = bits(_T_2428, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2430 = eq(btb_rd_addr_f, UInt<8>("h09f")) @[ifu_bp_ctl.scala 417:77] - node _T_2431 = bits(_T_2430, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2432 = eq(btb_rd_addr_f, UInt<8>("h0a0")) @[ifu_bp_ctl.scala 417:77] - node _T_2433 = bits(_T_2432, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2434 = eq(btb_rd_addr_f, UInt<8>("h0a1")) @[ifu_bp_ctl.scala 417:77] - node _T_2435 = bits(_T_2434, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2436 = eq(btb_rd_addr_f, UInt<8>("h0a2")) @[ifu_bp_ctl.scala 417:77] - node _T_2437 = bits(_T_2436, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2438 = eq(btb_rd_addr_f, UInt<8>("h0a3")) @[ifu_bp_ctl.scala 417:77] - node _T_2439 = bits(_T_2438, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2440 = eq(btb_rd_addr_f, UInt<8>("h0a4")) @[ifu_bp_ctl.scala 417:77] - node _T_2441 = bits(_T_2440, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2442 = eq(btb_rd_addr_f, UInt<8>("h0a5")) @[ifu_bp_ctl.scala 417:77] - node _T_2443 = bits(_T_2442, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2444 = eq(btb_rd_addr_f, UInt<8>("h0a6")) @[ifu_bp_ctl.scala 417:77] - node _T_2445 = bits(_T_2444, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2446 = eq(btb_rd_addr_f, UInt<8>("h0a7")) @[ifu_bp_ctl.scala 417:77] - node _T_2447 = bits(_T_2446, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2448 = eq(btb_rd_addr_f, UInt<8>("h0a8")) @[ifu_bp_ctl.scala 417:77] - node _T_2449 = bits(_T_2448, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2450 = eq(btb_rd_addr_f, UInt<8>("h0a9")) @[ifu_bp_ctl.scala 417:77] - node _T_2451 = bits(_T_2450, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2452 = eq(btb_rd_addr_f, UInt<8>("h0aa")) @[ifu_bp_ctl.scala 417:77] - node _T_2453 = bits(_T_2452, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2454 = eq(btb_rd_addr_f, UInt<8>("h0ab")) @[ifu_bp_ctl.scala 417:77] - node _T_2455 = bits(_T_2454, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2456 = eq(btb_rd_addr_f, UInt<8>("h0ac")) @[ifu_bp_ctl.scala 417:77] - node _T_2457 = bits(_T_2456, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2458 = eq(btb_rd_addr_f, UInt<8>("h0ad")) @[ifu_bp_ctl.scala 417:77] - node _T_2459 = bits(_T_2458, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2460 = eq(btb_rd_addr_f, UInt<8>("h0ae")) @[ifu_bp_ctl.scala 417:77] - node _T_2461 = bits(_T_2460, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2462 = eq(btb_rd_addr_f, UInt<8>("h0af")) @[ifu_bp_ctl.scala 417:77] - node _T_2463 = bits(_T_2462, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2464 = eq(btb_rd_addr_f, UInt<8>("h0b0")) @[ifu_bp_ctl.scala 417:77] - node _T_2465 = bits(_T_2464, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2466 = eq(btb_rd_addr_f, UInt<8>("h0b1")) @[ifu_bp_ctl.scala 417:77] - node _T_2467 = bits(_T_2466, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2468 = eq(btb_rd_addr_f, UInt<8>("h0b2")) @[ifu_bp_ctl.scala 417:77] - node _T_2469 = bits(_T_2468, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2470 = eq(btb_rd_addr_f, UInt<8>("h0b3")) @[ifu_bp_ctl.scala 417:77] - node _T_2471 = bits(_T_2470, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2472 = eq(btb_rd_addr_f, UInt<8>("h0b4")) @[ifu_bp_ctl.scala 417:77] - node _T_2473 = bits(_T_2472, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2474 = eq(btb_rd_addr_f, UInt<8>("h0b5")) @[ifu_bp_ctl.scala 417:77] - node _T_2475 = bits(_T_2474, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2476 = eq(btb_rd_addr_f, UInt<8>("h0b6")) @[ifu_bp_ctl.scala 417:77] - node _T_2477 = bits(_T_2476, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2478 = eq(btb_rd_addr_f, UInt<8>("h0b7")) @[ifu_bp_ctl.scala 417:77] - node _T_2479 = bits(_T_2478, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2480 = eq(btb_rd_addr_f, UInt<8>("h0b8")) @[ifu_bp_ctl.scala 417:77] - node _T_2481 = bits(_T_2480, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2482 = eq(btb_rd_addr_f, UInt<8>("h0b9")) @[ifu_bp_ctl.scala 417:77] - node _T_2483 = bits(_T_2482, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2484 = eq(btb_rd_addr_f, UInt<8>("h0ba")) @[ifu_bp_ctl.scala 417:77] - node _T_2485 = bits(_T_2484, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2486 = eq(btb_rd_addr_f, UInt<8>("h0bb")) @[ifu_bp_ctl.scala 417:77] - node _T_2487 = bits(_T_2486, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2488 = eq(btb_rd_addr_f, UInt<8>("h0bc")) @[ifu_bp_ctl.scala 417:77] - node _T_2489 = bits(_T_2488, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2490 = eq(btb_rd_addr_f, UInt<8>("h0bd")) @[ifu_bp_ctl.scala 417:77] - node _T_2491 = bits(_T_2490, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2492 = eq(btb_rd_addr_f, UInt<8>("h0be")) @[ifu_bp_ctl.scala 417:77] - node _T_2493 = bits(_T_2492, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2494 = eq(btb_rd_addr_f, UInt<8>("h0bf")) @[ifu_bp_ctl.scala 417:77] - node _T_2495 = bits(_T_2494, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2496 = eq(btb_rd_addr_f, UInt<8>("h0c0")) @[ifu_bp_ctl.scala 417:77] - node _T_2497 = bits(_T_2496, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2498 = eq(btb_rd_addr_f, UInt<8>("h0c1")) @[ifu_bp_ctl.scala 417:77] - node _T_2499 = bits(_T_2498, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2500 = eq(btb_rd_addr_f, UInt<8>("h0c2")) @[ifu_bp_ctl.scala 417:77] - node _T_2501 = bits(_T_2500, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2502 = eq(btb_rd_addr_f, UInt<8>("h0c3")) @[ifu_bp_ctl.scala 417:77] - node _T_2503 = bits(_T_2502, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2504 = eq(btb_rd_addr_f, UInt<8>("h0c4")) @[ifu_bp_ctl.scala 417:77] - node _T_2505 = bits(_T_2504, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2506 = eq(btb_rd_addr_f, UInt<8>("h0c5")) @[ifu_bp_ctl.scala 417:77] - node _T_2507 = bits(_T_2506, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2508 = eq(btb_rd_addr_f, UInt<8>("h0c6")) @[ifu_bp_ctl.scala 417:77] - node _T_2509 = bits(_T_2508, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2510 = eq(btb_rd_addr_f, UInt<8>("h0c7")) @[ifu_bp_ctl.scala 417:77] - node _T_2511 = bits(_T_2510, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2512 = eq(btb_rd_addr_f, UInt<8>("h0c8")) @[ifu_bp_ctl.scala 417:77] - node _T_2513 = bits(_T_2512, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2514 = eq(btb_rd_addr_f, UInt<8>("h0c9")) @[ifu_bp_ctl.scala 417:77] - node _T_2515 = bits(_T_2514, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2516 = eq(btb_rd_addr_f, UInt<8>("h0ca")) @[ifu_bp_ctl.scala 417:77] - node _T_2517 = bits(_T_2516, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2518 = eq(btb_rd_addr_f, UInt<8>("h0cb")) @[ifu_bp_ctl.scala 417:77] - node _T_2519 = bits(_T_2518, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2520 = eq(btb_rd_addr_f, UInt<8>("h0cc")) @[ifu_bp_ctl.scala 417:77] - node _T_2521 = bits(_T_2520, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2522 = eq(btb_rd_addr_f, UInt<8>("h0cd")) @[ifu_bp_ctl.scala 417:77] - node _T_2523 = bits(_T_2522, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2524 = eq(btb_rd_addr_f, UInt<8>("h0ce")) @[ifu_bp_ctl.scala 417:77] - node _T_2525 = bits(_T_2524, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2526 = eq(btb_rd_addr_f, UInt<8>("h0cf")) @[ifu_bp_ctl.scala 417:77] - node _T_2527 = bits(_T_2526, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2528 = eq(btb_rd_addr_f, UInt<8>("h0d0")) @[ifu_bp_ctl.scala 417:77] - node _T_2529 = bits(_T_2528, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2530 = eq(btb_rd_addr_f, UInt<8>("h0d1")) @[ifu_bp_ctl.scala 417:77] - node _T_2531 = bits(_T_2530, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2532 = eq(btb_rd_addr_f, UInt<8>("h0d2")) @[ifu_bp_ctl.scala 417:77] - node _T_2533 = bits(_T_2532, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2534 = eq(btb_rd_addr_f, UInt<8>("h0d3")) @[ifu_bp_ctl.scala 417:77] - node _T_2535 = bits(_T_2534, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2536 = eq(btb_rd_addr_f, UInt<8>("h0d4")) @[ifu_bp_ctl.scala 417:77] - node _T_2537 = bits(_T_2536, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2538 = eq(btb_rd_addr_f, UInt<8>("h0d5")) @[ifu_bp_ctl.scala 417:77] - node _T_2539 = bits(_T_2538, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2540 = eq(btb_rd_addr_f, UInt<8>("h0d6")) @[ifu_bp_ctl.scala 417:77] - node _T_2541 = bits(_T_2540, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2542 = eq(btb_rd_addr_f, UInt<8>("h0d7")) @[ifu_bp_ctl.scala 417:77] - node _T_2543 = bits(_T_2542, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2544 = eq(btb_rd_addr_f, UInt<8>("h0d8")) @[ifu_bp_ctl.scala 417:77] - node _T_2545 = bits(_T_2544, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2546 = eq(btb_rd_addr_f, UInt<8>("h0d9")) @[ifu_bp_ctl.scala 417:77] - node _T_2547 = bits(_T_2546, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2548 = eq(btb_rd_addr_f, UInt<8>("h0da")) @[ifu_bp_ctl.scala 417:77] - node _T_2549 = bits(_T_2548, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2550 = eq(btb_rd_addr_f, UInt<8>("h0db")) @[ifu_bp_ctl.scala 417:77] - node _T_2551 = bits(_T_2550, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2552 = eq(btb_rd_addr_f, UInt<8>("h0dc")) @[ifu_bp_ctl.scala 417:77] - node _T_2553 = bits(_T_2552, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2554 = eq(btb_rd_addr_f, UInt<8>("h0dd")) @[ifu_bp_ctl.scala 417:77] - node _T_2555 = bits(_T_2554, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2556 = eq(btb_rd_addr_f, UInt<8>("h0de")) @[ifu_bp_ctl.scala 417:77] - node _T_2557 = bits(_T_2556, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2558 = eq(btb_rd_addr_f, UInt<8>("h0df")) @[ifu_bp_ctl.scala 417:77] - node _T_2559 = bits(_T_2558, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2560 = eq(btb_rd_addr_f, UInt<8>("h0e0")) @[ifu_bp_ctl.scala 417:77] - node _T_2561 = bits(_T_2560, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2562 = eq(btb_rd_addr_f, UInt<8>("h0e1")) @[ifu_bp_ctl.scala 417:77] - node _T_2563 = bits(_T_2562, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2564 = eq(btb_rd_addr_f, UInt<8>("h0e2")) @[ifu_bp_ctl.scala 417:77] - node _T_2565 = bits(_T_2564, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2566 = eq(btb_rd_addr_f, UInt<8>("h0e3")) @[ifu_bp_ctl.scala 417:77] - node _T_2567 = bits(_T_2566, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2568 = eq(btb_rd_addr_f, UInt<8>("h0e4")) @[ifu_bp_ctl.scala 417:77] - node _T_2569 = bits(_T_2568, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2570 = eq(btb_rd_addr_f, UInt<8>("h0e5")) @[ifu_bp_ctl.scala 417:77] - node _T_2571 = bits(_T_2570, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2572 = eq(btb_rd_addr_f, UInt<8>("h0e6")) @[ifu_bp_ctl.scala 417:77] - node _T_2573 = bits(_T_2572, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2574 = eq(btb_rd_addr_f, UInt<8>("h0e7")) @[ifu_bp_ctl.scala 417:77] - node _T_2575 = bits(_T_2574, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2576 = eq(btb_rd_addr_f, UInt<8>("h0e8")) @[ifu_bp_ctl.scala 417:77] - node _T_2577 = bits(_T_2576, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2578 = eq(btb_rd_addr_f, UInt<8>("h0e9")) @[ifu_bp_ctl.scala 417:77] - node _T_2579 = bits(_T_2578, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2580 = eq(btb_rd_addr_f, UInt<8>("h0ea")) @[ifu_bp_ctl.scala 417:77] - node _T_2581 = bits(_T_2580, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2582 = eq(btb_rd_addr_f, UInt<8>("h0eb")) @[ifu_bp_ctl.scala 417:77] - node _T_2583 = bits(_T_2582, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2584 = eq(btb_rd_addr_f, UInt<8>("h0ec")) @[ifu_bp_ctl.scala 417:77] - node _T_2585 = bits(_T_2584, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2586 = eq(btb_rd_addr_f, UInt<8>("h0ed")) @[ifu_bp_ctl.scala 417:77] - node _T_2587 = bits(_T_2586, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2588 = eq(btb_rd_addr_f, UInt<8>("h0ee")) @[ifu_bp_ctl.scala 417:77] - node _T_2589 = bits(_T_2588, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2590 = eq(btb_rd_addr_f, UInt<8>("h0ef")) @[ifu_bp_ctl.scala 417:77] - node _T_2591 = bits(_T_2590, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2592 = eq(btb_rd_addr_f, UInt<8>("h0f0")) @[ifu_bp_ctl.scala 417:77] - node _T_2593 = bits(_T_2592, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2594 = eq(btb_rd_addr_f, UInt<8>("h0f1")) @[ifu_bp_ctl.scala 417:77] - node _T_2595 = bits(_T_2594, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2596 = eq(btb_rd_addr_f, UInt<8>("h0f2")) @[ifu_bp_ctl.scala 417:77] - node _T_2597 = bits(_T_2596, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2598 = eq(btb_rd_addr_f, UInt<8>("h0f3")) @[ifu_bp_ctl.scala 417:77] - node _T_2599 = bits(_T_2598, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2600 = eq(btb_rd_addr_f, UInt<8>("h0f4")) @[ifu_bp_ctl.scala 417:77] - node _T_2601 = bits(_T_2600, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2602 = eq(btb_rd_addr_f, UInt<8>("h0f5")) @[ifu_bp_ctl.scala 417:77] - node _T_2603 = bits(_T_2602, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2604 = eq(btb_rd_addr_f, UInt<8>("h0f6")) @[ifu_bp_ctl.scala 417:77] - node _T_2605 = bits(_T_2604, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2606 = eq(btb_rd_addr_f, UInt<8>("h0f7")) @[ifu_bp_ctl.scala 417:77] - node _T_2607 = bits(_T_2606, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2608 = eq(btb_rd_addr_f, UInt<8>("h0f8")) @[ifu_bp_ctl.scala 417:77] - node _T_2609 = bits(_T_2608, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2610 = eq(btb_rd_addr_f, UInt<8>("h0f9")) @[ifu_bp_ctl.scala 417:77] - node _T_2611 = bits(_T_2610, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2612 = eq(btb_rd_addr_f, UInt<8>("h0fa")) @[ifu_bp_ctl.scala 417:77] - node _T_2613 = bits(_T_2612, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2614 = eq(btb_rd_addr_f, UInt<8>("h0fb")) @[ifu_bp_ctl.scala 417:77] - node _T_2615 = bits(_T_2614, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2616 = eq(btb_rd_addr_f, UInt<8>("h0fc")) @[ifu_bp_ctl.scala 417:77] - node _T_2617 = bits(_T_2616, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2618 = eq(btb_rd_addr_f, UInt<8>("h0fd")) @[ifu_bp_ctl.scala 417:77] - node _T_2619 = bits(_T_2618, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2620 = eq(btb_rd_addr_f, UInt<8>("h0fe")) @[ifu_bp_ctl.scala 417:77] - node _T_2621 = bits(_T_2620, 0, 0) @[ifu_bp_ctl.scala 417:85] - node _T_2622 = eq(btb_rd_addr_f, UInt<8>("h0ff")) @[ifu_bp_ctl.scala 417:77] - node _T_2623 = bits(_T_2622, 0, 0) @[ifu_bp_ctl.scala 417:85] + node _T_2112 = eq(btb_rd_addr_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 418:77] + node _T_2113 = bits(_T_2112, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2114 = eq(btb_rd_addr_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 418:77] + node _T_2115 = bits(_T_2114, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2116 = eq(btb_rd_addr_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 418:77] + node _T_2117 = bits(_T_2116, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2118 = eq(btb_rd_addr_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 418:77] + node _T_2119 = bits(_T_2118, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2120 = eq(btb_rd_addr_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 418:77] + node _T_2121 = bits(_T_2120, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2122 = eq(btb_rd_addr_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 418:77] + node _T_2123 = bits(_T_2122, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2124 = eq(btb_rd_addr_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 418:77] + node _T_2125 = bits(_T_2124, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2126 = eq(btb_rd_addr_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 418:77] + node _T_2127 = bits(_T_2126, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2128 = eq(btb_rd_addr_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 418:77] + node _T_2129 = bits(_T_2128, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2130 = eq(btb_rd_addr_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 418:77] + node _T_2131 = bits(_T_2130, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2132 = eq(btb_rd_addr_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 418:77] + node _T_2133 = bits(_T_2132, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2134 = eq(btb_rd_addr_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 418:77] + node _T_2135 = bits(_T_2134, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2136 = eq(btb_rd_addr_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 418:77] + node _T_2137 = bits(_T_2136, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2138 = eq(btb_rd_addr_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 418:77] + node _T_2139 = bits(_T_2138, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2140 = eq(btb_rd_addr_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 418:77] + node _T_2141 = bits(_T_2140, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2142 = eq(btb_rd_addr_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 418:77] + node _T_2143 = bits(_T_2142, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2144 = eq(btb_rd_addr_f, UInt<5>("h010")) @[ifu_bp_ctl.scala 418:77] + node _T_2145 = bits(_T_2144, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2146 = eq(btb_rd_addr_f, UInt<5>("h011")) @[ifu_bp_ctl.scala 418:77] + node _T_2147 = bits(_T_2146, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2148 = eq(btb_rd_addr_f, UInt<5>("h012")) @[ifu_bp_ctl.scala 418:77] + node _T_2149 = bits(_T_2148, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2150 = eq(btb_rd_addr_f, UInt<5>("h013")) @[ifu_bp_ctl.scala 418:77] + node _T_2151 = bits(_T_2150, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2152 = eq(btb_rd_addr_f, UInt<5>("h014")) @[ifu_bp_ctl.scala 418:77] + node _T_2153 = bits(_T_2152, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2154 = eq(btb_rd_addr_f, UInt<5>("h015")) @[ifu_bp_ctl.scala 418:77] + node _T_2155 = bits(_T_2154, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2156 = eq(btb_rd_addr_f, UInt<5>("h016")) @[ifu_bp_ctl.scala 418:77] + node _T_2157 = bits(_T_2156, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2158 = eq(btb_rd_addr_f, UInt<5>("h017")) @[ifu_bp_ctl.scala 418:77] + node _T_2159 = bits(_T_2158, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2160 = eq(btb_rd_addr_f, UInt<5>("h018")) @[ifu_bp_ctl.scala 418:77] + node _T_2161 = bits(_T_2160, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2162 = eq(btb_rd_addr_f, UInt<5>("h019")) @[ifu_bp_ctl.scala 418:77] + node _T_2163 = bits(_T_2162, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2164 = eq(btb_rd_addr_f, UInt<5>("h01a")) @[ifu_bp_ctl.scala 418:77] + node _T_2165 = bits(_T_2164, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2166 = eq(btb_rd_addr_f, UInt<5>("h01b")) @[ifu_bp_ctl.scala 418:77] + node _T_2167 = bits(_T_2166, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2168 = eq(btb_rd_addr_f, UInt<5>("h01c")) @[ifu_bp_ctl.scala 418:77] + node _T_2169 = bits(_T_2168, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2170 = eq(btb_rd_addr_f, UInt<5>("h01d")) @[ifu_bp_ctl.scala 418:77] + node _T_2171 = bits(_T_2170, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2172 = eq(btb_rd_addr_f, UInt<5>("h01e")) @[ifu_bp_ctl.scala 418:77] + node _T_2173 = bits(_T_2172, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2174 = eq(btb_rd_addr_f, UInt<5>("h01f")) @[ifu_bp_ctl.scala 418:77] + node _T_2175 = bits(_T_2174, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2176 = eq(btb_rd_addr_f, UInt<6>("h020")) @[ifu_bp_ctl.scala 418:77] + node _T_2177 = bits(_T_2176, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2178 = eq(btb_rd_addr_f, UInt<6>("h021")) @[ifu_bp_ctl.scala 418:77] + node _T_2179 = bits(_T_2178, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2180 = eq(btb_rd_addr_f, UInt<6>("h022")) @[ifu_bp_ctl.scala 418:77] + node _T_2181 = bits(_T_2180, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2182 = eq(btb_rd_addr_f, UInt<6>("h023")) @[ifu_bp_ctl.scala 418:77] + node _T_2183 = bits(_T_2182, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2184 = eq(btb_rd_addr_f, UInt<6>("h024")) @[ifu_bp_ctl.scala 418:77] + node _T_2185 = bits(_T_2184, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2186 = eq(btb_rd_addr_f, UInt<6>("h025")) @[ifu_bp_ctl.scala 418:77] + node _T_2187 = bits(_T_2186, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2188 = eq(btb_rd_addr_f, UInt<6>("h026")) @[ifu_bp_ctl.scala 418:77] + node _T_2189 = bits(_T_2188, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2190 = eq(btb_rd_addr_f, UInt<6>("h027")) @[ifu_bp_ctl.scala 418:77] + node _T_2191 = bits(_T_2190, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2192 = eq(btb_rd_addr_f, UInt<6>("h028")) @[ifu_bp_ctl.scala 418:77] + node _T_2193 = bits(_T_2192, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2194 = eq(btb_rd_addr_f, UInt<6>("h029")) @[ifu_bp_ctl.scala 418:77] + node _T_2195 = bits(_T_2194, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2196 = eq(btb_rd_addr_f, UInt<6>("h02a")) @[ifu_bp_ctl.scala 418:77] + node _T_2197 = bits(_T_2196, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2198 = eq(btb_rd_addr_f, UInt<6>("h02b")) @[ifu_bp_ctl.scala 418:77] + node _T_2199 = bits(_T_2198, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2200 = eq(btb_rd_addr_f, UInt<6>("h02c")) @[ifu_bp_ctl.scala 418:77] + node _T_2201 = bits(_T_2200, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2202 = eq(btb_rd_addr_f, UInt<6>("h02d")) @[ifu_bp_ctl.scala 418:77] + node _T_2203 = bits(_T_2202, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2204 = eq(btb_rd_addr_f, UInt<6>("h02e")) @[ifu_bp_ctl.scala 418:77] + node _T_2205 = bits(_T_2204, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2206 = eq(btb_rd_addr_f, UInt<6>("h02f")) @[ifu_bp_ctl.scala 418:77] + node _T_2207 = bits(_T_2206, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2208 = eq(btb_rd_addr_f, UInt<6>("h030")) @[ifu_bp_ctl.scala 418:77] + node _T_2209 = bits(_T_2208, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2210 = eq(btb_rd_addr_f, UInt<6>("h031")) @[ifu_bp_ctl.scala 418:77] + node _T_2211 = bits(_T_2210, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2212 = eq(btb_rd_addr_f, UInt<6>("h032")) @[ifu_bp_ctl.scala 418:77] + node _T_2213 = bits(_T_2212, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2214 = eq(btb_rd_addr_f, UInt<6>("h033")) @[ifu_bp_ctl.scala 418:77] + node _T_2215 = bits(_T_2214, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2216 = eq(btb_rd_addr_f, UInt<6>("h034")) @[ifu_bp_ctl.scala 418:77] + node _T_2217 = bits(_T_2216, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2218 = eq(btb_rd_addr_f, UInt<6>("h035")) @[ifu_bp_ctl.scala 418:77] + node _T_2219 = bits(_T_2218, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2220 = eq(btb_rd_addr_f, UInt<6>("h036")) @[ifu_bp_ctl.scala 418:77] + node _T_2221 = bits(_T_2220, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2222 = eq(btb_rd_addr_f, UInt<6>("h037")) @[ifu_bp_ctl.scala 418:77] + node _T_2223 = bits(_T_2222, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2224 = eq(btb_rd_addr_f, UInt<6>("h038")) @[ifu_bp_ctl.scala 418:77] + node _T_2225 = bits(_T_2224, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2226 = eq(btb_rd_addr_f, UInt<6>("h039")) @[ifu_bp_ctl.scala 418:77] + node _T_2227 = bits(_T_2226, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2228 = eq(btb_rd_addr_f, UInt<6>("h03a")) @[ifu_bp_ctl.scala 418:77] + node _T_2229 = bits(_T_2228, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2230 = eq(btb_rd_addr_f, UInt<6>("h03b")) @[ifu_bp_ctl.scala 418:77] + node _T_2231 = bits(_T_2230, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2232 = eq(btb_rd_addr_f, UInt<6>("h03c")) @[ifu_bp_ctl.scala 418:77] + node _T_2233 = bits(_T_2232, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2234 = eq(btb_rd_addr_f, UInt<6>("h03d")) @[ifu_bp_ctl.scala 418:77] + node _T_2235 = bits(_T_2234, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2236 = eq(btb_rd_addr_f, UInt<6>("h03e")) @[ifu_bp_ctl.scala 418:77] + node _T_2237 = bits(_T_2236, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2238 = eq(btb_rd_addr_f, UInt<6>("h03f")) @[ifu_bp_ctl.scala 418:77] + node _T_2239 = bits(_T_2238, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2240 = eq(btb_rd_addr_f, UInt<7>("h040")) @[ifu_bp_ctl.scala 418:77] + node _T_2241 = bits(_T_2240, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2242 = eq(btb_rd_addr_f, UInt<7>("h041")) @[ifu_bp_ctl.scala 418:77] + node _T_2243 = bits(_T_2242, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2244 = eq(btb_rd_addr_f, UInt<7>("h042")) @[ifu_bp_ctl.scala 418:77] + node _T_2245 = bits(_T_2244, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2246 = eq(btb_rd_addr_f, UInt<7>("h043")) @[ifu_bp_ctl.scala 418:77] + node _T_2247 = bits(_T_2246, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2248 = eq(btb_rd_addr_f, UInt<7>("h044")) @[ifu_bp_ctl.scala 418:77] + node _T_2249 = bits(_T_2248, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2250 = eq(btb_rd_addr_f, UInt<7>("h045")) @[ifu_bp_ctl.scala 418:77] + node _T_2251 = bits(_T_2250, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2252 = eq(btb_rd_addr_f, UInt<7>("h046")) @[ifu_bp_ctl.scala 418:77] + node _T_2253 = bits(_T_2252, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2254 = eq(btb_rd_addr_f, UInt<7>("h047")) @[ifu_bp_ctl.scala 418:77] + node _T_2255 = bits(_T_2254, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2256 = eq(btb_rd_addr_f, UInt<7>("h048")) @[ifu_bp_ctl.scala 418:77] + node _T_2257 = bits(_T_2256, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2258 = eq(btb_rd_addr_f, UInt<7>("h049")) @[ifu_bp_ctl.scala 418:77] + node _T_2259 = bits(_T_2258, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2260 = eq(btb_rd_addr_f, UInt<7>("h04a")) @[ifu_bp_ctl.scala 418:77] + node _T_2261 = bits(_T_2260, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2262 = eq(btb_rd_addr_f, UInt<7>("h04b")) @[ifu_bp_ctl.scala 418:77] + node _T_2263 = bits(_T_2262, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2264 = eq(btb_rd_addr_f, UInt<7>("h04c")) @[ifu_bp_ctl.scala 418:77] + node _T_2265 = bits(_T_2264, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2266 = eq(btb_rd_addr_f, UInt<7>("h04d")) @[ifu_bp_ctl.scala 418:77] + node _T_2267 = bits(_T_2266, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2268 = eq(btb_rd_addr_f, UInt<7>("h04e")) @[ifu_bp_ctl.scala 418:77] + node _T_2269 = bits(_T_2268, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2270 = eq(btb_rd_addr_f, UInt<7>("h04f")) @[ifu_bp_ctl.scala 418:77] + node _T_2271 = bits(_T_2270, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2272 = eq(btb_rd_addr_f, UInt<7>("h050")) @[ifu_bp_ctl.scala 418:77] + node _T_2273 = bits(_T_2272, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2274 = eq(btb_rd_addr_f, UInt<7>("h051")) @[ifu_bp_ctl.scala 418:77] + node _T_2275 = bits(_T_2274, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2276 = eq(btb_rd_addr_f, UInt<7>("h052")) @[ifu_bp_ctl.scala 418:77] + node _T_2277 = bits(_T_2276, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2278 = eq(btb_rd_addr_f, UInt<7>("h053")) @[ifu_bp_ctl.scala 418:77] + node _T_2279 = bits(_T_2278, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2280 = eq(btb_rd_addr_f, UInt<7>("h054")) @[ifu_bp_ctl.scala 418:77] + node _T_2281 = bits(_T_2280, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2282 = eq(btb_rd_addr_f, UInt<7>("h055")) @[ifu_bp_ctl.scala 418:77] + node _T_2283 = bits(_T_2282, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2284 = eq(btb_rd_addr_f, UInt<7>("h056")) @[ifu_bp_ctl.scala 418:77] + node _T_2285 = bits(_T_2284, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2286 = eq(btb_rd_addr_f, UInt<7>("h057")) @[ifu_bp_ctl.scala 418:77] + node _T_2287 = bits(_T_2286, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2288 = eq(btb_rd_addr_f, UInt<7>("h058")) @[ifu_bp_ctl.scala 418:77] + node _T_2289 = bits(_T_2288, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2290 = eq(btb_rd_addr_f, UInt<7>("h059")) @[ifu_bp_ctl.scala 418:77] + node _T_2291 = bits(_T_2290, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2292 = eq(btb_rd_addr_f, UInt<7>("h05a")) @[ifu_bp_ctl.scala 418:77] + node _T_2293 = bits(_T_2292, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2294 = eq(btb_rd_addr_f, UInt<7>("h05b")) @[ifu_bp_ctl.scala 418:77] + node _T_2295 = bits(_T_2294, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2296 = eq(btb_rd_addr_f, UInt<7>("h05c")) @[ifu_bp_ctl.scala 418:77] + node _T_2297 = bits(_T_2296, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2298 = eq(btb_rd_addr_f, UInt<7>("h05d")) @[ifu_bp_ctl.scala 418:77] + node _T_2299 = bits(_T_2298, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2300 = eq(btb_rd_addr_f, UInt<7>("h05e")) @[ifu_bp_ctl.scala 418:77] + node _T_2301 = bits(_T_2300, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2302 = eq(btb_rd_addr_f, UInt<7>("h05f")) @[ifu_bp_ctl.scala 418:77] + node _T_2303 = bits(_T_2302, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2304 = eq(btb_rd_addr_f, UInt<7>("h060")) @[ifu_bp_ctl.scala 418:77] + node _T_2305 = bits(_T_2304, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2306 = eq(btb_rd_addr_f, UInt<7>("h061")) @[ifu_bp_ctl.scala 418:77] + node _T_2307 = bits(_T_2306, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2308 = eq(btb_rd_addr_f, UInt<7>("h062")) @[ifu_bp_ctl.scala 418:77] + node _T_2309 = bits(_T_2308, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2310 = eq(btb_rd_addr_f, UInt<7>("h063")) @[ifu_bp_ctl.scala 418:77] + node _T_2311 = bits(_T_2310, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2312 = eq(btb_rd_addr_f, UInt<7>("h064")) @[ifu_bp_ctl.scala 418:77] + node _T_2313 = bits(_T_2312, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2314 = eq(btb_rd_addr_f, UInt<7>("h065")) @[ifu_bp_ctl.scala 418:77] + node _T_2315 = bits(_T_2314, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2316 = eq(btb_rd_addr_f, UInt<7>("h066")) @[ifu_bp_ctl.scala 418:77] + node _T_2317 = bits(_T_2316, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2318 = eq(btb_rd_addr_f, UInt<7>("h067")) @[ifu_bp_ctl.scala 418:77] + node _T_2319 = bits(_T_2318, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2320 = eq(btb_rd_addr_f, UInt<7>("h068")) @[ifu_bp_ctl.scala 418:77] + node _T_2321 = bits(_T_2320, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2322 = eq(btb_rd_addr_f, UInt<7>("h069")) @[ifu_bp_ctl.scala 418:77] + node _T_2323 = bits(_T_2322, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2324 = eq(btb_rd_addr_f, UInt<7>("h06a")) @[ifu_bp_ctl.scala 418:77] + node _T_2325 = bits(_T_2324, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2326 = eq(btb_rd_addr_f, UInt<7>("h06b")) @[ifu_bp_ctl.scala 418:77] + node _T_2327 = bits(_T_2326, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2328 = eq(btb_rd_addr_f, UInt<7>("h06c")) @[ifu_bp_ctl.scala 418:77] + node _T_2329 = bits(_T_2328, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2330 = eq(btb_rd_addr_f, UInt<7>("h06d")) @[ifu_bp_ctl.scala 418:77] + node _T_2331 = bits(_T_2330, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2332 = eq(btb_rd_addr_f, UInt<7>("h06e")) @[ifu_bp_ctl.scala 418:77] + node _T_2333 = bits(_T_2332, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2334 = eq(btb_rd_addr_f, UInt<7>("h06f")) @[ifu_bp_ctl.scala 418:77] + node _T_2335 = bits(_T_2334, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2336 = eq(btb_rd_addr_f, UInt<7>("h070")) @[ifu_bp_ctl.scala 418:77] + node _T_2337 = bits(_T_2336, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2338 = eq(btb_rd_addr_f, UInt<7>("h071")) @[ifu_bp_ctl.scala 418:77] + node _T_2339 = bits(_T_2338, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2340 = eq(btb_rd_addr_f, UInt<7>("h072")) @[ifu_bp_ctl.scala 418:77] + node _T_2341 = bits(_T_2340, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2342 = eq(btb_rd_addr_f, UInt<7>("h073")) @[ifu_bp_ctl.scala 418:77] + node _T_2343 = bits(_T_2342, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2344 = eq(btb_rd_addr_f, UInt<7>("h074")) @[ifu_bp_ctl.scala 418:77] + node _T_2345 = bits(_T_2344, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2346 = eq(btb_rd_addr_f, UInt<7>("h075")) @[ifu_bp_ctl.scala 418:77] + node _T_2347 = bits(_T_2346, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2348 = eq(btb_rd_addr_f, UInt<7>("h076")) @[ifu_bp_ctl.scala 418:77] + node _T_2349 = bits(_T_2348, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2350 = eq(btb_rd_addr_f, UInt<7>("h077")) @[ifu_bp_ctl.scala 418:77] + node _T_2351 = bits(_T_2350, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2352 = eq(btb_rd_addr_f, UInt<7>("h078")) @[ifu_bp_ctl.scala 418:77] + node _T_2353 = bits(_T_2352, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2354 = eq(btb_rd_addr_f, UInt<7>("h079")) @[ifu_bp_ctl.scala 418:77] + node _T_2355 = bits(_T_2354, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2356 = eq(btb_rd_addr_f, UInt<7>("h07a")) @[ifu_bp_ctl.scala 418:77] + node _T_2357 = bits(_T_2356, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2358 = eq(btb_rd_addr_f, UInt<7>("h07b")) @[ifu_bp_ctl.scala 418:77] + node _T_2359 = bits(_T_2358, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2360 = eq(btb_rd_addr_f, UInt<7>("h07c")) @[ifu_bp_ctl.scala 418:77] + node _T_2361 = bits(_T_2360, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2362 = eq(btb_rd_addr_f, UInt<7>("h07d")) @[ifu_bp_ctl.scala 418:77] + node _T_2363 = bits(_T_2362, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2364 = eq(btb_rd_addr_f, UInt<7>("h07e")) @[ifu_bp_ctl.scala 418:77] + node _T_2365 = bits(_T_2364, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2366 = eq(btb_rd_addr_f, UInt<7>("h07f")) @[ifu_bp_ctl.scala 418:77] + node _T_2367 = bits(_T_2366, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2368 = eq(btb_rd_addr_f, UInt<8>("h080")) @[ifu_bp_ctl.scala 418:77] + node _T_2369 = bits(_T_2368, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2370 = eq(btb_rd_addr_f, UInt<8>("h081")) @[ifu_bp_ctl.scala 418:77] + node _T_2371 = bits(_T_2370, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2372 = eq(btb_rd_addr_f, UInt<8>("h082")) @[ifu_bp_ctl.scala 418:77] + node _T_2373 = bits(_T_2372, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2374 = eq(btb_rd_addr_f, UInt<8>("h083")) @[ifu_bp_ctl.scala 418:77] + node _T_2375 = bits(_T_2374, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2376 = eq(btb_rd_addr_f, UInt<8>("h084")) @[ifu_bp_ctl.scala 418:77] + node _T_2377 = bits(_T_2376, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2378 = eq(btb_rd_addr_f, UInt<8>("h085")) @[ifu_bp_ctl.scala 418:77] + node _T_2379 = bits(_T_2378, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2380 = eq(btb_rd_addr_f, UInt<8>("h086")) @[ifu_bp_ctl.scala 418:77] + node _T_2381 = bits(_T_2380, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2382 = eq(btb_rd_addr_f, UInt<8>("h087")) @[ifu_bp_ctl.scala 418:77] + node _T_2383 = bits(_T_2382, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2384 = eq(btb_rd_addr_f, UInt<8>("h088")) @[ifu_bp_ctl.scala 418:77] + node _T_2385 = bits(_T_2384, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2386 = eq(btb_rd_addr_f, UInt<8>("h089")) @[ifu_bp_ctl.scala 418:77] + node _T_2387 = bits(_T_2386, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2388 = eq(btb_rd_addr_f, UInt<8>("h08a")) @[ifu_bp_ctl.scala 418:77] + node _T_2389 = bits(_T_2388, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2390 = eq(btb_rd_addr_f, UInt<8>("h08b")) @[ifu_bp_ctl.scala 418:77] + node _T_2391 = bits(_T_2390, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2392 = eq(btb_rd_addr_f, UInt<8>("h08c")) @[ifu_bp_ctl.scala 418:77] + node _T_2393 = bits(_T_2392, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2394 = eq(btb_rd_addr_f, UInt<8>("h08d")) @[ifu_bp_ctl.scala 418:77] + node _T_2395 = bits(_T_2394, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2396 = eq(btb_rd_addr_f, UInt<8>("h08e")) @[ifu_bp_ctl.scala 418:77] + node _T_2397 = bits(_T_2396, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2398 = eq(btb_rd_addr_f, UInt<8>("h08f")) @[ifu_bp_ctl.scala 418:77] + node _T_2399 = bits(_T_2398, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2400 = eq(btb_rd_addr_f, UInt<8>("h090")) @[ifu_bp_ctl.scala 418:77] + node _T_2401 = bits(_T_2400, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2402 = eq(btb_rd_addr_f, UInt<8>("h091")) @[ifu_bp_ctl.scala 418:77] + node _T_2403 = bits(_T_2402, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2404 = eq(btb_rd_addr_f, UInt<8>("h092")) @[ifu_bp_ctl.scala 418:77] + node _T_2405 = bits(_T_2404, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2406 = eq(btb_rd_addr_f, UInt<8>("h093")) @[ifu_bp_ctl.scala 418:77] + node _T_2407 = bits(_T_2406, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2408 = eq(btb_rd_addr_f, UInt<8>("h094")) @[ifu_bp_ctl.scala 418:77] + node _T_2409 = bits(_T_2408, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2410 = eq(btb_rd_addr_f, UInt<8>("h095")) @[ifu_bp_ctl.scala 418:77] + node _T_2411 = bits(_T_2410, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2412 = eq(btb_rd_addr_f, UInt<8>("h096")) @[ifu_bp_ctl.scala 418:77] + node _T_2413 = bits(_T_2412, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2414 = eq(btb_rd_addr_f, UInt<8>("h097")) @[ifu_bp_ctl.scala 418:77] + node _T_2415 = bits(_T_2414, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2416 = eq(btb_rd_addr_f, UInt<8>("h098")) @[ifu_bp_ctl.scala 418:77] + node _T_2417 = bits(_T_2416, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2418 = eq(btb_rd_addr_f, UInt<8>("h099")) @[ifu_bp_ctl.scala 418:77] + node _T_2419 = bits(_T_2418, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2420 = eq(btb_rd_addr_f, UInt<8>("h09a")) @[ifu_bp_ctl.scala 418:77] + node _T_2421 = bits(_T_2420, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2422 = eq(btb_rd_addr_f, UInt<8>("h09b")) @[ifu_bp_ctl.scala 418:77] + node _T_2423 = bits(_T_2422, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2424 = eq(btb_rd_addr_f, UInt<8>("h09c")) @[ifu_bp_ctl.scala 418:77] + node _T_2425 = bits(_T_2424, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2426 = eq(btb_rd_addr_f, UInt<8>("h09d")) @[ifu_bp_ctl.scala 418:77] + node _T_2427 = bits(_T_2426, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2428 = eq(btb_rd_addr_f, UInt<8>("h09e")) @[ifu_bp_ctl.scala 418:77] + node _T_2429 = bits(_T_2428, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2430 = eq(btb_rd_addr_f, UInt<8>("h09f")) @[ifu_bp_ctl.scala 418:77] + node _T_2431 = bits(_T_2430, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2432 = eq(btb_rd_addr_f, UInt<8>("h0a0")) @[ifu_bp_ctl.scala 418:77] + node _T_2433 = bits(_T_2432, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2434 = eq(btb_rd_addr_f, UInt<8>("h0a1")) @[ifu_bp_ctl.scala 418:77] + node _T_2435 = bits(_T_2434, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2436 = eq(btb_rd_addr_f, UInt<8>("h0a2")) @[ifu_bp_ctl.scala 418:77] + node _T_2437 = bits(_T_2436, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2438 = eq(btb_rd_addr_f, UInt<8>("h0a3")) @[ifu_bp_ctl.scala 418:77] + node _T_2439 = bits(_T_2438, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2440 = eq(btb_rd_addr_f, UInt<8>("h0a4")) @[ifu_bp_ctl.scala 418:77] + node _T_2441 = bits(_T_2440, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2442 = eq(btb_rd_addr_f, UInt<8>("h0a5")) @[ifu_bp_ctl.scala 418:77] + node _T_2443 = bits(_T_2442, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2444 = eq(btb_rd_addr_f, UInt<8>("h0a6")) @[ifu_bp_ctl.scala 418:77] + node _T_2445 = bits(_T_2444, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2446 = eq(btb_rd_addr_f, UInt<8>("h0a7")) @[ifu_bp_ctl.scala 418:77] + node _T_2447 = bits(_T_2446, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2448 = eq(btb_rd_addr_f, UInt<8>("h0a8")) @[ifu_bp_ctl.scala 418:77] + node _T_2449 = bits(_T_2448, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2450 = eq(btb_rd_addr_f, UInt<8>("h0a9")) @[ifu_bp_ctl.scala 418:77] + node _T_2451 = bits(_T_2450, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2452 = eq(btb_rd_addr_f, UInt<8>("h0aa")) @[ifu_bp_ctl.scala 418:77] + node _T_2453 = bits(_T_2452, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2454 = eq(btb_rd_addr_f, UInt<8>("h0ab")) @[ifu_bp_ctl.scala 418:77] + node _T_2455 = bits(_T_2454, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2456 = eq(btb_rd_addr_f, UInt<8>("h0ac")) @[ifu_bp_ctl.scala 418:77] + node _T_2457 = bits(_T_2456, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2458 = eq(btb_rd_addr_f, UInt<8>("h0ad")) @[ifu_bp_ctl.scala 418:77] + node _T_2459 = bits(_T_2458, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2460 = eq(btb_rd_addr_f, UInt<8>("h0ae")) @[ifu_bp_ctl.scala 418:77] + node _T_2461 = bits(_T_2460, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2462 = eq(btb_rd_addr_f, UInt<8>("h0af")) @[ifu_bp_ctl.scala 418:77] + node _T_2463 = bits(_T_2462, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2464 = eq(btb_rd_addr_f, UInt<8>("h0b0")) @[ifu_bp_ctl.scala 418:77] + node _T_2465 = bits(_T_2464, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2466 = eq(btb_rd_addr_f, UInt<8>("h0b1")) @[ifu_bp_ctl.scala 418:77] + node _T_2467 = bits(_T_2466, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2468 = eq(btb_rd_addr_f, UInt<8>("h0b2")) @[ifu_bp_ctl.scala 418:77] + node _T_2469 = bits(_T_2468, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2470 = eq(btb_rd_addr_f, UInt<8>("h0b3")) @[ifu_bp_ctl.scala 418:77] + node _T_2471 = bits(_T_2470, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2472 = eq(btb_rd_addr_f, UInt<8>("h0b4")) @[ifu_bp_ctl.scala 418:77] + node _T_2473 = bits(_T_2472, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2474 = eq(btb_rd_addr_f, UInt<8>("h0b5")) @[ifu_bp_ctl.scala 418:77] + node _T_2475 = bits(_T_2474, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2476 = eq(btb_rd_addr_f, UInt<8>("h0b6")) @[ifu_bp_ctl.scala 418:77] + node _T_2477 = bits(_T_2476, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2478 = eq(btb_rd_addr_f, UInt<8>("h0b7")) @[ifu_bp_ctl.scala 418:77] + node _T_2479 = bits(_T_2478, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2480 = eq(btb_rd_addr_f, UInt<8>("h0b8")) @[ifu_bp_ctl.scala 418:77] + node _T_2481 = bits(_T_2480, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2482 = eq(btb_rd_addr_f, UInt<8>("h0b9")) @[ifu_bp_ctl.scala 418:77] + node _T_2483 = bits(_T_2482, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2484 = eq(btb_rd_addr_f, UInt<8>("h0ba")) @[ifu_bp_ctl.scala 418:77] + node _T_2485 = bits(_T_2484, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2486 = eq(btb_rd_addr_f, UInt<8>("h0bb")) @[ifu_bp_ctl.scala 418:77] + node _T_2487 = bits(_T_2486, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2488 = eq(btb_rd_addr_f, UInt<8>("h0bc")) @[ifu_bp_ctl.scala 418:77] + node _T_2489 = bits(_T_2488, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2490 = eq(btb_rd_addr_f, UInt<8>("h0bd")) @[ifu_bp_ctl.scala 418:77] + node _T_2491 = bits(_T_2490, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2492 = eq(btb_rd_addr_f, UInt<8>("h0be")) @[ifu_bp_ctl.scala 418:77] + node _T_2493 = bits(_T_2492, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2494 = eq(btb_rd_addr_f, UInt<8>("h0bf")) @[ifu_bp_ctl.scala 418:77] + node _T_2495 = bits(_T_2494, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2496 = eq(btb_rd_addr_f, UInt<8>("h0c0")) @[ifu_bp_ctl.scala 418:77] + node _T_2497 = bits(_T_2496, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2498 = eq(btb_rd_addr_f, UInt<8>("h0c1")) @[ifu_bp_ctl.scala 418:77] + node _T_2499 = bits(_T_2498, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2500 = eq(btb_rd_addr_f, UInt<8>("h0c2")) @[ifu_bp_ctl.scala 418:77] + node _T_2501 = bits(_T_2500, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2502 = eq(btb_rd_addr_f, UInt<8>("h0c3")) @[ifu_bp_ctl.scala 418:77] + node _T_2503 = bits(_T_2502, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2504 = eq(btb_rd_addr_f, UInt<8>("h0c4")) @[ifu_bp_ctl.scala 418:77] + node _T_2505 = bits(_T_2504, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2506 = eq(btb_rd_addr_f, UInt<8>("h0c5")) @[ifu_bp_ctl.scala 418:77] + node _T_2507 = bits(_T_2506, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2508 = eq(btb_rd_addr_f, UInt<8>("h0c6")) @[ifu_bp_ctl.scala 418:77] + node _T_2509 = bits(_T_2508, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2510 = eq(btb_rd_addr_f, UInt<8>("h0c7")) @[ifu_bp_ctl.scala 418:77] + node _T_2511 = bits(_T_2510, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2512 = eq(btb_rd_addr_f, UInt<8>("h0c8")) @[ifu_bp_ctl.scala 418:77] + node _T_2513 = bits(_T_2512, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2514 = eq(btb_rd_addr_f, UInt<8>("h0c9")) @[ifu_bp_ctl.scala 418:77] + node _T_2515 = bits(_T_2514, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2516 = eq(btb_rd_addr_f, UInt<8>("h0ca")) @[ifu_bp_ctl.scala 418:77] + node _T_2517 = bits(_T_2516, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2518 = eq(btb_rd_addr_f, UInt<8>("h0cb")) @[ifu_bp_ctl.scala 418:77] + node _T_2519 = bits(_T_2518, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2520 = eq(btb_rd_addr_f, UInt<8>("h0cc")) @[ifu_bp_ctl.scala 418:77] + node _T_2521 = bits(_T_2520, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2522 = eq(btb_rd_addr_f, UInt<8>("h0cd")) @[ifu_bp_ctl.scala 418:77] + node _T_2523 = bits(_T_2522, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2524 = eq(btb_rd_addr_f, UInt<8>("h0ce")) @[ifu_bp_ctl.scala 418:77] + node _T_2525 = bits(_T_2524, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2526 = eq(btb_rd_addr_f, UInt<8>("h0cf")) @[ifu_bp_ctl.scala 418:77] + node _T_2527 = bits(_T_2526, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2528 = eq(btb_rd_addr_f, UInt<8>("h0d0")) @[ifu_bp_ctl.scala 418:77] + node _T_2529 = bits(_T_2528, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2530 = eq(btb_rd_addr_f, UInt<8>("h0d1")) @[ifu_bp_ctl.scala 418:77] + node _T_2531 = bits(_T_2530, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2532 = eq(btb_rd_addr_f, UInt<8>("h0d2")) @[ifu_bp_ctl.scala 418:77] + node _T_2533 = bits(_T_2532, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2534 = eq(btb_rd_addr_f, UInt<8>("h0d3")) @[ifu_bp_ctl.scala 418:77] + node _T_2535 = bits(_T_2534, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2536 = eq(btb_rd_addr_f, UInt<8>("h0d4")) @[ifu_bp_ctl.scala 418:77] + node _T_2537 = bits(_T_2536, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2538 = eq(btb_rd_addr_f, UInt<8>("h0d5")) @[ifu_bp_ctl.scala 418:77] + node _T_2539 = bits(_T_2538, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2540 = eq(btb_rd_addr_f, UInt<8>("h0d6")) @[ifu_bp_ctl.scala 418:77] + node _T_2541 = bits(_T_2540, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2542 = eq(btb_rd_addr_f, UInt<8>("h0d7")) @[ifu_bp_ctl.scala 418:77] + node _T_2543 = bits(_T_2542, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2544 = eq(btb_rd_addr_f, UInt<8>("h0d8")) @[ifu_bp_ctl.scala 418:77] + node _T_2545 = bits(_T_2544, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2546 = eq(btb_rd_addr_f, UInt<8>("h0d9")) @[ifu_bp_ctl.scala 418:77] + node _T_2547 = bits(_T_2546, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2548 = eq(btb_rd_addr_f, UInt<8>("h0da")) @[ifu_bp_ctl.scala 418:77] + node _T_2549 = bits(_T_2548, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2550 = eq(btb_rd_addr_f, UInt<8>("h0db")) @[ifu_bp_ctl.scala 418:77] + node _T_2551 = bits(_T_2550, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2552 = eq(btb_rd_addr_f, UInt<8>("h0dc")) @[ifu_bp_ctl.scala 418:77] + node _T_2553 = bits(_T_2552, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2554 = eq(btb_rd_addr_f, UInt<8>("h0dd")) @[ifu_bp_ctl.scala 418:77] + node _T_2555 = bits(_T_2554, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2556 = eq(btb_rd_addr_f, UInt<8>("h0de")) @[ifu_bp_ctl.scala 418:77] + node _T_2557 = bits(_T_2556, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2558 = eq(btb_rd_addr_f, UInt<8>("h0df")) @[ifu_bp_ctl.scala 418:77] + node _T_2559 = bits(_T_2558, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2560 = eq(btb_rd_addr_f, UInt<8>("h0e0")) @[ifu_bp_ctl.scala 418:77] + node _T_2561 = bits(_T_2560, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2562 = eq(btb_rd_addr_f, UInt<8>("h0e1")) @[ifu_bp_ctl.scala 418:77] + node _T_2563 = bits(_T_2562, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2564 = eq(btb_rd_addr_f, UInt<8>("h0e2")) @[ifu_bp_ctl.scala 418:77] + node _T_2565 = bits(_T_2564, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2566 = eq(btb_rd_addr_f, UInt<8>("h0e3")) @[ifu_bp_ctl.scala 418:77] + node _T_2567 = bits(_T_2566, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2568 = eq(btb_rd_addr_f, UInt<8>("h0e4")) @[ifu_bp_ctl.scala 418:77] + node _T_2569 = bits(_T_2568, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2570 = eq(btb_rd_addr_f, UInt<8>("h0e5")) @[ifu_bp_ctl.scala 418:77] + node _T_2571 = bits(_T_2570, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2572 = eq(btb_rd_addr_f, UInt<8>("h0e6")) @[ifu_bp_ctl.scala 418:77] + node _T_2573 = bits(_T_2572, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2574 = eq(btb_rd_addr_f, UInt<8>("h0e7")) @[ifu_bp_ctl.scala 418:77] + node _T_2575 = bits(_T_2574, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2576 = eq(btb_rd_addr_f, UInt<8>("h0e8")) @[ifu_bp_ctl.scala 418:77] + node _T_2577 = bits(_T_2576, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2578 = eq(btb_rd_addr_f, UInt<8>("h0e9")) @[ifu_bp_ctl.scala 418:77] + node _T_2579 = bits(_T_2578, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2580 = eq(btb_rd_addr_f, UInt<8>("h0ea")) @[ifu_bp_ctl.scala 418:77] + node _T_2581 = bits(_T_2580, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2582 = eq(btb_rd_addr_f, UInt<8>("h0eb")) @[ifu_bp_ctl.scala 418:77] + node _T_2583 = bits(_T_2582, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2584 = eq(btb_rd_addr_f, UInt<8>("h0ec")) @[ifu_bp_ctl.scala 418:77] + node _T_2585 = bits(_T_2584, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2586 = eq(btb_rd_addr_f, UInt<8>("h0ed")) @[ifu_bp_ctl.scala 418:77] + node _T_2587 = bits(_T_2586, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2588 = eq(btb_rd_addr_f, UInt<8>("h0ee")) @[ifu_bp_ctl.scala 418:77] + node _T_2589 = bits(_T_2588, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2590 = eq(btb_rd_addr_f, UInt<8>("h0ef")) @[ifu_bp_ctl.scala 418:77] + node _T_2591 = bits(_T_2590, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2592 = eq(btb_rd_addr_f, UInt<8>("h0f0")) @[ifu_bp_ctl.scala 418:77] + node _T_2593 = bits(_T_2592, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2594 = eq(btb_rd_addr_f, UInt<8>("h0f1")) @[ifu_bp_ctl.scala 418:77] + node _T_2595 = bits(_T_2594, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2596 = eq(btb_rd_addr_f, UInt<8>("h0f2")) @[ifu_bp_ctl.scala 418:77] + node _T_2597 = bits(_T_2596, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2598 = eq(btb_rd_addr_f, UInt<8>("h0f3")) @[ifu_bp_ctl.scala 418:77] + node _T_2599 = bits(_T_2598, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2600 = eq(btb_rd_addr_f, UInt<8>("h0f4")) @[ifu_bp_ctl.scala 418:77] + node _T_2601 = bits(_T_2600, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2602 = eq(btb_rd_addr_f, UInt<8>("h0f5")) @[ifu_bp_ctl.scala 418:77] + node _T_2603 = bits(_T_2602, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2604 = eq(btb_rd_addr_f, UInt<8>("h0f6")) @[ifu_bp_ctl.scala 418:77] + node _T_2605 = bits(_T_2604, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2606 = eq(btb_rd_addr_f, UInt<8>("h0f7")) @[ifu_bp_ctl.scala 418:77] + node _T_2607 = bits(_T_2606, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2608 = eq(btb_rd_addr_f, UInt<8>("h0f8")) @[ifu_bp_ctl.scala 418:77] + node _T_2609 = bits(_T_2608, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2610 = eq(btb_rd_addr_f, UInt<8>("h0f9")) @[ifu_bp_ctl.scala 418:77] + node _T_2611 = bits(_T_2610, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2612 = eq(btb_rd_addr_f, UInt<8>("h0fa")) @[ifu_bp_ctl.scala 418:77] + node _T_2613 = bits(_T_2612, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2614 = eq(btb_rd_addr_f, UInt<8>("h0fb")) @[ifu_bp_ctl.scala 418:77] + node _T_2615 = bits(_T_2614, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2616 = eq(btb_rd_addr_f, UInt<8>("h0fc")) @[ifu_bp_ctl.scala 418:77] + node _T_2617 = bits(_T_2616, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2618 = eq(btb_rd_addr_f, UInt<8>("h0fd")) @[ifu_bp_ctl.scala 418:77] + node _T_2619 = bits(_T_2618, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2620 = eq(btb_rd_addr_f, UInt<8>("h0fe")) @[ifu_bp_ctl.scala 418:77] + node _T_2621 = bits(_T_2620, 0, 0) @[ifu_bp_ctl.scala 418:85] + node _T_2622 = eq(btb_rd_addr_f, UInt<8>("h0ff")) @[ifu_bp_ctl.scala 418:77] + node _T_2623 = bits(_T_2622, 0, 0) @[ifu_bp_ctl.scala 418:85] node _T_2624 = mux(_T_2113, btb_bank0_rd_data_way0_out_0, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2625 = mux(_T_2115, btb_bank0_rd_data_way0_out_1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2626 = mux(_T_2117, btb_bank0_rd_data_way0_out_2, UInt<1>("h00")) @[Mux.scala 27:72] @@ -36619,519 +36619,519 @@ circuit quasar_wrapper : node _T_3134 = or(_T_3133, _T_2879) @[Mux.scala 27:72] wire _T_3135 : UInt @[Mux.scala 27:72] _T_3135 <= _T_3134 @[Mux.scala 27:72] - btb_bank0_rd_data_way0_f <= _T_3135 @[ifu_bp_ctl.scala 417:28] - node _T_3136 = eq(btb_rd_addr_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 418:77] - node _T_3137 = bits(_T_3136, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3138 = eq(btb_rd_addr_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 418:77] - node _T_3139 = bits(_T_3138, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3140 = eq(btb_rd_addr_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 418:77] - node _T_3141 = bits(_T_3140, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3142 = eq(btb_rd_addr_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 418:77] - node _T_3143 = bits(_T_3142, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3144 = eq(btb_rd_addr_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 418:77] - node _T_3145 = bits(_T_3144, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3146 = eq(btb_rd_addr_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 418:77] - node _T_3147 = bits(_T_3146, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3148 = eq(btb_rd_addr_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 418:77] - node _T_3149 = bits(_T_3148, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3150 = eq(btb_rd_addr_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 418:77] - node _T_3151 = bits(_T_3150, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3152 = eq(btb_rd_addr_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 418:77] - node _T_3153 = bits(_T_3152, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3154 = eq(btb_rd_addr_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 418:77] - node _T_3155 = bits(_T_3154, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3156 = eq(btb_rd_addr_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 418:77] - node _T_3157 = bits(_T_3156, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3158 = eq(btb_rd_addr_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 418:77] - node _T_3159 = bits(_T_3158, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3160 = eq(btb_rd_addr_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 418:77] - node _T_3161 = bits(_T_3160, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3162 = eq(btb_rd_addr_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 418:77] - node _T_3163 = bits(_T_3162, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3164 = eq(btb_rd_addr_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 418:77] - node _T_3165 = bits(_T_3164, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3166 = eq(btb_rd_addr_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 418:77] - node _T_3167 = bits(_T_3166, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3168 = eq(btb_rd_addr_f, UInt<5>("h010")) @[ifu_bp_ctl.scala 418:77] - node _T_3169 = bits(_T_3168, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3170 = eq(btb_rd_addr_f, UInt<5>("h011")) @[ifu_bp_ctl.scala 418:77] - node _T_3171 = bits(_T_3170, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3172 = eq(btb_rd_addr_f, UInt<5>("h012")) @[ifu_bp_ctl.scala 418:77] - node _T_3173 = bits(_T_3172, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3174 = eq(btb_rd_addr_f, UInt<5>("h013")) @[ifu_bp_ctl.scala 418:77] - node _T_3175 = bits(_T_3174, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3176 = eq(btb_rd_addr_f, UInt<5>("h014")) @[ifu_bp_ctl.scala 418:77] - node _T_3177 = bits(_T_3176, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3178 = eq(btb_rd_addr_f, UInt<5>("h015")) @[ifu_bp_ctl.scala 418:77] - node _T_3179 = bits(_T_3178, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3180 = eq(btb_rd_addr_f, UInt<5>("h016")) @[ifu_bp_ctl.scala 418:77] - node _T_3181 = bits(_T_3180, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3182 = eq(btb_rd_addr_f, UInt<5>("h017")) @[ifu_bp_ctl.scala 418:77] - node _T_3183 = bits(_T_3182, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3184 = eq(btb_rd_addr_f, UInt<5>("h018")) @[ifu_bp_ctl.scala 418:77] - node _T_3185 = bits(_T_3184, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3186 = eq(btb_rd_addr_f, UInt<5>("h019")) @[ifu_bp_ctl.scala 418:77] - node _T_3187 = bits(_T_3186, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3188 = eq(btb_rd_addr_f, UInt<5>("h01a")) @[ifu_bp_ctl.scala 418:77] - node _T_3189 = bits(_T_3188, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3190 = eq(btb_rd_addr_f, UInt<5>("h01b")) @[ifu_bp_ctl.scala 418:77] - node _T_3191 = bits(_T_3190, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3192 = eq(btb_rd_addr_f, UInt<5>("h01c")) @[ifu_bp_ctl.scala 418:77] - node _T_3193 = bits(_T_3192, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3194 = eq(btb_rd_addr_f, UInt<5>("h01d")) @[ifu_bp_ctl.scala 418:77] - node _T_3195 = bits(_T_3194, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3196 = eq(btb_rd_addr_f, UInt<5>("h01e")) @[ifu_bp_ctl.scala 418:77] - node _T_3197 = bits(_T_3196, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3198 = eq(btb_rd_addr_f, UInt<5>("h01f")) @[ifu_bp_ctl.scala 418:77] - node _T_3199 = bits(_T_3198, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3200 = eq(btb_rd_addr_f, UInt<6>("h020")) @[ifu_bp_ctl.scala 418:77] - node _T_3201 = bits(_T_3200, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3202 = eq(btb_rd_addr_f, UInt<6>("h021")) @[ifu_bp_ctl.scala 418:77] - node _T_3203 = bits(_T_3202, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3204 = eq(btb_rd_addr_f, UInt<6>("h022")) @[ifu_bp_ctl.scala 418:77] - node _T_3205 = bits(_T_3204, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3206 = eq(btb_rd_addr_f, UInt<6>("h023")) @[ifu_bp_ctl.scala 418:77] - node _T_3207 = bits(_T_3206, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3208 = eq(btb_rd_addr_f, UInt<6>("h024")) @[ifu_bp_ctl.scala 418:77] - node _T_3209 = bits(_T_3208, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3210 = eq(btb_rd_addr_f, UInt<6>("h025")) @[ifu_bp_ctl.scala 418:77] - node _T_3211 = bits(_T_3210, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3212 = eq(btb_rd_addr_f, UInt<6>("h026")) @[ifu_bp_ctl.scala 418:77] - node _T_3213 = bits(_T_3212, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3214 = eq(btb_rd_addr_f, UInt<6>("h027")) @[ifu_bp_ctl.scala 418:77] - node _T_3215 = bits(_T_3214, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3216 = eq(btb_rd_addr_f, UInt<6>("h028")) @[ifu_bp_ctl.scala 418:77] - node _T_3217 = bits(_T_3216, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3218 = eq(btb_rd_addr_f, UInt<6>("h029")) @[ifu_bp_ctl.scala 418:77] - node _T_3219 = bits(_T_3218, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3220 = eq(btb_rd_addr_f, UInt<6>("h02a")) @[ifu_bp_ctl.scala 418:77] - node _T_3221 = bits(_T_3220, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3222 = eq(btb_rd_addr_f, UInt<6>("h02b")) @[ifu_bp_ctl.scala 418:77] - node _T_3223 = bits(_T_3222, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3224 = eq(btb_rd_addr_f, UInt<6>("h02c")) @[ifu_bp_ctl.scala 418:77] - node _T_3225 = bits(_T_3224, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3226 = eq(btb_rd_addr_f, UInt<6>("h02d")) @[ifu_bp_ctl.scala 418:77] - node _T_3227 = bits(_T_3226, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3228 = eq(btb_rd_addr_f, UInt<6>("h02e")) @[ifu_bp_ctl.scala 418:77] - node _T_3229 = bits(_T_3228, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3230 = eq(btb_rd_addr_f, UInt<6>("h02f")) @[ifu_bp_ctl.scala 418:77] - node _T_3231 = bits(_T_3230, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3232 = eq(btb_rd_addr_f, UInt<6>("h030")) @[ifu_bp_ctl.scala 418:77] - node _T_3233 = bits(_T_3232, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3234 = eq(btb_rd_addr_f, UInt<6>("h031")) @[ifu_bp_ctl.scala 418:77] - node _T_3235 = bits(_T_3234, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3236 = eq(btb_rd_addr_f, UInt<6>("h032")) @[ifu_bp_ctl.scala 418:77] - node _T_3237 = bits(_T_3236, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3238 = eq(btb_rd_addr_f, UInt<6>("h033")) @[ifu_bp_ctl.scala 418:77] - node _T_3239 = bits(_T_3238, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3240 = eq(btb_rd_addr_f, UInt<6>("h034")) @[ifu_bp_ctl.scala 418:77] - node _T_3241 = bits(_T_3240, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3242 = eq(btb_rd_addr_f, UInt<6>("h035")) @[ifu_bp_ctl.scala 418:77] - node _T_3243 = bits(_T_3242, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3244 = eq(btb_rd_addr_f, UInt<6>("h036")) @[ifu_bp_ctl.scala 418:77] - node _T_3245 = bits(_T_3244, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3246 = eq(btb_rd_addr_f, UInt<6>("h037")) @[ifu_bp_ctl.scala 418:77] - node _T_3247 = bits(_T_3246, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3248 = eq(btb_rd_addr_f, UInt<6>("h038")) @[ifu_bp_ctl.scala 418:77] - node _T_3249 = bits(_T_3248, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3250 = eq(btb_rd_addr_f, UInt<6>("h039")) @[ifu_bp_ctl.scala 418:77] - node _T_3251 = bits(_T_3250, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3252 = eq(btb_rd_addr_f, UInt<6>("h03a")) @[ifu_bp_ctl.scala 418:77] - node _T_3253 = bits(_T_3252, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3254 = eq(btb_rd_addr_f, UInt<6>("h03b")) @[ifu_bp_ctl.scala 418:77] - node _T_3255 = bits(_T_3254, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3256 = eq(btb_rd_addr_f, UInt<6>("h03c")) @[ifu_bp_ctl.scala 418:77] - node _T_3257 = bits(_T_3256, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3258 = eq(btb_rd_addr_f, UInt<6>("h03d")) @[ifu_bp_ctl.scala 418:77] - node _T_3259 = bits(_T_3258, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3260 = eq(btb_rd_addr_f, UInt<6>("h03e")) @[ifu_bp_ctl.scala 418:77] - node _T_3261 = bits(_T_3260, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3262 = eq(btb_rd_addr_f, UInt<6>("h03f")) @[ifu_bp_ctl.scala 418:77] - node _T_3263 = bits(_T_3262, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3264 = eq(btb_rd_addr_f, UInt<7>("h040")) @[ifu_bp_ctl.scala 418:77] - node _T_3265 = bits(_T_3264, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3266 = eq(btb_rd_addr_f, UInt<7>("h041")) @[ifu_bp_ctl.scala 418:77] - node _T_3267 = bits(_T_3266, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3268 = eq(btb_rd_addr_f, UInt<7>("h042")) @[ifu_bp_ctl.scala 418:77] - node _T_3269 = bits(_T_3268, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3270 = eq(btb_rd_addr_f, UInt<7>("h043")) @[ifu_bp_ctl.scala 418:77] - node _T_3271 = bits(_T_3270, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3272 = eq(btb_rd_addr_f, UInt<7>("h044")) @[ifu_bp_ctl.scala 418:77] - node _T_3273 = bits(_T_3272, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3274 = eq(btb_rd_addr_f, UInt<7>("h045")) @[ifu_bp_ctl.scala 418:77] - node _T_3275 = bits(_T_3274, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3276 = eq(btb_rd_addr_f, UInt<7>("h046")) @[ifu_bp_ctl.scala 418:77] - node _T_3277 = bits(_T_3276, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3278 = eq(btb_rd_addr_f, UInt<7>("h047")) @[ifu_bp_ctl.scala 418:77] - node _T_3279 = bits(_T_3278, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3280 = eq(btb_rd_addr_f, UInt<7>("h048")) @[ifu_bp_ctl.scala 418:77] - node _T_3281 = bits(_T_3280, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3282 = eq(btb_rd_addr_f, UInt<7>("h049")) @[ifu_bp_ctl.scala 418:77] - node _T_3283 = bits(_T_3282, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3284 = eq(btb_rd_addr_f, UInt<7>("h04a")) @[ifu_bp_ctl.scala 418:77] - node _T_3285 = bits(_T_3284, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3286 = eq(btb_rd_addr_f, UInt<7>("h04b")) @[ifu_bp_ctl.scala 418:77] - node _T_3287 = bits(_T_3286, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3288 = eq(btb_rd_addr_f, UInt<7>("h04c")) @[ifu_bp_ctl.scala 418:77] - node _T_3289 = bits(_T_3288, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3290 = eq(btb_rd_addr_f, UInt<7>("h04d")) @[ifu_bp_ctl.scala 418:77] - node _T_3291 = bits(_T_3290, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3292 = eq(btb_rd_addr_f, UInt<7>("h04e")) @[ifu_bp_ctl.scala 418:77] - node _T_3293 = bits(_T_3292, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3294 = eq(btb_rd_addr_f, UInt<7>("h04f")) @[ifu_bp_ctl.scala 418:77] - node _T_3295 = bits(_T_3294, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3296 = eq(btb_rd_addr_f, UInt<7>("h050")) @[ifu_bp_ctl.scala 418:77] - node _T_3297 = bits(_T_3296, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3298 = eq(btb_rd_addr_f, UInt<7>("h051")) @[ifu_bp_ctl.scala 418:77] - node _T_3299 = bits(_T_3298, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3300 = eq(btb_rd_addr_f, UInt<7>("h052")) @[ifu_bp_ctl.scala 418:77] - node _T_3301 = bits(_T_3300, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3302 = eq(btb_rd_addr_f, UInt<7>("h053")) @[ifu_bp_ctl.scala 418:77] - node _T_3303 = bits(_T_3302, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3304 = eq(btb_rd_addr_f, UInt<7>("h054")) @[ifu_bp_ctl.scala 418:77] - node _T_3305 = bits(_T_3304, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3306 = eq(btb_rd_addr_f, UInt<7>("h055")) @[ifu_bp_ctl.scala 418:77] - node _T_3307 = bits(_T_3306, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3308 = eq(btb_rd_addr_f, UInt<7>("h056")) @[ifu_bp_ctl.scala 418:77] - node _T_3309 = bits(_T_3308, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3310 = eq(btb_rd_addr_f, UInt<7>("h057")) @[ifu_bp_ctl.scala 418:77] - node _T_3311 = bits(_T_3310, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3312 = eq(btb_rd_addr_f, UInt<7>("h058")) @[ifu_bp_ctl.scala 418:77] - node _T_3313 = bits(_T_3312, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3314 = eq(btb_rd_addr_f, UInt<7>("h059")) @[ifu_bp_ctl.scala 418:77] - node _T_3315 = bits(_T_3314, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3316 = eq(btb_rd_addr_f, UInt<7>("h05a")) @[ifu_bp_ctl.scala 418:77] - node _T_3317 = bits(_T_3316, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3318 = eq(btb_rd_addr_f, UInt<7>("h05b")) @[ifu_bp_ctl.scala 418:77] - node _T_3319 = bits(_T_3318, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3320 = eq(btb_rd_addr_f, UInt<7>("h05c")) @[ifu_bp_ctl.scala 418:77] - node _T_3321 = bits(_T_3320, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3322 = eq(btb_rd_addr_f, UInt<7>("h05d")) @[ifu_bp_ctl.scala 418:77] - node _T_3323 = bits(_T_3322, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3324 = eq(btb_rd_addr_f, UInt<7>("h05e")) @[ifu_bp_ctl.scala 418:77] - node _T_3325 = bits(_T_3324, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3326 = eq(btb_rd_addr_f, UInt<7>("h05f")) @[ifu_bp_ctl.scala 418:77] - node _T_3327 = bits(_T_3326, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3328 = eq(btb_rd_addr_f, UInt<7>("h060")) @[ifu_bp_ctl.scala 418:77] - node _T_3329 = bits(_T_3328, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3330 = eq(btb_rd_addr_f, UInt<7>("h061")) @[ifu_bp_ctl.scala 418:77] - node _T_3331 = bits(_T_3330, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3332 = eq(btb_rd_addr_f, UInt<7>("h062")) @[ifu_bp_ctl.scala 418:77] - node _T_3333 = bits(_T_3332, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3334 = eq(btb_rd_addr_f, UInt<7>("h063")) @[ifu_bp_ctl.scala 418:77] - node _T_3335 = bits(_T_3334, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3336 = eq(btb_rd_addr_f, UInt<7>("h064")) @[ifu_bp_ctl.scala 418:77] - node _T_3337 = bits(_T_3336, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3338 = eq(btb_rd_addr_f, UInt<7>("h065")) @[ifu_bp_ctl.scala 418:77] - node _T_3339 = bits(_T_3338, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3340 = eq(btb_rd_addr_f, UInt<7>("h066")) @[ifu_bp_ctl.scala 418:77] - node _T_3341 = bits(_T_3340, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3342 = eq(btb_rd_addr_f, UInt<7>("h067")) @[ifu_bp_ctl.scala 418:77] - node _T_3343 = bits(_T_3342, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3344 = eq(btb_rd_addr_f, UInt<7>("h068")) @[ifu_bp_ctl.scala 418:77] - node _T_3345 = bits(_T_3344, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3346 = eq(btb_rd_addr_f, UInt<7>("h069")) @[ifu_bp_ctl.scala 418:77] - node _T_3347 = bits(_T_3346, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3348 = eq(btb_rd_addr_f, UInt<7>("h06a")) @[ifu_bp_ctl.scala 418:77] - node _T_3349 = bits(_T_3348, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3350 = eq(btb_rd_addr_f, UInt<7>("h06b")) @[ifu_bp_ctl.scala 418:77] - node _T_3351 = bits(_T_3350, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3352 = eq(btb_rd_addr_f, UInt<7>("h06c")) @[ifu_bp_ctl.scala 418:77] - node _T_3353 = bits(_T_3352, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3354 = eq(btb_rd_addr_f, UInt<7>("h06d")) @[ifu_bp_ctl.scala 418:77] - node _T_3355 = bits(_T_3354, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3356 = eq(btb_rd_addr_f, UInt<7>("h06e")) @[ifu_bp_ctl.scala 418:77] - node _T_3357 = bits(_T_3356, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3358 = eq(btb_rd_addr_f, UInt<7>("h06f")) @[ifu_bp_ctl.scala 418:77] - node _T_3359 = bits(_T_3358, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3360 = eq(btb_rd_addr_f, UInt<7>("h070")) @[ifu_bp_ctl.scala 418:77] - node _T_3361 = bits(_T_3360, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3362 = eq(btb_rd_addr_f, UInt<7>("h071")) @[ifu_bp_ctl.scala 418:77] - node _T_3363 = bits(_T_3362, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3364 = eq(btb_rd_addr_f, UInt<7>("h072")) @[ifu_bp_ctl.scala 418:77] - node _T_3365 = bits(_T_3364, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3366 = eq(btb_rd_addr_f, UInt<7>("h073")) @[ifu_bp_ctl.scala 418:77] - node _T_3367 = bits(_T_3366, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3368 = eq(btb_rd_addr_f, UInt<7>("h074")) @[ifu_bp_ctl.scala 418:77] - node _T_3369 = bits(_T_3368, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3370 = eq(btb_rd_addr_f, UInt<7>("h075")) @[ifu_bp_ctl.scala 418:77] - node _T_3371 = bits(_T_3370, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3372 = eq(btb_rd_addr_f, UInt<7>("h076")) @[ifu_bp_ctl.scala 418:77] - node _T_3373 = bits(_T_3372, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3374 = eq(btb_rd_addr_f, UInt<7>("h077")) @[ifu_bp_ctl.scala 418:77] - node _T_3375 = bits(_T_3374, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3376 = eq(btb_rd_addr_f, UInt<7>("h078")) @[ifu_bp_ctl.scala 418:77] - node _T_3377 = bits(_T_3376, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3378 = eq(btb_rd_addr_f, UInt<7>("h079")) @[ifu_bp_ctl.scala 418:77] - node _T_3379 = bits(_T_3378, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3380 = eq(btb_rd_addr_f, UInt<7>("h07a")) @[ifu_bp_ctl.scala 418:77] - node _T_3381 = bits(_T_3380, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3382 = eq(btb_rd_addr_f, UInt<7>("h07b")) @[ifu_bp_ctl.scala 418:77] - node _T_3383 = bits(_T_3382, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3384 = eq(btb_rd_addr_f, UInt<7>("h07c")) @[ifu_bp_ctl.scala 418:77] - node _T_3385 = bits(_T_3384, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3386 = eq(btb_rd_addr_f, UInt<7>("h07d")) @[ifu_bp_ctl.scala 418:77] - node _T_3387 = bits(_T_3386, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3388 = eq(btb_rd_addr_f, UInt<7>("h07e")) @[ifu_bp_ctl.scala 418:77] - node _T_3389 = bits(_T_3388, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3390 = eq(btb_rd_addr_f, UInt<7>("h07f")) @[ifu_bp_ctl.scala 418:77] - node _T_3391 = bits(_T_3390, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3392 = eq(btb_rd_addr_f, UInt<8>("h080")) @[ifu_bp_ctl.scala 418:77] - node _T_3393 = bits(_T_3392, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3394 = eq(btb_rd_addr_f, UInt<8>("h081")) @[ifu_bp_ctl.scala 418:77] - node _T_3395 = bits(_T_3394, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3396 = eq(btb_rd_addr_f, UInt<8>("h082")) @[ifu_bp_ctl.scala 418:77] - node _T_3397 = bits(_T_3396, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3398 = eq(btb_rd_addr_f, UInt<8>("h083")) @[ifu_bp_ctl.scala 418:77] - node _T_3399 = bits(_T_3398, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3400 = eq(btb_rd_addr_f, UInt<8>("h084")) @[ifu_bp_ctl.scala 418:77] - node _T_3401 = bits(_T_3400, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3402 = eq(btb_rd_addr_f, UInt<8>("h085")) @[ifu_bp_ctl.scala 418:77] - node _T_3403 = bits(_T_3402, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3404 = eq(btb_rd_addr_f, UInt<8>("h086")) @[ifu_bp_ctl.scala 418:77] - node _T_3405 = bits(_T_3404, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3406 = eq(btb_rd_addr_f, UInt<8>("h087")) @[ifu_bp_ctl.scala 418:77] - node _T_3407 = bits(_T_3406, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3408 = eq(btb_rd_addr_f, UInt<8>("h088")) @[ifu_bp_ctl.scala 418:77] - node _T_3409 = bits(_T_3408, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3410 = eq(btb_rd_addr_f, UInt<8>("h089")) @[ifu_bp_ctl.scala 418:77] - node _T_3411 = bits(_T_3410, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3412 = eq(btb_rd_addr_f, UInt<8>("h08a")) @[ifu_bp_ctl.scala 418:77] - node _T_3413 = bits(_T_3412, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3414 = eq(btb_rd_addr_f, UInt<8>("h08b")) @[ifu_bp_ctl.scala 418:77] - node _T_3415 = bits(_T_3414, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3416 = eq(btb_rd_addr_f, UInt<8>("h08c")) @[ifu_bp_ctl.scala 418:77] - node _T_3417 = bits(_T_3416, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3418 = eq(btb_rd_addr_f, UInt<8>("h08d")) @[ifu_bp_ctl.scala 418:77] - node _T_3419 = bits(_T_3418, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3420 = eq(btb_rd_addr_f, UInt<8>("h08e")) @[ifu_bp_ctl.scala 418:77] - node _T_3421 = bits(_T_3420, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3422 = eq(btb_rd_addr_f, UInt<8>("h08f")) @[ifu_bp_ctl.scala 418:77] - node _T_3423 = bits(_T_3422, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3424 = eq(btb_rd_addr_f, UInt<8>("h090")) @[ifu_bp_ctl.scala 418:77] - node _T_3425 = bits(_T_3424, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3426 = eq(btb_rd_addr_f, UInt<8>("h091")) @[ifu_bp_ctl.scala 418:77] - node _T_3427 = bits(_T_3426, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3428 = eq(btb_rd_addr_f, UInt<8>("h092")) @[ifu_bp_ctl.scala 418:77] - node _T_3429 = bits(_T_3428, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3430 = eq(btb_rd_addr_f, UInt<8>("h093")) @[ifu_bp_ctl.scala 418:77] - node _T_3431 = bits(_T_3430, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3432 = eq(btb_rd_addr_f, UInt<8>("h094")) @[ifu_bp_ctl.scala 418:77] - node _T_3433 = bits(_T_3432, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3434 = eq(btb_rd_addr_f, UInt<8>("h095")) @[ifu_bp_ctl.scala 418:77] - node _T_3435 = bits(_T_3434, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3436 = eq(btb_rd_addr_f, UInt<8>("h096")) @[ifu_bp_ctl.scala 418:77] - node _T_3437 = bits(_T_3436, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3438 = eq(btb_rd_addr_f, UInt<8>("h097")) @[ifu_bp_ctl.scala 418:77] - node _T_3439 = bits(_T_3438, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3440 = eq(btb_rd_addr_f, UInt<8>("h098")) @[ifu_bp_ctl.scala 418:77] - node _T_3441 = bits(_T_3440, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3442 = eq(btb_rd_addr_f, UInt<8>("h099")) @[ifu_bp_ctl.scala 418:77] - node _T_3443 = bits(_T_3442, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3444 = eq(btb_rd_addr_f, UInt<8>("h09a")) @[ifu_bp_ctl.scala 418:77] - node _T_3445 = bits(_T_3444, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3446 = eq(btb_rd_addr_f, UInt<8>("h09b")) @[ifu_bp_ctl.scala 418:77] - node _T_3447 = bits(_T_3446, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3448 = eq(btb_rd_addr_f, UInt<8>("h09c")) @[ifu_bp_ctl.scala 418:77] - node _T_3449 = bits(_T_3448, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3450 = eq(btb_rd_addr_f, UInt<8>("h09d")) @[ifu_bp_ctl.scala 418:77] - node _T_3451 = bits(_T_3450, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3452 = eq(btb_rd_addr_f, UInt<8>("h09e")) @[ifu_bp_ctl.scala 418:77] - node _T_3453 = bits(_T_3452, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3454 = eq(btb_rd_addr_f, UInt<8>("h09f")) @[ifu_bp_ctl.scala 418:77] - node _T_3455 = bits(_T_3454, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3456 = eq(btb_rd_addr_f, UInt<8>("h0a0")) @[ifu_bp_ctl.scala 418:77] - node _T_3457 = bits(_T_3456, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3458 = eq(btb_rd_addr_f, UInt<8>("h0a1")) @[ifu_bp_ctl.scala 418:77] - node _T_3459 = bits(_T_3458, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3460 = eq(btb_rd_addr_f, UInt<8>("h0a2")) @[ifu_bp_ctl.scala 418:77] - node _T_3461 = bits(_T_3460, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3462 = eq(btb_rd_addr_f, UInt<8>("h0a3")) @[ifu_bp_ctl.scala 418:77] - node _T_3463 = bits(_T_3462, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3464 = eq(btb_rd_addr_f, UInt<8>("h0a4")) @[ifu_bp_ctl.scala 418:77] - node _T_3465 = bits(_T_3464, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3466 = eq(btb_rd_addr_f, UInt<8>("h0a5")) @[ifu_bp_ctl.scala 418:77] - node _T_3467 = bits(_T_3466, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3468 = eq(btb_rd_addr_f, UInt<8>("h0a6")) @[ifu_bp_ctl.scala 418:77] - node _T_3469 = bits(_T_3468, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3470 = eq(btb_rd_addr_f, UInt<8>("h0a7")) @[ifu_bp_ctl.scala 418:77] - node _T_3471 = bits(_T_3470, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3472 = eq(btb_rd_addr_f, UInt<8>("h0a8")) @[ifu_bp_ctl.scala 418:77] - node _T_3473 = bits(_T_3472, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3474 = eq(btb_rd_addr_f, UInt<8>("h0a9")) @[ifu_bp_ctl.scala 418:77] - node _T_3475 = bits(_T_3474, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3476 = eq(btb_rd_addr_f, UInt<8>("h0aa")) @[ifu_bp_ctl.scala 418:77] - node _T_3477 = bits(_T_3476, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3478 = eq(btb_rd_addr_f, UInt<8>("h0ab")) @[ifu_bp_ctl.scala 418:77] - node _T_3479 = bits(_T_3478, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3480 = eq(btb_rd_addr_f, UInt<8>("h0ac")) @[ifu_bp_ctl.scala 418:77] - node _T_3481 = bits(_T_3480, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3482 = eq(btb_rd_addr_f, UInt<8>("h0ad")) @[ifu_bp_ctl.scala 418:77] - node _T_3483 = bits(_T_3482, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3484 = eq(btb_rd_addr_f, UInt<8>("h0ae")) @[ifu_bp_ctl.scala 418:77] - node _T_3485 = bits(_T_3484, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3486 = eq(btb_rd_addr_f, UInt<8>("h0af")) @[ifu_bp_ctl.scala 418:77] - node _T_3487 = bits(_T_3486, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3488 = eq(btb_rd_addr_f, UInt<8>("h0b0")) @[ifu_bp_ctl.scala 418:77] - node _T_3489 = bits(_T_3488, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3490 = eq(btb_rd_addr_f, UInt<8>("h0b1")) @[ifu_bp_ctl.scala 418:77] - node _T_3491 = bits(_T_3490, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3492 = eq(btb_rd_addr_f, UInt<8>("h0b2")) @[ifu_bp_ctl.scala 418:77] - node _T_3493 = bits(_T_3492, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3494 = eq(btb_rd_addr_f, UInt<8>("h0b3")) @[ifu_bp_ctl.scala 418:77] - node _T_3495 = bits(_T_3494, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3496 = eq(btb_rd_addr_f, UInt<8>("h0b4")) @[ifu_bp_ctl.scala 418:77] - node _T_3497 = bits(_T_3496, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3498 = eq(btb_rd_addr_f, UInt<8>("h0b5")) @[ifu_bp_ctl.scala 418:77] - node _T_3499 = bits(_T_3498, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3500 = eq(btb_rd_addr_f, UInt<8>("h0b6")) @[ifu_bp_ctl.scala 418:77] - node _T_3501 = bits(_T_3500, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3502 = eq(btb_rd_addr_f, UInt<8>("h0b7")) @[ifu_bp_ctl.scala 418:77] - node _T_3503 = bits(_T_3502, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3504 = eq(btb_rd_addr_f, UInt<8>("h0b8")) @[ifu_bp_ctl.scala 418:77] - node _T_3505 = bits(_T_3504, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3506 = eq(btb_rd_addr_f, UInt<8>("h0b9")) @[ifu_bp_ctl.scala 418:77] - node _T_3507 = bits(_T_3506, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3508 = eq(btb_rd_addr_f, UInt<8>("h0ba")) @[ifu_bp_ctl.scala 418:77] - node _T_3509 = bits(_T_3508, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3510 = eq(btb_rd_addr_f, UInt<8>("h0bb")) @[ifu_bp_ctl.scala 418:77] - node _T_3511 = bits(_T_3510, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3512 = eq(btb_rd_addr_f, UInt<8>("h0bc")) @[ifu_bp_ctl.scala 418:77] - node _T_3513 = bits(_T_3512, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3514 = eq(btb_rd_addr_f, UInt<8>("h0bd")) @[ifu_bp_ctl.scala 418:77] - node _T_3515 = bits(_T_3514, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3516 = eq(btb_rd_addr_f, UInt<8>("h0be")) @[ifu_bp_ctl.scala 418:77] - node _T_3517 = bits(_T_3516, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3518 = eq(btb_rd_addr_f, UInt<8>("h0bf")) @[ifu_bp_ctl.scala 418:77] - node _T_3519 = bits(_T_3518, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3520 = eq(btb_rd_addr_f, UInt<8>("h0c0")) @[ifu_bp_ctl.scala 418:77] - node _T_3521 = bits(_T_3520, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3522 = eq(btb_rd_addr_f, UInt<8>("h0c1")) @[ifu_bp_ctl.scala 418:77] - node _T_3523 = bits(_T_3522, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3524 = eq(btb_rd_addr_f, UInt<8>("h0c2")) @[ifu_bp_ctl.scala 418:77] - node _T_3525 = bits(_T_3524, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3526 = eq(btb_rd_addr_f, UInt<8>("h0c3")) @[ifu_bp_ctl.scala 418:77] - node _T_3527 = bits(_T_3526, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3528 = eq(btb_rd_addr_f, UInt<8>("h0c4")) @[ifu_bp_ctl.scala 418:77] - node _T_3529 = bits(_T_3528, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3530 = eq(btb_rd_addr_f, UInt<8>("h0c5")) @[ifu_bp_ctl.scala 418:77] - node _T_3531 = bits(_T_3530, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3532 = eq(btb_rd_addr_f, UInt<8>("h0c6")) @[ifu_bp_ctl.scala 418:77] - node _T_3533 = bits(_T_3532, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3534 = eq(btb_rd_addr_f, UInt<8>("h0c7")) @[ifu_bp_ctl.scala 418:77] - node _T_3535 = bits(_T_3534, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3536 = eq(btb_rd_addr_f, UInt<8>("h0c8")) @[ifu_bp_ctl.scala 418:77] - node _T_3537 = bits(_T_3536, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3538 = eq(btb_rd_addr_f, UInt<8>("h0c9")) @[ifu_bp_ctl.scala 418:77] - node _T_3539 = bits(_T_3538, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3540 = eq(btb_rd_addr_f, UInt<8>("h0ca")) @[ifu_bp_ctl.scala 418:77] - node _T_3541 = bits(_T_3540, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3542 = eq(btb_rd_addr_f, UInt<8>("h0cb")) @[ifu_bp_ctl.scala 418:77] - node _T_3543 = bits(_T_3542, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3544 = eq(btb_rd_addr_f, UInt<8>("h0cc")) @[ifu_bp_ctl.scala 418:77] - node _T_3545 = bits(_T_3544, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3546 = eq(btb_rd_addr_f, UInt<8>("h0cd")) @[ifu_bp_ctl.scala 418:77] - node _T_3547 = bits(_T_3546, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3548 = eq(btb_rd_addr_f, UInt<8>("h0ce")) @[ifu_bp_ctl.scala 418:77] - node _T_3549 = bits(_T_3548, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3550 = eq(btb_rd_addr_f, UInt<8>("h0cf")) @[ifu_bp_ctl.scala 418:77] - node _T_3551 = bits(_T_3550, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3552 = eq(btb_rd_addr_f, UInt<8>("h0d0")) @[ifu_bp_ctl.scala 418:77] - node _T_3553 = bits(_T_3552, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3554 = eq(btb_rd_addr_f, UInt<8>("h0d1")) @[ifu_bp_ctl.scala 418:77] - node _T_3555 = bits(_T_3554, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3556 = eq(btb_rd_addr_f, UInt<8>("h0d2")) @[ifu_bp_ctl.scala 418:77] - node _T_3557 = bits(_T_3556, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3558 = eq(btb_rd_addr_f, UInt<8>("h0d3")) @[ifu_bp_ctl.scala 418:77] - node _T_3559 = bits(_T_3558, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3560 = eq(btb_rd_addr_f, UInt<8>("h0d4")) @[ifu_bp_ctl.scala 418:77] - node _T_3561 = bits(_T_3560, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3562 = eq(btb_rd_addr_f, UInt<8>("h0d5")) @[ifu_bp_ctl.scala 418:77] - node _T_3563 = bits(_T_3562, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3564 = eq(btb_rd_addr_f, UInt<8>("h0d6")) @[ifu_bp_ctl.scala 418:77] - node _T_3565 = bits(_T_3564, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3566 = eq(btb_rd_addr_f, UInt<8>("h0d7")) @[ifu_bp_ctl.scala 418:77] - node _T_3567 = bits(_T_3566, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3568 = eq(btb_rd_addr_f, UInt<8>("h0d8")) @[ifu_bp_ctl.scala 418:77] - node _T_3569 = bits(_T_3568, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3570 = eq(btb_rd_addr_f, UInt<8>("h0d9")) @[ifu_bp_ctl.scala 418:77] - node _T_3571 = bits(_T_3570, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3572 = eq(btb_rd_addr_f, UInt<8>("h0da")) @[ifu_bp_ctl.scala 418:77] - node _T_3573 = bits(_T_3572, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3574 = eq(btb_rd_addr_f, UInt<8>("h0db")) @[ifu_bp_ctl.scala 418:77] - node _T_3575 = bits(_T_3574, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3576 = eq(btb_rd_addr_f, UInt<8>("h0dc")) @[ifu_bp_ctl.scala 418:77] - node _T_3577 = bits(_T_3576, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3578 = eq(btb_rd_addr_f, UInt<8>("h0dd")) @[ifu_bp_ctl.scala 418:77] - node _T_3579 = bits(_T_3578, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3580 = eq(btb_rd_addr_f, UInt<8>("h0de")) @[ifu_bp_ctl.scala 418:77] - node _T_3581 = bits(_T_3580, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3582 = eq(btb_rd_addr_f, UInt<8>("h0df")) @[ifu_bp_ctl.scala 418:77] - node _T_3583 = bits(_T_3582, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3584 = eq(btb_rd_addr_f, UInt<8>("h0e0")) @[ifu_bp_ctl.scala 418:77] - node _T_3585 = bits(_T_3584, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3586 = eq(btb_rd_addr_f, UInt<8>("h0e1")) @[ifu_bp_ctl.scala 418:77] - node _T_3587 = bits(_T_3586, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3588 = eq(btb_rd_addr_f, UInt<8>("h0e2")) @[ifu_bp_ctl.scala 418:77] - node _T_3589 = bits(_T_3588, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3590 = eq(btb_rd_addr_f, UInt<8>("h0e3")) @[ifu_bp_ctl.scala 418:77] - node _T_3591 = bits(_T_3590, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3592 = eq(btb_rd_addr_f, UInt<8>("h0e4")) @[ifu_bp_ctl.scala 418:77] - node _T_3593 = bits(_T_3592, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3594 = eq(btb_rd_addr_f, UInt<8>("h0e5")) @[ifu_bp_ctl.scala 418:77] - node _T_3595 = bits(_T_3594, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3596 = eq(btb_rd_addr_f, UInt<8>("h0e6")) @[ifu_bp_ctl.scala 418:77] - node _T_3597 = bits(_T_3596, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3598 = eq(btb_rd_addr_f, UInt<8>("h0e7")) @[ifu_bp_ctl.scala 418:77] - node _T_3599 = bits(_T_3598, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3600 = eq(btb_rd_addr_f, UInt<8>("h0e8")) @[ifu_bp_ctl.scala 418:77] - node _T_3601 = bits(_T_3600, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3602 = eq(btb_rd_addr_f, UInt<8>("h0e9")) @[ifu_bp_ctl.scala 418:77] - node _T_3603 = bits(_T_3602, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3604 = eq(btb_rd_addr_f, UInt<8>("h0ea")) @[ifu_bp_ctl.scala 418:77] - node _T_3605 = bits(_T_3604, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3606 = eq(btb_rd_addr_f, UInt<8>("h0eb")) @[ifu_bp_ctl.scala 418:77] - node _T_3607 = bits(_T_3606, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3608 = eq(btb_rd_addr_f, UInt<8>("h0ec")) @[ifu_bp_ctl.scala 418:77] - node _T_3609 = bits(_T_3608, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3610 = eq(btb_rd_addr_f, UInt<8>("h0ed")) @[ifu_bp_ctl.scala 418:77] - node _T_3611 = bits(_T_3610, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3612 = eq(btb_rd_addr_f, UInt<8>("h0ee")) @[ifu_bp_ctl.scala 418:77] - node _T_3613 = bits(_T_3612, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3614 = eq(btb_rd_addr_f, UInt<8>("h0ef")) @[ifu_bp_ctl.scala 418:77] - node _T_3615 = bits(_T_3614, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3616 = eq(btb_rd_addr_f, UInt<8>("h0f0")) @[ifu_bp_ctl.scala 418:77] - node _T_3617 = bits(_T_3616, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3618 = eq(btb_rd_addr_f, UInt<8>("h0f1")) @[ifu_bp_ctl.scala 418:77] - node _T_3619 = bits(_T_3618, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3620 = eq(btb_rd_addr_f, UInt<8>("h0f2")) @[ifu_bp_ctl.scala 418:77] - node _T_3621 = bits(_T_3620, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3622 = eq(btb_rd_addr_f, UInt<8>("h0f3")) @[ifu_bp_ctl.scala 418:77] - node _T_3623 = bits(_T_3622, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3624 = eq(btb_rd_addr_f, UInt<8>("h0f4")) @[ifu_bp_ctl.scala 418:77] - node _T_3625 = bits(_T_3624, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3626 = eq(btb_rd_addr_f, UInt<8>("h0f5")) @[ifu_bp_ctl.scala 418:77] - node _T_3627 = bits(_T_3626, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3628 = eq(btb_rd_addr_f, UInt<8>("h0f6")) @[ifu_bp_ctl.scala 418:77] - node _T_3629 = bits(_T_3628, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3630 = eq(btb_rd_addr_f, UInt<8>("h0f7")) @[ifu_bp_ctl.scala 418:77] - node _T_3631 = bits(_T_3630, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3632 = eq(btb_rd_addr_f, UInt<8>("h0f8")) @[ifu_bp_ctl.scala 418:77] - node _T_3633 = bits(_T_3632, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3634 = eq(btb_rd_addr_f, UInt<8>("h0f9")) @[ifu_bp_ctl.scala 418:77] - node _T_3635 = bits(_T_3634, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3636 = eq(btb_rd_addr_f, UInt<8>("h0fa")) @[ifu_bp_ctl.scala 418:77] - node _T_3637 = bits(_T_3636, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3638 = eq(btb_rd_addr_f, UInt<8>("h0fb")) @[ifu_bp_ctl.scala 418:77] - node _T_3639 = bits(_T_3638, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3640 = eq(btb_rd_addr_f, UInt<8>("h0fc")) @[ifu_bp_ctl.scala 418:77] - node _T_3641 = bits(_T_3640, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3642 = eq(btb_rd_addr_f, UInt<8>("h0fd")) @[ifu_bp_ctl.scala 418:77] - node _T_3643 = bits(_T_3642, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3644 = eq(btb_rd_addr_f, UInt<8>("h0fe")) @[ifu_bp_ctl.scala 418:77] - node _T_3645 = bits(_T_3644, 0, 0) @[ifu_bp_ctl.scala 418:85] - node _T_3646 = eq(btb_rd_addr_f, UInt<8>("h0ff")) @[ifu_bp_ctl.scala 418:77] - node _T_3647 = bits(_T_3646, 0, 0) @[ifu_bp_ctl.scala 418:85] + btb_bank0_rd_data_way0_f <= _T_3135 @[ifu_bp_ctl.scala 418:28] + node _T_3136 = eq(btb_rd_addr_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 419:77] + node _T_3137 = bits(_T_3136, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3138 = eq(btb_rd_addr_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 419:77] + node _T_3139 = bits(_T_3138, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3140 = eq(btb_rd_addr_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 419:77] + node _T_3141 = bits(_T_3140, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3142 = eq(btb_rd_addr_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 419:77] + node _T_3143 = bits(_T_3142, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3144 = eq(btb_rd_addr_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 419:77] + node _T_3145 = bits(_T_3144, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3146 = eq(btb_rd_addr_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 419:77] + node _T_3147 = bits(_T_3146, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3148 = eq(btb_rd_addr_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 419:77] + node _T_3149 = bits(_T_3148, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3150 = eq(btb_rd_addr_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 419:77] + node _T_3151 = bits(_T_3150, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3152 = eq(btb_rd_addr_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 419:77] + node _T_3153 = bits(_T_3152, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3154 = eq(btb_rd_addr_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 419:77] + node _T_3155 = bits(_T_3154, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3156 = eq(btb_rd_addr_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 419:77] + node _T_3157 = bits(_T_3156, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3158 = eq(btb_rd_addr_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 419:77] + node _T_3159 = bits(_T_3158, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3160 = eq(btb_rd_addr_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 419:77] + node _T_3161 = bits(_T_3160, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3162 = eq(btb_rd_addr_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 419:77] + node _T_3163 = bits(_T_3162, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3164 = eq(btb_rd_addr_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 419:77] + node _T_3165 = bits(_T_3164, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3166 = eq(btb_rd_addr_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 419:77] + node _T_3167 = bits(_T_3166, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3168 = eq(btb_rd_addr_f, UInt<5>("h010")) @[ifu_bp_ctl.scala 419:77] + node _T_3169 = bits(_T_3168, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3170 = eq(btb_rd_addr_f, UInt<5>("h011")) @[ifu_bp_ctl.scala 419:77] + node _T_3171 = bits(_T_3170, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3172 = eq(btb_rd_addr_f, UInt<5>("h012")) @[ifu_bp_ctl.scala 419:77] + node _T_3173 = bits(_T_3172, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3174 = eq(btb_rd_addr_f, UInt<5>("h013")) @[ifu_bp_ctl.scala 419:77] + node _T_3175 = bits(_T_3174, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3176 = eq(btb_rd_addr_f, UInt<5>("h014")) @[ifu_bp_ctl.scala 419:77] + node _T_3177 = bits(_T_3176, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3178 = eq(btb_rd_addr_f, UInt<5>("h015")) @[ifu_bp_ctl.scala 419:77] + node _T_3179 = bits(_T_3178, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3180 = eq(btb_rd_addr_f, UInt<5>("h016")) @[ifu_bp_ctl.scala 419:77] + node _T_3181 = bits(_T_3180, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3182 = eq(btb_rd_addr_f, UInt<5>("h017")) @[ifu_bp_ctl.scala 419:77] + node _T_3183 = bits(_T_3182, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3184 = eq(btb_rd_addr_f, UInt<5>("h018")) @[ifu_bp_ctl.scala 419:77] + node _T_3185 = bits(_T_3184, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3186 = eq(btb_rd_addr_f, UInt<5>("h019")) @[ifu_bp_ctl.scala 419:77] + node _T_3187 = bits(_T_3186, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3188 = eq(btb_rd_addr_f, UInt<5>("h01a")) @[ifu_bp_ctl.scala 419:77] + node _T_3189 = bits(_T_3188, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3190 = eq(btb_rd_addr_f, UInt<5>("h01b")) @[ifu_bp_ctl.scala 419:77] + node _T_3191 = bits(_T_3190, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3192 = eq(btb_rd_addr_f, UInt<5>("h01c")) @[ifu_bp_ctl.scala 419:77] + node _T_3193 = bits(_T_3192, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3194 = eq(btb_rd_addr_f, UInt<5>("h01d")) @[ifu_bp_ctl.scala 419:77] + node _T_3195 = bits(_T_3194, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3196 = eq(btb_rd_addr_f, UInt<5>("h01e")) @[ifu_bp_ctl.scala 419:77] + node _T_3197 = bits(_T_3196, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3198 = eq(btb_rd_addr_f, UInt<5>("h01f")) @[ifu_bp_ctl.scala 419:77] + node _T_3199 = bits(_T_3198, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3200 = eq(btb_rd_addr_f, UInt<6>("h020")) @[ifu_bp_ctl.scala 419:77] + node _T_3201 = bits(_T_3200, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3202 = eq(btb_rd_addr_f, UInt<6>("h021")) @[ifu_bp_ctl.scala 419:77] + node _T_3203 = bits(_T_3202, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3204 = eq(btb_rd_addr_f, UInt<6>("h022")) @[ifu_bp_ctl.scala 419:77] + node _T_3205 = bits(_T_3204, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3206 = eq(btb_rd_addr_f, UInt<6>("h023")) @[ifu_bp_ctl.scala 419:77] + node _T_3207 = bits(_T_3206, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3208 = eq(btb_rd_addr_f, UInt<6>("h024")) @[ifu_bp_ctl.scala 419:77] + node _T_3209 = bits(_T_3208, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3210 = eq(btb_rd_addr_f, UInt<6>("h025")) @[ifu_bp_ctl.scala 419:77] + node _T_3211 = bits(_T_3210, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3212 = eq(btb_rd_addr_f, UInt<6>("h026")) @[ifu_bp_ctl.scala 419:77] + node _T_3213 = bits(_T_3212, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3214 = eq(btb_rd_addr_f, UInt<6>("h027")) @[ifu_bp_ctl.scala 419:77] + node _T_3215 = bits(_T_3214, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3216 = eq(btb_rd_addr_f, UInt<6>("h028")) @[ifu_bp_ctl.scala 419:77] + node _T_3217 = bits(_T_3216, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3218 = eq(btb_rd_addr_f, UInt<6>("h029")) @[ifu_bp_ctl.scala 419:77] + node _T_3219 = bits(_T_3218, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3220 = eq(btb_rd_addr_f, UInt<6>("h02a")) @[ifu_bp_ctl.scala 419:77] + node _T_3221 = bits(_T_3220, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3222 = eq(btb_rd_addr_f, UInt<6>("h02b")) @[ifu_bp_ctl.scala 419:77] + node _T_3223 = bits(_T_3222, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3224 = eq(btb_rd_addr_f, UInt<6>("h02c")) @[ifu_bp_ctl.scala 419:77] + node _T_3225 = bits(_T_3224, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3226 = eq(btb_rd_addr_f, UInt<6>("h02d")) @[ifu_bp_ctl.scala 419:77] + node _T_3227 = bits(_T_3226, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3228 = eq(btb_rd_addr_f, UInt<6>("h02e")) @[ifu_bp_ctl.scala 419:77] + node _T_3229 = bits(_T_3228, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3230 = eq(btb_rd_addr_f, UInt<6>("h02f")) @[ifu_bp_ctl.scala 419:77] + node _T_3231 = bits(_T_3230, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3232 = eq(btb_rd_addr_f, UInt<6>("h030")) @[ifu_bp_ctl.scala 419:77] + node _T_3233 = bits(_T_3232, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3234 = eq(btb_rd_addr_f, UInt<6>("h031")) @[ifu_bp_ctl.scala 419:77] + node _T_3235 = bits(_T_3234, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3236 = eq(btb_rd_addr_f, UInt<6>("h032")) @[ifu_bp_ctl.scala 419:77] + node _T_3237 = bits(_T_3236, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3238 = eq(btb_rd_addr_f, UInt<6>("h033")) @[ifu_bp_ctl.scala 419:77] + node _T_3239 = bits(_T_3238, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3240 = eq(btb_rd_addr_f, UInt<6>("h034")) @[ifu_bp_ctl.scala 419:77] + node _T_3241 = bits(_T_3240, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3242 = eq(btb_rd_addr_f, UInt<6>("h035")) @[ifu_bp_ctl.scala 419:77] + node _T_3243 = bits(_T_3242, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3244 = eq(btb_rd_addr_f, UInt<6>("h036")) @[ifu_bp_ctl.scala 419:77] + node _T_3245 = bits(_T_3244, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3246 = eq(btb_rd_addr_f, UInt<6>("h037")) @[ifu_bp_ctl.scala 419:77] + node _T_3247 = bits(_T_3246, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3248 = eq(btb_rd_addr_f, UInt<6>("h038")) @[ifu_bp_ctl.scala 419:77] + node _T_3249 = bits(_T_3248, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3250 = eq(btb_rd_addr_f, UInt<6>("h039")) @[ifu_bp_ctl.scala 419:77] + node _T_3251 = bits(_T_3250, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3252 = eq(btb_rd_addr_f, UInt<6>("h03a")) @[ifu_bp_ctl.scala 419:77] + node _T_3253 = bits(_T_3252, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3254 = eq(btb_rd_addr_f, UInt<6>("h03b")) @[ifu_bp_ctl.scala 419:77] + node _T_3255 = bits(_T_3254, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3256 = eq(btb_rd_addr_f, UInt<6>("h03c")) @[ifu_bp_ctl.scala 419:77] + node _T_3257 = bits(_T_3256, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3258 = eq(btb_rd_addr_f, UInt<6>("h03d")) @[ifu_bp_ctl.scala 419:77] + node _T_3259 = bits(_T_3258, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3260 = eq(btb_rd_addr_f, UInt<6>("h03e")) @[ifu_bp_ctl.scala 419:77] + node _T_3261 = bits(_T_3260, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3262 = eq(btb_rd_addr_f, UInt<6>("h03f")) @[ifu_bp_ctl.scala 419:77] + node _T_3263 = bits(_T_3262, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3264 = eq(btb_rd_addr_f, UInt<7>("h040")) @[ifu_bp_ctl.scala 419:77] + node _T_3265 = bits(_T_3264, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3266 = eq(btb_rd_addr_f, UInt<7>("h041")) @[ifu_bp_ctl.scala 419:77] + node _T_3267 = bits(_T_3266, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3268 = eq(btb_rd_addr_f, UInt<7>("h042")) @[ifu_bp_ctl.scala 419:77] + node _T_3269 = bits(_T_3268, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3270 = eq(btb_rd_addr_f, UInt<7>("h043")) @[ifu_bp_ctl.scala 419:77] + node _T_3271 = bits(_T_3270, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3272 = eq(btb_rd_addr_f, UInt<7>("h044")) @[ifu_bp_ctl.scala 419:77] + node _T_3273 = bits(_T_3272, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3274 = eq(btb_rd_addr_f, UInt<7>("h045")) @[ifu_bp_ctl.scala 419:77] + node _T_3275 = bits(_T_3274, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3276 = eq(btb_rd_addr_f, UInt<7>("h046")) @[ifu_bp_ctl.scala 419:77] + node _T_3277 = bits(_T_3276, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3278 = eq(btb_rd_addr_f, UInt<7>("h047")) @[ifu_bp_ctl.scala 419:77] + node _T_3279 = bits(_T_3278, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3280 = eq(btb_rd_addr_f, UInt<7>("h048")) @[ifu_bp_ctl.scala 419:77] + node _T_3281 = bits(_T_3280, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3282 = eq(btb_rd_addr_f, UInt<7>("h049")) @[ifu_bp_ctl.scala 419:77] + node _T_3283 = bits(_T_3282, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3284 = eq(btb_rd_addr_f, UInt<7>("h04a")) @[ifu_bp_ctl.scala 419:77] + node _T_3285 = bits(_T_3284, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3286 = eq(btb_rd_addr_f, UInt<7>("h04b")) @[ifu_bp_ctl.scala 419:77] + node _T_3287 = bits(_T_3286, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3288 = eq(btb_rd_addr_f, UInt<7>("h04c")) @[ifu_bp_ctl.scala 419:77] + node _T_3289 = bits(_T_3288, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3290 = eq(btb_rd_addr_f, UInt<7>("h04d")) @[ifu_bp_ctl.scala 419:77] + node _T_3291 = bits(_T_3290, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3292 = eq(btb_rd_addr_f, UInt<7>("h04e")) @[ifu_bp_ctl.scala 419:77] + node _T_3293 = bits(_T_3292, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3294 = eq(btb_rd_addr_f, UInt<7>("h04f")) @[ifu_bp_ctl.scala 419:77] + node _T_3295 = bits(_T_3294, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3296 = eq(btb_rd_addr_f, UInt<7>("h050")) @[ifu_bp_ctl.scala 419:77] + node _T_3297 = bits(_T_3296, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3298 = eq(btb_rd_addr_f, UInt<7>("h051")) @[ifu_bp_ctl.scala 419:77] + node _T_3299 = bits(_T_3298, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3300 = eq(btb_rd_addr_f, UInt<7>("h052")) @[ifu_bp_ctl.scala 419:77] + node _T_3301 = bits(_T_3300, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3302 = eq(btb_rd_addr_f, UInt<7>("h053")) @[ifu_bp_ctl.scala 419:77] + node _T_3303 = bits(_T_3302, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3304 = eq(btb_rd_addr_f, UInt<7>("h054")) @[ifu_bp_ctl.scala 419:77] + node _T_3305 = bits(_T_3304, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3306 = eq(btb_rd_addr_f, UInt<7>("h055")) @[ifu_bp_ctl.scala 419:77] + node _T_3307 = bits(_T_3306, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3308 = eq(btb_rd_addr_f, UInt<7>("h056")) @[ifu_bp_ctl.scala 419:77] + node _T_3309 = bits(_T_3308, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3310 = eq(btb_rd_addr_f, UInt<7>("h057")) @[ifu_bp_ctl.scala 419:77] + node _T_3311 = bits(_T_3310, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3312 = eq(btb_rd_addr_f, UInt<7>("h058")) @[ifu_bp_ctl.scala 419:77] + node _T_3313 = bits(_T_3312, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3314 = eq(btb_rd_addr_f, UInt<7>("h059")) @[ifu_bp_ctl.scala 419:77] + node _T_3315 = bits(_T_3314, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3316 = eq(btb_rd_addr_f, UInt<7>("h05a")) @[ifu_bp_ctl.scala 419:77] + node _T_3317 = bits(_T_3316, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3318 = eq(btb_rd_addr_f, UInt<7>("h05b")) @[ifu_bp_ctl.scala 419:77] + node _T_3319 = bits(_T_3318, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3320 = eq(btb_rd_addr_f, UInt<7>("h05c")) @[ifu_bp_ctl.scala 419:77] + node _T_3321 = bits(_T_3320, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3322 = eq(btb_rd_addr_f, UInt<7>("h05d")) @[ifu_bp_ctl.scala 419:77] + node _T_3323 = bits(_T_3322, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3324 = eq(btb_rd_addr_f, UInt<7>("h05e")) @[ifu_bp_ctl.scala 419:77] + node _T_3325 = bits(_T_3324, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3326 = eq(btb_rd_addr_f, UInt<7>("h05f")) @[ifu_bp_ctl.scala 419:77] + node _T_3327 = bits(_T_3326, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3328 = eq(btb_rd_addr_f, UInt<7>("h060")) @[ifu_bp_ctl.scala 419:77] + node _T_3329 = bits(_T_3328, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3330 = eq(btb_rd_addr_f, UInt<7>("h061")) @[ifu_bp_ctl.scala 419:77] + node _T_3331 = bits(_T_3330, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3332 = eq(btb_rd_addr_f, UInt<7>("h062")) @[ifu_bp_ctl.scala 419:77] + node _T_3333 = bits(_T_3332, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3334 = eq(btb_rd_addr_f, UInt<7>("h063")) @[ifu_bp_ctl.scala 419:77] + node _T_3335 = bits(_T_3334, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3336 = eq(btb_rd_addr_f, UInt<7>("h064")) @[ifu_bp_ctl.scala 419:77] + node _T_3337 = bits(_T_3336, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3338 = eq(btb_rd_addr_f, UInt<7>("h065")) @[ifu_bp_ctl.scala 419:77] + node _T_3339 = bits(_T_3338, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3340 = eq(btb_rd_addr_f, UInt<7>("h066")) @[ifu_bp_ctl.scala 419:77] + node _T_3341 = bits(_T_3340, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3342 = eq(btb_rd_addr_f, UInt<7>("h067")) @[ifu_bp_ctl.scala 419:77] + node _T_3343 = bits(_T_3342, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3344 = eq(btb_rd_addr_f, UInt<7>("h068")) @[ifu_bp_ctl.scala 419:77] + node _T_3345 = bits(_T_3344, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3346 = eq(btb_rd_addr_f, UInt<7>("h069")) @[ifu_bp_ctl.scala 419:77] + node _T_3347 = bits(_T_3346, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3348 = eq(btb_rd_addr_f, UInt<7>("h06a")) @[ifu_bp_ctl.scala 419:77] + node _T_3349 = bits(_T_3348, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3350 = eq(btb_rd_addr_f, UInt<7>("h06b")) @[ifu_bp_ctl.scala 419:77] + node _T_3351 = bits(_T_3350, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3352 = eq(btb_rd_addr_f, UInt<7>("h06c")) @[ifu_bp_ctl.scala 419:77] + node _T_3353 = bits(_T_3352, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3354 = eq(btb_rd_addr_f, UInt<7>("h06d")) @[ifu_bp_ctl.scala 419:77] + node _T_3355 = bits(_T_3354, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3356 = eq(btb_rd_addr_f, UInt<7>("h06e")) @[ifu_bp_ctl.scala 419:77] + node _T_3357 = bits(_T_3356, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3358 = eq(btb_rd_addr_f, UInt<7>("h06f")) @[ifu_bp_ctl.scala 419:77] + node _T_3359 = bits(_T_3358, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3360 = eq(btb_rd_addr_f, UInt<7>("h070")) @[ifu_bp_ctl.scala 419:77] + node _T_3361 = bits(_T_3360, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3362 = eq(btb_rd_addr_f, UInt<7>("h071")) @[ifu_bp_ctl.scala 419:77] + node _T_3363 = bits(_T_3362, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3364 = eq(btb_rd_addr_f, UInt<7>("h072")) @[ifu_bp_ctl.scala 419:77] + node _T_3365 = bits(_T_3364, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3366 = eq(btb_rd_addr_f, UInt<7>("h073")) @[ifu_bp_ctl.scala 419:77] + node _T_3367 = bits(_T_3366, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3368 = eq(btb_rd_addr_f, UInt<7>("h074")) @[ifu_bp_ctl.scala 419:77] + node _T_3369 = bits(_T_3368, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3370 = eq(btb_rd_addr_f, UInt<7>("h075")) @[ifu_bp_ctl.scala 419:77] + node _T_3371 = bits(_T_3370, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3372 = eq(btb_rd_addr_f, UInt<7>("h076")) @[ifu_bp_ctl.scala 419:77] + node _T_3373 = bits(_T_3372, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3374 = eq(btb_rd_addr_f, UInt<7>("h077")) @[ifu_bp_ctl.scala 419:77] + node _T_3375 = bits(_T_3374, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3376 = eq(btb_rd_addr_f, UInt<7>("h078")) @[ifu_bp_ctl.scala 419:77] + node _T_3377 = bits(_T_3376, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3378 = eq(btb_rd_addr_f, UInt<7>("h079")) @[ifu_bp_ctl.scala 419:77] + node _T_3379 = bits(_T_3378, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3380 = eq(btb_rd_addr_f, UInt<7>("h07a")) @[ifu_bp_ctl.scala 419:77] + node _T_3381 = bits(_T_3380, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3382 = eq(btb_rd_addr_f, UInt<7>("h07b")) @[ifu_bp_ctl.scala 419:77] + node _T_3383 = bits(_T_3382, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3384 = eq(btb_rd_addr_f, UInt<7>("h07c")) @[ifu_bp_ctl.scala 419:77] + node _T_3385 = bits(_T_3384, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3386 = eq(btb_rd_addr_f, UInt<7>("h07d")) @[ifu_bp_ctl.scala 419:77] + node _T_3387 = bits(_T_3386, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3388 = eq(btb_rd_addr_f, UInt<7>("h07e")) @[ifu_bp_ctl.scala 419:77] + node _T_3389 = bits(_T_3388, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3390 = eq(btb_rd_addr_f, UInt<7>("h07f")) @[ifu_bp_ctl.scala 419:77] + node _T_3391 = bits(_T_3390, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3392 = eq(btb_rd_addr_f, UInt<8>("h080")) @[ifu_bp_ctl.scala 419:77] + node _T_3393 = bits(_T_3392, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3394 = eq(btb_rd_addr_f, UInt<8>("h081")) @[ifu_bp_ctl.scala 419:77] + node _T_3395 = bits(_T_3394, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3396 = eq(btb_rd_addr_f, UInt<8>("h082")) @[ifu_bp_ctl.scala 419:77] + node _T_3397 = bits(_T_3396, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3398 = eq(btb_rd_addr_f, UInt<8>("h083")) @[ifu_bp_ctl.scala 419:77] + node _T_3399 = bits(_T_3398, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3400 = eq(btb_rd_addr_f, UInt<8>("h084")) @[ifu_bp_ctl.scala 419:77] + node _T_3401 = bits(_T_3400, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3402 = eq(btb_rd_addr_f, UInt<8>("h085")) @[ifu_bp_ctl.scala 419:77] + node _T_3403 = bits(_T_3402, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3404 = eq(btb_rd_addr_f, UInt<8>("h086")) @[ifu_bp_ctl.scala 419:77] + node _T_3405 = bits(_T_3404, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3406 = eq(btb_rd_addr_f, UInt<8>("h087")) @[ifu_bp_ctl.scala 419:77] + node _T_3407 = bits(_T_3406, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3408 = eq(btb_rd_addr_f, UInt<8>("h088")) @[ifu_bp_ctl.scala 419:77] + node _T_3409 = bits(_T_3408, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3410 = eq(btb_rd_addr_f, UInt<8>("h089")) @[ifu_bp_ctl.scala 419:77] + node _T_3411 = bits(_T_3410, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3412 = eq(btb_rd_addr_f, UInt<8>("h08a")) @[ifu_bp_ctl.scala 419:77] + node _T_3413 = bits(_T_3412, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3414 = eq(btb_rd_addr_f, UInt<8>("h08b")) @[ifu_bp_ctl.scala 419:77] + node _T_3415 = bits(_T_3414, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3416 = eq(btb_rd_addr_f, UInt<8>("h08c")) @[ifu_bp_ctl.scala 419:77] + node _T_3417 = bits(_T_3416, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3418 = eq(btb_rd_addr_f, UInt<8>("h08d")) @[ifu_bp_ctl.scala 419:77] + node _T_3419 = bits(_T_3418, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3420 = eq(btb_rd_addr_f, UInt<8>("h08e")) @[ifu_bp_ctl.scala 419:77] + node _T_3421 = bits(_T_3420, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3422 = eq(btb_rd_addr_f, UInt<8>("h08f")) @[ifu_bp_ctl.scala 419:77] + node _T_3423 = bits(_T_3422, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3424 = eq(btb_rd_addr_f, UInt<8>("h090")) @[ifu_bp_ctl.scala 419:77] + node _T_3425 = bits(_T_3424, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3426 = eq(btb_rd_addr_f, UInt<8>("h091")) @[ifu_bp_ctl.scala 419:77] + node _T_3427 = bits(_T_3426, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3428 = eq(btb_rd_addr_f, UInt<8>("h092")) @[ifu_bp_ctl.scala 419:77] + node _T_3429 = bits(_T_3428, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3430 = eq(btb_rd_addr_f, UInt<8>("h093")) @[ifu_bp_ctl.scala 419:77] + node _T_3431 = bits(_T_3430, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3432 = eq(btb_rd_addr_f, UInt<8>("h094")) @[ifu_bp_ctl.scala 419:77] + node _T_3433 = bits(_T_3432, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3434 = eq(btb_rd_addr_f, UInt<8>("h095")) @[ifu_bp_ctl.scala 419:77] + node _T_3435 = bits(_T_3434, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3436 = eq(btb_rd_addr_f, UInt<8>("h096")) @[ifu_bp_ctl.scala 419:77] + node _T_3437 = bits(_T_3436, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3438 = eq(btb_rd_addr_f, UInt<8>("h097")) @[ifu_bp_ctl.scala 419:77] + node _T_3439 = bits(_T_3438, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3440 = eq(btb_rd_addr_f, UInt<8>("h098")) @[ifu_bp_ctl.scala 419:77] + node _T_3441 = bits(_T_3440, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3442 = eq(btb_rd_addr_f, UInt<8>("h099")) @[ifu_bp_ctl.scala 419:77] + node _T_3443 = bits(_T_3442, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3444 = eq(btb_rd_addr_f, UInt<8>("h09a")) @[ifu_bp_ctl.scala 419:77] + node _T_3445 = bits(_T_3444, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3446 = eq(btb_rd_addr_f, UInt<8>("h09b")) @[ifu_bp_ctl.scala 419:77] + node _T_3447 = bits(_T_3446, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3448 = eq(btb_rd_addr_f, UInt<8>("h09c")) @[ifu_bp_ctl.scala 419:77] + node _T_3449 = bits(_T_3448, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3450 = eq(btb_rd_addr_f, UInt<8>("h09d")) @[ifu_bp_ctl.scala 419:77] + node _T_3451 = bits(_T_3450, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3452 = eq(btb_rd_addr_f, UInt<8>("h09e")) @[ifu_bp_ctl.scala 419:77] + node _T_3453 = bits(_T_3452, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3454 = eq(btb_rd_addr_f, UInt<8>("h09f")) @[ifu_bp_ctl.scala 419:77] + node _T_3455 = bits(_T_3454, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3456 = eq(btb_rd_addr_f, UInt<8>("h0a0")) @[ifu_bp_ctl.scala 419:77] + node _T_3457 = bits(_T_3456, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3458 = eq(btb_rd_addr_f, UInt<8>("h0a1")) @[ifu_bp_ctl.scala 419:77] + node _T_3459 = bits(_T_3458, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3460 = eq(btb_rd_addr_f, UInt<8>("h0a2")) @[ifu_bp_ctl.scala 419:77] + node _T_3461 = bits(_T_3460, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3462 = eq(btb_rd_addr_f, UInt<8>("h0a3")) @[ifu_bp_ctl.scala 419:77] + node _T_3463 = bits(_T_3462, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3464 = eq(btb_rd_addr_f, UInt<8>("h0a4")) @[ifu_bp_ctl.scala 419:77] + node _T_3465 = bits(_T_3464, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3466 = eq(btb_rd_addr_f, UInt<8>("h0a5")) @[ifu_bp_ctl.scala 419:77] + node _T_3467 = bits(_T_3466, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3468 = eq(btb_rd_addr_f, UInt<8>("h0a6")) @[ifu_bp_ctl.scala 419:77] + node _T_3469 = bits(_T_3468, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3470 = eq(btb_rd_addr_f, UInt<8>("h0a7")) @[ifu_bp_ctl.scala 419:77] + node _T_3471 = bits(_T_3470, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3472 = eq(btb_rd_addr_f, UInt<8>("h0a8")) @[ifu_bp_ctl.scala 419:77] + node _T_3473 = bits(_T_3472, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3474 = eq(btb_rd_addr_f, UInt<8>("h0a9")) @[ifu_bp_ctl.scala 419:77] + node _T_3475 = bits(_T_3474, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3476 = eq(btb_rd_addr_f, UInt<8>("h0aa")) @[ifu_bp_ctl.scala 419:77] + node _T_3477 = bits(_T_3476, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3478 = eq(btb_rd_addr_f, UInt<8>("h0ab")) @[ifu_bp_ctl.scala 419:77] + node _T_3479 = bits(_T_3478, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3480 = eq(btb_rd_addr_f, UInt<8>("h0ac")) @[ifu_bp_ctl.scala 419:77] + node _T_3481 = bits(_T_3480, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3482 = eq(btb_rd_addr_f, UInt<8>("h0ad")) @[ifu_bp_ctl.scala 419:77] + node _T_3483 = bits(_T_3482, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3484 = eq(btb_rd_addr_f, UInt<8>("h0ae")) @[ifu_bp_ctl.scala 419:77] + node _T_3485 = bits(_T_3484, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3486 = eq(btb_rd_addr_f, UInt<8>("h0af")) @[ifu_bp_ctl.scala 419:77] + node _T_3487 = bits(_T_3486, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3488 = eq(btb_rd_addr_f, UInt<8>("h0b0")) @[ifu_bp_ctl.scala 419:77] + node _T_3489 = bits(_T_3488, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3490 = eq(btb_rd_addr_f, UInt<8>("h0b1")) @[ifu_bp_ctl.scala 419:77] + node _T_3491 = bits(_T_3490, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3492 = eq(btb_rd_addr_f, UInt<8>("h0b2")) @[ifu_bp_ctl.scala 419:77] + node _T_3493 = bits(_T_3492, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3494 = eq(btb_rd_addr_f, UInt<8>("h0b3")) @[ifu_bp_ctl.scala 419:77] + node _T_3495 = bits(_T_3494, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3496 = eq(btb_rd_addr_f, UInt<8>("h0b4")) @[ifu_bp_ctl.scala 419:77] + node _T_3497 = bits(_T_3496, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3498 = eq(btb_rd_addr_f, UInt<8>("h0b5")) @[ifu_bp_ctl.scala 419:77] + node _T_3499 = bits(_T_3498, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3500 = eq(btb_rd_addr_f, UInt<8>("h0b6")) @[ifu_bp_ctl.scala 419:77] + node _T_3501 = bits(_T_3500, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3502 = eq(btb_rd_addr_f, UInt<8>("h0b7")) @[ifu_bp_ctl.scala 419:77] + node _T_3503 = bits(_T_3502, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3504 = eq(btb_rd_addr_f, UInt<8>("h0b8")) @[ifu_bp_ctl.scala 419:77] + node _T_3505 = bits(_T_3504, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3506 = eq(btb_rd_addr_f, UInt<8>("h0b9")) @[ifu_bp_ctl.scala 419:77] + node _T_3507 = bits(_T_3506, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3508 = eq(btb_rd_addr_f, UInt<8>("h0ba")) @[ifu_bp_ctl.scala 419:77] + node _T_3509 = bits(_T_3508, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3510 = eq(btb_rd_addr_f, UInt<8>("h0bb")) @[ifu_bp_ctl.scala 419:77] + node _T_3511 = bits(_T_3510, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3512 = eq(btb_rd_addr_f, UInt<8>("h0bc")) @[ifu_bp_ctl.scala 419:77] + node _T_3513 = bits(_T_3512, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3514 = eq(btb_rd_addr_f, UInt<8>("h0bd")) @[ifu_bp_ctl.scala 419:77] + node _T_3515 = bits(_T_3514, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3516 = eq(btb_rd_addr_f, UInt<8>("h0be")) @[ifu_bp_ctl.scala 419:77] + node _T_3517 = bits(_T_3516, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3518 = eq(btb_rd_addr_f, UInt<8>("h0bf")) @[ifu_bp_ctl.scala 419:77] + node _T_3519 = bits(_T_3518, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3520 = eq(btb_rd_addr_f, UInt<8>("h0c0")) @[ifu_bp_ctl.scala 419:77] + node _T_3521 = bits(_T_3520, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3522 = eq(btb_rd_addr_f, UInt<8>("h0c1")) @[ifu_bp_ctl.scala 419:77] + node _T_3523 = bits(_T_3522, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3524 = eq(btb_rd_addr_f, UInt<8>("h0c2")) @[ifu_bp_ctl.scala 419:77] + node _T_3525 = bits(_T_3524, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3526 = eq(btb_rd_addr_f, UInt<8>("h0c3")) @[ifu_bp_ctl.scala 419:77] + node _T_3527 = bits(_T_3526, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3528 = eq(btb_rd_addr_f, UInt<8>("h0c4")) @[ifu_bp_ctl.scala 419:77] + node _T_3529 = bits(_T_3528, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3530 = eq(btb_rd_addr_f, UInt<8>("h0c5")) @[ifu_bp_ctl.scala 419:77] + node _T_3531 = bits(_T_3530, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3532 = eq(btb_rd_addr_f, UInt<8>("h0c6")) @[ifu_bp_ctl.scala 419:77] + node _T_3533 = bits(_T_3532, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3534 = eq(btb_rd_addr_f, UInt<8>("h0c7")) @[ifu_bp_ctl.scala 419:77] + node _T_3535 = bits(_T_3534, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3536 = eq(btb_rd_addr_f, UInt<8>("h0c8")) @[ifu_bp_ctl.scala 419:77] + node _T_3537 = bits(_T_3536, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3538 = eq(btb_rd_addr_f, UInt<8>("h0c9")) @[ifu_bp_ctl.scala 419:77] + node _T_3539 = bits(_T_3538, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3540 = eq(btb_rd_addr_f, UInt<8>("h0ca")) @[ifu_bp_ctl.scala 419:77] + node _T_3541 = bits(_T_3540, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3542 = eq(btb_rd_addr_f, UInt<8>("h0cb")) @[ifu_bp_ctl.scala 419:77] + node _T_3543 = bits(_T_3542, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3544 = eq(btb_rd_addr_f, UInt<8>("h0cc")) @[ifu_bp_ctl.scala 419:77] + node _T_3545 = bits(_T_3544, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3546 = eq(btb_rd_addr_f, UInt<8>("h0cd")) @[ifu_bp_ctl.scala 419:77] + node _T_3547 = bits(_T_3546, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3548 = eq(btb_rd_addr_f, UInt<8>("h0ce")) @[ifu_bp_ctl.scala 419:77] + node _T_3549 = bits(_T_3548, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3550 = eq(btb_rd_addr_f, UInt<8>("h0cf")) @[ifu_bp_ctl.scala 419:77] + node _T_3551 = bits(_T_3550, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3552 = eq(btb_rd_addr_f, UInt<8>("h0d0")) @[ifu_bp_ctl.scala 419:77] + node _T_3553 = bits(_T_3552, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3554 = eq(btb_rd_addr_f, UInt<8>("h0d1")) @[ifu_bp_ctl.scala 419:77] + node _T_3555 = bits(_T_3554, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3556 = eq(btb_rd_addr_f, UInt<8>("h0d2")) @[ifu_bp_ctl.scala 419:77] + node _T_3557 = bits(_T_3556, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3558 = eq(btb_rd_addr_f, UInt<8>("h0d3")) @[ifu_bp_ctl.scala 419:77] + node _T_3559 = bits(_T_3558, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3560 = eq(btb_rd_addr_f, UInt<8>("h0d4")) @[ifu_bp_ctl.scala 419:77] + node _T_3561 = bits(_T_3560, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3562 = eq(btb_rd_addr_f, UInt<8>("h0d5")) @[ifu_bp_ctl.scala 419:77] + node _T_3563 = bits(_T_3562, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3564 = eq(btb_rd_addr_f, UInt<8>("h0d6")) @[ifu_bp_ctl.scala 419:77] + node _T_3565 = bits(_T_3564, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3566 = eq(btb_rd_addr_f, UInt<8>("h0d7")) @[ifu_bp_ctl.scala 419:77] + node _T_3567 = bits(_T_3566, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3568 = eq(btb_rd_addr_f, UInt<8>("h0d8")) @[ifu_bp_ctl.scala 419:77] + node _T_3569 = bits(_T_3568, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3570 = eq(btb_rd_addr_f, UInt<8>("h0d9")) @[ifu_bp_ctl.scala 419:77] + node _T_3571 = bits(_T_3570, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3572 = eq(btb_rd_addr_f, UInt<8>("h0da")) @[ifu_bp_ctl.scala 419:77] + node _T_3573 = bits(_T_3572, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3574 = eq(btb_rd_addr_f, UInt<8>("h0db")) @[ifu_bp_ctl.scala 419:77] + node _T_3575 = bits(_T_3574, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3576 = eq(btb_rd_addr_f, UInt<8>("h0dc")) @[ifu_bp_ctl.scala 419:77] + node _T_3577 = bits(_T_3576, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3578 = eq(btb_rd_addr_f, UInt<8>("h0dd")) @[ifu_bp_ctl.scala 419:77] + node _T_3579 = bits(_T_3578, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3580 = eq(btb_rd_addr_f, UInt<8>("h0de")) @[ifu_bp_ctl.scala 419:77] + node _T_3581 = bits(_T_3580, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3582 = eq(btb_rd_addr_f, UInt<8>("h0df")) @[ifu_bp_ctl.scala 419:77] + node _T_3583 = bits(_T_3582, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3584 = eq(btb_rd_addr_f, UInt<8>("h0e0")) @[ifu_bp_ctl.scala 419:77] + node _T_3585 = bits(_T_3584, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3586 = eq(btb_rd_addr_f, UInt<8>("h0e1")) @[ifu_bp_ctl.scala 419:77] + node _T_3587 = bits(_T_3586, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3588 = eq(btb_rd_addr_f, UInt<8>("h0e2")) @[ifu_bp_ctl.scala 419:77] + node _T_3589 = bits(_T_3588, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3590 = eq(btb_rd_addr_f, UInt<8>("h0e3")) @[ifu_bp_ctl.scala 419:77] + node _T_3591 = bits(_T_3590, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3592 = eq(btb_rd_addr_f, UInt<8>("h0e4")) @[ifu_bp_ctl.scala 419:77] + node _T_3593 = bits(_T_3592, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3594 = eq(btb_rd_addr_f, UInt<8>("h0e5")) @[ifu_bp_ctl.scala 419:77] + node _T_3595 = bits(_T_3594, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3596 = eq(btb_rd_addr_f, UInt<8>("h0e6")) @[ifu_bp_ctl.scala 419:77] + node _T_3597 = bits(_T_3596, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3598 = eq(btb_rd_addr_f, UInt<8>("h0e7")) @[ifu_bp_ctl.scala 419:77] + node _T_3599 = bits(_T_3598, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3600 = eq(btb_rd_addr_f, UInt<8>("h0e8")) @[ifu_bp_ctl.scala 419:77] + node _T_3601 = bits(_T_3600, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3602 = eq(btb_rd_addr_f, UInt<8>("h0e9")) @[ifu_bp_ctl.scala 419:77] + node _T_3603 = bits(_T_3602, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3604 = eq(btb_rd_addr_f, UInt<8>("h0ea")) @[ifu_bp_ctl.scala 419:77] + node _T_3605 = bits(_T_3604, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3606 = eq(btb_rd_addr_f, UInt<8>("h0eb")) @[ifu_bp_ctl.scala 419:77] + node _T_3607 = bits(_T_3606, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3608 = eq(btb_rd_addr_f, UInt<8>("h0ec")) @[ifu_bp_ctl.scala 419:77] + node _T_3609 = bits(_T_3608, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3610 = eq(btb_rd_addr_f, UInt<8>("h0ed")) @[ifu_bp_ctl.scala 419:77] + node _T_3611 = bits(_T_3610, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3612 = eq(btb_rd_addr_f, UInt<8>("h0ee")) @[ifu_bp_ctl.scala 419:77] + node _T_3613 = bits(_T_3612, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3614 = eq(btb_rd_addr_f, UInt<8>("h0ef")) @[ifu_bp_ctl.scala 419:77] + node _T_3615 = bits(_T_3614, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3616 = eq(btb_rd_addr_f, UInt<8>("h0f0")) @[ifu_bp_ctl.scala 419:77] + node _T_3617 = bits(_T_3616, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3618 = eq(btb_rd_addr_f, UInt<8>("h0f1")) @[ifu_bp_ctl.scala 419:77] + node _T_3619 = bits(_T_3618, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3620 = eq(btb_rd_addr_f, UInt<8>("h0f2")) @[ifu_bp_ctl.scala 419:77] + node _T_3621 = bits(_T_3620, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3622 = eq(btb_rd_addr_f, UInt<8>("h0f3")) @[ifu_bp_ctl.scala 419:77] + node _T_3623 = bits(_T_3622, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3624 = eq(btb_rd_addr_f, UInt<8>("h0f4")) @[ifu_bp_ctl.scala 419:77] + node _T_3625 = bits(_T_3624, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3626 = eq(btb_rd_addr_f, UInt<8>("h0f5")) @[ifu_bp_ctl.scala 419:77] + node _T_3627 = bits(_T_3626, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3628 = eq(btb_rd_addr_f, UInt<8>("h0f6")) @[ifu_bp_ctl.scala 419:77] + node _T_3629 = bits(_T_3628, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3630 = eq(btb_rd_addr_f, UInt<8>("h0f7")) @[ifu_bp_ctl.scala 419:77] + node _T_3631 = bits(_T_3630, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3632 = eq(btb_rd_addr_f, UInt<8>("h0f8")) @[ifu_bp_ctl.scala 419:77] + node _T_3633 = bits(_T_3632, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3634 = eq(btb_rd_addr_f, UInt<8>("h0f9")) @[ifu_bp_ctl.scala 419:77] + node _T_3635 = bits(_T_3634, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3636 = eq(btb_rd_addr_f, UInt<8>("h0fa")) @[ifu_bp_ctl.scala 419:77] + node _T_3637 = bits(_T_3636, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3638 = eq(btb_rd_addr_f, UInt<8>("h0fb")) @[ifu_bp_ctl.scala 419:77] + node _T_3639 = bits(_T_3638, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3640 = eq(btb_rd_addr_f, UInt<8>("h0fc")) @[ifu_bp_ctl.scala 419:77] + node _T_3641 = bits(_T_3640, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3642 = eq(btb_rd_addr_f, UInt<8>("h0fd")) @[ifu_bp_ctl.scala 419:77] + node _T_3643 = bits(_T_3642, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3644 = eq(btb_rd_addr_f, UInt<8>("h0fe")) @[ifu_bp_ctl.scala 419:77] + node _T_3645 = bits(_T_3644, 0, 0) @[ifu_bp_ctl.scala 419:85] + node _T_3646 = eq(btb_rd_addr_f, UInt<8>("h0ff")) @[ifu_bp_ctl.scala 419:77] + node _T_3647 = bits(_T_3646, 0, 0) @[ifu_bp_ctl.scala 419:85] node _T_3648 = mux(_T_3137, btb_bank0_rd_data_way1_out_0, UInt<1>("h00")) @[Mux.scala 27:72] node _T_3649 = mux(_T_3139, btb_bank0_rd_data_way1_out_1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_3650 = mux(_T_3141, btb_bank0_rd_data_way1_out_2, UInt<1>("h00")) @[Mux.scala 27:72] @@ -37645,519 +37645,519 @@ circuit quasar_wrapper : node _T_4158 = or(_T_4157, _T_3903) @[Mux.scala 27:72] wire _T_4159 : UInt @[Mux.scala 27:72] _T_4159 <= _T_4158 @[Mux.scala 27:72] - btb_bank0_rd_data_way1_f <= _T_4159 @[ifu_bp_ctl.scala 418:28] - node _T_4160 = eq(btb_rd_addr_p1_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 421:83] - node _T_4161 = bits(_T_4160, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4162 = eq(btb_rd_addr_p1_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 421:83] - node _T_4163 = bits(_T_4162, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4164 = eq(btb_rd_addr_p1_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 421:83] - node _T_4165 = bits(_T_4164, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4166 = eq(btb_rd_addr_p1_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 421:83] - node _T_4167 = bits(_T_4166, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4168 = eq(btb_rd_addr_p1_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 421:83] - node _T_4169 = bits(_T_4168, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4170 = eq(btb_rd_addr_p1_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 421:83] - node _T_4171 = bits(_T_4170, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4172 = eq(btb_rd_addr_p1_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 421:83] - node _T_4173 = bits(_T_4172, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4174 = eq(btb_rd_addr_p1_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 421:83] - node _T_4175 = bits(_T_4174, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4176 = eq(btb_rd_addr_p1_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 421:83] - node _T_4177 = bits(_T_4176, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4178 = eq(btb_rd_addr_p1_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 421:83] - node _T_4179 = bits(_T_4178, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4180 = eq(btb_rd_addr_p1_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 421:83] - node _T_4181 = bits(_T_4180, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4182 = eq(btb_rd_addr_p1_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 421:83] - node _T_4183 = bits(_T_4182, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4184 = eq(btb_rd_addr_p1_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 421:83] - node _T_4185 = bits(_T_4184, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4186 = eq(btb_rd_addr_p1_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 421:83] - node _T_4187 = bits(_T_4186, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4188 = eq(btb_rd_addr_p1_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 421:83] - node _T_4189 = bits(_T_4188, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4190 = eq(btb_rd_addr_p1_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 421:83] - node _T_4191 = bits(_T_4190, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4192 = eq(btb_rd_addr_p1_f, UInt<5>("h010")) @[ifu_bp_ctl.scala 421:83] - node _T_4193 = bits(_T_4192, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4194 = eq(btb_rd_addr_p1_f, UInt<5>("h011")) @[ifu_bp_ctl.scala 421:83] - node _T_4195 = bits(_T_4194, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4196 = eq(btb_rd_addr_p1_f, UInt<5>("h012")) @[ifu_bp_ctl.scala 421:83] - node _T_4197 = bits(_T_4196, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4198 = eq(btb_rd_addr_p1_f, UInt<5>("h013")) @[ifu_bp_ctl.scala 421:83] - node _T_4199 = bits(_T_4198, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4200 = eq(btb_rd_addr_p1_f, UInt<5>("h014")) @[ifu_bp_ctl.scala 421:83] - node _T_4201 = bits(_T_4200, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4202 = eq(btb_rd_addr_p1_f, UInt<5>("h015")) @[ifu_bp_ctl.scala 421:83] - node _T_4203 = bits(_T_4202, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4204 = eq(btb_rd_addr_p1_f, UInt<5>("h016")) @[ifu_bp_ctl.scala 421:83] - node _T_4205 = bits(_T_4204, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4206 = eq(btb_rd_addr_p1_f, UInt<5>("h017")) @[ifu_bp_ctl.scala 421:83] - node _T_4207 = bits(_T_4206, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4208 = eq(btb_rd_addr_p1_f, UInt<5>("h018")) @[ifu_bp_ctl.scala 421:83] - node _T_4209 = bits(_T_4208, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4210 = eq(btb_rd_addr_p1_f, UInt<5>("h019")) @[ifu_bp_ctl.scala 421:83] - node _T_4211 = bits(_T_4210, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4212 = eq(btb_rd_addr_p1_f, UInt<5>("h01a")) @[ifu_bp_ctl.scala 421:83] - node _T_4213 = bits(_T_4212, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4214 = eq(btb_rd_addr_p1_f, UInt<5>("h01b")) @[ifu_bp_ctl.scala 421:83] - node _T_4215 = bits(_T_4214, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4216 = eq(btb_rd_addr_p1_f, UInt<5>("h01c")) @[ifu_bp_ctl.scala 421:83] - node _T_4217 = bits(_T_4216, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4218 = eq(btb_rd_addr_p1_f, UInt<5>("h01d")) @[ifu_bp_ctl.scala 421:83] - node _T_4219 = bits(_T_4218, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4220 = eq(btb_rd_addr_p1_f, UInt<5>("h01e")) @[ifu_bp_ctl.scala 421:83] - node _T_4221 = bits(_T_4220, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4222 = eq(btb_rd_addr_p1_f, UInt<5>("h01f")) @[ifu_bp_ctl.scala 421:83] - node _T_4223 = bits(_T_4222, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4224 = eq(btb_rd_addr_p1_f, UInt<6>("h020")) @[ifu_bp_ctl.scala 421:83] - node _T_4225 = bits(_T_4224, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4226 = eq(btb_rd_addr_p1_f, UInt<6>("h021")) @[ifu_bp_ctl.scala 421:83] - node _T_4227 = bits(_T_4226, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4228 = eq(btb_rd_addr_p1_f, UInt<6>("h022")) @[ifu_bp_ctl.scala 421:83] - node _T_4229 = bits(_T_4228, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4230 = eq(btb_rd_addr_p1_f, UInt<6>("h023")) @[ifu_bp_ctl.scala 421:83] - node _T_4231 = bits(_T_4230, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4232 = eq(btb_rd_addr_p1_f, UInt<6>("h024")) @[ifu_bp_ctl.scala 421:83] - node _T_4233 = bits(_T_4232, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4234 = eq(btb_rd_addr_p1_f, UInt<6>("h025")) @[ifu_bp_ctl.scala 421:83] - node _T_4235 = bits(_T_4234, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4236 = eq(btb_rd_addr_p1_f, UInt<6>("h026")) @[ifu_bp_ctl.scala 421:83] - node _T_4237 = bits(_T_4236, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4238 = eq(btb_rd_addr_p1_f, UInt<6>("h027")) @[ifu_bp_ctl.scala 421:83] - node _T_4239 = bits(_T_4238, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4240 = eq(btb_rd_addr_p1_f, UInt<6>("h028")) @[ifu_bp_ctl.scala 421:83] - node _T_4241 = bits(_T_4240, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4242 = eq(btb_rd_addr_p1_f, UInt<6>("h029")) @[ifu_bp_ctl.scala 421:83] - node _T_4243 = bits(_T_4242, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4244 = eq(btb_rd_addr_p1_f, UInt<6>("h02a")) @[ifu_bp_ctl.scala 421:83] - node _T_4245 = bits(_T_4244, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4246 = eq(btb_rd_addr_p1_f, UInt<6>("h02b")) @[ifu_bp_ctl.scala 421:83] - node _T_4247 = bits(_T_4246, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4248 = eq(btb_rd_addr_p1_f, UInt<6>("h02c")) @[ifu_bp_ctl.scala 421:83] - node _T_4249 = bits(_T_4248, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4250 = eq(btb_rd_addr_p1_f, UInt<6>("h02d")) @[ifu_bp_ctl.scala 421:83] - node _T_4251 = bits(_T_4250, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4252 = eq(btb_rd_addr_p1_f, UInt<6>("h02e")) @[ifu_bp_ctl.scala 421:83] - node _T_4253 = bits(_T_4252, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4254 = eq(btb_rd_addr_p1_f, UInt<6>("h02f")) @[ifu_bp_ctl.scala 421:83] - node _T_4255 = bits(_T_4254, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4256 = eq(btb_rd_addr_p1_f, UInt<6>("h030")) @[ifu_bp_ctl.scala 421:83] - node _T_4257 = bits(_T_4256, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4258 = eq(btb_rd_addr_p1_f, UInt<6>("h031")) @[ifu_bp_ctl.scala 421:83] - node _T_4259 = bits(_T_4258, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4260 = eq(btb_rd_addr_p1_f, UInt<6>("h032")) @[ifu_bp_ctl.scala 421:83] - node _T_4261 = bits(_T_4260, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4262 = eq(btb_rd_addr_p1_f, UInt<6>("h033")) @[ifu_bp_ctl.scala 421:83] - node _T_4263 = bits(_T_4262, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4264 = eq(btb_rd_addr_p1_f, UInt<6>("h034")) @[ifu_bp_ctl.scala 421:83] - node _T_4265 = bits(_T_4264, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4266 = eq(btb_rd_addr_p1_f, UInt<6>("h035")) @[ifu_bp_ctl.scala 421:83] - node _T_4267 = bits(_T_4266, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4268 = eq(btb_rd_addr_p1_f, UInt<6>("h036")) @[ifu_bp_ctl.scala 421:83] - node _T_4269 = bits(_T_4268, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4270 = eq(btb_rd_addr_p1_f, UInt<6>("h037")) @[ifu_bp_ctl.scala 421:83] - node _T_4271 = bits(_T_4270, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4272 = eq(btb_rd_addr_p1_f, UInt<6>("h038")) @[ifu_bp_ctl.scala 421:83] - node _T_4273 = bits(_T_4272, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4274 = eq(btb_rd_addr_p1_f, UInt<6>("h039")) @[ifu_bp_ctl.scala 421:83] - node _T_4275 = bits(_T_4274, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4276 = eq(btb_rd_addr_p1_f, UInt<6>("h03a")) @[ifu_bp_ctl.scala 421:83] - node _T_4277 = bits(_T_4276, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4278 = eq(btb_rd_addr_p1_f, UInt<6>("h03b")) @[ifu_bp_ctl.scala 421:83] - node _T_4279 = bits(_T_4278, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4280 = eq(btb_rd_addr_p1_f, UInt<6>("h03c")) @[ifu_bp_ctl.scala 421:83] - node _T_4281 = bits(_T_4280, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4282 = eq(btb_rd_addr_p1_f, UInt<6>("h03d")) @[ifu_bp_ctl.scala 421:83] - node _T_4283 = bits(_T_4282, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4284 = eq(btb_rd_addr_p1_f, UInt<6>("h03e")) @[ifu_bp_ctl.scala 421:83] - node _T_4285 = bits(_T_4284, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4286 = eq(btb_rd_addr_p1_f, UInt<6>("h03f")) @[ifu_bp_ctl.scala 421:83] - node _T_4287 = bits(_T_4286, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4288 = eq(btb_rd_addr_p1_f, UInt<7>("h040")) @[ifu_bp_ctl.scala 421:83] - node _T_4289 = bits(_T_4288, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4290 = eq(btb_rd_addr_p1_f, UInt<7>("h041")) @[ifu_bp_ctl.scala 421:83] - node _T_4291 = bits(_T_4290, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4292 = eq(btb_rd_addr_p1_f, UInt<7>("h042")) @[ifu_bp_ctl.scala 421:83] - node _T_4293 = bits(_T_4292, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4294 = eq(btb_rd_addr_p1_f, UInt<7>("h043")) @[ifu_bp_ctl.scala 421:83] - node _T_4295 = bits(_T_4294, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4296 = eq(btb_rd_addr_p1_f, UInt<7>("h044")) @[ifu_bp_ctl.scala 421:83] - node _T_4297 = bits(_T_4296, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4298 = eq(btb_rd_addr_p1_f, UInt<7>("h045")) @[ifu_bp_ctl.scala 421:83] - node _T_4299 = bits(_T_4298, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4300 = eq(btb_rd_addr_p1_f, UInt<7>("h046")) @[ifu_bp_ctl.scala 421:83] - node _T_4301 = bits(_T_4300, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4302 = eq(btb_rd_addr_p1_f, UInt<7>("h047")) @[ifu_bp_ctl.scala 421:83] - node _T_4303 = bits(_T_4302, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4304 = eq(btb_rd_addr_p1_f, UInt<7>("h048")) @[ifu_bp_ctl.scala 421:83] - node _T_4305 = bits(_T_4304, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4306 = eq(btb_rd_addr_p1_f, UInt<7>("h049")) @[ifu_bp_ctl.scala 421:83] - node _T_4307 = bits(_T_4306, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4308 = eq(btb_rd_addr_p1_f, UInt<7>("h04a")) @[ifu_bp_ctl.scala 421:83] - node _T_4309 = bits(_T_4308, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4310 = eq(btb_rd_addr_p1_f, UInt<7>("h04b")) @[ifu_bp_ctl.scala 421:83] - node _T_4311 = bits(_T_4310, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4312 = eq(btb_rd_addr_p1_f, UInt<7>("h04c")) @[ifu_bp_ctl.scala 421:83] - node _T_4313 = bits(_T_4312, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4314 = eq(btb_rd_addr_p1_f, UInt<7>("h04d")) @[ifu_bp_ctl.scala 421:83] - node _T_4315 = bits(_T_4314, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4316 = eq(btb_rd_addr_p1_f, UInt<7>("h04e")) @[ifu_bp_ctl.scala 421:83] - node _T_4317 = bits(_T_4316, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4318 = eq(btb_rd_addr_p1_f, UInt<7>("h04f")) @[ifu_bp_ctl.scala 421:83] - node _T_4319 = bits(_T_4318, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4320 = eq(btb_rd_addr_p1_f, UInt<7>("h050")) @[ifu_bp_ctl.scala 421:83] - node _T_4321 = bits(_T_4320, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4322 = eq(btb_rd_addr_p1_f, UInt<7>("h051")) @[ifu_bp_ctl.scala 421:83] - node _T_4323 = bits(_T_4322, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4324 = eq(btb_rd_addr_p1_f, UInt<7>("h052")) @[ifu_bp_ctl.scala 421:83] - node _T_4325 = bits(_T_4324, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4326 = eq(btb_rd_addr_p1_f, UInt<7>("h053")) @[ifu_bp_ctl.scala 421:83] - node _T_4327 = bits(_T_4326, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4328 = eq(btb_rd_addr_p1_f, UInt<7>("h054")) @[ifu_bp_ctl.scala 421:83] - node _T_4329 = bits(_T_4328, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4330 = eq(btb_rd_addr_p1_f, UInt<7>("h055")) @[ifu_bp_ctl.scala 421:83] - node _T_4331 = bits(_T_4330, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4332 = eq(btb_rd_addr_p1_f, UInt<7>("h056")) @[ifu_bp_ctl.scala 421:83] - node _T_4333 = bits(_T_4332, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4334 = eq(btb_rd_addr_p1_f, UInt<7>("h057")) @[ifu_bp_ctl.scala 421:83] - node _T_4335 = bits(_T_4334, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4336 = eq(btb_rd_addr_p1_f, UInt<7>("h058")) @[ifu_bp_ctl.scala 421:83] - node _T_4337 = bits(_T_4336, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4338 = eq(btb_rd_addr_p1_f, UInt<7>("h059")) @[ifu_bp_ctl.scala 421:83] - node _T_4339 = bits(_T_4338, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4340 = eq(btb_rd_addr_p1_f, UInt<7>("h05a")) @[ifu_bp_ctl.scala 421:83] - node _T_4341 = bits(_T_4340, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4342 = eq(btb_rd_addr_p1_f, UInt<7>("h05b")) @[ifu_bp_ctl.scala 421:83] - node _T_4343 = bits(_T_4342, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4344 = eq(btb_rd_addr_p1_f, UInt<7>("h05c")) @[ifu_bp_ctl.scala 421:83] - node _T_4345 = bits(_T_4344, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4346 = eq(btb_rd_addr_p1_f, UInt<7>("h05d")) @[ifu_bp_ctl.scala 421:83] - node _T_4347 = bits(_T_4346, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4348 = eq(btb_rd_addr_p1_f, UInt<7>("h05e")) @[ifu_bp_ctl.scala 421:83] - node _T_4349 = bits(_T_4348, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4350 = eq(btb_rd_addr_p1_f, UInt<7>("h05f")) @[ifu_bp_ctl.scala 421:83] - node _T_4351 = bits(_T_4350, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4352 = eq(btb_rd_addr_p1_f, UInt<7>("h060")) @[ifu_bp_ctl.scala 421:83] - node _T_4353 = bits(_T_4352, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4354 = eq(btb_rd_addr_p1_f, UInt<7>("h061")) @[ifu_bp_ctl.scala 421:83] - node _T_4355 = bits(_T_4354, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4356 = eq(btb_rd_addr_p1_f, UInt<7>("h062")) @[ifu_bp_ctl.scala 421:83] - node _T_4357 = bits(_T_4356, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4358 = eq(btb_rd_addr_p1_f, UInt<7>("h063")) @[ifu_bp_ctl.scala 421:83] - node _T_4359 = bits(_T_4358, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4360 = eq(btb_rd_addr_p1_f, UInt<7>("h064")) @[ifu_bp_ctl.scala 421:83] - node _T_4361 = bits(_T_4360, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4362 = eq(btb_rd_addr_p1_f, UInt<7>("h065")) @[ifu_bp_ctl.scala 421:83] - node _T_4363 = bits(_T_4362, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4364 = eq(btb_rd_addr_p1_f, UInt<7>("h066")) @[ifu_bp_ctl.scala 421:83] - node _T_4365 = bits(_T_4364, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4366 = eq(btb_rd_addr_p1_f, UInt<7>("h067")) @[ifu_bp_ctl.scala 421:83] - node _T_4367 = bits(_T_4366, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4368 = eq(btb_rd_addr_p1_f, UInt<7>("h068")) @[ifu_bp_ctl.scala 421:83] - node _T_4369 = bits(_T_4368, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4370 = eq(btb_rd_addr_p1_f, UInt<7>("h069")) @[ifu_bp_ctl.scala 421:83] - node _T_4371 = bits(_T_4370, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4372 = eq(btb_rd_addr_p1_f, UInt<7>("h06a")) @[ifu_bp_ctl.scala 421:83] - node _T_4373 = bits(_T_4372, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4374 = eq(btb_rd_addr_p1_f, UInt<7>("h06b")) @[ifu_bp_ctl.scala 421:83] - node _T_4375 = bits(_T_4374, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4376 = eq(btb_rd_addr_p1_f, UInt<7>("h06c")) @[ifu_bp_ctl.scala 421:83] - node _T_4377 = bits(_T_4376, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4378 = eq(btb_rd_addr_p1_f, UInt<7>("h06d")) @[ifu_bp_ctl.scala 421:83] - node _T_4379 = bits(_T_4378, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4380 = eq(btb_rd_addr_p1_f, UInt<7>("h06e")) @[ifu_bp_ctl.scala 421:83] - node _T_4381 = bits(_T_4380, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4382 = eq(btb_rd_addr_p1_f, UInt<7>("h06f")) @[ifu_bp_ctl.scala 421:83] - node _T_4383 = bits(_T_4382, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4384 = eq(btb_rd_addr_p1_f, UInt<7>("h070")) @[ifu_bp_ctl.scala 421:83] - node _T_4385 = bits(_T_4384, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4386 = eq(btb_rd_addr_p1_f, UInt<7>("h071")) @[ifu_bp_ctl.scala 421:83] - node _T_4387 = bits(_T_4386, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4388 = eq(btb_rd_addr_p1_f, UInt<7>("h072")) @[ifu_bp_ctl.scala 421:83] - node _T_4389 = bits(_T_4388, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4390 = eq(btb_rd_addr_p1_f, UInt<7>("h073")) @[ifu_bp_ctl.scala 421:83] - node _T_4391 = bits(_T_4390, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4392 = eq(btb_rd_addr_p1_f, UInt<7>("h074")) @[ifu_bp_ctl.scala 421:83] - node _T_4393 = bits(_T_4392, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4394 = eq(btb_rd_addr_p1_f, UInt<7>("h075")) @[ifu_bp_ctl.scala 421:83] - node _T_4395 = bits(_T_4394, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4396 = eq(btb_rd_addr_p1_f, UInt<7>("h076")) @[ifu_bp_ctl.scala 421:83] - node _T_4397 = bits(_T_4396, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4398 = eq(btb_rd_addr_p1_f, UInt<7>("h077")) @[ifu_bp_ctl.scala 421:83] - node _T_4399 = bits(_T_4398, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4400 = eq(btb_rd_addr_p1_f, UInt<7>("h078")) @[ifu_bp_ctl.scala 421:83] - node _T_4401 = bits(_T_4400, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4402 = eq(btb_rd_addr_p1_f, UInt<7>("h079")) @[ifu_bp_ctl.scala 421:83] - node _T_4403 = bits(_T_4402, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4404 = eq(btb_rd_addr_p1_f, UInt<7>("h07a")) @[ifu_bp_ctl.scala 421:83] - node _T_4405 = bits(_T_4404, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4406 = eq(btb_rd_addr_p1_f, UInt<7>("h07b")) @[ifu_bp_ctl.scala 421:83] - node _T_4407 = bits(_T_4406, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4408 = eq(btb_rd_addr_p1_f, UInt<7>("h07c")) @[ifu_bp_ctl.scala 421:83] - node _T_4409 = bits(_T_4408, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4410 = eq(btb_rd_addr_p1_f, UInt<7>("h07d")) @[ifu_bp_ctl.scala 421:83] - node _T_4411 = bits(_T_4410, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4412 = eq(btb_rd_addr_p1_f, UInt<7>("h07e")) @[ifu_bp_ctl.scala 421:83] - node _T_4413 = bits(_T_4412, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4414 = eq(btb_rd_addr_p1_f, UInt<7>("h07f")) @[ifu_bp_ctl.scala 421:83] - node _T_4415 = bits(_T_4414, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4416 = eq(btb_rd_addr_p1_f, UInt<8>("h080")) @[ifu_bp_ctl.scala 421:83] - node _T_4417 = bits(_T_4416, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4418 = eq(btb_rd_addr_p1_f, UInt<8>("h081")) @[ifu_bp_ctl.scala 421:83] - node _T_4419 = bits(_T_4418, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4420 = eq(btb_rd_addr_p1_f, UInt<8>("h082")) @[ifu_bp_ctl.scala 421:83] - node _T_4421 = bits(_T_4420, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4422 = eq(btb_rd_addr_p1_f, UInt<8>("h083")) @[ifu_bp_ctl.scala 421:83] - node _T_4423 = bits(_T_4422, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4424 = eq(btb_rd_addr_p1_f, UInt<8>("h084")) @[ifu_bp_ctl.scala 421:83] - node _T_4425 = bits(_T_4424, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4426 = eq(btb_rd_addr_p1_f, UInt<8>("h085")) @[ifu_bp_ctl.scala 421:83] - node _T_4427 = bits(_T_4426, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4428 = eq(btb_rd_addr_p1_f, UInt<8>("h086")) @[ifu_bp_ctl.scala 421:83] - node _T_4429 = bits(_T_4428, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4430 = eq(btb_rd_addr_p1_f, UInt<8>("h087")) @[ifu_bp_ctl.scala 421:83] - node _T_4431 = bits(_T_4430, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4432 = eq(btb_rd_addr_p1_f, UInt<8>("h088")) @[ifu_bp_ctl.scala 421:83] - node _T_4433 = bits(_T_4432, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4434 = eq(btb_rd_addr_p1_f, UInt<8>("h089")) @[ifu_bp_ctl.scala 421:83] - node _T_4435 = bits(_T_4434, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4436 = eq(btb_rd_addr_p1_f, UInt<8>("h08a")) @[ifu_bp_ctl.scala 421:83] - node _T_4437 = bits(_T_4436, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4438 = eq(btb_rd_addr_p1_f, UInt<8>("h08b")) @[ifu_bp_ctl.scala 421:83] - node _T_4439 = bits(_T_4438, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4440 = eq(btb_rd_addr_p1_f, UInt<8>("h08c")) @[ifu_bp_ctl.scala 421:83] - node _T_4441 = bits(_T_4440, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4442 = eq(btb_rd_addr_p1_f, UInt<8>("h08d")) @[ifu_bp_ctl.scala 421:83] - node _T_4443 = bits(_T_4442, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4444 = eq(btb_rd_addr_p1_f, UInt<8>("h08e")) @[ifu_bp_ctl.scala 421:83] - node _T_4445 = bits(_T_4444, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4446 = eq(btb_rd_addr_p1_f, UInt<8>("h08f")) @[ifu_bp_ctl.scala 421:83] - node _T_4447 = bits(_T_4446, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4448 = eq(btb_rd_addr_p1_f, UInt<8>("h090")) @[ifu_bp_ctl.scala 421:83] - node _T_4449 = bits(_T_4448, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4450 = eq(btb_rd_addr_p1_f, UInt<8>("h091")) @[ifu_bp_ctl.scala 421:83] - node _T_4451 = bits(_T_4450, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4452 = eq(btb_rd_addr_p1_f, UInt<8>("h092")) @[ifu_bp_ctl.scala 421:83] - node _T_4453 = bits(_T_4452, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4454 = eq(btb_rd_addr_p1_f, UInt<8>("h093")) @[ifu_bp_ctl.scala 421:83] - node _T_4455 = bits(_T_4454, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4456 = eq(btb_rd_addr_p1_f, UInt<8>("h094")) @[ifu_bp_ctl.scala 421:83] - node _T_4457 = bits(_T_4456, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4458 = eq(btb_rd_addr_p1_f, UInt<8>("h095")) @[ifu_bp_ctl.scala 421:83] - node _T_4459 = bits(_T_4458, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4460 = eq(btb_rd_addr_p1_f, UInt<8>("h096")) @[ifu_bp_ctl.scala 421:83] - node _T_4461 = bits(_T_4460, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4462 = eq(btb_rd_addr_p1_f, UInt<8>("h097")) @[ifu_bp_ctl.scala 421:83] - node _T_4463 = bits(_T_4462, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4464 = eq(btb_rd_addr_p1_f, UInt<8>("h098")) @[ifu_bp_ctl.scala 421:83] - node _T_4465 = bits(_T_4464, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4466 = eq(btb_rd_addr_p1_f, UInt<8>("h099")) @[ifu_bp_ctl.scala 421:83] - node _T_4467 = bits(_T_4466, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4468 = eq(btb_rd_addr_p1_f, UInt<8>("h09a")) @[ifu_bp_ctl.scala 421:83] - node _T_4469 = bits(_T_4468, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4470 = eq(btb_rd_addr_p1_f, UInt<8>("h09b")) @[ifu_bp_ctl.scala 421:83] - node _T_4471 = bits(_T_4470, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4472 = eq(btb_rd_addr_p1_f, UInt<8>("h09c")) @[ifu_bp_ctl.scala 421:83] - node _T_4473 = bits(_T_4472, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4474 = eq(btb_rd_addr_p1_f, UInt<8>("h09d")) @[ifu_bp_ctl.scala 421:83] - node _T_4475 = bits(_T_4474, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4476 = eq(btb_rd_addr_p1_f, UInt<8>("h09e")) @[ifu_bp_ctl.scala 421:83] - node _T_4477 = bits(_T_4476, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4478 = eq(btb_rd_addr_p1_f, UInt<8>("h09f")) @[ifu_bp_ctl.scala 421:83] - node _T_4479 = bits(_T_4478, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4480 = eq(btb_rd_addr_p1_f, UInt<8>("h0a0")) @[ifu_bp_ctl.scala 421:83] - node _T_4481 = bits(_T_4480, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4482 = eq(btb_rd_addr_p1_f, UInt<8>("h0a1")) @[ifu_bp_ctl.scala 421:83] - node _T_4483 = bits(_T_4482, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4484 = eq(btb_rd_addr_p1_f, UInt<8>("h0a2")) @[ifu_bp_ctl.scala 421:83] - node _T_4485 = bits(_T_4484, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4486 = eq(btb_rd_addr_p1_f, UInt<8>("h0a3")) @[ifu_bp_ctl.scala 421:83] - node _T_4487 = bits(_T_4486, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4488 = eq(btb_rd_addr_p1_f, UInt<8>("h0a4")) @[ifu_bp_ctl.scala 421:83] - node _T_4489 = bits(_T_4488, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4490 = eq(btb_rd_addr_p1_f, UInt<8>("h0a5")) @[ifu_bp_ctl.scala 421:83] - node _T_4491 = bits(_T_4490, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4492 = eq(btb_rd_addr_p1_f, UInt<8>("h0a6")) @[ifu_bp_ctl.scala 421:83] - node _T_4493 = bits(_T_4492, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4494 = eq(btb_rd_addr_p1_f, UInt<8>("h0a7")) @[ifu_bp_ctl.scala 421:83] - node _T_4495 = bits(_T_4494, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4496 = eq(btb_rd_addr_p1_f, UInt<8>("h0a8")) @[ifu_bp_ctl.scala 421:83] - node _T_4497 = bits(_T_4496, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4498 = eq(btb_rd_addr_p1_f, UInt<8>("h0a9")) @[ifu_bp_ctl.scala 421:83] - node _T_4499 = bits(_T_4498, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4500 = eq(btb_rd_addr_p1_f, UInt<8>("h0aa")) @[ifu_bp_ctl.scala 421:83] - node _T_4501 = bits(_T_4500, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4502 = eq(btb_rd_addr_p1_f, UInt<8>("h0ab")) @[ifu_bp_ctl.scala 421:83] - node _T_4503 = bits(_T_4502, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4504 = eq(btb_rd_addr_p1_f, UInt<8>("h0ac")) @[ifu_bp_ctl.scala 421:83] - node _T_4505 = bits(_T_4504, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4506 = eq(btb_rd_addr_p1_f, UInt<8>("h0ad")) @[ifu_bp_ctl.scala 421:83] - node _T_4507 = bits(_T_4506, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4508 = eq(btb_rd_addr_p1_f, UInt<8>("h0ae")) @[ifu_bp_ctl.scala 421:83] - node _T_4509 = bits(_T_4508, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4510 = eq(btb_rd_addr_p1_f, UInt<8>("h0af")) @[ifu_bp_ctl.scala 421:83] - node _T_4511 = bits(_T_4510, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4512 = eq(btb_rd_addr_p1_f, UInt<8>("h0b0")) @[ifu_bp_ctl.scala 421:83] - node _T_4513 = bits(_T_4512, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4514 = eq(btb_rd_addr_p1_f, UInt<8>("h0b1")) @[ifu_bp_ctl.scala 421:83] - node _T_4515 = bits(_T_4514, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4516 = eq(btb_rd_addr_p1_f, UInt<8>("h0b2")) @[ifu_bp_ctl.scala 421:83] - node _T_4517 = bits(_T_4516, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4518 = eq(btb_rd_addr_p1_f, UInt<8>("h0b3")) @[ifu_bp_ctl.scala 421:83] - node _T_4519 = bits(_T_4518, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4520 = eq(btb_rd_addr_p1_f, UInt<8>("h0b4")) @[ifu_bp_ctl.scala 421:83] - node _T_4521 = bits(_T_4520, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4522 = eq(btb_rd_addr_p1_f, UInt<8>("h0b5")) @[ifu_bp_ctl.scala 421:83] - node _T_4523 = bits(_T_4522, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4524 = eq(btb_rd_addr_p1_f, UInt<8>("h0b6")) @[ifu_bp_ctl.scala 421:83] - node _T_4525 = bits(_T_4524, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4526 = eq(btb_rd_addr_p1_f, UInt<8>("h0b7")) @[ifu_bp_ctl.scala 421:83] - node _T_4527 = bits(_T_4526, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4528 = eq(btb_rd_addr_p1_f, UInt<8>("h0b8")) @[ifu_bp_ctl.scala 421:83] - node _T_4529 = bits(_T_4528, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4530 = eq(btb_rd_addr_p1_f, UInt<8>("h0b9")) @[ifu_bp_ctl.scala 421:83] - node _T_4531 = bits(_T_4530, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4532 = eq(btb_rd_addr_p1_f, UInt<8>("h0ba")) @[ifu_bp_ctl.scala 421:83] - node _T_4533 = bits(_T_4532, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4534 = eq(btb_rd_addr_p1_f, UInt<8>("h0bb")) @[ifu_bp_ctl.scala 421:83] - node _T_4535 = bits(_T_4534, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4536 = eq(btb_rd_addr_p1_f, UInt<8>("h0bc")) @[ifu_bp_ctl.scala 421:83] - node _T_4537 = bits(_T_4536, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4538 = eq(btb_rd_addr_p1_f, UInt<8>("h0bd")) @[ifu_bp_ctl.scala 421:83] - node _T_4539 = bits(_T_4538, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4540 = eq(btb_rd_addr_p1_f, UInt<8>("h0be")) @[ifu_bp_ctl.scala 421:83] - node _T_4541 = bits(_T_4540, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4542 = eq(btb_rd_addr_p1_f, UInt<8>("h0bf")) @[ifu_bp_ctl.scala 421:83] - node _T_4543 = bits(_T_4542, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4544 = eq(btb_rd_addr_p1_f, UInt<8>("h0c0")) @[ifu_bp_ctl.scala 421:83] - node _T_4545 = bits(_T_4544, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4546 = eq(btb_rd_addr_p1_f, UInt<8>("h0c1")) @[ifu_bp_ctl.scala 421:83] - node _T_4547 = bits(_T_4546, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4548 = eq(btb_rd_addr_p1_f, UInt<8>("h0c2")) @[ifu_bp_ctl.scala 421:83] - node _T_4549 = bits(_T_4548, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4550 = eq(btb_rd_addr_p1_f, UInt<8>("h0c3")) @[ifu_bp_ctl.scala 421:83] - node _T_4551 = bits(_T_4550, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4552 = eq(btb_rd_addr_p1_f, UInt<8>("h0c4")) @[ifu_bp_ctl.scala 421:83] - node _T_4553 = bits(_T_4552, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4554 = eq(btb_rd_addr_p1_f, UInt<8>("h0c5")) @[ifu_bp_ctl.scala 421:83] - node _T_4555 = bits(_T_4554, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4556 = eq(btb_rd_addr_p1_f, UInt<8>("h0c6")) @[ifu_bp_ctl.scala 421:83] - node _T_4557 = bits(_T_4556, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4558 = eq(btb_rd_addr_p1_f, UInt<8>("h0c7")) @[ifu_bp_ctl.scala 421:83] - node _T_4559 = bits(_T_4558, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4560 = eq(btb_rd_addr_p1_f, UInt<8>("h0c8")) @[ifu_bp_ctl.scala 421:83] - node _T_4561 = bits(_T_4560, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4562 = eq(btb_rd_addr_p1_f, UInt<8>("h0c9")) @[ifu_bp_ctl.scala 421:83] - node _T_4563 = bits(_T_4562, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4564 = eq(btb_rd_addr_p1_f, UInt<8>("h0ca")) @[ifu_bp_ctl.scala 421:83] - node _T_4565 = bits(_T_4564, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4566 = eq(btb_rd_addr_p1_f, UInt<8>("h0cb")) @[ifu_bp_ctl.scala 421:83] - node _T_4567 = bits(_T_4566, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4568 = eq(btb_rd_addr_p1_f, UInt<8>("h0cc")) @[ifu_bp_ctl.scala 421:83] - node _T_4569 = bits(_T_4568, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4570 = eq(btb_rd_addr_p1_f, UInt<8>("h0cd")) @[ifu_bp_ctl.scala 421:83] - node _T_4571 = bits(_T_4570, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4572 = eq(btb_rd_addr_p1_f, UInt<8>("h0ce")) @[ifu_bp_ctl.scala 421:83] - node _T_4573 = bits(_T_4572, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4574 = eq(btb_rd_addr_p1_f, UInt<8>("h0cf")) @[ifu_bp_ctl.scala 421:83] - node _T_4575 = bits(_T_4574, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4576 = eq(btb_rd_addr_p1_f, UInt<8>("h0d0")) @[ifu_bp_ctl.scala 421:83] - node _T_4577 = bits(_T_4576, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4578 = eq(btb_rd_addr_p1_f, UInt<8>("h0d1")) @[ifu_bp_ctl.scala 421:83] - node _T_4579 = bits(_T_4578, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4580 = eq(btb_rd_addr_p1_f, UInt<8>("h0d2")) @[ifu_bp_ctl.scala 421:83] - node _T_4581 = bits(_T_4580, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4582 = eq(btb_rd_addr_p1_f, UInt<8>("h0d3")) @[ifu_bp_ctl.scala 421:83] - node _T_4583 = bits(_T_4582, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4584 = eq(btb_rd_addr_p1_f, UInt<8>("h0d4")) @[ifu_bp_ctl.scala 421:83] - node _T_4585 = bits(_T_4584, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4586 = eq(btb_rd_addr_p1_f, UInt<8>("h0d5")) @[ifu_bp_ctl.scala 421:83] - node _T_4587 = bits(_T_4586, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4588 = eq(btb_rd_addr_p1_f, UInt<8>("h0d6")) @[ifu_bp_ctl.scala 421:83] - node _T_4589 = bits(_T_4588, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4590 = eq(btb_rd_addr_p1_f, UInt<8>("h0d7")) @[ifu_bp_ctl.scala 421:83] - node _T_4591 = bits(_T_4590, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4592 = eq(btb_rd_addr_p1_f, UInt<8>("h0d8")) @[ifu_bp_ctl.scala 421:83] - node _T_4593 = bits(_T_4592, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4594 = eq(btb_rd_addr_p1_f, UInt<8>("h0d9")) @[ifu_bp_ctl.scala 421:83] - node _T_4595 = bits(_T_4594, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4596 = eq(btb_rd_addr_p1_f, UInt<8>("h0da")) @[ifu_bp_ctl.scala 421:83] - node _T_4597 = bits(_T_4596, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4598 = eq(btb_rd_addr_p1_f, UInt<8>("h0db")) @[ifu_bp_ctl.scala 421:83] - node _T_4599 = bits(_T_4598, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4600 = eq(btb_rd_addr_p1_f, UInt<8>("h0dc")) @[ifu_bp_ctl.scala 421:83] - node _T_4601 = bits(_T_4600, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4602 = eq(btb_rd_addr_p1_f, UInt<8>("h0dd")) @[ifu_bp_ctl.scala 421:83] - node _T_4603 = bits(_T_4602, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4604 = eq(btb_rd_addr_p1_f, UInt<8>("h0de")) @[ifu_bp_ctl.scala 421:83] - node _T_4605 = bits(_T_4604, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4606 = eq(btb_rd_addr_p1_f, UInt<8>("h0df")) @[ifu_bp_ctl.scala 421:83] - node _T_4607 = bits(_T_4606, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4608 = eq(btb_rd_addr_p1_f, UInt<8>("h0e0")) @[ifu_bp_ctl.scala 421:83] - node _T_4609 = bits(_T_4608, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4610 = eq(btb_rd_addr_p1_f, UInt<8>("h0e1")) @[ifu_bp_ctl.scala 421:83] - node _T_4611 = bits(_T_4610, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4612 = eq(btb_rd_addr_p1_f, UInt<8>("h0e2")) @[ifu_bp_ctl.scala 421:83] - node _T_4613 = bits(_T_4612, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4614 = eq(btb_rd_addr_p1_f, UInt<8>("h0e3")) @[ifu_bp_ctl.scala 421:83] - node _T_4615 = bits(_T_4614, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4616 = eq(btb_rd_addr_p1_f, UInt<8>("h0e4")) @[ifu_bp_ctl.scala 421:83] - node _T_4617 = bits(_T_4616, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4618 = eq(btb_rd_addr_p1_f, UInt<8>("h0e5")) @[ifu_bp_ctl.scala 421:83] - node _T_4619 = bits(_T_4618, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4620 = eq(btb_rd_addr_p1_f, UInt<8>("h0e6")) @[ifu_bp_ctl.scala 421:83] - node _T_4621 = bits(_T_4620, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4622 = eq(btb_rd_addr_p1_f, UInt<8>("h0e7")) @[ifu_bp_ctl.scala 421:83] - node _T_4623 = bits(_T_4622, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4624 = eq(btb_rd_addr_p1_f, UInt<8>("h0e8")) @[ifu_bp_ctl.scala 421:83] - node _T_4625 = bits(_T_4624, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4626 = eq(btb_rd_addr_p1_f, UInt<8>("h0e9")) @[ifu_bp_ctl.scala 421:83] - node _T_4627 = bits(_T_4626, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4628 = eq(btb_rd_addr_p1_f, UInt<8>("h0ea")) @[ifu_bp_ctl.scala 421:83] - node _T_4629 = bits(_T_4628, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4630 = eq(btb_rd_addr_p1_f, UInt<8>("h0eb")) @[ifu_bp_ctl.scala 421:83] - node _T_4631 = bits(_T_4630, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4632 = eq(btb_rd_addr_p1_f, UInt<8>("h0ec")) @[ifu_bp_ctl.scala 421:83] - node _T_4633 = bits(_T_4632, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4634 = eq(btb_rd_addr_p1_f, UInt<8>("h0ed")) @[ifu_bp_ctl.scala 421:83] - node _T_4635 = bits(_T_4634, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4636 = eq(btb_rd_addr_p1_f, UInt<8>("h0ee")) @[ifu_bp_ctl.scala 421:83] - node _T_4637 = bits(_T_4636, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4638 = eq(btb_rd_addr_p1_f, UInt<8>("h0ef")) @[ifu_bp_ctl.scala 421:83] - node _T_4639 = bits(_T_4638, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4640 = eq(btb_rd_addr_p1_f, UInt<8>("h0f0")) @[ifu_bp_ctl.scala 421:83] - node _T_4641 = bits(_T_4640, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4642 = eq(btb_rd_addr_p1_f, UInt<8>("h0f1")) @[ifu_bp_ctl.scala 421:83] - node _T_4643 = bits(_T_4642, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4644 = eq(btb_rd_addr_p1_f, UInt<8>("h0f2")) @[ifu_bp_ctl.scala 421:83] - node _T_4645 = bits(_T_4644, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4646 = eq(btb_rd_addr_p1_f, UInt<8>("h0f3")) @[ifu_bp_ctl.scala 421:83] - node _T_4647 = bits(_T_4646, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4648 = eq(btb_rd_addr_p1_f, UInt<8>("h0f4")) @[ifu_bp_ctl.scala 421:83] - node _T_4649 = bits(_T_4648, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4650 = eq(btb_rd_addr_p1_f, UInt<8>("h0f5")) @[ifu_bp_ctl.scala 421:83] - node _T_4651 = bits(_T_4650, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4652 = eq(btb_rd_addr_p1_f, UInt<8>("h0f6")) @[ifu_bp_ctl.scala 421:83] - node _T_4653 = bits(_T_4652, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4654 = eq(btb_rd_addr_p1_f, UInt<8>("h0f7")) @[ifu_bp_ctl.scala 421:83] - node _T_4655 = bits(_T_4654, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4656 = eq(btb_rd_addr_p1_f, UInt<8>("h0f8")) @[ifu_bp_ctl.scala 421:83] - node _T_4657 = bits(_T_4656, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4658 = eq(btb_rd_addr_p1_f, UInt<8>("h0f9")) @[ifu_bp_ctl.scala 421:83] - node _T_4659 = bits(_T_4658, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4660 = eq(btb_rd_addr_p1_f, UInt<8>("h0fa")) @[ifu_bp_ctl.scala 421:83] - node _T_4661 = bits(_T_4660, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4662 = eq(btb_rd_addr_p1_f, UInt<8>("h0fb")) @[ifu_bp_ctl.scala 421:83] - node _T_4663 = bits(_T_4662, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4664 = eq(btb_rd_addr_p1_f, UInt<8>("h0fc")) @[ifu_bp_ctl.scala 421:83] - node _T_4665 = bits(_T_4664, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4666 = eq(btb_rd_addr_p1_f, UInt<8>("h0fd")) @[ifu_bp_ctl.scala 421:83] - node _T_4667 = bits(_T_4666, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4668 = eq(btb_rd_addr_p1_f, UInt<8>("h0fe")) @[ifu_bp_ctl.scala 421:83] - node _T_4669 = bits(_T_4668, 0, 0) @[ifu_bp_ctl.scala 421:91] - node _T_4670 = eq(btb_rd_addr_p1_f, UInt<8>("h0ff")) @[ifu_bp_ctl.scala 421:83] - node _T_4671 = bits(_T_4670, 0, 0) @[ifu_bp_ctl.scala 421:91] + btb_bank0_rd_data_way1_f <= _T_4159 @[ifu_bp_ctl.scala 419:28] + node _T_4160 = eq(btb_rd_addr_p1_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 422:83] + node _T_4161 = bits(_T_4160, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4162 = eq(btb_rd_addr_p1_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 422:83] + node _T_4163 = bits(_T_4162, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4164 = eq(btb_rd_addr_p1_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 422:83] + node _T_4165 = bits(_T_4164, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4166 = eq(btb_rd_addr_p1_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 422:83] + node _T_4167 = bits(_T_4166, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4168 = eq(btb_rd_addr_p1_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 422:83] + node _T_4169 = bits(_T_4168, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4170 = eq(btb_rd_addr_p1_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 422:83] + node _T_4171 = bits(_T_4170, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4172 = eq(btb_rd_addr_p1_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 422:83] + node _T_4173 = bits(_T_4172, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4174 = eq(btb_rd_addr_p1_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 422:83] + node _T_4175 = bits(_T_4174, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4176 = eq(btb_rd_addr_p1_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 422:83] + node _T_4177 = bits(_T_4176, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4178 = eq(btb_rd_addr_p1_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 422:83] + node _T_4179 = bits(_T_4178, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4180 = eq(btb_rd_addr_p1_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 422:83] + node _T_4181 = bits(_T_4180, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4182 = eq(btb_rd_addr_p1_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 422:83] + node _T_4183 = bits(_T_4182, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4184 = eq(btb_rd_addr_p1_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 422:83] + node _T_4185 = bits(_T_4184, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4186 = eq(btb_rd_addr_p1_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 422:83] + node _T_4187 = bits(_T_4186, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4188 = eq(btb_rd_addr_p1_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 422:83] + node _T_4189 = bits(_T_4188, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4190 = eq(btb_rd_addr_p1_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 422:83] + node _T_4191 = bits(_T_4190, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4192 = eq(btb_rd_addr_p1_f, UInt<5>("h010")) @[ifu_bp_ctl.scala 422:83] + node _T_4193 = bits(_T_4192, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4194 = eq(btb_rd_addr_p1_f, UInt<5>("h011")) @[ifu_bp_ctl.scala 422:83] + node _T_4195 = bits(_T_4194, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4196 = eq(btb_rd_addr_p1_f, UInt<5>("h012")) @[ifu_bp_ctl.scala 422:83] + node _T_4197 = bits(_T_4196, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4198 = eq(btb_rd_addr_p1_f, UInt<5>("h013")) @[ifu_bp_ctl.scala 422:83] + node _T_4199 = bits(_T_4198, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4200 = eq(btb_rd_addr_p1_f, UInt<5>("h014")) @[ifu_bp_ctl.scala 422:83] + node _T_4201 = bits(_T_4200, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4202 = eq(btb_rd_addr_p1_f, UInt<5>("h015")) @[ifu_bp_ctl.scala 422:83] + node _T_4203 = bits(_T_4202, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4204 = eq(btb_rd_addr_p1_f, UInt<5>("h016")) @[ifu_bp_ctl.scala 422:83] + node _T_4205 = bits(_T_4204, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4206 = eq(btb_rd_addr_p1_f, UInt<5>("h017")) @[ifu_bp_ctl.scala 422:83] + node _T_4207 = bits(_T_4206, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4208 = eq(btb_rd_addr_p1_f, UInt<5>("h018")) @[ifu_bp_ctl.scala 422:83] + node _T_4209 = bits(_T_4208, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4210 = eq(btb_rd_addr_p1_f, UInt<5>("h019")) @[ifu_bp_ctl.scala 422:83] + node _T_4211 = bits(_T_4210, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4212 = eq(btb_rd_addr_p1_f, UInt<5>("h01a")) @[ifu_bp_ctl.scala 422:83] + node _T_4213 = bits(_T_4212, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4214 = eq(btb_rd_addr_p1_f, UInt<5>("h01b")) @[ifu_bp_ctl.scala 422:83] + node _T_4215 = bits(_T_4214, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4216 = eq(btb_rd_addr_p1_f, UInt<5>("h01c")) @[ifu_bp_ctl.scala 422:83] + node _T_4217 = bits(_T_4216, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4218 = eq(btb_rd_addr_p1_f, UInt<5>("h01d")) @[ifu_bp_ctl.scala 422:83] + node _T_4219 = bits(_T_4218, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4220 = eq(btb_rd_addr_p1_f, UInt<5>("h01e")) @[ifu_bp_ctl.scala 422:83] + node _T_4221 = bits(_T_4220, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4222 = eq(btb_rd_addr_p1_f, UInt<5>("h01f")) @[ifu_bp_ctl.scala 422:83] + node _T_4223 = bits(_T_4222, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4224 = eq(btb_rd_addr_p1_f, UInt<6>("h020")) @[ifu_bp_ctl.scala 422:83] + node _T_4225 = bits(_T_4224, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4226 = eq(btb_rd_addr_p1_f, UInt<6>("h021")) @[ifu_bp_ctl.scala 422:83] + node _T_4227 = bits(_T_4226, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4228 = eq(btb_rd_addr_p1_f, UInt<6>("h022")) @[ifu_bp_ctl.scala 422:83] + node _T_4229 = bits(_T_4228, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4230 = eq(btb_rd_addr_p1_f, UInt<6>("h023")) @[ifu_bp_ctl.scala 422:83] + node _T_4231 = bits(_T_4230, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4232 = eq(btb_rd_addr_p1_f, UInt<6>("h024")) @[ifu_bp_ctl.scala 422:83] + node _T_4233 = bits(_T_4232, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4234 = eq(btb_rd_addr_p1_f, UInt<6>("h025")) @[ifu_bp_ctl.scala 422:83] + node _T_4235 = bits(_T_4234, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4236 = eq(btb_rd_addr_p1_f, UInt<6>("h026")) @[ifu_bp_ctl.scala 422:83] + node _T_4237 = bits(_T_4236, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4238 = eq(btb_rd_addr_p1_f, UInt<6>("h027")) @[ifu_bp_ctl.scala 422:83] + node _T_4239 = bits(_T_4238, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4240 = eq(btb_rd_addr_p1_f, UInt<6>("h028")) @[ifu_bp_ctl.scala 422:83] + node _T_4241 = bits(_T_4240, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4242 = eq(btb_rd_addr_p1_f, UInt<6>("h029")) @[ifu_bp_ctl.scala 422:83] + node _T_4243 = bits(_T_4242, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4244 = eq(btb_rd_addr_p1_f, UInt<6>("h02a")) @[ifu_bp_ctl.scala 422:83] + node _T_4245 = bits(_T_4244, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4246 = eq(btb_rd_addr_p1_f, UInt<6>("h02b")) @[ifu_bp_ctl.scala 422:83] + node _T_4247 = bits(_T_4246, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4248 = eq(btb_rd_addr_p1_f, UInt<6>("h02c")) @[ifu_bp_ctl.scala 422:83] + node _T_4249 = bits(_T_4248, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4250 = eq(btb_rd_addr_p1_f, UInt<6>("h02d")) @[ifu_bp_ctl.scala 422:83] + node _T_4251 = bits(_T_4250, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4252 = eq(btb_rd_addr_p1_f, UInt<6>("h02e")) @[ifu_bp_ctl.scala 422:83] + node _T_4253 = bits(_T_4252, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4254 = eq(btb_rd_addr_p1_f, UInt<6>("h02f")) @[ifu_bp_ctl.scala 422:83] + node _T_4255 = bits(_T_4254, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4256 = eq(btb_rd_addr_p1_f, UInt<6>("h030")) @[ifu_bp_ctl.scala 422:83] + node _T_4257 = bits(_T_4256, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4258 = eq(btb_rd_addr_p1_f, UInt<6>("h031")) @[ifu_bp_ctl.scala 422:83] + node _T_4259 = bits(_T_4258, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4260 = eq(btb_rd_addr_p1_f, UInt<6>("h032")) @[ifu_bp_ctl.scala 422:83] + node _T_4261 = bits(_T_4260, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4262 = eq(btb_rd_addr_p1_f, UInt<6>("h033")) @[ifu_bp_ctl.scala 422:83] + node _T_4263 = bits(_T_4262, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4264 = eq(btb_rd_addr_p1_f, UInt<6>("h034")) @[ifu_bp_ctl.scala 422:83] + node _T_4265 = bits(_T_4264, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4266 = eq(btb_rd_addr_p1_f, UInt<6>("h035")) @[ifu_bp_ctl.scala 422:83] + node _T_4267 = bits(_T_4266, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4268 = eq(btb_rd_addr_p1_f, UInt<6>("h036")) @[ifu_bp_ctl.scala 422:83] + node _T_4269 = bits(_T_4268, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4270 = eq(btb_rd_addr_p1_f, UInt<6>("h037")) @[ifu_bp_ctl.scala 422:83] + node _T_4271 = bits(_T_4270, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4272 = eq(btb_rd_addr_p1_f, UInt<6>("h038")) @[ifu_bp_ctl.scala 422:83] + node _T_4273 = bits(_T_4272, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4274 = eq(btb_rd_addr_p1_f, UInt<6>("h039")) @[ifu_bp_ctl.scala 422:83] + node _T_4275 = bits(_T_4274, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4276 = eq(btb_rd_addr_p1_f, UInt<6>("h03a")) @[ifu_bp_ctl.scala 422:83] + node _T_4277 = bits(_T_4276, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4278 = eq(btb_rd_addr_p1_f, UInt<6>("h03b")) @[ifu_bp_ctl.scala 422:83] + node _T_4279 = bits(_T_4278, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4280 = eq(btb_rd_addr_p1_f, UInt<6>("h03c")) @[ifu_bp_ctl.scala 422:83] + node _T_4281 = bits(_T_4280, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4282 = eq(btb_rd_addr_p1_f, UInt<6>("h03d")) @[ifu_bp_ctl.scala 422:83] + node _T_4283 = bits(_T_4282, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4284 = eq(btb_rd_addr_p1_f, UInt<6>("h03e")) @[ifu_bp_ctl.scala 422:83] + node _T_4285 = bits(_T_4284, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4286 = eq(btb_rd_addr_p1_f, UInt<6>("h03f")) @[ifu_bp_ctl.scala 422:83] + node _T_4287 = bits(_T_4286, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4288 = eq(btb_rd_addr_p1_f, UInt<7>("h040")) @[ifu_bp_ctl.scala 422:83] + node _T_4289 = bits(_T_4288, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4290 = eq(btb_rd_addr_p1_f, UInt<7>("h041")) @[ifu_bp_ctl.scala 422:83] + node _T_4291 = bits(_T_4290, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4292 = eq(btb_rd_addr_p1_f, UInt<7>("h042")) @[ifu_bp_ctl.scala 422:83] + node _T_4293 = bits(_T_4292, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4294 = eq(btb_rd_addr_p1_f, UInt<7>("h043")) @[ifu_bp_ctl.scala 422:83] + node _T_4295 = bits(_T_4294, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4296 = eq(btb_rd_addr_p1_f, UInt<7>("h044")) @[ifu_bp_ctl.scala 422:83] + node _T_4297 = bits(_T_4296, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4298 = eq(btb_rd_addr_p1_f, UInt<7>("h045")) @[ifu_bp_ctl.scala 422:83] + node _T_4299 = bits(_T_4298, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4300 = eq(btb_rd_addr_p1_f, UInt<7>("h046")) @[ifu_bp_ctl.scala 422:83] + node _T_4301 = bits(_T_4300, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4302 = eq(btb_rd_addr_p1_f, UInt<7>("h047")) @[ifu_bp_ctl.scala 422:83] + node _T_4303 = bits(_T_4302, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4304 = eq(btb_rd_addr_p1_f, UInt<7>("h048")) @[ifu_bp_ctl.scala 422:83] + node _T_4305 = bits(_T_4304, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4306 = eq(btb_rd_addr_p1_f, UInt<7>("h049")) @[ifu_bp_ctl.scala 422:83] + node _T_4307 = bits(_T_4306, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4308 = eq(btb_rd_addr_p1_f, UInt<7>("h04a")) @[ifu_bp_ctl.scala 422:83] + node _T_4309 = bits(_T_4308, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4310 = eq(btb_rd_addr_p1_f, UInt<7>("h04b")) @[ifu_bp_ctl.scala 422:83] + node _T_4311 = bits(_T_4310, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4312 = eq(btb_rd_addr_p1_f, UInt<7>("h04c")) @[ifu_bp_ctl.scala 422:83] + node _T_4313 = bits(_T_4312, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4314 = eq(btb_rd_addr_p1_f, UInt<7>("h04d")) @[ifu_bp_ctl.scala 422:83] + node _T_4315 = bits(_T_4314, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4316 = eq(btb_rd_addr_p1_f, UInt<7>("h04e")) @[ifu_bp_ctl.scala 422:83] + node _T_4317 = bits(_T_4316, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4318 = eq(btb_rd_addr_p1_f, UInt<7>("h04f")) @[ifu_bp_ctl.scala 422:83] + node _T_4319 = bits(_T_4318, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4320 = eq(btb_rd_addr_p1_f, UInt<7>("h050")) @[ifu_bp_ctl.scala 422:83] + node _T_4321 = bits(_T_4320, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4322 = eq(btb_rd_addr_p1_f, UInt<7>("h051")) @[ifu_bp_ctl.scala 422:83] + node _T_4323 = bits(_T_4322, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4324 = eq(btb_rd_addr_p1_f, UInt<7>("h052")) @[ifu_bp_ctl.scala 422:83] + node _T_4325 = bits(_T_4324, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4326 = eq(btb_rd_addr_p1_f, UInt<7>("h053")) @[ifu_bp_ctl.scala 422:83] + node _T_4327 = bits(_T_4326, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4328 = eq(btb_rd_addr_p1_f, UInt<7>("h054")) @[ifu_bp_ctl.scala 422:83] + node _T_4329 = bits(_T_4328, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4330 = eq(btb_rd_addr_p1_f, UInt<7>("h055")) @[ifu_bp_ctl.scala 422:83] + node _T_4331 = bits(_T_4330, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4332 = eq(btb_rd_addr_p1_f, UInt<7>("h056")) @[ifu_bp_ctl.scala 422:83] + node _T_4333 = bits(_T_4332, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4334 = eq(btb_rd_addr_p1_f, UInt<7>("h057")) @[ifu_bp_ctl.scala 422:83] + node _T_4335 = bits(_T_4334, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4336 = eq(btb_rd_addr_p1_f, UInt<7>("h058")) @[ifu_bp_ctl.scala 422:83] + node _T_4337 = bits(_T_4336, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4338 = eq(btb_rd_addr_p1_f, UInt<7>("h059")) @[ifu_bp_ctl.scala 422:83] + node _T_4339 = bits(_T_4338, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4340 = eq(btb_rd_addr_p1_f, UInt<7>("h05a")) @[ifu_bp_ctl.scala 422:83] + node _T_4341 = bits(_T_4340, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4342 = eq(btb_rd_addr_p1_f, UInt<7>("h05b")) @[ifu_bp_ctl.scala 422:83] + node _T_4343 = bits(_T_4342, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4344 = eq(btb_rd_addr_p1_f, UInt<7>("h05c")) @[ifu_bp_ctl.scala 422:83] + node _T_4345 = bits(_T_4344, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4346 = eq(btb_rd_addr_p1_f, UInt<7>("h05d")) @[ifu_bp_ctl.scala 422:83] + node _T_4347 = bits(_T_4346, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4348 = eq(btb_rd_addr_p1_f, UInt<7>("h05e")) @[ifu_bp_ctl.scala 422:83] + node _T_4349 = bits(_T_4348, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4350 = eq(btb_rd_addr_p1_f, UInt<7>("h05f")) @[ifu_bp_ctl.scala 422:83] + node _T_4351 = bits(_T_4350, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4352 = eq(btb_rd_addr_p1_f, UInt<7>("h060")) @[ifu_bp_ctl.scala 422:83] + node _T_4353 = bits(_T_4352, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4354 = eq(btb_rd_addr_p1_f, UInt<7>("h061")) @[ifu_bp_ctl.scala 422:83] + node _T_4355 = bits(_T_4354, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4356 = eq(btb_rd_addr_p1_f, UInt<7>("h062")) @[ifu_bp_ctl.scala 422:83] + node _T_4357 = bits(_T_4356, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4358 = eq(btb_rd_addr_p1_f, UInt<7>("h063")) @[ifu_bp_ctl.scala 422:83] + node _T_4359 = bits(_T_4358, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4360 = eq(btb_rd_addr_p1_f, UInt<7>("h064")) @[ifu_bp_ctl.scala 422:83] + node _T_4361 = bits(_T_4360, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4362 = eq(btb_rd_addr_p1_f, UInt<7>("h065")) @[ifu_bp_ctl.scala 422:83] + node _T_4363 = bits(_T_4362, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4364 = eq(btb_rd_addr_p1_f, UInt<7>("h066")) @[ifu_bp_ctl.scala 422:83] + node _T_4365 = bits(_T_4364, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4366 = eq(btb_rd_addr_p1_f, UInt<7>("h067")) @[ifu_bp_ctl.scala 422:83] + node _T_4367 = bits(_T_4366, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4368 = eq(btb_rd_addr_p1_f, UInt<7>("h068")) @[ifu_bp_ctl.scala 422:83] + node _T_4369 = bits(_T_4368, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4370 = eq(btb_rd_addr_p1_f, UInt<7>("h069")) @[ifu_bp_ctl.scala 422:83] + node _T_4371 = bits(_T_4370, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4372 = eq(btb_rd_addr_p1_f, UInt<7>("h06a")) @[ifu_bp_ctl.scala 422:83] + node _T_4373 = bits(_T_4372, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4374 = eq(btb_rd_addr_p1_f, UInt<7>("h06b")) @[ifu_bp_ctl.scala 422:83] + node _T_4375 = bits(_T_4374, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4376 = eq(btb_rd_addr_p1_f, UInt<7>("h06c")) @[ifu_bp_ctl.scala 422:83] + node _T_4377 = bits(_T_4376, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4378 = eq(btb_rd_addr_p1_f, UInt<7>("h06d")) @[ifu_bp_ctl.scala 422:83] + node _T_4379 = bits(_T_4378, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4380 = eq(btb_rd_addr_p1_f, UInt<7>("h06e")) @[ifu_bp_ctl.scala 422:83] + node _T_4381 = bits(_T_4380, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4382 = eq(btb_rd_addr_p1_f, UInt<7>("h06f")) @[ifu_bp_ctl.scala 422:83] + node _T_4383 = bits(_T_4382, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4384 = eq(btb_rd_addr_p1_f, UInt<7>("h070")) @[ifu_bp_ctl.scala 422:83] + node _T_4385 = bits(_T_4384, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4386 = eq(btb_rd_addr_p1_f, UInt<7>("h071")) @[ifu_bp_ctl.scala 422:83] + node _T_4387 = bits(_T_4386, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4388 = eq(btb_rd_addr_p1_f, UInt<7>("h072")) @[ifu_bp_ctl.scala 422:83] + node _T_4389 = bits(_T_4388, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4390 = eq(btb_rd_addr_p1_f, UInt<7>("h073")) @[ifu_bp_ctl.scala 422:83] + node _T_4391 = bits(_T_4390, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4392 = eq(btb_rd_addr_p1_f, UInt<7>("h074")) @[ifu_bp_ctl.scala 422:83] + node _T_4393 = bits(_T_4392, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4394 = eq(btb_rd_addr_p1_f, UInt<7>("h075")) @[ifu_bp_ctl.scala 422:83] + node _T_4395 = bits(_T_4394, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4396 = eq(btb_rd_addr_p1_f, UInt<7>("h076")) @[ifu_bp_ctl.scala 422:83] + node _T_4397 = bits(_T_4396, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4398 = eq(btb_rd_addr_p1_f, UInt<7>("h077")) @[ifu_bp_ctl.scala 422:83] + node _T_4399 = bits(_T_4398, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4400 = eq(btb_rd_addr_p1_f, UInt<7>("h078")) @[ifu_bp_ctl.scala 422:83] + node _T_4401 = bits(_T_4400, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4402 = eq(btb_rd_addr_p1_f, UInt<7>("h079")) @[ifu_bp_ctl.scala 422:83] + node _T_4403 = bits(_T_4402, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4404 = eq(btb_rd_addr_p1_f, UInt<7>("h07a")) @[ifu_bp_ctl.scala 422:83] + node _T_4405 = bits(_T_4404, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4406 = eq(btb_rd_addr_p1_f, UInt<7>("h07b")) @[ifu_bp_ctl.scala 422:83] + node _T_4407 = bits(_T_4406, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4408 = eq(btb_rd_addr_p1_f, UInt<7>("h07c")) @[ifu_bp_ctl.scala 422:83] + node _T_4409 = bits(_T_4408, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4410 = eq(btb_rd_addr_p1_f, UInt<7>("h07d")) @[ifu_bp_ctl.scala 422:83] + node _T_4411 = bits(_T_4410, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4412 = eq(btb_rd_addr_p1_f, UInt<7>("h07e")) @[ifu_bp_ctl.scala 422:83] + node _T_4413 = bits(_T_4412, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4414 = eq(btb_rd_addr_p1_f, UInt<7>("h07f")) @[ifu_bp_ctl.scala 422:83] + node _T_4415 = bits(_T_4414, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4416 = eq(btb_rd_addr_p1_f, UInt<8>("h080")) @[ifu_bp_ctl.scala 422:83] + node _T_4417 = bits(_T_4416, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4418 = eq(btb_rd_addr_p1_f, UInt<8>("h081")) @[ifu_bp_ctl.scala 422:83] + node _T_4419 = bits(_T_4418, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4420 = eq(btb_rd_addr_p1_f, UInt<8>("h082")) @[ifu_bp_ctl.scala 422:83] + node _T_4421 = bits(_T_4420, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4422 = eq(btb_rd_addr_p1_f, UInt<8>("h083")) @[ifu_bp_ctl.scala 422:83] + node _T_4423 = bits(_T_4422, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4424 = eq(btb_rd_addr_p1_f, UInt<8>("h084")) @[ifu_bp_ctl.scala 422:83] + node _T_4425 = bits(_T_4424, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4426 = eq(btb_rd_addr_p1_f, UInt<8>("h085")) @[ifu_bp_ctl.scala 422:83] + node _T_4427 = bits(_T_4426, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4428 = eq(btb_rd_addr_p1_f, UInt<8>("h086")) @[ifu_bp_ctl.scala 422:83] + node _T_4429 = bits(_T_4428, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4430 = eq(btb_rd_addr_p1_f, UInt<8>("h087")) @[ifu_bp_ctl.scala 422:83] + node _T_4431 = bits(_T_4430, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4432 = eq(btb_rd_addr_p1_f, UInt<8>("h088")) @[ifu_bp_ctl.scala 422:83] + node _T_4433 = bits(_T_4432, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4434 = eq(btb_rd_addr_p1_f, UInt<8>("h089")) @[ifu_bp_ctl.scala 422:83] + node _T_4435 = bits(_T_4434, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4436 = eq(btb_rd_addr_p1_f, UInt<8>("h08a")) @[ifu_bp_ctl.scala 422:83] + node _T_4437 = bits(_T_4436, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4438 = eq(btb_rd_addr_p1_f, UInt<8>("h08b")) @[ifu_bp_ctl.scala 422:83] + node _T_4439 = bits(_T_4438, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4440 = eq(btb_rd_addr_p1_f, UInt<8>("h08c")) @[ifu_bp_ctl.scala 422:83] + node _T_4441 = bits(_T_4440, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4442 = eq(btb_rd_addr_p1_f, UInt<8>("h08d")) @[ifu_bp_ctl.scala 422:83] + node _T_4443 = bits(_T_4442, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4444 = eq(btb_rd_addr_p1_f, UInt<8>("h08e")) @[ifu_bp_ctl.scala 422:83] + node _T_4445 = bits(_T_4444, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4446 = eq(btb_rd_addr_p1_f, UInt<8>("h08f")) @[ifu_bp_ctl.scala 422:83] + node _T_4447 = bits(_T_4446, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4448 = eq(btb_rd_addr_p1_f, UInt<8>("h090")) @[ifu_bp_ctl.scala 422:83] + node _T_4449 = bits(_T_4448, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4450 = eq(btb_rd_addr_p1_f, UInt<8>("h091")) @[ifu_bp_ctl.scala 422:83] + node _T_4451 = bits(_T_4450, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4452 = eq(btb_rd_addr_p1_f, UInt<8>("h092")) @[ifu_bp_ctl.scala 422:83] + node _T_4453 = bits(_T_4452, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4454 = eq(btb_rd_addr_p1_f, UInt<8>("h093")) @[ifu_bp_ctl.scala 422:83] + node _T_4455 = bits(_T_4454, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4456 = eq(btb_rd_addr_p1_f, UInt<8>("h094")) @[ifu_bp_ctl.scala 422:83] + node _T_4457 = bits(_T_4456, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4458 = eq(btb_rd_addr_p1_f, UInt<8>("h095")) @[ifu_bp_ctl.scala 422:83] + node _T_4459 = bits(_T_4458, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4460 = eq(btb_rd_addr_p1_f, UInt<8>("h096")) @[ifu_bp_ctl.scala 422:83] + node _T_4461 = bits(_T_4460, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4462 = eq(btb_rd_addr_p1_f, UInt<8>("h097")) @[ifu_bp_ctl.scala 422:83] + node _T_4463 = bits(_T_4462, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4464 = eq(btb_rd_addr_p1_f, UInt<8>("h098")) @[ifu_bp_ctl.scala 422:83] + node _T_4465 = bits(_T_4464, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4466 = eq(btb_rd_addr_p1_f, UInt<8>("h099")) @[ifu_bp_ctl.scala 422:83] + node _T_4467 = bits(_T_4466, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4468 = eq(btb_rd_addr_p1_f, UInt<8>("h09a")) @[ifu_bp_ctl.scala 422:83] + node _T_4469 = bits(_T_4468, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4470 = eq(btb_rd_addr_p1_f, UInt<8>("h09b")) @[ifu_bp_ctl.scala 422:83] + node _T_4471 = bits(_T_4470, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4472 = eq(btb_rd_addr_p1_f, UInt<8>("h09c")) @[ifu_bp_ctl.scala 422:83] + node _T_4473 = bits(_T_4472, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4474 = eq(btb_rd_addr_p1_f, UInt<8>("h09d")) @[ifu_bp_ctl.scala 422:83] + node _T_4475 = bits(_T_4474, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4476 = eq(btb_rd_addr_p1_f, UInt<8>("h09e")) @[ifu_bp_ctl.scala 422:83] + node _T_4477 = bits(_T_4476, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4478 = eq(btb_rd_addr_p1_f, UInt<8>("h09f")) @[ifu_bp_ctl.scala 422:83] + node _T_4479 = bits(_T_4478, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4480 = eq(btb_rd_addr_p1_f, UInt<8>("h0a0")) @[ifu_bp_ctl.scala 422:83] + node _T_4481 = bits(_T_4480, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4482 = eq(btb_rd_addr_p1_f, UInt<8>("h0a1")) @[ifu_bp_ctl.scala 422:83] + node _T_4483 = bits(_T_4482, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4484 = eq(btb_rd_addr_p1_f, UInt<8>("h0a2")) @[ifu_bp_ctl.scala 422:83] + node _T_4485 = bits(_T_4484, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4486 = eq(btb_rd_addr_p1_f, UInt<8>("h0a3")) @[ifu_bp_ctl.scala 422:83] + node _T_4487 = bits(_T_4486, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4488 = eq(btb_rd_addr_p1_f, UInt<8>("h0a4")) @[ifu_bp_ctl.scala 422:83] + node _T_4489 = bits(_T_4488, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4490 = eq(btb_rd_addr_p1_f, UInt<8>("h0a5")) @[ifu_bp_ctl.scala 422:83] + node _T_4491 = bits(_T_4490, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4492 = eq(btb_rd_addr_p1_f, UInt<8>("h0a6")) @[ifu_bp_ctl.scala 422:83] + node _T_4493 = bits(_T_4492, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4494 = eq(btb_rd_addr_p1_f, UInt<8>("h0a7")) @[ifu_bp_ctl.scala 422:83] + node _T_4495 = bits(_T_4494, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4496 = eq(btb_rd_addr_p1_f, UInt<8>("h0a8")) @[ifu_bp_ctl.scala 422:83] + node _T_4497 = bits(_T_4496, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4498 = eq(btb_rd_addr_p1_f, UInt<8>("h0a9")) @[ifu_bp_ctl.scala 422:83] + node _T_4499 = bits(_T_4498, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4500 = eq(btb_rd_addr_p1_f, UInt<8>("h0aa")) @[ifu_bp_ctl.scala 422:83] + node _T_4501 = bits(_T_4500, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4502 = eq(btb_rd_addr_p1_f, UInt<8>("h0ab")) @[ifu_bp_ctl.scala 422:83] + node _T_4503 = bits(_T_4502, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4504 = eq(btb_rd_addr_p1_f, UInt<8>("h0ac")) @[ifu_bp_ctl.scala 422:83] + node _T_4505 = bits(_T_4504, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4506 = eq(btb_rd_addr_p1_f, UInt<8>("h0ad")) @[ifu_bp_ctl.scala 422:83] + node _T_4507 = bits(_T_4506, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4508 = eq(btb_rd_addr_p1_f, UInt<8>("h0ae")) @[ifu_bp_ctl.scala 422:83] + node _T_4509 = bits(_T_4508, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4510 = eq(btb_rd_addr_p1_f, UInt<8>("h0af")) @[ifu_bp_ctl.scala 422:83] + node _T_4511 = bits(_T_4510, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4512 = eq(btb_rd_addr_p1_f, UInt<8>("h0b0")) @[ifu_bp_ctl.scala 422:83] + node _T_4513 = bits(_T_4512, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4514 = eq(btb_rd_addr_p1_f, UInt<8>("h0b1")) @[ifu_bp_ctl.scala 422:83] + node _T_4515 = bits(_T_4514, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4516 = eq(btb_rd_addr_p1_f, UInt<8>("h0b2")) @[ifu_bp_ctl.scala 422:83] + node _T_4517 = bits(_T_4516, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4518 = eq(btb_rd_addr_p1_f, UInt<8>("h0b3")) @[ifu_bp_ctl.scala 422:83] + node _T_4519 = bits(_T_4518, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4520 = eq(btb_rd_addr_p1_f, UInt<8>("h0b4")) @[ifu_bp_ctl.scala 422:83] + node _T_4521 = bits(_T_4520, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4522 = eq(btb_rd_addr_p1_f, UInt<8>("h0b5")) @[ifu_bp_ctl.scala 422:83] + node _T_4523 = bits(_T_4522, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4524 = eq(btb_rd_addr_p1_f, UInt<8>("h0b6")) @[ifu_bp_ctl.scala 422:83] + node _T_4525 = bits(_T_4524, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4526 = eq(btb_rd_addr_p1_f, UInt<8>("h0b7")) @[ifu_bp_ctl.scala 422:83] + node _T_4527 = bits(_T_4526, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4528 = eq(btb_rd_addr_p1_f, UInt<8>("h0b8")) @[ifu_bp_ctl.scala 422:83] + node _T_4529 = bits(_T_4528, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4530 = eq(btb_rd_addr_p1_f, UInt<8>("h0b9")) @[ifu_bp_ctl.scala 422:83] + node _T_4531 = bits(_T_4530, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4532 = eq(btb_rd_addr_p1_f, UInt<8>("h0ba")) @[ifu_bp_ctl.scala 422:83] + node _T_4533 = bits(_T_4532, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4534 = eq(btb_rd_addr_p1_f, UInt<8>("h0bb")) @[ifu_bp_ctl.scala 422:83] + node _T_4535 = bits(_T_4534, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4536 = eq(btb_rd_addr_p1_f, UInt<8>("h0bc")) @[ifu_bp_ctl.scala 422:83] + node _T_4537 = bits(_T_4536, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4538 = eq(btb_rd_addr_p1_f, UInt<8>("h0bd")) @[ifu_bp_ctl.scala 422:83] + node _T_4539 = bits(_T_4538, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4540 = eq(btb_rd_addr_p1_f, UInt<8>("h0be")) @[ifu_bp_ctl.scala 422:83] + node _T_4541 = bits(_T_4540, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4542 = eq(btb_rd_addr_p1_f, UInt<8>("h0bf")) @[ifu_bp_ctl.scala 422:83] + node _T_4543 = bits(_T_4542, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4544 = eq(btb_rd_addr_p1_f, UInt<8>("h0c0")) @[ifu_bp_ctl.scala 422:83] + node _T_4545 = bits(_T_4544, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4546 = eq(btb_rd_addr_p1_f, UInt<8>("h0c1")) @[ifu_bp_ctl.scala 422:83] + node _T_4547 = bits(_T_4546, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4548 = eq(btb_rd_addr_p1_f, UInt<8>("h0c2")) @[ifu_bp_ctl.scala 422:83] + node _T_4549 = bits(_T_4548, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4550 = eq(btb_rd_addr_p1_f, UInt<8>("h0c3")) @[ifu_bp_ctl.scala 422:83] + node _T_4551 = bits(_T_4550, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4552 = eq(btb_rd_addr_p1_f, UInt<8>("h0c4")) @[ifu_bp_ctl.scala 422:83] + node _T_4553 = bits(_T_4552, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4554 = eq(btb_rd_addr_p1_f, UInt<8>("h0c5")) @[ifu_bp_ctl.scala 422:83] + node _T_4555 = bits(_T_4554, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4556 = eq(btb_rd_addr_p1_f, UInt<8>("h0c6")) @[ifu_bp_ctl.scala 422:83] + node _T_4557 = bits(_T_4556, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4558 = eq(btb_rd_addr_p1_f, UInt<8>("h0c7")) @[ifu_bp_ctl.scala 422:83] + node _T_4559 = bits(_T_4558, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4560 = eq(btb_rd_addr_p1_f, UInt<8>("h0c8")) @[ifu_bp_ctl.scala 422:83] + node _T_4561 = bits(_T_4560, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4562 = eq(btb_rd_addr_p1_f, UInt<8>("h0c9")) @[ifu_bp_ctl.scala 422:83] + node _T_4563 = bits(_T_4562, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4564 = eq(btb_rd_addr_p1_f, UInt<8>("h0ca")) @[ifu_bp_ctl.scala 422:83] + node _T_4565 = bits(_T_4564, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4566 = eq(btb_rd_addr_p1_f, UInt<8>("h0cb")) @[ifu_bp_ctl.scala 422:83] + node _T_4567 = bits(_T_4566, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4568 = eq(btb_rd_addr_p1_f, UInt<8>("h0cc")) @[ifu_bp_ctl.scala 422:83] + node _T_4569 = bits(_T_4568, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4570 = eq(btb_rd_addr_p1_f, UInt<8>("h0cd")) @[ifu_bp_ctl.scala 422:83] + node _T_4571 = bits(_T_4570, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4572 = eq(btb_rd_addr_p1_f, UInt<8>("h0ce")) @[ifu_bp_ctl.scala 422:83] + node _T_4573 = bits(_T_4572, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4574 = eq(btb_rd_addr_p1_f, UInt<8>("h0cf")) @[ifu_bp_ctl.scala 422:83] + node _T_4575 = bits(_T_4574, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4576 = eq(btb_rd_addr_p1_f, UInt<8>("h0d0")) @[ifu_bp_ctl.scala 422:83] + node _T_4577 = bits(_T_4576, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4578 = eq(btb_rd_addr_p1_f, UInt<8>("h0d1")) @[ifu_bp_ctl.scala 422:83] + node _T_4579 = bits(_T_4578, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4580 = eq(btb_rd_addr_p1_f, UInt<8>("h0d2")) @[ifu_bp_ctl.scala 422:83] + node _T_4581 = bits(_T_4580, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4582 = eq(btb_rd_addr_p1_f, UInt<8>("h0d3")) @[ifu_bp_ctl.scala 422:83] + node _T_4583 = bits(_T_4582, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4584 = eq(btb_rd_addr_p1_f, UInt<8>("h0d4")) @[ifu_bp_ctl.scala 422:83] + node _T_4585 = bits(_T_4584, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4586 = eq(btb_rd_addr_p1_f, UInt<8>("h0d5")) @[ifu_bp_ctl.scala 422:83] + node _T_4587 = bits(_T_4586, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4588 = eq(btb_rd_addr_p1_f, UInt<8>("h0d6")) @[ifu_bp_ctl.scala 422:83] + node _T_4589 = bits(_T_4588, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4590 = eq(btb_rd_addr_p1_f, UInt<8>("h0d7")) @[ifu_bp_ctl.scala 422:83] + node _T_4591 = bits(_T_4590, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4592 = eq(btb_rd_addr_p1_f, UInt<8>("h0d8")) @[ifu_bp_ctl.scala 422:83] + node _T_4593 = bits(_T_4592, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4594 = eq(btb_rd_addr_p1_f, UInt<8>("h0d9")) @[ifu_bp_ctl.scala 422:83] + node _T_4595 = bits(_T_4594, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4596 = eq(btb_rd_addr_p1_f, UInt<8>("h0da")) @[ifu_bp_ctl.scala 422:83] + node _T_4597 = bits(_T_4596, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4598 = eq(btb_rd_addr_p1_f, UInt<8>("h0db")) @[ifu_bp_ctl.scala 422:83] + node _T_4599 = bits(_T_4598, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4600 = eq(btb_rd_addr_p1_f, UInt<8>("h0dc")) @[ifu_bp_ctl.scala 422:83] + node _T_4601 = bits(_T_4600, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4602 = eq(btb_rd_addr_p1_f, UInt<8>("h0dd")) @[ifu_bp_ctl.scala 422:83] + node _T_4603 = bits(_T_4602, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4604 = eq(btb_rd_addr_p1_f, UInt<8>("h0de")) @[ifu_bp_ctl.scala 422:83] + node _T_4605 = bits(_T_4604, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4606 = eq(btb_rd_addr_p1_f, UInt<8>("h0df")) @[ifu_bp_ctl.scala 422:83] + node _T_4607 = bits(_T_4606, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4608 = eq(btb_rd_addr_p1_f, UInt<8>("h0e0")) @[ifu_bp_ctl.scala 422:83] + node _T_4609 = bits(_T_4608, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4610 = eq(btb_rd_addr_p1_f, UInt<8>("h0e1")) @[ifu_bp_ctl.scala 422:83] + node _T_4611 = bits(_T_4610, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4612 = eq(btb_rd_addr_p1_f, UInt<8>("h0e2")) @[ifu_bp_ctl.scala 422:83] + node _T_4613 = bits(_T_4612, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4614 = eq(btb_rd_addr_p1_f, UInt<8>("h0e3")) @[ifu_bp_ctl.scala 422:83] + node _T_4615 = bits(_T_4614, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4616 = eq(btb_rd_addr_p1_f, UInt<8>("h0e4")) @[ifu_bp_ctl.scala 422:83] + node _T_4617 = bits(_T_4616, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4618 = eq(btb_rd_addr_p1_f, UInt<8>("h0e5")) @[ifu_bp_ctl.scala 422:83] + node _T_4619 = bits(_T_4618, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4620 = eq(btb_rd_addr_p1_f, UInt<8>("h0e6")) @[ifu_bp_ctl.scala 422:83] + node _T_4621 = bits(_T_4620, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4622 = eq(btb_rd_addr_p1_f, UInt<8>("h0e7")) @[ifu_bp_ctl.scala 422:83] + node _T_4623 = bits(_T_4622, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4624 = eq(btb_rd_addr_p1_f, UInt<8>("h0e8")) @[ifu_bp_ctl.scala 422:83] + node _T_4625 = bits(_T_4624, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4626 = eq(btb_rd_addr_p1_f, UInt<8>("h0e9")) @[ifu_bp_ctl.scala 422:83] + node _T_4627 = bits(_T_4626, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4628 = eq(btb_rd_addr_p1_f, UInt<8>("h0ea")) @[ifu_bp_ctl.scala 422:83] + node _T_4629 = bits(_T_4628, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4630 = eq(btb_rd_addr_p1_f, UInt<8>("h0eb")) @[ifu_bp_ctl.scala 422:83] + node _T_4631 = bits(_T_4630, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4632 = eq(btb_rd_addr_p1_f, UInt<8>("h0ec")) @[ifu_bp_ctl.scala 422:83] + node _T_4633 = bits(_T_4632, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4634 = eq(btb_rd_addr_p1_f, UInt<8>("h0ed")) @[ifu_bp_ctl.scala 422:83] + node _T_4635 = bits(_T_4634, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4636 = eq(btb_rd_addr_p1_f, UInt<8>("h0ee")) @[ifu_bp_ctl.scala 422:83] + node _T_4637 = bits(_T_4636, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4638 = eq(btb_rd_addr_p1_f, UInt<8>("h0ef")) @[ifu_bp_ctl.scala 422:83] + node _T_4639 = bits(_T_4638, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4640 = eq(btb_rd_addr_p1_f, UInt<8>("h0f0")) @[ifu_bp_ctl.scala 422:83] + node _T_4641 = bits(_T_4640, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4642 = eq(btb_rd_addr_p1_f, UInt<8>("h0f1")) @[ifu_bp_ctl.scala 422:83] + node _T_4643 = bits(_T_4642, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4644 = eq(btb_rd_addr_p1_f, UInt<8>("h0f2")) @[ifu_bp_ctl.scala 422:83] + node _T_4645 = bits(_T_4644, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4646 = eq(btb_rd_addr_p1_f, UInt<8>("h0f3")) @[ifu_bp_ctl.scala 422:83] + node _T_4647 = bits(_T_4646, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4648 = eq(btb_rd_addr_p1_f, UInt<8>("h0f4")) @[ifu_bp_ctl.scala 422:83] + node _T_4649 = bits(_T_4648, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4650 = eq(btb_rd_addr_p1_f, UInt<8>("h0f5")) @[ifu_bp_ctl.scala 422:83] + node _T_4651 = bits(_T_4650, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4652 = eq(btb_rd_addr_p1_f, UInt<8>("h0f6")) @[ifu_bp_ctl.scala 422:83] + node _T_4653 = bits(_T_4652, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4654 = eq(btb_rd_addr_p1_f, UInt<8>("h0f7")) @[ifu_bp_ctl.scala 422:83] + node _T_4655 = bits(_T_4654, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4656 = eq(btb_rd_addr_p1_f, UInt<8>("h0f8")) @[ifu_bp_ctl.scala 422:83] + node _T_4657 = bits(_T_4656, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4658 = eq(btb_rd_addr_p1_f, UInt<8>("h0f9")) @[ifu_bp_ctl.scala 422:83] + node _T_4659 = bits(_T_4658, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4660 = eq(btb_rd_addr_p1_f, UInt<8>("h0fa")) @[ifu_bp_ctl.scala 422:83] + node _T_4661 = bits(_T_4660, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4662 = eq(btb_rd_addr_p1_f, UInt<8>("h0fb")) @[ifu_bp_ctl.scala 422:83] + node _T_4663 = bits(_T_4662, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4664 = eq(btb_rd_addr_p1_f, UInt<8>("h0fc")) @[ifu_bp_ctl.scala 422:83] + node _T_4665 = bits(_T_4664, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4666 = eq(btb_rd_addr_p1_f, UInt<8>("h0fd")) @[ifu_bp_ctl.scala 422:83] + node _T_4667 = bits(_T_4666, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4668 = eq(btb_rd_addr_p1_f, UInt<8>("h0fe")) @[ifu_bp_ctl.scala 422:83] + node _T_4669 = bits(_T_4668, 0, 0) @[ifu_bp_ctl.scala 422:91] + node _T_4670 = eq(btb_rd_addr_p1_f, UInt<8>("h0ff")) @[ifu_bp_ctl.scala 422:83] + node _T_4671 = bits(_T_4670, 0, 0) @[ifu_bp_ctl.scala 422:91] node _T_4672 = mux(_T_4161, btb_bank0_rd_data_way0_out_0, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4673 = mux(_T_4163, btb_bank0_rd_data_way0_out_1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4674 = mux(_T_4165, btb_bank0_rd_data_way0_out_2, UInt<1>("h00")) @[Mux.scala 27:72] @@ -38671,519 +38671,519 @@ circuit quasar_wrapper : node _T_5182 = or(_T_5181, _T_4927) @[Mux.scala 27:72] wire _T_5183 : UInt @[Mux.scala 27:72] _T_5183 <= _T_5182 @[Mux.scala 27:72] - btb_bank0_rd_data_way0_p1_f <= _T_5183 @[ifu_bp_ctl.scala 421:31] - node _T_5184 = eq(btb_rd_addr_p1_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 422:83] - node _T_5185 = bits(_T_5184, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5186 = eq(btb_rd_addr_p1_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 422:83] - node _T_5187 = bits(_T_5186, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5188 = eq(btb_rd_addr_p1_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 422:83] - node _T_5189 = bits(_T_5188, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5190 = eq(btb_rd_addr_p1_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 422:83] - node _T_5191 = bits(_T_5190, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5192 = eq(btb_rd_addr_p1_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 422:83] - node _T_5193 = bits(_T_5192, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5194 = eq(btb_rd_addr_p1_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 422:83] - node _T_5195 = bits(_T_5194, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5196 = eq(btb_rd_addr_p1_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 422:83] - node _T_5197 = bits(_T_5196, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5198 = eq(btb_rd_addr_p1_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 422:83] - node _T_5199 = bits(_T_5198, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5200 = eq(btb_rd_addr_p1_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 422:83] - node _T_5201 = bits(_T_5200, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5202 = eq(btb_rd_addr_p1_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 422:83] - node _T_5203 = bits(_T_5202, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5204 = eq(btb_rd_addr_p1_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 422:83] - node _T_5205 = bits(_T_5204, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5206 = eq(btb_rd_addr_p1_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 422:83] - node _T_5207 = bits(_T_5206, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5208 = eq(btb_rd_addr_p1_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 422:83] - node _T_5209 = bits(_T_5208, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5210 = eq(btb_rd_addr_p1_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 422:83] - node _T_5211 = bits(_T_5210, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5212 = eq(btb_rd_addr_p1_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 422:83] - node _T_5213 = bits(_T_5212, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5214 = eq(btb_rd_addr_p1_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 422:83] - node _T_5215 = bits(_T_5214, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5216 = eq(btb_rd_addr_p1_f, UInt<5>("h010")) @[ifu_bp_ctl.scala 422:83] - node _T_5217 = bits(_T_5216, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5218 = eq(btb_rd_addr_p1_f, UInt<5>("h011")) @[ifu_bp_ctl.scala 422:83] - node _T_5219 = bits(_T_5218, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5220 = eq(btb_rd_addr_p1_f, UInt<5>("h012")) @[ifu_bp_ctl.scala 422:83] - node _T_5221 = bits(_T_5220, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5222 = eq(btb_rd_addr_p1_f, UInt<5>("h013")) @[ifu_bp_ctl.scala 422:83] - node _T_5223 = bits(_T_5222, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5224 = eq(btb_rd_addr_p1_f, UInt<5>("h014")) @[ifu_bp_ctl.scala 422:83] - node _T_5225 = bits(_T_5224, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5226 = eq(btb_rd_addr_p1_f, UInt<5>("h015")) @[ifu_bp_ctl.scala 422:83] - node _T_5227 = bits(_T_5226, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5228 = eq(btb_rd_addr_p1_f, UInt<5>("h016")) @[ifu_bp_ctl.scala 422:83] - node _T_5229 = bits(_T_5228, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5230 = eq(btb_rd_addr_p1_f, UInt<5>("h017")) @[ifu_bp_ctl.scala 422:83] - node _T_5231 = bits(_T_5230, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5232 = eq(btb_rd_addr_p1_f, UInt<5>("h018")) @[ifu_bp_ctl.scala 422:83] - node _T_5233 = bits(_T_5232, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5234 = eq(btb_rd_addr_p1_f, UInt<5>("h019")) @[ifu_bp_ctl.scala 422:83] - node _T_5235 = bits(_T_5234, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5236 = eq(btb_rd_addr_p1_f, UInt<5>("h01a")) @[ifu_bp_ctl.scala 422:83] - node _T_5237 = bits(_T_5236, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5238 = eq(btb_rd_addr_p1_f, UInt<5>("h01b")) @[ifu_bp_ctl.scala 422:83] - node _T_5239 = bits(_T_5238, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5240 = eq(btb_rd_addr_p1_f, UInt<5>("h01c")) @[ifu_bp_ctl.scala 422:83] - node _T_5241 = bits(_T_5240, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5242 = eq(btb_rd_addr_p1_f, UInt<5>("h01d")) @[ifu_bp_ctl.scala 422:83] - node _T_5243 = bits(_T_5242, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5244 = eq(btb_rd_addr_p1_f, UInt<5>("h01e")) @[ifu_bp_ctl.scala 422:83] - node _T_5245 = bits(_T_5244, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5246 = eq(btb_rd_addr_p1_f, UInt<5>("h01f")) @[ifu_bp_ctl.scala 422:83] - node _T_5247 = bits(_T_5246, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5248 = eq(btb_rd_addr_p1_f, UInt<6>("h020")) @[ifu_bp_ctl.scala 422:83] - node _T_5249 = bits(_T_5248, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5250 = eq(btb_rd_addr_p1_f, UInt<6>("h021")) @[ifu_bp_ctl.scala 422:83] - node _T_5251 = bits(_T_5250, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5252 = eq(btb_rd_addr_p1_f, UInt<6>("h022")) @[ifu_bp_ctl.scala 422:83] - node _T_5253 = bits(_T_5252, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5254 = eq(btb_rd_addr_p1_f, UInt<6>("h023")) @[ifu_bp_ctl.scala 422:83] - node _T_5255 = bits(_T_5254, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5256 = eq(btb_rd_addr_p1_f, UInt<6>("h024")) @[ifu_bp_ctl.scala 422:83] - node _T_5257 = bits(_T_5256, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5258 = eq(btb_rd_addr_p1_f, UInt<6>("h025")) @[ifu_bp_ctl.scala 422:83] - node _T_5259 = bits(_T_5258, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5260 = eq(btb_rd_addr_p1_f, UInt<6>("h026")) @[ifu_bp_ctl.scala 422:83] - node _T_5261 = bits(_T_5260, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5262 = eq(btb_rd_addr_p1_f, UInt<6>("h027")) @[ifu_bp_ctl.scala 422:83] - node _T_5263 = bits(_T_5262, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5264 = eq(btb_rd_addr_p1_f, UInt<6>("h028")) @[ifu_bp_ctl.scala 422:83] - node _T_5265 = bits(_T_5264, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5266 = eq(btb_rd_addr_p1_f, UInt<6>("h029")) @[ifu_bp_ctl.scala 422:83] - node _T_5267 = bits(_T_5266, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5268 = eq(btb_rd_addr_p1_f, UInt<6>("h02a")) @[ifu_bp_ctl.scala 422:83] - node _T_5269 = bits(_T_5268, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5270 = eq(btb_rd_addr_p1_f, UInt<6>("h02b")) @[ifu_bp_ctl.scala 422:83] - node _T_5271 = bits(_T_5270, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5272 = eq(btb_rd_addr_p1_f, UInt<6>("h02c")) @[ifu_bp_ctl.scala 422:83] - node _T_5273 = bits(_T_5272, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5274 = eq(btb_rd_addr_p1_f, UInt<6>("h02d")) @[ifu_bp_ctl.scala 422:83] - node _T_5275 = bits(_T_5274, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5276 = eq(btb_rd_addr_p1_f, UInt<6>("h02e")) @[ifu_bp_ctl.scala 422:83] - node _T_5277 = bits(_T_5276, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5278 = eq(btb_rd_addr_p1_f, UInt<6>("h02f")) @[ifu_bp_ctl.scala 422:83] - node _T_5279 = bits(_T_5278, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5280 = eq(btb_rd_addr_p1_f, UInt<6>("h030")) @[ifu_bp_ctl.scala 422:83] - node _T_5281 = bits(_T_5280, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5282 = eq(btb_rd_addr_p1_f, UInt<6>("h031")) @[ifu_bp_ctl.scala 422:83] - node _T_5283 = bits(_T_5282, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5284 = eq(btb_rd_addr_p1_f, UInt<6>("h032")) @[ifu_bp_ctl.scala 422:83] - node _T_5285 = bits(_T_5284, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5286 = eq(btb_rd_addr_p1_f, UInt<6>("h033")) @[ifu_bp_ctl.scala 422:83] - node _T_5287 = bits(_T_5286, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5288 = eq(btb_rd_addr_p1_f, UInt<6>("h034")) @[ifu_bp_ctl.scala 422:83] - node _T_5289 = bits(_T_5288, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5290 = eq(btb_rd_addr_p1_f, UInt<6>("h035")) @[ifu_bp_ctl.scala 422:83] - node _T_5291 = bits(_T_5290, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5292 = eq(btb_rd_addr_p1_f, UInt<6>("h036")) @[ifu_bp_ctl.scala 422:83] - node _T_5293 = bits(_T_5292, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5294 = eq(btb_rd_addr_p1_f, UInt<6>("h037")) @[ifu_bp_ctl.scala 422:83] - node _T_5295 = bits(_T_5294, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5296 = eq(btb_rd_addr_p1_f, UInt<6>("h038")) @[ifu_bp_ctl.scala 422:83] - node _T_5297 = bits(_T_5296, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5298 = eq(btb_rd_addr_p1_f, UInt<6>("h039")) @[ifu_bp_ctl.scala 422:83] - node _T_5299 = bits(_T_5298, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5300 = eq(btb_rd_addr_p1_f, UInt<6>("h03a")) @[ifu_bp_ctl.scala 422:83] - node _T_5301 = bits(_T_5300, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5302 = eq(btb_rd_addr_p1_f, UInt<6>("h03b")) @[ifu_bp_ctl.scala 422:83] - node _T_5303 = bits(_T_5302, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5304 = eq(btb_rd_addr_p1_f, UInt<6>("h03c")) @[ifu_bp_ctl.scala 422:83] - node _T_5305 = bits(_T_5304, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5306 = eq(btb_rd_addr_p1_f, UInt<6>("h03d")) @[ifu_bp_ctl.scala 422:83] - node _T_5307 = bits(_T_5306, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5308 = eq(btb_rd_addr_p1_f, UInt<6>("h03e")) @[ifu_bp_ctl.scala 422:83] - node _T_5309 = bits(_T_5308, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5310 = eq(btb_rd_addr_p1_f, UInt<6>("h03f")) @[ifu_bp_ctl.scala 422:83] - node _T_5311 = bits(_T_5310, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5312 = eq(btb_rd_addr_p1_f, UInt<7>("h040")) @[ifu_bp_ctl.scala 422:83] - node _T_5313 = bits(_T_5312, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5314 = eq(btb_rd_addr_p1_f, UInt<7>("h041")) @[ifu_bp_ctl.scala 422:83] - node _T_5315 = bits(_T_5314, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5316 = eq(btb_rd_addr_p1_f, UInt<7>("h042")) @[ifu_bp_ctl.scala 422:83] - node _T_5317 = bits(_T_5316, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5318 = eq(btb_rd_addr_p1_f, UInt<7>("h043")) @[ifu_bp_ctl.scala 422:83] - node _T_5319 = bits(_T_5318, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5320 = eq(btb_rd_addr_p1_f, UInt<7>("h044")) @[ifu_bp_ctl.scala 422:83] - node _T_5321 = bits(_T_5320, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5322 = eq(btb_rd_addr_p1_f, UInt<7>("h045")) @[ifu_bp_ctl.scala 422:83] - node _T_5323 = bits(_T_5322, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5324 = eq(btb_rd_addr_p1_f, UInt<7>("h046")) @[ifu_bp_ctl.scala 422:83] - node _T_5325 = bits(_T_5324, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5326 = eq(btb_rd_addr_p1_f, UInt<7>("h047")) @[ifu_bp_ctl.scala 422:83] - node _T_5327 = bits(_T_5326, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5328 = eq(btb_rd_addr_p1_f, UInt<7>("h048")) @[ifu_bp_ctl.scala 422:83] - node _T_5329 = bits(_T_5328, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5330 = eq(btb_rd_addr_p1_f, UInt<7>("h049")) @[ifu_bp_ctl.scala 422:83] - node _T_5331 = bits(_T_5330, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5332 = eq(btb_rd_addr_p1_f, UInt<7>("h04a")) @[ifu_bp_ctl.scala 422:83] - node _T_5333 = bits(_T_5332, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5334 = eq(btb_rd_addr_p1_f, UInt<7>("h04b")) @[ifu_bp_ctl.scala 422:83] - node _T_5335 = bits(_T_5334, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5336 = eq(btb_rd_addr_p1_f, UInt<7>("h04c")) @[ifu_bp_ctl.scala 422:83] - node _T_5337 = bits(_T_5336, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5338 = eq(btb_rd_addr_p1_f, UInt<7>("h04d")) @[ifu_bp_ctl.scala 422:83] - node _T_5339 = bits(_T_5338, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5340 = eq(btb_rd_addr_p1_f, UInt<7>("h04e")) @[ifu_bp_ctl.scala 422:83] - node _T_5341 = bits(_T_5340, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5342 = eq(btb_rd_addr_p1_f, UInt<7>("h04f")) @[ifu_bp_ctl.scala 422:83] - node _T_5343 = bits(_T_5342, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5344 = eq(btb_rd_addr_p1_f, UInt<7>("h050")) @[ifu_bp_ctl.scala 422:83] - node _T_5345 = bits(_T_5344, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5346 = eq(btb_rd_addr_p1_f, UInt<7>("h051")) @[ifu_bp_ctl.scala 422:83] - node _T_5347 = bits(_T_5346, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5348 = eq(btb_rd_addr_p1_f, UInt<7>("h052")) @[ifu_bp_ctl.scala 422:83] - node _T_5349 = bits(_T_5348, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5350 = eq(btb_rd_addr_p1_f, UInt<7>("h053")) @[ifu_bp_ctl.scala 422:83] - node _T_5351 = bits(_T_5350, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5352 = eq(btb_rd_addr_p1_f, UInt<7>("h054")) @[ifu_bp_ctl.scala 422:83] - node _T_5353 = bits(_T_5352, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5354 = eq(btb_rd_addr_p1_f, UInt<7>("h055")) @[ifu_bp_ctl.scala 422:83] - node _T_5355 = bits(_T_5354, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5356 = eq(btb_rd_addr_p1_f, UInt<7>("h056")) @[ifu_bp_ctl.scala 422:83] - node _T_5357 = bits(_T_5356, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5358 = eq(btb_rd_addr_p1_f, UInt<7>("h057")) @[ifu_bp_ctl.scala 422:83] - node _T_5359 = bits(_T_5358, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5360 = eq(btb_rd_addr_p1_f, UInt<7>("h058")) @[ifu_bp_ctl.scala 422:83] - node _T_5361 = bits(_T_5360, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5362 = eq(btb_rd_addr_p1_f, UInt<7>("h059")) @[ifu_bp_ctl.scala 422:83] - node _T_5363 = bits(_T_5362, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5364 = eq(btb_rd_addr_p1_f, UInt<7>("h05a")) @[ifu_bp_ctl.scala 422:83] - node _T_5365 = bits(_T_5364, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5366 = eq(btb_rd_addr_p1_f, UInt<7>("h05b")) @[ifu_bp_ctl.scala 422:83] - node _T_5367 = bits(_T_5366, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5368 = eq(btb_rd_addr_p1_f, UInt<7>("h05c")) @[ifu_bp_ctl.scala 422:83] - node _T_5369 = bits(_T_5368, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5370 = eq(btb_rd_addr_p1_f, UInt<7>("h05d")) @[ifu_bp_ctl.scala 422:83] - node _T_5371 = bits(_T_5370, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5372 = eq(btb_rd_addr_p1_f, UInt<7>("h05e")) @[ifu_bp_ctl.scala 422:83] - node _T_5373 = bits(_T_5372, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5374 = eq(btb_rd_addr_p1_f, UInt<7>("h05f")) @[ifu_bp_ctl.scala 422:83] - node _T_5375 = bits(_T_5374, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5376 = eq(btb_rd_addr_p1_f, UInt<7>("h060")) @[ifu_bp_ctl.scala 422:83] - node _T_5377 = bits(_T_5376, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5378 = eq(btb_rd_addr_p1_f, UInt<7>("h061")) @[ifu_bp_ctl.scala 422:83] - node _T_5379 = bits(_T_5378, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5380 = eq(btb_rd_addr_p1_f, UInt<7>("h062")) @[ifu_bp_ctl.scala 422:83] - node _T_5381 = bits(_T_5380, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5382 = eq(btb_rd_addr_p1_f, UInt<7>("h063")) @[ifu_bp_ctl.scala 422:83] - node _T_5383 = bits(_T_5382, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5384 = eq(btb_rd_addr_p1_f, UInt<7>("h064")) @[ifu_bp_ctl.scala 422:83] - node _T_5385 = bits(_T_5384, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5386 = eq(btb_rd_addr_p1_f, UInt<7>("h065")) @[ifu_bp_ctl.scala 422:83] - node _T_5387 = bits(_T_5386, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5388 = eq(btb_rd_addr_p1_f, UInt<7>("h066")) @[ifu_bp_ctl.scala 422:83] - node _T_5389 = bits(_T_5388, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5390 = eq(btb_rd_addr_p1_f, UInt<7>("h067")) @[ifu_bp_ctl.scala 422:83] - node _T_5391 = bits(_T_5390, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5392 = eq(btb_rd_addr_p1_f, UInt<7>("h068")) @[ifu_bp_ctl.scala 422:83] - node _T_5393 = bits(_T_5392, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5394 = eq(btb_rd_addr_p1_f, UInt<7>("h069")) @[ifu_bp_ctl.scala 422:83] - node _T_5395 = bits(_T_5394, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5396 = eq(btb_rd_addr_p1_f, UInt<7>("h06a")) @[ifu_bp_ctl.scala 422:83] - node _T_5397 = bits(_T_5396, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5398 = eq(btb_rd_addr_p1_f, UInt<7>("h06b")) @[ifu_bp_ctl.scala 422:83] - node _T_5399 = bits(_T_5398, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5400 = eq(btb_rd_addr_p1_f, UInt<7>("h06c")) @[ifu_bp_ctl.scala 422:83] - node _T_5401 = bits(_T_5400, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5402 = eq(btb_rd_addr_p1_f, UInt<7>("h06d")) @[ifu_bp_ctl.scala 422:83] - node _T_5403 = bits(_T_5402, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5404 = eq(btb_rd_addr_p1_f, UInt<7>("h06e")) @[ifu_bp_ctl.scala 422:83] - node _T_5405 = bits(_T_5404, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5406 = eq(btb_rd_addr_p1_f, UInt<7>("h06f")) @[ifu_bp_ctl.scala 422:83] - node _T_5407 = bits(_T_5406, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5408 = eq(btb_rd_addr_p1_f, UInt<7>("h070")) @[ifu_bp_ctl.scala 422:83] - node _T_5409 = bits(_T_5408, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5410 = eq(btb_rd_addr_p1_f, UInt<7>("h071")) @[ifu_bp_ctl.scala 422:83] - node _T_5411 = bits(_T_5410, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5412 = eq(btb_rd_addr_p1_f, UInt<7>("h072")) @[ifu_bp_ctl.scala 422:83] - node _T_5413 = bits(_T_5412, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5414 = eq(btb_rd_addr_p1_f, UInt<7>("h073")) @[ifu_bp_ctl.scala 422:83] - node _T_5415 = bits(_T_5414, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5416 = eq(btb_rd_addr_p1_f, UInt<7>("h074")) @[ifu_bp_ctl.scala 422:83] - node _T_5417 = bits(_T_5416, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5418 = eq(btb_rd_addr_p1_f, UInt<7>("h075")) @[ifu_bp_ctl.scala 422:83] - node _T_5419 = bits(_T_5418, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5420 = eq(btb_rd_addr_p1_f, UInt<7>("h076")) @[ifu_bp_ctl.scala 422:83] - node _T_5421 = bits(_T_5420, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5422 = eq(btb_rd_addr_p1_f, UInt<7>("h077")) @[ifu_bp_ctl.scala 422:83] - node _T_5423 = bits(_T_5422, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5424 = eq(btb_rd_addr_p1_f, UInt<7>("h078")) @[ifu_bp_ctl.scala 422:83] - node _T_5425 = bits(_T_5424, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5426 = eq(btb_rd_addr_p1_f, UInt<7>("h079")) @[ifu_bp_ctl.scala 422:83] - node _T_5427 = bits(_T_5426, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5428 = eq(btb_rd_addr_p1_f, UInt<7>("h07a")) @[ifu_bp_ctl.scala 422:83] - node _T_5429 = bits(_T_5428, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5430 = eq(btb_rd_addr_p1_f, UInt<7>("h07b")) @[ifu_bp_ctl.scala 422:83] - node _T_5431 = bits(_T_5430, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5432 = eq(btb_rd_addr_p1_f, UInt<7>("h07c")) @[ifu_bp_ctl.scala 422:83] - node _T_5433 = bits(_T_5432, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5434 = eq(btb_rd_addr_p1_f, UInt<7>("h07d")) @[ifu_bp_ctl.scala 422:83] - node _T_5435 = bits(_T_5434, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5436 = eq(btb_rd_addr_p1_f, UInt<7>("h07e")) @[ifu_bp_ctl.scala 422:83] - node _T_5437 = bits(_T_5436, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5438 = eq(btb_rd_addr_p1_f, UInt<7>("h07f")) @[ifu_bp_ctl.scala 422:83] - node _T_5439 = bits(_T_5438, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5440 = eq(btb_rd_addr_p1_f, UInt<8>("h080")) @[ifu_bp_ctl.scala 422:83] - node _T_5441 = bits(_T_5440, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5442 = eq(btb_rd_addr_p1_f, UInt<8>("h081")) @[ifu_bp_ctl.scala 422:83] - node _T_5443 = bits(_T_5442, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5444 = eq(btb_rd_addr_p1_f, UInt<8>("h082")) @[ifu_bp_ctl.scala 422:83] - node _T_5445 = bits(_T_5444, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5446 = eq(btb_rd_addr_p1_f, UInt<8>("h083")) @[ifu_bp_ctl.scala 422:83] - node _T_5447 = bits(_T_5446, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5448 = eq(btb_rd_addr_p1_f, UInt<8>("h084")) @[ifu_bp_ctl.scala 422:83] - node _T_5449 = bits(_T_5448, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5450 = eq(btb_rd_addr_p1_f, UInt<8>("h085")) @[ifu_bp_ctl.scala 422:83] - node _T_5451 = bits(_T_5450, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5452 = eq(btb_rd_addr_p1_f, UInt<8>("h086")) @[ifu_bp_ctl.scala 422:83] - node _T_5453 = bits(_T_5452, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5454 = eq(btb_rd_addr_p1_f, UInt<8>("h087")) @[ifu_bp_ctl.scala 422:83] - node _T_5455 = bits(_T_5454, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5456 = eq(btb_rd_addr_p1_f, UInt<8>("h088")) @[ifu_bp_ctl.scala 422:83] - node _T_5457 = bits(_T_5456, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5458 = eq(btb_rd_addr_p1_f, UInt<8>("h089")) @[ifu_bp_ctl.scala 422:83] - node _T_5459 = bits(_T_5458, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5460 = eq(btb_rd_addr_p1_f, UInt<8>("h08a")) @[ifu_bp_ctl.scala 422:83] - node _T_5461 = bits(_T_5460, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5462 = eq(btb_rd_addr_p1_f, UInt<8>("h08b")) @[ifu_bp_ctl.scala 422:83] - node _T_5463 = bits(_T_5462, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5464 = eq(btb_rd_addr_p1_f, UInt<8>("h08c")) @[ifu_bp_ctl.scala 422:83] - node _T_5465 = bits(_T_5464, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5466 = eq(btb_rd_addr_p1_f, UInt<8>("h08d")) @[ifu_bp_ctl.scala 422:83] - node _T_5467 = bits(_T_5466, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5468 = eq(btb_rd_addr_p1_f, UInt<8>("h08e")) @[ifu_bp_ctl.scala 422:83] - node _T_5469 = bits(_T_5468, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5470 = eq(btb_rd_addr_p1_f, UInt<8>("h08f")) @[ifu_bp_ctl.scala 422:83] - node _T_5471 = bits(_T_5470, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5472 = eq(btb_rd_addr_p1_f, UInt<8>("h090")) @[ifu_bp_ctl.scala 422:83] - node _T_5473 = bits(_T_5472, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5474 = eq(btb_rd_addr_p1_f, UInt<8>("h091")) @[ifu_bp_ctl.scala 422:83] - node _T_5475 = bits(_T_5474, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5476 = eq(btb_rd_addr_p1_f, UInt<8>("h092")) @[ifu_bp_ctl.scala 422:83] - node _T_5477 = bits(_T_5476, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5478 = eq(btb_rd_addr_p1_f, UInt<8>("h093")) @[ifu_bp_ctl.scala 422:83] - node _T_5479 = bits(_T_5478, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5480 = eq(btb_rd_addr_p1_f, UInt<8>("h094")) @[ifu_bp_ctl.scala 422:83] - node _T_5481 = bits(_T_5480, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5482 = eq(btb_rd_addr_p1_f, UInt<8>("h095")) @[ifu_bp_ctl.scala 422:83] - node _T_5483 = bits(_T_5482, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5484 = eq(btb_rd_addr_p1_f, UInt<8>("h096")) @[ifu_bp_ctl.scala 422:83] - node _T_5485 = bits(_T_5484, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5486 = eq(btb_rd_addr_p1_f, UInt<8>("h097")) @[ifu_bp_ctl.scala 422:83] - node _T_5487 = bits(_T_5486, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5488 = eq(btb_rd_addr_p1_f, UInt<8>("h098")) @[ifu_bp_ctl.scala 422:83] - node _T_5489 = bits(_T_5488, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5490 = eq(btb_rd_addr_p1_f, UInt<8>("h099")) @[ifu_bp_ctl.scala 422:83] - node _T_5491 = bits(_T_5490, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5492 = eq(btb_rd_addr_p1_f, UInt<8>("h09a")) @[ifu_bp_ctl.scala 422:83] - node _T_5493 = bits(_T_5492, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5494 = eq(btb_rd_addr_p1_f, UInt<8>("h09b")) @[ifu_bp_ctl.scala 422:83] - node _T_5495 = bits(_T_5494, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5496 = eq(btb_rd_addr_p1_f, UInt<8>("h09c")) @[ifu_bp_ctl.scala 422:83] - node _T_5497 = bits(_T_5496, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5498 = eq(btb_rd_addr_p1_f, UInt<8>("h09d")) @[ifu_bp_ctl.scala 422:83] - node _T_5499 = bits(_T_5498, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5500 = eq(btb_rd_addr_p1_f, UInt<8>("h09e")) @[ifu_bp_ctl.scala 422:83] - node _T_5501 = bits(_T_5500, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5502 = eq(btb_rd_addr_p1_f, UInt<8>("h09f")) @[ifu_bp_ctl.scala 422:83] - node _T_5503 = bits(_T_5502, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5504 = eq(btb_rd_addr_p1_f, UInt<8>("h0a0")) @[ifu_bp_ctl.scala 422:83] - node _T_5505 = bits(_T_5504, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5506 = eq(btb_rd_addr_p1_f, UInt<8>("h0a1")) @[ifu_bp_ctl.scala 422:83] - node _T_5507 = bits(_T_5506, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5508 = eq(btb_rd_addr_p1_f, UInt<8>("h0a2")) @[ifu_bp_ctl.scala 422:83] - node _T_5509 = bits(_T_5508, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5510 = eq(btb_rd_addr_p1_f, UInt<8>("h0a3")) @[ifu_bp_ctl.scala 422:83] - node _T_5511 = bits(_T_5510, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5512 = eq(btb_rd_addr_p1_f, UInt<8>("h0a4")) @[ifu_bp_ctl.scala 422:83] - node _T_5513 = bits(_T_5512, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5514 = eq(btb_rd_addr_p1_f, UInt<8>("h0a5")) @[ifu_bp_ctl.scala 422:83] - node _T_5515 = bits(_T_5514, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5516 = eq(btb_rd_addr_p1_f, UInt<8>("h0a6")) @[ifu_bp_ctl.scala 422:83] - node _T_5517 = bits(_T_5516, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5518 = eq(btb_rd_addr_p1_f, UInt<8>("h0a7")) @[ifu_bp_ctl.scala 422:83] - node _T_5519 = bits(_T_5518, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5520 = eq(btb_rd_addr_p1_f, UInt<8>("h0a8")) @[ifu_bp_ctl.scala 422:83] - node _T_5521 = bits(_T_5520, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5522 = eq(btb_rd_addr_p1_f, UInt<8>("h0a9")) @[ifu_bp_ctl.scala 422:83] - node _T_5523 = bits(_T_5522, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5524 = eq(btb_rd_addr_p1_f, UInt<8>("h0aa")) @[ifu_bp_ctl.scala 422:83] - node _T_5525 = bits(_T_5524, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5526 = eq(btb_rd_addr_p1_f, UInt<8>("h0ab")) @[ifu_bp_ctl.scala 422:83] - node _T_5527 = bits(_T_5526, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5528 = eq(btb_rd_addr_p1_f, UInt<8>("h0ac")) @[ifu_bp_ctl.scala 422:83] - node _T_5529 = bits(_T_5528, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5530 = eq(btb_rd_addr_p1_f, UInt<8>("h0ad")) @[ifu_bp_ctl.scala 422:83] - node _T_5531 = bits(_T_5530, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5532 = eq(btb_rd_addr_p1_f, UInt<8>("h0ae")) @[ifu_bp_ctl.scala 422:83] - node _T_5533 = bits(_T_5532, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5534 = eq(btb_rd_addr_p1_f, UInt<8>("h0af")) @[ifu_bp_ctl.scala 422:83] - node _T_5535 = bits(_T_5534, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5536 = eq(btb_rd_addr_p1_f, UInt<8>("h0b0")) @[ifu_bp_ctl.scala 422:83] - node _T_5537 = bits(_T_5536, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5538 = eq(btb_rd_addr_p1_f, UInt<8>("h0b1")) @[ifu_bp_ctl.scala 422:83] - node _T_5539 = bits(_T_5538, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5540 = eq(btb_rd_addr_p1_f, UInt<8>("h0b2")) @[ifu_bp_ctl.scala 422:83] - node _T_5541 = bits(_T_5540, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5542 = eq(btb_rd_addr_p1_f, UInt<8>("h0b3")) @[ifu_bp_ctl.scala 422:83] - node _T_5543 = bits(_T_5542, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5544 = eq(btb_rd_addr_p1_f, UInt<8>("h0b4")) @[ifu_bp_ctl.scala 422:83] - node _T_5545 = bits(_T_5544, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5546 = eq(btb_rd_addr_p1_f, UInt<8>("h0b5")) @[ifu_bp_ctl.scala 422:83] - node _T_5547 = bits(_T_5546, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5548 = eq(btb_rd_addr_p1_f, UInt<8>("h0b6")) @[ifu_bp_ctl.scala 422:83] - node _T_5549 = bits(_T_5548, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5550 = eq(btb_rd_addr_p1_f, UInt<8>("h0b7")) @[ifu_bp_ctl.scala 422:83] - node _T_5551 = bits(_T_5550, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5552 = eq(btb_rd_addr_p1_f, UInt<8>("h0b8")) @[ifu_bp_ctl.scala 422:83] - node _T_5553 = bits(_T_5552, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5554 = eq(btb_rd_addr_p1_f, UInt<8>("h0b9")) @[ifu_bp_ctl.scala 422:83] - node _T_5555 = bits(_T_5554, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5556 = eq(btb_rd_addr_p1_f, UInt<8>("h0ba")) @[ifu_bp_ctl.scala 422:83] - node _T_5557 = bits(_T_5556, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5558 = eq(btb_rd_addr_p1_f, UInt<8>("h0bb")) @[ifu_bp_ctl.scala 422:83] - node _T_5559 = bits(_T_5558, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5560 = eq(btb_rd_addr_p1_f, UInt<8>("h0bc")) @[ifu_bp_ctl.scala 422:83] - node _T_5561 = bits(_T_5560, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5562 = eq(btb_rd_addr_p1_f, UInt<8>("h0bd")) @[ifu_bp_ctl.scala 422:83] - node _T_5563 = bits(_T_5562, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5564 = eq(btb_rd_addr_p1_f, UInt<8>("h0be")) @[ifu_bp_ctl.scala 422:83] - node _T_5565 = bits(_T_5564, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5566 = eq(btb_rd_addr_p1_f, UInt<8>("h0bf")) @[ifu_bp_ctl.scala 422:83] - node _T_5567 = bits(_T_5566, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5568 = eq(btb_rd_addr_p1_f, UInt<8>("h0c0")) @[ifu_bp_ctl.scala 422:83] - node _T_5569 = bits(_T_5568, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5570 = eq(btb_rd_addr_p1_f, UInt<8>("h0c1")) @[ifu_bp_ctl.scala 422:83] - node _T_5571 = bits(_T_5570, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5572 = eq(btb_rd_addr_p1_f, UInt<8>("h0c2")) @[ifu_bp_ctl.scala 422:83] - node _T_5573 = bits(_T_5572, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5574 = eq(btb_rd_addr_p1_f, UInt<8>("h0c3")) @[ifu_bp_ctl.scala 422:83] - node _T_5575 = bits(_T_5574, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5576 = eq(btb_rd_addr_p1_f, UInt<8>("h0c4")) @[ifu_bp_ctl.scala 422:83] - node _T_5577 = bits(_T_5576, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5578 = eq(btb_rd_addr_p1_f, UInt<8>("h0c5")) @[ifu_bp_ctl.scala 422:83] - node _T_5579 = bits(_T_5578, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5580 = eq(btb_rd_addr_p1_f, UInt<8>("h0c6")) @[ifu_bp_ctl.scala 422:83] - node _T_5581 = bits(_T_5580, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5582 = eq(btb_rd_addr_p1_f, UInt<8>("h0c7")) @[ifu_bp_ctl.scala 422:83] - node _T_5583 = bits(_T_5582, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5584 = eq(btb_rd_addr_p1_f, UInt<8>("h0c8")) @[ifu_bp_ctl.scala 422:83] - node _T_5585 = bits(_T_5584, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5586 = eq(btb_rd_addr_p1_f, UInt<8>("h0c9")) @[ifu_bp_ctl.scala 422:83] - node _T_5587 = bits(_T_5586, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5588 = eq(btb_rd_addr_p1_f, UInt<8>("h0ca")) @[ifu_bp_ctl.scala 422:83] - node _T_5589 = bits(_T_5588, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5590 = eq(btb_rd_addr_p1_f, UInt<8>("h0cb")) @[ifu_bp_ctl.scala 422:83] - node _T_5591 = bits(_T_5590, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5592 = eq(btb_rd_addr_p1_f, UInt<8>("h0cc")) @[ifu_bp_ctl.scala 422:83] - node _T_5593 = bits(_T_5592, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5594 = eq(btb_rd_addr_p1_f, UInt<8>("h0cd")) @[ifu_bp_ctl.scala 422:83] - node _T_5595 = bits(_T_5594, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5596 = eq(btb_rd_addr_p1_f, UInt<8>("h0ce")) @[ifu_bp_ctl.scala 422:83] - node _T_5597 = bits(_T_5596, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5598 = eq(btb_rd_addr_p1_f, UInt<8>("h0cf")) @[ifu_bp_ctl.scala 422:83] - node _T_5599 = bits(_T_5598, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5600 = eq(btb_rd_addr_p1_f, UInt<8>("h0d0")) @[ifu_bp_ctl.scala 422:83] - node _T_5601 = bits(_T_5600, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5602 = eq(btb_rd_addr_p1_f, UInt<8>("h0d1")) @[ifu_bp_ctl.scala 422:83] - node _T_5603 = bits(_T_5602, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5604 = eq(btb_rd_addr_p1_f, UInt<8>("h0d2")) @[ifu_bp_ctl.scala 422:83] - node _T_5605 = bits(_T_5604, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5606 = eq(btb_rd_addr_p1_f, UInt<8>("h0d3")) @[ifu_bp_ctl.scala 422:83] - node _T_5607 = bits(_T_5606, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5608 = eq(btb_rd_addr_p1_f, UInt<8>("h0d4")) @[ifu_bp_ctl.scala 422:83] - node _T_5609 = bits(_T_5608, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5610 = eq(btb_rd_addr_p1_f, UInt<8>("h0d5")) @[ifu_bp_ctl.scala 422:83] - node _T_5611 = bits(_T_5610, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5612 = eq(btb_rd_addr_p1_f, UInt<8>("h0d6")) @[ifu_bp_ctl.scala 422:83] - node _T_5613 = bits(_T_5612, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5614 = eq(btb_rd_addr_p1_f, UInt<8>("h0d7")) @[ifu_bp_ctl.scala 422:83] - node _T_5615 = bits(_T_5614, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5616 = eq(btb_rd_addr_p1_f, UInt<8>("h0d8")) @[ifu_bp_ctl.scala 422:83] - node _T_5617 = bits(_T_5616, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5618 = eq(btb_rd_addr_p1_f, UInt<8>("h0d9")) @[ifu_bp_ctl.scala 422:83] - node _T_5619 = bits(_T_5618, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5620 = eq(btb_rd_addr_p1_f, UInt<8>("h0da")) @[ifu_bp_ctl.scala 422:83] - node _T_5621 = bits(_T_5620, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5622 = eq(btb_rd_addr_p1_f, UInt<8>("h0db")) @[ifu_bp_ctl.scala 422:83] - node _T_5623 = bits(_T_5622, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5624 = eq(btb_rd_addr_p1_f, UInt<8>("h0dc")) @[ifu_bp_ctl.scala 422:83] - node _T_5625 = bits(_T_5624, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5626 = eq(btb_rd_addr_p1_f, UInt<8>("h0dd")) @[ifu_bp_ctl.scala 422:83] - node _T_5627 = bits(_T_5626, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5628 = eq(btb_rd_addr_p1_f, UInt<8>("h0de")) @[ifu_bp_ctl.scala 422:83] - node _T_5629 = bits(_T_5628, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5630 = eq(btb_rd_addr_p1_f, UInt<8>("h0df")) @[ifu_bp_ctl.scala 422:83] - node _T_5631 = bits(_T_5630, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5632 = eq(btb_rd_addr_p1_f, UInt<8>("h0e0")) @[ifu_bp_ctl.scala 422:83] - node _T_5633 = bits(_T_5632, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5634 = eq(btb_rd_addr_p1_f, UInt<8>("h0e1")) @[ifu_bp_ctl.scala 422:83] - node _T_5635 = bits(_T_5634, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5636 = eq(btb_rd_addr_p1_f, UInt<8>("h0e2")) @[ifu_bp_ctl.scala 422:83] - node _T_5637 = bits(_T_5636, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5638 = eq(btb_rd_addr_p1_f, UInt<8>("h0e3")) @[ifu_bp_ctl.scala 422:83] - node _T_5639 = bits(_T_5638, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5640 = eq(btb_rd_addr_p1_f, UInt<8>("h0e4")) @[ifu_bp_ctl.scala 422:83] - node _T_5641 = bits(_T_5640, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5642 = eq(btb_rd_addr_p1_f, UInt<8>("h0e5")) @[ifu_bp_ctl.scala 422:83] - node _T_5643 = bits(_T_5642, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5644 = eq(btb_rd_addr_p1_f, UInt<8>("h0e6")) @[ifu_bp_ctl.scala 422:83] - node _T_5645 = bits(_T_5644, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5646 = eq(btb_rd_addr_p1_f, UInt<8>("h0e7")) @[ifu_bp_ctl.scala 422:83] - node _T_5647 = bits(_T_5646, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5648 = eq(btb_rd_addr_p1_f, UInt<8>("h0e8")) @[ifu_bp_ctl.scala 422:83] - node _T_5649 = bits(_T_5648, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5650 = eq(btb_rd_addr_p1_f, UInt<8>("h0e9")) @[ifu_bp_ctl.scala 422:83] - node _T_5651 = bits(_T_5650, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5652 = eq(btb_rd_addr_p1_f, UInt<8>("h0ea")) @[ifu_bp_ctl.scala 422:83] - node _T_5653 = bits(_T_5652, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5654 = eq(btb_rd_addr_p1_f, UInt<8>("h0eb")) @[ifu_bp_ctl.scala 422:83] - node _T_5655 = bits(_T_5654, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5656 = eq(btb_rd_addr_p1_f, UInt<8>("h0ec")) @[ifu_bp_ctl.scala 422:83] - node _T_5657 = bits(_T_5656, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5658 = eq(btb_rd_addr_p1_f, UInt<8>("h0ed")) @[ifu_bp_ctl.scala 422:83] - node _T_5659 = bits(_T_5658, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5660 = eq(btb_rd_addr_p1_f, UInt<8>("h0ee")) @[ifu_bp_ctl.scala 422:83] - node _T_5661 = bits(_T_5660, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5662 = eq(btb_rd_addr_p1_f, UInt<8>("h0ef")) @[ifu_bp_ctl.scala 422:83] - node _T_5663 = bits(_T_5662, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5664 = eq(btb_rd_addr_p1_f, UInt<8>("h0f0")) @[ifu_bp_ctl.scala 422:83] - node _T_5665 = bits(_T_5664, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5666 = eq(btb_rd_addr_p1_f, UInt<8>("h0f1")) @[ifu_bp_ctl.scala 422:83] - node _T_5667 = bits(_T_5666, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5668 = eq(btb_rd_addr_p1_f, UInt<8>("h0f2")) @[ifu_bp_ctl.scala 422:83] - node _T_5669 = bits(_T_5668, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5670 = eq(btb_rd_addr_p1_f, UInt<8>("h0f3")) @[ifu_bp_ctl.scala 422:83] - node _T_5671 = bits(_T_5670, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5672 = eq(btb_rd_addr_p1_f, UInt<8>("h0f4")) @[ifu_bp_ctl.scala 422:83] - node _T_5673 = bits(_T_5672, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5674 = eq(btb_rd_addr_p1_f, UInt<8>("h0f5")) @[ifu_bp_ctl.scala 422:83] - node _T_5675 = bits(_T_5674, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5676 = eq(btb_rd_addr_p1_f, UInt<8>("h0f6")) @[ifu_bp_ctl.scala 422:83] - node _T_5677 = bits(_T_5676, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5678 = eq(btb_rd_addr_p1_f, UInt<8>("h0f7")) @[ifu_bp_ctl.scala 422:83] - node _T_5679 = bits(_T_5678, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5680 = eq(btb_rd_addr_p1_f, UInt<8>("h0f8")) @[ifu_bp_ctl.scala 422:83] - node _T_5681 = bits(_T_5680, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5682 = eq(btb_rd_addr_p1_f, UInt<8>("h0f9")) @[ifu_bp_ctl.scala 422:83] - node _T_5683 = bits(_T_5682, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5684 = eq(btb_rd_addr_p1_f, UInt<8>("h0fa")) @[ifu_bp_ctl.scala 422:83] - node _T_5685 = bits(_T_5684, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5686 = eq(btb_rd_addr_p1_f, UInt<8>("h0fb")) @[ifu_bp_ctl.scala 422:83] - node _T_5687 = bits(_T_5686, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5688 = eq(btb_rd_addr_p1_f, UInt<8>("h0fc")) @[ifu_bp_ctl.scala 422:83] - node _T_5689 = bits(_T_5688, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5690 = eq(btb_rd_addr_p1_f, UInt<8>("h0fd")) @[ifu_bp_ctl.scala 422:83] - node _T_5691 = bits(_T_5690, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5692 = eq(btb_rd_addr_p1_f, UInt<8>("h0fe")) @[ifu_bp_ctl.scala 422:83] - node _T_5693 = bits(_T_5692, 0, 0) @[ifu_bp_ctl.scala 422:91] - node _T_5694 = eq(btb_rd_addr_p1_f, UInt<8>("h0ff")) @[ifu_bp_ctl.scala 422:83] - node _T_5695 = bits(_T_5694, 0, 0) @[ifu_bp_ctl.scala 422:91] + btb_bank0_rd_data_way0_p1_f <= _T_5183 @[ifu_bp_ctl.scala 422:31] + node _T_5184 = eq(btb_rd_addr_p1_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 423:83] + node _T_5185 = bits(_T_5184, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5186 = eq(btb_rd_addr_p1_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 423:83] + node _T_5187 = bits(_T_5186, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5188 = eq(btb_rd_addr_p1_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 423:83] + node _T_5189 = bits(_T_5188, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5190 = eq(btb_rd_addr_p1_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 423:83] + node _T_5191 = bits(_T_5190, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5192 = eq(btb_rd_addr_p1_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 423:83] + node _T_5193 = bits(_T_5192, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5194 = eq(btb_rd_addr_p1_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 423:83] + node _T_5195 = bits(_T_5194, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5196 = eq(btb_rd_addr_p1_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 423:83] + node _T_5197 = bits(_T_5196, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5198 = eq(btb_rd_addr_p1_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 423:83] + node _T_5199 = bits(_T_5198, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5200 = eq(btb_rd_addr_p1_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 423:83] + node _T_5201 = bits(_T_5200, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5202 = eq(btb_rd_addr_p1_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 423:83] + node _T_5203 = bits(_T_5202, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5204 = eq(btb_rd_addr_p1_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 423:83] + node _T_5205 = bits(_T_5204, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5206 = eq(btb_rd_addr_p1_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 423:83] + node _T_5207 = bits(_T_5206, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5208 = eq(btb_rd_addr_p1_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 423:83] + node _T_5209 = bits(_T_5208, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5210 = eq(btb_rd_addr_p1_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 423:83] + node _T_5211 = bits(_T_5210, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5212 = eq(btb_rd_addr_p1_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 423:83] + node _T_5213 = bits(_T_5212, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5214 = eq(btb_rd_addr_p1_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 423:83] + node _T_5215 = bits(_T_5214, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5216 = eq(btb_rd_addr_p1_f, UInt<5>("h010")) @[ifu_bp_ctl.scala 423:83] + node _T_5217 = bits(_T_5216, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5218 = eq(btb_rd_addr_p1_f, UInt<5>("h011")) @[ifu_bp_ctl.scala 423:83] + node _T_5219 = bits(_T_5218, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5220 = eq(btb_rd_addr_p1_f, UInt<5>("h012")) @[ifu_bp_ctl.scala 423:83] + node _T_5221 = bits(_T_5220, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5222 = eq(btb_rd_addr_p1_f, UInt<5>("h013")) @[ifu_bp_ctl.scala 423:83] + node _T_5223 = bits(_T_5222, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5224 = eq(btb_rd_addr_p1_f, UInt<5>("h014")) @[ifu_bp_ctl.scala 423:83] + node _T_5225 = bits(_T_5224, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5226 = eq(btb_rd_addr_p1_f, UInt<5>("h015")) @[ifu_bp_ctl.scala 423:83] + node _T_5227 = bits(_T_5226, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5228 = eq(btb_rd_addr_p1_f, UInt<5>("h016")) @[ifu_bp_ctl.scala 423:83] + node _T_5229 = bits(_T_5228, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5230 = eq(btb_rd_addr_p1_f, UInt<5>("h017")) @[ifu_bp_ctl.scala 423:83] + node _T_5231 = bits(_T_5230, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5232 = eq(btb_rd_addr_p1_f, UInt<5>("h018")) @[ifu_bp_ctl.scala 423:83] + node _T_5233 = bits(_T_5232, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5234 = eq(btb_rd_addr_p1_f, UInt<5>("h019")) @[ifu_bp_ctl.scala 423:83] + node _T_5235 = bits(_T_5234, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5236 = eq(btb_rd_addr_p1_f, UInt<5>("h01a")) @[ifu_bp_ctl.scala 423:83] + node _T_5237 = bits(_T_5236, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5238 = eq(btb_rd_addr_p1_f, UInt<5>("h01b")) @[ifu_bp_ctl.scala 423:83] + node _T_5239 = bits(_T_5238, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5240 = eq(btb_rd_addr_p1_f, UInt<5>("h01c")) @[ifu_bp_ctl.scala 423:83] + node _T_5241 = bits(_T_5240, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5242 = eq(btb_rd_addr_p1_f, UInt<5>("h01d")) @[ifu_bp_ctl.scala 423:83] + node _T_5243 = bits(_T_5242, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5244 = eq(btb_rd_addr_p1_f, UInt<5>("h01e")) @[ifu_bp_ctl.scala 423:83] + node _T_5245 = bits(_T_5244, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5246 = eq(btb_rd_addr_p1_f, UInt<5>("h01f")) @[ifu_bp_ctl.scala 423:83] + node _T_5247 = bits(_T_5246, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5248 = eq(btb_rd_addr_p1_f, UInt<6>("h020")) @[ifu_bp_ctl.scala 423:83] + node _T_5249 = bits(_T_5248, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5250 = eq(btb_rd_addr_p1_f, UInt<6>("h021")) @[ifu_bp_ctl.scala 423:83] + node _T_5251 = bits(_T_5250, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5252 = eq(btb_rd_addr_p1_f, UInt<6>("h022")) @[ifu_bp_ctl.scala 423:83] + node _T_5253 = bits(_T_5252, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5254 = eq(btb_rd_addr_p1_f, UInt<6>("h023")) @[ifu_bp_ctl.scala 423:83] + node _T_5255 = bits(_T_5254, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5256 = eq(btb_rd_addr_p1_f, UInt<6>("h024")) @[ifu_bp_ctl.scala 423:83] + node _T_5257 = bits(_T_5256, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5258 = eq(btb_rd_addr_p1_f, UInt<6>("h025")) @[ifu_bp_ctl.scala 423:83] + node _T_5259 = bits(_T_5258, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5260 = eq(btb_rd_addr_p1_f, UInt<6>("h026")) @[ifu_bp_ctl.scala 423:83] + node _T_5261 = bits(_T_5260, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5262 = eq(btb_rd_addr_p1_f, UInt<6>("h027")) @[ifu_bp_ctl.scala 423:83] + node _T_5263 = bits(_T_5262, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5264 = eq(btb_rd_addr_p1_f, UInt<6>("h028")) @[ifu_bp_ctl.scala 423:83] + node _T_5265 = bits(_T_5264, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5266 = eq(btb_rd_addr_p1_f, UInt<6>("h029")) @[ifu_bp_ctl.scala 423:83] + node _T_5267 = bits(_T_5266, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5268 = eq(btb_rd_addr_p1_f, UInt<6>("h02a")) @[ifu_bp_ctl.scala 423:83] + node _T_5269 = bits(_T_5268, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5270 = eq(btb_rd_addr_p1_f, UInt<6>("h02b")) @[ifu_bp_ctl.scala 423:83] + node _T_5271 = bits(_T_5270, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5272 = eq(btb_rd_addr_p1_f, UInt<6>("h02c")) @[ifu_bp_ctl.scala 423:83] + node _T_5273 = bits(_T_5272, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5274 = eq(btb_rd_addr_p1_f, UInt<6>("h02d")) @[ifu_bp_ctl.scala 423:83] + node _T_5275 = bits(_T_5274, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5276 = eq(btb_rd_addr_p1_f, UInt<6>("h02e")) @[ifu_bp_ctl.scala 423:83] + node _T_5277 = bits(_T_5276, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5278 = eq(btb_rd_addr_p1_f, UInt<6>("h02f")) @[ifu_bp_ctl.scala 423:83] + node _T_5279 = bits(_T_5278, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5280 = eq(btb_rd_addr_p1_f, UInt<6>("h030")) @[ifu_bp_ctl.scala 423:83] + node _T_5281 = bits(_T_5280, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5282 = eq(btb_rd_addr_p1_f, UInt<6>("h031")) @[ifu_bp_ctl.scala 423:83] + node _T_5283 = bits(_T_5282, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5284 = eq(btb_rd_addr_p1_f, UInt<6>("h032")) @[ifu_bp_ctl.scala 423:83] + node _T_5285 = bits(_T_5284, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5286 = eq(btb_rd_addr_p1_f, UInt<6>("h033")) @[ifu_bp_ctl.scala 423:83] + node _T_5287 = bits(_T_5286, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5288 = eq(btb_rd_addr_p1_f, UInt<6>("h034")) @[ifu_bp_ctl.scala 423:83] + node _T_5289 = bits(_T_5288, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5290 = eq(btb_rd_addr_p1_f, UInt<6>("h035")) @[ifu_bp_ctl.scala 423:83] + node _T_5291 = bits(_T_5290, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5292 = eq(btb_rd_addr_p1_f, UInt<6>("h036")) @[ifu_bp_ctl.scala 423:83] + node _T_5293 = bits(_T_5292, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5294 = eq(btb_rd_addr_p1_f, UInt<6>("h037")) @[ifu_bp_ctl.scala 423:83] + node _T_5295 = bits(_T_5294, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5296 = eq(btb_rd_addr_p1_f, UInt<6>("h038")) @[ifu_bp_ctl.scala 423:83] + node _T_5297 = bits(_T_5296, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5298 = eq(btb_rd_addr_p1_f, UInt<6>("h039")) @[ifu_bp_ctl.scala 423:83] + node _T_5299 = bits(_T_5298, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5300 = eq(btb_rd_addr_p1_f, UInt<6>("h03a")) @[ifu_bp_ctl.scala 423:83] + node _T_5301 = bits(_T_5300, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5302 = eq(btb_rd_addr_p1_f, UInt<6>("h03b")) @[ifu_bp_ctl.scala 423:83] + node _T_5303 = bits(_T_5302, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5304 = eq(btb_rd_addr_p1_f, UInt<6>("h03c")) @[ifu_bp_ctl.scala 423:83] + node _T_5305 = bits(_T_5304, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5306 = eq(btb_rd_addr_p1_f, UInt<6>("h03d")) @[ifu_bp_ctl.scala 423:83] + node _T_5307 = bits(_T_5306, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5308 = eq(btb_rd_addr_p1_f, UInt<6>("h03e")) @[ifu_bp_ctl.scala 423:83] + node _T_5309 = bits(_T_5308, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5310 = eq(btb_rd_addr_p1_f, UInt<6>("h03f")) @[ifu_bp_ctl.scala 423:83] + node _T_5311 = bits(_T_5310, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5312 = eq(btb_rd_addr_p1_f, UInt<7>("h040")) @[ifu_bp_ctl.scala 423:83] + node _T_5313 = bits(_T_5312, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5314 = eq(btb_rd_addr_p1_f, UInt<7>("h041")) @[ifu_bp_ctl.scala 423:83] + node _T_5315 = bits(_T_5314, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5316 = eq(btb_rd_addr_p1_f, UInt<7>("h042")) @[ifu_bp_ctl.scala 423:83] + node _T_5317 = bits(_T_5316, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5318 = eq(btb_rd_addr_p1_f, UInt<7>("h043")) @[ifu_bp_ctl.scala 423:83] + node _T_5319 = bits(_T_5318, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5320 = eq(btb_rd_addr_p1_f, UInt<7>("h044")) @[ifu_bp_ctl.scala 423:83] + node _T_5321 = bits(_T_5320, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5322 = eq(btb_rd_addr_p1_f, UInt<7>("h045")) @[ifu_bp_ctl.scala 423:83] + node _T_5323 = bits(_T_5322, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5324 = eq(btb_rd_addr_p1_f, UInt<7>("h046")) @[ifu_bp_ctl.scala 423:83] + node _T_5325 = bits(_T_5324, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5326 = eq(btb_rd_addr_p1_f, UInt<7>("h047")) @[ifu_bp_ctl.scala 423:83] + node _T_5327 = bits(_T_5326, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5328 = eq(btb_rd_addr_p1_f, UInt<7>("h048")) @[ifu_bp_ctl.scala 423:83] + node _T_5329 = bits(_T_5328, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5330 = eq(btb_rd_addr_p1_f, UInt<7>("h049")) @[ifu_bp_ctl.scala 423:83] + node _T_5331 = bits(_T_5330, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5332 = eq(btb_rd_addr_p1_f, UInt<7>("h04a")) @[ifu_bp_ctl.scala 423:83] + node _T_5333 = bits(_T_5332, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5334 = eq(btb_rd_addr_p1_f, UInt<7>("h04b")) @[ifu_bp_ctl.scala 423:83] + node _T_5335 = bits(_T_5334, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5336 = eq(btb_rd_addr_p1_f, UInt<7>("h04c")) @[ifu_bp_ctl.scala 423:83] + node _T_5337 = bits(_T_5336, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5338 = eq(btb_rd_addr_p1_f, UInt<7>("h04d")) @[ifu_bp_ctl.scala 423:83] + node _T_5339 = bits(_T_5338, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5340 = eq(btb_rd_addr_p1_f, UInt<7>("h04e")) @[ifu_bp_ctl.scala 423:83] + node _T_5341 = bits(_T_5340, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5342 = eq(btb_rd_addr_p1_f, UInt<7>("h04f")) @[ifu_bp_ctl.scala 423:83] + node _T_5343 = bits(_T_5342, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5344 = eq(btb_rd_addr_p1_f, UInt<7>("h050")) @[ifu_bp_ctl.scala 423:83] + node _T_5345 = bits(_T_5344, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5346 = eq(btb_rd_addr_p1_f, UInt<7>("h051")) @[ifu_bp_ctl.scala 423:83] + node _T_5347 = bits(_T_5346, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5348 = eq(btb_rd_addr_p1_f, UInt<7>("h052")) @[ifu_bp_ctl.scala 423:83] + node _T_5349 = bits(_T_5348, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5350 = eq(btb_rd_addr_p1_f, UInt<7>("h053")) @[ifu_bp_ctl.scala 423:83] + node _T_5351 = bits(_T_5350, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5352 = eq(btb_rd_addr_p1_f, UInt<7>("h054")) @[ifu_bp_ctl.scala 423:83] + node _T_5353 = bits(_T_5352, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5354 = eq(btb_rd_addr_p1_f, UInt<7>("h055")) @[ifu_bp_ctl.scala 423:83] + node _T_5355 = bits(_T_5354, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5356 = eq(btb_rd_addr_p1_f, UInt<7>("h056")) @[ifu_bp_ctl.scala 423:83] + node _T_5357 = bits(_T_5356, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5358 = eq(btb_rd_addr_p1_f, UInt<7>("h057")) @[ifu_bp_ctl.scala 423:83] + node _T_5359 = bits(_T_5358, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5360 = eq(btb_rd_addr_p1_f, UInt<7>("h058")) @[ifu_bp_ctl.scala 423:83] + node _T_5361 = bits(_T_5360, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5362 = eq(btb_rd_addr_p1_f, UInt<7>("h059")) @[ifu_bp_ctl.scala 423:83] + node _T_5363 = bits(_T_5362, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5364 = eq(btb_rd_addr_p1_f, UInt<7>("h05a")) @[ifu_bp_ctl.scala 423:83] + node _T_5365 = bits(_T_5364, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5366 = eq(btb_rd_addr_p1_f, UInt<7>("h05b")) @[ifu_bp_ctl.scala 423:83] + node _T_5367 = bits(_T_5366, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5368 = eq(btb_rd_addr_p1_f, UInt<7>("h05c")) @[ifu_bp_ctl.scala 423:83] + node _T_5369 = bits(_T_5368, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5370 = eq(btb_rd_addr_p1_f, UInt<7>("h05d")) @[ifu_bp_ctl.scala 423:83] + node _T_5371 = bits(_T_5370, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5372 = eq(btb_rd_addr_p1_f, UInt<7>("h05e")) @[ifu_bp_ctl.scala 423:83] + node _T_5373 = bits(_T_5372, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5374 = eq(btb_rd_addr_p1_f, UInt<7>("h05f")) @[ifu_bp_ctl.scala 423:83] + node _T_5375 = bits(_T_5374, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5376 = eq(btb_rd_addr_p1_f, UInt<7>("h060")) @[ifu_bp_ctl.scala 423:83] + node _T_5377 = bits(_T_5376, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5378 = eq(btb_rd_addr_p1_f, UInt<7>("h061")) @[ifu_bp_ctl.scala 423:83] + node _T_5379 = bits(_T_5378, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5380 = eq(btb_rd_addr_p1_f, UInt<7>("h062")) @[ifu_bp_ctl.scala 423:83] + node _T_5381 = bits(_T_5380, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5382 = eq(btb_rd_addr_p1_f, UInt<7>("h063")) @[ifu_bp_ctl.scala 423:83] + node _T_5383 = bits(_T_5382, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5384 = eq(btb_rd_addr_p1_f, UInt<7>("h064")) @[ifu_bp_ctl.scala 423:83] + node _T_5385 = bits(_T_5384, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5386 = eq(btb_rd_addr_p1_f, UInt<7>("h065")) @[ifu_bp_ctl.scala 423:83] + node _T_5387 = bits(_T_5386, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5388 = eq(btb_rd_addr_p1_f, UInt<7>("h066")) @[ifu_bp_ctl.scala 423:83] + node _T_5389 = bits(_T_5388, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5390 = eq(btb_rd_addr_p1_f, UInt<7>("h067")) @[ifu_bp_ctl.scala 423:83] + node _T_5391 = bits(_T_5390, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5392 = eq(btb_rd_addr_p1_f, UInt<7>("h068")) @[ifu_bp_ctl.scala 423:83] + node _T_5393 = bits(_T_5392, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5394 = eq(btb_rd_addr_p1_f, UInt<7>("h069")) @[ifu_bp_ctl.scala 423:83] + node _T_5395 = bits(_T_5394, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5396 = eq(btb_rd_addr_p1_f, UInt<7>("h06a")) @[ifu_bp_ctl.scala 423:83] + node _T_5397 = bits(_T_5396, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5398 = eq(btb_rd_addr_p1_f, UInt<7>("h06b")) @[ifu_bp_ctl.scala 423:83] + node _T_5399 = bits(_T_5398, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5400 = eq(btb_rd_addr_p1_f, UInt<7>("h06c")) @[ifu_bp_ctl.scala 423:83] + node _T_5401 = bits(_T_5400, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5402 = eq(btb_rd_addr_p1_f, UInt<7>("h06d")) @[ifu_bp_ctl.scala 423:83] + node _T_5403 = bits(_T_5402, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5404 = eq(btb_rd_addr_p1_f, UInt<7>("h06e")) @[ifu_bp_ctl.scala 423:83] + node _T_5405 = bits(_T_5404, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5406 = eq(btb_rd_addr_p1_f, UInt<7>("h06f")) @[ifu_bp_ctl.scala 423:83] + node _T_5407 = bits(_T_5406, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5408 = eq(btb_rd_addr_p1_f, UInt<7>("h070")) @[ifu_bp_ctl.scala 423:83] + node _T_5409 = bits(_T_5408, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5410 = eq(btb_rd_addr_p1_f, UInt<7>("h071")) @[ifu_bp_ctl.scala 423:83] + node _T_5411 = bits(_T_5410, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5412 = eq(btb_rd_addr_p1_f, UInt<7>("h072")) @[ifu_bp_ctl.scala 423:83] + node _T_5413 = bits(_T_5412, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5414 = eq(btb_rd_addr_p1_f, UInt<7>("h073")) @[ifu_bp_ctl.scala 423:83] + node _T_5415 = bits(_T_5414, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5416 = eq(btb_rd_addr_p1_f, UInt<7>("h074")) @[ifu_bp_ctl.scala 423:83] + node _T_5417 = bits(_T_5416, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5418 = eq(btb_rd_addr_p1_f, UInt<7>("h075")) @[ifu_bp_ctl.scala 423:83] + node _T_5419 = bits(_T_5418, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5420 = eq(btb_rd_addr_p1_f, UInt<7>("h076")) @[ifu_bp_ctl.scala 423:83] + node _T_5421 = bits(_T_5420, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5422 = eq(btb_rd_addr_p1_f, UInt<7>("h077")) @[ifu_bp_ctl.scala 423:83] + node _T_5423 = bits(_T_5422, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5424 = eq(btb_rd_addr_p1_f, UInt<7>("h078")) @[ifu_bp_ctl.scala 423:83] + node _T_5425 = bits(_T_5424, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5426 = eq(btb_rd_addr_p1_f, UInt<7>("h079")) @[ifu_bp_ctl.scala 423:83] + node _T_5427 = bits(_T_5426, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5428 = eq(btb_rd_addr_p1_f, UInt<7>("h07a")) @[ifu_bp_ctl.scala 423:83] + node _T_5429 = bits(_T_5428, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5430 = eq(btb_rd_addr_p1_f, UInt<7>("h07b")) @[ifu_bp_ctl.scala 423:83] + node _T_5431 = bits(_T_5430, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5432 = eq(btb_rd_addr_p1_f, UInt<7>("h07c")) @[ifu_bp_ctl.scala 423:83] + node _T_5433 = bits(_T_5432, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5434 = eq(btb_rd_addr_p1_f, UInt<7>("h07d")) @[ifu_bp_ctl.scala 423:83] + node _T_5435 = bits(_T_5434, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5436 = eq(btb_rd_addr_p1_f, UInt<7>("h07e")) @[ifu_bp_ctl.scala 423:83] + node _T_5437 = bits(_T_5436, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5438 = eq(btb_rd_addr_p1_f, UInt<7>("h07f")) @[ifu_bp_ctl.scala 423:83] + node _T_5439 = bits(_T_5438, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5440 = eq(btb_rd_addr_p1_f, UInt<8>("h080")) @[ifu_bp_ctl.scala 423:83] + node _T_5441 = bits(_T_5440, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5442 = eq(btb_rd_addr_p1_f, UInt<8>("h081")) @[ifu_bp_ctl.scala 423:83] + node _T_5443 = bits(_T_5442, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5444 = eq(btb_rd_addr_p1_f, UInt<8>("h082")) @[ifu_bp_ctl.scala 423:83] + node _T_5445 = bits(_T_5444, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5446 = eq(btb_rd_addr_p1_f, UInt<8>("h083")) @[ifu_bp_ctl.scala 423:83] + node _T_5447 = bits(_T_5446, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5448 = eq(btb_rd_addr_p1_f, UInt<8>("h084")) @[ifu_bp_ctl.scala 423:83] + node _T_5449 = bits(_T_5448, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5450 = eq(btb_rd_addr_p1_f, UInt<8>("h085")) @[ifu_bp_ctl.scala 423:83] + node _T_5451 = bits(_T_5450, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5452 = eq(btb_rd_addr_p1_f, UInt<8>("h086")) @[ifu_bp_ctl.scala 423:83] + node _T_5453 = bits(_T_5452, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5454 = eq(btb_rd_addr_p1_f, UInt<8>("h087")) @[ifu_bp_ctl.scala 423:83] + node _T_5455 = bits(_T_5454, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5456 = eq(btb_rd_addr_p1_f, UInt<8>("h088")) @[ifu_bp_ctl.scala 423:83] + node _T_5457 = bits(_T_5456, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5458 = eq(btb_rd_addr_p1_f, UInt<8>("h089")) @[ifu_bp_ctl.scala 423:83] + node _T_5459 = bits(_T_5458, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5460 = eq(btb_rd_addr_p1_f, UInt<8>("h08a")) @[ifu_bp_ctl.scala 423:83] + node _T_5461 = bits(_T_5460, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5462 = eq(btb_rd_addr_p1_f, UInt<8>("h08b")) @[ifu_bp_ctl.scala 423:83] + node _T_5463 = bits(_T_5462, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5464 = eq(btb_rd_addr_p1_f, UInt<8>("h08c")) @[ifu_bp_ctl.scala 423:83] + node _T_5465 = bits(_T_5464, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5466 = eq(btb_rd_addr_p1_f, UInt<8>("h08d")) @[ifu_bp_ctl.scala 423:83] + node _T_5467 = bits(_T_5466, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5468 = eq(btb_rd_addr_p1_f, UInt<8>("h08e")) @[ifu_bp_ctl.scala 423:83] + node _T_5469 = bits(_T_5468, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5470 = eq(btb_rd_addr_p1_f, UInt<8>("h08f")) @[ifu_bp_ctl.scala 423:83] + node _T_5471 = bits(_T_5470, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5472 = eq(btb_rd_addr_p1_f, UInt<8>("h090")) @[ifu_bp_ctl.scala 423:83] + node _T_5473 = bits(_T_5472, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5474 = eq(btb_rd_addr_p1_f, UInt<8>("h091")) @[ifu_bp_ctl.scala 423:83] + node _T_5475 = bits(_T_5474, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5476 = eq(btb_rd_addr_p1_f, UInt<8>("h092")) @[ifu_bp_ctl.scala 423:83] + node _T_5477 = bits(_T_5476, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5478 = eq(btb_rd_addr_p1_f, UInt<8>("h093")) @[ifu_bp_ctl.scala 423:83] + node _T_5479 = bits(_T_5478, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5480 = eq(btb_rd_addr_p1_f, UInt<8>("h094")) @[ifu_bp_ctl.scala 423:83] + node _T_5481 = bits(_T_5480, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5482 = eq(btb_rd_addr_p1_f, UInt<8>("h095")) @[ifu_bp_ctl.scala 423:83] + node _T_5483 = bits(_T_5482, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5484 = eq(btb_rd_addr_p1_f, UInt<8>("h096")) @[ifu_bp_ctl.scala 423:83] + node _T_5485 = bits(_T_5484, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5486 = eq(btb_rd_addr_p1_f, UInt<8>("h097")) @[ifu_bp_ctl.scala 423:83] + node _T_5487 = bits(_T_5486, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5488 = eq(btb_rd_addr_p1_f, UInt<8>("h098")) @[ifu_bp_ctl.scala 423:83] + node _T_5489 = bits(_T_5488, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5490 = eq(btb_rd_addr_p1_f, UInt<8>("h099")) @[ifu_bp_ctl.scala 423:83] + node _T_5491 = bits(_T_5490, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5492 = eq(btb_rd_addr_p1_f, UInt<8>("h09a")) @[ifu_bp_ctl.scala 423:83] + node _T_5493 = bits(_T_5492, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5494 = eq(btb_rd_addr_p1_f, UInt<8>("h09b")) @[ifu_bp_ctl.scala 423:83] + node _T_5495 = bits(_T_5494, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5496 = eq(btb_rd_addr_p1_f, UInt<8>("h09c")) @[ifu_bp_ctl.scala 423:83] + node _T_5497 = bits(_T_5496, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5498 = eq(btb_rd_addr_p1_f, UInt<8>("h09d")) @[ifu_bp_ctl.scala 423:83] + node _T_5499 = bits(_T_5498, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5500 = eq(btb_rd_addr_p1_f, UInt<8>("h09e")) @[ifu_bp_ctl.scala 423:83] + node _T_5501 = bits(_T_5500, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5502 = eq(btb_rd_addr_p1_f, UInt<8>("h09f")) @[ifu_bp_ctl.scala 423:83] + node _T_5503 = bits(_T_5502, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5504 = eq(btb_rd_addr_p1_f, UInt<8>("h0a0")) @[ifu_bp_ctl.scala 423:83] + node _T_5505 = bits(_T_5504, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5506 = eq(btb_rd_addr_p1_f, UInt<8>("h0a1")) @[ifu_bp_ctl.scala 423:83] + node _T_5507 = bits(_T_5506, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5508 = eq(btb_rd_addr_p1_f, UInt<8>("h0a2")) @[ifu_bp_ctl.scala 423:83] + node _T_5509 = bits(_T_5508, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5510 = eq(btb_rd_addr_p1_f, UInt<8>("h0a3")) @[ifu_bp_ctl.scala 423:83] + node _T_5511 = bits(_T_5510, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5512 = eq(btb_rd_addr_p1_f, UInt<8>("h0a4")) @[ifu_bp_ctl.scala 423:83] + node _T_5513 = bits(_T_5512, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5514 = eq(btb_rd_addr_p1_f, UInt<8>("h0a5")) @[ifu_bp_ctl.scala 423:83] + node _T_5515 = bits(_T_5514, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5516 = eq(btb_rd_addr_p1_f, UInt<8>("h0a6")) @[ifu_bp_ctl.scala 423:83] + node _T_5517 = bits(_T_5516, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5518 = eq(btb_rd_addr_p1_f, UInt<8>("h0a7")) @[ifu_bp_ctl.scala 423:83] + node _T_5519 = bits(_T_5518, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5520 = eq(btb_rd_addr_p1_f, UInt<8>("h0a8")) @[ifu_bp_ctl.scala 423:83] + node _T_5521 = bits(_T_5520, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5522 = eq(btb_rd_addr_p1_f, UInt<8>("h0a9")) @[ifu_bp_ctl.scala 423:83] + node _T_5523 = bits(_T_5522, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5524 = eq(btb_rd_addr_p1_f, UInt<8>("h0aa")) @[ifu_bp_ctl.scala 423:83] + node _T_5525 = bits(_T_5524, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5526 = eq(btb_rd_addr_p1_f, UInt<8>("h0ab")) @[ifu_bp_ctl.scala 423:83] + node _T_5527 = bits(_T_5526, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5528 = eq(btb_rd_addr_p1_f, UInt<8>("h0ac")) @[ifu_bp_ctl.scala 423:83] + node _T_5529 = bits(_T_5528, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5530 = eq(btb_rd_addr_p1_f, UInt<8>("h0ad")) @[ifu_bp_ctl.scala 423:83] + node _T_5531 = bits(_T_5530, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5532 = eq(btb_rd_addr_p1_f, UInt<8>("h0ae")) @[ifu_bp_ctl.scala 423:83] + node _T_5533 = bits(_T_5532, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5534 = eq(btb_rd_addr_p1_f, UInt<8>("h0af")) @[ifu_bp_ctl.scala 423:83] + node _T_5535 = bits(_T_5534, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5536 = eq(btb_rd_addr_p1_f, UInt<8>("h0b0")) @[ifu_bp_ctl.scala 423:83] + node _T_5537 = bits(_T_5536, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5538 = eq(btb_rd_addr_p1_f, UInt<8>("h0b1")) @[ifu_bp_ctl.scala 423:83] + node _T_5539 = bits(_T_5538, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5540 = eq(btb_rd_addr_p1_f, UInt<8>("h0b2")) @[ifu_bp_ctl.scala 423:83] + node _T_5541 = bits(_T_5540, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5542 = eq(btb_rd_addr_p1_f, UInt<8>("h0b3")) @[ifu_bp_ctl.scala 423:83] + node _T_5543 = bits(_T_5542, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5544 = eq(btb_rd_addr_p1_f, UInt<8>("h0b4")) @[ifu_bp_ctl.scala 423:83] + node _T_5545 = bits(_T_5544, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5546 = eq(btb_rd_addr_p1_f, UInt<8>("h0b5")) @[ifu_bp_ctl.scala 423:83] + node _T_5547 = bits(_T_5546, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5548 = eq(btb_rd_addr_p1_f, UInt<8>("h0b6")) @[ifu_bp_ctl.scala 423:83] + node _T_5549 = bits(_T_5548, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5550 = eq(btb_rd_addr_p1_f, UInt<8>("h0b7")) @[ifu_bp_ctl.scala 423:83] + node _T_5551 = bits(_T_5550, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5552 = eq(btb_rd_addr_p1_f, UInt<8>("h0b8")) @[ifu_bp_ctl.scala 423:83] + node _T_5553 = bits(_T_5552, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5554 = eq(btb_rd_addr_p1_f, UInt<8>("h0b9")) @[ifu_bp_ctl.scala 423:83] + node _T_5555 = bits(_T_5554, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5556 = eq(btb_rd_addr_p1_f, UInt<8>("h0ba")) @[ifu_bp_ctl.scala 423:83] + node _T_5557 = bits(_T_5556, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5558 = eq(btb_rd_addr_p1_f, UInt<8>("h0bb")) @[ifu_bp_ctl.scala 423:83] + node _T_5559 = bits(_T_5558, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5560 = eq(btb_rd_addr_p1_f, UInt<8>("h0bc")) @[ifu_bp_ctl.scala 423:83] + node _T_5561 = bits(_T_5560, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5562 = eq(btb_rd_addr_p1_f, UInt<8>("h0bd")) @[ifu_bp_ctl.scala 423:83] + node _T_5563 = bits(_T_5562, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5564 = eq(btb_rd_addr_p1_f, UInt<8>("h0be")) @[ifu_bp_ctl.scala 423:83] + node _T_5565 = bits(_T_5564, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5566 = eq(btb_rd_addr_p1_f, UInt<8>("h0bf")) @[ifu_bp_ctl.scala 423:83] + node _T_5567 = bits(_T_5566, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5568 = eq(btb_rd_addr_p1_f, UInt<8>("h0c0")) @[ifu_bp_ctl.scala 423:83] + node _T_5569 = bits(_T_5568, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5570 = eq(btb_rd_addr_p1_f, UInt<8>("h0c1")) @[ifu_bp_ctl.scala 423:83] + node _T_5571 = bits(_T_5570, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5572 = eq(btb_rd_addr_p1_f, UInt<8>("h0c2")) @[ifu_bp_ctl.scala 423:83] + node _T_5573 = bits(_T_5572, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5574 = eq(btb_rd_addr_p1_f, UInt<8>("h0c3")) @[ifu_bp_ctl.scala 423:83] + node _T_5575 = bits(_T_5574, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5576 = eq(btb_rd_addr_p1_f, UInt<8>("h0c4")) @[ifu_bp_ctl.scala 423:83] + node _T_5577 = bits(_T_5576, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5578 = eq(btb_rd_addr_p1_f, UInt<8>("h0c5")) @[ifu_bp_ctl.scala 423:83] + node _T_5579 = bits(_T_5578, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5580 = eq(btb_rd_addr_p1_f, UInt<8>("h0c6")) @[ifu_bp_ctl.scala 423:83] + node _T_5581 = bits(_T_5580, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5582 = eq(btb_rd_addr_p1_f, UInt<8>("h0c7")) @[ifu_bp_ctl.scala 423:83] + node _T_5583 = bits(_T_5582, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5584 = eq(btb_rd_addr_p1_f, UInt<8>("h0c8")) @[ifu_bp_ctl.scala 423:83] + node _T_5585 = bits(_T_5584, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5586 = eq(btb_rd_addr_p1_f, UInt<8>("h0c9")) @[ifu_bp_ctl.scala 423:83] + node _T_5587 = bits(_T_5586, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5588 = eq(btb_rd_addr_p1_f, UInt<8>("h0ca")) @[ifu_bp_ctl.scala 423:83] + node _T_5589 = bits(_T_5588, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5590 = eq(btb_rd_addr_p1_f, UInt<8>("h0cb")) @[ifu_bp_ctl.scala 423:83] + node _T_5591 = bits(_T_5590, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5592 = eq(btb_rd_addr_p1_f, UInt<8>("h0cc")) @[ifu_bp_ctl.scala 423:83] + node _T_5593 = bits(_T_5592, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5594 = eq(btb_rd_addr_p1_f, UInt<8>("h0cd")) @[ifu_bp_ctl.scala 423:83] + node _T_5595 = bits(_T_5594, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5596 = eq(btb_rd_addr_p1_f, UInt<8>("h0ce")) @[ifu_bp_ctl.scala 423:83] + node _T_5597 = bits(_T_5596, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5598 = eq(btb_rd_addr_p1_f, UInt<8>("h0cf")) @[ifu_bp_ctl.scala 423:83] + node _T_5599 = bits(_T_5598, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5600 = eq(btb_rd_addr_p1_f, UInt<8>("h0d0")) @[ifu_bp_ctl.scala 423:83] + node _T_5601 = bits(_T_5600, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5602 = eq(btb_rd_addr_p1_f, UInt<8>("h0d1")) @[ifu_bp_ctl.scala 423:83] + node _T_5603 = bits(_T_5602, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5604 = eq(btb_rd_addr_p1_f, UInt<8>("h0d2")) @[ifu_bp_ctl.scala 423:83] + node _T_5605 = bits(_T_5604, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5606 = eq(btb_rd_addr_p1_f, UInt<8>("h0d3")) @[ifu_bp_ctl.scala 423:83] + node _T_5607 = bits(_T_5606, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5608 = eq(btb_rd_addr_p1_f, UInt<8>("h0d4")) @[ifu_bp_ctl.scala 423:83] + node _T_5609 = bits(_T_5608, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5610 = eq(btb_rd_addr_p1_f, UInt<8>("h0d5")) @[ifu_bp_ctl.scala 423:83] + node _T_5611 = bits(_T_5610, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5612 = eq(btb_rd_addr_p1_f, UInt<8>("h0d6")) @[ifu_bp_ctl.scala 423:83] + node _T_5613 = bits(_T_5612, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5614 = eq(btb_rd_addr_p1_f, UInt<8>("h0d7")) @[ifu_bp_ctl.scala 423:83] + node _T_5615 = bits(_T_5614, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5616 = eq(btb_rd_addr_p1_f, UInt<8>("h0d8")) @[ifu_bp_ctl.scala 423:83] + node _T_5617 = bits(_T_5616, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5618 = eq(btb_rd_addr_p1_f, UInt<8>("h0d9")) @[ifu_bp_ctl.scala 423:83] + node _T_5619 = bits(_T_5618, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5620 = eq(btb_rd_addr_p1_f, UInt<8>("h0da")) @[ifu_bp_ctl.scala 423:83] + node _T_5621 = bits(_T_5620, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5622 = eq(btb_rd_addr_p1_f, UInt<8>("h0db")) @[ifu_bp_ctl.scala 423:83] + node _T_5623 = bits(_T_5622, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5624 = eq(btb_rd_addr_p1_f, UInt<8>("h0dc")) @[ifu_bp_ctl.scala 423:83] + node _T_5625 = bits(_T_5624, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5626 = eq(btb_rd_addr_p1_f, UInt<8>("h0dd")) @[ifu_bp_ctl.scala 423:83] + node _T_5627 = bits(_T_5626, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5628 = eq(btb_rd_addr_p1_f, UInt<8>("h0de")) @[ifu_bp_ctl.scala 423:83] + node _T_5629 = bits(_T_5628, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5630 = eq(btb_rd_addr_p1_f, UInt<8>("h0df")) @[ifu_bp_ctl.scala 423:83] + node _T_5631 = bits(_T_5630, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5632 = eq(btb_rd_addr_p1_f, UInt<8>("h0e0")) @[ifu_bp_ctl.scala 423:83] + node _T_5633 = bits(_T_5632, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5634 = eq(btb_rd_addr_p1_f, UInt<8>("h0e1")) @[ifu_bp_ctl.scala 423:83] + node _T_5635 = bits(_T_5634, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5636 = eq(btb_rd_addr_p1_f, UInt<8>("h0e2")) @[ifu_bp_ctl.scala 423:83] + node _T_5637 = bits(_T_5636, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5638 = eq(btb_rd_addr_p1_f, UInt<8>("h0e3")) @[ifu_bp_ctl.scala 423:83] + node _T_5639 = bits(_T_5638, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5640 = eq(btb_rd_addr_p1_f, UInt<8>("h0e4")) @[ifu_bp_ctl.scala 423:83] + node _T_5641 = bits(_T_5640, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5642 = eq(btb_rd_addr_p1_f, UInt<8>("h0e5")) @[ifu_bp_ctl.scala 423:83] + node _T_5643 = bits(_T_5642, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5644 = eq(btb_rd_addr_p1_f, UInt<8>("h0e6")) @[ifu_bp_ctl.scala 423:83] + node _T_5645 = bits(_T_5644, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5646 = eq(btb_rd_addr_p1_f, UInt<8>("h0e7")) @[ifu_bp_ctl.scala 423:83] + node _T_5647 = bits(_T_5646, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5648 = eq(btb_rd_addr_p1_f, UInt<8>("h0e8")) @[ifu_bp_ctl.scala 423:83] + node _T_5649 = bits(_T_5648, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5650 = eq(btb_rd_addr_p1_f, UInt<8>("h0e9")) @[ifu_bp_ctl.scala 423:83] + node _T_5651 = bits(_T_5650, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5652 = eq(btb_rd_addr_p1_f, UInt<8>("h0ea")) @[ifu_bp_ctl.scala 423:83] + node _T_5653 = bits(_T_5652, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5654 = eq(btb_rd_addr_p1_f, UInt<8>("h0eb")) @[ifu_bp_ctl.scala 423:83] + node _T_5655 = bits(_T_5654, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5656 = eq(btb_rd_addr_p1_f, UInt<8>("h0ec")) @[ifu_bp_ctl.scala 423:83] + node _T_5657 = bits(_T_5656, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5658 = eq(btb_rd_addr_p1_f, UInt<8>("h0ed")) @[ifu_bp_ctl.scala 423:83] + node _T_5659 = bits(_T_5658, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5660 = eq(btb_rd_addr_p1_f, UInt<8>("h0ee")) @[ifu_bp_ctl.scala 423:83] + node _T_5661 = bits(_T_5660, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5662 = eq(btb_rd_addr_p1_f, UInt<8>("h0ef")) @[ifu_bp_ctl.scala 423:83] + node _T_5663 = bits(_T_5662, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5664 = eq(btb_rd_addr_p1_f, UInt<8>("h0f0")) @[ifu_bp_ctl.scala 423:83] + node _T_5665 = bits(_T_5664, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5666 = eq(btb_rd_addr_p1_f, UInt<8>("h0f1")) @[ifu_bp_ctl.scala 423:83] + node _T_5667 = bits(_T_5666, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5668 = eq(btb_rd_addr_p1_f, UInt<8>("h0f2")) @[ifu_bp_ctl.scala 423:83] + node _T_5669 = bits(_T_5668, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5670 = eq(btb_rd_addr_p1_f, UInt<8>("h0f3")) @[ifu_bp_ctl.scala 423:83] + node _T_5671 = bits(_T_5670, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5672 = eq(btb_rd_addr_p1_f, UInt<8>("h0f4")) @[ifu_bp_ctl.scala 423:83] + node _T_5673 = bits(_T_5672, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5674 = eq(btb_rd_addr_p1_f, UInt<8>("h0f5")) @[ifu_bp_ctl.scala 423:83] + node _T_5675 = bits(_T_5674, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5676 = eq(btb_rd_addr_p1_f, UInt<8>("h0f6")) @[ifu_bp_ctl.scala 423:83] + node _T_5677 = bits(_T_5676, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5678 = eq(btb_rd_addr_p1_f, UInt<8>("h0f7")) @[ifu_bp_ctl.scala 423:83] + node _T_5679 = bits(_T_5678, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5680 = eq(btb_rd_addr_p1_f, UInt<8>("h0f8")) @[ifu_bp_ctl.scala 423:83] + node _T_5681 = bits(_T_5680, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5682 = eq(btb_rd_addr_p1_f, UInt<8>("h0f9")) @[ifu_bp_ctl.scala 423:83] + node _T_5683 = bits(_T_5682, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5684 = eq(btb_rd_addr_p1_f, UInt<8>("h0fa")) @[ifu_bp_ctl.scala 423:83] + node _T_5685 = bits(_T_5684, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5686 = eq(btb_rd_addr_p1_f, UInt<8>("h0fb")) @[ifu_bp_ctl.scala 423:83] + node _T_5687 = bits(_T_5686, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5688 = eq(btb_rd_addr_p1_f, UInt<8>("h0fc")) @[ifu_bp_ctl.scala 423:83] + node _T_5689 = bits(_T_5688, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5690 = eq(btb_rd_addr_p1_f, UInt<8>("h0fd")) @[ifu_bp_ctl.scala 423:83] + node _T_5691 = bits(_T_5690, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5692 = eq(btb_rd_addr_p1_f, UInt<8>("h0fe")) @[ifu_bp_ctl.scala 423:83] + node _T_5693 = bits(_T_5692, 0, 0) @[ifu_bp_ctl.scala 423:91] + node _T_5694 = eq(btb_rd_addr_p1_f, UInt<8>("h0ff")) @[ifu_bp_ctl.scala 423:83] + node _T_5695 = bits(_T_5694, 0, 0) @[ifu_bp_ctl.scala 423:91] node _T_5696 = mux(_T_5185, btb_bank0_rd_data_way1_out_0, UInt<1>("h00")) @[Mux.scala 27:72] node _T_5697 = mux(_T_5187, btb_bank0_rd_data_way1_out_1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_5698 = mux(_T_5189, btb_bank0_rd_data_way1_out_2, UInt<1>("h00")) @[Mux.scala 27:72] @@ -39697,8 +39697,8 @@ circuit quasar_wrapper : node _T_6206 = or(_T_6205, _T_5951) @[Mux.scala 27:72] wire _T_6207 : UInt @[Mux.scala 27:72] _T_6207 <= _T_6206 @[Mux.scala 27:72] - btb_bank0_rd_data_way1_p1_f <= _T_6207 @[ifu_bp_ctl.scala 422:31] - wire bht_bank_clken : UInt<1>[16][2] @[ifu_bp_ctl.scala 424:28] + btb_bank0_rd_data_way1_p1_f <= _T_6207 @[ifu_bp_ctl.scala 423:31] + wire bht_bank_clken : UInt<1>[16][2] @[ifu_bp_ctl.scala 425:28] inst rvclkhdr_522 of rvclkhdr_616 @[lib.scala 327:22] rvclkhdr_522.clock <= clock rvclkhdr_522.reset <= reset @@ -39891,17800 +39891,17800 @@ circuit quasar_wrapper : rvclkhdr_553.io.clk <= clock @[lib.scala 328:17] rvclkhdr_553.io.en <= bht_bank_clken[1][15] @[lib.scala 329:16] rvclkhdr_553.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_6208 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 428:40] - node _T_6209 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6210 = eq(_T_6209, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:109] - node _T_6211 = or(_T_6210, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6212 = and(_T_6208, _T_6211) @[ifu_bp_ctl.scala 428:44] - node _T_6213 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 429:40] - node _T_6214 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6215 = eq(_T_6214, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:109] - node _T_6216 = or(_T_6215, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6217 = and(_T_6213, _T_6216) @[ifu_bp_ctl.scala 429:44] - node _T_6218 = or(_T_6212, _T_6217) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[0][0] <= _T_6218 @[ifu_bp_ctl.scala 428:26] - node _T_6219 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 428:40] - node _T_6220 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6221 = eq(_T_6220, UInt<1>("h01")) @[ifu_bp_ctl.scala 428:109] - node _T_6222 = or(_T_6221, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6223 = and(_T_6219, _T_6222) @[ifu_bp_ctl.scala 428:44] - node _T_6224 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 429:40] - node _T_6225 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6226 = eq(_T_6225, UInt<1>("h01")) @[ifu_bp_ctl.scala 429:109] - node _T_6227 = or(_T_6226, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6228 = and(_T_6224, _T_6227) @[ifu_bp_ctl.scala 429:44] - node _T_6229 = or(_T_6223, _T_6228) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[0][1] <= _T_6229 @[ifu_bp_ctl.scala 428:26] - node _T_6230 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 428:40] - node _T_6231 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6232 = eq(_T_6231, UInt<2>("h02")) @[ifu_bp_ctl.scala 428:109] - node _T_6233 = or(_T_6232, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6234 = and(_T_6230, _T_6233) @[ifu_bp_ctl.scala 428:44] - node _T_6235 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 429:40] - node _T_6236 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6237 = eq(_T_6236, UInt<2>("h02")) @[ifu_bp_ctl.scala 429:109] - node _T_6238 = or(_T_6237, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6239 = and(_T_6235, _T_6238) @[ifu_bp_ctl.scala 429:44] - node _T_6240 = or(_T_6234, _T_6239) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[0][2] <= _T_6240 @[ifu_bp_ctl.scala 428:26] - node _T_6241 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 428:40] - node _T_6242 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6243 = eq(_T_6242, UInt<2>("h03")) @[ifu_bp_ctl.scala 428:109] - node _T_6244 = or(_T_6243, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6245 = and(_T_6241, _T_6244) @[ifu_bp_ctl.scala 428:44] - node _T_6246 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 429:40] - node _T_6247 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6248 = eq(_T_6247, UInt<2>("h03")) @[ifu_bp_ctl.scala 429:109] - node _T_6249 = or(_T_6248, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6250 = and(_T_6246, _T_6249) @[ifu_bp_ctl.scala 429:44] - node _T_6251 = or(_T_6245, _T_6250) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[0][3] <= _T_6251 @[ifu_bp_ctl.scala 428:26] - node _T_6252 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 428:40] - node _T_6253 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6254 = eq(_T_6253, UInt<3>("h04")) @[ifu_bp_ctl.scala 428:109] - node _T_6255 = or(_T_6254, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6256 = and(_T_6252, _T_6255) @[ifu_bp_ctl.scala 428:44] - node _T_6257 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 429:40] - node _T_6258 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6259 = eq(_T_6258, UInt<3>("h04")) @[ifu_bp_ctl.scala 429:109] - node _T_6260 = or(_T_6259, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6261 = and(_T_6257, _T_6260) @[ifu_bp_ctl.scala 429:44] - node _T_6262 = or(_T_6256, _T_6261) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[0][4] <= _T_6262 @[ifu_bp_ctl.scala 428:26] - node _T_6263 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 428:40] - node _T_6264 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6265 = eq(_T_6264, UInt<3>("h05")) @[ifu_bp_ctl.scala 428:109] - node _T_6266 = or(_T_6265, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6267 = and(_T_6263, _T_6266) @[ifu_bp_ctl.scala 428:44] - node _T_6268 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 429:40] - node _T_6269 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6270 = eq(_T_6269, UInt<3>("h05")) @[ifu_bp_ctl.scala 429:109] - node _T_6271 = or(_T_6270, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6272 = and(_T_6268, _T_6271) @[ifu_bp_ctl.scala 429:44] - node _T_6273 = or(_T_6267, _T_6272) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[0][5] <= _T_6273 @[ifu_bp_ctl.scala 428:26] - node _T_6274 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 428:40] - node _T_6275 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6276 = eq(_T_6275, UInt<3>("h06")) @[ifu_bp_ctl.scala 428:109] - node _T_6277 = or(_T_6276, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6278 = and(_T_6274, _T_6277) @[ifu_bp_ctl.scala 428:44] - node _T_6279 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 429:40] - node _T_6280 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6281 = eq(_T_6280, UInt<3>("h06")) @[ifu_bp_ctl.scala 429:109] - node _T_6282 = or(_T_6281, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6283 = and(_T_6279, _T_6282) @[ifu_bp_ctl.scala 429:44] - node _T_6284 = or(_T_6278, _T_6283) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[0][6] <= _T_6284 @[ifu_bp_ctl.scala 428:26] - node _T_6285 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 428:40] - node _T_6286 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6287 = eq(_T_6286, UInt<3>("h07")) @[ifu_bp_ctl.scala 428:109] - node _T_6288 = or(_T_6287, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6289 = and(_T_6285, _T_6288) @[ifu_bp_ctl.scala 428:44] - node _T_6290 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 429:40] - node _T_6291 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6292 = eq(_T_6291, UInt<3>("h07")) @[ifu_bp_ctl.scala 429:109] - node _T_6293 = or(_T_6292, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6294 = and(_T_6290, _T_6293) @[ifu_bp_ctl.scala 429:44] - node _T_6295 = or(_T_6289, _T_6294) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[0][7] <= _T_6295 @[ifu_bp_ctl.scala 428:26] - node _T_6296 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 428:40] - node _T_6297 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6298 = eq(_T_6297, UInt<4>("h08")) @[ifu_bp_ctl.scala 428:109] - node _T_6299 = or(_T_6298, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6300 = and(_T_6296, _T_6299) @[ifu_bp_ctl.scala 428:44] - node _T_6301 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 429:40] - node _T_6302 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6303 = eq(_T_6302, UInt<4>("h08")) @[ifu_bp_ctl.scala 429:109] - node _T_6304 = or(_T_6303, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6305 = and(_T_6301, _T_6304) @[ifu_bp_ctl.scala 429:44] - node _T_6306 = or(_T_6300, _T_6305) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[0][8] <= _T_6306 @[ifu_bp_ctl.scala 428:26] - node _T_6307 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 428:40] - node _T_6308 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6309 = eq(_T_6308, UInt<4>("h09")) @[ifu_bp_ctl.scala 428:109] - node _T_6310 = or(_T_6309, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6311 = and(_T_6307, _T_6310) @[ifu_bp_ctl.scala 428:44] - node _T_6312 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 429:40] - node _T_6313 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6314 = eq(_T_6313, UInt<4>("h09")) @[ifu_bp_ctl.scala 429:109] - node _T_6315 = or(_T_6314, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6316 = and(_T_6312, _T_6315) @[ifu_bp_ctl.scala 429:44] - node _T_6317 = or(_T_6311, _T_6316) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[0][9] <= _T_6317 @[ifu_bp_ctl.scala 428:26] - node _T_6318 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 428:40] - node _T_6319 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6320 = eq(_T_6319, UInt<4>("h0a")) @[ifu_bp_ctl.scala 428:109] - node _T_6321 = or(_T_6320, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6322 = and(_T_6318, _T_6321) @[ifu_bp_ctl.scala 428:44] - node _T_6323 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 429:40] - node _T_6324 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6325 = eq(_T_6324, UInt<4>("h0a")) @[ifu_bp_ctl.scala 429:109] - node _T_6326 = or(_T_6325, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6327 = and(_T_6323, _T_6326) @[ifu_bp_ctl.scala 429:44] - node _T_6328 = or(_T_6322, _T_6327) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[0][10] <= _T_6328 @[ifu_bp_ctl.scala 428:26] - node _T_6329 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 428:40] - node _T_6330 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6331 = eq(_T_6330, UInt<4>("h0b")) @[ifu_bp_ctl.scala 428:109] - node _T_6332 = or(_T_6331, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6333 = and(_T_6329, _T_6332) @[ifu_bp_ctl.scala 428:44] - node _T_6334 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 429:40] - node _T_6335 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6336 = eq(_T_6335, UInt<4>("h0b")) @[ifu_bp_ctl.scala 429:109] - node _T_6337 = or(_T_6336, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6338 = and(_T_6334, _T_6337) @[ifu_bp_ctl.scala 429:44] - node _T_6339 = or(_T_6333, _T_6338) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[0][11] <= _T_6339 @[ifu_bp_ctl.scala 428:26] - node _T_6340 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 428:40] - node _T_6341 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6342 = eq(_T_6341, UInt<4>("h0c")) @[ifu_bp_ctl.scala 428:109] - node _T_6343 = or(_T_6342, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6344 = and(_T_6340, _T_6343) @[ifu_bp_ctl.scala 428:44] - node _T_6345 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 429:40] - node _T_6346 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6347 = eq(_T_6346, UInt<4>("h0c")) @[ifu_bp_ctl.scala 429:109] - node _T_6348 = or(_T_6347, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6349 = and(_T_6345, _T_6348) @[ifu_bp_ctl.scala 429:44] - node _T_6350 = or(_T_6344, _T_6349) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[0][12] <= _T_6350 @[ifu_bp_ctl.scala 428:26] - node _T_6351 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 428:40] - node _T_6352 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6353 = eq(_T_6352, UInt<4>("h0d")) @[ifu_bp_ctl.scala 428:109] - node _T_6354 = or(_T_6353, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6355 = and(_T_6351, _T_6354) @[ifu_bp_ctl.scala 428:44] - node _T_6356 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 429:40] - node _T_6357 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6358 = eq(_T_6357, UInt<4>("h0d")) @[ifu_bp_ctl.scala 429:109] - node _T_6359 = or(_T_6358, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6360 = and(_T_6356, _T_6359) @[ifu_bp_ctl.scala 429:44] - node _T_6361 = or(_T_6355, _T_6360) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[0][13] <= _T_6361 @[ifu_bp_ctl.scala 428:26] - node _T_6362 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 428:40] - node _T_6363 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6364 = eq(_T_6363, UInt<4>("h0e")) @[ifu_bp_ctl.scala 428:109] - node _T_6365 = or(_T_6364, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6366 = and(_T_6362, _T_6365) @[ifu_bp_ctl.scala 428:44] - node _T_6367 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 429:40] - node _T_6368 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6369 = eq(_T_6368, UInt<4>("h0e")) @[ifu_bp_ctl.scala 429:109] - node _T_6370 = or(_T_6369, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6371 = and(_T_6367, _T_6370) @[ifu_bp_ctl.scala 429:44] - node _T_6372 = or(_T_6366, _T_6371) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[0][14] <= _T_6372 @[ifu_bp_ctl.scala 428:26] - node _T_6373 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 428:40] - node _T_6374 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6375 = eq(_T_6374, UInt<4>("h0f")) @[ifu_bp_ctl.scala 428:109] - node _T_6376 = or(_T_6375, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6377 = and(_T_6373, _T_6376) @[ifu_bp_ctl.scala 428:44] - node _T_6378 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 429:40] - node _T_6379 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6380 = eq(_T_6379, UInt<4>("h0f")) @[ifu_bp_ctl.scala 429:109] - node _T_6381 = or(_T_6380, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6382 = and(_T_6378, _T_6381) @[ifu_bp_ctl.scala 429:44] - node _T_6383 = or(_T_6377, _T_6382) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[0][15] <= _T_6383 @[ifu_bp_ctl.scala 428:26] - node _T_6384 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 428:40] - node _T_6385 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6386 = eq(_T_6385, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:109] - node _T_6387 = or(_T_6386, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6388 = and(_T_6384, _T_6387) @[ifu_bp_ctl.scala 428:44] - node _T_6389 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 429:40] - node _T_6390 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6391 = eq(_T_6390, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:109] - node _T_6392 = or(_T_6391, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6393 = and(_T_6389, _T_6392) @[ifu_bp_ctl.scala 429:44] - node _T_6394 = or(_T_6388, _T_6393) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[1][0] <= _T_6394 @[ifu_bp_ctl.scala 428:26] - node _T_6395 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 428:40] - node _T_6396 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6397 = eq(_T_6396, UInt<1>("h01")) @[ifu_bp_ctl.scala 428:109] - node _T_6398 = or(_T_6397, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6399 = and(_T_6395, _T_6398) @[ifu_bp_ctl.scala 428:44] - node _T_6400 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 429:40] - node _T_6401 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6402 = eq(_T_6401, UInt<1>("h01")) @[ifu_bp_ctl.scala 429:109] - node _T_6403 = or(_T_6402, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6404 = and(_T_6400, _T_6403) @[ifu_bp_ctl.scala 429:44] - node _T_6405 = or(_T_6399, _T_6404) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[1][1] <= _T_6405 @[ifu_bp_ctl.scala 428:26] - node _T_6406 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 428:40] - node _T_6407 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6408 = eq(_T_6407, UInt<2>("h02")) @[ifu_bp_ctl.scala 428:109] - node _T_6409 = or(_T_6408, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6410 = and(_T_6406, _T_6409) @[ifu_bp_ctl.scala 428:44] - node _T_6411 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 429:40] - node _T_6412 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6413 = eq(_T_6412, UInt<2>("h02")) @[ifu_bp_ctl.scala 429:109] - node _T_6414 = or(_T_6413, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6415 = and(_T_6411, _T_6414) @[ifu_bp_ctl.scala 429:44] - node _T_6416 = or(_T_6410, _T_6415) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[1][2] <= _T_6416 @[ifu_bp_ctl.scala 428:26] - node _T_6417 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 428:40] - node _T_6418 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6419 = eq(_T_6418, UInt<2>("h03")) @[ifu_bp_ctl.scala 428:109] - node _T_6420 = or(_T_6419, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6421 = and(_T_6417, _T_6420) @[ifu_bp_ctl.scala 428:44] - node _T_6422 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 429:40] - node _T_6423 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6424 = eq(_T_6423, UInt<2>("h03")) @[ifu_bp_ctl.scala 429:109] - node _T_6425 = or(_T_6424, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6426 = and(_T_6422, _T_6425) @[ifu_bp_ctl.scala 429:44] - node _T_6427 = or(_T_6421, _T_6426) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[1][3] <= _T_6427 @[ifu_bp_ctl.scala 428:26] - node _T_6428 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 428:40] - node _T_6429 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6430 = eq(_T_6429, UInt<3>("h04")) @[ifu_bp_ctl.scala 428:109] - node _T_6431 = or(_T_6430, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6432 = and(_T_6428, _T_6431) @[ifu_bp_ctl.scala 428:44] - node _T_6433 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 429:40] - node _T_6434 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6435 = eq(_T_6434, UInt<3>("h04")) @[ifu_bp_ctl.scala 429:109] - node _T_6436 = or(_T_6435, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6437 = and(_T_6433, _T_6436) @[ifu_bp_ctl.scala 429:44] - node _T_6438 = or(_T_6432, _T_6437) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[1][4] <= _T_6438 @[ifu_bp_ctl.scala 428:26] - node _T_6439 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 428:40] - node _T_6440 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6441 = eq(_T_6440, UInt<3>("h05")) @[ifu_bp_ctl.scala 428:109] - node _T_6442 = or(_T_6441, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6443 = and(_T_6439, _T_6442) @[ifu_bp_ctl.scala 428:44] - node _T_6444 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 429:40] - node _T_6445 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6446 = eq(_T_6445, UInt<3>("h05")) @[ifu_bp_ctl.scala 429:109] - node _T_6447 = or(_T_6446, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6448 = and(_T_6444, _T_6447) @[ifu_bp_ctl.scala 429:44] - node _T_6449 = or(_T_6443, _T_6448) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[1][5] <= _T_6449 @[ifu_bp_ctl.scala 428:26] - node _T_6450 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 428:40] - node _T_6451 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6452 = eq(_T_6451, UInt<3>("h06")) @[ifu_bp_ctl.scala 428:109] - node _T_6453 = or(_T_6452, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6454 = and(_T_6450, _T_6453) @[ifu_bp_ctl.scala 428:44] - node _T_6455 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 429:40] - node _T_6456 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6457 = eq(_T_6456, UInt<3>("h06")) @[ifu_bp_ctl.scala 429:109] - node _T_6458 = or(_T_6457, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6459 = and(_T_6455, _T_6458) @[ifu_bp_ctl.scala 429:44] - node _T_6460 = or(_T_6454, _T_6459) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[1][6] <= _T_6460 @[ifu_bp_ctl.scala 428:26] - node _T_6461 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 428:40] - node _T_6462 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6463 = eq(_T_6462, UInt<3>("h07")) @[ifu_bp_ctl.scala 428:109] - node _T_6464 = or(_T_6463, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6465 = and(_T_6461, _T_6464) @[ifu_bp_ctl.scala 428:44] - node _T_6466 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 429:40] - node _T_6467 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6468 = eq(_T_6467, UInt<3>("h07")) @[ifu_bp_ctl.scala 429:109] - node _T_6469 = or(_T_6468, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6470 = and(_T_6466, _T_6469) @[ifu_bp_ctl.scala 429:44] - node _T_6471 = or(_T_6465, _T_6470) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[1][7] <= _T_6471 @[ifu_bp_ctl.scala 428:26] - node _T_6472 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 428:40] - node _T_6473 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6474 = eq(_T_6473, UInt<4>("h08")) @[ifu_bp_ctl.scala 428:109] - node _T_6475 = or(_T_6474, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6476 = and(_T_6472, _T_6475) @[ifu_bp_ctl.scala 428:44] - node _T_6477 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 429:40] - node _T_6478 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6479 = eq(_T_6478, UInt<4>("h08")) @[ifu_bp_ctl.scala 429:109] - node _T_6480 = or(_T_6479, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6481 = and(_T_6477, _T_6480) @[ifu_bp_ctl.scala 429:44] - node _T_6482 = or(_T_6476, _T_6481) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[1][8] <= _T_6482 @[ifu_bp_ctl.scala 428:26] - node _T_6483 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 428:40] - node _T_6484 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6485 = eq(_T_6484, UInt<4>("h09")) @[ifu_bp_ctl.scala 428:109] - node _T_6486 = or(_T_6485, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6487 = and(_T_6483, _T_6486) @[ifu_bp_ctl.scala 428:44] - node _T_6488 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 429:40] - node _T_6489 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6490 = eq(_T_6489, UInt<4>("h09")) @[ifu_bp_ctl.scala 429:109] - node _T_6491 = or(_T_6490, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6492 = and(_T_6488, _T_6491) @[ifu_bp_ctl.scala 429:44] - node _T_6493 = or(_T_6487, _T_6492) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[1][9] <= _T_6493 @[ifu_bp_ctl.scala 428:26] - node _T_6494 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 428:40] - node _T_6495 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6496 = eq(_T_6495, UInt<4>("h0a")) @[ifu_bp_ctl.scala 428:109] - node _T_6497 = or(_T_6496, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6498 = and(_T_6494, _T_6497) @[ifu_bp_ctl.scala 428:44] - node _T_6499 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 429:40] - node _T_6500 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6501 = eq(_T_6500, UInt<4>("h0a")) @[ifu_bp_ctl.scala 429:109] - node _T_6502 = or(_T_6501, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6503 = and(_T_6499, _T_6502) @[ifu_bp_ctl.scala 429:44] - node _T_6504 = or(_T_6498, _T_6503) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[1][10] <= _T_6504 @[ifu_bp_ctl.scala 428:26] - node _T_6505 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 428:40] - node _T_6506 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6507 = eq(_T_6506, UInt<4>("h0b")) @[ifu_bp_ctl.scala 428:109] - node _T_6508 = or(_T_6507, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6509 = and(_T_6505, _T_6508) @[ifu_bp_ctl.scala 428:44] - node _T_6510 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 429:40] - node _T_6511 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6512 = eq(_T_6511, UInt<4>("h0b")) @[ifu_bp_ctl.scala 429:109] - node _T_6513 = or(_T_6512, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6514 = and(_T_6510, _T_6513) @[ifu_bp_ctl.scala 429:44] - node _T_6515 = or(_T_6509, _T_6514) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[1][11] <= _T_6515 @[ifu_bp_ctl.scala 428:26] - node _T_6516 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 428:40] - node _T_6517 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6518 = eq(_T_6517, UInt<4>("h0c")) @[ifu_bp_ctl.scala 428:109] - node _T_6519 = or(_T_6518, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6520 = and(_T_6516, _T_6519) @[ifu_bp_ctl.scala 428:44] - node _T_6521 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 429:40] - node _T_6522 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6523 = eq(_T_6522, UInt<4>("h0c")) @[ifu_bp_ctl.scala 429:109] - node _T_6524 = or(_T_6523, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6525 = and(_T_6521, _T_6524) @[ifu_bp_ctl.scala 429:44] - node _T_6526 = or(_T_6520, _T_6525) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[1][12] <= _T_6526 @[ifu_bp_ctl.scala 428:26] - node _T_6527 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 428:40] - node _T_6528 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6529 = eq(_T_6528, UInt<4>("h0d")) @[ifu_bp_ctl.scala 428:109] - node _T_6530 = or(_T_6529, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6531 = and(_T_6527, _T_6530) @[ifu_bp_ctl.scala 428:44] - node _T_6532 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 429:40] - node _T_6533 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6534 = eq(_T_6533, UInt<4>("h0d")) @[ifu_bp_ctl.scala 429:109] - node _T_6535 = or(_T_6534, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6536 = and(_T_6532, _T_6535) @[ifu_bp_ctl.scala 429:44] - node _T_6537 = or(_T_6531, _T_6536) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[1][13] <= _T_6537 @[ifu_bp_ctl.scala 428:26] - node _T_6538 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 428:40] - node _T_6539 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6540 = eq(_T_6539, UInt<4>("h0e")) @[ifu_bp_ctl.scala 428:109] - node _T_6541 = or(_T_6540, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6542 = and(_T_6538, _T_6541) @[ifu_bp_ctl.scala 428:44] - node _T_6543 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 429:40] - node _T_6544 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6545 = eq(_T_6544, UInt<4>("h0e")) @[ifu_bp_ctl.scala 429:109] - node _T_6546 = or(_T_6545, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6547 = and(_T_6543, _T_6546) @[ifu_bp_ctl.scala 429:44] - node _T_6548 = or(_T_6542, _T_6547) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[1][14] <= _T_6548 @[ifu_bp_ctl.scala 428:26] - node _T_6549 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 428:40] - node _T_6550 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 428:60] - node _T_6551 = eq(_T_6550, UInt<4>("h0f")) @[ifu_bp_ctl.scala 428:109] - node _T_6552 = or(_T_6551, UInt<1>("h00")) @[ifu_bp_ctl.scala 428:117] - node _T_6553 = and(_T_6549, _T_6552) @[ifu_bp_ctl.scala 428:44] - node _T_6554 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 429:40] - node _T_6555 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 429:60] - node _T_6556 = eq(_T_6555, UInt<4>("h0f")) @[ifu_bp_ctl.scala 429:109] - node _T_6557 = or(_T_6556, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] - node _T_6558 = and(_T_6554, _T_6557) @[ifu_bp_ctl.scala 429:44] - node _T_6559 = or(_T_6553, _T_6558) @[ifu_bp_ctl.scala 428:142] - bht_bank_clken[1][15] <= _T_6559 @[ifu_bp_ctl.scala 428:26] - node _T_6560 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6561 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6562 = eq(_T_6561, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_6563 = and(_T_6560, _T_6562) @[ifu_bp_ctl.scala 434:23] - node _T_6564 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6565 = eq(_T_6564, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_6566 = and(_T_6563, _T_6565) @[ifu_bp_ctl.scala 434:81] - node _T_6567 = or(_T_6566, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6568 = bits(_T_6567, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_0_0 = mux(_T_6568, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6569 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6570 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6571 = eq(_T_6570, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_6572 = and(_T_6569, _T_6571) @[ifu_bp_ctl.scala 434:23] - node _T_6573 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6574 = eq(_T_6573, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_6575 = and(_T_6572, _T_6574) @[ifu_bp_ctl.scala 434:81] - node _T_6576 = or(_T_6575, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6577 = bits(_T_6576, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_0_1 = mux(_T_6577, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6578 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6579 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6580 = eq(_T_6579, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_6581 = and(_T_6578, _T_6580) @[ifu_bp_ctl.scala 434:23] - node _T_6582 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6583 = eq(_T_6582, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_6584 = and(_T_6581, _T_6583) @[ifu_bp_ctl.scala 434:81] - node _T_6585 = or(_T_6584, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6586 = bits(_T_6585, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_0_2 = mux(_T_6586, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6587 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6588 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6589 = eq(_T_6588, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_6590 = and(_T_6587, _T_6589) @[ifu_bp_ctl.scala 434:23] - node _T_6591 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6592 = eq(_T_6591, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_6593 = and(_T_6590, _T_6592) @[ifu_bp_ctl.scala 434:81] - node _T_6594 = or(_T_6593, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6595 = bits(_T_6594, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_0_3 = mux(_T_6595, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6596 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6597 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6598 = eq(_T_6597, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_6599 = and(_T_6596, _T_6598) @[ifu_bp_ctl.scala 434:23] - node _T_6600 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6601 = eq(_T_6600, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_6602 = and(_T_6599, _T_6601) @[ifu_bp_ctl.scala 434:81] - node _T_6603 = or(_T_6602, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6604 = bits(_T_6603, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_0_4 = mux(_T_6604, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6605 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6606 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6607 = eq(_T_6606, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_6608 = and(_T_6605, _T_6607) @[ifu_bp_ctl.scala 434:23] - node _T_6609 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6610 = eq(_T_6609, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_6611 = and(_T_6608, _T_6610) @[ifu_bp_ctl.scala 434:81] - node _T_6612 = or(_T_6611, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6613 = bits(_T_6612, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_0_5 = mux(_T_6613, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6614 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6615 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6616 = eq(_T_6615, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_6617 = and(_T_6614, _T_6616) @[ifu_bp_ctl.scala 434:23] - node _T_6618 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6619 = eq(_T_6618, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_6620 = and(_T_6617, _T_6619) @[ifu_bp_ctl.scala 434:81] - node _T_6621 = or(_T_6620, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6622 = bits(_T_6621, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_0_6 = mux(_T_6622, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6623 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6624 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6625 = eq(_T_6624, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_6626 = and(_T_6623, _T_6625) @[ifu_bp_ctl.scala 434:23] - node _T_6627 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6628 = eq(_T_6627, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_6629 = and(_T_6626, _T_6628) @[ifu_bp_ctl.scala 434:81] - node _T_6630 = or(_T_6629, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6631 = bits(_T_6630, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_0_7 = mux(_T_6631, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6632 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6633 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6634 = eq(_T_6633, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_6635 = and(_T_6632, _T_6634) @[ifu_bp_ctl.scala 434:23] - node _T_6636 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6637 = eq(_T_6636, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_6638 = and(_T_6635, _T_6637) @[ifu_bp_ctl.scala 434:81] - node _T_6639 = or(_T_6638, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6640 = bits(_T_6639, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_0_8 = mux(_T_6640, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6641 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6642 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6643 = eq(_T_6642, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_6644 = and(_T_6641, _T_6643) @[ifu_bp_ctl.scala 434:23] - node _T_6645 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6646 = eq(_T_6645, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_6647 = and(_T_6644, _T_6646) @[ifu_bp_ctl.scala 434:81] - node _T_6648 = or(_T_6647, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6649 = bits(_T_6648, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_0_9 = mux(_T_6649, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6650 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6651 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6652 = eq(_T_6651, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_6653 = and(_T_6650, _T_6652) @[ifu_bp_ctl.scala 434:23] - node _T_6654 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6655 = eq(_T_6654, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_6656 = and(_T_6653, _T_6655) @[ifu_bp_ctl.scala 434:81] - node _T_6657 = or(_T_6656, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6658 = bits(_T_6657, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_0_10 = mux(_T_6658, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6659 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6660 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6661 = eq(_T_6660, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_6662 = and(_T_6659, _T_6661) @[ifu_bp_ctl.scala 434:23] - node _T_6663 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6664 = eq(_T_6663, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_6665 = and(_T_6662, _T_6664) @[ifu_bp_ctl.scala 434:81] - node _T_6666 = or(_T_6665, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6667 = bits(_T_6666, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_0_11 = mux(_T_6667, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6668 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6669 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6670 = eq(_T_6669, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_6671 = and(_T_6668, _T_6670) @[ifu_bp_ctl.scala 434:23] - node _T_6672 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6673 = eq(_T_6672, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_6674 = and(_T_6671, _T_6673) @[ifu_bp_ctl.scala 434:81] - node _T_6675 = or(_T_6674, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6676 = bits(_T_6675, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_0_12 = mux(_T_6676, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6677 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6678 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6679 = eq(_T_6678, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_6680 = and(_T_6677, _T_6679) @[ifu_bp_ctl.scala 434:23] - node _T_6681 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6682 = eq(_T_6681, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_6683 = and(_T_6680, _T_6682) @[ifu_bp_ctl.scala 434:81] - node _T_6684 = or(_T_6683, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6685 = bits(_T_6684, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_0_13 = mux(_T_6685, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6686 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6687 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6688 = eq(_T_6687, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_6689 = and(_T_6686, _T_6688) @[ifu_bp_ctl.scala 434:23] - node _T_6690 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6691 = eq(_T_6690, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_6692 = and(_T_6689, _T_6691) @[ifu_bp_ctl.scala 434:81] - node _T_6693 = or(_T_6692, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6694 = bits(_T_6693, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_0_14 = mux(_T_6694, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6695 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6696 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6697 = eq(_T_6696, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_6698 = and(_T_6695, _T_6697) @[ifu_bp_ctl.scala 434:23] - node _T_6699 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6700 = eq(_T_6699, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_6701 = and(_T_6698, _T_6700) @[ifu_bp_ctl.scala 434:81] - node _T_6702 = or(_T_6701, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6703 = bits(_T_6702, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_0_15 = mux(_T_6703, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6704 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6705 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6706 = eq(_T_6705, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_6707 = and(_T_6704, _T_6706) @[ifu_bp_ctl.scala 434:23] - node _T_6708 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6709 = eq(_T_6708, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_6710 = and(_T_6707, _T_6709) @[ifu_bp_ctl.scala 434:81] - node _T_6711 = or(_T_6710, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6712 = bits(_T_6711, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_1_0 = mux(_T_6712, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6713 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6714 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6715 = eq(_T_6714, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_6716 = and(_T_6713, _T_6715) @[ifu_bp_ctl.scala 434:23] - node _T_6717 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6718 = eq(_T_6717, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_6719 = and(_T_6716, _T_6718) @[ifu_bp_ctl.scala 434:81] - node _T_6720 = or(_T_6719, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6721 = bits(_T_6720, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_1_1 = mux(_T_6721, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6722 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6723 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6724 = eq(_T_6723, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_6725 = and(_T_6722, _T_6724) @[ifu_bp_ctl.scala 434:23] - node _T_6726 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6727 = eq(_T_6726, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_6728 = and(_T_6725, _T_6727) @[ifu_bp_ctl.scala 434:81] - node _T_6729 = or(_T_6728, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6730 = bits(_T_6729, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_1_2 = mux(_T_6730, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6731 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6732 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6733 = eq(_T_6732, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_6734 = and(_T_6731, _T_6733) @[ifu_bp_ctl.scala 434:23] - node _T_6735 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6736 = eq(_T_6735, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_6737 = and(_T_6734, _T_6736) @[ifu_bp_ctl.scala 434:81] - node _T_6738 = or(_T_6737, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6739 = bits(_T_6738, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_1_3 = mux(_T_6739, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6740 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6741 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6742 = eq(_T_6741, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_6743 = and(_T_6740, _T_6742) @[ifu_bp_ctl.scala 434:23] - node _T_6744 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6745 = eq(_T_6744, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_6746 = and(_T_6743, _T_6745) @[ifu_bp_ctl.scala 434:81] - node _T_6747 = or(_T_6746, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6748 = bits(_T_6747, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_1_4 = mux(_T_6748, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6749 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6750 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6751 = eq(_T_6750, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_6752 = and(_T_6749, _T_6751) @[ifu_bp_ctl.scala 434:23] - node _T_6753 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6754 = eq(_T_6753, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_6755 = and(_T_6752, _T_6754) @[ifu_bp_ctl.scala 434:81] - node _T_6756 = or(_T_6755, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6757 = bits(_T_6756, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_1_5 = mux(_T_6757, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6758 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6759 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6760 = eq(_T_6759, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_6761 = and(_T_6758, _T_6760) @[ifu_bp_ctl.scala 434:23] - node _T_6762 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6763 = eq(_T_6762, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_6764 = and(_T_6761, _T_6763) @[ifu_bp_ctl.scala 434:81] - node _T_6765 = or(_T_6764, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6766 = bits(_T_6765, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_1_6 = mux(_T_6766, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6767 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6768 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6769 = eq(_T_6768, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_6770 = and(_T_6767, _T_6769) @[ifu_bp_ctl.scala 434:23] - node _T_6771 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6772 = eq(_T_6771, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_6773 = and(_T_6770, _T_6772) @[ifu_bp_ctl.scala 434:81] - node _T_6774 = or(_T_6773, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6775 = bits(_T_6774, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_1_7 = mux(_T_6775, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6776 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6777 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6778 = eq(_T_6777, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_6779 = and(_T_6776, _T_6778) @[ifu_bp_ctl.scala 434:23] - node _T_6780 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6781 = eq(_T_6780, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_6782 = and(_T_6779, _T_6781) @[ifu_bp_ctl.scala 434:81] - node _T_6783 = or(_T_6782, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6784 = bits(_T_6783, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_1_8 = mux(_T_6784, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6785 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6786 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6787 = eq(_T_6786, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_6788 = and(_T_6785, _T_6787) @[ifu_bp_ctl.scala 434:23] - node _T_6789 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6790 = eq(_T_6789, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_6791 = and(_T_6788, _T_6790) @[ifu_bp_ctl.scala 434:81] - node _T_6792 = or(_T_6791, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6793 = bits(_T_6792, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_1_9 = mux(_T_6793, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6794 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6795 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6796 = eq(_T_6795, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_6797 = and(_T_6794, _T_6796) @[ifu_bp_ctl.scala 434:23] - node _T_6798 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6799 = eq(_T_6798, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_6800 = and(_T_6797, _T_6799) @[ifu_bp_ctl.scala 434:81] - node _T_6801 = or(_T_6800, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6802 = bits(_T_6801, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_1_10 = mux(_T_6802, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6803 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6804 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6805 = eq(_T_6804, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_6806 = and(_T_6803, _T_6805) @[ifu_bp_ctl.scala 434:23] - node _T_6807 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6808 = eq(_T_6807, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_6809 = and(_T_6806, _T_6808) @[ifu_bp_ctl.scala 434:81] - node _T_6810 = or(_T_6809, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6811 = bits(_T_6810, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_1_11 = mux(_T_6811, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6812 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6813 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6814 = eq(_T_6813, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_6815 = and(_T_6812, _T_6814) @[ifu_bp_ctl.scala 434:23] - node _T_6816 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6817 = eq(_T_6816, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_6818 = and(_T_6815, _T_6817) @[ifu_bp_ctl.scala 434:81] - node _T_6819 = or(_T_6818, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6820 = bits(_T_6819, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_1_12 = mux(_T_6820, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6821 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6822 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6823 = eq(_T_6822, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_6824 = and(_T_6821, _T_6823) @[ifu_bp_ctl.scala 434:23] - node _T_6825 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6826 = eq(_T_6825, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_6827 = and(_T_6824, _T_6826) @[ifu_bp_ctl.scala 434:81] - node _T_6828 = or(_T_6827, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6829 = bits(_T_6828, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_1_13 = mux(_T_6829, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6830 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6831 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6832 = eq(_T_6831, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_6833 = and(_T_6830, _T_6832) @[ifu_bp_ctl.scala 434:23] - node _T_6834 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6835 = eq(_T_6834, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_6836 = and(_T_6833, _T_6835) @[ifu_bp_ctl.scala 434:81] - node _T_6837 = or(_T_6836, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6838 = bits(_T_6837, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_1_14 = mux(_T_6838, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6839 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6840 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6841 = eq(_T_6840, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_6842 = and(_T_6839, _T_6841) @[ifu_bp_ctl.scala 434:23] - node _T_6843 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6844 = eq(_T_6843, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_6845 = and(_T_6842, _T_6844) @[ifu_bp_ctl.scala 434:81] - node _T_6846 = or(_T_6845, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6847 = bits(_T_6846, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_1_15 = mux(_T_6847, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6848 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6849 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6850 = eq(_T_6849, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_6851 = and(_T_6848, _T_6850) @[ifu_bp_ctl.scala 434:23] - node _T_6852 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6853 = eq(_T_6852, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_6854 = and(_T_6851, _T_6853) @[ifu_bp_ctl.scala 434:81] - node _T_6855 = or(_T_6854, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6856 = bits(_T_6855, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_2_0 = mux(_T_6856, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6857 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6858 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6859 = eq(_T_6858, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_6860 = and(_T_6857, _T_6859) @[ifu_bp_ctl.scala 434:23] - node _T_6861 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6862 = eq(_T_6861, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_6863 = and(_T_6860, _T_6862) @[ifu_bp_ctl.scala 434:81] - node _T_6864 = or(_T_6863, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6865 = bits(_T_6864, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_2_1 = mux(_T_6865, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6866 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6867 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6868 = eq(_T_6867, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_6869 = and(_T_6866, _T_6868) @[ifu_bp_ctl.scala 434:23] - node _T_6870 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6871 = eq(_T_6870, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_6872 = and(_T_6869, _T_6871) @[ifu_bp_ctl.scala 434:81] - node _T_6873 = or(_T_6872, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6874 = bits(_T_6873, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_2_2 = mux(_T_6874, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6875 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6876 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6877 = eq(_T_6876, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_6878 = and(_T_6875, _T_6877) @[ifu_bp_ctl.scala 434:23] - node _T_6879 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6880 = eq(_T_6879, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_6881 = and(_T_6878, _T_6880) @[ifu_bp_ctl.scala 434:81] - node _T_6882 = or(_T_6881, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6883 = bits(_T_6882, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_2_3 = mux(_T_6883, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6884 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6885 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6886 = eq(_T_6885, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_6887 = and(_T_6884, _T_6886) @[ifu_bp_ctl.scala 434:23] - node _T_6888 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6889 = eq(_T_6888, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_6890 = and(_T_6887, _T_6889) @[ifu_bp_ctl.scala 434:81] - node _T_6891 = or(_T_6890, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6892 = bits(_T_6891, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_2_4 = mux(_T_6892, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6893 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6894 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6895 = eq(_T_6894, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_6896 = and(_T_6893, _T_6895) @[ifu_bp_ctl.scala 434:23] - node _T_6897 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6898 = eq(_T_6897, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_6899 = and(_T_6896, _T_6898) @[ifu_bp_ctl.scala 434:81] - node _T_6900 = or(_T_6899, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6901 = bits(_T_6900, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_2_5 = mux(_T_6901, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6902 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6903 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6904 = eq(_T_6903, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_6905 = and(_T_6902, _T_6904) @[ifu_bp_ctl.scala 434:23] - node _T_6906 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6907 = eq(_T_6906, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_6908 = and(_T_6905, _T_6907) @[ifu_bp_ctl.scala 434:81] - node _T_6909 = or(_T_6908, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6910 = bits(_T_6909, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_2_6 = mux(_T_6910, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6911 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6912 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6913 = eq(_T_6912, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_6914 = and(_T_6911, _T_6913) @[ifu_bp_ctl.scala 434:23] - node _T_6915 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6916 = eq(_T_6915, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_6917 = and(_T_6914, _T_6916) @[ifu_bp_ctl.scala 434:81] - node _T_6918 = or(_T_6917, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6919 = bits(_T_6918, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_2_7 = mux(_T_6919, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6920 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6921 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6922 = eq(_T_6921, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_6923 = and(_T_6920, _T_6922) @[ifu_bp_ctl.scala 434:23] - node _T_6924 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6925 = eq(_T_6924, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_6926 = and(_T_6923, _T_6925) @[ifu_bp_ctl.scala 434:81] - node _T_6927 = or(_T_6926, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6928 = bits(_T_6927, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_2_8 = mux(_T_6928, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6929 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6930 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6931 = eq(_T_6930, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_6932 = and(_T_6929, _T_6931) @[ifu_bp_ctl.scala 434:23] - node _T_6933 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6934 = eq(_T_6933, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_6935 = and(_T_6932, _T_6934) @[ifu_bp_ctl.scala 434:81] - node _T_6936 = or(_T_6935, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6937 = bits(_T_6936, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_2_9 = mux(_T_6937, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6938 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6939 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6940 = eq(_T_6939, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_6941 = and(_T_6938, _T_6940) @[ifu_bp_ctl.scala 434:23] - node _T_6942 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6943 = eq(_T_6942, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_6944 = and(_T_6941, _T_6943) @[ifu_bp_ctl.scala 434:81] - node _T_6945 = or(_T_6944, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6946 = bits(_T_6945, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_2_10 = mux(_T_6946, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6947 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6948 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6949 = eq(_T_6948, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_6950 = and(_T_6947, _T_6949) @[ifu_bp_ctl.scala 434:23] - node _T_6951 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6952 = eq(_T_6951, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_6953 = and(_T_6950, _T_6952) @[ifu_bp_ctl.scala 434:81] - node _T_6954 = or(_T_6953, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6955 = bits(_T_6954, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_2_11 = mux(_T_6955, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6956 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6957 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6958 = eq(_T_6957, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_6959 = and(_T_6956, _T_6958) @[ifu_bp_ctl.scala 434:23] - node _T_6960 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6961 = eq(_T_6960, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_6962 = and(_T_6959, _T_6961) @[ifu_bp_ctl.scala 434:81] - node _T_6963 = or(_T_6962, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6964 = bits(_T_6963, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_2_12 = mux(_T_6964, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6965 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6966 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6967 = eq(_T_6966, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_6968 = and(_T_6965, _T_6967) @[ifu_bp_ctl.scala 434:23] - node _T_6969 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6970 = eq(_T_6969, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_6971 = and(_T_6968, _T_6970) @[ifu_bp_ctl.scala 434:81] - node _T_6972 = or(_T_6971, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6973 = bits(_T_6972, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_2_13 = mux(_T_6973, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6974 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6975 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6976 = eq(_T_6975, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_6977 = and(_T_6974, _T_6976) @[ifu_bp_ctl.scala 434:23] - node _T_6978 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6979 = eq(_T_6978, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_6980 = and(_T_6977, _T_6979) @[ifu_bp_ctl.scala 434:81] - node _T_6981 = or(_T_6980, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6982 = bits(_T_6981, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_2_14 = mux(_T_6982, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6983 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6984 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6985 = eq(_T_6984, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_6986 = and(_T_6983, _T_6985) @[ifu_bp_ctl.scala 434:23] - node _T_6987 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6988 = eq(_T_6987, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_6989 = and(_T_6986, _T_6988) @[ifu_bp_ctl.scala 434:81] - node _T_6990 = or(_T_6989, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_6991 = bits(_T_6990, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_2_15 = mux(_T_6991, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_6992 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_6993 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_6994 = eq(_T_6993, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_6995 = and(_T_6992, _T_6994) @[ifu_bp_ctl.scala 434:23] - node _T_6996 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_6997 = eq(_T_6996, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_6998 = and(_T_6995, _T_6997) @[ifu_bp_ctl.scala 434:81] - node _T_6999 = or(_T_6998, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7000 = bits(_T_6999, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_3_0 = mux(_T_7000, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7001 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7002 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7003 = eq(_T_7002, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_7004 = and(_T_7001, _T_7003) @[ifu_bp_ctl.scala 434:23] - node _T_7005 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7006 = eq(_T_7005, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_7007 = and(_T_7004, _T_7006) @[ifu_bp_ctl.scala 434:81] - node _T_7008 = or(_T_7007, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7009 = bits(_T_7008, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_3_1 = mux(_T_7009, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7010 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7011 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7012 = eq(_T_7011, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_7013 = and(_T_7010, _T_7012) @[ifu_bp_ctl.scala 434:23] - node _T_7014 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7015 = eq(_T_7014, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_7016 = and(_T_7013, _T_7015) @[ifu_bp_ctl.scala 434:81] - node _T_7017 = or(_T_7016, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7018 = bits(_T_7017, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_3_2 = mux(_T_7018, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7019 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7020 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7021 = eq(_T_7020, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_7022 = and(_T_7019, _T_7021) @[ifu_bp_ctl.scala 434:23] - node _T_7023 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7024 = eq(_T_7023, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_7025 = and(_T_7022, _T_7024) @[ifu_bp_ctl.scala 434:81] - node _T_7026 = or(_T_7025, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7027 = bits(_T_7026, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_3_3 = mux(_T_7027, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7028 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7029 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7030 = eq(_T_7029, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_7031 = and(_T_7028, _T_7030) @[ifu_bp_ctl.scala 434:23] - node _T_7032 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7033 = eq(_T_7032, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_7034 = and(_T_7031, _T_7033) @[ifu_bp_ctl.scala 434:81] - node _T_7035 = or(_T_7034, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7036 = bits(_T_7035, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_3_4 = mux(_T_7036, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7037 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7038 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7039 = eq(_T_7038, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_7040 = and(_T_7037, _T_7039) @[ifu_bp_ctl.scala 434:23] - node _T_7041 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7042 = eq(_T_7041, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_7043 = and(_T_7040, _T_7042) @[ifu_bp_ctl.scala 434:81] - node _T_7044 = or(_T_7043, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7045 = bits(_T_7044, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_3_5 = mux(_T_7045, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7046 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7047 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7048 = eq(_T_7047, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_7049 = and(_T_7046, _T_7048) @[ifu_bp_ctl.scala 434:23] - node _T_7050 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7051 = eq(_T_7050, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_7052 = and(_T_7049, _T_7051) @[ifu_bp_ctl.scala 434:81] - node _T_7053 = or(_T_7052, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7054 = bits(_T_7053, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_3_6 = mux(_T_7054, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7055 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7056 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7057 = eq(_T_7056, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_7058 = and(_T_7055, _T_7057) @[ifu_bp_ctl.scala 434:23] - node _T_7059 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7060 = eq(_T_7059, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_7061 = and(_T_7058, _T_7060) @[ifu_bp_ctl.scala 434:81] - node _T_7062 = or(_T_7061, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7063 = bits(_T_7062, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_3_7 = mux(_T_7063, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7064 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7065 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7066 = eq(_T_7065, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_7067 = and(_T_7064, _T_7066) @[ifu_bp_ctl.scala 434:23] - node _T_7068 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7069 = eq(_T_7068, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_7070 = and(_T_7067, _T_7069) @[ifu_bp_ctl.scala 434:81] - node _T_7071 = or(_T_7070, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7072 = bits(_T_7071, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_3_8 = mux(_T_7072, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7073 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7074 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7075 = eq(_T_7074, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_7076 = and(_T_7073, _T_7075) @[ifu_bp_ctl.scala 434:23] - node _T_7077 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7078 = eq(_T_7077, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_7079 = and(_T_7076, _T_7078) @[ifu_bp_ctl.scala 434:81] - node _T_7080 = or(_T_7079, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7081 = bits(_T_7080, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_3_9 = mux(_T_7081, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7082 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7083 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7084 = eq(_T_7083, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_7085 = and(_T_7082, _T_7084) @[ifu_bp_ctl.scala 434:23] - node _T_7086 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7087 = eq(_T_7086, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_7088 = and(_T_7085, _T_7087) @[ifu_bp_ctl.scala 434:81] - node _T_7089 = or(_T_7088, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7090 = bits(_T_7089, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_3_10 = mux(_T_7090, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7091 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7092 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7093 = eq(_T_7092, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_7094 = and(_T_7091, _T_7093) @[ifu_bp_ctl.scala 434:23] - node _T_7095 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7096 = eq(_T_7095, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_7097 = and(_T_7094, _T_7096) @[ifu_bp_ctl.scala 434:81] - node _T_7098 = or(_T_7097, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7099 = bits(_T_7098, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_3_11 = mux(_T_7099, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7100 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7101 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7102 = eq(_T_7101, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_7103 = and(_T_7100, _T_7102) @[ifu_bp_ctl.scala 434:23] - node _T_7104 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7105 = eq(_T_7104, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_7106 = and(_T_7103, _T_7105) @[ifu_bp_ctl.scala 434:81] - node _T_7107 = or(_T_7106, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7108 = bits(_T_7107, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_3_12 = mux(_T_7108, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7109 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7110 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7111 = eq(_T_7110, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_7112 = and(_T_7109, _T_7111) @[ifu_bp_ctl.scala 434:23] - node _T_7113 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7114 = eq(_T_7113, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_7115 = and(_T_7112, _T_7114) @[ifu_bp_ctl.scala 434:81] - node _T_7116 = or(_T_7115, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7117 = bits(_T_7116, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_3_13 = mux(_T_7117, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7118 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7119 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7120 = eq(_T_7119, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_7121 = and(_T_7118, _T_7120) @[ifu_bp_ctl.scala 434:23] - node _T_7122 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7123 = eq(_T_7122, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_7124 = and(_T_7121, _T_7123) @[ifu_bp_ctl.scala 434:81] - node _T_7125 = or(_T_7124, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7126 = bits(_T_7125, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_3_14 = mux(_T_7126, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7127 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7128 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7129 = eq(_T_7128, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_7130 = and(_T_7127, _T_7129) @[ifu_bp_ctl.scala 434:23] - node _T_7131 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7132 = eq(_T_7131, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_7133 = and(_T_7130, _T_7132) @[ifu_bp_ctl.scala 434:81] - node _T_7134 = or(_T_7133, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7135 = bits(_T_7134, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_3_15 = mux(_T_7135, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7136 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7137 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7138 = eq(_T_7137, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_7139 = and(_T_7136, _T_7138) @[ifu_bp_ctl.scala 434:23] - node _T_7140 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7141 = eq(_T_7140, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_7142 = and(_T_7139, _T_7141) @[ifu_bp_ctl.scala 434:81] - node _T_7143 = or(_T_7142, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7144 = bits(_T_7143, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_4_0 = mux(_T_7144, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7145 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7146 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7147 = eq(_T_7146, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_7148 = and(_T_7145, _T_7147) @[ifu_bp_ctl.scala 434:23] - node _T_7149 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7150 = eq(_T_7149, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_7151 = and(_T_7148, _T_7150) @[ifu_bp_ctl.scala 434:81] - node _T_7152 = or(_T_7151, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7153 = bits(_T_7152, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_4_1 = mux(_T_7153, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7154 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7155 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7156 = eq(_T_7155, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_7157 = and(_T_7154, _T_7156) @[ifu_bp_ctl.scala 434:23] - node _T_7158 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7159 = eq(_T_7158, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_7160 = and(_T_7157, _T_7159) @[ifu_bp_ctl.scala 434:81] - node _T_7161 = or(_T_7160, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7162 = bits(_T_7161, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_4_2 = mux(_T_7162, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7163 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7164 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7165 = eq(_T_7164, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_7166 = and(_T_7163, _T_7165) @[ifu_bp_ctl.scala 434:23] - node _T_7167 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7168 = eq(_T_7167, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_7169 = and(_T_7166, _T_7168) @[ifu_bp_ctl.scala 434:81] - node _T_7170 = or(_T_7169, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7171 = bits(_T_7170, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_4_3 = mux(_T_7171, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7172 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7173 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7174 = eq(_T_7173, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_7175 = and(_T_7172, _T_7174) @[ifu_bp_ctl.scala 434:23] - node _T_7176 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7177 = eq(_T_7176, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_7178 = and(_T_7175, _T_7177) @[ifu_bp_ctl.scala 434:81] - node _T_7179 = or(_T_7178, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7180 = bits(_T_7179, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_4_4 = mux(_T_7180, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7181 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7182 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7183 = eq(_T_7182, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_7184 = and(_T_7181, _T_7183) @[ifu_bp_ctl.scala 434:23] - node _T_7185 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7186 = eq(_T_7185, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_7187 = and(_T_7184, _T_7186) @[ifu_bp_ctl.scala 434:81] - node _T_7188 = or(_T_7187, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7189 = bits(_T_7188, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_4_5 = mux(_T_7189, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7190 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7191 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7192 = eq(_T_7191, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_7193 = and(_T_7190, _T_7192) @[ifu_bp_ctl.scala 434:23] - node _T_7194 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7195 = eq(_T_7194, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_7196 = and(_T_7193, _T_7195) @[ifu_bp_ctl.scala 434:81] - node _T_7197 = or(_T_7196, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7198 = bits(_T_7197, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_4_6 = mux(_T_7198, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7199 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7200 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7201 = eq(_T_7200, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_7202 = and(_T_7199, _T_7201) @[ifu_bp_ctl.scala 434:23] - node _T_7203 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7204 = eq(_T_7203, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_7205 = and(_T_7202, _T_7204) @[ifu_bp_ctl.scala 434:81] - node _T_7206 = or(_T_7205, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7207 = bits(_T_7206, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_4_7 = mux(_T_7207, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7208 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7209 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7210 = eq(_T_7209, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_7211 = and(_T_7208, _T_7210) @[ifu_bp_ctl.scala 434:23] - node _T_7212 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7213 = eq(_T_7212, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_7214 = and(_T_7211, _T_7213) @[ifu_bp_ctl.scala 434:81] - node _T_7215 = or(_T_7214, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7216 = bits(_T_7215, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_4_8 = mux(_T_7216, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7217 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7218 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7219 = eq(_T_7218, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_7220 = and(_T_7217, _T_7219) @[ifu_bp_ctl.scala 434:23] - node _T_7221 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7222 = eq(_T_7221, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_7223 = and(_T_7220, _T_7222) @[ifu_bp_ctl.scala 434:81] - node _T_7224 = or(_T_7223, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7225 = bits(_T_7224, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_4_9 = mux(_T_7225, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7226 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7227 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7228 = eq(_T_7227, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_7229 = and(_T_7226, _T_7228) @[ifu_bp_ctl.scala 434:23] - node _T_7230 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7231 = eq(_T_7230, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_7232 = and(_T_7229, _T_7231) @[ifu_bp_ctl.scala 434:81] - node _T_7233 = or(_T_7232, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7234 = bits(_T_7233, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_4_10 = mux(_T_7234, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7235 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7236 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7237 = eq(_T_7236, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_7238 = and(_T_7235, _T_7237) @[ifu_bp_ctl.scala 434:23] - node _T_7239 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7240 = eq(_T_7239, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_7241 = and(_T_7238, _T_7240) @[ifu_bp_ctl.scala 434:81] - node _T_7242 = or(_T_7241, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7243 = bits(_T_7242, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_4_11 = mux(_T_7243, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7244 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7245 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7246 = eq(_T_7245, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_7247 = and(_T_7244, _T_7246) @[ifu_bp_ctl.scala 434:23] - node _T_7248 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7249 = eq(_T_7248, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_7250 = and(_T_7247, _T_7249) @[ifu_bp_ctl.scala 434:81] - node _T_7251 = or(_T_7250, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7252 = bits(_T_7251, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_4_12 = mux(_T_7252, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7253 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7254 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7255 = eq(_T_7254, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_7256 = and(_T_7253, _T_7255) @[ifu_bp_ctl.scala 434:23] - node _T_7257 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7258 = eq(_T_7257, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_7259 = and(_T_7256, _T_7258) @[ifu_bp_ctl.scala 434:81] - node _T_7260 = or(_T_7259, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7261 = bits(_T_7260, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_4_13 = mux(_T_7261, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7262 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7263 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7264 = eq(_T_7263, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_7265 = and(_T_7262, _T_7264) @[ifu_bp_ctl.scala 434:23] - node _T_7266 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7267 = eq(_T_7266, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_7268 = and(_T_7265, _T_7267) @[ifu_bp_ctl.scala 434:81] - node _T_7269 = or(_T_7268, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7270 = bits(_T_7269, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_4_14 = mux(_T_7270, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7271 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7272 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7273 = eq(_T_7272, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_7274 = and(_T_7271, _T_7273) @[ifu_bp_ctl.scala 434:23] - node _T_7275 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7276 = eq(_T_7275, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_7277 = and(_T_7274, _T_7276) @[ifu_bp_ctl.scala 434:81] - node _T_7278 = or(_T_7277, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7279 = bits(_T_7278, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_4_15 = mux(_T_7279, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7280 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7281 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7282 = eq(_T_7281, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_7283 = and(_T_7280, _T_7282) @[ifu_bp_ctl.scala 434:23] - node _T_7284 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7285 = eq(_T_7284, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_7286 = and(_T_7283, _T_7285) @[ifu_bp_ctl.scala 434:81] - node _T_7287 = or(_T_7286, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7288 = bits(_T_7287, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_5_0 = mux(_T_7288, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7289 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7290 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7291 = eq(_T_7290, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_7292 = and(_T_7289, _T_7291) @[ifu_bp_ctl.scala 434:23] - node _T_7293 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7294 = eq(_T_7293, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_7295 = and(_T_7292, _T_7294) @[ifu_bp_ctl.scala 434:81] - node _T_7296 = or(_T_7295, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7297 = bits(_T_7296, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_5_1 = mux(_T_7297, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7298 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7299 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7300 = eq(_T_7299, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_7301 = and(_T_7298, _T_7300) @[ifu_bp_ctl.scala 434:23] - node _T_7302 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7303 = eq(_T_7302, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_7304 = and(_T_7301, _T_7303) @[ifu_bp_ctl.scala 434:81] - node _T_7305 = or(_T_7304, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7306 = bits(_T_7305, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_5_2 = mux(_T_7306, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7307 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7308 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7309 = eq(_T_7308, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_7310 = and(_T_7307, _T_7309) @[ifu_bp_ctl.scala 434:23] - node _T_7311 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7312 = eq(_T_7311, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_7313 = and(_T_7310, _T_7312) @[ifu_bp_ctl.scala 434:81] - node _T_7314 = or(_T_7313, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7315 = bits(_T_7314, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_5_3 = mux(_T_7315, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7316 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7317 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7318 = eq(_T_7317, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_7319 = and(_T_7316, _T_7318) @[ifu_bp_ctl.scala 434:23] - node _T_7320 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7321 = eq(_T_7320, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_7322 = and(_T_7319, _T_7321) @[ifu_bp_ctl.scala 434:81] - node _T_7323 = or(_T_7322, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7324 = bits(_T_7323, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_5_4 = mux(_T_7324, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7325 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7326 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7327 = eq(_T_7326, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_7328 = and(_T_7325, _T_7327) @[ifu_bp_ctl.scala 434:23] - node _T_7329 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7330 = eq(_T_7329, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_7331 = and(_T_7328, _T_7330) @[ifu_bp_ctl.scala 434:81] - node _T_7332 = or(_T_7331, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7333 = bits(_T_7332, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_5_5 = mux(_T_7333, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7334 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7335 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7336 = eq(_T_7335, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_7337 = and(_T_7334, _T_7336) @[ifu_bp_ctl.scala 434:23] - node _T_7338 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7339 = eq(_T_7338, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_7340 = and(_T_7337, _T_7339) @[ifu_bp_ctl.scala 434:81] - node _T_7341 = or(_T_7340, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7342 = bits(_T_7341, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_5_6 = mux(_T_7342, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7343 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7344 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7345 = eq(_T_7344, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_7346 = and(_T_7343, _T_7345) @[ifu_bp_ctl.scala 434:23] - node _T_7347 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7348 = eq(_T_7347, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_7349 = and(_T_7346, _T_7348) @[ifu_bp_ctl.scala 434:81] - node _T_7350 = or(_T_7349, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7351 = bits(_T_7350, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_5_7 = mux(_T_7351, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7352 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7353 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7354 = eq(_T_7353, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_7355 = and(_T_7352, _T_7354) @[ifu_bp_ctl.scala 434:23] - node _T_7356 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7357 = eq(_T_7356, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_7358 = and(_T_7355, _T_7357) @[ifu_bp_ctl.scala 434:81] - node _T_7359 = or(_T_7358, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7360 = bits(_T_7359, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_5_8 = mux(_T_7360, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7361 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7362 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7363 = eq(_T_7362, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_7364 = and(_T_7361, _T_7363) @[ifu_bp_ctl.scala 434:23] - node _T_7365 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7366 = eq(_T_7365, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_7367 = and(_T_7364, _T_7366) @[ifu_bp_ctl.scala 434:81] - node _T_7368 = or(_T_7367, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7369 = bits(_T_7368, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_5_9 = mux(_T_7369, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7370 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7371 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7372 = eq(_T_7371, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_7373 = and(_T_7370, _T_7372) @[ifu_bp_ctl.scala 434:23] - node _T_7374 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7375 = eq(_T_7374, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_7376 = and(_T_7373, _T_7375) @[ifu_bp_ctl.scala 434:81] - node _T_7377 = or(_T_7376, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7378 = bits(_T_7377, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_5_10 = mux(_T_7378, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7379 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7380 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7381 = eq(_T_7380, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_7382 = and(_T_7379, _T_7381) @[ifu_bp_ctl.scala 434:23] - node _T_7383 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7384 = eq(_T_7383, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_7385 = and(_T_7382, _T_7384) @[ifu_bp_ctl.scala 434:81] - node _T_7386 = or(_T_7385, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7387 = bits(_T_7386, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_5_11 = mux(_T_7387, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7388 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7389 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7390 = eq(_T_7389, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_7391 = and(_T_7388, _T_7390) @[ifu_bp_ctl.scala 434:23] - node _T_7392 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7393 = eq(_T_7392, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_7394 = and(_T_7391, _T_7393) @[ifu_bp_ctl.scala 434:81] - node _T_7395 = or(_T_7394, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7396 = bits(_T_7395, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_5_12 = mux(_T_7396, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7397 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7398 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7399 = eq(_T_7398, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_7400 = and(_T_7397, _T_7399) @[ifu_bp_ctl.scala 434:23] - node _T_7401 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7402 = eq(_T_7401, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_7403 = and(_T_7400, _T_7402) @[ifu_bp_ctl.scala 434:81] - node _T_7404 = or(_T_7403, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7405 = bits(_T_7404, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_5_13 = mux(_T_7405, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7406 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7407 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7408 = eq(_T_7407, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_7409 = and(_T_7406, _T_7408) @[ifu_bp_ctl.scala 434:23] - node _T_7410 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7411 = eq(_T_7410, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_7412 = and(_T_7409, _T_7411) @[ifu_bp_ctl.scala 434:81] - node _T_7413 = or(_T_7412, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7414 = bits(_T_7413, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_5_14 = mux(_T_7414, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7415 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7416 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7417 = eq(_T_7416, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_7418 = and(_T_7415, _T_7417) @[ifu_bp_ctl.scala 434:23] - node _T_7419 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7420 = eq(_T_7419, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_7421 = and(_T_7418, _T_7420) @[ifu_bp_ctl.scala 434:81] - node _T_7422 = or(_T_7421, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7423 = bits(_T_7422, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_5_15 = mux(_T_7423, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7424 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7425 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7426 = eq(_T_7425, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_7427 = and(_T_7424, _T_7426) @[ifu_bp_ctl.scala 434:23] - node _T_7428 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7429 = eq(_T_7428, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_7430 = and(_T_7427, _T_7429) @[ifu_bp_ctl.scala 434:81] - node _T_7431 = or(_T_7430, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7432 = bits(_T_7431, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_6_0 = mux(_T_7432, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7433 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7434 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7435 = eq(_T_7434, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_7436 = and(_T_7433, _T_7435) @[ifu_bp_ctl.scala 434:23] - node _T_7437 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7438 = eq(_T_7437, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_7439 = and(_T_7436, _T_7438) @[ifu_bp_ctl.scala 434:81] - node _T_7440 = or(_T_7439, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7441 = bits(_T_7440, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_6_1 = mux(_T_7441, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7442 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7443 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7444 = eq(_T_7443, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_7445 = and(_T_7442, _T_7444) @[ifu_bp_ctl.scala 434:23] - node _T_7446 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7447 = eq(_T_7446, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_7448 = and(_T_7445, _T_7447) @[ifu_bp_ctl.scala 434:81] - node _T_7449 = or(_T_7448, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7450 = bits(_T_7449, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_6_2 = mux(_T_7450, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7451 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7452 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7453 = eq(_T_7452, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_7454 = and(_T_7451, _T_7453) @[ifu_bp_ctl.scala 434:23] - node _T_7455 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7456 = eq(_T_7455, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_7457 = and(_T_7454, _T_7456) @[ifu_bp_ctl.scala 434:81] - node _T_7458 = or(_T_7457, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7459 = bits(_T_7458, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_6_3 = mux(_T_7459, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7460 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7461 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7462 = eq(_T_7461, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_7463 = and(_T_7460, _T_7462) @[ifu_bp_ctl.scala 434:23] - node _T_7464 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7465 = eq(_T_7464, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_7466 = and(_T_7463, _T_7465) @[ifu_bp_ctl.scala 434:81] - node _T_7467 = or(_T_7466, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7468 = bits(_T_7467, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_6_4 = mux(_T_7468, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7469 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7470 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7471 = eq(_T_7470, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_7472 = and(_T_7469, _T_7471) @[ifu_bp_ctl.scala 434:23] - node _T_7473 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7474 = eq(_T_7473, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_7475 = and(_T_7472, _T_7474) @[ifu_bp_ctl.scala 434:81] - node _T_7476 = or(_T_7475, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7477 = bits(_T_7476, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_6_5 = mux(_T_7477, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7478 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7479 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7480 = eq(_T_7479, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_7481 = and(_T_7478, _T_7480) @[ifu_bp_ctl.scala 434:23] - node _T_7482 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7483 = eq(_T_7482, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_7484 = and(_T_7481, _T_7483) @[ifu_bp_ctl.scala 434:81] - node _T_7485 = or(_T_7484, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7486 = bits(_T_7485, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_6_6 = mux(_T_7486, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7487 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7488 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7489 = eq(_T_7488, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_7490 = and(_T_7487, _T_7489) @[ifu_bp_ctl.scala 434:23] - node _T_7491 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7492 = eq(_T_7491, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_7493 = and(_T_7490, _T_7492) @[ifu_bp_ctl.scala 434:81] - node _T_7494 = or(_T_7493, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7495 = bits(_T_7494, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_6_7 = mux(_T_7495, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7496 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7497 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7498 = eq(_T_7497, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_7499 = and(_T_7496, _T_7498) @[ifu_bp_ctl.scala 434:23] - node _T_7500 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7501 = eq(_T_7500, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_7502 = and(_T_7499, _T_7501) @[ifu_bp_ctl.scala 434:81] - node _T_7503 = or(_T_7502, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7504 = bits(_T_7503, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_6_8 = mux(_T_7504, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7505 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7506 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7507 = eq(_T_7506, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_7508 = and(_T_7505, _T_7507) @[ifu_bp_ctl.scala 434:23] - node _T_7509 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7510 = eq(_T_7509, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_7511 = and(_T_7508, _T_7510) @[ifu_bp_ctl.scala 434:81] - node _T_7512 = or(_T_7511, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7513 = bits(_T_7512, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_6_9 = mux(_T_7513, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7514 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7515 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7516 = eq(_T_7515, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_7517 = and(_T_7514, _T_7516) @[ifu_bp_ctl.scala 434:23] - node _T_7518 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7519 = eq(_T_7518, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_7520 = and(_T_7517, _T_7519) @[ifu_bp_ctl.scala 434:81] - node _T_7521 = or(_T_7520, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7522 = bits(_T_7521, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_6_10 = mux(_T_7522, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7523 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7524 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7525 = eq(_T_7524, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_7526 = and(_T_7523, _T_7525) @[ifu_bp_ctl.scala 434:23] - node _T_7527 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7528 = eq(_T_7527, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_7529 = and(_T_7526, _T_7528) @[ifu_bp_ctl.scala 434:81] - node _T_7530 = or(_T_7529, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7531 = bits(_T_7530, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_6_11 = mux(_T_7531, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7532 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7533 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7534 = eq(_T_7533, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_7535 = and(_T_7532, _T_7534) @[ifu_bp_ctl.scala 434:23] - node _T_7536 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7537 = eq(_T_7536, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_7538 = and(_T_7535, _T_7537) @[ifu_bp_ctl.scala 434:81] - node _T_7539 = or(_T_7538, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7540 = bits(_T_7539, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_6_12 = mux(_T_7540, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7541 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7542 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7543 = eq(_T_7542, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_7544 = and(_T_7541, _T_7543) @[ifu_bp_ctl.scala 434:23] - node _T_7545 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7546 = eq(_T_7545, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_7547 = and(_T_7544, _T_7546) @[ifu_bp_ctl.scala 434:81] - node _T_7548 = or(_T_7547, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7549 = bits(_T_7548, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_6_13 = mux(_T_7549, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7550 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7551 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7552 = eq(_T_7551, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_7553 = and(_T_7550, _T_7552) @[ifu_bp_ctl.scala 434:23] - node _T_7554 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7555 = eq(_T_7554, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_7556 = and(_T_7553, _T_7555) @[ifu_bp_ctl.scala 434:81] - node _T_7557 = or(_T_7556, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7558 = bits(_T_7557, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_6_14 = mux(_T_7558, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7559 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7560 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7561 = eq(_T_7560, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_7562 = and(_T_7559, _T_7561) @[ifu_bp_ctl.scala 434:23] - node _T_7563 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7564 = eq(_T_7563, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_7565 = and(_T_7562, _T_7564) @[ifu_bp_ctl.scala 434:81] - node _T_7566 = or(_T_7565, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7567 = bits(_T_7566, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_6_15 = mux(_T_7567, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7568 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7569 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7570 = eq(_T_7569, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_7571 = and(_T_7568, _T_7570) @[ifu_bp_ctl.scala 434:23] - node _T_7572 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7573 = eq(_T_7572, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_7574 = and(_T_7571, _T_7573) @[ifu_bp_ctl.scala 434:81] - node _T_7575 = or(_T_7574, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7576 = bits(_T_7575, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_7_0 = mux(_T_7576, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7577 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7578 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7579 = eq(_T_7578, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_7580 = and(_T_7577, _T_7579) @[ifu_bp_ctl.scala 434:23] - node _T_7581 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7582 = eq(_T_7581, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_7583 = and(_T_7580, _T_7582) @[ifu_bp_ctl.scala 434:81] - node _T_7584 = or(_T_7583, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7585 = bits(_T_7584, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_7_1 = mux(_T_7585, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7586 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7587 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7588 = eq(_T_7587, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_7589 = and(_T_7586, _T_7588) @[ifu_bp_ctl.scala 434:23] - node _T_7590 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7591 = eq(_T_7590, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_7592 = and(_T_7589, _T_7591) @[ifu_bp_ctl.scala 434:81] - node _T_7593 = or(_T_7592, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7594 = bits(_T_7593, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_7_2 = mux(_T_7594, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7595 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7596 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7597 = eq(_T_7596, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_7598 = and(_T_7595, _T_7597) @[ifu_bp_ctl.scala 434:23] - node _T_7599 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7600 = eq(_T_7599, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_7601 = and(_T_7598, _T_7600) @[ifu_bp_ctl.scala 434:81] - node _T_7602 = or(_T_7601, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7603 = bits(_T_7602, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_7_3 = mux(_T_7603, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7604 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7605 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7606 = eq(_T_7605, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_7607 = and(_T_7604, _T_7606) @[ifu_bp_ctl.scala 434:23] - node _T_7608 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7609 = eq(_T_7608, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_7610 = and(_T_7607, _T_7609) @[ifu_bp_ctl.scala 434:81] - node _T_7611 = or(_T_7610, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7612 = bits(_T_7611, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_7_4 = mux(_T_7612, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7613 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7614 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7615 = eq(_T_7614, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_7616 = and(_T_7613, _T_7615) @[ifu_bp_ctl.scala 434:23] - node _T_7617 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7618 = eq(_T_7617, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_7619 = and(_T_7616, _T_7618) @[ifu_bp_ctl.scala 434:81] - node _T_7620 = or(_T_7619, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7621 = bits(_T_7620, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_7_5 = mux(_T_7621, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7622 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7623 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7624 = eq(_T_7623, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_7625 = and(_T_7622, _T_7624) @[ifu_bp_ctl.scala 434:23] - node _T_7626 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7627 = eq(_T_7626, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_7628 = and(_T_7625, _T_7627) @[ifu_bp_ctl.scala 434:81] - node _T_7629 = or(_T_7628, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7630 = bits(_T_7629, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_7_6 = mux(_T_7630, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7631 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7632 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7633 = eq(_T_7632, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_7634 = and(_T_7631, _T_7633) @[ifu_bp_ctl.scala 434:23] - node _T_7635 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7636 = eq(_T_7635, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_7637 = and(_T_7634, _T_7636) @[ifu_bp_ctl.scala 434:81] - node _T_7638 = or(_T_7637, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7639 = bits(_T_7638, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_7_7 = mux(_T_7639, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7640 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7641 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7642 = eq(_T_7641, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_7643 = and(_T_7640, _T_7642) @[ifu_bp_ctl.scala 434:23] - node _T_7644 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7645 = eq(_T_7644, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_7646 = and(_T_7643, _T_7645) @[ifu_bp_ctl.scala 434:81] - node _T_7647 = or(_T_7646, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7648 = bits(_T_7647, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_7_8 = mux(_T_7648, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7649 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7650 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7651 = eq(_T_7650, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_7652 = and(_T_7649, _T_7651) @[ifu_bp_ctl.scala 434:23] - node _T_7653 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7654 = eq(_T_7653, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_7655 = and(_T_7652, _T_7654) @[ifu_bp_ctl.scala 434:81] - node _T_7656 = or(_T_7655, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7657 = bits(_T_7656, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_7_9 = mux(_T_7657, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7658 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7659 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7660 = eq(_T_7659, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_7661 = and(_T_7658, _T_7660) @[ifu_bp_ctl.scala 434:23] - node _T_7662 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7663 = eq(_T_7662, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_7664 = and(_T_7661, _T_7663) @[ifu_bp_ctl.scala 434:81] - node _T_7665 = or(_T_7664, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7666 = bits(_T_7665, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_7_10 = mux(_T_7666, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7667 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7668 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7669 = eq(_T_7668, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_7670 = and(_T_7667, _T_7669) @[ifu_bp_ctl.scala 434:23] - node _T_7671 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7672 = eq(_T_7671, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_7673 = and(_T_7670, _T_7672) @[ifu_bp_ctl.scala 434:81] - node _T_7674 = or(_T_7673, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7675 = bits(_T_7674, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_7_11 = mux(_T_7675, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7676 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7677 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7678 = eq(_T_7677, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_7679 = and(_T_7676, _T_7678) @[ifu_bp_ctl.scala 434:23] - node _T_7680 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7681 = eq(_T_7680, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_7682 = and(_T_7679, _T_7681) @[ifu_bp_ctl.scala 434:81] - node _T_7683 = or(_T_7682, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7684 = bits(_T_7683, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_7_12 = mux(_T_7684, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7685 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7686 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7687 = eq(_T_7686, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_7688 = and(_T_7685, _T_7687) @[ifu_bp_ctl.scala 434:23] - node _T_7689 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7690 = eq(_T_7689, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_7691 = and(_T_7688, _T_7690) @[ifu_bp_ctl.scala 434:81] - node _T_7692 = or(_T_7691, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7693 = bits(_T_7692, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_7_13 = mux(_T_7693, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7694 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7695 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7696 = eq(_T_7695, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_7697 = and(_T_7694, _T_7696) @[ifu_bp_ctl.scala 434:23] - node _T_7698 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7699 = eq(_T_7698, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_7700 = and(_T_7697, _T_7699) @[ifu_bp_ctl.scala 434:81] - node _T_7701 = or(_T_7700, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7702 = bits(_T_7701, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_7_14 = mux(_T_7702, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7703 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7704 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7705 = eq(_T_7704, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_7706 = and(_T_7703, _T_7705) @[ifu_bp_ctl.scala 434:23] - node _T_7707 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7708 = eq(_T_7707, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_7709 = and(_T_7706, _T_7708) @[ifu_bp_ctl.scala 434:81] - node _T_7710 = or(_T_7709, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7711 = bits(_T_7710, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_7_15 = mux(_T_7711, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7712 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7713 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7714 = eq(_T_7713, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_7715 = and(_T_7712, _T_7714) @[ifu_bp_ctl.scala 434:23] - node _T_7716 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7717 = eq(_T_7716, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_7718 = and(_T_7715, _T_7717) @[ifu_bp_ctl.scala 434:81] - node _T_7719 = or(_T_7718, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7720 = bits(_T_7719, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_8_0 = mux(_T_7720, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7721 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7722 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7723 = eq(_T_7722, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_7724 = and(_T_7721, _T_7723) @[ifu_bp_ctl.scala 434:23] - node _T_7725 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7726 = eq(_T_7725, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_7727 = and(_T_7724, _T_7726) @[ifu_bp_ctl.scala 434:81] - node _T_7728 = or(_T_7727, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7729 = bits(_T_7728, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_8_1 = mux(_T_7729, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7730 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7731 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7732 = eq(_T_7731, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_7733 = and(_T_7730, _T_7732) @[ifu_bp_ctl.scala 434:23] - node _T_7734 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7735 = eq(_T_7734, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_7736 = and(_T_7733, _T_7735) @[ifu_bp_ctl.scala 434:81] - node _T_7737 = or(_T_7736, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7738 = bits(_T_7737, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_8_2 = mux(_T_7738, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7739 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7740 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7741 = eq(_T_7740, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_7742 = and(_T_7739, _T_7741) @[ifu_bp_ctl.scala 434:23] - node _T_7743 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7744 = eq(_T_7743, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_7745 = and(_T_7742, _T_7744) @[ifu_bp_ctl.scala 434:81] - node _T_7746 = or(_T_7745, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7747 = bits(_T_7746, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_8_3 = mux(_T_7747, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7748 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7749 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7750 = eq(_T_7749, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_7751 = and(_T_7748, _T_7750) @[ifu_bp_ctl.scala 434:23] - node _T_7752 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7753 = eq(_T_7752, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_7754 = and(_T_7751, _T_7753) @[ifu_bp_ctl.scala 434:81] - node _T_7755 = or(_T_7754, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7756 = bits(_T_7755, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_8_4 = mux(_T_7756, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7757 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7758 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7759 = eq(_T_7758, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_7760 = and(_T_7757, _T_7759) @[ifu_bp_ctl.scala 434:23] - node _T_7761 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7762 = eq(_T_7761, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_7763 = and(_T_7760, _T_7762) @[ifu_bp_ctl.scala 434:81] - node _T_7764 = or(_T_7763, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7765 = bits(_T_7764, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_8_5 = mux(_T_7765, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7766 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7767 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7768 = eq(_T_7767, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_7769 = and(_T_7766, _T_7768) @[ifu_bp_ctl.scala 434:23] - node _T_7770 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7771 = eq(_T_7770, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_7772 = and(_T_7769, _T_7771) @[ifu_bp_ctl.scala 434:81] - node _T_7773 = or(_T_7772, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7774 = bits(_T_7773, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_8_6 = mux(_T_7774, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7775 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7776 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7777 = eq(_T_7776, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_7778 = and(_T_7775, _T_7777) @[ifu_bp_ctl.scala 434:23] - node _T_7779 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7780 = eq(_T_7779, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_7781 = and(_T_7778, _T_7780) @[ifu_bp_ctl.scala 434:81] - node _T_7782 = or(_T_7781, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7783 = bits(_T_7782, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_8_7 = mux(_T_7783, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7784 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7785 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7786 = eq(_T_7785, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_7787 = and(_T_7784, _T_7786) @[ifu_bp_ctl.scala 434:23] - node _T_7788 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7789 = eq(_T_7788, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_7790 = and(_T_7787, _T_7789) @[ifu_bp_ctl.scala 434:81] - node _T_7791 = or(_T_7790, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7792 = bits(_T_7791, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_8_8 = mux(_T_7792, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7793 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7794 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7795 = eq(_T_7794, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_7796 = and(_T_7793, _T_7795) @[ifu_bp_ctl.scala 434:23] - node _T_7797 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7798 = eq(_T_7797, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_7799 = and(_T_7796, _T_7798) @[ifu_bp_ctl.scala 434:81] - node _T_7800 = or(_T_7799, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7801 = bits(_T_7800, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_8_9 = mux(_T_7801, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7802 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7803 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7804 = eq(_T_7803, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_7805 = and(_T_7802, _T_7804) @[ifu_bp_ctl.scala 434:23] - node _T_7806 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7807 = eq(_T_7806, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_7808 = and(_T_7805, _T_7807) @[ifu_bp_ctl.scala 434:81] - node _T_7809 = or(_T_7808, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7810 = bits(_T_7809, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_8_10 = mux(_T_7810, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7811 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7812 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7813 = eq(_T_7812, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_7814 = and(_T_7811, _T_7813) @[ifu_bp_ctl.scala 434:23] - node _T_7815 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7816 = eq(_T_7815, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_7817 = and(_T_7814, _T_7816) @[ifu_bp_ctl.scala 434:81] - node _T_7818 = or(_T_7817, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7819 = bits(_T_7818, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_8_11 = mux(_T_7819, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7820 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7821 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7822 = eq(_T_7821, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_7823 = and(_T_7820, _T_7822) @[ifu_bp_ctl.scala 434:23] - node _T_7824 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7825 = eq(_T_7824, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_7826 = and(_T_7823, _T_7825) @[ifu_bp_ctl.scala 434:81] - node _T_7827 = or(_T_7826, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7828 = bits(_T_7827, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_8_12 = mux(_T_7828, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7829 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7830 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7831 = eq(_T_7830, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_7832 = and(_T_7829, _T_7831) @[ifu_bp_ctl.scala 434:23] - node _T_7833 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7834 = eq(_T_7833, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_7835 = and(_T_7832, _T_7834) @[ifu_bp_ctl.scala 434:81] - node _T_7836 = or(_T_7835, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7837 = bits(_T_7836, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_8_13 = mux(_T_7837, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7838 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7839 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7840 = eq(_T_7839, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_7841 = and(_T_7838, _T_7840) @[ifu_bp_ctl.scala 434:23] - node _T_7842 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7843 = eq(_T_7842, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_7844 = and(_T_7841, _T_7843) @[ifu_bp_ctl.scala 434:81] - node _T_7845 = or(_T_7844, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7846 = bits(_T_7845, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_8_14 = mux(_T_7846, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7847 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7848 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7849 = eq(_T_7848, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_7850 = and(_T_7847, _T_7849) @[ifu_bp_ctl.scala 434:23] - node _T_7851 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7852 = eq(_T_7851, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_7853 = and(_T_7850, _T_7852) @[ifu_bp_ctl.scala 434:81] - node _T_7854 = or(_T_7853, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7855 = bits(_T_7854, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_8_15 = mux(_T_7855, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7856 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7857 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7858 = eq(_T_7857, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_7859 = and(_T_7856, _T_7858) @[ifu_bp_ctl.scala 434:23] - node _T_7860 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7861 = eq(_T_7860, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_7862 = and(_T_7859, _T_7861) @[ifu_bp_ctl.scala 434:81] - node _T_7863 = or(_T_7862, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7864 = bits(_T_7863, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_9_0 = mux(_T_7864, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7865 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7866 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7867 = eq(_T_7866, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_7868 = and(_T_7865, _T_7867) @[ifu_bp_ctl.scala 434:23] - node _T_7869 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7870 = eq(_T_7869, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_7871 = and(_T_7868, _T_7870) @[ifu_bp_ctl.scala 434:81] - node _T_7872 = or(_T_7871, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7873 = bits(_T_7872, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_9_1 = mux(_T_7873, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7874 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7875 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7876 = eq(_T_7875, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_7877 = and(_T_7874, _T_7876) @[ifu_bp_ctl.scala 434:23] - node _T_7878 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7879 = eq(_T_7878, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_7880 = and(_T_7877, _T_7879) @[ifu_bp_ctl.scala 434:81] - node _T_7881 = or(_T_7880, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7882 = bits(_T_7881, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_9_2 = mux(_T_7882, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7883 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7884 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7885 = eq(_T_7884, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_7886 = and(_T_7883, _T_7885) @[ifu_bp_ctl.scala 434:23] - node _T_7887 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7888 = eq(_T_7887, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_7889 = and(_T_7886, _T_7888) @[ifu_bp_ctl.scala 434:81] - node _T_7890 = or(_T_7889, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7891 = bits(_T_7890, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_9_3 = mux(_T_7891, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7892 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7893 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7894 = eq(_T_7893, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_7895 = and(_T_7892, _T_7894) @[ifu_bp_ctl.scala 434:23] - node _T_7896 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7897 = eq(_T_7896, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_7898 = and(_T_7895, _T_7897) @[ifu_bp_ctl.scala 434:81] - node _T_7899 = or(_T_7898, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7900 = bits(_T_7899, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_9_4 = mux(_T_7900, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7901 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7902 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7903 = eq(_T_7902, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_7904 = and(_T_7901, _T_7903) @[ifu_bp_ctl.scala 434:23] - node _T_7905 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7906 = eq(_T_7905, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_7907 = and(_T_7904, _T_7906) @[ifu_bp_ctl.scala 434:81] - node _T_7908 = or(_T_7907, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7909 = bits(_T_7908, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_9_5 = mux(_T_7909, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7910 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7911 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7912 = eq(_T_7911, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_7913 = and(_T_7910, _T_7912) @[ifu_bp_ctl.scala 434:23] - node _T_7914 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7915 = eq(_T_7914, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_7916 = and(_T_7913, _T_7915) @[ifu_bp_ctl.scala 434:81] - node _T_7917 = or(_T_7916, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7918 = bits(_T_7917, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_9_6 = mux(_T_7918, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7919 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7920 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7921 = eq(_T_7920, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_7922 = and(_T_7919, _T_7921) @[ifu_bp_ctl.scala 434:23] - node _T_7923 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7924 = eq(_T_7923, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_7925 = and(_T_7922, _T_7924) @[ifu_bp_ctl.scala 434:81] - node _T_7926 = or(_T_7925, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7927 = bits(_T_7926, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_9_7 = mux(_T_7927, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7928 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7929 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7930 = eq(_T_7929, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_7931 = and(_T_7928, _T_7930) @[ifu_bp_ctl.scala 434:23] - node _T_7932 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7933 = eq(_T_7932, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_7934 = and(_T_7931, _T_7933) @[ifu_bp_ctl.scala 434:81] - node _T_7935 = or(_T_7934, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7936 = bits(_T_7935, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_9_8 = mux(_T_7936, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7937 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7938 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7939 = eq(_T_7938, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_7940 = and(_T_7937, _T_7939) @[ifu_bp_ctl.scala 434:23] - node _T_7941 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7942 = eq(_T_7941, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_7943 = and(_T_7940, _T_7942) @[ifu_bp_ctl.scala 434:81] - node _T_7944 = or(_T_7943, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7945 = bits(_T_7944, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_9_9 = mux(_T_7945, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7946 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7947 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7948 = eq(_T_7947, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_7949 = and(_T_7946, _T_7948) @[ifu_bp_ctl.scala 434:23] - node _T_7950 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7951 = eq(_T_7950, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_7952 = and(_T_7949, _T_7951) @[ifu_bp_ctl.scala 434:81] - node _T_7953 = or(_T_7952, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7954 = bits(_T_7953, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_9_10 = mux(_T_7954, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7955 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7956 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7957 = eq(_T_7956, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_7958 = and(_T_7955, _T_7957) @[ifu_bp_ctl.scala 434:23] - node _T_7959 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7960 = eq(_T_7959, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_7961 = and(_T_7958, _T_7960) @[ifu_bp_ctl.scala 434:81] - node _T_7962 = or(_T_7961, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7963 = bits(_T_7962, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_9_11 = mux(_T_7963, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7964 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7965 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7966 = eq(_T_7965, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_7967 = and(_T_7964, _T_7966) @[ifu_bp_ctl.scala 434:23] - node _T_7968 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7969 = eq(_T_7968, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_7970 = and(_T_7967, _T_7969) @[ifu_bp_ctl.scala 434:81] - node _T_7971 = or(_T_7970, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7972 = bits(_T_7971, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_9_12 = mux(_T_7972, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7973 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7974 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7975 = eq(_T_7974, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_7976 = and(_T_7973, _T_7975) @[ifu_bp_ctl.scala 434:23] - node _T_7977 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7978 = eq(_T_7977, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_7979 = and(_T_7976, _T_7978) @[ifu_bp_ctl.scala 434:81] - node _T_7980 = or(_T_7979, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7981 = bits(_T_7980, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_9_13 = mux(_T_7981, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7982 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7983 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7984 = eq(_T_7983, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_7985 = and(_T_7982, _T_7984) @[ifu_bp_ctl.scala 434:23] - node _T_7986 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7987 = eq(_T_7986, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_7988 = and(_T_7985, _T_7987) @[ifu_bp_ctl.scala 434:81] - node _T_7989 = or(_T_7988, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7990 = bits(_T_7989, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_9_14 = mux(_T_7990, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_7991 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_7992 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_7993 = eq(_T_7992, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_7994 = and(_T_7991, _T_7993) @[ifu_bp_ctl.scala 434:23] - node _T_7995 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_7996 = eq(_T_7995, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_7997 = and(_T_7994, _T_7996) @[ifu_bp_ctl.scala 434:81] - node _T_7998 = or(_T_7997, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_7999 = bits(_T_7998, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_9_15 = mux(_T_7999, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8000 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8001 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8002 = eq(_T_8001, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_8003 = and(_T_8000, _T_8002) @[ifu_bp_ctl.scala 434:23] - node _T_8004 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8005 = eq(_T_8004, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_8006 = and(_T_8003, _T_8005) @[ifu_bp_ctl.scala 434:81] - node _T_8007 = or(_T_8006, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8008 = bits(_T_8007, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_10_0 = mux(_T_8008, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8009 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8010 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8011 = eq(_T_8010, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_8012 = and(_T_8009, _T_8011) @[ifu_bp_ctl.scala 434:23] - node _T_8013 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8014 = eq(_T_8013, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_8015 = and(_T_8012, _T_8014) @[ifu_bp_ctl.scala 434:81] - node _T_8016 = or(_T_8015, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8017 = bits(_T_8016, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_10_1 = mux(_T_8017, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8018 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8019 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8020 = eq(_T_8019, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_8021 = and(_T_8018, _T_8020) @[ifu_bp_ctl.scala 434:23] - node _T_8022 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8023 = eq(_T_8022, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_8024 = and(_T_8021, _T_8023) @[ifu_bp_ctl.scala 434:81] - node _T_8025 = or(_T_8024, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8026 = bits(_T_8025, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_10_2 = mux(_T_8026, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8027 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8028 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8029 = eq(_T_8028, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_8030 = and(_T_8027, _T_8029) @[ifu_bp_ctl.scala 434:23] - node _T_8031 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8032 = eq(_T_8031, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_8033 = and(_T_8030, _T_8032) @[ifu_bp_ctl.scala 434:81] - node _T_8034 = or(_T_8033, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8035 = bits(_T_8034, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_10_3 = mux(_T_8035, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8036 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8037 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8038 = eq(_T_8037, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_8039 = and(_T_8036, _T_8038) @[ifu_bp_ctl.scala 434:23] - node _T_8040 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8041 = eq(_T_8040, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_8042 = and(_T_8039, _T_8041) @[ifu_bp_ctl.scala 434:81] - node _T_8043 = or(_T_8042, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8044 = bits(_T_8043, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_10_4 = mux(_T_8044, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8045 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8046 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8047 = eq(_T_8046, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_8048 = and(_T_8045, _T_8047) @[ifu_bp_ctl.scala 434:23] - node _T_8049 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8050 = eq(_T_8049, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_8051 = and(_T_8048, _T_8050) @[ifu_bp_ctl.scala 434:81] - node _T_8052 = or(_T_8051, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8053 = bits(_T_8052, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_10_5 = mux(_T_8053, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8054 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8055 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8056 = eq(_T_8055, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_8057 = and(_T_8054, _T_8056) @[ifu_bp_ctl.scala 434:23] - node _T_8058 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8059 = eq(_T_8058, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_8060 = and(_T_8057, _T_8059) @[ifu_bp_ctl.scala 434:81] - node _T_8061 = or(_T_8060, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8062 = bits(_T_8061, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_10_6 = mux(_T_8062, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8063 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8064 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8065 = eq(_T_8064, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_8066 = and(_T_8063, _T_8065) @[ifu_bp_ctl.scala 434:23] - node _T_8067 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8068 = eq(_T_8067, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_8069 = and(_T_8066, _T_8068) @[ifu_bp_ctl.scala 434:81] - node _T_8070 = or(_T_8069, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8071 = bits(_T_8070, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_10_7 = mux(_T_8071, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8072 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8073 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8074 = eq(_T_8073, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_8075 = and(_T_8072, _T_8074) @[ifu_bp_ctl.scala 434:23] - node _T_8076 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8077 = eq(_T_8076, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_8078 = and(_T_8075, _T_8077) @[ifu_bp_ctl.scala 434:81] - node _T_8079 = or(_T_8078, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8080 = bits(_T_8079, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_10_8 = mux(_T_8080, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8081 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8082 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8083 = eq(_T_8082, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_8084 = and(_T_8081, _T_8083) @[ifu_bp_ctl.scala 434:23] - node _T_8085 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8086 = eq(_T_8085, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_8087 = and(_T_8084, _T_8086) @[ifu_bp_ctl.scala 434:81] - node _T_8088 = or(_T_8087, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8089 = bits(_T_8088, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_10_9 = mux(_T_8089, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8090 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8091 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8092 = eq(_T_8091, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_8093 = and(_T_8090, _T_8092) @[ifu_bp_ctl.scala 434:23] - node _T_8094 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8095 = eq(_T_8094, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_8096 = and(_T_8093, _T_8095) @[ifu_bp_ctl.scala 434:81] - node _T_8097 = or(_T_8096, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8098 = bits(_T_8097, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_10_10 = mux(_T_8098, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8099 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8100 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8101 = eq(_T_8100, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_8102 = and(_T_8099, _T_8101) @[ifu_bp_ctl.scala 434:23] - node _T_8103 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8104 = eq(_T_8103, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_8105 = and(_T_8102, _T_8104) @[ifu_bp_ctl.scala 434:81] - node _T_8106 = or(_T_8105, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8107 = bits(_T_8106, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_10_11 = mux(_T_8107, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8108 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8109 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8110 = eq(_T_8109, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_8111 = and(_T_8108, _T_8110) @[ifu_bp_ctl.scala 434:23] - node _T_8112 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8113 = eq(_T_8112, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_8114 = and(_T_8111, _T_8113) @[ifu_bp_ctl.scala 434:81] - node _T_8115 = or(_T_8114, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8116 = bits(_T_8115, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_10_12 = mux(_T_8116, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8117 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8118 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8119 = eq(_T_8118, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_8120 = and(_T_8117, _T_8119) @[ifu_bp_ctl.scala 434:23] - node _T_8121 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8122 = eq(_T_8121, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_8123 = and(_T_8120, _T_8122) @[ifu_bp_ctl.scala 434:81] - node _T_8124 = or(_T_8123, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8125 = bits(_T_8124, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_10_13 = mux(_T_8125, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8126 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8127 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8128 = eq(_T_8127, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_8129 = and(_T_8126, _T_8128) @[ifu_bp_ctl.scala 434:23] - node _T_8130 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8131 = eq(_T_8130, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_8132 = and(_T_8129, _T_8131) @[ifu_bp_ctl.scala 434:81] - node _T_8133 = or(_T_8132, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8134 = bits(_T_8133, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_10_14 = mux(_T_8134, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8135 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8136 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8137 = eq(_T_8136, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_8138 = and(_T_8135, _T_8137) @[ifu_bp_ctl.scala 434:23] - node _T_8139 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8140 = eq(_T_8139, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_8141 = and(_T_8138, _T_8140) @[ifu_bp_ctl.scala 434:81] - node _T_8142 = or(_T_8141, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8143 = bits(_T_8142, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_10_15 = mux(_T_8143, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8144 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8145 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8146 = eq(_T_8145, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_8147 = and(_T_8144, _T_8146) @[ifu_bp_ctl.scala 434:23] - node _T_8148 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8149 = eq(_T_8148, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_8150 = and(_T_8147, _T_8149) @[ifu_bp_ctl.scala 434:81] - node _T_8151 = or(_T_8150, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8152 = bits(_T_8151, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_11_0 = mux(_T_8152, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8153 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8154 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8155 = eq(_T_8154, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_8156 = and(_T_8153, _T_8155) @[ifu_bp_ctl.scala 434:23] - node _T_8157 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8158 = eq(_T_8157, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_8159 = and(_T_8156, _T_8158) @[ifu_bp_ctl.scala 434:81] - node _T_8160 = or(_T_8159, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8161 = bits(_T_8160, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_11_1 = mux(_T_8161, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8162 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8163 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8164 = eq(_T_8163, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_8165 = and(_T_8162, _T_8164) @[ifu_bp_ctl.scala 434:23] - node _T_8166 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8167 = eq(_T_8166, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_8168 = and(_T_8165, _T_8167) @[ifu_bp_ctl.scala 434:81] - node _T_8169 = or(_T_8168, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8170 = bits(_T_8169, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_11_2 = mux(_T_8170, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8171 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8172 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8173 = eq(_T_8172, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_8174 = and(_T_8171, _T_8173) @[ifu_bp_ctl.scala 434:23] - node _T_8175 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8176 = eq(_T_8175, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_8177 = and(_T_8174, _T_8176) @[ifu_bp_ctl.scala 434:81] - node _T_8178 = or(_T_8177, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8179 = bits(_T_8178, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_11_3 = mux(_T_8179, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8180 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8181 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8182 = eq(_T_8181, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_8183 = and(_T_8180, _T_8182) @[ifu_bp_ctl.scala 434:23] - node _T_8184 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8185 = eq(_T_8184, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_8186 = and(_T_8183, _T_8185) @[ifu_bp_ctl.scala 434:81] - node _T_8187 = or(_T_8186, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8188 = bits(_T_8187, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_11_4 = mux(_T_8188, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8189 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8190 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8191 = eq(_T_8190, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_8192 = and(_T_8189, _T_8191) @[ifu_bp_ctl.scala 434:23] - node _T_8193 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8194 = eq(_T_8193, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_8195 = and(_T_8192, _T_8194) @[ifu_bp_ctl.scala 434:81] - node _T_8196 = or(_T_8195, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8197 = bits(_T_8196, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_11_5 = mux(_T_8197, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8198 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8199 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8200 = eq(_T_8199, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_8201 = and(_T_8198, _T_8200) @[ifu_bp_ctl.scala 434:23] - node _T_8202 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8203 = eq(_T_8202, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_8204 = and(_T_8201, _T_8203) @[ifu_bp_ctl.scala 434:81] - node _T_8205 = or(_T_8204, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8206 = bits(_T_8205, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_11_6 = mux(_T_8206, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8207 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8208 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8209 = eq(_T_8208, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_8210 = and(_T_8207, _T_8209) @[ifu_bp_ctl.scala 434:23] - node _T_8211 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8212 = eq(_T_8211, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_8213 = and(_T_8210, _T_8212) @[ifu_bp_ctl.scala 434:81] - node _T_8214 = or(_T_8213, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8215 = bits(_T_8214, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_11_7 = mux(_T_8215, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8216 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8217 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8218 = eq(_T_8217, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_8219 = and(_T_8216, _T_8218) @[ifu_bp_ctl.scala 434:23] - node _T_8220 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8221 = eq(_T_8220, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_8222 = and(_T_8219, _T_8221) @[ifu_bp_ctl.scala 434:81] - node _T_8223 = or(_T_8222, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8224 = bits(_T_8223, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_11_8 = mux(_T_8224, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8225 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8226 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8227 = eq(_T_8226, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_8228 = and(_T_8225, _T_8227) @[ifu_bp_ctl.scala 434:23] - node _T_8229 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8230 = eq(_T_8229, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_8231 = and(_T_8228, _T_8230) @[ifu_bp_ctl.scala 434:81] - node _T_8232 = or(_T_8231, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8233 = bits(_T_8232, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_11_9 = mux(_T_8233, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8234 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8235 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8236 = eq(_T_8235, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_8237 = and(_T_8234, _T_8236) @[ifu_bp_ctl.scala 434:23] - node _T_8238 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8239 = eq(_T_8238, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_8240 = and(_T_8237, _T_8239) @[ifu_bp_ctl.scala 434:81] - node _T_8241 = or(_T_8240, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8242 = bits(_T_8241, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_11_10 = mux(_T_8242, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8243 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8244 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8245 = eq(_T_8244, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_8246 = and(_T_8243, _T_8245) @[ifu_bp_ctl.scala 434:23] - node _T_8247 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8248 = eq(_T_8247, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_8249 = and(_T_8246, _T_8248) @[ifu_bp_ctl.scala 434:81] - node _T_8250 = or(_T_8249, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8251 = bits(_T_8250, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_11_11 = mux(_T_8251, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8252 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8253 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8254 = eq(_T_8253, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_8255 = and(_T_8252, _T_8254) @[ifu_bp_ctl.scala 434:23] - node _T_8256 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8257 = eq(_T_8256, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_8258 = and(_T_8255, _T_8257) @[ifu_bp_ctl.scala 434:81] - node _T_8259 = or(_T_8258, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8260 = bits(_T_8259, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_11_12 = mux(_T_8260, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8261 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8262 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8263 = eq(_T_8262, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_8264 = and(_T_8261, _T_8263) @[ifu_bp_ctl.scala 434:23] - node _T_8265 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8266 = eq(_T_8265, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_8267 = and(_T_8264, _T_8266) @[ifu_bp_ctl.scala 434:81] - node _T_8268 = or(_T_8267, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8269 = bits(_T_8268, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_11_13 = mux(_T_8269, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8270 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8271 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8272 = eq(_T_8271, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_8273 = and(_T_8270, _T_8272) @[ifu_bp_ctl.scala 434:23] - node _T_8274 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8275 = eq(_T_8274, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_8276 = and(_T_8273, _T_8275) @[ifu_bp_ctl.scala 434:81] - node _T_8277 = or(_T_8276, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8278 = bits(_T_8277, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_11_14 = mux(_T_8278, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8279 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8280 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8281 = eq(_T_8280, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_8282 = and(_T_8279, _T_8281) @[ifu_bp_ctl.scala 434:23] - node _T_8283 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8284 = eq(_T_8283, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_8285 = and(_T_8282, _T_8284) @[ifu_bp_ctl.scala 434:81] - node _T_8286 = or(_T_8285, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8287 = bits(_T_8286, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_11_15 = mux(_T_8287, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8288 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8289 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8290 = eq(_T_8289, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_8291 = and(_T_8288, _T_8290) @[ifu_bp_ctl.scala 434:23] - node _T_8292 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8293 = eq(_T_8292, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_8294 = and(_T_8291, _T_8293) @[ifu_bp_ctl.scala 434:81] - node _T_8295 = or(_T_8294, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8296 = bits(_T_8295, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_12_0 = mux(_T_8296, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8297 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8298 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8299 = eq(_T_8298, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_8300 = and(_T_8297, _T_8299) @[ifu_bp_ctl.scala 434:23] - node _T_8301 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8302 = eq(_T_8301, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_8303 = and(_T_8300, _T_8302) @[ifu_bp_ctl.scala 434:81] - node _T_8304 = or(_T_8303, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8305 = bits(_T_8304, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_12_1 = mux(_T_8305, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8306 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8307 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8308 = eq(_T_8307, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_8309 = and(_T_8306, _T_8308) @[ifu_bp_ctl.scala 434:23] - node _T_8310 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8311 = eq(_T_8310, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_8312 = and(_T_8309, _T_8311) @[ifu_bp_ctl.scala 434:81] - node _T_8313 = or(_T_8312, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8314 = bits(_T_8313, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_12_2 = mux(_T_8314, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8315 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8316 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8317 = eq(_T_8316, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_8318 = and(_T_8315, _T_8317) @[ifu_bp_ctl.scala 434:23] - node _T_8319 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8320 = eq(_T_8319, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_8321 = and(_T_8318, _T_8320) @[ifu_bp_ctl.scala 434:81] - node _T_8322 = or(_T_8321, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8323 = bits(_T_8322, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_12_3 = mux(_T_8323, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8324 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8325 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8326 = eq(_T_8325, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_8327 = and(_T_8324, _T_8326) @[ifu_bp_ctl.scala 434:23] - node _T_8328 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8329 = eq(_T_8328, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_8330 = and(_T_8327, _T_8329) @[ifu_bp_ctl.scala 434:81] - node _T_8331 = or(_T_8330, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8332 = bits(_T_8331, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_12_4 = mux(_T_8332, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8333 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8334 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8335 = eq(_T_8334, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_8336 = and(_T_8333, _T_8335) @[ifu_bp_ctl.scala 434:23] - node _T_8337 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8338 = eq(_T_8337, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_8339 = and(_T_8336, _T_8338) @[ifu_bp_ctl.scala 434:81] - node _T_8340 = or(_T_8339, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8341 = bits(_T_8340, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_12_5 = mux(_T_8341, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8342 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8343 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8344 = eq(_T_8343, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_8345 = and(_T_8342, _T_8344) @[ifu_bp_ctl.scala 434:23] - node _T_8346 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8347 = eq(_T_8346, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_8348 = and(_T_8345, _T_8347) @[ifu_bp_ctl.scala 434:81] - node _T_8349 = or(_T_8348, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8350 = bits(_T_8349, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_12_6 = mux(_T_8350, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8351 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8352 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8353 = eq(_T_8352, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_8354 = and(_T_8351, _T_8353) @[ifu_bp_ctl.scala 434:23] - node _T_8355 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8356 = eq(_T_8355, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_8357 = and(_T_8354, _T_8356) @[ifu_bp_ctl.scala 434:81] - node _T_8358 = or(_T_8357, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8359 = bits(_T_8358, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_12_7 = mux(_T_8359, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8360 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8361 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8362 = eq(_T_8361, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_8363 = and(_T_8360, _T_8362) @[ifu_bp_ctl.scala 434:23] - node _T_8364 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8365 = eq(_T_8364, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_8366 = and(_T_8363, _T_8365) @[ifu_bp_ctl.scala 434:81] - node _T_8367 = or(_T_8366, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8368 = bits(_T_8367, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_12_8 = mux(_T_8368, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8369 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8370 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8371 = eq(_T_8370, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_8372 = and(_T_8369, _T_8371) @[ifu_bp_ctl.scala 434:23] - node _T_8373 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8374 = eq(_T_8373, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_8375 = and(_T_8372, _T_8374) @[ifu_bp_ctl.scala 434:81] - node _T_8376 = or(_T_8375, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8377 = bits(_T_8376, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_12_9 = mux(_T_8377, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8378 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8379 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8380 = eq(_T_8379, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_8381 = and(_T_8378, _T_8380) @[ifu_bp_ctl.scala 434:23] - node _T_8382 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8383 = eq(_T_8382, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_8384 = and(_T_8381, _T_8383) @[ifu_bp_ctl.scala 434:81] - node _T_8385 = or(_T_8384, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8386 = bits(_T_8385, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_12_10 = mux(_T_8386, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8387 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8388 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8389 = eq(_T_8388, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_8390 = and(_T_8387, _T_8389) @[ifu_bp_ctl.scala 434:23] - node _T_8391 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8392 = eq(_T_8391, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_8393 = and(_T_8390, _T_8392) @[ifu_bp_ctl.scala 434:81] - node _T_8394 = or(_T_8393, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8395 = bits(_T_8394, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_12_11 = mux(_T_8395, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8396 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8397 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8398 = eq(_T_8397, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_8399 = and(_T_8396, _T_8398) @[ifu_bp_ctl.scala 434:23] - node _T_8400 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8401 = eq(_T_8400, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_8402 = and(_T_8399, _T_8401) @[ifu_bp_ctl.scala 434:81] - node _T_8403 = or(_T_8402, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8404 = bits(_T_8403, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_12_12 = mux(_T_8404, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8405 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8406 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8407 = eq(_T_8406, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_8408 = and(_T_8405, _T_8407) @[ifu_bp_ctl.scala 434:23] - node _T_8409 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8410 = eq(_T_8409, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_8411 = and(_T_8408, _T_8410) @[ifu_bp_ctl.scala 434:81] - node _T_8412 = or(_T_8411, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8413 = bits(_T_8412, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_12_13 = mux(_T_8413, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8414 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8415 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8416 = eq(_T_8415, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_8417 = and(_T_8414, _T_8416) @[ifu_bp_ctl.scala 434:23] - node _T_8418 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8419 = eq(_T_8418, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_8420 = and(_T_8417, _T_8419) @[ifu_bp_ctl.scala 434:81] - node _T_8421 = or(_T_8420, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8422 = bits(_T_8421, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_12_14 = mux(_T_8422, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8423 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8424 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8425 = eq(_T_8424, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_8426 = and(_T_8423, _T_8425) @[ifu_bp_ctl.scala 434:23] - node _T_8427 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8428 = eq(_T_8427, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_8429 = and(_T_8426, _T_8428) @[ifu_bp_ctl.scala 434:81] - node _T_8430 = or(_T_8429, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8431 = bits(_T_8430, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_12_15 = mux(_T_8431, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8432 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8433 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8434 = eq(_T_8433, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_8435 = and(_T_8432, _T_8434) @[ifu_bp_ctl.scala 434:23] - node _T_8436 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8437 = eq(_T_8436, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_8438 = and(_T_8435, _T_8437) @[ifu_bp_ctl.scala 434:81] - node _T_8439 = or(_T_8438, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8440 = bits(_T_8439, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_13_0 = mux(_T_8440, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8441 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8442 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8443 = eq(_T_8442, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_8444 = and(_T_8441, _T_8443) @[ifu_bp_ctl.scala 434:23] - node _T_8445 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8446 = eq(_T_8445, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_8447 = and(_T_8444, _T_8446) @[ifu_bp_ctl.scala 434:81] - node _T_8448 = or(_T_8447, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8449 = bits(_T_8448, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_13_1 = mux(_T_8449, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8450 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8451 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8452 = eq(_T_8451, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_8453 = and(_T_8450, _T_8452) @[ifu_bp_ctl.scala 434:23] - node _T_8454 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8455 = eq(_T_8454, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_8456 = and(_T_8453, _T_8455) @[ifu_bp_ctl.scala 434:81] - node _T_8457 = or(_T_8456, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8458 = bits(_T_8457, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_13_2 = mux(_T_8458, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8459 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8460 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8461 = eq(_T_8460, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_8462 = and(_T_8459, _T_8461) @[ifu_bp_ctl.scala 434:23] - node _T_8463 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8464 = eq(_T_8463, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_8465 = and(_T_8462, _T_8464) @[ifu_bp_ctl.scala 434:81] - node _T_8466 = or(_T_8465, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8467 = bits(_T_8466, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_13_3 = mux(_T_8467, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8468 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8469 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8470 = eq(_T_8469, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_8471 = and(_T_8468, _T_8470) @[ifu_bp_ctl.scala 434:23] - node _T_8472 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8473 = eq(_T_8472, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_8474 = and(_T_8471, _T_8473) @[ifu_bp_ctl.scala 434:81] - node _T_8475 = or(_T_8474, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8476 = bits(_T_8475, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_13_4 = mux(_T_8476, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8477 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8478 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8479 = eq(_T_8478, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_8480 = and(_T_8477, _T_8479) @[ifu_bp_ctl.scala 434:23] - node _T_8481 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8482 = eq(_T_8481, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_8483 = and(_T_8480, _T_8482) @[ifu_bp_ctl.scala 434:81] - node _T_8484 = or(_T_8483, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8485 = bits(_T_8484, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_13_5 = mux(_T_8485, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8486 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8487 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8488 = eq(_T_8487, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_8489 = and(_T_8486, _T_8488) @[ifu_bp_ctl.scala 434:23] - node _T_8490 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8491 = eq(_T_8490, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_8492 = and(_T_8489, _T_8491) @[ifu_bp_ctl.scala 434:81] - node _T_8493 = or(_T_8492, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8494 = bits(_T_8493, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_13_6 = mux(_T_8494, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8495 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8496 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8497 = eq(_T_8496, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_8498 = and(_T_8495, _T_8497) @[ifu_bp_ctl.scala 434:23] - node _T_8499 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8500 = eq(_T_8499, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_8501 = and(_T_8498, _T_8500) @[ifu_bp_ctl.scala 434:81] - node _T_8502 = or(_T_8501, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8503 = bits(_T_8502, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_13_7 = mux(_T_8503, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8504 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8505 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8506 = eq(_T_8505, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_8507 = and(_T_8504, _T_8506) @[ifu_bp_ctl.scala 434:23] - node _T_8508 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8509 = eq(_T_8508, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_8510 = and(_T_8507, _T_8509) @[ifu_bp_ctl.scala 434:81] - node _T_8511 = or(_T_8510, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8512 = bits(_T_8511, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_13_8 = mux(_T_8512, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8513 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8514 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8515 = eq(_T_8514, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_8516 = and(_T_8513, _T_8515) @[ifu_bp_ctl.scala 434:23] - node _T_8517 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8518 = eq(_T_8517, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_8519 = and(_T_8516, _T_8518) @[ifu_bp_ctl.scala 434:81] - node _T_8520 = or(_T_8519, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8521 = bits(_T_8520, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_13_9 = mux(_T_8521, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8522 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8523 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8524 = eq(_T_8523, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_8525 = and(_T_8522, _T_8524) @[ifu_bp_ctl.scala 434:23] - node _T_8526 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8527 = eq(_T_8526, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_8528 = and(_T_8525, _T_8527) @[ifu_bp_ctl.scala 434:81] - node _T_8529 = or(_T_8528, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8530 = bits(_T_8529, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_13_10 = mux(_T_8530, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8531 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8532 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8533 = eq(_T_8532, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_8534 = and(_T_8531, _T_8533) @[ifu_bp_ctl.scala 434:23] - node _T_8535 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8536 = eq(_T_8535, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_8537 = and(_T_8534, _T_8536) @[ifu_bp_ctl.scala 434:81] - node _T_8538 = or(_T_8537, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8539 = bits(_T_8538, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_13_11 = mux(_T_8539, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8540 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8541 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8542 = eq(_T_8541, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_8543 = and(_T_8540, _T_8542) @[ifu_bp_ctl.scala 434:23] - node _T_8544 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8545 = eq(_T_8544, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_8546 = and(_T_8543, _T_8545) @[ifu_bp_ctl.scala 434:81] - node _T_8547 = or(_T_8546, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8548 = bits(_T_8547, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_13_12 = mux(_T_8548, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8549 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8550 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8551 = eq(_T_8550, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_8552 = and(_T_8549, _T_8551) @[ifu_bp_ctl.scala 434:23] - node _T_8553 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8554 = eq(_T_8553, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_8555 = and(_T_8552, _T_8554) @[ifu_bp_ctl.scala 434:81] - node _T_8556 = or(_T_8555, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8557 = bits(_T_8556, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_13_13 = mux(_T_8557, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8558 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8559 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8560 = eq(_T_8559, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_8561 = and(_T_8558, _T_8560) @[ifu_bp_ctl.scala 434:23] - node _T_8562 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8563 = eq(_T_8562, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_8564 = and(_T_8561, _T_8563) @[ifu_bp_ctl.scala 434:81] - node _T_8565 = or(_T_8564, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8566 = bits(_T_8565, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_13_14 = mux(_T_8566, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8567 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8568 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8569 = eq(_T_8568, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_8570 = and(_T_8567, _T_8569) @[ifu_bp_ctl.scala 434:23] - node _T_8571 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8572 = eq(_T_8571, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_8573 = and(_T_8570, _T_8572) @[ifu_bp_ctl.scala 434:81] - node _T_8574 = or(_T_8573, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8575 = bits(_T_8574, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_13_15 = mux(_T_8575, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8576 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8577 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8578 = eq(_T_8577, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_8579 = and(_T_8576, _T_8578) @[ifu_bp_ctl.scala 434:23] - node _T_8580 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8581 = eq(_T_8580, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_8582 = and(_T_8579, _T_8581) @[ifu_bp_ctl.scala 434:81] - node _T_8583 = or(_T_8582, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8584 = bits(_T_8583, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_14_0 = mux(_T_8584, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8585 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8586 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8587 = eq(_T_8586, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_8588 = and(_T_8585, _T_8587) @[ifu_bp_ctl.scala 434:23] - node _T_8589 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8590 = eq(_T_8589, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_8591 = and(_T_8588, _T_8590) @[ifu_bp_ctl.scala 434:81] - node _T_8592 = or(_T_8591, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8593 = bits(_T_8592, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_14_1 = mux(_T_8593, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8594 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8595 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8596 = eq(_T_8595, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_8597 = and(_T_8594, _T_8596) @[ifu_bp_ctl.scala 434:23] - node _T_8598 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8599 = eq(_T_8598, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_8600 = and(_T_8597, _T_8599) @[ifu_bp_ctl.scala 434:81] - node _T_8601 = or(_T_8600, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8602 = bits(_T_8601, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_14_2 = mux(_T_8602, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8603 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8604 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8605 = eq(_T_8604, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_8606 = and(_T_8603, _T_8605) @[ifu_bp_ctl.scala 434:23] - node _T_8607 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8608 = eq(_T_8607, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_8609 = and(_T_8606, _T_8608) @[ifu_bp_ctl.scala 434:81] - node _T_8610 = or(_T_8609, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8611 = bits(_T_8610, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_14_3 = mux(_T_8611, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8612 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8613 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8614 = eq(_T_8613, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_8615 = and(_T_8612, _T_8614) @[ifu_bp_ctl.scala 434:23] - node _T_8616 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8617 = eq(_T_8616, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_8618 = and(_T_8615, _T_8617) @[ifu_bp_ctl.scala 434:81] - node _T_8619 = or(_T_8618, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8620 = bits(_T_8619, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_14_4 = mux(_T_8620, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8621 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8622 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8623 = eq(_T_8622, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_8624 = and(_T_8621, _T_8623) @[ifu_bp_ctl.scala 434:23] - node _T_8625 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8626 = eq(_T_8625, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_8627 = and(_T_8624, _T_8626) @[ifu_bp_ctl.scala 434:81] - node _T_8628 = or(_T_8627, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8629 = bits(_T_8628, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_14_5 = mux(_T_8629, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8630 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8631 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8632 = eq(_T_8631, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_8633 = and(_T_8630, _T_8632) @[ifu_bp_ctl.scala 434:23] - node _T_8634 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8635 = eq(_T_8634, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_8636 = and(_T_8633, _T_8635) @[ifu_bp_ctl.scala 434:81] - node _T_8637 = or(_T_8636, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8638 = bits(_T_8637, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_14_6 = mux(_T_8638, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8639 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8640 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8641 = eq(_T_8640, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_8642 = and(_T_8639, _T_8641) @[ifu_bp_ctl.scala 434:23] - node _T_8643 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8644 = eq(_T_8643, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_8645 = and(_T_8642, _T_8644) @[ifu_bp_ctl.scala 434:81] - node _T_8646 = or(_T_8645, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8647 = bits(_T_8646, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_14_7 = mux(_T_8647, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8648 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8649 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8650 = eq(_T_8649, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_8651 = and(_T_8648, _T_8650) @[ifu_bp_ctl.scala 434:23] - node _T_8652 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8653 = eq(_T_8652, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_8654 = and(_T_8651, _T_8653) @[ifu_bp_ctl.scala 434:81] - node _T_8655 = or(_T_8654, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8656 = bits(_T_8655, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_14_8 = mux(_T_8656, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8657 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8658 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8659 = eq(_T_8658, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_8660 = and(_T_8657, _T_8659) @[ifu_bp_ctl.scala 434:23] - node _T_8661 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8662 = eq(_T_8661, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_8663 = and(_T_8660, _T_8662) @[ifu_bp_ctl.scala 434:81] - node _T_8664 = or(_T_8663, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8665 = bits(_T_8664, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_14_9 = mux(_T_8665, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8666 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8667 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8668 = eq(_T_8667, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_8669 = and(_T_8666, _T_8668) @[ifu_bp_ctl.scala 434:23] - node _T_8670 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8671 = eq(_T_8670, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_8672 = and(_T_8669, _T_8671) @[ifu_bp_ctl.scala 434:81] - node _T_8673 = or(_T_8672, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8674 = bits(_T_8673, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_14_10 = mux(_T_8674, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8675 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8676 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8677 = eq(_T_8676, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_8678 = and(_T_8675, _T_8677) @[ifu_bp_ctl.scala 434:23] - node _T_8679 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8680 = eq(_T_8679, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_8681 = and(_T_8678, _T_8680) @[ifu_bp_ctl.scala 434:81] - node _T_8682 = or(_T_8681, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8683 = bits(_T_8682, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_14_11 = mux(_T_8683, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8684 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8685 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8686 = eq(_T_8685, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_8687 = and(_T_8684, _T_8686) @[ifu_bp_ctl.scala 434:23] - node _T_8688 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8689 = eq(_T_8688, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_8690 = and(_T_8687, _T_8689) @[ifu_bp_ctl.scala 434:81] - node _T_8691 = or(_T_8690, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8692 = bits(_T_8691, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_14_12 = mux(_T_8692, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8693 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8694 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8695 = eq(_T_8694, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_8696 = and(_T_8693, _T_8695) @[ifu_bp_ctl.scala 434:23] - node _T_8697 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8698 = eq(_T_8697, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_8699 = and(_T_8696, _T_8698) @[ifu_bp_ctl.scala 434:81] - node _T_8700 = or(_T_8699, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8701 = bits(_T_8700, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_14_13 = mux(_T_8701, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8702 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8703 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8704 = eq(_T_8703, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_8705 = and(_T_8702, _T_8704) @[ifu_bp_ctl.scala 434:23] - node _T_8706 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8707 = eq(_T_8706, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_8708 = and(_T_8705, _T_8707) @[ifu_bp_ctl.scala 434:81] - node _T_8709 = or(_T_8708, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8710 = bits(_T_8709, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_14_14 = mux(_T_8710, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8711 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8712 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8713 = eq(_T_8712, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_8714 = and(_T_8711, _T_8713) @[ifu_bp_ctl.scala 434:23] - node _T_8715 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8716 = eq(_T_8715, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_8717 = and(_T_8714, _T_8716) @[ifu_bp_ctl.scala 434:81] - node _T_8718 = or(_T_8717, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8719 = bits(_T_8718, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_14_15 = mux(_T_8719, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8720 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8721 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8722 = eq(_T_8721, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_8723 = and(_T_8720, _T_8722) @[ifu_bp_ctl.scala 434:23] - node _T_8724 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8725 = eq(_T_8724, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_8726 = and(_T_8723, _T_8725) @[ifu_bp_ctl.scala 434:81] - node _T_8727 = or(_T_8726, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8728 = bits(_T_8727, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_15_0 = mux(_T_8728, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8729 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8730 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8731 = eq(_T_8730, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_8732 = and(_T_8729, _T_8731) @[ifu_bp_ctl.scala 434:23] - node _T_8733 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8734 = eq(_T_8733, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_8735 = and(_T_8732, _T_8734) @[ifu_bp_ctl.scala 434:81] - node _T_8736 = or(_T_8735, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8737 = bits(_T_8736, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_15_1 = mux(_T_8737, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8738 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8739 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8740 = eq(_T_8739, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_8741 = and(_T_8738, _T_8740) @[ifu_bp_ctl.scala 434:23] - node _T_8742 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8743 = eq(_T_8742, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_8744 = and(_T_8741, _T_8743) @[ifu_bp_ctl.scala 434:81] - node _T_8745 = or(_T_8744, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8746 = bits(_T_8745, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_15_2 = mux(_T_8746, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8747 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8748 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8749 = eq(_T_8748, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_8750 = and(_T_8747, _T_8749) @[ifu_bp_ctl.scala 434:23] - node _T_8751 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8752 = eq(_T_8751, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_8753 = and(_T_8750, _T_8752) @[ifu_bp_ctl.scala 434:81] - node _T_8754 = or(_T_8753, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8755 = bits(_T_8754, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_15_3 = mux(_T_8755, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8756 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8757 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8758 = eq(_T_8757, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_8759 = and(_T_8756, _T_8758) @[ifu_bp_ctl.scala 434:23] - node _T_8760 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8761 = eq(_T_8760, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_8762 = and(_T_8759, _T_8761) @[ifu_bp_ctl.scala 434:81] - node _T_8763 = or(_T_8762, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8764 = bits(_T_8763, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_15_4 = mux(_T_8764, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8765 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8766 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8767 = eq(_T_8766, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_8768 = and(_T_8765, _T_8767) @[ifu_bp_ctl.scala 434:23] - node _T_8769 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8770 = eq(_T_8769, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_8771 = and(_T_8768, _T_8770) @[ifu_bp_ctl.scala 434:81] - node _T_8772 = or(_T_8771, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8773 = bits(_T_8772, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_15_5 = mux(_T_8773, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8774 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8775 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8776 = eq(_T_8775, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_8777 = and(_T_8774, _T_8776) @[ifu_bp_ctl.scala 434:23] - node _T_8778 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8779 = eq(_T_8778, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_8780 = and(_T_8777, _T_8779) @[ifu_bp_ctl.scala 434:81] - node _T_8781 = or(_T_8780, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8782 = bits(_T_8781, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_15_6 = mux(_T_8782, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8783 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8784 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8785 = eq(_T_8784, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_8786 = and(_T_8783, _T_8785) @[ifu_bp_ctl.scala 434:23] - node _T_8787 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8788 = eq(_T_8787, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_8789 = and(_T_8786, _T_8788) @[ifu_bp_ctl.scala 434:81] - node _T_8790 = or(_T_8789, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8791 = bits(_T_8790, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_15_7 = mux(_T_8791, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8792 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8793 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8794 = eq(_T_8793, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_8795 = and(_T_8792, _T_8794) @[ifu_bp_ctl.scala 434:23] - node _T_8796 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8797 = eq(_T_8796, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_8798 = and(_T_8795, _T_8797) @[ifu_bp_ctl.scala 434:81] - node _T_8799 = or(_T_8798, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8800 = bits(_T_8799, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_15_8 = mux(_T_8800, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8801 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8802 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8803 = eq(_T_8802, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_8804 = and(_T_8801, _T_8803) @[ifu_bp_ctl.scala 434:23] - node _T_8805 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8806 = eq(_T_8805, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_8807 = and(_T_8804, _T_8806) @[ifu_bp_ctl.scala 434:81] - node _T_8808 = or(_T_8807, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8809 = bits(_T_8808, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_15_9 = mux(_T_8809, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8810 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8811 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8812 = eq(_T_8811, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_8813 = and(_T_8810, _T_8812) @[ifu_bp_ctl.scala 434:23] - node _T_8814 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8815 = eq(_T_8814, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_8816 = and(_T_8813, _T_8815) @[ifu_bp_ctl.scala 434:81] - node _T_8817 = or(_T_8816, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8818 = bits(_T_8817, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_15_10 = mux(_T_8818, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8819 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8820 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8821 = eq(_T_8820, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_8822 = and(_T_8819, _T_8821) @[ifu_bp_ctl.scala 434:23] - node _T_8823 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8824 = eq(_T_8823, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_8825 = and(_T_8822, _T_8824) @[ifu_bp_ctl.scala 434:81] - node _T_8826 = or(_T_8825, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8827 = bits(_T_8826, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_15_11 = mux(_T_8827, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8828 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8829 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8830 = eq(_T_8829, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_8831 = and(_T_8828, _T_8830) @[ifu_bp_ctl.scala 434:23] - node _T_8832 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8833 = eq(_T_8832, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_8834 = and(_T_8831, _T_8833) @[ifu_bp_ctl.scala 434:81] - node _T_8835 = or(_T_8834, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8836 = bits(_T_8835, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_15_12 = mux(_T_8836, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8837 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8838 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8839 = eq(_T_8838, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_8840 = and(_T_8837, _T_8839) @[ifu_bp_ctl.scala 434:23] - node _T_8841 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8842 = eq(_T_8841, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_8843 = and(_T_8840, _T_8842) @[ifu_bp_ctl.scala 434:81] - node _T_8844 = or(_T_8843, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8845 = bits(_T_8844, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_15_13 = mux(_T_8845, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8846 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8847 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8848 = eq(_T_8847, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_8849 = and(_T_8846, _T_8848) @[ifu_bp_ctl.scala 434:23] - node _T_8850 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8851 = eq(_T_8850, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_8852 = and(_T_8849, _T_8851) @[ifu_bp_ctl.scala 434:81] - node _T_8853 = or(_T_8852, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8854 = bits(_T_8853, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_15_14 = mux(_T_8854, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8855 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 434:20] - node _T_8856 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8857 = eq(_T_8856, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_8858 = and(_T_8855, _T_8857) @[ifu_bp_ctl.scala 434:23] - node _T_8859 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8860 = eq(_T_8859, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_8861 = and(_T_8858, _T_8860) @[ifu_bp_ctl.scala 434:81] - node _T_8862 = or(_T_8861, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8863 = bits(_T_8862, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_0_15_15 = mux(_T_8863, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8864 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_8865 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8866 = eq(_T_8865, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_8867 = and(_T_8864, _T_8866) @[ifu_bp_ctl.scala 434:23] - node _T_8868 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8869 = eq(_T_8868, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_8870 = and(_T_8867, _T_8869) @[ifu_bp_ctl.scala 434:81] - node _T_8871 = or(_T_8870, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8872 = bits(_T_8871, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_0_0 = mux(_T_8872, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8873 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_8874 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8875 = eq(_T_8874, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_8876 = and(_T_8873, _T_8875) @[ifu_bp_ctl.scala 434:23] - node _T_8877 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8878 = eq(_T_8877, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_8879 = and(_T_8876, _T_8878) @[ifu_bp_ctl.scala 434:81] - node _T_8880 = or(_T_8879, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8881 = bits(_T_8880, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_0_1 = mux(_T_8881, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8882 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_8883 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8884 = eq(_T_8883, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_8885 = and(_T_8882, _T_8884) @[ifu_bp_ctl.scala 434:23] - node _T_8886 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8887 = eq(_T_8886, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_8888 = and(_T_8885, _T_8887) @[ifu_bp_ctl.scala 434:81] - node _T_8889 = or(_T_8888, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8890 = bits(_T_8889, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_0_2 = mux(_T_8890, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8891 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_8892 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8893 = eq(_T_8892, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_8894 = and(_T_8891, _T_8893) @[ifu_bp_ctl.scala 434:23] - node _T_8895 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8896 = eq(_T_8895, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_8897 = and(_T_8894, _T_8896) @[ifu_bp_ctl.scala 434:81] - node _T_8898 = or(_T_8897, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8899 = bits(_T_8898, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_0_3 = mux(_T_8899, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8900 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_8901 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8902 = eq(_T_8901, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_8903 = and(_T_8900, _T_8902) @[ifu_bp_ctl.scala 434:23] - node _T_8904 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8905 = eq(_T_8904, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_8906 = and(_T_8903, _T_8905) @[ifu_bp_ctl.scala 434:81] - node _T_8907 = or(_T_8906, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8908 = bits(_T_8907, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_0_4 = mux(_T_8908, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8909 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_8910 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8911 = eq(_T_8910, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_8912 = and(_T_8909, _T_8911) @[ifu_bp_ctl.scala 434:23] - node _T_8913 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8914 = eq(_T_8913, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_8915 = and(_T_8912, _T_8914) @[ifu_bp_ctl.scala 434:81] - node _T_8916 = or(_T_8915, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8917 = bits(_T_8916, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_0_5 = mux(_T_8917, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8918 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_8919 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8920 = eq(_T_8919, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_8921 = and(_T_8918, _T_8920) @[ifu_bp_ctl.scala 434:23] - node _T_8922 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8923 = eq(_T_8922, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_8924 = and(_T_8921, _T_8923) @[ifu_bp_ctl.scala 434:81] - node _T_8925 = or(_T_8924, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8926 = bits(_T_8925, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_0_6 = mux(_T_8926, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8927 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_8928 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8929 = eq(_T_8928, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_8930 = and(_T_8927, _T_8929) @[ifu_bp_ctl.scala 434:23] - node _T_8931 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8932 = eq(_T_8931, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_8933 = and(_T_8930, _T_8932) @[ifu_bp_ctl.scala 434:81] - node _T_8934 = or(_T_8933, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8935 = bits(_T_8934, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_0_7 = mux(_T_8935, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8936 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_8937 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8938 = eq(_T_8937, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_8939 = and(_T_8936, _T_8938) @[ifu_bp_ctl.scala 434:23] - node _T_8940 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8941 = eq(_T_8940, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_8942 = and(_T_8939, _T_8941) @[ifu_bp_ctl.scala 434:81] - node _T_8943 = or(_T_8942, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8944 = bits(_T_8943, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_0_8 = mux(_T_8944, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8945 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_8946 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8947 = eq(_T_8946, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_8948 = and(_T_8945, _T_8947) @[ifu_bp_ctl.scala 434:23] - node _T_8949 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8950 = eq(_T_8949, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_8951 = and(_T_8948, _T_8950) @[ifu_bp_ctl.scala 434:81] - node _T_8952 = or(_T_8951, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8953 = bits(_T_8952, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_0_9 = mux(_T_8953, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8954 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_8955 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8956 = eq(_T_8955, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_8957 = and(_T_8954, _T_8956) @[ifu_bp_ctl.scala 434:23] - node _T_8958 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8959 = eq(_T_8958, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_8960 = and(_T_8957, _T_8959) @[ifu_bp_ctl.scala 434:81] - node _T_8961 = or(_T_8960, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8962 = bits(_T_8961, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_0_10 = mux(_T_8962, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8963 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_8964 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8965 = eq(_T_8964, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_8966 = and(_T_8963, _T_8965) @[ifu_bp_ctl.scala 434:23] - node _T_8967 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8968 = eq(_T_8967, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_8969 = and(_T_8966, _T_8968) @[ifu_bp_ctl.scala 434:81] - node _T_8970 = or(_T_8969, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8971 = bits(_T_8970, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_0_11 = mux(_T_8971, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8972 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_8973 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8974 = eq(_T_8973, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_8975 = and(_T_8972, _T_8974) @[ifu_bp_ctl.scala 434:23] - node _T_8976 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8977 = eq(_T_8976, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_8978 = and(_T_8975, _T_8977) @[ifu_bp_ctl.scala 434:81] - node _T_8979 = or(_T_8978, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8980 = bits(_T_8979, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_0_12 = mux(_T_8980, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8981 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_8982 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8983 = eq(_T_8982, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_8984 = and(_T_8981, _T_8983) @[ifu_bp_ctl.scala 434:23] - node _T_8985 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8986 = eq(_T_8985, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_8987 = and(_T_8984, _T_8986) @[ifu_bp_ctl.scala 434:81] - node _T_8988 = or(_T_8987, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8989 = bits(_T_8988, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_0_13 = mux(_T_8989, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8990 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_8991 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_8992 = eq(_T_8991, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_8993 = and(_T_8990, _T_8992) @[ifu_bp_ctl.scala 434:23] - node _T_8994 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_8995 = eq(_T_8994, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_8996 = and(_T_8993, _T_8995) @[ifu_bp_ctl.scala 434:81] - node _T_8997 = or(_T_8996, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_8998 = bits(_T_8997, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_0_14 = mux(_T_8998, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_8999 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9000 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9001 = eq(_T_9000, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_9002 = and(_T_8999, _T_9001) @[ifu_bp_ctl.scala 434:23] - node _T_9003 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9004 = eq(_T_9003, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:154] - node _T_9005 = and(_T_9002, _T_9004) @[ifu_bp_ctl.scala 434:81] - node _T_9006 = or(_T_9005, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9007 = bits(_T_9006, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_0_15 = mux(_T_9007, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9008 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9009 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9010 = eq(_T_9009, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_9011 = and(_T_9008, _T_9010) @[ifu_bp_ctl.scala 434:23] - node _T_9012 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9013 = eq(_T_9012, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_9014 = and(_T_9011, _T_9013) @[ifu_bp_ctl.scala 434:81] - node _T_9015 = or(_T_9014, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9016 = bits(_T_9015, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_1_0 = mux(_T_9016, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9017 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9018 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9019 = eq(_T_9018, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_9020 = and(_T_9017, _T_9019) @[ifu_bp_ctl.scala 434:23] - node _T_9021 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9022 = eq(_T_9021, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_9023 = and(_T_9020, _T_9022) @[ifu_bp_ctl.scala 434:81] - node _T_9024 = or(_T_9023, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9025 = bits(_T_9024, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_1_1 = mux(_T_9025, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9026 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9027 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9028 = eq(_T_9027, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_9029 = and(_T_9026, _T_9028) @[ifu_bp_ctl.scala 434:23] - node _T_9030 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9031 = eq(_T_9030, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_9032 = and(_T_9029, _T_9031) @[ifu_bp_ctl.scala 434:81] - node _T_9033 = or(_T_9032, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9034 = bits(_T_9033, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_1_2 = mux(_T_9034, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9035 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9036 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9037 = eq(_T_9036, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_9038 = and(_T_9035, _T_9037) @[ifu_bp_ctl.scala 434:23] - node _T_9039 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9040 = eq(_T_9039, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_9041 = and(_T_9038, _T_9040) @[ifu_bp_ctl.scala 434:81] - node _T_9042 = or(_T_9041, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9043 = bits(_T_9042, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_1_3 = mux(_T_9043, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9044 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9045 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9046 = eq(_T_9045, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_9047 = and(_T_9044, _T_9046) @[ifu_bp_ctl.scala 434:23] - node _T_9048 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9049 = eq(_T_9048, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_9050 = and(_T_9047, _T_9049) @[ifu_bp_ctl.scala 434:81] - node _T_9051 = or(_T_9050, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9052 = bits(_T_9051, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_1_4 = mux(_T_9052, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9053 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9054 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9055 = eq(_T_9054, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_9056 = and(_T_9053, _T_9055) @[ifu_bp_ctl.scala 434:23] - node _T_9057 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9058 = eq(_T_9057, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_9059 = and(_T_9056, _T_9058) @[ifu_bp_ctl.scala 434:81] - node _T_9060 = or(_T_9059, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9061 = bits(_T_9060, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_1_5 = mux(_T_9061, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9062 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9063 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9064 = eq(_T_9063, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_9065 = and(_T_9062, _T_9064) @[ifu_bp_ctl.scala 434:23] - node _T_9066 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9067 = eq(_T_9066, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_9068 = and(_T_9065, _T_9067) @[ifu_bp_ctl.scala 434:81] - node _T_9069 = or(_T_9068, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9070 = bits(_T_9069, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_1_6 = mux(_T_9070, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9071 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9072 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9073 = eq(_T_9072, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_9074 = and(_T_9071, _T_9073) @[ifu_bp_ctl.scala 434:23] - node _T_9075 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9076 = eq(_T_9075, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_9077 = and(_T_9074, _T_9076) @[ifu_bp_ctl.scala 434:81] - node _T_9078 = or(_T_9077, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9079 = bits(_T_9078, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_1_7 = mux(_T_9079, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9080 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9081 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9082 = eq(_T_9081, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_9083 = and(_T_9080, _T_9082) @[ifu_bp_ctl.scala 434:23] - node _T_9084 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9085 = eq(_T_9084, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_9086 = and(_T_9083, _T_9085) @[ifu_bp_ctl.scala 434:81] - node _T_9087 = or(_T_9086, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9088 = bits(_T_9087, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_1_8 = mux(_T_9088, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9089 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9090 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9091 = eq(_T_9090, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_9092 = and(_T_9089, _T_9091) @[ifu_bp_ctl.scala 434:23] - node _T_9093 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9094 = eq(_T_9093, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_9095 = and(_T_9092, _T_9094) @[ifu_bp_ctl.scala 434:81] - node _T_9096 = or(_T_9095, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9097 = bits(_T_9096, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_1_9 = mux(_T_9097, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9098 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9099 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9100 = eq(_T_9099, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_9101 = and(_T_9098, _T_9100) @[ifu_bp_ctl.scala 434:23] - node _T_9102 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9103 = eq(_T_9102, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_9104 = and(_T_9101, _T_9103) @[ifu_bp_ctl.scala 434:81] - node _T_9105 = or(_T_9104, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9106 = bits(_T_9105, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_1_10 = mux(_T_9106, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9107 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9108 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9109 = eq(_T_9108, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_9110 = and(_T_9107, _T_9109) @[ifu_bp_ctl.scala 434:23] - node _T_9111 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9112 = eq(_T_9111, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_9113 = and(_T_9110, _T_9112) @[ifu_bp_ctl.scala 434:81] - node _T_9114 = or(_T_9113, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9115 = bits(_T_9114, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_1_11 = mux(_T_9115, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9116 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9117 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9118 = eq(_T_9117, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_9119 = and(_T_9116, _T_9118) @[ifu_bp_ctl.scala 434:23] - node _T_9120 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9121 = eq(_T_9120, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_9122 = and(_T_9119, _T_9121) @[ifu_bp_ctl.scala 434:81] - node _T_9123 = or(_T_9122, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9124 = bits(_T_9123, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_1_12 = mux(_T_9124, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9125 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9126 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9127 = eq(_T_9126, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_9128 = and(_T_9125, _T_9127) @[ifu_bp_ctl.scala 434:23] - node _T_9129 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9130 = eq(_T_9129, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_9131 = and(_T_9128, _T_9130) @[ifu_bp_ctl.scala 434:81] - node _T_9132 = or(_T_9131, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9133 = bits(_T_9132, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_1_13 = mux(_T_9133, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9134 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9135 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9136 = eq(_T_9135, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_9137 = and(_T_9134, _T_9136) @[ifu_bp_ctl.scala 434:23] - node _T_9138 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9139 = eq(_T_9138, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_9140 = and(_T_9137, _T_9139) @[ifu_bp_ctl.scala 434:81] - node _T_9141 = or(_T_9140, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9142 = bits(_T_9141, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_1_14 = mux(_T_9142, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9143 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9144 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9145 = eq(_T_9144, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_9146 = and(_T_9143, _T_9145) @[ifu_bp_ctl.scala 434:23] - node _T_9147 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9148 = eq(_T_9147, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:154] - node _T_9149 = and(_T_9146, _T_9148) @[ifu_bp_ctl.scala 434:81] - node _T_9150 = or(_T_9149, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9151 = bits(_T_9150, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_1_15 = mux(_T_9151, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9152 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9153 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9154 = eq(_T_9153, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_9155 = and(_T_9152, _T_9154) @[ifu_bp_ctl.scala 434:23] - node _T_9156 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9157 = eq(_T_9156, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_9158 = and(_T_9155, _T_9157) @[ifu_bp_ctl.scala 434:81] - node _T_9159 = or(_T_9158, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9160 = bits(_T_9159, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_2_0 = mux(_T_9160, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9161 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9162 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9163 = eq(_T_9162, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_9164 = and(_T_9161, _T_9163) @[ifu_bp_ctl.scala 434:23] - node _T_9165 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9166 = eq(_T_9165, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_9167 = and(_T_9164, _T_9166) @[ifu_bp_ctl.scala 434:81] - node _T_9168 = or(_T_9167, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9169 = bits(_T_9168, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_2_1 = mux(_T_9169, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9170 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9171 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9172 = eq(_T_9171, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_9173 = and(_T_9170, _T_9172) @[ifu_bp_ctl.scala 434:23] - node _T_9174 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9175 = eq(_T_9174, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_9176 = and(_T_9173, _T_9175) @[ifu_bp_ctl.scala 434:81] - node _T_9177 = or(_T_9176, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9178 = bits(_T_9177, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_2_2 = mux(_T_9178, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9179 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9180 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9181 = eq(_T_9180, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_9182 = and(_T_9179, _T_9181) @[ifu_bp_ctl.scala 434:23] - node _T_9183 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9184 = eq(_T_9183, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_9185 = and(_T_9182, _T_9184) @[ifu_bp_ctl.scala 434:81] - node _T_9186 = or(_T_9185, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9187 = bits(_T_9186, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_2_3 = mux(_T_9187, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9188 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9189 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9190 = eq(_T_9189, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_9191 = and(_T_9188, _T_9190) @[ifu_bp_ctl.scala 434:23] - node _T_9192 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9193 = eq(_T_9192, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_9194 = and(_T_9191, _T_9193) @[ifu_bp_ctl.scala 434:81] - node _T_9195 = or(_T_9194, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9196 = bits(_T_9195, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_2_4 = mux(_T_9196, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9197 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9198 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9199 = eq(_T_9198, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_9200 = and(_T_9197, _T_9199) @[ifu_bp_ctl.scala 434:23] - node _T_9201 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9202 = eq(_T_9201, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_9203 = and(_T_9200, _T_9202) @[ifu_bp_ctl.scala 434:81] - node _T_9204 = or(_T_9203, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9205 = bits(_T_9204, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_2_5 = mux(_T_9205, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9206 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9207 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9208 = eq(_T_9207, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_9209 = and(_T_9206, _T_9208) @[ifu_bp_ctl.scala 434:23] - node _T_9210 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9211 = eq(_T_9210, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_9212 = and(_T_9209, _T_9211) @[ifu_bp_ctl.scala 434:81] - node _T_9213 = or(_T_9212, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9214 = bits(_T_9213, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_2_6 = mux(_T_9214, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9215 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9216 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9217 = eq(_T_9216, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_9218 = and(_T_9215, _T_9217) @[ifu_bp_ctl.scala 434:23] - node _T_9219 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9220 = eq(_T_9219, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_9221 = and(_T_9218, _T_9220) @[ifu_bp_ctl.scala 434:81] - node _T_9222 = or(_T_9221, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9223 = bits(_T_9222, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_2_7 = mux(_T_9223, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9224 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9225 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9226 = eq(_T_9225, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_9227 = and(_T_9224, _T_9226) @[ifu_bp_ctl.scala 434:23] - node _T_9228 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9229 = eq(_T_9228, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_9230 = and(_T_9227, _T_9229) @[ifu_bp_ctl.scala 434:81] - node _T_9231 = or(_T_9230, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9232 = bits(_T_9231, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_2_8 = mux(_T_9232, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9233 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9234 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9235 = eq(_T_9234, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_9236 = and(_T_9233, _T_9235) @[ifu_bp_ctl.scala 434:23] - node _T_9237 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9238 = eq(_T_9237, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_9239 = and(_T_9236, _T_9238) @[ifu_bp_ctl.scala 434:81] - node _T_9240 = or(_T_9239, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9241 = bits(_T_9240, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_2_9 = mux(_T_9241, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9242 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9243 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9244 = eq(_T_9243, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_9245 = and(_T_9242, _T_9244) @[ifu_bp_ctl.scala 434:23] - node _T_9246 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9247 = eq(_T_9246, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_9248 = and(_T_9245, _T_9247) @[ifu_bp_ctl.scala 434:81] - node _T_9249 = or(_T_9248, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9250 = bits(_T_9249, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_2_10 = mux(_T_9250, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9251 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9252 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9253 = eq(_T_9252, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_9254 = and(_T_9251, _T_9253) @[ifu_bp_ctl.scala 434:23] - node _T_9255 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9256 = eq(_T_9255, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_9257 = and(_T_9254, _T_9256) @[ifu_bp_ctl.scala 434:81] - node _T_9258 = or(_T_9257, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9259 = bits(_T_9258, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_2_11 = mux(_T_9259, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9260 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9261 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9262 = eq(_T_9261, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_9263 = and(_T_9260, _T_9262) @[ifu_bp_ctl.scala 434:23] - node _T_9264 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9265 = eq(_T_9264, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_9266 = and(_T_9263, _T_9265) @[ifu_bp_ctl.scala 434:81] - node _T_9267 = or(_T_9266, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9268 = bits(_T_9267, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_2_12 = mux(_T_9268, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9269 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9270 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9271 = eq(_T_9270, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_9272 = and(_T_9269, _T_9271) @[ifu_bp_ctl.scala 434:23] - node _T_9273 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9274 = eq(_T_9273, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_9275 = and(_T_9272, _T_9274) @[ifu_bp_ctl.scala 434:81] - node _T_9276 = or(_T_9275, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9277 = bits(_T_9276, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_2_13 = mux(_T_9277, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9278 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9279 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9280 = eq(_T_9279, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_9281 = and(_T_9278, _T_9280) @[ifu_bp_ctl.scala 434:23] - node _T_9282 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9283 = eq(_T_9282, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_9284 = and(_T_9281, _T_9283) @[ifu_bp_ctl.scala 434:81] - node _T_9285 = or(_T_9284, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9286 = bits(_T_9285, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_2_14 = mux(_T_9286, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9287 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9288 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9289 = eq(_T_9288, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_9290 = and(_T_9287, _T_9289) @[ifu_bp_ctl.scala 434:23] - node _T_9291 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9292 = eq(_T_9291, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:154] - node _T_9293 = and(_T_9290, _T_9292) @[ifu_bp_ctl.scala 434:81] - node _T_9294 = or(_T_9293, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9295 = bits(_T_9294, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_2_15 = mux(_T_9295, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9296 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9297 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9298 = eq(_T_9297, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_9299 = and(_T_9296, _T_9298) @[ifu_bp_ctl.scala 434:23] - node _T_9300 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9301 = eq(_T_9300, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_9302 = and(_T_9299, _T_9301) @[ifu_bp_ctl.scala 434:81] - node _T_9303 = or(_T_9302, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9304 = bits(_T_9303, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_3_0 = mux(_T_9304, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9305 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9306 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9307 = eq(_T_9306, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_9308 = and(_T_9305, _T_9307) @[ifu_bp_ctl.scala 434:23] - node _T_9309 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9310 = eq(_T_9309, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_9311 = and(_T_9308, _T_9310) @[ifu_bp_ctl.scala 434:81] - node _T_9312 = or(_T_9311, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9313 = bits(_T_9312, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_3_1 = mux(_T_9313, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9314 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9315 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9316 = eq(_T_9315, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_9317 = and(_T_9314, _T_9316) @[ifu_bp_ctl.scala 434:23] - node _T_9318 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9319 = eq(_T_9318, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_9320 = and(_T_9317, _T_9319) @[ifu_bp_ctl.scala 434:81] - node _T_9321 = or(_T_9320, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9322 = bits(_T_9321, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_3_2 = mux(_T_9322, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9323 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9324 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9325 = eq(_T_9324, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_9326 = and(_T_9323, _T_9325) @[ifu_bp_ctl.scala 434:23] - node _T_9327 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9328 = eq(_T_9327, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_9329 = and(_T_9326, _T_9328) @[ifu_bp_ctl.scala 434:81] - node _T_9330 = or(_T_9329, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9331 = bits(_T_9330, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_3_3 = mux(_T_9331, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9332 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9333 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9334 = eq(_T_9333, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_9335 = and(_T_9332, _T_9334) @[ifu_bp_ctl.scala 434:23] - node _T_9336 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9337 = eq(_T_9336, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_9338 = and(_T_9335, _T_9337) @[ifu_bp_ctl.scala 434:81] - node _T_9339 = or(_T_9338, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9340 = bits(_T_9339, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_3_4 = mux(_T_9340, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9341 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9342 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9343 = eq(_T_9342, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_9344 = and(_T_9341, _T_9343) @[ifu_bp_ctl.scala 434:23] - node _T_9345 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9346 = eq(_T_9345, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_9347 = and(_T_9344, _T_9346) @[ifu_bp_ctl.scala 434:81] - node _T_9348 = or(_T_9347, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9349 = bits(_T_9348, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_3_5 = mux(_T_9349, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9350 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9351 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9352 = eq(_T_9351, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_9353 = and(_T_9350, _T_9352) @[ifu_bp_ctl.scala 434:23] - node _T_9354 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9355 = eq(_T_9354, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_9356 = and(_T_9353, _T_9355) @[ifu_bp_ctl.scala 434:81] - node _T_9357 = or(_T_9356, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9358 = bits(_T_9357, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_3_6 = mux(_T_9358, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9359 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9360 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9361 = eq(_T_9360, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_9362 = and(_T_9359, _T_9361) @[ifu_bp_ctl.scala 434:23] - node _T_9363 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9364 = eq(_T_9363, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_9365 = and(_T_9362, _T_9364) @[ifu_bp_ctl.scala 434:81] - node _T_9366 = or(_T_9365, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9367 = bits(_T_9366, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_3_7 = mux(_T_9367, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9368 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9369 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9370 = eq(_T_9369, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_9371 = and(_T_9368, _T_9370) @[ifu_bp_ctl.scala 434:23] - node _T_9372 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9373 = eq(_T_9372, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_9374 = and(_T_9371, _T_9373) @[ifu_bp_ctl.scala 434:81] - node _T_9375 = or(_T_9374, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9376 = bits(_T_9375, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_3_8 = mux(_T_9376, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9377 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9378 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9379 = eq(_T_9378, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_9380 = and(_T_9377, _T_9379) @[ifu_bp_ctl.scala 434:23] - node _T_9381 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9382 = eq(_T_9381, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_9383 = and(_T_9380, _T_9382) @[ifu_bp_ctl.scala 434:81] - node _T_9384 = or(_T_9383, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9385 = bits(_T_9384, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_3_9 = mux(_T_9385, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9386 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9387 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9388 = eq(_T_9387, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_9389 = and(_T_9386, _T_9388) @[ifu_bp_ctl.scala 434:23] - node _T_9390 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9391 = eq(_T_9390, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_9392 = and(_T_9389, _T_9391) @[ifu_bp_ctl.scala 434:81] - node _T_9393 = or(_T_9392, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9394 = bits(_T_9393, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_3_10 = mux(_T_9394, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9395 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9396 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9397 = eq(_T_9396, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_9398 = and(_T_9395, _T_9397) @[ifu_bp_ctl.scala 434:23] - node _T_9399 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9400 = eq(_T_9399, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_9401 = and(_T_9398, _T_9400) @[ifu_bp_ctl.scala 434:81] - node _T_9402 = or(_T_9401, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9403 = bits(_T_9402, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_3_11 = mux(_T_9403, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9404 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9405 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9406 = eq(_T_9405, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_9407 = and(_T_9404, _T_9406) @[ifu_bp_ctl.scala 434:23] - node _T_9408 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9409 = eq(_T_9408, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_9410 = and(_T_9407, _T_9409) @[ifu_bp_ctl.scala 434:81] - node _T_9411 = or(_T_9410, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9412 = bits(_T_9411, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_3_12 = mux(_T_9412, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9413 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9414 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9415 = eq(_T_9414, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_9416 = and(_T_9413, _T_9415) @[ifu_bp_ctl.scala 434:23] - node _T_9417 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9418 = eq(_T_9417, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_9419 = and(_T_9416, _T_9418) @[ifu_bp_ctl.scala 434:81] - node _T_9420 = or(_T_9419, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9421 = bits(_T_9420, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_3_13 = mux(_T_9421, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9422 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9423 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9424 = eq(_T_9423, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_9425 = and(_T_9422, _T_9424) @[ifu_bp_ctl.scala 434:23] - node _T_9426 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9427 = eq(_T_9426, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_9428 = and(_T_9425, _T_9427) @[ifu_bp_ctl.scala 434:81] - node _T_9429 = or(_T_9428, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9430 = bits(_T_9429, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_3_14 = mux(_T_9430, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9431 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9432 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9433 = eq(_T_9432, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_9434 = and(_T_9431, _T_9433) @[ifu_bp_ctl.scala 434:23] - node _T_9435 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9436 = eq(_T_9435, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:154] - node _T_9437 = and(_T_9434, _T_9436) @[ifu_bp_ctl.scala 434:81] - node _T_9438 = or(_T_9437, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9439 = bits(_T_9438, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_3_15 = mux(_T_9439, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9440 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9441 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9442 = eq(_T_9441, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_9443 = and(_T_9440, _T_9442) @[ifu_bp_ctl.scala 434:23] - node _T_9444 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9445 = eq(_T_9444, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_9446 = and(_T_9443, _T_9445) @[ifu_bp_ctl.scala 434:81] - node _T_9447 = or(_T_9446, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9448 = bits(_T_9447, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_4_0 = mux(_T_9448, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9449 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9450 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9451 = eq(_T_9450, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_9452 = and(_T_9449, _T_9451) @[ifu_bp_ctl.scala 434:23] - node _T_9453 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9454 = eq(_T_9453, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_9455 = and(_T_9452, _T_9454) @[ifu_bp_ctl.scala 434:81] - node _T_9456 = or(_T_9455, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9457 = bits(_T_9456, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_4_1 = mux(_T_9457, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9458 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9459 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9460 = eq(_T_9459, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_9461 = and(_T_9458, _T_9460) @[ifu_bp_ctl.scala 434:23] - node _T_9462 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9463 = eq(_T_9462, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_9464 = and(_T_9461, _T_9463) @[ifu_bp_ctl.scala 434:81] - node _T_9465 = or(_T_9464, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9466 = bits(_T_9465, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_4_2 = mux(_T_9466, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9467 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9468 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9469 = eq(_T_9468, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_9470 = and(_T_9467, _T_9469) @[ifu_bp_ctl.scala 434:23] - node _T_9471 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9472 = eq(_T_9471, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_9473 = and(_T_9470, _T_9472) @[ifu_bp_ctl.scala 434:81] - node _T_9474 = or(_T_9473, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9475 = bits(_T_9474, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_4_3 = mux(_T_9475, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9476 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9477 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9478 = eq(_T_9477, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_9479 = and(_T_9476, _T_9478) @[ifu_bp_ctl.scala 434:23] - node _T_9480 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9481 = eq(_T_9480, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_9482 = and(_T_9479, _T_9481) @[ifu_bp_ctl.scala 434:81] - node _T_9483 = or(_T_9482, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9484 = bits(_T_9483, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_4_4 = mux(_T_9484, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9485 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9486 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9487 = eq(_T_9486, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_9488 = and(_T_9485, _T_9487) @[ifu_bp_ctl.scala 434:23] - node _T_9489 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9490 = eq(_T_9489, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_9491 = and(_T_9488, _T_9490) @[ifu_bp_ctl.scala 434:81] - node _T_9492 = or(_T_9491, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9493 = bits(_T_9492, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_4_5 = mux(_T_9493, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9494 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9495 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9496 = eq(_T_9495, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_9497 = and(_T_9494, _T_9496) @[ifu_bp_ctl.scala 434:23] - node _T_9498 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9499 = eq(_T_9498, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_9500 = and(_T_9497, _T_9499) @[ifu_bp_ctl.scala 434:81] - node _T_9501 = or(_T_9500, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9502 = bits(_T_9501, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_4_6 = mux(_T_9502, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9503 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9504 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9505 = eq(_T_9504, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_9506 = and(_T_9503, _T_9505) @[ifu_bp_ctl.scala 434:23] - node _T_9507 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9508 = eq(_T_9507, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_9509 = and(_T_9506, _T_9508) @[ifu_bp_ctl.scala 434:81] - node _T_9510 = or(_T_9509, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9511 = bits(_T_9510, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_4_7 = mux(_T_9511, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9512 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9513 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9514 = eq(_T_9513, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_9515 = and(_T_9512, _T_9514) @[ifu_bp_ctl.scala 434:23] - node _T_9516 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9517 = eq(_T_9516, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_9518 = and(_T_9515, _T_9517) @[ifu_bp_ctl.scala 434:81] - node _T_9519 = or(_T_9518, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9520 = bits(_T_9519, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_4_8 = mux(_T_9520, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9521 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9522 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9523 = eq(_T_9522, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_9524 = and(_T_9521, _T_9523) @[ifu_bp_ctl.scala 434:23] - node _T_9525 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9526 = eq(_T_9525, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_9527 = and(_T_9524, _T_9526) @[ifu_bp_ctl.scala 434:81] - node _T_9528 = or(_T_9527, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9529 = bits(_T_9528, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_4_9 = mux(_T_9529, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9530 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9531 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9532 = eq(_T_9531, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_9533 = and(_T_9530, _T_9532) @[ifu_bp_ctl.scala 434:23] - node _T_9534 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9535 = eq(_T_9534, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_9536 = and(_T_9533, _T_9535) @[ifu_bp_ctl.scala 434:81] - node _T_9537 = or(_T_9536, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9538 = bits(_T_9537, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_4_10 = mux(_T_9538, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9539 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9540 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9541 = eq(_T_9540, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_9542 = and(_T_9539, _T_9541) @[ifu_bp_ctl.scala 434:23] - node _T_9543 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9544 = eq(_T_9543, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_9545 = and(_T_9542, _T_9544) @[ifu_bp_ctl.scala 434:81] - node _T_9546 = or(_T_9545, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9547 = bits(_T_9546, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_4_11 = mux(_T_9547, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9548 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9549 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9550 = eq(_T_9549, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_9551 = and(_T_9548, _T_9550) @[ifu_bp_ctl.scala 434:23] - node _T_9552 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9553 = eq(_T_9552, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_9554 = and(_T_9551, _T_9553) @[ifu_bp_ctl.scala 434:81] - node _T_9555 = or(_T_9554, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9556 = bits(_T_9555, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_4_12 = mux(_T_9556, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9557 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9558 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9559 = eq(_T_9558, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_9560 = and(_T_9557, _T_9559) @[ifu_bp_ctl.scala 434:23] - node _T_9561 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9562 = eq(_T_9561, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_9563 = and(_T_9560, _T_9562) @[ifu_bp_ctl.scala 434:81] - node _T_9564 = or(_T_9563, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9565 = bits(_T_9564, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_4_13 = mux(_T_9565, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9566 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9567 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9568 = eq(_T_9567, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_9569 = and(_T_9566, _T_9568) @[ifu_bp_ctl.scala 434:23] - node _T_9570 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9571 = eq(_T_9570, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_9572 = and(_T_9569, _T_9571) @[ifu_bp_ctl.scala 434:81] - node _T_9573 = or(_T_9572, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9574 = bits(_T_9573, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_4_14 = mux(_T_9574, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9575 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9576 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9577 = eq(_T_9576, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_9578 = and(_T_9575, _T_9577) @[ifu_bp_ctl.scala 434:23] - node _T_9579 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9580 = eq(_T_9579, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:154] - node _T_9581 = and(_T_9578, _T_9580) @[ifu_bp_ctl.scala 434:81] - node _T_9582 = or(_T_9581, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9583 = bits(_T_9582, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_4_15 = mux(_T_9583, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9584 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9585 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9586 = eq(_T_9585, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_9587 = and(_T_9584, _T_9586) @[ifu_bp_ctl.scala 434:23] - node _T_9588 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9589 = eq(_T_9588, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_9590 = and(_T_9587, _T_9589) @[ifu_bp_ctl.scala 434:81] - node _T_9591 = or(_T_9590, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9592 = bits(_T_9591, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_5_0 = mux(_T_9592, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9593 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9594 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9595 = eq(_T_9594, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_9596 = and(_T_9593, _T_9595) @[ifu_bp_ctl.scala 434:23] - node _T_9597 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9598 = eq(_T_9597, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_9599 = and(_T_9596, _T_9598) @[ifu_bp_ctl.scala 434:81] - node _T_9600 = or(_T_9599, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9601 = bits(_T_9600, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_5_1 = mux(_T_9601, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9602 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9603 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9604 = eq(_T_9603, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_9605 = and(_T_9602, _T_9604) @[ifu_bp_ctl.scala 434:23] - node _T_9606 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9607 = eq(_T_9606, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_9608 = and(_T_9605, _T_9607) @[ifu_bp_ctl.scala 434:81] - node _T_9609 = or(_T_9608, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9610 = bits(_T_9609, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_5_2 = mux(_T_9610, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9611 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9612 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9613 = eq(_T_9612, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_9614 = and(_T_9611, _T_9613) @[ifu_bp_ctl.scala 434:23] - node _T_9615 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9616 = eq(_T_9615, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_9617 = and(_T_9614, _T_9616) @[ifu_bp_ctl.scala 434:81] - node _T_9618 = or(_T_9617, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9619 = bits(_T_9618, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_5_3 = mux(_T_9619, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9620 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9621 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9622 = eq(_T_9621, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_9623 = and(_T_9620, _T_9622) @[ifu_bp_ctl.scala 434:23] - node _T_9624 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9625 = eq(_T_9624, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_9626 = and(_T_9623, _T_9625) @[ifu_bp_ctl.scala 434:81] - node _T_9627 = or(_T_9626, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9628 = bits(_T_9627, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_5_4 = mux(_T_9628, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9629 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9630 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9631 = eq(_T_9630, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_9632 = and(_T_9629, _T_9631) @[ifu_bp_ctl.scala 434:23] - node _T_9633 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9634 = eq(_T_9633, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_9635 = and(_T_9632, _T_9634) @[ifu_bp_ctl.scala 434:81] - node _T_9636 = or(_T_9635, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9637 = bits(_T_9636, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_5_5 = mux(_T_9637, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9638 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9639 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9640 = eq(_T_9639, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_9641 = and(_T_9638, _T_9640) @[ifu_bp_ctl.scala 434:23] - node _T_9642 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9643 = eq(_T_9642, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_9644 = and(_T_9641, _T_9643) @[ifu_bp_ctl.scala 434:81] - node _T_9645 = or(_T_9644, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9646 = bits(_T_9645, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_5_6 = mux(_T_9646, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9647 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9648 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9649 = eq(_T_9648, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_9650 = and(_T_9647, _T_9649) @[ifu_bp_ctl.scala 434:23] - node _T_9651 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9652 = eq(_T_9651, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_9653 = and(_T_9650, _T_9652) @[ifu_bp_ctl.scala 434:81] - node _T_9654 = or(_T_9653, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9655 = bits(_T_9654, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_5_7 = mux(_T_9655, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9656 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9657 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9658 = eq(_T_9657, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_9659 = and(_T_9656, _T_9658) @[ifu_bp_ctl.scala 434:23] - node _T_9660 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9661 = eq(_T_9660, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_9662 = and(_T_9659, _T_9661) @[ifu_bp_ctl.scala 434:81] - node _T_9663 = or(_T_9662, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9664 = bits(_T_9663, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_5_8 = mux(_T_9664, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9665 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9666 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9667 = eq(_T_9666, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_9668 = and(_T_9665, _T_9667) @[ifu_bp_ctl.scala 434:23] - node _T_9669 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9670 = eq(_T_9669, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_9671 = and(_T_9668, _T_9670) @[ifu_bp_ctl.scala 434:81] - node _T_9672 = or(_T_9671, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9673 = bits(_T_9672, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_5_9 = mux(_T_9673, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9674 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9675 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9676 = eq(_T_9675, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_9677 = and(_T_9674, _T_9676) @[ifu_bp_ctl.scala 434:23] - node _T_9678 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9679 = eq(_T_9678, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_9680 = and(_T_9677, _T_9679) @[ifu_bp_ctl.scala 434:81] - node _T_9681 = or(_T_9680, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9682 = bits(_T_9681, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_5_10 = mux(_T_9682, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9683 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9684 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9685 = eq(_T_9684, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_9686 = and(_T_9683, _T_9685) @[ifu_bp_ctl.scala 434:23] - node _T_9687 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9688 = eq(_T_9687, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_9689 = and(_T_9686, _T_9688) @[ifu_bp_ctl.scala 434:81] - node _T_9690 = or(_T_9689, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9691 = bits(_T_9690, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_5_11 = mux(_T_9691, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9692 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9693 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9694 = eq(_T_9693, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_9695 = and(_T_9692, _T_9694) @[ifu_bp_ctl.scala 434:23] - node _T_9696 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9697 = eq(_T_9696, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_9698 = and(_T_9695, _T_9697) @[ifu_bp_ctl.scala 434:81] - node _T_9699 = or(_T_9698, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9700 = bits(_T_9699, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_5_12 = mux(_T_9700, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9701 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9702 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9703 = eq(_T_9702, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_9704 = and(_T_9701, _T_9703) @[ifu_bp_ctl.scala 434:23] - node _T_9705 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9706 = eq(_T_9705, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_9707 = and(_T_9704, _T_9706) @[ifu_bp_ctl.scala 434:81] - node _T_9708 = or(_T_9707, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9709 = bits(_T_9708, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_5_13 = mux(_T_9709, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9710 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9711 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9712 = eq(_T_9711, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_9713 = and(_T_9710, _T_9712) @[ifu_bp_ctl.scala 434:23] - node _T_9714 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9715 = eq(_T_9714, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_9716 = and(_T_9713, _T_9715) @[ifu_bp_ctl.scala 434:81] - node _T_9717 = or(_T_9716, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9718 = bits(_T_9717, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_5_14 = mux(_T_9718, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9719 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9720 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9721 = eq(_T_9720, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_9722 = and(_T_9719, _T_9721) @[ifu_bp_ctl.scala 434:23] - node _T_9723 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9724 = eq(_T_9723, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:154] - node _T_9725 = and(_T_9722, _T_9724) @[ifu_bp_ctl.scala 434:81] - node _T_9726 = or(_T_9725, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9727 = bits(_T_9726, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_5_15 = mux(_T_9727, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9728 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9729 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9730 = eq(_T_9729, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_9731 = and(_T_9728, _T_9730) @[ifu_bp_ctl.scala 434:23] - node _T_9732 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9733 = eq(_T_9732, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_9734 = and(_T_9731, _T_9733) @[ifu_bp_ctl.scala 434:81] - node _T_9735 = or(_T_9734, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9736 = bits(_T_9735, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_6_0 = mux(_T_9736, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9737 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9738 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9739 = eq(_T_9738, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_9740 = and(_T_9737, _T_9739) @[ifu_bp_ctl.scala 434:23] - node _T_9741 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9742 = eq(_T_9741, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_9743 = and(_T_9740, _T_9742) @[ifu_bp_ctl.scala 434:81] - node _T_9744 = or(_T_9743, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9745 = bits(_T_9744, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_6_1 = mux(_T_9745, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9746 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9747 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9748 = eq(_T_9747, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_9749 = and(_T_9746, _T_9748) @[ifu_bp_ctl.scala 434:23] - node _T_9750 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9751 = eq(_T_9750, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_9752 = and(_T_9749, _T_9751) @[ifu_bp_ctl.scala 434:81] - node _T_9753 = or(_T_9752, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9754 = bits(_T_9753, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_6_2 = mux(_T_9754, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9755 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9756 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9757 = eq(_T_9756, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_9758 = and(_T_9755, _T_9757) @[ifu_bp_ctl.scala 434:23] - node _T_9759 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9760 = eq(_T_9759, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_9761 = and(_T_9758, _T_9760) @[ifu_bp_ctl.scala 434:81] - node _T_9762 = or(_T_9761, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9763 = bits(_T_9762, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_6_3 = mux(_T_9763, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9764 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9765 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9766 = eq(_T_9765, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_9767 = and(_T_9764, _T_9766) @[ifu_bp_ctl.scala 434:23] - node _T_9768 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9769 = eq(_T_9768, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_9770 = and(_T_9767, _T_9769) @[ifu_bp_ctl.scala 434:81] - node _T_9771 = or(_T_9770, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9772 = bits(_T_9771, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_6_4 = mux(_T_9772, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9773 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9774 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9775 = eq(_T_9774, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_9776 = and(_T_9773, _T_9775) @[ifu_bp_ctl.scala 434:23] - node _T_9777 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9778 = eq(_T_9777, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_9779 = and(_T_9776, _T_9778) @[ifu_bp_ctl.scala 434:81] - node _T_9780 = or(_T_9779, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9781 = bits(_T_9780, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_6_5 = mux(_T_9781, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9782 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9783 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9784 = eq(_T_9783, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_9785 = and(_T_9782, _T_9784) @[ifu_bp_ctl.scala 434:23] - node _T_9786 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9787 = eq(_T_9786, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_9788 = and(_T_9785, _T_9787) @[ifu_bp_ctl.scala 434:81] - node _T_9789 = or(_T_9788, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9790 = bits(_T_9789, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_6_6 = mux(_T_9790, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9791 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9792 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9793 = eq(_T_9792, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_9794 = and(_T_9791, _T_9793) @[ifu_bp_ctl.scala 434:23] - node _T_9795 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9796 = eq(_T_9795, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_9797 = and(_T_9794, _T_9796) @[ifu_bp_ctl.scala 434:81] - node _T_9798 = or(_T_9797, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9799 = bits(_T_9798, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_6_7 = mux(_T_9799, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9800 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9801 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9802 = eq(_T_9801, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_9803 = and(_T_9800, _T_9802) @[ifu_bp_ctl.scala 434:23] - node _T_9804 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9805 = eq(_T_9804, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_9806 = and(_T_9803, _T_9805) @[ifu_bp_ctl.scala 434:81] - node _T_9807 = or(_T_9806, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9808 = bits(_T_9807, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_6_8 = mux(_T_9808, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9809 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9810 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9811 = eq(_T_9810, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_9812 = and(_T_9809, _T_9811) @[ifu_bp_ctl.scala 434:23] - node _T_9813 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9814 = eq(_T_9813, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_9815 = and(_T_9812, _T_9814) @[ifu_bp_ctl.scala 434:81] - node _T_9816 = or(_T_9815, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9817 = bits(_T_9816, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_6_9 = mux(_T_9817, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9818 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9819 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9820 = eq(_T_9819, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_9821 = and(_T_9818, _T_9820) @[ifu_bp_ctl.scala 434:23] - node _T_9822 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9823 = eq(_T_9822, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_9824 = and(_T_9821, _T_9823) @[ifu_bp_ctl.scala 434:81] - node _T_9825 = or(_T_9824, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9826 = bits(_T_9825, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_6_10 = mux(_T_9826, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9827 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9828 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9829 = eq(_T_9828, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_9830 = and(_T_9827, _T_9829) @[ifu_bp_ctl.scala 434:23] - node _T_9831 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9832 = eq(_T_9831, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_9833 = and(_T_9830, _T_9832) @[ifu_bp_ctl.scala 434:81] - node _T_9834 = or(_T_9833, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9835 = bits(_T_9834, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_6_11 = mux(_T_9835, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9836 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9837 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9838 = eq(_T_9837, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_9839 = and(_T_9836, _T_9838) @[ifu_bp_ctl.scala 434:23] - node _T_9840 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9841 = eq(_T_9840, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_9842 = and(_T_9839, _T_9841) @[ifu_bp_ctl.scala 434:81] - node _T_9843 = or(_T_9842, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9844 = bits(_T_9843, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_6_12 = mux(_T_9844, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9845 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9846 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9847 = eq(_T_9846, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_9848 = and(_T_9845, _T_9847) @[ifu_bp_ctl.scala 434:23] - node _T_9849 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9850 = eq(_T_9849, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_9851 = and(_T_9848, _T_9850) @[ifu_bp_ctl.scala 434:81] - node _T_9852 = or(_T_9851, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9853 = bits(_T_9852, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_6_13 = mux(_T_9853, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9854 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9855 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9856 = eq(_T_9855, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_9857 = and(_T_9854, _T_9856) @[ifu_bp_ctl.scala 434:23] - node _T_9858 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9859 = eq(_T_9858, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_9860 = and(_T_9857, _T_9859) @[ifu_bp_ctl.scala 434:81] - node _T_9861 = or(_T_9860, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9862 = bits(_T_9861, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_6_14 = mux(_T_9862, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9863 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9864 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9865 = eq(_T_9864, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_9866 = and(_T_9863, _T_9865) @[ifu_bp_ctl.scala 434:23] - node _T_9867 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9868 = eq(_T_9867, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:154] - node _T_9869 = and(_T_9866, _T_9868) @[ifu_bp_ctl.scala 434:81] - node _T_9870 = or(_T_9869, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9871 = bits(_T_9870, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_6_15 = mux(_T_9871, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9872 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9873 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9874 = eq(_T_9873, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_9875 = and(_T_9872, _T_9874) @[ifu_bp_ctl.scala 434:23] - node _T_9876 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9877 = eq(_T_9876, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_9878 = and(_T_9875, _T_9877) @[ifu_bp_ctl.scala 434:81] - node _T_9879 = or(_T_9878, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9880 = bits(_T_9879, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_7_0 = mux(_T_9880, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9881 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9882 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9883 = eq(_T_9882, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_9884 = and(_T_9881, _T_9883) @[ifu_bp_ctl.scala 434:23] - node _T_9885 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9886 = eq(_T_9885, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_9887 = and(_T_9884, _T_9886) @[ifu_bp_ctl.scala 434:81] - node _T_9888 = or(_T_9887, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9889 = bits(_T_9888, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_7_1 = mux(_T_9889, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9890 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9891 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9892 = eq(_T_9891, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_9893 = and(_T_9890, _T_9892) @[ifu_bp_ctl.scala 434:23] - node _T_9894 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9895 = eq(_T_9894, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_9896 = and(_T_9893, _T_9895) @[ifu_bp_ctl.scala 434:81] - node _T_9897 = or(_T_9896, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9898 = bits(_T_9897, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_7_2 = mux(_T_9898, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9899 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9900 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9901 = eq(_T_9900, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_9902 = and(_T_9899, _T_9901) @[ifu_bp_ctl.scala 434:23] - node _T_9903 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9904 = eq(_T_9903, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_9905 = and(_T_9902, _T_9904) @[ifu_bp_ctl.scala 434:81] - node _T_9906 = or(_T_9905, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9907 = bits(_T_9906, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_7_3 = mux(_T_9907, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9908 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9909 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9910 = eq(_T_9909, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_9911 = and(_T_9908, _T_9910) @[ifu_bp_ctl.scala 434:23] - node _T_9912 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9913 = eq(_T_9912, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_9914 = and(_T_9911, _T_9913) @[ifu_bp_ctl.scala 434:81] - node _T_9915 = or(_T_9914, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9916 = bits(_T_9915, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_7_4 = mux(_T_9916, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9917 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9918 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9919 = eq(_T_9918, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_9920 = and(_T_9917, _T_9919) @[ifu_bp_ctl.scala 434:23] - node _T_9921 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9922 = eq(_T_9921, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_9923 = and(_T_9920, _T_9922) @[ifu_bp_ctl.scala 434:81] - node _T_9924 = or(_T_9923, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9925 = bits(_T_9924, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_7_5 = mux(_T_9925, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9926 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9927 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9928 = eq(_T_9927, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_9929 = and(_T_9926, _T_9928) @[ifu_bp_ctl.scala 434:23] - node _T_9930 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9931 = eq(_T_9930, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_9932 = and(_T_9929, _T_9931) @[ifu_bp_ctl.scala 434:81] - node _T_9933 = or(_T_9932, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9934 = bits(_T_9933, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_7_6 = mux(_T_9934, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9935 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9936 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9937 = eq(_T_9936, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_9938 = and(_T_9935, _T_9937) @[ifu_bp_ctl.scala 434:23] - node _T_9939 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9940 = eq(_T_9939, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_9941 = and(_T_9938, _T_9940) @[ifu_bp_ctl.scala 434:81] - node _T_9942 = or(_T_9941, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9943 = bits(_T_9942, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_7_7 = mux(_T_9943, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9944 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9945 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9946 = eq(_T_9945, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_9947 = and(_T_9944, _T_9946) @[ifu_bp_ctl.scala 434:23] - node _T_9948 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9949 = eq(_T_9948, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_9950 = and(_T_9947, _T_9949) @[ifu_bp_ctl.scala 434:81] - node _T_9951 = or(_T_9950, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9952 = bits(_T_9951, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_7_8 = mux(_T_9952, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9953 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9954 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9955 = eq(_T_9954, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_9956 = and(_T_9953, _T_9955) @[ifu_bp_ctl.scala 434:23] - node _T_9957 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9958 = eq(_T_9957, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_9959 = and(_T_9956, _T_9958) @[ifu_bp_ctl.scala 434:81] - node _T_9960 = or(_T_9959, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9961 = bits(_T_9960, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_7_9 = mux(_T_9961, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9962 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9963 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9964 = eq(_T_9963, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_9965 = and(_T_9962, _T_9964) @[ifu_bp_ctl.scala 434:23] - node _T_9966 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9967 = eq(_T_9966, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_9968 = and(_T_9965, _T_9967) @[ifu_bp_ctl.scala 434:81] - node _T_9969 = or(_T_9968, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9970 = bits(_T_9969, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_7_10 = mux(_T_9970, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9971 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9972 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9973 = eq(_T_9972, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_9974 = and(_T_9971, _T_9973) @[ifu_bp_ctl.scala 434:23] - node _T_9975 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9976 = eq(_T_9975, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_9977 = and(_T_9974, _T_9976) @[ifu_bp_ctl.scala 434:81] - node _T_9978 = or(_T_9977, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9979 = bits(_T_9978, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_7_11 = mux(_T_9979, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9980 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9981 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9982 = eq(_T_9981, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_9983 = and(_T_9980, _T_9982) @[ifu_bp_ctl.scala 434:23] - node _T_9984 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9985 = eq(_T_9984, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_9986 = and(_T_9983, _T_9985) @[ifu_bp_ctl.scala 434:81] - node _T_9987 = or(_T_9986, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9988 = bits(_T_9987, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_7_12 = mux(_T_9988, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9989 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9990 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_9991 = eq(_T_9990, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_9992 = and(_T_9989, _T_9991) @[ifu_bp_ctl.scala 434:23] - node _T_9993 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_9994 = eq(_T_9993, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_9995 = and(_T_9992, _T_9994) @[ifu_bp_ctl.scala 434:81] - node _T_9996 = or(_T_9995, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_9997 = bits(_T_9996, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_7_13 = mux(_T_9997, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_9998 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_9999 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10000 = eq(_T_9999, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_10001 = and(_T_9998, _T_10000) @[ifu_bp_ctl.scala 434:23] - node _T_10002 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10003 = eq(_T_10002, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_10004 = and(_T_10001, _T_10003) @[ifu_bp_ctl.scala 434:81] - node _T_10005 = or(_T_10004, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10006 = bits(_T_10005, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_7_14 = mux(_T_10006, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10007 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10008 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10009 = eq(_T_10008, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_10010 = and(_T_10007, _T_10009) @[ifu_bp_ctl.scala 434:23] - node _T_10011 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10012 = eq(_T_10011, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:154] - node _T_10013 = and(_T_10010, _T_10012) @[ifu_bp_ctl.scala 434:81] - node _T_10014 = or(_T_10013, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10015 = bits(_T_10014, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_7_15 = mux(_T_10015, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10016 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10017 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10018 = eq(_T_10017, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_10019 = and(_T_10016, _T_10018) @[ifu_bp_ctl.scala 434:23] - node _T_10020 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10021 = eq(_T_10020, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_10022 = and(_T_10019, _T_10021) @[ifu_bp_ctl.scala 434:81] - node _T_10023 = or(_T_10022, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10024 = bits(_T_10023, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_8_0 = mux(_T_10024, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10025 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10026 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10027 = eq(_T_10026, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_10028 = and(_T_10025, _T_10027) @[ifu_bp_ctl.scala 434:23] - node _T_10029 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10030 = eq(_T_10029, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_10031 = and(_T_10028, _T_10030) @[ifu_bp_ctl.scala 434:81] - node _T_10032 = or(_T_10031, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10033 = bits(_T_10032, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_8_1 = mux(_T_10033, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10034 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10035 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10036 = eq(_T_10035, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_10037 = and(_T_10034, _T_10036) @[ifu_bp_ctl.scala 434:23] - node _T_10038 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10039 = eq(_T_10038, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_10040 = and(_T_10037, _T_10039) @[ifu_bp_ctl.scala 434:81] - node _T_10041 = or(_T_10040, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10042 = bits(_T_10041, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_8_2 = mux(_T_10042, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10043 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10044 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10045 = eq(_T_10044, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_10046 = and(_T_10043, _T_10045) @[ifu_bp_ctl.scala 434:23] - node _T_10047 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10048 = eq(_T_10047, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_10049 = and(_T_10046, _T_10048) @[ifu_bp_ctl.scala 434:81] - node _T_10050 = or(_T_10049, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10051 = bits(_T_10050, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_8_3 = mux(_T_10051, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10052 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10053 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10054 = eq(_T_10053, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_10055 = and(_T_10052, _T_10054) @[ifu_bp_ctl.scala 434:23] - node _T_10056 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10057 = eq(_T_10056, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_10058 = and(_T_10055, _T_10057) @[ifu_bp_ctl.scala 434:81] - node _T_10059 = or(_T_10058, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10060 = bits(_T_10059, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_8_4 = mux(_T_10060, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10061 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10062 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10063 = eq(_T_10062, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_10064 = and(_T_10061, _T_10063) @[ifu_bp_ctl.scala 434:23] - node _T_10065 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10066 = eq(_T_10065, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_10067 = and(_T_10064, _T_10066) @[ifu_bp_ctl.scala 434:81] - node _T_10068 = or(_T_10067, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10069 = bits(_T_10068, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_8_5 = mux(_T_10069, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10070 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10071 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10072 = eq(_T_10071, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_10073 = and(_T_10070, _T_10072) @[ifu_bp_ctl.scala 434:23] - node _T_10074 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10075 = eq(_T_10074, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_10076 = and(_T_10073, _T_10075) @[ifu_bp_ctl.scala 434:81] - node _T_10077 = or(_T_10076, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10078 = bits(_T_10077, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_8_6 = mux(_T_10078, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10079 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10080 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10081 = eq(_T_10080, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_10082 = and(_T_10079, _T_10081) @[ifu_bp_ctl.scala 434:23] - node _T_10083 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10084 = eq(_T_10083, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_10085 = and(_T_10082, _T_10084) @[ifu_bp_ctl.scala 434:81] - node _T_10086 = or(_T_10085, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10087 = bits(_T_10086, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_8_7 = mux(_T_10087, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10088 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10089 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10090 = eq(_T_10089, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_10091 = and(_T_10088, _T_10090) @[ifu_bp_ctl.scala 434:23] - node _T_10092 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10093 = eq(_T_10092, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_10094 = and(_T_10091, _T_10093) @[ifu_bp_ctl.scala 434:81] - node _T_10095 = or(_T_10094, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10096 = bits(_T_10095, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_8_8 = mux(_T_10096, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10097 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10098 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10099 = eq(_T_10098, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_10100 = and(_T_10097, _T_10099) @[ifu_bp_ctl.scala 434:23] - node _T_10101 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10102 = eq(_T_10101, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_10103 = and(_T_10100, _T_10102) @[ifu_bp_ctl.scala 434:81] - node _T_10104 = or(_T_10103, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10105 = bits(_T_10104, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_8_9 = mux(_T_10105, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10106 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10107 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10108 = eq(_T_10107, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_10109 = and(_T_10106, _T_10108) @[ifu_bp_ctl.scala 434:23] - node _T_10110 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10111 = eq(_T_10110, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_10112 = and(_T_10109, _T_10111) @[ifu_bp_ctl.scala 434:81] - node _T_10113 = or(_T_10112, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10114 = bits(_T_10113, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_8_10 = mux(_T_10114, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10115 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10116 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10117 = eq(_T_10116, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_10118 = and(_T_10115, _T_10117) @[ifu_bp_ctl.scala 434:23] - node _T_10119 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10120 = eq(_T_10119, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_10121 = and(_T_10118, _T_10120) @[ifu_bp_ctl.scala 434:81] - node _T_10122 = or(_T_10121, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10123 = bits(_T_10122, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_8_11 = mux(_T_10123, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10124 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10125 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10126 = eq(_T_10125, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_10127 = and(_T_10124, _T_10126) @[ifu_bp_ctl.scala 434:23] - node _T_10128 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10129 = eq(_T_10128, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_10130 = and(_T_10127, _T_10129) @[ifu_bp_ctl.scala 434:81] - node _T_10131 = or(_T_10130, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10132 = bits(_T_10131, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_8_12 = mux(_T_10132, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10133 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10134 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10135 = eq(_T_10134, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_10136 = and(_T_10133, _T_10135) @[ifu_bp_ctl.scala 434:23] - node _T_10137 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10138 = eq(_T_10137, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_10139 = and(_T_10136, _T_10138) @[ifu_bp_ctl.scala 434:81] - node _T_10140 = or(_T_10139, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10141 = bits(_T_10140, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_8_13 = mux(_T_10141, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10142 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10143 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10144 = eq(_T_10143, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_10145 = and(_T_10142, _T_10144) @[ifu_bp_ctl.scala 434:23] - node _T_10146 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10147 = eq(_T_10146, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_10148 = and(_T_10145, _T_10147) @[ifu_bp_ctl.scala 434:81] - node _T_10149 = or(_T_10148, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10150 = bits(_T_10149, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_8_14 = mux(_T_10150, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10151 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10152 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10153 = eq(_T_10152, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_10154 = and(_T_10151, _T_10153) @[ifu_bp_ctl.scala 434:23] - node _T_10155 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10156 = eq(_T_10155, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:154] - node _T_10157 = and(_T_10154, _T_10156) @[ifu_bp_ctl.scala 434:81] - node _T_10158 = or(_T_10157, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10159 = bits(_T_10158, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_8_15 = mux(_T_10159, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10160 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10161 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10162 = eq(_T_10161, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_10163 = and(_T_10160, _T_10162) @[ifu_bp_ctl.scala 434:23] - node _T_10164 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10165 = eq(_T_10164, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_10166 = and(_T_10163, _T_10165) @[ifu_bp_ctl.scala 434:81] - node _T_10167 = or(_T_10166, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10168 = bits(_T_10167, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_9_0 = mux(_T_10168, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10169 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10170 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10171 = eq(_T_10170, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_10172 = and(_T_10169, _T_10171) @[ifu_bp_ctl.scala 434:23] - node _T_10173 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10174 = eq(_T_10173, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_10175 = and(_T_10172, _T_10174) @[ifu_bp_ctl.scala 434:81] - node _T_10176 = or(_T_10175, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10177 = bits(_T_10176, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_9_1 = mux(_T_10177, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10178 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10179 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10180 = eq(_T_10179, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_10181 = and(_T_10178, _T_10180) @[ifu_bp_ctl.scala 434:23] - node _T_10182 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10183 = eq(_T_10182, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_10184 = and(_T_10181, _T_10183) @[ifu_bp_ctl.scala 434:81] - node _T_10185 = or(_T_10184, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10186 = bits(_T_10185, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_9_2 = mux(_T_10186, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10187 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10188 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10189 = eq(_T_10188, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_10190 = and(_T_10187, _T_10189) @[ifu_bp_ctl.scala 434:23] - node _T_10191 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10192 = eq(_T_10191, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_10193 = and(_T_10190, _T_10192) @[ifu_bp_ctl.scala 434:81] - node _T_10194 = or(_T_10193, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10195 = bits(_T_10194, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_9_3 = mux(_T_10195, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10196 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10197 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10198 = eq(_T_10197, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_10199 = and(_T_10196, _T_10198) @[ifu_bp_ctl.scala 434:23] - node _T_10200 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10201 = eq(_T_10200, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_10202 = and(_T_10199, _T_10201) @[ifu_bp_ctl.scala 434:81] - node _T_10203 = or(_T_10202, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10204 = bits(_T_10203, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_9_4 = mux(_T_10204, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10205 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10206 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10207 = eq(_T_10206, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_10208 = and(_T_10205, _T_10207) @[ifu_bp_ctl.scala 434:23] - node _T_10209 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10210 = eq(_T_10209, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_10211 = and(_T_10208, _T_10210) @[ifu_bp_ctl.scala 434:81] - node _T_10212 = or(_T_10211, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10213 = bits(_T_10212, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_9_5 = mux(_T_10213, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10214 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10215 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10216 = eq(_T_10215, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_10217 = and(_T_10214, _T_10216) @[ifu_bp_ctl.scala 434:23] - node _T_10218 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10219 = eq(_T_10218, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_10220 = and(_T_10217, _T_10219) @[ifu_bp_ctl.scala 434:81] - node _T_10221 = or(_T_10220, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10222 = bits(_T_10221, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_9_6 = mux(_T_10222, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10223 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10224 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10225 = eq(_T_10224, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_10226 = and(_T_10223, _T_10225) @[ifu_bp_ctl.scala 434:23] - node _T_10227 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10228 = eq(_T_10227, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_10229 = and(_T_10226, _T_10228) @[ifu_bp_ctl.scala 434:81] - node _T_10230 = or(_T_10229, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10231 = bits(_T_10230, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_9_7 = mux(_T_10231, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10232 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10233 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10234 = eq(_T_10233, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_10235 = and(_T_10232, _T_10234) @[ifu_bp_ctl.scala 434:23] - node _T_10236 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10237 = eq(_T_10236, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_10238 = and(_T_10235, _T_10237) @[ifu_bp_ctl.scala 434:81] - node _T_10239 = or(_T_10238, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10240 = bits(_T_10239, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_9_8 = mux(_T_10240, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10241 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10242 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10243 = eq(_T_10242, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_10244 = and(_T_10241, _T_10243) @[ifu_bp_ctl.scala 434:23] - node _T_10245 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10246 = eq(_T_10245, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_10247 = and(_T_10244, _T_10246) @[ifu_bp_ctl.scala 434:81] - node _T_10248 = or(_T_10247, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10249 = bits(_T_10248, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_9_9 = mux(_T_10249, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10250 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10251 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10252 = eq(_T_10251, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_10253 = and(_T_10250, _T_10252) @[ifu_bp_ctl.scala 434:23] - node _T_10254 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10255 = eq(_T_10254, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_10256 = and(_T_10253, _T_10255) @[ifu_bp_ctl.scala 434:81] - node _T_10257 = or(_T_10256, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10258 = bits(_T_10257, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_9_10 = mux(_T_10258, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10259 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10260 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10261 = eq(_T_10260, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_10262 = and(_T_10259, _T_10261) @[ifu_bp_ctl.scala 434:23] - node _T_10263 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10264 = eq(_T_10263, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_10265 = and(_T_10262, _T_10264) @[ifu_bp_ctl.scala 434:81] - node _T_10266 = or(_T_10265, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10267 = bits(_T_10266, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_9_11 = mux(_T_10267, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10268 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10269 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10270 = eq(_T_10269, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_10271 = and(_T_10268, _T_10270) @[ifu_bp_ctl.scala 434:23] - node _T_10272 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10273 = eq(_T_10272, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_10274 = and(_T_10271, _T_10273) @[ifu_bp_ctl.scala 434:81] - node _T_10275 = or(_T_10274, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10276 = bits(_T_10275, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_9_12 = mux(_T_10276, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10277 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10278 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10279 = eq(_T_10278, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_10280 = and(_T_10277, _T_10279) @[ifu_bp_ctl.scala 434:23] - node _T_10281 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10282 = eq(_T_10281, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_10283 = and(_T_10280, _T_10282) @[ifu_bp_ctl.scala 434:81] - node _T_10284 = or(_T_10283, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10285 = bits(_T_10284, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_9_13 = mux(_T_10285, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10286 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10287 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10288 = eq(_T_10287, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_10289 = and(_T_10286, _T_10288) @[ifu_bp_ctl.scala 434:23] - node _T_10290 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10291 = eq(_T_10290, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_10292 = and(_T_10289, _T_10291) @[ifu_bp_ctl.scala 434:81] - node _T_10293 = or(_T_10292, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10294 = bits(_T_10293, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_9_14 = mux(_T_10294, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10295 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10296 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10297 = eq(_T_10296, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_10298 = and(_T_10295, _T_10297) @[ifu_bp_ctl.scala 434:23] - node _T_10299 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10300 = eq(_T_10299, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:154] - node _T_10301 = and(_T_10298, _T_10300) @[ifu_bp_ctl.scala 434:81] - node _T_10302 = or(_T_10301, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10303 = bits(_T_10302, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_9_15 = mux(_T_10303, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10304 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10305 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10306 = eq(_T_10305, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_10307 = and(_T_10304, _T_10306) @[ifu_bp_ctl.scala 434:23] - node _T_10308 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10309 = eq(_T_10308, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_10310 = and(_T_10307, _T_10309) @[ifu_bp_ctl.scala 434:81] - node _T_10311 = or(_T_10310, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10312 = bits(_T_10311, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_10_0 = mux(_T_10312, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10313 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10314 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10315 = eq(_T_10314, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_10316 = and(_T_10313, _T_10315) @[ifu_bp_ctl.scala 434:23] - node _T_10317 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10318 = eq(_T_10317, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_10319 = and(_T_10316, _T_10318) @[ifu_bp_ctl.scala 434:81] - node _T_10320 = or(_T_10319, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10321 = bits(_T_10320, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_10_1 = mux(_T_10321, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10322 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10323 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10324 = eq(_T_10323, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_10325 = and(_T_10322, _T_10324) @[ifu_bp_ctl.scala 434:23] - node _T_10326 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10327 = eq(_T_10326, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_10328 = and(_T_10325, _T_10327) @[ifu_bp_ctl.scala 434:81] - node _T_10329 = or(_T_10328, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10330 = bits(_T_10329, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_10_2 = mux(_T_10330, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10331 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10332 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10333 = eq(_T_10332, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_10334 = and(_T_10331, _T_10333) @[ifu_bp_ctl.scala 434:23] - node _T_10335 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10336 = eq(_T_10335, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_10337 = and(_T_10334, _T_10336) @[ifu_bp_ctl.scala 434:81] - node _T_10338 = or(_T_10337, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10339 = bits(_T_10338, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_10_3 = mux(_T_10339, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10340 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10341 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10342 = eq(_T_10341, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_10343 = and(_T_10340, _T_10342) @[ifu_bp_ctl.scala 434:23] - node _T_10344 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10345 = eq(_T_10344, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_10346 = and(_T_10343, _T_10345) @[ifu_bp_ctl.scala 434:81] - node _T_10347 = or(_T_10346, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10348 = bits(_T_10347, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_10_4 = mux(_T_10348, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10349 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10350 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10351 = eq(_T_10350, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_10352 = and(_T_10349, _T_10351) @[ifu_bp_ctl.scala 434:23] - node _T_10353 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10354 = eq(_T_10353, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_10355 = and(_T_10352, _T_10354) @[ifu_bp_ctl.scala 434:81] - node _T_10356 = or(_T_10355, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10357 = bits(_T_10356, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_10_5 = mux(_T_10357, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10358 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10359 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10360 = eq(_T_10359, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_10361 = and(_T_10358, _T_10360) @[ifu_bp_ctl.scala 434:23] - node _T_10362 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10363 = eq(_T_10362, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_10364 = and(_T_10361, _T_10363) @[ifu_bp_ctl.scala 434:81] - node _T_10365 = or(_T_10364, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10366 = bits(_T_10365, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_10_6 = mux(_T_10366, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10367 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10368 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10369 = eq(_T_10368, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_10370 = and(_T_10367, _T_10369) @[ifu_bp_ctl.scala 434:23] - node _T_10371 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10372 = eq(_T_10371, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_10373 = and(_T_10370, _T_10372) @[ifu_bp_ctl.scala 434:81] - node _T_10374 = or(_T_10373, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10375 = bits(_T_10374, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_10_7 = mux(_T_10375, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10376 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10377 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10378 = eq(_T_10377, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_10379 = and(_T_10376, _T_10378) @[ifu_bp_ctl.scala 434:23] - node _T_10380 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10381 = eq(_T_10380, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_10382 = and(_T_10379, _T_10381) @[ifu_bp_ctl.scala 434:81] - node _T_10383 = or(_T_10382, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10384 = bits(_T_10383, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_10_8 = mux(_T_10384, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10385 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10386 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10387 = eq(_T_10386, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_10388 = and(_T_10385, _T_10387) @[ifu_bp_ctl.scala 434:23] - node _T_10389 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10390 = eq(_T_10389, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_10391 = and(_T_10388, _T_10390) @[ifu_bp_ctl.scala 434:81] - node _T_10392 = or(_T_10391, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10393 = bits(_T_10392, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_10_9 = mux(_T_10393, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10394 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10395 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10396 = eq(_T_10395, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_10397 = and(_T_10394, _T_10396) @[ifu_bp_ctl.scala 434:23] - node _T_10398 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10399 = eq(_T_10398, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_10400 = and(_T_10397, _T_10399) @[ifu_bp_ctl.scala 434:81] - node _T_10401 = or(_T_10400, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10402 = bits(_T_10401, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_10_10 = mux(_T_10402, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10403 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10404 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10405 = eq(_T_10404, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_10406 = and(_T_10403, _T_10405) @[ifu_bp_ctl.scala 434:23] - node _T_10407 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10408 = eq(_T_10407, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_10409 = and(_T_10406, _T_10408) @[ifu_bp_ctl.scala 434:81] - node _T_10410 = or(_T_10409, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10411 = bits(_T_10410, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_10_11 = mux(_T_10411, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10412 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10413 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10414 = eq(_T_10413, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_10415 = and(_T_10412, _T_10414) @[ifu_bp_ctl.scala 434:23] - node _T_10416 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10417 = eq(_T_10416, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_10418 = and(_T_10415, _T_10417) @[ifu_bp_ctl.scala 434:81] - node _T_10419 = or(_T_10418, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10420 = bits(_T_10419, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_10_12 = mux(_T_10420, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10421 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10422 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10423 = eq(_T_10422, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_10424 = and(_T_10421, _T_10423) @[ifu_bp_ctl.scala 434:23] - node _T_10425 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10426 = eq(_T_10425, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_10427 = and(_T_10424, _T_10426) @[ifu_bp_ctl.scala 434:81] - node _T_10428 = or(_T_10427, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10429 = bits(_T_10428, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_10_13 = mux(_T_10429, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10430 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10431 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10432 = eq(_T_10431, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_10433 = and(_T_10430, _T_10432) @[ifu_bp_ctl.scala 434:23] - node _T_10434 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10435 = eq(_T_10434, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_10436 = and(_T_10433, _T_10435) @[ifu_bp_ctl.scala 434:81] - node _T_10437 = or(_T_10436, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10438 = bits(_T_10437, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_10_14 = mux(_T_10438, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10439 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10440 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10441 = eq(_T_10440, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_10442 = and(_T_10439, _T_10441) @[ifu_bp_ctl.scala 434:23] - node _T_10443 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10444 = eq(_T_10443, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:154] - node _T_10445 = and(_T_10442, _T_10444) @[ifu_bp_ctl.scala 434:81] - node _T_10446 = or(_T_10445, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10447 = bits(_T_10446, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_10_15 = mux(_T_10447, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10448 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10449 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10450 = eq(_T_10449, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_10451 = and(_T_10448, _T_10450) @[ifu_bp_ctl.scala 434:23] - node _T_10452 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10453 = eq(_T_10452, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_10454 = and(_T_10451, _T_10453) @[ifu_bp_ctl.scala 434:81] - node _T_10455 = or(_T_10454, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10456 = bits(_T_10455, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_11_0 = mux(_T_10456, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10457 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10458 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10459 = eq(_T_10458, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_10460 = and(_T_10457, _T_10459) @[ifu_bp_ctl.scala 434:23] - node _T_10461 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10462 = eq(_T_10461, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_10463 = and(_T_10460, _T_10462) @[ifu_bp_ctl.scala 434:81] - node _T_10464 = or(_T_10463, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10465 = bits(_T_10464, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_11_1 = mux(_T_10465, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10466 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10467 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10468 = eq(_T_10467, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_10469 = and(_T_10466, _T_10468) @[ifu_bp_ctl.scala 434:23] - node _T_10470 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10471 = eq(_T_10470, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_10472 = and(_T_10469, _T_10471) @[ifu_bp_ctl.scala 434:81] - node _T_10473 = or(_T_10472, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10474 = bits(_T_10473, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_11_2 = mux(_T_10474, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10475 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10476 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10477 = eq(_T_10476, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_10478 = and(_T_10475, _T_10477) @[ifu_bp_ctl.scala 434:23] - node _T_10479 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10480 = eq(_T_10479, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_10481 = and(_T_10478, _T_10480) @[ifu_bp_ctl.scala 434:81] - node _T_10482 = or(_T_10481, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10483 = bits(_T_10482, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_11_3 = mux(_T_10483, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10484 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10485 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10486 = eq(_T_10485, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_10487 = and(_T_10484, _T_10486) @[ifu_bp_ctl.scala 434:23] - node _T_10488 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10489 = eq(_T_10488, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_10490 = and(_T_10487, _T_10489) @[ifu_bp_ctl.scala 434:81] - node _T_10491 = or(_T_10490, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10492 = bits(_T_10491, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_11_4 = mux(_T_10492, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10493 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10494 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10495 = eq(_T_10494, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_10496 = and(_T_10493, _T_10495) @[ifu_bp_ctl.scala 434:23] - node _T_10497 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10498 = eq(_T_10497, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_10499 = and(_T_10496, _T_10498) @[ifu_bp_ctl.scala 434:81] - node _T_10500 = or(_T_10499, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10501 = bits(_T_10500, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_11_5 = mux(_T_10501, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10502 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10503 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10504 = eq(_T_10503, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_10505 = and(_T_10502, _T_10504) @[ifu_bp_ctl.scala 434:23] - node _T_10506 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10507 = eq(_T_10506, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_10508 = and(_T_10505, _T_10507) @[ifu_bp_ctl.scala 434:81] - node _T_10509 = or(_T_10508, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10510 = bits(_T_10509, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_11_6 = mux(_T_10510, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10511 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10512 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10513 = eq(_T_10512, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_10514 = and(_T_10511, _T_10513) @[ifu_bp_ctl.scala 434:23] - node _T_10515 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10516 = eq(_T_10515, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_10517 = and(_T_10514, _T_10516) @[ifu_bp_ctl.scala 434:81] - node _T_10518 = or(_T_10517, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10519 = bits(_T_10518, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_11_7 = mux(_T_10519, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10520 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10521 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10522 = eq(_T_10521, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_10523 = and(_T_10520, _T_10522) @[ifu_bp_ctl.scala 434:23] - node _T_10524 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10525 = eq(_T_10524, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_10526 = and(_T_10523, _T_10525) @[ifu_bp_ctl.scala 434:81] - node _T_10527 = or(_T_10526, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10528 = bits(_T_10527, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_11_8 = mux(_T_10528, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10529 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10530 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10531 = eq(_T_10530, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_10532 = and(_T_10529, _T_10531) @[ifu_bp_ctl.scala 434:23] - node _T_10533 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10534 = eq(_T_10533, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_10535 = and(_T_10532, _T_10534) @[ifu_bp_ctl.scala 434:81] - node _T_10536 = or(_T_10535, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10537 = bits(_T_10536, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_11_9 = mux(_T_10537, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10538 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10539 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10540 = eq(_T_10539, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_10541 = and(_T_10538, _T_10540) @[ifu_bp_ctl.scala 434:23] - node _T_10542 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10543 = eq(_T_10542, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_10544 = and(_T_10541, _T_10543) @[ifu_bp_ctl.scala 434:81] - node _T_10545 = or(_T_10544, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10546 = bits(_T_10545, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_11_10 = mux(_T_10546, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10547 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10548 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10549 = eq(_T_10548, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_10550 = and(_T_10547, _T_10549) @[ifu_bp_ctl.scala 434:23] - node _T_10551 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10552 = eq(_T_10551, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_10553 = and(_T_10550, _T_10552) @[ifu_bp_ctl.scala 434:81] - node _T_10554 = or(_T_10553, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10555 = bits(_T_10554, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_11_11 = mux(_T_10555, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10556 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10557 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10558 = eq(_T_10557, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_10559 = and(_T_10556, _T_10558) @[ifu_bp_ctl.scala 434:23] - node _T_10560 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10561 = eq(_T_10560, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_10562 = and(_T_10559, _T_10561) @[ifu_bp_ctl.scala 434:81] - node _T_10563 = or(_T_10562, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10564 = bits(_T_10563, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_11_12 = mux(_T_10564, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10565 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10566 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10567 = eq(_T_10566, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_10568 = and(_T_10565, _T_10567) @[ifu_bp_ctl.scala 434:23] - node _T_10569 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10570 = eq(_T_10569, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_10571 = and(_T_10568, _T_10570) @[ifu_bp_ctl.scala 434:81] - node _T_10572 = or(_T_10571, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10573 = bits(_T_10572, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_11_13 = mux(_T_10573, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10574 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10575 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10576 = eq(_T_10575, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_10577 = and(_T_10574, _T_10576) @[ifu_bp_ctl.scala 434:23] - node _T_10578 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10579 = eq(_T_10578, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_10580 = and(_T_10577, _T_10579) @[ifu_bp_ctl.scala 434:81] - node _T_10581 = or(_T_10580, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10582 = bits(_T_10581, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_11_14 = mux(_T_10582, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10583 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10584 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10585 = eq(_T_10584, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_10586 = and(_T_10583, _T_10585) @[ifu_bp_ctl.scala 434:23] - node _T_10587 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10588 = eq(_T_10587, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:154] - node _T_10589 = and(_T_10586, _T_10588) @[ifu_bp_ctl.scala 434:81] - node _T_10590 = or(_T_10589, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10591 = bits(_T_10590, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_11_15 = mux(_T_10591, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10592 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10593 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10594 = eq(_T_10593, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_10595 = and(_T_10592, _T_10594) @[ifu_bp_ctl.scala 434:23] - node _T_10596 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10597 = eq(_T_10596, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_10598 = and(_T_10595, _T_10597) @[ifu_bp_ctl.scala 434:81] - node _T_10599 = or(_T_10598, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10600 = bits(_T_10599, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_12_0 = mux(_T_10600, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10601 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10602 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10603 = eq(_T_10602, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_10604 = and(_T_10601, _T_10603) @[ifu_bp_ctl.scala 434:23] - node _T_10605 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10606 = eq(_T_10605, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_10607 = and(_T_10604, _T_10606) @[ifu_bp_ctl.scala 434:81] - node _T_10608 = or(_T_10607, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10609 = bits(_T_10608, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_12_1 = mux(_T_10609, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10610 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10611 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10612 = eq(_T_10611, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_10613 = and(_T_10610, _T_10612) @[ifu_bp_ctl.scala 434:23] - node _T_10614 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10615 = eq(_T_10614, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_10616 = and(_T_10613, _T_10615) @[ifu_bp_ctl.scala 434:81] - node _T_10617 = or(_T_10616, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10618 = bits(_T_10617, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_12_2 = mux(_T_10618, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10619 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10620 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10621 = eq(_T_10620, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_10622 = and(_T_10619, _T_10621) @[ifu_bp_ctl.scala 434:23] - node _T_10623 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10624 = eq(_T_10623, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_10625 = and(_T_10622, _T_10624) @[ifu_bp_ctl.scala 434:81] - node _T_10626 = or(_T_10625, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10627 = bits(_T_10626, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_12_3 = mux(_T_10627, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10628 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10629 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10630 = eq(_T_10629, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_10631 = and(_T_10628, _T_10630) @[ifu_bp_ctl.scala 434:23] - node _T_10632 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10633 = eq(_T_10632, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_10634 = and(_T_10631, _T_10633) @[ifu_bp_ctl.scala 434:81] - node _T_10635 = or(_T_10634, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10636 = bits(_T_10635, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_12_4 = mux(_T_10636, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10637 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10638 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10639 = eq(_T_10638, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_10640 = and(_T_10637, _T_10639) @[ifu_bp_ctl.scala 434:23] - node _T_10641 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10642 = eq(_T_10641, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_10643 = and(_T_10640, _T_10642) @[ifu_bp_ctl.scala 434:81] - node _T_10644 = or(_T_10643, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10645 = bits(_T_10644, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_12_5 = mux(_T_10645, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10646 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10647 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10648 = eq(_T_10647, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_10649 = and(_T_10646, _T_10648) @[ifu_bp_ctl.scala 434:23] - node _T_10650 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10651 = eq(_T_10650, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_10652 = and(_T_10649, _T_10651) @[ifu_bp_ctl.scala 434:81] - node _T_10653 = or(_T_10652, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10654 = bits(_T_10653, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_12_6 = mux(_T_10654, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10655 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10656 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10657 = eq(_T_10656, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_10658 = and(_T_10655, _T_10657) @[ifu_bp_ctl.scala 434:23] - node _T_10659 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10660 = eq(_T_10659, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_10661 = and(_T_10658, _T_10660) @[ifu_bp_ctl.scala 434:81] - node _T_10662 = or(_T_10661, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10663 = bits(_T_10662, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_12_7 = mux(_T_10663, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10664 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10665 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10666 = eq(_T_10665, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_10667 = and(_T_10664, _T_10666) @[ifu_bp_ctl.scala 434:23] - node _T_10668 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10669 = eq(_T_10668, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_10670 = and(_T_10667, _T_10669) @[ifu_bp_ctl.scala 434:81] - node _T_10671 = or(_T_10670, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10672 = bits(_T_10671, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_12_8 = mux(_T_10672, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10673 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10674 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10675 = eq(_T_10674, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_10676 = and(_T_10673, _T_10675) @[ifu_bp_ctl.scala 434:23] - node _T_10677 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10678 = eq(_T_10677, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_10679 = and(_T_10676, _T_10678) @[ifu_bp_ctl.scala 434:81] - node _T_10680 = or(_T_10679, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10681 = bits(_T_10680, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_12_9 = mux(_T_10681, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10682 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10683 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10684 = eq(_T_10683, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_10685 = and(_T_10682, _T_10684) @[ifu_bp_ctl.scala 434:23] - node _T_10686 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10687 = eq(_T_10686, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_10688 = and(_T_10685, _T_10687) @[ifu_bp_ctl.scala 434:81] - node _T_10689 = or(_T_10688, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10690 = bits(_T_10689, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_12_10 = mux(_T_10690, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10691 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10692 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10693 = eq(_T_10692, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_10694 = and(_T_10691, _T_10693) @[ifu_bp_ctl.scala 434:23] - node _T_10695 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10696 = eq(_T_10695, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_10697 = and(_T_10694, _T_10696) @[ifu_bp_ctl.scala 434:81] - node _T_10698 = or(_T_10697, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10699 = bits(_T_10698, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_12_11 = mux(_T_10699, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10700 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10701 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10702 = eq(_T_10701, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_10703 = and(_T_10700, _T_10702) @[ifu_bp_ctl.scala 434:23] - node _T_10704 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10705 = eq(_T_10704, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_10706 = and(_T_10703, _T_10705) @[ifu_bp_ctl.scala 434:81] - node _T_10707 = or(_T_10706, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10708 = bits(_T_10707, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_12_12 = mux(_T_10708, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10709 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10710 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10711 = eq(_T_10710, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_10712 = and(_T_10709, _T_10711) @[ifu_bp_ctl.scala 434:23] - node _T_10713 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10714 = eq(_T_10713, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_10715 = and(_T_10712, _T_10714) @[ifu_bp_ctl.scala 434:81] - node _T_10716 = or(_T_10715, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10717 = bits(_T_10716, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_12_13 = mux(_T_10717, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10718 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10719 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10720 = eq(_T_10719, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_10721 = and(_T_10718, _T_10720) @[ifu_bp_ctl.scala 434:23] - node _T_10722 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10723 = eq(_T_10722, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_10724 = and(_T_10721, _T_10723) @[ifu_bp_ctl.scala 434:81] - node _T_10725 = or(_T_10724, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10726 = bits(_T_10725, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_12_14 = mux(_T_10726, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10727 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10728 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10729 = eq(_T_10728, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_10730 = and(_T_10727, _T_10729) @[ifu_bp_ctl.scala 434:23] - node _T_10731 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10732 = eq(_T_10731, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:154] - node _T_10733 = and(_T_10730, _T_10732) @[ifu_bp_ctl.scala 434:81] - node _T_10734 = or(_T_10733, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10735 = bits(_T_10734, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_12_15 = mux(_T_10735, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10736 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10737 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10738 = eq(_T_10737, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_10739 = and(_T_10736, _T_10738) @[ifu_bp_ctl.scala 434:23] - node _T_10740 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10741 = eq(_T_10740, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_10742 = and(_T_10739, _T_10741) @[ifu_bp_ctl.scala 434:81] - node _T_10743 = or(_T_10742, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10744 = bits(_T_10743, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_13_0 = mux(_T_10744, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10745 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10746 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10747 = eq(_T_10746, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_10748 = and(_T_10745, _T_10747) @[ifu_bp_ctl.scala 434:23] - node _T_10749 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10750 = eq(_T_10749, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_10751 = and(_T_10748, _T_10750) @[ifu_bp_ctl.scala 434:81] - node _T_10752 = or(_T_10751, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10753 = bits(_T_10752, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_13_1 = mux(_T_10753, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10754 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10755 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10756 = eq(_T_10755, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_10757 = and(_T_10754, _T_10756) @[ifu_bp_ctl.scala 434:23] - node _T_10758 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10759 = eq(_T_10758, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_10760 = and(_T_10757, _T_10759) @[ifu_bp_ctl.scala 434:81] - node _T_10761 = or(_T_10760, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10762 = bits(_T_10761, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_13_2 = mux(_T_10762, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10763 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10764 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10765 = eq(_T_10764, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_10766 = and(_T_10763, _T_10765) @[ifu_bp_ctl.scala 434:23] - node _T_10767 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10768 = eq(_T_10767, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_10769 = and(_T_10766, _T_10768) @[ifu_bp_ctl.scala 434:81] - node _T_10770 = or(_T_10769, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10771 = bits(_T_10770, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_13_3 = mux(_T_10771, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10772 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10773 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10774 = eq(_T_10773, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_10775 = and(_T_10772, _T_10774) @[ifu_bp_ctl.scala 434:23] - node _T_10776 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10777 = eq(_T_10776, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_10778 = and(_T_10775, _T_10777) @[ifu_bp_ctl.scala 434:81] - node _T_10779 = or(_T_10778, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10780 = bits(_T_10779, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_13_4 = mux(_T_10780, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10781 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10782 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10783 = eq(_T_10782, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_10784 = and(_T_10781, _T_10783) @[ifu_bp_ctl.scala 434:23] - node _T_10785 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10786 = eq(_T_10785, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_10787 = and(_T_10784, _T_10786) @[ifu_bp_ctl.scala 434:81] - node _T_10788 = or(_T_10787, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10789 = bits(_T_10788, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_13_5 = mux(_T_10789, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10790 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10791 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10792 = eq(_T_10791, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_10793 = and(_T_10790, _T_10792) @[ifu_bp_ctl.scala 434:23] - node _T_10794 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10795 = eq(_T_10794, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_10796 = and(_T_10793, _T_10795) @[ifu_bp_ctl.scala 434:81] - node _T_10797 = or(_T_10796, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10798 = bits(_T_10797, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_13_6 = mux(_T_10798, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10799 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10800 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10801 = eq(_T_10800, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_10802 = and(_T_10799, _T_10801) @[ifu_bp_ctl.scala 434:23] - node _T_10803 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10804 = eq(_T_10803, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_10805 = and(_T_10802, _T_10804) @[ifu_bp_ctl.scala 434:81] - node _T_10806 = or(_T_10805, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10807 = bits(_T_10806, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_13_7 = mux(_T_10807, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10808 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10809 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10810 = eq(_T_10809, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_10811 = and(_T_10808, _T_10810) @[ifu_bp_ctl.scala 434:23] - node _T_10812 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10813 = eq(_T_10812, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_10814 = and(_T_10811, _T_10813) @[ifu_bp_ctl.scala 434:81] - node _T_10815 = or(_T_10814, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10816 = bits(_T_10815, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_13_8 = mux(_T_10816, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10817 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10818 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10819 = eq(_T_10818, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_10820 = and(_T_10817, _T_10819) @[ifu_bp_ctl.scala 434:23] - node _T_10821 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10822 = eq(_T_10821, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_10823 = and(_T_10820, _T_10822) @[ifu_bp_ctl.scala 434:81] - node _T_10824 = or(_T_10823, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10825 = bits(_T_10824, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_13_9 = mux(_T_10825, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10826 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10827 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10828 = eq(_T_10827, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_10829 = and(_T_10826, _T_10828) @[ifu_bp_ctl.scala 434:23] - node _T_10830 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10831 = eq(_T_10830, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_10832 = and(_T_10829, _T_10831) @[ifu_bp_ctl.scala 434:81] - node _T_10833 = or(_T_10832, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10834 = bits(_T_10833, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_13_10 = mux(_T_10834, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10835 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10836 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10837 = eq(_T_10836, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_10838 = and(_T_10835, _T_10837) @[ifu_bp_ctl.scala 434:23] - node _T_10839 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10840 = eq(_T_10839, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_10841 = and(_T_10838, _T_10840) @[ifu_bp_ctl.scala 434:81] - node _T_10842 = or(_T_10841, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10843 = bits(_T_10842, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_13_11 = mux(_T_10843, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10844 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10845 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10846 = eq(_T_10845, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_10847 = and(_T_10844, _T_10846) @[ifu_bp_ctl.scala 434:23] - node _T_10848 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10849 = eq(_T_10848, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_10850 = and(_T_10847, _T_10849) @[ifu_bp_ctl.scala 434:81] - node _T_10851 = or(_T_10850, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10852 = bits(_T_10851, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_13_12 = mux(_T_10852, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10853 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10854 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10855 = eq(_T_10854, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_10856 = and(_T_10853, _T_10855) @[ifu_bp_ctl.scala 434:23] - node _T_10857 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10858 = eq(_T_10857, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_10859 = and(_T_10856, _T_10858) @[ifu_bp_ctl.scala 434:81] - node _T_10860 = or(_T_10859, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10861 = bits(_T_10860, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_13_13 = mux(_T_10861, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10862 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10863 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10864 = eq(_T_10863, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_10865 = and(_T_10862, _T_10864) @[ifu_bp_ctl.scala 434:23] - node _T_10866 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10867 = eq(_T_10866, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_10868 = and(_T_10865, _T_10867) @[ifu_bp_ctl.scala 434:81] - node _T_10869 = or(_T_10868, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10870 = bits(_T_10869, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_13_14 = mux(_T_10870, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10871 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10872 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10873 = eq(_T_10872, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_10874 = and(_T_10871, _T_10873) @[ifu_bp_ctl.scala 434:23] - node _T_10875 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10876 = eq(_T_10875, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:154] - node _T_10877 = and(_T_10874, _T_10876) @[ifu_bp_ctl.scala 434:81] - node _T_10878 = or(_T_10877, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10879 = bits(_T_10878, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_13_15 = mux(_T_10879, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10880 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10881 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10882 = eq(_T_10881, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_10883 = and(_T_10880, _T_10882) @[ifu_bp_ctl.scala 434:23] - node _T_10884 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10885 = eq(_T_10884, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_10886 = and(_T_10883, _T_10885) @[ifu_bp_ctl.scala 434:81] - node _T_10887 = or(_T_10886, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10888 = bits(_T_10887, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_14_0 = mux(_T_10888, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10889 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10890 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10891 = eq(_T_10890, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_10892 = and(_T_10889, _T_10891) @[ifu_bp_ctl.scala 434:23] - node _T_10893 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10894 = eq(_T_10893, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_10895 = and(_T_10892, _T_10894) @[ifu_bp_ctl.scala 434:81] - node _T_10896 = or(_T_10895, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10897 = bits(_T_10896, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_14_1 = mux(_T_10897, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10898 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10899 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10900 = eq(_T_10899, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_10901 = and(_T_10898, _T_10900) @[ifu_bp_ctl.scala 434:23] - node _T_10902 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10903 = eq(_T_10902, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_10904 = and(_T_10901, _T_10903) @[ifu_bp_ctl.scala 434:81] - node _T_10905 = or(_T_10904, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10906 = bits(_T_10905, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_14_2 = mux(_T_10906, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10907 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10908 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10909 = eq(_T_10908, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_10910 = and(_T_10907, _T_10909) @[ifu_bp_ctl.scala 434:23] - node _T_10911 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10912 = eq(_T_10911, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_10913 = and(_T_10910, _T_10912) @[ifu_bp_ctl.scala 434:81] - node _T_10914 = or(_T_10913, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10915 = bits(_T_10914, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_14_3 = mux(_T_10915, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10916 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10917 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10918 = eq(_T_10917, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_10919 = and(_T_10916, _T_10918) @[ifu_bp_ctl.scala 434:23] - node _T_10920 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10921 = eq(_T_10920, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_10922 = and(_T_10919, _T_10921) @[ifu_bp_ctl.scala 434:81] - node _T_10923 = or(_T_10922, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10924 = bits(_T_10923, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_14_4 = mux(_T_10924, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10925 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10926 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10927 = eq(_T_10926, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_10928 = and(_T_10925, _T_10927) @[ifu_bp_ctl.scala 434:23] - node _T_10929 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10930 = eq(_T_10929, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_10931 = and(_T_10928, _T_10930) @[ifu_bp_ctl.scala 434:81] - node _T_10932 = or(_T_10931, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10933 = bits(_T_10932, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_14_5 = mux(_T_10933, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10934 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10935 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10936 = eq(_T_10935, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_10937 = and(_T_10934, _T_10936) @[ifu_bp_ctl.scala 434:23] - node _T_10938 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10939 = eq(_T_10938, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_10940 = and(_T_10937, _T_10939) @[ifu_bp_ctl.scala 434:81] - node _T_10941 = or(_T_10940, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10942 = bits(_T_10941, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_14_6 = mux(_T_10942, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10943 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10944 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10945 = eq(_T_10944, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_10946 = and(_T_10943, _T_10945) @[ifu_bp_ctl.scala 434:23] - node _T_10947 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10948 = eq(_T_10947, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_10949 = and(_T_10946, _T_10948) @[ifu_bp_ctl.scala 434:81] - node _T_10950 = or(_T_10949, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10951 = bits(_T_10950, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_14_7 = mux(_T_10951, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10952 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10953 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10954 = eq(_T_10953, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_10955 = and(_T_10952, _T_10954) @[ifu_bp_ctl.scala 434:23] - node _T_10956 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10957 = eq(_T_10956, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_10958 = and(_T_10955, _T_10957) @[ifu_bp_ctl.scala 434:81] - node _T_10959 = or(_T_10958, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10960 = bits(_T_10959, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_14_8 = mux(_T_10960, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10961 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10962 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10963 = eq(_T_10962, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_10964 = and(_T_10961, _T_10963) @[ifu_bp_ctl.scala 434:23] - node _T_10965 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10966 = eq(_T_10965, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_10967 = and(_T_10964, _T_10966) @[ifu_bp_ctl.scala 434:81] - node _T_10968 = or(_T_10967, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10969 = bits(_T_10968, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_14_9 = mux(_T_10969, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10970 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10971 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10972 = eq(_T_10971, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_10973 = and(_T_10970, _T_10972) @[ifu_bp_ctl.scala 434:23] - node _T_10974 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10975 = eq(_T_10974, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_10976 = and(_T_10973, _T_10975) @[ifu_bp_ctl.scala 434:81] - node _T_10977 = or(_T_10976, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10978 = bits(_T_10977, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_14_10 = mux(_T_10978, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10979 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10980 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10981 = eq(_T_10980, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_10982 = and(_T_10979, _T_10981) @[ifu_bp_ctl.scala 434:23] - node _T_10983 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10984 = eq(_T_10983, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_10985 = and(_T_10982, _T_10984) @[ifu_bp_ctl.scala 434:81] - node _T_10986 = or(_T_10985, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10987 = bits(_T_10986, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_14_11 = mux(_T_10987, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10988 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10989 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10990 = eq(_T_10989, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_10991 = and(_T_10988, _T_10990) @[ifu_bp_ctl.scala 434:23] - node _T_10992 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_10993 = eq(_T_10992, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_10994 = and(_T_10991, _T_10993) @[ifu_bp_ctl.scala 434:81] - node _T_10995 = or(_T_10994, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_10996 = bits(_T_10995, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_14_12 = mux(_T_10996, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_10997 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_10998 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_10999 = eq(_T_10998, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_11000 = and(_T_10997, _T_10999) @[ifu_bp_ctl.scala 434:23] - node _T_11001 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_11002 = eq(_T_11001, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_11003 = and(_T_11000, _T_11002) @[ifu_bp_ctl.scala 434:81] - node _T_11004 = or(_T_11003, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_11005 = bits(_T_11004, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_14_13 = mux(_T_11005, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_11006 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_11007 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_11008 = eq(_T_11007, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_11009 = and(_T_11006, _T_11008) @[ifu_bp_ctl.scala 434:23] - node _T_11010 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_11011 = eq(_T_11010, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_11012 = and(_T_11009, _T_11011) @[ifu_bp_ctl.scala 434:81] - node _T_11013 = or(_T_11012, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_11014 = bits(_T_11013, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_14_14 = mux(_T_11014, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_11015 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_11016 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_11017 = eq(_T_11016, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_11018 = and(_T_11015, _T_11017) @[ifu_bp_ctl.scala 434:23] - node _T_11019 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_11020 = eq(_T_11019, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:154] - node _T_11021 = and(_T_11018, _T_11020) @[ifu_bp_ctl.scala 434:81] - node _T_11022 = or(_T_11021, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_11023 = bits(_T_11022, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_14_15 = mux(_T_11023, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_11024 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_11025 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_11026 = eq(_T_11025, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:74] - node _T_11027 = and(_T_11024, _T_11026) @[ifu_bp_ctl.scala 434:23] - node _T_11028 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_11029 = eq(_T_11028, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_11030 = and(_T_11027, _T_11029) @[ifu_bp_ctl.scala 434:81] - node _T_11031 = or(_T_11030, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_11032 = bits(_T_11031, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_15_0 = mux(_T_11032, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_11033 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_11034 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_11035 = eq(_T_11034, UInt<1>("h01")) @[ifu_bp_ctl.scala 434:74] - node _T_11036 = and(_T_11033, _T_11035) @[ifu_bp_ctl.scala 434:23] - node _T_11037 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_11038 = eq(_T_11037, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_11039 = and(_T_11036, _T_11038) @[ifu_bp_ctl.scala 434:81] - node _T_11040 = or(_T_11039, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_11041 = bits(_T_11040, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_15_1 = mux(_T_11041, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_11042 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_11043 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_11044 = eq(_T_11043, UInt<2>("h02")) @[ifu_bp_ctl.scala 434:74] - node _T_11045 = and(_T_11042, _T_11044) @[ifu_bp_ctl.scala 434:23] - node _T_11046 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_11047 = eq(_T_11046, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_11048 = and(_T_11045, _T_11047) @[ifu_bp_ctl.scala 434:81] - node _T_11049 = or(_T_11048, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_11050 = bits(_T_11049, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_15_2 = mux(_T_11050, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_11051 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_11052 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_11053 = eq(_T_11052, UInt<2>("h03")) @[ifu_bp_ctl.scala 434:74] - node _T_11054 = and(_T_11051, _T_11053) @[ifu_bp_ctl.scala 434:23] - node _T_11055 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_11056 = eq(_T_11055, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_11057 = and(_T_11054, _T_11056) @[ifu_bp_ctl.scala 434:81] - node _T_11058 = or(_T_11057, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_11059 = bits(_T_11058, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_15_3 = mux(_T_11059, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_11060 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_11061 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_11062 = eq(_T_11061, UInt<3>("h04")) @[ifu_bp_ctl.scala 434:74] - node _T_11063 = and(_T_11060, _T_11062) @[ifu_bp_ctl.scala 434:23] - node _T_11064 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_11065 = eq(_T_11064, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_11066 = and(_T_11063, _T_11065) @[ifu_bp_ctl.scala 434:81] - node _T_11067 = or(_T_11066, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_11068 = bits(_T_11067, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_15_4 = mux(_T_11068, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_11069 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_11070 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_11071 = eq(_T_11070, UInt<3>("h05")) @[ifu_bp_ctl.scala 434:74] - node _T_11072 = and(_T_11069, _T_11071) @[ifu_bp_ctl.scala 434:23] - node _T_11073 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_11074 = eq(_T_11073, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_11075 = and(_T_11072, _T_11074) @[ifu_bp_ctl.scala 434:81] - node _T_11076 = or(_T_11075, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_11077 = bits(_T_11076, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_15_5 = mux(_T_11077, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_11078 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_11079 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_11080 = eq(_T_11079, UInt<3>("h06")) @[ifu_bp_ctl.scala 434:74] - node _T_11081 = and(_T_11078, _T_11080) @[ifu_bp_ctl.scala 434:23] - node _T_11082 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_11083 = eq(_T_11082, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_11084 = and(_T_11081, _T_11083) @[ifu_bp_ctl.scala 434:81] - node _T_11085 = or(_T_11084, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_11086 = bits(_T_11085, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_15_6 = mux(_T_11086, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_11087 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_11088 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_11089 = eq(_T_11088, UInt<3>("h07")) @[ifu_bp_ctl.scala 434:74] - node _T_11090 = and(_T_11087, _T_11089) @[ifu_bp_ctl.scala 434:23] - node _T_11091 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_11092 = eq(_T_11091, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_11093 = and(_T_11090, _T_11092) @[ifu_bp_ctl.scala 434:81] - node _T_11094 = or(_T_11093, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_11095 = bits(_T_11094, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_15_7 = mux(_T_11095, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_11096 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_11097 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_11098 = eq(_T_11097, UInt<4>("h08")) @[ifu_bp_ctl.scala 434:74] - node _T_11099 = and(_T_11096, _T_11098) @[ifu_bp_ctl.scala 434:23] - node _T_11100 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_11101 = eq(_T_11100, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_11102 = and(_T_11099, _T_11101) @[ifu_bp_ctl.scala 434:81] - node _T_11103 = or(_T_11102, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_11104 = bits(_T_11103, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_15_8 = mux(_T_11104, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_11105 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_11106 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_11107 = eq(_T_11106, UInt<4>("h09")) @[ifu_bp_ctl.scala 434:74] - node _T_11108 = and(_T_11105, _T_11107) @[ifu_bp_ctl.scala 434:23] - node _T_11109 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_11110 = eq(_T_11109, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_11111 = and(_T_11108, _T_11110) @[ifu_bp_ctl.scala 434:81] - node _T_11112 = or(_T_11111, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_11113 = bits(_T_11112, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_15_9 = mux(_T_11113, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_11114 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_11115 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_11116 = eq(_T_11115, UInt<4>("h0a")) @[ifu_bp_ctl.scala 434:74] - node _T_11117 = and(_T_11114, _T_11116) @[ifu_bp_ctl.scala 434:23] - node _T_11118 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_11119 = eq(_T_11118, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_11120 = and(_T_11117, _T_11119) @[ifu_bp_ctl.scala 434:81] - node _T_11121 = or(_T_11120, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_11122 = bits(_T_11121, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_15_10 = mux(_T_11122, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_11123 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_11124 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_11125 = eq(_T_11124, UInt<4>("h0b")) @[ifu_bp_ctl.scala 434:74] - node _T_11126 = and(_T_11123, _T_11125) @[ifu_bp_ctl.scala 434:23] - node _T_11127 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_11128 = eq(_T_11127, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_11129 = and(_T_11126, _T_11128) @[ifu_bp_ctl.scala 434:81] - node _T_11130 = or(_T_11129, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_11131 = bits(_T_11130, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_15_11 = mux(_T_11131, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_11132 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_11133 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_11134 = eq(_T_11133, UInt<4>("h0c")) @[ifu_bp_ctl.scala 434:74] - node _T_11135 = and(_T_11132, _T_11134) @[ifu_bp_ctl.scala 434:23] - node _T_11136 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_11137 = eq(_T_11136, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_11138 = and(_T_11135, _T_11137) @[ifu_bp_ctl.scala 434:81] - node _T_11139 = or(_T_11138, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_11140 = bits(_T_11139, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_15_12 = mux(_T_11140, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_11141 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_11142 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_11143 = eq(_T_11142, UInt<4>("h0d")) @[ifu_bp_ctl.scala 434:74] - node _T_11144 = and(_T_11141, _T_11143) @[ifu_bp_ctl.scala 434:23] - node _T_11145 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_11146 = eq(_T_11145, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_11147 = and(_T_11144, _T_11146) @[ifu_bp_ctl.scala 434:81] - node _T_11148 = or(_T_11147, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_11149 = bits(_T_11148, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_15_13 = mux(_T_11149, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_11150 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_11151 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_11152 = eq(_T_11151, UInt<4>("h0e")) @[ifu_bp_ctl.scala 434:74] - node _T_11153 = and(_T_11150, _T_11152) @[ifu_bp_ctl.scala 434:23] - node _T_11154 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_11155 = eq(_T_11154, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_11156 = and(_T_11153, _T_11155) @[ifu_bp_ctl.scala 434:81] - node _T_11157 = or(_T_11156, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_11158 = bits(_T_11157, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_15_14 = mux(_T_11158, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - node _T_11159 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 434:20] - node _T_11160 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 434:37] - node _T_11161 = eq(_T_11160, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:74] - node _T_11162 = and(_T_11159, _T_11161) @[ifu_bp_ctl.scala 434:23] - node _T_11163 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 434:95] - node _T_11164 = eq(_T_11163, UInt<4>("h0f")) @[ifu_bp_ctl.scala 434:154] - node _T_11165 = and(_T_11162, _T_11164) @[ifu_bp_ctl.scala 434:81] - node _T_11166 = or(_T_11165, UInt<1>("h00")) @[ifu_bp_ctl.scala 434:161] - node _T_11167 = bits(_T_11166, 0, 0) @[ifu_bp_ctl.scala 434:183] - node bht_bank_wr_data_1_15_15 = mux(_T_11167, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 434:8] - wire bht_bank_sel : UInt<1>[16][16][2] @[ifu_bp_ctl.scala 436:26] - node _T_11168 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11169 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11170 = eq(_T_11169, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_11171 = and(_T_11168, _T_11170) @[ifu_bp_ctl.scala 442:45] - node _T_11172 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11173 = eq(_T_11172, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_11174 = or(_T_11173, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11175 = and(_T_11171, _T_11174) @[ifu_bp_ctl.scala 442:110] - node _T_11176 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11177 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11178 = eq(_T_11177, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_11179 = and(_T_11176, _T_11178) @[ifu_bp_ctl.scala 443:22] - node _T_11180 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11181 = eq(_T_11180, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_11182 = or(_T_11181, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11183 = and(_T_11179, _T_11182) @[ifu_bp_ctl.scala 443:87] - node _T_11184 = or(_T_11175, _T_11183) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][0][0] <= _T_11184 @[ifu_bp_ctl.scala 442:27] - node _T_11185 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11186 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11187 = eq(_T_11186, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_11188 = and(_T_11185, _T_11187) @[ifu_bp_ctl.scala 442:45] - node _T_11189 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11190 = eq(_T_11189, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_11191 = or(_T_11190, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11192 = and(_T_11188, _T_11191) @[ifu_bp_ctl.scala 442:110] - node _T_11193 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11194 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11195 = eq(_T_11194, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_11196 = and(_T_11193, _T_11195) @[ifu_bp_ctl.scala 443:22] - node _T_11197 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11198 = eq(_T_11197, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_11199 = or(_T_11198, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11200 = and(_T_11196, _T_11199) @[ifu_bp_ctl.scala 443:87] - node _T_11201 = or(_T_11192, _T_11200) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][0][1] <= _T_11201 @[ifu_bp_ctl.scala 442:27] - node _T_11202 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11203 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11204 = eq(_T_11203, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_11205 = and(_T_11202, _T_11204) @[ifu_bp_ctl.scala 442:45] - node _T_11206 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11207 = eq(_T_11206, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_11208 = or(_T_11207, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11209 = and(_T_11205, _T_11208) @[ifu_bp_ctl.scala 442:110] - node _T_11210 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11211 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11212 = eq(_T_11211, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_11213 = and(_T_11210, _T_11212) @[ifu_bp_ctl.scala 443:22] - node _T_11214 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11215 = eq(_T_11214, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_11216 = or(_T_11215, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11217 = and(_T_11213, _T_11216) @[ifu_bp_ctl.scala 443:87] - node _T_11218 = or(_T_11209, _T_11217) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][0][2] <= _T_11218 @[ifu_bp_ctl.scala 442:27] - node _T_11219 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11220 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11221 = eq(_T_11220, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_11222 = and(_T_11219, _T_11221) @[ifu_bp_ctl.scala 442:45] - node _T_11223 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11224 = eq(_T_11223, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_11225 = or(_T_11224, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11226 = and(_T_11222, _T_11225) @[ifu_bp_ctl.scala 442:110] - node _T_11227 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11228 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11229 = eq(_T_11228, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_11230 = and(_T_11227, _T_11229) @[ifu_bp_ctl.scala 443:22] - node _T_11231 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11232 = eq(_T_11231, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_11233 = or(_T_11232, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11234 = and(_T_11230, _T_11233) @[ifu_bp_ctl.scala 443:87] - node _T_11235 = or(_T_11226, _T_11234) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][0][3] <= _T_11235 @[ifu_bp_ctl.scala 442:27] - node _T_11236 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11237 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11238 = eq(_T_11237, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_11239 = and(_T_11236, _T_11238) @[ifu_bp_ctl.scala 442:45] - node _T_11240 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11241 = eq(_T_11240, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_11242 = or(_T_11241, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11243 = and(_T_11239, _T_11242) @[ifu_bp_ctl.scala 442:110] - node _T_11244 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11245 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11246 = eq(_T_11245, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_11247 = and(_T_11244, _T_11246) @[ifu_bp_ctl.scala 443:22] - node _T_11248 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11249 = eq(_T_11248, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_11250 = or(_T_11249, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11251 = and(_T_11247, _T_11250) @[ifu_bp_ctl.scala 443:87] - node _T_11252 = or(_T_11243, _T_11251) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][0][4] <= _T_11252 @[ifu_bp_ctl.scala 442:27] - node _T_11253 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11254 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11255 = eq(_T_11254, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_11256 = and(_T_11253, _T_11255) @[ifu_bp_ctl.scala 442:45] - node _T_11257 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11258 = eq(_T_11257, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_11259 = or(_T_11258, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11260 = and(_T_11256, _T_11259) @[ifu_bp_ctl.scala 442:110] - node _T_11261 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11262 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11263 = eq(_T_11262, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_11264 = and(_T_11261, _T_11263) @[ifu_bp_ctl.scala 443:22] - node _T_11265 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11266 = eq(_T_11265, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_11267 = or(_T_11266, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11268 = and(_T_11264, _T_11267) @[ifu_bp_ctl.scala 443:87] - node _T_11269 = or(_T_11260, _T_11268) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][0][5] <= _T_11269 @[ifu_bp_ctl.scala 442:27] - node _T_11270 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11271 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11272 = eq(_T_11271, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_11273 = and(_T_11270, _T_11272) @[ifu_bp_ctl.scala 442:45] - node _T_11274 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11275 = eq(_T_11274, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_11276 = or(_T_11275, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11277 = and(_T_11273, _T_11276) @[ifu_bp_ctl.scala 442:110] - node _T_11278 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11279 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11280 = eq(_T_11279, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_11281 = and(_T_11278, _T_11280) @[ifu_bp_ctl.scala 443:22] - node _T_11282 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11283 = eq(_T_11282, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_11284 = or(_T_11283, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11285 = and(_T_11281, _T_11284) @[ifu_bp_ctl.scala 443:87] - node _T_11286 = or(_T_11277, _T_11285) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][0][6] <= _T_11286 @[ifu_bp_ctl.scala 442:27] - node _T_11287 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11288 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11289 = eq(_T_11288, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_11290 = and(_T_11287, _T_11289) @[ifu_bp_ctl.scala 442:45] - node _T_11291 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11292 = eq(_T_11291, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_11293 = or(_T_11292, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11294 = and(_T_11290, _T_11293) @[ifu_bp_ctl.scala 442:110] - node _T_11295 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11296 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11297 = eq(_T_11296, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_11298 = and(_T_11295, _T_11297) @[ifu_bp_ctl.scala 443:22] - node _T_11299 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11300 = eq(_T_11299, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_11301 = or(_T_11300, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11302 = and(_T_11298, _T_11301) @[ifu_bp_ctl.scala 443:87] - node _T_11303 = or(_T_11294, _T_11302) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][0][7] <= _T_11303 @[ifu_bp_ctl.scala 442:27] - node _T_11304 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11305 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11306 = eq(_T_11305, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_11307 = and(_T_11304, _T_11306) @[ifu_bp_ctl.scala 442:45] - node _T_11308 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11309 = eq(_T_11308, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_11310 = or(_T_11309, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11311 = and(_T_11307, _T_11310) @[ifu_bp_ctl.scala 442:110] - node _T_11312 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11313 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11314 = eq(_T_11313, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_11315 = and(_T_11312, _T_11314) @[ifu_bp_ctl.scala 443:22] - node _T_11316 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11317 = eq(_T_11316, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_11318 = or(_T_11317, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11319 = and(_T_11315, _T_11318) @[ifu_bp_ctl.scala 443:87] - node _T_11320 = or(_T_11311, _T_11319) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][0][8] <= _T_11320 @[ifu_bp_ctl.scala 442:27] - node _T_11321 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11322 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11323 = eq(_T_11322, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_11324 = and(_T_11321, _T_11323) @[ifu_bp_ctl.scala 442:45] - node _T_11325 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11326 = eq(_T_11325, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_11327 = or(_T_11326, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11328 = and(_T_11324, _T_11327) @[ifu_bp_ctl.scala 442:110] - node _T_11329 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11330 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11331 = eq(_T_11330, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_11332 = and(_T_11329, _T_11331) @[ifu_bp_ctl.scala 443:22] - node _T_11333 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11334 = eq(_T_11333, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_11335 = or(_T_11334, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11336 = and(_T_11332, _T_11335) @[ifu_bp_ctl.scala 443:87] - node _T_11337 = or(_T_11328, _T_11336) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][0][9] <= _T_11337 @[ifu_bp_ctl.scala 442:27] - node _T_11338 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11339 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11340 = eq(_T_11339, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_11341 = and(_T_11338, _T_11340) @[ifu_bp_ctl.scala 442:45] - node _T_11342 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11343 = eq(_T_11342, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_11344 = or(_T_11343, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11345 = and(_T_11341, _T_11344) @[ifu_bp_ctl.scala 442:110] - node _T_11346 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11347 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11348 = eq(_T_11347, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_11349 = and(_T_11346, _T_11348) @[ifu_bp_ctl.scala 443:22] - node _T_11350 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11351 = eq(_T_11350, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_11352 = or(_T_11351, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11353 = and(_T_11349, _T_11352) @[ifu_bp_ctl.scala 443:87] - node _T_11354 = or(_T_11345, _T_11353) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][0][10] <= _T_11354 @[ifu_bp_ctl.scala 442:27] - node _T_11355 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11356 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11357 = eq(_T_11356, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_11358 = and(_T_11355, _T_11357) @[ifu_bp_ctl.scala 442:45] - node _T_11359 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11360 = eq(_T_11359, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_11361 = or(_T_11360, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11362 = and(_T_11358, _T_11361) @[ifu_bp_ctl.scala 442:110] - node _T_11363 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11364 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11365 = eq(_T_11364, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_11366 = and(_T_11363, _T_11365) @[ifu_bp_ctl.scala 443:22] - node _T_11367 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11368 = eq(_T_11367, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_11369 = or(_T_11368, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11370 = and(_T_11366, _T_11369) @[ifu_bp_ctl.scala 443:87] - node _T_11371 = or(_T_11362, _T_11370) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][0][11] <= _T_11371 @[ifu_bp_ctl.scala 442:27] - node _T_11372 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11373 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11374 = eq(_T_11373, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_11375 = and(_T_11372, _T_11374) @[ifu_bp_ctl.scala 442:45] - node _T_11376 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11377 = eq(_T_11376, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_11378 = or(_T_11377, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11379 = and(_T_11375, _T_11378) @[ifu_bp_ctl.scala 442:110] - node _T_11380 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11381 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11382 = eq(_T_11381, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_11383 = and(_T_11380, _T_11382) @[ifu_bp_ctl.scala 443:22] - node _T_11384 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11385 = eq(_T_11384, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_11386 = or(_T_11385, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11387 = and(_T_11383, _T_11386) @[ifu_bp_ctl.scala 443:87] - node _T_11388 = or(_T_11379, _T_11387) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][0][12] <= _T_11388 @[ifu_bp_ctl.scala 442:27] - node _T_11389 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11390 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11391 = eq(_T_11390, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_11392 = and(_T_11389, _T_11391) @[ifu_bp_ctl.scala 442:45] - node _T_11393 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11394 = eq(_T_11393, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_11395 = or(_T_11394, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11396 = and(_T_11392, _T_11395) @[ifu_bp_ctl.scala 442:110] - node _T_11397 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11398 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11399 = eq(_T_11398, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_11400 = and(_T_11397, _T_11399) @[ifu_bp_ctl.scala 443:22] - node _T_11401 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11402 = eq(_T_11401, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_11403 = or(_T_11402, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11404 = and(_T_11400, _T_11403) @[ifu_bp_ctl.scala 443:87] - node _T_11405 = or(_T_11396, _T_11404) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][0][13] <= _T_11405 @[ifu_bp_ctl.scala 442:27] - node _T_11406 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11407 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11408 = eq(_T_11407, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_11409 = and(_T_11406, _T_11408) @[ifu_bp_ctl.scala 442:45] - node _T_11410 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11411 = eq(_T_11410, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_11412 = or(_T_11411, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11413 = and(_T_11409, _T_11412) @[ifu_bp_ctl.scala 442:110] - node _T_11414 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11415 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11416 = eq(_T_11415, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_11417 = and(_T_11414, _T_11416) @[ifu_bp_ctl.scala 443:22] - node _T_11418 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11419 = eq(_T_11418, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_11420 = or(_T_11419, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11421 = and(_T_11417, _T_11420) @[ifu_bp_ctl.scala 443:87] - node _T_11422 = or(_T_11413, _T_11421) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][0][14] <= _T_11422 @[ifu_bp_ctl.scala 442:27] - node _T_11423 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11424 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11425 = eq(_T_11424, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_11426 = and(_T_11423, _T_11425) @[ifu_bp_ctl.scala 442:45] - node _T_11427 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11428 = eq(_T_11427, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_11429 = or(_T_11428, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11430 = and(_T_11426, _T_11429) @[ifu_bp_ctl.scala 442:110] - node _T_11431 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11432 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11433 = eq(_T_11432, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_11434 = and(_T_11431, _T_11433) @[ifu_bp_ctl.scala 443:22] - node _T_11435 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11436 = eq(_T_11435, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_11437 = or(_T_11436, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11438 = and(_T_11434, _T_11437) @[ifu_bp_ctl.scala 443:87] - node _T_11439 = or(_T_11430, _T_11438) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][0][15] <= _T_11439 @[ifu_bp_ctl.scala 442:27] - node _T_11440 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11441 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11442 = eq(_T_11441, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_11443 = and(_T_11440, _T_11442) @[ifu_bp_ctl.scala 442:45] - node _T_11444 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11445 = eq(_T_11444, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_11446 = or(_T_11445, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11447 = and(_T_11443, _T_11446) @[ifu_bp_ctl.scala 442:110] - node _T_11448 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11449 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11450 = eq(_T_11449, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_11451 = and(_T_11448, _T_11450) @[ifu_bp_ctl.scala 443:22] - node _T_11452 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11453 = eq(_T_11452, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_11454 = or(_T_11453, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11455 = and(_T_11451, _T_11454) @[ifu_bp_ctl.scala 443:87] - node _T_11456 = or(_T_11447, _T_11455) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][1][0] <= _T_11456 @[ifu_bp_ctl.scala 442:27] - node _T_11457 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11458 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11459 = eq(_T_11458, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_11460 = and(_T_11457, _T_11459) @[ifu_bp_ctl.scala 442:45] - node _T_11461 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11462 = eq(_T_11461, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_11463 = or(_T_11462, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11464 = and(_T_11460, _T_11463) @[ifu_bp_ctl.scala 442:110] - node _T_11465 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11466 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11467 = eq(_T_11466, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_11468 = and(_T_11465, _T_11467) @[ifu_bp_ctl.scala 443:22] - node _T_11469 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11470 = eq(_T_11469, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_11471 = or(_T_11470, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11472 = and(_T_11468, _T_11471) @[ifu_bp_ctl.scala 443:87] - node _T_11473 = or(_T_11464, _T_11472) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][1][1] <= _T_11473 @[ifu_bp_ctl.scala 442:27] - node _T_11474 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11475 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11476 = eq(_T_11475, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_11477 = and(_T_11474, _T_11476) @[ifu_bp_ctl.scala 442:45] - node _T_11478 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11479 = eq(_T_11478, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_11480 = or(_T_11479, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11481 = and(_T_11477, _T_11480) @[ifu_bp_ctl.scala 442:110] - node _T_11482 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11483 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11484 = eq(_T_11483, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_11485 = and(_T_11482, _T_11484) @[ifu_bp_ctl.scala 443:22] - node _T_11486 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11487 = eq(_T_11486, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_11488 = or(_T_11487, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11489 = and(_T_11485, _T_11488) @[ifu_bp_ctl.scala 443:87] - node _T_11490 = or(_T_11481, _T_11489) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][1][2] <= _T_11490 @[ifu_bp_ctl.scala 442:27] - node _T_11491 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11492 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11493 = eq(_T_11492, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_11494 = and(_T_11491, _T_11493) @[ifu_bp_ctl.scala 442:45] - node _T_11495 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11496 = eq(_T_11495, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_11497 = or(_T_11496, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11498 = and(_T_11494, _T_11497) @[ifu_bp_ctl.scala 442:110] - node _T_11499 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11500 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11501 = eq(_T_11500, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_11502 = and(_T_11499, _T_11501) @[ifu_bp_ctl.scala 443:22] - node _T_11503 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11504 = eq(_T_11503, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_11505 = or(_T_11504, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11506 = and(_T_11502, _T_11505) @[ifu_bp_ctl.scala 443:87] - node _T_11507 = or(_T_11498, _T_11506) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][1][3] <= _T_11507 @[ifu_bp_ctl.scala 442:27] - node _T_11508 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11509 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11510 = eq(_T_11509, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_11511 = and(_T_11508, _T_11510) @[ifu_bp_ctl.scala 442:45] - node _T_11512 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11513 = eq(_T_11512, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_11514 = or(_T_11513, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11515 = and(_T_11511, _T_11514) @[ifu_bp_ctl.scala 442:110] - node _T_11516 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11517 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11518 = eq(_T_11517, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_11519 = and(_T_11516, _T_11518) @[ifu_bp_ctl.scala 443:22] - node _T_11520 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11521 = eq(_T_11520, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_11522 = or(_T_11521, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11523 = and(_T_11519, _T_11522) @[ifu_bp_ctl.scala 443:87] - node _T_11524 = or(_T_11515, _T_11523) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][1][4] <= _T_11524 @[ifu_bp_ctl.scala 442:27] - node _T_11525 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11526 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11527 = eq(_T_11526, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_11528 = and(_T_11525, _T_11527) @[ifu_bp_ctl.scala 442:45] - node _T_11529 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11530 = eq(_T_11529, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_11531 = or(_T_11530, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11532 = and(_T_11528, _T_11531) @[ifu_bp_ctl.scala 442:110] - node _T_11533 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11534 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11535 = eq(_T_11534, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_11536 = and(_T_11533, _T_11535) @[ifu_bp_ctl.scala 443:22] - node _T_11537 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11538 = eq(_T_11537, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_11539 = or(_T_11538, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11540 = and(_T_11536, _T_11539) @[ifu_bp_ctl.scala 443:87] - node _T_11541 = or(_T_11532, _T_11540) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][1][5] <= _T_11541 @[ifu_bp_ctl.scala 442:27] - node _T_11542 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11543 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11544 = eq(_T_11543, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_11545 = and(_T_11542, _T_11544) @[ifu_bp_ctl.scala 442:45] - node _T_11546 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11547 = eq(_T_11546, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_11548 = or(_T_11547, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11549 = and(_T_11545, _T_11548) @[ifu_bp_ctl.scala 442:110] - node _T_11550 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11551 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11552 = eq(_T_11551, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_11553 = and(_T_11550, _T_11552) @[ifu_bp_ctl.scala 443:22] - node _T_11554 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11555 = eq(_T_11554, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_11556 = or(_T_11555, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11557 = and(_T_11553, _T_11556) @[ifu_bp_ctl.scala 443:87] - node _T_11558 = or(_T_11549, _T_11557) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][1][6] <= _T_11558 @[ifu_bp_ctl.scala 442:27] - node _T_11559 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11560 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11561 = eq(_T_11560, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_11562 = and(_T_11559, _T_11561) @[ifu_bp_ctl.scala 442:45] - node _T_11563 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11564 = eq(_T_11563, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_11565 = or(_T_11564, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11566 = and(_T_11562, _T_11565) @[ifu_bp_ctl.scala 442:110] - node _T_11567 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11568 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11569 = eq(_T_11568, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_11570 = and(_T_11567, _T_11569) @[ifu_bp_ctl.scala 443:22] - node _T_11571 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11572 = eq(_T_11571, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_11573 = or(_T_11572, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11574 = and(_T_11570, _T_11573) @[ifu_bp_ctl.scala 443:87] - node _T_11575 = or(_T_11566, _T_11574) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][1][7] <= _T_11575 @[ifu_bp_ctl.scala 442:27] - node _T_11576 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11577 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11578 = eq(_T_11577, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_11579 = and(_T_11576, _T_11578) @[ifu_bp_ctl.scala 442:45] - node _T_11580 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11581 = eq(_T_11580, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_11582 = or(_T_11581, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11583 = and(_T_11579, _T_11582) @[ifu_bp_ctl.scala 442:110] - node _T_11584 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11585 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11586 = eq(_T_11585, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_11587 = and(_T_11584, _T_11586) @[ifu_bp_ctl.scala 443:22] - node _T_11588 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11589 = eq(_T_11588, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_11590 = or(_T_11589, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11591 = and(_T_11587, _T_11590) @[ifu_bp_ctl.scala 443:87] - node _T_11592 = or(_T_11583, _T_11591) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][1][8] <= _T_11592 @[ifu_bp_ctl.scala 442:27] - node _T_11593 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11594 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11595 = eq(_T_11594, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_11596 = and(_T_11593, _T_11595) @[ifu_bp_ctl.scala 442:45] - node _T_11597 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11598 = eq(_T_11597, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_11599 = or(_T_11598, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11600 = and(_T_11596, _T_11599) @[ifu_bp_ctl.scala 442:110] - node _T_11601 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11602 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11603 = eq(_T_11602, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_11604 = and(_T_11601, _T_11603) @[ifu_bp_ctl.scala 443:22] - node _T_11605 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11606 = eq(_T_11605, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_11607 = or(_T_11606, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11608 = and(_T_11604, _T_11607) @[ifu_bp_ctl.scala 443:87] - node _T_11609 = or(_T_11600, _T_11608) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][1][9] <= _T_11609 @[ifu_bp_ctl.scala 442:27] - node _T_11610 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11611 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11612 = eq(_T_11611, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_11613 = and(_T_11610, _T_11612) @[ifu_bp_ctl.scala 442:45] - node _T_11614 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11615 = eq(_T_11614, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_11616 = or(_T_11615, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11617 = and(_T_11613, _T_11616) @[ifu_bp_ctl.scala 442:110] - node _T_11618 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11619 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11620 = eq(_T_11619, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_11621 = and(_T_11618, _T_11620) @[ifu_bp_ctl.scala 443:22] - node _T_11622 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11623 = eq(_T_11622, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_11624 = or(_T_11623, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11625 = and(_T_11621, _T_11624) @[ifu_bp_ctl.scala 443:87] - node _T_11626 = or(_T_11617, _T_11625) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][1][10] <= _T_11626 @[ifu_bp_ctl.scala 442:27] - node _T_11627 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11628 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11629 = eq(_T_11628, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_11630 = and(_T_11627, _T_11629) @[ifu_bp_ctl.scala 442:45] - node _T_11631 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11632 = eq(_T_11631, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_11633 = or(_T_11632, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11634 = and(_T_11630, _T_11633) @[ifu_bp_ctl.scala 442:110] - node _T_11635 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11636 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11637 = eq(_T_11636, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_11638 = and(_T_11635, _T_11637) @[ifu_bp_ctl.scala 443:22] - node _T_11639 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11640 = eq(_T_11639, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_11641 = or(_T_11640, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11642 = and(_T_11638, _T_11641) @[ifu_bp_ctl.scala 443:87] - node _T_11643 = or(_T_11634, _T_11642) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][1][11] <= _T_11643 @[ifu_bp_ctl.scala 442:27] - node _T_11644 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11645 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11646 = eq(_T_11645, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_11647 = and(_T_11644, _T_11646) @[ifu_bp_ctl.scala 442:45] - node _T_11648 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11649 = eq(_T_11648, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_11650 = or(_T_11649, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11651 = and(_T_11647, _T_11650) @[ifu_bp_ctl.scala 442:110] - node _T_11652 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11653 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11654 = eq(_T_11653, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_11655 = and(_T_11652, _T_11654) @[ifu_bp_ctl.scala 443:22] - node _T_11656 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11657 = eq(_T_11656, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_11658 = or(_T_11657, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11659 = and(_T_11655, _T_11658) @[ifu_bp_ctl.scala 443:87] - node _T_11660 = or(_T_11651, _T_11659) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][1][12] <= _T_11660 @[ifu_bp_ctl.scala 442:27] - node _T_11661 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11662 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11663 = eq(_T_11662, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_11664 = and(_T_11661, _T_11663) @[ifu_bp_ctl.scala 442:45] - node _T_11665 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11666 = eq(_T_11665, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_11667 = or(_T_11666, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11668 = and(_T_11664, _T_11667) @[ifu_bp_ctl.scala 442:110] - node _T_11669 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11670 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11671 = eq(_T_11670, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_11672 = and(_T_11669, _T_11671) @[ifu_bp_ctl.scala 443:22] - node _T_11673 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11674 = eq(_T_11673, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_11675 = or(_T_11674, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11676 = and(_T_11672, _T_11675) @[ifu_bp_ctl.scala 443:87] - node _T_11677 = or(_T_11668, _T_11676) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][1][13] <= _T_11677 @[ifu_bp_ctl.scala 442:27] - node _T_11678 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11679 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11680 = eq(_T_11679, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_11681 = and(_T_11678, _T_11680) @[ifu_bp_ctl.scala 442:45] - node _T_11682 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11683 = eq(_T_11682, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_11684 = or(_T_11683, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11685 = and(_T_11681, _T_11684) @[ifu_bp_ctl.scala 442:110] - node _T_11686 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11687 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11688 = eq(_T_11687, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_11689 = and(_T_11686, _T_11688) @[ifu_bp_ctl.scala 443:22] - node _T_11690 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11691 = eq(_T_11690, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_11692 = or(_T_11691, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11693 = and(_T_11689, _T_11692) @[ifu_bp_ctl.scala 443:87] - node _T_11694 = or(_T_11685, _T_11693) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][1][14] <= _T_11694 @[ifu_bp_ctl.scala 442:27] - node _T_11695 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11696 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11697 = eq(_T_11696, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_11698 = and(_T_11695, _T_11697) @[ifu_bp_ctl.scala 442:45] - node _T_11699 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11700 = eq(_T_11699, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_11701 = or(_T_11700, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11702 = and(_T_11698, _T_11701) @[ifu_bp_ctl.scala 442:110] - node _T_11703 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11704 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11705 = eq(_T_11704, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_11706 = and(_T_11703, _T_11705) @[ifu_bp_ctl.scala 443:22] - node _T_11707 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11708 = eq(_T_11707, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_11709 = or(_T_11708, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11710 = and(_T_11706, _T_11709) @[ifu_bp_ctl.scala 443:87] - node _T_11711 = or(_T_11702, _T_11710) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][1][15] <= _T_11711 @[ifu_bp_ctl.scala 442:27] - node _T_11712 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11713 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11714 = eq(_T_11713, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_11715 = and(_T_11712, _T_11714) @[ifu_bp_ctl.scala 442:45] - node _T_11716 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11717 = eq(_T_11716, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_11718 = or(_T_11717, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11719 = and(_T_11715, _T_11718) @[ifu_bp_ctl.scala 442:110] - node _T_11720 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11721 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11722 = eq(_T_11721, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_11723 = and(_T_11720, _T_11722) @[ifu_bp_ctl.scala 443:22] - node _T_11724 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11725 = eq(_T_11724, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_11726 = or(_T_11725, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11727 = and(_T_11723, _T_11726) @[ifu_bp_ctl.scala 443:87] - node _T_11728 = or(_T_11719, _T_11727) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][2][0] <= _T_11728 @[ifu_bp_ctl.scala 442:27] - node _T_11729 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11730 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11731 = eq(_T_11730, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_11732 = and(_T_11729, _T_11731) @[ifu_bp_ctl.scala 442:45] - node _T_11733 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11734 = eq(_T_11733, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_11735 = or(_T_11734, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11736 = and(_T_11732, _T_11735) @[ifu_bp_ctl.scala 442:110] - node _T_11737 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11738 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11739 = eq(_T_11738, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_11740 = and(_T_11737, _T_11739) @[ifu_bp_ctl.scala 443:22] - node _T_11741 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11742 = eq(_T_11741, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_11743 = or(_T_11742, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11744 = and(_T_11740, _T_11743) @[ifu_bp_ctl.scala 443:87] - node _T_11745 = or(_T_11736, _T_11744) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][2][1] <= _T_11745 @[ifu_bp_ctl.scala 442:27] - node _T_11746 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11747 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11748 = eq(_T_11747, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_11749 = and(_T_11746, _T_11748) @[ifu_bp_ctl.scala 442:45] - node _T_11750 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11751 = eq(_T_11750, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_11752 = or(_T_11751, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11753 = and(_T_11749, _T_11752) @[ifu_bp_ctl.scala 442:110] - node _T_11754 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11755 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11756 = eq(_T_11755, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_11757 = and(_T_11754, _T_11756) @[ifu_bp_ctl.scala 443:22] - node _T_11758 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11759 = eq(_T_11758, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_11760 = or(_T_11759, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11761 = and(_T_11757, _T_11760) @[ifu_bp_ctl.scala 443:87] - node _T_11762 = or(_T_11753, _T_11761) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][2][2] <= _T_11762 @[ifu_bp_ctl.scala 442:27] - node _T_11763 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11764 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11765 = eq(_T_11764, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_11766 = and(_T_11763, _T_11765) @[ifu_bp_ctl.scala 442:45] - node _T_11767 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11768 = eq(_T_11767, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_11769 = or(_T_11768, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11770 = and(_T_11766, _T_11769) @[ifu_bp_ctl.scala 442:110] - node _T_11771 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11772 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11773 = eq(_T_11772, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_11774 = and(_T_11771, _T_11773) @[ifu_bp_ctl.scala 443:22] - node _T_11775 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11776 = eq(_T_11775, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_11777 = or(_T_11776, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11778 = and(_T_11774, _T_11777) @[ifu_bp_ctl.scala 443:87] - node _T_11779 = or(_T_11770, _T_11778) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][2][3] <= _T_11779 @[ifu_bp_ctl.scala 442:27] - node _T_11780 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11781 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11782 = eq(_T_11781, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_11783 = and(_T_11780, _T_11782) @[ifu_bp_ctl.scala 442:45] - node _T_11784 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11785 = eq(_T_11784, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_11786 = or(_T_11785, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11787 = and(_T_11783, _T_11786) @[ifu_bp_ctl.scala 442:110] - node _T_11788 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11789 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11790 = eq(_T_11789, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_11791 = and(_T_11788, _T_11790) @[ifu_bp_ctl.scala 443:22] - node _T_11792 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11793 = eq(_T_11792, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_11794 = or(_T_11793, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11795 = and(_T_11791, _T_11794) @[ifu_bp_ctl.scala 443:87] - node _T_11796 = or(_T_11787, _T_11795) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][2][4] <= _T_11796 @[ifu_bp_ctl.scala 442:27] - node _T_11797 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11798 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11799 = eq(_T_11798, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_11800 = and(_T_11797, _T_11799) @[ifu_bp_ctl.scala 442:45] - node _T_11801 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11802 = eq(_T_11801, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_11803 = or(_T_11802, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11804 = and(_T_11800, _T_11803) @[ifu_bp_ctl.scala 442:110] - node _T_11805 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11806 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11807 = eq(_T_11806, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_11808 = and(_T_11805, _T_11807) @[ifu_bp_ctl.scala 443:22] - node _T_11809 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11810 = eq(_T_11809, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_11811 = or(_T_11810, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11812 = and(_T_11808, _T_11811) @[ifu_bp_ctl.scala 443:87] - node _T_11813 = or(_T_11804, _T_11812) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][2][5] <= _T_11813 @[ifu_bp_ctl.scala 442:27] - node _T_11814 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11815 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11816 = eq(_T_11815, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_11817 = and(_T_11814, _T_11816) @[ifu_bp_ctl.scala 442:45] - node _T_11818 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11819 = eq(_T_11818, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_11820 = or(_T_11819, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11821 = and(_T_11817, _T_11820) @[ifu_bp_ctl.scala 442:110] - node _T_11822 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11823 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11824 = eq(_T_11823, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_11825 = and(_T_11822, _T_11824) @[ifu_bp_ctl.scala 443:22] - node _T_11826 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11827 = eq(_T_11826, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_11828 = or(_T_11827, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11829 = and(_T_11825, _T_11828) @[ifu_bp_ctl.scala 443:87] - node _T_11830 = or(_T_11821, _T_11829) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][2][6] <= _T_11830 @[ifu_bp_ctl.scala 442:27] - node _T_11831 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11832 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11833 = eq(_T_11832, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_11834 = and(_T_11831, _T_11833) @[ifu_bp_ctl.scala 442:45] - node _T_11835 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11836 = eq(_T_11835, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_11837 = or(_T_11836, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11838 = and(_T_11834, _T_11837) @[ifu_bp_ctl.scala 442:110] - node _T_11839 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11840 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11841 = eq(_T_11840, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_11842 = and(_T_11839, _T_11841) @[ifu_bp_ctl.scala 443:22] - node _T_11843 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11844 = eq(_T_11843, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_11845 = or(_T_11844, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11846 = and(_T_11842, _T_11845) @[ifu_bp_ctl.scala 443:87] - node _T_11847 = or(_T_11838, _T_11846) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][2][7] <= _T_11847 @[ifu_bp_ctl.scala 442:27] - node _T_11848 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11849 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11850 = eq(_T_11849, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_11851 = and(_T_11848, _T_11850) @[ifu_bp_ctl.scala 442:45] - node _T_11852 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11853 = eq(_T_11852, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_11854 = or(_T_11853, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11855 = and(_T_11851, _T_11854) @[ifu_bp_ctl.scala 442:110] - node _T_11856 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11857 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11858 = eq(_T_11857, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_11859 = and(_T_11856, _T_11858) @[ifu_bp_ctl.scala 443:22] - node _T_11860 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11861 = eq(_T_11860, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_11862 = or(_T_11861, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11863 = and(_T_11859, _T_11862) @[ifu_bp_ctl.scala 443:87] - node _T_11864 = or(_T_11855, _T_11863) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][2][8] <= _T_11864 @[ifu_bp_ctl.scala 442:27] - node _T_11865 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11866 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11867 = eq(_T_11866, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_11868 = and(_T_11865, _T_11867) @[ifu_bp_ctl.scala 442:45] - node _T_11869 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11870 = eq(_T_11869, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_11871 = or(_T_11870, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11872 = and(_T_11868, _T_11871) @[ifu_bp_ctl.scala 442:110] - node _T_11873 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11874 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11875 = eq(_T_11874, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_11876 = and(_T_11873, _T_11875) @[ifu_bp_ctl.scala 443:22] - node _T_11877 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11878 = eq(_T_11877, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_11879 = or(_T_11878, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11880 = and(_T_11876, _T_11879) @[ifu_bp_ctl.scala 443:87] - node _T_11881 = or(_T_11872, _T_11880) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][2][9] <= _T_11881 @[ifu_bp_ctl.scala 442:27] - node _T_11882 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11883 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11884 = eq(_T_11883, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_11885 = and(_T_11882, _T_11884) @[ifu_bp_ctl.scala 442:45] - node _T_11886 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11887 = eq(_T_11886, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_11888 = or(_T_11887, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11889 = and(_T_11885, _T_11888) @[ifu_bp_ctl.scala 442:110] - node _T_11890 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11891 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11892 = eq(_T_11891, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_11893 = and(_T_11890, _T_11892) @[ifu_bp_ctl.scala 443:22] - node _T_11894 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11895 = eq(_T_11894, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_11896 = or(_T_11895, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11897 = and(_T_11893, _T_11896) @[ifu_bp_ctl.scala 443:87] - node _T_11898 = or(_T_11889, _T_11897) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][2][10] <= _T_11898 @[ifu_bp_ctl.scala 442:27] - node _T_11899 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11900 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11901 = eq(_T_11900, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_11902 = and(_T_11899, _T_11901) @[ifu_bp_ctl.scala 442:45] - node _T_11903 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11904 = eq(_T_11903, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_11905 = or(_T_11904, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11906 = and(_T_11902, _T_11905) @[ifu_bp_ctl.scala 442:110] - node _T_11907 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11908 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11909 = eq(_T_11908, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_11910 = and(_T_11907, _T_11909) @[ifu_bp_ctl.scala 443:22] - node _T_11911 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11912 = eq(_T_11911, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_11913 = or(_T_11912, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11914 = and(_T_11910, _T_11913) @[ifu_bp_ctl.scala 443:87] - node _T_11915 = or(_T_11906, _T_11914) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][2][11] <= _T_11915 @[ifu_bp_ctl.scala 442:27] - node _T_11916 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11917 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11918 = eq(_T_11917, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_11919 = and(_T_11916, _T_11918) @[ifu_bp_ctl.scala 442:45] - node _T_11920 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11921 = eq(_T_11920, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_11922 = or(_T_11921, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11923 = and(_T_11919, _T_11922) @[ifu_bp_ctl.scala 442:110] - node _T_11924 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11925 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11926 = eq(_T_11925, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_11927 = and(_T_11924, _T_11926) @[ifu_bp_ctl.scala 443:22] - node _T_11928 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11929 = eq(_T_11928, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_11930 = or(_T_11929, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11931 = and(_T_11927, _T_11930) @[ifu_bp_ctl.scala 443:87] - node _T_11932 = or(_T_11923, _T_11931) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][2][12] <= _T_11932 @[ifu_bp_ctl.scala 442:27] - node _T_11933 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11934 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11935 = eq(_T_11934, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_11936 = and(_T_11933, _T_11935) @[ifu_bp_ctl.scala 442:45] - node _T_11937 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11938 = eq(_T_11937, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_11939 = or(_T_11938, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11940 = and(_T_11936, _T_11939) @[ifu_bp_ctl.scala 442:110] - node _T_11941 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11942 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11943 = eq(_T_11942, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_11944 = and(_T_11941, _T_11943) @[ifu_bp_ctl.scala 443:22] - node _T_11945 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11946 = eq(_T_11945, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_11947 = or(_T_11946, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11948 = and(_T_11944, _T_11947) @[ifu_bp_ctl.scala 443:87] - node _T_11949 = or(_T_11940, _T_11948) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][2][13] <= _T_11949 @[ifu_bp_ctl.scala 442:27] - node _T_11950 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11951 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11952 = eq(_T_11951, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_11953 = and(_T_11950, _T_11952) @[ifu_bp_ctl.scala 442:45] - node _T_11954 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11955 = eq(_T_11954, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_11956 = or(_T_11955, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11957 = and(_T_11953, _T_11956) @[ifu_bp_ctl.scala 442:110] - node _T_11958 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11959 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11960 = eq(_T_11959, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_11961 = and(_T_11958, _T_11960) @[ifu_bp_ctl.scala 443:22] - node _T_11962 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11963 = eq(_T_11962, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_11964 = or(_T_11963, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11965 = and(_T_11961, _T_11964) @[ifu_bp_ctl.scala 443:87] - node _T_11966 = or(_T_11957, _T_11965) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][2][14] <= _T_11966 @[ifu_bp_ctl.scala 442:27] - node _T_11967 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11968 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11969 = eq(_T_11968, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_11970 = and(_T_11967, _T_11969) @[ifu_bp_ctl.scala 442:45] - node _T_11971 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11972 = eq(_T_11971, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_11973 = or(_T_11972, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11974 = and(_T_11970, _T_11973) @[ifu_bp_ctl.scala 442:110] - node _T_11975 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11976 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11977 = eq(_T_11976, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_11978 = and(_T_11975, _T_11977) @[ifu_bp_ctl.scala 443:22] - node _T_11979 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11980 = eq(_T_11979, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_11981 = or(_T_11980, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11982 = and(_T_11978, _T_11981) @[ifu_bp_ctl.scala 443:87] - node _T_11983 = or(_T_11974, _T_11982) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][2][15] <= _T_11983 @[ifu_bp_ctl.scala 442:27] - node _T_11984 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_11985 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_11986 = eq(_T_11985, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_11987 = and(_T_11984, _T_11986) @[ifu_bp_ctl.scala 442:45] - node _T_11988 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_11989 = eq(_T_11988, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_11990 = or(_T_11989, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_11991 = and(_T_11987, _T_11990) @[ifu_bp_ctl.scala 442:110] - node _T_11992 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_11993 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_11994 = eq(_T_11993, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_11995 = and(_T_11992, _T_11994) @[ifu_bp_ctl.scala 443:22] - node _T_11996 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_11997 = eq(_T_11996, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_11998 = or(_T_11997, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_11999 = and(_T_11995, _T_11998) @[ifu_bp_ctl.scala 443:87] - node _T_12000 = or(_T_11991, _T_11999) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][3][0] <= _T_12000 @[ifu_bp_ctl.scala 442:27] - node _T_12001 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12002 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12003 = eq(_T_12002, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_12004 = and(_T_12001, _T_12003) @[ifu_bp_ctl.scala 442:45] - node _T_12005 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12006 = eq(_T_12005, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_12007 = or(_T_12006, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12008 = and(_T_12004, _T_12007) @[ifu_bp_ctl.scala 442:110] - node _T_12009 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12010 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12011 = eq(_T_12010, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_12012 = and(_T_12009, _T_12011) @[ifu_bp_ctl.scala 443:22] - node _T_12013 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12014 = eq(_T_12013, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_12015 = or(_T_12014, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12016 = and(_T_12012, _T_12015) @[ifu_bp_ctl.scala 443:87] - node _T_12017 = or(_T_12008, _T_12016) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][3][1] <= _T_12017 @[ifu_bp_ctl.scala 442:27] - node _T_12018 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12019 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12020 = eq(_T_12019, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_12021 = and(_T_12018, _T_12020) @[ifu_bp_ctl.scala 442:45] - node _T_12022 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12023 = eq(_T_12022, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_12024 = or(_T_12023, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12025 = and(_T_12021, _T_12024) @[ifu_bp_ctl.scala 442:110] - node _T_12026 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12027 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12028 = eq(_T_12027, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_12029 = and(_T_12026, _T_12028) @[ifu_bp_ctl.scala 443:22] - node _T_12030 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12031 = eq(_T_12030, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_12032 = or(_T_12031, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12033 = and(_T_12029, _T_12032) @[ifu_bp_ctl.scala 443:87] - node _T_12034 = or(_T_12025, _T_12033) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][3][2] <= _T_12034 @[ifu_bp_ctl.scala 442:27] - node _T_12035 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12036 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12037 = eq(_T_12036, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_12038 = and(_T_12035, _T_12037) @[ifu_bp_ctl.scala 442:45] - node _T_12039 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12040 = eq(_T_12039, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_12041 = or(_T_12040, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12042 = and(_T_12038, _T_12041) @[ifu_bp_ctl.scala 442:110] - node _T_12043 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12044 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12045 = eq(_T_12044, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_12046 = and(_T_12043, _T_12045) @[ifu_bp_ctl.scala 443:22] - node _T_12047 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12048 = eq(_T_12047, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_12049 = or(_T_12048, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12050 = and(_T_12046, _T_12049) @[ifu_bp_ctl.scala 443:87] - node _T_12051 = or(_T_12042, _T_12050) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][3][3] <= _T_12051 @[ifu_bp_ctl.scala 442:27] - node _T_12052 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12053 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12054 = eq(_T_12053, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_12055 = and(_T_12052, _T_12054) @[ifu_bp_ctl.scala 442:45] - node _T_12056 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12057 = eq(_T_12056, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_12058 = or(_T_12057, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12059 = and(_T_12055, _T_12058) @[ifu_bp_ctl.scala 442:110] - node _T_12060 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12061 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12062 = eq(_T_12061, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_12063 = and(_T_12060, _T_12062) @[ifu_bp_ctl.scala 443:22] - node _T_12064 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12065 = eq(_T_12064, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_12066 = or(_T_12065, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12067 = and(_T_12063, _T_12066) @[ifu_bp_ctl.scala 443:87] - node _T_12068 = or(_T_12059, _T_12067) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][3][4] <= _T_12068 @[ifu_bp_ctl.scala 442:27] - node _T_12069 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12070 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12071 = eq(_T_12070, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_12072 = and(_T_12069, _T_12071) @[ifu_bp_ctl.scala 442:45] - node _T_12073 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12074 = eq(_T_12073, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_12075 = or(_T_12074, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12076 = and(_T_12072, _T_12075) @[ifu_bp_ctl.scala 442:110] - node _T_12077 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12078 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12079 = eq(_T_12078, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_12080 = and(_T_12077, _T_12079) @[ifu_bp_ctl.scala 443:22] - node _T_12081 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12082 = eq(_T_12081, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_12083 = or(_T_12082, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12084 = and(_T_12080, _T_12083) @[ifu_bp_ctl.scala 443:87] - node _T_12085 = or(_T_12076, _T_12084) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][3][5] <= _T_12085 @[ifu_bp_ctl.scala 442:27] - node _T_12086 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12087 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12088 = eq(_T_12087, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_12089 = and(_T_12086, _T_12088) @[ifu_bp_ctl.scala 442:45] - node _T_12090 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12091 = eq(_T_12090, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_12092 = or(_T_12091, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12093 = and(_T_12089, _T_12092) @[ifu_bp_ctl.scala 442:110] - node _T_12094 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12095 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12096 = eq(_T_12095, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_12097 = and(_T_12094, _T_12096) @[ifu_bp_ctl.scala 443:22] - node _T_12098 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12099 = eq(_T_12098, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_12100 = or(_T_12099, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12101 = and(_T_12097, _T_12100) @[ifu_bp_ctl.scala 443:87] - node _T_12102 = or(_T_12093, _T_12101) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][3][6] <= _T_12102 @[ifu_bp_ctl.scala 442:27] - node _T_12103 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12104 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12105 = eq(_T_12104, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_12106 = and(_T_12103, _T_12105) @[ifu_bp_ctl.scala 442:45] - node _T_12107 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12108 = eq(_T_12107, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_12109 = or(_T_12108, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12110 = and(_T_12106, _T_12109) @[ifu_bp_ctl.scala 442:110] - node _T_12111 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12112 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12113 = eq(_T_12112, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_12114 = and(_T_12111, _T_12113) @[ifu_bp_ctl.scala 443:22] - node _T_12115 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12116 = eq(_T_12115, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_12117 = or(_T_12116, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12118 = and(_T_12114, _T_12117) @[ifu_bp_ctl.scala 443:87] - node _T_12119 = or(_T_12110, _T_12118) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][3][7] <= _T_12119 @[ifu_bp_ctl.scala 442:27] - node _T_12120 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12121 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12122 = eq(_T_12121, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_12123 = and(_T_12120, _T_12122) @[ifu_bp_ctl.scala 442:45] - node _T_12124 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12125 = eq(_T_12124, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_12126 = or(_T_12125, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12127 = and(_T_12123, _T_12126) @[ifu_bp_ctl.scala 442:110] - node _T_12128 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12129 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12130 = eq(_T_12129, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_12131 = and(_T_12128, _T_12130) @[ifu_bp_ctl.scala 443:22] - node _T_12132 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12133 = eq(_T_12132, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_12134 = or(_T_12133, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12135 = and(_T_12131, _T_12134) @[ifu_bp_ctl.scala 443:87] - node _T_12136 = or(_T_12127, _T_12135) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][3][8] <= _T_12136 @[ifu_bp_ctl.scala 442:27] - node _T_12137 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12138 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12139 = eq(_T_12138, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_12140 = and(_T_12137, _T_12139) @[ifu_bp_ctl.scala 442:45] - node _T_12141 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12142 = eq(_T_12141, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_12143 = or(_T_12142, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12144 = and(_T_12140, _T_12143) @[ifu_bp_ctl.scala 442:110] - node _T_12145 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12146 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12147 = eq(_T_12146, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_12148 = and(_T_12145, _T_12147) @[ifu_bp_ctl.scala 443:22] - node _T_12149 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12150 = eq(_T_12149, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_12151 = or(_T_12150, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12152 = and(_T_12148, _T_12151) @[ifu_bp_ctl.scala 443:87] - node _T_12153 = or(_T_12144, _T_12152) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][3][9] <= _T_12153 @[ifu_bp_ctl.scala 442:27] - node _T_12154 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12155 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12156 = eq(_T_12155, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_12157 = and(_T_12154, _T_12156) @[ifu_bp_ctl.scala 442:45] - node _T_12158 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12159 = eq(_T_12158, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_12160 = or(_T_12159, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12161 = and(_T_12157, _T_12160) @[ifu_bp_ctl.scala 442:110] - node _T_12162 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12163 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12164 = eq(_T_12163, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_12165 = and(_T_12162, _T_12164) @[ifu_bp_ctl.scala 443:22] - node _T_12166 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12167 = eq(_T_12166, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_12168 = or(_T_12167, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12169 = and(_T_12165, _T_12168) @[ifu_bp_ctl.scala 443:87] - node _T_12170 = or(_T_12161, _T_12169) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][3][10] <= _T_12170 @[ifu_bp_ctl.scala 442:27] - node _T_12171 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12172 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12173 = eq(_T_12172, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_12174 = and(_T_12171, _T_12173) @[ifu_bp_ctl.scala 442:45] - node _T_12175 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12176 = eq(_T_12175, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_12177 = or(_T_12176, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12178 = and(_T_12174, _T_12177) @[ifu_bp_ctl.scala 442:110] - node _T_12179 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12180 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12181 = eq(_T_12180, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_12182 = and(_T_12179, _T_12181) @[ifu_bp_ctl.scala 443:22] - node _T_12183 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12184 = eq(_T_12183, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_12185 = or(_T_12184, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12186 = and(_T_12182, _T_12185) @[ifu_bp_ctl.scala 443:87] - node _T_12187 = or(_T_12178, _T_12186) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][3][11] <= _T_12187 @[ifu_bp_ctl.scala 442:27] - node _T_12188 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12189 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12190 = eq(_T_12189, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_12191 = and(_T_12188, _T_12190) @[ifu_bp_ctl.scala 442:45] - node _T_12192 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12193 = eq(_T_12192, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_12194 = or(_T_12193, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12195 = and(_T_12191, _T_12194) @[ifu_bp_ctl.scala 442:110] - node _T_12196 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12197 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12198 = eq(_T_12197, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_12199 = and(_T_12196, _T_12198) @[ifu_bp_ctl.scala 443:22] - node _T_12200 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12201 = eq(_T_12200, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_12202 = or(_T_12201, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12203 = and(_T_12199, _T_12202) @[ifu_bp_ctl.scala 443:87] - node _T_12204 = or(_T_12195, _T_12203) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][3][12] <= _T_12204 @[ifu_bp_ctl.scala 442:27] - node _T_12205 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12206 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12207 = eq(_T_12206, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_12208 = and(_T_12205, _T_12207) @[ifu_bp_ctl.scala 442:45] - node _T_12209 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12210 = eq(_T_12209, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_12211 = or(_T_12210, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12212 = and(_T_12208, _T_12211) @[ifu_bp_ctl.scala 442:110] - node _T_12213 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12214 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12215 = eq(_T_12214, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_12216 = and(_T_12213, _T_12215) @[ifu_bp_ctl.scala 443:22] - node _T_12217 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12218 = eq(_T_12217, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_12219 = or(_T_12218, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12220 = and(_T_12216, _T_12219) @[ifu_bp_ctl.scala 443:87] - node _T_12221 = or(_T_12212, _T_12220) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][3][13] <= _T_12221 @[ifu_bp_ctl.scala 442:27] - node _T_12222 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12223 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12224 = eq(_T_12223, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_12225 = and(_T_12222, _T_12224) @[ifu_bp_ctl.scala 442:45] - node _T_12226 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12227 = eq(_T_12226, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_12228 = or(_T_12227, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12229 = and(_T_12225, _T_12228) @[ifu_bp_ctl.scala 442:110] - node _T_12230 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12231 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12232 = eq(_T_12231, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_12233 = and(_T_12230, _T_12232) @[ifu_bp_ctl.scala 443:22] - node _T_12234 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12235 = eq(_T_12234, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_12236 = or(_T_12235, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12237 = and(_T_12233, _T_12236) @[ifu_bp_ctl.scala 443:87] - node _T_12238 = or(_T_12229, _T_12237) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][3][14] <= _T_12238 @[ifu_bp_ctl.scala 442:27] - node _T_12239 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12240 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12241 = eq(_T_12240, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_12242 = and(_T_12239, _T_12241) @[ifu_bp_ctl.scala 442:45] - node _T_12243 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12244 = eq(_T_12243, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_12245 = or(_T_12244, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12246 = and(_T_12242, _T_12245) @[ifu_bp_ctl.scala 442:110] - node _T_12247 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12248 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12249 = eq(_T_12248, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_12250 = and(_T_12247, _T_12249) @[ifu_bp_ctl.scala 443:22] - node _T_12251 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12252 = eq(_T_12251, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_12253 = or(_T_12252, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12254 = and(_T_12250, _T_12253) @[ifu_bp_ctl.scala 443:87] - node _T_12255 = or(_T_12246, _T_12254) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][3][15] <= _T_12255 @[ifu_bp_ctl.scala 442:27] - node _T_12256 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12257 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12258 = eq(_T_12257, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_12259 = and(_T_12256, _T_12258) @[ifu_bp_ctl.scala 442:45] - node _T_12260 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12261 = eq(_T_12260, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_12262 = or(_T_12261, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12263 = and(_T_12259, _T_12262) @[ifu_bp_ctl.scala 442:110] - node _T_12264 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12265 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12266 = eq(_T_12265, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_12267 = and(_T_12264, _T_12266) @[ifu_bp_ctl.scala 443:22] - node _T_12268 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12269 = eq(_T_12268, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_12270 = or(_T_12269, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12271 = and(_T_12267, _T_12270) @[ifu_bp_ctl.scala 443:87] - node _T_12272 = or(_T_12263, _T_12271) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][4][0] <= _T_12272 @[ifu_bp_ctl.scala 442:27] - node _T_12273 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12274 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12275 = eq(_T_12274, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_12276 = and(_T_12273, _T_12275) @[ifu_bp_ctl.scala 442:45] - node _T_12277 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12278 = eq(_T_12277, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_12279 = or(_T_12278, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12280 = and(_T_12276, _T_12279) @[ifu_bp_ctl.scala 442:110] - node _T_12281 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12282 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12283 = eq(_T_12282, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_12284 = and(_T_12281, _T_12283) @[ifu_bp_ctl.scala 443:22] - node _T_12285 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12286 = eq(_T_12285, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_12287 = or(_T_12286, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12288 = and(_T_12284, _T_12287) @[ifu_bp_ctl.scala 443:87] - node _T_12289 = or(_T_12280, _T_12288) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][4][1] <= _T_12289 @[ifu_bp_ctl.scala 442:27] - node _T_12290 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12291 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12292 = eq(_T_12291, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_12293 = and(_T_12290, _T_12292) @[ifu_bp_ctl.scala 442:45] - node _T_12294 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12295 = eq(_T_12294, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_12296 = or(_T_12295, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12297 = and(_T_12293, _T_12296) @[ifu_bp_ctl.scala 442:110] - node _T_12298 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12299 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12300 = eq(_T_12299, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_12301 = and(_T_12298, _T_12300) @[ifu_bp_ctl.scala 443:22] - node _T_12302 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12303 = eq(_T_12302, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_12304 = or(_T_12303, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12305 = and(_T_12301, _T_12304) @[ifu_bp_ctl.scala 443:87] - node _T_12306 = or(_T_12297, _T_12305) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][4][2] <= _T_12306 @[ifu_bp_ctl.scala 442:27] - node _T_12307 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12308 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12309 = eq(_T_12308, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_12310 = and(_T_12307, _T_12309) @[ifu_bp_ctl.scala 442:45] - node _T_12311 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12312 = eq(_T_12311, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_12313 = or(_T_12312, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12314 = and(_T_12310, _T_12313) @[ifu_bp_ctl.scala 442:110] - node _T_12315 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12316 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12317 = eq(_T_12316, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_12318 = and(_T_12315, _T_12317) @[ifu_bp_ctl.scala 443:22] - node _T_12319 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12320 = eq(_T_12319, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_12321 = or(_T_12320, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12322 = and(_T_12318, _T_12321) @[ifu_bp_ctl.scala 443:87] - node _T_12323 = or(_T_12314, _T_12322) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][4][3] <= _T_12323 @[ifu_bp_ctl.scala 442:27] - node _T_12324 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12325 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12326 = eq(_T_12325, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_12327 = and(_T_12324, _T_12326) @[ifu_bp_ctl.scala 442:45] - node _T_12328 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12329 = eq(_T_12328, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_12330 = or(_T_12329, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12331 = and(_T_12327, _T_12330) @[ifu_bp_ctl.scala 442:110] - node _T_12332 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12333 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12334 = eq(_T_12333, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_12335 = and(_T_12332, _T_12334) @[ifu_bp_ctl.scala 443:22] - node _T_12336 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12337 = eq(_T_12336, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_12338 = or(_T_12337, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12339 = and(_T_12335, _T_12338) @[ifu_bp_ctl.scala 443:87] - node _T_12340 = or(_T_12331, _T_12339) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][4][4] <= _T_12340 @[ifu_bp_ctl.scala 442:27] - node _T_12341 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12342 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12343 = eq(_T_12342, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_12344 = and(_T_12341, _T_12343) @[ifu_bp_ctl.scala 442:45] - node _T_12345 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12346 = eq(_T_12345, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_12347 = or(_T_12346, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12348 = and(_T_12344, _T_12347) @[ifu_bp_ctl.scala 442:110] - node _T_12349 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12350 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12351 = eq(_T_12350, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_12352 = and(_T_12349, _T_12351) @[ifu_bp_ctl.scala 443:22] - node _T_12353 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12354 = eq(_T_12353, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_12355 = or(_T_12354, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12356 = and(_T_12352, _T_12355) @[ifu_bp_ctl.scala 443:87] - node _T_12357 = or(_T_12348, _T_12356) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][4][5] <= _T_12357 @[ifu_bp_ctl.scala 442:27] - node _T_12358 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12359 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12360 = eq(_T_12359, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_12361 = and(_T_12358, _T_12360) @[ifu_bp_ctl.scala 442:45] - node _T_12362 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12363 = eq(_T_12362, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_12364 = or(_T_12363, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12365 = and(_T_12361, _T_12364) @[ifu_bp_ctl.scala 442:110] - node _T_12366 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12367 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12368 = eq(_T_12367, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_12369 = and(_T_12366, _T_12368) @[ifu_bp_ctl.scala 443:22] - node _T_12370 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12371 = eq(_T_12370, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_12372 = or(_T_12371, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12373 = and(_T_12369, _T_12372) @[ifu_bp_ctl.scala 443:87] - node _T_12374 = or(_T_12365, _T_12373) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][4][6] <= _T_12374 @[ifu_bp_ctl.scala 442:27] - node _T_12375 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12376 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12377 = eq(_T_12376, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_12378 = and(_T_12375, _T_12377) @[ifu_bp_ctl.scala 442:45] - node _T_12379 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12380 = eq(_T_12379, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_12381 = or(_T_12380, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12382 = and(_T_12378, _T_12381) @[ifu_bp_ctl.scala 442:110] - node _T_12383 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12384 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12385 = eq(_T_12384, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_12386 = and(_T_12383, _T_12385) @[ifu_bp_ctl.scala 443:22] - node _T_12387 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12388 = eq(_T_12387, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_12389 = or(_T_12388, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12390 = and(_T_12386, _T_12389) @[ifu_bp_ctl.scala 443:87] - node _T_12391 = or(_T_12382, _T_12390) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][4][7] <= _T_12391 @[ifu_bp_ctl.scala 442:27] - node _T_12392 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12393 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12394 = eq(_T_12393, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_12395 = and(_T_12392, _T_12394) @[ifu_bp_ctl.scala 442:45] - node _T_12396 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12397 = eq(_T_12396, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_12398 = or(_T_12397, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12399 = and(_T_12395, _T_12398) @[ifu_bp_ctl.scala 442:110] - node _T_12400 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12401 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12402 = eq(_T_12401, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_12403 = and(_T_12400, _T_12402) @[ifu_bp_ctl.scala 443:22] - node _T_12404 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12405 = eq(_T_12404, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_12406 = or(_T_12405, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12407 = and(_T_12403, _T_12406) @[ifu_bp_ctl.scala 443:87] - node _T_12408 = or(_T_12399, _T_12407) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][4][8] <= _T_12408 @[ifu_bp_ctl.scala 442:27] - node _T_12409 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12410 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12411 = eq(_T_12410, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_12412 = and(_T_12409, _T_12411) @[ifu_bp_ctl.scala 442:45] - node _T_12413 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12414 = eq(_T_12413, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_12415 = or(_T_12414, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12416 = and(_T_12412, _T_12415) @[ifu_bp_ctl.scala 442:110] - node _T_12417 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12418 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12419 = eq(_T_12418, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_12420 = and(_T_12417, _T_12419) @[ifu_bp_ctl.scala 443:22] - node _T_12421 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12422 = eq(_T_12421, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_12423 = or(_T_12422, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12424 = and(_T_12420, _T_12423) @[ifu_bp_ctl.scala 443:87] - node _T_12425 = or(_T_12416, _T_12424) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][4][9] <= _T_12425 @[ifu_bp_ctl.scala 442:27] - node _T_12426 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12427 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12428 = eq(_T_12427, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_12429 = and(_T_12426, _T_12428) @[ifu_bp_ctl.scala 442:45] - node _T_12430 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12431 = eq(_T_12430, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_12432 = or(_T_12431, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12433 = and(_T_12429, _T_12432) @[ifu_bp_ctl.scala 442:110] - node _T_12434 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12435 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12436 = eq(_T_12435, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_12437 = and(_T_12434, _T_12436) @[ifu_bp_ctl.scala 443:22] - node _T_12438 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12439 = eq(_T_12438, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_12440 = or(_T_12439, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12441 = and(_T_12437, _T_12440) @[ifu_bp_ctl.scala 443:87] - node _T_12442 = or(_T_12433, _T_12441) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][4][10] <= _T_12442 @[ifu_bp_ctl.scala 442:27] - node _T_12443 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12444 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12445 = eq(_T_12444, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_12446 = and(_T_12443, _T_12445) @[ifu_bp_ctl.scala 442:45] - node _T_12447 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12448 = eq(_T_12447, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_12449 = or(_T_12448, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12450 = and(_T_12446, _T_12449) @[ifu_bp_ctl.scala 442:110] - node _T_12451 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12452 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12453 = eq(_T_12452, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_12454 = and(_T_12451, _T_12453) @[ifu_bp_ctl.scala 443:22] - node _T_12455 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12456 = eq(_T_12455, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_12457 = or(_T_12456, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12458 = and(_T_12454, _T_12457) @[ifu_bp_ctl.scala 443:87] - node _T_12459 = or(_T_12450, _T_12458) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][4][11] <= _T_12459 @[ifu_bp_ctl.scala 442:27] - node _T_12460 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12461 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12462 = eq(_T_12461, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_12463 = and(_T_12460, _T_12462) @[ifu_bp_ctl.scala 442:45] - node _T_12464 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12465 = eq(_T_12464, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_12466 = or(_T_12465, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12467 = and(_T_12463, _T_12466) @[ifu_bp_ctl.scala 442:110] - node _T_12468 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12469 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12470 = eq(_T_12469, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_12471 = and(_T_12468, _T_12470) @[ifu_bp_ctl.scala 443:22] - node _T_12472 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12473 = eq(_T_12472, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_12474 = or(_T_12473, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12475 = and(_T_12471, _T_12474) @[ifu_bp_ctl.scala 443:87] - node _T_12476 = or(_T_12467, _T_12475) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][4][12] <= _T_12476 @[ifu_bp_ctl.scala 442:27] - node _T_12477 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12478 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12479 = eq(_T_12478, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_12480 = and(_T_12477, _T_12479) @[ifu_bp_ctl.scala 442:45] - node _T_12481 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12482 = eq(_T_12481, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_12483 = or(_T_12482, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12484 = and(_T_12480, _T_12483) @[ifu_bp_ctl.scala 442:110] - node _T_12485 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12486 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12487 = eq(_T_12486, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_12488 = and(_T_12485, _T_12487) @[ifu_bp_ctl.scala 443:22] - node _T_12489 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12490 = eq(_T_12489, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_12491 = or(_T_12490, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12492 = and(_T_12488, _T_12491) @[ifu_bp_ctl.scala 443:87] - node _T_12493 = or(_T_12484, _T_12492) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][4][13] <= _T_12493 @[ifu_bp_ctl.scala 442:27] - node _T_12494 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12495 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12496 = eq(_T_12495, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_12497 = and(_T_12494, _T_12496) @[ifu_bp_ctl.scala 442:45] - node _T_12498 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12499 = eq(_T_12498, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_12500 = or(_T_12499, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12501 = and(_T_12497, _T_12500) @[ifu_bp_ctl.scala 442:110] - node _T_12502 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12503 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12504 = eq(_T_12503, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_12505 = and(_T_12502, _T_12504) @[ifu_bp_ctl.scala 443:22] - node _T_12506 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12507 = eq(_T_12506, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_12508 = or(_T_12507, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12509 = and(_T_12505, _T_12508) @[ifu_bp_ctl.scala 443:87] - node _T_12510 = or(_T_12501, _T_12509) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][4][14] <= _T_12510 @[ifu_bp_ctl.scala 442:27] - node _T_12511 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12512 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12513 = eq(_T_12512, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_12514 = and(_T_12511, _T_12513) @[ifu_bp_ctl.scala 442:45] - node _T_12515 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12516 = eq(_T_12515, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_12517 = or(_T_12516, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12518 = and(_T_12514, _T_12517) @[ifu_bp_ctl.scala 442:110] - node _T_12519 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12520 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12521 = eq(_T_12520, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_12522 = and(_T_12519, _T_12521) @[ifu_bp_ctl.scala 443:22] - node _T_12523 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12524 = eq(_T_12523, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_12525 = or(_T_12524, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12526 = and(_T_12522, _T_12525) @[ifu_bp_ctl.scala 443:87] - node _T_12527 = or(_T_12518, _T_12526) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][4][15] <= _T_12527 @[ifu_bp_ctl.scala 442:27] - node _T_12528 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12529 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12530 = eq(_T_12529, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_12531 = and(_T_12528, _T_12530) @[ifu_bp_ctl.scala 442:45] - node _T_12532 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12533 = eq(_T_12532, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_12534 = or(_T_12533, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12535 = and(_T_12531, _T_12534) @[ifu_bp_ctl.scala 442:110] - node _T_12536 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12537 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12538 = eq(_T_12537, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_12539 = and(_T_12536, _T_12538) @[ifu_bp_ctl.scala 443:22] - node _T_12540 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12541 = eq(_T_12540, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_12542 = or(_T_12541, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12543 = and(_T_12539, _T_12542) @[ifu_bp_ctl.scala 443:87] - node _T_12544 = or(_T_12535, _T_12543) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][5][0] <= _T_12544 @[ifu_bp_ctl.scala 442:27] - node _T_12545 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12546 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12547 = eq(_T_12546, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_12548 = and(_T_12545, _T_12547) @[ifu_bp_ctl.scala 442:45] - node _T_12549 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12550 = eq(_T_12549, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_12551 = or(_T_12550, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12552 = and(_T_12548, _T_12551) @[ifu_bp_ctl.scala 442:110] - node _T_12553 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12554 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12555 = eq(_T_12554, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_12556 = and(_T_12553, _T_12555) @[ifu_bp_ctl.scala 443:22] - node _T_12557 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12558 = eq(_T_12557, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_12559 = or(_T_12558, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12560 = and(_T_12556, _T_12559) @[ifu_bp_ctl.scala 443:87] - node _T_12561 = or(_T_12552, _T_12560) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][5][1] <= _T_12561 @[ifu_bp_ctl.scala 442:27] - node _T_12562 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12563 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12564 = eq(_T_12563, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_12565 = and(_T_12562, _T_12564) @[ifu_bp_ctl.scala 442:45] - node _T_12566 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12567 = eq(_T_12566, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_12568 = or(_T_12567, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12569 = and(_T_12565, _T_12568) @[ifu_bp_ctl.scala 442:110] - node _T_12570 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12571 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12572 = eq(_T_12571, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_12573 = and(_T_12570, _T_12572) @[ifu_bp_ctl.scala 443:22] - node _T_12574 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12575 = eq(_T_12574, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_12576 = or(_T_12575, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12577 = and(_T_12573, _T_12576) @[ifu_bp_ctl.scala 443:87] - node _T_12578 = or(_T_12569, _T_12577) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][5][2] <= _T_12578 @[ifu_bp_ctl.scala 442:27] - node _T_12579 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12580 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12581 = eq(_T_12580, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_12582 = and(_T_12579, _T_12581) @[ifu_bp_ctl.scala 442:45] - node _T_12583 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12584 = eq(_T_12583, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_12585 = or(_T_12584, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12586 = and(_T_12582, _T_12585) @[ifu_bp_ctl.scala 442:110] - node _T_12587 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12588 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12589 = eq(_T_12588, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_12590 = and(_T_12587, _T_12589) @[ifu_bp_ctl.scala 443:22] - node _T_12591 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12592 = eq(_T_12591, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_12593 = or(_T_12592, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12594 = and(_T_12590, _T_12593) @[ifu_bp_ctl.scala 443:87] - node _T_12595 = or(_T_12586, _T_12594) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][5][3] <= _T_12595 @[ifu_bp_ctl.scala 442:27] - node _T_12596 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12597 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12598 = eq(_T_12597, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_12599 = and(_T_12596, _T_12598) @[ifu_bp_ctl.scala 442:45] - node _T_12600 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12601 = eq(_T_12600, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_12602 = or(_T_12601, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12603 = and(_T_12599, _T_12602) @[ifu_bp_ctl.scala 442:110] - node _T_12604 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12605 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12606 = eq(_T_12605, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_12607 = and(_T_12604, _T_12606) @[ifu_bp_ctl.scala 443:22] - node _T_12608 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12609 = eq(_T_12608, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_12610 = or(_T_12609, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12611 = and(_T_12607, _T_12610) @[ifu_bp_ctl.scala 443:87] - node _T_12612 = or(_T_12603, _T_12611) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][5][4] <= _T_12612 @[ifu_bp_ctl.scala 442:27] - node _T_12613 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12614 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12615 = eq(_T_12614, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_12616 = and(_T_12613, _T_12615) @[ifu_bp_ctl.scala 442:45] - node _T_12617 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12618 = eq(_T_12617, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_12619 = or(_T_12618, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12620 = and(_T_12616, _T_12619) @[ifu_bp_ctl.scala 442:110] - node _T_12621 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12622 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12623 = eq(_T_12622, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_12624 = and(_T_12621, _T_12623) @[ifu_bp_ctl.scala 443:22] - node _T_12625 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12626 = eq(_T_12625, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_12627 = or(_T_12626, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12628 = and(_T_12624, _T_12627) @[ifu_bp_ctl.scala 443:87] - node _T_12629 = or(_T_12620, _T_12628) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][5][5] <= _T_12629 @[ifu_bp_ctl.scala 442:27] - node _T_12630 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12631 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12632 = eq(_T_12631, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_12633 = and(_T_12630, _T_12632) @[ifu_bp_ctl.scala 442:45] - node _T_12634 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12635 = eq(_T_12634, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_12636 = or(_T_12635, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12637 = and(_T_12633, _T_12636) @[ifu_bp_ctl.scala 442:110] - node _T_12638 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12639 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12640 = eq(_T_12639, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_12641 = and(_T_12638, _T_12640) @[ifu_bp_ctl.scala 443:22] - node _T_12642 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12643 = eq(_T_12642, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_12644 = or(_T_12643, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12645 = and(_T_12641, _T_12644) @[ifu_bp_ctl.scala 443:87] - node _T_12646 = or(_T_12637, _T_12645) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][5][6] <= _T_12646 @[ifu_bp_ctl.scala 442:27] - node _T_12647 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12648 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12649 = eq(_T_12648, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_12650 = and(_T_12647, _T_12649) @[ifu_bp_ctl.scala 442:45] - node _T_12651 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12652 = eq(_T_12651, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_12653 = or(_T_12652, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12654 = and(_T_12650, _T_12653) @[ifu_bp_ctl.scala 442:110] - node _T_12655 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12656 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12657 = eq(_T_12656, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_12658 = and(_T_12655, _T_12657) @[ifu_bp_ctl.scala 443:22] - node _T_12659 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12660 = eq(_T_12659, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_12661 = or(_T_12660, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12662 = and(_T_12658, _T_12661) @[ifu_bp_ctl.scala 443:87] - node _T_12663 = or(_T_12654, _T_12662) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][5][7] <= _T_12663 @[ifu_bp_ctl.scala 442:27] - node _T_12664 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12665 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12666 = eq(_T_12665, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_12667 = and(_T_12664, _T_12666) @[ifu_bp_ctl.scala 442:45] - node _T_12668 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12669 = eq(_T_12668, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_12670 = or(_T_12669, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12671 = and(_T_12667, _T_12670) @[ifu_bp_ctl.scala 442:110] - node _T_12672 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12673 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12674 = eq(_T_12673, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_12675 = and(_T_12672, _T_12674) @[ifu_bp_ctl.scala 443:22] - node _T_12676 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12677 = eq(_T_12676, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_12678 = or(_T_12677, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12679 = and(_T_12675, _T_12678) @[ifu_bp_ctl.scala 443:87] - node _T_12680 = or(_T_12671, _T_12679) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][5][8] <= _T_12680 @[ifu_bp_ctl.scala 442:27] - node _T_12681 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12682 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12683 = eq(_T_12682, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_12684 = and(_T_12681, _T_12683) @[ifu_bp_ctl.scala 442:45] - node _T_12685 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12686 = eq(_T_12685, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_12687 = or(_T_12686, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12688 = and(_T_12684, _T_12687) @[ifu_bp_ctl.scala 442:110] - node _T_12689 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12690 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12691 = eq(_T_12690, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_12692 = and(_T_12689, _T_12691) @[ifu_bp_ctl.scala 443:22] - node _T_12693 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12694 = eq(_T_12693, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_12695 = or(_T_12694, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12696 = and(_T_12692, _T_12695) @[ifu_bp_ctl.scala 443:87] - node _T_12697 = or(_T_12688, _T_12696) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][5][9] <= _T_12697 @[ifu_bp_ctl.scala 442:27] - node _T_12698 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12699 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12700 = eq(_T_12699, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_12701 = and(_T_12698, _T_12700) @[ifu_bp_ctl.scala 442:45] - node _T_12702 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12703 = eq(_T_12702, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_12704 = or(_T_12703, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12705 = and(_T_12701, _T_12704) @[ifu_bp_ctl.scala 442:110] - node _T_12706 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12707 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12708 = eq(_T_12707, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_12709 = and(_T_12706, _T_12708) @[ifu_bp_ctl.scala 443:22] - node _T_12710 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12711 = eq(_T_12710, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_12712 = or(_T_12711, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12713 = and(_T_12709, _T_12712) @[ifu_bp_ctl.scala 443:87] - node _T_12714 = or(_T_12705, _T_12713) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][5][10] <= _T_12714 @[ifu_bp_ctl.scala 442:27] - node _T_12715 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12716 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12717 = eq(_T_12716, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_12718 = and(_T_12715, _T_12717) @[ifu_bp_ctl.scala 442:45] - node _T_12719 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12720 = eq(_T_12719, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_12721 = or(_T_12720, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12722 = and(_T_12718, _T_12721) @[ifu_bp_ctl.scala 442:110] - node _T_12723 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12724 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12725 = eq(_T_12724, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_12726 = and(_T_12723, _T_12725) @[ifu_bp_ctl.scala 443:22] - node _T_12727 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12728 = eq(_T_12727, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_12729 = or(_T_12728, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12730 = and(_T_12726, _T_12729) @[ifu_bp_ctl.scala 443:87] - node _T_12731 = or(_T_12722, _T_12730) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][5][11] <= _T_12731 @[ifu_bp_ctl.scala 442:27] - node _T_12732 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12733 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12734 = eq(_T_12733, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_12735 = and(_T_12732, _T_12734) @[ifu_bp_ctl.scala 442:45] - node _T_12736 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12737 = eq(_T_12736, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_12738 = or(_T_12737, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12739 = and(_T_12735, _T_12738) @[ifu_bp_ctl.scala 442:110] - node _T_12740 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12741 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12742 = eq(_T_12741, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_12743 = and(_T_12740, _T_12742) @[ifu_bp_ctl.scala 443:22] - node _T_12744 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12745 = eq(_T_12744, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_12746 = or(_T_12745, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12747 = and(_T_12743, _T_12746) @[ifu_bp_ctl.scala 443:87] - node _T_12748 = or(_T_12739, _T_12747) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][5][12] <= _T_12748 @[ifu_bp_ctl.scala 442:27] - node _T_12749 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12750 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12751 = eq(_T_12750, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_12752 = and(_T_12749, _T_12751) @[ifu_bp_ctl.scala 442:45] - node _T_12753 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12754 = eq(_T_12753, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_12755 = or(_T_12754, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12756 = and(_T_12752, _T_12755) @[ifu_bp_ctl.scala 442:110] - node _T_12757 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12758 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12759 = eq(_T_12758, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_12760 = and(_T_12757, _T_12759) @[ifu_bp_ctl.scala 443:22] - node _T_12761 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12762 = eq(_T_12761, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_12763 = or(_T_12762, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12764 = and(_T_12760, _T_12763) @[ifu_bp_ctl.scala 443:87] - node _T_12765 = or(_T_12756, _T_12764) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][5][13] <= _T_12765 @[ifu_bp_ctl.scala 442:27] - node _T_12766 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12767 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12768 = eq(_T_12767, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_12769 = and(_T_12766, _T_12768) @[ifu_bp_ctl.scala 442:45] - node _T_12770 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12771 = eq(_T_12770, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_12772 = or(_T_12771, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12773 = and(_T_12769, _T_12772) @[ifu_bp_ctl.scala 442:110] - node _T_12774 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12775 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12776 = eq(_T_12775, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_12777 = and(_T_12774, _T_12776) @[ifu_bp_ctl.scala 443:22] - node _T_12778 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12779 = eq(_T_12778, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_12780 = or(_T_12779, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12781 = and(_T_12777, _T_12780) @[ifu_bp_ctl.scala 443:87] - node _T_12782 = or(_T_12773, _T_12781) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][5][14] <= _T_12782 @[ifu_bp_ctl.scala 442:27] - node _T_12783 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12784 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12785 = eq(_T_12784, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_12786 = and(_T_12783, _T_12785) @[ifu_bp_ctl.scala 442:45] - node _T_12787 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12788 = eq(_T_12787, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_12789 = or(_T_12788, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12790 = and(_T_12786, _T_12789) @[ifu_bp_ctl.scala 442:110] - node _T_12791 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12792 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12793 = eq(_T_12792, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_12794 = and(_T_12791, _T_12793) @[ifu_bp_ctl.scala 443:22] - node _T_12795 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12796 = eq(_T_12795, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_12797 = or(_T_12796, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12798 = and(_T_12794, _T_12797) @[ifu_bp_ctl.scala 443:87] - node _T_12799 = or(_T_12790, _T_12798) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][5][15] <= _T_12799 @[ifu_bp_ctl.scala 442:27] - node _T_12800 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12801 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12802 = eq(_T_12801, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_12803 = and(_T_12800, _T_12802) @[ifu_bp_ctl.scala 442:45] - node _T_12804 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12805 = eq(_T_12804, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_12806 = or(_T_12805, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12807 = and(_T_12803, _T_12806) @[ifu_bp_ctl.scala 442:110] - node _T_12808 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12809 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12810 = eq(_T_12809, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_12811 = and(_T_12808, _T_12810) @[ifu_bp_ctl.scala 443:22] - node _T_12812 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12813 = eq(_T_12812, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_12814 = or(_T_12813, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12815 = and(_T_12811, _T_12814) @[ifu_bp_ctl.scala 443:87] - node _T_12816 = or(_T_12807, _T_12815) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][6][0] <= _T_12816 @[ifu_bp_ctl.scala 442:27] - node _T_12817 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12818 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12819 = eq(_T_12818, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_12820 = and(_T_12817, _T_12819) @[ifu_bp_ctl.scala 442:45] - node _T_12821 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12822 = eq(_T_12821, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_12823 = or(_T_12822, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12824 = and(_T_12820, _T_12823) @[ifu_bp_ctl.scala 442:110] - node _T_12825 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12826 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12827 = eq(_T_12826, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_12828 = and(_T_12825, _T_12827) @[ifu_bp_ctl.scala 443:22] - node _T_12829 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12830 = eq(_T_12829, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_12831 = or(_T_12830, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12832 = and(_T_12828, _T_12831) @[ifu_bp_ctl.scala 443:87] - node _T_12833 = or(_T_12824, _T_12832) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][6][1] <= _T_12833 @[ifu_bp_ctl.scala 442:27] - node _T_12834 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12835 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12836 = eq(_T_12835, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_12837 = and(_T_12834, _T_12836) @[ifu_bp_ctl.scala 442:45] - node _T_12838 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12839 = eq(_T_12838, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_12840 = or(_T_12839, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12841 = and(_T_12837, _T_12840) @[ifu_bp_ctl.scala 442:110] - node _T_12842 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12843 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12844 = eq(_T_12843, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_12845 = and(_T_12842, _T_12844) @[ifu_bp_ctl.scala 443:22] - node _T_12846 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12847 = eq(_T_12846, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_12848 = or(_T_12847, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12849 = and(_T_12845, _T_12848) @[ifu_bp_ctl.scala 443:87] - node _T_12850 = or(_T_12841, _T_12849) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][6][2] <= _T_12850 @[ifu_bp_ctl.scala 442:27] - node _T_12851 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12852 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12853 = eq(_T_12852, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_12854 = and(_T_12851, _T_12853) @[ifu_bp_ctl.scala 442:45] - node _T_12855 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12856 = eq(_T_12855, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_12857 = or(_T_12856, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12858 = and(_T_12854, _T_12857) @[ifu_bp_ctl.scala 442:110] - node _T_12859 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12860 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12861 = eq(_T_12860, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_12862 = and(_T_12859, _T_12861) @[ifu_bp_ctl.scala 443:22] - node _T_12863 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12864 = eq(_T_12863, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_12865 = or(_T_12864, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12866 = and(_T_12862, _T_12865) @[ifu_bp_ctl.scala 443:87] - node _T_12867 = or(_T_12858, _T_12866) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][6][3] <= _T_12867 @[ifu_bp_ctl.scala 442:27] - node _T_12868 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12869 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12870 = eq(_T_12869, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_12871 = and(_T_12868, _T_12870) @[ifu_bp_ctl.scala 442:45] - node _T_12872 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12873 = eq(_T_12872, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_12874 = or(_T_12873, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12875 = and(_T_12871, _T_12874) @[ifu_bp_ctl.scala 442:110] - node _T_12876 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12877 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12878 = eq(_T_12877, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_12879 = and(_T_12876, _T_12878) @[ifu_bp_ctl.scala 443:22] - node _T_12880 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12881 = eq(_T_12880, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_12882 = or(_T_12881, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12883 = and(_T_12879, _T_12882) @[ifu_bp_ctl.scala 443:87] - node _T_12884 = or(_T_12875, _T_12883) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][6][4] <= _T_12884 @[ifu_bp_ctl.scala 442:27] - node _T_12885 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12886 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12887 = eq(_T_12886, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_12888 = and(_T_12885, _T_12887) @[ifu_bp_ctl.scala 442:45] - node _T_12889 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12890 = eq(_T_12889, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_12891 = or(_T_12890, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12892 = and(_T_12888, _T_12891) @[ifu_bp_ctl.scala 442:110] - node _T_12893 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12894 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12895 = eq(_T_12894, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_12896 = and(_T_12893, _T_12895) @[ifu_bp_ctl.scala 443:22] - node _T_12897 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12898 = eq(_T_12897, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_12899 = or(_T_12898, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12900 = and(_T_12896, _T_12899) @[ifu_bp_ctl.scala 443:87] - node _T_12901 = or(_T_12892, _T_12900) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][6][5] <= _T_12901 @[ifu_bp_ctl.scala 442:27] - node _T_12902 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12903 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12904 = eq(_T_12903, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_12905 = and(_T_12902, _T_12904) @[ifu_bp_ctl.scala 442:45] - node _T_12906 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12907 = eq(_T_12906, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_12908 = or(_T_12907, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12909 = and(_T_12905, _T_12908) @[ifu_bp_ctl.scala 442:110] - node _T_12910 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12911 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12912 = eq(_T_12911, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_12913 = and(_T_12910, _T_12912) @[ifu_bp_ctl.scala 443:22] - node _T_12914 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12915 = eq(_T_12914, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_12916 = or(_T_12915, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12917 = and(_T_12913, _T_12916) @[ifu_bp_ctl.scala 443:87] - node _T_12918 = or(_T_12909, _T_12917) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][6][6] <= _T_12918 @[ifu_bp_ctl.scala 442:27] - node _T_12919 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12920 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12921 = eq(_T_12920, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_12922 = and(_T_12919, _T_12921) @[ifu_bp_ctl.scala 442:45] - node _T_12923 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12924 = eq(_T_12923, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_12925 = or(_T_12924, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12926 = and(_T_12922, _T_12925) @[ifu_bp_ctl.scala 442:110] - node _T_12927 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12928 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12929 = eq(_T_12928, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_12930 = and(_T_12927, _T_12929) @[ifu_bp_ctl.scala 443:22] - node _T_12931 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12932 = eq(_T_12931, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_12933 = or(_T_12932, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12934 = and(_T_12930, _T_12933) @[ifu_bp_ctl.scala 443:87] - node _T_12935 = or(_T_12926, _T_12934) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][6][7] <= _T_12935 @[ifu_bp_ctl.scala 442:27] - node _T_12936 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12937 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12938 = eq(_T_12937, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_12939 = and(_T_12936, _T_12938) @[ifu_bp_ctl.scala 442:45] - node _T_12940 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12941 = eq(_T_12940, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_12942 = or(_T_12941, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12943 = and(_T_12939, _T_12942) @[ifu_bp_ctl.scala 442:110] - node _T_12944 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12945 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12946 = eq(_T_12945, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_12947 = and(_T_12944, _T_12946) @[ifu_bp_ctl.scala 443:22] - node _T_12948 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12949 = eq(_T_12948, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_12950 = or(_T_12949, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12951 = and(_T_12947, _T_12950) @[ifu_bp_ctl.scala 443:87] - node _T_12952 = or(_T_12943, _T_12951) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][6][8] <= _T_12952 @[ifu_bp_ctl.scala 442:27] - node _T_12953 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12954 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12955 = eq(_T_12954, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_12956 = and(_T_12953, _T_12955) @[ifu_bp_ctl.scala 442:45] - node _T_12957 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12958 = eq(_T_12957, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_12959 = or(_T_12958, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12960 = and(_T_12956, _T_12959) @[ifu_bp_ctl.scala 442:110] - node _T_12961 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12962 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12963 = eq(_T_12962, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_12964 = and(_T_12961, _T_12963) @[ifu_bp_ctl.scala 443:22] - node _T_12965 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12966 = eq(_T_12965, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_12967 = or(_T_12966, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12968 = and(_T_12964, _T_12967) @[ifu_bp_ctl.scala 443:87] - node _T_12969 = or(_T_12960, _T_12968) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][6][9] <= _T_12969 @[ifu_bp_ctl.scala 442:27] - node _T_12970 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12971 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12972 = eq(_T_12971, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_12973 = and(_T_12970, _T_12972) @[ifu_bp_ctl.scala 442:45] - node _T_12974 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12975 = eq(_T_12974, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_12976 = or(_T_12975, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12977 = and(_T_12973, _T_12976) @[ifu_bp_ctl.scala 442:110] - node _T_12978 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12979 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12980 = eq(_T_12979, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_12981 = and(_T_12978, _T_12980) @[ifu_bp_ctl.scala 443:22] - node _T_12982 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_12983 = eq(_T_12982, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_12984 = or(_T_12983, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_12985 = and(_T_12981, _T_12984) @[ifu_bp_ctl.scala 443:87] - node _T_12986 = or(_T_12977, _T_12985) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][6][10] <= _T_12986 @[ifu_bp_ctl.scala 442:27] - node _T_12987 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_12988 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_12989 = eq(_T_12988, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_12990 = and(_T_12987, _T_12989) @[ifu_bp_ctl.scala 442:45] - node _T_12991 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_12992 = eq(_T_12991, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_12993 = or(_T_12992, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_12994 = and(_T_12990, _T_12993) @[ifu_bp_ctl.scala 442:110] - node _T_12995 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_12996 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_12997 = eq(_T_12996, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_12998 = and(_T_12995, _T_12997) @[ifu_bp_ctl.scala 443:22] - node _T_12999 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13000 = eq(_T_12999, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_13001 = or(_T_13000, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13002 = and(_T_12998, _T_13001) @[ifu_bp_ctl.scala 443:87] - node _T_13003 = or(_T_12994, _T_13002) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][6][11] <= _T_13003 @[ifu_bp_ctl.scala 442:27] - node _T_13004 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13005 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13006 = eq(_T_13005, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_13007 = and(_T_13004, _T_13006) @[ifu_bp_ctl.scala 442:45] - node _T_13008 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13009 = eq(_T_13008, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_13010 = or(_T_13009, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13011 = and(_T_13007, _T_13010) @[ifu_bp_ctl.scala 442:110] - node _T_13012 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13013 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13014 = eq(_T_13013, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_13015 = and(_T_13012, _T_13014) @[ifu_bp_ctl.scala 443:22] - node _T_13016 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13017 = eq(_T_13016, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_13018 = or(_T_13017, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13019 = and(_T_13015, _T_13018) @[ifu_bp_ctl.scala 443:87] - node _T_13020 = or(_T_13011, _T_13019) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][6][12] <= _T_13020 @[ifu_bp_ctl.scala 442:27] - node _T_13021 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13022 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13023 = eq(_T_13022, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_13024 = and(_T_13021, _T_13023) @[ifu_bp_ctl.scala 442:45] - node _T_13025 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13026 = eq(_T_13025, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_13027 = or(_T_13026, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13028 = and(_T_13024, _T_13027) @[ifu_bp_ctl.scala 442:110] - node _T_13029 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13030 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13031 = eq(_T_13030, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_13032 = and(_T_13029, _T_13031) @[ifu_bp_ctl.scala 443:22] - node _T_13033 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13034 = eq(_T_13033, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_13035 = or(_T_13034, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13036 = and(_T_13032, _T_13035) @[ifu_bp_ctl.scala 443:87] - node _T_13037 = or(_T_13028, _T_13036) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][6][13] <= _T_13037 @[ifu_bp_ctl.scala 442:27] - node _T_13038 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13039 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13040 = eq(_T_13039, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_13041 = and(_T_13038, _T_13040) @[ifu_bp_ctl.scala 442:45] - node _T_13042 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13043 = eq(_T_13042, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_13044 = or(_T_13043, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13045 = and(_T_13041, _T_13044) @[ifu_bp_ctl.scala 442:110] - node _T_13046 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13047 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13048 = eq(_T_13047, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_13049 = and(_T_13046, _T_13048) @[ifu_bp_ctl.scala 443:22] - node _T_13050 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13051 = eq(_T_13050, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_13052 = or(_T_13051, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13053 = and(_T_13049, _T_13052) @[ifu_bp_ctl.scala 443:87] - node _T_13054 = or(_T_13045, _T_13053) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][6][14] <= _T_13054 @[ifu_bp_ctl.scala 442:27] - node _T_13055 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13056 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13057 = eq(_T_13056, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_13058 = and(_T_13055, _T_13057) @[ifu_bp_ctl.scala 442:45] - node _T_13059 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13060 = eq(_T_13059, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_13061 = or(_T_13060, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13062 = and(_T_13058, _T_13061) @[ifu_bp_ctl.scala 442:110] - node _T_13063 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13064 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13065 = eq(_T_13064, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_13066 = and(_T_13063, _T_13065) @[ifu_bp_ctl.scala 443:22] - node _T_13067 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13068 = eq(_T_13067, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_13069 = or(_T_13068, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13070 = and(_T_13066, _T_13069) @[ifu_bp_ctl.scala 443:87] - node _T_13071 = or(_T_13062, _T_13070) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][6][15] <= _T_13071 @[ifu_bp_ctl.scala 442:27] - node _T_13072 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13073 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13074 = eq(_T_13073, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_13075 = and(_T_13072, _T_13074) @[ifu_bp_ctl.scala 442:45] - node _T_13076 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13077 = eq(_T_13076, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_13078 = or(_T_13077, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13079 = and(_T_13075, _T_13078) @[ifu_bp_ctl.scala 442:110] - node _T_13080 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13081 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13082 = eq(_T_13081, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_13083 = and(_T_13080, _T_13082) @[ifu_bp_ctl.scala 443:22] - node _T_13084 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13085 = eq(_T_13084, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_13086 = or(_T_13085, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13087 = and(_T_13083, _T_13086) @[ifu_bp_ctl.scala 443:87] - node _T_13088 = or(_T_13079, _T_13087) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][7][0] <= _T_13088 @[ifu_bp_ctl.scala 442:27] - node _T_13089 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13090 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13091 = eq(_T_13090, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_13092 = and(_T_13089, _T_13091) @[ifu_bp_ctl.scala 442:45] - node _T_13093 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13094 = eq(_T_13093, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_13095 = or(_T_13094, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13096 = and(_T_13092, _T_13095) @[ifu_bp_ctl.scala 442:110] - node _T_13097 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13098 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13099 = eq(_T_13098, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_13100 = and(_T_13097, _T_13099) @[ifu_bp_ctl.scala 443:22] - node _T_13101 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13102 = eq(_T_13101, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_13103 = or(_T_13102, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13104 = and(_T_13100, _T_13103) @[ifu_bp_ctl.scala 443:87] - node _T_13105 = or(_T_13096, _T_13104) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][7][1] <= _T_13105 @[ifu_bp_ctl.scala 442:27] - node _T_13106 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13107 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13108 = eq(_T_13107, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_13109 = and(_T_13106, _T_13108) @[ifu_bp_ctl.scala 442:45] - node _T_13110 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13111 = eq(_T_13110, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_13112 = or(_T_13111, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13113 = and(_T_13109, _T_13112) @[ifu_bp_ctl.scala 442:110] - node _T_13114 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13115 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13116 = eq(_T_13115, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_13117 = and(_T_13114, _T_13116) @[ifu_bp_ctl.scala 443:22] - node _T_13118 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13119 = eq(_T_13118, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_13120 = or(_T_13119, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13121 = and(_T_13117, _T_13120) @[ifu_bp_ctl.scala 443:87] - node _T_13122 = or(_T_13113, _T_13121) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][7][2] <= _T_13122 @[ifu_bp_ctl.scala 442:27] - node _T_13123 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13124 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13125 = eq(_T_13124, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_13126 = and(_T_13123, _T_13125) @[ifu_bp_ctl.scala 442:45] - node _T_13127 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13128 = eq(_T_13127, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_13129 = or(_T_13128, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13130 = and(_T_13126, _T_13129) @[ifu_bp_ctl.scala 442:110] - node _T_13131 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13132 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13133 = eq(_T_13132, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_13134 = and(_T_13131, _T_13133) @[ifu_bp_ctl.scala 443:22] - node _T_13135 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13136 = eq(_T_13135, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_13137 = or(_T_13136, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13138 = and(_T_13134, _T_13137) @[ifu_bp_ctl.scala 443:87] - node _T_13139 = or(_T_13130, _T_13138) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][7][3] <= _T_13139 @[ifu_bp_ctl.scala 442:27] - node _T_13140 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13141 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13142 = eq(_T_13141, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_13143 = and(_T_13140, _T_13142) @[ifu_bp_ctl.scala 442:45] - node _T_13144 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13145 = eq(_T_13144, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_13146 = or(_T_13145, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13147 = and(_T_13143, _T_13146) @[ifu_bp_ctl.scala 442:110] - node _T_13148 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13149 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13150 = eq(_T_13149, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_13151 = and(_T_13148, _T_13150) @[ifu_bp_ctl.scala 443:22] - node _T_13152 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13153 = eq(_T_13152, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_13154 = or(_T_13153, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13155 = and(_T_13151, _T_13154) @[ifu_bp_ctl.scala 443:87] - node _T_13156 = or(_T_13147, _T_13155) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][7][4] <= _T_13156 @[ifu_bp_ctl.scala 442:27] - node _T_13157 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13158 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13159 = eq(_T_13158, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_13160 = and(_T_13157, _T_13159) @[ifu_bp_ctl.scala 442:45] - node _T_13161 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13162 = eq(_T_13161, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_13163 = or(_T_13162, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13164 = and(_T_13160, _T_13163) @[ifu_bp_ctl.scala 442:110] - node _T_13165 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13166 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13167 = eq(_T_13166, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_13168 = and(_T_13165, _T_13167) @[ifu_bp_ctl.scala 443:22] - node _T_13169 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13170 = eq(_T_13169, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_13171 = or(_T_13170, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13172 = and(_T_13168, _T_13171) @[ifu_bp_ctl.scala 443:87] - node _T_13173 = or(_T_13164, _T_13172) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][7][5] <= _T_13173 @[ifu_bp_ctl.scala 442:27] - node _T_13174 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13175 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13176 = eq(_T_13175, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_13177 = and(_T_13174, _T_13176) @[ifu_bp_ctl.scala 442:45] - node _T_13178 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13179 = eq(_T_13178, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_13180 = or(_T_13179, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13181 = and(_T_13177, _T_13180) @[ifu_bp_ctl.scala 442:110] - node _T_13182 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13183 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13184 = eq(_T_13183, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_13185 = and(_T_13182, _T_13184) @[ifu_bp_ctl.scala 443:22] - node _T_13186 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13187 = eq(_T_13186, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_13188 = or(_T_13187, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13189 = and(_T_13185, _T_13188) @[ifu_bp_ctl.scala 443:87] - node _T_13190 = or(_T_13181, _T_13189) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][7][6] <= _T_13190 @[ifu_bp_ctl.scala 442:27] - node _T_13191 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13192 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13193 = eq(_T_13192, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_13194 = and(_T_13191, _T_13193) @[ifu_bp_ctl.scala 442:45] - node _T_13195 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13196 = eq(_T_13195, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_13197 = or(_T_13196, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13198 = and(_T_13194, _T_13197) @[ifu_bp_ctl.scala 442:110] - node _T_13199 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13200 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13201 = eq(_T_13200, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_13202 = and(_T_13199, _T_13201) @[ifu_bp_ctl.scala 443:22] - node _T_13203 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13204 = eq(_T_13203, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_13205 = or(_T_13204, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13206 = and(_T_13202, _T_13205) @[ifu_bp_ctl.scala 443:87] - node _T_13207 = or(_T_13198, _T_13206) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][7][7] <= _T_13207 @[ifu_bp_ctl.scala 442:27] - node _T_13208 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13209 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13210 = eq(_T_13209, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_13211 = and(_T_13208, _T_13210) @[ifu_bp_ctl.scala 442:45] - node _T_13212 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13213 = eq(_T_13212, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_13214 = or(_T_13213, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13215 = and(_T_13211, _T_13214) @[ifu_bp_ctl.scala 442:110] - node _T_13216 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13217 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13218 = eq(_T_13217, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_13219 = and(_T_13216, _T_13218) @[ifu_bp_ctl.scala 443:22] - node _T_13220 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13221 = eq(_T_13220, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_13222 = or(_T_13221, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13223 = and(_T_13219, _T_13222) @[ifu_bp_ctl.scala 443:87] - node _T_13224 = or(_T_13215, _T_13223) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][7][8] <= _T_13224 @[ifu_bp_ctl.scala 442:27] - node _T_13225 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13226 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13227 = eq(_T_13226, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_13228 = and(_T_13225, _T_13227) @[ifu_bp_ctl.scala 442:45] - node _T_13229 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13230 = eq(_T_13229, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_13231 = or(_T_13230, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13232 = and(_T_13228, _T_13231) @[ifu_bp_ctl.scala 442:110] - node _T_13233 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13234 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13235 = eq(_T_13234, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_13236 = and(_T_13233, _T_13235) @[ifu_bp_ctl.scala 443:22] - node _T_13237 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13238 = eq(_T_13237, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_13239 = or(_T_13238, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13240 = and(_T_13236, _T_13239) @[ifu_bp_ctl.scala 443:87] - node _T_13241 = or(_T_13232, _T_13240) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][7][9] <= _T_13241 @[ifu_bp_ctl.scala 442:27] - node _T_13242 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13243 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13244 = eq(_T_13243, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_13245 = and(_T_13242, _T_13244) @[ifu_bp_ctl.scala 442:45] - node _T_13246 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13247 = eq(_T_13246, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_13248 = or(_T_13247, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13249 = and(_T_13245, _T_13248) @[ifu_bp_ctl.scala 442:110] - node _T_13250 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13251 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13252 = eq(_T_13251, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_13253 = and(_T_13250, _T_13252) @[ifu_bp_ctl.scala 443:22] - node _T_13254 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13255 = eq(_T_13254, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_13256 = or(_T_13255, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13257 = and(_T_13253, _T_13256) @[ifu_bp_ctl.scala 443:87] - node _T_13258 = or(_T_13249, _T_13257) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][7][10] <= _T_13258 @[ifu_bp_ctl.scala 442:27] - node _T_13259 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13260 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13261 = eq(_T_13260, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_13262 = and(_T_13259, _T_13261) @[ifu_bp_ctl.scala 442:45] - node _T_13263 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13264 = eq(_T_13263, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_13265 = or(_T_13264, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13266 = and(_T_13262, _T_13265) @[ifu_bp_ctl.scala 442:110] - node _T_13267 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13268 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13269 = eq(_T_13268, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_13270 = and(_T_13267, _T_13269) @[ifu_bp_ctl.scala 443:22] - node _T_13271 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13272 = eq(_T_13271, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_13273 = or(_T_13272, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13274 = and(_T_13270, _T_13273) @[ifu_bp_ctl.scala 443:87] - node _T_13275 = or(_T_13266, _T_13274) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][7][11] <= _T_13275 @[ifu_bp_ctl.scala 442:27] - node _T_13276 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13277 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13278 = eq(_T_13277, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_13279 = and(_T_13276, _T_13278) @[ifu_bp_ctl.scala 442:45] - node _T_13280 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13281 = eq(_T_13280, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_13282 = or(_T_13281, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13283 = and(_T_13279, _T_13282) @[ifu_bp_ctl.scala 442:110] - node _T_13284 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13285 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13286 = eq(_T_13285, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_13287 = and(_T_13284, _T_13286) @[ifu_bp_ctl.scala 443:22] - node _T_13288 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13289 = eq(_T_13288, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_13290 = or(_T_13289, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13291 = and(_T_13287, _T_13290) @[ifu_bp_ctl.scala 443:87] - node _T_13292 = or(_T_13283, _T_13291) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][7][12] <= _T_13292 @[ifu_bp_ctl.scala 442:27] - node _T_13293 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13294 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13295 = eq(_T_13294, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_13296 = and(_T_13293, _T_13295) @[ifu_bp_ctl.scala 442:45] - node _T_13297 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13298 = eq(_T_13297, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_13299 = or(_T_13298, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13300 = and(_T_13296, _T_13299) @[ifu_bp_ctl.scala 442:110] - node _T_13301 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13302 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13303 = eq(_T_13302, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_13304 = and(_T_13301, _T_13303) @[ifu_bp_ctl.scala 443:22] - node _T_13305 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13306 = eq(_T_13305, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_13307 = or(_T_13306, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13308 = and(_T_13304, _T_13307) @[ifu_bp_ctl.scala 443:87] - node _T_13309 = or(_T_13300, _T_13308) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][7][13] <= _T_13309 @[ifu_bp_ctl.scala 442:27] - node _T_13310 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13311 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13312 = eq(_T_13311, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_13313 = and(_T_13310, _T_13312) @[ifu_bp_ctl.scala 442:45] - node _T_13314 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13315 = eq(_T_13314, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_13316 = or(_T_13315, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13317 = and(_T_13313, _T_13316) @[ifu_bp_ctl.scala 442:110] - node _T_13318 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13319 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13320 = eq(_T_13319, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_13321 = and(_T_13318, _T_13320) @[ifu_bp_ctl.scala 443:22] - node _T_13322 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13323 = eq(_T_13322, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_13324 = or(_T_13323, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13325 = and(_T_13321, _T_13324) @[ifu_bp_ctl.scala 443:87] - node _T_13326 = or(_T_13317, _T_13325) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][7][14] <= _T_13326 @[ifu_bp_ctl.scala 442:27] - node _T_13327 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13328 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13329 = eq(_T_13328, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_13330 = and(_T_13327, _T_13329) @[ifu_bp_ctl.scala 442:45] - node _T_13331 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13332 = eq(_T_13331, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_13333 = or(_T_13332, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13334 = and(_T_13330, _T_13333) @[ifu_bp_ctl.scala 442:110] - node _T_13335 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13336 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13337 = eq(_T_13336, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_13338 = and(_T_13335, _T_13337) @[ifu_bp_ctl.scala 443:22] - node _T_13339 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13340 = eq(_T_13339, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_13341 = or(_T_13340, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13342 = and(_T_13338, _T_13341) @[ifu_bp_ctl.scala 443:87] - node _T_13343 = or(_T_13334, _T_13342) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][7][15] <= _T_13343 @[ifu_bp_ctl.scala 442:27] - node _T_13344 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13345 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13346 = eq(_T_13345, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_13347 = and(_T_13344, _T_13346) @[ifu_bp_ctl.scala 442:45] - node _T_13348 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13349 = eq(_T_13348, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_13350 = or(_T_13349, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13351 = and(_T_13347, _T_13350) @[ifu_bp_ctl.scala 442:110] - node _T_13352 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13353 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13354 = eq(_T_13353, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_13355 = and(_T_13352, _T_13354) @[ifu_bp_ctl.scala 443:22] - node _T_13356 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13357 = eq(_T_13356, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_13358 = or(_T_13357, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13359 = and(_T_13355, _T_13358) @[ifu_bp_ctl.scala 443:87] - node _T_13360 = or(_T_13351, _T_13359) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][8][0] <= _T_13360 @[ifu_bp_ctl.scala 442:27] - node _T_13361 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13362 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13363 = eq(_T_13362, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_13364 = and(_T_13361, _T_13363) @[ifu_bp_ctl.scala 442:45] - node _T_13365 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13366 = eq(_T_13365, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_13367 = or(_T_13366, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13368 = and(_T_13364, _T_13367) @[ifu_bp_ctl.scala 442:110] - node _T_13369 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13370 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13371 = eq(_T_13370, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_13372 = and(_T_13369, _T_13371) @[ifu_bp_ctl.scala 443:22] - node _T_13373 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13374 = eq(_T_13373, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_13375 = or(_T_13374, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13376 = and(_T_13372, _T_13375) @[ifu_bp_ctl.scala 443:87] - node _T_13377 = or(_T_13368, _T_13376) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][8][1] <= _T_13377 @[ifu_bp_ctl.scala 442:27] - node _T_13378 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13379 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13380 = eq(_T_13379, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_13381 = and(_T_13378, _T_13380) @[ifu_bp_ctl.scala 442:45] - node _T_13382 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13383 = eq(_T_13382, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_13384 = or(_T_13383, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13385 = and(_T_13381, _T_13384) @[ifu_bp_ctl.scala 442:110] - node _T_13386 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13387 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13388 = eq(_T_13387, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_13389 = and(_T_13386, _T_13388) @[ifu_bp_ctl.scala 443:22] - node _T_13390 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13391 = eq(_T_13390, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_13392 = or(_T_13391, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13393 = and(_T_13389, _T_13392) @[ifu_bp_ctl.scala 443:87] - node _T_13394 = or(_T_13385, _T_13393) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][8][2] <= _T_13394 @[ifu_bp_ctl.scala 442:27] - node _T_13395 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13396 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13397 = eq(_T_13396, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_13398 = and(_T_13395, _T_13397) @[ifu_bp_ctl.scala 442:45] - node _T_13399 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13400 = eq(_T_13399, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_13401 = or(_T_13400, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13402 = and(_T_13398, _T_13401) @[ifu_bp_ctl.scala 442:110] - node _T_13403 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13404 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13405 = eq(_T_13404, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_13406 = and(_T_13403, _T_13405) @[ifu_bp_ctl.scala 443:22] - node _T_13407 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13408 = eq(_T_13407, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_13409 = or(_T_13408, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13410 = and(_T_13406, _T_13409) @[ifu_bp_ctl.scala 443:87] - node _T_13411 = or(_T_13402, _T_13410) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][8][3] <= _T_13411 @[ifu_bp_ctl.scala 442:27] - node _T_13412 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13413 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13414 = eq(_T_13413, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_13415 = and(_T_13412, _T_13414) @[ifu_bp_ctl.scala 442:45] - node _T_13416 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13417 = eq(_T_13416, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_13418 = or(_T_13417, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13419 = and(_T_13415, _T_13418) @[ifu_bp_ctl.scala 442:110] - node _T_13420 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13421 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13422 = eq(_T_13421, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_13423 = and(_T_13420, _T_13422) @[ifu_bp_ctl.scala 443:22] - node _T_13424 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13425 = eq(_T_13424, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_13426 = or(_T_13425, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13427 = and(_T_13423, _T_13426) @[ifu_bp_ctl.scala 443:87] - node _T_13428 = or(_T_13419, _T_13427) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][8][4] <= _T_13428 @[ifu_bp_ctl.scala 442:27] - node _T_13429 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13430 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13431 = eq(_T_13430, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_13432 = and(_T_13429, _T_13431) @[ifu_bp_ctl.scala 442:45] - node _T_13433 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13434 = eq(_T_13433, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_13435 = or(_T_13434, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13436 = and(_T_13432, _T_13435) @[ifu_bp_ctl.scala 442:110] - node _T_13437 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13438 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13439 = eq(_T_13438, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_13440 = and(_T_13437, _T_13439) @[ifu_bp_ctl.scala 443:22] - node _T_13441 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13442 = eq(_T_13441, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_13443 = or(_T_13442, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13444 = and(_T_13440, _T_13443) @[ifu_bp_ctl.scala 443:87] - node _T_13445 = or(_T_13436, _T_13444) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][8][5] <= _T_13445 @[ifu_bp_ctl.scala 442:27] - node _T_13446 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13447 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13448 = eq(_T_13447, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_13449 = and(_T_13446, _T_13448) @[ifu_bp_ctl.scala 442:45] - node _T_13450 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13451 = eq(_T_13450, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_13452 = or(_T_13451, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13453 = and(_T_13449, _T_13452) @[ifu_bp_ctl.scala 442:110] - node _T_13454 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13455 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13456 = eq(_T_13455, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_13457 = and(_T_13454, _T_13456) @[ifu_bp_ctl.scala 443:22] - node _T_13458 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13459 = eq(_T_13458, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_13460 = or(_T_13459, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13461 = and(_T_13457, _T_13460) @[ifu_bp_ctl.scala 443:87] - node _T_13462 = or(_T_13453, _T_13461) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][8][6] <= _T_13462 @[ifu_bp_ctl.scala 442:27] - node _T_13463 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13464 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13465 = eq(_T_13464, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_13466 = and(_T_13463, _T_13465) @[ifu_bp_ctl.scala 442:45] - node _T_13467 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13468 = eq(_T_13467, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_13469 = or(_T_13468, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13470 = and(_T_13466, _T_13469) @[ifu_bp_ctl.scala 442:110] - node _T_13471 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13472 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13473 = eq(_T_13472, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_13474 = and(_T_13471, _T_13473) @[ifu_bp_ctl.scala 443:22] - node _T_13475 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13476 = eq(_T_13475, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_13477 = or(_T_13476, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13478 = and(_T_13474, _T_13477) @[ifu_bp_ctl.scala 443:87] - node _T_13479 = or(_T_13470, _T_13478) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][8][7] <= _T_13479 @[ifu_bp_ctl.scala 442:27] - node _T_13480 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13481 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13482 = eq(_T_13481, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_13483 = and(_T_13480, _T_13482) @[ifu_bp_ctl.scala 442:45] - node _T_13484 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13485 = eq(_T_13484, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_13486 = or(_T_13485, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13487 = and(_T_13483, _T_13486) @[ifu_bp_ctl.scala 442:110] - node _T_13488 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13489 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13490 = eq(_T_13489, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_13491 = and(_T_13488, _T_13490) @[ifu_bp_ctl.scala 443:22] - node _T_13492 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13493 = eq(_T_13492, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_13494 = or(_T_13493, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13495 = and(_T_13491, _T_13494) @[ifu_bp_ctl.scala 443:87] - node _T_13496 = or(_T_13487, _T_13495) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][8][8] <= _T_13496 @[ifu_bp_ctl.scala 442:27] - node _T_13497 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13498 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13499 = eq(_T_13498, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_13500 = and(_T_13497, _T_13499) @[ifu_bp_ctl.scala 442:45] - node _T_13501 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13502 = eq(_T_13501, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_13503 = or(_T_13502, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13504 = and(_T_13500, _T_13503) @[ifu_bp_ctl.scala 442:110] - node _T_13505 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13506 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13507 = eq(_T_13506, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_13508 = and(_T_13505, _T_13507) @[ifu_bp_ctl.scala 443:22] - node _T_13509 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13510 = eq(_T_13509, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_13511 = or(_T_13510, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13512 = and(_T_13508, _T_13511) @[ifu_bp_ctl.scala 443:87] - node _T_13513 = or(_T_13504, _T_13512) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][8][9] <= _T_13513 @[ifu_bp_ctl.scala 442:27] - node _T_13514 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13515 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13516 = eq(_T_13515, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_13517 = and(_T_13514, _T_13516) @[ifu_bp_ctl.scala 442:45] - node _T_13518 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13519 = eq(_T_13518, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_13520 = or(_T_13519, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13521 = and(_T_13517, _T_13520) @[ifu_bp_ctl.scala 442:110] - node _T_13522 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13523 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13524 = eq(_T_13523, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_13525 = and(_T_13522, _T_13524) @[ifu_bp_ctl.scala 443:22] - node _T_13526 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13527 = eq(_T_13526, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_13528 = or(_T_13527, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13529 = and(_T_13525, _T_13528) @[ifu_bp_ctl.scala 443:87] - node _T_13530 = or(_T_13521, _T_13529) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][8][10] <= _T_13530 @[ifu_bp_ctl.scala 442:27] - node _T_13531 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13532 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13533 = eq(_T_13532, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_13534 = and(_T_13531, _T_13533) @[ifu_bp_ctl.scala 442:45] - node _T_13535 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13536 = eq(_T_13535, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_13537 = or(_T_13536, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13538 = and(_T_13534, _T_13537) @[ifu_bp_ctl.scala 442:110] - node _T_13539 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13540 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13541 = eq(_T_13540, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_13542 = and(_T_13539, _T_13541) @[ifu_bp_ctl.scala 443:22] - node _T_13543 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13544 = eq(_T_13543, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_13545 = or(_T_13544, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13546 = and(_T_13542, _T_13545) @[ifu_bp_ctl.scala 443:87] - node _T_13547 = or(_T_13538, _T_13546) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][8][11] <= _T_13547 @[ifu_bp_ctl.scala 442:27] - node _T_13548 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13549 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13550 = eq(_T_13549, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_13551 = and(_T_13548, _T_13550) @[ifu_bp_ctl.scala 442:45] - node _T_13552 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13553 = eq(_T_13552, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_13554 = or(_T_13553, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13555 = and(_T_13551, _T_13554) @[ifu_bp_ctl.scala 442:110] - node _T_13556 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13557 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13558 = eq(_T_13557, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_13559 = and(_T_13556, _T_13558) @[ifu_bp_ctl.scala 443:22] - node _T_13560 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13561 = eq(_T_13560, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_13562 = or(_T_13561, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13563 = and(_T_13559, _T_13562) @[ifu_bp_ctl.scala 443:87] - node _T_13564 = or(_T_13555, _T_13563) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][8][12] <= _T_13564 @[ifu_bp_ctl.scala 442:27] - node _T_13565 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13566 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13567 = eq(_T_13566, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_13568 = and(_T_13565, _T_13567) @[ifu_bp_ctl.scala 442:45] - node _T_13569 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13570 = eq(_T_13569, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_13571 = or(_T_13570, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13572 = and(_T_13568, _T_13571) @[ifu_bp_ctl.scala 442:110] - node _T_13573 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13574 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13575 = eq(_T_13574, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_13576 = and(_T_13573, _T_13575) @[ifu_bp_ctl.scala 443:22] - node _T_13577 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13578 = eq(_T_13577, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_13579 = or(_T_13578, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13580 = and(_T_13576, _T_13579) @[ifu_bp_ctl.scala 443:87] - node _T_13581 = or(_T_13572, _T_13580) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][8][13] <= _T_13581 @[ifu_bp_ctl.scala 442:27] - node _T_13582 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13583 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13584 = eq(_T_13583, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_13585 = and(_T_13582, _T_13584) @[ifu_bp_ctl.scala 442:45] - node _T_13586 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13587 = eq(_T_13586, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_13588 = or(_T_13587, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13589 = and(_T_13585, _T_13588) @[ifu_bp_ctl.scala 442:110] - node _T_13590 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13591 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13592 = eq(_T_13591, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_13593 = and(_T_13590, _T_13592) @[ifu_bp_ctl.scala 443:22] - node _T_13594 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13595 = eq(_T_13594, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_13596 = or(_T_13595, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13597 = and(_T_13593, _T_13596) @[ifu_bp_ctl.scala 443:87] - node _T_13598 = or(_T_13589, _T_13597) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][8][14] <= _T_13598 @[ifu_bp_ctl.scala 442:27] - node _T_13599 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13600 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13601 = eq(_T_13600, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_13602 = and(_T_13599, _T_13601) @[ifu_bp_ctl.scala 442:45] - node _T_13603 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13604 = eq(_T_13603, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_13605 = or(_T_13604, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13606 = and(_T_13602, _T_13605) @[ifu_bp_ctl.scala 442:110] - node _T_13607 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13608 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13609 = eq(_T_13608, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_13610 = and(_T_13607, _T_13609) @[ifu_bp_ctl.scala 443:22] - node _T_13611 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13612 = eq(_T_13611, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_13613 = or(_T_13612, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13614 = and(_T_13610, _T_13613) @[ifu_bp_ctl.scala 443:87] - node _T_13615 = or(_T_13606, _T_13614) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][8][15] <= _T_13615 @[ifu_bp_ctl.scala 442:27] - node _T_13616 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13617 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13618 = eq(_T_13617, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_13619 = and(_T_13616, _T_13618) @[ifu_bp_ctl.scala 442:45] - node _T_13620 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13621 = eq(_T_13620, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_13622 = or(_T_13621, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13623 = and(_T_13619, _T_13622) @[ifu_bp_ctl.scala 442:110] - node _T_13624 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13625 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13626 = eq(_T_13625, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_13627 = and(_T_13624, _T_13626) @[ifu_bp_ctl.scala 443:22] - node _T_13628 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13629 = eq(_T_13628, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_13630 = or(_T_13629, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13631 = and(_T_13627, _T_13630) @[ifu_bp_ctl.scala 443:87] - node _T_13632 = or(_T_13623, _T_13631) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][9][0] <= _T_13632 @[ifu_bp_ctl.scala 442:27] - node _T_13633 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13634 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13635 = eq(_T_13634, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_13636 = and(_T_13633, _T_13635) @[ifu_bp_ctl.scala 442:45] - node _T_13637 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13638 = eq(_T_13637, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_13639 = or(_T_13638, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13640 = and(_T_13636, _T_13639) @[ifu_bp_ctl.scala 442:110] - node _T_13641 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13642 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13643 = eq(_T_13642, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_13644 = and(_T_13641, _T_13643) @[ifu_bp_ctl.scala 443:22] - node _T_13645 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13646 = eq(_T_13645, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_13647 = or(_T_13646, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13648 = and(_T_13644, _T_13647) @[ifu_bp_ctl.scala 443:87] - node _T_13649 = or(_T_13640, _T_13648) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][9][1] <= _T_13649 @[ifu_bp_ctl.scala 442:27] - node _T_13650 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13651 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13652 = eq(_T_13651, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_13653 = and(_T_13650, _T_13652) @[ifu_bp_ctl.scala 442:45] - node _T_13654 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13655 = eq(_T_13654, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_13656 = or(_T_13655, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13657 = and(_T_13653, _T_13656) @[ifu_bp_ctl.scala 442:110] - node _T_13658 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13659 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13660 = eq(_T_13659, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_13661 = and(_T_13658, _T_13660) @[ifu_bp_ctl.scala 443:22] - node _T_13662 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13663 = eq(_T_13662, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_13664 = or(_T_13663, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13665 = and(_T_13661, _T_13664) @[ifu_bp_ctl.scala 443:87] - node _T_13666 = or(_T_13657, _T_13665) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][9][2] <= _T_13666 @[ifu_bp_ctl.scala 442:27] - node _T_13667 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13668 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13669 = eq(_T_13668, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_13670 = and(_T_13667, _T_13669) @[ifu_bp_ctl.scala 442:45] - node _T_13671 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13672 = eq(_T_13671, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_13673 = or(_T_13672, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13674 = and(_T_13670, _T_13673) @[ifu_bp_ctl.scala 442:110] - node _T_13675 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13676 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13677 = eq(_T_13676, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_13678 = and(_T_13675, _T_13677) @[ifu_bp_ctl.scala 443:22] - node _T_13679 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13680 = eq(_T_13679, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_13681 = or(_T_13680, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13682 = and(_T_13678, _T_13681) @[ifu_bp_ctl.scala 443:87] - node _T_13683 = or(_T_13674, _T_13682) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][9][3] <= _T_13683 @[ifu_bp_ctl.scala 442:27] - node _T_13684 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13685 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13686 = eq(_T_13685, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_13687 = and(_T_13684, _T_13686) @[ifu_bp_ctl.scala 442:45] - node _T_13688 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13689 = eq(_T_13688, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_13690 = or(_T_13689, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13691 = and(_T_13687, _T_13690) @[ifu_bp_ctl.scala 442:110] - node _T_13692 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13693 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13694 = eq(_T_13693, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_13695 = and(_T_13692, _T_13694) @[ifu_bp_ctl.scala 443:22] - node _T_13696 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13697 = eq(_T_13696, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_13698 = or(_T_13697, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13699 = and(_T_13695, _T_13698) @[ifu_bp_ctl.scala 443:87] - node _T_13700 = or(_T_13691, _T_13699) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][9][4] <= _T_13700 @[ifu_bp_ctl.scala 442:27] - node _T_13701 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13702 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13703 = eq(_T_13702, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_13704 = and(_T_13701, _T_13703) @[ifu_bp_ctl.scala 442:45] - node _T_13705 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13706 = eq(_T_13705, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_13707 = or(_T_13706, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13708 = and(_T_13704, _T_13707) @[ifu_bp_ctl.scala 442:110] - node _T_13709 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13710 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13711 = eq(_T_13710, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_13712 = and(_T_13709, _T_13711) @[ifu_bp_ctl.scala 443:22] - node _T_13713 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13714 = eq(_T_13713, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_13715 = or(_T_13714, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13716 = and(_T_13712, _T_13715) @[ifu_bp_ctl.scala 443:87] - node _T_13717 = or(_T_13708, _T_13716) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][9][5] <= _T_13717 @[ifu_bp_ctl.scala 442:27] - node _T_13718 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13719 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13720 = eq(_T_13719, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_13721 = and(_T_13718, _T_13720) @[ifu_bp_ctl.scala 442:45] - node _T_13722 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13723 = eq(_T_13722, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_13724 = or(_T_13723, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13725 = and(_T_13721, _T_13724) @[ifu_bp_ctl.scala 442:110] - node _T_13726 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13727 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13728 = eq(_T_13727, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_13729 = and(_T_13726, _T_13728) @[ifu_bp_ctl.scala 443:22] - node _T_13730 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13731 = eq(_T_13730, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_13732 = or(_T_13731, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13733 = and(_T_13729, _T_13732) @[ifu_bp_ctl.scala 443:87] - node _T_13734 = or(_T_13725, _T_13733) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][9][6] <= _T_13734 @[ifu_bp_ctl.scala 442:27] - node _T_13735 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13736 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13737 = eq(_T_13736, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_13738 = and(_T_13735, _T_13737) @[ifu_bp_ctl.scala 442:45] - node _T_13739 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13740 = eq(_T_13739, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_13741 = or(_T_13740, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13742 = and(_T_13738, _T_13741) @[ifu_bp_ctl.scala 442:110] - node _T_13743 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13744 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13745 = eq(_T_13744, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_13746 = and(_T_13743, _T_13745) @[ifu_bp_ctl.scala 443:22] - node _T_13747 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13748 = eq(_T_13747, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_13749 = or(_T_13748, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13750 = and(_T_13746, _T_13749) @[ifu_bp_ctl.scala 443:87] - node _T_13751 = or(_T_13742, _T_13750) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][9][7] <= _T_13751 @[ifu_bp_ctl.scala 442:27] - node _T_13752 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13753 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13754 = eq(_T_13753, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_13755 = and(_T_13752, _T_13754) @[ifu_bp_ctl.scala 442:45] - node _T_13756 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13757 = eq(_T_13756, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_13758 = or(_T_13757, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13759 = and(_T_13755, _T_13758) @[ifu_bp_ctl.scala 442:110] - node _T_13760 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13761 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13762 = eq(_T_13761, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_13763 = and(_T_13760, _T_13762) @[ifu_bp_ctl.scala 443:22] - node _T_13764 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13765 = eq(_T_13764, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_13766 = or(_T_13765, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13767 = and(_T_13763, _T_13766) @[ifu_bp_ctl.scala 443:87] - node _T_13768 = or(_T_13759, _T_13767) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][9][8] <= _T_13768 @[ifu_bp_ctl.scala 442:27] - node _T_13769 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13770 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13771 = eq(_T_13770, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_13772 = and(_T_13769, _T_13771) @[ifu_bp_ctl.scala 442:45] - node _T_13773 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13774 = eq(_T_13773, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_13775 = or(_T_13774, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13776 = and(_T_13772, _T_13775) @[ifu_bp_ctl.scala 442:110] - node _T_13777 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13778 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13779 = eq(_T_13778, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_13780 = and(_T_13777, _T_13779) @[ifu_bp_ctl.scala 443:22] - node _T_13781 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13782 = eq(_T_13781, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_13783 = or(_T_13782, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13784 = and(_T_13780, _T_13783) @[ifu_bp_ctl.scala 443:87] - node _T_13785 = or(_T_13776, _T_13784) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][9][9] <= _T_13785 @[ifu_bp_ctl.scala 442:27] - node _T_13786 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13787 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13788 = eq(_T_13787, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_13789 = and(_T_13786, _T_13788) @[ifu_bp_ctl.scala 442:45] - node _T_13790 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13791 = eq(_T_13790, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_13792 = or(_T_13791, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13793 = and(_T_13789, _T_13792) @[ifu_bp_ctl.scala 442:110] - node _T_13794 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13795 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13796 = eq(_T_13795, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_13797 = and(_T_13794, _T_13796) @[ifu_bp_ctl.scala 443:22] - node _T_13798 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13799 = eq(_T_13798, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_13800 = or(_T_13799, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13801 = and(_T_13797, _T_13800) @[ifu_bp_ctl.scala 443:87] - node _T_13802 = or(_T_13793, _T_13801) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][9][10] <= _T_13802 @[ifu_bp_ctl.scala 442:27] - node _T_13803 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13804 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13805 = eq(_T_13804, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_13806 = and(_T_13803, _T_13805) @[ifu_bp_ctl.scala 442:45] - node _T_13807 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13808 = eq(_T_13807, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_13809 = or(_T_13808, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13810 = and(_T_13806, _T_13809) @[ifu_bp_ctl.scala 442:110] - node _T_13811 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13812 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13813 = eq(_T_13812, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_13814 = and(_T_13811, _T_13813) @[ifu_bp_ctl.scala 443:22] - node _T_13815 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13816 = eq(_T_13815, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_13817 = or(_T_13816, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13818 = and(_T_13814, _T_13817) @[ifu_bp_ctl.scala 443:87] - node _T_13819 = or(_T_13810, _T_13818) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][9][11] <= _T_13819 @[ifu_bp_ctl.scala 442:27] - node _T_13820 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13821 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13822 = eq(_T_13821, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_13823 = and(_T_13820, _T_13822) @[ifu_bp_ctl.scala 442:45] - node _T_13824 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13825 = eq(_T_13824, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_13826 = or(_T_13825, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13827 = and(_T_13823, _T_13826) @[ifu_bp_ctl.scala 442:110] - node _T_13828 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13829 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13830 = eq(_T_13829, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_13831 = and(_T_13828, _T_13830) @[ifu_bp_ctl.scala 443:22] - node _T_13832 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13833 = eq(_T_13832, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_13834 = or(_T_13833, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13835 = and(_T_13831, _T_13834) @[ifu_bp_ctl.scala 443:87] - node _T_13836 = or(_T_13827, _T_13835) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][9][12] <= _T_13836 @[ifu_bp_ctl.scala 442:27] - node _T_13837 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13838 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13839 = eq(_T_13838, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_13840 = and(_T_13837, _T_13839) @[ifu_bp_ctl.scala 442:45] - node _T_13841 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13842 = eq(_T_13841, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_13843 = or(_T_13842, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13844 = and(_T_13840, _T_13843) @[ifu_bp_ctl.scala 442:110] - node _T_13845 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13846 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13847 = eq(_T_13846, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_13848 = and(_T_13845, _T_13847) @[ifu_bp_ctl.scala 443:22] - node _T_13849 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13850 = eq(_T_13849, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_13851 = or(_T_13850, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13852 = and(_T_13848, _T_13851) @[ifu_bp_ctl.scala 443:87] - node _T_13853 = or(_T_13844, _T_13852) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][9][13] <= _T_13853 @[ifu_bp_ctl.scala 442:27] - node _T_13854 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13855 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13856 = eq(_T_13855, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_13857 = and(_T_13854, _T_13856) @[ifu_bp_ctl.scala 442:45] - node _T_13858 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13859 = eq(_T_13858, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_13860 = or(_T_13859, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13861 = and(_T_13857, _T_13860) @[ifu_bp_ctl.scala 442:110] - node _T_13862 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13863 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13864 = eq(_T_13863, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_13865 = and(_T_13862, _T_13864) @[ifu_bp_ctl.scala 443:22] - node _T_13866 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13867 = eq(_T_13866, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_13868 = or(_T_13867, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13869 = and(_T_13865, _T_13868) @[ifu_bp_ctl.scala 443:87] - node _T_13870 = or(_T_13861, _T_13869) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][9][14] <= _T_13870 @[ifu_bp_ctl.scala 442:27] - node _T_13871 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13872 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13873 = eq(_T_13872, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_13874 = and(_T_13871, _T_13873) @[ifu_bp_ctl.scala 442:45] - node _T_13875 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13876 = eq(_T_13875, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_13877 = or(_T_13876, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13878 = and(_T_13874, _T_13877) @[ifu_bp_ctl.scala 442:110] - node _T_13879 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13880 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13881 = eq(_T_13880, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_13882 = and(_T_13879, _T_13881) @[ifu_bp_ctl.scala 443:22] - node _T_13883 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13884 = eq(_T_13883, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_13885 = or(_T_13884, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13886 = and(_T_13882, _T_13885) @[ifu_bp_ctl.scala 443:87] - node _T_13887 = or(_T_13878, _T_13886) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][9][15] <= _T_13887 @[ifu_bp_ctl.scala 442:27] - node _T_13888 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13889 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13890 = eq(_T_13889, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_13891 = and(_T_13888, _T_13890) @[ifu_bp_ctl.scala 442:45] - node _T_13892 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13893 = eq(_T_13892, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_13894 = or(_T_13893, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13895 = and(_T_13891, _T_13894) @[ifu_bp_ctl.scala 442:110] - node _T_13896 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13897 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13898 = eq(_T_13897, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_13899 = and(_T_13896, _T_13898) @[ifu_bp_ctl.scala 443:22] - node _T_13900 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13901 = eq(_T_13900, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_13902 = or(_T_13901, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13903 = and(_T_13899, _T_13902) @[ifu_bp_ctl.scala 443:87] - node _T_13904 = or(_T_13895, _T_13903) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][10][0] <= _T_13904 @[ifu_bp_ctl.scala 442:27] - node _T_13905 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13906 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13907 = eq(_T_13906, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_13908 = and(_T_13905, _T_13907) @[ifu_bp_ctl.scala 442:45] - node _T_13909 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13910 = eq(_T_13909, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_13911 = or(_T_13910, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13912 = and(_T_13908, _T_13911) @[ifu_bp_ctl.scala 442:110] - node _T_13913 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13914 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13915 = eq(_T_13914, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_13916 = and(_T_13913, _T_13915) @[ifu_bp_ctl.scala 443:22] - node _T_13917 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13918 = eq(_T_13917, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_13919 = or(_T_13918, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13920 = and(_T_13916, _T_13919) @[ifu_bp_ctl.scala 443:87] - node _T_13921 = or(_T_13912, _T_13920) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][10][1] <= _T_13921 @[ifu_bp_ctl.scala 442:27] - node _T_13922 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13923 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13924 = eq(_T_13923, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_13925 = and(_T_13922, _T_13924) @[ifu_bp_ctl.scala 442:45] - node _T_13926 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13927 = eq(_T_13926, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_13928 = or(_T_13927, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13929 = and(_T_13925, _T_13928) @[ifu_bp_ctl.scala 442:110] - node _T_13930 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13931 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13932 = eq(_T_13931, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_13933 = and(_T_13930, _T_13932) @[ifu_bp_ctl.scala 443:22] - node _T_13934 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13935 = eq(_T_13934, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_13936 = or(_T_13935, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13937 = and(_T_13933, _T_13936) @[ifu_bp_ctl.scala 443:87] - node _T_13938 = or(_T_13929, _T_13937) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][10][2] <= _T_13938 @[ifu_bp_ctl.scala 442:27] - node _T_13939 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13940 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13941 = eq(_T_13940, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_13942 = and(_T_13939, _T_13941) @[ifu_bp_ctl.scala 442:45] - node _T_13943 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13944 = eq(_T_13943, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_13945 = or(_T_13944, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13946 = and(_T_13942, _T_13945) @[ifu_bp_ctl.scala 442:110] - node _T_13947 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13948 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13949 = eq(_T_13948, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_13950 = and(_T_13947, _T_13949) @[ifu_bp_ctl.scala 443:22] - node _T_13951 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13952 = eq(_T_13951, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_13953 = or(_T_13952, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13954 = and(_T_13950, _T_13953) @[ifu_bp_ctl.scala 443:87] - node _T_13955 = or(_T_13946, _T_13954) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][10][3] <= _T_13955 @[ifu_bp_ctl.scala 442:27] - node _T_13956 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13957 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13958 = eq(_T_13957, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_13959 = and(_T_13956, _T_13958) @[ifu_bp_ctl.scala 442:45] - node _T_13960 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13961 = eq(_T_13960, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_13962 = or(_T_13961, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13963 = and(_T_13959, _T_13962) @[ifu_bp_ctl.scala 442:110] - node _T_13964 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13965 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13966 = eq(_T_13965, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_13967 = and(_T_13964, _T_13966) @[ifu_bp_ctl.scala 443:22] - node _T_13968 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13969 = eq(_T_13968, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_13970 = or(_T_13969, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13971 = and(_T_13967, _T_13970) @[ifu_bp_ctl.scala 443:87] - node _T_13972 = or(_T_13963, _T_13971) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][10][4] <= _T_13972 @[ifu_bp_ctl.scala 442:27] - node _T_13973 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13974 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13975 = eq(_T_13974, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_13976 = and(_T_13973, _T_13975) @[ifu_bp_ctl.scala 442:45] - node _T_13977 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13978 = eq(_T_13977, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_13979 = or(_T_13978, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13980 = and(_T_13976, _T_13979) @[ifu_bp_ctl.scala 442:110] - node _T_13981 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13982 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_13983 = eq(_T_13982, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_13984 = and(_T_13981, _T_13983) @[ifu_bp_ctl.scala 443:22] - node _T_13985 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_13986 = eq(_T_13985, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_13987 = or(_T_13986, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_13988 = and(_T_13984, _T_13987) @[ifu_bp_ctl.scala 443:87] - node _T_13989 = or(_T_13980, _T_13988) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][10][5] <= _T_13989 @[ifu_bp_ctl.scala 442:27] - node _T_13990 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_13991 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_13992 = eq(_T_13991, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_13993 = and(_T_13990, _T_13992) @[ifu_bp_ctl.scala 442:45] - node _T_13994 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_13995 = eq(_T_13994, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_13996 = or(_T_13995, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_13997 = and(_T_13993, _T_13996) @[ifu_bp_ctl.scala 442:110] - node _T_13998 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_13999 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14000 = eq(_T_13999, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_14001 = and(_T_13998, _T_14000) @[ifu_bp_ctl.scala 443:22] - node _T_14002 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14003 = eq(_T_14002, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_14004 = or(_T_14003, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14005 = and(_T_14001, _T_14004) @[ifu_bp_ctl.scala 443:87] - node _T_14006 = or(_T_13997, _T_14005) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][10][6] <= _T_14006 @[ifu_bp_ctl.scala 442:27] - node _T_14007 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14008 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14009 = eq(_T_14008, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_14010 = and(_T_14007, _T_14009) @[ifu_bp_ctl.scala 442:45] - node _T_14011 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14012 = eq(_T_14011, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_14013 = or(_T_14012, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14014 = and(_T_14010, _T_14013) @[ifu_bp_ctl.scala 442:110] - node _T_14015 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14016 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14017 = eq(_T_14016, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_14018 = and(_T_14015, _T_14017) @[ifu_bp_ctl.scala 443:22] - node _T_14019 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14020 = eq(_T_14019, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_14021 = or(_T_14020, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14022 = and(_T_14018, _T_14021) @[ifu_bp_ctl.scala 443:87] - node _T_14023 = or(_T_14014, _T_14022) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][10][7] <= _T_14023 @[ifu_bp_ctl.scala 442:27] - node _T_14024 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14025 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14026 = eq(_T_14025, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_14027 = and(_T_14024, _T_14026) @[ifu_bp_ctl.scala 442:45] - node _T_14028 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14029 = eq(_T_14028, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_14030 = or(_T_14029, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14031 = and(_T_14027, _T_14030) @[ifu_bp_ctl.scala 442:110] - node _T_14032 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14033 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14034 = eq(_T_14033, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_14035 = and(_T_14032, _T_14034) @[ifu_bp_ctl.scala 443:22] - node _T_14036 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14037 = eq(_T_14036, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_14038 = or(_T_14037, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14039 = and(_T_14035, _T_14038) @[ifu_bp_ctl.scala 443:87] - node _T_14040 = or(_T_14031, _T_14039) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][10][8] <= _T_14040 @[ifu_bp_ctl.scala 442:27] - node _T_14041 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14042 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14043 = eq(_T_14042, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_14044 = and(_T_14041, _T_14043) @[ifu_bp_ctl.scala 442:45] - node _T_14045 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14046 = eq(_T_14045, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_14047 = or(_T_14046, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14048 = and(_T_14044, _T_14047) @[ifu_bp_ctl.scala 442:110] - node _T_14049 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14050 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14051 = eq(_T_14050, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_14052 = and(_T_14049, _T_14051) @[ifu_bp_ctl.scala 443:22] - node _T_14053 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14054 = eq(_T_14053, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_14055 = or(_T_14054, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14056 = and(_T_14052, _T_14055) @[ifu_bp_ctl.scala 443:87] - node _T_14057 = or(_T_14048, _T_14056) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][10][9] <= _T_14057 @[ifu_bp_ctl.scala 442:27] - node _T_14058 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14059 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14060 = eq(_T_14059, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_14061 = and(_T_14058, _T_14060) @[ifu_bp_ctl.scala 442:45] - node _T_14062 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14063 = eq(_T_14062, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_14064 = or(_T_14063, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14065 = and(_T_14061, _T_14064) @[ifu_bp_ctl.scala 442:110] - node _T_14066 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14067 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14068 = eq(_T_14067, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_14069 = and(_T_14066, _T_14068) @[ifu_bp_ctl.scala 443:22] - node _T_14070 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14071 = eq(_T_14070, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_14072 = or(_T_14071, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14073 = and(_T_14069, _T_14072) @[ifu_bp_ctl.scala 443:87] - node _T_14074 = or(_T_14065, _T_14073) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][10][10] <= _T_14074 @[ifu_bp_ctl.scala 442:27] - node _T_14075 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14076 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14077 = eq(_T_14076, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_14078 = and(_T_14075, _T_14077) @[ifu_bp_ctl.scala 442:45] - node _T_14079 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14080 = eq(_T_14079, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_14081 = or(_T_14080, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14082 = and(_T_14078, _T_14081) @[ifu_bp_ctl.scala 442:110] - node _T_14083 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14084 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14085 = eq(_T_14084, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_14086 = and(_T_14083, _T_14085) @[ifu_bp_ctl.scala 443:22] - node _T_14087 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14088 = eq(_T_14087, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_14089 = or(_T_14088, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14090 = and(_T_14086, _T_14089) @[ifu_bp_ctl.scala 443:87] - node _T_14091 = or(_T_14082, _T_14090) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][10][11] <= _T_14091 @[ifu_bp_ctl.scala 442:27] - node _T_14092 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14093 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14094 = eq(_T_14093, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_14095 = and(_T_14092, _T_14094) @[ifu_bp_ctl.scala 442:45] - node _T_14096 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14097 = eq(_T_14096, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_14098 = or(_T_14097, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14099 = and(_T_14095, _T_14098) @[ifu_bp_ctl.scala 442:110] - node _T_14100 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14101 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14102 = eq(_T_14101, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_14103 = and(_T_14100, _T_14102) @[ifu_bp_ctl.scala 443:22] - node _T_14104 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14105 = eq(_T_14104, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_14106 = or(_T_14105, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14107 = and(_T_14103, _T_14106) @[ifu_bp_ctl.scala 443:87] - node _T_14108 = or(_T_14099, _T_14107) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][10][12] <= _T_14108 @[ifu_bp_ctl.scala 442:27] - node _T_14109 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14110 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14111 = eq(_T_14110, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_14112 = and(_T_14109, _T_14111) @[ifu_bp_ctl.scala 442:45] - node _T_14113 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14114 = eq(_T_14113, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_14115 = or(_T_14114, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14116 = and(_T_14112, _T_14115) @[ifu_bp_ctl.scala 442:110] - node _T_14117 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14118 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14119 = eq(_T_14118, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_14120 = and(_T_14117, _T_14119) @[ifu_bp_ctl.scala 443:22] - node _T_14121 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14122 = eq(_T_14121, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_14123 = or(_T_14122, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14124 = and(_T_14120, _T_14123) @[ifu_bp_ctl.scala 443:87] - node _T_14125 = or(_T_14116, _T_14124) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][10][13] <= _T_14125 @[ifu_bp_ctl.scala 442:27] - node _T_14126 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14127 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14128 = eq(_T_14127, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_14129 = and(_T_14126, _T_14128) @[ifu_bp_ctl.scala 442:45] - node _T_14130 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14131 = eq(_T_14130, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_14132 = or(_T_14131, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14133 = and(_T_14129, _T_14132) @[ifu_bp_ctl.scala 442:110] - node _T_14134 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14135 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14136 = eq(_T_14135, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_14137 = and(_T_14134, _T_14136) @[ifu_bp_ctl.scala 443:22] - node _T_14138 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14139 = eq(_T_14138, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_14140 = or(_T_14139, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14141 = and(_T_14137, _T_14140) @[ifu_bp_ctl.scala 443:87] - node _T_14142 = or(_T_14133, _T_14141) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][10][14] <= _T_14142 @[ifu_bp_ctl.scala 442:27] - node _T_14143 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14144 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14145 = eq(_T_14144, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_14146 = and(_T_14143, _T_14145) @[ifu_bp_ctl.scala 442:45] - node _T_14147 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14148 = eq(_T_14147, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_14149 = or(_T_14148, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14150 = and(_T_14146, _T_14149) @[ifu_bp_ctl.scala 442:110] - node _T_14151 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14152 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14153 = eq(_T_14152, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_14154 = and(_T_14151, _T_14153) @[ifu_bp_ctl.scala 443:22] - node _T_14155 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14156 = eq(_T_14155, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_14157 = or(_T_14156, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14158 = and(_T_14154, _T_14157) @[ifu_bp_ctl.scala 443:87] - node _T_14159 = or(_T_14150, _T_14158) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][10][15] <= _T_14159 @[ifu_bp_ctl.scala 442:27] - node _T_14160 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14161 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14162 = eq(_T_14161, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_14163 = and(_T_14160, _T_14162) @[ifu_bp_ctl.scala 442:45] - node _T_14164 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14165 = eq(_T_14164, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_14166 = or(_T_14165, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14167 = and(_T_14163, _T_14166) @[ifu_bp_ctl.scala 442:110] - node _T_14168 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14169 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14170 = eq(_T_14169, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_14171 = and(_T_14168, _T_14170) @[ifu_bp_ctl.scala 443:22] - node _T_14172 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14173 = eq(_T_14172, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_14174 = or(_T_14173, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14175 = and(_T_14171, _T_14174) @[ifu_bp_ctl.scala 443:87] - node _T_14176 = or(_T_14167, _T_14175) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][11][0] <= _T_14176 @[ifu_bp_ctl.scala 442:27] - node _T_14177 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14178 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14179 = eq(_T_14178, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_14180 = and(_T_14177, _T_14179) @[ifu_bp_ctl.scala 442:45] - node _T_14181 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14182 = eq(_T_14181, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_14183 = or(_T_14182, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14184 = and(_T_14180, _T_14183) @[ifu_bp_ctl.scala 442:110] - node _T_14185 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14186 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14187 = eq(_T_14186, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_14188 = and(_T_14185, _T_14187) @[ifu_bp_ctl.scala 443:22] - node _T_14189 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14190 = eq(_T_14189, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_14191 = or(_T_14190, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14192 = and(_T_14188, _T_14191) @[ifu_bp_ctl.scala 443:87] - node _T_14193 = or(_T_14184, _T_14192) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][11][1] <= _T_14193 @[ifu_bp_ctl.scala 442:27] - node _T_14194 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14195 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14196 = eq(_T_14195, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_14197 = and(_T_14194, _T_14196) @[ifu_bp_ctl.scala 442:45] - node _T_14198 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14199 = eq(_T_14198, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_14200 = or(_T_14199, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14201 = and(_T_14197, _T_14200) @[ifu_bp_ctl.scala 442:110] - node _T_14202 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14203 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14204 = eq(_T_14203, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_14205 = and(_T_14202, _T_14204) @[ifu_bp_ctl.scala 443:22] - node _T_14206 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14207 = eq(_T_14206, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_14208 = or(_T_14207, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14209 = and(_T_14205, _T_14208) @[ifu_bp_ctl.scala 443:87] - node _T_14210 = or(_T_14201, _T_14209) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][11][2] <= _T_14210 @[ifu_bp_ctl.scala 442:27] - node _T_14211 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14212 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14213 = eq(_T_14212, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_14214 = and(_T_14211, _T_14213) @[ifu_bp_ctl.scala 442:45] - node _T_14215 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14216 = eq(_T_14215, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_14217 = or(_T_14216, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14218 = and(_T_14214, _T_14217) @[ifu_bp_ctl.scala 442:110] - node _T_14219 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14220 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14221 = eq(_T_14220, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_14222 = and(_T_14219, _T_14221) @[ifu_bp_ctl.scala 443:22] - node _T_14223 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14224 = eq(_T_14223, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_14225 = or(_T_14224, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14226 = and(_T_14222, _T_14225) @[ifu_bp_ctl.scala 443:87] - node _T_14227 = or(_T_14218, _T_14226) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][11][3] <= _T_14227 @[ifu_bp_ctl.scala 442:27] - node _T_14228 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14229 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14230 = eq(_T_14229, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_14231 = and(_T_14228, _T_14230) @[ifu_bp_ctl.scala 442:45] - node _T_14232 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14233 = eq(_T_14232, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_14234 = or(_T_14233, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14235 = and(_T_14231, _T_14234) @[ifu_bp_ctl.scala 442:110] - node _T_14236 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14237 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14238 = eq(_T_14237, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_14239 = and(_T_14236, _T_14238) @[ifu_bp_ctl.scala 443:22] - node _T_14240 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14241 = eq(_T_14240, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_14242 = or(_T_14241, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14243 = and(_T_14239, _T_14242) @[ifu_bp_ctl.scala 443:87] - node _T_14244 = or(_T_14235, _T_14243) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][11][4] <= _T_14244 @[ifu_bp_ctl.scala 442:27] - node _T_14245 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14246 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14247 = eq(_T_14246, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_14248 = and(_T_14245, _T_14247) @[ifu_bp_ctl.scala 442:45] - node _T_14249 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14250 = eq(_T_14249, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_14251 = or(_T_14250, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14252 = and(_T_14248, _T_14251) @[ifu_bp_ctl.scala 442:110] - node _T_14253 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14254 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14255 = eq(_T_14254, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_14256 = and(_T_14253, _T_14255) @[ifu_bp_ctl.scala 443:22] - node _T_14257 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14258 = eq(_T_14257, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_14259 = or(_T_14258, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14260 = and(_T_14256, _T_14259) @[ifu_bp_ctl.scala 443:87] - node _T_14261 = or(_T_14252, _T_14260) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][11][5] <= _T_14261 @[ifu_bp_ctl.scala 442:27] - node _T_14262 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14263 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14264 = eq(_T_14263, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_14265 = and(_T_14262, _T_14264) @[ifu_bp_ctl.scala 442:45] - node _T_14266 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14267 = eq(_T_14266, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_14268 = or(_T_14267, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14269 = and(_T_14265, _T_14268) @[ifu_bp_ctl.scala 442:110] - node _T_14270 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14271 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14272 = eq(_T_14271, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_14273 = and(_T_14270, _T_14272) @[ifu_bp_ctl.scala 443:22] - node _T_14274 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14275 = eq(_T_14274, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_14276 = or(_T_14275, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14277 = and(_T_14273, _T_14276) @[ifu_bp_ctl.scala 443:87] - node _T_14278 = or(_T_14269, _T_14277) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][11][6] <= _T_14278 @[ifu_bp_ctl.scala 442:27] - node _T_14279 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14280 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14281 = eq(_T_14280, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_14282 = and(_T_14279, _T_14281) @[ifu_bp_ctl.scala 442:45] - node _T_14283 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14284 = eq(_T_14283, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_14285 = or(_T_14284, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14286 = and(_T_14282, _T_14285) @[ifu_bp_ctl.scala 442:110] - node _T_14287 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14288 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14289 = eq(_T_14288, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_14290 = and(_T_14287, _T_14289) @[ifu_bp_ctl.scala 443:22] - node _T_14291 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14292 = eq(_T_14291, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_14293 = or(_T_14292, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14294 = and(_T_14290, _T_14293) @[ifu_bp_ctl.scala 443:87] - node _T_14295 = or(_T_14286, _T_14294) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][11][7] <= _T_14295 @[ifu_bp_ctl.scala 442:27] - node _T_14296 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14297 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14298 = eq(_T_14297, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_14299 = and(_T_14296, _T_14298) @[ifu_bp_ctl.scala 442:45] - node _T_14300 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14301 = eq(_T_14300, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_14302 = or(_T_14301, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14303 = and(_T_14299, _T_14302) @[ifu_bp_ctl.scala 442:110] - node _T_14304 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14305 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14306 = eq(_T_14305, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_14307 = and(_T_14304, _T_14306) @[ifu_bp_ctl.scala 443:22] - node _T_14308 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14309 = eq(_T_14308, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_14310 = or(_T_14309, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14311 = and(_T_14307, _T_14310) @[ifu_bp_ctl.scala 443:87] - node _T_14312 = or(_T_14303, _T_14311) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][11][8] <= _T_14312 @[ifu_bp_ctl.scala 442:27] - node _T_14313 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14314 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14315 = eq(_T_14314, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_14316 = and(_T_14313, _T_14315) @[ifu_bp_ctl.scala 442:45] - node _T_14317 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14318 = eq(_T_14317, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_14319 = or(_T_14318, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14320 = and(_T_14316, _T_14319) @[ifu_bp_ctl.scala 442:110] - node _T_14321 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14322 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14323 = eq(_T_14322, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_14324 = and(_T_14321, _T_14323) @[ifu_bp_ctl.scala 443:22] - node _T_14325 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14326 = eq(_T_14325, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_14327 = or(_T_14326, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14328 = and(_T_14324, _T_14327) @[ifu_bp_ctl.scala 443:87] - node _T_14329 = or(_T_14320, _T_14328) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][11][9] <= _T_14329 @[ifu_bp_ctl.scala 442:27] - node _T_14330 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14331 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14332 = eq(_T_14331, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_14333 = and(_T_14330, _T_14332) @[ifu_bp_ctl.scala 442:45] - node _T_14334 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14335 = eq(_T_14334, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_14336 = or(_T_14335, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14337 = and(_T_14333, _T_14336) @[ifu_bp_ctl.scala 442:110] - node _T_14338 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14339 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14340 = eq(_T_14339, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_14341 = and(_T_14338, _T_14340) @[ifu_bp_ctl.scala 443:22] - node _T_14342 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14343 = eq(_T_14342, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_14344 = or(_T_14343, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14345 = and(_T_14341, _T_14344) @[ifu_bp_ctl.scala 443:87] - node _T_14346 = or(_T_14337, _T_14345) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][11][10] <= _T_14346 @[ifu_bp_ctl.scala 442:27] - node _T_14347 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14348 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14349 = eq(_T_14348, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_14350 = and(_T_14347, _T_14349) @[ifu_bp_ctl.scala 442:45] - node _T_14351 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14352 = eq(_T_14351, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_14353 = or(_T_14352, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14354 = and(_T_14350, _T_14353) @[ifu_bp_ctl.scala 442:110] - node _T_14355 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14356 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14357 = eq(_T_14356, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_14358 = and(_T_14355, _T_14357) @[ifu_bp_ctl.scala 443:22] - node _T_14359 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14360 = eq(_T_14359, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_14361 = or(_T_14360, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14362 = and(_T_14358, _T_14361) @[ifu_bp_ctl.scala 443:87] - node _T_14363 = or(_T_14354, _T_14362) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][11][11] <= _T_14363 @[ifu_bp_ctl.scala 442:27] - node _T_14364 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14365 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14366 = eq(_T_14365, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_14367 = and(_T_14364, _T_14366) @[ifu_bp_ctl.scala 442:45] - node _T_14368 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14369 = eq(_T_14368, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_14370 = or(_T_14369, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14371 = and(_T_14367, _T_14370) @[ifu_bp_ctl.scala 442:110] - node _T_14372 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14373 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14374 = eq(_T_14373, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_14375 = and(_T_14372, _T_14374) @[ifu_bp_ctl.scala 443:22] - node _T_14376 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14377 = eq(_T_14376, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_14378 = or(_T_14377, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14379 = and(_T_14375, _T_14378) @[ifu_bp_ctl.scala 443:87] - node _T_14380 = or(_T_14371, _T_14379) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][11][12] <= _T_14380 @[ifu_bp_ctl.scala 442:27] - node _T_14381 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14382 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14383 = eq(_T_14382, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_14384 = and(_T_14381, _T_14383) @[ifu_bp_ctl.scala 442:45] - node _T_14385 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14386 = eq(_T_14385, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_14387 = or(_T_14386, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14388 = and(_T_14384, _T_14387) @[ifu_bp_ctl.scala 442:110] - node _T_14389 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14390 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14391 = eq(_T_14390, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_14392 = and(_T_14389, _T_14391) @[ifu_bp_ctl.scala 443:22] - node _T_14393 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14394 = eq(_T_14393, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_14395 = or(_T_14394, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14396 = and(_T_14392, _T_14395) @[ifu_bp_ctl.scala 443:87] - node _T_14397 = or(_T_14388, _T_14396) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][11][13] <= _T_14397 @[ifu_bp_ctl.scala 442:27] - node _T_14398 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14399 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14400 = eq(_T_14399, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_14401 = and(_T_14398, _T_14400) @[ifu_bp_ctl.scala 442:45] - node _T_14402 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14403 = eq(_T_14402, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_14404 = or(_T_14403, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14405 = and(_T_14401, _T_14404) @[ifu_bp_ctl.scala 442:110] - node _T_14406 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14407 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14408 = eq(_T_14407, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_14409 = and(_T_14406, _T_14408) @[ifu_bp_ctl.scala 443:22] - node _T_14410 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14411 = eq(_T_14410, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_14412 = or(_T_14411, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14413 = and(_T_14409, _T_14412) @[ifu_bp_ctl.scala 443:87] - node _T_14414 = or(_T_14405, _T_14413) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][11][14] <= _T_14414 @[ifu_bp_ctl.scala 442:27] - node _T_14415 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14416 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14417 = eq(_T_14416, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_14418 = and(_T_14415, _T_14417) @[ifu_bp_ctl.scala 442:45] - node _T_14419 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14420 = eq(_T_14419, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_14421 = or(_T_14420, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14422 = and(_T_14418, _T_14421) @[ifu_bp_ctl.scala 442:110] - node _T_14423 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14424 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14425 = eq(_T_14424, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_14426 = and(_T_14423, _T_14425) @[ifu_bp_ctl.scala 443:22] - node _T_14427 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14428 = eq(_T_14427, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_14429 = or(_T_14428, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14430 = and(_T_14426, _T_14429) @[ifu_bp_ctl.scala 443:87] - node _T_14431 = or(_T_14422, _T_14430) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][11][15] <= _T_14431 @[ifu_bp_ctl.scala 442:27] - node _T_14432 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14433 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14434 = eq(_T_14433, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_14435 = and(_T_14432, _T_14434) @[ifu_bp_ctl.scala 442:45] - node _T_14436 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14437 = eq(_T_14436, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_14438 = or(_T_14437, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14439 = and(_T_14435, _T_14438) @[ifu_bp_ctl.scala 442:110] - node _T_14440 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14441 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14442 = eq(_T_14441, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_14443 = and(_T_14440, _T_14442) @[ifu_bp_ctl.scala 443:22] - node _T_14444 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14445 = eq(_T_14444, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_14446 = or(_T_14445, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14447 = and(_T_14443, _T_14446) @[ifu_bp_ctl.scala 443:87] - node _T_14448 = or(_T_14439, _T_14447) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][12][0] <= _T_14448 @[ifu_bp_ctl.scala 442:27] - node _T_14449 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14450 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14451 = eq(_T_14450, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_14452 = and(_T_14449, _T_14451) @[ifu_bp_ctl.scala 442:45] - node _T_14453 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14454 = eq(_T_14453, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_14455 = or(_T_14454, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14456 = and(_T_14452, _T_14455) @[ifu_bp_ctl.scala 442:110] - node _T_14457 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14458 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14459 = eq(_T_14458, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_14460 = and(_T_14457, _T_14459) @[ifu_bp_ctl.scala 443:22] - node _T_14461 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14462 = eq(_T_14461, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_14463 = or(_T_14462, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14464 = and(_T_14460, _T_14463) @[ifu_bp_ctl.scala 443:87] - node _T_14465 = or(_T_14456, _T_14464) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][12][1] <= _T_14465 @[ifu_bp_ctl.scala 442:27] - node _T_14466 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14467 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14468 = eq(_T_14467, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_14469 = and(_T_14466, _T_14468) @[ifu_bp_ctl.scala 442:45] - node _T_14470 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14471 = eq(_T_14470, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_14472 = or(_T_14471, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14473 = and(_T_14469, _T_14472) @[ifu_bp_ctl.scala 442:110] - node _T_14474 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14475 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14476 = eq(_T_14475, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_14477 = and(_T_14474, _T_14476) @[ifu_bp_ctl.scala 443:22] - node _T_14478 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14479 = eq(_T_14478, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_14480 = or(_T_14479, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14481 = and(_T_14477, _T_14480) @[ifu_bp_ctl.scala 443:87] - node _T_14482 = or(_T_14473, _T_14481) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][12][2] <= _T_14482 @[ifu_bp_ctl.scala 442:27] - node _T_14483 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14484 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14485 = eq(_T_14484, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_14486 = and(_T_14483, _T_14485) @[ifu_bp_ctl.scala 442:45] - node _T_14487 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14488 = eq(_T_14487, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_14489 = or(_T_14488, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14490 = and(_T_14486, _T_14489) @[ifu_bp_ctl.scala 442:110] - node _T_14491 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14492 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14493 = eq(_T_14492, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_14494 = and(_T_14491, _T_14493) @[ifu_bp_ctl.scala 443:22] - node _T_14495 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14496 = eq(_T_14495, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_14497 = or(_T_14496, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14498 = and(_T_14494, _T_14497) @[ifu_bp_ctl.scala 443:87] - node _T_14499 = or(_T_14490, _T_14498) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][12][3] <= _T_14499 @[ifu_bp_ctl.scala 442:27] - node _T_14500 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14501 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14502 = eq(_T_14501, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_14503 = and(_T_14500, _T_14502) @[ifu_bp_ctl.scala 442:45] - node _T_14504 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14505 = eq(_T_14504, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_14506 = or(_T_14505, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14507 = and(_T_14503, _T_14506) @[ifu_bp_ctl.scala 442:110] - node _T_14508 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14509 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14510 = eq(_T_14509, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_14511 = and(_T_14508, _T_14510) @[ifu_bp_ctl.scala 443:22] - node _T_14512 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14513 = eq(_T_14512, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_14514 = or(_T_14513, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14515 = and(_T_14511, _T_14514) @[ifu_bp_ctl.scala 443:87] - node _T_14516 = or(_T_14507, _T_14515) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][12][4] <= _T_14516 @[ifu_bp_ctl.scala 442:27] - node _T_14517 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14518 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14519 = eq(_T_14518, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_14520 = and(_T_14517, _T_14519) @[ifu_bp_ctl.scala 442:45] - node _T_14521 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14522 = eq(_T_14521, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_14523 = or(_T_14522, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14524 = and(_T_14520, _T_14523) @[ifu_bp_ctl.scala 442:110] - node _T_14525 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14526 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14527 = eq(_T_14526, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_14528 = and(_T_14525, _T_14527) @[ifu_bp_ctl.scala 443:22] - node _T_14529 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14530 = eq(_T_14529, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_14531 = or(_T_14530, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14532 = and(_T_14528, _T_14531) @[ifu_bp_ctl.scala 443:87] - node _T_14533 = or(_T_14524, _T_14532) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][12][5] <= _T_14533 @[ifu_bp_ctl.scala 442:27] - node _T_14534 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14535 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14536 = eq(_T_14535, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_14537 = and(_T_14534, _T_14536) @[ifu_bp_ctl.scala 442:45] - node _T_14538 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14539 = eq(_T_14538, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_14540 = or(_T_14539, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14541 = and(_T_14537, _T_14540) @[ifu_bp_ctl.scala 442:110] - node _T_14542 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14543 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14544 = eq(_T_14543, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_14545 = and(_T_14542, _T_14544) @[ifu_bp_ctl.scala 443:22] - node _T_14546 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14547 = eq(_T_14546, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_14548 = or(_T_14547, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14549 = and(_T_14545, _T_14548) @[ifu_bp_ctl.scala 443:87] - node _T_14550 = or(_T_14541, _T_14549) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][12][6] <= _T_14550 @[ifu_bp_ctl.scala 442:27] - node _T_14551 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14552 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14553 = eq(_T_14552, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_14554 = and(_T_14551, _T_14553) @[ifu_bp_ctl.scala 442:45] - node _T_14555 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14556 = eq(_T_14555, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_14557 = or(_T_14556, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14558 = and(_T_14554, _T_14557) @[ifu_bp_ctl.scala 442:110] - node _T_14559 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14560 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14561 = eq(_T_14560, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_14562 = and(_T_14559, _T_14561) @[ifu_bp_ctl.scala 443:22] - node _T_14563 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14564 = eq(_T_14563, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_14565 = or(_T_14564, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14566 = and(_T_14562, _T_14565) @[ifu_bp_ctl.scala 443:87] - node _T_14567 = or(_T_14558, _T_14566) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][12][7] <= _T_14567 @[ifu_bp_ctl.scala 442:27] - node _T_14568 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14569 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14570 = eq(_T_14569, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_14571 = and(_T_14568, _T_14570) @[ifu_bp_ctl.scala 442:45] - node _T_14572 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14573 = eq(_T_14572, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_14574 = or(_T_14573, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14575 = and(_T_14571, _T_14574) @[ifu_bp_ctl.scala 442:110] - node _T_14576 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14577 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14578 = eq(_T_14577, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_14579 = and(_T_14576, _T_14578) @[ifu_bp_ctl.scala 443:22] - node _T_14580 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14581 = eq(_T_14580, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_14582 = or(_T_14581, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14583 = and(_T_14579, _T_14582) @[ifu_bp_ctl.scala 443:87] - node _T_14584 = or(_T_14575, _T_14583) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][12][8] <= _T_14584 @[ifu_bp_ctl.scala 442:27] - node _T_14585 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14586 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14587 = eq(_T_14586, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_14588 = and(_T_14585, _T_14587) @[ifu_bp_ctl.scala 442:45] - node _T_14589 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14590 = eq(_T_14589, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_14591 = or(_T_14590, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14592 = and(_T_14588, _T_14591) @[ifu_bp_ctl.scala 442:110] - node _T_14593 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14594 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14595 = eq(_T_14594, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_14596 = and(_T_14593, _T_14595) @[ifu_bp_ctl.scala 443:22] - node _T_14597 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14598 = eq(_T_14597, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_14599 = or(_T_14598, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14600 = and(_T_14596, _T_14599) @[ifu_bp_ctl.scala 443:87] - node _T_14601 = or(_T_14592, _T_14600) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][12][9] <= _T_14601 @[ifu_bp_ctl.scala 442:27] - node _T_14602 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14603 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14604 = eq(_T_14603, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_14605 = and(_T_14602, _T_14604) @[ifu_bp_ctl.scala 442:45] - node _T_14606 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14607 = eq(_T_14606, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_14608 = or(_T_14607, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14609 = and(_T_14605, _T_14608) @[ifu_bp_ctl.scala 442:110] - node _T_14610 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14611 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14612 = eq(_T_14611, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_14613 = and(_T_14610, _T_14612) @[ifu_bp_ctl.scala 443:22] - node _T_14614 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14615 = eq(_T_14614, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_14616 = or(_T_14615, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14617 = and(_T_14613, _T_14616) @[ifu_bp_ctl.scala 443:87] - node _T_14618 = or(_T_14609, _T_14617) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][12][10] <= _T_14618 @[ifu_bp_ctl.scala 442:27] - node _T_14619 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14620 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14621 = eq(_T_14620, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_14622 = and(_T_14619, _T_14621) @[ifu_bp_ctl.scala 442:45] - node _T_14623 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14624 = eq(_T_14623, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_14625 = or(_T_14624, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14626 = and(_T_14622, _T_14625) @[ifu_bp_ctl.scala 442:110] - node _T_14627 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14628 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14629 = eq(_T_14628, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_14630 = and(_T_14627, _T_14629) @[ifu_bp_ctl.scala 443:22] - node _T_14631 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14632 = eq(_T_14631, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_14633 = or(_T_14632, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14634 = and(_T_14630, _T_14633) @[ifu_bp_ctl.scala 443:87] - node _T_14635 = or(_T_14626, _T_14634) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][12][11] <= _T_14635 @[ifu_bp_ctl.scala 442:27] - node _T_14636 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14637 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14638 = eq(_T_14637, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_14639 = and(_T_14636, _T_14638) @[ifu_bp_ctl.scala 442:45] - node _T_14640 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14641 = eq(_T_14640, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_14642 = or(_T_14641, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14643 = and(_T_14639, _T_14642) @[ifu_bp_ctl.scala 442:110] - node _T_14644 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14645 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14646 = eq(_T_14645, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_14647 = and(_T_14644, _T_14646) @[ifu_bp_ctl.scala 443:22] - node _T_14648 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14649 = eq(_T_14648, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_14650 = or(_T_14649, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14651 = and(_T_14647, _T_14650) @[ifu_bp_ctl.scala 443:87] - node _T_14652 = or(_T_14643, _T_14651) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][12][12] <= _T_14652 @[ifu_bp_ctl.scala 442:27] - node _T_14653 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14654 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14655 = eq(_T_14654, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_14656 = and(_T_14653, _T_14655) @[ifu_bp_ctl.scala 442:45] - node _T_14657 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14658 = eq(_T_14657, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_14659 = or(_T_14658, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14660 = and(_T_14656, _T_14659) @[ifu_bp_ctl.scala 442:110] - node _T_14661 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14662 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14663 = eq(_T_14662, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_14664 = and(_T_14661, _T_14663) @[ifu_bp_ctl.scala 443:22] - node _T_14665 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14666 = eq(_T_14665, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_14667 = or(_T_14666, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14668 = and(_T_14664, _T_14667) @[ifu_bp_ctl.scala 443:87] - node _T_14669 = or(_T_14660, _T_14668) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][12][13] <= _T_14669 @[ifu_bp_ctl.scala 442:27] - node _T_14670 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14671 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14672 = eq(_T_14671, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_14673 = and(_T_14670, _T_14672) @[ifu_bp_ctl.scala 442:45] - node _T_14674 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14675 = eq(_T_14674, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_14676 = or(_T_14675, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14677 = and(_T_14673, _T_14676) @[ifu_bp_ctl.scala 442:110] - node _T_14678 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14679 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14680 = eq(_T_14679, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_14681 = and(_T_14678, _T_14680) @[ifu_bp_ctl.scala 443:22] - node _T_14682 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14683 = eq(_T_14682, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_14684 = or(_T_14683, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14685 = and(_T_14681, _T_14684) @[ifu_bp_ctl.scala 443:87] - node _T_14686 = or(_T_14677, _T_14685) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][12][14] <= _T_14686 @[ifu_bp_ctl.scala 442:27] - node _T_14687 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14688 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14689 = eq(_T_14688, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_14690 = and(_T_14687, _T_14689) @[ifu_bp_ctl.scala 442:45] - node _T_14691 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14692 = eq(_T_14691, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_14693 = or(_T_14692, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14694 = and(_T_14690, _T_14693) @[ifu_bp_ctl.scala 442:110] - node _T_14695 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14696 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14697 = eq(_T_14696, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_14698 = and(_T_14695, _T_14697) @[ifu_bp_ctl.scala 443:22] - node _T_14699 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14700 = eq(_T_14699, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_14701 = or(_T_14700, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14702 = and(_T_14698, _T_14701) @[ifu_bp_ctl.scala 443:87] - node _T_14703 = or(_T_14694, _T_14702) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][12][15] <= _T_14703 @[ifu_bp_ctl.scala 442:27] - node _T_14704 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14705 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14706 = eq(_T_14705, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_14707 = and(_T_14704, _T_14706) @[ifu_bp_ctl.scala 442:45] - node _T_14708 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14709 = eq(_T_14708, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_14710 = or(_T_14709, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14711 = and(_T_14707, _T_14710) @[ifu_bp_ctl.scala 442:110] - node _T_14712 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14713 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14714 = eq(_T_14713, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_14715 = and(_T_14712, _T_14714) @[ifu_bp_ctl.scala 443:22] - node _T_14716 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14717 = eq(_T_14716, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_14718 = or(_T_14717, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14719 = and(_T_14715, _T_14718) @[ifu_bp_ctl.scala 443:87] - node _T_14720 = or(_T_14711, _T_14719) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][13][0] <= _T_14720 @[ifu_bp_ctl.scala 442:27] - node _T_14721 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14722 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14723 = eq(_T_14722, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_14724 = and(_T_14721, _T_14723) @[ifu_bp_ctl.scala 442:45] - node _T_14725 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14726 = eq(_T_14725, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_14727 = or(_T_14726, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14728 = and(_T_14724, _T_14727) @[ifu_bp_ctl.scala 442:110] - node _T_14729 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14730 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14731 = eq(_T_14730, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_14732 = and(_T_14729, _T_14731) @[ifu_bp_ctl.scala 443:22] - node _T_14733 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14734 = eq(_T_14733, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_14735 = or(_T_14734, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14736 = and(_T_14732, _T_14735) @[ifu_bp_ctl.scala 443:87] - node _T_14737 = or(_T_14728, _T_14736) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][13][1] <= _T_14737 @[ifu_bp_ctl.scala 442:27] - node _T_14738 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14739 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14740 = eq(_T_14739, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_14741 = and(_T_14738, _T_14740) @[ifu_bp_ctl.scala 442:45] - node _T_14742 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14743 = eq(_T_14742, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_14744 = or(_T_14743, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14745 = and(_T_14741, _T_14744) @[ifu_bp_ctl.scala 442:110] - node _T_14746 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14747 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14748 = eq(_T_14747, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_14749 = and(_T_14746, _T_14748) @[ifu_bp_ctl.scala 443:22] - node _T_14750 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14751 = eq(_T_14750, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_14752 = or(_T_14751, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14753 = and(_T_14749, _T_14752) @[ifu_bp_ctl.scala 443:87] - node _T_14754 = or(_T_14745, _T_14753) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][13][2] <= _T_14754 @[ifu_bp_ctl.scala 442:27] - node _T_14755 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14756 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14757 = eq(_T_14756, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_14758 = and(_T_14755, _T_14757) @[ifu_bp_ctl.scala 442:45] - node _T_14759 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14760 = eq(_T_14759, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_14761 = or(_T_14760, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14762 = and(_T_14758, _T_14761) @[ifu_bp_ctl.scala 442:110] - node _T_14763 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14764 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14765 = eq(_T_14764, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_14766 = and(_T_14763, _T_14765) @[ifu_bp_ctl.scala 443:22] - node _T_14767 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14768 = eq(_T_14767, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_14769 = or(_T_14768, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14770 = and(_T_14766, _T_14769) @[ifu_bp_ctl.scala 443:87] - node _T_14771 = or(_T_14762, _T_14770) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][13][3] <= _T_14771 @[ifu_bp_ctl.scala 442:27] - node _T_14772 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14773 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14774 = eq(_T_14773, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_14775 = and(_T_14772, _T_14774) @[ifu_bp_ctl.scala 442:45] - node _T_14776 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14777 = eq(_T_14776, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_14778 = or(_T_14777, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14779 = and(_T_14775, _T_14778) @[ifu_bp_ctl.scala 442:110] - node _T_14780 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14781 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14782 = eq(_T_14781, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_14783 = and(_T_14780, _T_14782) @[ifu_bp_ctl.scala 443:22] - node _T_14784 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14785 = eq(_T_14784, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_14786 = or(_T_14785, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14787 = and(_T_14783, _T_14786) @[ifu_bp_ctl.scala 443:87] - node _T_14788 = or(_T_14779, _T_14787) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][13][4] <= _T_14788 @[ifu_bp_ctl.scala 442:27] - node _T_14789 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14790 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14791 = eq(_T_14790, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_14792 = and(_T_14789, _T_14791) @[ifu_bp_ctl.scala 442:45] - node _T_14793 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14794 = eq(_T_14793, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_14795 = or(_T_14794, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14796 = and(_T_14792, _T_14795) @[ifu_bp_ctl.scala 442:110] - node _T_14797 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14798 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14799 = eq(_T_14798, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_14800 = and(_T_14797, _T_14799) @[ifu_bp_ctl.scala 443:22] - node _T_14801 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14802 = eq(_T_14801, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_14803 = or(_T_14802, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14804 = and(_T_14800, _T_14803) @[ifu_bp_ctl.scala 443:87] - node _T_14805 = or(_T_14796, _T_14804) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][13][5] <= _T_14805 @[ifu_bp_ctl.scala 442:27] - node _T_14806 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14807 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14808 = eq(_T_14807, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_14809 = and(_T_14806, _T_14808) @[ifu_bp_ctl.scala 442:45] - node _T_14810 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14811 = eq(_T_14810, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_14812 = or(_T_14811, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14813 = and(_T_14809, _T_14812) @[ifu_bp_ctl.scala 442:110] - node _T_14814 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14815 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14816 = eq(_T_14815, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_14817 = and(_T_14814, _T_14816) @[ifu_bp_ctl.scala 443:22] - node _T_14818 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14819 = eq(_T_14818, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_14820 = or(_T_14819, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14821 = and(_T_14817, _T_14820) @[ifu_bp_ctl.scala 443:87] - node _T_14822 = or(_T_14813, _T_14821) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][13][6] <= _T_14822 @[ifu_bp_ctl.scala 442:27] - node _T_14823 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14824 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14825 = eq(_T_14824, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_14826 = and(_T_14823, _T_14825) @[ifu_bp_ctl.scala 442:45] - node _T_14827 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14828 = eq(_T_14827, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_14829 = or(_T_14828, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14830 = and(_T_14826, _T_14829) @[ifu_bp_ctl.scala 442:110] - node _T_14831 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14832 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14833 = eq(_T_14832, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_14834 = and(_T_14831, _T_14833) @[ifu_bp_ctl.scala 443:22] - node _T_14835 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14836 = eq(_T_14835, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_14837 = or(_T_14836, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14838 = and(_T_14834, _T_14837) @[ifu_bp_ctl.scala 443:87] - node _T_14839 = or(_T_14830, _T_14838) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][13][7] <= _T_14839 @[ifu_bp_ctl.scala 442:27] - node _T_14840 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14841 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14842 = eq(_T_14841, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_14843 = and(_T_14840, _T_14842) @[ifu_bp_ctl.scala 442:45] - node _T_14844 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14845 = eq(_T_14844, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_14846 = or(_T_14845, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14847 = and(_T_14843, _T_14846) @[ifu_bp_ctl.scala 442:110] - node _T_14848 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14849 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14850 = eq(_T_14849, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_14851 = and(_T_14848, _T_14850) @[ifu_bp_ctl.scala 443:22] - node _T_14852 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14853 = eq(_T_14852, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_14854 = or(_T_14853, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14855 = and(_T_14851, _T_14854) @[ifu_bp_ctl.scala 443:87] - node _T_14856 = or(_T_14847, _T_14855) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][13][8] <= _T_14856 @[ifu_bp_ctl.scala 442:27] - node _T_14857 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14858 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14859 = eq(_T_14858, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_14860 = and(_T_14857, _T_14859) @[ifu_bp_ctl.scala 442:45] - node _T_14861 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14862 = eq(_T_14861, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_14863 = or(_T_14862, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14864 = and(_T_14860, _T_14863) @[ifu_bp_ctl.scala 442:110] - node _T_14865 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14866 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14867 = eq(_T_14866, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_14868 = and(_T_14865, _T_14867) @[ifu_bp_ctl.scala 443:22] - node _T_14869 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14870 = eq(_T_14869, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_14871 = or(_T_14870, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14872 = and(_T_14868, _T_14871) @[ifu_bp_ctl.scala 443:87] - node _T_14873 = or(_T_14864, _T_14872) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][13][9] <= _T_14873 @[ifu_bp_ctl.scala 442:27] - node _T_14874 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14875 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14876 = eq(_T_14875, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_14877 = and(_T_14874, _T_14876) @[ifu_bp_ctl.scala 442:45] - node _T_14878 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14879 = eq(_T_14878, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_14880 = or(_T_14879, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14881 = and(_T_14877, _T_14880) @[ifu_bp_ctl.scala 442:110] - node _T_14882 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14883 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14884 = eq(_T_14883, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_14885 = and(_T_14882, _T_14884) @[ifu_bp_ctl.scala 443:22] - node _T_14886 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14887 = eq(_T_14886, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_14888 = or(_T_14887, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14889 = and(_T_14885, _T_14888) @[ifu_bp_ctl.scala 443:87] - node _T_14890 = or(_T_14881, _T_14889) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][13][10] <= _T_14890 @[ifu_bp_ctl.scala 442:27] - node _T_14891 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14892 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14893 = eq(_T_14892, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_14894 = and(_T_14891, _T_14893) @[ifu_bp_ctl.scala 442:45] - node _T_14895 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14896 = eq(_T_14895, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_14897 = or(_T_14896, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14898 = and(_T_14894, _T_14897) @[ifu_bp_ctl.scala 442:110] - node _T_14899 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14900 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14901 = eq(_T_14900, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_14902 = and(_T_14899, _T_14901) @[ifu_bp_ctl.scala 443:22] - node _T_14903 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14904 = eq(_T_14903, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_14905 = or(_T_14904, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14906 = and(_T_14902, _T_14905) @[ifu_bp_ctl.scala 443:87] - node _T_14907 = or(_T_14898, _T_14906) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][13][11] <= _T_14907 @[ifu_bp_ctl.scala 442:27] - node _T_14908 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14909 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14910 = eq(_T_14909, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_14911 = and(_T_14908, _T_14910) @[ifu_bp_ctl.scala 442:45] - node _T_14912 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14913 = eq(_T_14912, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_14914 = or(_T_14913, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14915 = and(_T_14911, _T_14914) @[ifu_bp_ctl.scala 442:110] - node _T_14916 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14917 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14918 = eq(_T_14917, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_14919 = and(_T_14916, _T_14918) @[ifu_bp_ctl.scala 443:22] - node _T_14920 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14921 = eq(_T_14920, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_14922 = or(_T_14921, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14923 = and(_T_14919, _T_14922) @[ifu_bp_ctl.scala 443:87] - node _T_14924 = or(_T_14915, _T_14923) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][13][12] <= _T_14924 @[ifu_bp_ctl.scala 442:27] - node _T_14925 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14926 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14927 = eq(_T_14926, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_14928 = and(_T_14925, _T_14927) @[ifu_bp_ctl.scala 442:45] - node _T_14929 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14930 = eq(_T_14929, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_14931 = or(_T_14930, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14932 = and(_T_14928, _T_14931) @[ifu_bp_ctl.scala 442:110] - node _T_14933 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14934 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14935 = eq(_T_14934, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_14936 = and(_T_14933, _T_14935) @[ifu_bp_ctl.scala 443:22] - node _T_14937 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14938 = eq(_T_14937, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_14939 = or(_T_14938, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14940 = and(_T_14936, _T_14939) @[ifu_bp_ctl.scala 443:87] - node _T_14941 = or(_T_14932, _T_14940) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][13][13] <= _T_14941 @[ifu_bp_ctl.scala 442:27] - node _T_14942 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14943 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14944 = eq(_T_14943, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_14945 = and(_T_14942, _T_14944) @[ifu_bp_ctl.scala 442:45] - node _T_14946 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14947 = eq(_T_14946, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_14948 = or(_T_14947, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14949 = and(_T_14945, _T_14948) @[ifu_bp_ctl.scala 442:110] - node _T_14950 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14951 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14952 = eq(_T_14951, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_14953 = and(_T_14950, _T_14952) @[ifu_bp_ctl.scala 443:22] - node _T_14954 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14955 = eq(_T_14954, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_14956 = or(_T_14955, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14957 = and(_T_14953, _T_14956) @[ifu_bp_ctl.scala 443:87] - node _T_14958 = or(_T_14949, _T_14957) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][13][14] <= _T_14958 @[ifu_bp_ctl.scala 442:27] - node _T_14959 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14960 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14961 = eq(_T_14960, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_14962 = and(_T_14959, _T_14961) @[ifu_bp_ctl.scala 442:45] - node _T_14963 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14964 = eq(_T_14963, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_14965 = or(_T_14964, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14966 = and(_T_14962, _T_14965) @[ifu_bp_ctl.scala 442:110] - node _T_14967 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14968 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14969 = eq(_T_14968, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_14970 = and(_T_14967, _T_14969) @[ifu_bp_ctl.scala 443:22] - node _T_14971 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14972 = eq(_T_14971, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_14973 = or(_T_14972, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14974 = and(_T_14970, _T_14973) @[ifu_bp_ctl.scala 443:87] - node _T_14975 = or(_T_14966, _T_14974) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][13][15] <= _T_14975 @[ifu_bp_ctl.scala 442:27] - node _T_14976 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14977 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14978 = eq(_T_14977, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_14979 = and(_T_14976, _T_14978) @[ifu_bp_ctl.scala 442:45] - node _T_14980 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14981 = eq(_T_14980, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_14982 = or(_T_14981, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_14983 = and(_T_14979, _T_14982) @[ifu_bp_ctl.scala 442:110] - node _T_14984 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_14985 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_14986 = eq(_T_14985, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_14987 = and(_T_14984, _T_14986) @[ifu_bp_ctl.scala 443:22] - node _T_14988 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_14989 = eq(_T_14988, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_14990 = or(_T_14989, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_14991 = and(_T_14987, _T_14990) @[ifu_bp_ctl.scala 443:87] - node _T_14992 = or(_T_14983, _T_14991) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][14][0] <= _T_14992 @[ifu_bp_ctl.scala 442:27] - node _T_14993 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_14994 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_14995 = eq(_T_14994, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_14996 = and(_T_14993, _T_14995) @[ifu_bp_ctl.scala 442:45] - node _T_14997 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_14998 = eq(_T_14997, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_14999 = or(_T_14998, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15000 = and(_T_14996, _T_14999) @[ifu_bp_ctl.scala 442:110] - node _T_15001 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15002 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15003 = eq(_T_15002, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_15004 = and(_T_15001, _T_15003) @[ifu_bp_ctl.scala 443:22] - node _T_15005 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15006 = eq(_T_15005, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_15007 = or(_T_15006, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15008 = and(_T_15004, _T_15007) @[ifu_bp_ctl.scala 443:87] - node _T_15009 = or(_T_15000, _T_15008) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][14][1] <= _T_15009 @[ifu_bp_ctl.scala 442:27] - node _T_15010 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15011 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15012 = eq(_T_15011, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_15013 = and(_T_15010, _T_15012) @[ifu_bp_ctl.scala 442:45] - node _T_15014 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15015 = eq(_T_15014, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_15016 = or(_T_15015, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15017 = and(_T_15013, _T_15016) @[ifu_bp_ctl.scala 442:110] - node _T_15018 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15019 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15020 = eq(_T_15019, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_15021 = and(_T_15018, _T_15020) @[ifu_bp_ctl.scala 443:22] - node _T_15022 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15023 = eq(_T_15022, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_15024 = or(_T_15023, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15025 = and(_T_15021, _T_15024) @[ifu_bp_ctl.scala 443:87] - node _T_15026 = or(_T_15017, _T_15025) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][14][2] <= _T_15026 @[ifu_bp_ctl.scala 442:27] - node _T_15027 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15028 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15029 = eq(_T_15028, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_15030 = and(_T_15027, _T_15029) @[ifu_bp_ctl.scala 442:45] - node _T_15031 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15032 = eq(_T_15031, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_15033 = or(_T_15032, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15034 = and(_T_15030, _T_15033) @[ifu_bp_ctl.scala 442:110] - node _T_15035 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15036 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15037 = eq(_T_15036, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_15038 = and(_T_15035, _T_15037) @[ifu_bp_ctl.scala 443:22] - node _T_15039 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15040 = eq(_T_15039, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_15041 = or(_T_15040, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15042 = and(_T_15038, _T_15041) @[ifu_bp_ctl.scala 443:87] - node _T_15043 = or(_T_15034, _T_15042) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][14][3] <= _T_15043 @[ifu_bp_ctl.scala 442:27] - node _T_15044 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15045 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15046 = eq(_T_15045, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_15047 = and(_T_15044, _T_15046) @[ifu_bp_ctl.scala 442:45] - node _T_15048 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15049 = eq(_T_15048, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_15050 = or(_T_15049, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15051 = and(_T_15047, _T_15050) @[ifu_bp_ctl.scala 442:110] - node _T_15052 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15053 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15054 = eq(_T_15053, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_15055 = and(_T_15052, _T_15054) @[ifu_bp_ctl.scala 443:22] - node _T_15056 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15057 = eq(_T_15056, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_15058 = or(_T_15057, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15059 = and(_T_15055, _T_15058) @[ifu_bp_ctl.scala 443:87] - node _T_15060 = or(_T_15051, _T_15059) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][14][4] <= _T_15060 @[ifu_bp_ctl.scala 442:27] - node _T_15061 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15062 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15063 = eq(_T_15062, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_15064 = and(_T_15061, _T_15063) @[ifu_bp_ctl.scala 442:45] - node _T_15065 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15066 = eq(_T_15065, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_15067 = or(_T_15066, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15068 = and(_T_15064, _T_15067) @[ifu_bp_ctl.scala 442:110] - node _T_15069 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15070 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15071 = eq(_T_15070, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_15072 = and(_T_15069, _T_15071) @[ifu_bp_ctl.scala 443:22] - node _T_15073 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15074 = eq(_T_15073, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_15075 = or(_T_15074, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15076 = and(_T_15072, _T_15075) @[ifu_bp_ctl.scala 443:87] - node _T_15077 = or(_T_15068, _T_15076) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][14][5] <= _T_15077 @[ifu_bp_ctl.scala 442:27] - node _T_15078 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15079 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15080 = eq(_T_15079, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_15081 = and(_T_15078, _T_15080) @[ifu_bp_ctl.scala 442:45] - node _T_15082 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15083 = eq(_T_15082, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_15084 = or(_T_15083, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15085 = and(_T_15081, _T_15084) @[ifu_bp_ctl.scala 442:110] - node _T_15086 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15087 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15088 = eq(_T_15087, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_15089 = and(_T_15086, _T_15088) @[ifu_bp_ctl.scala 443:22] - node _T_15090 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15091 = eq(_T_15090, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_15092 = or(_T_15091, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15093 = and(_T_15089, _T_15092) @[ifu_bp_ctl.scala 443:87] - node _T_15094 = or(_T_15085, _T_15093) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][14][6] <= _T_15094 @[ifu_bp_ctl.scala 442:27] - node _T_15095 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15096 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15097 = eq(_T_15096, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_15098 = and(_T_15095, _T_15097) @[ifu_bp_ctl.scala 442:45] - node _T_15099 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15100 = eq(_T_15099, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_15101 = or(_T_15100, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15102 = and(_T_15098, _T_15101) @[ifu_bp_ctl.scala 442:110] - node _T_15103 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15104 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15105 = eq(_T_15104, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_15106 = and(_T_15103, _T_15105) @[ifu_bp_ctl.scala 443:22] - node _T_15107 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15108 = eq(_T_15107, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_15109 = or(_T_15108, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15110 = and(_T_15106, _T_15109) @[ifu_bp_ctl.scala 443:87] - node _T_15111 = or(_T_15102, _T_15110) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][14][7] <= _T_15111 @[ifu_bp_ctl.scala 442:27] - node _T_15112 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15113 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15114 = eq(_T_15113, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_15115 = and(_T_15112, _T_15114) @[ifu_bp_ctl.scala 442:45] - node _T_15116 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15117 = eq(_T_15116, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_15118 = or(_T_15117, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15119 = and(_T_15115, _T_15118) @[ifu_bp_ctl.scala 442:110] - node _T_15120 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15121 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15122 = eq(_T_15121, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_15123 = and(_T_15120, _T_15122) @[ifu_bp_ctl.scala 443:22] - node _T_15124 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15125 = eq(_T_15124, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_15126 = or(_T_15125, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15127 = and(_T_15123, _T_15126) @[ifu_bp_ctl.scala 443:87] - node _T_15128 = or(_T_15119, _T_15127) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][14][8] <= _T_15128 @[ifu_bp_ctl.scala 442:27] - node _T_15129 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15130 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15131 = eq(_T_15130, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_15132 = and(_T_15129, _T_15131) @[ifu_bp_ctl.scala 442:45] - node _T_15133 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15134 = eq(_T_15133, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_15135 = or(_T_15134, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15136 = and(_T_15132, _T_15135) @[ifu_bp_ctl.scala 442:110] - node _T_15137 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15138 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15139 = eq(_T_15138, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_15140 = and(_T_15137, _T_15139) @[ifu_bp_ctl.scala 443:22] - node _T_15141 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15142 = eq(_T_15141, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_15143 = or(_T_15142, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15144 = and(_T_15140, _T_15143) @[ifu_bp_ctl.scala 443:87] - node _T_15145 = or(_T_15136, _T_15144) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][14][9] <= _T_15145 @[ifu_bp_ctl.scala 442:27] - node _T_15146 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15147 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15148 = eq(_T_15147, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_15149 = and(_T_15146, _T_15148) @[ifu_bp_ctl.scala 442:45] - node _T_15150 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15151 = eq(_T_15150, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_15152 = or(_T_15151, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15153 = and(_T_15149, _T_15152) @[ifu_bp_ctl.scala 442:110] - node _T_15154 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15155 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15156 = eq(_T_15155, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_15157 = and(_T_15154, _T_15156) @[ifu_bp_ctl.scala 443:22] - node _T_15158 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15159 = eq(_T_15158, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_15160 = or(_T_15159, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15161 = and(_T_15157, _T_15160) @[ifu_bp_ctl.scala 443:87] - node _T_15162 = or(_T_15153, _T_15161) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][14][10] <= _T_15162 @[ifu_bp_ctl.scala 442:27] - node _T_15163 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15164 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15165 = eq(_T_15164, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_15166 = and(_T_15163, _T_15165) @[ifu_bp_ctl.scala 442:45] - node _T_15167 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15168 = eq(_T_15167, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_15169 = or(_T_15168, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15170 = and(_T_15166, _T_15169) @[ifu_bp_ctl.scala 442:110] - node _T_15171 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15172 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15173 = eq(_T_15172, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_15174 = and(_T_15171, _T_15173) @[ifu_bp_ctl.scala 443:22] - node _T_15175 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15176 = eq(_T_15175, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_15177 = or(_T_15176, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15178 = and(_T_15174, _T_15177) @[ifu_bp_ctl.scala 443:87] - node _T_15179 = or(_T_15170, _T_15178) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][14][11] <= _T_15179 @[ifu_bp_ctl.scala 442:27] - node _T_15180 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15181 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15182 = eq(_T_15181, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_15183 = and(_T_15180, _T_15182) @[ifu_bp_ctl.scala 442:45] - node _T_15184 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15185 = eq(_T_15184, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_15186 = or(_T_15185, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15187 = and(_T_15183, _T_15186) @[ifu_bp_ctl.scala 442:110] - node _T_15188 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15189 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15190 = eq(_T_15189, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_15191 = and(_T_15188, _T_15190) @[ifu_bp_ctl.scala 443:22] - node _T_15192 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15193 = eq(_T_15192, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_15194 = or(_T_15193, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15195 = and(_T_15191, _T_15194) @[ifu_bp_ctl.scala 443:87] - node _T_15196 = or(_T_15187, _T_15195) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][14][12] <= _T_15196 @[ifu_bp_ctl.scala 442:27] - node _T_15197 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15198 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15199 = eq(_T_15198, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_15200 = and(_T_15197, _T_15199) @[ifu_bp_ctl.scala 442:45] - node _T_15201 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15202 = eq(_T_15201, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_15203 = or(_T_15202, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15204 = and(_T_15200, _T_15203) @[ifu_bp_ctl.scala 442:110] - node _T_15205 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15206 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15207 = eq(_T_15206, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_15208 = and(_T_15205, _T_15207) @[ifu_bp_ctl.scala 443:22] - node _T_15209 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15210 = eq(_T_15209, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_15211 = or(_T_15210, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15212 = and(_T_15208, _T_15211) @[ifu_bp_ctl.scala 443:87] - node _T_15213 = or(_T_15204, _T_15212) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][14][13] <= _T_15213 @[ifu_bp_ctl.scala 442:27] - node _T_15214 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15215 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15216 = eq(_T_15215, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_15217 = and(_T_15214, _T_15216) @[ifu_bp_ctl.scala 442:45] - node _T_15218 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15219 = eq(_T_15218, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_15220 = or(_T_15219, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15221 = and(_T_15217, _T_15220) @[ifu_bp_ctl.scala 442:110] - node _T_15222 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15223 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15224 = eq(_T_15223, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_15225 = and(_T_15222, _T_15224) @[ifu_bp_ctl.scala 443:22] - node _T_15226 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15227 = eq(_T_15226, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_15228 = or(_T_15227, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15229 = and(_T_15225, _T_15228) @[ifu_bp_ctl.scala 443:87] - node _T_15230 = or(_T_15221, _T_15229) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][14][14] <= _T_15230 @[ifu_bp_ctl.scala 442:27] - node _T_15231 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15232 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15233 = eq(_T_15232, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_15234 = and(_T_15231, _T_15233) @[ifu_bp_ctl.scala 442:45] - node _T_15235 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15236 = eq(_T_15235, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_15237 = or(_T_15236, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15238 = and(_T_15234, _T_15237) @[ifu_bp_ctl.scala 442:110] - node _T_15239 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15240 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15241 = eq(_T_15240, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_15242 = and(_T_15239, _T_15241) @[ifu_bp_ctl.scala 443:22] - node _T_15243 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15244 = eq(_T_15243, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_15245 = or(_T_15244, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15246 = and(_T_15242, _T_15245) @[ifu_bp_ctl.scala 443:87] - node _T_15247 = or(_T_15238, _T_15246) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][14][15] <= _T_15247 @[ifu_bp_ctl.scala 442:27] - node _T_15248 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15249 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15250 = eq(_T_15249, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_15251 = and(_T_15248, _T_15250) @[ifu_bp_ctl.scala 442:45] - node _T_15252 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15253 = eq(_T_15252, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_15254 = or(_T_15253, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15255 = and(_T_15251, _T_15254) @[ifu_bp_ctl.scala 442:110] - node _T_15256 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15257 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15258 = eq(_T_15257, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_15259 = and(_T_15256, _T_15258) @[ifu_bp_ctl.scala 443:22] - node _T_15260 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15261 = eq(_T_15260, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_15262 = or(_T_15261, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15263 = and(_T_15259, _T_15262) @[ifu_bp_ctl.scala 443:87] - node _T_15264 = or(_T_15255, _T_15263) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][15][0] <= _T_15264 @[ifu_bp_ctl.scala 442:27] - node _T_15265 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15266 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15267 = eq(_T_15266, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_15268 = and(_T_15265, _T_15267) @[ifu_bp_ctl.scala 442:45] - node _T_15269 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15270 = eq(_T_15269, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_15271 = or(_T_15270, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15272 = and(_T_15268, _T_15271) @[ifu_bp_ctl.scala 442:110] - node _T_15273 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15274 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15275 = eq(_T_15274, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_15276 = and(_T_15273, _T_15275) @[ifu_bp_ctl.scala 443:22] - node _T_15277 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15278 = eq(_T_15277, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_15279 = or(_T_15278, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15280 = and(_T_15276, _T_15279) @[ifu_bp_ctl.scala 443:87] - node _T_15281 = or(_T_15272, _T_15280) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][15][1] <= _T_15281 @[ifu_bp_ctl.scala 442:27] - node _T_15282 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15283 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15284 = eq(_T_15283, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_15285 = and(_T_15282, _T_15284) @[ifu_bp_ctl.scala 442:45] - node _T_15286 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15287 = eq(_T_15286, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_15288 = or(_T_15287, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15289 = and(_T_15285, _T_15288) @[ifu_bp_ctl.scala 442:110] - node _T_15290 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15291 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15292 = eq(_T_15291, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_15293 = and(_T_15290, _T_15292) @[ifu_bp_ctl.scala 443:22] - node _T_15294 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15295 = eq(_T_15294, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_15296 = or(_T_15295, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15297 = and(_T_15293, _T_15296) @[ifu_bp_ctl.scala 443:87] - node _T_15298 = or(_T_15289, _T_15297) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][15][2] <= _T_15298 @[ifu_bp_ctl.scala 442:27] - node _T_15299 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15300 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15301 = eq(_T_15300, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_15302 = and(_T_15299, _T_15301) @[ifu_bp_ctl.scala 442:45] - node _T_15303 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15304 = eq(_T_15303, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_15305 = or(_T_15304, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15306 = and(_T_15302, _T_15305) @[ifu_bp_ctl.scala 442:110] - node _T_15307 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15308 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15309 = eq(_T_15308, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_15310 = and(_T_15307, _T_15309) @[ifu_bp_ctl.scala 443:22] - node _T_15311 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15312 = eq(_T_15311, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_15313 = or(_T_15312, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15314 = and(_T_15310, _T_15313) @[ifu_bp_ctl.scala 443:87] - node _T_15315 = or(_T_15306, _T_15314) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][15][3] <= _T_15315 @[ifu_bp_ctl.scala 442:27] - node _T_15316 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15317 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15318 = eq(_T_15317, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_15319 = and(_T_15316, _T_15318) @[ifu_bp_ctl.scala 442:45] - node _T_15320 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15321 = eq(_T_15320, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_15322 = or(_T_15321, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15323 = and(_T_15319, _T_15322) @[ifu_bp_ctl.scala 442:110] - node _T_15324 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15325 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15326 = eq(_T_15325, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_15327 = and(_T_15324, _T_15326) @[ifu_bp_ctl.scala 443:22] - node _T_15328 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15329 = eq(_T_15328, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_15330 = or(_T_15329, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15331 = and(_T_15327, _T_15330) @[ifu_bp_ctl.scala 443:87] - node _T_15332 = or(_T_15323, _T_15331) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][15][4] <= _T_15332 @[ifu_bp_ctl.scala 442:27] - node _T_15333 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15334 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15335 = eq(_T_15334, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_15336 = and(_T_15333, _T_15335) @[ifu_bp_ctl.scala 442:45] - node _T_15337 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15338 = eq(_T_15337, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_15339 = or(_T_15338, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15340 = and(_T_15336, _T_15339) @[ifu_bp_ctl.scala 442:110] - node _T_15341 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15342 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15343 = eq(_T_15342, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_15344 = and(_T_15341, _T_15343) @[ifu_bp_ctl.scala 443:22] - node _T_15345 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15346 = eq(_T_15345, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_15347 = or(_T_15346, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15348 = and(_T_15344, _T_15347) @[ifu_bp_ctl.scala 443:87] - node _T_15349 = or(_T_15340, _T_15348) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][15][5] <= _T_15349 @[ifu_bp_ctl.scala 442:27] - node _T_15350 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15351 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15352 = eq(_T_15351, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_15353 = and(_T_15350, _T_15352) @[ifu_bp_ctl.scala 442:45] - node _T_15354 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15355 = eq(_T_15354, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_15356 = or(_T_15355, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15357 = and(_T_15353, _T_15356) @[ifu_bp_ctl.scala 442:110] - node _T_15358 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15359 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15360 = eq(_T_15359, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_15361 = and(_T_15358, _T_15360) @[ifu_bp_ctl.scala 443:22] - node _T_15362 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15363 = eq(_T_15362, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_15364 = or(_T_15363, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15365 = and(_T_15361, _T_15364) @[ifu_bp_ctl.scala 443:87] - node _T_15366 = or(_T_15357, _T_15365) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][15][6] <= _T_15366 @[ifu_bp_ctl.scala 442:27] - node _T_15367 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15368 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15369 = eq(_T_15368, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_15370 = and(_T_15367, _T_15369) @[ifu_bp_ctl.scala 442:45] - node _T_15371 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15372 = eq(_T_15371, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_15373 = or(_T_15372, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15374 = and(_T_15370, _T_15373) @[ifu_bp_ctl.scala 442:110] - node _T_15375 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15376 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15377 = eq(_T_15376, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_15378 = and(_T_15375, _T_15377) @[ifu_bp_ctl.scala 443:22] - node _T_15379 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15380 = eq(_T_15379, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_15381 = or(_T_15380, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15382 = and(_T_15378, _T_15381) @[ifu_bp_ctl.scala 443:87] - node _T_15383 = or(_T_15374, _T_15382) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][15][7] <= _T_15383 @[ifu_bp_ctl.scala 442:27] - node _T_15384 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15385 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15386 = eq(_T_15385, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_15387 = and(_T_15384, _T_15386) @[ifu_bp_ctl.scala 442:45] - node _T_15388 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15389 = eq(_T_15388, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_15390 = or(_T_15389, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15391 = and(_T_15387, _T_15390) @[ifu_bp_ctl.scala 442:110] - node _T_15392 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15393 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15394 = eq(_T_15393, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_15395 = and(_T_15392, _T_15394) @[ifu_bp_ctl.scala 443:22] - node _T_15396 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15397 = eq(_T_15396, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_15398 = or(_T_15397, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15399 = and(_T_15395, _T_15398) @[ifu_bp_ctl.scala 443:87] - node _T_15400 = or(_T_15391, _T_15399) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][15][8] <= _T_15400 @[ifu_bp_ctl.scala 442:27] - node _T_15401 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15402 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15403 = eq(_T_15402, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_15404 = and(_T_15401, _T_15403) @[ifu_bp_ctl.scala 442:45] - node _T_15405 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15406 = eq(_T_15405, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_15407 = or(_T_15406, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15408 = and(_T_15404, _T_15407) @[ifu_bp_ctl.scala 442:110] - node _T_15409 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15410 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15411 = eq(_T_15410, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_15412 = and(_T_15409, _T_15411) @[ifu_bp_ctl.scala 443:22] - node _T_15413 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15414 = eq(_T_15413, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_15415 = or(_T_15414, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15416 = and(_T_15412, _T_15415) @[ifu_bp_ctl.scala 443:87] - node _T_15417 = or(_T_15408, _T_15416) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][15][9] <= _T_15417 @[ifu_bp_ctl.scala 442:27] - node _T_15418 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15419 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15420 = eq(_T_15419, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_15421 = and(_T_15418, _T_15420) @[ifu_bp_ctl.scala 442:45] - node _T_15422 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15423 = eq(_T_15422, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_15424 = or(_T_15423, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15425 = and(_T_15421, _T_15424) @[ifu_bp_ctl.scala 442:110] - node _T_15426 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15427 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15428 = eq(_T_15427, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_15429 = and(_T_15426, _T_15428) @[ifu_bp_ctl.scala 443:22] - node _T_15430 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15431 = eq(_T_15430, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_15432 = or(_T_15431, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15433 = and(_T_15429, _T_15432) @[ifu_bp_ctl.scala 443:87] - node _T_15434 = or(_T_15425, _T_15433) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][15][10] <= _T_15434 @[ifu_bp_ctl.scala 442:27] - node _T_15435 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15436 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15437 = eq(_T_15436, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_15438 = and(_T_15435, _T_15437) @[ifu_bp_ctl.scala 442:45] - node _T_15439 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15440 = eq(_T_15439, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_15441 = or(_T_15440, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15442 = and(_T_15438, _T_15441) @[ifu_bp_ctl.scala 442:110] - node _T_15443 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15444 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15445 = eq(_T_15444, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_15446 = and(_T_15443, _T_15445) @[ifu_bp_ctl.scala 443:22] - node _T_15447 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15448 = eq(_T_15447, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_15449 = or(_T_15448, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15450 = and(_T_15446, _T_15449) @[ifu_bp_ctl.scala 443:87] - node _T_15451 = or(_T_15442, _T_15450) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][15][11] <= _T_15451 @[ifu_bp_ctl.scala 442:27] - node _T_15452 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15453 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15454 = eq(_T_15453, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_15455 = and(_T_15452, _T_15454) @[ifu_bp_ctl.scala 442:45] - node _T_15456 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15457 = eq(_T_15456, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_15458 = or(_T_15457, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15459 = and(_T_15455, _T_15458) @[ifu_bp_ctl.scala 442:110] - node _T_15460 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15461 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15462 = eq(_T_15461, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_15463 = and(_T_15460, _T_15462) @[ifu_bp_ctl.scala 443:22] - node _T_15464 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15465 = eq(_T_15464, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_15466 = or(_T_15465, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15467 = and(_T_15463, _T_15466) @[ifu_bp_ctl.scala 443:87] - node _T_15468 = or(_T_15459, _T_15467) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][15][12] <= _T_15468 @[ifu_bp_ctl.scala 442:27] - node _T_15469 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15470 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15471 = eq(_T_15470, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_15472 = and(_T_15469, _T_15471) @[ifu_bp_ctl.scala 442:45] - node _T_15473 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15474 = eq(_T_15473, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_15475 = or(_T_15474, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15476 = and(_T_15472, _T_15475) @[ifu_bp_ctl.scala 442:110] - node _T_15477 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15478 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15479 = eq(_T_15478, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_15480 = and(_T_15477, _T_15479) @[ifu_bp_ctl.scala 443:22] - node _T_15481 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15482 = eq(_T_15481, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_15483 = or(_T_15482, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15484 = and(_T_15480, _T_15483) @[ifu_bp_ctl.scala 443:87] - node _T_15485 = or(_T_15476, _T_15484) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][15][13] <= _T_15485 @[ifu_bp_ctl.scala 442:27] - node _T_15486 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15487 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15488 = eq(_T_15487, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_15489 = and(_T_15486, _T_15488) @[ifu_bp_ctl.scala 442:45] - node _T_15490 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15491 = eq(_T_15490, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_15492 = or(_T_15491, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15493 = and(_T_15489, _T_15492) @[ifu_bp_ctl.scala 442:110] - node _T_15494 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15495 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15496 = eq(_T_15495, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_15497 = and(_T_15494, _T_15496) @[ifu_bp_ctl.scala 443:22] - node _T_15498 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15499 = eq(_T_15498, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_15500 = or(_T_15499, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15501 = and(_T_15497, _T_15500) @[ifu_bp_ctl.scala 443:87] - node _T_15502 = or(_T_15493, _T_15501) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][15][14] <= _T_15502 @[ifu_bp_ctl.scala 442:27] - node _T_15503 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 442:41] - node _T_15504 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15505 = eq(_T_15504, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_15506 = and(_T_15503, _T_15505) @[ifu_bp_ctl.scala 442:45] - node _T_15507 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15508 = eq(_T_15507, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_15509 = or(_T_15508, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15510 = and(_T_15506, _T_15509) @[ifu_bp_ctl.scala 442:110] - node _T_15511 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 443:18] - node _T_15512 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15513 = eq(_T_15512, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_15514 = and(_T_15511, _T_15513) @[ifu_bp_ctl.scala 443:22] - node _T_15515 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15516 = eq(_T_15515, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_15517 = or(_T_15516, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15518 = and(_T_15514, _T_15517) @[ifu_bp_ctl.scala 443:87] - node _T_15519 = or(_T_15510, _T_15518) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[0][15][15] <= _T_15519 @[ifu_bp_ctl.scala 442:27] - node _T_15520 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15521 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15522 = eq(_T_15521, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_15523 = and(_T_15520, _T_15522) @[ifu_bp_ctl.scala 442:45] - node _T_15524 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15525 = eq(_T_15524, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_15526 = or(_T_15525, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15527 = and(_T_15523, _T_15526) @[ifu_bp_ctl.scala 442:110] - node _T_15528 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15529 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15530 = eq(_T_15529, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_15531 = and(_T_15528, _T_15530) @[ifu_bp_ctl.scala 443:22] - node _T_15532 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15533 = eq(_T_15532, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_15534 = or(_T_15533, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15535 = and(_T_15531, _T_15534) @[ifu_bp_ctl.scala 443:87] - node _T_15536 = or(_T_15527, _T_15535) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][0][0] <= _T_15536 @[ifu_bp_ctl.scala 442:27] - node _T_15537 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15538 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15539 = eq(_T_15538, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_15540 = and(_T_15537, _T_15539) @[ifu_bp_ctl.scala 442:45] - node _T_15541 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15542 = eq(_T_15541, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_15543 = or(_T_15542, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15544 = and(_T_15540, _T_15543) @[ifu_bp_ctl.scala 442:110] - node _T_15545 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15546 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15547 = eq(_T_15546, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_15548 = and(_T_15545, _T_15547) @[ifu_bp_ctl.scala 443:22] - node _T_15549 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15550 = eq(_T_15549, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_15551 = or(_T_15550, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15552 = and(_T_15548, _T_15551) @[ifu_bp_ctl.scala 443:87] - node _T_15553 = or(_T_15544, _T_15552) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][0][1] <= _T_15553 @[ifu_bp_ctl.scala 442:27] - node _T_15554 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15555 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15556 = eq(_T_15555, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_15557 = and(_T_15554, _T_15556) @[ifu_bp_ctl.scala 442:45] - node _T_15558 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15559 = eq(_T_15558, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_15560 = or(_T_15559, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15561 = and(_T_15557, _T_15560) @[ifu_bp_ctl.scala 442:110] - node _T_15562 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15563 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15564 = eq(_T_15563, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_15565 = and(_T_15562, _T_15564) @[ifu_bp_ctl.scala 443:22] - node _T_15566 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15567 = eq(_T_15566, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_15568 = or(_T_15567, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15569 = and(_T_15565, _T_15568) @[ifu_bp_ctl.scala 443:87] - node _T_15570 = or(_T_15561, _T_15569) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][0][2] <= _T_15570 @[ifu_bp_ctl.scala 442:27] - node _T_15571 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15572 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15573 = eq(_T_15572, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_15574 = and(_T_15571, _T_15573) @[ifu_bp_ctl.scala 442:45] - node _T_15575 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15576 = eq(_T_15575, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_15577 = or(_T_15576, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15578 = and(_T_15574, _T_15577) @[ifu_bp_ctl.scala 442:110] - node _T_15579 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15580 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15581 = eq(_T_15580, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_15582 = and(_T_15579, _T_15581) @[ifu_bp_ctl.scala 443:22] - node _T_15583 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15584 = eq(_T_15583, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_15585 = or(_T_15584, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15586 = and(_T_15582, _T_15585) @[ifu_bp_ctl.scala 443:87] - node _T_15587 = or(_T_15578, _T_15586) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][0][3] <= _T_15587 @[ifu_bp_ctl.scala 442:27] - node _T_15588 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15589 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15590 = eq(_T_15589, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_15591 = and(_T_15588, _T_15590) @[ifu_bp_ctl.scala 442:45] - node _T_15592 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15593 = eq(_T_15592, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_15594 = or(_T_15593, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15595 = and(_T_15591, _T_15594) @[ifu_bp_ctl.scala 442:110] - node _T_15596 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15597 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15598 = eq(_T_15597, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_15599 = and(_T_15596, _T_15598) @[ifu_bp_ctl.scala 443:22] - node _T_15600 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15601 = eq(_T_15600, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_15602 = or(_T_15601, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15603 = and(_T_15599, _T_15602) @[ifu_bp_ctl.scala 443:87] - node _T_15604 = or(_T_15595, _T_15603) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][0][4] <= _T_15604 @[ifu_bp_ctl.scala 442:27] - node _T_15605 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15606 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15607 = eq(_T_15606, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_15608 = and(_T_15605, _T_15607) @[ifu_bp_ctl.scala 442:45] - node _T_15609 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15610 = eq(_T_15609, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_15611 = or(_T_15610, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15612 = and(_T_15608, _T_15611) @[ifu_bp_ctl.scala 442:110] - node _T_15613 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15614 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15615 = eq(_T_15614, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_15616 = and(_T_15613, _T_15615) @[ifu_bp_ctl.scala 443:22] - node _T_15617 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15618 = eq(_T_15617, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_15619 = or(_T_15618, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15620 = and(_T_15616, _T_15619) @[ifu_bp_ctl.scala 443:87] - node _T_15621 = or(_T_15612, _T_15620) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][0][5] <= _T_15621 @[ifu_bp_ctl.scala 442:27] - node _T_15622 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15623 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15624 = eq(_T_15623, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_15625 = and(_T_15622, _T_15624) @[ifu_bp_ctl.scala 442:45] - node _T_15626 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15627 = eq(_T_15626, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_15628 = or(_T_15627, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15629 = and(_T_15625, _T_15628) @[ifu_bp_ctl.scala 442:110] - node _T_15630 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15631 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15632 = eq(_T_15631, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_15633 = and(_T_15630, _T_15632) @[ifu_bp_ctl.scala 443:22] - node _T_15634 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15635 = eq(_T_15634, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_15636 = or(_T_15635, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15637 = and(_T_15633, _T_15636) @[ifu_bp_ctl.scala 443:87] - node _T_15638 = or(_T_15629, _T_15637) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][0][6] <= _T_15638 @[ifu_bp_ctl.scala 442:27] - node _T_15639 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15640 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15641 = eq(_T_15640, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_15642 = and(_T_15639, _T_15641) @[ifu_bp_ctl.scala 442:45] - node _T_15643 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15644 = eq(_T_15643, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_15645 = or(_T_15644, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15646 = and(_T_15642, _T_15645) @[ifu_bp_ctl.scala 442:110] - node _T_15647 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15648 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15649 = eq(_T_15648, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_15650 = and(_T_15647, _T_15649) @[ifu_bp_ctl.scala 443:22] - node _T_15651 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15652 = eq(_T_15651, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_15653 = or(_T_15652, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15654 = and(_T_15650, _T_15653) @[ifu_bp_ctl.scala 443:87] - node _T_15655 = or(_T_15646, _T_15654) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][0][7] <= _T_15655 @[ifu_bp_ctl.scala 442:27] - node _T_15656 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15657 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15658 = eq(_T_15657, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_15659 = and(_T_15656, _T_15658) @[ifu_bp_ctl.scala 442:45] - node _T_15660 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15661 = eq(_T_15660, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_15662 = or(_T_15661, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15663 = and(_T_15659, _T_15662) @[ifu_bp_ctl.scala 442:110] - node _T_15664 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15665 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15666 = eq(_T_15665, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_15667 = and(_T_15664, _T_15666) @[ifu_bp_ctl.scala 443:22] - node _T_15668 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15669 = eq(_T_15668, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_15670 = or(_T_15669, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15671 = and(_T_15667, _T_15670) @[ifu_bp_ctl.scala 443:87] - node _T_15672 = or(_T_15663, _T_15671) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][0][8] <= _T_15672 @[ifu_bp_ctl.scala 442:27] - node _T_15673 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15674 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15675 = eq(_T_15674, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_15676 = and(_T_15673, _T_15675) @[ifu_bp_ctl.scala 442:45] - node _T_15677 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15678 = eq(_T_15677, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_15679 = or(_T_15678, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15680 = and(_T_15676, _T_15679) @[ifu_bp_ctl.scala 442:110] - node _T_15681 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15682 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15683 = eq(_T_15682, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_15684 = and(_T_15681, _T_15683) @[ifu_bp_ctl.scala 443:22] - node _T_15685 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15686 = eq(_T_15685, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_15687 = or(_T_15686, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15688 = and(_T_15684, _T_15687) @[ifu_bp_ctl.scala 443:87] - node _T_15689 = or(_T_15680, _T_15688) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][0][9] <= _T_15689 @[ifu_bp_ctl.scala 442:27] - node _T_15690 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15691 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15692 = eq(_T_15691, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_15693 = and(_T_15690, _T_15692) @[ifu_bp_ctl.scala 442:45] - node _T_15694 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15695 = eq(_T_15694, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_15696 = or(_T_15695, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15697 = and(_T_15693, _T_15696) @[ifu_bp_ctl.scala 442:110] - node _T_15698 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15699 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15700 = eq(_T_15699, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_15701 = and(_T_15698, _T_15700) @[ifu_bp_ctl.scala 443:22] - node _T_15702 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15703 = eq(_T_15702, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_15704 = or(_T_15703, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15705 = and(_T_15701, _T_15704) @[ifu_bp_ctl.scala 443:87] - node _T_15706 = or(_T_15697, _T_15705) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][0][10] <= _T_15706 @[ifu_bp_ctl.scala 442:27] - node _T_15707 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15708 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15709 = eq(_T_15708, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_15710 = and(_T_15707, _T_15709) @[ifu_bp_ctl.scala 442:45] - node _T_15711 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15712 = eq(_T_15711, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_15713 = or(_T_15712, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15714 = and(_T_15710, _T_15713) @[ifu_bp_ctl.scala 442:110] - node _T_15715 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15716 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15717 = eq(_T_15716, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_15718 = and(_T_15715, _T_15717) @[ifu_bp_ctl.scala 443:22] - node _T_15719 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15720 = eq(_T_15719, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_15721 = or(_T_15720, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15722 = and(_T_15718, _T_15721) @[ifu_bp_ctl.scala 443:87] - node _T_15723 = or(_T_15714, _T_15722) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][0][11] <= _T_15723 @[ifu_bp_ctl.scala 442:27] - node _T_15724 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15725 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15726 = eq(_T_15725, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_15727 = and(_T_15724, _T_15726) @[ifu_bp_ctl.scala 442:45] - node _T_15728 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15729 = eq(_T_15728, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_15730 = or(_T_15729, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15731 = and(_T_15727, _T_15730) @[ifu_bp_ctl.scala 442:110] - node _T_15732 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15733 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15734 = eq(_T_15733, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_15735 = and(_T_15732, _T_15734) @[ifu_bp_ctl.scala 443:22] - node _T_15736 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15737 = eq(_T_15736, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_15738 = or(_T_15737, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15739 = and(_T_15735, _T_15738) @[ifu_bp_ctl.scala 443:87] - node _T_15740 = or(_T_15731, _T_15739) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][0][12] <= _T_15740 @[ifu_bp_ctl.scala 442:27] - node _T_15741 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15742 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15743 = eq(_T_15742, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_15744 = and(_T_15741, _T_15743) @[ifu_bp_ctl.scala 442:45] - node _T_15745 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15746 = eq(_T_15745, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_15747 = or(_T_15746, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15748 = and(_T_15744, _T_15747) @[ifu_bp_ctl.scala 442:110] - node _T_15749 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15750 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15751 = eq(_T_15750, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_15752 = and(_T_15749, _T_15751) @[ifu_bp_ctl.scala 443:22] - node _T_15753 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15754 = eq(_T_15753, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_15755 = or(_T_15754, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15756 = and(_T_15752, _T_15755) @[ifu_bp_ctl.scala 443:87] - node _T_15757 = or(_T_15748, _T_15756) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][0][13] <= _T_15757 @[ifu_bp_ctl.scala 442:27] - node _T_15758 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15759 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15760 = eq(_T_15759, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_15761 = and(_T_15758, _T_15760) @[ifu_bp_ctl.scala 442:45] - node _T_15762 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15763 = eq(_T_15762, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_15764 = or(_T_15763, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15765 = and(_T_15761, _T_15764) @[ifu_bp_ctl.scala 442:110] - node _T_15766 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15767 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15768 = eq(_T_15767, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_15769 = and(_T_15766, _T_15768) @[ifu_bp_ctl.scala 443:22] - node _T_15770 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15771 = eq(_T_15770, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_15772 = or(_T_15771, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15773 = and(_T_15769, _T_15772) @[ifu_bp_ctl.scala 443:87] - node _T_15774 = or(_T_15765, _T_15773) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][0][14] <= _T_15774 @[ifu_bp_ctl.scala 442:27] - node _T_15775 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15776 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15777 = eq(_T_15776, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_15778 = and(_T_15775, _T_15777) @[ifu_bp_ctl.scala 442:45] - node _T_15779 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15780 = eq(_T_15779, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:186] - node _T_15781 = or(_T_15780, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15782 = and(_T_15778, _T_15781) @[ifu_bp_ctl.scala 442:110] - node _T_15783 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15784 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15785 = eq(_T_15784, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_15786 = and(_T_15783, _T_15785) @[ifu_bp_ctl.scala 443:22] - node _T_15787 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15788 = eq(_T_15787, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:163] - node _T_15789 = or(_T_15788, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15790 = and(_T_15786, _T_15789) @[ifu_bp_ctl.scala 443:87] - node _T_15791 = or(_T_15782, _T_15790) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][0][15] <= _T_15791 @[ifu_bp_ctl.scala 442:27] - node _T_15792 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15793 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15794 = eq(_T_15793, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_15795 = and(_T_15792, _T_15794) @[ifu_bp_ctl.scala 442:45] - node _T_15796 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15797 = eq(_T_15796, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_15798 = or(_T_15797, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15799 = and(_T_15795, _T_15798) @[ifu_bp_ctl.scala 442:110] - node _T_15800 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15801 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15802 = eq(_T_15801, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_15803 = and(_T_15800, _T_15802) @[ifu_bp_ctl.scala 443:22] - node _T_15804 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15805 = eq(_T_15804, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_15806 = or(_T_15805, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15807 = and(_T_15803, _T_15806) @[ifu_bp_ctl.scala 443:87] - node _T_15808 = or(_T_15799, _T_15807) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][1][0] <= _T_15808 @[ifu_bp_ctl.scala 442:27] - node _T_15809 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15810 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15811 = eq(_T_15810, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_15812 = and(_T_15809, _T_15811) @[ifu_bp_ctl.scala 442:45] - node _T_15813 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15814 = eq(_T_15813, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_15815 = or(_T_15814, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15816 = and(_T_15812, _T_15815) @[ifu_bp_ctl.scala 442:110] - node _T_15817 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15818 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15819 = eq(_T_15818, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_15820 = and(_T_15817, _T_15819) @[ifu_bp_ctl.scala 443:22] - node _T_15821 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15822 = eq(_T_15821, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_15823 = or(_T_15822, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15824 = and(_T_15820, _T_15823) @[ifu_bp_ctl.scala 443:87] - node _T_15825 = or(_T_15816, _T_15824) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][1][1] <= _T_15825 @[ifu_bp_ctl.scala 442:27] - node _T_15826 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15827 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15828 = eq(_T_15827, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_15829 = and(_T_15826, _T_15828) @[ifu_bp_ctl.scala 442:45] - node _T_15830 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15831 = eq(_T_15830, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_15832 = or(_T_15831, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15833 = and(_T_15829, _T_15832) @[ifu_bp_ctl.scala 442:110] - node _T_15834 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15835 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15836 = eq(_T_15835, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_15837 = and(_T_15834, _T_15836) @[ifu_bp_ctl.scala 443:22] - node _T_15838 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15839 = eq(_T_15838, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_15840 = or(_T_15839, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15841 = and(_T_15837, _T_15840) @[ifu_bp_ctl.scala 443:87] - node _T_15842 = or(_T_15833, _T_15841) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][1][2] <= _T_15842 @[ifu_bp_ctl.scala 442:27] - node _T_15843 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15844 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15845 = eq(_T_15844, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_15846 = and(_T_15843, _T_15845) @[ifu_bp_ctl.scala 442:45] - node _T_15847 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15848 = eq(_T_15847, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_15849 = or(_T_15848, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15850 = and(_T_15846, _T_15849) @[ifu_bp_ctl.scala 442:110] - node _T_15851 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15852 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15853 = eq(_T_15852, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_15854 = and(_T_15851, _T_15853) @[ifu_bp_ctl.scala 443:22] - node _T_15855 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15856 = eq(_T_15855, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_15857 = or(_T_15856, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15858 = and(_T_15854, _T_15857) @[ifu_bp_ctl.scala 443:87] - node _T_15859 = or(_T_15850, _T_15858) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][1][3] <= _T_15859 @[ifu_bp_ctl.scala 442:27] - node _T_15860 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15861 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15862 = eq(_T_15861, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_15863 = and(_T_15860, _T_15862) @[ifu_bp_ctl.scala 442:45] - node _T_15864 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15865 = eq(_T_15864, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_15866 = or(_T_15865, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15867 = and(_T_15863, _T_15866) @[ifu_bp_ctl.scala 442:110] - node _T_15868 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15869 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15870 = eq(_T_15869, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_15871 = and(_T_15868, _T_15870) @[ifu_bp_ctl.scala 443:22] - node _T_15872 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15873 = eq(_T_15872, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_15874 = or(_T_15873, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15875 = and(_T_15871, _T_15874) @[ifu_bp_ctl.scala 443:87] - node _T_15876 = or(_T_15867, _T_15875) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][1][4] <= _T_15876 @[ifu_bp_ctl.scala 442:27] - node _T_15877 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15878 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15879 = eq(_T_15878, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_15880 = and(_T_15877, _T_15879) @[ifu_bp_ctl.scala 442:45] - node _T_15881 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15882 = eq(_T_15881, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_15883 = or(_T_15882, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15884 = and(_T_15880, _T_15883) @[ifu_bp_ctl.scala 442:110] - node _T_15885 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15886 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15887 = eq(_T_15886, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_15888 = and(_T_15885, _T_15887) @[ifu_bp_ctl.scala 443:22] - node _T_15889 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15890 = eq(_T_15889, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_15891 = or(_T_15890, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15892 = and(_T_15888, _T_15891) @[ifu_bp_ctl.scala 443:87] - node _T_15893 = or(_T_15884, _T_15892) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][1][5] <= _T_15893 @[ifu_bp_ctl.scala 442:27] - node _T_15894 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15895 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15896 = eq(_T_15895, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_15897 = and(_T_15894, _T_15896) @[ifu_bp_ctl.scala 442:45] - node _T_15898 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15899 = eq(_T_15898, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_15900 = or(_T_15899, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15901 = and(_T_15897, _T_15900) @[ifu_bp_ctl.scala 442:110] - node _T_15902 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15903 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15904 = eq(_T_15903, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_15905 = and(_T_15902, _T_15904) @[ifu_bp_ctl.scala 443:22] - node _T_15906 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15907 = eq(_T_15906, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_15908 = or(_T_15907, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15909 = and(_T_15905, _T_15908) @[ifu_bp_ctl.scala 443:87] - node _T_15910 = or(_T_15901, _T_15909) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][1][6] <= _T_15910 @[ifu_bp_ctl.scala 442:27] - node _T_15911 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15912 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15913 = eq(_T_15912, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_15914 = and(_T_15911, _T_15913) @[ifu_bp_ctl.scala 442:45] - node _T_15915 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15916 = eq(_T_15915, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_15917 = or(_T_15916, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15918 = and(_T_15914, _T_15917) @[ifu_bp_ctl.scala 442:110] - node _T_15919 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15920 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15921 = eq(_T_15920, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_15922 = and(_T_15919, _T_15921) @[ifu_bp_ctl.scala 443:22] - node _T_15923 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15924 = eq(_T_15923, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_15925 = or(_T_15924, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15926 = and(_T_15922, _T_15925) @[ifu_bp_ctl.scala 443:87] - node _T_15927 = or(_T_15918, _T_15926) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][1][7] <= _T_15927 @[ifu_bp_ctl.scala 442:27] - node _T_15928 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15929 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15930 = eq(_T_15929, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_15931 = and(_T_15928, _T_15930) @[ifu_bp_ctl.scala 442:45] - node _T_15932 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15933 = eq(_T_15932, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_15934 = or(_T_15933, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15935 = and(_T_15931, _T_15934) @[ifu_bp_ctl.scala 442:110] - node _T_15936 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15937 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15938 = eq(_T_15937, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_15939 = and(_T_15936, _T_15938) @[ifu_bp_ctl.scala 443:22] - node _T_15940 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15941 = eq(_T_15940, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_15942 = or(_T_15941, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15943 = and(_T_15939, _T_15942) @[ifu_bp_ctl.scala 443:87] - node _T_15944 = or(_T_15935, _T_15943) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][1][8] <= _T_15944 @[ifu_bp_ctl.scala 442:27] - node _T_15945 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15946 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15947 = eq(_T_15946, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_15948 = and(_T_15945, _T_15947) @[ifu_bp_ctl.scala 442:45] - node _T_15949 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15950 = eq(_T_15949, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_15951 = or(_T_15950, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15952 = and(_T_15948, _T_15951) @[ifu_bp_ctl.scala 442:110] - node _T_15953 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15954 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15955 = eq(_T_15954, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_15956 = and(_T_15953, _T_15955) @[ifu_bp_ctl.scala 443:22] - node _T_15957 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15958 = eq(_T_15957, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_15959 = or(_T_15958, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15960 = and(_T_15956, _T_15959) @[ifu_bp_ctl.scala 443:87] - node _T_15961 = or(_T_15952, _T_15960) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][1][9] <= _T_15961 @[ifu_bp_ctl.scala 442:27] - node _T_15962 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15963 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15964 = eq(_T_15963, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_15965 = and(_T_15962, _T_15964) @[ifu_bp_ctl.scala 442:45] - node _T_15966 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15967 = eq(_T_15966, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_15968 = or(_T_15967, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15969 = and(_T_15965, _T_15968) @[ifu_bp_ctl.scala 442:110] - node _T_15970 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15971 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15972 = eq(_T_15971, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_15973 = and(_T_15970, _T_15972) @[ifu_bp_ctl.scala 443:22] - node _T_15974 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15975 = eq(_T_15974, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_15976 = or(_T_15975, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15977 = and(_T_15973, _T_15976) @[ifu_bp_ctl.scala 443:87] - node _T_15978 = or(_T_15969, _T_15977) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][1][10] <= _T_15978 @[ifu_bp_ctl.scala 442:27] - node _T_15979 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15980 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15981 = eq(_T_15980, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_15982 = and(_T_15979, _T_15981) @[ifu_bp_ctl.scala 442:45] - node _T_15983 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_15984 = eq(_T_15983, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_15985 = or(_T_15984, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_15986 = and(_T_15982, _T_15985) @[ifu_bp_ctl.scala 442:110] - node _T_15987 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_15988 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_15989 = eq(_T_15988, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_15990 = and(_T_15987, _T_15989) @[ifu_bp_ctl.scala 443:22] - node _T_15991 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_15992 = eq(_T_15991, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_15993 = or(_T_15992, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_15994 = and(_T_15990, _T_15993) @[ifu_bp_ctl.scala 443:87] - node _T_15995 = or(_T_15986, _T_15994) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][1][11] <= _T_15995 @[ifu_bp_ctl.scala 442:27] - node _T_15996 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_15997 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_15998 = eq(_T_15997, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_15999 = and(_T_15996, _T_15998) @[ifu_bp_ctl.scala 442:45] - node _T_16000 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16001 = eq(_T_16000, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_16002 = or(_T_16001, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16003 = and(_T_15999, _T_16002) @[ifu_bp_ctl.scala 442:110] - node _T_16004 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16005 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16006 = eq(_T_16005, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_16007 = and(_T_16004, _T_16006) @[ifu_bp_ctl.scala 443:22] - node _T_16008 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16009 = eq(_T_16008, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_16010 = or(_T_16009, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16011 = and(_T_16007, _T_16010) @[ifu_bp_ctl.scala 443:87] - node _T_16012 = or(_T_16003, _T_16011) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][1][12] <= _T_16012 @[ifu_bp_ctl.scala 442:27] - node _T_16013 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16014 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16015 = eq(_T_16014, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_16016 = and(_T_16013, _T_16015) @[ifu_bp_ctl.scala 442:45] - node _T_16017 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16018 = eq(_T_16017, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_16019 = or(_T_16018, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16020 = and(_T_16016, _T_16019) @[ifu_bp_ctl.scala 442:110] - node _T_16021 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16022 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16023 = eq(_T_16022, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_16024 = and(_T_16021, _T_16023) @[ifu_bp_ctl.scala 443:22] - node _T_16025 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16026 = eq(_T_16025, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_16027 = or(_T_16026, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16028 = and(_T_16024, _T_16027) @[ifu_bp_ctl.scala 443:87] - node _T_16029 = or(_T_16020, _T_16028) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][1][13] <= _T_16029 @[ifu_bp_ctl.scala 442:27] - node _T_16030 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16031 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16032 = eq(_T_16031, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_16033 = and(_T_16030, _T_16032) @[ifu_bp_ctl.scala 442:45] - node _T_16034 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16035 = eq(_T_16034, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_16036 = or(_T_16035, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16037 = and(_T_16033, _T_16036) @[ifu_bp_ctl.scala 442:110] - node _T_16038 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16039 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16040 = eq(_T_16039, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_16041 = and(_T_16038, _T_16040) @[ifu_bp_ctl.scala 443:22] - node _T_16042 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16043 = eq(_T_16042, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_16044 = or(_T_16043, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16045 = and(_T_16041, _T_16044) @[ifu_bp_ctl.scala 443:87] - node _T_16046 = or(_T_16037, _T_16045) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][1][14] <= _T_16046 @[ifu_bp_ctl.scala 442:27] - node _T_16047 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16048 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16049 = eq(_T_16048, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_16050 = and(_T_16047, _T_16049) @[ifu_bp_ctl.scala 442:45] - node _T_16051 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16052 = eq(_T_16051, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:186] - node _T_16053 = or(_T_16052, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16054 = and(_T_16050, _T_16053) @[ifu_bp_ctl.scala 442:110] - node _T_16055 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16056 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16057 = eq(_T_16056, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_16058 = and(_T_16055, _T_16057) @[ifu_bp_ctl.scala 443:22] - node _T_16059 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16060 = eq(_T_16059, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:163] - node _T_16061 = or(_T_16060, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16062 = and(_T_16058, _T_16061) @[ifu_bp_ctl.scala 443:87] - node _T_16063 = or(_T_16054, _T_16062) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][1][15] <= _T_16063 @[ifu_bp_ctl.scala 442:27] - node _T_16064 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16065 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16066 = eq(_T_16065, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_16067 = and(_T_16064, _T_16066) @[ifu_bp_ctl.scala 442:45] - node _T_16068 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16069 = eq(_T_16068, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_16070 = or(_T_16069, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16071 = and(_T_16067, _T_16070) @[ifu_bp_ctl.scala 442:110] - node _T_16072 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16073 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16074 = eq(_T_16073, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_16075 = and(_T_16072, _T_16074) @[ifu_bp_ctl.scala 443:22] - node _T_16076 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16077 = eq(_T_16076, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_16078 = or(_T_16077, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16079 = and(_T_16075, _T_16078) @[ifu_bp_ctl.scala 443:87] - node _T_16080 = or(_T_16071, _T_16079) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][2][0] <= _T_16080 @[ifu_bp_ctl.scala 442:27] - node _T_16081 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16082 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16083 = eq(_T_16082, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_16084 = and(_T_16081, _T_16083) @[ifu_bp_ctl.scala 442:45] - node _T_16085 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16086 = eq(_T_16085, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_16087 = or(_T_16086, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16088 = and(_T_16084, _T_16087) @[ifu_bp_ctl.scala 442:110] - node _T_16089 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16090 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16091 = eq(_T_16090, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_16092 = and(_T_16089, _T_16091) @[ifu_bp_ctl.scala 443:22] - node _T_16093 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16094 = eq(_T_16093, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_16095 = or(_T_16094, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16096 = and(_T_16092, _T_16095) @[ifu_bp_ctl.scala 443:87] - node _T_16097 = or(_T_16088, _T_16096) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][2][1] <= _T_16097 @[ifu_bp_ctl.scala 442:27] - node _T_16098 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16099 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16100 = eq(_T_16099, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_16101 = and(_T_16098, _T_16100) @[ifu_bp_ctl.scala 442:45] - node _T_16102 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16103 = eq(_T_16102, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_16104 = or(_T_16103, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16105 = and(_T_16101, _T_16104) @[ifu_bp_ctl.scala 442:110] - node _T_16106 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16107 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16108 = eq(_T_16107, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_16109 = and(_T_16106, _T_16108) @[ifu_bp_ctl.scala 443:22] - node _T_16110 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16111 = eq(_T_16110, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_16112 = or(_T_16111, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16113 = and(_T_16109, _T_16112) @[ifu_bp_ctl.scala 443:87] - node _T_16114 = or(_T_16105, _T_16113) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][2][2] <= _T_16114 @[ifu_bp_ctl.scala 442:27] - node _T_16115 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16116 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16117 = eq(_T_16116, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_16118 = and(_T_16115, _T_16117) @[ifu_bp_ctl.scala 442:45] - node _T_16119 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16120 = eq(_T_16119, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_16121 = or(_T_16120, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16122 = and(_T_16118, _T_16121) @[ifu_bp_ctl.scala 442:110] - node _T_16123 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16124 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16125 = eq(_T_16124, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_16126 = and(_T_16123, _T_16125) @[ifu_bp_ctl.scala 443:22] - node _T_16127 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16128 = eq(_T_16127, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_16129 = or(_T_16128, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16130 = and(_T_16126, _T_16129) @[ifu_bp_ctl.scala 443:87] - node _T_16131 = or(_T_16122, _T_16130) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][2][3] <= _T_16131 @[ifu_bp_ctl.scala 442:27] - node _T_16132 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16133 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16134 = eq(_T_16133, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_16135 = and(_T_16132, _T_16134) @[ifu_bp_ctl.scala 442:45] - node _T_16136 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16137 = eq(_T_16136, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_16138 = or(_T_16137, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16139 = and(_T_16135, _T_16138) @[ifu_bp_ctl.scala 442:110] - node _T_16140 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16141 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16142 = eq(_T_16141, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_16143 = and(_T_16140, _T_16142) @[ifu_bp_ctl.scala 443:22] - node _T_16144 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16145 = eq(_T_16144, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_16146 = or(_T_16145, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16147 = and(_T_16143, _T_16146) @[ifu_bp_ctl.scala 443:87] - node _T_16148 = or(_T_16139, _T_16147) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][2][4] <= _T_16148 @[ifu_bp_ctl.scala 442:27] - node _T_16149 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16150 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16151 = eq(_T_16150, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_16152 = and(_T_16149, _T_16151) @[ifu_bp_ctl.scala 442:45] - node _T_16153 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16154 = eq(_T_16153, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_16155 = or(_T_16154, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16156 = and(_T_16152, _T_16155) @[ifu_bp_ctl.scala 442:110] - node _T_16157 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16158 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16159 = eq(_T_16158, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_16160 = and(_T_16157, _T_16159) @[ifu_bp_ctl.scala 443:22] - node _T_16161 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16162 = eq(_T_16161, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_16163 = or(_T_16162, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16164 = and(_T_16160, _T_16163) @[ifu_bp_ctl.scala 443:87] - node _T_16165 = or(_T_16156, _T_16164) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][2][5] <= _T_16165 @[ifu_bp_ctl.scala 442:27] - node _T_16166 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16167 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16168 = eq(_T_16167, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_16169 = and(_T_16166, _T_16168) @[ifu_bp_ctl.scala 442:45] - node _T_16170 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16171 = eq(_T_16170, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_16172 = or(_T_16171, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16173 = and(_T_16169, _T_16172) @[ifu_bp_ctl.scala 442:110] - node _T_16174 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16175 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16176 = eq(_T_16175, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_16177 = and(_T_16174, _T_16176) @[ifu_bp_ctl.scala 443:22] - node _T_16178 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16179 = eq(_T_16178, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_16180 = or(_T_16179, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16181 = and(_T_16177, _T_16180) @[ifu_bp_ctl.scala 443:87] - node _T_16182 = or(_T_16173, _T_16181) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][2][6] <= _T_16182 @[ifu_bp_ctl.scala 442:27] - node _T_16183 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16184 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16185 = eq(_T_16184, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_16186 = and(_T_16183, _T_16185) @[ifu_bp_ctl.scala 442:45] - node _T_16187 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16188 = eq(_T_16187, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_16189 = or(_T_16188, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16190 = and(_T_16186, _T_16189) @[ifu_bp_ctl.scala 442:110] - node _T_16191 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16192 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16193 = eq(_T_16192, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_16194 = and(_T_16191, _T_16193) @[ifu_bp_ctl.scala 443:22] - node _T_16195 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16196 = eq(_T_16195, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_16197 = or(_T_16196, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16198 = and(_T_16194, _T_16197) @[ifu_bp_ctl.scala 443:87] - node _T_16199 = or(_T_16190, _T_16198) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][2][7] <= _T_16199 @[ifu_bp_ctl.scala 442:27] - node _T_16200 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16201 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16202 = eq(_T_16201, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_16203 = and(_T_16200, _T_16202) @[ifu_bp_ctl.scala 442:45] - node _T_16204 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16205 = eq(_T_16204, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_16206 = or(_T_16205, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16207 = and(_T_16203, _T_16206) @[ifu_bp_ctl.scala 442:110] - node _T_16208 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16209 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16210 = eq(_T_16209, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_16211 = and(_T_16208, _T_16210) @[ifu_bp_ctl.scala 443:22] - node _T_16212 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16213 = eq(_T_16212, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_16214 = or(_T_16213, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16215 = and(_T_16211, _T_16214) @[ifu_bp_ctl.scala 443:87] - node _T_16216 = or(_T_16207, _T_16215) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][2][8] <= _T_16216 @[ifu_bp_ctl.scala 442:27] - node _T_16217 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16218 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16219 = eq(_T_16218, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_16220 = and(_T_16217, _T_16219) @[ifu_bp_ctl.scala 442:45] - node _T_16221 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16222 = eq(_T_16221, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_16223 = or(_T_16222, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16224 = and(_T_16220, _T_16223) @[ifu_bp_ctl.scala 442:110] - node _T_16225 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16226 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16227 = eq(_T_16226, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_16228 = and(_T_16225, _T_16227) @[ifu_bp_ctl.scala 443:22] - node _T_16229 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16230 = eq(_T_16229, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_16231 = or(_T_16230, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16232 = and(_T_16228, _T_16231) @[ifu_bp_ctl.scala 443:87] - node _T_16233 = or(_T_16224, _T_16232) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][2][9] <= _T_16233 @[ifu_bp_ctl.scala 442:27] - node _T_16234 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16235 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16236 = eq(_T_16235, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_16237 = and(_T_16234, _T_16236) @[ifu_bp_ctl.scala 442:45] - node _T_16238 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16239 = eq(_T_16238, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_16240 = or(_T_16239, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16241 = and(_T_16237, _T_16240) @[ifu_bp_ctl.scala 442:110] - node _T_16242 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16243 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16244 = eq(_T_16243, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_16245 = and(_T_16242, _T_16244) @[ifu_bp_ctl.scala 443:22] - node _T_16246 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16247 = eq(_T_16246, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_16248 = or(_T_16247, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16249 = and(_T_16245, _T_16248) @[ifu_bp_ctl.scala 443:87] - node _T_16250 = or(_T_16241, _T_16249) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][2][10] <= _T_16250 @[ifu_bp_ctl.scala 442:27] - node _T_16251 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16252 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16253 = eq(_T_16252, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_16254 = and(_T_16251, _T_16253) @[ifu_bp_ctl.scala 442:45] - node _T_16255 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16256 = eq(_T_16255, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_16257 = or(_T_16256, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16258 = and(_T_16254, _T_16257) @[ifu_bp_ctl.scala 442:110] - node _T_16259 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16260 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16261 = eq(_T_16260, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_16262 = and(_T_16259, _T_16261) @[ifu_bp_ctl.scala 443:22] - node _T_16263 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16264 = eq(_T_16263, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_16265 = or(_T_16264, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16266 = and(_T_16262, _T_16265) @[ifu_bp_ctl.scala 443:87] - node _T_16267 = or(_T_16258, _T_16266) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][2][11] <= _T_16267 @[ifu_bp_ctl.scala 442:27] - node _T_16268 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16269 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16270 = eq(_T_16269, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_16271 = and(_T_16268, _T_16270) @[ifu_bp_ctl.scala 442:45] - node _T_16272 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16273 = eq(_T_16272, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_16274 = or(_T_16273, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16275 = and(_T_16271, _T_16274) @[ifu_bp_ctl.scala 442:110] - node _T_16276 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16277 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16278 = eq(_T_16277, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_16279 = and(_T_16276, _T_16278) @[ifu_bp_ctl.scala 443:22] - node _T_16280 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16281 = eq(_T_16280, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_16282 = or(_T_16281, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16283 = and(_T_16279, _T_16282) @[ifu_bp_ctl.scala 443:87] - node _T_16284 = or(_T_16275, _T_16283) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][2][12] <= _T_16284 @[ifu_bp_ctl.scala 442:27] - node _T_16285 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16286 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16287 = eq(_T_16286, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_16288 = and(_T_16285, _T_16287) @[ifu_bp_ctl.scala 442:45] - node _T_16289 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16290 = eq(_T_16289, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_16291 = or(_T_16290, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16292 = and(_T_16288, _T_16291) @[ifu_bp_ctl.scala 442:110] - node _T_16293 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16294 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16295 = eq(_T_16294, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_16296 = and(_T_16293, _T_16295) @[ifu_bp_ctl.scala 443:22] - node _T_16297 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16298 = eq(_T_16297, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_16299 = or(_T_16298, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16300 = and(_T_16296, _T_16299) @[ifu_bp_ctl.scala 443:87] - node _T_16301 = or(_T_16292, _T_16300) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][2][13] <= _T_16301 @[ifu_bp_ctl.scala 442:27] - node _T_16302 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16303 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16304 = eq(_T_16303, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_16305 = and(_T_16302, _T_16304) @[ifu_bp_ctl.scala 442:45] - node _T_16306 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16307 = eq(_T_16306, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_16308 = or(_T_16307, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16309 = and(_T_16305, _T_16308) @[ifu_bp_ctl.scala 442:110] - node _T_16310 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16311 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16312 = eq(_T_16311, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_16313 = and(_T_16310, _T_16312) @[ifu_bp_ctl.scala 443:22] - node _T_16314 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16315 = eq(_T_16314, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_16316 = or(_T_16315, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16317 = and(_T_16313, _T_16316) @[ifu_bp_ctl.scala 443:87] - node _T_16318 = or(_T_16309, _T_16317) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][2][14] <= _T_16318 @[ifu_bp_ctl.scala 442:27] - node _T_16319 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16320 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16321 = eq(_T_16320, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_16322 = and(_T_16319, _T_16321) @[ifu_bp_ctl.scala 442:45] - node _T_16323 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16324 = eq(_T_16323, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:186] - node _T_16325 = or(_T_16324, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16326 = and(_T_16322, _T_16325) @[ifu_bp_ctl.scala 442:110] - node _T_16327 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16328 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16329 = eq(_T_16328, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_16330 = and(_T_16327, _T_16329) @[ifu_bp_ctl.scala 443:22] - node _T_16331 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16332 = eq(_T_16331, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:163] - node _T_16333 = or(_T_16332, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16334 = and(_T_16330, _T_16333) @[ifu_bp_ctl.scala 443:87] - node _T_16335 = or(_T_16326, _T_16334) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][2][15] <= _T_16335 @[ifu_bp_ctl.scala 442:27] - node _T_16336 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16337 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16338 = eq(_T_16337, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_16339 = and(_T_16336, _T_16338) @[ifu_bp_ctl.scala 442:45] - node _T_16340 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16341 = eq(_T_16340, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_16342 = or(_T_16341, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16343 = and(_T_16339, _T_16342) @[ifu_bp_ctl.scala 442:110] - node _T_16344 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16345 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16346 = eq(_T_16345, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_16347 = and(_T_16344, _T_16346) @[ifu_bp_ctl.scala 443:22] - node _T_16348 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16349 = eq(_T_16348, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_16350 = or(_T_16349, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16351 = and(_T_16347, _T_16350) @[ifu_bp_ctl.scala 443:87] - node _T_16352 = or(_T_16343, _T_16351) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][3][0] <= _T_16352 @[ifu_bp_ctl.scala 442:27] - node _T_16353 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16354 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16355 = eq(_T_16354, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_16356 = and(_T_16353, _T_16355) @[ifu_bp_ctl.scala 442:45] - node _T_16357 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16358 = eq(_T_16357, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_16359 = or(_T_16358, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16360 = and(_T_16356, _T_16359) @[ifu_bp_ctl.scala 442:110] - node _T_16361 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16362 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16363 = eq(_T_16362, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_16364 = and(_T_16361, _T_16363) @[ifu_bp_ctl.scala 443:22] - node _T_16365 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16366 = eq(_T_16365, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_16367 = or(_T_16366, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16368 = and(_T_16364, _T_16367) @[ifu_bp_ctl.scala 443:87] - node _T_16369 = or(_T_16360, _T_16368) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][3][1] <= _T_16369 @[ifu_bp_ctl.scala 442:27] - node _T_16370 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16371 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16372 = eq(_T_16371, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_16373 = and(_T_16370, _T_16372) @[ifu_bp_ctl.scala 442:45] - node _T_16374 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16375 = eq(_T_16374, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_16376 = or(_T_16375, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16377 = and(_T_16373, _T_16376) @[ifu_bp_ctl.scala 442:110] - node _T_16378 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16379 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16380 = eq(_T_16379, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_16381 = and(_T_16378, _T_16380) @[ifu_bp_ctl.scala 443:22] - node _T_16382 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16383 = eq(_T_16382, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_16384 = or(_T_16383, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16385 = and(_T_16381, _T_16384) @[ifu_bp_ctl.scala 443:87] - node _T_16386 = or(_T_16377, _T_16385) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][3][2] <= _T_16386 @[ifu_bp_ctl.scala 442:27] - node _T_16387 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16388 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16389 = eq(_T_16388, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_16390 = and(_T_16387, _T_16389) @[ifu_bp_ctl.scala 442:45] - node _T_16391 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16392 = eq(_T_16391, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_16393 = or(_T_16392, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16394 = and(_T_16390, _T_16393) @[ifu_bp_ctl.scala 442:110] - node _T_16395 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16396 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16397 = eq(_T_16396, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_16398 = and(_T_16395, _T_16397) @[ifu_bp_ctl.scala 443:22] - node _T_16399 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16400 = eq(_T_16399, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_16401 = or(_T_16400, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16402 = and(_T_16398, _T_16401) @[ifu_bp_ctl.scala 443:87] - node _T_16403 = or(_T_16394, _T_16402) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][3][3] <= _T_16403 @[ifu_bp_ctl.scala 442:27] - node _T_16404 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16405 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16406 = eq(_T_16405, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_16407 = and(_T_16404, _T_16406) @[ifu_bp_ctl.scala 442:45] - node _T_16408 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16409 = eq(_T_16408, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_16410 = or(_T_16409, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16411 = and(_T_16407, _T_16410) @[ifu_bp_ctl.scala 442:110] - node _T_16412 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16413 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16414 = eq(_T_16413, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_16415 = and(_T_16412, _T_16414) @[ifu_bp_ctl.scala 443:22] - node _T_16416 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16417 = eq(_T_16416, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_16418 = or(_T_16417, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16419 = and(_T_16415, _T_16418) @[ifu_bp_ctl.scala 443:87] - node _T_16420 = or(_T_16411, _T_16419) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][3][4] <= _T_16420 @[ifu_bp_ctl.scala 442:27] - node _T_16421 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16422 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16423 = eq(_T_16422, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_16424 = and(_T_16421, _T_16423) @[ifu_bp_ctl.scala 442:45] - node _T_16425 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16426 = eq(_T_16425, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_16427 = or(_T_16426, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16428 = and(_T_16424, _T_16427) @[ifu_bp_ctl.scala 442:110] - node _T_16429 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16430 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16431 = eq(_T_16430, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_16432 = and(_T_16429, _T_16431) @[ifu_bp_ctl.scala 443:22] - node _T_16433 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16434 = eq(_T_16433, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_16435 = or(_T_16434, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16436 = and(_T_16432, _T_16435) @[ifu_bp_ctl.scala 443:87] - node _T_16437 = or(_T_16428, _T_16436) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][3][5] <= _T_16437 @[ifu_bp_ctl.scala 442:27] - node _T_16438 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16439 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16440 = eq(_T_16439, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_16441 = and(_T_16438, _T_16440) @[ifu_bp_ctl.scala 442:45] - node _T_16442 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16443 = eq(_T_16442, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_16444 = or(_T_16443, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16445 = and(_T_16441, _T_16444) @[ifu_bp_ctl.scala 442:110] - node _T_16446 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16447 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16448 = eq(_T_16447, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_16449 = and(_T_16446, _T_16448) @[ifu_bp_ctl.scala 443:22] - node _T_16450 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16451 = eq(_T_16450, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_16452 = or(_T_16451, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16453 = and(_T_16449, _T_16452) @[ifu_bp_ctl.scala 443:87] - node _T_16454 = or(_T_16445, _T_16453) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][3][6] <= _T_16454 @[ifu_bp_ctl.scala 442:27] - node _T_16455 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16456 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16457 = eq(_T_16456, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_16458 = and(_T_16455, _T_16457) @[ifu_bp_ctl.scala 442:45] - node _T_16459 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16460 = eq(_T_16459, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_16461 = or(_T_16460, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16462 = and(_T_16458, _T_16461) @[ifu_bp_ctl.scala 442:110] - node _T_16463 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16464 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16465 = eq(_T_16464, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_16466 = and(_T_16463, _T_16465) @[ifu_bp_ctl.scala 443:22] - node _T_16467 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16468 = eq(_T_16467, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_16469 = or(_T_16468, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16470 = and(_T_16466, _T_16469) @[ifu_bp_ctl.scala 443:87] - node _T_16471 = or(_T_16462, _T_16470) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][3][7] <= _T_16471 @[ifu_bp_ctl.scala 442:27] - node _T_16472 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16473 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16474 = eq(_T_16473, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_16475 = and(_T_16472, _T_16474) @[ifu_bp_ctl.scala 442:45] - node _T_16476 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16477 = eq(_T_16476, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_16478 = or(_T_16477, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16479 = and(_T_16475, _T_16478) @[ifu_bp_ctl.scala 442:110] - node _T_16480 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16481 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16482 = eq(_T_16481, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_16483 = and(_T_16480, _T_16482) @[ifu_bp_ctl.scala 443:22] - node _T_16484 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16485 = eq(_T_16484, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_16486 = or(_T_16485, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16487 = and(_T_16483, _T_16486) @[ifu_bp_ctl.scala 443:87] - node _T_16488 = or(_T_16479, _T_16487) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][3][8] <= _T_16488 @[ifu_bp_ctl.scala 442:27] - node _T_16489 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16490 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16491 = eq(_T_16490, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_16492 = and(_T_16489, _T_16491) @[ifu_bp_ctl.scala 442:45] - node _T_16493 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16494 = eq(_T_16493, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_16495 = or(_T_16494, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16496 = and(_T_16492, _T_16495) @[ifu_bp_ctl.scala 442:110] - node _T_16497 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16498 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16499 = eq(_T_16498, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_16500 = and(_T_16497, _T_16499) @[ifu_bp_ctl.scala 443:22] - node _T_16501 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16502 = eq(_T_16501, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_16503 = or(_T_16502, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16504 = and(_T_16500, _T_16503) @[ifu_bp_ctl.scala 443:87] - node _T_16505 = or(_T_16496, _T_16504) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][3][9] <= _T_16505 @[ifu_bp_ctl.scala 442:27] - node _T_16506 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16507 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16508 = eq(_T_16507, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_16509 = and(_T_16506, _T_16508) @[ifu_bp_ctl.scala 442:45] - node _T_16510 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16511 = eq(_T_16510, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_16512 = or(_T_16511, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16513 = and(_T_16509, _T_16512) @[ifu_bp_ctl.scala 442:110] - node _T_16514 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16515 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16516 = eq(_T_16515, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_16517 = and(_T_16514, _T_16516) @[ifu_bp_ctl.scala 443:22] - node _T_16518 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16519 = eq(_T_16518, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_16520 = or(_T_16519, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16521 = and(_T_16517, _T_16520) @[ifu_bp_ctl.scala 443:87] - node _T_16522 = or(_T_16513, _T_16521) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][3][10] <= _T_16522 @[ifu_bp_ctl.scala 442:27] - node _T_16523 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16524 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16525 = eq(_T_16524, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_16526 = and(_T_16523, _T_16525) @[ifu_bp_ctl.scala 442:45] - node _T_16527 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16528 = eq(_T_16527, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_16529 = or(_T_16528, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16530 = and(_T_16526, _T_16529) @[ifu_bp_ctl.scala 442:110] - node _T_16531 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16532 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16533 = eq(_T_16532, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_16534 = and(_T_16531, _T_16533) @[ifu_bp_ctl.scala 443:22] - node _T_16535 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16536 = eq(_T_16535, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_16537 = or(_T_16536, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16538 = and(_T_16534, _T_16537) @[ifu_bp_ctl.scala 443:87] - node _T_16539 = or(_T_16530, _T_16538) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][3][11] <= _T_16539 @[ifu_bp_ctl.scala 442:27] - node _T_16540 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16541 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16542 = eq(_T_16541, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_16543 = and(_T_16540, _T_16542) @[ifu_bp_ctl.scala 442:45] - node _T_16544 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16545 = eq(_T_16544, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_16546 = or(_T_16545, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16547 = and(_T_16543, _T_16546) @[ifu_bp_ctl.scala 442:110] - node _T_16548 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16549 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16550 = eq(_T_16549, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_16551 = and(_T_16548, _T_16550) @[ifu_bp_ctl.scala 443:22] - node _T_16552 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16553 = eq(_T_16552, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_16554 = or(_T_16553, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16555 = and(_T_16551, _T_16554) @[ifu_bp_ctl.scala 443:87] - node _T_16556 = or(_T_16547, _T_16555) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][3][12] <= _T_16556 @[ifu_bp_ctl.scala 442:27] - node _T_16557 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16558 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16559 = eq(_T_16558, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_16560 = and(_T_16557, _T_16559) @[ifu_bp_ctl.scala 442:45] - node _T_16561 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16562 = eq(_T_16561, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_16563 = or(_T_16562, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16564 = and(_T_16560, _T_16563) @[ifu_bp_ctl.scala 442:110] - node _T_16565 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16566 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16567 = eq(_T_16566, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_16568 = and(_T_16565, _T_16567) @[ifu_bp_ctl.scala 443:22] - node _T_16569 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16570 = eq(_T_16569, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_16571 = or(_T_16570, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16572 = and(_T_16568, _T_16571) @[ifu_bp_ctl.scala 443:87] - node _T_16573 = or(_T_16564, _T_16572) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][3][13] <= _T_16573 @[ifu_bp_ctl.scala 442:27] - node _T_16574 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16575 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16576 = eq(_T_16575, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_16577 = and(_T_16574, _T_16576) @[ifu_bp_ctl.scala 442:45] - node _T_16578 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16579 = eq(_T_16578, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_16580 = or(_T_16579, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16581 = and(_T_16577, _T_16580) @[ifu_bp_ctl.scala 442:110] - node _T_16582 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16583 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16584 = eq(_T_16583, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_16585 = and(_T_16582, _T_16584) @[ifu_bp_ctl.scala 443:22] - node _T_16586 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16587 = eq(_T_16586, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_16588 = or(_T_16587, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16589 = and(_T_16585, _T_16588) @[ifu_bp_ctl.scala 443:87] - node _T_16590 = or(_T_16581, _T_16589) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][3][14] <= _T_16590 @[ifu_bp_ctl.scala 442:27] - node _T_16591 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16592 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16593 = eq(_T_16592, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_16594 = and(_T_16591, _T_16593) @[ifu_bp_ctl.scala 442:45] - node _T_16595 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16596 = eq(_T_16595, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:186] - node _T_16597 = or(_T_16596, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16598 = and(_T_16594, _T_16597) @[ifu_bp_ctl.scala 442:110] - node _T_16599 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16600 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16601 = eq(_T_16600, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_16602 = and(_T_16599, _T_16601) @[ifu_bp_ctl.scala 443:22] - node _T_16603 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16604 = eq(_T_16603, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:163] - node _T_16605 = or(_T_16604, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16606 = and(_T_16602, _T_16605) @[ifu_bp_ctl.scala 443:87] - node _T_16607 = or(_T_16598, _T_16606) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][3][15] <= _T_16607 @[ifu_bp_ctl.scala 442:27] - node _T_16608 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16609 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16610 = eq(_T_16609, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_16611 = and(_T_16608, _T_16610) @[ifu_bp_ctl.scala 442:45] - node _T_16612 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16613 = eq(_T_16612, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_16614 = or(_T_16613, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16615 = and(_T_16611, _T_16614) @[ifu_bp_ctl.scala 442:110] - node _T_16616 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16617 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16618 = eq(_T_16617, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_16619 = and(_T_16616, _T_16618) @[ifu_bp_ctl.scala 443:22] - node _T_16620 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16621 = eq(_T_16620, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_16622 = or(_T_16621, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16623 = and(_T_16619, _T_16622) @[ifu_bp_ctl.scala 443:87] - node _T_16624 = or(_T_16615, _T_16623) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][4][0] <= _T_16624 @[ifu_bp_ctl.scala 442:27] - node _T_16625 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16626 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16627 = eq(_T_16626, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_16628 = and(_T_16625, _T_16627) @[ifu_bp_ctl.scala 442:45] - node _T_16629 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16630 = eq(_T_16629, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_16631 = or(_T_16630, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16632 = and(_T_16628, _T_16631) @[ifu_bp_ctl.scala 442:110] - node _T_16633 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16634 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16635 = eq(_T_16634, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_16636 = and(_T_16633, _T_16635) @[ifu_bp_ctl.scala 443:22] - node _T_16637 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16638 = eq(_T_16637, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_16639 = or(_T_16638, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16640 = and(_T_16636, _T_16639) @[ifu_bp_ctl.scala 443:87] - node _T_16641 = or(_T_16632, _T_16640) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][4][1] <= _T_16641 @[ifu_bp_ctl.scala 442:27] - node _T_16642 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16643 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16644 = eq(_T_16643, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_16645 = and(_T_16642, _T_16644) @[ifu_bp_ctl.scala 442:45] - node _T_16646 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16647 = eq(_T_16646, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_16648 = or(_T_16647, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16649 = and(_T_16645, _T_16648) @[ifu_bp_ctl.scala 442:110] - node _T_16650 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16651 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16652 = eq(_T_16651, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_16653 = and(_T_16650, _T_16652) @[ifu_bp_ctl.scala 443:22] - node _T_16654 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16655 = eq(_T_16654, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_16656 = or(_T_16655, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16657 = and(_T_16653, _T_16656) @[ifu_bp_ctl.scala 443:87] - node _T_16658 = or(_T_16649, _T_16657) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][4][2] <= _T_16658 @[ifu_bp_ctl.scala 442:27] - node _T_16659 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16660 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16661 = eq(_T_16660, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_16662 = and(_T_16659, _T_16661) @[ifu_bp_ctl.scala 442:45] - node _T_16663 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16664 = eq(_T_16663, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_16665 = or(_T_16664, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16666 = and(_T_16662, _T_16665) @[ifu_bp_ctl.scala 442:110] - node _T_16667 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16668 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16669 = eq(_T_16668, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_16670 = and(_T_16667, _T_16669) @[ifu_bp_ctl.scala 443:22] - node _T_16671 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16672 = eq(_T_16671, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_16673 = or(_T_16672, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16674 = and(_T_16670, _T_16673) @[ifu_bp_ctl.scala 443:87] - node _T_16675 = or(_T_16666, _T_16674) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][4][3] <= _T_16675 @[ifu_bp_ctl.scala 442:27] - node _T_16676 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16677 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16678 = eq(_T_16677, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_16679 = and(_T_16676, _T_16678) @[ifu_bp_ctl.scala 442:45] - node _T_16680 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16681 = eq(_T_16680, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_16682 = or(_T_16681, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16683 = and(_T_16679, _T_16682) @[ifu_bp_ctl.scala 442:110] - node _T_16684 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16685 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16686 = eq(_T_16685, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_16687 = and(_T_16684, _T_16686) @[ifu_bp_ctl.scala 443:22] - node _T_16688 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16689 = eq(_T_16688, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_16690 = or(_T_16689, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16691 = and(_T_16687, _T_16690) @[ifu_bp_ctl.scala 443:87] - node _T_16692 = or(_T_16683, _T_16691) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][4][4] <= _T_16692 @[ifu_bp_ctl.scala 442:27] - node _T_16693 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16694 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16695 = eq(_T_16694, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_16696 = and(_T_16693, _T_16695) @[ifu_bp_ctl.scala 442:45] - node _T_16697 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16698 = eq(_T_16697, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_16699 = or(_T_16698, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16700 = and(_T_16696, _T_16699) @[ifu_bp_ctl.scala 442:110] - node _T_16701 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16702 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16703 = eq(_T_16702, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_16704 = and(_T_16701, _T_16703) @[ifu_bp_ctl.scala 443:22] - node _T_16705 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16706 = eq(_T_16705, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_16707 = or(_T_16706, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16708 = and(_T_16704, _T_16707) @[ifu_bp_ctl.scala 443:87] - node _T_16709 = or(_T_16700, _T_16708) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][4][5] <= _T_16709 @[ifu_bp_ctl.scala 442:27] - node _T_16710 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16711 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16712 = eq(_T_16711, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_16713 = and(_T_16710, _T_16712) @[ifu_bp_ctl.scala 442:45] - node _T_16714 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16715 = eq(_T_16714, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_16716 = or(_T_16715, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16717 = and(_T_16713, _T_16716) @[ifu_bp_ctl.scala 442:110] - node _T_16718 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16719 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16720 = eq(_T_16719, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_16721 = and(_T_16718, _T_16720) @[ifu_bp_ctl.scala 443:22] - node _T_16722 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16723 = eq(_T_16722, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_16724 = or(_T_16723, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16725 = and(_T_16721, _T_16724) @[ifu_bp_ctl.scala 443:87] - node _T_16726 = or(_T_16717, _T_16725) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][4][6] <= _T_16726 @[ifu_bp_ctl.scala 442:27] - node _T_16727 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16728 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16729 = eq(_T_16728, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_16730 = and(_T_16727, _T_16729) @[ifu_bp_ctl.scala 442:45] - node _T_16731 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16732 = eq(_T_16731, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_16733 = or(_T_16732, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16734 = and(_T_16730, _T_16733) @[ifu_bp_ctl.scala 442:110] - node _T_16735 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16736 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16737 = eq(_T_16736, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_16738 = and(_T_16735, _T_16737) @[ifu_bp_ctl.scala 443:22] - node _T_16739 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16740 = eq(_T_16739, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_16741 = or(_T_16740, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16742 = and(_T_16738, _T_16741) @[ifu_bp_ctl.scala 443:87] - node _T_16743 = or(_T_16734, _T_16742) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][4][7] <= _T_16743 @[ifu_bp_ctl.scala 442:27] - node _T_16744 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16745 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16746 = eq(_T_16745, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_16747 = and(_T_16744, _T_16746) @[ifu_bp_ctl.scala 442:45] - node _T_16748 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16749 = eq(_T_16748, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_16750 = or(_T_16749, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16751 = and(_T_16747, _T_16750) @[ifu_bp_ctl.scala 442:110] - node _T_16752 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16753 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16754 = eq(_T_16753, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_16755 = and(_T_16752, _T_16754) @[ifu_bp_ctl.scala 443:22] - node _T_16756 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16757 = eq(_T_16756, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_16758 = or(_T_16757, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16759 = and(_T_16755, _T_16758) @[ifu_bp_ctl.scala 443:87] - node _T_16760 = or(_T_16751, _T_16759) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][4][8] <= _T_16760 @[ifu_bp_ctl.scala 442:27] - node _T_16761 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16762 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16763 = eq(_T_16762, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_16764 = and(_T_16761, _T_16763) @[ifu_bp_ctl.scala 442:45] - node _T_16765 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16766 = eq(_T_16765, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_16767 = or(_T_16766, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16768 = and(_T_16764, _T_16767) @[ifu_bp_ctl.scala 442:110] - node _T_16769 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16770 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16771 = eq(_T_16770, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_16772 = and(_T_16769, _T_16771) @[ifu_bp_ctl.scala 443:22] - node _T_16773 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16774 = eq(_T_16773, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_16775 = or(_T_16774, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16776 = and(_T_16772, _T_16775) @[ifu_bp_ctl.scala 443:87] - node _T_16777 = or(_T_16768, _T_16776) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][4][9] <= _T_16777 @[ifu_bp_ctl.scala 442:27] - node _T_16778 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16779 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16780 = eq(_T_16779, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_16781 = and(_T_16778, _T_16780) @[ifu_bp_ctl.scala 442:45] - node _T_16782 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16783 = eq(_T_16782, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_16784 = or(_T_16783, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16785 = and(_T_16781, _T_16784) @[ifu_bp_ctl.scala 442:110] - node _T_16786 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16787 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16788 = eq(_T_16787, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_16789 = and(_T_16786, _T_16788) @[ifu_bp_ctl.scala 443:22] - node _T_16790 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16791 = eq(_T_16790, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_16792 = or(_T_16791, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16793 = and(_T_16789, _T_16792) @[ifu_bp_ctl.scala 443:87] - node _T_16794 = or(_T_16785, _T_16793) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][4][10] <= _T_16794 @[ifu_bp_ctl.scala 442:27] - node _T_16795 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16796 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16797 = eq(_T_16796, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_16798 = and(_T_16795, _T_16797) @[ifu_bp_ctl.scala 442:45] - node _T_16799 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16800 = eq(_T_16799, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_16801 = or(_T_16800, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16802 = and(_T_16798, _T_16801) @[ifu_bp_ctl.scala 442:110] - node _T_16803 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16804 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16805 = eq(_T_16804, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_16806 = and(_T_16803, _T_16805) @[ifu_bp_ctl.scala 443:22] - node _T_16807 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16808 = eq(_T_16807, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_16809 = or(_T_16808, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16810 = and(_T_16806, _T_16809) @[ifu_bp_ctl.scala 443:87] - node _T_16811 = or(_T_16802, _T_16810) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][4][11] <= _T_16811 @[ifu_bp_ctl.scala 442:27] - node _T_16812 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16813 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16814 = eq(_T_16813, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_16815 = and(_T_16812, _T_16814) @[ifu_bp_ctl.scala 442:45] - node _T_16816 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16817 = eq(_T_16816, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_16818 = or(_T_16817, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16819 = and(_T_16815, _T_16818) @[ifu_bp_ctl.scala 442:110] - node _T_16820 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16821 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16822 = eq(_T_16821, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_16823 = and(_T_16820, _T_16822) @[ifu_bp_ctl.scala 443:22] - node _T_16824 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16825 = eq(_T_16824, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_16826 = or(_T_16825, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16827 = and(_T_16823, _T_16826) @[ifu_bp_ctl.scala 443:87] - node _T_16828 = or(_T_16819, _T_16827) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][4][12] <= _T_16828 @[ifu_bp_ctl.scala 442:27] - node _T_16829 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16830 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16831 = eq(_T_16830, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_16832 = and(_T_16829, _T_16831) @[ifu_bp_ctl.scala 442:45] - node _T_16833 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16834 = eq(_T_16833, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_16835 = or(_T_16834, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16836 = and(_T_16832, _T_16835) @[ifu_bp_ctl.scala 442:110] - node _T_16837 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16838 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16839 = eq(_T_16838, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_16840 = and(_T_16837, _T_16839) @[ifu_bp_ctl.scala 443:22] - node _T_16841 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16842 = eq(_T_16841, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_16843 = or(_T_16842, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16844 = and(_T_16840, _T_16843) @[ifu_bp_ctl.scala 443:87] - node _T_16845 = or(_T_16836, _T_16844) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][4][13] <= _T_16845 @[ifu_bp_ctl.scala 442:27] - node _T_16846 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16847 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16848 = eq(_T_16847, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_16849 = and(_T_16846, _T_16848) @[ifu_bp_ctl.scala 442:45] - node _T_16850 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16851 = eq(_T_16850, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_16852 = or(_T_16851, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16853 = and(_T_16849, _T_16852) @[ifu_bp_ctl.scala 442:110] - node _T_16854 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16855 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16856 = eq(_T_16855, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_16857 = and(_T_16854, _T_16856) @[ifu_bp_ctl.scala 443:22] - node _T_16858 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16859 = eq(_T_16858, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_16860 = or(_T_16859, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16861 = and(_T_16857, _T_16860) @[ifu_bp_ctl.scala 443:87] - node _T_16862 = or(_T_16853, _T_16861) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][4][14] <= _T_16862 @[ifu_bp_ctl.scala 442:27] - node _T_16863 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16864 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16865 = eq(_T_16864, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_16866 = and(_T_16863, _T_16865) @[ifu_bp_ctl.scala 442:45] - node _T_16867 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16868 = eq(_T_16867, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:186] - node _T_16869 = or(_T_16868, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16870 = and(_T_16866, _T_16869) @[ifu_bp_ctl.scala 442:110] - node _T_16871 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16872 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16873 = eq(_T_16872, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_16874 = and(_T_16871, _T_16873) @[ifu_bp_ctl.scala 443:22] - node _T_16875 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16876 = eq(_T_16875, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:163] - node _T_16877 = or(_T_16876, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16878 = and(_T_16874, _T_16877) @[ifu_bp_ctl.scala 443:87] - node _T_16879 = or(_T_16870, _T_16878) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][4][15] <= _T_16879 @[ifu_bp_ctl.scala 442:27] - node _T_16880 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16881 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16882 = eq(_T_16881, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_16883 = and(_T_16880, _T_16882) @[ifu_bp_ctl.scala 442:45] - node _T_16884 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16885 = eq(_T_16884, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_16886 = or(_T_16885, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16887 = and(_T_16883, _T_16886) @[ifu_bp_ctl.scala 442:110] - node _T_16888 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16889 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16890 = eq(_T_16889, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_16891 = and(_T_16888, _T_16890) @[ifu_bp_ctl.scala 443:22] - node _T_16892 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16893 = eq(_T_16892, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_16894 = or(_T_16893, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16895 = and(_T_16891, _T_16894) @[ifu_bp_ctl.scala 443:87] - node _T_16896 = or(_T_16887, _T_16895) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][5][0] <= _T_16896 @[ifu_bp_ctl.scala 442:27] - node _T_16897 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16898 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16899 = eq(_T_16898, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_16900 = and(_T_16897, _T_16899) @[ifu_bp_ctl.scala 442:45] - node _T_16901 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16902 = eq(_T_16901, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_16903 = or(_T_16902, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16904 = and(_T_16900, _T_16903) @[ifu_bp_ctl.scala 442:110] - node _T_16905 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16906 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16907 = eq(_T_16906, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_16908 = and(_T_16905, _T_16907) @[ifu_bp_ctl.scala 443:22] - node _T_16909 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16910 = eq(_T_16909, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_16911 = or(_T_16910, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16912 = and(_T_16908, _T_16911) @[ifu_bp_ctl.scala 443:87] - node _T_16913 = or(_T_16904, _T_16912) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][5][1] <= _T_16913 @[ifu_bp_ctl.scala 442:27] - node _T_16914 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16915 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16916 = eq(_T_16915, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_16917 = and(_T_16914, _T_16916) @[ifu_bp_ctl.scala 442:45] - node _T_16918 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16919 = eq(_T_16918, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_16920 = or(_T_16919, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16921 = and(_T_16917, _T_16920) @[ifu_bp_ctl.scala 442:110] - node _T_16922 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16923 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16924 = eq(_T_16923, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_16925 = and(_T_16922, _T_16924) @[ifu_bp_ctl.scala 443:22] - node _T_16926 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16927 = eq(_T_16926, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_16928 = or(_T_16927, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16929 = and(_T_16925, _T_16928) @[ifu_bp_ctl.scala 443:87] - node _T_16930 = or(_T_16921, _T_16929) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][5][2] <= _T_16930 @[ifu_bp_ctl.scala 442:27] - node _T_16931 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16932 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16933 = eq(_T_16932, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_16934 = and(_T_16931, _T_16933) @[ifu_bp_ctl.scala 442:45] - node _T_16935 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16936 = eq(_T_16935, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_16937 = or(_T_16936, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16938 = and(_T_16934, _T_16937) @[ifu_bp_ctl.scala 442:110] - node _T_16939 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16940 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16941 = eq(_T_16940, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_16942 = and(_T_16939, _T_16941) @[ifu_bp_ctl.scala 443:22] - node _T_16943 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16944 = eq(_T_16943, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_16945 = or(_T_16944, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16946 = and(_T_16942, _T_16945) @[ifu_bp_ctl.scala 443:87] - node _T_16947 = or(_T_16938, _T_16946) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][5][3] <= _T_16947 @[ifu_bp_ctl.scala 442:27] - node _T_16948 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16949 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16950 = eq(_T_16949, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_16951 = and(_T_16948, _T_16950) @[ifu_bp_ctl.scala 442:45] - node _T_16952 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16953 = eq(_T_16952, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_16954 = or(_T_16953, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16955 = and(_T_16951, _T_16954) @[ifu_bp_ctl.scala 442:110] - node _T_16956 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16957 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16958 = eq(_T_16957, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_16959 = and(_T_16956, _T_16958) @[ifu_bp_ctl.scala 443:22] - node _T_16960 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16961 = eq(_T_16960, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_16962 = or(_T_16961, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16963 = and(_T_16959, _T_16962) @[ifu_bp_ctl.scala 443:87] - node _T_16964 = or(_T_16955, _T_16963) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][5][4] <= _T_16964 @[ifu_bp_ctl.scala 442:27] - node _T_16965 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16966 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16967 = eq(_T_16966, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_16968 = and(_T_16965, _T_16967) @[ifu_bp_ctl.scala 442:45] - node _T_16969 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16970 = eq(_T_16969, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_16971 = or(_T_16970, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16972 = and(_T_16968, _T_16971) @[ifu_bp_ctl.scala 442:110] - node _T_16973 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16974 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16975 = eq(_T_16974, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_16976 = and(_T_16973, _T_16975) @[ifu_bp_ctl.scala 443:22] - node _T_16977 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16978 = eq(_T_16977, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_16979 = or(_T_16978, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16980 = and(_T_16976, _T_16979) @[ifu_bp_ctl.scala 443:87] - node _T_16981 = or(_T_16972, _T_16980) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][5][5] <= _T_16981 @[ifu_bp_ctl.scala 442:27] - node _T_16982 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_16983 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_16984 = eq(_T_16983, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_16985 = and(_T_16982, _T_16984) @[ifu_bp_ctl.scala 442:45] - node _T_16986 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_16987 = eq(_T_16986, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_16988 = or(_T_16987, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_16989 = and(_T_16985, _T_16988) @[ifu_bp_ctl.scala 442:110] - node _T_16990 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_16991 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_16992 = eq(_T_16991, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_16993 = and(_T_16990, _T_16992) @[ifu_bp_ctl.scala 443:22] - node _T_16994 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_16995 = eq(_T_16994, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_16996 = or(_T_16995, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_16997 = and(_T_16993, _T_16996) @[ifu_bp_ctl.scala 443:87] - node _T_16998 = or(_T_16989, _T_16997) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][5][6] <= _T_16998 @[ifu_bp_ctl.scala 442:27] - node _T_16999 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17000 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17001 = eq(_T_17000, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_17002 = and(_T_16999, _T_17001) @[ifu_bp_ctl.scala 442:45] - node _T_17003 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17004 = eq(_T_17003, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_17005 = or(_T_17004, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17006 = and(_T_17002, _T_17005) @[ifu_bp_ctl.scala 442:110] - node _T_17007 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17008 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17009 = eq(_T_17008, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_17010 = and(_T_17007, _T_17009) @[ifu_bp_ctl.scala 443:22] - node _T_17011 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17012 = eq(_T_17011, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_17013 = or(_T_17012, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17014 = and(_T_17010, _T_17013) @[ifu_bp_ctl.scala 443:87] - node _T_17015 = or(_T_17006, _T_17014) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][5][7] <= _T_17015 @[ifu_bp_ctl.scala 442:27] - node _T_17016 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17017 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17018 = eq(_T_17017, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_17019 = and(_T_17016, _T_17018) @[ifu_bp_ctl.scala 442:45] - node _T_17020 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17021 = eq(_T_17020, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_17022 = or(_T_17021, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17023 = and(_T_17019, _T_17022) @[ifu_bp_ctl.scala 442:110] - node _T_17024 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17025 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17026 = eq(_T_17025, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_17027 = and(_T_17024, _T_17026) @[ifu_bp_ctl.scala 443:22] - node _T_17028 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17029 = eq(_T_17028, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_17030 = or(_T_17029, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17031 = and(_T_17027, _T_17030) @[ifu_bp_ctl.scala 443:87] - node _T_17032 = or(_T_17023, _T_17031) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][5][8] <= _T_17032 @[ifu_bp_ctl.scala 442:27] - node _T_17033 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17034 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17035 = eq(_T_17034, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_17036 = and(_T_17033, _T_17035) @[ifu_bp_ctl.scala 442:45] - node _T_17037 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17038 = eq(_T_17037, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_17039 = or(_T_17038, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17040 = and(_T_17036, _T_17039) @[ifu_bp_ctl.scala 442:110] - node _T_17041 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17042 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17043 = eq(_T_17042, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_17044 = and(_T_17041, _T_17043) @[ifu_bp_ctl.scala 443:22] - node _T_17045 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17046 = eq(_T_17045, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_17047 = or(_T_17046, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17048 = and(_T_17044, _T_17047) @[ifu_bp_ctl.scala 443:87] - node _T_17049 = or(_T_17040, _T_17048) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][5][9] <= _T_17049 @[ifu_bp_ctl.scala 442:27] - node _T_17050 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17051 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17052 = eq(_T_17051, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_17053 = and(_T_17050, _T_17052) @[ifu_bp_ctl.scala 442:45] - node _T_17054 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17055 = eq(_T_17054, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_17056 = or(_T_17055, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17057 = and(_T_17053, _T_17056) @[ifu_bp_ctl.scala 442:110] - node _T_17058 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17059 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17060 = eq(_T_17059, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_17061 = and(_T_17058, _T_17060) @[ifu_bp_ctl.scala 443:22] - node _T_17062 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17063 = eq(_T_17062, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_17064 = or(_T_17063, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17065 = and(_T_17061, _T_17064) @[ifu_bp_ctl.scala 443:87] - node _T_17066 = or(_T_17057, _T_17065) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][5][10] <= _T_17066 @[ifu_bp_ctl.scala 442:27] - node _T_17067 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17068 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17069 = eq(_T_17068, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_17070 = and(_T_17067, _T_17069) @[ifu_bp_ctl.scala 442:45] - node _T_17071 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17072 = eq(_T_17071, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_17073 = or(_T_17072, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17074 = and(_T_17070, _T_17073) @[ifu_bp_ctl.scala 442:110] - node _T_17075 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17076 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17077 = eq(_T_17076, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_17078 = and(_T_17075, _T_17077) @[ifu_bp_ctl.scala 443:22] - node _T_17079 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17080 = eq(_T_17079, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_17081 = or(_T_17080, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17082 = and(_T_17078, _T_17081) @[ifu_bp_ctl.scala 443:87] - node _T_17083 = or(_T_17074, _T_17082) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][5][11] <= _T_17083 @[ifu_bp_ctl.scala 442:27] - node _T_17084 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17085 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17086 = eq(_T_17085, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_17087 = and(_T_17084, _T_17086) @[ifu_bp_ctl.scala 442:45] - node _T_17088 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17089 = eq(_T_17088, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_17090 = or(_T_17089, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17091 = and(_T_17087, _T_17090) @[ifu_bp_ctl.scala 442:110] - node _T_17092 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17093 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17094 = eq(_T_17093, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_17095 = and(_T_17092, _T_17094) @[ifu_bp_ctl.scala 443:22] - node _T_17096 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17097 = eq(_T_17096, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_17098 = or(_T_17097, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17099 = and(_T_17095, _T_17098) @[ifu_bp_ctl.scala 443:87] - node _T_17100 = or(_T_17091, _T_17099) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][5][12] <= _T_17100 @[ifu_bp_ctl.scala 442:27] - node _T_17101 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17102 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17103 = eq(_T_17102, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_17104 = and(_T_17101, _T_17103) @[ifu_bp_ctl.scala 442:45] - node _T_17105 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17106 = eq(_T_17105, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_17107 = or(_T_17106, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17108 = and(_T_17104, _T_17107) @[ifu_bp_ctl.scala 442:110] - node _T_17109 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17110 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17111 = eq(_T_17110, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_17112 = and(_T_17109, _T_17111) @[ifu_bp_ctl.scala 443:22] - node _T_17113 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17114 = eq(_T_17113, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_17115 = or(_T_17114, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17116 = and(_T_17112, _T_17115) @[ifu_bp_ctl.scala 443:87] - node _T_17117 = or(_T_17108, _T_17116) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][5][13] <= _T_17117 @[ifu_bp_ctl.scala 442:27] - node _T_17118 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17119 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17120 = eq(_T_17119, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_17121 = and(_T_17118, _T_17120) @[ifu_bp_ctl.scala 442:45] - node _T_17122 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17123 = eq(_T_17122, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_17124 = or(_T_17123, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17125 = and(_T_17121, _T_17124) @[ifu_bp_ctl.scala 442:110] - node _T_17126 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17127 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17128 = eq(_T_17127, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_17129 = and(_T_17126, _T_17128) @[ifu_bp_ctl.scala 443:22] - node _T_17130 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17131 = eq(_T_17130, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_17132 = or(_T_17131, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17133 = and(_T_17129, _T_17132) @[ifu_bp_ctl.scala 443:87] - node _T_17134 = or(_T_17125, _T_17133) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][5][14] <= _T_17134 @[ifu_bp_ctl.scala 442:27] - node _T_17135 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17136 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17137 = eq(_T_17136, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_17138 = and(_T_17135, _T_17137) @[ifu_bp_ctl.scala 442:45] - node _T_17139 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17140 = eq(_T_17139, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:186] - node _T_17141 = or(_T_17140, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17142 = and(_T_17138, _T_17141) @[ifu_bp_ctl.scala 442:110] - node _T_17143 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17144 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17145 = eq(_T_17144, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_17146 = and(_T_17143, _T_17145) @[ifu_bp_ctl.scala 443:22] - node _T_17147 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17148 = eq(_T_17147, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:163] - node _T_17149 = or(_T_17148, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17150 = and(_T_17146, _T_17149) @[ifu_bp_ctl.scala 443:87] - node _T_17151 = or(_T_17142, _T_17150) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][5][15] <= _T_17151 @[ifu_bp_ctl.scala 442:27] - node _T_17152 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17153 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17154 = eq(_T_17153, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_17155 = and(_T_17152, _T_17154) @[ifu_bp_ctl.scala 442:45] - node _T_17156 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17157 = eq(_T_17156, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_17158 = or(_T_17157, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17159 = and(_T_17155, _T_17158) @[ifu_bp_ctl.scala 442:110] - node _T_17160 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17161 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17162 = eq(_T_17161, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_17163 = and(_T_17160, _T_17162) @[ifu_bp_ctl.scala 443:22] - node _T_17164 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17165 = eq(_T_17164, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_17166 = or(_T_17165, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17167 = and(_T_17163, _T_17166) @[ifu_bp_ctl.scala 443:87] - node _T_17168 = or(_T_17159, _T_17167) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][6][0] <= _T_17168 @[ifu_bp_ctl.scala 442:27] - node _T_17169 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17170 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17171 = eq(_T_17170, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_17172 = and(_T_17169, _T_17171) @[ifu_bp_ctl.scala 442:45] - node _T_17173 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17174 = eq(_T_17173, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_17175 = or(_T_17174, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17176 = and(_T_17172, _T_17175) @[ifu_bp_ctl.scala 442:110] - node _T_17177 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17178 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17179 = eq(_T_17178, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_17180 = and(_T_17177, _T_17179) @[ifu_bp_ctl.scala 443:22] - node _T_17181 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17182 = eq(_T_17181, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_17183 = or(_T_17182, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17184 = and(_T_17180, _T_17183) @[ifu_bp_ctl.scala 443:87] - node _T_17185 = or(_T_17176, _T_17184) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][6][1] <= _T_17185 @[ifu_bp_ctl.scala 442:27] - node _T_17186 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17187 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17188 = eq(_T_17187, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_17189 = and(_T_17186, _T_17188) @[ifu_bp_ctl.scala 442:45] - node _T_17190 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17191 = eq(_T_17190, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_17192 = or(_T_17191, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17193 = and(_T_17189, _T_17192) @[ifu_bp_ctl.scala 442:110] - node _T_17194 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17195 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17196 = eq(_T_17195, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_17197 = and(_T_17194, _T_17196) @[ifu_bp_ctl.scala 443:22] - node _T_17198 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17199 = eq(_T_17198, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_17200 = or(_T_17199, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17201 = and(_T_17197, _T_17200) @[ifu_bp_ctl.scala 443:87] - node _T_17202 = or(_T_17193, _T_17201) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][6][2] <= _T_17202 @[ifu_bp_ctl.scala 442:27] - node _T_17203 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17204 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17205 = eq(_T_17204, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_17206 = and(_T_17203, _T_17205) @[ifu_bp_ctl.scala 442:45] - node _T_17207 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17208 = eq(_T_17207, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_17209 = or(_T_17208, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17210 = and(_T_17206, _T_17209) @[ifu_bp_ctl.scala 442:110] - node _T_17211 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17212 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17213 = eq(_T_17212, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_17214 = and(_T_17211, _T_17213) @[ifu_bp_ctl.scala 443:22] - node _T_17215 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17216 = eq(_T_17215, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_17217 = or(_T_17216, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17218 = and(_T_17214, _T_17217) @[ifu_bp_ctl.scala 443:87] - node _T_17219 = or(_T_17210, _T_17218) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][6][3] <= _T_17219 @[ifu_bp_ctl.scala 442:27] - node _T_17220 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17221 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17222 = eq(_T_17221, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_17223 = and(_T_17220, _T_17222) @[ifu_bp_ctl.scala 442:45] - node _T_17224 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17225 = eq(_T_17224, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_17226 = or(_T_17225, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17227 = and(_T_17223, _T_17226) @[ifu_bp_ctl.scala 442:110] - node _T_17228 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17229 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17230 = eq(_T_17229, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_17231 = and(_T_17228, _T_17230) @[ifu_bp_ctl.scala 443:22] - node _T_17232 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17233 = eq(_T_17232, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_17234 = or(_T_17233, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17235 = and(_T_17231, _T_17234) @[ifu_bp_ctl.scala 443:87] - node _T_17236 = or(_T_17227, _T_17235) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][6][4] <= _T_17236 @[ifu_bp_ctl.scala 442:27] - node _T_17237 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17238 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17239 = eq(_T_17238, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_17240 = and(_T_17237, _T_17239) @[ifu_bp_ctl.scala 442:45] - node _T_17241 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17242 = eq(_T_17241, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_17243 = or(_T_17242, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17244 = and(_T_17240, _T_17243) @[ifu_bp_ctl.scala 442:110] - node _T_17245 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17246 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17247 = eq(_T_17246, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_17248 = and(_T_17245, _T_17247) @[ifu_bp_ctl.scala 443:22] - node _T_17249 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17250 = eq(_T_17249, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_17251 = or(_T_17250, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17252 = and(_T_17248, _T_17251) @[ifu_bp_ctl.scala 443:87] - node _T_17253 = or(_T_17244, _T_17252) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][6][5] <= _T_17253 @[ifu_bp_ctl.scala 442:27] - node _T_17254 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17255 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17256 = eq(_T_17255, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_17257 = and(_T_17254, _T_17256) @[ifu_bp_ctl.scala 442:45] - node _T_17258 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17259 = eq(_T_17258, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_17260 = or(_T_17259, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17261 = and(_T_17257, _T_17260) @[ifu_bp_ctl.scala 442:110] - node _T_17262 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17263 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17264 = eq(_T_17263, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_17265 = and(_T_17262, _T_17264) @[ifu_bp_ctl.scala 443:22] - node _T_17266 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17267 = eq(_T_17266, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_17268 = or(_T_17267, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17269 = and(_T_17265, _T_17268) @[ifu_bp_ctl.scala 443:87] - node _T_17270 = or(_T_17261, _T_17269) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][6][6] <= _T_17270 @[ifu_bp_ctl.scala 442:27] - node _T_17271 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17272 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17273 = eq(_T_17272, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_17274 = and(_T_17271, _T_17273) @[ifu_bp_ctl.scala 442:45] - node _T_17275 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17276 = eq(_T_17275, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_17277 = or(_T_17276, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17278 = and(_T_17274, _T_17277) @[ifu_bp_ctl.scala 442:110] - node _T_17279 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17280 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17281 = eq(_T_17280, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_17282 = and(_T_17279, _T_17281) @[ifu_bp_ctl.scala 443:22] - node _T_17283 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17284 = eq(_T_17283, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_17285 = or(_T_17284, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17286 = and(_T_17282, _T_17285) @[ifu_bp_ctl.scala 443:87] - node _T_17287 = or(_T_17278, _T_17286) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][6][7] <= _T_17287 @[ifu_bp_ctl.scala 442:27] - node _T_17288 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17289 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17290 = eq(_T_17289, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_17291 = and(_T_17288, _T_17290) @[ifu_bp_ctl.scala 442:45] - node _T_17292 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17293 = eq(_T_17292, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_17294 = or(_T_17293, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17295 = and(_T_17291, _T_17294) @[ifu_bp_ctl.scala 442:110] - node _T_17296 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17297 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17298 = eq(_T_17297, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_17299 = and(_T_17296, _T_17298) @[ifu_bp_ctl.scala 443:22] - node _T_17300 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17301 = eq(_T_17300, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_17302 = or(_T_17301, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17303 = and(_T_17299, _T_17302) @[ifu_bp_ctl.scala 443:87] - node _T_17304 = or(_T_17295, _T_17303) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][6][8] <= _T_17304 @[ifu_bp_ctl.scala 442:27] - node _T_17305 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17306 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17307 = eq(_T_17306, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_17308 = and(_T_17305, _T_17307) @[ifu_bp_ctl.scala 442:45] - node _T_17309 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17310 = eq(_T_17309, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_17311 = or(_T_17310, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17312 = and(_T_17308, _T_17311) @[ifu_bp_ctl.scala 442:110] - node _T_17313 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17314 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17315 = eq(_T_17314, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_17316 = and(_T_17313, _T_17315) @[ifu_bp_ctl.scala 443:22] - node _T_17317 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17318 = eq(_T_17317, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_17319 = or(_T_17318, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17320 = and(_T_17316, _T_17319) @[ifu_bp_ctl.scala 443:87] - node _T_17321 = or(_T_17312, _T_17320) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][6][9] <= _T_17321 @[ifu_bp_ctl.scala 442:27] - node _T_17322 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17323 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17324 = eq(_T_17323, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_17325 = and(_T_17322, _T_17324) @[ifu_bp_ctl.scala 442:45] - node _T_17326 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17327 = eq(_T_17326, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_17328 = or(_T_17327, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17329 = and(_T_17325, _T_17328) @[ifu_bp_ctl.scala 442:110] - node _T_17330 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17331 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17332 = eq(_T_17331, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_17333 = and(_T_17330, _T_17332) @[ifu_bp_ctl.scala 443:22] - node _T_17334 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17335 = eq(_T_17334, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_17336 = or(_T_17335, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17337 = and(_T_17333, _T_17336) @[ifu_bp_ctl.scala 443:87] - node _T_17338 = or(_T_17329, _T_17337) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][6][10] <= _T_17338 @[ifu_bp_ctl.scala 442:27] - node _T_17339 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17340 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17341 = eq(_T_17340, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_17342 = and(_T_17339, _T_17341) @[ifu_bp_ctl.scala 442:45] - node _T_17343 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17344 = eq(_T_17343, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_17345 = or(_T_17344, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17346 = and(_T_17342, _T_17345) @[ifu_bp_ctl.scala 442:110] - node _T_17347 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17348 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17349 = eq(_T_17348, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_17350 = and(_T_17347, _T_17349) @[ifu_bp_ctl.scala 443:22] - node _T_17351 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17352 = eq(_T_17351, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_17353 = or(_T_17352, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17354 = and(_T_17350, _T_17353) @[ifu_bp_ctl.scala 443:87] - node _T_17355 = or(_T_17346, _T_17354) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][6][11] <= _T_17355 @[ifu_bp_ctl.scala 442:27] - node _T_17356 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17357 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17358 = eq(_T_17357, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_17359 = and(_T_17356, _T_17358) @[ifu_bp_ctl.scala 442:45] - node _T_17360 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17361 = eq(_T_17360, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_17362 = or(_T_17361, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17363 = and(_T_17359, _T_17362) @[ifu_bp_ctl.scala 442:110] - node _T_17364 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17365 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17366 = eq(_T_17365, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_17367 = and(_T_17364, _T_17366) @[ifu_bp_ctl.scala 443:22] - node _T_17368 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17369 = eq(_T_17368, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_17370 = or(_T_17369, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17371 = and(_T_17367, _T_17370) @[ifu_bp_ctl.scala 443:87] - node _T_17372 = or(_T_17363, _T_17371) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][6][12] <= _T_17372 @[ifu_bp_ctl.scala 442:27] - node _T_17373 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17374 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17375 = eq(_T_17374, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_17376 = and(_T_17373, _T_17375) @[ifu_bp_ctl.scala 442:45] - node _T_17377 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17378 = eq(_T_17377, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_17379 = or(_T_17378, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17380 = and(_T_17376, _T_17379) @[ifu_bp_ctl.scala 442:110] - node _T_17381 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17382 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17383 = eq(_T_17382, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_17384 = and(_T_17381, _T_17383) @[ifu_bp_ctl.scala 443:22] - node _T_17385 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17386 = eq(_T_17385, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_17387 = or(_T_17386, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17388 = and(_T_17384, _T_17387) @[ifu_bp_ctl.scala 443:87] - node _T_17389 = or(_T_17380, _T_17388) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][6][13] <= _T_17389 @[ifu_bp_ctl.scala 442:27] - node _T_17390 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17391 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17392 = eq(_T_17391, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_17393 = and(_T_17390, _T_17392) @[ifu_bp_ctl.scala 442:45] - node _T_17394 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17395 = eq(_T_17394, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_17396 = or(_T_17395, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17397 = and(_T_17393, _T_17396) @[ifu_bp_ctl.scala 442:110] - node _T_17398 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17399 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17400 = eq(_T_17399, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_17401 = and(_T_17398, _T_17400) @[ifu_bp_ctl.scala 443:22] - node _T_17402 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17403 = eq(_T_17402, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_17404 = or(_T_17403, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17405 = and(_T_17401, _T_17404) @[ifu_bp_ctl.scala 443:87] - node _T_17406 = or(_T_17397, _T_17405) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][6][14] <= _T_17406 @[ifu_bp_ctl.scala 442:27] - node _T_17407 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17408 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17409 = eq(_T_17408, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_17410 = and(_T_17407, _T_17409) @[ifu_bp_ctl.scala 442:45] - node _T_17411 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17412 = eq(_T_17411, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:186] - node _T_17413 = or(_T_17412, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17414 = and(_T_17410, _T_17413) @[ifu_bp_ctl.scala 442:110] - node _T_17415 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17416 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17417 = eq(_T_17416, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_17418 = and(_T_17415, _T_17417) @[ifu_bp_ctl.scala 443:22] - node _T_17419 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17420 = eq(_T_17419, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:163] - node _T_17421 = or(_T_17420, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17422 = and(_T_17418, _T_17421) @[ifu_bp_ctl.scala 443:87] - node _T_17423 = or(_T_17414, _T_17422) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][6][15] <= _T_17423 @[ifu_bp_ctl.scala 442:27] - node _T_17424 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17425 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17426 = eq(_T_17425, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_17427 = and(_T_17424, _T_17426) @[ifu_bp_ctl.scala 442:45] - node _T_17428 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17429 = eq(_T_17428, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_17430 = or(_T_17429, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17431 = and(_T_17427, _T_17430) @[ifu_bp_ctl.scala 442:110] - node _T_17432 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17433 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17434 = eq(_T_17433, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_17435 = and(_T_17432, _T_17434) @[ifu_bp_ctl.scala 443:22] - node _T_17436 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17437 = eq(_T_17436, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_17438 = or(_T_17437, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17439 = and(_T_17435, _T_17438) @[ifu_bp_ctl.scala 443:87] - node _T_17440 = or(_T_17431, _T_17439) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][7][0] <= _T_17440 @[ifu_bp_ctl.scala 442:27] - node _T_17441 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17442 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17443 = eq(_T_17442, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_17444 = and(_T_17441, _T_17443) @[ifu_bp_ctl.scala 442:45] - node _T_17445 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17446 = eq(_T_17445, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_17447 = or(_T_17446, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17448 = and(_T_17444, _T_17447) @[ifu_bp_ctl.scala 442:110] - node _T_17449 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17450 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17451 = eq(_T_17450, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_17452 = and(_T_17449, _T_17451) @[ifu_bp_ctl.scala 443:22] - node _T_17453 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17454 = eq(_T_17453, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_17455 = or(_T_17454, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17456 = and(_T_17452, _T_17455) @[ifu_bp_ctl.scala 443:87] - node _T_17457 = or(_T_17448, _T_17456) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][7][1] <= _T_17457 @[ifu_bp_ctl.scala 442:27] - node _T_17458 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17459 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17460 = eq(_T_17459, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_17461 = and(_T_17458, _T_17460) @[ifu_bp_ctl.scala 442:45] - node _T_17462 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17463 = eq(_T_17462, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_17464 = or(_T_17463, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17465 = and(_T_17461, _T_17464) @[ifu_bp_ctl.scala 442:110] - node _T_17466 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17467 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17468 = eq(_T_17467, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_17469 = and(_T_17466, _T_17468) @[ifu_bp_ctl.scala 443:22] - node _T_17470 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17471 = eq(_T_17470, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_17472 = or(_T_17471, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17473 = and(_T_17469, _T_17472) @[ifu_bp_ctl.scala 443:87] - node _T_17474 = or(_T_17465, _T_17473) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][7][2] <= _T_17474 @[ifu_bp_ctl.scala 442:27] - node _T_17475 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17476 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17477 = eq(_T_17476, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_17478 = and(_T_17475, _T_17477) @[ifu_bp_ctl.scala 442:45] - node _T_17479 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17480 = eq(_T_17479, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_17481 = or(_T_17480, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17482 = and(_T_17478, _T_17481) @[ifu_bp_ctl.scala 442:110] - node _T_17483 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17484 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17485 = eq(_T_17484, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_17486 = and(_T_17483, _T_17485) @[ifu_bp_ctl.scala 443:22] - node _T_17487 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17488 = eq(_T_17487, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_17489 = or(_T_17488, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17490 = and(_T_17486, _T_17489) @[ifu_bp_ctl.scala 443:87] - node _T_17491 = or(_T_17482, _T_17490) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][7][3] <= _T_17491 @[ifu_bp_ctl.scala 442:27] - node _T_17492 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17493 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17494 = eq(_T_17493, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_17495 = and(_T_17492, _T_17494) @[ifu_bp_ctl.scala 442:45] - node _T_17496 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17497 = eq(_T_17496, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_17498 = or(_T_17497, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17499 = and(_T_17495, _T_17498) @[ifu_bp_ctl.scala 442:110] - node _T_17500 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17501 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17502 = eq(_T_17501, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_17503 = and(_T_17500, _T_17502) @[ifu_bp_ctl.scala 443:22] - node _T_17504 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17505 = eq(_T_17504, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_17506 = or(_T_17505, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17507 = and(_T_17503, _T_17506) @[ifu_bp_ctl.scala 443:87] - node _T_17508 = or(_T_17499, _T_17507) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][7][4] <= _T_17508 @[ifu_bp_ctl.scala 442:27] - node _T_17509 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17510 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17511 = eq(_T_17510, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_17512 = and(_T_17509, _T_17511) @[ifu_bp_ctl.scala 442:45] - node _T_17513 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17514 = eq(_T_17513, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_17515 = or(_T_17514, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17516 = and(_T_17512, _T_17515) @[ifu_bp_ctl.scala 442:110] - node _T_17517 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17518 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17519 = eq(_T_17518, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_17520 = and(_T_17517, _T_17519) @[ifu_bp_ctl.scala 443:22] - node _T_17521 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17522 = eq(_T_17521, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_17523 = or(_T_17522, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17524 = and(_T_17520, _T_17523) @[ifu_bp_ctl.scala 443:87] - node _T_17525 = or(_T_17516, _T_17524) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][7][5] <= _T_17525 @[ifu_bp_ctl.scala 442:27] - node _T_17526 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17527 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17528 = eq(_T_17527, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_17529 = and(_T_17526, _T_17528) @[ifu_bp_ctl.scala 442:45] - node _T_17530 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17531 = eq(_T_17530, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_17532 = or(_T_17531, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17533 = and(_T_17529, _T_17532) @[ifu_bp_ctl.scala 442:110] - node _T_17534 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17535 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17536 = eq(_T_17535, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_17537 = and(_T_17534, _T_17536) @[ifu_bp_ctl.scala 443:22] - node _T_17538 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17539 = eq(_T_17538, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_17540 = or(_T_17539, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17541 = and(_T_17537, _T_17540) @[ifu_bp_ctl.scala 443:87] - node _T_17542 = or(_T_17533, _T_17541) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][7][6] <= _T_17542 @[ifu_bp_ctl.scala 442:27] - node _T_17543 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17544 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17545 = eq(_T_17544, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_17546 = and(_T_17543, _T_17545) @[ifu_bp_ctl.scala 442:45] - node _T_17547 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17548 = eq(_T_17547, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_17549 = or(_T_17548, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17550 = and(_T_17546, _T_17549) @[ifu_bp_ctl.scala 442:110] - node _T_17551 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17552 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17553 = eq(_T_17552, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_17554 = and(_T_17551, _T_17553) @[ifu_bp_ctl.scala 443:22] - node _T_17555 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17556 = eq(_T_17555, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_17557 = or(_T_17556, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17558 = and(_T_17554, _T_17557) @[ifu_bp_ctl.scala 443:87] - node _T_17559 = or(_T_17550, _T_17558) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][7][7] <= _T_17559 @[ifu_bp_ctl.scala 442:27] - node _T_17560 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17561 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17562 = eq(_T_17561, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_17563 = and(_T_17560, _T_17562) @[ifu_bp_ctl.scala 442:45] - node _T_17564 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17565 = eq(_T_17564, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_17566 = or(_T_17565, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17567 = and(_T_17563, _T_17566) @[ifu_bp_ctl.scala 442:110] - node _T_17568 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17569 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17570 = eq(_T_17569, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_17571 = and(_T_17568, _T_17570) @[ifu_bp_ctl.scala 443:22] - node _T_17572 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17573 = eq(_T_17572, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_17574 = or(_T_17573, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17575 = and(_T_17571, _T_17574) @[ifu_bp_ctl.scala 443:87] - node _T_17576 = or(_T_17567, _T_17575) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][7][8] <= _T_17576 @[ifu_bp_ctl.scala 442:27] - node _T_17577 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17578 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17579 = eq(_T_17578, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_17580 = and(_T_17577, _T_17579) @[ifu_bp_ctl.scala 442:45] - node _T_17581 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17582 = eq(_T_17581, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_17583 = or(_T_17582, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17584 = and(_T_17580, _T_17583) @[ifu_bp_ctl.scala 442:110] - node _T_17585 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17586 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17587 = eq(_T_17586, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_17588 = and(_T_17585, _T_17587) @[ifu_bp_ctl.scala 443:22] - node _T_17589 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17590 = eq(_T_17589, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_17591 = or(_T_17590, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17592 = and(_T_17588, _T_17591) @[ifu_bp_ctl.scala 443:87] - node _T_17593 = or(_T_17584, _T_17592) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][7][9] <= _T_17593 @[ifu_bp_ctl.scala 442:27] - node _T_17594 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17595 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17596 = eq(_T_17595, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_17597 = and(_T_17594, _T_17596) @[ifu_bp_ctl.scala 442:45] - node _T_17598 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17599 = eq(_T_17598, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_17600 = or(_T_17599, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17601 = and(_T_17597, _T_17600) @[ifu_bp_ctl.scala 442:110] - node _T_17602 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17603 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17604 = eq(_T_17603, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_17605 = and(_T_17602, _T_17604) @[ifu_bp_ctl.scala 443:22] - node _T_17606 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17607 = eq(_T_17606, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_17608 = or(_T_17607, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17609 = and(_T_17605, _T_17608) @[ifu_bp_ctl.scala 443:87] - node _T_17610 = or(_T_17601, _T_17609) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][7][10] <= _T_17610 @[ifu_bp_ctl.scala 442:27] - node _T_17611 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17612 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17613 = eq(_T_17612, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_17614 = and(_T_17611, _T_17613) @[ifu_bp_ctl.scala 442:45] - node _T_17615 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17616 = eq(_T_17615, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_17617 = or(_T_17616, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17618 = and(_T_17614, _T_17617) @[ifu_bp_ctl.scala 442:110] - node _T_17619 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17620 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17621 = eq(_T_17620, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_17622 = and(_T_17619, _T_17621) @[ifu_bp_ctl.scala 443:22] - node _T_17623 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17624 = eq(_T_17623, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_17625 = or(_T_17624, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17626 = and(_T_17622, _T_17625) @[ifu_bp_ctl.scala 443:87] - node _T_17627 = or(_T_17618, _T_17626) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][7][11] <= _T_17627 @[ifu_bp_ctl.scala 442:27] - node _T_17628 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17629 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17630 = eq(_T_17629, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_17631 = and(_T_17628, _T_17630) @[ifu_bp_ctl.scala 442:45] - node _T_17632 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17633 = eq(_T_17632, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_17634 = or(_T_17633, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17635 = and(_T_17631, _T_17634) @[ifu_bp_ctl.scala 442:110] - node _T_17636 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17637 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17638 = eq(_T_17637, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_17639 = and(_T_17636, _T_17638) @[ifu_bp_ctl.scala 443:22] - node _T_17640 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17641 = eq(_T_17640, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_17642 = or(_T_17641, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17643 = and(_T_17639, _T_17642) @[ifu_bp_ctl.scala 443:87] - node _T_17644 = or(_T_17635, _T_17643) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][7][12] <= _T_17644 @[ifu_bp_ctl.scala 442:27] - node _T_17645 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17646 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17647 = eq(_T_17646, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_17648 = and(_T_17645, _T_17647) @[ifu_bp_ctl.scala 442:45] - node _T_17649 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17650 = eq(_T_17649, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_17651 = or(_T_17650, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17652 = and(_T_17648, _T_17651) @[ifu_bp_ctl.scala 442:110] - node _T_17653 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17654 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17655 = eq(_T_17654, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_17656 = and(_T_17653, _T_17655) @[ifu_bp_ctl.scala 443:22] - node _T_17657 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17658 = eq(_T_17657, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_17659 = or(_T_17658, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17660 = and(_T_17656, _T_17659) @[ifu_bp_ctl.scala 443:87] - node _T_17661 = or(_T_17652, _T_17660) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][7][13] <= _T_17661 @[ifu_bp_ctl.scala 442:27] - node _T_17662 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17663 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17664 = eq(_T_17663, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_17665 = and(_T_17662, _T_17664) @[ifu_bp_ctl.scala 442:45] - node _T_17666 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17667 = eq(_T_17666, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_17668 = or(_T_17667, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17669 = and(_T_17665, _T_17668) @[ifu_bp_ctl.scala 442:110] - node _T_17670 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17671 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17672 = eq(_T_17671, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_17673 = and(_T_17670, _T_17672) @[ifu_bp_ctl.scala 443:22] - node _T_17674 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17675 = eq(_T_17674, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_17676 = or(_T_17675, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17677 = and(_T_17673, _T_17676) @[ifu_bp_ctl.scala 443:87] - node _T_17678 = or(_T_17669, _T_17677) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][7][14] <= _T_17678 @[ifu_bp_ctl.scala 442:27] - node _T_17679 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17680 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17681 = eq(_T_17680, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_17682 = and(_T_17679, _T_17681) @[ifu_bp_ctl.scala 442:45] - node _T_17683 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17684 = eq(_T_17683, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:186] - node _T_17685 = or(_T_17684, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17686 = and(_T_17682, _T_17685) @[ifu_bp_ctl.scala 442:110] - node _T_17687 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17688 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17689 = eq(_T_17688, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_17690 = and(_T_17687, _T_17689) @[ifu_bp_ctl.scala 443:22] - node _T_17691 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17692 = eq(_T_17691, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:163] - node _T_17693 = or(_T_17692, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17694 = and(_T_17690, _T_17693) @[ifu_bp_ctl.scala 443:87] - node _T_17695 = or(_T_17686, _T_17694) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][7][15] <= _T_17695 @[ifu_bp_ctl.scala 442:27] - node _T_17696 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17697 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17698 = eq(_T_17697, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_17699 = and(_T_17696, _T_17698) @[ifu_bp_ctl.scala 442:45] - node _T_17700 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17701 = eq(_T_17700, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_17702 = or(_T_17701, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17703 = and(_T_17699, _T_17702) @[ifu_bp_ctl.scala 442:110] - node _T_17704 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17705 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17706 = eq(_T_17705, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_17707 = and(_T_17704, _T_17706) @[ifu_bp_ctl.scala 443:22] - node _T_17708 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17709 = eq(_T_17708, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_17710 = or(_T_17709, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17711 = and(_T_17707, _T_17710) @[ifu_bp_ctl.scala 443:87] - node _T_17712 = or(_T_17703, _T_17711) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][8][0] <= _T_17712 @[ifu_bp_ctl.scala 442:27] - node _T_17713 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17714 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17715 = eq(_T_17714, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_17716 = and(_T_17713, _T_17715) @[ifu_bp_ctl.scala 442:45] - node _T_17717 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17718 = eq(_T_17717, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_17719 = or(_T_17718, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17720 = and(_T_17716, _T_17719) @[ifu_bp_ctl.scala 442:110] - node _T_17721 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17722 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17723 = eq(_T_17722, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_17724 = and(_T_17721, _T_17723) @[ifu_bp_ctl.scala 443:22] - node _T_17725 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17726 = eq(_T_17725, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_17727 = or(_T_17726, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17728 = and(_T_17724, _T_17727) @[ifu_bp_ctl.scala 443:87] - node _T_17729 = or(_T_17720, _T_17728) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][8][1] <= _T_17729 @[ifu_bp_ctl.scala 442:27] - node _T_17730 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17731 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17732 = eq(_T_17731, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_17733 = and(_T_17730, _T_17732) @[ifu_bp_ctl.scala 442:45] - node _T_17734 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17735 = eq(_T_17734, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_17736 = or(_T_17735, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17737 = and(_T_17733, _T_17736) @[ifu_bp_ctl.scala 442:110] - node _T_17738 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17739 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17740 = eq(_T_17739, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_17741 = and(_T_17738, _T_17740) @[ifu_bp_ctl.scala 443:22] - node _T_17742 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17743 = eq(_T_17742, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_17744 = or(_T_17743, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17745 = and(_T_17741, _T_17744) @[ifu_bp_ctl.scala 443:87] - node _T_17746 = or(_T_17737, _T_17745) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][8][2] <= _T_17746 @[ifu_bp_ctl.scala 442:27] - node _T_17747 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17748 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17749 = eq(_T_17748, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_17750 = and(_T_17747, _T_17749) @[ifu_bp_ctl.scala 442:45] - node _T_17751 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17752 = eq(_T_17751, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_17753 = or(_T_17752, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17754 = and(_T_17750, _T_17753) @[ifu_bp_ctl.scala 442:110] - node _T_17755 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17756 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17757 = eq(_T_17756, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_17758 = and(_T_17755, _T_17757) @[ifu_bp_ctl.scala 443:22] - node _T_17759 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17760 = eq(_T_17759, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_17761 = or(_T_17760, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17762 = and(_T_17758, _T_17761) @[ifu_bp_ctl.scala 443:87] - node _T_17763 = or(_T_17754, _T_17762) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][8][3] <= _T_17763 @[ifu_bp_ctl.scala 442:27] - node _T_17764 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17765 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17766 = eq(_T_17765, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_17767 = and(_T_17764, _T_17766) @[ifu_bp_ctl.scala 442:45] - node _T_17768 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17769 = eq(_T_17768, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_17770 = or(_T_17769, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17771 = and(_T_17767, _T_17770) @[ifu_bp_ctl.scala 442:110] - node _T_17772 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17773 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17774 = eq(_T_17773, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_17775 = and(_T_17772, _T_17774) @[ifu_bp_ctl.scala 443:22] - node _T_17776 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17777 = eq(_T_17776, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_17778 = or(_T_17777, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17779 = and(_T_17775, _T_17778) @[ifu_bp_ctl.scala 443:87] - node _T_17780 = or(_T_17771, _T_17779) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][8][4] <= _T_17780 @[ifu_bp_ctl.scala 442:27] - node _T_17781 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17782 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17783 = eq(_T_17782, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_17784 = and(_T_17781, _T_17783) @[ifu_bp_ctl.scala 442:45] - node _T_17785 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17786 = eq(_T_17785, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_17787 = or(_T_17786, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17788 = and(_T_17784, _T_17787) @[ifu_bp_ctl.scala 442:110] - node _T_17789 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17790 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17791 = eq(_T_17790, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_17792 = and(_T_17789, _T_17791) @[ifu_bp_ctl.scala 443:22] - node _T_17793 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17794 = eq(_T_17793, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_17795 = or(_T_17794, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17796 = and(_T_17792, _T_17795) @[ifu_bp_ctl.scala 443:87] - node _T_17797 = or(_T_17788, _T_17796) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][8][5] <= _T_17797 @[ifu_bp_ctl.scala 442:27] - node _T_17798 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17799 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17800 = eq(_T_17799, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_17801 = and(_T_17798, _T_17800) @[ifu_bp_ctl.scala 442:45] - node _T_17802 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17803 = eq(_T_17802, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_17804 = or(_T_17803, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17805 = and(_T_17801, _T_17804) @[ifu_bp_ctl.scala 442:110] - node _T_17806 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17807 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17808 = eq(_T_17807, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_17809 = and(_T_17806, _T_17808) @[ifu_bp_ctl.scala 443:22] - node _T_17810 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17811 = eq(_T_17810, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_17812 = or(_T_17811, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17813 = and(_T_17809, _T_17812) @[ifu_bp_ctl.scala 443:87] - node _T_17814 = or(_T_17805, _T_17813) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][8][6] <= _T_17814 @[ifu_bp_ctl.scala 442:27] - node _T_17815 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17816 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17817 = eq(_T_17816, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_17818 = and(_T_17815, _T_17817) @[ifu_bp_ctl.scala 442:45] - node _T_17819 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17820 = eq(_T_17819, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_17821 = or(_T_17820, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17822 = and(_T_17818, _T_17821) @[ifu_bp_ctl.scala 442:110] - node _T_17823 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17824 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17825 = eq(_T_17824, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_17826 = and(_T_17823, _T_17825) @[ifu_bp_ctl.scala 443:22] - node _T_17827 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17828 = eq(_T_17827, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_17829 = or(_T_17828, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17830 = and(_T_17826, _T_17829) @[ifu_bp_ctl.scala 443:87] - node _T_17831 = or(_T_17822, _T_17830) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][8][7] <= _T_17831 @[ifu_bp_ctl.scala 442:27] - node _T_17832 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17833 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17834 = eq(_T_17833, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_17835 = and(_T_17832, _T_17834) @[ifu_bp_ctl.scala 442:45] - node _T_17836 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17837 = eq(_T_17836, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_17838 = or(_T_17837, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17839 = and(_T_17835, _T_17838) @[ifu_bp_ctl.scala 442:110] - node _T_17840 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17841 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17842 = eq(_T_17841, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_17843 = and(_T_17840, _T_17842) @[ifu_bp_ctl.scala 443:22] - node _T_17844 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17845 = eq(_T_17844, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_17846 = or(_T_17845, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17847 = and(_T_17843, _T_17846) @[ifu_bp_ctl.scala 443:87] - node _T_17848 = or(_T_17839, _T_17847) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][8][8] <= _T_17848 @[ifu_bp_ctl.scala 442:27] - node _T_17849 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17850 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17851 = eq(_T_17850, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_17852 = and(_T_17849, _T_17851) @[ifu_bp_ctl.scala 442:45] - node _T_17853 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17854 = eq(_T_17853, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_17855 = or(_T_17854, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17856 = and(_T_17852, _T_17855) @[ifu_bp_ctl.scala 442:110] - node _T_17857 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17858 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17859 = eq(_T_17858, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_17860 = and(_T_17857, _T_17859) @[ifu_bp_ctl.scala 443:22] - node _T_17861 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17862 = eq(_T_17861, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_17863 = or(_T_17862, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17864 = and(_T_17860, _T_17863) @[ifu_bp_ctl.scala 443:87] - node _T_17865 = or(_T_17856, _T_17864) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][8][9] <= _T_17865 @[ifu_bp_ctl.scala 442:27] - node _T_17866 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17867 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17868 = eq(_T_17867, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_17869 = and(_T_17866, _T_17868) @[ifu_bp_ctl.scala 442:45] - node _T_17870 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17871 = eq(_T_17870, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_17872 = or(_T_17871, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17873 = and(_T_17869, _T_17872) @[ifu_bp_ctl.scala 442:110] - node _T_17874 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17875 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17876 = eq(_T_17875, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_17877 = and(_T_17874, _T_17876) @[ifu_bp_ctl.scala 443:22] - node _T_17878 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17879 = eq(_T_17878, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_17880 = or(_T_17879, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17881 = and(_T_17877, _T_17880) @[ifu_bp_ctl.scala 443:87] - node _T_17882 = or(_T_17873, _T_17881) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][8][10] <= _T_17882 @[ifu_bp_ctl.scala 442:27] - node _T_17883 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17884 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17885 = eq(_T_17884, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_17886 = and(_T_17883, _T_17885) @[ifu_bp_ctl.scala 442:45] - node _T_17887 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17888 = eq(_T_17887, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_17889 = or(_T_17888, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17890 = and(_T_17886, _T_17889) @[ifu_bp_ctl.scala 442:110] - node _T_17891 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17892 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17893 = eq(_T_17892, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_17894 = and(_T_17891, _T_17893) @[ifu_bp_ctl.scala 443:22] - node _T_17895 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17896 = eq(_T_17895, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_17897 = or(_T_17896, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17898 = and(_T_17894, _T_17897) @[ifu_bp_ctl.scala 443:87] - node _T_17899 = or(_T_17890, _T_17898) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][8][11] <= _T_17899 @[ifu_bp_ctl.scala 442:27] - node _T_17900 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17901 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17902 = eq(_T_17901, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_17903 = and(_T_17900, _T_17902) @[ifu_bp_ctl.scala 442:45] - node _T_17904 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17905 = eq(_T_17904, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_17906 = or(_T_17905, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17907 = and(_T_17903, _T_17906) @[ifu_bp_ctl.scala 442:110] - node _T_17908 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17909 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17910 = eq(_T_17909, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_17911 = and(_T_17908, _T_17910) @[ifu_bp_ctl.scala 443:22] - node _T_17912 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17913 = eq(_T_17912, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_17914 = or(_T_17913, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17915 = and(_T_17911, _T_17914) @[ifu_bp_ctl.scala 443:87] - node _T_17916 = or(_T_17907, _T_17915) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][8][12] <= _T_17916 @[ifu_bp_ctl.scala 442:27] - node _T_17917 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17918 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17919 = eq(_T_17918, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_17920 = and(_T_17917, _T_17919) @[ifu_bp_ctl.scala 442:45] - node _T_17921 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17922 = eq(_T_17921, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_17923 = or(_T_17922, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17924 = and(_T_17920, _T_17923) @[ifu_bp_ctl.scala 442:110] - node _T_17925 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17926 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17927 = eq(_T_17926, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_17928 = and(_T_17925, _T_17927) @[ifu_bp_ctl.scala 443:22] - node _T_17929 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17930 = eq(_T_17929, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_17931 = or(_T_17930, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17932 = and(_T_17928, _T_17931) @[ifu_bp_ctl.scala 443:87] - node _T_17933 = or(_T_17924, _T_17932) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][8][13] <= _T_17933 @[ifu_bp_ctl.scala 442:27] - node _T_17934 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17935 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17936 = eq(_T_17935, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_17937 = and(_T_17934, _T_17936) @[ifu_bp_ctl.scala 442:45] - node _T_17938 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17939 = eq(_T_17938, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_17940 = or(_T_17939, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17941 = and(_T_17937, _T_17940) @[ifu_bp_ctl.scala 442:110] - node _T_17942 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17943 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17944 = eq(_T_17943, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_17945 = and(_T_17942, _T_17944) @[ifu_bp_ctl.scala 443:22] - node _T_17946 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17947 = eq(_T_17946, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_17948 = or(_T_17947, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17949 = and(_T_17945, _T_17948) @[ifu_bp_ctl.scala 443:87] - node _T_17950 = or(_T_17941, _T_17949) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][8][14] <= _T_17950 @[ifu_bp_ctl.scala 442:27] - node _T_17951 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17952 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17953 = eq(_T_17952, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_17954 = and(_T_17951, _T_17953) @[ifu_bp_ctl.scala 442:45] - node _T_17955 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17956 = eq(_T_17955, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:186] - node _T_17957 = or(_T_17956, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17958 = and(_T_17954, _T_17957) @[ifu_bp_ctl.scala 442:110] - node _T_17959 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17960 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17961 = eq(_T_17960, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_17962 = and(_T_17959, _T_17961) @[ifu_bp_ctl.scala 443:22] - node _T_17963 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17964 = eq(_T_17963, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:163] - node _T_17965 = or(_T_17964, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17966 = and(_T_17962, _T_17965) @[ifu_bp_ctl.scala 443:87] - node _T_17967 = or(_T_17958, _T_17966) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][8][15] <= _T_17967 @[ifu_bp_ctl.scala 442:27] - node _T_17968 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17969 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17970 = eq(_T_17969, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_17971 = and(_T_17968, _T_17970) @[ifu_bp_ctl.scala 442:45] - node _T_17972 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17973 = eq(_T_17972, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_17974 = or(_T_17973, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17975 = and(_T_17971, _T_17974) @[ifu_bp_ctl.scala 442:110] - node _T_17976 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17977 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17978 = eq(_T_17977, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_17979 = and(_T_17976, _T_17978) @[ifu_bp_ctl.scala 443:22] - node _T_17980 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17981 = eq(_T_17980, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_17982 = or(_T_17981, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_17983 = and(_T_17979, _T_17982) @[ifu_bp_ctl.scala 443:87] - node _T_17984 = or(_T_17975, _T_17983) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][9][0] <= _T_17984 @[ifu_bp_ctl.scala 442:27] - node _T_17985 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_17986 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_17987 = eq(_T_17986, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_17988 = and(_T_17985, _T_17987) @[ifu_bp_ctl.scala 442:45] - node _T_17989 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_17990 = eq(_T_17989, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_17991 = or(_T_17990, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_17992 = and(_T_17988, _T_17991) @[ifu_bp_ctl.scala 442:110] - node _T_17993 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_17994 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_17995 = eq(_T_17994, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_17996 = and(_T_17993, _T_17995) @[ifu_bp_ctl.scala 443:22] - node _T_17997 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_17998 = eq(_T_17997, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_17999 = or(_T_17998, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18000 = and(_T_17996, _T_17999) @[ifu_bp_ctl.scala 443:87] - node _T_18001 = or(_T_17992, _T_18000) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][9][1] <= _T_18001 @[ifu_bp_ctl.scala 442:27] - node _T_18002 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18003 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18004 = eq(_T_18003, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_18005 = and(_T_18002, _T_18004) @[ifu_bp_ctl.scala 442:45] - node _T_18006 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18007 = eq(_T_18006, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_18008 = or(_T_18007, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18009 = and(_T_18005, _T_18008) @[ifu_bp_ctl.scala 442:110] - node _T_18010 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18011 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18012 = eq(_T_18011, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_18013 = and(_T_18010, _T_18012) @[ifu_bp_ctl.scala 443:22] - node _T_18014 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18015 = eq(_T_18014, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_18016 = or(_T_18015, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18017 = and(_T_18013, _T_18016) @[ifu_bp_ctl.scala 443:87] - node _T_18018 = or(_T_18009, _T_18017) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][9][2] <= _T_18018 @[ifu_bp_ctl.scala 442:27] - node _T_18019 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18020 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18021 = eq(_T_18020, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_18022 = and(_T_18019, _T_18021) @[ifu_bp_ctl.scala 442:45] - node _T_18023 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18024 = eq(_T_18023, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_18025 = or(_T_18024, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18026 = and(_T_18022, _T_18025) @[ifu_bp_ctl.scala 442:110] - node _T_18027 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18028 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18029 = eq(_T_18028, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_18030 = and(_T_18027, _T_18029) @[ifu_bp_ctl.scala 443:22] - node _T_18031 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18032 = eq(_T_18031, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_18033 = or(_T_18032, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18034 = and(_T_18030, _T_18033) @[ifu_bp_ctl.scala 443:87] - node _T_18035 = or(_T_18026, _T_18034) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][9][3] <= _T_18035 @[ifu_bp_ctl.scala 442:27] - node _T_18036 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18037 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18038 = eq(_T_18037, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_18039 = and(_T_18036, _T_18038) @[ifu_bp_ctl.scala 442:45] - node _T_18040 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18041 = eq(_T_18040, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_18042 = or(_T_18041, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18043 = and(_T_18039, _T_18042) @[ifu_bp_ctl.scala 442:110] - node _T_18044 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18045 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18046 = eq(_T_18045, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_18047 = and(_T_18044, _T_18046) @[ifu_bp_ctl.scala 443:22] - node _T_18048 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18049 = eq(_T_18048, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_18050 = or(_T_18049, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18051 = and(_T_18047, _T_18050) @[ifu_bp_ctl.scala 443:87] - node _T_18052 = or(_T_18043, _T_18051) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][9][4] <= _T_18052 @[ifu_bp_ctl.scala 442:27] - node _T_18053 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18054 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18055 = eq(_T_18054, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_18056 = and(_T_18053, _T_18055) @[ifu_bp_ctl.scala 442:45] - node _T_18057 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18058 = eq(_T_18057, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_18059 = or(_T_18058, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18060 = and(_T_18056, _T_18059) @[ifu_bp_ctl.scala 442:110] - node _T_18061 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18062 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18063 = eq(_T_18062, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_18064 = and(_T_18061, _T_18063) @[ifu_bp_ctl.scala 443:22] - node _T_18065 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18066 = eq(_T_18065, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_18067 = or(_T_18066, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18068 = and(_T_18064, _T_18067) @[ifu_bp_ctl.scala 443:87] - node _T_18069 = or(_T_18060, _T_18068) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][9][5] <= _T_18069 @[ifu_bp_ctl.scala 442:27] - node _T_18070 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18071 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18072 = eq(_T_18071, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_18073 = and(_T_18070, _T_18072) @[ifu_bp_ctl.scala 442:45] - node _T_18074 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18075 = eq(_T_18074, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_18076 = or(_T_18075, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18077 = and(_T_18073, _T_18076) @[ifu_bp_ctl.scala 442:110] - node _T_18078 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18079 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18080 = eq(_T_18079, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_18081 = and(_T_18078, _T_18080) @[ifu_bp_ctl.scala 443:22] - node _T_18082 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18083 = eq(_T_18082, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_18084 = or(_T_18083, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18085 = and(_T_18081, _T_18084) @[ifu_bp_ctl.scala 443:87] - node _T_18086 = or(_T_18077, _T_18085) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][9][6] <= _T_18086 @[ifu_bp_ctl.scala 442:27] - node _T_18087 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18088 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18089 = eq(_T_18088, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_18090 = and(_T_18087, _T_18089) @[ifu_bp_ctl.scala 442:45] - node _T_18091 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18092 = eq(_T_18091, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_18093 = or(_T_18092, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18094 = and(_T_18090, _T_18093) @[ifu_bp_ctl.scala 442:110] - node _T_18095 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18096 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18097 = eq(_T_18096, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_18098 = and(_T_18095, _T_18097) @[ifu_bp_ctl.scala 443:22] - node _T_18099 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18100 = eq(_T_18099, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_18101 = or(_T_18100, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18102 = and(_T_18098, _T_18101) @[ifu_bp_ctl.scala 443:87] - node _T_18103 = or(_T_18094, _T_18102) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][9][7] <= _T_18103 @[ifu_bp_ctl.scala 442:27] - node _T_18104 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18105 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18106 = eq(_T_18105, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_18107 = and(_T_18104, _T_18106) @[ifu_bp_ctl.scala 442:45] - node _T_18108 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18109 = eq(_T_18108, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_18110 = or(_T_18109, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18111 = and(_T_18107, _T_18110) @[ifu_bp_ctl.scala 442:110] - node _T_18112 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18113 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18114 = eq(_T_18113, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_18115 = and(_T_18112, _T_18114) @[ifu_bp_ctl.scala 443:22] - node _T_18116 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18117 = eq(_T_18116, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_18118 = or(_T_18117, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18119 = and(_T_18115, _T_18118) @[ifu_bp_ctl.scala 443:87] - node _T_18120 = or(_T_18111, _T_18119) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][9][8] <= _T_18120 @[ifu_bp_ctl.scala 442:27] - node _T_18121 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18122 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18123 = eq(_T_18122, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_18124 = and(_T_18121, _T_18123) @[ifu_bp_ctl.scala 442:45] - node _T_18125 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18126 = eq(_T_18125, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_18127 = or(_T_18126, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18128 = and(_T_18124, _T_18127) @[ifu_bp_ctl.scala 442:110] - node _T_18129 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18130 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18131 = eq(_T_18130, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_18132 = and(_T_18129, _T_18131) @[ifu_bp_ctl.scala 443:22] - node _T_18133 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18134 = eq(_T_18133, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_18135 = or(_T_18134, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18136 = and(_T_18132, _T_18135) @[ifu_bp_ctl.scala 443:87] - node _T_18137 = or(_T_18128, _T_18136) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][9][9] <= _T_18137 @[ifu_bp_ctl.scala 442:27] - node _T_18138 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18139 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18140 = eq(_T_18139, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_18141 = and(_T_18138, _T_18140) @[ifu_bp_ctl.scala 442:45] - node _T_18142 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18143 = eq(_T_18142, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_18144 = or(_T_18143, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18145 = and(_T_18141, _T_18144) @[ifu_bp_ctl.scala 442:110] - node _T_18146 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18147 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18148 = eq(_T_18147, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_18149 = and(_T_18146, _T_18148) @[ifu_bp_ctl.scala 443:22] - node _T_18150 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18151 = eq(_T_18150, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_18152 = or(_T_18151, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18153 = and(_T_18149, _T_18152) @[ifu_bp_ctl.scala 443:87] - node _T_18154 = or(_T_18145, _T_18153) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][9][10] <= _T_18154 @[ifu_bp_ctl.scala 442:27] - node _T_18155 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18156 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18157 = eq(_T_18156, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_18158 = and(_T_18155, _T_18157) @[ifu_bp_ctl.scala 442:45] - node _T_18159 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18160 = eq(_T_18159, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_18161 = or(_T_18160, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18162 = and(_T_18158, _T_18161) @[ifu_bp_ctl.scala 442:110] - node _T_18163 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18164 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18165 = eq(_T_18164, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_18166 = and(_T_18163, _T_18165) @[ifu_bp_ctl.scala 443:22] - node _T_18167 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18168 = eq(_T_18167, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_18169 = or(_T_18168, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18170 = and(_T_18166, _T_18169) @[ifu_bp_ctl.scala 443:87] - node _T_18171 = or(_T_18162, _T_18170) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][9][11] <= _T_18171 @[ifu_bp_ctl.scala 442:27] - node _T_18172 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18173 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18174 = eq(_T_18173, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_18175 = and(_T_18172, _T_18174) @[ifu_bp_ctl.scala 442:45] - node _T_18176 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18177 = eq(_T_18176, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_18178 = or(_T_18177, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18179 = and(_T_18175, _T_18178) @[ifu_bp_ctl.scala 442:110] - node _T_18180 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18181 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18182 = eq(_T_18181, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_18183 = and(_T_18180, _T_18182) @[ifu_bp_ctl.scala 443:22] - node _T_18184 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18185 = eq(_T_18184, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_18186 = or(_T_18185, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18187 = and(_T_18183, _T_18186) @[ifu_bp_ctl.scala 443:87] - node _T_18188 = or(_T_18179, _T_18187) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][9][12] <= _T_18188 @[ifu_bp_ctl.scala 442:27] - node _T_18189 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18190 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18191 = eq(_T_18190, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_18192 = and(_T_18189, _T_18191) @[ifu_bp_ctl.scala 442:45] - node _T_18193 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18194 = eq(_T_18193, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_18195 = or(_T_18194, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18196 = and(_T_18192, _T_18195) @[ifu_bp_ctl.scala 442:110] - node _T_18197 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18198 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18199 = eq(_T_18198, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_18200 = and(_T_18197, _T_18199) @[ifu_bp_ctl.scala 443:22] - node _T_18201 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18202 = eq(_T_18201, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_18203 = or(_T_18202, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18204 = and(_T_18200, _T_18203) @[ifu_bp_ctl.scala 443:87] - node _T_18205 = or(_T_18196, _T_18204) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][9][13] <= _T_18205 @[ifu_bp_ctl.scala 442:27] - node _T_18206 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18207 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18208 = eq(_T_18207, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_18209 = and(_T_18206, _T_18208) @[ifu_bp_ctl.scala 442:45] - node _T_18210 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18211 = eq(_T_18210, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_18212 = or(_T_18211, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18213 = and(_T_18209, _T_18212) @[ifu_bp_ctl.scala 442:110] - node _T_18214 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18215 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18216 = eq(_T_18215, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_18217 = and(_T_18214, _T_18216) @[ifu_bp_ctl.scala 443:22] - node _T_18218 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18219 = eq(_T_18218, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_18220 = or(_T_18219, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18221 = and(_T_18217, _T_18220) @[ifu_bp_ctl.scala 443:87] - node _T_18222 = or(_T_18213, _T_18221) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][9][14] <= _T_18222 @[ifu_bp_ctl.scala 442:27] - node _T_18223 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18224 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18225 = eq(_T_18224, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_18226 = and(_T_18223, _T_18225) @[ifu_bp_ctl.scala 442:45] - node _T_18227 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18228 = eq(_T_18227, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:186] - node _T_18229 = or(_T_18228, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18230 = and(_T_18226, _T_18229) @[ifu_bp_ctl.scala 442:110] - node _T_18231 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18232 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18233 = eq(_T_18232, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_18234 = and(_T_18231, _T_18233) @[ifu_bp_ctl.scala 443:22] - node _T_18235 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18236 = eq(_T_18235, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:163] - node _T_18237 = or(_T_18236, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18238 = and(_T_18234, _T_18237) @[ifu_bp_ctl.scala 443:87] - node _T_18239 = or(_T_18230, _T_18238) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][9][15] <= _T_18239 @[ifu_bp_ctl.scala 442:27] - node _T_18240 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18241 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18242 = eq(_T_18241, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_18243 = and(_T_18240, _T_18242) @[ifu_bp_ctl.scala 442:45] - node _T_18244 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18245 = eq(_T_18244, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_18246 = or(_T_18245, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18247 = and(_T_18243, _T_18246) @[ifu_bp_ctl.scala 442:110] - node _T_18248 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18249 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18250 = eq(_T_18249, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_18251 = and(_T_18248, _T_18250) @[ifu_bp_ctl.scala 443:22] - node _T_18252 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18253 = eq(_T_18252, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_18254 = or(_T_18253, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18255 = and(_T_18251, _T_18254) @[ifu_bp_ctl.scala 443:87] - node _T_18256 = or(_T_18247, _T_18255) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][10][0] <= _T_18256 @[ifu_bp_ctl.scala 442:27] - node _T_18257 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18258 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18259 = eq(_T_18258, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_18260 = and(_T_18257, _T_18259) @[ifu_bp_ctl.scala 442:45] - node _T_18261 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18262 = eq(_T_18261, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_18263 = or(_T_18262, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18264 = and(_T_18260, _T_18263) @[ifu_bp_ctl.scala 442:110] - node _T_18265 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18266 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18267 = eq(_T_18266, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_18268 = and(_T_18265, _T_18267) @[ifu_bp_ctl.scala 443:22] - node _T_18269 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18270 = eq(_T_18269, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_18271 = or(_T_18270, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18272 = and(_T_18268, _T_18271) @[ifu_bp_ctl.scala 443:87] - node _T_18273 = or(_T_18264, _T_18272) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][10][1] <= _T_18273 @[ifu_bp_ctl.scala 442:27] - node _T_18274 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18275 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18276 = eq(_T_18275, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_18277 = and(_T_18274, _T_18276) @[ifu_bp_ctl.scala 442:45] - node _T_18278 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18279 = eq(_T_18278, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_18280 = or(_T_18279, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18281 = and(_T_18277, _T_18280) @[ifu_bp_ctl.scala 442:110] - node _T_18282 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18283 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18284 = eq(_T_18283, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_18285 = and(_T_18282, _T_18284) @[ifu_bp_ctl.scala 443:22] - node _T_18286 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18287 = eq(_T_18286, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_18288 = or(_T_18287, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18289 = and(_T_18285, _T_18288) @[ifu_bp_ctl.scala 443:87] - node _T_18290 = or(_T_18281, _T_18289) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][10][2] <= _T_18290 @[ifu_bp_ctl.scala 442:27] - node _T_18291 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18292 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18293 = eq(_T_18292, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_18294 = and(_T_18291, _T_18293) @[ifu_bp_ctl.scala 442:45] - node _T_18295 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18296 = eq(_T_18295, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_18297 = or(_T_18296, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18298 = and(_T_18294, _T_18297) @[ifu_bp_ctl.scala 442:110] - node _T_18299 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18300 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18301 = eq(_T_18300, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_18302 = and(_T_18299, _T_18301) @[ifu_bp_ctl.scala 443:22] - node _T_18303 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18304 = eq(_T_18303, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_18305 = or(_T_18304, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18306 = and(_T_18302, _T_18305) @[ifu_bp_ctl.scala 443:87] - node _T_18307 = or(_T_18298, _T_18306) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][10][3] <= _T_18307 @[ifu_bp_ctl.scala 442:27] - node _T_18308 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18309 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18310 = eq(_T_18309, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_18311 = and(_T_18308, _T_18310) @[ifu_bp_ctl.scala 442:45] - node _T_18312 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18313 = eq(_T_18312, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_18314 = or(_T_18313, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18315 = and(_T_18311, _T_18314) @[ifu_bp_ctl.scala 442:110] - node _T_18316 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18317 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18318 = eq(_T_18317, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_18319 = and(_T_18316, _T_18318) @[ifu_bp_ctl.scala 443:22] - node _T_18320 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18321 = eq(_T_18320, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_18322 = or(_T_18321, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18323 = and(_T_18319, _T_18322) @[ifu_bp_ctl.scala 443:87] - node _T_18324 = or(_T_18315, _T_18323) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][10][4] <= _T_18324 @[ifu_bp_ctl.scala 442:27] - node _T_18325 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18326 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18327 = eq(_T_18326, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_18328 = and(_T_18325, _T_18327) @[ifu_bp_ctl.scala 442:45] - node _T_18329 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18330 = eq(_T_18329, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_18331 = or(_T_18330, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18332 = and(_T_18328, _T_18331) @[ifu_bp_ctl.scala 442:110] - node _T_18333 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18334 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18335 = eq(_T_18334, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_18336 = and(_T_18333, _T_18335) @[ifu_bp_ctl.scala 443:22] - node _T_18337 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18338 = eq(_T_18337, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_18339 = or(_T_18338, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18340 = and(_T_18336, _T_18339) @[ifu_bp_ctl.scala 443:87] - node _T_18341 = or(_T_18332, _T_18340) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][10][5] <= _T_18341 @[ifu_bp_ctl.scala 442:27] - node _T_18342 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18343 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18344 = eq(_T_18343, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_18345 = and(_T_18342, _T_18344) @[ifu_bp_ctl.scala 442:45] - node _T_18346 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18347 = eq(_T_18346, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_18348 = or(_T_18347, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18349 = and(_T_18345, _T_18348) @[ifu_bp_ctl.scala 442:110] - node _T_18350 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18351 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18352 = eq(_T_18351, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_18353 = and(_T_18350, _T_18352) @[ifu_bp_ctl.scala 443:22] - node _T_18354 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18355 = eq(_T_18354, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_18356 = or(_T_18355, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18357 = and(_T_18353, _T_18356) @[ifu_bp_ctl.scala 443:87] - node _T_18358 = or(_T_18349, _T_18357) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][10][6] <= _T_18358 @[ifu_bp_ctl.scala 442:27] - node _T_18359 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18360 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18361 = eq(_T_18360, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_18362 = and(_T_18359, _T_18361) @[ifu_bp_ctl.scala 442:45] - node _T_18363 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18364 = eq(_T_18363, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_18365 = or(_T_18364, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18366 = and(_T_18362, _T_18365) @[ifu_bp_ctl.scala 442:110] - node _T_18367 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18368 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18369 = eq(_T_18368, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_18370 = and(_T_18367, _T_18369) @[ifu_bp_ctl.scala 443:22] - node _T_18371 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18372 = eq(_T_18371, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_18373 = or(_T_18372, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18374 = and(_T_18370, _T_18373) @[ifu_bp_ctl.scala 443:87] - node _T_18375 = or(_T_18366, _T_18374) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][10][7] <= _T_18375 @[ifu_bp_ctl.scala 442:27] - node _T_18376 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18377 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18378 = eq(_T_18377, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_18379 = and(_T_18376, _T_18378) @[ifu_bp_ctl.scala 442:45] - node _T_18380 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18381 = eq(_T_18380, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_18382 = or(_T_18381, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18383 = and(_T_18379, _T_18382) @[ifu_bp_ctl.scala 442:110] - node _T_18384 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18385 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18386 = eq(_T_18385, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_18387 = and(_T_18384, _T_18386) @[ifu_bp_ctl.scala 443:22] - node _T_18388 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18389 = eq(_T_18388, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_18390 = or(_T_18389, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18391 = and(_T_18387, _T_18390) @[ifu_bp_ctl.scala 443:87] - node _T_18392 = or(_T_18383, _T_18391) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][10][8] <= _T_18392 @[ifu_bp_ctl.scala 442:27] - node _T_18393 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18394 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18395 = eq(_T_18394, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_18396 = and(_T_18393, _T_18395) @[ifu_bp_ctl.scala 442:45] - node _T_18397 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18398 = eq(_T_18397, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_18399 = or(_T_18398, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18400 = and(_T_18396, _T_18399) @[ifu_bp_ctl.scala 442:110] - node _T_18401 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18402 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18403 = eq(_T_18402, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_18404 = and(_T_18401, _T_18403) @[ifu_bp_ctl.scala 443:22] - node _T_18405 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18406 = eq(_T_18405, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_18407 = or(_T_18406, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18408 = and(_T_18404, _T_18407) @[ifu_bp_ctl.scala 443:87] - node _T_18409 = or(_T_18400, _T_18408) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][10][9] <= _T_18409 @[ifu_bp_ctl.scala 442:27] - node _T_18410 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18411 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18412 = eq(_T_18411, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_18413 = and(_T_18410, _T_18412) @[ifu_bp_ctl.scala 442:45] - node _T_18414 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18415 = eq(_T_18414, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_18416 = or(_T_18415, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18417 = and(_T_18413, _T_18416) @[ifu_bp_ctl.scala 442:110] - node _T_18418 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18419 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18420 = eq(_T_18419, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_18421 = and(_T_18418, _T_18420) @[ifu_bp_ctl.scala 443:22] - node _T_18422 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18423 = eq(_T_18422, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_18424 = or(_T_18423, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18425 = and(_T_18421, _T_18424) @[ifu_bp_ctl.scala 443:87] - node _T_18426 = or(_T_18417, _T_18425) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][10][10] <= _T_18426 @[ifu_bp_ctl.scala 442:27] - node _T_18427 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18428 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18429 = eq(_T_18428, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_18430 = and(_T_18427, _T_18429) @[ifu_bp_ctl.scala 442:45] - node _T_18431 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18432 = eq(_T_18431, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_18433 = or(_T_18432, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18434 = and(_T_18430, _T_18433) @[ifu_bp_ctl.scala 442:110] - node _T_18435 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18436 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18437 = eq(_T_18436, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_18438 = and(_T_18435, _T_18437) @[ifu_bp_ctl.scala 443:22] - node _T_18439 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18440 = eq(_T_18439, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_18441 = or(_T_18440, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18442 = and(_T_18438, _T_18441) @[ifu_bp_ctl.scala 443:87] - node _T_18443 = or(_T_18434, _T_18442) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][10][11] <= _T_18443 @[ifu_bp_ctl.scala 442:27] - node _T_18444 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18445 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18446 = eq(_T_18445, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_18447 = and(_T_18444, _T_18446) @[ifu_bp_ctl.scala 442:45] - node _T_18448 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18449 = eq(_T_18448, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_18450 = or(_T_18449, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18451 = and(_T_18447, _T_18450) @[ifu_bp_ctl.scala 442:110] - node _T_18452 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18453 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18454 = eq(_T_18453, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_18455 = and(_T_18452, _T_18454) @[ifu_bp_ctl.scala 443:22] - node _T_18456 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18457 = eq(_T_18456, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_18458 = or(_T_18457, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18459 = and(_T_18455, _T_18458) @[ifu_bp_ctl.scala 443:87] - node _T_18460 = or(_T_18451, _T_18459) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][10][12] <= _T_18460 @[ifu_bp_ctl.scala 442:27] - node _T_18461 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18462 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18463 = eq(_T_18462, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_18464 = and(_T_18461, _T_18463) @[ifu_bp_ctl.scala 442:45] - node _T_18465 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18466 = eq(_T_18465, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_18467 = or(_T_18466, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18468 = and(_T_18464, _T_18467) @[ifu_bp_ctl.scala 442:110] - node _T_18469 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18470 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18471 = eq(_T_18470, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_18472 = and(_T_18469, _T_18471) @[ifu_bp_ctl.scala 443:22] - node _T_18473 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18474 = eq(_T_18473, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_18475 = or(_T_18474, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18476 = and(_T_18472, _T_18475) @[ifu_bp_ctl.scala 443:87] - node _T_18477 = or(_T_18468, _T_18476) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][10][13] <= _T_18477 @[ifu_bp_ctl.scala 442:27] - node _T_18478 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18479 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18480 = eq(_T_18479, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_18481 = and(_T_18478, _T_18480) @[ifu_bp_ctl.scala 442:45] - node _T_18482 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18483 = eq(_T_18482, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_18484 = or(_T_18483, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18485 = and(_T_18481, _T_18484) @[ifu_bp_ctl.scala 442:110] - node _T_18486 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18487 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18488 = eq(_T_18487, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_18489 = and(_T_18486, _T_18488) @[ifu_bp_ctl.scala 443:22] - node _T_18490 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18491 = eq(_T_18490, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_18492 = or(_T_18491, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18493 = and(_T_18489, _T_18492) @[ifu_bp_ctl.scala 443:87] - node _T_18494 = or(_T_18485, _T_18493) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][10][14] <= _T_18494 @[ifu_bp_ctl.scala 442:27] - node _T_18495 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18496 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18497 = eq(_T_18496, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_18498 = and(_T_18495, _T_18497) @[ifu_bp_ctl.scala 442:45] - node _T_18499 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18500 = eq(_T_18499, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:186] - node _T_18501 = or(_T_18500, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18502 = and(_T_18498, _T_18501) @[ifu_bp_ctl.scala 442:110] - node _T_18503 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18504 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18505 = eq(_T_18504, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_18506 = and(_T_18503, _T_18505) @[ifu_bp_ctl.scala 443:22] - node _T_18507 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18508 = eq(_T_18507, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:163] - node _T_18509 = or(_T_18508, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18510 = and(_T_18506, _T_18509) @[ifu_bp_ctl.scala 443:87] - node _T_18511 = or(_T_18502, _T_18510) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][10][15] <= _T_18511 @[ifu_bp_ctl.scala 442:27] - node _T_18512 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18513 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18514 = eq(_T_18513, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_18515 = and(_T_18512, _T_18514) @[ifu_bp_ctl.scala 442:45] - node _T_18516 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18517 = eq(_T_18516, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_18518 = or(_T_18517, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18519 = and(_T_18515, _T_18518) @[ifu_bp_ctl.scala 442:110] - node _T_18520 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18521 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18522 = eq(_T_18521, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_18523 = and(_T_18520, _T_18522) @[ifu_bp_ctl.scala 443:22] - node _T_18524 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18525 = eq(_T_18524, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_18526 = or(_T_18525, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18527 = and(_T_18523, _T_18526) @[ifu_bp_ctl.scala 443:87] - node _T_18528 = or(_T_18519, _T_18527) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][11][0] <= _T_18528 @[ifu_bp_ctl.scala 442:27] - node _T_18529 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18530 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18531 = eq(_T_18530, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_18532 = and(_T_18529, _T_18531) @[ifu_bp_ctl.scala 442:45] - node _T_18533 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18534 = eq(_T_18533, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_18535 = or(_T_18534, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18536 = and(_T_18532, _T_18535) @[ifu_bp_ctl.scala 442:110] - node _T_18537 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18538 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18539 = eq(_T_18538, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_18540 = and(_T_18537, _T_18539) @[ifu_bp_ctl.scala 443:22] - node _T_18541 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18542 = eq(_T_18541, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_18543 = or(_T_18542, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18544 = and(_T_18540, _T_18543) @[ifu_bp_ctl.scala 443:87] - node _T_18545 = or(_T_18536, _T_18544) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][11][1] <= _T_18545 @[ifu_bp_ctl.scala 442:27] - node _T_18546 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18547 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18548 = eq(_T_18547, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_18549 = and(_T_18546, _T_18548) @[ifu_bp_ctl.scala 442:45] - node _T_18550 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18551 = eq(_T_18550, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_18552 = or(_T_18551, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18553 = and(_T_18549, _T_18552) @[ifu_bp_ctl.scala 442:110] - node _T_18554 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18555 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18556 = eq(_T_18555, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_18557 = and(_T_18554, _T_18556) @[ifu_bp_ctl.scala 443:22] - node _T_18558 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18559 = eq(_T_18558, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_18560 = or(_T_18559, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18561 = and(_T_18557, _T_18560) @[ifu_bp_ctl.scala 443:87] - node _T_18562 = or(_T_18553, _T_18561) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][11][2] <= _T_18562 @[ifu_bp_ctl.scala 442:27] - node _T_18563 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18564 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18565 = eq(_T_18564, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_18566 = and(_T_18563, _T_18565) @[ifu_bp_ctl.scala 442:45] - node _T_18567 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18568 = eq(_T_18567, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_18569 = or(_T_18568, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18570 = and(_T_18566, _T_18569) @[ifu_bp_ctl.scala 442:110] - node _T_18571 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18572 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18573 = eq(_T_18572, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_18574 = and(_T_18571, _T_18573) @[ifu_bp_ctl.scala 443:22] - node _T_18575 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18576 = eq(_T_18575, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_18577 = or(_T_18576, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18578 = and(_T_18574, _T_18577) @[ifu_bp_ctl.scala 443:87] - node _T_18579 = or(_T_18570, _T_18578) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][11][3] <= _T_18579 @[ifu_bp_ctl.scala 442:27] - node _T_18580 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18581 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18582 = eq(_T_18581, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_18583 = and(_T_18580, _T_18582) @[ifu_bp_ctl.scala 442:45] - node _T_18584 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18585 = eq(_T_18584, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_18586 = or(_T_18585, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18587 = and(_T_18583, _T_18586) @[ifu_bp_ctl.scala 442:110] - node _T_18588 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18589 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18590 = eq(_T_18589, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_18591 = and(_T_18588, _T_18590) @[ifu_bp_ctl.scala 443:22] - node _T_18592 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18593 = eq(_T_18592, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_18594 = or(_T_18593, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18595 = and(_T_18591, _T_18594) @[ifu_bp_ctl.scala 443:87] - node _T_18596 = or(_T_18587, _T_18595) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][11][4] <= _T_18596 @[ifu_bp_ctl.scala 442:27] - node _T_18597 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18598 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18599 = eq(_T_18598, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_18600 = and(_T_18597, _T_18599) @[ifu_bp_ctl.scala 442:45] - node _T_18601 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18602 = eq(_T_18601, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_18603 = or(_T_18602, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18604 = and(_T_18600, _T_18603) @[ifu_bp_ctl.scala 442:110] - node _T_18605 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18606 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18607 = eq(_T_18606, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_18608 = and(_T_18605, _T_18607) @[ifu_bp_ctl.scala 443:22] - node _T_18609 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18610 = eq(_T_18609, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_18611 = or(_T_18610, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18612 = and(_T_18608, _T_18611) @[ifu_bp_ctl.scala 443:87] - node _T_18613 = or(_T_18604, _T_18612) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][11][5] <= _T_18613 @[ifu_bp_ctl.scala 442:27] - node _T_18614 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18615 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18616 = eq(_T_18615, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_18617 = and(_T_18614, _T_18616) @[ifu_bp_ctl.scala 442:45] - node _T_18618 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18619 = eq(_T_18618, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_18620 = or(_T_18619, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18621 = and(_T_18617, _T_18620) @[ifu_bp_ctl.scala 442:110] - node _T_18622 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18623 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18624 = eq(_T_18623, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_18625 = and(_T_18622, _T_18624) @[ifu_bp_ctl.scala 443:22] - node _T_18626 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18627 = eq(_T_18626, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_18628 = or(_T_18627, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18629 = and(_T_18625, _T_18628) @[ifu_bp_ctl.scala 443:87] - node _T_18630 = or(_T_18621, _T_18629) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][11][6] <= _T_18630 @[ifu_bp_ctl.scala 442:27] - node _T_18631 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18632 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18633 = eq(_T_18632, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_18634 = and(_T_18631, _T_18633) @[ifu_bp_ctl.scala 442:45] - node _T_18635 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18636 = eq(_T_18635, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_18637 = or(_T_18636, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18638 = and(_T_18634, _T_18637) @[ifu_bp_ctl.scala 442:110] - node _T_18639 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18640 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18641 = eq(_T_18640, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_18642 = and(_T_18639, _T_18641) @[ifu_bp_ctl.scala 443:22] - node _T_18643 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18644 = eq(_T_18643, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_18645 = or(_T_18644, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18646 = and(_T_18642, _T_18645) @[ifu_bp_ctl.scala 443:87] - node _T_18647 = or(_T_18638, _T_18646) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][11][7] <= _T_18647 @[ifu_bp_ctl.scala 442:27] - node _T_18648 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18649 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18650 = eq(_T_18649, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_18651 = and(_T_18648, _T_18650) @[ifu_bp_ctl.scala 442:45] - node _T_18652 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18653 = eq(_T_18652, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_18654 = or(_T_18653, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18655 = and(_T_18651, _T_18654) @[ifu_bp_ctl.scala 442:110] - node _T_18656 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18657 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18658 = eq(_T_18657, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_18659 = and(_T_18656, _T_18658) @[ifu_bp_ctl.scala 443:22] - node _T_18660 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18661 = eq(_T_18660, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_18662 = or(_T_18661, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18663 = and(_T_18659, _T_18662) @[ifu_bp_ctl.scala 443:87] - node _T_18664 = or(_T_18655, _T_18663) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][11][8] <= _T_18664 @[ifu_bp_ctl.scala 442:27] - node _T_18665 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18666 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18667 = eq(_T_18666, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_18668 = and(_T_18665, _T_18667) @[ifu_bp_ctl.scala 442:45] - node _T_18669 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18670 = eq(_T_18669, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_18671 = or(_T_18670, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18672 = and(_T_18668, _T_18671) @[ifu_bp_ctl.scala 442:110] - node _T_18673 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18674 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18675 = eq(_T_18674, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_18676 = and(_T_18673, _T_18675) @[ifu_bp_ctl.scala 443:22] - node _T_18677 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18678 = eq(_T_18677, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_18679 = or(_T_18678, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18680 = and(_T_18676, _T_18679) @[ifu_bp_ctl.scala 443:87] - node _T_18681 = or(_T_18672, _T_18680) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][11][9] <= _T_18681 @[ifu_bp_ctl.scala 442:27] - node _T_18682 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18683 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18684 = eq(_T_18683, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_18685 = and(_T_18682, _T_18684) @[ifu_bp_ctl.scala 442:45] - node _T_18686 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18687 = eq(_T_18686, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_18688 = or(_T_18687, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18689 = and(_T_18685, _T_18688) @[ifu_bp_ctl.scala 442:110] - node _T_18690 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18691 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18692 = eq(_T_18691, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_18693 = and(_T_18690, _T_18692) @[ifu_bp_ctl.scala 443:22] - node _T_18694 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18695 = eq(_T_18694, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_18696 = or(_T_18695, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18697 = and(_T_18693, _T_18696) @[ifu_bp_ctl.scala 443:87] - node _T_18698 = or(_T_18689, _T_18697) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][11][10] <= _T_18698 @[ifu_bp_ctl.scala 442:27] - node _T_18699 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18700 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18701 = eq(_T_18700, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_18702 = and(_T_18699, _T_18701) @[ifu_bp_ctl.scala 442:45] - node _T_18703 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18704 = eq(_T_18703, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_18705 = or(_T_18704, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18706 = and(_T_18702, _T_18705) @[ifu_bp_ctl.scala 442:110] - node _T_18707 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18708 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18709 = eq(_T_18708, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_18710 = and(_T_18707, _T_18709) @[ifu_bp_ctl.scala 443:22] - node _T_18711 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18712 = eq(_T_18711, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_18713 = or(_T_18712, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18714 = and(_T_18710, _T_18713) @[ifu_bp_ctl.scala 443:87] - node _T_18715 = or(_T_18706, _T_18714) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][11][11] <= _T_18715 @[ifu_bp_ctl.scala 442:27] - node _T_18716 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18717 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18718 = eq(_T_18717, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_18719 = and(_T_18716, _T_18718) @[ifu_bp_ctl.scala 442:45] - node _T_18720 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18721 = eq(_T_18720, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_18722 = or(_T_18721, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18723 = and(_T_18719, _T_18722) @[ifu_bp_ctl.scala 442:110] - node _T_18724 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18725 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18726 = eq(_T_18725, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_18727 = and(_T_18724, _T_18726) @[ifu_bp_ctl.scala 443:22] - node _T_18728 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18729 = eq(_T_18728, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_18730 = or(_T_18729, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18731 = and(_T_18727, _T_18730) @[ifu_bp_ctl.scala 443:87] - node _T_18732 = or(_T_18723, _T_18731) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][11][12] <= _T_18732 @[ifu_bp_ctl.scala 442:27] - node _T_18733 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18734 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18735 = eq(_T_18734, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_18736 = and(_T_18733, _T_18735) @[ifu_bp_ctl.scala 442:45] - node _T_18737 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18738 = eq(_T_18737, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_18739 = or(_T_18738, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18740 = and(_T_18736, _T_18739) @[ifu_bp_ctl.scala 442:110] - node _T_18741 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18742 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18743 = eq(_T_18742, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_18744 = and(_T_18741, _T_18743) @[ifu_bp_ctl.scala 443:22] - node _T_18745 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18746 = eq(_T_18745, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_18747 = or(_T_18746, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18748 = and(_T_18744, _T_18747) @[ifu_bp_ctl.scala 443:87] - node _T_18749 = or(_T_18740, _T_18748) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][11][13] <= _T_18749 @[ifu_bp_ctl.scala 442:27] - node _T_18750 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18751 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18752 = eq(_T_18751, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_18753 = and(_T_18750, _T_18752) @[ifu_bp_ctl.scala 442:45] - node _T_18754 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18755 = eq(_T_18754, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_18756 = or(_T_18755, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18757 = and(_T_18753, _T_18756) @[ifu_bp_ctl.scala 442:110] - node _T_18758 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18759 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18760 = eq(_T_18759, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_18761 = and(_T_18758, _T_18760) @[ifu_bp_ctl.scala 443:22] - node _T_18762 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18763 = eq(_T_18762, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_18764 = or(_T_18763, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18765 = and(_T_18761, _T_18764) @[ifu_bp_ctl.scala 443:87] - node _T_18766 = or(_T_18757, _T_18765) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][11][14] <= _T_18766 @[ifu_bp_ctl.scala 442:27] - node _T_18767 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18768 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18769 = eq(_T_18768, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_18770 = and(_T_18767, _T_18769) @[ifu_bp_ctl.scala 442:45] - node _T_18771 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18772 = eq(_T_18771, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:186] - node _T_18773 = or(_T_18772, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18774 = and(_T_18770, _T_18773) @[ifu_bp_ctl.scala 442:110] - node _T_18775 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18776 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18777 = eq(_T_18776, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_18778 = and(_T_18775, _T_18777) @[ifu_bp_ctl.scala 443:22] - node _T_18779 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18780 = eq(_T_18779, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:163] - node _T_18781 = or(_T_18780, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18782 = and(_T_18778, _T_18781) @[ifu_bp_ctl.scala 443:87] - node _T_18783 = or(_T_18774, _T_18782) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][11][15] <= _T_18783 @[ifu_bp_ctl.scala 442:27] - node _T_18784 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18785 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18786 = eq(_T_18785, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_18787 = and(_T_18784, _T_18786) @[ifu_bp_ctl.scala 442:45] - node _T_18788 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18789 = eq(_T_18788, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_18790 = or(_T_18789, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18791 = and(_T_18787, _T_18790) @[ifu_bp_ctl.scala 442:110] - node _T_18792 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18793 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18794 = eq(_T_18793, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_18795 = and(_T_18792, _T_18794) @[ifu_bp_ctl.scala 443:22] - node _T_18796 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18797 = eq(_T_18796, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_18798 = or(_T_18797, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18799 = and(_T_18795, _T_18798) @[ifu_bp_ctl.scala 443:87] - node _T_18800 = or(_T_18791, _T_18799) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][12][0] <= _T_18800 @[ifu_bp_ctl.scala 442:27] - node _T_18801 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18802 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18803 = eq(_T_18802, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_18804 = and(_T_18801, _T_18803) @[ifu_bp_ctl.scala 442:45] - node _T_18805 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18806 = eq(_T_18805, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_18807 = or(_T_18806, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18808 = and(_T_18804, _T_18807) @[ifu_bp_ctl.scala 442:110] - node _T_18809 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18810 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18811 = eq(_T_18810, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_18812 = and(_T_18809, _T_18811) @[ifu_bp_ctl.scala 443:22] - node _T_18813 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18814 = eq(_T_18813, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_18815 = or(_T_18814, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18816 = and(_T_18812, _T_18815) @[ifu_bp_ctl.scala 443:87] - node _T_18817 = or(_T_18808, _T_18816) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][12][1] <= _T_18817 @[ifu_bp_ctl.scala 442:27] - node _T_18818 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18819 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18820 = eq(_T_18819, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_18821 = and(_T_18818, _T_18820) @[ifu_bp_ctl.scala 442:45] - node _T_18822 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18823 = eq(_T_18822, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_18824 = or(_T_18823, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18825 = and(_T_18821, _T_18824) @[ifu_bp_ctl.scala 442:110] - node _T_18826 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18827 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18828 = eq(_T_18827, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_18829 = and(_T_18826, _T_18828) @[ifu_bp_ctl.scala 443:22] - node _T_18830 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18831 = eq(_T_18830, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_18832 = or(_T_18831, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18833 = and(_T_18829, _T_18832) @[ifu_bp_ctl.scala 443:87] - node _T_18834 = or(_T_18825, _T_18833) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][12][2] <= _T_18834 @[ifu_bp_ctl.scala 442:27] - node _T_18835 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18836 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18837 = eq(_T_18836, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_18838 = and(_T_18835, _T_18837) @[ifu_bp_ctl.scala 442:45] - node _T_18839 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18840 = eq(_T_18839, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_18841 = or(_T_18840, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18842 = and(_T_18838, _T_18841) @[ifu_bp_ctl.scala 442:110] - node _T_18843 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18844 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18845 = eq(_T_18844, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_18846 = and(_T_18843, _T_18845) @[ifu_bp_ctl.scala 443:22] - node _T_18847 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18848 = eq(_T_18847, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_18849 = or(_T_18848, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18850 = and(_T_18846, _T_18849) @[ifu_bp_ctl.scala 443:87] - node _T_18851 = or(_T_18842, _T_18850) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][12][3] <= _T_18851 @[ifu_bp_ctl.scala 442:27] - node _T_18852 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18853 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18854 = eq(_T_18853, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_18855 = and(_T_18852, _T_18854) @[ifu_bp_ctl.scala 442:45] - node _T_18856 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18857 = eq(_T_18856, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_18858 = or(_T_18857, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18859 = and(_T_18855, _T_18858) @[ifu_bp_ctl.scala 442:110] - node _T_18860 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18861 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18862 = eq(_T_18861, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_18863 = and(_T_18860, _T_18862) @[ifu_bp_ctl.scala 443:22] - node _T_18864 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18865 = eq(_T_18864, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_18866 = or(_T_18865, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18867 = and(_T_18863, _T_18866) @[ifu_bp_ctl.scala 443:87] - node _T_18868 = or(_T_18859, _T_18867) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][12][4] <= _T_18868 @[ifu_bp_ctl.scala 442:27] - node _T_18869 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18870 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18871 = eq(_T_18870, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_18872 = and(_T_18869, _T_18871) @[ifu_bp_ctl.scala 442:45] - node _T_18873 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18874 = eq(_T_18873, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_18875 = or(_T_18874, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18876 = and(_T_18872, _T_18875) @[ifu_bp_ctl.scala 442:110] - node _T_18877 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18878 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18879 = eq(_T_18878, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_18880 = and(_T_18877, _T_18879) @[ifu_bp_ctl.scala 443:22] - node _T_18881 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18882 = eq(_T_18881, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_18883 = or(_T_18882, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18884 = and(_T_18880, _T_18883) @[ifu_bp_ctl.scala 443:87] - node _T_18885 = or(_T_18876, _T_18884) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][12][5] <= _T_18885 @[ifu_bp_ctl.scala 442:27] - node _T_18886 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18887 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18888 = eq(_T_18887, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_18889 = and(_T_18886, _T_18888) @[ifu_bp_ctl.scala 442:45] - node _T_18890 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18891 = eq(_T_18890, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_18892 = or(_T_18891, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18893 = and(_T_18889, _T_18892) @[ifu_bp_ctl.scala 442:110] - node _T_18894 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18895 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18896 = eq(_T_18895, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_18897 = and(_T_18894, _T_18896) @[ifu_bp_ctl.scala 443:22] - node _T_18898 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18899 = eq(_T_18898, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_18900 = or(_T_18899, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18901 = and(_T_18897, _T_18900) @[ifu_bp_ctl.scala 443:87] - node _T_18902 = or(_T_18893, _T_18901) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][12][6] <= _T_18902 @[ifu_bp_ctl.scala 442:27] - node _T_18903 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18904 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18905 = eq(_T_18904, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_18906 = and(_T_18903, _T_18905) @[ifu_bp_ctl.scala 442:45] - node _T_18907 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18908 = eq(_T_18907, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_18909 = or(_T_18908, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18910 = and(_T_18906, _T_18909) @[ifu_bp_ctl.scala 442:110] - node _T_18911 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18912 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18913 = eq(_T_18912, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_18914 = and(_T_18911, _T_18913) @[ifu_bp_ctl.scala 443:22] - node _T_18915 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18916 = eq(_T_18915, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_18917 = or(_T_18916, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18918 = and(_T_18914, _T_18917) @[ifu_bp_ctl.scala 443:87] - node _T_18919 = or(_T_18910, _T_18918) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][12][7] <= _T_18919 @[ifu_bp_ctl.scala 442:27] - node _T_18920 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18921 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18922 = eq(_T_18921, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_18923 = and(_T_18920, _T_18922) @[ifu_bp_ctl.scala 442:45] - node _T_18924 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18925 = eq(_T_18924, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_18926 = or(_T_18925, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18927 = and(_T_18923, _T_18926) @[ifu_bp_ctl.scala 442:110] - node _T_18928 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18929 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18930 = eq(_T_18929, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_18931 = and(_T_18928, _T_18930) @[ifu_bp_ctl.scala 443:22] - node _T_18932 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18933 = eq(_T_18932, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_18934 = or(_T_18933, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18935 = and(_T_18931, _T_18934) @[ifu_bp_ctl.scala 443:87] - node _T_18936 = or(_T_18927, _T_18935) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][12][8] <= _T_18936 @[ifu_bp_ctl.scala 442:27] - node _T_18937 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18938 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18939 = eq(_T_18938, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_18940 = and(_T_18937, _T_18939) @[ifu_bp_ctl.scala 442:45] - node _T_18941 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18942 = eq(_T_18941, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_18943 = or(_T_18942, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18944 = and(_T_18940, _T_18943) @[ifu_bp_ctl.scala 442:110] - node _T_18945 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18946 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18947 = eq(_T_18946, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_18948 = and(_T_18945, _T_18947) @[ifu_bp_ctl.scala 443:22] - node _T_18949 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18950 = eq(_T_18949, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_18951 = or(_T_18950, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18952 = and(_T_18948, _T_18951) @[ifu_bp_ctl.scala 443:87] - node _T_18953 = or(_T_18944, _T_18952) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][12][9] <= _T_18953 @[ifu_bp_ctl.scala 442:27] - node _T_18954 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18955 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18956 = eq(_T_18955, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_18957 = and(_T_18954, _T_18956) @[ifu_bp_ctl.scala 442:45] - node _T_18958 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18959 = eq(_T_18958, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_18960 = or(_T_18959, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18961 = and(_T_18957, _T_18960) @[ifu_bp_ctl.scala 442:110] - node _T_18962 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18963 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18964 = eq(_T_18963, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_18965 = and(_T_18962, _T_18964) @[ifu_bp_ctl.scala 443:22] - node _T_18966 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18967 = eq(_T_18966, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_18968 = or(_T_18967, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18969 = and(_T_18965, _T_18968) @[ifu_bp_ctl.scala 443:87] - node _T_18970 = or(_T_18961, _T_18969) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][12][10] <= _T_18970 @[ifu_bp_ctl.scala 442:27] - node _T_18971 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18972 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18973 = eq(_T_18972, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_18974 = and(_T_18971, _T_18973) @[ifu_bp_ctl.scala 442:45] - node _T_18975 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18976 = eq(_T_18975, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_18977 = or(_T_18976, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18978 = and(_T_18974, _T_18977) @[ifu_bp_ctl.scala 442:110] - node _T_18979 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18980 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18981 = eq(_T_18980, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_18982 = and(_T_18979, _T_18981) @[ifu_bp_ctl.scala 443:22] - node _T_18983 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_18984 = eq(_T_18983, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_18985 = or(_T_18984, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_18986 = and(_T_18982, _T_18985) @[ifu_bp_ctl.scala 443:87] - node _T_18987 = or(_T_18978, _T_18986) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][12][11] <= _T_18987 @[ifu_bp_ctl.scala 442:27] - node _T_18988 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_18989 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_18990 = eq(_T_18989, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_18991 = and(_T_18988, _T_18990) @[ifu_bp_ctl.scala 442:45] - node _T_18992 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_18993 = eq(_T_18992, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_18994 = or(_T_18993, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_18995 = and(_T_18991, _T_18994) @[ifu_bp_ctl.scala 442:110] - node _T_18996 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_18997 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_18998 = eq(_T_18997, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_18999 = and(_T_18996, _T_18998) @[ifu_bp_ctl.scala 443:22] - node _T_19000 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19001 = eq(_T_19000, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_19002 = or(_T_19001, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19003 = and(_T_18999, _T_19002) @[ifu_bp_ctl.scala 443:87] - node _T_19004 = or(_T_18995, _T_19003) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][12][12] <= _T_19004 @[ifu_bp_ctl.scala 442:27] - node _T_19005 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19006 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19007 = eq(_T_19006, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_19008 = and(_T_19005, _T_19007) @[ifu_bp_ctl.scala 442:45] - node _T_19009 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19010 = eq(_T_19009, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_19011 = or(_T_19010, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19012 = and(_T_19008, _T_19011) @[ifu_bp_ctl.scala 442:110] - node _T_19013 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19014 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19015 = eq(_T_19014, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_19016 = and(_T_19013, _T_19015) @[ifu_bp_ctl.scala 443:22] - node _T_19017 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19018 = eq(_T_19017, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_19019 = or(_T_19018, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19020 = and(_T_19016, _T_19019) @[ifu_bp_ctl.scala 443:87] - node _T_19021 = or(_T_19012, _T_19020) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][12][13] <= _T_19021 @[ifu_bp_ctl.scala 442:27] - node _T_19022 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19023 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19024 = eq(_T_19023, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_19025 = and(_T_19022, _T_19024) @[ifu_bp_ctl.scala 442:45] - node _T_19026 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19027 = eq(_T_19026, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_19028 = or(_T_19027, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19029 = and(_T_19025, _T_19028) @[ifu_bp_ctl.scala 442:110] - node _T_19030 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19031 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19032 = eq(_T_19031, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_19033 = and(_T_19030, _T_19032) @[ifu_bp_ctl.scala 443:22] - node _T_19034 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19035 = eq(_T_19034, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_19036 = or(_T_19035, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19037 = and(_T_19033, _T_19036) @[ifu_bp_ctl.scala 443:87] - node _T_19038 = or(_T_19029, _T_19037) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][12][14] <= _T_19038 @[ifu_bp_ctl.scala 442:27] - node _T_19039 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19040 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19041 = eq(_T_19040, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_19042 = and(_T_19039, _T_19041) @[ifu_bp_ctl.scala 442:45] - node _T_19043 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19044 = eq(_T_19043, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:186] - node _T_19045 = or(_T_19044, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19046 = and(_T_19042, _T_19045) @[ifu_bp_ctl.scala 442:110] - node _T_19047 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19048 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19049 = eq(_T_19048, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_19050 = and(_T_19047, _T_19049) @[ifu_bp_ctl.scala 443:22] - node _T_19051 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19052 = eq(_T_19051, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:163] - node _T_19053 = or(_T_19052, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19054 = and(_T_19050, _T_19053) @[ifu_bp_ctl.scala 443:87] - node _T_19055 = or(_T_19046, _T_19054) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][12][15] <= _T_19055 @[ifu_bp_ctl.scala 442:27] - node _T_19056 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19057 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19058 = eq(_T_19057, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_19059 = and(_T_19056, _T_19058) @[ifu_bp_ctl.scala 442:45] - node _T_19060 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19061 = eq(_T_19060, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_19062 = or(_T_19061, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19063 = and(_T_19059, _T_19062) @[ifu_bp_ctl.scala 442:110] - node _T_19064 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19065 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19066 = eq(_T_19065, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_19067 = and(_T_19064, _T_19066) @[ifu_bp_ctl.scala 443:22] - node _T_19068 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19069 = eq(_T_19068, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_19070 = or(_T_19069, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19071 = and(_T_19067, _T_19070) @[ifu_bp_ctl.scala 443:87] - node _T_19072 = or(_T_19063, _T_19071) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][13][0] <= _T_19072 @[ifu_bp_ctl.scala 442:27] - node _T_19073 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19074 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19075 = eq(_T_19074, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_19076 = and(_T_19073, _T_19075) @[ifu_bp_ctl.scala 442:45] - node _T_19077 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19078 = eq(_T_19077, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_19079 = or(_T_19078, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19080 = and(_T_19076, _T_19079) @[ifu_bp_ctl.scala 442:110] - node _T_19081 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19082 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19083 = eq(_T_19082, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_19084 = and(_T_19081, _T_19083) @[ifu_bp_ctl.scala 443:22] - node _T_19085 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19086 = eq(_T_19085, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_19087 = or(_T_19086, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19088 = and(_T_19084, _T_19087) @[ifu_bp_ctl.scala 443:87] - node _T_19089 = or(_T_19080, _T_19088) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][13][1] <= _T_19089 @[ifu_bp_ctl.scala 442:27] - node _T_19090 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19091 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19092 = eq(_T_19091, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_19093 = and(_T_19090, _T_19092) @[ifu_bp_ctl.scala 442:45] - node _T_19094 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19095 = eq(_T_19094, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_19096 = or(_T_19095, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19097 = and(_T_19093, _T_19096) @[ifu_bp_ctl.scala 442:110] - node _T_19098 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19099 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19100 = eq(_T_19099, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_19101 = and(_T_19098, _T_19100) @[ifu_bp_ctl.scala 443:22] - node _T_19102 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19103 = eq(_T_19102, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_19104 = or(_T_19103, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19105 = and(_T_19101, _T_19104) @[ifu_bp_ctl.scala 443:87] - node _T_19106 = or(_T_19097, _T_19105) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][13][2] <= _T_19106 @[ifu_bp_ctl.scala 442:27] - node _T_19107 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19108 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19109 = eq(_T_19108, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_19110 = and(_T_19107, _T_19109) @[ifu_bp_ctl.scala 442:45] - node _T_19111 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19112 = eq(_T_19111, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_19113 = or(_T_19112, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19114 = and(_T_19110, _T_19113) @[ifu_bp_ctl.scala 442:110] - node _T_19115 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19116 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19117 = eq(_T_19116, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_19118 = and(_T_19115, _T_19117) @[ifu_bp_ctl.scala 443:22] - node _T_19119 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19120 = eq(_T_19119, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_19121 = or(_T_19120, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19122 = and(_T_19118, _T_19121) @[ifu_bp_ctl.scala 443:87] - node _T_19123 = or(_T_19114, _T_19122) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][13][3] <= _T_19123 @[ifu_bp_ctl.scala 442:27] - node _T_19124 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19125 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19126 = eq(_T_19125, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_19127 = and(_T_19124, _T_19126) @[ifu_bp_ctl.scala 442:45] - node _T_19128 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19129 = eq(_T_19128, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_19130 = or(_T_19129, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19131 = and(_T_19127, _T_19130) @[ifu_bp_ctl.scala 442:110] - node _T_19132 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19133 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19134 = eq(_T_19133, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_19135 = and(_T_19132, _T_19134) @[ifu_bp_ctl.scala 443:22] - node _T_19136 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19137 = eq(_T_19136, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_19138 = or(_T_19137, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19139 = and(_T_19135, _T_19138) @[ifu_bp_ctl.scala 443:87] - node _T_19140 = or(_T_19131, _T_19139) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][13][4] <= _T_19140 @[ifu_bp_ctl.scala 442:27] - node _T_19141 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19142 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19143 = eq(_T_19142, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_19144 = and(_T_19141, _T_19143) @[ifu_bp_ctl.scala 442:45] - node _T_19145 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19146 = eq(_T_19145, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_19147 = or(_T_19146, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19148 = and(_T_19144, _T_19147) @[ifu_bp_ctl.scala 442:110] - node _T_19149 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19150 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19151 = eq(_T_19150, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_19152 = and(_T_19149, _T_19151) @[ifu_bp_ctl.scala 443:22] - node _T_19153 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19154 = eq(_T_19153, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_19155 = or(_T_19154, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19156 = and(_T_19152, _T_19155) @[ifu_bp_ctl.scala 443:87] - node _T_19157 = or(_T_19148, _T_19156) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][13][5] <= _T_19157 @[ifu_bp_ctl.scala 442:27] - node _T_19158 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19159 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19160 = eq(_T_19159, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_19161 = and(_T_19158, _T_19160) @[ifu_bp_ctl.scala 442:45] - node _T_19162 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19163 = eq(_T_19162, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_19164 = or(_T_19163, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19165 = and(_T_19161, _T_19164) @[ifu_bp_ctl.scala 442:110] - node _T_19166 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19167 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19168 = eq(_T_19167, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_19169 = and(_T_19166, _T_19168) @[ifu_bp_ctl.scala 443:22] - node _T_19170 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19171 = eq(_T_19170, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_19172 = or(_T_19171, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19173 = and(_T_19169, _T_19172) @[ifu_bp_ctl.scala 443:87] - node _T_19174 = or(_T_19165, _T_19173) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][13][6] <= _T_19174 @[ifu_bp_ctl.scala 442:27] - node _T_19175 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19176 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19177 = eq(_T_19176, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_19178 = and(_T_19175, _T_19177) @[ifu_bp_ctl.scala 442:45] - node _T_19179 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19180 = eq(_T_19179, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_19181 = or(_T_19180, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19182 = and(_T_19178, _T_19181) @[ifu_bp_ctl.scala 442:110] - node _T_19183 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19184 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19185 = eq(_T_19184, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_19186 = and(_T_19183, _T_19185) @[ifu_bp_ctl.scala 443:22] - node _T_19187 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19188 = eq(_T_19187, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_19189 = or(_T_19188, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19190 = and(_T_19186, _T_19189) @[ifu_bp_ctl.scala 443:87] - node _T_19191 = or(_T_19182, _T_19190) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][13][7] <= _T_19191 @[ifu_bp_ctl.scala 442:27] - node _T_19192 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19193 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19194 = eq(_T_19193, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_19195 = and(_T_19192, _T_19194) @[ifu_bp_ctl.scala 442:45] - node _T_19196 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19197 = eq(_T_19196, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_19198 = or(_T_19197, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19199 = and(_T_19195, _T_19198) @[ifu_bp_ctl.scala 442:110] - node _T_19200 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19201 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19202 = eq(_T_19201, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_19203 = and(_T_19200, _T_19202) @[ifu_bp_ctl.scala 443:22] - node _T_19204 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19205 = eq(_T_19204, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_19206 = or(_T_19205, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19207 = and(_T_19203, _T_19206) @[ifu_bp_ctl.scala 443:87] - node _T_19208 = or(_T_19199, _T_19207) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][13][8] <= _T_19208 @[ifu_bp_ctl.scala 442:27] - node _T_19209 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19210 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19211 = eq(_T_19210, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_19212 = and(_T_19209, _T_19211) @[ifu_bp_ctl.scala 442:45] - node _T_19213 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19214 = eq(_T_19213, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_19215 = or(_T_19214, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19216 = and(_T_19212, _T_19215) @[ifu_bp_ctl.scala 442:110] - node _T_19217 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19218 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19219 = eq(_T_19218, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_19220 = and(_T_19217, _T_19219) @[ifu_bp_ctl.scala 443:22] - node _T_19221 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19222 = eq(_T_19221, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_19223 = or(_T_19222, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19224 = and(_T_19220, _T_19223) @[ifu_bp_ctl.scala 443:87] - node _T_19225 = or(_T_19216, _T_19224) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][13][9] <= _T_19225 @[ifu_bp_ctl.scala 442:27] - node _T_19226 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19227 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19228 = eq(_T_19227, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_19229 = and(_T_19226, _T_19228) @[ifu_bp_ctl.scala 442:45] - node _T_19230 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19231 = eq(_T_19230, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_19232 = or(_T_19231, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19233 = and(_T_19229, _T_19232) @[ifu_bp_ctl.scala 442:110] - node _T_19234 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19235 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19236 = eq(_T_19235, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_19237 = and(_T_19234, _T_19236) @[ifu_bp_ctl.scala 443:22] - node _T_19238 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19239 = eq(_T_19238, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_19240 = or(_T_19239, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19241 = and(_T_19237, _T_19240) @[ifu_bp_ctl.scala 443:87] - node _T_19242 = or(_T_19233, _T_19241) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][13][10] <= _T_19242 @[ifu_bp_ctl.scala 442:27] - node _T_19243 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19244 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19245 = eq(_T_19244, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_19246 = and(_T_19243, _T_19245) @[ifu_bp_ctl.scala 442:45] - node _T_19247 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19248 = eq(_T_19247, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_19249 = or(_T_19248, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19250 = and(_T_19246, _T_19249) @[ifu_bp_ctl.scala 442:110] - node _T_19251 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19252 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19253 = eq(_T_19252, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_19254 = and(_T_19251, _T_19253) @[ifu_bp_ctl.scala 443:22] - node _T_19255 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19256 = eq(_T_19255, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_19257 = or(_T_19256, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19258 = and(_T_19254, _T_19257) @[ifu_bp_ctl.scala 443:87] - node _T_19259 = or(_T_19250, _T_19258) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][13][11] <= _T_19259 @[ifu_bp_ctl.scala 442:27] - node _T_19260 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19261 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19262 = eq(_T_19261, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_19263 = and(_T_19260, _T_19262) @[ifu_bp_ctl.scala 442:45] - node _T_19264 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19265 = eq(_T_19264, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_19266 = or(_T_19265, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19267 = and(_T_19263, _T_19266) @[ifu_bp_ctl.scala 442:110] - node _T_19268 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19269 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19270 = eq(_T_19269, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_19271 = and(_T_19268, _T_19270) @[ifu_bp_ctl.scala 443:22] - node _T_19272 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19273 = eq(_T_19272, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_19274 = or(_T_19273, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19275 = and(_T_19271, _T_19274) @[ifu_bp_ctl.scala 443:87] - node _T_19276 = or(_T_19267, _T_19275) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][13][12] <= _T_19276 @[ifu_bp_ctl.scala 442:27] - node _T_19277 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19278 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19279 = eq(_T_19278, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_19280 = and(_T_19277, _T_19279) @[ifu_bp_ctl.scala 442:45] - node _T_19281 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19282 = eq(_T_19281, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_19283 = or(_T_19282, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19284 = and(_T_19280, _T_19283) @[ifu_bp_ctl.scala 442:110] - node _T_19285 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19286 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19287 = eq(_T_19286, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_19288 = and(_T_19285, _T_19287) @[ifu_bp_ctl.scala 443:22] - node _T_19289 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19290 = eq(_T_19289, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_19291 = or(_T_19290, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19292 = and(_T_19288, _T_19291) @[ifu_bp_ctl.scala 443:87] - node _T_19293 = or(_T_19284, _T_19292) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][13][13] <= _T_19293 @[ifu_bp_ctl.scala 442:27] - node _T_19294 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19295 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19296 = eq(_T_19295, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_19297 = and(_T_19294, _T_19296) @[ifu_bp_ctl.scala 442:45] - node _T_19298 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19299 = eq(_T_19298, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_19300 = or(_T_19299, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19301 = and(_T_19297, _T_19300) @[ifu_bp_ctl.scala 442:110] - node _T_19302 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19303 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19304 = eq(_T_19303, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_19305 = and(_T_19302, _T_19304) @[ifu_bp_ctl.scala 443:22] - node _T_19306 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19307 = eq(_T_19306, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_19308 = or(_T_19307, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19309 = and(_T_19305, _T_19308) @[ifu_bp_ctl.scala 443:87] - node _T_19310 = or(_T_19301, _T_19309) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][13][14] <= _T_19310 @[ifu_bp_ctl.scala 442:27] - node _T_19311 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19312 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19313 = eq(_T_19312, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_19314 = and(_T_19311, _T_19313) @[ifu_bp_ctl.scala 442:45] - node _T_19315 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19316 = eq(_T_19315, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:186] - node _T_19317 = or(_T_19316, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19318 = and(_T_19314, _T_19317) @[ifu_bp_ctl.scala 442:110] - node _T_19319 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19320 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19321 = eq(_T_19320, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_19322 = and(_T_19319, _T_19321) @[ifu_bp_ctl.scala 443:22] - node _T_19323 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19324 = eq(_T_19323, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:163] - node _T_19325 = or(_T_19324, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19326 = and(_T_19322, _T_19325) @[ifu_bp_ctl.scala 443:87] - node _T_19327 = or(_T_19318, _T_19326) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][13][15] <= _T_19327 @[ifu_bp_ctl.scala 442:27] - node _T_19328 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19329 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19330 = eq(_T_19329, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_19331 = and(_T_19328, _T_19330) @[ifu_bp_ctl.scala 442:45] - node _T_19332 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19333 = eq(_T_19332, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_19334 = or(_T_19333, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19335 = and(_T_19331, _T_19334) @[ifu_bp_ctl.scala 442:110] - node _T_19336 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19337 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19338 = eq(_T_19337, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_19339 = and(_T_19336, _T_19338) @[ifu_bp_ctl.scala 443:22] - node _T_19340 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19341 = eq(_T_19340, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_19342 = or(_T_19341, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19343 = and(_T_19339, _T_19342) @[ifu_bp_ctl.scala 443:87] - node _T_19344 = or(_T_19335, _T_19343) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][14][0] <= _T_19344 @[ifu_bp_ctl.scala 442:27] - node _T_19345 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19346 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19347 = eq(_T_19346, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_19348 = and(_T_19345, _T_19347) @[ifu_bp_ctl.scala 442:45] - node _T_19349 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19350 = eq(_T_19349, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_19351 = or(_T_19350, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19352 = and(_T_19348, _T_19351) @[ifu_bp_ctl.scala 442:110] - node _T_19353 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19354 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19355 = eq(_T_19354, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_19356 = and(_T_19353, _T_19355) @[ifu_bp_ctl.scala 443:22] - node _T_19357 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19358 = eq(_T_19357, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_19359 = or(_T_19358, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19360 = and(_T_19356, _T_19359) @[ifu_bp_ctl.scala 443:87] - node _T_19361 = or(_T_19352, _T_19360) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][14][1] <= _T_19361 @[ifu_bp_ctl.scala 442:27] - node _T_19362 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19363 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19364 = eq(_T_19363, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_19365 = and(_T_19362, _T_19364) @[ifu_bp_ctl.scala 442:45] - node _T_19366 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19367 = eq(_T_19366, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_19368 = or(_T_19367, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19369 = and(_T_19365, _T_19368) @[ifu_bp_ctl.scala 442:110] - node _T_19370 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19371 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19372 = eq(_T_19371, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_19373 = and(_T_19370, _T_19372) @[ifu_bp_ctl.scala 443:22] - node _T_19374 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19375 = eq(_T_19374, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_19376 = or(_T_19375, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19377 = and(_T_19373, _T_19376) @[ifu_bp_ctl.scala 443:87] - node _T_19378 = or(_T_19369, _T_19377) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][14][2] <= _T_19378 @[ifu_bp_ctl.scala 442:27] - node _T_19379 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19380 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19381 = eq(_T_19380, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_19382 = and(_T_19379, _T_19381) @[ifu_bp_ctl.scala 442:45] - node _T_19383 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19384 = eq(_T_19383, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_19385 = or(_T_19384, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19386 = and(_T_19382, _T_19385) @[ifu_bp_ctl.scala 442:110] - node _T_19387 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19388 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19389 = eq(_T_19388, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_19390 = and(_T_19387, _T_19389) @[ifu_bp_ctl.scala 443:22] - node _T_19391 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19392 = eq(_T_19391, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_19393 = or(_T_19392, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19394 = and(_T_19390, _T_19393) @[ifu_bp_ctl.scala 443:87] - node _T_19395 = or(_T_19386, _T_19394) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][14][3] <= _T_19395 @[ifu_bp_ctl.scala 442:27] - node _T_19396 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19397 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19398 = eq(_T_19397, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_19399 = and(_T_19396, _T_19398) @[ifu_bp_ctl.scala 442:45] - node _T_19400 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19401 = eq(_T_19400, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_19402 = or(_T_19401, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19403 = and(_T_19399, _T_19402) @[ifu_bp_ctl.scala 442:110] - node _T_19404 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19405 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19406 = eq(_T_19405, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_19407 = and(_T_19404, _T_19406) @[ifu_bp_ctl.scala 443:22] - node _T_19408 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19409 = eq(_T_19408, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_19410 = or(_T_19409, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19411 = and(_T_19407, _T_19410) @[ifu_bp_ctl.scala 443:87] - node _T_19412 = or(_T_19403, _T_19411) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][14][4] <= _T_19412 @[ifu_bp_ctl.scala 442:27] - node _T_19413 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19414 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19415 = eq(_T_19414, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_19416 = and(_T_19413, _T_19415) @[ifu_bp_ctl.scala 442:45] - node _T_19417 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19418 = eq(_T_19417, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_19419 = or(_T_19418, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19420 = and(_T_19416, _T_19419) @[ifu_bp_ctl.scala 442:110] - node _T_19421 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19422 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19423 = eq(_T_19422, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_19424 = and(_T_19421, _T_19423) @[ifu_bp_ctl.scala 443:22] - node _T_19425 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19426 = eq(_T_19425, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_19427 = or(_T_19426, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19428 = and(_T_19424, _T_19427) @[ifu_bp_ctl.scala 443:87] - node _T_19429 = or(_T_19420, _T_19428) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][14][5] <= _T_19429 @[ifu_bp_ctl.scala 442:27] - node _T_19430 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19431 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19432 = eq(_T_19431, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_19433 = and(_T_19430, _T_19432) @[ifu_bp_ctl.scala 442:45] - node _T_19434 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19435 = eq(_T_19434, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_19436 = or(_T_19435, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19437 = and(_T_19433, _T_19436) @[ifu_bp_ctl.scala 442:110] - node _T_19438 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19439 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19440 = eq(_T_19439, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_19441 = and(_T_19438, _T_19440) @[ifu_bp_ctl.scala 443:22] - node _T_19442 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19443 = eq(_T_19442, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_19444 = or(_T_19443, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19445 = and(_T_19441, _T_19444) @[ifu_bp_ctl.scala 443:87] - node _T_19446 = or(_T_19437, _T_19445) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][14][6] <= _T_19446 @[ifu_bp_ctl.scala 442:27] - node _T_19447 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19448 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19449 = eq(_T_19448, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_19450 = and(_T_19447, _T_19449) @[ifu_bp_ctl.scala 442:45] - node _T_19451 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19452 = eq(_T_19451, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_19453 = or(_T_19452, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19454 = and(_T_19450, _T_19453) @[ifu_bp_ctl.scala 442:110] - node _T_19455 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19456 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19457 = eq(_T_19456, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_19458 = and(_T_19455, _T_19457) @[ifu_bp_ctl.scala 443:22] - node _T_19459 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19460 = eq(_T_19459, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_19461 = or(_T_19460, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19462 = and(_T_19458, _T_19461) @[ifu_bp_ctl.scala 443:87] - node _T_19463 = or(_T_19454, _T_19462) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][14][7] <= _T_19463 @[ifu_bp_ctl.scala 442:27] - node _T_19464 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19465 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19466 = eq(_T_19465, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_19467 = and(_T_19464, _T_19466) @[ifu_bp_ctl.scala 442:45] - node _T_19468 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19469 = eq(_T_19468, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_19470 = or(_T_19469, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19471 = and(_T_19467, _T_19470) @[ifu_bp_ctl.scala 442:110] - node _T_19472 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19473 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19474 = eq(_T_19473, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_19475 = and(_T_19472, _T_19474) @[ifu_bp_ctl.scala 443:22] - node _T_19476 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19477 = eq(_T_19476, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_19478 = or(_T_19477, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19479 = and(_T_19475, _T_19478) @[ifu_bp_ctl.scala 443:87] - node _T_19480 = or(_T_19471, _T_19479) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][14][8] <= _T_19480 @[ifu_bp_ctl.scala 442:27] - node _T_19481 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19482 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19483 = eq(_T_19482, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_19484 = and(_T_19481, _T_19483) @[ifu_bp_ctl.scala 442:45] - node _T_19485 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19486 = eq(_T_19485, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_19487 = or(_T_19486, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19488 = and(_T_19484, _T_19487) @[ifu_bp_ctl.scala 442:110] - node _T_19489 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19490 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19491 = eq(_T_19490, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_19492 = and(_T_19489, _T_19491) @[ifu_bp_ctl.scala 443:22] - node _T_19493 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19494 = eq(_T_19493, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_19495 = or(_T_19494, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19496 = and(_T_19492, _T_19495) @[ifu_bp_ctl.scala 443:87] - node _T_19497 = or(_T_19488, _T_19496) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][14][9] <= _T_19497 @[ifu_bp_ctl.scala 442:27] - node _T_19498 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19499 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19500 = eq(_T_19499, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_19501 = and(_T_19498, _T_19500) @[ifu_bp_ctl.scala 442:45] - node _T_19502 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19503 = eq(_T_19502, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_19504 = or(_T_19503, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19505 = and(_T_19501, _T_19504) @[ifu_bp_ctl.scala 442:110] - node _T_19506 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19507 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19508 = eq(_T_19507, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_19509 = and(_T_19506, _T_19508) @[ifu_bp_ctl.scala 443:22] - node _T_19510 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19511 = eq(_T_19510, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_19512 = or(_T_19511, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19513 = and(_T_19509, _T_19512) @[ifu_bp_ctl.scala 443:87] - node _T_19514 = or(_T_19505, _T_19513) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][14][10] <= _T_19514 @[ifu_bp_ctl.scala 442:27] - node _T_19515 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19516 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19517 = eq(_T_19516, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_19518 = and(_T_19515, _T_19517) @[ifu_bp_ctl.scala 442:45] - node _T_19519 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19520 = eq(_T_19519, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_19521 = or(_T_19520, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19522 = and(_T_19518, _T_19521) @[ifu_bp_ctl.scala 442:110] - node _T_19523 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19524 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19525 = eq(_T_19524, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_19526 = and(_T_19523, _T_19525) @[ifu_bp_ctl.scala 443:22] - node _T_19527 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19528 = eq(_T_19527, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_19529 = or(_T_19528, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19530 = and(_T_19526, _T_19529) @[ifu_bp_ctl.scala 443:87] - node _T_19531 = or(_T_19522, _T_19530) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][14][11] <= _T_19531 @[ifu_bp_ctl.scala 442:27] - node _T_19532 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19533 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19534 = eq(_T_19533, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_19535 = and(_T_19532, _T_19534) @[ifu_bp_ctl.scala 442:45] - node _T_19536 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19537 = eq(_T_19536, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_19538 = or(_T_19537, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19539 = and(_T_19535, _T_19538) @[ifu_bp_ctl.scala 442:110] - node _T_19540 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19541 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19542 = eq(_T_19541, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_19543 = and(_T_19540, _T_19542) @[ifu_bp_ctl.scala 443:22] - node _T_19544 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19545 = eq(_T_19544, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_19546 = or(_T_19545, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19547 = and(_T_19543, _T_19546) @[ifu_bp_ctl.scala 443:87] - node _T_19548 = or(_T_19539, _T_19547) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][14][12] <= _T_19548 @[ifu_bp_ctl.scala 442:27] - node _T_19549 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19550 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19551 = eq(_T_19550, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_19552 = and(_T_19549, _T_19551) @[ifu_bp_ctl.scala 442:45] - node _T_19553 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19554 = eq(_T_19553, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_19555 = or(_T_19554, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19556 = and(_T_19552, _T_19555) @[ifu_bp_ctl.scala 442:110] - node _T_19557 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19558 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19559 = eq(_T_19558, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_19560 = and(_T_19557, _T_19559) @[ifu_bp_ctl.scala 443:22] - node _T_19561 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19562 = eq(_T_19561, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_19563 = or(_T_19562, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19564 = and(_T_19560, _T_19563) @[ifu_bp_ctl.scala 443:87] - node _T_19565 = or(_T_19556, _T_19564) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][14][13] <= _T_19565 @[ifu_bp_ctl.scala 442:27] - node _T_19566 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19567 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19568 = eq(_T_19567, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_19569 = and(_T_19566, _T_19568) @[ifu_bp_ctl.scala 442:45] - node _T_19570 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19571 = eq(_T_19570, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_19572 = or(_T_19571, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19573 = and(_T_19569, _T_19572) @[ifu_bp_ctl.scala 442:110] - node _T_19574 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19575 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19576 = eq(_T_19575, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_19577 = and(_T_19574, _T_19576) @[ifu_bp_ctl.scala 443:22] - node _T_19578 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19579 = eq(_T_19578, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_19580 = or(_T_19579, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19581 = and(_T_19577, _T_19580) @[ifu_bp_ctl.scala 443:87] - node _T_19582 = or(_T_19573, _T_19581) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][14][14] <= _T_19582 @[ifu_bp_ctl.scala 442:27] - node _T_19583 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19584 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19585 = eq(_T_19584, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_19586 = and(_T_19583, _T_19585) @[ifu_bp_ctl.scala 442:45] - node _T_19587 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19588 = eq(_T_19587, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:186] - node _T_19589 = or(_T_19588, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19590 = and(_T_19586, _T_19589) @[ifu_bp_ctl.scala 442:110] - node _T_19591 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19592 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19593 = eq(_T_19592, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_19594 = and(_T_19591, _T_19593) @[ifu_bp_ctl.scala 443:22] - node _T_19595 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19596 = eq(_T_19595, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:163] - node _T_19597 = or(_T_19596, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19598 = and(_T_19594, _T_19597) @[ifu_bp_ctl.scala 443:87] - node _T_19599 = or(_T_19590, _T_19598) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][14][15] <= _T_19599 @[ifu_bp_ctl.scala 442:27] - node _T_19600 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19601 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19602 = eq(_T_19601, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:97] - node _T_19603 = and(_T_19600, _T_19602) @[ifu_bp_ctl.scala 442:45] - node _T_19604 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19605 = eq(_T_19604, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_19606 = or(_T_19605, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19607 = and(_T_19603, _T_19606) @[ifu_bp_ctl.scala 442:110] - node _T_19608 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19609 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19610 = eq(_T_19609, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:74] - node _T_19611 = and(_T_19608, _T_19610) @[ifu_bp_ctl.scala 443:22] - node _T_19612 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19613 = eq(_T_19612, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_19614 = or(_T_19613, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19615 = and(_T_19611, _T_19614) @[ifu_bp_ctl.scala 443:87] - node _T_19616 = or(_T_19607, _T_19615) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][15][0] <= _T_19616 @[ifu_bp_ctl.scala 442:27] - node _T_19617 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19618 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19619 = eq(_T_19618, UInt<1>("h01")) @[ifu_bp_ctl.scala 442:97] - node _T_19620 = and(_T_19617, _T_19619) @[ifu_bp_ctl.scala 442:45] - node _T_19621 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19622 = eq(_T_19621, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_19623 = or(_T_19622, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19624 = and(_T_19620, _T_19623) @[ifu_bp_ctl.scala 442:110] - node _T_19625 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19626 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19627 = eq(_T_19626, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:74] - node _T_19628 = and(_T_19625, _T_19627) @[ifu_bp_ctl.scala 443:22] - node _T_19629 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19630 = eq(_T_19629, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_19631 = or(_T_19630, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19632 = and(_T_19628, _T_19631) @[ifu_bp_ctl.scala 443:87] - node _T_19633 = or(_T_19624, _T_19632) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][15][1] <= _T_19633 @[ifu_bp_ctl.scala 442:27] - node _T_19634 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19635 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19636 = eq(_T_19635, UInt<2>("h02")) @[ifu_bp_ctl.scala 442:97] - node _T_19637 = and(_T_19634, _T_19636) @[ifu_bp_ctl.scala 442:45] - node _T_19638 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19639 = eq(_T_19638, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_19640 = or(_T_19639, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19641 = and(_T_19637, _T_19640) @[ifu_bp_ctl.scala 442:110] - node _T_19642 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19643 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19644 = eq(_T_19643, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:74] - node _T_19645 = and(_T_19642, _T_19644) @[ifu_bp_ctl.scala 443:22] - node _T_19646 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19647 = eq(_T_19646, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_19648 = or(_T_19647, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19649 = and(_T_19645, _T_19648) @[ifu_bp_ctl.scala 443:87] - node _T_19650 = or(_T_19641, _T_19649) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][15][2] <= _T_19650 @[ifu_bp_ctl.scala 442:27] - node _T_19651 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19652 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19653 = eq(_T_19652, UInt<2>("h03")) @[ifu_bp_ctl.scala 442:97] - node _T_19654 = and(_T_19651, _T_19653) @[ifu_bp_ctl.scala 442:45] - node _T_19655 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19656 = eq(_T_19655, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_19657 = or(_T_19656, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19658 = and(_T_19654, _T_19657) @[ifu_bp_ctl.scala 442:110] - node _T_19659 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19660 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19661 = eq(_T_19660, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:74] - node _T_19662 = and(_T_19659, _T_19661) @[ifu_bp_ctl.scala 443:22] - node _T_19663 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19664 = eq(_T_19663, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_19665 = or(_T_19664, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19666 = and(_T_19662, _T_19665) @[ifu_bp_ctl.scala 443:87] - node _T_19667 = or(_T_19658, _T_19666) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][15][3] <= _T_19667 @[ifu_bp_ctl.scala 442:27] - node _T_19668 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19669 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19670 = eq(_T_19669, UInt<3>("h04")) @[ifu_bp_ctl.scala 442:97] - node _T_19671 = and(_T_19668, _T_19670) @[ifu_bp_ctl.scala 442:45] - node _T_19672 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19673 = eq(_T_19672, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_19674 = or(_T_19673, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19675 = and(_T_19671, _T_19674) @[ifu_bp_ctl.scala 442:110] - node _T_19676 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19677 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19678 = eq(_T_19677, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:74] - node _T_19679 = and(_T_19676, _T_19678) @[ifu_bp_ctl.scala 443:22] - node _T_19680 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19681 = eq(_T_19680, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_19682 = or(_T_19681, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19683 = and(_T_19679, _T_19682) @[ifu_bp_ctl.scala 443:87] - node _T_19684 = or(_T_19675, _T_19683) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][15][4] <= _T_19684 @[ifu_bp_ctl.scala 442:27] - node _T_19685 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19686 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19687 = eq(_T_19686, UInt<3>("h05")) @[ifu_bp_ctl.scala 442:97] - node _T_19688 = and(_T_19685, _T_19687) @[ifu_bp_ctl.scala 442:45] - node _T_19689 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19690 = eq(_T_19689, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_19691 = or(_T_19690, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19692 = and(_T_19688, _T_19691) @[ifu_bp_ctl.scala 442:110] - node _T_19693 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19694 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19695 = eq(_T_19694, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:74] - node _T_19696 = and(_T_19693, _T_19695) @[ifu_bp_ctl.scala 443:22] - node _T_19697 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19698 = eq(_T_19697, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_19699 = or(_T_19698, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19700 = and(_T_19696, _T_19699) @[ifu_bp_ctl.scala 443:87] - node _T_19701 = or(_T_19692, _T_19700) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][15][5] <= _T_19701 @[ifu_bp_ctl.scala 442:27] - node _T_19702 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19703 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19704 = eq(_T_19703, UInt<3>("h06")) @[ifu_bp_ctl.scala 442:97] - node _T_19705 = and(_T_19702, _T_19704) @[ifu_bp_ctl.scala 442:45] - node _T_19706 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19707 = eq(_T_19706, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_19708 = or(_T_19707, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19709 = and(_T_19705, _T_19708) @[ifu_bp_ctl.scala 442:110] - node _T_19710 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19711 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19712 = eq(_T_19711, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:74] - node _T_19713 = and(_T_19710, _T_19712) @[ifu_bp_ctl.scala 443:22] - node _T_19714 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19715 = eq(_T_19714, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_19716 = or(_T_19715, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19717 = and(_T_19713, _T_19716) @[ifu_bp_ctl.scala 443:87] - node _T_19718 = or(_T_19709, _T_19717) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][15][6] <= _T_19718 @[ifu_bp_ctl.scala 442:27] - node _T_19719 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19720 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19721 = eq(_T_19720, UInt<3>("h07")) @[ifu_bp_ctl.scala 442:97] - node _T_19722 = and(_T_19719, _T_19721) @[ifu_bp_ctl.scala 442:45] - node _T_19723 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19724 = eq(_T_19723, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_19725 = or(_T_19724, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19726 = and(_T_19722, _T_19725) @[ifu_bp_ctl.scala 442:110] - node _T_19727 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19728 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19729 = eq(_T_19728, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:74] - node _T_19730 = and(_T_19727, _T_19729) @[ifu_bp_ctl.scala 443:22] - node _T_19731 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19732 = eq(_T_19731, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_19733 = or(_T_19732, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19734 = and(_T_19730, _T_19733) @[ifu_bp_ctl.scala 443:87] - node _T_19735 = or(_T_19726, _T_19734) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][15][7] <= _T_19735 @[ifu_bp_ctl.scala 442:27] - node _T_19736 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19737 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19738 = eq(_T_19737, UInt<4>("h08")) @[ifu_bp_ctl.scala 442:97] - node _T_19739 = and(_T_19736, _T_19738) @[ifu_bp_ctl.scala 442:45] - node _T_19740 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19741 = eq(_T_19740, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_19742 = or(_T_19741, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19743 = and(_T_19739, _T_19742) @[ifu_bp_ctl.scala 442:110] - node _T_19744 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19745 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19746 = eq(_T_19745, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:74] - node _T_19747 = and(_T_19744, _T_19746) @[ifu_bp_ctl.scala 443:22] - node _T_19748 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19749 = eq(_T_19748, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_19750 = or(_T_19749, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19751 = and(_T_19747, _T_19750) @[ifu_bp_ctl.scala 443:87] - node _T_19752 = or(_T_19743, _T_19751) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][15][8] <= _T_19752 @[ifu_bp_ctl.scala 442:27] - node _T_19753 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19754 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19755 = eq(_T_19754, UInt<4>("h09")) @[ifu_bp_ctl.scala 442:97] - node _T_19756 = and(_T_19753, _T_19755) @[ifu_bp_ctl.scala 442:45] - node _T_19757 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19758 = eq(_T_19757, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_19759 = or(_T_19758, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19760 = and(_T_19756, _T_19759) @[ifu_bp_ctl.scala 442:110] - node _T_19761 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19762 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19763 = eq(_T_19762, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:74] - node _T_19764 = and(_T_19761, _T_19763) @[ifu_bp_ctl.scala 443:22] - node _T_19765 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19766 = eq(_T_19765, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_19767 = or(_T_19766, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19768 = and(_T_19764, _T_19767) @[ifu_bp_ctl.scala 443:87] - node _T_19769 = or(_T_19760, _T_19768) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][15][9] <= _T_19769 @[ifu_bp_ctl.scala 442:27] - node _T_19770 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19771 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19772 = eq(_T_19771, UInt<4>("h0a")) @[ifu_bp_ctl.scala 442:97] - node _T_19773 = and(_T_19770, _T_19772) @[ifu_bp_ctl.scala 442:45] - node _T_19774 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19775 = eq(_T_19774, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_19776 = or(_T_19775, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19777 = and(_T_19773, _T_19776) @[ifu_bp_ctl.scala 442:110] - node _T_19778 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19779 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19780 = eq(_T_19779, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:74] - node _T_19781 = and(_T_19778, _T_19780) @[ifu_bp_ctl.scala 443:22] - node _T_19782 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19783 = eq(_T_19782, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_19784 = or(_T_19783, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19785 = and(_T_19781, _T_19784) @[ifu_bp_ctl.scala 443:87] - node _T_19786 = or(_T_19777, _T_19785) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][15][10] <= _T_19786 @[ifu_bp_ctl.scala 442:27] - node _T_19787 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19788 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19789 = eq(_T_19788, UInt<4>("h0b")) @[ifu_bp_ctl.scala 442:97] - node _T_19790 = and(_T_19787, _T_19789) @[ifu_bp_ctl.scala 442:45] - node _T_19791 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19792 = eq(_T_19791, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_19793 = or(_T_19792, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19794 = and(_T_19790, _T_19793) @[ifu_bp_ctl.scala 442:110] - node _T_19795 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19796 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19797 = eq(_T_19796, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:74] - node _T_19798 = and(_T_19795, _T_19797) @[ifu_bp_ctl.scala 443:22] - node _T_19799 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19800 = eq(_T_19799, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_19801 = or(_T_19800, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19802 = and(_T_19798, _T_19801) @[ifu_bp_ctl.scala 443:87] - node _T_19803 = or(_T_19794, _T_19802) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][15][11] <= _T_19803 @[ifu_bp_ctl.scala 442:27] - node _T_19804 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19805 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19806 = eq(_T_19805, UInt<4>("h0c")) @[ifu_bp_ctl.scala 442:97] - node _T_19807 = and(_T_19804, _T_19806) @[ifu_bp_ctl.scala 442:45] - node _T_19808 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19809 = eq(_T_19808, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_19810 = or(_T_19809, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19811 = and(_T_19807, _T_19810) @[ifu_bp_ctl.scala 442:110] - node _T_19812 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19813 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19814 = eq(_T_19813, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:74] - node _T_19815 = and(_T_19812, _T_19814) @[ifu_bp_ctl.scala 443:22] - node _T_19816 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19817 = eq(_T_19816, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_19818 = or(_T_19817, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19819 = and(_T_19815, _T_19818) @[ifu_bp_ctl.scala 443:87] - node _T_19820 = or(_T_19811, _T_19819) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][15][12] <= _T_19820 @[ifu_bp_ctl.scala 442:27] - node _T_19821 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19822 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19823 = eq(_T_19822, UInt<4>("h0d")) @[ifu_bp_ctl.scala 442:97] - node _T_19824 = and(_T_19821, _T_19823) @[ifu_bp_ctl.scala 442:45] - node _T_19825 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19826 = eq(_T_19825, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_19827 = or(_T_19826, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19828 = and(_T_19824, _T_19827) @[ifu_bp_ctl.scala 442:110] - node _T_19829 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19830 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19831 = eq(_T_19830, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:74] - node _T_19832 = and(_T_19829, _T_19831) @[ifu_bp_ctl.scala 443:22] - node _T_19833 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19834 = eq(_T_19833, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_19835 = or(_T_19834, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19836 = and(_T_19832, _T_19835) @[ifu_bp_ctl.scala 443:87] - node _T_19837 = or(_T_19828, _T_19836) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][15][13] <= _T_19837 @[ifu_bp_ctl.scala 442:27] - node _T_19838 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19839 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19840 = eq(_T_19839, UInt<4>("h0e")) @[ifu_bp_ctl.scala 442:97] - node _T_19841 = and(_T_19838, _T_19840) @[ifu_bp_ctl.scala 442:45] - node _T_19842 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19843 = eq(_T_19842, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_19844 = or(_T_19843, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19845 = and(_T_19841, _T_19844) @[ifu_bp_ctl.scala 442:110] - node _T_19846 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19847 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19848 = eq(_T_19847, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:74] - node _T_19849 = and(_T_19846, _T_19848) @[ifu_bp_ctl.scala 443:22] - node _T_19850 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19851 = eq(_T_19850, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_19852 = or(_T_19851, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19853 = and(_T_19849, _T_19852) @[ifu_bp_ctl.scala 443:87] - node _T_19854 = or(_T_19845, _T_19853) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][15][14] <= _T_19854 @[ifu_bp_ctl.scala 442:27] - node _T_19855 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 442:41] - node _T_19856 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 442:60] - node _T_19857 = eq(_T_19856, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:97] - node _T_19858 = and(_T_19855, _T_19857) @[ifu_bp_ctl.scala 442:45] - node _T_19859 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 442:126] - node _T_19860 = eq(_T_19859, UInt<4>("h0f")) @[ifu_bp_ctl.scala 442:186] - node _T_19861 = or(_T_19860, UInt<1>("h00")) @[ifu_bp_ctl.scala 442:199] - node _T_19862 = and(_T_19858, _T_19861) @[ifu_bp_ctl.scala 442:110] - node _T_19863 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 443:18] - node _T_19864 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 443:37] - node _T_19865 = eq(_T_19864, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:74] - node _T_19866 = and(_T_19863, _T_19865) @[ifu_bp_ctl.scala 443:22] - node _T_19867 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 443:103] - node _T_19868 = eq(_T_19867, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:163] - node _T_19869 = or(_T_19868, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:176] - node _T_19870 = and(_T_19866, _T_19869) @[ifu_bp_ctl.scala 443:87] - node _T_19871 = or(_T_19862, _T_19870) @[ifu_bp_ctl.scala 442:223] - bht_bank_sel[1][15][15] <= _T_19871 @[ifu_bp_ctl.scala 442:27] - wire bht_bank_rd_data_out : UInt<2>[256][2] @[ifu_bp_ctl.scala 447:34] + node _T_6208 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 429:40] + node _T_6209 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6210 = eq(_T_6209, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:109] + node _T_6211 = or(_T_6210, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6212 = and(_T_6208, _T_6211) @[ifu_bp_ctl.scala 429:44] + node _T_6213 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 430:40] + node _T_6214 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6215 = eq(_T_6214, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:109] + node _T_6216 = or(_T_6215, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6217 = and(_T_6213, _T_6216) @[ifu_bp_ctl.scala 430:44] + node _T_6218 = or(_T_6212, _T_6217) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[0][0] <= _T_6218 @[ifu_bp_ctl.scala 429:26] + node _T_6219 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 429:40] + node _T_6220 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6221 = eq(_T_6220, UInt<1>("h01")) @[ifu_bp_ctl.scala 429:109] + node _T_6222 = or(_T_6221, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6223 = and(_T_6219, _T_6222) @[ifu_bp_ctl.scala 429:44] + node _T_6224 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 430:40] + node _T_6225 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6226 = eq(_T_6225, UInt<1>("h01")) @[ifu_bp_ctl.scala 430:109] + node _T_6227 = or(_T_6226, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6228 = and(_T_6224, _T_6227) @[ifu_bp_ctl.scala 430:44] + node _T_6229 = or(_T_6223, _T_6228) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[0][1] <= _T_6229 @[ifu_bp_ctl.scala 429:26] + node _T_6230 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 429:40] + node _T_6231 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6232 = eq(_T_6231, UInt<2>("h02")) @[ifu_bp_ctl.scala 429:109] + node _T_6233 = or(_T_6232, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6234 = and(_T_6230, _T_6233) @[ifu_bp_ctl.scala 429:44] + node _T_6235 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 430:40] + node _T_6236 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6237 = eq(_T_6236, UInt<2>("h02")) @[ifu_bp_ctl.scala 430:109] + node _T_6238 = or(_T_6237, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6239 = and(_T_6235, _T_6238) @[ifu_bp_ctl.scala 430:44] + node _T_6240 = or(_T_6234, _T_6239) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[0][2] <= _T_6240 @[ifu_bp_ctl.scala 429:26] + node _T_6241 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 429:40] + node _T_6242 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6243 = eq(_T_6242, UInt<2>("h03")) @[ifu_bp_ctl.scala 429:109] + node _T_6244 = or(_T_6243, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6245 = and(_T_6241, _T_6244) @[ifu_bp_ctl.scala 429:44] + node _T_6246 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 430:40] + node _T_6247 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6248 = eq(_T_6247, UInt<2>("h03")) @[ifu_bp_ctl.scala 430:109] + node _T_6249 = or(_T_6248, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6250 = and(_T_6246, _T_6249) @[ifu_bp_ctl.scala 430:44] + node _T_6251 = or(_T_6245, _T_6250) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[0][3] <= _T_6251 @[ifu_bp_ctl.scala 429:26] + node _T_6252 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 429:40] + node _T_6253 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6254 = eq(_T_6253, UInt<3>("h04")) @[ifu_bp_ctl.scala 429:109] + node _T_6255 = or(_T_6254, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6256 = and(_T_6252, _T_6255) @[ifu_bp_ctl.scala 429:44] + node _T_6257 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 430:40] + node _T_6258 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6259 = eq(_T_6258, UInt<3>("h04")) @[ifu_bp_ctl.scala 430:109] + node _T_6260 = or(_T_6259, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6261 = and(_T_6257, _T_6260) @[ifu_bp_ctl.scala 430:44] + node _T_6262 = or(_T_6256, _T_6261) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[0][4] <= _T_6262 @[ifu_bp_ctl.scala 429:26] + node _T_6263 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 429:40] + node _T_6264 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6265 = eq(_T_6264, UInt<3>("h05")) @[ifu_bp_ctl.scala 429:109] + node _T_6266 = or(_T_6265, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6267 = and(_T_6263, _T_6266) @[ifu_bp_ctl.scala 429:44] + node _T_6268 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 430:40] + node _T_6269 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6270 = eq(_T_6269, UInt<3>("h05")) @[ifu_bp_ctl.scala 430:109] + node _T_6271 = or(_T_6270, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6272 = and(_T_6268, _T_6271) @[ifu_bp_ctl.scala 430:44] + node _T_6273 = or(_T_6267, _T_6272) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[0][5] <= _T_6273 @[ifu_bp_ctl.scala 429:26] + node _T_6274 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 429:40] + node _T_6275 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6276 = eq(_T_6275, UInt<3>("h06")) @[ifu_bp_ctl.scala 429:109] + node _T_6277 = or(_T_6276, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6278 = and(_T_6274, _T_6277) @[ifu_bp_ctl.scala 429:44] + node _T_6279 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 430:40] + node _T_6280 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6281 = eq(_T_6280, UInt<3>("h06")) @[ifu_bp_ctl.scala 430:109] + node _T_6282 = or(_T_6281, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6283 = and(_T_6279, _T_6282) @[ifu_bp_ctl.scala 430:44] + node _T_6284 = or(_T_6278, _T_6283) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[0][6] <= _T_6284 @[ifu_bp_ctl.scala 429:26] + node _T_6285 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 429:40] + node _T_6286 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6287 = eq(_T_6286, UInt<3>("h07")) @[ifu_bp_ctl.scala 429:109] + node _T_6288 = or(_T_6287, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6289 = and(_T_6285, _T_6288) @[ifu_bp_ctl.scala 429:44] + node _T_6290 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 430:40] + node _T_6291 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6292 = eq(_T_6291, UInt<3>("h07")) @[ifu_bp_ctl.scala 430:109] + node _T_6293 = or(_T_6292, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6294 = and(_T_6290, _T_6293) @[ifu_bp_ctl.scala 430:44] + node _T_6295 = or(_T_6289, _T_6294) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[0][7] <= _T_6295 @[ifu_bp_ctl.scala 429:26] + node _T_6296 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 429:40] + node _T_6297 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6298 = eq(_T_6297, UInt<4>("h08")) @[ifu_bp_ctl.scala 429:109] + node _T_6299 = or(_T_6298, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6300 = and(_T_6296, _T_6299) @[ifu_bp_ctl.scala 429:44] + node _T_6301 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 430:40] + node _T_6302 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6303 = eq(_T_6302, UInt<4>("h08")) @[ifu_bp_ctl.scala 430:109] + node _T_6304 = or(_T_6303, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6305 = and(_T_6301, _T_6304) @[ifu_bp_ctl.scala 430:44] + node _T_6306 = or(_T_6300, _T_6305) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[0][8] <= _T_6306 @[ifu_bp_ctl.scala 429:26] + node _T_6307 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 429:40] + node _T_6308 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6309 = eq(_T_6308, UInt<4>("h09")) @[ifu_bp_ctl.scala 429:109] + node _T_6310 = or(_T_6309, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6311 = and(_T_6307, _T_6310) @[ifu_bp_ctl.scala 429:44] + node _T_6312 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 430:40] + node _T_6313 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6314 = eq(_T_6313, UInt<4>("h09")) @[ifu_bp_ctl.scala 430:109] + node _T_6315 = or(_T_6314, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6316 = and(_T_6312, _T_6315) @[ifu_bp_ctl.scala 430:44] + node _T_6317 = or(_T_6311, _T_6316) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[0][9] <= _T_6317 @[ifu_bp_ctl.scala 429:26] + node _T_6318 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 429:40] + node _T_6319 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6320 = eq(_T_6319, UInt<4>("h0a")) @[ifu_bp_ctl.scala 429:109] + node _T_6321 = or(_T_6320, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6322 = and(_T_6318, _T_6321) @[ifu_bp_ctl.scala 429:44] + node _T_6323 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 430:40] + node _T_6324 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6325 = eq(_T_6324, UInt<4>("h0a")) @[ifu_bp_ctl.scala 430:109] + node _T_6326 = or(_T_6325, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6327 = and(_T_6323, _T_6326) @[ifu_bp_ctl.scala 430:44] + node _T_6328 = or(_T_6322, _T_6327) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[0][10] <= _T_6328 @[ifu_bp_ctl.scala 429:26] + node _T_6329 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 429:40] + node _T_6330 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6331 = eq(_T_6330, UInt<4>("h0b")) @[ifu_bp_ctl.scala 429:109] + node _T_6332 = or(_T_6331, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6333 = and(_T_6329, _T_6332) @[ifu_bp_ctl.scala 429:44] + node _T_6334 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 430:40] + node _T_6335 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6336 = eq(_T_6335, UInt<4>("h0b")) @[ifu_bp_ctl.scala 430:109] + node _T_6337 = or(_T_6336, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6338 = and(_T_6334, _T_6337) @[ifu_bp_ctl.scala 430:44] + node _T_6339 = or(_T_6333, _T_6338) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[0][11] <= _T_6339 @[ifu_bp_ctl.scala 429:26] + node _T_6340 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 429:40] + node _T_6341 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6342 = eq(_T_6341, UInt<4>("h0c")) @[ifu_bp_ctl.scala 429:109] + node _T_6343 = or(_T_6342, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6344 = and(_T_6340, _T_6343) @[ifu_bp_ctl.scala 429:44] + node _T_6345 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 430:40] + node _T_6346 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6347 = eq(_T_6346, UInt<4>("h0c")) @[ifu_bp_ctl.scala 430:109] + node _T_6348 = or(_T_6347, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6349 = and(_T_6345, _T_6348) @[ifu_bp_ctl.scala 430:44] + node _T_6350 = or(_T_6344, _T_6349) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[0][12] <= _T_6350 @[ifu_bp_ctl.scala 429:26] + node _T_6351 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 429:40] + node _T_6352 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6353 = eq(_T_6352, UInt<4>("h0d")) @[ifu_bp_ctl.scala 429:109] + node _T_6354 = or(_T_6353, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6355 = and(_T_6351, _T_6354) @[ifu_bp_ctl.scala 429:44] + node _T_6356 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 430:40] + node _T_6357 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6358 = eq(_T_6357, UInt<4>("h0d")) @[ifu_bp_ctl.scala 430:109] + node _T_6359 = or(_T_6358, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6360 = and(_T_6356, _T_6359) @[ifu_bp_ctl.scala 430:44] + node _T_6361 = or(_T_6355, _T_6360) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[0][13] <= _T_6361 @[ifu_bp_ctl.scala 429:26] + node _T_6362 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 429:40] + node _T_6363 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6364 = eq(_T_6363, UInt<4>("h0e")) @[ifu_bp_ctl.scala 429:109] + node _T_6365 = or(_T_6364, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6366 = and(_T_6362, _T_6365) @[ifu_bp_ctl.scala 429:44] + node _T_6367 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 430:40] + node _T_6368 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6369 = eq(_T_6368, UInt<4>("h0e")) @[ifu_bp_ctl.scala 430:109] + node _T_6370 = or(_T_6369, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6371 = and(_T_6367, _T_6370) @[ifu_bp_ctl.scala 430:44] + node _T_6372 = or(_T_6366, _T_6371) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[0][14] <= _T_6372 @[ifu_bp_ctl.scala 429:26] + node _T_6373 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 429:40] + node _T_6374 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6375 = eq(_T_6374, UInt<4>("h0f")) @[ifu_bp_ctl.scala 429:109] + node _T_6376 = or(_T_6375, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6377 = and(_T_6373, _T_6376) @[ifu_bp_ctl.scala 429:44] + node _T_6378 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 430:40] + node _T_6379 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6380 = eq(_T_6379, UInt<4>("h0f")) @[ifu_bp_ctl.scala 430:109] + node _T_6381 = or(_T_6380, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6382 = and(_T_6378, _T_6381) @[ifu_bp_ctl.scala 430:44] + node _T_6383 = or(_T_6377, _T_6382) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[0][15] <= _T_6383 @[ifu_bp_ctl.scala 429:26] + node _T_6384 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 429:40] + node _T_6385 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6386 = eq(_T_6385, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:109] + node _T_6387 = or(_T_6386, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6388 = and(_T_6384, _T_6387) @[ifu_bp_ctl.scala 429:44] + node _T_6389 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 430:40] + node _T_6390 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6391 = eq(_T_6390, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:109] + node _T_6392 = or(_T_6391, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6393 = and(_T_6389, _T_6392) @[ifu_bp_ctl.scala 430:44] + node _T_6394 = or(_T_6388, _T_6393) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[1][0] <= _T_6394 @[ifu_bp_ctl.scala 429:26] + node _T_6395 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 429:40] + node _T_6396 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6397 = eq(_T_6396, UInt<1>("h01")) @[ifu_bp_ctl.scala 429:109] + node _T_6398 = or(_T_6397, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6399 = and(_T_6395, _T_6398) @[ifu_bp_ctl.scala 429:44] + node _T_6400 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 430:40] + node _T_6401 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6402 = eq(_T_6401, UInt<1>("h01")) @[ifu_bp_ctl.scala 430:109] + node _T_6403 = or(_T_6402, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6404 = and(_T_6400, _T_6403) @[ifu_bp_ctl.scala 430:44] + node _T_6405 = or(_T_6399, _T_6404) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[1][1] <= _T_6405 @[ifu_bp_ctl.scala 429:26] + node _T_6406 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 429:40] + node _T_6407 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6408 = eq(_T_6407, UInt<2>("h02")) @[ifu_bp_ctl.scala 429:109] + node _T_6409 = or(_T_6408, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6410 = and(_T_6406, _T_6409) @[ifu_bp_ctl.scala 429:44] + node _T_6411 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 430:40] + node _T_6412 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6413 = eq(_T_6412, UInt<2>("h02")) @[ifu_bp_ctl.scala 430:109] + node _T_6414 = or(_T_6413, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6415 = and(_T_6411, _T_6414) @[ifu_bp_ctl.scala 430:44] + node _T_6416 = or(_T_6410, _T_6415) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[1][2] <= _T_6416 @[ifu_bp_ctl.scala 429:26] + node _T_6417 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 429:40] + node _T_6418 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6419 = eq(_T_6418, UInt<2>("h03")) @[ifu_bp_ctl.scala 429:109] + node _T_6420 = or(_T_6419, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6421 = and(_T_6417, _T_6420) @[ifu_bp_ctl.scala 429:44] + node _T_6422 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 430:40] + node _T_6423 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6424 = eq(_T_6423, UInt<2>("h03")) @[ifu_bp_ctl.scala 430:109] + node _T_6425 = or(_T_6424, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6426 = and(_T_6422, _T_6425) @[ifu_bp_ctl.scala 430:44] + node _T_6427 = or(_T_6421, _T_6426) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[1][3] <= _T_6427 @[ifu_bp_ctl.scala 429:26] + node _T_6428 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 429:40] + node _T_6429 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6430 = eq(_T_6429, UInt<3>("h04")) @[ifu_bp_ctl.scala 429:109] + node _T_6431 = or(_T_6430, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6432 = and(_T_6428, _T_6431) @[ifu_bp_ctl.scala 429:44] + node _T_6433 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 430:40] + node _T_6434 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6435 = eq(_T_6434, UInt<3>("h04")) @[ifu_bp_ctl.scala 430:109] + node _T_6436 = or(_T_6435, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6437 = and(_T_6433, _T_6436) @[ifu_bp_ctl.scala 430:44] + node _T_6438 = or(_T_6432, _T_6437) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[1][4] <= _T_6438 @[ifu_bp_ctl.scala 429:26] + node _T_6439 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 429:40] + node _T_6440 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6441 = eq(_T_6440, UInt<3>("h05")) @[ifu_bp_ctl.scala 429:109] + node _T_6442 = or(_T_6441, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6443 = and(_T_6439, _T_6442) @[ifu_bp_ctl.scala 429:44] + node _T_6444 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 430:40] + node _T_6445 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6446 = eq(_T_6445, UInt<3>("h05")) @[ifu_bp_ctl.scala 430:109] + node _T_6447 = or(_T_6446, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6448 = and(_T_6444, _T_6447) @[ifu_bp_ctl.scala 430:44] + node _T_6449 = or(_T_6443, _T_6448) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[1][5] <= _T_6449 @[ifu_bp_ctl.scala 429:26] + node _T_6450 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 429:40] + node _T_6451 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6452 = eq(_T_6451, UInt<3>("h06")) @[ifu_bp_ctl.scala 429:109] + node _T_6453 = or(_T_6452, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6454 = and(_T_6450, _T_6453) @[ifu_bp_ctl.scala 429:44] + node _T_6455 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 430:40] + node _T_6456 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6457 = eq(_T_6456, UInt<3>("h06")) @[ifu_bp_ctl.scala 430:109] + node _T_6458 = or(_T_6457, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6459 = and(_T_6455, _T_6458) @[ifu_bp_ctl.scala 430:44] + node _T_6460 = or(_T_6454, _T_6459) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[1][6] <= _T_6460 @[ifu_bp_ctl.scala 429:26] + node _T_6461 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 429:40] + node _T_6462 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6463 = eq(_T_6462, UInt<3>("h07")) @[ifu_bp_ctl.scala 429:109] + node _T_6464 = or(_T_6463, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6465 = and(_T_6461, _T_6464) @[ifu_bp_ctl.scala 429:44] + node _T_6466 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 430:40] + node _T_6467 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6468 = eq(_T_6467, UInt<3>("h07")) @[ifu_bp_ctl.scala 430:109] + node _T_6469 = or(_T_6468, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6470 = and(_T_6466, _T_6469) @[ifu_bp_ctl.scala 430:44] + node _T_6471 = or(_T_6465, _T_6470) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[1][7] <= _T_6471 @[ifu_bp_ctl.scala 429:26] + node _T_6472 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 429:40] + node _T_6473 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6474 = eq(_T_6473, UInt<4>("h08")) @[ifu_bp_ctl.scala 429:109] + node _T_6475 = or(_T_6474, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6476 = and(_T_6472, _T_6475) @[ifu_bp_ctl.scala 429:44] + node _T_6477 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 430:40] + node _T_6478 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6479 = eq(_T_6478, UInt<4>("h08")) @[ifu_bp_ctl.scala 430:109] + node _T_6480 = or(_T_6479, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6481 = and(_T_6477, _T_6480) @[ifu_bp_ctl.scala 430:44] + node _T_6482 = or(_T_6476, _T_6481) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[1][8] <= _T_6482 @[ifu_bp_ctl.scala 429:26] + node _T_6483 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 429:40] + node _T_6484 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6485 = eq(_T_6484, UInt<4>("h09")) @[ifu_bp_ctl.scala 429:109] + node _T_6486 = or(_T_6485, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6487 = and(_T_6483, _T_6486) @[ifu_bp_ctl.scala 429:44] + node _T_6488 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 430:40] + node _T_6489 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6490 = eq(_T_6489, UInt<4>("h09")) @[ifu_bp_ctl.scala 430:109] + node _T_6491 = or(_T_6490, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6492 = and(_T_6488, _T_6491) @[ifu_bp_ctl.scala 430:44] + node _T_6493 = or(_T_6487, _T_6492) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[1][9] <= _T_6493 @[ifu_bp_ctl.scala 429:26] + node _T_6494 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 429:40] + node _T_6495 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6496 = eq(_T_6495, UInt<4>("h0a")) @[ifu_bp_ctl.scala 429:109] + node _T_6497 = or(_T_6496, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6498 = and(_T_6494, _T_6497) @[ifu_bp_ctl.scala 429:44] + node _T_6499 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 430:40] + node _T_6500 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6501 = eq(_T_6500, UInt<4>("h0a")) @[ifu_bp_ctl.scala 430:109] + node _T_6502 = or(_T_6501, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6503 = and(_T_6499, _T_6502) @[ifu_bp_ctl.scala 430:44] + node _T_6504 = or(_T_6498, _T_6503) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[1][10] <= _T_6504 @[ifu_bp_ctl.scala 429:26] + node _T_6505 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 429:40] + node _T_6506 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6507 = eq(_T_6506, UInt<4>("h0b")) @[ifu_bp_ctl.scala 429:109] + node _T_6508 = or(_T_6507, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6509 = and(_T_6505, _T_6508) @[ifu_bp_ctl.scala 429:44] + node _T_6510 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 430:40] + node _T_6511 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6512 = eq(_T_6511, UInt<4>("h0b")) @[ifu_bp_ctl.scala 430:109] + node _T_6513 = or(_T_6512, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6514 = and(_T_6510, _T_6513) @[ifu_bp_ctl.scala 430:44] + node _T_6515 = or(_T_6509, _T_6514) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[1][11] <= _T_6515 @[ifu_bp_ctl.scala 429:26] + node _T_6516 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 429:40] + node _T_6517 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6518 = eq(_T_6517, UInt<4>("h0c")) @[ifu_bp_ctl.scala 429:109] + node _T_6519 = or(_T_6518, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6520 = and(_T_6516, _T_6519) @[ifu_bp_ctl.scala 429:44] + node _T_6521 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 430:40] + node _T_6522 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6523 = eq(_T_6522, UInt<4>("h0c")) @[ifu_bp_ctl.scala 430:109] + node _T_6524 = or(_T_6523, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6525 = and(_T_6521, _T_6524) @[ifu_bp_ctl.scala 430:44] + node _T_6526 = or(_T_6520, _T_6525) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[1][12] <= _T_6526 @[ifu_bp_ctl.scala 429:26] + node _T_6527 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 429:40] + node _T_6528 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6529 = eq(_T_6528, UInt<4>("h0d")) @[ifu_bp_ctl.scala 429:109] + node _T_6530 = or(_T_6529, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6531 = and(_T_6527, _T_6530) @[ifu_bp_ctl.scala 429:44] + node _T_6532 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 430:40] + node _T_6533 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6534 = eq(_T_6533, UInt<4>("h0d")) @[ifu_bp_ctl.scala 430:109] + node _T_6535 = or(_T_6534, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6536 = and(_T_6532, _T_6535) @[ifu_bp_ctl.scala 430:44] + node _T_6537 = or(_T_6531, _T_6536) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[1][13] <= _T_6537 @[ifu_bp_ctl.scala 429:26] + node _T_6538 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 429:40] + node _T_6539 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6540 = eq(_T_6539, UInt<4>("h0e")) @[ifu_bp_ctl.scala 429:109] + node _T_6541 = or(_T_6540, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6542 = and(_T_6538, _T_6541) @[ifu_bp_ctl.scala 429:44] + node _T_6543 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 430:40] + node _T_6544 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6545 = eq(_T_6544, UInt<4>("h0e")) @[ifu_bp_ctl.scala 430:109] + node _T_6546 = or(_T_6545, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6547 = and(_T_6543, _T_6546) @[ifu_bp_ctl.scala 430:44] + node _T_6548 = or(_T_6542, _T_6547) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[1][14] <= _T_6548 @[ifu_bp_ctl.scala 429:26] + node _T_6549 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 429:40] + node _T_6550 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 429:60] + node _T_6551 = eq(_T_6550, UInt<4>("h0f")) @[ifu_bp_ctl.scala 429:109] + node _T_6552 = or(_T_6551, UInt<1>("h00")) @[ifu_bp_ctl.scala 429:117] + node _T_6553 = and(_T_6549, _T_6552) @[ifu_bp_ctl.scala 429:44] + node _T_6554 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 430:40] + node _T_6555 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 430:60] + node _T_6556 = eq(_T_6555, UInt<4>("h0f")) @[ifu_bp_ctl.scala 430:109] + node _T_6557 = or(_T_6556, UInt<1>("h00")) @[ifu_bp_ctl.scala 430:117] + node _T_6558 = and(_T_6554, _T_6557) @[ifu_bp_ctl.scala 430:44] + node _T_6559 = or(_T_6553, _T_6558) @[ifu_bp_ctl.scala 429:142] + bht_bank_clken[1][15] <= _T_6559 @[ifu_bp_ctl.scala 429:26] + node _T_6560 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6561 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6562 = eq(_T_6561, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_6563 = and(_T_6560, _T_6562) @[ifu_bp_ctl.scala 435:23] + node _T_6564 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6565 = eq(_T_6564, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_6566 = and(_T_6563, _T_6565) @[ifu_bp_ctl.scala 435:81] + node _T_6567 = or(_T_6566, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6568 = bits(_T_6567, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_0_0 = mux(_T_6568, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6569 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6570 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6571 = eq(_T_6570, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_6572 = and(_T_6569, _T_6571) @[ifu_bp_ctl.scala 435:23] + node _T_6573 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6574 = eq(_T_6573, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_6575 = and(_T_6572, _T_6574) @[ifu_bp_ctl.scala 435:81] + node _T_6576 = or(_T_6575, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6577 = bits(_T_6576, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_0_1 = mux(_T_6577, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6578 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6579 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6580 = eq(_T_6579, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_6581 = and(_T_6578, _T_6580) @[ifu_bp_ctl.scala 435:23] + node _T_6582 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6583 = eq(_T_6582, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_6584 = and(_T_6581, _T_6583) @[ifu_bp_ctl.scala 435:81] + node _T_6585 = or(_T_6584, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6586 = bits(_T_6585, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_0_2 = mux(_T_6586, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6587 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6588 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6589 = eq(_T_6588, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_6590 = and(_T_6587, _T_6589) @[ifu_bp_ctl.scala 435:23] + node _T_6591 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6592 = eq(_T_6591, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_6593 = and(_T_6590, _T_6592) @[ifu_bp_ctl.scala 435:81] + node _T_6594 = or(_T_6593, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6595 = bits(_T_6594, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_0_3 = mux(_T_6595, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6596 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6597 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6598 = eq(_T_6597, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_6599 = and(_T_6596, _T_6598) @[ifu_bp_ctl.scala 435:23] + node _T_6600 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6601 = eq(_T_6600, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_6602 = and(_T_6599, _T_6601) @[ifu_bp_ctl.scala 435:81] + node _T_6603 = or(_T_6602, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6604 = bits(_T_6603, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_0_4 = mux(_T_6604, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6605 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6606 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6607 = eq(_T_6606, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_6608 = and(_T_6605, _T_6607) @[ifu_bp_ctl.scala 435:23] + node _T_6609 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6610 = eq(_T_6609, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_6611 = and(_T_6608, _T_6610) @[ifu_bp_ctl.scala 435:81] + node _T_6612 = or(_T_6611, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6613 = bits(_T_6612, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_0_5 = mux(_T_6613, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6614 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6615 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6616 = eq(_T_6615, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_6617 = and(_T_6614, _T_6616) @[ifu_bp_ctl.scala 435:23] + node _T_6618 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6619 = eq(_T_6618, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_6620 = and(_T_6617, _T_6619) @[ifu_bp_ctl.scala 435:81] + node _T_6621 = or(_T_6620, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6622 = bits(_T_6621, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_0_6 = mux(_T_6622, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6623 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6624 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6625 = eq(_T_6624, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_6626 = and(_T_6623, _T_6625) @[ifu_bp_ctl.scala 435:23] + node _T_6627 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6628 = eq(_T_6627, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_6629 = and(_T_6626, _T_6628) @[ifu_bp_ctl.scala 435:81] + node _T_6630 = or(_T_6629, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6631 = bits(_T_6630, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_0_7 = mux(_T_6631, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6632 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6633 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6634 = eq(_T_6633, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_6635 = and(_T_6632, _T_6634) @[ifu_bp_ctl.scala 435:23] + node _T_6636 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6637 = eq(_T_6636, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_6638 = and(_T_6635, _T_6637) @[ifu_bp_ctl.scala 435:81] + node _T_6639 = or(_T_6638, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6640 = bits(_T_6639, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_0_8 = mux(_T_6640, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6641 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6642 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6643 = eq(_T_6642, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_6644 = and(_T_6641, _T_6643) @[ifu_bp_ctl.scala 435:23] + node _T_6645 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6646 = eq(_T_6645, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_6647 = and(_T_6644, _T_6646) @[ifu_bp_ctl.scala 435:81] + node _T_6648 = or(_T_6647, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6649 = bits(_T_6648, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_0_9 = mux(_T_6649, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6650 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6651 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6652 = eq(_T_6651, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_6653 = and(_T_6650, _T_6652) @[ifu_bp_ctl.scala 435:23] + node _T_6654 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6655 = eq(_T_6654, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_6656 = and(_T_6653, _T_6655) @[ifu_bp_ctl.scala 435:81] + node _T_6657 = or(_T_6656, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6658 = bits(_T_6657, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_0_10 = mux(_T_6658, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6659 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6660 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6661 = eq(_T_6660, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_6662 = and(_T_6659, _T_6661) @[ifu_bp_ctl.scala 435:23] + node _T_6663 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6664 = eq(_T_6663, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_6665 = and(_T_6662, _T_6664) @[ifu_bp_ctl.scala 435:81] + node _T_6666 = or(_T_6665, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6667 = bits(_T_6666, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_0_11 = mux(_T_6667, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6668 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6669 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6670 = eq(_T_6669, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_6671 = and(_T_6668, _T_6670) @[ifu_bp_ctl.scala 435:23] + node _T_6672 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6673 = eq(_T_6672, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_6674 = and(_T_6671, _T_6673) @[ifu_bp_ctl.scala 435:81] + node _T_6675 = or(_T_6674, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6676 = bits(_T_6675, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_0_12 = mux(_T_6676, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6677 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6678 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6679 = eq(_T_6678, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_6680 = and(_T_6677, _T_6679) @[ifu_bp_ctl.scala 435:23] + node _T_6681 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6682 = eq(_T_6681, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_6683 = and(_T_6680, _T_6682) @[ifu_bp_ctl.scala 435:81] + node _T_6684 = or(_T_6683, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6685 = bits(_T_6684, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_0_13 = mux(_T_6685, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6686 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6687 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6688 = eq(_T_6687, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_6689 = and(_T_6686, _T_6688) @[ifu_bp_ctl.scala 435:23] + node _T_6690 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6691 = eq(_T_6690, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_6692 = and(_T_6689, _T_6691) @[ifu_bp_ctl.scala 435:81] + node _T_6693 = or(_T_6692, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6694 = bits(_T_6693, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_0_14 = mux(_T_6694, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6695 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6696 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6697 = eq(_T_6696, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_6698 = and(_T_6695, _T_6697) @[ifu_bp_ctl.scala 435:23] + node _T_6699 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6700 = eq(_T_6699, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_6701 = and(_T_6698, _T_6700) @[ifu_bp_ctl.scala 435:81] + node _T_6702 = or(_T_6701, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6703 = bits(_T_6702, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_0_15 = mux(_T_6703, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6704 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6705 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6706 = eq(_T_6705, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_6707 = and(_T_6704, _T_6706) @[ifu_bp_ctl.scala 435:23] + node _T_6708 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6709 = eq(_T_6708, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_6710 = and(_T_6707, _T_6709) @[ifu_bp_ctl.scala 435:81] + node _T_6711 = or(_T_6710, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6712 = bits(_T_6711, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_1_0 = mux(_T_6712, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6713 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6714 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6715 = eq(_T_6714, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_6716 = and(_T_6713, _T_6715) @[ifu_bp_ctl.scala 435:23] + node _T_6717 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6718 = eq(_T_6717, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_6719 = and(_T_6716, _T_6718) @[ifu_bp_ctl.scala 435:81] + node _T_6720 = or(_T_6719, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6721 = bits(_T_6720, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_1_1 = mux(_T_6721, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6722 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6723 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6724 = eq(_T_6723, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_6725 = and(_T_6722, _T_6724) @[ifu_bp_ctl.scala 435:23] + node _T_6726 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6727 = eq(_T_6726, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_6728 = and(_T_6725, _T_6727) @[ifu_bp_ctl.scala 435:81] + node _T_6729 = or(_T_6728, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6730 = bits(_T_6729, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_1_2 = mux(_T_6730, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6731 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6732 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6733 = eq(_T_6732, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_6734 = and(_T_6731, _T_6733) @[ifu_bp_ctl.scala 435:23] + node _T_6735 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6736 = eq(_T_6735, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_6737 = and(_T_6734, _T_6736) @[ifu_bp_ctl.scala 435:81] + node _T_6738 = or(_T_6737, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6739 = bits(_T_6738, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_1_3 = mux(_T_6739, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6740 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6741 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6742 = eq(_T_6741, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_6743 = and(_T_6740, _T_6742) @[ifu_bp_ctl.scala 435:23] + node _T_6744 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6745 = eq(_T_6744, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_6746 = and(_T_6743, _T_6745) @[ifu_bp_ctl.scala 435:81] + node _T_6747 = or(_T_6746, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6748 = bits(_T_6747, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_1_4 = mux(_T_6748, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6749 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6750 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6751 = eq(_T_6750, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_6752 = and(_T_6749, _T_6751) @[ifu_bp_ctl.scala 435:23] + node _T_6753 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6754 = eq(_T_6753, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_6755 = and(_T_6752, _T_6754) @[ifu_bp_ctl.scala 435:81] + node _T_6756 = or(_T_6755, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6757 = bits(_T_6756, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_1_5 = mux(_T_6757, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6758 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6759 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6760 = eq(_T_6759, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_6761 = and(_T_6758, _T_6760) @[ifu_bp_ctl.scala 435:23] + node _T_6762 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6763 = eq(_T_6762, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_6764 = and(_T_6761, _T_6763) @[ifu_bp_ctl.scala 435:81] + node _T_6765 = or(_T_6764, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6766 = bits(_T_6765, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_1_6 = mux(_T_6766, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6767 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6768 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6769 = eq(_T_6768, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_6770 = and(_T_6767, _T_6769) @[ifu_bp_ctl.scala 435:23] + node _T_6771 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6772 = eq(_T_6771, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_6773 = and(_T_6770, _T_6772) @[ifu_bp_ctl.scala 435:81] + node _T_6774 = or(_T_6773, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6775 = bits(_T_6774, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_1_7 = mux(_T_6775, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6776 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6777 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6778 = eq(_T_6777, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_6779 = and(_T_6776, _T_6778) @[ifu_bp_ctl.scala 435:23] + node _T_6780 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6781 = eq(_T_6780, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_6782 = and(_T_6779, _T_6781) @[ifu_bp_ctl.scala 435:81] + node _T_6783 = or(_T_6782, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6784 = bits(_T_6783, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_1_8 = mux(_T_6784, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6785 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6786 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6787 = eq(_T_6786, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_6788 = and(_T_6785, _T_6787) @[ifu_bp_ctl.scala 435:23] + node _T_6789 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6790 = eq(_T_6789, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_6791 = and(_T_6788, _T_6790) @[ifu_bp_ctl.scala 435:81] + node _T_6792 = or(_T_6791, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6793 = bits(_T_6792, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_1_9 = mux(_T_6793, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6794 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6795 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6796 = eq(_T_6795, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_6797 = and(_T_6794, _T_6796) @[ifu_bp_ctl.scala 435:23] + node _T_6798 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6799 = eq(_T_6798, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_6800 = and(_T_6797, _T_6799) @[ifu_bp_ctl.scala 435:81] + node _T_6801 = or(_T_6800, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6802 = bits(_T_6801, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_1_10 = mux(_T_6802, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6803 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6804 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6805 = eq(_T_6804, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_6806 = and(_T_6803, _T_6805) @[ifu_bp_ctl.scala 435:23] + node _T_6807 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6808 = eq(_T_6807, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_6809 = and(_T_6806, _T_6808) @[ifu_bp_ctl.scala 435:81] + node _T_6810 = or(_T_6809, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6811 = bits(_T_6810, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_1_11 = mux(_T_6811, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6812 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6813 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6814 = eq(_T_6813, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_6815 = and(_T_6812, _T_6814) @[ifu_bp_ctl.scala 435:23] + node _T_6816 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6817 = eq(_T_6816, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_6818 = and(_T_6815, _T_6817) @[ifu_bp_ctl.scala 435:81] + node _T_6819 = or(_T_6818, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6820 = bits(_T_6819, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_1_12 = mux(_T_6820, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6821 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6822 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6823 = eq(_T_6822, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_6824 = and(_T_6821, _T_6823) @[ifu_bp_ctl.scala 435:23] + node _T_6825 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6826 = eq(_T_6825, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_6827 = and(_T_6824, _T_6826) @[ifu_bp_ctl.scala 435:81] + node _T_6828 = or(_T_6827, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6829 = bits(_T_6828, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_1_13 = mux(_T_6829, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6830 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6831 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6832 = eq(_T_6831, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_6833 = and(_T_6830, _T_6832) @[ifu_bp_ctl.scala 435:23] + node _T_6834 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6835 = eq(_T_6834, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_6836 = and(_T_6833, _T_6835) @[ifu_bp_ctl.scala 435:81] + node _T_6837 = or(_T_6836, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6838 = bits(_T_6837, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_1_14 = mux(_T_6838, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6839 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6840 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6841 = eq(_T_6840, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_6842 = and(_T_6839, _T_6841) @[ifu_bp_ctl.scala 435:23] + node _T_6843 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6844 = eq(_T_6843, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_6845 = and(_T_6842, _T_6844) @[ifu_bp_ctl.scala 435:81] + node _T_6846 = or(_T_6845, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6847 = bits(_T_6846, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_1_15 = mux(_T_6847, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6848 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6849 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6850 = eq(_T_6849, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_6851 = and(_T_6848, _T_6850) @[ifu_bp_ctl.scala 435:23] + node _T_6852 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6853 = eq(_T_6852, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_6854 = and(_T_6851, _T_6853) @[ifu_bp_ctl.scala 435:81] + node _T_6855 = or(_T_6854, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6856 = bits(_T_6855, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_2_0 = mux(_T_6856, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6857 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6858 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6859 = eq(_T_6858, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_6860 = and(_T_6857, _T_6859) @[ifu_bp_ctl.scala 435:23] + node _T_6861 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6862 = eq(_T_6861, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_6863 = and(_T_6860, _T_6862) @[ifu_bp_ctl.scala 435:81] + node _T_6864 = or(_T_6863, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6865 = bits(_T_6864, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_2_1 = mux(_T_6865, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6866 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6867 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6868 = eq(_T_6867, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_6869 = and(_T_6866, _T_6868) @[ifu_bp_ctl.scala 435:23] + node _T_6870 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6871 = eq(_T_6870, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_6872 = and(_T_6869, _T_6871) @[ifu_bp_ctl.scala 435:81] + node _T_6873 = or(_T_6872, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6874 = bits(_T_6873, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_2_2 = mux(_T_6874, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6875 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6876 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6877 = eq(_T_6876, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_6878 = and(_T_6875, _T_6877) @[ifu_bp_ctl.scala 435:23] + node _T_6879 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6880 = eq(_T_6879, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_6881 = and(_T_6878, _T_6880) @[ifu_bp_ctl.scala 435:81] + node _T_6882 = or(_T_6881, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6883 = bits(_T_6882, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_2_3 = mux(_T_6883, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6884 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6885 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6886 = eq(_T_6885, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_6887 = and(_T_6884, _T_6886) @[ifu_bp_ctl.scala 435:23] + node _T_6888 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6889 = eq(_T_6888, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_6890 = and(_T_6887, _T_6889) @[ifu_bp_ctl.scala 435:81] + node _T_6891 = or(_T_6890, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6892 = bits(_T_6891, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_2_4 = mux(_T_6892, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6893 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6894 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6895 = eq(_T_6894, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_6896 = and(_T_6893, _T_6895) @[ifu_bp_ctl.scala 435:23] + node _T_6897 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6898 = eq(_T_6897, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_6899 = and(_T_6896, _T_6898) @[ifu_bp_ctl.scala 435:81] + node _T_6900 = or(_T_6899, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6901 = bits(_T_6900, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_2_5 = mux(_T_6901, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6902 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6903 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6904 = eq(_T_6903, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_6905 = and(_T_6902, _T_6904) @[ifu_bp_ctl.scala 435:23] + node _T_6906 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6907 = eq(_T_6906, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_6908 = and(_T_6905, _T_6907) @[ifu_bp_ctl.scala 435:81] + node _T_6909 = or(_T_6908, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6910 = bits(_T_6909, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_2_6 = mux(_T_6910, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6911 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6912 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6913 = eq(_T_6912, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_6914 = and(_T_6911, _T_6913) @[ifu_bp_ctl.scala 435:23] + node _T_6915 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6916 = eq(_T_6915, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_6917 = and(_T_6914, _T_6916) @[ifu_bp_ctl.scala 435:81] + node _T_6918 = or(_T_6917, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6919 = bits(_T_6918, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_2_7 = mux(_T_6919, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6920 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6921 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6922 = eq(_T_6921, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_6923 = and(_T_6920, _T_6922) @[ifu_bp_ctl.scala 435:23] + node _T_6924 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6925 = eq(_T_6924, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_6926 = and(_T_6923, _T_6925) @[ifu_bp_ctl.scala 435:81] + node _T_6927 = or(_T_6926, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6928 = bits(_T_6927, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_2_8 = mux(_T_6928, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6929 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6930 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6931 = eq(_T_6930, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_6932 = and(_T_6929, _T_6931) @[ifu_bp_ctl.scala 435:23] + node _T_6933 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6934 = eq(_T_6933, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_6935 = and(_T_6932, _T_6934) @[ifu_bp_ctl.scala 435:81] + node _T_6936 = or(_T_6935, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6937 = bits(_T_6936, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_2_9 = mux(_T_6937, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6938 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6939 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6940 = eq(_T_6939, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_6941 = and(_T_6938, _T_6940) @[ifu_bp_ctl.scala 435:23] + node _T_6942 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6943 = eq(_T_6942, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_6944 = and(_T_6941, _T_6943) @[ifu_bp_ctl.scala 435:81] + node _T_6945 = or(_T_6944, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6946 = bits(_T_6945, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_2_10 = mux(_T_6946, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6947 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6948 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6949 = eq(_T_6948, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_6950 = and(_T_6947, _T_6949) @[ifu_bp_ctl.scala 435:23] + node _T_6951 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6952 = eq(_T_6951, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_6953 = and(_T_6950, _T_6952) @[ifu_bp_ctl.scala 435:81] + node _T_6954 = or(_T_6953, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6955 = bits(_T_6954, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_2_11 = mux(_T_6955, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6956 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6957 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6958 = eq(_T_6957, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_6959 = and(_T_6956, _T_6958) @[ifu_bp_ctl.scala 435:23] + node _T_6960 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6961 = eq(_T_6960, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_6962 = and(_T_6959, _T_6961) @[ifu_bp_ctl.scala 435:81] + node _T_6963 = or(_T_6962, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6964 = bits(_T_6963, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_2_12 = mux(_T_6964, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6965 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6966 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6967 = eq(_T_6966, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_6968 = and(_T_6965, _T_6967) @[ifu_bp_ctl.scala 435:23] + node _T_6969 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6970 = eq(_T_6969, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_6971 = and(_T_6968, _T_6970) @[ifu_bp_ctl.scala 435:81] + node _T_6972 = or(_T_6971, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6973 = bits(_T_6972, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_2_13 = mux(_T_6973, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6974 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6975 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6976 = eq(_T_6975, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_6977 = and(_T_6974, _T_6976) @[ifu_bp_ctl.scala 435:23] + node _T_6978 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6979 = eq(_T_6978, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_6980 = and(_T_6977, _T_6979) @[ifu_bp_ctl.scala 435:81] + node _T_6981 = or(_T_6980, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6982 = bits(_T_6981, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_2_14 = mux(_T_6982, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6983 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6984 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6985 = eq(_T_6984, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_6986 = and(_T_6983, _T_6985) @[ifu_bp_ctl.scala 435:23] + node _T_6987 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6988 = eq(_T_6987, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_6989 = and(_T_6986, _T_6988) @[ifu_bp_ctl.scala 435:81] + node _T_6990 = or(_T_6989, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_6991 = bits(_T_6990, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_2_15 = mux(_T_6991, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_6992 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_6993 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_6994 = eq(_T_6993, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_6995 = and(_T_6992, _T_6994) @[ifu_bp_ctl.scala 435:23] + node _T_6996 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_6997 = eq(_T_6996, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_6998 = and(_T_6995, _T_6997) @[ifu_bp_ctl.scala 435:81] + node _T_6999 = or(_T_6998, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7000 = bits(_T_6999, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_3_0 = mux(_T_7000, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7001 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7002 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7003 = eq(_T_7002, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_7004 = and(_T_7001, _T_7003) @[ifu_bp_ctl.scala 435:23] + node _T_7005 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7006 = eq(_T_7005, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_7007 = and(_T_7004, _T_7006) @[ifu_bp_ctl.scala 435:81] + node _T_7008 = or(_T_7007, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7009 = bits(_T_7008, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_3_1 = mux(_T_7009, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7010 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7011 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7012 = eq(_T_7011, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_7013 = and(_T_7010, _T_7012) @[ifu_bp_ctl.scala 435:23] + node _T_7014 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7015 = eq(_T_7014, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_7016 = and(_T_7013, _T_7015) @[ifu_bp_ctl.scala 435:81] + node _T_7017 = or(_T_7016, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7018 = bits(_T_7017, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_3_2 = mux(_T_7018, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7019 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7020 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7021 = eq(_T_7020, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_7022 = and(_T_7019, _T_7021) @[ifu_bp_ctl.scala 435:23] + node _T_7023 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7024 = eq(_T_7023, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_7025 = and(_T_7022, _T_7024) @[ifu_bp_ctl.scala 435:81] + node _T_7026 = or(_T_7025, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7027 = bits(_T_7026, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_3_3 = mux(_T_7027, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7028 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7029 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7030 = eq(_T_7029, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_7031 = and(_T_7028, _T_7030) @[ifu_bp_ctl.scala 435:23] + node _T_7032 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7033 = eq(_T_7032, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_7034 = and(_T_7031, _T_7033) @[ifu_bp_ctl.scala 435:81] + node _T_7035 = or(_T_7034, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7036 = bits(_T_7035, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_3_4 = mux(_T_7036, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7037 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7038 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7039 = eq(_T_7038, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_7040 = and(_T_7037, _T_7039) @[ifu_bp_ctl.scala 435:23] + node _T_7041 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7042 = eq(_T_7041, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_7043 = and(_T_7040, _T_7042) @[ifu_bp_ctl.scala 435:81] + node _T_7044 = or(_T_7043, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7045 = bits(_T_7044, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_3_5 = mux(_T_7045, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7046 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7047 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7048 = eq(_T_7047, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_7049 = and(_T_7046, _T_7048) @[ifu_bp_ctl.scala 435:23] + node _T_7050 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7051 = eq(_T_7050, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_7052 = and(_T_7049, _T_7051) @[ifu_bp_ctl.scala 435:81] + node _T_7053 = or(_T_7052, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7054 = bits(_T_7053, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_3_6 = mux(_T_7054, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7055 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7056 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7057 = eq(_T_7056, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_7058 = and(_T_7055, _T_7057) @[ifu_bp_ctl.scala 435:23] + node _T_7059 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7060 = eq(_T_7059, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_7061 = and(_T_7058, _T_7060) @[ifu_bp_ctl.scala 435:81] + node _T_7062 = or(_T_7061, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7063 = bits(_T_7062, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_3_7 = mux(_T_7063, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7064 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7065 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7066 = eq(_T_7065, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_7067 = and(_T_7064, _T_7066) @[ifu_bp_ctl.scala 435:23] + node _T_7068 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7069 = eq(_T_7068, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_7070 = and(_T_7067, _T_7069) @[ifu_bp_ctl.scala 435:81] + node _T_7071 = or(_T_7070, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7072 = bits(_T_7071, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_3_8 = mux(_T_7072, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7073 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7074 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7075 = eq(_T_7074, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_7076 = and(_T_7073, _T_7075) @[ifu_bp_ctl.scala 435:23] + node _T_7077 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7078 = eq(_T_7077, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_7079 = and(_T_7076, _T_7078) @[ifu_bp_ctl.scala 435:81] + node _T_7080 = or(_T_7079, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7081 = bits(_T_7080, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_3_9 = mux(_T_7081, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7082 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7083 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7084 = eq(_T_7083, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_7085 = and(_T_7082, _T_7084) @[ifu_bp_ctl.scala 435:23] + node _T_7086 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7087 = eq(_T_7086, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_7088 = and(_T_7085, _T_7087) @[ifu_bp_ctl.scala 435:81] + node _T_7089 = or(_T_7088, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7090 = bits(_T_7089, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_3_10 = mux(_T_7090, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7091 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7092 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7093 = eq(_T_7092, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_7094 = and(_T_7091, _T_7093) @[ifu_bp_ctl.scala 435:23] + node _T_7095 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7096 = eq(_T_7095, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_7097 = and(_T_7094, _T_7096) @[ifu_bp_ctl.scala 435:81] + node _T_7098 = or(_T_7097, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7099 = bits(_T_7098, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_3_11 = mux(_T_7099, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7100 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7101 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7102 = eq(_T_7101, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_7103 = and(_T_7100, _T_7102) @[ifu_bp_ctl.scala 435:23] + node _T_7104 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7105 = eq(_T_7104, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_7106 = and(_T_7103, _T_7105) @[ifu_bp_ctl.scala 435:81] + node _T_7107 = or(_T_7106, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7108 = bits(_T_7107, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_3_12 = mux(_T_7108, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7109 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7110 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7111 = eq(_T_7110, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_7112 = and(_T_7109, _T_7111) @[ifu_bp_ctl.scala 435:23] + node _T_7113 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7114 = eq(_T_7113, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_7115 = and(_T_7112, _T_7114) @[ifu_bp_ctl.scala 435:81] + node _T_7116 = or(_T_7115, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7117 = bits(_T_7116, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_3_13 = mux(_T_7117, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7118 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7119 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7120 = eq(_T_7119, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_7121 = and(_T_7118, _T_7120) @[ifu_bp_ctl.scala 435:23] + node _T_7122 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7123 = eq(_T_7122, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_7124 = and(_T_7121, _T_7123) @[ifu_bp_ctl.scala 435:81] + node _T_7125 = or(_T_7124, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7126 = bits(_T_7125, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_3_14 = mux(_T_7126, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7127 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7128 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7129 = eq(_T_7128, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_7130 = and(_T_7127, _T_7129) @[ifu_bp_ctl.scala 435:23] + node _T_7131 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7132 = eq(_T_7131, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_7133 = and(_T_7130, _T_7132) @[ifu_bp_ctl.scala 435:81] + node _T_7134 = or(_T_7133, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7135 = bits(_T_7134, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_3_15 = mux(_T_7135, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7136 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7137 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7138 = eq(_T_7137, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_7139 = and(_T_7136, _T_7138) @[ifu_bp_ctl.scala 435:23] + node _T_7140 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7141 = eq(_T_7140, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_7142 = and(_T_7139, _T_7141) @[ifu_bp_ctl.scala 435:81] + node _T_7143 = or(_T_7142, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7144 = bits(_T_7143, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_4_0 = mux(_T_7144, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7145 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7146 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7147 = eq(_T_7146, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_7148 = and(_T_7145, _T_7147) @[ifu_bp_ctl.scala 435:23] + node _T_7149 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7150 = eq(_T_7149, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_7151 = and(_T_7148, _T_7150) @[ifu_bp_ctl.scala 435:81] + node _T_7152 = or(_T_7151, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7153 = bits(_T_7152, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_4_1 = mux(_T_7153, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7154 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7155 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7156 = eq(_T_7155, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_7157 = and(_T_7154, _T_7156) @[ifu_bp_ctl.scala 435:23] + node _T_7158 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7159 = eq(_T_7158, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_7160 = and(_T_7157, _T_7159) @[ifu_bp_ctl.scala 435:81] + node _T_7161 = or(_T_7160, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7162 = bits(_T_7161, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_4_2 = mux(_T_7162, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7163 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7164 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7165 = eq(_T_7164, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_7166 = and(_T_7163, _T_7165) @[ifu_bp_ctl.scala 435:23] + node _T_7167 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7168 = eq(_T_7167, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_7169 = and(_T_7166, _T_7168) @[ifu_bp_ctl.scala 435:81] + node _T_7170 = or(_T_7169, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7171 = bits(_T_7170, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_4_3 = mux(_T_7171, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7172 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7173 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7174 = eq(_T_7173, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_7175 = and(_T_7172, _T_7174) @[ifu_bp_ctl.scala 435:23] + node _T_7176 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7177 = eq(_T_7176, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_7178 = and(_T_7175, _T_7177) @[ifu_bp_ctl.scala 435:81] + node _T_7179 = or(_T_7178, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7180 = bits(_T_7179, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_4_4 = mux(_T_7180, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7181 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7182 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7183 = eq(_T_7182, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_7184 = and(_T_7181, _T_7183) @[ifu_bp_ctl.scala 435:23] + node _T_7185 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7186 = eq(_T_7185, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_7187 = and(_T_7184, _T_7186) @[ifu_bp_ctl.scala 435:81] + node _T_7188 = or(_T_7187, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7189 = bits(_T_7188, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_4_5 = mux(_T_7189, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7190 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7191 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7192 = eq(_T_7191, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_7193 = and(_T_7190, _T_7192) @[ifu_bp_ctl.scala 435:23] + node _T_7194 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7195 = eq(_T_7194, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_7196 = and(_T_7193, _T_7195) @[ifu_bp_ctl.scala 435:81] + node _T_7197 = or(_T_7196, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7198 = bits(_T_7197, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_4_6 = mux(_T_7198, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7199 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7200 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7201 = eq(_T_7200, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_7202 = and(_T_7199, _T_7201) @[ifu_bp_ctl.scala 435:23] + node _T_7203 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7204 = eq(_T_7203, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_7205 = and(_T_7202, _T_7204) @[ifu_bp_ctl.scala 435:81] + node _T_7206 = or(_T_7205, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7207 = bits(_T_7206, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_4_7 = mux(_T_7207, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7208 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7209 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7210 = eq(_T_7209, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_7211 = and(_T_7208, _T_7210) @[ifu_bp_ctl.scala 435:23] + node _T_7212 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7213 = eq(_T_7212, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_7214 = and(_T_7211, _T_7213) @[ifu_bp_ctl.scala 435:81] + node _T_7215 = or(_T_7214, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7216 = bits(_T_7215, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_4_8 = mux(_T_7216, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7217 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7218 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7219 = eq(_T_7218, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_7220 = and(_T_7217, _T_7219) @[ifu_bp_ctl.scala 435:23] + node _T_7221 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7222 = eq(_T_7221, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_7223 = and(_T_7220, _T_7222) @[ifu_bp_ctl.scala 435:81] + node _T_7224 = or(_T_7223, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7225 = bits(_T_7224, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_4_9 = mux(_T_7225, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7226 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7227 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7228 = eq(_T_7227, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_7229 = and(_T_7226, _T_7228) @[ifu_bp_ctl.scala 435:23] + node _T_7230 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7231 = eq(_T_7230, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_7232 = and(_T_7229, _T_7231) @[ifu_bp_ctl.scala 435:81] + node _T_7233 = or(_T_7232, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7234 = bits(_T_7233, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_4_10 = mux(_T_7234, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7235 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7236 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7237 = eq(_T_7236, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_7238 = and(_T_7235, _T_7237) @[ifu_bp_ctl.scala 435:23] + node _T_7239 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7240 = eq(_T_7239, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_7241 = and(_T_7238, _T_7240) @[ifu_bp_ctl.scala 435:81] + node _T_7242 = or(_T_7241, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7243 = bits(_T_7242, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_4_11 = mux(_T_7243, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7244 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7245 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7246 = eq(_T_7245, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_7247 = and(_T_7244, _T_7246) @[ifu_bp_ctl.scala 435:23] + node _T_7248 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7249 = eq(_T_7248, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_7250 = and(_T_7247, _T_7249) @[ifu_bp_ctl.scala 435:81] + node _T_7251 = or(_T_7250, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7252 = bits(_T_7251, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_4_12 = mux(_T_7252, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7253 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7254 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7255 = eq(_T_7254, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_7256 = and(_T_7253, _T_7255) @[ifu_bp_ctl.scala 435:23] + node _T_7257 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7258 = eq(_T_7257, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_7259 = and(_T_7256, _T_7258) @[ifu_bp_ctl.scala 435:81] + node _T_7260 = or(_T_7259, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7261 = bits(_T_7260, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_4_13 = mux(_T_7261, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7262 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7263 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7264 = eq(_T_7263, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_7265 = and(_T_7262, _T_7264) @[ifu_bp_ctl.scala 435:23] + node _T_7266 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7267 = eq(_T_7266, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_7268 = and(_T_7265, _T_7267) @[ifu_bp_ctl.scala 435:81] + node _T_7269 = or(_T_7268, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7270 = bits(_T_7269, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_4_14 = mux(_T_7270, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7271 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7272 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7273 = eq(_T_7272, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_7274 = and(_T_7271, _T_7273) @[ifu_bp_ctl.scala 435:23] + node _T_7275 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7276 = eq(_T_7275, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_7277 = and(_T_7274, _T_7276) @[ifu_bp_ctl.scala 435:81] + node _T_7278 = or(_T_7277, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7279 = bits(_T_7278, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_4_15 = mux(_T_7279, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7280 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7281 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7282 = eq(_T_7281, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_7283 = and(_T_7280, _T_7282) @[ifu_bp_ctl.scala 435:23] + node _T_7284 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7285 = eq(_T_7284, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_7286 = and(_T_7283, _T_7285) @[ifu_bp_ctl.scala 435:81] + node _T_7287 = or(_T_7286, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7288 = bits(_T_7287, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_5_0 = mux(_T_7288, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7289 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7290 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7291 = eq(_T_7290, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_7292 = and(_T_7289, _T_7291) @[ifu_bp_ctl.scala 435:23] + node _T_7293 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7294 = eq(_T_7293, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_7295 = and(_T_7292, _T_7294) @[ifu_bp_ctl.scala 435:81] + node _T_7296 = or(_T_7295, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7297 = bits(_T_7296, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_5_1 = mux(_T_7297, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7298 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7299 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7300 = eq(_T_7299, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_7301 = and(_T_7298, _T_7300) @[ifu_bp_ctl.scala 435:23] + node _T_7302 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7303 = eq(_T_7302, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_7304 = and(_T_7301, _T_7303) @[ifu_bp_ctl.scala 435:81] + node _T_7305 = or(_T_7304, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7306 = bits(_T_7305, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_5_2 = mux(_T_7306, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7307 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7308 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7309 = eq(_T_7308, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_7310 = and(_T_7307, _T_7309) @[ifu_bp_ctl.scala 435:23] + node _T_7311 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7312 = eq(_T_7311, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_7313 = and(_T_7310, _T_7312) @[ifu_bp_ctl.scala 435:81] + node _T_7314 = or(_T_7313, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7315 = bits(_T_7314, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_5_3 = mux(_T_7315, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7316 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7317 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7318 = eq(_T_7317, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_7319 = and(_T_7316, _T_7318) @[ifu_bp_ctl.scala 435:23] + node _T_7320 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7321 = eq(_T_7320, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_7322 = and(_T_7319, _T_7321) @[ifu_bp_ctl.scala 435:81] + node _T_7323 = or(_T_7322, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7324 = bits(_T_7323, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_5_4 = mux(_T_7324, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7325 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7326 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7327 = eq(_T_7326, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_7328 = and(_T_7325, _T_7327) @[ifu_bp_ctl.scala 435:23] + node _T_7329 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7330 = eq(_T_7329, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_7331 = and(_T_7328, _T_7330) @[ifu_bp_ctl.scala 435:81] + node _T_7332 = or(_T_7331, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7333 = bits(_T_7332, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_5_5 = mux(_T_7333, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7334 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7335 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7336 = eq(_T_7335, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_7337 = and(_T_7334, _T_7336) @[ifu_bp_ctl.scala 435:23] + node _T_7338 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7339 = eq(_T_7338, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_7340 = and(_T_7337, _T_7339) @[ifu_bp_ctl.scala 435:81] + node _T_7341 = or(_T_7340, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7342 = bits(_T_7341, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_5_6 = mux(_T_7342, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7343 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7344 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7345 = eq(_T_7344, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_7346 = and(_T_7343, _T_7345) @[ifu_bp_ctl.scala 435:23] + node _T_7347 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7348 = eq(_T_7347, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_7349 = and(_T_7346, _T_7348) @[ifu_bp_ctl.scala 435:81] + node _T_7350 = or(_T_7349, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7351 = bits(_T_7350, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_5_7 = mux(_T_7351, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7352 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7353 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7354 = eq(_T_7353, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_7355 = and(_T_7352, _T_7354) @[ifu_bp_ctl.scala 435:23] + node _T_7356 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7357 = eq(_T_7356, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_7358 = and(_T_7355, _T_7357) @[ifu_bp_ctl.scala 435:81] + node _T_7359 = or(_T_7358, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7360 = bits(_T_7359, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_5_8 = mux(_T_7360, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7361 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7362 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7363 = eq(_T_7362, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_7364 = and(_T_7361, _T_7363) @[ifu_bp_ctl.scala 435:23] + node _T_7365 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7366 = eq(_T_7365, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_7367 = and(_T_7364, _T_7366) @[ifu_bp_ctl.scala 435:81] + node _T_7368 = or(_T_7367, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7369 = bits(_T_7368, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_5_9 = mux(_T_7369, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7370 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7371 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7372 = eq(_T_7371, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_7373 = and(_T_7370, _T_7372) @[ifu_bp_ctl.scala 435:23] + node _T_7374 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7375 = eq(_T_7374, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_7376 = and(_T_7373, _T_7375) @[ifu_bp_ctl.scala 435:81] + node _T_7377 = or(_T_7376, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7378 = bits(_T_7377, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_5_10 = mux(_T_7378, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7379 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7380 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7381 = eq(_T_7380, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_7382 = and(_T_7379, _T_7381) @[ifu_bp_ctl.scala 435:23] + node _T_7383 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7384 = eq(_T_7383, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_7385 = and(_T_7382, _T_7384) @[ifu_bp_ctl.scala 435:81] + node _T_7386 = or(_T_7385, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7387 = bits(_T_7386, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_5_11 = mux(_T_7387, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7388 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7389 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7390 = eq(_T_7389, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_7391 = and(_T_7388, _T_7390) @[ifu_bp_ctl.scala 435:23] + node _T_7392 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7393 = eq(_T_7392, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_7394 = and(_T_7391, _T_7393) @[ifu_bp_ctl.scala 435:81] + node _T_7395 = or(_T_7394, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7396 = bits(_T_7395, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_5_12 = mux(_T_7396, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7397 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7398 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7399 = eq(_T_7398, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_7400 = and(_T_7397, _T_7399) @[ifu_bp_ctl.scala 435:23] + node _T_7401 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7402 = eq(_T_7401, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_7403 = and(_T_7400, _T_7402) @[ifu_bp_ctl.scala 435:81] + node _T_7404 = or(_T_7403, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7405 = bits(_T_7404, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_5_13 = mux(_T_7405, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7406 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7407 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7408 = eq(_T_7407, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_7409 = and(_T_7406, _T_7408) @[ifu_bp_ctl.scala 435:23] + node _T_7410 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7411 = eq(_T_7410, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_7412 = and(_T_7409, _T_7411) @[ifu_bp_ctl.scala 435:81] + node _T_7413 = or(_T_7412, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7414 = bits(_T_7413, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_5_14 = mux(_T_7414, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7415 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7416 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7417 = eq(_T_7416, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_7418 = and(_T_7415, _T_7417) @[ifu_bp_ctl.scala 435:23] + node _T_7419 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7420 = eq(_T_7419, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_7421 = and(_T_7418, _T_7420) @[ifu_bp_ctl.scala 435:81] + node _T_7422 = or(_T_7421, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7423 = bits(_T_7422, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_5_15 = mux(_T_7423, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7424 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7425 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7426 = eq(_T_7425, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_7427 = and(_T_7424, _T_7426) @[ifu_bp_ctl.scala 435:23] + node _T_7428 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7429 = eq(_T_7428, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_7430 = and(_T_7427, _T_7429) @[ifu_bp_ctl.scala 435:81] + node _T_7431 = or(_T_7430, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7432 = bits(_T_7431, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_6_0 = mux(_T_7432, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7433 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7434 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7435 = eq(_T_7434, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_7436 = and(_T_7433, _T_7435) @[ifu_bp_ctl.scala 435:23] + node _T_7437 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7438 = eq(_T_7437, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_7439 = and(_T_7436, _T_7438) @[ifu_bp_ctl.scala 435:81] + node _T_7440 = or(_T_7439, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7441 = bits(_T_7440, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_6_1 = mux(_T_7441, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7442 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7443 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7444 = eq(_T_7443, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_7445 = and(_T_7442, _T_7444) @[ifu_bp_ctl.scala 435:23] + node _T_7446 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7447 = eq(_T_7446, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_7448 = and(_T_7445, _T_7447) @[ifu_bp_ctl.scala 435:81] + node _T_7449 = or(_T_7448, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7450 = bits(_T_7449, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_6_2 = mux(_T_7450, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7451 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7452 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7453 = eq(_T_7452, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_7454 = and(_T_7451, _T_7453) @[ifu_bp_ctl.scala 435:23] + node _T_7455 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7456 = eq(_T_7455, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_7457 = and(_T_7454, _T_7456) @[ifu_bp_ctl.scala 435:81] + node _T_7458 = or(_T_7457, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7459 = bits(_T_7458, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_6_3 = mux(_T_7459, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7460 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7461 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7462 = eq(_T_7461, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_7463 = and(_T_7460, _T_7462) @[ifu_bp_ctl.scala 435:23] + node _T_7464 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7465 = eq(_T_7464, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_7466 = and(_T_7463, _T_7465) @[ifu_bp_ctl.scala 435:81] + node _T_7467 = or(_T_7466, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7468 = bits(_T_7467, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_6_4 = mux(_T_7468, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7469 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7470 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7471 = eq(_T_7470, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_7472 = and(_T_7469, _T_7471) @[ifu_bp_ctl.scala 435:23] + node _T_7473 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7474 = eq(_T_7473, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_7475 = and(_T_7472, _T_7474) @[ifu_bp_ctl.scala 435:81] + node _T_7476 = or(_T_7475, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7477 = bits(_T_7476, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_6_5 = mux(_T_7477, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7478 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7479 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7480 = eq(_T_7479, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_7481 = and(_T_7478, _T_7480) @[ifu_bp_ctl.scala 435:23] + node _T_7482 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7483 = eq(_T_7482, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_7484 = and(_T_7481, _T_7483) @[ifu_bp_ctl.scala 435:81] + node _T_7485 = or(_T_7484, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7486 = bits(_T_7485, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_6_6 = mux(_T_7486, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7487 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7488 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7489 = eq(_T_7488, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_7490 = and(_T_7487, _T_7489) @[ifu_bp_ctl.scala 435:23] + node _T_7491 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7492 = eq(_T_7491, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_7493 = and(_T_7490, _T_7492) @[ifu_bp_ctl.scala 435:81] + node _T_7494 = or(_T_7493, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7495 = bits(_T_7494, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_6_7 = mux(_T_7495, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7496 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7497 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7498 = eq(_T_7497, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_7499 = and(_T_7496, _T_7498) @[ifu_bp_ctl.scala 435:23] + node _T_7500 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7501 = eq(_T_7500, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_7502 = and(_T_7499, _T_7501) @[ifu_bp_ctl.scala 435:81] + node _T_7503 = or(_T_7502, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7504 = bits(_T_7503, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_6_8 = mux(_T_7504, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7505 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7506 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7507 = eq(_T_7506, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_7508 = and(_T_7505, _T_7507) @[ifu_bp_ctl.scala 435:23] + node _T_7509 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7510 = eq(_T_7509, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_7511 = and(_T_7508, _T_7510) @[ifu_bp_ctl.scala 435:81] + node _T_7512 = or(_T_7511, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7513 = bits(_T_7512, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_6_9 = mux(_T_7513, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7514 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7515 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7516 = eq(_T_7515, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_7517 = and(_T_7514, _T_7516) @[ifu_bp_ctl.scala 435:23] + node _T_7518 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7519 = eq(_T_7518, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_7520 = and(_T_7517, _T_7519) @[ifu_bp_ctl.scala 435:81] + node _T_7521 = or(_T_7520, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7522 = bits(_T_7521, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_6_10 = mux(_T_7522, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7523 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7524 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7525 = eq(_T_7524, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_7526 = and(_T_7523, _T_7525) @[ifu_bp_ctl.scala 435:23] + node _T_7527 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7528 = eq(_T_7527, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_7529 = and(_T_7526, _T_7528) @[ifu_bp_ctl.scala 435:81] + node _T_7530 = or(_T_7529, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7531 = bits(_T_7530, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_6_11 = mux(_T_7531, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7532 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7533 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7534 = eq(_T_7533, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_7535 = and(_T_7532, _T_7534) @[ifu_bp_ctl.scala 435:23] + node _T_7536 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7537 = eq(_T_7536, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_7538 = and(_T_7535, _T_7537) @[ifu_bp_ctl.scala 435:81] + node _T_7539 = or(_T_7538, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7540 = bits(_T_7539, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_6_12 = mux(_T_7540, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7541 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7542 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7543 = eq(_T_7542, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_7544 = and(_T_7541, _T_7543) @[ifu_bp_ctl.scala 435:23] + node _T_7545 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7546 = eq(_T_7545, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_7547 = and(_T_7544, _T_7546) @[ifu_bp_ctl.scala 435:81] + node _T_7548 = or(_T_7547, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7549 = bits(_T_7548, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_6_13 = mux(_T_7549, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7550 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7551 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7552 = eq(_T_7551, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_7553 = and(_T_7550, _T_7552) @[ifu_bp_ctl.scala 435:23] + node _T_7554 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7555 = eq(_T_7554, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_7556 = and(_T_7553, _T_7555) @[ifu_bp_ctl.scala 435:81] + node _T_7557 = or(_T_7556, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7558 = bits(_T_7557, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_6_14 = mux(_T_7558, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7559 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7560 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7561 = eq(_T_7560, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_7562 = and(_T_7559, _T_7561) @[ifu_bp_ctl.scala 435:23] + node _T_7563 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7564 = eq(_T_7563, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_7565 = and(_T_7562, _T_7564) @[ifu_bp_ctl.scala 435:81] + node _T_7566 = or(_T_7565, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7567 = bits(_T_7566, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_6_15 = mux(_T_7567, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7568 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7569 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7570 = eq(_T_7569, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_7571 = and(_T_7568, _T_7570) @[ifu_bp_ctl.scala 435:23] + node _T_7572 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7573 = eq(_T_7572, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_7574 = and(_T_7571, _T_7573) @[ifu_bp_ctl.scala 435:81] + node _T_7575 = or(_T_7574, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7576 = bits(_T_7575, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_7_0 = mux(_T_7576, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7577 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7578 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7579 = eq(_T_7578, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_7580 = and(_T_7577, _T_7579) @[ifu_bp_ctl.scala 435:23] + node _T_7581 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7582 = eq(_T_7581, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_7583 = and(_T_7580, _T_7582) @[ifu_bp_ctl.scala 435:81] + node _T_7584 = or(_T_7583, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7585 = bits(_T_7584, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_7_1 = mux(_T_7585, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7586 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7587 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7588 = eq(_T_7587, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_7589 = and(_T_7586, _T_7588) @[ifu_bp_ctl.scala 435:23] + node _T_7590 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7591 = eq(_T_7590, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_7592 = and(_T_7589, _T_7591) @[ifu_bp_ctl.scala 435:81] + node _T_7593 = or(_T_7592, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7594 = bits(_T_7593, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_7_2 = mux(_T_7594, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7595 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7596 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7597 = eq(_T_7596, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_7598 = and(_T_7595, _T_7597) @[ifu_bp_ctl.scala 435:23] + node _T_7599 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7600 = eq(_T_7599, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_7601 = and(_T_7598, _T_7600) @[ifu_bp_ctl.scala 435:81] + node _T_7602 = or(_T_7601, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7603 = bits(_T_7602, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_7_3 = mux(_T_7603, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7604 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7605 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7606 = eq(_T_7605, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_7607 = and(_T_7604, _T_7606) @[ifu_bp_ctl.scala 435:23] + node _T_7608 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7609 = eq(_T_7608, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_7610 = and(_T_7607, _T_7609) @[ifu_bp_ctl.scala 435:81] + node _T_7611 = or(_T_7610, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7612 = bits(_T_7611, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_7_4 = mux(_T_7612, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7613 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7614 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7615 = eq(_T_7614, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_7616 = and(_T_7613, _T_7615) @[ifu_bp_ctl.scala 435:23] + node _T_7617 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7618 = eq(_T_7617, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_7619 = and(_T_7616, _T_7618) @[ifu_bp_ctl.scala 435:81] + node _T_7620 = or(_T_7619, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7621 = bits(_T_7620, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_7_5 = mux(_T_7621, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7622 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7623 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7624 = eq(_T_7623, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_7625 = and(_T_7622, _T_7624) @[ifu_bp_ctl.scala 435:23] + node _T_7626 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7627 = eq(_T_7626, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_7628 = and(_T_7625, _T_7627) @[ifu_bp_ctl.scala 435:81] + node _T_7629 = or(_T_7628, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7630 = bits(_T_7629, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_7_6 = mux(_T_7630, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7631 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7632 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7633 = eq(_T_7632, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_7634 = and(_T_7631, _T_7633) @[ifu_bp_ctl.scala 435:23] + node _T_7635 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7636 = eq(_T_7635, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_7637 = and(_T_7634, _T_7636) @[ifu_bp_ctl.scala 435:81] + node _T_7638 = or(_T_7637, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7639 = bits(_T_7638, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_7_7 = mux(_T_7639, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7640 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7641 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7642 = eq(_T_7641, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_7643 = and(_T_7640, _T_7642) @[ifu_bp_ctl.scala 435:23] + node _T_7644 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7645 = eq(_T_7644, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_7646 = and(_T_7643, _T_7645) @[ifu_bp_ctl.scala 435:81] + node _T_7647 = or(_T_7646, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7648 = bits(_T_7647, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_7_8 = mux(_T_7648, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7649 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7650 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7651 = eq(_T_7650, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_7652 = and(_T_7649, _T_7651) @[ifu_bp_ctl.scala 435:23] + node _T_7653 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7654 = eq(_T_7653, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_7655 = and(_T_7652, _T_7654) @[ifu_bp_ctl.scala 435:81] + node _T_7656 = or(_T_7655, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7657 = bits(_T_7656, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_7_9 = mux(_T_7657, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7658 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7659 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7660 = eq(_T_7659, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_7661 = and(_T_7658, _T_7660) @[ifu_bp_ctl.scala 435:23] + node _T_7662 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7663 = eq(_T_7662, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_7664 = and(_T_7661, _T_7663) @[ifu_bp_ctl.scala 435:81] + node _T_7665 = or(_T_7664, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7666 = bits(_T_7665, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_7_10 = mux(_T_7666, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7667 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7668 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7669 = eq(_T_7668, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_7670 = and(_T_7667, _T_7669) @[ifu_bp_ctl.scala 435:23] + node _T_7671 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7672 = eq(_T_7671, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_7673 = and(_T_7670, _T_7672) @[ifu_bp_ctl.scala 435:81] + node _T_7674 = or(_T_7673, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7675 = bits(_T_7674, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_7_11 = mux(_T_7675, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7676 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7677 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7678 = eq(_T_7677, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_7679 = and(_T_7676, _T_7678) @[ifu_bp_ctl.scala 435:23] + node _T_7680 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7681 = eq(_T_7680, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_7682 = and(_T_7679, _T_7681) @[ifu_bp_ctl.scala 435:81] + node _T_7683 = or(_T_7682, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7684 = bits(_T_7683, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_7_12 = mux(_T_7684, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7685 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7686 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7687 = eq(_T_7686, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_7688 = and(_T_7685, _T_7687) @[ifu_bp_ctl.scala 435:23] + node _T_7689 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7690 = eq(_T_7689, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_7691 = and(_T_7688, _T_7690) @[ifu_bp_ctl.scala 435:81] + node _T_7692 = or(_T_7691, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7693 = bits(_T_7692, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_7_13 = mux(_T_7693, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7694 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7695 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7696 = eq(_T_7695, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_7697 = and(_T_7694, _T_7696) @[ifu_bp_ctl.scala 435:23] + node _T_7698 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7699 = eq(_T_7698, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_7700 = and(_T_7697, _T_7699) @[ifu_bp_ctl.scala 435:81] + node _T_7701 = or(_T_7700, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7702 = bits(_T_7701, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_7_14 = mux(_T_7702, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7703 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7704 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7705 = eq(_T_7704, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_7706 = and(_T_7703, _T_7705) @[ifu_bp_ctl.scala 435:23] + node _T_7707 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7708 = eq(_T_7707, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_7709 = and(_T_7706, _T_7708) @[ifu_bp_ctl.scala 435:81] + node _T_7710 = or(_T_7709, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7711 = bits(_T_7710, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_7_15 = mux(_T_7711, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7712 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7713 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7714 = eq(_T_7713, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_7715 = and(_T_7712, _T_7714) @[ifu_bp_ctl.scala 435:23] + node _T_7716 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7717 = eq(_T_7716, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_7718 = and(_T_7715, _T_7717) @[ifu_bp_ctl.scala 435:81] + node _T_7719 = or(_T_7718, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7720 = bits(_T_7719, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_8_0 = mux(_T_7720, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7721 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7722 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7723 = eq(_T_7722, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_7724 = and(_T_7721, _T_7723) @[ifu_bp_ctl.scala 435:23] + node _T_7725 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7726 = eq(_T_7725, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_7727 = and(_T_7724, _T_7726) @[ifu_bp_ctl.scala 435:81] + node _T_7728 = or(_T_7727, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7729 = bits(_T_7728, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_8_1 = mux(_T_7729, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7730 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7731 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7732 = eq(_T_7731, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_7733 = and(_T_7730, _T_7732) @[ifu_bp_ctl.scala 435:23] + node _T_7734 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7735 = eq(_T_7734, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_7736 = and(_T_7733, _T_7735) @[ifu_bp_ctl.scala 435:81] + node _T_7737 = or(_T_7736, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7738 = bits(_T_7737, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_8_2 = mux(_T_7738, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7739 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7740 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7741 = eq(_T_7740, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_7742 = and(_T_7739, _T_7741) @[ifu_bp_ctl.scala 435:23] + node _T_7743 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7744 = eq(_T_7743, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_7745 = and(_T_7742, _T_7744) @[ifu_bp_ctl.scala 435:81] + node _T_7746 = or(_T_7745, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7747 = bits(_T_7746, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_8_3 = mux(_T_7747, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7748 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7749 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7750 = eq(_T_7749, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_7751 = and(_T_7748, _T_7750) @[ifu_bp_ctl.scala 435:23] + node _T_7752 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7753 = eq(_T_7752, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_7754 = and(_T_7751, _T_7753) @[ifu_bp_ctl.scala 435:81] + node _T_7755 = or(_T_7754, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7756 = bits(_T_7755, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_8_4 = mux(_T_7756, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7757 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7758 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7759 = eq(_T_7758, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_7760 = and(_T_7757, _T_7759) @[ifu_bp_ctl.scala 435:23] + node _T_7761 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7762 = eq(_T_7761, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_7763 = and(_T_7760, _T_7762) @[ifu_bp_ctl.scala 435:81] + node _T_7764 = or(_T_7763, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7765 = bits(_T_7764, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_8_5 = mux(_T_7765, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7766 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7767 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7768 = eq(_T_7767, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_7769 = and(_T_7766, _T_7768) @[ifu_bp_ctl.scala 435:23] + node _T_7770 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7771 = eq(_T_7770, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_7772 = and(_T_7769, _T_7771) @[ifu_bp_ctl.scala 435:81] + node _T_7773 = or(_T_7772, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7774 = bits(_T_7773, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_8_6 = mux(_T_7774, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7775 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7776 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7777 = eq(_T_7776, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_7778 = and(_T_7775, _T_7777) @[ifu_bp_ctl.scala 435:23] + node _T_7779 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7780 = eq(_T_7779, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_7781 = and(_T_7778, _T_7780) @[ifu_bp_ctl.scala 435:81] + node _T_7782 = or(_T_7781, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7783 = bits(_T_7782, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_8_7 = mux(_T_7783, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7784 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7785 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7786 = eq(_T_7785, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_7787 = and(_T_7784, _T_7786) @[ifu_bp_ctl.scala 435:23] + node _T_7788 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7789 = eq(_T_7788, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_7790 = and(_T_7787, _T_7789) @[ifu_bp_ctl.scala 435:81] + node _T_7791 = or(_T_7790, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7792 = bits(_T_7791, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_8_8 = mux(_T_7792, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7793 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7794 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7795 = eq(_T_7794, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_7796 = and(_T_7793, _T_7795) @[ifu_bp_ctl.scala 435:23] + node _T_7797 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7798 = eq(_T_7797, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_7799 = and(_T_7796, _T_7798) @[ifu_bp_ctl.scala 435:81] + node _T_7800 = or(_T_7799, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7801 = bits(_T_7800, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_8_9 = mux(_T_7801, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7802 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7803 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7804 = eq(_T_7803, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_7805 = and(_T_7802, _T_7804) @[ifu_bp_ctl.scala 435:23] + node _T_7806 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7807 = eq(_T_7806, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_7808 = and(_T_7805, _T_7807) @[ifu_bp_ctl.scala 435:81] + node _T_7809 = or(_T_7808, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7810 = bits(_T_7809, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_8_10 = mux(_T_7810, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7811 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7812 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7813 = eq(_T_7812, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_7814 = and(_T_7811, _T_7813) @[ifu_bp_ctl.scala 435:23] + node _T_7815 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7816 = eq(_T_7815, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_7817 = and(_T_7814, _T_7816) @[ifu_bp_ctl.scala 435:81] + node _T_7818 = or(_T_7817, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7819 = bits(_T_7818, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_8_11 = mux(_T_7819, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7820 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7821 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7822 = eq(_T_7821, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_7823 = and(_T_7820, _T_7822) @[ifu_bp_ctl.scala 435:23] + node _T_7824 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7825 = eq(_T_7824, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_7826 = and(_T_7823, _T_7825) @[ifu_bp_ctl.scala 435:81] + node _T_7827 = or(_T_7826, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7828 = bits(_T_7827, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_8_12 = mux(_T_7828, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7829 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7830 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7831 = eq(_T_7830, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_7832 = and(_T_7829, _T_7831) @[ifu_bp_ctl.scala 435:23] + node _T_7833 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7834 = eq(_T_7833, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_7835 = and(_T_7832, _T_7834) @[ifu_bp_ctl.scala 435:81] + node _T_7836 = or(_T_7835, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7837 = bits(_T_7836, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_8_13 = mux(_T_7837, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7838 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7839 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7840 = eq(_T_7839, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_7841 = and(_T_7838, _T_7840) @[ifu_bp_ctl.scala 435:23] + node _T_7842 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7843 = eq(_T_7842, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_7844 = and(_T_7841, _T_7843) @[ifu_bp_ctl.scala 435:81] + node _T_7845 = or(_T_7844, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7846 = bits(_T_7845, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_8_14 = mux(_T_7846, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7847 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7848 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7849 = eq(_T_7848, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_7850 = and(_T_7847, _T_7849) @[ifu_bp_ctl.scala 435:23] + node _T_7851 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7852 = eq(_T_7851, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_7853 = and(_T_7850, _T_7852) @[ifu_bp_ctl.scala 435:81] + node _T_7854 = or(_T_7853, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7855 = bits(_T_7854, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_8_15 = mux(_T_7855, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7856 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7857 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7858 = eq(_T_7857, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_7859 = and(_T_7856, _T_7858) @[ifu_bp_ctl.scala 435:23] + node _T_7860 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7861 = eq(_T_7860, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_7862 = and(_T_7859, _T_7861) @[ifu_bp_ctl.scala 435:81] + node _T_7863 = or(_T_7862, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7864 = bits(_T_7863, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_9_0 = mux(_T_7864, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7865 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7866 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7867 = eq(_T_7866, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_7868 = and(_T_7865, _T_7867) @[ifu_bp_ctl.scala 435:23] + node _T_7869 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7870 = eq(_T_7869, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_7871 = and(_T_7868, _T_7870) @[ifu_bp_ctl.scala 435:81] + node _T_7872 = or(_T_7871, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7873 = bits(_T_7872, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_9_1 = mux(_T_7873, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7874 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7875 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7876 = eq(_T_7875, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_7877 = and(_T_7874, _T_7876) @[ifu_bp_ctl.scala 435:23] + node _T_7878 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7879 = eq(_T_7878, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_7880 = and(_T_7877, _T_7879) @[ifu_bp_ctl.scala 435:81] + node _T_7881 = or(_T_7880, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7882 = bits(_T_7881, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_9_2 = mux(_T_7882, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7883 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7884 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7885 = eq(_T_7884, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_7886 = and(_T_7883, _T_7885) @[ifu_bp_ctl.scala 435:23] + node _T_7887 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7888 = eq(_T_7887, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_7889 = and(_T_7886, _T_7888) @[ifu_bp_ctl.scala 435:81] + node _T_7890 = or(_T_7889, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7891 = bits(_T_7890, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_9_3 = mux(_T_7891, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7892 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7893 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7894 = eq(_T_7893, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_7895 = and(_T_7892, _T_7894) @[ifu_bp_ctl.scala 435:23] + node _T_7896 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7897 = eq(_T_7896, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_7898 = and(_T_7895, _T_7897) @[ifu_bp_ctl.scala 435:81] + node _T_7899 = or(_T_7898, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7900 = bits(_T_7899, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_9_4 = mux(_T_7900, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7901 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7902 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7903 = eq(_T_7902, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_7904 = and(_T_7901, _T_7903) @[ifu_bp_ctl.scala 435:23] + node _T_7905 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7906 = eq(_T_7905, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_7907 = and(_T_7904, _T_7906) @[ifu_bp_ctl.scala 435:81] + node _T_7908 = or(_T_7907, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7909 = bits(_T_7908, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_9_5 = mux(_T_7909, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7910 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7911 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7912 = eq(_T_7911, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_7913 = and(_T_7910, _T_7912) @[ifu_bp_ctl.scala 435:23] + node _T_7914 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7915 = eq(_T_7914, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_7916 = and(_T_7913, _T_7915) @[ifu_bp_ctl.scala 435:81] + node _T_7917 = or(_T_7916, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7918 = bits(_T_7917, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_9_6 = mux(_T_7918, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7919 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7920 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7921 = eq(_T_7920, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_7922 = and(_T_7919, _T_7921) @[ifu_bp_ctl.scala 435:23] + node _T_7923 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7924 = eq(_T_7923, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_7925 = and(_T_7922, _T_7924) @[ifu_bp_ctl.scala 435:81] + node _T_7926 = or(_T_7925, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7927 = bits(_T_7926, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_9_7 = mux(_T_7927, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7928 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7929 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7930 = eq(_T_7929, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_7931 = and(_T_7928, _T_7930) @[ifu_bp_ctl.scala 435:23] + node _T_7932 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7933 = eq(_T_7932, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_7934 = and(_T_7931, _T_7933) @[ifu_bp_ctl.scala 435:81] + node _T_7935 = or(_T_7934, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7936 = bits(_T_7935, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_9_8 = mux(_T_7936, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7937 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7938 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7939 = eq(_T_7938, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_7940 = and(_T_7937, _T_7939) @[ifu_bp_ctl.scala 435:23] + node _T_7941 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7942 = eq(_T_7941, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_7943 = and(_T_7940, _T_7942) @[ifu_bp_ctl.scala 435:81] + node _T_7944 = or(_T_7943, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7945 = bits(_T_7944, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_9_9 = mux(_T_7945, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7946 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7947 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7948 = eq(_T_7947, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_7949 = and(_T_7946, _T_7948) @[ifu_bp_ctl.scala 435:23] + node _T_7950 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7951 = eq(_T_7950, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_7952 = and(_T_7949, _T_7951) @[ifu_bp_ctl.scala 435:81] + node _T_7953 = or(_T_7952, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7954 = bits(_T_7953, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_9_10 = mux(_T_7954, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7955 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7956 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7957 = eq(_T_7956, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_7958 = and(_T_7955, _T_7957) @[ifu_bp_ctl.scala 435:23] + node _T_7959 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7960 = eq(_T_7959, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_7961 = and(_T_7958, _T_7960) @[ifu_bp_ctl.scala 435:81] + node _T_7962 = or(_T_7961, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7963 = bits(_T_7962, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_9_11 = mux(_T_7963, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7964 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7965 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7966 = eq(_T_7965, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_7967 = and(_T_7964, _T_7966) @[ifu_bp_ctl.scala 435:23] + node _T_7968 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7969 = eq(_T_7968, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_7970 = and(_T_7967, _T_7969) @[ifu_bp_ctl.scala 435:81] + node _T_7971 = or(_T_7970, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7972 = bits(_T_7971, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_9_12 = mux(_T_7972, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7973 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7974 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7975 = eq(_T_7974, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_7976 = and(_T_7973, _T_7975) @[ifu_bp_ctl.scala 435:23] + node _T_7977 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7978 = eq(_T_7977, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_7979 = and(_T_7976, _T_7978) @[ifu_bp_ctl.scala 435:81] + node _T_7980 = or(_T_7979, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7981 = bits(_T_7980, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_9_13 = mux(_T_7981, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7982 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7983 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7984 = eq(_T_7983, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_7985 = and(_T_7982, _T_7984) @[ifu_bp_ctl.scala 435:23] + node _T_7986 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7987 = eq(_T_7986, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_7988 = and(_T_7985, _T_7987) @[ifu_bp_ctl.scala 435:81] + node _T_7989 = or(_T_7988, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7990 = bits(_T_7989, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_9_14 = mux(_T_7990, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_7991 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_7992 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_7993 = eq(_T_7992, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_7994 = and(_T_7991, _T_7993) @[ifu_bp_ctl.scala 435:23] + node _T_7995 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_7996 = eq(_T_7995, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_7997 = and(_T_7994, _T_7996) @[ifu_bp_ctl.scala 435:81] + node _T_7998 = or(_T_7997, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_7999 = bits(_T_7998, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_9_15 = mux(_T_7999, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8000 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8001 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8002 = eq(_T_8001, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_8003 = and(_T_8000, _T_8002) @[ifu_bp_ctl.scala 435:23] + node _T_8004 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8005 = eq(_T_8004, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_8006 = and(_T_8003, _T_8005) @[ifu_bp_ctl.scala 435:81] + node _T_8007 = or(_T_8006, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8008 = bits(_T_8007, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_10_0 = mux(_T_8008, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8009 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8010 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8011 = eq(_T_8010, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_8012 = and(_T_8009, _T_8011) @[ifu_bp_ctl.scala 435:23] + node _T_8013 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8014 = eq(_T_8013, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_8015 = and(_T_8012, _T_8014) @[ifu_bp_ctl.scala 435:81] + node _T_8016 = or(_T_8015, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8017 = bits(_T_8016, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_10_1 = mux(_T_8017, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8018 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8019 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8020 = eq(_T_8019, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_8021 = and(_T_8018, _T_8020) @[ifu_bp_ctl.scala 435:23] + node _T_8022 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8023 = eq(_T_8022, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_8024 = and(_T_8021, _T_8023) @[ifu_bp_ctl.scala 435:81] + node _T_8025 = or(_T_8024, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8026 = bits(_T_8025, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_10_2 = mux(_T_8026, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8027 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8028 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8029 = eq(_T_8028, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_8030 = and(_T_8027, _T_8029) @[ifu_bp_ctl.scala 435:23] + node _T_8031 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8032 = eq(_T_8031, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_8033 = and(_T_8030, _T_8032) @[ifu_bp_ctl.scala 435:81] + node _T_8034 = or(_T_8033, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8035 = bits(_T_8034, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_10_3 = mux(_T_8035, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8036 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8037 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8038 = eq(_T_8037, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_8039 = and(_T_8036, _T_8038) @[ifu_bp_ctl.scala 435:23] + node _T_8040 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8041 = eq(_T_8040, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_8042 = and(_T_8039, _T_8041) @[ifu_bp_ctl.scala 435:81] + node _T_8043 = or(_T_8042, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8044 = bits(_T_8043, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_10_4 = mux(_T_8044, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8045 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8046 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8047 = eq(_T_8046, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_8048 = and(_T_8045, _T_8047) @[ifu_bp_ctl.scala 435:23] + node _T_8049 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8050 = eq(_T_8049, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_8051 = and(_T_8048, _T_8050) @[ifu_bp_ctl.scala 435:81] + node _T_8052 = or(_T_8051, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8053 = bits(_T_8052, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_10_5 = mux(_T_8053, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8054 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8055 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8056 = eq(_T_8055, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_8057 = and(_T_8054, _T_8056) @[ifu_bp_ctl.scala 435:23] + node _T_8058 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8059 = eq(_T_8058, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_8060 = and(_T_8057, _T_8059) @[ifu_bp_ctl.scala 435:81] + node _T_8061 = or(_T_8060, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8062 = bits(_T_8061, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_10_6 = mux(_T_8062, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8063 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8064 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8065 = eq(_T_8064, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_8066 = and(_T_8063, _T_8065) @[ifu_bp_ctl.scala 435:23] + node _T_8067 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8068 = eq(_T_8067, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_8069 = and(_T_8066, _T_8068) @[ifu_bp_ctl.scala 435:81] + node _T_8070 = or(_T_8069, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8071 = bits(_T_8070, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_10_7 = mux(_T_8071, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8072 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8073 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8074 = eq(_T_8073, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_8075 = and(_T_8072, _T_8074) @[ifu_bp_ctl.scala 435:23] + node _T_8076 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8077 = eq(_T_8076, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_8078 = and(_T_8075, _T_8077) @[ifu_bp_ctl.scala 435:81] + node _T_8079 = or(_T_8078, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8080 = bits(_T_8079, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_10_8 = mux(_T_8080, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8081 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8082 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8083 = eq(_T_8082, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_8084 = and(_T_8081, _T_8083) @[ifu_bp_ctl.scala 435:23] + node _T_8085 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8086 = eq(_T_8085, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_8087 = and(_T_8084, _T_8086) @[ifu_bp_ctl.scala 435:81] + node _T_8088 = or(_T_8087, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8089 = bits(_T_8088, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_10_9 = mux(_T_8089, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8090 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8091 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8092 = eq(_T_8091, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_8093 = and(_T_8090, _T_8092) @[ifu_bp_ctl.scala 435:23] + node _T_8094 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8095 = eq(_T_8094, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_8096 = and(_T_8093, _T_8095) @[ifu_bp_ctl.scala 435:81] + node _T_8097 = or(_T_8096, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8098 = bits(_T_8097, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_10_10 = mux(_T_8098, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8099 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8100 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8101 = eq(_T_8100, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_8102 = and(_T_8099, _T_8101) @[ifu_bp_ctl.scala 435:23] + node _T_8103 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8104 = eq(_T_8103, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_8105 = and(_T_8102, _T_8104) @[ifu_bp_ctl.scala 435:81] + node _T_8106 = or(_T_8105, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8107 = bits(_T_8106, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_10_11 = mux(_T_8107, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8108 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8109 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8110 = eq(_T_8109, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_8111 = and(_T_8108, _T_8110) @[ifu_bp_ctl.scala 435:23] + node _T_8112 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8113 = eq(_T_8112, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_8114 = and(_T_8111, _T_8113) @[ifu_bp_ctl.scala 435:81] + node _T_8115 = or(_T_8114, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8116 = bits(_T_8115, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_10_12 = mux(_T_8116, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8117 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8118 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8119 = eq(_T_8118, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_8120 = and(_T_8117, _T_8119) @[ifu_bp_ctl.scala 435:23] + node _T_8121 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8122 = eq(_T_8121, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_8123 = and(_T_8120, _T_8122) @[ifu_bp_ctl.scala 435:81] + node _T_8124 = or(_T_8123, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8125 = bits(_T_8124, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_10_13 = mux(_T_8125, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8126 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8127 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8128 = eq(_T_8127, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_8129 = and(_T_8126, _T_8128) @[ifu_bp_ctl.scala 435:23] + node _T_8130 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8131 = eq(_T_8130, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_8132 = and(_T_8129, _T_8131) @[ifu_bp_ctl.scala 435:81] + node _T_8133 = or(_T_8132, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8134 = bits(_T_8133, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_10_14 = mux(_T_8134, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8135 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8136 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8137 = eq(_T_8136, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_8138 = and(_T_8135, _T_8137) @[ifu_bp_ctl.scala 435:23] + node _T_8139 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8140 = eq(_T_8139, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_8141 = and(_T_8138, _T_8140) @[ifu_bp_ctl.scala 435:81] + node _T_8142 = or(_T_8141, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8143 = bits(_T_8142, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_10_15 = mux(_T_8143, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8144 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8145 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8146 = eq(_T_8145, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_8147 = and(_T_8144, _T_8146) @[ifu_bp_ctl.scala 435:23] + node _T_8148 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8149 = eq(_T_8148, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_8150 = and(_T_8147, _T_8149) @[ifu_bp_ctl.scala 435:81] + node _T_8151 = or(_T_8150, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8152 = bits(_T_8151, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_11_0 = mux(_T_8152, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8153 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8154 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8155 = eq(_T_8154, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_8156 = and(_T_8153, _T_8155) @[ifu_bp_ctl.scala 435:23] + node _T_8157 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8158 = eq(_T_8157, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_8159 = and(_T_8156, _T_8158) @[ifu_bp_ctl.scala 435:81] + node _T_8160 = or(_T_8159, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8161 = bits(_T_8160, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_11_1 = mux(_T_8161, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8162 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8163 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8164 = eq(_T_8163, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_8165 = and(_T_8162, _T_8164) @[ifu_bp_ctl.scala 435:23] + node _T_8166 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8167 = eq(_T_8166, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_8168 = and(_T_8165, _T_8167) @[ifu_bp_ctl.scala 435:81] + node _T_8169 = or(_T_8168, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8170 = bits(_T_8169, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_11_2 = mux(_T_8170, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8171 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8172 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8173 = eq(_T_8172, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_8174 = and(_T_8171, _T_8173) @[ifu_bp_ctl.scala 435:23] + node _T_8175 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8176 = eq(_T_8175, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_8177 = and(_T_8174, _T_8176) @[ifu_bp_ctl.scala 435:81] + node _T_8178 = or(_T_8177, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8179 = bits(_T_8178, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_11_3 = mux(_T_8179, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8180 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8181 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8182 = eq(_T_8181, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_8183 = and(_T_8180, _T_8182) @[ifu_bp_ctl.scala 435:23] + node _T_8184 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8185 = eq(_T_8184, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_8186 = and(_T_8183, _T_8185) @[ifu_bp_ctl.scala 435:81] + node _T_8187 = or(_T_8186, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8188 = bits(_T_8187, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_11_4 = mux(_T_8188, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8189 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8190 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8191 = eq(_T_8190, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_8192 = and(_T_8189, _T_8191) @[ifu_bp_ctl.scala 435:23] + node _T_8193 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8194 = eq(_T_8193, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_8195 = and(_T_8192, _T_8194) @[ifu_bp_ctl.scala 435:81] + node _T_8196 = or(_T_8195, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8197 = bits(_T_8196, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_11_5 = mux(_T_8197, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8198 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8199 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8200 = eq(_T_8199, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_8201 = and(_T_8198, _T_8200) @[ifu_bp_ctl.scala 435:23] + node _T_8202 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8203 = eq(_T_8202, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_8204 = and(_T_8201, _T_8203) @[ifu_bp_ctl.scala 435:81] + node _T_8205 = or(_T_8204, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8206 = bits(_T_8205, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_11_6 = mux(_T_8206, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8207 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8208 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8209 = eq(_T_8208, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_8210 = and(_T_8207, _T_8209) @[ifu_bp_ctl.scala 435:23] + node _T_8211 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8212 = eq(_T_8211, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_8213 = and(_T_8210, _T_8212) @[ifu_bp_ctl.scala 435:81] + node _T_8214 = or(_T_8213, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8215 = bits(_T_8214, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_11_7 = mux(_T_8215, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8216 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8217 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8218 = eq(_T_8217, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_8219 = and(_T_8216, _T_8218) @[ifu_bp_ctl.scala 435:23] + node _T_8220 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8221 = eq(_T_8220, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_8222 = and(_T_8219, _T_8221) @[ifu_bp_ctl.scala 435:81] + node _T_8223 = or(_T_8222, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8224 = bits(_T_8223, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_11_8 = mux(_T_8224, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8225 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8226 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8227 = eq(_T_8226, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_8228 = and(_T_8225, _T_8227) @[ifu_bp_ctl.scala 435:23] + node _T_8229 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8230 = eq(_T_8229, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_8231 = and(_T_8228, _T_8230) @[ifu_bp_ctl.scala 435:81] + node _T_8232 = or(_T_8231, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8233 = bits(_T_8232, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_11_9 = mux(_T_8233, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8234 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8235 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8236 = eq(_T_8235, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_8237 = and(_T_8234, _T_8236) @[ifu_bp_ctl.scala 435:23] + node _T_8238 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8239 = eq(_T_8238, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_8240 = and(_T_8237, _T_8239) @[ifu_bp_ctl.scala 435:81] + node _T_8241 = or(_T_8240, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8242 = bits(_T_8241, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_11_10 = mux(_T_8242, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8243 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8244 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8245 = eq(_T_8244, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_8246 = and(_T_8243, _T_8245) @[ifu_bp_ctl.scala 435:23] + node _T_8247 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8248 = eq(_T_8247, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_8249 = and(_T_8246, _T_8248) @[ifu_bp_ctl.scala 435:81] + node _T_8250 = or(_T_8249, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8251 = bits(_T_8250, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_11_11 = mux(_T_8251, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8252 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8253 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8254 = eq(_T_8253, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_8255 = and(_T_8252, _T_8254) @[ifu_bp_ctl.scala 435:23] + node _T_8256 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8257 = eq(_T_8256, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_8258 = and(_T_8255, _T_8257) @[ifu_bp_ctl.scala 435:81] + node _T_8259 = or(_T_8258, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8260 = bits(_T_8259, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_11_12 = mux(_T_8260, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8261 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8262 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8263 = eq(_T_8262, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_8264 = and(_T_8261, _T_8263) @[ifu_bp_ctl.scala 435:23] + node _T_8265 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8266 = eq(_T_8265, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_8267 = and(_T_8264, _T_8266) @[ifu_bp_ctl.scala 435:81] + node _T_8268 = or(_T_8267, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8269 = bits(_T_8268, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_11_13 = mux(_T_8269, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8270 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8271 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8272 = eq(_T_8271, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_8273 = and(_T_8270, _T_8272) @[ifu_bp_ctl.scala 435:23] + node _T_8274 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8275 = eq(_T_8274, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_8276 = and(_T_8273, _T_8275) @[ifu_bp_ctl.scala 435:81] + node _T_8277 = or(_T_8276, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8278 = bits(_T_8277, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_11_14 = mux(_T_8278, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8279 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8280 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8281 = eq(_T_8280, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_8282 = and(_T_8279, _T_8281) @[ifu_bp_ctl.scala 435:23] + node _T_8283 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8284 = eq(_T_8283, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_8285 = and(_T_8282, _T_8284) @[ifu_bp_ctl.scala 435:81] + node _T_8286 = or(_T_8285, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8287 = bits(_T_8286, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_11_15 = mux(_T_8287, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8288 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8289 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8290 = eq(_T_8289, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_8291 = and(_T_8288, _T_8290) @[ifu_bp_ctl.scala 435:23] + node _T_8292 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8293 = eq(_T_8292, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_8294 = and(_T_8291, _T_8293) @[ifu_bp_ctl.scala 435:81] + node _T_8295 = or(_T_8294, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8296 = bits(_T_8295, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_12_0 = mux(_T_8296, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8297 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8298 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8299 = eq(_T_8298, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_8300 = and(_T_8297, _T_8299) @[ifu_bp_ctl.scala 435:23] + node _T_8301 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8302 = eq(_T_8301, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_8303 = and(_T_8300, _T_8302) @[ifu_bp_ctl.scala 435:81] + node _T_8304 = or(_T_8303, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8305 = bits(_T_8304, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_12_1 = mux(_T_8305, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8306 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8307 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8308 = eq(_T_8307, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_8309 = and(_T_8306, _T_8308) @[ifu_bp_ctl.scala 435:23] + node _T_8310 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8311 = eq(_T_8310, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_8312 = and(_T_8309, _T_8311) @[ifu_bp_ctl.scala 435:81] + node _T_8313 = or(_T_8312, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8314 = bits(_T_8313, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_12_2 = mux(_T_8314, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8315 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8316 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8317 = eq(_T_8316, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_8318 = and(_T_8315, _T_8317) @[ifu_bp_ctl.scala 435:23] + node _T_8319 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8320 = eq(_T_8319, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_8321 = and(_T_8318, _T_8320) @[ifu_bp_ctl.scala 435:81] + node _T_8322 = or(_T_8321, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8323 = bits(_T_8322, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_12_3 = mux(_T_8323, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8324 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8325 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8326 = eq(_T_8325, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_8327 = and(_T_8324, _T_8326) @[ifu_bp_ctl.scala 435:23] + node _T_8328 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8329 = eq(_T_8328, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_8330 = and(_T_8327, _T_8329) @[ifu_bp_ctl.scala 435:81] + node _T_8331 = or(_T_8330, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8332 = bits(_T_8331, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_12_4 = mux(_T_8332, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8333 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8334 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8335 = eq(_T_8334, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_8336 = and(_T_8333, _T_8335) @[ifu_bp_ctl.scala 435:23] + node _T_8337 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8338 = eq(_T_8337, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_8339 = and(_T_8336, _T_8338) @[ifu_bp_ctl.scala 435:81] + node _T_8340 = or(_T_8339, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8341 = bits(_T_8340, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_12_5 = mux(_T_8341, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8342 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8343 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8344 = eq(_T_8343, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_8345 = and(_T_8342, _T_8344) @[ifu_bp_ctl.scala 435:23] + node _T_8346 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8347 = eq(_T_8346, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_8348 = and(_T_8345, _T_8347) @[ifu_bp_ctl.scala 435:81] + node _T_8349 = or(_T_8348, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8350 = bits(_T_8349, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_12_6 = mux(_T_8350, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8351 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8352 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8353 = eq(_T_8352, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_8354 = and(_T_8351, _T_8353) @[ifu_bp_ctl.scala 435:23] + node _T_8355 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8356 = eq(_T_8355, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_8357 = and(_T_8354, _T_8356) @[ifu_bp_ctl.scala 435:81] + node _T_8358 = or(_T_8357, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8359 = bits(_T_8358, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_12_7 = mux(_T_8359, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8360 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8361 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8362 = eq(_T_8361, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_8363 = and(_T_8360, _T_8362) @[ifu_bp_ctl.scala 435:23] + node _T_8364 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8365 = eq(_T_8364, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_8366 = and(_T_8363, _T_8365) @[ifu_bp_ctl.scala 435:81] + node _T_8367 = or(_T_8366, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8368 = bits(_T_8367, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_12_8 = mux(_T_8368, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8369 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8370 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8371 = eq(_T_8370, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_8372 = and(_T_8369, _T_8371) @[ifu_bp_ctl.scala 435:23] + node _T_8373 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8374 = eq(_T_8373, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_8375 = and(_T_8372, _T_8374) @[ifu_bp_ctl.scala 435:81] + node _T_8376 = or(_T_8375, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8377 = bits(_T_8376, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_12_9 = mux(_T_8377, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8378 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8379 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8380 = eq(_T_8379, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_8381 = and(_T_8378, _T_8380) @[ifu_bp_ctl.scala 435:23] + node _T_8382 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8383 = eq(_T_8382, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_8384 = and(_T_8381, _T_8383) @[ifu_bp_ctl.scala 435:81] + node _T_8385 = or(_T_8384, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8386 = bits(_T_8385, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_12_10 = mux(_T_8386, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8387 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8388 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8389 = eq(_T_8388, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_8390 = and(_T_8387, _T_8389) @[ifu_bp_ctl.scala 435:23] + node _T_8391 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8392 = eq(_T_8391, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_8393 = and(_T_8390, _T_8392) @[ifu_bp_ctl.scala 435:81] + node _T_8394 = or(_T_8393, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8395 = bits(_T_8394, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_12_11 = mux(_T_8395, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8396 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8397 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8398 = eq(_T_8397, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_8399 = and(_T_8396, _T_8398) @[ifu_bp_ctl.scala 435:23] + node _T_8400 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8401 = eq(_T_8400, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_8402 = and(_T_8399, _T_8401) @[ifu_bp_ctl.scala 435:81] + node _T_8403 = or(_T_8402, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8404 = bits(_T_8403, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_12_12 = mux(_T_8404, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8405 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8406 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8407 = eq(_T_8406, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_8408 = and(_T_8405, _T_8407) @[ifu_bp_ctl.scala 435:23] + node _T_8409 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8410 = eq(_T_8409, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_8411 = and(_T_8408, _T_8410) @[ifu_bp_ctl.scala 435:81] + node _T_8412 = or(_T_8411, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8413 = bits(_T_8412, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_12_13 = mux(_T_8413, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8414 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8415 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8416 = eq(_T_8415, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_8417 = and(_T_8414, _T_8416) @[ifu_bp_ctl.scala 435:23] + node _T_8418 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8419 = eq(_T_8418, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_8420 = and(_T_8417, _T_8419) @[ifu_bp_ctl.scala 435:81] + node _T_8421 = or(_T_8420, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8422 = bits(_T_8421, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_12_14 = mux(_T_8422, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8423 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8424 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8425 = eq(_T_8424, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_8426 = and(_T_8423, _T_8425) @[ifu_bp_ctl.scala 435:23] + node _T_8427 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8428 = eq(_T_8427, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_8429 = and(_T_8426, _T_8428) @[ifu_bp_ctl.scala 435:81] + node _T_8430 = or(_T_8429, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8431 = bits(_T_8430, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_12_15 = mux(_T_8431, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8432 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8433 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8434 = eq(_T_8433, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_8435 = and(_T_8432, _T_8434) @[ifu_bp_ctl.scala 435:23] + node _T_8436 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8437 = eq(_T_8436, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_8438 = and(_T_8435, _T_8437) @[ifu_bp_ctl.scala 435:81] + node _T_8439 = or(_T_8438, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8440 = bits(_T_8439, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_13_0 = mux(_T_8440, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8441 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8442 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8443 = eq(_T_8442, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_8444 = and(_T_8441, _T_8443) @[ifu_bp_ctl.scala 435:23] + node _T_8445 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8446 = eq(_T_8445, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_8447 = and(_T_8444, _T_8446) @[ifu_bp_ctl.scala 435:81] + node _T_8448 = or(_T_8447, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8449 = bits(_T_8448, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_13_1 = mux(_T_8449, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8450 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8451 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8452 = eq(_T_8451, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_8453 = and(_T_8450, _T_8452) @[ifu_bp_ctl.scala 435:23] + node _T_8454 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8455 = eq(_T_8454, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_8456 = and(_T_8453, _T_8455) @[ifu_bp_ctl.scala 435:81] + node _T_8457 = or(_T_8456, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8458 = bits(_T_8457, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_13_2 = mux(_T_8458, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8459 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8460 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8461 = eq(_T_8460, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_8462 = and(_T_8459, _T_8461) @[ifu_bp_ctl.scala 435:23] + node _T_8463 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8464 = eq(_T_8463, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_8465 = and(_T_8462, _T_8464) @[ifu_bp_ctl.scala 435:81] + node _T_8466 = or(_T_8465, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8467 = bits(_T_8466, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_13_3 = mux(_T_8467, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8468 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8469 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8470 = eq(_T_8469, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_8471 = and(_T_8468, _T_8470) @[ifu_bp_ctl.scala 435:23] + node _T_8472 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8473 = eq(_T_8472, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_8474 = and(_T_8471, _T_8473) @[ifu_bp_ctl.scala 435:81] + node _T_8475 = or(_T_8474, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8476 = bits(_T_8475, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_13_4 = mux(_T_8476, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8477 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8478 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8479 = eq(_T_8478, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_8480 = and(_T_8477, _T_8479) @[ifu_bp_ctl.scala 435:23] + node _T_8481 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8482 = eq(_T_8481, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_8483 = and(_T_8480, _T_8482) @[ifu_bp_ctl.scala 435:81] + node _T_8484 = or(_T_8483, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8485 = bits(_T_8484, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_13_5 = mux(_T_8485, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8486 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8487 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8488 = eq(_T_8487, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_8489 = and(_T_8486, _T_8488) @[ifu_bp_ctl.scala 435:23] + node _T_8490 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8491 = eq(_T_8490, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_8492 = and(_T_8489, _T_8491) @[ifu_bp_ctl.scala 435:81] + node _T_8493 = or(_T_8492, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8494 = bits(_T_8493, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_13_6 = mux(_T_8494, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8495 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8496 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8497 = eq(_T_8496, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_8498 = and(_T_8495, _T_8497) @[ifu_bp_ctl.scala 435:23] + node _T_8499 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8500 = eq(_T_8499, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_8501 = and(_T_8498, _T_8500) @[ifu_bp_ctl.scala 435:81] + node _T_8502 = or(_T_8501, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8503 = bits(_T_8502, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_13_7 = mux(_T_8503, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8504 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8505 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8506 = eq(_T_8505, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_8507 = and(_T_8504, _T_8506) @[ifu_bp_ctl.scala 435:23] + node _T_8508 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8509 = eq(_T_8508, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_8510 = and(_T_8507, _T_8509) @[ifu_bp_ctl.scala 435:81] + node _T_8511 = or(_T_8510, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8512 = bits(_T_8511, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_13_8 = mux(_T_8512, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8513 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8514 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8515 = eq(_T_8514, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_8516 = and(_T_8513, _T_8515) @[ifu_bp_ctl.scala 435:23] + node _T_8517 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8518 = eq(_T_8517, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_8519 = and(_T_8516, _T_8518) @[ifu_bp_ctl.scala 435:81] + node _T_8520 = or(_T_8519, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8521 = bits(_T_8520, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_13_9 = mux(_T_8521, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8522 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8523 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8524 = eq(_T_8523, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_8525 = and(_T_8522, _T_8524) @[ifu_bp_ctl.scala 435:23] + node _T_8526 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8527 = eq(_T_8526, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_8528 = and(_T_8525, _T_8527) @[ifu_bp_ctl.scala 435:81] + node _T_8529 = or(_T_8528, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8530 = bits(_T_8529, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_13_10 = mux(_T_8530, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8531 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8532 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8533 = eq(_T_8532, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_8534 = and(_T_8531, _T_8533) @[ifu_bp_ctl.scala 435:23] + node _T_8535 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8536 = eq(_T_8535, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_8537 = and(_T_8534, _T_8536) @[ifu_bp_ctl.scala 435:81] + node _T_8538 = or(_T_8537, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8539 = bits(_T_8538, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_13_11 = mux(_T_8539, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8540 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8541 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8542 = eq(_T_8541, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_8543 = and(_T_8540, _T_8542) @[ifu_bp_ctl.scala 435:23] + node _T_8544 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8545 = eq(_T_8544, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_8546 = and(_T_8543, _T_8545) @[ifu_bp_ctl.scala 435:81] + node _T_8547 = or(_T_8546, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8548 = bits(_T_8547, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_13_12 = mux(_T_8548, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8549 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8550 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8551 = eq(_T_8550, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_8552 = and(_T_8549, _T_8551) @[ifu_bp_ctl.scala 435:23] + node _T_8553 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8554 = eq(_T_8553, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_8555 = and(_T_8552, _T_8554) @[ifu_bp_ctl.scala 435:81] + node _T_8556 = or(_T_8555, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8557 = bits(_T_8556, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_13_13 = mux(_T_8557, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8558 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8559 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8560 = eq(_T_8559, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_8561 = and(_T_8558, _T_8560) @[ifu_bp_ctl.scala 435:23] + node _T_8562 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8563 = eq(_T_8562, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_8564 = and(_T_8561, _T_8563) @[ifu_bp_ctl.scala 435:81] + node _T_8565 = or(_T_8564, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8566 = bits(_T_8565, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_13_14 = mux(_T_8566, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8567 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8568 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8569 = eq(_T_8568, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_8570 = and(_T_8567, _T_8569) @[ifu_bp_ctl.scala 435:23] + node _T_8571 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8572 = eq(_T_8571, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_8573 = and(_T_8570, _T_8572) @[ifu_bp_ctl.scala 435:81] + node _T_8574 = or(_T_8573, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8575 = bits(_T_8574, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_13_15 = mux(_T_8575, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8576 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8577 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8578 = eq(_T_8577, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_8579 = and(_T_8576, _T_8578) @[ifu_bp_ctl.scala 435:23] + node _T_8580 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8581 = eq(_T_8580, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_8582 = and(_T_8579, _T_8581) @[ifu_bp_ctl.scala 435:81] + node _T_8583 = or(_T_8582, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8584 = bits(_T_8583, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_14_0 = mux(_T_8584, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8585 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8586 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8587 = eq(_T_8586, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_8588 = and(_T_8585, _T_8587) @[ifu_bp_ctl.scala 435:23] + node _T_8589 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8590 = eq(_T_8589, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_8591 = and(_T_8588, _T_8590) @[ifu_bp_ctl.scala 435:81] + node _T_8592 = or(_T_8591, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8593 = bits(_T_8592, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_14_1 = mux(_T_8593, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8594 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8595 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8596 = eq(_T_8595, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_8597 = and(_T_8594, _T_8596) @[ifu_bp_ctl.scala 435:23] + node _T_8598 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8599 = eq(_T_8598, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_8600 = and(_T_8597, _T_8599) @[ifu_bp_ctl.scala 435:81] + node _T_8601 = or(_T_8600, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8602 = bits(_T_8601, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_14_2 = mux(_T_8602, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8603 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8604 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8605 = eq(_T_8604, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_8606 = and(_T_8603, _T_8605) @[ifu_bp_ctl.scala 435:23] + node _T_8607 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8608 = eq(_T_8607, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_8609 = and(_T_8606, _T_8608) @[ifu_bp_ctl.scala 435:81] + node _T_8610 = or(_T_8609, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8611 = bits(_T_8610, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_14_3 = mux(_T_8611, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8612 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8613 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8614 = eq(_T_8613, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_8615 = and(_T_8612, _T_8614) @[ifu_bp_ctl.scala 435:23] + node _T_8616 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8617 = eq(_T_8616, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_8618 = and(_T_8615, _T_8617) @[ifu_bp_ctl.scala 435:81] + node _T_8619 = or(_T_8618, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8620 = bits(_T_8619, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_14_4 = mux(_T_8620, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8621 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8622 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8623 = eq(_T_8622, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_8624 = and(_T_8621, _T_8623) @[ifu_bp_ctl.scala 435:23] + node _T_8625 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8626 = eq(_T_8625, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_8627 = and(_T_8624, _T_8626) @[ifu_bp_ctl.scala 435:81] + node _T_8628 = or(_T_8627, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8629 = bits(_T_8628, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_14_5 = mux(_T_8629, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8630 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8631 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8632 = eq(_T_8631, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_8633 = and(_T_8630, _T_8632) @[ifu_bp_ctl.scala 435:23] + node _T_8634 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8635 = eq(_T_8634, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_8636 = and(_T_8633, _T_8635) @[ifu_bp_ctl.scala 435:81] + node _T_8637 = or(_T_8636, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8638 = bits(_T_8637, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_14_6 = mux(_T_8638, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8639 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8640 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8641 = eq(_T_8640, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_8642 = and(_T_8639, _T_8641) @[ifu_bp_ctl.scala 435:23] + node _T_8643 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8644 = eq(_T_8643, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_8645 = and(_T_8642, _T_8644) @[ifu_bp_ctl.scala 435:81] + node _T_8646 = or(_T_8645, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8647 = bits(_T_8646, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_14_7 = mux(_T_8647, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8648 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8649 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8650 = eq(_T_8649, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_8651 = and(_T_8648, _T_8650) @[ifu_bp_ctl.scala 435:23] + node _T_8652 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8653 = eq(_T_8652, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_8654 = and(_T_8651, _T_8653) @[ifu_bp_ctl.scala 435:81] + node _T_8655 = or(_T_8654, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8656 = bits(_T_8655, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_14_8 = mux(_T_8656, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8657 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8658 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8659 = eq(_T_8658, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_8660 = and(_T_8657, _T_8659) @[ifu_bp_ctl.scala 435:23] + node _T_8661 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8662 = eq(_T_8661, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_8663 = and(_T_8660, _T_8662) @[ifu_bp_ctl.scala 435:81] + node _T_8664 = or(_T_8663, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8665 = bits(_T_8664, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_14_9 = mux(_T_8665, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8666 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8667 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8668 = eq(_T_8667, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_8669 = and(_T_8666, _T_8668) @[ifu_bp_ctl.scala 435:23] + node _T_8670 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8671 = eq(_T_8670, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_8672 = and(_T_8669, _T_8671) @[ifu_bp_ctl.scala 435:81] + node _T_8673 = or(_T_8672, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8674 = bits(_T_8673, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_14_10 = mux(_T_8674, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8675 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8676 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8677 = eq(_T_8676, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_8678 = and(_T_8675, _T_8677) @[ifu_bp_ctl.scala 435:23] + node _T_8679 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8680 = eq(_T_8679, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_8681 = and(_T_8678, _T_8680) @[ifu_bp_ctl.scala 435:81] + node _T_8682 = or(_T_8681, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8683 = bits(_T_8682, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_14_11 = mux(_T_8683, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8684 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8685 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8686 = eq(_T_8685, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_8687 = and(_T_8684, _T_8686) @[ifu_bp_ctl.scala 435:23] + node _T_8688 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8689 = eq(_T_8688, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_8690 = and(_T_8687, _T_8689) @[ifu_bp_ctl.scala 435:81] + node _T_8691 = or(_T_8690, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8692 = bits(_T_8691, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_14_12 = mux(_T_8692, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8693 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8694 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8695 = eq(_T_8694, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_8696 = and(_T_8693, _T_8695) @[ifu_bp_ctl.scala 435:23] + node _T_8697 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8698 = eq(_T_8697, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_8699 = and(_T_8696, _T_8698) @[ifu_bp_ctl.scala 435:81] + node _T_8700 = or(_T_8699, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8701 = bits(_T_8700, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_14_13 = mux(_T_8701, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8702 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8703 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8704 = eq(_T_8703, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_8705 = and(_T_8702, _T_8704) @[ifu_bp_ctl.scala 435:23] + node _T_8706 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8707 = eq(_T_8706, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_8708 = and(_T_8705, _T_8707) @[ifu_bp_ctl.scala 435:81] + node _T_8709 = or(_T_8708, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8710 = bits(_T_8709, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_14_14 = mux(_T_8710, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8711 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8712 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8713 = eq(_T_8712, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_8714 = and(_T_8711, _T_8713) @[ifu_bp_ctl.scala 435:23] + node _T_8715 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8716 = eq(_T_8715, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_8717 = and(_T_8714, _T_8716) @[ifu_bp_ctl.scala 435:81] + node _T_8718 = or(_T_8717, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8719 = bits(_T_8718, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_14_15 = mux(_T_8719, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8720 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8721 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8722 = eq(_T_8721, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_8723 = and(_T_8720, _T_8722) @[ifu_bp_ctl.scala 435:23] + node _T_8724 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8725 = eq(_T_8724, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_8726 = and(_T_8723, _T_8725) @[ifu_bp_ctl.scala 435:81] + node _T_8727 = or(_T_8726, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8728 = bits(_T_8727, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_15_0 = mux(_T_8728, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8729 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8730 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8731 = eq(_T_8730, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_8732 = and(_T_8729, _T_8731) @[ifu_bp_ctl.scala 435:23] + node _T_8733 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8734 = eq(_T_8733, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_8735 = and(_T_8732, _T_8734) @[ifu_bp_ctl.scala 435:81] + node _T_8736 = or(_T_8735, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8737 = bits(_T_8736, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_15_1 = mux(_T_8737, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8738 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8739 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8740 = eq(_T_8739, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_8741 = and(_T_8738, _T_8740) @[ifu_bp_ctl.scala 435:23] + node _T_8742 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8743 = eq(_T_8742, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_8744 = and(_T_8741, _T_8743) @[ifu_bp_ctl.scala 435:81] + node _T_8745 = or(_T_8744, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8746 = bits(_T_8745, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_15_2 = mux(_T_8746, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8747 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8748 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8749 = eq(_T_8748, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_8750 = and(_T_8747, _T_8749) @[ifu_bp_ctl.scala 435:23] + node _T_8751 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8752 = eq(_T_8751, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_8753 = and(_T_8750, _T_8752) @[ifu_bp_ctl.scala 435:81] + node _T_8754 = or(_T_8753, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8755 = bits(_T_8754, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_15_3 = mux(_T_8755, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8756 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8757 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8758 = eq(_T_8757, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_8759 = and(_T_8756, _T_8758) @[ifu_bp_ctl.scala 435:23] + node _T_8760 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8761 = eq(_T_8760, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_8762 = and(_T_8759, _T_8761) @[ifu_bp_ctl.scala 435:81] + node _T_8763 = or(_T_8762, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8764 = bits(_T_8763, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_15_4 = mux(_T_8764, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8765 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8766 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8767 = eq(_T_8766, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_8768 = and(_T_8765, _T_8767) @[ifu_bp_ctl.scala 435:23] + node _T_8769 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8770 = eq(_T_8769, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_8771 = and(_T_8768, _T_8770) @[ifu_bp_ctl.scala 435:81] + node _T_8772 = or(_T_8771, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8773 = bits(_T_8772, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_15_5 = mux(_T_8773, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8774 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8775 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8776 = eq(_T_8775, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_8777 = and(_T_8774, _T_8776) @[ifu_bp_ctl.scala 435:23] + node _T_8778 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8779 = eq(_T_8778, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_8780 = and(_T_8777, _T_8779) @[ifu_bp_ctl.scala 435:81] + node _T_8781 = or(_T_8780, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8782 = bits(_T_8781, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_15_6 = mux(_T_8782, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8783 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8784 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8785 = eq(_T_8784, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_8786 = and(_T_8783, _T_8785) @[ifu_bp_ctl.scala 435:23] + node _T_8787 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8788 = eq(_T_8787, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_8789 = and(_T_8786, _T_8788) @[ifu_bp_ctl.scala 435:81] + node _T_8790 = or(_T_8789, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8791 = bits(_T_8790, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_15_7 = mux(_T_8791, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8792 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8793 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8794 = eq(_T_8793, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_8795 = and(_T_8792, _T_8794) @[ifu_bp_ctl.scala 435:23] + node _T_8796 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8797 = eq(_T_8796, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_8798 = and(_T_8795, _T_8797) @[ifu_bp_ctl.scala 435:81] + node _T_8799 = or(_T_8798, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8800 = bits(_T_8799, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_15_8 = mux(_T_8800, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8801 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8802 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8803 = eq(_T_8802, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_8804 = and(_T_8801, _T_8803) @[ifu_bp_ctl.scala 435:23] + node _T_8805 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8806 = eq(_T_8805, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_8807 = and(_T_8804, _T_8806) @[ifu_bp_ctl.scala 435:81] + node _T_8808 = or(_T_8807, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8809 = bits(_T_8808, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_15_9 = mux(_T_8809, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8810 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8811 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8812 = eq(_T_8811, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_8813 = and(_T_8810, _T_8812) @[ifu_bp_ctl.scala 435:23] + node _T_8814 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8815 = eq(_T_8814, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_8816 = and(_T_8813, _T_8815) @[ifu_bp_ctl.scala 435:81] + node _T_8817 = or(_T_8816, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8818 = bits(_T_8817, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_15_10 = mux(_T_8818, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8819 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8820 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8821 = eq(_T_8820, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_8822 = and(_T_8819, _T_8821) @[ifu_bp_ctl.scala 435:23] + node _T_8823 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8824 = eq(_T_8823, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_8825 = and(_T_8822, _T_8824) @[ifu_bp_ctl.scala 435:81] + node _T_8826 = or(_T_8825, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8827 = bits(_T_8826, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_15_11 = mux(_T_8827, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8828 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8829 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8830 = eq(_T_8829, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_8831 = and(_T_8828, _T_8830) @[ifu_bp_ctl.scala 435:23] + node _T_8832 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8833 = eq(_T_8832, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_8834 = and(_T_8831, _T_8833) @[ifu_bp_ctl.scala 435:81] + node _T_8835 = or(_T_8834, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8836 = bits(_T_8835, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_15_12 = mux(_T_8836, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8837 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8838 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8839 = eq(_T_8838, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_8840 = and(_T_8837, _T_8839) @[ifu_bp_ctl.scala 435:23] + node _T_8841 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8842 = eq(_T_8841, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_8843 = and(_T_8840, _T_8842) @[ifu_bp_ctl.scala 435:81] + node _T_8844 = or(_T_8843, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8845 = bits(_T_8844, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_15_13 = mux(_T_8845, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8846 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8847 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8848 = eq(_T_8847, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_8849 = and(_T_8846, _T_8848) @[ifu_bp_ctl.scala 435:23] + node _T_8850 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8851 = eq(_T_8850, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_8852 = and(_T_8849, _T_8851) @[ifu_bp_ctl.scala 435:81] + node _T_8853 = or(_T_8852, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8854 = bits(_T_8853, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_15_14 = mux(_T_8854, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8855 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 435:20] + node _T_8856 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8857 = eq(_T_8856, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_8858 = and(_T_8855, _T_8857) @[ifu_bp_ctl.scala 435:23] + node _T_8859 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8860 = eq(_T_8859, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_8861 = and(_T_8858, _T_8860) @[ifu_bp_ctl.scala 435:81] + node _T_8862 = or(_T_8861, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8863 = bits(_T_8862, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_0_15_15 = mux(_T_8863, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8864 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_8865 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8866 = eq(_T_8865, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_8867 = and(_T_8864, _T_8866) @[ifu_bp_ctl.scala 435:23] + node _T_8868 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8869 = eq(_T_8868, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_8870 = and(_T_8867, _T_8869) @[ifu_bp_ctl.scala 435:81] + node _T_8871 = or(_T_8870, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8872 = bits(_T_8871, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_0_0 = mux(_T_8872, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8873 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_8874 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8875 = eq(_T_8874, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_8876 = and(_T_8873, _T_8875) @[ifu_bp_ctl.scala 435:23] + node _T_8877 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8878 = eq(_T_8877, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_8879 = and(_T_8876, _T_8878) @[ifu_bp_ctl.scala 435:81] + node _T_8880 = or(_T_8879, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8881 = bits(_T_8880, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_0_1 = mux(_T_8881, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8882 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_8883 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8884 = eq(_T_8883, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_8885 = and(_T_8882, _T_8884) @[ifu_bp_ctl.scala 435:23] + node _T_8886 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8887 = eq(_T_8886, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_8888 = and(_T_8885, _T_8887) @[ifu_bp_ctl.scala 435:81] + node _T_8889 = or(_T_8888, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8890 = bits(_T_8889, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_0_2 = mux(_T_8890, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8891 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_8892 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8893 = eq(_T_8892, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_8894 = and(_T_8891, _T_8893) @[ifu_bp_ctl.scala 435:23] + node _T_8895 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8896 = eq(_T_8895, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_8897 = and(_T_8894, _T_8896) @[ifu_bp_ctl.scala 435:81] + node _T_8898 = or(_T_8897, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8899 = bits(_T_8898, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_0_3 = mux(_T_8899, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8900 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_8901 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8902 = eq(_T_8901, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_8903 = and(_T_8900, _T_8902) @[ifu_bp_ctl.scala 435:23] + node _T_8904 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8905 = eq(_T_8904, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_8906 = and(_T_8903, _T_8905) @[ifu_bp_ctl.scala 435:81] + node _T_8907 = or(_T_8906, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8908 = bits(_T_8907, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_0_4 = mux(_T_8908, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8909 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_8910 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8911 = eq(_T_8910, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_8912 = and(_T_8909, _T_8911) @[ifu_bp_ctl.scala 435:23] + node _T_8913 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8914 = eq(_T_8913, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_8915 = and(_T_8912, _T_8914) @[ifu_bp_ctl.scala 435:81] + node _T_8916 = or(_T_8915, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8917 = bits(_T_8916, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_0_5 = mux(_T_8917, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8918 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_8919 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8920 = eq(_T_8919, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_8921 = and(_T_8918, _T_8920) @[ifu_bp_ctl.scala 435:23] + node _T_8922 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8923 = eq(_T_8922, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_8924 = and(_T_8921, _T_8923) @[ifu_bp_ctl.scala 435:81] + node _T_8925 = or(_T_8924, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8926 = bits(_T_8925, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_0_6 = mux(_T_8926, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8927 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_8928 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8929 = eq(_T_8928, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_8930 = and(_T_8927, _T_8929) @[ifu_bp_ctl.scala 435:23] + node _T_8931 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8932 = eq(_T_8931, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_8933 = and(_T_8930, _T_8932) @[ifu_bp_ctl.scala 435:81] + node _T_8934 = or(_T_8933, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8935 = bits(_T_8934, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_0_7 = mux(_T_8935, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8936 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_8937 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8938 = eq(_T_8937, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_8939 = and(_T_8936, _T_8938) @[ifu_bp_ctl.scala 435:23] + node _T_8940 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8941 = eq(_T_8940, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_8942 = and(_T_8939, _T_8941) @[ifu_bp_ctl.scala 435:81] + node _T_8943 = or(_T_8942, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8944 = bits(_T_8943, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_0_8 = mux(_T_8944, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8945 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_8946 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8947 = eq(_T_8946, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_8948 = and(_T_8945, _T_8947) @[ifu_bp_ctl.scala 435:23] + node _T_8949 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8950 = eq(_T_8949, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_8951 = and(_T_8948, _T_8950) @[ifu_bp_ctl.scala 435:81] + node _T_8952 = or(_T_8951, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8953 = bits(_T_8952, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_0_9 = mux(_T_8953, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8954 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_8955 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8956 = eq(_T_8955, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_8957 = and(_T_8954, _T_8956) @[ifu_bp_ctl.scala 435:23] + node _T_8958 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8959 = eq(_T_8958, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_8960 = and(_T_8957, _T_8959) @[ifu_bp_ctl.scala 435:81] + node _T_8961 = or(_T_8960, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8962 = bits(_T_8961, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_0_10 = mux(_T_8962, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8963 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_8964 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8965 = eq(_T_8964, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_8966 = and(_T_8963, _T_8965) @[ifu_bp_ctl.scala 435:23] + node _T_8967 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8968 = eq(_T_8967, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_8969 = and(_T_8966, _T_8968) @[ifu_bp_ctl.scala 435:81] + node _T_8970 = or(_T_8969, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8971 = bits(_T_8970, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_0_11 = mux(_T_8971, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8972 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_8973 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8974 = eq(_T_8973, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_8975 = and(_T_8972, _T_8974) @[ifu_bp_ctl.scala 435:23] + node _T_8976 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8977 = eq(_T_8976, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_8978 = and(_T_8975, _T_8977) @[ifu_bp_ctl.scala 435:81] + node _T_8979 = or(_T_8978, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8980 = bits(_T_8979, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_0_12 = mux(_T_8980, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8981 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_8982 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8983 = eq(_T_8982, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_8984 = and(_T_8981, _T_8983) @[ifu_bp_ctl.scala 435:23] + node _T_8985 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8986 = eq(_T_8985, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_8987 = and(_T_8984, _T_8986) @[ifu_bp_ctl.scala 435:81] + node _T_8988 = or(_T_8987, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8989 = bits(_T_8988, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_0_13 = mux(_T_8989, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8990 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_8991 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_8992 = eq(_T_8991, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_8993 = and(_T_8990, _T_8992) @[ifu_bp_ctl.scala 435:23] + node _T_8994 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_8995 = eq(_T_8994, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_8996 = and(_T_8993, _T_8995) @[ifu_bp_ctl.scala 435:81] + node _T_8997 = or(_T_8996, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_8998 = bits(_T_8997, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_0_14 = mux(_T_8998, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_8999 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9000 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9001 = eq(_T_9000, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_9002 = and(_T_8999, _T_9001) @[ifu_bp_ctl.scala 435:23] + node _T_9003 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9004 = eq(_T_9003, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:154] + node _T_9005 = and(_T_9002, _T_9004) @[ifu_bp_ctl.scala 435:81] + node _T_9006 = or(_T_9005, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9007 = bits(_T_9006, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_0_15 = mux(_T_9007, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9008 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9009 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9010 = eq(_T_9009, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_9011 = and(_T_9008, _T_9010) @[ifu_bp_ctl.scala 435:23] + node _T_9012 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9013 = eq(_T_9012, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_9014 = and(_T_9011, _T_9013) @[ifu_bp_ctl.scala 435:81] + node _T_9015 = or(_T_9014, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9016 = bits(_T_9015, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_1_0 = mux(_T_9016, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9017 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9018 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9019 = eq(_T_9018, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_9020 = and(_T_9017, _T_9019) @[ifu_bp_ctl.scala 435:23] + node _T_9021 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9022 = eq(_T_9021, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_9023 = and(_T_9020, _T_9022) @[ifu_bp_ctl.scala 435:81] + node _T_9024 = or(_T_9023, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9025 = bits(_T_9024, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_1_1 = mux(_T_9025, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9026 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9027 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9028 = eq(_T_9027, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_9029 = and(_T_9026, _T_9028) @[ifu_bp_ctl.scala 435:23] + node _T_9030 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9031 = eq(_T_9030, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_9032 = and(_T_9029, _T_9031) @[ifu_bp_ctl.scala 435:81] + node _T_9033 = or(_T_9032, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9034 = bits(_T_9033, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_1_2 = mux(_T_9034, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9035 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9036 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9037 = eq(_T_9036, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_9038 = and(_T_9035, _T_9037) @[ifu_bp_ctl.scala 435:23] + node _T_9039 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9040 = eq(_T_9039, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_9041 = and(_T_9038, _T_9040) @[ifu_bp_ctl.scala 435:81] + node _T_9042 = or(_T_9041, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9043 = bits(_T_9042, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_1_3 = mux(_T_9043, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9044 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9045 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9046 = eq(_T_9045, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_9047 = and(_T_9044, _T_9046) @[ifu_bp_ctl.scala 435:23] + node _T_9048 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9049 = eq(_T_9048, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_9050 = and(_T_9047, _T_9049) @[ifu_bp_ctl.scala 435:81] + node _T_9051 = or(_T_9050, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9052 = bits(_T_9051, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_1_4 = mux(_T_9052, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9053 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9054 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9055 = eq(_T_9054, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_9056 = and(_T_9053, _T_9055) @[ifu_bp_ctl.scala 435:23] + node _T_9057 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9058 = eq(_T_9057, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_9059 = and(_T_9056, _T_9058) @[ifu_bp_ctl.scala 435:81] + node _T_9060 = or(_T_9059, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9061 = bits(_T_9060, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_1_5 = mux(_T_9061, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9062 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9063 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9064 = eq(_T_9063, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_9065 = and(_T_9062, _T_9064) @[ifu_bp_ctl.scala 435:23] + node _T_9066 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9067 = eq(_T_9066, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_9068 = and(_T_9065, _T_9067) @[ifu_bp_ctl.scala 435:81] + node _T_9069 = or(_T_9068, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9070 = bits(_T_9069, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_1_6 = mux(_T_9070, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9071 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9072 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9073 = eq(_T_9072, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_9074 = and(_T_9071, _T_9073) @[ifu_bp_ctl.scala 435:23] + node _T_9075 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9076 = eq(_T_9075, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_9077 = and(_T_9074, _T_9076) @[ifu_bp_ctl.scala 435:81] + node _T_9078 = or(_T_9077, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9079 = bits(_T_9078, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_1_7 = mux(_T_9079, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9080 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9081 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9082 = eq(_T_9081, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_9083 = and(_T_9080, _T_9082) @[ifu_bp_ctl.scala 435:23] + node _T_9084 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9085 = eq(_T_9084, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_9086 = and(_T_9083, _T_9085) @[ifu_bp_ctl.scala 435:81] + node _T_9087 = or(_T_9086, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9088 = bits(_T_9087, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_1_8 = mux(_T_9088, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9089 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9090 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9091 = eq(_T_9090, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_9092 = and(_T_9089, _T_9091) @[ifu_bp_ctl.scala 435:23] + node _T_9093 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9094 = eq(_T_9093, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_9095 = and(_T_9092, _T_9094) @[ifu_bp_ctl.scala 435:81] + node _T_9096 = or(_T_9095, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9097 = bits(_T_9096, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_1_9 = mux(_T_9097, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9098 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9099 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9100 = eq(_T_9099, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_9101 = and(_T_9098, _T_9100) @[ifu_bp_ctl.scala 435:23] + node _T_9102 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9103 = eq(_T_9102, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_9104 = and(_T_9101, _T_9103) @[ifu_bp_ctl.scala 435:81] + node _T_9105 = or(_T_9104, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9106 = bits(_T_9105, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_1_10 = mux(_T_9106, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9107 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9108 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9109 = eq(_T_9108, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_9110 = and(_T_9107, _T_9109) @[ifu_bp_ctl.scala 435:23] + node _T_9111 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9112 = eq(_T_9111, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_9113 = and(_T_9110, _T_9112) @[ifu_bp_ctl.scala 435:81] + node _T_9114 = or(_T_9113, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9115 = bits(_T_9114, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_1_11 = mux(_T_9115, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9116 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9117 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9118 = eq(_T_9117, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_9119 = and(_T_9116, _T_9118) @[ifu_bp_ctl.scala 435:23] + node _T_9120 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9121 = eq(_T_9120, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_9122 = and(_T_9119, _T_9121) @[ifu_bp_ctl.scala 435:81] + node _T_9123 = or(_T_9122, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9124 = bits(_T_9123, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_1_12 = mux(_T_9124, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9125 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9126 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9127 = eq(_T_9126, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_9128 = and(_T_9125, _T_9127) @[ifu_bp_ctl.scala 435:23] + node _T_9129 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9130 = eq(_T_9129, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_9131 = and(_T_9128, _T_9130) @[ifu_bp_ctl.scala 435:81] + node _T_9132 = or(_T_9131, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9133 = bits(_T_9132, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_1_13 = mux(_T_9133, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9134 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9135 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9136 = eq(_T_9135, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_9137 = and(_T_9134, _T_9136) @[ifu_bp_ctl.scala 435:23] + node _T_9138 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9139 = eq(_T_9138, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_9140 = and(_T_9137, _T_9139) @[ifu_bp_ctl.scala 435:81] + node _T_9141 = or(_T_9140, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9142 = bits(_T_9141, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_1_14 = mux(_T_9142, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9143 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9144 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9145 = eq(_T_9144, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_9146 = and(_T_9143, _T_9145) @[ifu_bp_ctl.scala 435:23] + node _T_9147 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9148 = eq(_T_9147, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:154] + node _T_9149 = and(_T_9146, _T_9148) @[ifu_bp_ctl.scala 435:81] + node _T_9150 = or(_T_9149, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9151 = bits(_T_9150, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_1_15 = mux(_T_9151, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9152 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9153 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9154 = eq(_T_9153, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_9155 = and(_T_9152, _T_9154) @[ifu_bp_ctl.scala 435:23] + node _T_9156 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9157 = eq(_T_9156, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_9158 = and(_T_9155, _T_9157) @[ifu_bp_ctl.scala 435:81] + node _T_9159 = or(_T_9158, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9160 = bits(_T_9159, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_2_0 = mux(_T_9160, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9161 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9162 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9163 = eq(_T_9162, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_9164 = and(_T_9161, _T_9163) @[ifu_bp_ctl.scala 435:23] + node _T_9165 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9166 = eq(_T_9165, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_9167 = and(_T_9164, _T_9166) @[ifu_bp_ctl.scala 435:81] + node _T_9168 = or(_T_9167, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9169 = bits(_T_9168, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_2_1 = mux(_T_9169, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9170 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9171 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9172 = eq(_T_9171, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_9173 = and(_T_9170, _T_9172) @[ifu_bp_ctl.scala 435:23] + node _T_9174 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9175 = eq(_T_9174, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_9176 = and(_T_9173, _T_9175) @[ifu_bp_ctl.scala 435:81] + node _T_9177 = or(_T_9176, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9178 = bits(_T_9177, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_2_2 = mux(_T_9178, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9179 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9180 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9181 = eq(_T_9180, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_9182 = and(_T_9179, _T_9181) @[ifu_bp_ctl.scala 435:23] + node _T_9183 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9184 = eq(_T_9183, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_9185 = and(_T_9182, _T_9184) @[ifu_bp_ctl.scala 435:81] + node _T_9186 = or(_T_9185, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9187 = bits(_T_9186, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_2_3 = mux(_T_9187, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9188 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9189 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9190 = eq(_T_9189, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_9191 = and(_T_9188, _T_9190) @[ifu_bp_ctl.scala 435:23] + node _T_9192 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9193 = eq(_T_9192, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_9194 = and(_T_9191, _T_9193) @[ifu_bp_ctl.scala 435:81] + node _T_9195 = or(_T_9194, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9196 = bits(_T_9195, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_2_4 = mux(_T_9196, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9197 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9198 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9199 = eq(_T_9198, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_9200 = and(_T_9197, _T_9199) @[ifu_bp_ctl.scala 435:23] + node _T_9201 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9202 = eq(_T_9201, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_9203 = and(_T_9200, _T_9202) @[ifu_bp_ctl.scala 435:81] + node _T_9204 = or(_T_9203, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9205 = bits(_T_9204, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_2_5 = mux(_T_9205, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9206 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9207 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9208 = eq(_T_9207, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_9209 = and(_T_9206, _T_9208) @[ifu_bp_ctl.scala 435:23] + node _T_9210 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9211 = eq(_T_9210, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_9212 = and(_T_9209, _T_9211) @[ifu_bp_ctl.scala 435:81] + node _T_9213 = or(_T_9212, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9214 = bits(_T_9213, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_2_6 = mux(_T_9214, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9215 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9216 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9217 = eq(_T_9216, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_9218 = and(_T_9215, _T_9217) @[ifu_bp_ctl.scala 435:23] + node _T_9219 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9220 = eq(_T_9219, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_9221 = and(_T_9218, _T_9220) @[ifu_bp_ctl.scala 435:81] + node _T_9222 = or(_T_9221, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9223 = bits(_T_9222, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_2_7 = mux(_T_9223, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9224 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9225 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9226 = eq(_T_9225, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_9227 = and(_T_9224, _T_9226) @[ifu_bp_ctl.scala 435:23] + node _T_9228 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9229 = eq(_T_9228, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_9230 = and(_T_9227, _T_9229) @[ifu_bp_ctl.scala 435:81] + node _T_9231 = or(_T_9230, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9232 = bits(_T_9231, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_2_8 = mux(_T_9232, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9233 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9234 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9235 = eq(_T_9234, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_9236 = and(_T_9233, _T_9235) @[ifu_bp_ctl.scala 435:23] + node _T_9237 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9238 = eq(_T_9237, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_9239 = and(_T_9236, _T_9238) @[ifu_bp_ctl.scala 435:81] + node _T_9240 = or(_T_9239, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9241 = bits(_T_9240, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_2_9 = mux(_T_9241, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9242 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9243 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9244 = eq(_T_9243, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_9245 = and(_T_9242, _T_9244) @[ifu_bp_ctl.scala 435:23] + node _T_9246 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9247 = eq(_T_9246, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_9248 = and(_T_9245, _T_9247) @[ifu_bp_ctl.scala 435:81] + node _T_9249 = or(_T_9248, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9250 = bits(_T_9249, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_2_10 = mux(_T_9250, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9251 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9252 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9253 = eq(_T_9252, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_9254 = and(_T_9251, _T_9253) @[ifu_bp_ctl.scala 435:23] + node _T_9255 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9256 = eq(_T_9255, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_9257 = and(_T_9254, _T_9256) @[ifu_bp_ctl.scala 435:81] + node _T_9258 = or(_T_9257, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9259 = bits(_T_9258, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_2_11 = mux(_T_9259, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9260 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9261 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9262 = eq(_T_9261, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_9263 = and(_T_9260, _T_9262) @[ifu_bp_ctl.scala 435:23] + node _T_9264 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9265 = eq(_T_9264, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_9266 = and(_T_9263, _T_9265) @[ifu_bp_ctl.scala 435:81] + node _T_9267 = or(_T_9266, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9268 = bits(_T_9267, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_2_12 = mux(_T_9268, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9269 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9270 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9271 = eq(_T_9270, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_9272 = and(_T_9269, _T_9271) @[ifu_bp_ctl.scala 435:23] + node _T_9273 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9274 = eq(_T_9273, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_9275 = and(_T_9272, _T_9274) @[ifu_bp_ctl.scala 435:81] + node _T_9276 = or(_T_9275, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9277 = bits(_T_9276, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_2_13 = mux(_T_9277, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9278 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9279 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9280 = eq(_T_9279, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_9281 = and(_T_9278, _T_9280) @[ifu_bp_ctl.scala 435:23] + node _T_9282 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9283 = eq(_T_9282, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_9284 = and(_T_9281, _T_9283) @[ifu_bp_ctl.scala 435:81] + node _T_9285 = or(_T_9284, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9286 = bits(_T_9285, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_2_14 = mux(_T_9286, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9287 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9288 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9289 = eq(_T_9288, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_9290 = and(_T_9287, _T_9289) @[ifu_bp_ctl.scala 435:23] + node _T_9291 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9292 = eq(_T_9291, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:154] + node _T_9293 = and(_T_9290, _T_9292) @[ifu_bp_ctl.scala 435:81] + node _T_9294 = or(_T_9293, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9295 = bits(_T_9294, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_2_15 = mux(_T_9295, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9296 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9297 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9298 = eq(_T_9297, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_9299 = and(_T_9296, _T_9298) @[ifu_bp_ctl.scala 435:23] + node _T_9300 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9301 = eq(_T_9300, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_9302 = and(_T_9299, _T_9301) @[ifu_bp_ctl.scala 435:81] + node _T_9303 = or(_T_9302, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9304 = bits(_T_9303, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_3_0 = mux(_T_9304, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9305 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9306 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9307 = eq(_T_9306, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_9308 = and(_T_9305, _T_9307) @[ifu_bp_ctl.scala 435:23] + node _T_9309 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9310 = eq(_T_9309, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_9311 = and(_T_9308, _T_9310) @[ifu_bp_ctl.scala 435:81] + node _T_9312 = or(_T_9311, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9313 = bits(_T_9312, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_3_1 = mux(_T_9313, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9314 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9315 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9316 = eq(_T_9315, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_9317 = and(_T_9314, _T_9316) @[ifu_bp_ctl.scala 435:23] + node _T_9318 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9319 = eq(_T_9318, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_9320 = and(_T_9317, _T_9319) @[ifu_bp_ctl.scala 435:81] + node _T_9321 = or(_T_9320, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9322 = bits(_T_9321, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_3_2 = mux(_T_9322, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9323 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9324 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9325 = eq(_T_9324, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_9326 = and(_T_9323, _T_9325) @[ifu_bp_ctl.scala 435:23] + node _T_9327 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9328 = eq(_T_9327, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_9329 = and(_T_9326, _T_9328) @[ifu_bp_ctl.scala 435:81] + node _T_9330 = or(_T_9329, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9331 = bits(_T_9330, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_3_3 = mux(_T_9331, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9332 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9333 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9334 = eq(_T_9333, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_9335 = and(_T_9332, _T_9334) @[ifu_bp_ctl.scala 435:23] + node _T_9336 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9337 = eq(_T_9336, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_9338 = and(_T_9335, _T_9337) @[ifu_bp_ctl.scala 435:81] + node _T_9339 = or(_T_9338, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9340 = bits(_T_9339, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_3_4 = mux(_T_9340, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9341 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9342 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9343 = eq(_T_9342, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_9344 = and(_T_9341, _T_9343) @[ifu_bp_ctl.scala 435:23] + node _T_9345 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9346 = eq(_T_9345, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_9347 = and(_T_9344, _T_9346) @[ifu_bp_ctl.scala 435:81] + node _T_9348 = or(_T_9347, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9349 = bits(_T_9348, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_3_5 = mux(_T_9349, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9350 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9351 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9352 = eq(_T_9351, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_9353 = and(_T_9350, _T_9352) @[ifu_bp_ctl.scala 435:23] + node _T_9354 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9355 = eq(_T_9354, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_9356 = and(_T_9353, _T_9355) @[ifu_bp_ctl.scala 435:81] + node _T_9357 = or(_T_9356, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9358 = bits(_T_9357, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_3_6 = mux(_T_9358, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9359 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9360 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9361 = eq(_T_9360, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_9362 = and(_T_9359, _T_9361) @[ifu_bp_ctl.scala 435:23] + node _T_9363 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9364 = eq(_T_9363, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_9365 = and(_T_9362, _T_9364) @[ifu_bp_ctl.scala 435:81] + node _T_9366 = or(_T_9365, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9367 = bits(_T_9366, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_3_7 = mux(_T_9367, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9368 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9369 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9370 = eq(_T_9369, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_9371 = and(_T_9368, _T_9370) @[ifu_bp_ctl.scala 435:23] + node _T_9372 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9373 = eq(_T_9372, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_9374 = and(_T_9371, _T_9373) @[ifu_bp_ctl.scala 435:81] + node _T_9375 = or(_T_9374, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9376 = bits(_T_9375, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_3_8 = mux(_T_9376, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9377 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9378 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9379 = eq(_T_9378, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_9380 = and(_T_9377, _T_9379) @[ifu_bp_ctl.scala 435:23] + node _T_9381 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9382 = eq(_T_9381, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_9383 = and(_T_9380, _T_9382) @[ifu_bp_ctl.scala 435:81] + node _T_9384 = or(_T_9383, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9385 = bits(_T_9384, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_3_9 = mux(_T_9385, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9386 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9387 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9388 = eq(_T_9387, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_9389 = and(_T_9386, _T_9388) @[ifu_bp_ctl.scala 435:23] + node _T_9390 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9391 = eq(_T_9390, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_9392 = and(_T_9389, _T_9391) @[ifu_bp_ctl.scala 435:81] + node _T_9393 = or(_T_9392, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9394 = bits(_T_9393, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_3_10 = mux(_T_9394, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9395 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9396 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9397 = eq(_T_9396, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_9398 = and(_T_9395, _T_9397) @[ifu_bp_ctl.scala 435:23] + node _T_9399 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9400 = eq(_T_9399, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_9401 = and(_T_9398, _T_9400) @[ifu_bp_ctl.scala 435:81] + node _T_9402 = or(_T_9401, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9403 = bits(_T_9402, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_3_11 = mux(_T_9403, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9404 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9405 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9406 = eq(_T_9405, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_9407 = and(_T_9404, _T_9406) @[ifu_bp_ctl.scala 435:23] + node _T_9408 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9409 = eq(_T_9408, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_9410 = and(_T_9407, _T_9409) @[ifu_bp_ctl.scala 435:81] + node _T_9411 = or(_T_9410, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9412 = bits(_T_9411, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_3_12 = mux(_T_9412, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9413 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9414 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9415 = eq(_T_9414, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_9416 = and(_T_9413, _T_9415) @[ifu_bp_ctl.scala 435:23] + node _T_9417 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9418 = eq(_T_9417, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_9419 = and(_T_9416, _T_9418) @[ifu_bp_ctl.scala 435:81] + node _T_9420 = or(_T_9419, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9421 = bits(_T_9420, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_3_13 = mux(_T_9421, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9422 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9423 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9424 = eq(_T_9423, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_9425 = and(_T_9422, _T_9424) @[ifu_bp_ctl.scala 435:23] + node _T_9426 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9427 = eq(_T_9426, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_9428 = and(_T_9425, _T_9427) @[ifu_bp_ctl.scala 435:81] + node _T_9429 = or(_T_9428, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9430 = bits(_T_9429, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_3_14 = mux(_T_9430, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9431 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9432 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9433 = eq(_T_9432, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_9434 = and(_T_9431, _T_9433) @[ifu_bp_ctl.scala 435:23] + node _T_9435 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9436 = eq(_T_9435, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:154] + node _T_9437 = and(_T_9434, _T_9436) @[ifu_bp_ctl.scala 435:81] + node _T_9438 = or(_T_9437, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9439 = bits(_T_9438, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_3_15 = mux(_T_9439, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9440 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9441 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9442 = eq(_T_9441, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_9443 = and(_T_9440, _T_9442) @[ifu_bp_ctl.scala 435:23] + node _T_9444 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9445 = eq(_T_9444, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_9446 = and(_T_9443, _T_9445) @[ifu_bp_ctl.scala 435:81] + node _T_9447 = or(_T_9446, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9448 = bits(_T_9447, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_4_0 = mux(_T_9448, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9449 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9450 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9451 = eq(_T_9450, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_9452 = and(_T_9449, _T_9451) @[ifu_bp_ctl.scala 435:23] + node _T_9453 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9454 = eq(_T_9453, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_9455 = and(_T_9452, _T_9454) @[ifu_bp_ctl.scala 435:81] + node _T_9456 = or(_T_9455, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9457 = bits(_T_9456, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_4_1 = mux(_T_9457, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9458 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9459 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9460 = eq(_T_9459, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_9461 = and(_T_9458, _T_9460) @[ifu_bp_ctl.scala 435:23] + node _T_9462 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9463 = eq(_T_9462, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_9464 = and(_T_9461, _T_9463) @[ifu_bp_ctl.scala 435:81] + node _T_9465 = or(_T_9464, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9466 = bits(_T_9465, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_4_2 = mux(_T_9466, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9467 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9468 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9469 = eq(_T_9468, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_9470 = and(_T_9467, _T_9469) @[ifu_bp_ctl.scala 435:23] + node _T_9471 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9472 = eq(_T_9471, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_9473 = and(_T_9470, _T_9472) @[ifu_bp_ctl.scala 435:81] + node _T_9474 = or(_T_9473, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9475 = bits(_T_9474, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_4_3 = mux(_T_9475, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9476 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9477 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9478 = eq(_T_9477, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_9479 = and(_T_9476, _T_9478) @[ifu_bp_ctl.scala 435:23] + node _T_9480 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9481 = eq(_T_9480, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_9482 = and(_T_9479, _T_9481) @[ifu_bp_ctl.scala 435:81] + node _T_9483 = or(_T_9482, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9484 = bits(_T_9483, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_4_4 = mux(_T_9484, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9485 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9486 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9487 = eq(_T_9486, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_9488 = and(_T_9485, _T_9487) @[ifu_bp_ctl.scala 435:23] + node _T_9489 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9490 = eq(_T_9489, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_9491 = and(_T_9488, _T_9490) @[ifu_bp_ctl.scala 435:81] + node _T_9492 = or(_T_9491, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9493 = bits(_T_9492, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_4_5 = mux(_T_9493, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9494 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9495 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9496 = eq(_T_9495, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_9497 = and(_T_9494, _T_9496) @[ifu_bp_ctl.scala 435:23] + node _T_9498 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9499 = eq(_T_9498, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_9500 = and(_T_9497, _T_9499) @[ifu_bp_ctl.scala 435:81] + node _T_9501 = or(_T_9500, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9502 = bits(_T_9501, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_4_6 = mux(_T_9502, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9503 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9504 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9505 = eq(_T_9504, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_9506 = and(_T_9503, _T_9505) @[ifu_bp_ctl.scala 435:23] + node _T_9507 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9508 = eq(_T_9507, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_9509 = and(_T_9506, _T_9508) @[ifu_bp_ctl.scala 435:81] + node _T_9510 = or(_T_9509, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9511 = bits(_T_9510, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_4_7 = mux(_T_9511, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9512 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9513 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9514 = eq(_T_9513, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_9515 = and(_T_9512, _T_9514) @[ifu_bp_ctl.scala 435:23] + node _T_9516 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9517 = eq(_T_9516, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_9518 = and(_T_9515, _T_9517) @[ifu_bp_ctl.scala 435:81] + node _T_9519 = or(_T_9518, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9520 = bits(_T_9519, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_4_8 = mux(_T_9520, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9521 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9522 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9523 = eq(_T_9522, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_9524 = and(_T_9521, _T_9523) @[ifu_bp_ctl.scala 435:23] + node _T_9525 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9526 = eq(_T_9525, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_9527 = and(_T_9524, _T_9526) @[ifu_bp_ctl.scala 435:81] + node _T_9528 = or(_T_9527, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9529 = bits(_T_9528, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_4_9 = mux(_T_9529, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9530 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9531 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9532 = eq(_T_9531, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_9533 = and(_T_9530, _T_9532) @[ifu_bp_ctl.scala 435:23] + node _T_9534 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9535 = eq(_T_9534, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_9536 = and(_T_9533, _T_9535) @[ifu_bp_ctl.scala 435:81] + node _T_9537 = or(_T_9536, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9538 = bits(_T_9537, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_4_10 = mux(_T_9538, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9539 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9540 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9541 = eq(_T_9540, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_9542 = and(_T_9539, _T_9541) @[ifu_bp_ctl.scala 435:23] + node _T_9543 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9544 = eq(_T_9543, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_9545 = and(_T_9542, _T_9544) @[ifu_bp_ctl.scala 435:81] + node _T_9546 = or(_T_9545, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9547 = bits(_T_9546, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_4_11 = mux(_T_9547, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9548 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9549 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9550 = eq(_T_9549, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_9551 = and(_T_9548, _T_9550) @[ifu_bp_ctl.scala 435:23] + node _T_9552 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9553 = eq(_T_9552, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_9554 = and(_T_9551, _T_9553) @[ifu_bp_ctl.scala 435:81] + node _T_9555 = or(_T_9554, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9556 = bits(_T_9555, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_4_12 = mux(_T_9556, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9557 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9558 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9559 = eq(_T_9558, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_9560 = and(_T_9557, _T_9559) @[ifu_bp_ctl.scala 435:23] + node _T_9561 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9562 = eq(_T_9561, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_9563 = and(_T_9560, _T_9562) @[ifu_bp_ctl.scala 435:81] + node _T_9564 = or(_T_9563, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9565 = bits(_T_9564, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_4_13 = mux(_T_9565, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9566 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9567 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9568 = eq(_T_9567, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_9569 = and(_T_9566, _T_9568) @[ifu_bp_ctl.scala 435:23] + node _T_9570 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9571 = eq(_T_9570, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_9572 = and(_T_9569, _T_9571) @[ifu_bp_ctl.scala 435:81] + node _T_9573 = or(_T_9572, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9574 = bits(_T_9573, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_4_14 = mux(_T_9574, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9575 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9576 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9577 = eq(_T_9576, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_9578 = and(_T_9575, _T_9577) @[ifu_bp_ctl.scala 435:23] + node _T_9579 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9580 = eq(_T_9579, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:154] + node _T_9581 = and(_T_9578, _T_9580) @[ifu_bp_ctl.scala 435:81] + node _T_9582 = or(_T_9581, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9583 = bits(_T_9582, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_4_15 = mux(_T_9583, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9584 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9585 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9586 = eq(_T_9585, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_9587 = and(_T_9584, _T_9586) @[ifu_bp_ctl.scala 435:23] + node _T_9588 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9589 = eq(_T_9588, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_9590 = and(_T_9587, _T_9589) @[ifu_bp_ctl.scala 435:81] + node _T_9591 = or(_T_9590, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9592 = bits(_T_9591, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_5_0 = mux(_T_9592, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9593 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9594 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9595 = eq(_T_9594, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_9596 = and(_T_9593, _T_9595) @[ifu_bp_ctl.scala 435:23] + node _T_9597 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9598 = eq(_T_9597, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_9599 = and(_T_9596, _T_9598) @[ifu_bp_ctl.scala 435:81] + node _T_9600 = or(_T_9599, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9601 = bits(_T_9600, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_5_1 = mux(_T_9601, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9602 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9603 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9604 = eq(_T_9603, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_9605 = and(_T_9602, _T_9604) @[ifu_bp_ctl.scala 435:23] + node _T_9606 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9607 = eq(_T_9606, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_9608 = and(_T_9605, _T_9607) @[ifu_bp_ctl.scala 435:81] + node _T_9609 = or(_T_9608, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9610 = bits(_T_9609, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_5_2 = mux(_T_9610, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9611 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9612 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9613 = eq(_T_9612, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_9614 = and(_T_9611, _T_9613) @[ifu_bp_ctl.scala 435:23] + node _T_9615 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9616 = eq(_T_9615, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_9617 = and(_T_9614, _T_9616) @[ifu_bp_ctl.scala 435:81] + node _T_9618 = or(_T_9617, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9619 = bits(_T_9618, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_5_3 = mux(_T_9619, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9620 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9621 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9622 = eq(_T_9621, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_9623 = and(_T_9620, _T_9622) @[ifu_bp_ctl.scala 435:23] + node _T_9624 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9625 = eq(_T_9624, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_9626 = and(_T_9623, _T_9625) @[ifu_bp_ctl.scala 435:81] + node _T_9627 = or(_T_9626, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9628 = bits(_T_9627, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_5_4 = mux(_T_9628, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9629 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9630 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9631 = eq(_T_9630, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_9632 = and(_T_9629, _T_9631) @[ifu_bp_ctl.scala 435:23] + node _T_9633 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9634 = eq(_T_9633, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_9635 = and(_T_9632, _T_9634) @[ifu_bp_ctl.scala 435:81] + node _T_9636 = or(_T_9635, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9637 = bits(_T_9636, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_5_5 = mux(_T_9637, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9638 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9639 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9640 = eq(_T_9639, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_9641 = and(_T_9638, _T_9640) @[ifu_bp_ctl.scala 435:23] + node _T_9642 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9643 = eq(_T_9642, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_9644 = and(_T_9641, _T_9643) @[ifu_bp_ctl.scala 435:81] + node _T_9645 = or(_T_9644, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9646 = bits(_T_9645, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_5_6 = mux(_T_9646, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9647 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9648 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9649 = eq(_T_9648, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_9650 = and(_T_9647, _T_9649) @[ifu_bp_ctl.scala 435:23] + node _T_9651 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9652 = eq(_T_9651, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_9653 = and(_T_9650, _T_9652) @[ifu_bp_ctl.scala 435:81] + node _T_9654 = or(_T_9653, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9655 = bits(_T_9654, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_5_7 = mux(_T_9655, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9656 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9657 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9658 = eq(_T_9657, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_9659 = and(_T_9656, _T_9658) @[ifu_bp_ctl.scala 435:23] + node _T_9660 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9661 = eq(_T_9660, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_9662 = and(_T_9659, _T_9661) @[ifu_bp_ctl.scala 435:81] + node _T_9663 = or(_T_9662, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9664 = bits(_T_9663, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_5_8 = mux(_T_9664, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9665 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9666 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9667 = eq(_T_9666, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_9668 = and(_T_9665, _T_9667) @[ifu_bp_ctl.scala 435:23] + node _T_9669 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9670 = eq(_T_9669, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_9671 = and(_T_9668, _T_9670) @[ifu_bp_ctl.scala 435:81] + node _T_9672 = or(_T_9671, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9673 = bits(_T_9672, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_5_9 = mux(_T_9673, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9674 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9675 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9676 = eq(_T_9675, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_9677 = and(_T_9674, _T_9676) @[ifu_bp_ctl.scala 435:23] + node _T_9678 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9679 = eq(_T_9678, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_9680 = and(_T_9677, _T_9679) @[ifu_bp_ctl.scala 435:81] + node _T_9681 = or(_T_9680, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9682 = bits(_T_9681, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_5_10 = mux(_T_9682, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9683 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9684 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9685 = eq(_T_9684, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_9686 = and(_T_9683, _T_9685) @[ifu_bp_ctl.scala 435:23] + node _T_9687 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9688 = eq(_T_9687, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_9689 = and(_T_9686, _T_9688) @[ifu_bp_ctl.scala 435:81] + node _T_9690 = or(_T_9689, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9691 = bits(_T_9690, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_5_11 = mux(_T_9691, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9692 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9693 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9694 = eq(_T_9693, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_9695 = and(_T_9692, _T_9694) @[ifu_bp_ctl.scala 435:23] + node _T_9696 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9697 = eq(_T_9696, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_9698 = and(_T_9695, _T_9697) @[ifu_bp_ctl.scala 435:81] + node _T_9699 = or(_T_9698, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9700 = bits(_T_9699, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_5_12 = mux(_T_9700, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9701 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9702 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9703 = eq(_T_9702, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_9704 = and(_T_9701, _T_9703) @[ifu_bp_ctl.scala 435:23] + node _T_9705 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9706 = eq(_T_9705, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_9707 = and(_T_9704, _T_9706) @[ifu_bp_ctl.scala 435:81] + node _T_9708 = or(_T_9707, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9709 = bits(_T_9708, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_5_13 = mux(_T_9709, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9710 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9711 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9712 = eq(_T_9711, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_9713 = and(_T_9710, _T_9712) @[ifu_bp_ctl.scala 435:23] + node _T_9714 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9715 = eq(_T_9714, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_9716 = and(_T_9713, _T_9715) @[ifu_bp_ctl.scala 435:81] + node _T_9717 = or(_T_9716, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9718 = bits(_T_9717, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_5_14 = mux(_T_9718, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9719 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9720 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9721 = eq(_T_9720, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_9722 = and(_T_9719, _T_9721) @[ifu_bp_ctl.scala 435:23] + node _T_9723 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9724 = eq(_T_9723, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:154] + node _T_9725 = and(_T_9722, _T_9724) @[ifu_bp_ctl.scala 435:81] + node _T_9726 = or(_T_9725, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9727 = bits(_T_9726, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_5_15 = mux(_T_9727, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9728 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9729 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9730 = eq(_T_9729, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_9731 = and(_T_9728, _T_9730) @[ifu_bp_ctl.scala 435:23] + node _T_9732 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9733 = eq(_T_9732, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_9734 = and(_T_9731, _T_9733) @[ifu_bp_ctl.scala 435:81] + node _T_9735 = or(_T_9734, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9736 = bits(_T_9735, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_6_0 = mux(_T_9736, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9737 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9738 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9739 = eq(_T_9738, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_9740 = and(_T_9737, _T_9739) @[ifu_bp_ctl.scala 435:23] + node _T_9741 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9742 = eq(_T_9741, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_9743 = and(_T_9740, _T_9742) @[ifu_bp_ctl.scala 435:81] + node _T_9744 = or(_T_9743, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9745 = bits(_T_9744, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_6_1 = mux(_T_9745, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9746 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9747 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9748 = eq(_T_9747, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_9749 = and(_T_9746, _T_9748) @[ifu_bp_ctl.scala 435:23] + node _T_9750 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9751 = eq(_T_9750, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_9752 = and(_T_9749, _T_9751) @[ifu_bp_ctl.scala 435:81] + node _T_9753 = or(_T_9752, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9754 = bits(_T_9753, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_6_2 = mux(_T_9754, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9755 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9756 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9757 = eq(_T_9756, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_9758 = and(_T_9755, _T_9757) @[ifu_bp_ctl.scala 435:23] + node _T_9759 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9760 = eq(_T_9759, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_9761 = and(_T_9758, _T_9760) @[ifu_bp_ctl.scala 435:81] + node _T_9762 = or(_T_9761, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9763 = bits(_T_9762, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_6_3 = mux(_T_9763, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9764 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9765 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9766 = eq(_T_9765, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_9767 = and(_T_9764, _T_9766) @[ifu_bp_ctl.scala 435:23] + node _T_9768 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9769 = eq(_T_9768, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_9770 = and(_T_9767, _T_9769) @[ifu_bp_ctl.scala 435:81] + node _T_9771 = or(_T_9770, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9772 = bits(_T_9771, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_6_4 = mux(_T_9772, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9773 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9774 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9775 = eq(_T_9774, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_9776 = and(_T_9773, _T_9775) @[ifu_bp_ctl.scala 435:23] + node _T_9777 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9778 = eq(_T_9777, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_9779 = and(_T_9776, _T_9778) @[ifu_bp_ctl.scala 435:81] + node _T_9780 = or(_T_9779, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9781 = bits(_T_9780, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_6_5 = mux(_T_9781, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9782 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9783 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9784 = eq(_T_9783, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_9785 = and(_T_9782, _T_9784) @[ifu_bp_ctl.scala 435:23] + node _T_9786 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9787 = eq(_T_9786, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_9788 = and(_T_9785, _T_9787) @[ifu_bp_ctl.scala 435:81] + node _T_9789 = or(_T_9788, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9790 = bits(_T_9789, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_6_6 = mux(_T_9790, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9791 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9792 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9793 = eq(_T_9792, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_9794 = and(_T_9791, _T_9793) @[ifu_bp_ctl.scala 435:23] + node _T_9795 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9796 = eq(_T_9795, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_9797 = and(_T_9794, _T_9796) @[ifu_bp_ctl.scala 435:81] + node _T_9798 = or(_T_9797, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9799 = bits(_T_9798, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_6_7 = mux(_T_9799, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9800 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9801 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9802 = eq(_T_9801, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_9803 = and(_T_9800, _T_9802) @[ifu_bp_ctl.scala 435:23] + node _T_9804 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9805 = eq(_T_9804, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_9806 = and(_T_9803, _T_9805) @[ifu_bp_ctl.scala 435:81] + node _T_9807 = or(_T_9806, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9808 = bits(_T_9807, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_6_8 = mux(_T_9808, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9809 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9810 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9811 = eq(_T_9810, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_9812 = and(_T_9809, _T_9811) @[ifu_bp_ctl.scala 435:23] + node _T_9813 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9814 = eq(_T_9813, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_9815 = and(_T_9812, _T_9814) @[ifu_bp_ctl.scala 435:81] + node _T_9816 = or(_T_9815, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9817 = bits(_T_9816, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_6_9 = mux(_T_9817, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9818 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9819 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9820 = eq(_T_9819, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_9821 = and(_T_9818, _T_9820) @[ifu_bp_ctl.scala 435:23] + node _T_9822 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9823 = eq(_T_9822, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_9824 = and(_T_9821, _T_9823) @[ifu_bp_ctl.scala 435:81] + node _T_9825 = or(_T_9824, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9826 = bits(_T_9825, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_6_10 = mux(_T_9826, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9827 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9828 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9829 = eq(_T_9828, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_9830 = and(_T_9827, _T_9829) @[ifu_bp_ctl.scala 435:23] + node _T_9831 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9832 = eq(_T_9831, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_9833 = and(_T_9830, _T_9832) @[ifu_bp_ctl.scala 435:81] + node _T_9834 = or(_T_9833, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9835 = bits(_T_9834, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_6_11 = mux(_T_9835, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9836 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9837 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9838 = eq(_T_9837, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_9839 = and(_T_9836, _T_9838) @[ifu_bp_ctl.scala 435:23] + node _T_9840 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9841 = eq(_T_9840, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_9842 = and(_T_9839, _T_9841) @[ifu_bp_ctl.scala 435:81] + node _T_9843 = or(_T_9842, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9844 = bits(_T_9843, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_6_12 = mux(_T_9844, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9845 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9846 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9847 = eq(_T_9846, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_9848 = and(_T_9845, _T_9847) @[ifu_bp_ctl.scala 435:23] + node _T_9849 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9850 = eq(_T_9849, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_9851 = and(_T_9848, _T_9850) @[ifu_bp_ctl.scala 435:81] + node _T_9852 = or(_T_9851, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9853 = bits(_T_9852, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_6_13 = mux(_T_9853, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9854 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9855 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9856 = eq(_T_9855, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_9857 = and(_T_9854, _T_9856) @[ifu_bp_ctl.scala 435:23] + node _T_9858 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9859 = eq(_T_9858, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_9860 = and(_T_9857, _T_9859) @[ifu_bp_ctl.scala 435:81] + node _T_9861 = or(_T_9860, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9862 = bits(_T_9861, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_6_14 = mux(_T_9862, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9863 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9864 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9865 = eq(_T_9864, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_9866 = and(_T_9863, _T_9865) @[ifu_bp_ctl.scala 435:23] + node _T_9867 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9868 = eq(_T_9867, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:154] + node _T_9869 = and(_T_9866, _T_9868) @[ifu_bp_ctl.scala 435:81] + node _T_9870 = or(_T_9869, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9871 = bits(_T_9870, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_6_15 = mux(_T_9871, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9872 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9873 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9874 = eq(_T_9873, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_9875 = and(_T_9872, _T_9874) @[ifu_bp_ctl.scala 435:23] + node _T_9876 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9877 = eq(_T_9876, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_9878 = and(_T_9875, _T_9877) @[ifu_bp_ctl.scala 435:81] + node _T_9879 = or(_T_9878, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9880 = bits(_T_9879, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_7_0 = mux(_T_9880, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9881 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9882 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9883 = eq(_T_9882, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_9884 = and(_T_9881, _T_9883) @[ifu_bp_ctl.scala 435:23] + node _T_9885 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9886 = eq(_T_9885, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_9887 = and(_T_9884, _T_9886) @[ifu_bp_ctl.scala 435:81] + node _T_9888 = or(_T_9887, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9889 = bits(_T_9888, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_7_1 = mux(_T_9889, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9890 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9891 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9892 = eq(_T_9891, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_9893 = and(_T_9890, _T_9892) @[ifu_bp_ctl.scala 435:23] + node _T_9894 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9895 = eq(_T_9894, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_9896 = and(_T_9893, _T_9895) @[ifu_bp_ctl.scala 435:81] + node _T_9897 = or(_T_9896, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9898 = bits(_T_9897, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_7_2 = mux(_T_9898, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9899 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9900 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9901 = eq(_T_9900, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_9902 = and(_T_9899, _T_9901) @[ifu_bp_ctl.scala 435:23] + node _T_9903 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9904 = eq(_T_9903, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_9905 = and(_T_9902, _T_9904) @[ifu_bp_ctl.scala 435:81] + node _T_9906 = or(_T_9905, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9907 = bits(_T_9906, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_7_3 = mux(_T_9907, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9908 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9909 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9910 = eq(_T_9909, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_9911 = and(_T_9908, _T_9910) @[ifu_bp_ctl.scala 435:23] + node _T_9912 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9913 = eq(_T_9912, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_9914 = and(_T_9911, _T_9913) @[ifu_bp_ctl.scala 435:81] + node _T_9915 = or(_T_9914, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9916 = bits(_T_9915, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_7_4 = mux(_T_9916, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9917 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9918 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9919 = eq(_T_9918, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_9920 = and(_T_9917, _T_9919) @[ifu_bp_ctl.scala 435:23] + node _T_9921 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9922 = eq(_T_9921, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_9923 = and(_T_9920, _T_9922) @[ifu_bp_ctl.scala 435:81] + node _T_9924 = or(_T_9923, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9925 = bits(_T_9924, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_7_5 = mux(_T_9925, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9926 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9927 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9928 = eq(_T_9927, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_9929 = and(_T_9926, _T_9928) @[ifu_bp_ctl.scala 435:23] + node _T_9930 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9931 = eq(_T_9930, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_9932 = and(_T_9929, _T_9931) @[ifu_bp_ctl.scala 435:81] + node _T_9933 = or(_T_9932, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9934 = bits(_T_9933, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_7_6 = mux(_T_9934, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9935 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9936 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9937 = eq(_T_9936, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_9938 = and(_T_9935, _T_9937) @[ifu_bp_ctl.scala 435:23] + node _T_9939 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9940 = eq(_T_9939, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_9941 = and(_T_9938, _T_9940) @[ifu_bp_ctl.scala 435:81] + node _T_9942 = or(_T_9941, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9943 = bits(_T_9942, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_7_7 = mux(_T_9943, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9944 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9945 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9946 = eq(_T_9945, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_9947 = and(_T_9944, _T_9946) @[ifu_bp_ctl.scala 435:23] + node _T_9948 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9949 = eq(_T_9948, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_9950 = and(_T_9947, _T_9949) @[ifu_bp_ctl.scala 435:81] + node _T_9951 = or(_T_9950, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9952 = bits(_T_9951, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_7_8 = mux(_T_9952, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9953 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9954 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9955 = eq(_T_9954, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_9956 = and(_T_9953, _T_9955) @[ifu_bp_ctl.scala 435:23] + node _T_9957 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9958 = eq(_T_9957, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_9959 = and(_T_9956, _T_9958) @[ifu_bp_ctl.scala 435:81] + node _T_9960 = or(_T_9959, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9961 = bits(_T_9960, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_7_9 = mux(_T_9961, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9962 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9963 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9964 = eq(_T_9963, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_9965 = and(_T_9962, _T_9964) @[ifu_bp_ctl.scala 435:23] + node _T_9966 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9967 = eq(_T_9966, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_9968 = and(_T_9965, _T_9967) @[ifu_bp_ctl.scala 435:81] + node _T_9969 = or(_T_9968, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9970 = bits(_T_9969, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_7_10 = mux(_T_9970, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9971 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9972 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9973 = eq(_T_9972, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_9974 = and(_T_9971, _T_9973) @[ifu_bp_ctl.scala 435:23] + node _T_9975 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9976 = eq(_T_9975, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_9977 = and(_T_9974, _T_9976) @[ifu_bp_ctl.scala 435:81] + node _T_9978 = or(_T_9977, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9979 = bits(_T_9978, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_7_11 = mux(_T_9979, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9980 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9981 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9982 = eq(_T_9981, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_9983 = and(_T_9980, _T_9982) @[ifu_bp_ctl.scala 435:23] + node _T_9984 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9985 = eq(_T_9984, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_9986 = and(_T_9983, _T_9985) @[ifu_bp_ctl.scala 435:81] + node _T_9987 = or(_T_9986, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9988 = bits(_T_9987, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_7_12 = mux(_T_9988, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9989 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9990 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_9991 = eq(_T_9990, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_9992 = and(_T_9989, _T_9991) @[ifu_bp_ctl.scala 435:23] + node _T_9993 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_9994 = eq(_T_9993, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_9995 = and(_T_9992, _T_9994) @[ifu_bp_ctl.scala 435:81] + node _T_9996 = or(_T_9995, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_9997 = bits(_T_9996, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_7_13 = mux(_T_9997, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_9998 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_9999 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10000 = eq(_T_9999, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_10001 = and(_T_9998, _T_10000) @[ifu_bp_ctl.scala 435:23] + node _T_10002 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10003 = eq(_T_10002, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_10004 = and(_T_10001, _T_10003) @[ifu_bp_ctl.scala 435:81] + node _T_10005 = or(_T_10004, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10006 = bits(_T_10005, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_7_14 = mux(_T_10006, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10007 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10008 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10009 = eq(_T_10008, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_10010 = and(_T_10007, _T_10009) @[ifu_bp_ctl.scala 435:23] + node _T_10011 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10012 = eq(_T_10011, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:154] + node _T_10013 = and(_T_10010, _T_10012) @[ifu_bp_ctl.scala 435:81] + node _T_10014 = or(_T_10013, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10015 = bits(_T_10014, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_7_15 = mux(_T_10015, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10016 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10017 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10018 = eq(_T_10017, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_10019 = and(_T_10016, _T_10018) @[ifu_bp_ctl.scala 435:23] + node _T_10020 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10021 = eq(_T_10020, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_10022 = and(_T_10019, _T_10021) @[ifu_bp_ctl.scala 435:81] + node _T_10023 = or(_T_10022, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10024 = bits(_T_10023, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_8_0 = mux(_T_10024, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10025 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10026 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10027 = eq(_T_10026, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_10028 = and(_T_10025, _T_10027) @[ifu_bp_ctl.scala 435:23] + node _T_10029 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10030 = eq(_T_10029, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_10031 = and(_T_10028, _T_10030) @[ifu_bp_ctl.scala 435:81] + node _T_10032 = or(_T_10031, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10033 = bits(_T_10032, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_8_1 = mux(_T_10033, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10034 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10035 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10036 = eq(_T_10035, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_10037 = and(_T_10034, _T_10036) @[ifu_bp_ctl.scala 435:23] + node _T_10038 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10039 = eq(_T_10038, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_10040 = and(_T_10037, _T_10039) @[ifu_bp_ctl.scala 435:81] + node _T_10041 = or(_T_10040, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10042 = bits(_T_10041, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_8_2 = mux(_T_10042, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10043 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10044 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10045 = eq(_T_10044, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_10046 = and(_T_10043, _T_10045) @[ifu_bp_ctl.scala 435:23] + node _T_10047 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10048 = eq(_T_10047, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_10049 = and(_T_10046, _T_10048) @[ifu_bp_ctl.scala 435:81] + node _T_10050 = or(_T_10049, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10051 = bits(_T_10050, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_8_3 = mux(_T_10051, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10052 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10053 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10054 = eq(_T_10053, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_10055 = and(_T_10052, _T_10054) @[ifu_bp_ctl.scala 435:23] + node _T_10056 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10057 = eq(_T_10056, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_10058 = and(_T_10055, _T_10057) @[ifu_bp_ctl.scala 435:81] + node _T_10059 = or(_T_10058, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10060 = bits(_T_10059, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_8_4 = mux(_T_10060, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10061 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10062 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10063 = eq(_T_10062, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_10064 = and(_T_10061, _T_10063) @[ifu_bp_ctl.scala 435:23] + node _T_10065 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10066 = eq(_T_10065, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_10067 = and(_T_10064, _T_10066) @[ifu_bp_ctl.scala 435:81] + node _T_10068 = or(_T_10067, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10069 = bits(_T_10068, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_8_5 = mux(_T_10069, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10070 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10071 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10072 = eq(_T_10071, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_10073 = and(_T_10070, _T_10072) @[ifu_bp_ctl.scala 435:23] + node _T_10074 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10075 = eq(_T_10074, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_10076 = and(_T_10073, _T_10075) @[ifu_bp_ctl.scala 435:81] + node _T_10077 = or(_T_10076, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10078 = bits(_T_10077, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_8_6 = mux(_T_10078, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10079 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10080 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10081 = eq(_T_10080, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_10082 = and(_T_10079, _T_10081) @[ifu_bp_ctl.scala 435:23] + node _T_10083 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10084 = eq(_T_10083, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_10085 = and(_T_10082, _T_10084) @[ifu_bp_ctl.scala 435:81] + node _T_10086 = or(_T_10085, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10087 = bits(_T_10086, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_8_7 = mux(_T_10087, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10088 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10089 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10090 = eq(_T_10089, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_10091 = and(_T_10088, _T_10090) @[ifu_bp_ctl.scala 435:23] + node _T_10092 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10093 = eq(_T_10092, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_10094 = and(_T_10091, _T_10093) @[ifu_bp_ctl.scala 435:81] + node _T_10095 = or(_T_10094, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10096 = bits(_T_10095, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_8_8 = mux(_T_10096, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10097 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10098 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10099 = eq(_T_10098, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_10100 = and(_T_10097, _T_10099) @[ifu_bp_ctl.scala 435:23] + node _T_10101 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10102 = eq(_T_10101, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_10103 = and(_T_10100, _T_10102) @[ifu_bp_ctl.scala 435:81] + node _T_10104 = or(_T_10103, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10105 = bits(_T_10104, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_8_9 = mux(_T_10105, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10106 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10107 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10108 = eq(_T_10107, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_10109 = and(_T_10106, _T_10108) @[ifu_bp_ctl.scala 435:23] + node _T_10110 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10111 = eq(_T_10110, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_10112 = and(_T_10109, _T_10111) @[ifu_bp_ctl.scala 435:81] + node _T_10113 = or(_T_10112, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10114 = bits(_T_10113, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_8_10 = mux(_T_10114, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10115 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10116 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10117 = eq(_T_10116, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_10118 = and(_T_10115, _T_10117) @[ifu_bp_ctl.scala 435:23] + node _T_10119 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10120 = eq(_T_10119, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_10121 = and(_T_10118, _T_10120) @[ifu_bp_ctl.scala 435:81] + node _T_10122 = or(_T_10121, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10123 = bits(_T_10122, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_8_11 = mux(_T_10123, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10124 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10125 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10126 = eq(_T_10125, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_10127 = and(_T_10124, _T_10126) @[ifu_bp_ctl.scala 435:23] + node _T_10128 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10129 = eq(_T_10128, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_10130 = and(_T_10127, _T_10129) @[ifu_bp_ctl.scala 435:81] + node _T_10131 = or(_T_10130, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10132 = bits(_T_10131, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_8_12 = mux(_T_10132, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10133 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10134 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10135 = eq(_T_10134, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_10136 = and(_T_10133, _T_10135) @[ifu_bp_ctl.scala 435:23] + node _T_10137 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10138 = eq(_T_10137, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_10139 = and(_T_10136, _T_10138) @[ifu_bp_ctl.scala 435:81] + node _T_10140 = or(_T_10139, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10141 = bits(_T_10140, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_8_13 = mux(_T_10141, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10142 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10143 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10144 = eq(_T_10143, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_10145 = and(_T_10142, _T_10144) @[ifu_bp_ctl.scala 435:23] + node _T_10146 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10147 = eq(_T_10146, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_10148 = and(_T_10145, _T_10147) @[ifu_bp_ctl.scala 435:81] + node _T_10149 = or(_T_10148, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10150 = bits(_T_10149, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_8_14 = mux(_T_10150, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10151 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10152 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10153 = eq(_T_10152, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_10154 = and(_T_10151, _T_10153) @[ifu_bp_ctl.scala 435:23] + node _T_10155 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10156 = eq(_T_10155, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:154] + node _T_10157 = and(_T_10154, _T_10156) @[ifu_bp_ctl.scala 435:81] + node _T_10158 = or(_T_10157, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10159 = bits(_T_10158, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_8_15 = mux(_T_10159, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10160 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10161 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10162 = eq(_T_10161, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_10163 = and(_T_10160, _T_10162) @[ifu_bp_ctl.scala 435:23] + node _T_10164 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10165 = eq(_T_10164, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_10166 = and(_T_10163, _T_10165) @[ifu_bp_ctl.scala 435:81] + node _T_10167 = or(_T_10166, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10168 = bits(_T_10167, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_9_0 = mux(_T_10168, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10169 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10170 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10171 = eq(_T_10170, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_10172 = and(_T_10169, _T_10171) @[ifu_bp_ctl.scala 435:23] + node _T_10173 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10174 = eq(_T_10173, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_10175 = and(_T_10172, _T_10174) @[ifu_bp_ctl.scala 435:81] + node _T_10176 = or(_T_10175, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10177 = bits(_T_10176, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_9_1 = mux(_T_10177, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10178 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10179 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10180 = eq(_T_10179, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_10181 = and(_T_10178, _T_10180) @[ifu_bp_ctl.scala 435:23] + node _T_10182 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10183 = eq(_T_10182, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_10184 = and(_T_10181, _T_10183) @[ifu_bp_ctl.scala 435:81] + node _T_10185 = or(_T_10184, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10186 = bits(_T_10185, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_9_2 = mux(_T_10186, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10187 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10188 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10189 = eq(_T_10188, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_10190 = and(_T_10187, _T_10189) @[ifu_bp_ctl.scala 435:23] + node _T_10191 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10192 = eq(_T_10191, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_10193 = and(_T_10190, _T_10192) @[ifu_bp_ctl.scala 435:81] + node _T_10194 = or(_T_10193, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10195 = bits(_T_10194, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_9_3 = mux(_T_10195, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10196 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10197 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10198 = eq(_T_10197, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_10199 = and(_T_10196, _T_10198) @[ifu_bp_ctl.scala 435:23] + node _T_10200 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10201 = eq(_T_10200, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_10202 = and(_T_10199, _T_10201) @[ifu_bp_ctl.scala 435:81] + node _T_10203 = or(_T_10202, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10204 = bits(_T_10203, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_9_4 = mux(_T_10204, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10205 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10206 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10207 = eq(_T_10206, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_10208 = and(_T_10205, _T_10207) @[ifu_bp_ctl.scala 435:23] + node _T_10209 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10210 = eq(_T_10209, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_10211 = and(_T_10208, _T_10210) @[ifu_bp_ctl.scala 435:81] + node _T_10212 = or(_T_10211, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10213 = bits(_T_10212, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_9_5 = mux(_T_10213, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10214 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10215 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10216 = eq(_T_10215, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_10217 = and(_T_10214, _T_10216) @[ifu_bp_ctl.scala 435:23] + node _T_10218 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10219 = eq(_T_10218, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_10220 = and(_T_10217, _T_10219) @[ifu_bp_ctl.scala 435:81] + node _T_10221 = or(_T_10220, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10222 = bits(_T_10221, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_9_6 = mux(_T_10222, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10223 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10224 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10225 = eq(_T_10224, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_10226 = and(_T_10223, _T_10225) @[ifu_bp_ctl.scala 435:23] + node _T_10227 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10228 = eq(_T_10227, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_10229 = and(_T_10226, _T_10228) @[ifu_bp_ctl.scala 435:81] + node _T_10230 = or(_T_10229, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10231 = bits(_T_10230, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_9_7 = mux(_T_10231, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10232 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10233 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10234 = eq(_T_10233, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_10235 = and(_T_10232, _T_10234) @[ifu_bp_ctl.scala 435:23] + node _T_10236 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10237 = eq(_T_10236, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_10238 = and(_T_10235, _T_10237) @[ifu_bp_ctl.scala 435:81] + node _T_10239 = or(_T_10238, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10240 = bits(_T_10239, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_9_8 = mux(_T_10240, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10241 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10242 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10243 = eq(_T_10242, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_10244 = and(_T_10241, _T_10243) @[ifu_bp_ctl.scala 435:23] + node _T_10245 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10246 = eq(_T_10245, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_10247 = and(_T_10244, _T_10246) @[ifu_bp_ctl.scala 435:81] + node _T_10248 = or(_T_10247, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10249 = bits(_T_10248, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_9_9 = mux(_T_10249, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10250 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10251 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10252 = eq(_T_10251, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_10253 = and(_T_10250, _T_10252) @[ifu_bp_ctl.scala 435:23] + node _T_10254 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10255 = eq(_T_10254, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_10256 = and(_T_10253, _T_10255) @[ifu_bp_ctl.scala 435:81] + node _T_10257 = or(_T_10256, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10258 = bits(_T_10257, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_9_10 = mux(_T_10258, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10259 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10260 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10261 = eq(_T_10260, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_10262 = and(_T_10259, _T_10261) @[ifu_bp_ctl.scala 435:23] + node _T_10263 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10264 = eq(_T_10263, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_10265 = and(_T_10262, _T_10264) @[ifu_bp_ctl.scala 435:81] + node _T_10266 = or(_T_10265, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10267 = bits(_T_10266, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_9_11 = mux(_T_10267, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10268 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10269 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10270 = eq(_T_10269, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_10271 = and(_T_10268, _T_10270) @[ifu_bp_ctl.scala 435:23] + node _T_10272 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10273 = eq(_T_10272, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_10274 = and(_T_10271, _T_10273) @[ifu_bp_ctl.scala 435:81] + node _T_10275 = or(_T_10274, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10276 = bits(_T_10275, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_9_12 = mux(_T_10276, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10277 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10278 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10279 = eq(_T_10278, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_10280 = and(_T_10277, _T_10279) @[ifu_bp_ctl.scala 435:23] + node _T_10281 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10282 = eq(_T_10281, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_10283 = and(_T_10280, _T_10282) @[ifu_bp_ctl.scala 435:81] + node _T_10284 = or(_T_10283, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10285 = bits(_T_10284, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_9_13 = mux(_T_10285, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10286 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10287 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10288 = eq(_T_10287, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_10289 = and(_T_10286, _T_10288) @[ifu_bp_ctl.scala 435:23] + node _T_10290 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10291 = eq(_T_10290, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_10292 = and(_T_10289, _T_10291) @[ifu_bp_ctl.scala 435:81] + node _T_10293 = or(_T_10292, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10294 = bits(_T_10293, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_9_14 = mux(_T_10294, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10295 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10296 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10297 = eq(_T_10296, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_10298 = and(_T_10295, _T_10297) @[ifu_bp_ctl.scala 435:23] + node _T_10299 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10300 = eq(_T_10299, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:154] + node _T_10301 = and(_T_10298, _T_10300) @[ifu_bp_ctl.scala 435:81] + node _T_10302 = or(_T_10301, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10303 = bits(_T_10302, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_9_15 = mux(_T_10303, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10304 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10305 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10306 = eq(_T_10305, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_10307 = and(_T_10304, _T_10306) @[ifu_bp_ctl.scala 435:23] + node _T_10308 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10309 = eq(_T_10308, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_10310 = and(_T_10307, _T_10309) @[ifu_bp_ctl.scala 435:81] + node _T_10311 = or(_T_10310, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10312 = bits(_T_10311, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_10_0 = mux(_T_10312, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10313 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10314 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10315 = eq(_T_10314, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_10316 = and(_T_10313, _T_10315) @[ifu_bp_ctl.scala 435:23] + node _T_10317 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10318 = eq(_T_10317, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_10319 = and(_T_10316, _T_10318) @[ifu_bp_ctl.scala 435:81] + node _T_10320 = or(_T_10319, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10321 = bits(_T_10320, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_10_1 = mux(_T_10321, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10322 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10323 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10324 = eq(_T_10323, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_10325 = and(_T_10322, _T_10324) @[ifu_bp_ctl.scala 435:23] + node _T_10326 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10327 = eq(_T_10326, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_10328 = and(_T_10325, _T_10327) @[ifu_bp_ctl.scala 435:81] + node _T_10329 = or(_T_10328, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10330 = bits(_T_10329, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_10_2 = mux(_T_10330, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10331 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10332 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10333 = eq(_T_10332, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_10334 = and(_T_10331, _T_10333) @[ifu_bp_ctl.scala 435:23] + node _T_10335 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10336 = eq(_T_10335, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_10337 = and(_T_10334, _T_10336) @[ifu_bp_ctl.scala 435:81] + node _T_10338 = or(_T_10337, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10339 = bits(_T_10338, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_10_3 = mux(_T_10339, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10340 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10341 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10342 = eq(_T_10341, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_10343 = and(_T_10340, _T_10342) @[ifu_bp_ctl.scala 435:23] + node _T_10344 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10345 = eq(_T_10344, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_10346 = and(_T_10343, _T_10345) @[ifu_bp_ctl.scala 435:81] + node _T_10347 = or(_T_10346, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10348 = bits(_T_10347, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_10_4 = mux(_T_10348, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10349 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10350 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10351 = eq(_T_10350, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_10352 = and(_T_10349, _T_10351) @[ifu_bp_ctl.scala 435:23] + node _T_10353 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10354 = eq(_T_10353, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_10355 = and(_T_10352, _T_10354) @[ifu_bp_ctl.scala 435:81] + node _T_10356 = or(_T_10355, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10357 = bits(_T_10356, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_10_5 = mux(_T_10357, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10358 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10359 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10360 = eq(_T_10359, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_10361 = and(_T_10358, _T_10360) @[ifu_bp_ctl.scala 435:23] + node _T_10362 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10363 = eq(_T_10362, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_10364 = and(_T_10361, _T_10363) @[ifu_bp_ctl.scala 435:81] + node _T_10365 = or(_T_10364, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10366 = bits(_T_10365, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_10_6 = mux(_T_10366, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10367 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10368 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10369 = eq(_T_10368, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_10370 = and(_T_10367, _T_10369) @[ifu_bp_ctl.scala 435:23] + node _T_10371 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10372 = eq(_T_10371, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_10373 = and(_T_10370, _T_10372) @[ifu_bp_ctl.scala 435:81] + node _T_10374 = or(_T_10373, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10375 = bits(_T_10374, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_10_7 = mux(_T_10375, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10376 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10377 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10378 = eq(_T_10377, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_10379 = and(_T_10376, _T_10378) @[ifu_bp_ctl.scala 435:23] + node _T_10380 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10381 = eq(_T_10380, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_10382 = and(_T_10379, _T_10381) @[ifu_bp_ctl.scala 435:81] + node _T_10383 = or(_T_10382, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10384 = bits(_T_10383, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_10_8 = mux(_T_10384, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10385 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10386 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10387 = eq(_T_10386, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_10388 = and(_T_10385, _T_10387) @[ifu_bp_ctl.scala 435:23] + node _T_10389 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10390 = eq(_T_10389, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_10391 = and(_T_10388, _T_10390) @[ifu_bp_ctl.scala 435:81] + node _T_10392 = or(_T_10391, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10393 = bits(_T_10392, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_10_9 = mux(_T_10393, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10394 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10395 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10396 = eq(_T_10395, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_10397 = and(_T_10394, _T_10396) @[ifu_bp_ctl.scala 435:23] + node _T_10398 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10399 = eq(_T_10398, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_10400 = and(_T_10397, _T_10399) @[ifu_bp_ctl.scala 435:81] + node _T_10401 = or(_T_10400, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10402 = bits(_T_10401, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_10_10 = mux(_T_10402, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10403 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10404 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10405 = eq(_T_10404, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_10406 = and(_T_10403, _T_10405) @[ifu_bp_ctl.scala 435:23] + node _T_10407 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10408 = eq(_T_10407, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_10409 = and(_T_10406, _T_10408) @[ifu_bp_ctl.scala 435:81] + node _T_10410 = or(_T_10409, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10411 = bits(_T_10410, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_10_11 = mux(_T_10411, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10412 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10413 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10414 = eq(_T_10413, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_10415 = and(_T_10412, _T_10414) @[ifu_bp_ctl.scala 435:23] + node _T_10416 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10417 = eq(_T_10416, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_10418 = and(_T_10415, _T_10417) @[ifu_bp_ctl.scala 435:81] + node _T_10419 = or(_T_10418, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10420 = bits(_T_10419, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_10_12 = mux(_T_10420, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10421 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10422 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10423 = eq(_T_10422, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_10424 = and(_T_10421, _T_10423) @[ifu_bp_ctl.scala 435:23] + node _T_10425 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10426 = eq(_T_10425, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_10427 = and(_T_10424, _T_10426) @[ifu_bp_ctl.scala 435:81] + node _T_10428 = or(_T_10427, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10429 = bits(_T_10428, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_10_13 = mux(_T_10429, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10430 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10431 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10432 = eq(_T_10431, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_10433 = and(_T_10430, _T_10432) @[ifu_bp_ctl.scala 435:23] + node _T_10434 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10435 = eq(_T_10434, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_10436 = and(_T_10433, _T_10435) @[ifu_bp_ctl.scala 435:81] + node _T_10437 = or(_T_10436, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10438 = bits(_T_10437, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_10_14 = mux(_T_10438, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10439 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10440 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10441 = eq(_T_10440, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_10442 = and(_T_10439, _T_10441) @[ifu_bp_ctl.scala 435:23] + node _T_10443 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10444 = eq(_T_10443, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:154] + node _T_10445 = and(_T_10442, _T_10444) @[ifu_bp_ctl.scala 435:81] + node _T_10446 = or(_T_10445, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10447 = bits(_T_10446, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_10_15 = mux(_T_10447, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10448 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10449 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10450 = eq(_T_10449, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_10451 = and(_T_10448, _T_10450) @[ifu_bp_ctl.scala 435:23] + node _T_10452 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10453 = eq(_T_10452, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_10454 = and(_T_10451, _T_10453) @[ifu_bp_ctl.scala 435:81] + node _T_10455 = or(_T_10454, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10456 = bits(_T_10455, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_11_0 = mux(_T_10456, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10457 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10458 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10459 = eq(_T_10458, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_10460 = and(_T_10457, _T_10459) @[ifu_bp_ctl.scala 435:23] + node _T_10461 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10462 = eq(_T_10461, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_10463 = and(_T_10460, _T_10462) @[ifu_bp_ctl.scala 435:81] + node _T_10464 = or(_T_10463, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10465 = bits(_T_10464, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_11_1 = mux(_T_10465, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10466 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10467 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10468 = eq(_T_10467, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_10469 = and(_T_10466, _T_10468) @[ifu_bp_ctl.scala 435:23] + node _T_10470 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10471 = eq(_T_10470, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_10472 = and(_T_10469, _T_10471) @[ifu_bp_ctl.scala 435:81] + node _T_10473 = or(_T_10472, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10474 = bits(_T_10473, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_11_2 = mux(_T_10474, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10475 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10476 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10477 = eq(_T_10476, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_10478 = and(_T_10475, _T_10477) @[ifu_bp_ctl.scala 435:23] + node _T_10479 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10480 = eq(_T_10479, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_10481 = and(_T_10478, _T_10480) @[ifu_bp_ctl.scala 435:81] + node _T_10482 = or(_T_10481, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10483 = bits(_T_10482, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_11_3 = mux(_T_10483, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10484 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10485 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10486 = eq(_T_10485, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_10487 = and(_T_10484, _T_10486) @[ifu_bp_ctl.scala 435:23] + node _T_10488 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10489 = eq(_T_10488, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_10490 = and(_T_10487, _T_10489) @[ifu_bp_ctl.scala 435:81] + node _T_10491 = or(_T_10490, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10492 = bits(_T_10491, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_11_4 = mux(_T_10492, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10493 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10494 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10495 = eq(_T_10494, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_10496 = and(_T_10493, _T_10495) @[ifu_bp_ctl.scala 435:23] + node _T_10497 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10498 = eq(_T_10497, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_10499 = and(_T_10496, _T_10498) @[ifu_bp_ctl.scala 435:81] + node _T_10500 = or(_T_10499, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10501 = bits(_T_10500, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_11_5 = mux(_T_10501, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10502 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10503 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10504 = eq(_T_10503, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_10505 = and(_T_10502, _T_10504) @[ifu_bp_ctl.scala 435:23] + node _T_10506 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10507 = eq(_T_10506, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_10508 = and(_T_10505, _T_10507) @[ifu_bp_ctl.scala 435:81] + node _T_10509 = or(_T_10508, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10510 = bits(_T_10509, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_11_6 = mux(_T_10510, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10511 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10512 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10513 = eq(_T_10512, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_10514 = and(_T_10511, _T_10513) @[ifu_bp_ctl.scala 435:23] + node _T_10515 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10516 = eq(_T_10515, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_10517 = and(_T_10514, _T_10516) @[ifu_bp_ctl.scala 435:81] + node _T_10518 = or(_T_10517, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10519 = bits(_T_10518, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_11_7 = mux(_T_10519, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10520 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10521 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10522 = eq(_T_10521, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_10523 = and(_T_10520, _T_10522) @[ifu_bp_ctl.scala 435:23] + node _T_10524 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10525 = eq(_T_10524, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_10526 = and(_T_10523, _T_10525) @[ifu_bp_ctl.scala 435:81] + node _T_10527 = or(_T_10526, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10528 = bits(_T_10527, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_11_8 = mux(_T_10528, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10529 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10530 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10531 = eq(_T_10530, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_10532 = and(_T_10529, _T_10531) @[ifu_bp_ctl.scala 435:23] + node _T_10533 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10534 = eq(_T_10533, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_10535 = and(_T_10532, _T_10534) @[ifu_bp_ctl.scala 435:81] + node _T_10536 = or(_T_10535, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10537 = bits(_T_10536, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_11_9 = mux(_T_10537, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10538 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10539 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10540 = eq(_T_10539, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_10541 = and(_T_10538, _T_10540) @[ifu_bp_ctl.scala 435:23] + node _T_10542 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10543 = eq(_T_10542, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_10544 = and(_T_10541, _T_10543) @[ifu_bp_ctl.scala 435:81] + node _T_10545 = or(_T_10544, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10546 = bits(_T_10545, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_11_10 = mux(_T_10546, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10547 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10548 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10549 = eq(_T_10548, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_10550 = and(_T_10547, _T_10549) @[ifu_bp_ctl.scala 435:23] + node _T_10551 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10552 = eq(_T_10551, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_10553 = and(_T_10550, _T_10552) @[ifu_bp_ctl.scala 435:81] + node _T_10554 = or(_T_10553, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10555 = bits(_T_10554, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_11_11 = mux(_T_10555, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10556 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10557 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10558 = eq(_T_10557, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_10559 = and(_T_10556, _T_10558) @[ifu_bp_ctl.scala 435:23] + node _T_10560 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10561 = eq(_T_10560, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_10562 = and(_T_10559, _T_10561) @[ifu_bp_ctl.scala 435:81] + node _T_10563 = or(_T_10562, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10564 = bits(_T_10563, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_11_12 = mux(_T_10564, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10565 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10566 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10567 = eq(_T_10566, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_10568 = and(_T_10565, _T_10567) @[ifu_bp_ctl.scala 435:23] + node _T_10569 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10570 = eq(_T_10569, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_10571 = and(_T_10568, _T_10570) @[ifu_bp_ctl.scala 435:81] + node _T_10572 = or(_T_10571, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10573 = bits(_T_10572, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_11_13 = mux(_T_10573, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10574 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10575 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10576 = eq(_T_10575, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_10577 = and(_T_10574, _T_10576) @[ifu_bp_ctl.scala 435:23] + node _T_10578 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10579 = eq(_T_10578, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_10580 = and(_T_10577, _T_10579) @[ifu_bp_ctl.scala 435:81] + node _T_10581 = or(_T_10580, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10582 = bits(_T_10581, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_11_14 = mux(_T_10582, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10583 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10584 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10585 = eq(_T_10584, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_10586 = and(_T_10583, _T_10585) @[ifu_bp_ctl.scala 435:23] + node _T_10587 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10588 = eq(_T_10587, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:154] + node _T_10589 = and(_T_10586, _T_10588) @[ifu_bp_ctl.scala 435:81] + node _T_10590 = or(_T_10589, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10591 = bits(_T_10590, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_11_15 = mux(_T_10591, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10592 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10593 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10594 = eq(_T_10593, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_10595 = and(_T_10592, _T_10594) @[ifu_bp_ctl.scala 435:23] + node _T_10596 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10597 = eq(_T_10596, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_10598 = and(_T_10595, _T_10597) @[ifu_bp_ctl.scala 435:81] + node _T_10599 = or(_T_10598, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10600 = bits(_T_10599, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_12_0 = mux(_T_10600, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10601 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10602 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10603 = eq(_T_10602, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_10604 = and(_T_10601, _T_10603) @[ifu_bp_ctl.scala 435:23] + node _T_10605 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10606 = eq(_T_10605, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_10607 = and(_T_10604, _T_10606) @[ifu_bp_ctl.scala 435:81] + node _T_10608 = or(_T_10607, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10609 = bits(_T_10608, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_12_1 = mux(_T_10609, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10610 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10611 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10612 = eq(_T_10611, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_10613 = and(_T_10610, _T_10612) @[ifu_bp_ctl.scala 435:23] + node _T_10614 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10615 = eq(_T_10614, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_10616 = and(_T_10613, _T_10615) @[ifu_bp_ctl.scala 435:81] + node _T_10617 = or(_T_10616, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10618 = bits(_T_10617, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_12_2 = mux(_T_10618, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10619 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10620 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10621 = eq(_T_10620, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_10622 = and(_T_10619, _T_10621) @[ifu_bp_ctl.scala 435:23] + node _T_10623 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10624 = eq(_T_10623, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_10625 = and(_T_10622, _T_10624) @[ifu_bp_ctl.scala 435:81] + node _T_10626 = or(_T_10625, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10627 = bits(_T_10626, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_12_3 = mux(_T_10627, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10628 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10629 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10630 = eq(_T_10629, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_10631 = and(_T_10628, _T_10630) @[ifu_bp_ctl.scala 435:23] + node _T_10632 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10633 = eq(_T_10632, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_10634 = and(_T_10631, _T_10633) @[ifu_bp_ctl.scala 435:81] + node _T_10635 = or(_T_10634, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10636 = bits(_T_10635, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_12_4 = mux(_T_10636, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10637 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10638 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10639 = eq(_T_10638, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_10640 = and(_T_10637, _T_10639) @[ifu_bp_ctl.scala 435:23] + node _T_10641 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10642 = eq(_T_10641, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_10643 = and(_T_10640, _T_10642) @[ifu_bp_ctl.scala 435:81] + node _T_10644 = or(_T_10643, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10645 = bits(_T_10644, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_12_5 = mux(_T_10645, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10646 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10647 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10648 = eq(_T_10647, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_10649 = and(_T_10646, _T_10648) @[ifu_bp_ctl.scala 435:23] + node _T_10650 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10651 = eq(_T_10650, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_10652 = and(_T_10649, _T_10651) @[ifu_bp_ctl.scala 435:81] + node _T_10653 = or(_T_10652, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10654 = bits(_T_10653, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_12_6 = mux(_T_10654, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10655 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10656 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10657 = eq(_T_10656, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_10658 = and(_T_10655, _T_10657) @[ifu_bp_ctl.scala 435:23] + node _T_10659 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10660 = eq(_T_10659, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_10661 = and(_T_10658, _T_10660) @[ifu_bp_ctl.scala 435:81] + node _T_10662 = or(_T_10661, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10663 = bits(_T_10662, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_12_7 = mux(_T_10663, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10664 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10665 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10666 = eq(_T_10665, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_10667 = and(_T_10664, _T_10666) @[ifu_bp_ctl.scala 435:23] + node _T_10668 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10669 = eq(_T_10668, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_10670 = and(_T_10667, _T_10669) @[ifu_bp_ctl.scala 435:81] + node _T_10671 = or(_T_10670, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10672 = bits(_T_10671, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_12_8 = mux(_T_10672, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10673 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10674 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10675 = eq(_T_10674, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_10676 = and(_T_10673, _T_10675) @[ifu_bp_ctl.scala 435:23] + node _T_10677 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10678 = eq(_T_10677, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_10679 = and(_T_10676, _T_10678) @[ifu_bp_ctl.scala 435:81] + node _T_10680 = or(_T_10679, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10681 = bits(_T_10680, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_12_9 = mux(_T_10681, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10682 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10683 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10684 = eq(_T_10683, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_10685 = and(_T_10682, _T_10684) @[ifu_bp_ctl.scala 435:23] + node _T_10686 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10687 = eq(_T_10686, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_10688 = and(_T_10685, _T_10687) @[ifu_bp_ctl.scala 435:81] + node _T_10689 = or(_T_10688, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10690 = bits(_T_10689, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_12_10 = mux(_T_10690, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10691 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10692 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10693 = eq(_T_10692, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_10694 = and(_T_10691, _T_10693) @[ifu_bp_ctl.scala 435:23] + node _T_10695 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10696 = eq(_T_10695, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_10697 = and(_T_10694, _T_10696) @[ifu_bp_ctl.scala 435:81] + node _T_10698 = or(_T_10697, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10699 = bits(_T_10698, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_12_11 = mux(_T_10699, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10700 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10701 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10702 = eq(_T_10701, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_10703 = and(_T_10700, _T_10702) @[ifu_bp_ctl.scala 435:23] + node _T_10704 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10705 = eq(_T_10704, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_10706 = and(_T_10703, _T_10705) @[ifu_bp_ctl.scala 435:81] + node _T_10707 = or(_T_10706, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10708 = bits(_T_10707, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_12_12 = mux(_T_10708, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10709 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10710 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10711 = eq(_T_10710, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_10712 = and(_T_10709, _T_10711) @[ifu_bp_ctl.scala 435:23] + node _T_10713 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10714 = eq(_T_10713, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_10715 = and(_T_10712, _T_10714) @[ifu_bp_ctl.scala 435:81] + node _T_10716 = or(_T_10715, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10717 = bits(_T_10716, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_12_13 = mux(_T_10717, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10718 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10719 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10720 = eq(_T_10719, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_10721 = and(_T_10718, _T_10720) @[ifu_bp_ctl.scala 435:23] + node _T_10722 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10723 = eq(_T_10722, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_10724 = and(_T_10721, _T_10723) @[ifu_bp_ctl.scala 435:81] + node _T_10725 = or(_T_10724, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10726 = bits(_T_10725, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_12_14 = mux(_T_10726, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10727 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10728 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10729 = eq(_T_10728, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_10730 = and(_T_10727, _T_10729) @[ifu_bp_ctl.scala 435:23] + node _T_10731 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10732 = eq(_T_10731, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:154] + node _T_10733 = and(_T_10730, _T_10732) @[ifu_bp_ctl.scala 435:81] + node _T_10734 = or(_T_10733, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10735 = bits(_T_10734, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_12_15 = mux(_T_10735, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10736 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10737 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10738 = eq(_T_10737, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_10739 = and(_T_10736, _T_10738) @[ifu_bp_ctl.scala 435:23] + node _T_10740 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10741 = eq(_T_10740, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_10742 = and(_T_10739, _T_10741) @[ifu_bp_ctl.scala 435:81] + node _T_10743 = or(_T_10742, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10744 = bits(_T_10743, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_13_0 = mux(_T_10744, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10745 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10746 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10747 = eq(_T_10746, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_10748 = and(_T_10745, _T_10747) @[ifu_bp_ctl.scala 435:23] + node _T_10749 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10750 = eq(_T_10749, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_10751 = and(_T_10748, _T_10750) @[ifu_bp_ctl.scala 435:81] + node _T_10752 = or(_T_10751, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10753 = bits(_T_10752, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_13_1 = mux(_T_10753, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10754 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10755 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10756 = eq(_T_10755, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_10757 = and(_T_10754, _T_10756) @[ifu_bp_ctl.scala 435:23] + node _T_10758 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10759 = eq(_T_10758, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_10760 = and(_T_10757, _T_10759) @[ifu_bp_ctl.scala 435:81] + node _T_10761 = or(_T_10760, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10762 = bits(_T_10761, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_13_2 = mux(_T_10762, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10763 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10764 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10765 = eq(_T_10764, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_10766 = and(_T_10763, _T_10765) @[ifu_bp_ctl.scala 435:23] + node _T_10767 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10768 = eq(_T_10767, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_10769 = and(_T_10766, _T_10768) @[ifu_bp_ctl.scala 435:81] + node _T_10770 = or(_T_10769, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10771 = bits(_T_10770, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_13_3 = mux(_T_10771, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10772 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10773 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10774 = eq(_T_10773, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_10775 = and(_T_10772, _T_10774) @[ifu_bp_ctl.scala 435:23] + node _T_10776 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10777 = eq(_T_10776, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_10778 = and(_T_10775, _T_10777) @[ifu_bp_ctl.scala 435:81] + node _T_10779 = or(_T_10778, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10780 = bits(_T_10779, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_13_4 = mux(_T_10780, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10781 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10782 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10783 = eq(_T_10782, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_10784 = and(_T_10781, _T_10783) @[ifu_bp_ctl.scala 435:23] + node _T_10785 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10786 = eq(_T_10785, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_10787 = and(_T_10784, _T_10786) @[ifu_bp_ctl.scala 435:81] + node _T_10788 = or(_T_10787, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10789 = bits(_T_10788, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_13_5 = mux(_T_10789, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10790 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10791 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10792 = eq(_T_10791, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_10793 = and(_T_10790, _T_10792) @[ifu_bp_ctl.scala 435:23] + node _T_10794 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10795 = eq(_T_10794, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_10796 = and(_T_10793, _T_10795) @[ifu_bp_ctl.scala 435:81] + node _T_10797 = or(_T_10796, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10798 = bits(_T_10797, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_13_6 = mux(_T_10798, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10799 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10800 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10801 = eq(_T_10800, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_10802 = and(_T_10799, _T_10801) @[ifu_bp_ctl.scala 435:23] + node _T_10803 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10804 = eq(_T_10803, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_10805 = and(_T_10802, _T_10804) @[ifu_bp_ctl.scala 435:81] + node _T_10806 = or(_T_10805, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10807 = bits(_T_10806, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_13_7 = mux(_T_10807, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10808 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10809 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10810 = eq(_T_10809, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_10811 = and(_T_10808, _T_10810) @[ifu_bp_ctl.scala 435:23] + node _T_10812 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10813 = eq(_T_10812, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_10814 = and(_T_10811, _T_10813) @[ifu_bp_ctl.scala 435:81] + node _T_10815 = or(_T_10814, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10816 = bits(_T_10815, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_13_8 = mux(_T_10816, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10817 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10818 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10819 = eq(_T_10818, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_10820 = and(_T_10817, _T_10819) @[ifu_bp_ctl.scala 435:23] + node _T_10821 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10822 = eq(_T_10821, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_10823 = and(_T_10820, _T_10822) @[ifu_bp_ctl.scala 435:81] + node _T_10824 = or(_T_10823, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10825 = bits(_T_10824, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_13_9 = mux(_T_10825, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10826 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10827 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10828 = eq(_T_10827, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_10829 = and(_T_10826, _T_10828) @[ifu_bp_ctl.scala 435:23] + node _T_10830 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10831 = eq(_T_10830, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_10832 = and(_T_10829, _T_10831) @[ifu_bp_ctl.scala 435:81] + node _T_10833 = or(_T_10832, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10834 = bits(_T_10833, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_13_10 = mux(_T_10834, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10835 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10836 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10837 = eq(_T_10836, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_10838 = and(_T_10835, _T_10837) @[ifu_bp_ctl.scala 435:23] + node _T_10839 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10840 = eq(_T_10839, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_10841 = and(_T_10838, _T_10840) @[ifu_bp_ctl.scala 435:81] + node _T_10842 = or(_T_10841, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10843 = bits(_T_10842, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_13_11 = mux(_T_10843, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10844 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10845 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10846 = eq(_T_10845, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_10847 = and(_T_10844, _T_10846) @[ifu_bp_ctl.scala 435:23] + node _T_10848 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10849 = eq(_T_10848, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_10850 = and(_T_10847, _T_10849) @[ifu_bp_ctl.scala 435:81] + node _T_10851 = or(_T_10850, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10852 = bits(_T_10851, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_13_12 = mux(_T_10852, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10853 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10854 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10855 = eq(_T_10854, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_10856 = and(_T_10853, _T_10855) @[ifu_bp_ctl.scala 435:23] + node _T_10857 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10858 = eq(_T_10857, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_10859 = and(_T_10856, _T_10858) @[ifu_bp_ctl.scala 435:81] + node _T_10860 = or(_T_10859, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10861 = bits(_T_10860, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_13_13 = mux(_T_10861, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10862 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10863 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10864 = eq(_T_10863, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_10865 = and(_T_10862, _T_10864) @[ifu_bp_ctl.scala 435:23] + node _T_10866 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10867 = eq(_T_10866, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_10868 = and(_T_10865, _T_10867) @[ifu_bp_ctl.scala 435:81] + node _T_10869 = or(_T_10868, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10870 = bits(_T_10869, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_13_14 = mux(_T_10870, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10871 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10872 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10873 = eq(_T_10872, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_10874 = and(_T_10871, _T_10873) @[ifu_bp_ctl.scala 435:23] + node _T_10875 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10876 = eq(_T_10875, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:154] + node _T_10877 = and(_T_10874, _T_10876) @[ifu_bp_ctl.scala 435:81] + node _T_10878 = or(_T_10877, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10879 = bits(_T_10878, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_13_15 = mux(_T_10879, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10880 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10881 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10882 = eq(_T_10881, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_10883 = and(_T_10880, _T_10882) @[ifu_bp_ctl.scala 435:23] + node _T_10884 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10885 = eq(_T_10884, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_10886 = and(_T_10883, _T_10885) @[ifu_bp_ctl.scala 435:81] + node _T_10887 = or(_T_10886, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10888 = bits(_T_10887, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_14_0 = mux(_T_10888, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10889 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10890 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10891 = eq(_T_10890, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_10892 = and(_T_10889, _T_10891) @[ifu_bp_ctl.scala 435:23] + node _T_10893 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10894 = eq(_T_10893, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_10895 = and(_T_10892, _T_10894) @[ifu_bp_ctl.scala 435:81] + node _T_10896 = or(_T_10895, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10897 = bits(_T_10896, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_14_1 = mux(_T_10897, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10898 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10899 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10900 = eq(_T_10899, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_10901 = and(_T_10898, _T_10900) @[ifu_bp_ctl.scala 435:23] + node _T_10902 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10903 = eq(_T_10902, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_10904 = and(_T_10901, _T_10903) @[ifu_bp_ctl.scala 435:81] + node _T_10905 = or(_T_10904, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10906 = bits(_T_10905, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_14_2 = mux(_T_10906, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10907 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10908 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10909 = eq(_T_10908, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_10910 = and(_T_10907, _T_10909) @[ifu_bp_ctl.scala 435:23] + node _T_10911 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10912 = eq(_T_10911, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_10913 = and(_T_10910, _T_10912) @[ifu_bp_ctl.scala 435:81] + node _T_10914 = or(_T_10913, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10915 = bits(_T_10914, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_14_3 = mux(_T_10915, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10916 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10917 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10918 = eq(_T_10917, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_10919 = and(_T_10916, _T_10918) @[ifu_bp_ctl.scala 435:23] + node _T_10920 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10921 = eq(_T_10920, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_10922 = and(_T_10919, _T_10921) @[ifu_bp_ctl.scala 435:81] + node _T_10923 = or(_T_10922, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10924 = bits(_T_10923, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_14_4 = mux(_T_10924, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10925 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10926 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10927 = eq(_T_10926, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_10928 = and(_T_10925, _T_10927) @[ifu_bp_ctl.scala 435:23] + node _T_10929 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10930 = eq(_T_10929, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_10931 = and(_T_10928, _T_10930) @[ifu_bp_ctl.scala 435:81] + node _T_10932 = or(_T_10931, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10933 = bits(_T_10932, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_14_5 = mux(_T_10933, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10934 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10935 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10936 = eq(_T_10935, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_10937 = and(_T_10934, _T_10936) @[ifu_bp_ctl.scala 435:23] + node _T_10938 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10939 = eq(_T_10938, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_10940 = and(_T_10937, _T_10939) @[ifu_bp_ctl.scala 435:81] + node _T_10941 = or(_T_10940, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10942 = bits(_T_10941, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_14_6 = mux(_T_10942, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10943 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10944 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10945 = eq(_T_10944, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_10946 = and(_T_10943, _T_10945) @[ifu_bp_ctl.scala 435:23] + node _T_10947 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10948 = eq(_T_10947, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_10949 = and(_T_10946, _T_10948) @[ifu_bp_ctl.scala 435:81] + node _T_10950 = or(_T_10949, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10951 = bits(_T_10950, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_14_7 = mux(_T_10951, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10952 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10953 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10954 = eq(_T_10953, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_10955 = and(_T_10952, _T_10954) @[ifu_bp_ctl.scala 435:23] + node _T_10956 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10957 = eq(_T_10956, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_10958 = and(_T_10955, _T_10957) @[ifu_bp_ctl.scala 435:81] + node _T_10959 = or(_T_10958, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10960 = bits(_T_10959, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_14_8 = mux(_T_10960, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10961 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10962 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10963 = eq(_T_10962, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_10964 = and(_T_10961, _T_10963) @[ifu_bp_ctl.scala 435:23] + node _T_10965 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10966 = eq(_T_10965, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_10967 = and(_T_10964, _T_10966) @[ifu_bp_ctl.scala 435:81] + node _T_10968 = or(_T_10967, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10969 = bits(_T_10968, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_14_9 = mux(_T_10969, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10970 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10971 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10972 = eq(_T_10971, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_10973 = and(_T_10970, _T_10972) @[ifu_bp_ctl.scala 435:23] + node _T_10974 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10975 = eq(_T_10974, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_10976 = and(_T_10973, _T_10975) @[ifu_bp_ctl.scala 435:81] + node _T_10977 = or(_T_10976, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10978 = bits(_T_10977, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_14_10 = mux(_T_10978, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10979 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10980 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10981 = eq(_T_10980, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_10982 = and(_T_10979, _T_10981) @[ifu_bp_ctl.scala 435:23] + node _T_10983 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10984 = eq(_T_10983, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_10985 = and(_T_10982, _T_10984) @[ifu_bp_ctl.scala 435:81] + node _T_10986 = or(_T_10985, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10987 = bits(_T_10986, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_14_11 = mux(_T_10987, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10988 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10989 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10990 = eq(_T_10989, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_10991 = and(_T_10988, _T_10990) @[ifu_bp_ctl.scala 435:23] + node _T_10992 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_10993 = eq(_T_10992, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_10994 = and(_T_10991, _T_10993) @[ifu_bp_ctl.scala 435:81] + node _T_10995 = or(_T_10994, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_10996 = bits(_T_10995, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_14_12 = mux(_T_10996, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_10997 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_10998 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_10999 = eq(_T_10998, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_11000 = and(_T_10997, _T_10999) @[ifu_bp_ctl.scala 435:23] + node _T_11001 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_11002 = eq(_T_11001, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_11003 = and(_T_11000, _T_11002) @[ifu_bp_ctl.scala 435:81] + node _T_11004 = or(_T_11003, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_11005 = bits(_T_11004, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_14_13 = mux(_T_11005, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_11006 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_11007 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_11008 = eq(_T_11007, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_11009 = and(_T_11006, _T_11008) @[ifu_bp_ctl.scala 435:23] + node _T_11010 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_11011 = eq(_T_11010, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_11012 = and(_T_11009, _T_11011) @[ifu_bp_ctl.scala 435:81] + node _T_11013 = or(_T_11012, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_11014 = bits(_T_11013, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_14_14 = mux(_T_11014, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_11015 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_11016 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_11017 = eq(_T_11016, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_11018 = and(_T_11015, _T_11017) @[ifu_bp_ctl.scala 435:23] + node _T_11019 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_11020 = eq(_T_11019, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:154] + node _T_11021 = and(_T_11018, _T_11020) @[ifu_bp_ctl.scala 435:81] + node _T_11022 = or(_T_11021, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_11023 = bits(_T_11022, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_14_15 = mux(_T_11023, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_11024 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_11025 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_11026 = eq(_T_11025, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:74] + node _T_11027 = and(_T_11024, _T_11026) @[ifu_bp_ctl.scala 435:23] + node _T_11028 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_11029 = eq(_T_11028, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_11030 = and(_T_11027, _T_11029) @[ifu_bp_ctl.scala 435:81] + node _T_11031 = or(_T_11030, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_11032 = bits(_T_11031, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_15_0 = mux(_T_11032, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_11033 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_11034 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_11035 = eq(_T_11034, UInt<1>("h01")) @[ifu_bp_ctl.scala 435:74] + node _T_11036 = and(_T_11033, _T_11035) @[ifu_bp_ctl.scala 435:23] + node _T_11037 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_11038 = eq(_T_11037, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_11039 = and(_T_11036, _T_11038) @[ifu_bp_ctl.scala 435:81] + node _T_11040 = or(_T_11039, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_11041 = bits(_T_11040, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_15_1 = mux(_T_11041, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_11042 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_11043 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_11044 = eq(_T_11043, UInt<2>("h02")) @[ifu_bp_ctl.scala 435:74] + node _T_11045 = and(_T_11042, _T_11044) @[ifu_bp_ctl.scala 435:23] + node _T_11046 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_11047 = eq(_T_11046, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_11048 = and(_T_11045, _T_11047) @[ifu_bp_ctl.scala 435:81] + node _T_11049 = or(_T_11048, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_11050 = bits(_T_11049, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_15_2 = mux(_T_11050, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_11051 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_11052 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_11053 = eq(_T_11052, UInt<2>("h03")) @[ifu_bp_ctl.scala 435:74] + node _T_11054 = and(_T_11051, _T_11053) @[ifu_bp_ctl.scala 435:23] + node _T_11055 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_11056 = eq(_T_11055, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_11057 = and(_T_11054, _T_11056) @[ifu_bp_ctl.scala 435:81] + node _T_11058 = or(_T_11057, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_11059 = bits(_T_11058, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_15_3 = mux(_T_11059, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_11060 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_11061 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_11062 = eq(_T_11061, UInt<3>("h04")) @[ifu_bp_ctl.scala 435:74] + node _T_11063 = and(_T_11060, _T_11062) @[ifu_bp_ctl.scala 435:23] + node _T_11064 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_11065 = eq(_T_11064, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_11066 = and(_T_11063, _T_11065) @[ifu_bp_ctl.scala 435:81] + node _T_11067 = or(_T_11066, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_11068 = bits(_T_11067, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_15_4 = mux(_T_11068, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_11069 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_11070 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_11071 = eq(_T_11070, UInt<3>("h05")) @[ifu_bp_ctl.scala 435:74] + node _T_11072 = and(_T_11069, _T_11071) @[ifu_bp_ctl.scala 435:23] + node _T_11073 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_11074 = eq(_T_11073, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_11075 = and(_T_11072, _T_11074) @[ifu_bp_ctl.scala 435:81] + node _T_11076 = or(_T_11075, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_11077 = bits(_T_11076, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_15_5 = mux(_T_11077, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_11078 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_11079 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_11080 = eq(_T_11079, UInt<3>("h06")) @[ifu_bp_ctl.scala 435:74] + node _T_11081 = and(_T_11078, _T_11080) @[ifu_bp_ctl.scala 435:23] + node _T_11082 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_11083 = eq(_T_11082, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_11084 = and(_T_11081, _T_11083) @[ifu_bp_ctl.scala 435:81] + node _T_11085 = or(_T_11084, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_11086 = bits(_T_11085, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_15_6 = mux(_T_11086, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_11087 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_11088 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_11089 = eq(_T_11088, UInt<3>("h07")) @[ifu_bp_ctl.scala 435:74] + node _T_11090 = and(_T_11087, _T_11089) @[ifu_bp_ctl.scala 435:23] + node _T_11091 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_11092 = eq(_T_11091, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_11093 = and(_T_11090, _T_11092) @[ifu_bp_ctl.scala 435:81] + node _T_11094 = or(_T_11093, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_11095 = bits(_T_11094, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_15_7 = mux(_T_11095, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_11096 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_11097 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_11098 = eq(_T_11097, UInt<4>("h08")) @[ifu_bp_ctl.scala 435:74] + node _T_11099 = and(_T_11096, _T_11098) @[ifu_bp_ctl.scala 435:23] + node _T_11100 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_11101 = eq(_T_11100, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_11102 = and(_T_11099, _T_11101) @[ifu_bp_ctl.scala 435:81] + node _T_11103 = or(_T_11102, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_11104 = bits(_T_11103, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_15_8 = mux(_T_11104, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_11105 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_11106 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_11107 = eq(_T_11106, UInt<4>("h09")) @[ifu_bp_ctl.scala 435:74] + node _T_11108 = and(_T_11105, _T_11107) @[ifu_bp_ctl.scala 435:23] + node _T_11109 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_11110 = eq(_T_11109, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_11111 = and(_T_11108, _T_11110) @[ifu_bp_ctl.scala 435:81] + node _T_11112 = or(_T_11111, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_11113 = bits(_T_11112, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_15_9 = mux(_T_11113, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_11114 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_11115 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_11116 = eq(_T_11115, UInt<4>("h0a")) @[ifu_bp_ctl.scala 435:74] + node _T_11117 = and(_T_11114, _T_11116) @[ifu_bp_ctl.scala 435:23] + node _T_11118 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_11119 = eq(_T_11118, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_11120 = and(_T_11117, _T_11119) @[ifu_bp_ctl.scala 435:81] + node _T_11121 = or(_T_11120, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_11122 = bits(_T_11121, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_15_10 = mux(_T_11122, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_11123 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_11124 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_11125 = eq(_T_11124, UInt<4>("h0b")) @[ifu_bp_ctl.scala 435:74] + node _T_11126 = and(_T_11123, _T_11125) @[ifu_bp_ctl.scala 435:23] + node _T_11127 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_11128 = eq(_T_11127, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_11129 = and(_T_11126, _T_11128) @[ifu_bp_ctl.scala 435:81] + node _T_11130 = or(_T_11129, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_11131 = bits(_T_11130, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_15_11 = mux(_T_11131, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_11132 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_11133 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_11134 = eq(_T_11133, UInt<4>("h0c")) @[ifu_bp_ctl.scala 435:74] + node _T_11135 = and(_T_11132, _T_11134) @[ifu_bp_ctl.scala 435:23] + node _T_11136 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_11137 = eq(_T_11136, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_11138 = and(_T_11135, _T_11137) @[ifu_bp_ctl.scala 435:81] + node _T_11139 = or(_T_11138, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_11140 = bits(_T_11139, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_15_12 = mux(_T_11140, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_11141 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_11142 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_11143 = eq(_T_11142, UInt<4>("h0d")) @[ifu_bp_ctl.scala 435:74] + node _T_11144 = and(_T_11141, _T_11143) @[ifu_bp_ctl.scala 435:23] + node _T_11145 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_11146 = eq(_T_11145, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_11147 = and(_T_11144, _T_11146) @[ifu_bp_ctl.scala 435:81] + node _T_11148 = or(_T_11147, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_11149 = bits(_T_11148, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_15_13 = mux(_T_11149, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_11150 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_11151 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_11152 = eq(_T_11151, UInt<4>("h0e")) @[ifu_bp_ctl.scala 435:74] + node _T_11153 = and(_T_11150, _T_11152) @[ifu_bp_ctl.scala 435:23] + node _T_11154 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_11155 = eq(_T_11154, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_11156 = and(_T_11153, _T_11155) @[ifu_bp_ctl.scala 435:81] + node _T_11157 = or(_T_11156, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_11158 = bits(_T_11157, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_15_14 = mux(_T_11158, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + node _T_11159 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 435:20] + node _T_11160 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 435:37] + node _T_11161 = eq(_T_11160, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:74] + node _T_11162 = and(_T_11159, _T_11161) @[ifu_bp_ctl.scala 435:23] + node _T_11163 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 435:95] + node _T_11164 = eq(_T_11163, UInt<4>("h0f")) @[ifu_bp_ctl.scala 435:154] + node _T_11165 = and(_T_11162, _T_11164) @[ifu_bp_ctl.scala 435:81] + node _T_11166 = or(_T_11165, UInt<1>("h00")) @[ifu_bp_ctl.scala 435:161] + node _T_11167 = bits(_T_11166, 0, 0) @[ifu_bp_ctl.scala 435:183] + node bht_bank_wr_data_1_15_15 = mux(_T_11167, io.dec_bp.dec_tlu_br0_r_pkt.bits.hist, io.exu_bp.exu_mp_pkt.bits.hist) @[ifu_bp_ctl.scala 435:8] + wire bht_bank_sel : UInt<1>[16][16][2] @[ifu_bp_ctl.scala 437:26] + node _T_11168 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11169 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11170 = eq(_T_11169, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_11171 = and(_T_11168, _T_11170) @[ifu_bp_ctl.scala 443:45] + node _T_11172 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11173 = eq(_T_11172, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_11174 = or(_T_11173, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11175 = and(_T_11171, _T_11174) @[ifu_bp_ctl.scala 443:110] + node _T_11176 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11177 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11178 = eq(_T_11177, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_11179 = and(_T_11176, _T_11178) @[ifu_bp_ctl.scala 444:22] + node _T_11180 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11181 = eq(_T_11180, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_11182 = or(_T_11181, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11183 = and(_T_11179, _T_11182) @[ifu_bp_ctl.scala 444:87] + node _T_11184 = or(_T_11175, _T_11183) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][0][0] <= _T_11184 @[ifu_bp_ctl.scala 443:27] + node _T_11185 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11186 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11187 = eq(_T_11186, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_11188 = and(_T_11185, _T_11187) @[ifu_bp_ctl.scala 443:45] + node _T_11189 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11190 = eq(_T_11189, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_11191 = or(_T_11190, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11192 = and(_T_11188, _T_11191) @[ifu_bp_ctl.scala 443:110] + node _T_11193 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11194 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11195 = eq(_T_11194, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_11196 = and(_T_11193, _T_11195) @[ifu_bp_ctl.scala 444:22] + node _T_11197 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11198 = eq(_T_11197, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_11199 = or(_T_11198, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11200 = and(_T_11196, _T_11199) @[ifu_bp_ctl.scala 444:87] + node _T_11201 = or(_T_11192, _T_11200) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][0][1] <= _T_11201 @[ifu_bp_ctl.scala 443:27] + node _T_11202 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11203 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11204 = eq(_T_11203, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_11205 = and(_T_11202, _T_11204) @[ifu_bp_ctl.scala 443:45] + node _T_11206 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11207 = eq(_T_11206, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_11208 = or(_T_11207, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11209 = and(_T_11205, _T_11208) @[ifu_bp_ctl.scala 443:110] + node _T_11210 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11211 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11212 = eq(_T_11211, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_11213 = and(_T_11210, _T_11212) @[ifu_bp_ctl.scala 444:22] + node _T_11214 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11215 = eq(_T_11214, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_11216 = or(_T_11215, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11217 = and(_T_11213, _T_11216) @[ifu_bp_ctl.scala 444:87] + node _T_11218 = or(_T_11209, _T_11217) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][0][2] <= _T_11218 @[ifu_bp_ctl.scala 443:27] + node _T_11219 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11220 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11221 = eq(_T_11220, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_11222 = and(_T_11219, _T_11221) @[ifu_bp_ctl.scala 443:45] + node _T_11223 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11224 = eq(_T_11223, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_11225 = or(_T_11224, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11226 = and(_T_11222, _T_11225) @[ifu_bp_ctl.scala 443:110] + node _T_11227 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11228 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11229 = eq(_T_11228, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_11230 = and(_T_11227, _T_11229) @[ifu_bp_ctl.scala 444:22] + node _T_11231 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11232 = eq(_T_11231, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_11233 = or(_T_11232, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11234 = and(_T_11230, _T_11233) @[ifu_bp_ctl.scala 444:87] + node _T_11235 = or(_T_11226, _T_11234) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][0][3] <= _T_11235 @[ifu_bp_ctl.scala 443:27] + node _T_11236 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11237 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11238 = eq(_T_11237, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_11239 = and(_T_11236, _T_11238) @[ifu_bp_ctl.scala 443:45] + node _T_11240 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11241 = eq(_T_11240, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_11242 = or(_T_11241, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11243 = and(_T_11239, _T_11242) @[ifu_bp_ctl.scala 443:110] + node _T_11244 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11245 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11246 = eq(_T_11245, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_11247 = and(_T_11244, _T_11246) @[ifu_bp_ctl.scala 444:22] + node _T_11248 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11249 = eq(_T_11248, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_11250 = or(_T_11249, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11251 = and(_T_11247, _T_11250) @[ifu_bp_ctl.scala 444:87] + node _T_11252 = or(_T_11243, _T_11251) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][0][4] <= _T_11252 @[ifu_bp_ctl.scala 443:27] + node _T_11253 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11254 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11255 = eq(_T_11254, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_11256 = and(_T_11253, _T_11255) @[ifu_bp_ctl.scala 443:45] + node _T_11257 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11258 = eq(_T_11257, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_11259 = or(_T_11258, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11260 = and(_T_11256, _T_11259) @[ifu_bp_ctl.scala 443:110] + node _T_11261 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11262 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11263 = eq(_T_11262, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_11264 = and(_T_11261, _T_11263) @[ifu_bp_ctl.scala 444:22] + node _T_11265 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11266 = eq(_T_11265, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_11267 = or(_T_11266, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11268 = and(_T_11264, _T_11267) @[ifu_bp_ctl.scala 444:87] + node _T_11269 = or(_T_11260, _T_11268) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][0][5] <= _T_11269 @[ifu_bp_ctl.scala 443:27] + node _T_11270 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11271 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11272 = eq(_T_11271, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_11273 = and(_T_11270, _T_11272) @[ifu_bp_ctl.scala 443:45] + node _T_11274 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11275 = eq(_T_11274, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_11276 = or(_T_11275, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11277 = and(_T_11273, _T_11276) @[ifu_bp_ctl.scala 443:110] + node _T_11278 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11279 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11280 = eq(_T_11279, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_11281 = and(_T_11278, _T_11280) @[ifu_bp_ctl.scala 444:22] + node _T_11282 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11283 = eq(_T_11282, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_11284 = or(_T_11283, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11285 = and(_T_11281, _T_11284) @[ifu_bp_ctl.scala 444:87] + node _T_11286 = or(_T_11277, _T_11285) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][0][6] <= _T_11286 @[ifu_bp_ctl.scala 443:27] + node _T_11287 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11288 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11289 = eq(_T_11288, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_11290 = and(_T_11287, _T_11289) @[ifu_bp_ctl.scala 443:45] + node _T_11291 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11292 = eq(_T_11291, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_11293 = or(_T_11292, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11294 = and(_T_11290, _T_11293) @[ifu_bp_ctl.scala 443:110] + node _T_11295 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11296 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11297 = eq(_T_11296, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_11298 = and(_T_11295, _T_11297) @[ifu_bp_ctl.scala 444:22] + node _T_11299 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11300 = eq(_T_11299, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_11301 = or(_T_11300, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11302 = and(_T_11298, _T_11301) @[ifu_bp_ctl.scala 444:87] + node _T_11303 = or(_T_11294, _T_11302) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][0][7] <= _T_11303 @[ifu_bp_ctl.scala 443:27] + node _T_11304 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11305 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11306 = eq(_T_11305, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_11307 = and(_T_11304, _T_11306) @[ifu_bp_ctl.scala 443:45] + node _T_11308 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11309 = eq(_T_11308, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_11310 = or(_T_11309, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11311 = and(_T_11307, _T_11310) @[ifu_bp_ctl.scala 443:110] + node _T_11312 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11313 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11314 = eq(_T_11313, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_11315 = and(_T_11312, _T_11314) @[ifu_bp_ctl.scala 444:22] + node _T_11316 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11317 = eq(_T_11316, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_11318 = or(_T_11317, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11319 = and(_T_11315, _T_11318) @[ifu_bp_ctl.scala 444:87] + node _T_11320 = or(_T_11311, _T_11319) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][0][8] <= _T_11320 @[ifu_bp_ctl.scala 443:27] + node _T_11321 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11322 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11323 = eq(_T_11322, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_11324 = and(_T_11321, _T_11323) @[ifu_bp_ctl.scala 443:45] + node _T_11325 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11326 = eq(_T_11325, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_11327 = or(_T_11326, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11328 = and(_T_11324, _T_11327) @[ifu_bp_ctl.scala 443:110] + node _T_11329 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11330 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11331 = eq(_T_11330, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_11332 = and(_T_11329, _T_11331) @[ifu_bp_ctl.scala 444:22] + node _T_11333 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11334 = eq(_T_11333, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_11335 = or(_T_11334, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11336 = and(_T_11332, _T_11335) @[ifu_bp_ctl.scala 444:87] + node _T_11337 = or(_T_11328, _T_11336) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][0][9] <= _T_11337 @[ifu_bp_ctl.scala 443:27] + node _T_11338 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11339 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11340 = eq(_T_11339, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_11341 = and(_T_11338, _T_11340) @[ifu_bp_ctl.scala 443:45] + node _T_11342 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11343 = eq(_T_11342, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_11344 = or(_T_11343, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11345 = and(_T_11341, _T_11344) @[ifu_bp_ctl.scala 443:110] + node _T_11346 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11347 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11348 = eq(_T_11347, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_11349 = and(_T_11346, _T_11348) @[ifu_bp_ctl.scala 444:22] + node _T_11350 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11351 = eq(_T_11350, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_11352 = or(_T_11351, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11353 = and(_T_11349, _T_11352) @[ifu_bp_ctl.scala 444:87] + node _T_11354 = or(_T_11345, _T_11353) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][0][10] <= _T_11354 @[ifu_bp_ctl.scala 443:27] + node _T_11355 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11356 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11357 = eq(_T_11356, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_11358 = and(_T_11355, _T_11357) @[ifu_bp_ctl.scala 443:45] + node _T_11359 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11360 = eq(_T_11359, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_11361 = or(_T_11360, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11362 = and(_T_11358, _T_11361) @[ifu_bp_ctl.scala 443:110] + node _T_11363 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11364 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11365 = eq(_T_11364, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_11366 = and(_T_11363, _T_11365) @[ifu_bp_ctl.scala 444:22] + node _T_11367 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11368 = eq(_T_11367, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_11369 = or(_T_11368, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11370 = and(_T_11366, _T_11369) @[ifu_bp_ctl.scala 444:87] + node _T_11371 = or(_T_11362, _T_11370) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][0][11] <= _T_11371 @[ifu_bp_ctl.scala 443:27] + node _T_11372 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11373 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11374 = eq(_T_11373, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_11375 = and(_T_11372, _T_11374) @[ifu_bp_ctl.scala 443:45] + node _T_11376 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11377 = eq(_T_11376, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_11378 = or(_T_11377, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11379 = and(_T_11375, _T_11378) @[ifu_bp_ctl.scala 443:110] + node _T_11380 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11381 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11382 = eq(_T_11381, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_11383 = and(_T_11380, _T_11382) @[ifu_bp_ctl.scala 444:22] + node _T_11384 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11385 = eq(_T_11384, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_11386 = or(_T_11385, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11387 = and(_T_11383, _T_11386) @[ifu_bp_ctl.scala 444:87] + node _T_11388 = or(_T_11379, _T_11387) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][0][12] <= _T_11388 @[ifu_bp_ctl.scala 443:27] + node _T_11389 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11390 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11391 = eq(_T_11390, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_11392 = and(_T_11389, _T_11391) @[ifu_bp_ctl.scala 443:45] + node _T_11393 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11394 = eq(_T_11393, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_11395 = or(_T_11394, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11396 = and(_T_11392, _T_11395) @[ifu_bp_ctl.scala 443:110] + node _T_11397 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11398 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11399 = eq(_T_11398, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_11400 = and(_T_11397, _T_11399) @[ifu_bp_ctl.scala 444:22] + node _T_11401 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11402 = eq(_T_11401, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_11403 = or(_T_11402, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11404 = and(_T_11400, _T_11403) @[ifu_bp_ctl.scala 444:87] + node _T_11405 = or(_T_11396, _T_11404) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][0][13] <= _T_11405 @[ifu_bp_ctl.scala 443:27] + node _T_11406 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11407 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11408 = eq(_T_11407, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_11409 = and(_T_11406, _T_11408) @[ifu_bp_ctl.scala 443:45] + node _T_11410 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11411 = eq(_T_11410, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_11412 = or(_T_11411, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11413 = and(_T_11409, _T_11412) @[ifu_bp_ctl.scala 443:110] + node _T_11414 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11415 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11416 = eq(_T_11415, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_11417 = and(_T_11414, _T_11416) @[ifu_bp_ctl.scala 444:22] + node _T_11418 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11419 = eq(_T_11418, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_11420 = or(_T_11419, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11421 = and(_T_11417, _T_11420) @[ifu_bp_ctl.scala 444:87] + node _T_11422 = or(_T_11413, _T_11421) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][0][14] <= _T_11422 @[ifu_bp_ctl.scala 443:27] + node _T_11423 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11424 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11425 = eq(_T_11424, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_11426 = and(_T_11423, _T_11425) @[ifu_bp_ctl.scala 443:45] + node _T_11427 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11428 = eq(_T_11427, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_11429 = or(_T_11428, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11430 = and(_T_11426, _T_11429) @[ifu_bp_ctl.scala 443:110] + node _T_11431 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11432 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11433 = eq(_T_11432, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_11434 = and(_T_11431, _T_11433) @[ifu_bp_ctl.scala 444:22] + node _T_11435 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11436 = eq(_T_11435, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_11437 = or(_T_11436, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11438 = and(_T_11434, _T_11437) @[ifu_bp_ctl.scala 444:87] + node _T_11439 = or(_T_11430, _T_11438) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][0][15] <= _T_11439 @[ifu_bp_ctl.scala 443:27] + node _T_11440 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11441 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11442 = eq(_T_11441, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_11443 = and(_T_11440, _T_11442) @[ifu_bp_ctl.scala 443:45] + node _T_11444 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11445 = eq(_T_11444, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_11446 = or(_T_11445, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11447 = and(_T_11443, _T_11446) @[ifu_bp_ctl.scala 443:110] + node _T_11448 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11449 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11450 = eq(_T_11449, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_11451 = and(_T_11448, _T_11450) @[ifu_bp_ctl.scala 444:22] + node _T_11452 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11453 = eq(_T_11452, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_11454 = or(_T_11453, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11455 = and(_T_11451, _T_11454) @[ifu_bp_ctl.scala 444:87] + node _T_11456 = or(_T_11447, _T_11455) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][1][0] <= _T_11456 @[ifu_bp_ctl.scala 443:27] + node _T_11457 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11458 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11459 = eq(_T_11458, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_11460 = and(_T_11457, _T_11459) @[ifu_bp_ctl.scala 443:45] + node _T_11461 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11462 = eq(_T_11461, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_11463 = or(_T_11462, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11464 = and(_T_11460, _T_11463) @[ifu_bp_ctl.scala 443:110] + node _T_11465 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11466 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11467 = eq(_T_11466, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_11468 = and(_T_11465, _T_11467) @[ifu_bp_ctl.scala 444:22] + node _T_11469 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11470 = eq(_T_11469, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_11471 = or(_T_11470, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11472 = and(_T_11468, _T_11471) @[ifu_bp_ctl.scala 444:87] + node _T_11473 = or(_T_11464, _T_11472) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][1][1] <= _T_11473 @[ifu_bp_ctl.scala 443:27] + node _T_11474 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11475 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11476 = eq(_T_11475, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_11477 = and(_T_11474, _T_11476) @[ifu_bp_ctl.scala 443:45] + node _T_11478 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11479 = eq(_T_11478, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_11480 = or(_T_11479, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11481 = and(_T_11477, _T_11480) @[ifu_bp_ctl.scala 443:110] + node _T_11482 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11483 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11484 = eq(_T_11483, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_11485 = and(_T_11482, _T_11484) @[ifu_bp_ctl.scala 444:22] + node _T_11486 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11487 = eq(_T_11486, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_11488 = or(_T_11487, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11489 = and(_T_11485, _T_11488) @[ifu_bp_ctl.scala 444:87] + node _T_11490 = or(_T_11481, _T_11489) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][1][2] <= _T_11490 @[ifu_bp_ctl.scala 443:27] + node _T_11491 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11492 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11493 = eq(_T_11492, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_11494 = and(_T_11491, _T_11493) @[ifu_bp_ctl.scala 443:45] + node _T_11495 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11496 = eq(_T_11495, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_11497 = or(_T_11496, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11498 = and(_T_11494, _T_11497) @[ifu_bp_ctl.scala 443:110] + node _T_11499 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11500 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11501 = eq(_T_11500, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_11502 = and(_T_11499, _T_11501) @[ifu_bp_ctl.scala 444:22] + node _T_11503 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11504 = eq(_T_11503, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_11505 = or(_T_11504, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11506 = and(_T_11502, _T_11505) @[ifu_bp_ctl.scala 444:87] + node _T_11507 = or(_T_11498, _T_11506) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][1][3] <= _T_11507 @[ifu_bp_ctl.scala 443:27] + node _T_11508 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11509 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11510 = eq(_T_11509, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_11511 = and(_T_11508, _T_11510) @[ifu_bp_ctl.scala 443:45] + node _T_11512 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11513 = eq(_T_11512, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_11514 = or(_T_11513, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11515 = and(_T_11511, _T_11514) @[ifu_bp_ctl.scala 443:110] + node _T_11516 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11517 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11518 = eq(_T_11517, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_11519 = and(_T_11516, _T_11518) @[ifu_bp_ctl.scala 444:22] + node _T_11520 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11521 = eq(_T_11520, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_11522 = or(_T_11521, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11523 = and(_T_11519, _T_11522) @[ifu_bp_ctl.scala 444:87] + node _T_11524 = or(_T_11515, _T_11523) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][1][4] <= _T_11524 @[ifu_bp_ctl.scala 443:27] + node _T_11525 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11526 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11527 = eq(_T_11526, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_11528 = and(_T_11525, _T_11527) @[ifu_bp_ctl.scala 443:45] + node _T_11529 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11530 = eq(_T_11529, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_11531 = or(_T_11530, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11532 = and(_T_11528, _T_11531) @[ifu_bp_ctl.scala 443:110] + node _T_11533 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11534 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11535 = eq(_T_11534, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_11536 = and(_T_11533, _T_11535) @[ifu_bp_ctl.scala 444:22] + node _T_11537 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11538 = eq(_T_11537, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_11539 = or(_T_11538, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11540 = and(_T_11536, _T_11539) @[ifu_bp_ctl.scala 444:87] + node _T_11541 = or(_T_11532, _T_11540) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][1][5] <= _T_11541 @[ifu_bp_ctl.scala 443:27] + node _T_11542 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11543 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11544 = eq(_T_11543, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_11545 = and(_T_11542, _T_11544) @[ifu_bp_ctl.scala 443:45] + node _T_11546 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11547 = eq(_T_11546, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_11548 = or(_T_11547, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11549 = and(_T_11545, _T_11548) @[ifu_bp_ctl.scala 443:110] + node _T_11550 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11551 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11552 = eq(_T_11551, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_11553 = and(_T_11550, _T_11552) @[ifu_bp_ctl.scala 444:22] + node _T_11554 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11555 = eq(_T_11554, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_11556 = or(_T_11555, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11557 = and(_T_11553, _T_11556) @[ifu_bp_ctl.scala 444:87] + node _T_11558 = or(_T_11549, _T_11557) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][1][6] <= _T_11558 @[ifu_bp_ctl.scala 443:27] + node _T_11559 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11560 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11561 = eq(_T_11560, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_11562 = and(_T_11559, _T_11561) @[ifu_bp_ctl.scala 443:45] + node _T_11563 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11564 = eq(_T_11563, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_11565 = or(_T_11564, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11566 = and(_T_11562, _T_11565) @[ifu_bp_ctl.scala 443:110] + node _T_11567 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11568 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11569 = eq(_T_11568, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_11570 = and(_T_11567, _T_11569) @[ifu_bp_ctl.scala 444:22] + node _T_11571 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11572 = eq(_T_11571, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_11573 = or(_T_11572, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11574 = and(_T_11570, _T_11573) @[ifu_bp_ctl.scala 444:87] + node _T_11575 = or(_T_11566, _T_11574) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][1][7] <= _T_11575 @[ifu_bp_ctl.scala 443:27] + node _T_11576 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11577 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11578 = eq(_T_11577, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_11579 = and(_T_11576, _T_11578) @[ifu_bp_ctl.scala 443:45] + node _T_11580 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11581 = eq(_T_11580, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_11582 = or(_T_11581, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11583 = and(_T_11579, _T_11582) @[ifu_bp_ctl.scala 443:110] + node _T_11584 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11585 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11586 = eq(_T_11585, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_11587 = and(_T_11584, _T_11586) @[ifu_bp_ctl.scala 444:22] + node _T_11588 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11589 = eq(_T_11588, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_11590 = or(_T_11589, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11591 = and(_T_11587, _T_11590) @[ifu_bp_ctl.scala 444:87] + node _T_11592 = or(_T_11583, _T_11591) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][1][8] <= _T_11592 @[ifu_bp_ctl.scala 443:27] + node _T_11593 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11594 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11595 = eq(_T_11594, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_11596 = and(_T_11593, _T_11595) @[ifu_bp_ctl.scala 443:45] + node _T_11597 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11598 = eq(_T_11597, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_11599 = or(_T_11598, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11600 = and(_T_11596, _T_11599) @[ifu_bp_ctl.scala 443:110] + node _T_11601 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11602 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11603 = eq(_T_11602, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_11604 = and(_T_11601, _T_11603) @[ifu_bp_ctl.scala 444:22] + node _T_11605 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11606 = eq(_T_11605, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_11607 = or(_T_11606, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11608 = and(_T_11604, _T_11607) @[ifu_bp_ctl.scala 444:87] + node _T_11609 = or(_T_11600, _T_11608) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][1][9] <= _T_11609 @[ifu_bp_ctl.scala 443:27] + node _T_11610 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11611 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11612 = eq(_T_11611, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_11613 = and(_T_11610, _T_11612) @[ifu_bp_ctl.scala 443:45] + node _T_11614 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11615 = eq(_T_11614, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_11616 = or(_T_11615, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11617 = and(_T_11613, _T_11616) @[ifu_bp_ctl.scala 443:110] + node _T_11618 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11619 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11620 = eq(_T_11619, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_11621 = and(_T_11618, _T_11620) @[ifu_bp_ctl.scala 444:22] + node _T_11622 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11623 = eq(_T_11622, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_11624 = or(_T_11623, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11625 = and(_T_11621, _T_11624) @[ifu_bp_ctl.scala 444:87] + node _T_11626 = or(_T_11617, _T_11625) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][1][10] <= _T_11626 @[ifu_bp_ctl.scala 443:27] + node _T_11627 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11628 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11629 = eq(_T_11628, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_11630 = and(_T_11627, _T_11629) @[ifu_bp_ctl.scala 443:45] + node _T_11631 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11632 = eq(_T_11631, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_11633 = or(_T_11632, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11634 = and(_T_11630, _T_11633) @[ifu_bp_ctl.scala 443:110] + node _T_11635 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11636 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11637 = eq(_T_11636, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_11638 = and(_T_11635, _T_11637) @[ifu_bp_ctl.scala 444:22] + node _T_11639 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11640 = eq(_T_11639, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_11641 = or(_T_11640, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11642 = and(_T_11638, _T_11641) @[ifu_bp_ctl.scala 444:87] + node _T_11643 = or(_T_11634, _T_11642) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][1][11] <= _T_11643 @[ifu_bp_ctl.scala 443:27] + node _T_11644 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11645 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11646 = eq(_T_11645, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_11647 = and(_T_11644, _T_11646) @[ifu_bp_ctl.scala 443:45] + node _T_11648 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11649 = eq(_T_11648, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_11650 = or(_T_11649, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11651 = and(_T_11647, _T_11650) @[ifu_bp_ctl.scala 443:110] + node _T_11652 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11653 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11654 = eq(_T_11653, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_11655 = and(_T_11652, _T_11654) @[ifu_bp_ctl.scala 444:22] + node _T_11656 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11657 = eq(_T_11656, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_11658 = or(_T_11657, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11659 = and(_T_11655, _T_11658) @[ifu_bp_ctl.scala 444:87] + node _T_11660 = or(_T_11651, _T_11659) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][1][12] <= _T_11660 @[ifu_bp_ctl.scala 443:27] + node _T_11661 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11662 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11663 = eq(_T_11662, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_11664 = and(_T_11661, _T_11663) @[ifu_bp_ctl.scala 443:45] + node _T_11665 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11666 = eq(_T_11665, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_11667 = or(_T_11666, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11668 = and(_T_11664, _T_11667) @[ifu_bp_ctl.scala 443:110] + node _T_11669 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11670 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11671 = eq(_T_11670, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_11672 = and(_T_11669, _T_11671) @[ifu_bp_ctl.scala 444:22] + node _T_11673 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11674 = eq(_T_11673, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_11675 = or(_T_11674, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11676 = and(_T_11672, _T_11675) @[ifu_bp_ctl.scala 444:87] + node _T_11677 = or(_T_11668, _T_11676) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][1][13] <= _T_11677 @[ifu_bp_ctl.scala 443:27] + node _T_11678 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11679 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11680 = eq(_T_11679, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_11681 = and(_T_11678, _T_11680) @[ifu_bp_ctl.scala 443:45] + node _T_11682 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11683 = eq(_T_11682, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_11684 = or(_T_11683, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11685 = and(_T_11681, _T_11684) @[ifu_bp_ctl.scala 443:110] + node _T_11686 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11687 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11688 = eq(_T_11687, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_11689 = and(_T_11686, _T_11688) @[ifu_bp_ctl.scala 444:22] + node _T_11690 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11691 = eq(_T_11690, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_11692 = or(_T_11691, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11693 = and(_T_11689, _T_11692) @[ifu_bp_ctl.scala 444:87] + node _T_11694 = or(_T_11685, _T_11693) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][1][14] <= _T_11694 @[ifu_bp_ctl.scala 443:27] + node _T_11695 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11696 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11697 = eq(_T_11696, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_11698 = and(_T_11695, _T_11697) @[ifu_bp_ctl.scala 443:45] + node _T_11699 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11700 = eq(_T_11699, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_11701 = or(_T_11700, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11702 = and(_T_11698, _T_11701) @[ifu_bp_ctl.scala 443:110] + node _T_11703 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11704 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11705 = eq(_T_11704, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_11706 = and(_T_11703, _T_11705) @[ifu_bp_ctl.scala 444:22] + node _T_11707 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11708 = eq(_T_11707, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_11709 = or(_T_11708, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11710 = and(_T_11706, _T_11709) @[ifu_bp_ctl.scala 444:87] + node _T_11711 = or(_T_11702, _T_11710) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][1][15] <= _T_11711 @[ifu_bp_ctl.scala 443:27] + node _T_11712 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11713 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11714 = eq(_T_11713, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_11715 = and(_T_11712, _T_11714) @[ifu_bp_ctl.scala 443:45] + node _T_11716 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11717 = eq(_T_11716, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_11718 = or(_T_11717, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11719 = and(_T_11715, _T_11718) @[ifu_bp_ctl.scala 443:110] + node _T_11720 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11721 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11722 = eq(_T_11721, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_11723 = and(_T_11720, _T_11722) @[ifu_bp_ctl.scala 444:22] + node _T_11724 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11725 = eq(_T_11724, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_11726 = or(_T_11725, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11727 = and(_T_11723, _T_11726) @[ifu_bp_ctl.scala 444:87] + node _T_11728 = or(_T_11719, _T_11727) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][2][0] <= _T_11728 @[ifu_bp_ctl.scala 443:27] + node _T_11729 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11730 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11731 = eq(_T_11730, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_11732 = and(_T_11729, _T_11731) @[ifu_bp_ctl.scala 443:45] + node _T_11733 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11734 = eq(_T_11733, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_11735 = or(_T_11734, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11736 = and(_T_11732, _T_11735) @[ifu_bp_ctl.scala 443:110] + node _T_11737 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11738 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11739 = eq(_T_11738, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_11740 = and(_T_11737, _T_11739) @[ifu_bp_ctl.scala 444:22] + node _T_11741 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11742 = eq(_T_11741, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_11743 = or(_T_11742, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11744 = and(_T_11740, _T_11743) @[ifu_bp_ctl.scala 444:87] + node _T_11745 = or(_T_11736, _T_11744) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][2][1] <= _T_11745 @[ifu_bp_ctl.scala 443:27] + node _T_11746 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11747 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11748 = eq(_T_11747, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_11749 = and(_T_11746, _T_11748) @[ifu_bp_ctl.scala 443:45] + node _T_11750 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11751 = eq(_T_11750, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_11752 = or(_T_11751, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11753 = and(_T_11749, _T_11752) @[ifu_bp_ctl.scala 443:110] + node _T_11754 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11755 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11756 = eq(_T_11755, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_11757 = and(_T_11754, _T_11756) @[ifu_bp_ctl.scala 444:22] + node _T_11758 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11759 = eq(_T_11758, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_11760 = or(_T_11759, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11761 = and(_T_11757, _T_11760) @[ifu_bp_ctl.scala 444:87] + node _T_11762 = or(_T_11753, _T_11761) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][2][2] <= _T_11762 @[ifu_bp_ctl.scala 443:27] + node _T_11763 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11764 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11765 = eq(_T_11764, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_11766 = and(_T_11763, _T_11765) @[ifu_bp_ctl.scala 443:45] + node _T_11767 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11768 = eq(_T_11767, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_11769 = or(_T_11768, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11770 = and(_T_11766, _T_11769) @[ifu_bp_ctl.scala 443:110] + node _T_11771 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11772 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11773 = eq(_T_11772, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_11774 = and(_T_11771, _T_11773) @[ifu_bp_ctl.scala 444:22] + node _T_11775 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11776 = eq(_T_11775, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_11777 = or(_T_11776, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11778 = and(_T_11774, _T_11777) @[ifu_bp_ctl.scala 444:87] + node _T_11779 = or(_T_11770, _T_11778) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][2][3] <= _T_11779 @[ifu_bp_ctl.scala 443:27] + node _T_11780 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11781 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11782 = eq(_T_11781, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_11783 = and(_T_11780, _T_11782) @[ifu_bp_ctl.scala 443:45] + node _T_11784 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11785 = eq(_T_11784, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_11786 = or(_T_11785, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11787 = and(_T_11783, _T_11786) @[ifu_bp_ctl.scala 443:110] + node _T_11788 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11789 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11790 = eq(_T_11789, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_11791 = and(_T_11788, _T_11790) @[ifu_bp_ctl.scala 444:22] + node _T_11792 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11793 = eq(_T_11792, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_11794 = or(_T_11793, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11795 = and(_T_11791, _T_11794) @[ifu_bp_ctl.scala 444:87] + node _T_11796 = or(_T_11787, _T_11795) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][2][4] <= _T_11796 @[ifu_bp_ctl.scala 443:27] + node _T_11797 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11798 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11799 = eq(_T_11798, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_11800 = and(_T_11797, _T_11799) @[ifu_bp_ctl.scala 443:45] + node _T_11801 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11802 = eq(_T_11801, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_11803 = or(_T_11802, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11804 = and(_T_11800, _T_11803) @[ifu_bp_ctl.scala 443:110] + node _T_11805 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11806 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11807 = eq(_T_11806, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_11808 = and(_T_11805, _T_11807) @[ifu_bp_ctl.scala 444:22] + node _T_11809 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11810 = eq(_T_11809, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_11811 = or(_T_11810, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11812 = and(_T_11808, _T_11811) @[ifu_bp_ctl.scala 444:87] + node _T_11813 = or(_T_11804, _T_11812) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][2][5] <= _T_11813 @[ifu_bp_ctl.scala 443:27] + node _T_11814 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11815 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11816 = eq(_T_11815, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_11817 = and(_T_11814, _T_11816) @[ifu_bp_ctl.scala 443:45] + node _T_11818 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11819 = eq(_T_11818, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_11820 = or(_T_11819, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11821 = and(_T_11817, _T_11820) @[ifu_bp_ctl.scala 443:110] + node _T_11822 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11823 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11824 = eq(_T_11823, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_11825 = and(_T_11822, _T_11824) @[ifu_bp_ctl.scala 444:22] + node _T_11826 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11827 = eq(_T_11826, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_11828 = or(_T_11827, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11829 = and(_T_11825, _T_11828) @[ifu_bp_ctl.scala 444:87] + node _T_11830 = or(_T_11821, _T_11829) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][2][6] <= _T_11830 @[ifu_bp_ctl.scala 443:27] + node _T_11831 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11832 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11833 = eq(_T_11832, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_11834 = and(_T_11831, _T_11833) @[ifu_bp_ctl.scala 443:45] + node _T_11835 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11836 = eq(_T_11835, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_11837 = or(_T_11836, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11838 = and(_T_11834, _T_11837) @[ifu_bp_ctl.scala 443:110] + node _T_11839 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11840 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11841 = eq(_T_11840, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_11842 = and(_T_11839, _T_11841) @[ifu_bp_ctl.scala 444:22] + node _T_11843 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11844 = eq(_T_11843, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_11845 = or(_T_11844, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11846 = and(_T_11842, _T_11845) @[ifu_bp_ctl.scala 444:87] + node _T_11847 = or(_T_11838, _T_11846) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][2][7] <= _T_11847 @[ifu_bp_ctl.scala 443:27] + node _T_11848 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11849 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11850 = eq(_T_11849, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_11851 = and(_T_11848, _T_11850) @[ifu_bp_ctl.scala 443:45] + node _T_11852 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11853 = eq(_T_11852, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_11854 = or(_T_11853, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11855 = and(_T_11851, _T_11854) @[ifu_bp_ctl.scala 443:110] + node _T_11856 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11857 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11858 = eq(_T_11857, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_11859 = and(_T_11856, _T_11858) @[ifu_bp_ctl.scala 444:22] + node _T_11860 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11861 = eq(_T_11860, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_11862 = or(_T_11861, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11863 = and(_T_11859, _T_11862) @[ifu_bp_ctl.scala 444:87] + node _T_11864 = or(_T_11855, _T_11863) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][2][8] <= _T_11864 @[ifu_bp_ctl.scala 443:27] + node _T_11865 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11866 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11867 = eq(_T_11866, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_11868 = and(_T_11865, _T_11867) @[ifu_bp_ctl.scala 443:45] + node _T_11869 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11870 = eq(_T_11869, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_11871 = or(_T_11870, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11872 = and(_T_11868, _T_11871) @[ifu_bp_ctl.scala 443:110] + node _T_11873 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11874 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11875 = eq(_T_11874, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_11876 = and(_T_11873, _T_11875) @[ifu_bp_ctl.scala 444:22] + node _T_11877 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11878 = eq(_T_11877, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_11879 = or(_T_11878, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11880 = and(_T_11876, _T_11879) @[ifu_bp_ctl.scala 444:87] + node _T_11881 = or(_T_11872, _T_11880) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][2][9] <= _T_11881 @[ifu_bp_ctl.scala 443:27] + node _T_11882 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11883 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11884 = eq(_T_11883, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_11885 = and(_T_11882, _T_11884) @[ifu_bp_ctl.scala 443:45] + node _T_11886 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11887 = eq(_T_11886, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_11888 = or(_T_11887, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11889 = and(_T_11885, _T_11888) @[ifu_bp_ctl.scala 443:110] + node _T_11890 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11891 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11892 = eq(_T_11891, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_11893 = and(_T_11890, _T_11892) @[ifu_bp_ctl.scala 444:22] + node _T_11894 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11895 = eq(_T_11894, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_11896 = or(_T_11895, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11897 = and(_T_11893, _T_11896) @[ifu_bp_ctl.scala 444:87] + node _T_11898 = or(_T_11889, _T_11897) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][2][10] <= _T_11898 @[ifu_bp_ctl.scala 443:27] + node _T_11899 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11900 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11901 = eq(_T_11900, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_11902 = and(_T_11899, _T_11901) @[ifu_bp_ctl.scala 443:45] + node _T_11903 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11904 = eq(_T_11903, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_11905 = or(_T_11904, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11906 = and(_T_11902, _T_11905) @[ifu_bp_ctl.scala 443:110] + node _T_11907 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11908 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11909 = eq(_T_11908, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_11910 = and(_T_11907, _T_11909) @[ifu_bp_ctl.scala 444:22] + node _T_11911 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11912 = eq(_T_11911, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_11913 = or(_T_11912, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11914 = and(_T_11910, _T_11913) @[ifu_bp_ctl.scala 444:87] + node _T_11915 = or(_T_11906, _T_11914) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][2][11] <= _T_11915 @[ifu_bp_ctl.scala 443:27] + node _T_11916 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11917 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11918 = eq(_T_11917, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_11919 = and(_T_11916, _T_11918) @[ifu_bp_ctl.scala 443:45] + node _T_11920 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11921 = eq(_T_11920, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_11922 = or(_T_11921, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11923 = and(_T_11919, _T_11922) @[ifu_bp_ctl.scala 443:110] + node _T_11924 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11925 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11926 = eq(_T_11925, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_11927 = and(_T_11924, _T_11926) @[ifu_bp_ctl.scala 444:22] + node _T_11928 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11929 = eq(_T_11928, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_11930 = or(_T_11929, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11931 = and(_T_11927, _T_11930) @[ifu_bp_ctl.scala 444:87] + node _T_11932 = or(_T_11923, _T_11931) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][2][12] <= _T_11932 @[ifu_bp_ctl.scala 443:27] + node _T_11933 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11934 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11935 = eq(_T_11934, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_11936 = and(_T_11933, _T_11935) @[ifu_bp_ctl.scala 443:45] + node _T_11937 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11938 = eq(_T_11937, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_11939 = or(_T_11938, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11940 = and(_T_11936, _T_11939) @[ifu_bp_ctl.scala 443:110] + node _T_11941 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11942 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11943 = eq(_T_11942, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_11944 = and(_T_11941, _T_11943) @[ifu_bp_ctl.scala 444:22] + node _T_11945 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11946 = eq(_T_11945, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_11947 = or(_T_11946, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11948 = and(_T_11944, _T_11947) @[ifu_bp_ctl.scala 444:87] + node _T_11949 = or(_T_11940, _T_11948) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][2][13] <= _T_11949 @[ifu_bp_ctl.scala 443:27] + node _T_11950 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11951 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11952 = eq(_T_11951, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_11953 = and(_T_11950, _T_11952) @[ifu_bp_ctl.scala 443:45] + node _T_11954 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11955 = eq(_T_11954, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_11956 = or(_T_11955, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11957 = and(_T_11953, _T_11956) @[ifu_bp_ctl.scala 443:110] + node _T_11958 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11959 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11960 = eq(_T_11959, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_11961 = and(_T_11958, _T_11960) @[ifu_bp_ctl.scala 444:22] + node _T_11962 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11963 = eq(_T_11962, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_11964 = or(_T_11963, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11965 = and(_T_11961, _T_11964) @[ifu_bp_ctl.scala 444:87] + node _T_11966 = or(_T_11957, _T_11965) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][2][14] <= _T_11966 @[ifu_bp_ctl.scala 443:27] + node _T_11967 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11968 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11969 = eq(_T_11968, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_11970 = and(_T_11967, _T_11969) @[ifu_bp_ctl.scala 443:45] + node _T_11971 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11972 = eq(_T_11971, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_11973 = or(_T_11972, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11974 = and(_T_11970, _T_11973) @[ifu_bp_ctl.scala 443:110] + node _T_11975 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11976 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11977 = eq(_T_11976, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_11978 = and(_T_11975, _T_11977) @[ifu_bp_ctl.scala 444:22] + node _T_11979 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11980 = eq(_T_11979, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_11981 = or(_T_11980, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11982 = and(_T_11978, _T_11981) @[ifu_bp_ctl.scala 444:87] + node _T_11983 = or(_T_11974, _T_11982) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][2][15] <= _T_11983 @[ifu_bp_ctl.scala 443:27] + node _T_11984 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_11985 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_11986 = eq(_T_11985, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_11987 = and(_T_11984, _T_11986) @[ifu_bp_ctl.scala 443:45] + node _T_11988 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_11989 = eq(_T_11988, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_11990 = or(_T_11989, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_11991 = and(_T_11987, _T_11990) @[ifu_bp_ctl.scala 443:110] + node _T_11992 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_11993 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_11994 = eq(_T_11993, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_11995 = and(_T_11992, _T_11994) @[ifu_bp_ctl.scala 444:22] + node _T_11996 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_11997 = eq(_T_11996, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_11998 = or(_T_11997, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_11999 = and(_T_11995, _T_11998) @[ifu_bp_ctl.scala 444:87] + node _T_12000 = or(_T_11991, _T_11999) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][3][0] <= _T_12000 @[ifu_bp_ctl.scala 443:27] + node _T_12001 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12002 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12003 = eq(_T_12002, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_12004 = and(_T_12001, _T_12003) @[ifu_bp_ctl.scala 443:45] + node _T_12005 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12006 = eq(_T_12005, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_12007 = or(_T_12006, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12008 = and(_T_12004, _T_12007) @[ifu_bp_ctl.scala 443:110] + node _T_12009 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12010 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12011 = eq(_T_12010, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_12012 = and(_T_12009, _T_12011) @[ifu_bp_ctl.scala 444:22] + node _T_12013 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12014 = eq(_T_12013, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_12015 = or(_T_12014, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12016 = and(_T_12012, _T_12015) @[ifu_bp_ctl.scala 444:87] + node _T_12017 = or(_T_12008, _T_12016) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][3][1] <= _T_12017 @[ifu_bp_ctl.scala 443:27] + node _T_12018 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12019 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12020 = eq(_T_12019, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_12021 = and(_T_12018, _T_12020) @[ifu_bp_ctl.scala 443:45] + node _T_12022 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12023 = eq(_T_12022, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_12024 = or(_T_12023, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12025 = and(_T_12021, _T_12024) @[ifu_bp_ctl.scala 443:110] + node _T_12026 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12027 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12028 = eq(_T_12027, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_12029 = and(_T_12026, _T_12028) @[ifu_bp_ctl.scala 444:22] + node _T_12030 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12031 = eq(_T_12030, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_12032 = or(_T_12031, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12033 = and(_T_12029, _T_12032) @[ifu_bp_ctl.scala 444:87] + node _T_12034 = or(_T_12025, _T_12033) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][3][2] <= _T_12034 @[ifu_bp_ctl.scala 443:27] + node _T_12035 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12036 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12037 = eq(_T_12036, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_12038 = and(_T_12035, _T_12037) @[ifu_bp_ctl.scala 443:45] + node _T_12039 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12040 = eq(_T_12039, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_12041 = or(_T_12040, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12042 = and(_T_12038, _T_12041) @[ifu_bp_ctl.scala 443:110] + node _T_12043 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12044 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12045 = eq(_T_12044, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_12046 = and(_T_12043, _T_12045) @[ifu_bp_ctl.scala 444:22] + node _T_12047 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12048 = eq(_T_12047, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_12049 = or(_T_12048, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12050 = and(_T_12046, _T_12049) @[ifu_bp_ctl.scala 444:87] + node _T_12051 = or(_T_12042, _T_12050) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][3][3] <= _T_12051 @[ifu_bp_ctl.scala 443:27] + node _T_12052 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12053 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12054 = eq(_T_12053, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_12055 = and(_T_12052, _T_12054) @[ifu_bp_ctl.scala 443:45] + node _T_12056 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12057 = eq(_T_12056, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_12058 = or(_T_12057, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12059 = and(_T_12055, _T_12058) @[ifu_bp_ctl.scala 443:110] + node _T_12060 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12061 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12062 = eq(_T_12061, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_12063 = and(_T_12060, _T_12062) @[ifu_bp_ctl.scala 444:22] + node _T_12064 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12065 = eq(_T_12064, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_12066 = or(_T_12065, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12067 = and(_T_12063, _T_12066) @[ifu_bp_ctl.scala 444:87] + node _T_12068 = or(_T_12059, _T_12067) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][3][4] <= _T_12068 @[ifu_bp_ctl.scala 443:27] + node _T_12069 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12070 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12071 = eq(_T_12070, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_12072 = and(_T_12069, _T_12071) @[ifu_bp_ctl.scala 443:45] + node _T_12073 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12074 = eq(_T_12073, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_12075 = or(_T_12074, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12076 = and(_T_12072, _T_12075) @[ifu_bp_ctl.scala 443:110] + node _T_12077 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12078 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12079 = eq(_T_12078, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_12080 = and(_T_12077, _T_12079) @[ifu_bp_ctl.scala 444:22] + node _T_12081 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12082 = eq(_T_12081, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_12083 = or(_T_12082, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12084 = and(_T_12080, _T_12083) @[ifu_bp_ctl.scala 444:87] + node _T_12085 = or(_T_12076, _T_12084) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][3][5] <= _T_12085 @[ifu_bp_ctl.scala 443:27] + node _T_12086 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12087 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12088 = eq(_T_12087, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_12089 = and(_T_12086, _T_12088) @[ifu_bp_ctl.scala 443:45] + node _T_12090 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12091 = eq(_T_12090, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_12092 = or(_T_12091, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12093 = and(_T_12089, _T_12092) @[ifu_bp_ctl.scala 443:110] + node _T_12094 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12095 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12096 = eq(_T_12095, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_12097 = and(_T_12094, _T_12096) @[ifu_bp_ctl.scala 444:22] + node _T_12098 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12099 = eq(_T_12098, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_12100 = or(_T_12099, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12101 = and(_T_12097, _T_12100) @[ifu_bp_ctl.scala 444:87] + node _T_12102 = or(_T_12093, _T_12101) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][3][6] <= _T_12102 @[ifu_bp_ctl.scala 443:27] + node _T_12103 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12104 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12105 = eq(_T_12104, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_12106 = and(_T_12103, _T_12105) @[ifu_bp_ctl.scala 443:45] + node _T_12107 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12108 = eq(_T_12107, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_12109 = or(_T_12108, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12110 = and(_T_12106, _T_12109) @[ifu_bp_ctl.scala 443:110] + node _T_12111 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12112 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12113 = eq(_T_12112, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_12114 = and(_T_12111, _T_12113) @[ifu_bp_ctl.scala 444:22] + node _T_12115 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12116 = eq(_T_12115, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_12117 = or(_T_12116, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12118 = and(_T_12114, _T_12117) @[ifu_bp_ctl.scala 444:87] + node _T_12119 = or(_T_12110, _T_12118) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][3][7] <= _T_12119 @[ifu_bp_ctl.scala 443:27] + node _T_12120 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12121 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12122 = eq(_T_12121, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_12123 = and(_T_12120, _T_12122) @[ifu_bp_ctl.scala 443:45] + node _T_12124 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12125 = eq(_T_12124, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_12126 = or(_T_12125, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12127 = and(_T_12123, _T_12126) @[ifu_bp_ctl.scala 443:110] + node _T_12128 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12129 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12130 = eq(_T_12129, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_12131 = and(_T_12128, _T_12130) @[ifu_bp_ctl.scala 444:22] + node _T_12132 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12133 = eq(_T_12132, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_12134 = or(_T_12133, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12135 = and(_T_12131, _T_12134) @[ifu_bp_ctl.scala 444:87] + node _T_12136 = or(_T_12127, _T_12135) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][3][8] <= _T_12136 @[ifu_bp_ctl.scala 443:27] + node _T_12137 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12138 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12139 = eq(_T_12138, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_12140 = and(_T_12137, _T_12139) @[ifu_bp_ctl.scala 443:45] + node _T_12141 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12142 = eq(_T_12141, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_12143 = or(_T_12142, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12144 = and(_T_12140, _T_12143) @[ifu_bp_ctl.scala 443:110] + node _T_12145 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12146 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12147 = eq(_T_12146, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_12148 = and(_T_12145, _T_12147) @[ifu_bp_ctl.scala 444:22] + node _T_12149 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12150 = eq(_T_12149, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_12151 = or(_T_12150, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12152 = and(_T_12148, _T_12151) @[ifu_bp_ctl.scala 444:87] + node _T_12153 = or(_T_12144, _T_12152) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][3][9] <= _T_12153 @[ifu_bp_ctl.scala 443:27] + node _T_12154 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12155 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12156 = eq(_T_12155, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_12157 = and(_T_12154, _T_12156) @[ifu_bp_ctl.scala 443:45] + node _T_12158 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12159 = eq(_T_12158, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_12160 = or(_T_12159, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12161 = and(_T_12157, _T_12160) @[ifu_bp_ctl.scala 443:110] + node _T_12162 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12163 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12164 = eq(_T_12163, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_12165 = and(_T_12162, _T_12164) @[ifu_bp_ctl.scala 444:22] + node _T_12166 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12167 = eq(_T_12166, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_12168 = or(_T_12167, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12169 = and(_T_12165, _T_12168) @[ifu_bp_ctl.scala 444:87] + node _T_12170 = or(_T_12161, _T_12169) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][3][10] <= _T_12170 @[ifu_bp_ctl.scala 443:27] + node _T_12171 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12172 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12173 = eq(_T_12172, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_12174 = and(_T_12171, _T_12173) @[ifu_bp_ctl.scala 443:45] + node _T_12175 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12176 = eq(_T_12175, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_12177 = or(_T_12176, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12178 = and(_T_12174, _T_12177) @[ifu_bp_ctl.scala 443:110] + node _T_12179 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12180 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12181 = eq(_T_12180, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_12182 = and(_T_12179, _T_12181) @[ifu_bp_ctl.scala 444:22] + node _T_12183 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12184 = eq(_T_12183, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_12185 = or(_T_12184, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12186 = and(_T_12182, _T_12185) @[ifu_bp_ctl.scala 444:87] + node _T_12187 = or(_T_12178, _T_12186) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][3][11] <= _T_12187 @[ifu_bp_ctl.scala 443:27] + node _T_12188 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12189 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12190 = eq(_T_12189, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_12191 = and(_T_12188, _T_12190) @[ifu_bp_ctl.scala 443:45] + node _T_12192 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12193 = eq(_T_12192, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_12194 = or(_T_12193, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12195 = and(_T_12191, _T_12194) @[ifu_bp_ctl.scala 443:110] + node _T_12196 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12197 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12198 = eq(_T_12197, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_12199 = and(_T_12196, _T_12198) @[ifu_bp_ctl.scala 444:22] + node _T_12200 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12201 = eq(_T_12200, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_12202 = or(_T_12201, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12203 = and(_T_12199, _T_12202) @[ifu_bp_ctl.scala 444:87] + node _T_12204 = or(_T_12195, _T_12203) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][3][12] <= _T_12204 @[ifu_bp_ctl.scala 443:27] + node _T_12205 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12206 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12207 = eq(_T_12206, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_12208 = and(_T_12205, _T_12207) @[ifu_bp_ctl.scala 443:45] + node _T_12209 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12210 = eq(_T_12209, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_12211 = or(_T_12210, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12212 = and(_T_12208, _T_12211) @[ifu_bp_ctl.scala 443:110] + node _T_12213 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12214 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12215 = eq(_T_12214, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_12216 = and(_T_12213, _T_12215) @[ifu_bp_ctl.scala 444:22] + node _T_12217 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12218 = eq(_T_12217, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_12219 = or(_T_12218, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12220 = and(_T_12216, _T_12219) @[ifu_bp_ctl.scala 444:87] + node _T_12221 = or(_T_12212, _T_12220) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][3][13] <= _T_12221 @[ifu_bp_ctl.scala 443:27] + node _T_12222 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12223 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12224 = eq(_T_12223, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_12225 = and(_T_12222, _T_12224) @[ifu_bp_ctl.scala 443:45] + node _T_12226 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12227 = eq(_T_12226, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_12228 = or(_T_12227, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12229 = and(_T_12225, _T_12228) @[ifu_bp_ctl.scala 443:110] + node _T_12230 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12231 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12232 = eq(_T_12231, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_12233 = and(_T_12230, _T_12232) @[ifu_bp_ctl.scala 444:22] + node _T_12234 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12235 = eq(_T_12234, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_12236 = or(_T_12235, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12237 = and(_T_12233, _T_12236) @[ifu_bp_ctl.scala 444:87] + node _T_12238 = or(_T_12229, _T_12237) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][3][14] <= _T_12238 @[ifu_bp_ctl.scala 443:27] + node _T_12239 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12240 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12241 = eq(_T_12240, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_12242 = and(_T_12239, _T_12241) @[ifu_bp_ctl.scala 443:45] + node _T_12243 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12244 = eq(_T_12243, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_12245 = or(_T_12244, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12246 = and(_T_12242, _T_12245) @[ifu_bp_ctl.scala 443:110] + node _T_12247 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12248 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12249 = eq(_T_12248, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_12250 = and(_T_12247, _T_12249) @[ifu_bp_ctl.scala 444:22] + node _T_12251 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12252 = eq(_T_12251, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_12253 = or(_T_12252, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12254 = and(_T_12250, _T_12253) @[ifu_bp_ctl.scala 444:87] + node _T_12255 = or(_T_12246, _T_12254) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][3][15] <= _T_12255 @[ifu_bp_ctl.scala 443:27] + node _T_12256 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12257 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12258 = eq(_T_12257, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_12259 = and(_T_12256, _T_12258) @[ifu_bp_ctl.scala 443:45] + node _T_12260 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12261 = eq(_T_12260, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_12262 = or(_T_12261, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12263 = and(_T_12259, _T_12262) @[ifu_bp_ctl.scala 443:110] + node _T_12264 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12265 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12266 = eq(_T_12265, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_12267 = and(_T_12264, _T_12266) @[ifu_bp_ctl.scala 444:22] + node _T_12268 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12269 = eq(_T_12268, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_12270 = or(_T_12269, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12271 = and(_T_12267, _T_12270) @[ifu_bp_ctl.scala 444:87] + node _T_12272 = or(_T_12263, _T_12271) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][4][0] <= _T_12272 @[ifu_bp_ctl.scala 443:27] + node _T_12273 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12274 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12275 = eq(_T_12274, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_12276 = and(_T_12273, _T_12275) @[ifu_bp_ctl.scala 443:45] + node _T_12277 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12278 = eq(_T_12277, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_12279 = or(_T_12278, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12280 = and(_T_12276, _T_12279) @[ifu_bp_ctl.scala 443:110] + node _T_12281 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12282 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12283 = eq(_T_12282, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_12284 = and(_T_12281, _T_12283) @[ifu_bp_ctl.scala 444:22] + node _T_12285 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12286 = eq(_T_12285, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_12287 = or(_T_12286, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12288 = and(_T_12284, _T_12287) @[ifu_bp_ctl.scala 444:87] + node _T_12289 = or(_T_12280, _T_12288) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][4][1] <= _T_12289 @[ifu_bp_ctl.scala 443:27] + node _T_12290 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12291 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12292 = eq(_T_12291, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_12293 = and(_T_12290, _T_12292) @[ifu_bp_ctl.scala 443:45] + node _T_12294 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12295 = eq(_T_12294, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_12296 = or(_T_12295, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12297 = and(_T_12293, _T_12296) @[ifu_bp_ctl.scala 443:110] + node _T_12298 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12299 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12300 = eq(_T_12299, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_12301 = and(_T_12298, _T_12300) @[ifu_bp_ctl.scala 444:22] + node _T_12302 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12303 = eq(_T_12302, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_12304 = or(_T_12303, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12305 = and(_T_12301, _T_12304) @[ifu_bp_ctl.scala 444:87] + node _T_12306 = or(_T_12297, _T_12305) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][4][2] <= _T_12306 @[ifu_bp_ctl.scala 443:27] + node _T_12307 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12308 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12309 = eq(_T_12308, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_12310 = and(_T_12307, _T_12309) @[ifu_bp_ctl.scala 443:45] + node _T_12311 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12312 = eq(_T_12311, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_12313 = or(_T_12312, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12314 = and(_T_12310, _T_12313) @[ifu_bp_ctl.scala 443:110] + node _T_12315 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12316 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12317 = eq(_T_12316, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_12318 = and(_T_12315, _T_12317) @[ifu_bp_ctl.scala 444:22] + node _T_12319 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12320 = eq(_T_12319, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_12321 = or(_T_12320, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12322 = and(_T_12318, _T_12321) @[ifu_bp_ctl.scala 444:87] + node _T_12323 = or(_T_12314, _T_12322) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][4][3] <= _T_12323 @[ifu_bp_ctl.scala 443:27] + node _T_12324 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12325 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12326 = eq(_T_12325, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_12327 = and(_T_12324, _T_12326) @[ifu_bp_ctl.scala 443:45] + node _T_12328 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12329 = eq(_T_12328, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_12330 = or(_T_12329, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12331 = and(_T_12327, _T_12330) @[ifu_bp_ctl.scala 443:110] + node _T_12332 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12333 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12334 = eq(_T_12333, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_12335 = and(_T_12332, _T_12334) @[ifu_bp_ctl.scala 444:22] + node _T_12336 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12337 = eq(_T_12336, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_12338 = or(_T_12337, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12339 = and(_T_12335, _T_12338) @[ifu_bp_ctl.scala 444:87] + node _T_12340 = or(_T_12331, _T_12339) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][4][4] <= _T_12340 @[ifu_bp_ctl.scala 443:27] + node _T_12341 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12342 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12343 = eq(_T_12342, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_12344 = and(_T_12341, _T_12343) @[ifu_bp_ctl.scala 443:45] + node _T_12345 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12346 = eq(_T_12345, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_12347 = or(_T_12346, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12348 = and(_T_12344, _T_12347) @[ifu_bp_ctl.scala 443:110] + node _T_12349 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12350 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12351 = eq(_T_12350, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_12352 = and(_T_12349, _T_12351) @[ifu_bp_ctl.scala 444:22] + node _T_12353 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12354 = eq(_T_12353, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_12355 = or(_T_12354, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12356 = and(_T_12352, _T_12355) @[ifu_bp_ctl.scala 444:87] + node _T_12357 = or(_T_12348, _T_12356) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][4][5] <= _T_12357 @[ifu_bp_ctl.scala 443:27] + node _T_12358 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12359 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12360 = eq(_T_12359, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_12361 = and(_T_12358, _T_12360) @[ifu_bp_ctl.scala 443:45] + node _T_12362 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12363 = eq(_T_12362, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_12364 = or(_T_12363, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12365 = and(_T_12361, _T_12364) @[ifu_bp_ctl.scala 443:110] + node _T_12366 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12367 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12368 = eq(_T_12367, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_12369 = and(_T_12366, _T_12368) @[ifu_bp_ctl.scala 444:22] + node _T_12370 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12371 = eq(_T_12370, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_12372 = or(_T_12371, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12373 = and(_T_12369, _T_12372) @[ifu_bp_ctl.scala 444:87] + node _T_12374 = or(_T_12365, _T_12373) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][4][6] <= _T_12374 @[ifu_bp_ctl.scala 443:27] + node _T_12375 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12376 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12377 = eq(_T_12376, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_12378 = and(_T_12375, _T_12377) @[ifu_bp_ctl.scala 443:45] + node _T_12379 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12380 = eq(_T_12379, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_12381 = or(_T_12380, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12382 = and(_T_12378, _T_12381) @[ifu_bp_ctl.scala 443:110] + node _T_12383 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12384 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12385 = eq(_T_12384, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_12386 = and(_T_12383, _T_12385) @[ifu_bp_ctl.scala 444:22] + node _T_12387 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12388 = eq(_T_12387, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_12389 = or(_T_12388, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12390 = and(_T_12386, _T_12389) @[ifu_bp_ctl.scala 444:87] + node _T_12391 = or(_T_12382, _T_12390) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][4][7] <= _T_12391 @[ifu_bp_ctl.scala 443:27] + node _T_12392 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12393 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12394 = eq(_T_12393, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_12395 = and(_T_12392, _T_12394) @[ifu_bp_ctl.scala 443:45] + node _T_12396 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12397 = eq(_T_12396, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_12398 = or(_T_12397, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12399 = and(_T_12395, _T_12398) @[ifu_bp_ctl.scala 443:110] + node _T_12400 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12401 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12402 = eq(_T_12401, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_12403 = and(_T_12400, _T_12402) @[ifu_bp_ctl.scala 444:22] + node _T_12404 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12405 = eq(_T_12404, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_12406 = or(_T_12405, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12407 = and(_T_12403, _T_12406) @[ifu_bp_ctl.scala 444:87] + node _T_12408 = or(_T_12399, _T_12407) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][4][8] <= _T_12408 @[ifu_bp_ctl.scala 443:27] + node _T_12409 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12410 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12411 = eq(_T_12410, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_12412 = and(_T_12409, _T_12411) @[ifu_bp_ctl.scala 443:45] + node _T_12413 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12414 = eq(_T_12413, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_12415 = or(_T_12414, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12416 = and(_T_12412, _T_12415) @[ifu_bp_ctl.scala 443:110] + node _T_12417 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12418 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12419 = eq(_T_12418, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_12420 = and(_T_12417, _T_12419) @[ifu_bp_ctl.scala 444:22] + node _T_12421 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12422 = eq(_T_12421, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_12423 = or(_T_12422, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12424 = and(_T_12420, _T_12423) @[ifu_bp_ctl.scala 444:87] + node _T_12425 = or(_T_12416, _T_12424) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][4][9] <= _T_12425 @[ifu_bp_ctl.scala 443:27] + node _T_12426 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12427 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12428 = eq(_T_12427, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_12429 = and(_T_12426, _T_12428) @[ifu_bp_ctl.scala 443:45] + node _T_12430 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12431 = eq(_T_12430, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_12432 = or(_T_12431, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12433 = and(_T_12429, _T_12432) @[ifu_bp_ctl.scala 443:110] + node _T_12434 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12435 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12436 = eq(_T_12435, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_12437 = and(_T_12434, _T_12436) @[ifu_bp_ctl.scala 444:22] + node _T_12438 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12439 = eq(_T_12438, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_12440 = or(_T_12439, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12441 = and(_T_12437, _T_12440) @[ifu_bp_ctl.scala 444:87] + node _T_12442 = or(_T_12433, _T_12441) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][4][10] <= _T_12442 @[ifu_bp_ctl.scala 443:27] + node _T_12443 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12444 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12445 = eq(_T_12444, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_12446 = and(_T_12443, _T_12445) @[ifu_bp_ctl.scala 443:45] + node _T_12447 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12448 = eq(_T_12447, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_12449 = or(_T_12448, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12450 = and(_T_12446, _T_12449) @[ifu_bp_ctl.scala 443:110] + node _T_12451 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12452 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12453 = eq(_T_12452, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_12454 = and(_T_12451, _T_12453) @[ifu_bp_ctl.scala 444:22] + node _T_12455 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12456 = eq(_T_12455, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_12457 = or(_T_12456, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12458 = and(_T_12454, _T_12457) @[ifu_bp_ctl.scala 444:87] + node _T_12459 = or(_T_12450, _T_12458) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][4][11] <= _T_12459 @[ifu_bp_ctl.scala 443:27] + node _T_12460 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12461 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12462 = eq(_T_12461, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_12463 = and(_T_12460, _T_12462) @[ifu_bp_ctl.scala 443:45] + node _T_12464 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12465 = eq(_T_12464, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_12466 = or(_T_12465, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12467 = and(_T_12463, _T_12466) @[ifu_bp_ctl.scala 443:110] + node _T_12468 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12469 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12470 = eq(_T_12469, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_12471 = and(_T_12468, _T_12470) @[ifu_bp_ctl.scala 444:22] + node _T_12472 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12473 = eq(_T_12472, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_12474 = or(_T_12473, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12475 = and(_T_12471, _T_12474) @[ifu_bp_ctl.scala 444:87] + node _T_12476 = or(_T_12467, _T_12475) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][4][12] <= _T_12476 @[ifu_bp_ctl.scala 443:27] + node _T_12477 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12478 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12479 = eq(_T_12478, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_12480 = and(_T_12477, _T_12479) @[ifu_bp_ctl.scala 443:45] + node _T_12481 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12482 = eq(_T_12481, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_12483 = or(_T_12482, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12484 = and(_T_12480, _T_12483) @[ifu_bp_ctl.scala 443:110] + node _T_12485 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12486 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12487 = eq(_T_12486, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_12488 = and(_T_12485, _T_12487) @[ifu_bp_ctl.scala 444:22] + node _T_12489 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12490 = eq(_T_12489, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_12491 = or(_T_12490, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12492 = and(_T_12488, _T_12491) @[ifu_bp_ctl.scala 444:87] + node _T_12493 = or(_T_12484, _T_12492) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][4][13] <= _T_12493 @[ifu_bp_ctl.scala 443:27] + node _T_12494 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12495 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12496 = eq(_T_12495, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_12497 = and(_T_12494, _T_12496) @[ifu_bp_ctl.scala 443:45] + node _T_12498 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12499 = eq(_T_12498, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_12500 = or(_T_12499, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12501 = and(_T_12497, _T_12500) @[ifu_bp_ctl.scala 443:110] + node _T_12502 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12503 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12504 = eq(_T_12503, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_12505 = and(_T_12502, _T_12504) @[ifu_bp_ctl.scala 444:22] + node _T_12506 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12507 = eq(_T_12506, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_12508 = or(_T_12507, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12509 = and(_T_12505, _T_12508) @[ifu_bp_ctl.scala 444:87] + node _T_12510 = or(_T_12501, _T_12509) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][4][14] <= _T_12510 @[ifu_bp_ctl.scala 443:27] + node _T_12511 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12512 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12513 = eq(_T_12512, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_12514 = and(_T_12511, _T_12513) @[ifu_bp_ctl.scala 443:45] + node _T_12515 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12516 = eq(_T_12515, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_12517 = or(_T_12516, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12518 = and(_T_12514, _T_12517) @[ifu_bp_ctl.scala 443:110] + node _T_12519 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12520 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12521 = eq(_T_12520, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_12522 = and(_T_12519, _T_12521) @[ifu_bp_ctl.scala 444:22] + node _T_12523 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12524 = eq(_T_12523, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_12525 = or(_T_12524, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12526 = and(_T_12522, _T_12525) @[ifu_bp_ctl.scala 444:87] + node _T_12527 = or(_T_12518, _T_12526) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][4][15] <= _T_12527 @[ifu_bp_ctl.scala 443:27] + node _T_12528 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12529 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12530 = eq(_T_12529, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_12531 = and(_T_12528, _T_12530) @[ifu_bp_ctl.scala 443:45] + node _T_12532 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12533 = eq(_T_12532, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_12534 = or(_T_12533, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12535 = and(_T_12531, _T_12534) @[ifu_bp_ctl.scala 443:110] + node _T_12536 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12537 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12538 = eq(_T_12537, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_12539 = and(_T_12536, _T_12538) @[ifu_bp_ctl.scala 444:22] + node _T_12540 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12541 = eq(_T_12540, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_12542 = or(_T_12541, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12543 = and(_T_12539, _T_12542) @[ifu_bp_ctl.scala 444:87] + node _T_12544 = or(_T_12535, _T_12543) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][5][0] <= _T_12544 @[ifu_bp_ctl.scala 443:27] + node _T_12545 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12546 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12547 = eq(_T_12546, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_12548 = and(_T_12545, _T_12547) @[ifu_bp_ctl.scala 443:45] + node _T_12549 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12550 = eq(_T_12549, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_12551 = or(_T_12550, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12552 = and(_T_12548, _T_12551) @[ifu_bp_ctl.scala 443:110] + node _T_12553 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12554 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12555 = eq(_T_12554, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_12556 = and(_T_12553, _T_12555) @[ifu_bp_ctl.scala 444:22] + node _T_12557 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12558 = eq(_T_12557, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_12559 = or(_T_12558, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12560 = and(_T_12556, _T_12559) @[ifu_bp_ctl.scala 444:87] + node _T_12561 = or(_T_12552, _T_12560) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][5][1] <= _T_12561 @[ifu_bp_ctl.scala 443:27] + node _T_12562 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12563 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12564 = eq(_T_12563, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_12565 = and(_T_12562, _T_12564) @[ifu_bp_ctl.scala 443:45] + node _T_12566 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12567 = eq(_T_12566, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_12568 = or(_T_12567, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12569 = and(_T_12565, _T_12568) @[ifu_bp_ctl.scala 443:110] + node _T_12570 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12571 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12572 = eq(_T_12571, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_12573 = and(_T_12570, _T_12572) @[ifu_bp_ctl.scala 444:22] + node _T_12574 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12575 = eq(_T_12574, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_12576 = or(_T_12575, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12577 = and(_T_12573, _T_12576) @[ifu_bp_ctl.scala 444:87] + node _T_12578 = or(_T_12569, _T_12577) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][5][2] <= _T_12578 @[ifu_bp_ctl.scala 443:27] + node _T_12579 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12580 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12581 = eq(_T_12580, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_12582 = and(_T_12579, _T_12581) @[ifu_bp_ctl.scala 443:45] + node _T_12583 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12584 = eq(_T_12583, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_12585 = or(_T_12584, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12586 = and(_T_12582, _T_12585) @[ifu_bp_ctl.scala 443:110] + node _T_12587 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12588 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12589 = eq(_T_12588, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_12590 = and(_T_12587, _T_12589) @[ifu_bp_ctl.scala 444:22] + node _T_12591 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12592 = eq(_T_12591, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_12593 = or(_T_12592, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12594 = and(_T_12590, _T_12593) @[ifu_bp_ctl.scala 444:87] + node _T_12595 = or(_T_12586, _T_12594) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][5][3] <= _T_12595 @[ifu_bp_ctl.scala 443:27] + node _T_12596 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12597 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12598 = eq(_T_12597, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_12599 = and(_T_12596, _T_12598) @[ifu_bp_ctl.scala 443:45] + node _T_12600 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12601 = eq(_T_12600, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_12602 = or(_T_12601, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12603 = and(_T_12599, _T_12602) @[ifu_bp_ctl.scala 443:110] + node _T_12604 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12605 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12606 = eq(_T_12605, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_12607 = and(_T_12604, _T_12606) @[ifu_bp_ctl.scala 444:22] + node _T_12608 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12609 = eq(_T_12608, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_12610 = or(_T_12609, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12611 = and(_T_12607, _T_12610) @[ifu_bp_ctl.scala 444:87] + node _T_12612 = or(_T_12603, _T_12611) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][5][4] <= _T_12612 @[ifu_bp_ctl.scala 443:27] + node _T_12613 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12614 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12615 = eq(_T_12614, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_12616 = and(_T_12613, _T_12615) @[ifu_bp_ctl.scala 443:45] + node _T_12617 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12618 = eq(_T_12617, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_12619 = or(_T_12618, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12620 = and(_T_12616, _T_12619) @[ifu_bp_ctl.scala 443:110] + node _T_12621 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12622 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12623 = eq(_T_12622, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_12624 = and(_T_12621, _T_12623) @[ifu_bp_ctl.scala 444:22] + node _T_12625 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12626 = eq(_T_12625, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_12627 = or(_T_12626, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12628 = and(_T_12624, _T_12627) @[ifu_bp_ctl.scala 444:87] + node _T_12629 = or(_T_12620, _T_12628) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][5][5] <= _T_12629 @[ifu_bp_ctl.scala 443:27] + node _T_12630 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12631 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12632 = eq(_T_12631, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_12633 = and(_T_12630, _T_12632) @[ifu_bp_ctl.scala 443:45] + node _T_12634 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12635 = eq(_T_12634, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_12636 = or(_T_12635, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12637 = and(_T_12633, _T_12636) @[ifu_bp_ctl.scala 443:110] + node _T_12638 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12639 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12640 = eq(_T_12639, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_12641 = and(_T_12638, _T_12640) @[ifu_bp_ctl.scala 444:22] + node _T_12642 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12643 = eq(_T_12642, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_12644 = or(_T_12643, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12645 = and(_T_12641, _T_12644) @[ifu_bp_ctl.scala 444:87] + node _T_12646 = or(_T_12637, _T_12645) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][5][6] <= _T_12646 @[ifu_bp_ctl.scala 443:27] + node _T_12647 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12648 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12649 = eq(_T_12648, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_12650 = and(_T_12647, _T_12649) @[ifu_bp_ctl.scala 443:45] + node _T_12651 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12652 = eq(_T_12651, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_12653 = or(_T_12652, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12654 = and(_T_12650, _T_12653) @[ifu_bp_ctl.scala 443:110] + node _T_12655 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12656 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12657 = eq(_T_12656, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_12658 = and(_T_12655, _T_12657) @[ifu_bp_ctl.scala 444:22] + node _T_12659 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12660 = eq(_T_12659, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_12661 = or(_T_12660, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12662 = and(_T_12658, _T_12661) @[ifu_bp_ctl.scala 444:87] + node _T_12663 = or(_T_12654, _T_12662) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][5][7] <= _T_12663 @[ifu_bp_ctl.scala 443:27] + node _T_12664 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12665 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12666 = eq(_T_12665, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_12667 = and(_T_12664, _T_12666) @[ifu_bp_ctl.scala 443:45] + node _T_12668 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12669 = eq(_T_12668, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_12670 = or(_T_12669, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12671 = and(_T_12667, _T_12670) @[ifu_bp_ctl.scala 443:110] + node _T_12672 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12673 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12674 = eq(_T_12673, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_12675 = and(_T_12672, _T_12674) @[ifu_bp_ctl.scala 444:22] + node _T_12676 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12677 = eq(_T_12676, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_12678 = or(_T_12677, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12679 = and(_T_12675, _T_12678) @[ifu_bp_ctl.scala 444:87] + node _T_12680 = or(_T_12671, _T_12679) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][5][8] <= _T_12680 @[ifu_bp_ctl.scala 443:27] + node _T_12681 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12682 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12683 = eq(_T_12682, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_12684 = and(_T_12681, _T_12683) @[ifu_bp_ctl.scala 443:45] + node _T_12685 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12686 = eq(_T_12685, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_12687 = or(_T_12686, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12688 = and(_T_12684, _T_12687) @[ifu_bp_ctl.scala 443:110] + node _T_12689 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12690 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12691 = eq(_T_12690, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_12692 = and(_T_12689, _T_12691) @[ifu_bp_ctl.scala 444:22] + node _T_12693 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12694 = eq(_T_12693, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_12695 = or(_T_12694, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12696 = and(_T_12692, _T_12695) @[ifu_bp_ctl.scala 444:87] + node _T_12697 = or(_T_12688, _T_12696) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][5][9] <= _T_12697 @[ifu_bp_ctl.scala 443:27] + node _T_12698 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12699 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12700 = eq(_T_12699, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_12701 = and(_T_12698, _T_12700) @[ifu_bp_ctl.scala 443:45] + node _T_12702 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12703 = eq(_T_12702, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_12704 = or(_T_12703, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12705 = and(_T_12701, _T_12704) @[ifu_bp_ctl.scala 443:110] + node _T_12706 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12707 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12708 = eq(_T_12707, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_12709 = and(_T_12706, _T_12708) @[ifu_bp_ctl.scala 444:22] + node _T_12710 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12711 = eq(_T_12710, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_12712 = or(_T_12711, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12713 = and(_T_12709, _T_12712) @[ifu_bp_ctl.scala 444:87] + node _T_12714 = or(_T_12705, _T_12713) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][5][10] <= _T_12714 @[ifu_bp_ctl.scala 443:27] + node _T_12715 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12716 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12717 = eq(_T_12716, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_12718 = and(_T_12715, _T_12717) @[ifu_bp_ctl.scala 443:45] + node _T_12719 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12720 = eq(_T_12719, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_12721 = or(_T_12720, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12722 = and(_T_12718, _T_12721) @[ifu_bp_ctl.scala 443:110] + node _T_12723 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12724 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12725 = eq(_T_12724, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_12726 = and(_T_12723, _T_12725) @[ifu_bp_ctl.scala 444:22] + node _T_12727 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12728 = eq(_T_12727, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_12729 = or(_T_12728, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12730 = and(_T_12726, _T_12729) @[ifu_bp_ctl.scala 444:87] + node _T_12731 = or(_T_12722, _T_12730) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][5][11] <= _T_12731 @[ifu_bp_ctl.scala 443:27] + node _T_12732 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12733 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12734 = eq(_T_12733, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_12735 = and(_T_12732, _T_12734) @[ifu_bp_ctl.scala 443:45] + node _T_12736 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12737 = eq(_T_12736, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_12738 = or(_T_12737, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12739 = and(_T_12735, _T_12738) @[ifu_bp_ctl.scala 443:110] + node _T_12740 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12741 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12742 = eq(_T_12741, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_12743 = and(_T_12740, _T_12742) @[ifu_bp_ctl.scala 444:22] + node _T_12744 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12745 = eq(_T_12744, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_12746 = or(_T_12745, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12747 = and(_T_12743, _T_12746) @[ifu_bp_ctl.scala 444:87] + node _T_12748 = or(_T_12739, _T_12747) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][5][12] <= _T_12748 @[ifu_bp_ctl.scala 443:27] + node _T_12749 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12750 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12751 = eq(_T_12750, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_12752 = and(_T_12749, _T_12751) @[ifu_bp_ctl.scala 443:45] + node _T_12753 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12754 = eq(_T_12753, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_12755 = or(_T_12754, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12756 = and(_T_12752, _T_12755) @[ifu_bp_ctl.scala 443:110] + node _T_12757 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12758 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12759 = eq(_T_12758, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_12760 = and(_T_12757, _T_12759) @[ifu_bp_ctl.scala 444:22] + node _T_12761 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12762 = eq(_T_12761, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_12763 = or(_T_12762, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12764 = and(_T_12760, _T_12763) @[ifu_bp_ctl.scala 444:87] + node _T_12765 = or(_T_12756, _T_12764) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][5][13] <= _T_12765 @[ifu_bp_ctl.scala 443:27] + node _T_12766 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12767 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12768 = eq(_T_12767, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_12769 = and(_T_12766, _T_12768) @[ifu_bp_ctl.scala 443:45] + node _T_12770 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12771 = eq(_T_12770, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_12772 = or(_T_12771, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12773 = and(_T_12769, _T_12772) @[ifu_bp_ctl.scala 443:110] + node _T_12774 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12775 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12776 = eq(_T_12775, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_12777 = and(_T_12774, _T_12776) @[ifu_bp_ctl.scala 444:22] + node _T_12778 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12779 = eq(_T_12778, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_12780 = or(_T_12779, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12781 = and(_T_12777, _T_12780) @[ifu_bp_ctl.scala 444:87] + node _T_12782 = or(_T_12773, _T_12781) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][5][14] <= _T_12782 @[ifu_bp_ctl.scala 443:27] + node _T_12783 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12784 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12785 = eq(_T_12784, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_12786 = and(_T_12783, _T_12785) @[ifu_bp_ctl.scala 443:45] + node _T_12787 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12788 = eq(_T_12787, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_12789 = or(_T_12788, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12790 = and(_T_12786, _T_12789) @[ifu_bp_ctl.scala 443:110] + node _T_12791 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12792 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12793 = eq(_T_12792, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_12794 = and(_T_12791, _T_12793) @[ifu_bp_ctl.scala 444:22] + node _T_12795 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12796 = eq(_T_12795, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_12797 = or(_T_12796, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12798 = and(_T_12794, _T_12797) @[ifu_bp_ctl.scala 444:87] + node _T_12799 = or(_T_12790, _T_12798) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][5][15] <= _T_12799 @[ifu_bp_ctl.scala 443:27] + node _T_12800 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12801 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12802 = eq(_T_12801, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_12803 = and(_T_12800, _T_12802) @[ifu_bp_ctl.scala 443:45] + node _T_12804 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12805 = eq(_T_12804, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_12806 = or(_T_12805, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12807 = and(_T_12803, _T_12806) @[ifu_bp_ctl.scala 443:110] + node _T_12808 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12809 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12810 = eq(_T_12809, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_12811 = and(_T_12808, _T_12810) @[ifu_bp_ctl.scala 444:22] + node _T_12812 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12813 = eq(_T_12812, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_12814 = or(_T_12813, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12815 = and(_T_12811, _T_12814) @[ifu_bp_ctl.scala 444:87] + node _T_12816 = or(_T_12807, _T_12815) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][6][0] <= _T_12816 @[ifu_bp_ctl.scala 443:27] + node _T_12817 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12818 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12819 = eq(_T_12818, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_12820 = and(_T_12817, _T_12819) @[ifu_bp_ctl.scala 443:45] + node _T_12821 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12822 = eq(_T_12821, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_12823 = or(_T_12822, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12824 = and(_T_12820, _T_12823) @[ifu_bp_ctl.scala 443:110] + node _T_12825 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12826 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12827 = eq(_T_12826, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_12828 = and(_T_12825, _T_12827) @[ifu_bp_ctl.scala 444:22] + node _T_12829 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12830 = eq(_T_12829, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_12831 = or(_T_12830, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12832 = and(_T_12828, _T_12831) @[ifu_bp_ctl.scala 444:87] + node _T_12833 = or(_T_12824, _T_12832) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][6][1] <= _T_12833 @[ifu_bp_ctl.scala 443:27] + node _T_12834 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12835 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12836 = eq(_T_12835, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_12837 = and(_T_12834, _T_12836) @[ifu_bp_ctl.scala 443:45] + node _T_12838 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12839 = eq(_T_12838, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_12840 = or(_T_12839, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12841 = and(_T_12837, _T_12840) @[ifu_bp_ctl.scala 443:110] + node _T_12842 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12843 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12844 = eq(_T_12843, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_12845 = and(_T_12842, _T_12844) @[ifu_bp_ctl.scala 444:22] + node _T_12846 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12847 = eq(_T_12846, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_12848 = or(_T_12847, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12849 = and(_T_12845, _T_12848) @[ifu_bp_ctl.scala 444:87] + node _T_12850 = or(_T_12841, _T_12849) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][6][2] <= _T_12850 @[ifu_bp_ctl.scala 443:27] + node _T_12851 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12852 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12853 = eq(_T_12852, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_12854 = and(_T_12851, _T_12853) @[ifu_bp_ctl.scala 443:45] + node _T_12855 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12856 = eq(_T_12855, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_12857 = or(_T_12856, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12858 = and(_T_12854, _T_12857) @[ifu_bp_ctl.scala 443:110] + node _T_12859 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12860 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12861 = eq(_T_12860, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_12862 = and(_T_12859, _T_12861) @[ifu_bp_ctl.scala 444:22] + node _T_12863 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12864 = eq(_T_12863, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_12865 = or(_T_12864, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12866 = and(_T_12862, _T_12865) @[ifu_bp_ctl.scala 444:87] + node _T_12867 = or(_T_12858, _T_12866) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][6][3] <= _T_12867 @[ifu_bp_ctl.scala 443:27] + node _T_12868 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12869 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12870 = eq(_T_12869, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_12871 = and(_T_12868, _T_12870) @[ifu_bp_ctl.scala 443:45] + node _T_12872 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12873 = eq(_T_12872, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_12874 = or(_T_12873, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12875 = and(_T_12871, _T_12874) @[ifu_bp_ctl.scala 443:110] + node _T_12876 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12877 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12878 = eq(_T_12877, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_12879 = and(_T_12876, _T_12878) @[ifu_bp_ctl.scala 444:22] + node _T_12880 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12881 = eq(_T_12880, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_12882 = or(_T_12881, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12883 = and(_T_12879, _T_12882) @[ifu_bp_ctl.scala 444:87] + node _T_12884 = or(_T_12875, _T_12883) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][6][4] <= _T_12884 @[ifu_bp_ctl.scala 443:27] + node _T_12885 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12886 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12887 = eq(_T_12886, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_12888 = and(_T_12885, _T_12887) @[ifu_bp_ctl.scala 443:45] + node _T_12889 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12890 = eq(_T_12889, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_12891 = or(_T_12890, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12892 = and(_T_12888, _T_12891) @[ifu_bp_ctl.scala 443:110] + node _T_12893 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12894 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12895 = eq(_T_12894, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_12896 = and(_T_12893, _T_12895) @[ifu_bp_ctl.scala 444:22] + node _T_12897 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12898 = eq(_T_12897, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_12899 = or(_T_12898, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12900 = and(_T_12896, _T_12899) @[ifu_bp_ctl.scala 444:87] + node _T_12901 = or(_T_12892, _T_12900) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][6][5] <= _T_12901 @[ifu_bp_ctl.scala 443:27] + node _T_12902 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12903 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12904 = eq(_T_12903, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_12905 = and(_T_12902, _T_12904) @[ifu_bp_ctl.scala 443:45] + node _T_12906 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12907 = eq(_T_12906, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_12908 = or(_T_12907, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12909 = and(_T_12905, _T_12908) @[ifu_bp_ctl.scala 443:110] + node _T_12910 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12911 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12912 = eq(_T_12911, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_12913 = and(_T_12910, _T_12912) @[ifu_bp_ctl.scala 444:22] + node _T_12914 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12915 = eq(_T_12914, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_12916 = or(_T_12915, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12917 = and(_T_12913, _T_12916) @[ifu_bp_ctl.scala 444:87] + node _T_12918 = or(_T_12909, _T_12917) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][6][6] <= _T_12918 @[ifu_bp_ctl.scala 443:27] + node _T_12919 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12920 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12921 = eq(_T_12920, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_12922 = and(_T_12919, _T_12921) @[ifu_bp_ctl.scala 443:45] + node _T_12923 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12924 = eq(_T_12923, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_12925 = or(_T_12924, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12926 = and(_T_12922, _T_12925) @[ifu_bp_ctl.scala 443:110] + node _T_12927 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12928 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12929 = eq(_T_12928, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_12930 = and(_T_12927, _T_12929) @[ifu_bp_ctl.scala 444:22] + node _T_12931 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12932 = eq(_T_12931, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_12933 = or(_T_12932, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12934 = and(_T_12930, _T_12933) @[ifu_bp_ctl.scala 444:87] + node _T_12935 = or(_T_12926, _T_12934) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][6][7] <= _T_12935 @[ifu_bp_ctl.scala 443:27] + node _T_12936 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12937 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12938 = eq(_T_12937, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_12939 = and(_T_12936, _T_12938) @[ifu_bp_ctl.scala 443:45] + node _T_12940 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12941 = eq(_T_12940, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_12942 = or(_T_12941, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12943 = and(_T_12939, _T_12942) @[ifu_bp_ctl.scala 443:110] + node _T_12944 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12945 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12946 = eq(_T_12945, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_12947 = and(_T_12944, _T_12946) @[ifu_bp_ctl.scala 444:22] + node _T_12948 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12949 = eq(_T_12948, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_12950 = or(_T_12949, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12951 = and(_T_12947, _T_12950) @[ifu_bp_ctl.scala 444:87] + node _T_12952 = or(_T_12943, _T_12951) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][6][8] <= _T_12952 @[ifu_bp_ctl.scala 443:27] + node _T_12953 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12954 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12955 = eq(_T_12954, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_12956 = and(_T_12953, _T_12955) @[ifu_bp_ctl.scala 443:45] + node _T_12957 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12958 = eq(_T_12957, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_12959 = or(_T_12958, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12960 = and(_T_12956, _T_12959) @[ifu_bp_ctl.scala 443:110] + node _T_12961 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12962 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12963 = eq(_T_12962, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_12964 = and(_T_12961, _T_12963) @[ifu_bp_ctl.scala 444:22] + node _T_12965 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12966 = eq(_T_12965, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_12967 = or(_T_12966, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12968 = and(_T_12964, _T_12967) @[ifu_bp_ctl.scala 444:87] + node _T_12969 = or(_T_12960, _T_12968) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][6][9] <= _T_12969 @[ifu_bp_ctl.scala 443:27] + node _T_12970 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12971 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12972 = eq(_T_12971, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_12973 = and(_T_12970, _T_12972) @[ifu_bp_ctl.scala 443:45] + node _T_12974 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12975 = eq(_T_12974, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_12976 = or(_T_12975, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12977 = and(_T_12973, _T_12976) @[ifu_bp_ctl.scala 443:110] + node _T_12978 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12979 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12980 = eq(_T_12979, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_12981 = and(_T_12978, _T_12980) @[ifu_bp_ctl.scala 444:22] + node _T_12982 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_12983 = eq(_T_12982, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_12984 = or(_T_12983, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_12985 = and(_T_12981, _T_12984) @[ifu_bp_ctl.scala 444:87] + node _T_12986 = or(_T_12977, _T_12985) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][6][10] <= _T_12986 @[ifu_bp_ctl.scala 443:27] + node _T_12987 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_12988 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_12989 = eq(_T_12988, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_12990 = and(_T_12987, _T_12989) @[ifu_bp_ctl.scala 443:45] + node _T_12991 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_12992 = eq(_T_12991, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_12993 = or(_T_12992, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_12994 = and(_T_12990, _T_12993) @[ifu_bp_ctl.scala 443:110] + node _T_12995 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_12996 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_12997 = eq(_T_12996, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_12998 = and(_T_12995, _T_12997) @[ifu_bp_ctl.scala 444:22] + node _T_12999 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13000 = eq(_T_12999, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_13001 = or(_T_13000, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13002 = and(_T_12998, _T_13001) @[ifu_bp_ctl.scala 444:87] + node _T_13003 = or(_T_12994, _T_13002) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][6][11] <= _T_13003 @[ifu_bp_ctl.scala 443:27] + node _T_13004 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13005 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13006 = eq(_T_13005, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_13007 = and(_T_13004, _T_13006) @[ifu_bp_ctl.scala 443:45] + node _T_13008 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13009 = eq(_T_13008, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_13010 = or(_T_13009, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13011 = and(_T_13007, _T_13010) @[ifu_bp_ctl.scala 443:110] + node _T_13012 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13013 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13014 = eq(_T_13013, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_13015 = and(_T_13012, _T_13014) @[ifu_bp_ctl.scala 444:22] + node _T_13016 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13017 = eq(_T_13016, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_13018 = or(_T_13017, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13019 = and(_T_13015, _T_13018) @[ifu_bp_ctl.scala 444:87] + node _T_13020 = or(_T_13011, _T_13019) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][6][12] <= _T_13020 @[ifu_bp_ctl.scala 443:27] + node _T_13021 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13022 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13023 = eq(_T_13022, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_13024 = and(_T_13021, _T_13023) @[ifu_bp_ctl.scala 443:45] + node _T_13025 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13026 = eq(_T_13025, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_13027 = or(_T_13026, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13028 = and(_T_13024, _T_13027) @[ifu_bp_ctl.scala 443:110] + node _T_13029 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13030 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13031 = eq(_T_13030, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_13032 = and(_T_13029, _T_13031) @[ifu_bp_ctl.scala 444:22] + node _T_13033 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13034 = eq(_T_13033, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_13035 = or(_T_13034, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13036 = and(_T_13032, _T_13035) @[ifu_bp_ctl.scala 444:87] + node _T_13037 = or(_T_13028, _T_13036) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][6][13] <= _T_13037 @[ifu_bp_ctl.scala 443:27] + node _T_13038 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13039 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13040 = eq(_T_13039, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_13041 = and(_T_13038, _T_13040) @[ifu_bp_ctl.scala 443:45] + node _T_13042 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13043 = eq(_T_13042, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_13044 = or(_T_13043, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13045 = and(_T_13041, _T_13044) @[ifu_bp_ctl.scala 443:110] + node _T_13046 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13047 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13048 = eq(_T_13047, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_13049 = and(_T_13046, _T_13048) @[ifu_bp_ctl.scala 444:22] + node _T_13050 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13051 = eq(_T_13050, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_13052 = or(_T_13051, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13053 = and(_T_13049, _T_13052) @[ifu_bp_ctl.scala 444:87] + node _T_13054 = or(_T_13045, _T_13053) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][6][14] <= _T_13054 @[ifu_bp_ctl.scala 443:27] + node _T_13055 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13056 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13057 = eq(_T_13056, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_13058 = and(_T_13055, _T_13057) @[ifu_bp_ctl.scala 443:45] + node _T_13059 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13060 = eq(_T_13059, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_13061 = or(_T_13060, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13062 = and(_T_13058, _T_13061) @[ifu_bp_ctl.scala 443:110] + node _T_13063 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13064 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13065 = eq(_T_13064, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_13066 = and(_T_13063, _T_13065) @[ifu_bp_ctl.scala 444:22] + node _T_13067 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13068 = eq(_T_13067, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_13069 = or(_T_13068, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13070 = and(_T_13066, _T_13069) @[ifu_bp_ctl.scala 444:87] + node _T_13071 = or(_T_13062, _T_13070) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][6][15] <= _T_13071 @[ifu_bp_ctl.scala 443:27] + node _T_13072 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13073 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13074 = eq(_T_13073, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_13075 = and(_T_13072, _T_13074) @[ifu_bp_ctl.scala 443:45] + node _T_13076 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13077 = eq(_T_13076, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_13078 = or(_T_13077, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13079 = and(_T_13075, _T_13078) @[ifu_bp_ctl.scala 443:110] + node _T_13080 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13081 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13082 = eq(_T_13081, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_13083 = and(_T_13080, _T_13082) @[ifu_bp_ctl.scala 444:22] + node _T_13084 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13085 = eq(_T_13084, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_13086 = or(_T_13085, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13087 = and(_T_13083, _T_13086) @[ifu_bp_ctl.scala 444:87] + node _T_13088 = or(_T_13079, _T_13087) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][7][0] <= _T_13088 @[ifu_bp_ctl.scala 443:27] + node _T_13089 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13090 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13091 = eq(_T_13090, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_13092 = and(_T_13089, _T_13091) @[ifu_bp_ctl.scala 443:45] + node _T_13093 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13094 = eq(_T_13093, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_13095 = or(_T_13094, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13096 = and(_T_13092, _T_13095) @[ifu_bp_ctl.scala 443:110] + node _T_13097 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13098 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13099 = eq(_T_13098, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_13100 = and(_T_13097, _T_13099) @[ifu_bp_ctl.scala 444:22] + node _T_13101 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13102 = eq(_T_13101, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_13103 = or(_T_13102, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13104 = and(_T_13100, _T_13103) @[ifu_bp_ctl.scala 444:87] + node _T_13105 = or(_T_13096, _T_13104) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][7][1] <= _T_13105 @[ifu_bp_ctl.scala 443:27] + node _T_13106 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13107 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13108 = eq(_T_13107, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_13109 = and(_T_13106, _T_13108) @[ifu_bp_ctl.scala 443:45] + node _T_13110 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13111 = eq(_T_13110, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_13112 = or(_T_13111, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13113 = and(_T_13109, _T_13112) @[ifu_bp_ctl.scala 443:110] + node _T_13114 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13115 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13116 = eq(_T_13115, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_13117 = and(_T_13114, _T_13116) @[ifu_bp_ctl.scala 444:22] + node _T_13118 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13119 = eq(_T_13118, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_13120 = or(_T_13119, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13121 = and(_T_13117, _T_13120) @[ifu_bp_ctl.scala 444:87] + node _T_13122 = or(_T_13113, _T_13121) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][7][2] <= _T_13122 @[ifu_bp_ctl.scala 443:27] + node _T_13123 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13124 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13125 = eq(_T_13124, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_13126 = and(_T_13123, _T_13125) @[ifu_bp_ctl.scala 443:45] + node _T_13127 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13128 = eq(_T_13127, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_13129 = or(_T_13128, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13130 = and(_T_13126, _T_13129) @[ifu_bp_ctl.scala 443:110] + node _T_13131 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13132 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13133 = eq(_T_13132, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_13134 = and(_T_13131, _T_13133) @[ifu_bp_ctl.scala 444:22] + node _T_13135 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13136 = eq(_T_13135, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_13137 = or(_T_13136, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13138 = and(_T_13134, _T_13137) @[ifu_bp_ctl.scala 444:87] + node _T_13139 = or(_T_13130, _T_13138) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][7][3] <= _T_13139 @[ifu_bp_ctl.scala 443:27] + node _T_13140 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13141 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13142 = eq(_T_13141, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_13143 = and(_T_13140, _T_13142) @[ifu_bp_ctl.scala 443:45] + node _T_13144 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13145 = eq(_T_13144, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_13146 = or(_T_13145, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13147 = and(_T_13143, _T_13146) @[ifu_bp_ctl.scala 443:110] + node _T_13148 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13149 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13150 = eq(_T_13149, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_13151 = and(_T_13148, _T_13150) @[ifu_bp_ctl.scala 444:22] + node _T_13152 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13153 = eq(_T_13152, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_13154 = or(_T_13153, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13155 = and(_T_13151, _T_13154) @[ifu_bp_ctl.scala 444:87] + node _T_13156 = or(_T_13147, _T_13155) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][7][4] <= _T_13156 @[ifu_bp_ctl.scala 443:27] + node _T_13157 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13158 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13159 = eq(_T_13158, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_13160 = and(_T_13157, _T_13159) @[ifu_bp_ctl.scala 443:45] + node _T_13161 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13162 = eq(_T_13161, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_13163 = or(_T_13162, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13164 = and(_T_13160, _T_13163) @[ifu_bp_ctl.scala 443:110] + node _T_13165 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13166 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13167 = eq(_T_13166, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_13168 = and(_T_13165, _T_13167) @[ifu_bp_ctl.scala 444:22] + node _T_13169 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13170 = eq(_T_13169, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_13171 = or(_T_13170, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13172 = and(_T_13168, _T_13171) @[ifu_bp_ctl.scala 444:87] + node _T_13173 = or(_T_13164, _T_13172) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][7][5] <= _T_13173 @[ifu_bp_ctl.scala 443:27] + node _T_13174 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13175 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13176 = eq(_T_13175, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_13177 = and(_T_13174, _T_13176) @[ifu_bp_ctl.scala 443:45] + node _T_13178 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13179 = eq(_T_13178, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_13180 = or(_T_13179, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13181 = and(_T_13177, _T_13180) @[ifu_bp_ctl.scala 443:110] + node _T_13182 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13183 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13184 = eq(_T_13183, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_13185 = and(_T_13182, _T_13184) @[ifu_bp_ctl.scala 444:22] + node _T_13186 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13187 = eq(_T_13186, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_13188 = or(_T_13187, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13189 = and(_T_13185, _T_13188) @[ifu_bp_ctl.scala 444:87] + node _T_13190 = or(_T_13181, _T_13189) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][7][6] <= _T_13190 @[ifu_bp_ctl.scala 443:27] + node _T_13191 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13192 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13193 = eq(_T_13192, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_13194 = and(_T_13191, _T_13193) @[ifu_bp_ctl.scala 443:45] + node _T_13195 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13196 = eq(_T_13195, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_13197 = or(_T_13196, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13198 = and(_T_13194, _T_13197) @[ifu_bp_ctl.scala 443:110] + node _T_13199 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13200 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13201 = eq(_T_13200, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_13202 = and(_T_13199, _T_13201) @[ifu_bp_ctl.scala 444:22] + node _T_13203 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13204 = eq(_T_13203, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_13205 = or(_T_13204, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13206 = and(_T_13202, _T_13205) @[ifu_bp_ctl.scala 444:87] + node _T_13207 = or(_T_13198, _T_13206) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][7][7] <= _T_13207 @[ifu_bp_ctl.scala 443:27] + node _T_13208 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13209 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13210 = eq(_T_13209, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_13211 = and(_T_13208, _T_13210) @[ifu_bp_ctl.scala 443:45] + node _T_13212 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13213 = eq(_T_13212, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_13214 = or(_T_13213, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13215 = and(_T_13211, _T_13214) @[ifu_bp_ctl.scala 443:110] + node _T_13216 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13217 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13218 = eq(_T_13217, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_13219 = and(_T_13216, _T_13218) @[ifu_bp_ctl.scala 444:22] + node _T_13220 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13221 = eq(_T_13220, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_13222 = or(_T_13221, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13223 = and(_T_13219, _T_13222) @[ifu_bp_ctl.scala 444:87] + node _T_13224 = or(_T_13215, _T_13223) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][7][8] <= _T_13224 @[ifu_bp_ctl.scala 443:27] + node _T_13225 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13226 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13227 = eq(_T_13226, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_13228 = and(_T_13225, _T_13227) @[ifu_bp_ctl.scala 443:45] + node _T_13229 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13230 = eq(_T_13229, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_13231 = or(_T_13230, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13232 = and(_T_13228, _T_13231) @[ifu_bp_ctl.scala 443:110] + node _T_13233 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13234 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13235 = eq(_T_13234, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_13236 = and(_T_13233, _T_13235) @[ifu_bp_ctl.scala 444:22] + node _T_13237 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13238 = eq(_T_13237, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_13239 = or(_T_13238, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13240 = and(_T_13236, _T_13239) @[ifu_bp_ctl.scala 444:87] + node _T_13241 = or(_T_13232, _T_13240) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][7][9] <= _T_13241 @[ifu_bp_ctl.scala 443:27] + node _T_13242 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13243 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13244 = eq(_T_13243, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_13245 = and(_T_13242, _T_13244) @[ifu_bp_ctl.scala 443:45] + node _T_13246 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13247 = eq(_T_13246, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_13248 = or(_T_13247, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13249 = and(_T_13245, _T_13248) @[ifu_bp_ctl.scala 443:110] + node _T_13250 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13251 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13252 = eq(_T_13251, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_13253 = and(_T_13250, _T_13252) @[ifu_bp_ctl.scala 444:22] + node _T_13254 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13255 = eq(_T_13254, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_13256 = or(_T_13255, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13257 = and(_T_13253, _T_13256) @[ifu_bp_ctl.scala 444:87] + node _T_13258 = or(_T_13249, _T_13257) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][7][10] <= _T_13258 @[ifu_bp_ctl.scala 443:27] + node _T_13259 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13260 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13261 = eq(_T_13260, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_13262 = and(_T_13259, _T_13261) @[ifu_bp_ctl.scala 443:45] + node _T_13263 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13264 = eq(_T_13263, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_13265 = or(_T_13264, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13266 = and(_T_13262, _T_13265) @[ifu_bp_ctl.scala 443:110] + node _T_13267 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13268 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13269 = eq(_T_13268, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_13270 = and(_T_13267, _T_13269) @[ifu_bp_ctl.scala 444:22] + node _T_13271 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13272 = eq(_T_13271, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_13273 = or(_T_13272, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13274 = and(_T_13270, _T_13273) @[ifu_bp_ctl.scala 444:87] + node _T_13275 = or(_T_13266, _T_13274) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][7][11] <= _T_13275 @[ifu_bp_ctl.scala 443:27] + node _T_13276 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13277 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13278 = eq(_T_13277, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_13279 = and(_T_13276, _T_13278) @[ifu_bp_ctl.scala 443:45] + node _T_13280 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13281 = eq(_T_13280, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_13282 = or(_T_13281, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13283 = and(_T_13279, _T_13282) @[ifu_bp_ctl.scala 443:110] + node _T_13284 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13285 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13286 = eq(_T_13285, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_13287 = and(_T_13284, _T_13286) @[ifu_bp_ctl.scala 444:22] + node _T_13288 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13289 = eq(_T_13288, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_13290 = or(_T_13289, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13291 = and(_T_13287, _T_13290) @[ifu_bp_ctl.scala 444:87] + node _T_13292 = or(_T_13283, _T_13291) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][7][12] <= _T_13292 @[ifu_bp_ctl.scala 443:27] + node _T_13293 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13294 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13295 = eq(_T_13294, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_13296 = and(_T_13293, _T_13295) @[ifu_bp_ctl.scala 443:45] + node _T_13297 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13298 = eq(_T_13297, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_13299 = or(_T_13298, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13300 = and(_T_13296, _T_13299) @[ifu_bp_ctl.scala 443:110] + node _T_13301 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13302 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13303 = eq(_T_13302, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_13304 = and(_T_13301, _T_13303) @[ifu_bp_ctl.scala 444:22] + node _T_13305 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13306 = eq(_T_13305, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_13307 = or(_T_13306, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13308 = and(_T_13304, _T_13307) @[ifu_bp_ctl.scala 444:87] + node _T_13309 = or(_T_13300, _T_13308) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][7][13] <= _T_13309 @[ifu_bp_ctl.scala 443:27] + node _T_13310 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13311 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13312 = eq(_T_13311, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_13313 = and(_T_13310, _T_13312) @[ifu_bp_ctl.scala 443:45] + node _T_13314 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13315 = eq(_T_13314, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_13316 = or(_T_13315, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13317 = and(_T_13313, _T_13316) @[ifu_bp_ctl.scala 443:110] + node _T_13318 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13319 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13320 = eq(_T_13319, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_13321 = and(_T_13318, _T_13320) @[ifu_bp_ctl.scala 444:22] + node _T_13322 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13323 = eq(_T_13322, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_13324 = or(_T_13323, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13325 = and(_T_13321, _T_13324) @[ifu_bp_ctl.scala 444:87] + node _T_13326 = or(_T_13317, _T_13325) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][7][14] <= _T_13326 @[ifu_bp_ctl.scala 443:27] + node _T_13327 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13328 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13329 = eq(_T_13328, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_13330 = and(_T_13327, _T_13329) @[ifu_bp_ctl.scala 443:45] + node _T_13331 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13332 = eq(_T_13331, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_13333 = or(_T_13332, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13334 = and(_T_13330, _T_13333) @[ifu_bp_ctl.scala 443:110] + node _T_13335 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13336 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13337 = eq(_T_13336, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_13338 = and(_T_13335, _T_13337) @[ifu_bp_ctl.scala 444:22] + node _T_13339 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13340 = eq(_T_13339, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_13341 = or(_T_13340, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13342 = and(_T_13338, _T_13341) @[ifu_bp_ctl.scala 444:87] + node _T_13343 = or(_T_13334, _T_13342) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][7][15] <= _T_13343 @[ifu_bp_ctl.scala 443:27] + node _T_13344 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13345 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13346 = eq(_T_13345, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_13347 = and(_T_13344, _T_13346) @[ifu_bp_ctl.scala 443:45] + node _T_13348 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13349 = eq(_T_13348, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_13350 = or(_T_13349, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13351 = and(_T_13347, _T_13350) @[ifu_bp_ctl.scala 443:110] + node _T_13352 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13353 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13354 = eq(_T_13353, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_13355 = and(_T_13352, _T_13354) @[ifu_bp_ctl.scala 444:22] + node _T_13356 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13357 = eq(_T_13356, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_13358 = or(_T_13357, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13359 = and(_T_13355, _T_13358) @[ifu_bp_ctl.scala 444:87] + node _T_13360 = or(_T_13351, _T_13359) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][8][0] <= _T_13360 @[ifu_bp_ctl.scala 443:27] + node _T_13361 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13362 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13363 = eq(_T_13362, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_13364 = and(_T_13361, _T_13363) @[ifu_bp_ctl.scala 443:45] + node _T_13365 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13366 = eq(_T_13365, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_13367 = or(_T_13366, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13368 = and(_T_13364, _T_13367) @[ifu_bp_ctl.scala 443:110] + node _T_13369 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13370 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13371 = eq(_T_13370, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_13372 = and(_T_13369, _T_13371) @[ifu_bp_ctl.scala 444:22] + node _T_13373 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13374 = eq(_T_13373, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_13375 = or(_T_13374, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13376 = and(_T_13372, _T_13375) @[ifu_bp_ctl.scala 444:87] + node _T_13377 = or(_T_13368, _T_13376) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][8][1] <= _T_13377 @[ifu_bp_ctl.scala 443:27] + node _T_13378 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13379 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13380 = eq(_T_13379, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_13381 = and(_T_13378, _T_13380) @[ifu_bp_ctl.scala 443:45] + node _T_13382 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13383 = eq(_T_13382, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_13384 = or(_T_13383, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13385 = and(_T_13381, _T_13384) @[ifu_bp_ctl.scala 443:110] + node _T_13386 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13387 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13388 = eq(_T_13387, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_13389 = and(_T_13386, _T_13388) @[ifu_bp_ctl.scala 444:22] + node _T_13390 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13391 = eq(_T_13390, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_13392 = or(_T_13391, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13393 = and(_T_13389, _T_13392) @[ifu_bp_ctl.scala 444:87] + node _T_13394 = or(_T_13385, _T_13393) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][8][2] <= _T_13394 @[ifu_bp_ctl.scala 443:27] + node _T_13395 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13396 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13397 = eq(_T_13396, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_13398 = and(_T_13395, _T_13397) @[ifu_bp_ctl.scala 443:45] + node _T_13399 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13400 = eq(_T_13399, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_13401 = or(_T_13400, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13402 = and(_T_13398, _T_13401) @[ifu_bp_ctl.scala 443:110] + node _T_13403 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13404 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13405 = eq(_T_13404, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_13406 = and(_T_13403, _T_13405) @[ifu_bp_ctl.scala 444:22] + node _T_13407 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13408 = eq(_T_13407, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_13409 = or(_T_13408, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13410 = and(_T_13406, _T_13409) @[ifu_bp_ctl.scala 444:87] + node _T_13411 = or(_T_13402, _T_13410) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][8][3] <= _T_13411 @[ifu_bp_ctl.scala 443:27] + node _T_13412 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13413 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13414 = eq(_T_13413, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_13415 = and(_T_13412, _T_13414) @[ifu_bp_ctl.scala 443:45] + node _T_13416 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13417 = eq(_T_13416, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_13418 = or(_T_13417, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13419 = and(_T_13415, _T_13418) @[ifu_bp_ctl.scala 443:110] + node _T_13420 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13421 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13422 = eq(_T_13421, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_13423 = and(_T_13420, _T_13422) @[ifu_bp_ctl.scala 444:22] + node _T_13424 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13425 = eq(_T_13424, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_13426 = or(_T_13425, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13427 = and(_T_13423, _T_13426) @[ifu_bp_ctl.scala 444:87] + node _T_13428 = or(_T_13419, _T_13427) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][8][4] <= _T_13428 @[ifu_bp_ctl.scala 443:27] + node _T_13429 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13430 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13431 = eq(_T_13430, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_13432 = and(_T_13429, _T_13431) @[ifu_bp_ctl.scala 443:45] + node _T_13433 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13434 = eq(_T_13433, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_13435 = or(_T_13434, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13436 = and(_T_13432, _T_13435) @[ifu_bp_ctl.scala 443:110] + node _T_13437 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13438 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13439 = eq(_T_13438, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_13440 = and(_T_13437, _T_13439) @[ifu_bp_ctl.scala 444:22] + node _T_13441 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13442 = eq(_T_13441, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_13443 = or(_T_13442, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13444 = and(_T_13440, _T_13443) @[ifu_bp_ctl.scala 444:87] + node _T_13445 = or(_T_13436, _T_13444) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][8][5] <= _T_13445 @[ifu_bp_ctl.scala 443:27] + node _T_13446 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13447 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13448 = eq(_T_13447, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_13449 = and(_T_13446, _T_13448) @[ifu_bp_ctl.scala 443:45] + node _T_13450 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13451 = eq(_T_13450, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_13452 = or(_T_13451, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13453 = and(_T_13449, _T_13452) @[ifu_bp_ctl.scala 443:110] + node _T_13454 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13455 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13456 = eq(_T_13455, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_13457 = and(_T_13454, _T_13456) @[ifu_bp_ctl.scala 444:22] + node _T_13458 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13459 = eq(_T_13458, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_13460 = or(_T_13459, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13461 = and(_T_13457, _T_13460) @[ifu_bp_ctl.scala 444:87] + node _T_13462 = or(_T_13453, _T_13461) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][8][6] <= _T_13462 @[ifu_bp_ctl.scala 443:27] + node _T_13463 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13464 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13465 = eq(_T_13464, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_13466 = and(_T_13463, _T_13465) @[ifu_bp_ctl.scala 443:45] + node _T_13467 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13468 = eq(_T_13467, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_13469 = or(_T_13468, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13470 = and(_T_13466, _T_13469) @[ifu_bp_ctl.scala 443:110] + node _T_13471 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13472 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13473 = eq(_T_13472, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_13474 = and(_T_13471, _T_13473) @[ifu_bp_ctl.scala 444:22] + node _T_13475 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13476 = eq(_T_13475, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_13477 = or(_T_13476, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13478 = and(_T_13474, _T_13477) @[ifu_bp_ctl.scala 444:87] + node _T_13479 = or(_T_13470, _T_13478) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][8][7] <= _T_13479 @[ifu_bp_ctl.scala 443:27] + node _T_13480 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13481 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13482 = eq(_T_13481, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_13483 = and(_T_13480, _T_13482) @[ifu_bp_ctl.scala 443:45] + node _T_13484 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13485 = eq(_T_13484, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_13486 = or(_T_13485, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13487 = and(_T_13483, _T_13486) @[ifu_bp_ctl.scala 443:110] + node _T_13488 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13489 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13490 = eq(_T_13489, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_13491 = and(_T_13488, _T_13490) @[ifu_bp_ctl.scala 444:22] + node _T_13492 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13493 = eq(_T_13492, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_13494 = or(_T_13493, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13495 = and(_T_13491, _T_13494) @[ifu_bp_ctl.scala 444:87] + node _T_13496 = or(_T_13487, _T_13495) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][8][8] <= _T_13496 @[ifu_bp_ctl.scala 443:27] + node _T_13497 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13498 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13499 = eq(_T_13498, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_13500 = and(_T_13497, _T_13499) @[ifu_bp_ctl.scala 443:45] + node _T_13501 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13502 = eq(_T_13501, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_13503 = or(_T_13502, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13504 = and(_T_13500, _T_13503) @[ifu_bp_ctl.scala 443:110] + node _T_13505 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13506 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13507 = eq(_T_13506, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_13508 = and(_T_13505, _T_13507) @[ifu_bp_ctl.scala 444:22] + node _T_13509 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13510 = eq(_T_13509, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_13511 = or(_T_13510, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13512 = and(_T_13508, _T_13511) @[ifu_bp_ctl.scala 444:87] + node _T_13513 = or(_T_13504, _T_13512) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][8][9] <= _T_13513 @[ifu_bp_ctl.scala 443:27] + node _T_13514 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13515 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13516 = eq(_T_13515, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_13517 = and(_T_13514, _T_13516) @[ifu_bp_ctl.scala 443:45] + node _T_13518 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13519 = eq(_T_13518, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_13520 = or(_T_13519, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13521 = and(_T_13517, _T_13520) @[ifu_bp_ctl.scala 443:110] + node _T_13522 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13523 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13524 = eq(_T_13523, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_13525 = and(_T_13522, _T_13524) @[ifu_bp_ctl.scala 444:22] + node _T_13526 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13527 = eq(_T_13526, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_13528 = or(_T_13527, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13529 = and(_T_13525, _T_13528) @[ifu_bp_ctl.scala 444:87] + node _T_13530 = or(_T_13521, _T_13529) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][8][10] <= _T_13530 @[ifu_bp_ctl.scala 443:27] + node _T_13531 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13532 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13533 = eq(_T_13532, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_13534 = and(_T_13531, _T_13533) @[ifu_bp_ctl.scala 443:45] + node _T_13535 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13536 = eq(_T_13535, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_13537 = or(_T_13536, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13538 = and(_T_13534, _T_13537) @[ifu_bp_ctl.scala 443:110] + node _T_13539 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13540 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13541 = eq(_T_13540, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_13542 = and(_T_13539, _T_13541) @[ifu_bp_ctl.scala 444:22] + node _T_13543 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13544 = eq(_T_13543, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_13545 = or(_T_13544, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13546 = and(_T_13542, _T_13545) @[ifu_bp_ctl.scala 444:87] + node _T_13547 = or(_T_13538, _T_13546) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][8][11] <= _T_13547 @[ifu_bp_ctl.scala 443:27] + node _T_13548 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13549 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13550 = eq(_T_13549, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_13551 = and(_T_13548, _T_13550) @[ifu_bp_ctl.scala 443:45] + node _T_13552 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13553 = eq(_T_13552, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_13554 = or(_T_13553, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13555 = and(_T_13551, _T_13554) @[ifu_bp_ctl.scala 443:110] + node _T_13556 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13557 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13558 = eq(_T_13557, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_13559 = and(_T_13556, _T_13558) @[ifu_bp_ctl.scala 444:22] + node _T_13560 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13561 = eq(_T_13560, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_13562 = or(_T_13561, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13563 = and(_T_13559, _T_13562) @[ifu_bp_ctl.scala 444:87] + node _T_13564 = or(_T_13555, _T_13563) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][8][12] <= _T_13564 @[ifu_bp_ctl.scala 443:27] + node _T_13565 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13566 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13567 = eq(_T_13566, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_13568 = and(_T_13565, _T_13567) @[ifu_bp_ctl.scala 443:45] + node _T_13569 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13570 = eq(_T_13569, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_13571 = or(_T_13570, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13572 = and(_T_13568, _T_13571) @[ifu_bp_ctl.scala 443:110] + node _T_13573 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13574 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13575 = eq(_T_13574, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_13576 = and(_T_13573, _T_13575) @[ifu_bp_ctl.scala 444:22] + node _T_13577 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13578 = eq(_T_13577, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_13579 = or(_T_13578, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13580 = and(_T_13576, _T_13579) @[ifu_bp_ctl.scala 444:87] + node _T_13581 = or(_T_13572, _T_13580) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][8][13] <= _T_13581 @[ifu_bp_ctl.scala 443:27] + node _T_13582 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13583 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13584 = eq(_T_13583, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_13585 = and(_T_13582, _T_13584) @[ifu_bp_ctl.scala 443:45] + node _T_13586 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13587 = eq(_T_13586, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_13588 = or(_T_13587, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13589 = and(_T_13585, _T_13588) @[ifu_bp_ctl.scala 443:110] + node _T_13590 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13591 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13592 = eq(_T_13591, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_13593 = and(_T_13590, _T_13592) @[ifu_bp_ctl.scala 444:22] + node _T_13594 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13595 = eq(_T_13594, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_13596 = or(_T_13595, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13597 = and(_T_13593, _T_13596) @[ifu_bp_ctl.scala 444:87] + node _T_13598 = or(_T_13589, _T_13597) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][8][14] <= _T_13598 @[ifu_bp_ctl.scala 443:27] + node _T_13599 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13600 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13601 = eq(_T_13600, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_13602 = and(_T_13599, _T_13601) @[ifu_bp_ctl.scala 443:45] + node _T_13603 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13604 = eq(_T_13603, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_13605 = or(_T_13604, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13606 = and(_T_13602, _T_13605) @[ifu_bp_ctl.scala 443:110] + node _T_13607 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13608 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13609 = eq(_T_13608, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_13610 = and(_T_13607, _T_13609) @[ifu_bp_ctl.scala 444:22] + node _T_13611 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13612 = eq(_T_13611, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_13613 = or(_T_13612, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13614 = and(_T_13610, _T_13613) @[ifu_bp_ctl.scala 444:87] + node _T_13615 = or(_T_13606, _T_13614) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][8][15] <= _T_13615 @[ifu_bp_ctl.scala 443:27] + node _T_13616 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13617 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13618 = eq(_T_13617, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_13619 = and(_T_13616, _T_13618) @[ifu_bp_ctl.scala 443:45] + node _T_13620 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13621 = eq(_T_13620, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_13622 = or(_T_13621, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13623 = and(_T_13619, _T_13622) @[ifu_bp_ctl.scala 443:110] + node _T_13624 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13625 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13626 = eq(_T_13625, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_13627 = and(_T_13624, _T_13626) @[ifu_bp_ctl.scala 444:22] + node _T_13628 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13629 = eq(_T_13628, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_13630 = or(_T_13629, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13631 = and(_T_13627, _T_13630) @[ifu_bp_ctl.scala 444:87] + node _T_13632 = or(_T_13623, _T_13631) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][9][0] <= _T_13632 @[ifu_bp_ctl.scala 443:27] + node _T_13633 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13634 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13635 = eq(_T_13634, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_13636 = and(_T_13633, _T_13635) @[ifu_bp_ctl.scala 443:45] + node _T_13637 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13638 = eq(_T_13637, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_13639 = or(_T_13638, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13640 = and(_T_13636, _T_13639) @[ifu_bp_ctl.scala 443:110] + node _T_13641 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13642 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13643 = eq(_T_13642, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_13644 = and(_T_13641, _T_13643) @[ifu_bp_ctl.scala 444:22] + node _T_13645 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13646 = eq(_T_13645, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_13647 = or(_T_13646, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13648 = and(_T_13644, _T_13647) @[ifu_bp_ctl.scala 444:87] + node _T_13649 = or(_T_13640, _T_13648) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][9][1] <= _T_13649 @[ifu_bp_ctl.scala 443:27] + node _T_13650 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13651 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13652 = eq(_T_13651, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_13653 = and(_T_13650, _T_13652) @[ifu_bp_ctl.scala 443:45] + node _T_13654 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13655 = eq(_T_13654, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_13656 = or(_T_13655, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13657 = and(_T_13653, _T_13656) @[ifu_bp_ctl.scala 443:110] + node _T_13658 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13659 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13660 = eq(_T_13659, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_13661 = and(_T_13658, _T_13660) @[ifu_bp_ctl.scala 444:22] + node _T_13662 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13663 = eq(_T_13662, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_13664 = or(_T_13663, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13665 = and(_T_13661, _T_13664) @[ifu_bp_ctl.scala 444:87] + node _T_13666 = or(_T_13657, _T_13665) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][9][2] <= _T_13666 @[ifu_bp_ctl.scala 443:27] + node _T_13667 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13668 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13669 = eq(_T_13668, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_13670 = and(_T_13667, _T_13669) @[ifu_bp_ctl.scala 443:45] + node _T_13671 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13672 = eq(_T_13671, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_13673 = or(_T_13672, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13674 = and(_T_13670, _T_13673) @[ifu_bp_ctl.scala 443:110] + node _T_13675 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13676 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13677 = eq(_T_13676, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_13678 = and(_T_13675, _T_13677) @[ifu_bp_ctl.scala 444:22] + node _T_13679 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13680 = eq(_T_13679, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_13681 = or(_T_13680, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13682 = and(_T_13678, _T_13681) @[ifu_bp_ctl.scala 444:87] + node _T_13683 = or(_T_13674, _T_13682) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][9][3] <= _T_13683 @[ifu_bp_ctl.scala 443:27] + node _T_13684 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13685 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13686 = eq(_T_13685, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_13687 = and(_T_13684, _T_13686) @[ifu_bp_ctl.scala 443:45] + node _T_13688 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13689 = eq(_T_13688, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_13690 = or(_T_13689, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13691 = and(_T_13687, _T_13690) @[ifu_bp_ctl.scala 443:110] + node _T_13692 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13693 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13694 = eq(_T_13693, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_13695 = and(_T_13692, _T_13694) @[ifu_bp_ctl.scala 444:22] + node _T_13696 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13697 = eq(_T_13696, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_13698 = or(_T_13697, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13699 = and(_T_13695, _T_13698) @[ifu_bp_ctl.scala 444:87] + node _T_13700 = or(_T_13691, _T_13699) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][9][4] <= _T_13700 @[ifu_bp_ctl.scala 443:27] + node _T_13701 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13702 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13703 = eq(_T_13702, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_13704 = and(_T_13701, _T_13703) @[ifu_bp_ctl.scala 443:45] + node _T_13705 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13706 = eq(_T_13705, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_13707 = or(_T_13706, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13708 = and(_T_13704, _T_13707) @[ifu_bp_ctl.scala 443:110] + node _T_13709 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13710 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13711 = eq(_T_13710, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_13712 = and(_T_13709, _T_13711) @[ifu_bp_ctl.scala 444:22] + node _T_13713 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13714 = eq(_T_13713, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_13715 = or(_T_13714, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13716 = and(_T_13712, _T_13715) @[ifu_bp_ctl.scala 444:87] + node _T_13717 = or(_T_13708, _T_13716) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][9][5] <= _T_13717 @[ifu_bp_ctl.scala 443:27] + node _T_13718 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13719 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13720 = eq(_T_13719, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_13721 = and(_T_13718, _T_13720) @[ifu_bp_ctl.scala 443:45] + node _T_13722 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13723 = eq(_T_13722, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_13724 = or(_T_13723, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13725 = and(_T_13721, _T_13724) @[ifu_bp_ctl.scala 443:110] + node _T_13726 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13727 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13728 = eq(_T_13727, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_13729 = and(_T_13726, _T_13728) @[ifu_bp_ctl.scala 444:22] + node _T_13730 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13731 = eq(_T_13730, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_13732 = or(_T_13731, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13733 = and(_T_13729, _T_13732) @[ifu_bp_ctl.scala 444:87] + node _T_13734 = or(_T_13725, _T_13733) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][9][6] <= _T_13734 @[ifu_bp_ctl.scala 443:27] + node _T_13735 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13736 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13737 = eq(_T_13736, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_13738 = and(_T_13735, _T_13737) @[ifu_bp_ctl.scala 443:45] + node _T_13739 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13740 = eq(_T_13739, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_13741 = or(_T_13740, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13742 = and(_T_13738, _T_13741) @[ifu_bp_ctl.scala 443:110] + node _T_13743 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13744 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13745 = eq(_T_13744, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_13746 = and(_T_13743, _T_13745) @[ifu_bp_ctl.scala 444:22] + node _T_13747 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13748 = eq(_T_13747, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_13749 = or(_T_13748, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13750 = and(_T_13746, _T_13749) @[ifu_bp_ctl.scala 444:87] + node _T_13751 = or(_T_13742, _T_13750) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][9][7] <= _T_13751 @[ifu_bp_ctl.scala 443:27] + node _T_13752 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13753 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13754 = eq(_T_13753, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_13755 = and(_T_13752, _T_13754) @[ifu_bp_ctl.scala 443:45] + node _T_13756 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13757 = eq(_T_13756, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_13758 = or(_T_13757, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13759 = and(_T_13755, _T_13758) @[ifu_bp_ctl.scala 443:110] + node _T_13760 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13761 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13762 = eq(_T_13761, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_13763 = and(_T_13760, _T_13762) @[ifu_bp_ctl.scala 444:22] + node _T_13764 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13765 = eq(_T_13764, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_13766 = or(_T_13765, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13767 = and(_T_13763, _T_13766) @[ifu_bp_ctl.scala 444:87] + node _T_13768 = or(_T_13759, _T_13767) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][9][8] <= _T_13768 @[ifu_bp_ctl.scala 443:27] + node _T_13769 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13770 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13771 = eq(_T_13770, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_13772 = and(_T_13769, _T_13771) @[ifu_bp_ctl.scala 443:45] + node _T_13773 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13774 = eq(_T_13773, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_13775 = or(_T_13774, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13776 = and(_T_13772, _T_13775) @[ifu_bp_ctl.scala 443:110] + node _T_13777 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13778 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13779 = eq(_T_13778, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_13780 = and(_T_13777, _T_13779) @[ifu_bp_ctl.scala 444:22] + node _T_13781 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13782 = eq(_T_13781, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_13783 = or(_T_13782, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13784 = and(_T_13780, _T_13783) @[ifu_bp_ctl.scala 444:87] + node _T_13785 = or(_T_13776, _T_13784) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][9][9] <= _T_13785 @[ifu_bp_ctl.scala 443:27] + node _T_13786 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13787 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13788 = eq(_T_13787, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_13789 = and(_T_13786, _T_13788) @[ifu_bp_ctl.scala 443:45] + node _T_13790 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13791 = eq(_T_13790, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_13792 = or(_T_13791, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13793 = and(_T_13789, _T_13792) @[ifu_bp_ctl.scala 443:110] + node _T_13794 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13795 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13796 = eq(_T_13795, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_13797 = and(_T_13794, _T_13796) @[ifu_bp_ctl.scala 444:22] + node _T_13798 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13799 = eq(_T_13798, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_13800 = or(_T_13799, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13801 = and(_T_13797, _T_13800) @[ifu_bp_ctl.scala 444:87] + node _T_13802 = or(_T_13793, _T_13801) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][9][10] <= _T_13802 @[ifu_bp_ctl.scala 443:27] + node _T_13803 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13804 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13805 = eq(_T_13804, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_13806 = and(_T_13803, _T_13805) @[ifu_bp_ctl.scala 443:45] + node _T_13807 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13808 = eq(_T_13807, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_13809 = or(_T_13808, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13810 = and(_T_13806, _T_13809) @[ifu_bp_ctl.scala 443:110] + node _T_13811 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13812 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13813 = eq(_T_13812, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_13814 = and(_T_13811, _T_13813) @[ifu_bp_ctl.scala 444:22] + node _T_13815 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13816 = eq(_T_13815, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_13817 = or(_T_13816, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13818 = and(_T_13814, _T_13817) @[ifu_bp_ctl.scala 444:87] + node _T_13819 = or(_T_13810, _T_13818) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][9][11] <= _T_13819 @[ifu_bp_ctl.scala 443:27] + node _T_13820 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13821 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13822 = eq(_T_13821, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_13823 = and(_T_13820, _T_13822) @[ifu_bp_ctl.scala 443:45] + node _T_13824 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13825 = eq(_T_13824, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_13826 = or(_T_13825, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13827 = and(_T_13823, _T_13826) @[ifu_bp_ctl.scala 443:110] + node _T_13828 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13829 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13830 = eq(_T_13829, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_13831 = and(_T_13828, _T_13830) @[ifu_bp_ctl.scala 444:22] + node _T_13832 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13833 = eq(_T_13832, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_13834 = or(_T_13833, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13835 = and(_T_13831, _T_13834) @[ifu_bp_ctl.scala 444:87] + node _T_13836 = or(_T_13827, _T_13835) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][9][12] <= _T_13836 @[ifu_bp_ctl.scala 443:27] + node _T_13837 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13838 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13839 = eq(_T_13838, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_13840 = and(_T_13837, _T_13839) @[ifu_bp_ctl.scala 443:45] + node _T_13841 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13842 = eq(_T_13841, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_13843 = or(_T_13842, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13844 = and(_T_13840, _T_13843) @[ifu_bp_ctl.scala 443:110] + node _T_13845 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13846 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13847 = eq(_T_13846, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_13848 = and(_T_13845, _T_13847) @[ifu_bp_ctl.scala 444:22] + node _T_13849 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13850 = eq(_T_13849, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_13851 = or(_T_13850, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13852 = and(_T_13848, _T_13851) @[ifu_bp_ctl.scala 444:87] + node _T_13853 = or(_T_13844, _T_13852) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][9][13] <= _T_13853 @[ifu_bp_ctl.scala 443:27] + node _T_13854 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13855 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13856 = eq(_T_13855, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_13857 = and(_T_13854, _T_13856) @[ifu_bp_ctl.scala 443:45] + node _T_13858 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13859 = eq(_T_13858, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_13860 = or(_T_13859, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13861 = and(_T_13857, _T_13860) @[ifu_bp_ctl.scala 443:110] + node _T_13862 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13863 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13864 = eq(_T_13863, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_13865 = and(_T_13862, _T_13864) @[ifu_bp_ctl.scala 444:22] + node _T_13866 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13867 = eq(_T_13866, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_13868 = or(_T_13867, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13869 = and(_T_13865, _T_13868) @[ifu_bp_ctl.scala 444:87] + node _T_13870 = or(_T_13861, _T_13869) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][9][14] <= _T_13870 @[ifu_bp_ctl.scala 443:27] + node _T_13871 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13872 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13873 = eq(_T_13872, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_13874 = and(_T_13871, _T_13873) @[ifu_bp_ctl.scala 443:45] + node _T_13875 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13876 = eq(_T_13875, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_13877 = or(_T_13876, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13878 = and(_T_13874, _T_13877) @[ifu_bp_ctl.scala 443:110] + node _T_13879 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13880 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13881 = eq(_T_13880, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_13882 = and(_T_13879, _T_13881) @[ifu_bp_ctl.scala 444:22] + node _T_13883 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13884 = eq(_T_13883, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_13885 = or(_T_13884, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13886 = and(_T_13882, _T_13885) @[ifu_bp_ctl.scala 444:87] + node _T_13887 = or(_T_13878, _T_13886) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][9][15] <= _T_13887 @[ifu_bp_ctl.scala 443:27] + node _T_13888 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13889 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13890 = eq(_T_13889, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_13891 = and(_T_13888, _T_13890) @[ifu_bp_ctl.scala 443:45] + node _T_13892 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13893 = eq(_T_13892, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_13894 = or(_T_13893, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13895 = and(_T_13891, _T_13894) @[ifu_bp_ctl.scala 443:110] + node _T_13896 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13897 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13898 = eq(_T_13897, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_13899 = and(_T_13896, _T_13898) @[ifu_bp_ctl.scala 444:22] + node _T_13900 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13901 = eq(_T_13900, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_13902 = or(_T_13901, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13903 = and(_T_13899, _T_13902) @[ifu_bp_ctl.scala 444:87] + node _T_13904 = or(_T_13895, _T_13903) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][10][0] <= _T_13904 @[ifu_bp_ctl.scala 443:27] + node _T_13905 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13906 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13907 = eq(_T_13906, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_13908 = and(_T_13905, _T_13907) @[ifu_bp_ctl.scala 443:45] + node _T_13909 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13910 = eq(_T_13909, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_13911 = or(_T_13910, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13912 = and(_T_13908, _T_13911) @[ifu_bp_ctl.scala 443:110] + node _T_13913 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13914 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13915 = eq(_T_13914, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_13916 = and(_T_13913, _T_13915) @[ifu_bp_ctl.scala 444:22] + node _T_13917 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13918 = eq(_T_13917, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_13919 = or(_T_13918, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13920 = and(_T_13916, _T_13919) @[ifu_bp_ctl.scala 444:87] + node _T_13921 = or(_T_13912, _T_13920) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][10][1] <= _T_13921 @[ifu_bp_ctl.scala 443:27] + node _T_13922 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13923 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13924 = eq(_T_13923, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_13925 = and(_T_13922, _T_13924) @[ifu_bp_ctl.scala 443:45] + node _T_13926 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13927 = eq(_T_13926, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_13928 = or(_T_13927, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13929 = and(_T_13925, _T_13928) @[ifu_bp_ctl.scala 443:110] + node _T_13930 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13931 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13932 = eq(_T_13931, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_13933 = and(_T_13930, _T_13932) @[ifu_bp_ctl.scala 444:22] + node _T_13934 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13935 = eq(_T_13934, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_13936 = or(_T_13935, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13937 = and(_T_13933, _T_13936) @[ifu_bp_ctl.scala 444:87] + node _T_13938 = or(_T_13929, _T_13937) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][10][2] <= _T_13938 @[ifu_bp_ctl.scala 443:27] + node _T_13939 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13940 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13941 = eq(_T_13940, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_13942 = and(_T_13939, _T_13941) @[ifu_bp_ctl.scala 443:45] + node _T_13943 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13944 = eq(_T_13943, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_13945 = or(_T_13944, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13946 = and(_T_13942, _T_13945) @[ifu_bp_ctl.scala 443:110] + node _T_13947 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13948 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13949 = eq(_T_13948, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_13950 = and(_T_13947, _T_13949) @[ifu_bp_ctl.scala 444:22] + node _T_13951 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13952 = eq(_T_13951, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_13953 = or(_T_13952, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13954 = and(_T_13950, _T_13953) @[ifu_bp_ctl.scala 444:87] + node _T_13955 = or(_T_13946, _T_13954) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][10][3] <= _T_13955 @[ifu_bp_ctl.scala 443:27] + node _T_13956 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13957 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13958 = eq(_T_13957, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_13959 = and(_T_13956, _T_13958) @[ifu_bp_ctl.scala 443:45] + node _T_13960 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13961 = eq(_T_13960, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_13962 = or(_T_13961, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13963 = and(_T_13959, _T_13962) @[ifu_bp_ctl.scala 443:110] + node _T_13964 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13965 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13966 = eq(_T_13965, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_13967 = and(_T_13964, _T_13966) @[ifu_bp_ctl.scala 444:22] + node _T_13968 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13969 = eq(_T_13968, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_13970 = or(_T_13969, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13971 = and(_T_13967, _T_13970) @[ifu_bp_ctl.scala 444:87] + node _T_13972 = or(_T_13963, _T_13971) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][10][4] <= _T_13972 @[ifu_bp_ctl.scala 443:27] + node _T_13973 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13974 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13975 = eq(_T_13974, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_13976 = and(_T_13973, _T_13975) @[ifu_bp_ctl.scala 443:45] + node _T_13977 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13978 = eq(_T_13977, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_13979 = or(_T_13978, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13980 = and(_T_13976, _T_13979) @[ifu_bp_ctl.scala 443:110] + node _T_13981 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13982 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_13983 = eq(_T_13982, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_13984 = and(_T_13981, _T_13983) @[ifu_bp_ctl.scala 444:22] + node _T_13985 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_13986 = eq(_T_13985, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_13987 = or(_T_13986, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_13988 = and(_T_13984, _T_13987) @[ifu_bp_ctl.scala 444:87] + node _T_13989 = or(_T_13980, _T_13988) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][10][5] <= _T_13989 @[ifu_bp_ctl.scala 443:27] + node _T_13990 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_13991 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_13992 = eq(_T_13991, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_13993 = and(_T_13990, _T_13992) @[ifu_bp_ctl.scala 443:45] + node _T_13994 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_13995 = eq(_T_13994, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_13996 = or(_T_13995, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_13997 = and(_T_13993, _T_13996) @[ifu_bp_ctl.scala 443:110] + node _T_13998 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_13999 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14000 = eq(_T_13999, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_14001 = and(_T_13998, _T_14000) @[ifu_bp_ctl.scala 444:22] + node _T_14002 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14003 = eq(_T_14002, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_14004 = or(_T_14003, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14005 = and(_T_14001, _T_14004) @[ifu_bp_ctl.scala 444:87] + node _T_14006 = or(_T_13997, _T_14005) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][10][6] <= _T_14006 @[ifu_bp_ctl.scala 443:27] + node _T_14007 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14008 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14009 = eq(_T_14008, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_14010 = and(_T_14007, _T_14009) @[ifu_bp_ctl.scala 443:45] + node _T_14011 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14012 = eq(_T_14011, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_14013 = or(_T_14012, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14014 = and(_T_14010, _T_14013) @[ifu_bp_ctl.scala 443:110] + node _T_14015 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14016 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14017 = eq(_T_14016, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_14018 = and(_T_14015, _T_14017) @[ifu_bp_ctl.scala 444:22] + node _T_14019 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14020 = eq(_T_14019, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_14021 = or(_T_14020, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14022 = and(_T_14018, _T_14021) @[ifu_bp_ctl.scala 444:87] + node _T_14023 = or(_T_14014, _T_14022) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][10][7] <= _T_14023 @[ifu_bp_ctl.scala 443:27] + node _T_14024 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14025 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14026 = eq(_T_14025, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_14027 = and(_T_14024, _T_14026) @[ifu_bp_ctl.scala 443:45] + node _T_14028 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14029 = eq(_T_14028, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_14030 = or(_T_14029, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14031 = and(_T_14027, _T_14030) @[ifu_bp_ctl.scala 443:110] + node _T_14032 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14033 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14034 = eq(_T_14033, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_14035 = and(_T_14032, _T_14034) @[ifu_bp_ctl.scala 444:22] + node _T_14036 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14037 = eq(_T_14036, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_14038 = or(_T_14037, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14039 = and(_T_14035, _T_14038) @[ifu_bp_ctl.scala 444:87] + node _T_14040 = or(_T_14031, _T_14039) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][10][8] <= _T_14040 @[ifu_bp_ctl.scala 443:27] + node _T_14041 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14042 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14043 = eq(_T_14042, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_14044 = and(_T_14041, _T_14043) @[ifu_bp_ctl.scala 443:45] + node _T_14045 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14046 = eq(_T_14045, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_14047 = or(_T_14046, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14048 = and(_T_14044, _T_14047) @[ifu_bp_ctl.scala 443:110] + node _T_14049 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14050 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14051 = eq(_T_14050, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_14052 = and(_T_14049, _T_14051) @[ifu_bp_ctl.scala 444:22] + node _T_14053 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14054 = eq(_T_14053, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_14055 = or(_T_14054, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14056 = and(_T_14052, _T_14055) @[ifu_bp_ctl.scala 444:87] + node _T_14057 = or(_T_14048, _T_14056) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][10][9] <= _T_14057 @[ifu_bp_ctl.scala 443:27] + node _T_14058 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14059 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14060 = eq(_T_14059, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_14061 = and(_T_14058, _T_14060) @[ifu_bp_ctl.scala 443:45] + node _T_14062 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14063 = eq(_T_14062, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_14064 = or(_T_14063, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14065 = and(_T_14061, _T_14064) @[ifu_bp_ctl.scala 443:110] + node _T_14066 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14067 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14068 = eq(_T_14067, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_14069 = and(_T_14066, _T_14068) @[ifu_bp_ctl.scala 444:22] + node _T_14070 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14071 = eq(_T_14070, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_14072 = or(_T_14071, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14073 = and(_T_14069, _T_14072) @[ifu_bp_ctl.scala 444:87] + node _T_14074 = or(_T_14065, _T_14073) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][10][10] <= _T_14074 @[ifu_bp_ctl.scala 443:27] + node _T_14075 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14076 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14077 = eq(_T_14076, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_14078 = and(_T_14075, _T_14077) @[ifu_bp_ctl.scala 443:45] + node _T_14079 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14080 = eq(_T_14079, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_14081 = or(_T_14080, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14082 = and(_T_14078, _T_14081) @[ifu_bp_ctl.scala 443:110] + node _T_14083 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14084 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14085 = eq(_T_14084, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_14086 = and(_T_14083, _T_14085) @[ifu_bp_ctl.scala 444:22] + node _T_14087 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14088 = eq(_T_14087, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_14089 = or(_T_14088, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14090 = and(_T_14086, _T_14089) @[ifu_bp_ctl.scala 444:87] + node _T_14091 = or(_T_14082, _T_14090) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][10][11] <= _T_14091 @[ifu_bp_ctl.scala 443:27] + node _T_14092 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14093 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14094 = eq(_T_14093, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_14095 = and(_T_14092, _T_14094) @[ifu_bp_ctl.scala 443:45] + node _T_14096 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14097 = eq(_T_14096, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_14098 = or(_T_14097, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14099 = and(_T_14095, _T_14098) @[ifu_bp_ctl.scala 443:110] + node _T_14100 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14101 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14102 = eq(_T_14101, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_14103 = and(_T_14100, _T_14102) @[ifu_bp_ctl.scala 444:22] + node _T_14104 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14105 = eq(_T_14104, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_14106 = or(_T_14105, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14107 = and(_T_14103, _T_14106) @[ifu_bp_ctl.scala 444:87] + node _T_14108 = or(_T_14099, _T_14107) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][10][12] <= _T_14108 @[ifu_bp_ctl.scala 443:27] + node _T_14109 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14110 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14111 = eq(_T_14110, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_14112 = and(_T_14109, _T_14111) @[ifu_bp_ctl.scala 443:45] + node _T_14113 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14114 = eq(_T_14113, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_14115 = or(_T_14114, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14116 = and(_T_14112, _T_14115) @[ifu_bp_ctl.scala 443:110] + node _T_14117 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14118 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14119 = eq(_T_14118, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_14120 = and(_T_14117, _T_14119) @[ifu_bp_ctl.scala 444:22] + node _T_14121 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14122 = eq(_T_14121, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_14123 = or(_T_14122, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14124 = and(_T_14120, _T_14123) @[ifu_bp_ctl.scala 444:87] + node _T_14125 = or(_T_14116, _T_14124) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][10][13] <= _T_14125 @[ifu_bp_ctl.scala 443:27] + node _T_14126 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14127 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14128 = eq(_T_14127, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_14129 = and(_T_14126, _T_14128) @[ifu_bp_ctl.scala 443:45] + node _T_14130 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14131 = eq(_T_14130, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_14132 = or(_T_14131, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14133 = and(_T_14129, _T_14132) @[ifu_bp_ctl.scala 443:110] + node _T_14134 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14135 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14136 = eq(_T_14135, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_14137 = and(_T_14134, _T_14136) @[ifu_bp_ctl.scala 444:22] + node _T_14138 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14139 = eq(_T_14138, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_14140 = or(_T_14139, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14141 = and(_T_14137, _T_14140) @[ifu_bp_ctl.scala 444:87] + node _T_14142 = or(_T_14133, _T_14141) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][10][14] <= _T_14142 @[ifu_bp_ctl.scala 443:27] + node _T_14143 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14144 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14145 = eq(_T_14144, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_14146 = and(_T_14143, _T_14145) @[ifu_bp_ctl.scala 443:45] + node _T_14147 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14148 = eq(_T_14147, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_14149 = or(_T_14148, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14150 = and(_T_14146, _T_14149) @[ifu_bp_ctl.scala 443:110] + node _T_14151 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14152 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14153 = eq(_T_14152, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_14154 = and(_T_14151, _T_14153) @[ifu_bp_ctl.scala 444:22] + node _T_14155 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14156 = eq(_T_14155, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_14157 = or(_T_14156, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14158 = and(_T_14154, _T_14157) @[ifu_bp_ctl.scala 444:87] + node _T_14159 = or(_T_14150, _T_14158) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][10][15] <= _T_14159 @[ifu_bp_ctl.scala 443:27] + node _T_14160 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14161 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14162 = eq(_T_14161, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_14163 = and(_T_14160, _T_14162) @[ifu_bp_ctl.scala 443:45] + node _T_14164 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14165 = eq(_T_14164, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_14166 = or(_T_14165, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14167 = and(_T_14163, _T_14166) @[ifu_bp_ctl.scala 443:110] + node _T_14168 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14169 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14170 = eq(_T_14169, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_14171 = and(_T_14168, _T_14170) @[ifu_bp_ctl.scala 444:22] + node _T_14172 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14173 = eq(_T_14172, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_14174 = or(_T_14173, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14175 = and(_T_14171, _T_14174) @[ifu_bp_ctl.scala 444:87] + node _T_14176 = or(_T_14167, _T_14175) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][11][0] <= _T_14176 @[ifu_bp_ctl.scala 443:27] + node _T_14177 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14178 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14179 = eq(_T_14178, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_14180 = and(_T_14177, _T_14179) @[ifu_bp_ctl.scala 443:45] + node _T_14181 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14182 = eq(_T_14181, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_14183 = or(_T_14182, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14184 = and(_T_14180, _T_14183) @[ifu_bp_ctl.scala 443:110] + node _T_14185 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14186 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14187 = eq(_T_14186, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_14188 = and(_T_14185, _T_14187) @[ifu_bp_ctl.scala 444:22] + node _T_14189 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14190 = eq(_T_14189, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_14191 = or(_T_14190, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14192 = and(_T_14188, _T_14191) @[ifu_bp_ctl.scala 444:87] + node _T_14193 = or(_T_14184, _T_14192) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][11][1] <= _T_14193 @[ifu_bp_ctl.scala 443:27] + node _T_14194 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14195 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14196 = eq(_T_14195, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_14197 = and(_T_14194, _T_14196) @[ifu_bp_ctl.scala 443:45] + node _T_14198 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14199 = eq(_T_14198, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_14200 = or(_T_14199, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14201 = and(_T_14197, _T_14200) @[ifu_bp_ctl.scala 443:110] + node _T_14202 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14203 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14204 = eq(_T_14203, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_14205 = and(_T_14202, _T_14204) @[ifu_bp_ctl.scala 444:22] + node _T_14206 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14207 = eq(_T_14206, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_14208 = or(_T_14207, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14209 = and(_T_14205, _T_14208) @[ifu_bp_ctl.scala 444:87] + node _T_14210 = or(_T_14201, _T_14209) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][11][2] <= _T_14210 @[ifu_bp_ctl.scala 443:27] + node _T_14211 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14212 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14213 = eq(_T_14212, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_14214 = and(_T_14211, _T_14213) @[ifu_bp_ctl.scala 443:45] + node _T_14215 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14216 = eq(_T_14215, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_14217 = or(_T_14216, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14218 = and(_T_14214, _T_14217) @[ifu_bp_ctl.scala 443:110] + node _T_14219 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14220 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14221 = eq(_T_14220, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_14222 = and(_T_14219, _T_14221) @[ifu_bp_ctl.scala 444:22] + node _T_14223 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14224 = eq(_T_14223, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_14225 = or(_T_14224, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14226 = and(_T_14222, _T_14225) @[ifu_bp_ctl.scala 444:87] + node _T_14227 = or(_T_14218, _T_14226) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][11][3] <= _T_14227 @[ifu_bp_ctl.scala 443:27] + node _T_14228 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14229 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14230 = eq(_T_14229, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_14231 = and(_T_14228, _T_14230) @[ifu_bp_ctl.scala 443:45] + node _T_14232 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14233 = eq(_T_14232, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_14234 = or(_T_14233, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14235 = and(_T_14231, _T_14234) @[ifu_bp_ctl.scala 443:110] + node _T_14236 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14237 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14238 = eq(_T_14237, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_14239 = and(_T_14236, _T_14238) @[ifu_bp_ctl.scala 444:22] + node _T_14240 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14241 = eq(_T_14240, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_14242 = or(_T_14241, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14243 = and(_T_14239, _T_14242) @[ifu_bp_ctl.scala 444:87] + node _T_14244 = or(_T_14235, _T_14243) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][11][4] <= _T_14244 @[ifu_bp_ctl.scala 443:27] + node _T_14245 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14246 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14247 = eq(_T_14246, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_14248 = and(_T_14245, _T_14247) @[ifu_bp_ctl.scala 443:45] + node _T_14249 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14250 = eq(_T_14249, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_14251 = or(_T_14250, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14252 = and(_T_14248, _T_14251) @[ifu_bp_ctl.scala 443:110] + node _T_14253 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14254 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14255 = eq(_T_14254, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_14256 = and(_T_14253, _T_14255) @[ifu_bp_ctl.scala 444:22] + node _T_14257 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14258 = eq(_T_14257, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_14259 = or(_T_14258, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14260 = and(_T_14256, _T_14259) @[ifu_bp_ctl.scala 444:87] + node _T_14261 = or(_T_14252, _T_14260) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][11][5] <= _T_14261 @[ifu_bp_ctl.scala 443:27] + node _T_14262 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14263 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14264 = eq(_T_14263, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_14265 = and(_T_14262, _T_14264) @[ifu_bp_ctl.scala 443:45] + node _T_14266 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14267 = eq(_T_14266, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_14268 = or(_T_14267, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14269 = and(_T_14265, _T_14268) @[ifu_bp_ctl.scala 443:110] + node _T_14270 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14271 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14272 = eq(_T_14271, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_14273 = and(_T_14270, _T_14272) @[ifu_bp_ctl.scala 444:22] + node _T_14274 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14275 = eq(_T_14274, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_14276 = or(_T_14275, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14277 = and(_T_14273, _T_14276) @[ifu_bp_ctl.scala 444:87] + node _T_14278 = or(_T_14269, _T_14277) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][11][6] <= _T_14278 @[ifu_bp_ctl.scala 443:27] + node _T_14279 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14280 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14281 = eq(_T_14280, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_14282 = and(_T_14279, _T_14281) @[ifu_bp_ctl.scala 443:45] + node _T_14283 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14284 = eq(_T_14283, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_14285 = or(_T_14284, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14286 = and(_T_14282, _T_14285) @[ifu_bp_ctl.scala 443:110] + node _T_14287 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14288 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14289 = eq(_T_14288, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_14290 = and(_T_14287, _T_14289) @[ifu_bp_ctl.scala 444:22] + node _T_14291 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14292 = eq(_T_14291, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_14293 = or(_T_14292, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14294 = and(_T_14290, _T_14293) @[ifu_bp_ctl.scala 444:87] + node _T_14295 = or(_T_14286, _T_14294) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][11][7] <= _T_14295 @[ifu_bp_ctl.scala 443:27] + node _T_14296 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14297 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14298 = eq(_T_14297, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_14299 = and(_T_14296, _T_14298) @[ifu_bp_ctl.scala 443:45] + node _T_14300 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14301 = eq(_T_14300, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_14302 = or(_T_14301, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14303 = and(_T_14299, _T_14302) @[ifu_bp_ctl.scala 443:110] + node _T_14304 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14305 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14306 = eq(_T_14305, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_14307 = and(_T_14304, _T_14306) @[ifu_bp_ctl.scala 444:22] + node _T_14308 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14309 = eq(_T_14308, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_14310 = or(_T_14309, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14311 = and(_T_14307, _T_14310) @[ifu_bp_ctl.scala 444:87] + node _T_14312 = or(_T_14303, _T_14311) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][11][8] <= _T_14312 @[ifu_bp_ctl.scala 443:27] + node _T_14313 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14314 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14315 = eq(_T_14314, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_14316 = and(_T_14313, _T_14315) @[ifu_bp_ctl.scala 443:45] + node _T_14317 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14318 = eq(_T_14317, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_14319 = or(_T_14318, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14320 = and(_T_14316, _T_14319) @[ifu_bp_ctl.scala 443:110] + node _T_14321 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14322 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14323 = eq(_T_14322, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_14324 = and(_T_14321, _T_14323) @[ifu_bp_ctl.scala 444:22] + node _T_14325 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14326 = eq(_T_14325, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_14327 = or(_T_14326, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14328 = and(_T_14324, _T_14327) @[ifu_bp_ctl.scala 444:87] + node _T_14329 = or(_T_14320, _T_14328) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][11][9] <= _T_14329 @[ifu_bp_ctl.scala 443:27] + node _T_14330 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14331 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14332 = eq(_T_14331, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_14333 = and(_T_14330, _T_14332) @[ifu_bp_ctl.scala 443:45] + node _T_14334 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14335 = eq(_T_14334, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_14336 = or(_T_14335, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14337 = and(_T_14333, _T_14336) @[ifu_bp_ctl.scala 443:110] + node _T_14338 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14339 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14340 = eq(_T_14339, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_14341 = and(_T_14338, _T_14340) @[ifu_bp_ctl.scala 444:22] + node _T_14342 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14343 = eq(_T_14342, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_14344 = or(_T_14343, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14345 = and(_T_14341, _T_14344) @[ifu_bp_ctl.scala 444:87] + node _T_14346 = or(_T_14337, _T_14345) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][11][10] <= _T_14346 @[ifu_bp_ctl.scala 443:27] + node _T_14347 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14348 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14349 = eq(_T_14348, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_14350 = and(_T_14347, _T_14349) @[ifu_bp_ctl.scala 443:45] + node _T_14351 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14352 = eq(_T_14351, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_14353 = or(_T_14352, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14354 = and(_T_14350, _T_14353) @[ifu_bp_ctl.scala 443:110] + node _T_14355 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14356 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14357 = eq(_T_14356, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_14358 = and(_T_14355, _T_14357) @[ifu_bp_ctl.scala 444:22] + node _T_14359 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14360 = eq(_T_14359, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_14361 = or(_T_14360, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14362 = and(_T_14358, _T_14361) @[ifu_bp_ctl.scala 444:87] + node _T_14363 = or(_T_14354, _T_14362) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][11][11] <= _T_14363 @[ifu_bp_ctl.scala 443:27] + node _T_14364 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14365 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14366 = eq(_T_14365, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_14367 = and(_T_14364, _T_14366) @[ifu_bp_ctl.scala 443:45] + node _T_14368 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14369 = eq(_T_14368, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_14370 = or(_T_14369, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14371 = and(_T_14367, _T_14370) @[ifu_bp_ctl.scala 443:110] + node _T_14372 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14373 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14374 = eq(_T_14373, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_14375 = and(_T_14372, _T_14374) @[ifu_bp_ctl.scala 444:22] + node _T_14376 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14377 = eq(_T_14376, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_14378 = or(_T_14377, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14379 = and(_T_14375, _T_14378) @[ifu_bp_ctl.scala 444:87] + node _T_14380 = or(_T_14371, _T_14379) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][11][12] <= _T_14380 @[ifu_bp_ctl.scala 443:27] + node _T_14381 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14382 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14383 = eq(_T_14382, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_14384 = and(_T_14381, _T_14383) @[ifu_bp_ctl.scala 443:45] + node _T_14385 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14386 = eq(_T_14385, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_14387 = or(_T_14386, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14388 = and(_T_14384, _T_14387) @[ifu_bp_ctl.scala 443:110] + node _T_14389 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14390 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14391 = eq(_T_14390, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_14392 = and(_T_14389, _T_14391) @[ifu_bp_ctl.scala 444:22] + node _T_14393 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14394 = eq(_T_14393, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_14395 = or(_T_14394, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14396 = and(_T_14392, _T_14395) @[ifu_bp_ctl.scala 444:87] + node _T_14397 = or(_T_14388, _T_14396) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][11][13] <= _T_14397 @[ifu_bp_ctl.scala 443:27] + node _T_14398 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14399 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14400 = eq(_T_14399, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_14401 = and(_T_14398, _T_14400) @[ifu_bp_ctl.scala 443:45] + node _T_14402 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14403 = eq(_T_14402, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_14404 = or(_T_14403, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14405 = and(_T_14401, _T_14404) @[ifu_bp_ctl.scala 443:110] + node _T_14406 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14407 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14408 = eq(_T_14407, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_14409 = and(_T_14406, _T_14408) @[ifu_bp_ctl.scala 444:22] + node _T_14410 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14411 = eq(_T_14410, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_14412 = or(_T_14411, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14413 = and(_T_14409, _T_14412) @[ifu_bp_ctl.scala 444:87] + node _T_14414 = or(_T_14405, _T_14413) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][11][14] <= _T_14414 @[ifu_bp_ctl.scala 443:27] + node _T_14415 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14416 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14417 = eq(_T_14416, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_14418 = and(_T_14415, _T_14417) @[ifu_bp_ctl.scala 443:45] + node _T_14419 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14420 = eq(_T_14419, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_14421 = or(_T_14420, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14422 = and(_T_14418, _T_14421) @[ifu_bp_ctl.scala 443:110] + node _T_14423 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14424 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14425 = eq(_T_14424, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_14426 = and(_T_14423, _T_14425) @[ifu_bp_ctl.scala 444:22] + node _T_14427 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14428 = eq(_T_14427, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_14429 = or(_T_14428, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14430 = and(_T_14426, _T_14429) @[ifu_bp_ctl.scala 444:87] + node _T_14431 = or(_T_14422, _T_14430) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][11][15] <= _T_14431 @[ifu_bp_ctl.scala 443:27] + node _T_14432 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14433 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14434 = eq(_T_14433, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_14435 = and(_T_14432, _T_14434) @[ifu_bp_ctl.scala 443:45] + node _T_14436 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14437 = eq(_T_14436, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_14438 = or(_T_14437, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14439 = and(_T_14435, _T_14438) @[ifu_bp_ctl.scala 443:110] + node _T_14440 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14441 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14442 = eq(_T_14441, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_14443 = and(_T_14440, _T_14442) @[ifu_bp_ctl.scala 444:22] + node _T_14444 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14445 = eq(_T_14444, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_14446 = or(_T_14445, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14447 = and(_T_14443, _T_14446) @[ifu_bp_ctl.scala 444:87] + node _T_14448 = or(_T_14439, _T_14447) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][12][0] <= _T_14448 @[ifu_bp_ctl.scala 443:27] + node _T_14449 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14450 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14451 = eq(_T_14450, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_14452 = and(_T_14449, _T_14451) @[ifu_bp_ctl.scala 443:45] + node _T_14453 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14454 = eq(_T_14453, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_14455 = or(_T_14454, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14456 = and(_T_14452, _T_14455) @[ifu_bp_ctl.scala 443:110] + node _T_14457 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14458 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14459 = eq(_T_14458, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_14460 = and(_T_14457, _T_14459) @[ifu_bp_ctl.scala 444:22] + node _T_14461 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14462 = eq(_T_14461, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_14463 = or(_T_14462, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14464 = and(_T_14460, _T_14463) @[ifu_bp_ctl.scala 444:87] + node _T_14465 = or(_T_14456, _T_14464) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][12][1] <= _T_14465 @[ifu_bp_ctl.scala 443:27] + node _T_14466 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14467 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14468 = eq(_T_14467, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_14469 = and(_T_14466, _T_14468) @[ifu_bp_ctl.scala 443:45] + node _T_14470 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14471 = eq(_T_14470, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_14472 = or(_T_14471, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14473 = and(_T_14469, _T_14472) @[ifu_bp_ctl.scala 443:110] + node _T_14474 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14475 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14476 = eq(_T_14475, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_14477 = and(_T_14474, _T_14476) @[ifu_bp_ctl.scala 444:22] + node _T_14478 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14479 = eq(_T_14478, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_14480 = or(_T_14479, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14481 = and(_T_14477, _T_14480) @[ifu_bp_ctl.scala 444:87] + node _T_14482 = or(_T_14473, _T_14481) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][12][2] <= _T_14482 @[ifu_bp_ctl.scala 443:27] + node _T_14483 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14484 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14485 = eq(_T_14484, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_14486 = and(_T_14483, _T_14485) @[ifu_bp_ctl.scala 443:45] + node _T_14487 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14488 = eq(_T_14487, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_14489 = or(_T_14488, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14490 = and(_T_14486, _T_14489) @[ifu_bp_ctl.scala 443:110] + node _T_14491 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14492 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14493 = eq(_T_14492, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_14494 = and(_T_14491, _T_14493) @[ifu_bp_ctl.scala 444:22] + node _T_14495 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14496 = eq(_T_14495, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_14497 = or(_T_14496, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14498 = and(_T_14494, _T_14497) @[ifu_bp_ctl.scala 444:87] + node _T_14499 = or(_T_14490, _T_14498) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][12][3] <= _T_14499 @[ifu_bp_ctl.scala 443:27] + node _T_14500 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14501 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14502 = eq(_T_14501, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_14503 = and(_T_14500, _T_14502) @[ifu_bp_ctl.scala 443:45] + node _T_14504 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14505 = eq(_T_14504, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_14506 = or(_T_14505, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14507 = and(_T_14503, _T_14506) @[ifu_bp_ctl.scala 443:110] + node _T_14508 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14509 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14510 = eq(_T_14509, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_14511 = and(_T_14508, _T_14510) @[ifu_bp_ctl.scala 444:22] + node _T_14512 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14513 = eq(_T_14512, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_14514 = or(_T_14513, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14515 = and(_T_14511, _T_14514) @[ifu_bp_ctl.scala 444:87] + node _T_14516 = or(_T_14507, _T_14515) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][12][4] <= _T_14516 @[ifu_bp_ctl.scala 443:27] + node _T_14517 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14518 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14519 = eq(_T_14518, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_14520 = and(_T_14517, _T_14519) @[ifu_bp_ctl.scala 443:45] + node _T_14521 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14522 = eq(_T_14521, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_14523 = or(_T_14522, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14524 = and(_T_14520, _T_14523) @[ifu_bp_ctl.scala 443:110] + node _T_14525 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14526 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14527 = eq(_T_14526, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_14528 = and(_T_14525, _T_14527) @[ifu_bp_ctl.scala 444:22] + node _T_14529 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14530 = eq(_T_14529, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_14531 = or(_T_14530, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14532 = and(_T_14528, _T_14531) @[ifu_bp_ctl.scala 444:87] + node _T_14533 = or(_T_14524, _T_14532) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][12][5] <= _T_14533 @[ifu_bp_ctl.scala 443:27] + node _T_14534 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14535 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14536 = eq(_T_14535, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_14537 = and(_T_14534, _T_14536) @[ifu_bp_ctl.scala 443:45] + node _T_14538 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14539 = eq(_T_14538, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_14540 = or(_T_14539, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14541 = and(_T_14537, _T_14540) @[ifu_bp_ctl.scala 443:110] + node _T_14542 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14543 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14544 = eq(_T_14543, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_14545 = and(_T_14542, _T_14544) @[ifu_bp_ctl.scala 444:22] + node _T_14546 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14547 = eq(_T_14546, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_14548 = or(_T_14547, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14549 = and(_T_14545, _T_14548) @[ifu_bp_ctl.scala 444:87] + node _T_14550 = or(_T_14541, _T_14549) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][12][6] <= _T_14550 @[ifu_bp_ctl.scala 443:27] + node _T_14551 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14552 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14553 = eq(_T_14552, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_14554 = and(_T_14551, _T_14553) @[ifu_bp_ctl.scala 443:45] + node _T_14555 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14556 = eq(_T_14555, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_14557 = or(_T_14556, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14558 = and(_T_14554, _T_14557) @[ifu_bp_ctl.scala 443:110] + node _T_14559 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14560 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14561 = eq(_T_14560, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_14562 = and(_T_14559, _T_14561) @[ifu_bp_ctl.scala 444:22] + node _T_14563 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14564 = eq(_T_14563, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_14565 = or(_T_14564, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14566 = and(_T_14562, _T_14565) @[ifu_bp_ctl.scala 444:87] + node _T_14567 = or(_T_14558, _T_14566) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][12][7] <= _T_14567 @[ifu_bp_ctl.scala 443:27] + node _T_14568 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14569 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14570 = eq(_T_14569, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_14571 = and(_T_14568, _T_14570) @[ifu_bp_ctl.scala 443:45] + node _T_14572 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14573 = eq(_T_14572, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_14574 = or(_T_14573, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14575 = and(_T_14571, _T_14574) @[ifu_bp_ctl.scala 443:110] + node _T_14576 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14577 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14578 = eq(_T_14577, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_14579 = and(_T_14576, _T_14578) @[ifu_bp_ctl.scala 444:22] + node _T_14580 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14581 = eq(_T_14580, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_14582 = or(_T_14581, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14583 = and(_T_14579, _T_14582) @[ifu_bp_ctl.scala 444:87] + node _T_14584 = or(_T_14575, _T_14583) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][12][8] <= _T_14584 @[ifu_bp_ctl.scala 443:27] + node _T_14585 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14586 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14587 = eq(_T_14586, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_14588 = and(_T_14585, _T_14587) @[ifu_bp_ctl.scala 443:45] + node _T_14589 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14590 = eq(_T_14589, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_14591 = or(_T_14590, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14592 = and(_T_14588, _T_14591) @[ifu_bp_ctl.scala 443:110] + node _T_14593 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14594 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14595 = eq(_T_14594, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_14596 = and(_T_14593, _T_14595) @[ifu_bp_ctl.scala 444:22] + node _T_14597 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14598 = eq(_T_14597, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_14599 = or(_T_14598, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14600 = and(_T_14596, _T_14599) @[ifu_bp_ctl.scala 444:87] + node _T_14601 = or(_T_14592, _T_14600) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][12][9] <= _T_14601 @[ifu_bp_ctl.scala 443:27] + node _T_14602 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14603 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14604 = eq(_T_14603, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_14605 = and(_T_14602, _T_14604) @[ifu_bp_ctl.scala 443:45] + node _T_14606 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14607 = eq(_T_14606, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_14608 = or(_T_14607, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14609 = and(_T_14605, _T_14608) @[ifu_bp_ctl.scala 443:110] + node _T_14610 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14611 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14612 = eq(_T_14611, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_14613 = and(_T_14610, _T_14612) @[ifu_bp_ctl.scala 444:22] + node _T_14614 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14615 = eq(_T_14614, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_14616 = or(_T_14615, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14617 = and(_T_14613, _T_14616) @[ifu_bp_ctl.scala 444:87] + node _T_14618 = or(_T_14609, _T_14617) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][12][10] <= _T_14618 @[ifu_bp_ctl.scala 443:27] + node _T_14619 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14620 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14621 = eq(_T_14620, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_14622 = and(_T_14619, _T_14621) @[ifu_bp_ctl.scala 443:45] + node _T_14623 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14624 = eq(_T_14623, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_14625 = or(_T_14624, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14626 = and(_T_14622, _T_14625) @[ifu_bp_ctl.scala 443:110] + node _T_14627 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14628 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14629 = eq(_T_14628, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_14630 = and(_T_14627, _T_14629) @[ifu_bp_ctl.scala 444:22] + node _T_14631 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14632 = eq(_T_14631, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_14633 = or(_T_14632, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14634 = and(_T_14630, _T_14633) @[ifu_bp_ctl.scala 444:87] + node _T_14635 = or(_T_14626, _T_14634) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][12][11] <= _T_14635 @[ifu_bp_ctl.scala 443:27] + node _T_14636 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14637 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14638 = eq(_T_14637, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_14639 = and(_T_14636, _T_14638) @[ifu_bp_ctl.scala 443:45] + node _T_14640 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14641 = eq(_T_14640, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_14642 = or(_T_14641, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14643 = and(_T_14639, _T_14642) @[ifu_bp_ctl.scala 443:110] + node _T_14644 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14645 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14646 = eq(_T_14645, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_14647 = and(_T_14644, _T_14646) @[ifu_bp_ctl.scala 444:22] + node _T_14648 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14649 = eq(_T_14648, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_14650 = or(_T_14649, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14651 = and(_T_14647, _T_14650) @[ifu_bp_ctl.scala 444:87] + node _T_14652 = or(_T_14643, _T_14651) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][12][12] <= _T_14652 @[ifu_bp_ctl.scala 443:27] + node _T_14653 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14654 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14655 = eq(_T_14654, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_14656 = and(_T_14653, _T_14655) @[ifu_bp_ctl.scala 443:45] + node _T_14657 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14658 = eq(_T_14657, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_14659 = or(_T_14658, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14660 = and(_T_14656, _T_14659) @[ifu_bp_ctl.scala 443:110] + node _T_14661 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14662 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14663 = eq(_T_14662, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_14664 = and(_T_14661, _T_14663) @[ifu_bp_ctl.scala 444:22] + node _T_14665 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14666 = eq(_T_14665, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_14667 = or(_T_14666, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14668 = and(_T_14664, _T_14667) @[ifu_bp_ctl.scala 444:87] + node _T_14669 = or(_T_14660, _T_14668) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][12][13] <= _T_14669 @[ifu_bp_ctl.scala 443:27] + node _T_14670 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14671 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14672 = eq(_T_14671, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_14673 = and(_T_14670, _T_14672) @[ifu_bp_ctl.scala 443:45] + node _T_14674 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14675 = eq(_T_14674, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_14676 = or(_T_14675, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14677 = and(_T_14673, _T_14676) @[ifu_bp_ctl.scala 443:110] + node _T_14678 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14679 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14680 = eq(_T_14679, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_14681 = and(_T_14678, _T_14680) @[ifu_bp_ctl.scala 444:22] + node _T_14682 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14683 = eq(_T_14682, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_14684 = or(_T_14683, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14685 = and(_T_14681, _T_14684) @[ifu_bp_ctl.scala 444:87] + node _T_14686 = or(_T_14677, _T_14685) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][12][14] <= _T_14686 @[ifu_bp_ctl.scala 443:27] + node _T_14687 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14688 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14689 = eq(_T_14688, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_14690 = and(_T_14687, _T_14689) @[ifu_bp_ctl.scala 443:45] + node _T_14691 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14692 = eq(_T_14691, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_14693 = or(_T_14692, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14694 = and(_T_14690, _T_14693) @[ifu_bp_ctl.scala 443:110] + node _T_14695 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14696 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14697 = eq(_T_14696, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_14698 = and(_T_14695, _T_14697) @[ifu_bp_ctl.scala 444:22] + node _T_14699 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14700 = eq(_T_14699, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_14701 = or(_T_14700, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14702 = and(_T_14698, _T_14701) @[ifu_bp_ctl.scala 444:87] + node _T_14703 = or(_T_14694, _T_14702) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][12][15] <= _T_14703 @[ifu_bp_ctl.scala 443:27] + node _T_14704 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14705 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14706 = eq(_T_14705, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_14707 = and(_T_14704, _T_14706) @[ifu_bp_ctl.scala 443:45] + node _T_14708 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14709 = eq(_T_14708, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_14710 = or(_T_14709, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14711 = and(_T_14707, _T_14710) @[ifu_bp_ctl.scala 443:110] + node _T_14712 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14713 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14714 = eq(_T_14713, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_14715 = and(_T_14712, _T_14714) @[ifu_bp_ctl.scala 444:22] + node _T_14716 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14717 = eq(_T_14716, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_14718 = or(_T_14717, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14719 = and(_T_14715, _T_14718) @[ifu_bp_ctl.scala 444:87] + node _T_14720 = or(_T_14711, _T_14719) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][13][0] <= _T_14720 @[ifu_bp_ctl.scala 443:27] + node _T_14721 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14722 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14723 = eq(_T_14722, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_14724 = and(_T_14721, _T_14723) @[ifu_bp_ctl.scala 443:45] + node _T_14725 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14726 = eq(_T_14725, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_14727 = or(_T_14726, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14728 = and(_T_14724, _T_14727) @[ifu_bp_ctl.scala 443:110] + node _T_14729 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14730 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14731 = eq(_T_14730, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_14732 = and(_T_14729, _T_14731) @[ifu_bp_ctl.scala 444:22] + node _T_14733 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14734 = eq(_T_14733, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_14735 = or(_T_14734, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14736 = and(_T_14732, _T_14735) @[ifu_bp_ctl.scala 444:87] + node _T_14737 = or(_T_14728, _T_14736) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][13][1] <= _T_14737 @[ifu_bp_ctl.scala 443:27] + node _T_14738 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14739 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14740 = eq(_T_14739, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_14741 = and(_T_14738, _T_14740) @[ifu_bp_ctl.scala 443:45] + node _T_14742 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14743 = eq(_T_14742, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_14744 = or(_T_14743, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14745 = and(_T_14741, _T_14744) @[ifu_bp_ctl.scala 443:110] + node _T_14746 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14747 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14748 = eq(_T_14747, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_14749 = and(_T_14746, _T_14748) @[ifu_bp_ctl.scala 444:22] + node _T_14750 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14751 = eq(_T_14750, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_14752 = or(_T_14751, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14753 = and(_T_14749, _T_14752) @[ifu_bp_ctl.scala 444:87] + node _T_14754 = or(_T_14745, _T_14753) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][13][2] <= _T_14754 @[ifu_bp_ctl.scala 443:27] + node _T_14755 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14756 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14757 = eq(_T_14756, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_14758 = and(_T_14755, _T_14757) @[ifu_bp_ctl.scala 443:45] + node _T_14759 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14760 = eq(_T_14759, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_14761 = or(_T_14760, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14762 = and(_T_14758, _T_14761) @[ifu_bp_ctl.scala 443:110] + node _T_14763 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14764 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14765 = eq(_T_14764, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_14766 = and(_T_14763, _T_14765) @[ifu_bp_ctl.scala 444:22] + node _T_14767 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14768 = eq(_T_14767, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_14769 = or(_T_14768, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14770 = and(_T_14766, _T_14769) @[ifu_bp_ctl.scala 444:87] + node _T_14771 = or(_T_14762, _T_14770) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][13][3] <= _T_14771 @[ifu_bp_ctl.scala 443:27] + node _T_14772 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14773 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14774 = eq(_T_14773, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_14775 = and(_T_14772, _T_14774) @[ifu_bp_ctl.scala 443:45] + node _T_14776 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14777 = eq(_T_14776, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_14778 = or(_T_14777, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14779 = and(_T_14775, _T_14778) @[ifu_bp_ctl.scala 443:110] + node _T_14780 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14781 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14782 = eq(_T_14781, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_14783 = and(_T_14780, _T_14782) @[ifu_bp_ctl.scala 444:22] + node _T_14784 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14785 = eq(_T_14784, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_14786 = or(_T_14785, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14787 = and(_T_14783, _T_14786) @[ifu_bp_ctl.scala 444:87] + node _T_14788 = or(_T_14779, _T_14787) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][13][4] <= _T_14788 @[ifu_bp_ctl.scala 443:27] + node _T_14789 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14790 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14791 = eq(_T_14790, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_14792 = and(_T_14789, _T_14791) @[ifu_bp_ctl.scala 443:45] + node _T_14793 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14794 = eq(_T_14793, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_14795 = or(_T_14794, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14796 = and(_T_14792, _T_14795) @[ifu_bp_ctl.scala 443:110] + node _T_14797 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14798 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14799 = eq(_T_14798, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_14800 = and(_T_14797, _T_14799) @[ifu_bp_ctl.scala 444:22] + node _T_14801 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14802 = eq(_T_14801, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_14803 = or(_T_14802, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14804 = and(_T_14800, _T_14803) @[ifu_bp_ctl.scala 444:87] + node _T_14805 = or(_T_14796, _T_14804) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][13][5] <= _T_14805 @[ifu_bp_ctl.scala 443:27] + node _T_14806 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14807 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14808 = eq(_T_14807, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_14809 = and(_T_14806, _T_14808) @[ifu_bp_ctl.scala 443:45] + node _T_14810 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14811 = eq(_T_14810, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_14812 = or(_T_14811, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14813 = and(_T_14809, _T_14812) @[ifu_bp_ctl.scala 443:110] + node _T_14814 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14815 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14816 = eq(_T_14815, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_14817 = and(_T_14814, _T_14816) @[ifu_bp_ctl.scala 444:22] + node _T_14818 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14819 = eq(_T_14818, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_14820 = or(_T_14819, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14821 = and(_T_14817, _T_14820) @[ifu_bp_ctl.scala 444:87] + node _T_14822 = or(_T_14813, _T_14821) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][13][6] <= _T_14822 @[ifu_bp_ctl.scala 443:27] + node _T_14823 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14824 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14825 = eq(_T_14824, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_14826 = and(_T_14823, _T_14825) @[ifu_bp_ctl.scala 443:45] + node _T_14827 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14828 = eq(_T_14827, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_14829 = or(_T_14828, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14830 = and(_T_14826, _T_14829) @[ifu_bp_ctl.scala 443:110] + node _T_14831 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14832 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14833 = eq(_T_14832, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_14834 = and(_T_14831, _T_14833) @[ifu_bp_ctl.scala 444:22] + node _T_14835 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14836 = eq(_T_14835, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_14837 = or(_T_14836, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14838 = and(_T_14834, _T_14837) @[ifu_bp_ctl.scala 444:87] + node _T_14839 = or(_T_14830, _T_14838) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][13][7] <= _T_14839 @[ifu_bp_ctl.scala 443:27] + node _T_14840 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14841 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14842 = eq(_T_14841, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_14843 = and(_T_14840, _T_14842) @[ifu_bp_ctl.scala 443:45] + node _T_14844 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14845 = eq(_T_14844, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_14846 = or(_T_14845, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14847 = and(_T_14843, _T_14846) @[ifu_bp_ctl.scala 443:110] + node _T_14848 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14849 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14850 = eq(_T_14849, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_14851 = and(_T_14848, _T_14850) @[ifu_bp_ctl.scala 444:22] + node _T_14852 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14853 = eq(_T_14852, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_14854 = or(_T_14853, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14855 = and(_T_14851, _T_14854) @[ifu_bp_ctl.scala 444:87] + node _T_14856 = or(_T_14847, _T_14855) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][13][8] <= _T_14856 @[ifu_bp_ctl.scala 443:27] + node _T_14857 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14858 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14859 = eq(_T_14858, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_14860 = and(_T_14857, _T_14859) @[ifu_bp_ctl.scala 443:45] + node _T_14861 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14862 = eq(_T_14861, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_14863 = or(_T_14862, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14864 = and(_T_14860, _T_14863) @[ifu_bp_ctl.scala 443:110] + node _T_14865 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14866 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14867 = eq(_T_14866, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_14868 = and(_T_14865, _T_14867) @[ifu_bp_ctl.scala 444:22] + node _T_14869 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14870 = eq(_T_14869, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_14871 = or(_T_14870, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14872 = and(_T_14868, _T_14871) @[ifu_bp_ctl.scala 444:87] + node _T_14873 = or(_T_14864, _T_14872) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][13][9] <= _T_14873 @[ifu_bp_ctl.scala 443:27] + node _T_14874 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14875 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14876 = eq(_T_14875, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_14877 = and(_T_14874, _T_14876) @[ifu_bp_ctl.scala 443:45] + node _T_14878 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14879 = eq(_T_14878, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_14880 = or(_T_14879, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14881 = and(_T_14877, _T_14880) @[ifu_bp_ctl.scala 443:110] + node _T_14882 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14883 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14884 = eq(_T_14883, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_14885 = and(_T_14882, _T_14884) @[ifu_bp_ctl.scala 444:22] + node _T_14886 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14887 = eq(_T_14886, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_14888 = or(_T_14887, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14889 = and(_T_14885, _T_14888) @[ifu_bp_ctl.scala 444:87] + node _T_14890 = or(_T_14881, _T_14889) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][13][10] <= _T_14890 @[ifu_bp_ctl.scala 443:27] + node _T_14891 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14892 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14893 = eq(_T_14892, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_14894 = and(_T_14891, _T_14893) @[ifu_bp_ctl.scala 443:45] + node _T_14895 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14896 = eq(_T_14895, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_14897 = or(_T_14896, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14898 = and(_T_14894, _T_14897) @[ifu_bp_ctl.scala 443:110] + node _T_14899 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14900 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14901 = eq(_T_14900, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_14902 = and(_T_14899, _T_14901) @[ifu_bp_ctl.scala 444:22] + node _T_14903 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14904 = eq(_T_14903, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_14905 = or(_T_14904, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14906 = and(_T_14902, _T_14905) @[ifu_bp_ctl.scala 444:87] + node _T_14907 = or(_T_14898, _T_14906) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][13][11] <= _T_14907 @[ifu_bp_ctl.scala 443:27] + node _T_14908 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14909 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14910 = eq(_T_14909, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_14911 = and(_T_14908, _T_14910) @[ifu_bp_ctl.scala 443:45] + node _T_14912 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14913 = eq(_T_14912, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_14914 = or(_T_14913, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14915 = and(_T_14911, _T_14914) @[ifu_bp_ctl.scala 443:110] + node _T_14916 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14917 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14918 = eq(_T_14917, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_14919 = and(_T_14916, _T_14918) @[ifu_bp_ctl.scala 444:22] + node _T_14920 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14921 = eq(_T_14920, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_14922 = or(_T_14921, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14923 = and(_T_14919, _T_14922) @[ifu_bp_ctl.scala 444:87] + node _T_14924 = or(_T_14915, _T_14923) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][13][12] <= _T_14924 @[ifu_bp_ctl.scala 443:27] + node _T_14925 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14926 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14927 = eq(_T_14926, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_14928 = and(_T_14925, _T_14927) @[ifu_bp_ctl.scala 443:45] + node _T_14929 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14930 = eq(_T_14929, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_14931 = or(_T_14930, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14932 = and(_T_14928, _T_14931) @[ifu_bp_ctl.scala 443:110] + node _T_14933 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14934 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14935 = eq(_T_14934, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_14936 = and(_T_14933, _T_14935) @[ifu_bp_ctl.scala 444:22] + node _T_14937 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14938 = eq(_T_14937, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_14939 = or(_T_14938, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14940 = and(_T_14936, _T_14939) @[ifu_bp_ctl.scala 444:87] + node _T_14941 = or(_T_14932, _T_14940) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][13][13] <= _T_14941 @[ifu_bp_ctl.scala 443:27] + node _T_14942 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14943 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14944 = eq(_T_14943, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_14945 = and(_T_14942, _T_14944) @[ifu_bp_ctl.scala 443:45] + node _T_14946 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14947 = eq(_T_14946, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_14948 = or(_T_14947, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14949 = and(_T_14945, _T_14948) @[ifu_bp_ctl.scala 443:110] + node _T_14950 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14951 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14952 = eq(_T_14951, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_14953 = and(_T_14950, _T_14952) @[ifu_bp_ctl.scala 444:22] + node _T_14954 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14955 = eq(_T_14954, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_14956 = or(_T_14955, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14957 = and(_T_14953, _T_14956) @[ifu_bp_ctl.scala 444:87] + node _T_14958 = or(_T_14949, _T_14957) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][13][14] <= _T_14958 @[ifu_bp_ctl.scala 443:27] + node _T_14959 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14960 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14961 = eq(_T_14960, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_14962 = and(_T_14959, _T_14961) @[ifu_bp_ctl.scala 443:45] + node _T_14963 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14964 = eq(_T_14963, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_14965 = or(_T_14964, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14966 = and(_T_14962, _T_14965) @[ifu_bp_ctl.scala 443:110] + node _T_14967 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14968 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14969 = eq(_T_14968, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_14970 = and(_T_14967, _T_14969) @[ifu_bp_ctl.scala 444:22] + node _T_14971 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14972 = eq(_T_14971, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_14973 = or(_T_14972, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14974 = and(_T_14970, _T_14973) @[ifu_bp_ctl.scala 444:87] + node _T_14975 = or(_T_14966, _T_14974) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][13][15] <= _T_14975 @[ifu_bp_ctl.scala 443:27] + node _T_14976 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14977 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14978 = eq(_T_14977, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_14979 = and(_T_14976, _T_14978) @[ifu_bp_ctl.scala 443:45] + node _T_14980 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14981 = eq(_T_14980, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_14982 = or(_T_14981, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_14983 = and(_T_14979, _T_14982) @[ifu_bp_ctl.scala 443:110] + node _T_14984 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_14985 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_14986 = eq(_T_14985, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_14987 = and(_T_14984, _T_14986) @[ifu_bp_ctl.scala 444:22] + node _T_14988 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_14989 = eq(_T_14988, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_14990 = or(_T_14989, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_14991 = and(_T_14987, _T_14990) @[ifu_bp_ctl.scala 444:87] + node _T_14992 = or(_T_14983, _T_14991) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][14][0] <= _T_14992 @[ifu_bp_ctl.scala 443:27] + node _T_14993 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_14994 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_14995 = eq(_T_14994, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_14996 = and(_T_14993, _T_14995) @[ifu_bp_ctl.scala 443:45] + node _T_14997 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_14998 = eq(_T_14997, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_14999 = or(_T_14998, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15000 = and(_T_14996, _T_14999) @[ifu_bp_ctl.scala 443:110] + node _T_15001 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15002 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15003 = eq(_T_15002, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_15004 = and(_T_15001, _T_15003) @[ifu_bp_ctl.scala 444:22] + node _T_15005 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15006 = eq(_T_15005, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_15007 = or(_T_15006, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15008 = and(_T_15004, _T_15007) @[ifu_bp_ctl.scala 444:87] + node _T_15009 = or(_T_15000, _T_15008) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][14][1] <= _T_15009 @[ifu_bp_ctl.scala 443:27] + node _T_15010 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15011 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15012 = eq(_T_15011, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_15013 = and(_T_15010, _T_15012) @[ifu_bp_ctl.scala 443:45] + node _T_15014 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15015 = eq(_T_15014, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_15016 = or(_T_15015, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15017 = and(_T_15013, _T_15016) @[ifu_bp_ctl.scala 443:110] + node _T_15018 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15019 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15020 = eq(_T_15019, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_15021 = and(_T_15018, _T_15020) @[ifu_bp_ctl.scala 444:22] + node _T_15022 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15023 = eq(_T_15022, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_15024 = or(_T_15023, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15025 = and(_T_15021, _T_15024) @[ifu_bp_ctl.scala 444:87] + node _T_15026 = or(_T_15017, _T_15025) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][14][2] <= _T_15026 @[ifu_bp_ctl.scala 443:27] + node _T_15027 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15028 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15029 = eq(_T_15028, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_15030 = and(_T_15027, _T_15029) @[ifu_bp_ctl.scala 443:45] + node _T_15031 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15032 = eq(_T_15031, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_15033 = or(_T_15032, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15034 = and(_T_15030, _T_15033) @[ifu_bp_ctl.scala 443:110] + node _T_15035 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15036 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15037 = eq(_T_15036, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_15038 = and(_T_15035, _T_15037) @[ifu_bp_ctl.scala 444:22] + node _T_15039 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15040 = eq(_T_15039, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_15041 = or(_T_15040, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15042 = and(_T_15038, _T_15041) @[ifu_bp_ctl.scala 444:87] + node _T_15043 = or(_T_15034, _T_15042) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][14][3] <= _T_15043 @[ifu_bp_ctl.scala 443:27] + node _T_15044 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15045 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15046 = eq(_T_15045, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_15047 = and(_T_15044, _T_15046) @[ifu_bp_ctl.scala 443:45] + node _T_15048 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15049 = eq(_T_15048, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_15050 = or(_T_15049, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15051 = and(_T_15047, _T_15050) @[ifu_bp_ctl.scala 443:110] + node _T_15052 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15053 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15054 = eq(_T_15053, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_15055 = and(_T_15052, _T_15054) @[ifu_bp_ctl.scala 444:22] + node _T_15056 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15057 = eq(_T_15056, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_15058 = or(_T_15057, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15059 = and(_T_15055, _T_15058) @[ifu_bp_ctl.scala 444:87] + node _T_15060 = or(_T_15051, _T_15059) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][14][4] <= _T_15060 @[ifu_bp_ctl.scala 443:27] + node _T_15061 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15062 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15063 = eq(_T_15062, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_15064 = and(_T_15061, _T_15063) @[ifu_bp_ctl.scala 443:45] + node _T_15065 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15066 = eq(_T_15065, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_15067 = or(_T_15066, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15068 = and(_T_15064, _T_15067) @[ifu_bp_ctl.scala 443:110] + node _T_15069 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15070 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15071 = eq(_T_15070, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_15072 = and(_T_15069, _T_15071) @[ifu_bp_ctl.scala 444:22] + node _T_15073 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15074 = eq(_T_15073, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_15075 = or(_T_15074, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15076 = and(_T_15072, _T_15075) @[ifu_bp_ctl.scala 444:87] + node _T_15077 = or(_T_15068, _T_15076) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][14][5] <= _T_15077 @[ifu_bp_ctl.scala 443:27] + node _T_15078 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15079 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15080 = eq(_T_15079, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_15081 = and(_T_15078, _T_15080) @[ifu_bp_ctl.scala 443:45] + node _T_15082 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15083 = eq(_T_15082, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_15084 = or(_T_15083, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15085 = and(_T_15081, _T_15084) @[ifu_bp_ctl.scala 443:110] + node _T_15086 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15087 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15088 = eq(_T_15087, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_15089 = and(_T_15086, _T_15088) @[ifu_bp_ctl.scala 444:22] + node _T_15090 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15091 = eq(_T_15090, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_15092 = or(_T_15091, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15093 = and(_T_15089, _T_15092) @[ifu_bp_ctl.scala 444:87] + node _T_15094 = or(_T_15085, _T_15093) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][14][6] <= _T_15094 @[ifu_bp_ctl.scala 443:27] + node _T_15095 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15096 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15097 = eq(_T_15096, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_15098 = and(_T_15095, _T_15097) @[ifu_bp_ctl.scala 443:45] + node _T_15099 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15100 = eq(_T_15099, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_15101 = or(_T_15100, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15102 = and(_T_15098, _T_15101) @[ifu_bp_ctl.scala 443:110] + node _T_15103 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15104 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15105 = eq(_T_15104, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_15106 = and(_T_15103, _T_15105) @[ifu_bp_ctl.scala 444:22] + node _T_15107 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15108 = eq(_T_15107, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_15109 = or(_T_15108, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15110 = and(_T_15106, _T_15109) @[ifu_bp_ctl.scala 444:87] + node _T_15111 = or(_T_15102, _T_15110) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][14][7] <= _T_15111 @[ifu_bp_ctl.scala 443:27] + node _T_15112 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15113 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15114 = eq(_T_15113, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_15115 = and(_T_15112, _T_15114) @[ifu_bp_ctl.scala 443:45] + node _T_15116 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15117 = eq(_T_15116, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_15118 = or(_T_15117, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15119 = and(_T_15115, _T_15118) @[ifu_bp_ctl.scala 443:110] + node _T_15120 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15121 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15122 = eq(_T_15121, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_15123 = and(_T_15120, _T_15122) @[ifu_bp_ctl.scala 444:22] + node _T_15124 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15125 = eq(_T_15124, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_15126 = or(_T_15125, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15127 = and(_T_15123, _T_15126) @[ifu_bp_ctl.scala 444:87] + node _T_15128 = or(_T_15119, _T_15127) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][14][8] <= _T_15128 @[ifu_bp_ctl.scala 443:27] + node _T_15129 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15130 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15131 = eq(_T_15130, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_15132 = and(_T_15129, _T_15131) @[ifu_bp_ctl.scala 443:45] + node _T_15133 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15134 = eq(_T_15133, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_15135 = or(_T_15134, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15136 = and(_T_15132, _T_15135) @[ifu_bp_ctl.scala 443:110] + node _T_15137 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15138 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15139 = eq(_T_15138, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_15140 = and(_T_15137, _T_15139) @[ifu_bp_ctl.scala 444:22] + node _T_15141 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15142 = eq(_T_15141, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_15143 = or(_T_15142, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15144 = and(_T_15140, _T_15143) @[ifu_bp_ctl.scala 444:87] + node _T_15145 = or(_T_15136, _T_15144) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][14][9] <= _T_15145 @[ifu_bp_ctl.scala 443:27] + node _T_15146 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15147 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15148 = eq(_T_15147, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_15149 = and(_T_15146, _T_15148) @[ifu_bp_ctl.scala 443:45] + node _T_15150 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15151 = eq(_T_15150, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_15152 = or(_T_15151, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15153 = and(_T_15149, _T_15152) @[ifu_bp_ctl.scala 443:110] + node _T_15154 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15155 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15156 = eq(_T_15155, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_15157 = and(_T_15154, _T_15156) @[ifu_bp_ctl.scala 444:22] + node _T_15158 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15159 = eq(_T_15158, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_15160 = or(_T_15159, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15161 = and(_T_15157, _T_15160) @[ifu_bp_ctl.scala 444:87] + node _T_15162 = or(_T_15153, _T_15161) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][14][10] <= _T_15162 @[ifu_bp_ctl.scala 443:27] + node _T_15163 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15164 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15165 = eq(_T_15164, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_15166 = and(_T_15163, _T_15165) @[ifu_bp_ctl.scala 443:45] + node _T_15167 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15168 = eq(_T_15167, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_15169 = or(_T_15168, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15170 = and(_T_15166, _T_15169) @[ifu_bp_ctl.scala 443:110] + node _T_15171 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15172 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15173 = eq(_T_15172, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_15174 = and(_T_15171, _T_15173) @[ifu_bp_ctl.scala 444:22] + node _T_15175 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15176 = eq(_T_15175, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_15177 = or(_T_15176, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15178 = and(_T_15174, _T_15177) @[ifu_bp_ctl.scala 444:87] + node _T_15179 = or(_T_15170, _T_15178) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][14][11] <= _T_15179 @[ifu_bp_ctl.scala 443:27] + node _T_15180 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15181 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15182 = eq(_T_15181, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_15183 = and(_T_15180, _T_15182) @[ifu_bp_ctl.scala 443:45] + node _T_15184 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15185 = eq(_T_15184, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_15186 = or(_T_15185, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15187 = and(_T_15183, _T_15186) @[ifu_bp_ctl.scala 443:110] + node _T_15188 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15189 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15190 = eq(_T_15189, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_15191 = and(_T_15188, _T_15190) @[ifu_bp_ctl.scala 444:22] + node _T_15192 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15193 = eq(_T_15192, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_15194 = or(_T_15193, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15195 = and(_T_15191, _T_15194) @[ifu_bp_ctl.scala 444:87] + node _T_15196 = or(_T_15187, _T_15195) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][14][12] <= _T_15196 @[ifu_bp_ctl.scala 443:27] + node _T_15197 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15198 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15199 = eq(_T_15198, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_15200 = and(_T_15197, _T_15199) @[ifu_bp_ctl.scala 443:45] + node _T_15201 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15202 = eq(_T_15201, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_15203 = or(_T_15202, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15204 = and(_T_15200, _T_15203) @[ifu_bp_ctl.scala 443:110] + node _T_15205 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15206 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15207 = eq(_T_15206, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_15208 = and(_T_15205, _T_15207) @[ifu_bp_ctl.scala 444:22] + node _T_15209 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15210 = eq(_T_15209, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_15211 = or(_T_15210, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15212 = and(_T_15208, _T_15211) @[ifu_bp_ctl.scala 444:87] + node _T_15213 = or(_T_15204, _T_15212) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][14][13] <= _T_15213 @[ifu_bp_ctl.scala 443:27] + node _T_15214 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15215 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15216 = eq(_T_15215, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_15217 = and(_T_15214, _T_15216) @[ifu_bp_ctl.scala 443:45] + node _T_15218 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15219 = eq(_T_15218, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_15220 = or(_T_15219, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15221 = and(_T_15217, _T_15220) @[ifu_bp_ctl.scala 443:110] + node _T_15222 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15223 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15224 = eq(_T_15223, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_15225 = and(_T_15222, _T_15224) @[ifu_bp_ctl.scala 444:22] + node _T_15226 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15227 = eq(_T_15226, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_15228 = or(_T_15227, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15229 = and(_T_15225, _T_15228) @[ifu_bp_ctl.scala 444:87] + node _T_15230 = or(_T_15221, _T_15229) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][14][14] <= _T_15230 @[ifu_bp_ctl.scala 443:27] + node _T_15231 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15232 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15233 = eq(_T_15232, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_15234 = and(_T_15231, _T_15233) @[ifu_bp_ctl.scala 443:45] + node _T_15235 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15236 = eq(_T_15235, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_15237 = or(_T_15236, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15238 = and(_T_15234, _T_15237) @[ifu_bp_ctl.scala 443:110] + node _T_15239 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15240 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15241 = eq(_T_15240, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_15242 = and(_T_15239, _T_15241) @[ifu_bp_ctl.scala 444:22] + node _T_15243 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15244 = eq(_T_15243, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_15245 = or(_T_15244, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15246 = and(_T_15242, _T_15245) @[ifu_bp_ctl.scala 444:87] + node _T_15247 = or(_T_15238, _T_15246) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][14][15] <= _T_15247 @[ifu_bp_ctl.scala 443:27] + node _T_15248 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15249 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15250 = eq(_T_15249, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_15251 = and(_T_15248, _T_15250) @[ifu_bp_ctl.scala 443:45] + node _T_15252 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15253 = eq(_T_15252, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_15254 = or(_T_15253, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15255 = and(_T_15251, _T_15254) @[ifu_bp_ctl.scala 443:110] + node _T_15256 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15257 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15258 = eq(_T_15257, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_15259 = and(_T_15256, _T_15258) @[ifu_bp_ctl.scala 444:22] + node _T_15260 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15261 = eq(_T_15260, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_15262 = or(_T_15261, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15263 = and(_T_15259, _T_15262) @[ifu_bp_ctl.scala 444:87] + node _T_15264 = or(_T_15255, _T_15263) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][15][0] <= _T_15264 @[ifu_bp_ctl.scala 443:27] + node _T_15265 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15266 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15267 = eq(_T_15266, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_15268 = and(_T_15265, _T_15267) @[ifu_bp_ctl.scala 443:45] + node _T_15269 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15270 = eq(_T_15269, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_15271 = or(_T_15270, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15272 = and(_T_15268, _T_15271) @[ifu_bp_ctl.scala 443:110] + node _T_15273 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15274 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15275 = eq(_T_15274, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_15276 = and(_T_15273, _T_15275) @[ifu_bp_ctl.scala 444:22] + node _T_15277 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15278 = eq(_T_15277, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_15279 = or(_T_15278, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15280 = and(_T_15276, _T_15279) @[ifu_bp_ctl.scala 444:87] + node _T_15281 = or(_T_15272, _T_15280) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][15][1] <= _T_15281 @[ifu_bp_ctl.scala 443:27] + node _T_15282 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15283 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15284 = eq(_T_15283, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_15285 = and(_T_15282, _T_15284) @[ifu_bp_ctl.scala 443:45] + node _T_15286 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15287 = eq(_T_15286, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_15288 = or(_T_15287, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15289 = and(_T_15285, _T_15288) @[ifu_bp_ctl.scala 443:110] + node _T_15290 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15291 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15292 = eq(_T_15291, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_15293 = and(_T_15290, _T_15292) @[ifu_bp_ctl.scala 444:22] + node _T_15294 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15295 = eq(_T_15294, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_15296 = or(_T_15295, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15297 = and(_T_15293, _T_15296) @[ifu_bp_ctl.scala 444:87] + node _T_15298 = or(_T_15289, _T_15297) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][15][2] <= _T_15298 @[ifu_bp_ctl.scala 443:27] + node _T_15299 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15300 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15301 = eq(_T_15300, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_15302 = and(_T_15299, _T_15301) @[ifu_bp_ctl.scala 443:45] + node _T_15303 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15304 = eq(_T_15303, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_15305 = or(_T_15304, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15306 = and(_T_15302, _T_15305) @[ifu_bp_ctl.scala 443:110] + node _T_15307 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15308 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15309 = eq(_T_15308, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_15310 = and(_T_15307, _T_15309) @[ifu_bp_ctl.scala 444:22] + node _T_15311 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15312 = eq(_T_15311, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_15313 = or(_T_15312, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15314 = and(_T_15310, _T_15313) @[ifu_bp_ctl.scala 444:87] + node _T_15315 = or(_T_15306, _T_15314) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][15][3] <= _T_15315 @[ifu_bp_ctl.scala 443:27] + node _T_15316 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15317 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15318 = eq(_T_15317, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_15319 = and(_T_15316, _T_15318) @[ifu_bp_ctl.scala 443:45] + node _T_15320 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15321 = eq(_T_15320, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_15322 = or(_T_15321, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15323 = and(_T_15319, _T_15322) @[ifu_bp_ctl.scala 443:110] + node _T_15324 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15325 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15326 = eq(_T_15325, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_15327 = and(_T_15324, _T_15326) @[ifu_bp_ctl.scala 444:22] + node _T_15328 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15329 = eq(_T_15328, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_15330 = or(_T_15329, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15331 = and(_T_15327, _T_15330) @[ifu_bp_ctl.scala 444:87] + node _T_15332 = or(_T_15323, _T_15331) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][15][4] <= _T_15332 @[ifu_bp_ctl.scala 443:27] + node _T_15333 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15334 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15335 = eq(_T_15334, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_15336 = and(_T_15333, _T_15335) @[ifu_bp_ctl.scala 443:45] + node _T_15337 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15338 = eq(_T_15337, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_15339 = or(_T_15338, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15340 = and(_T_15336, _T_15339) @[ifu_bp_ctl.scala 443:110] + node _T_15341 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15342 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15343 = eq(_T_15342, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_15344 = and(_T_15341, _T_15343) @[ifu_bp_ctl.scala 444:22] + node _T_15345 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15346 = eq(_T_15345, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_15347 = or(_T_15346, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15348 = and(_T_15344, _T_15347) @[ifu_bp_ctl.scala 444:87] + node _T_15349 = or(_T_15340, _T_15348) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][15][5] <= _T_15349 @[ifu_bp_ctl.scala 443:27] + node _T_15350 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15351 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15352 = eq(_T_15351, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_15353 = and(_T_15350, _T_15352) @[ifu_bp_ctl.scala 443:45] + node _T_15354 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15355 = eq(_T_15354, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_15356 = or(_T_15355, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15357 = and(_T_15353, _T_15356) @[ifu_bp_ctl.scala 443:110] + node _T_15358 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15359 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15360 = eq(_T_15359, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_15361 = and(_T_15358, _T_15360) @[ifu_bp_ctl.scala 444:22] + node _T_15362 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15363 = eq(_T_15362, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_15364 = or(_T_15363, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15365 = and(_T_15361, _T_15364) @[ifu_bp_ctl.scala 444:87] + node _T_15366 = or(_T_15357, _T_15365) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][15][6] <= _T_15366 @[ifu_bp_ctl.scala 443:27] + node _T_15367 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15368 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15369 = eq(_T_15368, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_15370 = and(_T_15367, _T_15369) @[ifu_bp_ctl.scala 443:45] + node _T_15371 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15372 = eq(_T_15371, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_15373 = or(_T_15372, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15374 = and(_T_15370, _T_15373) @[ifu_bp_ctl.scala 443:110] + node _T_15375 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15376 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15377 = eq(_T_15376, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_15378 = and(_T_15375, _T_15377) @[ifu_bp_ctl.scala 444:22] + node _T_15379 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15380 = eq(_T_15379, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_15381 = or(_T_15380, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15382 = and(_T_15378, _T_15381) @[ifu_bp_ctl.scala 444:87] + node _T_15383 = or(_T_15374, _T_15382) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][15][7] <= _T_15383 @[ifu_bp_ctl.scala 443:27] + node _T_15384 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15385 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15386 = eq(_T_15385, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_15387 = and(_T_15384, _T_15386) @[ifu_bp_ctl.scala 443:45] + node _T_15388 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15389 = eq(_T_15388, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_15390 = or(_T_15389, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15391 = and(_T_15387, _T_15390) @[ifu_bp_ctl.scala 443:110] + node _T_15392 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15393 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15394 = eq(_T_15393, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_15395 = and(_T_15392, _T_15394) @[ifu_bp_ctl.scala 444:22] + node _T_15396 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15397 = eq(_T_15396, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_15398 = or(_T_15397, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15399 = and(_T_15395, _T_15398) @[ifu_bp_ctl.scala 444:87] + node _T_15400 = or(_T_15391, _T_15399) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][15][8] <= _T_15400 @[ifu_bp_ctl.scala 443:27] + node _T_15401 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15402 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15403 = eq(_T_15402, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_15404 = and(_T_15401, _T_15403) @[ifu_bp_ctl.scala 443:45] + node _T_15405 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15406 = eq(_T_15405, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_15407 = or(_T_15406, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15408 = and(_T_15404, _T_15407) @[ifu_bp_ctl.scala 443:110] + node _T_15409 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15410 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15411 = eq(_T_15410, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_15412 = and(_T_15409, _T_15411) @[ifu_bp_ctl.scala 444:22] + node _T_15413 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15414 = eq(_T_15413, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_15415 = or(_T_15414, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15416 = and(_T_15412, _T_15415) @[ifu_bp_ctl.scala 444:87] + node _T_15417 = or(_T_15408, _T_15416) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][15][9] <= _T_15417 @[ifu_bp_ctl.scala 443:27] + node _T_15418 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15419 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15420 = eq(_T_15419, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_15421 = and(_T_15418, _T_15420) @[ifu_bp_ctl.scala 443:45] + node _T_15422 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15423 = eq(_T_15422, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_15424 = or(_T_15423, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15425 = and(_T_15421, _T_15424) @[ifu_bp_ctl.scala 443:110] + node _T_15426 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15427 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15428 = eq(_T_15427, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_15429 = and(_T_15426, _T_15428) @[ifu_bp_ctl.scala 444:22] + node _T_15430 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15431 = eq(_T_15430, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_15432 = or(_T_15431, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15433 = and(_T_15429, _T_15432) @[ifu_bp_ctl.scala 444:87] + node _T_15434 = or(_T_15425, _T_15433) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][15][10] <= _T_15434 @[ifu_bp_ctl.scala 443:27] + node _T_15435 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15436 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15437 = eq(_T_15436, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_15438 = and(_T_15435, _T_15437) @[ifu_bp_ctl.scala 443:45] + node _T_15439 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15440 = eq(_T_15439, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_15441 = or(_T_15440, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15442 = and(_T_15438, _T_15441) @[ifu_bp_ctl.scala 443:110] + node _T_15443 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15444 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15445 = eq(_T_15444, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_15446 = and(_T_15443, _T_15445) @[ifu_bp_ctl.scala 444:22] + node _T_15447 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15448 = eq(_T_15447, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_15449 = or(_T_15448, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15450 = and(_T_15446, _T_15449) @[ifu_bp_ctl.scala 444:87] + node _T_15451 = or(_T_15442, _T_15450) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][15][11] <= _T_15451 @[ifu_bp_ctl.scala 443:27] + node _T_15452 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15453 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15454 = eq(_T_15453, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_15455 = and(_T_15452, _T_15454) @[ifu_bp_ctl.scala 443:45] + node _T_15456 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15457 = eq(_T_15456, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_15458 = or(_T_15457, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15459 = and(_T_15455, _T_15458) @[ifu_bp_ctl.scala 443:110] + node _T_15460 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15461 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15462 = eq(_T_15461, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_15463 = and(_T_15460, _T_15462) @[ifu_bp_ctl.scala 444:22] + node _T_15464 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15465 = eq(_T_15464, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_15466 = or(_T_15465, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15467 = and(_T_15463, _T_15466) @[ifu_bp_ctl.scala 444:87] + node _T_15468 = or(_T_15459, _T_15467) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][15][12] <= _T_15468 @[ifu_bp_ctl.scala 443:27] + node _T_15469 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15470 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15471 = eq(_T_15470, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_15472 = and(_T_15469, _T_15471) @[ifu_bp_ctl.scala 443:45] + node _T_15473 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15474 = eq(_T_15473, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_15475 = or(_T_15474, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15476 = and(_T_15472, _T_15475) @[ifu_bp_ctl.scala 443:110] + node _T_15477 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15478 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15479 = eq(_T_15478, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_15480 = and(_T_15477, _T_15479) @[ifu_bp_ctl.scala 444:22] + node _T_15481 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15482 = eq(_T_15481, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_15483 = or(_T_15482, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15484 = and(_T_15480, _T_15483) @[ifu_bp_ctl.scala 444:87] + node _T_15485 = or(_T_15476, _T_15484) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][15][13] <= _T_15485 @[ifu_bp_ctl.scala 443:27] + node _T_15486 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15487 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15488 = eq(_T_15487, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_15489 = and(_T_15486, _T_15488) @[ifu_bp_ctl.scala 443:45] + node _T_15490 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15491 = eq(_T_15490, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_15492 = or(_T_15491, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15493 = and(_T_15489, _T_15492) @[ifu_bp_ctl.scala 443:110] + node _T_15494 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15495 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15496 = eq(_T_15495, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_15497 = and(_T_15494, _T_15496) @[ifu_bp_ctl.scala 444:22] + node _T_15498 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15499 = eq(_T_15498, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_15500 = or(_T_15499, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15501 = and(_T_15497, _T_15500) @[ifu_bp_ctl.scala 444:87] + node _T_15502 = or(_T_15493, _T_15501) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][15][14] <= _T_15502 @[ifu_bp_ctl.scala 443:27] + node _T_15503 = bits(bht_wr_en0, 0, 0) @[ifu_bp_ctl.scala 443:41] + node _T_15504 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15505 = eq(_T_15504, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_15506 = and(_T_15503, _T_15505) @[ifu_bp_ctl.scala 443:45] + node _T_15507 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15508 = eq(_T_15507, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_15509 = or(_T_15508, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15510 = and(_T_15506, _T_15509) @[ifu_bp_ctl.scala 443:110] + node _T_15511 = bits(bht_wr_en2, 0, 0) @[ifu_bp_ctl.scala 444:18] + node _T_15512 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15513 = eq(_T_15512, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_15514 = and(_T_15511, _T_15513) @[ifu_bp_ctl.scala 444:22] + node _T_15515 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15516 = eq(_T_15515, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_15517 = or(_T_15516, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15518 = and(_T_15514, _T_15517) @[ifu_bp_ctl.scala 444:87] + node _T_15519 = or(_T_15510, _T_15518) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[0][15][15] <= _T_15519 @[ifu_bp_ctl.scala 443:27] + node _T_15520 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15521 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15522 = eq(_T_15521, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_15523 = and(_T_15520, _T_15522) @[ifu_bp_ctl.scala 443:45] + node _T_15524 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15525 = eq(_T_15524, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_15526 = or(_T_15525, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15527 = and(_T_15523, _T_15526) @[ifu_bp_ctl.scala 443:110] + node _T_15528 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15529 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15530 = eq(_T_15529, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_15531 = and(_T_15528, _T_15530) @[ifu_bp_ctl.scala 444:22] + node _T_15532 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15533 = eq(_T_15532, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_15534 = or(_T_15533, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15535 = and(_T_15531, _T_15534) @[ifu_bp_ctl.scala 444:87] + node _T_15536 = or(_T_15527, _T_15535) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][0][0] <= _T_15536 @[ifu_bp_ctl.scala 443:27] + node _T_15537 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15538 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15539 = eq(_T_15538, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_15540 = and(_T_15537, _T_15539) @[ifu_bp_ctl.scala 443:45] + node _T_15541 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15542 = eq(_T_15541, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_15543 = or(_T_15542, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15544 = and(_T_15540, _T_15543) @[ifu_bp_ctl.scala 443:110] + node _T_15545 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15546 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15547 = eq(_T_15546, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_15548 = and(_T_15545, _T_15547) @[ifu_bp_ctl.scala 444:22] + node _T_15549 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15550 = eq(_T_15549, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_15551 = or(_T_15550, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15552 = and(_T_15548, _T_15551) @[ifu_bp_ctl.scala 444:87] + node _T_15553 = or(_T_15544, _T_15552) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][0][1] <= _T_15553 @[ifu_bp_ctl.scala 443:27] + node _T_15554 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15555 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15556 = eq(_T_15555, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_15557 = and(_T_15554, _T_15556) @[ifu_bp_ctl.scala 443:45] + node _T_15558 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15559 = eq(_T_15558, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_15560 = or(_T_15559, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15561 = and(_T_15557, _T_15560) @[ifu_bp_ctl.scala 443:110] + node _T_15562 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15563 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15564 = eq(_T_15563, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_15565 = and(_T_15562, _T_15564) @[ifu_bp_ctl.scala 444:22] + node _T_15566 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15567 = eq(_T_15566, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_15568 = or(_T_15567, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15569 = and(_T_15565, _T_15568) @[ifu_bp_ctl.scala 444:87] + node _T_15570 = or(_T_15561, _T_15569) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][0][2] <= _T_15570 @[ifu_bp_ctl.scala 443:27] + node _T_15571 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15572 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15573 = eq(_T_15572, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_15574 = and(_T_15571, _T_15573) @[ifu_bp_ctl.scala 443:45] + node _T_15575 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15576 = eq(_T_15575, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_15577 = or(_T_15576, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15578 = and(_T_15574, _T_15577) @[ifu_bp_ctl.scala 443:110] + node _T_15579 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15580 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15581 = eq(_T_15580, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_15582 = and(_T_15579, _T_15581) @[ifu_bp_ctl.scala 444:22] + node _T_15583 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15584 = eq(_T_15583, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_15585 = or(_T_15584, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15586 = and(_T_15582, _T_15585) @[ifu_bp_ctl.scala 444:87] + node _T_15587 = or(_T_15578, _T_15586) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][0][3] <= _T_15587 @[ifu_bp_ctl.scala 443:27] + node _T_15588 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15589 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15590 = eq(_T_15589, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_15591 = and(_T_15588, _T_15590) @[ifu_bp_ctl.scala 443:45] + node _T_15592 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15593 = eq(_T_15592, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_15594 = or(_T_15593, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15595 = and(_T_15591, _T_15594) @[ifu_bp_ctl.scala 443:110] + node _T_15596 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15597 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15598 = eq(_T_15597, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_15599 = and(_T_15596, _T_15598) @[ifu_bp_ctl.scala 444:22] + node _T_15600 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15601 = eq(_T_15600, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_15602 = or(_T_15601, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15603 = and(_T_15599, _T_15602) @[ifu_bp_ctl.scala 444:87] + node _T_15604 = or(_T_15595, _T_15603) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][0][4] <= _T_15604 @[ifu_bp_ctl.scala 443:27] + node _T_15605 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15606 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15607 = eq(_T_15606, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_15608 = and(_T_15605, _T_15607) @[ifu_bp_ctl.scala 443:45] + node _T_15609 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15610 = eq(_T_15609, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_15611 = or(_T_15610, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15612 = and(_T_15608, _T_15611) @[ifu_bp_ctl.scala 443:110] + node _T_15613 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15614 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15615 = eq(_T_15614, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_15616 = and(_T_15613, _T_15615) @[ifu_bp_ctl.scala 444:22] + node _T_15617 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15618 = eq(_T_15617, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_15619 = or(_T_15618, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15620 = and(_T_15616, _T_15619) @[ifu_bp_ctl.scala 444:87] + node _T_15621 = or(_T_15612, _T_15620) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][0][5] <= _T_15621 @[ifu_bp_ctl.scala 443:27] + node _T_15622 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15623 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15624 = eq(_T_15623, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_15625 = and(_T_15622, _T_15624) @[ifu_bp_ctl.scala 443:45] + node _T_15626 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15627 = eq(_T_15626, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_15628 = or(_T_15627, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15629 = and(_T_15625, _T_15628) @[ifu_bp_ctl.scala 443:110] + node _T_15630 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15631 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15632 = eq(_T_15631, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_15633 = and(_T_15630, _T_15632) @[ifu_bp_ctl.scala 444:22] + node _T_15634 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15635 = eq(_T_15634, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_15636 = or(_T_15635, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15637 = and(_T_15633, _T_15636) @[ifu_bp_ctl.scala 444:87] + node _T_15638 = or(_T_15629, _T_15637) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][0][6] <= _T_15638 @[ifu_bp_ctl.scala 443:27] + node _T_15639 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15640 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15641 = eq(_T_15640, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_15642 = and(_T_15639, _T_15641) @[ifu_bp_ctl.scala 443:45] + node _T_15643 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15644 = eq(_T_15643, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_15645 = or(_T_15644, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15646 = and(_T_15642, _T_15645) @[ifu_bp_ctl.scala 443:110] + node _T_15647 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15648 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15649 = eq(_T_15648, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_15650 = and(_T_15647, _T_15649) @[ifu_bp_ctl.scala 444:22] + node _T_15651 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15652 = eq(_T_15651, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_15653 = or(_T_15652, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15654 = and(_T_15650, _T_15653) @[ifu_bp_ctl.scala 444:87] + node _T_15655 = or(_T_15646, _T_15654) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][0][7] <= _T_15655 @[ifu_bp_ctl.scala 443:27] + node _T_15656 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15657 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15658 = eq(_T_15657, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_15659 = and(_T_15656, _T_15658) @[ifu_bp_ctl.scala 443:45] + node _T_15660 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15661 = eq(_T_15660, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_15662 = or(_T_15661, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15663 = and(_T_15659, _T_15662) @[ifu_bp_ctl.scala 443:110] + node _T_15664 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15665 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15666 = eq(_T_15665, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_15667 = and(_T_15664, _T_15666) @[ifu_bp_ctl.scala 444:22] + node _T_15668 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15669 = eq(_T_15668, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_15670 = or(_T_15669, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15671 = and(_T_15667, _T_15670) @[ifu_bp_ctl.scala 444:87] + node _T_15672 = or(_T_15663, _T_15671) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][0][8] <= _T_15672 @[ifu_bp_ctl.scala 443:27] + node _T_15673 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15674 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15675 = eq(_T_15674, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_15676 = and(_T_15673, _T_15675) @[ifu_bp_ctl.scala 443:45] + node _T_15677 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15678 = eq(_T_15677, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_15679 = or(_T_15678, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15680 = and(_T_15676, _T_15679) @[ifu_bp_ctl.scala 443:110] + node _T_15681 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15682 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15683 = eq(_T_15682, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_15684 = and(_T_15681, _T_15683) @[ifu_bp_ctl.scala 444:22] + node _T_15685 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15686 = eq(_T_15685, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_15687 = or(_T_15686, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15688 = and(_T_15684, _T_15687) @[ifu_bp_ctl.scala 444:87] + node _T_15689 = or(_T_15680, _T_15688) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][0][9] <= _T_15689 @[ifu_bp_ctl.scala 443:27] + node _T_15690 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15691 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15692 = eq(_T_15691, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_15693 = and(_T_15690, _T_15692) @[ifu_bp_ctl.scala 443:45] + node _T_15694 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15695 = eq(_T_15694, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_15696 = or(_T_15695, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15697 = and(_T_15693, _T_15696) @[ifu_bp_ctl.scala 443:110] + node _T_15698 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15699 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15700 = eq(_T_15699, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_15701 = and(_T_15698, _T_15700) @[ifu_bp_ctl.scala 444:22] + node _T_15702 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15703 = eq(_T_15702, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_15704 = or(_T_15703, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15705 = and(_T_15701, _T_15704) @[ifu_bp_ctl.scala 444:87] + node _T_15706 = or(_T_15697, _T_15705) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][0][10] <= _T_15706 @[ifu_bp_ctl.scala 443:27] + node _T_15707 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15708 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15709 = eq(_T_15708, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_15710 = and(_T_15707, _T_15709) @[ifu_bp_ctl.scala 443:45] + node _T_15711 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15712 = eq(_T_15711, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_15713 = or(_T_15712, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15714 = and(_T_15710, _T_15713) @[ifu_bp_ctl.scala 443:110] + node _T_15715 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15716 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15717 = eq(_T_15716, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_15718 = and(_T_15715, _T_15717) @[ifu_bp_ctl.scala 444:22] + node _T_15719 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15720 = eq(_T_15719, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_15721 = or(_T_15720, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15722 = and(_T_15718, _T_15721) @[ifu_bp_ctl.scala 444:87] + node _T_15723 = or(_T_15714, _T_15722) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][0][11] <= _T_15723 @[ifu_bp_ctl.scala 443:27] + node _T_15724 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15725 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15726 = eq(_T_15725, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_15727 = and(_T_15724, _T_15726) @[ifu_bp_ctl.scala 443:45] + node _T_15728 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15729 = eq(_T_15728, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_15730 = or(_T_15729, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15731 = and(_T_15727, _T_15730) @[ifu_bp_ctl.scala 443:110] + node _T_15732 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15733 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15734 = eq(_T_15733, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_15735 = and(_T_15732, _T_15734) @[ifu_bp_ctl.scala 444:22] + node _T_15736 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15737 = eq(_T_15736, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_15738 = or(_T_15737, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15739 = and(_T_15735, _T_15738) @[ifu_bp_ctl.scala 444:87] + node _T_15740 = or(_T_15731, _T_15739) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][0][12] <= _T_15740 @[ifu_bp_ctl.scala 443:27] + node _T_15741 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15742 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15743 = eq(_T_15742, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_15744 = and(_T_15741, _T_15743) @[ifu_bp_ctl.scala 443:45] + node _T_15745 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15746 = eq(_T_15745, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_15747 = or(_T_15746, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15748 = and(_T_15744, _T_15747) @[ifu_bp_ctl.scala 443:110] + node _T_15749 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15750 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15751 = eq(_T_15750, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_15752 = and(_T_15749, _T_15751) @[ifu_bp_ctl.scala 444:22] + node _T_15753 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15754 = eq(_T_15753, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_15755 = or(_T_15754, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15756 = and(_T_15752, _T_15755) @[ifu_bp_ctl.scala 444:87] + node _T_15757 = or(_T_15748, _T_15756) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][0][13] <= _T_15757 @[ifu_bp_ctl.scala 443:27] + node _T_15758 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15759 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15760 = eq(_T_15759, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_15761 = and(_T_15758, _T_15760) @[ifu_bp_ctl.scala 443:45] + node _T_15762 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15763 = eq(_T_15762, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_15764 = or(_T_15763, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15765 = and(_T_15761, _T_15764) @[ifu_bp_ctl.scala 443:110] + node _T_15766 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15767 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15768 = eq(_T_15767, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_15769 = and(_T_15766, _T_15768) @[ifu_bp_ctl.scala 444:22] + node _T_15770 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15771 = eq(_T_15770, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_15772 = or(_T_15771, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15773 = and(_T_15769, _T_15772) @[ifu_bp_ctl.scala 444:87] + node _T_15774 = or(_T_15765, _T_15773) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][0][14] <= _T_15774 @[ifu_bp_ctl.scala 443:27] + node _T_15775 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15776 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15777 = eq(_T_15776, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_15778 = and(_T_15775, _T_15777) @[ifu_bp_ctl.scala 443:45] + node _T_15779 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15780 = eq(_T_15779, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:186] + node _T_15781 = or(_T_15780, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15782 = and(_T_15778, _T_15781) @[ifu_bp_ctl.scala 443:110] + node _T_15783 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15784 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15785 = eq(_T_15784, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_15786 = and(_T_15783, _T_15785) @[ifu_bp_ctl.scala 444:22] + node _T_15787 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15788 = eq(_T_15787, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:163] + node _T_15789 = or(_T_15788, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15790 = and(_T_15786, _T_15789) @[ifu_bp_ctl.scala 444:87] + node _T_15791 = or(_T_15782, _T_15790) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][0][15] <= _T_15791 @[ifu_bp_ctl.scala 443:27] + node _T_15792 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15793 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15794 = eq(_T_15793, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_15795 = and(_T_15792, _T_15794) @[ifu_bp_ctl.scala 443:45] + node _T_15796 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15797 = eq(_T_15796, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_15798 = or(_T_15797, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15799 = and(_T_15795, _T_15798) @[ifu_bp_ctl.scala 443:110] + node _T_15800 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15801 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15802 = eq(_T_15801, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_15803 = and(_T_15800, _T_15802) @[ifu_bp_ctl.scala 444:22] + node _T_15804 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15805 = eq(_T_15804, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_15806 = or(_T_15805, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15807 = and(_T_15803, _T_15806) @[ifu_bp_ctl.scala 444:87] + node _T_15808 = or(_T_15799, _T_15807) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][1][0] <= _T_15808 @[ifu_bp_ctl.scala 443:27] + node _T_15809 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15810 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15811 = eq(_T_15810, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_15812 = and(_T_15809, _T_15811) @[ifu_bp_ctl.scala 443:45] + node _T_15813 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15814 = eq(_T_15813, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_15815 = or(_T_15814, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15816 = and(_T_15812, _T_15815) @[ifu_bp_ctl.scala 443:110] + node _T_15817 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15818 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15819 = eq(_T_15818, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_15820 = and(_T_15817, _T_15819) @[ifu_bp_ctl.scala 444:22] + node _T_15821 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15822 = eq(_T_15821, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_15823 = or(_T_15822, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15824 = and(_T_15820, _T_15823) @[ifu_bp_ctl.scala 444:87] + node _T_15825 = or(_T_15816, _T_15824) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][1][1] <= _T_15825 @[ifu_bp_ctl.scala 443:27] + node _T_15826 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15827 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15828 = eq(_T_15827, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_15829 = and(_T_15826, _T_15828) @[ifu_bp_ctl.scala 443:45] + node _T_15830 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15831 = eq(_T_15830, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_15832 = or(_T_15831, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15833 = and(_T_15829, _T_15832) @[ifu_bp_ctl.scala 443:110] + node _T_15834 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15835 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15836 = eq(_T_15835, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_15837 = and(_T_15834, _T_15836) @[ifu_bp_ctl.scala 444:22] + node _T_15838 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15839 = eq(_T_15838, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_15840 = or(_T_15839, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15841 = and(_T_15837, _T_15840) @[ifu_bp_ctl.scala 444:87] + node _T_15842 = or(_T_15833, _T_15841) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][1][2] <= _T_15842 @[ifu_bp_ctl.scala 443:27] + node _T_15843 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15844 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15845 = eq(_T_15844, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_15846 = and(_T_15843, _T_15845) @[ifu_bp_ctl.scala 443:45] + node _T_15847 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15848 = eq(_T_15847, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_15849 = or(_T_15848, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15850 = and(_T_15846, _T_15849) @[ifu_bp_ctl.scala 443:110] + node _T_15851 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15852 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15853 = eq(_T_15852, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_15854 = and(_T_15851, _T_15853) @[ifu_bp_ctl.scala 444:22] + node _T_15855 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15856 = eq(_T_15855, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_15857 = or(_T_15856, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15858 = and(_T_15854, _T_15857) @[ifu_bp_ctl.scala 444:87] + node _T_15859 = or(_T_15850, _T_15858) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][1][3] <= _T_15859 @[ifu_bp_ctl.scala 443:27] + node _T_15860 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15861 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15862 = eq(_T_15861, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_15863 = and(_T_15860, _T_15862) @[ifu_bp_ctl.scala 443:45] + node _T_15864 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15865 = eq(_T_15864, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_15866 = or(_T_15865, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15867 = and(_T_15863, _T_15866) @[ifu_bp_ctl.scala 443:110] + node _T_15868 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15869 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15870 = eq(_T_15869, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_15871 = and(_T_15868, _T_15870) @[ifu_bp_ctl.scala 444:22] + node _T_15872 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15873 = eq(_T_15872, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_15874 = or(_T_15873, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15875 = and(_T_15871, _T_15874) @[ifu_bp_ctl.scala 444:87] + node _T_15876 = or(_T_15867, _T_15875) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][1][4] <= _T_15876 @[ifu_bp_ctl.scala 443:27] + node _T_15877 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15878 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15879 = eq(_T_15878, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_15880 = and(_T_15877, _T_15879) @[ifu_bp_ctl.scala 443:45] + node _T_15881 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15882 = eq(_T_15881, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_15883 = or(_T_15882, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15884 = and(_T_15880, _T_15883) @[ifu_bp_ctl.scala 443:110] + node _T_15885 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15886 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15887 = eq(_T_15886, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_15888 = and(_T_15885, _T_15887) @[ifu_bp_ctl.scala 444:22] + node _T_15889 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15890 = eq(_T_15889, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_15891 = or(_T_15890, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15892 = and(_T_15888, _T_15891) @[ifu_bp_ctl.scala 444:87] + node _T_15893 = or(_T_15884, _T_15892) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][1][5] <= _T_15893 @[ifu_bp_ctl.scala 443:27] + node _T_15894 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15895 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15896 = eq(_T_15895, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_15897 = and(_T_15894, _T_15896) @[ifu_bp_ctl.scala 443:45] + node _T_15898 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15899 = eq(_T_15898, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_15900 = or(_T_15899, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15901 = and(_T_15897, _T_15900) @[ifu_bp_ctl.scala 443:110] + node _T_15902 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15903 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15904 = eq(_T_15903, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_15905 = and(_T_15902, _T_15904) @[ifu_bp_ctl.scala 444:22] + node _T_15906 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15907 = eq(_T_15906, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_15908 = or(_T_15907, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15909 = and(_T_15905, _T_15908) @[ifu_bp_ctl.scala 444:87] + node _T_15910 = or(_T_15901, _T_15909) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][1][6] <= _T_15910 @[ifu_bp_ctl.scala 443:27] + node _T_15911 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15912 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15913 = eq(_T_15912, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_15914 = and(_T_15911, _T_15913) @[ifu_bp_ctl.scala 443:45] + node _T_15915 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15916 = eq(_T_15915, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_15917 = or(_T_15916, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15918 = and(_T_15914, _T_15917) @[ifu_bp_ctl.scala 443:110] + node _T_15919 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15920 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15921 = eq(_T_15920, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_15922 = and(_T_15919, _T_15921) @[ifu_bp_ctl.scala 444:22] + node _T_15923 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15924 = eq(_T_15923, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_15925 = or(_T_15924, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15926 = and(_T_15922, _T_15925) @[ifu_bp_ctl.scala 444:87] + node _T_15927 = or(_T_15918, _T_15926) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][1][7] <= _T_15927 @[ifu_bp_ctl.scala 443:27] + node _T_15928 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15929 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15930 = eq(_T_15929, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_15931 = and(_T_15928, _T_15930) @[ifu_bp_ctl.scala 443:45] + node _T_15932 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15933 = eq(_T_15932, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_15934 = or(_T_15933, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15935 = and(_T_15931, _T_15934) @[ifu_bp_ctl.scala 443:110] + node _T_15936 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15937 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15938 = eq(_T_15937, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_15939 = and(_T_15936, _T_15938) @[ifu_bp_ctl.scala 444:22] + node _T_15940 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15941 = eq(_T_15940, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_15942 = or(_T_15941, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15943 = and(_T_15939, _T_15942) @[ifu_bp_ctl.scala 444:87] + node _T_15944 = or(_T_15935, _T_15943) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][1][8] <= _T_15944 @[ifu_bp_ctl.scala 443:27] + node _T_15945 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15946 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15947 = eq(_T_15946, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_15948 = and(_T_15945, _T_15947) @[ifu_bp_ctl.scala 443:45] + node _T_15949 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15950 = eq(_T_15949, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_15951 = or(_T_15950, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15952 = and(_T_15948, _T_15951) @[ifu_bp_ctl.scala 443:110] + node _T_15953 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15954 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15955 = eq(_T_15954, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_15956 = and(_T_15953, _T_15955) @[ifu_bp_ctl.scala 444:22] + node _T_15957 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15958 = eq(_T_15957, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_15959 = or(_T_15958, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15960 = and(_T_15956, _T_15959) @[ifu_bp_ctl.scala 444:87] + node _T_15961 = or(_T_15952, _T_15960) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][1][9] <= _T_15961 @[ifu_bp_ctl.scala 443:27] + node _T_15962 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15963 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15964 = eq(_T_15963, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_15965 = and(_T_15962, _T_15964) @[ifu_bp_ctl.scala 443:45] + node _T_15966 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15967 = eq(_T_15966, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_15968 = or(_T_15967, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15969 = and(_T_15965, _T_15968) @[ifu_bp_ctl.scala 443:110] + node _T_15970 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15971 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15972 = eq(_T_15971, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_15973 = and(_T_15970, _T_15972) @[ifu_bp_ctl.scala 444:22] + node _T_15974 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15975 = eq(_T_15974, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_15976 = or(_T_15975, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15977 = and(_T_15973, _T_15976) @[ifu_bp_ctl.scala 444:87] + node _T_15978 = or(_T_15969, _T_15977) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][1][10] <= _T_15978 @[ifu_bp_ctl.scala 443:27] + node _T_15979 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15980 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15981 = eq(_T_15980, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_15982 = and(_T_15979, _T_15981) @[ifu_bp_ctl.scala 443:45] + node _T_15983 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_15984 = eq(_T_15983, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_15985 = or(_T_15984, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_15986 = and(_T_15982, _T_15985) @[ifu_bp_ctl.scala 443:110] + node _T_15987 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_15988 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_15989 = eq(_T_15988, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_15990 = and(_T_15987, _T_15989) @[ifu_bp_ctl.scala 444:22] + node _T_15991 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_15992 = eq(_T_15991, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_15993 = or(_T_15992, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_15994 = and(_T_15990, _T_15993) @[ifu_bp_ctl.scala 444:87] + node _T_15995 = or(_T_15986, _T_15994) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][1][11] <= _T_15995 @[ifu_bp_ctl.scala 443:27] + node _T_15996 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_15997 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_15998 = eq(_T_15997, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_15999 = and(_T_15996, _T_15998) @[ifu_bp_ctl.scala 443:45] + node _T_16000 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16001 = eq(_T_16000, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_16002 = or(_T_16001, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16003 = and(_T_15999, _T_16002) @[ifu_bp_ctl.scala 443:110] + node _T_16004 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16005 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16006 = eq(_T_16005, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_16007 = and(_T_16004, _T_16006) @[ifu_bp_ctl.scala 444:22] + node _T_16008 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16009 = eq(_T_16008, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_16010 = or(_T_16009, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16011 = and(_T_16007, _T_16010) @[ifu_bp_ctl.scala 444:87] + node _T_16012 = or(_T_16003, _T_16011) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][1][12] <= _T_16012 @[ifu_bp_ctl.scala 443:27] + node _T_16013 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16014 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16015 = eq(_T_16014, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_16016 = and(_T_16013, _T_16015) @[ifu_bp_ctl.scala 443:45] + node _T_16017 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16018 = eq(_T_16017, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_16019 = or(_T_16018, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16020 = and(_T_16016, _T_16019) @[ifu_bp_ctl.scala 443:110] + node _T_16021 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16022 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16023 = eq(_T_16022, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_16024 = and(_T_16021, _T_16023) @[ifu_bp_ctl.scala 444:22] + node _T_16025 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16026 = eq(_T_16025, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_16027 = or(_T_16026, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16028 = and(_T_16024, _T_16027) @[ifu_bp_ctl.scala 444:87] + node _T_16029 = or(_T_16020, _T_16028) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][1][13] <= _T_16029 @[ifu_bp_ctl.scala 443:27] + node _T_16030 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16031 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16032 = eq(_T_16031, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_16033 = and(_T_16030, _T_16032) @[ifu_bp_ctl.scala 443:45] + node _T_16034 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16035 = eq(_T_16034, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_16036 = or(_T_16035, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16037 = and(_T_16033, _T_16036) @[ifu_bp_ctl.scala 443:110] + node _T_16038 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16039 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16040 = eq(_T_16039, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_16041 = and(_T_16038, _T_16040) @[ifu_bp_ctl.scala 444:22] + node _T_16042 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16043 = eq(_T_16042, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_16044 = or(_T_16043, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16045 = and(_T_16041, _T_16044) @[ifu_bp_ctl.scala 444:87] + node _T_16046 = or(_T_16037, _T_16045) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][1][14] <= _T_16046 @[ifu_bp_ctl.scala 443:27] + node _T_16047 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16048 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16049 = eq(_T_16048, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_16050 = and(_T_16047, _T_16049) @[ifu_bp_ctl.scala 443:45] + node _T_16051 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16052 = eq(_T_16051, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:186] + node _T_16053 = or(_T_16052, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16054 = and(_T_16050, _T_16053) @[ifu_bp_ctl.scala 443:110] + node _T_16055 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16056 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16057 = eq(_T_16056, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_16058 = and(_T_16055, _T_16057) @[ifu_bp_ctl.scala 444:22] + node _T_16059 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16060 = eq(_T_16059, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:163] + node _T_16061 = or(_T_16060, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16062 = and(_T_16058, _T_16061) @[ifu_bp_ctl.scala 444:87] + node _T_16063 = or(_T_16054, _T_16062) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][1][15] <= _T_16063 @[ifu_bp_ctl.scala 443:27] + node _T_16064 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16065 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16066 = eq(_T_16065, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_16067 = and(_T_16064, _T_16066) @[ifu_bp_ctl.scala 443:45] + node _T_16068 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16069 = eq(_T_16068, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_16070 = or(_T_16069, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16071 = and(_T_16067, _T_16070) @[ifu_bp_ctl.scala 443:110] + node _T_16072 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16073 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16074 = eq(_T_16073, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_16075 = and(_T_16072, _T_16074) @[ifu_bp_ctl.scala 444:22] + node _T_16076 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16077 = eq(_T_16076, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_16078 = or(_T_16077, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16079 = and(_T_16075, _T_16078) @[ifu_bp_ctl.scala 444:87] + node _T_16080 = or(_T_16071, _T_16079) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][2][0] <= _T_16080 @[ifu_bp_ctl.scala 443:27] + node _T_16081 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16082 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16083 = eq(_T_16082, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_16084 = and(_T_16081, _T_16083) @[ifu_bp_ctl.scala 443:45] + node _T_16085 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16086 = eq(_T_16085, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_16087 = or(_T_16086, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16088 = and(_T_16084, _T_16087) @[ifu_bp_ctl.scala 443:110] + node _T_16089 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16090 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16091 = eq(_T_16090, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_16092 = and(_T_16089, _T_16091) @[ifu_bp_ctl.scala 444:22] + node _T_16093 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16094 = eq(_T_16093, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_16095 = or(_T_16094, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16096 = and(_T_16092, _T_16095) @[ifu_bp_ctl.scala 444:87] + node _T_16097 = or(_T_16088, _T_16096) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][2][1] <= _T_16097 @[ifu_bp_ctl.scala 443:27] + node _T_16098 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16099 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16100 = eq(_T_16099, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_16101 = and(_T_16098, _T_16100) @[ifu_bp_ctl.scala 443:45] + node _T_16102 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16103 = eq(_T_16102, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_16104 = or(_T_16103, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16105 = and(_T_16101, _T_16104) @[ifu_bp_ctl.scala 443:110] + node _T_16106 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16107 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16108 = eq(_T_16107, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_16109 = and(_T_16106, _T_16108) @[ifu_bp_ctl.scala 444:22] + node _T_16110 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16111 = eq(_T_16110, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_16112 = or(_T_16111, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16113 = and(_T_16109, _T_16112) @[ifu_bp_ctl.scala 444:87] + node _T_16114 = or(_T_16105, _T_16113) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][2][2] <= _T_16114 @[ifu_bp_ctl.scala 443:27] + node _T_16115 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16116 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16117 = eq(_T_16116, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_16118 = and(_T_16115, _T_16117) @[ifu_bp_ctl.scala 443:45] + node _T_16119 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16120 = eq(_T_16119, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_16121 = or(_T_16120, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16122 = and(_T_16118, _T_16121) @[ifu_bp_ctl.scala 443:110] + node _T_16123 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16124 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16125 = eq(_T_16124, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_16126 = and(_T_16123, _T_16125) @[ifu_bp_ctl.scala 444:22] + node _T_16127 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16128 = eq(_T_16127, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_16129 = or(_T_16128, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16130 = and(_T_16126, _T_16129) @[ifu_bp_ctl.scala 444:87] + node _T_16131 = or(_T_16122, _T_16130) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][2][3] <= _T_16131 @[ifu_bp_ctl.scala 443:27] + node _T_16132 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16133 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16134 = eq(_T_16133, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_16135 = and(_T_16132, _T_16134) @[ifu_bp_ctl.scala 443:45] + node _T_16136 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16137 = eq(_T_16136, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_16138 = or(_T_16137, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16139 = and(_T_16135, _T_16138) @[ifu_bp_ctl.scala 443:110] + node _T_16140 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16141 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16142 = eq(_T_16141, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_16143 = and(_T_16140, _T_16142) @[ifu_bp_ctl.scala 444:22] + node _T_16144 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16145 = eq(_T_16144, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_16146 = or(_T_16145, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16147 = and(_T_16143, _T_16146) @[ifu_bp_ctl.scala 444:87] + node _T_16148 = or(_T_16139, _T_16147) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][2][4] <= _T_16148 @[ifu_bp_ctl.scala 443:27] + node _T_16149 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16150 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16151 = eq(_T_16150, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_16152 = and(_T_16149, _T_16151) @[ifu_bp_ctl.scala 443:45] + node _T_16153 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16154 = eq(_T_16153, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_16155 = or(_T_16154, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16156 = and(_T_16152, _T_16155) @[ifu_bp_ctl.scala 443:110] + node _T_16157 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16158 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16159 = eq(_T_16158, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_16160 = and(_T_16157, _T_16159) @[ifu_bp_ctl.scala 444:22] + node _T_16161 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16162 = eq(_T_16161, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_16163 = or(_T_16162, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16164 = and(_T_16160, _T_16163) @[ifu_bp_ctl.scala 444:87] + node _T_16165 = or(_T_16156, _T_16164) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][2][5] <= _T_16165 @[ifu_bp_ctl.scala 443:27] + node _T_16166 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16167 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16168 = eq(_T_16167, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_16169 = and(_T_16166, _T_16168) @[ifu_bp_ctl.scala 443:45] + node _T_16170 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16171 = eq(_T_16170, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_16172 = or(_T_16171, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16173 = and(_T_16169, _T_16172) @[ifu_bp_ctl.scala 443:110] + node _T_16174 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16175 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16176 = eq(_T_16175, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_16177 = and(_T_16174, _T_16176) @[ifu_bp_ctl.scala 444:22] + node _T_16178 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16179 = eq(_T_16178, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_16180 = or(_T_16179, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16181 = and(_T_16177, _T_16180) @[ifu_bp_ctl.scala 444:87] + node _T_16182 = or(_T_16173, _T_16181) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][2][6] <= _T_16182 @[ifu_bp_ctl.scala 443:27] + node _T_16183 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16184 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16185 = eq(_T_16184, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_16186 = and(_T_16183, _T_16185) @[ifu_bp_ctl.scala 443:45] + node _T_16187 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16188 = eq(_T_16187, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_16189 = or(_T_16188, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16190 = and(_T_16186, _T_16189) @[ifu_bp_ctl.scala 443:110] + node _T_16191 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16192 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16193 = eq(_T_16192, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_16194 = and(_T_16191, _T_16193) @[ifu_bp_ctl.scala 444:22] + node _T_16195 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16196 = eq(_T_16195, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_16197 = or(_T_16196, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16198 = and(_T_16194, _T_16197) @[ifu_bp_ctl.scala 444:87] + node _T_16199 = or(_T_16190, _T_16198) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][2][7] <= _T_16199 @[ifu_bp_ctl.scala 443:27] + node _T_16200 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16201 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16202 = eq(_T_16201, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_16203 = and(_T_16200, _T_16202) @[ifu_bp_ctl.scala 443:45] + node _T_16204 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16205 = eq(_T_16204, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_16206 = or(_T_16205, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16207 = and(_T_16203, _T_16206) @[ifu_bp_ctl.scala 443:110] + node _T_16208 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16209 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16210 = eq(_T_16209, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_16211 = and(_T_16208, _T_16210) @[ifu_bp_ctl.scala 444:22] + node _T_16212 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16213 = eq(_T_16212, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_16214 = or(_T_16213, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16215 = and(_T_16211, _T_16214) @[ifu_bp_ctl.scala 444:87] + node _T_16216 = or(_T_16207, _T_16215) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][2][8] <= _T_16216 @[ifu_bp_ctl.scala 443:27] + node _T_16217 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16218 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16219 = eq(_T_16218, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_16220 = and(_T_16217, _T_16219) @[ifu_bp_ctl.scala 443:45] + node _T_16221 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16222 = eq(_T_16221, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_16223 = or(_T_16222, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16224 = and(_T_16220, _T_16223) @[ifu_bp_ctl.scala 443:110] + node _T_16225 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16226 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16227 = eq(_T_16226, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_16228 = and(_T_16225, _T_16227) @[ifu_bp_ctl.scala 444:22] + node _T_16229 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16230 = eq(_T_16229, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_16231 = or(_T_16230, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16232 = and(_T_16228, _T_16231) @[ifu_bp_ctl.scala 444:87] + node _T_16233 = or(_T_16224, _T_16232) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][2][9] <= _T_16233 @[ifu_bp_ctl.scala 443:27] + node _T_16234 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16235 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16236 = eq(_T_16235, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_16237 = and(_T_16234, _T_16236) @[ifu_bp_ctl.scala 443:45] + node _T_16238 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16239 = eq(_T_16238, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_16240 = or(_T_16239, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16241 = and(_T_16237, _T_16240) @[ifu_bp_ctl.scala 443:110] + node _T_16242 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16243 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16244 = eq(_T_16243, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_16245 = and(_T_16242, _T_16244) @[ifu_bp_ctl.scala 444:22] + node _T_16246 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16247 = eq(_T_16246, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_16248 = or(_T_16247, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16249 = and(_T_16245, _T_16248) @[ifu_bp_ctl.scala 444:87] + node _T_16250 = or(_T_16241, _T_16249) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][2][10] <= _T_16250 @[ifu_bp_ctl.scala 443:27] + node _T_16251 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16252 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16253 = eq(_T_16252, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_16254 = and(_T_16251, _T_16253) @[ifu_bp_ctl.scala 443:45] + node _T_16255 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16256 = eq(_T_16255, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_16257 = or(_T_16256, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16258 = and(_T_16254, _T_16257) @[ifu_bp_ctl.scala 443:110] + node _T_16259 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16260 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16261 = eq(_T_16260, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_16262 = and(_T_16259, _T_16261) @[ifu_bp_ctl.scala 444:22] + node _T_16263 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16264 = eq(_T_16263, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_16265 = or(_T_16264, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16266 = and(_T_16262, _T_16265) @[ifu_bp_ctl.scala 444:87] + node _T_16267 = or(_T_16258, _T_16266) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][2][11] <= _T_16267 @[ifu_bp_ctl.scala 443:27] + node _T_16268 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16269 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16270 = eq(_T_16269, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_16271 = and(_T_16268, _T_16270) @[ifu_bp_ctl.scala 443:45] + node _T_16272 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16273 = eq(_T_16272, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_16274 = or(_T_16273, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16275 = and(_T_16271, _T_16274) @[ifu_bp_ctl.scala 443:110] + node _T_16276 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16277 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16278 = eq(_T_16277, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_16279 = and(_T_16276, _T_16278) @[ifu_bp_ctl.scala 444:22] + node _T_16280 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16281 = eq(_T_16280, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_16282 = or(_T_16281, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16283 = and(_T_16279, _T_16282) @[ifu_bp_ctl.scala 444:87] + node _T_16284 = or(_T_16275, _T_16283) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][2][12] <= _T_16284 @[ifu_bp_ctl.scala 443:27] + node _T_16285 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16286 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16287 = eq(_T_16286, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_16288 = and(_T_16285, _T_16287) @[ifu_bp_ctl.scala 443:45] + node _T_16289 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16290 = eq(_T_16289, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_16291 = or(_T_16290, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16292 = and(_T_16288, _T_16291) @[ifu_bp_ctl.scala 443:110] + node _T_16293 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16294 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16295 = eq(_T_16294, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_16296 = and(_T_16293, _T_16295) @[ifu_bp_ctl.scala 444:22] + node _T_16297 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16298 = eq(_T_16297, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_16299 = or(_T_16298, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16300 = and(_T_16296, _T_16299) @[ifu_bp_ctl.scala 444:87] + node _T_16301 = or(_T_16292, _T_16300) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][2][13] <= _T_16301 @[ifu_bp_ctl.scala 443:27] + node _T_16302 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16303 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16304 = eq(_T_16303, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_16305 = and(_T_16302, _T_16304) @[ifu_bp_ctl.scala 443:45] + node _T_16306 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16307 = eq(_T_16306, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_16308 = or(_T_16307, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16309 = and(_T_16305, _T_16308) @[ifu_bp_ctl.scala 443:110] + node _T_16310 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16311 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16312 = eq(_T_16311, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_16313 = and(_T_16310, _T_16312) @[ifu_bp_ctl.scala 444:22] + node _T_16314 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16315 = eq(_T_16314, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_16316 = or(_T_16315, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16317 = and(_T_16313, _T_16316) @[ifu_bp_ctl.scala 444:87] + node _T_16318 = or(_T_16309, _T_16317) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][2][14] <= _T_16318 @[ifu_bp_ctl.scala 443:27] + node _T_16319 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16320 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16321 = eq(_T_16320, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_16322 = and(_T_16319, _T_16321) @[ifu_bp_ctl.scala 443:45] + node _T_16323 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16324 = eq(_T_16323, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:186] + node _T_16325 = or(_T_16324, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16326 = and(_T_16322, _T_16325) @[ifu_bp_ctl.scala 443:110] + node _T_16327 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16328 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16329 = eq(_T_16328, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_16330 = and(_T_16327, _T_16329) @[ifu_bp_ctl.scala 444:22] + node _T_16331 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16332 = eq(_T_16331, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:163] + node _T_16333 = or(_T_16332, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16334 = and(_T_16330, _T_16333) @[ifu_bp_ctl.scala 444:87] + node _T_16335 = or(_T_16326, _T_16334) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][2][15] <= _T_16335 @[ifu_bp_ctl.scala 443:27] + node _T_16336 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16337 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16338 = eq(_T_16337, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_16339 = and(_T_16336, _T_16338) @[ifu_bp_ctl.scala 443:45] + node _T_16340 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16341 = eq(_T_16340, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_16342 = or(_T_16341, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16343 = and(_T_16339, _T_16342) @[ifu_bp_ctl.scala 443:110] + node _T_16344 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16345 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16346 = eq(_T_16345, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_16347 = and(_T_16344, _T_16346) @[ifu_bp_ctl.scala 444:22] + node _T_16348 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16349 = eq(_T_16348, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_16350 = or(_T_16349, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16351 = and(_T_16347, _T_16350) @[ifu_bp_ctl.scala 444:87] + node _T_16352 = or(_T_16343, _T_16351) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][3][0] <= _T_16352 @[ifu_bp_ctl.scala 443:27] + node _T_16353 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16354 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16355 = eq(_T_16354, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_16356 = and(_T_16353, _T_16355) @[ifu_bp_ctl.scala 443:45] + node _T_16357 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16358 = eq(_T_16357, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_16359 = or(_T_16358, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16360 = and(_T_16356, _T_16359) @[ifu_bp_ctl.scala 443:110] + node _T_16361 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16362 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16363 = eq(_T_16362, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_16364 = and(_T_16361, _T_16363) @[ifu_bp_ctl.scala 444:22] + node _T_16365 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16366 = eq(_T_16365, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_16367 = or(_T_16366, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16368 = and(_T_16364, _T_16367) @[ifu_bp_ctl.scala 444:87] + node _T_16369 = or(_T_16360, _T_16368) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][3][1] <= _T_16369 @[ifu_bp_ctl.scala 443:27] + node _T_16370 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16371 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16372 = eq(_T_16371, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_16373 = and(_T_16370, _T_16372) @[ifu_bp_ctl.scala 443:45] + node _T_16374 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16375 = eq(_T_16374, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_16376 = or(_T_16375, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16377 = and(_T_16373, _T_16376) @[ifu_bp_ctl.scala 443:110] + node _T_16378 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16379 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16380 = eq(_T_16379, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_16381 = and(_T_16378, _T_16380) @[ifu_bp_ctl.scala 444:22] + node _T_16382 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16383 = eq(_T_16382, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_16384 = or(_T_16383, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16385 = and(_T_16381, _T_16384) @[ifu_bp_ctl.scala 444:87] + node _T_16386 = or(_T_16377, _T_16385) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][3][2] <= _T_16386 @[ifu_bp_ctl.scala 443:27] + node _T_16387 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16388 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16389 = eq(_T_16388, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_16390 = and(_T_16387, _T_16389) @[ifu_bp_ctl.scala 443:45] + node _T_16391 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16392 = eq(_T_16391, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_16393 = or(_T_16392, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16394 = and(_T_16390, _T_16393) @[ifu_bp_ctl.scala 443:110] + node _T_16395 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16396 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16397 = eq(_T_16396, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_16398 = and(_T_16395, _T_16397) @[ifu_bp_ctl.scala 444:22] + node _T_16399 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16400 = eq(_T_16399, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_16401 = or(_T_16400, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16402 = and(_T_16398, _T_16401) @[ifu_bp_ctl.scala 444:87] + node _T_16403 = or(_T_16394, _T_16402) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][3][3] <= _T_16403 @[ifu_bp_ctl.scala 443:27] + node _T_16404 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16405 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16406 = eq(_T_16405, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_16407 = and(_T_16404, _T_16406) @[ifu_bp_ctl.scala 443:45] + node _T_16408 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16409 = eq(_T_16408, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_16410 = or(_T_16409, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16411 = and(_T_16407, _T_16410) @[ifu_bp_ctl.scala 443:110] + node _T_16412 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16413 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16414 = eq(_T_16413, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_16415 = and(_T_16412, _T_16414) @[ifu_bp_ctl.scala 444:22] + node _T_16416 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16417 = eq(_T_16416, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_16418 = or(_T_16417, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16419 = and(_T_16415, _T_16418) @[ifu_bp_ctl.scala 444:87] + node _T_16420 = or(_T_16411, _T_16419) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][3][4] <= _T_16420 @[ifu_bp_ctl.scala 443:27] + node _T_16421 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16422 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16423 = eq(_T_16422, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_16424 = and(_T_16421, _T_16423) @[ifu_bp_ctl.scala 443:45] + node _T_16425 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16426 = eq(_T_16425, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_16427 = or(_T_16426, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16428 = and(_T_16424, _T_16427) @[ifu_bp_ctl.scala 443:110] + node _T_16429 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16430 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16431 = eq(_T_16430, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_16432 = and(_T_16429, _T_16431) @[ifu_bp_ctl.scala 444:22] + node _T_16433 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16434 = eq(_T_16433, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_16435 = or(_T_16434, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16436 = and(_T_16432, _T_16435) @[ifu_bp_ctl.scala 444:87] + node _T_16437 = or(_T_16428, _T_16436) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][3][5] <= _T_16437 @[ifu_bp_ctl.scala 443:27] + node _T_16438 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16439 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16440 = eq(_T_16439, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_16441 = and(_T_16438, _T_16440) @[ifu_bp_ctl.scala 443:45] + node _T_16442 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16443 = eq(_T_16442, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_16444 = or(_T_16443, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16445 = and(_T_16441, _T_16444) @[ifu_bp_ctl.scala 443:110] + node _T_16446 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16447 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16448 = eq(_T_16447, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_16449 = and(_T_16446, _T_16448) @[ifu_bp_ctl.scala 444:22] + node _T_16450 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16451 = eq(_T_16450, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_16452 = or(_T_16451, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16453 = and(_T_16449, _T_16452) @[ifu_bp_ctl.scala 444:87] + node _T_16454 = or(_T_16445, _T_16453) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][3][6] <= _T_16454 @[ifu_bp_ctl.scala 443:27] + node _T_16455 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16456 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16457 = eq(_T_16456, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_16458 = and(_T_16455, _T_16457) @[ifu_bp_ctl.scala 443:45] + node _T_16459 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16460 = eq(_T_16459, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_16461 = or(_T_16460, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16462 = and(_T_16458, _T_16461) @[ifu_bp_ctl.scala 443:110] + node _T_16463 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16464 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16465 = eq(_T_16464, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_16466 = and(_T_16463, _T_16465) @[ifu_bp_ctl.scala 444:22] + node _T_16467 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16468 = eq(_T_16467, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_16469 = or(_T_16468, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16470 = and(_T_16466, _T_16469) @[ifu_bp_ctl.scala 444:87] + node _T_16471 = or(_T_16462, _T_16470) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][3][7] <= _T_16471 @[ifu_bp_ctl.scala 443:27] + node _T_16472 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16473 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16474 = eq(_T_16473, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_16475 = and(_T_16472, _T_16474) @[ifu_bp_ctl.scala 443:45] + node _T_16476 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16477 = eq(_T_16476, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_16478 = or(_T_16477, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16479 = and(_T_16475, _T_16478) @[ifu_bp_ctl.scala 443:110] + node _T_16480 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16481 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16482 = eq(_T_16481, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_16483 = and(_T_16480, _T_16482) @[ifu_bp_ctl.scala 444:22] + node _T_16484 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16485 = eq(_T_16484, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_16486 = or(_T_16485, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16487 = and(_T_16483, _T_16486) @[ifu_bp_ctl.scala 444:87] + node _T_16488 = or(_T_16479, _T_16487) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][3][8] <= _T_16488 @[ifu_bp_ctl.scala 443:27] + node _T_16489 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16490 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16491 = eq(_T_16490, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_16492 = and(_T_16489, _T_16491) @[ifu_bp_ctl.scala 443:45] + node _T_16493 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16494 = eq(_T_16493, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_16495 = or(_T_16494, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16496 = and(_T_16492, _T_16495) @[ifu_bp_ctl.scala 443:110] + node _T_16497 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16498 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16499 = eq(_T_16498, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_16500 = and(_T_16497, _T_16499) @[ifu_bp_ctl.scala 444:22] + node _T_16501 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16502 = eq(_T_16501, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_16503 = or(_T_16502, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16504 = and(_T_16500, _T_16503) @[ifu_bp_ctl.scala 444:87] + node _T_16505 = or(_T_16496, _T_16504) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][3][9] <= _T_16505 @[ifu_bp_ctl.scala 443:27] + node _T_16506 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16507 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16508 = eq(_T_16507, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_16509 = and(_T_16506, _T_16508) @[ifu_bp_ctl.scala 443:45] + node _T_16510 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16511 = eq(_T_16510, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_16512 = or(_T_16511, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16513 = and(_T_16509, _T_16512) @[ifu_bp_ctl.scala 443:110] + node _T_16514 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16515 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16516 = eq(_T_16515, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_16517 = and(_T_16514, _T_16516) @[ifu_bp_ctl.scala 444:22] + node _T_16518 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16519 = eq(_T_16518, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_16520 = or(_T_16519, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16521 = and(_T_16517, _T_16520) @[ifu_bp_ctl.scala 444:87] + node _T_16522 = or(_T_16513, _T_16521) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][3][10] <= _T_16522 @[ifu_bp_ctl.scala 443:27] + node _T_16523 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16524 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16525 = eq(_T_16524, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_16526 = and(_T_16523, _T_16525) @[ifu_bp_ctl.scala 443:45] + node _T_16527 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16528 = eq(_T_16527, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_16529 = or(_T_16528, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16530 = and(_T_16526, _T_16529) @[ifu_bp_ctl.scala 443:110] + node _T_16531 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16532 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16533 = eq(_T_16532, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_16534 = and(_T_16531, _T_16533) @[ifu_bp_ctl.scala 444:22] + node _T_16535 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16536 = eq(_T_16535, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_16537 = or(_T_16536, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16538 = and(_T_16534, _T_16537) @[ifu_bp_ctl.scala 444:87] + node _T_16539 = or(_T_16530, _T_16538) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][3][11] <= _T_16539 @[ifu_bp_ctl.scala 443:27] + node _T_16540 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16541 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16542 = eq(_T_16541, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_16543 = and(_T_16540, _T_16542) @[ifu_bp_ctl.scala 443:45] + node _T_16544 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16545 = eq(_T_16544, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_16546 = or(_T_16545, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16547 = and(_T_16543, _T_16546) @[ifu_bp_ctl.scala 443:110] + node _T_16548 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16549 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16550 = eq(_T_16549, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_16551 = and(_T_16548, _T_16550) @[ifu_bp_ctl.scala 444:22] + node _T_16552 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16553 = eq(_T_16552, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_16554 = or(_T_16553, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16555 = and(_T_16551, _T_16554) @[ifu_bp_ctl.scala 444:87] + node _T_16556 = or(_T_16547, _T_16555) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][3][12] <= _T_16556 @[ifu_bp_ctl.scala 443:27] + node _T_16557 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16558 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16559 = eq(_T_16558, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_16560 = and(_T_16557, _T_16559) @[ifu_bp_ctl.scala 443:45] + node _T_16561 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16562 = eq(_T_16561, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_16563 = or(_T_16562, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16564 = and(_T_16560, _T_16563) @[ifu_bp_ctl.scala 443:110] + node _T_16565 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16566 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16567 = eq(_T_16566, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_16568 = and(_T_16565, _T_16567) @[ifu_bp_ctl.scala 444:22] + node _T_16569 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16570 = eq(_T_16569, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_16571 = or(_T_16570, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16572 = and(_T_16568, _T_16571) @[ifu_bp_ctl.scala 444:87] + node _T_16573 = or(_T_16564, _T_16572) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][3][13] <= _T_16573 @[ifu_bp_ctl.scala 443:27] + node _T_16574 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16575 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16576 = eq(_T_16575, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_16577 = and(_T_16574, _T_16576) @[ifu_bp_ctl.scala 443:45] + node _T_16578 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16579 = eq(_T_16578, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_16580 = or(_T_16579, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16581 = and(_T_16577, _T_16580) @[ifu_bp_ctl.scala 443:110] + node _T_16582 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16583 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16584 = eq(_T_16583, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_16585 = and(_T_16582, _T_16584) @[ifu_bp_ctl.scala 444:22] + node _T_16586 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16587 = eq(_T_16586, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_16588 = or(_T_16587, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16589 = and(_T_16585, _T_16588) @[ifu_bp_ctl.scala 444:87] + node _T_16590 = or(_T_16581, _T_16589) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][3][14] <= _T_16590 @[ifu_bp_ctl.scala 443:27] + node _T_16591 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16592 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16593 = eq(_T_16592, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_16594 = and(_T_16591, _T_16593) @[ifu_bp_ctl.scala 443:45] + node _T_16595 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16596 = eq(_T_16595, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:186] + node _T_16597 = or(_T_16596, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16598 = and(_T_16594, _T_16597) @[ifu_bp_ctl.scala 443:110] + node _T_16599 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16600 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16601 = eq(_T_16600, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_16602 = and(_T_16599, _T_16601) @[ifu_bp_ctl.scala 444:22] + node _T_16603 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16604 = eq(_T_16603, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:163] + node _T_16605 = or(_T_16604, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16606 = and(_T_16602, _T_16605) @[ifu_bp_ctl.scala 444:87] + node _T_16607 = or(_T_16598, _T_16606) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][3][15] <= _T_16607 @[ifu_bp_ctl.scala 443:27] + node _T_16608 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16609 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16610 = eq(_T_16609, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_16611 = and(_T_16608, _T_16610) @[ifu_bp_ctl.scala 443:45] + node _T_16612 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16613 = eq(_T_16612, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_16614 = or(_T_16613, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16615 = and(_T_16611, _T_16614) @[ifu_bp_ctl.scala 443:110] + node _T_16616 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16617 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16618 = eq(_T_16617, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_16619 = and(_T_16616, _T_16618) @[ifu_bp_ctl.scala 444:22] + node _T_16620 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16621 = eq(_T_16620, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_16622 = or(_T_16621, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16623 = and(_T_16619, _T_16622) @[ifu_bp_ctl.scala 444:87] + node _T_16624 = or(_T_16615, _T_16623) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][4][0] <= _T_16624 @[ifu_bp_ctl.scala 443:27] + node _T_16625 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16626 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16627 = eq(_T_16626, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_16628 = and(_T_16625, _T_16627) @[ifu_bp_ctl.scala 443:45] + node _T_16629 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16630 = eq(_T_16629, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_16631 = or(_T_16630, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16632 = and(_T_16628, _T_16631) @[ifu_bp_ctl.scala 443:110] + node _T_16633 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16634 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16635 = eq(_T_16634, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_16636 = and(_T_16633, _T_16635) @[ifu_bp_ctl.scala 444:22] + node _T_16637 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16638 = eq(_T_16637, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_16639 = or(_T_16638, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16640 = and(_T_16636, _T_16639) @[ifu_bp_ctl.scala 444:87] + node _T_16641 = or(_T_16632, _T_16640) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][4][1] <= _T_16641 @[ifu_bp_ctl.scala 443:27] + node _T_16642 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16643 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16644 = eq(_T_16643, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_16645 = and(_T_16642, _T_16644) @[ifu_bp_ctl.scala 443:45] + node _T_16646 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16647 = eq(_T_16646, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_16648 = or(_T_16647, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16649 = and(_T_16645, _T_16648) @[ifu_bp_ctl.scala 443:110] + node _T_16650 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16651 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16652 = eq(_T_16651, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_16653 = and(_T_16650, _T_16652) @[ifu_bp_ctl.scala 444:22] + node _T_16654 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16655 = eq(_T_16654, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_16656 = or(_T_16655, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16657 = and(_T_16653, _T_16656) @[ifu_bp_ctl.scala 444:87] + node _T_16658 = or(_T_16649, _T_16657) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][4][2] <= _T_16658 @[ifu_bp_ctl.scala 443:27] + node _T_16659 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16660 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16661 = eq(_T_16660, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_16662 = and(_T_16659, _T_16661) @[ifu_bp_ctl.scala 443:45] + node _T_16663 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16664 = eq(_T_16663, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_16665 = or(_T_16664, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16666 = and(_T_16662, _T_16665) @[ifu_bp_ctl.scala 443:110] + node _T_16667 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16668 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16669 = eq(_T_16668, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_16670 = and(_T_16667, _T_16669) @[ifu_bp_ctl.scala 444:22] + node _T_16671 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16672 = eq(_T_16671, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_16673 = or(_T_16672, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16674 = and(_T_16670, _T_16673) @[ifu_bp_ctl.scala 444:87] + node _T_16675 = or(_T_16666, _T_16674) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][4][3] <= _T_16675 @[ifu_bp_ctl.scala 443:27] + node _T_16676 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16677 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16678 = eq(_T_16677, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_16679 = and(_T_16676, _T_16678) @[ifu_bp_ctl.scala 443:45] + node _T_16680 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16681 = eq(_T_16680, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_16682 = or(_T_16681, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16683 = and(_T_16679, _T_16682) @[ifu_bp_ctl.scala 443:110] + node _T_16684 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16685 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16686 = eq(_T_16685, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_16687 = and(_T_16684, _T_16686) @[ifu_bp_ctl.scala 444:22] + node _T_16688 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16689 = eq(_T_16688, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_16690 = or(_T_16689, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16691 = and(_T_16687, _T_16690) @[ifu_bp_ctl.scala 444:87] + node _T_16692 = or(_T_16683, _T_16691) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][4][4] <= _T_16692 @[ifu_bp_ctl.scala 443:27] + node _T_16693 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16694 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16695 = eq(_T_16694, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_16696 = and(_T_16693, _T_16695) @[ifu_bp_ctl.scala 443:45] + node _T_16697 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16698 = eq(_T_16697, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_16699 = or(_T_16698, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16700 = and(_T_16696, _T_16699) @[ifu_bp_ctl.scala 443:110] + node _T_16701 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16702 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16703 = eq(_T_16702, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_16704 = and(_T_16701, _T_16703) @[ifu_bp_ctl.scala 444:22] + node _T_16705 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16706 = eq(_T_16705, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_16707 = or(_T_16706, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16708 = and(_T_16704, _T_16707) @[ifu_bp_ctl.scala 444:87] + node _T_16709 = or(_T_16700, _T_16708) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][4][5] <= _T_16709 @[ifu_bp_ctl.scala 443:27] + node _T_16710 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16711 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16712 = eq(_T_16711, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_16713 = and(_T_16710, _T_16712) @[ifu_bp_ctl.scala 443:45] + node _T_16714 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16715 = eq(_T_16714, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_16716 = or(_T_16715, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16717 = and(_T_16713, _T_16716) @[ifu_bp_ctl.scala 443:110] + node _T_16718 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16719 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16720 = eq(_T_16719, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_16721 = and(_T_16718, _T_16720) @[ifu_bp_ctl.scala 444:22] + node _T_16722 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16723 = eq(_T_16722, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_16724 = or(_T_16723, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16725 = and(_T_16721, _T_16724) @[ifu_bp_ctl.scala 444:87] + node _T_16726 = or(_T_16717, _T_16725) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][4][6] <= _T_16726 @[ifu_bp_ctl.scala 443:27] + node _T_16727 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16728 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16729 = eq(_T_16728, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_16730 = and(_T_16727, _T_16729) @[ifu_bp_ctl.scala 443:45] + node _T_16731 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16732 = eq(_T_16731, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_16733 = or(_T_16732, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16734 = and(_T_16730, _T_16733) @[ifu_bp_ctl.scala 443:110] + node _T_16735 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16736 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16737 = eq(_T_16736, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_16738 = and(_T_16735, _T_16737) @[ifu_bp_ctl.scala 444:22] + node _T_16739 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16740 = eq(_T_16739, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_16741 = or(_T_16740, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16742 = and(_T_16738, _T_16741) @[ifu_bp_ctl.scala 444:87] + node _T_16743 = or(_T_16734, _T_16742) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][4][7] <= _T_16743 @[ifu_bp_ctl.scala 443:27] + node _T_16744 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16745 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16746 = eq(_T_16745, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_16747 = and(_T_16744, _T_16746) @[ifu_bp_ctl.scala 443:45] + node _T_16748 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16749 = eq(_T_16748, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_16750 = or(_T_16749, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16751 = and(_T_16747, _T_16750) @[ifu_bp_ctl.scala 443:110] + node _T_16752 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16753 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16754 = eq(_T_16753, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_16755 = and(_T_16752, _T_16754) @[ifu_bp_ctl.scala 444:22] + node _T_16756 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16757 = eq(_T_16756, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_16758 = or(_T_16757, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16759 = and(_T_16755, _T_16758) @[ifu_bp_ctl.scala 444:87] + node _T_16760 = or(_T_16751, _T_16759) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][4][8] <= _T_16760 @[ifu_bp_ctl.scala 443:27] + node _T_16761 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16762 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16763 = eq(_T_16762, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_16764 = and(_T_16761, _T_16763) @[ifu_bp_ctl.scala 443:45] + node _T_16765 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16766 = eq(_T_16765, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_16767 = or(_T_16766, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16768 = and(_T_16764, _T_16767) @[ifu_bp_ctl.scala 443:110] + node _T_16769 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16770 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16771 = eq(_T_16770, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_16772 = and(_T_16769, _T_16771) @[ifu_bp_ctl.scala 444:22] + node _T_16773 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16774 = eq(_T_16773, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_16775 = or(_T_16774, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16776 = and(_T_16772, _T_16775) @[ifu_bp_ctl.scala 444:87] + node _T_16777 = or(_T_16768, _T_16776) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][4][9] <= _T_16777 @[ifu_bp_ctl.scala 443:27] + node _T_16778 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16779 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16780 = eq(_T_16779, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_16781 = and(_T_16778, _T_16780) @[ifu_bp_ctl.scala 443:45] + node _T_16782 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16783 = eq(_T_16782, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_16784 = or(_T_16783, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16785 = and(_T_16781, _T_16784) @[ifu_bp_ctl.scala 443:110] + node _T_16786 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16787 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16788 = eq(_T_16787, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_16789 = and(_T_16786, _T_16788) @[ifu_bp_ctl.scala 444:22] + node _T_16790 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16791 = eq(_T_16790, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_16792 = or(_T_16791, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16793 = and(_T_16789, _T_16792) @[ifu_bp_ctl.scala 444:87] + node _T_16794 = or(_T_16785, _T_16793) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][4][10] <= _T_16794 @[ifu_bp_ctl.scala 443:27] + node _T_16795 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16796 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16797 = eq(_T_16796, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_16798 = and(_T_16795, _T_16797) @[ifu_bp_ctl.scala 443:45] + node _T_16799 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16800 = eq(_T_16799, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_16801 = or(_T_16800, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16802 = and(_T_16798, _T_16801) @[ifu_bp_ctl.scala 443:110] + node _T_16803 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16804 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16805 = eq(_T_16804, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_16806 = and(_T_16803, _T_16805) @[ifu_bp_ctl.scala 444:22] + node _T_16807 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16808 = eq(_T_16807, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_16809 = or(_T_16808, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16810 = and(_T_16806, _T_16809) @[ifu_bp_ctl.scala 444:87] + node _T_16811 = or(_T_16802, _T_16810) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][4][11] <= _T_16811 @[ifu_bp_ctl.scala 443:27] + node _T_16812 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16813 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16814 = eq(_T_16813, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_16815 = and(_T_16812, _T_16814) @[ifu_bp_ctl.scala 443:45] + node _T_16816 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16817 = eq(_T_16816, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_16818 = or(_T_16817, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16819 = and(_T_16815, _T_16818) @[ifu_bp_ctl.scala 443:110] + node _T_16820 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16821 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16822 = eq(_T_16821, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_16823 = and(_T_16820, _T_16822) @[ifu_bp_ctl.scala 444:22] + node _T_16824 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16825 = eq(_T_16824, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_16826 = or(_T_16825, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16827 = and(_T_16823, _T_16826) @[ifu_bp_ctl.scala 444:87] + node _T_16828 = or(_T_16819, _T_16827) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][4][12] <= _T_16828 @[ifu_bp_ctl.scala 443:27] + node _T_16829 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16830 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16831 = eq(_T_16830, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_16832 = and(_T_16829, _T_16831) @[ifu_bp_ctl.scala 443:45] + node _T_16833 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16834 = eq(_T_16833, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_16835 = or(_T_16834, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16836 = and(_T_16832, _T_16835) @[ifu_bp_ctl.scala 443:110] + node _T_16837 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16838 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16839 = eq(_T_16838, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_16840 = and(_T_16837, _T_16839) @[ifu_bp_ctl.scala 444:22] + node _T_16841 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16842 = eq(_T_16841, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_16843 = or(_T_16842, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16844 = and(_T_16840, _T_16843) @[ifu_bp_ctl.scala 444:87] + node _T_16845 = or(_T_16836, _T_16844) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][4][13] <= _T_16845 @[ifu_bp_ctl.scala 443:27] + node _T_16846 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16847 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16848 = eq(_T_16847, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_16849 = and(_T_16846, _T_16848) @[ifu_bp_ctl.scala 443:45] + node _T_16850 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16851 = eq(_T_16850, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_16852 = or(_T_16851, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16853 = and(_T_16849, _T_16852) @[ifu_bp_ctl.scala 443:110] + node _T_16854 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16855 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16856 = eq(_T_16855, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_16857 = and(_T_16854, _T_16856) @[ifu_bp_ctl.scala 444:22] + node _T_16858 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16859 = eq(_T_16858, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_16860 = or(_T_16859, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16861 = and(_T_16857, _T_16860) @[ifu_bp_ctl.scala 444:87] + node _T_16862 = or(_T_16853, _T_16861) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][4][14] <= _T_16862 @[ifu_bp_ctl.scala 443:27] + node _T_16863 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16864 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16865 = eq(_T_16864, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_16866 = and(_T_16863, _T_16865) @[ifu_bp_ctl.scala 443:45] + node _T_16867 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16868 = eq(_T_16867, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:186] + node _T_16869 = or(_T_16868, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16870 = and(_T_16866, _T_16869) @[ifu_bp_ctl.scala 443:110] + node _T_16871 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16872 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16873 = eq(_T_16872, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_16874 = and(_T_16871, _T_16873) @[ifu_bp_ctl.scala 444:22] + node _T_16875 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16876 = eq(_T_16875, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:163] + node _T_16877 = or(_T_16876, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16878 = and(_T_16874, _T_16877) @[ifu_bp_ctl.scala 444:87] + node _T_16879 = or(_T_16870, _T_16878) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][4][15] <= _T_16879 @[ifu_bp_ctl.scala 443:27] + node _T_16880 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16881 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16882 = eq(_T_16881, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_16883 = and(_T_16880, _T_16882) @[ifu_bp_ctl.scala 443:45] + node _T_16884 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16885 = eq(_T_16884, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_16886 = or(_T_16885, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16887 = and(_T_16883, _T_16886) @[ifu_bp_ctl.scala 443:110] + node _T_16888 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16889 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16890 = eq(_T_16889, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_16891 = and(_T_16888, _T_16890) @[ifu_bp_ctl.scala 444:22] + node _T_16892 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16893 = eq(_T_16892, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_16894 = or(_T_16893, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16895 = and(_T_16891, _T_16894) @[ifu_bp_ctl.scala 444:87] + node _T_16896 = or(_T_16887, _T_16895) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][5][0] <= _T_16896 @[ifu_bp_ctl.scala 443:27] + node _T_16897 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16898 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16899 = eq(_T_16898, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_16900 = and(_T_16897, _T_16899) @[ifu_bp_ctl.scala 443:45] + node _T_16901 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16902 = eq(_T_16901, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_16903 = or(_T_16902, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16904 = and(_T_16900, _T_16903) @[ifu_bp_ctl.scala 443:110] + node _T_16905 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16906 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16907 = eq(_T_16906, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_16908 = and(_T_16905, _T_16907) @[ifu_bp_ctl.scala 444:22] + node _T_16909 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16910 = eq(_T_16909, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_16911 = or(_T_16910, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16912 = and(_T_16908, _T_16911) @[ifu_bp_ctl.scala 444:87] + node _T_16913 = or(_T_16904, _T_16912) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][5][1] <= _T_16913 @[ifu_bp_ctl.scala 443:27] + node _T_16914 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16915 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16916 = eq(_T_16915, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_16917 = and(_T_16914, _T_16916) @[ifu_bp_ctl.scala 443:45] + node _T_16918 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16919 = eq(_T_16918, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_16920 = or(_T_16919, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16921 = and(_T_16917, _T_16920) @[ifu_bp_ctl.scala 443:110] + node _T_16922 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16923 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16924 = eq(_T_16923, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_16925 = and(_T_16922, _T_16924) @[ifu_bp_ctl.scala 444:22] + node _T_16926 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16927 = eq(_T_16926, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_16928 = or(_T_16927, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16929 = and(_T_16925, _T_16928) @[ifu_bp_ctl.scala 444:87] + node _T_16930 = or(_T_16921, _T_16929) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][5][2] <= _T_16930 @[ifu_bp_ctl.scala 443:27] + node _T_16931 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16932 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16933 = eq(_T_16932, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_16934 = and(_T_16931, _T_16933) @[ifu_bp_ctl.scala 443:45] + node _T_16935 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16936 = eq(_T_16935, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_16937 = or(_T_16936, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16938 = and(_T_16934, _T_16937) @[ifu_bp_ctl.scala 443:110] + node _T_16939 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16940 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16941 = eq(_T_16940, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_16942 = and(_T_16939, _T_16941) @[ifu_bp_ctl.scala 444:22] + node _T_16943 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16944 = eq(_T_16943, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_16945 = or(_T_16944, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16946 = and(_T_16942, _T_16945) @[ifu_bp_ctl.scala 444:87] + node _T_16947 = or(_T_16938, _T_16946) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][5][3] <= _T_16947 @[ifu_bp_ctl.scala 443:27] + node _T_16948 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16949 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16950 = eq(_T_16949, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_16951 = and(_T_16948, _T_16950) @[ifu_bp_ctl.scala 443:45] + node _T_16952 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16953 = eq(_T_16952, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_16954 = or(_T_16953, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16955 = and(_T_16951, _T_16954) @[ifu_bp_ctl.scala 443:110] + node _T_16956 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16957 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16958 = eq(_T_16957, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_16959 = and(_T_16956, _T_16958) @[ifu_bp_ctl.scala 444:22] + node _T_16960 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16961 = eq(_T_16960, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_16962 = or(_T_16961, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16963 = and(_T_16959, _T_16962) @[ifu_bp_ctl.scala 444:87] + node _T_16964 = or(_T_16955, _T_16963) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][5][4] <= _T_16964 @[ifu_bp_ctl.scala 443:27] + node _T_16965 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16966 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16967 = eq(_T_16966, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_16968 = and(_T_16965, _T_16967) @[ifu_bp_ctl.scala 443:45] + node _T_16969 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16970 = eq(_T_16969, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_16971 = or(_T_16970, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16972 = and(_T_16968, _T_16971) @[ifu_bp_ctl.scala 443:110] + node _T_16973 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16974 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16975 = eq(_T_16974, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_16976 = and(_T_16973, _T_16975) @[ifu_bp_ctl.scala 444:22] + node _T_16977 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16978 = eq(_T_16977, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_16979 = or(_T_16978, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16980 = and(_T_16976, _T_16979) @[ifu_bp_ctl.scala 444:87] + node _T_16981 = or(_T_16972, _T_16980) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][5][5] <= _T_16981 @[ifu_bp_ctl.scala 443:27] + node _T_16982 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_16983 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_16984 = eq(_T_16983, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_16985 = and(_T_16982, _T_16984) @[ifu_bp_ctl.scala 443:45] + node _T_16986 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_16987 = eq(_T_16986, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_16988 = or(_T_16987, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_16989 = and(_T_16985, _T_16988) @[ifu_bp_ctl.scala 443:110] + node _T_16990 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_16991 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_16992 = eq(_T_16991, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_16993 = and(_T_16990, _T_16992) @[ifu_bp_ctl.scala 444:22] + node _T_16994 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_16995 = eq(_T_16994, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_16996 = or(_T_16995, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_16997 = and(_T_16993, _T_16996) @[ifu_bp_ctl.scala 444:87] + node _T_16998 = or(_T_16989, _T_16997) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][5][6] <= _T_16998 @[ifu_bp_ctl.scala 443:27] + node _T_16999 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17000 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17001 = eq(_T_17000, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_17002 = and(_T_16999, _T_17001) @[ifu_bp_ctl.scala 443:45] + node _T_17003 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17004 = eq(_T_17003, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_17005 = or(_T_17004, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17006 = and(_T_17002, _T_17005) @[ifu_bp_ctl.scala 443:110] + node _T_17007 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17008 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17009 = eq(_T_17008, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_17010 = and(_T_17007, _T_17009) @[ifu_bp_ctl.scala 444:22] + node _T_17011 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17012 = eq(_T_17011, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_17013 = or(_T_17012, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17014 = and(_T_17010, _T_17013) @[ifu_bp_ctl.scala 444:87] + node _T_17015 = or(_T_17006, _T_17014) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][5][7] <= _T_17015 @[ifu_bp_ctl.scala 443:27] + node _T_17016 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17017 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17018 = eq(_T_17017, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_17019 = and(_T_17016, _T_17018) @[ifu_bp_ctl.scala 443:45] + node _T_17020 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17021 = eq(_T_17020, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_17022 = or(_T_17021, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17023 = and(_T_17019, _T_17022) @[ifu_bp_ctl.scala 443:110] + node _T_17024 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17025 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17026 = eq(_T_17025, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_17027 = and(_T_17024, _T_17026) @[ifu_bp_ctl.scala 444:22] + node _T_17028 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17029 = eq(_T_17028, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_17030 = or(_T_17029, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17031 = and(_T_17027, _T_17030) @[ifu_bp_ctl.scala 444:87] + node _T_17032 = or(_T_17023, _T_17031) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][5][8] <= _T_17032 @[ifu_bp_ctl.scala 443:27] + node _T_17033 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17034 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17035 = eq(_T_17034, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_17036 = and(_T_17033, _T_17035) @[ifu_bp_ctl.scala 443:45] + node _T_17037 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17038 = eq(_T_17037, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_17039 = or(_T_17038, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17040 = and(_T_17036, _T_17039) @[ifu_bp_ctl.scala 443:110] + node _T_17041 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17042 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17043 = eq(_T_17042, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_17044 = and(_T_17041, _T_17043) @[ifu_bp_ctl.scala 444:22] + node _T_17045 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17046 = eq(_T_17045, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_17047 = or(_T_17046, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17048 = and(_T_17044, _T_17047) @[ifu_bp_ctl.scala 444:87] + node _T_17049 = or(_T_17040, _T_17048) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][5][9] <= _T_17049 @[ifu_bp_ctl.scala 443:27] + node _T_17050 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17051 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17052 = eq(_T_17051, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_17053 = and(_T_17050, _T_17052) @[ifu_bp_ctl.scala 443:45] + node _T_17054 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17055 = eq(_T_17054, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_17056 = or(_T_17055, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17057 = and(_T_17053, _T_17056) @[ifu_bp_ctl.scala 443:110] + node _T_17058 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17059 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17060 = eq(_T_17059, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_17061 = and(_T_17058, _T_17060) @[ifu_bp_ctl.scala 444:22] + node _T_17062 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17063 = eq(_T_17062, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_17064 = or(_T_17063, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17065 = and(_T_17061, _T_17064) @[ifu_bp_ctl.scala 444:87] + node _T_17066 = or(_T_17057, _T_17065) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][5][10] <= _T_17066 @[ifu_bp_ctl.scala 443:27] + node _T_17067 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17068 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17069 = eq(_T_17068, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_17070 = and(_T_17067, _T_17069) @[ifu_bp_ctl.scala 443:45] + node _T_17071 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17072 = eq(_T_17071, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_17073 = or(_T_17072, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17074 = and(_T_17070, _T_17073) @[ifu_bp_ctl.scala 443:110] + node _T_17075 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17076 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17077 = eq(_T_17076, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_17078 = and(_T_17075, _T_17077) @[ifu_bp_ctl.scala 444:22] + node _T_17079 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17080 = eq(_T_17079, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_17081 = or(_T_17080, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17082 = and(_T_17078, _T_17081) @[ifu_bp_ctl.scala 444:87] + node _T_17083 = or(_T_17074, _T_17082) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][5][11] <= _T_17083 @[ifu_bp_ctl.scala 443:27] + node _T_17084 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17085 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17086 = eq(_T_17085, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_17087 = and(_T_17084, _T_17086) @[ifu_bp_ctl.scala 443:45] + node _T_17088 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17089 = eq(_T_17088, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_17090 = or(_T_17089, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17091 = and(_T_17087, _T_17090) @[ifu_bp_ctl.scala 443:110] + node _T_17092 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17093 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17094 = eq(_T_17093, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_17095 = and(_T_17092, _T_17094) @[ifu_bp_ctl.scala 444:22] + node _T_17096 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17097 = eq(_T_17096, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_17098 = or(_T_17097, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17099 = and(_T_17095, _T_17098) @[ifu_bp_ctl.scala 444:87] + node _T_17100 = or(_T_17091, _T_17099) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][5][12] <= _T_17100 @[ifu_bp_ctl.scala 443:27] + node _T_17101 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17102 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17103 = eq(_T_17102, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_17104 = and(_T_17101, _T_17103) @[ifu_bp_ctl.scala 443:45] + node _T_17105 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17106 = eq(_T_17105, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_17107 = or(_T_17106, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17108 = and(_T_17104, _T_17107) @[ifu_bp_ctl.scala 443:110] + node _T_17109 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17110 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17111 = eq(_T_17110, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_17112 = and(_T_17109, _T_17111) @[ifu_bp_ctl.scala 444:22] + node _T_17113 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17114 = eq(_T_17113, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_17115 = or(_T_17114, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17116 = and(_T_17112, _T_17115) @[ifu_bp_ctl.scala 444:87] + node _T_17117 = or(_T_17108, _T_17116) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][5][13] <= _T_17117 @[ifu_bp_ctl.scala 443:27] + node _T_17118 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17119 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17120 = eq(_T_17119, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_17121 = and(_T_17118, _T_17120) @[ifu_bp_ctl.scala 443:45] + node _T_17122 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17123 = eq(_T_17122, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_17124 = or(_T_17123, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17125 = and(_T_17121, _T_17124) @[ifu_bp_ctl.scala 443:110] + node _T_17126 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17127 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17128 = eq(_T_17127, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_17129 = and(_T_17126, _T_17128) @[ifu_bp_ctl.scala 444:22] + node _T_17130 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17131 = eq(_T_17130, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_17132 = or(_T_17131, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17133 = and(_T_17129, _T_17132) @[ifu_bp_ctl.scala 444:87] + node _T_17134 = or(_T_17125, _T_17133) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][5][14] <= _T_17134 @[ifu_bp_ctl.scala 443:27] + node _T_17135 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17136 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17137 = eq(_T_17136, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_17138 = and(_T_17135, _T_17137) @[ifu_bp_ctl.scala 443:45] + node _T_17139 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17140 = eq(_T_17139, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:186] + node _T_17141 = or(_T_17140, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17142 = and(_T_17138, _T_17141) @[ifu_bp_ctl.scala 443:110] + node _T_17143 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17144 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17145 = eq(_T_17144, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_17146 = and(_T_17143, _T_17145) @[ifu_bp_ctl.scala 444:22] + node _T_17147 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17148 = eq(_T_17147, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:163] + node _T_17149 = or(_T_17148, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17150 = and(_T_17146, _T_17149) @[ifu_bp_ctl.scala 444:87] + node _T_17151 = or(_T_17142, _T_17150) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][5][15] <= _T_17151 @[ifu_bp_ctl.scala 443:27] + node _T_17152 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17153 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17154 = eq(_T_17153, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_17155 = and(_T_17152, _T_17154) @[ifu_bp_ctl.scala 443:45] + node _T_17156 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17157 = eq(_T_17156, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_17158 = or(_T_17157, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17159 = and(_T_17155, _T_17158) @[ifu_bp_ctl.scala 443:110] + node _T_17160 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17161 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17162 = eq(_T_17161, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_17163 = and(_T_17160, _T_17162) @[ifu_bp_ctl.scala 444:22] + node _T_17164 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17165 = eq(_T_17164, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_17166 = or(_T_17165, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17167 = and(_T_17163, _T_17166) @[ifu_bp_ctl.scala 444:87] + node _T_17168 = or(_T_17159, _T_17167) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][6][0] <= _T_17168 @[ifu_bp_ctl.scala 443:27] + node _T_17169 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17170 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17171 = eq(_T_17170, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_17172 = and(_T_17169, _T_17171) @[ifu_bp_ctl.scala 443:45] + node _T_17173 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17174 = eq(_T_17173, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_17175 = or(_T_17174, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17176 = and(_T_17172, _T_17175) @[ifu_bp_ctl.scala 443:110] + node _T_17177 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17178 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17179 = eq(_T_17178, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_17180 = and(_T_17177, _T_17179) @[ifu_bp_ctl.scala 444:22] + node _T_17181 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17182 = eq(_T_17181, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_17183 = or(_T_17182, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17184 = and(_T_17180, _T_17183) @[ifu_bp_ctl.scala 444:87] + node _T_17185 = or(_T_17176, _T_17184) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][6][1] <= _T_17185 @[ifu_bp_ctl.scala 443:27] + node _T_17186 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17187 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17188 = eq(_T_17187, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_17189 = and(_T_17186, _T_17188) @[ifu_bp_ctl.scala 443:45] + node _T_17190 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17191 = eq(_T_17190, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_17192 = or(_T_17191, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17193 = and(_T_17189, _T_17192) @[ifu_bp_ctl.scala 443:110] + node _T_17194 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17195 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17196 = eq(_T_17195, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_17197 = and(_T_17194, _T_17196) @[ifu_bp_ctl.scala 444:22] + node _T_17198 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17199 = eq(_T_17198, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_17200 = or(_T_17199, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17201 = and(_T_17197, _T_17200) @[ifu_bp_ctl.scala 444:87] + node _T_17202 = or(_T_17193, _T_17201) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][6][2] <= _T_17202 @[ifu_bp_ctl.scala 443:27] + node _T_17203 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17204 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17205 = eq(_T_17204, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_17206 = and(_T_17203, _T_17205) @[ifu_bp_ctl.scala 443:45] + node _T_17207 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17208 = eq(_T_17207, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_17209 = or(_T_17208, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17210 = and(_T_17206, _T_17209) @[ifu_bp_ctl.scala 443:110] + node _T_17211 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17212 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17213 = eq(_T_17212, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_17214 = and(_T_17211, _T_17213) @[ifu_bp_ctl.scala 444:22] + node _T_17215 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17216 = eq(_T_17215, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_17217 = or(_T_17216, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17218 = and(_T_17214, _T_17217) @[ifu_bp_ctl.scala 444:87] + node _T_17219 = or(_T_17210, _T_17218) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][6][3] <= _T_17219 @[ifu_bp_ctl.scala 443:27] + node _T_17220 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17221 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17222 = eq(_T_17221, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_17223 = and(_T_17220, _T_17222) @[ifu_bp_ctl.scala 443:45] + node _T_17224 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17225 = eq(_T_17224, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_17226 = or(_T_17225, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17227 = and(_T_17223, _T_17226) @[ifu_bp_ctl.scala 443:110] + node _T_17228 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17229 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17230 = eq(_T_17229, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_17231 = and(_T_17228, _T_17230) @[ifu_bp_ctl.scala 444:22] + node _T_17232 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17233 = eq(_T_17232, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_17234 = or(_T_17233, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17235 = and(_T_17231, _T_17234) @[ifu_bp_ctl.scala 444:87] + node _T_17236 = or(_T_17227, _T_17235) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][6][4] <= _T_17236 @[ifu_bp_ctl.scala 443:27] + node _T_17237 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17238 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17239 = eq(_T_17238, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_17240 = and(_T_17237, _T_17239) @[ifu_bp_ctl.scala 443:45] + node _T_17241 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17242 = eq(_T_17241, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_17243 = or(_T_17242, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17244 = and(_T_17240, _T_17243) @[ifu_bp_ctl.scala 443:110] + node _T_17245 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17246 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17247 = eq(_T_17246, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_17248 = and(_T_17245, _T_17247) @[ifu_bp_ctl.scala 444:22] + node _T_17249 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17250 = eq(_T_17249, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_17251 = or(_T_17250, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17252 = and(_T_17248, _T_17251) @[ifu_bp_ctl.scala 444:87] + node _T_17253 = or(_T_17244, _T_17252) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][6][5] <= _T_17253 @[ifu_bp_ctl.scala 443:27] + node _T_17254 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17255 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17256 = eq(_T_17255, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_17257 = and(_T_17254, _T_17256) @[ifu_bp_ctl.scala 443:45] + node _T_17258 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17259 = eq(_T_17258, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_17260 = or(_T_17259, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17261 = and(_T_17257, _T_17260) @[ifu_bp_ctl.scala 443:110] + node _T_17262 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17263 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17264 = eq(_T_17263, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_17265 = and(_T_17262, _T_17264) @[ifu_bp_ctl.scala 444:22] + node _T_17266 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17267 = eq(_T_17266, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_17268 = or(_T_17267, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17269 = and(_T_17265, _T_17268) @[ifu_bp_ctl.scala 444:87] + node _T_17270 = or(_T_17261, _T_17269) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][6][6] <= _T_17270 @[ifu_bp_ctl.scala 443:27] + node _T_17271 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17272 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17273 = eq(_T_17272, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_17274 = and(_T_17271, _T_17273) @[ifu_bp_ctl.scala 443:45] + node _T_17275 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17276 = eq(_T_17275, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_17277 = or(_T_17276, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17278 = and(_T_17274, _T_17277) @[ifu_bp_ctl.scala 443:110] + node _T_17279 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17280 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17281 = eq(_T_17280, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_17282 = and(_T_17279, _T_17281) @[ifu_bp_ctl.scala 444:22] + node _T_17283 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17284 = eq(_T_17283, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_17285 = or(_T_17284, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17286 = and(_T_17282, _T_17285) @[ifu_bp_ctl.scala 444:87] + node _T_17287 = or(_T_17278, _T_17286) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][6][7] <= _T_17287 @[ifu_bp_ctl.scala 443:27] + node _T_17288 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17289 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17290 = eq(_T_17289, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_17291 = and(_T_17288, _T_17290) @[ifu_bp_ctl.scala 443:45] + node _T_17292 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17293 = eq(_T_17292, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_17294 = or(_T_17293, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17295 = and(_T_17291, _T_17294) @[ifu_bp_ctl.scala 443:110] + node _T_17296 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17297 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17298 = eq(_T_17297, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_17299 = and(_T_17296, _T_17298) @[ifu_bp_ctl.scala 444:22] + node _T_17300 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17301 = eq(_T_17300, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_17302 = or(_T_17301, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17303 = and(_T_17299, _T_17302) @[ifu_bp_ctl.scala 444:87] + node _T_17304 = or(_T_17295, _T_17303) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][6][8] <= _T_17304 @[ifu_bp_ctl.scala 443:27] + node _T_17305 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17306 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17307 = eq(_T_17306, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_17308 = and(_T_17305, _T_17307) @[ifu_bp_ctl.scala 443:45] + node _T_17309 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17310 = eq(_T_17309, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_17311 = or(_T_17310, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17312 = and(_T_17308, _T_17311) @[ifu_bp_ctl.scala 443:110] + node _T_17313 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17314 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17315 = eq(_T_17314, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_17316 = and(_T_17313, _T_17315) @[ifu_bp_ctl.scala 444:22] + node _T_17317 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17318 = eq(_T_17317, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_17319 = or(_T_17318, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17320 = and(_T_17316, _T_17319) @[ifu_bp_ctl.scala 444:87] + node _T_17321 = or(_T_17312, _T_17320) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][6][9] <= _T_17321 @[ifu_bp_ctl.scala 443:27] + node _T_17322 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17323 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17324 = eq(_T_17323, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_17325 = and(_T_17322, _T_17324) @[ifu_bp_ctl.scala 443:45] + node _T_17326 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17327 = eq(_T_17326, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_17328 = or(_T_17327, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17329 = and(_T_17325, _T_17328) @[ifu_bp_ctl.scala 443:110] + node _T_17330 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17331 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17332 = eq(_T_17331, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_17333 = and(_T_17330, _T_17332) @[ifu_bp_ctl.scala 444:22] + node _T_17334 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17335 = eq(_T_17334, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_17336 = or(_T_17335, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17337 = and(_T_17333, _T_17336) @[ifu_bp_ctl.scala 444:87] + node _T_17338 = or(_T_17329, _T_17337) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][6][10] <= _T_17338 @[ifu_bp_ctl.scala 443:27] + node _T_17339 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17340 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17341 = eq(_T_17340, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_17342 = and(_T_17339, _T_17341) @[ifu_bp_ctl.scala 443:45] + node _T_17343 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17344 = eq(_T_17343, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_17345 = or(_T_17344, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17346 = and(_T_17342, _T_17345) @[ifu_bp_ctl.scala 443:110] + node _T_17347 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17348 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17349 = eq(_T_17348, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_17350 = and(_T_17347, _T_17349) @[ifu_bp_ctl.scala 444:22] + node _T_17351 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17352 = eq(_T_17351, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_17353 = or(_T_17352, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17354 = and(_T_17350, _T_17353) @[ifu_bp_ctl.scala 444:87] + node _T_17355 = or(_T_17346, _T_17354) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][6][11] <= _T_17355 @[ifu_bp_ctl.scala 443:27] + node _T_17356 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17357 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17358 = eq(_T_17357, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_17359 = and(_T_17356, _T_17358) @[ifu_bp_ctl.scala 443:45] + node _T_17360 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17361 = eq(_T_17360, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_17362 = or(_T_17361, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17363 = and(_T_17359, _T_17362) @[ifu_bp_ctl.scala 443:110] + node _T_17364 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17365 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17366 = eq(_T_17365, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_17367 = and(_T_17364, _T_17366) @[ifu_bp_ctl.scala 444:22] + node _T_17368 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17369 = eq(_T_17368, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_17370 = or(_T_17369, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17371 = and(_T_17367, _T_17370) @[ifu_bp_ctl.scala 444:87] + node _T_17372 = or(_T_17363, _T_17371) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][6][12] <= _T_17372 @[ifu_bp_ctl.scala 443:27] + node _T_17373 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17374 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17375 = eq(_T_17374, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_17376 = and(_T_17373, _T_17375) @[ifu_bp_ctl.scala 443:45] + node _T_17377 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17378 = eq(_T_17377, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_17379 = or(_T_17378, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17380 = and(_T_17376, _T_17379) @[ifu_bp_ctl.scala 443:110] + node _T_17381 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17382 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17383 = eq(_T_17382, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_17384 = and(_T_17381, _T_17383) @[ifu_bp_ctl.scala 444:22] + node _T_17385 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17386 = eq(_T_17385, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_17387 = or(_T_17386, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17388 = and(_T_17384, _T_17387) @[ifu_bp_ctl.scala 444:87] + node _T_17389 = or(_T_17380, _T_17388) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][6][13] <= _T_17389 @[ifu_bp_ctl.scala 443:27] + node _T_17390 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17391 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17392 = eq(_T_17391, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_17393 = and(_T_17390, _T_17392) @[ifu_bp_ctl.scala 443:45] + node _T_17394 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17395 = eq(_T_17394, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_17396 = or(_T_17395, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17397 = and(_T_17393, _T_17396) @[ifu_bp_ctl.scala 443:110] + node _T_17398 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17399 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17400 = eq(_T_17399, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_17401 = and(_T_17398, _T_17400) @[ifu_bp_ctl.scala 444:22] + node _T_17402 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17403 = eq(_T_17402, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_17404 = or(_T_17403, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17405 = and(_T_17401, _T_17404) @[ifu_bp_ctl.scala 444:87] + node _T_17406 = or(_T_17397, _T_17405) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][6][14] <= _T_17406 @[ifu_bp_ctl.scala 443:27] + node _T_17407 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17408 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17409 = eq(_T_17408, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_17410 = and(_T_17407, _T_17409) @[ifu_bp_ctl.scala 443:45] + node _T_17411 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17412 = eq(_T_17411, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:186] + node _T_17413 = or(_T_17412, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17414 = and(_T_17410, _T_17413) @[ifu_bp_ctl.scala 443:110] + node _T_17415 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17416 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17417 = eq(_T_17416, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_17418 = and(_T_17415, _T_17417) @[ifu_bp_ctl.scala 444:22] + node _T_17419 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17420 = eq(_T_17419, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:163] + node _T_17421 = or(_T_17420, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17422 = and(_T_17418, _T_17421) @[ifu_bp_ctl.scala 444:87] + node _T_17423 = or(_T_17414, _T_17422) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][6][15] <= _T_17423 @[ifu_bp_ctl.scala 443:27] + node _T_17424 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17425 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17426 = eq(_T_17425, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_17427 = and(_T_17424, _T_17426) @[ifu_bp_ctl.scala 443:45] + node _T_17428 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17429 = eq(_T_17428, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_17430 = or(_T_17429, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17431 = and(_T_17427, _T_17430) @[ifu_bp_ctl.scala 443:110] + node _T_17432 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17433 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17434 = eq(_T_17433, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_17435 = and(_T_17432, _T_17434) @[ifu_bp_ctl.scala 444:22] + node _T_17436 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17437 = eq(_T_17436, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_17438 = or(_T_17437, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17439 = and(_T_17435, _T_17438) @[ifu_bp_ctl.scala 444:87] + node _T_17440 = or(_T_17431, _T_17439) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][7][0] <= _T_17440 @[ifu_bp_ctl.scala 443:27] + node _T_17441 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17442 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17443 = eq(_T_17442, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_17444 = and(_T_17441, _T_17443) @[ifu_bp_ctl.scala 443:45] + node _T_17445 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17446 = eq(_T_17445, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_17447 = or(_T_17446, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17448 = and(_T_17444, _T_17447) @[ifu_bp_ctl.scala 443:110] + node _T_17449 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17450 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17451 = eq(_T_17450, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_17452 = and(_T_17449, _T_17451) @[ifu_bp_ctl.scala 444:22] + node _T_17453 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17454 = eq(_T_17453, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_17455 = or(_T_17454, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17456 = and(_T_17452, _T_17455) @[ifu_bp_ctl.scala 444:87] + node _T_17457 = or(_T_17448, _T_17456) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][7][1] <= _T_17457 @[ifu_bp_ctl.scala 443:27] + node _T_17458 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17459 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17460 = eq(_T_17459, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_17461 = and(_T_17458, _T_17460) @[ifu_bp_ctl.scala 443:45] + node _T_17462 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17463 = eq(_T_17462, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_17464 = or(_T_17463, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17465 = and(_T_17461, _T_17464) @[ifu_bp_ctl.scala 443:110] + node _T_17466 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17467 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17468 = eq(_T_17467, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_17469 = and(_T_17466, _T_17468) @[ifu_bp_ctl.scala 444:22] + node _T_17470 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17471 = eq(_T_17470, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_17472 = or(_T_17471, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17473 = and(_T_17469, _T_17472) @[ifu_bp_ctl.scala 444:87] + node _T_17474 = or(_T_17465, _T_17473) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][7][2] <= _T_17474 @[ifu_bp_ctl.scala 443:27] + node _T_17475 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17476 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17477 = eq(_T_17476, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_17478 = and(_T_17475, _T_17477) @[ifu_bp_ctl.scala 443:45] + node _T_17479 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17480 = eq(_T_17479, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_17481 = or(_T_17480, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17482 = and(_T_17478, _T_17481) @[ifu_bp_ctl.scala 443:110] + node _T_17483 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17484 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17485 = eq(_T_17484, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_17486 = and(_T_17483, _T_17485) @[ifu_bp_ctl.scala 444:22] + node _T_17487 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17488 = eq(_T_17487, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_17489 = or(_T_17488, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17490 = and(_T_17486, _T_17489) @[ifu_bp_ctl.scala 444:87] + node _T_17491 = or(_T_17482, _T_17490) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][7][3] <= _T_17491 @[ifu_bp_ctl.scala 443:27] + node _T_17492 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17493 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17494 = eq(_T_17493, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_17495 = and(_T_17492, _T_17494) @[ifu_bp_ctl.scala 443:45] + node _T_17496 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17497 = eq(_T_17496, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_17498 = or(_T_17497, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17499 = and(_T_17495, _T_17498) @[ifu_bp_ctl.scala 443:110] + node _T_17500 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17501 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17502 = eq(_T_17501, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_17503 = and(_T_17500, _T_17502) @[ifu_bp_ctl.scala 444:22] + node _T_17504 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17505 = eq(_T_17504, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_17506 = or(_T_17505, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17507 = and(_T_17503, _T_17506) @[ifu_bp_ctl.scala 444:87] + node _T_17508 = or(_T_17499, _T_17507) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][7][4] <= _T_17508 @[ifu_bp_ctl.scala 443:27] + node _T_17509 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17510 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17511 = eq(_T_17510, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_17512 = and(_T_17509, _T_17511) @[ifu_bp_ctl.scala 443:45] + node _T_17513 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17514 = eq(_T_17513, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_17515 = or(_T_17514, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17516 = and(_T_17512, _T_17515) @[ifu_bp_ctl.scala 443:110] + node _T_17517 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17518 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17519 = eq(_T_17518, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_17520 = and(_T_17517, _T_17519) @[ifu_bp_ctl.scala 444:22] + node _T_17521 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17522 = eq(_T_17521, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_17523 = or(_T_17522, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17524 = and(_T_17520, _T_17523) @[ifu_bp_ctl.scala 444:87] + node _T_17525 = or(_T_17516, _T_17524) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][7][5] <= _T_17525 @[ifu_bp_ctl.scala 443:27] + node _T_17526 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17527 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17528 = eq(_T_17527, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_17529 = and(_T_17526, _T_17528) @[ifu_bp_ctl.scala 443:45] + node _T_17530 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17531 = eq(_T_17530, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_17532 = or(_T_17531, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17533 = and(_T_17529, _T_17532) @[ifu_bp_ctl.scala 443:110] + node _T_17534 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17535 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17536 = eq(_T_17535, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_17537 = and(_T_17534, _T_17536) @[ifu_bp_ctl.scala 444:22] + node _T_17538 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17539 = eq(_T_17538, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_17540 = or(_T_17539, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17541 = and(_T_17537, _T_17540) @[ifu_bp_ctl.scala 444:87] + node _T_17542 = or(_T_17533, _T_17541) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][7][6] <= _T_17542 @[ifu_bp_ctl.scala 443:27] + node _T_17543 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17544 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17545 = eq(_T_17544, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_17546 = and(_T_17543, _T_17545) @[ifu_bp_ctl.scala 443:45] + node _T_17547 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17548 = eq(_T_17547, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_17549 = or(_T_17548, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17550 = and(_T_17546, _T_17549) @[ifu_bp_ctl.scala 443:110] + node _T_17551 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17552 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17553 = eq(_T_17552, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_17554 = and(_T_17551, _T_17553) @[ifu_bp_ctl.scala 444:22] + node _T_17555 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17556 = eq(_T_17555, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_17557 = or(_T_17556, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17558 = and(_T_17554, _T_17557) @[ifu_bp_ctl.scala 444:87] + node _T_17559 = or(_T_17550, _T_17558) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][7][7] <= _T_17559 @[ifu_bp_ctl.scala 443:27] + node _T_17560 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17561 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17562 = eq(_T_17561, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_17563 = and(_T_17560, _T_17562) @[ifu_bp_ctl.scala 443:45] + node _T_17564 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17565 = eq(_T_17564, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_17566 = or(_T_17565, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17567 = and(_T_17563, _T_17566) @[ifu_bp_ctl.scala 443:110] + node _T_17568 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17569 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17570 = eq(_T_17569, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_17571 = and(_T_17568, _T_17570) @[ifu_bp_ctl.scala 444:22] + node _T_17572 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17573 = eq(_T_17572, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_17574 = or(_T_17573, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17575 = and(_T_17571, _T_17574) @[ifu_bp_ctl.scala 444:87] + node _T_17576 = or(_T_17567, _T_17575) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][7][8] <= _T_17576 @[ifu_bp_ctl.scala 443:27] + node _T_17577 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17578 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17579 = eq(_T_17578, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_17580 = and(_T_17577, _T_17579) @[ifu_bp_ctl.scala 443:45] + node _T_17581 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17582 = eq(_T_17581, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_17583 = or(_T_17582, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17584 = and(_T_17580, _T_17583) @[ifu_bp_ctl.scala 443:110] + node _T_17585 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17586 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17587 = eq(_T_17586, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_17588 = and(_T_17585, _T_17587) @[ifu_bp_ctl.scala 444:22] + node _T_17589 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17590 = eq(_T_17589, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_17591 = or(_T_17590, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17592 = and(_T_17588, _T_17591) @[ifu_bp_ctl.scala 444:87] + node _T_17593 = or(_T_17584, _T_17592) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][7][9] <= _T_17593 @[ifu_bp_ctl.scala 443:27] + node _T_17594 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17595 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17596 = eq(_T_17595, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_17597 = and(_T_17594, _T_17596) @[ifu_bp_ctl.scala 443:45] + node _T_17598 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17599 = eq(_T_17598, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_17600 = or(_T_17599, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17601 = and(_T_17597, _T_17600) @[ifu_bp_ctl.scala 443:110] + node _T_17602 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17603 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17604 = eq(_T_17603, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_17605 = and(_T_17602, _T_17604) @[ifu_bp_ctl.scala 444:22] + node _T_17606 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17607 = eq(_T_17606, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_17608 = or(_T_17607, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17609 = and(_T_17605, _T_17608) @[ifu_bp_ctl.scala 444:87] + node _T_17610 = or(_T_17601, _T_17609) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][7][10] <= _T_17610 @[ifu_bp_ctl.scala 443:27] + node _T_17611 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17612 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17613 = eq(_T_17612, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_17614 = and(_T_17611, _T_17613) @[ifu_bp_ctl.scala 443:45] + node _T_17615 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17616 = eq(_T_17615, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_17617 = or(_T_17616, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17618 = and(_T_17614, _T_17617) @[ifu_bp_ctl.scala 443:110] + node _T_17619 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17620 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17621 = eq(_T_17620, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_17622 = and(_T_17619, _T_17621) @[ifu_bp_ctl.scala 444:22] + node _T_17623 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17624 = eq(_T_17623, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_17625 = or(_T_17624, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17626 = and(_T_17622, _T_17625) @[ifu_bp_ctl.scala 444:87] + node _T_17627 = or(_T_17618, _T_17626) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][7][11] <= _T_17627 @[ifu_bp_ctl.scala 443:27] + node _T_17628 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17629 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17630 = eq(_T_17629, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_17631 = and(_T_17628, _T_17630) @[ifu_bp_ctl.scala 443:45] + node _T_17632 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17633 = eq(_T_17632, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_17634 = or(_T_17633, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17635 = and(_T_17631, _T_17634) @[ifu_bp_ctl.scala 443:110] + node _T_17636 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17637 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17638 = eq(_T_17637, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_17639 = and(_T_17636, _T_17638) @[ifu_bp_ctl.scala 444:22] + node _T_17640 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17641 = eq(_T_17640, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_17642 = or(_T_17641, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17643 = and(_T_17639, _T_17642) @[ifu_bp_ctl.scala 444:87] + node _T_17644 = or(_T_17635, _T_17643) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][7][12] <= _T_17644 @[ifu_bp_ctl.scala 443:27] + node _T_17645 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17646 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17647 = eq(_T_17646, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_17648 = and(_T_17645, _T_17647) @[ifu_bp_ctl.scala 443:45] + node _T_17649 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17650 = eq(_T_17649, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_17651 = or(_T_17650, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17652 = and(_T_17648, _T_17651) @[ifu_bp_ctl.scala 443:110] + node _T_17653 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17654 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17655 = eq(_T_17654, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_17656 = and(_T_17653, _T_17655) @[ifu_bp_ctl.scala 444:22] + node _T_17657 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17658 = eq(_T_17657, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_17659 = or(_T_17658, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17660 = and(_T_17656, _T_17659) @[ifu_bp_ctl.scala 444:87] + node _T_17661 = or(_T_17652, _T_17660) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][7][13] <= _T_17661 @[ifu_bp_ctl.scala 443:27] + node _T_17662 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17663 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17664 = eq(_T_17663, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_17665 = and(_T_17662, _T_17664) @[ifu_bp_ctl.scala 443:45] + node _T_17666 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17667 = eq(_T_17666, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_17668 = or(_T_17667, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17669 = and(_T_17665, _T_17668) @[ifu_bp_ctl.scala 443:110] + node _T_17670 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17671 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17672 = eq(_T_17671, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_17673 = and(_T_17670, _T_17672) @[ifu_bp_ctl.scala 444:22] + node _T_17674 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17675 = eq(_T_17674, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_17676 = or(_T_17675, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17677 = and(_T_17673, _T_17676) @[ifu_bp_ctl.scala 444:87] + node _T_17678 = or(_T_17669, _T_17677) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][7][14] <= _T_17678 @[ifu_bp_ctl.scala 443:27] + node _T_17679 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17680 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17681 = eq(_T_17680, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_17682 = and(_T_17679, _T_17681) @[ifu_bp_ctl.scala 443:45] + node _T_17683 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17684 = eq(_T_17683, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:186] + node _T_17685 = or(_T_17684, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17686 = and(_T_17682, _T_17685) @[ifu_bp_ctl.scala 443:110] + node _T_17687 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17688 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17689 = eq(_T_17688, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_17690 = and(_T_17687, _T_17689) @[ifu_bp_ctl.scala 444:22] + node _T_17691 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17692 = eq(_T_17691, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:163] + node _T_17693 = or(_T_17692, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17694 = and(_T_17690, _T_17693) @[ifu_bp_ctl.scala 444:87] + node _T_17695 = or(_T_17686, _T_17694) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][7][15] <= _T_17695 @[ifu_bp_ctl.scala 443:27] + node _T_17696 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17697 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17698 = eq(_T_17697, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_17699 = and(_T_17696, _T_17698) @[ifu_bp_ctl.scala 443:45] + node _T_17700 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17701 = eq(_T_17700, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_17702 = or(_T_17701, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17703 = and(_T_17699, _T_17702) @[ifu_bp_ctl.scala 443:110] + node _T_17704 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17705 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17706 = eq(_T_17705, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_17707 = and(_T_17704, _T_17706) @[ifu_bp_ctl.scala 444:22] + node _T_17708 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17709 = eq(_T_17708, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_17710 = or(_T_17709, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17711 = and(_T_17707, _T_17710) @[ifu_bp_ctl.scala 444:87] + node _T_17712 = or(_T_17703, _T_17711) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][8][0] <= _T_17712 @[ifu_bp_ctl.scala 443:27] + node _T_17713 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17714 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17715 = eq(_T_17714, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_17716 = and(_T_17713, _T_17715) @[ifu_bp_ctl.scala 443:45] + node _T_17717 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17718 = eq(_T_17717, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_17719 = or(_T_17718, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17720 = and(_T_17716, _T_17719) @[ifu_bp_ctl.scala 443:110] + node _T_17721 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17722 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17723 = eq(_T_17722, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_17724 = and(_T_17721, _T_17723) @[ifu_bp_ctl.scala 444:22] + node _T_17725 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17726 = eq(_T_17725, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_17727 = or(_T_17726, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17728 = and(_T_17724, _T_17727) @[ifu_bp_ctl.scala 444:87] + node _T_17729 = or(_T_17720, _T_17728) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][8][1] <= _T_17729 @[ifu_bp_ctl.scala 443:27] + node _T_17730 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17731 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17732 = eq(_T_17731, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_17733 = and(_T_17730, _T_17732) @[ifu_bp_ctl.scala 443:45] + node _T_17734 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17735 = eq(_T_17734, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_17736 = or(_T_17735, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17737 = and(_T_17733, _T_17736) @[ifu_bp_ctl.scala 443:110] + node _T_17738 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17739 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17740 = eq(_T_17739, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_17741 = and(_T_17738, _T_17740) @[ifu_bp_ctl.scala 444:22] + node _T_17742 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17743 = eq(_T_17742, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_17744 = or(_T_17743, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17745 = and(_T_17741, _T_17744) @[ifu_bp_ctl.scala 444:87] + node _T_17746 = or(_T_17737, _T_17745) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][8][2] <= _T_17746 @[ifu_bp_ctl.scala 443:27] + node _T_17747 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17748 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17749 = eq(_T_17748, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_17750 = and(_T_17747, _T_17749) @[ifu_bp_ctl.scala 443:45] + node _T_17751 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17752 = eq(_T_17751, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_17753 = or(_T_17752, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17754 = and(_T_17750, _T_17753) @[ifu_bp_ctl.scala 443:110] + node _T_17755 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17756 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17757 = eq(_T_17756, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_17758 = and(_T_17755, _T_17757) @[ifu_bp_ctl.scala 444:22] + node _T_17759 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17760 = eq(_T_17759, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_17761 = or(_T_17760, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17762 = and(_T_17758, _T_17761) @[ifu_bp_ctl.scala 444:87] + node _T_17763 = or(_T_17754, _T_17762) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][8][3] <= _T_17763 @[ifu_bp_ctl.scala 443:27] + node _T_17764 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17765 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17766 = eq(_T_17765, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_17767 = and(_T_17764, _T_17766) @[ifu_bp_ctl.scala 443:45] + node _T_17768 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17769 = eq(_T_17768, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_17770 = or(_T_17769, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17771 = and(_T_17767, _T_17770) @[ifu_bp_ctl.scala 443:110] + node _T_17772 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17773 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17774 = eq(_T_17773, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_17775 = and(_T_17772, _T_17774) @[ifu_bp_ctl.scala 444:22] + node _T_17776 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17777 = eq(_T_17776, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_17778 = or(_T_17777, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17779 = and(_T_17775, _T_17778) @[ifu_bp_ctl.scala 444:87] + node _T_17780 = or(_T_17771, _T_17779) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][8][4] <= _T_17780 @[ifu_bp_ctl.scala 443:27] + node _T_17781 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17782 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17783 = eq(_T_17782, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_17784 = and(_T_17781, _T_17783) @[ifu_bp_ctl.scala 443:45] + node _T_17785 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17786 = eq(_T_17785, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_17787 = or(_T_17786, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17788 = and(_T_17784, _T_17787) @[ifu_bp_ctl.scala 443:110] + node _T_17789 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17790 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17791 = eq(_T_17790, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_17792 = and(_T_17789, _T_17791) @[ifu_bp_ctl.scala 444:22] + node _T_17793 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17794 = eq(_T_17793, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_17795 = or(_T_17794, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17796 = and(_T_17792, _T_17795) @[ifu_bp_ctl.scala 444:87] + node _T_17797 = or(_T_17788, _T_17796) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][8][5] <= _T_17797 @[ifu_bp_ctl.scala 443:27] + node _T_17798 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17799 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17800 = eq(_T_17799, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_17801 = and(_T_17798, _T_17800) @[ifu_bp_ctl.scala 443:45] + node _T_17802 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17803 = eq(_T_17802, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_17804 = or(_T_17803, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17805 = and(_T_17801, _T_17804) @[ifu_bp_ctl.scala 443:110] + node _T_17806 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17807 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17808 = eq(_T_17807, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_17809 = and(_T_17806, _T_17808) @[ifu_bp_ctl.scala 444:22] + node _T_17810 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17811 = eq(_T_17810, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_17812 = or(_T_17811, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17813 = and(_T_17809, _T_17812) @[ifu_bp_ctl.scala 444:87] + node _T_17814 = or(_T_17805, _T_17813) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][8][6] <= _T_17814 @[ifu_bp_ctl.scala 443:27] + node _T_17815 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17816 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17817 = eq(_T_17816, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_17818 = and(_T_17815, _T_17817) @[ifu_bp_ctl.scala 443:45] + node _T_17819 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17820 = eq(_T_17819, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_17821 = or(_T_17820, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17822 = and(_T_17818, _T_17821) @[ifu_bp_ctl.scala 443:110] + node _T_17823 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17824 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17825 = eq(_T_17824, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_17826 = and(_T_17823, _T_17825) @[ifu_bp_ctl.scala 444:22] + node _T_17827 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17828 = eq(_T_17827, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_17829 = or(_T_17828, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17830 = and(_T_17826, _T_17829) @[ifu_bp_ctl.scala 444:87] + node _T_17831 = or(_T_17822, _T_17830) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][8][7] <= _T_17831 @[ifu_bp_ctl.scala 443:27] + node _T_17832 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17833 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17834 = eq(_T_17833, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_17835 = and(_T_17832, _T_17834) @[ifu_bp_ctl.scala 443:45] + node _T_17836 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17837 = eq(_T_17836, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_17838 = or(_T_17837, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17839 = and(_T_17835, _T_17838) @[ifu_bp_ctl.scala 443:110] + node _T_17840 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17841 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17842 = eq(_T_17841, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_17843 = and(_T_17840, _T_17842) @[ifu_bp_ctl.scala 444:22] + node _T_17844 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17845 = eq(_T_17844, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_17846 = or(_T_17845, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17847 = and(_T_17843, _T_17846) @[ifu_bp_ctl.scala 444:87] + node _T_17848 = or(_T_17839, _T_17847) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][8][8] <= _T_17848 @[ifu_bp_ctl.scala 443:27] + node _T_17849 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17850 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17851 = eq(_T_17850, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_17852 = and(_T_17849, _T_17851) @[ifu_bp_ctl.scala 443:45] + node _T_17853 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17854 = eq(_T_17853, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_17855 = or(_T_17854, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17856 = and(_T_17852, _T_17855) @[ifu_bp_ctl.scala 443:110] + node _T_17857 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17858 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17859 = eq(_T_17858, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_17860 = and(_T_17857, _T_17859) @[ifu_bp_ctl.scala 444:22] + node _T_17861 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17862 = eq(_T_17861, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_17863 = or(_T_17862, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17864 = and(_T_17860, _T_17863) @[ifu_bp_ctl.scala 444:87] + node _T_17865 = or(_T_17856, _T_17864) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][8][9] <= _T_17865 @[ifu_bp_ctl.scala 443:27] + node _T_17866 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17867 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17868 = eq(_T_17867, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_17869 = and(_T_17866, _T_17868) @[ifu_bp_ctl.scala 443:45] + node _T_17870 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17871 = eq(_T_17870, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_17872 = or(_T_17871, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17873 = and(_T_17869, _T_17872) @[ifu_bp_ctl.scala 443:110] + node _T_17874 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17875 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17876 = eq(_T_17875, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_17877 = and(_T_17874, _T_17876) @[ifu_bp_ctl.scala 444:22] + node _T_17878 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17879 = eq(_T_17878, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_17880 = or(_T_17879, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17881 = and(_T_17877, _T_17880) @[ifu_bp_ctl.scala 444:87] + node _T_17882 = or(_T_17873, _T_17881) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][8][10] <= _T_17882 @[ifu_bp_ctl.scala 443:27] + node _T_17883 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17884 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17885 = eq(_T_17884, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_17886 = and(_T_17883, _T_17885) @[ifu_bp_ctl.scala 443:45] + node _T_17887 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17888 = eq(_T_17887, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_17889 = or(_T_17888, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17890 = and(_T_17886, _T_17889) @[ifu_bp_ctl.scala 443:110] + node _T_17891 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17892 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17893 = eq(_T_17892, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_17894 = and(_T_17891, _T_17893) @[ifu_bp_ctl.scala 444:22] + node _T_17895 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17896 = eq(_T_17895, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_17897 = or(_T_17896, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17898 = and(_T_17894, _T_17897) @[ifu_bp_ctl.scala 444:87] + node _T_17899 = or(_T_17890, _T_17898) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][8][11] <= _T_17899 @[ifu_bp_ctl.scala 443:27] + node _T_17900 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17901 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17902 = eq(_T_17901, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_17903 = and(_T_17900, _T_17902) @[ifu_bp_ctl.scala 443:45] + node _T_17904 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17905 = eq(_T_17904, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_17906 = or(_T_17905, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17907 = and(_T_17903, _T_17906) @[ifu_bp_ctl.scala 443:110] + node _T_17908 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17909 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17910 = eq(_T_17909, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_17911 = and(_T_17908, _T_17910) @[ifu_bp_ctl.scala 444:22] + node _T_17912 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17913 = eq(_T_17912, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_17914 = or(_T_17913, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17915 = and(_T_17911, _T_17914) @[ifu_bp_ctl.scala 444:87] + node _T_17916 = or(_T_17907, _T_17915) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][8][12] <= _T_17916 @[ifu_bp_ctl.scala 443:27] + node _T_17917 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17918 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17919 = eq(_T_17918, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_17920 = and(_T_17917, _T_17919) @[ifu_bp_ctl.scala 443:45] + node _T_17921 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17922 = eq(_T_17921, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_17923 = or(_T_17922, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17924 = and(_T_17920, _T_17923) @[ifu_bp_ctl.scala 443:110] + node _T_17925 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17926 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17927 = eq(_T_17926, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_17928 = and(_T_17925, _T_17927) @[ifu_bp_ctl.scala 444:22] + node _T_17929 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17930 = eq(_T_17929, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_17931 = or(_T_17930, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17932 = and(_T_17928, _T_17931) @[ifu_bp_ctl.scala 444:87] + node _T_17933 = or(_T_17924, _T_17932) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][8][13] <= _T_17933 @[ifu_bp_ctl.scala 443:27] + node _T_17934 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17935 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17936 = eq(_T_17935, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_17937 = and(_T_17934, _T_17936) @[ifu_bp_ctl.scala 443:45] + node _T_17938 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17939 = eq(_T_17938, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_17940 = or(_T_17939, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17941 = and(_T_17937, _T_17940) @[ifu_bp_ctl.scala 443:110] + node _T_17942 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17943 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17944 = eq(_T_17943, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_17945 = and(_T_17942, _T_17944) @[ifu_bp_ctl.scala 444:22] + node _T_17946 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17947 = eq(_T_17946, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_17948 = or(_T_17947, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17949 = and(_T_17945, _T_17948) @[ifu_bp_ctl.scala 444:87] + node _T_17950 = or(_T_17941, _T_17949) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][8][14] <= _T_17950 @[ifu_bp_ctl.scala 443:27] + node _T_17951 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17952 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17953 = eq(_T_17952, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_17954 = and(_T_17951, _T_17953) @[ifu_bp_ctl.scala 443:45] + node _T_17955 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17956 = eq(_T_17955, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:186] + node _T_17957 = or(_T_17956, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17958 = and(_T_17954, _T_17957) @[ifu_bp_ctl.scala 443:110] + node _T_17959 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17960 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17961 = eq(_T_17960, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_17962 = and(_T_17959, _T_17961) @[ifu_bp_ctl.scala 444:22] + node _T_17963 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17964 = eq(_T_17963, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:163] + node _T_17965 = or(_T_17964, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17966 = and(_T_17962, _T_17965) @[ifu_bp_ctl.scala 444:87] + node _T_17967 = or(_T_17958, _T_17966) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][8][15] <= _T_17967 @[ifu_bp_ctl.scala 443:27] + node _T_17968 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17969 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17970 = eq(_T_17969, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_17971 = and(_T_17968, _T_17970) @[ifu_bp_ctl.scala 443:45] + node _T_17972 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17973 = eq(_T_17972, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_17974 = or(_T_17973, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17975 = and(_T_17971, _T_17974) @[ifu_bp_ctl.scala 443:110] + node _T_17976 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17977 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17978 = eq(_T_17977, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_17979 = and(_T_17976, _T_17978) @[ifu_bp_ctl.scala 444:22] + node _T_17980 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17981 = eq(_T_17980, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_17982 = or(_T_17981, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_17983 = and(_T_17979, _T_17982) @[ifu_bp_ctl.scala 444:87] + node _T_17984 = or(_T_17975, _T_17983) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][9][0] <= _T_17984 @[ifu_bp_ctl.scala 443:27] + node _T_17985 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_17986 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_17987 = eq(_T_17986, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_17988 = and(_T_17985, _T_17987) @[ifu_bp_ctl.scala 443:45] + node _T_17989 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_17990 = eq(_T_17989, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_17991 = or(_T_17990, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_17992 = and(_T_17988, _T_17991) @[ifu_bp_ctl.scala 443:110] + node _T_17993 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_17994 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_17995 = eq(_T_17994, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_17996 = and(_T_17993, _T_17995) @[ifu_bp_ctl.scala 444:22] + node _T_17997 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_17998 = eq(_T_17997, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_17999 = or(_T_17998, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18000 = and(_T_17996, _T_17999) @[ifu_bp_ctl.scala 444:87] + node _T_18001 = or(_T_17992, _T_18000) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][9][1] <= _T_18001 @[ifu_bp_ctl.scala 443:27] + node _T_18002 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18003 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18004 = eq(_T_18003, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_18005 = and(_T_18002, _T_18004) @[ifu_bp_ctl.scala 443:45] + node _T_18006 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18007 = eq(_T_18006, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_18008 = or(_T_18007, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18009 = and(_T_18005, _T_18008) @[ifu_bp_ctl.scala 443:110] + node _T_18010 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18011 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18012 = eq(_T_18011, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_18013 = and(_T_18010, _T_18012) @[ifu_bp_ctl.scala 444:22] + node _T_18014 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18015 = eq(_T_18014, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_18016 = or(_T_18015, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18017 = and(_T_18013, _T_18016) @[ifu_bp_ctl.scala 444:87] + node _T_18018 = or(_T_18009, _T_18017) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][9][2] <= _T_18018 @[ifu_bp_ctl.scala 443:27] + node _T_18019 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18020 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18021 = eq(_T_18020, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_18022 = and(_T_18019, _T_18021) @[ifu_bp_ctl.scala 443:45] + node _T_18023 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18024 = eq(_T_18023, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_18025 = or(_T_18024, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18026 = and(_T_18022, _T_18025) @[ifu_bp_ctl.scala 443:110] + node _T_18027 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18028 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18029 = eq(_T_18028, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_18030 = and(_T_18027, _T_18029) @[ifu_bp_ctl.scala 444:22] + node _T_18031 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18032 = eq(_T_18031, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_18033 = or(_T_18032, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18034 = and(_T_18030, _T_18033) @[ifu_bp_ctl.scala 444:87] + node _T_18035 = or(_T_18026, _T_18034) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][9][3] <= _T_18035 @[ifu_bp_ctl.scala 443:27] + node _T_18036 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18037 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18038 = eq(_T_18037, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_18039 = and(_T_18036, _T_18038) @[ifu_bp_ctl.scala 443:45] + node _T_18040 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18041 = eq(_T_18040, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_18042 = or(_T_18041, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18043 = and(_T_18039, _T_18042) @[ifu_bp_ctl.scala 443:110] + node _T_18044 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18045 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18046 = eq(_T_18045, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_18047 = and(_T_18044, _T_18046) @[ifu_bp_ctl.scala 444:22] + node _T_18048 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18049 = eq(_T_18048, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_18050 = or(_T_18049, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18051 = and(_T_18047, _T_18050) @[ifu_bp_ctl.scala 444:87] + node _T_18052 = or(_T_18043, _T_18051) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][9][4] <= _T_18052 @[ifu_bp_ctl.scala 443:27] + node _T_18053 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18054 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18055 = eq(_T_18054, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_18056 = and(_T_18053, _T_18055) @[ifu_bp_ctl.scala 443:45] + node _T_18057 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18058 = eq(_T_18057, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_18059 = or(_T_18058, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18060 = and(_T_18056, _T_18059) @[ifu_bp_ctl.scala 443:110] + node _T_18061 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18062 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18063 = eq(_T_18062, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_18064 = and(_T_18061, _T_18063) @[ifu_bp_ctl.scala 444:22] + node _T_18065 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18066 = eq(_T_18065, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_18067 = or(_T_18066, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18068 = and(_T_18064, _T_18067) @[ifu_bp_ctl.scala 444:87] + node _T_18069 = or(_T_18060, _T_18068) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][9][5] <= _T_18069 @[ifu_bp_ctl.scala 443:27] + node _T_18070 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18071 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18072 = eq(_T_18071, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_18073 = and(_T_18070, _T_18072) @[ifu_bp_ctl.scala 443:45] + node _T_18074 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18075 = eq(_T_18074, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_18076 = or(_T_18075, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18077 = and(_T_18073, _T_18076) @[ifu_bp_ctl.scala 443:110] + node _T_18078 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18079 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18080 = eq(_T_18079, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_18081 = and(_T_18078, _T_18080) @[ifu_bp_ctl.scala 444:22] + node _T_18082 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18083 = eq(_T_18082, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_18084 = or(_T_18083, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18085 = and(_T_18081, _T_18084) @[ifu_bp_ctl.scala 444:87] + node _T_18086 = or(_T_18077, _T_18085) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][9][6] <= _T_18086 @[ifu_bp_ctl.scala 443:27] + node _T_18087 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18088 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18089 = eq(_T_18088, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_18090 = and(_T_18087, _T_18089) @[ifu_bp_ctl.scala 443:45] + node _T_18091 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18092 = eq(_T_18091, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_18093 = or(_T_18092, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18094 = and(_T_18090, _T_18093) @[ifu_bp_ctl.scala 443:110] + node _T_18095 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18096 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18097 = eq(_T_18096, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_18098 = and(_T_18095, _T_18097) @[ifu_bp_ctl.scala 444:22] + node _T_18099 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18100 = eq(_T_18099, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_18101 = or(_T_18100, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18102 = and(_T_18098, _T_18101) @[ifu_bp_ctl.scala 444:87] + node _T_18103 = or(_T_18094, _T_18102) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][9][7] <= _T_18103 @[ifu_bp_ctl.scala 443:27] + node _T_18104 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18105 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18106 = eq(_T_18105, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_18107 = and(_T_18104, _T_18106) @[ifu_bp_ctl.scala 443:45] + node _T_18108 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18109 = eq(_T_18108, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_18110 = or(_T_18109, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18111 = and(_T_18107, _T_18110) @[ifu_bp_ctl.scala 443:110] + node _T_18112 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18113 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18114 = eq(_T_18113, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_18115 = and(_T_18112, _T_18114) @[ifu_bp_ctl.scala 444:22] + node _T_18116 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18117 = eq(_T_18116, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_18118 = or(_T_18117, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18119 = and(_T_18115, _T_18118) @[ifu_bp_ctl.scala 444:87] + node _T_18120 = or(_T_18111, _T_18119) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][9][8] <= _T_18120 @[ifu_bp_ctl.scala 443:27] + node _T_18121 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18122 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18123 = eq(_T_18122, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_18124 = and(_T_18121, _T_18123) @[ifu_bp_ctl.scala 443:45] + node _T_18125 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18126 = eq(_T_18125, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_18127 = or(_T_18126, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18128 = and(_T_18124, _T_18127) @[ifu_bp_ctl.scala 443:110] + node _T_18129 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18130 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18131 = eq(_T_18130, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_18132 = and(_T_18129, _T_18131) @[ifu_bp_ctl.scala 444:22] + node _T_18133 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18134 = eq(_T_18133, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_18135 = or(_T_18134, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18136 = and(_T_18132, _T_18135) @[ifu_bp_ctl.scala 444:87] + node _T_18137 = or(_T_18128, _T_18136) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][9][9] <= _T_18137 @[ifu_bp_ctl.scala 443:27] + node _T_18138 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18139 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18140 = eq(_T_18139, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_18141 = and(_T_18138, _T_18140) @[ifu_bp_ctl.scala 443:45] + node _T_18142 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18143 = eq(_T_18142, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_18144 = or(_T_18143, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18145 = and(_T_18141, _T_18144) @[ifu_bp_ctl.scala 443:110] + node _T_18146 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18147 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18148 = eq(_T_18147, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_18149 = and(_T_18146, _T_18148) @[ifu_bp_ctl.scala 444:22] + node _T_18150 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18151 = eq(_T_18150, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_18152 = or(_T_18151, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18153 = and(_T_18149, _T_18152) @[ifu_bp_ctl.scala 444:87] + node _T_18154 = or(_T_18145, _T_18153) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][9][10] <= _T_18154 @[ifu_bp_ctl.scala 443:27] + node _T_18155 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18156 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18157 = eq(_T_18156, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_18158 = and(_T_18155, _T_18157) @[ifu_bp_ctl.scala 443:45] + node _T_18159 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18160 = eq(_T_18159, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_18161 = or(_T_18160, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18162 = and(_T_18158, _T_18161) @[ifu_bp_ctl.scala 443:110] + node _T_18163 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18164 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18165 = eq(_T_18164, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_18166 = and(_T_18163, _T_18165) @[ifu_bp_ctl.scala 444:22] + node _T_18167 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18168 = eq(_T_18167, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_18169 = or(_T_18168, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18170 = and(_T_18166, _T_18169) @[ifu_bp_ctl.scala 444:87] + node _T_18171 = or(_T_18162, _T_18170) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][9][11] <= _T_18171 @[ifu_bp_ctl.scala 443:27] + node _T_18172 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18173 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18174 = eq(_T_18173, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_18175 = and(_T_18172, _T_18174) @[ifu_bp_ctl.scala 443:45] + node _T_18176 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18177 = eq(_T_18176, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_18178 = or(_T_18177, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18179 = and(_T_18175, _T_18178) @[ifu_bp_ctl.scala 443:110] + node _T_18180 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18181 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18182 = eq(_T_18181, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_18183 = and(_T_18180, _T_18182) @[ifu_bp_ctl.scala 444:22] + node _T_18184 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18185 = eq(_T_18184, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_18186 = or(_T_18185, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18187 = and(_T_18183, _T_18186) @[ifu_bp_ctl.scala 444:87] + node _T_18188 = or(_T_18179, _T_18187) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][9][12] <= _T_18188 @[ifu_bp_ctl.scala 443:27] + node _T_18189 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18190 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18191 = eq(_T_18190, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_18192 = and(_T_18189, _T_18191) @[ifu_bp_ctl.scala 443:45] + node _T_18193 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18194 = eq(_T_18193, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_18195 = or(_T_18194, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18196 = and(_T_18192, _T_18195) @[ifu_bp_ctl.scala 443:110] + node _T_18197 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18198 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18199 = eq(_T_18198, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_18200 = and(_T_18197, _T_18199) @[ifu_bp_ctl.scala 444:22] + node _T_18201 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18202 = eq(_T_18201, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_18203 = or(_T_18202, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18204 = and(_T_18200, _T_18203) @[ifu_bp_ctl.scala 444:87] + node _T_18205 = or(_T_18196, _T_18204) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][9][13] <= _T_18205 @[ifu_bp_ctl.scala 443:27] + node _T_18206 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18207 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18208 = eq(_T_18207, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_18209 = and(_T_18206, _T_18208) @[ifu_bp_ctl.scala 443:45] + node _T_18210 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18211 = eq(_T_18210, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_18212 = or(_T_18211, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18213 = and(_T_18209, _T_18212) @[ifu_bp_ctl.scala 443:110] + node _T_18214 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18215 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18216 = eq(_T_18215, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_18217 = and(_T_18214, _T_18216) @[ifu_bp_ctl.scala 444:22] + node _T_18218 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18219 = eq(_T_18218, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_18220 = or(_T_18219, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18221 = and(_T_18217, _T_18220) @[ifu_bp_ctl.scala 444:87] + node _T_18222 = or(_T_18213, _T_18221) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][9][14] <= _T_18222 @[ifu_bp_ctl.scala 443:27] + node _T_18223 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18224 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18225 = eq(_T_18224, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_18226 = and(_T_18223, _T_18225) @[ifu_bp_ctl.scala 443:45] + node _T_18227 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18228 = eq(_T_18227, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:186] + node _T_18229 = or(_T_18228, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18230 = and(_T_18226, _T_18229) @[ifu_bp_ctl.scala 443:110] + node _T_18231 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18232 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18233 = eq(_T_18232, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_18234 = and(_T_18231, _T_18233) @[ifu_bp_ctl.scala 444:22] + node _T_18235 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18236 = eq(_T_18235, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:163] + node _T_18237 = or(_T_18236, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18238 = and(_T_18234, _T_18237) @[ifu_bp_ctl.scala 444:87] + node _T_18239 = or(_T_18230, _T_18238) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][9][15] <= _T_18239 @[ifu_bp_ctl.scala 443:27] + node _T_18240 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18241 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18242 = eq(_T_18241, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_18243 = and(_T_18240, _T_18242) @[ifu_bp_ctl.scala 443:45] + node _T_18244 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18245 = eq(_T_18244, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_18246 = or(_T_18245, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18247 = and(_T_18243, _T_18246) @[ifu_bp_ctl.scala 443:110] + node _T_18248 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18249 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18250 = eq(_T_18249, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_18251 = and(_T_18248, _T_18250) @[ifu_bp_ctl.scala 444:22] + node _T_18252 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18253 = eq(_T_18252, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_18254 = or(_T_18253, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18255 = and(_T_18251, _T_18254) @[ifu_bp_ctl.scala 444:87] + node _T_18256 = or(_T_18247, _T_18255) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][10][0] <= _T_18256 @[ifu_bp_ctl.scala 443:27] + node _T_18257 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18258 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18259 = eq(_T_18258, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_18260 = and(_T_18257, _T_18259) @[ifu_bp_ctl.scala 443:45] + node _T_18261 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18262 = eq(_T_18261, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_18263 = or(_T_18262, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18264 = and(_T_18260, _T_18263) @[ifu_bp_ctl.scala 443:110] + node _T_18265 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18266 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18267 = eq(_T_18266, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_18268 = and(_T_18265, _T_18267) @[ifu_bp_ctl.scala 444:22] + node _T_18269 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18270 = eq(_T_18269, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_18271 = or(_T_18270, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18272 = and(_T_18268, _T_18271) @[ifu_bp_ctl.scala 444:87] + node _T_18273 = or(_T_18264, _T_18272) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][10][1] <= _T_18273 @[ifu_bp_ctl.scala 443:27] + node _T_18274 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18275 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18276 = eq(_T_18275, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_18277 = and(_T_18274, _T_18276) @[ifu_bp_ctl.scala 443:45] + node _T_18278 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18279 = eq(_T_18278, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_18280 = or(_T_18279, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18281 = and(_T_18277, _T_18280) @[ifu_bp_ctl.scala 443:110] + node _T_18282 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18283 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18284 = eq(_T_18283, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_18285 = and(_T_18282, _T_18284) @[ifu_bp_ctl.scala 444:22] + node _T_18286 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18287 = eq(_T_18286, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_18288 = or(_T_18287, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18289 = and(_T_18285, _T_18288) @[ifu_bp_ctl.scala 444:87] + node _T_18290 = or(_T_18281, _T_18289) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][10][2] <= _T_18290 @[ifu_bp_ctl.scala 443:27] + node _T_18291 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18292 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18293 = eq(_T_18292, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_18294 = and(_T_18291, _T_18293) @[ifu_bp_ctl.scala 443:45] + node _T_18295 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18296 = eq(_T_18295, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_18297 = or(_T_18296, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18298 = and(_T_18294, _T_18297) @[ifu_bp_ctl.scala 443:110] + node _T_18299 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18300 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18301 = eq(_T_18300, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_18302 = and(_T_18299, _T_18301) @[ifu_bp_ctl.scala 444:22] + node _T_18303 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18304 = eq(_T_18303, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_18305 = or(_T_18304, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18306 = and(_T_18302, _T_18305) @[ifu_bp_ctl.scala 444:87] + node _T_18307 = or(_T_18298, _T_18306) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][10][3] <= _T_18307 @[ifu_bp_ctl.scala 443:27] + node _T_18308 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18309 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18310 = eq(_T_18309, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_18311 = and(_T_18308, _T_18310) @[ifu_bp_ctl.scala 443:45] + node _T_18312 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18313 = eq(_T_18312, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_18314 = or(_T_18313, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18315 = and(_T_18311, _T_18314) @[ifu_bp_ctl.scala 443:110] + node _T_18316 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18317 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18318 = eq(_T_18317, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_18319 = and(_T_18316, _T_18318) @[ifu_bp_ctl.scala 444:22] + node _T_18320 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18321 = eq(_T_18320, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_18322 = or(_T_18321, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18323 = and(_T_18319, _T_18322) @[ifu_bp_ctl.scala 444:87] + node _T_18324 = or(_T_18315, _T_18323) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][10][4] <= _T_18324 @[ifu_bp_ctl.scala 443:27] + node _T_18325 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18326 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18327 = eq(_T_18326, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_18328 = and(_T_18325, _T_18327) @[ifu_bp_ctl.scala 443:45] + node _T_18329 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18330 = eq(_T_18329, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_18331 = or(_T_18330, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18332 = and(_T_18328, _T_18331) @[ifu_bp_ctl.scala 443:110] + node _T_18333 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18334 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18335 = eq(_T_18334, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_18336 = and(_T_18333, _T_18335) @[ifu_bp_ctl.scala 444:22] + node _T_18337 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18338 = eq(_T_18337, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_18339 = or(_T_18338, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18340 = and(_T_18336, _T_18339) @[ifu_bp_ctl.scala 444:87] + node _T_18341 = or(_T_18332, _T_18340) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][10][5] <= _T_18341 @[ifu_bp_ctl.scala 443:27] + node _T_18342 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18343 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18344 = eq(_T_18343, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_18345 = and(_T_18342, _T_18344) @[ifu_bp_ctl.scala 443:45] + node _T_18346 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18347 = eq(_T_18346, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_18348 = or(_T_18347, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18349 = and(_T_18345, _T_18348) @[ifu_bp_ctl.scala 443:110] + node _T_18350 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18351 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18352 = eq(_T_18351, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_18353 = and(_T_18350, _T_18352) @[ifu_bp_ctl.scala 444:22] + node _T_18354 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18355 = eq(_T_18354, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_18356 = or(_T_18355, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18357 = and(_T_18353, _T_18356) @[ifu_bp_ctl.scala 444:87] + node _T_18358 = or(_T_18349, _T_18357) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][10][6] <= _T_18358 @[ifu_bp_ctl.scala 443:27] + node _T_18359 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18360 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18361 = eq(_T_18360, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_18362 = and(_T_18359, _T_18361) @[ifu_bp_ctl.scala 443:45] + node _T_18363 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18364 = eq(_T_18363, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_18365 = or(_T_18364, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18366 = and(_T_18362, _T_18365) @[ifu_bp_ctl.scala 443:110] + node _T_18367 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18368 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18369 = eq(_T_18368, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_18370 = and(_T_18367, _T_18369) @[ifu_bp_ctl.scala 444:22] + node _T_18371 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18372 = eq(_T_18371, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_18373 = or(_T_18372, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18374 = and(_T_18370, _T_18373) @[ifu_bp_ctl.scala 444:87] + node _T_18375 = or(_T_18366, _T_18374) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][10][7] <= _T_18375 @[ifu_bp_ctl.scala 443:27] + node _T_18376 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18377 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18378 = eq(_T_18377, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_18379 = and(_T_18376, _T_18378) @[ifu_bp_ctl.scala 443:45] + node _T_18380 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18381 = eq(_T_18380, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_18382 = or(_T_18381, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18383 = and(_T_18379, _T_18382) @[ifu_bp_ctl.scala 443:110] + node _T_18384 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18385 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18386 = eq(_T_18385, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_18387 = and(_T_18384, _T_18386) @[ifu_bp_ctl.scala 444:22] + node _T_18388 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18389 = eq(_T_18388, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_18390 = or(_T_18389, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18391 = and(_T_18387, _T_18390) @[ifu_bp_ctl.scala 444:87] + node _T_18392 = or(_T_18383, _T_18391) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][10][8] <= _T_18392 @[ifu_bp_ctl.scala 443:27] + node _T_18393 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18394 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18395 = eq(_T_18394, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_18396 = and(_T_18393, _T_18395) @[ifu_bp_ctl.scala 443:45] + node _T_18397 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18398 = eq(_T_18397, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_18399 = or(_T_18398, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18400 = and(_T_18396, _T_18399) @[ifu_bp_ctl.scala 443:110] + node _T_18401 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18402 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18403 = eq(_T_18402, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_18404 = and(_T_18401, _T_18403) @[ifu_bp_ctl.scala 444:22] + node _T_18405 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18406 = eq(_T_18405, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_18407 = or(_T_18406, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18408 = and(_T_18404, _T_18407) @[ifu_bp_ctl.scala 444:87] + node _T_18409 = or(_T_18400, _T_18408) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][10][9] <= _T_18409 @[ifu_bp_ctl.scala 443:27] + node _T_18410 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18411 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18412 = eq(_T_18411, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_18413 = and(_T_18410, _T_18412) @[ifu_bp_ctl.scala 443:45] + node _T_18414 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18415 = eq(_T_18414, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_18416 = or(_T_18415, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18417 = and(_T_18413, _T_18416) @[ifu_bp_ctl.scala 443:110] + node _T_18418 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18419 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18420 = eq(_T_18419, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_18421 = and(_T_18418, _T_18420) @[ifu_bp_ctl.scala 444:22] + node _T_18422 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18423 = eq(_T_18422, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_18424 = or(_T_18423, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18425 = and(_T_18421, _T_18424) @[ifu_bp_ctl.scala 444:87] + node _T_18426 = or(_T_18417, _T_18425) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][10][10] <= _T_18426 @[ifu_bp_ctl.scala 443:27] + node _T_18427 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18428 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18429 = eq(_T_18428, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_18430 = and(_T_18427, _T_18429) @[ifu_bp_ctl.scala 443:45] + node _T_18431 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18432 = eq(_T_18431, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_18433 = or(_T_18432, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18434 = and(_T_18430, _T_18433) @[ifu_bp_ctl.scala 443:110] + node _T_18435 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18436 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18437 = eq(_T_18436, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_18438 = and(_T_18435, _T_18437) @[ifu_bp_ctl.scala 444:22] + node _T_18439 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18440 = eq(_T_18439, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_18441 = or(_T_18440, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18442 = and(_T_18438, _T_18441) @[ifu_bp_ctl.scala 444:87] + node _T_18443 = or(_T_18434, _T_18442) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][10][11] <= _T_18443 @[ifu_bp_ctl.scala 443:27] + node _T_18444 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18445 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18446 = eq(_T_18445, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_18447 = and(_T_18444, _T_18446) @[ifu_bp_ctl.scala 443:45] + node _T_18448 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18449 = eq(_T_18448, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_18450 = or(_T_18449, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18451 = and(_T_18447, _T_18450) @[ifu_bp_ctl.scala 443:110] + node _T_18452 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18453 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18454 = eq(_T_18453, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_18455 = and(_T_18452, _T_18454) @[ifu_bp_ctl.scala 444:22] + node _T_18456 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18457 = eq(_T_18456, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_18458 = or(_T_18457, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18459 = and(_T_18455, _T_18458) @[ifu_bp_ctl.scala 444:87] + node _T_18460 = or(_T_18451, _T_18459) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][10][12] <= _T_18460 @[ifu_bp_ctl.scala 443:27] + node _T_18461 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18462 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18463 = eq(_T_18462, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_18464 = and(_T_18461, _T_18463) @[ifu_bp_ctl.scala 443:45] + node _T_18465 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18466 = eq(_T_18465, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_18467 = or(_T_18466, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18468 = and(_T_18464, _T_18467) @[ifu_bp_ctl.scala 443:110] + node _T_18469 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18470 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18471 = eq(_T_18470, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_18472 = and(_T_18469, _T_18471) @[ifu_bp_ctl.scala 444:22] + node _T_18473 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18474 = eq(_T_18473, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_18475 = or(_T_18474, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18476 = and(_T_18472, _T_18475) @[ifu_bp_ctl.scala 444:87] + node _T_18477 = or(_T_18468, _T_18476) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][10][13] <= _T_18477 @[ifu_bp_ctl.scala 443:27] + node _T_18478 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18479 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18480 = eq(_T_18479, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_18481 = and(_T_18478, _T_18480) @[ifu_bp_ctl.scala 443:45] + node _T_18482 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18483 = eq(_T_18482, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_18484 = or(_T_18483, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18485 = and(_T_18481, _T_18484) @[ifu_bp_ctl.scala 443:110] + node _T_18486 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18487 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18488 = eq(_T_18487, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_18489 = and(_T_18486, _T_18488) @[ifu_bp_ctl.scala 444:22] + node _T_18490 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18491 = eq(_T_18490, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_18492 = or(_T_18491, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18493 = and(_T_18489, _T_18492) @[ifu_bp_ctl.scala 444:87] + node _T_18494 = or(_T_18485, _T_18493) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][10][14] <= _T_18494 @[ifu_bp_ctl.scala 443:27] + node _T_18495 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18496 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18497 = eq(_T_18496, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_18498 = and(_T_18495, _T_18497) @[ifu_bp_ctl.scala 443:45] + node _T_18499 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18500 = eq(_T_18499, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:186] + node _T_18501 = or(_T_18500, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18502 = and(_T_18498, _T_18501) @[ifu_bp_ctl.scala 443:110] + node _T_18503 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18504 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18505 = eq(_T_18504, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_18506 = and(_T_18503, _T_18505) @[ifu_bp_ctl.scala 444:22] + node _T_18507 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18508 = eq(_T_18507, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:163] + node _T_18509 = or(_T_18508, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18510 = and(_T_18506, _T_18509) @[ifu_bp_ctl.scala 444:87] + node _T_18511 = or(_T_18502, _T_18510) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][10][15] <= _T_18511 @[ifu_bp_ctl.scala 443:27] + node _T_18512 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18513 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18514 = eq(_T_18513, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_18515 = and(_T_18512, _T_18514) @[ifu_bp_ctl.scala 443:45] + node _T_18516 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18517 = eq(_T_18516, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_18518 = or(_T_18517, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18519 = and(_T_18515, _T_18518) @[ifu_bp_ctl.scala 443:110] + node _T_18520 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18521 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18522 = eq(_T_18521, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_18523 = and(_T_18520, _T_18522) @[ifu_bp_ctl.scala 444:22] + node _T_18524 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18525 = eq(_T_18524, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_18526 = or(_T_18525, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18527 = and(_T_18523, _T_18526) @[ifu_bp_ctl.scala 444:87] + node _T_18528 = or(_T_18519, _T_18527) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][11][0] <= _T_18528 @[ifu_bp_ctl.scala 443:27] + node _T_18529 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18530 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18531 = eq(_T_18530, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_18532 = and(_T_18529, _T_18531) @[ifu_bp_ctl.scala 443:45] + node _T_18533 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18534 = eq(_T_18533, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_18535 = or(_T_18534, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18536 = and(_T_18532, _T_18535) @[ifu_bp_ctl.scala 443:110] + node _T_18537 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18538 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18539 = eq(_T_18538, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_18540 = and(_T_18537, _T_18539) @[ifu_bp_ctl.scala 444:22] + node _T_18541 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18542 = eq(_T_18541, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_18543 = or(_T_18542, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18544 = and(_T_18540, _T_18543) @[ifu_bp_ctl.scala 444:87] + node _T_18545 = or(_T_18536, _T_18544) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][11][1] <= _T_18545 @[ifu_bp_ctl.scala 443:27] + node _T_18546 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18547 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18548 = eq(_T_18547, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_18549 = and(_T_18546, _T_18548) @[ifu_bp_ctl.scala 443:45] + node _T_18550 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18551 = eq(_T_18550, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_18552 = or(_T_18551, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18553 = and(_T_18549, _T_18552) @[ifu_bp_ctl.scala 443:110] + node _T_18554 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18555 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18556 = eq(_T_18555, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_18557 = and(_T_18554, _T_18556) @[ifu_bp_ctl.scala 444:22] + node _T_18558 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18559 = eq(_T_18558, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_18560 = or(_T_18559, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18561 = and(_T_18557, _T_18560) @[ifu_bp_ctl.scala 444:87] + node _T_18562 = or(_T_18553, _T_18561) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][11][2] <= _T_18562 @[ifu_bp_ctl.scala 443:27] + node _T_18563 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18564 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18565 = eq(_T_18564, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_18566 = and(_T_18563, _T_18565) @[ifu_bp_ctl.scala 443:45] + node _T_18567 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18568 = eq(_T_18567, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_18569 = or(_T_18568, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18570 = and(_T_18566, _T_18569) @[ifu_bp_ctl.scala 443:110] + node _T_18571 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18572 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18573 = eq(_T_18572, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_18574 = and(_T_18571, _T_18573) @[ifu_bp_ctl.scala 444:22] + node _T_18575 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18576 = eq(_T_18575, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_18577 = or(_T_18576, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18578 = and(_T_18574, _T_18577) @[ifu_bp_ctl.scala 444:87] + node _T_18579 = or(_T_18570, _T_18578) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][11][3] <= _T_18579 @[ifu_bp_ctl.scala 443:27] + node _T_18580 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18581 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18582 = eq(_T_18581, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_18583 = and(_T_18580, _T_18582) @[ifu_bp_ctl.scala 443:45] + node _T_18584 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18585 = eq(_T_18584, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_18586 = or(_T_18585, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18587 = and(_T_18583, _T_18586) @[ifu_bp_ctl.scala 443:110] + node _T_18588 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18589 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18590 = eq(_T_18589, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_18591 = and(_T_18588, _T_18590) @[ifu_bp_ctl.scala 444:22] + node _T_18592 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18593 = eq(_T_18592, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_18594 = or(_T_18593, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18595 = and(_T_18591, _T_18594) @[ifu_bp_ctl.scala 444:87] + node _T_18596 = or(_T_18587, _T_18595) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][11][4] <= _T_18596 @[ifu_bp_ctl.scala 443:27] + node _T_18597 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18598 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18599 = eq(_T_18598, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_18600 = and(_T_18597, _T_18599) @[ifu_bp_ctl.scala 443:45] + node _T_18601 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18602 = eq(_T_18601, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_18603 = or(_T_18602, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18604 = and(_T_18600, _T_18603) @[ifu_bp_ctl.scala 443:110] + node _T_18605 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18606 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18607 = eq(_T_18606, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_18608 = and(_T_18605, _T_18607) @[ifu_bp_ctl.scala 444:22] + node _T_18609 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18610 = eq(_T_18609, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_18611 = or(_T_18610, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18612 = and(_T_18608, _T_18611) @[ifu_bp_ctl.scala 444:87] + node _T_18613 = or(_T_18604, _T_18612) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][11][5] <= _T_18613 @[ifu_bp_ctl.scala 443:27] + node _T_18614 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18615 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18616 = eq(_T_18615, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_18617 = and(_T_18614, _T_18616) @[ifu_bp_ctl.scala 443:45] + node _T_18618 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18619 = eq(_T_18618, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_18620 = or(_T_18619, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18621 = and(_T_18617, _T_18620) @[ifu_bp_ctl.scala 443:110] + node _T_18622 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18623 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18624 = eq(_T_18623, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_18625 = and(_T_18622, _T_18624) @[ifu_bp_ctl.scala 444:22] + node _T_18626 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18627 = eq(_T_18626, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_18628 = or(_T_18627, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18629 = and(_T_18625, _T_18628) @[ifu_bp_ctl.scala 444:87] + node _T_18630 = or(_T_18621, _T_18629) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][11][6] <= _T_18630 @[ifu_bp_ctl.scala 443:27] + node _T_18631 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18632 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18633 = eq(_T_18632, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_18634 = and(_T_18631, _T_18633) @[ifu_bp_ctl.scala 443:45] + node _T_18635 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18636 = eq(_T_18635, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_18637 = or(_T_18636, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18638 = and(_T_18634, _T_18637) @[ifu_bp_ctl.scala 443:110] + node _T_18639 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18640 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18641 = eq(_T_18640, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_18642 = and(_T_18639, _T_18641) @[ifu_bp_ctl.scala 444:22] + node _T_18643 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18644 = eq(_T_18643, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_18645 = or(_T_18644, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18646 = and(_T_18642, _T_18645) @[ifu_bp_ctl.scala 444:87] + node _T_18647 = or(_T_18638, _T_18646) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][11][7] <= _T_18647 @[ifu_bp_ctl.scala 443:27] + node _T_18648 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18649 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18650 = eq(_T_18649, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_18651 = and(_T_18648, _T_18650) @[ifu_bp_ctl.scala 443:45] + node _T_18652 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18653 = eq(_T_18652, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_18654 = or(_T_18653, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18655 = and(_T_18651, _T_18654) @[ifu_bp_ctl.scala 443:110] + node _T_18656 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18657 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18658 = eq(_T_18657, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_18659 = and(_T_18656, _T_18658) @[ifu_bp_ctl.scala 444:22] + node _T_18660 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18661 = eq(_T_18660, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_18662 = or(_T_18661, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18663 = and(_T_18659, _T_18662) @[ifu_bp_ctl.scala 444:87] + node _T_18664 = or(_T_18655, _T_18663) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][11][8] <= _T_18664 @[ifu_bp_ctl.scala 443:27] + node _T_18665 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18666 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18667 = eq(_T_18666, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_18668 = and(_T_18665, _T_18667) @[ifu_bp_ctl.scala 443:45] + node _T_18669 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18670 = eq(_T_18669, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_18671 = or(_T_18670, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18672 = and(_T_18668, _T_18671) @[ifu_bp_ctl.scala 443:110] + node _T_18673 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18674 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18675 = eq(_T_18674, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_18676 = and(_T_18673, _T_18675) @[ifu_bp_ctl.scala 444:22] + node _T_18677 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18678 = eq(_T_18677, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_18679 = or(_T_18678, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18680 = and(_T_18676, _T_18679) @[ifu_bp_ctl.scala 444:87] + node _T_18681 = or(_T_18672, _T_18680) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][11][9] <= _T_18681 @[ifu_bp_ctl.scala 443:27] + node _T_18682 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18683 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18684 = eq(_T_18683, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_18685 = and(_T_18682, _T_18684) @[ifu_bp_ctl.scala 443:45] + node _T_18686 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18687 = eq(_T_18686, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_18688 = or(_T_18687, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18689 = and(_T_18685, _T_18688) @[ifu_bp_ctl.scala 443:110] + node _T_18690 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18691 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18692 = eq(_T_18691, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_18693 = and(_T_18690, _T_18692) @[ifu_bp_ctl.scala 444:22] + node _T_18694 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18695 = eq(_T_18694, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_18696 = or(_T_18695, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18697 = and(_T_18693, _T_18696) @[ifu_bp_ctl.scala 444:87] + node _T_18698 = or(_T_18689, _T_18697) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][11][10] <= _T_18698 @[ifu_bp_ctl.scala 443:27] + node _T_18699 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18700 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18701 = eq(_T_18700, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_18702 = and(_T_18699, _T_18701) @[ifu_bp_ctl.scala 443:45] + node _T_18703 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18704 = eq(_T_18703, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_18705 = or(_T_18704, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18706 = and(_T_18702, _T_18705) @[ifu_bp_ctl.scala 443:110] + node _T_18707 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18708 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18709 = eq(_T_18708, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_18710 = and(_T_18707, _T_18709) @[ifu_bp_ctl.scala 444:22] + node _T_18711 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18712 = eq(_T_18711, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_18713 = or(_T_18712, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18714 = and(_T_18710, _T_18713) @[ifu_bp_ctl.scala 444:87] + node _T_18715 = or(_T_18706, _T_18714) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][11][11] <= _T_18715 @[ifu_bp_ctl.scala 443:27] + node _T_18716 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18717 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18718 = eq(_T_18717, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_18719 = and(_T_18716, _T_18718) @[ifu_bp_ctl.scala 443:45] + node _T_18720 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18721 = eq(_T_18720, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_18722 = or(_T_18721, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18723 = and(_T_18719, _T_18722) @[ifu_bp_ctl.scala 443:110] + node _T_18724 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18725 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18726 = eq(_T_18725, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_18727 = and(_T_18724, _T_18726) @[ifu_bp_ctl.scala 444:22] + node _T_18728 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18729 = eq(_T_18728, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_18730 = or(_T_18729, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18731 = and(_T_18727, _T_18730) @[ifu_bp_ctl.scala 444:87] + node _T_18732 = or(_T_18723, _T_18731) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][11][12] <= _T_18732 @[ifu_bp_ctl.scala 443:27] + node _T_18733 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18734 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18735 = eq(_T_18734, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_18736 = and(_T_18733, _T_18735) @[ifu_bp_ctl.scala 443:45] + node _T_18737 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18738 = eq(_T_18737, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_18739 = or(_T_18738, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18740 = and(_T_18736, _T_18739) @[ifu_bp_ctl.scala 443:110] + node _T_18741 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18742 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18743 = eq(_T_18742, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_18744 = and(_T_18741, _T_18743) @[ifu_bp_ctl.scala 444:22] + node _T_18745 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18746 = eq(_T_18745, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_18747 = or(_T_18746, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18748 = and(_T_18744, _T_18747) @[ifu_bp_ctl.scala 444:87] + node _T_18749 = or(_T_18740, _T_18748) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][11][13] <= _T_18749 @[ifu_bp_ctl.scala 443:27] + node _T_18750 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18751 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18752 = eq(_T_18751, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_18753 = and(_T_18750, _T_18752) @[ifu_bp_ctl.scala 443:45] + node _T_18754 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18755 = eq(_T_18754, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_18756 = or(_T_18755, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18757 = and(_T_18753, _T_18756) @[ifu_bp_ctl.scala 443:110] + node _T_18758 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18759 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18760 = eq(_T_18759, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_18761 = and(_T_18758, _T_18760) @[ifu_bp_ctl.scala 444:22] + node _T_18762 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18763 = eq(_T_18762, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_18764 = or(_T_18763, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18765 = and(_T_18761, _T_18764) @[ifu_bp_ctl.scala 444:87] + node _T_18766 = or(_T_18757, _T_18765) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][11][14] <= _T_18766 @[ifu_bp_ctl.scala 443:27] + node _T_18767 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18768 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18769 = eq(_T_18768, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_18770 = and(_T_18767, _T_18769) @[ifu_bp_ctl.scala 443:45] + node _T_18771 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18772 = eq(_T_18771, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:186] + node _T_18773 = or(_T_18772, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18774 = and(_T_18770, _T_18773) @[ifu_bp_ctl.scala 443:110] + node _T_18775 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18776 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18777 = eq(_T_18776, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_18778 = and(_T_18775, _T_18777) @[ifu_bp_ctl.scala 444:22] + node _T_18779 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18780 = eq(_T_18779, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:163] + node _T_18781 = or(_T_18780, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18782 = and(_T_18778, _T_18781) @[ifu_bp_ctl.scala 444:87] + node _T_18783 = or(_T_18774, _T_18782) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][11][15] <= _T_18783 @[ifu_bp_ctl.scala 443:27] + node _T_18784 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18785 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18786 = eq(_T_18785, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_18787 = and(_T_18784, _T_18786) @[ifu_bp_ctl.scala 443:45] + node _T_18788 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18789 = eq(_T_18788, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_18790 = or(_T_18789, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18791 = and(_T_18787, _T_18790) @[ifu_bp_ctl.scala 443:110] + node _T_18792 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18793 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18794 = eq(_T_18793, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_18795 = and(_T_18792, _T_18794) @[ifu_bp_ctl.scala 444:22] + node _T_18796 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18797 = eq(_T_18796, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_18798 = or(_T_18797, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18799 = and(_T_18795, _T_18798) @[ifu_bp_ctl.scala 444:87] + node _T_18800 = or(_T_18791, _T_18799) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][12][0] <= _T_18800 @[ifu_bp_ctl.scala 443:27] + node _T_18801 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18802 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18803 = eq(_T_18802, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_18804 = and(_T_18801, _T_18803) @[ifu_bp_ctl.scala 443:45] + node _T_18805 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18806 = eq(_T_18805, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_18807 = or(_T_18806, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18808 = and(_T_18804, _T_18807) @[ifu_bp_ctl.scala 443:110] + node _T_18809 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18810 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18811 = eq(_T_18810, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_18812 = and(_T_18809, _T_18811) @[ifu_bp_ctl.scala 444:22] + node _T_18813 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18814 = eq(_T_18813, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_18815 = or(_T_18814, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18816 = and(_T_18812, _T_18815) @[ifu_bp_ctl.scala 444:87] + node _T_18817 = or(_T_18808, _T_18816) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][12][1] <= _T_18817 @[ifu_bp_ctl.scala 443:27] + node _T_18818 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18819 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18820 = eq(_T_18819, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_18821 = and(_T_18818, _T_18820) @[ifu_bp_ctl.scala 443:45] + node _T_18822 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18823 = eq(_T_18822, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_18824 = or(_T_18823, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18825 = and(_T_18821, _T_18824) @[ifu_bp_ctl.scala 443:110] + node _T_18826 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18827 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18828 = eq(_T_18827, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_18829 = and(_T_18826, _T_18828) @[ifu_bp_ctl.scala 444:22] + node _T_18830 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18831 = eq(_T_18830, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_18832 = or(_T_18831, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18833 = and(_T_18829, _T_18832) @[ifu_bp_ctl.scala 444:87] + node _T_18834 = or(_T_18825, _T_18833) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][12][2] <= _T_18834 @[ifu_bp_ctl.scala 443:27] + node _T_18835 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18836 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18837 = eq(_T_18836, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_18838 = and(_T_18835, _T_18837) @[ifu_bp_ctl.scala 443:45] + node _T_18839 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18840 = eq(_T_18839, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_18841 = or(_T_18840, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18842 = and(_T_18838, _T_18841) @[ifu_bp_ctl.scala 443:110] + node _T_18843 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18844 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18845 = eq(_T_18844, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_18846 = and(_T_18843, _T_18845) @[ifu_bp_ctl.scala 444:22] + node _T_18847 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18848 = eq(_T_18847, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_18849 = or(_T_18848, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18850 = and(_T_18846, _T_18849) @[ifu_bp_ctl.scala 444:87] + node _T_18851 = or(_T_18842, _T_18850) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][12][3] <= _T_18851 @[ifu_bp_ctl.scala 443:27] + node _T_18852 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18853 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18854 = eq(_T_18853, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_18855 = and(_T_18852, _T_18854) @[ifu_bp_ctl.scala 443:45] + node _T_18856 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18857 = eq(_T_18856, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_18858 = or(_T_18857, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18859 = and(_T_18855, _T_18858) @[ifu_bp_ctl.scala 443:110] + node _T_18860 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18861 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18862 = eq(_T_18861, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_18863 = and(_T_18860, _T_18862) @[ifu_bp_ctl.scala 444:22] + node _T_18864 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18865 = eq(_T_18864, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_18866 = or(_T_18865, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18867 = and(_T_18863, _T_18866) @[ifu_bp_ctl.scala 444:87] + node _T_18868 = or(_T_18859, _T_18867) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][12][4] <= _T_18868 @[ifu_bp_ctl.scala 443:27] + node _T_18869 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18870 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18871 = eq(_T_18870, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_18872 = and(_T_18869, _T_18871) @[ifu_bp_ctl.scala 443:45] + node _T_18873 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18874 = eq(_T_18873, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_18875 = or(_T_18874, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18876 = and(_T_18872, _T_18875) @[ifu_bp_ctl.scala 443:110] + node _T_18877 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18878 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18879 = eq(_T_18878, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_18880 = and(_T_18877, _T_18879) @[ifu_bp_ctl.scala 444:22] + node _T_18881 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18882 = eq(_T_18881, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_18883 = or(_T_18882, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18884 = and(_T_18880, _T_18883) @[ifu_bp_ctl.scala 444:87] + node _T_18885 = or(_T_18876, _T_18884) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][12][5] <= _T_18885 @[ifu_bp_ctl.scala 443:27] + node _T_18886 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18887 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18888 = eq(_T_18887, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_18889 = and(_T_18886, _T_18888) @[ifu_bp_ctl.scala 443:45] + node _T_18890 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18891 = eq(_T_18890, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_18892 = or(_T_18891, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18893 = and(_T_18889, _T_18892) @[ifu_bp_ctl.scala 443:110] + node _T_18894 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18895 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18896 = eq(_T_18895, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_18897 = and(_T_18894, _T_18896) @[ifu_bp_ctl.scala 444:22] + node _T_18898 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18899 = eq(_T_18898, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_18900 = or(_T_18899, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18901 = and(_T_18897, _T_18900) @[ifu_bp_ctl.scala 444:87] + node _T_18902 = or(_T_18893, _T_18901) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][12][6] <= _T_18902 @[ifu_bp_ctl.scala 443:27] + node _T_18903 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18904 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18905 = eq(_T_18904, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_18906 = and(_T_18903, _T_18905) @[ifu_bp_ctl.scala 443:45] + node _T_18907 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18908 = eq(_T_18907, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_18909 = or(_T_18908, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18910 = and(_T_18906, _T_18909) @[ifu_bp_ctl.scala 443:110] + node _T_18911 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18912 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18913 = eq(_T_18912, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_18914 = and(_T_18911, _T_18913) @[ifu_bp_ctl.scala 444:22] + node _T_18915 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18916 = eq(_T_18915, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_18917 = or(_T_18916, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18918 = and(_T_18914, _T_18917) @[ifu_bp_ctl.scala 444:87] + node _T_18919 = or(_T_18910, _T_18918) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][12][7] <= _T_18919 @[ifu_bp_ctl.scala 443:27] + node _T_18920 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18921 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18922 = eq(_T_18921, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_18923 = and(_T_18920, _T_18922) @[ifu_bp_ctl.scala 443:45] + node _T_18924 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18925 = eq(_T_18924, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_18926 = or(_T_18925, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18927 = and(_T_18923, _T_18926) @[ifu_bp_ctl.scala 443:110] + node _T_18928 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18929 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18930 = eq(_T_18929, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_18931 = and(_T_18928, _T_18930) @[ifu_bp_ctl.scala 444:22] + node _T_18932 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18933 = eq(_T_18932, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_18934 = or(_T_18933, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18935 = and(_T_18931, _T_18934) @[ifu_bp_ctl.scala 444:87] + node _T_18936 = or(_T_18927, _T_18935) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][12][8] <= _T_18936 @[ifu_bp_ctl.scala 443:27] + node _T_18937 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18938 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18939 = eq(_T_18938, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_18940 = and(_T_18937, _T_18939) @[ifu_bp_ctl.scala 443:45] + node _T_18941 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18942 = eq(_T_18941, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_18943 = or(_T_18942, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18944 = and(_T_18940, _T_18943) @[ifu_bp_ctl.scala 443:110] + node _T_18945 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18946 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18947 = eq(_T_18946, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_18948 = and(_T_18945, _T_18947) @[ifu_bp_ctl.scala 444:22] + node _T_18949 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18950 = eq(_T_18949, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_18951 = or(_T_18950, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18952 = and(_T_18948, _T_18951) @[ifu_bp_ctl.scala 444:87] + node _T_18953 = or(_T_18944, _T_18952) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][12][9] <= _T_18953 @[ifu_bp_ctl.scala 443:27] + node _T_18954 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18955 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18956 = eq(_T_18955, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_18957 = and(_T_18954, _T_18956) @[ifu_bp_ctl.scala 443:45] + node _T_18958 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18959 = eq(_T_18958, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_18960 = or(_T_18959, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18961 = and(_T_18957, _T_18960) @[ifu_bp_ctl.scala 443:110] + node _T_18962 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18963 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18964 = eq(_T_18963, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_18965 = and(_T_18962, _T_18964) @[ifu_bp_ctl.scala 444:22] + node _T_18966 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18967 = eq(_T_18966, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_18968 = or(_T_18967, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18969 = and(_T_18965, _T_18968) @[ifu_bp_ctl.scala 444:87] + node _T_18970 = or(_T_18961, _T_18969) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][12][10] <= _T_18970 @[ifu_bp_ctl.scala 443:27] + node _T_18971 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18972 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18973 = eq(_T_18972, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_18974 = and(_T_18971, _T_18973) @[ifu_bp_ctl.scala 443:45] + node _T_18975 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18976 = eq(_T_18975, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_18977 = or(_T_18976, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18978 = and(_T_18974, _T_18977) @[ifu_bp_ctl.scala 443:110] + node _T_18979 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18980 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18981 = eq(_T_18980, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_18982 = and(_T_18979, _T_18981) @[ifu_bp_ctl.scala 444:22] + node _T_18983 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_18984 = eq(_T_18983, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_18985 = or(_T_18984, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_18986 = and(_T_18982, _T_18985) @[ifu_bp_ctl.scala 444:87] + node _T_18987 = or(_T_18978, _T_18986) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][12][11] <= _T_18987 @[ifu_bp_ctl.scala 443:27] + node _T_18988 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_18989 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_18990 = eq(_T_18989, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_18991 = and(_T_18988, _T_18990) @[ifu_bp_ctl.scala 443:45] + node _T_18992 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_18993 = eq(_T_18992, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_18994 = or(_T_18993, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_18995 = and(_T_18991, _T_18994) @[ifu_bp_ctl.scala 443:110] + node _T_18996 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_18997 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_18998 = eq(_T_18997, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_18999 = and(_T_18996, _T_18998) @[ifu_bp_ctl.scala 444:22] + node _T_19000 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19001 = eq(_T_19000, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_19002 = or(_T_19001, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19003 = and(_T_18999, _T_19002) @[ifu_bp_ctl.scala 444:87] + node _T_19004 = or(_T_18995, _T_19003) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][12][12] <= _T_19004 @[ifu_bp_ctl.scala 443:27] + node _T_19005 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19006 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19007 = eq(_T_19006, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_19008 = and(_T_19005, _T_19007) @[ifu_bp_ctl.scala 443:45] + node _T_19009 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19010 = eq(_T_19009, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_19011 = or(_T_19010, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19012 = and(_T_19008, _T_19011) @[ifu_bp_ctl.scala 443:110] + node _T_19013 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19014 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19015 = eq(_T_19014, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_19016 = and(_T_19013, _T_19015) @[ifu_bp_ctl.scala 444:22] + node _T_19017 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19018 = eq(_T_19017, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_19019 = or(_T_19018, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19020 = and(_T_19016, _T_19019) @[ifu_bp_ctl.scala 444:87] + node _T_19021 = or(_T_19012, _T_19020) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][12][13] <= _T_19021 @[ifu_bp_ctl.scala 443:27] + node _T_19022 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19023 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19024 = eq(_T_19023, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_19025 = and(_T_19022, _T_19024) @[ifu_bp_ctl.scala 443:45] + node _T_19026 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19027 = eq(_T_19026, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_19028 = or(_T_19027, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19029 = and(_T_19025, _T_19028) @[ifu_bp_ctl.scala 443:110] + node _T_19030 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19031 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19032 = eq(_T_19031, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_19033 = and(_T_19030, _T_19032) @[ifu_bp_ctl.scala 444:22] + node _T_19034 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19035 = eq(_T_19034, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_19036 = or(_T_19035, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19037 = and(_T_19033, _T_19036) @[ifu_bp_ctl.scala 444:87] + node _T_19038 = or(_T_19029, _T_19037) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][12][14] <= _T_19038 @[ifu_bp_ctl.scala 443:27] + node _T_19039 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19040 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19041 = eq(_T_19040, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_19042 = and(_T_19039, _T_19041) @[ifu_bp_ctl.scala 443:45] + node _T_19043 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19044 = eq(_T_19043, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:186] + node _T_19045 = or(_T_19044, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19046 = and(_T_19042, _T_19045) @[ifu_bp_ctl.scala 443:110] + node _T_19047 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19048 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19049 = eq(_T_19048, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_19050 = and(_T_19047, _T_19049) @[ifu_bp_ctl.scala 444:22] + node _T_19051 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19052 = eq(_T_19051, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:163] + node _T_19053 = or(_T_19052, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19054 = and(_T_19050, _T_19053) @[ifu_bp_ctl.scala 444:87] + node _T_19055 = or(_T_19046, _T_19054) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][12][15] <= _T_19055 @[ifu_bp_ctl.scala 443:27] + node _T_19056 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19057 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19058 = eq(_T_19057, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_19059 = and(_T_19056, _T_19058) @[ifu_bp_ctl.scala 443:45] + node _T_19060 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19061 = eq(_T_19060, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_19062 = or(_T_19061, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19063 = and(_T_19059, _T_19062) @[ifu_bp_ctl.scala 443:110] + node _T_19064 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19065 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19066 = eq(_T_19065, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_19067 = and(_T_19064, _T_19066) @[ifu_bp_ctl.scala 444:22] + node _T_19068 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19069 = eq(_T_19068, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_19070 = or(_T_19069, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19071 = and(_T_19067, _T_19070) @[ifu_bp_ctl.scala 444:87] + node _T_19072 = or(_T_19063, _T_19071) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][13][0] <= _T_19072 @[ifu_bp_ctl.scala 443:27] + node _T_19073 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19074 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19075 = eq(_T_19074, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_19076 = and(_T_19073, _T_19075) @[ifu_bp_ctl.scala 443:45] + node _T_19077 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19078 = eq(_T_19077, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_19079 = or(_T_19078, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19080 = and(_T_19076, _T_19079) @[ifu_bp_ctl.scala 443:110] + node _T_19081 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19082 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19083 = eq(_T_19082, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_19084 = and(_T_19081, _T_19083) @[ifu_bp_ctl.scala 444:22] + node _T_19085 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19086 = eq(_T_19085, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_19087 = or(_T_19086, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19088 = and(_T_19084, _T_19087) @[ifu_bp_ctl.scala 444:87] + node _T_19089 = or(_T_19080, _T_19088) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][13][1] <= _T_19089 @[ifu_bp_ctl.scala 443:27] + node _T_19090 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19091 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19092 = eq(_T_19091, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_19093 = and(_T_19090, _T_19092) @[ifu_bp_ctl.scala 443:45] + node _T_19094 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19095 = eq(_T_19094, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_19096 = or(_T_19095, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19097 = and(_T_19093, _T_19096) @[ifu_bp_ctl.scala 443:110] + node _T_19098 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19099 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19100 = eq(_T_19099, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_19101 = and(_T_19098, _T_19100) @[ifu_bp_ctl.scala 444:22] + node _T_19102 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19103 = eq(_T_19102, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_19104 = or(_T_19103, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19105 = and(_T_19101, _T_19104) @[ifu_bp_ctl.scala 444:87] + node _T_19106 = or(_T_19097, _T_19105) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][13][2] <= _T_19106 @[ifu_bp_ctl.scala 443:27] + node _T_19107 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19108 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19109 = eq(_T_19108, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_19110 = and(_T_19107, _T_19109) @[ifu_bp_ctl.scala 443:45] + node _T_19111 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19112 = eq(_T_19111, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_19113 = or(_T_19112, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19114 = and(_T_19110, _T_19113) @[ifu_bp_ctl.scala 443:110] + node _T_19115 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19116 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19117 = eq(_T_19116, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_19118 = and(_T_19115, _T_19117) @[ifu_bp_ctl.scala 444:22] + node _T_19119 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19120 = eq(_T_19119, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_19121 = or(_T_19120, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19122 = and(_T_19118, _T_19121) @[ifu_bp_ctl.scala 444:87] + node _T_19123 = or(_T_19114, _T_19122) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][13][3] <= _T_19123 @[ifu_bp_ctl.scala 443:27] + node _T_19124 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19125 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19126 = eq(_T_19125, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_19127 = and(_T_19124, _T_19126) @[ifu_bp_ctl.scala 443:45] + node _T_19128 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19129 = eq(_T_19128, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_19130 = or(_T_19129, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19131 = and(_T_19127, _T_19130) @[ifu_bp_ctl.scala 443:110] + node _T_19132 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19133 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19134 = eq(_T_19133, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_19135 = and(_T_19132, _T_19134) @[ifu_bp_ctl.scala 444:22] + node _T_19136 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19137 = eq(_T_19136, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_19138 = or(_T_19137, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19139 = and(_T_19135, _T_19138) @[ifu_bp_ctl.scala 444:87] + node _T_19140 = or(_T_19131, _T_19139) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][13][4] <= _T_19140 @[ifu_bp_ctl.scala 443:27] + node _T_19141 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19142 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19143 = eq(_T_19142, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_19144 = and(_T_19141, _T_19143) @[ifu_bp_ctl.scala 443:45] + node _T_19145 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19146 = eq(_T_19145, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_19147 = or(_T_19146, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19148 = and(_T_19144, _T_19147) @[ifu_bp_ctl.scala 443:110] + node _T_19149 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19150 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19151 = eq(_T_19150, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_19152 = and(_T_19149, _T_19151) @[ifu_bp_ctl.scala 444:22] + node _T_19153 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19154 = eq(_T_19153, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_19155 = or(_T_19154, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19156 = and(_T_19152, _T_19155) @[ifu_bp_ctl.scala 444:87] + node _T_19157 = or(_T_19148, _T_19156) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][13][5] <= _T_19157 @[ifu_bp_ctl.scala 443:27] + node _T_19158 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19159 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19160 = eq(_T_19159, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_19161 = and(_T_19158, _T_19160) @[ifu_bp_ctl.scala 443:45] + node _T_19162 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19163 = eq(_T_19162, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_19164 = or(_T_19163, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19165 = and(_T_19161, _T_19164) @[ifu_bp_ctl.scala 443:110] + node _T_19166 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19167 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19168 = eq(_T_19167, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_19169 = and(_T_19166, _T_19168) @[ifu_bp_ctl.scala 444:22] + node _T_19170 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19171 = eq(_T_19170, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_19172 = or(_T_19171, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19173 = and(_T_19169, _T_19172) @[ifu_bp_ctl.scala 444:87] + node _T_19174 = or(_T_19165, _T_19173) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][13][6] <= _T_19174 @[ifu_bp_ctl.scala 443:27] + node _T_19175 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19176 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19177 = eq(_T_19176, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_19178 = and(_T_19175, _T_19177) @[ifu_bp_ctl.scala 443:45] + node _T_19179 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19180 = eq(_T_19179, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_19181 = or(_T_19180, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19182 = and(_T_19178, _T_19181) @[ifu_bp_ctl.scala 443:110] + node _T_19183 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19184 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19185 = eq(_T_19184, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_19186 = and(_T_19183, _T_19185) @[ifu_bp_ctl.scala 444:22] + node _T_19187 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19188 = eq(_T_19187, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_19189 = or(_T_19188, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19190 = and(_T_19186, _T_19189) @[ifu_bp_ctl.scala 444:87] + node _T_19191 = or(_T_19182, _T_19190) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][13][7] <= _T_19191 @[ifu_bp_ctl.scala 443:27] + node _T_19192 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19193 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19194 = eq(_T_19193, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_19195 = and(_T_19192, _T_19194) @[ifu_bp_ctl.scala 443:45] + node _T_19196 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19197 = eq(_T_19196, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_19198 = or(_T_19197, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19199 = and(_T_19195, _T_19198) @[ifu_bp_ctl.scala 443:110] + node _T_19200 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19201 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19202 = eq(_T_19201, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_19203 = and(_T_19200, _T_19202) @[ifu_bp_ctl.scala 444:22] + node _T_19204 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19205 = eq(_T_19204, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_19206 = or(_T_19205, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19207 = and(_T_19203, _T_19206) @[ifu_bp_ctl.scala 444:87] + node _T_19208 = or(_T_19199, _T_19207) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][13][8] <= _T_19208 @[ifu_bp_ctl.scala 443:27] + node _T_19209 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19210 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19211 = eq(_T_19210, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_19212 = and(_T_19209, _T_19211) @[ifu_bp_ctl.scala 443:45] + node _T_19213 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19214 = eq(_T_19213, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_19215 = or(_T_19214, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19216 = and(_T_19212, _T_19215) @[ifu_bp_ctl.scala 443:110] + node _T_19217 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19218 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19219 = eq(_T_19218, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_19220 = and(_T_19217, _T_19219) @[ifu_bp_ctl.scala 444:22] + node _T_19221 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19222 = eq(_T_19221, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_19223 = or(_T_19222, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19224 = and(_T_19220, _T_19223) @[ifu_bp_ctl.scala 444:87] + node _T_19225 = or(_T_19216, _T_19224) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][13][9] <= _T_19225 @[ifu_bp_ctl.scala 443:27] + node _T_19226 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19227 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19228 = eq(_T_19227, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_19229 = and(_T_19226, _T_19228) @[ifu_bp_ctl.scala 443:45] + node _T_19230 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19231 = eq(_T_19230, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_19232 = or(_T_19231, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19233 = and(_T_19229, _T_19232) @[ifu_bp_ctl.scala 443:110] + node _T_19234 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19235 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19236 = eq(_T_19235, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_19237 = and(_T_19234, _T_19236) @[ifu_bp_ctl.scala 444:22] + node _T_19238 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19239 = eq(_T_19238, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_19240 = or(_T_19239, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19241 = and(_T_19237, _T_19240) @[ifu_bp_ctl.scala 444:87] + node _T_19242 = or(_T_19233, _T_19241) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][13][10] <= _T_19242 @[ifu_bp_ctl.scala 443:27] + node _T_19243 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19244 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19245 = eq(_T_19244, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_19246 = and(_T_19243, _T_19245) @[ifu_bp_ctl.scala 443:45] + node _T_19247 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19248 = eq(_T_19247, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_19249 = or(_T_19248, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19250 = and(_T_19246, _T_19249) @[ifu_bp_ctl.scala 443:110] + node _T_19251 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19252 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19253 = eq(_T_19252, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_19254 = and(_T_19251, _T_19253) @[ifu_bp_ctl.scala 444:22] + node _T_19255 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19256 = eq(_T_19255, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_19257 = or(_T_19256, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19258 = and(_T_19254, _T_19257) @[ifu_bp_ctl.scala 444:87] + node _T_19259 = or(_T_19250, _T_19258) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][13][11] <= _T_19259 @[ifu_bp_ctl.scala 443:27] + node _T_19260 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19261 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19262 = eq(_T_19261, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_19263 = and(_T_19260, _T_19262) @[ifu_bp_ctl.scala 443:45] + node _T_19264 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19265 = eq(_T_19264, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_19266 = or(_T_19265, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19267 = and(_T_19263, _T_19266) @[ifu_bp_ctl.scala 443:110] + node _T_19268 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19269 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19270 = eq(_T_19269, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_19271 = and(_T_19268, _T_19270) @[ifu_bp_ctl.scala 444:22] + node _T_19272 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19273 = eq(_T_19272, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_19274 = or(_T_19273, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19275 = and(_T_19271, _T_19274) @[ifu_bp_ctl.scala 444:87] + node _T_19276 = or(_T_19267, _T_19275) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][13][12] <= _T_19276 @[ifu_bp_ctl.scala 443:27] + node _T_19277 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19278 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19279 = eq(_T_19278, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_19280 = and(_T_19277, _T_19279) @[ifu_bp_ctl.scala 443:45] + node _T_19281 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19282 = eq(_T_19281, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_19283 = or(_T_19282, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19284 = and(_T_19280, _T_19283) @[ifu_bp_ctl.scala 443:110] + node _T_19285 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19286 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19287 = eq(_T_19286, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_19288 = and(_T_19285, _T_19287) @[ifu_bp_ctl.scala 444:22] + node _T_19289 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19290 = eq(_T_19289, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_19291 = or(_T_19290, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19292 = and(_T_19288, _T_19291) @[ifu_bp_ctl.scala 444:87] + node _T_19293 = or(_T_19284, _T_19292) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][13][13] <= _T_19293 @[ifu_bp_ctl.scala 443:27] + node _T_19294 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19295 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19296 = eq(_T_19295, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_19297 = and(_T_19294, _T_19296) @[ifu_bp_ctl.scala 443:45] + node _T_19298 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19299 = eq(_T_19298, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_19300 = or(_T_19299, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19301 = and(_T_19297, _T_19300) @[ifu_bp_ctl.scala 443:110] + node _T_19302 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19303 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19304 = eq(_T_19303, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_19305 = and(_T_19302, _T_19304) @[ifu_bp_ctl.scala 444:22] + node _T_19306 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19307 = eq(_T_19306, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_19308 = or(_T_19307, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19309 = and(_T_19305, _T_19308) @[ifu_bp_ctl.scala 444:87] + node _T_19310 = or(_T_19301, _T_19309) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][13][14] <= _T_19310 @[ifu_bp_ctl.scala 443:27] + node _T_19311 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19312 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19313 = eq(_T_19312, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_19314 = and(_T_19311, _T_19313) @[ifu_bp_ctl.scala 443:45] + node _T_19315 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19316 = eq(_T_19315, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:186] + node _T_19317 = or(_T_19316, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19318 = and(_T_19314, _T_19317) @[ifu_bp_ctl.scala 443:110] + node _T_19319 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19320 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19321 = eq(_T_19320, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_19322 = and(_T_19319, _T_19321) @[ifu_bp_ctl.scala 444:22] + node _T_19323 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19324 = eq(_T_19323, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:163] + node _T_19325 = or(_T_19324, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19326 = and(_T_19322, _T_19325) @[ifu_bp_ctl.scala 444:87] + node _T_19327 = or(_T_19318, _T_19326) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][13][15] <= _T_19327 @[ifu_bp_ctl.scala 443:27] + node _T_19328 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19329 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19330 = eq(_T_19329, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_19331 = and(_T_19328, _T_19330) @[ifu_bp_ctl.scala 443:45] + node _T_19332 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19333 = eq(_T_19332, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_19334 = or(_T_19333, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19335 = and(_T_19331, _T_19334) @[ifu_bp_ctl.scala 443:110] + node _T_19336 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19337 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19338 = eq(_T_19337, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_19339 = and(_T_19336, _T_19338) @[ifu_bp_ctl.scala 444:22] + node _T_19340 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19341 = eq(_T_19340, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_19342 = or(_T_19341, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19343 = and(_T_19339, _T_19342) @[ifu_bp_ctl.scala 444:87] + node _T_19344 = or(_T_19335, _T_19343) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][14][0] <= _T_19344 @[ifu_bp_ctl.scala 443:27] + node _T_19345 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19346 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19347 = eq(_T_19346, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_19348 = and(_T_19345, _T_19347) @[ifu_bp_ctl.scala 443:45] + node _T_19349 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19350 = eq(_T_19349, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_19351 = or(_T_19350, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19352 = and(_T_19348, _T_19351) @[ifu_bp_ctl.scala 443:110] + node _T_19353 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19354 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19355 = eq(_T_19354, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_19356 = and(_T_19353, _T_19355) @[ifu_bp_ctl.scala 444:22] + node _T_19357 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19358 = eq(_T_19357, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_19359 = or(_T_19358, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19360 = and(_T_19356, _T_19359) @[ifu_bp_ctl.scala 444:87] + node _T_19361 = or(_T_19352, _T_19360) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][14][1] <= _T_19361 @[ifu_bp_ctl.scala 443:27] + node _T_19362 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19363 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19364 = eq(_T_19363, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_19365 = and(_T_19362, _T_19364) @[ifu_bp_ctl.scala 443:45] + node _T_19366 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19367 = eq(_T_19366, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_19368 = or(_T_19367, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19369 = and(_T_19365, _T_19368) @[ifu_bp_ctl.scala 443:110] + node _T_19370 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19371 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19372 = eq(_T_19371, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_19373 = and(_T_19370, _T_19372) @[ifu_bp_ctl.scala 444:22] + node _T_19374 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19375 = eq(_T_19374, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_19376 = or(_T_19375, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19377 = and(_T_19373, _T_19376) @[ifu_bp_ctl.scala 444:87] + node _T_19378 = or(_T_19369, _T_19377) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][14][2] <= _T_19378 @[ifu_bp_ctl.scala 443:27] + node _T_19379 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19380 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19381 = eq(_T_19380, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_19382 = and(_T_19379, _T_19381) @[ifu_bp_ctl.scala 443:45] + node _T_19383 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19384 = eq(_T_19383, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_19385 = or(_T_19384, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19386 = and(_T_19382, _T_19385) @[ifu_bp_ctl.scala 443:110] + node _T_19387 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19388 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19389 = eq(_T_19388, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_19390 = and(_T_19387, _T_19389) @[ifu_bp_ctl.scala 444:22] + node _T_19391 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19392 = eq(_T_19391, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_19393 = or(_T_19392, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19394 = and(_T_19390, _T_19393) @[ifu_bp_ctl.scala 444:87] + node _T_19395 = or(_T_19386, _T_19394) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][14][3] <= _T_19395 @[ifu_bp_ctl.scala 443:27] + node _T_19396 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19397 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19398 = eq(_T_19397, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_19399 = and(_T_19396, _T_19398) @[ifu_bp_ctl.scala 443:45] + node _T_19400 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19401 = eq(_T_19400, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_19402 = or(_T_19401, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19403 = and(_T_19399, _T_19402) @[ifu_bp_ctl.scala 443:110] + node _T_19404 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19405 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19406 = eq(_T_19405, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_19407 = and(_T_19404, _T_19406) @[ifu_bp_ctl.scala 444:22] + node _T_19408 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19409 = eq(_T_19408, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_19410 = or(_T_19409, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19411 = and(_T_19407, _T_19410) @[ifu_bp_ctl.scala 444:87] + node _T_19412 = or(_T_19403, _T_19411) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][14][4] <= _T_19412 @[ifu_bp_ctl.scala 443:27] + node _T_19413 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19414 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19415 = eq(_T_19414, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_19416 = and(_T_19413, _T_19415) @[ifu_bp_ctl.scala 443:45] + node _T_19417 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19418 = eq(_T_19417, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_19419 = or(_T_19418, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19420 = and(_T_19416, _T_19419) @[ifu_bp_ctl.scala 443:110] + node _T_19421 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19422 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19423 = eq(_T_19422, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_19424 = and(_T_19421, _T_19423) @[ifu_bp_ctl.scala 444:22] + node _T_19425 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19426 = eq(_T_19425, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_19427 = or(_T_19426, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19428 = and(_T_19424, _T_19427) @[ifu_bp_ctl.scala 444:87] + node _T_19429 = or(_T_19420, _T_19428) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][14][5] <= _T_19429 @[ifu_bp_ctl.scala 443:27] + node _T_19430 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19431 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19432 = eq(_T_19431, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_19433 = and(_T_19430, _T_19432) @[ifu_bp_ctl.scala 443:45] + node _T_19434 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19435 = eq(_T_19434, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_19436 = or(_T_19435, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19437 = and(_T_19433, _T_19436) @[ifu_bp_ctl.scala 443:110] + node _T_19438 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19439 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19440 = eq(_T_19439, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_19441 = and(_T_19438, _T_19440) @[ifu_bp_ctl.scala 444:22] + node _T_19442 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19443 = eq(_T_19442, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_19444 = or(_T_19443, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19445 = and(_T_19441, _T_19444) @[ifu_bp_ctl.scala 444:87] + node _T_19446 = or(_T_19437, _T_19445) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][14][6] <= _T_19446 @[ifu_bp_ctl.scala 443:27] + node _T_19447 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19448 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19449 = eq(_T_19448, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_19450 = and(_T_19447, _T_19449) @[ifu_bp_ctl.scala 443:45] + node _T_19451 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19452 = eq(_T_19451, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_19453 = or(_T_19452, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19454 = and(_T_19450, _T_19453) @[ifu_bp_ctl.scala 443:110] + node _T_19455 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19456 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19457 = eq(_T_19456, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_19458 = and(_T_19455, _T_19457) @[ifu_bp_ctl.scala 444:22] + node _T_19459 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19460 = eq(_T_19459, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_19461 = or(_T_19460, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19462 = and(_T_19458, _T_19461) @[ifu_bp_ctl.scala 444:87] + node _T_19463 = or(_T_19454, _T_19462) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][14][7] <= _T_19463 @[ifu_bp_ctl.scala 443:27] + node _T_19464 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19465 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19466 = eq(_T_19465, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_19467 = and(_T_19464, _T_19466) @[ifu_bp_ctl.scala 443:45] + node _T_19468 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19469 = eq(_T_19468, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_19470 = or(_T_19469, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19471 = and(_T_19467, _T_19470) @[ifu_bp_ctl.scala 443:110] + node _T_19472 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19473 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19474 = eq(_T_19473, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_19475 = and(_T_19472, _T_19474) @[ifu_bp_ctl.scala 444:22] + node _T_19476 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19477 = eq(_T_19476, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_19478 = or(_T_19477, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19479 = and(_T_19475, _T_19478) @[ifu_bp_ctl.scala 444:87] + node _T_19480 = or(_T_19471, _T_19479) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][14][8] <= _T_19480 @[ifu_bp_ctl.scala 443:27] + node _T_19481 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19482 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19483 = eq(_T_19482, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_19484 = and(_T_19481, _T_19483) @[ifu_bp_ctl.scala 443:45] + node _T_19485 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19486 = eq(_T_19485, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_19487 = or(_T_19486, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19488 = and(_T_19484, _T_19487) @[ifu_bp_ctl.scala 443:110] + node _T_19489 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19490 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19491 = eq(_T_19490, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_19492 = and(_T_19489, _T_19491) @[ifu_bp_ctl.scala 444:22] + node _T_19493 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19494 = eq(_T_19493, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_19495 = or(_T_19494, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19496 = and(_T_19492, _T_19495) @[ifu_bp_ctl.scala 444:87] + node _T_19497 = or(_T_19488, _T_19496) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][14][9] <= _T_19497 @[ifu_bp_ctl.scala 443:27] + node _T_19498 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19499 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19500 = eq(_T_19499, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_19501 = and(_T_19498, _T_19500) @[ifu_bp_ctl.scala 443:45] + node _T_19502 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19503 = eq(_T_19502, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_19504 = or(_T_19503, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19505 = and(_T_19501, _T_19504) @[ifu_bp_ctl.scala 443:110] + node _T_19506 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19507 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19508 = eq(_T_19507, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_19509 = and(_T_19506, _T_19508) @[ifu_bp_ctl.scala 444:22] + node _T_19510 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19511 = eq(_T_19510, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_19512 = or(_T_19511, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19513 = and(_T_19509, _T_19512) @[ifu_bp_ctl.scala 444:87] + node _T_19514 = or(_T_19505, _T_19513) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][14][10] <= _T_19514 @[ifu_bp_ctl.scala 443:27] + node _T_19515 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19516 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19517 = eq(_T_19516, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_19518 = and(_T_19515, _T_19517) @[ifu_bp_ctl.scala 443:45] + node _T_19519 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19520 = eq(_T_19519, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_19521 = or(_T_19520, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19522 = and(_T_19518, _T_19521) @[ifu_bp_ctl.scala 443:110] + node _T_19523 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19524 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19525 = eq(_T_19524, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_19526 = and(_T_19523, _T_19525) @[ifu_bp_ctl.scala 444:22] + node _T_19527 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19528 = eq(_T_19527, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_19529 = or(_T_19528, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19530 = and(_T_19526, _T_19529) @[ifu_bp_ctl.scala 444:87] + node _T_19531 = or(_T_19522, _T_19530) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][14][11] <= _T_19531 @[ifu_bp_ctl.scala 443:27] + node _T_19532 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19533 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19534 = eq(_T_19533, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_19535 = and(_T_19532, _T_19534) @[ifu_bp_ctl.scala 443:45] + node _T_19536 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19537 = eq(_T_19536, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_19538 = or(_T_19537, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19539 = and(_T_19535, _T_19538) @[ifu_bp_ctl.scala 443:110] + node _T_19540 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19541 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19542 = eq(_T_19541, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_19543 = and(_T_19540, _T_19542) @[ifu_bp_ctl.scala 444:22] + node _T_19544 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19545 = eq(_T_19544, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_19546 = or(_T_19545, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19547 = and(_T_19543, _T_19546) @[ifu_bp_ctl.scala 444:87] + node _T_19548 = or(_T_19539, _T_19547) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][14][12] <= _T_19548 @[ifu_bp_ctl.scala 443:27] + node _T_19549 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19550 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19551 = eq(_T_19550, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_19552 = and(_T_19549, _T_19551) @[ifu_bp_ctl.scala 443:45] + node _T_19553 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19554 = eq(_T_19553, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_19555 = or(_T_19554, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19556 = and(_T_19552, _T_19555) @[ifu_bp_ctl.scala 443:110] + node _T_19557 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19558 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19559 = eq(_T_19558, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_19560 = and(_T_19557, _T_19559) @[ifu_bp_ctl.scala 444:22] + node _T_19561 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19562 = eq(_T_19561, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_19563 = or(_T_19562, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19564 = and(_T_19560, _T_19563) @[ifu_bp_ctl.scala 444:87] + node _T_19565 = or(_T_19556, _T_19564) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][14][13] <= _T_19565 @[ifu_bp_ctl.scala 443:27] + node _T_19566 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19567 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19568 = eq(_T_19567, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_19569 = and(_T_19566, _T_19568) @[ifu_bp_ctl.scala 443:45] + node _T_19570 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19571 = eq(_T_19570, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_19572 = or(_T_19571, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19573 = and(_T_19569, _T_19572) @[ifu_bp_ctl.scala 443:110] + node _T_19574 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19575 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19576 = eq(_T_19575, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_19577 = and(_T_19574, _T_19576) @[ifu_bp_ctl.scala 444:22] + node _T_19578 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19579 = eq(_T_19578, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_19580 = or(_T_19579, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19581 = and(_T_19577, _T_19580) @[ifu_bp_ctl.scala 444:87] + node _T_19582 = or(_T_19573, _T_19581) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][14][14] <= _T_19582 @[ifu_bp_ctl.scala 443:27] + node _T_19583 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19584 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19585 = eq(_T_19584, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_19586 = and(_T_19583, _T_19585) @[ifu_bp_ctl.scala 443:45] + node _T_19587 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19588 = eq(_T_19587, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:186] + node _T_19589 = or(_T_19588, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19590 = and(_T_19586, _T_19589) @[ifu_bp_ctl.scala 443:110] + node _T_19591 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19592 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19593 = eq(_T_19592, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_19594 = and(_T_19591, _T_19593) @[ifu_bp_ctl.scala 444:22] + node _T_19595 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19596 = eq(_T_19595, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:163] + node _T_19597 = or(_T_19596, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19598 = and(_T_19594, _T_19597) @[ifu_bp_ctl.scala 444:87] + node _T_19599 = or(_T_19590, _T_19598) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][14][15] <= _T_19599 @[ifu_bp_ctl.scala 443:27] + node _T_19600 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19601 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19602 = eq(_T_19601, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:97] + node _T_19603 = and(_T_19600, _T_19602) @[ifu_bp_ctl.scala 443:45] + node _T_19604 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19605 = eq(_T_19604, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_19606 = or(_T_19605, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19607 = and(_T_19603, _T_19606) @[ifu_bp_ctl.scala 443:110] + node _T_19608 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19609 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19610 = eq(_T_19609, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:74] + node _T_19611 = and(_T_19608, _T_19610) @[ifu_bp_ctl.scala 444:22] + node _T_19612 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19613 = eq(_T_19612, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_19614 = or(_T_19613, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19615 = and(_T_19611, _T_19614) @[ifu_bp_ctl.scala 444:87] + node _T_19616 = or(_T_19607, _T_19615) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][15][0] <= _T_19616 @[ifu_bp_ctl.scala 443:27] + node _T_19617 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19618 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19619 = eq(_T_19618, UInt<1>("h01")) @[ifu_bp_ctl.scala 443:97] + node _T_19620 = and(_T_19617, _T_19619) @[ifu_bp_ctl.scala 443:45] + node _T_19621 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19622 = eq(_T_19621, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_19623 = or(_T_19622, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19624 = and(_T_19620, _T_19623) @[ifu_bp_ctl.scala 443:110] + node _T_19625 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19626 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19627 = eq(_T_19626, UInt<1>("h01")) @[ifu_bp_ctl.scala 444:74] + node _T_19628 = and(_T_19625, _T_19627) @[ifu_bp_ctl.scala 444:22] + node _T_19629 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19630 = eq(_T_19629, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_19631 = or(_T_19630, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19632 = and(_T_19628, _T_19631) @[ifu_bp_ctl.scala 444:87] + node _T_19633 = or(_T_19624, _T_19632) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][15][1] <= _T_19633 @[ifu_bp_ctl.scala 443:27] + node _T_19634 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19635 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19636 = eq(_T_19635, UInt<2>("h02")) @[ifu_bp_ctl.scala 443:97] + node _T_19637 = and(_T_19634, _T_19636) @[ifu_bp_ctl.scala 443:45] + node _T_19638 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19639 = eq(_T_19638, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_19640 = or(_T_19639, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19641 = and(_T_19637, _T_19640) @[ifu_bp_ctl.scala 443:110] + node _T_19642 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19643 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19644 = eq(_T_19643, UInt<2>("h02")) @[ifu_bp_ctl.scala 444:74] + node _T_19645 = and(_T_19642, _T_19644) @[ifu_bp_ctl.scala 444:22] + node _T_19646 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19647 = eq(_T_19646, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_19648 = or(_T_19647, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19649 = and(_T_19645, _T_19648) @[ifu_bp_ctl.scala 444:87] + node _T_19650 = or(_T_19641, _T_19649) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][15][2] <= _T_19650 @[ifu_bp_ctl.scala 443:27] + node _T_19651 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19652 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19653 = eq(_T_19652, UInt<2>("h03")) @[ifu_bp_ctl.scala 443:97] + node _T_19654 = and(_T_19651, _T_19653) @[ifu_bp_ctl.scala 443:45] + node _T_19655 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19656 = eq(_T_19655, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_19657 = or(_T_19656, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19658 = and(_T_19654, _T_19657) @[ifu_bp_ctl.scala 443:110] + node _T_19659 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19660 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19661 = eq(_T_19660, UInt<2>("h03")) @[ifu_bp_ctl.scala 444:74] + node _T_19662 = and(_T_19659, _T_19661) @[ifu_bp_ctl.scala 444:22] + node _T_19663 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19664 = eq(_T_19663, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_19665 = or(_T_19664, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19666 = and(_T_19662, _T_19665) @[ifu_bp_ctl.scala 444:87] + node _T_19667 = or(_T_19658, _T_19666) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][15][3] <= _T_19667 @[ifu_bp_ctl.scala 443:27] + node _T_19668 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19669 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19670 = eq(_T_19669, UInt<3>("h04")) @[ifu_bp_ctl.scala 443:97] + node _T_19671 = and(_T_19668, _T_19670) @[ifu_bp_ctl.scala 443:45] + node _T_19672 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19673 = eq(_T_19672, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_19674 = or(_T_19673, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19675 = and(_T_19671, _T_19674) @[ifu_bp_ctl.scala 443:110] + node _T_19676 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19677 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19678 = eq(_T_19677, UInt<3>("h04")) @[ifu_bp_ctl.scala 444:74] + node _T_19679 = and(_T_19676, _T_19678) @[ifu_bp_ctl.scala 444:22] + node _T_19680 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19681 = eq(_T_19680, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_19682 = or(_T_19681, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19683 = and(_T_19679, _T_19682) @[ifu_bp_ctl.scala 444:87] + node _T_19684 = or(_T_19675, _T_19683) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][15][4] <= _T_19684 @[ifu_bp_ctl.scala 443:27] + node _T_19685 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19686 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19687 = eq(_T_19686, UInt<3>("h05")) @[ifu_bp_ctl.scala 443:97] + node _T_19688 = and(_T_19685, _T_19687) @[ifu_bp_ctl.scala 443:45] + node _T_19689 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19690 = eq(_T_19689, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_19691 = or(_T_19690, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19692 = and(_T_19688, _T_19691) @[ifu_bp_ctl.scala 443:110] + node _T_19693 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19694 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19695 = eq(_T_19694, UInt<3>("h05")) @[ifu_bp_ctl.scala 444:74] + node _T_19696 = and(_T_19693, _T_19695) @[ifu_bp_ctl.scala 444:22] + node _T_19697 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19698 = eq(_T_19697, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_19699 = or(_T_19698, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19700 = and(_T_19696, _T_19699) @[ifu_bp_ctl.scala 444:87] + node _T_19701 = or(_T_19692, _T_19700) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][15][5] <= _T_19701 @[ifu_bp_ctl.scala 443:27] + node _T_19702 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19703 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19704 = eq(_T_19703, UInt<3>("h06")) @[ifu_bp_ctl.scala 443:97] + node _T_19705 = and(_T_19702, _T_19704) @[ifu_bp_ctl.scala 443:45] + node _T_19706 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19707 = eq(_T_19706, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_19708 = or(_T_19707, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19709 = and(_T_19705, _T_19708) @[ifu_bp_ctl.scala 443:110] + node _T_19710 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19711 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19712 = eq(_T_19711, UInt<3>("h06")) @[ifu_bp_ctl.scala 444:74] + node _T_19713 = and(_T_19710, _T_19712) @[ifu_bp_ctl.scala 444:22] + node _T_19714 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19715 = eq(_T_19714, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_19716 = or(_T_19715, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19717 = and(_T_19713, _T_19716) @[ifu_bp_ctl.scala 444:87] + node _T_19718 = or(_T_19709, _T_19717) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][15][6] <= _T_19718 @[ifu_bp_ctl.scala 443:27] + node _T_19719 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19720 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19721 = eq(_T_19720, UInt<3>("h07")) @[ifu_bp_ctl.scala 443:97] + node _T_19722 = and(_T_19719, _T_19721) @[ifu_bp_ctl.scala 443:45] + node _T_19723 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19724 = eq(_T_19723, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_19725 = or(_T_19724, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19726 = and(_T_19722, _T_19725) @[ifu_bp_ctl.scala 443:110] + node _T_19727 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19728 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19729 = eq(_T_19728, UInt<3>("h07")) @[ifu_bp_ctl.scala 444:74] + node _T_19730 = and(_T_19727, _T_19729) @[ifu_bp_ctl.scala 444:22] + node _T_19731 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19732 = eq(_T_19731, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_19733 = or(_T_19732, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19734 = and(_T_19730, _T_19733) @[ifu_bp_ctl.scala 444:87] + node _T_19735 = or(_T_19726, _T_19734) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][15][7] <= _T_19735 @[ifu_bp_ctl.scala 443:27] + node _T_19736 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19737 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19738 = eq(_T_19737, UInt<4>("h08")) @[ifu_bp_ctl.scala 443:97] + node _T_19739 = and(_T_19736, _T_19738) @[ifu_bp_ctl.scala 443:45] + node _T_19740 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19741 = eq(_T_19740, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_19742 = or(_T_19741, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19743 = and(_T_19739, _T_19742) @[ifu_bp_ctl.scala 443:110] + node _T_19744 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19745 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19746 = eq(_T_19745, UInt<4>("h08")) @[ifu_bp_ctl.scala 444:74] + node _T_19747 = and(_T_19744, _T_19746) @[ifu_bp_ctl.scala 444:22] + node _T_19748 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19749 = eq(_T_19748, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_19750 = or(_T_19749, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19751 = and(_T_19747, _T_19750) @[ifu_bp_ctl.scala 444:87] + node _T_19752 = or(_T_19743, _T_19751) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][15][8] <= _T_19752 @[ifu_bp_ctl.scala 443:27] + node _T_19753 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19754 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19755 = eq(_T_19754, UInt<4>("h09")) @[ifu_bp_ctl.scala 443:97] + node _T_19756 = and(_T_19753, _T_19755) @[ifu_bp_ctl.scala 443:45] + node _T_19757 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19758 = eq(_T_19757, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_19759 = or(_T_19758, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19760 = and(_T_19756, _T_19759) @[ifu_bp_ctl.scala 443:110] + node _T_19761 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19762 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19763 = eq(_T_19762, UInt<4>("h09")) @[ifu_bp_ctl.scala 444:74] + node _T_19764 = and(_T_19761, _T_19763) @[ifu_bp_ctl.scala 444:22] + node _T_19765 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19766 = eq(_T_19765, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_19767 = or(_T_19766, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19768 = and(_T_19764, _T_19767) @[ifu_bp_ctl.scala 444:87] + node _T_19769 = or(_T_19760, _T_19768) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][15][9] <= _T_19769 @[ifu_bp_ctl.scala 443:27] + node _T_19770 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19771 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19772 = eq(_T_19771, UInt<4>("h0a")) @[ifu_bp_ctl.scala 443:97] + node _T_19773 = and(_T_19770, _T_19772) @[ifu_bp_ctl.scala 443:45] + node _T_19774 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19775 = eq(_T_19774, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_19776 = or(_T_19775, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19777 = and(_T_19773, _T_19776) @[ifu_bp_ctl.scala 443:110] + node _T_19778 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19779 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19780 = eq(_T_19779, UInt<4>("h0a")) @[ifu_bp_ctl.scala 444:74] + node _T_19781 = and(_T_19778, _T_19780) @[ifu_bp_ctl.scala 444:22] + node _T_19782 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19783 = eq(_T_19782, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_19784 = or(_T_19783, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19785 = and(_T_19781, _T_19784) @[ifu_bp_ctl.scala 444:87] + node _T_19786 = or(_T_19777, _T_19785) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][15][10] <= _T_19786 @[ifu_bp_ctl.scala 443:27] + node _T_19787 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19788 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19789 = eq(_T_19788, UInt<4>("h0b")) @[ifu_bp_ctl.scala 443:97] + node _T_19790 = and(_T_19787, _T_19789) @[ifu_bp_ctl.scala 443:45] + node _T_19791 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19792 = eq(_T_19791, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_19793 = or(_T_19792, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19794 = and(_T_19790, _T_19793) @[ifu_bp_ctl.scala 443:110] + node _T_19795 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19796 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19797 = eq(_T_19796, UInt<4>("h0b")) @[ifu_bp_ctl.scala 444:74] + node _T_19798 = and(_T_19795, _T_19797) @[ifu_bp_ctl.scala 444:22] + node _T_19799 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19800 = eq(_T_19799, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_19801 = or(_T_19800, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19802 = and(_T_19798, _T_19801) @[ifu_bp_ctl.scala 444:87] + node _T_19803 = or(_T_19794, _T_19802) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][15][11] <= _T_19803 @[ifu_bp_ctl.scala 443:27] + node _T_19804 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19805 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19806 = eq(_T_19805, UInt<4>("h0c")) @[ifu_bp_ctl.scala 443:97] + node _T_19807 = and(_T_19804, _T_19806) @[ifu_bp_ctl.scala 443:45] + node _T_19808 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19809 = eq(_T_19808, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_19810 = or(_T_19809, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19811 = and(_T_19807, _T_19810) @[ifu_bp_ctl.scala 443:110] + node _T_19812 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19813 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19814 = eq(_T_19813, UInt<4>("h0c")) @[ifu_bp_ctl.scala 444:74] + node _T_19815 = and(_T_19812, _T_19814) @[ifu_bp_ctl.scala 444:22] + node _T_19816 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19817 = eq(_T_19816, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_19818 = or(_T_19817, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19819 = and(_T_19815, _T_19818) @[ifu_bp_ctl.scala 444:87] + node _T_19820 = or(_T_19811, _T_19819) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][15][12] <= _T_19820 @[ifu_bp_ctl.scala 443:27] + node _T_19821 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19822 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19823 = eq(_T_19822, UInt<4>("h0d")) @[ifu_bp_ctl.scala 443:97] + node _T_19824 = and(_T_19821, _T_19823) @[ifu_bp_ctl.scala 443:45] + node _T_19825 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19826 = eq(_T_19825, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_19827 = or(_T_19826, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19828 = and(_T_19824, _T_19827) @[ifu_bp_ctl.scala 443:110] + node _T_19829 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19830 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19831 = eq(_T_19830, UInt<4>("h0d")) @[ifu_bp_ctl.scala 444:74] + node _T_19832 = and(_T_19829, _T_19831) @[ifu_bp_ctl.scala 444:22] + node _T_19833 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19834 = eq(_T_19833, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_19835 = or(_T_19834, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19836 = and(_T_19832, _T_19835) @[ifu_bp_ctl.scala 444:87] + node _T_19837 = or(_T_19828, _T_19836) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][15][13] <= _T_19837 @[ifu_bp_ctl.scala 443:27] + node _T_19838 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19839 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19840 = eq(_T_19839, UInt<4>("h0e")) @[ifu_bp_ctl.scala 443:97] + node _T_19841 = and(_T_19838, _T_19840) @[ifu_bp_ctl.scala 443:45] + node _T_19842 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19843 = eq(_T_19842, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_19844 = or(_T_19843, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19845 = and(_T_19841, _T_19844) @[ifu_bp_ctl.scala 443:110] + node _T_19846 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19847 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19848 = eq(_T_19847, UInt<4>("h0e")) @[ifu_bp_ctl.scala 444:74] + node _T_19849 = and(_T_19846, _T_19848) @[ifu_bp_ctl.scala 444:22] + node _T_19850 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19851 = eq(_T_19850, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_19852 = or(_T_19851, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19853 = and(_T_19849, _T_19852) @[ifu_bp_ctl.scala 444:87] + node _T_19854 = or(_T_19845, _T_19853) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][15][14] <= _T_19854 @[ifu_bp_ctl.scala 443:27] + node _T_19855 = bits(bht_wr_en0, 1, 1) @[ifu_bp_ctl.scala 443:41] + node _T_19856 = bits(bht_wr_addr0, 3, 0) @[ifu_bp_ctl.scala 443:60] + node _T_19857 = eq(_T_19856, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:97] + node _T_19858 = and(_T_19855, _T_19857) @[ifu_bp_ctl.scala 443:45] + node _T_19859 = bits(bht_wr_addr0, 7, 4) @[ifu_bp_ctl.scala 443:126] + node _T_19860 = eq(_T_19859, UInt<4>("h0f")) @[ifu_bp_ctl.scala 443:186] + node _T_19861 = or(_T_19860, UInt<1>("h00")) @[ifu_bp_ctl.scala 443:199] + node _T_19862 = and(_T_19858, _T_19861) @[ifu_bp_ctl.scala 443:110] + node _T_19863 = bits(bht_wr_en2, 1, 1) @[ifu_bp_ctl.scala 444:18] + node _T_19864 = bits(bht_wr_addr2, 3, 0) @[ifu_bp_ctl.scala 444:37] + node _T_19865 = eq(_T_19864, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:74] + node _T_19866 = and(_T_19863, _T_19865) @[ifu_bp_ctl.scala 444:22] + node _T_19867 = bits(bht_wr_addr2, 7, 4) @[ifu_bp_ctl.scala 444:103] + node _T_19868 = eq(_T_19867, UInt<4>("h0f")) @[ifu_bp_ctl.scala 444:163] + node _T_19869 = or(_T_19868, UInt<1>("h00")) @[ifu_bp_ctl.scala 444:176] + node _T_19870 = and(_T_19866, _T_19869) @[ifu_bp_ctl.scala 444:87] + node _T_19871 = or(_T_19862, _T_19870) @[ifu_bp_ctl.scala 443:223] + bht_bank_sel[1][15][15] <= _T_19871 @[ifu_bp_ctl.scala 443:27] + wire bht_bank_rd_data_out : UInt<2>[256][2] @[ifu_bp_ctl.scala 448:34] reg _T_19872 : UInt, rvclkhdr_522.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][0][0] : @[Reg.scala 28:19] _T_19872 <= bht_bank_wr_data_0_0_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][0] <= _T_19872 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][0] <= _T_19872 @[ifu_bp_ctl.scala 450:39] reg _T_19873 : UInt, rvclkhdr_522.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][0][1] : @[Reg.scala 28:19] _T_19873 <= bht_bank_wr_data_0_0_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][1] <= _T_19873 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][1] <= _T_19873 @[ifu_bp_ctl.scala 450:39] reg _T_19874 : UInt, rvclkhdr_522.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][0][2] : @[Reg.scala 28:19] _T_19874 <= bht_bank_wr_data_0_0_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][2] <= _T_19874 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][2] <= _T_19874 @[ifu_bp_ctl.scala 450:39] reg _T_19875 : UInt, rvclkhdr_522.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][0][3] : @[Reg.scala 28:19] _T_19875 <= bht_bank_wr_data_0_0_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][3] <= _T_19875 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][3] <= _T_19875 @[ifu_bp_ctl.scala 450:39] reg _T_19876 : UInt, rvclkhdr_522.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][0][4] : @[Reg.scala 28:19] _T_19876 <= bht_bank_wr_data_0_0_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][4] <= _T_19876 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][4] <= _T_19876 @[ifu_bp_ctl.scala 450:39] reg _T_19877 : UInt, rvclkhdr_522.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][0][5] : @[Reg.scala 28:19] _T_19877 <= bht_bank_wr_data_0_0_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][5] <= _T_19877 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][5] <= _T_19877 @[ifu_bp_ctl.scala 450:39] reg _T_19878 : UInt, rvclkhdr_522.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][0][6] : @[Reg.scala 28:19] _T_19878 <= bht_bank_wr_data_0_0_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][6] <= _T_19878 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][6] <= _T_19878 @[ifu_bp_ctl.scala 450:39] reg _T_19879 : UInt, rvclkhdr_522.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][0][7] : @[Reg.scala 28:19] _T_19879 <= bht_bank_wr_data_0_0_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][7] <= _T_19879 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][7] <= _T_19879 @[ifu_bp_ctl.scala 450:39] reg _T_19880 : UInt, rvclkhdr_522.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][0][8] : @[Reg.scala 28:19] _T_19880 <= bht_bank_wr_data_0_0_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][8] <= _T_19880 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][8] <= _T_19880 @[ifu_bp_ctl.scala 450:39] reg _T_19881 : UInt, rvclkhdr_522.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][0][9] : @[Reg.scala 28:19] _T_19881 <= bht_bank_wr_data_0_0_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][9] <= _T_19881 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][9] <= _T_19881 @[ifu_bp_ctl.scala 450:39] reg _T_19882 : UInt, rvclkhdr_522.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][0][10] : @[Reg.scala 28:19] _T_19882 <= bht_bank_wr_data_0_0_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][10] <= _T_19882 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][10] <= _T_19882 @[ifu_bp_ctl.scala 450:39] reg _T_19883 : UInt, rvclkhdr_522.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][0][11] : @[Reg.scala 28:19] _T_19883 <= bht_bank_wr_data_0_0_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][11] <= _T_19883 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][11] <= _T_19883 @[ifu_bp_ctl.scala 450:39] reg _T_19884 : UInt, rvclkhdr_522.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][0][12] : @[Reg.scala 28:19] _T_19884 <= bht_bank_wr_data_0_0_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][12] <= _T_19884 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][12] <= _T_19884 @[ifu_bp_ctl.scala 450:39] reg _T_19885 : UInt, rvclkhdr_522.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][0][13] : @[Reg.scala 28:19] _T_19885 <= bht_bank_wr_data_0_0_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][13] <= _T_19885 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][13] <= _T_19885 @[ifu_bp_ctl.scala 450:39] reg _T_19886 : UInt, rvclkhdr_522.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][0][14] : @[Reg.scala 28:19] _T_19886 <= bht_bank_wr_data_0_0_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][14] <= _T_19886 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][14] <= _T_19886 @[ifu_bp_ctl.scala 450:39] reg _T_19887 : UInt, rvclkhdr_522.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][0][15] : @[Reg.scala 28:19] _T_19887 <= bht_bank_wr_data_0_0_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][15] <= _T_19887 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][15] <= _T_19887 @[ifu_bp_ctl.scala 450:39] reg _T_19888 : UInt, rvclkhdr_523.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][1][0] : @[Reg.scala 28:19] _T_19888 <= bht_bank_wr_data_0_1_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][16] <= _T_19888 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][16] <= _T_19888 @[ifu_bp_ctl.scala 450:39] reg _T_19889 : UInt, rvclkhdr_523.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][1][1] : @[Reg.scala 28:19] _T_19889 <= bht_bank_wr_data_0_1_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][17] <= _T_19889 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][17] <= _T_19889 @[ifu_bp_ctl.scala 450:39] reg _T_19890 : UInt, rvclkhdr_523.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][1][2] : @[Reg.scala 28:19] _T_19890 <= bht_bank_wr_data_0_1_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][18] <= _T_19890 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][18] <= _T_19890 @[ifu_bp_ctl.scala 450:39] reg _T_19891 : UInt, rvclkhdr_523.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][1][3] : @[Reg.scala 28:19] _T_19891 <= bht_bank_wr_data_0_1_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][19] <= _T_19891 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][19] <= _T_19891 @[ifu_bp_ctl.scala 450:39] reg _T_19892 : UInt, rvclkhdr_523.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][1][4] : @[Reg.scala 28:19] _T_19892 <= bht_bank_wr_data_0_1_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][20] <= _T_19892 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][20] <= _T_19892 @[ifu_bp_ctl.scala 450:39] reg _T_19893 : UInt, rvclkhdr_523.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][1][5] : @[Reg.scala 28:19] _T_19893 <= bht_bank_wr_data_0_1_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][21] <= _T_19893 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][21] <= _T_19893 @[ifu_bp_ctl.scala 450:39] reg _T_19894 : UInt, rvclkhdr_523.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][1][6] : @[Reg.scala 28:19] _T_19894 <= bht_bank_wr_data_0_1_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][22] <= _T_19894 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][22] <= _T_19894 @[ifu_bp_ctl.scala 450:39] reg _T_19895 : UInt, rvclkhdr_523.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][1][7] : @[Reg.scala 28:19] _T_19895 <= bht_bank_wr_data_0_1_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][23] <= _T_19895 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][23] <= _T_19895 @[ifu_bp_ctl.scala 450:39] reg _T_19896 : UInt, rvclkhdr_523.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][1][8] : @[Reg.scala 28:19] _T_19896 <= bht_bank_wr_data_0_1_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][24] <= _T_19896 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][24] <= _T_19896 @[ifu_bp_ctl.scala 450:39] reg _T_19897 : UInt, rvclkhdr_523.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][1][9] : @[Reg.scala 28:19] _T_19897 <= bht_bank_wr_data_0_1_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][25] <= _T_19897 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][25] <= _T_19897 @[ifu_bp_ctl.scala 450:39] reg _T_19898 : UInt, rvclkhdr_523.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][1][10] : @[Reg.scala 28:19] _T_19898 <= bht_bank_wr_data_0_1_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][26] <= _T_19898 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][26] <= _T_19898 @[ifu_bp_ctl.scala 450:39] reg _T_19899 : UInt, rvclkhdr_523.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][1][11] : @[Reg.scala 28:19] _T_19899 <= bht_bank_wr_data_0_1_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][27] <= _T_19899 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][27] <= _T_19899 @[ifu_bp_ctl.scala 450:39] reg _T_19900 : UInt, rvclkhdr_523.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][1][12] : @[Reg.scala 28:19] _T_19900 <= bht_bank_wr_data_0_1_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][28] <= _T_19900 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][28] <= _T_19900 @[ifu_bp_ctl.scala 450:39] reg _T_19901 : UInt, rvclkhdr_523.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][1][13] : @[Reg.scala 28:19] _T_19901 <= bht_bank_wr_data_0_1_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][29] <= _T_19901 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][29] <= _T_19901 @[ifu_bp_ctl.scala 450:39] reg _T_19902 : UInt, rvclkhdr_523.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][1][14] : @[Reg.scala 28:19] _T_19902 <= bht_bank_wr_data_0_1_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][30] <= _T_19902 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][30] <= _T_19902 @[ifu_bp_ctl.scala 450:39] reg _T_19903 : UInt, rvclkhdr_523.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][1][15] : @[Reg.scala 28:19] _T_19903 <= bht_bank_wr_data_0_1_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][31] <= _T_19903 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][31] <= _T_19903 @[ifu_bp_ctl.scala 450:39] reg _T_19904 : UInt, rvclkhdr_524.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][2][0] : @[Reg.scala 28:19] _T_19904 <= bht_bank_wr_data_0_2_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][32] <= _T_19904 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][32] <= _T_19904 @[ifu_bp_ctl.scala 450:39] reg _T_19905 : UInt, rvclkhdr_524.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][2][1] : @[Reg.scala 28:19] _T_19905 <= bht_bank_wr_data_0_2_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][33] <= _T_19905 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][33] <= _T_19905 @[ifu_bp_ctl.scala 450:39] reg _T_19906 : UInt, rvclkhdr_524.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][2][2] : @[Reg.scala 28:19] _T_19906 <= bht_bank_wr_data_0_2_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][34] <= _T_19906 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][34] <= _T_19906 @[ifu_bp_ctl.scala 450:39] reg _T_19907 : UInt, rvclkhdr_524.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][2][3] : @[Reg.scala 28:19] _T_19907 <= bht_bank_wr_data_0_2_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][35] <= _T_19907 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][35] <= _T_19907 @[ifu_bp_ctl.scala 450:39] reg _T_19908 : UInt, rvclkhdr_524.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][2][4] : @[Reg.scala 28:19] _T_19908 <= bht_bank_wr_data_0_2_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][36] <= _T_19908 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][36] <= _T_19908 @[ifu_bp_ctl.scala 450:39] reg _T_19909 : UInt, rvclkhdr_524.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][2][5] : @[Reg.scala 28:19] _T_19909 <= bht_bank_wr_data_0_2_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][37] <= _T_19909 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][37] <= _T_19909 @[ifu_bp_ctl.scala 450:39] reg _T_19910 : UInt, rvclkhdr_524.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][2][6] : @[Reg.scala 28:19] _T_19910 <= bht_bank_wr_data_0_2_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][38] <= _T_19910 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][38] <= _T_19910 @[ifu_bp_ctl.scala 450:39] reg _T_19911 : UInt, rvclkhdr_524.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][2][7] : @[Reg.scala 28:19] _T_19911 <= bht_bank_wr_data_0_2_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][39] <= _T_19911 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][39] <= _T_19911 @[ifu_bp_ctl.scala 450:39] reg _T_19912 : UInt, rvclkhdr_524.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][2][8] : @[Reg.scala 28:19] _T_19912 <= bht_bank_wr_data_0_2_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][40] <= _T_19912 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][40] <= _T_19912 @[ifu_bp_ctl.scala 450:39] reg _T_19913 : UInt, rvclkhdr_524.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][2][9] : @[Reg.scala 28:19] _T_19913 <= bht_bank_wr_data_0_2_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][41] <= _T_19913 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][41] <= _T_19913 @[ifu_bp_ctl.scala 450:39] reg _T_19914 : UInt, rvclkhdr_524.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][2][10] : @[Reg.scala 28:19] _T_19914 <= bht_bank_wr_data_0_2_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][42] <= _T_19914 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][42] <= _T_19914 @[ifu_bp_ctl.scala 450:39] reg _T_19915 : UInt, rvclkhdr_524.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][2][11] : @[Reg.scala 28:19] _T_19915 <= bht_bank_wr_data_0_2_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][43] <= _T_19915 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][43] <= _T_19915 @[ifu_bp_ctl.scala 450:39] reg _T_19916 : UInt, rvclkhdr_524.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][2][12] : @[Reg.scala 28:19] _T_19916 <= bht_bank_wr_data_0_2_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][44] <= _T_19916 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][44] <= _T_19916 @[ifu_bp_ctl.scala 450:39] reg _T_19917 : UInt, rvclkhdr_524.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][2][13] : @[Reg.scala 28:19] _T_19917 <= bht_bank_wr_data_0_2_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][45] <= _T_19917 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][45] <= _T_19917 @[ifu_bp_ctl.scala 450:39] reg _T_19918 : UInt, rvclkhdr_524.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][2][14] : @[Reg.scala 28:19] _T_19918 <= bht_bank_wr_data_0_2_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][46] <= _T_19918 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][46] <= _T_19918 @[ifu_bp_ctl.scala 450:39] reg _T_19919 : UInt, rvclkhdr_524.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][2][15] : @[Reg.scala 28:19] _T_19919 <= bht_bank_wr_data_0_2_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][47] <= _T_19919 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][47] <= _T_19919 @[ifu_bp_ctl.scala 450:39] reg _T_19920 : UInt, rvclkhdr_525.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][3][0] : @[Reg.scala 28:19] _T_19920 <= bht_bank_wr_data_0_3_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][48] <= _T_19920 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][48] <= _T_19920 @[ifu_bp_ctl.scala 450:39] reg _T_19921 : UInt, rvclkhdr_525.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][3][1] : @[Reg.scala 28:19] _T_19921 <= bht_bank_wr_data_0_3_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][49] <= _T_19921 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][49] <= _T_19921 @[ifu_bp_ctl.scala 450:39] reg _T_19922 : UInt, rvclkhdr_525.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][3][2] : @[Reg.scala 28:19] _T_19922 <= bht_bank_wr_data_0_3_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][50] <= _T_19922 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][50] <= _T_19922 @[ifu_bp_ctl.scala 450:39] reg _T_19923 : UInt, rvclkhdr_525.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][3][3] : @[Reg.scala 28:19] _T_19923 <= bht_bank_wr_data_0_3_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][51] <= _T_19923 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][51] <= _T_19923 @[ifu_bp_ctl.scala 450:39] reg _T_19924 : UInt, rvclkhdr_525.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][3][4] : @[Reg.scala 28:19] _T_19924 <= bht_bank_wr_data_0_3_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][52] <= _T_19924 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][52] <= _T_19924 @[ifu_bp_ctl.scala 450:39] reg _T_19925 : UInt, rvclkhdr_525.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][3][5] : @[Reg.scala 28:19] _T_19925 <= bht_bank_wr_data_0_3_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][53] <= _T_19925 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][53] <= _T_19925 @[ifu_bp_ctl.scala 450:39] reg _T_19926 : UInt, rvclkhdr_525.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][3][6] : @[Reg.scala 28:19] _T_19926 <= bht_bank_wr_data_0_3_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][54] <= _T_19926 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][54] <= _T_19926 @[ifu_bp_ctl.scala 450:39] reg _T_19927 : UInt, rvclkhdr_525.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][3][7] : @[Reg.scala 28:19] _T_19927 <= bht_bank_wr_data_0_3_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][55] <= _T_19927 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][55] <= _T_19927 @[ifu_bp_ctl.scala 450:39] reg _T_19928 : UInt, rvclkhdr_525.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][3][8] : @[Reg.scala 28:19] _T_19928 <= bht_bank_wr_data_0_3_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][56] <= _T_19928 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][56] <= _T_19928 @[ifu_bp_ctl.scala 450:39] reg _T_19929 : UInt, rvclkhdr_525.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][3][9] : @[Reg.scala 28:19] _T_19929 <= bht_bank_wr_data_0_3_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][57] <= _T_19929 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][57] <= _T_19929 @[ifu_bp_ctl.scala 450:39] reg _T_19930 : UInt, rvclkhdr_525.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][3][10] : @[Reg.scala 28:19] _T_19930 <= bht_bank_wr_data_0_3_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][58] <= _T_19930 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][58] <= _T_19930 @[ifu_bp_ctl.scala 450:39] reg _T_19931 : UInt, rvclkhdr_525.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][3][11] : @[Reg.scala 28:19] _T_19931 <= bht_bank_wr_data_0_3_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][59] <= _T_19931 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][59] <= _T_19931 @[ifu_bp_ctl.scala 450:39] reg _T_19932 : UInt, rvclkhdr_525.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][3][12] : @[Reg.scala 28:19] _T_19932 <= bht_bank_wr_data_0_3_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][60] <= _T_19932 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][60] <= _T_19932 @[ifu_bp_ctl.scala 450:39] reg _T_19933 : UInt, rvclkhdr_525.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][3][13] : @[Reg.scala 28:19] _T_19933 <= bht_bank_wr_data_0_3_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][61] <= _T_19933 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][61] <= _T_19933 @[ifu_bp_ctl.scala 450:39] reg _T_19934 : UInt, rvclkhdr_525.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][3][14] : @[Reg.scala 28:19] _T_19934 <= bht_bank_wr_data_0_3_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][62] <= _T_19934 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][62] <= _T_19934 @[ifu_bp_ctl.scala 450:39] reg _T_19935 : UInt, rvclkhdr_525.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][3][15] : @[Reg.scala 28:19] _T_19935 <= bht_bank_wr_data_0_3_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][63] <= _T_19935 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][63] <= _T_19935 @[ifu_bp_ctl.scala 450:39] reg _T_19936 : UInt, rvclkhdr_526.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][4][0] : @[Reg.scala 28:19] _T_19936 <= bht_bank_wr_data_0_4_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][64] <= _T_19936 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][64] <= _T_19936 @[ifu_bp_ctl.scala 450:39] reg _T_19937 : UInt, rvclkhdr_526.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][4][1] : @[Reg.scala 28:19] _T_19937 <= bht_bank_wr_data_0_4_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][65] <= _T_19937 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][65] <= _T_19937 @[ifu_bp_ctl.scala 450:39] reg _T_19938 : UInt, rvclkhdr_526.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][4][2] : @[Reg.scala 28:19] _T_19938 <= bht_bank_wr_data_0_4_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][66] <= _T_19938 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][66] <= _T_19938 @[ifu_bp_ctl.scala 450:39] reg _T_19939 : UInt, rvclkhdr_526.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][4][3] : @[Reg.scala 28:19] _T_19939 <= bht_bank_wr_data_0_4_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][67] <= _T_19939 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][67] <= _T_19939 @[ifu_bp_ctl.scala 450:39] reg _T_19940 : UInt, rvclkhdr_526.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][4][4] : @[Reg.scala 28:19] _T_19940 <= bht_bank_wr_data_0_4_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][68] <= _T_19940 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][68] <= _T_19940 @[ifu_bp_ctl.scala 450:39] reg _T_19941 : UInt, rvclkhdr_526.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][4][5] : @[Reg.scala 28:19] _T_19941 <= bht_bank_wr_data_0_4_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][69] <= _T_19941 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][69] <= _T_19941 @[ifu_bp_ctl.scala 450:39] reg _T_19942 : UInt, rvclkhdr_526.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][4][6] : @[Reg.scala 28:19] _T_19942 <= bht_bank_wr_data_0_4_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][70] <= _T_19942 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][70] <= _T_19942 @[ifu_bp_ctl.scala 450:39] reg _T_19943 : UInt, rvclkhdr_526.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][4][7] : @[Reg.scala 28:19] _T_19943 <= bht_bank_wr_data_0_4_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][71] <= _T_19943 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][71] <= _T_19943 @[ifu_bp_ctl.scala 450:39] reg _T_19944 : UInt, rvclkhdr_526.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][4][8] : @[Reg.scala 28:19] _T_19944 <= bht_bank_wr_data_0_4_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][72] <= _T_19944 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][72] <= _T_19944 @[ifu_bp_ctl.scala 450:39] reg _T_19945 : UInt, rvclkhdr_526.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][4][9] : @[Reg.scala 28:19] _T_19945 <= bht_bank_wr_data_0_4_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][73] <= _T_19945 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][73] <= _T_19945 @[ifu_bp_ctl.scala 450:39] reg _T_19946 : UInt, rvclkhdr_526.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][4][10] : @[Reg.scala 28:19] _T_19946 <= bht_bank_wr_data_0_4_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][74] <= _T_19946 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][74] <= _T_19946 @[ifu_bp_ctl.scala 450:39] reg _T_19947 : UInt, rvclkhdr_526.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][4][11] : @[Reg.scala 28:19] _T_19947 <= bht_bank_wr_data_0_4_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][75] <= _T_19947 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][75] <= _T_19947 @[ifu_bp_ctl.scala 450:39] reg _T_19948 : UInt, rvclkhdr_526.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][4][12] : @[Reg.scala 28:19] _T_19948 <= bht_bank_wr_data_0_4_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][76] <= _T_19948 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][76] <= _T_19948 @[ifu_bp_ctl.scala 450:39] reg _T_19949 : UInt, rvclkhdr_526.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][4][13] : @[Reg.scala 28:19] _T_19949 <= bht_bank_wr_data_0_4_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][77] <= _T_19949 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][77] <= _T_19949 @[ifu_bp_ctl.scala 450:39] reg _T_19950 : UInt, rvclkhdr_526.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][4][14] : @[Reg.scala 28:19] _T_19950 <= bht_bank_wr_data_0_4_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][78] <= _T_19950 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][78] <= _T_19950 @[ifu_bp_ctl.scala 450:39] reg _T_19951 : UInt, rvclkhdr_526.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][4][15] : @[Reg.scala 28:19] _T_19951 <= bht_bank_wr_data_0_4_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][79] <= _T_19951 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][79] <= _T_19951 @[ifu_bp_ctl.scala 450:39] reg _T_19952 : UInt, rvclkhdr_527.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][5][0] : @[Reg.scala 28:19] _T_19952 <= bht_bank_wr_data_0_5_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][80] <= _T_19952 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][80] <= _T_19952 @[ifu_bp_ctl.scala 450:39] reg _T_19953 : UInt, rvclkhdr_527.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][5][1] : @[Reg.scala 28:19] _T_19953 <= bht_bank_wr_data_0_5_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][81] <= _T_19953 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][81] <= _T_19953 @[ifu_bp_ctl.scala 450:39] reg _T_19954 : UInt, rvclkhdr_527.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][5][2] : @[Reg.scala 28:19] _T_19954 <= bht_bank_wr_data_0_5_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][82] <= _T_19954 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][82] <= _T_19954 @[ifu_bp_ctl.scala 450:39] reg _T_19955 : UInt, rvclkhdr_527.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][5][3] : @[Reg.scala 28:19] _T_19955 <= bht_bank_wr_data_0_5_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][83] <= _T_19955 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][83] <= _T_19955 @[ifu_bp_ctl.scala 450:39] reg _T_19956 : UInt, rvclkhdr_527.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][5][4] : @[Reg.scala 28:19] _T_19956 <= bht_bank_wr_data_0_5_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][84] <= _T_19956 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][84] <= _T_19956 @[ifu_bp_ctl.scala 450:39] reg _T_19957 : UInt, rvclkhdr_527.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][5][5] : @[Reg.scala 28:19] _T_19957 <= bht_bank_wr_data_0_5_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][85] <= _T_19957 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][85] <= _T_19957 @[ifu_bp_ctl.scala 450:39] reg _T_19958 : UInt, rvclkhdr_527.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][5][6] : @[Reg.scala 28:19] _T_19958 <= bht_bank_wr_data_0_5_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][86] <= _T_19958 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][86] <= _T_19958 @[ifu_bp_ctl.scala 450:39] reg _T_19959 : UInt, rvclkhdr_527.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][5][7] : @[Reg.scala 28:19] _T_19959 <= bht_bank_wr_data_0_5_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][87] <= _T_19959 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][87] <= _T_19959 @[ifu_bp_ctl.scala 450:39] reg _T_19960 : UInt, rvclkhdr_527.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][5][8] : @[Reg.scala 28:19] _T_19960 <= bht_bank_wr_data_0_5_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][88] <= _T_19960 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][88] <= _T_19960 @[ifu_bp_ctl.scala 450:39] reg _T_19961 : UInt, rvclkhdr_527.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][5][9] : @[Reg.scala 28:19] _T_19961 <= bht_bank_wr_data_0_5_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][89] <= _T_19961 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][89] <= _T_19961 @[ifu_bp_ctl.scala 450:39] reg _T_19962 : UInt, rvclkhdr_527.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][5][10] : @[Reg.scala 28:19] _T_19962 <= bht_bank_wr_data_0_5_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][90] <= _T_19962 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][90] <= _T_19962 @[ifu_bp_ctl.scala 450:39] reg _T_19963 : UInt, rvclkhdr_527.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][5][11] : @[Reg.scala 28:19] _T_19963 <= bht_bank_wr_data_0_5_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][91] <= _T_19963 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][91] <= _T_19963 @[ifu_bp_ctl.scala 450:39] reg _T_19964 : UInt, rvclkhdr_527.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][5][12] : @[Reg.scala 28:19] _T_19964 <= bht_bank_wr_data_0_5_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][92] <= _T_19964 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][92] <= _T_19964 @[ifu_bp_ctl.scala 450:39] reg _T_19965 : UInt, rvclkhdr_527.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][5][13] : @[Reg.scala 28:19] _T_19965 <= bht_bank_wr_data_0_5_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][93] <= _T_19965 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][93] <= _T_19965 @[ifu_bp_ctl.scala 450:39] reg _T_19966 : UInt, rvclkhdr_527.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][5][14] : @[Reg.scala 28:19] _T_19966 <= bht_bank_wr_data_0_5_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][94] <= _T_19966 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][94] <= _T_19966 @[ifu_bp_ctl.scala 450:39] reg _T_19967 : UInt, rvclkhdr_527.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][5][15] : @[Reg.scala 28:19] _T_19967 <= bht_bank_wr_data_0_5_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][95] <= _T_19967 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][95] <= _T_19967 @[ifu_bp_ctl.scala 450:39] reg _T_19968 : UInt, rvclkhdr_528.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][6][0] : @[Reg.scala 28:19] _T_19968 <= bht_bank_wr_data_0_6_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][96] <= _T_19968 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][96] <= _T_19968 @[ifu_bp_ctl.scala 450:39] reg _T_19969 : UInt, rvclkhdr_528.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][6][1] : @[Reg.scala 28:19] _T_19969 <= bht_bank_wr_data_0_6_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][97] <= _T_19969 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][97] <= _T_19969 @[ifu_bp_ctl.scala 450:39] reg _T_19970 : UInt, rvclkhdr_528.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][6][2] : @[Reg.scala 28:19] _T_19970 <= bht_bank_wr_data_0_6_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][98] <= _T_19970 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][98] <= _T_19970 @[ifu_bp_ctl.scala 450:39] reg _T_19971 : UInt, rvclkhdr_528.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][6][3] : @[Reg.scala 28:19] _T_19971 <= bht_bank_wr_data_0_6_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][99] <= _T_19971 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][99] <= _T_19971 @[ifu_bp_ctl.scala 450:39] reg _T_19972 : UInt, rvclkhdr_528.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][6][4] : @[Reg.scala 28:19] _T_19972 <= bht_bank_wr_data_0_6_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][100] <= _T_19972 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][100] <= _T_19972 @[ifu_bp_ctl.scala 450:39] reg _T_19973 : UInt, rvclkhdr_528.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][6][5] : @[Reg.scala 28:19] _T_19973 <= bht_bank_wr_data_0_6_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][101] <= _T_19973 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][101] <= _T_19973 @[ifu_bp_ctl.scala 450:39] reg _T_19974 : UInt, rvclkhdr_528.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][6][6] : @[Reg.scala 28:19] _T_19974 <= bht_bank_wr_data_0_6_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][102] <= _T_19974 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][102] <= _T_19974 @[ifu_bp_ctl.scala 450:39] reg _T_19975 : UInt, rvclkhdr_528.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][6][7] : @[Reg.scala 28:19] _T_19975 <= bht_bank_wr_data_0_6_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][103] <= _T_19975 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][103] <= _T_19975 @[ifu_bp_ctl.scala 450:39] reg _T_19976 : UInt, rvclkhdr_528.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][6][8] : @[Reg.scala 28:19] _T_19976 <= bht_bank_wr_data_0_6_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][104] <= _T_19976 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][104] <= _T_19976 @[ifu_bp_ctl.scala 450:39] reg _T_19977 : UInt, rvclkhdr_528.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][6][9] : @[Reg.scala 28:19] _T_19977 <= bht_bank_wr_data_0_6_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][105] <= _T_19977 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][105] <= _T_19977 @[ifu_bp_ctl.scala 450:39] reg _T_19978 : UInt, rvclkhdr_528.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][6][10] : @[Reg.scala 28:19] _T_19978 <= bht_bank_wr_data_0_6_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][106] <= _T_19978 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][106] <= _T_19978 @[ifu_bp_ctl.scala 450:39] reg _T_19979 : UInt, rvclkhdr_528.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][6][11] : @[Reg.scala 28:19] _T_19979 <= bht_bank_wr_data_0_6_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][107] <= _T_19979 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][107] <= _T_19979 @[ifu_bp_ctl.scala 450:39] reg _T_19980 : UInt, rvclkhdr_528.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][6][12] : @[Reg.scala 28:19] _T_19980 <= bht_bank_wr_data_0_6_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][108] <= _T_19980 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][108] <= _T_19980 @[ifu_bp_ctl.scala 450:39] reg _T_19981 : UInt, rvclkhdr_528.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][6][13] : @[Reg.scala 28:19] _T_19981 <= bht_bank_wr_data_0_6_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][109] <= _T_19981 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][109] <= _T_19981 @[ifu_bp_ctl.scala 450:39] reg _T_19982 : UInt, rvclkhdr_528.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][6][14] : @[Reg.scala 28:19] _T_19982 <= bht_bank_wr_data_0_6_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][110] <= _T_19982 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][110] <= _T_19982 @[ifu_bp_ctl.scala 450:39] reg _T_19983 : UInt, rvclkhdr_528.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][6][15] : @[Reg.scala 28:19] _T_19983 <= bht_bank_wr_data_0_6_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][111] <= _T_19983 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][111] <= _T_19983 @[ifu_bp_ctl.scala 450:39] reg _T_19984 : UInt, rvclkhdr_529.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][7][0] : @[Reg.scala 28:19] _T_19984 <= bht_bank_wr_data_0_7_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][112] <= _T_19984 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][112] <= _T_19984 @[ifu_bp_ctl.scala 450:39] reg _T_19985 : UInt, rvclkhdr_529.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][7][1] : @[Reg.scala 28:19] _T_19985 <= bht_bank_wr_data_0_7_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][113] <= _T_19985 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][113] <= _T_19985 @[ifu_bp_ctl.scala 450:39] reg _T_19986 : UInt, rvclkhdr_529.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][7][2] : @[Reg.scala 28:19] _T_19986 <= bht_bank_wr_data_0_7_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][114] <= _T_19986 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][114] <= _T_19986 @[ifu_bp_ctl.scala 450:39] reg _T_19987 : UInt, rvclkhdr_529.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][7][3] : @[Reg.scala 28:19] _T_19987 <= bht_bank_wr_data_0_7_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][115] <= _T_19987 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][115] <= _T_19987 @[ifu_bp_ctl.scala 450:39] reg _T_19988 : UInt, rvclkhdr_529.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][7][4] : @[Reg.scala 28:19] _T_19988 <= bht_bank_wr_data_0_7_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][116] <= _T_19988 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][116] <= _T_19988 @[ifu_bp_ctl.scala 450:39] reg _T_19989 : UInt, rvclkhdr_529.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][7][5] : @[Reg.scala 28:19] _T_19989 <= bht_bank_wr_data_0_7_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][117] <= _T_19989 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][117] <= _T_19989 @[ifu_bp_ctl.scala 450:39] reg _T_19990 : UInt, rvclkhdr_529.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][7][6] : @[Reg.scala 28:19] _T_19990 <= bht_bank_wr_data_0_7_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][118] <= _T_19990 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][118] <= _T_19990 @[ifu_bp_ctl.scala 450:39] reg _T_19991 : UInt, rvclkhdr_529.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][7][7] : @[Reg.scala 28:19] _T_19991 <= bht_bank_wr_data_0_7_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][119] <= _T_19991 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][119] <= _T_19991 @[ifu_bp_ctl.scala 450:39] reg _T_19992 : UInt, rvclkhdr_529.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][7][8] : @[Reg.scala 28:19] _T_19992 <= bht_bank_wr_data_0_7_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][120] <= _T_19992 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][120] <= _T_19992 @[ifu_bp_ctl.scala 450:39] reg _T_19993 : UInt, rvclkhdr_529.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][7][9] : @[Reg.scala 28:19] _T_19993 <= bht_bank_wr_data_0_7_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][121] <= _T_19993 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][121] <= _T_19993 @[ifu_bp_ctl.scala 450:39] reg _T_19994 : UInt, rvclkhdr_529.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][7][10] : @[Reg.scala 28:19] _T_19994 <= bht_bank_wr_data_0_7_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][122] <= _T_19994 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][122] <= _T_19994 @[ifu_bp_ctl.scala 450:39] reg _T_19995 : UInt, rvclkhdr_529.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][7][11] : @[Reg.scala 28:19] _T_19995 <= bht_bank_wr_data_0_7_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][123] <= _T_19995 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][123] <= _T_19995 @[ifu_bp_ctl.scala 450:39] reg _T_19996 : UInt, rvclkhdr_529.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][7][12] : @[Reg.scala 28:19] _T_19996 <= bht_bank_wr_data_0_7_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][124] <= _T_19996 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][124] <= _T_19996 @[ifu_bp_ctl.scala 450:39] reg _T_19997 : UInt, rvclkhdr_529.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][7][13] : @[Reg.scala 28:19] _T_19997 <= bht_bank_wr_data_0_7_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][125] <= _T_19997 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][125] <= _T_19997 @[ifu_bp_ctl.scala 450:39] reg _T_19998 : UInt, rvclkhdr_529.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][7][14] : @[Reg.scala 28:19] _T_19998 <= bht_bank_wr_data_0_7_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][126] <= _T_19998 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][126] <= _T_19998 @[ifu_bp_ctl.scala 450:39] reg _T_19999 : UInt, rvclkhdr_529.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][7][15] : @[Reg.scala 28:19] _T_19999 <= bht_bank_wr_data_0_7_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][127] <= _T_19999 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][127] <= _T_19999 @[ifu_bp_ctl.scala 450:39] reg _T_20000 : UInt, rvclkhdr_530.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][8][0] : @[Reg.scala 28:19] _T_20000 <= bht_bank_wr_data_0_8_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][128] <= _T_20000 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][128] <= _T_20000 @[ifu_bp_ctl.scala 450:39] reg _T_20001 : UInt, rvclkhdr_530.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][8][1] : @[Reg.scala 28:19] _T_20001 <= bht_bank_wr_data_0_8_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][129] <= _T_20001 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][129] <= _T_20001 @[ifu_bp_ctl.scala 450:39] reg _T_20002 : UInt, rvclkhdr_530.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][8][2] : @[Reg.scala 28:19] _T_20002 <= bht_bank_wr_data_0_8_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][130] <= _T_20002 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][130] <= _T_20002 @[ifu_bp_ctl.scala 450:39] reg _T_20003 : UInt, rvclkhdr_530.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][8][3] : @[Reg.scala 28:19] _T_20003 <= bht_bank_wr_data_0_8_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][131] <= _T_20003 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][131] <= _T_20003 @[ifu_bp_ctl.scala 450:39] reg _T_20004 : UInt, rvclkhdr_530.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][8][4] : @[Reg.scala 28:19] _T_20004 <= bht_bank_wr_data_0_8_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][132] <= _T_20004 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][132] <= _T_20004 @[ifu_bp_ctl.scala 450:39] reg _T_20005 : UInt, rvclkhdr_530.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][8][5] : @[Reg.scala 28:19] _T_20005 <= bht_bank_wr_data_0_8_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][133] <= _T_20005 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][133] <= _T_20005 @[ifu_bp_ctl.scala 450:39] reg _T_20006 : UInt, rvclkhdr_530.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][8][6] : @[Reg.scala 28:19] _T_20006 <= bht_bank_wr_data_0_8_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][134] <= _T_20006 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][134] <= _T_20006 @[ifu_bp_ctl.scala 450:39] reg _T_20007 : UInt, rvclkhdr_530.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][8][7] : @[Reg.scala 28:19] _T_20007 <= bht_bank_wr_data_0_8_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][135] <= _T_20007 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][135] <= _T_20007 @[ifu_bp_ctl.scala 450:39] reg _T_20008 : UInt, rvclkhdr_530.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][8][8] : @[Reg.scala 28:19] _T_20008 <= bht_bank_wr_data_0_8_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][136] <= _T_20008 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][136] <= _T_20008 @[ifu_bp_ctl.scala 450:39] reg _T_20009 : UInt, rvclkhdr_530.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][8][9] : @[Reg.scala 28:19] _T_20009 <= bht_bank_wr_data_0_8_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][137] <= _T_20009 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][137] <= _T_20009 @[ifu_bp_ctl.scala 450:39] reg _T_20010 : UInt, rvclkhdr_530.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][8][10] : @[Reg.scala 28:19] _T_20010 <= bht_bank_wr_data_0_8_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][138] <= _T_20010 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][138] <= _T_20010 @[ifu_bp_ctl.scala 450:39] reg _T_20011 : UInt, rvclkhdr_530.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][8][11] : @[Reg.scala 28:19] _T_20011 <= bht_bank_wr_data_0_8_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][139] <= _T_20011 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][139] <= _T_20011 @[ifu_bp_ctl.scala 450:39] reg _T_20012 : UInt, rvclkhdr_530.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][8][12] : @[Reg.scala 28:19] _T_20012 <= bht_bank_wr_data_0_8_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][140] <= _T_20012 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][140] <= _T_20012 @[ifu_bp_ctl.scala 450:39] reg _T_20013 : UInt, rvclkhdr_530.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][8][13] : @[Reg.scala 28:19] _T_20013 <= bht_bank_wr_data_0_8_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][141] <= _T_20013 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][141] <= _T_20013 @[ifu_bp_ctl.scala 450:39] reg _T_20014 : UInt, rvclkhdr_530.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][8][14] : @[Reg.scala 28:19] _T_20014 <= bht_bank_wr_data_0_8_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][142] <= _T_20014 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][142] <= _T_20014 @[ifu_bp_ctl.scala 450:39] reg _T_20015 : UInt, rvclkhdr_530.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][8][15] : @[Reg.scala 28:19] _T_20015 <= bht_bank_wr_data_0_8_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][143] <= _T_20015 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][143] <= _T_20015 @[ifu_bp_ctl.scala 450:39] reg _T_20016 : UInt, rvclkhdr_531.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][9][0] : @[Reg.scala 28:19] _T_20016 <= bht_bank_wr_data_0_9_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][144] <= _T_20016 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][144] <= _T_20016 @[ifu_bp_ctl.scala 450:39] reg _T_20017 : UInt, rvclkhdr_531.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][9][1] : @[Reg.scala 28:19] _T_20017 <= bht_bank_wr_data_0_9_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][145] <= _T_20017 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][145] <= _T_20017 @[ifu_bp_ctl.scala 450:39] reg _T_20018 : UInt, rvclkhdr_531.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][9][2] : @[Reg.scala 28:19] _T_20018 <= bht_bank_wr_data_0_9_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][146] <= _T_20018 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][146] <= _T_20018 @[ifu_bp_ctl.scala 450:39] reg _T_20019 : UInt, rvclkhdr_531.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][9][3] : @[Reg.scala 28:19] _T_20019 <= bht_bank_wr_data_0_9_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][147] <= _T_20019 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][147] <= _T_20019 @[ifu_bp_ctl.scala 450:39] reg _T_20020 : UInt, rvclkhdr_531.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][9][4] : @[Reg.scala 28:19] _T_20020 <= bht_bank_wr_data_0_9_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][148] <= _T_20020 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][148] <= _T_20020 @[ifu_bp_ctl.scala 450:39] reg _T_20021 : UInt, rvclkhdr_531.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][9][5] : @[Reg.scala 28:19] _T_20021 <= bht_bank_wr_data_0_9_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][149] <= _T_20021 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][149] <= _T_20021 @[ifu_bp_ctl.scala 450:39] reg _T_20022 : UInt, rvclkhdr_531.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][9][6] : @[Reg.scala 28:19] _T_20022 <= bht_bank_wr_data_0_9_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][150] <= _T_20022 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][150] <= _T_20022 @[ifu_bp_ctl.scala 450:39] reg _T_20023 : UInt, rvclkhdr_531.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][9][7] : @[Reg.scala 28:19] _T_20023 <= bht_bank_wr_data_0_9_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][151] <= _T_20023 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][151] <= _T_20023 @[ifu_bp_ctl.scala 450:39] reg _T_20024 : UInt, rvclkhdr_531.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][9][8] : @[Reg.scala 28:19] _T_20024 <= bht_bank_wr_data_0_9_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][152] <= _T_20024 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][152] <= _T_20024 @[ifu_bp_ctl.scala 450:39] reg _T_20025 : UInt, rvclkhdr_531.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][9][9] : @[Reg.scala 28:19] _T_20025 <= bht_bank_wr_data_0_9_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][153] <= _T_20025 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][153] <= _T_20025 @[ifu_bp_ctl.scala 450:39] reg _T_20026 : UInt, rvclkhdr_531.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][9][10] : @[Reg.scala 28:19] _T_20026 <= bht_bank_wr_data_0_9_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][154] <= _T_20026 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][154] <= _T_20026 @[ifu_bp_ctl.scala 450:39] reg _T_20027 : UInt, rvclkhdr_531.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][9][11] : @[Reg.scala 28:19] _T_20027 <= bht_bank_wr_data_0_9_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][155] <= _T_20027 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][155] <= _T_20027 @[ifu_bp_ctl.scala 450:39] reg _T_20028 : UInt, rvclkhdr_531.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][9][12] : @[Reg.scala 28:19] _T_20028 <= bht_bank_wr_data_0_9_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][156] <= _T_20028 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][156] <= _T_20028 @[ifu_bp_ctl.scala 450:39] reg _T_20029 : UInt, rvclkhdr_531.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][9][13] : @[Reg.scala 28:19] _T_20029 <= bht_bank_wr_data_0_9_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][157] <= _T_20029 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][157] <= _T_20029 @[ifu_bp_ctl.scala 450:39] reg _T_20030 : UInt, rvclkhdr_531.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][9][14] : @[Reg.scala 28:19] _T_20030 <= bht_bank_wr_data_0_9_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][158] <= _T_20030 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][158] <= _T_20030 @[ifu_bp_ctl.scala 450:39] reg _T_20031 : UInt, rvclkhdr_531.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][9][15] : @[Reg.scala 28:19] _T_20031 <= bht_bank_wr_data_0_9_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][159] <= _T_20031 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][159] <= _T_20031 @[ifu_bp_ctl.scala 450:39] reg _T_20032 : UInt, rvclkhdr_532.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][10][0] : @[Reg.scala 28:19] _T_20032 <= bht_bank_wr_data_0_10_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][160] <= _T_20032 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][160] <= _T_20032 @[ifu_bp_ctl.scala 450:39] reg _T_20033 : UInt, rvclkhdr_532.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][10][1] : @[Reg.scala 28:19] _T_20033 <= bht_bank_wr_data_0_10_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][161] <= _T_20033 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][161] <= _T_20033 @[ifu_bp_ctl.scala 450:39] reg _T_20034 : UInt, rvclkhdr_532.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][10][2] : @[Reg.scala 28:19] _T_20034 <= bht_bank_wr_data_0_10_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][162] <= _T_20034 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][162] <= _T_20034 @[ifu_bp_ctl.scala 450:39] reg _T_20035 : UInt, rvclkhdr_532.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][10][3] : @[Reg.scala 28:19] _T_20035 <= bht_bank_wr_data_0_10_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][163] <= _T_20035 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][163] <= _T_20035 @[ifu_bp_ctl.scala 450:39] reg _T_20036 : UInt, rvclkhdr_532.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][10][4] : @[Reg.scala 28:19] _T_20036 <= bht_bank_wr_data_0_10_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][164] <= _T_20036 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][164] <= _T_20036 @[ifu_bp_ctl.scala 450:39] reg _T_20037 : UInt, rvclkhdr_532.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][10][5] : @[Reg.scala 28:19] _T_20037 <= bht_bank_wr_data_0_10_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][165] <= _T_20037 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][165] <= _T_20037 @[ifu_bp_ctl.scala 450:39] reg _T_20038 : UInt, rvclkhdr_532.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][10][6] : @[Reg.scala 28:19] _T_20038 <= bht_bank_wr_data_0_10_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][166] <= _T_20038 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][166] <= _T_20038 @[ifu_bp_ctl.scala 450:39] reg _T_20039 : UInt, rvclkhdr_532.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][10][7] : @[Reg.scala 28:19] _T_20039 <= bht_bank_wr_data_0_10_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][167] <= _T_20039 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][167] <= _T_20039 @[ifu_bp_ctl.scala 450:39] reg _T_20040 : UInt, rvclkhdr_532.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][10][8] : @[Reg.scala 28:19] _T_20040 <= bht_bank_wr_data_0_10_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][168] <= _T_20040 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][168] <= _T_20040 @[ifu_bp_ctl.scala 450:39] reg _T_20041 : UInt, rvclkhdr_532.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][10][9] : @[Reg.scala 28:19] _T_20041 <= bht_bank_wr_data_0_10_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][169] <= _T_20041 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][169] <= _T_20041 @[ifu_bp_ctl.scala 450:39] reg _T_20042 : UInt, rvclkhdr_532.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][10][10] : @[Reg.scala 28:19] _T_20042 <= bht_bank_wr_data_0_10_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][170] <= _T_20042 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][170] <= _T_20042 @[ifu_bp_ctl.scala 450:39] reg _T_20043 : UInt, rvclkhdr_532.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][10][11] : @[Reg.scala 28:19] _T_20043 <= bht_bank_wr_data_0_10_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][171] <= _T_20043 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][171] <= _T_20043 @[ifu_bp_ctl.scala 450:39] reg _T_20044 : UInt, rvclkhdr_532.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][10][12] : @[Reg.scala 28:19] _T_20044 <= bht_bank_wr_data_0_10_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][172] <= _T_20044 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][172] <= _T_20044 @[ifu_bp_ctl.scala 450:39] reg _T_20045 : UInt, rvclkhdr_532.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][10][13] : @[Reg.scala 28:19] _T_20045 <= bht_bank_wr_data_0_10_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][173] <= _T_20045 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][173] <= _T_20045 @[ifu_bp_ctl.scala 450:39] reg _T_20046 : UInt, rvclkhdr_532.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][10][14] : @[Reg.scala 28:19] _T_20046 <= bht_bank_wr_data_0_10_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][174] <= _T_20046 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][174] <= _T_20046 @[ifu_bp_ctl.scala 450:39] reg _T_20047 : UInt, rvclkhdr_532.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][10][15] : @[Reg.scala 28:19] _T_20047 <= bht_bank_wr_data_0_10_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][175] <= _T_20047 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][175] <= _T_20047 @[ifu_bp_ctl.scala 450:39] reg _T_20048 : UInt, rvclkhdr_533.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][11][0] : @[Reg.scala 28:19] _T_20048 <= bht_bank_wr_data_0_11_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][176] <= _T_20048 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][176] <= _T_20048 @[ifu_bp_ctl.scala 450:39] reg _T_20049 : UInt, rvclkhdr_533.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][11][1] : @[Reg.scala 28:19] _T_20049 <= bht_bank_wr_data_0_11_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][177] <= _T_20049 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][177] <= _T_20049 @[ifu_bp_ctl.scala 450:39] reg _T_20050 : UInt, rvclkhdr_533.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][11][2] : @[Reg.scala 28:19] _T_20050 <= bht_bank_wr_data_0_11_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][178] <= _T_20050 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][178] <= _T_20050 @[ifu_bp_ctl.scala 450:39] reg _T_20051 : UInt, rvclkhdr_533.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][11][3] : @[Reg.scala 28:19] _T_20051 <= bht_bank_wr_data_0_11_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][179] <= _T_20051 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][179] <= _T_20051 @[ifu_bp_ctl.scala 450:39] reg _T_20052 : UInt, rvclkhdr_533.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][11][4] : @[Reg.scala 28:19] _T_20052 <= bht_bank_wr_data_0_11_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][180] <= _T_20052 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][180] <= _T_20052 @[ifu_bp_ctl.scala 450:39] reg _T_20053 : UInt, rvclkhdr_533.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][11][5] : @[Reg.scala 28:19] _T_20053 <= bht_bank_wr_data_0_11_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][181] <= _T_20053 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][181] <= _T_20053 @[ifu_bp_ctl.scala 450:39] reg _T_20054 : UInt, rvclkhdr_533.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][11][6] : @[Reg.scala 28:19] _T_20054 <= bht_bank_wr_data_0_11_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][182] <= _T_20054 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][182] <= _T_20054 @[ifu_bp_ctl.scala 450:39] reg _T_20055 : UInt, rvclkhdr_533.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][11][7] : @[Reg.scala 28:19] _T_20055 <= bht_bank_wr_data_0_11_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][183] <= _T_20055 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][183] <= _T_20055 @[ifu_bp_ctl.scala 450:39] reg _T_20056 : UInt, rvclkhdr_533.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][11][8] : @[Reg.scala 28:19] _T_20056 <= bht_bank_wr_data_0_11_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][184] <= _T_20056 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][184] <= _T_20056 @[ifu_bp_ctl.scala 450:39] reg _T_20057 : UInt, rvclkhdr_533.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][11][9] : @[Reg.scala 28:19] _T_20057 <= bht_bank_wr_data_0_11_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][185] <= _T_20057 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][185] <= _T_20057 @[ifu_bp_ctl.scala 450:39] reg _T_20058 : UInt, rvclkhdr_533.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][11][10] : @[Reg.scala 28:19] _T_20058 <= bht_bank_wr_data_0_11_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][186] <= _T_20058 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][186] <= _T_20058 @[ifu_bp_ctl.scala 450:39] reg _T_20059 : UInt, rvclkhdr_533.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][11][11] : @[Reg.scala 28:19] _T_20059 <= bht_bank_wr_data_0_11_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][187] <= _T_20059 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][187] <= _T_20059 @[ifu_bp_ctl.scala 450:39] reg _T_20060 : UInt, rvclkhdr_533.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][11][12] : @[Reg.scala 28:19] _T_20060 <= bht_bank_wr_data_0_11_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][188] <= _T_20060 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][188] <= _T_20060 @[ifu_bp_ctl.scala 450:39] reg _T_20061 : UInt, rvclkhdr_533.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][11][13] : @[Reg.scala 28:19] _T_20061 <= bht_bank_wr_data_0_11_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][189] <= _T_20061 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][189] <= _T_20061 @[ifu_bp_ctl.scala 450:39] reg _T_20062 : UInt, rvclkhdr_533.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][11][14] : @[Reg.scala 28:19] _T_20062 <= bht_bank_wr_data_0_11_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][190] <= _T_20062 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][190] <= _T_20062 @[ifu_bp_ctl.scala 450:39] reg _T_20063 : UInt, rvclkhdr_533.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][11][15] : @[Reg.scala 28:19] _T_20063 <= bht_bank_wr_data_0_11_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][191] <= _T_20063 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][191] <= _T_20063 @[ifu_bp_ctl.scala 450:39] reg _T_20064 : UInt, rvclkhdr_534.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][12][0] : @[Reg.scala 28:19] _T_20064 <= bht_bank_wr_data_0_12_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][192] <= _T_20064 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][192] <= _T_20064 @[ifu_bp_ctl.scala 450:39] reg _T_20065 : UInt, rvclkhdr_534.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][12][1] : @[Reg.scala 28:19] _T_20065 <= bht_bank_wr_data_0_12_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][193] <= _T_20065 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][193] <= _T_20065 @[ifu_bp_ctl.scala 450:39] reg _T_20066 : UInt, rvclkhdr_534.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][12][2] : @[Reg.scala 28:19] _T_20066 <= bht_bank_wr_data_0_12_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][194] <= _T_20066 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][194] <= _T_20066 @[ifu_bp_ctl.scala 450:39] reg _T_20067 : UInt, rvclkhdr_534.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][12][3] : @[Reg.scala 28:19] _T_20067 <= bht_bank_wr_data_0_12_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][195] <= _T_20067 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][195] <= _T_20067 @[ifu_bp_ctl.scala 450:39] reg _T_20068 : UInt, rvclkhdr_534.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][12][4] : @[Reg.scala 28:19] _T_20068 <= bht_bank_wr_data_0_12_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][196] <= _T_20068 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][196] <= _T_20068 @[ifu_bp_ctl.scala 450:39] reg _T_20069 : UInt, rvclkhdr_534.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][12][5] : @[Reg.scala 28:19] _T_20069 <= bht_bank_wr_data_0_12_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][197] <= _T_20069 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][197] <= _T_20069 @[ifu_bp_ctl.scala 450:39] reg _T_20070 : UInt, rvclkhdr_534.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][12][6] : @[Reg.scala 28:19] _T_20070 <= bht_bank_wr_data_0_12_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][198] <= _T_20070 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][198] <= _T_20070 @[ifu_bp_ctl.scala 450:39] reg _T_20071 : UInt, rvclkhdr_534.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][12][7] : @[Reg.scala 28:19] _T_20071 <= bht_bank_wr_data_0_12_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][199] <= _T_20071 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][199] <= _T_20071 @[ifu_bp_ctl.scala 450:39] reg _T_20072 : UInt, rvclkhdr_534.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][12][8] : @[Reg.scala 28:19] _T_20072 <= bht_bank_wr_data_0_12_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][200] <= _T_20072 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][200] <= _T_20072 @[ifu_bp_ctl.scala 450:39] reg _T_20073 : UInt, rvclkhdr_534.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][12][9] : @[Reg.scala 28:19] _T_20073 <= bht_bank_wr_data_0_12_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][201] <= _T_20073 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][201] <= _T_20073 @[ifu_bp_ctl.scala 450:39] reg _T_20074 : UInt, rvclkhdr_534.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][12][10] : @[Reg.scala 28:19] _T_20074 <= bht_bank_wr_data_0_12_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][202] <= _T_20074 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][202] <= _T_20074 @[ifu_bp_ctl.scala 450:39] reg _T_20075 : UInt, rvclkhdr_534.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][12][11] : @[Reg.scala 28:19] _T_20075 <= bht_bank_wr_data_0_12_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][203] <= _T_20075 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][203] <= _T_20075 @[ifu_bp_ctl.scala 450:39] reg _T_20076 : UInt, rvclkhdr_534.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][12][12] : @[Reg.scala 28:19] _T_20076 <= bht_bank_wr_data_0_12_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][204] <= _T_20076 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][204] <= _T_20076 @[ifu_bp_ctl.scala 450:39] reg _T_20077 : UInt, rvclkhdr_534.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][12][13] : @[Reg.scala 28:19] _T_20077 <= bht_bank_wr_data_0_12_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][205] <= _T_20077 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][205] <= _T_20077 @[ifu_bp_ctl.scala 450:39] reg _T_20078 : UInt, rvclkhdr_534.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][12][14] : @[Reg.scala 28:19] _T_20078 <= bht_bank_wr_data_0_12_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][206] <= _T_20078 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][206] <= _T_20078 @[ifu_bp_ctl.scala 450:39] reg _T_20079 : UInt, rvclkhdr_534.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][12][15] : @[Reg.scala 28:19] _T_20079 <= bht_bank_wr_data_0_12_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][207] <= _T_20079 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][207] <= _T_20079 @[ifu_bp_ctl.scala 450:39] reg _T_20080 : UInt, rvclkhdr_535.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][13][0] : @[Reg.scala 28:19] _T_20080 <= bht_bank_wr_data_0_13_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][208] <= _T_20080 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][208] <= _T_20080 @[ifu_bp_ctl.scala 450:39] reg _T_20081 : UInt, rvclkhdr_535.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][13][1] : @[Reg.scala 28:19] _T_20081 <= bht_bank_wr_data_0_13_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][209] <= _T_20081 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][209] <= _T_20081 @[ifu_bp_ctl.scala 450:39] reg _T_20082 : UInt, rvclkhdr_535.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][13][2] : @[Reg.scala 28:19] _T_20082 <= bht_bank_wr_data_0_13_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][210] <= _T_20082 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][210] <= _T_20082 @[ifu_bp_ctl.scala 450:39] reg _T_20083 : UInt, rvclkhdr_535.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][13][3] : @[Reg.scala 28:19] _T_20083 <= bht_bank_wr_data_0_13_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][211] <= _T_20083 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][211] <= _T_20083 @[ifu_bp_ctl.scala 450:39] reg _T_20084 : UInt, rvclkhdr_535.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][13][4] : @[Reg.scala 28:19] _T_20084 <= bht_bank_wr_data_0_13_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][212] <= _T_20084 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][212] <= _T_20084 @[ifu_bp_ctl.scala 450:39] reg _T_20085 : UInt, rvclkhdr_535.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][13][5] : @[Reg.scala 28:19] _T_20085 <= bht_bank_wr_data_0_13_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][213] <= _T_20085 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][213] <= _T_20085 @[ifu_bp_ctl.scala 450:39] reg _T_20086 : UInt, rvclkhdr_535.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][13][6] : @[Reg.scala 28:19] _T_20086 <= bht_bank_wr_data_0_13_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][214] <= _T_20086 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][214] <= _T_20086 @[ifu_bp_ctl.scala 450:39] reg _T_20087 : UInt, rvclkhdr_535.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][13][7] : @[Reg.scala 28:19] _T_20087 <= bht_bank_wr_data_0_13_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][215] <= _T_20087 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][215] <= _T_20087 @[ifu_bp_ctl.scala 450:39] reg _T_20088 : UInt, rvclkhdr_535.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][13][8] : @[Reg.scala 28:19] _T_20088 <= bht_bank_wr_data_0_13_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][216] <= _T_20088 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][216] <= _T_20088 @[ifu_bp_ctl.scala 450:39] reg _T_20089 : UInt, rvclkhdr_535.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][13][9] : @[Reg.scala 28:19] _T_20089 <= bht_bank_wr_data_0_13_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][217] <= _T_20089 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][217] <= _T_20089 @[ifu_bp_ctl.scala 450:39] reg _T_20090 : UInt, rvclkhdr_535.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][13][10] : @[Reg.scala 28:19] _T_20090 <= bht_bank_wr_data_0_13_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][218] <= _T_20090 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][218] <= _T_20090 @[ifu_bp_ctl.scala 450:39] reg _T_20091 : UInt, rvclkhdr_535.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][13][11] : @[Reg.scala 28:19] _T_20091 <= bht_bank_wr_data_0_13_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][219] <= _T_20091 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][219] <= _T_20091 @[ifu_bp_ctl.scala 450:39] reg _T_20092 : UInt, rvclkhdr_535.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][13][12] : @[Reg.scala 28:19] _T_20092 <= bht_bank_wr_data_0_13_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][220] <= _T_20092 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][220] <= _T_20092 @[ifu_bp_ctl.scala 450:39] reg _T_20093 : UInt, rvclkhdr_535.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][13][13] : @[Reg.scala 28:19] _T_20093 <= bht_bank_wr_data_0_13_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][221] <= _T_20093 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][221] <= _T_20093 @[ifu_bp_ctl.scala 450:39] reg _T_20094 : UInt, rvclkhdr_535.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][13][14] : @[Reg.scala 28:19] _T_20094 <= bht_bank_wr_data_0_13_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][222] <= _T_20094 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][222] <= _T_20094 @[ifu_bp_ctl.scala 450:39] reg _T_20095 : UInt, rvclkhdr_535.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][13][15] : @[Reg.scala 28:19] _T_20095 <= bht_bank_wr_data_0_13_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][223] <= _T_20095 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][223] <= _T_20095 @[ifu_bp_ctl.scala 450:39] reg _T_20096 : UInt, rvclkhdr_536.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][14][0] : @[Reg.scala 28:19] _T_20096 <= bht_bank_wr_data_0_14_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][224] <= _T_20096 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][224] <= _T_20096 @[ifu_bp_ctl.scala 450:39] reg _T_20097 : UInt, rvclkhdr_536.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][14][1] : @[Reg.scala 28:19] _T_20097 <= bht_bank_wr_data_0_14_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][225] <= _T_20097 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][225] <= _T_20097 @[ifu_bp_ctl.scala 450:39] reg _T_20098 : UInt, rvclkhdr_536.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][14][2] : @[Reg.scala 28:19] _T_20098 <= bht_bank_wr_data_0_14_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][226] <= _T_20098 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][226] <= _T_20098 @[ifu_bp_ctl.scala 450:39] reg _T_20099 : UInt, rvclkhdr_536.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][14][3] : @[Reg.scala 28:19] _T_20099 <= bht_bank_wr_data_0_14_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][227] <= _T_20099 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][227] <= _T_20099 @[ifu_bp_ctl.scala 450:39] reg _T_20100 : UInt, rvclkhdr_536.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][14][4] : @[Reg.scala 28:19] _T_20100 <= bht_bank_wr_data_0_14_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][228] <= _T_20100 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][228] <= _T_20100 @[ifu_bp_ctl.scala 450:39] reg _T_20101 : UInt, rvclkhdr_536.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][14][5] : @[Reg.scala 28:19] _T_20101 <= bht_bank_wr_data_0_14_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][229] <= _T_20101 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][229] <= _T_20101 @[ifu_bp_ctl.scala 450:39] reg _T_20102 : UInt, rvclkhdr_536.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][14][6] : @[Reg.scala 28:19] _T_20102 <= bht_bank_wr_data_0_14_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][230] <= _T_20102 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][230] <= _T_20102 @[ifu_bp_ctl.scala 450:39] reg _T_20103 : UInt, rvclkhdr_536.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][14][7] : @[Reg.scala 28:19] _T_20103 <= bht_bank_wr_data_0_14_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][231] <= _T_20103 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][231] <= _T_20103 @[ifu_bp_ctl.scala 450:39] reg _T_20104 : UInt, rvclkhdr_536.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][14][8] : @[Reg.scala 28:19] _T_20104 <= bht_bank_wr_data_0_14_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][232] <= _T_20104 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][232] <= _T_20104 @[ifu_bp_ctl.scala 450:39] reg _T_20105 : UInt, rvclkhdr_536.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][14][9] : @[Reg.scala 28:19] _T_20105 <= bht_bank_wr_data_0_14_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][233] <= _T_20105 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][233] <= _T_20105 @[ifu_bp_ctl.scala 450:39] reg _T_20106 : UInt, rvclkhdr_536.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][14][10] : @[Reg.scala 28:19] _T_20106 <= bht_bank_wr_data_0_14_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][234] <= _T_20106 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][234] <= _T_20106 @[ifu_bp_ctl.scala 450:39] reg _T_20107 : UInt, rvclkhdr_536.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][14][11] : @[Reg.scala 28:19] _T_20107 <= bht_bank_wr_data_0_14_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][235] <= _T_20107 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][235] <= _T_20107 @[ifu_bp_ctl.scala 450:39] reg _T_20108 : UInt, rvclkhdr_536.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][14][12] : @[Reg.scala 28:19] _T_20108 <= bht_bank_wr_data_0_14_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][236] <= _T_20108 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][236] <= _T_20108 @[ifu_bp_ctl.scala 450:39] reg _T_20109 : UInt, rvclkhdr_536.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][14][13] : @[Reg.scala 28:19] _T_20109 <= bht_bank_wr_data_0_14_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][237] <= _T_20109 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][237] <= _T_20109 @[ifu_bp_ctl.scala 450:39] reg _T_20110 : UInt, rvclkhdr_536.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][14][14] : @[Reg.scala 28:19] _T_20110 <= bht_bank_wr_data_0_14_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][238] <= _T_20110 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][238] <= _T_20110 @[ifu_bp_ctl.scala 450:39] reg _T_20111 : UInt, rvclkhdr_536.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][14][15] : @[Reg.scala 28:19] _T_20111 <= bht_bank_wr_data_0_14_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][239] <= _T_20111 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][239] <= _T_20111 @[ifu_bp_ctl.scala 450:39] reg _T_20112 : UInt, rvclkhdr_537.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][15][0] : @[Reg.scala 28:19] _T_20112 <= bht_bank_wr_data_0_15_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][240] <= _T_20112 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][240] <= _T_20112 @[ifu_bp_ctl.scala 450:39] reg _T_20113 : UInt, rvclkhdr_537.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][15][1] : @[Reg.scala 28:19] _T_20113 <= bht_bank_wr_data_0_15_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][241] <= _T_20113 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][241] <= _T_20113 @[ifu_bp_ctl.scala 450:39] reg _T_20114 : UInt, rvclkhdr_537.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][15][2] : @[Reg.scala 28:19] _T_20114 <= bht_bank_wr_data_0_15_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][242] <= _T_20114 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][242] <= _T_20114 @[ifu_bp_ctl.scala 450:39] reg _T_20115 : UInt, rvclkhdr_537.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][15][3] : @[Reg.scala 28:19] _T_20115 <= bht_bank_wr_data_0_15_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][243] <= _T_20115 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][243] <= _T_20115 @[ifu_bp_ctl.scala 450:39] reg _T_20116 : UInt, rvclkhdr_537.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][15][4] : @[Reg.scala 28:19] _T_20116 <= bht_bank_wr_data_0_15_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][244] <= _T_20116 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][244] <= _T_20116 @[ifu_bp_ctl.scala 450:39] reg _T_20117 : UInt, rvclkhdr_537.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][15][5] : @[Reg.scala 28:19] _T_20117 <= bht_bank_wr_data_0_15_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][245] <= _T_20117 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][245] <= _T_20117 @[ifu_bp_ctl.scala 450:39] reg _T_20118 : UInt, rvclkhdr_537.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][15][6] : @[Reg.scala 28:19] _T_20118 <= bht_bank_wr_data_0_15_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][246] <= _T_20118 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][246] <= _T_20118 @[ifu_bp_ctl.scala 450:39] reg _T_20119 : UInt, rvclkhdr_537.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][15][7] : @[Reg.scala 28:19] _T_20119 <= bht_bank_wr_data_0_15_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][247] <= _T_20119 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][247] <= _T_20119 @[ifu_bp_ctl.scala 450:39] reg _T_20120 : UInt, rvclkhdr_537.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][15][8] : @[Reg.scala 28:19] _T_20120 <= bht_bank_wr_data_0_15_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][248] <= _T_20120 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][248] <= _T_20120 @[ifu_bp_ctl.scala 450:39] reg _T_20121 : UInt, rvclkhdr_537.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][15][9] : @[Reg.scala 28:19] _T_20121 <= bht_bank_wr_data_0_15_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][249] <= _T_20121 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][249] <= _T_20121 @[ifu_bp_ctl.scala 450:39] reg _T_20122 : UInt, rvclkhdr_537.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][15][10] : @[Reg.scala 28:19] _T_20122 <= bht_bank_wr_data_0_15_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][250] <= _T_20122 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][250] <= _T_20122 @[ifu_bp_ctl.scala 450:39] reg _T_20123 : UInt, rvclkhdr_537.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][15][11] : @[Reg.scala 28:19] _T_20123 <= bht_bank_wr_data_0_15_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][251] <= _T_20123 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][251] <= _T_20123 @[ifu_bp_ctl.scala 450:39] reg _T_20124 : UInt, rvclkhdr_537.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][15][12] : @[Reg.scala 28:19] _T_20124 <= bht_bank_wr_data_0_15_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][252] <= _T_20124 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][252] <= _T_20124 @[ifu_bp_ctl.scala 450:39] reg _T_20125 : UInt, rvclkhdr_537.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][15][13] : @[Reg.scala 28:19] _T_20125 <= bht_bank_wr_data_0_15_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][253] <= _T_20125 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][253] <= _T_20125 @[ifu_bp_ctl.scala 450:39] reg _T_20126 : UInt, rvclkhdr_537.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][15][14] : @[Reg.scala 28:19] _T_20126 <= bht_bank_wr_data_0_15_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][254] <= _T_20126 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][254] <= _T_20126 @[ifu_bp_ctl.scala 450:39] reg _T_20127 : UInt, rvclkhdr_537.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[0][15][15] : @[Reg.scala 28:19] _T_20127 <= bht_bank_wr_data_0_15_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[0][255] <= _T_20127 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[0][255] <= _T_20127 @[ifu_bp_ctl.scala 450:39] reg _T_20128 : UInt, rvclkhdr_538.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][0][0] : @[Reg.scala 28:19] _T_20128 <= bht_bank_wr_data_1_0_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][0] <= _T_20128 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][0] <= _T_20128 @[ifu_bp_ctl.scala 450:39] reg _T_20129 : UInt, rvclkhdr_538.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][0][1] : @[Reg.scala 28:19] _T_20129 <= bht_bank_wr_data_1_0_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][1] <= _T_20129 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][1] <= _T_20129 @[ifu_bp_ctl.scala 450:39] reg _T_20130 : UInt, rvclkhdr_538.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][0][2] : @[Reg.scala 28:19] _T_20130 <= bht_bank_wr_data_1_0_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][2] <= _T_20130 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][2] <= _T_20130 @[ifu_bp_ctl.scala 450:39] reg _T_20131 : UInt, rvclkhdr_538.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][0][3] : @[Reg.scala 28:19] _T_20131 <= bht_bank_wr_data_1_0_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][3] <= _T_20131 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][3] <= _T_20131 @[ifu_bp_ctl.scala 450:39] reg _T_20132 : UInt, rvclkhdr_538.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][0][4] : @[Reg.scala 28:19] _T_20132 <= bht_bank_wr_data_1_0_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][4] <= _T_20132 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][4] <= _T_20132 @[ifu_bp_ctl.scala 450:39] reg _T_20133 : UInt, rvclkhdr_538.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][0][5] : @[Reg.scala 28:19] _T_20133 <= bht_bank_wr_data_1_0_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][5] <= _T_20133 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][5] <= _T_20133 @[ifu_bp_ctl.scala 450:39] reg _T_20134 : UInt, rvclkhdr_538.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][0][6] : @[Reg.scala 28:19] _T_20134 <= bht_bank_wr_data_1_0_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][6] <= _T_20134 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][6] <= _T_20134 @[ifu_bp_ctl.scala 450:39] reg _T_20135 : UInt, rvclkhdr_538.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][0][7] : @[Reg.scala 28:19] _T_20135 <= bht_bank_wr_data_1_0_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][7] <= _T_20135 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][7] <= _T_20135 @[ifu_bp_ctl.scala 450:39] reg _T_20136 : UInt, rvclkhdr_538.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][0][8] : @[Reg.scala 28:19] _T_20136 <= bht_bank_wr_data_1_0_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][8] <= _T_20136 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][8] <= _T_20136 @[ifu_bp_ctl.scala 450:39] reg _T_20137 : UInt, rvclkhdr_538.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][0][9] : @[Reg.scala 28:19] _T_20137 <= bht_bank_wr_data_1_0_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][9] <= _T_20137 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][9] <= _T_20137 @[ifu_bp_ctl.scala 450:39] reg _T_20138 : UInt, rvclkhdr_538.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][0][10] : @[Reg.scala 28:19] _T_20138 <= bht_bank_wr_data_1_0_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][10] <= _T_20138 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][10] <= _T_20138 @[ifu_bp_ctl.scala 450:39] reg _T_20139 : UInt, rvclkhdr_538.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][0][11] : @[Reg.scala 28:19] _T_20139 <= bht_bank_wr_data_1_0_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][11] <= _T_20139 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][11] <= _T_20139 @[ifu_bp_ctl.scala 450:39] reg _T_20140 : UInt, rvclkhdr_538.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][0][12] : @[Reg.scala 28:19] _T_20140 <= bht_bank_wr_data_1_0_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][12] <= _T_20140 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][12] <= _T_20140 @[ifu_bp_ctl.scala 450:39] reg _T_20141 : UInt, rvclkhdr_538.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][0][13] : @[Reg.scala 28:19] _T_20141 <= bht_bank_wr_data_1_0_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][13] <= _T_20141 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][13] <= _T_20141 @[ifu_bp_ctl.scala 450:39] reg _T_20142 : UInt, rvclkhdr_538.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][0][14] : @[Reg.scala 28:19] _T_20142 <= bht_bank_wr_data_1_0_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][14] <= _T_20142 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][14] <= _T_20142 @[ifu_bp_ctl.scala 450:39] reg _T_20143 : UInt, rvclkhdr_538.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][0][15] : @[Reg.scala 28:19] _T_20143 <= bht_bank_wr_data_1_0_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][15] <= _T_20143 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][15] <= _T_20143 @[ifu_bp_ctl.scala 450:39] reg _T_20144 : UInt, rvclkhdr_539.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][1][0] : @[Reg.scala 28:19] _T_20144 <= bht_bank_wr_data_1_1_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][16] <= _T_20144 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][16] <= _T_20144 @[ifu_bp_ctl.scala 450:39] reg _T_20145 : UInt, rvclkhdr_539.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][1][1] : @[Reg.scala 28:19] _T_20145 <= bht_bank_wr_data_1_1_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][17] <= _T_20145 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][17] <= _T_20145 @[ifu_bp_ctl.scala 450:39] reg _T_20146 : UInt, rvclkhdr_539.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][1][2] : @[Reg.scala 28:19] _T_20146 <= bht_bank_wr_data_1_1_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][18] <= _T_20146 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][18] <= _T_20146 @[ifu_bp_ctl.scala 450:39] reg _T_20147 : UInt, rvclkhdr_539.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][1][3] : @[Reg.scala 28:19] _T_20147 <= bht_bank_wr_data_1_1_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][19] <= _T_20147 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][19] <= _T_20147 @[ifu_bp_ctl.scala 450:39] reg _T_20148 : UInt, rvclkhdr_539.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][1][4] : @[Reg.scala 28:19] _T_20148 <= bht_bank_wr_data_1_1_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][20] <= _T_20148 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][20] <= _T_20148 @[ifu_bp_ctl.scala 450:39] reg _T_20149 : UInt, rvclkhdr_539.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][1][5] : @[Reg.scala 28:19] _T_20149 <= bht_bank_wr_data_1_1_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][21] <= _T_20149 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][21] <= _T_20149 @[ifu_bp_ctl.scala 450:39] reg _T_20150 : UInt, rvclkhdr_539.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][1][6] : @[Reg.scala 28:19] _T_20150 <= bht_bank_wr_data_1_1_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][22] <= _T_20150 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][22] <= _T_20150 @[ifu_bp_ctl.scala 450:39] reg _T_20151 : UInt, rvclkhdr_539.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][1][7] : @[Reg.scala 28:19] _T_20151 <= bht_bank_wr_data_1_1_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][23] <= _T_20151 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][23] <= _T_20151 @[ifu_bp_ctl.scala 450:39] reg _T_20152 : UInt, rvclkhdr_539.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][1][8] : @[Reg.scala 28:19] _T_20152 <= bht_bank_wr_data_1_1_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][24] <= _T_20152 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][24] <= _T_20152 @[ifu_bp_ctl.scala 450:39] reg _T_20153 : UInt, rvclkhdr_539.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][1][9] : @[Reg.scala 28:19] _T_20153 <= bht_bank_wr_data_1_1_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][25] <= _T_20153 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][25] <= _T_20153 @[ifu_bp_ctl.scala 450:39] reg _T_20154 : UInt, rvclkhdr_539.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][1][10] : @[Reg.scala 28:19] _T_20154 <= bht_bank_wr_data_1_1_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][26] <= _T_20154 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][26] <= _T_20154 @[ifu_bp_ctl.scala 450:39] reg _T_20155 : UInt, rvclkhdr_539.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][1][11] : @[Reg.scala 28:19] _T_20155 <= bht_bank_wr_data_1_1_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][27] <= _T_20155 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][27] <= _T_20155 @[ifu_bp_ctl.scala 450:39] reg _T_20156 : UInt, rvclkhdr_539.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][1][12] : @[Reg.scala 28:19] _T_20156 <= bht_bank_wr_data_1_1_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][28] <= _T_20156 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][28] <= _T_20156 @[ifu_bp_ctl.scala 450:39] reg _T_20157 : UInt, rvclkhdr_539.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][1][13] : @[Reg.scala 28:19] _T_20157 <= bht_bank_wr_data_1_1_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][29] <= _T_20157 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][29] <= _T_20157 @[ifu_bp_ctl.scala 450:39] reg _T_20158 : UInt, rvclkhdr_539.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][1][14] : @[Reg.scala 28:19] _T_20158 <= bht_bank_wr_data_1_1_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][30] <= _T_20158 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][30] <= _T_20158 @[ifu_bp_ctl.scala 450:39] reg _T_20159 : UInt, rvclkhdr_539.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][1][15] : @[Reg.scala 28:19] _T_20159 <= bht_bank_wr_data_1_1_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][31] <= _T_20159 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][31] <= _T_20159 @[ifu_bp_ctl.scala 450:39] reg _T_20160 : UInt, rvclkhdr_540.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][2][0] : @[Reg.scala 28:19] _T_20160 <= bht_bank_wr_data_1_2_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][32] <= _T_20160 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][32] <= _T_20160 @[ifu_bp_ctl.scala 450:39] reg _T_20161 : UInt, rvclkhdr_540.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][2][1] : @[Reg.scala 28:19] _T_20161 <= bht_bank_wr_data_1_2_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][33] <= _T_20161 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][33] <= _T_20161 @[ifu_bp_ctl.scala 450:39] reg _T_20162 : UInt, rvclkhdr_540.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][2][2] : @[Reg.scala 28:19] _T_20162 <= bht_bank_wr_data_1_2_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][34] <= _T_20162 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][34] <= _T_20162 @[ifu_bp_ctl.scala 450:39] reg _T_20163 : UInt, rvclkhdr_540.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][2][3] : @[Reg.scala 28:19] _T_20163 <= bht_bank_wr_data_1_2_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][35] <= _T_20163 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][35] <= _T_20163 @[ifu_bp_ctl.scala 450:39] reg _T_20164 : UInt, rvclkhdr_540.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][2][4] : @[Reg.scala 28:19] _T_20164 <= bht_bank_wr_data_1_2_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][36] <= _T_20164 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][36] <= _T_20164 @[ifu_bp_ctl.scala 450:39] reg _T_20165 : UInt, rvclkhdr_540.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][2][5] : @[Reg.scala 28:19] _T_20165 <= bht_bank_wr_data_1_2_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][37] <= _T_20165 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][37] <= _T_20165 @[ifu_bp_ctl.scala 450:39] reg _T_20166 : UInt, rvclkhdr_540.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][2][6] : @[Reg.scala 28:19] _T_20166 <= bht_bank_wr_data_1_2_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][38] <= _T_20166 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][38] <= _T_20166 @[ifu_bp_ctl.scala 450:39] reg _T_20167 : UInt, rvclkhdr_540.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][2][7] : @[Reg.scala 28:19] _T_20167 <= bht_bank_wr_data_1_2_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][39] <= _T_20167 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][39] <= _T_20167 @[ifu_bp_ctl.scala 450:39] reg _T_20168 : UInt, rvclkhdr_540.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][2][8] : @[Reg.scala 28:19] _T_20168 <= bht_bank_wr_data_1_2_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][40] <= _T_20168 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][40] <= _T_20168 @[ifu_bp_ctl.scala 450:39] reg _T_20169 : UInt, rvclkhdr_540.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][2][9] : @[Reg.scala 28:19] _T_20169 <= bht_bank_wr_data_1_2_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][41] <= _T_20169 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][41] <= _T_20169 @[ifu_bp_ctl.scala 450:39] reg _T_20170 : UInt, rvclkhdr_540.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][2][10] : @[Reg.scala 28:19] _T_20170 <= bht_bank_wr_data_1_2_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][42] <= _T_20170 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][42] <= _T_20170 @[ifu_bp_ctl.scala 450:39] reg _T_20171 : UInt, rvclkhdr_540.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][2][11] : @[Reg.scala 28:19] _T_20171 <= bht_bank_wr_data_1_2_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][43] <= _T_20171 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][43] <= _T_20171 @[ifu_bp_ctl.scala 450:39] reg _T_20172 : UInt, rvclkhdr_540.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][2][12] : @[Reg.scala 28:19] _T_20172 <= bht_bank_wr_data_1_2_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][44] <= _T_20172 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][44] <= _T_20172 @[ifu_bp_ctl.scala 450:39] reg _T_20173 : UInt, rvclkhdr_540.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][2][13] : @[Reg.scala 28:19] _T_20173 <= bht_bank_wr_data_1_2_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][45] <= _T_20173 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][45] <= _T_20173 @[ifu_bp_ctl.scala 450:39] reg _T_20174 : UInt, rvclkhdr_540.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][2][14] : @[Reg.scala 28:19] _T_20174 <= bht_bank_wr_data_1_2_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][46] <= _T_20174 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][46] <= _T_20174 @[ifu_bp_ctl.scala 450:39] reg _T_20175 : UInt, rvclkhdr_540.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][2][15] : @[Reg.scala 28:19] _T_20175 <= bht_bank_wr_data_1_2_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][47] <= _T_20175 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][47] <= _T_20175 @[ifu_bp_ctl.scala 450:39] reg _T_20176 : UInt, rvclkhdr_541.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][3][0] : @[Reg.scala 28:19] _T_20176 <= bht_bank_wr_data_1_3_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][48] <= _T_20176 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][48] <= _T_20176 @[ifu_bp_ctl.scala 450:39] reg _T_20177 : UInt, rvclkhdr_541.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][3][1] : @[Reg.scala 28:19] _T_20177 <= bht_bank_wr_data_1_3_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][49] <= _T_20177 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][49] <= _T_20177 @[ifu_bp_ctl.scala 450:39] reg _T_20178 : UInt, rvclkhdr_541.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][3][2] : @[Reg.scala 28:19] _T_20178 <= bht_bank_wr_data_1_3_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][50] <= _T_20178 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][50] <= _T_20178 @[ifu_bp_ctl.scala 450:39] reg _T_20179 : UInt, rvclkhdr_541.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][3][3] : @[Reg.scala 28:19] _T_20179 <= bht_bank_wr_data_1_3_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][51] <= _T_20179 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][51] <= _T_20179 @[ifu_bp_ctl.scala 450:39] reg _T_20180 : UInt, rvclkhdr_541.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][3][4] : @[Reg.scala 28:19] _T_20180 <= bht_bank_wr_data_1_3_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][52] <= _T_20180 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][52] <= _T_20180 @[ifu_bp_ctl.scala 450:39] reg _T_20181 : UInt, rvclkhdr_541.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][3][5] : @[Reg.scala 28:19] _T_20181 <= bht_bank_wr_data_1_3_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][53] <= _T_20181 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][53] <= _T_20181 @[ifu_bp_ctl.scala 450:39] reg _T_20182 : UInt, rvclkhdr_541.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][3][6] : @[Reg.scala 28:19] _T_20182 <= bht_bank_wr_data_1_3_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][54] <= _T_20182 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][54] <= _T_20182 @[ifu_bp_ctl.scala 450:39] reg _T_20183 : UInt, rvclkhdr_541.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][3][7] : @[Reg.scala 28:19] _T_20183 <= bht_bank_wr_data_1_3_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][55] <= _T_20183 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][55] <= _T_20183 @[ifu_bp_ctl.scala 450:39] reg _T_20184 : UInt, rvclkhdr_541.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][3][8] : @[Reg.scala 28:19] _T_20184 <= bht_bank_wr_data_1_3_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][56] <= _T_20184 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][56] <= _T_20184 @[ifu_bp_ctl.scala 450:39] reg _T_20185 : UInt, rvclkhdr_541.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][3][9] : @[Reg.scala 28:19] _T_20185 <= bht_bank_wr_data_1_3_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][57] <= _T_20185 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][57] <= _T_20185 @[ifu_bp_ctl.scala 450:39] reg _T_20186 : UInt, rvclkhdr_541.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][3][10] : @[Reg.scala 28:19] _T_20186 <= bht_bank_wr_data_1_3_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][58] <= _T_20186 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][58] <= _T_20186 @[ifu_bp_ctl.scala 450:39] reg _T_20187 : UInt, rvclkhdr_541.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][3][11] : @[Reg.scala 28:19] _T_20187 <= bht_bank_wr_data_1_3_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][59] <= _T_20187 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][59] <= _T_20187 @[ifu_bp_ctl.scala 450:39] reg _T_20188 : UInt, rvclkhdr_541.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][3][12] : @[Reg.scala 28:19] _T_20188 <= bht_bank_wr_data_1_3_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][60] <= _T_20188 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][60] <= _T_20188 @[ifu_bp_ctl.scala 450:39] reg _T_20189 : UInt, rvclkhdr_541.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][3][13] : @[Reg.scala 28:19] _T_20189 <= bht_bank_wr_data_1_3_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][61] <= _T_20189 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][61] <= _T_20189 @[ifu_bp_ctl.scala 450:39] reg _T_20190 : UInt, rvclkhdr_541.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][3][14] : @[Reg.scala 28:19] _T_20190 <= bht_bank_wr_data_1_3_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][62] <= _T_20190 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][62] <= _T_20190 @[ifu_bp_ctl.scala 450:39] reg _T_20191 : UInt, rvclkhdr_541.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][3][15] : @[Reg.scala 28:19] _T_20191 <= bht_bank_wr_data_1_3_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][63] <= _T_20191 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][63] <= _T_20191 @[ifu_bp_ctl.scala 450:39] reg _T_20192 : UInt, rvclkhdr_542.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][4][0] : @[Reg.scala 28:19] _T_20192 <= bht_bank_wr_data_1_4_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][64] <= _T_20192 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][64] <= _T_20192 @[ifu_bp_ctl.scala 450:39] reg _T_20193 : UInt, rvclkhdr_542.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][4][1] : @[Reg.scala 28:19] _T_20193 <= bht_bank_wr_data_1_4_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][65] <= _T_20193 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][65] <= _T_20193 @[ifu_bp_ctl.scala 450:39] reg _T_20194 : UInt, rvclkhdr_542.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][4][2] : @[Reg.scala 28:19] _T_20194 <= bht_bank_wr_data_1_4_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][66] <= _T_20194 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][66] <= _T_20194 @[ifu_bp_ctl.scala 450:39] reg _T_20195 : UInt, rvclkhdr_542.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][4][3] : @[Reg.scala 28:19] _T_20195 <= bht_bank_wr_data_1_4_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][67] <= _T_20195 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][67] <= _T_20195 @[ifu_bp_ctl.scala 450:39] reg _T_20196 : UInt, rvclkhdr_542.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][4][4] : @[Reg.scala 28:19] _T_20196 <= bht_bank_wr_data_1_4_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][68] <= _T_20196 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][68] <= _T_20196 @[ifu_bp_ctl.scala 450:39] reg _T_20197 : UInt, rvclkhdr_542.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][4][5] : @[Reg.scala 28:19] _T_20197 <= bht_bank_wr_data_1_4_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][69] <= _T_20197 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][69] <= _T_20197 @[ifu_bp_ctl.scala 450:39] reg _T_20198 : UInt, rvclkhdr_542.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][4][6] : @[Reg.scala 28:19] _T_20198 <= bht_bank_wr_data_1_4_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][70] <= _T_20198 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][70] <= _T_20198 @[ifu_bp_ctl.scala 450:39] reg _T_20199 : UInt, rvclkhdr_542.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][4][7] : @[Reg.scala 28:19] _T_20199 <= bht_bank_wr_data_1_4_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][71] <= _T_20199 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][71] <= _T_20199 @[ifu_bp_ctl.scala 450:39] reg _T_20200 : UInt, rvclkhdr_542.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][4][8] : @[Reg.scala 28:19] _T_20200 <= bht_bank_wr_data_1_4_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][72] <= _T_20200 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][72] <= _T_20200 @[ifu_bp_ctl.scala 450:39] reg _T_20201 : UInt, rvclkhdr_542.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][4][9] : @[Reg.scala 28:19] _T_20201 <= bht_bank_wr_data_1_4_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][73] <= _T_20201 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][73] <= _T_20201 @[ifu_bp_ctl.scala 450:39] reg _T_20202 : UInt, rvclkhdr_542.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][4][10] : @[Reg.scala 28:19] _T_20202 <= bht_bank_wr_data_1_4_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][74] <= _T_20202 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][74] <= _T_20202 @[ifu_bp_ctl.scala 450:39] reg _T_20203 : UInt, rvclkhdr_542.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][4][11] : @[Reg.scala 28:19] _T_20203 <= bht_bank_wr_data_1_4_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][75] <= _T_20203 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][75] <= _T_20203 @[ifu_bp_ctl.scala 450:39] reg _T_20204 : UInt, rvclkhdr_542.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][4][12] : @[Reg.scala 28:19] _T_20204 <= bht_bank_wr_data_1_4_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][76] <= _T_20204 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][76] <= _T_20204 @[ifu_bp_ctl.scala 450:39] reg _T_20205 : UInt, rvclkhdr_542.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][4][13] : @[Reg.scala 28:19] _T_20205 <= bht_bank_wr_data_1_4_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][77] <= _T_20205 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][77] <= _T_20205 @[ifu_bp_ctl.scala 450:39] reg _T_20206 : UInt, rvclkhdr_542.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][4][14] : @[Reg.scala 28:19] _T_20206 <= bht_bank_wr_data_1_4_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][78] <= _T_20206 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][78] <= _T_20206 @[ifu_bp_ctl.scala 450:39] reg _T_20207 : UInt, rvclkhdr_542.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][4][15] : @[Reg.scala 28:19] _T_20207 <= bht_bank_wr_data_1_4_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][79] <= _T_20207 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][79] <= _T_20207 @[ifu_bp_ctl.scala 450:39] reg _T_20208 : UInt, rvclkhdr_543.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][5][0] : @[Reg.scala 28:19] _T_20208 <= bht_bank_wr_data_1_5_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][80] <= _T_20208 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][80] <= _T_20208 @[ifu_bp_ctl.scala 450:39] reg _T_20209 : UInt, rvclkhdr_543.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][5][1] : @[Reg.scala 28:19] _T_20209 <= bht_bank_wr_data_1_5_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][81] <= _T_20209 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][81] <= _T_20209 @[ifu_bp_ctl.scala 450:39] reg _T_20210 : UInt, rvclkhdr_543.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][5][2] : @[Reg.scala 28:19] _T_20210 <= bht_bank_wr_data_1_5_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][82] <= _T_20210 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][82] <= _T_20210 @[ifu_bp_ctl.scala 450:39] reg _T_20211 : UInt, rvclkhdr_543.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][5][3] : @[Reg.scala 28:19] _T_20211 <= bht_bank_wr_data_1_5_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][83] <= _T_20211 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][83] <= _T_20211 @[ifu_bp_ctl.scala 450:39] reg _T_20212 : UInt, rvclkhdr_543.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][5][4] : @[Reg.scala 28:19] _T_20212 <= bht_bank_wr_data_1_5_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][84] <= _T_20212 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][84] <= _T_20212 @[ifu_bp_ctl.scala 450:39] reg _T_20213 : UInt, rvclkhdr_543.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][5][5] : @[Reg.scala 28:19] _T_20213 <= bht_bank_wr_data_1_5_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][85] <= _T_20213 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][85] <= _T_20213 @[ifu_bp_ctl.scala 450:39] reg _T_20214 : UInt, rvclkhdr_543.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][5][6] : @[Reg.scala 28:19] _T_20214 <= bht_bank_wr_data_1_5_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][86] <= _T_20214 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][86] <= _T_20214 @[ifu_bp_ctl.scala 450:39] reg _T_20215 : UInt, rvclkhdr_543.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][5][7] : @[Reg.scala 28:19] _T_20215 <= bht_bank_wr_data_1_5_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][87] <= _T_20215 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][87] <= _T_20215 @[ifu_bp_ctl.scala 450:39] reg _T_20216 : UInt, rvclkhdr_543.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][5][8] : @[Reg.scala 28:19] _T_20216 <= bht_bank_wr_data_1_5_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][88] <= _T_20216 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][88] <= _T_20216 @[ifu_bp_ctl.scala 450:39] reg _T_20217 : UInt, rvclkhdr_543.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][5][9] : @[Reg.scala 28:19] _T_20217 <= bht_bank_wr_data_1_5_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][89] <= _T_20217 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][89] <= _T_20217 @[ifu_bp_ctl.scala 450:39] reg _T_20218 : UInt, rvclkhdr_543.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][5][10] : @[Reg.scala 28:19] _T_20218 <= bht_bank_wr_data_1_5_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][90] <= _T_20218 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][90] <= _T_20218 @[ifu_bp_ctl.scala 450:39] reg _T_20219 : UInt, rvclkhdr_543.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][5][11] : @[Reg.scala 28:19] _T_20219 <= bht_bank_wr_data_1_5_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][91] <= _T_20219 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][91] <= _T_20219 @[ifu_bp_ctl.scala 450:39] reg _T_20220 : UInt, rvclkhdr_543.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][5][12] : @[Reg.scala 28:19] _T_20220 <= bht_bank_wr_data_1_5_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][92] <= _T_20220 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][92] <= _T_20220 @[ifu_bp_ctl.scala 450:39] reg _T_20221 : UInt, rvclkhdr_543.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][5][13] : @[Reg.scala 28:19] _T_20221 <= bht_bank_wr_data_1_5_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][93] <= _T_20221 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][93] <= _T_20221 @[ifu_bp_ctl.scala 450:39] reg _T_20222 : UInt, rvclkhdr_543.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][5][14] : @[Reg.scala 28:19] _T_20222 <= bht_bank_wr_data_1_5_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][94] <= _T_20222 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][94] <= _T_20222 @[ifu_bp_ctl.scala 450:39] reg _T_20223 : UInt, rvclkhdr_543.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][5][15] : @[Reg.scala 28:19] _T_20223 <= bht_bank_wr_data_1_5_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][95] <= _T_20223 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][95] <= _T_20223 @[ifu_bp_ctl.scala 450:39] reg _T_20224 : UInt, rvclkhdr_544.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][6][0] : @[Reg.scala 28:19] _T_20224 <= bht_bank_wr_data_1_6_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][96] <= _T_20224 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][96] <= _T_20224 @[ifu_bp_ctl.scala 450:39] reg _T_20225 : UInt, rvclkhdr_544.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][6][1] : @[Reg.scala 28:19] _T_20225 <= bht_bank_wr_data_1_6_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][97] <= _T_20225 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][97] <= _T_20225 @[ifu_bp_ctl.scala 450:39] reg _T_20226 : UInt, rvclkhdr_544.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][6][2] : @[Reg.scala 28:19] _T_20226 <= bht_bank_wr_data_1_6_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][98] <= _T_20226 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][98] <= _T_20226 @[ifu_bp_ctl.scala 450:39] reg _T_20227 : UInt, rvclkhdr_544.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][6][3] : @[Reg.scala 28:19] _T_20227 <= bht_bank_wr_data_1_6_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][99] <= _T_20227 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][99] <= _T_20227 @[ifu_bp_ctl.scala 450:39] reg _T_20228 : UInt, rvclkhdr_544.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][6][4] : @[Reg.scala 28:19] _T_20228 <= bht_bank_wr_data_1_6_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][100] <= _T_20228 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][100] <= _T_20228 @[ifu_bp_ctl.scala 450:39] reg _T_20229 : UInt, rvclkhdr_544.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][6][5] : @[Reg.scala 28:19] _T_20229 <= bht_bank_wr_data_1_6_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][101] <= _T_20229 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][101] <= _T_20229 @[ifu_bp_ctl.scala 450:39] reg _T_20230 : UInt, rvclkhdr_544.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][6][6] : @[Reg.scala 28:19] _T_20230 <= bht_bank_wr_data_1_6_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][102] <= _T_20230 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][102] <= _T_20230 @[ifu_bp_ctl.scala 450:39] reg _T_20231 : UInt, rvclkhdr_544.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][6][7] : @[Reg.scala 28:19] _T_20231 <= bht_bank_wr_data_1_6_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][103] <= _T_20231 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][103] <= _T_20231 @[ifu_bp_ctl.scala 450:39] reg _T_20232 : UInt, rvclkhdr_544.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][6][8] : @[Reg.scala 28:19] _T_20232 <= bht_bank_wr_data_1_6_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][104] <= _T_20232 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][104] <= _T_20232 @[ifu_bp_ctl.scala 450:39] reg _T_20233 : UInt, rvclkhdr_544.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][6][9] : @[Reg.scala 28:19] _T_20233 <= bht_bank_wr_data_1_6_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][105] <= _T_20233 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][105] <= _T_20233 @[ifu_bp_ctl.scala 450:39] reg _T_20234 : UInt, rvclkhdr_544.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][6][10] : @[Reg.scala 28:19] _T_20234 <= bht_bank_wr_data_1_6_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][106] <= _T_20234 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][106] <= _T_20234 @[ifu_bp_ctl.scala 450:39] reg _T_20235 : UInt, rvclkhdr_544.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][6][11] : @[Reg.scala 28:19] _T_20235 <= bht_bank_wr_data_1_6_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][107] <= _T_20235 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][107] <= _T_20235 @[ifu_bp_ctl.scala 450:39] reg _T_20236 : UInt, rvclkhdr_544.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][6][12] : @[Reg.scala 28:19] _T_20236 <= bht_bank_wr_data_1_6_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][108] <= _T_20236 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][108] <= _T_20236 @[ifu_bp_ctl.scala 450:39] reg _T_20237 : UInt, rvclkhdr_544.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][6][13] : @[Reg.scala 28:19] _T_20237 <= bht_bank_wr_data_1_6_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][109] <= _T_20237 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][109] <= _T_20237 @[ifu_bp_ctl.scala 450:39] reg _T_20238 : UInt, rvclkhdr_544.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][6][14] : @[Reg.scala 28:19] _T_20238 <= bht_bank_wr_data_1_6_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][110] <= _T_20238 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][110] <= _T_20238 @[ifu_bp_ctl.scala 450:39] reg _T_20239 : UInt, rvclkhdr_544.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][6][15] : @[Reg.scala 28:19] _T_20239 <= bht_bank_wr_data_1_6_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][111] <= _T_20239 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][111] <= _T_20239 @[ifu_bp_ctl.scala 450:39] reg _T_20240 : UInt, rvclkhdr_545.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][7][0] : @[Reg.scala 28:19] _T_20240 <= bht_bank_wr_data_1_7_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][112] <= _T_20240 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][112] <= _T_20240 @[ifu_bp_ctl.scala 450:39] reg _T_20241 : UInt, rvclkhdr_545.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][7][1] : @[Reg.scala 28:19] _T_20241 <= bht_bank_wr_data_1_7_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][113] <= _T_20241 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][113] <= _T_20241 @[ifu_bp_ctl.scala 450:39] reg _T_20242 : UInt, rvclkhdr_545.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][7][2] : @[Reg.scala 28:19] _T_20242 <= bht_bank_wr_data_1_7_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][114] <= _T_20242 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][114] <= _T_20242 @[ifu_bp_ctl.scala 450:39] reg _T_20243 : UInt, rvclkhdr_545.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][7][3] : @[Reg.scala 28:19] _T_20243 <= bht_bank_wr_data_1_7_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][115] <= _T_20243 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][115] <= _T_20243 @[ifu_bp_ctl.scala 450:39] reg _T_20244 : UInt, rvclkhdr_545.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][7][4] : @[Reg.scala 28:19] _T_20244 <= bht_bank_wr_data_1_7_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][116] <= _T_20244 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][116] <= _T_20244 @[ifu_bp_ctl.scala 450:39] reg _T_20245 : UInt, rvclkhdr_545.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][7][5] : @[Reg.scala 28:19] _T_20245 <= bht_bank_wr_data_1_7_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][117] <= _T_20245 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][117] <= _T_20245 @[ifu_bp_ctl.scala 450:39] reg _T_20246 : UInt, rvclkhdr_545.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][7][6] : @[Reg.scala 28:19] _T_20246 <= bht_bank_wr_data_1_7_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][118] <= _T_20246 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][118] <= _T_20246 @[ifu_bp_ctl.scala 450:39] reg _T_20247 : UInt, rvclkhdr_545.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][7][7] : @[Reg.scala 28:19] _T_20247 <= bht_bank_wr_data_1_7_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][119] <= _T_20247 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][119] <= _T_20247 @[ifu_bp_ctl.scala 450:39] reg _T_20248 : UInt, rvclkhdr_545.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][7][8] : @[Reg.scala 28:19] _T_20248 <= bht_bank_wr_data_1_7_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][120] <= _T_20248 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][120] <= _T_20248 @[ifu_bp_ctl.scala 450:39] reg _T_20249 : UInt, rvclkhdr_545.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][7][9] : @[Reg.scala 28:19] _T_20249 <= bht_bank_wr_data_1_7_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][121] <= _T_20249 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][121] <= _T_20249 @[ifu_bp_ctl.scala 450:39] reg _T_20250 : UInt, rvclkhdr_545.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][7][10] : @[Reg.scala 28:19] _T_20250 <= bht_bank_wr_data_1_7_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][122] <= _T_20250 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][122] <= _T_20250 @[ifu_bp_ctl.scala 450:39] reg _T_20251 : UInt, rvclkhdr_545.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][7][11] : @[Reg.scala 28:19] _T_20251 <= bht_bank_wr_data_1_7_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][123] <= _T_20251 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][123] <= _T_20251 @[ifu_bp_ctl.scala 450:39] reg _T_20252 : UInt, rvclkhdr_545.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][7][12] : @[Reg.scala 28:19] _T_20252 <= bht_bank_wr_data_1_7_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][124] <= _T_20252 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][124] <= _T_20252 @[ifu_bp_ctl.scala 450:39] reg _T_20253 : UInt, rvclkhdr_545.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][7][13] : @[Reg.scala 28:19] _T_20253 <= bht_bank_wr_data_1_7_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][125] <= _T_20253 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][125] <= _T_20253 @[ifu_bp_ctl.scala 450:39] reg _T_20254 : UInt, rvclkhdr_545.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][7][14] : @[Reg.scala 28:19] _T_20254 <= bht_bank_wr_data_1_7_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][126] <= _T_20254 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][126] <= _T_20254 @[ifu_bp_ctl.scala 450:39] reg _T_20255 : UInt, rvclkhdr_545.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][7][15] : @[Reg.scala 28:19] _T_20255 <= bht_bank_wr_data_1_7_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][127] <= _T_20255 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][127] <= _T_20255 @[ifu_bp_ctl.scala 450:39] reg _T_20256 : UInt, rvclkhdr_546.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][8][0] : @[Reg.scala 28:19] _T_20256 <= bht_bank_wr_data_1_8_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][128] <= _T_20256 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][128] <= _T_20256 @[ifu_bp_ctl.scala 450:39] reg _T_20257 : UInt, rvclkhdr_546.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][8][1] : @[Reg.scala 28:19] _T_20257 <= bht_bank_wr_data_1_8_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][129] <= _T_20257 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][129] <= _T_20257 @[ifu_bp_ctl.scala 450:39] reg _T_20258 : UInt, rvclkhdr_546.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][8][2] : @[Reg.scala 28:19] _T_20258 <= bht_bank_wr_data_1_8_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][130] <= _T_20258 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][130] <= _T_20258 @[ifu_bp_ctl.scala 450:39] reg _T_20259 : UInt, rvclkhdr_546.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][8][3] : @[Reg.scala 28:19] _T_20259 <= bht_bank_wr_data_1_8_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][131] <= _T_20259 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][131] <= _T_20259 @[ifu_bp_ctl.scala 450:39] reg _T_20260 : UInt, rvclkhdr_546.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][8][4] : @[Reg.scala 28:19] _T_20260 <= bht_bank_wr_data_1_8_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][132] <= _T_20260 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][132] <= _T_20260 @[ifu_bp_ctl.scala 450:39] reg _T_20261 : UInt, rvclkhdr_546.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][8][5] : @[Reg.scala 28:19] _T_20261 <= bht_bank_wr_data_1_8_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][133] <= _T_20261 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][133] <= _T_20261 @[ifu_bp_ctl.scala 450:39] reg _T_20262 : UInt, rvclkhdr_546.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][8][6] : @[Reg.scala 28:19] _T_20262 <= bht_bank_wr_data_1_8_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][134] <= _T_20262 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][134] <= _T_20262 @[ifu_bp_ctl.scala 450:39] reg _T_20263 : UInt, rvclkhdr_546.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][8][7] : @[Reg.scala 28:19] _T_20263 <= bht_bank_wr_data_1_8_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][135] <= _T_20263 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][135] <= _T_20263 @[ifu_bp_ctl.scala 450:39] reg _T_20264 : UInt, rvclkhdr_546.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][8][8] : @[Reg.scala 28:19] _T_20264 <= bht_bank_wr_data_1_8_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][136] <= _T_20264 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][136] <= _T_20264 @[ifu_bp_ctl.scala 450:39] reg _T_20265 : UInt, rvclkhdr_546.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][8][9] : @[Reg.scala 28:19] _T_20265 <= bht_bank_wr_data_1_8_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][137] <= _T_20265 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][137] <= _T_20265 @[ifu_bp_ctl.scala 450:39] reg _T_20266 : UInt, rvclkhdr_546.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][8][10] : @[Reg.scala 28:19] _T_20266 <= bht_bank_wr_data_1_8_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][138] <= _T_20266 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][138] <= _T_20266 @[ifu_bp_ctl.scala 450:39] reg _T_20267 : UInt, rvclkhdr_546.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][8][11] : @[Reg.scala 28:19] _T_20267 <= bht_bank_wr_data_1_8_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][139] <= _T_20267 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][139] <= _T_20267 @[ifu_bp_ctl.scala 450:39] reg _T_20268 : UInt, rvclkhdr_546.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][8][12] : @[Reg.scala 28:19] _T_20268 <= bht_bank_wr_data_1_8_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][140] <= _T_20268 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][140] <= _T_20268 @[ifu_bp_ctl.scala 450:39] reg _T_20269 : UInt, rvclkhdr_546.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][8][13] : @[Reg.scala 28:19] _T_20269 <= bht_bank_wr_data_1_8_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][141] <= _T_20269 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][141] <= _T_20269 @[ifu_bp_ctl.scala 450:39] reg _T_20270 : UInt, rvclkhdr_546.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][8][14] : @[Reg.scala 28:19] _T_20270 <= bht_bank_wr_data_1_8_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][142] <= _T_20270 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][142] <= _T_20270 @[ifu_bp_ctl.scala 450:39] reg _T_20271 : UInt, rvclkhdr_546.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][8][15] : @[Reg.scala 28:19] _T_20271 <= bht_bank_wr_data_1_8_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][143] <= _T_20271 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][143] <= _T_20271 @[ifu_bp_ctl.scala 450:39] reg _T_20272 : UInt, rvclkhdr_547.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][9][0] : @[Reg.scala 28:19] _T_20272 <= bht_bank_wr_data_1_9_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][144] <= _T_20272 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][144] <= _T_20272 @[ifu_bp_ctl.scala 450:39] reg _T_20273 : UInt, rvclkhdr_547.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][9][1] : @[Reg.scala 28:19] _T_20273 <= bht_bank_wr_data_1_9_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][145] <= _T_20273 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][145] <= _T_20273 @[ifu_bp_ctl.scala 450:39] reg _T_20274 : UInt, rvclkhdr_547.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][9][2] : @[Reg.scala 28:19] _T_20274 <= bht_bank_wr_data_1_9_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][146] <= _T_20274 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][146] <= _T_20274 @[ifu_bp_ctl.scala 450:39] reg _T_20275 : UInt, rvclkhdr_547.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][9][3] : @[Reg.scala 28:19] _T_20275 <= bht_bank_wr_data_1_9_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][147] <= _T_20275 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][147] <= _T_20275 @[ifu_bp_ctl.scala 450:39] reg _T_20276 : UInt, rvclkhdr_547.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][9][4] : @[Reg.scala 28:19] _T_20276 <= bht_bank_wr_data_1_9_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][148] <= _T_20276 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][148] <= _T_20276 @[ifu_bp_ctl.scala 450:39] reg _T_20277 : UInt, rvclkhdr_547.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][9][5] : @[Reg.scala 28:19] _T_20277 <= bht_bank_wr_data_1_9_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][149] <= _T_20277 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][149] <= _T_20277 @[ifu_bp_ctl.scala 450:39] reg _T_20278 : UInt, rvclkhdr_547.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][9][6] : @[Reg.scala 28:19] _T_20278 <= bht_bank_wr_data_1_9_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][150] <= _T_20278 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][150] <= _T_20278 @[ifu_bp_ctl.scala 450:39] reg _T_20279 : UInt, rvclkhdr_547.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][9][7] : @[Reg.scala 28:19] _T_20279 <= bht_bank_wr_data_1_9_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][151] <= _T_20279 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][151] <= _T_20279 @[ifu_bp_ctl.scala 450:39] reg _T_20280 : UInt, rvclkhdr_547.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][9][8] : @[Reg.scala 28:19] _T_20280 <= bht_bank_wr_data_1_9_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][152] <= _T_20280 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][152] <= _T_20280 @[ifu_bp_ctl.scala 450:39] reg _T_20281 : UInt, rvclkhdr_547.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][9][9] : @[Reg.scala 28:19] _T_20281 <= bht_bank_wr_data_1_9_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][153] <= _T_20281 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][153] <= _T_20281 @[ifu_bp_ctl.scala 450:39] reg _T_20282 : UInt, rvclkhdr_547.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][9][10] : @[Reg.scala 28:19] _T_20282 <= bht_bank_wr_data_1_9_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][154] <= _T_20282 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][154] <= _T_20282 @[ifu_bp_ctl.scala 450:39] reg _T_20283 : UInt, rvclkhdr_547.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][9][11] : @[Reg.scala 28:19] _T_20283 <= bht_bank_wr_data_1_9_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][155] <= _T_20283 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][155] <= _T_20283 @[ifu_bp_ctl.scala 450:39] reg _T_20284 : UInt, rvclkhdr_547.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][9][12] : @[Reg.scala 28:19] _T_20284 <= bht_bank_wr_data_1_9_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][156] <= _T_20284 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][156] <= _T_20284 @[ifu_bp_ctl.scala 450:39] reg _T_20285 : UInt, rvclkhdr_547.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][9][13] : @[Reg.scala 28:19] _T_20285 <= bht_bank_wr_data_1_9_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][157] <= _T_20285 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][157] <= _T_20285 @[ifu_bp_ctl.scala 450:39] reg _T_20286 : UInt, rvclkhdr_547.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][9][14] : @[Reg.scala 28:19] _T_20286 <= bht_bank_wr_data_1_9_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][158] <= _T_20286 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][158] <= _T_20286 @[ifu_bp_ctl.scala 450:39] reg _T_20287 : UInt, rvclkhdr_547.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][9][15] : @[Reg.scala 28:19] _T_20287 <= bht_bank_wr_data_1_9_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][159] <= _T_20287 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][159] <= _T_20287 @[ifu_bp_ctl.scala 450:39] reg _T_20288 : UInt, rvclkhdr_548.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][10][0] : @[Reg.scala 28:19] _T_20288 <= bht_bank_wr_data_1_10_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][160] <= _T_20288 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][160] <= _T_20288 @[ifu_bp_ctl.scala 450:39] reg _T_20289 : UInt, rvclkhdr_548.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][10][1] : @[Reg.scala 28:19] _T_20289 <= bht_bank_wr_data_1_10_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][161] <= _T_20289 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][161] <= _T_20289 @[ifu_bp_ctl.scala 450:39] reg _T_20290 : UInt, rvclkhdr_548.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][10][2] : @[Reg.scala 28:19] _T_20290 <= bht_bank_wr_data_1_10_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][162] <= _T_20290 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][162] <= _T_20290 @[ifu_bp_ctl.scala 450:39] reg _T_20291 : UInt, rvclkhdr_548.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][10][3] : @[Reg.scala 28:19] _T_20291 <= bht_bank_wr_data_1_10_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][163] <= _T_20291 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][163] <= _T_20291 @[ifu_bp_ctl.scala 450:39] reg _T_20292 : UInt, rvclkhdr_548.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][10][4] : @[Reg.scala 28:19] _T_20292 <= bht_bank_wr_data_1_10_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][164] <= _T_20292 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][164] <= _T_20292 @[ifu_bp_ctl.scala 450:39] reg _T_20293 : UInt, rvclkhdr_548.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][10][5] : @[Reg.scala 28:19] _T_20293 <= bht_bank_wr_data_1_10_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][165] <= _T_20293 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][165] <= _T_20293 @[ifu_bp_ctl.scala 450:39] reg _T_20294 : UInt, rvclkhdr_548.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][10][6] : @[Reg.scala 28:19] _T_20294 <= bht_bank_wr_data_1_10_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][166] <= _T_20294 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][166] <= _T_20294 @[ifu_bp_ctl.scala 450:39] reg _T_20295 : UInt, rvclkhdr_548.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][10][7] : @[Reg.scala 28:19] _T_20295 <= bht_bank_wr_data_1_10_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][167] <= _T_20295 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][167] <= _T_20295 @[ifu_bp_ctl.scala 450:39] reg _T_20296 : UInt, rvclkhdr_548.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][10][8] : @[Reg.scala 28:19] _T_20296 <= bht_bank_wr_data_1_10_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][168] <= _T_20296 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][168] <= _T_20296 @[ifu_bp_ctl.scala 450:39] reg _T_20297 : UInt, rvclkhdr_548.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][10][9] : @[Reg.scala 28:19] _T_20297 <= bht_bank_wr_data_1_10_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][169] <= _T_20297 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][169] <= _T_20297 @[ifu_bp_ctl.scala 450:39] reg _T_20298 : UInt, rvclkhdr_548.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][10][10] : @[Reg.scala 28:19] _T_20298 <= bht_bank_wr_data_1_10_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][170] <= _T_20298 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][170] <= _T_20298 @[ifu_bp_ctl.scala 450:39] reg _T_20299 : UInt, rvclkhdr_548.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][10][11] : @[Reg.scala 28:19] _T_20299 <= bht_bank_wr_data_1_10_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][171] <= _T_20299 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][171] <= _T_20299 @[ifu_bp_ctl.scala 450:39] reg _T_20300 : UInt, rvclkhdr_548.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][10][12] : @[Reg.scala 28:19] _T_20300 <= bht_bank_wr_data_1_10_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][172] <= _T_20300 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][172] <= _T_20300 @[ifu_bp_ctl.scala 450:39] reg _T_20301 : UInt, rvclkhdr_548.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][10][13] : @[Reg.scala 28:19] _T_20301 <= bht_bank_wr_data_1_10_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][173] <= _T_20301 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][173] <= _T_20301 @[ifu_bp_ctl.scala 450:39] reg _T_20302 : UInt, rvclkhdr_548.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][10][14] : @[Reg.scala 28:19] _T_20302 <= bht_bank_wr_data_1_10_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][174] <= _T_20302 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][174] <= _T_20302 @[ifu_bp_ctl.scala 450:39] reg _T_20303 : UInt, rvclkhdr_548.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][10][15] : @[Reg.scala 28:19] _T_20303 <= bht_bank_wr_data_1_10_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][175] <= _T_20303 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][175] <= _T_20303 @[ifu_bp_ctl.scala 450:39] reg _T_20304 : UInt, rvclkhdr_549.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][11][0] : @[Reg.scala 28:19] _T_20304 <= bht_bank_wr_data_1_11_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][176] <= _T_20304 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][176] <= _T_20304 @[ifu_bp_ctl.scala 450:39] reg _T_20305 : UInt, rvclkhdr_549.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][11][1] : @[Reg.scala 28:19] _T_20305 <= bht_bank_wr_data_1_11_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][177] <= _T_20305 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][177] <= _T_20305 @[ifu_bp_ctl.scala 450:39] reg _T_20306 : UInt, rvclkhdr_549.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][11][2] : @[Reg.scala 28:19] _T_20306 <= bht_bank_wr_data_1_11_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][178] <= _T_20306 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][178] <= _T_20306 @[ifu_bp_ctl.scala 450:39] reg _T_20307 : UInt, rvclkhdr_549.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][11][3] : @[Reg.scala 28:19] _T_20307 <= bht_bank_wr_data_1_11_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][179] <= _T_20307 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][179] <= _T_20307 @[ifu_bp_ctl.scala 450:39] reg _T_20308 : UInt, rvclkhdr_549.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][11][4] : @[Reg.scala 28:19] _T_20308 <= bht_bank_wr_data_1_11_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][180] <= _T_20308 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][180] <= _T_20308 @[ifu_bp_ctl.scala 450:39] reg _T_20309 : UInt, rvclkhdr_549.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][11][5] : @[Reg.scala 28:19] _T_20309 <= bht_bank_wr_data_1_11_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][181] <= _T_20309 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][181] <= _T_20309 @[ifu_bp_ctl.scala 450:39] reg _T_20310 : UInt, rvclkhdr_549.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][11][6] : @[Reg.scala 28:19] _T_20310 <= bht_bank_wr_data_1_11_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][182] <= _T_20310 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][182] <= _T_20310 @[ifu_bp_ctl.scala 450:39] reg _T_20311 : UInt, rvclkhdr_549.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][11][7] : @[Reg.scala 28:19] _T_20311 <= bht_bank_wr_data_1_11_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][183] <= _T_20311 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][183] <= _T_20311 @[ifu_bp_ctl.scala 450:39] reg _T_20312 : UInt, rvclkhdr_549.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][11][8] : @[Reg.scala 28:19] _T_20312 <= bht_bank_wr_data_1_11_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][184] <= _T_20312 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][184] <= _T_20312 @[ifu_bp_ctl.scala 450:39] reg _T_20313 : UInt, rvclkhdr_549.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][11][9] : @[Reg.scala 28:19] _T_20313 <= bht_bank_wr_data_1_11_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][185] <= _T_20313 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][185] <= _T_20313 @[ifu_bp_ctl.scala 450:39] reg _T_20314 : UInt, rvclkhdr_549.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][11][10] : @[Reg.scala 28:19] _T_20314 <= bht_bank_wr_data_1_11_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][186] <= _T_20314 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][186] <= _T_20314 @[ifu_bp_ctl.scala 450:39] reg _T_20315 : UInt, rvclkhdr_549.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][11][11] : @[Reg.scala 28:19] _T_20315 <= bht_bank_wr_data_1_11_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][187] <= _T_20315 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][187] <= _T_20315 @[ifu_bp_ctl.scala 450:39] reg _T_20316 : UInt, rvclkhdr_549.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][11][12] : @[Reg.scala 28:19] _T_20316 <= bht_bank_wr_data_1_11_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][188] <= _T_20316 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][188] <= _T_20316 @[ifu_bp_ctl.scala 450:39] reg _T_20317 : UInt, rvclkhdr_549.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][11][13] : @[Reg.scala 28:19] _T_20317 <= bht_bank_wr_data_1_11_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][189] <= _T_20317 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][189] <= _T_20317 @[ifu_bp_ctl.scala 450:39] reg _T_20318 : UInt, rvclkhdr_549.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][11][14] : @[Reg.scala 28:19] _T_20318 <= bht_bank_wr_data_1_11_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][190] <= _T_20318 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][190] <= _T_20318 @[ifu_bp_ctl.scala 450:39] reg _T_20319 : UInt, rvclkhdr_549.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][11][15] : @[Reg.scala 28:19] _T_20319 <= bht_bank_wr_data_1_11_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][191] <= _T_20319 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][191] <= _T_20319 @[ifu_bp_ctl.scala 450:39] reg _T_20320 : UInt, rvclkhdr_550.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][12][0] : @[Reg.scala 28:19] _T_20320 <= bht_bank_wr_data_1_12_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][192] <= _T_20320 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][192] <= _T_20320 @[ifu_bp_ctl.scala 450:39] reg _T_20321 : UInt, rvclkhdr_550.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][12][1] : @[Reg.scala 28:19] _T_20321 <= bht_bank_wr_data_1_12_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][193] <= _T_20321 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][193] <= _T_20321 @[ifu_bp_ctl.scala 450:39] reg _T_20322 : UInt, rvclkhdr_550.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][12][2] : @[Reg.scala 28:19] _T_20322 <= bht_bank_wr_data_1_12_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][194] <= _T_20322 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][194] <= _T_20322 @[ifu_bp_ctl.scala 450:39] reg _T_20323 : UInt, rvclkhdr_550.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][12][3] : @[Reg.scala 28:19] _T_20323 <= bht_bank_wr_data_1_12_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][195] <= _T_20323 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][195] <= _T_20323 @[ifu_bp_ctl.scala 450:39] reg _T_20324 : UInt, rvclkhdr_550.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][12][4] : @[Reg.scala 28:19] _T_20324 <= bht_bank_wr_data_1_12_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][196] <= _T_20324 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][196] <= _T_20324 @[ifu_bp_ctl.scala 450:39] reg _T_20325 : UInt, rvclkhdr_550.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][12][5] : @[Reg.scala 28:19] _T_20325 <= bht_bank_wr_data_1_12_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][197] <= _T_20325 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][197] <= _T_20325 @[ifu_bp_ctl.scala 450:39] reg _T_20326 : UInt, rvclkhdr_550.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][12][6] : @[Reg.scala 28:19] _T_20326 <= bht_bank_wr_data_1_12_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][198] <= _T_20326 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][198] <= _T_20326 @[ifu_bp_ctl.scala 450:39] reg _T_20327 : UInt, rvclkhdr_550.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][12][7] : @[Reg.scala 28:19] _T_20327 <= bht_bank_wr_data_1_12_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][199] <= _T_20327 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][199] <= _T_20327 @[ifu_bp_ctl.scala 450:39] reg _T_20328 : UInt, rvclkhdr_550.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][12][8] : @[Reg.scala 28:19] _T_20328 <= bht_bank_wr_data_1_12_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][200] <= _T_20328 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][200] <= _T_20328 @[ifu_bp_ctl.scala 450:39] reg _T_20329 : UInt, rvclkhdr_550.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][12][9] : @[Reg.scala 28:19] _T_20329 <= bht_bank_wr_data_1_12_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][201] <= _T_20329 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][201] <= _T_20329 @[ifu_bp_ctl.scala 450:39] reg _T_20330 : UInt, rvclkhdr_550.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][12][10] : @[Reg.scala 28:19] _T_20330 <= bht_bank_wr_data_1_12_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][202] <= _T_20330 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][202] <= _T_20330 @[ifu_bp_ctl.scala 450:39] reg _T_20331 : UInt, rvclkhdr_550.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][12][11] : @[Reg.scala 28:19] _T_20331 <= bht_bank_wr_data_1_12_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][203] <= _T_20331 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][203] <= _T_20331 @[ifu_bp_ctl.scala 450:39] reg _T_20332 : UInt, rvclkhdr_550.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][12][12] : @[Reg.scala 28:19] _T_20332 <= bht_bank_wr_data_1_12_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][204] <= _T_20332 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][204] <= _T_20332 @[ifu_bp_ctl.scala 450:39] reg _T_20333 : UInt, rvclkhdr_550.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][12][13] : @[Reg.scala 28:19] _T_20333 <= bht_bank_wr_data_1_12_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][205] <= _T_20333 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][205] <= _T_20333 @[ifu_bp_ctl.scala 450:39] reg _T_20334 : UInt, rvclkhdr_550.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][12][14] : @[Reg.scala 28:19] _T_20334 <= bht_bank_wr_data_1_12_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][206] <= _T_20334 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][206] <= _T_20334 @[ifu_bp_ctl.scala 450:39] reg _T_20335 : UInt, rvclkhdr_550.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][12][15] : @[Reg.scala 28:19] _T_20335 <= bht_bank_wr_data_1_12_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][207] <= _T_20335 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][207] <= _T_20335 @[ifu_bp_ctl.scala 450:39] reg _T_20336 : UInt, rvclkhdr_551.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][13][0] : @[Reg.scala 28:19] _T_20336 <= bht_bank_wr_data_1_13_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][208] <= _T_20336 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][208] <= _T_20336 @[ifu_bp_ctl.scala 450:39] reg _T_20337 : UInt, rvclkhdr_551.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][13][1] : @[Reg.scala 28:19] _T_20337 <= bht_bank_wr_data_1_13_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][209] <= _T_20337 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][209] <= _T_20337 @[ifu_bp_ctl.scala 450:39] reg _T_20338 : UInt, rvclkhdr_551.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][13][2] : @[Reg.scala 28:19] _T_20338 <= bht_bank_wr_data_1_13_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][210] <= _T_20338 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][210] <= _T_20338 @[ifu_bp_ctl.scala 450:39] reg _T_20339 : UInt, rvclkhdr_551.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][13][3] : @[Reg.scala 28:19] _T_20339 <= bht_bank_wr_data_1_13_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][211] <= _T_20339 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][211] <= _T_20339 @[ifu_bp_ctl.scala 450:39] reg _T_20340 : UInt, rvclkhdr_551.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][13][4] : @[Reg.scala 28:19] _T_20340 <= bht_bank_wr_data_1_13_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][212] <= _T_20340 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][212] <= _T_20340 @[ifu_bp_ctl.scala 450:39] reg _T_20341 : UInt, rvclkhdr_551.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][13][5] : @[Reg.scala 28:19] _T_20341 <= bht_bank_wr_data_1_13_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][213] <= _T_20341 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][213] <= _T_20341 @[ifu_bp_ctl.scala 450:39] reg _T_20342 : UInt, rvclkhdr_551.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][13][6] : @[Reg.scala 28:19] _T_20342 <= bht_bank_wr_data_1_13_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][214] <= _T_20342 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][214] <= _T_20342 @[ifu_bp_ctl.scala 450:39] reg _T_20343 : UInt, rvclkhdr_551.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][13][7] : @[Reg.scala 28:19] _T_20343 <= bht_bank_wr_data_1_13_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][215] <= _T_20343 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][215] <= _T_20343 @[ifu_bp_ctl.scala 450:39] reg _T_20344 : UInt, rvclkhdr_551.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][13][8] : @[Reg.scala 28:19] _T_20344 <= bht_bank_wr_data_1_13_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][216] <= _T_20344 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][216] <= _T_20344 @[ifu_bp_ctl.scala 450:39] reg _T_20345 : UInt, rvclkhdr_551.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][13][9] : @[Reg.scala 28:19] _T_20345 <= bht_bank_wr_data_1_13_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][217] <= _T_20345 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][217] <= _T_20345 @[ifu_bp_ctl.scala 450:39] reg _T_20346 : UInt, rvclkhdr_551.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][13][10] : @[Reg.scala 28:19] _T_20346 <= bht_bank_wr_data_1_13_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][218] <= _T_20346 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][218] <= _T_20346 @[ifu_bp_ctl.scala 450:39] reg _T_20347 : UInt, rvclkhdr_551.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][13][11] : @[Reg.scala 28:19] _T_20347 <= bht_bank_wr_data_1_13_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][219] <= _T_20347 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][219] <= _T_20347 @[ifu_bp_ctl.scala 450:39] reg _T_20348 : UInt, rvclkhdr_551.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][13][12] : @[Reg.scala 28:19] _T_20348 <= bht_bank_wr_data_1_13_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][220] <= _T_20348 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][220] <= _T_20348 @[ifu_bp_ctl.scala 450:39] reg _T_20349 : UInt, rvclkhdr_551.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][13][13] : @[Reg.scala 28:19] _T_20349 <= bht_bank_wr_data_1_13_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][221] <= _T_20349 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][221] <= _T_20349 @[ifu_bp_ctl.scala 450:39] reg _T_20350 : UInt, rvclkhdr_551.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][13][14] : @[Reg.scala 28:19] _T_20350 <= bht_bank_wr_data_1_13_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][222] <= _T_20350 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][222] <= _T_20350 @[ifu_bp_ctl.scala 450:39] reg _T_20351 : UInt, rvclkhdr_551.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][13][15] : @[Reg.scala 28:19] _T_20351 <= bht_bank_wr_data_1_13_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][223] <= _T_20351 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][223] <= _T_20351 @[ifu_bp_ctl.scala 450:39] reg _T_20352 : UInt, rvclkhdr_552.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][14][0] : @[Reg.scala 28:19] _T_20352 <= bht_bank_wr_data_1_14_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][224] <= _T_20352 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][224] <= _T_20352 @[ifu_bp_ctl.scala 450:39] reg _T_20353 : UInt, rvclkhdr_552.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][14][1] : @[Reg.scala 28:19] _T_20353 <= bht_bank_wr_data_1_14_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][225] <= _T_20353 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][225] <= _T_20353 @[ifu_bp_ctl.scala 450:39] reg _T_20354 : UInt, rvclkhdr_552.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][14][2] : @[Reg.scala 28:19] _T_20354 <= bht_bank_wr_data_1_14_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][226] <= _T_20354 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][226] <= _T_20354 @[ifu_bp_ctl.scala 450:39] reg _T_20355 : UInt, rvclkhdr_552.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][14][3] : @[Reg.scala 28:19] _T_20355 <= bht_bank_wr_data_1_14_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][227] <= _T_20355 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][227] <= _T_20355 @[ifu_bp_ctl.scala 450:39] reg _T_20356 : UInt, rvclkhdr_552.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][14][4] : @[Reg.scala 28:19] _T_20356 <= bht_bank_wr_data_1_14_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][228] <= _T_20356 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][228] <= _T_20356 @[ifu_bp_ctl.scala 450:39] reg _T_20357 : UInt, rvclkhdr_552.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][14][5] : @[Reg.scala 28:19] _T_20357 <= bht_bank_wr_data_1_14_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][229] <= _T_20357 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][229] <= _T_20357 @[ifu_bp_ctl.scala 450:39] reg _T_20358 : UInt, rvclkhdr_552.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][14][6] : @[Reg.scala 28:19] _T_20358 <= bht_bank_wr_data_1_14_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][230] <= _T_20358 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][230] <= _T_20358 @[ifu_bp_ctl.scala 450:39] reg _T_20359 : UInt, rvclkhdr_552.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][14][7] : @[Reg.scala 28:19] _T_20359 <= bht_bank_wr_data_1_14_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][231] <= _T_20359 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][231] <= _T_20359 @[ifu_bp_ctl.scala 450:39] reg _T_20360 : UInt, rvclkhdr_552.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][14][8] : @[Reg.scala 28:19] _T_20360 <= bht_bank_wr_data_1_14_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][232] <= _T_20360 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][232] <= _T_20360 @[ifu_bp_ctl.scala 450:39] reg _T_20361 : UInt, rvclkhdr_552.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][14][9] : @[Reg.scala 28:19] _T_20361 <= bht_bank_wr_data_1_14_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][233] <= _T_20361 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][233] <= _T_20361 @[ifu_bp_ctl.scala 450:39] reg _T_20362 : UInt, rvclkhdr_552.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][14][10] : @[Reg.scala 28:19] _T_20362 <= bht_bank_wr_data_1_14_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][234] <= _T_20362 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][234] <= _T_20362 @[ifu_bp_ctl.scala 450:39] reg _T_20363 : UInt, rvclkhdr_552.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][14][11] : @[Reg.scala 28:19] _T_20363 <= bht_bank_wr_data_1_14_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][235] <= _T_20363 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][235] <= _T_20363 @[ifu_bp_ctl.scala 450:39] reg _T_20364 : UInt, rvclkhdr_552.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][14][12] : @[Reg.scala 28:19] _T_20364 <= bht_bank_wr_data_1_14_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][236] <= _T_20364 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][236] <= _T_20364 @[ifu_bp_ctl.scala 450:39] reg _T_20365 : UInt, rvclkhdr_552.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][14][13] : @[Reg.scala 28:19] _T_20365 <= bht_bank_wr_data_1_14_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][237] <= _T_20365 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][237] <= _T_20365 @[ifu_bp_ctl.scala 450:39] reg _T_20366 : UInt, rvclkhdr_552.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][14][14] : @[Reg.scala 28:19] _T_20366 <= bht_bank_wr_data_1_14_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][238] <= _T_20366 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][238] <= _T_20366 @[ifu_bp_ctl.scala 450:39] reg _T_20367 : UInt, rvclkhdr_552.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][14][15] : @[Reg.scala 28:19] _T_20367 <= bht_bank_wr_data_1_14_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][239] <= _T_20367 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][239] <= _T_20367 @[ifu_bp_ctl.scala 450:39] reg _T_20368 : UInt, rvclkhdr_553.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][15][0] : @[Reg.scala 28:19] _T_20368 <= bht_bank_wr_data_1_15_0 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][240] <= _T_20368 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][240] <= _T_20368 @[ifu_bp_ctl.scala 450:39] reg _T_20369 : UInt, rvclkhdr_553.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][15][1] : @[Reg.scala 28:19] _T_20369 <= bht_bank_wr_data_1_15_1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][241] <= _T_20369 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][241] <= _T_20369 @[ifu_bp_ctl.scala 450:39] reg _T_20370 : UInt, rvclkhdr_553.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][15][2] : @[Reg.scala 28:19] _T_20370 <= bht_bank_wr_data_1_15_2 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][242] <= _T_20370 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][242] <= _T_20370 @[ifu_bp_ctl.scala 450:39] reg _T_20371 : UInt, rvclkhdr_553.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][15][3] : @[Reg.scala 28:19] _T_20371 <= bht_bank_wr_data_1_15_3 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][243] <= _T_20371 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][243] <= _T_20371 @[ifu_bp_ctl.scala 450:39] reg _T_20372 : UInt, rvclkhdr_553.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][15][4] : @[Reg.scala 28:19] _T_20372 <= bht_bank_wr_data_1_15_4 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][244] <= _T_20372 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][244] <= _T_20372 @[ifu_bp_ctl.scala 450:39] reg _T_20373 : UInt, rvclkhdr_553.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][15][5] : @[Reg.scala 28:19] _T_20373 <= bht_bank_wr_data_1_15_5 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][245] <= _T_20373 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][245] <= _T_20373 @[ifu_bp_ctl.scala 450:39] reg _T_20374 : UInt, rvclkhdr_553.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][15][6] : @[Reg.scala 28:19] _T_20374 <= bht_bank_wr_data_1_15_6 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][246] <= _T_20374 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][246] <= _T_20374 @[ifu_bp_ctl.scala 450:39] reg _T_20375 : UInt, rvclkhdr_553.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][15][7] : @[Reg.scala 28:19] _T_20375 <= bht_bank_wr_data_1_15_7 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][247] <= _T_20375 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][247] <= _T_20375 @[ifu_bp_ctl.scala 450:39] reg _T_20376 : UInt, rvclkhdr_553.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][15][8] : @[Reg.scala 28:19] _T_20376 <= bht_bank_wr_data_1_15_8 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][248] <= _T_20376 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][248] <= _T_20376 @[ifu_bp_ctl.scala 450:39] reg _T_20377 : UInt, rvclkhdr_553.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][15][9] : @[Reg.scala 28:19] _T_20377 <= bht_bank_wr_data_1_15_9 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][249] <= _T_20377 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][249] <= _T_20377 @[ifu_bp_ctl.scala 450:39] reg _T_20378 : UInt, rvclkhdr_553.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][15][10] : @[Reg.scala 28:19] _T_20378 <= bht_bank_wr_data_1_15_10 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][250] <= _T_20378 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][250] <= _T_20378 @[ifu_bp_ctl.scala 450:39] reg _T_20379 : UInt, rvclkhdr_553.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][15][11] : @[Reg.scala 28:19] _T_20379 <= bht_bank_wr_data_1_15_11 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][251] <= _T_20379 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][251] <= _T_20379 @[ifu_bp_ctl.scala 450:39] reg _T_20380 : UInt, rvclkhdr_553.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][15][12] : @[Reg.scala 28:19] _T_20380 <= bht_bank_wr_data_1_15_12 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][252] <= _T_20380 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][252] <= _T_20380 @[ifu_bp_ctl.scala 450:39] reg _T_20381 : UInt, rvclkhdr_553.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][15][13] : @[Reg.scala 28:19] _T_20381 <= bht_bank_wr_data_1_15_13 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][253] <= _T_20381 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][253] <= _T_20381 @[ifu_bp_ctl.scala 450:39] reg _T_20382 : UInt, rvclkhdr_553.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][15][14] : @[Reg.scala 28:19] _T_20382 <= bht_bank_wr_data_1_15_14 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][254] <= _T_20382 @[ifu_bp_ctl.scala 449:39] + bht_bank_rd_data_out[1][254] <= _T_20382 @[ifu_bp_ctl.scala 450:39] reg _T_20383 : UInt, rvclkhdr_553.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when bht_bank_sel[1][15][15] : @[Reg.scala 28:19] _T_20383 <= bht_bank_wr_data_1_15_15 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - bht_bank_rd_data_out[1][255] <= _T_20383 @[ifu_bp_ctl.scala 449:39] - node _T_20384 = eq(bht_rd_addr_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 453:79] - node _T_20385 = bits(_T_20384, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20386 = eq(bht_rd_addr_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 453:79] - node _T_20387 = bits(_T_20386, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20388 = eq(bht_rd_addr_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 453:79] - node _T_20389 = bits(_T_20388, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20390 = eq(bht_rd_addr_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 453:79] - node _T_20391 = bits(_T_20390, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20392 = eq(bht_rd_addr_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 453:79] - node _T_20393 = bits(_T_20392, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20394 = eq(bht_rd_addr_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 453:79] - node _T_20395 = bits(_T_20394, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20396 = eq(bht_rd_addr_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 453:79] - node _T_20397 = bits(_T_20396, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20398 = eq(bht_rd_addr_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 453:79] - node _T_20399 = bits(_T_20398, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20400 = eq(bht_rd_addr_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 453:79] - node _T_20401 = bits(_T_20400, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20402 = eq(bht_rd_addr_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 453:79] - node _T_20403 = bits(_T_20402, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20404 = eq(bht_rd_addr_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 453:79] - node _T_20405 = bits(_T_20404, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20406 = eq(bht_rd_addr_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 453:79] - node _T_20407 = bits(_T_20406, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20408 = eq(bht_rd_addr_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 453:79] - node _T_20409 = bits(_T_20408, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20410 = eq(bht_rd_addr_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 453:79] - node _T_20411 = bits(_T_20410, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20412 = eq(bht_rd_addr_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 453:79] - node _T_20413 = bits(_T_20412, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20414 = eq(bht_rd_addr_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 453:79] - node _T_20415 = bits(_T_20414, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20416 = eq(bht_rd_addr_f, UInt<5>("h010")) @[ifu_bp_ctl.scala 453:79] - node _T_20417 = bits(_T_20416, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20418 = eq(bht_rd_addr_f, UInt<5>("h011")) @[ifu_bp_ctl.scala 453:79] - node _T_20419 = bits(_T_20418, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20420 = eq(bht_rd_addr_f, UInt<5>("h012")) @[ifu_bp_ctl.scala 453:79] - node _T_20421 = bits(_T_20420, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20422 = eq(bht_rd_addr_f, UInt<5>("h013")) @[ifu_bp_ctl.scala 453:79] - node _T_20423 = bits(_T_20422, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20424 = eq(bht_rd_addr_f, UInt<5>("h014")) @[ifu_bp_ctl.scala 453:79] - node _T_20425 = bits(_T_20424, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20426 = eq(bht_rd_addr_f, UInt<5>("h015")) @[ifu_bp_ctl.scala 453:79] - node _T_20427 = bits(_T_20426, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20428 = eq(bht_rd_addr_f, UInt<5>("h016")) @[ifu_bp_ctl.scala 453:79] - node _T_20429 = bits(_T_20428, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20430 = eq(bht_rd_addr_f, UInt<5>("h017")) @[ifu_bp_ctl.scala 453:79] - node _T_20431 = bits(_T_20430, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20432 = eq(bht_rd_addr_f, UInt<5>("h018")) @[ifu_bp_ctl.scala 453:79] - node _T_20433 = bits(_T_20432, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20434 = eq(bht_rd_addr_f, UInt<5>("h019")) @[ifu_bp_ctl.scala 453:79] - node _T_20435 = bits(_T_20434, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20436 = eq(bht_rd_addr_f, UInt<5>("h01a")) @[ifu_bp_ctl.scala 453:79] - node _T_20437 = bits(_T_20436, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20438 = eq(bht_rd_addr_f, UInt<5>("h01b")) @[ifu_bp_ctl.scala 453:79] - node _T_20439 = bits(_T_20438, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20440 = eq(bht_rd_addr_f, UInt<5>("h01c")) @[ifu_bp_ctl.scala 453:79] - node _T_20441 = bits(_T_20440, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20442 = eq(bht_rd_addr_f, UInt<5>("h01d")) @[ifu_bp_ctl.scala 453:79] - node _T_20443 = bits(_T_20442, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20444 = eq(bht_rd_addr_f, UInt<5>("h01e")) @[ifu_bp_ctl.scala 453:79] - node _T_20445 = bits(_T_20444, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20446 = eq(bht_rd_addr_f, UInt<5>("h01f")) @[ifu_bp_ctl.scala 453:79] - node _T_20447 = bits(_T_20446, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20448 = eq(bht_rd_addr_f, UInt<6>("h020")) @[ifu_bp_ctl.scala 453:79] - node _T_20449 = bits(_T_20448, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20450 = eq(bht_rd_addr_f, UInt<6>("h021")) @[ifu_bp_ctl.scala 453:79] - node _T_20451 = bits(_T_20450, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20452 = eq(bht_rd_addr_f, UInt<6>("h022")) @[ifu_bp_ctl.scala 453:79] - node _T_20453 = bits(_T_20452, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20454 = eq(bht_rd_addr_f, UInt<6>("h023")) @[ifu_bp_ctl.scala 453:79] - node _T_20455 = bits(_T_20454, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20456 = eq(bht_rd_addr_f, UInt<6>("h024")) @[ifu_bp_ctl.scala 453:79] - node _T_20457 = bits(_T_20456, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20458 = eq(bht_rd_addr_f, UInt<6>("h025")) @[ifu_bp_ctl.scala 453:79] - node _T_20459 = bits(_T_20458, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20460 = eq(bht_rd_addr_f, UInt<6>("h026")) @[ifu_bp_ctl.scala 453:79] - node _T_20461 = bits(_T_20460, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20462 = eq(bht_rd_addr_f, UInt<6>("h027")) @[ifu_bp_ctl.scala 453:79] - node _T_20463 = bits(_T_20462, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20464 = eq(bht_rd_addr_f, UInt<6>("h028")) @[ifu_bp_ctl.scala 453:79] - node _T_20465 = bits(_T_20464, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20466 = eq(bht_rd_addr_f, UInt<6>("h029")) @[ifu_bp_ctl.scala 453:79] - node _T_20467 = bits(_T_20466, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20468 = eq(bht_rd_addr_f, UInt<6>("h02a")) @[ifu_bp_ctl.scala 453:79] - node _T_20469 = bits(_T_20468, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20470 = eq(bht_rd_addr_f, UInt<6>("h02b")) @[ifu_bp_ctl.scala 453:79] - node _T_20471 = bits(_T_20470, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20472 = eq(bht_rd_addr_f, UInt<6>("h02c")) @[ifu_bp_ctl.scala 453:79] - node _T_20473 = bits(_T_20472, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20474 = eq(bht_rd_addr_f, UInt<6>("h02d")) @[ifu_bp_ctl.scala 453:79] - node _T_20475 = bits(_T_20474, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20476 = eq(bht_rd_addr_f, UInt<6>("h02e")) @[ifu_bp_ctl.scala 453:79] - node _T_20477 = bits(_T_20476, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20478 = eq(bht_rd_addr_f, UInt<6>("h02f")) @[ifu_bp_ctl.scala 453:79] - node _T_20479 = bits(_T_20478, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20480 = eq(bht_rd_addr_f, UInt<6>("h030")) @[ifu_bp_ctl.scala 453:79] - node _T_20481 = bits(_T_20480, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20482 = eq(bht_rd_addr_f, UInt<6>("h031")) @[ifu_bp_ctl.scala 453:79] - node _T_20483 = bits(_T_20482, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20484 = eq(bht_rd_addr_f, UInt<6>("h032")) @[ifu_bp_ctl.scala 453:79] - node _T_20485 = bits(_T_20484, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20486 = eq(bht_rd_addr_f, UInt<6>("h033")) @[ifu_bp_ctl.scala 453:79] - node _T_20487 = bits(_T_20486, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20488 = eq(bht_rd_addr_f, UInt<6>("h034")) @[ifu_bp_ctl.scala 453:79] - node _T_20489 = bits(_T_20488, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20490 = eq(bht_rd_addr_f, UInt<6>("h035")) @[ifu_bp_ctl.scala 453:79] - node _T_20491 = bits(_T_20490, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20492 = eq(bht_rd_addr_f, UInt<6>("h036")) @[ifu_bp_ctl.scala 453:79] - node _T_20493 = bits(_T_20492, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20494 = eq(bht_rd_addr_f, UInt<6>("h037")) @[ifu_bp_ctl.scala 453:79] - node _T_20495 = bits(_T_20494, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20496 = eq(bht_rd_addr_f, UInt<6>("h038")) @[ifu_bp_ctl.scala 453:79] - node _T_20497 = bits(_T_20496, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20498 = eq(bht_rd_addr_f, UInt<6>("h039")) @[ifu_bp_ctl.scala 453:79] - node _T_20499 = bits(_T_20498, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20500 = eq(bht_rd_addr_f, UInt<6>("h03a")) @[ifu_bp_ctl.scala 453:79] - node _T_20501 = bits(_T_20500, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20502 = eq(bht_rd_addr_f, UInt<6>("h03b")) @[ifu_bp_ctl.scala 453:79] - node _T_20503 = bits(_T_20502, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20504 = eq(bht_rd_addr_f, UInt<6>("h03c")) @[ifu_bp_ctl.scala 453:79] - node _T_20505 = bits(_T_20504, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20506 = eq(bht_rd_addr_f, UInt<6>("h03d")) @[ifu_bp_ctl.scala 453:79] - node _T_20507 = bits(_T_20506, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20508 = eq(bht_rd_addr_f, UInt<6>("h03e")) @[ifu_bp_ctl.scala 453:79] - node _T_20509 = bits(_T_20508, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20510 = eq(bht_rd_addr_f, UInt<6>("h03f")) @[ifu_bp_ctl.scala 453:79] - node _T_20511 = bits(_T_20510, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20512 = eq(bht_rd_addr_f, UInt<7>("h040")) @[ifu_bp_ctl.scala 453:79] - node _T_20513 = bits(_T_20512, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20514 = eq(bht_rd_addr_f, UInt<7>("h041")) @[ifu_bp_ctl.scala 453:79] - node _T_20515 = bits(_T_20514, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20516 = eq(bht_rd_addr_f, UInt<7>("h042")) @[ifu_bp_ctl.scala 453:79] - node _T_20517 = bits(_T_20516, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20518 = eq(bht_rd_addr_f, UInt<7>("h043")) @[ifu_bp_ctl.scala 453:79] - node _T_20519 = bits(_T_20518, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20520 = eq(bht_rd_addr_f, UInt<7>("h044")) @[ifu_bp_ctl.scala 453:79] - node _T_20521 = bits(_T_20520, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20522 = eq(bht_rd_addr_f, UInt<7>("h045")) @[ifu_bp_ctl.scala 453:79] - node _T_20523 = bits(_T_20522, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20524 = eq(bht_rd_addr_f, UInt<7>("h046")) @[ifu_bp_ctl.scala 453:79] - node _T_20525 = bits(_T_20524, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20526 = eq(bht_rd_addr_f, UInt<7>("h047")) @[ifu_bp_ctl.scala 453:79] - node _T_20527 = bits(_T_20526, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20528 = eq(bht_rd_addr_f, UInt<7>("h048")) @[ifu_bp_ctl.scala 453:79] - node _T_20529 = bits(_T_20528, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20530 = eq(bht_rd_addr_f, UInt<7>("h049")) @[ifu_bp_ctl.scala 453:79] - node _T_20531 = bits(_T_20530, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20532 = eq(bht_rd_addr_f, UInt<7>("h04a")) @[ifu_bp_ctl.scala 453:79] - node _T_20533 = bits(_T_20532, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20534 = eq(bht_rd_addr_f, UInt<7>("h04b")) @[ifu_bp_ctl.scala 453:79] - node _T_20535 = bits(_T_20534, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20536 = eq(bht_rd_addr_f, UInt<7>("h04c")) @[ifu_bp_ctl.scala 453:79] - node _T_20537 = bits(_T_20536, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20538 = eq(bht_rd_addr_f, UInt<7>("h04d")) @[ifu_bp_ctl.scala 453:79] - node _T_20539 = bits(_T_20538, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20540 = eq(bht_rd_addr_f, UInt<7>("h04e")) @[ifu_bp_ctl.scala 453:79] - node _T_20541 = bits(_T_20540, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20542 = eq(bht_rd_addr_f, UInt<7>("h04f")) @[ifu_bp_ctl.scala 453:79] - node _T_20543 = bits(_T_20542, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20544 = eq(bht_rd_addr_f, UInt<7>("h050")) @[ifu_bp_ctl.scala 453:79] - node _T_20545 = bits(_T_20544, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20546 = eq(bht_rd_addr_f, UInt<7>("h051")) @[ifu_bp_ctl.scala 453:79] - node _T_20547 = bits(_T_20546, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20548 = eq(bht_rd_addr_f, UInt<7>("h052")) @[ifu_bp_ctl.scala 453:79] - node _T_20549 = bits(_T_20548, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20550 = eq(bht_rd_addr_f, UInt<7>("h053")) @[ifu_bp_ctl.scala 453:79] - node _T_20551 = bits(_T_20550, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20552 = eq(bht_rd_addr_f, UInt<7>("h054")) @[ifu_bp_ctl.scala 453:79] - node _T_20553 = bits(_T_20552, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20554 = eq(bht_rd_addr_f, UInt<7>("h055")) @[ifu_bp_ctl.scala 453:79] - node _T_20555 = bits(_T_20554, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20556 = eq(bht_rd_addr_f, UInt<7>("h056")) @[ifu_bp_ctl.scala 453:79] - node _T_20557 = bits(_T_20556, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20558 = eq(bht_rd_addr_f, UInt<7>("h057")) @[ifu_bp_ctl.scala 453:79] - node _T_20559 = bits(_T_20558, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20560 = eq(bht_rd_addr_f, UInt<7>("h058")) @[ifu_bp_ctl.scala 453:79] - node _T_20561 = bits(_T_20560, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20562 = eq(bht_rd_addr_f, UInt<7>("h059")) @[ifu_bp_ctl.scala 453:79] - node _T_20563 = bits(_T_20562, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20564 = eq(bht_rd_addr_f, UInt<7>("h05a")) @[ifu_bp_ctl.scala 453:79] - node _T_20565 = bits(_T_20564, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20566 = eq(bht_rd_addr_f, UInt<7>("h05b")) @[ifu_bp_ctl.scala 453:79] - node _T_20567 = bits(_T_20566, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20568 = eq(bht_rd_addr_f, UInt<7>("h05c")) @[ifu_bp_ctl.scala 453:79] - node _T_20569 = bits(_T_20568, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20570 = eq(bht_rd_addr_f, UInt<7>("h05d")) @[ifu_bp_ctl.scala 453:79] - node _T_20571 = bits(_T_20570, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20572 = eq(bht_rd_addr_f, UInt<7>("h05e")) @[ifu_bp_ctl.scala 453:79] - node _T_20573 = bits(_T_20572, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20574 = eq(bht_rd_addr_f, UInt<7>("h05f")) @[ifu_bp_ctl.scala 453:79] - node _T_20575 = bits(_T_20574, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20576 = eq(bht_rd_addr_f, UInt<7>("h060")) @[ifu_bp_ctl.scala 453:79] - node _T_20577 = bits(_T_20576, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20578 = eq(bht_rd_addr_f, UInt<7>("h061")) @[ifu_bp_ctl.scala 453:79] - node _T_20579 = bits(_T_20578, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20580 = eq(bht_rd_addr_f, UInt<7>("h062")) @[ifu_bp_ctl.scala 453:79] - node _T_20581 = bits(_T_20580, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20582 = eq(bht_rd_addr_f, UInt<7>("h063")) @[ifu_bp_ctl.scala 453:79] - node _T_20583 = bits(_T_20582, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20584 = eq(bht_rd_addr_f, UInt<7>("h064")) @[ifu_bp_ctl.scala 453:79] - node _T_20585 = bits(_T_20584, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20586 = eq(bht_rd_addr_f, UInt<7>("h065")) @[ifu_bp_ctl.scala 453:79] - node _T_20587 = bits(_T_20586, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20588 = eq(bht_rd_addr_f, UInt<7>("h066")) @[ifu_bp_ctl.scala 453:79] - node _T_20589 = bits(_T_20588, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20590 = eq(bht_rd_addr_f, UInt<7>("h067")) @[ifu_bp_ctl.scala 453:79] - node _T_20591 = bits(_T_20590, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20592 = eq(bht_rd_addr_f, UInt<7>("h068")) @[ifu_bp_ctl.scala 453:79] - node _T_20593 = bits(_T_20592, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20594 = eq(bht_rd_addr_f, UInt<7>("h069")) @[ifu_bp_ctl.scala 453:79] - node _T_20595 = bits(_T_20594, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20596 = eq(bht_rd_addr_f, UInt<7>("h06a")) @[ifu_bp_ctl.scala 453:79] - node _T_20597 = bits(_T_20596, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20598 = eq(bht_rd_addr_f, UInt<7>("h06b")) @[ifu_bp_ctl.scala 453:79] - node _T_20599 = bits(_T_20598, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20600 = eq(bht_rd_addr_f, UInt<7>("h06c")) @[ifu_bp_ctl.scala 453:79] - node _T_20601 = bits(_T_20600, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20602 = eq(bht_rd_addr_f, UInt<7>("h06d")) @[ifu_bp_ctl.scala 453:79] - node _T_20603 = bits(_T_20602, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20604 = eq(bht_rd_addr_f, UInt<7>("h06e")) @[ifu_bp_ctl.scala 453:79] - node _T_20605 = bits(_T_20604, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20606 = eq(bht_rd_addr_f, UInt<7>("h06f")) @[ifu_bp_ctl.scala 453:79] - node _T_20607 = bits(_T_20606, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20608 = eq(bht_rd_addr_f, UInt<7>("h070")) @[ifu_bp_ctl.scala 453:79] - node _T_20609 = bits(_T_20608, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20610 = eq(bht_rd_addr_f, UInt<7>("h071")) @[ifu_bp_ctl.scala 453:79] - node _T_20611 = bits(_T_20610, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20612 = eq(bht_rd_addr_f, UInt<7>("h072")) @[ifu_bp_ctl.scala 453:79] - node _T_20613 = bits(_T_20612, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20614 = eq(bht_rd_addr_f, UInt<7>("h073")) @[ifu_bp_ctl.scala 453:79] - node _T_20615 = bits(_T_20614, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20616 = eq(bht_rd_addr_f, UInt<7>("h074")) @[ifu_bp_ctl.scala 453:79] - node _T_20617 = bits(_T_20616, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20618 = eq(bht_rd_addr_f, UInt<7>("h075")) @[ifu_bp_ctl.scala 453:79] - node _T_20619 = bits(_T_20618, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20620 = eq(bht_rd_addr_f, UInt<7>("h076")) @[ifu_bp_ctl.scala 453:79] - node _T_20621 = bits(_T_20620, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20622 = eq(bht_rd_addr_f, UInt<7>("h077")) @[ifu_bp_ctl.scala 453:79] - node _T_20623 = bits(_T_20622, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20624 = eq(bht_rd_addr_f, UInt<7>("h078")) @[ifu_bp_ctl.scala 453:79] - node _T_20625 = bits(_T_20624, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20626 = eq(bht_rd_addr_f, UInt<7>("h079")) @[ifu_bp_ctl.scala 453:79] - node _T_20627 = bits(_T_20626, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20628 = eq(bht_rd_addr_f, UInt<7>("h07a")) @[ifu_bp_ctl.scala 453:79] - node _T_20629 = bits(_T_20628, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20630 = eq(bht_rd_addr_f, UInt<7>("h07b")) @[ifu_bp_ctl.scala 453:79] - node _T_20631 = bits(_T_20630, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20632 = eq(bht_rd_addr_f, UInt<7>("h07c")) @[ifu_bp_ctl.scala 453:79] - node _T_20633 = bits(_T_20632, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20634 = eq(bht_rd_addr_f, UInt<7>("h07d")) @[ifu_bp_ctl.scala 453:79] - node _T_20635 = bits(_T_20634, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20636 = eq(bht_rd_addr_f, UInt<7>("h07e")) @[ifu_bp_ctl.scala 453:79] - node _T_20637 = bits(_T_20636, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20638 = eq(bht_rd_addr_f, UInt<7>("h07f")) @[ifu_bp_ctl.scala 453:79] - node _T_20639 = bits(_T_20638, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20640 = eq(bht_rd_addr_f, UInt<8>("h080")) @[ifu_bp_ctl.scala 453:79] - node _T_20641 = bits(_T_20640, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20642 = eq(bht_rd_addr_f, UInt<8>("h081")) @[ifu_bp_ctl.scala 453:79] - node _T_20643 = bits(_T_20642, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20644 = eq(bht_rd_addr_f, UInt<8>("h082")) @[ifu_bp_ctl.scala 453:79] - node _T_20645 = bits(_T_20644, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20646 = eq(bht_rd_addr_f, UInt<8>("h083")) @[ifu_bp_ctl.scala 453:79] - node _T_20647 = bits(_T_20646, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20648 = eq(bht_rd_addr_f, UInt<8>("h084")) @[ifu_bp_ctl.scala 453:79] - node _T_20649 = bits(_T_20648, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20650 = eq(bht_rd_addr_f, UInt<8>("h085")) @[ifu_bp_ctl.scala 453:79] - node _T_20651 = bits(_T_20650, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20652 = eq(bht_rd_addr_f, UInt<8>("h086")) @[ifu_bp_ctl.scala 453:79] - node _T_20653 = bits(_T_20652, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20654 = eq(bht_rd_addr_f, UInt<8>("h087")) @[ifu_bp_ctl.scala 453:79] - node _T_20655 = bits(_T_20654, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20656 = eq(bht_rd_addr_f, UInt<8>("h088")) @[ifu_bp_ctl.scala 453:79] - node _T_20657 = bits(_T_20656, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20658 = eq(bht_rd_addr_f, UInt<8>("h089")) @[ifu_bp_ctl.scala 453:79] - node _T_20659 = bits(_T_20658, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20660 = eq(bht_rd_addr_f, UInt<8>("h08a")) @[ifu_bp_ctl.scala 453:79] - node _T_20661 = bits(_T_20660, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20662 = eq(bht_rd_addr_f, UInt<8>("h08b")) @[ifu_bp_ctl.scala 453:79] - node _T_20663 = bits(_T_20662, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20664 = eq(bht_rd_addr_f, UInt<8>("h08c")) @[ifu_bp_ctl.scala 453:79] - node _T_20665 = bits(_T_20664, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20666 = eq(bht_rd_addr_f, UInt<8>("h08d")) @[ifu_bp_ctl.scala 453:79] - node _T_20667 = bits(_T_20666, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20668 = eq(bht_rd_addr_f, UInt<8>("h08e")) @[ifu_bp_ctl.scala 453:79] - node _T_20669 = bits(_T_20668, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20670 = eq(bht_rd_addr_f, UInt<8>("h08f")) @[ifu_bp_ctl.scala 453:79] - node _T_20671 = bits(_T_20670, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20672 = eq(bht_rd_addr_f, UInt<8>("h090")) @[ifu_bp_ctl.scala 453:79] - node _T_20673 = bits(_T_20672, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20674 = eq(bht_rd_addr_f, UInt<8>("h091")) @[ifu_bp_ctl.scala 453:79] - node _T_20675 = bits(_T_20674, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20676 = eq(bht_rd_addr_f, UInt<8>("h092")) @[ifu_bp_ctl.scala 453:79] - node _T_20677 = bits(_T_20676, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20678 = eq(bht_rd_addr_f, UInt<8>("h093")) @[ifu_bp_ctl.scala 453:79] - node _T_20679 = bits(_T_20678, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20680 = eq(bht_rd_addr_f, UInt<8>("h094")) @[ifu_bp_ctl.scala 453:79] - node _T_20681 = bits(_T_20680, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20682 = eq(bht_rd_addr_f, UInt<8>("h095")) @[ifu_bp_ctl.scala 453:79] - node _T_20683 = bits(_T_20682, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20684 = eq(bht_rd_addr_f, UInt<8>("h096")) @[ifu_bp_ctl.scala 453:79] - node _T_20685 = bits(_T_20684, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20686 = eq(bht_rd_addr_f, UInt<8>("h097")) @[ifu_bp_ctl.scala 453:79] - node _T_20687 = bits(_T_20686, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20688 = eq(bht_rd_addr_f, UInt<8>("h098")) @[ifu_bp_ctl.scala 453:79] - node _T_20689 = bits(_T_20688, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20690 = eq(bht_rd_addr_f, UInt<8>("h099")) @[ifu_bp_ctl.scala 453:79] - node _T_20691 = bits(_T_20690, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20692 = eq(bht_rd_addr_f, UInt<8>("h09a")) @[ifu_bp_ctl.scala 453:79] - node _T_20693 = bits(_T_20692, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20694 = eq(bht_rd_addr_f, UInt<8>("h09b")) @[ifu_bp_ctl.scala 453:79] - node _T_20695 = bits(_T_20694, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20696 = eq(bht_rd_addr_f, UInt<8>("h09c")) @[ifu_bp_ctl.scala 453:79] - node _T_20697 = bits(_T_20696, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20698 = eq(bht_rd_addr_f, UInt<8>("h09d")) @[ifu_bp_ctl.scala 453:79] - node _T_20699 = bits(_T_20698, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20700 = eq(bht_rd_addr_f, UInt<8>("h09e")) @[ifu_bp_ctl.scala 453:79] - node _T_20701 = bits(_T_20700, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20702 = eq(bht_rd_addr_f, UInt<8>("h09f")) @[ifu_bp_ctl.scala 453:79] - node _T_20703 = bits(_T_20702, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20704 = eq(bht_rd_addr_f, UInt<8>("h0a0")) @[ifu_bp_ctl.scala 453:79] - node _T_20705 = bits(_T_20704, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20706 = eq(bht_rd_addr_f, UInt<8>("h0a1")) @[ifu_bp_ctl.scala 453:79] - node _T_20707 = bits(_T_20706, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20708 = eq(bht_rd_addr_f, UInt<8>("h0a2")) @[ifu_bp_ctl.scala 453:79] - node _T_20709 = bits(_T_20708, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20710 = eq(bht_rd_addr_f, UInt<8>("h0a3")) @[ifu_bp_ctl.scala 453:79] - node _T_20711 = bits(_T_20710, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20712 = eq(bht_rd_addr_f, UInt<8>("h0a4")) @[ifu_bp_ctl.scala 453:79] - node _T_20713 = bits(_T_20712, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20714 = eq(bht_rd_addr_f, UInt<8>("h0a5")) @[ifu_bp_ctl.scala 453:79] - node _T_20715 = bits(_T_20714, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20716 = eq(bht_rd_addr_f, UInt<8>("h0a6")) @[ifu_bp_ctl.scala 453:79] - node _T_20717 = bits(_T_20716, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20718 = eq(bht_rd_addr_f, UInt<8>("h0a7")) @[ifu_bp_ctl.scala 453:79] - node _T_20719 = bits(_T_20718, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20720 = eq(bht_rd_addr_f, UInt<8>("h0a8")) @[ifu_bp_ctl.scala 453:79] - node _T_20721 = bits(_T_20720, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20722 = eq(bht_rd_addr_f, UInt<8>("h0a9")) @[ifu_bp_ctl.scala 453:79] - node _T_20723 = bits(_T_20722, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20724 = eq(bht_rd_addr_f, UInt<8>("h0aa")) @[ifu_bp_ctl.scala 453:79] - node _T_20725 = bits(_T_20724, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20726 = eq(bht_rd_addr_f, UInt<8>("h0ab")) @[ifu_bp_ctl.scala 453:79] - node _T_20727 = bits(_T_20726, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20728 = eq(bht_rd_addr_f, UInt<8>("h0ac")) @[ifu_bp_ctl.scala 453:79] - node _T_20729 = bits(_T_20728, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20730 = eq(bht_rd_addr_f, UInt<8>("h0ad")) @[ifu_bp_ctl.scala 453:79] - node _T_20731 = bits(_T_20730, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20732 = eq(bht_rd_addr_f, UInt<8>("h0ae")) @[ifu_bp_ctl.scala 453:79] - node _T_20733 = bits(_T_20732, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20734 = eq(bht_rd_addr_f, UInt<8>("h0af")) @[ifu_bp_ctl.scala 453:79] - node _T_20735 = bits(_T_20734, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20736 = eq(bht_rd_addr_f, UInt<8>("h0b0")) @[ifu_bp_ctl.scala 453:79] - node _T_20737 = bits(_T_20736, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20738 = eq(bht_rd_addr_f, UInt<8>("h0b1")) @[ifu_bp_ctl.scala 453:79] - node _T_20739 = bits(_T_20738, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20740 = eq(bht_rd_addr_f, UInt<8>("h0b2")) @[ifu_bp_ctl.scala 453:79] - node _T_20741 = bits(_T_20740, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20742 = eq(bht_rd_addr_f, UInt<8>("h0b3")) @[ifu_bp_ctl.scala 453:79] - node _T_20743 = bits(_T_20742, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20744 = eq(bht_rd_addr_f, UInt<8>("h0b4")) @[ifu_bp_ctl.scala 453:79] - node _T_20745 = bits(_T_20744, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20746 = eq(bht_rd_addr_f, UInt<8>("h0b5")) @[ifu_bp_ctl.scala 453:79] - node _T_20747 = bits(_T_20746, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20748 = eq(bht_rd_addr_f, UInt<8>("h0b6")) @[ifu_bp_ctl.scala 453:79] - node _T_20749 = bits(_T_20748, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20750 = eq(bht_rd_addr_f, UInt<8>("h0b7")) @[ifu_bp_ctl.scala 453:79] - node _T_20751 = bits(_T_20750, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20752 = eq(bht_rd_addr_f, UInt<8>("h0b8")) @[ifu_bp_ctl.scala 453:79] - node _T_20753 = bits(_T_20752, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20754 = eq(bht_rd_addr_f, UInt<8>("h0b9")) @[ifu_bp_ctl.scala 453:79] - node _T_20755 = bits(_T_20754, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20756 = eq(bht_rd_addr_f, UInt<8>("h0ba")) @[ifu_bp_ctl.scala 453:79] - node _T_20757 = bits(_T_20756, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20758 = eq(bht_rd_addr_f, UInt<8>("h0bb")) @[ifu_bp_ctl.scala 453:79] - node _T_20759 = bits(_T_20758, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20760 = eq(bht_rd_addr_f, UInt<8>("h0bc")) @[ifu_bp_ctl.scala 453:79] - node _T_20761 = bits(_T_20760, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20762 = eq(bht_rd_addr_f, UInt<8>("h0bd")) @[ifu_bp_ctl.scala 453:79] - node _T_20763 = bits(_T_20762, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20764 = eq(bht_rd_addr_f, UInt<8>("h0be")) @[ifu_bp_ctl.scala 453:79] - node _T_20765 = bits(_T_20764, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20766 = eq(bht_rd_addr_f, UInt<8>("h0bf")) @[ifu_bp_ctl.scala 453:79] - node _T_20767 = bits(_T_20766, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20768 = eq(bht_rd_addr_f, UInt<8>("h0c0")) @[ifu_bp_ctl.scala 453:79] - node _T_20769 = bits(_T_20768, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20770 = eq(bht_rd_addr_f, UInt<8>("h0c1")) @[ifu_bp_ctl.scala 453:79] - node _T_20771 = bits(_T_20770, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20772 = eq(bht_rd_addr_f, UInt<8>("h0c2")) @[ifu_bp_ctl.scala 453:79] - node _T_20773 = bits(_T_20772, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20774 = eq(bht_rd_addr_f, UInt<8>("h0c3")) @[ifu_bp_ctl.scala 453:79] - node _T_20775 = bits(_T_20774, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20776 = eq(bht_rd_addr_f, UInt<8>("h0c4")) @[ifu_bp_ctl.scala 453:79] - node _T_20777 = bits(_T_20776, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20778 = eq(bht_rd_addr_f, UInt<8>("h0c5")) @[ifu_bp_ctl.scala 453:79] - node _T_20779 = bits(_T_20778, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20780 = eq(bht_rd_addr_f, UInt<8>("h0c6")) @[ifu_bp_ctl.scala 453:79] - node _T_20781 = bits(_T_20780, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20782 = eq(bht_rd_addr_f, UInt<8>("h0c7")) @[ifu_bp_ctl.scala 453:79] - node _T_20783 = bits(_T_20782, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20784 = eq(bht_rd_addr_f, UInt<8>("h0c8")) @[ifu_bp_ctl.scala 453:79] - node _T_20785 = bits(_T_20784, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20786 = eq(bht_rd_addr_f, UInt<8>("h0c9")) @[ifu_bp_ctl.scala 453:79] - node _T_20787 = bits(_T_20786, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20788 = eq(bht_rd_addr_f, UInt<8>("h0ca")) @[ifu_bp_ctl.scala 453:79] - node _T_20789 = bits(_T_20788, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20790 = eq(bht_rd_addr_f, UInt<8>("h0cb")) @[ifu_bp_ctl.scala 453:79] - node _T_20791 = bits(_T_20790, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20792 = eq(bht_rd_addr_f, UInt<8>("h0cc")) @[ifu_bp_ctl.scala 453:79] - node _T_20793 = bits(_T_20792, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20794 = eq(bht_rd_addr_f, UInt<8>("h0cd")) @[ifu_bp_ctl.scala 453:79] - node _T_20795 = bits(_T_20794, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20796 = eq(bht_rd_addr_f, UInt<8>("h0ce")) @[ifu_bp_ctl.scala 453:79] - node _T_20797 = bits(_T_20796, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20798 = eq(bht_rd_addr_f, UInt<8>("h0cf")) @[ifu_bp_ctl.scala 453:79] - node _T_20799 = bits(_T_20798, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20800 = eq(bht_rd_addr_f, UInt<8>("h0d0")) @[ifu_bp_ctl.scala 453:79] - node _T_20801 = bits(_T_20800, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20802 = eq(bht_rd_addr_f, UInt<8>("h0d1")) @[ifu_bp_ctl.scala 453:79] - node _T_20803 = bits(_T_20802, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20804 = eq(bht_rd_addr_f, UInt<8>("h0d2")) @[ifu_bp_ctl.scala 453:79] - node _T_20805 = bits(_T_20804, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20806 = eq(bht_rd_addr_f, UInt<8>("h0d3")) @[ifu_bp_ctl.scala 453:79] - node _T_20807 = bits(_T_20806, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20808 = eq(bht_rd_addr_f, UInt<8>("h0d4")) @[ifu_bp_ctl.scala 453:79] - node _T_20809 = bits(_T_20808, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20810 = eq(bht_rd_addr_f, UInt<8>("h0d5")) @[ifu_bp_ctl.scala 453:79] - node _T_20811 = bits(_T_20810, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20812 = eq(bht_rd_addr_f, UInt<8>("h0d6")) @[ifu_bp_ctl.scala 453:79] - node _T_20813 = bits(_T_20812, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20814 = eq(bht_rd_addr_f, UInt<8>("h0d7")) @[ifu_bp_ctl.scala 453:79] - node _T_20815 = bits(_T_20814, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20816 = eq(bht_rd_addr_f, UInt<8>("h0d8")) @[ifu_bp_ctl.scala 453:79] - node _T_20817 = bits(_T_20816, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20818 = eq(bht_rd_addr_f, UInt<8>("h0d9")) @[ifu_bp_ctl.scala 453:79] - node _T_20819 = bits(_T_20818, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20820 = eq(bht_rd_addr_f, UInt<8>("h0da")) @[ifu_bp_ctl.scala 453:79] - node _T_20821 = bits(_T_20820, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20822 = eq(bht_rd_addr_f, UInt<8>("h0db")) @[ifu_bp_ctl.scala 453:79] - node _T_20823 = bits(_T_20822, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20824 = eq(bht_rd_addr_f, UInt<8>("h0dc")) @[ifu_bp_ctl.scala 453:79] - node _T_20825 = bits(_T_20824, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20826 = eq(bht_rd_addr_f, UInt<8>("h0dd")) @[ifu_bp_ctl.scala 453:79] - node _T_20827 = bits(_T_20826, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20828 = eq(bht_rd_addr_f, UInt<8>("h0de")) @[ifu_bp_ctl.scala 453:79] - node _T_20829 = bits(_T_20828, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20830 = eq(bht_rd_addr_f, UInt<8>("h0df")) @[ifu_bp_ctl.scala 453:79] - node _T_20831 = bits(_T_20830, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20832 = eq(bht_rd_addr_f, UInt<8>("h0e0")) @[ifu_bp_ctl.scala 453:79] - node _T_20833 = bits(_T_20832, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20834 = eq(bht_rd_addr_f, UInt<8>("h0e1")) @[ifu_bp_ctl.scala 453:79] - node _T_20835 = bits(_T_20834, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20836 = eq(bht_rd_addr_f, UInt<8>("h0e2")) @[ifu_bp_ctl.scala 453:79] - node _T_20837 = bits(_T_20836, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20838 = eq(bht_rd_addr_f, UInt<8>("h0e3")) @[ifu_bp_ctl.scala 453:79] - node _T_20839 = bits(_T_20838, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20840 = eq(bht_rd_addr_f, UInt<8>("h0e4")) @[ifu_bp_ctl.scala 453:79] - node _T_20841 = bits(_T_20840, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20842 = eq(bht_rd_addr_f, UInt<8>("h0e5")) @[ifu_bp_ctl.scala 453:79] - node _T_20843 = bits(_T_20842, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20844 = eq(bht_rd_addr_f, UInt<8>("h0e6")) @[ifu_bp_ctl.scala 453:79] - node _T_20845 = bits(_T_20844, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20846 = eq(bht_rd_addr_f, UInt<8>("h0e7")) @[ifu_bp_ctl.scala 453:79] - node _T_20847 = bits(_T_20846, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20848 = eq(bht_rd_addr_f, UInt<8>("h0e8")) @[ifu_bp_ctl.scala 453:79] - node _T_20849 = bits(_T_20848, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20850 = eq(bht_rd_addr_f, UInt<8>("h0e9")) @[ifu_bp_ctl.scala 453:79] - node _T_20851 = bits(_T_20850, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20852 = eq(bht_rd_addr_f, UInt<8>("h0ea")) @[ifu_bp_ctl.scala 453:79] - node _T_20853 = bits(_T_20852, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20854 = eq(bht_rd_addr_f, UInt<8>("h0eb")) @[ifu_bp_ctl.scala 453:79] - node _T_20855 = bits(_T_20854, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20856 = eq(bht_rd_addr_f, UInt<8>("h0ec")) @[ifu_bp_ctl.scala 453:79] - node _T_20857 = bits(_T_20856, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20858 = eq(bht_rd_addr_f, UInt<8>("h0ed")) @[ifu_bp_ctl.scala 453:79] - node _T_20859 = bits(_T_20858, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20860 = eq(bht_rd_addr_f, UInt<8>("h0ee")) @[ifu_bp_ctl.scala 453:79] - node _T_20861 = bits(_T_20860, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20862 = eq(bht_rd_addr_f, UInt<8>("h0ef")) @[ifu_bp_ctl.scala 453:79] - node _T_20863 = bits(_T_20862, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20864 = eq(bht_rd_addr_f, UInt<8>("h0f0")) @[ifu_bp_ctl.scala 453:79] - node _T_20865 = bits(_T_20864, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20866 = eq(bht_rd_addr_f, UInt<8>("h0f1")) @[ifu_bp_ctl.scala 453:79] - node _T_20867 = bits(_T_20866, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20868 = eq(bht_rd_addr_f, UInt<8>("h0f2")) @[ifu_bp_ctl.scala 453:79] - node _T_20869 = bits(_T_20868, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20870 = eq(bht_rd_addr_f, UInt<8>("h0f3")) @[ifu_bp_ctl.scala 453:79] - node _T_20871 = bits(_T_20870, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20872 = eq(bht_rd_addr_f, UInt<8>("h0f4")) @[ifu_bp_ctl.scala 453:79] - node _T_20873 = bits(_T_20872, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20874 = eq(bht_rd_addr_f, UInt<8>("h0f5")) @[ifu_bp_ctl.scala 453:79] - node _T_20875 = bits(_T_20874, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20876 = eq(bht_rd_addr_f, UInt<8>("h0f6")) @[ifu_bp_ctl.scala 453:79] - node _T_20877 = bits(_T_20876, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20878 = eq(bht_rd_addr_f, UInt<8>("h0f7")) @[ifu_bp_ctl.scala 453:79] - node _T_20879 = bits(_T_20878, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20880 = eq(bht_rd_addr_f, UInt<8>("h0f8")) @[ifu_bp_ctl.scala 453:79] - node _T_20881 = bits(_T_20880, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20882 = eq(bht_rd_addr_f, UInt<8>("h0f9")) @[ifu_bp_ctl.scala 453:79] - node _T_20883 = bits(_T_20882, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20884 = eq(bht_rd_addr_f, UInt<8>("h0fa")) @[ifu_bp_ctl.scala 453:79] - node _T_20885 = bits(_T_20884, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20886 = eq(bht_rd_addr_f, UInt<8>("h0fb")) @[ifu_bp_ctl.scala 453:79] - node _T_20887 = bits(_T_20886, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20888 = eq(bht_rd_addr_f, UInt<8>("h0fc")) @[ifu_bp_ctl.scala 453:79] - node _T_20889 = bits(_T_20888, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20890 = eq(bht_rd_addr_f, UInt<8>("h0fd")) @[ifu_bp_ctl.scala 453:79] - node _T_20891 = bits(_T_20890, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20892 = eq(bht_rd_addr_f, UInt<8>("h0fe")) @[ifu_bp_ctl.scala 453:79] - node _T_20893 = bits(_T_20892, 0, 0) @[ifu_bp_ctl.scala 453:87] - node _T_20894 = eq(bht_rd_addr_f, UInt<8>("h0ff")) @[ifu_bp_ctl.scala 453:79] - node _T_20895 = bits(_T_20894, 0, 0) @[ifu_bp_ctl.scala 453:87] + bht_bank_rd_data_out[1][255] <= _T_20383 @[ifu_bp_ctl.scala 450:39] + node _T_20384 = eq(bht_rd_addr_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 454:79] + node _T_20385 = bits(_T_20384, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20386 = eq(bht_rd_addr_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 454:79] + node _T_20387 = bits(_T_20386, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20388 = eq(bht_rd_addr_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 454:79] + node _T_20389 = bits(_T_20388, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20390 = eq(bht_rd_addr_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 454:79] + node _T_20391 = bits(_T_20390, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20392 = eq(bht_rd_addr_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 454:79] + node _T_20393 = bits(_T_20392, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20394 = eq(bht_rd_addr_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 454:79] + node _T_20395 = bits(_T_20394, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20396 = eq(bht_rd_addr_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 454:79] + node _T_20397 = bits(_T_20396, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20398 = eq(bht_rd_addr_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 454:79] + node _T_20399 = bits(_T_20398, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20400 = eq(bht_rd_addr_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 454:79] + node _T_20401 = bits(_T_20400, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20402 = eq(bht_rd_addr_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 454:79] + node _T_20403 = bits(_T_20402, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20404 = eq(bht_rd_addr_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 454:79] + node _T_20405 = bits(_T_20404, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20406 = eq(bht_rd_addr_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 454:79] + node _T_20407 = bits(_T_20406, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20408 = eq(bht_rd_addr_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 454:79] + node _T_20409 = bits(_T_20408, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20410 = eq(bht_rd_addr_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 454:79] + node _T_20411 = bits(_T_20410, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20412 = eq(bht_rd_addr_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 454:79] + node _T_20413 = bits(_T_20412, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20414 = eq(bht_rd_addr_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 454:79] + node _T_20415 = bits(_T_20414, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20416 = eq(bht_rd_addr_f, UInt<5>("h010")) @[ifu_bp_ctl.scala 454:79] + node _T_20417 = bits(_T_20416, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20418 = eq(bht_rd_addr_f, UInt<5>("h011")) @[ifu_bp_ctl.scala 454:79] + node _T_20419 = bits(_T_20418, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20420 = eq(bht_rd_addr_f, UInt<5>("h012")) @[ifu_bp_ctl.scala 454:79] + node _T_20421 = bits(_T_20420, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20422 = eq(bht_rd_addr_f, UInt<5>("h013")) @[ifu_bp_ctl.scala 454:79] + node _T_20423 = bits(_T_20422, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20424 = eq(bht_rd_addr_f, UInt<5>("h014")) @[ifu_bp_ctl.scala 454:79] + node _T_20425 = bits(_T_20424, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20426 = eq(bht_rd_addr_f, UInt<5>("h015")) @[ifu_bp_ctl.scala 454:79] + node _T_20427 = bits(_T_20426, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20428 = eq(bht_rd_addr_f, UInt<5>("h016")) @[ifu_bp_ctl.scala 454:79] + node _T_20429 = bits(_T_20428, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20430 = eq(bht_rd_addr_f, UInt<5>("h017")) @[ifu_bp_ctl.scala 454:79] + node _T_20431 = bits(_T_20430, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20432 = eq(bht_rd_addr_f, UInt<5>("h018")) @[ifu_bp_ctl.scala 454:79] + node _T_20433 = bits(_T_20432, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20434 = eq(bht_rd_addr_f, UInt<5>("h019")) @[ifu_bp_ctl.scala 454:79] + node _T_20435 = bits(_T_20434, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20436 = eq(bht_rd_addr_f, UInt<5>("h01a")) @[ifu_bp_ctl.scala 454:79] + node _T_20437 = bits(_T_20436, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20438 = eq(bht_rd_addr_f, UInt<5>("h01b")) @[ifu_bp_ctl.scala 454:79] + node _T_20439 = bits(_T_20438, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20440 = eq(bht_rd_addr_f, UInt<5>("h01c")) @[ifu_bp_ctl.scala 454:79] + node _T_20441 = bits(_T_20440, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20442 = eq(bht_rd_addr_f, UInt<5>("h01d")) @[ifu_bp_ctl.scala 454:79] + node _T_20443 = bits(_T_20442, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20444 = eq(bht_rd_addr_f, UInt<5>("h01e")) @[ifu_bp_ctl.scala 454:79] + node _T_20445 = bits(_T_20444, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20446 = eq(bht_rd_addr_f, UInt<5>("h01f")) @[ifu_bp_ctl.scala 454:79] + node _T_20447 = bits(_T_20446, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20448 = eq(bht_rd_addr_f, UInt<6>("h020")) @[ifu_bp_ctl.scala 454:79] + node _T_20449 = bits(_T_20448, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20450 = eq(bht_rd_addr_f, UInt<6>("h021")) @[ifu_bp_ctl.scala 454:79] + node _T_20451 = bits(_T_20450, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20452 = eq(bht_rd_addr_f, UInt<6>("h022")) @[ifu_bp_ctl.scala 454:79] + node _T_20453 = bits(_T_20452, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20454 = eq(bht_rd_addr_f, UInt<6>("h023")) @[ifu_bp_ctl.scala 454:79] + node _T_20455 = bits(_T_20454, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20456 = eq(bht_rd_addr_f, UInt<6>("h024")) @[ifu_bp_ctl.scala 454:79] + node _T_20457 = bits(_T_20456, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20458 = eq(bht_rd_addr_f, UInt<6>("h025")) @[ifu_bp_ctl.scala 454:79] + node _T_20459 = bits(_T_20458, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20460 = eq(bht_rd_addr_f, UInt<6>("h026")) @[ifu_bp_ctl.scala 454:79] + node _T_20461 = bits(_T_20460, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20462 = eq(bht_rd_addr_f, UInt<6>("h027")) @[ifu_bp_ctl.scala 454:79] + node _T_20463 = bits(_T_20462, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20464 = eq(bht_rd_addr_f, UInt<6>("h028")) @[ifu_bp_ctl.scala 454:79] + node _T_20465 = bits(_T_20464, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20466 = eq(bht_rd_addr_f, UInt<6>("h029")) @[ifu_bp_ctl.scala 454:79] + node _T_20467 = bits(_T_20466, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20468 = eq(bht_rd_addr_f, UInt<6>("h02a")) @[ifu_bp_ctl.scala 454:79] + node _T_20469 = bits(_T_20468, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20470 = eq(bht_rd_addr_f, UInt<6>("h02b")) @[ifu_bp_ctl.scala 454:79] + node _T_20471 = bits(_T_20470, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20472 = eq(bht_rd_addr_f, UInt<6>("h02c")) @[ifu_bp_ctl.scala 454:79] + node _T_20473 = bits(_T_20472, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20474 = eq(bht_rd_addr_f, UInt<6>("h02d")) @[ifu_bp_ctl.scala 454:79] + node _T_20475 = bits(_T_20474, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20476 = eq(bht_rd_addr_f, UInt<6>("h02e")) @[ifu_bp_ctl.scala 454:79] + node _T_20477 = bits(_T_20476, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20478 = eq(bht_rd_addr_f, UInt<6>("h02f")) @[ifu_bp_ctl.scala 454:79] + node _T_20479 = bits(_T_20478, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20480 = eq(bht_rd_addr_f, UInt<6>("h030")) @[ifu_bp_ctl.scala 454:79] + node _T_20481 = bits(_T_20480, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20482 = eq(bht_rd_addr_f, UInt<6>("h031")) @[ifu_bp_ctl.scala 454:79] + node _T_20483 = bits(_T_20482, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20484 = eq(bht_rd_addr_f, UInt<6>("h032")) @[ifu_bp_ctl.scala 454:79] + node _T_20485 = bits(_T_20484, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20486 = eq(bht_rd_addr_f, UInt<6>("h033")) @[ifu_bp_ctl.scala 454:79] + node _T_20487 = bits(_T_20486, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20488 = eq(bht_rd_addr_f, UInt<6>("h034")) @[ifu_bp_ctl.scala 454:79] + node _T_20489 = bits(_T_20488, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20490 = eq(bht_rd_addr_f, UInt<6>("h035")) @[ifu_bp_ctl.scala 454:79] + node _T_20491 = bits(_T_20490, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20492 = eq(bht_rd_addr_f, UInt<6>("h036")) @[ifu_bp_ctl.scala 454:79] + node _T_20493 = bits(_T_20492, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20494 = eq(bht_rd_addr_f, UInt<6>("h037")) @[ifu_bp_ctl.scala 454:79] + node _T_20495 = bits(_T_20494, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20496 = eq(bht_rd_addr_f, UInt<6>("h038")) @[ifu_bp_ctl.scala 454:79] + node _T_20497 = bits(_T_20496, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20498 = eq(bht_rd_addr_f, UInt<6>("h039")) @[ifu_bp_ctl.scala 454:79] + node _T_20499 = bits(_T_20498, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20500 = eq(bht_rd_addr_f, UInt<6>("h03a")) @[ifu_bp_ctl.scala 454:79] + node _T_20501 = bits(_T_20500, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20502 = eq(bht_rd_addr_f, UInt<6>("h03b")) @[ifu_bp_ctl.scala 454:79] + node _T_20503 = bits(_T_20502, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20504 = eq(bht_rd_addr_f, UInt<6>("h03c")) @[ifu_bp_ctl.scala 454:79] + node _T_20505 = bits(_T_20504, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20506 = eq(bht_rd_addr_f, UInt<6>("h03d")) @[ifu_bp_ctl.scala 454:79] + node _T_20507 = bits(_T_20506, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20508 = eq(bht_rd_addr_f, UInt<6>("h03e")) @[ifu_bp_ctl.scala 454:79] + node _T_20509 = bits(_T_20508, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20510 = eq(bht_rd_addr_f, UInt<6>("h03f")) @[ifu_bp_ctl.scala 454:79] + node _T_20511 = bits(_T_20510, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20512 = eq(bht_rd_addr_f, UInt<7>("h040")) @[ifu_bp_ctl.scala 454:79] + node _T_20513 = bits(_T_20512, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20514 = eq(bht_rd_addr_f, UInt<7>("h041")) @[ifu_bp_ctl.scala 454:79] + node _T_20515 = bits(_T_20514, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20516 = eq(bht_rd_addr_f, UInt<7>("h042")) @[ifu_bp_ctl.scala 454:79] + node _T_20517 = bits(_T_20516, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20518 = eq(bht_rd_addr_f, UInt<7>("h043")) @[ifu_bp_ctl.scala 454:79] + node _T_20519 = bits(_T_20518, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20520 = eq(bht_rd_addr_f, UInt<7>("h044")) @[ifu_bp_ctl.scala 454:79] + node _T_20521 = bits(_T_20520, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20522 = eq(bht_rd_addr_f, UInt<7>("h045")) @[ifu_bp_ctl.scala 454:79] + node _T_20523 = bits(_T_20522, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20524 = eq(bht_rd_addr_f, UInt<7>("h046")) @[ifu_bp_ctl.scala 454:79] + node _T_20525 = bits(_T_20524, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20526 = eq(bht_rd_addr_f, UInt<7>("h047")) @[ifu_bp_ctl.scala 454:79] + node _T_20527 = bits(_T_20526, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20528 = eq(bht_rd_addr_f, UInt<7>("h048")) @[ifu_bp_ctl.scala 454:79] + node _T_20529 = bits(_T_20528, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20530 = eq(bht_rd_addr_f, UInt<7>("h049")) @[ifu_bp_ctl.scala 454:79] + node _T_20531 = bits(_T_20530, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20532 = eq(bht_rd_addr_f, UInt<7>("h04a")) @[ifu_bp_ctl.scala 454:79] + node _T_20533 = bits(_T_20532, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20534 = eq(bht_rd_addr_f, UInt<7>("h04b")) @[ifu_bp_ctl.scala 454:79] + node _T_20535 = bits(_T_20534, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20536 = eq(bht_rd_addr_f, UInt<7>("h04c")) @[ifu_bp_ctl.scala 454:79] + node _T_20537 = bits(_T_20536, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20538 = eq(bht_rd_addr_f, UInt<7>("h04d")) @[ifu_bp_ctl.scala 454:79] + node _T_20539 = bits(_T_20538, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20540 = eq(bht_rd_addr_f, UInt<7>("h04e")) @[ifu_bp_ctl.scala 454:79] + node _T_20541 = bits(_T_20540, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20542 = eq(bht_rd_addr_f, UInt<7>("h04f")) @[ifu_bp_ctl.scala 454:79] + node _T_20543 = bits(_T_20542, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20544 = eq(bht_rd_addr_f, UInt<7>("h050")) @[ifu_bp_ctl.scala 454:79] + node _T_20545 = bits(_T_20544, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20546 = eq(bht_rd_addr_f, UInt<7>("h051")) @[ifu_bp_ctl.scala 454:79] + node _T_20547 = bits(_T_20546, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20548 = eq(bht_rd_addr_f, UInt<7>("h052")) @[ifu_bp_ctl.scala 454:79] + node _T_20549 = bits(_T_20548, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20550 = eq(bht_rd_addr_f, UInt<7>("h053")) @[ifu_bp_ctl.scala 454:79] + node _T_20551 = bits(_T_20550, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20552 = eq(bht_rd_addr_f, UInt<7>("h054")) @[ifu_bp_ctl.scala 454:79] + node _T_20553 = bits(_T_20552, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20554 = eq(bht_rd_addr_f, UInt<7>("h055")) @[ifu_bp_ctl.scala 454:79] + node _T_20555 = bits(_T_20554, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20556 = eq(bht_rd_addr_f, UInt<7>("h056")) @[ifu_bp_ctl.scala 454:79] + node _T_20557 = bits(_T_20556, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20558 = eq(bht_rd_addr_f, UInt<7>("h057")) @[ifu_bp_ctl.scala 454:79] + node _T_20559 = bits(_T_20558, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20560 = eq(bht_rd_addr_f, UInt<7>("h058")) @[ifu_bp_ctl.scala 454:79] + node _T_20561 = bits(_T_20560, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20562 = eq(bht_rd_addr_f, UInt<7>("h059")) @[ifu_bp_ctl.scala 454:79] + node _T_20563 = bits(_T_20562, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20564 = eq(bht_rd_addr_f, UInt<7>("h05a")) @[ifu_bp_ctl.scala 454:79] + node _T_20565 = bits(_T_20564, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20566 = eq(bht_rd_addr_f, UInt<7>("h05b")) @[ifu_bp_ctl.scala 454:79] + node _T_20567 = bits(_T_20566, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20568 = eq(bht_rd_addr_f, UInt<7>("h05c")) @[ifu_bp_ctl.scala 454:79] + node _T_20569 = bits(_T_20568, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20570 = eq(bht_rd_addr_f, UInt<7>("h05d")) @[ifu_bp_ctl.scala 454:79] + node _T_20571 = bits(_T_20570, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20572 = eq(bht_rd_addr_f, UInt<7>("h05e")) @[ifu_bp_ctl.scala 454:79] + node _T_20573 = bits(_T_20572, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20574 = eq(bht_rd_addr_f, UInt<7>("h05f")) @[ifu_bp_ctl.scala 454:79] + node _T_20575 = bits(_T_20574, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20576 = eq(bht_rd_addr_f, UInt<7>("h060")) @[ifu_bp_ctl.scala 454:79] + node _T_20577 = bits(_T_20576, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20578 = eq(bht_rd_addr_f, UInt<7>("h061")) @[ifu_bp_ctl.scala 454:79] + node _T_20579 = bits(_T_20578, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20580 = eq(bht_rd_addr_f, UInt<7>("h062")) @[ifu_bp_ctl.scala 454:79] + node _T_20581 = bits(_T_20580, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20582 = eq(bht_rd_addr_f, UInt<7>("h063")) @[ifu_bp_ctl.scala 454:79] + node _T_20583 = bits(_T_20582, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20584 = eq(bht_rd_addr_f, UInt<7>("h064")) @[ifu_bp_ctl.scala 454:79] + node _T_20585 = bits(_T_20584, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20586 = eq(bht_rd_addr_f, UInt<7>("h065")) @[ifu_bp_ctl.scala 454:79] + node _T_20587 = bits(_T_20586, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20588 = eq(bht_rd_addr_f, UInt<7>("h066")) @[ifu_bp_ctl.scala 454:79] + node _T_20589 = bits(_T_20588, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20590 = eq(bht_rd_addr_f, UInt<7>("h067")) @[ifu_bp_ctl.scala 454:79] + node _T_20591 = bits(_T_20590, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20592 = eq(bht_rd_addr_f, UInt<7>("h068")) @[ifu_bp_ctl.scala 454:79] + node _T_20593 = bits(_T_20592, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20594 = eq(bht_rd_addr_f, UInt<7>("h069")) @[ifu_bp_ctl.scala 454:79] + node _T_20595 = bits(_T_20594, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20596 = eq(bht_rd_addr_f, UInt<7>("h06a")) @[ifu_bp_ctl.scala 454:79] + node _T_20597 = bits(_T_20596, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20598 = eq(bht_rd_addr_f, UInt<7>("h06b")) @[ifu_bp_ctl.scala 454:79] + node _T_20599 = bits(_T_20598, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20600 = eq(bht_rd_addr_f, UInt<7>("h06c")) @[ifu_bp_ctl.scala 454:79] + node _T_20601 = bits(_T_20600, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20602 = eq(bht_rd_addr_f, UInt<7>("h06d")) @[ifu_bp_ctl.scala 454:79] + node _T_20603 = bits(_T_20602, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20604 = eq(bht_rd_addr_f, UInt<7>("h06e")) @[ifu_bp_ctl.scala 454:79] + node _T_20605 = bits(_T_20604, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20606 = eq(bht_rd_addr_f, UInt<7>("h06f")) @[ifu_bp_ctl.scala 454:79] + node _T_20607 = bits(_T_20606, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20608 = eq(bht_rd_addr_f, UInt<7>("h070")) @[ifu_bp_ctl.scala 454:79] + node _T_20609 = bits(_T_20608, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20610 = eq(bht_rd_addr_f, UInt<7>("h071")) @[ifu_bp_ctl.scala 454:79] + node _T_20611 = bits(_T_20610, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20612 = eq(bht_rd_addr_f, UInt<7>("h072")) @[ifu_bp_ctl.scala 454:79] + node _T_20613 = bits(_T_20612, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20614 = eq(bht_rd_addr_f, UInt<7>("h073")) @[ifu_bp_ctl.scala 454:79] + node _T_20615 = bits(_T_20614, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20616 = eq(bht_rd_addr_f, UInt<7>("h074")) @[ifu_bp_ctl.scala 454:79] + node _T_20617 = bits(_T_20616, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20618 = eq(bht_rd_addr_f, UInt<7>("h075")) @[ifu_bp_ctl.scala 454:79] + node _T_20619 = bits(_T_20618, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20620 = eq(bht_rd_addr_f, UInt<7>("h076")) @[ifu_bp_ctl.scala 454:79] + node _T_20621 = bits(_T_20620, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20622 = eq(bht_rd_addr_f, UInt<7>("h077")) @[ifu_bp_ctl.scala 454:79] + node _T_20623 = bits(_T_20622, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20624 = eq(bht_rd_addr_f, UInt<7>("h078")) @[ifu_bp_ctl.scala 454:79] + node _T_20625 = bits(_T_20624, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20626 = eq(bht_rd_addr_f, UInt<7>("h079")) @[ifu_bp_ctl.scala 454:79] + node _T_20627 = bits(_T_20626, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20628 = eq(bht_rd_addr_f, UInt<7>("h07a")) @[ifu_bp_ctl.scala 454:79] + node _T_20629 = bits(_T_20628, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20630 = eq(bht_rd_addr_f, UInt<7>("h07b")) @[ifu_bp_ctl.scala 454:79] + node _T_20631 = bits(_T_20630, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20632 = eq(bht_rd_addr_f, UInt<7>("h07c")) @[ifu_bp_ctl.scala 454:79] + node _T_20633 = bits(_T_20632, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20634 = eq(bht_rd_addr_f, UInt<7>("h07d")) @[ifu_bp_ctl.scala 454:79] + node _T_20635 = bits(_T_20634, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20636 = eq(bht_rd_addr_f, UInt<7>("h07e")) @[ifu_bp_ctl.scala 454:79] + node _T_20637 = bits(_T_20636, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20638 = eq(bht_rd_addr_f, UInt<7>("h07f")) @[ifu_bp_ctl.scala 454:79] + node _T_20639 = bits(_T_20638, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20640 = eq(bht_rd_addr_f, UInt<8>("h080")) @[ifu_bp_ctl.scala 454:79] + node _T_20641 = bits(_T_20640, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20642 = eq(bht_rd_addr_f, UInt<8>("h081")) @[ifu_bp_ctl.scala 454:79] + node _T_20643 = bits(_T_20642, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20644 = eq(bht_rd_addr_f, UInt<8>("h082")) @[ifu_bp_ctl.scala 454:79] + node _T_20645 = bits(_T_20644, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20646 = eq(bht_rd_addr_f, UInt<8>("h083")) @[ifu_bp_ctl.scala 454:79] + node _T_20647 = bits(_T_20646, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20648 = eq(bht_rd_addr_f, UInt<8>("h084")) @[ifu_bp_ctl.scala 454:79] + node _T_20649 = bits(_T_20648, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20650 = eq(bht_rd_addr_f, UInt<8>("h085")) @[ifu_bp_ctl.scala 454:79] + node _T_20651 = bits(_T_20650, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20652 = eq(bht_rd_addr_f, UInt<8>("h086")) @[ifu_bp_ctl.scala 454:79] + node _T_20653 = bits(_T_20652, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20654 = eq(bht_rd_addr_f, UInt<8>("h087")) @[ifu_bp_ctl.scala 454:79] + node _T_20655 = bits(_T_20654, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20656 = eq(bht_rd_addr_f, UInt<8>("h088")) @[ifu_bp_ctl.scala 454:79] + node _T_20657 = bits(_T_20656, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20658 = eq(bht_rd_addr_f, UInt<8>("h089")) @[ifu_bp_ctl.scala 454:79] + node _T_20659 = bits(_T_20658, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20660 = eq(bht_rd_addr_f, UInt<8>("h08a")) @[ifu_bp_ctl.scala 454:79] + node _T_20661 = bits(_T_20660, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20662 = eq(bht_rd_addr_f, UInt<8>("h08b")) @[ifu_bp_ctl.scala 454:79] + node _T_20663 = bits(_T_20662, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20664 = eq(bht_rd_addr_f, UInt<8>("h08c")) @[ifu_bp_ctl.scala 454:79] + node _T_20665 = bits(_T_20664, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20666 = eq(bht_rd_addr_f, UInt<8>("h08d")) @[ifu_bp_ctl.scala 454:79] + node _T_20667 = bits(_T_20666, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20668 = eq(bht_rd_addr_f, UInt<8>("h08e")) @[ifu_bp_ctl.scala 454:79] + node _T_20669 = bits(_T_20668, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20670 = eq(bht_rd_addr_f, UInt<8>("h08f")) @[ifu_bp_ctl.scala 454:79] + node _T_20671 = bits(_T_20670, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20672 = eq(bht_rd_addr_f, UInt<8>("h090")) @[ifu_bp_ctl.scala 454:79] + node _T_20673 = bits(_T_20672, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20674 = eq(bht_rd_addr_f, UInt<8>("h091")) @[ifu_bp_ctl.scala 454:79] + node _T_20675 = bits(_T_20674, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20676 = eq(bht_rd_addr_f, UInt<8>("h092")) @[ifu_bp_ctl.scala 454:79] + node _T_20677 = bits(_T_20676, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20678 = eq(bht_rd_addr_f, UInt<8>("h093")) @[ifu_bp_ctl.scala 454:79] + node _T_20679 = bits(_T_20678, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20680 = eq(bht_rd_addr_f, UInt<8>("h094")) @[ifu_bp_ctl.scala 454:79] + node _T_20681 = bits(_T_20680, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20682 = eq(bht_rd_addr_f, UInt<8>("h095")) @[ifu_bp_ctl.scala 454:79] + node _T_20683 = bits(_T_20682, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20684 = eq(bht_rd_addr_f, UInt<8>("h096")) @[ifu_bp_ctl.scala 454:79] + node _T_20685 = bits(_T_20684, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20686 = eq(bht_rd_addr_f, UInt<8>("h097")) @[ifu_bp_ctl.scala 454:79] + node _T_20687 = bits(_T_20686, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20688 = eq(bht_rd_addr_f, UInt<8>("h098")) @[ifu_bp_ctl.scala 454:79] + node _T_20689 = bits(_T_20688, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20690 = eq(bht_rd_addr_f, UInt<8>("h099")) @[ifu_bp_ctl.scala 454:79] + node _T_20691 = bits(_T_20690, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20692 = eq(bht_rd_addr_f, UInt<8>("h09a")) @[ifu_bp_ctl.scala 454:79] + node _T_20693 = bits(_T_20692, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20694 = eq(bht_rd_addr_f, UInt<8>("h09b")) @[ifu_bp_ctl.scala 454:79] + node _T_20695 = bits(_T_20694, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20696 = eq(bht_rd_addr_f, UInt<8>("h09c")) @[ifu_bp_ctl.scala 454:79] + node _T_20697 = bits(_T_20696, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20698 = eq(bht_rd_addr_f, UInt<8>("h09d")) @[ifu_bp_ctl.scala 454:79] + node _T_20699 = bits(_T_20698, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20700 = eq(bht_rd_addr_f, UInt<8>("h09e")) @[ifu_bp_ctl.scala 454:79] + node _T_20701 = bits(_T_20700, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20702 = eq(bht_rd_addr_f, UInt<8>("h09f")) @[ifu_bp_ctl.scala 454:79] + node _T_20703 = bits(_T_20702, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20704 = eq(bht_rd_addr_f, UInt<8>("h0a0")) @[ifu_bp_ctl.scala 454:79] + node _T_20705 = bits(_T_20704, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20706 = eq(bht_rd_addr_f, UInt<8>("h0a1")) @[ifu_bp_ctl.scala 454:79] + node _T_20707 = bits(_T_20706, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20708 = eq(bht_rd_addr_f, UInt<8>("h0a2")) @[ifu_bp_ctl.scala 454:79] + node _T_20709 = bits(_T_20708, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20710 = eq(bht_rd_addr_f, UInt<8>("h0a3")) @[ifu_bp_ctl.scala 454:79] + node _T_20711 = bits(_T_20710, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20712 = eq(bht_rd_addr_f, UInt<8>("h0a4")) @[ifu_bp_ctl.scala 454:79] + node _T_20713 = bits(_T_20712, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20714 = eq(bht_rd_addr_f, UInt<8>("h0a5")) @[ifu_bp_ctl.scala 454:79] + node _T_20715 = bits(_T_20714, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20716 = eq(bht_rd_addr_f, UInt<8>("h0a6")) @[ifu_bp_ctl.scala 454:79] + node _T_20717 = bits(_T_20716, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20718 = eq(bht_rd_addr_f, UInt<8>("h0a7")) @[ifu_bp_ctl.scala 454:79] + node _T_20719 = bits(_T_20718, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20720 = eq(bht_rd_addr_f, UInt<8>("h0a8")) @[ifu_bp_ctl.scala 454:79] + node _T_20721 = bits(_T_20720, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20722 = eq(bht_rd_addr_f, UInt<8>("h0a9")) @[ifu_bp_ctl.scala 454:79] + node _T_20723 = bits(_T_20722, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20724 = eq(bht_rd_addr_f, UInt<8>("h0aa")) @[ifu_bp_ctl.scala 454:79] + node _T_20725 = bits(_T_20724, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20726 = eq(bht_rd_addr_f, UInt<8>("h0ab")) @[ifu_bp_ctl.scala 454:79] + node _T_20727 = bits(_T_20726, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20728 = eq(bht_rd_addr_f, UInt<8>("h0ac")) @[ifu_bp_ctl.scala 454:79] + node _T_20729 = bits(_T_20728, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20730 = eq(bht_rd_addr_f, UInt<8>("h0ad")) @[ifu_bp_ctl.scala 454:79] + node _T_20731 = bits(_T_20730, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20732 = eq(bht_rd_addr_f, UInt<8>("h0ae")) @[ifu_bp_ctl.scala 454:79] + node _T_20733 = bits(_T_20732, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20734 = eq(bht_rd_addr_f, UInt<8>("h0af")) @[ifu_bp_ctl.scala 454:79] + node _T_20735 = bits(_T_20734, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20736 = eq(bht_rd_addr_f, UInt<8>("h0b0")) @[ifu_bp_ctl.scala 454:79] + node _T_20737 = bits(_T_20736, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20738 = eq(bht_rd_addr_f, UInt<8>("h0b1")) @[ifu_bp_ctl.scala 454:79] + node _T_20739 = bits(_T_20738, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20740 = eq(bht_rd_addr_f, UInt<8>("h0b2")) @[ifu_bp_ctl.scala 454:79] + node _T_20741 = bits(_T_20740, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20742 = eq(bht_rd_addr_f, UInt<8>("h0b3")) @[ifu_bp_ctl.scala 454:79] + node _T_20743 = bits(_T_20742, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20744 = eq(bht_rd_addr_f, UInt<8>("h0b4")) @[ifu_bp_ctl.scala 454:79] + node _T_20745 = bits(_T_20744, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20746 = eq(bht_rd_addr_f, UInt<8>("h0b5")) @[ifu_bp_ctl.scala 454:79] + node _T_20747 = bits(_T_20746, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20748 = eq(bht_rd_addr_f, UInt<8>("h0b6")) @[ifu_bp_ctl.scala 454:79] + node _T_20749 = bits(_T_20748, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20750 = eq(bht_rd_addr_f, UInt<8>("h0b7")) @[ifu_bp_ctl.scala 454:79] + node _T_20751 = bits(_T_20750, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20752 = eq(bht_rd_addr_f, UInt<8>("h0b8")) @[ifu_bp_ctl.scala 454:79] + node _T_20753 = bits(_T_20752, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20754 = eq(bht_rd_addr_f, UInt<8>("h0b9")) @[ifu_bp_ctl.scala 454:79] + node _T_20755 = bits(_T_20754, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20756 = eq(bht_rd_addr_f, UInt<8>("h0ba")) @[ifu_bp_ctl.scala 454:79] + node _T_20757 = bits(_T_20756, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20758 = eq(bht_rd_addr_f, UInt<8>("h0bb")) @[ifu_bp_ctl.scala 454:79] + node _T_20759 = bits(_T_20758, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20760 = eq(bht_rd_addr_f, UInt<8>("h0bc")) @[ifu_bp_ctl.scala 454:79] + node _T_20761 = bits(_T_20760, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20762 = eq(bht_rd_addr_f, UInt<8>("h0bd")) @[ifu_bp_ctl.scala 454:79] + node _T_20763 = bits(_T_20762, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20764 = eq(bht_rd_addr_f, UInt<8>("h0be")) @[ifu_bp_ctl.scala 454:79] + node _T_20765 = bits(_T_20764, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20766 = eq(bht_rd_addr_f, UInt<8>("h0bf")) @[ifu_bp_ctl.scala 454:79] + node _T_20767 = bits(_T_20766, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20768 = eq(bht_rd_addr_f, UInt<8>("h0c0")) @[ifu_bp_ctl.scala 454:79] + node _T_20769 = bits(_T_20768, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20770 = eq(bht_rd_addr_f, UInt<8>("h0c1")) @[ifu_bp_ctl.scala 454:79] + node _T_20771 = bits(_T_20770, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20772 = eq(bht_rd_addr_f, UInt<8>("h0c2")) @[ifu_bp_ctl.scala 454:79] + node _T_20773 = bits(_T_20772, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20774 = eq(bht_rd_addr_f, UInt<8>("h0c3")) @[ifu_bp_ctl.scala 454:79] + node _T_20775 = bits(_T_20774, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20776 = eq(bht_rd_addr_f, UInt<8>("h0c4")) @[ifu_bp_ctl.scala 454:79] + node _T_20777 = bits(_T_20776, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20778 = eq(bht_rd_addr_f, UInt<8>("h0c5")) @[ifu_bp_ctl.scala 454:79] + node _T_20779 = bits(_T_20778, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20780 = eq(bht_rd_addr_f, UInt<8>("h0c6")) @[ifu_bp_ctl.scala 454:79] + node _T_20781 = bits(_T_20780, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20782 = eq(bht_rd_addr_f, UInt<8>("h0c7")) @[ifu_bp_ctl.scala 454:79] + node _T_20783 = bits(_T_20782, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20784 = eq(bht_rd_addr_f, UInt<8>("h0c8")) @[ifu_bp_ctl.scala 454:79] + node _T_20785 = bits(_T_20784, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20786 = eq(bht_rd_addr_f, UInt<8>("h0c9")) @[ifu_bp_ctl.scala 454:79] + node _T_20787 = bits(_T_20786, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20788 = eq(bht_rd_addr_f, UInt<8>("h0ca")) @[ifu_bp_ctl.scala 454:79] + node _T_20789 = bits(_T_20788, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20790 = eq(bht_rd_addr_f, UInt<8>("h0cb")) @[ifu_bp_ctl.scala 454:79] + node _T_20791 = bits(_T_20790, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20792 = eq(bht_rd_addr_f, UInt<8>("h0cc")) @[ifu_bp_ctl.scala 454:79] + node _T_20793 = bits(_T_20792, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20794 = eq(bht_rd_addr_f, UInt<8>("h0cd")) @[ifu_bp_ctl.scala 454:79] + node _T_20795 = bits(_T_20794, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20796 = eq(bht_rd_addr_f, UInt<8>("h0ce")) @[ifu_bp_ctl.scala 454:79] + node _T_20797 = bits(_T_20796, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20798 = eq(bht_rd_addr_f, UInt<8>("h0cf")) @[ifu_bp_ctl.scala 454:79] + node _T_20799 = bits(_T_20798, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20800 = eq(bht_rd_addr_f, UInt<8>("h0d0")) @[ifu_bp_ctl.scala 454:79] + node _T_20801 = bits(_T_20800, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20802 = eq(bht_rd_addr_f, UInt<8>("h0d1")) @[ifu_bp_ctl.scala 454:79] + node _T_20803 = bits(_T_20802, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20804 = eq(bht_rd_addr_f, UInt<8>("h0d2")) @[ifu_bp_ctl.scala 454:79] + node _T_20805 = bits(_T_20804, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20806 = eq(bht_rd_addr_f, UInt<8>("h0d3")) @[ifu_bp_ctl.scala 454:79] + node _T_20807 = bits(_T_20806, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20808 = eq(bht_rd_addr_f, UInt<8>("h0d4")) @[ifu_bp_ctl.scala 454:79] + node _T_20809 = bits(_T_20808, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20810 = eq(bht_rd_addr_f, UInt<8>("h0d5")) @[ifu_bp_ctl.scala 454:79] + node _T_20811 = bits(_T_20810, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20812 = eq(bht_rd_addr_f, UInt<8>("h0d6")) @[ifu_bp_ctl.scala 454:79] + node _T_20813 = bits(_T_20812, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20814 = eq(bht_rd_addr_f, UInt<8>("h0d7")) @[ifu_bp_ctl.scala 454:79] + node _T_20815 = bits(_T_20814, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20816 = eq(bht_rd_addr_f, UInt<8>("h0d8")) @[ifu_bp_ctl.scala 454:79] + node _T_20817 = bits(_T_20816, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20818 = eq(bht_rd_addr_f, UInt<8>("h0d9")) @[ifu_bp_ctl.scala 454:79] + node _T_20819 = bits(_T_20818, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20820 = eq(bht_rd_addr_f, UInt<8>("h0da")) @[ifu_bp_ctl.scala 454:79] + node _T_20821 = bits(_T_20820, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20822 = eq(bht_rd_addr_f, UInt<8>("h0db")) @[ifu_bp_ctl.scala 454:79] + node _T_20823 = bits(_T_20822, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20824 = eq(bht_rd_addr_f, UInt<8>("h0dc")) @[ifu_bp_ctl.scala 454:79] + node _T_20825 = bits(_T_20824, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20826 = eq(bht_rd_addr_f, UInt<8>("h0dd")) @[ifu_bp_ctl.scala 454:79] + node _T_20827 = bits(_T_20826, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20828 = eq(bht_rd_addr_f, UInt<8>("h0de")) @[ifu_bp_ctl.scala 454:79] + node _T_20829 = bits(_T_20828, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20830 = eq(bht_rd_addr_f, UInt<8>("h0df")) @[ifu_bp_ctl.scala 454:79] + node _T_20831 = bits(_T_20830, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20832 = eq(bht_rd_addr_f, UInt<8>("h0e0")) @[ifu_bp_ctl.scala 454:79] + node _T_20833 = bits(_T_20832, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20834 = eq(bht_rd_addr_f, UInt<8>("h0e1")) @[ifu_bp_ctl.scala 454:79] + node _T_20835 = bits(_T_20834, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20836 = eq(bht_rd_addr_f, UInt<8>("h0e2")) @[ifu_bp_ctl.scala 454:79] + node _T_20837 = bits(_T_20836, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20838 = eq(bht_rd_addr_f, UInt<8>("h0e3")) @[ifu_bp_ctl.scala 454:79] + node _T_20839 = bits(_T_20838, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20840 = eq(bht_rd_addr_f, UInt<8>("h0e4")) @[ifu_bp_ctl.scala 454:79] + node _T_20841 = bits(_T_20840, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20842 = eq(bht_rd_addr_f, UInt<8>("h0e5")) @[ifu_bp_ctl.scala 454:79] + node _T_20843 = bits(_T_20842, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20844 = eq(bht_rd_addr_f, UInt<8>("h0e6")) @[ifu_bp_ctl.scala 454:79] + node _T_20845 = bits(_T_20844, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20846 = eq(bht_rd_addr_f, UInt<8>("h0e7")) @[ifu_bp_ctl.scala 454:79] + node _T_20847 = bits(_T_20846, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20848 = eq(bht_rd_addr_f, UInt<8>("h0e8")) @[ifu_bp_ctl.scala 454:79] + node _T_20849 = bits(_T_20848, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20850 = eq(bht_rd_addr_f, UInt<8>("h0e9")) @[ifu_bp_ctl.scala 454:79] + node _T_20851 = bits(_T_20850, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20852 = eq(bht_rd_addr_f, UInt<8>("h0ea")) @[ifu_bp_ctl.scala 454:79] + node _T_20853 = bits(_T_20852, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20854 = eq(bht_rd_addr_f, UInt<8>("h0eb")) @[ifu_bp_ctl.scala 454:79] + node _T_20855 = bits(_T_20854, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20856 = eq(bht_rd_addr_f, UInt<8>("h0ec")) @[ifu_bp_ctl.scala 454:79] + node _T_20857 = bits(_T_20856, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20858 = eq(bht_rd_addr_f, UInt<8>("h0ed")) @[ifu_bp_ctl.scala 454:79] + node _T_20859 = bits(_T_20858, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20860 = eq(bht_rd_addr_f, UInt<8>("h0ee")) @[ifu_bp_ctl.scala 454:79] + node _T_20861 = bits(_T_20860, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20862 = eq(bht_rd_addr_f, UInt<8>("h0ef")) @[ifu_bp_ctl.scala 454:79] + node _T_20863 = bits(_T_20862, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20864 = eq(bht_rd_addr_f, UInt<8>("h0f0")) @[ifu_bp_ctl.scala 454:79] + node _T_20865 = bits(_T_20864, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20866 = eq(bht_rd_addr_f, UInt<8>("h0f1")) @[ifu_bp_ctl.scala 454:79] + node _T_20867 = bits(_T_20866, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20868 = eq(bht_rd_addr_f, UInt<8>("h0f2")) @[ifu_bp_ctl.scala 454:79] + node _T_20869 = bits(_T_20868, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20870 = eq(bht_rd_addr_f, UInt<8>("h0f3")) @[ifu_bp_ctl.scala 454:79] + node _T_20871 = bits(_T_20870, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20872 = eq(bht_rd_addr_f, UInt<8>("h0f4")) @[ifu_bp_ctl.scala 454:79] + node _T_20873 = bits(_T_20872, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20874 = eq(bht_rd_addr_f, UInt<8>("h0f5")) @[ifu_bp_ctl.scala 454:79] + node _T_20875 = bits(_T_20874, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20876 = eq(bht_rd_addr_f, UInt<8>("h0f6")) @[ifu_bp_ctl.scala 454:79] + node _T_20877 = bits(_T_20876, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20878 = eq(bht_rd_addr_f, UInt<8>("h0f7")) @[ifu_bp_ctl.scala 454:79] + node _T_20879 = bits(_T_20878, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20880 = eq(bht_rd_addr_f, UInt<8>("h0f8")) @[ifu_bp_ctl.scala 454:79] + node _T_20881 = bits(_T_20880, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20882 = eq(bht_rd_addr_f, UInt<8>("h0f9")) @[ifu_bp_ctl.scala 454:79] + node _T_20883 = bits(_T_20882, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20884 = eq(bht_rd_addr_f, UInt<8>("h0fa")) @[ifu_bp_ctl.scala 454:79] + node _T_20885 = bits(_T_20884, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20886 = eq(bht_rd_addr_f, UInt<8>("h0fb")) @[ifu_bp_ctl.scala 454:79] + node _T_20887 = bits(_T_20886, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20888 = eq(bht_rd_addr_f, UInt<8>("h0fc")) @[ifu_bp_ctl.scala 454:79] + node _T_20889 = bits(_T_20888, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20890 = eq(bht_rd_addr_f, UInt<8>("h0fd")) @[ifu_bp_ctl.scala 454:79] + node _T_20891 = bits(_T_20890, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20892 = eq(bht_rd_addr_f, UInt<8>("h0fe")) @[ifu_bp_ctl.scala 454:79] + node _T_20893 = bits(_T_20892, 0, 0) @[ifu_bp_ctl.scala 454:87] + node _T_20894 = eq(bht_rd_addr_f, UInt<8>("h0ff")) @[ifu_bp_ctl.scala 454:79] + node _T_20895 = bits(_T_20894, 0, 0) @[ifu_bp_ctl.scala 454:87] node _T_20896 = mux(_T_20385, bht_bank_rd_data_out[0][0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_20897 = mux(_T_20387, bht_bank_rd_data_out[0][1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_20898 = mux(_T_20389, bht_bank_rd_data_out[0][2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -58198,519 +58198,519 @@ circuit quasar_wrapper : node _T_21406 = or(_T_21405, _T_21151) @[Mux.scala 27:72] wire _T_21407 : UInt<2> @[Mux.scala 27:72] _T_21407 <= _T_21406 @[Mux.scala 27:72] - bht_bank0_rd_data_f <= _T_21407 @[ifu_bp_ctl.scala 453:23] - node _T_21408 = eq(bht_rd_addr_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 454:79] - node _T_21409 = bits(_T_21408, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21410 = eq(bht_rd_addr_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 454:79] - node _T_21411 = bits(_T_21410, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21412 = eq(bht_rd_addr_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 454:79] - node _T_21413 = bits(_T_21412, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21414 = eq(bht_rd_addr_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 454:79] - node _T_21415 = bits(_T_21414, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21416 = eq(bht_rd_addr_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 454:79] - node _T_21417 = bits(_T_21416, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21418 = eq(bht_rd_addr_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 454:79] - node _T_21419 = bits(_T_21418, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21420 = eq(bht_rd_addr_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 454:79] - node _T_21421 = bits(_T_21420, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21422 = eq(bht_rd_addr_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 454:79] - node _T_21423 = bits(_T_21422, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21424 = eq(bht_rd_addr_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 454:79] - node _T_21425 = bits(_T_21424, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21426 = eq(bht_rd_addr_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 454:79] - node _T_21427 = bits(_T_21426, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21428 = eq(bht_rd_addr_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 454:79] - node _T_21429 = bits(_T_21428, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21430 = eq(bht_rd_addr_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 454:79] - node _T_21431 = bits(_T_21430, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21432 = eq(bht_rd_addr_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 454:79] - node _T_21433 = bits(_T_21432, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21434 = eq(bht_rd_addr_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 454:79] - node _T_21435 = bits(_T_21434, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21436 = eq(bht_rd_addr_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 454:79] - node _T_21437 = bits(_T_21436, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21438 = eq(bht_rd_addr_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 454:79] - node _T_21439 = bits(_T_21438, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21440 = eq(bht_rd_addr_f, UInt<5>("h010")) @[ifu_bp_ctl.scala 454:79] - node _T_21441 = bits(_T_21440, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21442 = eq(bht_rd_addr_f, UInt<5>("h011")) @[ifu_bp_ctl.scala 454:79] - node _T_21443 = bits(_T_21442, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21444 = eq(bht_rd_addr_f, UInt<5>("h012")) @[ifu_bp_ctl.scala 454:79] - node _T_21445 = bits(_T_21444, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21446 = eq(bht_rd_addr_f, UInt<5>("h013")) @[ifu_bp_ctl.scala 454:79] - node _T_21447 = bits(_T_21446, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21448 = eq(bht_rd_addr_f, UInt<5>("h014")) @[ifu_bp_ctl.scala 454:79] - node _T_21449 = bits(_T_21448, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21450 = eq(bht_rd_addr_f, UInt<5>("h015")) @[ifu_bp_ctl.scala 454:79] - node _T_21451 = bits(_T_21450, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21452 = eq(bht_rd_addr_f, UInt<5>("h016")) @[ifu_bp_ctl.scala 454:79] - node _T_21453 = bits(_T_21452, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21454 = eq(bht_rd_addr_f, UInt<5>("h017")) @[ifu_bp_ctl.scala 454:79] - node _T_21455 = bits(_T_21454, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21456 = eq(bht_rd_addr_f, UInt<5>("h018")) @[ifu_bp_ctl.scala 454:79] - node _T_21457 = bits(_T_21456, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21458 = eq(bht_rd_addr_f, UInt<5>("h019")) @[ifu_bp_ctl.scala 454:79] - node _T_21459 = bits(_T_21458, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21460 = eq(bht_rd_addr_f, UInt<5>("h01a")) @[ifu_bp_ctl.scala 454:79] - node _T_21461 = bits(_T_21460, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21462 = eq(bht_rd_addr_f, UInt<5>("h01b")) @[ifu_bp_ctl.scala 454:79] - node _T_21463 = bits(_T_21462, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21464 = eq(bht_rd_addr_f, UInt<5>("h01c")) @[ifu_bp_ctl.scala 454:79] - node _T_21465 = bits(_T_21464, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21466 = eq(bht_rd_addr_f, UInt<5>("h01d")) @[ifu_bp_ctl.scala 454:79] - node _T_21467 = bits(_T_21466, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21468 = eq(bht_rd_addr_f, UInt<5>("h01e")) @[ifu_bp_ctl.scala 454:79] - node _T_21469 = bits(_T_21468, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21470 = eq(bht_rd_addr_f, UInt<5>("h01f")) @[ifu_bp_ctl.scala 454:79] - node _T_21471 = bits(_T_21470, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21472 = eq(bht_rd_addr_f, UInt<6>("h020")) @[ifu_bp_ctl.scala 454:79] - node _T_21473 = bits(_T_21472, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21474 = eq(bht_rd_addr_f, UInt<6>("h021")) @[ifu_bp_ctl.scala 454:79] - node _T_21475 = bits(_T_21474, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21476 = eq(bht_rd_addr_f, UInt<6>("h022")) @[ifu_bp_ctl.scala 454:79] - node _T_21477 = bits(_T_21476, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21478 = eq(bht_rd_addr_f, UInt<6>("h023")) @[ifu_bp_ctl.scala 454:79] - node _T_21479 = bits(_T_21478, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21480 = eq(bht_rd_addr_f, UInt<6>("h024")) @[ifu_bp_ctl.scala 454:79] - node _T_21481 = bits(_T_21480, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21482 = eq(bht_rd_addr_f, UInt<6>("h025")) @[ifu_bp_ctl.scala 454:79] - node _T_21483 = bits(_T_21482, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21484 = eq(bht_rd_addr_f, UInt<6>("h026")) @[ifu_bp_ctl.scala 454:79] - node _T_21485 = bits(_T_21484, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21486 = eq(bht_rd_addr_f, UInt<6>("h027")) @[ifu_bp_ctl.scala 454:79] - node _T_21487 = bits(_T_21486, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21488 = eq(bht_rd_addr_f, UInt<6>("h028")) @[ifu_bp_ctl.scala 454:79] - node _T_21489 = bits(_T_21488, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21490 = eq(bht_rd_addr_f, UInt<6>("h029")) @[ifu_bp_ctl.scala 454:79] - node _T_21491 = bits(_T_21490, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21492 = eq(bht_rd_addr_f, UInt<6>("h02a")) @[ifu_bp_ctl.scala 454:79] - node _T_21493 = bits(_T_21492, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21494 = eq(bht_rd_addr_f, UInt<6>("h02b")) @[ifu_bp_ctl.scala 454:79] - node _T_21495 = bits(_T_21494, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21496 = eq(bht_rd_addr_f, UInt<6>("h02c")) @[ifu_bp_ctl.scala 454:79] - node _T_21497 = bits(_T_21496, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21498 = eq(bht_rd_addr_f, UInt<6>("h02d")) @[ifu_bp_ctl.scala 454:79] - node _T_21499 = bits(_T_21498, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21500 = eq(bht_rd_addr_f, UInt<6>("h02e")) @[ifu_bp_ctl.scala 454:79] - node _T_21501 = bits(_T_21500, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21502 = eq(bht_rd_addr_f, UInt<6>("h02f")) @[ifu_bp_ctl.scala 454:79] - node _T_21503 = bits(_T_21502, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21504 = eq(bht_rd_addr_f, UInt<6>("h030")) @[ifu_bp_ctl.scala 454:79] - node _T_21505 = bits(_T_21504, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21506 = eq(bht_rd_addr_f, UInt<6>("h031")) @[ifu_bp_ctl.scala 454:79] - node _T_21507 = bits(_T_21506, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21508 = eq(bht_rd_addr_f, UInt<6>("h032")) @[ifu_bp_ctl.scala 454:79] - node _T_21509 = bits(_T_21508, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21510 = eq(bht_rd_addr_f, UInt<6>("h033")) @[ifu_bp_ctl.scala 454:79] - node _T_21511 = bits(_T_21510, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21512 = eq(bht_rd_addr_f, UInt<6>("h034")) @[ifu_bp_ctl.scala 454:79] - node _T_21513 = bits(_T_21512, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21514 = eq(bht_rd_addr_f, UInt<6>("h035")) @[ifu_bp_ctl.scala 454:79] - node _T_21515 = bits(_T_21514, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21516 = eq(bht_rd_addr_f, UInt<6>("h036")) @[ifu_bp_ctl.scala 454:79] - node _T_21517 = bits(_T_21516, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21518 = eq(bht_rd_addr_f, UInt<6>("h037")) @[ifu_bp_ctl.scala 454:79] - node _T_21519 = bits(_T_21518, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21520 = eq(bht_rd_addr_f, UInt<6>("h038")) @[ifu_bp_ctl.scala 454:79] - node _T_21521 = bits(_T_21520, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21522 = eq(bht_rd_addr_f, UInt<6>("h039")) @[ifu_bp_ctl.scala 454:79] - node _T_21523 = bits(_T_21522, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21524 = eq(bht_rd_addr_f, UInt<6>("h03a")) @[ifu_bp_ctl.scala 454:79] - node _T_21525 = bits(_T_21524, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21526 = eq(bht_rd_addr_f, UInt<6>("h03b")) @[ifu_bp_ctl.scala 454:79] - node _T_21527 = bits(_T_21526, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21528 = eq(bht_rd_addr_f, UInt<6>("h03c")) @[ifu_bp_ctl.scala 454:79] - node _T_21529 = bits(_T_21528, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21530 = eq(bht_rd_addr_f, UInt<6>("h03d")) @[ifu_bp_ctl.scala 454:79] - node _T_21531 = bits(_T_21530, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21532 = eq(bht_rd_addr_f, UInt<6>("h03e")) @[ifu_bp_ctl.scala 454:79] - node _T_21533 = bits(_T_21532, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21534 = eq(bht_rd_addr_f, UInt<6>("h03f")) @[ifu_bp_ctl.scala 454:79] - node _T_21535 = bits(_T_21534, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21536 = eq(bht_rd_addr_f, UInt<7>("h040")) @[ifu_bp_ctl.scala 454:79] - node _T_21537 = bits(_T_21536, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21538 = eq(bht_rd_addr_f, UInt<7>("h041")) @[ifu_bp_ctl.scala 454:79] - node _T_21539 = bits(_T_21538, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21540 = eq(bht_rd_addr_f, UInt<7>("h042")) @[ifu_bp_ctl.scala 454:79] - node _T_21541 = bits(_T_21540, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21542 = eq(bht_rd_addr_f, UInt<7>("h043")) @[ifu_bp_ctl.scala 454:79] - node _T_21543 = bits(_T_21542, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21544 = eq(bht_rd_addr_f, UInt<7>("h044")) @[ifu_bp_ctl.scala 454:79] - node _T_21545 = bits(_T_21544, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21546 = eq(bht_rd_addr_f, UInt<7>("h045")) @[ifu_bp_ctl.scala 454:79] - node _T_21547 = bits(_T_21546, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21548 = eq(bht_rd_addr_f, UInt<7>("h046")) @[ifu_bp_ctl.scala 454:79] - node _T_21549 = bits(_T_21548, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21550 = eq(bht_rd_addr_f, UInt<7>("h047")) @[ifu_bp_ctl.scala 454:79] - node _T_21551 = bits(_T_21550, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21552 = eq(bht_rd_addr_f, UInt<7>("h048")) @[ifu_bp_ctl.scala 454:79] - node _T_21553 = bits(_T_21552, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21554 = eq(bht_rd_addr_f, UInt<7>("h049")) @[ifu_bp_ctl.scala 454:79] - node _T_21555 = bits(_T_21554, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21556 = eq(bht_rd_addr_f, UInt<7>("h04a")) @[ifu_bp_ctl.scala 454:79] - node _T_21557 = bits(_T_21556, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21558 = eq(bht_rd_addr_f, UInt<7>("h04b")) @[ifu_bp_ctl.scala 454:79] - node _T_21559 = bits(_T_21558, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21560 = eq(bht_rd_addr_f, UInt<7>("h04c")) @[ifu_bp_ctl.scala 454:79] - node _T_21561 = bits(_T_21560, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21562 = eq(bht_rd_addr_f, UInt<7>("h04d")) @[ifu_bp_ctl.scala 454:79] - node _T_21563 = bits(_T_21562, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21564 = eq(bht_rd_addr_f, UInt<7>("h04e")) @[ifu_bp_ctl.scala 454:79] - node _T_21565 = bits(_T_21564, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21566 = eq(bht_rd_addr_f, UInt<7>("h04f")) @[ifu_bp_ctl.scala 454:79] - node _T_21567 = bits(_T_21566, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21568 = eq(bht_rd_addr_f, UInt<7>("h050")) @[ifu_bp_ctl.scala 454:79] - node _T_21569 = bits(_T_21568, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21570 = eq(bht_rd_addr_f, UInt<7>("h051")) @[ifu_bp_ctl.scala 454:79] - node _T_21571 = bits(_T_21570, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21572 = eq(bht_rd_addr_f, UInt<7>("h052")) @[ifu_bp_ctl.scala 454:79] - node _T_21573 = bits(_T_21572, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21574 = eq(bht_rd_addr_f, UInt<7>("h053")) @[ifu_bp_ctl.scala 454:79] - node _T_21575 = bits(_T_21574, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21576 = eq(bht_rd_addr_f, UInt<7>("h054")) @[ifu_bp_ctl.scala 454:79] - node _T_21577 = bits(_T_21576, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21578 = eq(bht_rd_addr_f, UInt<7>("h055")) @[ifu_bp_ctl.scala 454:79] - node _T_21579 = bits(_T_21578, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21580 = eq(bht_rd_addr_f, UInt<7>("h056")) @[ifu_bp_ctl.scala 454:79] - node _T_21581 = bits(_T_21580, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21582 = eq(bht_rd_addr_f, UInt<7>("h057")) @[ifu_bp_ctl.scala 454:79] - node _T_21583 = bits(_T_21582, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21584 = eq(bht_rd_addr_f, UInt<7>("h058")) @[ifu_bp_ctl.scala 454:79] - node _T_21585 = bits(_T_21584, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21586 = eq(bht_rd_addr_f, UInt<7>("h059")) @[ifu_bp_ctl.scala 454:79] - node _T_21587 = bits(_T_21586, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21588 = eq(bht_rd_addr_f, UInt<7>("h05a")) @[ifu_bp_ctl.scala 454:79] - node _T_21589 = bits(_T_21588, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21590 = eq(bht_rd_addr_f, UInt<7>("h05b")) @[ifu_bp_ctl.scala 454:79] - node _T_21591 = bits(_T_21590, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21592 = eq(bht_rd_addr_f, UInt<7>("h05c")) @[ifu_bp_ctl.scala 454:79] - node _T_21593 = bits(_T_21592, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21594 = eq(bht_rd_addr_f, UInt<7>("h05d")) @[ifu_bp_ctl.scala 454:79] - node _T_21595 = bits(_T_21594, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21596 = eq(bht_rd_addr_f, UInt<7>("h05e")) @[ifu_bp_ctl.scala 454:79] - node _T_21597 = bits(_T_21596, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21598 = eq(bht_rd_addr_f, UInt<7>("h05f")) @[ifu_bp_ctl.scala 454:79] - node _T_21599 = bits(_T_21598, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21600 = eq(bht_rd_addr_f, UInt<7>("h060")) @[ifu_bp_ctl.scala 454:79] - node _T_21601 = bits(_T_21600, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21602 = eq(bht_rd_addr_f, UInt<7>("h061")) @[ifu_bp_ctl.scala 454:79] - node _T_21603 = bits(_T_21602, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21604 = eq(bht_rd_addr_f, UInt<7>("h062")) @[ifu_bp_ctl.scala 454:79] - node _T_21605 = bits(_T_21604, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21606 = eq(bht_rd_addr_f, UInt<7>("h063")) @[ifu_bp_ctl.scala 454:79] - node _T_21607 = bits(_T_21606, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21608 = eq(bht_rd_addr_f, UInt<7>("h064")) @[ifu_bp_ctl.scala 454:79] - node _T_21609 = bits(_T_21608, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21610 = eq(bht_rd_addr_f, UInt<7>("h065")) @[ifu_bp_ctl.scala 454:79] - node _T_21611 = bits(_T_21610, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21612 = eq(bht_rd_addr_f, UInt<7>("h066")) @[ifu_bp_ctl.scala 454:79] - node _T_21613 = bits(_T_21612, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21614 = eq(bht_rd_addr_f, UInt<7>("h067")) @[ifu_bp_ctl.scala 454:79] - node _T_21615 = bits(_T_21614, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21616 = eq(bht_rd_addr_f, UInt<7>("h068")) @[ifu_bp_ctl.scala 454:79] - node _T_21617 = bits(_T_21616, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21618 = eq(bht_rd_addr_f, UInt<7>("h069")) @[ifu_bp_ctl.scala 454:79] - node _T_21619 = bits(_T_21618, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21620 = eq(bht_rd_addr_f, UInt<7>("h06a")) @[ifu_bp_ctl.scala 454:79] - node _T_21621 = bits(_T_21620, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21622 = eq(bht_rd_addr_f, UInt<7>("h06b")) @[ifu_bp_ctl.scala 454:79] - node _T_21623 = bits(_T_21622, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21624 = eq(bht_rd_addr_f, UInt<7>("h06c")) @[ifu_bp_ctl.scala 454:79] - node _T_21625 = bits(_T_21624, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21626 = eq(bht_rd_addr_f, UInt<7>("h06d")) @[ifu_bp_ctl.scala 454:79] - node _T_21627 = bits(_T_21626, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21628 = eq(bht_rd_addr_f, UInt<7>("h06e")) @[ifu_bp_ctl.scala 454:79] - node _T_21629 = bits(_T_21628, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21630 = eq(bht_rd_addr_f, UInt<7>("h06f")) @[ifu_bp_ctl.scala 454:79] - node _T_21631 = bits(_T_21630, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21632 = eq(bht_rd_addr_f, UInt<7>("h070")) @[ifu_bp_ctl.scala 454:79] - node _T_21633 = bits(_T_21632, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21634 = eq(bht_rd_addr_f, UInt<7>("h071")) @[ifu_bp_ctl.scala 454:79] - node _T_21635 = bits(_T_21634, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21636 = eq(bht_rd_addr_f, UInt<7>("h072")) @[ifu_bp_ctl.scala 454:79] - node _T_21637 = bits(_T_21636, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21638 = eq(bht_rd_addr_f, UInt<7>("h073")) @[ifu_bp_ctl.scala 454:79] - node _T_21639 = bits(_T_21638, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21640 = eq(bht_rd_addr_f, UInt<7>("h074")) @[ifu_bp_ctl.scala 454:79] - node _T_21641 = bits(_T_21640, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21642 = eq(bht_rd_addr_f, UInt<7>("h075")) @[ifu_bp_ctl.scala 454:79] - node _T_21643 = bits(_T_21642, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21644 = eq(bht_rd_addr_f, UInt<7>("h076")) @[ifu_bp_ctl.scala 454:79] - node _T_21645 = bits(_T_21644, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21646 = eq(bht_rd_addr_f, UInt<7>("h077")) @[ifu_bp_ctl.scala 454:79] - node _T_21647 = bits(_T_21646, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21648 = eq(bht_rd_addr_f, UInt<7>("h078")) @[ifu_bp_ctl.scala 454:79] - node _T_21649 = bits(_T_21648, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21650 = eq(bht_rd_addr_f, UInt<7>("h079")) @[ifu_bp_ctl.scala 454:79] - node _T_21651 = bits(_T_21650, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21652 = eq(bht_rd_addr_f, UInt<7>("h07a")) @[ifu_bp_ctl.scala 454:79] - node _T_21653 = bits(_T_21652, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21654 = eq(bht_rd_addr_f, UInt<7>("h07b")) @[ifu_bp_ctl.scala 454:79] - node _T_21655 = bits(_T_21654, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21656 = eq(bht_rd_addr_f, UInt<7>("h07c")) @[ifu_bp_ctl.scala 454:79] - node _T_21657 = bits(_T_21656, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21658 = eq(bht_rd_addr_f, UInt<7>("h07d")) @[ifu_bp_ctl.scala 454:79] - node _T_21659 = bits(_T_21658, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21660 = eq(bht_rd_addr_f, UInt<7>("h07e")) @[ifu_bp_ctl.scala 454:79] - node _T_21661 = bits(_T_21660, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21662 = eq(bht_rd_addr_f, UInt<7>("h07f")) @[ifu_bp_ctl.scala 454:79] - node _T_21663 = bits(_T_21662, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21664 = eq(bht_rd_addr_f, UInt<8>("h080")) @[ifu_bp_ctl.scala 454:79] - node _T_21665 = bits(_T_21664, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21666 = eq(bht_rd_addr_f, UInt<8>("h081")) @[ifu_bp_ctl.scala 454:79] - node _T_21667 = bits(_T_21666, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21668 = eq(bht_rd_addr_f, UInt<8>("h082")) @[ifu_bp_ctl.scala 454:79] - node _T_21669 = bits(_T_21668, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21670 = eq(bht_rd_addr_f, UInt<8>("h083")) @[ifu_bp_ctl.scala 454:79] - node _T_21671 = bits(_T_21670, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21672 = eq(bht_rd_addr_f, UInt<8>("h084")) @[ifu_bp_ctl.scala 454:79] - node _T_21673 = bits(_T_21672, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21674 = eq(bht_rd_addr_f, UInt<8>("h085")) @[ifu_bp_ctl.scala 454:79] - node _T_21675 = bits(_T_21674, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21676 = eq(bht_rd_addr_f, UInt<8>("h086")) @[ifu_bp_ctl.scala 454:79] - node _T_21677 = bits(_T_21676, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21678 = eq(bht_rd_addr_f, UInt<8>("h087")) @[ifu_bp_ctl.scala 454:79] - node _T_21679 = bits(_T_21678, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21680 = eq(bht_rd_addr_f, UInt<8>("h088")) @[ifu_bp_ctl.scala 454:79] - node _T_21681 = bits(_T_21680, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21682 = eq(bht_rd_addr_f, UInt<8>("h089")) @[ifu_bp_ctl.scala 454:79] - node _T_21683 = bits(_T_21682, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21684 = eq(bht_rd_addr_f, UInt<8>("h08a")) @[ifu_bp_ctl.scala 454:79] - node _T_21685 = bits(_T_21684, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21686 = eq(bht_rd_addr_f, UInt<8>("h08b")) @[ifu_bp_ctl.scala 454:79] - node _T_21687 = bits(_T_21686, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21688 = eq(bht_rd_addr_f, UInt<8>("h08c")) @[ifu_bp_ctl.scala 454:79] - node _T_21689 = bits(_T_21688, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21690 = eq(bht_rd_addr_f, UInt<8>("h08d")) @[ifu_bp_ctl.scala 454:79] - node _T_21691 = bits(_T_21690, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21692 = eq(bht_rd_addr_f, UInt<8>("h08e")) @[ifu_bp_ctl.scala 454:79] - node _T_21693 = bits(_T_21692, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21694 = eq(bht_rd_addr_f, UInt<8>("h08f")) @[ifu_bp_ctl.scala 454:79] - node _T_21695 = bits(_T_21694, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21696 = eq(bht_rd_addr_f, UInt<8>("h090")) @[ifu_bp_ctl.scala 454:79] - node _T_21697 = bits(_T_21696, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21698 = eq(bht_rd_addr_f, UInt<8>("h091")) @[ifu_bp_ctl.scala 454:79] - node _T_21699 = bits(_T_21698, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21700 = eq(bht_rd_addr_f, UInt<8>("h092")) @[ifu_bp_ctl.scala 454:79] - node _T_21701 = bits(_T_21700, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21702 = eq(bht_rd_addr_f, UInt<8>("h093")) @[ifu_bp_ctl.scala 454:79] - node _T_21703 = bits(_T_21702, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21704 = eq(bht_rd_addr_f, UInt<8>("h094")) @[ifu_bp_ctl.scala 454:79] - node _T_21705 = bits(_T_21704, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21706 = eq(bht_rd_addr_f, UInt<8>("h095")) @[ifu_bp_ctl.scala 454:79] - node _T_21707 = bits(_T_21706, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21708 = eq(bht_rd_addr_f, UInt<8>("h096")) @[ifu_bp_ctl.scala 454:79] - node _T_21709 = bits(_T_21708, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21710 = eq(bht_rd_addr_f, UInt<8>("h097")) @[ifu_bp_ctl.scala 454:79] - node _T_21711 = bits(_T_21710, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21712 = eq(bht_rd_addr_f, UInt<8>("h098")) @[ifu_bp_ctl.scala 454:79] - node _T_21713 = bits(_T_21712, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21714 = eq(bht_rd_addr_f, UInt<8>("h099")) @[ifu_bp_ctl.scala 454:79] - node _T_21715 = bits(_T_21714, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21716 = eq(bht_rd_addr_f, UInt<8>("h09a")) @[ifu_bp_ctl.scala 454:79] - node _T_21717 = bits(_T_21716, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21718 = eq(bht_rd_addr_f, UInt<8>("h09b")) @[ifu_bp_ctl.scala 454:79] - node _T_21719 = bits(_T_21718, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21720 = eq(bht_rd_addr_f, UInt<8>("h09c")) @[ifu_bp_ctl.scala 454:79] - node _T_21721 = bits(_T_21720, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21722 = eq(bht_rd_addr_f, UInt<8>("h09d")) @[ifu_bp_ctl.scala 454:79] - node _T_21723 = bits(_T_21722, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21724 = eq(bht_rd_addr_f, UInt<8>("h09e")) @[ifu_bp_ctl.scala 454:79] - node _T_21725 = bits(_T_21724, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21726 = eq(bht_rd_addr_f, UInt<8>("h09f")) @[ifu_bp_ctl.scala 454:79] - node _T_21727 = bits(_T_21726, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21728 = eq(bht_rd_addr_f, UInt<8>("h0a0")) @[ifu_bp_ctl.scala 454:79] - node _T_21729 = bits(_T_21728, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21730 = eq(bht_rd_addr_f, UInt<8>("h0a1")) @[ifu_bp_ctl.scala 454:79] - node _T_21731 = bits(_T_21730, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21732 = eq(bht_rd_addr_f, UInt<8>("h0a2")) @[ifu_bp_ctl.scala 454:79] - node _T_21733 = bits(_T_21732, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21734 = eq(bht_rd_addr_f, UInt<8>("h0a3")) @[ifu_bp_ctl.scala 454:79] - node _T_21735 = bits(_T_21734, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21736 = eq(bht_rd_addr_f, UInt<8>("h0a4")) @[ifu_bp_ctl.scala 454:79] - node _T_21737 = bits(_T_21736, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21738 = eq(bht_rd_addr_f, UInt<8>("h0a5")) @[ifu_bp_ctl.scala 454:79] - node _T_21739 = bits(_T_21738, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21740 = eq(bht_rd_addr_f, UInt<8>("h0a6")) @[ifu_bp_ctl.scala 454:79] - node _T_21741 = bits(_T_21740, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21742 = eq(bht_rd_addr_f, UInt<8>("h0a7")) @[ifu_bp_ctl.scala 454:79] - node _T_21743 = bits(_T_21742, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21744 = eq(bht_rd_addr_f, UInt<8>("h0a8")) @[ifu_bp_ctl.scala 454:79] - node _T_21745 = bits(_T_21744, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21746 = eq(bht_rd_addr_f, UInt<8>("h0a9")) @[ifu_bp_ctl.scala 454:79] - node _T_21747 = bits(_T_21746, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21748 = eq(bht_rd_addr_f, UInt<8>("h0aa")) @[ifu_bp_ctl.scala 454:79] - node _T_21749 = bits(_T_21748, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21750 = eq(bht_rd_addr_f, UInt<8>("h0ab")) @[ifu_bp_ctl.scala 454:79] - node _T_21751 = bits(_T_21750, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21752 = eq(bht_rd_addr_f, UInt<8>("h0ac")) @[ifu_bp_ctl.scala 454:79] - node _T_21753 = bits(_T_21752, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21754 = eq(bht_rd_addr_f, UInt<8>("h0ad")) @[ifu_bp_ctl.scala 454:79] - node _T_21755 = bits(_T_21754, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21756 = eq(bht_rd_addr_f, UInt<8>("h0ae")) @[ifu_bp_ctl.scala 454:79] - node _T_21757 = bits(_T_21756, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21758 = eq(bht_rd_addr_f, UInt<8>("h0af")) @[ifu_bp_ctl.scala 454:79] - node _T_21759 = bits(_T_21758, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21760 = eq(bht_rd_addr_f, UInt<8>("h0b0")) @[ifu_bp_ctl.scala 454:79] - node _T_21761 = bits(_T_21760, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21762 = eq(bht_rd_addr_f, UInt<8>("h0b1")) @[ifu_bp_ctl.scala 454:79] - node _T_21763 = bits(_T_21762, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21764 = eq(bht_rd_addr_f, UInt<8>("h0b2")) @[ifu_bp_ctl.scala 454:79] - node _T_21765 = bits(_T_21764, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21766 = eq(bht_rd_addr_f, UInt<8>("h0b3")) @[ifu_bp_ctl.scala 454:79] - node _T_21767 = bits(_T_21766, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21768 = eq(bht_rd_addr_f, UInt<8>("h0b4")) @[ifu_bp_ctl.scala 454:79] - node _T_21769 = bits(_T_21768, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21770 = eq(bht_rd_addr_f, UInt<8>("h0b5")) @[ifu_bp_ctl.scala 454:79] - node _T_21771 = bits(_T_21770, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21772 = eq(bht_rd_addr_f, UInt<8>("h0b6")) @[ifu_bp_ctl.scala 454:79] - node _T_21773 = bits(_T_21772, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21774 = eq(bht_rd_addr_f, UInt<8>("h0b7")) @[ifu_bp_ctl.scala 454:79] - node _T_21775 = bits(_T_21774, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21776 = eq(bht_rd_addr_f, UInt<8>("h0b8")) @[ifu_bp_ctl.scala 454:79] - node _T_21777 = bits(_T_21776, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21778 = eq(bht_rd_addr_f, UInt<8>("h0b9")) @[ifu_bp_ctl.scala 454:79] - node _T_21779 = bits(_T_21778, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21780 = eq(bht_rd_addr_f, UInt<8>("h0ba")) @[ifu_bp_ctl.scala 454:79] - node _T_21781 = bits(_T_21780, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21782 = eq(bht_rd_addr_f, UInt<8>("h0bb")) @[ifu_bp_ctl.scala 454:79] - node _T_21783 = bits(_T_21782, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21784 = eq(bht_rd_addr_f, UInt<8>("h0bc")) @[ifu_bp_ctl.scala 454:79] - node _T_21785 = bits(_T_21784, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21786 = eq(bht_rd_addr_f, UInt<8>("h0bd")) @[ifu_bp_ctl.scala 454:79] - node _T_21787 = bits(_T_21786, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21788 = eq(bht_rd_addr_f, UInt<8>("h0be")) @[ifu_bp_ctl.scala 454:79] - node _T_21789 = bits(_T_21788, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21790 = eq(bht_rd_addr_f, UInt<8>("h0bf")) @[ifu_bp_ctl.scala 454:79] - node _T_21791 = bits(_T_21790, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21792 = eq(bht_rd_addr_f, UInt<8>("h0c0")) @[ifu_bp_ctl.scala 454:79] - node _T_21793 = bits(_T_21792, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21794 = eq(bht_rd_addr_f, UInt<8>("h0c1")) @[ifu_bp_ctl.scala 454:79] - node _T_21795 = bits(_T_21794, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21796 = eq(bht_rd_addr_f, UInt<8>("h0c2")) @[ifu_bp_ctl.scala 454:79] - node _T_21797 = bits(_T_21796, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21798 = eq(bht_rd_addr_f, UInt<8>("h0c3")) @[ifu_bp_ctl.scala 454:79] - node _T_21799 = bits(_T_21798, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21800 = eq(bht_rd_addr_f, UInt<8>("h0c4")) @[ifu_bp_ctl.scala 454:79] - node _T_21801 = bits(_T_21800, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21802 = eq(bht_rd_addr_f, UInt<8>("h0c5")) @[ifu_bp_ctl.scala 454:79] - node _T_21803 = bits(_T_21802, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21804 = eq(bht_rd_addr_f, UInt<8>("h0c6")) @[ifu_bp_ctl.scala 454:79] - node _T_21805 = bits(_T_21804, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21806 = eq(bht_rd_addr_f, UInt<8>("h0c7")) @[ifu_bp_ctl.scala 454:79] - node _T_21807 = bits(_T_21806, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21808 = eq(bht_rd_addr_f, UInt<8>("h0c8")) @[ifu_bp_ctl.scala 454:79] - node _T_21809 = bits(_T_21808, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21810 = eq(bht_rd_addr_f, UInt<8>("h0c9")) @[ifu_bp_ctl.scala 454:79] - node _T_21811 = bits(_T_21810, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21812 = eq(bht_rd_addr_f, UInt<8>("h0ca")) @[ifu_bp_ctl.scala 454:79] - node _T_21813 = bits(_T_21812, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21814 = eq(bht_rd_addr_f, UInt<8>("h0cb")) @[ifu_bp_ctl.scala 454:79] - node _T_21815 = bits(_T_21814, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21816 = eq(bht_rd_addr_f, UInt<8>("h0cc")) @[ifu_bp_ctl.scala 454:79] - node _T_21817 = bits(_T_21816, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21818 = eq(bht_rd_addr_f, UInt<8>("h0cd")) @[ifu_bp_ctl.scala 454:79] - node _T_21819 = bits(_T_21818, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21820 = eq(bht_rd_addr_f, UInt<8>("h0ce")) @[ifu_bp_ctl.scala 454:79] - node _T_21821 = bits(_T_21820, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21822 = eq(bht_rd_addr_f, UInt<8>("h0cf")) @[ifu_bp_ctl.scala 454:79] - node _T_21823 = bits(_T_21822, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21824 = eq(bht_rd_addr_f, UInt<8>("h0d0")) @[ifu_bp_ctl.scala 454:79] - node _T_21825 = bits(_T_21824, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21826 = eq(bht_rd_addr_f, UInt<8>("h0d1")) @[ifu_bp_ctl.scala 454:79] - node _T_21827 = bits(_T_21826, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21828 = eq(bht_rd_addr_f, UInt<8>("h0d2")) @[ifu_bp_ctl.scala 454:79] - node _T_21829 = bits(_T_21828, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21830 = eq(bht_rd_addr_f, UInt<8>("h0d3")) @[ifu_bp_ctl.scala 454:79] - node _T_21831 = bits(_T_21830, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21832 = eq(bht_rd_addr_f, UInt<8>("h0d4")) @[ifu_bp_ctl.scala 454:79] - node _T_21833 = bits(_T_21832, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21834 = eq(bht_rd_addr_f, UInt<8>("h0d5")) @[ifu_bp_ctl.scala 454:79] - node _T_21835 = bits(_T_21834, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21836 = eq(bht_rd_addr_f, UInt<8>("h0d6")) @[ifu_bp_ctl.scala 454:79] - node _T_21837 = bits(_T_21836, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21838 = eq(bht_rd_addr_f, UInt<8>("h0d7")) @[ifu_bp_ctl.scala 454:79] - node _T_21839 = bits(_T_21838, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21840 = eq(bht_rd_addr_f, UInt<8>("h0d8")) @[ifu_bp_ctl.scala 454:79] - node _T_21841 = bits(_T_21840, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21842 = eq(bht_rd_addr_f, UInt<8>("h0d9")) @[ifu_bp_ctl.scala 454:79] - node _T_21843 = bits(_T_21842, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21844 = eq(bht_rd_addr_f, UInt<8>("h0da")) @[ifu_bp_ctl.scala 454:79] - node _T_21845 = bits(_T_21844, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21846 = eq(bht_rd_addr_f, UInt<8>("h0db")) @[ifu_bp_ctl.scala 454:79] - node _T_21847 = bits(_T_21846, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21848 = eq(bht_rd_addr_f, UInt<8>("h0dc")) @[ifu_bp_ctl.scala 454:79] - node _T_21849 = bits(_T_21848, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21850 = eq(bht_rd_addr_f, UInt<8>("h0dd")) @[ifu_bp_ctl.scala 454:79] - node _T_21851 = bits(_T_21850, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21852 = eq(bht_rd_addr_f, UInt<8>("h0de")) @[ifu_bp_ctl.scala 454:79] - node _T_21853 = bits(_T_21852, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21854 = eq(bht_rd_addr_f, UInt<8>("h0df")) @[ifu_bp_ctl.scala 454:79] - node _T_21855 = bits(_T_21854, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21856 = eq(bht_rd_addr_f, UInt<8>("h0e0")) @[ifu_bp_ctl.scala 454:79] - node _T_21857 = bits(_T_21856, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21858 = eq(bht_rd_addr_f, UInt<8>("h0e1")) @[ifu_bp_ctl.scala 454:79] - node _T_21859 = bits(_T_21858, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21860 = eq(bht_rd_addr_f, UInt<8>("h0e2")) @[ifu_bp_ctl.scala 454:79] - node _T_21861 = bits(_T_21860, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21862 = eq(bht_rd_addr_f, UInt<8>("h0e3")) @[ifu_bp_ctl.scala 454:79] - node _T_21863 = bits(_T_21862, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21864 = eq(bht_rd_addr_f, UInt<8>("h0e4")) @[ifu_bp_ctl.scala 454:79] - node _T_21865 = bits(_T_21864, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21866 = eq(bht_rd_addr_f, UInt<8>("h0e5")) @[ifu_bp_ctl.scala 454:79] - node _T_21867 = bits(_T_21866, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21868 = eq(bht_rd_addr_f, UInt<8>("h0e6")) @[ifu_bp_ctl.scala 454:79] - node _T_21869 = bits(_T_21868, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21870 = eq(bht_rd_addr_f, UInt<8>("h0e7")) @[ifu_bp_ctl.scala 454:79] - node _T_21871 = bits(_T_21870, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21872 = eq(bht_rd_addr_f, UInt<8>("h0e8")) @[ifu_bp_ctl.scala 454:79] - node _T_21873 = bits(_T_21872, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21874 = eq(bht_rd_addr_f, UInt<8>("h0e9")) @[ifu_bp_ctl.scala 454:79] - node _T_21875 = bits(_T_21874, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21876 = eq(bht_rd_addr_f, UInt<8>("h0ea")) @[ifu_bp_ctl.scala 454:79] - node _T_21877 = bits(_T_21876, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21878 = eq(bht_rd_addr_f, UInt<8>("h0eb")) @[ifu_bp_ctl.scala 454:79] - node _T_21879 = bits(_T_21878, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21880 = eq(bht_rd_addr_f, UInt<8>("h0ec")) @[ifu_bp_ctl.scala 454:79] - node _T_21881 = bits(_T_21880, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21882 = eq(bht_rd_addr_f, UInt<8>("h0ed")) @[ifu_bp_ctl.scala 454:79] - node _T_21883 = bits(_T_21882, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21884 = eq(bht_rd_addr_f, UInt<8>("h0ee")) @[ifu_bp_ctl.scala 454:79] - node _T_21885 = bits(_T_21884, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21886 = eq(bht_rd_addr_f, UInt<8>("h0ef")) @[ifu_bp_ctl.scala 454:79] - node _T_21887 = bits(_T_21886, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21888 = eq(bht_rd_addr_f, UInt<8>("h0f0")) @[ifu_bp_ctl.scala 454:79] - node _T_21889 = bits(_T_21888, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21890 = eq(bht_rd_addr_f, UInt<8>("h0f1")) @[ifu_bp_ctl.scala 454:79] - node _T_21891 = bits(_T_21890, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21892 = eq(bht_rd_addr_f, UInt<8>("h0f2")) @[ifu_bp_ctl.scala 454:79] - node _T_21893 = bits(_T_21892, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21894 = eq(bht_rd_addr_f, UInt<8>("h0f3")) @[ifu_bp_ctl.scala 454:79] - node _T_21895 = bits(_T_21894, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21896 = eq(bht_rd_addr_f, UInt<8>("h0f4")) @[ifu_bp_ctl.scala 454:79] - node _T_21897 = bits(_T_21896, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21898 = eq(bht_rd_addr_f, UInt<8>("h0f5")) @[ifu_bp_ctl.scala 454:79] - node _T_21899 = bits(_T_21898, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21900 = eq(bht_rd_addr_f, UInt<8>("h0f6")) @[ifu_bp_ctl.scala 454:79] - node _T_21901 = bits(_T_21900, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21902 = eq(bht_rd_addr_f, UInt<8>("h0f7")) @[ifu_bp_ctl.scala 454:79] - node _T_21903 = bits(_T_21902, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21904 = eq(bht_rd_addr_f, UInt<8>("h0f8")) @[ifu_bp_ctl.scala 454:79] - node _T_21905 = bits(_T_21904, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21906 = eq(bht_rd_addr_f, UInt<8>("h0f9")) @[ifu_bp_ctl.scala 454:79] - node _T_21907 = bits(_T_21906, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21908 = eq(bht_rd_addr_f, UInt<8>("h0fa")) @[ifu_bp_ctl.scala 454:79] - node _T_21909 = bits(_T_21908, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21910 = eq(bht_rd_addr_f, UInt<8>("h0fb")) @[ifu_bp_ctl.scala 454:79] - node _T_21911 = bits(_T_21910, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21912 = eq(bht_rd_addr_f, UInt<8>("h0fc")) @[ifu_bp_ctl.scala 454:79] - node _T_21913 = bits(_T_21912, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21914 = eq(bht_rd_addr_f, UInt<8>("h0fd")) @[ifu_bp_ctl.scala 454:79] - node _T_21915 = bits(_T_21914, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21916 = eq(bht_rd_addr_f, UInt<8>("h0fe")) @[ifu_bp_ctl.scala 454:79] - node _T_21917 = bits(_T_21916, 0, 0) @[ifu_bp_ctl.scala 454:87] - node _T_21918 = eq(bht_rd_addr_f, UInt<8>("h0ff")) @[ifu_bp_ctl.scala 454:79] - node _T_21919 = bits(_T_21918, 0, 0) @[ifu_bp_ctl.scala 454:87] + bht_bank0_rd_data_f <= _T_21407 @[ifu_bp_ctl.scala 454:23] + node _T_21408 = eq(bht_rd_addr_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 455:79] + node _T_21409 = bits(_T_21408, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21410 = eq(bht_rd_addr_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 455:79] + node _T_21411 = bits(_T_21410, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21412 = eq(bht_rd_addr_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 455:79] + node _T_21413 = bits(_T_21412, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21414 = eq(bht_rd_addr_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 455:79] + node _T_21415 = bits(_T_21414, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21416 = eq(bht_rd_addr_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 455:79] + node _T_21417 = bits(_T_21416, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21418 = eq(bht_rd_addr_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 455:79] + node _T_21419 = bits(_T_21418, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21420 = eq(bht_rd_addr_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 455:79] + node _T_21421 = bits(_T_21420, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21422 = eq(bht_rd_addr_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 455:79] + node _T_21423 = bits(_T_21422, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21424 = eq(bht_rd_addr_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 455:79] + node _T_21425 = bits(_T_21424, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21426 = eq(bht_rd_addr_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 455:79] + node _T_21427 = bits(_T_21426, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21428 = eq(bht_rd_addr_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 455:79] + node _T_21429 = bits(_T_21428, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21430 = eq(bht_rd_addr_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 455:79] + node _T_21431 = bits(_T_21430, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21432 = eq(bht_rd_addr_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 455:79] + node _T_21433 = bits(_T_21432, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21434 = eq(bht_rd_addr_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 455:79] + node _T_21435 = bits(_T_21434, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21436 = eq(bht_rd_addr_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 455:79] + node _T_21437 = bits(_T_21436, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21438 = eq(bht_rd_addr_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 455:79] + node _T_21439 = bits(_T_21438, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21440 = eq(bht_rd_addr_f, UInt<5>("h010")) @[ifu_bp_ctl.scala 455:79] + node _T_21441 = bits(_T_21440, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21442 = eq(bht_rd_addr_f, UInt<5>("h011")) @[ifu_bp_ctl.scala 455:79] + node _T_21443 = bits(_T_21442, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21444 = eq(bht_rd_addr_f, UInt<5>("h012")) @[ifu_bp_ctl.scala 455:79] + node _T_21445 = bits(_T_21444, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21446 = eq(bht_rd_addr_f, UInt<5>("h013")) @[ifu_bp_ctl.scala 455:79] + node _T_21447 = bits(_T_21446, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21448 = eq(bht_rd_addr_f, UInt<5>("h014")) @[ifu_bp_ctl.scala 455:79] + node _T_21449 = bits(_T_21448, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21450 = eq(bht_rd_addr_f, UInt<5>("h015")) @[ifu_bp_ctl.scala 455:79] + node _T_21451 = bits(_T_21450, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21452 = eq(bht_rd_addr_f, UInt<5>("h016")) @[ifu_bp_ctl.scala 455:79] + node _T_21453 = bits(_T_21452, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21454 = eq(bht_rd_addr_f, UInt<5>("h017")) @[ifu_bp_ctl.scala 455:79] + node _T_21455 = bits(_T_21454, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21456 = eq(bht_rd_addr_f, UInt<5>("h018")) @[ifu_bp_ctl.scala 455:79] + node _T_21457 = bits(_T_21456, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21458 = eq(bht_rd_addr_f, UInt<5>("h019")) @[ifu_bp_ctl.scala 455:79] + node _T_21459 = bits(_T_21458, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21460 = eq(bht_rd_addr_f, UInt<5>("h01a")) @[ifu_bp_ctl.scala 455:79] + node _T_21461 = bits(_T_21460, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21462 = eq(bht_rd_addr_f, UInt<5>("h01b")) @[ifu_bp_ctl.scala 455:79] + node _T_21463 = bits(_T_21462, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21464 = eq(bht_rd_addr_f, UInt<5>("h01c")) @[ifu_bp_ctl.scala 455:79] + node _T_21465 = bits(_T_21464, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21466 = eq(bht_rd_addr_f, UInt<5>("h01d")) @[ifu_bp_ctl.scala 455:79] + node _T_21467 = bits(_T_21466, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21468 = eq(bht_rd_addr_f, UInt<5>("h01e")) @[ifu_bp_ctl.scala 455:79] + node _T_21469 = bits(_T_21468, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21470 = eq(bht_rd_addr_f, UInt<5>("h01f")) @[ifu_bp_ctl.scala 455:79] + node _T_21471 = bits(_T_21470, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21472 = eq(bht_rd_addr_f, UInt<6>("h020")) @[ifu_bp_ctl.scala 455:79] + node _T_21473 = bits(_T_21472, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21474 = eq(bht_rd_addr_f, UInt<6>("h021")) @[ifu_bp_ctl.scala 455:79] + node _T_21475 = bits(_T_21474, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21476 = eq(bht_rd_addr_f, UInt<6>("h022")) @[ifu_bp_ctl.scala 455:79] + node _T_21477 = bits(_T_21476, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21478 = eq(bht_rd_addr_f, UInt<6>("h023")) @[ifu_bp_ctl.scala 455:79] + node _T_21479 = bits(_T_21478, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21480 = eq(bht_rd_addr_f, UInt<6>("h024")) @[ifu_bp_ctl.scala 455:79] + node _T_21481 = bits(_T_21480, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21482 = eq(bht_rd_addr_f, UInt<6>("h025")) @[ifu_bp_ctl.scala 455:79] + node _T_21483 = bits(_T_21482, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21484 = eq(bht_rd_addr_f, UInt<6>("h026")) @[ifu_bp_ctl.scala 455:79] + node _T_21485 = bits(_T_21484, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21486 = eq(bht_rd_addr_f, UInt<6>("h027")) @[ifu_bp_ctl.scala 455:79] + node _T_21487 = bits(_T_21486, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21488 = eq(bht_rd_addr_f, UInt<6>("h028")) @[ifu_bp_ctl.scala 455:79] + node _T_21489 = bits(_T_21488, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21490 = eq(bht_rd_addr_f, UInt<6>("h029")) @[ifu_bp_ctl.scala 455:79] + node _T_21491 = bits(_T_21490, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21492 = eq(bht_rd_addr_f, UInt<6>("h02a")) @[ifu_bp_ctl.scala 455:79] + node _T_21493 = bits(_T_21492, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21494 = eq(bht_rd_addr_f, UInt<6>("h02b")) @[ifu_bp_ctl.scala 455:79] + node _T_21495 = bits(_T_21494, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21496 = eq(bht_rd_addr_f, UInt<6>("h02c")) @[ifu_bp_ctl.scala 455:79] + node _T_21497 = bits(_T_21496, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21498 = eq(bht_rd_addr_f, UInt<6>("h02d")) @[ifu_bp_ctl.scala 455:79] + node _T_21499 = bits(_T_21498, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21500 = eq(bht_rd_addr_f, UInt<6>("h02e")) @[ifu_bp_ctl.scala 455:79] + node _T_21501 = bits(_T_21500, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21502 = eq(bht_rd_addr_f, UInt<6>("h02f")) @[ifu_bp_ctl.scala 455:79] + node _T_21503 = bits(_T_21502, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21504 = eq(bht_rd_addr_f, UInt<6>("h030")) @[ifu_bp_ctl.scala 455:79] + node _T_21505 = bits(_T_21504, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21506 = eq(bht_rd_addr_f, UInt<6>("h031")) @[ifu_bp_ctl.scala 455:79] + node _T_21507 = bits(_T_21506, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21508 = eq(bht_rd_addr_f, UInt<6>("h032")) @[ifu_bp_ctl.scala 455:79] + node _T_21509 = bits(_T_21508, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21510 = eq(bht_rd_addr_f, UInt<6>("h033")) @[ifu_bp_ctl.scala 455:79] + node _T_21511 = bits(_T_21510, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21512 = eq(bht_rd_addr_f, UInt<6>("h034")) @[ifu_bp_ctl.scala 455:79] + node _T_21513 = bits(_T_21512, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21514 = eq(bht_rd_addr_f, UInt<6>("h035")) @[ifu_bp_ctl.scala 455:79] + node _T_21515 = bits(_T_21514, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21516 = eq(bht_rd_addr_f, UInt<6>("h036")) @[ifu_bp_ctl.scala 455:79] + node _T_21517 = bits(_T_21516, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21518 = eq(bht_rd_addr_f, UInt<6>("h037")) @[ifu_bp_ctl.scala 455:79] + node _T_21519 = bits(_T_21518, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21520 = eq(bht_rd_addr_f, UInt<6>("h038")) @[ifu_bp_ctl.scala 455:79] + node _T_21521 = bits(_T_21520, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21522 = eq(bht_rd_addr_f, UInt<6>("h039")) @[ifu_bp_ctl.scala 455:79] + node _T_21523 = bits(_T_21522, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21524 = eq(bht_rd_addr_f, UInt<6>("h03a")) @[ifu_bp_ctl.scala 455:79] + node _T_21525 = bits(_T_21524, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21526 = eq(bht_rd_addr_f, UInt<6>("h03b")) @[ifu_bp_ctl.scala 455:79] + node _T_21527 = bits(_T_21526, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21528 = eq(bht_rd_addr_f, UInt<6>("h03c")) @[ifu_bp_ctl.scala 455:79] + node _T_21529 = bits(_T_21528, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21530 = eq(bht_rd_addr_f, UInt<6>("h03d")) @[ifu_bp_ctl.scala 455:79] + node _T_21531 = bits(_T_21530, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21532 = eq(bht_rd_addr_f, UInt<6>("h03e")) @[ifu_bp_ctl.scala 455:79] + node _T_21533 = bits(_T_21532, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21534 = eq(bht_rd_addr_f, UInt<6>("h03f")) @[ifu_bp_ctl.scala 455:79] + node _T_21535 = bits(_T_21534, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21536 = eq(bht_rd_addr_f, UInt<7>("h040")) @[ifu_bp_ctl.scala 455:79] + node _T_21537 = bits(_T_21536, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21538 = eq(bht_rd_addr_f, UInt<7>("h041")) @[ifu_bp_ctl.scala 455:79] + node _T_21539 = bits(_T_21538, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21540 = eq(bht_rd_addr_f, UInt<7>("h042")) @[ifu_bp_ctl.scala 455:79] + node _T_21541 = bits(_T_21540, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21542 = eq(bht_rd_addr_f, UInt<7>("h043")) @[ifu_bp_ctl.scala 455:79] + node _T_21543 = bits(_T_21542, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21544 = eq(bht_rd_addr_f, UInt<7>("h044")) @[ifu_bp_ctl.scala 455:79] + node _T_21545 = bits(_T_21544, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21546 = eq(bht_rd_addr_f, UInt<7>("h045")) @[ifu_bp_ctl.scala 455:79] + node _T_21547 = bits(_T_21546, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21548 = eq(bht_rd_addr_f, UInt<7>("h046")) @[ifu_bp_ctl.scala 455:79] + node _T_21549 = bits(_T_21548, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21550 = eq(bht_rd_addr_f, UInt<7>("h047")) @[ifu_bp_ctl.scala 455:79] + node _T_21551 = bits(_T_21550, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21552 = eq(bht_rd_addr_f, UInt<7>("h048")) @[ifu_bp_ctl.scala 455:79] + node _T_21553 = bits(_T_21552, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21554 = eq(bht_rd_addr_f, UInt<7>("h049")) @[ifu_bp_ctl.scala 455:79] + node _T_21555 = bits(_T_21554, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21556 = eq(bht_rd_addr_f, UInt<7>("h04a")) @[ifu_bp_ctl.scala 455:79] + node _T_21557 = bits(_T_21556, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21558 = eq(bht_rd_addr_f, UInt<7>("h04b")) @[ifu_bp_ctl.scala 455:79] + node _T_21559 = bits(_T_21558, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21560 = eq(bht_rd_addr_f, UInt<7>("h04c")) @[ifu_bp_ctl.scala 455:79] + node _T_21561 = bits(_T_21560, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21562 = eq(bht_rd_addr_f, UInt<7>("h04d")) @[ifu_bp_ctl.scala 455:79] + node _T_21563 = bits(_T_21562, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21564 = eq(bht_rd_addr_f, UInt<7>("h04e")) @[ifu_bp_ctl.scala 455:79] + node _T_21565 = bits(_T_21564, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21566 = eq(bht_rd_addr_f, UInt<7>("h04f")) @[ifu_bp_ctl.scala 455:79] + node _T_21567 = bits(_T_21566, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21568 = eq(bht_rd_addr_f, UInt<7>("h050")) @[ifu_bp_ctl.scala 455:79] + node _T_21569 = bits(_T_21568, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21570 = eq(bht_rd_addr_f, UInt<7>("h051")) @[ifu_bp_ctl.scala 455:79] + node _T_21571 = bits(_T_21570, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21572 = eq(bht_rd_addr_f, UInt<7>("h052")) @[ifu_bp_ctl.scala 455:79] + node _T_21573 = bits(_T_21572, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21574 = eq(bht_rd_addr_f, UInt<7>("h053")) @[ifu_bp_ctl.scala 455:79] + node _T_21575 = bits(_T_21574, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21576 = eq(bht_rd_addr_f, UInt<7>("h054")) @[ifu_bp_ctl.scala 455:79] + node _T_21577 = bits(_T_21576, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21578 = eq(bht_rd_addr_f, UInt<7>("h055")) @[ifu_bp_ctl.scala 455:79] + node _T_21579 = bits(_T_21578, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21580 = eq(bht_rd_addr_f, UInt<7>("h056")) @[ifu_bp_ctl.scala 455:79] + node _T_21581 = bits(_T_21580, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21582 = eq(bht_rd_addr_f, UInt<7>("h057")) @[ifu_bp_ctl.scala 455:79] + node _T_21583 = bits(_T_21582, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21584 = eq(bht_rd_addr_f, UInt<7>("h058")) @[ifu_bp_ctl.scala 455:79] + node _T_21585 = bits(_T_21584, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21586 = eq(bht_rd_addr_f, UInt<7>("h059")) @[ifu_bp_ctl.scala 455:79] + node _T_21587 = bits(_T_21586, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21588 = eq(bht_rd_addr_f, UInt<7>("h05a")) @[ifu_bp_ctl.scala 455:79] + node _T_21589 = bits(_T_21588, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21590 = eq(bht_rd_addr_f, UInt<7>("h05b")) @[ifu_bp_ctl.scala 455:79] + node _T_21591 = bits(_T_21590, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21592 = eq(bht_rd_addr_f, UInt<7>("h05c")) @[ifu_bp_ctl.scala 455:79] + node _T_21593 = bits(_T_21592, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21594 = eq(bht_rd_addr_f, UInt<7>("h05d")) @[ifu_bp_ctl.scala 455:79] + node _T_21595 = bits(_T_21594, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21596 = eq(bht_rd_addr_f, UInt<7>("h05e")) @[ifu_bp_ctl.scala 455:79] + node _T_21597 = bits(_T_21596, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21598 = eq(bht_rd_addr_f, UInt<7>("h05f")) @[ifu_bp_ctl.scala 455:79] + node _T_21599 = bits(_T_21598, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21600 = eq(bht_rd_addr_f, UInt<7>("h060")) @[ifu_bp_ctl.scala 455:79] + node _T_21601 = bits(_T_21600, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21602 = eq(bht_rd_addr_f, UInt<7>("h061")) @[ifu_bp_ctl.scala 455:79] + node _T_21603 = bits(_T_21602, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21604 = eq(bht_rd_addr_f, UInt<7>("h062")) @[ifu_bp_ctl.scala 455:79] + node _T_21605 = bits(_T_21604, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21606 = eq(bht_rd_addr_f, UInt<7>("h063")) @[ifu_bp_ctl.scala 455:79] + node _T_21607 = bits(_T_21606, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21608 = eq(bht_rd_addr_f, UInt<7>("h064")) @[ifu_bp_ctl.scala 455:79] + node _T_21609 = bits(_T_21608, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21610 = eq(bht_rd_addr_f, UInt<7>("h065")) @[ifu_bp_ctl.scala 455:79] + node _T_21611 = bits(_T_21610, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21612 = eq(bht_rd_addr_f, UInt<7>("h066")) @[ifu_bp_ctl.scala 455:79] + node _T_21613 = bits(_T_21612, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21614 = eq(bht_rd_addr_f, UInt<7>("h067")) @[ifu_bp_ctl.scala 455:79] + node _T_21615 = bits(_T_21614, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21616 = eq(bht_rd_addr_f, UInt<7>("h068")) @[ifu_bp_ctl.scala 455:79] + node _T_21617 = bits(_T_21616, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21618 = eq(bht_rd_addr_f, UInt<7>("h069")) @[ifu_bp_ctl.scala 455:79] + node _T_21619 = bits(_T_21618, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21620 = eq(bht_rd_addr_f, UInt<7>("h06a")) @[ifu_bp_ctl.scala 455:79] + node _T_21621 = bits(_T_21620, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21622 = eq(bht_rd_addr_f, UInt<7>("h06b")) @[ifu_bp_ctl.scala 455:79] + node _T_21623 = bits(_T_21622, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21624 = eq(bht_rd_addr_f, UInt<7>("h06c")) @[ifu_bp_ctl.scala 455:79] + node _T_21625 = bits(_T_21624, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21626 = eq(bht_rd_addr_f, UInt<7>("h06d")) @[ifu_bp_ctl.scala 455:79] + node _T_21627 = bits(_T_21626, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21628 = eq(bht_rd_addr_f, UInt<7>("h06e")) @[ifu_bp_ctl.scala 455:79] + node _T_21629 = bits(_T_21628, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21630 = eq(bht_rd_addr_f, UInt<7>("h06f")) @[ifu_bp_ctl.scala 455:79] + node _T_21631 = bits(_T_21630, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21632 = eq(bht_rd_addr_f, UInt<7>("h070")) @[ifu_bp_ctl.scala 455:79] + node _T_21633 = bits(_T_21632, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21634 = eq(bht_rd_addr_f, UInt<7>("h071")) @[ifu_bp_ctl.scala 455:79] + node _T_21635 = bits(_T_21634, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21636 = eq(bht_rd_addr_f, UInt<7>("h072")) @[ifu_bp_ctl.scala 455:79] + node _T_21637 = bits(_T_21636, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21638 = eq(bht_rd_addr_f, UInt<7>("h073")) @[ifu_bp_ctl.scala 455:79] + node _T_21639 = bits(_T_21638, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21640 = eq(bht_rd_addr_f, UInt<7>("h074")) @[ifu_bp_ctl.scala 455:79] + node _T_21641 = bits(_T_21640, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21642 = eq(bht_rd_addr_f, UInt<7>("h075")) @[ifu_bp_ctl.scala 455:79] + node _T_21643 = bits(_T_21642, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21644 = eq(bht_rd_addr_f, UInt<7>("h076")) @[ifu_bp_ctl.scala 455:79] + node _T_21645 = bits(_T_21644, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21646 = eq(bht_rd_addr_f, UInt<7>("h077")) @[ifu_bp_ctl.scala 455:79] + node _T_21647 = bits(_T_21646, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21648 = eq(bht_rd_addr_f, UInt<7>("h078")) @[ifu_bp_ctl.scala 455:79] + node _T_21649 = bits(_T_21648, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21650 = eq(bht_rd_addr_f, UInt<7>("h079")) @[ifu_bp_ctl.scala 455:79] + node _T_21651 = bits(_T_21650, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21652 = eq(bht_rd_addr_f, UInt<7>("h07a")) @[ifu_bp_ctl.scala 455:79] + node _T_21653 = bits(_T_21652, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21654 = eq(bht_rd_addr_f, UInt<7>("h07b")) @[ifu_bp_ctl.scala 455:79] + node _T_21655 = bits(_T_21654, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21656 = eq(bht_rd_addr_f, UInt<7>("h07c")) @[ifu_bp_ctl.scala 455:79] + node _T_21657 = bits(_T_21656, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21658 = eq(bht_rd_addr_f, UInt<7>("h07d")) @[ifu_bp_ctl.scala 455:79] + node _T_21659 = bits(_T_21658, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21660 = eq(bht_rd_addr_f, UInt<7>("h07e")) @[ifu_bp_ctl.scala 455:79] + node _T_21661 = bits(_T_21660, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21662 = eq(bht_rd_addr_f, UInt<7>("h07f")) @[ifu_bp_ctl.scala 455:79] + node _T_21663 = bits(_T_21662, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21664 = eq(bht_rd_addr_f, UInt<8>("h080")) @[ifu_bp_ctl.scala 455:79] + node _T_21665 = bits(_T_21664, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21666 = eq(bht_rd_addr_f, UInt<8>("h081")) @[ifu_bp_ctl.scala 455:79] + node _T_21667 = bits(_T_21666, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21668 = eq(bht_rd_addr_f, UInt<8>("h082")) @[ifu_bp_ctl.scala 455:79] + node _T_21669 = bits(_T_21668, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21670 = eq(bht_rd_addr_f, UInt<8>("h083")) @[ifu_bp_ctl.scala 455:79] + node _T_21671 = bits(_T_21670, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21672 = eq(bht_rd_addr_f, UInt<8>("h084")) @[ifu_bp_ctl.scala 455:79] + node _T_21673 = bits(_T_21672, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21674 = eq(bht_rd_addr_f, UInt<8>("h085")) @[ifu_bp_ctl.scala 455:79] + node _T_21675 = bits(_T_21674, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21676 = eq(bht_rd_addr_f, UInt<8>("h086")) @[ifu_bp_ctl.scala 455:79] + node _T_21677 = bits(_T_21676, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21678 = eq(bht_rd_addr_f, UInt<8>("h087")) @[ifu_bp_ctl.scala 455:79] + node _T_21679 = bits(_T_21678, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21680 = eq(bht_rd_addr_f, UInt<8>("h088")) @[ifu_bp_ctl.scala 455:79] + node _T_21681 = bits(_T_21680, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21682 = eq(bht_rd_addr_f, UInt<8>("h089")) @[ifu_bp_ctl.scala 455:79] + node _T_21683 = bits(_T_21682, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21684 = eq(bht_rd_addr_f, UInt<8>("h08a")) @[ifu_bp_ctl.scala 455:79] + node _T_21685 = bits(_T_21684, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21686 = eq(bht_rd_addr_f, UInt<8>("h08b")) @[ifu_bp_ctl.scala 455:79] + node _T_21687 = bits(_T_21686, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21688 = eq(bht_rd_addr_f, UInt<8>("h08c")) @[ifu_bp_ctl.scala 455:79] + node _T_21689 = bits(_T_21688, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21690 = eq(bht_rd_addr_f, UInt<8>("h08d")) @[ifu_bp_ctl.scala 455:79] + node _T_21691 = bits(_T_21690, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21692 = eq(bht_rd_addr_f, UInt<8>("h08e")) @[ifu_bp_ctl.scala 455:79] + node _T_21693 = bits(_T_21692, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21694 = eq(bht_rd_addr_f, UInt<8>("h08f")) @[ifu_bp_ctl.scala 455:79] + node _T_21695 = bits(_T_21694, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21696 = eq(bht_rd_addr_f, UInt<8>("h090")) @[ifu_bp_ctl.scala 455:79] + node _T_21697 = bits(_T_21696, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21698 = eq(bht_rd_addr_f, UInt<8>("h091")) @[ifu_bp_ctl.scala 455:79] + node _T_21699 = bits(_T_21698, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21700 = eq(bht_rd_addr_f, UInt<8>("h092")) @[ifu_bp_ctl.scala 455:79] + node _T_21701 = bits(_T_21700, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21702 = eq(bht_rd_addr_f, UInt<8>("h093")) @[ifu_bp_ctl.scala 455:79] + node _T_21703 = bits(_T_21702, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21704 = eq(bht_rd_addr_f, UInt<8>("h094")) @[ifu_bp_ctl.scala 455:79] + node _T_21705 = bits(_T_21704, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21706 = eq(bht_rd_addr_f, UInt<8>("h095")) @[ifu_bp_ctl.scala 455:79] + node _T_21707 = bits(_T_21706, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21708 = eq(bht_rd_addr_f, UInt<8>("h096")) @[ifu_bp_ctl.scala 455:79] + node _T_21709 = bits(_T_21708, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21710 = eq(bht_rd_addr_f, UInt<8>("h097")) @[ifu_bp_ctl.scala 455:79] + node _T_21711 = bits(_T_21710, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21712 = eq(bht_rd_addr_f, UInt<8>("h098")) @[ifu_bp_ctl.scala 455:79] + node _T_21713 = bits(_T_21712, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21714 = eq(bht_rd_addr_f, UInt<8>("h099")) @[ifu_bp_ctl.scala 455:79] + node _T_21715 = bits(_T_21714, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21716 = eq(bht_rd_addr_f, UInt<8>("h09a")) @[ifu_bp_ctl.scala 455:79] + node _T_21717 = bits(_T_21716, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21718 = eq(bht_rd_addr_f, UInt<8>("h09b")) @[ifu_bp_ctl.scala 455:79] + node _T_21719 = bits(_T_21718, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21720 = eq(bht_rd_addr_f, UInt<8>("h09c")) @[ifu_bp_ctl.scala 455:79] + node _T_21721 = bits(_T_21720, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21722 = eq(bht_rd_addr_f, UInt<8>("h09d")) @[ifu_bp_ctl.scala 455:79] + node _T_21723 = bits(_T_21722, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21724 = eq(bht_rd_addr_f, UInt<8>("h09e")) @[ifu_bp_ctl.scala 455:79] + node _T_21725 = bits(_T_21724, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21726 = eq(bht_rd_addr_f, UInt<8>("h09f")) @[ifu_bp_ctl.scala 455:79] + node _T_21727 = bits(_T_21726, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21728 = eq(bht_rd_addr_f, UInt<8>("h0a0")) @[ifu_bp_ctl.scala 455:79] + node _T_21729 = bits(_T_21728, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21730 = eq(bht_rd_addr_f, UInt<8>("h0a1")) @[ifu_bp_ctl.scala 455:79] + node _T_21731 = bits(_T_21730, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21732 = eq(bht_rd_addr_f, UInt<8>("h0a2")) @[ifu_bp_ctl.scala 455:79] + node _T_21733 = bits(_T_21732, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21734 = eq(bht_rd_addr_f, UInt<8>("h0a3")) @[ifu_bp_ctl.scala 455:79] + node _T_21735 = bits(_T_21734, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21736 = eq(bht_rd_addr_f, UInt<8>("h0a4")) @[ifu_bp_ctl.scala 455:79] + node _T_21737 = bits(_T_21736, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21738 = eq(bht_rd_addr_f, UInt<8>("h0a5")) @[ifu_bp_ctl.scala 455:79] + node _T_21739 = bits(_T_21738, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21740 = eq(bht_rd_addr_f, UInt<8>("h0a6")) @[ifu_bp_ctl.scala 455:79] + node _T_21741 = bits(_T_21740, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21742 = eq(bht_rd_addr_f, UInt<8>("h0a7")) @[ifu_bp_ctl.scala 455:79] + node _T_21743 = bits(_T_21742, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21744 = eq(bht_rd_addr_f, UInt<8>("h0a8")) @[ifu_bp_ctl.scala 455:79] + node _T_21745 = bits(_T_21744, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21746 = eq(bht_rd_addr_f, UInt<8>("h0a9")) @[ifu_bp_ctl.scala 455:79] + node _T_21747 = bits(_T_21746, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21748 = eq(bht_rd_addr_f, UInt<8>("h0aa")) @[ifu_bp_ctl.scala 455:79] + node _T_21749 = bits(_T_21748, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21750 = eq(bht_rd_addr_f, UInt<8>("h0ab")) @[ifu_bp_ctl.scala 455:79] + node _T_21751 = bits(_T_21750, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21752 = eq(bht_rd_addr_f, UInt<8>("h0ac")) @[ifu_bp_ctl.scala 455:79] + node _T_21753 = bits(_T_21752, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21754 = eq(bht_rd_addr_f, UInt<8>("h0ad")) @[ifu_bp_ctl.scala 455:79] + node _T_21755 = bits(_T_21754, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21756 = eq(bht_rd_addr_f, UInt<8>("h0ae")) @[ifu_bp_ctl.scala 455:79] + node _T_21757 = bits(_T_21756, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21758 = eq(bht_rd_addr_f, UInt<8>("h0af")) @[ifu_bp_ctl.scala 455:79] + node _T_21759 = bits(_T_21758, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21760 = eq(bht_rd_addr_f, UInt<8>("h0b0")) @[ifu_bp_ctl.scala 455:79] + node _T_21761 = bits(_T_21760, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21762 = eq(bht_rd_addr_f, UInt<8>("h0b1")) @[ifu_bp_ctl.scala 455:79] + node _T_21763 = bits(_T_21762, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21764 = eq(bht_rd_addr_f, UInt<8>("h0b2")) @[ifu_bp_ctl.scala 455:79] + node _T_21765 = bits(_T_21764, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21766 = eq(bht_rd_addr_f, UInt<8>("h0b3")) @[ifu_bp_ctl.scala 455:79] + node _T_21767 = bits(_T_21766, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21768 = eq(bht_rd_addr_f, UInt<8>("h0b4")) @[ifu_bp_ctl.scala 455:79] + node _T_21769 = bits(_T_21768, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21770 = eq(bht_rd_addr_f, UInt<8>("h0b5")) @[ifu_bp_ctl.scala 455:79] + node _T_21771 = bits(_T_21770, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21772 = eq(bht_rd_addr_f, UInt<8>("h0b6")) @[ifu_bp_ctl.scala 455:79] + node _T_21773 = bits(_T_21772, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21774 = eq(bht_rd_addr_f, UInt<8>("h0b7")) @[ifu_bp_ctl.scala 455:79] + node _T_21775 = bits(_T_21774, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21776 = eq(bht_rd_addr_f, UInt<8>("h0b8")) @[ifu_bp_ctl.scala 455:79] + node _T_21777 = bits(_T_21776, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21778 = eq(bht_rd_addr_f, UInt<8>("h0b9")) @[ifu_bp_ctl.scala 455:79] + node _T_21779 = bits(_T_21778, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21780 = eq(bht_rd_addr_f, UInt<8>("h0ba")) @[ifu_bp_ctl.scala 455:79] + node _T_21781 = bits(_T_21780, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21782 = eq(bht_rd_addr_f, UInt<8>("h0bb")) @[ifu_bp_ctl.scala 455:79] + node _T_21783 = bits(_T_21782, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21784 = eq(bht_rd_addr_f, UInt<8>("h0bc")) @[ifu_bp_ctl.scala 455:79] + node _T_21785 = bits(_T_21784, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21786 = eq(bht_rd_addr_f, UInt<8>("h0bd")) @[ifu_bp_ctl.scala 455:79] + node _T_21787 = bits(_T_21786, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21788 = eq(bht_rd_addr_f, UInt<8>("h0be")) @[ifu_bp_ctl.scala 455:79] + node _T_21789 = bits(_T_21788, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21790 = eq(bht_rd_addr_f, UInt<8>("h0bf")) @[ifu_bp_ctl.scala 455:79] + node _T_21791 = bits(_T_21790, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21792 = eq(bht_rd_addr_f, UInt<8>("h0c0")) @[ifu_bp_ctl.scala 455:79] + node _T_21793 = bits(_T_21792, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21794 = eq(bht_rd_addr_f, UInt<8>("h0c1")) @[ifu_bp_ctl.scala 455:79] + node _T_21795 = bits(_T_21794, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21796 = eq(bht_rd_addr_f, UInt<8>("h0c2")) @[ifu_bp_ctl.scala 455:79] + node _T_21797 = bits(_T_21796, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21798 = eq(bht_rd_addr_f, UInt<8>("h0c3")) @[ifu_bp_ctl.scala 455:79] + node _T_21799 = bits(_T_21798, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21800 = eq(bht_rd_addr_f, UInt<8>("h0c4")) @[ifu_bp_ctl.scala 455:79] + node _T_21801 = bits(_T_21800, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21802 = eq(bht_rd_addr_f, UInt<8>("h0c5")) @[ifu_bp_ctl.scala 455:79] + node _T_21803 = bits(_T_21802, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21804 = eq(bht_rd_addr_f, UInt<8>("h0c6")) @[ifu_bp_ctl.scala 455:79] + node _T_21805 = bits(_T_21804, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21806 = eq(bht_rd_addr_f, UInt<8>("h0c7")) @[ifu_bp_ctl.scala 455:79] + node _T_21807 = bits(_T_21806, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21808 = eq(bht_rd_addr_f, UInt<8>("h0c8")) @[ifu_bp_ctl.scala 455:79] + node _T_21809 = bits(_T_21808, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21810 = eq(bht_rd_addr_f, UInt<8>("h0c9")) @[ifu_bp_ctl.scala 455:79] + node _T_21811 = bits(_T_21810, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21812 = eq(bht_rd_addr_f, UInt<8>("h0ca")) @[ifu_bp_ctl.scala 455:79] + node _T_21813 = bits(_T_21812, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21814 = eq(bht_rd_addr_f, UInt<8>("h0cb")) @[ifu_bp_ctl.scala 455:79] + node _T_21815 = bits(_T_21814, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21816 = eq(bht_rd_addr_f, UInt<8>("h0cc")) @[ifu_bp_ctl.scala 455:79] + node _T_21817 = bits(_T_21816, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21818 = eq(bht_rd_addr_f, UInt<8>("h0cd")) @[ifu_bp_ctl.scala 455:79] + node _T_21819 = bits(_T_21818, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21820 = eq(bht_rd_addr_f, UInt<8>("h0ce")) @[ifu_bp_ctl.scala 455:79] + node _T_21821 = bits(_T_21820, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21822 = eq(bht_rd_addr_f, UInt<8>("h0cf")) @[ifu_bp_ctl.scala 455:79] + node _T_21823 = bits(_T_21822, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21824 = eq(bht_rd_addr_f, UInt<8>("h0d0")) @[ifu_bp_ctl.scala 455:79] + node _T_21825 = bits(_T_21824, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21826 = eq(bht_rd_addr_f, UInt<8>("h0d1")) @[ifu_bp_ctl.scala 455:79] + node _T_21827 = bits(_T_21826, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21828 = eq(bht_rd_addr_f, UInt<8>("h0d2")) @[ifu_bp_ctl.scala 455:79] + node _T_21829 = bits(_T_21828, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21830 = eq(bht_rd_addr_f, UInt<8>("h0d3")) @[ifu_bp_ctl.scala 455:79] + node _T_21831 = bits(_T_21830, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21832 = eq(bht_rd_addr_f, UInt<8>("h0d4")) @[ifu_bp_ctl.scala 455:79] + node _T_21833 = bits(_T_21832, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21834 = eq(bht_rd_addr_f, UInt<8>("h0d5")) @[ifu_bp_ctl.scala 455:79] + node _T_21835 = bits(_T_21834, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21836 = eq(bht_rd_addr_f, UInt<8>("h0d6")) @[ifu_bp_ctl.scala 455:79] + node _T_21837 = bits(_T_21836, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21838 = eq(bht_rd_addr_f, UInt<8>("h0d7")) @[ifu_bp_ctl.scala 455:79] + node _T_21839 = bits(_T_21838, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21840 = eq(bht_rd_addr_f, UInt<8>("h0d8")) @[ifu_bp_ctl.scala 455:79] + node _T_21841 = bits(_T_21840, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21842 = eq(bht_rd_addr_f, UInt<8>("h0d9")) @[ifu_bp_ctl.scala 455:79] + node _T_21843 = bits(_T_21842, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21844 = eq(bht_rd_addr_f, UInt<8>("h0da")) @[ifu_bp_ctl.scala 455:79] + node _T_21845 = bits(_T_21844, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21846 = eq(bht_rd_addr_f, UInt<8>("h0db")) @[ifu_bp_ctl.scala 455:79] + node _T_21847 = bits(_T_21846, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21848 = eq(bht_rd_addr_f, UInt<8>("h0dc")) @[ifu_bp_ctl.scala 455:79] + node _T_21849 = bits(_T_21848, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21850 = eq(bht_rd_addr_f, UInt<8>("h0dd")) @[ifu_bp_ctl.scala 455:79] + node _T_21851 = bits(_T_21850, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21852 = eq(bht_rd_addr_f, UInt<8>("h0de")) @[ifu_bp_ctl.scala 455:79] + node _T_21853 = bits(_T_21852, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21854 = eq(bht_rd_addr_f, UInt<8>("h0df")) @[ifu_bp_ctl.scala 455:79] + node _T_21855 = bits(_T_21854, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21856 = eq(bht_rd_addr_f, UInt<8>("h0e0")) @[ifu_bp_ctl.scala 455:79] + node _T_21857 = bits(_T_21856, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21858 = eq(bht_rd_addr_f, UInt<8>("h0e1")) @[ifu_bp_ctl.scala 455:79] + node _T_21859 = bits(_T_21858, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21860 = eq(bht_rd_addr_f, UInt<8>("h0e2")) @[ifu_bp_ctl.scala 455:79] + node _T_21861 = bits(_T_21860, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21862 = eq(bht_rd_addr_f, UInt<8>("h0e3")) @[ifu_bp_ctl.scala 455:79] + node _T_21863 = bits(_T_21862, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21864 = eq(bht_rd_addr_f, UInt<8>("h0e4")) @[ifu_bp_ctl.scala 455:79] + node _T_21865 = bits(_T_21864, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21866 = eq(bht_rd_addr_f, UInt<8>("h0e5")) @[ifu_bp_ctl.scala 455:79] + node _T_21867 = bits(_T_21866, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21868 = eq(bht_rd_addr_f, UInt<8>("h0e6")) @[ifu_bp_ctl.scala 455:79] + node _T_21869 = bits(_T_21868, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21870 = eq(bht_rd_addr_f, UInt<8>("h0e7")) @[ifu_bp_ctl.scala 455:79] + node _T_21871 = bits(_T_21870, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21872 = eq(bht_rd_addr_f, UInt<8>("h0e8")) @[ifu_bp_ctl.scala 455:79] + node _T_21873 = bits(_T_21872, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21874 = eq(bht_rd_addr_f, UInt<8>("h0e9")) @[ifu_bp_ctl.scala 455:79] + node _T_21875 = bits(_T_21874, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21876 = eq(bht_rd_addr_f, UInt<8>("h0ea")) @[ifu_bp_ctl.scala 455:79] + node _T_21877 = bits(_T_21876, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21878 = eq(bht_rd_addr_f, UInt<8>("h0eb")) @[ifu_bp_ctl.scala 455:79] + node _T_21879 = bits(_T_21878, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21880 = eq(bht_rd_addr_f, UInt<8>("h0ec")) @[ifu_bp_ctl.scala 455:79] + node _T_21881 = bits(_T_21880, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21882 = eq(bht_rd_addr_f, UInt<8>("h0ed")) @[ifu_bp_ctl.scala 455:79] + node _T_21883 = bits(_T_21882, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21884 = eq(bht_rd_addr_f, UInt<8>("h0ee")) @[ifu_bp_ctl.scala 455:79] + node _T_21885 = bits(_T_21884, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21886 = eq(bht_rd_addr_f, UInt<8>("h0ef")) @[ifu_bp_ctl.scala 455:79] + node _T_21887 = bits(_T_21886, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21888 = eq(bht_rd_addr_f, UInt<8>("h0f0")) @[ifu_bp_ctl.scala 455:79] + node _T_21889 = bits(_T_21888, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21890 = eq(bht_rd_addr_f, UInt<8>("h0f1")) @[ifu_bp_ctl.scala 455:79] + node _T_21891 = bits(_T_21890, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21892 = eq(bht_rd_addr_f, UInt<8>("h0f2")) @[ifu_bp_ctl.scala 455:79] + node _T_21893 = bits(_T_21892, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21894 = eq(bht_rd_addr_f, UInt<8>("h0f3")) @[ifu_bp_ctl.scala 455:79] + node _T_21895 = bits(_T_21894, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21896 = eq(bht_rd_addr_f, UInt<8>("h0f4")) @[ifu_bp_ctl.scala 455:79] + node _T_21897 = bits(_T_21896, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21898 = eq(bht_rd_addr_f, UInt<8>("h0f5")) @[ifu_bp_ctl.scala 455:79] + node _T_21899 = bits(_T_21898, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21900 = eq(bht_rd_addr_f, UInt<8>("h0f6")) @[ifu_bp_ctl.scala 455:79] + node _T_21901 = bits(_T_21900, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21902 = eq(bht_rd_addr_f, UInt<8>("h0f7")) @[ifu_bp_ctl.scala 455:79] + node _T_21903 = bits(_T_21902, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21904 = eq(bht_rd_addr_f, UInt<8>("h0f8")) @[ifu_bp_ctl.scala 455:79] + node _T_21905 = bits(_T_21904, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21906 = eq(bht_rd_addr_f, UInt<8>("h0f9")) @[ifu_bp_ctl.scala 455:79] + node _T_21907 = bits(_T_21906, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21908 = eq(bht_rd_addr_f, UInt<8>("h0fa")) @[ifu_bp_ctl.scala 455:79] + node _T_21909 = bits(_T_21908, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21910 = eq(bht_rd_addr_f, UInt<8>("h0fb")) @[ifu_bp_ctl.scala 455:79] + node _T_21911 = bits(_T_21910, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21912 = eq(bht_rd_addr_f, UInt<8>("h0fc")) @[ifu_bp_ctl.scala 455:79] + node _T_21913 = bits(_T_21912, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21914 = eq(bht_rd_addr_f, UInt<8>("h0fd")) @[ifu_bp_ctl.scala 455:79] + node _T_21915 = bits(_T_21914, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21916 = eq(bht_rd_addr_f, UInt<8>("h0fe")) @[ifu_bp_ctl.scala 455:79] + node _T_21917 = bits(_T_21916, 0, 0) @[ifu_bp_ctl.scala 455:87] + node _T_21918 = eq(bht_rd_addr_f, UInt<8>("h0ff")) @[ifu_bp_ctl.scala 455:79] + node _T_21919 = bits(_T_21918, 0, 0) @[ifu_bp_ctl.scala 455:87] node _T_21920 = mux(_T_21409, bht_bank_rd_data_out[1][0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_21921 = mux(_T_21411, bht_bank_rd_data_out[1][1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_21922 = mux(_T_21413, bht_bank_rd_data_out[1][2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -59224,519 +59224,519 @@ circuit quasar_wrapper : node _T_22430 = or(_T_22429, _T_22175) @[Mux.scala 27:72] wire _T_22431 : UInt<2> @[Mux.scala 27:72] _T_22431 <= _T_22430 @[Mux.scala 27:72] - bht_bank1_rd_data_f <= _T_22431 @[ifu_bp_ctl.scala 454:23] - node _T_22432 = eq(bht_rd_addr_hashed_p1_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 455:85] - node _T_22433 = bits(_T_22432, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22434 = eq(bht_rd_addr_hashed_p1_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 455:85] - node _T_22435 = bits(_T_22434, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22436 = eq(bht_rd_addr_hashed_p1_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 455:85] - node _T_22437 = bits(_T_22436, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22438 = eq(bht_rd_addr_hashed_p1_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 455:85] - node _T_22439 = bits(_T_22438, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22440 = eq(bht_rd_addr_hashed_p1_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 455:85] - node _T_22441 = bits(_T_22440, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22442 = eq(bht_rd_addr_hashed_p1_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 455:85] - node _T_22443 = bits(_T_22442, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22444 = eq(bht_rd_addr_hashed_p1_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 455:85] - node _T_22445 = bits(_T_22444, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22446 = eq(bht_rd_addr_hashed_p1_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 455:85] - node _T_22447 = bits(_T_22446, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22448 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 455:85] - node _T_22449 = bits(_T_22448, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22450 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 455:85] - node _T_22451 = bits(_T_22450, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22452 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 455:85] - node _T_22453 = bits(_T_22452, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22454 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 455:85] - node _T_22455 = bits(_T_22454, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22456 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 455:85] - node _T_22457 = bits(_T_22456, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22458 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 455:85] - node _T_22459 = bits(_T_22458, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22460 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 455:85] - node _T_22461 = bits(_T_22460, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22462 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 455:85] - node _T_22463 = bits(_T_22462, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22464 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h010")) @[ifu_bp_ctl.scala 455:85] - node _T_22465 = bits(_T_22464, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22466 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h011")) @[ifu_bp_ctl.scala 455:85] - node _T_22467 = bits(_T_22466, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22468 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h012")) @[ifu_bp_ctl.scala 455:85] - node _T_22469 = bits(_T_22468, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22470 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h013")) @[ifu_bp_ctl.scala 455:85] - node _T_22471 = bits(_T_22470, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22472 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h014")) @[ifu_bp_ctl.scala 455:85] - node _T_22473 = bits(_T_22472, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22474 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h015")) @[ifu_bp_ctl.scala 455:85] - node _T_22475 = bits(_T_22474, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22476 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h016")) @[ifu_bp_ctl.scala 455:85] - node _T_22477 = bits(_T_22476, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22478 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h017")) @[ifu_bp_ctl.scala 455:85] - node _T_22479 = bits(_T_22478, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22480 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h018")) @[ifu_bp_ctl.scala 455:85] - node _T_22481 = bits(_T_22480, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22482 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h019")) @[ifu_bp_ctl.scala 455:85] - node _T_22483 = bits(_T_22482, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22484 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h01a")) @[ifu_bp_ctl.scala 455:85] - node _T_22485 = bits(_T_22484, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22486 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h01b")) @[ifu_bp_ctl.scala 455:85] - node _T_22487 = bits(_T_22486, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22488 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h01c")) @[ifu_bp_ctl.scala 455:85] - node _T_22489 = bits(_T_22488, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22490 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h01d")) @[ifu_bp_ctl.scala 455:85] - node _T_22491 = bits(_T_22490, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22492 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h01e")) @[ifu_bp_ctl.scala 455:85] - node _T_22493 = bits(_T_22492, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22494 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h01f")) @[ifu_bp_ctl.scala 455:85] - node _T_22495 = bits(_T_22494, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22496 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h020")) @[ifu_bp_ctl.scala 455:85] - node _T_22497 = bits(_T_22496, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22498 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h021")) @[ifu_bp_ctl.scala 455:85] - node _T_22499 = bits(_T_22498, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22500 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h022")) @[ifu_bp_ctl.scala 455:85] - node _T_22501 = bits(_T_22500, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22502 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h023")) @[ifu_bp_ctl.scala 455:85] - node _T_22503 = bits(_T_22502, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22504 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h024")) @[ifu_bp_ctl.scala 455:85] - node _T_22505 = bits(_T_22504, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22506 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h025")) @[ifu_bp_ctl.scala 455:85] - node _T_22507 = bits(_T_22506, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22508 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h026")) @[ifu_bp_ctl.scala 455:85] - node _T_22509 = bits(_T_22508, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22510 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h027")) @[ifu_bp_ctl.scala 455:85] - node _T_22511 = bits(_T_22510, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22512 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h028")) @[ifu_bp_ctl.scala 455:85] - node _T_22513 = bits(_T_22512, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22514 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h029")) @[ifu_bp_ctl.scala 455:85] - node _T_22515 = bits(_T_22514, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22516 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h02a")) @[ifu_bp_ctl.scala 455:85] - node _T_22517 = bits(_T_22516, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22518 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h02b")) @[ifu_bp_ctl.scala 455:85] - node _T_22519 = bits(_T_22518, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22520 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h02c")) @[ifu_bp_ctl.scala 455:85] - node _T_22521 = bits(_T_22520, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22522 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h02d")) @[ifu_bp_ctl.scala 455:85] - node _T_22523 = bits(_T_22522, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22524 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h02e")) @[ifu_bp_ctl.scala 455:85] - node _T_22525 = bits(_T_22524, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22526 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h02f")) @[ifu_bp_ctl.scala 455:85] - node _T_22527 = bits(_T_22526, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22528 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h030")) @[ifu_bp_ctl.scala 455:85] - node _T_22529 = bits(_T_22528, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22530 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h031")) @[ifu_bp_ctl.scala 455:85] - node _T_22531 = bits(_T_22530, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22532 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h032")) @[ifu_bp_ctl.scala 455:85] - node _T_22533 = bits(_T_22532, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22534 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h033")) @[ifu_bp_ctl.scala 455:85] - node _T_22535 = bits(_T_22534, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22536 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h034")) @[ifu_bp_ctl.scala 455:85] - node _T_22537 = bits(_T_22536, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22538 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h035")) @[ifu_bp_ctl.scala 455:85] - node _T_22539 = bits(_T_22538, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22540 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h036")) @[ifu_bp_ctl.scala 455:85] - node _T_22541 = bits(_T_22540, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22542 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h037")) @[ifu_bp_ctl.scala 455:85] - node _T_22543 = bits(_T_22542, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22544 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h038")) @[ifu_bp_ctl.scala 455:85] - node _T_22545 = bits(_T_22544, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22546 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h039")) @[ifu_bp_ctl.scala 455:85] - node _T_22547 = bits(_T_22546, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22548 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h03a")) @[ifu_bp_ctl.scala 455:85] - node _T_22549 = bits(_T_22548, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22550 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h03b")) @[ifu_bp_ctl.scala 455:85] - node _T_22551 = bits(_T_22550, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22552 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h03c")) @[ifu_bp_ctl.scala 455:85] - node _T_22553 = bits(_T_22552, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22554 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h03d")) @[ifu_bp_ctl.scala 455:85] - node _T_22555 = bits(_T_22554, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22556 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h03e")) @[ifu_bp_ctl.scala 455:85] - node _T_22557 = bits(_T_22556, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22558 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h03f")) @[ifu_bp_ctl.scala 455:85] - node _T_22559 = bits(_T_22558, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22560 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h040")) @[ifu_bp_ctl.scala 455:85] - node _T_22561 = bits(_T_22560, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22562 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h041")) @[ifu_bp_ctl.scala 455:85] - node _T_22563 = bits(_T_22562, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22564 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h042")) @[ifu_bp_ctl.scala 455:85] - node _T_22565 = bits(_T_22564, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22566 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h043")) @[ifu_bp_ctl.scala 455:85] - node _T_22567 = bits(_T_22566, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22568 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h044")) @[ifu_bp_ctl.scala 455:85] - node _T_22569 = bits(_T_22568, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22570 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h045")) @[ifu_bp_ctl.scala 455:85] - node _T_22571 = bits(_T_22570, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22572 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h046")) @[ifu_bp_ctl.scala 455:85] - node _T_22573 = bits(_T_22572, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22574 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h047")) @[ifu_bp_ctl.scala 455:85] - node _T_22575 = bits(_T_22574, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22576 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h048")) @[ifu_bp_ctl.scala 455:85] - node _T_22577 = bits(_T_22576, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22578 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h049")) @[ifu_bp_ctl.scala 455:85] - node _T_22579 = bits(_T_22578, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22580 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h04a")) @[ifu_bp_ctl.scala 455:85] - node _T_22581 = bits(_T_22580, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22582 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h04b")) @[ifu_bp_ctl.scala 455:85] - node _T_22583 = bits(_T_22582, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22584 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h04c")) @[ifu_bp_ctl.scala 455:85] - node _T_22585 = bits(_T_22584, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22586 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h04d")) @[ifu_bp_ctl.scala 455:85] - node _T_22587 = bits(_T_22586, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22588 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h04e")) @[ifu_bp_ctl.scala 455:85] - node _T_22589 = bits(_T_22588, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22590 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h04f")) @[ifu_bp_ctl.scala 455:85] - node _T_22591 = bits(_T_22590, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22592 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h050")) @[ifu_bp_ctl.scala 455:85] - node _T_22593 = bits(_T_22592, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22594 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h051")) @[ifu_bp_ctl.scala 455:85] - node _T_22595 = bits(_T_22594, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22596 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h052")) @[ifu_bp_ctl.scala 455:85] - node _T_22597 = bits(_T_22596, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22598 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h053")) @[ifu_bp_ctl.scala 455:85] - node _T_22599 = bits(_T_22598, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22600 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h054")) @[ifu_bp_ctl.scala 455:85] - node _T_22601 = bits(_T_22600, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22602 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h055")) @[ifu_bp_ctl.scala 455:85] - node _T_22603 = bits(_T_22602, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22604 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h056")) @[ifu_bp_ctl.scala 455:85] - node _T_22605 = bits(_T_22604, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22606 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h057")) @[ifu_bp_ctl.scala 455:85] - node _T_22607 = bits(_T_22606, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22608 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h058")) @[ifu_bp_ctl.scala 455:85] - node _T_22609 = bits(_T_22608, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22610 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h059")) @[ifu_bp_ctl.scala 455:85] - node _T_22611 = bits(_T_22610, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22612 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h05a")) @[ifu_bp_ctl.scala 455:85] - node _T_22613 = bits(_T_22612, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22614 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h05b")) @[ifu_bp_ctl.scala 455:85] - node _T_22615 = bits(_T_22614, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22616 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h05c")) @[ifu_bp_ctl.scala 455:85] - node _T_22617 = bits(_T_22616, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22618 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h05d")) @[ifu_bp_ctl.scala 455:85] - node _T_22619 = bits(_T_22618, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22620 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h05e")) @[ifu_bp_ctl.scala 455:85] - node _T_22621 = bits(_T_22620, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22622 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h05f")) @[ifu_bp_ctl.scala 455:85] - node _T_22623 = bits(_T_22622, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22624 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h060")) @[ifu_bp_ctl.scala 455:85] - node _T_22625 = bits(_T_22624, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22626 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h061")) @[ifu_bp_ctl.scala 455:85] - node _T_22627 = bits(_T_22626, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22628 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h062")) @[ifu_bp_ctl.scala 455:85] - node _T_22629 = bits(_T_22628, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22630 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h063")) @[ifu_bp_ctl.scala 455:85] - node _T_22631 = bits(_T_22630, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22632 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h064")) @[ifu_bp_ctl.scala 455:85] - node _T_22633 = bits(_T_22632, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22634 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h065")) @[ifu_bp_ctl.scala 455:85] - node _T_22635 = bits(_T_22634, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22636 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h066")) @[ifu_bp_ctl.scala 455:85] - node _T_22637 = bits(_T_22636, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22638 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h067")) @[ifu_bp_ctl.scala 455:85] - node _T_22639 = bits(_T_22638, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22640 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h068")) @[ifu_bp_ctl.scala 455:85] - node _T_22641 = bits(_T_22640, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22642 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h069")) @[ifu_bp_ctl.scala 455:85] - node _T_22643 = bits(_T_22642, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22644 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h06a")) @[ifu_bp_ctl.scala 455:85] - node _T_22645 = bits(_T_22644, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22646 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h06b")) @[ifu_bp_ctl.scala 455:85] - node _T_22647 = bits(_T_22646, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22648 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h06c")) @[ifu_bp_ctl.scala 455:85] - node _T_22649 = bits(_T_22648, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22650 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h06d")) @[ifu_bp_ctl.scala 455:85] - node _T_22651 = bits(_T_22650, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22652 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h06e")) @[ifu_bp_ctl.scala 455:85] - node _T_22653 = bits(_T_22652, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22654 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h06f")) @[ifu_bp_ctl.scala 455:85] - node _T_22655 = bits(_T_22654, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22656 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h070")) @[ifu_bp_ctl.scala 455:85] - node _T_22657 = bits(_T_22656, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22658 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h071")) @[ifu_bp_ctl.scala 455:85] - node _T_22659 = bits(_T_22658, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22660 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h072")) @[ifu_bp_ctl.scala 455:85] - node _T_22661 = bits(_T_22660, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22662 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h073")) @[ifu_bp_ctl.scala 455:85] - node _T_22663 = bits(_T_22662, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22664 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h074")) @[ifu_bp_ctl.scala 455:85] - node _T_22665 = bits(_T_22664, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22666 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h075")) @[ifu_bp_ctl.scala 455:85] - node _T_22667 = bits(_T_22666, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22668 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h076")) @[ifu_bp_ctl.scala 455:85] - node _T_22669 = bits(_T_22668, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22670 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h077")) @[ifu_bp_ctl.scala 455:85] - node _T_22671 = bits(_T_22670, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22672 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h078")) @[ifu_bp_ctl.scala 455:85] - node _T_22673 = bits(_T_22672, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22674 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h079")) @[ifu_bp_ctl.scala 455:85] - node _T_22675 = bits(_T_22674, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22676 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h07a")) @[ifu_bp_ctl.scala 455:85] - node _T_22677 = bits(_T_22676, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22678 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h07b")) @[ifu_bp_ctl.scala 455:85] - node _T_22679 = bits(_T_22678, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22680 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h07c")) @[ifu_bp_ctl.scala 455:85] - node _T_22681 = bits(_T_22680, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22682 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h07d")) @[ifu_bp_ctl.scala 455:85] - node _T_22683 = bits(_T_22682, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22684 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h07e")) @[ifu_bp_ctl.scala 455:85] - node _T_22685 = bits(_T_22684, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22686 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h07f")) @[ifu_bp_ctl.scala 455:85] - node _T_22687 = bits(_T_22686, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22688 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h080")) @[ifu_bp_ctl.scala 455:85] - node _T_22689 = bits(_T_22688, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22690 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h081")) @[ifu_bp_ctl.scala 455:85] - node _T_22691 = bits(_T_22690, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22692 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h082")) @[ifu_bp_ctl.scala 455:85] - node _T_22693 = bits(_T_22692, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22694 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h083")) @[ifu_bp_ctl.scala 455:85] - node _T_22695 = bits(_T_22694, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22696 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h084")) @[ifu_bp_ctl.scala 455:85] - node _T_22697 = bits(_T_22696, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22698 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h085")) @[ifu_bp_ctl.scala 455:85] - node _T_22699 = bits(_T_22698, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22700 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h086")) @[ifu_bp_ctl.scala 455:85] - node _T_22701 = bits(_T_22700, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22702 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h087")) @[ifu_bp_ctl.scala 455:85] - node _T_22703 = bits(_T_22702, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22704 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h088")) @[ifu_bp_ctl.scala 455:85] - node _T_22705 = bits(_T_22704, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22706 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h089")) @[ifu_bp_ctl.scala 455:85] - node _T_22707 = bits(_T_22706, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22708 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h08a")) @[ifu_bp_ctl.scala 455:85] - node _T_22709 = bits(_T_22708, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22710 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h08b")) @[ifu_bp_ctl.scala 455:85] - node _T_22711 = bits(_T_22710, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22712 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h08c")) @[ifu_bp_ctl.scala 455:85] - node _T_22713 = bits(_T_22712, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22714 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h08d")) @[ifu_bp_ctl.scala 455:85] - node _T_22715 = bits(_T_22714, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22716 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h08e")) @[ifu_bp_ctl.scala 455:85] - node _T_22717 = bits(_T_22716, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22718 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h08f")) @[ifu_bp_ctl.scala 455:85] - node _T_22719 = bits(_T_22718, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22720 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h090")) @[ifu_bp_ctl.scala 455:85] - node _T_22721 = bits(_T_22720, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22722 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h091")) @[ifu_bp_ctl.scala 455:85] - node _T_22723 = bits(_T_22722, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22724 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h092")) @[ifu_bp_ctl.scala 455:85] - node _T_22725 = bits(_T_22724, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22726 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h093")) @[ifu_bp_ctl.scala 455:85] - node _T_22727 = bits(_T_22726, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22728 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h094")) @[ifu_bp_ctl.scala 455:85] - node _T_22729 = bits(_T_22728, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22730 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h095")) @[ifu_bp_ctl.scala 455:85] - node _T_22731 = bits(_T_22730, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22732 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h096")) @[ifu_bp_ctl.scala 455:85] - node _T_22733 = bits(_T_22732, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22734 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h097")) @[ifu_bp_ctl.scala 455:85] - node _T_22735 = bits(_T_22734, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22736 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h098")) @[ifu_bp_ctl.scala 455:85] - node _T_22737 = bits(_T_22736, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22738 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h099")) @[ifu_bp_ctl.scala 455:85] - node _T_22739 = bits(_T_22738, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22740 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h09a")) @[ifu_bp_ctl.scala 455:85] - node _T_22741 = bits(_T_22740, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22742 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h09b")) @[ifu_bp_ctl.scala 455:85] - node _T_22743 = bits(_T_22742, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22744 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h09c")) @[ifu_bp_ctl.scala 455:85] - node _T_22745 = bits(_T_22744, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22746 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h09d")) @[ifu_bp_ctl.scala 455:85] - node _T_22747 = bits(_T_22746, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22748 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h09e")) @[ifu_bp_ctl.scala 455:85] - node _T_22749 = bits(_T_22748, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22750 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h09f")) @[ifu_bp_ctl.scala 455:85] - node _T_22751 = bits(_T_22750, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22752 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0a0")) @[ifu_bp_ctl.scala 455:85] - node _T_22753 = bits(_T_22752, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22754 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0a1")) @[ifu_bp_ctl.scala 455:85] - node _T_22755 = bits(_T_22754, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22756 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0a2")) @[ifu_bp_ctl.scala 455:85] - node _T_22757 = bits(_T_22756, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22758 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0a3")) @[ifu_bp_ctl.scala 455:85] - node _T_22759 = bits(_T_22758, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22760 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0a4")) @[ifu_bp_ctl.scala 455:85] - node _T_22761 = bits(_T_22760, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22762 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0a5")) @[ifu_bp_ctl.scala 455:85] - node _T_22763 = bits(_T_22762, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22764 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0a6")) @[ifu_bp_ctl.scala 455:85] - node _T_22765 = bits(_T_22764, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22766 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0a7")) @[ifu_bp_ctl.scala 455:85] - node _T_22767 = bits(_T_22766, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22768 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0a8")) @[ifu_bp_ctl.scala 455:85] - node _T_22769 = bits(_T_22768, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22770 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0a9")) @[ifu_bp_ctl.scala 455:85] - node _T_22771 = bits(_T_22770, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22772 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0aa")) @[ifu_bp_ctl.scala 455:85] - node _T_22773 = bits(_T_22772, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22774 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ab")) @[ifu_bp_ctl.scala 455:85] - node _T_22775 = bits(_T_22774, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22776 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ac")) @[ifu_bp_ctl.scala 455:85] - node _T_22777 = bits(_T_22776, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22778 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ad")) @[ifu_bp_ctl.scala 455:85] - node _T_22779 = bits(_T_22778, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22780 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ae")) @[ifu_bp_ctl.scala 455:85] - node _T_22781 = bits(_T_22780, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22782 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0af")) @[ifu_bp_ctl.scala 455:85] - node _T_22783 = bits(_T_22782, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22784 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0b0")) @[ifu_bp_ctl.scala 455:85] - node _T_22785 = bits(_T_22784, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22786 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0b1")) @[ifu_bp_ctl.scala 455:85] - node _T_22787 = bits(_T_22786, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22788 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0b2")) @[ifu_bp_ctl.scala 455:85] - node _T_22789 = bits(_T_22788, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22790 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0b3")) @[ifu_bp_ctl.scala 455:85] - node _T_22791 = bits(_T_22790, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22792 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0b4")) @[ifu_bp_ctl.scala 455:85] - node _T_22793 = bits(_T_22792, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22794 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0b5")) @[ifu_bp_ctl.scala 455:85] - node _T_22795 = bits(_T_22794, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22796 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0b6")) @[ifu_bp_ctl.scala 455:85] - node _T_22797 = bits(_T_22796, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22798 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0b7")) @[ifu_bp_ctl.scala 455:85] - node _T_22799 = bits(_T_22798, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22800 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0b8")) @[ifu_bp_ctl.scala 455:85] - node _T_22801 = bits(_T_22800, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22802 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0b9")) @[ifu_bp_ctl.scala 455:85] - node _T_22803 = bits(_T_22802, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22804 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ba")) @[ifu_bp_ctl.scala 455:85] - node _T_22805 = bits(_T_22804, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22806 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0bb")) @[ifu_bp_ctl.scala 455:85] - node _T_22807 = bits(_T_22806, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22808 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0bc")) @[ifu_bp_ctl.scala 455:85] - node _T_22809 = bits(_T_22808, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22810 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0bd")) @[ifu_bp_ctl.scala 455:85] - node _T_22811 = bits(_T_22810, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22812 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0be")) @[ifu_bp_ctl.scala 455:85] - node _T_22813 = bits(_T_22812, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22814 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0bf")) @[ifu_bp_ctl.scala 455:85] - node _T_22815 = bits(_T_22814, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22816 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0c0")) @[ifu_bp_ctl.scala 455:85] - node _T_22817 = bits(_T_22816, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22818 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0c1")) @[ifu_bp_ctl.scala 455:85] - node _T_22819 = bits(_T_22818, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22820 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0c2")) @[ifu_bp_ctl.scala 455:85] - node _T_22821 = bits(_T_22820, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22822 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0c3")) @[ifu_bp_ctl.scala 455:85] - node _T_22823 = bits(_T_22822, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22824 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0c4")) @[ifu_bp_ctl.scala 455:85] - node _T_22825 = bits(_T_22824, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22826 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0c5")) @[ifu_bp_ctl.scala 455:85] - node _T_22827 = bits(_T_22826, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22828 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0c6")) @[ifu_bp_ctl.scala 455:85] - node _T_22829 = bits(_T_22828, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22830 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0c7")) @[ifu_bp_ctl.scala 455:85] - node _T_22831 = bits(_T_22830, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22832 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0c8")) @[ifu_bp_ctl.scala 455:85] - node _T_22833 = bits(_T_22832, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22834 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0c9")) @[ifu_bp_ctl.scala 455:85] - node _T_22835 = bits(_T_22834, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22836 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ca")) @[ifu_bp_ctl.scala 455:85] - node _T_22837 = bits(_T_22836, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22838 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0cb")) @[ifu_bp_ctl.scala 455:85] - node _T_22839 = bits(_T_22838, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22840 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0cc")) @[ifu_bp_ctl.scala 455:85] - node _T_22841 = bits(_T_22840, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22842 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0cd")) @[ifu_bp_ctl.scala 455:85] - node _T_22843 = bits(_T_22842, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22844 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ce")) @[ifu_bp_ctl.scala 455:85] - node _T_22845 = bits(_T_22844, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22846 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0cf")) @[ifu_bp_ctl.scala 455:85] - node _T_22847 = bits(_T_22846, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22848 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0d0")) @[ifu_bp_ctl.scala 455:85] - node _T_22849 = bits(_T_22848, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22850 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0d1")) @[ifu_bp_ctl.scala 455:85] - node _T_22851 = bits(_T_22850, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22852 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0d2")) @[ifu_bp_ctl.scala 455:85] - node _T_22853 = bits(_T_22852, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22854 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0d3")) @[ifu_bp_ctl.scala 455:85] - node _T_22855 = bits(_T_22854, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22856 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0d4")) @[ifu_bp_ctl.scala 455:85] - node _T_22857 = bits(_T_22856, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22858 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0d5")) @[ifu_bp_ctl.scala 455:85] - node _T_22859 = bits(_T_22858, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22860 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0d6")) @[ifu_bp_ctl.scala 455:85] - node _T_22861 = bits(_T_22860, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22862 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0d7")) @[ifu_bp_ctl.scala 455:85] - node _T_22863 = bits(_T_22862, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22864 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0d8")) @[ifu_bp_ctl.scala 455:85] - node _T_22865 = bits(_T_22864, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22866 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0d9")) @[ifu_bp_ctl.scala 455:85] - node _T_22867 = bits(_T_22866, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22868 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0da")) @[ifu_bp_ctl.scala 455:85] - node _T_22869 = bits(_T_22868, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22870 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0db")) @[ifu_bp_ctl.scala 455:85] - node _T_22871 = bits(_T_22870, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22872 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0dc")) @[ifu_bp_ctl.scala 455:85] - node _T_22873 = bits(_T_22872, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22874 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0dd")) @[ifu_bp_ctl.scala 455:85] - node _T_22875 = bits(_T_22874, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22876 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0de")) @[ifu_bp_ctl.scala 455:85] - node _T_22877 = bits(_T_22876, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22878 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0df")) @[ifu_bp_ctl.scala 455:85] - node _T_22879 = bits(_T_22878, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22880 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0e0")) @[ifu_bp_ctl.scala 455:85] - node _T_22881 = bits(_T_22880, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22882 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0e1")) @[ifu_bp_ctl.scala 455:85] - node _T_22883 = bits(_T_22882, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22884 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0e2")) @[ifu_bp_ctl.scala 455:85] - node _T_22885 = bits(_T_22884, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22886 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0e3")) @[ifu_bp_ctl.scala 455:85] - node _T_22887 = bits(_T_22886, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22888 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0e4")) @[ifu_bp_ctl.scala 455:85] - node _T_22889 = bits(_T_22888, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22890 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0e5")) @[ifu_bp_ctl.scala 455:85] - node _T_22891 = bits(_T_22890, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22892 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0e6")) @[ifu_bp_ctl.scala 455:85] - node _T_22893 = bits(_T_22892, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22894 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0e7")) @[ifu_bp_ctl.scala 455:85] - node _T_22895 = bits(_T_22894, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22896 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0e8")) @[ifu_bp_ctl.scala 455:85] - node _T_22897 = bits(_T_22896, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22898 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0e9")) @[ifu_bp_ctl.scala 455:85] - node _T_22899 = bits(_T_22898, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22900 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ea")) @[ifu_bp_ctl.scala 455:85] - node _T_22901 = bits(_T_22900, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22902 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0eb")) @[ifu_bp_ctl.scala 455:85] - node _T_22903 = bits(_T_22902, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22904 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ec")) @[ifu_bp_ctl.scala 455:85] - node _T_22905 = bits(_T_22904, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22906 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ed")) @[ifu_bp_ctl.scala 455:85] - node _T_22907 = bits(_T_22906, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22908 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ee")) @[ifu_bp_ctl.scala 455:85] - node _T_22909 = bits(_T_22908, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22910 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ef")) @[ifu_bp_ctl.scala 455:85] - node _T_22911 = bits(_T_22910, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22912 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0f0")) @[ifu_bp_ctl.scala 455:85] - node _T_22913 = bits(_T_22912, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22914 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0f1")) @[ifu_bp_ctl.scala 455:85] - node _T_22915 = bits(_T_22914, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22916 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0f2")) @[ifu_bp_ctl.scala 455:85] - node _T_22917 = bits(_T_22916, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22918 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0f3")) @[ifu_bp_ctl.scala 455:85] - node _T_22919 = bits(_T_22918, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22920 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0f4")) @[ifu_bp_ctl.scala 455:85] - node _T_22921 = bits(_T_22920, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22922 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0f5")) @[ifu_bp_ctl.scala 455:85] - node _T_22923 = bits(_T_22922, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22924 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0f6")) @[ifu_bp_ctl.scala 455:85] - node _T_22925 = bits(_T_22924, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22926 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0f7")) @[ifu_bp_ctl.scala 455:85] - node _T_22927 = bits(_T_22926, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22928 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0f8")) @[ifu_bp_ctl.scala 455:85] - node _T_22929 = bits(_T_22928, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22930 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0f9")) @[ifu_bp_ctl.scala 455:85] - node _T_22931 = bits(_T_22930, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22932 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0fa")) @[ifu_bp_ctl.scala 455:85] - node _T_22933 = bits(_T_22932, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22934 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0fb")) @[ifu_bp_ctl.scala 455:85] - node _T_22935 = bits(_T_22934, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22936 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0fc")) @[ifu_bp_ctl.scala 455:85] - node _T_22937 = bits(_T_22936, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22938 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0fd")) @[ifu_bp_ctl.scala 455:85] - node _T_22939 = bits(_T_22938, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22940 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0fe")) @[ifu_bp_ctl.scala 455:85] - node _T_22941 = bits(_T_22940, 0, 0) @[ifu_bp_ctl.scala 455:93] - node _T_22942 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ff")) @[ifu_bp_ctl.scala 455:85] - node _T_22943 = bits(_T_22942, 0, 0) @[ifu_bp_ctl.scala 455:93] + bht_bank1_rd_data_f <= _T_22431 @[ifu_bp_ctl.scala 455:23] + node _T_22432 = eq(bht_rd_addr_hashed_p1_f, UInt<1>("h00")) @[ifu_bp_ctl.scala 456:85] + node _T_22433 = bits(_T_22432, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22434 = eq(bht_rd_addr_hashed_p1_f, UInt<1>("h01")) @[ifu_bp_ctl.scala 456:85] + node _T_22435 = bits(_T_22434, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22436 = eq(bht_rd_addr_hashed_p1_f, UInt<2>("h02")) @[ifu_bp_ctl.scala 456:85] + node _T_22437 = bits(_T_22436, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22438 = eq(bht_rd_addr_hashed_p1_f, UInt<2>("h03")) @[ifu_bp_ctl.scala 456:85] + node _T_22439 = bits(_T_22438, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22440 = eq(bht_rd_addr_hashed_p1_f, UInt<3>("h04")) @[ifu_bp_ctl.scala 456:85] + node _T_22441 = bits(_T_22440, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22442 = eq(bht_rd_addr_hashed_p1_f, UInt<3>("h05")) @[ifu_bp_ctl.scala 456:85] + node _T_22443 = bits(_T_22442, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22444 = eq(bht_rd_addr_hashed_p1_f, UInt<3>("h06")) @[ifu_bp_ctl.scala 456:85] + node _T_22445 = bits(_T_22444, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22446 = eq(bht_rd_addr_hashed_p1_f, UInt<3>("h07")) @[ifu_bp_ctl.scala 456:85] + node _T_22447 = bits(_T_22446, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22448 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h08")) @[ifu_bp_ctl.scala 456:85] + node _T_22449 = bits(_T_22448, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22450 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h09")) @[ifu_bp_ctl.scala 456:85] + node _T_22451 = bits(_T_22450, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22452 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0a")) @[ifu_bp_ctl.scala 456:85] + node _T_22453 = bits(_T_22452, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22454 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0b")) @[ifu_bp_ctl.scala 456:85] + node _T_22455 = bits(_T_22454, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22456 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0c")) @[ifu_bp_ctl.scala 456:85] + node _T_22457 = bits(_T_22456, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22458 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0d")) @[ifu_bp_ctl.scala 456:85] + node _T_22459 = bits(_T_22458, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22460 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0e")) @[ifu_bp_ctl.scala 456:85] + node _T_22461 = bits(_T_22460, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22462 = eq(bht_rd_addr_hashed_p1_f, UInt<4>("h0f")) @[ifu_bp_ctl.scala 456:85] + node _T_22463 = bits(_T_22462, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22464 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h010")) @[ifu_bp_ctl.scala 456:85] + node _T_22465 = bits(_T_22464, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22466 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h011")) @[ifu_bp_ctl.scala 456:85] + node _T_22467 = bits(_T_22466, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22468 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h012")) @[ifu_bp_ctl.scala 456:85] + node _T_22469 = bits(_T_22468, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22470 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h013")) @[ifu_bp_ctl.scala 456:85] + node _T_22471 = bits(_T_22470, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22472 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h014")) @[ifu_bp_ctl.scala 456:85] + node _T_22473 = bits(_T_22472, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22474 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h015")) @[ifu_bp_ctl.scala 456:85] + node _T_22475 = bits(_T_22474, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22476 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h016")) @[ifu_bp_ctl.scala 456:85] + node _T_22477 = bits(_T_22476, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22478 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h017")) @[ifu_bp_ctl.scala 456:85] + node _T_22479 = bits(_T_22478, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22480 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h018")) @[ifu_bp_ctl.scala 456:85] + node _T_22481 = bits(_T_22480, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22482 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h019")) @[ifu_bp_ctl.scala 456:85] + node _T_22483 = bits(_T_22482, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22484 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h01a")) @[ifu_bp_ctl.scala 456:85] + node _T_22485 = bits(_T_22484, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22486 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h01b")) @[ifu_bp_ctl.scala 456:85] + node _T_22487 = bits(_T_22486, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22488 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h01c")) @[ifu_bp_ctl.scala 456:85] + node _T_22489 = bits(_T_22488, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22490 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h01d")) @[ifu_bp_ctl.scala 456:85] + node _T_22491 = bits(_T_22490, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22492 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h01e")) @[ifu_bp_ctl.scala 456:85] + node _T_22493 = bits(_T_22492, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22494 = eq(bht_rd_addr_hashed_p1_f, UInt<5>("h01f")) @[ifu_bp_ctl.scala 456:85] + node _T_22495 = bits(_T_22494, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22496 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h020")) @[ifu_bp_ctl.scala 456:85] + node _T_22497 = bits(_T_22496, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22498 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h021")) @[ifu_bp_ctl.scala 456:85] + node _T_22499 = bits(_T_22498, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22500 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h022")) @[ifu_bp_ctl.scala 456:85] + node _T_22501 = bits(_T_22500, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22502 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h023")) @[ifu_bp_ctl.scala 456:85] + node _T_22503 = bits(_T_22502, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22504 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h024")) @[ifu_bp_ctl.scala 456:85] + node _T_22505 = bits(_T_22504, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22506 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h025")) @[ifu_bp_ctl.scala 456:85] + node _T_22507 = bits(_T_22506, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22508 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h026")) @[ifu_bp_ctl.scala 456:85] + node _T_22509 = bits(_T_22508, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22510 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h027")) @[ifu_bp_ctl.scala 456:85] + node _T_22511 = bits(_T_22510, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22512 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h028")) @[ifu_bp_ctl.scala 456:85] + node _T_22513 = bits(_T_22512, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22514 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h029")) @[ifu_bp_ctl.scala 456:85] + node _T_22515 = bits(_T_22514, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22516 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h02a")) @[ifu_bp_ctl.scala 456:85] + node _T_22517 = bits(_T_22516, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22518 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h02b")) @[ifu_bp_ctl.scala 456:85] + node _T_22519 = bits(_T_22518, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22520 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h02c")) @[ifu_bp_ctl.scala 456:85] + node _T_22521 = bits(_T_22520, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22522 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h02d")) @[ifu_bp_ctl.scala 456:85] + node _T_22523 = bits(_T_22522, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22524 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h02e")) @[ifu_bp_ctl.scala 456:85] + node _T_22525 = bits(_T_22524, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22526 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h02f")) @[ifu_bp_ctl.scala 456:85] + node _T_22527 = bits(_T_22526, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22528 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h030")) @[ifu_bp_ctl.scala 456:85] + node _T_22529 = bits(_T_22528, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22530 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h031")) @[ifu_bp_ctl.scala 456:85] + node _T_22531 = bits(_T_22530, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22532 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h032")) @[ifu_bp_ctl.scala 456:85] + node _T_22533 = bits(_T_22532, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22534 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h033")) @[ifu_bp_ctl.scala 456:85] + node _T_22535 = bits(_T_22534, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22536 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h034")) @[ifu_bp_ctl.scala 456:85] + node _T_22537 = bits(_T_22536, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22538 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h035")) @[ifu_bp_ctl.scala 456:85] + node _T_22539 = bits(_T_22538, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22540 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h036")) @[ifu_bp_ctl.scala 456:85] + node _T_22541 = bits(_T_22540, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22542 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h037")) @[ifu_bp_ctl.scala 456:85] + node _T_22543 = bits(_T_22542, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22544 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h038")) @[ifu_bp_ctl.scala 456:85] + node _T_22545 = bits(_T_22544, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22546 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h039")) @[ifu_bp_ctl.scala 456:85] + node _T_22547 = bits(_T_22546, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22548 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h03a")) @[ifu_bp_ctl.scala 456:85] + node _T_22549 = bits(_T_22548, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22550 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h03b")) @[ifu_bp_ctl.scala 456:85] + node _T_22551 = bits(_T_22550, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22552 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h03c")) @[ifu_bp_ctl.scala 456:85] + node _T_22553 = bits(_T_22552, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22554 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h03d")) @[ifu_bp_ctl.scala 456:85] + node _T_22555 = bits(_T_22554, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22556 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h03e")) @[ifu_bp_ctl.scala 456:85] + node _T_22557 = bits(_T_22556, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22558 = eq(bht_rd_addr_hashed_p1_f, UInt<6>("h03f")) @[ifu_bp_ctl.scala 456:85] + node _T_22559 = bits(_T_22558, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22560 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h040")) @[ifu_bp_ctl.scala 456:85] + node _T_22561 = bits(_T_22560, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22562 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h041")) @[ifu_bp_ctl.scala 456:85] + node _T_22563 = bits(_T_22562, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22564 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h042")) @[ifu_bp_ctl.scala 456:85] + node _T_22565 = bits(_T_22564, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22566 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h043")) @[ifu_bp_ctl.scala 456:85] + node _T_22567 = bits(_T_22566, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22568 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h044")) @[ifu_bp_ctl.scala 456:85] + node _T_22569 = bits(_T_22568, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22570 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h045")) @[ifu_bp_ctl.scala 456:85] + node _T_22571 = bits(_T_22570, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22572 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h046")) @[ifu_bp_ctl.scala 456:85] + node _T_22573 = bits(_T_22572, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22574 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h047")) @[ifu_bp_ctl.scala 456:85] + node _T_22575 = bits(_T_22574, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22576 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h048")) @[ifu_bp_ctl.scala 456:85] + node _T_22577 = bits(_T_22576, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22578 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h049")) @[ifu_bp_ctl.scala 456:85] + node _T_22579 = bits(_T_22578, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22580 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h04a")) @[ifu_bp_ctl.scala 456:85] + node _T_22581 = bits(_T_22580, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22582 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h04b")) @[ifu_bp_ctl.scala 456:85] + node _T_22583 = bits(_T_22582, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22584 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h04c")) @[ifu_bp_ctl.scala 456:85] + node _T_22585 = bits(_T_22584, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22586 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h04d")) @[ifu_bp_ctl.scala 456:85] + node _T_22587 = bits(_T_22586, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22588 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h04e")) @[ifu_bp_ctl.scala 456:85] + node _T_22589 = bits(_T_22588, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22590 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h04f")) @[ifu_bp_ctl.scala 456:85] + node _T_22591 = bits(_T_22590, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22592 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h050")) @[ifu_bp_ctl.scala 456:85] + node _T_22593 = bits(_T_22592, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22594 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h051")) @[ifu_bp_ctl.scala 456:85] + node _T_22595 = bits(_T_22594, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22596 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h052")) @[ifu_bp_ctl.scala 456:85] + node _T_22597 = bits(_T_22596, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22598 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h053")) @[ifu_bp_ctl.scala 456:85] + node _T_22599 = bits(_T_22598, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22600 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h054")) @[ifu_bp_ctl.scala 456:85] + node _T_22601 = bits(_T_22600, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22602 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h055")) @[ifu_bp_ctl.scala 456:85] + node _T_22603 = bits(_T_22602, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22604 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h056")) @[ifu_bp_ctl.scala 456:85] + node _T_22605 = bits(_T_22604, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22606 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h057")) @[ifu_bp_ctl.scala 456:85] + node _T_22607 = bits(_T_22606, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22608 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h058")) @[ifu_bp_ctl.scala 456:85] + node _T_22609 = bits(_T_22608, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22610 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h059")) @[ifu_bp_ctl.scala 456:85] + node _T_22611 = bits(_T_22610, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22612 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h05a")) @[ifu_bp_ctl.scala 456:85] + node _T_22613 = bits(_T_22612, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22614 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h05b")) @[ifu_bp_ctl.scala 456:85] + node _T_22615 = bits(_T_22614, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22616 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h05c")) @[ifu_bp_ctl.scala 456:85] + node _T_22617 = bits(_T_22616, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22618 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h05d")) @[ifu_bp_ctl.scala 456:85] + node _T_22619 = bits(_T_22618, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22620 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h05e")) @[ifu_bp_ctl.scala 456:85] + node _T_22621 = bits(_T_22620, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22622 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h05f")) @[ifu_bp_ctl.scala 456:85] + node _T_22623 = bits(_T_22622, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22624 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h060")) @[ifu_bp_ctl.scala 456:85] + node _T_22625 = bits(_T_22624, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22626 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h061")) @[ifu_bp_ctl.scala 456:85] + node _T_22627 = bits(_T_22626, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22628 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h062")) @[ifu_bp_ctl.scala 456:85] + node _T_22629 = bits(_T_22628, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22630 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h063")) @[ifu_bp_ctl.scala 456:85] + node _T_22631 = bits(_T_22630, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22632 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h064")) @[ifu_bp_ctl.scala 456:85] + node _T_22633 = bits(_T_22632, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22634 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h065")) @[ifu_bp_ctl.scala 456:85] + node _T_22635 = bits(_T_22634, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22636 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h066")) @[ifu_bp_ctl.scala 456:85] + node _T_22637 = bits(_T_22636, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22638 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h067")) @[ifu_bp_ctl.scala 456:85] + node _T_22639 = bits(_T_22638, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22640 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h068")) @[ifu_bp_ctl.scala 456:85] + node _T_22641 = bits(_T_22640, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22642 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h069")) @[ifu_bp_ctl.scala 456:85] + node _T_22643 = bits(_T_22642, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22644 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h06a")) @[ifu_bp_ctl.scala 456:85] + node _T_22645 = bits(_T_22644, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22646 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h06b")) @[ifu_bp_ctl.scala 456:85] + node _T_22647 = bits(_T_22646, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22648 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h06c")) @[ifu_bp_ctl.scala 456:85] + node _T_22649 = bits(_T_22648, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22650 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h06d")) @[ifu_bp_ctl.scala 456:85] + node _T_22651 = bits(_T_22650, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22652 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h06e")) @[ifu_bp_ctl.scala 456:85] + node _T_22653 = bits(_T_22652, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22654 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h06f")) @[ifu_bp_ctl.scala 456:85] + node _T_22655 = bits(_T_22654, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22656 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h070")) @[ifu_bp_ctl.scala 456:85] + node _T_22657 = bits(_T_22656, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22658 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h071")) @[ifu_bp_ctl.scala 456:85] + node _T_22659 = bits(_T_22658, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22660 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h072")) @[ifu_bp_ctl.scala 456:85] + node _T_22661 = bits(_T_22660, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22662 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h073")) @[ifu_bp_ctl.scala 456:85] + node _T_22663 = bits(_T_22662, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22664 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h074")) @[ifu_bp_ctl.scala 456:85] + node _T_22665 = bits(_T_22664, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22666 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h075")) @[ifu_bp_ctl.scala 456:85] + node _T_22667 = bits(_T_22666, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22668 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h076")) @[ifu_bp_ctl.scala 456:85] + node _T_22669 = bits(_T_22668, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22670 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h077")) @[ifu_bp_ctl.scala 456:85] + node _T_22671 = bits(_T_22670, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22672 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h078")) @[ifu_bp_ctl.scala 456:85] + node _T_22673 = bits(_T_22672, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22674 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h079")) @[ifu_bp_ctl.scala 456:85] + node _T_22675 = bits(_T_22674, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22676 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h07a")) @[ifu_bp_ctl.scala 456:85] + node _T_22677 = bits(_T_22676, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22678 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h07b")) @[ifu_bp_ctl.scala 456:85] + node _T_22679 = bits(_T_22678, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22680 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h07c")) @[ifu_bp_ctl.scala 456:85] + node _T_22681 = bits(_T_22680, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22682 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h07d")) @[ifu_bp_ctl.scala 456:85] + node _T_22683 = bits(_T_22682, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22684 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h07e")) @[ifu_bp_ctl.scala 456:85] + node _T_22685 = bits(_T_22684, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22686 = eq(bht_rd_addr_hashed_p1_f, UInt<7>("h07f")) @[ifu_bp_ctl.scala 456:85] + node _T_22687 = bits(_T_22686, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22688 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h080")) @[ifu_bp_ctl.scala 456:85] + node _T_22689 = bits(_T_22688, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22690 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h081")) @[ifu_bp_ctl.scala 456:85] + node _T_22691 = bits(_T_22690, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22692 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h082")) @[ifu_bp_ctl.scala 456:85] + node _T_22693 = bits(_T_22692, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22694 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h083")) @[ifu_bp_ctl.scala 456:85] + node _T_22695 = bits(_T_22694, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22696 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h084")) @[ifu_bp_ctl.scala 456:85] + node _T_22697 = bits(_T_22696, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22698 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h085")) @[ifu_bp_ctl.scala 456:85] + node _T_22699 = bits(_T_22698, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22700 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h086")) @[ifu_bp_ctl.scala 456:85] + node _T_22701 = bits(_T_22700, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22702 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h087")) @[ifu_bp_ctl.scala 456:85] + node _T_22703 = bits(_T_22702, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22704 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h088")) @[ifu_bp_ctl.scala 456:85] + node _T_22705 = bits(_T_22704, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22706 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h089")) @[ifu_bp_ctl.scala 456:85] + node _T_22707 = bits(_T_22706, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22708 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h08a")) @[ifu_bp_ctl.scala 456:85] + node _T_22709 = bits(_T_22708, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22710 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h08b")) @[ifu_bp_ctl.scala 456:85] + node _T_22711 = bits(_T_22710, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22712 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h08c")) @[ifu_bp_ctl.scala 456:85] + node _T_22713 = bits(_T_22712, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22714 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h08d")) @[ifu_bp_ctl.scala 456:85] + node _T_22715 = bits(_T_22714, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22716 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h08e")) @[ifu_bp_ctl.scala 456:85] + node _T_22717 = bits(_T_22716, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22718 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h08f")) @[ifu_bp_ctl.scala 456:85] + node _T_22719 = bits(_T_22718, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22720 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h090")) @[ifu_bp_ctl.scala 456:85] + node _T_22721 = bits(_T_22720, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22722 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h091")) @[ifu_bp_ctl.scala 456:85] + node _T_22723 = bits(_T_22722, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22724 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h092")) @[ifu_bp_ctl.scala 456:85] + node _T_22725 = bits(_T_22724, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22726 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h093")) @[ifu_bp_ctl.scala 456:85] + node _T_22727 = bits(_T_22726, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22728 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h094")) @[ifu_bp_ctl.scala 456:85] + node _T_22729 = bits(_T_22728, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22730 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h095")) @[ifu_bp_ctl.scala 456:85] + node _T_22731 = bits(_T_22730, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22732 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h096")) @[ifu_bp_ctl.scala 456:85] + node _T_22733 = bits(_T_22732, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22734 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h097")) @[ifu_bp_ctl.scala 456:85] + node _T_22735 = bits(_T_22734, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22736 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h098")) @[ifu_bp_ctl.scala 456:85] + node _T_22737 = bits(_T_22736, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22738 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h099")) @[ifu_bp_ctl.scala 456:85] + node _T_22739 = bits(_T_22738, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22740 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h09a")) @[ifu_bp_ctl.scala 456:85] + node _T_22741 = bits(_T_22740, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22742 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h09b")) @[ifu_bp_ctl.scala 456:85] + node _T_22743 = bits(_T_22742, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22744 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h09c")) @[ifu_bp_ctl.scala 456:85] + node _T_22745 = bits(_T_22744, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22746 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h09d")) @[ifu_bp_ctl.scala 456:85] + node _T_22747 = bits(_T_22746, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22748 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h09e")) @[ifu_bp_ctl.scala 456:85] + node _T_22749 = bits(_T_22748, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22750 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h09f")) @[ifu_bp_ctl.scala 456:85] + node _T_22751 = bits(_T_22750, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22752 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0a0")) @[ifu_bp_ctl.scala 456:85] + node _T_22753 = bits(_T_22752, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22754 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0a1")) @[ifu_bp_ctl.scala 456:85] + node _T_22755 = bits(_T_22754, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22756 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0a2")) @[ifu_bp_ctl.scala 456:85] + node _T_22757 = bits(_T_22756, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22758 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0a3")) @[ifu_bp_ctl.scala 456:85] + node _T_22759 = bits(_T_22758, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22760 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0a4")) @[ifu_bp_ctl.scala 456:85] + node _T_22761 = bits(_T_22760, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22762 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0a5")) @[ifu_bp_ctl.scala 456:85] + node _T_22763 = bits(_T_22762, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22764 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0a6")) @[ifu_bp_ctl.scala 456:85] + node _T_22765 = bits(_T_22764, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22766 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0a7")) @[ifu_bp_ctl.scala 456:85] + node _T_22767 = bits(_T_22766, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22768 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0a8")) @[ifu_bp_ctl.scala 456:85] + node _T_22769 = bits(_T_22768, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22770 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0a9")) @[ifu_bp_ctl.scala 456:85] + node _T_22771 = bits(_T_22770, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22772 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0aa")) @[ifu_bp_ctl.scala 456:85] + node _T_22773 = bits(_T_22772, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22774 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ab")) @[ifu_bp_ctl.scala 456:85] + node _T_22775 = bits(_T_22774, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22776 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ac")) @[ifu_bp_ctl.scala 456:85] + node _T_22777 = bits(_T_22776, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22778 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ad")) @[ifu_bp_ctl.scala 456:85] + node _T_22779 = bits(_T_22778, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22780 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ae")) @[ifu_bp_ctl.scala 456:85] + node _T_22781 = bits(_T_22780, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22782 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0af")) @[ifu_bp_ctl.scala 456:85] + node _T_22783 = bits(_T_22782, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22784 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0b0")) @[ifu_bp_ctl.scala 456:85] + node _T_22785 = bits(_T_22784, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22786 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0b1")) @[ifu_bp_ctl.scala 456:85] + node _T_22787 = bits(_T_22786, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22788 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0b2")) @[ifu_bp_ctl.scala 456:85] + node _T_22789 = bits(_T_22788, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22790 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0b3")) @[ifu_bp_ctl.scala 456:85] + node _T_22791 = bits(_T_22790, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22792 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0b4")) @[ifu_bp_ctl.scala 456:85] + node _T_22793 = bits(_T_22792, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22794 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0b5")) @[ifu_bp_ctl.scala 456:85] + node _T_22795 = bits(_T_22794, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22796 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0b6")) @[ifu_bp_ctl.scala 456:85] + node _T_22797 = bits(_T_22796, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22798 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0b7")) @[ifu_bp_ctl.scala 456:85] + node _T_22799 = bits(_T_22798, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22800 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0b8")) @[ifu_bp_ctl.scala 456:85] + node _T_22801 = bits(_T_22800, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22802 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0b9")) @[ifu_bp_ctl.scala 456:85] + node _T_22803 = bits(_T_22802, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22804 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ba")) @[ifu_bp_ctl.scala 456:85] + node _T_22805 = bits(_T_22804, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22806 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0bb")) @[ifu_bp_ctl.scala 456:85] + node _T_22807 = bits(_T_22806, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22808 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0bc")) @[ifu_bp_ctl.scala 456:85] + node _T_22809 = bits(_T_22808, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22810 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0bd")) @[ifu_bp_ctl.scala 456:85] + node _T_22811 = bits(_T_22810, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22812 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0be")) @[ifu_bp_ctl.scala 456:85] + node _T_22813 = bits(_T_22812, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22814 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0bf")) @[ifu_bp_ctl.scala 456:85] + node _T_22815 = bits(_T_22814, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22816 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0c0")) @[ifu_bp_ctl.scala 456:85] + node _T_22817 = bits(_T_22816, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22818 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0c1")) @[ifu_bp_ctl.scala 456:85] + node _T_22819 = bits(_T_22818, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22820 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0c2")) @[ifu_bp_ctl.scala 456:85] + node _T_22821 = bits(_T_22820, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22822 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0c3")) @[ifu_bp_ctl.scala 456:85] + node _T_22823 = bits(_T_22822, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22824 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0c4")) @[ifu_bp_ctl.scala 456:85] + node _T_22825 = bits(_T_22824, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22826 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0c5")) @[ifu_bp_ctl.scala 456:85] + node _T_22827 = bits(_T_22826, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22828 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0c6")) @[ifu_bp_ctl.scala 456:85] + node _T_22829 = bits(_T_22828, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22830 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0c7")) @[ifu_bp_ctl.scala 456:85] + node _T_22831 = bits(_T_22830, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22832 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0c8")) @[ifu_bp_ctl.scala 456:85] + node _T_22833 = bits(_T_22832, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22834 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0c9")) @[ifu_bp_ctl.scala 456:85] + node _T_22835 = bits(_T_22834, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22836 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ca")) @[ifu_bp_ctl.scala 456:85] + node _T_22837 = bits(_T_22836, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22838 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0cb")) @[ifu_bp_ctl.scala 456:85] + node _T_22839 = bits(_T_22838, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22840 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0cc")) @[ifu_bp_ctl.scala 456:85] + node _T_22841 = bits(_T_22840, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22842 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0cd")) @[ifu_bp_ctl.scala 456:85] + node _T_22843 = bits(_T_22842, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22844 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ce")) @[ifu_bp_ctl.scala 456:85] + node _T_22845 = bits(_T_22844, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22846 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0cf")) @[ifu_bp_ctl.scala 456:85] + node _T_22847 = bits(_T_22846, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22848 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0d0")) @[ifu_bp_ctl.scala 456:85] + node _T_22849 = bits(_T_22848, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22850 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0d1")) @[ifu_bp_ctl.scala 456:85] + node _T_22851 = bits(_T_22850, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22852 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0d2")) @[ifu_bp_ctl.scala 456:85] + node _T_22853 = bits(_T_22852, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22854 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0d3")) @[ifu_bp_ctl.scala 456:85] + node _T_22855 = bits(_T_22854, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22856 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0d4")) @[ifu_bp_ctl.scala 456:85] + node _T_22857 = bits(_T_22856, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22858 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0d5")) @[ifu_bp_ctl.scala 456:85] + node _T_22859 = bits(_T_22858, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22860 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0d6")) @[ifu_bp_ctl.scala 456:85] + node _T_22861 = bits(_T_22860, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22862 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0d7")) @[ifu_bp_ctl.scala 456:85] + node _T_22863 = bits(_T_22862, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22864 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0d8")) @[ifu_bp_ctl.scala 456:85] + node _T_22865 = bits(_T_22864, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22866 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0d9")) @[ifu_bp_ctl.scala 456:85] + node _T_22867 = bits(_T_22866, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22868 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0da")) @[ifu_bp_ctl.scala 456:85] + node _T_22869 = bits(_T_22868, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22870 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0db")) @[ifu_bp_ctl.scala 456:85] + node _T_22871 = bits(_T_22870, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22872 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0dc")) @[ifu_bp_ctl.scala 456:85] + node _T_22873 = bits(_T_22872, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22874 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0dd")) @[ifu_bp_ctl.scala 456:85] + node _T_22875 = bits(_T_22874, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22876 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0de")) @[ifu_bp_ctl.scala 456:85] + node _T_22877 = bits(_T_22876, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22878 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0df")) @[ifu_bp_ctl.scala 456:85] + node _T_22879 = bits(_T_22878, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22880 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0e0")) @[ifu_bp_ctl.scala 456:85] + node _T_22881 = bits(_T_22880, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22882 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0e1")) @[ifu_bp_ctl.scala 456:85] + node _T_22883 = bits(_T_22882, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22884 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0e2")) @[ifu_bp_ctl.scala 456:85] + node _T_22885 = bits(_T_22884, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22886 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0e3")) @[ifu_bp_ctl.scala 456:85] + node _T_22887 = bits(_T_22886, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22888 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0e4")) @[ifu_bp_ctl.scala 456:85] + node _T_22889 = bits(_T_22888, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22890 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0e5")) @[ifu_bp_ctl.scala 456:85] + node _T_22891 = bits(_T_22890, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22892 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0e6")) @[ifu_bp_ctl.scala 456:85] + node _T_22893 = bits(_T_22892, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22894 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0e7")) @[ifu_bp_ctl.scala 456:85] + node _T_22895 = bits(_T_22894, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22896 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0e8")) @[ifu_bp_ctl.scala 456:85] + node _T_22897 = bits(_T_22896, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22898 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0e9")) @[ifu_bp_ctl.scala 456:85] + node _T_22899 = bits(_T_22898, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22900 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ea")) @[ifu_bp_ctl.scala 456:85] + node _T_22901 = bits(_T_22900, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22902 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0eb")) @[ifu_bp_ctl.scala 456:85] + node _T_22903 = bits(_T_22902, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22904 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ec")) @[ifu_bp_ctl.scala 456:85] + node _T_22905 = bits(_T_22904, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22906 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ed")) @[ifu_bp_ctl.scala 456:85] + node _T_22907 = bits(_T_22906, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22908 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ee")) @[ifu_bp_ctl.scala 456:85] + node _T_22909 = bits(_T_22908, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22910 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ef")) @[ifu_bp_ctl.scala 456:85] + node _T_22911 = bits(_T_22910, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22912 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0f0")) @[ifu_bp_ctl.scala 456:85] + node _T_22913 = bits(_T_22912, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22914 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0f1")) @[ifu_bp_ctl.scala 456:85] + node _T_22915 = bits(_T_22914, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22916 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0f2")) @[ifu_bp_ctl.scala 456:85] + node _T_22917 = bits(_T_22916, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22918 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0f3")) @[ifu_bp_ctl.scala 456:85] + node _T_22919 = bits(_T_22918, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22920 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0f4")) @[ifu_bp_ctl.scala 456:85] + node _T_22921 = bits(_T_22920, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22922 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0f5")) @[ifu_bp_ctl.scala 456:85] + node _T_22923 = bits(_T_22922, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22924 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0f6")) @[ifu_bp_ctl.scala 456:85] + node _T_22925 = bits(_T_22924, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22926 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0f7")) @[ifu_bp_ctl.scala 456:85] + node _T_22927 = bits(_T_22926, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22928 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0f8")) @[ifu_bp_ctl.scala 456:85] + node _T_22929 = bits(_T_22928, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22930 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0f9")) @[ifu_bp_ctl.scala 456:85] + node _T_22931 = bits(_T_22930, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22932 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0fa")) @[ifu_bp_ctl.scala 456:85] + node _T_22933 = bits(_T_22932, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22934 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0fb")) @[ifu_bp_ctl.scala 456:85] + node _T_22935 = bits(_T_22934, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22936 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0fc")) @[ifu_bp_ctl.scala 456:85] + node _T_22937 = bits(_T_22936, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22938 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0fd")) @[ifu_bp_ctl.scala 456:85] + node _T_22939 = bits(_T_22938, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22940 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0fe")) @[ifu_bp_ctl.scala 456:85] + node _T_22941 = bits(_T_22940, 0, 0) @[ifu_bp_ctl.scala 456:93] + node _T_22942 = eq(bht_rd_addr_hashed_p1_f, UInt<8>("h0ff")) @[ifu_bp_ctl.scala 456:85] + node _T_22943 = bits(_T_22942, 0, 0) @[ifu_bp_ctl.scala 456:93] node _T_22944 = mux(_T_22433, bht_bank_rd_data_out[0][0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_22945 = mux(_T_22435, bht_bank_rd_data_out[0][1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_22946 = mux(_T_22437, bht_bank_rd_data_out[0][2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -60250,7 +60250,7 @@ circuit quasar_wrapper : node _T_23454 = or(_T_23453, _T_23199) @[Mux.scala 27:72] wire _T_23455 : UInt<2> @[Mux.scala 27:72] _T_23455 <= _T_23454 @[Mux.scala 27:72] - bht_bank0_rd_data_p1_f <= _T_23455 @[ifu_bp_ctl.scala 455:26] + bht_bank0_rd_data_p1_f <= _T_23455 @[ifu_bp_ctl.scala 456:26] extmodule gated_latch_648 : output Q : Clock @@ -64024,224 +64024,224 @@ circuit quasar_wrapper : module ifu : input clock : Clock input reset : AsyncReset - output io : {flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip free_clk : Clock, flip active_clk : Clock, ifu_dec : {dec_aln : {aln_dec : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, aln_ib : {ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_i0_valid : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}, ifu_pmu_instr_aligned : UInt<1>}, dec_mem_ctrl : {flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, dec_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, dec_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}}, exu_ifu : {flip exu_bp : {exu_i0_br_index_r : UInt<8>, exu_i0_br_fghr_r : UInt<8>, exu_i0_br_way_r : UInt<1>, exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, exu_mp_eghr : UInt<8>, exu_mp_fghr : UInt<8>, exu_mp_index : UInt<8>, exu_mp_btag : UInt<5>}}, iccm : {rw_addr : UInt<15>, buf_correct_ecc : UInt<1>, correction_state : UInt<1>, wren : UInt<1>, rden : UInt<1>, wr_size : UInt<3>, wr_data : UInt<78>, flip rd_data : UInt<64>, flip rd_data_ecc : UInt<78>}, ic : {rw_addr : UInt<31>, tag_valid : UInt<2>, wr_en : UInt<2>, rd_en : UInt<1>, wr_data : UInt<71>[2], debug_wr_data : UInt<71>, debug_addr : UInt<10>, flip rd_data : UInt<64>, flip debug_rd_data : UInt<71>, flip tag_debug_rd_data : UInt<26>, flip eccerr : UInt<2>, flip parerr : UInt<2>, flip rd_hit : UInt<2>, flip tag_perr : UInt<1>, debug_rd_en : UInt<1>, debug_wr_en : UInt<1>, debug_tag_array : UInt<1>, debug_way : UInt<2>, premux_data : UInt<64>, sel_premux_data : UInt<1>}, ifu : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip ifu_bus_clk_en : UInt<1>, ifu_dma : {dma_ifc : {flip dma_iccm_stall_any : UInt<1>}, dma_mem_ctl : {flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>}}, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, iccm_dma_sb_error : UInt<1>, flip scan_mode : UInt<1>} + output io : {flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip free_clk : Clock, flip active_clk : Clock, ifu_dec : {dec_aln : {aln_dec : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, aln_ib : {ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_i0_valid : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}, ifu_pmu_instr_aligned : UInt<1>}, dec_mem_ctrl : {flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, dec_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, dec_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}}, exu_ifu : {flip exu_bp : {exu_i0_br_index_r : UInt<8>, exu_i0_br_fghr_r : UInt<8>, exu_i0_br_way_r : UInt<1>, exu_mp_pkt : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, exu_mp_eghr : UInt<8>, exu_mp_fghr : UInt<8>, exu_mp_index : UInt<8>, exu_mp_btag : UInt<5>}}, iccm : {rw_addr : UInt<15>, buf_correct_ecc : UInt<1>, correction_state : UInt<1>, wren : UInt<1>, rden : UInt<1>, wr_size : UInt<3>, wr_data : UInt<78>, flip rd_data : UInt<64>, flip rd_data_ecc : UInt<78>}, ic : {rw_addr : UInt<31>, tag_valid : UInt<2>, wr_en : UInt<2>, rd_en : UInt<1>, wr_data : UInt<71>[2], debug_wr_data : UInt<71>, debug_addr : UInt<10>, flip rd_data : UInt<64>, flip debug_rd_data : UInt<71>, flip tag_debug_rd_data : UInt<26>, flip eccerr : UInt<2>, flip parerr : UInt<2>, flip rd_hit : UInt<2>, flip tag_perr : UInt<1>, debug_rd_en : UInt<1>, debug_wr_en : UInt<1>, debug_tag_array : UInt<1>, debug_way : UInt<2>, premux_data : UInt<64>, sel_premux_data : UInt<1>}, ifu : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip ifu_bus_clk_en : UInt<1>, ifu_dma : {dma_ifc : {flip dma_iccm_stall_any : UInt<1>}, dma_mem_ctl : {flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>}}, iccm_dma_ecc_error : UInt<1>, iccm_dma_rvalid : UInt<1>, iccm_dma_rdata : UInt<64>, iccm_dma_rtag : UInt<3>, iccm_ready : UInt<1>, iccm_dma_sb_error : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip scan_mode : UInt<1>} - inst mem_ctl of ifu_mem_ctl @[ifu.scala 37:23] + inst mem_ctl of ifu_mem_ctl @[ifu.scala 36:23] mem_ctl.clock <= clock mem_ctl.reset <= reset - inst bp_ctl of ifu_bp_ctl @[ifu.scala 38:22] + inst bp_ctl of ifu_bp_ctl @[ifu.scala 37:22] bp_ctl.clock <= clock bp_ctl.reset <= reset - inst aln_ctl of ifu_aln_ctl @[ifu.scala 39:23] + inst aln_ctl of ifu_aln_ctl @[ifu.scala 38:23] aln_ctl.clock <= clock aln_ctl.reset <= reset - inst ifc_ctl of ifu_ifc_ctl @[ifu.scala 40:23] + inst ifc_ctl of ifu_ifc_ctl @[ifu.scala 39:23] ifc_ctl.clock <= clock ifc_ctl.reset <= reset - ifc_ctl.io.active_clk <= io.active_clk @[ifu.scala 43:25] - ifc_ctl.io.free_clk <= io.free_clk @[ifu.scala 44:23] - ifc_ctl.io.scan_mode <= io.scan_mode @[ifu.scala 45:24] - ifc_ctl.io.ic_hit_f <= mem_ctl.io.ic_hit_f @[ifu.scala 46:23] - ifc_ctl.io.ifu_fb_consume1 <= aln_ctl.io.ifu_fb_consume1 @[ifu.scala 47:30] - ifc_ctl.io.ifu_fb_consume2 <= aln_ctl.io.ifu_fb_consume2 @[ifu.scala 48:30] - io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall <= ifc_ctl.io.dec_ifc.ifu_pmu_fetch_stall @[ifu.scala 49:22] - ifc_ctl.io.dec_ifc.dec_tlu_mrac_ff <= io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[ifu.scala 49:22] - ifc_ctl.io.dec_ifc.dec_tlu_flush_noredir_wb <= io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb @[ifu.scala 49:22] - ifc_ctl.io.exu_flush_final <= io.exu_flush_final @[ifu.scala 50:30] - ifc_ctl.io.ifu_bp_hit_taken_f <= bp_ctl.io.ifu_bp_hit_taken_f @[ifu.scala 51:33] - ifc_ctl.io.ifu_bp_btb_target_f <= bp_ctl.io.ifu_bp_btb_target_f @[ifu.scala 52:34] - ifc_ctl.io.ic_dma_active <= mem_ctl.io.ic_dma_active @[ifu.scala 53:28] - ifc_ctl.io.ic_write_stall <= mem_ctl.io.ic_write_stall @[ifu.scala 54:29] - ifc_ctl.io.dma_ifc.dma_iccm_stall_any <= io.ifu_dma.dma_ifc.dma_iccm_stall_any @[ifu.scala 55:22] - ifc_ctl.io.ifu_ic_mb_empty <= mem_ctl.io.ifu_ic_mb_empty @[ifu.scala 56:30] - ifc_ctl.io.exu_flush_path_final <= io.exu_flush_path_final @[ifu.scala 57:35] - aln_ctl.io.scan_mode <= io.scan_mode @[ifu.scala 60:24] - aln_ctl.io.active_clk <= io.active_clk @[ifu.scala 61:25] - aln_ctl.io.ifu_async_error_start <= mem_ctl.io.ifu_async_error_start @[ifu.scala 62:36] - aln_ctl.io.iccm_rd_ecc_double_err <= mem_ctl.io.iccm_rd_ecc_double_err @[ifu.scala 63:37] - aln_ctl.io.ic_access_fault_f <= mem_ctl.io.ic_access_fault_f @[ifu.scala 64:32] - aln_ctl.io.ic_access_fault_type_f <= mem_ctl.io.ic_access_fault_type_f @[ifu.scala 65:37] - aln_ctl.io.ifu_bp_fghr_f <= bp_ctl.io.ifu_bp_fghr_f @[ifu.scala 66:28] - aln_ctl.io.ifu_bp_btb_target_f <= bp_ctl.io.ifu_bp_btb_target_f @[ifu.scala 67:34] - aln_ctl.io.ifu_bp_poffset_f <= bp_ctl.io.ifu_bp_poffset_f @[ifu.scala 68:31] - aln_ctl.io.ifu_bp_hist0_f <= bp_ctl.io.ifu_bp_hist0_f @[ifu.scala 69:29] - aln_ctl.io.ifu_bp_hist1_f <= bp_ctl.io.ifu_bp_hist1_f @[ifu.scala 70:29] - aln_ctl.io.ifu_bp_pc4_f <= bp_ctl.io.ifu_bp_pc4_f @[ifu.scala 71:27] - aln_ctl.io.ifu_bp_way_f <= bp_ctl.io.ifu_bp_way_f @[ifu.scala 72:27] - aln_ctl.io.ifu_bp_valid_f <= bp_ctl.io.ifu_bp_valid_f @[ifu.scala 73:29] - aln_ctl.io.ifu_bp_ret_f <= bp_ctl.io.ifu_bp_ret_f @[ifu.scala 74:27] - aln_ctl.io.exu_flush_final <= io.exu_flush_final @[ifu.scala 75:30] - io.ifu_dec.dec_aln.ifu_pmu_instr_aligned <= aln_ctl.io.dec_aln.ifu_pmu_instr_aligned @[ifu.scala 76:22] - io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.ret @[ifu.scala 76:22] - io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.way @[ifu.scala 76:22] - io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.prett @[ifu.scala 76:22] - io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.bank @[ifu.scala 76:22] - io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.br_start_error @[ifu.scala 76:22] - io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.br_error @[ifu.scala 76:22] - io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.hist @[ifu.scala 76:22] - io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.toffset @[ifu.scala 76:22] - io.ifu_dec.dec_aln.aln_ib.i0_brp.valid <= aln_ctl.io.dec_aln.aln_ib.i0_brp.valid @[ifu.scala 76:22] - io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_pc4 @[ifu.scala 76:22] - io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_pc @[ifu.scala 76:22] - io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_instr @[ifu.scala 76:22] - io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_valid @[ifu.scala 76:22] - io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_bp_btag @[ifu.scala 76:22] - io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_bp_fghr @[ifu.scala 76:22] - io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_bp_index @[ifu.scala 76:22] - io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_dbecc @[ifu.scala 76:22] - io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_icaf_f1 @[ifu.scala 76:22] - io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_icaf_type @[ifu.scala 76:22] - io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_icaf @[ifu.scala 76:22] - io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst <= aln_ctl.io.dec_aln.aln_dec.ifu_i0_cinst @[ifu.scala 76:22] - aln_ctl.io.dec_aln.aln_dec.dec_i0_decode_d <= io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d @[ifu.scala 76:22] - aln_ctl.io.ifu_fetch_data_f <= mem_ctl.io.ic_data_f @[ifu.scala 77:31] - aln_ctl.io.ifu_fetch_val <= mem_ctl.io.ifu_fetch_val @[ifu.scala 78:28] - aln_ctl.io.ifu_fetch_pc <= ifc_ctl.io.ifc_fetch_addr_f @[ifu.scala 79:27] - bp_ctl.io.scan_mode <= io.scan_mode @[ifu.scala 82:23] - bp_ctl.io.active_clk <= io.active_clk @[ifu.scala 83:24] - bp_ctl.io.ic_hit_f <= mem_ctl.io.ic_hit_f @[ifu.scala 84:22] - bp_ctl.io.ifc_fetch_addr_f <= ifc_ctl.io.ifc_fetch_addr_f @[ifu.scala 85:30] - bp_ctl.io.ifc_fetch_req_f <= ifc_ctl.io.ifc_fetch_req_f @[ifu.scala 86:29] - bp_ctl.io.dec_bp.dec_tlu_bpred_disable <= io.ifu_dec.dec_bp.dec_tlu_bpred_disable @[ifu.scala 87:20] - bp_ctl.io.dec_bp.dec_tlu_flush_leak_one_wb <= io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb @[ifu.scala 87:20] - bp_ctl.io.dec_bp.dec_tlu_flush_lower_wb <= io.ifu_dec.dec_bp.dec_tlu_flush_lower_wb @[ifu.scala 87:20] - bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle @[ifu.scala 87:20] - bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.bits.way <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way @[ifu.scala 87:20] - bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[ifu.scala 87:20] - bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error @[ifu.scala 87:20] - bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist @[ifu.scala 87:20] - bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.valid <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid @[ifu.scala 87:20] - bp_ctl.io.exu_bp.exu_mp_btag <= io.exu_ifu.exu_bp.exu_mp_btag @[ifu.scala 88:20] - bp_ctl.io.exu_bp.exu_mp_index <= io.exu_ifu.exu_bp.exu_mp_index @[ifu.scala 88:20] - bp_ctl.io.exu_bp.exu_mp_fghr <= io.exu_ifu.exu_bp.exu_mp_fghr @[ifu.scala 88:20] - bp_ctl.io.exu_bp.exu_mp_eghr <= io.exu_ifu.exu_bp.exu_mp_eghr @[ifu.scala 88:20] - bp_ctl.io.exu_bp.exu_mp_pkt.bits.way <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.way @[ifu.scala 88:20] - bp_ctl.io.exu_bp.exu_mp_pkt.bits.pja <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.pja @[ifu.scala 88:20] - bp_ctl.io.exu_bp.exu_mp_pkt.bits.pret <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.pret @[ifu.scala 88:20] - bp_ctl.io.exu_bp.exu_mp_pkt.bits.pcall <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.pcall @[ifu.scala 88:20] - bp_ctl.io.exu_bp.exu_mp_pkt.bits.prett <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.prett @[ifu.scala 88:20] - bp_ctl.io.exu_bp.exu_mp_pkt.bits.br_start_error <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_start_error @[ifu.scala 88:20] - bp_ctl.io.exu_bp.exu_mp_pkt.bits.br_error <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_error @[ifu.scala 88:20] - bp_ctl.io.exu_bp.exu_mp_pkt.bits.toffset <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.toffset @[ifu.scala 88:20] - bp_ctl.io.exu_bp.exu_mp_pkt.bits.hist <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.hist @[ifu.scala 88:20] - bp_ctl.io.exu_bp.exu_mp_pkt.bits.pc4 <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.pc4 @[ifu.scala 88:20] - bp_ctl.io.exu_bp.exu_mp_pkt.bits.boffset <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.boffset @[ifu.scala 88:20] - bp_ctl.io.exu_bp.exu_mp_pkt.bits.ataken <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.ataken @[ifu.scala 88:20] - bp_ctl.io.exu_bp.exu_mp_pkt.bits.misp <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.misp @[ifu.scala 88:20] - bp_ctl.io.exu_bp.exu_mp_pkt.valid <= io.exu_ifu.exu_bp.exu_mp_pkt.valid @[ifu.scala 88:20] - bp_ctl.io.exu_bp.exu_i0_br_way_r <= io.exu_ifu.exu_bp.exu_i0_br_way_r @[ifu.scala 88:20] - bp_ctl.io.exu_bp.exu_i0_br_fghr_r <= io.exu_ifu.exu_bp.exu_i0_br_fghr_r @[ifu.scala 88:20] - bp_ctl.io.exu_bp.exu_i0_br_index_r <= io.exu_ifu.exu_bp.exu_i0_br_index_r @[ifu.scala 88:20] - bp_ctl.io.exu_flush_final <= io.exu_flush_final @[ifu.scala 89:29] - mem_ctl.io.free_clk <= io.free_clk @[ifu.scala 92:23] - mem_ctl.io.active_clk <= io.active_clk @[ifu.scala 93:25] - mem_ctl.io.exu_flush_final <= io.exu_flush_final @[ifu.scala 94:30] - io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle <= mem_ctl.io.dec_mem_ctrl.ifu_miss_state_idle @[ifu.scala 95:27] - io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= mem_ctl.io.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[ifu.scala 95:27] - io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data <= mem_ctl.io.dec_mem_ctrl.ifu_ic_debug_rd_data @[ifu.scala 95:27] - io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= mem_ctl.io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[ifu.scala 95:27] - io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start <= mem_ctl.io.dec_mem_ctrl.ifu_ic_error_start @[ifu.scala 95:27] - io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn <= mem_ctl.io.dec_mem_ctrl.ifu_pmu_bus_trxn @[ifu.scala 95:27] - io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy <= mem_ctl.io.dec_mem_ctrl.ifu_pmu_bus_busy @[ifu.scala 95:27] - io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error <= mem_ctl.io.dec_mem_ctrl.ifu_pmu_bus_error @[ifu.scala 95:27] - io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit <= mem_ctl.io.dec_mem_ctrl.ifu_pmu_ic_hit @[ifu.scala 95:27] - io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss <= mem_ctl.io.dec_mem_ctrl.ifu_pmu_ic_miss @[ifu.scala 95:27] - mem_ctl.io.dec_mem_ctrl.dec_tlu_core_ecc_disable <= io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[ifu.scala 95:27] - mem_ctl.io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[ifu.scala 95:27] - mem_ctl.io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[ifu.scala 95:27] - mem_ctl.io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[ifu.scala 95:27] - mem_ctl.io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[ifu.scala 95:27] - mem_ctl.io.dec_mem_ctrl.dec_tlu_fence_i_wb <= io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb @[ifu.scala 95:27] - mem_ctl.io.dec_mem_ctrl.dec_tlu_force_halt <= io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[ifu.scala 95:27] - mem_ctl.io.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt @[ifu.scala 95:27] - mem_ctl.io.dec_mem_ctrl.dec_tlu_flush_err_wb <= io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb @[ifu.scala 95:27] - mem_ctl.io.dec_mem_ctrl.dec_tlu_flush_lower_wb <= io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_lower_wb @[ifu.scala 95:27] - mem_ctl.io.ifc_fetch_addr_bf <= ifc_ctl.io.ifc_fetch_addr_bf @[ifu.scala 96:32] - mem_ctl.io.ifc_fetch_uncacheable_bf <= ifc_ctl.io.ifc_fetch_uncacheable_bf @[ifu.scala 97:39] - mem_ctl.io.ifc_fetch_req_bf <= ifc_ctl.io.ifc_fetch_req_bf @[ifu.scala 98:31] - mem_ctl.io.ifc_fetch_req_bf_raw <= ifc_ctl.io.ifc_fetch_req_bf_raw @[ifu.scala 99:35] - mem_ctl.io.ifc_iccm_access_bf <= ifc_ctl.io.ifc_iccm_access_bf @[ifu.scala 100:33] - mem_ctl.io.ifc_region_acc_fault_bf <= ifc_ctl.io.ifc_region_acc_fault_bf @[ifu.scala 101:38] - mem_ctl.io.ifc_dma_access_ok <= ifc_ctl.io.ifc_dma_access_ok @[ifu.scala 102:32] - mem_ctl.io.ifu_bp_hit_taken_f <= bp_ctl.io.ifu_bp_hit_taken_f @[ifu.scala 103:33] - mem_ctl.io.ifu_bp_inst_mask_f <= bp_ctl.io.ifu_bp_inst_mask_f @[ifu.scala 104:33] - mem_ctl.io.ifu_axi.r.bits.last <= io.ifu.r.bits.last @[ifu.scala 105:22] - mem_ctl.io.ifu_axi.r.bits.resp <= io.ifu.r.bits.resp @[ifu.scala 105:22] - mem_ctl.io.ifu_axi.r.bits.data <= io.ifu.r.bits.data @[ifu.scala 105:22] - mem_ctl.io.ifu_axi.r.bits.id <= io.ifu.r.bits.id @[ifu.scala 105:22] - mem_ctl.io.ifu_axi.r.valid <= io.ifu.r.valid @[ifu.scala 105:22] - io.ifu.r.ready <= mem_ctl.io.ifu_axi.r.ready @[ifu.scala 105:22] - io.ifu.ar.bits.qos <= mem_ctl.io.ifu_axi.ar.bits.qos @[ifu.scala 105:22] - io.ifu.ar.bits.prot <= mem_ctl.io.ifu_axi.ar.bits.prot @[ifu.scala 105:22] - io.ifu.ar.bits.cache <= mem_ctl.io.ifu_axi.ar.bits.cache @[ifu.scala 105:22] - io.ifu.ar.bits.lock <= mem_ctl.io.ifu_axi.ar.bits.lock @[ifu.scala 105:22] - io.ifu.ar.bits.burst <= mem_ctl.io.ifu_axi.ar.bits.burst @[ifu.scala 105:22] - io.ifu.ar.bits.size <= mem_ctl.io.ifu_axi.ar.bits.size @[ifu.scala 105:22] - io.ifu.ar.bits.len <= mem_ctl.io.ifu_axi.ar.bits.len @[ifu.scala 105:22] - io.ifu.ar.bits.region <= mem_ctl.io.ifu_axi.ar.bits.region @[ifu.scala 105:22] - io.ifu.ar.bits.addr <= mem_ctl.io.ifu_axi.ar.bits.addr @[ifu.scala 105:22] - io.ifu.ar.bits.id <= mem_ctl.io.ifu_axi.ar.bits.id @[ifu.scala 105:22] - io.ifu.ar.valid <= mem_ctl.io.ifu_axi.ar.valid @[ifu.scala 105:22] - mem_ctl.io.ifu_axi.ar.ready <= io.ifu.ar.ready @[ifu.scala 105:22] - mem_ctl.io.ifu_axi.b.bits.id <= io.ifu.b.bits.id @[ifu.scala 105:22] - mem_ctl.io.ifu_axi.b.bits.resp <= io.ifu.b.bits.resp @[ifu.scala 105:22] - mem_ctl.io.ifu_axi.b.valid <= io.ifu.b.valid @[ifu.scala 105:22] - io.ifu.b.ready <= mem_ctl.io.ifu_axi.b.ready @[ifu.scala 105:22] - io.ifu.w.bits.last <= mem_ctl.io.ifu_axi.w.bits.last @[ifu.scala 105:22] - io.ifu.w.bits.strb <= mem_ctl.io.ifu_axi.w.bits.strb @[ifu.scala 105:22] - io.ifu.w.bits.data <= mem_ctl.io.ifu_axi.w.bits.data @[ifu.scala 105:22] - io.ifu.w.valid <= mem_ctl.io.ifu_axi.w.valid @[ifu.scala 105:22] - mem_ctl.io.ifu_axi.w.ready <= io.ifu.w.ready @[ifu.scala 105:22] - io.ifu.aw.bits.qos <= mem_ctl.io.ifu_axi.aw.bits.qos @[ifu.scala 105:22] - io.ifu.aw.bits.prot <= mem_ctl.io.ifu_axi.aw.bits.prot @[ifu.scala 105:22] - io.ifu.aw.bits.cache <= mem_ctl.io.ifu_axi.aw.bits.cache @[ifu.scala 105:22] - io.ifu.aw.bits.lock <= mem_ctl.io.ifu_axi.aw.bits.lock @[ifu.scala 105:22] - io.ifu.aw.bits.burst <= mem_ctl.io.ifu_axi.aw.bits.burst @[ifu.scala 105:22] - io.ifu.aw.bits.size <= mem_ctl.io.ifu_axi.aw.bits.size @[ifu.scala 105:22] - io.ifu.aw.bits.len <= mem_ctl.io.ifu_axi.aw.bits.len @[ifu.scala 105:22] - io.ifu.aw.bits.region <= mem_ctl.io.ifu_axi.aw.bits.region @[ifu.scala 105:22] - io.ifu.aw.bits.addr <= mem_ctl.io.ifu_axi.aw.bits.addr @[ifu.scala 105:22] - io.ifu.aw.bits.id <= mem_ctl.io.ifu_axi.aw.bits.id @[ifu.scala 105:22] - io.ifu.aw.valid <= mem_ctl.io.ifu_axi.aw.valid @[ifu.scala 105:22] - mem_ctl.io.ifu_axi.aw.ready <= io.ifu.aw.ready @[ifu.scala 105:22] - mem_ctl.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[ifu.scala 106:29] - mem_ctl.io.dma_mem_ctl.dma_mem_tag <= io.ifu_dma.dma_mem_ctl.dma_mem_tag @[ifu.scala 107:26] - mem_ctl.io.dma_mem_ctl.dma_mem_wdata <= io.ifu_dma.dma_mem_ctl.dma_mem_wdata @[ifu.scala 107:26] - mem_ctl.io.dma_mem_ctl.dma_mem_write <= io.ifu_dma.dma_mem_ctl.dma_mem_write @[ifu.scala 107:26] - mem_ctl.io.dma_mem_ctl.dma_mem_sz <= io.ifu_dma.dma_mem_ctl.dma_mem_sz @[ifu.scala 107:26] - mem_ctl.io.dma_mem_ctl.dma_mem_addr <= io.ifu_dma.dma_mem_ctl.dma_mem_addr @[ifu.scala 107:26] - mem_ctl.io.dma_mem_ctl.dma_iccm_req <= io.ifu_dma.dma_mem_ctl.dma_iccm_req @[ifu.scala 107:26] - io.ic.sel_premux_data <= mem_ctl.io.ic.sel_premux_data @[ifu.scala 108:17] - io.ic.premux_data <= mem_ctl.io.ic.premux_data @[ifu.scala 108:17] - io.ic.debug_way <= mem_ctl.io.ic.debug_way @[ifu.scala 108:17] - io.ic.debug_tag_array <= mem_ctl.io.ic.debug_tag_array @[ifu.scala 108:17] - io.ic.debug_wr_en <= mem_ctl.io.ic.debug_wr_en @[ifu.scala 108:17] - io.ic.debug_rd_en <= mem_ctl.io.ic.debug_rd_en @[ifu.scala 108:17] - mem_ctl.io.ic.tag_perr <= io.ic.tag_perr @[ifu.scala 108:17] - mem_ctl.io.ic.rd_hit <= io.ic.rd_hit @[ifu.scala 108:17] - mem_ctl.io.ic.parerr <= io.ic.parerr @[ifu.scala 108:17] - mem_ctl.io.ic.eccerr <= io.ic.eccerr @[ifu.scala 108:17] - mem_ctl.io.ic.tag_debug_rd_data <= io.ic.tag_debug_rd_data @[ifu.scala 108:17] - mem_ctl.io.ic.debug_rd_data <= io.ic.debug_rd_data @[ifu.scala 108:17] - mem_ctl.io.ic.rd_data <= io.ic.rd_data @[ifu.scala 108:17] - io.ic.debug_addr <= mem_ctl.io.ic.debug_addr @[ifu.scala 108:17] - io.ic.debug_wr_data <= mem_ctl.io.ic.debug_wr_data @[ifu.scala 108:17] - io.ic.wr_data[0] <= mem_ctl.io.ic.wr_data[0] @[ifu.scala 108:17] - io.ic.wr_data[1] <= mem_ctl.io.ic.wr_data[1] @[ifu.scala 108:17] - io.ic.rd_en <= mem_ctl.io.ic.rd_en @[ifu.scala 108:17] - io.ic.wr_en <= mem_ctl.io.ic.wr_en @[ifu.scala 108:17] - io.ic.tag_valid <= mem_ctl.io.ic.tag_valid @[ifu.scala 108:17] - io.ic.rw_addr <= mem_ctl.io.ic.rw_addr @[ifu.scala 108:17] - mem_ctl.io.iccm.rd_data_ecc <= io.iccm.rd_data_ecc @[ifu.scala 109:19] - mem_ctl.io.iccm.rd_data <= io.iccm.rd_data @[ifu.scala 109:19] - io.iccm.wr_data <= mem_ctl.io.iccm.wr_data @[ifu.scala 109:19] - io.iccm.wr_size <= mem_ctl.io.iccm.wr_size @[ifu.scala 109:19] - io.iccm.rden <= mem_ctl.io.iccm.rden @[ifu.scala 109:19] - io.iccm.wren <= mem_ctl.io.iccm.wren @[ifu.scala 109:19] - io.iccm.correction_state <= mem_ctl.io.iccm.correction_state @[ifu.scala 109:19] - io.iccm.buf_correct_ecc <= mem_ctl.io.iccm.buf_correct_ecc @[ifu.scala 109:19] - io.iccm.rw_addr <= mem_ctl.io.iccm.rw_addr @[ifu.scala 109:19] - mem_ctl.io.ifu_fetch_val <= mem_ctl.io.ic_fetch_val_f @[ifu.scala 110:28] + ifc_ctl.io.active_clk <= io.active_clk @[ifu.scala 42:25] + ifc_ctl.io.free_clk <= io.free_clk @[ifu.scala 43:23] + ifc_ctl.io.scan_mode <= io.scan_mode @[ifu.scala 44:24] + ifc_ctl.io.ic_hit_f <= mem_ctl.io.ic_hit_f @[ifu.scala 45:23] + ifc_ctl.io.ifu_fb_consume1 <= aln_ctl.io.ifu_fb_consume1 @[ifu.scala 46:30] + ifc_ctl.io.ifu_fb_consume2 <= aln_ctl.io.ifu_fb_consume2 @[ifu.scala 47:30] + io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall <= ifc_ctl.io.dec_ifc.ifu_pmu_fetch_stall @[ifu.scala 48:22] + ifc_ctl.io.dec_ifc.dec_tlu_mrac_ff <= io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[ifu.scala 48:22] + ifc_ctl.io.dec_ifc.dec_tlu_flush_noredir_wb <= io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb @[ifu.scala 48:22] + ifc_ctl.io.exu_flush_final <= io.exu_flush_final @[ifu.scala 49:30] + ifc_ctl.io.ifu_bp_hit_taken_f <= bp_ctl.io.ifu_bp_hit_taken_f @[ifu.scala 50:33] + ifc_ctl.io.ifu_bp_btb_target_f <= bp_ctl.io.ifu_bp_btb_target_f @[ifu.scala 51:34] + ifc_ctl.io.ic_dma_active <= mem_ctl.io.ic_dma_active @[ifu.scala 52:28] + ifc_ctl.io.ic_write_stall <= mem_ctl.io.ic_write_stall @[ifu.scala 53:29] + ifc_ctl.io.dma_ifc.dma_iccm_stall_any <= io.ifu_dma.dma_ifc.dma_iccm_stall_any @[ifu.scala 54:22] + ifc_ctl.io.ifu_ic_mb_empty <= mem_ctl.io.ifu_ic_mb_empty @[ifu.scala 55:30] + ifc_ctl.io.exu_flush_path_final <= io.exu_flush_path_final @[ifu.scala 56:35] + aln_ctl.io.scan_mode <= io.scan_mode @[ifu.scala 59:24] + aln_ctl.io.active_clk <= io.active_clk @[ifu.scala 60:25] + aln_ctl.io.ifu_async_error_start <= mem_ctl.io.ifu_async_error_start @[ifu.scala 61:36] + aln_ctl.io.iccm_rd_ecc_double_err <= mem_ctl.io.iccm_rd_ecc_double_err @[ifu.scala 62:37] + aln_ctl.io.ic_access_fault_f <= mem_ctl.io.ic_access_fault_f @[ifu.scala 63:32] + aln_ctl.io.ic_access_fault_type_f <= mem_ctl.io.ic_access_fault_type_f @[ifu.scala 64:37] + aln_ctl.io.ifu_bp_fghr_f <= bp_ctl.io.ifu_bp_fghr_f @[ifu.scala 65:28] + aln_ctl.io.ifu_bp_btb_target_f <= bp_ctl.io.ifu_bp_btb_target_f @[ifu.scala 66:34] + aln_ctl.io.ifu_bp_poffset_f <= bp_ctl.io.ifu_bp_poffset_f @[ifu.scala 67:31] + aln_ctl.io.ifu_bp_hist0_f <= bp_ctl.io.ifu_bp_hist0_f @[ifu.scala 68:29] + aln_ctl.io.ifu_bp_hist1_f <= bp_ctl.io.ifu_bp_hist1_f @[ifu.scala 69:29] + aln_ctl.io.ifu_bp_pc4_f <= bp_ctl.io.ifu_bp_pc4_f @[ifu.scala 70:27] + aln_ctl.io.ifu_bp_way_f <= bp_ctl.io.ifu_bp_way_f @[ifu.scala 71:27] + aln_ctl.io.ifu_bp_valid_f <= bp_ctl.io.ifu_bp_valid_f @[ifu.scala 72:29] + aln_ctl.io.ifu_bp_ret_f <= bp_ctl.io.ifu_bp_ret_f @[ifu.scala 73:27] + aln_ctl.io.exu_flush_final <= io.exu_flush_final @[ifu.scala 74:30] + io.ifu_dec.dec_aln.ifu_pmu_instr_aligned <= aln_ctl.io.dec_aln.ifu_pmu_instr_aligned @[ifu.scala 75:22] + io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.ret @[ifu.scala 75:22] + io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.way @[ifu.scala 75:22] + io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.prett @[ifu.scala 75:22] + io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.bank @[ifu.scala 75:22] + io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.br_start_error @[ifu.scala 75:22] + io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.br_error @[ifu.scala 75:22] + io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.hist @[ifu.scala 75:22] + io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset <= aln_ctl.io.dec_aln.aln_ib.i0_brp.bits.toffset @[ifu.scala 75:22] + io.ifu_dec.dec_aln.aln_ib.i0_brp.valid <= aln_ctl.io.dec_aln.aln_ib.i0_brp.valid @[ifu.scala 75:22] + io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_pc4 @[ifu.scala 75:22] + io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_pc @[ifu.scala 75:22] + io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_instr @[ifu.scala 75:22] + io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_valid @[ifu.scala 75:22] + io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_bp_btag @[ifu.scala 75:22] + io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_bp_fghr @[ifu.scala 75:22] + io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_bp_index @[ifu.scala 75:22] + io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_dbecc @[ifu.scala 75:22] + io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_icaf_f1 @[ifu.scala 75:22] + io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_icaf_type @[ifu.scala 75:22] + io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf <= aln_ctl.io.dec_aln.aln_ib.ifu_i0_icaf @[ifu.scala 75:22] + io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst <= aln_ctl.io.dec_aln.aln_dec.ifu_i0_cinst @[ifu.scala 75:22] + aln_ctl.io.dec_aln.aln_dec.dec_i0_decode_d <= io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d @[ifu.scala 75:22] + aln_ctl.io.ifu_fetch_data_f <= mem_ctl.io.ic_data_f @[ifu.scala 76:31] + aln_ctl.io.ifu_fetch_val <= mem_ctl.io.ifu_fetch_val @[ifu.scala 77:28] + aln_ctl.io.ifu_fetch_pc <= ifc_ctl.io.ifc_fetch_addr_f @[ifu.scala 78:27] + bp_ctl.io.scan_mode <= io.scan_mode @[ifu.scala 81:23] + bp_ctl.io.active_clk <= io.active_clk @[ifu.scala 82:24] + bp_ctl.io.ic_hit_f <= mem_ctl.io.ic_hit_f @[ifu.scala 83:22] + bp_ctl.io.ifc_fetch_addr_f <= ifc_ctl.io.ifc_fetch_addr_f @[ifu.scala 84:30] + bp_ctl.io.ifc_fetch_req_f <= ifc_ctl.io.ifc_fetch_req_f @[ifu.scala 85:29] + bp_ctl.io.dec_bp.dec_tlu_bpred_disable <= io.ifu_dec.dec_bp.dec_tlu_bpred_disable @[ifu.scala 86:20] + bp_ctl.io.dec_bp.dec_tlu_flush_leak_one_wb <= io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb @[ifu.scala 86:20] + bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle @[ifu.scala 86:20] + bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.bits.way <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way @[ifu.scala 86:20] + bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[ifu.scala 86:20] + bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error @[ifu.scala 86:20] + bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist @[ifu.scala 86:20] + bp_ctl.io.dec_bp.dec_tlu_br0_r_pkt.valid <= io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid @[ifu.scala 86:20] + bp_ctl.io.exu_bp.exu_mp_btag <= io.exu_ifu.exu_bp.exu_mp_btag @[ifu.scala 87:20] + bp_ctl.io.exu_bp.exu_mp_index <= io.exu_ifu.exu_bp.exu_mp_index @[ifu.scala 87:20] + bp_ctl.io.exu_bp.exu_mp_fghr <= io.exu_ifu.exu_bp.exu_mp_fghr @[ifu.scala 87:20] + bp_ctl.io.exu_bp.exu_mp_eghr <= io.exu_ifu.exu_bp.exu_mp_eghr @[ifu.scala 87:20] + bp_ctl.io.exu_bp.exu_mp_pkt.bits.way <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.way @[ifu.scala 87:20] + bp_ctl.io.exu_bp.exu_mp_pkt.bits.pja <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.pja @[ifu.scala 87:20] + bp_ctl.io.exu_bp.exu_mp_pkt.bits.pret <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.pret @[ifu.scala 87:20] + bp_ctl.io.exu_bp.exu_mp_pkt.bits.pcall <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.pcall @[ifu.scala 87:20] + bp_ctl.io.exu_bp.exu_mp_pkt.bits.prett <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.prett @[ifu.scala 87:20] + bp_ctl.io.exu_bp.exu_mp_pkt.bits.br_start_error <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_start_error @[ifu.scala 87:20] + bp_ctl.io.exu_bp.exu_mp_pkt.bits.br_error <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_error @[ifu.scala 87:20] + bp_ctl.io.exu_bp.exu_mp_pkt.bits.toffset <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.toffset @[ifu.scala 87:20] + bp_ctl.io.exu_bp.exu_mp_pkt.bits.hist <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.hist @[ifu.scala 87:20] + bp_ctl.io.exu_bp.exu_mp_pkt.bits.pc4 <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.pc4 @[ifu.scala 87:20] + bp_ctl.io.exu_bp.exu_mp_pkt.bits.boffset <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.boffset @[ifu.scala 87:20] + bp_ctl.io.exu_bp.exu_mp_pkt.bits.ataken <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.ataken @[ifu.scala 87:20] + bp_ctl.io.exu_bp.exu_mp_pkt.bits.misp <= io.exu_ifu.exu_bp.exu_mp_pkt.bits.misp @[ifu.scala 87:20] + bp_ctl.io.exu_bp.exu_mp_pkt.valid <= io.exu_ifu.exu_bp.exu_mp_pkt.valid @[ifu.scala 87:20] + bp_ctl.io.exu_bp.exu_i0_br_way_r <= io.exu_ifu.exu_bp.exu_i0_br_way_r @[ifu.scala 87:20] + bp_ctl.io.exu_bp.exu_i0_br_fghr_r <= io.exu_ifu.exu_bp.exu_i0_br_fghr_r @[ifu.scala 87:20] + bp_ctl.io.exu_bp.exu_i0_br_index_r <= io.exu_ifu.exu_bp.exu_i0_br_index_r @[ifu.scala 87:20] + bp_ctl.io.exu_flush_final <= io.exu_flush_final @[ifu.scala 88:29] + bp_ctl.io.dec_tlu_flush_lower_wb <= io.dec_tlu_flush_lower_wb @[ifu.scala 89:36] + mem_ctl.io.free_clk <= io.free_clk @[ifu.scala 91:23] + mem_ctl.io.active_clk <= io.active_clk @[ifu.scala 92:25] + mem_ctl.io.exu_flush_final <= io.exu_flush_final @[ifu.scala 93:30] + io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle <= mem_ctl.io.dec_mem_ctrl.ifu_miss_state_idle @[ifu.scala 94:27] + io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= mem_ctl.io.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[ifu.scala 94:27] + io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data <= mem_ctl.io.dec_mem_ctrl.ifu_ic_debug_rd_data @[ifu.scala 94:27] + io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= mem_ctl.io.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[ifu.scala 94:27] + io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start <= mem_ctl.io.dec_mem_ctrl.ifu_ic_error_start @[ifu.scala 94:27] + io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn <= mem_ctl.io.dec_mem_ctrl.ifu_pmu_bus_trxn @[ifu.scala 94:27] + io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy <= mem_ctl.io.dec_mem_ctrl.ifu_pmu_bus_busy @[ifu.scala 94:27] + io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error <= mem_ctl.io.dec_mem_ctrl.ifu_pmu_bus_error @[ifu.scala 94:27] + io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit <= mem_ctl.io.dec_mem_ctrl.ifu_pmu_ic_hit @[ifu.scala 94:27] + io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss <= mem_ctl.io.dec_mem_ctrl.ifu_pmu_ic_miss @[ifu.scala 94:27] + mem_ctl.io.dec_mem_ctrl.dec_tlu_core_ecc_disable <= io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[ifu.scala 94:27] + mem_ctl.io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[ifu.scala 94:27] + mem_ctl.io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[ifu.scala 94:27] + mem_ctl.io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[ifu.scala 94:27] + mem_ctl.io.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[ifu.scala 94:27] + mem_ctl.io.dec_mem_ctrl.dec_tlu_fence_i_wb <= io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb @[ifu.scala 94:27] + mem_ctl.io.dec_mem_ctrl.dec_tlu_force_halt <= io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[ifu.scala 94:27] + mem_ctl.io.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt @[ifu.scala 94:27] + mem_ctl.io.dec_mem_ctrl.dec_tlu_flush_err_wb <= io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb @[ifu.scala 94:27] + mem_ctl.io.ifc_fetch_addr_bf <= ifc_ctl.io.ifc_fetch_addr_bf @[ifu.scala 95:32] + mem_ctl.io.ifc_fetch_uncacheable_bf <= ifc_ctl.io.ifc_fetch_uncacheable_bf @[ifu.scala 96:39] + mem_ctl.io.ifc_fetch_req_bf <= ifc_ctl.io.ifc_fetch_req_bf @[ifu.scala 97:31] + mem_ctl.io.ifc_fetch_req_bf_raw <= ifc_ctl.io.ifc_fetch_req_bf_raw @[ifu.scala 98:35] + mem_ctl.io.ifc_iccm_access_bf <= ifc_ctl.io.ifc_iccm_access_bf @[ifu.scala 99:33] + mem_ctl.io.ifc_region_acc_fault_bf <= ifc_ctl.io.ifc_region_acc_fault_bf @[ifu.scala 100:38] + mem_ctl.io.ifc_dma_access_ok <= ifc_ctl.io.ifc_dma_access_ok @[ifu.scala 101:32] + mem_ctl.io.ifu_bp_hit_taken_f <= bp_ctl.io.ifu_bp_hit_taken_f @[ifu.scala 102:33] + mem_ctl.io.ifu_bp_inst_mask_f <= bp_ctl.io.ifu_bp_inst_mask_f @[ifu.scala 103:33] + mem_ctl.io.ifu_axi.r.bits.last <= io.ifu.r.bits.last @[ifu.scala 104:22] + mem_ctl.io.ifu_axi.r.bits.resp <= io.ifu.r.bits.resp @[ifu.scala 104:22] + mem_ctl.io.ifu_axi.r.bits.data <= io.ifu.r.bits.data @[ifu.scala 104:22] + mem_ctl.io.ifu_axi.r.bits.id <= io.ifu.r.bits.id @[ifu.scala 104:22] + mem_ctl.io.ifu_axi.r.valid <= io.ifu.r.valid @[ifu.scala 104:22] + io.ifu.r.ready <= mem_ctl.io.ifu_axi.r.ready @[ifu.scala 104:22] + io.ifu.ar.bits.qos <= mem_ctl.io.ifu_axi.ar.bits.qos @[ifu.scala 104:22] + io.ifu.ar.bits.prot <= mem_ctl.io.ifu_axi.ar.bits.prot @[ifu.scala 104:22] + io.ifu.ar.bits.cache <= mem_ctl.io.ifu_axi.ar.bits.cache @[ifu.scala 104:22] + io.ifu.ar.bits.lock <= mem_ctl.io.ifu_axi.ar.bits.lock @[ifu.scala 104:22] + io.ifu.ar.bits.burst <= mem_ctl.io.ifu_axi.ar.bits.burst @[ifu.scala 104:22] + io.ifu.ar.bits.size <= mem_ctl.io.ifu_axi.ar.bits.size @[ifu.scala 104:22] + io.ifu.ar.bits.len <= mem_ctl.io.ifu_axi.ar.bits.len @[ifu.scala 104:22] + io.ifu.ar.bits.region <= mem_ctl.io.ifu_axi.ar.bits.region @[ifu.scala 104:22] + io.ifu.ar.bits.addr <= mem_ctl.io.ifu_axi.ar.bits.addr @[ifu.scala 104:22] + io.ifu.ar.bits.id <= mem_ctl.io.ifu_axi.ar.bits.id @[ifu.scala 104:22] + io.ifu.ar.valid <= mem_ctl.io.ifu_axi.ar.valid @[ifu.scala 104:22] + mem_ctl.io.ifu_axi.ar.ready <= io.ifu.ar.ready @[ifu.scala 104:22] + mem_ctl.io.ifu_axi.b.bits.id <= io.ifu.b.bits.id @[ifu.scala 104:22] + mem_ctl.io.ifu_axi.b.bits.resp <= io.ifu.b.bits.resp @[ifu.scala 104:22] + mem_ctl.io.ifu_axi.b.valid <= io.ifu.b.valid @[ifu.scala 104:22] + io.ifu.b.ready <= mem_ctl.io.ifu_axi.b.ready @[ifu.scala 104:22] + io.ifu.w.bits.last <= mem_ctl.io.ifu_axi.w.bits.last @[ifu.scala 104:22] + io.ifu.w.bits.strb <= mem_ctl.io.ifu_axi.w.bits.strb @[ifu.scala 104:22] + io.ifu.w.bits.data <= mem_ctl.io.ifu_axi.w.bits.data @[ifu.scala 104:22] + io.ifu.w.valid <= mem_ctl.io.ifu_axi.w.valid @[ifu.scala 104:22] + mem_ctl.io.ifu_axi.w.ready <= io.ifu.w.ready @[ifu.scala 104:22] + io.ifu.aw.bits.qos <= mem_ctl.io.ifu_axi.aw.bits.qos @[ifu.scala 104:22] + io.ifu.aw.bits.prot <= mem_ctl.io.ifu_axi.aw.bits.prot @[ifu.scala 104:22] + io.ifu.aw.bits.cache <= mem_ctl.io.ifu_axi.aw.bits.cache @[ifu.scala 104:22] + io.ifu.aw.bits.lock <= mem_ctl.io.ifu_axi.aw.bits.lock @[ifu.scala 104:22] + io.ifu.aw.bits.burst <= mem_ctl.io.ifu_axi.aw.bits.burst @[ifu.scala 104:22] + io.ifu.aw.bits.size <= mem_ctl.io.ifu_axi.aw.bits.size @[ifu.scala 104:22] + io.ifu.aw.bits.len <= mem_ctl.io.ifu_axi.aw.bits.len @[ifu.scala 104:22] + io.ifu.aw.bits.region <= mem_ctl.io.ifu_axi.aw.bits.region @[ifu.scala 104:22] + io.ifu.aw.bits.addr <= mem_ctl.io.ifu_axi.aw.bits.addr @[ifu.scala 104:22] + io.ifu.aw.bits.id <= mem_ctl.io.ifu_axi.aw.bits.id @[ifu.scala 104:22] + io.ifu.aw.valid <= mem_ctl.io.ifu_axi.aw.valid @[ifu.scala 104:22] + mem_ctl.io.ifu_axi.aw.ready <= io.ifu.aw.ready @[ifu.scala 104:22] + mem_ctl.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[ifu.scala 105:29] + mem_ctl.io.dma_mem_ctl.dma_mem_tag <= io.ifu_dma.dma_mem_ctl.dma_mem_tag @[ifu.scala 106:26] + mem_ctl.io.dma_mem_ctl.dma_mem_wdata <= io.ifu_dma.dma_mem_ctl.dma_mem_wdata @[ifu.scala 106:26] + mem_ctl.io.dma_mem_ctl.dma_mem_write <= io.ifu_dma.dma_mem_ctl.dma_mem_write @[ifu.scala 106:26] + mem_ctl.io.dma_mem_ctl.dma_mem_sz <= io.ifu_dma.dma_mem_ctl.dma_mem_sz @[ifu.scala 106:26] + mem_ctl.io.dma_mem_ctl.dma_mem_addr <= io.ifu_dma.dma_mem_ctl.dma_mem_addr @[ifu.scala 106:26] + mem_ctl.io.dma_mem_ctl.dma_iccm_req <= io.ifu_dma.dma_mem_ctl.dma_iccm_req @[ifu.scala 106:26] + io.ic.sel_premux_data <= mem_ctl.io.ic.sel_premux_data @[ifu.scala 107:17] + io.ic.premux_data <= mem_ctl.io.ic.premux_data @[ifu.scala 107:17] + io.ic.debug_way <= mem_ctl.io.ic.debug_way @[ifu.scala 107:17] + io.ic.debug_tag_array <= mem_ctl.io.ic.debug_tag_array @[ifu.scala 107:17] + io.ic.debug_wr_en <= mem_ctl.io.ic.debug_wr_en @[ifu.scala 107:17] + io.ic.debug_rd_en <= mem_ctl.io.ic.debug_rd_en @[ifu.scala 107:17] + mem_ctl.io.ic.tag_perr <= io.ic.tag_perr @[ifu.scala 107:17] + mem_ctl.io.ic.rd_hit <= io.ic.rd_hit @[ifu.scala 107:17] + mem_ctl.io.ic.parerr <= io.ic.parerr @[ifu.scala 107:17] + mem_ctl.io.ic.eccerr <= io.ic.eccerr @[ifu.scala 107:17] + mem_ctl.io.ic.tag_debug_rd_data <= io.ic.tag_debug_rd_data @[ifu.scala 107:17] + mem_ctl.io.ic.debug_rd_data <= io.ic.debug_rd_data @[ifu.scala 107:17] + mem_ctl.io.ic.rd_data <= io.ic.rd_data @[ifu.scala 107:17] + io.ic.debug_addr <= mem_ctl.io.ic.debug_addr @[ifu.scala 107:17] + io.ic.debug_wr_data <= mem_ctl.io.ic.debug_wr_data @[ifu.scala 107:17] + io.ic.wr_data[0] <= mem_ctl.io.ic.wr_data[0] @[ifu.scala 107:17] + io.ic.wr_data[1] <= mem_ctl.io.ic.wr_data[1] @[ifu.scala 107:17] + io.ic.rd_en <= mem_ctl.io.ic.rd_en @[ifu.scala 107:17] + io.ic.wr_en <= mem_ctl.io.ic.wr_en @[ifu.scala 107:17] + io.ic.tag_valid <= mem_ctl.io.ic.tag_valid @[ifu.scala 107:17] + io.ic.rw_addr <= mem_ctl.io.ic.rw_addr @[ifu.scala 107:17] + mem_ctl.io.iccm.rd_data_ecc <= io.iccm.rd_data_ecc @[ifu.scala 108:19] + mem_ctl.io.iccm.rd_data <= io.iccm.rd_data @[ifu.scala 108:19] + io.iccm.wr_data <= mem_ctl.io.iccm.wr_data @[ifu.scala 108:19] + io.iccm.wr_size <= mem_ctl.io.iccm.wr_size @[ifu.scala 108:19] + io.iccm.rden <= mem_ctl.io.iccm.rden @[ifu.scala 108:19] + io.iccm.wren <= mem_ctl.io.iccm.wren @[ifu.scala 108:19] + io.iccm.correction_state <= mem_ctl.io.iccm.correction_state @[ifu.scala 108:19] + io.iccm.buf_correct_ecc <= mem_ctl.io.iccm.buf_correct_ecc @[ifu.scala 108:19] + io.iccm.rw_addr <= mem_ctl.io.iccm.rw_addr @[ifu.scala 108:19] + mem_ctl.io.ifu_fetch_val <= mem_ctl.io.ic_fetch_val_f @[ifu.scala 109:28] + mem_ctl.io.dec_tlu_flush_lower_wb <= io.dec_tlu_flush_lower_wb @[ifu.scala 110:37] mem_ctl.io.scan_mode <= io.scan_mode @[ifu.scala 111:24] io.iccm_dma_ecc_error <= mem_ctl.io.iccm_dma_ecc_error @[ifu.scala 113:25] io.iccm_dma_rvalid <= mem_ctl.io.iccm_dma_rvalid @[ifu.scala 114:22] @@ -66826,7 +66826,7 @@ circuit quasar_wrapper : module dec_decode_ctl : input clock : Clock input reset : AsyncReset - output io : {flip decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, flip dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, flip dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, div_waddr_wb : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>, flip dec_aln : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}} + output io : {flip decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, flip dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, flip dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, flip dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, div_waddr_wb : UInt<5>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>, flip dec_aln : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}} wire _T : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}} @[dec_decode_ctl.scala 97:38] _T.bits.bfp <= UInt<1>("h00") @[dec_decode_ctl.scala 97:38] @@ -68193,9 +68193,9 @@ circuit quasar_wrapper : node _T_485 = or(_T_484, i0_load_block_d) @[dec_decode_ctl.scala 513:72] node _T_486 = or(_T_485, i0_nonblock_div_stall) @[dec_decode_ctl.scala 514:21] node i0_block_raw_d = or(_T_486, i0_div_prior_div_stall) @[dec_decode_ctl.scala 514:45] - node _T_487 = or(io.lsu_store_stall_any, io.dma_dccm_stall_any) @[dec_decode_ctl.scala 516:65] + node _T_487 = or(io.lsu_store_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 516:65] node i0_store_stall_d = and(i0_dp.store, _T_487) @[dec_decode_ctl.scala 516:39] - node _T_488 = or(io.lsu_load_stall_any, io.dma_dccm_stall_any) @[dec_decode_ctl.scala 517:63] + node _T_488 = or(io.lsu_load_stall_any, io.dctl_dma.dma_dccm_stall_any) @[dec_decode_ctl.scala 517:63] node i0_load_stall_d = and(i0_dp.load, _T_488) @[dec_decode_ctl.scala 517:38] node _T_489 = or(i0_block_raw_d, i0_store_stall_d) @[dec_decode_ctl.scala 518:38] node i0_block_d = or(_T_489, i0_load_stall_d) @[dec_decode_ctl.scala 518:57] @@ -69310,11 +69310,11 @@ circuit quasar_wrapper : io.decode_exu.dec_i0_rs2_bypass_data_d <= _T_989 @[dec_decode_ctl.scala 782:42] node _T_990 = or(i0_dp_raw.load, i0_dp_raw.store) @[dec_decode_ctl.scala 787:68] node _T_991 = and(io.dec_ib0_valid_d, _T_990) @[dec_decode_ctl.scala 787:50] - node _T_992 = eq(io.dma_dccm_stall_any, UInt<1>("h00")) @[dec_decode_ctl.scala 787:89] + node _T_992 = eq(io.dctl_dma.dma_dccm_stall_any, UInt<1>("h00")) @[dec_decode_ctl.scala 787:89] node _T_993 = and(_T_991, _T_992) @[dec_decode_ctl.scala 787:87] - node _T_994 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 787:114] - node _T_995 = and(_T_993, _T_994) @[dec_decode_ctl.scala 787:112] - node _T_996 = or(_T_995, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 787:131] + node _T_994 = eq(i0_block_raw_d, UInt<1>("h00")) @[dec_decode_ctl.scala 787:123] + node _T_995 = and(_T_993, _T_994) @[dec_decode_ctl.scala 787:121] + node _T_996 = or(_T_995, io.decode_exu.dec_extint_stall) @[dec_decode_ctl.scala 787:140] io.dec_lsu_valid_raw_d <= _T_996 @[dec_decode_ctl.scala 787:26] node _T_997 = eq(io.decode_exu.dec_extint_stall, UInt<1>("h00")) @[dec_decode_ctl.scala 789:6] node _T_998 = and(_T_997, i0_dp.lsu) @[dec_decode_ctl.scala 789:38] @@ -71681,32 +71681,32 @@ circuit quasar_wrapper : mitcnt1 <= UInt<1>("h00") wire mitcnt0 : UInt<32> mitcnt0 <= UInt<1>("h00") - node mit0_match_ns = geq(mitcnt0, mitb0) @[dec_tlu_ctl.scala 2678:36] - node mit1_match_ns = geq(mitcnt1, mitb1) @[dec_tlu_ctl.scala 2679:36] - io.dec_timer_t0_pulse <= mit0_match_ns @[dec_tlu_ctl.scala 2681:31] - io.dec_timer_t1_pulse <= mit1_match_ns @[dec_tlu_ctl.scala 2682:31] - node _T = eq(io.dec_csr_wraddr_r, UInt<12>("h07d2")) @[dec_tlu_ctl.scala 2689:72] - node wr_mitcnt0_r = and(io.dec_csr_wen_r_mod, _T) @[dec_tlu_ctl.scala 2689:49] - node _T_1 = bits(mitctl0, 0, 0) @[dec_tlu_ctl.scala 2691:37] - node _T_2 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2691:56] - node _T_3 = bits(mitctl0, 2, 2) @[dec_tlu_ctl.scala 2691:85] - node _T_4 = or(_T_2, _T_3) @[dec_tlu_ctl.scala 2691:76] - node _T_5 = and(_T_1, _T_4) @[dec_tlu_ctl.scala 2691:53] - node _T_6 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2691:112] - node _T_7 = bits(mitctl0, 1, 1) @[dec_tlu_ctl.scala 2691:147] - node _T_8 = or(_T_6, _T_7) @[dec_tlu_ctl.scala 2691:138] - node _T_9 = and(_T_5, _T_8) @[dec_tlu_ctl.scala 2691:109] - node _T_10 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2691:173] - node mitcnt0_inc_ok = and(_T_9, _T_10) @[dec_tlu_ctl.scala 2691:171] - node _T_11 = add(mitcnt0, UInt<32>("h01")) @[dec_tlu_ctl.scala 2692:35] - node mitcnt0_inc = tail(_T_11, 1) @[dec_tlu_ctl.scala 2692:35] - node _T_12 = bits(mit0_match_ns, 0, 0) @[dec_tlu_ctl.scala 2693:44] - node _T_13 = bits(wr_mitcnt0_r, 0, 0) @[dec_tlu_ctl.scala 2693:74] - node _T_14 = mux(_T_13, io.dec_csr_wrdata_r, mitcnt0_inc) @[dec_tlu_ctl.scala 2693:60] - node mitcnt0_ns = mux(_T_12, UInt<1>("h00"), _T_14) @[dec_tlu_ctl.scala 2693:29] - node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[dec_tlu_ctl.scala 2694:59] - node _T_16 = or(_T_15, mit0_match_ns) @[dec_tlu_ctl.scala 2694:76] - node _T_17 = bits(_T_16, 0, 0) @[dec_tlu_ctl.scala 2694:93] + node mit0_match_ns = geq(mitcnt0, mitb0) @[dec_tlu_ctl.scala 2674:36] + node mit1_match_ns = geq(mitcnt1, mitb1) @[dec_tlu_ctl.scala 2675:36] + io.dec_timer_t0_pulse <= mit0_match_ns @[dec_tlu_ctl.scala 2677:31] + io.dec_timer_t1_pulse <= mit1_match_ns @[dec_tlu_ctl.scala 2678:31] + node _T = eq(io.dec_csr_wraddr_r, UInt<12>("h07d2")) @[dec_tlu_ctl.scala 2685:72] + node wr_mitcnt0_r = and(io.dec_csr_wen_r_mod, _T) @[dec_tlu_ctl.scala 2685:49] + node _T_1 = bits(mitctl0, 0, 0) @[dec_tlu_ctl.scala 2687:37] + node _T_2 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2687:56] + node _T_3 = bits(mitctl0, 2, 2) @[dec_tlu_ctl.scala 2687:85] + node _T_4 = or(_T_2, _T_3) @[dec_tlu_ctl.scala 2687:76] + node _T_5 = and(_T_1, _T_4) @[dec_tlu_ctl.scala 2687:53] + node _T_6 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2687:112] + node _T_7 = bits(mitctl0, 1, 1) @[dec_tlu_ctl.scala 2687:147] + node _T_8 = or(_T_6, _T_7) @[dec_tlu_ctl.scala 2687:138] + node _T_9 = and(_T_5, _T_8) @[dec_tlu_ctl.scala 2687:109] + node _T_10 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2687:173] + node mitcnt0_inc_ok = and(_T_9, _T_10) @[dec_tlu_ctl.scala 2687:171] + node _T_11 = add(mitcnt0, UInt<32>("h01")) @[dec_tlu_ctl.scala 2688:35] + node mitcnt0_inc = tail(_T_11, 1) @[dec_tlu_ctl.scala 2688:35] + node _T_12 = bits(mit0_match_ns, 0, 0) @[dec_tlu_ctl.scala 2689:44] + node _T_13 = bits(wr_mitcnt0_r, 0, 0) @[dec_tlu_ctl.scala 2689:74] + node _T_14 = mux(_T_13, io.dec_csr_wrdata_r, mitcnt0_inc) @[dec_tlu_ctl.scala 2689:60] + node mitcnt0_ns = mux(_T_12, UInt<1>("h00"), _T_14) @[dec_tlu_ctl.scala 2689:29] + node _T_15 = or(wr_mitcnt0_r, mitcnt0_inc_ok) @[dec_tlu_ctl.scala 2690:59] + node _T_16 = or(_T_15, mit0_match_ns) @[dec_tlu_ctl.scala 2690:76] + node _T_17 = bits(_T_16, 0, 0) @[dec_tlu_ctl.scala 2690:93] inst rvclkhdr of rvclkhdr_712 @[lib.scala 352:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -71715,34 +71715,34 @@ circuit quasar_wrapper : rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_18 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_18 <= mitcnt0_ns @[lib.scala 358:16] - mitcnt0 <= _T_18 @[dec_tlu_ctl.scala 2694:25] - node _T_19 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[dec_tlu_ctl.scala 2701:72] - node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_19) @[dec_tlu_ctl.scala 2701:49] - node _T_20 = bits(mitctl1, 0, 0) @[dec_tlu_ctl.scala 2703:37] - node _T_21 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2703:56] - node _T_22 = bits(mitctl1, 2, 2) @[dec_tlu_ctl.scala 2703:85] - node _T_23 = or(_T_21, _T_22) @[dec_tlu_ctl.scala 2703:76] - node _T_24 = and(_T_20, _T_23) @[dec_tlu_ctl.scala 2703:53] - node _T_25 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2703:112] - node _T_26 = bits(mitctl1, 1, 1) @[dec_tlu_ctl.scala 2703:147] - node _T_27 = or(_T_25, _T_26) @[dec_tlu_ctl.scala 2703:138] - node _T_28 = and(_T_24, _T_27) @[dec_tlu_ctl.scala 2703:109] - node _T_29 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2703:173] - node mitcnt1_inc_ok = and(_T_28, _T_29) @[dec_tlu_ctl.scala 2703:171] + mitcnt0 <= _T_18 @[dec_tlu_ctl.scala 2690:25] + node _T_19 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d5")) @[dec_tlu_ctl.scala 2697:72] + node wr_mitcnt1_r = and(io.dec_csr_wen_r_mod, _T_19) @[dec_tlu_ctl.scala 2697:49] + node _T_20 = bits(mitctl1, 0, 0) @[dec_tlu_ctl.scala 2699:37] + node _T_21 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 2699:56] + node _T_22 = bits(mitctl1, 2, 2) @[dec_tlu_ctl.scala 2699:85] + node _T_23 = or(_T_21, _T_22) @[dec_tlu_ctl.scala 2699:76] + node _T_24 = and(_T_20, _T_23) @[dec_tlu_ctl.scala 2699:53] + node _T_25 = not(io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2699:112] + node _T_26 = bits(mitctl1, 1, 1) @[dec_tlu_ctl.scala 2699:147] + node _T_27 = or(_T_25, _T_26) @[dec_tlu_ctl.scala 2699:138] + node _T_28 = and(_T_24, _T_27) @[dec_tlu_ctl.scala 2699:109] + node _T_29 = not(io.internal_dbg_halt_timers) @[dec_tlu_ctl.scala 2699:173] + node mitcnt1_inc_ok = and(_T_28, _T_29) @[dec_tlu_ctl.scala 2699:171] node _T_30 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] - node _T_31 = bits(mitctl1, 3, 3) @[dec_tlu_ctl.scala 2706:68] - node _T_32 = not(_T_31) @[dec_tlu_ctl.scala 2706:60] - node _T_33 = or(_T_32, mit0_match_ns) @[dec_tlu_ctl.scala 2706:72] + node _T_31 = bits(mitctl1, 3, 3) @[dec_tlu_ctl.scala 2702:68] + node _T_32 = not(_T_31) @[dec_tlu_ctl.scala 2702:60] + node _T_33 = or(_T_32, mit0_match_ns) @[dec_tlu_ctl.scala 2702:72] node _T_34 = cat(_T_30, _T_33) @[Cat.scala 29:58] - node _T_35 = add(mitcnt1, _T_34) @[dec_tlu_ctl.scala 2706:35] - node mitcnt1_inc = tail(_T_35, 1) @[dec_tlu_ctl.scala 2706:35] - node _T_36 = bits(mit1_match_ns, 0, 0) @[dec_tlu_ctl.scala 2707:45] - node _T_37 = bits(wr_mitcnt1_r, 0, 0) @[dec_tlu_ctl.scala 2707:75] - node _T_38 = mux(_T_37, io.dec_csr_wrdata_r, mitcnt1_inc) @[dec_tlu_ctl.scala 2707:61] - node mitcnt1_ns = mux(_T_36, UInt<1>("h00"), _T_38) @[dec_tlu_ctl.scala 2707:30] - node _T_39 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[dec_tlu_ctl.scala 2708:60] - node _T_40 = or(_T_39, mit1_match_ns) @[dec_tlu_ctl.scala 2708:77] - node _T_41 = bits(_T_40, 0, 0) @[dec_tlu_ctl.scala 2708:94] + node _T_35 = add(mitcnt1, _T_34) @[dec_tlu_ctl.scala 2702:35] + node mitcnt1_inc = tail(_T_35, 1) @[dec_tlu_ctl.scala 2702:35] + node _T_36 = bits(mit1_match_ns, 0, 0) @[dec_tlu_ctl.scala 2703:45] + node _T_37 = bits(wr_mitcnt1_r, 0, 0) @[dec_tlu_ctl.scala 2703:75] + node _T_38 = mux(_T_37, io.dec_csr_wrdata_r, mitcnt1_inc) @[dec_tlu_ctl.scala 2703:61] + node mitcnt1_ns = mux(_T_36, UInt<1>("h00"), _T_38) @[dec_tlu_ctl.scala 2703:30] + node _T_39 = or(wr_mitcnt1_r, mitcnt1_inc_ok) @[dec_tlu_ctl.scala 2704:60] + node _T_40 = or(_T_39, mit1_match_ns) @[dec_tlu_ctl.scala 2704:77] + node _T_41 = bits(_T_40, 0, 0) @[dec_tlu_ctl.scala 2704:94] inst rvclkhdr_1 of rvclkhdr_713 @[lib.scala 352:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -71751,11 +71751,11 @@ circuit quasar_wrapper : rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_42 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_42 <= mitcnt1_ns @[lib.scala 358:16] - mitcnt1 <= _T_42 @[dec_tlu_ctl.scala 2708:25] - node _T_43 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[dec_tlu_ctl.scala 2715:70] - node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_43) @[dec_tlu_ctl.scala 2715:47] - node _T_44 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2716:38] - node _T_45 = bits(wr_mitb0_r, 0, 0) @[dec_tlu_ctl.scala 2716:71] + mitcnt1 <= _T_42 @[dec_tlu_ctl.scala 2704:25] + node _T_43 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d3")) @[dec_tlu_ctl.scala 2711:70] + node wr_mitb0_r = and(io.dec_csr_wen_r_mod, _T_43) @[dec_tlu_ctl.scala 2711:47] + node _T_44 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2712:38] + node _T_45 = bits(wr_mitb0_r, 0, 0) @[dec_tlu_ctl.scala 2712:71] inst rvclkhdr_2 of rvclkhdr_714 @[lib.scala 352:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -71764,12 +71764,12 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg mitb0_b : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] mitb0_b <= _T_44 @[lib.scala 358:16] - node _T_46 = not(mitb0_b) @[dec_tlu_ctl.scala 2717:22] - mitb0 <= _T_46 @[dec_tlu_ctl.scala 2717:19] - node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[dec_tlu_ctl.scala 2724:69] - node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[dec_tlu_ctl.scala 2724:47] - node _T_48 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2725:29] - node _T_49 = bits(wr_mitb1_r, 0, 0) @[dec_tlu_ctl.scala 2725:62] + node _T_46 = not(mitb0_b) @[dec_tlu_ctl.scala 2713:22] + mitb0 <= _T_46 @[dec_tlu_ctl.scala 2713:19] + node _T_47 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d6")) @[dec_tlu_ctl.scala 2720:69] + node wr_mitb1_r = and(io.dec_csr_wen_r_mod, _T_47) @[dec_tlu_ctl.scala 2720:47] + node _T_48 = not(io.dec_csr_wrdata_r) @[dec_tlu_ctl.scala 2721:29] + node _T_49 = bits(wr_mitb1_r, 0, 0) @[dec_tlu_ctl.scala 2721:62] inst rvclkhdr_3 of rvclkhdr_715 @[lib.scala 352:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -71778,55 +71778,55 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg mitb1_b : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] mitb1_b <= _T_48 @[lib.scala 358:16] - node _T_50 = not(mitb1_b) @[dec_tlu_ctl.scala 2726:18] - mitb1 <= _T_50 @[dec_tlu_ctl.scala 2726:15] - node _T_51 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[dec_tlu_ctl.scala 2737:72] - node wr_mitctl0_r = and(io.dec_csr_wen_r_mod, _T_51) @[dec_tlu_ctl.scala 2737:49] - node _T_52 = bits(wr_mitctl0_r, 0, 0) @[dec_tlu_ctl.scala 2738:45] - node _T_53 = bits(io.dec_csr_wrdata_r, 2, 0) @[dec_tlu_ctl.scala 2738:72] - node _T_54 = bits(mitctl0, 2, 0) @[dec_tlu_ctl.scala 2738:86] - node mitctl0_ns = mux(_T_52, _T_53, _T_54) @[dec_tlu_ctl.scala 2738:31] - node _T_55 = bits(mitctl0_ns, 0, 0) @[dec_tlu_ctl.scala 2740:41] - node mitctl0_0_b_ns = not(_T_55) @[dec_tlu_ctl.scala 2740:30] - reg mitctl0_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2741:60] - mitctl0_0_b <= mitctl0_0_b_ns @[dec_tlu_ctl.scala 2741:60] - node _T_56 = bits(mitctl0_ns, 2, 1) @[dec_tlu_ctl.scala 2742:78] - reg _T_57 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2742:67] - _T_57 <= _T_56 @[dec_tlu_ctl.scala 2742:67] - node _T_58 = not(mitctl0_0_b) @[dec_tlu_ctl.scala 2742:90] + node _T_50 = not(mitb1_b) @[dec_tlu_ctl.scala 2722:18] + mitb1 <= _T_50 @[dec_tlu_ctl.scala 2722:15] + node _T_51 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d4")) @[dec_tlu_ctl.scala 2733:72] + node wr_mitctl0_r = and(io.dec_csr_wen_r_mod, _T_51) @[dec_tlu_ctl.scala 2733:49] + node _T_52 = bits(wr_mitctl0_r, 0, 0) @[dec_tlu_ctl.scala 2734:45] + node _T_53 = bits(io.dec_csr_wrdata_r, 2, 0) @[dec_tlu_ctl.scala 2734:72] + node _T_54 = bits(mitctl0, 2, 0) @[dec_tlu_ctl.scala 2734:86] + node mitctl0_ns = mux(_T_52, _T_53, _T_54) @[dec_tlu_ctl.scala 2734:31] + node _T_55 = bits(mitctl0_ns, 0, 0) @[dec_tlu_ctl.scala 2736:41] + node mitctl0_0_b_ns = not(_T_55) @[dec_tlu_ctl.scala 2736:30] + reg mitctl0_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2737:60] + mitctl0_0_b <= mitctl0_0_b_ns @[dec_tlu_ctl.scala 2737:60] + node _T_56 = bits(mitctl0_ns, 2, 1) @[dec_tlu_ctl.scala 2738:78] + reg _T_57 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2738:67] + _T_57 <= _T_56 @[dec_tlu_ctl.scala 2738:67] + node _T_58 = not(mitctl0_0_b) @[dec_tlu_ctl.scala 2738:90] node _T_59 = cat(_T_57, _T_58) @[Cat.scala 29:58] - mitctl0 <= _T_59 @[dec_tlu_ctl.scala 2742:31] - node _T_60 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d7")) @[dec_tlu_ctl.scala 2752:71] - node wr_mitctl1_r = and(io.dec_csr_wen_r_mod, _T_60) @[dec_tlu_ctl.scala 2752:49] - node _T_61 = bits(wr_mitctl1_r, 0, 0) @[dec_tlu_ctl.scala 2753:45] - node _T_62 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2753:71] - node _T_63 = bits(mitctl1, 3, 0) @[dec_tlu_ctl.scala 2753:85] - node mitctl1_ns = mux(_T_61, _T_62, _T_63) @[dec_tlu_ctl.scala 2753:31] - node _T_64 = bits(mitctl1_ns, 0, 0) @[dec_tlu_ctl.scala 2754:40] - node mitctl1_0_b_ns = not(_T_64) @[dec_tlu_ctl.scala 2754:29] - reg mitctl1_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2755:55] - mitctl1_0_b <= mitctl1_0_b_ns @[dec_tlu_ctl.scala 2755:55] - node _T_65 = bits(mitctl1_ns, 3, 1) @[dec_tlu_ctl.scala 2756:63] - reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2756:52] - _T_66 <= _T_65 @[dec_tlu_ctl.scala 2756:52] - node _T_67 = not(mitctl1_0_b) @[dec_tlu_ctl.scala 2756:75] + mitctl0 <= _T_59 @[dec_tlu_ctl.scala 2738:31] + node _T_60 = eq(io.dec_csr_wraddr_r, UInt<12>("h07d7")) @[dec_tlu_ctl.scala 2748:71] + node wr_mitctl1_r = and(io.dec_csr_wen_r_mod, _T_60) @[dec_tlu_ctl.scala 2748:49] + node _T_61 = bits(wr_mitctl1_r, 0, 0) @[dec_tlu_ctl.scala 2749:45] + node _T_62 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2749:71] + node _T_63 = bits(mitctl1, 3, 0) @[dec_tlu_ctl.scala 2749:85] + node mitctl1_ns = mux(_T_61, _T_62, _T_63) @[dec_tlu_ctl.scala 2749:31] + node _T_64 = bits(mitctl1_ns, 0, 0) @[dec_tlu_ctl.scala 2750:40] + node mitctl1_0_b_ns = not(_T_64) @[dec_tlu_ctl.scala 2750:29] + reg mitctl1_0_b : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2751:55] + mitctl1_0_b <= mitctl1_0_b_ns @[dec_tlu_ctl.scala 2751:55] + node _T_65 = bits(mitctl1_ns, 3, 1) @[dec_tlu_ctl.scala 2752:63] + reg _T_66 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2752:52] + _T_66 <= _T_65 @[dec_tlu_ctl.scala 2752:52] + node _T_67 = not(mitctl1_0_b) @[dec_tlu_ctl.scala 2752:75] node _T_68 = cat(_T_66, _T_67) @[Cat.scala 29:58] - mitctl1 <= _T_68 @[dec_tlu_ctl.scala 2756:16] - node _T_69 = or(io.csr_mitcnt1, io.csr_mitcnt0) @[dec_tlu_ctl.scala 2758:51] - node _T_70 = or(_T_69, io.csr_mitb1) @[dec_tlu_ctl.scala 2758:68] - node _T_71 = or(_T_70, io.csr_mitb0) @[dec_tlu_ctl.scala 2758:83] - node _T_72 = or(_T_71, io.csr_mitctl0) @[dec_tlu_ctl.scala 2758:98] - node _T_73 = or(_T_72, io.csr_mitctl1) @[dec_tlu_ctl.scala 2758:115] - io.dec_timer_read_d <= _T_73 @[dec_tlu_ctl.scala 2758:33] - node _T_74 = bits(io.csr_mitcnt0, 0, 0) @[dec_tlu_ctl.scala 2760:25] - node _T_75 = bits(mitcnt0, 31, 0) @[dec_tlu_ctl.scala 2760:44] - node _T_76 = bits(io.csr_mitcnt1, 0, 0) @[dec_tlu_ctl.scala 2761:32] - node _T_77 = bits(io.csr_mitb0, 0, 0) @[dec_tlu_ctl.scala 2762:30] - node _T_78 = bits(io.csr_mitb1, 0, 0) @[dec_tlu_ctl.scala 2763:30] - node _T_79 = bits(io.csr_mitctl0, 0, 0) @[dec_tlu_ctl.scala 2764:32] + mitctl1 <= _T_68 @[dec_tlu_ctl.scala 2752:16] + node _T_69 = or(io.csr_mitcnt1, io.csr_mitcnt0) @[dec_tlu_ctl.scala 2754:51] + node _T_70 = or(_T_69, io.csr_mitb1) @[dec_tlu_ctl.scala 2754:68] + node _T_71 = or(_T_70, io.csr_mitb0) @[dec_tlu_ctl.scala 2754:83] + node _T_72 = or(_T_71, io.csr_mitctl0) @[dec_tlu_ctl.scala 2754:98] + node _T_73 = or(_T_72, io.csr_mitctl1) @[dec_tlu_ctl.scala 2754:115] + io.dec_timer_read_d <= _T_73 @[dec_tlu_ctl.scala 2754:33] + node _T_74 = bits(io.csr_mitcnt0, 0, 0) @[dec_tlu_ctl.scala 2756:25] + node _T_75 = bits(mitcnt0, 31, 0) @[dec_tlu_ctl.scala 2756:44] + node _T_76 = bits(io.csr_mitcnt1, 0, 0) @[dec_tlu_ctl.scala 2757:32] + node _T_77 = bits(io.csr_mitb0, 0, 0) @[dec_tlu_ctl.scala 2758:30] + node _T_78 = bits(io.csr_mitb1, 0, 0) @[dec_tlu_ctl.scala 2759:30] + node _T_79 = bits(io.csr_mitctl0, 0, 0) @[dec_tlu_ctl.scala 2760:32] node _T_80 = mux(UInt<1>("h00"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12] node _T_81 = cat(_T_80, mitctl0) @[Cat.scala 29:58] - node _T_82 = bits(io.csr_mitctl1, 0, 0) @[dec_tlu_ctl.scala 2765:32] + node _T_82 = bits(io.csr_mitctl1, 0, 0) @[dec_tlu_ctl.scala 2761:32] node _T_83 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] node _T_84 = cat(_T_83, mitctl1) @[Cat.scala 29:58] node _T_85 = mux(_T_74, _T_75, UInt<1>("h00")) @[Mux.scala 27:72] @@ -71842,7 +71842,7 @@ circuit quasar_wrapper : node _T_95 = or(_T_94, _T_90) @[Mux.scala 27:72] wire _T_96 : UInt<32> @[Mux.scala 27:72] _T_96 <= _T_95 @[Mux.scala 27:72] - io.dec_timer_rddata_d <= _T_96 @[dec_tlu_ctl.scala 2759:33] + io.dec_timer_rddata_d <= _T_96 @[dec_tlu_ctl.scala 2755:33] extmodule gated_latch_716 : output Q : Clock @@ -72825,8 +72825,8 @@ circuit quasar_wrapper : perfcnt_halted <= UInt<1>("h00") wire mhpmc3_incr : UInt<64> mhpmc3_incr <= UInt<1>("h00") - wire mhpme_vec : UInt<10>[4] @[dec_tlu_ctl.scala 1399:41] - wire mtdata2_t : UInt<32>[4] @[dec_tlu_ctl.scala 1400:65] + wire mhpme_vec : UInt<10>[4] @[dec_tlu_ctl.scala 1395:41] + wire mtdata2_t : UInt<32>[4] @[dec_tlu_ctl.scala 1396:65] wire wr_meicpct_r : UInt<1> wr_meicpct_r <= UInt<1>("h00") wire force_halt_ctr_f : UInt<32> @@ -72901,48 +72901,48 @@ circuit quasar_wrapper : mpmc <= UInt<1>("h00") wire dicad1 : UInt<32> dicad1 <= UInt<1>("h00") - node _T = eq(io.i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1455:45] - node _T_1 = and(io.dec_csr_wen_r, _T) @[dec_tlu_ctl.scala 1455:43] - node _T_2 = eq(io.rfpc_i0_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1455:68] - node _T_3 = and(_T_1, _T_2) @[dec_tlu_ctl.scala 1455:66] - io.dec_csr_wen_r_mod <= _T_3 @[dec_tlu_ctl.scala 1455:23] - node _T_4 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1456:64] - node _T_5 = eq(_T_4, UInt<12>("h0300")) @[dec_tlu_ctl.scala 1456:71] - node wr_mstatus_r = and(io.dec_csr_wen_r_mod, _T_5) @[dec_tlu_ctl.scala 1456:42] - node _T_6 = eq(mpmc_b_ns, UInt<1>("h00")) @[dec_tlu_ctl.scala 1459:28] - node set_mie_pmu_fw_halt = and(_T_6, io.fw_halt_req) @[dec_tlu_ctl.scala 1459:39] - node _T_7 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1462:5] - node _T_8 = and(_T_7, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1462:19] - node _T_9 = bits(_T_8, 0, 0) @[dec_tlu_ctl.scala 1462:44] - node _T_10 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1462:68] - node _T_11 = bits(_T_10, 0, 0) @[dec_tlu_ctl.scala 1462:68] + node _T = eq(io.i0_trigger_hit_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1451:45] + node _T_1 = and(io.dec_csr_wen_r, _T) @[dec_tlu_ctl.scala 1451:43] + node _T_2 = eq(io.rfpc_i0_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1451:68] + node _T_3 = and(_T_1, _T_2) @[dec_tlu_ctl.scala 1451:66] + io.dec_csr_wen_r_mod <= _T_3 @[dec_tlu_ctl.scala 1451:23] + node _T_4 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1452:64] + node _T_5 = eq(_T_4, UInt<12>("h0300")) @[dec_tlu_ctl.scala 1452:71] + node wr_mstatus_r = and(io.dec_csr_wen_r_mod, _T_5) @[dec_tlu_ctl.scala 1452:42] + node _T_6 = eq(mpmc_b_ns, UInt<1>("h00")) @[dec_tlu_ctl.scala 1455:28] + node set_mie_pmu_fw_halt = and(_T_6, io.fw_halt_req) @[dec_tlu_ctl.scala 1455:39] + node _T_7 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1458:5] + node _T_8 = and(_T_7, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1458:19] + node _T_9 = bits(_T_8, 0, 0) @[dec_tlu_ctl.scala 1458:44] + node _T_10 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1458:68] + node _T_11 = bits(_T_10, 0, 0) @[dec_tlu_ctl.scala 1458:68] node _T_12 = cat(_T_11, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_13 = and(wr_mstatus_r, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1463:18] - node _T_14 = bits(_T_13, 0, 0) @[dec_tlu_ctl.scala 1463:43] - node _T_15 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1463:76] + node _T_13 = and(wr_mstatus_r, io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1459:18] + node _T_14 = bits(_T_13, 0, 0) @[dec_tlu_ctl.scala 1459:43] + node _T_15 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1459:76] node _T_16 = cat(_T_15, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_17 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1464:17] - node _T_18 = and(io.mret_r, _T_17) @[dec_tlu_ctl.scala 1464:15] - node _T_19 = bits(_T_18, 0, 0) @[dec_tlu_ctl.scala 1464:41] - node _T_20 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1464:70] + node _T_17 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1460:17] + node _T_18 = and(io.mret_r, _T_17) @[dec_tlu_ctl.scala 1460:15] + node _T_19 = bits(_T_18, 0, 0) @[dec_tlu_ctl.scala 1460:41] + node _T_20 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1460:70] node _T_21 = cat(UInt<1>("h01"), _T_20) @[Cat.scala 29:58] - node _T_22 = bits(set_mie_pmu_fw_halt, 0, 0) @[dec_tlu_ctl.scala 1465:26] - node _T_23 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1465:50] + node _T_22 = bits(set_mie_pmu_fw_halt, 0, 0) @[dec_tlu_ctl.scala 1461:26] + node _T_23 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 1461:50] node _T_24 = cat(_T_23, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_25 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1466:20] - node _T_26 = and(wr_mstatus_r, _T_25) @[dec_tlu_ctl.scala 1466:18] - node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 1466:44] - node _T_28 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1466:77] - node _T_29 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1466:101] + node _T_25 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1462:20] + node _T_26 = and(wr_mstatus_r, _T_25) @[dec_tlu_ctl.scala 1462:18] + node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 1462:44] + node _T_28 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1462:77] + node _T_29 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1462:101] node _T_30 = cat(_T_28, _T_29) @[Cat.scala 29:58] - node _T_31 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1467:5] - node _T_32 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1467:21] - node _T_33 = and(_T_31, _T_32) @[dec_tlu_ctl.scala 1467:19] - node _T_34 = eq(io.mret_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1467:46] - node _T_35 = and(_T_33, _T_34) @[dec_tlu_ctl.scala 1467:44] - node _T_36 = eq(set_mie_pmu_fw_halt, UInt<1>("h00")) @[dec_tlu_ctl.scala 1467:59] - node _T_37 = and(_T_35, _T_36) @[dec_tlu_ctl.scala 1467:57] - node _T_38 = bits(_T_37, 0, 0) @[dec_tlu_ctl.scala 1467:81] + node _T_31 = eq(wr_mstatus_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1463:5] + node _T_32 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1463:21] + node _T_33 = and(_T_31, _T_32) @[dec_tlu_ctl.scala 1463:19] + node _T_34 = eq(io.mret_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1463:46] + node _T_35 = and(_T_33, _T_34) @[dec_tlu_ctl.scala 1463:44] + node _T_36 = eq(set_mie_pmu_fw_halt, UInt<1>("h00")) @[dec_tlu_ctl.scala 1463:59] + node _T_37 = and(_T_35, _T_36) @[dec_tlu_ctl.scala 1463:57] + node _T_38 = bits(_T_37, 0, 0) @[dec_tlu_ctl.scala 1463:81] node _T_39 = mux(_T_9, _T_12, UInt<1>("h00")) @[Mux.scala 27:72] node _T_40 = mux(_T_14, _T_16, UInt<1>("h00")) @[Mux.scala 27:72] node _T_41 = mux(_T_19, _T_21, UInt<1>("h00")) @[Mux.scala 27:72] @@ -72956,23 +72956,23 @@ circuit quasar_wrapper : node _T_49 = or(_T_48, _T_44) @[Mux.scala 27:72] wire mstatus_ns : UInt<2> @[Mux.scala 27:72] mstatus_ns <= _T_49 @[Mux.scala 27:72] - node _T_50 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1470:33] - node _T_51 = bits(_T_50, 0, 0) @[dec_tlu_ctl.scala 1470:33] - node _T_52 = not(io.dcsr_single_step_running_f) @[dec_tlu_ctl.scala 1470:50] - node _T_53 = bits(io.dcsr, 11, 11) @[dec_tlu_ctl.scala 1470:90] - node _T_54 = or(_T_52, _T_53) @[dec_tlu_ctl.scala 1470:81] - node _T_55 = and(_T_51, _T_54) @[dec_tlu_ctl.scala 1470:47] - io.mstatus_mie_ns <= _T_55 @[dec_tlu_ctl.scala 1470:20] - reg _T_56 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1472:11] - _T_56 <= mstatus_ns @[dec_tlu_ctl.scala 1472:11] - io.mstatus <= _T_56 @[dec_tlu_ctl.scala 1471:13] - node _T_57 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1481:62] - node _T_58 = eq(_T_57, UInt<12>("h0305")) @[dec_tlu_ctl.scala 1481:69] - node wr_mtvec_r = and(io.dec_csr_wen_r_mod, _T_58) @[dec_tlu_ctl.scala 1481:40] - node _T_59 = bits(io.dec_csr_wrdata_r, 31, 2) @[dec_tlu_ctl.scala 1482:40] - node _T_60 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1482:68] + node _T_50 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 1466:33] + node _T_51 = bits(_T_50, 0, 0) @[dec_tlu_ctl.scala 1466:33] + node _T_52 = not(io.dcsr_single_step_running_f) @[dec_tlu_ctl.scala 1466:50] + node _T_53 = bits(io.dcsr, 11, 11) @[dec_tlu_ctl.scala 1466:90] + node _T_54 = or(_T_52, _T_53) @[dec_tlu_ctl.scala 1466:81] + node _T_55 = and(_T_51, _T_54) @[dec_tlu_ctl.scala 1466:47] + io.mstatus_mie_ns <= _T_55 @[dec_tlu_ctl.scala 1466:20] + reg _T_56 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1468:11] + _T_56 <= mstatus_ns @[dec_tlu_ctl.scala 1468:11] + io.mstatus <= _T_56 @[dec_tlu_ctl.scala 1467:13] + node _T_57 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1477:62] + node _T_58 = eq(_T_57, UInt<12>("h0305")) @[dec_tlu_ctl.scala 1477:69] + node wr_mtvec_r = and(io.dec_csr_wen_r_mod, _T_58) @[dec_tlu_ctl.scala 1477:40] + node _T_59 = bits(io.dec_csr_wrdata_r, 31, 2) @[dec_tlu_ctl.scala 1478:40] + node _T_60 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1478:68] node mtvec_ns = cat(_T_59, _T_60) @[Cat.scala 29:58] - node _T_61 = bits(wr_mtvec_r, 0, 0) @[dec_tlu_ctl.scala 1483:42] + node _T_61 = bits(wr_mtvec_r, 0, 0) @[dec_tlu_ctl.scala 1479:42] inst rvclkhdr of rvclkhdr_720 @[lib.scala 352:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -72981,57 +72981,57 @@ circuit quasar_wrapper : rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_62 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_62 <= mtvec_ns @[lib.scala 358:16] - io.mtvec <= _T_62 @[dec_tlu_ctl.scala 1483:11] - node _T_63 = or(mdccme_ce_req, miccme_ce_req) @[dec_tlu_ctl.scala 1495:30] - node ce_int = or(_T_63, mice_ce_req) @[dec_tlu_ctl.scala 1495:46] + io.mtvec <= _T_62 @[dec_tlu_ctl.scala 1479:11] + node _T_63 = or(mdccme_ce_req, miccme_ce_req) @[dec_tlu_ctl.scala 1491:30] + node ce_int = or(_T_63, mice_ce_req) @[dec_tlu_ctl.scala 1491:46] node _T_64 = cat(io.mexintpend, io.timer_int_sync) @[Cat.scala 29:58] node _T_65 = cat(_T_64, io.soft_int_sync) @[Cat.scala 29:58] node _T_66 = cat(ce_int, io.dec_timer_t0_pulse) @[Cat.scala 29:58] node _T_67 = cat(_T_66, io.dec_timer_t1_pulse) @[Cat.scala 29:58] node mip_ns = cat(_T_67, _T_65) @[Cat.scala 29:58] - reg _T_68 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1499:11] - _T_68 <= mip_ns @[dec_tlu_ctl.scala 1499:11] - io.mip <= _T_68 @[dec_tlu_ctl.scala 1498:9] - node _T_69 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1511:60] - node _T_70 = eq(_T_69, UInt<12>("h0304")) @[dec_tlu_ctl.scala 1511:67] - node wr_mie_r = and(io.dec_csr_wen_r_mod, _T_70) @[dec_tlu_ctl.scala 1511:38] - node _T_71 = bits(wr_mie_r, 0, 0) @[dec_tlu_ctl.scala 1512:28] - node _T_72 = bits(io.dec_csr_wrdata_r, 30, 28) @[dec_tlu_ctl.scala 1512:59] - node _T_73 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1512:88] - node _T_74 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1512:113] - node _T_75 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1512:137] + reg _T_68 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1495:11] + _T_68 <= mip_ns @[dec_tlu_ctl.scala 1495:11] + io.mip <= _T_68 @[dec_tlu_ctl.scala 1494:9] + node _T_69 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1507:60] + node _T_70 = eq(_T_69, UInt<12>("h0304")) @[dec_tlu_ctl.scala 1507:67] + node wr_mie_r = and(io.dec_csr_wen_r_mod, _T_70) @[dec_tlu_ctl.scala 1507:38] + node _T_71 = bits(wr_mie_r, 0, 0) @[dec_tlu_ctl.scala 1508:28] + node _T_72 = bits(io.dec_csr_wrdata_r, 30, 28) @[dec_tlu_ctl.scala 1508:59] + node _T_73 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1508:88] + node _T_74 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1508:113] + node _T_75 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1508:137] node _T_76 = cat(_T_74, _T_75) @[Cat.scala 29:58] node _T_77 = cat(_T_72, _T_73) @[Cat.scala 29:58] node _T_78 = cat(_T_77, _T_76) @[Cat.scala 29:58] - node _T_79 = mux(_T_71, _T_78, mie) @[dec_tlu_ctl.scala 1512:18] - io.mie_ns <= _T_79 @[dec_tlu_ctl.scala 1512:12] - reg _T_80 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1514:11] - _T_80 <= io.mie_ns @[dec_tlu_ctl.scala 1514:11] - mie <= _T_80 @[dec_tlu_ctl.scala 1513:6] - node _T_81 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1521:63] - node kill_ebreak_count_r = and(io.ebreak_to_debug_mode_r, _T_81) @[dec_tlu_ctl.scala 1521:54] - node _T_82 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1523:64] - node _T_83 = eq(_T_82, UInt<12>("h0b00")) @[dec_tlu_ctl.scala 1523:71] - node wr_mcyclel_r = and(io.dec_csr_wen_r_mod, _T_83) @[dec_tlu_ctl.scala 1523:42] - node _T_84 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1525:80] - node _T_85 = and(io.dec_tlu_dbg_halted, _T_84) @[dec_tlu_ctl.scala 1525:71] - node _T_86 = or(kill_ebreak_count_r, _T_85) @[dec_tlu_ctl.scala 1525:46] - node _T_87 = or(_T_86, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 1525:94] - node _T_88 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 1525:136] - node _T_89 = or(_T_87, _T_88) @[dec_tlu_ctl.scala 1525:121] - node mcyclel_cout_in = not(_T_89) @[dec_tlu_ctl.scala 1525:24] + node _T_79 = mux(_T_71, _T_78, mie) @[dec_tlu_ctl.scala 1508:18] + io.mie_ns <= _T_79 @[dec_tlu_ctl.scala 1508:12] + reg _T_80 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1510:11] + _T_80 <= io.mie_ns @[dec_tlu_ctl.scala 1510:11] + mie <= _T_80 @[dec_tlu_ctl.scala 1509:6] + node _T_81 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1517:63] + node kill_ebreak_count_r = and(io.ebreak_to_debug_mode_r, _T_81) @[dec_tlu_ctl.scala 1517:54] + node _T_82 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1519:64] + node _T_83 = eq(_T_82, UInt<12>("h0b00")) @[dec_tlu_ctl.scala 1519:71] + node wr_mcyclel_r = and(io.dec_csr_wen_r_mod, _T_83) @[dec_tlu_ctl.scala 1519:42] + node _T_84 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 1521:80] + node _T_85 = and(io.dec_tlu_dbg_halted, _T_84) @[dec_tlu_ctl.scala 1521:71] + node _T_86 = or(kill_ebreak_count_r, _T_85) @[dec_tlu_ctl.scala 1521:46] + node _T_87 = or(_T_86, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 1521:94] + node _T_88 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 1521:136] + node _T_89 = or(_T_87, _T_88) @[dec_tlu_ctl.scala 1521:121] + node mcyclel_cout_in = not(_T_89) @[dec_tlu_ctl.scala 1521:24] wire mcyclel_inc : UInt<33> mcyclel_inc <= UInt<1>("h00") node _T_90 = cat(UInt<31>("h00"), mcyclel_cout_in) @[Cat.scala 29:58] - node _T_91 = add(mcyclel, _T_90) @[dec_tlu_ctl.scala 1529:25] - mcyclel_inc <= _T_91 @[dec_tlu_ctl.scala 1529:14] - node _T_92 = bits(wr_mcyclel_r, 0, 0) @[dec_tlu_ctl.scala 1530:36] - node _T_93 = bits(mcyclel_inc, 31, 0) @[dec_tlu_ctl.scala 1530:76] - node mcyclel_ns = mux(_T_92, io.dec_csr_wrdata_r, _T_93) @[dec_tlu_ctl.scala 1530:22] - node _T_94 = bits(mcyclel_inc, 32, 32) @[dec_tlu_ctl.scala 1531:32] - node mcyclel_cout = bits(_T_94, 0, 0) @[dec_tlu_ctl.scala 1531:37] - node _T_95 = or(wr_mcyclel_r, mcyclel_cout_in) @[dec_tlu_ctl.scala 1532:46] - node _T_96 = bits(_T_95, 0, 0) @[dec_tlu_ctl.scala 1532:72] + node _T_91 = add(mcyclel, _T_90) @[dec_tlu_ctl.scala 1525:25] + mcyclel_inc <= _T_91 @[dec_tlu_ctl.scala 1525:14] + node _T_92 = bits(wr_mcyclel_r, 0, 0) @[dec_tlu_ctl.scala 1526:36] + node _T_93 = bits(mcyclel_inc, 31, 0) @[dec_tlu_ctl.scala 1526:76] + node mcyclel_ns = mux(_T_92, io.dec_csr_wrdata_r, _T_93) @[dec_tlu_ctl.scala 1526:22] + node _T_94 = bits(mcyclel_inc, 32, 32) @[dec_tlu_ctl.scala 1527:32] + node mcyclel_cout = bits(_T_94, 0, 0) @[dec_tlu_ctl.scala 1527:37] + node _T_95 = or(wr_mcyclel_r, mcyclel_cout_in) @[dec_tlu_ctl.scala 1528:46] + node _T_96 = bits(_T_95, 0, 0) @[dec_tlu_ctl.scala 1528:72] inst rvclkhdr_1 of rvclkhdr_721 @[lib.scala 352:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -73040,22 +73040,22 @@ circuit quasar_wrapper : rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_97 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_97 <= mcyclel_ns @[lib.scala 358:16] - mcyclel <= _T_97 @[dec_tlu_ctl.scala 1532:10] - node _T_98 = eq(wr_mcycleh_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1533:71] - node _T_99 = and(mcyclel_cout, _T_98) @[dec_tlu_ctl.scala 1533:69] - reg mcyclel_cout_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1533:54] - mcyclel_cout_f <= _T_99 @[dec_tlu_ctl.scala 1533:54] - node _T_100 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1539:61] - node _T_101 = eq(_T_100, UInt<12>("h0b80")) @[dec_tlu_ctl.scala 1539:68] - node _T_102 = and(io.dec_csr_wen_r_mod, _T_101) @[dec_tlu_ctl.scala 1539:39] - wr_mcycleh_r <= _T_102 @[dec_tlu_ctl.scala 1539:15] + mcyclel <= _T_97 @[dec_tlu_ctl.scala 1528:10] + node _T_98 = eq(wr_mcycleh_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1529:71] + node _T_99 = and(mcyclel_cout, _T_98) @[dec_tlu_ctl.scala 1529:69] + reg mcyclel_cout_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1529:54] + mcyclel_cout_f <= _T_99 @[dec_tlu_ctl.scala 1529:54] + node _T_100 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1535:61] + node _T_101 = eq(_T_100, UInt<12>("h0b80")) @[dec_tlu_ctl.scala 1535:68] + node _T_102 = and(io.dec_csr_wen_r_mod, _T_101) @[dec_tlu_ctl.scala 1535:39] + wr_mcycleh_r <= _T_102 @[dec_tlu_ctl.scala 1535:15] node _T_103 = cat(UInt<31>("h00"), mcyclel_cout_f) @[Cat.scala 29:58] - node _T_104 = add(mcycleh, _T_103) @[dec_tlu_ctl.scala 1541:28] - node mcycleh_inc = tail(_T_104, 1) @[dec_tlu_ctl.scala 1541:28] - node _T_105 = bits(wr_mcycleh_r, 0, 0) @[dec_tlu_ctl.scala 1542:36] - node mcycleh_ns = mux(_T_105, io.dec_csr_wrdata_r, mcycleh_inc) @[dec_tlu_ctl.scala 1542:22] - node _T_106 = or(wr_mcycleh_r, mcyclel_cout_f) @[dec_tlu_ctl.scala 1544:46] - node _T_107 = bits(_T_106, 0, 0) @[dec_tlu_ctl.scala 1544:64] + node _T_104 = add(mcycleh, _T_103) @[dec_tlu_ctl.scala 1537:28] + node mcycleh_inc = tail(_T_104, 1) @[dec_tlu_ctl.scala 1537:28] + node _T_105 = bits(wr_mcycleh_r, 0, 0) @[dec_tlu_ctl.scala 1538:36] + node mcycleh_ns = mux(_T_105, io.dec_csr_wrdata_r, mcycleh_inc) @[dec_tlu_ctl.scala 1538:22] + node _T_106 = or(wr_mcycleh_r, mcyclel_cout_f) @[dec_tlu_ctl.scala 1540:46] + node _T_107 = bits(_T_106, 0, 0) @[dec_tlu_ctl.scala 1540:64] inst rvclkhdr_2 of rvclkhdr_722 @[lib.scala 352:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -73064,28 +73064,28 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_108 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_108 <= mcycleh_ns @[lib.scala 358:16] - mcycleh <= _T_108 @[dec_tlu_ctl.scala 1544:10] - node _T_109 = or(io.ebreak_r, io.ecall_r) @[dec_tlu_ctl.scala 1558:72] - node _T_110 = or(_T_109, io.ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 1558:85] - node _T_111 = or(_T_110, io.illegal_r) @[dec_tlu_ctl.scala 1558:113] - node _T_112 = bits(mcountinhibit, 2, 2) @[dec_tlu_ctl.scala 1558:143] - node _T_113 = or(_T_111, _T_112) @[dec_tlu_ctl.scala 1558:128] - node _T_114 = bits(_T_113, 0, 0) @[dec_tlu_ctl.scala 1558:148] - node _T_115 = not(_T_114) @[dec_tlu_ctl.scala 1558:58] - node i0_valid_no_ebreak_ecall_r = and(io.tlu_i0_commit_cmt, _T_115) @[dec_tlu_ctl.scala 1558:56] - node _T_116 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1560:66] - node _T_117 = eq(_T_116, UInt<12>("h0b02")) @[dec_tlu_ctl.scala 1560:73] - node wr_minstretl_r = and(io.dec_csr_wen_r_mod, _T_117) @[dec_tlu_ctl.scala 1560:44] + mcycleh <= _T_108 @[dec_tlu_ctl.scala 1540:10] + node _T_109 = or(io.ebreak_r, io.ecall_r) @[dec_tlu_ctl.scala 1554:72] + node _T_110 = or(_T_109, io.ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 1554:85] + node _T_111 = or(_T_110, io.illegal_r) @[dec_tlu_ctl.scala 1554:113] + node _T_112 = bits(mcountinhibit, 2, 2) @[dec_tlu_ctl.scala 1554:143] + node _T_113 = or(_T_111, _T_112) @[dec_tlu_ctl.scala 1554:128] + node _T_114 = bits(_T_113, 0, 0) @[dec_tlu_ctl.scala 1554:148] + node _T_115 = not(_T_114) @[dec_tlu_ctl.scala 1554:58] + node i0_valid_no_ebreak_ecall_r = and(io.tlu_i0_commit_cmt, _T_115) @[dec_tlu_ctl.scala 1554:56] + node _T_116 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1556:66] + node _T_117 = eq(_T_116, UInt<12>("h0b02")) @[dec_tlu_ctl.scala 1556:73] + node wr_minstretl_r = and(io.dec_csr_wen_r_mod, _T_117) @[dec_tlu_ctl.scala 1556:44] node _T_118 = cat(UInt<31>("h00"), i0_valid_no_ebreak_ecall_r) @[Cat.scala 29:58] - node _T_119 = add(minstretl, _T_118) @[dec_tlu_ctl.scala 1562:29] - minstretl_inc <= _T_119 @[dec_tlu_ctl.scala 1562:16] - node minstretl_cout = bits(minstretl_inc, 32, 32) @[dec_tlu_ctl.scala 1563:36] - node _T_120 = or(i0_valid_no_ebreak_ecall_r, wr_minstretl_r) @[dec_tlu_ctl.scala 1564:52] - node minstret_enable = bits(_T_120, 0, 0) @[dec_tlu_ctl.scala 1564:70] - node _T_121 = bits(wr_minstretl_r, 0, 0) @[dec_tlu_ctl.scala 1566:40] - node _T_122 = bits(minstretl_inc, 31, 0) @[dec_tlu_ctl.scala 1566:83] - node minstretl_ns = mux(_T_121, io.dec_csr_wrdata_r, _T_122) @[dec_tlu_ctl.scala 1566:24] - node _T_123 = bits(minstret_enable, 0, 0) @[dec_tlu_ctl.scala 1567:51] + node _T_119 = add(minstretl, _T_118) @[dec_tlu_ctl.scala 1558:29] + minstretl_inc <= _T_119 @[dec_tlu_ctl.scala 1558:16] + node minstretl_cout = bits(minstretl_inc, 32, 32) @[dec_tlu_ctl.scala 1559:36] + node _T_120 = or(i0_valid_no_ebreak_ecall_r, wr_minstretl_r) @[dec_tlu_ctl.scala 1560:52] + node minstret_enable = bits(_T_120, 0, 0) @[dec_tlu_ctl.scala 1560:70] + node _T_121 = bits(wr_minstretl_r, 0, 0) @[dec_tlu_ctl.scala 1562:40] + node _T_122 = bits(minstretl_inc, 31, 0) @[dec_tlu_ctl.scala 1562:83] + node minstretl_ns = mux(_T_121, io.dec_csr_wrdata_r, _T_122) @[dec_tlu_ctl.scala 1562:24] + node _T_123 = bits(minstret_enable, 0, 0) @[dec_tlu_ctl.scala 1563:51] inst rvclkhdr_3 of rvclkhdr_723 @[lib.scala 352:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -73094,26 +73094,26 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_124 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_124 <= minstretl_ns @[lib.scala 358:16] - minstretl <= _T_124 @[dec_tlu_ctl.scala 1567:12] - reg minstret_enable_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1568:56] - minstret_enable_f <= minstret_enable @[dec_tlu_ctl.scala 1568:56] - node _T_125 = not(wr_minstreth_r) @[dec_tlu_ctl.scala 1569:75] - node _T_126 = and(minstretl_cout, _T_125) @[dec_tlu_ctl.scala 1569:73] - reg minstretl_cout_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1569:56] - minstretl_cout_f <= _T_126 @[dec_tlu_ctl.scala 1569:56] - node _T_127 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1577:64] - node _T_128 = eq(_T_127, UInt<12>("h0b82")) @[dec_tlu_ctl.scala 1577:71] - node _T_129 = and(io.dec_csr_wen_r_mod, _T_128) @[dec_tlu_ctl.scala 1577:42] - node _T_130 = bits(_T_129, 0, 0) @[dec_tlu_ctl.scala 1577:87] - wr_minstreth_r <= _T_130 @[dec_tlu_ctl.scala 1577:17] + minstretl <= _T_124 @[dec_tlu_ctl.scala 1563:12] + reg minstret_enable_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1564:56] + minstret_enable_f <= minstret_enable @[dec_tlu_ctl.scala 1564:56] + node _T_125 = not(wr_minstreth_r) @[dec_tlu_ctl.scala 1565:75] + node _T_126 = and(minstretl_cout, _T_125) @[dec_tlu_ctl.scala 1565:73] + reg minstretl_cout_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1565:56] + minstretl_cout_f <= _T_126 @[dec_tlu_ctl.scala 1565:56] + node _T_127 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1573:64] + node _T_128 = eq(_T_127, UInt<12>("h0b82")) @[dec_tlu_ctl.scala 1573:71] + node _T_129 = and(io.dec_csr_wen_r_mod, _T_128) @[dec_tlu_ctl.scala 1573:42] + node _T_130 = bits(_T_129, 0, 0) @[dec_tlu_ctl.scala 1573:87] + wr_minstreth_r <= _T_130 @[dec_tlu_ctl.scala 1573:17] node _T_131 = cat(UInt<31>("h00"), minstretl_cout_f) @[Cat.scala 29:58] - node _T_132 = add(minstreth, _T_131) @[dec_tlu_ctl.scala 1580:29] - node _T_133 = tail(_T_132, 1) @[dec_tlu_ctl.scala 1580:29] - minstreth_inc <= _T_133 @[dec_tlu_ctl.scala 1580:16] - node _T_134 = bits(wr_minstreth_r, 0, 0) @[dec_tlu_ctl.scala 1581:41] - node minstreth_ns = mux(_T_134, io.dec_csr_wrdata_r, minstreth_inc) @[dec_tlu_ctl.scala 1581:25] - node _T_135 = or(minstret_enable_f, wr_minstreth_r) @[dec_tlu_ctl.scala 1583:55] - node _T_136 = bits(_T_135, 0, 0) @[dec_tlu_ctl.scala 1583:73] + node _T_132 = add(minstreth, _T_131) @[dec_tlu_ctl.scala 1576:29] + node _T_133 = tail(_T_132, 1) @[dec_tlu_ctl.scala 1576:29] + minstreth_inc <= _T_133 @[dec_tlu_ctl.scala 1576:16] + node _T_134 = bits(wr_minstreth_r, 0, 0) @[dec_tlu_ctl.scala 1577:41] + node minstreth_ns = mux(_T_134, io.dec_csr_wrdata_r, minstreth_inc) @[dec_tlu_ctl.scala 1577:25] + node _T_135 = or(minstret_enable_f, wr_minstreth_r) @[dec_tlu_ctl.scala 1579:55] + node _T_136 = bits(_T_135, 0, 0) @[dec_tlu_ctl.scala 1579:73] inst rvclkhdr_4 of rvclkhdr_724 @[lib.scala 352:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -73122,11 +73122,11 @@ circuit quasar_wrapper : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_137 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_137 <= minstreth_ns @[lib.scala 358:16] - minstreth <= _T_137 @[dec_tlu_ctl.scala 1583:12] - node _T_138 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1591:65] - node _T_139 = eq(_T_138, UInt<12>("h0340")) @[dec_tlu_ctl.scala 1591:72] - node wr_mscratch_r = and(io.dec_csr_wen_r_mod, _T_139) @[dec_tlu_ctl.scala 1591:43] - node _T_140 = bits(wr_mscratch_r, 0, 0) @[dec_tlu_ctl.scala 1593:55] + minstreth <= _T_137 @[dec_tlu_ctl.scala 1579:12] + node _T_138 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1587:65] + node _T_139 = eq(_T_138, UInt<12>("h0340")) @[dec_tlu_ctl.scala 1587:72] + node wr_mscratch_r = and(io.dec_csr_wen_r_mod, _T_139) @[dec_tlu_ctl.scala 1587:43] + node _T_140 = bits(wr_mscratch_r, 0, 0) @[dec_tlu_ctl.scala 1589:55] inst rvclkhdr_5 of rvclkhdr_725 @[lib.scala 352:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -73135,24 +73135,24 @@ circuit quasar_wrapper : rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_141 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_141 <= io.dec_csr_wrdata_r @[lib.scala 358:16] - mscratch <= _T_141 @[dec_tlu_ctl.scala 1593:11] - node _T_142 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1602:22] - node _T_143 = eq(io.tlu_flush_lower_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1602:47] - node _T_144 = and(_T_142, _T_143) @[dec_tlu_ctl.scala 1602:45] - node sel_exu_npc_r = and(_T_144, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1602:72] - node _T_145 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1603:24] - node _T_146 = and(_T_145, io.tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 1603:47] - node _T_147 = eq(io.dec_tlu_flush_noredir_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1603:75] - node sel_flush_npc_r = and(_T_146, _T_147) @[dec_tlu_ctl.scala 1603:73] - node _T_148 = eq(sel_exu_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1604:23] - node _T_149 = eq(sel_flush_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1604:40] - node sel_hold_npc_r = and(_T_148, _T_149) @[dec_tlu_ctl.scala 1604:38] - node _T_150 = bits(sel_exu_npc_r, 0, 0) @[dec_tlu_ctl.scala 1607:26] - node _T_151 = eq(io.mpc_reset_run_req, UInt<1>("h00")) @[dec_tlu_ctl.scala 1608:13] - node _T_152 = and(_T_151, io.reset_delayed) @[dec_tlu_ctl.scala 1608:35] - node _T_153 = bits(_T_152, 0, 0) @[dec_tlu_ctl.scala 1608:55] - node _T_154 = bits(sel_flush_npc_r, 0, 0) @[dec_tlu_ctl.scala 1609:28] - node _T_155 = bits(sel_hold_npc_r, 0, 0) @[dec_tlu_ctl.scala 1610:27] + mscratch <= _T_141 @[dec_tlu_ctl.scala 1589:11] + node _T_142 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1598:22] + node _T_143 = eq(io.tlu_flush_lower_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1598:47] + node _T_144 = and(_T_142, _T_143) @[dec_tlu_ctl.scala 1598:45] + node sel_exu_npc_r = and(_T_144, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1598:72] + node _T_145 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1599:24] + node _T_146 = and(_T_145, io.tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 1599:47] + node _T_147 = eq(io.dec_tlu_flush_noredir_r_d1, UInt<1>("h00")) @[dec_tlu_ctl.scala 1599:75] + node sel_flush_npc_r = and(_T_146, _T_147) @[dec_tlu_ctl.scala 1599:73] + node _T_148 = eq(sel_exu_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1600:23] + node _T_149 = eq(sel_flush_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1600:40] + node sel_hold_npc_r = and(_T_148, _T_149) @[dec_tlu_ctl.scala 1600:38] + node _T_150 = bits(sel_exu_npc_r, 0, 0) @[dec_tlu_ctl.scala 1603:26] + node _T_151 = eq(io.mpc_reset_run_req, UInt<1>("h00")) @[dec_tlu_ctl.scala 1604:13] + node _T_152 = and(_T_151, io.reset_delayed) @[dec_tlu_ctl.scala 1604:35] + node _T_153 = bits(_T_152, 0, 0) @[dec_tlu_ctl.scala 1604:55] + node _T_154 = bits(sel_flush_npc_r, 0, 0) @[dec_tlu_ctl.scala 1605:28] + node _T_155 = bits(sel_hold_npc_r, 0, 0) @[dec_tlu_ctl.scala 1606:27] node _T_156 = mux(_T_150, io.exu_npc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_157 = mux(_T_153, io.rst_vec, UInt<1>("h00")) @[Mux.scala 27:72] node _T_158 = mux(_T_154, io.tlu_flush_path_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73162,10 +73162,10 @@ circuit quasar_wrapper : node _T_162 = or(_T_161, _T_159) @[Mux.scala 27:72] wire _T_163 : UInt<31> @[Mux.scala 27:72] _T_163 <= _T_162 @[Mux.scala 27:72] - io.npc_r <= _T_163 @[dec_tlu_ctl.scala 1606:11] - node _T_164 = or(sel_exu_npc_r, sel_flush_npc_r) @[dec_tlu_ctl.scala 1612:48] - node _T_165 = or(_T_164, io.reset_delayed) @[dec_tlu_ctl.scala 1612:66] - node _T_166 = bits(_T_165, 0, 0) @[dec_tlu_ctl.scala 1612:86] + io.npc_r <= _T_163 @[dec_tlu_ctl.scala 1602:11] + node _T_164 = or(sel_exu_npc_r, sel_flush_npc_r) @[dec_tlu_ctl.scala 1608:48] + node _T_165 = or(_T_164, io.reset_delayed) @[dec_tlu_ctl.scala 1608:66] + node _T_166 = bits(_T_165, 0, 0) @[dec_tlu_ctl.scala 1608:86] inst rvclkhdr_6 of rvclkhdr_726 @[lib.scala 352:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset @@ -73174,11 +73174,11 @@ circuit quasar_wrapper : rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_167 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_167 <= io.npc_r @[lib.scala 358:16] - io.npc_r_d1 <= _T_167 @[dec_tlu_ctl.scala 1612:14] - node _T_168 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1615:21] - node _T_169 = and(_T_168, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1615:44] - node pc0_valid_r = bits(_T_169, 0, 0) @[dec_tlu_ctl.scala 1615:69] - node _T_170 = not(pc0_valid_r) @[dec_tlu_ctl.scala 1619:22] + io.npc_r_d1 <= _T_167 @[dec_tlu_ctl.scala 1608:14] + node _T_168 = eq(io.dec_tlu_dbg_halted, UInt<1>("h00")) @[dec_tlu_ctl.scala 1611:21] + node _T_169 = and(_T_168, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 1611:44] + node pc0_valid_r = bits(_T_169, 0, 0) @[dec_tlu_ctl.scala 1611:69] + node _T_170 = not(pc0_valid_r) @[dec_tlu_ctl.scala 1615:22] node _T_171 = mux(pc0_valid_r, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_172 = mux(_T_170, pc_r_d1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_173 = or(_T_171, _T_172) @[Mux.scala 27:72] @@ -73192,22 +73192,22 @@ circuit quasar_wrapper : rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_174 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_174 <= pc_r @[lib.scala 358:16] - pc_r_d1 <= _T_174 @[dec_tlu_ctl.scala 1621:10] - node _T_175 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1623:61] - node _T_176 = eq(_T_175, UInt<12>("h0341")) @[dec_tlu_ctl.scala 1623:68] - node wr_mepc_r = and(io.dec_csr_wen_r_mod, _T_176) @[dec_tlu_ctl.scala 1623:39] - node _T_177 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1626:27] - node _T_178 = or(_T_177, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1626:48] - node _T_179 = bits(_T_178, 0, 0) @[dec_tlu_ctl.scala 1626:80] - node _T_180 = bits(io.interrupt_valid_r, 0, 0) @[dec_tlu_ctl.scala 1627:25] - node _T_181 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1628:15] - node _T_182 = and(wr_mepc_r, _T_181) @[dec_tlu_ctl.scala 1628:13] - node _T_183 = bits(_T_182, 0, 0) @[dec_tlu_ctl.scala 1628:39] - node _T_184 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 1628:104] - node _T_185 = eq(wr_mepc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1629:3] - node _T_186 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1629:16] - node _T_187 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 1629:14] - node _T_188 = bits(_T_187, 0, 0) @[dec_tlu_ctl.scala 1629:40] + pc_r_d1 <= _T_174 @[dec_tlu_ctl.scala 1617:10] + node _T_175 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1619:61] + node _T_176 = eq(_T_175, UInt<12>("h0341")) @[dec_tlu_ctl.scala 1619:68] + node wr_mepc_r = and(io.dec_csr_wen_r_mod, _T_176) @[dec_tlu_ctl.scala 1619:39] + node _T_177 = or(io.i0_exception_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1622:27] + node _T_178 = or(_T_177, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1622:48] + node _T_179 = bits(_T_178, 0, 0) @[dec_tlu_ctl.scala 1622:80] + node _T_180 = bits(io.interrupt_valid_r, 0, 0) @[dec_tlu_ctl.scala 1623:25] + node _T_181 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1624:15] + node _T_182 = and(wr_mepc_r, _T_181) @[dec_tlu_ctl.scala 1624:13] + node _T_183 = bits(_T_182, 0, 0) @[dec_tlu_ctl.scala 1624:39] + node _T_184 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 1624:104] + node _T_185 = eq(wr_mepc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1625:3] + node _T_186 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1625:16] + node _T_187 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 1625:14] + node _T_188 = bits(_T_187, 0, 0) @[dec_tlu_ctl.scala 1625:40] node _T_189 = mux(_T_179, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_190 = mux(_T_180, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_191 = mux(_T_183, _T_184, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73217,42 +73217,42 @@ circuit quasar_wrapper : node _T_195 = or(_T_194, _T_192) @[Mux.scala 27:72] wire mepc_ns : UInt<31> @[Mux.scala 27:72] mepc_ns <= _T_195 @[Mux.scala 27:72] - reg _T_196 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1631:47] - _T_196 <= mepc_ns @[dec_tlu_ctl.scala 1631:47] - io.mepc <= _T_196 @[dec_tlu_ctl.scala 1631:10] - node _T_197 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1638:65] - node _T_198 = eq(_T_197, UInt<12>("h0342")) @[dec_tlu_ctl.scala 1638:72] - node wr_mcause_r = and(io.dec_csr_wen_r_mod, _T_198) @[dec_tlu_ctl.scala 1638:43] - node _T_199 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1639:53] - node mcause_sel_nmi_store = and(_T_199, io.nmi_lsu_store_type) @[dec_tlu_ctl.scala 1639:67] - node _T_200 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1640:52] - node mcause_sel_nmi_load = and(_T_200, io.nmi_lsu_load_type) @[dec_tlu_ctl.scala 1640:66] - node _T_201 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1641:51] - node _T_202 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1641:84] - node mcause_sel_nmi_ext = and(_T_201, _T_202) @[dec_tlu_ctl.scala 1641:65] - node _T_203 = andr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1647:53] - node _T_204 = bits(io.lsu_fir_error, 1, 1) @[dec_tlu_ctl.scala 1647:76] - node _T_205 = bits(io.lsu_fir_error, 0, 0) @[dec_tlu_ctl.scala 1647:99] - node _T_206 = not(_T_205) @[dec_tlu_ctl.scala 1647:82] - node _T_207 = and(_T_204, _T_206) @[dec_tlu_ctl.scala 1647:80] + reg _T_196 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1627:47] + _T_196 <= mepc_ns @[dec_tlu_ctl.scala 1627:47] + io.mepc <= _T_196 @[dec_tlu_ctl.scala 1627:10] + node _T_197 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1634:65] + node _T_198 = eq(_T_197, UInt<12>("h0342")) @[dec_tlu_ctl.scala 1634:72] + node wr_mcause_r = and(io.dec_csr_wen_r_mod, _T_198) @[dec_tlu_ctl.scala 1634:43] + node _T_199 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1635:53] + node mcause_sel_nmi_store = and(_T_199, io.nmi_lsu_store_type) @[dec_tlu_ctl.scala 1635:67] + node _T_200 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1636:52] + node mcause_sel_nmi_load = and(_T_200, io.nmi_lsu_load_type) @[dec_tlu_ctl.scala 1636:66] + node _T_201 = and(io.exc_or_int_valid_r, io.take_nmi) @[dec_tlu_ctl.scala 1637:51] + node _T_202 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1637:84] + node mcause_sel_nmi_ext = and(_T_201, _T_202) @[dec_tlu_ctl.scala 1637:65] + node _T_203 = andr(io.lsu_fir_error) @[dec_tlu_ctl.scala 1643:53] + node _T_204 = bits(io.lsu_fir_error, 1, 1) @[dec_tlu_ctl.scala 1643:76] + node _T_205 = bits(io.lsu_fir_error, 0, 0) @[dec_tlu_ctl.scala 1643:99] + node _T_206 = not(_T_205) @[dec_tlu_ctl.scala 1643:82] + node _T_207 = and(_T_204, _T_206) @[dec_tlu_ctl.scala 1643:80] node mcause_fir_error_type = cat(_T_203, _T_207) @[Cat.scala 29:58] - node _T_208 = bits(mcause_sel_nmi_store, 0, 0) @[dec_tlu_ctl.scala 1650:52] - node _T_209 = bits(mcause_sel_nmi_load, 0, 0) @[dec_tlu_ctl.scala 1651:51] - node _T_210 = bits(mcause_sel_nmi_ext, 0, 0) @[dec_tlu_ctl.scala 1652:50] + node _T_208 = bits(mcause_sel_nmi_store, 0, 0) @[dec_tlu_ctl.scala 1646:52] + node _T_209 = bits(mcause_sel_nmi_load, 0, 0) @[dec_tlu_ctl.scala 1647:51] + node _T_210 = bits(mcause_sel_nmi_ext, 0, 0) @[dec_tlu_ctl.scala 1648:50] node _T_211 = cat(UInt<28>("h0f000100"), UInt<2>("h00")) @[Cat.scala 29:58] node _T_212 = cat(_T_211, mcause_fir_error_type) @[Cat.scala 29:58] - node _T_213 = not(io.take_nmi) @[dec_tlu_ctl.scala 1653:56] - node _T_214 = and(io.exc_or_int_valid_r, _T_213) @[dec_tlu_ctl.scala 1653:54] - node _T_215 = bits(_T_214, 0, 0) @[dec_tlu_ctl.scala 1653:70] + node _T_213 = not(io.take_nmi) @[dec_tlu_ctl.scala 1649:56] + node _T_214 = and(io.exc_or_int_valid_r, _T_213) @[dec_tlu_ctl.scala 1649:54] + node _T_215 = bits(_T_214, 0, 0) @[dec_tlu_ctl.scala 1649:70] node _T_216 = cat(io.interrupt_valid_r, UInt<26>("h00")) @[Cat.scala 29:58] node _T_217 = cat(_T_216, io.exc_cause_r) @[Cat.scala 29:58] - node _T_218 = not(io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1654:46] - node _T_219 = and(wr_mcause_r, _T_218) @[dec_tlu_ctl.scala 1654:44] - node _T_220 = bits(_T_219, 0, 0) @[dec_tlu_ctl.scala 1654:70] - node _T_221 = not(wr_mcause_r) @[dec_tlu_ctl.scala 1655:32] - node _T_222 = not(io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1655:47] - node _T_223 = and(_T_221, _T_222) @[dec_tlu_ctl.scala 1655:45] - node _T_224 = bits(_T_223, 0, 0) @[dec_tlu_ctl.scala 1655:71] + node _T_218 = not(io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1650:46] + node _T_219 = and(wr_mcause_r, _T_218) @[dec_tlu_ctl.scala 1650:44] + node _T_220 = bits(_T_219, 0, 0) @[dec_tlu_ctl.scala 1650:70] + node _T_221 = not(wr_mcause_r) @[dec_tlu_ctl.scala 1651:32] + node _T_222 = not(io.exc_or_int_valid_r) @[dec_tlu_ctl.scala 1651:47] + node _T_223 = and(_T_221, _T_222) @[dec_tlu_ctl.scala 1651:45] + node _T_224 = bits(_T_223, 0, 0) @[dec_tlu_ctl.scala 1651:71] node _T_225 = mux(_T_208, UInt<32>("h0f0000000"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_226 = mux(_T_209, UInt<32>("h0f0000001"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_227 = mux(_T_210, _T_212, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73266,19 +73266,19 @@ circuit quasar_wrapper : node _T_235 = or(_T_234, _T_230) @[Mux.scala 27:72] wire mcause_ns : UInt<32> @[Mux.scala 27:72] mcause_ns <= _T_235 @[Mux.scala 27:72] - reg _T_236 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1657:49] - _T_236 <= mcause_ns @[dec_tlu_ctl.scala 1657:49] - mcause <= _T_236 @[dec_tlu_ctl.scala 1657:12] - node _T_237 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1664:64] - node _T_238 = eq(_T_237, UInt<12>("h07ff")) @[dec_tlu_ctl.scala 1664:71] - node wr_mscause_r = and(io.dec_csr_wen_r_mod, _T_238) @[dec_tlu_ctl.scala 1664:42] - node _T_239 = eq(io.dec_tlu_packet_r.icaf_type, UInt<2>("h00")) @[dec_tlu_ctl.scala 1666:56] + reg _T_236 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1653:49] + _T_236 <= mcause_ns @[dec_tlu_ctl.scala 1653:49] + mcause <= _T_236 @[dec_tlu_ctl.scala 1653:12] + node _T_237 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1660:64] + node _T_238 = eq(_T_237, UInt<12>("h07ff")) @[dec_tlu_ctl.scala 1660:71] + node wr_mscause_r = and(io.dec_csr_wen_r_mod, _T_238) @[dec_tlu_ctl.scala 1660:42] + node _T_239 = eq(io.dec_tlu_packet_r.icaf_type, UInt<2>("h00")) @[dec_tlu_ctl.scala 1662:56] node _T_240 = cat(UInt<2>("h00"), io.dec_tlu_packet_r.icaf_type) @[Cat.scala 29:58] - node ifu_mscause = mux(_T_239, UInt<4>("h09"), _T_240) @[dec_tlu_ctl.scala 1666:24] - node _T_241 = bits(io.lsu_i0_exc_r, 0, 0) @[dec_tlu_ctl.scala 1669:36] - node _T_242 = bits(io.i0_trigger_hit_r, 0, 0) @[dec_tlu_ctl.scala 1670:40] - node _T_243 = bits(io.ebreak_r, 0, 0) @[dec_tlu_ctl.scala 1671:32] - node _T_244 = bits(io.inst_acc_r, 0, 0) @[dec_tlu_ctl.scala 1672:34] + node ifu_mscause = mux(_T_239, UInt<4>("h09"), _T_240) @[dec_tlu_ctl.scala 1662:24] + node _T_241 = bits(io.lsu_i0_exc_r, 0, 0) @[dec_tlu_ctl.scala 1665:36] + node _T_242 = bits(io.i0_trigger_hit_r, 0, 0) @[dec_tlu_ctl.scala 1666:40] + node _T_243 = bits(io.ebreak_r, 0, 0) @[dec_tlu_ctl.scala 1667:32] + node _T_244 = bits(io.inst_acc_r, 0, 0) @[dec_tlu_ctl.scala 1668:34] node _T_245 = mux(_T_241, io.lsu_error_pkt_r.bits.mscause, UInt<1>("h00")) @[Mux.scala 27:72] node _T_246 = mux(_T_242, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_247 = mux(_T_243, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -73288,15 +73288,15 @@ circuit quasar_wrapper : node _T_251 = or(_T_250, _T_248) @[Mux.scala 27:72] wire mscause_type : UInt<4> @[Mux.scala 27:72] mscause_type <= _T_251 @[Mux.scala 27:72] - node _T_252 = bits(io.exc_or_int_valid_r, 0, 0) @[dec_tlu_ctl.scala 1676:48] - node _T_253 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1677:40] - node _T_254 = and(wr_mscause_r, _T_253) @[dec_tlu_ctl.scala 1677:38] - node _T_255 = bits(_T_254, 0, 0) @[dec_tlu_ctl.scala 1677:64] - node _T_256 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1677:103] - node _T_257 = eq(wr_mscause_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1678:25] - node _T_258 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1678:41] - node _T_259 = and(_T_257, _T_258) @[dec_tlu_ctl.scala 1678:39] - node _T_260 = bits(_T_259, 0, 0) @[dec_tlu_ctl.scala 1678:65] + node _T_252 = bits(io.exc_or_int_valid_r, 0, 0) @[dec_tlu_ctl.scala 1672:48] + node _T_253 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1673:40] + node _T_254 = and(wr_mscause_r, _T_253) @[dec_tlu_ctl.scala 1673:38] + node _T_255 = bits(_T_254, 0, 0) @[dec_tlu_ctl.scala 1673:64] + node _T_256 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1673:103] + node _T_257 = eq(wr_mscause_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1674:25] + node _T_258 = eq(io.exc_or_int_valid_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 1674:41] + node _T_259 = and(_T_257, _T_258) @[dec_tlu_ctl.scala 1674:39] + node _T_260 = bits(_T_259, 0, 0) @[dec_tlu_ctl.scala 1674:65] node _T_261 = mux(_T_252, mscause_type, UInt<1>("h00")) @[Mux.scala 27:72] node _T_262 = mux(_T_255, _T_256, UInt<1>("h00")) @[Mux.scala 27:72] node _T_263 = mux(_T_260, mscause, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73304,60 +73304,60 @@ circuit quasar_wrapper : node _T_265 = or(_T_264, _T_263) @[Mux.scala 27:72] wire mscause_ns : UInt<4> @[Mux.scala 27:72] mscause_ns <= _T_265 @[Mux.scala 27:72] - reg _T_266 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1680:47] - _T_266 <= mscause_ns @[dec_tlu_ctl.scala 1680:47] - mscause <= _T_266 @[dec_tlu_ctl.scala 1680:10] - node _T_267 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1687:62] - node _T_268 = eq(_T_267, UInt<12>("h0343")) @[dec_tlu_ctl.scala 1687:69] - node wr_mtval_r = and(io.dec_csr_wen_r_mod, _T_268) @[dec_tlu_ctl.scala 1687:40] - node _T_269 = not(io.inst_acc_second_r) @[dec_tlu_ctl.scala 1688:83] - node _T_270 = and(io.inst_acc_r, _T_269) @[dec_tlu_ctl.scala 1688:81] - node _T_271 = or(io.ebreak_r, _T_270) @[dec_tlu_ctl.scala 1688:64] - node _T_272 = or(_T_271, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1688:106] - node _T_273 = and(io.exc_or_int_valid_r, _T_272) @[dec_tlu_ctl.scala 1688:49] - node _T_274 = not(io.take_nmi) @[dec_tlu_ctl.scala 1688:140] - node mtval_capture_pc_r = and(_T_273, _T_274) @[dec_tlu_ctl.scala 1688:138] - node _T_275 = and(io.inst_acc_r, io.inst_acc_second_r) @[dec_tlu_ctl.scala 1689:72] - node _T_276 = and(io.exc_or_int_valid_r, _T_275) @[dec_tlu_ctl.scala 1689:55] - node _T_277 = not(io.take_nmi) @[dec_tlu_ctl.scala 1689:98] - node mtval_capture_pc_plus2_r = and(_T_276, _T_277) @[dec_tlu_ctl.scala 1689:96] - node _T_278 = and(io.exc_or_int_valid_r, io.illegal_r) @[dec_tlu_ctl.scala 1690:51] - node _T_279 = not(io.take_nmi) @[dec_tlu_ctl.scala 1690:68] - node mtval_capture_inst_r = and(_T_278, _T_279) @[dec_tlu_ctl.scala 1690:66] - node _T_280 = and(io.exc_or_int_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1691:50] - node _T_281 = not(io.take_nmi) @[dec_tlu_ctl.scala 1691:73] - node mtval_capture_lsu_r = and(_T_280, _T_281) @[dec_tlu_ctl.scala 1691:71] - node _T_282 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1692:46] - node _T_283 = and(io.exc_or_int_valid_r, _T_282) @[dec_tlu_ctl.scala 1692:44] - node _T_284 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1692:68] - node _T_285 = and(_T_283, _T_284) @[dec_tlu_ctl.scala 1692:66] - node _T_286 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1692:92] - node _T_287 = and(_T_285, _T_286) @[dec_tlu_ctl.scala 1692:90] - node _T_288 = not(io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1692:115] - node mtval_clear_r = and(_T_287, _T_288) @[dec_tlu_ctl.scala 1692:113] - node _T_289 = bits(mtval_capture_pc_r, 0, 0) @[dec_tlu_ctl.scala 1696:25] + reg _T_266 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1676:47] + _T_266 <= mscause_ns @[dec_tlu_ctl.scala 1676:47] + mscause <= _T_266 @[dec_tlu_ctl.scala 1676:10] + node _T_267 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1683:62] + node _T_268 = eq(_T_267, UInt<12>("h0343")) @[dec_tlu_ctl.scala 1683:69] + node wr_mtval_r = and(io.dec_csr_wen_r_mod, _T_268) @[dec_tlu_ctl.scala 1683:40] + node _T_269 = not(io.inst_acc_second_r) @[dec_tlu_ctl.scala 1684:83] + node _T_270 = and(io.inst_acc_r, _T_269) @[dec_tlu_ctl.scala 1684:81] + node _T_271 = or(io.ebreak_r, _T_270) @[dec_tlu_ctl.scala 1684:64] + node _T_272 = or(_T_271, io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1684:106] + node _T_273 = and(io.exc_or_int_valid_r, _T_272) @[dec_tlu_ctl.scala 1684:49] + node _T_274 = not(io.take_nmi) @[dec_tlu_ctl.scala 1684:140] + node mtval_capture_pc_r = and(_T_273, _T_274) @[dec_tlu_ctl.scala 1684:138] + node _T_275 = and(io.inst_acc_r, io.inst_acc_second_r) @[dec_tlu_ctl.scala 1685:72] + node _T_276 = and(io.exc_or_int_valid_r, _T_275) @[dec_tlu_ctl.scala 1685:55] + node _T_277 = not(io.take_nmi) @[dec_tlu_ctl.scala 1685:98] + node mtval_capture_pc_plus2_r = and(_T_276, _T_277) @[dec_tlu_ctl.scala 1685:96] + node _T_278 = and(io.exc_or_int_valid_r, io.illegal_r) @[dec_tlu_ctl.scala 1686:51] + node _T_279 = not(io.take_nmi) @[dec_tlu_ctl.scala 1686:68] + node mtval_capture_inst_r = and(_T_278, _T_279) @[dec_tlu_ctl.scala 1686:66] + node _T_280 = and(io.exc_or_int_valid_r, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 1687:50] + node _T_281 = not(io.take_nmi) @[dec_tlu_ctl.scala 1687:73] + node mtval_capture_lsu_r = and(_T_280, _T_281) @[dec_tlu_ctl.scala 1687:71] + node _T_282 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1688:46] + node _T_283 = and(io.exc_or_int_valid_r, _T_282) @[dec_tlu_ctl.scala 1688:44] + node _T_284 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1688:68] + node _T_285 = and(_T_283, _T_284) @[dec_tlu_ctl.scala 1688:66] + node _T_286 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1688:92] + node _T_287 = and(_T_285, _T_286) @[dec_tlu_ctl.scala 1688:90] + node _T_288 = not(io.mepc_trigger_hit_sel_pc_r) @[dec_tlu_ctl.scala 1688:115] + node mtval_clear_r = and(_T_287, _T_288) @[dec_tlu_ctl.scala 1688:113] + node _T_289 = bits(mtval_capture_pc_r, 0, 0) @[dec_tlu_ctl.scala 1692:25] node _T_290 = cat(pc_r, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_291 = bits(mtval_capture_pc_plus2_r, 0, 0) @[dec_tlu_ctl.scala 1697:31] - node _T_292 = add(pc_r, UInt<31>("h01")) @[dec_tlu_ctl.scala 1697:83] - node _T_293 = tail(_T_292, 1) @[dec_tlu_ctl.scala 1697:83] + node _T_291 = bits(mtval_capture_pc_plus2_r, 0, 0) @[dec_tlu_ctl.scala 1693:31] + node _T_292 = add(pc_r, UInt<31>("h01")) @[dec_tlu_ctl.scala 1693:83] + node _T_293 = tail(_T_292, 1) @[dec_tlu_ctl.scala 1693:83] node _T_294 = cat(_T_293, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_295 = bits(mtval_capture_inst_r, 0, 0) @[dec_tlu_ctl.scala 1698:27] - node _T_296 = bits(mtval_capture_lsu_r, 0, 0) @[dec_tlu_ctl.scala 1699:26] - node _T_297 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1700:18] - node _T_298 = and(wr_mtval_r, _T_297) @[dec_tlu_ctl.scala 1700:16] - node _T_299 = bits(_T_298, 0, 0) @[dec_tlu_ctl.scala 1700:48] - node _T_300 = not(io.take_nmi) @[dec_tlu_ctl.scala 1701:5] - node _T_301 = not(wr_mtval_r) @[dec_tlu_ctl.scala 1701:20] - node _T_302 = and(_T_300, _T_301) @[dec_tlu_ctl.scala 1701:18] - node _T_303 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1701:34] - node _T_304 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 1701:32] - node _T_305 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1701:56] - node _T_306 = and(_T_304, _T_305) @[dec_tlu_ctl.scala 1701:54] - node _T_307 = not(mtval_clear_r) @[dec_tlu_ctl.scala 1701:80] - node _T_308 = and(_T_306, _T_307) @[dec_tlu_ctl.scala 1701:78] - node _T_309 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1701:97] - node _T_310 = and(_T_308, _T_309) @[dec_tlu_ctl.scala 1701:95] - node _T_311 = bits(_T_310, 0, 0) @[dec_tlu_ctl.scala 1701:119] + node _T_295 = bits(mtval_capture_inst_r, 0, 0) @[dec_tlu_ctl.scala 1694:27] + node _T_296 = bits(mtval_capture_lsu_r, 0, 0) @[dec_tlu_ctl.scala 1695:26] + node _T_297 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1696:18] + node _T_298 = and(wr_mtval_r, _T_297) @[dec_tlu_ctl.scala 1696:16] + node _T_299 = bits(_T_298, 0, 0) @[dec_tlu_ctl.scala 1696:48] + node _T_300 = not(io.take_nmi) @[dec_tlu_ctl.scala 1697:5] + node _T_301 = not(wr_mtval_r) @[dec_tlu_ctl.scala 1697:20] + node _T_302 = and(_T_300, _T_301) @[dec_tlu_ctl.scala 1697:18] + node _T_303 = not(mtval_capture_pc_r) @[dec_tlu_ctl.scala 1697:34] + node _T_304 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 1697:32] + node _T_305 = not(mtval_capture_inst_r) @[dec_tlu_ctl.scala 1697:56] + node _T_306 = and(_T_304, _T_305) @[dec_tlu_ctl.scala 1697:54] + node _T_307 = not(mtval_clear_r) @[dec_tlu_ctl.scala 1697:80] + node _T_308 = and(_T_306, _T_307) @[dec_tlu_ctl.scala 1697:78] + node _T_309 = not(mtval_capture_lsu_r) @[dec_tlu_ctl.scala 1697:97] + node _T_310 = and(_T_308, _T_309) @[dec_tlu_ctl.scala 1697:95] + node _T_311 = bits(_T_310, 0, 0) @[dec_tlu_ctl.scala 1697:119] node _T_312 = mux(_T_289, _T_290, UInt<1>("h00")) @[Mux.scala 27:72] node _T_313 = mux(_T_291, _T_294, UInt<1>("h00")) @[Mux.scala 27:72] node _T_314 = mux(_T_295, io.dec_illegal_inst, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73371,14 +73371,14 @@ circuit quasar_wrapper : node _T_322 = or(_T_321, _T_317) @[Mux.scala 27:72] wire mtval_ns : UInt<32> @[Mux.scala 27:72] mtval_ns <= _T_322 @[Mux.scala 27:72] - reg _T_323 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1703:46] - _T_323 <= mtval_ns @[dec_tlu_ctl.scala 1703:46] - mtval <= _T_323 @[dec_tlu_ctl.scala 1703:8] - node _T_324 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1718:61] - node _T_325 = eq(_T_324, UInt<12>("h07f8")) @[dec_tlu_ctl.scala 1718:68] - node wr_mcgc_r = and(io.dec_csr_wen_r_mod, _T_325) @[dec_tlu_ctl.scala 1718:39] - node _T_326 = bits(io.dec_csr_wrdata_r, 8, 0) @[dec_tlu_ctl.scala 1720:39] - node _T_327 = bits(wr_mcgc_r, 0, 0) @[dec_tlu_ctl.scala 1720:55] + reg _T_323 : UInt, io.e4e5_int_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1699:46] + _T_323 <= mtval_ns @[dec_tlu_ctl.scala 1699:46] + mtval <= _T_323 @[dec_tlu_ctl.scala 1699:8] + node _T_324 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1714:61] + node _T_325 = eq(_T_324, UInt<12>("h07f8")) @[dec_tlu_ctl.scala 1714:68] + node wr_mcgc_r = and(io.dec_csr_wen_r_mod, _T_325) @[dec_tlu_ctl.scala 1714:39] + node _T_326 = bits(io.dec_csr_wrdata_r, 8, 0) @[dec_tlu_ctl.scala 1716:39] + node _T_327 = bits(wr_mcgc_r, 0, 0) @[dec_tlu_ctl.scala 1716:55] inst rvclkhdr_8 of rvclkhdr_728 @[lib.scala 352:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset @@ -73387,26 +73387,26 @@ circuit quasar_wrapper : rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg mcgc : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] mcgc <= _T_326 @[lib.scala 358:16] - node _T_328 = bits(mcgc, 8, 8) @[dec_tlu_ctl.scala 1722:38] - io.dec_tlu_misc_clk_override <= _T_328 @[dec_tlu_ctl.scala 1722:31] - node _T_329 = bits(mcgc, 7, 7) @[dec_tlu_ctl.scala 1723:38] - io.dec_tlu_dec_clk_override <= _T_329 @[dec_tlu_ctl.scala 1723:31] - node _T_330 = bits(mcgc, 5, 5) @[dec_tlu_ctl.scala 1724:38] - io.dec_tlu_ifu_clk_override <= _T_330 @[dec_tlu_ctl.scala 1724:31] - node _T_331 = bits(mcgc, 4, 4) @[dec_tlu_ctl.scala 1725:38] - io.dec_tlu_lsu_clk_override <= _T_331 @[dec_tlu_ctl.scala 1725:31] - node _T_332 = bits(mcgc, 3, 3) @[dec_tlu_ctl.scala 1726:38] - io.dec_tlu_bus_clk_override <= _T_332 @[dec_tlu_ctl.scala 1726:31] - node _T_333 = bits(mcgc, 2, 2) @[dec_tlu_ctl.scala 1727:38] - io.dec_tlu_pic_clk_override <= _T_333 @[dec_tlu_ctl.scala 1727:31] - node _T_334 = bits(mcgc, 1, 1) @[dec_tlu_ctl.scala 1728:38] - io.dec_tlu_dccm_clk_override <= _T_334 @[dec_tlu_ctl.scala 1728:31] - node _T_335 = bits(mcgc, 0, 0) @[dec_tlu_ctl.scala 1729:38] - io.dec_tlu_icm_clk_override <= _T_335 @[dec_tlu_ctl.scala 1729:31] - node _T_336 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1748:61] - node _T_337 = eq(_T_336, UInt<12>("h07f9")) @[dec_tlu_ctl.scala 1748:68] - node wr_mfdc_r = and(io.dec_csr_wen_r_mod, _T_337) @[dec_tlu_ctl.scala 1748:39] - node _T_338 = bits(wr_mfdc_r, 0, 0) @[dec_tlu_ctl.scala 1752:39] + node _T_328 = bits(mcgc, 8, 8) @[dec_tlu_ctl.scala 1718:38] + io.dec_tlu_misc_clk_override <= _T_328 @[dec_tlu_ctl.scala 1718:31] + node _T_329 = bits(mcgc, 7, 7) @[dec_tlu_ctl.scala 1719:38] + io.dec_tlu_dec_clk_override <= _T_329 @[dec_tlu_ctl.scala 1719:31] + node _T_330 = bits(mcgc, 5, 5) @[dec_tlu_ctl.scala 1720:38] + io.dec_tlu_ifu_clk_override <= _T_330 @[dec_tlu_ctl.scala 1720:31] + node _T_331 = bits(mcgc, 4, 4) @[dec_tlu_ctl.scala 1721:38] + io.dec_tlu_lsu_clk_override <= _T_331 @[dec_tlu_ctl.scala 1721:31] + node _T_332 = bits(mcgc, 3, 3) @[dec_tlu_ctl.scala 1722:38] + io.dec_tlu_bus_clk_override <= _T_332 @[dec_tlu_ctl.scala 1722:31] + node _T_333 = bits(mcgc, 2, 2) @[dec_tlu_ctl.scala 1723:38] + io.dec_tlu_pic_clk_override <= _T_333 @[dec_tlu_ctl.scala 1723:31] + node _T_334 = bits(mcgc, 1, 1) @[dec_tlu_ctl.scala 1724:38] + io.dec_tlu_dccm_clk_override <= _T_334 @[dec_tlu_ctl.scala 1724:31] + node _T_335 = bits(mcgc, 0, 0) @[dec_tlu_ctl.scala 1725:38] + io.dec_tlu_icm_clk_override <= _T_335 @[dec_tlu_ctl.scala 1725:31] + node _T_336 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1744:61] + node _T_337 = eq(_T_336, UInt<12>("h07f9")) @[dec_tlu_ctl.scala 1744:68] + node wr_mfdc_r = and(io.dec_csr_wen_r_mod, _T_337) @[dec_tlu_ctl.scala 1744:39] + node _T_338 = bits(wr_mfdc_r, 0, 0) @[dec_tlu_ctl.scala 1748:39] inst rvclkhdr_9 of rvclkhdr_729 @[lib.scala 352:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset @@ -73415,123 +73415,123 @@ circuit quasar_wrapper : rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_339 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_339 <= mfdc_ns @[lib.scala 358:16] - mfdc_int <= _T_339 @[dec_tlu_ctl.scala 1752:11] - node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1761:39] - node _T_341 = not(_T_340) @[dec_tlu_ctl.scala 1761:19] - node _T_342 = bits(io.dec_csr_wrdata_r, 11, 0) @[dec_tlu_ctl.scala 1761:66] + mfdc_int <= _T_339 @[dec_tlu_ctl.scala 1748:11] + node _T_340 = bits(io.dec_csr_wrdata_r, 18, 16) @[dec_tlu_ctl.scala 1757:39] + node _T_341 = not(_T_340) @[dec_tlu_ctl.scala 1757:19] + node _T_342 = bits(io.dec_csr_wrdata_r, 11, 0) @[dec_tlu_ctl.scala 1757:66] node _T_343 = cat(_T_341, _T_342) @[Cat.scala 29:58] - mfdc_ns <= _T_343 @[dec_tlu_ctl.scala 1761:12] - node _T_344 = bits(mfdc_int, 14, 12) @[dec_tlu_ctl.scala 1762:28] - node _T_345 = not(_T_344) @[dec_tlu_ctl.scala 1762:19] - node _T_346 = bits(mfdc_int, 11, 0) @[dec_tlu_ctl.scala 1762:54] + mfdc_ns <= _T_343 @[dec_tlu_ctl.scala 1757:12] + node _T_344 = bits(mfdc_int, 14, 12) @[dec_tlu_ctl.scala 1758:28] + node _T_345 = not(_T_344) @[dec_tlu_ctl.scala 1758:19] + node _T_346 = bits(mfdc_int, 11, 0) @[dec_tlu_ctl.scala 1758:54] node _T_347 = cat(_T_345, UInt<4>("h00")) @[Cat.scala 29:58] node _T_348 = cat(_T_347, _T_346) @[Cat.scala 29:58] - mfdc <= _T_348 @[dec_tlu_ctl.scala 1762:12] - node _T_349 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1766:46] - io.dec_tlu_dma_qos_prty <= _T_349 @[dec_tlu_ctl.scala 1766:39] - node _T_350 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1767:46] - io.dec_tlu_external_ldfwd_disable <= _T_350 @[dec_tlu_ctl.scala 1767:39] - node _T_351 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1768:46] - io.dec_tlu_core_ecc_disable <= _T_351 @[dec_tlu_ctl.scala 1768:39] - node _T_352 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1769:46] - io.dec_tlu_sideeffect_posted_disable <= _T_352 @[dec_tlu_ctl.scala 1769:39] - node _T_353 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1770:46] - io.dec_tlu_bpred_disable <= _T_353 @[dec_tlu_ctl.scala 1770:39] - node _T_354 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1771:46] - io.dec_tlu_wb_coalescing_disable <= _T_354 @[dec_tlu_ctl.scala 1771:39] - node _T_355 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1772:46] - io.dec_tlu_pipelining_disable <= _T_355 @[dec_tlu_ctl.scala 1772:39] - node _T_356 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1781:70] - node _T_357 = eq(_T_356, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1781:77] - node _T_358 = and(io.dec_csr_wen_r_mod, _T_357) @[dec_tlu_ctl.scala 1781:48] - node _T_359 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1781:89] - node _T_360 = and(_T_358, _T_359) @[dec_tlu_ctl.scala 1781:87] - node _T_361 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1781:113] - node _T_362 = and(_T_360, _T_361) @[dec_tlu_ctl.scala 1781:111] - io.dec_tlu_wr_pause_r <= _T_362 @[dec_tlu_ctl.scala 1781:24] - node _T_363 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1788:61] - node _T_364 = eq(_T_363, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1788:68] - node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_364) @[dec_tlu_ctl.scala 1788:39] - node _T_365 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1791:39] - node _T_366 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1791:64] - node _T_367 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1791:91] - node _T_368 = not(_T_367) @[dec_tlu_ctl.scala 1791:71] - node _T_369 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 1791:69] - node _T_370 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1792:41] - node _T_371 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1792:66] - node _T_372 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1792:93] - node _T_373 = not(_T_372) @[dec_tlu_ctl.scala 1792:73] - node _T_374 = and(_T_371, _T_373) @[dec_tlu_ctl.scala 1792:71] - node _T_375 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1793:41] - node _T_376 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1793:66] - node _T_377 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1793:93] - node _T_378 = not(_T_377) @[dec_tlu_ctl.scala 1793:73] - node _T_379 = and(_T_376, _T_378) @[dec_tlu_ctl.scala 1793:71] - node _T_380 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1794:41] - node _T_381 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1794:66] - node _T_382 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1794:93] - node _T_383 = not(_T_382) @[dec_tlu_ctl.scala 1794:73] - node _T_384 = and(_T_381, _T_383) @[dec_tlu_ctl.scala 1794:71] - node _T_385 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1795:41] - node _T_386 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1795:66] - node _T_387 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1795:93] - node _T_388 = not(_T_387) @[dec_tlu_ctl.scala 1795:73] - node _T_389 = and(_T_386, _T_388) @[dec_tlu_ctl.scala 1795:71] - node _T_390 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1796:41] - node _T_391 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1796:66] - node _T_392 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1796:93] - node _T_393 = not(_T_392) @[dec_tlu_ctl.scala 1796:73] - node _T_394 = and(_T_391, _T_393) @[dec_tlu_ctl.scala 1796:71] - node _T_395 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1797:41] - node _T_396 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1797:66] - node _T_397 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1797:93] - node _T_398 = not(_T_397) @[dec_tlu_ctl.scala 1797:73] - node _T_399 = and(_T_396, _T_398) @[dec_tlu_ctl.scala 1797:71] - node _T_400 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1798:41] - node _T_401 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1798:66] - node _T_402 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1798:93] - node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1798:73] - node _T_404 = and(_T_401, _T_403) @[dec_tlu_ctl.scala 1798:71] - node _T_405 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1799:41] - node _T_406 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1799:66] - node _T_407 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1799:93] - node _T_408 = not(_T_407) @[dec_tlu_ctl.scala 1799:73] - node _T_409 = and(_T_406, _T_408) @[dec_tlu_ctl.scala 1799:71] - node _T_410 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1800:41] - node _T_411 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1800:66] - node _T_412 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1800:93] - node _T_413 = not(_T_412) @[dec_tlu_ctl.scala 1800:73] - node _T_414 = and(_T_411, _T_413) @[dec_tlu_ctl.scala 1800:71] - node _T_415 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1801:41] - node _T_416 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1801:66] - node _T_417 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1801:93] - node _T_418 = not(_T_417) @[dec_tlu_ctl.scala 1801:73] - node _T_419 = and(_T_416, _T_418) @[dec_tlu_ctl.scala 1801:71] - node _T_420 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1802:41] - node _T_421 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1802:66] - node _T_422 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1802:93] - node _T_423 = not(_T_422) @[dec_tlu_ctl.scala 1802:73] - node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 1802:70] - node _T_425 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1803:41] - node _T_426 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1803:66] - node _T_427 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1803:93] - node _T_428 = not(_T_427) @[dec_tlu_ctl.scala 1803:73] - node _T_429 = and(_T_426, _T_428) @[dec_tlu_ctl.scala 1803:70] - node _T_430 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1804:41] - node _T_431 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1804:66] - node _T_432 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1804:93] - node _T_433 = not(_T_432) @[dec_tlu_ctl.scala 1804:73] - node _T_434 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 1804:70] - node _T_435 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1805:41] - node _T_436 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1805:66] - node _T_437 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1805:93] - node _T_438 = not(_T_437) @[dec_tlu_ctl.scala 1805:73] - node _T_439 = and(_T_436, _T_438) @[dec_tlu_ctl.scala 1805:70] - node _T_440 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1806:41] - node _T_441 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1806:66] - node _T_442 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1806:93] - node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 1806:73] - node _T_444 = and(_T_441, _T_443) @[dec_tlu_ctl.scala 1806:70] + mfdc <= _T_348 @[dec_tlu_ctl.scala 1758:12] + node _T_349 = bits(mfdc, 18, 16) @[dec_tlu_ctl.scala 1762:46] + io.dec_tlu_dma_qos_prty <= _T_349 @[dec_tlu_ctl.scala 1762:39] + node _T_350 = bits(mfdc, 11, 11) @[dec_tlu_ctl.scala 1763:46] + io.dec_tlu_external_ldfwd_disable <= _T_350 @[dec_tlu_ctl.scala 1763:39] + node _T_351 = bits(mfdc, 8, 8) @[dec_tlu_ctl.scala 1764:46] + io.dec_tlu_core_ecc_disable <= _T_351 @[dec_tlu_ctl.scala 1764:39] + node _T_352 = bits(mfdc, 6, 6) @[dec_tlu_ctl.scala 1765:46] + io.dec_tlu_sideeffect_posted_disable <= _T_352 @[dec_tlu_ctl.scala 1765:39] + node _T_353 = bits(mfdc, 3, 3) @[dec_tlu_ctl.scala 1766:46] + io.dec_tlu_bpred_disable <= _T_353 @[dec_tlu_ctl.scala 1766:39] + node _T_354 = bits(mfdc, 2, 2) @[dec_tlu_ctl.scala 1767:46] + io.dec_tlu_wb_coalescing_disable <= _T_354 @[dec_tlu_ctl.scala 1767:39] + node _T_355 = bits(mfdc, 0, 0) @[dec_tlu_ctl.scala 1768:46] + io.dec_tlu_pipelining_disable <= _T_355 @[dec_tlu_ctl.scala 1768:39] + node _T_356 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1777:70] + node _T_357 = eq(_T_356, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 1777:77] + node _T_358 = and(io.dec_csr_wen_r_mod, _T_357) @[dec_tlu_ctl.scala 1777:48] + node _T_359 = not(io.interrupt_valid_r) @[dec_tlu_ctl.scala 1777:89] + node _T_360 = and(_T_358, _T_359) @[dec_tlu_ctl.scala 1777:87] + node _T_361 = not(io.take_ext_int_start) @[dec_tlu_ctl.scala 1777:113] + node _T_362 = and(_T_360, _T_361) @[dec_tlu_ctl.scala 1777:111] + io.dec_tlu_wr_pause_r <= _T_362 @[dec_tlu_ctl.scala 1777:24] + node _T_363 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1784:61] + node _T_364 = eq(_T_363, UInt<12>("h07c0")) @[dec_tlu_ctl.scala 1784:68] + node wr_mrac_r = and(io.dec_csr_wen_r_mod, _T_364) @[dec_tlu_ctl.scala 1784:39] + node _T_365 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1787:39] + node _T_366 = bits(io.dec_csr_wrdata_r, 30, 30) @[dec_tlu_ctl.scala 1787:64] + node _T_367 = bits(io.dec_csr_wrdata_r, 31, 31) @[dec_tlu_ctl.scala 1787:91] + node _T_368 = not(_T_367) @[dec_tlu_ctl.scala 1787:71] + node _T_369 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 1787:69] + node _T_370 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1788:41] + node _T_371 = bits(io.dec_csr_wrdata_r, 28, 28) @[dec_tlu_ctl.scala 1788:66] + node _T_372 = bits(io.dec_csr_wrdata_r, 29, 29) @[dec_tlu_ctl.scala 1788:93] + node _T_373 = not(_T_372) @[dec_tlu_ctl.scala 1788:73] + node _T_374 = and(_T_371, _T_373) @[dec_tlu_ctl.scala 1788:71] + node _T_375 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1789:41] + node _T_376 = bits(io.dec_csr_wrdata_r, 26, 26) @[dec_tlu_ctl.scala 1789:66] + node _T_377 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 1789:93] + node _T_378 = not(_T_377) @[dec_tlu_ctl.scala 1789:73] + node _T_379 = and(_T_376, _T_378) @[dec_tlu_ctl.scala 1789:71] + node _T_380 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1790:41] + node _T_381 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 1790:66] + node _T_382 = bits(io.dec_csr_wrdata_r, 25, 25) @[dec_tlu_ctl.scala 1790:93] + node _T_383 = not(_T_382) @[dec_tlu_ctl.scala 1790:73] + node _T_384 = and(_T_381, _T_383) @[dec_tlu_ctl.scala 1790:71] + node _T_385 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1791:41] + node _T_386 = bits(io.dec_csr_wrdata_r, 22, 22) @[dec_tlu_ctl.scala 1791:66] + node _T_387 = bits(io.dec_csr_wrdata_r, 23, 23) @[dec_tlu_ctl.scala 1791:93] + node _T_388 = not(_T_387) @[dec_tlu_ctl.scala 1791:73] + node _T_389 = and(_T_386, _T_388) @[dec_tlu_ctl.scala 1791:71] + node _T_390 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1792:41] + node _T_391 = bits(io.dec_csr_wrdata_r, 20, 20) @[dec_tlu_ctl.scala 1792:66] + node _T_392 = bits(io.dec_csr_wrdata_r, 21, 21) @[dec_tlu_ctl.scala 1792:93] + node _T_393 = not(_T_392) @[dec_tlu_ctl.scala 1792:73] + node _T_394 = and(_T_391, _T_393) @[dec_tlu_ctl.scala 1792:71] + node _T_395 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1793:41] + node _T_396 = bits(io.dec_csr_wrdata_r, 18, 18) @[dec_tlu_ctl.scala 1793:66] + node _T_397 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 1793:93] + node _T_398 = not(_T_397) @[dec_tlu_ctl.scala 1793:73] + node _T_399 = and(_T_396, _T_398) @[dec_tlu_ctl.scala 1793:71] + node _T_400 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1794:41] + node _T_401 = bits(io.dec_csr_wrdata_r, 16, 16) @[dec_tlu_ctl.scala 1794:66] + node _T_402 = bits(io.dec_csr_wrdata_r, 17, 17) @[dec_tlu_ctl.scala 1794:93] + node _T_403 = not(_T_402) @[dec_tlu_ctl.scala 1794:73] + node _T_404 = and(_T_401, _T_403) @[dec_tlu_ctl.scala 1794:71] + node _T_405 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1795:41] + node _T_406 = bits(io.dec_csr_wrdata_r, 14, 14) @[dec_tlu_ctl.scala 1795:66] + node _T_407 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 1795:93] + node _T_408 = not(_T_407) @[dec_tlu_ctl.scala 1795:73] + node _T_409 = and(_T_406, _T_408) @[dec_tlu_ctl.scala 1795:71] + node _T_410 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1796:41] + node _T_411 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 1796:66] + node _T_412 = bits(io.dec_csr_wrdata_r, 13, 13) @[dec_tlu_ctl.scala 1796:93] + node _T_413 = not(_T_412) @[dec_tlu_ctl.scala 1796:73] + node _T_414 = and(_T_411, _T_413) @[dec_tlu_ctl.scala 1796:71] + node _T_415 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1797:41] + node _T_416 = bits(io.dec_csr_wrdata_r, 10, 10) @[dec_tlu_ctl.scala 1797:66] + node _T_417 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 1797:93] + node _T_418 = not(_T_417) @[dec_tlu_ctl.scala 1797:73] + node _T_419 = and(_T_416, _T_418) @[dec_tlu_ctl.scala 1797:71] + node _T_420 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1798:41] + node _T_421 = bits(io.dec_csr_wrdata_r, 8, 8) @[dec_tlu_ctl.scala 1798:66] + node _T_422 = bits(io.dec_csr_wrdata_r, 9, 9) @[dec_tlu_ctl.scala 1798:93] + node _T_423 = not(_T_422) @[dec_tlu_ctl.scala 1798:73] + node _T_424 = and(_T_421, _T_423) @[dec_tlu_ctl.scala 1798:70] + node _T_425 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1799:41] + node _T_426 = bits(io.dec_csr_wrdata_r, 6, 6) @[dec_tlu_ctl.scala 1799:66] + node _T_427 = bits(io.dec_csr_wrdata_r, 7, 7) @[dec_tlu_ctl.scala 1799:93] + node _T_428 = not(_T_427) @[dec_tlu_ctl.scala 1799:73] + node _T_429 = and(_T_426, _T_428) @[dec_tlu_ctl.scala 1799:70] + node _T_430 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1800:41] + node _T_431 = bits(io.dec_csr_wrdata_r, 4, 4) @[dec_tlu_ctl.scala 1800:66] + node _T_432 = bits(io.dec_csr_wrdata_r, 5, 5) @[dec_tlu_ctl.scala 1800:93] + node _T_433 = not(_T_432) @[dec_tlu_ctl.scala 1800:73] + node _T_434 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 1800:70] + node _T_435 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1801:41] + node _T_436 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 1801:66] + node _T_437 = bits(io.dec_csr_wrdata_r, 3, 3) @[dec_tlu_ctl.scala 1801:93] + node _T_438 = not(_T_437) @[dec_tlu_ctl.scala 1801:73] + node _T_439 = and(_T_436, _T_438) @[dec_tlu_ctl.scala 1801:70] + node _T_440 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1802:41] + node _T_441 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1802:66] + node _T_442 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1802:93] + node _T_443 = not(_T_442) @[dec_tlu_ctl.scala 1802:73] + node _T_444 = and(_T_441, _T_443) @[dec_tlu_ctl.scala 1802:70] node _T_445 = cat(_T_440, _T_444) @[Cat.scala 29:58] node _T_446 = cat(_T_435, _T_439) @[Cat.scala 29:58] node _T_447 = cat(_T_446, _T_445) @[Cat.scala 29:58] @@ -73563,7 +73563,7 @@ circuit quasar_wrapper : node _T_473 = cat(_T_472, _T_469) @[Cat.scala 29:58] node _T_474 = cat(_T_473, _T_466) @[Cat.scala 29:58] node mrac_in = cat(_T_474, _T_459) @[Cat.scala 29:58] - node _T_475 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1809:38] + node _T_475 = bits(wr_mrac_r, 0, 0) @[dec_tlu_ctl.scala 1805:38] inst rvclkhdr_10 of rvclkhdr_730 @[lib.scala 352:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset @@ -73572,21 +73572,21 @@ circuit quasar_wrapper : rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg mrac : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] mrac <= mrac_in @[lib.scala 358:16] - io.dec_tlu_mrac_ff <= mrac @[dec_tlu_ctl.scala 1811:21] - node _T_476 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1819:62] - node _T_477 = eq(_T_476, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1819:69] - node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_477) @[dec_tlu_ctl.scala 1819:40] - node _T_478 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1829:59] - node _T_479 = and(io.mdseac_locked_f, _T_478) @[dec_tlu_ctl.scala 1829:57] - node _T_480 = or(mdseac_en, _T_479) @[dec_tlu_ctl.scala 1829:35] - io.mdseac_locked_ns <= _T_480 @[dec_tlu_ctl.scala 1829:22] - node _T_481 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1831:49] - node _T_482 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1831:86] - node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 1831:84] - node _T_484 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1831:111] - node _T_485 = and(_T_483, _T_484) @[dec_tlu_ctl.scala 1831:109] - mdseac_en <= _T_485 @[dec_tlu_ctl.scala 1831:12] - node _T_486 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1833:64] + io.dec_tlu_mrac_ff <= mrac @[dec_tlu_ctl.scala 1807:21] + node _T_476 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1815:62] + node _T_477 = eq(_T_476, UInt<12>("h0bc0")) @[dec_tlu_ctl.scala 1815:69] + node wr_mdeau_r = and(io.dec_csr_wen_r_mod, _T_477) @[dec_tlu_ctl.scala 1815:40] + node _T_478 = not(wr_mdeau_r) @[dec_tlu_ctl.scala 1825:59] + node _T_479 = and(io.mdseac_locked_f, _T_478) @[dec_tlu_ctl.scala 1825:57] + node _T_480 = or(mdseac_en, _T_479) @[dec_tlu_ctl.scala 1825:35] + io.mdseac_locked_ns <= _T_480 @[dec_tlu_ctl.scala 1825:22] + node _T_481 = or(io.lsu_imprecise_error_store_any, io.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 1827:49] + node _T_482 = not(io.nmi_int_detected_f) @[dec_tlu_ctl.scala 1827:86] + node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 1827:84] + node _T_484 = not(io.mdseac_locked_f) @[dec_tlu_ctl.scala 1827:111] + node _T_485 = and(_T_483, _T_484) @[dec_tlu_ctl.scala 1827:109] + mdseac_en <= _T_485 @[dec_tlu_ctl.scala 1827:12] + node _T_486 = bits(mdseac_en, 0, 0) @[dec_tlu_ctl.scala 1829:64] inst rvclkhdr_11 of rvclkhdr_731 @[lib.scala 352:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset @@ -73595,54 +73595,54 @@ circuit quasar_wrapper : rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg mdseac : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] mdseac <= io.lsu_imprecise_error_addr_any @[lib.scala 358:16] - node _T_487 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1842:61] - node _T_488 = eq(_T_487, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1842:68] - node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_488) @[dec_tlu_ctl.scala 1842:39] - node _T_489 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1846:51] - node _T_490 = and(wr_mpmc_r, _T_489) @[dec_tlu_ctl.scala 1846:30] - node _T_491 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1846:57] - node _T_492 = and(_T_490, _T_491) @[dec_tlu_ctl.scala 1846:55] - node _T_493 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1846:89] - node _T_494 = and(_T_492, _T_493) @[dec_tlu_ctl.scala 1846:87] - io.fw_halt_req <= _T_494 @[dec_tlu_ctl.scala 1846:17] + node _T_487 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1838:61] + node _T_488 = eq(_T_487, UInt<12>("h07c6")) @[dec_tlu_ctl.scala 1838:68] + node wr_mpmc_r = and(io.dec_csr_wen_r_mod, _T_488) @[dec_tlu_ctl.scala 1838:39] + node _T_489 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 1842:51] + node _T_490 = and(wr_mpmc_r, _T_489) @[dec_tlu_ctl.scala 1842:30] + node _T_491 = not(io.internal_dbg_halt_mode_f2) @[dec_tlu_ctl.scala 1842:57] + node _T_492 = and(_T_490, _T_491) @[dec_tlu_ctl.scala 1842:55] + node _T_493 = not(io.ext_int_freeze_d1) @[dec_tlu_ctl.scala 1842:89] + node _T_494 = and(_T_492, _T_493) @[dec_tlu_ctl.scala 1842:87] + io.fw_halt_req <= _T_494 @[dec_tlu_ctl.scala 1842:17] wire fw_halted_ns : UInt<1> fw_halted_ns <= UInt<1>("h00") - reg fw_halted : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1848:48] - fw_halted <= fw_halted_ns @[dec_tlu_ctl.scala 1848:48] - node _T_495 = or(io.fw_halt_req, fw_halted) @[dec_tlu_ctl.scala 1849:34] - node _T_496 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1849:49] - node _T_497 = and(_T_495, _T_496) @[dec_tlu_ctl.scala 1849:47] - fw_halted_ns <= _T_497 @[dec_tlu_ctl.scala 1849:15] - node _T_498 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1850:29] - node _T_499 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1850:57] - node _T_500 = not(_T_499) @[dec_tlu_ctl.scala 1850:37] - node _T_501 = not(mpmc) @[dec_tlu_ctl.scala 1850:62] - node _T_502 = mux(_T_498, _T_500, _T_501) @[dec_tlu_ctl.scala 1850:18] - mpmc_b_ns <= _T_502 @[dec_tlu_ctl.scala 1850:12] - reg _T_503 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1852:44] - _T_503 <= mpmc_b_ns @[dec_tlu_ctl.scala 1852:44] - mpmc_b <= _T_503 @[dec_tlu_ctl.scala 1852:9] - node _T_504 = not(mpmc_b) @[dec_tlu_ctl.scala 1855:10] - mpmc <= _T_504 @[dec_tlu_ctl.scala 1855:7] - node _T_505 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1864:40] - node _T_506 = gt(_T_505, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1864:48] - node _T_507 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1864:92] - node csr_sat = mux(_T_506, UInt<5>("h01a"), _T_507) @[dec_tlu_ctl.scala 1864:19] - node _T_508 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1866:63] - node _T_509 = eq(_T_508, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1866:70] - node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_509) @[dec_tlu_ctl.scala 1866:41] + reg fw_halted : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1844:48] + fw_halted <= fw_halted_ns @[dec_tlu_ctl.scala 1844:48] + node _T_495 = or(io.fw_halt_req, fw_halted) @[dec_tlu_ctl.scala 1845:34] + node _T_496 = not(set_mie_pmu_fw_halt) @[dec_tlu_ctl.scala 1845:49] + node _T_497 = and(_T_495, _T_496) @[dec_tlu_ctl.scala 1845:47] + fw_halted_ns <= _T_497 @[dec_tlu_ctl.scala 1845:15] + node _T_498 = bits(wr_mpmc_r, 0, 0) @[dec_tlu_ctl.scala 1846:29] + node _T_499 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 1846:57] + node _T_500 = not(_T_499) @[dec_tlu_ctl.scala 1846:37] + node _T_501 = not(mpmc) @[dec_tlu_ctl.scala 1846:62] + node _T_502 = mux(_T_498, _T_500, _T_501) @[dec_tlu_ctl.scala 1846:18] + mpmc_b_ns <= _T_502 @[dec_tlu_ctl.scala 1846:12] + reg _T_503 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1848:44] + _T_503 <= mpmc_b_ns @[dec_tlu_ctl.scala 1848:44] + mpmc_b <= _T_503 @[dec_tlu_ctl.scala 1848:9] + node _T_504 = not(mpmc_b) @[dec_tlu_ctl.scala 1851:10] + mpmc <= _T_504 @[dec_tlu_ctl.scala 1851:7] + node _T_505 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1860:40] + node _T_506 = gt(_T_505, UInt<5>("h01a")) @[dec_tlu_ctl.scala 1860:48] + node _T_507 = bits(io.dec_csr_wrdata_r, 31, 27) @[dec_tlu_ctl.scala 1860:92] + node csr_sat = mux(_T_506, UInt<5>("h01a"), _T_507) @[dec_tlu_ctl.scala 1860:19] + node _T_508 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1862:63] + node _T_509 = eq(_T_508, UInt<12>("h07f0")) @[dec_tlu_ctl.scala 1862:70] + node wr_micect_r = and(io.dec_csr_wen_r_mod, _T_509) @[dec_tlu_ctl.scala 1862:41] node _T_510 = cat(UInt<26>("h00"), io.ic_perr_r_d1) @[Cat.scala 29:58] - node _T_511 = add(micect, _T_510) @[dec_tlu_ctl.scala 1867:23] - node _T_512 = tail(_T_511, 1) @[dec_tlu_ctl.scala 1867:23] - micect_inc <= _T_512 @[dec_tlu_ctl.scala 1867:13] - node _T_513 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1868:35] - node _T_514 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1868:75] + node _T_511 = add(micect, _T_510) @[dec_tlu_ctl.scala 1863:23] + node _T_512 = tail(_T_511, 1) @[dec_tlu_ctl.scala 1863:23] + micect_inc <= _T_512 @[dec_tlu_ctl.scala 1863:13] + node _T_513 = bits(wr_micect_r, 0, 0) @[dec_tlu_ctl.scala 1864:35] + node _T_514 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1864:75] node _T_515 = cat(csr_sat, _T_514) @[Cat.scala 29:58] - node _T_516 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1868:95] + node _T_516 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1864:95] node _T_517 = cat(_T_516, micect_inc) @[Cat.scala 29:58] - node micect_ns = mux(_T_513, _T_515, _T_517) @[dec_tlu_ctl.scala 1868:22] - node _T_518 = or(wr_micect_r, io.ic_perr_r_d1) @[dec_tlu_ctl.scala 1870:42] - node _T_519 = bits(_T_518, 0, 0) @[dec_tlu_ctl.scala 1870:61] + node micect_ns = mux(_T_513, _T_515, _T_517) @[dec_tlu_ctl.scala 1864:22] + node _T_518 = or(wr_micect_r, io.ic_perr_r_d1) @[dec_tlu_ctl.scala 1866:42] + node _T_519 = bits(_T_518, 0, 0) @[dec_tlu_ctl.scala 1866:61] inst rvclkhdr_12 of rvclkhdr_732 @[lib.scala 352:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset @@ -73651,32 +73651,32 @@ circuit quasar_wrapper : rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_520 : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_520 <= micect_ns @[lib.scala 358:16] - micect <= _T_520 @[dec_tlu_ctl.scala 1870:9] - node _T_521 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1872:48] - node _T_522 = dshl(UInt<32>("h0ffffffff"), _T_521) @[dec_tlu_ctl.scala 1872:39] - node _T_523 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1872:79] + micect <= _T_520 @[dec_tlu_ctl.scala 1866:9] + node _T_521 = bits(micect, 31, 27) @[dec_tlu_ctl.scala 1868:48] + node _T_522 = dshl(UInt<32>("h0ffffffff"), _T_521) @[dec_tlu_ctl.scala 1868:39] + node _T_523 = bits(micect, 26, 0) @[dec_tlu_ctl.scala 1868:79] node _T_524 = cat(UInt<5>("h00"), _T_523) @[Cat.scala 29:58] - node _T_525 = and(_T_522, _T_524) @[dec_tlu_ctl.scala 1872:57] - node _T_526 = orr(_T_525) @[dec_tlu_ctl.scala 1872:88] - mice_ce_req <= _T_526 @[dec_tlu_ctl.scala 1872:14] - node _T_527 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1881:69] - node _T_528 = eq(_T_527, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1881:76] - node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_528) @[dec_tlu_ctl.scala 1881:47] - node _T_529 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1882:26] - node _T_530 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1882:70] + node _T_525 = and(_T_522, _T_524) @[dec_tlu_ctl.scala 1868:57] + node _T_526 = orr(_T_525) @[dec_tlu_ctl.scala 1868:88] + mice_ce_req <= _T_526 @[dec_tlu_ctl.scala 1868:14] + node _T_527 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1877:69] + node _T_528 = eq(_T_527, UInt<12>("h07f1")) @[dec_tlu_ctl.scala 1877:76] + node wr_miccmect_r = and(io.dec_csr_wen_r_mod, _T_528) @[dec_tlu_ctl.scala 1877:47] + node _T_529 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1878:26] + node _T_530 = or(io.iccm_sbecc_r_d1, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1878:70] node _T_531 = cat(UInt<26>("h00"), _T_530) @[Cat.scala 29:58] - node _T_532 = add(_T_529, _T_531) @[dec_tlu_ctl.scala 1882:33] - node _T_533 = tail(_T_532, 1) @[dec_tlu_ctl.scala 1882:33] - miccmect_inc <= _T_533 @[dec_tlu_ctl.scala 1882:15] - node _T_534 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1883:45] - node _T_535 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1883:85] + node _T_532 = add(_T_529, _T_531) @[dec_tlu_ctl.scala 1878:33] + node _T_533 = tail(_T_532, 1) @[dec_tlu_ctl.scala 1878:33] + miccmect_inc <= _T_533 @[dec_tlu_ctl.scala 1878:15] + node _T_534 = bits(wr_miccmect_r, 0, 0) @[dec_tlu_ctl.scala 1879:45] + node _T_535 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1879:85] node _T_536 = cat(csr_sat, _T_535) @[Cat.scala 29:58] - node _T_537 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1883:107] + node _T_537 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1879:107] node _T_538 = cat(_T_537, miccmect_inc) @[Cat.scala 29:58] - node miccmect_ns = mux(_T_534, _T_536, _T_538) @[dec_tlu_ctl.scala 1883:30] - node _T_539 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 1885:48] - node _T_540 = or(_T_539, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1885:69] - node _T_541 = bits(_T_540, 0, 0) @[dec_tlu_ctl.scala 1885:93] + node miccmect_ns = mux(_T_534, _T_536, _T_538) @[dec_tlu_ctl.scala 1879:30] + node _T_539 = or(wr_miccmect_r, io.iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 1881:48] + node _T_540 = or(_T_539, io.iccm_dma_sb_error) @[dec_tlu_ctl.scala 1881:69] + node _T_541 = bits(_T_540, 0, 0) @[dec_tlu_ctl.scala 1881:93] inst rvclkhdr_13 of rvclkhdr_733 @[lib.scala 352:23] rvclkhdr_13.clock <= clock rvclkhdr_13.reset <= reset @@ -73685,30 +73685,30 @@ circuit quasar_wrapper : rvclkhdr_13.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_542 : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_542 <= miccmect_ns @[lib.scala 358:16] - miccmect <= _T_542 @[dec_tlu_ctl.scala 1885:11] - node _T_543 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1887:51] - node _T_544 = dshl(UInt<32>("h0ffffffff"), _T_543) @[dec_tlu_ctl.scala 1887:40] - node _T_545 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1887:84] + miccmect <= _T_542 @[dec_tlu_ctl.scala 1881:11] + node _T_543 = bits(miccmect, 31, 27) @[dec_tlu_ctl.scala 1883:51] + node _T_544 = dshl(UInt<32>("h0ffffffff"), _T_543) @[dec_tlu_ctl.scala 1883:40] + node _T_545 = bits(miccmect, 26, 0) @[dec_tlu_ctl.scala 1883:84] node _T_546 = cat(UInt<5>("h00"), _T_545) @[Cat.scala 29:58] - node _T_547 = and(_T_544, _T_546) @[dec_tlu_ctl.scala 1887:60] - node _T_548 = orr(_T_547) @[dec_tlu_ctl.scala 1887:93] - miccme_ce_req <= _T_548 @[dec_tlu_ctl.scala 1887:15] - node _T_549 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1896:69] - node _T_550 = eq(_T_549, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1896:76] - node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_550) @[dec_tlu_ctl.scala 1896:47] - node _T_551 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1897:26] + node _T_547 = and(_T_544, _T_546) @[dec_tlu_ctl.scala 1883:60] + node _T_548 = orr(_T_547) @[dec_tlu_ctl.scala 1883:93] + miccme_ce_req <= _T_548 @[dec_tlu_ctl.scala 1883:15] + node _T_549 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1892:69] + node _T_550 = eq(_T_549, UInt<12>("h07f2")) @[dec_tlu_ctl.scala 1892:76] + node wr_mdccmect_r = and(io.dec_csr_wen_r_mod, _T_550) @[dec_tlu_ctl.scala 1892:47] + node _T_551 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1893:26] node _T_552 = cat(UInt<26>("h00"), io.lsu_single_ecc_error_r_d1) @[Cat.scala 29:58] - node _T_553 = add(_T_551, _T_552) @[dec_tlu_ctl.scala 1897:33] - node _T_554 = tail(_T_553, 1) @[dec_tlu_ctl.scala 1897:33] - mdccmect_inc <= _T_554 @[dec_tlu_ctl.scala 1897:15] - node _T_555 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1898:45] - node _T_556 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1898:85] + node _T_553 = add(_T_551, _T_552) @[dec_tlu_ctl.scala 1893:33] + node _T_554 = tail(_T_553, 1) @[dec_tlu_ctl.scala 1893:33] + mdccmect_inc <= _T_554 @[dec_tlu_ctl.scala 1893:15] + node _T_555 = bits(wr_mdccmect_r, 0, 0) @[dec_tlu_ctl.scala 1894:45] + node _T_556 = bits(io.dec_csr_wrdata_r, 26, 0) @[dec_tlu_ctl.scala 1894:85] node _T_557 = cat(csr_sat, _T_556) @[Cat.scala 29:58] - node _T_558 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1898:107] + node _T_558 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1894:107] node _T_559 = cat(_T_558, mdccmect_inc) @[Cat.scala 29:58] - node mdccmect_ns = mux(_T_555, _T_557, _T_559) @[dec_tlu_ctl.scala 1898:30] - node _T_560 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1900:49] - node _T_561 = bits(_T_560, 0, 0) @[dec_tlu_ctl.scala 1900:81] + node mdccmect_ns = mux(_T_555, _T_557, _T_559) @[dec_tlu_ctl.scala 1894:30] + node _T_560 = or(wr_mdccmect_r, io.lsu_single_ecc_error_r_d1) @[dec_tlu_ctl.scala 1896:49] + node _T_561 = bits(_T_560, 0, 0) @[dec_tlu_ctl.scala 1896:81] inst rvclkhdr_14 of rvclkhdr_734 @[lib.scala 352:23] rvclkhdr_14.clock <= clock rvclkhdr_14.reset <= reset @@ -73717,67 +73717,67 @@ circuit quasar_wrapper : rvclkhdr_14.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_562 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_562 <= mdccmect_ns @[lib.scala 358:16] - mdccmect <= _T_562 @[dec_tlu_ctl.scala 1900:11] - node _T_563 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1902:52] - node _T_564 = dshl(UInt<32>("h0ffffffff"), _T_563) @[dec_tlu_ctl.scala 1902:41] - node _T_565 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1902:85] + mdccmect <= _T_562 @[dec_tlu_ctl.scala 1896:11] + node _T_563 = bits(mdccmect, 31, 27) @[dec_tlu_ctl.scala 1898:52] + node _T_564 = dshl(UInt<32>("h0ffffffff"), _T_563) @[dec_tlu_ctl.scala 1898:41] + node _T_565 = bits(mdccmect, 26, 0) @[dec_tlu_ctl.scala 1898:85] node _T_566 = cat(UInt<5>("h00"), _T_565) @[Cat.scala 29:58] - node _T_567 = and(_T_564, _T_566) @[dec_tlu_ctl.scala 1902:61] - node _T_568 = orr(_T_567) @[dec_tlu_ctl.scala 1902:94] - mdccme_ce_req <= _T_568 @[dec_tlu_ctl.scala 1902:16] - node _T_569 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1912:62] - node _T_570 = eq(_T_569, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1912:69] - node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_570) @[dec_tlu_ctl.scala 1912:40] - node _T_571 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1914:32] - node _T_572 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1914:59] - node mfdht_ns = mux(_T_571, _T_572, mfdht) @[dec_tlu_ctl.scala 1914:20] - reg _T_573 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1916:43] - _T_573 <= mfdht_ns @[dec_tlu_ctl.scala 1916:43] - mfdht <= _T_573 @[dec_tlu_ctl.scala 1916:8] - node _T_574 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1925:62] - node _T_575 = eq(_T_574, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1925:69] - node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_575) @[dec_tlu_ctl.scala 1925:40] - node _T_576 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1927:32] - node _T_577 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1927:60] - node _T_578 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1928:43] - node _T_579 = and(io.dbg_tlu_halted, _T_578) @[dec_tlu_ctl.scala 1928:41] - node _T_580 = bits(_T_579, 0, 0) @[dec_tlu_ctl.scala 1928:65] - node _T_581 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1928:78] - node _T_582 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1928:98] + node _T_567 = and(_T_564, _T_566) @[dec_tlu_ctl.scala 1898:61] + node _T_568 = orr(_T_567) @[dec_tlu_ctl.scala 1898:94] + mdccme_ce_req <= _T_568 @[dec_tlu_ctl.scala 1898:16] + node _T_569 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1908:62] + node _T_570 = eq(_T_569, UInt<12>("h07ce")) @[dec_tlu_ctl.scala 1908:69] + node wr_mfdht_r = and(io.dec_csr_wen_r_mod, _T_570) @[dec_tlu_ctl.scala 1908:40] + node _T_571 = bits(wr_mfdht_r, 0, 0) @[dec_tlu_ctl.scala 1910:32] + node _T_572 = bits(io.dec_csr_wrdata_r, 5, 0) @[dec_tlu_ctl.scala 1910:59] + node mfdht_ns = mux(_T_571, _T_572, mfdht) @[dec_tlu_ctl.scala 1910:20] + reg _T_573 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1912:43] + _T_573 <= mfdht_ns @[dec_tlu_ctl.scala 1912:43] + mfdht <= _T_573 @[dec_tlu_ctl.scala 1912:8] + node _T_574 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1921:62] + node _T_575 = eq(_T_574, UInt<12>("h07cf")) @[dec_tlu_ctl.scala 1921:69] + node wr_mfdhs_r = and(io.dec_csr_wen_r_mod, _T_575) @[dec_tlu_ctl.scala 1921:40] + node _T_576 = bits(wr_mfdhs_r, 0, 0) @[dec_tlu_ctl.scala 1923:32] + node _T_577 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 1923:60] + node _T_578 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1924:43] + node _T_579 = and(io.dbg_tlu_halted, _T_578) @[dec_tlu_ctl.scala 1924:41] + node _T_580 = bits(_T_579, 0, 0) @[dec_tlu_ctl.scala 1924:65] + node _T_581 = not(io.lsu_idle_any_f) @[dec_tlu_ctl.scala 1924:78] + node _T_582 = not(io.ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 1924:98] node _T_583 = cat(_T_581, _T_582) @[Cat.scala 29:58] - node _T_584 = mux(_T_580, _T_583, mfdhs) @[dec_tlu_ctl.scala 1928:21] - node mfdhs_ns = mux(_T_576, _T_577, _T_584) @[dec_tlu_ctl.scala 1927:20] - node _T_585 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1930:71] - node _T_586 = bits(_T_585, 0, 0) @[dec_tlu_ctl.scala 1930:92] + node _T_584 = mux(_T_580, _T_583, mfdhs) @[dec_tlu_ctl.scala 1924:21] + node mfdhs_ns = mux(_T_576, _T_577, _T_584) @[dec_tlu_ctl.scala 1923:20] + node _T_585 = or(wr_mfdhs_r, io.dbg_tlu_halted) @[dec_tlu_ctl.scala 1926:71] + node _T_586 = bits(_T_585, 0, 0) @[dec_tlu_ctl.scala 1926:92] reg _T_587 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_586 : @[Reg.scala 28:19] _T_587 <= mfdhs_ns @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mfdhs <= _T_587 @[dec_tlu_ctl.scala 1930:8] - node _T_588 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1932:47] - node _T_589 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1932:74] - node _T_590 = tail(_T_589, 1) @[dec_tlu_ctl.scala 1932:74] - node _T_591 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1933:48] - node _T_592 = mux(_T_591, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1933:27] - node force_halt_ctr = mux(_T_588, _T_590, _T_592) @[dec_tlu_ctl.scala 1932:26] - node _T_593 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1935:81] + mfdhs <= _T_587 @[dec_tlu_ctl.scala 1926:8] + node _T_588 = bits(io.debug_halt_req_f, 0, 0) @[dec_tlu_ctl.scala 1928:47] + node _T_589 = add(force_halt_ctr_f, UInt<32>("h01")) @[dec_tlu_ctl.scala 1928:74] + node _T_590 = tail(_T_589, 1) @[dec_tlu_ctl.scala 1928:74] + node _T_591 = bits(io.dbg_tlu_halted_f, 0, 0) @[dec_tlu_ctl.scala 1929:48] + node _T_592 = mux(_T_591, UInt<32>("h00"), force_halt_ctr_f) @[dec_tlu_ctl.scala 1929:27] + node force_halt_ctr = mux(_T_588, _T_590, _T_592) @[dec_tlu_ctl.scala 1928:26] + node _T_593 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1931:81] reg _T_594 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_593 : @[Reg.scala 28:19] _T_594 <= force_halt_ctr @[Reg.scala 28:23] skip @[Reg.scala 28:19] - force_halt_ctr_f <= _T_594 @[dec_tlu_ctl.scala 1935:19] - node _T_595 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1937:24] - node _T_596 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1937:79] - node _T_597 = dshl(UInt<32>("h0ffffffff"), _T_596) @[dec_tlu_ctl.scala 1937:71] - node _T_598 = and(force_halt_ctr_f, _T_597) @[dec_tlu_ctl.scala 1937:48] - node _T_599 = orr(_T_598) @[dec_tlu_ctl.scala 1937:87] - node _T_600 = and(_T_595, _T_599) @[dec_tlu_ctl.scala 1937:28] - io.force_halt <= _T_600 @[dec_tlu_ctl.scala 1937:16] - node _T_601 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1945:62] - node _T_602 = eq(_T_601, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1945:69] - node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_602) @[dec_tlu_ctl.scala 1945:40] - node _T_603 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1947:40] - node _T_604 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1947:59] + force_halt_ctr_f <= _T_594 @[dec_tlu_ctl.scala 1931:19] + node _T_595 = bits(mfdht, 0, 0) @[dec_tlu_ctl.scala 1933:24] + node _T_596 = bits(mfdht, 5, 1) @[dec_tlu_ctl.scala 1933:79] + node _T_597 = dshl(UInt<32>("h0ffffffff"), _T_596) @[dec_tlu_ctl.scala 1933:71] + node _T_598 = and(force_halt_ctr_f, _T_597) @[dec_tlu_ctl.scala 1933:48] + node _T_599 = orr(_T_598) @[dec_tlu_ctl.scala 1933:87] + node _T_600 = and(_T_595, _T_599) @[dec_tlu_ctl.scala 1933:28] + io.force_halt <= _T_600 @[dec_tlu_ctl.scala 1933:16] + node _T_601 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1941:62] + node _T_602 = eq(_T_601, UInt<12>("h0bc8")) @[dec_tlu_ctl.scala 1941:69] + node wr_meivt_r = and(io.dec_csr_wen_r_mod, _T_602) @[dec_tlu_ctl.scala 1941:40] + node _T_603 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 1943:40] + node _T_604 = bits(wr_meivt_r, 0, 0) @[dec_tlu_ctl.scala 1943:59] inst rvclkhdr_15 of rvclkhdr_735 @[lib.scala 352:23] rvclkhdr_15.clock <= clock rvclkhdr_15.reset <= reset @@ -73786,7 +73786,7 @@ circuit quasar_wrapper : rvclkhdr_15.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg meivt : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] meivt <= _T_603 @[lib.scala 358:16] - node _T_605 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1959:49] + node _T_605 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1955:49] inst rvclkhdr_16 of rvclkhdr_736 @[lib.scala 352:23] rvclkhdr_16.clock <= clock rvclkhdr_16.reset <= reset @@ -73796,62 +73796,62 @@ circuit quasar_wrapper : reg meihap : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] meihap <= io.pic_claimid @[lib.scala 358:16] node _T_606 = cat(meivt, meihap) @[Cat.scala 29:58] - io.dec_tlu_meihap <= _T_606 @[dec_tlu_ctl.scala 1960:20] - node _T_607 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1969:65] - node _T_608 = eq(_T_607, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 1969:72] - node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_608) @[dec_tlu_ctl.scala 1969:43] - node _T_609 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 1970:38] - node _T_610 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1970:65] - node meicurpl_ns = mux(_T_609, _T_610, meicurpl) @[dec_tlu_ctl.scala 1970:23] - reg _T_611 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1972:46] - _T_611 <= meicurpl_ns @[dec_tlu_ctl.scala 1972:46] - meicurpl <= _T_611 @[dec_tlu_ctl.scala 1972:11] - io.dec_tlu_meicurpl <= meicurpl @[dec_tlu_ctl.scala 1974:22] - node _T_612 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1984:66] - node _T_613 = eq(_T_612, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 1984:73] - node _T_614 = and(io.dec_csr_wen_r_mod, _T_613) @[dec_tlu_ctl.scala 1984:44] - node wr_meicidpl_r = or(_T_614, io.take_ext_int_start) @[dec_tlu_ctl.scala 1984:88] - node _T_615 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1986:37] - node _T_616 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 1987:38] - node _T_617 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1987:65] - node _T_618 = mux(_T_616, _T_617, meicidpl) @[dec_tlu_ctl.scala 1987:23] - node meicidpl_ns = mux(_T_615, io.pic_pl, _T_618) @[dec_tlu_ctl.scala 1986:23] - reg _T_619 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1989:44] - _T_619 <= meicidpl_ns @[dec_tlu_ctl.scala 1989:44] - meicidpl <= _T_619 @[dec_tlu_ctl.scala 1989:11] - node _T_620 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1996:62] - node _T_621 = eq(_T_620, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 1996:69] - node _T_622 = and(io.dec_csr_wen_r_mod, _T_621) @[dec_tlu_ctl.scala 1996:40] - node _T_623 = or(_T_622, io.take_ext_int_start) @[dec_tlu_ctl.scala 1996:83] - wr_meicpct_r <= _T_623 @[dec_tlu_ctl.scala 1996:15] - node _T_624 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2005:62] - node _T_625 = eq(_T_624, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 2005:69] - node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_625) @[dec_tlu_ctl.scala 2005:40] - node _T_626 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 2006:32] - node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2006:59] - node meipt_ns = mux(_T_626, _T_627, meipt) @[dec_tlu_ctl.scala 2006:20] - reg _T_628 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2008:43] - _T_628 <= meipt_ns @[dec_tlu_ctl.scala 2008:43] - meipt <= _T_628 @[dec_tlu_ctl.scala 2008:8] - io.dec_tlu_meipt <= meipt @[dec_tlu_ctl.scala 2010:19] - node _T_629 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2036:89] - node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_629) @[dec_tlu_ctl.scala 2036:66] - node _T_630 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2039:31] - node _T_631 = and(io.dcsr_single_step_done_f, _T_630) @[dec_tlu_ctl.scala 2039:29] - node _T_632 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2039:63] - node _T_633 = and(_T_631, _T_632) @[dec_tlu_ctl.scala 2039:61] - node _T_634 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2039:98] - node _T_635 = and(_T_633, _T_634) @[dec_tlu_ctl.scala 2039:96] - node _T_636 = bits(_T_635, 0, 0) @[dec_tlu_ctl.scala 2039:118] - node _T_637 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2040:48] - node _T_638 = and(io.debug_halt_req, _T_637) @[dec_tlu_ctl.scala 2040:46] - node _T_639 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2040:80] - node _T_640 = and(_T_638, _T_639) @[dec_tlu_ctl.scala 2040:78] - node _T_641 = bits(_T_640, 0, 0) @[dec_tlu_ctl.scala 2040:114] - node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2041:77] - node _T_643 = and(io.ebreak_to_debug_mode_r_d1, _T_642) @[dec_tlu_ctl.scala 2041:75] - node _T_644 = bits(_T_643, 0, 0) @[dec_tlu_ctl.scala 2041:111] - node _T_645 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2042:108] + io.dec_tlu_meihap <= _T_606 @[dec_tlu_ctl.scala 1956:20] + node _T_607 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1965:65] + node _T_608 = eq(_T_607, UInt<12>("h0bcc")) @[dec_tlu_ctl.scala 1965:72] + node wr_meicurpl_r = and(io.dec_csr_wen_r_mod, _T_608) @[dec_tlu_ctl.scala 1965:43] + node _T_609 = bits(wr_meicurpl_r, 0, 0) @[dec_tlu_ctl.scala 1966:38] + node _T_610 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1966:65] + node meicurpl_ns = mux(_T_609, _T_610, meicurpl) @[dec_tlu_ctl.scala 1966:23] + reg _T_611 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1968:46] + _T_611 <= meicurpl_ns @[dec_tlu_ctl.scala 1968:46] + meicurpl <= _T_611 @[dec_tlu_ctl.scala 1968:11] + io.dec_tlu_meicurpl <= meicurpl @[dec_tlu_ctl.scala 1970:22] + node _T_612 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1980:66] + node _T_613 = eq(_T_612, UInt<12>("h0bcb")) @[dec_tlu_ctl.scala 1980:73] + node _T_614 = and(io.dec_csr_wen_r_mod, _T_613) @[dec_tlu_ctl.scala 1980:44] + node wr_meicidpl_r = or(_T_614, io.take_ext_int_start) @[dec_tlu_ctl.scala 1980:88] + node _T_615 = bits(wr_meicpct_r, 0, 0) @[dec_tlu_ctl.scala 1982:37] + node _T_616 = bits(wr_meicidpl_r, 0, 0) @[dec_tlu_ctl.scala 1983:38] + node _T_617 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 1983:65] + node _T_618 = mux(_T_616, _T_617, meicidpl) @[dec_tlu_ctl.scala 1983:23] + node meicidpl_ns = mux(_T_615, io.pic_pl, _T_618) @[dec_tlu_ctl.scala 1982:23] + reg _T_619 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 1985:44] + _T_619 <= meicidpl_ns @[dec_tlu_ctl.scala 1985:44] + meicidpl <= _T_619 @[dec_tlu_ctl.scala 1985:11] + node _T_620 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 1992:62] + node _T_621 = eq(_T_620, UInt<12>("h0bca")) @[dec_tlu_ctl.scala 1992:69] + node _T_622 = and(io.dec_csr_wen_r_mod, _T_621) @[dec_tlu_ctl.scala 1992:40] + node _T_623 = or(_T_622, io.take_ext_int_start) @[dec_tlu_ctl.scala 1992:83] + wr_meicpct_r <= _T_623 @[dec_tlu_ctl.scala 1992:15] + node _T_624 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2001:62] + node _T_625 = eq(_T_624, UInt<12>("h0bc9")) @[dec_tlu_ctl.scala 2001:69] + node wr_meipt_r = and(io.dec_csr_wen_r_mod, _T_625) @[dec_tlu_ctl.scala 2001:40] + node _T_626 = bits(wr_meipt_r, 0, 0) @[dec_tlu_ctl.scala 2002:32] + node _T_627 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2002:59] + node meipt_ns = mux(_T_626, _T_627, meipt) @[dec_tlu_ctl.scala 2002:20] + reg _T_628 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2004:43] + _T_628 <= meipt_ns @[dec_tlu_ctl.scala 2004:43] + meipt <= _T_628 @[dec_tlu_ctl.scala 2004:8] + io.dec_tlu_meipt <= meipt @[dec_tlu_ctl.scala 2006:19] + node _T_629 = and(io.trigger_hit_r_d1, io.dcsr_single_step_done_f) @[dec_tlu_ctl.scala 2032:89] + node trigger_hit_for_dscr_cause_r_d1 = or(io.trigger_hit_dmode_r_d1, _T_629) @[dec_tlu_ctl.scala 2032:66] + node _T_630 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2035:31] + node _T_631 = and(io.dcsr_single_step_done_f, _T_630) @[dec_tlu_ctl.scala 2035:29] + node _T_632 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2035:63] + node _T_633 = and(_T_631, _T_632) @[dec_tlu_ctl.scala 2035:61] + node _T_634 = not(io.debug_halt_req) @[dec_tlu_ctl.scala 2035:98] + node _T_635 = and(_T_633, _T_634) @[dec_tlu_ctl.scala 2035:96] + node _T_636 = bits(_T_635, 0, 0) @[dec_tlu_ctl.scala 2035:118] + node _T_637 = not(io.ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 2036:48] + node _T_638 = and(io.debug_halt_req, _T_637) @[dec_tlu_ctl.scala 2036:46] + node _T_639 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2036:80] + node _T_640 = and(_T_638, _T_639) @[dec_tlu_ctl.scala 2036:78] + node _T_641 = bits(_T_640, 0, 0) @[dec_tlu_ctl.scala 2036:114] + node _T_642 = not(trigger_hit_for_dscr_cause_r_d1) @[dec_tlu_ctl.scala 2037:77] + node _T_643 = and(io.ebreak_to_debug_mode_r_d1, _T_642) @[dec_tlu_ctl.scala 2037:75] + node _T_644 = bits(_T_643, 0, 0) @[dec_tlu_ctl.scala 2037:111] + node _T_645 = bits(trigger_hit_for_dscr_cause_r_d1, 0, 0) @[dec_tlu_ctl.scala 2038:108] node _T_646 = mux(_T_636, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_647 = mux(_T_641, UInt<3>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_648 = mux(_T_644, UInt<3>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -73861,30 +73861,30 @@ circuit quasar_wrapper : node _T_652 = or(_T_651, _T_649) @[Mux.scala 27:72] wire dcsr_cause : UInt<3> @[Mux.scala 27:72] dcsr_cause <= _T_652 @[Mux.scala 27:72] - node _T_653 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2044:46] - node _T_654 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2044:91] - node _T_655 = eq(_T_654, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2044:98] - node wr_dcsr_r = and(_T_653, _T_655) @[dec_tlu_ctl.scala 2044:69] - node _T_656 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2050:69] - node _T_657 = eq(_T_656, UInt<3>("h03")) @[dec_tlu_ctl.scala 2050:75] - node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_657) @[dec_tlu_ctl.scala 2050:59] - node _T_658 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2051:59] - node _T_659 = or(_T_658, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2051:78] - node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_659) @[dec_tlu_ctl.scala 2051:56] - node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 2053:48] - node _T_660 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2054:44] - node _T_661 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2054:64] - node _T_662 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2054:91] + node _T_653 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2040:46] + node _T_654 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2040:91] + node _T_655 = eq(_T_654, UInt<12>("h07b0")) @[dec_tlu_ctl.scala 2040:98] + node wr_dcsr_r = and(_T_653, _T_655) @[dec_tlu_ctl.scala 2040:69] + node _T_656 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2046:69] + node _T_657 = eq(_T_656, UInt<3>("h03")) @[dec_tlu_ctl.scala 2046:75] + node dcsr_cause_upgradeable = and(io.internal_dbg_halt_mode_f, _T_657) @[dec_tlu_ctl.scala 2046:59] + node _T_658 = not(io.dbg_tlu_halted) @[dec_tlu_ctl.scala 2047:59] + node _T_659 = or(_T_658, dcsr_cause_upgradeable) @[dec_tlu_ctl.scala 2047:78] + node enter_debug_halt_req_le = and(io.enter_debug_halt_req, _T_659) @[dec_tlu_ctl.scala 2047:56] + node nmi_in_debug_mode = and(io.nmi_int_detected_f, io.internal_dbg_halt_mode_f) @[dec_tlu_ctl.scala 2049:48] + node _T_660 = bits(enter_debug_halt_req_le, 0, 0) @[dec_tlu_ctl.scala 2050:44] + node _T_661 = bits(io.dcsr, 15, 9) @[dec_tlu_ctl.scala 2050:64] + node _T_662 = bits(io.dcsr, 5, 2) @[dec_tlu_ctl.scala 2050:91] node _T_663 = cat(_T_662, UInt<2>("h03")) @[Cat.scala 29:58] node _T_664 = cat(_T_661, dcsr_cause) @[Cat.scala 29:58] node _T_665 = cat(_T_664, _T_663) @[Cat.scala 29:58] - node _T_666 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2055:18] - node _T_667 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2055:49] - node _T_668 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2055:84] - node _T_669 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2055:110] - node _T_670 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2055:154] - node _T_671 = or(nmi_in_debug_mode, _T_670) @[dec_tlu_ctl.scala 2055:145] - node _T_672 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2055:178] + node _T_666 = bits(wr_dcsr_r, 0, 0) @[dec_tlu_ctl.scala 2051:18] + node _T_667 = bits(io.dec_csr_wrdata_r, 15, 15) @[dec_tlu_ctl.scala 2051:49] + node _T_668 = bits(io.dec_csr_wrdata_r, 11, 10) @[dec_tlu_ctl.scala 2051:84] + node _T_669 = bits(io.dcsr, 8, 6) @[dec_tlu_ctl.scala 2051:110] + node _T_670 = bits(io.dcsr, 3, 3) @[dec_tlu_ctl.scala 2051:154] + node _T_671 = or(nmi_in_debug_mode, _T_670) @[dec_tlu_ctl.scala 2051:145] + node _T_672 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2051:178] node _T_673 = cat(_T_672, UInt<2>("h03")) @[Cat.scala 29:58] node _T_674 = cat(UInt<2>("h00"), _T_671) @[Cat.scala 29:58] node _T_675 = cat(_T_674, _T_673) @[Cat.scala 29:58] @@ -73893,17 +73893,17 @@ circuit quasar_wrapper : node _T_678 = cat(_T_677, _T_668) @[Cat.scala 29:58] node _T_679 = cat(_T_678, _T_676) @[Cat.scala 29:58] node _T_680 = cat(_T_679, _T_675) @[Cat.scala 29:58] - node _T_681 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2055:211] - node _T_682 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2055:245] + node _T_681 = bits(io.dcsr, 15, 4) @[dec_tlu_ctl.scala 2051:211] + node _T_682 = bits(io.dcsr, 2, 2) @[dec_tlu_ctl.scala 2051:245] node _T_683 = cat(_T_682, UInt<2>("h03")) @[Cat.scala 29:58] node _T_684 = cat(_T_681, nmi_in_debug_mode) @[Cat.scala 29:58] node _T_685 = cat(_T_684, _T_683) @[Cat.scala 29:58] - node _T_686 = mux(_T_666, _T_680, _T_685) @[dec_tlu_ctl.scala 2055:7] - node dcsr_ns = mux(_T_660, _T_665, _T_686) @[dec_tlu_ctl.scala 2054:19] - node _T_687 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2057:54] - node _T_688 = or(_T_687, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2057:66] - node _T_689 = or(_T_688, io.take_nmi) @[dec_tlu_ctl.scala 2057:94] - node _T_690 = bits(_T_689, 0, 0) @[dec_tlu_ctl.scala 2057:109] + node _T_686 = mux(_T_666, _T_680, _T_685) @[dec_tlu_ctl.scala 2051:7] + node dcsr_ns = mux(_T_660, _T_665, _T_686) @[dec_tlu_ctl.scala 2050:19] + node _T_687 = or(enter_debug_halt_req_le, wr_dcsr_r) @[dec_tlu_ctl.scala 2053:54] + node _T_688 = or(_T_687, io.internal_dbg_halt_mode) @[dec_tlu_ctl.scala 2053:66] + node _T_689 = or(_T_688, io.take_nmi) @[dec_tlu_ctl.scala 2053:94] + node _T_690 = bits(_T_689, 0, 0) @[dec_tlu_ctl.scala 2053:109] inst rvclkhdr_17 of rvclkhdr_737 @[lib.scala 352:23] rvclkhdr_17.clock <= clock rvclkhdr_17.reset <= reset @@ -73912,25 +73912,25 @@ circuit quasar_wrapper : rvclkhdr_17.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_691 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_691 <= dcsr_ns @[lib.scala 358:16] - io.dcsr <= _T_691 @[dec_tlu_ctl.scala 2057:10] - node _T_692 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2065:45] - node _T_693 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2065:90] - node _T_694 = eq(_T_693, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2065:97] - node wr_dpc_r = and(_T_692, _T_694) @[dec_tlu_ctl.scala 2065:68] - node _T_695 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2066:44] - node _T_696 = and(io.dbg_tlu_halted, _T_695) @[dec_tlu_ctl.scala 2066:42] - node _T_697 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2066:67] - node dpc_capture_npc = and(_T_696, _T_697) @[dec_tlu_ctl.scala 2066:65] - node _T_698 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2070:21] - node _T_699 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2070:39] - node _T_700 = and(_T_698, _T_699) @[dec_tlu_ctl.scala 2070:37] - node _T_701 = and(_T_700, wr_dpc_r) @[dec_tlu_ctl.scala 2070:56] - node _T_702 = bits(_T_701, 0, 0) @[dec_tlu_ctl.scala 2070:68] - node _T_703 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2070:97] - node _T_704 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2071:68] - node _T_705 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2072:33] - node _T_706 = and(_T_705, dpc_capture_npc) @[dec_tlu_ctl.scala 2072:49] - node _T_707 = bits(_T_706, 0, 0) @[dec_tlu_ctl.scala 2072:68] + io.dcsr <= _T_691 @[dec_tlu_ctl.scala 2053:10] + node _T_692 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2061:45] + node _T_693 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2061:90] + node _T_694 = eq(_T_693, UInt<12>("h07b1")) @[dec_tlu_ctl.scala 2061:97] + node wr_dpc_r = and(_T_692, _T_694) @[dec_tlu_ctl.scala 2061:68] + node _T_695 = not(io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2062:44] + node _T_696 = and(io.dbg_tlu_halted, _T_695) @[dec_tlu_ctl.scala 2062:42] + node _T_697 = not(io.request_debug_mode_done) @[dec_tlu_ctl.scala 2062:67] + node dpc_capture_npc = and(_T_696, _T_697) @[dec_tlu_ctl.scala 2062:65] + node _T_698 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2066:21] + node _T_699 = not(dpc_capture_npc) @[dec_tlu_ctl.scala 2066:39] + node _T_700 = and(_T_698, _T_699) @[dec_tlu_ctl.scala 2066:37] + node _T_701 = and(_T_700, wr_dpc_r) @[dec_tlu_ctl.scala 2066:56] + node _T_702 = bits(_T_701, 0, 0) @[dec_tlu_ctl.scala 2066:68] + node _T_703 = bits(io.dec_csr_wrdata_r, 31, 1) @[dec_tlu_ctl.scala 2066:97] + node _T_704 = bits(io.request_debug_mode_r, 0, 0) @[dec_tlu_ctl.scala 2067:68] + node _T_705 = not(io.request_debug_mode_r) @[dec_tlu_ctl.scala 2068:33] + node _T_706 = and(_T_705, dpc_capture_npc) @[dec_tlu_ctl.scala 2068:49] + node _T_707 = bits(_T_706, 0, 0) @[dec_tlu_ctl.scala 2068:68] node _T_708 = mux(_T_702, _T_703, UInt<1>("h00")) @[Mux.scala 27:72] node _T_709 = mux(_T_704, pc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_710 = mux(_T_707, io.npc_r, UInt<1>("h00")) @[Mux.scala 27:72] @@ -73938,9 +73938,9 @@ circuit quasar_wrapper : node _T_712 = or(_T_711, _T_710) @[Mux.scala 27:72] wire dpc_ns : UInt<31> @[Mux.scala 27:72] dpc_ns <= _T_712 @[Mux.scala 27:72] - node _T_713 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2074:36] - node _T_714 = or(_T_713, dpc_capture_npc) @[dec_tlu_ctl.scala 2074:53] - node _T_715 = bits(_T_714, 0, 0) @[dec_tlu_ctl.scala 2074:72] + node _T_713 = or(wr_dpc_r, io.request_debug_mode_r) @[dec_tlu_ctl.scala 2070:36] + node _T_714 = or(_T_713, dpc_capture_npc) @[dec_tlu_ctl.scala 2070:53] + node _T_715 = bits(_T_714, 0, 0) @[dec_tlu_ctl.scala 2070:72] inst rvclkhdr_18 of rvclkhdr_738 @[lib.scala 352:23] rvclkhdr_18.clock <= clock rvclkhdr_18.reset <= reset @@ -73949,17 +73949,17 @@ circuit quasar_wrapper : rvclkhdr_18.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_716 : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_716 <= dpc_ns @[lib.scala 358:16] - io.dpc <= _T_716 @[dec_tlu_ctl.scala 2074:9] - node _T_717 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2088:43] - node _T_718 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2088:68] - node _T_719 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2088:96] + io.dpc <= _T_716 @[dec_tlu_ctl.scala 2070:9] + node _T_717 = bits(io.dec_csr_wrdata_r, 24, 24) @[dec_tlu_ctl.scala 2084:43] + node _T_718 = bits(io.dec_csr_wrdata_r, 21, 20) @[dec_tlu_ctl.scala 2084:68] + node _T_719 = bits(io.dec_csr_wrdata_r, 16, 3) @[dec_tlu_ctl.scala 2084:96] node _T_720 = cat(_T_717, _T_718) @[Cat.scala 29:58] node dicawics_ns = cat(_T_720, _T_719) @[Cat.scala 29:58] - node _T_721 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2089:50] - node _T_722 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2089:95] - node _T_723 = eq(_T_722, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2089:102] - node wr_dicawics_r = and(_T_721, _T_723) @[dec_tlu_ctl.scala 2089:73] - node _T_724 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2091:50] + node _T_721 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2085:50] + node _T_722 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2085:95] + node _T_723 = eq(_T_722, UInt<12>("h07c8")) @[dec_tlu_ctl.scala 2085:102] + node wr_dicawics_r = and(_T_721, _T_723) @[dec_tlu_ctl.scala 2085:73] + node _T_724 = bits(wr_dicawics_r, 0, 0) @[dec_tlu_ctl.scala 2087:50] inst rvclkhdr_19 of rvclkhdr_739 @[lib.scala 352:23] rvclkhdr_19.clock <= clock rvclkhdr_19.reset <= reset @@ -73968,14 +73968,14 @@ circuit quasar_wrapper : rvclkhdr_19.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg dicawics : UInt, rvclkhdr_19.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] dicawics <= dicawics_ns @[lib.scala 358:16] - node _T_725 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2107:48] - node _T_726 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2107:93] - node _T_727 = eq(_T_726, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2107:100] - node wr_dicad0_r = and(_T_725, _T_727) @[dec_tlu_ctl.scala 2107:71] - node _T_728 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2108:34] - node dicad0_ns = mux(_T_728, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[dec_tlu_ctl.scala 2108:21] - node _T_729 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2110:46] - node _T_730 = bits(_T_729, 0, 0) @[dec_tlu_ctl.scala 2110:79] + node _T_725 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2103:48] + node _T_726 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2103:93] + node _T_727 = eq(_T_726, UInt<12>("h07c9")) @[dec_tlu_ctl.scala 2103:100] + node wr_dicad0_r = and(_T_725, _T_727) @[dec_tlu_ctl.scala 2103:71] + node _T_728 = bits(wr_dicad0_r, 0, 0) @[dec_tlu_ctl.scala 2104:34] + node dicad0_ns = mux(_T_728, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) @[dec_tlu_ctl.scala 2104:21] + node _T_729 = or(wr_dicad0_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2106:46] + node _T_730 = bits(_T_729, 0, 0) @[dec_tlu_ctl.scala 2106:79] inst rvclkhdr_20 of rvclkhdr_740 @[lib.scala 352:23] rvclkhdr_20.clock <= clock rvclkhdr_20.reset <= reset @@ -73984,15 +73984,15 @@ circuit quasar_wrapper : rvclkhdr_20.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg dicad0 : UInt, rvclkhdr_20.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] dicad0 <= dicad0_ns @[lib.scala 358:16] - node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2120:49] - node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2120:94] - node _T_733 = eq(_T_732, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2120:101] - node wr_dicad0h_r = and(_T_731, _T_733) @[dec_tlu_ctl.scala 2120:72] - node _T_734 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2122:36] - node _T_735 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2122:88] - node dicad0h_ns = mux(_T_734, io.dec_csr_wrdata_r, _T_735) @[dec_tlu_ctl.scala 2122:22] - node _T_736 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2124:48] - node _T_737 = bits(_T_736, 0, 0) @[dec_tlu_ctl.scala 2124:81] + node _T_731 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2116:49] + node _T_732 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2116:94] + node _T_733 = eq(_T_732, UInt<12>("h07cc")) @[dec_tlu_ctl.scala 2116:101] + node wr_dicad0h_r = and(_T_731, _T_733) @[dec_tlu_ctl.scala 2116:72] + node _T_734 = bits(wr_dicad0h_r, 0, 0) @[dec_tlu_ctl.scala 2118:36] + node _T_735 = bits(io.ifu_ic_debug_rd_data, 63, 32) @[dec_tlu_ctl.scala 2118:88] + node dicad0h_ns = mux(_T_734, io.dec_csr_wrdata_r, _T_735) @[dec_tlu_ctl.scala 2118:22] + node _T_736 = or(wr_dicad0h_r, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2120:48] + node _T_737 = bits(_T_736, 0, 0) @[dec_tlu_ctl.scala 2120:81] inst rvclkhdr_21 of rvclkhdr_741 @[lib.scala 352:23] rvclkhdr_21.clock <= clock rvclkhdr_21.reset <= reset @@ -74003,75 +74003,75 @@ circuit quasar_wrapper : dicad0h <= dicad0h_ns @[lib.scala 358:16] wire _T_738 : UInt<4> _T_738 <= UInt<1>("h00") - node _T_739 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2147:48] - node _T_740 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2147:93] - node _T_741 = eq(_T_740, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2147:100] - node _T_742 = and(_T_739, _T_741) @[dec_tlu_ctl.scala 2147:71] - node _T_743 = bits(_T_742, 0, 0) @[dec_tlu_ctl.scala 2149:34] - node _T_744 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2149:61] - node _T_745 = bits(io.ifu_ic_debug_rd_data, 67, 64) @[dec_tlu_ctl.scala 2149:91] - node _T_746 = mux(_T_743, _T_744, _T_745) @[dec_tlu_ctl.scala 2149:21] - node _T_747 = or(_T_742, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2151:77] - node _T_748 = bits(_T_747, 0, 0) @[dec_tlu_ctl.scala 2151:110] + node _T_739 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2143:48] + node _T_740 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2143:93] + node _T_741 = eq(_T_740, UInt<12>("h07ca")) @[dec_tlu_ctl.scala 2143:100] + node _T_742 = and(_T_739, _T_741) @[dec_tlu_ctl.scala 2143:71] + node _T_743 = bits(_T_742, 0, 0) @[dec_tlu_ctl.scala 2145:34] + node _T_744 = bits(io.dec_csr_wrdata_r, 3, 0) @[dec_tlu_ctl.scala 2145:61] + node _T_745 = bits(io.ifu_ic_debug_rd_data, 67, 64) @[dec_tlu_ctl.scala 2145:91] + node _T_746 = mux(_T_743, _T_744, _T_745) @[dec_tlu_ctl.scala 2145:21] + node _T_747 = or(_T_742, io.ifu_ic_debug_rd_data_valid) @[dec_tlu_ctl.scala 2147:77] + node _T_748 = bits(_T_747, 0, 0) @[dec_tlu_ctl.scala 2147:110] reg _T_749 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_748 : @[Reg.scala 28:19] _T_749 <= _T_746 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - _T_738 <= _T_749 @[dec_tlu_ctl.scala 2151:13] + _T_738 <= _T_749 @[dec_tlu_ctl.scala 2147:13] node _T_750 = cat(UInt<28>("h00"), _T_738) @[Cat.scala 29:58] - dicad1 <= _T_750 @[dec_tlu_ctl.scala 2152:9] - node _T_751 = bits(dicad1, 3, 0) @[dec_tlu_ctl.scala 2160:69] - node _T_752 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2160:83] - node _T_753 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2160:97] + dicad1 <= _T_750 @[dec_tlu_ctl.scala 2148:9] + node _T_751 = bits(dicad1, 3, 0) @[dec_tlu_ctl.scala 2156:69] + node _T_752 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2156:83] + node _T_753 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2156:97] node _T_754 = cat(_T_752, _T_753) @[Cat.scala 29:58] node _T_755 = cat(UInt<2>("h00"), _T_751) @[Cat.scala 29:58] node _T_756 = cat(_T_755, _T_754) @[Cat.scala 29:58] - io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_756 @[dec_tlu_ctl.scala 2160:47] - io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2162:41] - node _T_757 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2164:52] - node _T_758 = and(_T_757, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2164:75] - node _T_759 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2164:98] - node _T_760 = and(_T_758, _T_759) @[dec_tlu_ctl.scala 2164:96] - node _T_761 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2164:142] - node _T_762 = eq(_T_761, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2164:149] - node icache_rd_valid = and(_T_760, _T_762) @[dec_tlu_ctl.scala 2164:120] - node _T_763 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2165:52] - node _T_764 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2165:97] - node _T_765 = eq(_T_764, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2165:104] - node icache_wr_valid = and(_T_763, _T_765) @[dec_tlu_ctl.scala 2165:75] - reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2167:58] - icache_rd_valid_f <= icache_rd_valid @[dec_tlu_ctl.scala 2167:58] - reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2168:58] - icache_wr_valid_f <= icache_wr_valid @[dec_tlu_ctl.scala 2168:58] - io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[dec_tlu_ctl.scala 2170:41] - io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[dec_tlu_ctl.scala 2171:41] - node _T_766 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2179:62] - node _T_767 = eq(_T_766, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2179:69] - node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_767) @[dec_tlu_ctl.scala 2179:40] - node _T_768 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2180:32] - node _T_769 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2180:59] - node mtsel_ns = mux(_T_768, _T_769, mtsel) @[dec_tlu_ctl.scala 2180:20] - reg _T_770 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2182:43] - _T_770 <= mtsel_ns @[dec_tlu_ctl.scala 2182:43] - mtsel <= _T_770 @[dec_tlu_ctl.scala 2182:8] - node _T_771 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2217:38] - node _T_772 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2217:64] - node _T_773 = not(_T_772) @[dec_tlu_ctl.scala 2217:44] - node tdata_load = and(_T_771, _T_773) @[dec_tlu_ctl.scala 2217:42] - node _T_774 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2219:40] - node _T_775 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2219:66] - node _T_776 = not(_T_775) @[dec_tlu_ctl.scala 2219:46] - node tdata_opcode = and(_T_774, _T_776) @[dec_tlu_ctl.scala 2219:44] - node _T_777 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2221:41] - node _T_778 = and(_T_777, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2221:46] - node _T_779 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2221:90] - node tdata_action = and(_T_778, _T_779) @[dec_tlu_ctl.scala 2221:69] - node _T_780 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2223:47] - node _T_781 = and(_T_780, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:52] - node _T_782 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2223:94] - node _T_783 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2223:136] - node _T_784 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2224:43] - node _T_785 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2224:83] + io.dec_tlu_ic_diag_pkt.icache_wrdata <= _T_756 @[dec_tlu_ctl.scala 2156:47] + io.dec_tlu_ic_diag_pkt.icache_dicawics <= dicawics @[dec_tlu_ctl.scala 2158:41] + node _T_757 = and(io.allow_dbg_halt_csr_write, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 2160:52] + node _T_758 = and(_T_757, io.dec_i0_decode_d) @[dec_tlu_ctl.scala 2160:75] + node _T_759 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 2160:98] + node _T_760 = and(_T_758, _T_759) @[dec_tlu_ctl.scala 2160:96] + node _T_761 = bits(io.dec_csr_rdaddr_d, 11, 0) @[dec_tlu_ctl.scala 2160:142] + node _T_762 = eq(_T_761, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2160:149] + node icache_rd_valid = and(_T_760, _T_762) @[dec_tlu_ctl.scala 2160:120] + node _T_763 = and(io.allow_dbg_halt_csr_write, io.dec_csr_wen_r_mod) @[dec_tlu_ctl.scala 2161:52] + node _T_764 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2161:97] + node _T_765 = eq(_T_764, UInt<12>("h07cb")) @[dec_tlu_ctl.scala 2161:104] + node icache_wr_valid = and(_T_763, _T_765) @[dec_tlu_ctl.scala 2161:75] + reg icache_rd_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2163:58] + icache_rd_valid_f <= icache_rd_valid @[dec_tlu_ctl.scala 2163:58] + reg icache_wr_valid_f : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2164:58] + icache_wr_valid_f <= icache_wr_valid @[dec_tlu_ctl.scala 2164:58] + io.dec_tlu_ic_diag_pkt.icache_rd_valid <= icache_rd_valid_f @[dec_tlu_ctl.scala 2166:41] + io.dec_tlu_ic_diag_pkt.icache_wr_valid <= icache_wr_valid_f @[dec_tlu_ctl.scala 2167:41] + node _T_766 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2175:62] + node _T_767 = eq(_T_766, UInt<12>("h07a0")) @[dec_tlu_ctl.scala 2175:69] + node wr_mtsel_r = and(io.dec_csr_wen_r_mod, _T_767) @[dec_tlu_ctl.scala 2175:40] + node _T_768 = bits(wr_mtsel_r, 0, 0) @[dec_tlu_ctl.scala 2176:32] + node _T_769 = bits(io.dec_csr_wrdata_r, 1, 0) @[dec_tlu_ctl.scala 2176:59] + node mtsel_ns = mux(_T_768, _T_769, mtsel) @[dec_tlu_ctl.scala 2176:20] + reg _T_770 : UInt, io.csr_wr_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2178:43] + _T_770 <= mtsel_ns @[dec_tlu_ctl.scala 2178:43] + mtsel <= _T_770 @[dec_tlu_ctl.scala 2178:8] + node _T_771 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2213:38] + node _T_772 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2213:64] + node _T_773 = not(_T_772) @[dec_tlu_ctl.scala 2213:44] + node tdata_load = and(_T_771, _T_773) @[dec_tlu_ctl.scala 2213:42] + node _T_774 = bits(io.dec_csr_wrdata_r, 2, 2) @[dec_tlu_ctl.scala 2215:40] + node _T_775 = bits(io.dec_csr_wrdata_r, 19, 19) @[dec_tlu_ctl.scala 2215:66] + node _T_776 = not(_T_775) @[dec_tlu_ctl.scala 2215:46] + node tdata_opcode = and(_T_774, _T_776) @[dec_tlu_ctl.scala 2215:44] + node _T_777 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2217:41] + node _T_778 = and(_T_777, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2217:46] + node _T_779 = bits(io.dec_csr_wrdata_r, 12, 12) @[dec_tlu_ctl.scala 2217:90] + node tdata_action = and(_T_778, _T_779) @[dec_tlu_ctl.scala 2217:69] + node _T_780 = bits(io.dec_csr_wrdata_r, 27, 27) @[dec_tlu_ctl.scala 2219:47] + node _T_781 = and(_T_780, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2219:52] + node _T_782 = bits(io.dec_csr_wrdata_r, 20, 19) @[dec_tlu_ctl.scala 2219:94] + node _T_783 = bits(io.dec_csr_wrdata_r, 11, 11) @[dec_tlu_ctl.scala 2219:136] + node _T_784 = bits(io.dec_csr_wrdata_r, 7, 6) @[dec_tlu_ctl.scala 2220:43] + node _T_785 = bits(io.dec_csr_wrdata_r, 1, 1) @[dec_tlu_ctl.scala 2220:83] node _T_786 = cat(_T_785, tdata_load) @[Cat.scala 29:58] node _T_787 = cat(_T_784, tdata_opcode) @[Cat.scala 29:58] node _T_788 = cat(_T_787, _T_786) @[Cat.scala 29:58] @@ -74079,106 +74079,106 @@ circuit quasar_wrapper : node _T_790 = cat(_T_781, _T_782) @[Cat.scala 29:58] node _T_791 = cat(_T_790, _T_789) @[Cat.scala 29:58] node tdata_wrdata_r = cat(_T_791, _T_788) @[Cat.scala 29:58] - node _T_792 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2227:92] - node _T_793 = eq(_T_792, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2227:99] - node _T_794 = and(io.dec_csr_wen_r_mod, _T_793) @[dec_tlu_ctl.scala 2227:70] - node _T_795 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2227:121] - node _T_796 = and(_T_794, _T_795) @[dec_tlu_ctl.scala 2227:112] - node _T_797 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2227:154] - node _T_798 = not(_T_797) @[dec_tlu_ctl.scala 2227:138] - node _T_799 = or(_T_798, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2227:170] - node _T_800 = and(_T_796, _T_799) @[dec_tlu_ctl.scala 2227:135] - node _T_801 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2227:92] - node _T_802 = eq(_T_801, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2227:99] - node _T_803 = and(io.dec_csr_wen_r_mod, _T_802) @[dec_tlu_ctl.scala 2227:70] - node _T_804 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2227:121] - node _T_805 = and(_T_803, _T_804) @[dec_tlu_ctl.scala 2227:112] - node _T_806 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2227:154] - node _T_807 = not(_T_806) @[dec_tlu_ctl.scala 2227:138] - node _T_808 = or(_T_807, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2227:170] - node _T_809 = and(_T_805, _T_808) @[dec_tlu_ctl.scala 2227:135] - node _T_810 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2227:92] - node _T_811 = eq(_T_810, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2227:99] - node _T_812 = and(io.dec_csr_wen_r_mod, _T_811) @[dec_tlu_ctl.scala 2227:70] - node _T_813 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2227:121] - node _T_814 = and(_T_812, _T_813) @[dec_tlu_ctl.scala 2227:112] - node _T_815 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2227:154] - node _T_816 = not(_T_815) @[dec_tlu_ctl.scala 2227:138] - node _T_817 = or(_T_816, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2227:170] - node _T_818 = and(_T_814, _T_817) @[dec_tlu_ctl.scala 2227:135] - node _T_819 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2227:92] - node _T_820 = eq(_T_819, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2227:99] - node _T_821 = and(io.dec_csr_wen_r_mod, _T_820) @[dec_tlu_ctl.scala 2227:70] - node _T_822 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2227:121] - node _T_823 = and(_T_821, _T_822) @[dec_tlu_ctl.scala 2227:112] - node _T_824 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2227:154] - node _T_825 = not(_T_824) @[dec_tlu_ctl.scala 2227:138] - node _T_826 = or(_T_825, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2227:170] - node _T_827 = and(_T_823, _T_826) @[dec_tlu_ctl.scala 2227:135] - wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2227:42] - wr_mtdata1_t_r[0] <= _T_800 @[dec_tlu_ctl.scala 2227:42] - wr_mtdata1_t_r[1] <= _T_809 @[dec_tlu_ctl.scala 2227:42] - wr_mtdata1_t_r[2] <= _T_818 @[dec_tlu_ctl.scala 2227:42] - wr_mtdata1_t_r[3] <= _T_827 @[dec_tlu_ctl.scala 2227:42] - node _T_828 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2228:68] - node _T_829 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2228:111] - node _T_830 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2228:135] - node _T_831 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2228:156] - node _T_832 = or(_T_830, _T_831) @[dec_tlu_ctl.scala 2228:139] - node _T_833 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2228:176] + node _T_792 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] + node _T_793 = eq(_T_792, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] + node _T_794 = and(io.dec_csr_wen_r_mod, _T_793) @[dec_tlu_ctl.scala 2223:70] + node _T_795 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2223:121] + node _T_796 = and(_T_794, _T_795) @[dec_tlu_ctl.scala 2223:112] + node _T_797 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2223:154] + node _T_798 = not(_T_797) @[dec_tlu_ctl.scala 2223:138] + node _T_799 = or(_T_798, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] + node _T_800 = and(_T_796, _T_799) @[dec_tlu_ctl.scala 2223:135] + node _T_801 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] + node _T_802 = eq(_T_801, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] + node _T_803 = and(io.dec_csr_wen_r_mod, _T_802) @[dec_tlu_ctl.scala 2223:70] + node _T_804 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2223:121] + node _T_805 = and(_T_803, _T_804) @[dec_tlu_ctl.scala 2223:112] + node _T_806 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2223:154] + node _T_807 = not(_T_806) @[dec_tlu_ctl.scala 2223:138] + node _T_808 = or(_T_807, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] + node _T_809 = and(_T_805, _T_808) @[dec_tlu_ctl.scala 2223:135] + node _T_810 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] + node _T_811 = eq(_T_810, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] + node _T_812 = and(io.dec_csr_wen_r_mod, _T_811) @[dec_tlu_ctl.scala 2223:70] + node _T_813 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2223:121] + node _T_814 = and(_T_812, _T_813) @[dec_tlu_ctl.scala 2223:112] + node _T_815 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2223:154] + node _T_816 = not(_T_815) @[dec_tlu_ctl.scala 2223:138] + node _T_817 = or(_T_816, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] + node _T_818 = and(_T_814, _T_817) @[dec_tlu_ctl.scala 2223:135] + node _T_819 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2223:92] + node _T_820 = eq(_T_819, UInt<12>("h07a1")) @[dec_tlu_ctl.scala 2223:99] + node _T_821 = and(io.dec_csr_wen_r_mod, _T_820) @[dec_tlu_ctl.scala 2223:70] + node _T_822 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2223:121] + node _T_823 = and(_T_821, _T_822) @[dec_tlu_ctl.scala 2223:112] + node _T_824 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2223:154] + node _T_825 = not(_T_824) @[dec_tlu_ctl.scala 2223:138] + node _T_826 = or(_T_825, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2223:170] + node _T_827 = and(_T_823, _T_826) @[dec_tlu_ctl.scala 2223:135] + wire wr_mtdata1_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2223:42] + wr_mtdata1_t_r[0] <= _T_800 @[dec_tlu_ctl.scala 2223:42] + wr_mtdata1_t_r[1] <= _T_809 @[dec_tlu_ctl.scala 2223:42] + wr_mtdata1_t_r[2] <= _T_818 @[dec_tlu_ctl.scala 2223:42] + wr_mtdata1_t_r[3] <= _T_827 @[dec_tlu_ctl.scala 2223:42] + node _T_828 = bits(wr_mtdata1_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2224:68] + node _T_829 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2224:111] + node _T_830 = bits(io.update_hit_bit_r, 0, 0) @[dec_tlu_ctl.scala 2224:135] + node _T_831 = bits(io.mtdata1_t[0], 8, 8) @[dec_tlu_ctl.scala 2224:156] + node _T_832 = or(_T_830, _T_831) @[dec_tlu_ctl.scala 2224:139] + node _T_833 = bits(io.mtdata1_t[0], 7, 0) @[dec_tlu_ctl.scala 2224:176] node _T_834 = cat(_T_829, _T_832) @[Cat.scala 29:58] node _T_835 = cat(_T_834, _T_833) @[Cat.scala 29:58] - node _T_836 = mux(_T_828, tdata_wrdata_r, _T_835) @[dec_tlu_ctl.scala 2228:49] - node _T_837 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2228:68] - node _T_838 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2228:111] - node _T_839 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2228:135] - node _T_840 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2228:156] - node _T_841 = or(_T_839, _T_840) @[dec_tlu_ctl.scala 2228:139] - node _T_842 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2228:176] + node _T_836 = mux(_T_828, tdata_wrdata_r, _T_835) @[dec_tlu_ctl.scala 2224:49] + node _T_837 = bits(wr_mtdata1_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2224:68] + node _T_838 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2224:111] + node _T_839 = bits(io.update_hit_bit_r, 1, 1) @[dec_tlu_ctl.scala 2224:135] + node _T_840 = bits(io.mtdata1_t[1], 8, 8) @[dec_tlu_ctl.scala 2224:156] + node _T_841 = or(_T_839, _T_840) @[dec_tlu_ctl.scala 2224:139] + node _T_842 = bits(io.mtdata1_t[1], 7, 0) @[dec_tlu_ctl.scala 2224:176] node _T_843 = cat(_T_838, _T_841) @[Cat.scala 29:58] node _T_844 = cat(_T_843, _T_842) @[Cat.scala 29:58] - node _T_845 = mux(_T_837, tdata_wrdata_r, _T_844) @[dec_tlu_ctl.scala 2228:49] - node _T_846 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2228:68] - node _T_847 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2228:111] - node _T_848 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2228:135] - node _T_849 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2228:156] - node _T_850 = or(_T_848, _T_849) @[dec_tlu_ctl.scala 2228:139] - node _T_851 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2228:176] + node _T_845 = mux(_T_837, tdata_wrdata_r, _T_844) @[dec_tlu_ctl.scala 2224:49] + node _T_846 = bits(wr_mtdata1_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2224:68] + node _T_847 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2224:111] + node _T_848 = bits(io.update_hit_bit_r, 2, 2) @[dec_tlu_ctl.scala 2224:135] + node _T_849 = bits(io.mtdata1_t[2], 8, 8) @[dec_tlu_ctl.scala 2224:156] + node _T_850 = or(_T_848, _T_849) @[dec_tlu_ctl.scala 2224:139] + node _T_851 = bits(io.mtdata1_t[2], 7, 0) @[dec_tlu_ctl.scala 2224:176] node _T_852 = cat(_T_847, _T_850) @[Cat.scala 29:58] node _T_853 = cat(_T_852, _T_851) @[Cat.scala 29:58] - node _T_854 = mux(_T_846, tdata_wrdata_r, _T_853) @[dec_tlu_ctl.scala 2228:49] - node _T_855 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2228:68] - node _T_856 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2228:111] - node _T_857 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2228:135] - node _T_858 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2228:156] - node _T_859 = or(_T_857, _T_858) @[dec_tlu_ctl.scala 2228:139] - node _T_860 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2228:176] + node _T_854 = mux(_T_846, tdata_wrdata_r, _T_853) @[dec_tlu_ctl.scala 2224:49] + node _T_855 = bits(wr_mtdata1_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2224:68] + node _T_856 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2224:111] + node _T_857 = bits(io.update_hit_bit_r, 3, 3) @[dec_tlu_ctl.scala 2224:135] + node _T_858 = bits(io.mtdata1_t[3], 8, 8) @[dec_tlu_ctl.scala 2224:156] + node _T_859 = or(_T_857, _T_858) @[dec_tlu_ctl.scala 2224:139] + node _T_860 = bits(io.mtdata1_t[3], 7, 0) @[dec_tlu_ctl.scala 2224:176] node _T_861 = cat(_T_856, _T_859) @[Cat.scala 29:58] node _T_862 = cat(_T_861, _T_860) @[Cat.scala 29:58] - node _T_863 = mux(_T_855, tdata_wrdata_r, _T_862) @[dec_tlu_ctl.scala 2228:49] - wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2228:40] - mtdata1_t_ns[0] <= _T_836 @[dec_tlu_ctl.scala 2228:40] - mtdata1_t_ns[1] <= _T_845 @[dec_tlu_ctl.scala 2228:40] - mtdata1_t_ns[2] <= _T_854 @[dec_tlu_ctl.scala 2228:40] - mtdata1_t_ns[3] <= _T_863 @[dec_tlu_ctl.scala 2228:40] - reg _T_864 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2230:74] - _T_864 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2230:74] - io.mtdata1_t[0] <= _T_864 @[dec_tlu_ctl.scala 2230:39] - reg _T_865 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2230:74] - _T_865 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2230:74] - io.mtdata1_t[1] <= _T_865 @[dec_tlu_ctl.scala 2230:39] - reg _T_866 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2230:74] - _T_866 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2230:74] - io.mtdata1_t[2] <= _T_866 @[dec_tlu_ctl.scala 2230:39] - reg _T_867 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2230:74] - _T_867 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2230:74] - io.mtdata1_t[3] <= _T_867 @[dec_tlu_ctl.scala 2230:39] - node _T_868 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2233:58] - node _T_869 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2233:104] - node _T_870 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2233:142] - node _T_871 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2233:174] - node _T_872 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2233:206] - node _T_873 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2233:238] + node _T_863 = mux(_T_855, tdata_wrdata_r, _T_862) @[dec_tlu_ctl.scala 2224:49] + wire mtdata1_t_ns : UInt<10>[4] @[dec_tlu_ctl.scala 2224:40] + mtdata1_t_ns[0] <= _T_836 @[dec_tlu_ctl.scala 2224:40] + mtdata1_t_ns[1] <= _T_845 @[dec_tlu_ctl.scala 2224:40] + mtdata1_t_ns[2] <= _T_854 @[dec_tlu_ctl.scala 2224:40] + mtdata1_t_ns[3] <= _T_863 @[dec_tlu_ctl.scala 2224:40] + reg _T_864 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74] + _T_864 <= mtdata1_t_ns[0] @[dec_tlu_ctl.scala 2226:74] + io.mtdata1_t[0] <= _T_864 @[dec_tlu_ctl.scala 2226:39] + reg _T_865 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74] + _T_865 <= mtdata1_t_ns[1] @[dec_tlu_ctl.scala 2226:74] + io.mtdata1_t[1] <= _T_865 @[dec_tlu_ctl.scala 2226:39] + reg _T_866 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74] + _T_866 <= mtdata1_t_ns[2] @[dec_tlu_ctl.scala 2226:74] + io.mtdata1_t[2] <= _T_866 @[dec_tlu_ctl.scala 2226:39] + reg _T_867 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2226:74] + _T_867 <= mtdata1_t_ns[3] @[dec_tlu_ctl.scala 2226:74] + io.mtdata1_t[3] <= _T_867 @[dec_tlu_ctl.scala 2226:39] + node _T_868 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2229:58] + node _T_869 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2229:104] + node _T_870 = bits(io.mtdata1_t[0], 8, 7) @[dec_tlu_ctl.scala 2229:142] + node _T_871 = bits(io.mtdata1_t[0], 6, 5) @[dec_tlu_ctl.scala 2229:174] + node _T_872 = bits(io.mtdata1_t[0], 4, 3) @[dec_tlu_ctl.scala 2229:206] + node _T_873 = bits(io.mtdata1_t[0], 2, 0) @[dec_tlu_ctl.scala 2229:238] node _T_874 = cat(UInt<3>("h00"), _T_873) @[Cat.scala 29:58] node _T_875 = cat(_T_871, UInt<3>("h00")) @[Cat.scala 29:58] node _T_876 = cat(_T_875, _T_872) @[Cat.scala 29:58] @@ -74188,12 +74188,12 @@ circuit quasar_wrapper : node _T_880 = cat(_T_879, UInt<6>("h01f")) @[Cat.scala 29:58] node _T_881 = cat(_T_880, _T_878) @[Cat.scala 29:58] node _T_882 = cat(_T_881, _T_877) @[Cat.scala 29:58] - node _T_883 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2233:58] - node _T_884 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2233:104] - node _T_885 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2233:142] - node _T_886 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2233:174] - node _T_887 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2233:206] - node _T_888 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2233:238] + node _T_883 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2229:58] + node _T_884 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2229:104] + node _T_885 = bits(io.mtdata1_t[1], 8, 7) @[dec_tlu_ctl.scala 2229:142] + node _T_886 = bits(io.mtdata1_t[1], 6, 5) @[dec_tlu_ctl.scala 2229:174] + node _T_887 = bits(io.mtdata1_t[1], 4, 3) @[dec_tlu_ctl.scala 2229:206] + node _T_888 = bits(io.mtdata1_t[1], 2, 0) @[dec_tlu_ctl.scala 2229:238] node _T_889 = cat(UInt<3>("h00"), _T_888) @[Cat.scala 29:58] node _T_890 = cat(_T_886, UInt<3>("h00")) @[Cat.scala 29:58] node _T_891 = cat(_T_890, _T_887) @[Cat.scala 29:58] @@ -74203,12 +74203,12 @@ circuit quasar_wrapper : node _T_895 = cat(_T_894, UInt<6>("h01f")) @[Cat.scala 29:58] node _T_896 = cat(_T_895, _T_893) @[Cat.scala 29:58] node _T_897 = cat(_T_896, _T_892) @[Cat.scala 29:58] - node _T_898 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2233:58] - node _T_899 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2233:104] - node _T_900 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2233:142] - node _T_901 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2233:174] - node _T_902 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2233:206] - node _T_903 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2233:238] + node _T_898 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2229:58] + node _T_899 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2229:104] + node _T_900 = bits(io.mtdata1_t[2], 8, 7) @[dec_tlu_ctl.scala 2229:142] + node _T_901 = bits(io.mtdata1_t[2], 6, 5) @[dec_tlu_ctl.scala 2229:174] + node _T_902 = bits(io.mtdata1_t[2], 4, 3) @[dec_tlu_ctl.scala 2229:206] + node _T_903 = bits(io.mtdata1_t[2], 2, 0) @[dec_tlu_ctl.scala 2229:238] node _T_904 = cat(UInt<3>("h00"), _T_903) @[Cat.scala 29:58] node _T_905 = cat(_T_901, UInt<3>("h00")) @[Cat.scala 29:58] node _T_906 = cat(_T_905, _T_902) @[Cat.scala 29:58] @@ -74218,12 +74218,12 @@ circuit quasar_wrapper : node _T_910 = cat(_T_909, UInt<6>("h01f")) @[Cat.scala 29:58] node _T_911 = cat(_T_910, _T_908) @[Cat.scala 29:58] node _T_912 = cat(_T_911, _T_907) @[Cat.scala 29:58] - node _T_913 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2233:58] - node _T_914 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2233:104] - node _T_915 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2233:142] - node _T_916 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2233:174] - node _T_917 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2233:206] - node _T_918 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2233:238] + node _T_913 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2229:58] + node _T_914 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2229:104] + node _T_915 = bits(io.mtdata1_t[3], 8, 7) @[dec_tlu_ctl.scala 2229:142] + node _T_916 = bits(io.mtdata1_t[3], 6, 5) @[dec_tlu_ctl.scala 2229:174] + node _T_917 = bits(io.mtdata1_t[3], 4, 3) @[dec_tlu_ctl.scala 2229:206] + node _T_918 = bits(io.mtdata1_t[3], 2, 0) @[dec_tlu_ctl.scala 2229:238] node _T_919 = cat(UInt<3>("h00"), _T_918) @[Cat.scala 29:58] node _T_920 = cat(_T_916, UInt<3>("h00")) @[Cat.scala 29:58] node _T_921 = cat(_T_920, _T_917) @[Cat.scala 29:58] @@ -74242,96 +74242,96 @@ circuit quasar_wrapper : node _T_934 = or(_T_933, _T_931) @[Mux.scala 27:72] wire mtdata1_tsel_out : UInt<32> @[Mux.scala 27:72] mtdata1_tsel_out <= _T_934 @[Mux.scala 27:72] - node _T_935 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[0].select <= _T_935 @[dec_tlu_ctl.scala 2235:40] - node _T_936 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2236:61] - io.trigger_pkt_any[0].match_pkt <= _T_936 @[dec_tlu_ctl.scala 2236:43] - node _T_937 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2237:58] - io.trigger_pkt_any[0].store <= _T_937 @[dec_tlu_ctl.scala 2237:40] - node _T_938 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2238:58] - io.trigger_pkt_any[0].load <= _T_938 @[dec_tlu_ctl.scala 2238:40] - node _T_939 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2239:58] - io.trigger_pkt_any[0].execute <= _T_939 @[dec_tlu_ctl.scala 2239:40] - node _T_940 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2240:58] - io.trigger_pkt_any[0].m <= _T_940 @[dec_tlu_ctl.scala 2240:40] - node _T_941 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[1].select <= _T_941 @[dec_tlu_ctl.scala 2235:40] - node _T_942 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2236:61] - io.trigger_pkt_any[1].match_pkt <= _T_942 @[dec_tlu_ctl.scala 2236:43] - node _T_943 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2237:58] - io.trigger_pkt_any[1].store <= _T_943 @[dec_tlu_ctl.scala 2237:40] - node _T_944 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2238:58] - io.trigger_pkt_any[1].load <= _T_944 @[dec_tlu_ctl.scala 2238:40] - node _T_945 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2239:58] - io.trigger_pkt_any[1].execute <= _T_945 @[dec_tlu_ctl.scala 2239:40] - node _T_946 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2240:58] - io.trigger_pkt_any[1].m <= _T_946 @[dec_tlu_ctl.scala 2240:40] - node _T_947 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[2].select <= _T_947 @[dec_tlu_ctl.scala 2235:40] - node _T_948 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2236:61] - io.trigger_pkt_any[2].match_pkt <= _T_948 @[dec_tlu_ctl.scala 2236:43] - node _T_949 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2237:58] - io.trigger_pkt_any[2].store <= _T_949 @[dec_tlu_ctl.scala 2237:40] - node _T_950 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2238:58] - io.trigger_pkt_any[2].load <= _T_950 @[dec_tlu_ctl.scala 2238:40] - node _T_951 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2239:58] - io.trigger_pkt_any[2].execute <= _T_951 @[dec_tlu_ctl.scala 2239:40] - node _T_952 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2240:58] - io.trigger_pkt_any[2].m <= _T_952 @[dec_tlu_ctl.scala 2240:40] - node _T_953 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2235:58] - io.trigger_pkt_any[3].select <= _T_953 @[dec_tlu_ctl.scala 2235:40] - node _T_954 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2236:61] - io.trigger_pkt_any[3].match_pkt <= _T_954 @[dec_tlu_ctl.scala 2236:43] - node _T_955 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2237:58] - io.trigger_pkt_any[3].store <= _T_955 @[dec_tlu_ctl.scala 2237:40] - node _T_956 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2238:58] - io.trigger_pkt_any[3].load <= _T_956 @[dec_tlu_ctl.scala 2238:40] - node _T_957 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2239:58] - io.trigger_pkt_any[3].execute <= _T_957 @[dec_tlu_ctl.scala 2239:40] - node _T_958 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2240:58] - io.trigger_pkt_any[3].m <= _T_958 @[dec_tlu_ctl.scala 2240:40] - node _T_959 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2247:91] - node _T_960 = eq(_T_959, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2247:98] - node _T_961 = and(io.dec_csr_wen_r_mod, _T_960) @[dec_tlu_ctl.scala 2247:69] - node _T_962 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2247:120] - node _T_963 = and(_T_961, _T_962) @[dec_tlu_ctl.scala 2247:111] - node _T_964 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2247:153] - node _T_965 = not(_T_964) @[dec_tlu_ctl.scala 2247:137] - node _T_966 = or(_T_965, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2247:169] - node _T_967 = and(_T_963, _T_966) @[dec_tlu_ctl.scala 2247:134] - node _T_968 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2247:91] - node _T_969 = eq(_T_968, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2247:98] - node _T_970 = and(io.dec_csr_wen_r_mod, _T_969) @[dec_tlu_ctl.scala 2247:69] - node _T_971 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2247:120] - node _T_972 = and(_T_970, _T_971) @[dec_tlu_ctl.scala 2247:111] - node _T_973 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2247:153] - node _T_974 = not(_T_973) @[dec_tlu_ctl.scala 2247:137] - node _T_975 = or(_T_974, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2247:169] - node _T_976 = and(_T_972, _T_975) @[dec_tlu_ctl.scala 2247:134] - node _T_977 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2247:91] - node _T_978 = eq(_T_977, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2247:98] - node _T_979 = and(io.dec_csr_wen_r_mod, _T_978) @[dec_tlu_ctl.scala 2247:69] - node _T_980 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2247:120] - node _T_981 = and(_T_979, _T_980) @[dec_tlu_ctl.scala 2247:111] - node _T_982 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2247:153] - node _T_983 = not(_T_982) @[dec_tlu_ctl.scala 2247:137] - node _T_984 = or(_T_983, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2247:169] - node _T_985 = and(_T_981, _T_984) @[dec_tlu_ctl.scala 2247:134] - node _T_986 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2247:91] - node _T_987 = eq(_T_986, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2247:98] - node _T_988 = and(io.dec_csr_wen_r_mod, _T_987) @[dec_tlu_ctl.scala 2247:69] - node _T_989 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2247:120] - node _T_990 = and(_T_988, _T_989) @[dec_tlu_ctl.scala 2247:111] - node _T_991 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2247:153] - node _T_992 = not(_T_991) @[dec_tlu_ctl.scala 2247:137] - node _T_993 = or(_T_992, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2247:169] - node _T_994 = and(_T_990, _T_993) @[dec_tlu_ctl.scala 2247:134] - wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2247:42] - wr_mtdata2_t_r[0] <= _T_967 @[dec_tlu_ctl.scala 2247:42] - wr_mtdata2_t_r[1] <= _T_976 @[dec_tlu_ctl.scala 2247:42] - wr_mtdata2_t_r[2] <= _T_985 @[dec_tlu_ctl.scala 2247:42] - wr_mtdata2_t_r[3] <= _T_994 @[dec_tlu_ctl.scala 2247:42] - node _T_995 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2248:84] + node _T_935 = bits(io.mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 2231:58] + io.trigger_pkt_any[0].select <= _T_935 @[dec_tlu_ctl.scala 2231:40] + node _T_936 = bits(io.mtdata1_t[0], 4, 4) @[dec_tlu_ctl.scala 2232:61] + io.trigger_pkt_any[0].match_pkt <= _T_936 @[dec_tlu_ctl.scala 2232:43] + node _T_937 = bits(io.mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[0].store <= _T_937 @[dec_tlu_ctl.scala 2233:40] + node _T_938 = bits(io.mtdata1_t[0], 0, 0) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[0].load <= _T_938 @[dec_tlu_ctl.scala 2234:40] + node _T_939 = bits(io.mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[0].execute <= _T_939 @[dec_tlu_ctl.scala 2235:40] + node _T_940 = bits(io.mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 2236:58] + io.trigger_pkt_any[0].m <= _T_940 @[dec_tlu_ctl.scala 2236:40] + node _T_941 = bits(io.mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 2231:58] + io.trigger_pkt_any[1].select <= _T_941 @[dec_tlu_ctl.scala 2231:40] + node _T_942 = bits(io.mtdata1_t[1], 4, 4) @[dec_tlu_ctl.scala 2232:61] + io.trigger_pkt_any[1].match_pkt <= _T_942 @[dec_tlu_ctl.scala 2232:43] + node _T_943 = bits(io.mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[1].store <= _T_943 @[dec_tlu_ctl.scala 2233:40] + node _T_944 = bits(io.mtdata1_t[1], 0, 0) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[1].load <= _T_944 @[dec_tlu_ctl.scala 2234:40] + node _T_945 = bits(io.mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[1].execute <= _T_945 @[dec_tlu_ctl.scala 2235:40] + node _T_946 = bits(io.mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 2236:58] + io.trigger_pkt_any[1].m <= _T_946 @[dec_tlu_ctl.scala 2236:40] + node _T_947 = bits(io.mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 2231:58] + io.trigger_pkt_any[2].select <= _T_947 @[dec_tlu_ctl.scala 2231:40] + node _T_948 = bits(io.mtdata1_t[2], 4, 4) @[dec_tlu_ctl.scala 2232:61] + io.trigger_pkt_any[2].match_pkt <= _T_948 @[dec_tlu_ctl.scala 2232:43] + node _T_949 = bits(io.mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[2].store <= _T_949 @[dec_tlu_ctl.scala 2233:40] + node _T_950 = bits(io.mtdata1_t[2], 0, 0) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[2].load <= _T_950 @[dec_tlu_ctl.scala 2234:40] + node _T_951 = bits(io.mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[2].execute <= _T_951 @[dec_tlu_ctl.scala 2235:40] + node _T_952 = bits(io.mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 2236:58] + io.trigger_pkt_any[2].m <= _T_952 @[dec_tlu_ctl.scala 2236:40] + node _T_953 = bits(io.mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 2231:58] + io.trigger_pkt_any[3].select <= _T_953 @[dec_tlu_ctl.scala 2231:40] + node _T_954 = bits(io.mtdata1_t[3], 4, 4) @[dec_tlu_ctl.scala 2232:61] + io.trigger_pkt_any[3].match_pkt <= _T_954 @[dec_tlu_ctl.scala 2232:43] + node _T_955 = bits(io.mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 2233:58] + io.trigger_pkt_any[3].store <= _T_955 @[dec_tlu_ctl.scala 2233:40] + node _T_956 = bits(io.mtdata1_t[3], 0, 0) @[dec_tlu_ctl.scala 2234:58] + io.trigger_pkt_any[3].load <= _T_956 @[dec_tlu_ctl.scala 2234:40] + node _T_957 = bits(io.mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 2235:58] + io.trigger_pkt_any[3].execute <= _T_957 @[dec_tlu_ctl.scala 2235:40] + node _T_958 = bits(io.mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 2236:58] + io.trigger_pkt_any[3].m <= _T_958 @[dec_tlu_ctl.scala 2236:40] + node _T_959 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] + node _T_960 = eq(_T_959, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] + node _T_961 = and(io.dec_csr_wen_r_mod, _T_960) @[dec_tlu_ctl.scala 2243:69] + node _T_962 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2243:120] + node _T_963 = and(_T_961, _T_962) @[dec_tlu_ctl.scala 2243:111] + node _T_964 = bits(io.mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 2243:153] + node _T_965 = not(_T_964) @[dec_tlu_ctl.scala 2243:137] + node _T_966 = or(_T_965, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] + node _T_967 = and(_T_963, _T_966) @[dec_tlu_ctl.scala 2243:134] + node _T_968 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] + node _T_969 = eq(_T_968, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] + node _T_970 = and(io.dec_csr_wen_r_mod, _T_969) @[dec_tlu_ctl.scala 2243:69] + node _T_971 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2243:120] + node _T_972 = and(_T_970, _T_971) @[dec_tlu_ctl.scala 2243:111] + node _T_973 = bits(io.mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 2243:153] + node _T_974 = not(_T_973) @[dec_tlu_ctl.scala 2243:137] + node _T_975 = or(_T_974, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] + node _T_976 = and(_T_972, _T_975) @[dec_tlu_ctl.scala 2243:134] + node _T_977 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] + node _T_978 = eq(_T_977, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] + node _T_979 = and(io.dec_csr_wen_r_mod, _T_978) @[dec_tlu_ctl.scala 2243:69] + node _T_980 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2243:120] + node _T_981 = and(_T_979, _T_980) @[dec_tlu_ctl.scala 2243:111] + node _T_982 = bits(io.mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 2243:153] + node _T_983 = not(_T_982) @[dec_tlu_ctl.scala 2243:137] + node _T_984 = or(_T_983, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] + node _T_985 = and(_T_981, _T_984) @[dec_tlu_ctl.scala 2243:134] + node _T_986 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2243:91] + node _T_987 = eq(_T_986, UInt<12>("h07a2")) @[dec_tlu_ctl.scala 2243:98] + node _T_988 = and(io.dec_csr_wen_r_mod, _T_987) @[dec_tlu_ctl.scala 2243:69] + node _T_989 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2243:120] + node _T_990 = and(_T_988, _T_989) @[dec_tlu_ctl.scala 2243:111] + node _T_991 = bits(io.mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 2243:153] + node _T_992 = not(_T_991) @[dec_tlu_ctl.scala 2243:137] + node _T_993 = or(_T_992, io.dbg_tlu_halted_f) @[dec_tlu_ctl.scala 2243:169] + node _T_994 = and(_T_990, _T_993) @[dec_tlu_ctl.scala 2243:134] + wire wr_mtdata2_t_r : UInt<1>[4] @[dec_tlu_ctl.scala 2243:42] + wr_mtdata2_t_r[0] <= _T_967 @[dec_tlu_ctl.scala 2243:42] + wr_mtdata2_t_r[1] <= _T_976 @[dec_tlu_ctl.scala 2243:42] + wr_mtdata2_t_r[2] <= _T_985 @[dec_tlu_ctl.scala 2243:42] + wr_mtdata2_t_r[3] <= _T_994 @[dec_tlu_ctl.scala 2243:42] + node _T_995 = bits(wr_mtdata2_t_r[0], 0, 0) @[dec_tlu_ctl.scala 2244:84] inst rvclkhdr_22 of rvclkhdr_742 @[lib.scala 352:23] rvclkhdr_22.clock <= clock rvclkhdr_22.reset <= reset @@ -74340,8 +74340,8 @@ circuit quasar_wrapper : rvclkhdr_22.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_996 : UInt, rvclkhdr_22.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_996 <= io.dec_csr_wrdata_r @[lib.scala 358:16] - mtdata2_t[0] <= _T_996 @[dec_tlu_ctl.scala 2248:36] - node _T_997 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2248:84] + mtdata2_t[0] <= _T_996 @[dec_tlu_ctl.scala 2244:36] + node _T_997 = bits(wr_mtdata2_t_r[1], 0, 0) @[dec_tlu_ctl.scala 2244:84] inst rvclkhdr_23 of rvclkhdr_743 @[lib.scala 352:23] rvclkhdr_23.clock <= clock rvclkhdr_23.reset <= reset @@ -74350,8 +74350,8 @@ circuit quasar_wrapper : rvclkhdr_23.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_998 : UInt, rvclkhdr_23.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_998 <= io.dec_csr_wrdata_r @[lib.scala 358:16] - mtdata2_t[1] <= _T_998 @[dec_tlu_ctl.scala 2248:36] - node _T_999 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2248:84] + mtdata2_t[1] <= _T_998 @[dec_tlu_ctl.scala 2244:36] + node _T_999 = bits(wr_mtdata2_t_r[2], 0, 0) @[dec_tlu_ctl.scala 2244:84] inst rvclkhdr_24 of rvclkhdr_744 @[lib.scala 352:23] rvclkhdr_24.clock <= clock rvclkhdr_24.reset <= reset @@ -74360,8 +74360,8 @@ circuit quasar_wrapper : rvclkhdr_24.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_1000 : UInt, rvclkhdr_24.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_1000 <= io.dec_csr_wrdata_r @[lib.scala 358:16] - mtdata2_t[2] <= _T_1000 @[dec_tlu_ctl.scala 2248:36] - node _T_1001 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2248:84] + mtdata2_t[2] <= _T_1000 @[dec_tlu_ctl.scala 2244:36] + node _T_1001 = bits(wr_mtdata2_t_r[3], 0, 0) @[dec_tlu_ctl.scala 2244:84] inst rvclkhdr_25 of rvclkhdr_745 @[lib.scala 352:23] rvclkhdr_25.clock <= clock rvclkhdr_25.reset <= reset @@ -74370,11 +74370,11 @@ circuit quasar_wrapper : rvclkhdr_25.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_1002 : UInt, rvclkhdr_25.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_1002 <= io.dec_csr_wrdata_r @[lib.scala 358:16] - mtdata2_t[3] <= _T_1002 @[dec_tlu_ctl.scala 2248:36] - node _T_1003 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2252:57] - node _T_1004 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2252:57] - node _T_1005 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2252:57] - node _T_1006 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2252:57] + mtdata2_t[3] <= _T_1002 @[dec_tlu_ctl.scala 2244:36] + node _T_1003 = eq(mtsel, UInt<2>("h00")) @[dec_tlu_ctl.scala 2248:57] + node _T_1004 = eq(mtsel, UInt<2>("h01")) @[dec_tlu_ctl.scala 2248:57] + node _T_1005 = eq(mtsel, UInt<2>("h02")) @[dec_tlu_ctl.scala 2248:57] + node _T_1006 = eq(mtsel, UInt<2>("h03")) @[dec_tlu_ctl.scala 2248:57] node _T_1007 = mux(_T_1003, mtdata2_t[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1008 = mux(_T_1004, mtdata2_t[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_1009 = mux(_T_1005, mtdata2_t[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -74384,188 +74384,188 @@ circuit quasar_wrapper : node _T_1013 = or(_T_1012, _T_1010) @[Mux.scala 27:72] wire mtdata2_tsel_out : UInt<32> @[Mux.scala 27:72] mtdata2_tsel_out <= _T_1013 @[Mux.scala 27:72] - io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2253:51] - io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2253:51] - io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2253:51] - io.trigger_pkt_any[3].tdata2 <= mtdata2_t[3] @[dec_tlu_ctl.scala 2253:51] - mhpme_vec[0] <= mhpme3 @[dec_tlu_ctl.scala 2263:15] - mhpme_vec[1] <= mhpme4 @[dec_tlu_ctl.scala 2264:15] - mhpme_vec[2] <= mhpme5 @[dec_tlu_ctl.scala 2265:15] - mhpme_vec[3] <= mhpme6 @[dec_tlu_ctl.scala 2266:15] + io.trigger_pkt_any[0].tdata2 <= mtdata2_t[0] @[dec_tlu_ctl.scala 2249:51] + io.trigger_pkt_any[1].tdata2 <= mtdata2_t[1] @[dec_tlu_ctl.scala 2249:51] + io.trigger_pkt_any[2].tdata2 <= mtdata2_t[2] @[dec_tlu_ctl.scala 2249:51] + io.trigger_pkt_any[3].tdata2 <= mtdata2_t[3] @[dec_tlu_ctl.scala 2249:51] + mhpme_vec[0] <= mhpme3 @[dec_tlu_ctl.scala 2259:15] + mhpme_vec[1] <= mhpme4 @[dec_tlu_ctl.scala 2260:15] + mhpme_vec[2] <= mhpme5 @[dec_tlu_ctl.scala 2261:15] + mhpme_vec[3] <= mhpme6 @[dec_tlu_ctl.scala 2262:15] node _T_1014 = bits(io.tlu_i0_commit_cmt, 0, 0) @[Bitwise.scala 72:15] node _T_1015 = mux(_T_1014, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1015) @[dec_tlu_ctl.scala 2272:59] - wire mhpmc_inc_r : UInt<1>[4] @[dec_tlu_ctl.scala 2273:24] - wire mhpmc_inc_r_d1 : UInt<1>[4] @[dec_tlu_ctl.scala 2274:27] - node _T_1016 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2278:38] - node _T_1017 = not(_T_1016) @[dec_tlu_ctl.scala 2278:24] - node _T_1018 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2279:34] - node _T_1019 = bits(_T_1018, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1020 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2280:34] - node _T_1021 = bits(_T_1020, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1022 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2281:34] - node _T_1023 = bits(_T_1022, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1024 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2282:34] - node _T_1025 = bits(_T_1024, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1026 = not(io.illegal_r) @[dec_tlu_ctl.scala 2282:96] - node _T_1027 = and(io.tlu_i0_commit_cmt, _T_1026) @[dec_tlu_ctl.scala 2282:94] - node _T_1028 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2283:34] - node _T_1029 = bits(_T_1028, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1030 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2283:96] - node _T_1031 = and(io.tlu_i0_commit_cmt, _T_1030) @[dec_tlu_ctl.scala 2283:94] - node _T_1032 = not(io.illegal_r) @[dec_tlu_ctl.scala 2283:117] - node _T_1033 = and(_T_1031, _T_1032) @[dec_tlu_ctl.scala 2283:115] - node _T_1034 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2284:34] - node _T_1035 = bits(_T_1034, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1036 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2284:94] - node _T_1037 = not(io.illegal_r) @[dec_tlu_ctl.scala 2284:117] - node _T_1038 = and(_T_1036, _T_1037) @[dec_tlu_ctl.scala 2284:115] - node _T_1039 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2285:34] - node _T_1040 = bits(_T_1039, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1041 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2286:34] - node _T_1042 = bits(_T_1041, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1043 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2287:34] - node _T_1044 = bits(_T_1043, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1045 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2288:34] - node _T_1046 = bits(_T_1045, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1047 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2288:91] - node _T_1048 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2289:34] - node _T_1049 = bits(_T_1048, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1050 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2289:105] - node _T_1051 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2290:34] - node _T_1052 = bits(_T_1051, 0, 0) @[dec_tlu_ctl.scala 2290:62] - node _T_1053 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2290:91] - node _T_1054 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2291:34] - node _T_1055 = bits(_T_1054, 0, 0) @[dec_tlu_ctl.scala 2291:62] - node _T_1056 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2291:91] - node _T_1057 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2292:34] - node _T_1058 = bits(_T_1057, 0, 0) @[dec_tlu_ctl.scala 2292:62] - node _T_1059 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2292:91] - node _T_1060 = and(_T_1059, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2292:100] - node _T_1061 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2293:34] - node _T_1062 = bits(_T_1061, 0, 0) @[dec_tlu_ctl.scala 2293:62] - node _T_1063 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2293:91] - node _T_1064 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2293:142] - node _T_1065 = and(_T_1063, _T_1064) @[dec_tlu_ctl.scala 2293:101] - node _T_1066 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2294:34] - node _T_1067 = bits(_T_1066, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1068 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2294:89] - node _T_1069 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2295:34] - node _T_1070 = bits(_T_1069, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1071 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2295:89] - node _T_1072 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2296:34] - node _T_1073 = bits(_T_1072, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1074 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2296:89] - node _T_1075 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2297:34] - node _T_1076 = bits(_T_1075, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1077 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2297:89] - node _T_1078 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2298:34] - node _T_1079 = bits(_T_1078, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1080 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2298:89] - node _T_1081 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2299:34] - node _T_1082 = bits(_T_1081, 0, 0) @[dec_tlu_ctl.scala 2299:59] - node _T_1083 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2299:89] - node _T_1084 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2300:34] - node _T_1085 = bits(_T_1084, 0, 0) @[dec_tlu_ctl.scala 2300:59] - node _T_1086 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2300:89] - node _T_1087 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2301:34] - node _T_1088 = bits(_T_1087, 0, 0) @[dec_tlu_ctl.scala 2301:59] - node _T_1089 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2301:89] - node _T_1090 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2302:34] - node _T_1091 = bits(_T_1090, 0, 0) @[dec_tlu_ctl.scala 2302:59] - node _T_1092 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2302:89] - node _T_1093 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2303:34] - node _T_1094 = bits(_T_1093, 0, 0) @[dec_tlu_ctl.scala 2303:59] - node _T_1095 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2303:89] - node _T_1096 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2303:122] - node _T_1097 = or(_T_1095, _T_1096) @[dec_tlu_ctl.scala 2303:101] - node _T_1098 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2304:34] - node _T_1099 = bits(_T_1098, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1100 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2304:95] - node _T_1101 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2305:34] - node _T_1102 = bits(_T_1101, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1103 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2305:97] - node _T_1104 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2306:34] - node _T_1105 = bits(_T_1104, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1106 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2306:110] - node _T_1107 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2307:34] - node _T_1108 = bits(_T_1107, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1109 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2308:34] - node _T_1110 = bits(_T_1109, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1111 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2309:34] - node _T_1112 = bits(_T_1111, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1113 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2310:34] - node _T_1114 = bits(_T_1113, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1115 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2311:34] - node _T_1116 = bits(_T_1115, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1117 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2312:34] - node _T_1118 = bits(_T_1117, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1119 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2313:34] - node _T_1120 = bits(_T_1119, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1121 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2314:34] - node _T_1122 = bits(_T_1121, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1123 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2314:98] - node _T_1124 = or(_T_1123, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2314:120] - node _T_1125 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2315:34] - node _T_1126 = bits(_T_1125, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1127 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2315:92] - node _T_1128 = or(_T_1127, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2315:117] - node _T_1129 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2316:34] - node _T_1130 = bits(_T_1129, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1131 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2317:34] - node _T_1132 = bits(_T_1131, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1133 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2318:34] - node _T_1134 = bits(_T_1133, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1135 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2318:97] - node _T_1136 = and(_T_1135, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2318:129] - node _T_1137 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2319:34] - node _T_1138 = bits(_T_1137, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1139 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2320:34] - node _T_1140 = bits(_T_1139, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1141 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2321:34] - node _T_1142 = bits(_T_1141, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1143 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2322:34] - node _T_1144 = bits(_T_1143, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1145 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2323:34] - node _T_1146 = bits(_T_1145, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1147 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2324:34] - node _T_1148 = bits(_T_1147, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1149 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2325:34] - node _T_1150 = bits(_T_1149, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1151 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2326:34] - node _T_1152 = bits(_T_1151, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_1153 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2326:84] - node _T_1154 = bits(_T_1153, 0, 0) @[dec_tlu_ctl.scala 2326:84] - node _T_1155 = not(_T_1154) @[dec_tlu_ctl.scala 2326:73] - node _T_1156 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2327:34] - node _T_1157 = bits(_T_1156, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_1158 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2327:84] - node _T_1159 = bits(_T_1158, 0, 0) @[dec_tlu_ctl.scala 2327:84] - node _T_1160 = not(_T_1159) @[dec_tlu_ctl.scala 2327:73] - node _T_1161 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2327:107] - node _T_1162 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2327:118] - node _T_1163 = and(_T_1161, _T_1162) @[dec_tlu_ctl.scala 2327:113] - node _T_1164 = orr(_T_1163) @[dec_tlu_ctl.scala 2327:125] - node _T_1165 = and(_T_1160, _T_1164) @[dec_tlu_ctl.scala 2327:98] - node _T_1166 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2328:34] - node _T_1167 = bits(_T_1166, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1168 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2328:91] - node _T_1169 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2329:34] - node _T_1170 = bits(_T_1169, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1171 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2329:94] - node _T_1172 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2330:34] - node _T_1173 = bits(_T_1172, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1174 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2330:94] - node _T_1175 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2332:34] - node _T_1176 = bits(_T_1175, 0, 0) @[dec_tlu_ctl.scala 2332:62] - node _T_1177 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2333:34] - node _T_1178 = bits(_T_1177, 0, 0) @[dec_tlu_ctl.scala 2333:62] - node _T_1179 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2334:34] - node _T_1180 = bits(_T_1179, 0, 0) @[dec_tlu_ctl.scala 2334:62] - node _T_1181 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2335:34] - node _T_1182 = bits(_T_1181, 0, 0) @[dec_tlu_ctl.scala 2335:62] - node _T_1183 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2336:34] - node _T_1184 = bits(_T_1183, 0, 0) @[dec_tlu_ctl.scala 2336:62] + node pmu_i0_itype_qual = and(io.dec_tlu_packet_r.pmu_i0_itype, _T_1015) @[dec_tlu_ctl.scala 2268:59] + wire mhpmc_inc_r : UInt<1>[4] @[dec_tlu_ctl.scala 2269:24] + wire mhpmc_inc_r_d1 : UInt<1>[4] @[dec_tlu_ctl.scala 2270:27] + node _T_1016 = bits(mcountinhibit, 3, 3) @[dec_tlu_ctl.scala 2274:38] + node _T_1017 = not(_T_1016) @[dec_tlu_ctl.scala 2274:24] + node _T_1018 = eq(mhpme_vec[0], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] + node _T_1019 = bits(_T_1018, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1020 = eq(mhpme_vec[0], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] + node _T_1021 = bits(_T_1020, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1022 = eq(mhpme_vec[0], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] + node _T_1023 = bits(_T_1022, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1024 = eq(mhpme_vec[0], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] + node _T_1025 = bits(_T_1024, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1026 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] + node _T_1027 = and(io.tlu_i0_commit_cmt, _T_1026) @[dec_tlu_ctl.scala 2278:94] + node _T_1028 = eq(mhpme_vec[0], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] + node _T_1029 = bits(_T_1028, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1030 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] + node _T_1031 = and(io.tlu_i0_commit_cmt, _T_1030) @[dec_tlu_ctl.scala 2279:94] + node _T_1032 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1033 = and(_T_1031, _T_1032) @[dec_tlu_ctl.scala 2279:115] + node _T_1034 = eq(mhpme_vec[0], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] + node _T_1035 = bits(_T_1034, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1036 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] + node _T_1037 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] + node _T_1038 = and(_T_1036, _T_1037) @[dec_tlu_ctl.scala 2280:115] + node _T_1039 = eq(mhpme_vec[0], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] + node _T_1040 = bits(_T_1039, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1041 = eq(mhpme_vec[0], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] + node _T_1042 = bits(_T_1041, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1043 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] + node _T_1044 = bits(_T_1043, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1045 = eq(mhpme_vec[0], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] + node _T_1046 = bits(_T_1045, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1047 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] + node _T_1048 = eq(mhpme_vec[0], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] + node _T_1049 = bits(_T_1048, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1050 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] + node _T_1051 = eq(mhpme_vec[0], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] + node _T_1052 = bits(_T_1051, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1053 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] + node _T_1054 = eq(mhpme_vec[0], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] + node _T_1055 = bits(_T_1054, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1056 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] + node _T_1057 = eq(mhpme_vec[0], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] + node _T_1058 = bits(_T_1057, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1059 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] + node _T_1060 = and(_T_1059, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] + node _T_1061 = eq(mhpme_vec[0], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] + node _T_1062 = bits(_T_1061, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1063 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] + node _T_1064 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] + node _T_1065 = and(_T_1063, _T_1064) @[dec_tlu_ctl.scala 2289:101] + node _T_1066 = eq(mhpme_vec[0], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] + node _T_1067 = bits(_T_1066, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1068 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] + node _T_1069 = eq(mhpme_vec[0], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] + node _T_1070 = bits(_T_1069, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1071 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] + node _T_1072 = eq(mhpme_vec[0], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] + node _T_1073 = bits(_T_1072, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1074 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] + node _T_1075 = eq(mhpme_vec[0], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] + node _T_1076 = bits(_T_1075, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1077 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] + node _T_1078 = eq(mhpme_vec[0], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] + node _T_1079 = bits(_T_1078, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1080 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] + node _T_1081 = eq(mhpme_vec[0], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] + node _T_1082 = bits(_T_1081, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1083 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] + node _T_1084 = eq(mhpme_vec[0], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] + node _T_1085 = bits(_T_1084, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1086 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] + node _T_1087 = eq(mhpme_vec[0], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] + node _T_1088 = bits(_T_1087, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1089 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] + node _T_1090 = eq(mhpme_vec[0], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] + node _T_1091 = bits(_T_1090, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1092 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] + node _T_1093 = eq(mhpme_vec[0], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] + node _T_1094 = bits(_T_1093, 0, 0) @[dec_tlu_ctl.scala 2299:59] + node _T_1095 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] + node _T_1096 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] + node _T_1097 = or(_T_1095, _T_1096) @[dec_tlu_ctl.scala 2299:101] + node _T_1098 = eq(mhpme_vec[0], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] + node _T_1099 = bits(_T_1098, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1100 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] + node _T_1101 = eq(mhpme_vec[0], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] + node _T_1102 = bits(_T_1101, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1103 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] + node _T_1104 = eq(mhpme_vec[0], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] + node _T_1105 = bits(_T_1104, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1106 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] + node _T_1107 = eq(mhpme_vec[0], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] + node _T_1108 = bits(_T_1107, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1109 = eq(mhpme_vec[0], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] + node _T_1110 = bits(_T_1109, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1111 = eq(mhpme_vec[0], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] + node _T_1112 = bits(_T_1111, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1113 = eq(mhpme_vec[0], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] + node _T_1114 = bits(_T_1113, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1115 = eq(mhpme_vec[0], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] + node _T_1116 = bits(_T_1115, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1117 = eq(mhpme_vec[0], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] + node _T_1118 = bits(_T_1117, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1119 = eq(mhpme_vec[0], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] + node _T_1120 = bits(_T_1119, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1121 = eq(mhpme_vec[0], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] + node _T_1122 = bits(_T_1121, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1123 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] + node _T_1124 = or(_T_1123, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] + node _T_1125 = eq(mhpme_vec[0], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] + node _T_1126 = bits(_T_1125, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1127 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] + node _T_1128 = or(_T_1127, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] + node _T_1129 = eq(mhpme_vec[0], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] + node _T_1130 = bits(_T_1129, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1131 = eq(mhpme_vec[0], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] + node _T_1132 = bits(_T_1131, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1133 = eq(mhpme_vec[0], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] + node _T_1134 = bits(_T_1133, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1135 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] + node _T_1136 = and(_T_1135, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] + node _T_1137 = eq(mhpme_vec[0], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] + node _T_1138 = bits(_T_1137, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1139 = eq(mhpme_vec[0], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] + node _T_1140 = bits(_T_1139, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1141 = eq(mhpme_vec[0], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] + node _T_1142 = bits(_T_1141, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1143 = eq(mhpme_vec[0], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] + node _T_1144 = bits(_T_1143, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1145 = eq(mhpme_vec[0], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] + node _T_1146 = bits(_T_1145, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1147 = eq(mhpme_vec[0], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] + node _T_1148 = bits(_T_1147, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1149 = eq(mhpme_vec[0], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] + node _T_1150 = bits(_T_1149, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1151 = eq(mhpme_vec[0], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] + node _T_1152 = bits(_T_1151, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1153 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1154 = bits(_T_1153, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1155 = not(_T_1154) @[dec_tlu_ctl.scala 2322:73] + node _T_1156 = eq(mhpme_vec[0], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] + node _T_1157 = bits(_T_1156, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1158 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] + node _T_1159 = bits(_T_1158, 0, 0) @[dec_tlu_ctl.scala 2323:84] + node _T_1160 = not(_T_1159) @[dec_tlu_ctl.scala 2323:73] + node _T_1161 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] + node _T_1162 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] + node _T_1163 = and(_T_1161, _T_1162) @[dec_tlu_ctl.scala 2323:113] + node _T_1164 = orr(_T_1163) @[dec_tlu_ctl.scala 2323:125] + node _T_1165 = and(_T_1160, _T_1164) @[dec_tlu_ctl.scala 2323:98] + node _T_1166 = eq(mhpme_vec[0], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] + node _T_1167 = bits(_T_1166, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1168 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] + node _T_1169 = eq(mhpme_vec[0], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] + node _T_1170 = bits(_T_1169, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1171 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1172 = eq(mhpme_vec[0], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] + node _T_1173 = bits(_T_1172, 0, 0) @[dec_tlu_ctl.scala 2326:62] + node _T_1174 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] + node _T_1175 = eq(mhpme_vec[0], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] + node _T_1176 = bits(_T_1175, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1177 = eq(mhpme_vec[0], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] + node _T_1178 = bits(_T_1177, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1179 = eq(mhpme_vec[0], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] + node _T_1180 = bits(_T_1179, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1181 = eq(mhpme_vec[0], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] + node _T_1182 = bits(_T_1181, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1183 = eq(mhpme_vec[0], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] + node _T_1184 = bits(_T_1183, 0, 0) @[dec_tlu_ctl.scala 2332:62] node _T_1185 = mux(_T_1019, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1186 = mux(_T_1021, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1187 = mux(_T_1023, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] @@ -74681,177 +74681,177 @@ circuit quasar_wrapper : node _T_1297 = or(_T_1296, _T_1241) @[Mux.scala 27:72] wire _T_1298 : UInt<1> @[Mux.scala 27:72] _T_1298 <= _T_1297 @[Mux.scala 27:72] - node _T_1299 = and(_T_1017, _T_1298) @[dec_tlu_ctl.scala 2278:44] - mhpmc_inc_r[0] <= _T_1299 @[dec_tlu_ctl.scala 2278:19] - node _T_1300 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2278:38] - node _T_1301 = not(_T_1300) @[dec_tlu_ctl.scala 2278:24] - node _T_1302 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2279:34] - node _T_1303 = bits(_T_1302, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1304 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2280:34] - node _T_1305 = bits(_T_1304, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1306 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2281:34] - node _T_1307 = bits(_T_1306, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1308 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2282:34] - node _T_1309 = bits(_T_1308, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1310 = not(io.illegal_r) @[dec_tlu_ctl.scala 2282:96] - node _T_1311 = and(io.tlu_i0_commit_cmt, _T_1310) @[dec_tlu_ctl.scala 2282:94] - node _T_1312 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2283:34] - node _T_1313 = bits(_T_1312, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1314 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2283:96] - node _T_1315 = and(io.tlu_i0_commit_cmt, _T_1314) @[dec_tlu_ctl.scala 2283:94] - node _T_1316 = not(io.illegal_r) @[dec_tlu_ctl.scala 2283:117] - node _T_1317 = and(_T_1315, _T_1316) @[dec_tlu_ctl.scala 2283:115] - node _T_1318 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2284:34] - node _T_1319 = bits(_T_1318, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1320 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2284:94] - node _T_1321 = not(io.illegal_r) @[dec_tlu_ctl.scala 2284:117] - node _T_1322 = and(_T_1320, _T_1321) @[dec_tlu_ctl.scala 2284:115] - node _T_1323 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2285:34] - node _T_1324 = bits(_T_1323, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1325 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2286:34] - node _T_1326 = bits(_T_1325, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1327 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2287:34] - node _T_1328 = bits(_T_1327, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1329 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2288:34] - node _T_1330 = bits(_T_1329, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1331 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2288:91] - node _T_1332 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2289:34] - node _T_1333 = bits(_T_1332, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1334 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2289:105] - node _T_1335 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2290:34] - node _T_1336 = bits(_T_1335, 0, 0) @[dec_tlu_ctl.scala 2290:62] - node _T_1337 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2290:91] - node _T_1338 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2291:34] - node _T_1339 = bits(_T_1338, 0, 0) @[dec_tlu_ctl.scala 2291:62] - node _T_1340 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2291:91] - node _T_1341 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2292:34] - node _T_1342 = bits(_T_1341, 0, 0) @[dec_tlu_ctl.scala 2292:62] - node _T_1343 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2292:91] - node _T_1344 = and(_T_1343, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2292:100] - node _T_1345 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2293:34] - node _T_1346 = bits(_T_1345, 0, 0) @[dec_tlu_ctl.scala 2293:62] - node _T_1347 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2293:91] - node _T_1348 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2293:142] - node _T_1349 = and(_T_1347, _T_1348) @[dec_tlu_ctl.scala 2293:101] - node _T_1350 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2294:34] - node _T_1351 = bits(_T_1350, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1352 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2294:89] - node _T_1353 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2295:34] - node _T_1354 = bits(_T_1353, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1355 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2295:89] - node _T_1356 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2296:34] - node _T_1357 = bits(_T_1356, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1358 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2296:89] - node _T_1359 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2297:34] - node _T_1360 = bits(_T_1359, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1361 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2297:89] - node _T_1362 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2298:34] - node _T_1363 = bits(_T_1362, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1364 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2298:89] - node _T_1365 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2299:34] - node _T_1366 = bits(_T_1365, 0, 0) @[dec_tlu_ctl.scala 2299:59] - node _T_1367 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2299:89] - node _T_1368 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2300:34] - node _T_1369 = bits(_T_1368, 0, 0) @[dec_tlu_ctl.scala 2300:59] - node _T_1370 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2300:89] - node _T_1371 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2301:34] - node _T_1372 = bits(_T_1371, 0, 0) @[dec_tlu_ctl.scala 2301:59] - node _T_1373 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2301:89] - node _T_1374 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2302:34] - node _T_1375 = bits(_T_1374, 0, 0) @[dec_tlu_ctl.scala 2302:59] - node _T_1376 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2302:89] - node _T_1377 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2303:34] - node _T_1378 = bits(_T_1377, 0, 0) @[dec_tlu_ctl.scala 2303:59] - node _T_1379 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2303:89] - node _T_1380 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2303:122] - node _T_1381 = or(_T_1379, _T_1380) @[dec_tlu_ctl.scala 2303:101] - node _T_1382 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2304:34] - node _T_1383 = bits(_T_1382, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1384 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2304:95] - node _T_1385 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2305:34] - node _T_1386 = bits(_T_1385, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1387 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2305:97] - node _T_1388 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2306:34] - node _T_1389 = bits(_T_1388, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1390 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2306:110] - node _T_1391 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2307:34] - node _T_1392 = bits(_T_1391, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2308:34] - node _T_1394 = bits(_T_1393, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1395 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2309:34] - node _T_1396 = bits(_T_1395, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1397 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2310:34] - node _T_1398 = bits(_T_1397, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1399 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2311:34] - node _T_1400 = bits(_T_1399, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1401 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2312:34] - node _T_1402 = bits(_T_1401, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1403 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2313:34] - node _T_1404 = bits(_T_1403, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1405 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2314:34] - node _T_1406 = bits(_T_1405, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1407 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2314:98] - node _T_1408 = or(_T_1407, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2314:120] - node _T_1409 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2315:34] - node _T_1410 = bits(_T_1409, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1411 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2315:92] - node _T_1412 = or(_T_1411, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2315:117] - node _T_1413 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2316:34] - node _T_1414 = bits(_T_1413, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1415 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2317:34] - node _T_1416 = bits(_T_1415, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1417 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2318:34] - node _T_1418 = bits(_T_1417, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1419 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2318:97] - node _T_1420 = and(_T_1419, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2318:129] - node _T_1421 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2319:34] - node _T_1422 = bits(_T_1421, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1423 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2320:34] - node _T_1424 = bits(_T_1423, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1425 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2321:34] - node _T_1426 = bits(_T_1425, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1427 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2322:34] - node _T_1428 = bits(_T_1427, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2323:34] - node _T_1430 = bits(_T_1429, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1431 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2324:34] - node _T_1432 = bits(_T_1431, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1433 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2325:34] - node _T_1434 = bits(_T_1433, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1435 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2326:34] - node _T_1436 = bits(_T_1435, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_1437 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2326:84] - node _T_1438 = bits(_T_1437, 0, 0) @[dec_tlu_ctl.scala 2326:84] - node _T_1439 = not(_T_1438) @[dec_tlu_ctl.scala 2326:73] - node _T_1440 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2327:34] - node _T_1441 = bits(_T_1440, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_1442 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2327:84] - node _T_1443 = bits(_T_1442, 0, 0) @[dec_tlu_ctl.scala 2327:84] - node _T_1444 = not(_T_1443) @[dec_tlu_ctl.scala 2327:73] - node _T_1445 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2327:107] - node _T_1446 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2327:118] - node _T_1447 = and(_T_1445, _T_1446) @[dec_tlu_ctl.scala 2327:113] - node _T_1448 = orr(_T_1447) @[dec_tlu_ctl.scala 2327:125] - node _T_1449 = and(_T_1444, _T_1448) @[dec_tlu_ctl.scala 2327:98] - node _T_1450 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2328:34] - node _T_1451 = bits(_T_1450, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1452 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2328:91] - node _T_1453 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2329:34] - node _T_1454 = bits(_T_1453, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1455 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2329:94] - node _T_1456 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2330:34] - node _T_1457 = bits(_T_1456, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1458 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2330:94] - node _T_1459 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2332:34] - node _T_1460 = bits(_T_1459, 0, 0) @[dec_tlu_ctl.scala 2332:62] - node _T_1461 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2333:34] - node _T_1462 = bits(_T_1461, 0, 0) @[dec_tlu_ctl.scala 2333:62] - node _T_1463 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2334:34] - node _T_1464 = bits(_T_1463, 0, 0) @[dec_tlu_ctl.scala 2334:62] - node _T_1465 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2335:34] - node _T_1466 = bits(_T_1465, 0, 0) @[dec_tlu_ctl.scala 2335:62] - node _T_1467 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2336:34] - node _T_1468 = bits(_T_1467, 0, 0) @[dec_tlu_ctl.scala 2336:62] + node _T_1299 = and(_T_1017, _T_1298) @[dec_tlu_ctl.scala 2274:44] + mhpmc_inc_r[0] <= _T_1299 @[dec_tlu_ctl.scala 2274:19] + node _T_1300 = bits(mcountinhibit, 4, 4) @[dec_tlu_ctl.scala 2274:38] + node _T_1301 = not(_T_1300) @[dec_tlu_ctl.scala 2274:24] + node _T_1302 = eq(mhpme_vec[1], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] + node _T_1303 = bits(_T_1302, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1304 = eq(mhpme_vec[1], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] + node _T_1305 = bits(_T_1304, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1306 = eq(mhpme_vec[1], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] + node _T_1307 = bits(_T_1306, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1308 = eq(mhpme_vec[1], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] + node _T_1309 = bits(_T_1308, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1310 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] + node _T_1311 = and(io.tlu_i0_commit_cmt, _T_1310) @[dec_tlu_ctl.scala 2278:94] + node _T_1312 = eq(mhpme_vec[1], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] + node _T_1313 = bits(_T_1312, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1314 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] + node _T_1315 = and(io.tlu_i0_commit_cmt, _T_1314) @[dec_tlu_ctl.scala 2279:94] + node _T_1316 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1317 = and(_T_1315, _T_1316) @[dec_tlu_ctl.scala 2279:115] + node _T_1318 = eq(mhpme_vec[1], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] + node _T_1319 = bits(_T_1318, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1320 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] + node _T_1321 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] + node _T_1322 = and(_T_1320, _T_1321) @[dec_tlu_ctl.scala 2280:115] + node _T_1323 = eq(mhpme_vec[1], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] + node _T_1324 = bits(_T_1323, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1325 = eq(mhpme_vec[1], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] + node _T_1326 = bits(_T_1325, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1327 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] + node _T_1328 = bits(_T_1327, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1329 = eq(mhpme_vec[1], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] + node _T_1330 = bits(_T_1329, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1331 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] + node _T_1332 = eq(mhpme_vec[1], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] + node _T_1333 = bits(_T_1332, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1334 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] + node _T_1335 = eq(mhpme_vec[1], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] + node _T_1336 = bits(_T_1335, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1337 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] + node _T_1338 = eq(mhpme_vec[1], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] + node _T_1339 = bits(_T_1338, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1340 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] + node _T_1341 = eq(mhpme_vec[1], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] + node _T_1342 = bits(_T_1341, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1343 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] + node _T_1344 = and(_T_1343, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] + node _T_1345 = eq(mhpme_vec[1], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] + node _T_1346 = bits(_T_1345, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1347 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] + node _T_1348 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] + node _T_1349 = and(_T_1347, _T_1348) @[dec_tlu_ctl.scala 2289:101] + node _T_1350 = eq(mhpme_vec[1], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] + node _T_1351 = bits(_T_1350, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1352 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] + node _T_1353 = eq(mhpme_vec[1], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] + node _T_1354 = bits(_T_1353, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1355 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] + node _T_1356 = eq(mhpme_vec[1], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] + node _T_1357 = bits(_T_1356, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1358 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] + node _T_1359 = eq(mhpme_vec[1], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] + node _T_1360 = bits(_T_1359, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1361 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] + node _T_1362 = eq(mhpme_vec[1], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] + node _T_1363 = bits(_T_1362, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1364 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] + node _T_1365 = eq(mhpme_vec[1], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] + node _T_1366 = bits(_T_1365, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1367 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] + node _T_1368 = eq(mhpme_vec[1], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] + node _T_1369 = bits(_T_1368, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1370 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] + node _T_1371 = eq(mhpme_vec[1], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] + node _T_1372 = bits(_T_1371, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1373 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] + node _T_1374 = eq(mhpme_vec[1], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] + node _T_1375 = bits(_T_1374, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1376 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] + node _T_1377 = eq(mhpme_vec[1], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] + node _T_1378 = bits(_T_1377, 0, 0) @[dec_tlu_ctl.scala 2299:59] + node _T_1379 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] + node _T_1380 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] + node _T_1381 = or(_T_1379, _T_1380) @[dec_tlu_ctl.scala 2299:101] + node _T_1382 = eq(mhpme_vec[1], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] + node _T_1383 = bits(_T_1382, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1384 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] + node _T_1385 = eq(mhpme_vec[1], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] + node _T_1386 = bits(_T_1385, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1387 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] + node _T_1388 = eq(mhpme_vec[1], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] + node _T_1389 = bits(_T_1388, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1390 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] + node _T_1391 = eq(mhpme_vec[1], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] + node _T_1392 = bits(_T_1391, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1393 = eq(mhpme_vec[1], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] + node _T_1394 = bits(_T_1393, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1395 = eq(mhpme_vec[1], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] + node _T_1396 = bits(_T_1395, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1397 = eq(mhpme_vec[1], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] + node _T_1398 = bits(_T_1397, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1399 = eq(mhpme_vec[1], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] + node _T_1400 = bits(_T_1399, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1401 = eq(mhpme_vec[1], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] + node _T_1402 = bits(_T_1401, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1403 = eq(mhpme_vec[1], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] + node _T_1404 = bits(_T_1403, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1405 = eq(mhpme_vec[1], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] + node _T_1406 = bits(_T_1405, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1407 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] + node _T_1408 = or(_T_1407, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] + node _T_1409 = eq(mhpme_vec[1], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] + node _T_1410 = bits(_T_1409, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1411 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] + node _T_1412 = or(_T_1411, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] + node _T_1413 = eq(mhpme_vec[1], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] + node _T_1414 = bits(_T_1413, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1415 = eq(mhpme_vec[1], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] + node _T_1416 = bits(_T_1415, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1417 = eq(mhpme_vec[1], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] + node _T_1418 = bits(_T_1417, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1419 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] + node _T_1420 = and(_T_1419, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] + node _T_1421 = eq(mhpme_vec[1], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] + node _T_1422 = bits(_T_1421, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1423 = eq(mhpme_vec[1], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] + node _T_1424 = bits(_T_1423, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1425 = eq(mhpme_vec[1], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] + node _T_1426 = bits(_T_1425, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1427 = eq(mhpme_vec[1], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] + node _T_1428 = bits(_T_1427, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1429 = eq(mhpme_vec[1], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] + node _T_1430 = bits(_T_1429, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1431 = eq(mhpme_vec[1], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] + node _T_1432 = bits(_T_1431, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1433 = eq(mhpme_vec[1], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] + node _T_1434 = bits(_T_1433, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1435 = eq(mhpme_vec[1], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] + node _T_1436 = bits(_T_1435, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1437 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1438 = bits(_T_1437, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1439 = not(_T_1438) @[dec_tlu_ctl.scala 2322:73] + node _T_1440 = eq(mhpme_vec[1], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] + node _T_1441 = bits(_T_1440, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1442 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] + node _T_1443 = bits(_T_1442, 0, 0) @[dec_tlu_ctl.scala 2323:84] + node _T_1444 = not(_T_1443) @[dec_tlu_ctl.scala 2323:73] + node _T_1445 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] + node _T_1446 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] + node _T_1447 = and(_T_1445, _T_1446) @[dec_tlu_ctl.scala 2323:113] + node _T_1448 = orr(_T_1447) @[dec_tlu_ctl.scala 2323:125] + node _T_1449 = and(_T_1444, _T_1448) @[dec_tlu_ctl.scala 2323:98] + node _T_1450 = eq(mhpme_vec[1], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] + node _T_1451 = bits(_T_1450, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1452 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] + node _T_1453 = eq(mhpme_vec[1], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] + node _T_1454 = bits(_T_1453, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1455 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1456 = eq(mhpme_vec[1], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] + node _T_1457 = bits(_T_1456, 0, 0) @[dec_tlu_ctl.scala 2326:62] + node _T_1458 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] + node _T_1459 = eq(mhpme_vec[1], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] + node _T_1460 = bits(_T_1459, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1461 = eq(mhpme_vec[1], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] + node _T_1462 = bits(_T_1461, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1463 = eq(mhpme_vec[1], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] + node _T_1464 = bits(_T_1463, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1465 = eq(mhpme_vec[1], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] + node _T_1466 = bits(_T_1465, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1467 = eq(mhpme_vec[1], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] + node _T_1468 = bits(_T_1467, 0, 0) @[dec_tlu_ctl.scala 2332:62] node _T_1469 = mux(_T_1303, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1470 = mux(_T_1305, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1471 = mux(_T_1307, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] @@ -74967,177 +74967,177 @@ circuit quasar_wrapper : node _T_1581 = or(_T_1580, _T_1525) @[Mux.scala 27:72] wire _T_1582 : UInt<1> @[Mux.scala 27:72] _T_1582 <= _T_1581 @[Mux.scala 27:72] - node _T_1583 = and(_T_1301, _T_1582) @[dec_tlu_ctl.scala 2278:44] - mhpmc_inc_r[1] <= _T_1583 @[dec_tlu_ctl.scala 2278:19] - node _T_1584 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2278:38] - node _T_1585 = not(_T_1584) @[dec_tlu_ctl.scala 2278:24] - node _T_1586 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2279:34] - node _T_1587 = bits(_T_1586, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1588 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2280:34] - node _T_1589 = bits(_T_1588, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1590 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2281:34] - node _T_1591 = bits(_T_1590, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1592 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2282:34] - node _T_1593 = bits(_T_1592, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1594 = not(io.illegal_r) @[dec_tlu_ctl.scala 2282:96] - node _T_1595 = and(io.tlu_i0_commit_cmt, _T_1594) @[dec_tlu_ctl.scala 2282:94] - node _T_1596 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2283:34] - node _T_1597 = bits(_T_1596, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1598 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2283:96] - node _T_1599 = and(io.tlu_i0_commit_cmt, _T_1598) @[dec_tlu_ctl.scala 2283:94] - node _T_1600 = not(io.illegal_r) @[dec_tlu_ctl.scala 2283:117] - node _T_1601 = and(_T_1599, _T_1600) @[dec_tlu_ctl.scala 2283:115] - node _T_1602 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2284:34] - node _T_1603 = bits(_T_1602, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1604 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2284:94] - node _T_1605 = not(io.illegal_r) @[dec_tlu_ctl.scala 2284:117] - node _T_1606 = and(_T_1604, _T_1605) @[dec_tlu_ctl.scala 2284:115] - node _T_1607 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2285:34] - node _T_1608 = bits(_T_1607, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1609 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2286:34] - node _T_1610 = bits(_T_1609, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1611 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2287:34] - node _T_1612 = bits(_T_1611, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1613 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2288:34] - node _T_1614 = bits(_T_1613, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1615 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2288:91] - node _T_1616 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2289:34] - node _T_1617 = bits(_T_1616, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1618 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2289:105] - node _T_1619 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2290:34] - node _T_1620 = bits(_T_1619, 0, 0) @[dec_tlu_ctl.scala 2290:62] - node _T_1621 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2290:91] - node _T_1622 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2291:34] - node _T_1623 = bits(_T_1622, 0, 0) @[dec_tlu_ctl.scala 2291:62] - node _T_1624 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2291:91] - node _T_1625 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2292:34] - node _T_1626 = bits(_T_1625, 0, 0) @[dec_tlu_ctl.scala 2292:62] - node _T_1627 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2292:91] - node _T_1628 = and(_T_1627, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2292:100] - node _T_1629 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2293:34] - node _T_1630 = bits(_T_1629, 0, 0) @[dec_tlu_ctl.scala 2293:62] - node _T_1631 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2293:91] - node _T_1632 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2293:142] - node _T_1633 = and(_T_1631, _T_1632) @[dec_tlu_ctl.scala 2293:101] - node _T_1634 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2294:34] - node _T_1635 = bits(_T_1634, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1636 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2294:89] - node _T_1637 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2295:34] - node _T_1638 = bits(_T_1637, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1639 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2295:89] - node _T_1640 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2296:34] - node _T_1641 = bits(_T_1640, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1642 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2296:89] - node _T_1643 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2297:34] - node _T_1644 = bits(_T_1643, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1645 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2297:89] - node _T_1646 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2298:34] - node _T_1647 = bits(_T_1646, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1648 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2298:89] - node _T_1649 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2299:34] - node _T_1650 = bits(_T_1649, 0, 0) @[dec_tlu_ctl.scala 2299:59] - node _T_1651 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2299:89] - node _T_1652 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2300:34] - node _T_1653 = bits(_T_1652, 0, 0) @[dec_tlu_ctl.scala 2300:59] - node _T_1654 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2300:89] - node _T_1655 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2301:34] - node _T_1656 = bits(_T_1655, 0, 0) @[dec_tlu_ctl.scala 2301:59] - node _T_1657 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2301:89] - node _T_1658 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2302:34] - node _T_1659 = bits(_T_1658, 0, 0) @[dec_tlu_ctl.scala 2302:59] - node _T_1660 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2302:89] - node _T_1661 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2303:34] - node _T_1662 = bits(_T_1661, 0, 0) @[dec_tlu_ctl.scala 2303:59] - node _T_1663 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2303:89] - node _T_1664 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2303:122] - node _T_1665 = or(_T_1663, _T_1664) @[dec_tlu_ctl.scala 2303:101] - node _T_1666 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2304:34] - node _T_1667 = bits(_T_1666, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1668 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2304:95] - node _T_1669 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2305:34] - node _T_1670 = bits(_T_1669, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1671 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2305:97] - node _T_1672 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2306:34] - node _T_1673 = bits(_T_1672, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1674 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2306:110] - node _T_1675 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2307:34] - node _T_1676 = bits(_T_1675, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1677 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2308:34] - node _T_1678 = bits(_T_1677, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1679 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2309:34] - node _T_1680 = bits(_T_1679, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1681 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2310:34] - node _T_1682 = bits(_T_1681, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1683 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2311:34] - node _T_1684 = bits(_T_1683, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1685 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2312:34] - node _T_1686 = bits(_T_1685, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1687 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2313:34] - node _T_1688 = bits(_T_1687, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1689 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2314:34] - node _T_1690 = bits(_T_1689, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1691 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2314:98] - node _T_1692 = or(_T_1691, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2314:120] - node _T_1693 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2315:34] - node _T_1694 = bits(_T_1693, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1695 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2315:92] - node _T_1696 = or(_T_1695, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2315:117] - node _T_1697 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2316:34] - node _T_1698 = bits(_T_1697, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1699 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2317:34] - node _T_1700 = bits(_T_1699, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1701 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2318:34] - node _T_1702 = bits(_T_1701, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1703 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2318:97] - node _T_1704 = and(_T_1703, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2318:129] - node _T_1705 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2319:34] - node _T_1706 = bits(_T_1705, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1707 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2320:34] - node _T_1708 = bits(_T_1707, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1709 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2321:34] - node _T_1710 = bits(_T_1709, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1711 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2322:34] - node _T_1712 = bits(_T_1711, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1713 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2323:34] - node _T_1714 = bits(_T_1713, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1715 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2324:34] - node _T_1716 = bits(_T_1715, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_1717 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2325:34] - node _T_1718 = bits(_T_1717, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_1719 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2326:34] - node _T_1720 = bits(_T_1719, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_1721 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2326:84] - node _T_1722 = bits(_T_1721, 0, 0) @[dec_tlu_ctl.scala 2326:84] - node _T_1723 = not(_T_1722) @[dec_tlu_ctl.scala 2326:73] - node _T_1724 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2327:34] - node _T_1725 = bits(_T_1724, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_1726 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2327:84] - node _T_1727 = bits(_T_1726, 0, 0) @[dec_tlu_ctl.scala 2327:84] - node _T_1728 = not(_T_1727) @[dec_tlu_ctl.scala 2327:73] - node _T_1729 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2327:107] - node _T_1730 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2327:118] - node _T_1731 = and(_T_1729, _T_1730) @[dec_tlu_ctl.scala 2327:113] - node _T_1732 = orr(_T_1731) @[dec_tlu_ctl.scala 2327:125] - node _T_1733 = and(_T_1728, _T_1732) @[dec_tlu_ctl.scala 2327:98] - node _T_1734 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2328:34] - node _T_1735 = bits(_T_1734, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_1736 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2328:91] - node _T_1737 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2329:34] - node _T_1738 = bits(_T_1737, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_1739 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2329:94] - node _T_1740 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2330:34] - node _T_1741 = bits(_T_1740, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_1742 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2330:94] - node _T_1743 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2332:34] - node _T_1744 = bits(_T_1743, 0, 0) @[dec_tlu_ctl.scala 2332:62] - node _T_1745 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2333:34] - node _T_1746 = bits(_T_1745, 0, 0) @[dec_tlu_ctl.scala 2333:62] - node _T_1747 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2334:34] - node _T_1748 = bits(_T_1747, 0, 0) @[dec_tlu_ctl.scala 2334:62] - node _T_1749 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2335:34] - node _T_1750 = bits(_T_1749, 0, 0) @[dec_tlu_ctl.scala 2335:62] - node _T_1751 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2336:34] - node _T_1752 = bits(_T_1751, 0, 0) @[dec_tlu_ctl.scala 2336:62] + node _T_1583 = and(_T_1301, _T_1582) @[dec_tlu_ctl.scala 2274:44] + mhpmc_inc_r[1] <= _T_1583 @[dec_tlu_ctl.scala 2274:19] + node _T_1584 = bits(mcountinhibit, 5, 5) @[dec_tlu_ctl.scala 2274:38] + node _T_1585 = not(_T_1584) @[dec_tlu_ctl.scala 2274:24] + node _T_1586 = eq(mhpme_vec[2], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] + node _T_1587 = bits(_T_1586, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1588 = eq(mhpme_vec[2], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] + node _T_1589 = bits(_T_1588, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1590 = eq(mhpme_vec[2], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] + node _T_1591 = bits(_T_1590, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1592 = eq(mhpme_vec[2], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] + node _T_1593 = bits(_T_1592, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1594 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] + node _T_1595 = and(io.tlu_i0_commit_cmt, _T_1594) @[dec_tlu_ctl.scala 2278:94] + node _T_1596 = eq(mhpme_vec[2], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] + node _T_1597 = bits(_T_1596, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1598 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] + node _T_1599 = and(io.tlu_i0_commit_cmt, _T_1598) @[dec_tlu_ctl.scala 2279:94] + node _T_1600 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1601 = and(_T_1599, _T_1600) @[dec_tlu_ctl.scala 2279:115] + node _T_1602 = eq(mhpme_vec[2], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] + node _T_1603 = bits(_T_1602, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1604 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] + node _T_1605 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] + node _T_1606 = and(_T_1604, _T_1605) @[dec_tlu_ctl.scala 2280:115] + node _T_1607 = eq(mhpme_vec[2], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] + node _T_1608 = bits(_T_1607, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1609 = eq(mhpme_vec[2], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] + node _T_1610 = bits(_T_1609, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1611 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] + node _T_1612 = bits(_T_1611, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1613 = eq(mhpme_vec[2], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] + node _T_1614 = bits(_T_1613, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1615 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] + node _T_1616 = eq(mhpme_vec[2], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] + node _T_1617 = bits(_T_1616, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1618 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] + node _T_1619 = eq(mhpme_vec[2], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] + node _T_1620 = bits(_T_1619, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1621 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] + node _T_1622 = eq(mhpme_vec[2], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] + node _T_1623 = bits(_T_1622, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1624 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] + node _T_1625 = eq(mhpme_vec[2], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] + node _T_1626 = bits(_T_1625, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1627 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] + node _T_1628 = and(_T_1627, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] + node _T_1629 = eq(mhpme_vec[2], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] + node _T_1630 = bits(_T_1629, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1631 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] + node _T_1632 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] + node _T_1633 = and(_T_1631, _T_1632) @[dec_tlu_ctl.scala 2289:101] + node _T_1634 = eq(mhpme_vec[2], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] + node _T_1635 = bits(_T_1634, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1636 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] + node _T_1637 = eq(mhpme_vec[2], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] + node _T_1638 = bits(_T_1637, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1639 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] + node _T_1640 = eq(mhpme_vec[2], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] + node _T_1641 = bits(_T_1640, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1642 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] + node _T_1643 = eq(mhpme_vec[2], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] + node _T_1644 = bits(_T_1643, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1645 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] + node _T_1646 = eq(mhpme_vec[2], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] + node _T_1647 = bits(_T_1646, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1648 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] + node _T_1649 = eq(mhpme_vec[2], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] + node _T_1650 = bits(_T_1649, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1651 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] + node _T_1652 = eq(mhpme_vec[2], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] + node _T_1653 = bits(_T_1652, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1654 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] + node _T_1655 = eq(mhpme_vec[2], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] + node _T_1656 = bits(_T_1655, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1657 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] + node _T_1658 = eq(mhpme_vec[2], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] + node _T_1659 = bits(_T_1658, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1660 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] + node _T_1661 = eq(mhpme_vec[2], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] + node _T_1662 = bits(_T_1661, 0, 0) @[dec_tlu_ctl.scala 2299:59] + node _T_1663 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] + node _T_1664 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] + node _T_1665 = or(_T_1663, _T_1664) @[dec_tlu_ctl.scala 2299:101] + node _T_1666 = eq(mhpme_vec[2], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] + node _T_1667 = bits(_T_1666, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1668 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] + node _T_1669 = eq(mhpme_vec[2], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] + node _T_1670 = bits(_T_1669, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1671 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] + node _T_1672 = eq(mhpme_vec[2], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] + node _T_1673 = bits(_T_1672, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1674 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] + node _T_1675 = eq(mhpme_vec[2], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] + node _T_1676 = bits(_T_1675, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1677 = eq(mhpme_vec[2], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] + node _T_1678 = bits(_T_1677, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1679 = eq(mhpme_vec[2], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] + node _T_1680 = bits(_T_1679, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1681 = eq(mhpme_vec[2], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] + node _T_1682 = bits(_T_1681, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1683 = eq(mhpme_vec[2], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] + node _T_1684 = bits(_T_1683, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1685 = eq(mhpme_vec[2], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] + node _T_1686 = bits(_T_1685, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1687 = eq(mhpme_vec[2], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] + node _T_1688 = bits(_T_1687, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1689 = eq(mhpme_vec[2], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] + node _T_1690 = bits(_T_1689, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1691 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] + node _T_1692 = or(_T_1691, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] + node _T_1693 = eq(mhpme_vec[2], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] + node _T_1694 = bits(_T_1693, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1695 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] + node _T_1696 = or(_T_1695, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] + node _T_1697 = eq(mhpme_vec[2], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] + node _T_1698 = bits(_T_1697, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1699 = eq(mhpme_vec[2], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] + node _T_1700 = bits(_T_1699, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1701 = eq(mhpme_vec[2], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] + node _T_1702 = bits(_T_1701, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1703 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] + node _T_1704 = and(_T_1703, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] + node _T_1705 = eq(mhpme_vec[2], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] + node _T_1706 = bits(_T_1705, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1707 = eq(mhpme_vec[2], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] + node _T_1708 = bits(_T_1707, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1709 = eq(mhpme_vec[2], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] + node _T_1710 = bits(_T_1709, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1711 = eq(mhpme_vec[2], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] + node _T_1712 = bits(_T_1711, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1713 = eq(mhpme_vec[2], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] + node _T_1714 = bits(_T_1713, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1715 = eq(mhpme_vec[2], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] + node _T_1716 = bits(_T_1715, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_1717 = eq(mhpme_vec[2], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] + node _T_1718 = bits(_T_1717, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_1719 = eq(mhpme_vec[2], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] + node _T_1720 = bits(_T_1719, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_1721 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_1722 = bits(_T_1721, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_1723 = not(_T_1722) @[dec_tlu_ctl.scala 2322:73] + node _T_1724 = eq(mhpme_vec[2], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] + node _T_1725 = bits(_T_1724, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_1726 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] + node _T_1727 = bits(_T_1726, 0, 0) @[dec_tlu_ctl.scala 2323:84] + node _T_1728 = not(_T_1727) @[dec_tlu_ctl.scala 2323:73] + node _T_1729 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] + node _T_1730 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] + node _T_1731 = and(_T_1729, _T_1730) @[dec_tlu_ctl.scala 2323:113] + node _T_1732 = orr(_T_1731) @[dec_tlu_ctl.scala 2323:125] + node _T_1733 = and(_T_1728, _T_1732) @[dec_tlu_ctl.scala 2323:98] + node _T_1734 = eq(mhpme_vec[2], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] + node _T_1735 = bits(_T_1734, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_1736 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] + node _T_1737 = eq(mhpme_vec[2], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] + node _T_1738 = bits(_T_1737, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_1739 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_1740 = eq(mhpme_vec[2], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] + node _T_1741 = bits(_T_1740, 0, 0) @[dec_tlu_ctl.scala 2326:62] + node _T_1742 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] + node _T_1743 = eq(mhpme_vec[2], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] + node _T_1744 = bits(_T_1743, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_1745 = eq(mhpme_vec[2], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] + node _T_1746 = bits(_T_1745, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_1747 = eq(mhpme_vec[2], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] + node _T_1748 = bits(_T_1747, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_1749 = eq(mhpme_vec[2], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] + node _T_1750 = bits(_T_1749, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_1751 = eq(mhpme_vec[2], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] + node _T_1752 = bits(_T_1751, 0, 0) @[dec_tlu_ctl.scala 2332:62] node _T_1753 = mux(_T_1587, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_1754 = mux(_T_1589, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1755 = mux(_T_1591, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] @@ -75253,177 +75253,177 @@ circuit quasar_wrapper : node _T_1865 = or(_T_1864, _T_1809) @[Mux.scala 27:72] wire _T_1866 : UInt<1> @[Mux.scala 27:72] _T_1866 <= _T_1865 @[Mux.scala 27:72] - node _T_1867 = and(_T_1585, _T_1866) @[dec_tlu_ctl.scala 2278:44] - mhpmc_inc_r[2] <= _T_1867 @[dec_tlu_ctl.scala 2278:19] - node _T_1868 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2278:38] - node _T_1869 = not(_T_1868) @[dec_tlu_ctl.scala 2278:24] - node _T_1870 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2279:34] - node _T_1871 = bits(_T_1870, 0, 0) @[dec_tlu_ctl.scala 2279:62] - node _T_1872 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2280:34] - node _T_1873 = bits(_T_1872, 0, 0) @[dec_tlu_ctl.scala 2280:62] - node _T_1874 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2281:34] - node _T_1875 = bits(_T_1874, 0, 0) @[dec_tlu_ctl.scala 2281:62] - node _T_1876 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2282:34] - node _T_1877 = bits(_T_1876, 0, 0) @[dec_tlu_ctl.scala 2282:62] - node _T_1878 = not(io.illegal_r) @[dec_tlu_ctl.scala 2282:96] - node _T_1879 = and(io.tlu_i0_commit_cmt, _T_1878) @[dec_tlu_ctl.scala 2282:94] - node _T_1880 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2283:34] - node _T_1881 = bits(_T_1880, 0, 0) @[dec_tlu_ctl.scala 2283:62] - node _T_1882 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2283:96] - node _T_1883 = and(io.tlu_i0_commit_cmt, _T_1882) @[dec_tlu_ctl.scala 2283:94] - node _T_1884 = not(io.illegal_r) @[dec_tlu_ctl.scala 2283:117] - node _T_1885 = and(_T_1883, _T_1884) @[dec_tlu_ctl.scala 2283:115] - node _T_1886 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2284:34] - node _T_1887 = bits(_T_1886, 0, 0) @[dec_tlu_ctl.scala 2284:62] - node _T_1888 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2284:94] - node _T_1889 = not(io.illegal_r) @[dec_tlu_ctl.scala 2284:117] - node _T_1890 = and(_T_1888, _T_1889) @[dec_tlu_ctl.scala 2284:115] - node _T_1891 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2285:34] - node _T_1892 = bits(_T_1891, 0, 0) @[dec_tlu_ctl.scala 2285:62] - node _T_1893 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2286:34] - node _T_1894 = bits(_T_1893, 0, 0) @[dec_tlu_ctl.scala 2286:62] - node _T_1895 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2287:34] - node _T_1896 = bits(_T_1895, 0, 0) @[dec_tlu_ctl.scala 2287:62] - node _T_1897 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2288:34] - node _T_1898 = bits(_T_1897, 0, 0) @[dec_tlu_ctl.scala 2288:62] - node _T_1899 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2288:91] - node _T_1900 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2289:34] - node _T_1901 = bits(_T_1900, 0, 0) @[dec_tlu_ctl.scala 2289:62] - node _T_1902 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2289:105] - node _T_1903 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2290:34] - node _T_1904 = bits(_T_1903, 0, 0) @[dec_tlu_ctl.scala 2290:62] - node _T_1905 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2290:91] - node _T_1906 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2291:34] - node _T_1907 = bits(_T_1906, 0, 0) @[dec_tlu_ctl.scala 2291:62] - node _T_1908 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2291:91] - node _T_1909 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2292:34] - node _T_1910 = bits(_T_1909, 0, 0) @[dec_tlu_ctl.scala 2292:62] - node _T_1911 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2292:91] - node _T_1912 = and(_T_1911, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2292:100] - node _T_1913 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2293:34] - node _T_1914 = bits(_T_1913, 0, 0) @[dec_tlu_ctl.scala 2293:62] - node _T_1915 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2293:91] - node _T_1916 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2293:142] - node _T_1917 = and(_T_1915, _T_1916) @[dec_tlu_ctl.scala 2293:101] - node _T_1918 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2294:34] - node _T_1919 = bits(_T_1918, 0, 0) @[dec_tlu_ctl.scala 2294:59] - node _T_1920 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2294:89] - node _T_1921 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2295:34] - node _T_1922 = bits(_T_1921, 0, 0) @[dec_tlu_ctl.scala 2295:59] - node _T_1923 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2295:89] - node _T_1924 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2296:34] - node _T_1925 = bits(_T_1924, 0, 0) @[dec_tlu_ctl.scala 2296:59] - node _T_1926 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2296:89] - node _T_1927 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2297:34] - node _T_1928 = bits(_T_1927, 0, 0) @[dec_tlu_ctl.scala 2297:59] - node _T_1929 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2297:89] - node _T_1930 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2298:34] - node _T_1931 = bits(_T_1930, 0, 0) @[dec_tlu_ctl.scala 2298:59] - node _T_1932 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2298:89] - node _T_1933 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2299:34] - node _T_1934 = bits(_T_1933, 0, 0) @[dec_tlu_ctl.scala 2299:59] - node _T_1935 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2299:89] - node _T_1936 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2300:34] - node _T_1937 = bits(_T_1936, 0, 0) @[dec_tlu_ctl.scala 2300:59] - node _T_1938 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2300:89] - node _T_1939 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2301:34] - node _T_1940 = bits(_T_1939, 0, 0) @[dec_tlu_ctl.scala 2301:59] - node _T_1941 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2301:89] - node _T_1942 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2302:34] - node _T_1943 = bits(_T_1942, 0, 0) @[dec_tlu_ctl.scala 2302:59] - node _T_1944 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2302:89] - node _T_1945 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2303:34] - node _T_1946 = bits(_T_1945, 0, 0) @[dec_tlu_ctl.scala 2303:59] - node _T_1947 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2303:89] - node _T_1948 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2303:122] - node _T_1949 = or(_T_1947, _T_1948) @[dec_tlu_ctl.scala 2303:101] - node _T_1950 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2304:34] - node _T_1951 = bits(_T_1950, 0, 0) @[dec_tlu_ctl.scala 2304:62] - node _T_1952 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2304:95] - node _T_1953 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2305:34] - node _T_1954 = bits(_T_1953, 0, 0) @[dec_tlu_ctl.scala 2305:62] - node _T_1955 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2305:97] - node _T_1956 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2306:34] - node _T_1957 = bits(_T_1956, 0, 0) @[dec_tlu_ctl.scala 2306:62] - node _T_1958 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2306:110] - node _T_1959 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2307:34] - node _T_1960 = bits(_T_1959, 0, 0) @[dec_tlu_ctl.scala 2307:62] - node _T_1961 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2308:34] - node _T_1962 = bits(_T_1961, 0, 0) @[dec_tlu_ctl.scala 2308:62] - node _T_1963 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2309:34] - node _T_1964 = bits(_T_1963, 0, 0) @[dec_tlu_ctl.scala 2309:62] - node _T_1965 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2310:34] - node _T_1966 = bits(_T_1965, 0, 0) @[dec_tlu_ctl.scala 2310:62] - node _T_1967 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2311:34] - node _T_1968 = bits(_T_1967, 0, 0) @[dec_tlu_ctl.scala 2311:62] - node _T_1969 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2312:34] - node _T_1970 = bits(_T_1969, 0, 0) @[dec_tlu_ctl.scala 2312:62] - node _T_1971 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2313:34] - node _T_1972 = bits(_T_1971, 0, 0) @[dec_tlu_ctl.scala 2313:62] - node _T_1973 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2314:34] - node _T_1974 = bits(_T_1973, 0, 0) @[dec_tlu_ctl.scala 2314:62] - node _T_1975 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2314:98] - node _T_1976 = or(_T_1975, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2314:120] - node _T_1977 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2315:34] - node _T_1978 = bits(_T_1977, 0, 0) @[dec_tlu_ctl.scala 2315:62] - node _T_1979 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2315:92] - node _T_1980 = or(_T_1979, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2315:117] - node _T_1981 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2316:34] - node _T_1982 = bits(_T_1981, 0, 0) @[dec_tlu_ctl.scala 2316:62] - node _T_1983 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2317:34] - node _T_1984 = bits(_T_1983, 0, 0) @[dec_tlu_ctl.scala 2317:62] - node _T_1985 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2318:34] - node _T_1986 = bits(_T_1985, 0, 0) @[dec_tlu_ctl.scala 2318:62] - node _T_1987 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2318:97] - node _T_1988 = and(_T_1987, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2318:129] - node _T_1989 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2319:34] - node _T_1990 = bits(_T_1989, 0, 0) @[dec_tlu_ctl.scala 2319:62] - node _T_1991 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2320:34] - node _T_1992 = bits(_T_1991, 0, 0) @[dec_tlu_ctl.scala 2320:62] - node _T_1993 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2321:34] - node _T_1994 = bits(_T_1993, 0, 0) @[dec_tlu_ctl.scala 2321:62] - node _T_1995 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2322:34] - node _T_1996 = bits(_T_1995, 0, 0) @[dec_tlu_ctl.scala 2322:62] - node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2323:34] - node _T_1998 = bits(_T_1997, 0, 0) @[dec_tlu_ctl.scala 2323:62] - node _T_1999 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2324:34] - node _T_2000 = bits(_T_1999, 0, 0) @[dec_tlu_ctl.scala 2324:62] - node _T_2001 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2325:34] - node _T_2002 = bits(_T_2001, 0, 0) @[dec_tlu_ctl.scala 2325:62] - node _T_2003 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2326:34] - node _T_2004 = bits(_T_2003, 0, 0) @[dec_tlu_ctl.scala 2326:62] - node _T_2005 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2326:84] - node _T_2006 = bits(_T_2005, 0, 0) @[dec_tlu_ctl.scala 2326:84] - node _T_2007 = not(_T_2006) @[dec_tlu_ctl.scala 2326:73] - node _T_2008 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2327:34] - node _T_2009 = bits(_T_2008, 0, 0) @[dec_tlu_ctl.scala 2327:62] - node _T_2010 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2327:84] - node _T_2011 = bits(_T_2010, 0, 0) @[dec_tlu_ctl.scala 2327:84] - node _T_2012 = not(_T_2011) @[dec_tlu_ctl.scala 2327:73] - node _T_2013 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2327:107] - node _T_2014 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2327:118] - node _T_2015 = and(_T_2013, _T_2014) @[dec_tlu_ctl.scala 2327:113] - node _T_2016 = orr(_T_2015) @[dec_tlu_ctl.scala 2327:125] - node _T_2017 = and(_T_2012, _T_2016) @[dec_tlu_ctl.scala 2327:98] - node _T_2018 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2328:34] - node _T_2019 = bits(_T_2018, 0, 0) @[dec_tlu_ctl.scala 2328:62] - node _T_2020 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2328:91] - node _T_2021 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2329:34] - node _T_2022 = bits(_T_2021, 0, 0) @[dec_tlu_ctl.scala 2329:62] - node _T_2023 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2329:94] - node _T_2024 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2330:34] - node _T_2025 = bits(_T_2024, 0, 0) @[dec_tlu_ctl.scala 2330:62] - node _T_2026 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2330:94] - node _T_2027 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2332:34] - node _T_2028 = bits(_T_2027, 0, 0) @[dec_tlu_ctl.scala 2332:62] - node _T_2029 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2333:34] - node _T_2030 = bits(_T_2029, 0, 0) @[dec_tlu_ctl.scala 2333:62] - node _T_2031 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2334:34] - node _T_2032 = bits(_T_2031, 0, 0) @[dec_tlu_ctl.scala 2334:62] - node _T_2033 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2335:34] - node _T_2034 = bits(_T_2033, 0, 0) @[dec_tlu_ctl.scala 2335:62] - node _T_2035 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2336:34] - node _T_2036 = bits(_T_2035, 0, 0) @[dec_tlu_ctl.scala 2336:62] + node _T_1867 = and(_T_1585, _T_1866) @[dec_tlu_ctl.scala 2274:44] + mhpmc_inc_r[2] <= _T_1867 @[dec_tlu_ctl.scala 2274:19] + node _T_1868 = bits(mcountinhibit, 6, 6) @[dec_tlu_ctl.scala 2274:38] + node _T_1869 = not(_T_1868) @[dec_tlu_ctl.scala 2274:24] + node _T_1870 = eq(mhpme_vec[3], UInt<1>("h01")) @[dec_tlu_ctl.scala 2275:34] + node _T_1871 = bits(_T_1870, 0, 0) @[dec_tlu_ctl.scala 2275:62] + node _T_1872 = eq(mhpme_vec[3], UInt<2>("h02")) @[dec_tlu_ctl.scala 2276:34] + node _T_1873 = bits(_T_1872, 0, 0) @[dec_tlu_ctl.scala 2276:62] + node _T_1874 = eq(mhpme_vec[3], UInt<2>("h03")) @[dec_tlu_ctl.scala 2277:34] + node _T_1875 = bits(_T_1874, 0, 0) @[dec_tlu_ctl.scala 2277:62] + node _T_1876 = eq(mhpme_vec[3], UInt<3>("h04")) @[dec_tlu_ctl.scala 2278:34] + node _T_1877 = bits(_T_1876, 0, 0) @[dec_tlu_ctl.scala 2278:62] + node _T_1878 = not(io.illegal_r) @[dec_tlu_ctl.scala 2278:96] + node _T_1879 = and(io.tlu_i0_commit_cmt, _T_1878) @[dec_tlu_ctl.scala 2278:94] + node _T_1880 = eq(mhpme_vec[3], UInt<3>("h05")) @[dec_tlu_ctl.scala 2279:34] + node _T_1881 = bits(_T_1880, 0, 0) @[dec_tlu_ctl.scala 2279:62] + node _T_1882 = not(io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2279:96] + node _T_1883 = and(io.tlu_i0_commit_cmt, _T_1882) @[dec_tlu_ctl.scala 2279:94] + node _T_1884 = not(io.illegal_r) @[dec_tlu_ctl.scala 2279:117] + node _T_1885 = and(_T_1883, _T_1884) @[dec_tlu_ctl.scala 2279:115] + node _T_1886 = eq(mhpme_vec[3], UInt<3>("h06")) @[dec_tlu_ctl.scala 2280:34] + node _T_1887 = bits(_T_1886, 0, 0) @[dec_tlu_ctl.scala 2280:62] + node _T_1888 = and(io.tlu_i0_commit_cmt, io.exu_pmu_i0_pc4) @[dec_tlu_ctl.scala 2280:94] + node _T_1889 = not(io.illegal_r) @[dec_tlu_ctl.scala 2280:117] + node _T_1890 = and(_T_1888, _T_1889) @[dec_tlu_ctl.scala 2280:115] + node _T_1891 = eq(mhpme_vec[3], UInt<3>("h07")) @[dec_tlu_ctl.scala 2281:34] + node _T_1892 = bits(_T_1891, 0, 0) @[dec_tlu_ctl.scala 2281:62] + node _T_1893 = eq(mhpme_vec[3], UInt<4>("h08")) @[dec_tlu_ctl.scala 2282:34] + node _T_1894 = bits(_T_1893, 0, 0) @[dec_tlu_ctl.scala 2282:62] + node _T_1895 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2283:34] + node _T_1896 = bits(_T_1895, 0, 0) @[dec_tlu_ctl.scala 2283:62] + node _T_1897 = eq(mhpme_vec[3], UInt<4>("h09")) @[dec_tlu_ctl.scala 2284:34] + node _T_1898 = bits(_T_1897, 0, 0) @[dec_tlu_ctl.scala 2284:62] + node _T_1899 = eq(pmu_i0_itype_qual, UInt<4>("h01")) @[dec_tlu_ctl.scala 2284:91] + node _T_1900 = eq(mhpme_vec[3], UInt<4>("h0a")) @[dec_tlu_ctl.scala 2285:34] + node _T_1901 = bits(_T_1900, 0, 0) @[dec_tlu_ctl.scala 2285:62] + node _T_1902 = and(io.dec_tlu_packet_r.pmu_divide, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2285:105] + node _T_1903 = eq(mhpme_vec[3], UInt<4>("h0b")) @[dec_tlu_ctl.scala 2286:34] + node _T_1904 = bits(_T_1903, 0, 0) @[dec_tlu_ctl.scala 2286:62] + node _T_1905 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2286:91] + node _T_1906 = eq(mhpme_vec[3], UInt<4>("h0c")) @[dec_tlu_ctl.scala 2287:34] + node _T_1907 = bits(_T_1906, 0, 0) @[dec_tlu_ctl.scala 2287:62] + node _T_1908 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2287:91] + node _T_1909 = eq(mhpme_vec[3], UInt<4>("h0d")) @[dec_tlu_ctl.scala 2288:34] + node _T_1910 = bits(_T_1909, 0, 0) @[dec_tlu_ctl.scala 2288:62] + node _T_1911 = eq(pmu_i0_itype_qual, UInt<4>("h02")) @[dec_tlu_ctl.scala 2288:91] + node _T_1912 = and(_T_1911, io.dec_tlu_packet_r.pmu_lsu_misaligned) @[dec_tlu_ctl.scala 2288:100] + node _T_1913 = eq(mhpme_vec[3], UInt<4>("h0e")) @[dec_tlu_ctl.scala 2289:34] + node _T_1914 = bits(_T_1913, 0, 0) @[dec_tlu_ctl.scala 2289:62] + node _T_1915 = eq(pmu_i0_itype_qual, UInt<4>("h03")) @[dec_tlu_ctl.scala 2289:91] + node _T_1916 = bits(io.dec_tlu_packet_r.pmu_lsu_misaligned, 0, 0) @[dec_tlu_ctl.scala 2289:142] + node _T_1917 = and(_T_1915, _T_1916) @[dec_tlu_ctl.scala 2289:101] + node _T_1918 = eq(mhpme_vec[3], UInt<4>("h0f")) @[dec_tlu_ctl.scala 2290:34] + node _T_1919 = bits(_T_1918, 0, 0) @[dec_tlu_ctl.scala 2290:59] + node _T_1920 = eq(pmu_i0_itype_qual, UInt<4>("h04")) @[dec_tlu_ctl.scala 2290:89] + node _T_1921 = eq(mhpme_vec[3], UInt<5>("h010")) @[dec_tlu_ctl.scala 2291:34] + node _T_1922 = bits(_T_1921, 0, 0) @[dec_tlu_ctl.scala 2291:59] + node _T_1923 = eq(pmu_i0_itype_qual, UInt<4>("h05")) @[dec_tlu_ctl.scala 2291:89] + node _T_1924 = eq(mhpme_vec[3], UInt<5>("h012")) @[dec_tlu_ctl.scala 2292:34] + node _T_1925 = bits(_T_1924, 0, 0) @[dec_tlu_ctl.scala 2292:59] + node _T_1926 = eq(pmu_i0_itype_qual, UInt<4>("h06")) @[dec_tlu_ctl.scala 2292:89] + node _T_1927 = eq(mhpme_vec[3], UInt<5>("h011")) @[dec_tlu_ctl.scala 2293:34] + node _T_1928 = bits(_T_1927, 0, 0) @[dec_tlu_ctl.scala 2293:59] + node _T_1929 = eq(pmu_i0_itype_qual, UInt<4>("h07")) @[dec_tlu_ctl.scala 2293:89] + node _T_1930 = eq(mhpme_vec[3], UInt<5>("h013")) @[dec_tlu_ctl.scala 2294:34] + node _T_1931 = bits(_T_1930, 0, 0) @[dec_tlu_ctl.scala 2294:59] + node _T_1932 = eq(pmu_i0_itype_qual, UInt<4>("h08")) @[dec_tlu_ctl.scala 2294:89] + node _T_1933 = eq(mhpme_vec[3], UInt<5>("h014")) @[dec_tlu_ctl.scala 2295:34] + node _T_1934 = bits(_T_1933, 0, 0) @[dec_tlu_ctl.scala 2295:59] + node _T_1935 = eq(pmu_i0_itype_qual, UInt<4>("h09")) @[dec_tlu_ctl.scala 2295:89] + node _T_1936 = eq(mhpme_vec[3], UInt<5>("h015")) @[dec_tlu_ctl.scala 2296:34] + node _T_1937 = bits(_T_1936, 0, 0) @[dec_tlu_ctl.scala 2296:59] + node _T_1938 = eq(pmu_i0_itype_qual, UInt<4>("h0a")) @[dec_tlu_ctl.scala 2296:89] + node _T_1939 = eq(mhpme_vec[3], UInt<5>("h016")) @[dec_tlu_ctl.scala 2297:34] + node _T_1940 = bits(_T_1939, 0, 0) @[dec_tlu_ctl.scala 2297:59] + node _T_1941 = eq(pmu_i0_itype_qual, UInt<4>("h0b")) @[dec_tlu_ctl.scala 2297:89] + node _T_1942 = eq(mhpme_vec[3], UInt<5>("h017")) @[dec_tlu_ctl.scala 2298:34] + node _T_1943 = bits(_T_1942, 0, 0) @[dec_tlu_ctl.scala 2298:59] + node _T_1944 = eq(pmu_i0_itype_qual, UInt<4>("h0c")) @[dec_tlu_ctl.scala 2298:89] + node _T_1945 = eq(mhpme_vec[3], UInt<5>("h018")) @[dec_tlu_ctl.scala 2299:34] + node _T_1946 = bits(_T_1945, 0, 0) @[dec_tlu_ctl.scala 2299:59] + node _T_1947 = eq(pmu_i0_itype_qual, UInt<4>("h0d")) @[dec_tlu_ctl.scala 2299:89] + node _T_1948 = eq(pmu_i0_itype_qual, UInt<4>("h0e")) @[dec_tlu_ctl.scala 2299:122] + node _T_1949 = or(_T_1947, _T_1948) @[dec_tlu_ctl.scala 2299:101] + node _T_1950 = eq(mhpme_vec[3], UInt<5>("h019")) @[dec_tlu_ctl.scala 2300:34] + node _T_1951 = bits(_T_1950, 0, 0) @[dec_tlu_ctl.scala 2300:62] + node _T_1952 = and(io.exu_pmu_i0_br_misp, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2300:95] + node _T_1953 = eq(mhpme_vec[3], UInt<5>("h01a")) @[dec_tlu_ctl.scala 2301:34] + node _T_1954 = bits(_T_1953, 0, 0) @[dec_tlu_ctl.scala 2301:62] + node _T_1955 = and(io.exu_pmu_i0_br_ataken, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2301:97] + node _T_1956 = eq(mhpme_vec[3], UInt<5>("h01b")) @[dec_tlu_ctl.scala 2302:34] + node _T_1957 = bits(_T_1956, 0, 0) @[dec_tlu_ctl.scala 2302:62] + node _T_1958 = and(io.dec_tlu_packet_r.pmu_i0_br_unpred, io.tlu_i0_commit_cmt) @[dec_tlu_ctl.scala 2302:110] + node _T_1959 = eq(mhpme_vec[3], UInt<5>("h01c")) @[dec_tlu_ctl.scala 2303:34] + node _T_1960 = bits(_T_1959, 0, 0) @[dec_tlu_ctl.scala 2303:62] + node _T_1961 = eq(mhpme_vec[3], UInt<5>("h01e")) @[dec_tlu_ctl.scala 2304:34] + node _T_1962 = bits(_T_1961, 0, 0) @[dec_tlu_ctl.scala 2304:62] + node _T_1963 = eq(mhpme_vec[3], UInt<5>("h01f")) @[dec_tlu_ctl.scala 2305:34] + node _T_1964 = bits(_T_1963, 0, 0) @[dec_tlu_ctl.scala 2305:62] + node _T_1965 = eq(mhpme_vec[3], UInt<6>("h020")) @[dec_tlu_ctl.scala 2306:34] + node _T_1966 = bits(_T_1965, 0, 0) @[dec_tlu_ctl.scala 2306:62] + node _T_1967 = eq(mhpme_vec[3], UInt<6>("h022")) @[dec_tlu_ctl.scala 2307:34] + node _T_1968 = bits(_T_1967, 0, 0) @[dec_tlu_ctl.scala 2307:62] + node _T_1969 = eq(mhpme_vec[3], UInt<6>("h023")) @[dec_tlu_ctl.scala 2308:34] + node _T_1970 = bits(_T_1969, 0, 0) @[dec_tlu_ctl.scala 2308:62] + node _T_1971 = eq(mhpme_vec[3], UInt<6>("h024")) @[dec_tlu_ctl.scala 2309:34] + node _T_1972 = bits(_T_1971, 0, 0) @[dec_tlu_ctl.scala 2309:62] + node _T_1973 = eq(mhpme_vec[3], UInt<6>("h025")) @[dec_tlu_ctl.scala 2310:34] + node _T_1974 = bits(_T_1973, 0, 0) @[dec_tlu_ctl.scala 2310:62] + node _T_1975 = or(io.i0_exception_valid_r, io.i0_trigger_hit_r) @[dec_tlu_ctl.scala 2310:98] + node _T_1976 = or(_T_1975, io.lsu_exc_valid_r) @[dec_tlu_ctl.scala 2310:120] + node _T_1977 = eq(mhpme_vec[3], UInt<6>("h026")) @[dec_tlu_ctl.scala 2311:34] + node _T_1978 = bits(_T_1977, 0, 0) @[dec_tlu_ctl.scala 2311:62] + node _T_1979 = or(io.take_timer_int, io.take_int_timer0_int) @[dec_tlu_ctl.scala 2311:92] + node _T_1980 = or(_T_1979, io.take_int_timer1_int) @[dec_tlu_ctl.scala 2311:117] + node _T_1981 = eq(mhpme_vec[3], UInt<6>("h027")) @[dec_tlu_ctl.scala 2312:34] + node _T_1982 = bits(_T_1981, 0, 0) @[dec_tlu_ctl.scala 2312:62] + node _T_1983 = eq(mhpme_vec[3], UInt<6>("h028")) @[dec_tlu_ctl.scala 2313:34] + node _T_1984 = bits(_T_1983, 0, 0) @[dec_tlu_ctl.scala 2313:62] + node _T_1985 = eq(mhpme_vec[3], UInt<6>("h029")) @[dec_tlu_ctl.scala 2314:34] + node _T_1986 = bits(_T_1985, 0, 0) @[dec_tlu_ctl.scala 2314:62] + node _T_1987 = or(io.dec_tlu_br0_error_r, io.dec_tlu_br0_start_error_r) @[dec_tlu_ctl.scala 2314:97] + node _T_1988 = and(_T_1987, io.rfpc_i0_r) @[dec_tlu_ctl.scala 2314:129] + node _T_1989 = eq(mhpme_vec[3], UInt<6>("h02a")) @[dec_tlu_ctl.scala 2315:34] + node _T_1990 = bits(_T_1989, 0, 0) @[dec_tlu_ctl.scala 2315:62] + node _T_1991 = eq(mhpme_vec[3], UInt<6>("h02b")) @[dec_tlu_ctl.scala 2316:34] + node _T_1992 = bits(_T_1991, 0, 0) @[dec_tlu_ctl.scala 2316:62] + node _T_1993 = eq(mhpme_vec[3], UInt<6>("h02c")) @[dec_tlu_ctl.scala 2317:34] + node _T_1994 = bits(_T_1993, 0, 0) @[dec_tlu_ctl.scala 2317:62] + node _T_1995 = eq(mhpme_vec[3], UInt<6>("h02d")) @[dec_tlu_ctl.scala 2318:34] + node _T_1996 = bits(_T_1995, 0, 0) @[dec_tlu_ctl.scala 2318:62] + node _T_1997 = eq(mhpme_vec[3], UInt<6>("h02e")) @[dec_tlu_ctl.scala 2319:34] + node _T_1998 = bits(_T_1997, 0, 0) @[dec_tlu_ctl.scala 2319:62] + node _T_1999 = eq(mhpme_vec[3], UInt<6>("h02f")) @[dec_tlu_ctl.scala 2320:34] + node _T_2000 = bits(_T_1999, 0, 0) @[dec_tlu_ctl.scala 2320:62] + node _T_2001 = eq(mhpme_vec[3], UInt<6>("h030")) @[dec_tlu_ctl.scala 2321:34] + node _T_2002 = bits(_T_2001, 0, 0) @[dec_tlu_ctl.scala 2321:62] + node _T_2003 = eq(mhpme_vec[3], UInt<6>("h031")) @[dec_tlu_ctl.scala 2322:34] + node _T_2004 = bits(_T_2003, 0, 0) @[dec_tlu_ctl.scala 2322:62] + node _T_2005 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2322:84] + node _T_2006 = bits(_T_2005, 0, 0) @[dec_tlu_ctl.scala 2322:84] + node _T_2007 = not(_T_2006) @[dec_tlu_ctl.scala 2322:73] + node _T_2008 = eq(mhpme_vec[3], UInt<6>("h032")) @[dec_tlu_ctl.scala 2323:34] + node _T_2009 = bits(_T_2008, 0, 0) @[dec_tlu_ctl.scala 2323:62] + node _T_2010 = dshr(io.mstatus, UInt<1>("h00")) @[dec_tlu_ctl.scala 2323:84] + node _T_2011 = bits(_T_2010, 0, 0) @[dec_tlu_ctl.scala 2323:84] + node _T_2012 = not(_T_2011) @[dec_tlu_ctl.scala 2323:73] + node _T_2013 = bits(io.mip, 5, 0) @[dec_tlu_ctl.scala 2323:107] + node _T_2014 = bits(mie, 5, 0) @[dec_tlu_ctl.scala 2323:118] + node _T_2015 = and(_T_2013, _T_2014) @[dec_tlu_ctl.scala 2323:113] + node _T_2016 = orr(_T_2015) @[dec_tlu_ctl.scala 2323:125] + node _T_2017 = and(_T_2012, _T_2016) @[dec_tlu_ctl.scala 2323:98] + node _T_2018 = eq(mhpme_vec[3], UInt<6>("h036")) @[dec_tlu_ctl.scala 2324:34] + node _T_2019 = bits(_T_2018, 0, 0) @[dec_tlu_ctl.scala 2324:62] + node _T_2020 = eq(pmu_i0_itype_qual, UInt<4>("h0f")) @[dec_tlu_ctl.scala 2324:91] + node _T_2021 = eq(mhpme_vec[3], UInt<6>("h037")) @[dec_tlu_ctl.scala 2325:34] + node _T_2022 = bits(_T_2021, 0, 0) @[dec_tlu_ctl.scala 2325:62] + node _T_2023 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_load_external_r) @[dec_tlu_ctl.scala 2325:94] + node _T_2024 = eq(mhpme_vec[3], UInt<6>("h038")) @[dec_tlu_ctl.scala 2326:34] + node _T_2025 = bits(_T_2024, 0, 0) @[dec_tlu_ctl.scala 2326:62] + node _T_2026 = and(io.tlu_i0_commit_cmt, io.lsu_pmu_store_external_r) @[dec_tlu_ctl.scala 2326:94] + node _T_2027 = eq(mhpme_vec[3], UInt<10>("h0200")) @[dec_tlu_ctl.scala 2328:34] + node _T_2028 = bits(_T_2027, 0, 0) @[dec_tlu_ctl.scala 2328:62] + node _T_2029 = eq(mhpme_vec[3], UInt<10>("h0201")) @[dec_tlu_ctl.scala 2329:34] + node _T_2030 = bits(_T_2029, 0, 0) @[dec_tlu_ctl.scala 2329:62] + node _T_2031 = eq(mhpme_vec[3], UInt<10>("h0202")) @[dec_tlu_ctl.scala 2330:34] + node _T_2032 = bits(_T_2031, 0, 0) @[dec_tlu_ctl.scala 2330:62] + node _T_2033 = eq(mhpme_vec[3], UInt<10>("h0203")) @[dec_tlu_ctl.scala 2331:34] + node _T_2034 = bits(_T_2033, 0, 0) @[dec_tlu_ctl.scala 2331:62] + node _T_2035 = eq(mhpme_vec[3], UInt<10>("h0204")) @[dec_tlu_ctl.scala 2332:34] + node _T_2036 = bits(_T_2035, 0, 0) @[dec_tlu_ctl.scala 2332:62] node _T_2037 = mux(_T_1871, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_2038 = mux(_T_1873, io.ifu_pmu_ic_hit, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2039 = mux(_T_1875, io.ifu_pmu_ic_miss, UInt<1>("h00")) @[Mux.scala 27:72] @@ -75539,83 +75539,83 @@ circuit quasar_wrapper : node _T_2149 = or(_T_2148, _T_2093) @[Mux.scala 27:72] wire _T_2150 : UInt<1> @[Mux.scala 27:72] _T_2150 <= _T_2149 @[Mux.scala 27:72] - node _T_2151 = and(_T_1869, _T_2150) @[dec_tlu_ctl.scala 2278:44] - mhpmc_inc_r[3] <= _T_2151 @[dec_tlu_ctl.scala 2278:19] - reg _T_2152 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2339:53] - _T_2152 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2339:53] - mhpmc_inc_r_d1[0] <= _T_2152 @[dec_tlu_ctl.scala 2339:20] - reg _T_2153 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2340:53] - _T_2153 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2340:53] - mhpmc_inc_r_d1[1] <= _T_2153 @[dec_tlu_ctl.scala 2340:20] - reg _T_2154 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2341:53] - _T_2154 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2341:53] - mhpmc_inc_r_d1[2] <= _T_2154 @[dec_tlu_ctl.scala 2341:20] - reg _T_2155 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2342:53] - _T_2155 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2342:53] - mhpmc_inc_r_d1[3] <= _T_2155 @[dec_tlu_ctl.scala 2342:20] - reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2343:56] - perfcnt_halted_d1 <= perfcnt_halted @[dec_tlu_ctl.scala 2343:56] - node _T_2156 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2346:53] - node _T_2157 = and(io.dec_tlu_dbg_halted, _T_2156) @[dec_tlu_ctl.scala 2346:44] - node _T_2158 = or(_T_2157, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2346:67] - perfcnt_halted <= _T_2158 @[dec_tlu_ctl.scala 2346:17] - node _T_2159 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2347:70] - node _T_2160 = and(io.dec_tlu_dbg_halted, _T_2159) @[dec_tlu_ctl.scala 2347:61] - node _T_2161 = not(_T_2160) @[dec_tlu_ctl.scala 2347:37] + node _T_2151 = and(_T_1869, _T_2150) @[dec_tlu_ctl.scala 2274:44] + mhpmc_inc_r[3] <= _T_2151 @[dec_tlu_ctl.scala 2274:19] + reg _T_2152 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2335:53] + _T_2152 <= mhpmc_inc_r[0] @[dec_tlu_ctl.scala 2335:53] + mhpmc_inc_r_d1[0] <= _T_2152 @[dec_tlu_ctl.scala 2335:20] + reg _T_2153 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2336:53] + _T_2153 <= mhpmc_inc_r[1] @[dec_tlu_ctl.scala 2336:53] + mhpmc_inc_r_d1[1] <= _T_2153 @[dec_tlu_ctl.scala 2336:20] + reg _T_2154 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2337:53] + _T_2154 <= mhpmc_inc_r[2] @[dec_tlu_ctl.scala 2337:53] + mhpmc_inc_r_d1[2] <= _T_2154 @[dec_tlu_ctl.scala 2337:20] + reg _T_2155 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2338:53] + _T_2155 <= mhpmc_inc_r[3] @[dec_tlu_ctl.scala 2338:53] + mhpmc_inc_r_d1[3] <= _T_2155 @[dec_tlu_ctl.scala 2338:20] + reg perfcnt_halted_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2339:56] + perfcnt_halted_d1 <= perfcnt_halted @[dec_tlu_ctl.scala 2339:56] + node _T_2156 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2342:53] + node _T_2157 = and(io.dec_tlu_dbg_halted, _T_2156) @[dec_tlu_ctl.scala 2342:44] + node _T_2158 = or(_T_2157, io.dec_tlu_pmu_fw_halted) @[dec_tlu_ctl.scala 2342:67] + perfcnt_halted <= _T_2158 @[dec_tlu_ctl.scala 2342:17] + node _T_2159 = bits(io.dcsr, 10, 10) @[dec_tlu_ctl.scala 2343:70] + node _T_2160 = and(io.dec_tlu_dbg_halted, _T_2159) @[dec_tlu_ctl.scala 2343:61] + node _T_2161 = not(_T_2160) @[dec_tlu_ctl.scala 2343:37] node _T_2162 = bits(_T_2161, 0, 0) @[Bitwise.scala 72:15] node _T_2163 = mux(_T_2162, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_2164 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2347:104] - node _T_2165 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2347:120] - node _T_2166 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2347:136] - node _T_2167 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2347:152] + node _T_2164 = bits(mhpme_vec[3], 9, 9) @[dec_tlu_ctl.scala 2343:104] + node _T_2165 = bits(mhpme_vec[2], 9, 9) @[dec_tlu_ctl.scala 2343:120] + node _T_2166 = bits(mhpme_vec[1], 9, 9) @[dec_tlu_ctl.scala 2343:136] + node _T_2167 = bits(mhpme_vec[0], 9, 9) @[dec_tlu_ctl.scala 2343:152] node _T_2168 = cat(_T_2166, _T_2167) @[Cat.scala 29:58] node _T_2169 = cat(_T_2164, _T_2165) @[Cat.scala 29:58] node _T_2170 = cat(_T_2169, _T_2168) @[Cat.scala 29:58] - node perfcnt_during_sleep = and(_T_2163, _T_2170) @[dec_tlu_ctl.scala 2347:86] - node _T_2171 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2349:88] - node _T_2172 = not(_T_2171) @[dec_tlu_ctl.scala 2349:67] - node _T_2173 = and(perfcnt_halted_d1, _T_2172) @[dec_tlu_ctl.scala 2349:65] - node _T_2174 = not(_T_2173) @[dec_tlu_ctl.scala 2349:45] - node _T_2175 = and(mhpmc_inc_r_d1[0], _T_2174) @[dec_tlu_ctl.scala 2349:43] - io.dec_tlu_perfcnt0 <= _T_2175 @[dec_tlu_ctl.scala 2349:22] - node _T_2176 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2350:88] - node _T_2177 = not(_T_2176) @[dec_tlu_ctl.scala 2350:67] - node _T_2178 = and(perfcnt_halted_d1, _T_2177) @[dec_tlu_ctl.scala 2350:65] - node _T_2179 = not(_T_2178) @[dec_tlu_ctl.scala 2350:45] - node _T_2180 = and(mhpmc_inc_r_d1[1], _T_2179) @[dec_tlu_ctl.scala 2350:43] - io.dec_tlu_perfcnt1 <= _T_2180 @[dec_tlu_ctl.scala 2350:22] - node _T_2181 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2351:88] - node _T_2182 = not(_T_2181) @[dec_tlu_ctl.scala 2351:67] - node _T_2183 = and(perfcnt_halted_d1, _T_2182) @[dec_tlu_ctl.scala 2351:65] - node _T_2184 = not(_T_2183) @[dec_tlu_ctl.scala 2351:45] - node _T_2185 = and(mhpmc_inc_r_d1[2], _T_2184) @[dec_tlu_ctl.scala 2351:43] - io.dec_tlu_perfcnt2 <= _T_2185 @[dec_tlu_ctl.scala 2351:22] - node _T_2186 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2352:88] - node _T_2187 = not(_T_2186) @[dec_tlu_ctl.scala 2352:67] - node _T_2188 = and(perfcnt_halted_d1, _T_2187) @[dec_tlu_ctl.scala 2352:65] - node _T_2189 = not(_T_2188) @[dec_tlu_ctl.scala 2352:45] - node _T_2190 = and(mhpmc_inc_r_d1[3], _T_2189) @[dec_tlu_ctl.scala 2352:43] - io.dec_tlu_perfcnt3 <= _T_2190 @[dec_tlu_ctl.scala 2352:22] - node _T_2191 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2358:65] - node _T_2192 = eq(_T_2191, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2358:72] - node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2192) @[dec_tlu_ctl.scala 2358:43] - node _T_2193 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2359:23] - node _T_2194 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2359:61] - node _T_2195 = or(_T_2193, _T_2194) @[dec_tlu_ctl.scala 2359:39] - node _T_2196 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2359:86] - node mhpmc3_wr_en1 = and(_T_2195, _T_2196) @[dec_tlu_ctl.scala 2359:66] - node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2360:36] - node _T_2197 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2363:28] - node _T_2198 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2363:41] + node perfcnt_during_sleep = and(_T_2163, _T_2170) @[dec_tlu_ctl.scala 2343:86] + node _T_2171 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2345:88] + node _T_2172 = not(_T_2171) @[dec_tlu_ctl.scala 2345:67] + node _T_2173 = and(perfcnt_halted_d1, _T_2172) @[dec_tlu_ctl.scala 2345:65] + node _T_2174 = not(_T_2173) @[dec_tlu_ctl.scala 2345:45] + node _T_2175 = and(mhpmc_inc_r_d1[0], _T_2174) @[dec_tlu_ctl.scala 2345:43] + io.dec_tlu_perfcnt0 <= _T_2175 @[dec_tlu_ctl.scala 2345:22] + node _T_2176 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2346:88] + node _T_2177 = not(_T_2176) @[dec_tlu_ctl.scala 2346:67] + node _T_2178 = and(perfcnt_halted_d1, _T_2177) @[dec_tlu_ctl.scala 2346:65] + node _T_2179 = not(_T_2178) @[dec_tlu_ctl.scala 2346:45] + node _T_2180 = and(mhpmc_inc_r_d1[1], _T_2179) @[dec_tlu_ctl.scala 2346:43] + io.dec_tlu_perfcnt1 <= _T_2180 @[dec_tlu_ctl.scala 2346:22] + node _T_2181 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2347:88] + node _T_2182 = not(_T_2181) @[dec_tlu_ctl.scala 2347:67] + node _T_2183 = and(perfcnt_halted_d1, _T_2182) @[dec_tlu_ctl.scala 2347:65] + node _T_2184 = not(_T_2183) @[dec_tlu_ctl.scala 2347:45] + node _T_2185 = and(mhpmc_inc_r_d1[2], _T_2184) @[dec_tlu_ctl.scala 2347:43] + io.dec_tlu_perfcnt2 <= _T_2185 @[dec_tlu_ctl.scala 2347:22] + node _T_2186 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2348:88] + node _T_2187 = not(_T_2186) @[dec_tlu_ctl.scala 2348:67] + node _T_2188 = and(perfcnt_halted_d1, _T_2187) @[dec_tlu_ctl.scala 2348:65] + node _T_2189 = not(_T_2188) @[dec_tlu_ctl.scala 2348:45] + node _T_2190 = and(mhpmc_inc_r_d1[3], _T_2189) @[dec_tlu_ctl.scala 2348:43] + io.dec_tlu_perfcnt3 <= _T_2190 @[dec_tlu_ctl.scala 2348:22] + node _T_2191 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2354:65] + node _T_2192 = eq(_T_2191, UInt<12>("h0b03")) @[dec_tlu_ctl.scala 2354:72] + node mhpmc3_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2192) @[dec_tlu_ctl.scala 2354:43] + node _T_2193 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2355:23] + node _T_2194 = bits(perfcnt_during_sleep, 0, 0) @[dec_tlu_ctl.scala 2355:61] + node _T_2195 = or(_T_2193, _T_2194) @[dec_tlu_ctl.scala 2355:39] + node _T_2196 = orr(mhpmc_inc_r[0]) @[dec_tlu_ctl.scala 2355:86] + node mhpmc3_wr_en1 = and(_T_2195, _T_2196) @[dec_tlu_ctl.scala 2355:66] + node mhpmc3_wr_en = or(mhpmc3_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2356:36] + node _T_2197 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2359:28] + node _T_2198 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2359:41] node _T_2199 = cat(_T_2197, _T_2198) @[Cat.scala 29:58] node _T_2200 = cat(UInt<63>("h00"), mhpmc_inc_r[0]) @[Cat.scala 29:58] - node _T_2201 = add(_T_2199, _T_2200) @[dec_tlu_ctl.scala 2363:49] - node _T_2202 = tail(_T_2201, 1) @[dec_tlu_ctl.scala 2363:49] - mhpmc3_incr <= _T_2202 @[dec_tlu_ctl.scala 2363:14] - node _T_2203 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2364:36] - node _T_2204 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2364:76] - node mhpmc3_ns = mux(_T_2203, io.dec_csr_wrdata_r, _T_2204) @[dec_tlu_ctl.scala 2364:21] - node _T_2205 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2366:42] + node _T_2201 = add(_T_2199, _T_2200) @[dec_tlu_ctl.scala 2359:49] + node _T_2202 = tail(_T_2201, 1) @[dec_tlu_ctl.scala 2359:49] + mhpmc3_incr <= _T_2202 @[dec_tlu_ctl.scala 2359:14] + node _T_2203 = bits(mhpmc3_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2360:36] + node _T_2204 = bits(mhpmc3_incr, 31, 0) @[dec_tlu_ctl.scala 2360:76] + node mhpmc3_ns = mux(_T_2203, io.dec_csr_wrdata_r, _T_2204) @[dec_tlu_ctl.scala 2360:21] + node _T_2205 = bits(mhpmc3_wr_en, 0, 0) @[dec_tlu_ctl.scala 2362:42] inst rvclkhdr_26 of rvclkhdr_746 @[lib.scala 352:23] rvclkhdr_26.clock <= clock rvclkhdr_26.reset <= reset @@ -75624,15 +75624,15 @@ circuit quasar_wrapper : rvclkhdr_26.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_2206 : UInt, rvclkhdr_26.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_2206 <= mhpmc3_ns @[lib.scala 358:16] - mhpmc3 <= _T_2206 @[dec_tlu_ctl.scala 2366:9] - node _T_2207 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2368:66] - node _T_2208 = eq(_T_2207, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2368:73] - node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2208) @[dec_tlu_ctl.scala 2368:44] - node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2369:38] - node _T_2209 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2370:38] - node _T_2210 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2370:78] - node mhpmc3h_ns = mux(_T_2209, io.dec_csr_wrdata_r, _T_2210) @[dec_tlu_ctl.scala 2370:22] - node _T_2211 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2372:46] + mhpmc3 <= _T_2206 @[dec_tlu_ctl.scala 2362:9] + node _T_2207 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2364:66] + node _T_2208 = eq(_T_2207, UInt<12>("h0b83")) @[dec_tlu_ctl.scala 2364:73] + node mhpmc3h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2208) @[dec_tlu_ctl.scala 2364:44] + node mhpmc3h_wr_en = or(mhpmc3h_wr_en0, mhpmc3_wr_en1) @[dec_tlu_ctl.scala 2365:38] + node _T_2209 = bits(mhpmc3h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2366:38] + node _T_2210 = bits(mhpmc3_incr, 63, 32) @[dec_tlu_ctl.scala 2366:78] + node mhpmc3h_ns = mux(_T_2209, io.dec_csr_wrdata_r, _T_2210) @[dec_tlu_ctl.scala 2366:22] + node _T_2211 = bits(mhpmc3h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2368:46] inst rvclkhdr_27 of rvclkhdr_747 @[lib.scala 352:23] rvclkhdr_27.clock <= clock rvclkhdr_27.reset <= reset @@ -75641,28 +75641,28 @@ circuit quasar_wrapper : rvclkhdr_27.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_2212 : UInt, rvclkhdr_27.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_2212 <= mhpmc3h_ns @[lib.scala 358:16] - mhpmc3h <= _T_2212 @[dec_tlu_ctl.scala 2372:10] - node _T_2213 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2377:65] - node _T_2214 = eq(_T_2213, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2377:72] - node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2214) @[dec_tlu_ctl.scala 2377:43] - node _T_2215 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2378:23] - node _T_2216 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2378:61] - node _T_2217 = or(_T_2215, _T_2216) @[dec_tlu_ctl.scala 2378:39] - node _T_2218 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2378:86] - node mhpmc4_wr_en1 = and(_T_2217, _T_2218) @[dec_tlu_ctl.scala 2378:66] - node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2379:36] - node _T_2219 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2383:28] - node _T_2220 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2383:41] + mhpmc3h <= _T_2212 @[dec_tlu_ctl.scala 2368:10] + node _T_2213 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2373:65] + node _T_2214 = eq(_T_2213, UInt<12>("h0b04")) @[dec_tlu_ctl.scala 2373:72] + node mhpmc4_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2214) @[dec_tlu_ctl.scala 2373:43] + node _T_2215 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2374:23] + node _T_2216 = bits(perfcnt_during_sleep, 1, 1) @[dec_tlu_ctl.scala 2374:61] + node _T_2217 = or(_T_2215, _T_2216) @[dec_tlu_ctl.scala 2374:39] + node _T_2218 = orr(mhpmc_inc_r[1]) @[dec_tlu_ctl.scala 2374:86] + node mhpmc4_wr_en1 = and(_T_2217, _T_2218) @[dec_tlu_ctl.scala 2374:66] + node mhpmc4_wr_en = or(mhpmc4_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2375:36] + node _T_2219 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2379:28] + node _T_2220 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2379:41] node _T_2221 = cat(_T_2219, _T_2220) @[Cat.scala 29:58] node _T_2222 = cat(UInt<63>("h00"), mhpmc_inc_r[1]) @[Cat.scala 29:58] - node _T_2223 = add(_T_2221, _T_2222) @[dec_tlu_ctl.scala 2383:49] - node _T_2224 = tail(_T_2223, 1) @[dec_tlu_ctl.scala 2383:49] - mhpmc4_incr <= _T_2224 @[dec_tlu_ctl.scala 2383:14] - node _T_2225 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2384:36] - node _T_2226 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2384:63] - node _T_2227 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2384:82] - node mhpmc4_ns = mux(_T_2225, _T_2226, _T_2227) @[dec_tlu_ctl.scala 2384:21] - node _T_2228 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2385:43] + node _T_2223 = add(_T_2221, _T_2222) @[dec_tlu_ctl.scala 2379:49] + node _T_2224 = tail(_T_2223, 1) @[dec_tlu_ctl.scala 2379:49] + mhpmc4_incr <= _T_2224 @[dec_tlu_ctl.scala 2379:14] + node _T_2225 = bits(mhpmc4_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2380:36] + node _T_2226 = bits(io.dec_csr_wrdata_r, 31, 0) @[dec_tlu_ctl.scala 2380:63] + node _T_2227 = bits(mhpmc4_incr, 31, 0) @[dec_tlu_ctl.scala 2380:82] + node mhpmc4_ns = mux(_T_2225, _T_2226, _T_2227) @[dec_tlu_ctl.scala 2380:21] + node _T_2228 = bits(mhpmc4_wr_en, 0, 0) @[dec_tlu_ctl.scala 2381:43] inst rvclkhdr_28 of rvclkhdr_748 @[lib.scala 352:23] rvclkhdr_28.clock <= clock rvclkhdr_28.reset <= reset @@ -75671,15 +75671,15 @@ circuit quasar_wrapper : rvclkhdr_28.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_2229 : UInt, rvclkhdr_28.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_2229 <= mhpmc4_ns @[lib.scala 358:16] - mhpmc4 <= _T_2229 @[dec_tlu_ctl.scala 2385:9] - node _T_2230 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2387:66] - node _T_2231 = eq(_T_2230, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2387:73] - node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2231) @[dec_tlu_ctl.scala 2387:44] - node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2388:38] - node _T_2232 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2389:38] - node _T_2233 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2389:78] - node mhpmc4h_ns = mux(_T_2232, io.dec_csr_wrdata_r, _T_2233) @[dec_tlu_ctl.scala 2389:22] - node _T_2234 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2390:46] + mhpmc4 <= _T_2229 @[dec_tlu_ctl.scala 2381:9] + node _T_2230 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2383:66] + node _T_2231 = eq(_T_2230, UInt<12>("h0b84")) @[dec_tlu_ctl.scala 2383:73] + node mhpmc4h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2231) @[dec_tlu_ctl.scala 2383:44] + node mhpmc4h_wr_en = or(mhpmc4h_wr_en0, mhpmc4_wr_en1) @[dec_tlu_ctl.scala 2384:38] + node _T_2232 = bits(mhpmc4h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2385:38] + node _T_2233 = bits(mhpmc4_incr, 63, 32) @[dec_tlu_ctl.scala 2385:78] + node mhpmc4h_ns = mux(_T_2232, io.dec_csr_wrdata_r, _T_2233) @[dec_tlu_ctl.scala 2385:22] + node _T_2234 = bits(mhpmc4h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2386:46] inst rvclkhdr_29 of rvclkhdr_749 @[lib.scala 352:23] rvclkhdr_29.clock <= clock rvclkhdr_29.reset <= reset @@ -75688,27 +75688,27 @@ circuit quasar_wrapper : rvclkhdr_29.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_2235 : UInt, rvclkhdr_29.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_2235 <= mhpmc4h_ns @[lib.scala 358:16] - mhpmc4h <= _T_2235 @[dec_tlu_ctl.scala 2390:10] - node _T_2236 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2396:65] - node _T_2237 = eq(_T_2236, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2396:72] - node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2237) @[dec_tlu_ctl.scala 2396:43] - node _T_2238 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2397:23] - node _T_2239 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2397:61] - node _T_2240 = or(_T_2238, _T_2239) @[dec_tlu_ctl.scala 2397:39] - node _T_2241 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2397:86] - node mhpmc5_wr_en1 = and(_T_2240, _T_2241) @[dec_tlu_ctl.scala 2397:66] - node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2398:36] - node _T_2242 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2400:28] - node _T_2243 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2400:41] + mhpmc4h <= _T_2235 @[dec_tlu_ctl.scala 2386:10] + node _T_2236 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2392:65] + node _T_2237 = eq(_T_2236, UInt<12>("h0b05")) @[dec_tlu_ctl.scala 2392:72] + node mhpmc5_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2237) @[dec_tlu_ctl.scala 2392:43] + node _T_2238 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2393:23] + node _T_2239 = bits(perfcnt_during_sleep, 2, 2) @[dec_tlu_ctl.scala 2393:61] + node _T_2240 = or(_T_2238, _T_2239) @[dec_tlu_ctl.scala 2393:39] + node _T_2241 = orr(mhpmc_inc_r[2]) @[dec_tlu_ctl.scala 2393:86] + node mhpmc5_wr_en1 = and(_T_2240, _T_2241) @[dec_tlu_ctl.scala 2393:66] + node mhpmc5_wr_en = or(mhpmc5_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2394:36] + node _T_2242 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2396:28] + node _T_2243 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2396:41] node _T_2244 = cat(_T_2242, _T_2243) @[Cat.scala 29:58] node _T_2245 = cat(UInt<63>("h00"), mhpmc_inc_r[2]) @[Cat.scala 29:58] - node _T_2246 = add(_T_2244, _T_2245) @[dec_tlu_ctl.scala 2400:49] - node _T_2247 = tail(_T_2246, 1) @[dec_tlu_ctl.scala 2400:49] - mhpmc5_incr <= _T_2247 @[dec_tlu_ctl.scala 2400:14] - node _T_2248 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2401:36] - node _T_2249 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2401:76] - node mhpmc5_ns = mux(_T_2248, io.dec_csr_wrdata_r, _T_2249) @[dec_tlu_ctl.scala 2401:21] - node _T_2250 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2403:43] + node _T_2246 = add(_T_2244, _T_2245) @[dec_tlu_ctl.scala 2396:49] + node _T_2247 = tail(_T_2246, 1) @[dec_tlu_ctl.scala 2396:49] + mhpmc5_incr <= _T_2247 @[dec_tlu_ctl.scala 2396:14] + node _T_2248 = bits(mhpmc5_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2397:36] + node _T_2249 = bits(mhpmc5_incr, 31, 0) @[dec_tlu_ctl.scala 2397:76] + node mhpmc5_ns = mux(_T_2248, io.dec_csr_wrdata_r, _T_2249) @[dec_tlu_ctl.scala 2397:21] + node _T_2250 = bits(mhpmc5_wr_en, 0, 0) @[dec_tlu_ctl.scala 2399:43] inst rvclkhdr_30 of rvclkhdr_750 @[lib.scala 352:23] rvclkhdr_30.clock <= clock rvclkhdr_30.reset <= reset @@ -75717,15 +75717,15 @@ circuit quasar_wrapper : rvclkhdr_30.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_2251 : UInt, rvclkhdr_30.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_2251 <= mhpmc5_ns @[lib.scala 358:16] - mhpmc5 <= _T_2251 @[dec_tlu_ctl.scala 2403:9] - node _T_2252 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2405:66] - node _T_2253 = eq(_T_2252, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2405:73] - node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2253) @[dec_tlu_ctl.scala 2405:44] - node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2406:38] - node _T_2254 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2407:38] - node _T_2255 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2407:78] - node mhpmc5h_ns = mux(_T_2254, io.dec_csr_wrdata_r, _T_2255) @[dec_tlu_ctl.scala 2407:22] - node _T_2256 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2409:46] + mhpmc5 <= _T_2251 @[dec_tlu_ctl.scala 2399:9] + node _T_2252 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2401:66] + node _T_2253 = eq(_T_2252, UInt<12>("h0b85")) @[dec_tlu_ctl.scala 2401:73] + node mhpmc5h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2253) @[dec_tlu_ctl.scala 2401:44] + node mhpmc5h_wr_en = or(mhpmc5h_wr_en0, mhpmc5_wr_en1) @[dec_tlu_ctl.scala 2402:38] + node _T_2254 = bits(mhpmc5h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2403:38] + node _T_2255 = bits(mhpmc5_incr, 63, 32) @[dec_tlu_ctl.scala 2403:78] + node mhpmc5h_ns = mux(_T_2254, io.dec_csr_wrdata_r, _T_2255) @[dec_tlu_ctl.scala 2403:22] + node _T_2256 = bits(mhpmc5h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2405:46] inst rvclkhdr_31 of rvclkhdr_751 @[lib.scala 352:23] rvclkhdr_31.clock <= clock rvclkhdr_31.reset <= reset @@ -75734,27 +75734,27 @@ circuit quasar_wrapper : rvclkhdr_31.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_2257 : UInt, rvclkhdr_31.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_2257 <= mhpmc5h_ns @[lib.scala 358:16] - mhpmc5h <= _T_2257 @[dec_tlu_ctl.scala 2409:10] - node _T_2258 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2414:65] - node _T_2259 = eq(_T_2258, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2414:72] - node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2259) @[dec_tlu_ctl.scala 2414:43] - node _T_2260 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2415:23] - node _T_2261 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2415:61] - node _T_2262 = or(_T_2260, _T_2261) @[dec_tlu_ctl.scala 2415:39] - node _T_2263 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2415:86] - node mhpmc6_wr_en1 = and(_T_2262, _T_2263) @[dec_tlu_ctl.scala 2415:66] - node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2416:36] - node _T_2264 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2418:28] - node _T_2265 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2418:41] + mhpmc5h <= _T_2257 @[dec_tlu_ctl.scala 2405:10] + node _T_2258 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2410:65] + node _T_2259 = eq(_T_2258, UInt<12>("h0b06")) @[dec_tlu_ctl.scala 2410:72] + node mhpmc6_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2259) @[dec_tlu_ctl.scala 2410:43] + node _T_2260 = not(perfcnt_halted) @[dec_tlu_ctl.scala 2411:23] + node _T_2261 = bits(perfcnt_during_sleep, 3, 3) @[dec_tlu_ctl.scala 2411:61] + node _T_2262 = or(_T_2260, _T_2261) @[dec_tlu_ctl.scala 2411:39] + node _T_2263 = orr(mhpmc_inc_r[3]) @[dec_tlu_ctl.scala 2411:86] + node mhpmc6_wr_en1 = and(_T_2262, _T_2263) @[dec_tlu_ctl.scala 2411:66] + node mhpmc6_wr_en = or(mhpmc6_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2412:36] + node _T_2264 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2414:28] + node _T_2265 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2414:41] node _T_2266 = cat(_T_2264, _T_2265) @[Cat.scala 29:58] node _T_2267 = cat(UInt<63>("h00"), mhpmc_inc_r[3]) @[Cat.scala 29:58] - node _T_2268 = add(_T_2266, _T_2267) @[dec_tlu_ctl.scala 2418:49] - node _T_2269 = tail(_T_2268, 1) @[dec_tlu_ctl.scala 2418:49] - mhpmc6_incr <= _T_2269 @[dec_tlu_ctl.scala 2418:14] - node _T_2270 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2419:36] - node _T_2271 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2419:76] - node mhpmc6_ns = mux(_T_2270, io.dec_csr_wrdata_r, _T_2271) @[dec_tlu_ctl.scala 2419:21] - node _T_2272 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2421:43] + node _T_2268 = add(_T_2266, _T_2267) @[dec_tlu_ctl.scala 2414:49] + node _T_2269 = tail(_T_2268, 1) @[dec_tlu_ctl.scala 2414:49] + mhpmc6_incr <= _T_2269 @[dec_tlu_ctl.scala 2414:14] + node _T_2270 = bits(mhpmc6_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2415:36] + node _T_2271 = bits(mhpmc6_incr, 31, 0) @[dec_tlu_ctl.scala 2415:76] + node mhpmc6_ns = mux(_T_2270, io.dec_csr_wrdata_r, _T_2271) @[dec_tlu_ctl.scala 2415:21] + node _T_2272 = bits(mhpmc6_wr_en, 0, 0) @[dec_tlu_ctl.scala 2417:43] inst rvclkhdr_32 of rvclkhdr_752 @[lib.scala 352:23] rvclkhdr_32.clock <= clock rvclkhdr_32.reset <= reset @@ -75763,15 +75763,15 @@ circuit quasar_wrapper : rvclkhdr_32.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_2273 : UInt, rvclkhdr_32.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_2273 <= mhpmc6_ns @[lib.scala 358:16] - mhpmc6 <= _T_2273 @[dec_tlu_ctl.scala 2421:9] - node _T_2274 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2423:66] - node _T_2275 = eq(_T_2274, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2423:73] - node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2275) @[dec_tlu_ctl.scala 2423:44] - node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2424:38] - node _T_2276 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2425:38] - node _T_2277 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2425:78] - node mhpmc6h_ns = mux(_T_2276, io.dec_csr_wrdata_r, _T_2277) @[dec_tlu_ctl.scala 2425:22] - node _T_2278 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2427:46] + mhpmc6 <= _T_2273 @[dec_tlu_ctl.scala 2417:9] + node _T_2274 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2419:66] + node _T_2275 = eq(_T_2274, UInt<12>("h0b86")) @[dec_tlu_ctl.scala 2419:73] + node mhpmc6h_wr_en0 = and(io.dec_csr_wen_r_mod, _T_2275) @[dec_tlu_ctl.scala 2419:44] + node mhpmc6h_wr_en = or(mhpmc6h_wr_en0, mhpmc6_wr_en1) @[dec_tlu_ctl.scala 2420:38] + node _T_2276 = bits(mhpmc6h_wr_en0, 0, 0) @[dec_tlu_ctl.scala 2421:38] + node _T_2277 = bits(mhpmc6_incr, 63, 32) @[dec_tlu_ctl.scala 2421:78] + node mhpmc6h_ns = mux(_T_2276, io.dec_csr_wrdata_r, _T_2277) @[dec_tlu_ctl.scala 2421:22] + node _T_2278 = bits(mhpmc6h_wr_en, 0, 0) @[dec_tlu_ctl.scala 2423:46] inst rvclkhdr_33 of rvclkhdr_753 @[lib.scala 352:23] rvclkhdr_33.clock <= clock rvclkhdr_33.reset <= reset @@ -75780,134 +75780,134 @@ circuit quasar_wrapper : rvclkhdr_33.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_2279 : UInt, rvclkhdr_33.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_2279 <= mhpmc6h_ns @[lib.scala 358:16] - mhpmc6h <= _T_2279 @[dec_tlu_ctl.scala 2427:10] - node _T_2280 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2434:50] - node _T_2281 = gt(_T_2280, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2434:56] - node _T_2282 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2434:93] - node _T_2283 = orr(_T_2282) @[dec_tlu_ctl.scala 2434:102] - node _T_2284 = or(_T_2281, _T_2283) @[dec_tlu_ctl.scala 2434:71] - node _T_2285 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2434:141] - node event_saturate_r = mux(_T_2284, UInt<10>("h0204"), _T_2285) @[dec_tlu_ctl.scala 2434:28] - node _T_2286 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2436:63] - node _T_2287 = eq(_T_2286, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2436:70] - node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2287) @[dec_tlu_ctl.scala 2436:41] - node _T_2288 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2438:80] + mhpmc6h <= _T_2279 @[dec_tlu_ctl.scala 2423:10] + node _T_2280 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2430:50] + node _T_2281 = gt(_T_2280, UInt<10>("h0204")) @[dec_tlu_ctl.scala 2430:56] + node _T_2282 = bits(io.dec_csr_wrdata_r, 31, 10) @[dec_tlu_ctl.scala 2430:93] + node _T_2283 = orr(_T_2282) @[dec_tlu_ctl.scala 2430:102] + node _T_2284 = or(_T_2281, _T_2283) @[dec_tlu_ctl.scala 2430:71] + node _T_2285 = bits(io.dec_csr_wrdata_r, 9, 0) @[dec_tlu_ctl.scala 2430:141] + node event_saturate_r = mux(_T_2284, UInt<10>("h0204"), _T_2285) @[dec_tlu_ctl.scala 2430:28] + node _T_2286 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2432:63] + node _T_2287 = eq(_T_2286, UInt<12>("h0323")) @[dec_tlu_ctl.scala 2432:70] + node wr_mhpme3_r = and(io.dec_csr_wen_r_mod, _T_2287) @[dec_tlu_ctl.scala 2432:41] + node _T_2288 = bits(wr_mhpme3_r, 0, 0) @[dec_tlu_ctl.scala 2434:80] reg _T_2289 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_2288 : @[Reg.scala 28:19] _T_2289 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme3 <= _T_2289 @[dec_tlu_ctl.scala 2438:9] - node _T_2290 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2443:63] - node _T_2291 = eq(_T_2290, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2443:70] - node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2291) @[dec_tlu_ctl.scala 2443:41] - node _T_2292 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2444:80] + mhpme3 <= _T_2289 @[dec_tlu_ctl.scala 2434:9] + node _T_2290 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2439:63] + node _T_2291 = eq(_T_2290, UInt<12>("h0324")) @[dec_tlu_ctl.scala 2439:70] + node wr_mhpme4_r = and(io.dec_csr_wen_r_mod, _T_2291) @[dec_tlu_ctl.scala 2439:41] + node _T_2292 = bits(wr_mhpme4_r, 0, 0) @[dec_tlu_ctl.scala 2440:80] reg _T_2293 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_2292 : @[Reg.scala 28:19] _T_2293 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme4 <= _T_2293 @[dec_tlu_ctl.scala 2444:9] - node _T_2294 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2450:63] - node _T_2295 = eq(_T_2294, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2450:70] - node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2295) @[dec_tlu_ctl.scala 2450:41] - node _T_2296 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2451:80] + mhpme4 <= _T_2293 @[dec_tlu_ctl.scala 2440:9] + node _T_2294 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2446:63] + node _T_2295 = eq(_T_2294, UInt<12>("h0325")) @[dec_tlu_ctl.scala 2446:70] + node wr_mhpme5_r = and(io.dec_csr_wen_r_mod, _T_2295) @[dec_tlu_ctl.scala 2446:41] + node _T_2296 = bits(wr_mhpme5_r, 0, 0) @[dec_tlu_ctl.scala 2447:80] reg _T_2297 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_2296 : @[Reg.scala 28:19] _T_2297 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme5 <= _T_2297 @[dec_tlu_ctl.scala 2451:9] - node _T_2298 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2457:63] - node _T_2299 = eq(_T_2298, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2457:70] - node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2299) @[dec_tlu_ctl.scala 2457:41] - node _T_2300 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2458:80] + mhpme5 <= _T_2297 @[dec_tlu_ctl.scala 2447:9] + node _T_2298 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2453:63] + node _T_2299 = eq(_T_2298, UInt<12>("h0326")) @[dec_tlu_ctl.scala 2453:70] + node wr_mhpme6_r = and(io.dec_csr_wen_r_mod, _T_2299) @[dec_tlu_ctl.scala 2453:41] + node _T_2300 = bits(wr_mhpme6_r, 0, 0) @[dec_tlu_ctl.scala 2454:80] reg _T_2301 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_2300 : @[Reg.scala 28:19] _T_2301 <= event_saturate_r @[Reg.scala 28:23] skip @[Reg.scala 28:19] - mhpme6 <= _T_2301 @[dec_tlu_ctl.scala 2458:9] - node _T_2302 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2474:70] - node _T_2303 = eq(_T_2302, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2474:77] - node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2303) @[dec_tlu_ctl.scala 2474:48] - node _T_2304 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2476:54] + mhpme6 <= _T_2301 @[dec_tlu_ctl.scala 2454:9] + node _T_2302 = bits(io.dec_csr_wraddr_r, 11, 0) @[dec_tlu_ctl.scala 2470:70] + node _T_2303 = eq(_T_2302, UInt<12>("h0320")) @[dec_tlu_ctl.scala 2470:77] + node wr_mcountinhibit_r = and(io.dec_csr_wen_r_mod, _T_2303) @[dec_tlu_ctl.scala 2470:48] + node _T_2304 = bits(mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2472:54] wire temp_ncount0 : UInt<1> temp_ncount0 <= _T_2304 - node _T_2305 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2477:54] + node _T_2305 = bits(mcountinhibit, 1, 1) @[dec_tlu_ctl.scala 2473:54] wire temp_ncount1 : UInt<1> temp_ncount1 <= _T_2305 - node _T_2306 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2478:55] + node _T_2306 = bits(mcountinhibit, 6, 2) @[dec_tlu_ctl.scala 2474:55] wire temp_ncount6_2 : UInt<5> temp_ncount6_2 <= _T_2306 - node _T_2307 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2479:74] - node _T_2308 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2479:103] + node _T_2307 = bits(io.dec_csr_wrdata_r, 6, 2) @[dec_tlu_ctl.scala 2475:74] + node _T_2308 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2475:103] reg _T_2309 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_2308 : @[Reg.scala 28:19] _T_2309 <= _T_2307 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount6_2 <= _T_2309 @[dec_tlu_ctl.scala 2479:17] - node _T_2310 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2481:72] - node _T_2311 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2481:99] + temp_ncount6_2 <= _T_2309 @[dec_tlu_ctl.scala 2475:17] + node _T_2310 = bits(io.dec_csr_wrdata_r, 0, 0) @[dec_tlu_ctl.scala 2477:72] + node _T_2311 = bits(wr_mcountinhibit_r, 0, 0) @[dec_tlu_ctl.scala 2477:99] reg _T_2312 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_2311 : @[Reg.scala 28:19] _T_2312 <= _T_2310 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - temp_ncount0 <= _T_2312 @[dec_tlu_ctl.scala 2481:15] + temp_ncount0 <= _T_2312 @[dec_tlu_ctl.scala 2477:15] node _T_2313 = cat(temp_ncount6_2, UInt<1>("h00")) @[Cat.scala 29:58] node _T_2314 = cat(_T_2313, temp_ncount0) @[Cat.scala 29:58] - mcountinhibit <= _T_2314 @[dec_tlu_ctl.scala 2482:16] - node _T_2315 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2489:51] - node _T_2316 = or(_T_2315, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2489:78] - node _T_2317 = or(_T_2316, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2489:104] - node _T_2318 = or(_T_2317, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2489:130] - node _T_2319 = or(_T_2318, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2490:32] - node _T_2320 = or(_T_2319, io.clk_override) @[dec_tlu_ctl.scala 2490:59] - node _T_2321 = bits(_T_2320, 0, 0) @[dec_tlu_ctl.scala 2490:78] + mcountinhibit <= _T_2314 @[dec_tlu_ctl.scala 2478:16] + node _T_2315 = or(io.i0_valid_wb, io.exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 2485:51] + node _T_2316 = or(_T_2315, io.interrupt_valid_r_d1) @[dec_tlu_ctl.scala 2485:78] + node _T_2317 = or(_T_2316, io.dec_tlu_i0_valid_wb1) @[dec_tlu_ctl.scala 2485:104] + node _T_2318 = or(_T_2317, io.dec_tlu_i0_exc_valid_wb1) @[dec_tlu_ctl.scala 2485:130] + node _T_2319 = or(_T_2318, io.dec_tlu_int_valid_wb1) @[dec_tlu_ctl.scala 2486:32] + node _T_2320 = or(_T_2319, io.clk_override) @[dec_tlu_ctl.scala 2486:59] + node _T_2321 = bits(_T_2320, 0, 0) @[dec_tlu_ctl.scala 2486:78] inst rvclkhdr_34 of rvclkhdr_754 @[lib.scala 327:22] rvclkhdr_34.clock <= clock rvclkhdr_34.reset <= reset rvclkhdr_34.io.clk <= clock @[lib.scala 328:17] rvclkhdr_34.io.en <= _T_2321 @[lib.scala 329:16] rvclkhdr_34.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - reg _T_2322 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2492:62] - _T_2322 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2492:62] - io.dec_tlu_i0_valid_wb1 <= _T_2322 @[dec_tlu_ctl.scala 2492:30] - node _T_2323 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2493:91] - node _T_2324 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2493:137] - node _T_2325 = and(io.trigger_hit_r_d1, _T_2324) @[dec_tlu_ctl.scala 2493:135] - node _T_2326 = or(_T_2323, _T_2325) @[dec_tlu_ctl.scala 2493:112] - reg _T_2327 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2493:62] - _T_2327 <= _T_2326 @[dec_tlu_ctl.scala 2493:62] - io.dec_tlu_i0_exc_valid_wb1 <= _T_2327 @[dec_tlu_ctl.scala 2493:30] - reg _T_2328 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2494:62] - _T_2328 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2494:62] - io.dec_tlu_exc_cause_wb1 <= _T_2328 @[dec_tlu_ctl.scala 2494:30] - reg _T_2329 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2495:62] - _T_2329 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2495:62] - io.dec_tlu_int_valid_wb1 <= _T_2329 @[dec_tlu_ctl.scala 2495:30] - io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2497:24] - node _T_2330 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2503:61] - node _T_2331 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2504:42] - node _T_2332 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2505:40] - node _T_2333 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2506:39] - node _T_2334 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2507:40] + reg _T_2322 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2488:62] + _T_2322 <= io.i0_valid_wb @[dec_tlu_ctl.scala 2488:62] + io.dec_tlu_i0_valid_wb1 <= _T_2322 @[dec_tlu_ctl.scala 2488:30] + node _T_2323 = or(io.i0_exception_valid_r_d1, io.lsu_i0_exc_r_d1) @[dec_tlu_ctl.scala 2489:91] + node _T_2324 = not(io.trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 2489:137] + node _T_2325 = and(io.trigger_hit_r_d1, _T_2324) @[dec_tlu_ctl.scala 2489:135] + node _T_2326 = or(_T_2323, _T_2325) @[dec_tlu_ctl.scala 2489:112] + reg _T_2327 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2489:62] + _T_2327 <= _T_2326 @[dec_tlu_ctl.scala 2489:62] + io.dec_tlu_i0_exc_valid_wb1 <= _T_2327 @[dec_tlu_ctl.scala 2489:30] + reg _T_2328 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2490:62] + _T_2328 <= io.exc_cause_wb @[dec_tlu_ctl.scala 2490:62] + io.dec_tlu_exc_cause_wb1 <= _T_2328 @[dec_tlu_ctl.scala 2490:30] + reg _T_2329 : UInt, rvclkhdr_34.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 2491:62] + _T_2329 <= io.interrupt_valid_r_d1 @[dec_tlu_ctl.scala 2491:62] + io.dec_tlu_int_valid_wb1 <= _T_2329 @[dec_tlu_ctl.scala 2491:30] + io.dec_tlu_mtval_wb1 <= mtval @[dec_tlu_ctl.scala 2493:24] + node _T_2330 = bits(io.csr_pkt.csr_misa, 0, 0) @[dec_tlu_ctl.scala 2499:61] + node _T_2331 = bits(io.csr_pkt.csr_mvendorid, 0, 0) @[dec_tlu_ctl.scala 2500:42] + node _T_2332 = bits(io.csr_pkt.csr_marchid, 0, 0) @[dec_tlu_ctl.scala 2501:40] + node _T_2333 = bits(io.csr_pkt.csr_mimpid, 0, 0) @[dec_tlu_ctl.scala 2502:39] + node _T_2334 = bits(io.csr_pkt.csr_mhartid, 0, 0) @[dec_tlu_ctl.scala 2503:40] node _T_2335 = cat(io.core_id, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_2336 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2508:40] - node _T_2337 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2508:103] - node _T_2338 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2508:128] + node _T_2336 = bits(io.csr_pkt.csr_mstatus, 0, 0) @[dec_tlu_ctl.scala 2504:40] + node _T_2337 = bits(io.mstatus, 1, 1) @[dec_tlu_ctl.scala 2504:103] + node _T_2338 = bits(io.mstatus, 0, 0) @[dec_tlu_ctl.scala 2504:128] node _T_2339 = cat(UInt<3>("h00"), _T_2338) @[Cat.scala 29:58] node _T_2340 = cat(_T_2339, UInt<3>("h00")) @[Cat.scala 29:58] node _T_2341 = cat(UInt<3>("h00"), _T_2337) @[Cat.scala 29:58] node _T_2342 = cat(UInt<19>("h00"), UInt<2>("h03")) @[Cat.scala 29:58] node _T_2343 = cat(_T_2342, _T_2341) @[Cat.scala 29:58] node _T_2344 = cat(_T_2343, _T_2340) @[Cat.scala 29:58] - node _T_2345 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2509:38] - node _T_2346 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2509:70] - node _T_2347 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2509:96] + node _T_2345 = bits(io.csr_pkt.csr_mtvec, 0, 0) @[dec_tlu_ctl.scala 2505:38] + node _T_2346 = bits(io.mtvec, 30, 1) @[dec_tlu_ctl.scala 2505:70] + node _T_2347 = bits(io.mtvec, 0, 0) @[dec_tlu_ctl.scala 2505:96] node _T_2348 = cat(_T_2346, UInt<1>("h00")) @[Cat.scala 29:58] node _T_2349 = cat(_T_2348, _T_2347) @[Cat.scala 29:58] - node _T_2350 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2510:36] - node _T_2351 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2510:78] - node _T_2352 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2510:102] - node _T_2353 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2510:123] - node _T_2354 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2510:144] + node _T_2350 = bits(io.csr_pkt.csr_mip, 0, 0) @[dec_tlu_ctl.scala 2506:36] + node _T_2351 = bits(io.mip, 5, 3) @[dec_tlu_ctl.scala 2506:78] + node _T_2352 = bits(io.mip, 2, 2) @[dec_tlu_ctl.scala 2506:102] + node _T_2353 = bits(io.mip, 1, 1) @[dec_tlu_ctl.scala 2506:123] + node _T_2354 = bits(io.mip, 0, 0) @[dec_tlu_ctl.scala 2506:144] node _T_2355 = cat(_T_2354, UInt<3>("h00")) @[Cat.scala 29:58] node _T_2356 = cat(_T_2353, UInt<3>("h00")) @[Cat.scala 29:58] node _T_2357 = cat(_T_2356, _T_2355) @[Cat.scala 29:58] @@ -75916,11 +75916,11 @@ circuit quasar_wrapper : node _T_2360 = cat(_T_2359, UInt<16>("h00")) @[Cat.scala 29:58] node _T_2361 = cat(_T_2360, _T_2358) @[Cat.scala 29:58] node _T_2362 = cat(_T_2361, _T_2357) @[Cat.scala 29:58] - node _T_2363 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2511:36] - node _T_2364 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2511:75] - node _T_2365 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2511:96] - node _T_2366 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2511:114] - node _T_2367 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2511:132] + node _T_2363 = bits(io.csr_pkt.csr_mie, 0, 0) @[dec_tlu_ctl.scala 2507:36] + node _T_2364 = bits(mie, 5, 3) @[dec_tlu_ctl.scala 2507:75] + node _T_2365 = bits(mie, 2, 2) @[dec_tlu_ctl.scala 2507:96] + node _T_2366 = bits(mie, 1, 1) @[dec_tlu_ctl.scala 2507:114] + node _T_2367 = bits(mie, 0, 0) @[dec_tlu_ctl.scala 2507:132] node _T_2368 = cat(_T_2367, UInt<3>("h00")) @[Cat.scala 29:58] node _T_2369 = cat(_T_2366, UInt<3>("h00")) @[Cat.scala 29:58] node _T_2370 = cat(_T_2369, _T_2368) @[Cat.scala 29:58] @@ -75929,130 +75929,130 @@ circuit quasar_wrapper : node _T_2373 = cat(_T_2372, UInt<16>("h00")) @[Cat.scala 29:58] node _T_2374 = cat(_T_2373, _T_2371) @[Cat.scala 29:58] node _T_2375 = cat(_T_2374, _T_2370) @[Cat.scala 29:58] - node _T_2376 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2512:40] - node _T_2377 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2512:65] - node _T_2378 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2513:40] - node _T_2379 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2513:69] - node _T_2380 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2514:42] - node _T_2381 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2514:72] - node _T_2382 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2515:42] - node _T_2383 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2515:72] - node _T_2384 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2516:41] - node _T_2385 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2516:66] - node _T_2386 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2517:37] + node _T_2376 = bits(io.csr_pkt.csr_mcyclel, 0, 0) @[dec_tlu_ctl.scala 2508:40] + node _T_2377 = bits(mcyclel, 31, 0) @[dec_tlu_ctl.scala 2508:65] + node _T_2378 = bits(io.csr_pkt.csr_mcycleh, 0, 0) @[dec_tlu_ctl.scala 2509:40] + node _T_2379 = bits(mcycleh_inc, 31, 0) @[dec_tlu_ctl.scala 2509:69] + node _T_2380 = bits(io.csr_pkt.csr_minstretl, 0, 0) @[dec_tlu_ctl.scala 2510:42] + node _T_2381 = bits(minstretl, 31, 0) @[dec_tlu_ctl.scala 2510:72] + node _T_2382 = bits(io.csr_pkt.csr_minstreth, 0, 0) @[dec_tlu_ctl.scala 2511:42] + node _T_2383 = bits(minstreth_inc, 31, 0) @[dec_tlu_ctl.scala 2511:72] + node _T_2384 = bits(io.csr_pkt.csr_mscratch, 0, 0) @[dec_tlu_ctl.scala 2512:41] + node _T_2385 = bits(mscratch, 31, 0) @[dec_tlu_ctl.scala 2512:66] + node _T_2386 = bits(io.csr_pkt.csr_mepc, 0, 0) @[dec_tlu_ctl.scala 2513:37] node _T_2387 = cat(io.mepc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2388 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2518:39] - node _T_2389 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2518:64] - node _T_2390 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2519:40] - node _T_2391 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2519:80] + node _T_2388 = bits(io.csr_pkt.csr_mcause, 0, 0) @[dec_tlu_ctl.scala 2514:39] + node _T_2389 = bits(mcause, 31, 0) @[dec_tlu_ctl.scala 2514:64] + node _T_2390 = bits(io.csr_pkt.csr_mscause, 0, 0) @[dec_tlu_ctl.scala 2515:40] + node _T_2391 = bits(mscause, 3, 0) @[dec_tlu_ctl.scala 2515:80] node _T_2392 = cat(UInt<28>("h00"), _T_2391) @[Cat.scala 29:58] - node _T_2393 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2520:38] - node _T_2394 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2520:63] - node _T_2395 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2521:37] - node _T_2396 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2521:62] - node _T_2397 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2522:39] - node _T_2398 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2522:64] - node _T_2399 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2523:38] + node _T_2393 = bits(io.csr_pkt.csr_mtval, 0, 0) @[dec_tlu_ctl.scala 2516:38] + node _T_2394 = bits(mtval, 31, 0) @[dec_tlu_ctl.scala 2516:63] + node _T_2395 = bits(io.csr_pkt.csr_mrac, 0, 0) @[dec_tlu_ctl.scala 2517:37] + node _T_2396 = bits(mrac, 31, 0) @[dec_tlu_ctl.scala 2517:62] + node _T_2397 = bits(io.csr_pkt.csr_mdseac, 0, 0) @[dec_tlu_ctl.scala 2518:39] + node _T_2398 = bits(mdseac, 31, 0) @[dec_tlu_ctl.scala 2518:64] + node _T_2399 = bits(io.csr_pkt.csr_meivt, 0, 0) @[dec_tlu_ctl.scala 2519:38] node _T_2400 = cat(meivt, UInt<10>("h00")) @[Cat.scala 29:58] - node _T_2401 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2524:39] + node _T_2401 = bits(io.csr_pkt.csr_meihap, 0, 0) @[dec_tlu_ctl.scala 2520:39] node _T_2402 = cat(meivt, meihap) @[Cat.scala 29:58] node _T_2403 = cat(_T_2402, UInt<2>("h00")) @[Cat.scala 29:58] - node _T_2404 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2525:41] - node _T_2405 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2525:81] + node _T_2404 = bits(io.csr_pkt.csr_meicurpl, 0, 0) @[dec_tlu_ctl.scala 2521:41] + node _T_2405 = bits(meicurpl, 3, 0) @[dec_tlu_ctl.scala 2521:81] node _T_2406 = cat(UInt<28>("h00"), _T_2405) @[Cat.scala 29:58] - node _T_2407 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2526:41] - node _T_2408 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2526:81] + node _T_2407 = bits(io.csr_pkt.csr_meicidpl, 0, 0) @[dec_tlu_ctl.scala 2522:41] + node _T_2408 = bits(meicidpl, 3, 0) @[dec_tlu_ctl.scala 2522:81] node _T_2409 = cat(UInt<28>("h00"), _T_2408) @[Cat.scala 29:58] - node _T_2410 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2527:38] - node _T_2411 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2527:78] + node _T_2410 = bits(io.csr_pkt.csr_meipt, 0, 0) @[dec_tlu_ctl.scala 2523:38] + node _T_2411 = bits(meipt, 3, 0) @[dec_tlu_ctl.scala 2523:78] node _T_2412 = cat(UInt<28>("h00"), _T_2411) @[Cat.scala 29:58] - node _T_2413 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2528:37] - node _T_2414 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2528:77] + node _T_2413 = bits(io.csr_pkt.csr_mcgc, 0, 0) @[dec_tlu_ctl.scala 2524:37] + node _T_2414 = bits(mcgc, 8, 0) @[dec_tlu_ctl.scala 2524:77] node _T_2415 = cat(UInt<23>("h00"), _T_2414) @[Cat.scala 29:58] - node _T_2416 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2529:37] - node _T_2417 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2529:77] + node _T_2416 = bits(io.csr_pkt.csr_mfdc, 0, 0) @[dec_tlu_ctl.scala 2525:37] + node _T_2417 = bits(mfdc, 18, 0) @[dec_tlu_ctl.scala 2525:77] node _T_2418 = cat(UInt<13>("h00"), _T_2417) @[Cat.scala 29:58] - node _T_2419 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2530:37] - node _T_2420 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2530:85] + node _T_2419 = bits(io.csr_pkt.csr_dcsr, 0, 0) @[dec_tlu_ctl.scala 2526:37] + node _T_2420 = bits(io.dcsr, 15, 2) @[dec_tlu_ctl.scala 2526:85] node _T_2421 = cat(UInt<16>("h04000"), _T_2420) @[Cat.scala 29:58] node _T_2422 = cat(_T_2421, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_2423 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2531:36] + node _T_2423 = bits(io.csr_pkt.csr_dpc, 0, 0) @[dec_tlu_ctl.scala 2527:36] node _T_2424 = cat(io.dpc, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2425 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2532:39] - node _T_2426 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2532:64] - node _T_2427 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2533:40] - node _T_2428 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2533:65] - node _T_2429 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2534:39] - node _T_2430 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2534:64] - node _T_2431 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2535:41] - node _T_2432 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2535:80] - node _T_2433 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2535:104] - node _T_2434 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2535:131] + node _T_2425 = bits(io.csr_pkt.csr_dicad0, 0, 0) @[dec_tlu_ctl.scala 2528:39] + node _T_2426 = bits(dicad0, 31, 0) @[dec_tlu_ctl.scala 2528:64] + node _T_2427 = bits(io.csr_pkt.csr_dicad0h, 0, 0) @[dec_tlu_ctl.scala 2529:40] + node _T_2428 = bits(dicad0h, 31, 0) @[dec_tlu_ctl.scala 2529:65] + node _T_2429 = bits(io.csr_pkt.csr_dicad1, 0, 0) @[dec_tlu_ctl.scala 2530:39] + node _T_2430 = bits(dicad1, 31, 0) @[dec_tlu_ctl.scala 2530:64] + node _T_2431 = bits(io.csr_pkt.csr_dicawics, 0, 0) @[dec_tlu_ctl.scala 2531:41] + node _T_2432 = bits(dicawics, 16, 16) @[dec_tlu_ctl.scala 2531:80] + node _T_2433 = bits(dicawics, 15, 14) @[dec_tlu_ctl.scala 2531:104] + node _T_2434 = bits(dicawics, 13, 0) @[dec_tlu_ctl.scala 2531:131] node _T_2435 = cat(UInt<3>("h00"), _T_2434) @[Cat.scala 29:58] node _T_2436 = cat(_T_2435, UInt<3>("h00")) @[Cat.scala 29:58] node _T_2437 = cat(UInt<2>("h00"), _T_2433) @[Cat.scala 29:58] node _T_2438 = cat(UInt<7>("h00"), _T_2432) @[Cat.scala 29:58] node _T_2439 = cat(_T_2438, _T_2437) @[Cat.scala 29:58] node _T_2440 = cat(_T_2439, _T_2436) @[Cat.scala 29:58] - node _T_2441 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2536:38] - node _T_2442 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2536:78] + node _T_2441 = bits(io.csr_pkt.csr_mtsel, 0, 0) @[dec_tlu_ctl.scala 2532:38] + node _T_2442 = bits(mtsel, 1, 0) @[dec_tlu_ctl.scala 2532:78] node _T_2443 = cat(UInt<30>("h00"), _T_2442) @[Cat.scala 29:58] - node _T_2444 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2537:40] - node _T_2445 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2537:74] - node _T_2446 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2538:40] - node _T_2447 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2538:74] - node _T_2448 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2539:39] - node _T_2449 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2539:64] - node _T_2450 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2540:41] - node _T_2451 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2540:66] - node _T_2452 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2541:41] - node _T_2453 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2541:66] - node _T_2454 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2542:39] - node _T_2455 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2542:64] - node _T_2456 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2543:39] - node _T_2457 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2543:64] - node _T_2458 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2544:39] - node _T_2459 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2544:64] - node _T_2460 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2545:39] - node _T_2461 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2545:64] - node _T_2462 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2546:40] - node _T_2463 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2546:65] - node _T_2464 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2547:40] - node _T_2465 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2547:65] - node _T_2466 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2548:40] - node _T_2467 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2548:65] - node _T_2468 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2549:40] - node _T_2469 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2549:65] - node _T_2470 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2550:38] - node _T_2471 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2550:78] + node _T_2444 = bits(io.csr_pkt.csr_mtdata1, 0, 0) @[dec_tlu_ctl.scala 2533:40] + node _T_2445 = bits(mtdata1_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2533:74] + node _T_2446 = bits(io.csr_pkt.csr_mtdata2, 0, 0) @[dec_tlu_ctl.scala 2534:40] + node _T_2447 = bits(mtdata2_tsel_out, 31, 0) @[dec_tlu_ctl.scala 2534:74] + node _T_2448 = bits(io.csr_pkt.csr_micect, 0, 0) @[dec_tlu_ctl.scala 2535:39] + node _T_2449 = bits(micect, 31, 0) @[dec_tlu_ctl.scala 2535:64] + node _T_2450 = bits(io.csr_pkt.csr_miccmect, 0, 0) @[dec_tlu_ctl.scala 2536:41] + node _T_2451 = bits(miccmect, 31, 0) @[dec_tlu_ctl.scala 2536:66] + node _T_2452 = bits(io.csr_pkt.csr_mdccmect, 0, 0) @[dec_tlu_ctl.scala 2537:41] + node _T_2453 = bits(mdccmect, 31, 0) @[dec_tlu_ctl.scala 2537:66] + node _T_2454 = bits(io.csr_pkt.csr_mhpmc3, 0, 0) @[dec_tlu_ctl.scala 2538:39] + node _T_2455 = bits(mhpmc3, 31, 0) @[dec_tlu_ctl.scala 2538:64] + node _T_2456 = bits(io.csr_pkt.csr_mhpmc4, 0, 0) @[dec_tlu_ctl.scala 2539:39] + node _T_2457 = bits(mhpmc4, 31, 0) @[dec_tlu_ctl.scala 2539:64] + node _T_2458 = bits(io.csr_pkt.csr_mhpmc5, 0, 0) @[dec_tlu_ctl.scala 2540:39] + node _T_2459 = bits(mhpmc5, 31, 0) @[dec_tlu_ctl.scala 2540:64] + node _T_2460 = bits(io.csr_pkt.csr_mhpmc6, 0, 0) @[dec_tlu_ctl.scala 2541:39] + node _T_2461 = bits(mhpmc6, 31, 0) @[dec_tlu_ctl.scala 2541:64] + node _T_2462 = bits(io.csr_pkt.csr_mhpmc3h, 0, 0) @[dec_tlu_ctl.scala 2542:40] + node _T_2463 = bits(mhpmc3h, 31, 0) @[dec_tlu_ctl.scala 2542:65] + node _T_2464 = bits(io.csr_pkt.csr_mhpmc4h, 0, 0) @[dec_tlu_ctl.scala 2543:40] + node _T_2465 = bits(mhpmc4h, 31, 0) @[dec_tlu_ctl.scala 2543:65] + node _T_2466 = bits(io.csr_pkt.csr_mhpmc5h, 0, 0) @[dec_tlu_ctl.scala 2544:40] + node _T_2467 = bits(mhpmc5h, 31, 0) @[dec_tlu_ctl.scala 2544:65] + node _T_2468 = bits(io.csr_pkt.csr_mhpmc6h, 0, 0) @[dec_tlu_ctl.scala 2545:40] + node _T_2469 = bits(mhpmc6h, 31, 0) @[dec_tlu_ctl.scala 2545:65] + node _T_2470 = bits(io.csr_pkt.csr_mfdht, 0, 0) @[dec_tlu_ctl.scala 2546:38] + node _T_2471 = bits(mfdht, 5, 0) @[dec_tlu_ctl.scala 2546:78] node _T_2472 = cat(UInt<26>("h00"), _T_2471) @[Cat.scala 29:58] - node _T_2473 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2551:38] - node _T_2474 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2551:78] + node _T_2473 = bits(io.csr_pkt.csr_mfdhs, 0, 0) @[dec_tlu_ctl.scala 2547:38] + node _T_2474 = bits(mfdhs, 1, 0) @[dec_tlu_ctl.scala 2547:78] node _T_2475 = cat(UInt<30>("h00"), _T_2474) @[Cat.scala 29:58] - node _T_2476 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2552:39] - node _T_2477 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2552:79] + node _T_2476 = bits(io.csr_pkt.csr_mhpme3, 0, 0) @[dec_tlu_ctl.scala 2548:39] + node _T_2477 = bits(mhpme3, 9, 0) @[dec_tlu_ctl.scala 2548:79] node _T_2478 = cat(UInt<22>("h00"), _T_2477) @[Cat.scala 29:58] - node _T_2479 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2553:39] - node _T_2480 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2553:79] + node _T_2479 = bits(io.csr_pkt.csr_mhpme4, 0, 0) @[dec_tlu_ctl.scala 2549:39] + node _T_2480 = bits(mhpme4, 9, 0) @[dec_tlu_ctl.scala 2549:79] node _T_2481 = cat(UInt<22>("h00"), _T_2480) @[Cat.scala 29:58] - node _T_2482 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2554:39] - node _T_2483 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2554:78] + node _T_2482 = bits(io.csr_pkt.csr_mhpme5, 0, 0) @[dec_tlu_ctl.scala 2550:39] + node _T_2483 = bits(mhpme5, 9, 0) @[dec_tlu_ctl.scala 2550:78] node _T_2484 = cat(UInt<22>("h00"), _T_2483) @[Cat.scala 29:58] - node _T_2485 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2555:39] - node _T_2486 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2555:78] + node _T_2485 = bits(io.csr_pkt.csr_mhpme6, 0, 0) @[dec_tlu_ctl.scala 2551:39] + node _T_2486 = bits(mhpme6, 9, 0) @[dec_tlu_ctl.scala 2551:78] node _T_2487 = cat(UInt<22>("h00"), _T_2486) @[Cat.scala 29:58] - node _T_2488 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2556:46] - node _T_2489 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2556:86] + node _T_2488 = bits(io.csr_pkt.csr_mcountinhibit, 0, 0) @[dec_tlu_ctl.scala 2552:46] + node _T_2489 = bits(mcountinhibit, 6, 0) @[dec_tlu_ctl.scala 2552:86] node _T_2490 = cat(UInt<25>("h00"), _T_2489) @[Cat.scala 29:58] - node _T_2491 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2557:37] + node _T_2491 = bits(io.csr_pkt.csr_mpmc, 0, 0) @[dec_tlu_ctl.scala 2553:37] node _T_2492 = cat(UInt<30>("h00"), mpmc) @[Cat.scala 29:58] node _T_2493 = cat(_T_2492, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_2494 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2558:37] - node _T_2495 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2558:76] + node _T_2494 = bits(io.dec_timer_read_d, 0, 0) @[dec_tlu_ctl.scala 2554:37] + node _T_2495 = bits(io.dec_timer_rddata_d, 31, 0) @[dec_tlu_ctl.scala 2554:76] node _T_2496 = mux(_T_2330, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_2497 = mux(_T_2331, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_2498 = mux(_T_2332, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_2499 = mux(_T_2333, UInt<32>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_2499 = mux(_T_2333, UInt<32>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_2500 = mux(_T_2334, _T_2335, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2501 = mux(_T_2336, _T_2344, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2502 = mux(_T_2345, _T_2349, UInt<1>("h00")) @[Mux.scala 27:72] @@ -76162,1695 +76162,1695 @@ circuit quasar_wrapper : node _T_2606 = or(_T_2605, _T_2551) @[Mux.scala 27:72] wire _T_2607 : UInt @[Mux.scala 27:72] _T_2607 <= _T_2606 @[Mux.scala 27:72] - io.dec_csr_rddata_d <= _T_2607 @[dec_tlu_ctl.scala 2502:21] + io.dec_csr_rddata_d <= _T_2607 @[dec_tlu_ctl.scala 2498:21] module dec_decode_csr_read : input clock : Clock input reset : AsyncReset output io : {flip dec_csr_rdaddr_d : UInt<12>, csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>}} - node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_1 = eq(_T, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_2 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_3 = eq(_T_2, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_4 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_5 = eq(_T_4, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_6 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_7 = eq(_T_6, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_8 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_9 = and(_T_1, _T_3) @[dec_tlu_ctl.scala 2574:198] - node _T_10 = and(_T_9, _T_5) @[dec_tlu_ctl.scala 2574:198] - node _T_11 = and(_T_10, _T_7) @[dec_tlu_ctl.scala 2574:198] - node _T_12 = and(_T_11, _T_8) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_misa <= _T_12 @[dec_tlu_ctl.scala 2576:57] - node _T_13 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_14 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_15 = eq(_T_14, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_16 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_17 = eq(_T_16, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_18 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_19 = and(_T_13, _T_15) @[dec_tlu_ctl.scala 2574:198] - node _T_20 = and(_T_19, _T_17) @[dec_tlu_ctl.scala 2574:198] - node _T_21 = and(_T_20, _T_18) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mvendorid <= _T_21 @[dec_tlu_ctl.scala 2577:57] - node _T_22 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_23 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_24 = eq(_T_23, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_25 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_26 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_27 = eq(_T_26, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_28 = and(_T_22, _T_24) @[dec_tlu_ctl.scala 2574:198] - node _T_29 = and(_T_28, _T_25) @[dec_tlu_ctl.scala 2574:198] - node _T_30 = and(_T_29, _T_27) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_marchid <= _T_30 @[dec_tlu_ctl.scala 2578:57] - node _T_31 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_32 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_33 = eq(_T_32, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_34 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_35 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_36 = and(_T_31, _T_33) @[dec_tlu_ctl.scala 2574:198] - node _T_37 = and(_T_36, _T_34) @[dec_tlu_ctl.scala 2574:198] - node _T_38 = and(_T_37, _T_35) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mimpid <= _T_38 @[dec_tlu_ctl.scala 2579:57] - node _T_39 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_40 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_41 = eq(_T_40, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_42 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_43 = and(_T_39, _T_41) @[dec_tlu_ctl.scala 2574:198] - node _T_44 = and(_T_43, _T_42) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mhartid <= _T_44 @[dec_tlu_ctl.scala 2580:57] - node _T_45 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_46 = eq(_T_45, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_47 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_49 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_50 = eq(_T_49, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_51 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_52 = eq(_T_51, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_53 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_54 = eq(_T_53, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_55 = and(_T_46, _T_48) @[dec_tlu_ctl.scala 2574:198] - node _T_56 = and(_T_55, _T_50) @[dec_tlu_ctl.scala 2574:198] - node _T_57 = and(_T_56, _T_52) @[dec_tlu_ctl.scala 2574:198] - node _T_58 = and(_T_57, _T_54) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mstatus <= _T_58 @[dec_tlu_ctl.scala 2581:57] - node _T_59 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_60 = eq(_T_59, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_61 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_62 = eq(_T_61, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_63 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_64 = eq(_T_63, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_65 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_66 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_67 = and(_T_60, _T_62) @[dec_tlu_ctl.scala 2574:198] - node _T_68 = and(_T_67, _T_64) @[dec_tlu_ctl.scala 2574:198] - node _T_69 = and(_T_68, _T_65) @[dec_tlu_ctl.scala 2574:198] - node _T_70 = and(_T_69, _T_66) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mtvec <= _T_70 @[dec_tlu_ctl.scala 2582:57] - node _T_71 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_72 = eq(_T_71, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_73 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_74 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_75 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 2574:198] - node _T_76 = and(_T_75, _T_74) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mip <= _T_76 @[dec_tlu_ctl.scala 2583:65] - node _T_77 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_78 = eq(_T_77, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_79 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_80 = eq(_T_79, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_81 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_82 = eq(_T_81, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_83 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_84 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_85 = eq(_T_84, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_86 = and(_T_78, _T_80) @[dec_tlu_ctl.scala 2574:198] - node _T_87 = and(_T_86, _T_82) @[dec_tlu_ctl.scala 2574:198] - node _T_88 = and(_T_87, _T_83) @[dec_tlu_ctl.scala 2574:198] - node _T_89 = and(_T_88, _T_85) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mie <= _T_89 @[dec_tlu_ctl.scala 2584:65] - node _T_90 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_91 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_92 = eq(_T_91, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_93 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_94 = eq(_T_93, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_95 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_96 = eq(_T_95, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_97 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_98 = eq(_T_97, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_99 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_100 = eq(_T_99, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_101 = and(_T_90, _T_92) @[dec_tlu_ctl.scala 2574:198] - node _T_102 = and(_T_101, _T_94) @[dec_tlu_ctl.scala 2574:198] - node _T_103 = and(_T_102, _T_96) @[dec_tlu_ctl.scala 2574:198] - node _T_104 = and(_T_103, _T_98) @[dec_tlu_ctl.scala 2574:198] - node _T_105 = and(_T_104, _T_100) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mcyclel <= _T_105 @[dec_tlu_ctl.scala 2585:57] - node _T_106 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_107 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_108 = eq(_T_107, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_109 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_110 = eq(_T_109, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_111 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_112 = eq(_T_111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_113 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_114 = eq(_T_113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_115 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_116 = eq(_T_115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_117 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_118 = eq(_T_117, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_119 = and(_T_106, _T_108) @[dec_tlu_ctl.scala 2574:198] - node _T_120 = and(_T_119, _T_110) @[dec_tlu_ctl.scala 2574:198] - node _T_121 = and(_T_120, _T_112) @[dec_tlu_ctl.scala 2574:198] - node _T_122 = and(_T_121, _T_114) @[dec_tlu_ctl.scala 2574:198] - node _T_123 = and(_T_122, _T_116) @[dec_tlu_ctl.scala 2574:198] - node _T_124 = and(_T_123, _T_118) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mcycleh <= _T_124 @[dec_tlu_ctl.scala 2586:57] - node _T_125 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_126 = eq(_T_125, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_127 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_128 = eq(_T_127, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_129 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_130 = eq(_T_129, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_131 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_132 = eq(_T_131, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_133 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_134 = eq(_T_133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_135 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_136 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_137 = eq(_T_136, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_138 = and(_T_126, _T_128) @[dec_tlu_ctl.scala 2574:198] - node _T_139 = and(_T_138, _T_130) @[dec_tlu_ctl.scala 2574:198] - node _T_140 = and(_T_139, _T_132) @[dec_tlu_ctl.scala 2574:198] - node _T_141 = and(_T_140, _T_134) @[dec_tlu_ctl.scala 2574:198] - node _T_142 = and(_T_141, _T_135) @[dec_tlu_ctl.scala 2574:198] - node _T_143 = and(_T_142, _T_137) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_minstretl <= _T_143 @[dec_tlu_ctl.scala 2587:57] - node _T_144 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:149] - node _T_145 = eq(_T_144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_146 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_147 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_148 = eq(_T_147, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_149 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_150 = eq(_T_149, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_151 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_152 = eq(_T_151, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_153 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_154 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_155 = eq(_T_154, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_156 = and(_T_145, _T_146) @[dec_tlu_ctl.scala 2574:198] - node _T_157 = and(_T_156, _T_148) @[dec_tlu_ctl.scala 2574:198] - node _T_158 = and(_T_157, _T_150) @[dec_tlu_ctl.scala 2574:198] - node _T_159 = and(_T_158, _T_152) @[dec_tlu_ctl.scala 2574:198] - node _T_160 = and(_T_159, _T_153) @[dec_tlu_ctl.scala 2574:198] - node _T_161 = and(_T_160, _T_155) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_minstreth <= _T_161 @[dec_tlu_ctl.scala 2588:57] - node _T_162 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_163 = eq(_T_162, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_164 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_165 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_166 = eq(_T_165, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_167 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_168 = eq(_T_167, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_169 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_170 = eq(_T_169, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_171 = and(_T_163, _T_164) @[dec_tlu_ctl.scala 2574:198] - node _T_172 = and(_T_171, _T_166) @[dec_tlu_ctl.scala 2574:198] - node _T_173 = and(_T_172, _T_168) @[dec_tlu_ctl.scala 2574:198] - node _T_174 = and(_T_173, _T_170) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mscratch <= _T_174 @[dec_tlu_ctl.scala 2589:57] - node _T_175 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_176 = eq(_T_175, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_177 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_178 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_179 = eq(_T_178, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_180 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_181 = and(_T_176, _T_177) @[dec_tlu_ctl.scala 2574:198] - node _T_182 = and(_T_181, _T_179) @[dec_tlu_ctl.scala 2574:198] - node _T_183 = and(_T_182, _T_180) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mepc <= _T_183 @[dec_tlu_ctl.scala 2590:57] - node _T_184 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_185 = eq(_T_184, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_186 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_187 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_188 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_189 = eq(_T_188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_190 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 2574:198] - node _T_191 = and(_T_190, _T_187) @[dec_tlu_ctl.scala 2574:198] - node _T_192 = and(_T_191, _T_189) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mcause <= _T_192 @[dec_tlu_ctl.scala 2591:57] - node _T_193 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_194 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_195 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_196 = and(_T_193, _T_194) @[dec_tlu_ctl.scala 2574:198] - node _T_197 = and(_T_196, _T_195) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mscause <= _T_197 @[dec_tlu_ctl.scala 2592:57] - node _T_198 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_199 = eq(_T_198, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_200 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_201 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_202 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_203 = and(_T_199, _T_200) @[dec_tlu_ctl.scala 2574:198] - node _T_204 = and(_T_203, _T_201) @[dec_tlu_ctl.scala 2574:198] - node _T_205 = and(_T_204, _T_202) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mtval <= _T_205 @[dec_tlu_ctl.scala 2593:57] - node _T_206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_207 = eq(_T_206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_208 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_209 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_210 = eq(_T_209, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_211 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_212 = eq(_T_211, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_213 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_214 = eq(_T_213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_215 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_216 = eq(_T_215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_217 = and(_T_207, _T_208) @[dec_tlu_ctl.scala 2574:198] - node _T_218 = and(_T_217, _T_210) @[dec_tlu_ctl.scala 2574:198] - node _T_219 = and(_T_218, _T_212) @[dec_tlu_ctl.scala 2574:198] - node _T_220 = and(_T_219, _T_214) @[dec_tlu_ctl.scala 2574:198] - node _T_221 = and(_T_220, _T_216) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mrac <= _T_221 @[dec_tlu_ctl.scala 2594:57] - node _T_222 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_223 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_224 = eq(_T_223, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_225 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_226 = eq(_T_225, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_227 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_228 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_229 = eq(_T_228, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_230 = and(_T_222, _T_224) @[dec_tlu_ctl.scala 2574:198] - node _T_231 = and(_T_230, _T_226) @[dec_tlu_ctl.scala 2574:198] - node _T_232 = and(_T_231, _T_227) @[dec_tlu_ctl.scala 2574:198] - node _T_233 = and(_T_232, _T_229) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_dmst <= _T_233 @[dec_tlu_ctl.scala 2595:57] - node _T_234 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_235 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_236 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_237 = eq(_T_236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_238 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_239 = eq(_T_238, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_240 = and(_T_234, _T_235) @[dec_tlu_ctl.scala 2574:198] - node _T_241 = and(_T_240, _T_237) @[dec_tlu_ctl.scala 2574:198] - node _T_242 = and(_T_241, _T_239) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mdseac <= _T_242 @[dec_tlu_ctl.scala 2596:57] - node _T_243 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_244 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_245 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:106] - node _T_246 = and(_T_243, _T_244) @[dec_tlu_ctl.scala 2574:198] - node _T_247 = and(_T_246, _T_245) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_meihap <= _T_247 @[dec_tlu_ctl.scala 2597:57] - node _T_248 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:149] - node _T_249 = eq(_T_248, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_250 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_251 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:106] - node _T_252 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_253 = eq(_T_252, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_254 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_255 = eq(_T_254, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_256 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_257 = eq(_T_256, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_258 = and(_T_249, _T_250) @[dec_tlu_ctl.scala 2574:198] - node _T_259 = and(_T_258, _T_251) @[dec_tlu_ctl.scala 2574:198] - node _T_260 = and(_T_259, _T_253) @[dec_tlu_ctl.scala 2574:198] - node _T_261 = and(_T_260, _T_255) @[dec_tlu_ctl.scala 2574:198] - node _T_262 = and(_T_261, _T_257) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_meivt <= _T_262 @[dec_tlu_ctl.scala 2598:57] - node _T_263 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_264 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_266 = eq(_T_265, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_267 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_268 = and(_T_263, _T_264) @[dec_tlu_ctl.scala 2574:198] - node _T_269 = and(_T_268, _T_266) @[dec_tlu_ctl.scala 2574:198] - node _T_270 = and(_T_269, _T_267) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_meipt <= _T_270 @[dec_tlu_ctl.scala 2599:57] - node _T_271 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_272 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_273 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_274 = and(_T_271, _T_272) @[dec_tlu_ctl.scala 2574:198] - node _T_275 = and(_T_274, _T_273) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_meicurpl <= _T_275 @[dec_tlu_ctl.scala 2600:57] - node _T_276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_277 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_278 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_279 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_280 = and(_T_276, _T_277) @[dec_tlu_ctl.scala 2574:198] - node _T_281 = and(_T_280, _T_278) @[dec_tlu_ctl.scala 2574:198] - node _T_282 = and(_T_281, _T_279) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_meicidpl <= _T_282 @[dec_tlu_ctl.scala 2601:57] - node _T_283 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_284 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_285 = eq(_T_284, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_286 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_287 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:106] - node _T_288 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_289 = eq(_T_288, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_290 = and(_T_283, _T_285) @[dec_tlu_ctl.scala 2574:198] - node _T_291 = and(_T_290, _T_286) @[dec_tlu_ctl.scala 2574:198] - node _T_292 = and(_T_291, _T_287) @[dec_tlu_ctl.scala 2574:198] - node _T_293 = and(_T_292, _T_289) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_dcsr <= _T_293 @[dec_tlu_ctl.scala 2602:57] - node _T_294 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_295 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:106] - node _T_296 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:106] - node _T_297 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_298 = eq(_T_297, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_299 = and(_T_294, _T_295) @[dec_tlu_ctl.scala 2574:198] - node _T_300 = and(_T_299, _T_296) @[dec_tlu_ctl.scala 2574:198] - node _T_301 = and(_T_300, _T_298) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mcgc <= _T_301 @[dec_tlu_ctl.scala 2603:57] - node _T_302 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_303 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:106] - node _T_304 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:106] - node _T_305 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_306 = eq(_T_305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_307 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_308 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 2574:198] - node _T_309 = and(_T_308, _T_304) @[dec_tlu_ctl.scala 2574:198] - node _T_310 = and(_T_309, _T_306) @[dec_tlu_ctl.scala 2574:198] - node _T_311 = and(_T_310, _T_307) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mfdc <= _T_311 @[dec_tlu_ctl.scala 2604:57] - node _T_312 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_313 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_314 = eq(_T_313, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_315 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_316 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:106] - node _T_317 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_318 = and(_T_312, _T_314) @[dec_tlu_ctl.scala 2574:198] - node _T_319 = and(_T_318, _T_315) @[dec_tlu_ctl.scala 2574:198] - node _T_320 = and(_T_319, _T_316) @[dec_tlu_ctl.scala 2574:198] - node _T_321 = and(_T_320, _T_317) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_dpc <= _T_321 @[dec_tlu_ctl.scala 2605:65] - node _T_322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_323 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_324 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_325 = eq(_T_324, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_326 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_327 = eq(_T_326, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_328 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_329 = eq(_T_328, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_330 = and(_T_322, _T_323) @[dec_tlu_ctl.scala 2574:198] - node _T_331 = and(_T_330, _T_325) @[dec_tlu_ctl.scala 2574:198] - node _T_332 = and(_T_331, _T_327) @[dec_tlu_ctl.scala 2574:198] - node _T_333 = and(_T_332, _T_329) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mtsel <= _T_333 @[dec_tlu_ctl.scala 2606:57] - node _T_334 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_335 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_336 = eq(_T_335, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_337 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_338 = eq(_T_337, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_339 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_340 = and(_T_334, _T_336) @[dec_tlu_ctl.scala 2574:198] - node _T_341 = and(_T_340, _T_338) @[dec_tlu_ctl.scala 2574:198] - node _T_342 = and(_T_341, _T_339) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mtdata1 <= _T_342 @[dec_tlu_ctl.scala 2607:57] - node _T_343 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_344 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_345 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_346 = eq(_T_345, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_347 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_348 = and(_T_343, _T_344) @[dec_tlu_ctl.scala 2574:198] - node _T_349 = and(_T_348, _T_346) @[dec_tlu_ctl.scala 2574:198] - node _T_350 = and(_T_349, _T_347) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mtdata2 <= _T_350 @[dec_tlu_ctl.scala 2608:57] - node _T_351 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_352 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_353 = eq(_T_352, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_354 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_355 = eq(_T_354, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_356 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_357 = eq(_T_356, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_358 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_359 = eq(_T_358, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_360 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_361 = and(_T_351, _T_353) @[dec_tlu_ctl.scala 2574:198] - node _T_362 = and(_T_361, _T_355) @[dec_tlu_ctl.scala 2574:198] - node _T_363 = and(_T_362, _T_357) @[dec_tlu_ctl.scala 2574:198] - node _T_364 = and(_T_363, _T_359) @[dec_tlu_ctl.scala 2574:198] - node _T_365 = and(_T_364, _T_360) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mhpmc3 <= _T_365 @[dec_tlu_ctl.scala 2609:57] - node _T_366 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_367 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_368 = eq(_T_367, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_369 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_370 = eq(_T_369, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_371 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_372 = eq(_T_371, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_373 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_374 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_375 = eq(_T_374, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_376 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_377 = eq(_T_376, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_378 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 2574:198] - node _T_379 = and(_T_378, _T_370) @[dec_tlu_ctl.scala 2574:198] - node _T_380 = and(_T_379, _T_372) @[dec_tlu_ctl.scala 2574:198] - node _T_381 = and(_T_380, _T_373) @[dec_tlu_ctl.scala 2574:198] - node _T_382 = and(_T_381, _T_375) @[dec_tlu_ctl.scala 2574:198] - node _T_383 = and(_T_382, _T_377) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mhpmc4 <= _T_383 @[dec_tlu_ctl.scala 2610:57] - node _T_384 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_385 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_386 = eq(_T_385, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_387 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_388 = eq(_T_387, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_389 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_390 = eq(_T_389, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_391 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_392 = eq(_T_391, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_393 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_394 = and(_T_384, _T_386) @[dec_tlu_ctl.scala 2574:198] - node _T_395 = and(_T_394, _T_388) @[dec_tlu_ctl.scala 2574:198] - node _T_396 = and(_T_395, _T_390) @[dec_tlu_ctl.scala 2574:198] - node _T_397 = and(_T_396, _T_392) @[dec_tlu_ctl.scala 2574:198] - node _T_398 = and(_T_397, _T_393) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mhpmc5 <= _T_398 @[dec_tlu_ctl.scala 2611:57] - node _T_399 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_400 = eq(_T_399, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_401 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_402 = eq(_T_401, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_403 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_404 = eq(_T_403, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_405 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_406 = eq(_T_405, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_407 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_408 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_409 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_410 = eq(_T_409, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_411 = and(_T_400, _T_402) @[dec_tlu_ctl.scala 2574:198] - node _T_412 = and(_T_411, _T_404) @[dec_tlu_ctl.scala 2574:198] - node _T_413 = and(_T_412, _T_406) @[dec_tlu_ctl.scala 2574:198] - node _T_414 = and(_T_413, _T_407) @[dec_tlu_ctl.scala 2574:198] - node _T_415 = and(_T_414, _T_408) @[dec_tlu_ctl.scala 2574:198] - node _T_416 = and(_T_415, _T_410) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mhpmc6 <= _T_416 @[dec_tlu_ctl.scala 2612:57] - node _T_417 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_419 = eq(_T_418, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_421 = eq(_T_420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_423 = eq(_T_422, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_424 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_425 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_426 = and(_T_417, _T_419) @[dec_tlu_ctl.scala 2574:198] - node _T_427 = and(_T_426, _T_421) @[dec_tlu_ctl.scala 2574:198] - node _T_428 = and(_T_427, _T_423) @[dec_tlu_ctl.scala 2574:198] - node _T_429 = and(_T_428, _T_424) @[dec_tlu_ctl.scala 2574:198] - node _T_430 = and(_T_429, _T_425) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mhpmc3h <= _T_430 @[dec_tlu_ctl.scala 2613:57] - node _T_431 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_432 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_433 = eq(_T_432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_434 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_435 = eq(_T_434, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_436 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_437 = eq(_T_436, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_438 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_439 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_440 = eq(_T_439, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_441 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_442 = eq(_T_441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_443 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 2574:198] - node _T_444 = and(_T_443, _T_435) @[dec_tlu_ctl.scala 2574:198] - node _T_445 = and(_T_444, _T_437) @[dec_tlu_ctl.scala 2574:198] - node _T_446 = and(_T_445, _T_438) @[dec_tlu_ctl.scala 2574:198] - node _T_447 = and(_T_446, _T_440) @[dec_tlu_ctl.scala 2574:198] - node _T_448 = and(_T_447, _T_442) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mhpmc4h <= _T_448 @[dec_tlu_ctl.scala 2614:57] - node _T_449 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_450 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_451 = eq(_T_450, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_452 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_453 = eq(_T_452, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_454 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_455 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_456 = eq(_T_455, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_457 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_458 = and(_T_449, _T_451) @[dec_tlu_ctl.scala 2574:198] - node _T_459 = and(_T_458, _T_453) @[dec_tlu_ctl.scala 2574:198] - node _T_460 = and(_T_459, _T_454) @[dec_tlu_ctl.scala 2574:198] - node _T_461 = and(_T_460, _T_456) @[dec_tlu_ctl.scala 2574:198] - node _T_462 = and(_T_461, _T_457) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mhpmc5h <= _T_462 @[dec_tlu_ctl.scala 2615:57] - node _T_463 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_464 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_465 = eq(_T_464, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_466 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_467 = eq(_T_466, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_468 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_469 = eq(_T_468, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_470 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_471 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_472 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_473 = eq(_T_472, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_474 = and(_T_463, _T_465) @[dec_tlu_ctl.scala 2574:198] - node _T_475 = and(_T_474, _T_467) @[dec_tlu_ctl.scala 2574:198] - node _T_476 = and(_T_475, _T_469) @[dec_tlu_ctl.scala 2574:198] - node _T_477 = and(_T_476, _T_470) @[dec_tlu_ctl.scala 2574:198] - node _T_478 = and(_T_477, _T_471) @[dec_tlu_ctl.scala 2574:198] - node _T_479 = and(_T_478, _T_473) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mhpmc6h <= _T_479 @[dec_tlu_ctl.scala 2616:57] - node _T_480 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_481 = eq(_T_480, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_482 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_483 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_484 = eq(_T_483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_485 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_486 = eq(_T_485, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_487 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_488 = eq(_T_487, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_489 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_490 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 2574:198] - node _T_491 = and(_T_490, _T_484) @[dec_tlu_ctl.scala 2574:198] - node _T_492 = and(_T_491, _T_486) @[dec_tlu_ctl.scala 2574:198] - node _T_493 = and(_T_492, _T_488) @[dec_tlu_ctl.scala 2574:198] - node _T_494 = and(_T_493, _T_489) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mhpme3 <= _T_494 @[dec_tlu_ctl.scala 2617:57] - node _T_495 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_496 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_497 = eq(_T_496, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_498 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_499 = eq(_T_498, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_500 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_501 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_502 = eq(_T_501, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_503 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_504 = eq(_T_503, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_505 = and(_T_495, _T_497) @[dec_tlu_ctl.scala 2574:198] - node _T_506 = and(_T_505, _T_499) @[dec_tlu_ctl.scala 2574:198] - node _T_507 = and(_T_506, _T_500) @[dec_tlu_ctl.scala 2574:198] - node _T_508 = and(_T_507, _T_502) @[dec_tlu_ctl.scala 2574:198] - node _T_509 = and(_T_508, _T_504) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mhpme4 <= _T_509 @[dec_tlu_ctl.scala 2618:57] - node _T_510 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_511 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_512 = eq(_T_511, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_513 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_514 = eq(_T_513, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_515 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_516 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_517 = eq(_T_516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_518 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_519 = and(_T_510, _T_512) @[dec_tlu_ctl.scala 2574:198] - node _T_520 = and(_T_519, _T_514) @[dec_tlu_ctl.scala 2574:198] - node _T_521 = and(_T_520, _T_515) @[dec_tlu_ctl.scala 2574:198] - node _T_522 = and(_T_521, _T_517) @[dec_tlu_ctl.scala 2574:198] - node _T_523 = and(_T_522, _T_518) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mhpme5 <= _T_523 @[dec_tlu_ctl.scala 2619:57] - node _T_524 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_525 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_526 = eq(_T_525, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_527 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_528 = eq(_T_527, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_529 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_530 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_531 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_532 = eq(_T_531, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_533 = and(_T_524, _T_526) @[dec_tlu_ctl.scala 2574:198] - node _T_534 = and(_T_533, _T_528) @[dec_tlu_ctl.scala 2574:198] - node _T_535 = and(_T_534, _T_529) @[dec_tlu_ctl.scala 2574:198] - node _T_536 = and(_T_535, _T_530) @[dec_tlu_ctl.scala 2574:198] - node _T_537 = and(_T_536, _T_532) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mhpme6 <= _T_537 @[dec_tlu_ctl.scala 2620:57] - node _T_538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_539 = eq(_T_538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_540 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_541 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_542 = eq(_T_541, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_544 = eq(_T_543, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_545 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_546 = eq(_T_545, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_547 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_548 = eq(_T_547, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_549 = and(_T_539, _T_540) @[dec_tlu_ctl.scala 2574:198] - node _T_550 = and(_T_549, _T_542) @[dec_tlu_ctl.scala 2574:198] - node _T_551 = and(_T_550, _T_544) @[dec_tlu_ctl.scala 2574:198] - node _T_552 = and(_T_551, _T_546) @[dec_tlu_ctl.scala 2574:198] - node _T_553 = and(_T_552, _T_548) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mcountinhibit <= _T_553 @[dec_tlu_ctl.scala 2621:49] - node _T_554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_555 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_556 = eq(_T_555, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:106] - node _T_558 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_559 = eq(_T_558, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_560 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_561 = eq(_T_560, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_562 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 2574:198] - node _T_563 = and(_T_562, _T_557) @[dec_tlu_ctl.scala 2574:198] - node _T_564 = and(_T_563, _T_559) @[dec_tlu_ctl.scala 2574:198] - node _T_565 = and(_T_564, _T_561) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mitctl0 <= _T_565 @[dec_tlu_ctl.scala 2622:57] - node _T_566 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_567 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_568 = eq(_T_567, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_569 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_570 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_571 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_572 = and(_T_566, _T_568) @[dec_tlu_ctl.scala 2574:198] - node _T_573 = and(_T_572, _T_569) @[dec_tlu_ctl.scala 2574:198] - node _T_574 = and(_T_573, _T_570) @[dec_tlu_ctl.scala 2574:198] - node _T_575 = and(_T_574, _T_571) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mitctl1 <= _T_575 @[dec_tlu_ctl.scala 2623:57] - node _T_576 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_577 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_578 = eq(_T_577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_579 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:106] - node _T_580 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_581 = eq(_T_580, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_582 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_583 = and(_T_576, _T_578) @[dec_tlu_ctl.scala 2574:198] - node _T_584 = and(_T_583, _T_579) @[dec_tlu_ctl.scala 2574:198] - node _T_585 = and(_T_584, _T_581) @[dec_tlu_ctl.scala 2574:198] - node _T_586 = and(_T_585, _T_582) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mitb0 <= _T_586 @[dec_tlu_ctl.scala 2624:57] - node _T_587 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_588 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:106] - node _T_589 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_590 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_591 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_592 = eq(_T_591, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_593 = and(_T_587, _T_588) @[dec_tlu_ctl.scala 2574:198] - node _T_594 = and(_T_593, _T_589) @[dec_tlu_ctl.scala 2574:198] - node _T_595 = and(_T_594, _T_590) @[dec_tlu_ctl.scala 2574:198] - node _T_596 = and(_T_595, _T_592) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mitb1 <= _T_596 @[dec_tlu_ctl.scala 2625:57] - node _T_597 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_598 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_599 = eq(_T_598, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_600 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:106] - node _T_601 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_602 = eq(_T_601, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_603 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_604 = eq(_T_603, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_605 = and(_T_597, _T_599) @[dec_tlu_ctl.scala 2574:198] - node _T_606 = and(_T_605, _T_600) @[dec_tlu_ctl.scala 2574:198] - node _T_607 = and(_T_606, _T_602) @[dec_tlu_ctl.scala 2574:198] - node _T_608 = and(_T_607, _T_604) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mitcnt0 <= _T_608 @[dec_tlu_ctl.scala 2626:57] - node _T_609 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_610 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_611 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_612 = eq(_T_611, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_613 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_614 = and(_T_609, _T_610) @[dec_tlu_ctl.scala 2574:198] - node _T_615 = and(_T_614, _T_612) @[dec_tlu_ctl.scala 2574:198] - node _T_616 = and(_T_615, _T_613) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mitcnt1 <= _T_616 @[dec_tlu_ctl.scala 2627:57] - node _T_617 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_618 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_619 = eq(_T_618, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_620 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_621 = eq(_T_620, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_622 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_623 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_624 = and(_T_617, _T_619) @[dec_tlu_ctl.scala 2574:198] - node _T_625 = and(_T_624, _T_621) @[dec_tlu_ctl.scala 2574:198] - node _T_626 = and(_T_625, _T_622) @[dec_tlu_ctl.scala 2574:198] - node _T_627 = and(_T_626, _T_623) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mpmc <= _T_627 @[dec_tlu_ctl.scala 2628:57] - node _T_628 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_629 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_630 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_631 = eq(_T_630, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_632 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_634 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_635 = eq(_T_634, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_636 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_637 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 2574:198] - node _T_638 = and(_T_637, _T_631) @[dec_tlu_ctl.scala 2574:198] - node _T_639 = and(_T_638, _T_633) @[dec_tlu_ctl.scala 2574:198] - node _T_640 = and(_T_639, _T_635) @[dec_tlu_ctl.scala 2574:198] - node _T_641 = and(_T_640, _T_636) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mcpc <= _T_641 @[dec_tlu_ctl.scala 2629:57] - node _T_642 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_643 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_644 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_645 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_646 = eq(_T_645, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_647 = and(_T_642, _T_643) @[dec_tlu_ctl.scala 2574:198] - node _T_648 = and(_T_647, _T_644) @[dec_tlu_ctl.scala 2574:198] - node _T_649 = and(_T_648, _T_646) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_meicpct <= _T_649 @[dec_tlu_ctl.scala 2630:57] - node _T_650 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:149] - node _T_651 = eq(_T_650, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_652 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_653 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_654 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_655 = eq(_T_654, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_656 = and(_T_651, _T_652) @[dec_tlu_ctl.scala 2574:198] - node _T_657 = and(_T_656, _T_653) @[dec_tlu_ctl.scala 2574:198] - node _T_658 = and(_T_657, _T_655) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mdeau <= _T_658 @[dec_tlu_ctl.scala 2631:57] - node _T_659 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_660 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_661 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_662 = eq(_T_661, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_663 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_664 = eq(_T_663, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_665 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_666 = eq(_T_665, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_667 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 2574:198] - node _T_668 = and(_T_667, _T_662) @[dec_tlu_ctl.scala 2574:198] - node _T_669 = and(_T_668, _T_664) @[dec_tlu_ctl.scala 2574:198] - node _T_670 = and(_T_669, _T_666) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_micect <= _T_670 @[dec_tlu_ctl.scala 2632:57] - node _T_671 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_672 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_673 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_674 = eq(_T_673, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_675 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_676 = and(_T_671, _T_672) @[dec_tlu_ctl.scala 2574:198] - node _T_677 = and(_T_676, _T_674) @[dec_tlu_ctl.scala 2574:198] - node _T_678 = and(_T_677, _T_675) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_miccmect <= _T_678 @[dec_tlu_ctl.scala 2633:57] - node _T_679 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_680 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_681 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_682 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_683 = eq(_T_682, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_684 = and(_T_679, _T_680) @[dec_tlu_ctl.scala 2574:198] - node _T_685 = and(_T_684, _T_681) @[dec_tlu_ctl.scala 2574:198] - node _T_686 = and(_T_685, _T_683) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mdccmect <= _T_686 @[dec_tlu_ctl.scala 2634:57] - node _T_687 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_688 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:106] - node _T_689 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_690 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_691 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_692 = eq(_T_691, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_693 = and(_T_687, _T_688) @[dec_tlu_ctl.scala 2574:198] - node _T_694 = and(_T_693, _T_689) @[dec_tlu_ctl.scala 2574:198] - node _T_695 = and(_T_694, _T_690) @[dec_tlu_ctl.scala 2574:198] - node _T_696 = and(_T_695, _T_692) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mfdht <= _T_696 @[dec_tlu_ctl.scala 2635:57] - node _T_697 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_698 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_699 = eq(_T_698, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_700 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_701 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_702 = and(_T_697, _T_699) @[dec_tlu_ctl.scala 2574:198] - node _T_703 = and(_T_702, _T_700) @[dec_tlu_ctl.scala 2574:198] - node _T_704 = and(_T_703, _T_701) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_mfdhs <= _T_704 @[dec_tlu_ctl.scala 2636:57] - node _T_705 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_706 = eq(_T_705, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_707 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_708 = eq(_T_707, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_709 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:106] - node _T_710 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_711 = eq(_T_710, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_712 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_713 = eq(_T_712, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_714 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_715 = eq(_T_714, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_716 = and(_T_706, _T_708) @[dec_tlu_ctl.scala 2574:198] - node _T_717 = and(_T_716, _T_709) @[dec_tlu_ctl.scala 2574:198] - node _T_718 = and(_T_717, _T_711) @[dec_tlu_ctl.scala 2574:198] - node _T_719 = and(_T_718, _T_713) @[dec_tlu_ctl.scala 2574:198] - node _T_720 = and(_T_719, _T_715) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_dicawics <= _T_720 @[dec_tlu_ctl.scala 2637:57] - node _T_721 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_722 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:106] - node _T_723 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_724 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_725 = eq(_T_724, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_726 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 2574:198] - node _T_727 = and(_T_726, _T_723) @[dec_tlu_ctl.scala 2574:198] - node _T_728 = and(_T_727, _T_725) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_dicad0h <= _T_728 @[dec_tlu_ctl.scala 2638:57] - node _T_729 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_730 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_731 = eq(_T_730, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_732 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:106] - node _T_733 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_734 = eq(_T_733, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_735 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_736 = and(_T_729, _T_731) @[dec_tlu_ctl.scala 2574:198] - node _T_737 = and(_T_736, _T_732) @[dec_tlu_ctl.scala 2574:198] - node _T_738 = and(_T_737, _T_734) @[dec_tlu_ctl.scala 2574:198] - node _T_739 = and(_T_738, _T_735) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_dicad0 <= _T_739 @[dec_tlu_ctl.scala 2639:57] - node _T_740 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_741 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:106] - node _T_742 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_743 = eq(_T_742, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_744 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_745 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_746 = eq(_T_745, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_747 = and(_T_740, _T_741) @[dec_tlu_ctl.scala 2574:198] - node _T_748 = and(_T_747, _T_743) @[dec_tlu_ctl.scala 2574:198] - node _T_749 = and(_T_748, _T_744) @[dec_tlu_ctl.scala 2574:198] - node _T_750 = and(_T_749, _T_746) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_dicad1 <= _T_750 @[dec_tlu_ctl.scala 2640:57] - node _T_751 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_752 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:106] - node _T_753 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_754 = eq(_T_753, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_755 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_756 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_757 = and(_T_751, _T_752) @[dec_tlu_ctl.scala 2574:198] - node _T_758 = and(_T_757, _T_754) @[dec_tlu_ctl.scala 2574:198] - node _T_759 = and(_T_758, _T_755) @[dec_tlu_ctl.scala 2574:198] - node _T_760 = and(_T_759, _T_756) @[dec_tlu_ctl.scala 2574:198] - io.csr_pkt.csr_dicago <= _T_760 @[dec_tlu_ctl.scala 2641:57] - node _T_761 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_762 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:106] - node _T_763 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:106] - node _T_764 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_765 = eq(_T_764, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_766 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_767 = and(_T_761, _T_762) @[dec_tlu_ctl.scala 2574:198] - node _T_768 = and(_T_767, _T_763) @[dec_tlu_ctl.scala 2574:198] - node _T_769 = and(_T_768, _T_765) @[dec_tlu_ctl.scala 2574:198] - node _T_770 = and(_T_769, _T_766) @[dec_tlu_ctl.scala 2574:198] - node _T_771 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_772 = eq(_T_771, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_773 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_774 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_775 = eq(_T_774, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_776 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_777 = eq(_T_776, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_778 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_779 = eq(_T_778, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_780 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_781 = eq(_T_780, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_782 = and(_T_772, _T_773) @[dec_tlu_ctl.scala 2574:198] - node _T_783 = and(_T_782, _T_775) @[dec_tlu_ctl.scala 2574:198] - node _T_784 = and(_T_783, _T_777) @[dec_tlu_ctl.scala 2574:198] - node _T_785 = and(_T_784, _T_779) @[dec_tlu_ctl.scala 2574:198] - node _T_786 = and(_T_785, _T_781) @[dec_tlu_ctl.scala 2574:198] - node _T_787 = or(_T_770, _T_786) @[dec_tlu_ctl.scala 2642:81] - node _T_788 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_789 = eq(_T_788, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_790 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_791 = eq(_T_790, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_792 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_793 = eq(_T_792, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_794 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_795 = eq(_T_794, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_796 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_797 = eq(_T_796, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_798 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_799 = and(_T_789, _T_791) @[dec_tlu_ctl.scala 2574:198] - node _T_800 = and(_T_799, _T_793) @[dec_tlu_ctl.scala 2574:198] - node _T_801 = and(_T_800, _T_795) @[dec_tlu_ctl.scala 2574:198] - node _T_802 = and(_T_801, _T_797) @[dec_tlu_ctl.scala 2574:198] - node _T_803 = and(_T_802, _T_798) @[dec_tlu_ctl.scala 2574:198] - node _T_804 = or(_T_787, _T_803) @[dec_tlu_ctl.scala 2642:121] - node _T_805 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_806 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_807 = eq(_T_806, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_808 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_809 = eq(_T_808, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_810 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_811 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_812 = eq(_T_811, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_813 = and(_T_805, _T_807) @[dec_tlu_ctl.scala 2574:198] - node _T_814 = and(_T_813, _T_809) @[dec_tlu_ctl.scala 2574:198] - node _T_815 = and(_T_814, _T_810) @[dec_tlu_ctl.scala 2574:198] - node _T_816 = and(_T_815, _T_812) @[dec_tlu_ctl.scala 2574:198] - node _T_817 = or(_T_804, _T_816) @[dec_tlu_ctl.scala 2642:155] - node _T_818 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_819 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_820 = eq(_T_819, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_821 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_822 = eq(_T_821, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_823 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_824 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_825 = eq(_T_824, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_826 = and(_T_818, _T_820) @[dec_tlu_ctl.scala 2574:198] - node _T_827 = and(_T_826, _T_822) @[dec_tlu_ctl.scala 2574:198] - node _T_828 = and(_T_827, _T_823) @[dec_tlu_ctl.scala 2574:198] - node _T_829 = and(_T_828, _T_825) @[dec_tlu_ctl.scala 2574:198] - node _T_830 = or(_T_817, _T_829) @[dec_tlu_ctl.scala 2643:97] - node _T_831 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_832 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_833 = eq(_T_832, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_834 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_835 = eq(_T_834, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_836 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_837 = eq(_T_836, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_838 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_839 = eq(_T_838, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_840 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_841 = and(_T_831, _T_833) @[dec_tlu_ctl.scala 2574:198] - node _T_842 = and(_T_841, _T_835) @[dec_tlu_ctl.scala 2574:198] - node _T_843 = and(_T_842, _T_837) @[dec_tlu_ctl.scala 2574:198] - node _T_844 = and(_T_843, _T_839) @[dec_tlu_ctl.scala 2574:198] - node _T_845 = and(_T_844, _T_840) @[dec_tlu_ctl.scala 2574:198] - node _T_846 = or(_T_830, _T_845) @[dec_tlu_ctl.scala 2643:137] - io.csr_pkt.presync <= _T_846 @[dec_tlu_ctl.scala 2642:34] - node _T_847 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_848 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:106] - node _T_849 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:106] - node _T_850 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_851 = eq(_T_850, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_852 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_853 = and(_T_847, _T_848) @[dec_tlu_ctl.scala 2574:198] - node _T_854 = and(_T_853, _T_849) @[dec_tlu_ctl.scala 2574:198] - node _T_855 = and(_T_854, _T_851) @[dec_tlu_ctl.scala 2574:198] - node _T_856 = and(_T_855, _T_852) @[dec_tlu_ctl.scala 2574:198] - node _T_857 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_858 = eq(_T_857, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_859 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_860 = eq(_T_859, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_861 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_862 = eq(_T_861, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_863 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_864 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_865 = and(_T_858, _T_860) @[dec_tlu_ctl.scala 2574:198] - node _T_866 = and(_T_865, _T_862) @[dec_tlu_ctl.scala 2574:198] - node _T_867 = and(_T_866, _T_863) @[dec_tlu_ctl.scala 2574:198] - node _T_868 = and(_T_867, _T_864) @[dec_tlu_ctl.scala 2574:198] - node _T_869 = or(_T_856, _T_868) @[dec_tlu_ctl.scala 2644:81] - node _T_870 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_871 = eq(_T_870, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_872 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_873 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_874 = eq(_T_873, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_875 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_876 = and(_T_871, _T_872) @[dec_tlu_ctl.scala 2574:198] - node _T_877 = and(_T_876, _T_874) @[dec_tlu_ctl.scala 2574:198] - node _T_878 = and(_T_877, _T_875) @[dec_tlu_ctl.scala 2574:198] - node _T_879 = or(_T_869, _T_878) @[dec_tlu_ctl.scala 2644:121] - node _T_880 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_881 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_882 = eq(_T_881, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_883 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_884 = eq(_T_883, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_885 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_886 = and(_T_880, _T_882) @[dec_tlu_ctl.scala 2574:198] - node _T_887 = and(_T_886, _T_884) @[dec_tlu_ctl.scala 2574:198] - node _T_888 = and(_T_887, _T_885) @[dec_tlu_ctl.scala 2574:198] - node _T_889 = or(_T_879, _T_888) @[dec_tlu_ctl.scala 2644:162] - node _T_890 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_891 = eq(_T_890, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_892 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_893 = eq(_T_892, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_894 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_895 = eq(_T_894, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_896 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_897 = eq(_T_896, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_898 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_899 = eq(_T_898, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_900 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_901 = eq(_T_900, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_902 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_903 = eq(_T_902, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_904 = and(_T_891, _T_893) @[dec_tlu_ctl.scala 2574:198] - node _T_905 = and(_T_904, _T_895) @[dec_tlu_ctl.scala 2574:198] - node _T_906 = and(_T_905, _T_897) @[dec_tlu_ctl.scala 2574:198] - node _T_907 = and(_T_906, _T_899) @[dec_tlu_ctl.scala 2574:198] - node _T_908 = and(_T_907, _T_901) @[dec_tlu_ctl.scala 2574:198] - node _T_909 = and(_T_908, _T_903) @[dec_tlu_ctl.scala 2574:198] - node _T_910 = or(_T_889, _T_909) @[dec_tlu_ctl.scala 2645:105] - node _T_911 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_912 = eq(_T_911, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_913 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_914 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_915 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_916 = eq(_T_915, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_917 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_918 = eq(_T_917, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_919 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_920 = eq(_T_919, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_921 = and(_T_912, _T_913) @[dec_tlu_ctl.scala 2574:198] - node _T_922 = and(_T_921, _T_914) @[dec_tlu_ctl.scala 2574:198] - node _T_923 = and(_T_922, _T_916) @[dec_tlu_ctl.scala 2574:198] - node _T_924 = and(_T_923, _T_918) @[dec_tlu_ctl.scala 2574:198] - node _T_925 = and(_T_924, _T_920) @[dec_tlu_ctl.scala 2574:198] - node _T_926 = or(_T_910, _T_925) @[dec_tlu_ctl.scala 2645:145] - node _T_927 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_928 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_929 = eq(_T_928, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_930 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_931 = eq(_T_930, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_932 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_933 = eq(_T_932, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_934 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_935 = and(_T_927, _T_929) @[dec_tlu_ctl.scala 2574:198] - node _T_936 = and(_T_935, _T_931) @[dec_tlu_ctl.scala 2574:198] - node _T_937 = and(_T_936, _T_933) @[dec_tlu_ctl.scala 2574:198] - node _T_938 = and(_T_937, _T_934) @[dec_tlu_ctl.scala 2574:198] - node _T_939 = or(_T_926, _T_938) @[dec_tlu_ctl.scala 2645:178] - io.csr_pkt.postsync <= _T_939 @[dec_tlu_ctl.scala 2644:30] - node _T_940 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_941 = eq(_T_940, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_942 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_943 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_944 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_945 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_946 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_947 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:106] - node _T_948 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_949 = eq(_T_948, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_950 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_951 = eq(_T_950, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_952 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_953 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_954 = eq(_T_953, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_955 = and(_T_941, _T_942) @[dec_tlu_ctl.scala 2574:198] - node _T_956 = and(_T_955, _T_943) @[dec_tlu_ctl.scala 2574:198] - node _T_957 = and(_T_956, _T_944) @[dec_tlu_ctl.scala 2574:198] - node _T_958 = and(_T_957, _T_945) @[dec_tlu_ctl.scala 2574:198] - node _T_959 = and(_T_958, _T_946) @[dec_tlu_ctl.scala 2574:198] - node _T_960 = and(_T_959, _T_947) @[dec_tlu_ctl.scala 2574:198] - node _T_961 = and(_T_960, _T_949) @[dec_tlu_ctl.scala 2574:198] - node _T_962 = and(_T_961, _T_951) @[dec_tlu_ctl.scala 2574:198] - node _T_963 = and(_T_962, _T_952) @[dec_tlu_ctl.scala 2574:198] - node _T_964 = and(_T_963, _T_954) @[dec_tlu_ctl.scala 2574:198] - node _T_965 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_966 = eq(_T_965, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_967 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:149] - node _T_968 = eq(_T_967, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_969 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_970 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_971 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_972 = eq(_T_971, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_973 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_974 = eq(_T_973, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_975 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_976 = eq(_T_975, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_977 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_978 = eq(_T_977, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_979 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_981 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_983 = and(_T_966, _T_968) @[dec_tlu_ctl.scala 2574:198] - node _T_984 = and(_T_983, _T_969) @[dec_tlu_ctl.scala 2574:198] - node _T_985 = and(_T_984, _T_970) @[dec_tlu_ctl.scala 2574:198] - node _T_986 = and(_T_985, _T_972) @[dec_tlu_ctl.scala 2574:198] - node _T_987 = and(_T_986, _T_974) @[dec_tlu_ctl.scala 2574:198] - node _T_988 = and(_T_987, _T_976) @[dec_tlu_ctl.scala 2574:198] - node _T_989 = and(_T_988, _T_978) @[dec_tlu_ctl.scala 2574:198] - node _T_990 = and(_T_989, _T_980) @[dec_tlu_ctl.scala 2574:198] - node _T_991 = and(_T_990, _T_982) @[dec_tlu_ctl.scala 2574:198] - node _T_992 = or(_T_964, _T_991) @[dec_tlu_ctl.scala 2647:81] - node _T_993 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_994 = eq(_T_993, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_995 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:149] - node _T_996 = eq(_T_995, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_997 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_998 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_999 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_1000 = eq(_T_999, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1001 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1003 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_1004 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_1005 = eq(_T_1004, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1006 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_1008 = and(_T_994, _T_996) @[dec_tlu_ctl.scala 2574:198] - node _T_1009 = and(_T_1008, _T_997) @[dec_tlu_ctl.scala 2574:198] - node _T_1010 = and(_T_1009, _T_998) @[dec_tlu_ctl.scala 2574:198] - node _T_1011 = and(_T_1010, _T_1000) @[dec_tlu_ctl.scala 2574:198] - node _T_1012 = and(_T_1011, _T_1002) @[dec_tlu_ctl.scala 2574:198] - node _T_1013 = and(_T_1012, _T_1003) @[dec_tlu_ctl.scala 2574:198] - node _T_1014 = and(_T_1013, _T_1005) @[dec_tlu_ctl.scala 2574:198] - node _T_1015 = and(_T_1014, _T_1007) @[dec_tlu_ctl.scala 2574:198] - node _T_1016 = or(_T_992, _T_1015) @[dec_tlu_ctl.scala 2647:129] - node _T_1017 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_1018 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1019 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1020 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_1021 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_1022 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1024 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1026 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1028 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1030 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_1032 = and(_T_1017, _T_1018) @[dec_tlu_ctl.scala 2574:198] - node _T_1033 = and(_T_1032, _T_1019) @[dec_tlu_ctl.scala 2574:198] - node _T_1034 = and(_T_1033, _T_1020) @[dec_tlu_ctl.scala 2574:198] - node _T_1035 = and(_T_1034, _T_1021) @[dec_tlu_ctl.scala 2574:198] - node _T_1036 = and(_T_1035, _T_1023) @[dec_tlu_ctl.scala 2574:198] - node _T_1037 = and(_T_1036, _T_1025) @[dec_tlu_ctl.scala 2574:198] - node _T_1038 = and(_T_1037, _T_1027) @[dec_tlu_ctl.scala 2574:198] - node _T_1039 = and(_T_1038, _T_1029) @[dec_tlu_ctl.scala 2574:198] - node _T_1040 = and(_T_1039, _T_1031) @[dec_tlu_ctl.scala 2574:198] - node _T_1041 = or(_T_1016, _T_1040) @[dec_tlu_ctl.scala 2648:105] - node _T_1042 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_1043 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:149] - node _T_1044 = eq(_T_1043, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1045 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1046 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1047 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1049 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1051 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_1053 = and(_T_1042, _T_1044) @[dec_tlu_ctl.scala 2574:198] - node _T_1054 = and(_T_1053, _T_1045) @[dec_tlu_ctl.scala 2574:198] - node _T_1055 = and(_T_1054, _T_1046) @[dec_tlu_ctl.scala 2574:198] - node _T_1056 = and(_T_1055, _T_1048) @[dec_tlu_ctl.scala 2574:198] - node _T_1057 = and(_T_1056, _T_1050) @[dec_tlu_ctl.scala 2574:198] - node _T_1058 = and(_T_1057, _T_1052) @[dec_tlu_ctl.scala 2574:198] - node _T_1059 = or(_T_1041, _T_1058) @[dec_tlu_ctl.scala 2648:153] - node _T_1060 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1062 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_1063 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1064 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1065 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_1066 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_1067 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_1068 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:106] - node _T_1069 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:106] - node _T_1070 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_1071 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_1072 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_1073 = and(_T_1061, _T_1062) @[dec_tlu_ctl.scala 2574:198] - node _T_1074 = and(_T_1073, _T_1063) @[dec_tlu_ctl.scala 2574:198] - node _T_1075 = and(_T_1074, _T_1064) @[dec_tlu_ctl.scala 2574:198] - node _T_1076 = and(_T_1075, _T_1065) @[dec_tlu_ctl.scala 2574:198] - node _T_1077 = and(_T_1076, _T_1066) @[dec_tlu_ctl.scala 2574:198] - node _T_1078 = and(_T_1077, _T_1067) @[dec_tlu_ctl.scala 2574:198] - node _T_1079 = and(_T_1078, _T_1068) @[dec_tlu_ctl.scala 2574:198] - node _T_1080 = and(_T_1079, _T_1069) @[dec_tlu_ctl.scala 2574:198] - node _T_1081 = and(_T_1080, _T_1070) @[dec_tlu_ctl.scala 2574:198] - node _T_1082 = and(_T_1081, _T_1071) @[dec_tlu_ctl.scala 2574:198] - node _T_1083 = and(_T_1082, _T_1072) @[dec_tlu_ctl.scala 2574:198] - node _T_1084 = or(_T_1059, _T_1083) @[dec_tlu_ctl.scala 2649:105] - node _T_1085 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_1086 = eq(_T_1085, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1087 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_1088 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1089 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1090 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_1091 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_1092 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_1093 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:106] - node _T_1094 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_1095 = eq(_T_1094, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1096 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1098 = and(_T_1086, _T_1087) @[dec_tlu_ctl.scala 2574:198] - node _T_1099 = and(_T_1098, _T_1088) @[dec_tlu_ctl.scala 2574:198] - node _T_1100 = and(_T_1099, _T_1089) @[dec_tlu_ctl.scala 2574:198] - node _T_1101 = and(_T_1100, _T_1090) @[dec_tlu_ctl.scala 2574:198] - node _T_1102 = and(_T_1101, _T_1091) @[dec_tlu_ctl.scala 2574:198] - node _T_1103 = and(_T_1102, _T_1092) @[dec_tlu_ctl.scala 2574:198] - node _T_1104 = and(_T_1103, _T_1093) @[dec_tlu_ctl.scala 2574:198] - node _T_1105 = and(_T_1104, _T_1095) @[dec_tlu_ctl.scala 2574:198] - node _T_1106 = and(_T_1105, _T_1097) @[dec_tlu_ctl.scala 2574:198] - node _T_1107 = or(_T_1084, _T_1106) @[dec_tlu_ctl.scala 2649:153] - node _T_1108 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_1109 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1110 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1111 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_1112 = eq(_T_1111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1113 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_1114 = eq(_T_1113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1115 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_1116 = eq(_T_1115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1117 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:106] - node _T_1118 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_1119 = eq(_T_1118, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1120 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_1121 = eq(_T_1120, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1122 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_1123 = and(_T_1108, _T_1109) @[dec_tlu_ctl.scala 2574:198] - node _T_1124 = and(_T_1123, _T_1110) @[dec_tlu_ctl.scala 2574:198] - node _T_1125 = and(_T_1124, _T_1112) @[dec_tlu_ctl.scala 2574:198] - node _T_1126 = and(_T_1125, _T_1114) @[dec_tlu_ctl.scala 2574:198] - node _T_1127 = and(_T_1126, _T_1116) @[dec_tlu_ctl.scala 2574:198] - node _T_1128 = and(_T_1127, _T_1117) @[dec_tlu_ctl.scala 2574:198] - node _T_1129 = and(_T_1128, _T_1119) @[dec_tlu_ctl.scala 2574:198] - node _T_1130 = and(_T_1129, _T_1121) @[dec_tlu_ctl.scala 2574:198] - node _T_1131 = and(_T_1130, _T_1122) @[dec_tlu_ctl.scala 2574:198] - node _T_1132 = or(_T_1107, _T_1131) @[dec_tlu_ctl.scala 2650:105] - node _T_1133 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1135 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_1136 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1137 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1138 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_1139 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_1140 = eq(_T_1139, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1141 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_1142 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_1143 = eq(_T_1142, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1144 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1146 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1148 = and(_T_1134, _T_1135) @[dec_tlu_ctl.scala 2574:198] - node _T_1149 = and(_T_1148, _T_1136) @[dec_tlu_ctl.scala 2574:198] - node _T_1150 = and(_T_1149, _T_1137) @[dec_tlu_ctl.scala 2574:198] - node _T_1151 = and(_T_1150, _T_1138) @[dec_tlu_ctl.scala 2574:198] - node _T_1152 = and(_T_1151, _T_1140) @[dec_tlu_ctl.scala 2574:198] - node _T_1153 = and(_T_1152, _T_1141) @[dec_tlu_ctl.scala 2574:198] - node _T_1154 = and(_T_1153, _T_1143) @[dec_tlu_ctl.scala 2574:198] - node _T_1155 = and(_T_1154, _T_1145) @[dec_tlu_ctl.scala 2574:198] - node _T_1156 = and(_T_1155, _T_1147) @[dec_tlu_ctl.scala 2574:198] - node _T_1157 = or(_T_1132, _T_1156) @[dec_tlu_ctl.scala 2650:161] - node _T_1158 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1160 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:149] - node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1162 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1163 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1164 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_1165 = eq(_T_1164, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1166 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_1167 = eq(_T_1166, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1168 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_1169 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_1170 = and(_T_1159, _T_1161) @[dec_tlu_ctl.scala 2574:198] - node _T_1171 = and(_T_1170, _T_1162) @[dec_tlu_ctl.scala 2574:198] - node _T_1172 = and(_T_1171, _T_1163) @[dec_tlu_ctl.scala 2574:198] - node _T_1173 = and(_T_1172, _T_1165) @[dec_tlu_ctl.scala 2574:198] - node _T_1174 = and(_T_1173, _T_1167) @[dec_tlu_ctl.scala 2574:198] - node _T_1175 = and(_T_1174, _T_1168) @[dec_tlu_ctl.scala 2574:198] - node _T_1176 = and(_T_1175, _T_1169) @[dec_tlu_ctl.scala 2574:198] - node _T_1177 = or(_T_1157, _T_1176) @[dec_tlu_ctl.scala 2651:105] - node _T_1178 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_1179 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1180 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1181 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_1182 = eq(_T_1181, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1183 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_1184 = eq(_T_1183, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1185 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_1186 = eq(_T_1185, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1187 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:106] - node _T_1188 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_1189 = eq(_T_1188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1190 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_1191 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_1192 = eq(_T_1191, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1193 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_1194 = eq(_T_1193, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_1195 = and(_T_1178, _T_1179) @[dec_tlu_ctl.scala 2574:198] - node _T_1196 = and(_T_1195, _T_1180) @[dec_tlu_ctl.scala 2574:198] - node _T_1197 = and(_T_1196, _T_1182) @[dec_tlu_ctl.scala 2574:198] - node _T_1198 = and(_T_1197, _T_1184) @[dec_tlu_ctl.scala 2574:198] - node _T_1199 = and(_T_1198, _T_1186) @[dec_tlu_ctl.scala 2574:198] - node _T_1200 = and(_T_1199, _T_1187) @[dec_tlu_ctl.scala 2574:198] - node _T_1201 = and(_T_1200, _T_1189) @[dec_tlu_ctl.scala 2574:198] - node _T_1202 = and(_T_1201, _T_1190) @[dec_tlu_ctl.scala 2574:198] - node _T_1203 = and(_T_1202, _T_1192) @[dec_tlu_ctl.scala 2574:198] - node _T_1204 = and(_T_1203, _T_1194) @[dec_tlu_ctl.scala 2574:198] - node _T_1205 = or(_T_1177, _T_1204) @[dec_tlu_ctl.scala 2651:161] - node _T_1206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1208 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_1209 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1210 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1211 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_1212 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_1213 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1215 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1217 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:106] - node _T_1218 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_1219 = and(_T_1207, _T_1208) @[dec_tlu_ctl.scala 2574:198] - node _T_1220 = and(_T_1219, _T_1209) @[dec_tlu_ctl.scala 2574:198] - node _T_1221 = and(_T_1220, _T_1210) @[dec_tlu_ctl.scala 2574:198] - node _T_1222 = and(_T_1221, _T_1211) @[dec_tlu_ctl.scala 2574:198] - node _T_1223 = and(_T_1222, _T_1212) @[dec_tlu_ctl.scala 2574:198] - node _T_1224 = and(_T_1223, _T_1214) @[dec_tlu_ctl.scala 2574:198] - node _T_1225 = and(_T_1224, _T_1216) @[dec_tlu_ctl.scala 2574:198] - node _T_1226 = and(_T_1225, _T_1217) @[dec_tlu_ctl.scala 2574:198] - node _T_1227 = and(_T_1226, _T_1218) @[dec_tlu_ctl.scala 2574:198] - node _T_1228 = or(_T_1205, _T_1227) @[dec_tlu_ctl.scala 2652:97] - node _T_1229 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1231 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_1232 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1233 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1234 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_1235 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_1236 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1238 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:106] - node _T_1239 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1241 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_1242 = and(_T_1230, _T_1231) @[dec_tlu_ctl.scala 2574:198] - node _T_1243 = and(_T_1242, _T_1232) @[dec_tlu_ctl.scala 2574:198] - node _T_1244 = and(_T_1243, _T_1233) @[dec_tlu_ctl.scala 2574:198] - node _T_1245 = and(_T_1244, _T_1234) @[dec_tlu_ctl.scala 2574:198] - node _T_1246 = and(_T_1245, _T_1235) @[dec_tlu_ctl.scala 2574:198] - node _T_1247 = and(_T_1246, _T_1237) @[dec_tlu_ctl.scala 2574:198] - node _T_1248 = and(_T_1247, _T_1238) @[dec_tlu_ctl.scala 2574:198] - node _T_1249 = and(_T_1248, _T_1240) @[dec_tlu_ctl.scala 2574:198] - node _T_1250 = and(_T_1249, _T_1241) @[dec_tlu_ctl.scala 2574:198] - node _T_1251 = or(_T_1228, _T_1250) @[dec_tlu_ctl.scala 2652:153] - node _T_1252 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_1253 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1254 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1255 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_1256 = eq(_T_1255, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1257 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_1258 = eq(_T_1257, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1259 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_1260 = eq(_T_1259, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1261 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:106] - node _T_1262 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1264 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1266 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_1267 = and(_T_1252, _T_1253) @[dec_tlu_ctl.scala 2574:198] - node _T_1268 = and(_T_1267, _T_1254) @[dec_tlu_ctl.scala 2574:198] - node _T_1269 = and(_T_1268, _T_1256) @[dec_tlu_ctl.scala 2574:198] - node _T_1270 = and(_T_1269, _T_1258) @[dec_tlu_ctl.scala 2574:198] - node _T_1271 = and(_T_1270, _T_1260) @[dec_tlu_ctl.scala 2574:198] - node _T_1272 = and(_T_1271, _T_1261) @[dec_tlu_ctl.scala 2574:198] - node _T_1273 = and(_T_1272, _T_1263) @[dec_tlu_ctl.scala 2574:198] - node _T_1274 = and(_T_1273, _T_1265) @[dec_tlu_ctl.scala 2574:198] - node _T_1275 = and(_T_1274, _T_1266) @[dec_tlu_ctl.scala 2574:198] - node _T_1276 = or(_T_1251, _T_1275) @[dec_tlu_ctl.scala 2653:105] - node _T_1277 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1279 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:149] - node _T_1280 = eq(_T_1279, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1281 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1282 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1283 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_1284 = eq(_T_1283, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1285 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_1286 = eq(_T_1285, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1287 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_1288 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_1289 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:106] - node _T_1290 = and(_T_1278, _T_1280) @[dec_tlu_ctl.scala 2574:198] - node _T_1291 = and(_T_1290, _T_1281) @[dec_tlu_ctl.scala 2574:198] - node _T_1292 = and(_T_1291, _T_1282) @[dec_tlu_ctl.scala 2574:198] - node _T_1293 = and(_T_1292, _T_1284) @[dec_tlu_ctl.scala 2574:198] - node _T_1294 = and(_T_1293, _T_1286) @[dec_tlu_ctl.scala 2574:198] - node _T_1295 = and(_T_1294, _T_1287) @[dec_tlu_ctl.scala 2574:198] - node _T_1296 = and(_T_1295, _T_1288) @[dec_tlu_ctl.scala 2574:198] - node _T_1297 = and(_T_1296, _T_1289) @[dec_tlu_ctl.scala 2574:198] - node _T_1298 = or(_T_1276, _T_1297) @[dec_tlu_ctl.scala 2653:161] - node _T_1299 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_1300 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:149] - node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1302 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1303 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1304 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_1305 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1307 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1309 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:106] - node _T_1310 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1312 = and(_T_1299, _T_1301) @[dec_tlu_ctl.scala 2574:198] - node _T_1313 = and(_T_1312, _T_1302) @[dec_tlu_ctl.scala 2574:198] - node _T_1314 = and(_T_1313, _T_1303) @[dec_tlu_ctl.scala 2574:198] - node _T_1315 = and(_T_1314, _T_1304) @[dec_tlu_ctl.scala 2574:198] - node _T_1316 = and(_T_1315, _T_1306) @[dec_tlu_ctl.scala 2574:198] - node _T_1317 = and(_T_1316, _T_1308) @[dec_tlu_ctl.scala 2574:198] - node _T_1318 = and(_T_1317, _T_1309) @[dec_tlu_ctl.scala 2574:198] - node _T_1319 = and(_T_1318, _T_1311) @[dec_tlu_ctl.scala 2574:198] - node _T_1320 = or(_T_1298, _T_1319) @[dec_tlu_ctl.scala 2654:105] - node _T_1321 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_1322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:149] - node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1324 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1325 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1326 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_1327 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1329 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1331 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:106] - node _T_1332 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1334 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_1336 = and(_T_1321, _T_1323) @[dec_tlu_ctl.scala 2574:198] - node _T_1337 = and(_T_1336, _T_1324) @[dec_tlu_ctl.scala 2574:198] - node _T_1338 = and(_T_1337, _T_1325) @[dec_tlu_ctl.scala 2574:198] - node _T_1339 = and(_T_1338, _T_1326) @[dec_tlu_ctl.scala 2574:198] - node _T_1340 = and(_T_1339, _T_1328) @[dec_tlu_ctl.scala 2574:198] - node _T_1341 = and(_T_1340, _T_1330) @[dec_tlu_ctl.scala 2574:198] - node _T_1342 = and(_T_1341, _T_1331) @[dec_tlu_ctl.scala 2574:198] - node _T_1343 = and(_T_1342, _T_1333) @[dec_tlu_ctl.scala 2574:198] - node _T_1344 = and(_T_1343, _T_1335) @[dec_tlu_ctl.scala 2574:198] - node _T_1345 = or(_T_1320, _T_1344) @[dec_tlu_ctl.scala 2654:161] - node _T_1346 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_1347 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:149] - node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1349 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1350 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1351 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_1352 = eq(_T_1351, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1353 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_1354 = eq(_T_1353, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1355 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:106] - node _T_1356 = and(_T_1346, _T_1348) @[dec_tlu_ctl.scala 2574:198] - node _T_1357 = and(_T_1356, _T_1349) @[dec_tlu_ctl.scala 2574:198] - node _T_1358 = and(_T_1357, _T_1350) @[dec_tlu_ctl.scala 2574:198] - node _T_1359 = and(_T_1358, _T_1352) @[dec_tlu_ctl.scala 2574:198] - node _T_1360 = and(_T_1359, _T_1354) @[dec_tlu_ctl.scala 2574:198] - node _T_1361 = and(_T_1360, _T_1355) @[dec_tlu_ctl.scala 2574:198] - node _T_1362 = or(_T_1345, _T_1361) @[dec_tlu_ctl.scala 2655:105] - node _T_1363 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1365 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_1366 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1367 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1368 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_1369 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_1370 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_1371 = eq(_T_1370, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1372 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:106] - node _T_1373 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_1374 = eq(_T_1373, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1375 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_1376 = and(_T_1364, _T_1365) @[dec_tlu_ctl.scala 2574:198] - node _T_1377 = and(_T_1376, _T_1366) @[dec_tlu_ctl.scala 2574:198] - node _T_1378 = and(_T_1377, _T_1367) @[dec_tlu_ctl.scala 2574:198] - node _T_1379 = and(_T_1378, _T_1368) @[dec_tlu_ctl.scala 2574:198] - node _T_1380 = and(_T_1379, _T_1369) @[dec_tlu_ctl.scala 2574:198] - node _T_1381 = and(_T_1380, _T_1371) @[dec_tlu_ctl.scala 2574:198] - node _T_1382 = and(_T_1381, _T_1372) @[dec_tlu_ctl.scala 2574:198] - node _T_1383 = and(_T_1382, _T_1374) @[dec_tlu_ctl.scala 2574:198] - node _T_1384 = and(_T_1383, _T_1375) @[dec_tlu_ctl.scala 2574:198] - node _T_1385 = or(_T_1362, _T_1384) @[dec_tlu_ctl.scala 2655:161] - node _T_1386 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1388 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_1389 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1390 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1391 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_1392 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_1393 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_1394 = eq(_T_1393, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1395 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_1396 = eq(_T_1395, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1397 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_1399 = and(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2574:198] - node _T_1400 = and(_T_1399, _T_1389) @[dec_tlu_ctl.scala 2574:198] - node _T_1401 = and(_T_1400, _T_1390) @[dec_tlu_ctl.scala 2574:198] - node _T_1402 = and(_T_1401, _T_1391) @[dec_tlu_ctl.scala 2574:198] - node _T_1403 = and(_T_1402, _T_1392) @[dec_tlu_ctl.scala 2574:198] - node _T_1404 = and(_T_1403, _T_1394) @[dec_tlu_ctl.scala 2574:198] - node _T_1405 = and(_T_1404, _T_1396) @[dec_tlu_ctl.scala 2574:198] - node _T_1406 = and(_T_1405, _T_1398) @[dec_tlu_ctl.scala 2574:198] - node _T_1407 = or(_T_1385, _T_1406) @[dec_tlu_ctl.scala 2656:105] - node _T_1408 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1410 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_1411 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1412 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1413 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_1414 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_1415 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_1416 = eq(_T_1415, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1417 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_1418 = eq(_T_1417, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1419 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:106] - node _T_1420 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1422 = and(_T_1409, _T_1410) @[dec_tlu_ctl.scala 2574:198] - node _T_1423 = and(_T_1422, _T_1411) @[dec_tlu_ctl.scala 2574:198] - node _T_1424 = and(_T_1423, _T_1412) @[dec_tlu_ctl.scala 2574:198] - node _T_1425 = and(_T_1424, _T_1413) @[dec_tlu_ctl.scala 2574:198] - node _T_1426 = and(_T_1425, _T_1414) @[dec_tlu_ctl.scala 2574:198] - node _T_1427 = and(_T_1426, _T_1416) @[dec_tlu_ctl.scala 2574:198] - node _T_1428 = and(_T_1427, _T_1418) @[dec_tlu_ctl.scala 2574:198] - node _T_1429 = and(_T_1428, _T_1419) @[dec_tlu_ctl.scala 2574:198] - node _T_1430 = and(_T_1429, _T_1421) @[dec_tlu_ctl.scala 2574:198] - node _T_1431 = or(_T_1407, _T_1430) @[dec_tlu_ctl.scala 2656:161] - node _T_1432 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1434 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:106] - node _T_1435 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1436 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1437 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:106] - node _T_1438 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1440 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_1441 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_1442 = eq(_T_1441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1443 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1445 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1447 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_1448 = eq(_T_1447, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_1449 = and(_T_1433, _T_1434) @[dec_tlu_ctl.scala 2574:198] - node _T_1450 = and(_T_1449, _T_1435) @[dec_tlu_ctl.scala 2574:198] - node _T_1451 = and(_T_1450, _T_1436) @[dec_tlu_ctl.scala 2574:198] - node _T_1452 = and(_T_1451, _T_1437) @[dec_tlu_ctl.scala 2574:198] - node _T_1453 = and(_T_1452, _T_1439) @[dec_tlu_ctl.scala 2574:198] - node _T_1454 = and(_T_1453, _T_1440) @[dec_tlu_ctl.scala 2574:198] - node _T_1455 = and(_T_1454, _T_1442) @[dec_tlu_ctl.scala 2574:198] - node _T_1456 = and(_T_1455, _T_1444) @[dec_tlu_ctl.scala 2574:198] - node _T_1457 = and(_T_1456, _T_1446) @[dec_tlu_ctl.scala 2574:198] - node _T_1458 = and(_T_1457, _T_1448) @[dec_tlu_ctl.scala 2574:198] - node _T_1459 = or(_T_1431, _T_1458) @[dec_tlu_ctl.scala 2657:105] - node _T_1460 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_1461 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:149] - node _T_1462 = eq(_T_1461, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1463 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1464 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1465 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1467 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1469 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:106] - node _T_1470 = and(_T_1460, _T_1462) @[dec_tlu_ctl.scala 2574:198] - node _T_1471 = and(_T_1470, _T_1463) @[dec_tlu_ctl.scala 2574:198] - node _T_1472 = and(_T_1471, _T_1464) @[dec_tlu_ctl.scala 2574:198] - node _T_1473 = and(_T_1472, _T_1466) @[dec_tlu_ctl.scala 2574:198] - node _T_1474 = and(_T_1473, _T_1468) @[dec_tlu_ctl.scala 2574:198] - node _T_1475 = and(_T_1474, _T_1469) @[dec_tlu_ctl.scala 2574:198] - node _T_1476 = or(_T_1459, _T_1475) @[dec_tlu_ctl.scala 2657:153] - node _T_1477 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1479 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:149] - node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1481 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1482 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1483 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1485 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:106] - node _T_1486 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_1487 = eq(_T_1486, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1488 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_1489 = eq(_T_1488, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1490 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1492 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2574:149] - node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1494 = and(_T_1478, _T_1480) @[dec_tlu_ctl.scala 2574:198] - node _T_1495 = and(_T_1494, _T_1481) @[dec_tlu_ctl.scala 2574:198] - node _T_1496 = and(_T_1495, _T_1482) @[dec_tlu_ctl.scala 2574:198] - node _T_1497 = and(_T_1496, _T_1484) @[dec_tlu_ctl.scala 2574:198] - node _T_1498 = and(_T_1497, _T_1485) @[dec_tlu_ctl.scala 2574:198] - node _T_1499 = and(_T_1498, _T_1487) @[dec_tlu_ctl.scala 2574:198] - node _T_1500 = and(_T_1499, _T_1489) @[dec_tlu_ctl.scala 2574:198] - node _T_1501 = and(_T_1500, _T_1491) @[dec_tlu_ctl.scala 2574:198] - node _T_1502 = and(_T_1501, _T_1493) @[dec_tlu_ctl.scala 2574:198] - node _T_1503 = or(_T_1476, _T_1502) @[dec_tlu_ctl.scala 2658:113] - node _T_1504 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_1505 = eq(_T_1504, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1506 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:149] - node _T_1507 = eq(_T_1506, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1508 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1509 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1510 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_1511 = eq(_T_1510, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1512 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1514 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:149] - node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1516 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:149] - node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1518 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2574:149] - node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1520 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2574:185] - node _T_1521 = eq(_T_1520, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:165] - node _T_1522 = and(_T_1505, _T_1507) @[dec_tlu_ctl.scala 2574:198] - node _T_1523 = and(_T_1522, _T_1508) @[dec_tlu_ctl.scala 2574:198] - node _T_1524 = and(_T_1523, _T_1509) @[dec_tlu_ctl.scala 2574:198] - node _T_1525 = and(_T_1524, _T_1511) @[dec_tlu_ctl.scala 2574:198] - node _T_1526 = and(_T_1525, _T_1513) @[dec_tlu_ctl.scala 2574:198] - node _T_1527 = and(_T_1526, _T_1515) @[dec_tlu_ctl.scala 2574:198] - node _T_1528 = and(_T_1527, _T_1517) @[dec_tlu_ctl.scala 2574:198] - node _T_1529 = and(_T_1528, _T_1519) @[dec_tlu_ctl.scala 2574:198] - node _T_1530 = and(_T_1529, _T_1521) @[dec_tlu_ctl.scala 2574:198] - node _T_1531 = or(_T_1503, _T_1530) @[dec_tlu_ctl.scala 2658:161] - node _T_1532 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_1533 = eq(_T_1532, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1534 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:149] - node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1536 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1537 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_1539 = eq(_T_1538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1540 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_1541 = eq(_T_1540, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1542 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_1543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:106] - node _T_1544 = and(_T_1533, _T_1535) @[dec_tlu_ctl.scala 2574:198] - node _T_1545 = and(_T_1544, _T_1536) @[dec_tlu_ctl.scala 2574:198] - node _T_1546 = and(_T_1545, _T_1537) @[dec_tlu_ctl.scala 2574:198] - node _T_1547 = and(_T_1546, _T_1539) @[dec_tlu_ctl.scala 2574:198] - node _T_1548 = and(_T_1547, _T_1541) @[dec_tlu_ctl.scala 2574:198] - node _T_1549 = and(_T_1548, _T_1542) @[dec_tlu_ctl.scala 2574:198] - node _T_1550 = and(_T_1549, _T_1543) @[dec_tlu_ctl.scala 2574:198] - node _T_1551 = or(_T_1531, _T_1550) @[dec_tlu_ctl.scala 2659:97] - node _T_1552 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_1553 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:149] - node _T_1554 = eq(_T_1553, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1555 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1556 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1557 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_1558 = eq(_T_1557, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1559 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_1560 = eq(_T_1559, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1561 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2574:106] - node _T_1562 = and(_T_1552, _T_1554) @[dec_tlu_ctl.scala 2574:198] - node _T_1563 = and(_T_1562, _T_1555) @[dec_tlu_ctl.scala 2574:198] - node _T_1564 = and(_T_1563, _T_1556) @[dec_tlu_ctl.scala 2574:198] - node _T_1565 = and(_T_1564, _T_1558) @[dec_tlu_ctl.scala 2574:198] - node _T_1566 = and(_T_1565, _T_1560) @[dec_tlu_ctl.scala 2574:198] - node _T_1567 = and(_T_1566, _T_1561) @[dec_tlu_ctl.scala 2574:198] - node _T_1568 = or(_T_1551, _T_1567) @[dec_tlu_ctl.scala 2659:153] - node _T_1569 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:149] - node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1571 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:149] - node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1573 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1574 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1575 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2574:149] - node _T_1576 = eq(_T_1575, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1577 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_1578 = eq(_T_1577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1579 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:106] - node _T_1580 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:106] - node _T_1581 = and(_T_1570, _T_1572) @[dec_tlu_ctl.scala 2574:198] - node _T_1582 = and(_T_1581, _T_1573) @[dec_tlu_ctl.scala 2574:198] - node _T_1583 = and(_T_1582, _T_1574) @[dec_tlu_ctl.scala 2574:198] - node _T_1584 = and(_T_1583, _T_1576) @[dec_tlu_ctl.scala 2574:198] - node _T_1585 = and(_T_1584, _T_1578) @[dec_tlu_ctl.scala 2574:198] - node _T_1586 = and(_T_1585, _T_1579) @[dec_tlu_ctl.scala 2574:198] - node _T_1587 = and(_T_1586, _T_1580) @[dec_tlu_ctl.scala 2574:198] - node _T_1588 = or(_T_1568, _T_1587) @[dec_tlu_ctl.scala 2660:113] - node _T_1589 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2574:106] - node _T_1590 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2574:149] - node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1592 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2574:106] - node _T_1593 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2574:106] - node _T_1594 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2574:149] - node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1596 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2574:149] - node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[dec_tlu_ctl.scala 2574:129] - node _T_1598 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2574:106] - node _T_1599 = and(_T_1589, _T_1591) @[dec_tlu_ctl.scala 2574:198] - node _T_1600 = and(_T_1599, _T_1592) @[dec_tlu_ctl.scala 2574:198] - node _T_1601 = and(_T_1600, _T_1593) @[dec_tlu_ctl.scala 2574:198] - node _T_1602 = and(_T_1601, _T_1595) @[dec_tlu_ctl.scala 2574:198] - node _T_1603 = and(_T_1602, _T_1597) @[dec_tlu_ctl.scala 2574:198] - node _T_1604 = and(_T_1603, _T_1598) @[dec_tlu_ctl.scala 2574:198] - node _T_1605 = or(_T_1588, _T_1604) @[dec_tlu_ctl.scala 2660:169] - io.csr_pkt.legal <= _T_1605 @[dec_tlu_ctl.scala 2647:26] + node _T = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_1 = eq(_T, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_2 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_3 = eq(_T_2, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_4 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_5 = eq(_T_4, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_6 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_7 = eq(_T_6, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_8 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_9 = and(_T_1, _T_3) @[dec_tlu_ctl.scala 2570:198] + node _T_10 = and(_T_9, _T_5) @[dec_tlu_ctl.scala 2570:198] + node _T_11 = and(_T_10, _T_7) @[dec_tlu_ctl.scala 2570:198] + node _T_12 = and(_T_11, _T_8) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_misa <= _T_12 @[dec_tlu_ctl.scala 2572:57] + node _T_13 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_14 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_15 = eq(_T_14, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_16 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_17 = eq(_T_16, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_18 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_19 = and(_T_13, _T_15) @[dec_tlu_ctl.scala 2570:198] + node _T_20 = and(_T_19, _T_17) @[dec_tlu_ctl.scala 2570:198] + node _T_21 = and(_T_20, _T_18) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mvendorid <= _T_21 @[dec_tlu_ctl.scala 2573:57] + node _T_22 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_23 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_24 = eq(_T_23, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_25 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_26 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_27 = eq(_T_26, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_28 = and(_T_22, _T_24) @[dec_tlu_ctl.scala 2570:198] + node _T_29 = and(_T_28, _T_25) @[dec_tlu_ctl.scala 2570:198] + node _T_30 = and(_T_29, _T_27) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_marchid <= _T_30 @[dec_tlu_ctl.scala 2574:57] + node _T_31 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_32 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_33 = eq(_T_32, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_34 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_35 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_36 = and(_T_31, _T_33) @[dec_tlu_ctl.scala 2570:198] + node _T_37 = and(_T_36, _T_34) @[dec_tlu_ctl.scala 2570:198] + node _T_38 = and(_T_37, _T_35) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mimpid <= _T_38 @[dec_tlu_ctl.scala 2575:57] + node _T_39 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_40 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_41 = eq(_T_40, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_42 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_43 = and(_T_39, _T_41) @[dec_tlu_ctl.scala 2570:198] + node _T_44 = and(_T_43, _T_42) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mhartid <= _T_44 @[dec_tlu_ctl.scala 2576:57] + node _T_45 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_46 = eq(_T_45, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_47 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_48 = eq(_T_47, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_49 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_50 = eq(_T_49, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_51 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_52 = eq(_T_51, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_53 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_54 = eq(_T_53, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_55 = and(_T_46, _T_48) @[dec_tlu_ctl.scala 2570:198] + node _T_56 = and(_T_55, _T_50) @[dec_tlu_ctl.scala 2570:198] + node _T_57 = and(_T_56, _T_52) @[dec_tlu_ctl.scala 2570:198] + node _T_58 = and(_T_57, _T_54) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mstatus <= _T_58 @[dec_tlu_ctl.scala 2577:57] + node _T_59 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_60 = eq(_T_59, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_61 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_62 = eq(_T_61, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_63 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_64 = eq(_T_63, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_65 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_66 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_67 = and(_T_60, _T_62) @[dec_tlu_ctl.scala 2570:198] + node _T_68 = and(_T_67, _T_64) @[dec_tlu_ctl.scala 2570:198] + node _T_69 = and(_T_68, _T_65) @[dec_tlu_ctl.scala 2570:198] + node _T_70 = and(_T_69, _T_66) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mtvec <= _T_70 @[dec_tlu_ctl.scala 2578:57] + node _T_71 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_72 = eq(_T_71, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_73 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_74 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_75 = and(_T_72, _T_73) @[dec_tlu_ctl.scala 2570:198] + node _T_76 = and(_T_75, _T_74) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mip <= _T_76 @[dec_tlu_ctl.scala 2579:65] + node _T_77 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_78 = eq(_T_77, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_79 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_80 = eq(_T_79, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_81 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_82 = eq(_T_81, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_83 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_84 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_85 = eq(_T_84, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_86 = and(_T_78, _T_80) @[dec_tlu_ctl.scala 2570:198] + node _T_87 = and(_T_86, _T_82) @[dec_tlu_ctl.scala 2570:198] + node _T_88 = and(_T_87, _T_83) @[dec_tlu_ctl.scala 2570:198] + node _T_89 = and(_T_88, _T_85) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mie <= _T_89 @[dec_tlu_ctl.scala 2580:65] + node _T_90 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_91 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_92 = eq(_T_91, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_93 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_94 = eq(_T_93, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_95 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_96 = eq(_T_95, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_97 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_98 = eq(_T_97, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_99 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_100 = eq(_T_99, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_101 = and(_T_90, _T_92) @[dec_tlu_ctl.scala 2570:198] + node _T_102 = and(_T_101, _T_94) @[dec_tlu_ctl.scala 2570:198] + node _T_103 = and(_T_102, _T_96) @[dec_tlu_ctl.scala 2570:198] + node _T_104 = and(_T_103, _T_98) @[dec_tlu_ctl.scala 2570:198] + node _T_105 = and(_T_104, _T_100) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mcyclel <= _T_105 @[dec_tlu_ctl.scala 2581:57] + node _T_106 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_107 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_108 = eq(_T_107, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_109 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_110 = eq(_T_109, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_111 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_112 = eq(_T_111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_113 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_114 = eq(_T_113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_115 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_116 = eq(_T_115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_117 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_118 = eq(_T_117, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_119 = and(_T_106, _T_108) @[dec_tlu_ctl.scala 2570:198] + node _T_120 = and(_T_119, _T_110) @[dec_tlu_ctl.scala 2570:198] + node _T_121 = and(_T_120, _T_112) @[dec_tlu_ctl.scala 2570:198] + node _T_122 = and(_T_121, _T_114) @[dec_tlu_ctl.scala 2570:198] + node _T_123 = and(_T_122, _T_116) @[dec_tlu_ctl.scala 2570:198] + node _T_124 = and(_T_123, _T_118) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mcycleh <= _T_124 @[dec_tlu_ctl.scala 2582:57] + node _T_125 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_126 = eq(_T_125, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_127 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_128 = eq(_T_127, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_129 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_130 = eq(_T_129, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_131 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_132 = eq(_T_131, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_133 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_134 = eq(_T_133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_135 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_136 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_137 = eq(_T_136, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_138 = and(_T_126, _T_128) @[dec_tlu_ctl.scala 2570:198] + node _T_139 = and(_T_138, _T_130) @[dec_tlu_ctl.scala 2570:198] + node _T_140 = and(_T_139, _T_132) @[dec_tlu_ctl.scala 2570:198] + node _T_141 = and(_T_140, _T_134) @[dec_tlu_ctl.scala 2570:198] + node _T_142 = and(_T_141, _T_135) @[dec_tlu_ctl.scala 2570:198] + node _T_143 = and(_T_142, _T_137) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_minstretl <= _T_143 @[dec_tlu_ctl.scala 2583:57] + node _T_144 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] + node _T_145 = eq(_T_144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_146 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_147 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_148 = eq(_T_147, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_149 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_150 = eq(_T_149, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_151 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_152 = eq(_T_151, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_153 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_154 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_155 = eq(_T_154, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_156 = and(_T_145, _T_146) @[dec_tlu_ctl.scala 2570:198] + node _T_157 = and(_T_156, _T_148) @[dec_tlu_ctl.scala 2570:198] + node _T_158 = and(_T_157, _T_150) @[dec_tlu_ctl.scala 2570:198] + node _T_159 = and(_T_158, _T_152) @[dec_tlu_ctl.scala 2570:198] + node _T_160 = and(_T_159, _T_153) @[dec_tlu_ctl.scala 2570:198] + node _T_161 = and(_T_160, _T_155) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_minstreth <= _T_161 @[dec_tlu_ctl.scala 2584:57] + node _T_162 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_163 = eq(_T_162, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_164 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_165 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_166 = eq(_T_165, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_167 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_168 = eq(_T_167, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_169 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_170 = eq(_T_169, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_171 = and(_T_163, _T_164) @[dec_tlu_ctl.scala 2570:198] + node _T_172 = and(_T_171, _T_166) @[dec_tlu_ctl.scala 2570:198] + node _T_173 = and(_T_172, _T_168) @[dec_tlu_ctl.scala 2570:198] + node _T_174 = and(_T_173, _T_170) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mscratch <= _T_174 @[dec_tlu_ctl.scala 2585:57] + node _T_175 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_176 = eq(_T_175, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_177 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_178 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_179 = eq(_T_178, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_180 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_181 = and(_T_176, _T_177) @[dec_tlu_ctl.scala 2570:198] + node _T_182 = and(_T_181, _T_179) @[dec_tlu_ctl.scala 2570:198] + node _T_183 = and(_T_182, _T_180) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mepc <= _T_183 @[dec_tlu_ctl.scala 2586:57] + node _T_184 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_185 = eq(_T_184, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_186 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_187 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_188 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_189 = eq(_T_188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_190 = and(_T_185, _T_186) @[dec_tlu_ctl.scala 2570:198] + node _T_191 = and(_T_190, _T_187) @[dec_tlu_ctl.scala 2570:198] + node _T_192 = and(_T_191, _T_189) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mcause <= _T_192 @[dec_tlu_ctl.scala 2587:57] + node _T_193 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_194 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_195 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_196 = and(_T_193, _T_194) @[dec_tlu_ctl.scala 2570:198] + node _T_197 = and(_T_196, _T_195) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mscause <= _T_197 @[dec_tlu_ctl.scala 2588:57] + node _T_198 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_199 = eq(_T_198, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_200 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_201 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_202 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_203 = and(_T_199, _T_200) @[dec_tlu_ctl.scala 2570:198] + node _T_204 = and(_T_203, _T_201) @[dec_tlu_ctl.scala 2570:198] + node _T_205 = and(_T_204, _T_202) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mtval <= _T_205 @[dec_tlu_ctl.scala 2589:57] + node _T_206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_207 = eq(_T_206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_208 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_209 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_210 = eq(_T_209, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_211 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_212 = eq(_T_211, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_213 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_214 = eq(_T_213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_215 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_216 = eq(_T_215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_217 = and(_T_207, _T_208) @[dec_tlu_ctl.scala 2570:198] + node _T_218 = and(_T_217, _T_210) @[dec_tlu_ctl.scala 2570:198] + node _T_219 = and(_T_218, _T_212) @[dec_tlu_ctl.scala 2570:198] + node _T_220 = and(_T_219, _T_214) @[dec_tlu_ctl.scala 2570:198] + node _T_221 = and(_T_220, _T_216) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mrac <= _T_221 @[dec_tlu_ctl.scala 2590:57] + node _T_222 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_223 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_224 = eq(_T_223, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_225 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_226 = eq(_T_225, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_227 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_228 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_229 = eq(_T_228, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_230 = and(_T_222, _T_224) @[dec_tlu_ctl.scala 2570:198] + node _T_231 = and(_T_230, _T_226) @[dec_tlu_ctl.scala 2570:198] + node _T_232 = and(_T_231, _T_227) @[dec_tlu_ctl.scala 2570:198] + node _T_233 = and(_T_232, _T_229) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_dmst <= _T_233 @[dec_tlu_ctl.scala 2591:57] + node _T_234 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_235 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_236 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_237 = eq(_T_236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_238 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_239 = eq(_T_238, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_240 = and(_T_234, _T_235) @[dec_tlu_ctl.scala 2570:198] + node _T_241 = and(_T_240, _T_237) @[dec_tlu_ctl.scala 2570:198] + node _T_242 = and(_T_241, _T_239) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mdseac <= _T_242 @[dec_tlu_ctl.scala 2592:57] + node _T_243 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_244 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_245 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] + node _T_246 = and(_T_243, _T_244) @[dec_tlu_ctl.scala 2570:198] + node _T_247 = and(_T_246, _T_245) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_meihap <= _T_247 @[dec_tlu_ctl.scala 2593:57] + node _T_248 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_250 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_251 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] + node _T_252 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_253 = eq(_T_252, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_254 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_255 = eq(_T_254, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_256 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_258 = and(_T_249, _T_250) @[dec_tlu_ctl.scala 2570:198] + node _T_259 = and(_T_258, _T_251) @[dec_tlu_ctl.scala 2570:198] + node _T_260 = and(_T_259, _T_253) @[dec_tlu_ctl.scala 2570:198] + node _T_261 = and(_T_260, _T_255) @[dec_tlu_ctl.scala 2570:198] + node _T_262 = and(_T_261, _T_257) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_meivt <= _T_262 @[dec_tlu_ctl.scala 2594:57] + node _T_263 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_264 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_265 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_266 = eq(_T_265, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_267 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_268 = and(_T_263, _T_264) @[dec_tlu_ctl.scala 2570:198] + node _T_269 = and(_T_268, _T_266) @[dec_tlu_ctl.scala 2570:198] + node _T_270 = and(_T_269, _T_267) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_meipt <= _T_270 @[dec_tlu_ctl.scala 2595:57] + node _T_271 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_272 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_273 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_274 = and(_T_271, _T_272) @[dec_tlu_ctl.scala 2570:198] + node _T_275 = and(_T_274, _T_273) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_meicurpl <= _T_275 @[dec_tlu_ctl.scala 2596:57] + node _T_276 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_277 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_278 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_279 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_280 = and(_T_276, _T_277) @[dec_tlu_ctl.scala 2570:198] + node _T_281 = and(_T_280, _T_278) @[dec_tlu_ctl.scala 2570:198] + node _T_282 = and(_T_281, _T_279) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_meicidpl <= _T_282 @[dec_tlu_ctl.scala 2597:57] + node _T_283 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_284 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_285 = eq(_T_284, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_286 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_287 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] + node _T_288 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_289 = eq(_T_288, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_290 = and(_T_283, _T_285) @[dec_tlu_ctl.scala 2570:198] + node _T_291 = and(_T_290, _T_286) @[dec_tlu_ctl.scala 2570:198] + node _T_292 = and(_T_291, _T_287) @[dec_tlu_ctl.scala 2570:198] + node _T_293 = and(_T_292, _T_289) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_dcsr <= _T_293 @[dec_tlu_ctl.scala 2598:57] + node _T_294 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_295 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] + node _T_296 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] + node _T_297 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_298 = eq(_T_297, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_299 = and(_T_294, _T_295) @[dec_tlu_ctl.scala 2570:198] + node _T_300 = and(_T_299, _T_296) @[dec_tlu_ctl.scala 2570:198] + node _T_301 = and(_T_300, _T_298) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mcgc <= _T_301 @[dec_tlu_ctl.scala 2599:57] + node _T_302 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_303 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] + node _T_304 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] + node _T_305 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_307 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_308 = and(_T_302, _T_303) @[dec_tlu_ctl.scala 2570:198] + node _T_309 = and(_T_308, _T_304) @[dec_tlu_ctl.scala 2570:198] + node _T_310 = and(_T_309, _T_306) @[dec_tlu_ctl.scala 2570:198] + node _T_311 = and(_T_310, _T_307) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mfdc <= _T_311 @[dec_tlu_ctl.scala 2600:57] + node _T_312 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_313 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_315 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_316 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] + node _T_317 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_318 = and(_T_312, _T_314) @[dec_tlu_ctl.scala 2570:198] + node _T_319 = and(_T_318, _T_315) @[dec_tlu_ctl.scala 2570:198] + node _T_320 = and(_T_319, _T_316) @[dec_tlu_ctl.scala 2570:198] + node _T_321 = and(_T_320, _T_317) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_dpc <= _T_321 @[dec_tlu_ctl.scala 2601:65] + node _T_322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_323 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_324 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_325 = eq(_T_324, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_326 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_328 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_329 = eq(_T_328, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_330 = and(_T_322, _T_323) @[dec_tlu_ctl.scala 2570:198] + node _T_331 = and(_T_330, _T_325) @[dec_tlu_ctl.scala 2570:198] + node _T_332 = and(_T_331, _T_327) @[dec_tlu_ctl.scala 2570:198] + node _T_333 = and(_T_332, _T_329) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mtsel <= _T_333 @[dec_tlu_ctl.scala 2602:57] + node _T_334 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_335 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_336 = eq(_T_335, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_337 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_339 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_340 = and(_T_334, _T_336) @[dec_tlu_ctl.scala 2570:198] + node _T_341 = and(_T_340, _T_338) @[dec_tlu_ctl.scala 2570:198] + node _T_342 = and(_T_341, _T_339) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mtdata1 <= _T_342 @[dec_tlu_ctl.scala 2603:57] + node _T_343 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_344 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_345 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_347 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_348 = and(_T_343, _T_344) @[dec_tlu_ctl.scala 2570:198] + node _T_349 = and(_T_348, _T_346) @[dec_tlu_ctl.scala 2570:198] + node _T_350 = and(_T_349, _T_347) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mtdata2 <= _T_350 @[dec_tlu_ctl.scala 2604:57] + node _T_351 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_352 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_354 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_355 = eq(_T_354, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_356 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_358 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_359 = eq(_T_358, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_360 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_361 = and(_T_351, _T_353) @[dec_tlu_ctl.scala 2570:198] + node _T_362 = and(_T_361, _T_355) @[dec_tlu_ctl.scala 2570:198] + node _T_363 = and(_T_362, _T_357) @[dec_tlu_ctl.scala 2570:198] + node _T_364 = and(_T_363, _T_359) @[dec_tlu_ctl.scala 2570:198] + node _T_365 = and(_T_364, _T_360) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mhpmc3 <= _T_365 @[dec_tlu_ctl.scala 2605:57] + node _T_366 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_367 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_368 = eq(_T_367, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_369 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_370 = eq(_T_369, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_371 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_372 = eq(_T_371, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_373 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_374 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_375 = eq(_T_374, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_376 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_377 = eq(_T_376, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_378 = and(_T_366, _T_368) @[dec_tlu_ctl.scala 2570:198] + node _T_379 = and(_T_378, _T_370) @[dec_tlu_ctl.scala 2570:198] + node _T_380 = and(_T_379, _T_372) @[dec_tlu_ctl.scala 2570:198] + node _T_381 = and(_T_380, _T_373) @[dec_tlu_ctl.scala 2570:198] + node _T_382 = and(_T_381, _T_375) @[dec_tlu_ctl.scala 2570:198] + node _T_383 = and(_T_382, _T_377) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mhpmc4 <= _T_383 @[dec_tlu_ctl.scala 2606:57] + node _T_384 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_385 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_386 = eq(_T_385, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_387 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_388 = eq(_T_387, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_389 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_390 = eq(_T_389, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_391 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_393 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_394 = and(_T_384, _T_386) @[dec_tlu_ctl.scala 2570:198] + node _T_395 = and(_T_394, _T_388) @[dec_tlu_ctl.scala 2570:198] + node _T_396 = and(_T_395, _T_390) @[dec_tlu_ctl.scala 2570:198] + node _T_397 = and(_T_396, _T_392) @[dec_tlu_ctl.scala 2570:198] + node _T_398 = and(_T_397, _T_393) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mhpmc5 <= _T_398 @[dec_tlu_ctl.scala 2607:57] + node _T_399 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_401 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_402 = eq(_T_401, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_403 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_404 = eq(_T_403, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_405 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_406 = eq(_T_405, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_407 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_408 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_409 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_410 = eq(_T_409, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_411 = and(_T_400, _T_402) @[dec_tlu_ctl.scala 2570:198] + node _T_412 = and(_T_411, _T_404) @[dec_tlu_ctl.scala 2570:198] + node _T_413 = and(_T_412, _T_406) @[dec_tlu_ctl.scala 2570:198] + node _T_414 = and(_T_413, _T_407) @[dec_tlu_ctl.scala 2570:198] + node _T_415 = and(_T_414, _T_408) @[dec_tlu_ctl.scala 2570:198] + node _T_416 = and(_T_415, _T_410) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mhpmc6 <= _T_416 @[dec_tlu_ctl.scala 2608:57] + node _T_417 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_418 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_420 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_421 = eq(_T_420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_422 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_423 = eq(_T_422, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_424 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_425 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_426 = and(_T_417, _T_419) @[dec_tlu_ctl.scala 2570:198] + node _T_427 = and(_T_426, _T_421) @[dec_tlu_ctl.scala 2570:198] + node _T_428 = and(_T_427, _T_423) @[dec_tlu_ctl.scala 2570:198] + node _T_429 = and(_T_428, _T_424) @[dec_tlu_ctl.scala 2570:198] + node _T_430 = and(_T_429, _T_425) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mhpmc3h <= _T_430 @[dec_tlu_ctl.scala 2609:57] + node _T_431 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_432 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_433 = eq(_T_432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_434 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_436 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_437 = eq(_T_436, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_438 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_439 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_440 = eq(_T_439, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_441 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_442 = eq(_T_441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_443 = and(_T_431, _T_433) @[dec_tlu_ctl.scala 2570:198] + node _T_444 = and(_T_443, _T_435) @[dec_tlu_ctl.scala 2570:198] + node _T_445 = and(_T_444, _T_437) @[dec_tlu_ctl.scala 2570:198] + node _T_446 = and(_T_445, _T_438) @[dec_tlu_ctl.scala 2570:198] + node _T_447 = and(_T_446, _T_440) @[dec_tlu_ctl.scala 2570:198] + node _T_448 = and(_T_447, _T_442) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mhpmc4h <= _T_448 @[dec_tlu_ctl.scala 2610:57] + node _T_449 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_450 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_452 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_453 = eq(_T_452, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_454 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_455 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_456 = eq(_T_455, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_457 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_458 = and(_T_449, _T_451) @[dec_tlu_ctl.scala 2570:198] + node _T_459 = and(_T_458, _T_453) @[dec_tlu_ctl.scala 2570:198] + node _T_460 = and(_T_459, _T_454) @[dec_tlu_ctl.scala 2570:198] + node _T_461 = and(_T_460, _T_456) @[dec_tlu_ctl.scala 2570:198] + node _T_462 = and(_T_461, _T_457) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mhpmc5h <= _T_462 @[dec_tlu_ctl.scala 2611:57] + node _T_463 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_464 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_465 = eq(_T_464, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_466 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_468 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_469 = eq(_T_468, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_470 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_471 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_472 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_473 = eq(_T_472, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_474 = and(_T_463, _T_465) @[dec_tlu_ctl.scala 2570:198] + node _T_475 = and(_T_474, _T_467) @[dec_tlu_ctl.scala 2570:198] + node _T_476 = and(_T_475, _T_469) @[dec_tlu_ctl.scala 2570:198] + node _T_477 = and(_T_476, _T_470) @[dec_tlu_ctl.scala 2570:198] + node _T_478 = and(_T_477, _T_471) @[dec_tlu_ctl.scala 2570:198] + node _T_479 = and(_T_478, _T_473) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mhpmc6h <= _T_479 @[dec_tlu_ctl.scala 2612:57] + node _T_480 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_482 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_483 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_484 = eq(_T_483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_485 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_487 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_488 = eq(_T_487, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_489 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_490 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 2570:198] + node _T_491 = and(_T_490, _T_484) @[dec_tlu_ctl.scala 2570:198] + node _T_492 = and(_T_491, _T_486) @[dec_tlu_ctl.scala 2570:198] + node _T_493 = and(_T_492, _T_488) @[dec_tlu_ctl.scala 2570:198] + node _T_494 = and(_T_493, _T_489) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mhpme3 <= _T_494 @[dec_tlu_ctl.scala 2613:57] + node _T_495 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_496 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_498 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_499 = eq(_T_498, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_500 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_501 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_503 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_504 = eq(_T_503, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_505 = and(_T_495, _T_497) @[dec_tlu_ctl.scala 2570:198] + node _T_506 = and(_T_505, _T_499) @[dec_tlu_ctl.scala 2570:198] + node _T_507 = and(_T_506, _T_500) @[dec_tlu_ctl.scala 2570:198] + node _T_508 = and(_T_507, _T_502) @[dec_tlu_ctl.scala 2570:198] + node _T_509 = and(_T_508, _T_504) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mhpme4 <= _T_509 @[dec_tlu_ctl.scala 2614:57] + node _T_510 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_511 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_512 = eq(_T_511, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_513 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_514 = eq(_T_513, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_515 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_516 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_517 = eq(_T_516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_518 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_519 = and(_T_510, _T_512) @[dec_tlu_ctl.scala 2570:198] + node _T_520 = and(_T_519, _T_514) @[dec_tlu_ctl.scala 2570:198] + node _T_521 = and(_T_520, _T_515) @[dec_tlu_ctl.scala 2570:198] + node _T_522 = and(_T_521, _T_517) @[dec_tlu_ctl.scala 2570:198] + node _T_523 = and(_T_522, _T_518) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mhpme5 <= _T_523 @[dec_tlu_ctl.scala 2615:57] + node _T_524 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_525 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_526 = eq(_T_525, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_527 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_528 = eq(_T_527, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_529 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_530 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_531 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_532 = eq(_T_531, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_533 = and(_T_524, _T_526) @[dec_tlu_ctl.scala 2570:198] + node _T_534 = and(_T_533, _T_528) @[dec_tlu_ctl.scala 2570:198] + node _T_535 = and(_T_534, _T_529) @[dec_tlu_ctl.scala 2570:198] + node _T_536 = and(_T_535, _T_530) @[dec_tlu_ctl.scala 2570:198] + node _T_537 = and(_T_536, _T_532) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mhpme6 <= _T_537 @[dec_tlu_ctl.scala 2616:57] + node _T_538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_539 = eq(_T_538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_540 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_541 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_542 = eq(_T_541, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_544 = eq(_T_543, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_545 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_546 = eq(_T_545, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_547 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_548 = eq(_T_547, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_549 = and(_T_539, _T_540) @[dec_tlu_ctl.scala 2570:198] + node _T_550 = and(_T_549, _T_542) @[dec_tlu_ctl.scala 2570:198] + node _T_551 = and(_T_550, _T_544) @[dec_tlu_ctl.scala 2570:198] + node _T_552 = and(_T_551, _T_546) @[dec_tlu_ctl.scala 2570:198] + node _T_553 = and(_T_552, _T_548) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mcountinhibit <= _T_553 @[dec_tlu_ctl.scala 2617:49] + node _T_554 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_555 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_556 = eq(_T_555, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_557 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] + node _T_558 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_560 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_561 = eq(_T_560, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_562 = and(_T_554, _T_556) @[dec_tlu_ctl.scala 2570:198] + node _T_563 = and(_T_562, _T_557) @[dec_tlu_ctl.scala 2570:198] + node _T_564 = and(_T_563, _T_559) @[dec_tlu_ctl.scala 2570:198] + node _T_565 = and(_T_564, _T_561) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mitctl0 <= _T_565 @[dec_tlu_ctl.scala 2618:57] + node _T_566 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_567 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_568 = eq(_T_567, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_569 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_570 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_571 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_572 = and(_T_566, _T_568) @[dec_tlu_ctl.scala 2570:198] + node _T_573 = and(_T_572, _T_569) @[dec_tlu_ctl.scala 2570:198] + node _T_574 = and(_T_573, _T_570) @[dec_tlu_ctl.scala 2570:198] + node _T_575 = and(_T_574, _T_571) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mitctl1 <= _T_575 @[dec_tlu_ctl.scala 2619:57] + node _T_576 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_577 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_578 = eq(_T_577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_579 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] + node _T_580 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_581 = eq(_T_580, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_582 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_583 = and(_T_576, _T_578) @[dec_tlu_ctl.scala 2570:198] + node _T_584 = and(_T_583, _T_579) @[dec_tlu_ctl.scala 2570:198] + node _T_585 = and(_T_584, _T_581) @[dec_tlu_ctl.scala 2570:198] + node _T_586 = and(_T_585, _T_582) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mitb0 <= _T_586 @[dec_tlu_ctl.scala 2620:57] + node _T_587 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_588 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] + node _T_589 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_590 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_591 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_592 = eq(_T_591, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_593 = and(_T_587, _T_588) @[dec_tlu_ctl.scala 2570:198] + node _T_594 = and(_T_593, _T_589) @[dec_tlu_ctl.scala 2570:198] + node _T_595 = and(_T_594, _T_590) @[dec_tlu_ctl.scala 2570:198] + node _T_596 = and(_T_595, _T_592) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mitb1 <= _T_596 @[dec_tlu_ctl.scala 2621:57] + node _T_597 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_598 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_599 = eq(_T_598, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_600 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] + node _T_601 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_602 = eq(_T_601, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_603 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_604 = eq(_T_603, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_605 = and(_T_597, _T_599) @[dec_tlu_ctl.scala 2570:198] + node _T_606 = and(_T_605, _T_600) @[dec_tlu_ctl.scala 2570:198] + node _T_607 = and(_T_606, _T_602) @[dec_tlu_ctl.scala 2570:198] + node _T_608 = and(_T_607, _T_604) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mitcnt0 <= _T_608 @[dec_tlu_ctl.scala 2622:57] + node _T_609 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_610 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_611 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_612 = eq(_T_611, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_613 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_614 = and(_T_609, _T_610) @[dec_tlu_ctl.scala 2570:198] + node _T_615 = and(_T_614, _T_612) @[dec_tlu_ctl.scala 2570:198] + node _T_616 = and(_T_615, _T_613) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mitcnt1 <= _T_616 @[dec_tlu_ctl.scala 2623:57] + node _T_617 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_618 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_619 = eq(_T_618, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_620 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_621 = eq(_T_620, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_622 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_623 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_624 = and(_T_617, _T_619) @[dec_tlu_ctl.scala 2570:198] + node _T_625 = and(_T_624, _T_621) @[dec_tlu_ctl.scala 2570:198] + node _T_626 = and(_T_625, _T_622) @[dec_tlu_ctl.scala 2570:198] + node _T_627 = and(_T_626, _T_623) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mpmc <= _T_627 @[dec_tlu_ctl.scala 2624:57] + node _T_628 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_629 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_630 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_631 = eq(_T_630, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_632 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_634 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_635 = eq(_T_634, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_636 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_637 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 2570:198] + node _T_638 = and(_T_637, _T_631) @[dec_tlu_ctl.scala 2570:198] + node _T_639 = and(_T_638, _T_633) @[dec_tlu_ctl.scala 2570:198] + node _T_640 = and(_T_639, _T_635) @[dec_tlu_ctl.scala 2570:198] + node _T_641 = and(_T_640, _T_636) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mcpc <= _T_641 @[dec_tlu_ctl.scala 2625:57] + node _T_642 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_643 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_644 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_645 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_646 = eq(_T_645, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_647 = and(_T_642, _T_643) @[dec_tlu_ctl.scala 2570:198] + node _T_648 = and(_T_647, _T_644) @[dec_tlu_ctl.scala 2570:198] + node _T_649 = and(_T_648, _T_646) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_meicpct <= _T_649 @[dec_tlu_ctl.scala 2626:57] + node _T_650 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] + node _T_651 = eq(_T_650, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_652 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_653 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_654 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_655 = eq(_T_654, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_656 = and(_T_651, _T_652) @[dec_tlu_ctl.scala 2570:198] + node _T_657 = and(_T_656, _T_653) @[dec_tlu_ctl.scala 2570:198] + node _T_658 = and(_T_657, _T_655) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mdeau <= _T_658 @[dec_tlu_ctl.scala 2627:57] + node _T_659 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_660 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_661 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_662 = eq(_T_661, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_663 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_664 = eq(_T_663, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_665 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_666 = eq(_T_665, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_667 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 2570:198] + node _T_668 = and(_T_667, _T_662) @[dec_tlu_ctl.scala 2570:198] + node _T_669 = and(_T_668, _T_664) @[dec_tlu_ctl.scala 2570:198] + node _T_670 = and(_T_669, _T_666) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_micect <= _T_670 @[dec_tlu_ctl.scala 2628:57] + node _T_671 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_672 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_673 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_674 = eq(_T_673, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_675 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_676 = and(_T_671, _T_672) @[dec_tlu_ctl.scala 2570:198] + node _T_677 = and(_T_676, _T_674) @[dec_tlu_ctl.scala 2570:198] + node _T_678 = and(_T_677, _T_675) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_miccmect <= _T_678 @[dec_tlu_ctl.scala 2629:57] + node _T_679 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_680 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_681 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_682 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_683 = eq(_T_682, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_684 = and(_T_679, _T_680) @[dec_tlu_ctl.scala 2570:198] + node _T_685 = and(_T_684, _T_681) @[dec_tlu_ctl.scala 2570:198] + node _T_686 = and(_T_685, _T_683) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mdccmect <= _T_686 @[dec_tlu_ctl.scala 2630:57] + node _T_687 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_688 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] + node _T_689 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_690 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_691 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_692 = eq(_T_691, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_693 = and(_T_687, _T_688) @[dec_tlu_ctl.scala 2570:198] + node _T_694 = and(_T_693, _T_689) @[dec_tlu_ctl.scala 2570:198] + node _T_695 = and(_T_694, _T_690) @[dec_tlu_ctl.scala 2570:198] + node _T_696 = and(_T_695, _T_692) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mfdht <= _T_696 @[dec_tlu_ctl.scala 2631:57] + node _T_697 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_698 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_699 = eq(_T_698, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_700 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_701 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_702 = and(_T_697, _T_699) @[dec_tlu_ctl.scala 2570:198] + node _T_703 = and(_T_702, _T_700) @[dec_tlu_ctl.scala 2570:198] + node _T_704 = and(_T_703, _T_701) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_mfdhs <= _T_704 @[dec_tlu_ctl.scala 2632:57] + node _T_705 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_706 = eq(_T_705, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_707 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_708 = eq(_T_707, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_709 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] + node _T_710 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_711 = eq(_T_710, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_712 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_713 = eq(_T_712, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_714 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_715 = eq(_T_714, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_716 = and(_T_706, _T_708) @[dec_tlu_ctl.scala 2570:198] + node _T_717 = and(_T_716, _T_709) @[dec_tlu_ctl.scala 2570:198] + node _T_718 = and(_T_717, _T_711) @[dec_tlu_ctl.scala 2570:198] + node _T_719 = and(_T_718, _T_713) @[dec_tlu_ctl.scala 2570:198] + node _T_720 = and(_T_719, _T_715) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_dicawics <= _T_720 @[dec_tlu_ctl.scala 2633:57] + node _T_721 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_722 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] + node _T_723 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_724 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_725 = eq(_T_724, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_726 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 2570:198] + node _T_727 = and(_T_726, _T_723) @[dec_tlu_ctl.scala 2570:198] + node _T_728 = and(_T_727, _T_725) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_dicad0h <= _T_728 @[dec_tlu_ctl.scala 2634:57] + node _T_729 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_730 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_731 = eq(_T_730, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_732 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] + node _T_733 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_734 = eq(_T_733, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_735 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_736 = and(_T_729, _T_731) @[dec_tlu_ctl.scala 2570:198] + node _T_737 = and(_T_736, _T_732) @[dec_tlu_ctl.scala 2570:198] + node _T_738 = and(_T_737, _T_734) @[dec_tlu_ctl.scala 2570:198] + node _T_739 = and(_T_738, _T_735) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_dicad0 <= _T_739 @[dec_tlu_ctl.scala 2635:57] + node _T_740 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_741 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] + node _T_742 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_743 = eq(_T_742, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_744 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_745 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_746 = eq(_T_745, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_747 = and(_T_740, _T_741) @[dec_tlu_ctl.scala 2570:198] + node _T_748 = and(_T_747, _T_743) @[dec_tlu_ctl.scala 2570:198] + node _T_749 = and(_T_748, _T_744) @[dec_tlu_ctl.scala 2570:198] + node _T_750 = and(_T_749, _T_746) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_dicad1 <= _T_750 @[dec_tlu_ctl.scala 2636:57] + node _T_751 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_752 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] + node _T_753 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_754 = eq(_T_753, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_755 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_756 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_757 = and(_T_751, _T_752) @[dec_tlu_ctl.scala 2570:198] + node _T_758 = and(_T_757, _T_754) @[dec_tlu_ctl.scala 2570:198] + node _T_759 = and(_T_758, _T_755) @[dec_tlu_ctl.scala 2570:198] + node _T_760 = and(_T_759, _T_756) @[dec_tlu_ctl.scala 2570:198] + io.csr_pkt.csr_dicago <= _T_760 @[dec_tlu_ctl.scala 2637:57] + node _T_761 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_762 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] + node _T_763 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] + node _T_764 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_765 = eq(_T_764, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_766 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_767 = and(_T_761, _T_762) @[dec_tlu_ctl.scala 2570:198] + node _T_768 = and(_T_767, _T_763) @[dec_tlu_ctl.scala 2570:198] + node _T_769 = and(_T_768, _T_765) @[dec_tlu_ctl.scala 2570:198] + node _T_770 = and(_T_769, _T_766) @[dec_tlu_ctl.scala 2570:198] + node _T_771 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_772 = eq(_T_771, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_773 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_774 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_775 = eq(_T_774, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_776 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_778 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_779 = eq(_T_778, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_780 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_781 = eq(_T_780, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_782 = and(_T_772, _T_773) @[dec_tlu_ctl.scala 2570:198] + node _T_783 = and(_T_782, _T_775) @[dec_tlu_ctl.scala 2570:198] + node _T_784 = and(_T_783, _T_777) @[dec_tlu_ctl.scala 2570:198] + node _T_785 = and(_T_784, _T_779) @[dec_tlu_ctl.scala 2570:198] + node _T_786 = and(_T_785, _T_781) @[dec_tlu_ctl.scala 2570:198] + node _T_787 = or(_T_770, _T_786) @[dec_tlu_ctl.scala 2638:81] + node _T_788 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_789 = eq(_T_788, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_790 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_791 = eq(_T_790, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_792 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_793 = eq(_T_792, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_794 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_795 = eq(_T_794, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_796 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_797 = eq(_T_796, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_798 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_799 = and(_T_789, _T_791) @[dec_tlu_ctl.scala 2570:198] + node _T_800 = and(_T_799, _T_793) @[dec_tlu_ctl.scala 2570:198] + node _T_801 = and(_T_800, _T_795) @[dec_tlu_ctl.scala 2570:198] + node _T_802 = and(_T_801, _T_797) @[dec_tlu_ctl.scala 2570:198] + node _T_803 = and(_T_802, _T_798) @[dec_tlu_ctl.scala 2570:198] + node _T_804 = or(_T_787, _T_803) @[dec_tlu_ctl.scala 2638:121] + node _T_805 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_806 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_807 = eq(_T_806, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_808 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_809 = eq(_T_808, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_810 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_811 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_812 = eq(_T_811, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_813 = and(_T_805, _T_807) @[dec_tlu_ctl.scala 2570:198] + node _T_814 = and(_T_813, _T_809) @[dec_tlu_ctl.scala 2570:198] + node _T_815 = and(_T_814, _T_810) @[dec_tlu_ctl.scala 2570:198] + node _T_816 = and(_T_815, _T_812) @[dec_tlu_ctl.scala 2570:198] + node _T_817 = or(_T_804, _T_816) @[dec_tlu_ctl.scala 2638:155] + node _T_818 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_819 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_820 = eq(_T_819, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_821 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_822 = eq(_T_821, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_823 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_824 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_825 = eq(_T_824, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_826 = and(_T_818, _T_820) @[dec_tlu_ctl.scala 2570:198] + node _T_827 = and(_T_826, _T_822) @[dec_tlu_ctl.scala 2570:198] + node _T_828 = and(_T_827, _T_823) @[dec_tlu_ctl.scala 2570:198] + node _T_829 = and(_T_828, _T_825) @[dec_tlu_ctl.scala 2570:198] + node _T_830 = or(_T_817, _T_829) @[dec_tlu_ctl.scala 2639:97] + node _T_831 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_832 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_833 = eq(_T_832, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_834 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_835 = eq(_T_834, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_836 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_837 = eq(_T_836, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_838 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_839 = eq(_T_838, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_840 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_841 = and(_T_831, _T_833) @[dec_tlu_ctl.scala 2570:198] + node _T_842 = and(_T_841, _T_835) @[dec_tlu_ctl.scala 2570:198] + node _T_843 = and(_T_842, _T_837) @[dec_tlu_ctl.scala 2570:198] + node _T_844 = and(_T_843, _T_839) @[dec_tlu_ctl.scala 2570:198] + node _T_845 = and(_T_844, _T_840) @[dec_tlu_ctl.scala 2570:198] + node _T_846 = or(_T_830, _T_845) @[dec_tlu_ctl.scala 2639:137] + io.csr_pkt.presync <= _T_846 @[dec_tlu_ctl.scala 2638:34] + node _T_847 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_848 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] + node _T_849 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] + node _T_850 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_851 = eq(_T_850, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_852 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_853 = and(_T_847, _T_848) @[dec_tlu_ctl.scala 2570:198] + node _T_854 = and(_T_853, _T_849) @[dec_tlu_ctl.scala 2570:198] + node _T_855 = and(_T_854, _T_851) @[dec_tlu_ctl.scala 2570:198] + node _T_856 = and(_T_855, _T_852) @[dec_tlu_ctl.scala 2570:198] + node _T_857 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_858 = eq(_T_857, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_859 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_860 = eq(_T_859, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_861 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_862 = eq(_T_861, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_863 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_864 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_865 = and(_T_858, _T_860) @[dec_tlu_ctl.scala 2570:198] + node _T_866 = and(_T_865, _T_862) @[dec_tlu_ctl.scala 2570:198] + node _T_867 = and(_T_866, _T_863) @[dec_tlu_ctl.scala 2570:198] + node _T_868 = and(_T_867, _T_864) @[dec_tlu_ctl.scala 2570:198] + node _T_869 = or(_T_856, _T_868) @[dec_tlu_ctl.scala 2640:81] + node _T_870 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_871 = eq(_T_870, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_872 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_873 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_874 = eq(_T_873, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_875 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_876 = and(_T_871, _T_872) @[dec_tlu_ctl.scala 2570:198] + node _T_877 = and(_T_876, _T_874) @[dec_tlu_ctl.scala 2570:198] + node _T_878 = and(_T_877, _T_875) @[dec_tlu_ctl.scala 2570:198] + node _T_879 = or(_T_869, _T_878) @[dec_tlu_ctl.scala 2640:121] + node _T_880 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_881 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_882 = eq(_T_881, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_883 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_884 = eq(_T_883, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_885 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_886 = and(_T_880, _T_882) @[dec_tlu_ctl.scala 2570:198] + node _T_887 = and(_T_886, _T_884) @[dec_tlu_ctl.scala 2570:198] + node _T_888 = and(_T_887, _T_885) @[dec_tlu_ctl.scala 2570:198] + node _T_889 = or(_T_879, _T_888) @[dec_tlu_ctl.scala 2640:162] + node _T_890 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_891 = eq(_T_890, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_892 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_893 = eq(_T_892, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_894 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_895 = eq(_T_894, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_896 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_897 = eq(_T_896, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_898 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_899 = eq(_T_898, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_900 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_901 = eq(_T_900, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_902 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_903 = eq(_T_902, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_904 = and(_T_891, _T_893) @[dec_tlu_ctl.scala 2570:198] + node _T_905 = and(_T_904, _T_895) @[dec_tlu_ctl.scala 2570:198] + node _T_906 = and(_T_905, _T_897) @[dec_tlu_ctl.scala 2570:198] + node _T_907 = and(_T_906, _T_899) @[dec_tlu_ctl.scala 2570:198] + node _T_908 = and(_T_907, _T_901) @[dec_tlu_ctl.scala 2570:198] + node _T_909 = and(_T_908, _T_903) @[dec_tlu_ctl.scala 2570:198] + node _T_910 = or(_T_889, _T_909) @[dec_tlu_ctl.scala 2641:105] + node _T_911 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_912 = eq(_T_911, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_913 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_914 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_915 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_916 = eq(_T_915, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_917 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_918 = eq(_T_917, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_919 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_920 = eq(_T_919, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_921 = and(_T_912, _T_913) @[dec_tlu_ctl.scala 2570:198] + node _T_922 = and(_T_921, _T_914) @[dec_tlu_ctl.scala 2570:198] + node _T_923 = and(_T_922, _T_916) @[dec_tlu_ctl.scala 2570:198] + node _T_924 = and(_T_923, _T_918) @[dec_tlu_ctl.scala 2570:198] + node _T_925 = and(_T_924, _T_920) @[dec_tlu_ctl.scala 2570:198] + node _T_926 = or(_T_910, _T_925) @[dec_tlu_ctl.scala 2641:145] + node _T_927 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_928 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_929 = eq(_T_928, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_930 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_931 = eq(_T_930, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_932 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_933 = eq(_T_932, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_934 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_935 = and(_T_927, _T_929) @[dec_tlu_ctl.scala 2570:198] + node _T_936 = and(_T_935, _T_931) @[dec_tlu_ctl.scala 2570:198] + node _T_937 = and(_T_936, _T_933) @[dec_tlu_ctl.scala 2570:198] + node _T_938 = and(_T_937, _T_934) @[dec_tlu_ctl.scala 2570:198] + node _T_939 = or(_T_926, _T_938) @[dec_tlu_ctl.scala 2641:178] + io.csr_pkt.postsync <= _T_939 @[dec_tlu_ctl.scala 2640:30] + node _T_940 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_941 = eq(_T_940, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_942 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_943 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_944 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_945 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_946 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_947 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] + node _T_948 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_949 = eq(_T_948, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_950 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_951 = eq(_T_950, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_952 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_953 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_954 = eq(_T_953, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_955 = and(_T_941, _T_942) @[dec_tlu_ctl.scala 2570:198] + node _T_956 = and(_T_955, _T_943) @[dec_tlu_ctl.scala 2570:198] + node _T_957 = and(_T_956, _T_944) @[dec_tlu_ctl.scala 2570:198] + node _T_958 = and(_T_957, _T_945) @[dec_tlu_ctl.scala 2570:198] + node _T_959 = and(_T_958, _T_946) @[dec_tlu_ctl.scala 2570:198] + node _T_960 = and(_T_959, _T_947) @[dec_tlu_ctl.scala 2570:198] + node _T_961 = and(_T_960, _T_949) @[dec_tlu_ctl.scala 2570:198] + node _T_962 = and(_T_961, _T_951) @[dec_tlu_ctl.scala 2570:198] + node _T_963 = and(_T_962, _T_952) @[dec_tlu_ctl.scala 2570:198] + node _T_964 = and(_T_963, _T_954) @[dec_tlu_ctl.scala 2570:198] + node _T_965 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_966 = eq(_T_965, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_967 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] + node _T_968 = eq(_T_967, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_969 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_970 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_971 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_972 = eq(_T_971, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_973 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_974 = eq(_T_973, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_975 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_976 = eq(_T_975, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_977 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_978 = eq(_T_977, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_979 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_980 = eq(_T_979, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_981 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_982 = eq(_T_981, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_983 = and(_T_966, _T_968) @[dec_tlu_ctl.scala 2570:198] + node _T_984 = and(_T_983, _T_969) @[dec_tlu_ctl.scala 2570:198] + node _T_985 = and(_T_984, _T_970) @[dec_tlu_ctl.scala 2570:198] + node _T_986 = and(_T_985, _T_972) @[dec_tlu_ctl.scala 2570:198] + node _T_987 = and(_T_986, _T_974) @[dec_tlu_ctl.scala 2570:198] + node _T_988 = and(_T_987, _T_976) @[dec_tlu_ctl.scala 2570:198] + node _T_989 = and(_T_988, _T_978) @[dec_tlu_ctl.scala 2570:198] + node _T_990 = and(_T_989, _T_980) @[dec_tlu_ctl.scala 2570:198] + node _T_991 = and(_T_990, _T_982) @[dec_tlu_ctl.scala 2570:198] + node _T_992 = or(_T_964, _T_991) @[dec_tlu_ctl.scala 2643:81] + node _T_993 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_994 = eq(_T_993, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_995 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] + node _T_996 = eq(_T_995, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_997 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_998 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_999 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_1000 = eq(_T_999, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1001 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1003 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_1004 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_1005 = eq(_T_1004, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1006 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_1008 = and(_T_994, _T_996) @[dec_tlu_ctl.scala 2570:198] + node _T_1009 = and(_T_1008, _T_997) @[dec_tlu_ctl.scala 2570:198] + node _T_1010 = and(_T_1009, _T_998) @[dec_tlu_ctl.scala 2570:198] + node _T_1011 = and(_T_1010, _T_1000) @[dec_tlu_ctl.scala 2570:198] + node _T_1012 = and(_T_1011, _T_1002) @[dec_tlu_ctl.scala 2570:198] + node _T_1013 = and(_T_1012, _T_1003) @[dec_tlu_ctl.scala 2570:198] + node _T_1014 = and(_T_1013, _T_1005) @[dec_tlu_ctl.scala 2570:198] + node _T_1015 = and(_T_1014, _T_1007) @[dec_tlu_ctl.scala 2570:198] + node _T_1016 = or(_T_992, _T_1015) @[dec_tlu_ctl.scala 2643:129] + node _T_1017 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_1018 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1019 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1020 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_1021 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_1022 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1024 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_1025 = eq(_T_1024, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1026 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_1027 = eq(_T_1026, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1028 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1030 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_1031 = eq(_T_1030, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_1032 = and(_T_1017, _T_1018) @[dec_tlu_ctl.scala 2570:198] + node _T_1033 = and(_T_1032, _T_1019) @[dec_tlu_ctl.scala 2570:198] + node _T_1034 = and(_T_1033, _T_1020) @[dec_tlu_ctl.scala 2570:198] + node _T_1035 = and(_T_1034, _T_1021) @[dec_tlu_ctl.scala 2570:198] + node _T_1036 = and(_T_1035, _T_1023) @[dec_tlu_ctl.scala 2570:198] + node _T_1037 = and(_T_1036, _T_1025) @[dec_tlu_ctl.scala 2570:198] + node _T_1038 = and(_T_1037, _T_1027) @[dec_tlu_ctl.scala 2570:198] + node _T_1039 = and(_T_1038, _T_1029) @[dec_tlu_ctl.scala 2570:198] + node _T_1040 = and(_T_1039, _T_1031) @[dec_tlu_ctl.scala 2570:198] + node _T_1041 = or(_T_1016, _T_1040) @[dec_tlu_ctl.scala 2644:105] + node _T_1042 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_1043 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] + node _T_1044 = eq(_T_1043, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1045 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1046 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1047 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1049 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1051 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_1053 = and(_T_1042, _T_1044) @[dec_tlu_ctl.scala 2570:198] + node _T_1054 = and(_T_1053, _T_1045) @[dec_tlu_ctl.scala 2570:198] + node _T_1055 = and(_T_1054, _T_1046) @[dec_tlu_ctl.scala 2570:198] + node _T_1056 = and(_T_1055, _T_1048) @[dec_tlu_ctl.scala 2570:198] + node _T_1057 = and(_T_1056, _T_1050) @[dec_tlu_ctl.scala 2570:198] + node _T_1058 = and(_T_1057, _T_1052) @[dec_tlu_ctl.scala 2570:198] + node _T_1059 = or(_T_1041, _T_1058) @[dec_tlu_ctl.scala 2644:153] + node _T_1060 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_1061 = eq(_T_1060, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1062 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_1063 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1064 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1065 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_1066 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_1067 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_1068 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] + node _T_1069 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] + node _T_1070 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_1071 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_1072 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_1073 = and(_T_1061, _T_1062) @[dec_tlu_ctl.scala 2570:198] + node _T_1074 = and(_T_1073, _T_1063) @[dec_tlu_ctl.scala 2570:198] + node _T_1075 = and(_T_1074, _T_1064) @[dec_tlu_ctl.scala 2570:198] + node _T_1076 = and(_T_1075, _T_1065) @[dec_tlu_ctl.scala 2570:198] + node _T_1077 = and(_T_1076, _T_1066) @[dec_tlu_ctl.scala 2570:198] + node _T_1078 = and(_T_1077, _T_1067) @[dec_tlu_ctl.scala 2570:198] + node _T_1079 = and(_T_1078, _T_1068) @[dec_tlu_ctl.scala 2570:198] + node _T_1080 = and(_T_1079, _T_1069) @[dec_tlu_ctl.scala 2570:198] + node _T_1081 = and(_T_1080, _T_1070) @[dec_tlu_ctl.scala 2570:198] + node _T_1082 = and(_T_1081, _T_1071) @[dec_tlu_ctl.scala 2570:198] + node _T_1083 = and(_T_1082, _T_1072) @[dec_tlu_ctl.scala 2570:198] + node _T_1084 = or(_T_1059, _T_1083) @[dec_tlu_ctl.scala 2645:105] + node _T_1085 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_1086 = eq(_T_1085, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1087 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_1088 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1089 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1090 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_1091 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_1092 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_1093 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] + node _T_1094 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_1095 = eq(_T_1094, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1096 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_1097 = eq(_T_1096, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1098 = and(_T_1086, _T_1087) @[dec_tlu_ctl.scala 2570:198] + node _T_1099 = and(_T_1098, _T_1088) @[dec_tlu_ctl.scala 2570:198] + node _T_1100 = and(_T_1099, _T_1089) @[dec_tlu_ctl.scala 2570:198] + node _T_1101 = and(_T_1100, _T_1090) @[dec_tlu_ctl.scala 2570:198] + node _T_1102 = and(_T_1101, _T_1091) @[dec_tlu_ctl.scala 2570:198] + node _T_1103 = and(_T_1102, _T_1092) @[dec_tlu_ctl.scala 2570:198] + node _T_1104 = and(_T_1103, _T_1093) @[dec_tlu_ctl.scala 2570:198] + node _T_1105 = and(_T_1104, _T_1095) @[dec_tlu_ctl.scala 2570:198] + node _T_1106 = and(_T_1105, _T_1097) @[dec_tlu_ctl.scala 2570:198] + node _T_1107 = or(_T_1084, _T_1106) @[dec_tlu_ctl.scala 2645:153] + node _T_1108 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_1109 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1110 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1111 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_1112 = eq(_T_1111, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1113 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_1114 = eq(_T_1113, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1115 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_1116 = eq(_T_1115, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1117 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] + node _T_1118 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_1119 = eq(_T_1118, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1120 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_1121 = eq(_T_1120, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1122 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_1123 = and(_T_1108, _T_1109) @[dec_tlu_ctl.scala 2570:198] + node _T_1124 = and(_T_1123, _T_1110) @[dec_tlu_ctl.scala 2570:198] + node _T_1125 = and(_T_1124, _T_1112) @[dec_tlu_ctl.scala 2570:198] + node _T_1126 = and(_T_1125, _T_1114) @[dec_tlu_ctl.scala 2570:198] + node _T_1127 = and(_T_1126, _T_1116) @[dec_tlu_ctl.scala 2570:198] + node _T_1128 = and(_T_1127, _T_1117) @[dec_tlu_ctl.scala 2570:198] + node _T_1129 = and(_T_1128, _T_1119) @[dec_tlu_ctl.scala 2570:198] + node _T_1130 = and(_T_1129, _T_1121) @[dec_tlu_ctl.scala 2570:198] + node _T_1131 = and(_T_1130, _T_1122) @[dec_tlu_ctl.scala 2570:198] + node _T_1132 = or(_T_1107, _T_1131) @[dec_tlu_ctl.scala 2646:105] + node _T_1133 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1135 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_1136 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1137 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1138 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_1139 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_1140 = eq(_T_1139, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1141 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_1142 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_1143 = eq(_T_1142, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1144 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1146 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1148 = and(_T_1134, _T_1135) @[dec_tlu_ctl.scala 2570:198] + node _T_1149 = and(_T_1148, _T_1136) @[dec_tlu_ctl.scala 2570:198] + node _T_1150 = and(_T_1149, _T_1137) @[dec_tlu_ctl.scala 2570:198] + node _T_1151 = and(_T_1150, _T_1138) @[dec_tlu_ctl.scala 2570:198] + node _T_1152 = and(_T_1151, _T_1140) @[dec_tlu_ctl.scala 2570:198] + node _T_1153 = and(_T_1152, _T_1141) @[dec_tlu_ctl.scala 2570:198] + node _T_1154 = and(_T_1153, _T_1143) @[dec_tlu_ctl.scala 2570:198] + node _T_1155 = and(_T_1154, _T_1145) @[dec_tlu_ctl.scala 2570:198] + node _T_1156 = and(_T_1155, _T_1147) @[dec_tlu_ctl.scala 2570:198] + node _T_1157 = or(_T_1132, _T_1156) @[dec_tlu_ctl.scala 2646:161] + node _T_1158 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_1159 = eq(_T_1158, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1160 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] + node _T_1161 = eq(_T_1160, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1162 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1163 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1164 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_1165 = eq(_T_1164, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1166 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_1167 = eq(_T_1166, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1168 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_1169 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_1170 = and(_T_1159, _T_1161) @[dec_tlu_ctl.scala 2570:198] + node _T_1171 = and(_T_1170, _T_1162) @[dec_tlu_ctl.scala 2570:198] + node _T_1172 = and(_T_1171, _T_1163) @[dec_tlu_ctl.scala 2570:198] + node _T_1173 = and(_T_1172, _T_1165) @[dec_tlu_ctl.scala 2570:198] + node _T_1174 = and(_T_1173, _T_1167) @[dec_tlu_ctl.scala 2570:198] + node _T_1175 = and(_T_1174, _T_1168) @[dec_tlu_ctl.scala 2570:198] + node _T_1176 = and(_T_1175, _T_1169) @[dec_tlu_ctl.scala 2570:198] + node _T_1177 = or(_T_1157, _T_1176) @[dec_tlu_ctl.scala 2647:105] + node _T_1178 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_1179 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1180 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1181 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_1182 = eq(_T_1181, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1183 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_1184 = eq(_T_1183, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1185 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_1186 = eq(_T_1185, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1187 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] + node _T_1188 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_1189 = eq(_T_1188, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1190 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_1191 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_1192 = eq(_T_1191, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1193 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_1194 = eq(_T_1193, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_1195 = and(_T_1178, _T_1179) @[dec_tlu_ctl.scala 2570:198] + node _T_1196 = and(_T_1195, _T_1180) @[dec_tlu_ctl.scala 2570:198] + node _T_1197 = and(_T_1196, _T_1182) @[dec_tlu_ctl.scala 2570:198] + node _T_1198 = and(_T_1197, _T_1184) @[dec_tlu_ctl.scala 2570:198] + node _T_1199 = and(_T_1198, _T_1186) @[dec_tlu_ctl.scala 2570:198] + node _T_1200 = and(_T_1199, _T_1187) @[dec_tlu_ctl.scala 2570:198] + node _T_1201 = and(_T_1200, _T_1189) @[dec_tlu_ctl.scala 2570:198] + node _T_1202 = and(_T_1201, _T_1190) @[dec_tlu_ctl.scala 2570:198] + node _T_1203 = and(_T_1202, _T_1192) @[dec_tlu_ctl.scala 2570:198] + node _T_1204 = and(_T_1203, _T_1194) @[dec_tlu_ctl.scala 2570:198] + node _T_1205 = or(_T_1177, _T_1204) @[dec_tlu_ctl.scala 2647:161] + node _T_1206 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1208 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_1209 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1210 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1211 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_1212 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_1213 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_1214 = eq(_T_1213, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1215 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1217 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] + node _T_1218 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_1219 = and(_T_1207, _T_1208) @[dec_tlu_ctl.scala 2570:198] + node _T_1220 = and(_T_1219, _T_1209) @[dec_tlu_ctl.scala 2570:198] + node _T_1221 = and(_T_1220, _T_1210) @[dec_tlu_ctl.scala 2570:198] + node _T_1222 = and(_T_1221, _T_1211) @[dec_tlu_ctl.scala 2570:198] + node _T_1223 = and(_T_1222, _T_1212) @[dec_tlu_ctl.scala 2570:198] + node _T_1224 = and(_T_1223, _T_1214) @[dec_tlu_ctl.scala 2570:198] + node _T_1225 = and(_T_1224, _T_1216) @[dec_tlu_ctl.scala 2570:198] + node _T_1226 = and(_T_1225, _T_1217) @[dec_tlu_ctl.scala 2570:198] + node _T_1227 = and(_T_1226, _T_1218) @[dec_tlu_ctl.scala 2570:198] + node _T_1228 = or(_T_1205, _T_1227) @[dec_tlu_ctl.scala 2648:97] + node _T_1229 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1231 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_1232 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1233 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1234 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_1235 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_1236 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_1237 = eq(_T_1236, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1238 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] + node _T_1239 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1241 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_1242 = and(_T_1230, _T_1231) @[dec_tlu_ctl.scala 2570:198] + node _T_1243 = and(_T_1242, _T_1232) @[dec_tlu_ctl.scala 2570:198] + node _T_1244 = and(_T_1243, _T_1233) @[dec_tlu_ctl.scala 2570:198] + node _T_1245 = and(_T_1244, _T_1234) @[dec_tlu_ctl.scala 2570:198] + node _T_1246 = and(_T_1245, _T_1235) @[dec_tlu_ctl.scala 2570:198] + node _T_1247 = and(_T_1246, _T_1237) @[dec_tlu_ctl.scala 2570:198] + node _T_1248 = and(_T_1247, _T_1238) @[dec_tlu_ctl.scala 2570:198] + node _T_1249 = and(_T_1248, _T_1240) @[dec_tlu_ctl.scala 2570:198] + node _T_1250 = and(_T_1249, _T_1241) @[dec_tlu_ctl.scala 2570:198] + node _T_1251 = or(_T_1228, _T_1250) @[dec_tlu_ctl.scala 2648:153] + node _T_1252 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_1253 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1254 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1255 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_1256 = eq(_T_1255, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1257 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_1258 = eq(_T_1257, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1259 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_1260 = eq(_T_1259, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1261 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] + node _T_1262 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1264 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1266 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_1267 = and(_T_1252, _T_1253) @[dec_tlu_ctl.scala 2570:198] + node _T_1268 = and(_T_1267, _T_1254) @[dec_tlu_ctl.scala 2570:198] + node _T_1269 = and(_T_1268, _T_1256) @[dec_tlu_ctl.scala 2570:198] + node _T_1270 = and(_T_1269, _T_1258) @[dec_tlu_ctl.scala 2570:198] + node _T_1271 = and(_T_1270, _T_1260) @[dec_tlu_ctl.scala 2570:198] + node _T_1272 = and(_T_1271, _T_1261) @[dec_tlu_ctl.scala 2570:198] + node _T_1273 = and(_T_1272, _T_1263) @[dec_tlu_ctl.scala 2570:198] + node _T_1274 = and(_T_1273, _T_1265) @[dec_tlu_ctl.scala 2570:198] + node _T_1275 = and(_T_1274, _T_1266) @[dec_tlu_ctl.scala 2570:198] + node _T_1276 = or(_T_1251, _T_1275) @[dec_tlu_ctl.scala 2649:105] + node _T_1277 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1279 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] + node _T_1280 = eq(_T_1279, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1281 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1282 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1283 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_1284 = eq(_T_1283, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1285 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_1286 = eq(_T_1285, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1287 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_1288 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_1289 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:106] + node _T_1290 = and(_T_1278, _T_1280) @[dec_tlu_ctl.scala 2570:198] + node _T_1291 = and(_T_1290, _T_1281) @[dec_tlu_ctl.scala 2570:198] + node _T_1292 = and(_T_1291, _T_1282) @[dec_tlu_ctl.scala 2570:198] + node _T_1293 = and(_T_1292, _T_1284) @[dec_tlu_ctl.scala 2570:198] + node _T_1294 = and(_T_1293, _T_1286) @[dec_tlu_ctl.scala 2570:198] + node _T_1295 = and(_T_1294, _T_1287) @[dec_tlu_ctl.scala 2570:198] + node _T_1296 = and(_T_1295, _T_1288) @[dec_tlu_ctl.scala 2570:198] + node _T_1297 = and(_T_1296, _T_1289) @[dec_tlu_ctl.scala 2570:198] + node _T_1298 = or(_T_1276, _T_1297) @[dec_tlu_ctl.scala 2649:161] + node _T_1299 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_1300 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] + node _T_1301 = eq(_T_1300, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1302 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1303 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1304 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_1305 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_1306 = eq(_T_1305, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1307 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1309 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] + node _T_1310 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1312 = and(_T_1299, _T_1301) @[dec_tlu_ctl.scala 2570:198] + node _T_1313 = and(_T_1312, _T_1302) @[dec_tlu_ctl.scala 2570:198] + node _T_1314 = and(_T_1313, _T_1303) @[dec_tlu_ctl.scala 2570:198] + node _T_1315 = and(_T_1314, _T_1304) @[dec_tlu_ctl.scala 2570:198] + node _T_1316 = and(_T_1315, _T_1306) @[dec_tlu_ctl.scala 2570:198] + node _T_1317 = and(_T_1316, _T_1308) @[dec_tlu_ctl.scala 2570:198] + node _T_1318 = and(_T_1317, _T_1309) @[dec_tlu_ctl.scala 2570:198] + node _T_1319 = and(_T_1318, _T_1311) @[dec_tlu_ctl.scala 2570:198] + node _T_1320 = or(_T_1298, _T_1319) @[dec_tlu_ctl.scala 2650:105] + node _T_1321 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_1322 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] + node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1324 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1325 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1326 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_1327 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_1328 = eq(_T_1327, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1329 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1331 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] + node _T_1332 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1334 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_1336 = and(_T_1321, _T_1323) @[dec_tlu_ctl.scala 2570:198] + node _T_1337 = and(_T_1336, _T_1324) @[dec_tlu_ctl.scala 2570:198] + node _T_1338 = and(_T_1337, _T_1325) @[dec_tlu_ctl.scala 2570:198] + node _T_1339 = and(_T_1338, _T_1326) @[dec_tlu_ctl.scala 2570:198] + node _T_1340 = and(_T_1339, _T_1328) @[dec_tlu_ctl.scala 2570:198] + node _T_1341 = and(_T_1340, _T_1330) @[dec_tlu_ctl.scala 2570:198] + node _T_1342 = and(_T_1341, _T_1331) @[dec_tlu_ctl.scala 2570:198] + node _T_1343 = and(_T_1342, _T_1333) @[dec_tlu_ctl.scala 2570:198] + node _T_1344 = and(_T_1343, _T_1335) @[dec_tlu_ctl.scala 2570:198] + node _T_1345 = or(_T_1320, _T_1344) @[dec_tlu_ctl.scala 2650:161] + node _T_1346 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_1347 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] + node _T_1348 = eq(_T_1347, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1349 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1350 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1351 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_1352 = eq(_T_1351, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1353 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_1354 = eq(_T_1353, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1355 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:106] + node _T_1356 = and(_T_1346, _T_1348) @[dec_tlu_ctl.scala 2570:198] + node _T_1357 = and(_T_1356, _T_1349) @[dec_tlu_ctl.scala 2570:198] + node _T_1358 = and(_T_1357, _T_1350) @[dec_tlu_ctl.scala 2570:198] + node _T_1359 = and(_T_1358, _T_1352) @[dec_tlu_ctl.scala 2570:198] + node _T_1360 = and(_T_1359, _T_1354) @[dec_tlu_ctl.scala 2570:198] + node _T_1361 = and(_T_1360, _T_1355) @[dec_tlu_ctl.scala 2570:198] + node _T_1362 = or(_T_1345, _T_1361) @[dec_tlu_ctl.scala 2651:105] + node _T_1363 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_1364 = eq(_T_1363, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1365 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_1366 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1367 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1368 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_1369 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_1370 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_1371 = eq(_T_1370, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1372 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] + node _T_1373 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_1374 = eq(_T_1373, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1375 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_1376 = and(_T_1364, _T_1365) @[dec_tlu_ctl.scala 2570:198] + node _T_1377 = and(_T_1376, _T_1366) @[dec_tlu_ctl.scala 2570:198] + node _T_1378 = and(_T_1377, _T_1367) @[dec_tlu_ctl.scala 2570:198] + node _T_1379 = and(_T_1378, _T_1368) @[dec_tlu_ctl.scala 2570:198] + node _T_1380 = and(_T_1379, _T_1369) @[dec_tlu_ctl.scala 2570:198] + node _T_1381 = and(_T_1380, _T_1371) @[dec_tlu_ctl.scala 2570:198] + node _T_1382 = and(_T_1381, _T_1372) @[dec_tlu_ctl.scala 2570:198] + node _T_1383 = and(_T_1382, _T_1374) @[dec_tlu_ctl.scala 2570:198] + node _T_1384 = and(_T_1383, _T_1375) @[dec_tlu_ctl.scala 2570:198] + node _T_1385 = or(_T_1362, _T_1384) @[dec_tlu_ctl.scala 2651:161] + node _T_1386 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_1387 = eq(_T_1386, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1388 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_1389 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1390 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1391 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_1392 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_1393 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_1394 = eq(_T_1393, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1395 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_1396 = eq(_T_1395, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1397 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_1398 = eq(_T_1397, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_1399 = and(_T_1387, _T_1388) @[dec_tlu_ctl.scala 2570:198] + node _T_1400 = and(_T_1399, _T_1389) @[dec_tlu_ctl.scala 2570:198] + node _T_1401 = and(_T_1400, _T_1390) @[dec_tlu_ctl.scala 2570:198] + node _T_1402 = and(_T_1401, _T_1391) @[dec_tlu_ctl.scala 2570:198] + node _T_1403 = and(_T_1402, _T_1392) @[dec_tlu_ctl.scala 2570:198] + node _T_1404 = and(_T_1403, _T_1394) @[dec_tlu_ctl.scala 2570:198] + node _T_1405 = and(_T_1404, _T_1396) @[dec_tlu_ctl.scala 2570:198] + node _T_1406 = and(_T_1405, _T_1398) @[dec_tlu_ctl.scala 2570:198] + node _T_1407 = or(_T_1385, _T_1406) @[dec_tlu_ctl.scala 2652:105] + node _T_1408 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1410 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_1411 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1412 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1413 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_1414 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_1415 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_1416 = eq(_T_1415, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1417 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_1418 = eq(_T_1417, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1419 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] + node _T_1420 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1422 = and(_T_1409, _T_1410) @[dec_tlu_ctl.scala 2570:198] + node _T_1423 = and(_T_1422, _T_1411) @[dec_tlu_ctl.scala 2570:198] + node _T_1424 = and(_T_1423, _T_1412) @[dec_tlu_ctl.scala 2570:198] + node _T_1425 = and(_T_1424, _T_1413) @[dec_tlu_ctl.scala 2570:198] + node _T_1426 = and(_T_1425, _T_1414) @[dec_tlu_ctl.scala 2570:198] + node _T_1427 = and(_T_1426, _T_1416) @[dec_tlu_ctl.scala 2570:198] + node _T_1428 = and(_T_1427, _T_1418) @[dec_tlu_ctl.scala 2570:198] + node _T_1429 = and(_T_1428, _T_1419) @[dec_tlu_ctl.scala 2570:198] + node _T_1430 = and(_T_1429, _T_1421) @[dec_tlu_ctl.scala 2570:198] + node _T_1431 = or(_T_1407, _T_1430) @[dec_tlu_ctl.scala 2652:161] + node _T_1432 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1434 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:106] + node _T_1435 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1436 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1437 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:106] + node _T_1438 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1440 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_1441 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_1442 = eq(_T_1441, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1443 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1445 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1447 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_1448 = eq(_T_1447, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_1449 = and(_T_1433, _T_1434) @[dec_tlu_ctl.scala 2570:198] + node _T_1450 = and(_T_1449, _T_1435) @[dec_tlu_ctl.scala 2570:198] + node _T_1451 = and(_T_1450, _T_1436) @[dec_tlu_ctl.scala 2570:198] + node _T_1452 = and(_T_1451, _T_1437) @[dec_tlu_ctl.scala 2570:198] + node _T_1453 = and(_T_1452, _T_1439) @[dec_tlu_ctl.scala 2570:198] + node _T_1454 = and(_T_1453, _T_1440) @[dec_tlu_ctl.scala 2570:198] + node _T_1455 = and(_T_1454, _T_1442) @[dec_tlu_ctl.scala 2570:198] + node _T_1456 = and(_T_1455, _T_1444) @[dec_tlu_ctl.scala 2570:198] + node _T_1457 = and(_T_1456, _T_1446) @[dec_tlu_ctl.scala 2570:198] + node _T_1458 = and(_T_1457, _T_1448) @[dec_tlu_ctl.scala 2570:198] + node _T_1459 = or(_T_1431, _T_1458) @[dec_tlu_ctl.scala 2653:105] + node _T_1460 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_1461 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] + node _T_1462 = eq(_T_1461, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1463 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1464 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1465 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_1466 = eq(_T_1465, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1467 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1469 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:106] + node _T_1470 = and(_T_1460, _T_1462) @[dec_tlu_ctl.scala 2570:198] + node _T_1471 = and(_T_1470, _T_1463) @[dec_tlu_ctl.scala 2570:198] + node _T_1472 = and(_T_1471, _T_1464) @[dec_tlu_ctl.scala 2570:198] + node _T_1473 = and(_T_1472, _T_1466) @[dec_tlu_ctl.scala 2570:198] + node _T_1474 = and(_T_1473, _T_1468) @[dec_tlu_ctl.scala 2570:198] + node _T_1475 = and(_T_1474, _T_1469) @[dec_tlu_ctl.scala 2570:198] + node _T_1476 = or(_T_1459, _T_1475) @[dec_tlu_ctl.scala 2653:153] + node _T_1477 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1479 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] + node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1481 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1482 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1483 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1485 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:106] + node _T_1486 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_1487 = eq(_T_1486, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1488 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_1489 = eq(_T_1488, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1490 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_1491 = eq(_T_1490, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1492 = bits(io.dec_csr_rdaddr_d, 2, 2) @[dec_tlu_ctl.scala 2570:149] + node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1494 = and(_T_1478, _T_1480) @[dec_tlu_ctl.scala 2570:198] + node _T_1495 = and(_T_1494, _T_1481) @[dec_tlu_ctl.scala 2570:198] + node _T_1496 = and(_T_1495, _T_1482) @[dec_tlu_ctl.scala 2570:198] + node _T_1497 = and(_T_1496, _T_1484) @[dec_tlu_ctl.scala 2570:198] + node _T_1498 = and(_T_1497, _T_1485) @[dec_tlu_ctl.scala 2570:198] + node _T_1499 = and(_T_1498, _T_1487) @[dec_tlu_ctl.scala 2570:198] + node _T_1500 = and(_T_1499, _T_1489) @[dec_tlu_ctl.scala 2570:198] + node _T_1501 = and(_T_1500, _T_1491) @[dec_tlu_ctl.scala 2570:198] + node _T_1502 = and(_T_1501, _T_1493) @[dec_tlu_ctl.scala 2570:198] + node _T_1503 = or(_T_1476, _T_1502) @[dec_tlu_ctl.scala 2654:113] + node _T_1504 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_1505 = eq(_T_1504, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1506 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] + node _T_1507 = eq(_T_1506, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1508 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1509 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1510 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_1511 = eq(_T_1510, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1512 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_1513 = eq(_T_1512, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1514 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:149] + node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1516 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:149] + node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1518 = bits(io.dec_csr_rdaddr_d, 1, 1) @[dec_tlu_ctl.scala 2570:149] + node _T_1519 = eq(_T_1518, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1520 = bits(io.dec_csr_rdaddr_d, 0, 0) @[dec_tlu_ctl.scala 2570:185] + node _T_1521 = eq(_T_1520, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:165] + node _T_1522 = and(_T_1505, _T_1507) @[dec_tlu_ctl.scala 2570:198] + node _T_1523 = and(_T_1522, _T_1508) @[dec_tlu_ctl.scala 2570:198] + node _T_1524 = and(_T_1523, _T_1509) @[dec_tlu_ctl.scala 2570:198] + node _T_1525 = and(_T_1524, _T_1511) @[dec_tlu_ctl.scala 2570:198] + node _T_1526 = and(_T_1525, _T_1513) @[dec_tlu_ctl.scala 2570:198] + node _T_1527 = and(_T_1526, _T_1515) @[dec_tlu_ctl.scala 2570:198] + node _T_1528 = and(_T_1527, _T_1517) @[dec_tlu_ctl.scala 2570:198] + node _T_1529 = and(_T_1528, _T_1519) @[dec_tlu_ctl.scala 2570:198] + node _T_1530 = and(_T_1529, _T_1521) @[dec_tlu_ctl.scala 2570:198] + node _T_1531 = or(_T_1503, _T_1530) @[dec_tlu_ctl.scala 2654:161] + node _T_1532 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_1533 = eq(_T_1532, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1534 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] + node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1536 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1537 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1538 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_1539 = eq(_T_1538, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1540 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_1541 = eq(_T_1540, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1542 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_1543 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] + node _T_1544 = and(_T_1533, _T_1535) @[dec_tlu_ctl.scala 2570:198] + node _T_1545 = and(_T_1544, _T_1536) @[dec_tlu_ctl.scala 2570:198] + node _T_1546 = and(_T_1545, _T_1537) @[dec_tlu_ctl.scala 2570:198] + node _T_1547 = and(_T_1546, _T_1539) @[dec_tlu_ctl.scala 2570:198] + node _T_1548 = and(_T_1547, _T_1541) @[dec_tlu_ctl.scala 2570:198] + node _T_1549 = and(_T_1548, _T_1542) @[dec_tlu_ctl.scala 2570:198] + node _T_1550 = and(_T_1549, _T_1543) @[dec_tlu_ctl.scala 2570:198] + node _T_1551 = or(_T_1531, _T_1550) @[dec_tlu_ctl.scala 2655:97] + node _T_1552 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_1553 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] + node _T_1554 = eq(_T_1553, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1555 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1556 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1557 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_1558 = eq(_T_1557, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1559 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_1560 = eq(_T_1559, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1561 = bits(io.dec_csr_rdaddr_d, 3, 3) @[dec_tlu_ctl.scala 2570:106] + node _T_1562 = and(_T_1552, _T_1554) @[dec_tlu_ctl.scala 2570:198] + node _T_1563 = and(_T_1562, _T_1555) @[dec_tlu_ctl.scala 2570:198] + node _T_1564 = and(_T_1563, _T_1556) @[dec_tlu_ctl.scala 2570:198] + node _T_1565 = and(_T_1564, _T_1558) @[dec_tlu_ctl.scala 2570:198] + node _T_1566 = and(_T_1565, _T_1560) @[dec_tlu_ctl.scala 2570:198] + node _T_1567 = and(_T_1566, _T_1561) @[dec_tlu_ctl.scala 2570:198] + node _T_1568 = or(_T_1551, _T_1567) @[dec_tlu_ctl.scala 2655:153] + node _T_1569 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:149] + node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1571 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] + node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1573 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1574 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1575 = bits(io.dec_csr_rdaddr_d, 7, 7) @[dec_tlu_ctl.scala 2570:149] + node _T_1576 = eq(_T_1575, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1577 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_1578 = eq(_T_1577, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1579 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:106] + node _T_1580 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] + node _T_1581 = and(_T_1570, _T_1572) @[dec_tlu_ctl.scala 2570:198] + node _T_1582 = and(_T_1581, _T_1573) @[dec_tlu_ctl.scala 2570:198] + node _T_1583 = and(_T_1582, _T_1574) @[dec_tlu_ctl.scala 2570:198] + node _T_1584 = and(_T_1583, _T_1576) @[dec_tlu_ctl.scala 2570:198] + node _T_1585 = and(_T_1584, _T_1578) @[dec_tlu_ctl.scala 2570:198] + node _T_1586 = and(_T_1585, _T_1579) @[dec_tlu_ctl.scala 2570:198] + node _T_1587 = and(_T_1586, _T_1580) @[dec_tlu_ctl.scala 2570:198] + node _T_1588 = or(_T_1568, _T_1587) @[dec_tlu_ctl.scala 2656:113] + node _T_1589 = bits(io.dec_csr_rdaddr_d, 11, 11) @[dec_tlu_ctl.scala 2570:106] + node _T_1590 = bits(io.dec_csr_rdaddr_d, 10, 10) @[dec_tlu_ctl.scala 2570:149] + node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1592 = bits(io.dec_csr_rdaddr_d, 9, 9) @[dec_tlu_ctl.scala 2570:106] + node _T_1593 = bits(io.dec_csr_rdaddr_d, 8, 8) @[dec_tlu_ctl.scala 2570:106] + node _T_1594 = bits(io.dec_csr_rdaddr_d, 6, 6) @[dec_tlu_ctl.scala 2570:149] + node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1596 = bits(io.dec_csr_rdaddr_d, 5, 5) @[dec_tlu_ctl.scala 2570:149] + node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[dec_tlu_ctl.scala 2570:129] + node _T_1598 = bits(io.dec_csr_rdaddr_d, 4, 4) @[dec_tlu_ctl.scala 2570:106] + node _T_1599 = and(_T_1589, _T_1591) @[dec_tlu_ctl.scala 2570:198] + node _T_1600 = and(_T_1599, _T_1592) @[dec_tlu_ctl.scala 2570:198] + node _T_1601 = and(_T_1600, _T_1593) @[dec_tlu_ctl.scala 2570:198] + node _T_1602 = and(_T_1601, _T_1595) @[dec_tlu_ctl.scala 2570:198] + node _T_1603 = and(_T_1602, _T_1597) @[dec_tlu_ctl.scala 2570:198] + node _T_1604 = and(_T_1603, _T_1598) @[dec_tlu_ctl.scala 2570:198] + node _T_1605 = or(_T_1588, _T_1604) @[dec_tlu_ctl.scala 2656:169] + io.csr_pkt.legal <= _T_1605 @[dec_tlu_ctl.scala 2643:26] module dec_tlu_ctl : input clock : Clock input reset : AsyncReset - output io : {flip tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_extint : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip tlu_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}, flip tlu_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, flip tlu_mem : {flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, flip tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, flip lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}} + output io : {flip tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}, flip active_clk : Clock, flip free_clk : Clock, flip scan_mode : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, flip lsu_fastint_stall_any : UInt<1>, flip lsu_idle_any : UInt<1>, flip dec_pmu_instr_decoded : UInt<1>, flip dec_pmu_decode_stall : UInt<1>, flip dec_pmu_presync_stall : UInt<1>, flip dec_pmu_postsync_stall : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip iccm_dma_sb_error : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip dec_pause_state : UInt<1>, flip dec_csr_wen_unq_d : UInt<1>, flip dec_csr_any_unq_d : UInt<1>, flip dec_csr_rdaddr_d : UInt<12>, flip dec_csr_wen_r : UInt<1>, flip dec_csr_wraddr_r : UInt<12>, flip dec_csr_wrdata_r : UInt<32>, flip dec_csr_stall_int_ff : UInt<1>, flip dec_tlu_i0_valid_r : UInt<1>, flip dec_tlu_i0_pc_r : UInt<31>, flip dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, flip dec_illegal_inst : UInt<32>, flip dec_i0_decode_d : UInt<1>, flip exu_i0_br_way_r : UInt<1>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_debug_stall : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_tlu_flush_extint : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, flip dec_div_active : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip timer_int : UInt<1>, flip soft_int : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_csr_rddata_d : UInt<32>, dec_csr_legal_d : UInt<1>, dec_tlu_i0_kill_writeb_wb : UInt<1>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_wr_pause_r : UInt<1>, dec_tlu_flush_pause_r : UInt<1>, dec_tlu_presync_d : UInt<1>, dec_tlu_postsync_d : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_tlu_i0_exc_valid_wb1 : UInt<1>, dec_tlu_i0_valid_wb1 : UInt<1>, dec_tlu_int_valid_wb1 : UInt<1>, dec_tlu_exc_cause_wb1 : UInt<5>, dec_tlu_mtval_wb1 : UInt<32>, dec_tlu_pipelining_disable : UInt<1>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_dec_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, dec_tlu_flush_lower_wb : UInt<1>, flip ifu_pmu_instr_aligned : UInt<1>, flip tlu_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}, flip tlu_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, flip tlu_mem : {flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, flip tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, flip lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, dec_pic : {flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip mexintpend : UInt<1>}} - wire mtdata1_t : UInt<10>[4] @[dec_tlu_ctl.scala 160:67] + wire mtdata1_t : UInt<10>[4] @[dec_tlu_ctl.scala 156:67] wire pause_expired_wb : UInt<1> pause_expired_wb <= UInt<1>("h00") wire take_nmi_r_d1 : UInt<1> @@ -78077,30 +78077,30 @@ circuit quasar_wrapper : mtvec <= UInt<1>("h00") wire mip : UInt<6> mip <= UInt<1>("h00") - wire csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>} @[dec_tlu_ctl.scala 275:41] + wire csr_pkt : {csr_misa : UInt<1>, csr_mvendorid : UInt<1>, csr_marchid : UInt<1>, csr_mimpid : UInt<1>, csr_mhartid : UInt<1>, csr_mstatus : UInt<1>, csr_mtvec : UInt<1>, csr_mip : UInt<1>, csr_mie : UInt<1>, csr_mcyclel : UInt<1>, csr_mcycleh : UInt<1>, csr_minstretl : UInt<1>, csr_minstreth : UInt<1>, csr_mscratch : UInt<1>, csr_mepc : UInt<1>, csr_mcause : UInt<1>, csr_mscause : UInt<1>, csr_mtval : UInt<1>, csr_mrac : UInt<1>, csr_dmst : UInt<1>, csr_mdseac : UInt<1>, csr_meihap : UInt<1>, csr_meivt : UInt<1>, csr_meipt : UInt<1>, csr_meicurpl : UInt<1>, csr_meicidpl : UInt<1>, csr_dcsr : UInt<1>, csr_mcgc : UInt<1>, csr_mfdc : UInt<1>, csr_dpc : UInt<1>, csr_mtsel : UInt<1>, csr_mtdata1 : UInt<1>, csr_mtdata2 : UInt<1>, csr_mhpmc3 : UInt<1>, csr_mhpmc4 : UInt<1>, csr_mhpmc5 : UInt<1>, csr_mhpmc6 : UInt<1>, csr_mhpmc3h : UInt<1>, csr_mhpmc4h : UInt<1>, csr_mhpmc5h : UInt<1>, csr_mhpmc6h : UInt<1>, csr_mhpme3 : UInt<1>, csr_mhpme4 : UInt<1>, csr_mhpme5 : UInt<1>, csr_mhpme6 : UInt<1>, csr_mcountinhibit : UInt<1>, csr_mitctl0 : UInt<1>, csr_mitctl1 : UInt<1>, csr_mitb0 : UInt<1>, csr_mitb1 : UInt<1>, csr_mitcnt0 : UInt<1>, csr_mitcnt1 : UInt<1>, csr_mpmc : UInt<1>, csr_mcpc : UInt<1>, csr_meicpct : UInt<1>, csr_mdeau : UInt<1>, csr_micect : UInt<1>, csr_miccmect : UInt<1>, csr_mdccmect : UInt<1>, csr_mfdht : UInt<1>, csr_mfdhs : UInt<1>, csr_dicawics : UInt<1>, csr_dicad0h : UInt<1>, csr_dicad0 : UInt<1>, csr_dicad1 : UInt<1>, csr_dicago : UInt<1>, presync : UInt<1>, postsync : UInt<1>, legal : UInt<1>} @[dec_tlu_ctl.scala 271:41] wire dec_tlu_mpc_halted_only_ns : UInt<1> dec_tlu_mpc_halted_only_ns <= UInt<1>("h00") - node _T = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 278:39] - node _T_1 = and(_T, mpc_halt_state_f) @[dec_tlu_ctl.scala 278:57] - dec_tlu_mpc_halted_only_ns <= _T_1 @[dec_tlu_ctl.scala 278:36] - inst int_timers of dec_timer_ctl @[dec_tlu_ctl.scala 279:30] + node _T = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 274:39] + node _T_1 = and(_T, mpc_halt_state_f) @[dec_tlu_ctl.scala 274:57] + dec_tlu_mpc_halted_only_ns <= _T_1 @[dec_tlu_ctl.scala 274:36] + inst int_timers of dec_timer_ctl @[dec_tlu_ctl.scala 275:30] int_timers.clock <= clock int_timers.reset <= reset - int_timers.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 280:57] - int_timers.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 281:57] - int_timers.io.dec_csr_wen_r_mod <= dec_csr_wen_r_mod @[dec_tlu_ctl.scala 282:49] - int_timers.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 283:49] - int_timers.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 284:49] - int_timers.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 285:49] - int_timers.io.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 286:57] - int_timers.io.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 287:57] - int_timers.io.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 288:57] - int_timers.io.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 289:57] - int_timers.io.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 290:57] - int_timers.io.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 291:57] - int_timers.io.dec_pause_state <= io.dec_pause_state @[dec_tlu_ctl.scala 292:49] - int_timers.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 293:49] - int_timers.io.internal_dbg_halt_timers <= internal_dbg_halt_timers @[dec_tlu_ctl.scala 294:47] + int_timers.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 276:57] + int_timers.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 277:57] + int_timers.io.dec_csr_wen_r_mod <= dec_csr_wen_r_mod @[dec_tlu_ctl.scala 278:49] + int_timers.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 279:49] + int_timers.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 280:49] + int_timers.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 281:49] + int_timers.io.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 282:57] + int_timers.io.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 283:57] + int_timers.io.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 284:57] + int_timers.io.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 285:57] + int_timers.io.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 286:57] + int_timers.io.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 287:57] + int_timers.io.dec_pause_state <= io.dec_pause_state @[dec_tlu_ctl.scala 288:49] + int_timers.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 289:49] + int_timers.io.internal_dbg_halt_timers <= internal_dbg_halt_timers @[dec_tlu_ctl.scala 290:47] node _T_2 = cat(io.i_cpu_run_req, io.mpc_debug_halt_req) @[Cat.scala 29:58] node _T_3 = cat(_T_2, io.mpc_debug_run_req) @[Cat.scala 29:58] node _T_4 = cat(io.soft_int, io.i_cpu_halt_req) @[Cat.scala 29:58] @@ -78111,841 +78111,841 @@ circuit quasar_wrapper : _T_8 <= _T_7 @[lib.scala 21:81] reg syncro_ff : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 21:58] syncro_ff <= _T_8 @[lib.scala 21:58] - node nmi_int_sync = bits(syncro_ff, 6, 6) @[dec_tlu_ctl.scala 306:67] - node timer_int_sync = bits(syncro_ff, 5, 5) @[dec_tlu_ctl.scala 307:59] - node soft_int_sync = bits(syncro_ff, 4, 4) @[dec_tlu_ctl.scala 308:59] - node i_cpu_halt_req_sync = bits(syncro_ff, 3, 3) @[dec_tlu_ctl.scala 309:59] - node i_cpu_run_req_sync = bits(syncro_ff, 2, 2) @[dec_tlu_ctl.scala 310:59] - node mpc_debug_halt_req_sync_raw = bits(syncro_ff, 1, 1) @[dec_tlu_ctl.scala 311:51] - node mpc_debug_run_req_sync = bits(syncro_ff, 0, 0) @[dec_tlu_ctl.scala 312:51] - node _T_9 = or(dec_csr_wen_r_mod, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 315:58] - node _T_10 = bits(_T_9, 0, 0) @[dec_tlu_ctl.scala 315:74] + node nmi_int_sync = bits(syncro_ff, 6, 6) @[dec_tlu_ctl.scala 302:67] + node timer_int_sync = bits(syncro_ff, 5, 5) @[dec_tlu_ctl.scala 303:59] + node soft_int_sync = bits(syncro_ff, 4, 4) @[dec_tlu_ctl.scala 304:59] + node i_cpu_halt_req_sync = bits(syncro_ff, 3, 3) @[dec_tlu_ctl.scala 305:59] + node i_cpu_run_req_sync = bits(syncro_ff, 2, 2) @[dec_tlu_ctl.scala 306:59] + node mpc_debug_halt_req_sync_raw = bits(syncro_ff, 1, 1) @[dec_tlu_ctl.scala 307:51] + node mpc_debug_run_req_sync = bits(syncro_ff, 0, 0) @[dec_tlu_ctl.scala 308:51] + node _T_9 = or(dec_csr_wen_r_mod, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 311:58] + node _T_10 = bits(_T_9, 0, 0) @[dec_tlu_ctl.scala 311:74] inst rvclkhdr of rvclkhdr_716 @[lib.scala 327:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 328:17] rvclkhdr.io.en <= _T_10 @[lib.scala 329:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_11 = or(io.lsu_error_pkt_r.valid, lsu_exc_valid_r_d1) @[dec_tlu_ctl.scala 316:67] - node _T_12 = or(_T_11, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 316:88] - node _T_13 = bits(_T_12, 0, 0) @[dec_tlu_ctl.scala 316:104] + node _T_11 = or(io.lsu_error_pkt_r.valid, lsu_exc_valid_r_d1) @[dec_tlu_ctl.scala 312:67] + node _T_12 = or(_T_11, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 312:88] + node _T_13 = bits(_T_12, 0, 0) @[dec_tlu_ctl.scala 312:104] inst rvclkhdr_1 of rvclkhdr_717 @[lib.scala 327:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 328:17] rvclkhdr_1.io.en <= _T_13 @[lib.scala 329:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node e4e5_valid = or(io.dec_tlu_i0_valid_r, e5_valid) @[dec_tlu_ctl.scala 319:30] - node _T_14 = or(debug_mode_status, i_cpu_run_req_d1) @[dec_tlu_ctl.scala 320:50] - node _T_15 = or(_T_14, interrupt_valid_r) @[dec_tlu_ctl.scala 320:69] - node _T_16 = or(_T_15, interrupt_valid_r_d1) @[dec_tlu_ctl.scala 320:89] - node _T_17 = or(_T_16, reset_delayed) @[dec_tlu_ctl.scala 320:112] - node _T_18 = or(_T_17, pause_expired_r) @[dec_tlu_ctl.scala 320:128] - node _T_19 = or(_T_18, pause_expired_wb) @[dec_tlu_ctl.scala 320:146] - node _T_20 = or(_T_19, ic_perr_r) @[dec_tlu_ctl.scala 320:165] - node _T_21 = or(_T_20, ic_perr_r_d1) @[dec_tlu_ctl.scala 320:177] - node _T_22 = or(_T_21, iccm_sbecc_r) @[dec_tlu_ctl.scala 320:192] - node _T_23 = or(_T_22, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 320:207] - node flush_clkvalid = or(_T_23, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 320:225] - node _T_24 = or(e4e5_valid, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 322:49] - node _T_25 = bits(_T_24, 0, 0) @[dec_tlu_ctl.scala 322:65] + node e4e5_valid = or(io.dec_tlu_i0_valid_r, e5_valid) @[dec_tlu_ctl.scala 315:30] + node _T_14 = or(debug_mode_status, i_cpu_run_req_d1) @[dec_tlu_ctl.scala 316:50] + node _T_15 = or(_T_14, interrupt_valid_r) @[dec_tlu_ctl.scala 316:69] + node _T_16 = or(_T_15, interrupt_valid_r_d1) @[dec_tlu_ctl.scala 316:89] + node _T_17 = or(_T_16, reset_delayed) @[dec_tlu_ctl.scala 316:112] + node _T_18 = or(_T_17, pause_expired_r) @[dec_tlu_ctl.scala 316:128] + node _T_19 = or(_T_18, pause_expired_wb) @[dec_tlu_ctl.scala 316:146] + node _T_20 = or(_T_19, ic_perr_r) @[dec_tlu_ctl.scala 316:165] + node _T_21 = or(_T_20, ic_perr_r_d1) @[dec_tlu_ctl.scala 316:177] + node _T_22 = or(_T_21, iccm_sbecc_r) @[dec_tlu_ctl.scala 316:192] + node _T_23 = or(_T_22, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 316:207] + node flush_clkvalid = or(_T_23, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 316:225] + node _T_24 = or(e4e5_valid, io.dec_tlu_dec_clk_override) @[dec_tlu_ctl.scala 318:49] + node _T_25 = bits(_T_24, 0, 0) @[dec_tlu_ctl.scala 318:65] inst rvclkhdr_2 of rvclkhdr_718 @[lib.scala 327:22] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 328:17] rvclkhdr_2.io.en <= _T_25 @[lib.scala 329:16] rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_26 = or(e4e5_valid, flush_clkvalid) @[dec_tlu_ctl.scala 323:53] - node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 323:71] + node _T_26 = or(e4e5_valid, flush_clkvalid) @[dec_tlu_ctl.scala 319:53] + node _T_27 = bits(_T_26, 0, 0) @[dec_tlu_ctl.scala 319:71] inst rvclkhdr_3 of rvclkhdr_719 @[lib.scala 327:22] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[lib.scala 328:17] rvclkhdr_3.io.en <= _T_27 @[lib.scala 329:16] rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - reg iccm_repair_state_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 325:80] - iccm_repair_state_d1 <= iccm_repair_state_ns @[dec_tlu_ctl.scala 325:80] - reg _T_28 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 326:89] - _T_28 <= ic_perr_r @[dec_tlu_ctl.scala 326:89] - ic_perr_r_d1 <= _T_28 @[dec_tlu_ctl.scala 326:57] - reg _T_29 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 327:89] - _T_29 <= iccm_sbecc_r @[dec_tlu_ctl.scala 327:89] - iccm_sbecc_r_d1 <= _T_29 @[dec_tlu_ctl.scala 327:57] - reg _T_30 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 328:97] - _T_30 <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 328:97] - e5_valid <= _T_30 @[dec_tlu_ctl.scala 328:65] - reg _T_31 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 329:81] - _T_31 <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 329:81] - debug_mode_status <= _T_31 @[dec_tlu_ctl.scala 329:49] - reg lsu_pmu_load_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 330:80] - lsu_pmu_load_external_r <= io.lsu_tlu.lsu_pmu_load_external_m @[dec_tlu_ctl.scala 330:80] - reg lsu_pmu_store_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 331:72] - lsu_pmu_store_external_r <= io.lsu_tlu.lsu_pmu_store_external_m @[dec_tlu_ctl.scala 331:72] - reg tlu_flush_lower_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 332:80] - tlu_flush_lower_r_d1 <= tlu_flush_lower_r @[dec_tlu_ctl.scala 332:80] - reg _T_32 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 333:73] - _T_32 <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 333:73] - io.dec_tlu_i0_kill_writeb_wb <= _T_32 @[dec_tlu_ctl.scala 333:41] - reg internal_dbg_halt_mode_f2 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 334:72] - internal_dbg_halt_mode_f2 <= debug_mode_status @[dec_tlu_ctl.scala 334:72] - reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 335:89] - _T_33 <= force_halt @[dec_tlu_ctl.scala 335:89] - io.tlu_mem.dec_tlu_force_halt <= _T_33 @[dec_tlu_ctl.scala 335:57] - io.dec_tlu_i0_kill_writeb_r <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 339:41] - reg reset_detect : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 340:88] - reset_detect <= UInt<1>("h01") @[dec_tlu_ctl.scala 340:88] - reg reset_detected : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 341:88] - reset_detected <= reset_detect @[dec_tlu_ctl.scala 341:88] - node _T_34 = xor(reset_detect, reset_detected) @[dec_tlu_ctl.scala 342:64] - reset_delayed <= _T_34 @[dec_tlu_ctl.scala 342:49] - reg nmi_int_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 344:72] - nmi_int_delayed <= nmi_int_sync @[dec_tlu_ctl.scala 344:72] - reg nmi_int_detected_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 345:72] - nmi_int_detected_f <= nmi_int_detected @[dec_tlu_ctl.scala 345:72] - reg nmi_lsu_load_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 346:72] - nmi_lsu_load_type_f <= nmi_lsu_load_type @[dec_tlu_ctl.scala 346:72] - reg nmi_lsu_store_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 347:72] - nmi_lsu_store_type_f <= nmi_lsu_store_type @[dec_tlu_ctl.scala 347:72] - node _T_35 = not(mdseac_locked_f) @[dec_tlu_ctl.scala 351:32] - node _T_36 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 351:96] - node nmi_lsu_detected = and(_T_35, _T_36) @[dec_tlu_ctl.scala 351:49] - node _T_37 = not(nmi_int_delayed) @[dec_tlu_ctl.scala 353:45] - node _T_38 = and(nmi_int_sync, _T_37) @[dec_tlu_ctl.scala 353:43] - node _T_39 = or(_T_38, nmi_lsu_detected) @[dec_tlu_ctl.scala 353:63] - node _T_40 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 353:106] - node _T_41 = and(nmi_int_detected_f, _T_40) @[dec_tlu_ctl.scala 353:104] - node _T_42 = or(_T_39, _T_41) @[dec_tlu_ctl.scala 353:82] - node _T_43 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 353:165] - node _T_44 = and(take_ext_int_start_d3, _T_43) @[dec_tlu_ctl.scala 353:146] - node _T_45 = or(_T_42, _T_44) @[dec_tlu_ctl.scala 353:122] - nmi_int_detected <= _T_45 @[dec_tlu_ctl.scala 353:26] - node _T_46 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 355:48] - node _T_47 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 355:119] - node _T_48 = and(nmi_int_detected_f, _T_47) @[dec_tlu_ctl.scala 355:117] - node _T_49 = not(_T_48) @[dec_tlu_ctl.scala 355:96] - node _T_50 = and(_T_46, _T_49) @[dec_tlu_ctl.scala 355:94] - node _T_51 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 355:161] - node _T_52 = and(nmi_lsu_load_type_f, _T_51) @[dec_tlu_ctl.scala 355:159] - node _T_53 = or(_T_50, _T_52) @[dec_tlu_ctl.scala 355:136] - nmi_lsu_load_type <= _T_53 @[dec_tlu_ctl.scala 355:27] - node _T_54 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 356:49] - node _T_55 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 356:121] - node _T_56 = and(nmi_int_detected_f, _T_55) @[dec_tlu_ctl.scala 356:119] - node _T_57 = not(_T_56) @[dec_tlu_ctl.scala 356:98] - node _T_58 = and(_T_54, _T_57) @[dec_tlu_ctl.scala 356:96] - node _T_59 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 356:164] - node _T_60 = and(nmi_lsu_store_type_f, _T_59) @[dec_tlu_ctl.scala 356:162] - node _T_61 = or(_T_58, _T_60) @[dec_tlu_ctl.scala 356:138] - nmi_lsu_store_type <= _T_61 @[dec_tlu_ctl.scala 356:28] - node _T_62 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 363:69] - node mpc_debug_halt_req_sync = and(mpc_debug_halt_req_sync_raw, _T_62) @[dec_tlu_ctl.scala 363:67] - reg mpc_debug_halt_req_sync_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 364:72] - mpc_debug_halt_req_sync_f <= mpc_debug_halt_req_sync @[dec_tlu_ctl.scala 364:72] - reg mpc_debug_run_req_sync_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 365:72] - mpc_debug_run_req_sync_f <= mpc_debug_run_req_sync @[dec_tlu_ctl.scala 365:72] - reg _T_63 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 366:89] - _T_63 <= mpc_halt_state_ns @[dec_tlu_ctl.scala 366:89] - mpc_halt_state_f <= _T_63 @[dec_tlu_ctl.scala 366:57] - reg mpc_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 367:88] - mpc_run_state_f <= mpc_run_state_ns @[dec_tlu_ctl.scala 367:88] - reg debug_brkpt_status_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 368:80] - debug_brkpt_status_f <= debug_brkpt_status_ns @[dec_tlu_ctl.scala 368:80] - reg mpc_debug_halt_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 369:80] - mpc_debug_halt_ack_f <= mpc_debug_halt_ack_ns @[dec_tlu_ctl.scala 369:80] - reg mpc_debug_run_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 370:80] - mpc_debug_run_ack_f <= mpc_debug_run_ack_ns @[dec_tlu_ctl.scala 370:80] - reg _T_64 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 371:89] - _T_64 <= dbg_halt_state_ns @[dec_tlu_ctl.scala 371:89] - dbg_halt_state_f <= _T_64 @[dec_tlu_ctl.scala 371:57] - reg dbg_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 372:88] - dbg_run_state_f <= dbg_run_state_ns @[dec_tlu_ctl.scala 372:88] - reg _T_65 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 373:81] - _T_65 <= dec_tlu_mpc_halted_only_ns @[dec_tlu_ctl.scala 373:81] - io.dec_tlu_mpc_halted_only <= _T_65 @[dec_tlu_ctl.scala 373:49] - node _T_66 = not(mpc_debug_halt_req_sync_f) @[dec_tlu_ctl.scala 377:71] - node mpc_debug_halt_req_sync_pulse = and(mpc_debug_halt_req_sync, _T_66) @[dec_tlu_ctl.scala 377:69] - node _T_67 = not(mpc_debug_run_req_sync_f) @[dec_tlu_ctl.scala 378:70] - node mpc_debug_run_req_sync_pulse = and(mpc_debug_run_req_sync, _T_67) @[dec_tlu_ctl.scala 378:68] - node _T_68 = or(mpc_halt_state_f, mpc_debug_halt_req_sync_pulse) @[dec_tlu_ctl.scala 380:48] - node _T_69 = not(io.mpc_reset_run_req) @[dec_tlu_ctl.scala 380:99] - node _T_70 = and(reset_delayed, _T_69) @[dec_tlu_ctl.scala 380:97] - node _T_71 = or(_T_68, _T_70) @[dec_tlu_ctl.scala 380:80] - node _T_72 = not(mpc_debug_run_req_sync) @[dec_tlu_ctl.scala 380:125] - node _T_73 = and(_T_71, _T_72) @[dec_tlu_ctl.scala 380:123] - mpc_halt_state_ns <= _T_73 @[dec_tlu_ctl.scala 380:27] - node _T_74 = not(mpc_debug_run_ack_f) @[dec_tlu_ctl.scala 381:80] - node _T_75 = and(mpc_debug_run_req_sync_pulse, _T_74) @[dec_tlu_ctl.scala 381:78] - node _T_76 = or(mpc_run_state_f, _T_75) @[dec_tlu_ctl.scala 381:46] - node _T_77 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 381:133] - node _T_78 = and(debug_mode_status, _T_77) @[dec_tlu_ctl.scala 381:131] - node _T_79 = and(_T_76, _T_78) @[dec_tlu_ctl.scala 381:103] - mpc_run_state_ns <= _T_79 @[dec_tlu_ctl.scala 381:26] - node _T_80 = or(dbg_halt_req_final, dcsr_single_step_done_f) @[dec_tlu_ctl.scala 383:70] - node _T_81 = or(_T_80, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 383:96] - node _T_82 = or(_T_81, ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 383:121] - node _T_83 = or(dbg_halt_state_f, _T_82) @[dec_tlu_ctl.scala 383:48] - node _T_84 = not(io.dbg_resume_req) @[dec_tlu_ctl.scala 383:153] - node _T_85 = and(_T_83, _T_84) @[dec_tlu_ctl.scala 383:151] - dbg_halt_state_ns <= _T_85 @[dec_tlu_ctl.scala 383:27] - node _T_86 = or(dbg_run_state_f, io.dbg_resume_req) @[dec_tlu_ctl.scala 384:46] - node _T_87 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 384:97] - node _T_88 = and(debug_mode_status, _T_87) @[dec_tlu_ctl.scala 384:95] - node _T_89 = and(_T_86, _T_88) @[dec_tlu_ctl.scala 384:67] - dbg_run_state_ns <= _T_89 @[dec_tlu_ctl.scala 384:26] - node _T_90 = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 387:39] - node _T_91 = and(_T_90, mpc_halt_state_f) @[dec_tlu_ctl.scala 387:57] - dec_tlu_mpc_halted_only_ns <= _T_91 @[dec_tlu_ctl.scala 387:36] - node debug_brkpt_valid = or(ebreak_to_debug_mode_r_d1, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 390:59] - node _T_92 = or(debug_brkpt_valid, debug_brkpt_status_f) @[dec_tlu_ctl.scala 391:53] - node _T_93 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 391:105] - node _T_94 = and(internal_dbg_halt_mode, _T_93) @[dec_tlu_ctl.scala 391:103] - node _T_95 = and(_T_92, _T_94) @[dec_tlu_ctl.scala 391:77] - debug_brkpt_status_ns <= _T_95 @[dec_tlu_ctl.scala 391:31] - node _T_96 = and(mpc_halt_state_f, debug_mode_status) @[dec_tlu_ctl.scala 394:51] - node _T_97 = and(_T_96, mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 394:78] - node _T_98 = and(_T_97, core_empty) @[dec_tlu_ctl.scala 394:104] - mpc_debug_halt_ack_ns <= _T_98 @[dec_tlu_ctl.scala 394:31] - node _T_99 = not(dbg_halt_state_ns) @[dec_tlu_ctl.scala 395:59] - node _T_100 = and(mpc_debug_run_req_sync, _T_99) @[dec_tlu_ctl.scala 395:57] - node _T_101 = not(mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 395:80] - node _T_102 = and(_T_100, _T_101) @[dec_tlu_ctl.scala 395:78] - node _T_103 = and(mpc_debug_run_ack_f, mpc_debug_run_req_sync) @[dec_tlu_ctl.scala 395:129] - node _T_104 = or(_T_102, _T_103) @[dec_tlu_ctl.scala 395:106] - mpc_debug_run_ack_ns <= _T_104 @[dec_tlu_ctl.scala 395:30] - io.mpc_debug_halt_ack <= mpc_debug_halt_ack_f @[dec_tlu_ctl.scala 398:31] - io.mpc_debug_run_ack <= mpc_debug_run_ack_f @[dec_tlu_ctl.scala 399:31] - io.debug_brkpt_status <= debug_brkpt_status_f @[dec_tlu_ctl.scala 400:31] - node _T_105 = or(io.dbg_halt_req, dbg_halt_req_held) @[dec_tlu_ctl.scala 403:53] - node dbg_halt_req_held_ns = and(_T_105, ext_int_freeze_d1) @[dec_tlu_ctl.scala 403:74] - node _T_106 = or(io.dbg_halt_req, dbg_halt_req_held) @[dec_tlu_ctl.scala 404:48] - node _T_107 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 404:71] - node _T_108 = and(_T_106, _T_107) @[dec_tlu_ctl.scala 404:69] - dbg_halt_req_final <= _T_108 @[dec_tlu_ctl.scala 404:28] - node _T_109 = or(dbg_halt_req_final, mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 407:50] - node _T_110 = not(io.mpc_reset_run_req) @[dec_tlu_ctl.scala 407:95] - node _T_111 = and(reset_delayed, _T_110) @[dec_tlu_ctl.scala 407:93] - node _T_112 = or(_T_109, _T_111) @[dec_tlu_ctl.scala 407:76] - node _T_113 = not(debug_mode_status) @[dec_tlu_ctl.scala 407:121] - node _T_114 = and(_T_112, _T_113) @[dec_tlu_ctl.scala 407:119] - node _T_115 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 407:149] - node debug_halt_req = and(_T_114, _T_115) @[dec_tlu_ctl.scala 407:147] - node _T_116 = not(debug_resume_req_f) @[dec_tlu_ctl.scala 409:32] - node _T_117 = not(dbg_halt_state_ns) @[dec_tlu_ctl.scala 409:75] - node _T_118 = and(mpc_run_state_ns, _T_117) @[dec_tlu_ctl.scala 409:73] - node _T_119 = not(mpc_halt_state_ns) @[dec_tlu_ctl.scala 409:117] - node _T_120 = and(dbg_run_state_ns, _T_119) @[dec_tlu_ctl.scala 409:115] - node _T_121 = or(_T_118, _T_120) @[dec_tlu_ctl.scala 409:95] - node debug_resume_req = and(_T_116, _T_121) @[dec_tlu_ctl.scala 409:52] - node _T_122 = or(debug_halt_req_f, pmu_fw_halt_req_f) @[dec_tlu_ctl.scala 414:43] - node _T_123 = not(synchronous_flush_r) @[dec_tlu_ctl.scala 414:66] - node _T_124 = and(_T_122, _T_123) @[dec_tlu_ctl.scala 414:64] - node _T_125 = not(mret_r) @[dec_tlu_ctl.scala 414:89] - node _T_126 = and(_T_124, _T_125) @[dec_tlu_ctl.scala 414:87] - node _T_127 = not(halt_taken_f) @[dec_tlu_ctl.scala 414:99] - node _T_128 = and(_T_126, _T_127) @[dec_tlu_ctl.scala 414:97] - node _T_129 = not(dec_tlu_flush_noredir_r_d1) @[dec_tlu_ctl.scala 414:115] - node _T_130 = and(_T_128, _T_129) @[dec_tlu_ctl.scala 414:113] - node _T_131 = not(take_reset) @[dec_tlu_ctl.scala 414:145] - node take_halt = and(_T_130, _T_131) @[dec_tlu_ctl.scala 414:143] - node _T_132 = not(dec_tlu_flush_pause_r_d1) @[dec_tlu_ctl.scala 417:56] - node _T_133 = and(dec_tlu_flush_noredir_r_d1, _T_132) @[dec_tlu_ctl.scala 417:54] - node _T_134 = not(take_ext_int_start_d1) @[dec_tlu_ctl.scala 417:84] - node _T_135 = and(_T_133, _T_134) @[dec_tlu_ctl.scala 417:82] - node _T_136 = not(dbg_tlu_halted_f) @[dec_tlu_ctl.scala 417:126] - node _T_137 = and(halt_taken_f, _T_136) @[dec_tlu_ctl.scala 417:124] - node _T_138 = not(pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 417:146] - node _T_139 = and(_T_137, _T_138) @[dec_tlu_ctl.scala 417:144] - node _T_140 = not(interrupt_valid_r_d1) @[dec_tlu_ctl.scala 417:169] - node _T_141 = and(_T_139, _T_140) @[dec_tlu_ctl.scala 417:167] - node halt_taken = or(_T_135, _T_141) @[dec_tlu_ctl.scala 417:108] - node _T_142 = and(io.lsu_idle_any, lsu_idle_any_f) @[dec_tlu_ctl.scala 421:53] - node _T_143 = and(_T_142, io.tlu_mem.ifu_miss_state_idle) @[dec_tlu_ctl.scala 421:70] - node _T_144 = and(_T_143, ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 421:103] - node _T_145 = not(debug_halt_req) @[dec_tlu_ctl.scala 421:129] - node _T_146 = and(_T_144, _T_145) @[dec_tlu_ctl.scala 421:127] - node _T_147 = not(debug_halt_req_d1) @[dec_tlu_ctl.scala 421:147] - node _T_148 = and(_T_146, _T_147) @[dec_tlu_ctl.scala 421:145] - node _T_149 = not(io.dec_div_active) @[dec_tlu_ctl.scala 421:168] - node _T_150 = and(_T_148, _T_149) @[dec_tlu_ctl.scala 421:166] - node _T_151 = or(force_halt, _T_150) @[dec_tlu_ctl.scala 421:34] - core_empty <= _T_151 @[dec_tlu_ctl.scala 421:20] - node _T_152 = not(debug_mode_status) @[dec_tlu_ctl.scala 427:37] - node _T_153 = and(_T_152, debug_halt_req) @[dec_tlu_ctl.scala 427:63] - node _T_154 = or(_T_153, dcsr_single_step_done_f) @[dec_tlu_ctl.scala 427:81] - node _T_155 = or(_T_154, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 427:107] - node enter_debug_halt_req = or(_T_155, ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 427:132] - node _T_156 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 430:111] - node _T_157 = not(_T_156) @[dec_tlu_ctl.scala 430:106] - node _T_158 = and(debug_resume_req_f, _T_157) @[dec_tlu_ctl.scala 430:104] - node _T_159 = not(_T_158) @[dec_tlu_ctl.scala 430:83] - node _T_160 = and(debug_mode_status, _T_159) @[dec_tlu_ctl.scala 430:81] - node _T_161 = or(debug_halt_req_ns, _T_160) @[dec_tlu_ctl.scala 430:53] - internal_dbg_halt_mode <= _T_161 @[dec_tlu_ctl.scala 430:32] - node _T_162 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 432:67] - node allow_dbg_halt_csr_write = and(debug_mode_status, _T_162) @[dec_tlu_ctl.scala 432:65] - node _T_163 = and(debug_halt_req_f, core_empty) @[dec_tlu_ctl.scala 437:48] - node _T_164 = and(_T_163, halt_taken) @[dec_tlu_ctl.scala 437:61] - node _T_165 = not(debug_resume_req_f) @[dec_tlu_ctl.scala 437:97] - node _T_166 = and(dbg_tlu_halted_f, _T_165) @[dec_tlu_ctl.scala 437:95] - node dbg_tlu_halted = or(_T_164, _T_166) @[dec_tlu_ctl.scala 437:75] - node _T_167 = not(dbg_tlu_halted) @[dec_tlu_ctl.scala 438:73] - node _T_168 = and(debug_halt_req_f, _T_167) @[dec_tlu_ctl.scala 438:71] - node _T_169 = or(enter_debug_halt_req, _T_168) @[dec_tlu_ctl.scala 438:51] - debug_halt_req_ns <= _T_169 @[dec_tlu_ctl.scala 438:27] - node _T_170 = and(debug_resume_req_f, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 439:49] - node resume_ack_ns = and(_T_170, dbg_run_state_ns) @[dec_tlu_ctl.scala 439:68] - node _T_171 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 441:61] - node _T_172 = and(io.dec_tlu_i0_valid_r, _T_171) @[dec_tlu_ctl.scala 441:59] - node _T_173 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 441:90] - node _T_174 = and(_T_172, _T_173) @[dec_tlu_ctl.scala 441:84] - node _T_175 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 441:104] - node dcsr_single_step_done = and(_T_174, _T_175) @[dec_tlu_ctl.scala 441:102] - node _T_176 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 443:66] - node _T_177 = and(debug_resume_req_f, _T_176) @[dec_tlu_ctl.scala 443:60] - node _T_178 = not(dcsr_single_step_done_f) @[dec_tlu_ctl.scala 443:111] - node _T_179 = and(dcsr_single_step_running_f, _T_178) @[dec_tlu_ctl.scala 443:109] - node dcsr_single_step_running = or(_T_177, _T_179) @[dec_tlu_ctl.scala 443:79] - node dbg_cmd_done_ns = and(io.dec_tlu_i0_valid_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 445:53] - node _T_180 = or(trigger_hit_dmode_r, ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 448:57] - node _T_181 = not(io.tlu_bp.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 448:112] - node _T_182 = and(request_debug_mode_r_d1, _T_181) @[dec_tlu_ctl.scala 448:110] - node request_debug_mode_r = or(_T_180, _T_182) @[dec_tlu_ctl.scala 448:83] - node _T_183 = or(request_debug_mode_r_d1, request_debug_mode_done_f) @[dec_tlu_ctl.scala 450:64] - node _T_184 = not(dbg_tlu_halted_f) @[dec_tlu_ctl.scala 450:95] - node request_debug_mode_done = and(_T_183, _T_184) @[dec_tlu_ctl.scala 450:93] - reg _T_185 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 453:81] - _T_185 <= io.tlu_ifc.dec_tlu_flush_noredir_wb @[dec_tlu_ctl.scala 453:81] - dec_tlu_flush_noredir_r_d1 <= _T_185 @[dec_tlu_ctl.scala 453:49] - reg _T_186 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 454:89] - _T_186 <= halt_taken @[dec_tlu_ctl.scala 454:89] - halt_taken_f <= _T_186 @[dec_tlu_ctl.scala 454:57] - reg _T_187 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 455:89] - _T_187 <= io.lsu_idle_any @[dec_tlu_ctl.scala 455:89] - lsu_idle_any_f <= _T_187 @[dec_tlu_ctl.scala 455:57] - reg _T_188 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 456:81] - _T_188 <= io.tlu_mem.ifu_miss_state_idle @[dec_tlu_ctl.scala 456:81] - ifu_miss_state_idle_f <= _T_188 @[dec_tlu_ctl.scala 456:49] - reg _T_189 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 457:89] - _T_189 <= dbg_tlu_halted @[dec_tlu_ctl.scala 457:89] - dbg_tlu_halted_f <= _T_189 @[dec_tlu_ctl.scala 457:57] - reg _T_190 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 458:81] - _T_190 <= resume_ack_ns @[dec_tlu_ctl.scala 458:81] - io.dec_tlu_resume_ack <= _T_190 @[dec_tlu_ctl.scala 458:49] - reg _T_191 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 459:89] - _T_191 <= debug_halt_req_ns @[dec_tlu_ctl.scala 459:89] - debug_halt_req_f <= _T_191 @[dec_tlu_ctl.scala 459:57] - reg _T_192 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 460:89] - _T_192 <= debug_resume_req @[dec_tlu_ctl.scala 460:89] - debug_resume_req_f <= _T_192 @[dec_tlu_ctl.scala 460:57] - reg _T_193 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 461:81] - _T_193 <= trigger_hit_dmode_r @[dec_tlu_ctl.scala 461:81] - trigger_hit_dmode_r_d1 <= _T_193 @[dec_tlu_ctl.scala 461:49] - reg _T_194 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 462:81] - _T_194 <= dcsr_single_step_done @[dec_tlu_ctl.scala 462:81] - dcsr_single_step_done_f <= _T_194 @[dec_tlu_ctl.scala 462:49] - reg _T_195 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 463:89] - _T_195 <= debug_halt_req @[dec_tlu_ctl.scala 463:89] - debug_halt_req_d1 <= _T_195 @[dec_tlu_ctl.scala 463:57] - reg dec_tlu_wr_pause_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 464:81] - dec_tlu_wr_pause_r_d1 <= io.dec_tlu_wr_pause_r @[dec_tlu_ctl.scala 464:81] - reg dec_pause_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 465:81] - dec_pause_state_f <= io.dec_pause_state @[dec_tlu_ctl.scala 465:81] - reg _T_196 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 466:81] - _T_196 <= request_debug_mode_r @[dec_tlu_ctl.scala 466:81] - request_debug_mode_r_d1 <= _T_196 @[dec_tlu_ctl.scala 466:49] - reg _T_197 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 467:73] - _T_197 <= request_debug_mode_done @[dec_tlu_ctl.scala 467:73] - request_debug_mode_done_f <= _T_197 @[dec_tlu_ctl.scala 467:41] - reg _T_198 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 468:73] - _T_198 <= dcsr_single_step_running @[dec_tlu_ctl.scala 468:73] - dcsr_single_step_running_f <= _T_198 @[dec_tlu_ctl.scala 468:41] - reg _T_199 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 469:73] - _T_199 <= io.dec_tlu_flush_pause_r @[dec_tlu_ctl.scala 469:73] - dec_tlu_flush_pause_r_d1 <= _T_199 @[dec_tlu_ctl.scala 469:41] - reg _T_200 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 470:81] - _T_200 <= dbg_halt_req_held_ns @[dec_tlu_ctl.scala 470:81] - dbg_halt_req_held <= _T_200 @[dec_tlu_ctl.scala 470:49] - io.dec_tlu_debug_stall <= debug_halt_req_f @[dec_tlu_ctl.scala 473:41] - io.dec_tlu_dbg_halted <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 474:41] - io.dec_tlu_debug_mode <= debug_mode_status @[dec_tlu_ctl.scala 475:41] - dec_tlu_pmu_fw_halted <= pmu_fw_tlu_halted_f @[dec_tlu_ctl.scala 476:41] - node _T_201 = and(fence_i_r, internal_dbg_halt_mode) @[dec_tlu_ctl.scala 479:71] - node _T_202 = or(take_halt, _T_201) @[dec_tlu_ctl.scala 479:58] - node _T_203 = or(_T_202, io.dec_tlu_flush_pause_r) @[dec_tlu_ctl.scala 479:97] - node _T_204 = and(i0_trigger_hit_r, trigger_hit_dmode_r) @[dec_tlu_ctl.scala 479:144] - node _T_205 = or(_T_203, _T_204) @[dec_tlu_ctl.scala 479:124] - node _T_206 = or(_T_205, take_ext_int_start) @[dec_tlu_ctl.scala 479:167] - io.tlu_ifc.dec_tlu_flush_noredir_wb <= _T_206 @[dec_tlu_ctl.scala 479:45] - io.dec_tlu_flush_extint <= take_ext_int_start @[dec_tlu_ctl.scala 481:33] - node _T_207 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 484:61] - node _T_208 = and(dec_tlu_wr_pause_r_d1, _T_207) @[dec_tlu_ctl.scala 484:59] - node _T_209 = not(take_ext_int_start) @[dec_tlu_ctl.scala 484:82] - node _T_210 = and(_T_208, _T_209) @[dec_tlu_ctl.scala 484:80] - io.dec_tlu_flush_pause_r <= _T_210 @[dec_tlu_ctl.scala 484:34] - node _T_211 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 486:28] - node _T_212 = and(_T_211, dec_pause_state_f) @[dec_tlu_ctl.scala 486:48] - node _T_213 = or(ext_int_ready, ce_int_ready) @[dec_tlu_ctl.scala 486:86] - node _T_214 = or(_T_213, timer_int_ready) @[dec_tlu_ctl.scala 486:101] - node _T_215 = or(_T_214, soft_int_ready) @[dec_tlu_ctl.scala 486:119] - node _T_216 = or(_T_215, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 486:136] - node _T_217 = or(_T_216, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 486:160] - node _T_218 = or(_T_217, nmi_int_detected) @[dec_tlu_ctl.scala 486:184] - node _T_219 = or(_T_218, ext_int_freeze_d1) @[dec_tlu_ctl.scala 486:203] - node _T_220 = not(_T_219) @[dec_tlu_ctl.scala 486:70] - node _T_221 = and(_T_212, _T_220) @[dec_tlu_ctl.scala 486:68] - node _T_222 = not(interrupt_valid_r_d1) @[dec_tlu_ctl.scala 486:226] - node _T_223 = and(_T_221, _T_222) @[dec_tlu_ctl.scala 486:224] - node _T_224 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 486:250] - node _T_225 = and(_T_223, _T_224) @[dec_tlu_ctl.scala 486:248] - node _T_226 = not(pmu_fw_halt_req_f) @[dec_tlu_ctl.scala 486:270] - node _T_227 = and(_T_225, _T_226) @[dec_tlu_ctl.scala 486:268] - node _T_228 = not(halt_taken_f) @[dec_tlu_ctl.scala 486:291] - node _T_229 = and(_T_227, _T_228) @[dec_tlu_ctl.scala 486:289] - pause_expired_r <= _T_229 @[dec_tlu_ctl.scala 486:25] - node _T_230 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 488:88] - node _T_231 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_230) @[dec_tlu_ctl.scala 488:82] - node _T_232 = or(io.dec_tlu_resume_ack, dcsr_single_step_running) @[dec_tlu_ctl.scala 488:125] - node _T_233 = and(_T_231, _T_232) @[dec_tlu_ctl.scala 488:100] - node _T_234 = not(io.tlu_ifc.dec_tlu_flush_noredir_wb) @[dec_tlu_ctl.scala 488:155] - node _T_235 = and(_T_233, _T_234) @[dec_tlu_ctl.scala 488:153] - io.tlu_bp.dec_tlu_flush_leak_one_wb <= _T_235 @[dec_tlu_ctl.scala 488:45] - node _T_236 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 489:93] - node _T_237 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_236) @[dec_tlu_ctl.scala 489:77] - io.tlu_mem.dec_tlu_flush_err_wb <= _T_237 @[dec_tlu_ctl.scala 489:41] - io.dec_dbg_cmd_done <= dbg_cmd_done_ns @[dec_tlu_ctl.scala 492:29] - node _T_238 = and(illegal_r, io.dec_dbg_cmd_done) @[dec_tlu_ctl.scala 493:42] - io.dec_dbg_cmd_fail <= _T_238 @[dec_tlu_ctl.scala 493:29] - node _T_239 = bits(mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 506:48] - node _T_240 = bits(mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 506:75] - node _T_241 = bits(mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 506:102] - node _T_242 = bits(mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 506:129] + reg iccm_repair_state_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 321:80] + iccm_repair_state_d1 <= iccm_repair_state_ns @[dec_tlu_ctl.scala 321:80] + reg _T_28 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 322:89] + _T_28 <= ic_perr_r @[dec_tlu_ctl.scala 322:89] + ic_perr_r_d1 <= _T_28 @[dec_tlu_ctl.scala 322:57] + reg _T_29 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 323:89] + _T_29 <= iccm_sbecc_r @[dec_tlu_ctl.scala 323:89] + iccm_sbecc_r_d1 <= _T_29 @[dec_tlu_ctl.scala 323:57] + reg _T_30 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 324:97] + _T_30 <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 324:97] + e5_valid <= _T_30 @[dec_tlu_ctl.scala 324:65] + reg _T_31 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 325:81] + _T_31 <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 325:81] + debug_mode_status <= _T_31 @[dec_tlu_ctl.scala 325:49] + reg lsu_pmu_load_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 326:80] + lsu_pmu_load_external_r <= io.lsu_tlu.lsu_pmu_load_external_m @[dec_tlu_ctl.scala 326:80] + reg lsu_pmu_store_external_r : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 327:72] + lsu_pmu_store_external_r <= io.lsu_tlu.lsu_pmu_store_external_m @[dec_tlu_ctl.scala 327:72] + reg tlu_flush_lower_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 328:80] + tlu_flush_lower_r_d1 <= tlu_flush_lower_r @[dec_tlu_ctl.scala 328:80] + reg _T_32 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 329:73] + _T_32 <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 329:73] + io.dec_tlu_i0_kill_writeb_wb <= _T_32 @[dec_tlu_ctl.scala 329:41] + reg internal_dbg_halt_mode_f2 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 330:72] + internal_dbg_halt_mode_f2 <= debug_mode_status @[dec_tlu_ctl.scala 330:72] + reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 331:89] + _T_33 <= force_halt @[dec_tlu_ctl.scala 331:89] + io.tlu_mem.dec_tlu_force_halt <= _T_33 @[dec_tlu_ctl.scala 331:57] + io.dec_tlu_i0_kill_writeb_r <= tlu_i0_kill_writeb_r @[dec_tlu_ctl.scala 335:41] + reg reset_detect : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 336:88] + reset_detect <= UInt<1>("h01") @[dec_tlu_ctl.scala 336:88] + reg reset_detected : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 337:88] + reset_detected <= reset_detect @[dec_tlu_ctl.scala 337:88] + node _T_34 = xor(reset_detect, reset_detected) @[dec_tlu_ctl.scala 338:64] + reset_delayed <= _T_34 @[dec_tlu_ctl.scala 338:49] + reg nmi_int_delayed : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 340:72] + nmi_int_delayed <= nmi_int_sync @[dec_tlu_ctl.scala 340:72] + reg nmi_int_detected_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 341:72] + nmi_int_detected_f <= nmi_int_detected @[dec_tlu_ctl.scala 341:72] + reg nmi_lsu_load_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 342:72] + nmi_lsu_load_type_f <= nmi_lsu_load_type @[dec_tlu_ctl.scala 342:72] + reg nmi_lsu_store_type_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 343:72] + nmi_lsu_store_type_f <= nmi_lsu_store_type @[dec_tlu_ctl.scala 343:72] + node _T_35 = not(mdseac_locked_f) @[dec_tlu_ctl.scala 347:32] + node _T_36 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 347:96] + node nmi_lsu_detected = and(_T_35, _T_36) @[dec_tlu_ctl.scala 347:49] + node _T_37 = not(nmi_int_delayed) @[dec_tlu_ctl.scala 349:45] + node _T_38 = and(nmi_int_sync, _T_37) @[dec_tlu_ctl.scala 349:43] + node _T_39 = or(_T_38, nmi_lsu_detected) @[dec_tlu_ctl.scala 349:63] + node _T_40 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 349:106] + node _T_41 = and(nmi_int_detected_f, _T_40) @[dec_tlu_ctl.scala 349:104] + node _T_42 = or(_T_39, _T_41) @[dec_tlu_ctl.scala 349:82] + node _T_43 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 349:165] + node _T_44 = and(take_ext_int_start_d3, _T_43) @[dec_tlu_ctl.scala 349:146] + node _T_45 = or(_T_42, _T_44) @[dec_tlu_ctl.scala 349:122] + nmi_int_detected <= _T_45 @[dec_tlu_ctl.scala 349:26] + node _T_46 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_load_any) @[dec_tlu_ctl.scala 351:48] + node _T_47 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 351:119] + node _T_48 = and(nmi_int_detected_f, _T_47) @[dec_tlu_ctl.scala 351:117] + node _T_49 = not(_T_48) @[dec_tlu_ctl.scala 351:96] + node _T_50 = and(_T_46, _T_49) @[dec_tlu_ctl.scala 351:94] + node _T_51 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 351:161] + node _T_52 = and(nmi_lsu_load_type_f, _T_51) @[dec_tlu_ctl.scala 351:159] + node _T_53 = or(_T_50, _T_52) @[dec_tlu_ctl.scala 351:136] + nmi_lsu_load_type <= _T_53 @[dec_tlu_ctl.scala 351:27] + node _T_54 = and(nmi_lsu_detected, io.tlu_busbuff.lsu_imprecise_error_store_any) @[dec_tlu_ctl.scala 352:49] + node _T_55 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 352:121] + node _T_56 = and(nmi_int_detected_f, _T_55) @[dec_tlu_ctl.scala 352:119] + node _T_57 = not(_T_56) @[dec_tlu_ctl.scala 352:98] + node _T_58 = and(_T_54, _T_57) @[dec_tlu_ctl.scala 352:96] + node _T_59 = not(take_nmi_r_d1) @[dec_tlu_ctl.scala 352:164] + node _T_60 = and(nmi_lsu_store_type_f, _T_59) @[dec_tlu_ctl.scala 352:162] + node _T_61 = or(_T_58, _T_60) @[dec_tlu_ctl.scala 352:138] + nmi_lsu_store_type <= _T_61 @[dec_tlu_ctl.scala 352:28] + node _T_62 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 359:69] + node mpc_debug_halt_req_sync = and(mpc_debug_halt_req_sync_raw, _T_62) @[dec_tlu_ctl.scala 359:67] + reg mpc_debug_halt_req_sync_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 360:72] + mpc_debug_halt_req_sync_f <= mpc_debug_halt_req_sync @[dec_tlu_ctl.scala 360:72] + reg mpc_debug_run_req_sync_f : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 361:72] + mpc_debug_run_req_sync_f <= mpc_debug_run_req_sync @[dec_tlu_ctl.scala 361:72] + reg _T_63 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 362:89] + _T_63 <= mpc_halt_state_ns @[dec_tlu_ctl.scala 362:89] + mpc_halt_state_f <= _T_63 @[dec_tlu_ctl.scala 362:57] + reg mpc_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 363:88] + mpc_run_state_f <= mpc_run_state_ns @[dec_tlu_ctl.scala 363:88] + reg debug_brkpt_status_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 364:80] + debug_brkpt_status_f <= debug_brkpt_status_ns @[dec_tlu_ctl.scala 364:80] + reg mpc_debug_halt_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 365:80] + mpc_debug_halt_ack_f <= mpc_debug_halt_ack_ns @[dec_tlu_ctl.scala 365:80] + reg mpc_debug_run_ack_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 366:80] + mpc_debug_run_ack_f <= mpc_debug_run_ack_ns @[dec_tlu_ctl.scala 366:80] + reg _T_64 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 367:89] + _T_64 <= dbg_halt_state_ns @[dec_tlu_ctl.scala 367:89] + dbg_halt_state_f <= _T_64 @[dec_tlu_ctl.scala 367:57] + reg dbg_run_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 368:88] + dbg_run_state_f <= dbg_run_state_ns @[dec_tlu_ctl.scala 368:88] + reg _T_65 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 369:81] + _T_65 <= dec_tlu_mpc_halted_only_ns @[dec_tlu_ctl.scala 369:81] + io.dec_tlu_mpc_halted_only <= _T_65 @[dec_tlu_ctl.scala 369:49] + node _T_66 = not(mpc_debug_halt_req_sync_f) @[dec_tlu_ctl.scala 373:71] + node mpc_debug_halt_req_sync_pulse = and(mpc_debug_halt_req_sync, _T_66) @[dec_tlu_ctl.scala 373:69] + node _T_67 = not(mpc_debug_run_req_sync_f) @[dec_tlu_ctl.scala 374:70] + node mpc_debug_run_req_sync_pulse = and(mpc_debug_run_req_sync, _T_67) @[dec_tlu_ctl.scala 374:68] + node _T_68 = or(mpc_halt_state_f, mpc_debug_halt_req_sync_pulse) @[dec_tlu_ctl.scala 376:48] + node _T_69 = not(io.mpc_reset_run_req) @[dec_tlu_ctl.scala 376:99] + node _T_70 = and(reset_delayed, _T_69) @[dec_tlu_ctl.scala 376:97] + node _T_71 = or(_T_68, _T_70) @[dec_tlu_ctl.scala 376:80] + node _T_72 = not(mpc_debug_run_req_sync) @[dec_tlu_ctl.scala 376:125] + node _T_73 = and(_T_71, _T_72) @[dec_tlu_ctl.scala 376:123] + mpc_halt_state_ns <= _T_73 @[dec_tlu_ctl.scala 376:27] + node _T_74 = not(mpc_debug_run_ack_f) @[dec_tlu_ctl.scala 377:80] + node _T_75 = and(mpc_debug_run_req_sync_pulse, _T_74) @[dec_tlu_ctl.scala 377:78] + node _T_76 = or(mpc_run_state_f, _T_75) @[dec_tlu_ctl.scala 377:46] + node _T_77 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 377:133] + node _T_78 = and(debug_mode_status, _T_77) @[dec_tlu_ctl.scala 377:131] + node _T_79 = and(_T_76, _T_78) @[dec_tlu_ctl.scala 377:103] + mpc_run_state_ns <= _T_79 @[dec_tlu_ctl.scala 377:26] + node _T_80 = or(dbg_halt_req_final, dcsr_single_step_done_f) @[dec_tlu_ctl.scala 379:70] + node _T_81 = or(_T_80, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 379:96] + node _T_82 = or(_T_81, ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 379:121] + node _T_83 = or(dbg_halt_state_f, _T_82) @[dec_tlu_ctl.scala 379:48] + node _T_84 = not(io.dbg_resume_req) @[dec_tlu_ctl.scala 379:153] + node _T_85 = and(_T_83, _T_84) @[dec_tlu_ctl.scala 379:151] + dbg_halt_state_ns <= _T_85 @[dec_tlu_ctl.scala 379:27] + node _T_86 = or(dbg_run_state_f, io.dbg_resume_req) @[dec_tlu_ctl.scala 380:46] + node _T_87 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 380:97] + node _T_88 = and(debug_mode_status, _T_87) @[dec_tlu_ctl.scala 380:95] + node _T_89 = and(_T_86, _T_88) @[dec_tlu_ctl.scala 380:67] + dbg_run_state_ns <= _T_89 @[dec_tlu_ctl.scala 380:26] + node _T_90 = not(dbg_halt_state_f) @[dec_tlu_ctl.scala 383:39] + node _T_91 = and(_T_90, mpc_halt_state_f) @[dec_tlu_ctl.scala 383:57] + dec_tlu_mpc_halted_only_ns <= _T_91 @[dec_tlu_ctl.scala 383:36] + node debug_brkpt_valid = or(ebreak_to_debug_mode_r_d1, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 386:59] + node _T_92 = or(debug_brkpt_valid, debug_brkpt_status_f) @[dec_tlu_ctl.scala 387:53] + node _T_93 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 387:105] + node _T_94 = and(internal_dbg_halt_mode, _T_93) @[dec_tlu_ctl.scala 387:103] + node _T_95 = and(_T_92, _T_94) @[dec_tlu_ctl.scala 387:77] + debug_brkpt_status_ns <= _T_95 @[dec_tlu_ctl.scala 387:31] + node _T_96 = and(mpc_halt_state_f, debug_mode_status) @[dec_tlu_ctl.scala 390:51] + node _T_97 = and(_T_96, mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 390:78] + node _T_98 = and(_T_97, core_empty) @[dec_tlu_ctl.scala 390:104] + mpc_debug_halt_ack_ns <= _T_98 @[dec_tlu_ctl.scala 390:31] + node _T_99 = not(dbg_halt_state_ns) @[dec_tlu_ctl.scala 391:59] + node _T_100 = and(mpc_debug_run_req_sync, _T_99) @[dec_tlu_ctl.scala 391:57] + node _T_101 = not(mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 391:80] + node _T_102 = and(_T_100, _T_101) @[dec_tlu_ctl.scala 391:78] + node _T_103 = and(mpc_debug_run_ack_f, mpc_debug_run_req_sync) @[dec_tlu_ctl.scala 391:129] + node _T_104 = or(_T_102, _T_103) @[dec_tlu_ctl.scala 391:106] + mpc_debug_run_ack_ns <= _T_104 @[dec_tlu_ctl.scala 391:30] + io.mpc_debug_halt_ack <= mpc_debug_halt_ack_f @[dec_tlu_ctl.scala 394:31] + io.mpc_debug_run_ack <= mpc_debug_run_ack_f @[dec_tlu_ctl.scala 395:31] + io.debug_brkpt_status <= debug_brkpt_status_f @[dec_tlu_ctl.scala 396:31] + node _T_105 = or(io.dbg_halt_req, dbg_halt_req_held) @[dec_tlu_ctl.scala 399:53] + node dbg_halt_req_held_ns = and(_T_105, ext_int_freeze_d1) @[dec_tlu_ctl.scala 399:74] + node _T_106 = or(io.dbg_halt_req, dbg_halt_req_held) @[dec_tlu_ctl.scala 400:48] + node _T_107 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 400:71] + node _T_108 = and(_T_106, _T_107) @[dec_tlu_ctl.scala 400:69] + dbg_halt_req_final <= _T_108 @[dec_tlu_ctl.scala 400:28] + node _T_109 = or(dbg_halt_req_final, mpc_debug_halt_req_sync) @[dec_tlu_ctl.scala 403:50] + node _T_110 = not(io.mpc_reset_run_req) @[dec_tlu_ctl.scala 403:95] + node _T_111 = and(reset_delayed, _T_110) @[dec_tlu_ctl.scala 403:93] + node _T_112 = or(_T_109, _T_111) @[dec_tlu_ctl.scala 403:76] + node _T_113 = not(debug_mode_status) @[dec_tlu_ctl.scala 403:121] + node _T_114 = and(_T_112, _T_113) @[dec_tlu_ctl.scala 403:119] + node _T_115 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 403:149] + node debug_halt_req = and(_T_114, _T_115) @[dec_tlu_ctl.scala 403:147] + node _T_116 = not(debug_resume_req_f) @[dec_tlu_ctl.scala 405:32] + node _T_117 = not(dbg_halt_state_ns) @[dec_tlu_ctl.scala 405:75] + node _T_118 = and(mpc_run_state_ns, _T_117) @[dec_tlu_ctl.scala 405:73] + node _T_119 = not(mpc_halt_state_ns) @[dec_tlu_ctl.scala 405:117] + node _T_120 = and(dbg_run_state_ns, _T_119) @[dec_tlu_ctl.scala 405:115] + node _T_121 = or(_T_118, _T_120) @[dec_tlu_ctl.scala 405:95] + node debug_resume_req = and(_T_116, _T_121) @[dec_tlu_ctl.scala 405:52] + node _T_122 = or(debug_halt_req_f, pmu_fw_halt_req_f) @[dec_tlu_ctl.scala 410:43] + node _T_123 = not(synchronous_flush_r) @[dec_tlu_ctl.scala 410:66] + node _T_124 = and(_T_122, _T_123) @[dec_tlu_ctl.scala 410:64] + node _T_125 = not(mret_r) @[dec_tlu_ctl.scala 410:89] + node _T_126 = and(_T_124, _T_125) @[dec_tlu_ctl.scala 410:87] + node _T_127 = not(halt_taken_f) @[dec_tlu_ctl.scala 410:99] + node _T_128 = and(_T_126, _T_127) @[dec_tlu_ctl.scala 410:97] + node _T_129 = not(dec_tlu_flush_noredir_r_d1) @[dec_tlu_ctl.scala 410:115] + node _T_130 = and(_T_128, _T_129) @[dec_tlu_ctl.scala 410:113] + node _T_131 = not(take_reset) @[dec_tlu_ctl.scala 410:145] + node take_halt = and(_T_130, _T_131) @[dec_tlu_ctl.scala 410:143] + node _T_132 = not(dec_tlu_flush_pause_r_d1) @[dec_tlu_ctl.scala 413:56] + node _T_133 = and(dec_tlu_flush_noredir_r_d1, _T_132) @[dec_tlu_ctl.scala 413:54] + node _T_134 = not(take_ext_int_start_d1) @[dec_tlu_ctl.scala 413:84] + node _T_135 = and(_T_133, _T_134) @[dec_tlu_ctl.scala 413:82] + node _T_136 = not(dbg_tlu_halted_f) @[dec_tlu_ctl.scala 413:126] + node _T_137 = and(halt_taken_f, _T_136) @[dec_tlu_ctl.scala 413:124] + node _T_138 = not(pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 413:146] + node _T_139 = and(_T_137, _T_138) @[dec_tlu_ctl.scala 413:144] + node _T_140 = not(interrupt_valid_r_d1) @[dec_tlu_ctl.scala 413:169] + node _T_141 = and(_T_139, _T_140) @[dec_tlu_ctl.scala 413:167] + node halt_taken = or(_T_135, _T_141) @[dec_tlu_ctl.scala 413:108] + node _T_142 = and(io.lsu_idle_any, lsu_idle_any_f) @[dec_tlu_ctl.scala 417:53] + node _T_143 = and(_T_142, io.tlu_mem.ifu_miss_state_idle) @[dec_tlu_ctl.scala 417:70] + node _T_144 = and(_T_143, ifu_miss_state_idle_f) @[dec_tlu_ctl.scala 417:103] + node _T_145 = not(debug_halt_req) @[dec_tlu_ctl.scala 417:129] + node _T_146 = and(_T_144, _T_145) @[dec_tlu_ctl.scala 417:127] + node _T_147 = not(debug_halt_req_d1) @[dec_tlu_ctl.scala 417:147] + node _T_148 = and(_T_146, _T_147) @[dec_tlu_ctl.scala 417:145] + node _T_149 = not(io.dec_div_active) @[dec_tlu_ctl.scala 417:168] + node _T_150 = and(_T_148, _T_149) @[dec_tlu_ctl.scala 417:166] + node _T_151 = or(force_halt, _T_150) @[dec_tlu_ctl.scala 417:34] + core_empty <= _T_151 @[dec_tlu_ctl.scala 417:20] + node _T_152 = not(debug_mode_status) @[dec_tlu_ctl.scala 423:37] + node _T_153 = and(_T_152, debug_halt_req) @[dec_tlu_ctl.scala 423:63] + node _T_154 = or(_T_153, dcsr_single_step_done_f) @[dec_tlu_ctl.scala 423:81] + node _T_155 = or(_T_154, trigger_hit_dmode_r_d1) @[dec_tlu_ctl.scala 423:107] + node enter_debug_halt_req = or(_T_155, ebreak_to_debug_mode_r_d1) @[dec_tlu_ctl.scala 423:132] + node _T_156 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 426:111] + node _T_157 = not(_T_156) @[dec_tlu_ctl.scala 426:106] + node _T_158 = and(debug_resume_req_f, _T_157) @[dec_tlu_ctl.scala 426:104] + node _T_159 = not(_T_158) @[dec_tlu_ctl.scala 426:83] + node _T_160 = and(debug_mode_status, _T_159) @[dec_tlu_ctl.scala 426:81] + node _T_161 = or(debug_halt_req_ns, _T_160) @[dec_tlu_ctl.scala 426:53] + internal_dbg_halt_mode <= _T_161 @[dec_tlu_ctl.scala 426:32] + node _T_162 = not(dcsr_single_step_running_f) @[dec_tlu_ctl.scala 428:67] + node allow_dbg_halt_csr_write = and(debug_mode_status, _T_162) @[dec_tlu_ctl.scala 428:65] + node _T_163 = and(debug_halt_req_f, core_empty) @[dec_tlu_ctl.scala 433:48] + node _T_164 = and(_T_163, halt_taken) @[dec_tlu_ctl.scala 433:61] + node _T_165 = not(debug_resume_req_f) @[dec_tlu_ctl.scala 433:97] + node _T_166 = and(dbg_tlu_halted_f, _T_165) @[dec_tlu_ctl.scala 433:95] + node dbg_tlu_halted = or(_T_164, _T_166) @[dec_tlu_ctl.scala 433:75] + node _T_167 = not(dbg_tlu_halted) @[dec_tlu_ctl.scala 434:73] + node _T_168 = and(debug_halt_req_f, _T_167) @[dec_tlu_ctl.scala 434:71] + node _T_169 = or(enter_debug_halt_req, _T_168) @[dec_tlu_ctl.scala 434:51] + debug_halt_req_ns <= _T_169 @[dec_tlu_ctl.scala 434:27] + node _T_170 = and(debug_resume_req_f, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 435:49] + node resume_ack_ns = and(_T_170, dbg_run_state_ns) @[dec_tlu_ctl.scala 435:68] + node _T_171 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 437:61] + node _T_172 = and(io.dec_tlu_i0_valid_r, _T_171) @[dec_tlu_ctl.scala 437:59] + node _T_173 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 437:90] + node _T_174 = and(_T_172, _T_173) @[dec_tlu_ctl.scala 437:84] + node _T_175 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 437:104] + node dcsr_single_step_done = and(_T_174, _T_175) @[dec_tlu_ctl.scala 437:102] + node _T_176 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 439:66] + node _T_177 = and(debug_resume_req_f, _T_176) @[dec_tlu_ctl.scala 439:60] + node _T_178 = not(dcsr_single_step_done_f) @[dec_tlu_ctl.scala 439:111] + node _T_179 = and(dcsr_single_step_running_f, _T_178) @[dec_tlu_ctl.scala 439:109] + node dcsr_single_step_running = or(_T_177, _T_179) @[dec_tlu_ctl.scala 439:79] + node dbg_cmd_done_ns = and(io.dec_tlu_i0_valid_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 441:53] + node _T_180 = or(trigger_hit_dmode_r, ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 444:57] + node _T_181 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 444:112] + node _T_182 = and(request_debug_mode_r_d1, _T_181) @[dec_tlu_ctl.scala 444:110] + node request_debug_mode_r = or(_T_180, _T_182) @[dec_tlu_ctl.scala 444:83] + node _T_183 = or(request_debug_mode_r_d1, request_debug_mode_done_f) @[dec_tlu_ctl.scala 446:64] + node _T_184 = not(dbg_tlu_halted_f) @[dec_tlu_ctl.scala 446:95] + node request_debug_mode_done = and(_T_183, _T_184) @[dec_tlu_ctl.scala 446:93] + reg _T_185 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 449:81] + _T_185 <= io.tlu_ifc.dec_tlu_flush_noredir_wb @[dec_tlu_ctl.scala 449:81] + dec_tlu_flush_noredir_r_d1 <= _T_185 @[dec_tlu_ctl.scala 449:49] + reg _T_186 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 450:89] + _T_186 <= halt_taken @[dec_tlu_ctl.scala 450:89] + halt_taken_f <= _T_186 @[dec_tlu_ctl.scala 450:57] + reg _T_187 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 451:89] + _T_187 <= io.lsu_idle_any @[dec_tlu_ctl.scala 451:89] + lsu_idle_any_f <= _T_187 @[dec_tlu_ctl.scala 451:57] + reg _T_188 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 452:81] + _T_188 <= io.tlu_mem.ifu_miss_state_idle @[dec_tlu_ctl.scala 452:81] + ifu_miss_state_idle_f <= _T_188 @[dec_tlu_ctl.scala 452:49] + reg _T_189 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 453:89] + _T_189 <= dbg_tlu_halted @[dec_tlu_ctl.scala 453:89] + dbg_tlu_halted_f <= _T_189 @[dec_tlu_ctl.scala 453:57] + reg _T_190 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 454:81] + _T_190 <= resume_ack_ns @[dec_tlu_ctl.scala 454:81] + io.dec_tlu_resume_ack <= _T_190 @[dec_tlu_ctl.scala 454:49] + reg _T_191 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 455:89] + _T_191 <= debug_halt_req_ns @[dec_tlu_ctl.scala 455:89] + debug_halt_req_f <= _T_191 @[dec_tlu_ctl.scala 455:57] + reg _T_192 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 456:89] + _T_192 <= debug_resume_req @[dec_tlu_ctl.scala 456:89] + debug_resume_req_f <= _T_192 @[dec_tlu_ctl.scala 456:57] + reg _T_193 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 457:81] + _T_193 <= trigger_hit_dmode_r @[dec_tlu_ctl.scala 457:81] + trigger_hit_dmode_r_d1 <= _T_193 @[dec_tlu_ctl.scala 457:49] + reg _T_194 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 458:81] + _T_194 <= dcsr_single_step_done @[dec_tlu_ctl.scala 458:81] + dcsr_single_step_done_f <= _T_194 @[dec_tlu_ctl.scala 458:49] + reg _T_195 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 459:89] + _T_195 <= debug_halt_req @[dec_tlu_ctl.scala 459:89] + debug_halt_req_d1 <= _T_195 @[dec_tlu_ctl.scala 459:57] + reg dec_tlu_wr_pause_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 460:81] + dec_tlu_wr_pause_r_d1 <= io.dec_tlu_wr_pause_r @[dec_tlu_ctl.scala 460:81] + reg dec_pause_state_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 461:81] + dec_pause_state_f <= io.dec_pause_state @[dec_tlu_ctl.scala 461:81] + reg _T_196 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 462:81] + _T_196 <= request_debug_mode_r @[dec_tlu_ctl.scala 462:81] + request_debug_mode_r_d1 <= _T_196 @[dec_tlu_ctl.scala 462:49] + reg _T_197 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 463:73] + _T_197 <= request_debug_mode_done @[dec_tlu_ctl.scala 463:73] + request_debug_mode_done_f <= _T_197 @[dec_tlu_ctl.scala 463:41] + reg _T_198 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 464:73] + _T_198 <= dcsr_single_step_running @[dec_tlu_ctl.scala 464:73] + dcsr_single_step_running_f <= _T_198 @[dec_tlu_ctl.scala 464:41] + reg _T_199 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 465:73] + _T_199 <= io.dec_tlu_flush_pause_r @[dec_tlu_ctl.scala 465:73] + dec_tlu_flush_pause_r_d1 <= _T_199 @[dec_tlu_ctl.scala 465:41] + reg _T_200 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 466:81] + _T_200 <= dbg_halt_req_held_ns @[dec_tlu_ctl.scala 466:81] + dbg_halt_req_held <= _T_200 @[dec_tlu_ctl.scala 466:49] + io.dec_tlu_debug_stall <= debug_halt_req_f @[dec_tlu_ctl.scala 469:41] + io.dec_tlu_dbg_halted <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 470:41] + io.dec_tlu_debug_mode <= debug_mode_status @[dec_tlu_ctl.scala 471:41] + dec_tlu_pmu_fw_halted <= pmu_fw_tlu_halted_f @[dec_tlu_ctl.scala 472:41] + node _T_201 = and(fence_i_r, internal_dbg_halt_mode) @[dec_tlu_ctl.scala 475:71] + node _T_202 = or(take_halt, _T_201) @[dec_tlu_ctl.scala 475:58] + node _T_203 = or(_T_202, io.dec_tlu_flush_pause_r) @[dec_tlu_ctl.scala 475:97] + node _T_204 = and(i0_trigger_hit_r, trigger_hit_dmode_r) @[dec_tlu_ctl.scala 475:144] + node _T_205 = or(_T_203, _T_204) @[dec_tlu_ctl.scala 475:124] + node _T_206 = or(_T_205, take_ext_int_start) @[dec_tlu_ctl.scala 475:167] + io.tlu_ifc.dec_tlu_flush_noredir_wb <= _T_206 @[dec_tlu_ctl.scala 475:45] + io.dec_tlu_flush_extint <= take_ext_int_start @[dec_tlu_ctl.scala 477:33] + node _T_207 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 480:61] + node _T_208 = and(dec_tlu_wr_pause_r_d1, _T_207) @[dec_tlu_ctl.scala 480:59] + node _T_209 = not(take_ext_int_start) @[dec_tlu_ctl.scala 480:82] + node _T_210 = and(_T_208, _T_209) @[dec_tlu_ctl.scala 480:80] + io.dec_tlu_flush_pause_r <= _T_210 @[dec_tlu_ctl.scala 480:34] + node _T_211 = not(io.dec_pause_state) @[dec_tlu_ctl.scala 482:28] + node _T_212 = and(_T_211, dec_pause_state_f) @[dec_tlu_ctl.scala 482:48] + node _T_213 = or(ext_int_ready, ce_int_ready) @[dec_tlu_ctl.scala 482:86] + node _T_214 = or(_T_213, timer_int_ready) @[dec_tlu_ctl.scala 482:101] + node _T_215 = or(_T_214, soft_int_ready) @[dec_tlu_ctl.scala 482:119] + node _T_216 = or(_T_215, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 482:136] + node _T_217 = or(_T_216, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 482:160] + node _T_218 = or(_T_217, nmi_int_detected) @[dec_tlu_ctl.scala 482:184] + node _T_219 = or(_T_218, ext_int_freeze_d1) @[dec_tlu_ctl.scala 482:203] + node _T_220 = not(_T_219) @[dec_tlu_ctl.scala 482:70] + node _T_221 = and(_T_212, _T_220) @[dec_tlu_ctl.scala 482:68] + node _T_222 = not(interrupt_valid_r_d1) @[dec_tlu_ctl.scala 482:226] + node _T_223 = and(_T_221, _T_222) @[dec_tlu_ctl.scala 482:224] + node _T_224 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 482:250] + node _T_225 = and(_T_223, _T_224) @[dec_tlu_ctl.scala 482:248] + node _T_226 = not(pmu_fw_halt_req_f) @[dec_tlu_ctl.scala 482:270] + node _T_227 = and(_T_225, _T_226) @[dec_tlu_ctl.scala 482:268] + node _T_228 = not(halt_taken_f) @[dec_tlu_ctl.scala 482:291] + node _T_229 = and(_T_227, _T_228) @[dec_tlu_ctl.scala 482:289] + pause_expired_r <= _T_229 @[dec_tlu_ctl.scala 482:25] + node _T_230 = bits(dcsr, 2, 2) @[dec_tlu_ctl.scala 484:88] + node _T_231 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_230) @[dec_tlu_ctl.scala 484:82] + node _T_232 = or(io.dec_tlu_resume_ack, dcsr_single_step_running) @[dec_tlu_ctl.scala 484:125] + node _T_233 = and(_T_231, _T_232) @[dec_tlu_ctl.scala 484:100] + node _T_234 = not(io.tlu_ifc.dec_tlu_flush_noredir_wb) @[dec_tlu_ctl.scala 484:155] + node _T_235 = and(_T_233, _T_234) @[dec_tlu_ctl.scala 484:153] + io.tlu_bp.dec_tlu_flush_leak_one_wb <= _T_235 @[dec_tlu_ctl.scala 484:45] + node _T_236 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 485:93] + node _T_237 = and(io.tlu_exu.dec_tlu_flush_lower_r, _T_236) @[dec_tlu_ctl.scala 485:77] + io.tlu_mem.dec_tlu_flush_err_wb <= _T_237 @[dec_tlu_ctl.scala 485:41] + io.dec_dbg_cmd_done <= dbg_cmd_done_ns @[dec_tlu_ctl.scala 488:29] + node _T_238 = and(illegal_r, io.dec_dbg_cmd_done) @[dec_tlu_ctl.scala 489:42] + io.dec_dbg_cmd_fail <= _T_238 @[dec_tlu_ctl.scala 489:29] + node _T_239 = bits(mtdata1_t[3], 2, 2) @[dec_tlu_ctl.scala 502:48] + node _T_240 = bits(mtdata1_t[2], 2, 2) @[dec_tlu_ctl.scala 502:75] + node _T_241 = bits(mtdata1_t[1], 2, 2) @[dec_tlu_ctl.scala 502:102] + node _T_242 = bits(mtdata1_t[0], 2, 2) @[dec_tlu_ctl.scala 502:129] node _T_243 = cat(_T_241, _T_242) @[Cat.scala 29:58] node _T_244 = cat(_T_239, _T_240) @[Cat.scala 29:58] node trigger_execute = cat(_T_244, _T_243) @[Cat.scala 29:58] - node _T_245 = bits(mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 507:52] - node _T_246 = bits(mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 507:79] - node _T_247 = bits(mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 507:106] - node _T_248 = bits(mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 507:133] + node _T_245 = bits(mtdata1_t[3], 7, 7) @[dec_tlu_ctl.scala 503:52] + node _T_246 = bits(mtdata1_t[2], 7, 7) @[dec_tlu_ctl.scala 503:79] + node _T_247 = bits(mtdata1_t[1], 7, 7) @[dec_tlu_ctl.scala 503:106] + node _T_248 = bits(mtdata1_t[0], 7, 7) @[dec_tlu_ctl.scala 503:133] node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58] node _T_250 = cat(_T_245, _T_246) @[Cat.scala 29:58] node trigger_data = cat(_T_250, _T_249) @[Cat.scala 29:58] - node _T_251 = bits(mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 508:52] - node _T_252 = bits(mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 508:79] - node _T_253 = bits(mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 508:106] - node _T_254 = bits(mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 508:133] + node _T_251 = bits(mtdata1_t[3], 1, 1) @[dec_tlu_ctl.scala 504:52] + node _T_252 = bits(mtdata1_t[2], 1, 1) @[dec_tlu_ctl.scala 504:79] + node _T_253 = bits(mtdata1_t[1], 1, 1) @[dec_tlu_ctl.scala 504:106] + node _T_254 = bits(mtdata1_t[0], 1, 1) @[dec_tlu_ctl.scala 504:133] node _T_255 = cat(_T_253, _T_254) @[Cat.scala 29:58] node _T_256 = cat(_T_251, _T_252) @[Cat.scala 29:58] node trigger_store = cat(_T_256, _T_255) @[Cat.scala 29:58] - node _T_257 = bits(mtdata1_t[3], 6, 6) @[dec_tlu_ctl.scala 511:45] - node _T_258 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 511:71] - node _T_259 = or(_T_257, _T_258) @[dec_tlu_ctl.scala 511:62] - node _T_260 = bits(mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 511:100] - node _T_261 = and(_T_259, _T_260) @[dec_tlu_ctl.scala 511:86] - node _T_262 = bits(mtdata1_t[2], 6, 6) @[dec_tlu_ctl.scala 511:133] - node _T_263 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 511:159] - node _T_264 = or(_T_262, _T_263) @[dec_tlu_ctl.scala 511:150] - node _T_265 = bits(mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 511:188] - node _T_266 = and(_T_264, _T_265) @[dec_tlu_ctl.scala 511:174] - node _T_267 = bits(mtdata1_t[1], 6, 6) @[dec_tlu_ctl.scala 511:222] - node _T_268 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 511:248] - node _T_269 = or(_T_267, _T_268) @[dec_tlu_ctl.scala 511:239] - node _T_270 = bits(mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 511:277] - node _T_271 = and(_T_269, _T_270) @[dec_tlu_ctl.scala 511:263] - node _T_272 = bits(mtdata1_t[0], 6, 6) @[dec_tlu_ctl.scala 511:311] - node _T_273 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 511:337] - node _T_274 = or(_T_272, _T_273) @[dec_tlu_ctl.scala 511:328] - node _T_275 = bits(mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 511:366] - node _T_276 = and(_T_274, _T_275) @[dec_tlu_ctl.scala 511:352] + node _T_257 = bits(mtdata1_t[3], 6, 6) @[dec_tlu_ctl.scala 507:45] + node _T_258 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 507:71] + node _T_259 = or(_T_257, _T_258) @[dec_tlu_ctl.scala 507:62] + node _T_260 = bits(mtdata1_t[3], 3, 3) @[dec_tlu_ctl.scala 507:100] + node _T_261 = and(_T_259, _T_260) @[dec_tlu_ctl.scala 507:86] + node _T_262 = bits(mtdata1_t[2], 6, 6) @[dec_tlu_ctl.scala 507:133] + node _T_263 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 507:159] + node _T_264 = or(_T_262, _T_263) @[dec_tlu_ctl.scala 507:150] + node _T_265 = bits(mtdata1_t[2], 3, 3) @[dec_tlu_ctl.scala 507:188] + node _T_266 = and(_T_264, _T_265) @[dec_tlu_ctl.scala 507:174] + node _T_267 = bits(mtdata1_t[1], 6, 6) @[dec_tlu_ctl.scala 507:222] + node _T_268 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 507:248] + node _T_269 = or(_T_267, _T_268) @[dec_tlu_ctl.scala 507:239] + node _T_270 = bits(mtdata1_t[1], 3, 3) @[dec_tlu_ctl.scala 507:277] + node _T_271 = and(_T_269, _T_270) @[dec_tlu_ctl.scala 507:263] + node _T_272 = bits(mtdata1_t[0], 6, 6) @[dec_tlu_ctl.scala 507:311] + node _T_273 = bits(mstatus, 0, 0) @[dec_tlu_ctl.scala 507:337] + node _T_274 = or(_T_272, _T_273) @[dec_tlu_ctl.scala 507:328] + node _T_275 = bits(mtdata1_t[0], 3, 3) @[dec_tlu_ctl.scala 507:366] + node _T_276 = and(_T_274, _T_275) @[dec_tlu_ctl.scala 507:352] node _T_277 = cat(_T_271, _T_276) @[Cat.scala 29:58] node _T_278 = cat(_T_261, _T_266) @[Cat.scala 29:58] node trigger_enabled = cat(_T_278, _T_277) @[Cat.scala 29:58] - node _T_279 = and(trigger_execute, trigger_data) @[dec_tlu_ctl.scala 514:57] + node _T_279 = and(trigger_execute, trigger_data) @[dec_tlu_ctl.scala 510:57] node _T_280 = bits(inst_acc_r_raw, 0, 0) @[Bitwise.scala 72:15] node _T_281 = mux(_T_280, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_282 = and(_T_279, _T_281) @[dec_tlu_ctl.scala 514:72] - node _T_283 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 514:137] + node _T_282 = and(_T_279, _T_281) @[dec_tlu_ctl.scala 510:72] + node _T_283 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 510:137] node _T_284 = bits(_T_283, 0, 0) @[Bitwise.scala 72:15] node _T_285 = mux(_T_284, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_286 = or(_T_282, _T_285) @[dec_tlu_ctl.scala 514:98] - node i0_iside_trigger_has_pri_r = not(_T_286) @[dec_tlu_ctl.scala 514:38] - node _T_287 = and(trigger_store, trigger_data) @[dec_tlu_ctl.scala 517:51] + node _T_286 = or(_T_282, _T_285) @[dec_tlu_ctl.scala 510:98] + node i0_iside_trigger_has_pri_r = not(_T_286) @[dec_tlu_ctl.scala 510:38] + node _T_287 = and(trigger_store, trigger_data) @[dec_tlu_ctl.scala 513:51] node _T_288 = bits(lsu_i0_exc_r_raw, 0, 0) @[Bitwise.scala 72:15] node _T_289 = mux(_T_288, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_290 = and(_T_287, _T_289) @[dec_tlu_ctl.scala 517:66] - node i0_lsu_trigger_has_pri_r = not(_T_290) @[dec_tlu_ctl.scala 517:35] + node _T_290 = and(_T_287, _T_289) @[dec_tlu_ctl.scala 513:66] + node i0_lsu_trigger_has_pri_r = not(_T_290) @[dec_tlu_ctl.scala 513:35] node _T_291 = bits(io.dec_tlu_i0_valid_r, 0, 0) @[Bitwise.scala 72:15] node _T_292 = mux(_T_291, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_293 = bits(io.dec_tlu_packet_r.i0trigger, 3, 0) @[dec_tlu_ctl.scala 522:84] - node _T_294 = and(_T_292, _T_293) @[dec_tlu_ctl.scala 522:53] - node _T_295 = and(_T_294, i0_iside_trigger_has_pri_r) @[dec_tlu_ctl.scala 522:90] - node _T_296 = and(_T_295, i0_lsu_trigger_has_pri_r) @[dec_tlu_ctl.scala 522:119] - node i0trigger_qual_r = and(_T_296, trigger_enabled) @[dec_tlu_ctl.scala 522:146] - node _T_297 = or(io.tlu_bp.dec_tlu_flush_lower_wb, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 524:65] + node _T_293 = bits(io.dec_tlu_packet_r.i0trigger, 3, 0) @[dec_tlu_ctl.scala 518:84] + node _T_294 = and(_T_292, _T_293) @[dec_tlu_ctl.scala 518:53] + node _T_295 = and(_T_294, i0_iside_trigger_has_pri_r) @[dec_tlu_ctl.scala 518:90] + node _T_296 = and(_T_295, i0_lsu_trigger_has_pri_r) @[dec_tlu_ctl.scala 518:119] + node i0trigger_qual_r = and(_T_296, trigger_enabled) @[dec_tlu_ctl.scala 518:146] + node _T_297 = or(io.dec_tlu_flush_lower_wb, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 520:58] node _T_298 = bits(_T_297, 0, 0) @[Bitwise.scala 72:15] node _T_299 = mux(_T_298, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_300 = not(_T_299) @[dec_tlu_ctl.scala 524:23] - node i0_trigger_r = and(_T_300, i0trigger_qual_r) @[dec_tlu_ctl.scala 524:91] - node _T_301 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 527:53] - node _T_302 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 527:73] - node _T_303 = not(_T_302) @[dec_tlu_ctl.scala 527:60] - node _T_304 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 527:103] - node _T_305 = or(_T_303, _T_304) @[dec_tlu_ctl.scala 527:89] - node _T_306 = and(_T_301, _T_305) @[dec_tlu_ctl.scala 527:57] - node _T_307 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 527:121] - node _T_308 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 527:141] - node _T_309 = not(_T_308) @[dec_tlu_ctl.scala 527:128] - node _T_310 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 527:171] - node _T_311 = or(_T_309, _T_310) @[dec_tlu_ctl.scala 527:157] - node _T_312 = and(_T_307, _T_311) @[dec_tlu_ctl.scala 527:125] - node _T_313 = bits(i0_trigger_r, 1, 1) @[dec_tlu_ctl.scala 527:189] - node _T_314 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 527:209] - node _T_315 = not(_T_314) @[dec_tlu_ctl.scala 527:196] - node _T_316 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 527:239] - node _T_317 = or(_T_315, _T_316) @[dec_tlu_ctl.scala 527:225] - node _T_318 = and(_T_313, _T_317) @[dec_tlu_ctl.scala 527:193] - node _T_319 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 527:257] - node _T_320 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 527:277] - node _T_321 = not(_T_320) @[dec_tlu_ctl.scala 527:264] - node _T_322 = bits(i0_trigger_r, 1, 1) @[dec_tlu_ctl.scala 527:307] - node _T_323 = or(_T_321, _T_322) @[dec_tlu_ctl.scala 527:293] - node _T_324 = and(_T_319, _T_323) @[dec_tlu_ctl.scala 527:261] + node _T_300 = not(_T_299) @[dec_tlu_ctl.scala 520:23] + node i0_trigger_r = and(_T_300, i0trigger_qual_r) @[dec_tlu_ctl.scala 520:84] + node _T_301 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 523:53] + node _T_302 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 523:73] + node _T_303 = not(_T_302) @[dec_tlu_ctl.scala 523:60] + node _T_304 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 523:103] + node _T_305 = or(_T_303, _T_304) @[dec_tlu_ctl.scala 523:89] + node _T_306 = and(_T_301, _T_305) @[dec_tlu_ctl.scala 523:57] + node _T_307 = bits(i0_trigger_r, 2, 2) @[dec_tlu_ctl.scala 523:121] + node _T_308 = bits(mtdata1_t[2], 5, 5) @[dec_tlu_ctl.scala 523:141] + node _T_309 = not(_T_308) @[dec_tlu_ctl.scala 523:128] + node _T_310 = bits(i0_trigger_r, 3, 3) @[dec_tlu_ctl.scala 523:171] + node _T_311 = or(_T_309, _T_310) @[dec_tlu_ctl.scala 523:157] + node _T_312 = and(_T_307, _T_311) @[dec_tlu_ctl.scala 523:125] + node _T_313 = bits(i0_trigger_r, 1, 1) @[dec_tlu_ctl.scala 523:189] + node _T_314 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 523:209] + node _T_315 = not(_T_314) @[dec_tlu_ctl.scala 523:196] + node _T_316 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 523:239] + node _T_317 = or(_T_315, _T_316) @[dec_tlu_ctl.scala 523:225] + node _T_318 = and(_T_313, _T_317) @[dec_tlu_ctl.scala 523:193] + node _T_319 = bits(i0_trigger_r, 0, 0) @[dec_tlu_ctl.scala 523:257] + node _T_320 = bits(mtdata1_t[0], 5, 5) @[dec_tlu_ctl.scala 523:277] + node _T_321 = not(_T_320) @[dec_tlu_ctl.scala 523:264] + node _T_322 = bits(i0_trigger_r, 1, 1) @[dec_tlu_ctl.scala 523:307] + node _T_323 = or(_T_321, _T_322) @[dec_tlu_ctl.scala 523:293] + node _T_324 = and(_T_319, _T_323) @[dec_tlu_ctl.scala 523:261] node _T_325 = cat(_T_318, _T_324) @[Cat.scala 29:58] node _T_326 = cat(_T_306, _T_312) @[Cat.scala 29:58] node i0_trigger_chain_masked_r = cat(_T_326, _T_325) @[Cat.scala 29:58] - node i0_trigger_hit_raw_r = orr(i0_trigger_chain_masked_r) @[dec_tlu_ctl.scala 530:57] - i0_trigger_hit_r <= i0_trigger_hit_raw_r @[dec_tlu_ctl.scala 532:25] - node _T_327 = bits(mtdata1_t[3], 6, 6) @[dec_tlu_ctl.scala 536:44] - node _T_328 = bits(mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 536:75] - node _T_329 = and(_T_327, _T_328) @[dec_tlu_ctl.scala 536:61] - node _T_330 = bits(mtdata1_t[2], 6, 6) @[dec_tlu_ctl.scala 536:104] - node _T_331 = bits(mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 536:135] - node _T_332 = and(_T_330, _T_331) @[dec_tlu_ctl.scala 536:121] - node _T_333 = bits(mtdata1_t[1], 6, 6) @[dec_tlu_ctl.scala 536:164] - node _T_334 = bits(mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 536:195] - node _T_335 = and(_T_333, _T_334) @[dec_tlu_ctl.scala 536:181] - node _T_336 = bits(mtdata1_t[0], 6, 6) @[dec_tlu_ctl.scala 536:224] - node _T_337 = bits(mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 536:255] - node _T_338 = and(_T_336, _T_337) @[dec_tlu_ctl.scala 536:241] + node i0_trigger_hit_raw_r = orr(i0_trigger_chain_masked_r) @[dec_tlu_ctl.scala 526:57] + i0_trigger_hit_r <= i0_trigger_hit_raw_r @[dec_tlu_ctl.scala 528:25] + node _T_327 = bits(mtdata1_t[3], 6, 6) @[dec_tlu_ctl.scala 532:44] + node _T_328 = bits(mtdata1_t[3], 9, 9) @[dec_tlu_ctl.scala 532:75] + node _T_329 = and(_T_327, _T_328) @[dec_tlu_ctl.scala 532:61] + node _T_330 = bits(mtdata1_t[2], 6, 6) @[dec_tlu_ctl.scala 532:104] + node _T_331 = bits(mtdata1_t[2], 9, 9) @[dec_tlu_ctl.scala 532:135] + node _T_332 = and(_T_330, _T_331) @[dec_tlu_ctl.scala 532:121] + node _T_333 = bits(mtdata1_t[1], 6, 6) @[dec_tlu_ctl.scala 532:164] + node _T_334 = bits(mtdata1_t[1], 9, 9) @[dec_tlu_ctl.scala 532:195] + node _T_335 = and(_T_333, _T_334) @[dec_tlu_ctl.scala 532:181] + node _T_336 = bits(mtdata1_t[0], 6, 6) @[dec_tlu_ctl.scala 532:224] + node _T_337 = bits(mtdata1_t[0], 9, 9) @[dec_tlu_ctl.scala 532:255] + node _T_338 = and(_T_336, _T_337) @[dec_tlu_ctl.scala 532:241] node _T_339 = cat(_T_335, _T_338) @[Cat.scala 29:58] node _T_340 = cat(_T_329, _T_332) @[Cat.scala 29:58] node trigger_action = cat(_T_340, _T_339) @[Cat.scala 29:58] node _T_341 = bits(i0_trigger_hit_r, 0, 0) @[Bitwise.scala 72:15] node _T_342 = mux(_T_341, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node update_hit_bit_r = and(_T_342, i0_trigger_chain_masked_r) @[dec_tlu_ctl.scala 539:56] - node _T_343 = and(i0_trigger_chain_masked_r, trigger_action) @[dec_tlu_ctl.scala 542:57] - node i0_trigger_action_r = orr(_T_343) @[dec_tlu_ctl.scala 542:75] - node _T_344 = and(i0_trigger_hit_r, i0_trigger_action_r) @[dec_tlu_ctl.scala 544:45] - trigger_hit_dmode_r <= _T_344 @[dec_tlu_ctl.scala 544:24] - node _T_345 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 546:55] - node mepc_trigger_hit_sel_pc_r = and(i0_trigger_hit_r, _T_345) @[dec_tlu_ctl.scala 546:53] - node _T_346 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 573:62] - node _T_347 = and(i_cpu_halt_req_sync, _T_346) @[dec_tlu_ctl.scala 573:60] - node _T_348 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 573:87] - node i_cpu_halt_req_sync_qual = and(_T_347, _T_348) @[dec_tlu_ctl.scala 573:85] - node _T_349 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 574:60] - node _T_350 = and(i_cpu_run_req_sync, _T_349) @[dec_tlu_ctl.scala 574:58] - node _T_351 = and(_T_350, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 574:83] - node _T_352 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 574:107] - node i_cpu_run_req_sync_qual = and(_T_351, _T_352) @[dec_tlu_ctl.scala 574:105] - reg i_cpu_halt_req_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 576:80] - i_cpu_halt_req_d1 <= i_cpu_halt_req_sync_qual @[dec_tlu_ctl.scala 576:80] - reg i_cpu_run_req_d1_raw : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 577:80] - i_cpu_run_req_d1_raw <= i_cpu_run_req_sync_qual @[dec_tlu_ctl.scala 577:80] - reg _T_353 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 578:81] - _T_353 <= cpu_halt_status @[dec_tlu_ctl.scala 578:81] - io.o_cpu_halt_status <= _T_353 @[dec_tlu_ctl.scala 578:49] - reg _T_354 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 579:81] - _T_354 <= cpu_halt_ack @[dec_tlu_ctl.scala 579:81] - io.o_cpu_halt_ack <= _T_354 @[dec_tlu_ctl.scala 579:49] - reg _T_355 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 580:81] - _T_355 <= cpu_run_ack @[dec_tlu_ctl.scala 580:81] - io.o_cpu_run_ack <= _T_355 @[dec_tlu_ctl.scala 580:49] - reg internal_pmu_fw_halt_mode_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 581:68] - internal_pmu_fw_halt_mode_f <= internal_pmu_fw_halt_mode @[dec_tlu_ctl.scala 581:68] - reg _T_356 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 582:73] - _T_356 <= pmu_fw_halt_req_ns @[dec_tlu_ctl.scala 582:73] - pmu_fw_halt_req_f <= _T_356 @[dec_tlu_ctl.scala 582:41] - reg _T_357 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 583:73] - _T_357 <= pmu_fw_tlu_halted @[dec_tlu_ctl.scala 583:73] - pmu_fw_tlu_halted_f <= _T_357 @[dec_tlu_ctl.scala 583:41] - reg _T_358 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 584:73] - _T_358 <= int_timer0_int_hold @[dec_tlu_ctl.scala 584:73] - int_timer0_int_hold_f <= _T_358 @[dec_tlu_ctl.scala 584:41] - reg _T_359 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 585:73] - _T_359 <= int_timer1_int_hold @[dec_tlu_ctl.scala 585:73] - int_timer1_int_hold_f <= _T_359 @[dec_tlu_ctl.scala 585:41] - node _T_360 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 589:52] - node ext_halt_pulse = and(i_cpu_halt_req_sync_qual, _T_360) @[dec_tlu_ctl.scala 589:50] - node enter_pmu_fw_halt_req = or(ext_halt_pulse, fw_halt_req) @[dec_tlu_ctl.scala 590:48] - node _T_361 = not(pmu_fw_tlu_halted) @[dec_tlu_ctl.scala 591:72] - node _T_362 = and(pmu_fw_halt_req_f, _T_361) @[dec_tlu_ctl.scala 591:70] - node _T_363 = or(enter_pmu_fw_halt_req, _T_362) @[dec_tlu_ctl.scala 591:49] - node _T_364 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 591:95] - node _T_365 = and(_T_363, _T_364) @[dec_tlu_ctl.scala 591:93] - pmu_fw_halt_req_ns <= _T_365 @[dec_tlu_ctl.scala 591:23] - node _T_366 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 592:85] - node _T_367 = and(internal_pmu_fw_halt_mode_f, _T_366) @[dec_tlu_ctl.scala 592:83] - node _T_368 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 592:105] - node _T_369 = and(_T_367, _T_368) @[dec_tlu_ctl.scala 592:103] - node _T_370 = or(pmu_fw_halt_req_ns, _T_369) @[dec_tlu_ctl.scala 592:52] - internal_pmu_fw_halt_mode <= _T_370 @[dec_tlu_ctl.scala 592:30] - node _T_371 = and(pmu_fw_halt_req_f, core_empty) @[dec_tlu_ctl.scala 595:45] - node _T_372 = and(_T_371, halt_taken) @[dec_tlu_ctl.scala 595:58] - node _T_373 = not(enter_debug_halt_req) @[dec_tlu_ctl.scala 595:73] - node _T_374 = and(_T_372, _T_373) @[dec_tlu_ctl.scala 595:71] - node _T_375 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 595:121] - node _T_376 = and(pmu_fw_tlu_halted_f, _T_375) @[dec_tlu_ctl.scala 595:119] - node _T_377 = or(_T_374, _T_376) @[dec_tlu_ctl.scala 595:96] - node _T_378 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 595:143] - node _T_379 = and(_T_377, _T_378) @[dec_tlu_ctl.scala 595:141] - pmu_fw_tlu_halted <= _T_379 @[dec_tlu_ctl.scala 595:22] - node _T_380 = and(i_cpu_halt_req_d1, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 597:38] - cpu_halt_ack <= _T_380 @[dec_tlu_ctl.scala 597:17] - node _T_381 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 598:46] - node _T_382 = and(pmu_fw_tlu_halted_f, _T_381) @[dec_tlu_ctl.scala 598:44] - node _T_383 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 598:91] - node _T_384 = and(io.o_cpu_halt_status, _T_383) @[dec_tlu_ctl.scala 598:89] - node _T_385 = not(debug_mode_status) @[dec_tlu_ctl.scala 598:111] - node _T_386 = and(_T_384, _T_385) @[dec_tlu_ctl.scala 598:109] - node _T_387 = or(_T_382, _T_386) @[dec_tlu_ctl.scala 598:65] - cpu_halt_status <= _T_387 @[dec_tlu_ctl.scala 598:20] - node _T_388 = and(io.o_cpu_halt_status, i_cpu_run_req_sync_qual) @[dec_tlu_ctl.scala 599:41] - node _T_389 = and(io.o_cpu_run_ack, i_cpu_run_req_sync_qual) @[dec_tlu_ctl.scala 599:88] - node _T_390 = or(_T_388, _T_389) @[dec_tlu_ctl.scala 599:68] - cpu_run_ack <= _T_390 @[dec_tlu_ctl.scala 599:16] - io.o_debug_mode_status <= debug_mode_status @[dec_tlu_ctl.scala 601:27] - node _T_391 = or(nmi_int_detected, timer_int_ready) @[dec_tlu_ctl.scala 604:66] - node _T_392 = or(_T_391, soft_int_ready) @[dec_tlu_ctl.scala 604:84] - node _T_393 = or(_T_392, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 604:101] - node _T_394 = or(_T_393, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 604:125] - node _T_395 = and(io.mhwakeup, mhwakeup_ready) @[dec_tlu_ctl.scala 604:164] - node _T_396 = or(_T_394, _T_395) @[dec_tlu_ctl.scala 604:149] - node _T_397 = and(_T_396, io.o_cpu_halt_status) @[dec_tlu_ctl.scala 604:183] - node _T_398 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 604:208] - node _T_399 = and(_T_397, _T_398) @[dec_tlu_ctl.scala 604:206] - node _T_400 = or(i_cpu_run_req_d1_raw, _T_399) @[dec_tlu_ctl.scala 604:45] - i_cpu_run_req_d1 <= _T_400 @[dec_tlu_ctl.scala 604:21] - reg _T_401 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 610:89] - _T_401 <= mdseac_locked_ns @[dec_tlu_ctl.scala 610:89] - mdseac_locked_f <= _T_401 @[dec_tlu_ctl.scala 610:57] - reg lsu_single_ecc_error_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 611:72] - lsu_single_ecc_error_r_d1 <= io.lsu_single_ecc_error_incr @[dec_tlu_ctl.scala 611:72] - node _T_402 = not(io.tlu_bp.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 613:57] - node lsu_exc_valid_r_raw = and(io.lsu_error_pkt_r.valid, _T_402) @[dec_tlu_ctl.scala 613:55] - lsu_i0_exc_r_raw <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 614:21] - node _T_403 = and(lsu_i0_exc_r_raw, lsu_exc_valid_r_raw) @[dec_tlu_ctl.scala 615:40] - node _T_404 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 615:64] - node _T_405 = and(_T_403, _T_404) @[dec_tlu_ctl.scala 615:62] - node _T_406 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 615:84] - node lsu_exc_valid_r = and(_T_405, _T_406) @[dec_tlu_ctl.scala 615:82] - reg _T_407 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 617:74] - _T_407 <= lsu_exc_valid_r @[dec_tlu_ctl.scala 617:74] - lsu_exc_valid_r_d1 <= _T_407 @[dec_tlu_ctl.scala 617:41] - reg lsu_i0_exc_r_d1 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 618:73] - lsu_i0_exc_r_d1 <= lsu_exc_valid_r @[dec_tlu_ctl.scala 618:73] - node _T_408 = not(io.lsu_error_pkt_r.bits.exc_type) @[dec_tlu_ctl.scala 619:40] - node lsu_exc_ma_r = and(lsu_exc_valid_r, _T_408) @[dec_tlu_ctl.scala 619:38] - node lsu_exc_acc_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.exc_type) @[dec_tlu_ctl.scala 620:38] - node lsu_exc_st_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 621:38] - node _T_409 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 625:49] - node _T_410 = and(io.dec_tlu_i0_valid_r, _T_409) @[dec_tlu_ctl.scala 625:47] - node _T_411 = not(io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 625:70] - node _T_412 = and(_T_411, io.lsu_error_pkt_r.bits.single_ecc_error) @[dec_tlu_ctl.scala 625:105] - node lsu_i0_rfnpc_r = and(_T_410, _T_412) @[dec_tlu_ctl.scala 625:67] - node _T_413 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 628:52] - node _T_414 = and(io.dec_tlu_i0_valid_r, _T_413) @[dec_tlu_ctl.scala 628:50] - node _T_415 = not(lsu_exc_valid_r) @[dec_tlu_ctl.scala 628:65] - node _T_416 = and(_T_414, _T_415) @[dec_tlu_ctl.scala 628:63] - node _T_417 = not(inst_acc_r) @[dec_tlu_ctl.scala 628:82] - node _T_418 = and(_T_416, _T_417) @[dec_tlu_ctl.scala 628:79] - node _T_419 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 628:96] - node _T_420 = and(_T_418, _T_419) @[dec_tlu_ctl.scala 628:94] - node _T_421 = not(request_debug_mode_r_d1) @[dec_tlu_ctl.scala 628:121] - node _T_422 = and(_T_420, _T_421) @[dec_tlu_ctl.scala 628:119] - node _T_423 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 628:148] - node tlu_i0_commit_cmt = and(_T_422, _T_423) @[dec_tlu_ctl.scala 628:146] - node _T_424 = or(rfpc_i0_r, lsu_exc_valid_r) @[dec_tlu_ctl.scala 631:38] - node _T_425 = or(_T_424, inst_acc_r) @[dec_tlu_ctl.scala 631:53] - node _T_426 = and(illegal_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 631:79] - node _T_427 = or(_T_425, _T_426) @[dec_tlu_ctl.scala 631:66] - node _T_428 = or(_T_427, i0_trigger_hit_r) @[dec_tlu_ctl.scala 631:104] - tlu_i0_kill_writeb_r <= _T_428 @[dec_tlu_ctl.scala 631:25] - io.tlu_mem.dec_tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 632:37] - node _T_429 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 637:44] - node _T_430 = and(io.dec_tlu_i0_valid_r, _T_429) @[dec_tlu_ctl.scala 637:42] - node _T_431 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 637:98] - node _T_432 = and(_T_430, _T_431) @[dec_tlu_ctl.scala 637:66] - node _T_433 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 637:154] - node _T_434 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 637:175] - node _T_435 = and(_T_433, _T_434) @[dec_tlu_ctl.scala 637:173] - node _T_436 = or(_T_432, _T_435) @[dec_tlu_ctl.scala 637:137] - node _T_437 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 637:199] - node _T_438 = and(_T_436, _T_437) @[dec_tlu_ctl.scala 637:196] - node _T_439 = not(lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 637:220] - node _T_440 = and(_T_438, _T_439) @[dec_tlu_ctl.scala 637:217] - rfpc_i0_r <= _T_440 @[dec_tlu_ctl.scala 637:14] - node _T_441 = not(io.tlu_exu.dec_tlu_flush_lower_r) @[dec_tlu_ctl.scala 640:70] - node _T_442 = and(iccm_repair_state_d1, _T_441) @[dec_tlu_ctl.scala 640:68] - node _T_443 = or(iccm_sbecc_r_d1, _T_442) @[dec_tlu_ctl.scala 640:44] - iccm_repair_state_ns <= _T_443 @[dec_tlu_ctl.scala 640:25] - node _T_444 = and(tlu_i0_commit_cmt, iccm_repair_state_d1) @[dec_tlu_ctl.scala 646:52] - node _T_445 = or(ebreak_r, ecall_r) @[dec_tlu_ctl.scala 646:88] - node _T_446 = or(_T_445, mret_r) @[dec_tlu_ctl.scala 646:98] - node _T_447 = or(_T_446, take_reset) @[dec_tlu_ctl.scala 646:107] - node _T_448 = or(_T_447, illegal_r) @[dec_tlu_ctl.scala 646:120] - node _T_449 = eq(io.dec_csr_wraddr_r, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 646:176] - node _T_450 = and(dec_csr_wen_r_mod, _T_449) @[dec_tlu_ctl.scala 646:153] - node _T_451 = or(_T_448, _T_450) @[dec_tlu_ctl.scala 646:132] - node _T_452 = not(_T_451) @[dec_tlu_ctl.scala 646:77] - node iccm_repair_state_rfnpc = and(_T_444, _T_452) @[dec_tlu_ctl.scala 646:75] - node _T_453 = and(io.tlu_exu.exu_i0_br_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 649:59] - node _T_454 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 649:85] - node dec_tlu_br0_error_r = and(_T_453, _T_454) @[dec_tlu_ctl.scala 649:83] - node _T_455 = and(io.tlu_exu.exu_i0_br_start_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 650:71] - node _T_456 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 650:97] - node dec_tlu_br0_start_error_r = and(_T_455, _T_456) @[dec_tlu_ctl.scala 650:95] - node _T_457 = and(io.tlu_exu.exu_i0_br_valid_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 651:55] - node _T_458 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 651:81] - node _T_459 = and(_T_457, _T_458) @[dec_tlu_ctl.scala 651:79] - node _T_460 = not(io.tlu_exu.exu_i0_br_mp_r) @[dec_tlu_ctl.scala 651:106] - node _T_461 = not(io.tlu_exu.exu_pmu_i0_br_ataken) @[dec_tlu_ctl.scala 651:135] - node _T_462 = or(_T_460, _T_461) @[dec_tlu_ctl.scala 651:133] - node dec_tlu_br0_v_r = and(_T_459, _T_462) @[dec_tlu_ctl.scala 651:103] - io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist <= io.tlu_exu.exu_i0_br_hist_r @[dec_tlu_ctl.scala 654:65] - io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 655:57] - io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 656:57] - io.tlu_bp.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[dec_tlu_ctl.scala 657:57] - io.tlu_bp.dec_tlu_br0_r_pkt.bits.way <= io.exu_i0_br_way_r @[dec_tlu_ctl.scala 658:65] - io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle <= io.tlu_exu.exu_i0_br_middle_r @[dec_tlu_ctl.scala 659:65] - node _T_463 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 662:51] - node _T_464 = and(_T_463, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 662:64] - node _T_465 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 662:90] - node _T_466 = and(_T_464, _T_465) @[dec_tlu_ctl.scala 662:88] - node _T_467 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 662:115] - node _T_468 = not(_T_467) @[dec_tlu_ctl.scala 662:110] - node _T_469 = and(_T_466, _T_468) @[dec_tlu_ctl.scala 662:108] - node _T_470 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 662:132] - node _T_471 = and(_T_469, _T_470) @[dec_tlu_ctl.scala 662:130] - ebreak_r <= _T_471 @[dec_tlu_ctl.scala 662:13] - node _T_472 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h09")) @[dec_tlu_ctl.scala 663:51] - node _T_473 = and(_T_472, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 663:64] - node _T_474 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 663:90] - node _T_475 = and(_T_473, _T_474) @[dec_tlu_ctl.scala 663:88] - node _T_476 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 663:110] - node _T_477 = and(_T_475, _T_476) @[dec_tlu_ctl.scala 663:108] - ecall_r <= _T_477 @[dec_tlu_ctl.scala 663:13] - node _T_478 = not(io.dec_tlu_packet_r.legal) @[dec_tlu_ctl.scala 664:17] - node _T_479 = and(_T_478, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 664:46] - node _T_480 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 664:72] - node _T_481 = and(_T_479, _T_480) @[dec_tlu_ctl.scala 664:70] - node _T_482 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 664:92] - node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 664:90] - illegal_r <= _T_483 @[dec_tlu_ctl.scala 664:13] - node _T_484 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h0c")) @[dec_tlu_ctl.scala 665:51] - node _T_485 = and(_T_484, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 665:64] - node _T_486 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 665:90] - node _T_487 = and(_T_485, _T_486) @[dec_tlu_ctl.scala 665:88] - node _T_488 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 665:110] - node _T_489 = and(_T_487, _T_488) @[dec_tlu_ctl.scala 665:108] - mret_r <= _T_489 @[dec_tlu_ctl.scala 665:13] - node _T_490 = and(io.dec_tlu_packet_r.fence_i, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 667:50] - node _T_491 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 667:76] - node _T_492 = and(_T_490, _T_491) @[dec_tlu_ctl.scala 667:74] - node _T_493 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 667:97] - node _T_494 = and(_T_492, _T_493) @[dec_tlu_ctl.scala 667:95] - fence_i_r <= _T_494 @[dec_tlu_ctl.scala 667:17] - node _T_495 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 668:53] - node _T_496 = and(io.tlu_mem.ifu_ic_error_start, _T_495) @[dec_tlu_ctl.scala 668:51] - node _T_497 = not(debug_mode_status) @[dec_tlu_ctl.scala 668:75] - node _T_498 = or(_T_497, dcsr_single_step_running) @[dec_tlu_ctl.scala 668:101] - node _T_499 = and(_T_496, _T_498) @[dec_tlu_ctl.scala 668:72] - node _T_500 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 668:131] - node _T_501 = and(_T_499, _T_500) @[dec_tlu_ctl.scala 668:129] - ic_perr_r <= _T_501 @[dec_tlu_ctl.scala 668:17] - node _T_502 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 669:61] - node _T_503 = and(io.tlu_mem.ifu_iccm_rd_ecc_single_err, _T_502) @[dec_tlu_ctl.scala 669:59] - node _T_504 = not(debug_mode_status) @[dec_tlu_ctl.scala 669:83] - node _T_505 = or(_T_504, dcsr_single_step_running) @[dec_tlu_ctl.scala 669:109] - node _T_506 = and(_T_503, _T_505) @[dec_tlu_ctl.scala 669:80] - node _T_507 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 669:139] - node _T_508 = and(_T_506, _T_507) @[dec_tlu_ctl.scala 669:137] - iccm_sbecc_r <= _T_508 @[dec_tlu_ctl.scala 669:17] - node _T_509 = and(io.dec_tlu_packet_r.icaf, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 670:49] - inst_acc_r_raw <= _T_509 @[dec_tlu_ctl.scala 670:20] - node _T_510 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 671:35] - node _T_511 = and(inst_acc_r_raw, _T_510) @[dec_tlu_ctl.scala 671:33] - node _T_512 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 671:48] - node _T_513 = and(_T_511, _T_512) @[dec_tlu_ctl.scala 671:46] - inst_acc_r <= _T_513 @[dec_tlu_ctl.scala 671:15] - node _T_514 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 674:64] - node _T_515 = and(_T_514, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 674:77] - node _T_516 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 674:103] - node _T_517 = and(_T_515, _T_516) @[dec_tlu_ctl.scala 674:101] - node _T_518 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 674:127] - node _T_519 = and(_T_517, _T_518) @[dec_tlu_ctl.scala 674:121] - node _T_520 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 674:144] - node _T_521 = and(_T_519, _T_520) @[dec_tlu_ctl.scala 674:142] - ebreak_to_debug_mode_r <= _T_521 @[dec_tlu_ctl.scala 674:27] - reg _T_522 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 676:64] - _T_522 <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 676:64] - ebreak_to_debug_mode_r_d1 <= _T_522 @[dec_tlu_ctl.scala 676:34] - io.tlu_mem.dec_tlu_fence_i_wb <= fence_i_r @[dec_tlu_ctl.scala 677:39] - node _T_523 = or(ebreak_r, ecall_r) @[dec_tlu_ctl.scala 690:41] - node _T_524 = or(_T_523, illegal_r) @[dec_tlu_ctl.scala 690:51] - node _T_525 = or(_T_524, inst_acc_r) @[dec_tlu_ctl.scala 690:63] - node _T_526 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 690:79] - node _T_527 = and(_T_525, _T_526) @[dec_tlu_ctl.scala 690:77] - node _T_528 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 690:92] - node i0_exception_valid_r = and(_T_527, _T_528) @[dec_tlu_ctl.scala 690:90] - node _T_529 = not(take_nmi) @[dec_tlu_ctl.scala 699:33] - node _T_530 = and(take_ext_int, _T_529) @[dec_tlu_ctl.scala 699:31] - node _T_531 = bits(_T_530, 0, 0) @[dec_tlu_ctl.scala 699:44] - node _T_532 = not(take_nmi) @[dec_tlu_ctl.scala 700:27] - node _T_533 = and(take_timer_int, _T_532) @[dec_tlu_ctl.scala 700:25] - node _T_534 = bits(_T_533, 0, 0) @[dec_tlu_ctl.scala 700:38] - node _T_535 = not(take_nmi) @[dec_tlu_ctl.scala 701:26] - node _T_536 = and(take_soft_int, _T_535) @[dec_tlu_ctl.scala 701:24] - node _T_537 = bits(_T_536, 0, 0) @[dec_tlu_ctl.scala 701:37] - node _T_538 = not(take_nmi) @[dec_tlu_ctl.scala 702:32] - node _T_539 = and(take_int_timer0_int, _T_538) @[dec_tlu_ctl.scala 702:30] - node _T_540 = bits(_T_539, 0, 0) @[dec_tlu_ctl.scala 702:43] - node _T_541 = not(take_nmi) @[dec_tlu_ctl.scala 703:32] - node _T_542 = and(take_int_timer1_int, _T_541) @[dec_tlu_ctl.scala 703:30] - node _T_543 = bits(_T_542, 0, 0) @[dec_tlu_ctl.scala 703:43] - node _T_544 = not(take_nmi) @[dec_tlu_ctl.scala 704:24] - node _T_545 = and(take_ce_int, _T_544) @[dec_tlu_ctl.scala 704:22] - node _T_546 = bits(_T_545, 0, 0) @[dec_tlu_ctl.scala 704:35] - node _T_547 = not(take_nmi) @[dec_tlu_ctl.scala 705:22] - node _T_548 = and(illegal_r, _T_547) @[dec_tlu_ctl.scala 705:20] - node _T_549 = bits(_T_548, 0, 0) @[dec_tlu_ctl.scala 705:33] - node _T_550 = not(take_nmi) @[dec_tlu_ctl.scala 706:21] - node _T_551 = and(ecall_r, _T_550) @[dec_tlu_ctl.scala 706:19] - node _T_552 = bits(_T_551, 0, 0) @[dec_tlu_ctl.scala 706:32] - node _T_553 = not(take_nmi) @[dec_tlu_ctl.scala 707:24] - node _T_554 = and(inst_acc_r, _T_553) @[dec_tlu_ctl.scala 707:22] - node _T_555 = bits(_T_554, 0, 0) @[dec_tlu_ctl.scala 707:35] - node _T_556 = or(ebreak_r, i0_trigger_hit_r) @[dec_tlu_ctl.scala 708:20] - node _T_557 = not(take_nmi) @[dec_tlu_ctl.scala 708:42] - node _T_558 = and(_T_556, _T_557) @[dec_tlu_ctl.scala 708:40] - node _T_559 = bits(_T_558, 0, 0) @[dec_tlu_ctl.scala 708:53] - node _T_560 = not(lsu_exc_st_r) @[dec_tlu_ctl.scala 709:25] - node _T_561 = and(lsu_exc_ma_r, _T_560) @[dec_tlu_ctl.scala 709:23] - node _T_562 = not(take_nmi) @[dec_tlu_ctl.scala 709:41] - node _T_563 = and(_T_561, _T_562) @[dec_tlu_ctl.scala 709:39] - node _T_564 = bits(_T_563, 0, 0) @[dec_tlu_ctl.scala 709:52] - node _T_565 = not(lsu_exc_st_r) @[dec_tlu_ctl.scala 710:26] - node _T_566 = and(lsu_exc_acc_r, _T_565) @[dec_tlu_ctl.scala 710:24] - node _T_567 = not(take_nmi) @[dec_tlu_ctl.scala 710:42] - node _T_568 = and(_T_566, _T_567) @[dec_tlu_ctl.scala 710:40] - node _T_569 = bits(_T_568, 0, 0) @[dec_tlu_ctl.scala 710:53] - node _T_570 = and(lsu_exc_ma_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 711:23] - node _T_571 = not(take_nmi) @[dec_tlu_ctl.scala 711:40] - node _T_572 = and(_T_570, _T_571) @[dec_tlu_ctl.scala 711:38] - node _T_573 = bits(_T_572, 0, 0) @[dec_tlu_ctl.scala 711:51] - node _T_574 = and(lsu_exc_acc_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 712:24] - node _T_575 = not(take_nmi) @[dec_tlu_ctl.scala 712:41] - node _T_576 = and(_T_574, _T_575) @[dec_tlu_ctl.scala 712:39] - node _T_577 = bits(_T_576, 0, 0) @[dec_tlu_ctl.scala 712:52] + node update_hit_bit_r = and(_T_342, i0_trigger_chain_masked_r) @[dec_tlu_ctl.scala 535:56] + node _T_343 = and(i0_trigger_chain_masked_r, trigger_action) @[dec_tlu_ctl.scala 538:57] + node i0_trigger_action_r = orr(_T_343) @[dec_tlu_ctl.scala 538:75] + node _T_344 = and(i0_trigger_hit_r, i0_trigger_action_r) @[dec_tlu_ctl.scala 540:45] + trigger_hit_dmode_r <= _T_344 @[dec_tlu_ctl.scala 540:24] + node _T_345 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 542:55] + node mepc_trigger_hit_sel_pc_r = and(i0_trigger_hit_r, _T_345) @[dec_tlu_ctl.scala 542:53] + node _T_346 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 569:62] + node _T_347 = and(i_cpu_halt_req_sync, _T_346) @[dec_tlu_ctl.scala 569:60] + node _T_348 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 569:87] + node i_cpu_halt_req_sync_qual = and(_T_347, _T_348) @[dec_tlu_ctl.scala 569:85] + node _T_349 = not(io.dec_tlu_debug_mode) @[dec_tlu_ctl.scala 570:60] + node _T_350 = and(i_cpu_run_req_sync, _T_349) @[dec_tlu_ctl.scala 570:58] + node _T_351 = and(_T_350, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 570:83] + node _T_352 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 570:107] + node i_cpu_run_req_sync_qual = and(_T_351, _T_352) @[dec_tlu_ctl.scala 570:105] + reg i_cpu_halt_req_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 572:80] + i_cpu_halt_req_d1 <= i_cpu_halt_req_sync_qual @[dec_tlu_ctl.scala 572:80] + reg i_cpu_run_req_d1_raw : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 573:80] + i_cpu_run_req_d1_raw <= i_cpu_run_req_sync_qual @[dec_tlu_ctl.scala 573:80] + reg _T_353 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 574:81] + _T_353 <= cpu_halt_status @[dec_tlu_ctl.scala 574:81] + io.o_cpu_halt_status <= _T_353 @[dec_tlu_ctl.scala 574:49] + reg _T_354 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 575:81] + _T_354 <= cpu_halt_ack @[dec_tlu_ctl.scala 575:81] + io.o_cpu_halt_ack <= _T_354 @[dec_tlu_ctl.scala 575:49] + reg _T_355 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 576:81] + _T_355 <= cpu_run_ack @[dec_tlu_ctl.scala 576:81] + io.o_cpu_run_ack <= _T_355 @[dec_tlu_ctl.scala 576:49] + reg internal_pmu_fw_halt_mode_f : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 577:68] + internal_pmu_fw_halt_mode_f <= internal_pmu_fw_halt_mode @[dec_tlu_ctl.scala 577:68] + reg _T_356 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 578:73] + _T_356 <= pmu_fw_halt_req_ns @[dec_tlu_ctl.scala 578:73] + pmu_fw_halt_req_f <= _T_356 @[dec_tlu_ctl.scala 578:41] + reg _T_357 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 579:73] + _T_357 <= pmu_fw_tlu_halted @[dec_tlu_ctl.scala 579:73] + pmu_fw_tlu_halted_f <= _T_357 @[dec_tlu_ctl.scala 579:41] + reg _T_358 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 580:73] + _T_358 <= int_timer0_int_hold @[dec_tlu_ctl.scala 580:73] + int_timer0_int_hold_f <= _T_358 @[dec_tlu_ctl.scala 580:41] + reg _T_359 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 581:73] + _T_359 <= int_timer1_int_hold @[dec_tlu_ctl.scala 581:73] + int_timer1_int_hold_f <= _T_359 @[dec_tlu_ctl.scala 581:41] + node _T_360 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 585:52] + node ext_halt_pulse = and(i_cpu_halt_req_sync_qual, _T_360) @[dec_tlu_ctl.scala 585:50] + node enter_pmu_fw_halt_req = or(ext_halt_pulse, fw_halt_req) @[dec_tlu_ctl.scala 586:48] + node _T_361 = not(pmu_fw_tlu_halted) @[dec_tlu_ctl.scala 587:72] + node _T_362 = and(pmu_fw_halt_req_f, _T_361) @[dec_tlu_ctl.scala 587:70] + node _T_363 = or(enter_pmu_fw_halt_req, _T_362) @[dec_tlu_ctl.scala 587:49] + node _T_364 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 587:95] + node _T_365 = and(_T_363, _T_364) @[dec_tlu_ctl.scala 587:93] + pmu_fw_halt_req_ns <= _T_365 @[dec_tlu_ctl.scala 587:23] + node _T_366 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 588:85] + node _T_367 = and(internal_pmu_fw_halt_mode_f, _T_366) @[dec_tlu_ctl.scala 588:83] + node _T_368 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 588:105] + node _T_369 = and(_T_367, _T_368) @[dec_tlu_ctl.scala 588:103] + node _T_370 = or(pmu_fw_halt_req_ns, _T_369) @[dec_tlu_ctl.scala 588:52] + internal_pmu_fw_halt_mode <= _T_370 @[dec_tlu_ctl.scala 588:30] + node _T_371 = and(pmu_fw_halt_req_f, core_empty) @[dec_tlu_ctl.scala 591:45] + node _T_372 = and(_T_371, halt_taken) @[dec_tlu_ctl.scala 591:58] + node _T_373 = not(enter_debug_halt_req) @[dec_tlu_ctl.scala 591:73] + node _T_374 = and(_T_372, _T_373) @[dec_tlu_ctl.scala 591:71] + node _T_375 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 591:121] + node _T_376 = and(pmu_fw_tlu_halted_f, _T_375) @[dec_tlu_ctl.scala 591:119] + node _T_377 = or(_T_374, _T_376) @[dec_tlu_ctl.scala 591:96] + node _T_378 = not(debug_halt_req_f) @[dec_tlu_ctl.scala 591:143] + node _T_379 = and(_T_377, _T_378) @[dec_tlu_ctl.scala 591:141] + pmu_fw_tlu_halted <= _T_379 @[dec_tlu_ctl.scala 591:22] + node _T_380 = and(i_cpu_halt_req_d1, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 593:38] + cpu_halt_ack <= _T_380 @[dec_tlu_ctl.scala 593:17] + node _T_381 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 594:46] + node _T_382 = and(pmu_fw_tlu_halted_f, _T_381) @[dec_tlu_ctl.scala 594:44] + node _T_383 = not(i_cpu_run_req_d1) @[dec_tlu_ctl.scala 594:91] + node _T_384 = and(io.o_cpu_halt_status, _T_383) @[dec_tlu_ctl.scala 594:89] + node _T_385 = not(debug_mode_status) @[dec_tlu_ctl.scala 594:111] + node _T_386 = and(_T_384, _T_385) @[dec_tlu_ctl.scala 594:109] + node _T_387 = or(_T_382, _T_386) @[dec_tlu_ctl.scala 594:65] + cpu_halt_status <= _T_387 @[dec_tlu_ctl.scala 594:20] + node _T_388 = and(io.o_cpu_halt_status, i_cpu_run_req_sync_qual) @[dec_tlu_ctl.scala 595:41] + node _T_389 = and(io.o_cpu_run_ack, i_cpu_run_req_sync_qual) @[dec_tlu_ctl.scala 595:88] + node _T_390 = or(_T_388, _T_389) @[dec_tlu_ctl.scala 595:68] + cpu_run_ack <= _T_390 @[dec_tlu_ctl.scala 595:16] + io.o_debug_mode_status <= debug_mode_status @[dec_tlu_ctl.scala 597:27] + node _T_391 = or(nmi_int_detected, timer_int_ready) @[dec_tlu_ctl.scala 600:66] + node _T_392 = or(_T_391, soft_int_ready) @[dec_tlu_ctl.scala 600:84] + node _T_393 = or(_T_392, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 600:101] + node _T_394 = or(_T_393, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 600:125] + node _T_395 = and(io.dec_pic.mhwakeup, mhwakeup_ready) @[dec_tlu_ctl.scala 600:172] + node _T_396 = or(_T_394, _T_395) @[dec_tlu_ctl.scala 600:149] + node _T_397 = and(_T_396, io.o_cpu_halt_status) @[dec_tlu_ctl.scala 600:191] + node _T_398 = not(i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 600:216] + node _T_399 = and(_T_397, _T_398) @[dec_tlu_ctl.scala 600:214] + node _T_400 = or(i_cpu_run_req_d1_raw, _T_399) @[dec_tlu_ctl.scala 600:45] + i_cpu_run_req_d1 <= _T_400 @[dec_tlu_ctl.scala 600:21] + reg _T_401 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 606:89] + _T_401 <= mdseac_locked_ns @[dec_tlu_ctl.scala 606:89] + mdseac_locked_f <= _T_401 @[dec_tlu_ctl.scala 606:57] + reg lsu_single_ecc_error_r_d1 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 607:72] + lsu_single_ecc_error_r_d1 <= io.lsu_single_ecc_error_incr @[dec_tlu_ctl.scala 607:72] + node _T_402 = not(io.dec_tlu_flush_lower_wb) @[dec_tlu_ctl.scala 609:57] + node lsu_exc_valid_r_raw = and(io.lsu_error_pkt_r.valid, _T_402) @[dec_tlu_ctl.scala 609:55] + lsu_i0_exc_r_raw <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 610:21] + node _T_403 = and(lsu_i0_exc_r_raw, lsu_exc_valid_r_raw) @[dec_tlu_ctl.scala 611:40] + node _T_404 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 611:64] + node _T_405 = and(_T_403, _T_404) @[dec_tlu_ctl.scala 611:62] + node _T_406 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 611:84] + node lsu_exc_valid_r = and(_T_405, _T_406) @[dec_tlu_ctl.scala 611:82] + reg _T_407 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 613:74] + _T_407 <= lsu_exc_valid_r @[dec_tlu_ctl.scala 613:74] + lsu_exc_valid_r_d1 <= _T_407 @[dec_tlu_ctl.scala 613:41] + reg lsu_i0_exc_r_d1 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 614:73] + lsu_i0_exc_r_d1 <= lsu_exc_valid_r @[dec_tlu_ctl.scala 614:73] + node _T_408 = not(io.lsu_error_pkt_r.bits.exc_type) @[dec_tlu_ctl.scala 615:40] + node lsu_exc_ma_r = and(lsu_exc_valid_r, _T_408) @[dec_tlu_ctl.scala 615:38] + node lsu_exc_acc_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.exc_type) @[dec_tlu_ctl.scala 616:38] + node lsu_exc_st_r = and(lsu_exc_valid_r, io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 617:38] + node _T_409 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 621:49] + node _T_410 = and(io.dec_tlu_i0_valid_r, _T_409) @[dec_tlu_ctl.scala 621:47] + node _T_411 = not(io.lsu_error_pkt_r.bits.inst_type) @[dec_tlu_ctl.scala 621:70] + node _T_412 = and(_T_411, io.lsu_error_pkt_r.bits.single_ecc_error) @[dec_tlu_ctl.scala 621:105] + node lsu_i0_rfnpc_r = and(_T_410, _T_412) @[dec_tlu_ctl.scala 621:67] + node _T_413 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 624:52] + node _T_414 = and(io.dec_tlu_i0_valid_r, _T_413) @[dec_tlu_ctl.scala 624:50] + node _T_415 = not(lsu_exc_valid_r) @[dec_tlu_ctl.scala 624:65] + node _T_416 = and(_T_414, _T_415) @[dec_tlu_ctl.scala 624:63] + node _T_417 = not(inst_acc_r) @[dec_tlu_ctl.scala 624:82] + node _T_418 = and(_T_416, _T_417) @[dec_tlu_ctl.scala 624:79] + node _T_419 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 624:96] + node _T_420 = and(_T_418, _T_419) @[dec_tlu_ctl.scala 624:94] + node _T_421 = not(request_debug_mode_r_d1) @[dec_tlu_ctl.scala 624:121] + node _T_422 = and(_T_420, _T_421) @[dec_tlu_ctl.scala 624:119] + node _T_423 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 624:148] + node tlu_i0_commit_cmt = and(_T_422, _T_423) @[dec_tlu_ctl.scala 624:146] + node _T_424 = or(rfpc_i0_r, lsu_exc_valid_r) @[dec_tlu_ctl.scala 627:38] + node _T_425 = or(_T_424, inst_acc_r) @[dec_tlu_ctl.scala 627:53] + node _T_426 = and(illegal_r, io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 627:79] + node _T_427 = or(_T_425, _T_426) @[dec_tlu_ctl.scala 627:66] + node _T_428 = or(_T_427, i0_trigger_hit_r) @[dec_tlu_ctl.scala 627:104] + tlu_i0_kill_writeb_r <= _T_428 @[dec_tlu_ctl.scala 627:25] + io.tlu_mem.dec_tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 628:37] + node _T_429 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 633:44] + node _T_430 = and(io.dec_tlu_i0_valid_r, _T_429) @[dec_tlu_ctl.scala 633:42] + node _T_431 = or(io.tlu_exu.exu_i0_br_error_r, io.tlu_exu.exu_i0_br_start_error_r) @[dec_tlu_ctl.scala 633:98] + node _T_432 = and(_T_430, _T_431) @[dec_tlu_ctl.scala 633:66] + node _T_433 = or(ic_perr_r_d1, iccm_sbecc_r_d1) @[dec_tlu_ctl.scala 633:154] + node _T_434 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 633:175] + node _T_435 = and(_T_433, _T_434) @[dec_tlu_ctl.scala 633:173] + node _T_436 = or(_T_432, _T_435) @[dec_tlu_ctl.scala 633:137] + node _T_437 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 633:199] + node _T_438 = and(_T_436, _T_437) @[dec_tlu_ctl.scala 633:196] + node _T_439 = not(lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 633:220] + node _T_440 = and(_T_438, _T_439) @[dec_tlu_ctl.scala 633:217] + rfpc_i0_r <= _T_440 @[dec_tlu_ctl.scala 633:14] + node _T_441 = not(io.tlu_exu.dec_tlu_flush_lower_r) @[dec_tlu_ctl.scala 636:70] + node _T_442 = and(iccm_repair_state_d1, _T_441) @[dec_tlu_ctl.scala 636:68] + node _T_443 = or(iccm_sbecc_r_d1, _T_442) @[dec_tlu_ctl.scala 636:44] + iccm_repair_state_ns <= _T_443 @[dec_tlu_ctl.scala 636:25] + node _T_444 = and(tlu_i0_commit_cmt, iccm_repair_state_d1) @[dec_tlu_ctl.scala 642:52] + node _T_445 = or(ebreak_r, ecall_r) @[dec_tlu_ctl.scala 642:88] + node _T_446 = or(_T_445, mret_r) @[dec_tlu_ctl.scala 642:98] + node _T_447 = or(_T_446, take_reset) @[dec_tlu_ctl.scala 642:107] + node _T_448 = or(_T_447, illegal_r) @[dec_tlu_ctl.scala 642:120] + node _T_449 = eq(io.dec_csr_wraddr_r, UInt<12>("h07c2")) @[dec_tlu_ctl.scala 642:176] + node _T_450 = and(dec_csr_wen_r_mod, _T_449) @[dec_tlu_ctl.scala 642:153] + node _T_451 = or(_T_448, _T_450) @[dec_tlu_ctl.scala 642:132] + node _T_452 = not(_T_451) @[dec_tlu_ctl.scala 642:77] + node iccm_repair_state_rfnpc = and(_T_444, _T_452) @[dec_tlu_ctl.scala 642:75] + node _T_453 = and(io.tlu_exu.exu_i0_br_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 645:59] + node _T_454 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 645:85] + node dec_tlu_br0_error_r = and(_T_453, _T_454) @[dec_tlu_ctl.scala 645:83] + node _T_455 = and(io.tlu_exu.exu_i0_br_start_error_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 646:71] + node _T_456 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 646:97] + node dec_tlu_br0_start_error_r = and(_T_455, _T_456) @[dec_tlu_ctl.scala 646:95] + node _T_457 = and(io.tlu_exu.exu_i0_br_valid_r, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 647:55] + node _T_458 = not(tlu_flush_lower_r_d1) @[dec_tlu_ctl.scala 647:81] + node _T_459 = and(_T_457, _T_458) @[dec_tlu_ctl.scala 647:79] + node _T_460 = not(io.tlu_exu.exu_i0_br_mp_r) @[dec_tlu_ctl.scala 647:106] + node _T_461 = not(io.tlu_exu.exu_pmu_i0_br_ataken) @[dec_tlu_ctl.scala 647:135] + node _T_462 = or(_T_460, _T_461) @[dec_tlu_ctl.scala 647:133] + node dec_tlu_br0_v_r = and(_T_459, _T_462) @[dec_tlu_ctl.scala 647:103] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist <= io.tlu_exu.exu_i0_br_hist_r @[dec_tlu_ctl.scala 650:65] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 651:57] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 652:57] + io.tlu_bp.dec_tlu_br0_r_pkt.valid <= dec_tlu_br0_v_r @[dec_tlu_ctl.scala 653:57] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.way <= io.exu_i0_br_way_r @[dec_tlu_ctl.scala 654:65] + io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle <= io.tlu_exu.exu_i0_br_middle_r @[dec_tlu_ctl.scala 655:65] + node _T_463 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 658:51] + node _T_464 = and(_T_463, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 658:64] + node _T_465 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 658:90] + node _T_466 = and(_T_464, _T_465) @[dec_tlu_ctl.scala 658:88] + node _T_467 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 658:115] + node _T_468 = not(_T_467) @[dec_tlu_ctl.scala 658:110] + node _T_469 = and(_T_466, _T_468) @[dec_tlu_ctl.scala 658:108] + node _T_470 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 658:132] + node _T_471 = and(_T_469, _T_470) @[dec_tlu_ctl.scala 658:130] + ebreak_r <= _T_471 @[dec_tlu_ctl.scala 658:13] + node _T_472 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h09")) @[dec_tlu_ctl.scala 659:51] + node _T_473 = and(_T_472, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 659:64] + node _T_474 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 659:90] + node _T_475 = and(_T_473, _T_474) @[dec_tlu_ctl.scala 659:88] + node _T_476 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 659:110] + node _T_477 = and(_T_475, _T_476) @[dec_tlu_ctl.scala 659:108] + ecall_r <= _T_477 @[dec_tlu_ctl.scala 659:13] + node _T_478 = not(io.dec_tlu_packet_r.legal) @[dec_tlu_ctl.scala 660:17] + node _T_479 = and(_T_478, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 660:46] + node _T_480 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 660:72] + node _T_481 = and(_T_479, _T_480) @[dec_tlu_ctl.scala 660:70] + node _T_482 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 660:92] + node _T_483 = and(_T_481, _T_482) @[dec_tlu_ctl.scala 660:90] + illegal_r <= _T_483 @[dec_tlu_ctl.scala 660:13] + node _T_484 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h0c")) @[dec_tlu_ctl.scala 661:51] + node _T_485 = and(_T_484, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 661:64] + node _T_486 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 661:90] + node _T_487 = and(_T_485, _T_486) @[dec_tlu_ctl.scala 661:88] + node _T_488 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 661:110] + node _T_489 = and(_T_487, _T_488) @[dec_tlu_ctl.scala 661:108] + mret_r <= _T_489 @[dec_tlu_ctl.scala 661:13] + node _T_490 = and(io.dec_tlu_packet_r.fence_i, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 663:50] + node _T_491 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 663:76] + node _T_492 = and(_T_490, _T_491) @[dec_tlu_ctl.scala 663:74] + node _T_493 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 663:97] + node _T_494 = and(_T_492, _T_493) @[dec_tlu_ctl.scala 663:95] + fence_i_r <= _T_494 @[dec_tlu_ctl.scala 663:17] + node _T_495 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 664:53] + node _T_496 = and(io.tlu_mem.ifu_ic_error_start, _T_495) @[dec_tlu_ctl.scala 664:51] + node _T_497 = not(debug_mode_status) @[dec_tlu_ctl.scala 664:75] + node _T_498 = or(_T_497, dcsr_single_step_running) @[dec_tlu_ctl.scala 664:101] + node _T_499 = and(_T_496, _T_498) @[dec_tlu_ctl.scala 664:72] + node _T_500 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 664:131] + node _T_501 = and(_T_499, _T_500) @[dec_tlu_ctl.scala 664:129] + ic_perr_r <= _T_501 @[dec_tlu_ctl.scala 664:17] + node _T_502 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 665:61] + node _T_503 = and(io.tlu_mem.ifu_iccm_rd_ecc_single_err, _T_502) @[dec_tlu_ctl.scala 665:59] + node _T_504 = not(debug_mode_status) @[dec_tlu_ctl.scala 665:83] + node _T_505 = or(_T_504, dcsr_single_step_running) @[dec_tlu_ctl.scala 665:109] + node _T_506 = and(_T_503, _T_505) @[dec_tlu_ctl.scala 665:80] + node _T_507 = not(internal_pmu_fw_halt_mode_f) @[dec_tlu_ctl.scala 665:139] + node _T_508 = and(_T_506, _T_507) @[dec_tlu_ctl.scala 665:137] + iccm_sbecc_r <= _T_508 @[dec_tlu_ctl.scala 665:17] + node _T_509 = and(io.dec_tlu_packet_r.icaf, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 666:49] + inst_acc_r_raw <= _T_509 @[dec_tlu_ctl.scala 666:20] + node _T_510 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 667:35] + node _T_511 = and(inst_acc_r_raw, _T_510) @[dec_tlu_ctl.scala 667:33] + node _T_512 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 667:48] + node _T_513 = and(_T_511, _T_512) @[dec_tlu_ctl.scala 667:46] + inst_acc_r <= _T_513 @[dec_tlu_ctl.scala 667:15] + node _T_514 = eq(io.dec_tlu_packet_r.pmu_i0_itype, UInt<4>("h08")) @[dec_tlu_ctl.scala 670:64] + node _T_515 = and(_T_514, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 670:77] + node _T_516 = not(i0_trigger_hit_r) @[dec_tlu_ctl.scala 670:103] + node _T_517 = and(_T_515, _T_516) @[dec_tlu_ctl.scala 670:101] + node _T_518 = bits(dcsr, 15, 15) @[dec_tlu_ctl.scala 670:127] + node _T_519 = and(_T_517, _T_518) @[dec_tlu_ctl.scala 670:121] + node _T_520 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 670:144] + node _T_521 = and(_T_519, _T_520) @[dec_tlu_ctl.scala 670:142] + ebreak_to_debug_mode_r <= _T_521 @[dec_tlu_ctl.scala 670:27] + reg _T_522 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 672:64] + _T_522 <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 672:64] + ebreak_to_debug_mode_r_d1 <= _T_522 @[dec_tlu_ctl.scala 672:34] + io.tlu_mem.dec_tlu_fence_i_wb <= fence_i_r @[dec_tlu_ctl.scala 673:39] + node _T_523 = or(ebreak_r, ecall_r) @[dec_tlu_ctl.scala 686:41] + node _T_524 = or(_T_523, illegal_r) @[dec_tlu_ctl.scala 686:51] + node _T_525 = or(_T_524, inst_acc_r) @[dec_tlu_ctl.scala 686:63] + node _T_526 = not(rfpc_i0_r) @[dec_tlu_ctl.scala 686:79] + node _T_527 = and(_T_525, _T_526) @[dec_tlu_ctl.scala 686:77] + node _T_528 = not(io.dec_tlu_dbg_halted) @[dec_tlu_ctl.scala 686:92] + node i0_exception_valid_r = and(_T_527, _T_528) @[dec_tlu_ctl.scala 686:90] + node _T_529 = not(take_nmi) @[dec_tlu_ctl.scala 695:33] + node _T_530 = and(take_ext_int, _T_529) @[dec_tlu_ctl.scala 695:31] + node _T_531 = bits(_T_530, 0, 0) @[dec_tlu_ctl.scala 695:44] + node _T_532 = not(take_nmi) @[dec_tlu_ctl.scala 696:27] + node _T_533 = and(take_timer_int, _T_532) @[dec_tlu_ctl.scala 696:25] + node _T_534 = bits(_T_533, 0, 0) @[dec_tlu_ctl.scala 696:38] + node _T_535 = not(take_nmi) @[dec_tlu_ctl.scala 697:26] + node _T_536 = and(take_soft_int, _T_535) @[dec_tlu_ctl.scala 697:24] + node _T_537 = bits(_T_536, 0, 0) @[dec_tlu_ctl.scala 697:37] + node _T_538 = not(take_nmi) @[dec_tlu_ctl.scala 698:32] + node _T_539 = and(take_int_timer0_int, _T_538) @[dec_tlu_ctl.scala 698:30] + node _T_540 = bits(_T_539, 0, 0) @[dec_tlu_ctl.scala 698:43] + node _T_541 = not(take_nmi) @[dec_tlu_ctl.scala 699:32] + node _T_542 = and(take_int_timer1_int, _T_541) @[dec_tlu_ctl.scala 699:30] + node _T_543 = bits(_T_542, 0, 0) @[dec_tlu_ctl.scala 699:43] + node _T_544 = not(take_nmi) @[dec_tlu_ctl.scala 700:24] + node _T_545 = and(take_ce_int, _T_544) @[dec_tlu_ctl.scala 700:22] + node _T_546 = bits(_T_545, 0, 0) @[dec_tlu_ctl.scala 700:35] + node _T_547 = not(take_nmi) @[dec_tlu_ctl.scala 701:22] + node _T_548 = and(illegal_r, _T_547) @[dec_tlu_ctl.scala 701:20] + node _T_549 = bits(_T_548, 0, 0) @[dec_tlu_ctl.scala 701:33] + node _T_550 = not(take_nmi) @[dec_tlu_ctl.scala 702:21] + node _T_551 = and(ecall_r, _T_550) @[dec_tlu_ctl.scala 702:19] + node _T_552 = bits(_T_551, 0, 0) @[dec_tlu_ctl.scala 702:32] + node _T_553 = not(take_nmi) @[dec_tlu_ctl.scala 703:24] + node _T_554 = and(inst_acc_r, _T_553) @[dec_tlu_ctl.scala 703:22] + node _T_555 = bits(_T_554, 0, 0) @[dec_tlu_ctl.scala 703:35] + node _T_556 = or(ebreak_r, i0_trigger_hit_r) @[dec_tlu_ctl.scala 704:20] + node _T_557 = not(take_nmi) @[dec_tlu_ctl.scala 704:42] + node _T_558 = and(_T_556, _T_557) @[dec_tlu_ctl.scala 704:40] + node _T_559 = bits(_T_558, 0, 0) @[dec_tlu_ctl.scala 704:53] + node _T_560 = not(lsu_exc_st_r) @[dec_tlu_ctl.scala 705:25] + node _T_561 = and(lsu_exc_ma_r, _T_560) @[dec_tlu_ctl.scala 705:23] + node _T_562 = not(take_nmi) @[dec_tlu_ctl.scala 705:41] + node _T_563 = and(_T_561, _T_562) @[dec_tlu_ctl.scala 705:39] + node _T_564 = bits(_T_563, 0, 0) @[dec_tlu_ctl.scala 705:52] + node _T_565 = not(lsu_exc_st_r) @[dec_tlu_ctl.scala 706:26] + node _T_566 = and(lsu_exc_acc_r, _T_565) @[dec_tlu_ctl.scala 706:24] + node _T_567 = not(take_nmi) @[dec_tlu_ctl.scala 706:42] + node _T_568 = and(_T_566, _T_567) @[dec_tlu_ctl.scala 706:40] + node _T_569 = bits(_T_568, 0, 0) @[dec_tlu_ctl.scala 706:53] + node _T_570 = and(lsu_exc_ma_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 707:23] + node _T_571 = not(take_nmi) @[dec_tlu_ctl.scala 707:40] + node _T_572 = and(_T_570, _T_571) @[dec_tlu_ctl.scala 707:38] + node _T_573 = bits(_T_572, 0, 0) @[dec_tlu_ctl.scala 707:51] + node _T_574 = and(lsu_exc_acc_r, lsu_exc_st_r) @[dec_tlu_ctl.scala 708:24] + node _T_575 = not(take_nmi) @[dec_tlu_ctl.scala 708:41] + node _T_576 = and(_T_574, _T_575) @[dec_tlu_ctl.scala 708:39] + node _T_577 = bits(_T_576, 0, 0) @[dec_tlu_ctl.scala 708:52] node _T_578 = mux(_T_531, UInt<5>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_579 = mux(_T_534, UInt<5>("h07"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_580 = mux(_T_537, UInt<5>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -78975,281 +78975,281 @@ circuit quasar_wrapper : node _T_604 = or(_T_603, _T_591) @[Mux.scala 27:72] wire exc_cause_r : UInt<5> @[Mux.scala 27:72] exc_cause_r <= _T_604 @[Mux.scala 27:72] - node _T_605 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 723:24] - node _T_606 = and(_T_605, mstatus_mie_ns) @[dec_tlu_ctl.scala 723:49] - node _T_607 = bits(mip, 2, 2) @[dec_tlu_ctl.scala 723:71] - node _T_608 = and(_T_606, _T_607) @[dec_tlu_ctl.scala 723:66] - node _T_609 = bits(mie_ns, 2, 2) @[dec_tlu_ctl.scala 723:92] - node _T_610 = and(_T_608, _T_609) @[dec_tlu_ctl.scala 723:84] - mhwakeup_ready <= _T_610 @[dec_tlu_ctl.scala 723:20] - node _T_611 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 724:23] - node _T_612 = and(_T_611, mstatus_mie_ns) @[dec_tlu_ctl.scala 724:48] - node _T_613 = bits(mip, 2, 2) @[dec_tlu_ctl.scala 724:70] - node _T_614 = and(_T_612, _T_613) @[dec_tlu_ctl.scala 724:65] - node _T_615 = bits(mie_ns, 2, 2) @[dec_tlu_ctl.scala 724:91] - node _T_616 = and(_T_614, _T_615) @[dec_tlu_ctl.scala 724:83] - node _T_617 = not(ignore_ext_int_due_to_lsu_stall) @[dec_tlu_ctl.scala 724:104] - node _T_618 = and(_T_616, _T_617) @[dec_tlu_ctl.scala 724:102] - ext_int_ready <= _T_618 @[dec_tlu_ctl.scala 724:20] - node _T_619 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 725:23] - node _T_620 = and(_T_619, mstatus_mie_ns) @[dec_tlu_ctl.scala 725:48] - node _T_621 = bits(mip, 5, 5) @[dec_tlu_ctl.scala 725:70] - node _T_622 = and(_T_620, _T_621) @[dec_tlu_ctl.scala 725:65] - node _T_623 = bits(mie_ns, 5, 5) @[dec_tlu_ctl.scala 725:91] - node _T_624 = and(_T_622, _T_623) @[dec_tlu_ctl.scala 725:83] - ce_int_ready <= _T_624 @[dec_tlu_ctl.scala 725:20] - node _T_625 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 726:23] - node _T_626 = and(_T_625, mstatus_mie_ns) @[dec_tlu_ctl.scala 726:48] - node _T_627 = bits(mip, 0, 0) @[dec_tlu_ctl.scala 726:70] - node _T_628 = and(_T_626, _T_627) @[dec_tlu_ctl.scala 726:65] - node _T_629 = bits(mie_ns, 0, 0) @[dec_tlu_ctl.scala 726:91] - node _T_630 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 726:83] - soft_int_ready <= _T_630 @[dec_tlu_ctl.scala 726:20] - node _T_631 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 727:23] - node _T_632 = and(_T_631, mstatus_mie_ns) @[dec_tlu_ctl.scala 727:48] - node _T_633 = bits(mip, 1, 1) @[dec_tlu_ctl.scala 727:70] - node _T_634 = and(_T_632, _T_633) @[dec_tlu_ctl.scala 727:65] - node _T_635 = bits(mie_ns, 1, 1) @[dec_tlu_ctl.scala 727:91] - node _T_636 = and(_T_634, _T_635) @[dec_tlu_ctl.scala 727:83] - timer_int_ready <= _T_636 @[dec_tlu_ctl.scala 727:20] - node _T_637 = bits(mie_ns, 4, 4) @[dec_tlu_ctl.scala 730:57] - node int_timer0_int_possible = and(mstatus_mie_ns, _T_637) @[dec_tlu_ctl.scala 730:49] - node _T_638 = bits(mip, 4, 4) @[dec_tlu_ctl.scala 731:34] - node int_timer0_int_ready = and(_T_638, int_timer0_int_possible) @[dec_tlu_ctl.scala 731:47] - node _T_639 = bits(mie_ns, 3, 3) @[dec_tlu_ctl.scala 732:57] - node int_timer1_int_possible = and(mstatus_mie_ns, _T_639) @[dec_tlu_ctl.scala 732:49] - node _T_640 = bits(mip, 3, 3) @[dec_tlu_ctl.scala 733:34] - node int_timer1_int_ready = and(_T_640, int_timer1_int_possible) @[dec_tlu_ctl.scala 733:47] - node _T_641 = or(io.dec_csr_stall_int_ff, synchronous_flush_r) @[dec_tlu_ctl.scala 737:52] - node _T_642 = or(_T_641, exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 737:74] - node int_timer_stalled = or(_T_642, mret_r) @[dec_tlu_ctl.scala 737:98] - node _T_643 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 739:72] - node _T_644 = and(int_timer0_int_ready, _T_643) @[dec_tlu_ctl.scala 739:49] - node _T_645 = and(int_timer0_int_possible, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 739:121] - node _T_646 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 739:147] - node _T_647 = and(_T_645, _T_646) @[dec_tlu_ctl.scala 739:145] - node _T_648 = not(take_ext_int_start) @[dec_tlu_ctl.scala 739:168] - node _T_649 = and(_T_647, _T_648) @[dec_tlu_ctl.scala 739:166] - node _T_650 = not(debug_mode_status) @[dec_tlu_ctl.scala 739:190] - node _T_651 = and(_T_649, _T_650) @[dec_tlu_ctl.scala 739:188] - node _T_652 = or(_T_644, _T_651) @[dec_tlu_ctl.scala 739:94] - int_timer0_int_hold <= _T_652 @[dec_tlu_ctl.scala 739:24] - node _T_653 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 740:72] - node _T_654 = and(int_timer1_int_ready, _T_653) @[dec_tlu_ctl.scala 740:49] - node _T_655 = and(int_timer1_int_possible, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 740:121] - node _T_656 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 740:147] - node _T_657 = and(_T_655, _T_656) @[dec_tlu_ctl.scala 740:145] - node _T_658 = not(take_ext_int_start) @[dec_tlu_ctl.scala 740:168] - node _T_659 = and(_T_657, _T_658) @[dec_tlu_ctl.scala 740:166] - node _T_660 = not(debug_mode_status) @[dec_tlu_ctl.scala 740:190] - node _T_661 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 740:188] - node _T_662 = or(_T_654, _T_661) @[dec_tlu_ctl.scala 740:94] - int_timer1_int_hold <= _T_662 @[dec_tlu_ctl.scala 740:24] - node _T_663 = not(dcsr_single_step_running) @[dec_tlu_ctl.scala 742:59] - node _T_664 = and(debug_mode_status, _T_663) @[dec_tlu_ctl.scala 742:57] - internal_dbg_halt_timers <= _T_664 @[dec_tlu_ctl.scala 742:29] - node _T_665 = not(dcsr_single_step_running) @[dec_tlu_ctl.scala 744:55] - node _T_666 = or(_T_665, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 744:81] - node _T_667 = and(internal_dbg_halt_mode, _T_666) @[dec_tlu_ctl.scala 744:52] - node _T_668 = or(_T_667, internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 744:107] - node _T_669 = or(_T_668, i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 744:135] - node _T_670 = or(_T_669, take_nmi) @[dec_tlu_ctl.scala 744:155] - node _T_671 = or(_T_670, ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 744:166] - node _T_672 = or(_T_671, synchronous_flush_r) @[dec_tlu_ctl.scala 744:191] - node _T_673 = or(_T_672, exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 744:214] - node _T_674 = or(_T_673, mret_r) @[dec_tlu_ctl.scala 744:238] - node block_interrupts = or(_T_674, ext_int_freeze_d1) @[dec_tlu_ctl.scala 744:247] - reg _T_675 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 748:62] - _T_675 <= take_ext_int_start @[dec_tlu_ctl.scala 748:62] - take_ext_int_start_d1 <= _T_675 @[dec_tlu_ctl.scala 748:30] - reg _T_676 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 749:62] - _T_676 <= take_ext_int_start_d1 @[dec_tlu_ctl.scala 749:62] - take_ext_int_start_d2 <= _T_676 @[dec_tlu_ctl.scala 749:30] - reg _T_677 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 750:62] - _T_677 <= take_ext_int_start_d2 @[dec_tlu_ctl.scala 750:62] - take_ext_int_start_d3 <= _T_677 @[dec_tlu_ctl.scala 750:30] - reg _T_678 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 751:66] - _T_678 <= ext_int_freeze @[dec_tlu_ctl.scala 751:66] - ext_int_freeze_d1 <= _T_678 @[dec_tlu_ctl.scala 751:34] - node _T_679 = not(block_interrupts) @[dec_tlu_ctl.scala 752:47] - node _T_680 = and(ext_int_ready, _T_679) @[dec_tlu_ctl.scala 752:45] - take_ext_int_start <= _T_680 @[dec_tlu_ctl.scala 752:28] - node _T_681 = or(take_ext_int_start, take_ext_int_start_d1) @[dec_tlu_ctl.scala 754:46] - node _T_682 = or(_T_681, take_ext_int_start_d2) @[dec_tlu_ctl.scala 754:70] - node _T_683 = or(_T_682, take_ext_int_start_d3) @[dec_tlu_ctl.scala 754:94] - ext_int_freeze <= _T_683 @[dec_tlu_ctl.scala 754:24] - node _T_684 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 755:67] - node _T_685 = not(_T_684) @[dec_tlu_ctl.scala 755:49] - node _T_686 = and(take_ext_int_start_d3, _T_685) @[dec_tlu_ctl.scala 755:47] - take_ext_int <= _T_686 @[dec_tlu_ctl.scala 755:22] - node _T_687 = and(csr_pkt.csr_meicpct, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 756:49] - fast_int_meicpct <= _T_687 @[dec_tlu_ctl.scala 756:26] - ignore_ext_int_due_to_lsu_stall <= io.lsu_fastint_stall_any @[dec_tlu_ctl.scala 757:41] - node _T_688 = not(ext_int_ready) @[dec_tlu_ctl.scala 770:35] - node _T_689 = and(ce_int_ready, _T_688) @[dec_tlu_ctl.scala 770:33] - node _T_690 = not(block_interrupts) @[dec_tlu_ctl.scala 770:52] - node _T_691 = and(_T_689, _T_690) @[dec_tlu_ctl.scala 770:50] - take_ce_int <= _T_691 @[dec_tlu_ctl.scala 770:17] - node _T_692 = not(ext_int_ready) @[dec_tlu_ctl.scala 771:38] - node _T_693 = and(soft_int_ready, _T_692) @[dec_tlu_ctl.scala 771:36] - node _T_694 = not(ce_int_ready) @[dec_tlu_ctl.scala 771:55] - node _T_695 = and(_T_693, _T_694) @[dec_tlu_ctl.scala 771:53] - node _T_696 = not(block_interrupts) @[dec_tlu_ctl.scala 771:71] - node _T_697 = and(_T_695, _T_696) @[dec_tlu_ctl.scala 771:69] - take_soft_int <= _T_697 @[dec_tlu_ctl.scala 771:18] - node _T_698 = not(soft_int_ready) @[dec_tlu_ctl.scala 772:40] - node _T_699 = and(timer_int_ready, _T_698) @[dec_tlu_ctl.scala 772:38] - node _T_700 = not(ext_int_ready) @[dec_tlu_ctl.scala 772:58] - node _T_701 = and(_T_699, _T_700) @[dec_tlu_ctl.scala 772:56] - node _T_702 = not(ce_int_ready) @[dec_tlu_ctl.scala 772:75] - node _T_703 = and(_T_701, _T_702) @[dec_tlu_ctl.scala 772:73] - node _T_704 = not(block_interrupts) @[dec_tlu_ctl.scala 772:91] - node _T_705 = and(_T_703, _T_704) @[dec_tlu_ctl.scala 772:89] - take_timer_int <= _T_705 @[dec_tlu_ctl.scala 772:19] - node _T_706 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 773:49] - node _T_707 = and(_T_706, int_timer0_int_possible) @[dec_tlu_ctl.scala 773:74] - node _T_708 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 773:102] - node _T_709 = and(_T_707, _T_708) @[dec_tlu_ctl.scala 773:100] - node _T_710 = not(timer_int_ready) @[dec_tlu_ctl.scala 773:129] - node _T_711 = and(_T_709, _T_710) @[dec_tlu_ctl.scala 773:127] - node _T_712 = not(soft_int_ready) @[dec_tlu_ctl.scala 773:148] - node _T_713 = and(_T_711, _T_712) @[dec_tlu_ctl.scala 773:146] - node _T_714 = not(ext_int_ready) @[dec_tlu_ctl.scala 773:166] - node _T_715 = and(_T_713, _T_714) @[dec_tlu_ctl.scala 773:164] - node _T_716 = not(ce_int_ready) @[dec_tlu_ctl.scala 773:183] - node _T_717 = and(_T_715, _T_716) @[dec_tlu_ctl.scala 773:181] - node _T_718 = not(block_interrupts) @[dec_tlu_ctl.scala 773:199] - node _T_719 = and(_T_717, _T_718) @[dec_tlu_ctl.scala 773:197] - take_int_timer0_int <= _T_719 @[dec_tlu_ctl.scala 773:24] - node _T_720 = or(int_timer1_int_ready, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 774:49] - node _T_721 = and(_T_720, int_timer1_int_possible) @[dec_tlu_ctl.scala 774:74] - node _T_722 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 774:102] - node _T_723 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 774:100] - node _T_724 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 774:152] - node _T_725 = not(_T_724) @[dec_tlu_ctl.scala 774:129] - node _T_726 = and(_T_723, _T_725) @[dec_tlu_ctl.scala 774:127] - node _T_727 = not(timer_int_ready) @[dec_tlu_ctl.scala 774:179] - node _T_728 = and(_T_726, _T_727) @[dec_tlu_ctl.scala 774:177] - node _T_729 = not(soft_int_ready) @[dec_tlu_ctl.scala 774:198] - node _T_730 = and(_T_728, _T_729) @[dec_tlu_ctl.scala 774:196] - node _T_731 = not(ext_int_ready) @[dec_tlu_ctl.scala 774:216] - node _T_732 = and(_T_730, _T_731) @[dec_tlu_ctl.scala 774:214] - node _T_733 = not(ce_int_ready) @[dec_tlu_ctl.scala 774:233] - node _T_734 = and(_T_732, _T_733) @[dec_tlu_ctl.scala 774:231] - node _T_735 = not(block_interrupts) @[dec_tlu_ctl.scala 774:249] - node _T_736 = and(_T_734, _T_735) @[dec_tlu_ctl.scala 774:247] - take_int_timer1_int <= _T_736 @[dec_tlu_ctl.scala 774:24] - node _T_737 = and(reset_delayed, io.mpc_reset_run_req) @[dec_tlu_ctl.scala 775:32] - take_reset <= _T_737 @[dec_tlu_ctl.scala 775:15] - node _T_738 = not(internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 776:35] - node _T_739 = and(nmi_int_detected, _T_738) @[dec_tlu_ctl.scala 776:33] - node _T_740 = not(internal_dbg_halt_mode) @[dec_tlu_ctl.scala 776:65] - node _T_741 = bits(dcsr, 11, 11) @[dec_tlu_ctl.scala 776:125] - node _T_742 = and(dcsr_single_step_running_f, _T_741) @[dec_tlu_ctl.scala 776:119] - node _T_743 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 776:141] - node _T_744 = and(_T_742, _T_743) @[dec_tlu_ctl.scala 776:139] - node _T_745 = not(dcsr_single_step_done_f) @[dec_tlu_ctl.scala 776:166] - node _T_746 = and(_T_744, _T_745) @[dec_tlu_ctl.scala 776:164] - node _T_747 = or(_T_740, _T_746) @[dec_tlu_ctl.scala 776:89] - node _T_748 = and(_T_739, _T_747) @[dec_tlu_ctl.scala 776:62] - node _T_749 = not(synchronous_flush_r) @[dec_tlu_ctl.scala 776:195] - node _T_750 = and(_T_748, _T_749) @[dec_tlu_ctl.scala 776:193] - node _T_751 = not(mret_r) @[dec_tlu_ctl.scala 776:218] - node _T_752 = and(_T_750, _T_751) @[dec_tlu_ctl.scala 776:216] - node _T_753 = not(take_reset) @[dec_tlu_ctl.scala 776:228] - node _T_754 = and(_T_752, _T_753) @[dec_tlu_ctl.scala 776:226] - node _T_755 = not(ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 776:242] - node _T_756 = and(_T_754, _T_755) @[dec_tlu_ctl.scala 776:240] - node _T_757 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 776:269] - node _T_758 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 776:332] - node _T_759 = and(take_ext_int_start_d3, _T_758) @[dec_tlu_ctl.scala 776:313] - node _T_760 = or(_T_757, _T_759) @[dec_tlu_ctl.scala 776:288] - node _T_761 = and(_T_756, _T_760) @[dec_tlu_ctl.scala 776:266] - take_nmi <= _T_761 @[dec_tlu_ctl.scala 776:13] - node _T_762 = or(take_ext_int, take_timer_int) @[dec_tlu_ctl.scala 779:38] - node _T_763 = or(_T_762, take_soft_int) @[dec_tlu_ctl.scala 779:55] - node _T_764 = or(_T_763, take_nmi) @[dec_tlu_ctl.scala 779:71] - node _T_765 = or(_T_764, take_ce_int) @[dec_tlu_ctl.scala 779:82] - node _T_766 = or(_T_765, take_int_timer0_int) @[dec_tlu_ctl.scala 779:96] - node _T_767 = or(_T_766, take_int_timer1_int) @[dec_tlu_ctl.scala 779:118] - interrupt_valid_r <= _T_767 @[dec_tlu_ctl.scala 779:22] - node _T_768 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 784:34] + node _T_605 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 719:24] + node _T_606 = and(_T_605, mstatus_mie_ns) @[dec_tlu_ctl.scala 719:49] + node _T_607 = bits(mip, 2, 2) @[dec_tlu_ctl.scala 719:71] + node _T_608 = and(_T_606, _T_607) @[dec_tlu_ctl.scala 719:66] + node _T_609 = bits(mie_ns, 2, 2) @[dec_tlu_ctl.scala 719:92] + node _T_610 = and(_T_608, _T_609) @[dec_tlu_ctl.scala 719:84] + mhwakeup_ready <= _T_610 @[dec_tlu_ctl.scala 719:20] + node _T_611 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 720:23] + node _T_612 = and(_T_611, mstatus_mie_ns) @[dec_tlu_ctl.scala 720:48] + node _T_613 = bits(mip, 2, 2) @[dec_tlu_ctl.scala 720:70] + node _T_614 = and(_T_612, _T_613) @[dec_tlu_ctl.scala 720:65] + node _T_615 = bits(mie_ns, 2, 2) @[dec_tlu_ctl.scala 720:91] + node _T_616 = and(_T_614, _T_615) @[dec_tlu_ctl.scala 720:83] + node _T_617 = not(ignore_ext_int_due_to_lsu_stall) @[dec_tlu_ctl.scala 720:104] + node _T_618 = and(_T_616, _T_617) @[dec_tlu_ctl.scala 720:102] + ext_int_ready <= _T_618 @[dec_tlu_ctl.scala 720:20] + node _T_619 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 721:23] + node _T_620 = and(_T_619, mstatus_mie_ns) @[dec_tlu_ctl.scala 721:48] + node _T_621 = bits(mip, 5, 5) @[dec_tlu_ctl.scala 721:70] + node _T_622 = and(_T_620, _T_621) @[dec_tlu_ctl.scala 721:65] + node _T_623 = bits(mie_ns, 5, 5) @[dec_tlu_ctl.scala 721:91] + node _T_624 = and(_T_622, _T_623) @[dec_tlu_ctl.scala 721:83] + ce_int_ready <= _T_624 @[dec_tlu_ctl.scala 721:20] + node _T_625 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 722:23] + node _T_626 = and(_T_625, mstatus_mie_ns) @[dec_tlu_ctl.scala 722:48] + node _T_627 = bits(mip, 0, 0) @[dec_tlu_ctl.scala 722:70] + node _T_628 = and(_T_626, _T_627) @[dec_tlu_ctl.scala 722:65] + node _T_629 = bits(mie_ns, 0, 0) @[dec_tlu_ctl.scala 722:91] + node _T_630 = and(_T_628, _T_629) @[dec_tlu_ctl.scala 722:83] + soft_int_ready <= _T_630 @[dec_tlu_ctl.scala 722:20] + node _T_631 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 723:23] + node _T_632 = and(_T_631, mstatus_mie_ns) @[dec_tlu_ctl.scala 723:48] + node _T_633 = bits(mip, 1, 1) @[dec_tlu_ctl.scala 723:70] + node _T_634 = and(_T_632, _T_633) @[dec_tlu_ctl.scala 723:65] + node _T_635 = bits(mie_ns, 1, 1) @[dec_tlu_ctl.scala 723:91] + node _T_636 = and(_T_634, _T_635) @[dec_tlu_ctl.scala 723:83] + timer_int_ready <= _T_636 @[dec_tlu_ctl.scala 723:20] + node _T_637 = bits(mie_ns, 4, 4) @[dec_tlu_ctl.scala 726:57] + node int_timer0_int_possible = and(mstatus_mie_ns, _T_637) @[dec_tlu_ctl.scala 726:49] + node _T_638 = bits(mip, 4, 4) @[dec_tlu_ctl.scala 727:34] + node int_timer0_int_ready = and(_T_638, int_timer0_int_possible) @[dec_tlu_ctl.scala 727:47] + node _T_639 = bits(mie_ns, 3, 3) @[dec_tlu_ctl.scala 728:57] + node int_timer1_int_possible = and(mstatus_mie_ns, _T_639) @[dec_tlu_ctl.scala 728:49] + node _T_640 = bits(mip, 3, 3) @[dec_tlu_ctl.scala 729:34] + node int_timer1_int_ready = and(_T_640, int_timer1_int_possible) @[dec_tlu_ctl.scala 729:47] + node _T_641 = or(io.dec_csr_stall_int_ff, synchronous_flush_r) @[dec_tlu_ctl.scala 733:52] + node _T_642 = or(_T_641, exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 733:74] + node int_timer_stalled = or(_T_642, mret_r) @[dec_tlu_ctl.scala 733:98] + node _T_643 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 735:72] + node _T_644 = and(int_timer0_int_ready, _T_643) @[dec_tlu_ctl.scala 735:49] + node _T_645 = and(int_timer0_int_possible, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 735:121] + node _T_646 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 735:147] + node _T_647 = and(_T_645, _T_646) @[dec_tlu_ctl.scala 735:145] + node _T_648 = not(take_ext_int_start) @[dec_tlu_ctl.scala 735:168] + node _T_649 = and(_T_647, _T_648) @[dec_tlu_ctl.scala 735:166] + node _T_650 = not(debug_mode_status) @[dec_tlu_ctl.scala 735:190] + node _T_651 = and(_T_649, _T_650) @[dec_tlu_ctl.scala 735:188] + node _T_652 = or(_T_644, _T_651) @[dec_tlu_ctl.scala 735:94] + int_timer0_int_hold <= _T_652 @[dec_tlu_ctl.scala 735:24] + node _T_653 = or(pmu_fw_tlu_halted_f, int_timer_stalled) @[dec_tlu_ctl.scala 736:72] + node _T_654 = and(int_timer1_int_ready, _T_653) @[dec_tlu_ctl.scala 736:49] + node _T_655 = and(int_timer1_int_possible, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 736:121] + node _T_656 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 736:147] + node _T_657 = and(_T_655, _T_656) @[dec_tlu_ctl.scala 736:145] + node _T_658 = not(take_ext_int_start) @[dec_tlu_ctl.scala 736:168] + node _T_659 = and(_T_657, _T_658) @[dec_tlu_ctl.scala 736:166] + node _T_660 = not(debug_mode_status) @[dec_tlu_ctl.scala 736:190] + node _T_661 = and(_T_659, _T_660) @[dec_tlu_ctl.scala 736:188] + node _T_662 = or(_T_654, _T_661) @[dec_tlu_ctl.scala 736:94] + int_timer1_int_hold <= _T_662 @[dec_tlu_ctl.scala 736:24] + node _T_663 = not(dcsr_single_step_running) @[dec_tlu_ctl.scala 738:59] + node _T_664 = and(debug_mode_status, _T_663) @[dec_tlu_ctl.scala 738:57] + internal_dbg_halt_timers <= _T_664 @[dec_tlu_ctl.scala 738:29] + node _T_665 = not(dcsr_single_step_running) @[dec_tlu_ctl.scala 740:55] + node _T_666 = or(_T_665, io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 740:81] + node _T_667 = and(internal_dbg_halt_mode, _T_666) @[dec_tlu_ctl.scala 740:52] + node _T_668 = or(_T_667, internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 740:107] + node _T_669 = or(_T_668, i_cpu_halt_req_d1) @[dec_tlu_ctl.scala 740:135] + node _T_670 = or(_T_669, take_nmi) @[dec_tlu_ctl.scala 740:155] + node _T_671 = or(_T_670, ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 740:166] + node _T_672 = or(_T_671, synchronous_flush_r) @[dec_tlu_ctl.scala 740:191] + node _T_673 = or(_T_672, exc_or_int_valid_r_d1) @[dec_tlu_ctl.scala 740:214] + node _T_674 = or(_T_673, mret_r) @[dec_tlu_ctl.scala 740:238] + node block_interrupts = or(_T_674, ext_int_freeze_d1) @[dec_tlu_ctl.scala 740:247] + reg _T_675 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 744:62] + _T_675 <= take_ext_int_start @[dec_tlu_ctl.scala 744:62] + take_ext_int_start_d1 <= _T_675 @[dec_tlu_ctl.scala 744:30] + reg _T_676 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 745:62] + _T_676 <= take_ext_int_start_d1 @[dec_tlu_ctl.scala 745:62] + take_ext_int_start_d2 <= _T_676 @[dec_tlu_ctl.scala 745:30] + reg _T_677 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 746:62] + _T_677 <= take_ext_int_start_d2 @[dec_tlu_ctl.scala 746:62] + take_ext_int_start_d3 <= _T_677 @[dec_tlu_ctl.scala 746:30] + reg _T_678 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 747:66] + _T_678 <= ext_int_freeze @[dec_tlu_ctl.scala 747:66] + ext_int_freeze_d1 <= _T_678 @[dec_tlu_ctl.scala 747:34] + node _T_679 = not(block_interrupts) @[dec_tlu_ctl.scala 748:47] + node _T_680 = and(ext_int_ready, _T_679) @[dec_tlu_ctl.scala 748:45] + take_ext_int_start <= _T_680 @[dec_tlu_ctl.scala 748:28] + node _T_681 = or(take_ext_int_start, take_ext_int_start_d1) @[dec_tlu_ctl.scala 750:46] + node _T_682 = or(_T_681, take_ext_int_start_d2) @[dec_tlu_ctl.scala 750:70] + node _T_683 = or(_T_682, take_ext_int_start_d3) @[dec_tlu_ctl.scala 750:94] + ext_int_freeze <= _T_683 @[dec_tlu_ctl.scala 750:24] + node _T_684 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 751:67] + node _T_685 = not(_T_684) @[dec_tlu_ctl.scala 751:49] + node _T_686 = and(take_ext_int_start_d3, _T_685) @[dec_tlu_ctl.scala 751:47] + take_ext_int <= _T_686 @[dec_tlu_ctl.scala 751:22] + node _T_687 = and(csr_pkt.csr_meicpct, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 752:49] + fast_int_meicpct <= _T_687 @[dec_tlu_ctl.scala 752:26] + ignore_ext_int_due_to_lsu_stall <= io.lsu_fastint_stall_any @[dec_tlu_ctl.scala 753:41] + node _T_688 = not(ext_int_ready) @[dec_tlu_ctl.scala 766:35] + node _T_689 = and(ce_int_ready, _T_688) @[dec_tlu_ctl.scala 766:33] + node _T_690 = not(block_interrupts) @[dec_tlu_ctl.scala 766:52] + node _T_691 = and(_T_689, _T_690) @[dec_tlu_ctl.scala 766:50] + take_ce_int <= _T_691 @[dec_tlu_ctl.scala 766:17] + node _T_692 = not(ext_int_ready) @[dec_tlu_ctl.scala 767:38] + node _T_693 = and(soft_int_ready, _T_692) @[dec_tlu_ctl.scala 767:36] + node _T_694 = not(ce_int_ready) @[dec_tlu_ctl.scala 767:55] + node _T_695 = and(_T_693, _T_694) @[dec_tlu_ctl.scala 767:53] + node _T_696 = not(block_interrupts) @[dec_tlu_ctl.scala 767:71] + node _T_697 = and(_T_695, _T_696) @[dec_tlu_ctl.scala 767:69] + take_soft_int <= _T_697 @[dec_tlu_ctl.scala 767:18] + node _T_698 = not(soft_int_ready) @[dec_tlu_ctl.scala 768:40] + node _T_699 = and(timer_int_ready, _T_698) @[dec_tlu_ctl.scala 768:38] + node _T_700 = not(ext_int_ready) @[dec_tlu_ctl.scala 768:58] + node _T_701 = and(_T_699, _T_700) @[dec_tlu_ctl.scala 768:56] + node _T_702 = not(ce_int_ready) @[dec_tlu_ctl.scala 768:75] + node _T_703 = and(_T_701, _T_702) @[dec_tlu_ctl.scala 768:73] + node _T_704 = not(block_interrupts) @[dec_tlu_ctl.scala 768:91] + node _T_705 = and(_T_703, _T_704) @[dec_tlu_ctl.scala 768:89] + take_timer_int <= _T_705 @[dec_tlu_ctl.scala 768:19] + node _T_706 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 769:49] + node _T_707 = and(_T_706, int_timer0_int_possible) @[dec_tlu_ctl.scala 769:74] + node _T_708 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 769:102] + node _T_709 = and(_T_707, _T_708) @[dec_tlu_ctl.scala 769:100] + node _T_710 = not(timer_int_ready) @[dec_tlu_ctl.scala 769:129] + node _T_711 = and(_T_709, _T_710) @[dec_tlu_ctl.scala 769:127] + node _T_712 = not(soft_int_ready) @[dec_tlu_ctl.scala 769:148] + node _T_713 = and(_T_711, _T_712) @[dec_tlu_ctl.scala 769:146] + node _T_714 = not(ext_int_ready) @[dec_tlu_ctl.scala 769:166] + node _T_715 = and(_T_713, _T_714) @[dec_tlu_ctl.scala 769:164] + node _T_716 = not(ce_int_ready) @[dec_tlu_ctl.scala 769:183] + node _T_717 = and(_T_715, _T_716) @[dec_tlu_ctl.scala 769:181] + node _T_718 = not(block_interrupts) @[dec_tlu_ctl.scala 769:199] + node _T_719 = and(_T_717, _T_718) @[dec_tlu_ctl.scala 769:197] + take_int_timer0_int <= _T_719 @[dec_tlu_ctl.scala 769:24] + node _T_720 = or(int_timer1_int_ready, int_timer1_int_hold_f) @[dec_tlu_ctl.scala 770:49] + node _T_721 = and(_T_720, int_timer1_int_possible) @[dec_tlu_ctl.scala 770:74] + node _T_722 = not(io.dec_csr_stall_int_ff) @[dec_tlu_ctl.scala 770:102] + node _T_723 = and(_T_721, _T_722) @[dec_tlu_ctl.scala 770:100] + node _T_724 = or(int_timer0_int_ready, int_timer0_int_hold_f) @[dec_tlu_ctl.scala 770:152] + node _T_725 = not(_T_724) @[dec_tlu_ctl.scala 770:129] + node _T_726 = and(_T_723, _T_725) @[dec_tlu_ctl.scala 770:127] + node _T_727 = not(timer_int_ready) @[dec_tlu_ctl.scala 770:179] + node _T_728 = and(_T_726, _T_727) @[dec_tlu_ctl.scala 770:177] + node _T_729 = not(soft_int_ready) @[dec_tlu_ctl.scala 770:198] + node _T_730 = and(_T_728, _T_729) @[dec_tlu_ctl.scala 770:196] + node _T_731 = not(ext_int_ready) @[dec_tlu_ctl.scala 770:216] + node _T_732 = and(_T_730, _T_731) @[dec_tlu_ctl.scala 770:214] + node _T_733 = not(ce_int_ready) @[dec_tlu_ctl.scala 770:233] + node _T_734 = and(_T_732, _T_733) @[dec_tlu_ctl.scala 770:231] + node _T_735 = not(block_interrupts) @[dec_tlu_ctl.scala 770:249] + node _T_736 = and(_T_734, _T_735) @[dec_tlu_ctl.scala 770:247] + take_int_timer1_int <= _T_736 @[dec_tlu_ctl.scala 770:24] + node _T_737 = and(reset_delayed, io.mpc_reset_run_req) @[dec_tlu_ctl.scala 771:32] + take_reset <= _T_737 @[dec_tlu_ctl.scala 771:15] + node _T_738 = not(internal_pmu_fw_halt_mode) @[dec_tlu_ctl.scala 772:35] + node _T_739 = and(nmi_int_detected, _T_738) @[dec_tlu_ctl.scala 772:33] + node _T_740 = not(internal_dbg_halt_mode) @[dec_tlu_ctl.scala 772:65] + node _T_741 = bits(dcsr, 11, 11) @[dec_tlu_ctl.scala 772:125] + node _T_742 = and(dcsr_single_step_running_f, _T_741) @[dec_tlu_ctl.scala 772:119] + node _T_743 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 772:141] + node _T_744 = and(_T_742, _T_743) @[dec_tlu_ctl.scala 772:139] + node _T_745 = not(dcsr_single_step_done_f) @[dec_tlu_ctl.scala 772:166] + node _T_746 = and(_T_744, _T_745) @[dec_tlu_ctl.scala 772:164] + node _T_747 = or(_T_740, _T_746) @[dec_tlu_ctl.scala 772:89] + node _T_748 = and(_T_739, _T_747) @[dec_tlu_ctl.scala 772:62] + node _T_749 = not(synchronous_flush_r) @[dec_tlu_ctl.scala 772:195] + node _T_750 = and(_T_748, _T_749) @[dec_tlu_ctl.scala 772:193] + node _T_751 = not(mret_r) @[dec_tlu_ctl.scala 772:218] + node _T_752 = and(_T_750, _T_751) @[dec_tlu_ctl.scala 772:216] + node _T_753 = not(take_reset) @[dec_tlu_ctl.scala 772:228] + node _T_754 = and(_T_752, _T_753) @[dec_tlu_ctl.scala 772:226] + node _T_755 = not(ebreak_to_debug_mode_r) @[dec_tlu_ctl.scala 772:242] + node _T_756 = and(_T_754, _T_755) @[dec_tlu_ctl.scala 772:240] + node _T_757 = not(ext_int_freeze_d1) @[dec_tlu_ctl.scala 772:269] + node _T_758 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 772:332] + node _T_759 = and(take_ext_int_start_d3, _T_758) @[dec_tlu_ctl.scala 772:313] + node _T_760 = or(_T_757, _T_759) @[dec_tlu_ctl.scala 772:288] + node _T_761 = and(_T_756, _T_760) @[dec_tlu_ctl.scala 772:266] + take_nmi <= _T_761 @[dec_tlu_ctl.scala 772:13] + node _T_762 = or(take_ext_int, take_timer_int) @[dec_tlu_ctl.scala 775:38] + node _T_763 = or(_T_762, take_soft_int) @[dec_tlu_ctl.scala 775:55] + node _T_764 = or(_T_763, take_nmi) @[dec_tlu_ctl.scala 775:71] + node _T_765 = or(_T_764, take_ce_int) @[dec_tlu_ctl.scala 775:82] + node _T_766 = or(_T_765, take_int_timer0_int) @[dec_tlu_ctl.scala 775:96] + node _T_767 = or(_T_766, take_int_timer1_int) @[dec_tlu_ctl.scala 775:118] + interrupt_valid_r <= _T_767 @[dec_tlu_ctl.scala 775:22] + node _T_768 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 780:34] node _T_769 = cat(_T_768, UInt<1>("h00")) @[Cat.scala 29:58] node _T_770 = cat(UInt<25>("h00"), exc_cause_r) @[Cat.scala 29:58] node _T_771 = cat(_T_770, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_772 = add(_T_769, _T_771) @[dec_tlu_ctl.scala 784:51] - node vectored_path = tail(_T_772, 1) @[dec_tlu_ctl.scala 784:51] - node _T_773 = bits(take_nmi, 0, 0) @[dec_tlu_ctl.scala 785:38] - node _T_774 = bits(mtvec, 0, 0) @[dec_tlu_ctl.scala 785:67] - node _T_775 = eq(_T_774, UInt<1>("h01")) @[dec_tlu_ctl.scala 785:71] - node _T_776 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 785:104] + node _T_772 = add(_T_769, _T_771) @[dec_tlu_ctl.scala 780:51] + node vectored_path = tail(_T_772, 1) @[dec_tlu_ctl.scala 780:51] + node _T_773 = bits(take_nmi, 0, 0) @[dec_tlu_ctl.scala 781:38] + node _T_774 = bits(mtvec, 0, 0) @[dec_tlu_ctl.scala 781:67] + node _T_775 = eq(_T_774, UInt<1>("h01")) @[dec_tlu_ctl.scala 781:71] + node _T_776 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 781:104] node _T_777 = cat(_T_776, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_778 = mux(_T_775, vectored_path, _T_777) @[dec_tlu_ctl.scala 785:61] - node interrupt_path = mux(_T_773, io.nmi_vec, _T_778) @[dec_tlu_ctl.scala 785:28] - node _T_779 = or(lsu_i0_rfnpc_r, fence_i_r) @[dec_tlu_ctl.scala 786:36] - node _T_780 = or(_T_779, iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 786:48] - node _T_781 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 786:96] - node _T_782 = and(i_cpu_run_req_d1, _T_781) @[dec_tlu_ctl.scala 786:94] - node _T_783 = or(_T_780, _T_782) @[dec_tlu_ctl.scala 786:74] - node _T_784 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 786:131] - node _T_785 = and(rfpc_i0_r, _T_784) @[dec_tlu_ctl.scala 786:129] - node sel_npc_r = or(_T_783, _T_785) @[dec_tlu_ctl.scala 786:116] - node _T_786 = and(i_cpu_run_req_d1, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 787:43] - node sel_npc_resume = or(_T_786, pause_expired_r) @[dec_tlu_ctl.scala 787:66] - node _T_787 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 788:65] - node _T_788 = not(_T_787) @[dec_tlu_ctl.scala 788:47] - node sel_fir_addr = and(take_ext_int_start_d3, _T_788) @[dec_tlu_ctl.scala 788:45] - node _T_789 = or(i0_exception_valid_r, rfpc_i0_r) @[dec_tlu_ctl.scala 789:49] - node _T_790 = or(_T_789, lsu_exc_valid_r) @[dec_tlu_ctl.scala 789:61] - node _T_791 = or(_T_790, fence_i_r) @[dec_tlu_ctl.scala 789:79] - node _T_792 = or(_T_791, lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 789:91] - node _T_793 = or(_T_792, iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 789:108] - node _T_794 = or(_T_793, debug_resume_req_f) @[dec_tlu_ctl.scala 789:135] - node _T_795 = or(_T_794, sel_npc_resume) @[dec_tlu_ctl.scala 789:157] - node _T_796 = or(_T_795, dec_tlu_wr_pause_r_d1) @[dec_tlu_ctl.scala 789:175] - node _T_797 = or(_T_796, i0_trigger_hit_r) @[dec_tlu_ctl.scala 789:201] - synchronous_flush_r <= _T_797 @[dec_tlu_ctl.scala 789:25] - node _T_798 = or(interrupt_valid_r, mret_r) @[dec_tlu_ctl.scala 790:43] - node _T_799 = or(_T_798, synchronous_flush_r) @[dec_tlu_ctl.scala 790:52] - node _T_800 = or(_T_799, take_halt) @[dec_tlu_ctl.scala 790:74] - node _T_801 = or(_T_800, take_reset) @[dec_tlu_ctl.scala 790:86] - node _T_802 = or(_T_801, take_ext_int_start) @[dec_tlu_ctl.scala 790:99] - tlu_flush_lower_r <= _T_802 @[dec_tlu_ctl.scala 790:22] - node _T_803 = bits(take_reset, 0, 0) @[dec_tlu_ctl.scala 792:42] - node _T_804 = bits(sel_fir_addr, 0, 0) @[dec_tlu_ctl.scala 793:72] - node _T_805 = eq(take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 794:66] - node _T_806 = eq(sel_npc_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 794:84] - node _T_807 = and(_T_805, _T_806) @[dec_tlu_ctl.scala 794:73] - node _T_808 = eq(take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 795:66] - node _T_809 = eq(rfpc_i0_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 795:84] - node _T_810 = and(_T_808, _T_809) @[dec_tlu_ctl.scala 795:73] - node _T_811 = eq(io.dec_tlu_i0_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 795:114] - node _T_812 = and(_T_810, _T_811) @[dec_tlu_ctl.scala 795:91] - node _T_813 = eq(sel_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 795:132] - node _T_814 = and(_T_812, _T_813) @[dec_tlu_ctl.scala 795:121] - node _T_815 = eq(interrupt_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 796:75] - node _T_816 = eq(sel_fir_addr, UInt<1>("h00")) @[dec_tlu_ctl.scala 796:96] - node _T_817 = and(_T_815, _T_816) @[dec_tlu_ctl.scala 796:82] - node _T_818 = or(i0_exception_valid_r, lsu_exc_valid_r) @[dec_tlu_ctl.scala 797:80] - node _T_819 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 797:120] - node _T_820 = and(i0_trigger_hit_r, _T_819) @[dec_tlu_ctl.scala 797:118] - node _T_821 = or(_T_818, _T_820) @[dec_tlu_ctl.scala 797:98] - node _T_822 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 797:145] - node _T_823 = and(_T_821, _T_822) @[dec_tlu_ctl.scala 797:143] - node _T_824 = not(sel_fir_addr) @[dec_tlu_ctl.scala 797:166] - node _T_825 = and(_T_823, _T_824) @[dec_tlu_ctl.scala 797:164] - node _T_826 = bits(_T_825, 0, 0) @[dec_tlu_ctl.scala 797:181] - node _T_827 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 797:205] + node _T_778 = mux(_T_775, vectored_path, _T_777) @[dec_tlu_ctl.scala 781:61] + node interrupt_path = mux(_T_773, io.nmi_vec, _T_778) @[dec_tlu_ctl.scala 781:28] + node _T_779 = or(lsu_i0_rfnpc_r, fence_i_r) @[dec_tlu_ctl.scala 782:36] + node _T_780 = or(_T_779, iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 782:48] + node _T_781 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 782:96] + node _T_782 = and(i_cpu_run_req_d1, _T_781) @[dec_tlu_ctl.scala 782:94] + node _T_783 = or(_T_780, _T_782) @[dec_tlu_ctl.scala 782:74] + node _T_784 = not(io.dec_tlu_i0_valid_r) @[dec_tlu_ctl.scala 782:131] + node _T_785 = and(rfpc_i0_r, _T_784) @[dec_tlu_ctl.scala 782:129] + node sel_npc_r = or(_T_783, _T_785) @[dec_tlu_ctl.scala 782:116] + node _T_786 = and(i_cpu_run_req_d1, pmu_fw_tlu_halted_f) @[dec_tlu_ctl.scala 783:43] + node sel_npc_resume = or(_T_786, pause_expired_r) @[dec_tlu_ctl.scala 783:66] + node _T_787 = orr(io.lsu_fir_error) @[dec_tlu_ctl.scala 784:65] + node _T_788 = not(_T_787) @[dec_tlu_ctl.scala 784:47] + node sel_fir_addr = and(take_ext_int_start_d3, _T_788) @[dec_tlu_ctl.scala 784:45] + node _T_789 = or(i0_exception_valid_r, rfpc_i0_r) @[dec_tlu_ctl.scala 785:49] + node _T_790 = or(_T_789, lsu_exc_valid_r) @[dec_tlu_ctl.scala 785:61] + node _T_791 = or(_T_790, fence_i_r) @[dec_tlu_ctl.scala 785:79] + node _T_792 = or(_T_791, lsu_i0_rfnpc_r) @[dec_tlu_ctl.scala 785:91] + node _T_793 = or(_T_792, iccm_repair_state_rfnpc) @[dec_tlu_ctl.scala 785:108] + node _T_794 = or(_T_793, debug_resume_req_f) @[dec_tlu_ctl.scala 785:135] + node _T_795 = or(_T_794, sel_npc_resume) @[dec_tlu_ctl.scala 785:157] + node _T_796 = or(_T_795, dec_tlu_wr_pause_r_d1) @[dec_tlu_ctl.scala 785:175] + node _T_797 = or(_T_796, i0_trigger_hit_r) @[dec_tlu_ctl.scala 785:201] + synchronous_flush_r <= _T_797 @[dec_tlu_ctl.scala 785:25] + node _T_798 = or(interrupt_valid_r, mret_r) @[dec_tlu_ctl.scala 786:43] + node _T_799 = or(_T_798, synchronous_flush_r) @[dec_tlu_ctl.scala 786:52] + node _T_800 = or(_T_799, take_halt) @[dec_tlu_ctl.scala 786:74] + node _T_801 = or(_T_800, take_reset) @[dec_tlu_ctl.scala 786:86] + node _T_802 = or(_T_801, take_ext_int_start) @[dec_tlu_ctl.scala 786:99] + tlu_flush_lower_r <= _T_802 @[dec_tlu_ctl.scala 786:22] + node _T_803 = bits(take_reset, 0, 0) @[dec_tlu_ctl.scala 788:42] + node _T_804 = bits(sel_fir_addr, 0, 0) @[dec_tlu_ctl.scala 789:72] + node _T_805 = eq(take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 790:66] + node _T_806 = eq(sel_npc_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 790:84] + node _T_807 = and(_T_805, _T_806) @[dec_tlu_ctl.scala 790:73] + node _T_808 = eq(take_nmi, UInt<1>("h00")) @[dec_tlu_ctl.scala 791:66] + node _T_809 = eq(rfpc_i0_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 791:84] + node _T_810 = and(_T_808, _T_809) @[dec_tlu_ctl.scala 791:73] + node _T_811 = eq(io.dec_tlu_i0_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 791:114] + node _T_812 = and(_T_810, _T_811) @[dec_tlu_ctl.scala 791:91] + node _T_813 = eq(sel_npc_r, UInt<1>("h00")) @[dec_tlu_ctl.scala 791:132] + node _T_814 = and(_T_812, _T_813) @[dec_tlu_ctl.scala 791:121] + node _T_815 = eq(interrupt_valid_r, UInt<1>("h01")) @[dec_tlu_ctl.scala 792:75] + node _T_816 = eq(sel_fir_addr, UInt<1>("h00")) @[dec_tlu_ctl.scala 792:96] + node _T_817 = and(_T_815, _T_816) @[dec_tlu_ctl.scala 792:82] + node _T_818 = or(i0_exception_valid_r, lsu_exc_valid_r) @[dec_tlu_ctl.scala 793:80] + node _T_819 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 793:120] + node _T_820 = and(i0_trigger_hit_r, _T_819) @[dec_tlu_ctl.scala 793:118] + node _T_821 = or(_T_818, _T_820) @[dec_tlu_ctl.scala 793:98] + node _T_822 = not(interrupt_valid_r) @[dec_tlu_ctl.scala 793:145] + node _T_823 = and(_T_821, _T_822) @[dec_tlu_ctl.scala 793:143] + node _T_824 = not(sel_fir_addr) @[dec_tlu_ctl.scala 793:166] + node _T_825 = and(_T_823, _T_824) @[dec_tlu_ctl.scala 793:164] + node _T_826 = bits(_T_825, 0, 0) @[dec_tlu_ctl.scala 793:181] + node _T_827 = bits(mtvec, 30, 1) @[dec_tlu_ctl.scala 793:205] node _T_828 = cat(_T_827, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_829 = not(take_nmi) @[dec_tlu_ctl.scala 798:58] - node _T_830 = and(_T_829, mret_r) @[dec_tlu_ctl.scala 798:68] - node _T_831 = bits(_T_830, 0, 0) @[dec_tlu_ctl.scala 798:78] - node _T_832 = not(take_nmi) @[dec_tlu_ctl.scala 799:58] - node _T_833 = and(_T_832, debug_resume_req_f) @[dec_tlu_ctl.scala 799:68] - node _T_834 = bits(_T_833, 0, 0) @[dec_tlu_ctl.scala 799:90] - node _T_835 = not(take_nmi) @[dec_tlu_ctl.scala 800:58] - node _T_836 = and(_T_835, sel_npc_resume) @[dec_tlu_ctl.scala 800:68] - node _T_837 = bits(_T_836, 0, 0) @[dec_tlu_ctl.scala 800:86] + node _T_829 = not(take_nmi) @[dec_tlu_ctl.scala 794:58] + node _T_830 = and(_T_829, mret_r) @[dec_tlu_ctl.scala 794:68] + node _T_831 = bits(_T_830, 0, 0) @[dec_tlu_ctl.scala 794:78] + node _T_832 = not(take_nmi) @[dec_tlu_ctl.scala 795:58] + node _T_833 = and(_T_832, debug_resume_req_f) @[dec_tlu_ctl.scala 795:68] + node _T_834 = bits(_T_833, 0, 0) @[dec_tlu_ctl.scala 795:90] + node _T_835 = not(take_nmi) @[dec_tlu_ctl.scala 796:58] + node _T_836 = and(_T_835, sel_npc_resume) @[dec_tlu_ctl.scala 796:68] + node _T_837 = bits(_T_836, 0, 0) @[dec_tlu_ctl.scala 796:86] node _T_838 = mux(_T_804, io.lsu_fir_addr, UInt<1>("h00")) @[Mux.scala 27:72] node _T_839 = mux(_T_807, npc_r, UInt<1>("h00")) @[Mux.scala 27:72] node _T_840 = mux(_T_814, io.dec_tlu_i0_pc_r, UInt<1>("h00")) @[Mux.scala 27:72] @@ -79267,462 +79267,461 @@ circuit quasar_wrapper : node _T_852 = or(_T_851, _T_845) @[Mux.scala 27:72] wire _T_853 : UInt<31> @[Mux.scala 27:72] _T_853 <= _T_852 @[Mux.scala 27:72] - node tlu_flush_path_r = mux(_T_803, io.rst_vec, _T_853) @[dec_tlu_ctl.scala 792:30] - reg tlu_flush_path_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 803:64] - tlu_flush_path_r_d1 <= tlu_flush_path_r @[dec_tlu_ctl.scala 803:64] - io.tlu_bp.dec_tlu_flush_lower_wb <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 805:49] - io.tlu_mem.dec_tlu_flush_lower_wb <= io.tlu_bp.dec_tlu_flush_lower_wb @[dec_tlu_ctl.scala 806:41] - io.tlu_exu.dec_tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 807:49] - io.tlu_exu.dec_tlu_flush_path_r <= tlu_flush_path_r @[dec_tlu_ctl.scala 808:49] - node _T_854 = or(lsu_exc_valid_r, i0_exception_valid_r) @[dec_tlu_ctl.scala 811:45] - node _T_855 = or(_T_854, interrupt_valid_r) @[dec_tlu_ctl.scala 811:68] - node _T_856 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 811:110] - node _T_857 = and(i0_trigger_hit_r, _T_856) @[dec_tlu_ctl.scala 811:108] - node exc_or_int_valid_r = or(_T_855, _T_857) @[dec_tlu_ctl.scala 811:88] - reg _T_858 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 813:90] - _T_858 <= interrupt_valid_r @[dec_tlu_ctl.scala 813:90] - interrupt_valid_r_d1 <= _T_858 @[dec_tlu_ctl.scala 813:57] - reg i0_exception_valid_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 814:89] - i0_exception_valid_r_d1 <= i0_exception_valid_r @[dec_tlu_ctl.scala 814:89] - reg _T_859 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 815:90] - _T_859 <= exc_or_int_valid_r @[dec_tlu_ctl.scala 815:90] - exc_or_int_valid_r_d1 <= _T_859 @[dec_tlu_ctl.scala 815:57] - reg exc_cause_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 816:89] - exc_cause_wb <= exc_cause_r @[dec_tlu_ctl.scala 816:89] - node _T_860 = not(illegal_r) @[dec_tlu_ctl.scala 817:119] - node _T_861 = and(tlu_i0_commit_cmt, _T_860) @[dec_tlu_ctl.scala 817:117] - reg i0_valid_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 817:97] - i0_valid_wb <= _T_861 @[dec_tlu_ctl.scala 817:97] - reg trigger_hit_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 818:89] - trigger_hit_r_d1 <= i0_trigger_hit_r @[dec_tlu_ctl.scala 818:89] - reg _T_862 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 819:98] - _T_862 <= take_nmi @[dec_tlu_ctl.scala 819:98] - take_nmi_r_d1 <= _T_862 @[dec_tlu_ctl.scala 819:65] - reg _T_863 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 820:90] - _T_863 <= pause_expired_r @[dec_tlu_ctl.scala 820:90] - pause_expired_wb <= _T_863 @[dec_tlu_ctl.scala 820:57] - inst csr of csr_tlu @[dec_tlu_ctl.scala 822:15] + node tlu_flush_path_r = mux(_T_803, io.rst_vec, _T_853) @[dec_tlu_ctl.scala 788:30] + reg tlu_flush_path_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 799:64] + tlu_flush_path_r_d1 <= tlu_flush_path_r @[dec_tlu_ctl.scala 799:64] + io.dec_tlu_flush_lower_wb <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 801:41] + io.tlu_exu.dec_tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 803:49] + io.tlu_exu.dec_tlu_flush_path_r <= tlu_flush_path_r @[dec_tlu_ctl.scala 804:49] + node _T_854 = or(lsu_exc_valid_r, i0_exception_valid_r) @[dec_tlu_ctl.scala 807:45] + node _T_855 = or(_T_854, interrupt_valid_r) @[dec_tlu_ctl.scala 807:68] + node _T_856 = not(trigger_hit_dmode_r) @[dec_tlu_ctl.scala 807:110] + node _T_857 = and(i0_trigger_hit_r, _T_856) @[dec_tlu_ctl.scala 807:108] + node exc_or_int_valid_r = or(_T_855, _T_857) @[dec_tlu_ctl.scala 807:88] + reg _T_858 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 809:90] + _T_858 <= interrupt_valid_r @[dec_tlu_ctl.scala 809:90] + interrupt_valid_r_d1 <= _T_858 @[dec_tlu_ctl.scala 809:57] + reg i0_exception_valid_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 810:89] + i0_exception_valid_r_d1 <= i0_exception_valid_r @[dec_tlu_ctl.scala 810:89] + reg _T_859 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 811:90] + _T_859 <= exc_or_int_valid_r @[dec_tlu_ctl.scala 811:90] + exc_or_int_valid_r_d1 <= _T_859 @[dec_tlu_ctl.scala 811:57] + reg exc_cause_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 812:89] + exc_cause_wb <= exc_cause_r @[dec_tlu_ctl.scala 812:89] + node _T_860 = not(illegal_r) @[dec_tlu_ctl.scala 813:119] + node _T_861 = and(tlu_i0_commit_cmt, _T_860) @[dec_tlu_ctl.scala 813:117] + reg i0_valid_wb : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 813:97] + i0_valid_wb <= _T_861 @[dec_tlu_ctl.scala 813:97] + reg trigger_hit_r_d1 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 814:89] + trigger_hit_r_d1 <= i0_trigger_hit_r @[dec_tlu_ctl.scala 814:89] + reg _T_862 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 815:98] + _T_862 <= take_nmi @[dec_tlu_ctl.scala 815:98] + take_nmi_r_d1 <= _T_862 @[dec_tlu_ctl.scala 815:65] + reg _T_863 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[dec_tlu_ctl.scala 816:90] + _T_863 <= pause_expired_r @[dec_tlu_ctl.scala 816:90] + pause_expired_wb <= _T_863 @[dec_tlu_ctl.scala 816:57] + inst csr of csr_tlu @[dec_tlu_ctl.scala 818:15] csr.clock <= clock csr.reset <= reset - csr.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 823:44] - csr.io.active_clk <= io.active_clk @[dec_tlu_ctl.scala 824:44] - csr.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 825:44] - csr.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 826:44] - csr.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 827:44] - csr.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 828:44] - csr.io.dec_csr_wen_unq_d <= io.dec_csr_wen_unq_d @[dec_tlu_ctl.scala 829:44] - csr.io.dec_i0_decode_d <= io.dec_i0_decode_d @[dec_tlu_ctl.scala 830:44] - csr.io.ifu_ic_debug_rd_data_valid <= io.tlu_mem.ifu_ic_debug_rd_data_valid @[dec_tlu_ctl.scala 831:44] - csr.io.ifu_pmu_bus_trxn <= io.tlu_mem.ifu_pmu_bus_trxn @[dec_tlu_ctl.scala 832:44] - csr.io.dma_iccm_stall_any <= io.dma_iccm_stall_any @[dec_tlu_ctl.scala 833:44] - csr.io.dma_dccm_stall_any <= io.dma_dccm_stall_any @[dec_tlu_ctl.scala 834:44] - csr.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec_tlu_ctl.scala 835:44] - csr.io.dec_pmu_presync_stall <= io.dec_pmu_presync_stall @[dec_tlu_ctl.scala 836:44] - csr.io.dec_pmu_postsync_stall <= io.dec_pmu_postsync_stall @[dec_tlu_ctl.scala 837:44] - csr.io.dec_pmu_decode_stall <= io.dec_pmu_decode_stall @[dec_tlu_ctl.scala 838:44] - csr.io.ifu_pmu_fetch_stall <= io.tlu_ifc.ifu_pmu_fetch_stall @[dec_tlu_ctl.scala 839:44] - csr.io.dec_tlu_packet_r.pmu_lsu_misaligned <= io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec_tlu_ctl.scala 840:44] - csr.io.dec_tlu_packet_r.pmu_divide <= io.dec_tlu_packet_r.pmu_divide @[dec_tlu_ctl.scala 840:44] - csr.io.dec_tlu_packet_r.pmu_i0_br_unpred <= io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec_tlu_ctl.scala 840:44] - csr.io.dec_tlu_packet_r.pmu_i0_itype <= io.dec_tlu_packet_r.pmu_i0_itype @[dec_tlu_ctl.scala 840:44] - csr.io.dec_tlu_packet_r.i0trigger <= io.dec_tlu_packet_r.i0trigger @[dec_tlu_ctl.scala 840:44] - csr.io.dec_tlu_packet_r.fence_i <= io.dec_tlu_packet_r.fence_i @[dec_tlu_ctl.scala 840:44] - csr.io.dec_tlu_packet_r.icaf_type <= io.dec_tlu_packet_r.icaf_type @[dec_tlu_ctl.scala 840:44] - csr.io.dec_tlu_packet_r.icaf_f1 <= io.dec_tlu_packet_r.icaf_f1 @[dec_tlu_ctl.scala 840:44] - csr.io.dec_tlu_packet_r.icaf <= io.dec_tlu_packet_r.icaf @[dec_tlu_ctl.scala 840:44] - csr.io.dec_tlu_packet_r.legal <= io.dec_tlu_packet_r.legal @[dec_tlu_ctl.scala 840:44] - csr.io.exu_pmu_i0_br_ataken <= io.tlu_exu.exu_pmu_i0_br_ataken @[dec_tlu_ctl.scala 841:44] - csr.io.exu_pmu_i0_br_misp <= io.tlu_exu.exu_pmu_i0_br_misp @[dec_tlu_ctl.scala 842:44] - csr.io.dec_pmu_instr_decoded <= io.dec_pmu_instr_decoded @[dec_tlu_ctl.scala 843:44] - csr.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[dec_tlu_ctl.scala 844:44] - csr.io.exu_pmu_i0_pc4 <= io.tlu_exu.exu_pmu_i0_pc4 @[dec_tlu_ctl.scala 845:44] - csr.io.ifu_pmu_ic_miss <= io.tlu_mem.ifu_pmu_ic_miss @[dec_tlu_ctl.scala 846:44] - csr.io.ifu_pmu_ic_hit <= io.tlu_mem.ifu_pmu_ic_hit @[dec_tlu_ctl.scala 847:44] - csr.io.dec_csr_wen_r <= io.dec_csr_wen_r @[dec_tlu_ctl.scala 848:44] - csr.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[dec_tlu_ctl.scala 849:44] - csr.io.dma_pmu_dccm_write <= io.dma_pmu_dccm_write @[dec_tlu_ctl.scala 850:44] - csr.io.dma_pmu_dccm_read <= io.dma_pmu_dccm_read @[dec_tlu_ctl.scala 851:44] - csr.io.dma_pmu_any_write <= io.dma_pmu_any_write @[dec_tlu_ctl.scala 852:44] - csr.io.dma_pmu_any_read <= io.dma_pmu_any_read @[dec_tlu_ctl.scala 853:44] - csr.io.lsu_pmu_bus_busy <= io.tlu_busbuff.lsu_pmu_bus_busy @[dec_tlu_ctl.scala 854:44] - csr.io.dec_tlu_i0_pc_r <= io.dec_tlu_i0_pc_r @[dec_tlu_ctl.scala 855:44] - csr.io.dec_tlu_i0_valid_r <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 856:44] - csr.io.dec_csr_stall_int_ff <= io.dec_csr_stall_int_ff @[dec_tlu_ctl.scala 857:44] - csr.io.dec_csr_any_unq_d <= io.dec_csr_any_unq_d @[dec_tlu_ctl.scala 858:44] - csr.io.ifu_pmu_bus_busy <= io.tlu_mem.ifu_pmu_bus_busy @[dec_tlu_ctl.scala 859:44] - csr.io.lsu_pmu_bus_error <= io.tlu_busbuff.lsu_pmu_bus_error @[dec_tlu_ctl.scala 860:44] - csr.io.ifu_pmu_bus_error <= io.tlu_mem.ifu_pmu_bus_error @[dec_tlu_ctl.scala 861:44] - csr.io.lsu_pmu_bus_misaligned <= io.tlu_busbuff.lsu_pmu_bus_misaligned @[dec_tlu_ctl.scala 862:44] - csr.io.lsu_pmu_bus_trxn <= io.tlu_busbuff.lsu_pmu_bus_trxn @[dec_tlu_ctl.scala 863:44] - csr.io.ifu_ic_debug_rd_data <= io.tlu_mem.ifu_ic_debug_rd_data @[dec_tlu_ctl.scala 864:44] - csr.io.pic_pl <= io.pic_pl @[dec_tlu_ctl.scala 865:44] - csr.io.pic_claimid <= io.pic_claimid @[dec_tlu_ctl.scala 866:44] - csr.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[dec_tlu_ctl.scala 867:44] - csr.io.lsu_imprecise_error_addr_any <= io.tlu_busbuff.lsu_imprecise_error_addr_any @[dec_tlu_ctl.scala 868:44] - csr.io.lsu_imprecise_error_load_any <= io.tlu_busbuff.lsu_imprecise_error_load_any @[dec_tlu_ctl.scala 869:44] - csr.io.lsu_imprecise_error_store_any <= io.tlu_busbuff.lsu_imprecise_error_store_any @[dec_tlu_ctl.scala 870:44] - csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 871:44] - csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 872:44] - csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 872:44] - csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 872:44] - csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 872:44] - csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 872:44] - csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 872:44] - csr.io.mexintpend <= io.mexintpend @[dec_tlu_ctl.scala 873:44] - csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 874:44] - csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 875:44] - csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 876:44] - csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 877:44] - csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 878:44] - csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 879:44] - io.dec_tlu_meicurpl <= csr.io.dec_tlu_meicurpl @[dec_tlu_ctl.scala 880:44] - io.tlu_exu.dec_tlu_meihap <= csr.io.dec_tlu_meihap @[dec_tlu_ctl.scala 881:52] - io.dec_tlu_meipt <= csr.io.dec_tlu_meipt @[dec_tlu_ctl.scala 882:44] - io.dec_tlu_int_valid_wb1 <= csr.io.dec_tlu_int_valid_wb1 @[dec_tlu_ctl.scala 883:44] - io.dec_tlu_i0_exc_valid_wb1 <= csr.io.dec_tlu_i0_exc_valid_wb1 @[dec_tlu_ctl.scala 884:44] - io.dec_tlu_i0_valid_wb1 <= csr.io.dec_tlu_i0_valid_wb1 @[dec_tlu_ctl.scala 885:44] - io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wr_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[dec_tlu_ctl.scala 886:52] - io.tlu_mem.dec_tlu_ic_diag_pkt.icache_rd_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[dec_tlu_ctl.scala 886:52] - io.tlu_mem.dec_tlu_ic_diag_pkt.icache_dicawics <= csr.io.dec_tlu_ic_diag_pkt.icache_dicawics @[dec_tlu_ctl.scala 886:52] - io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wrdata <= csr.io.dec_tlu_ic_diag_pkt.icache_wrdata @[dec_tlu_ctl.scala 886:52] - io.trigger_pkt_any[0].tdata2 <= csr.io.trigger_pkt_any[0].tdata2 @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[0].m <= csr.io.trigger_pkt_any[0].m @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[0].execute <= csr.io.trigger_pkt_any[0].execute @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[0].load <= csr.io.trigger_pkt_any[0].load @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[0].store <= csr.io.trigger_pkt_any[0].store @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[0].match_pkt <= csr.io.trigger_pkt_any[0].match_pkt @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[0].select <= csr.io.trigger_pkt_any[0].select @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[1].tdata2 <= csr.io.trigger_pkt_any[1].tdata2 @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[1].m <= csr.io.trigger_pkt_any[1].m @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[1].execute <= csr.io.trigger_pkt_any[1].execute @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[1].load <= csr.io.trigger_pkt_any[1].load @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[1].store <= csr.io.trigger_pkt_any[1].store @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[1].match_pkt <= csr.io.trigger_pkt_any[1].match_pkt @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[1].select <= csr.io.trigger_pkt_any[1].select @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[2].tdata2 <= csr.io.trigger_pkt_any[2].tdata2 @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[2].m <= csr.io.trigger_pkt_any[2].m @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[2].execute <= csr.io.trigger_pkt_any[2].execute @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[2].load <= csr.io.trigger_pkt_any[2].load @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[2].store <= csr.io.trigger_pkt_any[2].store @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[2].match_pkt <= csr.io.trigger_pkt_any[2].match_pkt @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[2].select <= csr.io.trigger_pkt_any[2].select @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[3].tdata2 <= csr.io.trigger_pkt_any[3].tdata2 @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[3].m <= csr.io.trigger_pkt_any[3].m @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[3].execute <= csr.io.trigger_pkt_any[3].execute @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[3].load <= csr.io.trigger_pkt_any[3].load @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[3].store <= csr.io.trigger_pkt_any[3].store @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[3].match_pkt <= csr.io.trigger_pkt_any[3].match_pkt @[dec_tlu_ctl.scala 887:40] - io.trigger_pkt_any[3].select <= csr.io.trigger_pkt_any[3].select @[dec_tlu_ctl.scala 887:40] - io.dec_tlu_mtval_wb1 <= csr.io.dec_tlu_mtval_wb1 @[dec_tlu_ctl.scala 888:40] - io.dec_tlu_exc_cause_wb1 <= csr.io.dec_tlu_exc_cause_wb1 @[dec_tlu_ctl.scala 889:40] - io.dec_tlu_perfcnt0 <= csr.io.dec_tlu_perfcnt0 @[dec_tlu_ctl.scala 890:40] - io.dec_tlu_perfcnt1 <= csr.io.dec_tlu_perfcnt1 @[dec_tlu_ctl.scala 891:40] - io.dec_tlu_perfcnt2 <= csr.io.dec_tlu_perfcnt2 @[dec_tlu_ctl.scala 892:40] - io.dec_tlu_perfcnt3 <= csr.io.dec_tlu_perfcnt3 @[dec_tlu_ctl.scala 893:40] - io.dec_tlu_misc_clk_override <= csr.io.dec_tlu_misc_clk_override @[dec_tlu_ctl.scala 894:40] - io.dec_tlu_dec_clk_override <= csr.io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 895:40] - io.dec_tlu_ifu_clk_override <= csr.io.dec_tlu_ifu_clk_override @[dec_tlu_ctl.scala 896:40] - io.dec_tlu_lsu_clk_override <= csr.io.dec_tlu_lsu_clk_override @[dec_tlu_ctl.scala 897:40] - io.dec_tlu_bus_clk_override <= csr.io.dec_tlu_bus_clk_override @[dec_tlu_ctl.scala 898:40] - io.dec_tlu_pic_clk_override <= csr.io.dec_tlu_pic_clk_override @[dec_tlu_ctl.scala 899:40] - io.dec_tlu_dccm_clk_override <= csr.io.dec_tlu_dccm_clk_override @[dec_tlu_ctl.scala 900:40] - io.dec_tlu_icm_clk_override <= csr.io.dec_tlu_icm_clk_override @[dec_tlu_ctl.scala 901:40] - io.dec_csr_rddata_d <= csr.io.dec_csr_rddata_d @[dec_tlu_ctl.scala 902:40] - io.dec_tlu_pipelining_disable <= csr.io.dec_tlu_pipelining_disable @[dec_tlu_ctl.scala 903:40] - io.dec_tlu_wr_pause_r <= csr.io.dec_tlu_wr_pause_r @[dec_tlu_ctl.scala 904:40] - io.tlu_ifc.dec_tlu_mrac_ff <= csr.io.dec_tlu_mrac_ff @[dec_tlu_ctl.scala 905:48] - io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= csr.io.dec_tlu_wb_coalescing_disable @[dec_tlu_ctl.scala 906:52] - io.tlu_bp.dec_tlu_bpred_disable <= csr.io.dec_tlu_bpred_disable @[dec_tlu_ctl.scala 907:47] - io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= csr.io.dec_tlu_sideeffect_posted_disable @[dec_tlu_ctl.scala 908:52] - io.tlu_mem.dec_tlu_core_ecc_disable <= csr.io.dec_tlu_core_ecc_disable @[dec_tlu_ctl.scala 909:48] - io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= csr.io.dec_tlu_external_ldfwd_disable @[dec_tlu_ctl.scala 910:52] - io.dec_tlu_dma_qos_prty <= csr.io.dec_tlu_dma_qos_prty @[dec_tlu_ctl.scala 911:40] - csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 912:44] - csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 913:44] - csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 913:44] - csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 913:44] - csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 913:44] - csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 913:44] - csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 913:44] - csr.io.mexintpend <= io.mexintpend @[dec_tlu_ctl.scala 914:44] - csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 915:44] - csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 916:44] - csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 917:44] - csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 918:44] - csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 919:44] - csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 920:44] - csr.io.rfpc_i0_r <= rfpc_i0_r @[dec_tlu_ctl.scala 923:39] - csr.io.i0_trigger_hit_r <= i0_trigger_hit_r @[dec_tlu_ctl.scala 924:39] - csr.io.exc_or_int_valid_r <= exc_or_int_valid_r @[dec_tlu_ctl.scala 925:39] - csr.io.mret_r <= mret_r @[dec_tlu_ctl.scala 926:39] - csr.io.dcsr_single_step_running_f <= dcsr_single_step_running_f @[dec_tlu_ctl.scala 927:39] - csr.io.dec_timer_t0_pulse <= int_timers.io.dec_timer_t0_pulse @[dec_tlu_ctl.scala 928:39] - csr.io.dec_timer_t1_pulse <= int_timers.io.dec_timer_t1_pulse @[dec_tlu_ctl.scala 929:39] - csr.io.timer_int_sync <= timer_int_sync @[dec_tlu_ctl.scala 930:39] - csr.io.soft_int_sync <= soft_int_sync @[dec_tlu_ctl.scala 931:39] - csr.io.csr_wr_clk <= rvclkhdr.io.l1clk @[dec_tlu_ctl.scala 932:39] - csr.io.ebreak_to_debug_mode_r <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 933:39] - csr.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 934:39] - csr.io.lsu_fir_error <= io.lsu_fir_error @[dec_tlu_ctl.scala 935:39] - csr.io.tlu_flush_lower_r_d1 <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 936:39] - csr.io.dec_tlu_flush_noredir_r_d1 <= dec_tlu_flush_noredir_r_d1 @[dec_tlu_ctl.scala 937:39] - csr.io.tlu_flush_path_r_d1 <= tlu_flush_path_r_d1 @[dec_tlu_ctl.scala 938:39] - csr.io.reset_delayed <= reset_delayed @[dec_tlu_ctl.scala 939:39] - csr.io.interrupt_valid_r <= interrupt_valid_r @[dec_tlu_ctl.scala 940:39] - csr.io.i0_exception_valid_r <= i0_exception_valid_r @[dec_tlu_ctl.scala 941:39] - csr.io.lsu_exc_valid_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 942:39] - csr.io.mepc_trigger_hit_sel_pc_r <= mepc_trigger_hit_sel_pc_r @[dec_tlu_ctl.scala 943:39] - csr.io.e4e5_int_clk <= rvclkhdr_3.io.l1clk @[dec_tlu_ctl.scala 944:39] - csr.io.lsu_i0_exc_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 945:39] - csr.io.inst_acc_r <= inst_acc_r @[dec_tlu_ctl.scala 946:39] - csr.io.inst_acc_second_r <= io.dec_tlu_packet_r.icaf_f1 @[dec_tlu_ctl.scala 947:39] - csr.io.take_nmi <= take_nmi @[dec_tlu_ctl.scala 948:39] - csr.io.lsu_error_pkt_addr_r <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 949:39] - csr.io.exc_cause_r <= exc_cause_r @[dec_tlu_ctl.scala 950:39] - csr.io.i0_valid_wb <= i0_valid_wb @[dec_tlu_ctl.scala 951:39] - csr.io.exc_or_int_valid_r_d1 <= exc_or_int_valid_r_d1 @[dec_tlu_ctl.scala 952:39] - csr.io.interrupt_valid_r_d1 <= interrupt_valid_r_d1 @[dec_tlu_ctl.scala 953:39] - csr.io.clk_override <= io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 954:39] - csr.io.i0_exception_valid_r_d1 <= i0_exception_valid_r_d1 @[dec_tlu_ctl.scala 955:39] - csr.io.lsu_i0_exc_r_d1 <= lsu_i0_exc_r_d1 @[dec_tlu_ctl.scala 956:39] - csr.io.exc_cause_wb <= exc_cause_wb @[dec_tlu_ctl.scala 957:39] - csr.io.nmi_lsu_store_type <= nmi_lsu_store_type @[dec_tlu_ctl.scala 958:39] - csr.io.nmi_lsu_load_type <= nmi_lsu_load_type @[dec_tlu_ctl.scala 959:39] - csr.io.tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 960:39] - csr.io.ebreak_r <= ebreak_r @[dec_tlu_ctl.scala 961:39] - csr.io.ecall_r <= ecall_r @[dec_tlu_ctl.scala 962:39] - csr.io.illegal_r <= illegal_r @[dec_tlu_ctl.scala 963:39] - csr.io.mdseac_locked_f <= mdseac_locked_f @[dec_tlu_ctl.scala 964:39] - csr.io.nmi_int_detected_f <= nmi_int_detected_f @[dec_tlu_ctl.scala 965:39] - csr.io.internal_dbg_halt_mode_f2 <= internal_dbg_halt_mode_f2 @[dec_tlu_ctl.scala 966:39] - csr.io.ext_int_freeze_d1 <= ext_int_freeze_d1 @[dec_tlu_ctl.scala 967:39] - csr.io.ic_perr_r_d1 <= ic_perr_r_d1 @[dec_tlu_ctl.scala 968:39] - csr.io.iccm_sbecc_r_d1 <= iccm_sbecc_r_d1 @[dec_tlu_ctl.scala 969:39] - csr.io.lsu_single_ecc_error_r_d1 <= lsu_single_ecc_error_r_d1 @[dec_tlu_ctl.scala 970:39] - csr.io.ifu_miss_state_idle_f <= ifu_miss_state_idle_f @[dec_tlu_ctl.scala 971:39] - csr.io.lsu_idle_any_f <= lsu_idle_any_f @[dec_tlu_ctl.scala 972:39] - csr.io.dbg_tlu_halted_f <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 973:39] - csr.io.dbg_tlu_halted <= dbg_tlu_halted @[dec_tlu_ctl.scala 974:39] - csr.io.debug_halt_req_f <= debug_halt_req_f @[dec_tlu_ctl.scala 975:51] - csr.io.take_ext_int_start <= take_ext_int_start @[dec_tlu_ctl.scala 976:47] - csr.io.trigger_hit_dmode_r_d1 <= trigger_hit_dmode_r_d1 @[dec_tlu_ctl.scala 977:43] - csr.io.trigger_hit_r_d1 <= trigger_hit_r_d1 @[dec_tlu_ctl.scala 978:43] - csr.io.dcsr_single_step_done_f <= dcsr_single_step_done_f @[dec_tlu_ctl.scala 979:43] - csr.io.ebreak_to_debug_mode_r_d1 <= ebreak_to_debug_mode_r_d1 @[dec_tlu_ctl.scala 980:39] - csr.io.debug_halt_req <= debug_halt_req @[dec_tlu_ctl.scala 981:51] - csr.io.allow_dbg_halt_csr_write <= allow_dbg_halt_csr_write @[dec_tlu_ctl.scala 982:39] - csr.io.internal_dbg_halt_mode_f <= debug_mode_status @[dec_tlu_ctl.scala 983:39] - csr.io.enter_debug_halt_req <= enter_debug_halt_req @[dec_tlu_ctl.scala 984:39] - csr.io.internal_dbg_halt_mode <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 985:39] - csr.io.request_debug_mode_done <= request_debug_mode_done @[dec_tlu_ctl.scala 986:39] - csr.io.request_debug_mode_r <= request_debug_mode_r @[dec_tlu_ctl.scala 987:39] - csr.io.update_hit_bit_r <= update_hit_bit_r @[dec_tlu_ctl.scala 988:39] - csr.io.take_timer_int <= take_timer_int @[dec_tlu_ctl.scala 989:39] - csr.io.take_int_timer0_int <= take_int_timer0_int @[dec_tlu_ctl.scala 990:39] - csr.io.take_int_timer1_int <= take_int_timer1_int @[dec_tlu_ctl.scala 991:39] - csr.io.take_ext_int <= take_ext_int @[dec_tlu_ctl.scala 992:39] - csr.io.tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 993:39] - csr.io.dec_tlu_br0_error_r <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 994:39] - csr.io.dec_tlu_br0_start_error_r <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 995:39] - csr.io.lsu_pmu_load_external_r <= lsu_pmu_load_external_r @[dec_tlu_ctl.scala 996:39] - csr.io.lsu_pmu_store_external_r <= lsu_pmu_store_external_r @[dec_tlu_ctl.scala 997:39] - csr.io.csr_pkt.legal <= csr_pkt.legal @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.postsync <= csr_pkt.postsync @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.presync <= csr_pkt.presync @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_dicago <= csr_pkt.csr_dicago @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_dicad1 <= csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_dicad0 <= csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_dicad0h <= csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_dicawics <= csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mfdhs <= csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mfdht <= csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mdccmect <= csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_miccmect <= csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_micect <= csr_pkt.csr_micect @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mdeau <= csr_pkt.csr_mdeau @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_meicpct <= csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mcpc <= csr_pkt.csr_mcpc @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mpmc <= csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mcountinhibit <= csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mhpme6 <= csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mhpme5 <= csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mhpme4 <= csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mhpme3 <= csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mhpmc6h <= csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mhpmc5h <= csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mhpmc4h <= csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mhpmc3h <= csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mhpmc6 <= csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mhpmc5 <= csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mhpmc4 <= csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mhpmc3 <= csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mtdata2 <= csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mtdata1 <= csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mtsel <= csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_dpc <= csr_pkt.csr_dpc @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mfdc <= csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mcgc <= csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_dcsr <= csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_meicidpl <= csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_meicurpl <= csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_meipt <= csr_pkt.csr_meipt @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_meivt <= csr_pkt.csr_meivt @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_meihap <= csr_pkt.csr_meihap @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mdseac <= csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_dmst <= csr_pkt.csr_dmst @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mrac <= csr_pkt.csr_mrac @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mtval <= csr_pkt.csr_mtval @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mscause <= csr_pkt.csr_mscause @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mcause <= csr_pkt.csr_mcause @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mepc <= csr_pkt.csr_mepc @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mscratch <= csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_minstreth <= csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_minstretl <= csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mcycleh <= csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mcyclel <= csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mie <= csr_pkt.csr_mie @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mip <= csr_pkt.csr_mip @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mtvec <= csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mstatus <= csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mhartid <= csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mimpid <= csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_marchid <= csr_pkt.csr_marchid @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_mvendorid <= csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 998:39] - csr.io.csr_pkt.csr_misa <= csr_pkt.csr_misa @[dec_tlu_ctl.scala 998:39] - npc_r <= csr.io.npc_r @[dec_tlu_ctl.scala 1000:31] - npc_r_d1 <= csr.io.npc_r_d1 @[dec_tlu_ctl.scala 1001:31] - mie_ns <= csr.io.mie_ns @[dec_tlu_ctl.scala 1002:31] - mepc <= csr.io.mepc @[dec_tlu_ctl.scala 1003:31] - mdseac_locked_ns <= csr.io.mdseac_locked_ns @[dec_tlu_ctl.scala 1004:31] - force_halt <= csr.io.force_halt @[dec_tlu_ctl.scala 1005:31] - dpc <= csr.io.dpc @[dec_tlu_ctl.scala 1006:31] - mstatus_mie_ns <= csr.io.mstatus_mie_ns @[dec_tlu_ctl.scala 1007:31] - dec_csr_wen_r_mod <= csr.io.dec_csr_wen_r_mod @[dec_tlu_ctl.scala 1008:31] - fw_halt_req <= csr.io.fw_halt_req @[dec_tlu_ctl.scala 1009:31] - mstatus <= csr.io.mstatus @[dec_tlu_ctl.scala 1010:31] - dcsr <= csr.io.dcsr @[dec_tlu_ctl.scala 1011:31] - mtvec <= csr.io.mtvec @[dec_tlu_ctl.scala 1012:31] - mip <= csr.io.mip @[dec_tlu_ctl.scala 1013:31] - mtdata1_t[0] <= csr.io.mtdata1_t[0] @[dec_tlu_ctl.scala 1014:33] - mtdata1_t[1] <= csr.io.mtdata1_t[1] @[dec_tlu_ctl.scala 1014:33] - mtdata1_t[2] <= csr.io.mtdata1_t[2] @[dec_tlu_ctl.scala 1014:33] - mtdata1_t[3] <= csr.io.mtdata1_t[3] @[dec_tlu_ctl.scala 1014:33] - inst csr_read of dec_decode_csr_read @[dec_tlu_ctl.scala 1015:22] + csr.io.free_clk <= io.free_clk @[dec_tlu_ctl.scala 819:44] + csr.io.active_clk <= io.active_clk @[dec_tlu_ctl.scala 820:44] + csr.io.scan_mode <= io.scan_mode @[dec_tlu_ctl.scala 821:44] + csr.io.dec_csr_wrdata_r <= io.dec_csr_wrdata_r @[dec_tlu_ctl.scala 822:44] + csr.io.dec_csr_wraddr_r <= io.dec_csr_wraddr_r @[dec_tlu_ctl.scala 823:44] + csr.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 824:44] + csr.io.dec_csr_wen_unq_d <= io.dec_csr_wen_unq_d @[dec_tlu_ctl.scala 825:44] + csr.io.dec_i0_decode_d <= io.dec_i0_decode_d @[dec_tlu_ctl.scala 826:44] + csr.io.ifu_ic_debug_rd_data_valid <= io.tlu_mem.ifu_ic_debug_rd_data_valid @[dec_tlu_ctl.scala 827:44] + csr.io.ifu_pmu_bus_trxn <= io.tlu_mem.ifu_pmu_bus_trxn @[dec_tlu_ctl.scala 828:44] + csr.io.dma_iccm_stall_any <= io.tlu_dma.dma_iccm_stall_any @[dec_tlu_ctl.scala 829:44] + csr.io.dma_dccm_stall_any <= io.tlu_dma.dma_dccm_stall_any @[dec_tlu_ctl.scala 830:44] + csr.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec_tlu_ctl.scala 831:44] + csr.io.dec_pmu_presync_stall <= io.dec_pmu_presync_stall @[dec_tlu_ctl.scala 832:44] + csr.io.dec_pmu_postsync_stall <= io.dec_pmu_postsync_stall @[dec_tlu_ctl.scala 833:44] + csr.io.dec_pmu_decode_stall <= io.dec_pmu_decode_stall @[dec_tlu_ctl.scala 834:44] + csr.io.ifu_pmu_fetch_stall <= io.tlu_ifc.ifu_pmu_fetch_stall @[dec_tlu_ctl.scala 835:44] + csr.io.dec_tlu_packet_r.pmu_lsu_misaligned <= io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec_tlu_ctl.scala 836:44] + csr.io.dec_tlu_packet_r.pmu_divide <= io.dec_tlu_packet_r.pmu_divide @[dec_tlu_ctl.scala 836:44] + csr.io.dec_tlu_packet_r.pmu_i0_br_unpred <= io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec_tlu_ctl.scala 836:44] + csr.io.dec_tlu_packet_r.pmu_i0_itype <= io.dec_tlu_packet_r.pmu_i0_itype @[dec_tlu_ctl.scala 836:44] + csr.io.dec_tlu_packet_r.i0trigger <= io.dec_tlu_packet_r.i0trigger @[dec_tlu_ctl.scala 836:44] + csr.io.dec_tlu_packet_r.fence_i <= io.dec_tlu_packet_r.fence_i @[dec_tlu_ctl.scala 836:44] + csr.io.dec_tlu_packet_r.icaf_type <= io.dec_tlu_packet_r.icaf_type @[dec_tlu_ctl.scala 836:44] + csr.io.dec_tlu_packet_r.icaf_f1 <= io.dec_tlu_packet_r.icaf_f1 @[dec_tlu_ctl.scala 836:44] + csr.io.dec_tlu_packet_r.icaf <= io.dec_tlu_packet_r.icaf @[dec_tlu_ctl.scala 836:44] + csr.io.dec_tlu_packet_r.legal <= io.dec_tlu_packet_r.legal @[dec_tlu_ctl.scala 836:44] + csr.io.exu_pmu_i0_br_ataken <= io.tlu_exu.exu_pmu_i0_br_ataken @[dec_tlu_ctl.scala 837:44] + csr.io.exu_pmu_i0_br_misp <= io.tlu_exu.exu_pmu_i0_br_misp @[dec_tlu_ctl.scala 838:44] + csr.io.dec_pmu_instr_decoded <= io.dec_pmu_instr_decoded @[dec_tlu_ctl.scala 839:44] + csr.io.ifu_pmu_instr_aligned <= io.ifu_pmu_instr_aligned @[dec_tlu_ctl.scala 840:44] + csr.io.exu_pmu_i0_pc4 <= io.tlu_exu.exu_pmu_i0_pc4 @[dec_tlu_ctl.scala 841:44] + csr.io.ifu_pmu_ic_miss <= io.tlu_mem.ifu_pmu_ic_miss @[dec_tlu_ctl.scala 842:44] + csr.io.ifu_pmu_ic_hit <= io.tlu_mem.ifu_pmu_ic_hit @[dec_tlu_ctl.scala 843:44] + csr.io.dec_csr_wen_r <= io.dec_csr_wen_r @[dec_tlu_ctl.scala 844:44] + csr.io.dec_tlu_dbg_halted <= io.dec_tlu_dbg_halted @[dec_tlu_ctl.scala 845:44] + csr.io.dma_pmu_dccm_write <= io.tlu_dma.dma_pmu_dccm_write @[dec_tlu_ctl.scala 846:44] + csr.io.dma_pmu_dccm_read <= io.tlu_dma.dma_pmu_dccm_read @[dec_tlu_ctl.scala 847:44] + csr.io.dma_pmu_any_write <= io.tlu_dma.dma_pmu_any_write @[dec_tlu_ctl.scala 848:44] + csr.io.dma_pmu_any_read <= io.tlu_dma.dma_pmu_any_read @[dec_tlu_ctl.scala 849:44] + csr.io.lsu_pmu_bus_busy <= io.tlu_busbuff.lsu_pmu_bus_busy @[dec_tlu_ctl.scala 850:44] + csr.io.dec_tlu_i0_pc_r <= io.dec_tlu_i0_pc_r @[dec_tlu_ctl.scala 851:44] + csr.io.dec_tlu_i0_valid_r <= io.dec_tlu_i0_valid_r @[dec_tlu_ctl.scala 852:44] + csr.io.dec_csr_stall_int_ff <= io.dec_csr_stall_int_ff @[dec_tlu_ctl.scala 853:44] + csr.io.dec_csr_any_unq_d <= io.dec_csr_any_unq_d @[dec_tlu_ctl.scala 854:44] + csr.io.ifu_pmu_bus_busy <= io.tlu_mem.ifu_pmu_bus_busy @[dec_tlu_ctl.scala 855:44] + csr.io.lsu_pmu_bus_error <= io.tlu_busbuff.lsu_pmu_bus_error @[dec_tlu_ctl.scala 856:44] + csr.io.ifu_pmu_bus_error <= io.tlu_mem.ifu_pmu_bus_error @[dec_tlu_ctl.scala 857:44] + csr.io.lsu_pmu_bus_misaligned <= io.tlu_busbuff.lsu_pmu_bus_misaligned @[dec_tlu_ctl.scala 858:44] + csr.io.lsu_pmu_bus_trxn <= io.tlu_busbuff.lsu_pmu_bus_trxn @[dec_tlu_ctl.scala 859:44] + csr.io.ifu_ic_debug_rd_data <= io.tlu_mem.ifu_ic_debug_rd_data @[dec_tlu_ctl.scala 860:44] + csr.io.pic_pl <= io.dec_pic.pic_pl @[dec_tlu_ctl.scala 861:44] + csr.io.pic_claimid <= io.dec_pic.pic_claimid @[dec_tlu_ctl.scala 862:44] + csr.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[dec_tlu_ctl.scala 863:44] + csr.io.lsu_imprecise_error_addr_any <= io.tlu_busbuff.lsu_imprecise_error_addr_any @[dec_tlu_ctl.scala 864:44] + csr.io.lsu_imprecise_error_load_any <= io.tlu_busbuff.lsu_imprecise_error_load_any @[dec_tlu_ctl.scala 865:44] + csr.io.lsu_imprecise_error_store_any <= io.tlu_busbuff.lsu_imprecise_error_store_any @[dec_tlu_ctl.scala 866:44] + csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 867:44] + csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 868:44] + csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 868:44] + csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 868:44] + csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 868:44] + csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 868:44] + csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 868:44] + csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 869:44] + csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 870:44] + csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 871:44] + csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 872:44] + csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 873:44] + csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 874:44] + csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 875:44] + io.dec_pic.dec_tlu_meicurpl <= csr.io.dec_tlu_meicurpl @[dec_tlu_ctl.scala 876:52] + io.tlu_exu.dec_tlu_meihap <= csr.io.dec_tlu_meihap @[dec_tlu_ctl.scala 877:52] + io.dec_pic.dec_tlu_meipt <= csr.io.dec_tlu_meipt @[dec_tlu_ctl.scala 878:52] + io.dec_tlu_int_valid_wb1 <= csr.io.dec_tlu_int_valid_wb1 @[dec_tlu_ctl.scala 879:44] + io.dec_tlu_i0_exc_valid_wb1 <= csr.io.dec_tlu_i0_exc_valid_wb1 @[dec_tlu_ctl.scala 880:44] + io.dec_tlu_i0_valid_wb1 <= csr.io.dec_tlu_i0_valid_wb1 @[dec_tlu_ctl.scala 881:44] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wr_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_wr_valid @[dec_tlu_ctl.scala 882:52] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_rd_valid <= csr.io.dec_tlu_ic_diag_pkt.icache_rd_valid @[dec_tlu_ctl.scala 882:52] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_dicawics <= csr.io.dec_tlu_ic_diag_pkt.icache_dicawics @[dec_tlu_ctl.scala 882:52] + io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wrdata <= csr.io.dec_tlu_ic_diag_pkt.icache_wrdata @[dec_tlu_ctl.scala 882:52] + io.trigger_pkt_any[0].tdata2 <= csr.io.trigger_pkt_any[0].tdata2 @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[0].m <= csr.io.trigger_pkt_any[0].m @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[0].execute <= csr.io.trigger_pkt_any[0].execute @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[0].load <= csr.io.trigger_pkt_any[0].load @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[0].store <= csr.io.trigger_pkt_any[0].store @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[0].match_pkt <= csr.io.trigger_pkt_any[0].match_pkt @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[0].select <= csr.io.trigger_pkt_any[0].select @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[1].tdata2 <= csr.io.trigger_pkt_any[1].tdata2 @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[1].m <= csr.io.trigger_pkt_any[1].m @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[1].execute <= csr.io.trigger_pkt_any[1].execute @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[1].load <= csr.io.trigger_pkt_any[1].load @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[1].store <= csr.io.trigger_pkt_any[1].store @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[1].match_pkt <= csr.io.trigger_pkt_any[1].match_pkt @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[1].select <= csr.io.trigger_pkt_any[1].select @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[2].tdata2 <= csr.io.trigger_pkt_any[2].tdata2 @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[2].m <= csr.io.trigger_pkt_any[2].m @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[2].execute <= csr.io.trigger_pkt_any[2].execute @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[2].load <= csr.io.trigger_pkt_any[2].load @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[2].store <= csr.io.trigger_pkt_any[2].store @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[2].match_pkt <= csr.io.trigger_pkt_any[2].match_pkt @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[2].select <= csr.io.trigger_pkt_any[2].select @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[3].tdata2 <= csr.io.trigger_pkt_any[3].tdata2 @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[3].m <= csr.io.trigger_pkt_any[3].m @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[3].execute <= csr.io.trigger_pkt_any[3].execute @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[3].load <= csr.io.trigger_pkt_any[3].load @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[3].store <= csr.io.trigger_pkt_any[3].store @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[3].match_pkt <= csr.io.trigger_pkt_any[3].match_pkt @[dec_tlu_ctl.scala 883:40] + io.trigger_pkt_any[3].select <= csr.io.trigger_pkt_any[3].select @[dec_tlu_ctl.scala 883:40] + io.dec_tlu_mtval_wb1 <= csr.io.dec_tlu_mtval_wb1 @[dec_tlu_ctl.scala 884:40] + io.dec_tlu_exc_cause_wb1 <= csr.io.dec_tlu_exc_cause_wb1 @[dec_tlu_ctl.scala 885:40] + io.dec_tlu_perfcnt0 <= csr.io.dec_tlu_perfcnt0 @[dec_tlu_ctl.scala 886:40] + io.dec_tlu_perfcnt1 <= csr.io.dec_tlu_perfcnt1 @[dec_tlu_ctl.scala 887:40] + io.dec_tlu_perfcnt2 <= csr.io.dec_tlu_perfcnt2 @[dec_tlu_ctl.scala 888:40] + io.dec_tlu_perfcnt3 <= csr.io.dec_tlu_perfcnt3 @[dec_tlu_ctl.scala 889:40] + io.dec_tlu_misc_clk_override <= csr.io.dec_tlu_misc_clk_override @[dec_tlu_ctl.scala 890:40] + io.dec_tlu_dec_clk_override <= csr.io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 891:40] + io.dec_tlu_ifu_clk_override <= csr.io.dec_tlu_ifu_clk_override @[dec_tlu_ctl.scala 892:40] + io.dec_tlu_lsu_clk_override <= csr.io.dec_tlu_lsu_clk_override @[dec_tlu_ctl.scala 893:40] + io.dec_tlu_bus_clk_override <= csr.io.dec_tlu_bus_clk_override @[dec_tlu_ctl.scala 894:40] + io.dec_tlu_pic_clk_override <= csr.io.dec_tlu_pic_clk_override @[dec_tlu_ctl.scala 895:40] + io.dec_tlu_dccm_clk_override <= csr.io.dec_tlu_dccm_clk_override @[dec_tlu_ctl.scala 896:40] + io.dec_tlu_icm_clk_override <= csr.io.dec_tlu_icm_clk_override @[dec_tlu_ctl.scala 897:40] + io.dec_csr_rddata_d <= csr.io.dec_csr_rddata_d @[dec_tlu_ctl.scala 898:40] + io.dec_tlu_pipelining_disable <= csr.io.dec_tlu_pipelining_disable @[dec_tlu_ctl.scala 899:40] + io.dec_tlu_wr_pause_r <= csr.io.dec_tlu_wr_pause_r @[dec_tlu_ctl.scala 900:40] + io.tlu_ifc.dec_tlu_mrac_ff <= csr.io.dec_tlu_mrac_ff @[dec_tlu_ctl.scala 901:48] + io.tlu_busbuff.dec_tlu_wb_coalescing_disable <= csr.io.dec_tlu_wb_coalescing_disable @[dec_tlu_ctl.scala 902:52] + io.tlu_bp.dec_tlu_bpred_disable <= csr.io.dec_tlu_bpred_disable @[dec_tlu_ctl.scala 903:47] + io.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= csr.io.dec_tlu_sideeffect_posted_disable @[dec_tlu_ctl.scala 904:52] + io.tlu_mem.dec_tlu_core_ecc_disable <= csr.io.dec_tlu_core_ecc_disable @[dec_tlu_ctl.scala 905:48] + io.tlu_busbuff.dec_tlu_external_ldfwd_disable <= csr.io.dec_tlu_external_ldfwd_disable @[dec_tlu_ctl.scala 906:52] + io.tlu_dma.dec_tlu_dma_qos_prty <= csr.io.dec_tlu_dma_qos_prty @[dec_tlu_ctl.scala 907:48] + csr.io.dec_illegal_inst <= io.dec_illegal_inst @[dec_tlu_ctl.scala 908:44] + csr.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 909:44] + csr.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec_tlu_ctl.scala 909:44] + csr.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec_tlu_ctl.scala 909:44] + csr.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec_tlu_ctl.scala 909:44] + csr.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec_tlu_ctl.scala 909:44] + csr.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec_tlu_ctl.scala 909:44] + csr.io.mexintpend <= io.dec_pic.mexintpend @[dec_tlu_ctl.scala 910:44] + csr.io.exu_npc_r <= io.tlu_exu.exu_npc_r @[dec_tlu_ctl.scala 911:44] + csr.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec_tlu_ctl.scala 912:44] + csr.io.rst_vec <= io.rst_vec @[dec_tlu_ctl.scala 913:44] + csr.io.core_id <= io.core_id @[dec_tlu_ctl.scala 914:44] + csr.io.dec_timer_rddata_d <= int_timers.io.dec_timer_rddata_d @[dec_tlu_ctl.scala 915:44] + csr.io.dec_timer_read_d <= int_timers.io.dec_timer_read_d @[dec_tlu_ctl.scala 916:44] + csr.io.rfpc_i0_r <= rfpc_i0_r @[dec_tlu_ctl.scala 919:39] + csr.io.i0_trigger_hit_r <= i0_trigger_hit_r @[dec_tlu_ctl.scala 920:39] + csr.io.exc_or_int_valid_r <= exc_or_int_valid_r @[dec_tlu_ctl.scala 921:39] + csr.io.mret_r <= mret_r @[dec_tlu_ctl.scala 922:39] + csr.io.dcsr_single_step_running_f <= dcsr_single_step_running_f @[dec_tlu_ctl.scala 923:39] + csr.io.dec_timer_t0_pulse <= int_timers.io.dec_timer_t0_pulse @[dec_tlu_ctl.scala 924:39] + csr.io.dec_timer_t1_pulse <= int_timers.io.dec_timer_t1_pulse @[dec_tlu_ctl.scala 925:39] + csr.io.timer_int_sync <= timer_int_sync @[dec_tlu_ctl.scala 926:39] + csr.io.soft_int_sync <= soft_int_sync @[dec_tlu_ctl.scala 927:39] + csr.io.csr_wr_clk <= rvclkhdr.io.l1clk @[dec_tlu_ctl.scala 928:39] + csr.io.ebreak_to_debug_mode_r <= ebreak_to_debug_mode_r @[dec_tlu_ctl.scala 929:39] + csr.io.dec_tlu_pmu_fw_halted <= dec_tlu_pmu_fw_halted @[dec_tlu_ctl.scala 930:39] + csr.io.lsu_fir_error <= io.lsu_fir_error @[dec_tlu_ctl.scala 931:39] + csr.io.tlu_flush_lower_r_d1 <= tlu_flush_lower_r_d1 @[dec_tlu_ctl.scala 932:39] + csr.io.dec_tlu_flush_noredir_r_d1 <= dec_tlu_flush_noredir_r_d1 @[dec_tlu_ctl.scala 933:39] + csr.io.tlu_flush_path_r_d1 <= tlu_flush_path_r_d1 @[dec_tlu_ctl.scala 934:39] + csr.io.reset_delayed <= reset_delayed @[dec_tlu_ctl.scala 935:39] + csr.io.interrupt_valid_r <= interrupt_valid_r @[dec_tlu_ctl.scala 936:39] + csr.io.i0_exception_valid_r <= i0_exception_valid_r @[dec_tlu_ctl.scala 937:39] + csr.io.lsu_exc_valid_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 938:39] + csr.io.mepc_trigger_hit_sel_pc_r <= mepc_trigger_hit_sel_pc_r @[dec_tlu_ctl.scala 939:39] + csr.io.e4e5_int_clk <= rvclkhdr_3.io.l1clk @[dec_tlu_ctl.scala 940:39] + csr.io.lsu_i0_exc_r <= lsu_exc_valid_r @[dec_tlu_ctl.scala 941:39] + csr.io.inst_acc_r <= inst_acc_r @[dec_tlu_ctl.scala 942:39] + csr.io.inst_acc_second_r <= io.dec_tlu_packet_r.icaf_f1 @[dec_tlu_ctl.scala 943:39] + csr.io.take_nmi <= take_nmi @[dec_tlu_ctl.scala 944:39] + csr.io.lsu_error_pkt_addr_r <= io.lsu_error_pkt_r.bits.addr @[dec_tlu_ctl.scala 945:39] + csr.io.exc_cause_r <= exc_cause_r @[dec_tlu_ctl.scala 946:39] + csr.io.i0_valid_wb <= i0_valid_wb @[dec_tlu_ctl.scala 947:39] + csr.io.exc_or_int_valid_r_d1 <= exc_or_int_valid_r_d1 @[dec_tlu_ctl.scala 948:39] + csr.io.interrupt_valid_r_d1 <= interrupt_valid_r_d1 @[dec_tlu_ctl.scala 949:39] + csr.io.clk_override <= io.dec_tlu_dec_clk_override @[dec_tlu_ctl.scala 950:39] + csr.io.i0_exception_valid_r_d1 <= i0_exception_valid_r_d1 @[dec_tlu_ctl.scala 951:39] + csr.io.lsu_i0_exc_r_d1 <= lsu_i0_exc_r_d1 @[dec_tlu_ctl.scala 952:39] + csr.io.exc_cause_wb <= exc_cause_wb @[dec_tlu_ctl.scala 953:39] + csr.io.nmi_lsu_store_type <= nmi_lsu_store_type @[dec_tlu_ctl.scala 954:39] + csr.io.nmi_lsu_load_type <= nmi_lsu_load_type @[dec_tlu_ctl.scala 955:39] + csr.io.tlu_i0_commit_cmt <= tlu_i0_commit_cmt @[dec_tlu_ctl.scala 956:39] + csr.io.ebreak_r <= ebreak_r @[dec_tlu_ctl.scala 957:39] + csr.io.ecall_r <= ecall_r @[dec_tlu_ctl.scala 958:39] + csr.io.illegal_r <= illegal_r @[dec_tlu_ctl.scala 959:39] + csr.io.mdseac_locked_f <= mdseac_locked_f @[dec_tlu_ctl.scala 960:39] + csr.io.nmi_int_detected_f <= nmi_int_detected_f @[dec_tlu_ctl.scala 961:39] + csr.io.internal_dbg_halt_mode_f2 <= internal_dbg_halt_mode_f2 @[dec_tlu_ctl.scala 962:39] + csr.io.ext_int_freeze_d1 <= ext_int_freeze_d1 @[dec_tlu_ctl.scala 963:39] + csr.io.ic_perr_r_d1 <= ic_perr_r_d1 @[dec_tlu_ctl.scala 964:39] + csr.io.iccm_sbecc_r_d1 <= iccm_sbecc_r_d1 @[dec_tlu_ctl.scala 965:39] + csr.io.lsu_single_ecc_error_r_d1 <= lsu_single_ecc_error_r_d1 @[dec_tlu_ctl.scala 966:39] + csr.io.ifu_miss_state_idle_f <= ifu_miss_state_idle_f @[dec_tlu_ctl.scala 967:39] + csr.io.lsu_idle_any_f <= lsu_idle_any_f @[dec_tlu_ctl.scala 968:39] + csr.io.dbg_tlu_halted_f <= dbg_tlu_halted_f @[dec_tlu_ctl.scala 969:39] + csr.io.dbg_tlu_halted <= dbg_tlu_halted @[dec_tlu_ctl.scala 970:39] + csr.io.debug_halt_req_f <= debug_halt_req_f @[dec_tlu_ctl.scala 971:51] + csr.io.take_ext_int_start <= take_ext_int_start @[dec_tlu_ctl.scala 972:47] + csr.io.trigger_hit_dmode_r_d1 <= trigger_hit_dmode_r_d1 @[dec_tlu_ctl.scala 973:43] + csr.io.trigger_hit_r_d1 <= trigger_hit_r_d1 @[dec_tlu_ctl.scala 974:43] + csr.io.dcsr_single_step_done_f <= dcsr_single_step_done_f @[dec_tlu_ctl.scala 975:43] + csr.io.ebreak_to_debug_mode_r_d1 <= ebreak_to_debug_mode_r_d1 @[dec_tlu_ctl.scala 976:39] + csr.io.debug_halt_req <= debug_halt_req @[dec_tlu_ctl.scala 977:51] + csr.io.allow_dbg_halt_csr_write <= allow_dbg_halt_csr_write @[dec_tlu_ctl.scala 978:39] + csr.io.internal_dbg_halt_mode_f <= debug_mode_status @[dec_tlu_ctl.scala 979:39] + csr.io.enter_debug_halt_req <= enter_debug_halt_req @[dec_tlu_ctl.scala 980:39] + csr.io.internal_dbg_halt_mode <= internal_dbg_halt_mode @[dec_tlu_ctl.scala 981:39] + csr.io.request_debug_mode_done <= request_debug_mode_done @[dec_tlu_ctl.scala 982:39] + csr.io.request_debug_mode_r <= request_debug_mode_r @[dec_tlu_ctl.scala 983:39] + csr.io.update_hit_bit_r <= update_hit_bit_r @[dec_tlu_ctl.scala 984:39] + csr.io.take_timer_int <= take_timer_int @[dec_tlu_ctl.scala 985:39] + csr.io.take_int_timer0_int <= take_int_timer0_int @[dec_tlu_ctl.scala 986:39] + csr.io.take_int_timer1_int <= take_int_timer1_int @[dec_tlu_ctl.scala 987:39] + csr.io.take_ext_int <= take_ext_int @[dec_tlu_ctl.scala 988:39] + csr.io.tlu_flush_lower_r <= tlu_flush_lower_r @[dec_tlu_ctl.scala 989:39] + csr.io.dec_tlu_br0_error_r <= dec_tlu_br0_error_r @[dec_tlu_ctl.scala 990:39] + csr.io.dec_tlu_br0_start_error_r <= dec_tlu_br0_start_error_r @[dec_tlu_ctl.scala 991:39] + csr.io.lsu_pmu_load_external_r <= lsu_pmu_load_external_r @[dec_tlu_ctl.scala 992:39] + csr.io.lsu_pmu_store_external_r <= lsu_pmu_store_external_r @[dec_tlu_ctl.scala 993:39] + csr.io.csr_pkt.legal <= csr_pkt.legal @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.postsync <= csr_pkt.postsync @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.presync <= csr_pkt.presync @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_dicago <= csr_pkt.csr_dicago @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_dicad1 <= csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_dicad0 <= csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_dicad0h <= csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_dicawics <= csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mfdhs <= csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mfdht <= csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mdccmect <= csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_miccmect <= csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_micect <= csr_pkt.csr_micect @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mdeau <= csr_pkt.csr_mdeau @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_meicpct <= csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mcpc <= csr_pkt.csr_mcpc @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mpmc <= csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mitcnt1 <= csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mitcnt0 <= csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mitb1 <= csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mitb0 <= csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mitctl1 <= csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mitctl0 <= csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mcountinhibit <= csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mhpme6 <= csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mhpme5 <= csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mhpme4 <= csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mhpme3 <= csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mhpmc6h <= csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mhpmc5h <= csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mhpmc4h <= csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mhpmc3h <= csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mhpmc6 <= csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mhpmc5 <= csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mhpmc4 <= csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mhpmc3 <= csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mtdata2 <= csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mtdata1 <= csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mtsel <= csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_dpc <= csr_pkt.csr_dpc @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mfdc <= csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mcgc <= csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_dcsr <= csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_meicidpl <= csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_meicurpl <= csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_meipt <= csr_pkt.csr_meipt @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_meivt <= csr_pkt.csr_meivt @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_meihap <= csr_pkt.csr_meihap @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mdseac <= csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_dmst <= csr_pkt.csr_dmst @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mrac <= csr_pkt.csr_mrac @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mtval <= csr_pkt.csr_mtval @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mscause <= csr_pkt.csr_mscause @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mcause <= csr_pkt.csr_mcause @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mepc <= csr_pkt.csr_mepc @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mscratch <= csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_minstreth <= csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_minstretl <= csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mcycleh <= csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mcyclel <= csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mie <= csr_pkt.csr_mie @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mip <= csr_pkt.csr_mip @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mtvec <= csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mstatus <= csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mhartid <= csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mimpid <= csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_marchid <= csr_pkt.csr_marchid @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_mvendorid <= csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 994:39] + csr.io.csr_pkt.csr_misa <= csr_pkt.csr_misa @[dec_tlu_ctl.scala 994:39] + npc_r <= csr.io.npc_r @[dec_tlu_ctl.scala 996:31] + npc_r_d1 <= csr.io.npc_r_d1 @[dec_tlu_ctl.scala 997:31] + mie_ns <= csr.io.mie_ns @[dec_tlu_ctl.scala 998:31] + mepc <= csr.io.mepc @[dec_tlu_ctl.scala 999:31] + mdseac_locked_ns <= csr.io.mdseac_locked_ns @[dec_tlu_ctl.scala 1000:31] + force_halt <= csr.io.force_halt @[dec_tlu_ctl.scala 1001:31] + dpc <= csr.io.dpc @[dec_tlu_ctl.scala 1002:31] + mstatus_mie_ns <= csr.io.mstatus_mie_ns @[dec_tlu_ctl.scala 1003:31] + dec_csr_wen_r_mod <= csr.io.dec_csr_wen_r_mod @[dec_tlu_ctl.scala 1004:31] + fw_halt_req <= csr.io.fw_halt_req @[dec_tlu_ctl.scala 1005:31] + mstatus <= csr.io.mstatus @[dec_tlu_ctl.scala 1006:31] + dcsr <= csr.io.dcsr @[dec_tlu_ctl.scala 1007:31] + mtvec <= csr.io.mtvec @[dec_tlu_ctl.scala 1008:31] + mip <= csr.io.mip @[dec_tlu_ctl.scala 1009:31] + mtdata1_t[0] <= csr.io.mtdata1_t[0] @[dec_tlu_ctl.scala 1010:33] + mtdata1_t[1] <= csr.io.mtdata1_t[1] @[dec_tlu_ctl.scala 1010:33] + mtdata1_t[2] <= csr.io.mtdata1_t[2] @[dec_tlu_ctl.scala 1010:33] + mtdata1_t[3] <= csr.io.mtdata1_t[3] @[dec_tlu_ctl.scala 1010:33] + inst csr_read of dec_decode_csr_read @[dec_tlu_ctl.scala 1011:22] csr_read.clock <= clock csr_read.reset <= reset - csr_read.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 1016:37] - csr_pkt.legal <= csr_read.io.csr_pkt.legal @[dec_tlu_ctl.scala 1017:16] - csr_pkt.postsync <= csr_read.io.csr_pkt.postsync @[dec_tlu_ctl.scala 1017:16] - csr_pkt.presync <= csr_read.io.csr_pkt.presync @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_dicago <= csr_read.io.csr_pkt.csr_dicago @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_dicad1 <= csr_read.io.csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_dicad0 <= csr_read.io.csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_dicad0h <= csr_read.io.csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_dicawics <= csr_read.io.csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mfdhs <= csr_read.io.csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mfdht <= csr_read.io.csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mdccmect <= csr_read.io.csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_miccmect <= csr_read.io.csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_micect <= csr_read.io.csr_pkt.csr_micect @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mdeau <= csr_read.io.csr_pkt.csr_mdeau @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_meicpct <= csr_read.io.csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mcpc <= csr_read.io.csr_pkt.csr_mcpc @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mpmc <= csr_read.io.csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mitcnt1 <= csr_read.io.csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mitcnt0 <= csr_read.io.csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mitb1 <= csr_read.io.csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mitb0 <= csr_read.io.csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mitctl1 <= csr_read.io.csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mitctl0 <= csr_read.io.csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mcountinhibit <= csr_read.io.csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mhpme6 <= csr_read.io.csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mhpme5 <= csr_read.io.csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mhpme4 <= csr_read.io.csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mhpme3 <= csr_read.io.csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mhpmc6h <= csr_read.io.csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mhpmc5h <= csr_read.io.csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mhpmc4h <= csr_read.io.csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mhpmc3h <= csr_read.io.csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mhpmc6 <= csr_read.io.csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mhpmc5 <= csr_read.io.csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mhpmc4 <= csr_read.io.csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mhpmc3 <= csr_read.io.csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mtdata2 <= csr_read.io.csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mtdata1 <= csr_read.io.csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mtsel <= csr_read.io.csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_dpc <= csr_read.io.csr_pkt.csr_dpc @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mfdc <= csr_read.io.csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mcgc <= csr_read.io.csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_dcsr <= csr_read.io.csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_meicidpl <= csr_read.io.csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_meicurpl <= csr_read.io.csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_meipt <= csr_read.io.csr_pkt.csr_meipt @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_meivt <= csr_read.io.csr_pkt.csr_meivt @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_meihap <= csr_read.io.csr_pkt.csr_meihap @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mdseac <= csr_read.io.csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_dmst <= csr_read.io.csr_pkt.csr_dmst @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mrac <= csr_read.io.csr_pkt.csr_mrac @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mtval <= csr_read.io.csr_pkt.csr_mtval @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mscause <= csr_read.io.csr_pkt.csr_mscause @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mcause <= csr_read.io.csr_pkt.csr_mcause @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mepc <= csr_read.io.csr_pkt.csr_mepc @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mscratch <= csr_read.io.csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_minstreth <= csr_read.io.csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_minstretl <= csr_read.io.csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mcycleh <= csr_read.io.csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mcyclel <= csr_read.io.csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mie <= csr_read.io.csr_pkt.csr_mie @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mip <= csr_read.io.csr_pkt.csr_mip @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mtvec <= csr_read.io.csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mstatus <= csr_read.io.csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mhartid <= csr_read.io.csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mimpid <= csr_read.io.csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_marchid <= csr_read.io.csr_pkt.csr_marchid @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_mvendorid <= csr_read.io.csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 1017:16] - csr_pkt.csr_misa <= csr_read.io.csr_pkt.csr_misa @[dec_tlu_ctl.scala 1017:16] - node _T_864 = and(csr_pkt.presync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1019:42] - node _T_865 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 1019:67] - node _T_866 = and(_T_864, _T_865) @[dec_tlu_ctl.scala 1019:65] - io.dec_tlu_presync_d <= _T_866 @[dec_tlu_ctl.scala 1019:23] - node _T_867 = and(csr_pkt.postsync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1020:43] - io.dec_tlu_postsync_d <= _T_867 @[dec_tlu_ctl.scala 1020:23] - node _T_868 = or(csr_pkt.csr_mitcnt0, csr_pkt.csr_mitcnt1) @[dec_tlu_ctl.scala 1023:50] - node _T_869 = or(_T_868, csr_pkt.csr_mitb0) @[dec_tlu_ctl.scala 1023:72] - node _T_870 = or(_T_869, csr_pkt.csr_mitb1) @[dec_tlu_ctl.scala 1023:92] - node _T_871 = or(_T_870, csr_pkt.csr_mitctl0) @[dec_tlu_ctl.scala 1023:112] - node _T_872 = or(_T_871, csr_pkt.csr_mitctl1) @[dec_tlu_ctl.scala 1023:134] - node _T_873 = not(UInt<1>("h01")) @[dec_tlu_ctl.scala 1023:159] - node conditionally_illegal = and(_T_872, _T_873) @[dec_tlu_ctl.scala 1023:157] - node _T_874 = or(csr_pkt.csr_dcsr, csr_pkt.csr_dpc) @[dec_tlu_ctl.scala 1024:55] - node _T_875 = or(_T_874, csr_pkt.csr_dmst) @[dec_tlu_ctl.scala 1024:73] - node _T_876 = or(_T_875, csr_pkt.csr_dicawics) @[dec_tlu_ctl.scala 1024:92] - node _T_877 = or(_T_876, csr_pkt.csr_dicad0) @[dec_tlu_ctl.scala 1024:115] - node _T_878 = or(_T_877, csr_pkt.csr_dicad0h) @[dec_tlu_ctl.scala 1024:136] - node _T_879 = or(_T_878, csr_pkt.csr_dicad1) @[dec_tlu_ctl.scala 1024:158] - node _T_880 = or(_T_879, csr_pkt.csr_dicago) @[dec_tlu_ctl.scala 1024:179] - node _T_881 = not(_T_880) @[dec_tlu_ctl.scala 1024:36] - node _T_882 = or(_T_881, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1024:201] - node _T_883 = and(csr_pkt.legal, _T_882) @[dec_tlu_ctl.scala 1024:33] - node _T_884 = not(fast_int_meicpct) @[dec_tlu_ctl.scala 1024:223] - node _T_885 = and(_T_883, _T_884) @[dec_tlu_ctl.scala 1024:221] - node _T_886 = not(conditionally_illegal) @[dec_tlu_ctl.scala 1024:243] - node valid_csr = and(_T_885, _T_886) @[dec_tlu_ctl.scala 1024:241] - node _T_887 = and(io.dec_csr_any_unq_d, valid_csr) @[dec_tlu_ctl.scala 1026:46] - node _T_888 = or(csr_pkt.csr_mvendorid, csr_pkt.csr_marchid) @[dec_tlu_ctl.scala 1026:107] - node _T_889 = or(_T_888, csr_pkt.csr_mimpid) @[dec_tlu_ctl.scala 1026:129] - node _T_890 = or(_T_889, csr_pkt.csr_mhartid) @[dec_tlu_ctl.scala 1026:150] - node _T_891 = or(_T_890, csr_pkt.csr_mdseac) @[dec_tlu_ctl.scala 1026:172] - node _T_892 = or(_T_891, csr_pkt.csr_meihap) @[dec_tlu_ctl.scala 1026:193] - node _T_893 = and(io.dec_csr_wen_unq_d, _T_892) @[dec_tlu_ctl.scala 1026:82] - node _T_894 = not(_T_893) @[dec_tlu_ctl.scala 1026:59] - node _T_895 = and(_T_887, _T_894) @[dec_tlu_ctl.scala 1026:57] - io.dec_csr_legal_d <= _T_895 @[dec_tlu_ctl.scala 1026:20] + csr_read.io.dec_csr_rdaddr_d <= io.dec_csr_rdaddr_d @[dec_tlu_ctl.scala 1012:37] + csr_pkt.legal <= csr_read.io.csr_pkt.legal @[dec_tlu_ctl.scala 1013:16] + csr_pkt.postsync <= csr_read.io.csr_pkt.postsync @[dec_tlu_ctl.scala 1013:16] + csr_pkt.presync <= csr_read.io.csr_pkt.presync @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_dicago <= csr_read.io.csr_pkt.csr_dicago @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_dicad1 <= csr_read.io.csr_pkt.csr_dicad1 @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_dicad0 <= csr_read.io.csr_pkt.csr_dicad0 @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_dicad0h <= csr_read.io.csr_pkt.csr_dicad0h @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_dicawics <= csr_read.io.csr_pkt.csr_dicawics @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mfdhs <= csr_read.io.csr_pkt.csr_mfdhs @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mfdht <= csr_read.io.csr_pkt.csr_mfdht @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mdccmect <= csr_read.io.csr_pkt.csr_mdccmect @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_miccmect <= csr_read.io.csr_pkt.csr_miccmect @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_micect <= csr_read.io.csr_pkt.csr_micect @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mdeau <= csr_read.io.csr_pkt.csr_mdeau @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_meicpct <= csr_read.io.csr_pkt.csr_meicpct @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mcpc <= csr_read.io.csr_pkt.csr_mcpc @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mpmc <= csr_read.io.csr_pkt.csr_mpmc @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mitcnt1 <= csr_read.io.csr_pkt.csr_mitcnt1 @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mitcnt0 <= csr_read.io.csr_pkt.csr_mitcnt0 @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mitb1 <= csr_read.io.csr_pkt.csr_mitb1 @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mitb0 <= csr_read.io.csr_pkt.csr_mitb0 @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mitctl1 <= csr_read.io.csr_pkt.csr_mitctl1 @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mitctl0 <= csr_read.io.csr_pkt.csr_mitctl0 @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mcountinhibit <= csr_read.io.csr_pkt.csr_mcountinhibit @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mhpme6 <= csr_read.io.csr_pkt.csr_mhpme6 @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mhpme5 <= csr_read.io.csr_pkt.csr_mhpme5 @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mhpme4 <= csr_read.io.csr_pkt.csr_mhpme4 @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mhpme3 <= csr_read.io.csr_pkt.csr_mhpme3 @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mhpmc6h <= csr_read.io.csr_pkt.csr_mhpmc6h @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mhpmc5h <= csr_read.io.csr_pkt.csr_mhpmc5h @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mhpmc4h <= csr_read.io.csr_pkt.csr_mhpmc4h @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mhpmc3h <= csr_read.io.csr_pkt.csr_mhpmc3h @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mhpmc6 <= csr_read.io.csr_pkt.csr_mhpmc6 @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mhpmc5 <= csr_read.io.csr_pkt.csr_mhpmc5 @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mhpmc4 <= csr_read.io.csr_pkt.csr_mhpmc4 @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mhpmc3 <= csr_read.io.csr_pkt.csr_mhpmc3 @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mtdata2 <= csr_read.io.csr_pkt.csr_mtdata2 @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mtdata1 <= csr_read.io.csr_pkt.csr_mtdata1 @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mtsel <= csr_read.io.csr_pkt.csr_mtsel @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_dpc <= csr_read.io.csr_pkt.csr_dpc @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mfdc <= csr_read.io.csr_pkt.csr_mfdc @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mcgc <= csr_read.io.csr_pkt.csr_mcgc @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_dcsr <= csr_read.io.csr_pkt.csr_dcsr @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_meicidpl <= csr_read.io.csr_pkt.csr_meicidpl @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_meicurpl <= csr_read.io.csr_pkt.csr_meicurpl @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_meipt <= csr_read.io.csr_pkt.csr_meipt @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_meivt <= csr_read.io.csr_pkt.csr_meivt @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_meihap <= csr_read.io.csr_pkt.csr_meihap @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mdseac <= csr_read.io.csr_pkt.csr_mdseac @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_dmst <= csr_read.io.csr_pkt.csr_dmst @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mrac <= csr_read.io.csr_pkt.csr_mrac @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mtval <= csr_read.io.csr_pkt.csr_mtval @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mscause <= csr_read.io.csr_pkt.csr_mscause @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mcause <= csr_read.io.csr_pkt.csr_mcause @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mepc <= csr_read.io.csr_pkt.csr_mepc @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mscratch <= csr_read.io.csr_pkt.csr_mscratch @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_minstreth <= csr_read.io.csr_pkt.csr_minstreth @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_minstretl <= csr_read.io.csr_pkt.csr_minstretl @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mcycleh <= csr_read.io.csr_pkt.csr_mcycleh @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mcyclel <= csr_read.io.csr_pkt.csr_mcyclel @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mie <= csr_read.io.csr_pkt.csr_mie @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mip <= csr_read.io.csr_pkt.csr_mip @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mtvec <= csr_read.io.csr_pkt.csr_mtvec @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mstatus <= csr_read.io.csr_pkt.csr_mstatus @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mhartid <= csr_read.io.csr_pkt.csr_mhartid @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mimpid <= csr_read.io.csr_pkt.csr_mimpid @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_marchid <= csr_read.io.csr_pkt.csr_marchid @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_mvendorid <= csr_read.io.csr_pkt.csr_mvendorid @[dec_tlu_ctl.scala 1013:16] + csr_pkt.csr_misa <= csr_read.io.csr_pkt.csr_misa @[dec_tlu_ctl.scala 1013:16] + node _T_864 = and(csr_pkt.presync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1015:42] + node _T_865 = not(io.dec_csr_wen_unq_d) @[dec_tlu_ctl.scala 1015:67] + node _T_866 = and(_T_864, _T_865) @[dec_tlu_ctl.scala 1015:65] + io.dec_tlu_presync_d <= _T_866 @[dec_tlu_ctl.scala 1015:23] + node _T_867 = and(csr_pkt.postsync, io.dec_csr_any_unq_d) @[dec_tlu_ctl.scala 1016:43] + io.dec_tlu_postsync_d <= _T_867 @[dec_tlu_ctl.scala 1016:23] + node _T_868 = or(csr_pkt.csr_mitcnt0, csr_pkt.csr_mitcnt1) @[dec_tlu_ctl.scala 1019:50] + node _T_869 = or(_T_868, csr_pkt.csr_mitb0) @[dec_tlu_ctl.scala 1019:72] + node _T_870 = or(_T_869, csr_pkt.csr_mitb1) @[dec_tlu_ctl.scala 1019:92] + node _T_871 = or(_T_870, csr_pkt.csr_mitctl0) @[dec_tlu_ctl.scala 1019:112] + node _T_872 = or(_T_871, csr_pkt.csr_mitctl1) @[dec_tlu_ctl.scala 1019:134] + node _T_873 = not(UInt<1>("h01")) @[dec_tlu_ctl.scala 1019:159] + node conditionally_illegal = and(_T_872, _T_873) @[dec_tlu_ctl.scala 1019:157] + node _T_874 = or(csr_pkt.csr_dcsr, csr_pkt.csr_dpc) @[dec_tlu_ctl.scala 1020:55] + node _T_875 = or(_T_874, csr_pkt.csr_dmst) @[dec_tlu_ctl.scala 1020:73] + node _T_876 = or(_T_875, csr_pkt.csr_dicawics) @[dec_tlu_ctl.scala 1020:92] + node _T_877 = or(_T_876, csr_pkt.csr_dicad0) @[dec_tlu_ctl.scala 1020:115] + node _T_878 = or(_T_877, csr_pkt.csr_dicad0h) @[dec_tlu_ctl.scala 1020:136] + node _T_879 = or(_T_878, csr_pkt.csr_dicad1) @[dec_tlu_ctl.scala 1020:158] + node _T_880 = or(_T_879, csr_pkt.csr_dicago) @[dec_tlu_ctl.scala 1020:179] + node _T_881 = not(_T_880) @[dec_tlu_ctl.scala 1020:36] + node _T_882 = or(_T_881, dbg_tlu_halted_f) @[dec_tlu_ctl.scala 1020:201] + node _T_883 = and(csr_pkt.legal, _T_882) @[dec_tlu_ctl.scala 1020:33] + node _T_884 = not(fast_int_meicpct) @[dec_tlu_ctl.scala 1020:223] + node _T_885 = and(_T_883, _T_884) @[dec_tlu_ctl.scala 1020:221] + node _T_886 = not(conditionally_illegal) @[dec_tlu_ctl.scala 1020:243] + node valid_csr = and(_T_885, _T_886) @[dec_tlu_ctl.scala 1020:241] + node _T_887 = and(io.dec_csr_any_unq_d, valid_csr) @[dec_tlu_ctl.scala 1022:46] + node _T_888 = or(csr_pkt.csr_mvendorid, csr_pkt.csr_marchid) @[dec_tlu_ctl.scala 1022:107] + node _T_889 = or(_T_888, csr_pkt.csr_mimpid) @[dec_tlu_ctl.scala 1022:129] + node _T_890 = or(_T_889, csr_pkt.csr_mhartid) @[dec_tlu_ctl.scala 1022:150] + node _T_891 = or(_T_890, csr_pkt.csr_mdseac) @[dec_tlu_ctl.scala 1022:172] + node _T_892 = or(_T_891, csr_pkt.csr_meihap) @[dec_tlu_ctl.scala 1022:193] + node _T_893 = and(io.dec_csr_wen_unq_d, _T_892) @[dec_tlu_ctl.scala 1022:82] + node _T_894 = not(_T_893) @[dec_tlu_ctl.scala 1022:59] + node _T_895 = and(_T_887, _T_894) @[dec_tlu_ctl.scala 1022:57] + io.dec_csr_legal_d <= _T_895 @[dec_tlu_ctl.scala 1022:20] module dec_trigger : input clock : Clock @@ -81182,7 +81181,7 @@ circuit quasar_wrapper : module dec : input clock : Clock input reset : AsyncReset - output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip lsu_trigger_match_m : UInt<4>, flip lsu_idle_any : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip mexintpend : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip exu_i0_br_way_r : UInt<1>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, dec_lsu_offset_d : UInt<12>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dec_tlu_dma_qos_prty : UInt<3>, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, flip scan_mode : UInt<1>, flip ifu_dec : {dec_aln : {aln_dec : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, aln_ib : {ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_i0_valid : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}, ifu_pmu_instr_aligned : UInt<1>}, dec_mem_ctrl : {flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, dec_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, dec_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}}, flip dec_exu : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, ib_exu : {flip dec_i0_pc_d : UInt<31>, flip dec_debug_wdata_rs1_d : UInt<1>}, gpr_exu : {flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>}}, flip lsu_dec : {tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}}, flip lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, dec_dbg : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}}} + output io : {flip free_clk : Clock, flip active_clk : Clock, flip lsu_fastint_stall_any : UInt<1>, dec_pause_state_cg : UInt<1>, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip lsu_pmu_misaligned_m : UInt<1>, flip lsu_fir_addr : UInt<31>, flip lsu_fir_error : UInt<2>, flip lsu_trigger_match_m : UInt<4>, flip lsu_idle_any : UInt<1>, flip lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, flip lsu_single_ecc_error_incr : UInt<1>, flip exu_div_result : UInt<32>, flip exu_div_wren : UInt<1>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip iccm_dma_sb_error : UInt<1>, flip exu_flush_final : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip dbg_halt_req : UInt<1>, flip dbg_resume_req : UInt<1>, dec_tlu_dbg_halted : UInt<1>, dec_tlu_debug_mode : UInt<1>, dec_tlu_resume_ack : UInt<1>, dec_tlu_mpc_halted_only : UInt<1>, dec_dbg_rddata : UInt<32>, dec_dbg_cmd_done : UInt<1>, dec_dbg_cmd_fail : UInt<1>, trigger_pkt_any : {select : UInt<1>, match_pkt : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip exu_i0_br_way_r : UInt<1>, lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, dec_lsu_offset_d : UInt<12>, dec_tlu_i0_kill_writeb_r : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dec_tlu_misc_clk_override : UInt<1>, dec_tlu_ifu_clk_override : UInt<1>, dec_tlu_lsu_clk_override : UInt<1>, dec_tlu_bus_clk_override : UInt<1>, dec_tlu_pic_clk_override : UInt<1>, dec_tlu_dccm_clk_override : UInt<1>, dec_tlu_icm_clk_override : UInt<1>, flip scan_mode : UInt<1>, flip ifu_dec : {dec_aln : {aln_dec : {flip dec_i0_decode_d : UInt<1>, ifu_i0_cinst : UInt<16>}, aln_ib : {ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_i0_valid : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}, ifu_pmu_instr_aligned : UInt<1>}, dec_mem_ctrl : {flip dec_tlu_flush_err_wb : UInt<1>, flip dec_tlu_i0_commit_cmt : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_fence_i_wb : UInt<1>, flip dec_tlu_ic_diag_pkt : {icache_wrdata : UInt<71>, icache_dicawics : UInt<17>, icache_rd_valid : UInt<1>, icache_wr_valid : UInt<1>}, flip dec_tlu_core_ecc_disable : UInt<1>, ifu_pmu_ic_miss : UInt<1>, ifu_pmu_ic_hit : UInt<1>, ifu_pmu_bus_error : UInt<1>, ifu_pmu_bus_busy : UInt<1>, ifu_pmu_bus_trxn : UInt<1>, ifu_ic_error_start : UInt<1>, ifu_iccm_rd_ecc_single_err : UInt<1>, ifu_ic_debug_rd_data : UInt<71>, ifu_ic_debug_rd_data_valid : UInt<1>, ifu_miss_state_idle : UInt<1>}, dec_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, dec_bp : {flip dec_tlu_br0_r_pkt : {valid : UInt<1>, bits : {hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}}, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>}}, flip dec_exu : {dec_alu : {flip dec_i0_alu_decode_d : UInt<1>, flip dec_csr_ren_d : UInt<1>, flip dec_i0_br_immed_d : UInt<12>, exu_i0_pc_x : UInt<31>}, dec_div : {flip div_p : {valid : UInt<1>, bits : {unsign : UInt<1>, rem : UInt<1>}}, flip dec_div_cancel : UInt<1>}, decode_exu : {flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_i0_predict_p_d : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip pred_correct_npc_x : UInt<31>, flip dec_extint_stall : UInt<1>, exu_i0_result_x : UInt<32>, exu_csr_rs1_x : UInt<32>}, tlu_exu : {flip dec_tlu_meihap : UInt<30>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_npc_r : UInt<31>}, ib_exu : {flip dec_i0_pc_d : UInt<31>, flip dec_debug_wdata_rs1_d : UInt<1>}, gpr_exu : {flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>}}, flip lsu_dec : {tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}}, flip lsu_tlu : {lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>}, dec_dbg : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}}, dec_dma : {dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}}, dec_pic : {flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip mexintpend : UInt<1>}} wire dec_i0_inst_wb1 : UInt<32> dec_i0_inst_wb1 <= UInt<1>("h00") @@ -81198,448 +81197,446 @@ circuit quasar_wrapper : dec_tlu_mtval_wb1 <= UInt<1>("h00") wire dec_tlu_i0_exc_valid_wb1 : UInt<1> dec_tlu_i0_exc_valid_wb1 <= UInt<1>("h00") - inst instbuff of dec_ib_ctl @[dec.scala 126:24] + inst instbuff of dec_ib_ctl @[dec.scala 117:24] instbuff.clock <= clock instbuff.reset <= reset - inst decode of dec_decode_ctl @[dec.scala 127:22] + inst decode of dec_decode_ctl @[dec.scala 118:22] decode.clock <= clock decode.reset <= reset - inst gpr of dec_gpr_ctl @[dec.scala 128:19] + inst gpr of dec_gpr_ctl @[dec.scala 119:19] gpr.clock <= clock gpr.reset <= reset - inst tlu of dec_tlu_ctl @[dec.scala 129:19] + inst tlu of dec_tlu_ctl @[dec.scala 120:19] tlu.clock <= clock tlu.reset <= reset - inst dec_trigger of dec_trigger @[dec.scala 130:27] + inst dec_trigger of dec_trigger @[dec.scala 121:27] dec_trigger.clock <= clock dec_trigger.reset <= reset - instbuff.io.ifu_ib.i0_brp.bits.ret <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret @[dec.scala 134:22] - instbuff.io.ifu_ib.i0_brp.bits.way <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way @[dec.scala 134:22] - instbuff.io.ifu_ib.i0_brp.bits.prett <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett @[dec.scala 134:22] - instbuff.io.ifu_ib.i0_brp.bits.bank <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank @[dec.scala 134:22] - instbuff.io.ifu_ib.i0_brp.bits.br_start_error <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error @[dec.scala 134:22] - instbuff.io.ifu_ib.i0_brp.bits.br_error <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error @[dec.scala 134:22] - instbuff.io.ifu_ib.i0_brp.bits.hist <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist @[dec.scala 134:22] - instbuff.io.ifu_ib.i0_brp.bits.toffset <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset @[dec.scala 134:22] - instbuff.io.ifu_ib.i0_brp.valid <= io.ifu_dec.dec_aln.aln_ib.i0_brp.valid @[dec.scala 134:22] - instbuff.io.ifu_ib.ifu_i0_pc4 <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 @[dec.scala 134:22] - instbuff.io.ifu_ib.ifu_i0_pc <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc @[dec.scala 134:22] - instbuff.io.ifu_ib.ifu_i0_instr <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr @[dec.scala 134:22] - instbuff.io.ifu_ib.ifu_i0_valid <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid @[dec.scala 134:22] - instbuff.io.ifu_ib.ifu_i0_bp_btag <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag @[dec.scala 134:22] - instbuff.io.ifu_ib.ifu_i0_bp_fghr <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr @[dec.scala 134:22] - instbuff.io.ifu_ib.ifu_i0_bp_index <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index @[dec.scala 134:22] - instbuff.io.ifu_ib.ifu_i0_dbecc <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc @[dec.scala 134:22] - instbuff.io.ifu_ib.ifu_i0_icaf_f1 <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 @[dec.scala 134:22] - instbuff.io.ifu_ib.ifu_i0_icaf_type <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type @[dec.scala 134:22] - instbuff.io.ifu_ib.ifu_i0_icaf <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf @[dec.scala 134:22] - io.dec_exu.ib_exu.dec_debug_wdata_rs1_d <= instbuff.io.ib_exu.dec_debug_wdata_rs1_d @[dec.scala 135:22] - io.dec_exu.ib_exu.dec_i0_pc_d <= instbuff.io.ib_exu.dec_i0_pc_d @[dec.scala 135:22] - instbuff.io.dbg_ib.dbg_cmd_addr <= io.dec_dbg.dbg_ib.dbg_cmd_addr @[dec.scala 136:22] - instbuff.io.dbg_ib.dbg_cmd_type <= io.dec_dbg.dbg_ib.dbg_cmd_type @[dec.scala 136:22] - instbuff.io.dbg_ib.dbg_cmd_write <= io.dec_dbg.dbg_ib.dbg_cmd_write @[dec.scala 136:22] - instbuff.io.dbg_ib.dbg_cmd_valid <= io.dec_dbg.dbg_ib.dbg_cmd_valid @[dec.scala 136:22] - dec_trigger.io.dec_i0_pc_d <= instbuff.io.ib_exu.dec_i0_pc_d @[dec.scala 137:30] - dec_trigger.io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[dec.scala 138:34] - dec_trigger.io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[dec.scala 138:34] - decode.io.dec_aln.ifu_i0_cinst <= io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst @[dec.scala 142:21] - io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d <= decode.io.dec_aln.dec_i0_decode_d @[dec.scala 142:21] - decode.io.decode_exu.exu_csr_rs1_x <= io.dec_exu.decode_exu.exu_csr_rs1_x @[dec.scala 143:23] - decode.io.decode_exu.exu_i0_result_x <= io.dec_exu.decode_exu.exu_i0_result_x @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_extint_stall <= decode.io.decode_exu.dec_extint_stall @[dec.scala 143:23] - io.dec_exu.decode_exu.pred_correct_npc_x <= decode.io.decode_exu.pred_correct_npc_x @[dec.scala 143:23] - io.dec_exu.decode_exu.mul_p.bits.bfp <= decode.io.decode_exu.mul_p.bits.bfp @[dec.scala 143:23] - io.dec_exu.decode_exu.mul_p.bits.crc32c_w <= decode.io.decode_exu.mul_p.bits.crc32c_w @[dec.scala 143:23] - io.dec_exu.decode_exu.mul_p.bits.crc32c_h <= decode.io.decode_exu.mul_p.bits.crc32c_h @[dec.scala 143:23] - io.dec_exu.decode_exu.mul_p.bits.crc32c_b <= decode.io.decode_exu.mul_p.bits.crc32c_b @[dec.scala 143:23] - io.dec_exu.decode_exu.mul_p.bits.crc32_w <= decode.io.decode_exu.mul_p.bits.crc32_w @[dec.scala 143:23] - io.dec_exu.decode_exu.mul_p.bits.crc32_h <= decode.io.decode_exu.mul_p.bits.crc32_h @[dec.scala 143:23] - io.dec_exu.decode_exu.mul_p.bits.crc32_b <= decode.io.decode_exu.mul_p.bits.crc32_b @[dec.scala 143:23] - io.dec_exu.decode_exu.mul_p.bits.unshfl <= decode.io.decode_exu.mul_p.bits.unshfl @[dec.scala 143:23] - io.dec_exu.decode_exu.mul_p.bits.shfl <= decode.io.decode_exu.mul_p.bits.shfl @[dec.scala 143:23] - io.dec_exu.decode_exu.mul_p.bits.grev <= decode.io.decode_exu.mul_p.bits.grev @[dec.scala 143:23] - io.dec_exu.decode_exu.mul_p.bits.clmulr <= decode.io.decode_exu.mul_p.bits.clmulr @[dec.scala 143:23] - io.dec_exu.decode_exu.mul_p.bits.clmulh <= decode.io.decode_exu.mul_p.bits.clmulh @[dec.scala 143:23] - io.dec_exu.decode_exu.mul_p.bits.clmul <= decode.io.decode_exu.mul_p.bits.clmul @[dec.scala 143:23] - io.dec_exu.decode_exu.mul_p.bits.bdep <= decode.io.decode_exu.mul_p.bits.bdep @[dec.scala 143:23] - io.dec_exu.decode_exu.mul_p.bits.bext <= decode.io.decode_exu.mul_p.bits.bext @[dec.scala 143:23] - io.dec_exu.decode_exu.mul_p.bits.low <= decode.io.decode_exu.mul_p.bits.low @[dec.scala 143:23] - io.dec_exu.decode_exu.mul_p.bits.rs2_sign <= decode.io.decode_exu.mul_p.bits.rs2_sign @[dec.scala 143:23] - io.dec_exu.decode_exu.mul_p.bits.rs1_sign <= decode.io.decode_exu.mul_p.bits.rs1_sign @[dec.scala 143:23] - io.dec_exu.decode_exu.mul_p.valid <= decode.io.decode_exu.mul_p.valid @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d <= decode.io.decode_exu.dec_i0_rs2_bypass_en_d @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d <= decode.io.decode_exu.dec_i0_rs1_bypass_en_d @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_select_pc_d <= decode.io.decode_exu.dec_i0_select_pc_d @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d <= decode.io.decode_exu.dec_i0_rs2_bypass_data_d @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d <= decode.io.decode_exu.dec_i0_rs1_bypass_data_d @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_immed_d <= decode.io.decode_exu.dec_i0_immed_d @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_rs2_en_d <= decode.io.decode_exu.dec_i0_rs2_en_d @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_rs1_en_d <= decode.io.decode_exu.dec_i0_rs1_en_d @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_predict_btag_d <= decode.io.decode_exu.i0_predict_btag_d @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_predict_index_d <= decode.io.decode_exu.i0_predict_index_d @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_predict_fghr_d <= decode.io.decode_exu.i0_predict_fghr_d @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way <= decode.io.decode_exu.dec_i0_predict_p_d.bits.way @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pja @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pret @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pcall @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett <= decode.io.decode_exu.dec_i0_predict_p_d.bits.prett @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= decode.io.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error <= decode.io.decode_exu.dec_i0_predict_p_d.bits.br_error @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset <= decode.io.decode_exu.dec_i0_predict_p_d.bits.toffset @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist <= decode.io.decode_exu.dec_i0_predict_p_d.bits.hist @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pc4 @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset <= decode.io.decode_exu.dec_i0_predict_p_d.bits.boffset @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken <= decode.io.decode_exu.dec_i0_predict_p_d.bits.ataken @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp <= decode.io.decode_exu.dec_i0_predict_p_d.bits.misp @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_i0_predict_p_d.valid <= decode.io.decode_exu.dec_i0_predict_p_d.valid @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_ap.csr_imm <= decode.io.decode_exu.i0_ap.csr_imm @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_ap.csr_write <= decode.io.decode_exu.i0_ap.csr_write @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_ap.predict_nt <= decode.io.decode_exu.i0_ap.predict_nt @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_ap.predict_t <= decode.io.decode_exu.i0_ap.predict_t @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_ap.jal <= decode.io.decode_exu.i0_ap.jal @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_ap.unsign <= decode.io.decode_exu.i0_ap.unsign @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_ap.slt <= decode.io.decode_exu.i0_ap.slt @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_ap.sub <= decode.io.decode_exu.i0_ap.sub @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_ap.add <= decode.io.decode_exu.i0_ap.add @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_ap.bge <= decode.io.decode_exu.i0_ap.bge @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_ap.blt <= decode.io.decode_exu.i0_ap.blt @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_ap.bne <= decode.io.decode_exu.i0_ap.bne @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_ap.beq <= decode.io.decode_exu.i0_ap.beq @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_ap.sra <= decode.io.decode_exu.i0_ap.sra @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_ap.srl <= decode.io.decode_exu.i0_ap.srl @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_ap.sll <= decode.io.decode_exu.i0_ap.sll @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_ap.lxor <= decode.io.decode_exu.i0_ap.lxor @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_ap.lor <= decode.io.decode_exu.i0_ap.lor @[dec.scala 143:23] - io.dec_exu.decode_exu.i0_ap.land <= decode.io.decode_exu.i0_ap.land @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_ctl_en <= decode.io.decode_exu.dec_ctl_en @[dec.scala 143:23] - io.dec_exu.decode_exu.dec_data_en <= decode.io.decode_exu.dec_data_en @[dec.scala 143:23] - decode.io.dec_alu.exu_i0_pc_x <= io.dec_exu.dec_alu.exu_i0_pc_x @[dec.scala 144:20] - io.dec_exu.dec_alu.dec_i0_br_immed_d <= decode.io.dec_alu.dec_i0_br_immed_d @[dec.scala 144:20] - io.dec_exu.dec_alu.dec_csr_ren_d <= decode.io.dec_alu.dec_csr_ren_d @[dec.scala 144:20] - io.dec_exu.dec_alu.dec_i0_alu_decode_d <= decode.io.dec_alu.dec_i0_alu_decode_d @[dec.scala 144:20] - io.dec_exu.dec_div.dec_div_cancel <= decode.io.dec_div.dec_div_cancel @[dec.scala 145:20] - io.dec_exu.dec_div.div_p.bits.rem <= decode.io.dec_div.div_p.bits.rem @[dec.scala 145:20] - io.dec_exu.dec_div.div_p.bits.unsign <= decode.io.dec_div.div_p.bits.unsign @[dec.scala 145:20] - io.dec_exu.dec_div.div_p.valid <= decode.io.dec_div.div_p.valid @[dec.scala 145:20] - decode.io.dec_tlu_flush_extint <= tlu.io.dec_tlu_flush_extint @[dec.scala 146:48] - decode.io.dec_tlu_force_halt <= tlu.io.tlu_mem.dec_tlu_force_halt @[dec.scala 147:48] - decode.io.dctl_busbuff.lsu_nonblock_load_data <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data @[dec.scala 148:26] - decode.io.dctl_busbuff.lsu_nonblock_load_data_tag <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag @[dec.scala 148:26] - decode.io.dctl_busbuff.lsu_nonblock_load_data_error <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error @[dec.scala 148:26] - decode.io.dctl_busbuff.lsu_nonblock_load_data_valid <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid @[dec.scala 148:26] - decode.io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[dec.scala 148:26] - decode.io.dctl_busbuff.lsu_nonblock_load_inv_r <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r @[dec.scala 148:26] - decode.io.dctl_busbuff.lsu_nonblock_load_tag_m <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m @[dec.scala 148:26] - decode.io.dctl_busbuff.lsu_nonblock_load_valid_m <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m @[dec.scala 148:26] - decode.io.dec_i0_trigger_match_d <= dec_trigger.io.dec_i0_trigger_match_d @[dec.scala 149:48] - decode.io.dec_tlu_wr_pause_r <= tlu.io.dec_tlu_wr_pause_r @[dec.scala 150:48] - decode.io.dec_tlu_pipelining_disable <= tlu.io.dec_tlu_pipelining_disable @[dec.scala 151:48] - decode.io.lsu_trigger_match_m <= io.lsu_trigger_match_m @[dec.scala 152:48] - decode.io.lsu_pmu_misaligned_m <= io.lsu_pmu_misaligned_m @[dec.scala 153:48] - decode.io.dec_tlu_debug_stall <= tlu.io.dec_tlu_debug_stall @[dec.scala 154:48] - decode.io.dec_tlu_flush_leak_one_r <= tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb @[dec.scala 155:48] - decode.io.dec_debug_fence_d <= instbuff.io.dec_debug_fence_d @[dec.scala 156:48] - decode.io.dbg_dctl.dbg_cmd_wrdata <= io.dec_dbg.dbg_dctl.dbg_cmd_wrdata @[dec.scala 157:22] - decode.io.dec_i0_icaf_d <= instbuff.io.dec_i0_icaf_d @[dec.scala 158:48] - decode.io.dec_i0_icaf_f1_d <= instbuff.io.dec_i0_icaf_f1_d @[dec.scala 159:48] - decode.io.dec_i0_icaf_type_d <= instbuff.io.dec_i0_icaf_type_d @[dec.scala 160:48] - decode.io.dec_i0_dbecc_d <= instbuff.io.dec_i0_dbecc_d @[dec.scala 161:48] - decode.io.dec_i0_brp.bits.ret <= instbuff.io.dec_i0_brp.bits.ret @[dec.scala 162:48] - decode.io.dec_i0_brp.bits.way <= instbuff.io.dec_i0_brp.bits.way @[dec.scala 162:48] - decode.io.dec_i0_brp.bits.prett <= instbuff.io.dec_i0_brp.bits.prett @[dec.scala 162:48] - decode.io.dec_i0_brp.bits.bank <= instbuff.io.dec_i0_brp.bits.bank @[dec.scala 162:48] - decode.io.dec_i0_brp.bits.br_start_error <= instbuff.io.dec_i0_brp.bits.br_start_error @[dec.scala 162:48] - decode.io.dec_i0_brp.bits.br_error <= instbuff.io.dec_i0_brp.bits.br_error @[dec.scala 162:48] - decode.io.dec_i0_brp.bits.hist <= instbuff.io.dec_i0_brp.bits.hist @[dec.scala 162:48] - decode.io.dec_i0_brp.bits.toffset <= instbuff.io.dec_i0_brp.bits.toffset @[dec.scala 162:48] - decode.io.dec_i0_brp.valid <= instbuff.io.dec_i0_brp.valid @[dec.scala 162:48] - decode.io.dec_i0_bp_index <= instbuff.io.dec_i0_bp_index @[dec.scala 163:48] - decode.io.dec_i0_bp_fghr <= instbuff.io.dec_i0_bp_fghr @[dec.scala 164:48] - decode.io.dec_i0_bp_btag <= instbuff.io.dec_i0_bp_btag @[dec.scala 165:48] - decode.io.dec_i0_pc_d <= instbuff.io.ib_exu.dec_i0_pc_d @[dec.scala 166:48] - decode.io.lsu_idle_any <= io.lsu_idle_any @[dec.scala 167:48] - decode.io.lsu_load_stall_any <= io.lsu_load_stall_any @[dec.scala 168:48] - decode.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec.scala 169:48] - decode.io.dma_dccm_stall_any <= io.dma_dccm_stall_any @[dec.scala 170:48] - decode.io.exu_div_wren <= io.exu_div_wren @[dec.scala 171:48] - decode.io.dec_tlu_i0_kill_writeb_wb <= tlu.io.dec_tlu_i0_kill_writeb_wb @[dec.scala 172:48] - decode.io.dec_tlu_flush_lower_wb <= tlu.io.tlu_bp.dec_tlu_flush_lower_wb @[dec.scala 173:48] - decode.io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[dec.scala 174:48] - decode.io.dec_tlu_flush_lower_r <= tlu.io.tlu_exu.dec_tlu_flush_lower_r @[dec.scala 175:48] - decode.io.dec_tlu_flush_pause_r <= tlu.io.dec_tlu_flush_pause_r @[dec.scala 176:48] - decode.io.dec_tlu_presync_d <= tlu.io.dec_tlu_presync_d @[dec.scala 177:48] - decode.io.dec_tlu_postsync_d <= tlu.io.dec_tlu_postsync_d @[dec.scala 178:48] - decode.io.dec_i0_pc4_d <= instbuff.io.dec_i0_pc4_d @[dec.scala 179:48] - decode.io.dec_csr_rddata_d <= tlu.io.dec_csr_rddata_d @[dec.scala 180:48] - decode.io.dec_csr_legal_d <= tlu.io.dec_csr_legal_d @[dec.scala 181:48] - decode.io.lsu_result_m <= io.lsu_result_m @[dec.scala 182:48] - decode.io.lsu_result_corr_r <= io.lsu_result_corr_r @[dec.scala 183:48] - decode.io.exu_flush_final <= io.exu_flush_final @[dec.scala 184:48] - decode.io.dec_i0_instr_d <= instbuff.io.dec_i0_instr_d @[dec.scala 185:48] - decode.io.dec_ib0_valid_d <= instbuff.io.dec_ib0_valid_d @[dec.scala 186:48] - decode.io.free_clk <= io.free_clk @[dec.scala 187:48] - decode.io.active_clk <= io.active_clk @[dec.scala 188:48] - decode.io.clk_override <= tlu.io.dec_tlu_dec_clk_override @[dec.scala 189:48] - decode.io.scan_mode <= io.scan_mode @[dec.scala 190:48] - dec_i0_inst_wb1 <= decode.io.dec_i0_inst_wb1 @[dec.scala 191:40] - dec_i0_pc_wb1 <= decode.io.dec_i0_pc_wb1 @[dec.scala 192:40] - io.lsu_p.bits.store_data_bypass_m <= decode.io.lsu_p.bits.store_data_bypass_m @[dec.scala 193:40] - io.lsu_p.bits.load_ldst_bypass_d <= decode.io.lsu_p.bits.load_ldst_bypass_d @[dec.scala 193:40] - io.lsu_p.bits.store_data_bypass_d <= decode.io.lsu_p.bits.store_data_bypass_d @[dec.scala 193:40] - io.lsu_p.bits.dma <= decode.io.lsu_p.bits.dma @[dec.scala 193:40] - io.lsu_p.bits.unsign <= decode.io.lsu_p.bits.unsign @[dec.scala 193:40] - io.lsu_p.bits.store <= decode.io.lsu_p.bits.store @[dec.scala 193:40] - io.lsu_p.bits.load <= decode.io.lsu_p.bits.load @[dec.scala 193:40] - io.lsu_p.bits.dword <= decode.io.lsu_p.bits.dword @[dec.scala 193:40] - io.lsu_p.bits.word <= decode.io.lsu_p.bits.word @[dec.scala 193:40] - io.lsu_p.bits.half <= decode.io.lsu_p.bits.half @[dec.scala 193:40] - io.lsu_p.bits.by <= decode.io.lsu_p.bits.by @[dec.scala 193:40] - io.lsu_p.bits.fast_int <= decode.io.lsu_p.bits.fast_int @[dec.scala 193:40] - io.lsu_p.valid <= decode.io.lsu_p.valid @[dec.scala 193:40] - io.dec_lsu_valid_raw_d <= decode.io.dec_lsu_valid_raw_d @[dec.scala 194:40] - io.dec_lsu_offset_d <= decode.io.dec_lsu_offset_d @[dec.scala 195:40] - io.dec_pause_state_cg <= decode.io.dec_pause_state_cg @[dec.scala 196:40] - gpr.io.raddr0 <= decode.io.dec_i0_rs1_d @[dec.scala 197:23] - gpr.io.raddr1 <= decode.io.dec_i0_rs2_d @[dec.scala 198:23] - gpr.io.wen0 <= decode.io.dec_i0_wen_r @[dec.scala 199:23] - gpr.io.waddr0 <= decode.io.dec_i0_waddr_r @[dec.scala 200:23] - gpr.io.wd0 <= decode.io.dec_i0_wdata_r @[dec.scala 201:23] - gpr.io.wen1 <= decode.io.dec_nonblock_load_wen @[dec.scala 202:23] - gpr.io.waddr1 <= decode.io.dec_nonblock_load_waddr @[dec.scala 203:23] - gpr.io.wd1 <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data @[dec.scala 204:23] - gpr.io.wen2 <= io.exu_div_wren @[dec.scala 205:23] - gpr.io.waddr2 <= decode.io.div_waddr_wb @[dec.scala 206:23] - gpr.io.wd2 <= io.exu_div_result @[dec.scala 207:23] - gpr.io.scan_mode <= io.scan_mode @[dec.scala 208:23] - io.dec_exu.gpr_exu.gpr_i0_rs2_d <= gpr.io.gpr_exu.gpr_i0_rs2_d @[dec.scala 209:22] - io.dec_exu.gpr_exu.gpr_i0_rs1_d <= gpr.io.gpr_exu.gpr_i0_rs1_d @[dec.scala 209:22] - tlu.io.tlu_mem.ifu_miss_state_idle <= io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle @[dec.scala 210:18] - tlu.io.tlu_mem.ifu_ic_debug_rd_data_valid <= io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[dec.scala 210:18] - tlu.io.tlu_mem.ifu_ic_debug_rd_data <= io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data @[dec.scala 210:18] - tlu.io.tlu_mem.ifu_iccm_rd_ecc_single_err <= io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[dec.scala 210:18] - tlu.io.tlu_mem.ifu_ic_error_start <= io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start @[dec.scala 210:18] - tlu.io.tlu_mem.ifu_pmu_bus_trxn <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn @[dec.scala 210:18] - tlu.io.tlu_mem.ifu_pmu_bus_busy <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy @[dec.scala 210:18] - tlu.io.tlu_mem.ifu_pmu_bus_error <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error @[dec.scala 210:18] - tlu.io.tlu_mem.ifu_pmu_ic_hit <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit @[dec.scala 210:18] - tlu.io.tlu_mem.ifu_pmu_ic_miss <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss @[dec.scala 210:18] - io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable <= tlu.io.tlu_mem.dec_tlu_core_ecc_disable @[dec.scala 210:18] - io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wr_valid @[dec.scala 210:18] - io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_rd_valid @[dec.scala 210:18] - io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_dicawics @[dec.scala 210:18] - io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wrdata @[dec.scala 210:18] - io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb <= tlu.io.tlu_mem.dec_tlu_fence_i_wb @[dec.scala 210:18] - io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt <= tlu.io.tlu_mem.dec_tlu_force_halt @[dec.scala 210:18] - io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= tlu.io.tlu_mem.dec_tlu_i0_commit_cmt @[dec.scala 210:18] - io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb <= tlu.io.tlu_mem.dec_tlu_flush_err_wb @[dec.scala 210:18] - io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_lower_wb <= tlu.io.tlu_mem.dec_tlu_flush_lower_wb @[dec.scala 210:18] - tlu.io.tlu_ifc.ifu_pmu_fetch_stall <= io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall @[dec.scala 211:18] - io.ifu_dec.dec_ifc.dec_tlu_mrac_ff <= tlu.io.tlu_ifc.dec_tlu_mrac_ff @[dec.scala 211:18] - io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb <= tlu.io.tlu_ifc.dec_tlu_flush_noredir_wb @[dec.scala 211:18] - io.ifu_dec.dec_bp.dec_tlu_bpred_disable <= tlu.io.tlu_bp.dec_tlu_bpred_disable @[dec.scala 212:18] - io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb <= tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb @[dec.scala 212:18] - io.ifu_dec.dec_bp.dec_tlu_flush_lower_wb <= tlu.io.tlu_bp.dec_tlu_flush_lower_wb @[dec.scala 212:18] - io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle @[dec.scala 212:18] - io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.way @[dec.scala 212:18] - io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[dec.scala 212:18] - io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error @[dec.scala 212:18] - io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist @[dec.scala 212:18] - io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.valid @[dec.scala 212:18] - tlu.io.tlu_exu.exu_npc_r <= io.dec_exu.tlu_exu.exu_npc_r @[dec.scala 213:18] - tlu.io.tlu_exu.exu_pmu_i0_pc4 <= io.dec_exu.tlu_exu.exu_pmu_i0_pc4 @[dec.scala 213:18] - tlu.io.tlu_exu.exu_pmu_i0_br_ataken <= io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken @[dec.scala 213:18] - tlu.io.tlu_exu.exu_pmu_i0_br_misp <= io.dec_exu.tlu_exu.exu_pmu_i0_br_misp @[dec.scala 213:18] - tlu.io.tlu_exu.exu_i0_br_middle_r <= io.dec_exu.tlu_exu.exu_i0_br_middle_r @[dec.scala 213:18] - tlu.io.tlu_exu.exu_i0_br_mp_r <= io.dec_exu.tlu_exu.exu_i0_br_mp_r @[dec.scala 213:18] - tlu.io.tlu_exu.exu_i0_br_valid_r <= io.dec_exu.tlu_exu.exu_i0_br_valid_r @[dec.scala 213:18] - tlu.io.tlu_exu.exu_i0_br_index_r <= io.dec_exu.tlu_exu.exu_i0_br_index_r @[dec.scala 213:18] - tlu.io.tlu_exu.exu_i0_br_start_error_r <= io.dec_exu.tlu_exu.exu_i0_br_start_error_r @[dec.scala 213:18] - tlu.io.tlu_exu.exu_i0_br_error_r <= io.dec_exu.tlu_exu.exu_i0_br_error_r @[dec.scala 213:18] - tlu.io.tlu_exu.exu_i0_br_hist_r <= io.dec_exu.tlu_exu.exu_i0_br_hist_r @[dec.scala 213:18] - io.dec_exu.tlu_exu.dec_tlu_flush_path_r <= tlu.io.tlu_exu.dec_tlu_flush_path_r @[dec.scala 213:18] - io.dec_exu.tlu_exu.dec_tlu_flush_lower_r <= tlu.io.tlu_exu.dec_tlu_flush_lower_r @[dec.scala 213:18] - io.dec_exu.tlu_exu.dec_tlu_meihap <= tlu.io.tlu_exu.dec_tlu_meihap @[dec.scala 213:18] - tlu.io.active_clk <= io.active_clk @[dec.scala 214:45] - tlu.io.free_clk <= io.free_clk @[dec.scala 215:45] - tlu.io.scan_mode <= io.scan_mode @[dec.scala 216:45] - tlu.io.rst_vec <= io.rst_vec @[dec.scala 217:45] - tlu.io.nmi_int <= io.nmi_int @[dec.scala 218:45] - tlu.io.nmi_vec <= io.nmi_vec @[dec.scala 219:45] - tlu.io.i_cpu_halt_req <= io.i_cpu_halt_req @[dec.scala 220:45] - tlu.io.i_cpu_run_req <= io.i_cpu_run_req @[dec.scala 221:45] - tlu.io.lsu_fastint_stall_any <= io.lsu_fastint_stall_any @[dec.scala 222:45] - tlu.io.ifu_pmu_instr_aligned <= io.ifu_dec.dec_aln.ifu_pmu_instr_aligned @[dec.scala 223:45] - tlu.io.dec_pmu_instr_decoded <= decode.io.dec_pmu_instr_decoded @[dec.scala 224:45] - tlu.io.dec_pmu_decode_stall <= decode.io.dec_pmu_decode_stall @[dec.scala 225:45] - tlu.io.dec_pmu_presync_stall <= decode.io.dec_pmu_presync_stall @[dec.scala 226:45] - tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_postsync_stall @[dec.scala 227:45] - tlu.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec.scala 228:45] - tlu.io.dma_dccm_stall_any <= io.dma_dccm_stall_any @[dec.scala 229:45] - tlu.io.dma_iccm_stall_any <= io.dma_iccm_stall_any @[dec.scala 230:45] - tlu.io.tlu_busbuff.lsu_imprecise_error_addr_any <= io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any @[dec.scala 231:26] - tlu.io.tlu_busbuff.lsu_imprecise_error_store_any <= io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any @[dec.scala 231:26] - tlu.io.tlu_busbuff.lsu_imprecise_error_load_any <= io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any @[dec.scala 231:26] - io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= tlu.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[dec.scala 231:26] - io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable <= tlu.io.tlu_busbuff.dec_tlu_wb_coalescing_disable @[dec.scala 231:26] - io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable <= tlu.io.tlu_busbuff.dec_tlu_external_ldfwd_disable @[dec.scala 231:26] - tlu.io.tlu_busbuff.lsu_pmu_bus_busy <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy @[dec.scala 231:26] - tlu.io.tlu_busbuff.lsu_pmu_bus_error <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error @[dec.scala 231:26] - tlu.io.tlu_busbuff.lsu_pmu_bus_misaligned <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned @[dec.scala 231:26] - tlu.io.tlu_busbuff.lsu_pmu_bus_trxn <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn @[dec.scala 231:26] - tlu.io.lsu_tlu.lsu_pmu_store_external_m <= io.lsu_tlu.lsu_pmu_store_external_m @[dec.scala 232:14] - tlu.io.lsu_tlu.lsu_pmu_load_external_m <= io.lsu_tlu.lsu_pmu_load_external_m @[dec.scala 232:14] - tlu.io.dma_pmu_dccm_read <= io.dma_pmu_dccm_read @[dec.scala 233:45] - tlu.io.dma_pmu_dccm_write <= io.dma_pmu_dccm_write @[dec.scala 234:45] - tlu.io.dma_pmu_any_read <= io.dma_pmu_any_read @[dec.scala 235:45] - tlu.io.dma_pmu_any_write <= io.dma_pmu_any_write @[dec.scala 236:45] - tlu.io.lsu_fir_addr <= io.lsu_fir_addr @[dec.scala 237:45] - tlu.io.lsu_fir_error <= io.lsu_fir_error @[dec.scala 238:45] - tlu.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[dec.scala 239:45] - tlu.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec.scala 240:45] - tlu.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec.scala 240:45] - tlu.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec.scala 240:45] - tlu.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec.scala 240:45] - tlu.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec.scala 240:45] - tlu.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec.scala 240:45] - tlu.io.lsu_single_ecc_error_incr <= io.lsu_single_ecc_error_incr @[dec.scala 241:45] - tlu.io.dec_pause_state <= decode.io.dec_pause_state @[dec.scala 242:45] - tlu.io.dec_csr_wen_unq_d <= decode.io.dec_csr_wen_unq_d @[dec.scala 243:45] - tlu.io.dec_csr_any_unq_d <= decode.io.dec_csr_any_unq_d @[dec.scala 244:45] - tlu.io.dec_csr_rdaddr_d <= decode.io.dec_csr_rdaddr_d @[dec.scala 245:45] - tlu.io.dec_csr_wen_r <= decode.io.dec_csr_wen_r @[dec.scala 246:45] - tlu.io.dec_csr_wraddr_r <= decode.io.dec_csr_wraddr_r @[dec.scala 247:45] - tlu.io.dec_csr_wrdata_r <= decode.io.dec_csr_wrdata_r @[dec.scala 248:45] - tlu.io.dec_csr_stall_int_ff <= decode.io.dec_csr_stall_int_ff @[dec.scala 249:45] - tlu.io.dec_tlu_i0_valid_r <= decode.io.dec_tlu_i0_valid_r @[dec.scala 250:45] - tlu.io.dec_tlu_i0_pc_r <= decode.io.dec_tlu_i0_pc_r @[dec.scala 251:45] - tlu.io.dec_tlu_packet_r.pmu_lsu_misaligned <= decode.io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec.scala 252:45] - tlu.io.dec_tlu_packet_r.pmu_divide <= decode.io.dec_tlu_packet_r.pmu_divide @[dec.scala 252:45] - tlu.io.dec_tlu_packet_r.pmu_i0_br_unpred <= decode.io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec.scala 252:45] - tlu.io.dec_tlu_packet_r.pmu_i0_itype <= decode.io.dec_tlu_packet_r.pmu_i0_itype @[dec.scala 252:45] - tlu.io.dec_tlu_packet_r.i0trigger <= decode.io.dec_tlu_packet_r.i0trigger @[dec.scala 252:45] - tlu.io.dec_tlu_packet_r.fence_i <= decode.io.dec_tlu_packet_r.fence_i @[dec.scala 252:45] - tlu.io.dec_tlu_packet_r.icaf_type <= decode.io.dec_tlu_packet_r.icaf_type @[dec.scala 252:45] - tlu.io.dec_tlu_packet_r.icaf_f1 <= decode.io.dec_tlu_packet_r.icaf_f1 @[dec.scala 252:45] - tlu.io.dec_tlu_packet_r.icaf <= decode.io.dec_tlu_packet_r.icaf @[dec.scala 252:45] - tlu.io.dec_tlu_packet_r.legal <= decode.io.dec_tlu_packet_r.legal @[dec.scala 252:45] - tlu.io.dec_illegal_inst <= decode.io.dec_illegal_inst @[dec.scala 253:45] - tlu.io.dec_i0_decode_d <= decode.io.dec_aln.dec_i0_decode_d @[dec.scala 254:45] - tlu.io.exu_i0_br_way_r <= io.exu_i0_br_way_r @[dec.scala 255:45] - tlu.io.dbg_halt_req <= io.dbg_halt_req @[dec.scala 256:45] - tlu.io.dbg_resume_req <= io.dbg_resume_req @[dec.scala 257:45] - tlu.io.lsu_idle_any <= io.lsu_idle_any @[dec.scala 258:45] - tlu.io.dec_div_active <= decode.io.dec_div_active @[dec.scala 259:45] - tlu.io.pic_claimid <= io.pic_claimid @[dec.scala 260:45] - tlu.io.pic_pl <= io.pic_pl @[dec.scala 261:45] - tlu.io.mhwakeup <= io.mhwakeup @[dec.scala 262:45] - tlu.io.mexintpend <= io.mexintpend @[dec.scala 263:45] - tlu.io.timer_int <= io.timer_int @[dec.scala 264:45] - tlu.io.soft_int <= io.soft_int @[dec.scala 265:45] - tlu.io.core_id <= io.core_id @[dec.scala 266:45] - tlu.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[dec.scala 267:45] - tlu.io.mpc_debug_run_req <= io.mpc_debug_run_req @[dec.scala 268:45] - tlu.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec.scala 269:45] - io.dec_dbg_cmd_done <= tlu.io.dec_dbg_cmd_done @[dec.scala 270:28] - io.dec_dbg_cmd_fail <= tlu.io.dec_dbg_cmd_fail @[dec.scala 271:28] - io.dec_tlu_dbg_halted <= tlu.io.dec_tlu_dbg_halted @[dec.scala 272:28] - io.dec_tlu_debug_mode <= tlu.io.dec_tlu_debug_mode @[dec.scala 273:28] - io.dec_tlu_resume_ack <= tlu.io.dec_tlu_resume_ack @[dec.scala 274:28] - io.dec_tlu_mpc_halted_only <= tlu.io.dec_tlu_mpc_halted_only @[dec.scala 275:51] - io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[dec.scala 276:29] - io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[dec.scala 276:29] - io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[dec.scala 276:29] - io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[dec.scala 276:29] - io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[dec.scala 276:29] - io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[dec.scala 276:29] - io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[dec.scala 276:29] - io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[dec.scala 276:29] - io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[dec.scala 276:29] - io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[dec.scala 276:29] - io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[dec.scala 276:29] - io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[dec.scala 276:29] - io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[dec.scala 276:29] - io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[dec.scala 276:29] - io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[dec.scala 276:29] - io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[dec.scala 276:29] - io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[dec.scala 276:29] - io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[dec.scala 276:29] - io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[dec.scala 276:29] - io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[dec.scala 276:29] - io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[dec.scala 276:29] - io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[dec.scala 276:29] - io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[dec.scala 276:29] - io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[dec.scala 276:29] - io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[dec.scala 276:29] - io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[dec.scala 276:29] - io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[dec.scala 276:29] - io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[dec.scala 276:29] - io.o_cpu_halt_status <= tlu.io.o_cpu_halt_status @[dec.scala 277:29] - io.o_cpu_halt_ack <= tlu.io.o_cpu_halt_ack @[dec.scala 278:29] - io.o_cpu_run_ack <= tlu.io.o_cpu_run_ack @[dec.scala 279:29] - io.o_debug_mode_status <= tlu.io.o_debug_mode_status @[dec.scala 280:29] - io.mpc_debug_halt_ack <= tlu.io.mpc_debug_halt_ack @[dec.scala 281:29] - io.mpc_debug_run_ack <= tlu.io.mpc_debug_run_ack @[dec.scala 282:29] - io.debug_brkpt_status <= tlu.io.debug_brkpt_status @[dec.scala 283:29] - io.dec_tlu_meicurpl <= tlu.io.dec_tlu_meicurpl @[dec.scala 284:29] - io.dec_tlu_meipt <= tlu.io.dec_tlu_meipt @[dec.scala 285:29] - io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[dec.scala 286:34] - io.dec_tlu_perfcnt0 <= tlu.io.dec_tlu_perfcnt0 @[dec.scala 287:29] - io.dec_tlu_perfcnt1 <= tlu.io.dec_tlu_perfcnt1 @[dec.scala 288:29] - io.dec_tlu_perfcnt2 <= tlu.io.dec_tlu_perfcnt2 @[dec.scala 289:29] - io.dec_tlu_perfcnt3 <= tlu.io.dec_tlu_perfcnt3 @[dec.scala 290:29] - dec_tlu_i0_exc_valid_wb1 <= tlu.io.dec_tlu_i0_exc_valid_wb1 @[dec.scala 291:32] - dec_tlu_i0_valid_wb1 <= tlu.io.dec_tlu_i0_valid_wb1 @[dec.scala 292:32] - dec_tlu_int_valid_wb1 <= tlu.io.dec_tlu_int_valid_wb1 @[dec.scala 293:32] - dec_tlu_exc_cause_wb1 <= tlu.io.dec_tlu_exc_cause_wb1 @[dec.scala 294:32] - dec_tlu_mtval_wb1 <= tlu.io.dec_tlu_mtval_wb1 @[dec.scala 295:32] - io.dec_tlu_dma_qos_prty <= tlu.io.dec_tlu_dma_qos_prty @[dec.scala 296:35] - io.dec_tlu_misc_clk_override <= tlu.io.dec_tlu_misc_clk_override @[dec.scala 297:35] - io.dec_tlu_ifu_clk_override <= tlu.io.dec_tlu_ifu_clk_override @[dec.scala 298:36] - io.dec_tlu_lsu_clk_override <= tlu.io.dec_tlu_lsu_clk_override @[dec.scala 299:36] - io.dec_tlu_bus_clk_override <= tlu.io.dec_tlu_bus_clk_override @[dec.scala 300:36] - io.dec_tlu_pic_clk_override <= tlu.io.dec_tlu_pic_clk_override @[dec.scala 301:36] - io.dec_tlu_dccm_clk_override <= tlu.io.dec_tlu_dccm_clk_override @[dec.scala 302:36] - io.dec_tlu_icm_clk_override <= tlu.io.dec_tlu_icm_clk_override @[dec.scala 303:36] - io.rv_trace_pkt.rv_i_insn_ip <= decode.io.dec_i0_inst_wb1 @[dec.scala 307:32] + instbuff.io.ifu_ib.i0_brp.bits.ret <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret @[dec.scala 125:22] + instbuff.io.ifu_ib.i0_brp.bits.way <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way @[dec.scala 125:22] + instbuff.io.ifu_ib.i0_brp.bits.prett <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett @[dec.scala 125:22] + instbuff.io.ifu_ib.i0_brp.bits.bank <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank @[dec.scala 125:22] + instbuff.io.ifu_ib.i0_brp.bits.br_start_error <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error @[dec.scala 125:22] + instbuff.io.ifu_ib.i0_brp.bits.br_error <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error @[dec.scala 125:22] + instbuff.io.ifu_ib.i0_brp.bits.hist <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist @[dec.scala 125:22] + instbuff.io.ifu_ib.i0_brp.bits.toffset <= io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset @[dec.scala 125:22] + instbuff.io.ifu_ib.i0_brp.valid <= io.ifu_dec.dec_aln.aln_ib.i0_brp.valid @[dec.scala 125:22] + instbuff.io.ifu_ib.ifu_i0_pc4 <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 @[dec.scala 125:22] + instbuff.io.ifu_ib.ifu_i0_pc <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc @[dec.scala 125:22] + instbuff.io.ifu_ib.ifu_i0_instr <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr @[dec.scala 125:22] + instbuff.io.ifu_ib.ifu_i0_valid <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid @[dec.scala 125:22] + instbuff.io.ifu_ib.ifu_i0_bp_btag <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag @[dec.scala 125:22] + instbuff.io.ifu_ib.ifu_i0_bp_fghr <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr @[dec.scala 125:22] + instbuff.io.ifu_ib.ifu_i0_bp_index <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index @[dec.scala 125:22] + instbuff.io.ifu_ib.ifu_i0_dbecc <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc @[dec.scala 125:22] + instbuff.io.ifu_ib.ifu_i0_icaf_f1 <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 @[dec.scala 125:22] + instbuff.io.ifu_ib.ifu_i0_icaf_type <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type @[dec.scala 125:22] + instbuff.io.ifu_ib.ifu_i0_icaf <= io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf @[dec.scala 125:22] + io.dec_exu.ib_exu.dec_debug_wdata_rs1_d <= instbuff.io.ib_exu.dec_debug_wdata_rs1_d @[dec.scala 126:22] + io.dec_exu.ib_exu.dec_i0_pc_d <= instbuff.io.ib_exu.dec_i0_pc_d @[dec.scala 126:22] + instbuff.io.dbg_ib.dbg_cmd_addr <= io.dec_dbg.dbg_ib.dbg_cmd_addr @[dec.scala 127:22] + instbuff.io.dbg_ib.dbg_cmd_type <= io.dec_dbg.dbg_ib.dbg_cmd_type @[dec.scala 127:22] + instbuff.io.dbg_ib.dbg_cmd_write <= io.dec_dbg.dbg_ib.dbg_cmd_write @[dec.scala 127:22] + instbuff.io.dbg_ib.dbg_cmd_valid <= io.dec_dbg.dbg_ib.dbg_cmd_valid @[dec.scala 127:22] + dec_trigger.io.dec_i0_pc_d <= instbuff.io.ib_exu.dec_i0_pc_d @[dec.scala 128:30] + dec_trigger.io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[dec.scala 129:34] + dec_trigger.io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[dec.scala 129:34] + decode.io.dec_aln.ifu_i0_cinst <= io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst @[dec.scala 133:21] + io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d <= decode.io.dec_aln.dec_i0_decode_d @[dec.scala 133:21] + decode.io.decode_exu.exu_csr_rs1_x <= io.dec_exu.decode_exu.exu_csr_rs1_x @[dec.scala 135:23] + decode.io.decode_exu.exu_i0_result_x <= io.dec_exu.decode_exu.exu_i0_result_x @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_extint_stall <= decode.io.decode_exu.dec_extint_stall @[dec.scala 135:23] + io.dec_exu.decode_exu.pred_correct_npc_x <= decode.io.decode_exu.pred_correct_npc_x @[dec.scala 135:23] + io.dec_exu.decode_exu.mul_p.bits.bfp <= decode.io.decode_exu.mul_p.bits.bfp @[dec.scala 135:23] + io.dec_exu.decode_exu.mul_p.bits.crc32c_w <= decode.io.decode_exu.mul_p.bits.crc32c_w @[dec.scala 135:23] + io.dec_exu.decode_exu.mul_p.bits.crc32c_h <= decode.io.decode_exu.mul_p.bits.crc32c_h @[dec.scala 135:23] + io.dec_exu.decode_exu.mul_p.bits.crc32c_b <= decode.io.decode_exu.mul_p.bits.crc32c_b @[dec.scala 135:23] + io.dec_exu.decode_exu.mul_p.bits.crc32_w <= decode.io.decode_exu.mul_p.bits.crc32_w @[dec.scala 135:23] + io.dec_exu.decode_exu.mul_p.bits.crc32_h <= decode.io.decode_exu.mul_p.bits.crc32_h @[dec.scala 135:23] + io.dec_exu.decode_exu.mul_p.bits.crc32_b <= decode.io.decode_exu.mul_p.bits.crc32_b @[dec.scala 135:23] + io.dec_exu.decode_exu.mul_p.bits.unshfl <= decode.io.decode_exu.mul_p.bits.unshfl @[dec.scala 135:23] + io.dec_exu.decode_exu.mul_p.bits.shfl <= decode.io.decode_exu.mul_p.bits.shfl @[dec.scala 135:23] + io.dec_exu.decode_exu.mul_p.bits.grev <= decode.io.decode_exu.mul_p.bits.grev @[dec.scala 135:23] + io.dec_exu.decode_exu.mul_p.bits.clmulr <= decode.io.decode_exu.mul_p.bits.clmulr @[dec.scala 135:23] + io.dec_exu.decode_exu.mul_p.bits.clmulh <= decode.io.decode_exu.mul_p.bits.clmulh @[dec.scala 135:23] + io.dec_exu.decode_exu.mul_p.bits.clmul <= decode.io.decode_exu.mul_p.bits.clmul @[dec.scala 135:23] + io.dec_exu.decode_exu.mul_p.bits.bdep <= decode.io.decode_exu.mul_p.bits.bdep @[dec.scala 135:23] + io.dec_exu.decode_exu.mul_p.bits.bext <= decode.io.decode_exu.mul_p.bits.bext @[dec.scala 135:23] + io.dec_exu.decode_exu.mul_p.bits.low <= decode.io.decode_exu.mul_p.bits.low @[dec.scala 135:23] + io.dec_exu.decode_exu.mul_p.bits.rs2_sign <= decode.io.decode_exu.mul_p.bits.rs2_sign @[dec.scala 135:23] + io.dec_exu.decode_exu.mul_p.bits.rs1_sign <= decode.io.decode_exu.mul_p.bits.rs1_sign @[dec.scala 135:23] + io.dec_exu.decode_exu.mul_p.valid <= decode.io.decode_exu.mul_p.valid @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d <= decode.io.decode_exu.dec_i0_rs2_bypass_en_d @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d <= decode.io.decode_exu.dec_i0_rs1_bypass_en_d @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_select_pc_d <= decode.io.decode_exu.dec_i0_select_pc_d @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d <= decode.io.decode_exu.dec_i0_rs2_bypass_data_d @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d <= decode.io.decode_exu.dec_i0_rs1_bypass_data_d @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_immed_d <= decode.io.decode_exu.dec_i0_immed_d @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_rs2_en_d <= decode.io.decode_exu.dec_i0_rs2_en_d @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_rs1_en_d <= decode.io.decode_exu.dec_i0_rs1_en_d @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_predict_btag_d <= decode.io.decode_exu.i0_predict_btag_d @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_predict_index_d <= decode.io.decode_exu.i0_predict_index_d @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_predict_fghr_d <= decode.io.decode_exu.i0_predict_fghr_d @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way <= decode.io.decode_exu.dec_i0_predict_p_d.bits.way @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pja @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pret @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pcall @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett <= decode.io.decode_exu.dec_i0_predict_p_d.bits.prett @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= decode.io.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error <= decode.io.decode_exu.dec_i0_predict_p_d.bits.br_error @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset <= decode.io.decode_exu.dec_i0_predict_p_d.bits.toffset @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist <= decode.io.decode_exu.dec_i0_predict_p_d.bits.hist @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 <= decode.io.decode_exu.dec_i0_predict_p_d.bits.pc4 @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset <= decode.io.decode_exu.dec_i0_predict_p_d.bits.boffset @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken <= decode.io.decode_exu.dec_i0_predict_p_d.bits.ataken @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp <= decode.io.decode_exu.dec_i0_predict_p_d.bits.misp @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_i0_predict_p_d.valid <= decode.io.decode_exu.dec_i0_predict_p_d.valid @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_ap.csr_imm <= decode.io.decode_exu.i0_ap.csr_imm @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_ap.csr_write <= decode.io.decode_exu.i0_ap.csr_write @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_ap.predict_nt <= decode.io.decode_exu.i0_ap.predict_nt @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_ap.predict_t <= decode.io.decode_exu.i0_ap.predict_t @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_ap.jal <= decode.io.decode_exu.i0_ap.jal @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_ap.unsign <= decode.io.decode_exu.i0_ap.unsign @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_ap.slt <= decode.io.decode_exu.i0_ap.slt @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_ap.sub <= decode.io.decode_exu.i0_ap.sub @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_ap.add <= decode.io.decode_exu.i0_ap.add @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_ap.bge <= decode.io.decode_exu.i0_ap.bge @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_ap.blt <= decode.io.decode_exu.i0_ap.blt @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_ap.bne <= decode.io.decode_exu.i0_ap.bne @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_ap.beq <= decode.io.decode_exu.i0_ap.beq @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_ap.sra <= decode.io.decode_exu.i0_ap.sra @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_ap.srl <= decode.io.decode_exu.i0_ap.srl @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_ap.sll <= decode.io.decode_exu.i0_ap.sll @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_ap.lxor <= decode.io.decode_exu.i0_ap.lxor @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_ap.lor <= decode.io.decode_exu.i0_ap.lor @[dec.scala 135:23] + io.dec_exu.decode_exu.i0_ap.land <= decode.io.decode_exu.i0_ap.land @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_ctl_en <= decode.io.decode_exu.dec_ctl_en @[dec.scala 135:23] + io.dec_exu.decode_exu.dec_data_en <= decode.io.decode_exu.dec_data_en @[dec.scala 135:23] + decode.io.dec_alu.exu_i0_pc_x <= io.dec_exu.dec_alu.exu_i0_pc_x @[dec.scala 136:20] + io.dec_exu.dec_alu.dec_i0_br_immed_d <= decode.io.dec_alu.dec_i0_br_immed_d @[dec.scala 136:20] + io.dec_exu.dec_alu.dec_csr_ren_d <= decode.io.dec_alu.dec_csr_ren_d @[dec.scala 136:20] + io.dec_exu.dec_alu.dec_i0_alu_decode_d <= decode.io.dec_alu.dec_i0_alu_decode_d @[dec.scala 136:20] + io.dec_exu.dec_div.dec_div_cancel <= decode.io.dec_div.dec_div_cancel @[dec.scala 137:20] + io.dec_exu.dec_div.div_p.bits.rem <= decode.io.dec_div.div_p.bits.rem @[dec.scala 137:20] + io.dec_exu.dec_div.div_p.bits.unsign <= decode.io.dec_div.div_p.bits.unsign @[dec.scala 137:20] + io.dec_exu.dec_div.div_p.valid <= decode.io.dec_div.div_p.valid @[dec.scala 137:20] + decode.io.dctl_dma.dma_dccm_stall_any <= io.dec_dma.dctl_dma.dma_dccm_stall_any @[dec.scala 138:22] + decode.io.dec_tlu_flush_extint <= tlu.io.dec_tlu_flush_extint @[dec.scala 139:48] + decode.io.dec_tlu_force_halt <= tlu.io.tlu_mem.dec_tlu_force_halt @[dec.scala 140:48] + decode.io.dctl_busbuff.lsu_nonblock_load_data <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data @[dec.scala 141:26] + decode.io.dctl_busbuff.lsu_nonblock_load_data_tag <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag @[dec.scala 141:26] + decode.io.dctl_busbuff.lsu_nonblock_load_data_error <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error @[dec.scala 141:26] + decode.io.dctl_busbuff.lsu_nonblock_load_data_valid <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid @[dec.scala 141:26] + decode.io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[dec.scala 141:26] + decode.io.dctl_busbuff.lsu_nonblock_load_inv_r <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r @[dec.scala 141:26] + decode.io.dctl_busbuff.lsu_nonblock_load_tag_m <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m @[dec.scala 141:26] + decode.io.dctl_busbuff.lsu_nonblock_load_valid_m <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m @[dec.scala 141:26] + decode.io.dec_i0_trigger_match_d <= dec_trigger.io.dec_i0_trigger_match_d @[dec.scala 142:48] + decode.io.dec_tlu_wr_pause_r <= tlu.io.dec_tlu_wr_pause_r @[dec.scala 143:48] + decode.io.dec_tlu_pipelining_disable <= tlu.io.dec_tlu_pipelining_disable @[dec.scala 144:48] + decode.io.lsu_trigger_match_m <= io.lsu_trigger_match_m @[dec.scala 145:48] + decode.io.lsu_pmu_misaligned_m <= io.lsu_pmu_misaligned_m @[dec.scala 146:48] + decode.io.dec_tlu_debug_stall <= tlu.io.dec_tlu_debug_stall @[dec.scala 147:48] + decode.io.dec_tlu_flush_leak_one_r <= tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb @[dec.scala 148:48] + decode.io.dec_debug_fence_d <= instbuff.io.dec_debug_fence_d @[dec.scala 149:48] + decode.io.dbg_dctl.dbg_cmd_wrdata <= io.dec_dbg.dbg_dctl.dbg_cmd_wrdata @[dec.scala 150:22] + decode.io.dec_i0_icaf_d <= instbuff.io.dec_i0_icaf_d @[dec.scala 151:48] + decode.io.dec_i0_icaf_f1_d <= instbuff.io.dec_i0_icaf_f1_d @[dec.scala 152:48] + decode.io.dec_i0_icaf_type_d <= instbuff.io.dec_i0_icaf_type_d @[dec.scala 153:48] + decode.io.dec_i0_dbecc_d <= instbuff.io.dec_i0_dbecc_d @[dec.scala 154:48] + decode.io.dec_i0_brp.bits.ret <= instbuff.io.dec_i0_brp.bits.ret @[dec.scala 155:48] + decode.io.dec_i0_brp.bits.way <= instbuff.io.dec_i0_brp.bits.way @[dec.scala 155:48] + decode.io.dec_i0_brp.bits.prett <= instbuff.io.dec_i0_brp.bits.prett @[dec.scala 155:48] + decode.io.dec_i0_brp.bits.bank <= instbuff.io.dec_i0_brp.bits.bank @[dec.scala 155:48] + decode.io.dec_i0_brp.bits.br_start_error <= instbuff.io.dec_i0_brp.bits.br_start_error @[dec.scala 155:48] + decode.io.dec_i0_brp.bits.br_error <= instbuff.io.dec_i0_brp.bits.br_error @[dec.scala 155:48] + decode.io.dec_i0_brp.bits.hist <= instbuff.io.dec_i0_brp.bits.hist @[dec.scala 155:48] + decode.io.dec_i0_brp.bits.toffset <= instbuff.io.dec_i0_brp.bits.toffset @[dec.scala 155:48] + decode.io.dec_i0_brp.valid <= instbuff.io.dec_i0_brp.valid @[dec.scala 155:48] + decode.io.dec_i0_bp_index <= instbuff.io.dec_i0_bp_index @[dec.scala 156:48] + decode.io.dec_i0_bp_fghr <= instbuff.io.dec_i0_bp_fghr @[dec.scala 157:48] + decode.io.dec_i0_bp_btag <= instbuff.io.dec_i0_bp_btag @[dec.scala 158:48] + decode.io.dec_i0_pc_d <= instbuff.io.ib_exu.dec_i0_pc_d @[dec.scala 159:48] + decode.io.lsu_idle_any <= io.lsu_idle_any @[dec.scala 160:48] + decode.io.lsu_load_stall_any <= io.lsu_load_stall_any @[dec.scala 161:48] + decode.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec.scala 162:48] + decode.io.exu_div_wren <= io.exu_div_wren @[dec.scala 163:48] + decode.io.dec_tlu_i0_kill_writeb_wb <= tlu.io.dec_tlu_i0_kill_writeb_wb @[dec.scala 164:48] + decode.io.dec_tlu_flush_lower_wb <= tlu.io.dec_tlu_flush_lower_wb @[dec.scala 165:48] + decode.io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[dec.scala 166:48] + decode.io.dec_tlu_flush_lower_r <= tlu.io.tlu_exu.dec_tlu_flush_lower_r @[dec.scala 167:48] + decode.io.dec_tlu_flush_pause_r <= tlu.io.dec_tlu_flush_pause_r @[dec.scala 168:48] + decode.io.dec_tlu_presync_d <= tlu.io.dec_tlu_presync_d @[dec.scala 169:48] + decode.io.dec_tlu_postsync_d <= tlu.io.dec_tlu_postsync_d @[dec.scala 170:48] + decode.io.dec_i0_pc4_d <= instbuff.io.dec_i0_pc4_d @[dec.scala 171:48] + decode.io.dec_csr_rddata_d <= tlu.io.dec_csr_rddata_d @[dec.scala 172:48] + decode.io.dec_csr_legal_d <= tlu.io.dec_csr_legal_d @[dec.scala 173:48] + decode.io.lsu_result_m <= io.lsu_result_m @[dec.scala 174:48] + decode.io.lsu_result_corr_r <= io.lsu_result_corr_r @[dec.scala 175:48] + decode.io.exu_flush_final <= io.exu_flush_final @[dec.scala 176:48] + decode.io.dec_i0_instr_d <= instbuff.io.dec_i0_instr_d @[dec.scala 177:48] + decode.io.dec_ib0_valid_d <= instbuff.io.dec_ib0_valid_d @[dec.scala 178:48] + decode.io.free_clk <= io.free_clk @[dec.scala 179:48] + decode.io.active_clk <= io.active_clk @[dec.scala 180:48] + decode.io.clk_override <= tlu.io.dec_tlu_dec_clk_override @[dec.scala 181:48] + decode.io.scan_mode <= io.scan_mode @[dec.scala 182:48] + dec_i0_inst_wb1 <= decode.io.dec_i0_inst_wb1 @[dec.scala 183:40] + dec_i0_pc_wb1 <= decode.io.dec_i0_pc_wb1 @[dec.scala 184:40] + io.lsu_p.bits.store_data_bypass_m <= decode.io.lsu_p.bits.store_data_bypass_m @[dec.scala 185:40] + io.lsu_p.bits.load_ldst_bypass_d <= decode.io.lsu_p.bits.load_ldst_bypass_d @[dec.scala 185:40] + io.lsu_p.bits.store_data_bypass_d <= decode.io.lsu_p.bits.store_data_bypass_d @[dec.scala 185:40] + io.lsu_p.bits.dma <= decode.io.lsu_p.bits.dma @[dec.scala 185:40] + io.lsu_p.bits.unsign <= decode.io.lsu_p.bits.unsign @[dec.scala 185:40] + io.lsu_p.bits.store <= decode.io.lsu_p.bits.store @[dec.scala 185:40] + io.lsu_p.bits.load <= decode.io.lsu_p.bits.load @[dec.scala 185:40] + io.lsu_p.bits.dword <= decode.io.lsu_p.bits.dword @[dec.scala 185:40] + io.lsu_p.bits.word <= decode.io.lsu_p.bits.word @[dec.scala 185:40] + io.lsu_p.bits.half <= decode.io.lsu_p.bits.half @[dec.scala 185:40] + io.lsu_p.bits.by <= decode.io.lsu_p.bits.by @[dec.scala 185:40] + io.lsu_p.bits.fast_int <= decode.io.lsu_p.bits.fast_int @[dec.scala 185:40] + io.lsu_p.valid <= decode.io.lsu_p.valid @[dec.scala 185:40] + io.dec_lsu_valid_raw_d <= decode.io.dec_lsu_valid_raw_d @[dec.scala 186:40] + io.dec_lsu_offset_d <= decode.io.dec_lsu_offset_d @[dec.scala 187:40] + io.dec_pause_state_cg <= decode.io.dec_pause_state_cg @[dec.scala 188:40] + gpr.io.raddr0 <= decode.io.dec_i0_rs1_d @[dec.scala 189:23] + gpr.io.raddr1 <= decode.io.dec_i0_rs2_d @[dec.scala 190:23] + gpr.io.wen0 <= decode.io.dec_i0_wen_r @[dec.scala 191:23] + gpr.io.waddr0 <= decode.io.dec_i0_waddr_r @[dec.scala 192:23] + gpr.io.wd0 <= decode.io.dec_i0_wdata_r @[dec.scala 193:23] + gpr.io.wen1 <= decode.io.dec_nonblock_load_wen @[dec.scala 194:23] + gpr.io.waddr1 <= decode.io.dec_nonblock_load_waddr @[dec.scala 195:23] + gpr.io.wd1 <= io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data @[dec.scala 196:23] + gpr.io.wen2 <= io.exu_div_wren @[dec.scala 197:23] + gpr.io.waddr2 <= decode.io.div_waddr_wb @[dec.scala 198:23] + gpr.io.wd2 <= io.exu_div_result @[dec.scala 199:23] + gpr.io.scan_mode <= io.scan_mode @[dec.scala 200:23] + io.dec_exu.gpr_exu.gpr_i0_rs2_d <= gpr.io.gpr_exu.gpr_i0_rs2_d @[dec.scala 201:22] + io.dec_exu.gpr_exu.gpr_i0_rs1_d <= gpr.io.gpr_exu.gpr_i0_rs1_d @[dec.scala 201:22] + tlu.io.tlu_mem.ifu_miss_state_idle <= io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle @[dec.scala 202:18] + tlu.io.tlu_mem.ifu_ic_debug_rd_data_valid <= io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[dec.scala 202:18] + tlu.io.tlu_mem.ifu_ic_debug_rd_data <= io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data @[dec.scala 202:18] + tlu.io.tlu_mem.ifu_iccm_rd_ecc_single_err <= io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[dec.scala 202:18] + tlu.io.tlu_mem.ifu_ic_error_start <= io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start @[dec.scala 202:18] + tlu.io.tlu_mem.ifu_pmu_bus_trxn <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn @[dec.scala 202:18] + tlu.io.tlu_mem.ifu_pmu_bus_busy <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy @[dec.scala 202:18] + tlu.io.tlu_mem.ifu_pmu_bus_error <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error @[dec.scala 202:18] + tlu.io.tlu_mem.ifu_pmu_ic_hit <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit @[dec.scala 202:18] + tlu.io.tlu_mem.ifu_pmu_ic_miss <= io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss @[dec.scala 202:18] + io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable <= tlu.io.tlu_mem.dec_tlu_core_ecc_disable @[dec.scala 202:18] + io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wr_valid @[dec.scala 202:18] + io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_rd_valid @[dec.scala 202:18] + io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_dicawics @[dec.scala 202:18] + io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= tlu.io.tlu_mem.dec_tlu_ic_diag_pkt.icache_wrdata @[dec.scala 202:18] + io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb <= tlu.io.tlu_mem.dec_tlu_fence_i_wb @[dec.scala 202:18] + io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt <= tlu.io.tlu_mem.dec_tlu_force_halt @[dec.scala 202:18] + io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= tlu.io.tlu_mem.dec_tlu_i0_commit_cmt @[dec.scala 202:18] + io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb <= tlu.io.tlu_mem.dec_tlu_flush_err_wb @[dec.scala 202:18] + tlu.io.tlu_ifc.ifu_pmu_fetch_stall <= io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall @[dec.scala 203:18] + io.ifu_dec.dec_ifc.dec_tlu_mrac_ff <= tlu.io.tlu_ifc.dec_tlu_mrac_ff @[dec.scala 203:18] + io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb <= tlu.io.tlu_ifc.dec_tlu_flush_noredir_wb @[dec.scala 203:18] + io.ifu_dec.dec_bp.dec_tlu_bpred_disable <= tlu.io.tlu_bp.dec_tlu_bpred_disable @[dec.scala 204:18] + io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb <= tlu.io.tlu_bp.dec_tlu_flush_leak_one_wb @[dec.scala 204:18] + io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.middle @[dec.scala 204:18] + io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.way @[dec.scala 204:18] + io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[dec.scala 204:18] + io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.br_error @[dec.scala 204:18] + io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.bits.hist @[dec.scala 204:18] + io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid <= tlu.io.tlu_bp.dec_tlu_br0_r_pkt.valid @[dec.scala 204:18] + tlu.io.tlu_exu.exu_npc_r <= io.dec_exu.tlu_exu.exu_npc_r @[dec.scala 205:18] + tlu.io.tlu_exu.exu_pmu_i0_pc4 <= io.dec_exu.tlu_exu.exu_pmu_i0_pc4 @[dec.scala 205:18] + tlu.io.tlu_exu.exu_pmu_i0_br_ataken <= io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken @[dec.scala 205:18] + tlu.io.tlu_exu.exu_pmu_i0_br_misp <= io.dec_exu.tlu_exu.exu_pmu_i0_br_misp @[dec.scala 205:18] + tlu.io.tlu_exu.exu_i0_br_middle_r <= io.dec_exu.tlu_exu.exu_i0_br_middle_r @[dec.scala 205:18] + tlu.io.tlu_exu.exu_i0_br_mp_r <= io.dec_exu.tlu_exu.exu_i0_br_mp_r @[dec.scala 205:18] + tlu.io.tlu_exu.exu_i0_br_valid_r <= io.dec_exu.tlu_exu.exu_i0_br_valid_r @[dec.scala 205:18] + tlu.io.tlu_exu.exu_i0_br_index_r <= io.dec_exu.tlu_exu.exu_i0_br_index_r @[dec.scala 205:18] + tlu.io.tlu_exu.exu_i0_br_start_error_r <= io.dec_exu.tlu_exu.exu_i0_br_start_error_r @[dec.scala 205:18] + tlu.io.tlu_exu.exu_i0_br_error_r <= io.dec_exu.tlu_exu.exu_i0_br_error_r @[dec.scala 205:18] + tlu.io.tlu_exu.exu_i0_br_hist_r <= io.dec_exu.tlu_exu.exu_i0_br_hist_r @[dec.scala 205:18] + io.dec_exu.tlu_exu.dec_tlu_flush_path_r <= tlu.io.tlu_exu.dec_tlu_flush_path_r @[dec.scala 205:18] + io.dec_exu.tlu_exu.dec_tlu_flush_lower_r <= tlu.io.tlu_exu.dec_tlu_flush_lower_r @[dec.scala 205:18] + io.dec_exu.tlu_exu.dec_tlu_meihap <= tlu.io.tlu_exu.dec_tlu_meihap @[dec.scala 205:18] + tlu.io.tlu_dma.dma_iccm_stall_any <= io.dec_dma.tlu_dma.dma_iccm_stall_any @[dec.scala 206:18] + tlu.io.tlu_dma.dma_dccm_stall_any <= io.dec_dma.tlu_dma.dma_dccm_stall_any @[dec.scala 206:18] + io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty <= tlu.io.tlu_dma.dec_tlu_dma_qos_prty @[dec.scala 206:18] + tlu.io.tlu_dma.dma_pmu_any_write <= io.dec_dma.tlu_dma.dma_pmu_any_write @[dec.scala 206:18] + tlu.io.tlu_dma.dma_pmu_any_read <= io.dec_dma.tlu_dma.dma_pmu_any_read @[dec.scala 206:18] + tlu.io.tlu_dma.dma_pmu_dccm_write <= io.dec_dma.tlu_dma.dma_pmu_dccm_write @[dec.scala 206:18] + tlu.io.tlu_dma.dma_pmu_dccm_read <= io.dec_dma.tlu_dma.dma_pmu_dccm_read @[dec.scala 206:18] + tlu.io.active_clk <= io.active_clk @[dec.scala 207:45] + tlu.io.free_clk <= io.free_clk @[dec.scala 208:45] + tlu.io.scan_mode <= io.scan_mode @[dec.scala 209:45] + tlu.io.rst_vec <= io.rst_vec @[dec.scala 210:45] + tlu.io.nmi_int <= io.nmi_int @[dec.scala 211:45] + tlu.io.nmi_vec <= io.nmi_vec @[dec.scala 212:45] + tlu.io.i_cpu_halt_req <= io.i_cpu_halt_req @[dec.scala 213:45] + tlu.io.i_cpu_run_req <= io.i_cpu_run_req @[dec.scala 214:45] + tlu.io.lsu_fastint_stall_any <= io.lsu_fastint_stall_any @[dec.scala 215:45] + tlu.io.ifu_pmu_instr_aligned <= io.ifu_dec.dec_aln.ifu_pmu_instr_aligned @[dec.scala 216:45] + tlu.io.dec_pmu_instr_decoded <= decode.io.dec_pmu_instr_decoded @[dec.scala 217:45] + tlu.io.dec_pmu_decode_stall <= decode.io.dec_pmu_decode_stall @[dec.scala 218:45] + tlu.io.dec_pmu_presync_stall <= decode.io.dec_pmu_presync_stall @[dec.scala 219:45] + tlu.io.dec_pmu_postsync_stall <= decode.io.dec_pmu_postsync_stall @[dec.scala 220:45] + tlu.io.lsu_store_stall_any <= io.lsu_store_stall_any @[dec.scala 221:45] + tlu.io.tlu_busbuff.lsu_imprecise_error_addr_any <= io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any @[dec.scala 222:26] + tlu.io.tlu_busbuff.lsu_imprecise_error_store_any <= io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any @[dec.scala 222:26] + tlu.io.tlu_busbuff.lsu_imprecise_error_load_any <= io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any @[dec.scala 222:26] + io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= tlu.io.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[dec.scala 222:26] + io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable <= tlu.io.tlu_busbuff.dec_tlu_wb_coalescing_disable @[dec.scala 222:26] + io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable <= tlu.io.tlu_busbuff.dec_tlu_external_ldfwd_disable @[dec.scala 222:26] + tlu.io.tlu_busbuff.lsu_pmu_bus_busy <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy @[dec.scala 222:26] + tlu.io.tlu_busbuff.lsu_pmu_bus_error <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error @[dec.scala 222:26] + tlu.io.tlu_busbuff.lsu_pmu_bus_misaligned <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned @[dec.scala 222:26] + tlu.io.tlu_busbuff.lsu_pmu_bus_trxn <= io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn @[dec.scala 222:26] + tlu.io.lsu_tlu.lsu_pmu_store_external_m <= io.lsu_tlu.lsu_pmu_store_external_m @[dec.scala 223:14] + tlu.io.lsu_tlu.lsu_pmu_load_external_m <= io.lsu_tlu.lsu_pmu_load_external_m @[dec.scala 223:14] + tlu.io.dec_pic.mexintpend <= io.dec_pic.mexintpend @[dec.scala 224:14] + io.dec_pic.dec_tlu_meipt <= tlu.io.dec_pic.dec_tlu_meipt @[dec.scala 224:14] + io.dec_pic.dec_tlu_meicurpl <= tlu.io.dec_pic.dec_tlu_meicurpl @[dec.scala 224:14] + tlu.io.dec_pic.mhwakeup <= io.dec_pic.mhwakeup @[dec.scala 224:14] + tlu.io.dec_pic.pic_pl <= io.dec_pic.pic_pl @[dec.scala 224:14] + tlu.io.dec_pic.pic_claimid <= io.dec_pic.pic_claimid @[dec.scala 224:14] + tlu.io.lsu_fir_addr <= io.lsu_fir_addr @[dec.scala 225:45] + tlu.io.lsu_fir_error <= io.lsu_fir_error @[dec.scala 226:45] + tlu.io.iccm_dma_sb_error <= io.iccm_dma_sb_error @[dec.scala 227:45] + tlu.io.lsu_error_pkt_r.bits.addr <= io.lsu_error_pkt_r.bits.addr @[dec.scala 228:45] + tlu.io.lsu_error_pkt_r.bits.mscause <= io.lsu_error_pkt_r.bits.mscause @[dec.scala 228:45] + tlu.io.lsu_error_pkt_r.bits.exc_type <= io.lsu_error_pkt_r.bits.exc_type @[dec.scala 228:45] + tlu.io.lsu_error_pkt_r.bits.inst_type <= io.lsu_error_pkt_r.bits.inst_type @[dec.scala 228:45] + tlu.io.lsu_error_pkt_r.bits.single_ecc_error <= io.lsu_error_pkt_r.bits.single_ecc_error @[dec.scala 228:45] + tlu.io.lsu_error_pkt_r.valid <= io.lsu_error_pkt_r.valid @[dec.scala 228:45] + tlu.io.lsu_single_ecc_error_incr <= io.lsu_single_ecc_error_incr @[dec.scala 229:45] + tlu.io.dec_pause_state <= decode.io.dec_pause_state @[dec.scala 230:45] + tlu.io.dec_csr_wen_unq_d <= decode.io.dec_csr_wen_unq_d @[dec.scala 231:45] + tlu.io.dec_csr_any_unq_d <= decode.io.dec_csr_any_unq_d @[dec.scala 232:45] + tlu.io.dec_csr_rdaddr_d <= decode.io.dec_csr_rdaddr_d @[dec.scala 233:45] + tlu.io.dec_csr_wen_r <= decode.io.dec_csr_wen_r @[dec.scala 234:45] + tlu.io.dec_csr_wraddr_r <= decode.io.dec_csr_wraddr_r @[dec.scala 235:45] + tlu.io.dec_csr_wrdata_r <= decode.io.dec_csr_wrdata_r @[dec.scala 236:45] + tlu.io.dec_csr_stall_int_ff <= decode.io.dec_csr_stall_int_ff @[dec.scala 237:45] + tlu.io.dec_tlu_i0_valid_r <= decode.io.dec_tlu_i0_valid_r @[dec.scala 238:45] + tlu.io.dec_tlu_i0_pc_r <= decode.io.dec_tlu_i0_pc_r @[dec.scala 239:45] + tlu.io.dec_tlu_packet_r.pmu_lsu_misaligned <= decode.io.dec_tlu_packet_r.pmu_lsu_misaligned @[dec.scala 240:45] + tlu.io.dec_tlu_packet_r.pmu_divide <= decode.io.dec_tlu_packet_r.pmu_divide @[dec.scala 240:45] + tlu.io.dec_tlu_packet_r.pmu_i0_br_unpred <= decode.io.dec_tlu_packet_r.pmu_i0_br_unpred @[dec.scala 240:45] + tlu.io.dec_tlu_packet_r.pmu_i0_itype <= decode.io.dec_tlu_packet_r.pmu_i0_itype @[dec.scala 240:45] + tlu.io.dec_tlu_packet_r.i0trigger <= decode.io.dec_tlu_packet_r.i0trigger @[dec.scala 240:45] + tlu.io.dec_tlu_packet_r.fence_i <= decode.io.dec_tlu_packet_r.fence_i @[dec.scala 240:45] + tlu.io.dec_tlu_packet_r.icaf_type <= decode.io.dec_tlu_packet_r.icaf_type @[dec.scala 240:45] + tlu.io.dec_tlu_packet_r.icaf_f1 <= decode.io.dec_tlu_packet_r.icaf_f1 @[dec.scala 240:45] + tlu.io.dec_tlu_packet_r.icaf <= decode.io.dec_tlu_packet_r.icaf @[dec.scala 240:45] + tlu.io.dec_tlu_packet_r.legal <= decode.io.dec_tlu_packet_r.legal @[dec.scala 240:45] + tlu.io.dec_illegal_inst <= decode.io.dec_illegal_inst @[dec.scala 241:45] + tlu.io.dec_i0_decode_d <= decode.io.dec_aln.dec_i0_decode_d @[dec.scala 242:45] + tlu.io.exu_i0_br_way_r <= io.exu_i0_br_way_r @[dec.scala 243:45] + tlu.io.dbg_halt_req <= io.dbg_halt_req @[dec.scala 244:45] + tlu.io.dbg_resume_req <= io.dbg_resume_req @[dec.scala 245:45] + tlu.io.lsu_idle_any <= io.lsu_idle_any @[dec.scala 246:45] + tlu.io.dec_div_active <= decode.io.dec_div_active @[dec.scala 247:45] + tlu.io.timer_int <= io.timer_int @[dec.scala 252:45] + tlu.io.soft_int <= io.soft_int @[dec.scala 253:45] + tlu.io.core_id <= io.core_id @[dec.scala 254:45] + tlu.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[dec.scala 255:45] + tlu.io.mpc_debug_run_req <= io.mpc_debug_run_req @[dec.scala 256:45] + tlu.io.mpc_reset_run_req <= io.mpc_reset_run_req @[dec.scala 257:45] + io.dec_dbg_cmd_done <= tlu.io.dec_dbg_cmd_done @[dec.scala 258:28] + io.dec_dbg_cmd_fail <= tlu.io.dec_dbg_cmd_fail @[dec.scala 259:28] + io.dec_tlu_dbg_halted <= tlu.io.dec_tlu_dbg_halted @[dec.scala 260:28] + io.dec_tlu_debug_mode <= tlu.io.dec_tlu_debug_mode @[dec.scala 261:28] + io.dec_tlu_resume_ack <= tlu.io.dec_tlu_resume_ack @[dec.scala 262:28] + io.dec_tlu_mpc_halted_only <= tlu.io.dec_tlu_mpc_halted_only @[dec.scala 263:51] + io.trigger_pkt_any[0].tdata2 <= tlu.io.trigger_pkt_any[0].tdata2 @[dec.scala 264:29] + io.trigger_pkt_any[0].m <= tlu.io.trigger_pkt_any[0].m @[dec.scala 264:29] + io.trigger_pkt_any[0].execute <= tlu.io.trigger_pkt_any[0].execute @[dec.scala 264:29] + io.trigger_pkt_any[0].load <= tlu.io.trigger_pkt_any[0].load @[dec.scala 264:29] + io.trigger_pkt_any[0].store <= tlu.io.trigger_pkt_any[0].store @[dec.scala 264:29] + io.trigger_pkt_any[0].match_pkt <= tlu.io.trigger_pkt_any[0].match_pkt @[dec.scala 264:29] + io.trigger_pkt_any[0].select <= tlu.io.trigger_pkt_any[0].select @[dec.scala 264:29] + io.trigger_pkt_any[1].tdata2 <= tlu.io.trigger_pkt_any[1].tdata2 @[dec.scala 264:29] + io.trigger_pkt_any[1].m <= tlu.io.trigger_pkt_any[1].m @[dec.scala 264:29] + io.trigger_pkt_any[1].execute <= tlu.io.trigger_pkt_any[1].execute @[dec.scala 264:29] + io.trigger_pkt_any[1].load <= tlu.io.trigger_pkt_any[1].load @[dec.scala 264:29] + io.trigger_pkt_any[1].store <= tlu.io.trigger_pkt_any[1].store @[dec.scala 264:29] + io.trigger_pkt_any[1].match_pkt <= tlu.io.trigger_pkt_any[1].match_pkt @[dec.scala 264:29] + io.trigger_pkt_any[1].select <= tlu.io.trigger_pkt_any[1].select @[dec.scala 264:29] + io.trigger_pkt_any[2].tdata2 <= tlu.io.trigger_pkt_any[2].tdata2 @[dec.scala 264:29] + io.trigger_pkt_any[2].m <= tlu.io.trigger_pkt_any[2].m @[dec.scala 264:29] + io.trigger_pkt_any[2].execute <= tlu.io.trigger_pkt_any[2].execute @[dec.scala 264:29] + io.trigger_pkt_any[2].load <= tlu.io.trigger_pkt_any[2].load @[dec.scala 264:29] + io.trigger_pkt_any[2].store <= tlu.io.trigger_pkt_any[2].store @[dec.scala 264:29] + io.trigger_pkt_any[2].match_pkt <= tlu.io.trigger_pkt_any[2].match_pkt @[dec.scala 264:29] + io.trigger_pkt_any[2].select <= tlu.io.trigger_pkt_any[2].select @[dec.scala 264:29] + io.trigger_pkt_any[3].tdata2 <= tlu.io.trigger_pkt_any[3].tdata2 @[dec.scala 264:29] + io.trigger_pkt_any[3].m <= tlu.io.trigger_pkt_any[3].m @[dec.scala 264:29] + io.trigger_pkt_any[3].execute <= tlu.io.trigger_pkt_any[3].execute @[dec.scala 264:29] + io.trigger_pkt_any[3].load <= tlu.io.trigger_pkt_any[3].load @[dec.scala 264:29] + io.trigger_pkt_any[3].store <= tlu.io.trigger_pkt_any[3].store @[dec.scala 264:29] + io.trigger_pkt_any[3].match_pkt <= tlu.io.trigger_pkt_any[3].match_pkt @[dec.scala 264:29] + io.trigger_pkt_any[3].select <= tlu.io.trigger_pkt_any[3].select @[dec.scala 264:29] + io.o_cpu_halt_status <= tlu.io.o_cpu_halt_status @[dec.scala 265:29] + io.o_cpu_halt_ack <= tlu.io.o_cpu_halt_ack @[dec.scala 266:29] + io.o_cpu_run_ack <= tlu.io.o_cpu_run_ack @[dec.scala 267:29] + io.o_debug_mode_status <= tlu.io.o_debug_mode_status @[dec.scala 268:29] + io.mpc_debug_halt_ack <= tlu.io.mpc_debug_halt_ack @[dec.scala 269:29] + io.mpc_debug_run_ack <= tlu.io.mpc_debug_run_ack @[dec.scala 270:29] + io.debug_brkpt_status <= tlu.io.debug_brkpt_status @[dec.scala 271:29] + io.dec_tlu_i0_kill_writeb_r <= tlu.io.dec_tlu_i0_kill_writeb_r @[dec.scala 274:34] + io.dec_tlu_perfcnt0 <= tlu.io.dec_tlu_perfcnt0 @[dec.scala 275:29] + io.dec_tlu_perfcnt1 <= tlu.io.dec_tlu_perfcnt1 @[dec.scala 276:29] + io.dec_tlu_perfcnt2 <= tlu.io.dec_tlu_perfcnt2 @[dec.scala 277:29] + io.dec_tlu_perfcnt3 <= tlu.io.dec_tlu_perfcnt3 @[dec.scala 278:29] + dec_tlu_i0_exc_valid_wb1 <= tlu.io.dec_tlu_i0_exc_valid_wb1 @[dec.scala 279:32] + dec_tlu_i0_valid_wb1 <= tlu.io.dec_tlu_i0_valid_wb1 @[dec.scala 280:32] + dec_tlu_int_valid_wb1 <= tlu.io.dec_tlu_int_valid_wb1 @[dec.scala 281:32] + dec_tlu_exc_cause_wb1 <= tlu.io.dec_tlu_exc_cause_wb1 @[dec.scala 282:32] + dec_tlu_mtval_wb1 <= tlu.io.dec_tlu_mtval_wb1 @[dec.scala 283:32] + io.dec_tlu_misc_clk_override <= tlu.io.dec_tlu_misc_clk_override @[dec.scala 284:35] + io.dec_tlu_ifu_clk_override <= tlu.io.dec_tlu_ifu_clk_override @[dec.scala 285:36] + io.dec_tlu_lsu_clk_override <= tlu.io.dec_tlu_lsu_clk_override @[dec.scala 286:36] + io.dec_tlu_bus_clk_override <= tlu.io.dec_tlu_bus_clk_override @[dec.scala 287:36] + io.dec_tlu_pic_clk_override <= tlu.io.dec_tlu_pic_clk_override @[dec.scala 288:36] + io.dec_tlu_dccm_clk_override <= tlu.io.dec_tlu_dccm_clk_override @[dec.scala 289:36] + io.dec_tlu_icm_clk_override <= tlu.io.dec_tlu_icm_clk_override @[dec.scala 290:36] + io.rv_trace_pkt.rv_i_insn_ip <= decode.io.dec_i0_inst_wb1 @[dec.scala 294:32] node _T = cat(decode.io.dec_i0_pc_wb1, UInt<1>("h00")) @[Cat.scala 29:58] - io.rv_trace_pkt.rv_i_address_ip <= _T @[dec.scala 308:35] - node _T_1 = or(tlu.io.dec_tlu_i0_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[dec.scala 309:98] + io.rv_trace_pkt.rv_i_address_ip <= _T @[dec.scala 295:35] + node _T_1 = or(tlu.io.dec_tlu_i0_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[dec.scala 296:98] node _T_2 = cat(tlu.io.dec_tlu_int_valid_wb1, _T_1) @[Cat.scala 29:58] - io.rv_trace_pkt.rv_i_valid_ip <= _T_2 @[dec.scala 309:33] + io.rv_trace_pkt.rv_i_valid_ip <= _T_2 @[dec.scala 296:33] node _T_3 = cat(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1) @[Cat.scala 29:58] - io.rv_trace_pkt.rv_i_exception_ip <= _T_3 @[dec.scala 310:37] - node _T_4 = bits(tlu.io.dec_tlu_exc_cause_wb1, 4, 0) @[dec.scala 311:65] - io.rv_trace_pkt.rv_i_ecause_ip <= _T_4 @[dec.scala 311:34] + io.rv_trace_pkt.rv_i_exception_ip <= _T_3 @[dec.scala 297:37] + node _T_4 = bits(tlu.io.dec_tlu_exc_cause_wb1, 4, 0) @[dec.scala 298:65] + io.rv_trace_pkt.rv_i_ecause_ip <= _T_4 @[dec.scala 298:34] node _T_5 = cat(tlu.io.dec_tlu_int_valid_wb1, UInt<1>("h00")) @[Cat.scala 29:58] - io.rv_trace_pkt.rv_i_interrupt_ip <= _T_5 @[dec.scala 312:37] - io.rv_trace_pkt.rv_i_tval_ip <= tlu.io.dec_tlu_mtval_wb1 @[dec.scala 313:32] - io.dec_dbg_rddata <= decode.io.dec_i0_wdata_r @[dec.scala 317:21] + io.rv_trace_pkt.rv_i_interrupt_ip <= _T_5 @[dec.scala 299:37] + io.rv_trace_pkt.rv_i_tval_ip <= tlu.io.dec_tlu_mtval_wb1 @[dec.scala 300:32] + io.dec_dbg_rddata <= decode.io.dec_i0_wdata_r @[dec.scala 304:21] extmodule gated_latch_755 : output Q : Clock @@ -95835,7 +95832,7 @@ circuit quasar_wrapper : node _T_748 = and(ld_fwddata_buf_hi_initial, ibuf_data) @[lsu_bus_buffer.scala 175:32] node _T_749 = or(_T_747, _T_748) @[lsu_bus_buffer.scala 174:103] io.ld_fwddata_buf_hi <= _T_749 @[lsu_bus_buffer.scala 171:24] - node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 177:77] + node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h01")) @[lsu_bus_buffer.scala 177:77] node _T_750 = mux(io.lsu_pkt_r.bits.by, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_751 = mux(io.lsu_pkt_r.bits.half, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_752 = mux(io.lsu_pkt_r.bits.word, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -96578,37 +96575,37 @@ circuit quasar_wrapper : wire obuf_merge_en : UInt<1> obuf_merge_en <= UInt<1>("h00") node obuf_tag0_in = mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) @[lsu_bus_buffer.scala 298:25] - node obuf_tag1_in = mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1) @[lsu_bus_buffer.scala 301:25] + node obuf_tag1_in = mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1) @[lsu_bus_buffer.scala 300:25] wire obuf_cmd_done : UInt<1> obuf_cmd_done <= UInt<1>("h00") wire bus_wcmd_sent : UInt<1> bus_wcmd_sent <= UInt<1>("h00") - node _T_1304 = or(obuf_wr_en, obuf_rst) @[lsu_bus_buffer.scala 304:39] - node _T_1305 = eq(_T_1304, UInt<1>("h00")) @[lsu_bus_buffer.scala 304:26] - node _T_1306 = or(obuf_cmd_done, bus_wcmd_sent) @[lsu_bus_buffer.scala 304:68] - node obuf_cmd_done_in = and(_T_1305, _T_1306) @[lsu_bus_buffer.scala 304:51] + node _T_1304 = or(obuf_wr_en, obuf_rst) @[lsu_bus_buffer.scala 303:39] + node _T_1305 = eq(_T_1304, UInt<1>("h00")) @[lsu_bus_buffer.scala 303:26] + node _T_1306 = or(obuf_cmd_done, bus_wcmd_sent) @[lsu_bus_buffer.scala 303:68] + node obuf_cmd_done_in = and(_T_1305, _T_1306) @[lsu_bus_buffer.scala 303:51] wire obuf_data_done : UInt<1> obuf_data_done <= UInt<1>("h00") wire bus_wdata_sent : UInt<1> bus_wdata_sent <= UInt<1>("h00") - node _T_1307 = or(obuf_wr_en, obuf_rst) @[lsu_bus_buffer.scala 307:40] - node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[lsu_bus_buffer.scala 307:27] - node _T_1309 = or(obuf_data_done, bus_wdata_sent) @[lsu_bus_buffer.scala 307:70] - node obuf_data_done_in = and(_T_1308, _T_1309) @[lsu_bus_buffer.scala 307:52] - node _T_1310 = bits(obuf_sz_in, 1, 0) @[lsu_bus_buffer.scala 308:67] - node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[lsu_bus_buffer.scala 308:72] - node _T_1312 = bits(obuf_sz_in, 0, 0) @[lsu_bus_buffer.scala 308:92] - node _T_1313 = bits(obuf_addr_in, 0, 0) @[lsu_bus_buffer.scala 308:111] - node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[lsu_bus_buffer.scala 308:98] - node _T_1315 = and(_T_1312, _T_1314) @[lsu_bus_buffer.scala 308:96] - node _T_1316 = or(_T_1311, _T_1315) @[lsu_bus_buffer.scala 308:79] - node _T_1317 = bits(obuf_sz_in, 1, 1) @[lsu_bus_buffer.scala 308:129] - node _T_1318 = bits(obuf_addr_in, 1, 0) @[lsu_bus_buffer.scala 308:147] - node _T_1319 = orr(_T_1318) @[lsu_bus_buffer.scala 308:153] - node _T_1320 = eq(_T_1319, UInt<1>("h00")) @[lsu_bus_buffer.scala 308:134] - node _T_1321 = and(_T_1317, _T_1320) @[lsu_bus_buffer.scala 308:132] - node _T_1322 = or(_T_1316, _T_1321) @[lsu_bus_buffer.scala 308:116] - node obuf_aligned_in = mux(ibuf_buf_byp, is_aligned_r, _T_1322) @[lsu_bus_buffer.scala 308:28] + node _T_1307 = or(obuf_wr_en, obuf_rst) @[lsu_bus_buffer.scala 306:40] + node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[lsu_bus_buffer.scala 306:27] + node _T_1309 = or(obuf_data_done, bus_wdata_sent) @[lsu_bus_buffer.scala 306:70] + node obuf_data_done_in = and(_T_1308, _T_1309) @[lsu_bus_buffer.scala 306:52] + node _T_1310 = bits(obuf_sz_in, 1, 0) @[lsu_bus_buffer.scala 307:67] + node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[lsu_bus_buffer.scala 307:72] + node _T_1312 = bits(obuf_sz_in, 0, 0) @[lsu_bus_buffer.scala 307:92] + node _T_1313 = bits(obuf_addr_in, 0, 0) @[lsu_bus_buffer.scala 307:111] + node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[lsu_bus_buffer.scala 307:98] + node _T_1315 = and(_T_1312, _T_1314) @[lsu_bus_buffer.scala 307:96] + node _T_1316 = or(_T_1311, _T_1315) @[lsu_bus_buffer.scala 307:79] + node _T_1317 = bits(obuf_sz_in, 1, 1) @[lsu_bus_buffer.scala 307:129] + node _T_1318 = bits(obuf_addr_in, 1, 0) @[lsu_bus_buffer.scala 307:147] + node _T_1319 = orr(_T_1318) @[lsu_bus_buffer.scala 307:153] + node _T_1320 = eq(_T_1319, UInt<1>("h00")) @[lsu_bus_buffer.scala 307:134] + node _T_1321 = and(_T_1317, _T_1320) @[lsu_bus_buffer.scala 307:132] + node _T_1322 = or(_T_1316, _T_1321) @[lsu_bus_buffer.scala 307:116] + node obuf_aligned_in = mux(ibuf_buf_byp, is_aligned_r, _T_1322) @[lsu_bus_buffer.scala 307:28] wire obuf_nosend_in : UInt<1> obuf_nosend_in <= UInt<1>("h00") wire obuf_rdrsp_pend : UInt<1> @@ -96621,53 +96618,53 @@ circuit quasar_wrapper : obuf_rdrsp_tag <= UInt<1>("h00") wire obuf_write : UInt<1> obuf_write <= UInt<1>("h00") - node _T_1323 = eq(obuf_nosend_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 316:44] - node _T_1324 = and(obuf_wr_en, _T_1323) @[lsu_bus_buffer.scala 316:42] - node _T_1325 = eq(_T_1324, UInt<1>("h00")) @[lsu_bus_buffer.scala 316:29] - node _T_1326 = and(_T_1325, obuf_rdrsp_pend) @[lsu_bus_buffer.scala 316:61] - node _T_1327 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 316:116] - node _T_1328 = and(bus_rsp_read, _T_1327) @[lsu_bus_buffer.scala 316:96] - node _T_1329 = eq(_T_1328, UInt<1>("h00")) @[lsu_bus_buffer.scala 316:81] - node _T_1330 = and(_T_1326, _T_1329) @[lsu_bus_buffer.scala 316:79] - node _T_1331 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 317:22] - node _T_1332 = and(bus_cmd_sent, _T_1331) @[lsu_bus_buffer.scala 317:20] - node _T_1333 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 317:37] - node _T_1334 = and(_T_1332, _T_1333) @[lsu_bus_buffer.scala 317:35] - node obuf_rdrsp_pend_in = or(_T_1330, _T_1334) @[lsu_bus_buffer.scala 316:138] + node _T_1323 = eq(obuf_nosend_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 315:44] + node _T_1324 = and(obuf_wr_en, _T_1323) @[lsu_bus_buffer.scala 315:42] + node _T_1325 = eq(_T_1324, UInt<1>("h00")) @[lsu_bus_buffer.scala 315:29] + node _T_1326 = and(_T_1325, obuf_rdrsp_pend) @[lsu_bus_buffer.scala 315:61] + node _T_1327 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 315:116] + node _T_1328 = and(bus_rsp_read, _T_1327) @[lsu_bus_buffer.scala 315:96] + node _T_1329 = eq(_T_1328, UInt<1>("h00")) @[lsu_bus_buffer.scala 315:81] + node _T_1330 = and(_T_1326, _T_1329) @[lsu_bus_buffer.scala 315:79] + node _T_1331 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 316:22] + node _T_1332 = and(bus_cmd_sent, _T_1331) @[lsu_bus_buffer.scala 316:20] + node _T_1333 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 316:37] + node _T_1334 = and(_T_1332, _T_1333) @[lsu_bus_buffer.scala 316:35] + node obuf_rdrsp_pend_in = or(_T_1330, _T_1334) @[lsu_bus_buffer.scala 315:138] wire obuf_tag0 : UInt<3> obuf_tag0 <= UInt<1>("h00") - node _T_1335 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 319:46] - node _T_1336 = and(bus_cmd_sent, _T_1335) @[lsu_bus_buffer.scala 319:44] - node obuf_rdrsp_tag_in = mux(_T_1336, obuf_tag0, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 319:30] + node _T_1335 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 318:46] + node _T_1336 = and(bus_cmd_sent, _T_1335) @[lsu_bus_buffer.scala 318:44] + node obuf_rdrsp_tag_in = mux(_T_1336, obuf_tag0, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 318:30] wire obuf_addr : UInt<32> obuf_addr <= UInt<1>("h00") wire obuf_sideeffect : UInt<1> obuf_sideeffect <= UInt<1>("h00") - node _T_1337 = bits(obuf_addr_in, 31, 3) @[lsu_bus_buffer.scala 322:34] - node _T_1338 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 322:52] - node _T_1339 = eq(_T_1337, _T_1338) @[lsu_bus_buffer.scala 322:40] - node _T_1340 = and(_T_1339, obuf_aligned_in) @[lsu_bus_buffer.scala 322:60] - node _T_1341 = eq(obuf_sideeffect, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:80] - node _T_1342 = and(_T_1340, _T_1341) @[lsu_bus_buffer.scala 322:78] - node _T_1343 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:99] - node _T_1344 = and(_T_1342, _T_1343) @[lsu_bus_buffer.scala 322:97] - node _T_1345 = eq(obuf_write_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:113] - node _T_1346 = and(_T_1344, _T_1345) @[lsu_bus_buffer.scala 322:111] - node _T_1347 = eq(io.tlu_busbuff.dec_tlu_external_ldfwd_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:130] - node _T_1348 = and(_T_1346, _T_1347) @[lsu_bus_buffer.scala 322:128] - node _T_1349 = eq(obuf_nosend, UInt<1>("h00")) @[lsu_bus_buffer.scala 323:20] - node _T_1350 = and(obuf_valid, _T_1349) @[lsu_bus_buffer.scala 323:18] - node _T_1351 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 323:90] - node _T_1352 = and(bus_rsp_read, _T_1351) @[lsu_bus_buffer.scala 323:70] - node _T_1353 = eq(_T_1352, UInt<1>("h00")) @[lsu_bus_buffer.scala 323:55] - node _T_1354 = and(obuf_rdrsp_pend, _T_1353) @[lsu_bus_buffer.scala 323:53] - node _T_1355 = or(_T_1350, _T_1354) @[lsu_bus_buffer.scala 323:34] - node _T_1356 = and(_T_1348, _T_1355) @[lsu_bus_buffer.scala 322:177] - obuf_nosend_in <= _T_1356 @[lsu_bus_buffer.scala 322:18] - node _T_1357 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 324:60] + node _T_1337 = bits(obuf_addr_in, 31, 3) @[lsu_bus_buffer.scala 321:34] + node _T_1338 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 321:52] + node _T_1339 = eq(_T_1337, _T_1338) @[lsu_bus_buffer.scala 321:40] + node _T_1340 = and(_T_1339, obuf_aligned_in) @[lsu_bus_buffer.scala 321:60] + node _T_1341 = eq(obuf_sideeffect, UInt<1>("h00")) @[lsu_bus_buffer.scala 321:80] + node _T_1342 = and(_T_1340, _T_1341) @[lsu_bus_buffer.scala 321:78] + node _T_1343 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 321:99] + node _T_1344 = and(_T_1342, _T_1343) @[lsu_bus_buffer.scala 321:97] + node _T_1345 = eq(obuf_write_in, UInt<1>("h00")) @[lsu_bus_buffer.scala 321:113] + node _T_1346 = and(_T_1344, _T_1345) @[lsu_bus_buffer.scala 321:111] + node _T_1347 = eq(io.tlu_busbuff.dec_tlu_external_ldfwd_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 321:130] + node _T_1348 = and(_T_1346, _T_1347) @[lsu_bus_buffer.scala 321:128] + node _T_1349 = eq(obuf_nosend, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:20] + node _T_1350 = and(obuf_valid, _T_1349) @[lsu_bus_buffer.scala 322:18] + node _T_1351 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 322:90] + node _T_1352 = and(bus_rsp_read, _T_1351) @[lsu_bus_buffer.scala 322:70] + node _T_1353 = eq(_T_1352, UInt<1>("h00")) @[lsu_bus_buffer.scala 322:55] + node _T_1354 = and(obuf_rdrsp_pend, _T_1353) @[lsu_bus_buffer.scala 322:53] + node _T_1355 = or(_T_1350, _T_1354) @[lsu_bus_buffer.scala 322:34] + node _T_1356 = and(_T_1348, _T_1355) @[lsu_bus_buffer.scala 321:177] + obuf_nosend_in <= _T_1356 @[lsu_bus_buffer.scala 321:18] + node _T_1357 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 323:60] node _T_1358 = cat(ldst_byteen_lo_r, UInt<4>("h00")) @[Cat.scala 29:58] node _T_1359 = cat(UInt<4>("h00"), ldst_byteen_lo_r) @[Cat.scala 29:58] - node _T_1360 = mux(_T_1357, _T_1358, _T_1359) @[lsu_bus_buffer.scala 324:46] + node _T_1360 = mux(_T_1357, _T_1358, _T_1359) @[lsu_bus_buffer.scala 323:46] node _T_1361 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] node _T_1362 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] node _T_1363 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] @@ -96681,8 +96678,8 @@ circuit quasar_wrapper : node _T_1371 = or(_T_1370, _T_1368) @[Mux.scala 27:72] wire _T_1372 : UInt<32> @[Mux.scala 27:72] _T_1372 <= _T_1371 @[Mux.scala 27:72] - node _T_1373 = bits(_T_1372, 2, 2) @[lsu_bus_buffer.scala 325:36] - node _T_1374 = bits(_T_1373, 0, 0) @[lsu_bus_buffer.scala 325:46] + node _T_1373 = bits(_T_1372, 2, 2) @[lsu_bus_buffer.scala 324:36] + node _T_1374 = bits(_T_1373, 0, 0) @[lsu_bus_buffer.scala 324:46] node _T_1375 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] node _T_1376 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] node _T_1377 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] @@ -96711,12 +96708,12 @@ circuit quasar_wrapper : wire _T_1399 : UInt<4> @[Mux.scala 27:72] _T_1399 <= _T_1398 @[Mux.scala 27:72] node _T_1400 = cat(UInt<4>("h00"), _T_1399) @[Cat.scala 29:58] - node _T_1401 = mux(_T_1374, _T_1387, _T_1400) @[lsu_bus_buffer.scala 325:8] - node obuf_byteen0_in = mux(ibuf_buf_byp, _T_1360, _T_1401) @[lsu_bus_buffer.scala 324:28] - node _T_1402 = bits(io.end_addr_r, 2, 2) @[lsu_bus_buffer.scala 326:60] + node _T_1401 = mux(_T_1374, _T_1387, _T_1400) @[lsu_bus_buffer.scala 324:8] + node obuf_byteen0_in = mux(ibuf_buf_byp, _T_1360, _T_1401) @[lsu_bus_buffer.scala 323:28] + node _T_1402 = bits(io.end_addr_r, 2, 2) @[lsu_bus_buffer.scala 325:60] node _T_1403 = cat(ldst_byteen_hi_r, UInt<4>("h00")) @[Cat.scala 29:58] node _T_1404 = cat(UInt<4>("h00"), ldst_byteen_hi_r) @[Cat.scala 29:58] - node _T_1405 = mux(_T_1402, _T_1403, _T_1404) @[lsu_bus_buffer.scala 326:46] + node _T_1405 = mux(_T_1402, _T_1403, _T_1404) @[lsu_bus_buffer.scala 325:46] node _T_1406 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] node _T_1407 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] node _T_1408 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] @@ -96730,8 +96727,8 @@ circuit quasar_wrapper : node _T_1416 = or(_T_1415, _T_1413) @[Mux.scala 27:72] wire _T_1417 : UInt<32> @[Mux.scala 27:72] _T_1417 <= _T_1416 @[Mux.scala 27:72] - node _T_1418 = bits(_T_1417, 2, 2) @[lsu_bus_buffer.scala 327:36] - node _T_1419 = bits(_T_1418, 0, 0) @[lsu_bus_buffer.scala 327:46] + node _T_1418 = bits(_T_1417, 2, 2) @[lsu_bus_buffer.scala 326:36] + node _T_1419 = bits(_T_1418, 0, 0) @[lsu_bus_buffer.scala 326:46] node _T_1420 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] node _T_1421 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] node _T_1422 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] @@ -96760,12 +96757,12 @@ circuit quasar_wrapper : wire _T_1444 : UInt<4> @[Mux.scala 27:72] _T_1444 <= _T_1443 @[Mux.scala 27:72] node _T_1445 = cat(UInt<4>("h00"), _T_1444) @[Cat.scala 29:58] - node _T_1446 = mux(_T_1419, _T_1432, _T_1445) @[lsu_bus_buffer.scala 327:8] - node obuf_byteen1_in = mux(ibuf_buf_byp, _T_1405, _T_1446) @[lsu_bus_buffer.scala 326:28] - node _T_1447 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 329:58] + node _T_1446 = mux(_T_1419, _T_1432, _T_1445) @[lsu_bus_buffer.scala 326:8] + node obuf_byteen1_in = mux(ibuf_buf_byp, _T_1405, _T_1446) @[lsu_bus_buffer.scala 325:28] + node _T_1447 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 328:58] node _T_1448 = cat(store_data_lo_r, UInt<32>("h00")) @[Cat.scala 29:58] node _T_1449 = cat(UInt<32>("h00"), store_data_lo_r) @[Cat.scala 29:58] - node _T_1450 = mux(_T_1447, _T_1448, _T_1449) @[lsu_bus_buffer.scala 329:44] + node _T_1450 = mux(_T_1447, _T_1448, _T_1449) @[lsu_bus_buffer.scala 328:44] node _T_1451 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] node _T_1452 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] node _T_1453 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] @@ -96779,8 +96776,8 @@ circuit quasar_wrapper : node _T_1461 = or(_T_1460, _T_1458) @[Mux.scala 27:72] wire _T_1462 : UInt<32> @[Mux.scala 27:72] _T_1462 <= _T_1461 @[Mux.scala 27:72] - node _T_1463 = bits(_T_1462, 2, 2) @[lsu_bus_buffer.scala 330:36] - node _T_1464 = bits(_T_1463, 0, 0) @[lsu_bus_buffer.scala 330:46] + node _T_1463 = bits(_T_1462, 2, 2) @[lsu_bus_buffer.scala 329:36] + node _T_1464 = bits(_T_1463, 0, 0) @[lsu_bus_buffer.scala 329:46] node _T_1465 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] node _T_1466 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] node _T_1467 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] @@ -96809,12 +96806,12 @@ circuit quasar_wrapper : wire _T_1489 : UInt<32> @[Mux.scala 27:72] _T_1489 <= _T_1488 @[Mux.scala 27:72] node _T_1490 = cat(UInt<32>("h00"), _T_1489) @[Cat.scala 29:58] - node _T_1491 = mux(_T_1464, _T_1477, _T_1490) @[lsu_bus_buffer.scala 330:8] - node obuf_data0_in = mux(ibuf_buf_byp, _T_1450, _T_1491) @[lsu_bus_buffer.scala 329:26] - node _T_1492 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 331:58] + node _T_1491 = mux(_T_1464, _T_1477, _T_1490) @[lsu_bus_buffer.scala 329:8] + node obuf_data0_in = mux(ibuf_buf_byp, _T_1450, _T_1491) @[lsu_bus_buffer.scala 328:26] + node _T_1492 = bits(io.lsu_addr_r, 2, 2) @[lsu_bus_buffer.scala 330:58] node _T_1493 = cat(store_data_hi_r, UInt<32>("h00")) @[Cat.scala 29:58] node _T_1494 = cat(UInt<32>("h00"), store_data_hi_r) @[Cat.scala 29:58] - node _T_1495 = mux(_T_1492, _T_1493, _T_1494) @[lsu_bus_buffer.scala 331:44] + node _T_1495 = mux(_T_1492, _T_1493, _T_1494) @[lsu_bus_buffer.scala 330:44] node _T_1496 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] node _T_1497 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] node _T_1498 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] @@ -96828,8 +96825,8 @@ circuit quasar_wrapper : node _T_1506 = or(_T_1505, _T_1503) @[Mux.scala 27:72] wire _T_1507 : UInt<32> @[Mux.scala 27:72] _T_1507 <= _T_1506 @[Mux.scala 27:72] - node _T_1508 = bits(_T_1507, 2, 2) @[lsu_bus_buffer.scala 332:36] - node _T_1509 = bits(_T_1508, 0, 0) @[lsu_bus_buffer.scala 332:46] + node _T_1508 = bits(_T_1507, 2, 2) @[lsu_bus_buffer.scala 331:36] + node _T_1509 = bits(_T_1508, 0, 0) @[lsu_bus_buffer.scala 331:46] node _T_1510 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] node _T_1511 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] node _T_1512 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] @@ -96858,40 +96855,40 @@ circuit quasar_wrapper : wire _T_1534 : UInt<32> @[Mux.scala 27:72] _T_1534 <= _T_1533 @[Mux.scala 27:72] node _T_1535 = cat(UInt<32>("h00"), _T_1534) @[Cat.scala 29:58] - node _T_1536 = mux(_T_1509, _T_1522, _T_1535) @[lsu_bus_buffer.scala 332:8] - node obuf_data1_in = mux(ibuf_buf_byp, _T_1495, _T_1536) @[lsu_bus_buffer.scala 331:26] - node _T_1537 = bits(obuf_byteen0_in, 0, 0) @[lsu_bus_buffer.scala 333:59] - node _T_1538 = bits(obuf_byteen1_in, 0, 0) @[lsu_bus_buffer.scala 333:97] - node _T_1539 = and(obuf_merge_en, _T_1538) @[lsu_bus_buffer.scala 333:80] - node _T_1540 = or(_T_1537, _T_1539) @[lsu_bus_buffer.scala 333:63] - node _T_1541 = bits(obuf_byteen0_in, 1, 1) @[lsu_bus_buffer.scala 333:59] - node _T_1542 = bits(obuf_byteen1_in, 1, 1) @[lsu_bus_buffer.scala 333:97] - node _T_1543 = and(obuf_merge_en, _T_1542) @[lsu_bus_buffer.scala 333:80] - node _T_1544 = or(_T_1541, _T_1543) @[lsu_bus_buffer.scala 333:63] - node _T_1545 = bits(obuf_byteen0_in, 2, 2) @[lsu_bus_buffer.scala 333:59] - node _T_1546 = bits(obuf_byteen1_in, 2, 2) @[lsu_bus_buffer.scala 333:97] - node _T_1547 = and(obuf_merge_en, _T_1546) @[lsu_bus_buffer.scala 333:80] - node _T_1548 = or(_T_1545, _T_1547) @[lsu_bus_buffer.scala 333:63] - node _T_1549 = bits(obuf_byteen0_in, 3, 3) @[lsu_bus_buffer.scala 333:59] - node _T_1550 = bits(obuf_byteen1_in, 3, 3) @[lsu_bus_buffer.scala 333:97] - node _T_1551 = and(obuf_merge_en, _T_1550) @[lsu_bus_buffer.scala 333:80] - node _T_1552 = or(_T_1549, _T_1551) @[lsu_bus_buffer.scala 333:63] - node _T_1553 = bits(obuf_byteen0_in, 4, 4) @[lsu_bus_buffer.scala 333:59] - node _T_1554 = bits(obuf_byteen1_in, 4, 4) @[lsu_bus_buffer.scala 333:97] - node _T_1555 = and(obuf_merge_en, _T_1554) @[lsu_bus_buffer.scala 333:80] - node _T_1556 = or(_T_1553, _T_1555) @[lsu_bus_buffer.scala 333:63] - node _T_1557 = bits(obuf_byteen0_in, 5, 5) @[lsu_bus_buffer.scala 333:59] - node _T_1558 = bits(obuf_byteen1_in, 5, 5) @[lsu_bus_buffer.scala 333:97] - node _T_1559 = and(obuf_merge_en, _T_1558) @[lsu_bus_buffer.scala 333:80] - node _T_1560 = or(_T_1557, _T_1559) @[lsu_bus_buffer.scala 333:63] - node _T_1561 = bits(obuf_byteen0_in, 6, 6) @[lsu_bus_buffer.scala 333:59] - node _T_1562 = bits(obuf_byteen1_in, 6, 6) @[lsu_bus_buffer.scala 333:97] - node _T_1563 = and(obuf_merge_en, _T_1562) @[lsu_bus_buffer.scala 333:80] - node _T_1564 = or(_T_1561, _T_1563) @[lsu_bus_buffer.scala 333:63] - node _T_1565 = bits(obuf_byteen0_in, 7, 7) @[lsu_bus_buffer.scala 333:59] - node _T_1566 = bits(obuf_byteen1_in, 7, 7) @[lsu_bus_buffer.scala 333:97] - node _T_1567 = and(obuf_merge_en, _T_1566) @[lsu_bus_buffer.scala 333:80] - node _T_1568 = or(_T_1565, _T_1567) @[lsu_bus_buffer.scala 333:63] + node _T_1536 = mux(_T_1509, _T_1522, _T_1535) @[lsu_bus_buffer.scala 331:8] + node obuf_data1_in = mux(ibuf_buf_byp, _T_1495, _T_1536) @[lsu_bus_buffer.scala 330:26] + node _T_1537 = bits(obuf_byteen0_in, 0, 0) @[lsu_bus_buffer.scala 332:59] + node _T_1538 = bits(obuf_byteen1_in, 0, 0) @[lsu_bus_buffer.scala 332:97] + node _T_1539 = and(obuf_merge_en, _T_1538) @[lsu_bus_buffer.scala 332:80] + node _T_1540 = or(_T_1537, _T_1539) @[lsu_bus_buffer.scala 332:63] + node _T_1541 = bits(obuf_byteen0_in, 1, 1) @[lsu_bus_buffer.scala 332:59] + node _T_1542 = bits(obuf_byteen1_in, 1, 1) @[lsu_bus_buffer.scala 332:97] + node _T_1543 = and(obuf_merge_en, _T_1542) @[lsu_bus_buffer.scala 332:80] + node _T_1544 = or(_T_1541, _T_1543) @[lsu_bus_buffer.scala 332:63] + node _T_1545 = bits(obuf_byteen0_in, 2, 2) @[lsu_bus_buffer.scala 332:59] + node _T_1546 = bits(obuf_byteen1_in, 2, 2) @[lsu_bus_buffer.scala 332:97] + node _T_1547 = and(obuf_merge_en, _T_1546) @[lsu_bus_buffer.scala 332:80] + node _T_1548 = or(_T_1545, _T_1547) @[lsu_bus_buffer.scala 332:63] + node _T_1549 = bits(obuf_byteen0_in, 3, 3) @[lsu_bus_buffer.scala 332:59] + node _T_1550 = bits(obuf_byteen1_in, 3, 3) @[lsu_bus_buffer.scala 332:97] + node _T_1551 = and(obuf_merge_en, _T_1550) @[lsu_bus_buffer.scala 332:80] + node _T_1552 = or(_T_1549, _T_1551) @[lsu_bus_buffer.scala 332:63] + node _T_1553 = bits(obuf_byteen0_in, 4, 4) @[lsu_bus_buffer.scala 332:59] + node _T_1554 = bits(obuf_byteen1_in, 4, 4) @[lsu_bus_buffer.scala 332:97] + node _T_1555 = and(obuf_merge_en, _T_1554) @[lsu_bus_buffer.scala 332:80] + node _T_1556 = or(_T_1553, _T_1555) @[lsu_bus_buffer.scala 332:63] + node _T_1557 = bits(obuf_byteen0_in, 5, 5) @[lsu_bus_buffer.scala 332:59] + node _T_1558 = bits(obuf_byteen1_in, 5, 5) @[lsu_bus_buffer.scala 332:97] + node _T_1559 = and(obuf_merge_en, _T_1558) @[lsu_bus_buffer.scala 332:80] + node _T_1560 = or(_T_1557, _T_1559) @[lsu_bus_buffer.scala 332:63] + node _T_1561 = bits(obuf_byteen0_in, 6, 6) @[lsu_bus_buffer.scala 332:59] + node _T_1562 = bits(obuf_byteen1_in, 6, 6) @[lsu_bus_buffer.scala 332:97] + node _T_1563 = and(obuf_merge_en, _T_1562) @[lsu_bus_buffer.scala 332:80] + node _T_1564 = or(_T_1561, _T_1563) @[lsu_bus_buffer.scala 332:63] + node _T_1565 = bits(obuf_byteen0_in, 7, 7) @[lsu_bus_buffer.scala 332:59] + node _T_1566 = bits(obuf_byteen1_in, 7, 7) @[lsu_bus_buffer.scala 332:97] + node _T_1567 = and(obuf_merge_en, _T_1566) @[lsu_bus_buffer.scala 332:80] + node _T_1568 = or(_T_1565, _T_1567) @[lsu_bus_buffer.scala 332:63] node _T_1569 = cat(_T_1568, _T_1564) @[Cat.scala 29:58] node _T_1570 = cat(_T_1569, _T_1560) @[Cat.scala 29:58] node _T_1571 = cat(_T_1570, _T_1556) @[Cat.scala 29:58] @@ -96899,46 +96896,46 @@ circuit quasar_wrapper : node _T_1573 = cat(_T_1572, _T_1548) @[Cat.scala 29:58] node _T_1574 = cat(_T_1573, _T_1544) @[Cat.scala 29:58] node obuf_byteen_in = cat(_T_1574, _T_1540) @[Cat.scala 29:58] - node _T_1575 = bits(obuf_byteen1_in, 0, 0) @[lsu_bus_buffer.scala 334:76] - node _T_1576 = and(obuf_merge_en, _T_1575) @[lsu_bus_buffer.scala 334:59] - node _T_1577 = bits(obuf_data1_in, 7, 0) @[lsu_bus_buffer.scala 334:94] - node _T_1578 = bits(obuf_data0_in, 7, 0) @[lsu_bus_buffer.scala 334:123] - node _T_1579 = mux(_T_1576, _T_1577, _T_1578) @[lsu_bus_buffer.scala 334:44] - node _T_1580 = bits(obuf_byteen1_in, 1, 1) @[lsu_bus_buffer.scala 334:76] - node _T_1581 = and(obuf_merge_en, _T_1580) @[lsu_bus_buffer.scala 334:59] - node _T_1582 = bits(obuf_data1_in, 15, 8) @[lsu_bus_buffer.scala 334:94] - node _T_1583 = bits(obuf_data0_in, 15, 8) @[lsu_bus_buffer.scala 334:123] - node _T_1584 = mux(_T_1581, _T_1582, _T_1583) @[lsu_bus_buffer.scala 334:44] - node _T_1585 = bits(obuf_byteen1_in, 2, 2) @[lsu_bus_buffer.scala 334:76] - node _T_1586 = and(obuf_merge_en, _T_1585) @[lsu_bus_buffer.scala 334:59] - node _T_1587 = bits(obuf_data1_in, 23, 16) @[lsu_bus_buffer.scala 334:94] - node _T_1588 = bits(obuf_data0_in, 23, 16) @[lsu_bus_buffer.scala 334:123] - node _T_1589 = mux(_T_1586, _T_1587, _T_1588) @[lsu_bus_buffer.scala 334:44] - node _T_1590 = bits(obuf_byteen1_in, 3, 3) @[lsu_bus_buffer.scala 334:76] - node _T_1591 = and(obuf_merge_en, _T_1590) @[lsu_bus_buffer.scala 334:59] - node _T_1592 = bits(obuf_data1_in, 31, 24) @[lsu_bus_buffer.scala 334:94] - node _T_1593 = bits(obuf_data0_in, 31, 24) @[lsu_bus_buffer.scala 334:123] - node _T_1594 = mux(_T_1591, _T_1592, _T_1593) @[lsu_bus_buffer.scala 334:44] - node _T_1595 = bits(obuf_byteen1_in, 4, 4) @[lsu_bus_buffer.scala 334:76] - node _T_1596 = and(obuf_merge_en, _T_1595) @[lsu_bus_buffer.scala 334:59] - node _T_1597 = bits(obuf_data1_in, 39, 32) @[lsu_bus_buffer.scala 334:94] - node _T_1598 = bits(obuf_data0_in, 39, 32) @[lsu_bus_buffer.scala 334:123] - node _T_1599 = mux(_T_1596, _T_1597, _T_1598) @[lsu_bus_buffer.scala 334:44] - node _T_1600 = bits(obuf_byteen1_in, 5, 5) @[lsu_bus_buffer.scala 334:76] - node _T_1601 = and(obuf_merge_en, _T_1600) @[lsu_bus_buffer.scala 334:59] - node _T_1602 = bits(obuf_data1_in, 47, 40) @[lsu_bus_buffer.scala 334:94] - node _T_1603 = bits(obuf_data0_in, 47, 40) @[lsu_bus_buffer.scala 334:123] - node _T_1604 = mux(_T_1601, _T_1602, _T_1603) @[lsu_bus_buffer.scala 334:44] - node _T_1605 = bits(obuf_byteen1_in, 6, 6) @[lsu_bus_buffer.scala 334:76] - node _T_1606 = and(obuf_merge_en, _T_1605) @[lsu_bus_buffer.scala 334:59] - node _T_1607 = bits(obuf_data1_in, 55, 48) @[lsu_bus_buffer.scala 334:94] - node _T_1608 = bits(obuf_data0_in, 55, 48) @[lsu_bus_buffer.scala 334:123] - node _T_1609 = mux(_T_1606, _T_1607, _T_1608) @[lsu_bus_buffer.scala 334:44] - node _T_1610 = bits(obuf_byteen1_in, 7, 7) @[lsu_bus_buffer.scala 334:76] - node _T_1611 = and(obuf_merge_en, _T_1610) @[lsu_bus_buffer.scala 334:59] - node _T_1612 = bits(obuf_data1_in, 63, 56) @[lsu_bus_buffer.scala 334:94] - node _T_1613 = bits(obuf_data0_in, 63, 56) @[lsu_bus_buffer.scala 334:123] - node _T_1614 = mux(_T_1611, _T_1612, _T_1613) @[lsu_bus_buffer.scala 334:44] + node _T_1575 = bits(obuf_byteen1_in, 0, 0) @[lsu_bus_buffer.scala 333:76] + node _T_1576 = and(obuf_merge_en, _T_1575) @[lsu_bus_buffer.scala 333:59] + node _T_1577 = bits(obuf_data1_in, 7, 0) @[lsu_bus_buffer.scala 333:94] + node _T_1578 = bits(obuf_data0_in, 7, 0) @[lsu_bus_buffer.scala 333:123] + node _T_1579 = mux(_T_1576, _T_1577, _T_1578) @[lsu_bus_buffer.scala 333:44] + node _T_1580 = bits(obuf_byteen1_in, 1, 1) @[lsu_bus_buffer.scala 333:76] + node _T_1581 = and(obuf_merge_en, _T_1580) @[lsu_bus_buffer.scala 333:59] + node _T_1582 = bits(obuf_data1_in, 15, 8) @[lsu_bus_buffer.scala 333:94] + node _T_1583 = bits(obuf_data0_in, 15, 8) @[lsu_bus_buffer.scala 333:123] + node _T_1584 = mux(_T_1581, _T_1582, _T_1583) @[lsu_bus_buffer.scala 333:44] + node _T_1585 = bits(obuf_byteen1_in, 2, 2) @[lsu_bus_buffer.scala 333:76] + node _T_1586 = and(obuf_merge_en, _T_1585) @[lsu_bus_buffer.scala 333:59] + node _T_1587 = bits(obuf_data1_in, 23, 16) @[lsu_bus_buffer.scala 333:94] + node _T_1588 = bits(obuf_data0_in, 23, 16) @[lsu_bus_buffer.scala 333:123] + node _T_1589 = mux(_T_1586, _T_1587, _T_1588) @[lsu_bus_buffer.scala 333:44] + node _T_1590 = bits(obuf_byteen1_in, 3, 3) @[lsu_bus_buffer.scala 333:76] + node _T_1591 = and(obuf_merge_en, _T_1590) @[lsu_bus_buffer.scala 333:59] + node _T_1592 = bits(obuf_data1_in, 31, 24) @[lsu_bus_buffer.scala 333:94] + node _T_1593 = bits(obuf_data0_in, 31, 24) @[lsu_bus_buffer.scala 333:123] + node _T_1594 = mux(_T_1591, _T_1592, _T_1593) @[lsu_bus_buffer.scala 333:44] + node _T_1595 = bits(obuf_byteen1_in, 4, 4) @[lsu_bus_buffer.scala 333:76] + node _T_1596 = and(obuf_merge_en, _T_1595) @[lsu_bus_buffer.scala 333:59] + node _T_1597 = bits(obuf_data1_in, 39, 32) @[lsu_bus_buffer.scala 333:94] + node _T_1598 = bits(obuf_data0_in, 39, 32) @[lsu_bus_buffer.scala 333:123] + node _T_1599 = mux(_T_1596, _T_1597, _T_1598) @[lsu_bus_buffer.scala 333:44] + node _T_1600 = bits(obuf_byteen1_in, 5, 5) @[lsu_bus_buffer.scala 333:76] + node _T_1601 = and(obuf_merge_en, _T_1600) @[lsu_bus_buffer.scala 333:59] + node _T_1602 = bits(obuf_data1_in, 47, 40) @[lsu_bus_buffer.scala 333:94] + node _T_1603 = bits(obuf_data0_in, 47, 40) @[lsu_bus_buffer.scala 333:123] + node _T_1604 = mux(_T_1601, _T_1602, _T_1603) @[lsu_bus_buffer.scala 333:44] + node _T_1605 = bits(obuf_byteen1_in, 6, 6) @[lsu_bus_buffer.scala 333:76] + node _T_1606 = and(obuf_merge_en, _T_1605) @[lsu_bus_buffer.scala 333:59] + node _T_1607 = bits(obuf_data1_in, 55, 48) @[lsu_bus_buffer.scala 333:94] + node _T_1608 = bits(obuf_data0_in, 55, 48) @[lsu_bus_buffer.scala 333:123] + node _T_1609 = mux(_T_1606, _T_1607, _T_1608) @[lsu_bus_buffer.scala 333:44] + node _T_1610 = bits(obuf_byteen1_in, 7, 7) @[lsu_bus_buffer.scala 333:76] + node _T_1611 = and(obuf_merge_en, _T_1610) @[lsu_bus_buffer.scala 333:59] + node _T_1612 = bits(obuf_data1_in, 63, 56) @[lsu_bus_buffer.scala 333:94] + node _T_1613 = bits(obuf_data0_in, 63, 56) @[lsu_bus_buffer.scala 333:123] + node _T_1614 = mux(_T_1611, _T_1612, _T_1613) @[lsu_bus_buffer.scala 333:44] node _T_1615 = cat(_T_1614, _T_1609) @[Cat.scala 29:58] node _T_1616 = cat(_T_1615, _T_1604) @[Cat.scala 29:58] node _T_1617 = cat(_T_1616, _T_1599) @[Cat.scala 29:58] @@ -96946,14 +96943,14 @@ circuit quasar_wrapper : node _T_1619 = cat(_T_1618, _T_1589) @[Cat.scala 29:58] node _T_1620 = cat(_T_1619, _T_1584) @[Cat.scala 29:58] node obuf_data_in = cat(_T_1620, _T_1579) @[Cat.scala 29:58] - wire buf_dualhi : UInt<1>[4] @[lsu_bus_buffer.scala 336:24] - buf_dualhi[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 337:14] - buf_dualhi[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 337:14] - buf_dualhi[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 337:14] - buf_dualhi[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 337:14] - node _T_1621 = neq(CmdPtr0, CmdPtr1) @[lsu_bus_buffer.scala 338:30] - node _T_1622 = and(_T_1621, found_cmdptr0) @[lsu_bus_buffer.scala 338:43] - node _T_1623 = and(_T_1622, found_cmdptr1) @[lsu_bus_buffer.scala 338:59] + wire buf_dualhi : UInt<1>[4] @[lsu_bus_buffer.scala 335:24] + buf_dualhi[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 336:14] + buf_dualhi[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 336:14] + buf_dualhi[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 336:14] + buf_dualhi[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 336:14] + node _T_1621 = neq(CmdPtr0, CmdPtr1) @[lsu_bus_buffer.scala 337:30] + node _T_1622 = and(_T_1621, found_cmdptr0) @[lsu_bus_buffer.scala 337:43] + node _T_1623 = and(_T_1622, found_cmdptr1) @[lsu_bus_buffer.scala 337:59] node _T_1624 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] node _T_1625 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] node _T_1626 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] @@ -96967,8 +96964,8 @@ circuit quasar_wrapper : node _T_1634 = or(_T_1633, _T_1631) @[Mux.scala 27:72] wire _T_1635 : UInt<3> @[Mux.scala 27:72] _T_1635 <= _T_1634 @[Mux.scala 27:72] - node _T_1636 = eq(_T_1635, UInt<3>("h02")) @[lsu_bus_buffer.scala 338:107] - node _T_1637 = and(_T_1623, _T_1636) @[lsu_bus_buffer.scala 338:75] + node _T_1636 = eq(_T_1635, UInt<3>("h02")) @[lsu_bus_buffer.scala 337:107] + node _T_1637 = and(_T_1623, _T_1636) @[lsu_bus_buffer.scala 337:75] node _T_1638 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] node _T_1639 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] node _T_1640 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] @@ -96982,8 +96979,8 @@ circuit quasar_wrapper : node _T_1648 = or(_T_1647, _T_1645) @[Mux.scala 27:72] wire _T_1649 : UInt<3> @[Mux.scala 27:72] _T_1649 <= _T_1648 @[Mux.scala 27:72] - node _T_1650 = eq(_T_1649, UInt<3>("h02")) @[lsu_bus_buffer.scala 338:150] - node _T_1651 = and(_T_1637, _T_1650) @[lsu_bus_buffer.scala 338:118] + node _T_1650 = eq(_T_1649, UInt<3>("h02")) @[lsu_bus_buffer.scala 337:150] + node _T_1651 = and(_T_1637, _T_1650) @[lsu_bus_buffer.scala 337:118] node _T_1652 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] node _T_1653 = cat(_T_1652, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] node _T_1654 = cat(_T_1653, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] @@ -97004,8 +97001,8 @@ circuit quasar_wrapper : node _T_1669 = or(_T_1668, _T_1666) @[Mux.scala 27:72] wire _T_1670 : UInt<1> @[Mux.scala 27:72] _T_1670 <= _T_1669 @[Mux.scala 27:72] - node _T_1671 = eq(_T_1670, UInt<1>("h00")) @[lsu_bus_buffer.scala 339:5] - node _T_1672 = and(_T_1651, _T_1671) @[lsu_bus_buffer.scala 338:161] + node _T_1671 = eq(_T_1670, UInt<1>("h00")) @[lsu_bus_buffer.scala 338:5] + node _T_1672 = and(_T_1651, _T_1671) @[lsu_bus_buffer.scala 337:161] node _T_1673 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] node _T_1674 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 57:129] node _T_1675 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] @@ -97023,8 +97020,8 @@ circuit quasar_wrapper : node _T_1687 = or(_T_1686, _T_1684) @[Mux.scala 27:72] wire _T_1688 : UInt<1> @[Mux.scala 27:72] _T_1688 <= _T_1687 @[Mux.scala 27:72] - node _T_1689 = eq(_T_1688, UInt<1>("h00")) @[lsu_bus_buffer.scala 339:87] - node _T_1690 = and(_T_1672, _T_1689) @[lsu_bus_buffer.scala 339:85] + node _T_1689 = eq(_T_1688, UInt<1>("h00")) @[lsu_bus_buffer.scala 338:87] + node _T_1690 = and(_T_1672, _T_1689) @[lsu_bus_buffer.scala 338:85] node _T_1691 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] node _T_1692 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 57:129] node _T_1693 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] @@ -97059,7 +97056,7 @@ circuit quasar_wrapper : node _T_1721 = or(_T_1720, _T_1718) @[Mux.scala 27:72] wire _T_1722 : UInt<1> @[Mux.scala 27:72] _T_1722 <= _T_1721 @[Mux.scala 27:72] - node _T_1723 = and(_T_1706, _T_1722) @[lsu_bus_buffer.scala 340:36] + node _T_1723 = and(_T_1706, _T_1722) @[lsu_bus_buffer.scala 339:36] node _T_1724 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] node _T_1725 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] node _T_1726 = eq(CmdPtr0, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] @@ -97073,7 +97070,7 @@ circuit quasar_wrapper : node _T_1734 = or(_T_1733, _T_1731) @[Mux.scala 27:72] wire _T_1735 : UInt<32> @[Mux.scala 27:72] _T_1735 <= _T_1734 @[Mux.scala 27:72] - node _T_1736 = bits(_T_1735, 31, 3) @[lsu_bus_buffer.scala 341:35] + node _T_1736 = bits(_T_1735, 31, 3) @[lsu_bus_buffer.scala 340:35] node _T_1737 = eq(CmdPtr1, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] node _T_1738 = eq(CmdPtr1, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] node _T_1739 = eq(CmdPtr1, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] @@ -97087,13 +97084,13 @@ circuit quasar_wrapper : node _T_1747 = or(_T_1746, _T_1744) @[Mux.scala 27:72] wire _T_1748 : UInt<32> @[Mux.scala 27:72] _T_1748 <= _T_1747 @[Mux.scala 27:72] - node _T_1749 = bits(_T_1748, 31, 3) @[lsu_bus_buffer.scala 341:71] - node _T_1750 = eq(_T_1736, _T_1749) @[lsu_bus_buffer.scala 341:41] - node _T_1751 = and(_T_1723, _T_1750) @[lsu_bus_buffer.scala 340:67] - node _T_1752 = eq(bus_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 341:81] - node _T_1753 = and(_T_1751, _T_1752) @[lsu_bus_buffer.scala 341:79] - node _T_1754 = eq(UInt<1>("h01"), UInt<1>("h00")) @[lsu_bus_buffer.scala 341:107] - node _T_1755 = and(_T_1753, _T_1754) @[lsu_bus_buffer.scala 341:105] + node _T_1749 = bits(_T_1748, 31, 3) @[lsu_bus_buffer.scala 340:71] + node _T_1750 = eq(_T_1736, _T_1749) @[lsu_bus_buffer.scala 340:41] + node _T_1751 = and(_T_1723, _T_1750) @[lsu_bus_buffer.scala 339:67] + node _T_1752 = eq(bus_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 340:81] + node _T_1753 = and(_T_1751, _T_1752) @[lsu_bus_buffer.scala 340:79] + node _T_1754 = eq(UInt<1>("h01"), UInt<1>("h00")) @[lsu_bus_buffer.scala 340:107] + node _T_1755 = and(_T_1753, _T_1754) @[lsu_bus_buffer.scala 340:105] node _T_1756 = eq(CmdPtr0, UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] node _T_1757 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 57:129] node _T_1758 = eq(CmdPtr0, UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] @@ -97111,7 +97108,7 @@ circuit quasar_wrapper : node _T_1770 = or(_T_1769, _T_1767) @[Mux.scala 27:72] wire _T_1771 : UInt<1> @[Mux.scala 27:72] _T_1771 <= _T_1770 @[Mux.scala 27:72] - node _T_1772 = eq(_T_1771, UInt<1>("h00")) @[lsu_bus_buffer.scala 342:8] + node _T_1772 = eq(_T_1771, UInt<1>("h00")) @[lsu_bus_buffer.scala 341:8] node _T_1773 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] node _T_1774 = cat(_T_1773, buf_dual[1]) @[Cat.scala 29:58] node _T_1775 = cat(_T_1774, buf_dual[0]) @[Cat.scala 29:58] @@ -97132,7 +97129,7 @@ circuit quasar_wrapper : node _T_1790 = or(_T_1789, _T_1787) @[Mux.scala 27:72] wire _T_1791 : UInt<1> @[Mux.scala 27:72] _T_1791 <= _T_1790 @[Mux.scala 27:72] - node _T_1792 = and(_T_1772, _T_1791) @[lsu_bus_buffer.scala 342:38] + node _T_1792 = and(_T_1772, _T_1791) @[lsu_bus_buffer.scala 341:38] node _T_1793 = cat(buf_dualhi[3], buf_dualhi[2]) @[Cat.scala 29:58] node _T_1794 = cat(_T_1793, buf_dualhi[1]) @[Cat.scala 29:58] node _T_1795 = cat(_T_1794, buf_dualhi[0]) @[Cat.scala 29:58] @@ -97153,8 +97150,8 @@ circuit quasar_wrapper : node _T_1810 = or(_T_1809, _T_1807) @[Mux.scala 27:72] wire _T_1811 : UInt<1> @[Mux.scala 27:72] _T_1811 <= _T_1810 @[Mux.scala 27:72] - node _T_1812 = eq(_T_1811, UInt<1>("h00")) @[lsu_bus_buffer.scala 342:109] - node _T_1813 = and(_T_1792, _T_1812) @[lsu_bus_buffer.scala 342:107] + node _T_1812 = eq(_T_1811, UInt<1>("h00")) @[lsu_bus_buffer.scala 341:109] + node _T_1813 = and(_T_1792, _T_1812) @[lsu_bus_buffer.scala 341:107] node _T_1814 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] node _T_1815 = cat(_T_1814, buf_samedw[1]) @[Cat.scala 29:58] node _T_1816 = cat(_T_1815, buf_samedw[0]) @[Cat.scala 29:58] @@ -97175,43 +97172,43 @@ circuit quasar_wrapper : node _T_1831 = or(_T_1830, _T_1828) @[Mux.scala 27:72] wire _T_1832 : UInt<1> @[Mux.scala 27:72] _T_1832 <= _T_1831 @[Mux.scala 27:72] - node _T_1833 = and(_T_1813, _T_1832) @[lsu_bus_buffer.scala 342:179] - node _T_1834 = or(_T_1755, _T_1833) @[lsu_bus_buffer.scala 341:128] - node _T_1835 = and(_T_1690, _T_1834) @[lsu_bus_buffer.scala 339:122] - node _T_1836 = and(ibuf_buf_byp, ldst_samedw_r) @[lsu_bus_buffer.scala 343:19] - node _T_1837 = and(_T_1836, io.ldst_dual_r) @[lsu_bus_buffer.scala 343:35] - node _T_1838 = or(_T_1835, _T_1837) @[lsu_bus_buffer.scala 342:253] - obuf_merge_en <= _T_1838 @[lsu_bus_buffer.scala 338:17] - reg obuf_wr_enQ : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 345:55] - obuf_wr_enQ <= obuf_wr_en @[lsu_bus_buffer.scala 345:55] - node _T_1839 = mux(obuf_wr_en, UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 346:58] - node _T_1840 = eq(obuf_rst, UInt<1>("h00")) @[lsu_bus_buffer.scala 346:93] - node _T_1841 = and(_T_1839, _T_1840) @[lsu_bus_buffer.scala 346:91] - reg _T_1842 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 346:54] - _T_1842 <= _T_1841 @[lsu_bus_buffer.scala 346:54] - obuf_valid <= _T_1842 @[lsu_bus_buffer.scala 346:14] + node _T_1833 = and(_T_1813, _T_1832) @[lsu_bus_buffer.scala 341:179] + node _T_1834 = or(_T_1755, _T_1833) @[lsu_bus_buffer.scala 340:128] + node _T_1835 = and(_T_1690, _T_1834) @[lsu_bus_buffer.scala 338:122] + node _T_1836 = and(ibuf_buf_byp, ldst_samedw_r) @[lsu_bus_buffer.scala 342:19] + node _T_1837 = and(_T_1836, io.ldst_dual_r) @[lsu_bus_buffer.scala 342:35] + node _T_1838 = or(_T_1835, _T_1837) @[lsu_bus_buffer.scala 341:253] + obuf_merge_en <= _T_1838 @[lsu_bus_buffer.scala 337:17] + reg obuf_wr_enQ : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 344:55] + obuf_wr_enQ <= obuf_wr_en @[lsu_bus_buffer.scala 344:55] + node _T_1839 = mux(obuf_wr_en, UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 345:58] + node _T_1840 = eq(obuf_rst, UInt<1>("h00")) @[lsu_bus_buffer.scala 345:93] + node _T_1841 = and(_T_1839, _T_1840) @[lsu_bus_buffer.scala 345:91] + reg _T_1842 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 345:54] + _T_1842 <= _T_1841 @[lsu_bus_buffer.scala 345:54] + obuf_valid <= _T_1842 @[lsu_bus_buffer.scala 345:14] reg _T_1843 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] _T_1843 <= obuf_nosend_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_nosend <= _T_1843 @[lsu_bus_buffer.scala 347:15] - reg _T_1844 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 348:54] - _T_1844 <= obuf_cmd_done_in @[lsu_bus_buffer.scala 348:54] - obuf_cmd_done <= _T_1844 @[lsu_bus_buffer.scala 348:17] - reg _T_1845 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 349:55] - _T_1845 <= obuf_data_done_in @[lsu_bus_buffer.scala 349:55] - obuf_data_done <= _T_1845 @[lsu_bus_buffer.scala 349:18] - reg _T_1846 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 350:56] - _T_1846 <= obuf_rdrsp_pend_in @[lsu_bus_buffer.scala 350:56] - obuf_rdrsp_pend <= _T_1846 @[lsu_bus_buffer.scala 350:19] - reg _T_1847 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 351:55] - _T_1847 <= obuf_rdrsp_tag_in @[lsu_bus_buffer.scala 351:55] - obuf_rdrsp_tag <= _T_1847 @[lsu_bus_buffer.scala 351:18] + obuf_nosend <= _T_1843 @[lsu_bus_buffer.scala 346:15] + reg _T_1844 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 347:54] + _T_1844 <= obuf_cmd_done_in @[lsu_bus_buffer.scala 347:54] + obuf_cmd_done <= _T_1844 @[lsu_bus_buffer.scala 347:17] + reg _T_1845 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 348:55] + _T_1845 <= obuf_data_done_in @[lsu_bus_buffer.scala 348:55] + obuf_data_done <= _T_1845 @[lsu_bus_buffer.scala 348:18] + reg _T_1846 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 349:56] + _T_1846 <= obuf_rdrsp_pend_in @[lsu_bus_buffer.scala 349:56] + obuf_rdrsp_pend <= _T_1846 @[lsu_bus_buffer.scala 349:19] + reg _T_1847 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 350:55] + _T_1847 <= obuf_rdrsp_tag_in @[lsu_bus_buffer.scala 350:55] + obuf_rdrsp_tag <= _T_1847 @[lsu_bus_buffer.scala 350:18] reg _T_1848 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] _T_1848 <= obuf_tag0_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_tag0 <= _T_1848 @[lsu_bus_buffer.scala 352:13] + obuf_tag0 <= _T_1848 @[lsu_bus_buffer.scala 351:13] reg obuf_tag1 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] obuf_tag1 <= obuf_tag1_in @[Reg.scala 28:23] @@ -97224,12 +97221,12 @@ circuit quasar_wrapper : when obuf_wr_en : @[Reg.scala 28:19] _T_1849 <= obuf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_write <= _T_1849 @[lsu_bus_buffer.scala 355:14] + obuf_write <= _T_1849 @[lsu_bus_buffer.scala 354:14] reg _T_1850 : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] _T_1850 <= obuf_sideeffect_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_sideeffect <= _T_1850 @[lsu_bus_buffer.scala 356:19] + obuf_sideeffect <= _T_1850 @[lsu_bus_buffer.scala 355:19] reg obuf_sz : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] obuf_sz <= obuf_sz_in @[Reg.scala 28:23] @@ -97242,7 +97239,7 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_1851 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_1851 <= obuf_addr_in @[lib.scala 358:16] - obuf_addr <= _T_1851 @[lsu_bus_buffer.scala 358:13] + obuf_addr <= _T_1851 @[lsu_bus_buffer.scala 357:13] reg obuf_byteen : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] obuf_byteen <= obuf_byteen_in @[Reg.scala 28:23] @@ -97255,1901 +97252,1901 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg obuf_data : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] obuf_data <= obuf_data_in @[lib.scala 358:16] - reg _T_1852 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 361:54] - _T_1852 <= obuf_wr_timer_in @[lsu_bus_buffer.scala 361:54] - obuf_wr_timer <= _T_1852 @[lsu_bus_buffer.scala 361:17] + reg _T_1852 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 360:54] + _T_1852 <= obuf_wr_timer_in @[lsu_bus_buffer.scala 360:54] + obuf_wr_timer <= _T_1852 @[lsu_bus_buffer.scala 360:17] wire WrPtr0_m : UInt<2> WrPtr0_m <= UInt<1>("h00") - node _T_1853 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 364:65] - node _T_1854 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 365:30] - node _T_1855 = and(ibuf_valid, _T_1854) @[lsu_bus_buffer.scala 365:19] - node _T_1856 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 366:18] - node _T_1857 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 366:57] - node _T_1858 = and(io.ldst_dual_r, _T_1857) @[lsu_bus_buffer.scala 366:45] - node _T_1859 = or(_T_1856, _T_1858) @[lsu_bus_buffer.scala 366:27] - node _T_1860 = and(io.lsu_busreq_r, _T_1859) @[lsu_bus_buffer.scala 365:58] - node _T_1861 = or(_T_1855, _T_1860) @[lsu_bus_buffer.scala 365:39] - node _T_1862 = eq(_T_1861, UInt<1>("h00")) @[lsu_bus_buffer.scala 365:5] - node _T_1863 = and(_T_1853, _T_1862) @[lsu_bus_buffer.scala 364:76] - node _T_1864 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 364:65] - node _T_1865 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 365:30] - node _T_1866 = and(ibuf_valid, _T_1865) @[lsu_bus_buffer.scala 365:19] - node _T_1867 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 366:18] - node _T_1868 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 366:57] - node _T_1869 = and(io.ldst_dual_r, _T_1868) @[lsu_bus_buffer.scala 366:45] - node _T_1870 = or(_T_1867, _T_1869) @[lsu_bus_buffer.scala 366:27] - node _T_1871 = and(io.lsu_busreq_r, _T_1870) @[lsu_bus_buffer.scala 365:58] - node _T_1872 = or(_T_1866, _T_1871) @[lsu_bus_buffer.scala 365:39] - node _T_1873 = eq(_T_1872, UInt<1>("h00")) @[lsu_bus_buffer.scala 365:5] - node _T_1874 = and(_T_1864, _T_1873) @[lsu_bus_buffer.scala 364:76] - node _T_1875 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 364:65] - node _T_1876 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 365:30] - node _T_1877 = and(ibuf_valid, _T_1876) @[lsu_bus_buffer.scala 365:19] - node _T_1878 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 366:18] - node _T_1879 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 366:57] - node _T_1880 = and(io.ldst_dual_r, _T_1879) @[lsu_bus_buffer.scala 366:45] - node _T_1881 = or(_T_1878, _T_1880) @[lsu_bus_buffer.scala 366:27] - node _T_1882 = and(io.lsu_busreq_r, _T_1881) @[lsu_bus_buffer.scala 365:58] - node _T_1883 = or(_T_1877, _T_1882) @[lsu_bus_buffer.scala 365:39] - node _T_1884 = eq(_T_1883, UInt<1>("h00")) @[lsu_bus_buffer.scala 365:5] - node _T_1885 = and(_T_1875, _T_1884) @[lsu_bus_buffer.scala 364:76] - node _T_1886 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 364:65] - node _T_1887 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 365:30] - node _T_1888 = and(ibuf_valid, _T_1887) @[lsu_bus_buffer.scala 365:19] - node _T_1889 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 366:18] - node _T_1890 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 366:57] - node _T_1891 = and(io.ldst_dual_r, _T_1890) @[lsu_bus_buffer.scala 366:45] - node _T_1892 = or(_T_1889, _T_1891) @[lsu_bus_buffer.scala 366:27] - node _T_1893 = and(io.lsu_busreq_r, _T_1892) @[lsu_bus_buffer.scala 365:58] - node _T_1894 = or(_T_1888, _T_1893) @[lsu_bus_buffer.scala 365:39] - node _T_1895 = eq(_T_1894, UInt<1>("h00")) @[lsu_bus_buffer.scala 365:5] - node _T_1896 = and(_T_1886, _T_1895) @[lsu_bus_buffer.scala 364:76] + node _T_1853 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 363:65] + node _T_1854 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 364:30] + node _T_1855 = and(ibuf_valid, _T_1854) @[lsu_bus_buffer.scala 364:19] + node _T_1856 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 365:18] + node _T_1857 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 365:57] + node _T_1858 = and(io.ldst_dual_r, _T_1857) @[lsu_bus_buffer.scala 365:45] + node _T_1859 = or(_T_1856, _T_1858) @[lsu_bus_buffer.scala 365:27] + node _T_1860 = and(io.lsu_busreq_r, _T_1859) @[lsu_bus_buffer.scala 364:58] + node _T_1861 = or(_T_1855, _T_1860) @[lsu_bus_buffer.scala 364:39] + node _T_1862 = eq(_T_1861, UInt<1>("h00")) @[lsu_bus_buffer.scala 364:5] + node _T_1863 = and(_T_1853, _T_1862) @[lsu_bus_buffer.scala 363:76] + node _T_1864 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 363:65] + node _T_1865 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 364:30] + node _T_1866 = and(ibuf_valid, _T_1865) @[lsu_bus_buffer.scala 364:19] + node _T_1867 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 365:18] + node _T_1868 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 365:57] + node _T_1869 = and(io.ldst_dual_r, _T_1868) @[lsu_bus_buffer.scala 365:45] + node _T_1870 = or(_T_1867, _T_1869) @[lsu_bus_buffer.scala 365:27] + node _T_1871 = and(io.lsu_busreq_r, _T_1870) @[lsu_bus_buffer.scala 364:58] + node _T_1872 = or(_T_1866, _T_1871) @[lsu_bus_buffer.scala 364:39] + node _T_1873 = eq(_T_1872, UInt<1>("h00")) @[lsu_bus_buffer.scala 364:5] + node _T_1874 = and(_T_1864, _T_1873) @[lsu_bus_buffer.scala 363:76] + node _T_1875 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 363:65] + node _T_1876 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 364:30] + node _T_1877 = and(ibuf_valid, _T_1876) @[lsu_bus_buffer.scala 364:19] + node _T_1878 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 365:18] + node _T_1879 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 365:57] + node _T_1880 = and(io.ldst_dual_r, _T_1879) @[lsu_bus_buffer.scala 365:45] + node _T_1881 = or(_T_1878, _T_1880) @[lsu_bus_buffer.scala 365:27] + node _T_1882 = and(io.lsu_busreq_r, _T_1881) @[lsu_bus_buffer.scala 364:58] + node _T_1883 = or(_T_1877, _T_1882) @[lsu_bus_buffer.scala 364:39] + node _T_1884 = eq(_T_1883, UInt<1>("h00")) @[lsu_bus_buffer.scala 364:5] + node _T_1885 = and(_T_1875, _T_1884) @[lsu_bus_buffer.scala 363:76] + node _T_1886 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 363:65] + node _T_1887 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 364:30] + node _T_1888 = and(ibuf_valid, _T_1887) @[lsu_bus_buffer.scala 364:19] + node _T_1889 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 365:18] + node _T_1890 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 365:57] + node _T_1891 = and(io.ldst_dual_r, _T_1890) @[lsu_bus_buffer.scala 365:45] + node _T_1892 = or(_T_1889, _T_1891) @[lsu_bus_buffer.scala 365:27] + node _T_1893 = and(io.lsu_busreq_r, _T_1892) @[lsu_bus_buffer.scala 364:58] + node _T_1894 = or(_T_1888, _T_1893) @[lsu_bus_buffer.scala 364:39] + node _T_1895 = eq(_T_1894, UInt<1>("h00")) @[lsu_bus_buffer.scala 364:5] + node _T_1896 = and(_T_1886, _T_1895) @[lsu_bus_buffer.scala 363:76] node _T_1897 = mux(_T_1896, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] node _T_1898 = mux(_T_1885, UInt<2>("h02"), _T_1897) @[Mux.scala 98:16] node _T_1899 = mux(_T_1874, UInt<1>("h01"), _T_1898) @[Mux.scala 98:16] node _T_1900 = mux(_T_1863, UInt<1>("h00"), _T_1899) @[Mux.scala 98:16] - WrPtr0_m <= _T_1900 @[lsu_bus_buffer.scala 364:12] + WrPtr0_m <= _T_1900 @[lsu_bus_buffer.scala 363:12] wire WrPtr1_m : UInt<2> WrPtr1_m <= UInt<1>("h00") - node _T_1901 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 370:65] - node _T_1902 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:103] - node _T_1903 = and(ibuf_valid, _T_1902) @[lsu_bus_buffer.scala 370:92] - node _T_1904 = eq(WrPtr0_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 371:33] - node _T_1905 = and(io.lsu_busreq_m, _T_1904) @[lsu_bus_buffer.scala 371:22] - node _T_1906 = or(_T_1903, _T_1905) @[lsu_bus_buffer.scala 370:112] - node _T_1907 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 372:36] - node _T_1908 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 373:34] - node _T_1909 = and(io.ldst_dual_r, _T_1908) @[lsu_bus_buffer.scala 373:23] - node _T_1910 = or(_T_1907, _T_1909) @[lsu_bus_buffer.scala 372:46] - node _T_1911 = and(io.lsu_busreq_r, _T_1910) @[lsu_bus_buffer.scala 372:22] - node _T_1912 = or(_T_1906, _T_1911) @[lsu_bus_buffer.scala 371:42] - node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:78] - node _T_1914 = and(_T_1901, _T_1913) @[lsu_bus_buffer.scala 370:76] - node _T_1915 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 370:65] - node _T_1916 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 370:103] - node _T_1917 = and(ibuf_valid, _T_1916) @[lsu_bus_buffer.scala 370:92] - node _T_1918 = eq(WrPtr0_m, UInt<1>("h01")) @[lsu_bus_buffer.scala 371:33] - node _T_1919 = and(io.lsu_busreq_m, _T_1918) @[lsu_bus_buffer.scala 371:22] - node _T_1920 = or(_T_1917, _T_1919) @[lsu_bus_buffer.scala 370:112] - node _T_1921 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 372:36] - node _T_1922 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 373:34] - node _T_1923 = and(io.ldst_dual_r, _T_1922) @[lsu_bus_buffer.scala 373:23] - node _T_1924 = or(_T_1921, _T_1923) @[lsu_bus_buffer.scala 372:46] - node _T_1925 = and(io.lsu_busreq_r, _T_1924) @[lsu_bus_buffer.scala 372:22] - node _T_1926 = or(_T_1920, _T_1925) @[lsu_bus_buffer.scala 371:42] - node _T_1927 = eq(_T_1926, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:78] - node _T_1928 = and(_T_1915, _T_1927) @[lsu_bus_buffer.scala 370:76] - node _T_1929 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 370:65] - node _T_1930 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 370:103] - node _T_1931 = and(ibuf_valid, _T_1930) @[lsu_bus_buffer.scala 370:92] - node _T_1932 = eq(WrPtr0_m, UInt<2>("h02")) @[lsu_bus_buffer.scala 371:33] - node _T_1933 = and(io.lsu_busreq_m, _T_1932) @[lsu_bus_buffer.scala 371:22] - node _T_1934 = or(_T_1931, _T_1933) @[lsu_bus_buffer.scala 370:112] - node _T_1935 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 372:36] - node _T_1936 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 373:34] - node _T_1937 = and(io.ldst_dual_r, _T_1936) @[lsu_bus_buffer.scala 373:23] - node _T_1938 = or(_T_1935, _T_1937) @[lsu_bus_buffer.scala 372:46] - node _T_1939 = and(io.lsu_busreq_r, _T_1938) @[lsu_bus_buffer.scala 372:22] - node _T_1940 = or(_T_1934, _T_1939) @[lsu_bus_buffer.scala 371:42] - node _T_1941 = eq(_T_1940, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:78] - node _T_1942 = and(_T_1929, _T_1941) @[lsu_bus_buffer.scala 370:76] - node _T_1943 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 370:65] - node _T_1944 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 370:103] - node _T_1945 = and(ibuf_valid, _T_1944) @[lsu_bus_buffer.scala 370:92] - node _T_1946 = eq(WrPtr0_m, UInt<2>("h03")) @[lsu_bus_buffer.scala 371:33] - node _T_1947 = and(io.lsu_busreq_m, _T_1946) @[lsu_bus_buffer.scala 371:22] - node _T_1948 = or(_T_1945, _T_1947) @[lsu_bus_buffer.scala 370:112] - node _T_1949 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 372:36] - node _T_1950 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 373:34] - node _T_1951 = and(io.ldst_dual_r, _T_1950) @[lsu_bus_buffer.scala 373:23] - node _T_1952 = or(_T_1949, _T_1951) @[lsu_bus_buffer.scala 372:46] - node _T_1953 = and(io.lsu_busreq_r, _T_1952) @[lsu_bus_buffer.scala 372:22] - node _T_1954 = or(_T_1948, _T_1953) @[lsu_bus_buffer.scala 371:42] - node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:78] - node _T_1956 = and(_T_1943, _T_1955) @[lsu_bus_buffer.scala 370:76] + node _T_1901 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1902 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 369:103] + node _T_1903 = and(ibuf_valid, _T_1902) @[lsu_bus_buffer.scala 369:92] + node _T_1904 = eq(WrPtr0_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 370:33] + node _T_1905 = and(io.lsu_busreq_m, _T_1904) @[lsu_bus_buffer.scala 370:22] + node _T_1906 = or(_T_1903, _T_1905) @[lsu_bus_buffer.scala 369:112] + node _T_1907 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 371:36] + node _T_1908 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 372:34] + node _T_1909 = and(io.ldst_dual_r, _T_1908) @[lsu_bus_buffer.scala 372:23] + node _T_1910 = or(_T_1907, _T_1909) @[lsu_bus_buffer.scala 371:46] + node _T_1911 = and(io.lsu_busreq_r, _T_1910) @[lsu_bus_buffer.scala 371:22] + node _T_1912 = or(_T_1906, _T_1911) @[lsu_bus_buffer.scala 370:42] + node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[lsu_bus_buffer.scala 369:78] + node _T_1914 = and(_T_1901, _T_1913) @[lsu_bus_buffer.scala 369:76] + node _T_1915 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1916 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 369:103] + node _T_1917 = and(ibuf_valid, _T_1916) @[lsu_bus_buffer.scala 369:92] + node _T_1918 = eq(WrPtr0_m, UInt<1>("h01")) @[lsu_bus_buffer.scala 370:33] + node _T_1919 = and(io.lsu_busreq_m, _T_1918) @[lsu_bus_buffer.scala 370:22] + node _T_1920 = or(_T_1917, _T_1919) @[lsu_bus_buffer.scala 369:112] + node _T_1921 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 371:36] + node _T_1922 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 372:34] + node _T_1923 = and(io.ldst_dual_r, _T_1922) @[lsu_bus_buffer.scala 372:23] + node _T_1924 = or(_T_1921, _T_1923) @[lsu_bus_buffer.scala 371:46] + node _T_1925 = and(io.lsu_busreq_r, _T_1924) @[lsu_bus_buffer.scala 371:22] + node _T_1926 = or(_T_1920, _T_1925) @[lsu_bus_buffer.scala 370:42] + node _T_1927 = eq(_T_1926, UInt<1>("h00")) @[lsu_bus_buffer.scala 369:78] + node _T_1928 = and(_T_1915, _T_1927) @[lsu_bus_buffer.scala 369:76] + node _T_1929 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1930 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 369:103] + node _T_1931 = and(ibuf_valid, _T_1930) @[lsu_bus_buffer.scala 369:92] + node _T_1932 = eq(WrPtr0_m, UInt<2>("h02")) @[lsu_bus_buffer.scala 370:33] + node _T_1933 = and(io.lsu_busreq_m, _T_1932) @[lsu_bus_buffer.scala 370:22] + node _T_1934 = or(_T_1931, _T_1933) @[lsu_bus_buffer.scala 369:112] + node _T_1935 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 371:36] + node _T_1936 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 372:34] + node _T_1937 = and(io.ldst_dual_r, _T_1936) @[lsu_bus_buffer.scala 372:23] + node _T_1938 = or(_T_1935, _T_1937) @[lsu_bus_buffer.scala 371:46] + node _T_1939 = and(io.lsu_busreq_r, _T_1938) @[lsu_bus_buffer.scala 371:22] + node _T_1940 = or(_T_1934, _T_1939) @[lsu_bus_buffer.scala 370:42] + node _T_1941 = eq(_T_1940, UInt<1>("h00")) @[lsu_bus_buffer.scala 369:78] + node _T_1942 = and(_T_1929, _T_1941) @[lsu_bus_buffer.scala 369:76] + node _T_1943 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 369:65] + node _T_1944 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 369:103] + node _T_1945 = and(ibuf_valid, _T_1944) @[lsu_bus_buffer.scala 369:92] + node _T_1946 = eq(WrPtr0_m, UInt<2>("h03")) @[lsu_bus_buffer.scala 370:33] + node _T_1947 = and(io.lsu_busreq_m, _T_1946) @[lsu_bus_buffer.scala 370:22] + node _T_1948 = or(_T_1945, _T_1947) @[lsu_bus_buffer.scala 369:112] + node _T_1949 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 371:36] + node _T_1950 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 372:34] + node _T_1951 = and(io.ldst_dual_r, _T_1950) @[lsu_bus_buffer.scala 372:23] + node _T_1952 = or(_T_1949, _T_1951) @[lsu_bus_buffer.scala 371:46] + node _T_1953 = and(io.lsu_busreq_r, _T_1952) @[lsu_bus_buffer.scala 371:22] + node _T_1954 = or(_T_1948, _T_1953) @[lsu_bus_buffer.scala 370:42] + node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[lsu_bus_buffer.scala 369:78] + node _T_1956 = and(_T_1943, _T_1955) @[lsu_bus_buffer.scala 369:76] node _T_1957 = mux(_T_1956, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] node _T_1958 = mux(_T_1942, UInt<2>("h02"), _T_1957) @[Mux.scala 98:16] node _T_1959 = mux(_T_1928, UInt<1>("h01"), _T_1958) @[Mux.scala 98:16] node _T_1960 = mux(_T_1914, UInt<1>("h00"), _T_1959) @[Mux.scala 98:16] - WrPtr1_m <= _T_1960 @[lsu_bus_buffer.scala 370:12] - wire buf_age : UInt<4>[4] @[lsu_bus_buffer.scala 375:21] - buf_age[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 376:11] - buf_age[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 376:11] - buf_age[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 376:11] - buf_age[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 376:11] - node _T_1961 = orr(buf_age[0]) @[lsu_bus_buffer.scala 378:58] - node _T_1962 = eq(_T_1961, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:45] - node _T_1963 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 378:78] - node _T_1964 = and(_T_1962, _T_1963) @[lsu_bus_buffer.scala 378:63] - node _T_1965 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 378:90] - node _T_1966 = and(_T_1964, _T_1965) @[lsu_bus_buffer.scala 378:88] - node _T_1967 = orr(buf_age[1]) @[lsu_bus_buffer.scala 378:58] - node _T_1968 = eq(_T_1967, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:45] - node _T_1969 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 378:78] - node _T_1970 = and(_T_1968, _T_1969) @[lsu_bus_buffer.scala 378:63] - node _T_1971 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 378:90] - node _T_1972 = and(_T_1970, _T_1971) @[lsu_bus_buffer.scala 378:88] - node _T_1973 = orr(buf_age[2]) @[lsu_bus_buffer.scala 378:58] - node _T_1974 = eq(_T_1973, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:45] - node _T_1975 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 378:78] - node _T_1976 = and(_T_1974, _T_1975) @[lsu_bus_buffer.scala 378:63] - node _T_1977 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 378:90] - node _T_1978 = and(_T_1976, _T_1977) @[lsu_bus_buffer.scala 378:88] - node _T_1979 = orr(buf_age[3]) @[lsu_bus_buffer.scala 378:58] - node _T_1980 = eq(_T_1979, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:45] - node _T_1981 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 378:78] - node _T_1982 = and(_T_1980, _T_1981) @[lsu_bus_buffer.scala 378:63] - node _T_1983 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 378:90] - node _T_1984 = and(_T_1982, _T_1983) @[lsu_bus_buffer.scala 378:88] + WrPtr1_m <= _T_1960 @[lsu_bus_buffer.scala 369:12] + wire buf_age : UInt<4>[4] @[lsu_bus_buffer.scala 374:21] + buf_age[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 375:11] + buf_age[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 375:11] + buf_age[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 375:11] + buf_age[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 375:11] + node _T_1961 = orr(buf_age[0]) @[lsu_bus_buffer.scala 377:58] + node _T_1962 = eq(_T_1961, UInt<1>("h00")) @[lsu_bus_buffer.scala 377:45] + node _T_1963 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 377:78] + node _T_1964 = and(_T_1962, _T_1963) @[lsu_bus_buffer.scala 377:63] + node _T_1965 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 377:90] + node _T_1966 = and(_T_1964, _T_1965) @[lsu_bus_buffer.scala 377:88] + node _T_1967 = orr(buf_age[1]) @[lsu_bus_buffer.scala 377:58] + node _T_1968 = eq(_T_1967, UInt<1>("h00")) @[lsu_bus_buffer.scala 377:45] + node _T_1969 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 377:78] + node _T_1970 = and(_T_1968, _T_1969) @[lsu_bus_buffer.scala 377:63] + node _T_1971 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 377:90] + node _T_1972 = and(_T_1970, _T_1971) @[lsu_bus_buffer.scala 377:88] + node _T_1973 = orr(buf_age[2]) @[lsu_bus_buffer.scala 377:58] + node _T_1974 = eq(_T_1973, UInt<1>("h00")) @[lsu_bus_buffer.scala 377:45] + node _T_1975 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 377:78] + node _T_1976 = and(_T_1974, _T_1975) @[lsu_bus_buffer.scala 377:63] + node _T_1977 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 377:90] + node _T_1978 = and(_T_1976, _T_1977) @[lsu_bus_buffer.scala 377:88] + node _T_1979 = orr(buf_age[3]) @[lsu_bus_buffer.scala 377:58] + node _T_1980 = eq(_T_1979, UInt<1>("h00")) @[lsu_bus_buffer.scala 377:45] + node _T_1981 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 377:78] + node _T_1982 = and(_T_1980, _T_1981) @[lsu_bus_buffer.scala 377:63] + node _T_1983 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 377:90] + node _T_1984 = and(_T_1982, _T_1983) @[lsu_bus_buffer.scala 377:88] node _T_1985 = cat(_T_1984, _T_1978) @[Cat.scala 29:58] node _T_1986 = cat(_T_1985, _T_1972) @[Cat.scala 29:58] node CmdPtr0Dec = cat(_T_1986, _T_1966) @[Cat.scala 29:58] - node _T_1987 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 379:62] - node _T_1988 = and(buf_age[0], _T_1987) @[lsu_bus_buffer.scala 379:59] - node _T_1989 = orr(_T_1988) @[lsu_bus_buffer.scala 379:76] - node _T_1990 = eq(_T_1989, UInt<1>("h00")) @[lsu_bus_buffer.scala 379:45] - node _T_1991 = bits(CmdPtr0Dec, 0, 0) @[lsu_bus_buffer.scala 379:94] - node _T_1992 = eq(_T_1991, UInt<1>("h00")) @[lsu_bus_buffer.scala 379:83] - node _T_1993 = and(_T_1990, _T_1992) @[lsu_bus_buffer.scala 379:81] - node _T_1994 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 379:113] - node _T_1995 = and(_T_1993, _T_1994) @[lsu_bus_buffer.scala 379:98] - node _T_1996 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 379:125] - node _T_1997 = and(_T_1995, _T_1996) @[lsu_bus_buffer.scala 379:123] - node _T_1998 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 379:62] - node _T_1999 = and(buf_age[1], _T_1998) @[lsu_bus_buffer.scala 379:59] - node _T_2000 = orr(_T_1999) @[lsu_bus_buffer.scala 379:76] - node _T_2001 = eq(_T_2000, UInt<1>("h00")) @[lsu_bus_buffer.scala 379:45] - node _T_2002 = bits(CmdPtr0Dec, 1, 1) @[lsu_bus_buffer.scala 379:94] - node _T_2003 = eq(_T_2002, UInt<1>("h00")) @[lsu_bus_buffer.scala 379:83] - node _T_2004 = and(_T_2001, _T_2003) @[lsu_bus_buffer.scala 379:81] - node _T_2005 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 379:113] - node _T_2006 = and(_T_2004, _T_2005) @[lsu_bus_buffer.scala 379:98] - node _T_2007 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 379:125] - node _T_2008 = and(_T_2006, _T_2007) @[lsu_bus_buffer.scala 379:123] - node _T_2009 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 379:62] - node _T_2010 = and(buf_age[2], _T_2009) @[lsu_bus_buffer.scala 379:59] - node _T_2011 = orr(_T_2010) @[lsu_bus_buffer.scala 379:76] - node _T_2012 = eq(_T_2011, UInt<1>("h00")) @[lsu_bus_buffer.scala 379:45] - node _T_2013 = bits(CmdPtr0Dec, 2, 2) @[lsu_bus_buffer.scala 379:94] - node _T_2014 = eq(_T_2013, UInt<1>("h00")) @[lsu_bus_buffer.scala 379:83] - node _T_2015 = and(_T_2012, _T_2014) @[lsu_bus_buffer.scala 379:81] - node _T_2016 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 379:113] - node _T_2017 = and(_T_2015, _T_2016) @[lsu_bus_buffer.scala 379:98] - node _T_2018 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 379:125] - node _T_2019 = and(_T_2017, _T_2018) @[lsu_bus_buffer.scala 379:123] - node _T_2020 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 379:62] - node _T_2021 = and(buf_age[3], _T_2020) @[lsu_bus_buffer.scala 379:59] - node _T_2022 = orr(_T_2021) @[lsu_bus_buffer.scala 379:76] - node _T_2023 = eq(_T_2022, UInt<1>("h00")) @[lsu_bus_buffer.scala 379:45] - node _T_2024 = bits(CmdPtr0Dec, 3, 3) @[lsu_bus_buffer.scala 379:94] - node _T_2025 = eq(_T_2024, UInt<1>("h00")) @[lsu_bus_buffer.scala 379:83] - node _T_2026 = and(_T_2023, _T_2025) @[lsu_bus_buffer.scala 379:81] - node _T_2027 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 379:113] - node _T_2028 = and(_T_2026, _T_2027) @[lsu_bus_buffer.scala 379:98] - node _T_2029 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 379:125] - node _T_2030 = and(_T_2028, _T_2029) @[lsu_bus_buffer.scala 379:123] + node _T_1987 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 378:62] + node _T_1988 = and(buf_age[0], _T_1987) @[lsu_bus_buffer.scala 378:59] + node _T_1989 = orr(_T_1988) @[lsu_bus_buffer.scala 378:76] + node _T_1990 = eq(_T_1989, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:45] + node _T_1991 = bits(CmdPtr0Dec, 0, 0) @[lsu_bus_buffer.scala 378:94] + node _T_1992 = eq(_T_1991, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:83] + node _T_1993 = and(_T_1990, _T_1992) @[lsu_bus_buffer.scala 378:81] + node _T_1994 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 378:113] + node _T_1995 = and(_T_1993, _T_1994) @[lsu_bus_buffer.scala 378:98] + node _T_1996 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 378:125] + node _T_1997 = and(_T_1995, _T_1996) @[lsu_bus_buffer.scala 378:123] + node _T_1998 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 378:62] + node _T_1999 = and(buf_age[1], _T_1998) @[lsu_bus_buffer.scala 378:59] + node _T_2000 = orr(_T_1999) @[lsu_bus_buffer.scala 378:76] + node _T_2001 = eq(_T_2000, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:45] + node _T_2002 = bits(CmdPtr0Dec, 1, 1) @[lsu_bus_buffer.scala 378:94] + node _T_2003 = eq(_T_2002, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:83] + node _T_2004 = and(_T_2001, _T_2003) @[lsu_bus_buffer.scala 378:81] + node _T_2005 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 378:113] + node _T_2006 = and(_T_2004, _T_2005) @[lsu_bus_buffer.scala 378:98] + node _T_2007 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 378:125] + node _T_2008 = and(_T_2006, _T_2007) @[lsu_bus_buffer.scala 378:123] + node _T_2009 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 378:62] + node _T_2010 = and(buf_age[2], _T_2009) @[lsu_bus_buffer.scala 378:59] + node _T_2011 = orr(_T_2010) @[lsu_bus_buffer.scala 378:76] + node _T_2012 = eq(_T_2011, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:45] + node _T_2013 = bits(CmdPtr0Dec, 2, 2) @[lsu_bus_buffer.scala 378:94] + node _T_2014 = eq(_T_2013, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:83] + node _T_2015 = and(_T_2012, _T_2014) @[lsu_bus_buffer.scala 378:81] + node _T_2016 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 378:113] + node _T_2017 = and(_T_2015, _T_2016) @[lsu_bus_buffer.scala 378:98] + node _T_2018 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 378:125] + node _T_2019 = and(_T_2017, _T_2018) @[lsu_bus_buffer.scala 378:123] + node _T_2020 = not(CmdPtr0Dec) @[lsu_bus_buffer.scala 378:62] + node _T_2021 = and(buf_age[3], _T_2020) @[lsu_bus_buffer.scala 378:59] + node _T_2022 = orr(_T_2021) @[lsu_bus_buffer.scala 378:76] + node _T_2023 = eq(_T_2022, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:45] + node _T_2024 = bits(CmdPtr0Dec, 3, 3) @[lsu_bus_buffer.scala 378:94] + node _T_2025 = eq(_T_2024, UInt<1>("h00")) @[lsu_bus_buffer.scala 378:83] + node _T_2026 = and(_T_2023, _T_2025) @[lsu_bus_buffer.scala 378:81] + node _T_2027 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 378:113] + node _T_2028 = and(_T_2026, _T_2027) @[lsu_bus_buffer.scala 378:98] + node _T_2029 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 378:125] + node _T_2030 = and(_T_2028, _T_2029) @[lsu_bus_buffer.scala 378:123] node _T_2031 = cat(_T_2030, _T_2019) @[Cat.scala 29:58] node _T_2032 = cat(_T_2031, _T_2008) @[Cat.scala 29:58] node CmdPtr1Dec = cat(_T_2032, _T_1997) @[Cat.scala 29:58] - wire buf_rsp_pickage : UInt<4>[4] @[lsu_bus_buffer.scala 380:29] - buf_rsp_pickage[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:19] - buf_rsp_pickage[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:19] - buf_rsp_pickage[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:19] - buf_rsp_pickage[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 381:19] - node _T_2033 = orr(buf_rsp_pickage[0]) @[lsu_bus_buffer.scala 382:65] - node _T_2034 = eq(_T_2033, UInt<1>("h00")) @[lsu_bus_buffer.scala 382:44] - node _T_2035 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 382:85] - node _T_2036 = and(_T_2034, _T_2035) @[lsu_bus_buffer.scala 382:70] - node _T_2037 = orr(buf_rsp_pickage[1]) @[lsu_bus_buffer.scala 382:65] - node _T_2038 = eq(_T_2037, UInt<1>("h00")) @[lsu_bus_buffer.scala 382:44] - node _T_2039 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 382:85] - node _T_2040 = and(_T_2038, _T_2039) @[lsu_bus_buffer.scala 382:70] - node _T_2041 = orr(buf_rsp_pickage[2]) @[lsu_bus_buffer.scala 382:65] - node _T_2042 = eq(_T_2041, UInt<1>("h00")) @[lsu_bus_buffer.scala 382:44] - node _T_2043 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 382:85] - node _T_2044 = and(_T_2042, _T_2043) @[lsu_bus_buffer.scala 382:70] - node _T_2045 = orr(buf_rsp_pickage[3]) @[lsu_bus_buffer.scala 382:65] - node _T_2046 = eq(_T_2045, UInt<1>("h00")) @[lsu_bus_buffer.scala 382:44] - node _T_2047 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 382:85] - node _T_2048 = and(_T_2046, _T_2047) @[lsu_bus_buffer.scala 382:70] + wire buf_rsp_pickage : UInt<4>[4] @[lsu_bus_buffer.scala 379:29] + buf_rsp_pickage[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 380:19] + buf_rsp_pickage[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 380:19] + buf_rsp_pickage[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 380:19] + buf_rsp_pickage[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 380:19] + node _T_2033 = orr(buf_rsp_pickage[0]) @[lsu_bus_buffer.scala 381:65] + node _T_2034 = eq(_T_2033, UInt<1>("h00")) @[lsu_bus_buffer.scala 381:44] + node _T_2035 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 381:85] + node _T_2036 = and(_T_2034, _T_2035) @[lsu_bus_buffer.scala 381:70] + node _T_2037 = orr(buf_rsp_pickage[1]) @[lsu_bus_buffer.scala 381:65] + node _T_2038 = eq(_T_2037, UInt<1>("h00")) @[lsu_bus_buffer.scala 381:44] + node _T_2039 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 381:85] + node _T_2040 = and(_T_2038, _T_2039) @[lsu_bus_buffer.scala 381:70] + node _T_2041 = orr(buf_rsp_pickage[2]) @[lsu_bus_buffer.scala 381:65] + node _T_2042 = eq(_T_2041, UInt<1>("h00")) @[lsu_bus_buffer.scala 381:44] + node _T_2043 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 381:85] + node _T_2044 = and(_T_2042, _T_2043) @[lsu_bus_buffer.scala 381:70] + node _T_2045 = orr(buf_rsp_pickage[3]) @[lsu_bus_buffer.scala 381:65] + node _T_2046 = eq(_T_2045, UInt<1>("h00")) @[lsu_bus_buffer.scala 381:44] + node _T_2047 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 381:85] + node _T_2048 = and(_T_2046, _T_2047) @[lsu_bus_buffer.scala 381:70] node _T_2049 = cat(_T_2048, _T_2044) @[Cat.scala 29:58] node _T_2050 = cat(_T_2049, _T_2040) @[Cat.scala 29:58] node RspPtrDec = cat(_T_2050, _T_2036) @[Cat.scala 29:58] - node _T_2051 = orr(CmdPtr0Dec) @[lsu_bus_buffer.scala 383:31] - found_cmdptr0 <= _T_2051 @[lsu_bus_buffer.scala 383:17] - node _T_2052 = orr(CmdPtr1Dec) @[lsu_bus_buffer.scala 384:31] - found_cmdptr1 <= _T_2052 @[lsu_bus_buffer.scala 384:17] + node _T_2051 = orr(CmdPtr0Dec) @[lsu_bus_buffer.scala 382:31] + found_cmdptr0 <= _T_2051 @[lsu_bus_buffer.scala 382:17] + node _T_2052 = orr(CmdPtr1Dec) @[lsu_bus_buffer.scala 383:31] + found_cmdptr1 <= _T_2052 @[lsu_bus_buffer.scala 383:17] wire RspPtr : UInt<2> RspPtr <= UInt<1>("h00") node _T_2053 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] node _T_2054 = cat(_T_2053, CmdPtr0Dec) @[Cat.scala 29:58] - node _T_2055 = bits(_T_2054, 4, 4) @[lsu_bus_buffer.scala 386:39] - node _T_2056 = bits(_T_2054, 5, 5) @[lsu_bus_buffer.scala 386:45] - node _T_2057 = or(_T_2055, _T_2056) @[lsu_bus_buffer.scala 386:42] - node _T_2058 = bits(_T_2054, 6, 6) @[lsu_bus_buffer.scala 386:51] - node _T_2059 = or(_T_2057, _T_2058) @[lsu_bus_buffer.scala 386:48] - node _T_2060 = bits(_T_2054, 7, 7) @[lsu_bus_buffer.scala 386:57] - node _T_2061 = or(_T_2059, _T_2060) @[lsu_bus_buffer.scala 386:54] - node _T_2062 = bits(_T_2054, 2, 2) @[lsu_bus_buffer.scala 386:64] - node _T_2063 = bits(_T_2054, 3, 3) @[lsu_bus_buffer.scala 386:70] - node _T_2064 = or(_T_2062, _T_2063) @[lsu_bus_buffer.scala 386:67] - node _T_2065 = bits(_T_2054, 6, 6) @[lsu_bus_buffer.scala 386:76] - node _T_2066 = or(_T_2064, _T_2065) @[lsu_bus_buffer.scala 386:73] - node _T_2067 = bits(_T_2054, 7, 7) @[lsu_bus_buffer.scala 386:82] - node _T_2068 = or(_T_2066, _T_2067) @[lsu_bus_buffer.scala 386:79] - node _T_2069 = bits(_T_2054, 1, 1) @[lsu_bus_buffer.scala 386:89] - node _T_2070 = bits(_T_2054, 3, 3) @[lsu_bus_buffer.scala 386:95] - node _T_2071 = or(_T_2069, _T_2070) @[lsu_bus_buffer.scala 386:92] - node _T_2072 = bits(_T_2054, 5, 5) @[lsu_bus_buffer.scala 386:101] - node _T_2073 = or(_T_2071, _T_2072) @[lsu_bus_buffer.scala 386:98] - node _T_2074 = bits(_T_2054, 7, 7) @[lsu_bus_buffer.scala 386:107] - node _T_2075 = or(_T_2073, _T_2074) @[lsu_bus_buffer.scala 386:104] + node _T_2055 = bits(_T_2054, 4, 4) @[lsu_bus_buffer.scala 385:39] + node _T_2056 = bits(_T_2054, 5, 5) @[lsu_bus_buffer.scala 385:45] + node _T_2057 = or(_T_2055, _T_2056) @[lsu_bus_buffer.scala 385:42] + node _T_2058 = bits(_T_2054, 6, 6) @[lsu_bus_buffer.scala 385:51] + node _T_2059 = or(_T_2057, _T_2058) @[lsu_bus_buffer.scala 385:48] + node _T_2060 = bits(_T_2054, 7, 7) @[lsu_bus_buffer.scala 385:57] + node _T_2061 = or(_T_2059, _T_2060) @[lsu_bus_buffer.scala 385:54] + node _T_2062 = bits(_T_2054, 2, 2) @[lsu_bus_buffer.scala 385:64] + node _T_2063 = bits(_T_2054, 3, 3) @[lsu_bus_buffer.scala 385:70] + node _T_2064 = or(_T_2062, _T_2063) @[lsu_bus_buffer.scala 385:67] + node _T_2065 = bits(_T_2054, 6, 6) @[lsu_bus_buffer.scala 385:76] + node _T_2066 = or(_T_2064, _T_2065) @[lsu_bus_buffer.scala 385:73] + node _T_2067 = bits(_T_2054, 7, 7) @[lsu_bus_buffer.scala 385:82] + node _T_2068 = or(_T_2066, _T_2067) @[lsu_bus_buffer.scala 385:79] + node _T_2069 = bits(_T_2054, 1, 1) @[lsu_bus_buffer.scala 385:89] + node _T_2070 = bits(_T_2054, 3, 3) @[lsu_bus_buffer.scala 385:95] + node _T_2071 = or(_T_2069, _T_2070) @[lsu_bus_buffer.scala 385:92] + node _T_2072 = bits(_T_2054, 5, 5) @[lsu_bus_buffer.scala 385:101] + node _T_2073 = or(_T_2071, _T_2072) @[lsu_bus_buffer.scala 385:98] + node _T_2074 = bits(_T_2054, 7, 7) @[lsu_bus_buffer.scala 385:107] + node _T_2075 = or(_T_2073, _T_2074) @[lsu_bus_buffer.scala 385:104] node _T_2076 = cat(_T_2061, _T_2068) @[Cat.scala 29:58] node _T_2077 = cat(_T_2076, _T_2075) @[Cat.scala 29:58] - CmdPtr0 <= _T_2077 @[lsu_bus_buffer.scala 391:11] + CmdPtr0 <= _T_2077 @[lsu_bus_buffer.scala 390:11] node _T_2078 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] node _T_2079 = cat(_T_2078, CmdPtr1Dec) @[Cat.scala 29:58] - node _T_2080 = bits(_T_2079, 4, 4) @[lsu_bus_buffer.scala 386:39] - node _T_2081 = bits(_T_2079, 5, 5) @[lsu_bus_buffer.scala 386:45] - node _T_2082 = or(_T_2080, _T_2081) @[lsu_bus_buffer.scala 386:42] - node _T_2083 = bits(_T_2079, 6, 6) @[lsu_bus_buffer.scala 386:51] - node _T_2084 = or(_T_2082, _T_2083) @[lsu_bus_buffer.scala 386:48] - node _T_2085 = bits(_T_2079, 7, 7) @[lsu_bus_buffer.scala 386:57] - node _T_2086 = or(_T_2084, _T_2085) @[lsu_bus_buffer.scala 386:54] - node _T_2087 = bits(_T_2079, 2, 2) @[lsu_bus_buffer.scala 386:64] - node _T_2088 = bits(_T_2079, 3, 3) @[lsu_bus_buffer.scala 386:70] - node _T_2089 = or(_T_2087, _T_2088) @[lsu_bus_buffer.scala 386:67] - node _T_2090 = bits(_T_2079, 6, 6) @[lsu_bus_buffer.scala 386:76] - node _T_2091 = or(_T_2089, _T_2090) @[lsu_bus_buffer.scala 386:73] - node _T_2092 = bits(_T_2079, 7, 7) @[lsu_bus_buffer.scala 386:82] - node _T_2093 = or(_T_2091, _T_2092) @[lsu_bus_buffer.scala 386:79] - node _T_2094 = bits(_T_2079, 1, 1) @[lsu_bus_buffer.scala 386:89] - node _T_2095 = bits(_T_2079, 3, 3) @[lsu_bus_buffer.scala 386:95] - node _T_2096 = or(_T_2094, _T_2095) @[lsu_bus_buffer.scala 386:92] - node _T_2097 = bits(_T_2079, 5, 5) @[lsu_bus_buffer.scala 386:101] - node _T_2098 = or(_T_2096, _T_2097) @[lsu_bus_buffer.scala 386:98] - node _T_2099 = bits(_T_2079, 7, 7) @[lsu_bus_buffer.scala 386:107] - node _T_2100 = or(_T_2098, _T_2099) @[lsu_bus_buffer.scala 386:104] + node _T_2080 = bits(_T_2079, 4, 4) @[lsu_bus_buffer.scala 385:39] + node _T_2081 = bits(_T_2079, 5, 5) @[lsu_bus_buffer.scala 385:45] + node _T_2082 = or(_T_2080, _T_2081) @[lsu_bus_buffer.scala 385:42] + node _T_2083 = bits(_T_2079, 6, 6) @[lsu_bus_buffer.scala 385:51] + node _T_2084 = or(_T_2082, _T_2083) @[lsu_bus_buffer.scala 385:48] + node _T_2085 = bits(_T_2079, 7, 7) @[lsu_bus_buffer.scala 385:57] + node _T_2086 = or(_T_2084, _T_2085) @[lsu_bus_buffer.scala 385:54] + node _T_2087 = bits(_T_2079, 2, 2) @[lsu_bus_buffer.scala 385:64] + node _T_2088 = bits(_T_2079, 3, 3) @[lsu_bus_buffer.scala 385:70] + node _T_2089 = or(_T_2087, _T_2088) @[lsu_bus_buffer.scala 385:67] + node _T_2090 = bits(_T_2079, 6, 6) @[lsu_bus_buffer.scala 385:76] + node _T_2091 = or(_T_2089, _T_2090) @[lsu_bus_buffer.scala 385:73] + node _T_2092 = bits(_T_2079, 7, 7) @[lsu_bus_buffer.scala 385:82] + node _T_2093 = or(_T_2091, _T_2092) @[lsu_bus_buffer.scala 385:79] + node _T_2094 = bits(_T_2079, 1, 1) @[lsu_bus_buffer.scala 385:89] + node _T_2095 = bits(_T_2079, 3, 3) @[lsu_bus_buffer.scala 385:95] + node _T_2096 = or(_T_2094, _T_2095) @[lsu_bus_buffer.scala 385:92] + node _T_2097 = bits(_T_2079, 5, 5) @[lsu_bus_buffer.scala 385:101] + node _T_2098 = or(_T_2096, _T_2097) @[lsu_bus_buffer.scala 385:98] + node _T_2099 = bits(_T_2079, 7, 7) @[lsu_bus_buffer.scala 385:107] + node _T_2100 = or(_T_2098, _T_2099) @[lsu_bus_buffer.scala 385:104] node _T_2101 = cat(_T_2086, _T_2093) @[Cat.scala 29:58] node _T_2102 = cat(_T_2101, _T_2100) @[Cat.scala 29:58] - CmdPtr1 <= _T_2102 @[lsu_bus_buffer.scala 393:11] + CmdPtr1 <= _T_2102 @[lsu_bus_buffer.scala 392:11] node _T_2103 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] node _T_2104 = cat(_T_2103, RspPtrDec) @[Cat.scala 29:58] - node _T_2105 = bits(_T_2104, 4, 4) @[lsu_bus_buffer.scala 386:39] - node _T_2106 = bits(_T_2104, 5, 5) @[lsu_bus_buffer.scala 386:45] - node _T_2107 = or(_T_2105, _T_2106) @[lsu_bus_buffer.scala 386:42] - node _T_2108 = bits(_T_2104, 6, 6) @[lsu_bus_buffer.scala 386:51] - node _T_2109 = or(_T_2107, _T_2108) @[lsu_bus_buffer.scala 386:48] - node _T_2110 = bits(_T_2104, 7, 7) @[lsu_bus_buffer.scala 386:57] - node _T_2111 = or(_T_2109, _T_2110) @[lsu_bus_buffer.scala 386:54] - node _T_2112 = bits(_T_2104, 2, 2) @[lsu_bus_buffer.scala 386:64] - node _T_2113 = bits(_T_2104, 3, 3) @[lsu_bus_buffer.scala 386:70] - node _T_2114 = or(_T_2112, _T_2113) @[lsu_bus_buffer.scala 386:67] - node _T_2115 = bits(_T_2104, 6, 6) @[lsu_bus_buffer.scala 386:76] - node _T_2116 = or(_T_2114, _T_2115) @[lsu_bus_buffer.scala 386:73] - node _T_2117 = bits(_T_2104, 7, 7) @[lsu_bus_buffer.scala 386:82] - node _T_2118 = or(_T_2116, _T_2117) @[lsu_bus_buffer.scala 386:79] - node _T_2119 = bits(_T_2104, 1, 1) @[lsu_bus_buffer.scala 386:89] - node _T_2120 = bits(_T_2104, 3, 3) @[lsu_bus_buffer.scala 386:95] - node _T_2121 = or(_T_2119, _T_2120) @[lsu_bus_buffer.scala 386:92] - node _T_2122 = bits(_T_2104, 5, 5) @[lsu_bus_buffer.scala 386:101] - node _T_2123 = or(_T_2121, _T_2122) @[lsu_bus_buffer.scala 386:98] - node _T_2124 = bits(_T_2104, 7, 7) @[lsu_bus_buffer.scala 386:107] - node _T_2125 = or(_T_2123, _T_2124) @[lsu_bus_buffer.scala 386:104] + node _T_2105 = bits(_T_2104, 4, 4) @[lsu_bus_buffer.scala 385:39] + node _T_2106 = bits(_T_2104, 5, 5) @[lsu_bus_buffer.scala 385:45] + node _T_2107 = or(_T_2105, _T_2106) @[lsu_bus_buffer.scala 385:42] + node _T_2108 = bits(_T_2104, 6, 6) @[lsu_bus_buffer.scala 385:51] + node _T_2109 = or(_T_2107, _T_2108) @[lsu_bus_buffer.scala 385:48] + node _T_2110 = bits(_T_2104, 7, 7) @[lsu_bus_buffer.scala 385:57] + node _T_2111 = or(_T_2109, _T_2110) @[lsu_bus_buffer.scala 385:54] + node _T_2112 = bits(_T_2104, 2, 2) @[lsu_bus_buffer.scala 385:64] + node _T_2113 = bits(_T_2104, 3, 3) @[lsu_bus_buffer.scala 385:70] + node _T_2114 = or(_T_2112, _T_2113) @[lsu_bus_buffer.scala 385:67] + node _T_2115 = bits(_T_2104, 6, 6) @[lsu_bus_buffer.scala 385:76] + node _T_2116 = or(_T_2114, _T_2115) @[lsu_bus_buffer.scala 385:73] + node _T_2117 = bits(_T_2104, 7, 7) @[lsu_bus_buffer.scala 385:82] + node _T_2118 = or(_T_2116, _T_2117) @[lsu_bus_buffer.scala 385:79] + node _T_2119 = bits(_T_2104, 1, 1) @[lsu_bus_buffer.scala 385:89] + node _T_2120 = bits(_T_2104, 3, 3) @[lsu_bus_buffer.scala 385:95] + node _T_2121 = or(_T_2119, _T_2120) @[lsu_bus_buffer.scala 385:92] + node _T_2122 = bits(_T_2104, 5, 5) @[lsu_bus_buffer.scala 385:101] + node _T_2123 = or(_T_2121, _T_2122) @[lsu_bus_buffer.scala 385:98] + node _T_2124 = bits(_T_2104, 7, 7) @[lsu_bus_buffer.scala 385:107] + node _T_2125 = or(_T_2123, _T_2124) @[lsu_bus_buffer.scala 385:104] node _T_2126 = cat(_T_2111, _T_2118) @[Cat.scala 29:58] node _T_2127 = cat(_T_2126, _T_2125) @[Cat.scala 29:58] - RspPtr <= _T_2127 @[lsu_bus_buffer.scala 394:10] - wire buf_state_en : UInt<1>[4] @[lsu_bus_buffer.scala 395:26] - buf_state_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 396:16] - buf_state_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 396:16] - buf_state_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 396:16] - buf_state_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 396:16] - wire buf_rspageQ : UInt<4>[4] @[lsu_bus_buffer.scala 397:25] - buf_rspageQ[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 398:15] - buf_rspageQ[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 398:15] - buf_rspageQ[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 398:15] - buf_rspageQ[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 398:15] - wire buf_rspage_set : UInt<4>[4] @[lsu_bus_buffer.scala 399:28] - buf_rspage_set[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 400:18] - buf_rspage_set[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 400:18] - buf_rspage_set[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 400:18] - buf_rspage_set[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 400:18] - wire buf_rspage_in : UInt<4>[4] @[lsu_bus_buffer.scala 401:27] - buf_rspage_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 402:17] - buf_rspage_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 402:17] - buf_rspage_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 402:17] - buf_rspage_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 402:17] - wire buf_rspage : UInt<4>[4] @[lsu_bus_buffer.scala 403:24] - buf_rspage[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 404:14] - buf_rspage[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 404:14] - buf_rspage[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 404:14] - buf_rspage[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 404:14] - node _T_2128 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] - node _T_2129 = and(_T_2128, buf_state_en[0]) @[lsu_bus_buffer.scala 406:94] - node _T_2130 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] - node _T_2131 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] - node _T_2132 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] - node _T_2133 = and(_T_2131, _T_2132) @[lsu_bus_buffer.scala 407:57] - node _T_2134 = or(_T_2130, _T_2133) @[lsu_bus_buffer.scala 407:31] - node _T_2135 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] - node _T_2136 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] - node _T_2137 = and(_T_2135, _T_2136) @[lsu_bus_buffer.scala 408:41] - node _T_2138 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:83] - node _T_2139 = and(_T_2137, _T_2138) @[lsu_bus_buffer.scala 408:71] - node _T_2140 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:104] - node _T_2141 = and(_T_2139, _T_2140) @[lsu_bus_buffer.scala 408:92] - node _T_2142 = or(_T_2134, _T_2141) @[lsu_bus_buffer.scala 407:86] - node _T_2143 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] - node _T_2144 = and(_T_2143, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] - node _T_2145 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 409:64] - node _T_2146 = and(_T_2144, _T_2145) @[lsu_bus_buffer.scala 409:52] - node _T_2147 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 409:85] - node _T_2148 = and(_T_2146, _T_2147) @[lsu_bus_buffer.scala 409:73] - node _T_2149 = or(_T_2142, _T_2148) @[lsu_bus_buffer.scala 408:114] - node _T_2150 = and(_T_2129, _T_2149) @[lsu_bus_buffer.scala 406:113] - node _T_2151 = bits(buf_age[0], 0, 0) @[lsu_bus_buffer.scala 409:109] - node _T_2152 = or(_T_2150, _T_2151) @[lsu_bus_buffer.scala 409:97] - node _T_2153 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] - node _T_2154 = and(_T_2153, buf_state_en[0]) @[lsu_bus_buffer.scala 406:94] - node _T_2155 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] - node _T_2156 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] - node _T_2157 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] - node _T_2158 = and(_T_2156, _T_2157) @[lsu_bus_buffer.scala 407:57] - node _T_2159 = or(_T_2155, _T_2158) @[lsu_bus_buffer.scala 407:31] - node _T_2160 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] - node _T_2161 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] - node _T_2162 = and(_T_2160, _T_2161) @[lsu_bus_buffer.scala 408:41] - node _T_2163 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:83] - node _T_2164 = and(_T_2162, _T_2163) @[lsu_bus_buffer.scala 408:71] - node _T_2165 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:104] - node _T_2166 = and(_T_2164, _T_2165) @[lsu_bus_buffer.scala 408:92] - node _T_2167 = or(_T_2159, _T_2166) @[lsu_bus_buffer.scala 407:86] - node _T_2168 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] - node _T_2169 = and(_T_2168, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] - node _T_2170 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 409:64] - node _T_2171 = and(_T_2169, _T_2170) @[lsu_bus_buffer.scala 409:52] - node _T_2172 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 409:85] - node _T_2173 = and(_T_2171, _T_2172) @[lsu_bus_buffer.scala 409:73] - node _T_2174 = or(_T_2167, _T_2173) @[lsu_bus_buffer.scala 408:114] - node _T_2175 = and(_T_2154, _T_2174) @[lsu_bus_buffer.scala 406:113] - node _T_2176 = bits(buf_age[0], 1, 1) @[lsu_bus_buffer.scala 409:109] - node _T_2177 = or(_T_2175, _T_2176) @[lsu_bus_buffer.scala 409:97] - node _T_2178 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] - node _T_2179 = and(_T_2178, buf_state_en[0]) @[lsu_bus_buffer.scala 406:94] - node _T_2180 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] - node _T_2181 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] - node _T_2182 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] - node _T_2183 = and(_T_2181, _T_2182) @[lsu_bus_buffer.scala 407:57] - node _T_2184 = or(_T_2180, _T_2183) @[lsu_bus_buffer.scala 407:31] - node _T_2185 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] - node _T_2186 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] - node _T_2187 = and(_T_2185, _T_2186) @[lsu_bus_buffer.scala 408:41] - node _T_2188 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:83] - node _T_2189 = and(_T_2187, _T_2188) @[lsu_bus_buffer.scala 408:71] - node _T_2190 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:104] - node _T_2191 = and(_T_2189, _T_2190) @[lsu_bus_buffer.scala 408:92] - node _T_2192 = or(_T_2184, _T_2191) @[lsu_bus_buffer.scala 407:86] - node _T_2193 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] - node _T_2194 = and(_T_2193, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] - node _T_2195 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 409:64] - node _T_2196 = and(_T_2194, _T_2195) @[lsu_bus_buffer.scala 409:52] - node _T_2197 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 409:85] - node _T_2198 = and(_T_2196, _T_2197) @[lsu_bus_buffer.scala 409:73] - node _T_2199 = or(_T_2192, _T_2198) @[lsu_bus_buffer.scala 408:114] - node _T_2200 = and(_T_2179, _T_2199) @[lsu_bus_buffer.scala 406:113] - node _T_2201 = bits(buf_age[0], 2, 2) @[lsu_bus_buffer.scala 409:109] - node _T_2202 = or(_T_2200, _T_2201) @[lsu_bus_buffer.scala 409:97] - node _T_2203 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] - node _T_2204 = and(_T_2203, buf_state_en[0]) @[lsu_bus_buffer.scala 406:94] - node _T_2205 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] - node _T_2206 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] - node _T_2207 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] - node _T_2208 = and(_T_2206, _T_2207) @[lsu_bus_buffer.scala 407:57] - node _T_2209 = or(_T_2205, _T_2208) @[lsu_bus_buffer.scala 407:31] - node _T_2210 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] - node _T_2211 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] - node _T_2212 = and(_T_2210, _T_2211) @[lsu_bus_buffer.scala 408:41] - node _T_2213 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:83] - node _T_2214 = and(_T_2212, _T_2213) @[lsu_bus_buffer.scala 408:71] - node _T_2215 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:104] - node _T_2216 = and(_T_2214, _T_2215) @[lsu_bus_buffer.scala 408:92] - node _T_2217 = or(_T_2209, _T_2216) @[lsu_bus_buffer.scala 407:86] - node _T_2218 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] - node _T_2219 = and(_T_2218, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] - node _T_2220 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 409:64] - node _T_2221 = and(_T_2219, _T_2220) @[lsu_bus_buffer.scala 409:52] - node _T_2222 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 409:85] - node _T_2223 = and(_T_2221, _T_2222) @[lsu_bus_buffer.scala 409:73] - node _T_2224 = or(_T_2217, _T_2223) @[lsu_bus_buffer.scala 408:114] - node _T_2225 = and(_T_2204, _T_2224) @[lsu_bus_buffer.scala 406:113] - node _T_2226 = bits(buf_age[0], 3, 3) @[lsu_bus_buffer.scala 409:109] - node _T_2227 = or(_T_2225, _T_2226) @[lsu_bus_buffer.scala 409:97] + RspPtr <= _T_2127 @[lsu_bus_buffer.scala 393:10] + wire buf_state_en : UInt<1>[4] @[lsu_bus_buffer.scala 394:26] + buf_state_en[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 395:16] + buf_state_en[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 395:16] + buf_state_en[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 395:16] + buf_state_en[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 395:16] + wire buf_rspageQ : UInt<4>[4] @[lsu_bus_buffer.scala 396:25] + buf_rspageQ[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 397:15] + buf_rspageQ[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 397:15] + buf_rspageQ[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 397:15] + buf_rspageQ[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 397:15] + wire buf_rspage_set : UInt<4>[4] @[lsu_bus_buffer.scala 398:28] + buf_rspage_set[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 399:18] + buf_rspage_set[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 399:18] + buf_rspage_set[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 399:18] + buf_rspage_set[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 399:18] + wire buf_rspage_in : UInt<4>[4] @[lsu_bus_buffer.scala 400:27] + buf_rspage_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:17] + buf_rspage_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:17] + buf_rspage_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:17] + buf_rspage_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 401:17] + wire buf_rspage : UInt<4>[4] @[lsu_bus_buffer.scala 402:24] + buf_rspage[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:14] + buf_rspage[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:14] + buf_rspage[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:14] + buf_rspage[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 403:14] + node _T_2128 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2129 = and(_T_2128, buf_state_en[0]) @[lsu_bus_buffer.scala 405:94] + node _T_2130 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2131 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2132 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2133 = and(_T_2131, _T_2132) @[lsu_bus_buffer.scala 406:57] + node _T_2134 = or(_T_2130, _T_2133) @[lsu_bus_buffer.scala 406:31] + node _T_2135 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2136 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2137 = and(_T_2135, _T_2136) @[lsu_bus_buffer.scala 407:41] + node _T_2138 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 407:83] + node _T_2139 = and(_T_2137, _T_2138) @[lsu_bus_buffer.scala 407:71] + node _T_2140 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 407:104] + node _T_2141 = and(_T_2139, _T_2140) @[lsu_bus_buffer.scala 407:92] + node _T_2142 = or(_T_2134, _T_2141) @[lsu_bus_buffer.scala 406:86] + node _T_2143 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2144 = and(_T_2143, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2145 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:64] + node _T_2146 = and(_T_2144, _T_2145) @[lsu_bus_buffer.scala 408:52] + node _T_2147 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:85] + node _T_2148 = and(_T_2146, _T_2147) @[lsu_bus_buffer.scala 408:73] + node _T_2149 = or(_T_2142, _T_2148) @[lsu_bus_buffer.scala 407:114] + node _T_2150 = and(_T_2129, _T_2149) @[lsu_bus_buffer.scala 405:113] + node _T_2151 = bits(buf_age[0], 0, 0) @[lsu_bus_buffer.scala 408:109] + node _T_2152 = or(_T_2150, _T_2151) @[lsu_bus_buffer.scala 408:97] + node _T_2153 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2154 = and(_T_2153, buf_state_en[0]) @[lsu_bus_buffer.scala 405:94] + node _T_2155 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2156 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2157 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2158 = and(_T_2156, _T_2157) @[lsu_bus_buffer.scala 406:57] + node _T_2159 = or(_T_2155, _T_2158) @[lsu_bus_buffer.scala 406:31] + node _T_2160 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2161 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2162 = and(_T_2160, _T_2161) @[lsu_bus_buffer.scala 407:41] + node _T_2163 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 407:83] + node _T_2164 = and(_T_2162, _T_2163) @[lsu_bus_buffer.scala 407:71] + node _T_2165 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 407:104] + node _T_2166 = and(_T_2164, _T_2165) @[lsu_bus_buffer.scala 407:92] + node _T_2167 = or(_T_2159, _T_2166) @[lsu_bus_buffer.scala 406:86] + node _T_2168 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2169 = and(_T_2168, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2170 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:64] + node _T_2171 = and(_T_2169, _T_2170) @[lsu_bus_buffer.scala 408:52] + node _T_2172 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:85] + node _T_2173 = and(_T_2171, _T_2172) @[lsu_bus_buffer.scala 408:73] + node _T_2174 = or(_T_2167, _T_2173) @[lsu_bus_buffer.scala 407:114] + node _T_2175 = and(_T_2154, _T_2174) @[lsu_bus_buffer.scala 405:113] + node _T_2176 = bits(buf_age[0], 1, 1) @[lsu_bus_buffer.scala 408:109] + node _T_2177 = or(_T_2175, _T_2176) @[lsu_bus_buffer.scala 408:97] + node _T_2178 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2179 = and(_T_2178, buf_state_en[0]) @[lsu_bus_buffer.scala 405:94] + node _T_2180 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2181 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2182 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2183 = and(_T_2181, _T_2182) @[lsu_bus_buffer.scala 406:57] + node _T_2184 = or(_T_2180, _T_2183) @[lsu_bus_buffer.scala 406:31] + node _T_2185 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2186 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2187 = and(_T_2185, _T_2186) @[lsu_bus_buffer.scala 407:41] + node _T_2188 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 407:83] + node _T_2189 = and(_T_2187, _T_2188) @[lsu_bus_buffer.scala 407:71] + node _T_2190 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 407:104] + node _T_2191 = and(_T_2189, _T_2190) @[lsu_bus_buffer.scala 407:92] + node _T_2192 = or(_T_2184, _T_2191) @[lsu_bus_buffer.scala 406:86] + node _T_2193 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2194 = and(_T_2193, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2195 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:64] + node _T_2196 = and(_T_2194, _T_2195) @[lsu_bus_buffer.scala 408:52] + node _T_2197 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:85] + node _T_2198 = and(_T_2196, _T_2197) @[lsu_bus_buffer.scala 408:73] + node _T_2199 = or(_T_2192, _T_2198) @[lsu_bus_buffer.scala 407:114] + node _T_2200 = and(_T_2179, _T_2199) @[lsu_bus_buffer.scala 405:113] + node _T_2201 = bits(buf_age[0], 2, 2) @[lsu_bus_buffer.scala 408:109] + node _T_2202 = or(_T_2200, _T_2201) @[lsu_bus_buffer.scala 408:97] + node _T_2203 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2204 = and(_T_2203, buf_state_en[0]) @[lsu_bus_buffer.scala 405:94] + node _T_2205 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2206 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2207 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2208 = and(_T_2206, _T_2207) @[lsu_bus_buffer.scala 406:57] + node _T_2209 = or(_T_2205, _T_2208) @[lsu_bus_buffer.scala 406:31] + node _T_2210 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2211 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2212 = and(_T_2210, _T_2211) @[lsu_bus_buffer.scala 407:41] + node _T_2213 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 407:83] + node _T_2214 = and(_T_2212, _T_2213) @[lsu_bus_buffer.scala 407:71] + node _T_2215 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 407:104] + node _T_2216 = and(_T_2214, _T_2215) @[lsu_bus_buffer.scala 407:92] + node _T_2217 = or(_T_2209, _T_2216) @[lsu_bus_buffer.scala 406:86] + node _T_2218 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2219 = and(_T_2218, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2220 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:64] + node _T_2221 = and(_T_2219, _T_2220) @[lsu_bus_buffer.scala 408:52] + node _T_2222 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:85] + node _T_2223 = and(_T_2221, _T_2222) @[lsu_bus_buffer.scala 408:73] + node _T_2224 = or(_T_2217, _T_2223) @[lsu_bus_buffer.scala 407:114] + node _T_2225 = and(_T_2204, _T_2224) @[lsu_bus_buffer.scala 405:113] + node _T_2226 = bits(buf_age[0], 3, 3) @[lsu_bus_buffer.scala 408:109] + node _T_2227 = or(_T_2225, _T_2226) @[lsu_bus_buffer.scala 408:97] node _T_2228 = cat(_T_2227, _T_2202) @[Cat.scala 29:58] node _T_2229 = cat(_T_2228, _T_2177) @[Cat.scala 29:58] node buf_age_in_0 = cat(_T_2229, _T_2152) @[Cat.scala 29:58] - node _T_2230 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] - node _T_2231 = and(_T_2230, buf_state_en[1]) @[lsu_bus_buffer.scala 406:94] - node _T_2232 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] - node _T_2233 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] - node _T_2234 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] - node _T_2235 = and(_T_2233, _T_2234) @[lsu_bus_buffer.scala 407:57] - node _T_2236 = or(_T_2232, _T_2235) @[lsu_bus_buffer.scala 407:31] - node _T_2237 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] - node _T_2238 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] - node _T_2239 = and(_T_2237, _T_2238) @[lsu_bus_buffer.scala 408:41] - node _T_2240 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:83] - node _T_2241 = and(_T_2239, _T_2240) @[lsu_bus_buffer.scala 408:71] - node _T_2242 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:104] - node _T_2243 = and(_T_2241, _T_2242) @[lsu_bus_buffer.scala 408:92] - node _T_2244 = or(_T_2236, _T_2243) @[lsu_bus_buffer.scala 407:86] - node _T_2245 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] - node _T_2246 = and(_T_2245, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] - node _T_2247 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 409:64] - node _T_2248 = and(_T_2246, _T_2247) @[lsu_bus_buffer.scala 409:52] - node _T_2249 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 409:85] - node _T_2250 = and(_T_2248, _T_2249) @[lsu_bus_buffer.scala 409:73] - node _T_2251 = or(_T_2244, _T_2250) @[lsu_bus_buffer.scala 408:114] - node _T_2252 = and(_T_2231, _T_2251) @[lsu_bus_buffer.scala 406:113] - node _T_2253 = bits(buf_age[1], 0, 0) @[lsu_bus_buffer.scala 409:109] - node _T_2254 = or(_T_2252, _T_2253) @[lsu_bus_buffer.scala 409:97] - node _T_2255 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] - node _T_2256 = and(_T_2255, buf_state_en[1]) @[lsu_bus_buffer.scala 406:94] - node _T_2257 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] - node _T_2258 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] - node _T_2259 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] - node _T_2260 = and(_T_2258, _T_2259) @[lsu_bus_buffer.scala 407:57] - node _T_2261 = or(_T_2257, _T_2260) @[lsu_bus_buffer.scala 407:31] - node _T_2262 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] - node _T_2263 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] - node _T_2264 = and(_T_2262, _T_2263) @[lsu_bus_buffer.scala 408:41] - node _T_2265 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:83] - node _T_2266 = and(_T_2264, _T_2265) @[lsu_bus_buffer.scala 408:71] - node _T_2267 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:104] - node _T_2268 = and(_T_2266, _T_2267) @[lsu_bus_buffer.scala 408:92] - node _T_2269 = or(_T_2261, _T_2268) @[lsu_bus_buffer.scala 407:86] - node _T_2270 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] - node _T_2271 = and(_T_2270, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] - node _T_2272 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 409:64] - node _T_2273 = and(_T_2271, _T_2272) @[lsu_bus_buffer.scala 409:52] - node _T_2274 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 409:85] - node _T_2275 = and(_T_2273, _T_2274) @[lsu_bus_buffer.scala 409:73] - node _T_2276 = or(_T_2269, _T_2275) @[lsu_bus_buffer.scala 408:114] - node _T_2277 = and(_T_2256, _T_2276) @[lsu_bus_buffer.scala 406:113] - node _T_2278 = bits(buf_age[1], 1, 1) @[lsu_bus_buffer.scala 409:109] - node _T_2279 = or(_T_2277, _T_2278) @[lsu_bus_buffer.scala 409:97] - node _T_2280 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] - node _T_2281 = and(_T_2280, buf_state_en[1]) @[lsu_bus_buffer.scala 406:94] - node _T_2282 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] - node _T_2283 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] - node _T_2284 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] - node _T_2285 = and(_T_2283, _T_2284) @[lsu_bus_buffer.scala 407:57] - node _T_2286 = or(_T_2282, _T_2285) @[lsu_bus_buffer.scala 407:31] - node _T_2287 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] - node _T_2288 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] - node _T_2289 = and(_T_2287, _T_2288) @[lsu_bus_buffer.scala 408:41] - node _T_2290 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:83] - node _T_2291 = and(_T_2289, _T_2290) @[lsu_bus_buffer.scala 408:71] - node _T_2292 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:104] - node _T_2293 = and(_T_2291, _T_2292) @[lsu_bus_buffer.scala 408:92] - node _T_2294 = or(_T_2286, _T_2293) @[lsu_bus_buffer.scala 407:86] - node _T_2295 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] - node _T_2296 = and(_T_2295, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] - node _T_2297 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 409:64] - node _T_2298 = and(_T_2296, _T_2297) @[lsu_bus_buffer.scala 409:52] - node _T_2299 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 409:85] - node _T_2300 = and(_T_2298, _T_2299) @[lsu_bus_buffer.scala 409:73] - node _T_2301 = or(_T_2294, _T_2300) @[lsu_bus_buffer.scala 408:114] - node _T_2302 = and(_T_2281, _T_2301) @[lsu_bus_buffer.scala 406:113] - node _T_2303 = bits(buf_age[1], 2, 2) @[lsu_bus_buffer.scala 409:109] - node _T_2304 = or(_T_2302, _T_2303) @[lsu_bus_buffer.scala 409:97] - node _T_2305 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] - node _T_2306 = and(_T_2305, buf_state_en[1]) @[lsu_bus_buffer.scala 406:94] - node _T_2307 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] - node _T_2308 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] - node _T_2309 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] - node _T_2310 = and(_T_2308, _T_2309) @[lsu_bus_buffer.scala 407:57] - node _T_2311 = or(_T_2307, _T_2310) @[lsu_bus_buffer.scala 407:31] - node _T_2312 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] - node _T_2313 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] - node _T_2314 = and(_T_2312, _T_2313) @[lsu_bus_buffer.scala 408:41] - node _T_2315 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:83] - node _T_2316 = and(_T_2314, _T_2315) @[lsu_bus_buffer.scala 408:71] - node _T_2317 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:104] - node _T_2318 = and(_T_2316, _T_2317) @[lsu_bus_buffer.scala 408:92] - node _T_2319 = or(_T_2311, _T_2318) @[lsu_bus_buffer.scala 407:86] - node _T_2320 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] - node _T_2321 = and(_T_2320, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] - node _T_2322 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 409:64] - node _T_2323 = and(_T_2321, _T_2322) @[lsu_bus_buffer.scala 409:52] - node _T_2324 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 409:85] - node _T_2325 = and(_T_2323, _T_2324) @[lsu_bus_buffer.scala 409:73] - node _T_2326 = or(_T_2319, _T_2325) @[lsu_bus_buffer.scala 408:114] - node _T_2327 = and(_T_2306, _T_2326) @[lsu_bus_buffer.scala 406:113] - node _T_2328 = bits(buf_age[1], 3, 3) @[lsu_bus_buffer.scala 409:109] - node _T_2329 = or(_T_2327, _T_2328) @[lsu_bus_buffer.scala 409:97] + node _T_2230 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2231 = and(_T_2230, buf_state_en[1]) @[lsu_bus_buffer.scala 405:94] + node _T_2232 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2233 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2234 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2235 = and(_T_2233, _T_2234) @[lsu_bus_buffer.scala 406:57] + node _T_2236 = or(_T_2232, _T_2235) @[lsu_bus_buffer.scala 406:31] + node _T_2237 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2238 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2239 = and(_T_2237, _T_2238) @[lsu_bus_buffer.scala 407:41] + node _T_2240 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 407:83] + node _T_2241 = and(_T_2239, _T_2240) @[lsu_bus_buffer.scala 407:71] + node _T_2242 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 407:104] + node _T_2243 = and(_T_2241, _T_2242) @[lsu_bus_buffer.scala 407:92] + node _T_2244 = or(_T_2236, _T_2243) @[lsu_bus_buffer.scala 406:86] + node _T_2245 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2246 = and(_T_2245, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2247 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:64] + node _T_2248 = and(_T_2246, _T_2247) @[lsu_bus_buffer.scala 408:52] + node _T_2249 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:85] + node _T_2250 = and(_T_2248, _T_2249) @[lsu_bus_buffer.scala 408:73] + node _T_2251 = or(_T_2244, _T_2250) @[lsu_bus_buffer.scala 407:114] + node _T_2252 = and(_T_2231, _T_2251) @[lsu_bus_buffer.scala 405:113] + node _T_2253 = bits(buf_age[1], 0, 0) @[lsu_bus_buffer.scala 408:109] + node _T_2254 = or(_T_2252, _T_2253) @[lsu_bus_buffer.scala 408:97] + node _T_2255 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2256 = and(_T_2255, buf_state_en[1]) @[lsu_bus_buffer.scala 405:94] + node _T_2257 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2258 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2259 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2260 = and(_T_2258, _T_2259) @[lsu_bus_buffer.scala 406:57] + node _T_2261 = or(_T_2257, _T_2260) @[lsu_bus_buffer.scala 406:31] + node _T_2262 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2263 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2264 = and(_T_2262, _T_2263) @[lsu_bus_buffer.scala 407:41] + node _T_2265 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 407:83] + node _T_2266 = and(_T_2264, _T_2265) @[lsu_bus_buffer.scala 407:71] + node _T_2267 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 407:104] + node _T_2268 = and(_T_2266, _T_2267) @[lsu_bus_buffer.scala 407:92] + node _T_2269 = or(_T_2261, _T_2268) @[lsu_bus_buffer.scala 406:86] + node _T_2270 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2271 = and(_T_2270, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2272 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:64] + node _T_2273 = and(_T_2271, _T_2272) @[lsu_bus_buffer.scala 408:52] + node _T_2274 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:85] + node _T_2275 = and(_T_2273, _T_2274) @[lsu_bus_buffer.scala 408:73] + node _T_2276 = or(_T_2269, _T_2275) @[lsu_bus_buffer.scala 407:114] + node _T_2277 = and(_T_2256, _T_2276) @[lsu_bus_buffer.scala 405:113] + node _T_2278 = bits(buf_age[1], 1, 1) @[lsu_bus_buffer.scala 408:109] + node _T_2279 = or(_T_2277, _T_2278) @[lsu_bus_buffer.scala 408:97] + node _T_2280 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2281 = and(_T_2280, buf_state_en[1]) @[lsu_bus_buffer.scala 405:94] + node _T_2282 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2283 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2284 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2285 = and(_T_2283, _T_2284) @[lsu_bus_buffer.scala 406:57] + node _T_2286 = or(_T_2282, _T_2285) @[lsu_bus_buffer.scala 406:31] + node _T_2287 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2288 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2289 = and(_T_2287, _T_2288) @[lsu_bus_buffer.scala 407:41] + node _T_2290 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 407:83] + node _T_2291 = and(_T_2289, _T_2290) @[lsu_bus_buffer.scala 407:71] + node _T_2292 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 407:104] + node _T_2293 = and(_T_2291, _T_2292) @[lsu_bus_buffer.scala 407:92] + node _T_2294 = or(_T_2286, _T_2293) @[lsu_bus_buffer.scala 406:86] + node _T_2295 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2296 = and(_T_2295, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2297 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:64] + node _T_2298 = and(_T_2296, _T_2297) @[lsu_bus_buffer.scala 408:52] + node _T_2299 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:85] + node _T_2300 = and(_T_2298, _T_2299) @[lsu_bus_buffer.scala 408:73] + node _T_2301 = or(_T_2294, _T_2300) @[lsu_bus_buffer.scala 407:114] + node _T_2302 = and(_T_2281, _T_2301) @[lsu_bus_buffer.scala 405:113] + node _T_2303 = bits(buf_age[1], 2, 2) @[lsu_bus_buffer.scala 408:109] + node _T_2304 = or(_T_2302, _T_2303) @[lsu_bus_buffer.scala 408:97] + node _T_2305 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2306 = and(_T_2305, buf_state_en[1]) @[lsu_bus_buffer.scala 405:94] + node _T_2307 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2308 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2309 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2310 = and(_T_2308, _T_2309) @[lsu_bus_buffer.scala 406:57] + node _T_2311 = or(_T_2307, _T_2310) @[lsu_bus_buffer.scala 406:31] + node _T_2312 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2313 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2314 = and(_T_2312, _T_2313) @[lsu_bus_buffer.scala 407:41] + node _T_2315 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 407:83] + node _T_2316 = and(_T_2314, _T_2315) @[lsu_bus_buffer.scala 407:71] + node _T_2317 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 407:104] + node _T_2318 = and(_T_2316, _T_2317) @[lsu_bus_buffer.scala 407:92] + node _T_2319 = or(_T_2311, _T_2318) @[lsu_bus_buffer.scala 406:86] + node _T_2320 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2321 = and(_T_2320, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2322 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:64] + node _T_2323 = and(_T_2321, _T_2322) @[lsu_bus_buffer.scala 408:52] + node _T_2324 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:85] + node _T_2325 = and(_T_2323, _T_2324) @[lsu_bus_buffer.scala 408:73] + node _T_2326 = or(_T_2319, _T_2325) @[lsu_bus_buffer.scala 407:114] + node _T_2327 = and(_T_2306, _T_2326) @[lsu_bus_buffer.scala 405:113] + node _T_2328 = bits(buf_age[1], 3, 3) @[lsu_bus_buffer.scala 408:109] + node _T_2329 = or(_T_2327, _T_2328) @[lsu_bus_buffer.scala 408:97] node _T_2330 = cat(_T_2329, _T_2304) @[Cat.scala 29:58] node _T_2331 = cat(_T_2330, _T_2279) @[Cat.scala 29:58] node buf_age_in_1 = cat(_T_2331, _T_2254) @[Cat.scala 29:58] - node _T_2332 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] - node _T_2333 = and(_T_2332, buf_state_en[2]) @[lsu_bus_buffer.scala 406:94] - node _T_2334 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] - node _T_2335 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] - node _T_2336 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] - node _T_2337 = and(_T_2335, _T_2336) @[lsu_bus_buffer.scala 407:57] - node _T_2338 = or(_T_2334, _T_2337) @[lsu_bus_buffer.scala 407:31] - node _T_2339 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] - node _T_2340 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] - node _T_2341 = and(_T_2339, _T_2340) @[lsu_bus_buffer.scala 408:41] - node _T_2342 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:83] - node _T_2343 = and(_T_2341, _T_2342) @[lsu_bus_buffer.scala 408:71] - node _T_2344 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:104] - node _T_2345 = and(_T_2343, _T_2344) @[lsu_bus_buffer.scala 408:92] - node _T_2346 = or(_T_2338, _T_2345) @[lsu_bus_buffer.scala 407:86] - node _T_2347 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] - node _T_2348 = and(_T_2347, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] - node _T_2349 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 409:64] - node _T_2350 = and(_T_2348, _T_2349) @[lsu_bus_buffer.scala 409:52] - node _T_2351 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 409:85] - node _T_2352 = and(_T_2350, _T_2351) @[lsu_bus_buffer.scala 409:73] - node _T_2353 = or(_T_2346, _T_2352) @[lsu_bus_buffer.scala 408:114] - node _T_2354 = and(_T_2333, _T_2353) @[lsu_bus_buffer.scala 406:113] - node _T_2355 = bits(buf_age[2], 0, 0) @[lsu_bus_buffer.scala 409:109] - node _T_2356 = or(_T_2354, _T_2355) @[lsu_bus_buffer.scala 409:97] - node _T_2357 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] - node _T_2358 = and(_T_2357, buf_state_en[2]) @[lsu_bus_buffer.scala 406:94] - node _T_2359 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] - node _T_2360 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] - node _T_2361 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] - node _T_2362 = and(_T_2360, _T_2361) @[lsu_bus_buffer.scala 407:57] - node _T_2363 = or(_T_2359, _T_2362) @[lsu_bus_buffer.scala 407:31] - node _T_2364 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] - node _T_2365 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] - node _T_2366 = and(_T_2364, _T_2365) @[lsu_bus_buffer.scala 408:41] - node _T_2367 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:83] - node _T_2368 = and(_T_2366, _T_2367) @[lsu_bus_buffer.scala 408:71] - node _T_2369 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:104] - node _T_2370 = and(_T_2368, _T_2369) @[lsu_bus_buffer.scala 408:92] - node _T_2371 = or(_T_2363, _T_2370) @[lsu_bus_buffer.scala 407:86] - node _T_2372 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] - node _T_2373 = and(_T_2372, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] - node _T_2374 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 409:64] - node _T_2375 = and(_T_2373, _T_2374) @[lsu_bus_buffer.scala 409:52] - node _T_2376 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 409:85] - node _T_2377 = and(_T_2375, _T_2376) @[lsu_bus_buffer.scala 409:73] - node _T_2378 = or(_T_2371, _T_2377) @[lsu_bus_buffer.scala 408:114] - node _T_2379 = and(_T_2358, _T_2378) @[lsu_bus_buffer.scala 406:113] - node _T_2380 = bits(buf_age[2], 1, 1) @[lsu_bus_buffer.scala 409:109] - node _T_2381 = or(_T_2379, _T_2380) @[lsu_bus_buffer.scala 409:97] - node _T_2382 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] - node _T_2383 = and(_T_2382, buf_state_en[2]) @[lsu_bus_buffer.scala 406:94] - node _T_2384 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] - node _T_2385 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] - node _T_2386 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] - node _T_2387 = and(_T_2385, _T_2386) @[lsu_bus_buffer.scala 407:57] - node _T_2388 = or(_T_2384, _T_2387) @[lsu_bus_buffer.scala 407:31] - node _T_2389 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] - node _T_2390 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] - node _T_2391 = and(_T_2389, _T_2390) @[lsu_bus_buffer.scala 408:41] - node _T_2392 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:83] - node _T_2393 = and(_T_2391, _T_2392) @[lsu_bus_buffer.scala 408:71] - node _T_2394 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:104] - node _T_2395 = and(_T_2393, _T_2394) @[lsu_bus_buffer.scala 408:92] - node _T_2396 = or(_T_2388, _T_2395) @[lsu_bus_buffer.scala 407:86] - node _T_2397 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] - node _T_2398 = and(_T_2397, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] - node _T_2399 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 409:64] - node _T_2400 = and(_T_2398, _T_2399) @[lsu_bus_buffer.scala 409:52] - node _T_2401 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 409:85] - node _T_2402 = and(_T_2400, _T_2401) @[lsu_bus_buffer.scala 409:73] - node _T_2403 = or(_T_2396, _T_2402) @[lsu_bus_buffer.scala 408:114] - node _T_2404 = and(_T_2383, _T_2403) @[lsu_bus_buffer.scala 406:113] - node _T_2405 = bits(buf_age[2], 2, 2) @[lsu_bus_buffer.scala 409:109] - node _T_2406 = or(_T_2404, _T_2405) @[lsu_bus_buffer.scala 409:97] - node _T_2407 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] - node _T_2408 = and(_T_2407, buf_state_en[2]) @[lsu_bus_buffer.scala 406:94] - node _T_2409 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] - node _T_2410 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] - node _T_2411 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] - node _T_2412 = and(_T_2410, _T_2411) @[lsu_bus_buffer.scala 407:57] - node _T_2413 = or(_T_2409, _T_2412) @[lsu_bus_buffer.scala 407:31] - node _T_2414 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] - node _T_2415 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] - node _T_2416 = and(_T_2414, _T_2415) @[lsu_bus_buffer.scala 408:41] - node _T_2417 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:83] - node _T_2418 = and(_T_2416, _T_2417) @[lsu_bus_buffer.scala 408:71] - node _T_2419 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:104] - node _T_2420 = and(_T_2418, _T_2419) @[lsu_bus_buffer.scala 408:92] - node _T_2421 = or(_T_2413, _T_2420) @[lsu_bus_buffer.scala 407:86] - node _T_2422 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] - node _T_2423 = and(_T_2422, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] - node _T_2424 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 409:64] - node _T_2425 = and(_T_2423, _T_2424) @[lsu_bus_buffer.scala 409:52] - node _T_2426 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 409:85] - node _T_2427 = and(_T_2425, _T_2426) @[lsu_bus_buffer.scala 409:73] - node _T_2428 = or(_T_2421, _T_2427) @[lsu_bus_buffer.scala 408:114] - node _T_2429 = and(_T_2408, _T_2428) @[lsu_bus_buffer.scala 406:113] - node _T_2430 = bits(buf_age[2], 3, 3) @[lsu_bus_buffer.scala 409:109] - node _T_2431 = or(_T_2429, _T_2430) @[lsu_bus_buffer.scala 409:97] + node _T_2332 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2333 = and(_T_2332, buf_state_en[2]) @[lsu_bus_buffer.scala 405:94] + node _T_2334 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2335 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2336 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2337 = and(_T_2335, _T_2336) @[lsu_bus_buffer.scala 406:57] + node _T_2338 = or(_T_2334, _T_2337) @[lsu_bus_buffer.scala 406:31] + node _T_2339 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2340 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2341 = and(_T_2339, _T_2340) @[lsu_bus_buffer.scala 407:41] + node _T_2342 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 407:83] + node _T_2343 = and(_T_2341, _T_2342) @[lsu_bus_buffer.scala 407:71] + node _T_2344 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 407:104] + node _T_2345 = and(_T_2343, _T_2344) @[lsu_bus_buffer.scala 407:92] + node _T_2346 = or(_T_2338, _T_2345) @[lsu_bus_buffer.scala 406:86] + node _T_2347 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2348 = and(_T_2347, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2349 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:64] + node _T_2350 = and(_T_2348, _T_2349) @[lsu_bus_buffer.scala 408:52] + node _T_2351 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:85] + node _T_2352 = and(_T_2350, _T_2351) @[lsu_bus_buffer.scala 408:73] + node _T_2353 = or(_T_2346, _T_2352) @[lsu_bus_buffer.scala 407:114] + node _T_2354 = and(_T_2333, _T_2353) @[lsu_bus_buffer.scala 405:113] + node _T_2355 = bits(buf_age[2], 0, 0) @[lsu_bus_buffer.scala 408:109] + node _T_2356 = or(_T_2354, _T_2355) @[lsu_bus_buffer.scala 408:97] + node _T_2357 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2358 = and(_T_2357, buf_state_en[2]) @[lsu_bus_buffer.scala 405:94] + node _T_2359 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2360 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2361 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2362 = and(_T_2360, _T_2361) @[lsu_bus_buffer.scala 406:57] + node _T_2363 = or(_T_2359, _T_2362) @[lsu_bus_buffer.scala 406:31] + node _T_2364 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2365 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2366 = and(_T_2364, _T_2365) @[lsu_bus_buffer.scala 407:41] + node _T_2367 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 407:83] + node _T_2368 = and(_T_2366, _T_2367) @[lsu_bus_buffer.scala 407:71] + node _T_2369 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 407:104] + node _T_2370 = and(_T_2368, _T_2369) @[lsu_bus_buffer.scala 407:92] + node _T_2371 = or(_T_2363, _T_2370) @[lsu_bus_buffer.scala 406:86] + node _T_2372 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2373 = and(_T_2372, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2374 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:64] + node _T_2375 = and(_T_2373, _T_2374) @[lsu_bus_buffer.scala 408:52] + node _T_2376 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:85] + node _T_2377 = and(_T_2375, _T_2376) @[lsu_bus_buffer.scala 408:73] + node _T_2378 = or(_T_2371, _T_2377) @[lsu_bus_buffer.scala 407:114] + node _T_2379 = and(_T_2358, _T_2378) @[lsu_bus_buffer.scala 405:113] + node _T_2380 = bits(buf_age[2], 1, 1) @[lsu_bus_buffer.scala 408:109] + node _T_2381 = or(_T_2379, _T_2380) @[lsu_bus_buffer.scala 408:97] + node _T_2382 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2383 = and(_T_2382, buf_state_en[2]) @[lsu_bus_buffer.scala 405:94] + node _T_2384 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2385 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2386 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2387 = and(_T_2385, _T_2386) @[lsu_bus_buffer.scala 406:57] + node _T_2388 = or(_T_2384, _T_2387) @[lsu_bus_buffer.scala 406:31] + node _T_2389 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2390 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2391 = and(_T_2389, _T_2390) @[lsu_bus_buffer.scala 407:41] + node _T_2392 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 407:83] + node _T_2393 = and(_T_2391, _T_2392) @[lsu_bus_buffer.scala 407:71] + node _T_2394 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 407:104] + node _T_2395 = and(_T_2393, _T_2394) @[lsu_bus_buffer.scala 407:92] + node _T_2396 = or(_T_2388, _T_2395) @[lsu_bus_buffer.scala 406:86] + node _T_2397 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2398 = and(_T_2397, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2399 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:64] + node _T_2400 = and(_T_2398, _T_2399) @[lsu_bus_buffer.scala 408:52] + node _T_2401 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:85] + node _T_2402 = and(_T_2400, _T_2401) @[lsu_bus_buffer.scala 408:73] + node _T_2403 = or(_T_2396, _T_2402) @[lsu_bus_buffer.scala 407:114] + node _T_2404 = and(_T_2383, _T_2403) @[lsu_bus_buffer.scala 405:113] + node _T_2405 = bits(buf_age[2], 2, 2) @[lsu_bus_buffer.scala 408:109] + node _T_2406 = or(_T_2404, _T_2405) @[lsu_bus_buffer.scala 408:97] + node _T_2407 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2408 = and(_T_2407, buf_state_en[2]) @[lsu_bus_buffer.scala 405:94] + node _T_2409 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2410 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2411 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2412 = and(_T_2410, _T_2411) @[lsu_bus_buffer.scala 406:57] + node _T_2413 = or(_T_2409, _T_2412) @[lsu_bus_buffer.scala 406:31] + node _T_2414 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2415 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2416 = and(_T_2414, _T_2415) @[lsu_bus_buffer.scala 407:41] + node _T_2417 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 407:83] + node _T_2418 = and(_T_2416, _T_2417) @[lsu_bus_buffer.scala 407:71] + node _T_2419 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 407:104] + node _T_2420 = and(_T_2418, _T_2419) @[lsu_bus_buffer.scala 407:92] + node _T_2421 = or(_T_2413, _T_2420) @[lsu_bus_buffer.scala 406:86] + node _T_2422 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2423 = and(_T_2422, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2424 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:64] + node _T_2425 = and(_T_2423, _T_2424) @[lsu_bus_buffer.scala 408:52] + node _T_2426 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:85] + node _T_2427 = and(_T_2425, _T_2426) @[lsu_bus_buffer.scala 408:73] + node _T_2428 = or(_T_2421, _T_2427) @[lsu_bus_buffer.scala 407:114] + node _T_2429 = and(_T_2408, _T_2428) @[lsu_bus_buffer.scala 405:113] + node _T_2430 = bits(buf_age[2], 3, 3) @[lsu_bus_buffer.scala 408:109] + node _T_2431 = or(_T_2429, _T_2430) @[lsu_bus_buffer.scala 408:97] node _T_2432 = cat(_T_2431, _T_2406) @[Cat.scala 29:58] node _T_2433 = cat(_T_2432, _T_2381) @[Cat.scala 29:58] node buf_age_in_2 = cat(_T_2433, _T_2356) @[Cat.scala 29:58] - node _T_2434 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] - node _T_2435 = and(_T_2434, buf_state_en[3]) @[lsu_bus_buffer.scala 406:94] - node _T_2436 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] - node _T_2437 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] - node _T_2438 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] - node _T_2439 = and(_T_2437, _T_2438) @[lsu_bus_buffer.scala 407:57] - node _T_2440 = or(_T_2436, _T_2439) @[lsu_bus_buffer.scala 407:31] - node _T_2441 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] - node _T_2442 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] - node _T_2443 = and(_T_2441, _T_2442) @[lsu_bus_buffer.scala 408:41] - node _T_2444 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:83] - node _T_2445 = and(_T_2443, _T_2444) @[lsu_bus_buffer.scala 408:71] - node _T_2446 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:104] - node _T_2447 = and(_T_2445, _T_2446) @[lsu_bus_buffer.scala 408:92] - node _T_2448 = or(_T_2440, _T_2447) @[lsu_bus_buffer.scala 407:86] - node _T_2449 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] - node _T_2450 = and(_T_2449, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] - node _T_2451 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 409:64] - node _T_2452 = and(_T_2450, _T_2451) @[lsu_bus_buffer.scala 409:52] - node _T_2453 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 409:85] - node _T_2454 = and(_T_2452, _T_2453) @[lsu_bus_buffer.scala 409:73] - node _T_2455 = or(_T_2448, _T_2454) @[lsu_bus_buffer.scala 408:114] - node _T_2456 = and(_T_2435, _T_2455) @[lsu_bus_buffer.scala 406:113] - node _T_2457 = bits(buf_age[3], 0, 0) @[lsu_bus_buffer.scala 409:109] - node _T_2458 = or(_T_2456, _T_2457) @[lsu_bus_buffer.scala 409:97] - node _T_2459 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] - node _T_2460 = and(_T_2459, buf_state_en[3]) @[lsu_bus_buffer.scala 406:94] - node _T_2461 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] - node _T_2462 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] - node _T_2463 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] - node _T_2464 = and(_T_2462, _T_2463) @[lsu_bus_buffer.scala 407:57] - node _T_2465 = or(_T_2461, _T_2464) @[lsu_bus_buffer.scala 407:31] - node _T_2466 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] - node _T_2467 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] - node _T_2468 = and(_T_2466, _T_2467) @[lsu_bus_buffer.scala 408:41] - node _T_2469 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:83] - node _T_2470 = and(_T_2468, _T_2469) @[lsu_bus_buffer.scala 408:71] - node _T_2471 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:104] - node _T_2472 = and(_T_2470, _T_2471) @[lsu_bus_buffer.scala 408:92] - node _T_2473 = or(_T_2465, _T_2472) @[lsu_bus_buffer.scala 407:86] - node _T_2474 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] - node _T_2475 = and(_T_2474, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] - node _T_2476 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 409:64] - node _T_2477 = and(_T_2475, _T_2476) @[lsu_bus_buffer.scala 409:52] - node _T_2478 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 409:85] - node _T_2479 = and(_T_2477, _T_2478) @[lsu_bus_buffer.scala 409:73] - node _T_2480 = or(_T_2473, _T_2479) @[lsu_bus_buffer.scala 408:114] - node _T_2481 = and(_T_2460, _T_2480) @[lsu_bus_buffer.scala 406:113] - node _T_2482 = bits(buf_age[3], 1, 1) @[lsu_bus_buffer.scala 409:109] - node _T_2483 = or(_T_2481, _T_2482) @[lsu_bus_buffer.scala 409:97] - node _T_2484 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] - node _T_2485 = and(_T_2484, buf_state_en[3]) @[lsu_bus_buffer.scala 406:94] - node _T_2486 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] - node _T_2487 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] - node _T_2488 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] - node _T_2489 = and(_T_2487, _T_2488) @[lsu_bus_buffer.scala 407:57] - node _T_2490 = or(_T_2486, _T_2489) @[lsu_bus_buffer.scala 407:31] - node _T_2491 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] - node _T_2492 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] - node _T_2493 = and(_T_2491, _T_2492) @[lsu_bus_buffer.scala 408:41] - node _T_2494 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:83] - node _T_2495 = and(_T_2493, _T_2494) @[lsu_bus_buffer.scala 408:71] - node _T_2496 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:104] - node _T_2497 = and(_T_2495, _T_2496) @[lsu_bus_buffer.scala 408:92] - node _T_2498 = or(_T_2490, _T_2497) @[lsu_bus_buffer.scala 407:86] - node _T_2499 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] - node _T_2500 = and(_T_2499, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] - node _T_2501 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 409:64] - node _T_2502 = and(_T_2500, _T_2501) @[lsu_bus_buffer.scala 409:52] - node _T_2503 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 409:85] - node _T_2504 = and(_T_2502, _T_2503) @[lsu_bus_buffer.scala 409:73] - node _T_2505 = or(_T_2498, _T_2504) @[lsu_bus_buffer.scala 408:114] - node _T_2506 = and(_T_2485, _T_2505) @[lsu_bus_buffer.scala 406:113] - node _T_2507 = bits(buf_age[3], 2, 2) @[lsu_bus_buffer.scala 409:109] - node _T_2508 = or(_T_2506, _T_2507) @[lsu_bus_buffer.scala 409:97] - node _T_2509 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 406:83] - node _T_2510 = and(_T_2509, buf_state_en[3]) @[lsu_bus_buffer.scala 406:94] - node _T_2511 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 407:20] - node _T_2512 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 407:47] - node _T_2513 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 407:59] - node _T_2514 = and(_T_2512, _T_2513) @[lsu_bus_buffer.scala 407:57] - node _T_2515 = or(_T_2511, _T_2514) @[lsu_bus_buffer.scala 407:31] - node _T_2516 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:23] - node _T_2517 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:53] - node _T_2518 = and(_T_2516, _T_2517) @[lsu_bus_buffer.scala 408:41] - node _T_2519 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:83] - node _T_2520 = and(_T_2518, _T_2519) @[lsu_bus_buffer.scala 408:71] - node _T_2521 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:104] - node _T_2522 = and(_T_2520, _T_2521) @[lsu_bus_buffer.scala 408:92] - node _T_2523 = or(_T_2515, _T_2522) @[lsu_bus_buffer.scala 407:86] - node _T_2524 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 409:17] - node _T_2525 = and(_T_2524, io.ldst_dual_r) @[lsu_bus_buffer.scala 409:35] - node _T_2526 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 409:64] - node _T_2527 = and(_T_2525, _T_2526) @[lsu_bus_buffer.scala 409:52] - node _T_2528 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 409:85] - node _T_2529 = and(_T_2527, _T_2528) @[lsu_bus_buffer.scala 409:73] - node _T_2530 = or(_T_2523, _T_2529) @[lsu_bus_buffer.scala 408:114] - node _T_2531 = and(_T_2510, _T_2530) @[lsu_bus_buffer.scala 406:113] - node _T_2532 = bits(buf_age[3], 3, 3) @[lsu_bus_buffer.scala 409:109] - node _T_2533 = or(_T_2531, _T_2532) @[lsu_bus_buffer.scala 409:97] + node _T_2434 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2435 = and(_T_2434, buf_state_en[3]) @[lsu_bus_buffer.scala 405:94] + node _T_2436 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2437 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2438 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2439 = and(_T_2437, _T_2438) @[lsu_bus_buffer.scala 406:57] + node _T_2440 = or(_T_2436, _T_2439) @[lsu_bus_buffer.scala 406:31] + node _T_2441 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2442 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2443 = and(_T_2441, _T_2442) @[lsu_bus_buffer.scala 407:41] + node _T_2444 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 407:83] + node _T_2445 = and(_T_2443, _T_2444) @[lsu_bus_buffer.scala 407:71] + node _T_2446 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 407:104] + node _T_2447 = and(_T_2445, _T_2446) @[lsu_bus_buffer.scala 407:92] + node _T_2448 = or(_T_2440, _T_2447) @[lsu_bus_buffer.scala 406:86] + node _T_2449 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2450 = and(_T_2449, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2451 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:64] + node _T_2452 = and(_T_2450, _T_2451) @[lsu_bus_buffer.scala 408:52] + node _T_2453 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 408:85] + node _T_2454 = and(_T_2452, _T_2453) @[lsu_bus_buffer.scala 408:73] + node _T_2455 = or(_T_2448, _T_2454) @[lsu_bus_buffer.scala 407:114] + node _T_2456 = and(_T_2435, _T_2455) @[lsu_bus_buffer.scala 405:113] + node _T_2457 = bits(buf_age[3], 0, 0) @[lsu_bus_buffer.scala 408:109] + node _T_2458 = or(_T_2456, _T_2457) @[lsu_bus_buffer.scala 408:97] + node _T_2459 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2460 = and(_T_2459, buf_state_en[3]) @[lsu_bus_buffer.scala 405:94] + node _T_2461 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2462 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2463 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2464 = and(_T_2462, _T_2463) @[lsu_bus_buffer.scala 406:57] + node _T_2465 = or(_T_2461, _T_2464) @[lsu_bus_buffer.scala 406:31] + node _T_2466 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2467 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2468 = and(_T_2466, _T_2467) @[lsu_bus_buffer.scala 407:41] + node _T_2469 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 407:83] + node _T_2470 = and(_T_2468, _T_2469) @[lsu_bus_buffer.scala 407:71] + node _T_2471 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 407:104] + node _T_2472 = and(_T_2470, _T_2471) @[lsu_bus_buffer.scala 407:92] + node _T_2473 = or(_T_2465, _T_2472) @[lsu_bus_buffer.scala 406:86] + node _T_2474 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2475 = and(_T_2474, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2476 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:64] + node _T_2477 = and(_T_2475, _T_2476) @[lsu_bus_buffer.scala 408:52] + node _T_2478 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 408:85] + node _T_2479 = and(_T_2477, _T_2478) @[lsu_bus_buffer.scala 408:73] + node _T_2480 = or(_T_2473, _T_2479) @[lsu_bus_buffer.scala 407:114] + node _T_2481 = and(_T_2460, _T_2480) @[lsu_bus_buffer.scala 405:113] + node _T_2482 = bits(buf_age[3], 1, 1) @[lsu_bus_buffer.scala 408:109] + node _T_2483 = or(_T_2481, _T_2482) @[lsu_bus_buffer.scala 408:97] + node _T_2484 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2485 = and(_T_2484, buf_state_en[3]) @[lsu_bus_buffer.scala 405:94] + node _T_2486 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2487 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2488 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2489 = and(_T_2487, _T_2488) @[lsu_bus_buffer.scala 406:57] + node _T_2490 = or(_T_2486, _T_2489) @[lsu_bus_buffer.scala 406:31] + node _T_2491 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2492 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2493 = and(_T_2491, _T_2492) @[lsu_bus_buffer.scala 407:41] + node _T_2494 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 407:83] + node _T_2495 = and(_T_2493, _T_2494) @[lsu_bus_buffer.scala 407:71] + node _T_2496 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 407:104] + node _T_2497 = and(_T_2495, _T_2496) @[lsu_bus_buffer.scala 407:92] + node _T_2498 = or(_T_2490, _T_2497) @[lsu_bus_buffer.scala 406:86] + node _T_2499 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2500 = and(_T_2499, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2501 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:64] + node _T_2502 = and(_T_2500, _T_2501) @[lsu_bus_buffer.scala 408:52] + node _T_2503 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 408:85] + node _T_2504 = and(_T_2502, _T_2503) @[lsu_bus_buffer.scala 408:73] + node _T_2505 = or(_T_2498, _T_2504) @[lsu_bus_buffer.scala 407:114] + node _T_2506 = and(_T_2485, _T_2505) @[lsu_bus_buffer.scala 405:113] + node _T_2507 = bits(buf_age[3], 2, 2) @[lsu_bus_buffer.scala 408:109] + node _T_2508 = or(_T_2506, _T_2507) @[lsu_bus_buffer.scala 408:97] + node _T_2509 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 405:83] + node _T_2510 = and(_T_2509, buf_state_en[3]) @[lsu_bus_buffer.scala 405:94] + node _T_2511 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 406:20] + node _T_2512 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 406:47] + node _T_2513 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 406:59] + node _T_2514 = and(_T_2512, _T_2513) @[lsu_bus_buffer.scala 406:57] + node _T_2515 = or(_T_2511, _T_2514) @[lsu_bus_buffer.scala 406:31] + node _T_2516 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 407:23] + node _T_2517 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 407:53] + node _T_2518 = and(_T_2516, _T_2517) @[lsu_bus_buffer.scala 407:41] + node _T_2519 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 407:83] + node _T_2520 = and(_T_2518, _T_2519) @[lsu_bus_buffer.scala 407:71] + node _T_2521 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 407:104] + node _T_2522 = and(_T_2520, _T_2521) @[lsu_bus_buffer.scala 407:92] + node _T_2523 = or(_T_2515, _T_2522) @[lsu_bus_buffer.scala 406:86] + node _T_2524 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 408:17] + node _T_2525 = and(_T_2524, io.ldst_dual_r) @[lsu_bus_buffer.scala 408:35] + node _T_2526 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:64] + node _T_2527 = and(_T_2525, _T_2526) @[lsu_bus_buffer.scala 408:52] + node _T_2528 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 408:85] + node _T_2529 = and(_T_2527, _T_2528) @[lsu_bus_buffer.scala 408:73] + node _T_2530 = or(_T_2523, _T_2529) @[lsu_bus_buffer.scala 407:114] + node _T_2531 = and(_T_2510, _T_2530) @[lsu_bus_buffer.scala 405:113] + node _T_2532 = bits(buf_age[3], 3, 3) @[lsu_bus_buffer.scala 408:109] + node _T_2533 = or(_T_2531, _T_2532) @[lsu_bus_buffer.scala 408:97] node _T_2534 = cat(_T_2533, _T_2508) @[Cat.scala 29:58] node _T_2535 = cat(_T_2534, _T_2483) @[Cat.scala 29:58] node buf_age_in_3 = cat(_T_2535, _T_2458) @[Cat.scala 29:58] - wire buf_ageQ : UInt<4>[4] @[lsu_bus_buffer.scala 410:22] - buf_ageQ[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 411:12] - buf_ageQ[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 411:12] - buf_ageQ[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 411:12] - buf_ageQ[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 411:12] - node _T_2536 = bits(buf_ageQ[0], 0, 0) @[lsu_bus_buffer.scala 412:72] - node _T_2537 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] - node _T_2538 = and(_T_2537, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 412:103] - node _T_2539 = eq(_T_2538, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] - node _T_2540 = and(_T_2536, _T_2539) @[lsu_bus_buffer.scala 412:76] - node _T_2541 = bits(buf_ageQ[0], 1, 1) @[lsu_bus_buffer.scala 412:72] - node _T_2542 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] - node _T_2543 = and(_T_2542, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 412:103] - node _T_2544 = eq(_T_2543, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] - node _T_2545 = and(_T_2541, _T_2544) @[lsu_bus_buffer.scala 412:76] - node _T_2546 = bits(buf_ageQ[0], 2, 2) @[lsu_bus_buffer.scala 412:72] - node _T_2547 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] - node _T_2548 = and(_T_2547, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 412:103] - node _T_2549 = eq(_T_2548, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] - node _T_2550 = and(_T_2546, _T_2549) @[lsu_bus_buffer.scala 412:76] - node _T_2551 = bits(buf_ageQ[0], 3, 3) @[lsu_bus_buffer.scala 412:72] - node _T_2552 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] - node _T_2553 = and(_T_2552, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 412:103] - node _T_2554 = eq(_T_2553, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] - node _T_2555 = and(_T_2551, _T_2554) @[lsu_bus_buffer.scala 412:76] + wire buf_ageQ : UInt<4>[4] @[lsu_bus_buffer.scala 409:22] + buf_ageQ[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 410:12] + buf_ageQ[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 410:12] + buf_ageQ[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 410:12] + buf_ageQ[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 410:12] + node _T_2536 = bits(buf_ageQ[0], 0, 0) @[lsu_bus_buffer.scala 411:72] + node _T_2537 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2538 = and(_T_2537, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 411:103] + node _T_2539 = eq(_T_2538, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2540 = and(_T_2536, _T_2539) @[lsu_bus_buffer.scala 411:76] + node _T_2541 = bits(buf_ageQ[0], 1, 1) @[lsu_bus_buffer.scala 411:72] + node _T_2542 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2543 = and(_T_2542, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 411:103] + node _T_2544 = eq(_T_2543, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2545 = and(_T_2541, _T_2544) @[lsu_bus_buffer.scala 411:76] + node _T_2546 = bits(buf_ageQ[0], 2, 2) @[lsu_bus_buffer.scala 411:72] + node _T_2547 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2548 = and(_T_2547, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 411:103] + node _T_2549 = eq(_T_2548, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2550 = and(_T_2546, _T_2549) @[lsu_bus_buffer.scala 411:76] + node _T_2551 = bits(buf_ageQ[0], 3, 3) @[lsu_bus_buffer.scala 411:72] + node _T_2552 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2553 = and(_T_2552, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 411:103] + node _T_2554 = eq(_T_2553, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2555 = and(_T_2551, _T_2554) @[lsu_bus_buffer.scala 411:76] node _T_2556 = cat(_T_2555, _T_2550) @[Cat.scala 29:58] node _T_2557 = cat(_T_2556, _T_2545) @[Cat.scala 29:58] node _T_2558 = cat(_T_2557, _T_2540) @[Cat.scala 29:58] - node _T_2559 = bits(buf_ageQ[1], 0, 0) @[lsu_bus_buffer.scala 412:72] - node _T_2560 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] - node _T_2561 = and(_T_2560, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 412:103] - node _T_2562 = eq(_T_2561, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] - node _T_2563 = and(_T_2559, _T_2562) @[lsu_bus_buffer.scala 412:76] - node _T_2564 = bits(buf_ageQ[1], 1, 1) @[lsu_bus_buffer.scala 412:72] - node _T_2565 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] - node _T_2566 = and(_T_2565, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 412:103] - node _T_2567 = eq(_T_2566, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] - node _T_2568 = and(_T_2564, _T_2567) @[lsu_bus_buffer.scala 412:76] - node _T_2569 = bits(buf_ageQ[1], 2, 2) @[lsu_bus_buffer.scala 412:72] - node _T_2570 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] - node _T_2571 = and(_T_2570, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 412:103] - node _T_2572 = eq(_T_2571, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] - node _T_2573 = and(_T_2569, _T_2572) @[lsu_bus_buffer.scala 412:76] - node _T_2574 = bits(buf_ageQ[1], 3, 3) @[lsu_bus_buffer.scala 412:72] - node _T_2575 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] - node _T_2576 = and(_T_2575, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 412:103] - node _T_2577 = eq(_T_2576, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] - node _T_2578 = and(_T_2574, _T_2577) @[lsu_bus_buffer.scala 412:76] + node _T_2559 = bits(buf_ageQ[1], 0, 0) @[lsu_bus_buffer.scala 411:72] + node _T_2560 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2561 = and(_T_2560, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 411:103] + node _T_2562 = eq(_T_2561, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2563 = and(_T_2559, _T_2562) @[lsu_bus_buffer.scala 411:76] + node _T_2564 = bits(buf_ageQ[1], 1, 1) @[lsu_bus_buffer.scala 411:72] + node _T_2565 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2566 = and(_T_2565, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 411:103] + node _T_2567 = eq(_T_2566, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2568 = and(_T_2564, _T_2567) @[lsu_bus_buffer.scala 411:76] + node _T_2569 = bits(buf_ageQ[1], 2, 2) @[lsu_bus_buffer.scala 411:72] + node _T_2570 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2571 = and(_T_2570, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 411:103] + node _T_2572 = eq(_T_2571, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2573 = and(_T_2569, _T_2572) @[lsu_bus_buffer.scala 411:76] + node _T_2574 = bits(buf_ageQ[1], 3, 3) @[lsu_bus_buffer.scala 411:72] + node _T_2575 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2576 = and(_T_2575, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 411:103] + node _T_2577 = eq(_T_2576, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2578 = and(_T_2574, _T_2577) @[lsu_bus_buffer.scala 411:76] node _T_2579 = cat(_T_2578, _T_2573) @[Cat.scala 29:58] node _T_2580 = cat(_T_2579, _T_2568) @[Cat.scala 29:58] node _T_2581 = cat(_T_2580, _T_2563) @[Cat.scala 29:58] - node _T_2582 = bits(buf_ageQ[2], 0, 0) @[lsu_bus_buffer.scala 412:72] - node _T_2583 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] - node _T_2584 = and(_T_2583, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 412:103] - node _T_2585 = eq(_T_2584, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] - node _T_2586 = and(_T_2582, _T_2585) @[lsu_bus_buffer.scala 412:76] - node _T_2587 = bits(buf_ageQ[2], 1, 1) @[lsu_bus_buffer.scala 412:72] - node _T_2588 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] - node _T_2589 = and(_T_2588, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 412:103] - node _T_2590 = eq(_T_2589, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] - node _T_2591 = and(_T_2587, _T_2590) @[lsu_bus_buffer.scala 412:76] - node _T_2592 = bits(buf_ageQ[2], 2, 2) @[lsu_bus_buffer.scala 412:72] - node _T_2593 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] - node _T_2594 = and(_T_2593, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 412:103] - node _T_2595 = eq(_T_2594, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] - node _T_2596 = and(_T_2592, _T_2595) @[lsu_bus_buffer.scala 412:76] - node _T_2597 = bits(buf_ageQ[2], 3, 3) @[lsu_bus_buffer.scala 412:72] - node _T_2598 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] - node _T_2599 = and(_T_2598, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 412:103] - node _T_2600 = eq(_T_2599, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] - node _T_2601 = and(_T_2597, _T_2600) @[lsu_bus_buffer.scala 412:76] + node _T_2582 = bits(buf_ageQ[2], 0, 0) @[lsu_bus_buffer.scala 411:72] + node _T_2583 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2584 = and(_T_2583, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 411:103] + node _T_2585 = eq(_T_2584, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2586 = and(_T_2582, _T_2585) @[lsu_bus_buffer.scala 411:76] + node _T_2587 = bits(buf_ageQ[2], 1, 1) @[lsu_bus_buffer.scala 411:72] + node _T_2588 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2589 = and(_T_2588, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 411:103] + node _T_2590 = eq(_T_2589, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2591 = and(_T_2587, _T_2590) @[lsu_bus_buffer.scala 411:76] + node _T_2592 = bits(buf_ageQ[2], 2, 2) @[lsu_bus_buffer.scala 411:72] + node _T_2593 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2594 = and(_T_2593, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 411:103] + node _T_2595 = eq(_T_2594, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2596 = and(_T_2592, _T_2595) @[lsu_bus_buffer.scala 411:76] + node _T_2597 = bits(buf_ageQ[2], 3, 3) @[lsu_bus_buffer.scala 411:72] + node _T_2598 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2599 = and(_T_2598, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 411:103] + node _T_2600 = eq(_T_2599, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2601 = and(_T_2597, _T_2600) @[lsu_bus_buffer.scala 411:76] node _T_2602 = cat(_T_2601, _T_2596) @[Cat.scala 29:58] node _T_2603 = cat(_T_2602, _T_2591) @[Cat.scala 29:58] node _T_2604 = cat(_T_2603, _T_2586) @[Cat.scala 29:58] - node _T_2605 = bits(buf_ageQ[3], 0, 0) @[lsu_bus_buffer.scala 412:72] - node _T_2606 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] - node _T_2607 = and(_T_2606, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 412:103] - node _T_2608 = eq(_T_2607, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] - node _T_2609 = and(_T_2605, _T_2608) @[lsu_bus_buffer.scala 412:76] - node _T_2610 = bits(buf_ageQ[3], 1, 1) @[lsu_bus_buffer.scala 412:72] - node _T_2611 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] - node _T_2612 = and(_T_2611, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 412:103] - node _T_2613 = eq(_T_2612, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] - node _T_2614 = and(_T_2610, _T_2613) @[lsu_bus_buffer.scala 412:76] - node _T_2615 = bits(buf_ageQ[3], 2, 2) @[lsu_bus_buffer.scala 412:72] - node _T_2616 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] - node _T_2617 = and(_T_2616, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 412:103] - node _T_2618 = eq(_T_2617, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] - node _T_2619 = and(_T_2615, _T_2618) @[lsu_bus_buffer.scala 412:76] - node _T_2620 = bits(buf_ageQ[3], 3, 3) @[lsu_bus_buffer.scala 412:72] - node _T_2621 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 412:93] - node _T_2622 = and(_T_2621, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 412:103] - node _T_2623 = eq(_T_2622, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:78] - node _T_2624 = and(_T_2620, _T_2623) @[lsu_bus_buffer.scala 412:76] + node _T_2605 = bits(buf_ageQ[3], 0, 0) @[lsu_bus_buffer.scala 411:72] + node _T_2606 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2607 = and(_T_2606, buf_cmd_state_bus_en[0]) @[lsu_bus_buffer.scala 411:103] + node _T_2608 = eq(_T_2607, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2609 = and(_T_2605, _T_2608) @[lsu_bus_buffer.scala 411:76] + node _T_2610 = bits(buf_ageQ[3], 1, 1) @[lsu_bus_buffer.scala 411:72] + node _T_2611 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2612 = and(_T_2611, buf_cmd_state_bus_en[1]) @[lsu_bus_buffer.scala 411:103] + node _T_2613 = eq(_T_2612, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2614 = and(_T_2610, _T_2613) @[lsu_bus_buffer.scala 411:76] + node _T_2615 = bits(buf_ageQ[3], 2, 2) @[lsu_bus_buffer.scala 411:72] + node _T_2616 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2617 = and(_T_2616, buf_cmd_state_bus_en[2]) @[lsu_bus_buffer.scala 411:103] + node _T_2618 = eq(_T_2617, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2619 = and(_T_2615, _T_2618) @[lsu_bus_buffer.scala 411:76] + node _T_2620 = bits(buf_ageQ[3], 3, 3) @[lsu_bus_buffer.scala 411:72] + node _T_2621 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 411:93] + node _T_2622 = and(_T_2621, buf_cmd_state_bus_en[3]) @[lsu_bus_buffer.scala 411:103] + node _T_2623 = eq(_T_2622, UInt<1>("h00")) @[lsu_bus_buffer.scala 411:78] + node _T_2624 = and(_T_2620, _T_2623) @[lsu_bus_buffer.scala 411:76] node _T_2625 = cat(_T_2624, _T_2619) @[Cat.scala 29:58] node _T_2626 = cat(_T_2625, _T_2614) @[Cat.scala 29:58] node _T_2627 = cat(_T_2626, _T_2609) @[Cat.scala 29:58] - buf_age[0] <= _T_2558 @[lsu_bus_buffer.scala 412:11] - buf_age[1] <= _T_2581 @[lsu_bus_buffer.scala 412:11] - buf_age[2] <= _T_2604 @[lsu_bus_buffer.scala 412:11] - buf_age[3] <= _T_2627 @[lsu_bus_buffer.scala 412:11] - node _T_2628 = eq(UInt<1>("h00"), UInt<1>("h00")) @[lsu_bus_buffer.scala 413:76] - node _T_2629 = bits(buf_age[0], 0, 0) @[lsu_bus_buffer.scala 413:100] - node _T_2630 = eq(_T_2629, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] - node _T_2631 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] - node _T_2632 = and(_T_2630, _T_2631) @[lsu_bus_buffer.scala 413:104] - node _T_2633 = mux(_T_2628, UInt<1>("h00"), _T_2632) @[lsu_bus_buffer.scala 413:72] - node _T_2634 = eq(UInt<1>("h00"), UInt<1>("h01")) @[lsu_bus_buffer.scala 413:76] - node _T_2635 = bits(buf_age[0], 1, 1) @[lsu_bus_buffer.scala 413:100] - node _T_2636 = eq(_T_2635, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] - node _T_2637 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] - node _T_2638 = and(_T_2636, _T_2637) @[lsu_bus_buffer.scala 413:104] - node _T_2639 = mux(_T_2634, UInt<1>("h00"), _T_2638) @[lsu_bus_buffer.scala 413:72] - node _T_2640 = eq(UInt<1>("h00"), UInt<2>("h02")) @[lsu_bus_buffer.scala 413:76] - node _T_2641 = bits(buf_age[0], 2, 2) @[lsu_bus_buffer.scala 413:100] - node _T_2642 = eq(_T_2641, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] - node _T_2643 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] - node _T_2644 = and(_T_2642, _T_2643) @[lsu_bus_buffer.scala 413:104] - node _T_2645 = mux(_T_2640, UInt<1>("h00"), _T_2644) @[lsu_bus_buffer.scala 413:72] - node _T_2646 = eq(UInt<1>("h00"), UInt<2>("h03")) @[lsu_bus_buffer.scala 413:76] - node _T_2647 = bits(buf_age[0], 3, 3) @[lsu_bus_buffer.scala 413:100] - node _T_2648 = eq(_T_2647, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] - node _T_2649 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] - node _T_2650 = and(_T_2648, _T_2649) @[lsu_bus_buffer.scala 413:104] - node _T_2651 = mux(_T_2646, UInt<1>("h00"), _T_2650) @[lsu_bus_buffer.scala 413:72] + buf_age[0] <= _T_2558 @[lsu_bus_buffer.scala 411:11] + buf_age[1] <= _T_2581 @[lsu_bus_buffer.scala 411:11] + buf_age[2] <= _T_2604 @[lsu_bus_buffer.scala 411:11] + buf_age[3] <= _T_2627 @[lsu_bus_buffer.scala 411:11] + node _T_2628 = eq(UInt<1>("h00"), UInt<1>("h00")) @[lsu_bus_buffer.scala 412:76] + node _T_2629 = bits(buf_age[0], 0, 0) @[lsu_bus_buffer.scala 412:100] + node _T_2630 = eq(_T_2629, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2631 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2632 = and(_T_2630, _T_2631) @[lsu_bus_buffer.scala 412:104] + node _T_2633 = mux(_T_2628, UInt<1>("h00"), _T_2632) @[lsu_bus_buffer.scala 412:72] + node _T_2634 = eq(UInt<1>("h00"), UInt<1>("h01")) @[lsu_bus_buffer.scala 412:76] + node _T_2635 = bits(buf_age[0], 1, 1) @[lsu_bus_buffer.scala 412:100] + node _T_2636 = eq(_T_2635, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2637 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2638 = and(_T_2636, _T_2637) @[lsu_bus_buffer.scala 412:104] + node _T_2639 = mux(_T_2634, UInt<1>("h00"), _T_2638) @[lsu_bus_buffer.scala 412:72] + node _T_2640 = eq(UInt<1>("h00"), UInt<2>("h02")) @[lsu_bus_buffer.scala 412:76] + node _T_2641 = bits(buf_age[0], 2, 2) @[lsu_bus_buffer.scala 412:100] + node _T_2642 = eq(_T_2641, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2643 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2644 = and(_T_2642, _T_2643) @[lsu_bus_buffer.scala 412:104] + node _T_2645 = mux(_T_2640, UInt<1>("h00"), _T_2644) @[lsu_bus_buffer.scala 412:72] + node _T_2646 = eq(UInt<1>("h00"), UInt<2>("h03")) @[lsu_bus_buffer.scala 412:76] + node _T_2647 = bits(buf_age[0], 3, 3) @[lsu_bus_buffer.scala 412:100] + node _T_2648 = eq(_T_2647, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2649 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2650 = and(_T_2648, _T_2649) @[lsu_bus_buffer.scala 412:104] + node _T_2651 = mux(_T_2646, UInt<1>("h00"), _T_2650) @[lsu_bus_buffer.scala 412:72] node _T_2652 = cat(_T_2651, _T_2645) @[Cat.scala 29:58] node _T_2653 = cat(_T_2652, _T_2639) @[Cat.scala 29:58] node _T_2654 = cat(_T_2653, _T_2633) @[Cat.scala 29:58] - node _T_2655 = eq(UInt<1>("h01"), UInt<1>("h00")) @[lsu_bus_buffer.scala 413:76] - node _T_2656 = bits(buf_age[1], 0, 0) @[lsu_bus_buffer.scala 413:100] - node _T_2657 = eq(_T_2656, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] - node _T_2658 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] - node _T_2659 = and(_T_2657, _T_2658) @[lsu_bus_buffer.scala 413:104] - node _T_2660 = mux(_T_2655, UInt<1>("h00"), _T_2659) @[lsu_bus_buffer.scala 413:72] - node _T_2661 = eq(UInt<1>("h01"), UInt<1>("h01")) @[lsu_bus_buffer.scala 413:76] - node _T_2662 = bits(buf_age[1], 1, 1) @[lsu_bus_buffer.scala 413:100] - node _T_2663 = eq(_T_2662, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] - node _T_2664 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] - node _T_2665 = and(_T_2663, _T_2664) @[lsu_bus_buffer.scala 413:104] - node _T_2666 = mux(_T_2661, UInt<1>("h00"), _T_2665) @[lsu_bus_buffer.scala 413:72] - node _T_2667 = eq(UInt<1>("h01"), UInt<2>("h02")) @[lsu_bus_buffer.scala 413:76] - node _T_2668 = bits(buf_age[1], 2, 2) @[lsu_bus_buffer.scala 413:100] - node _T_2669 = eq(_T_2668, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] - node _T_2670 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] - node _T_2671 = and(_T_2669, _T_2670) @[lsu_bus_buffer.scala 413:104] - node _T_2672 = mux(_T_2667, UInt<1>("h00"), _T_2671) @[lsu_bus_buffer.scala 413:72] - node _T_2673 = eq(UInt<1>("h01"), UInt<2>("h03")) @[lsu_bus_buffer.scala 413:76] - node _T_2674 = bits(buf_age[1], 3, 3) @[lsu_bus_buffer.scala 413:100] - node _T_2675 = eq(_T_2674, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] - node _T_2676 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] - node _T_2677 = and(_T_2675, _T_2676) @[lsu_bus_buffer.scala 413:104] - node _T_2678 = mux(_T_2673, UInt<1>("h00"), _T_2677) @[lsu_bus_buffer.scala 413:72] + node _T_2655 = eq(UInt<1>("h01"), UInt<1>("h00")) @[lsu_bus_buffer.scala 412:76] + node _T_2656 = bits(buf_age[1], 0, 0) @[lsu_bus_buffer.scala 412:100] + node _T_2657 = eq(_T_2656, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2658 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2659 = and(_T_2657, _T_2658) @[lsu_bus_buffer.scala 412:104] + node _T_2660 = mux(_T_2655, UInt<1>("h00"), _T_2659) @[lsu_bus_buffer.scala 412:72] + node _T_2661 = eq(UInt<1>("h01"), UInt<1>("h01")) @[lsu_bus_buffer.scala 412:76] + node _T_2662 = bits(buf_age[1], 1, 1) @[lsu_bus_buffer.scala 412:100] + node _T_2663 = eq(_T_2662, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2664 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2665 = and(_T_2663, _T_2664) @[lsu_bus_buffer.scala 412:104] + node _T_2666 = mux(_T_2661, UInt<1>("h00"), _T_2665) @[lsu_bus_buffer.scala 412:72] + node _T_2667 = eq(UInt<1>("h01"), UInt<2>("h02")) @[lsu_bus_buffer.scala 412:76] + node _T_2668 = bits(buf_age[1], 2, 2) @[lsu_bus_buffer.scala 412:100] + node _T_2669 = eq(_T_2668, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2670 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2671 = and(_T_2669, _T_2670) @[lsu_bus_buffer.scala 412:104] + node _T_2672 = mux(_T_2667, UInt<1>("h00"), _T_2671) @[lsu_bus_buffer.scala 412:72] + node _T_2673 = eq(UInt<1>("h01"), UInt<2>("h03")) @[lsu_bus_buffer.scala 412:76] + node _T_2674 = bits(buf_age[1], 3, 3) @[lsu_bus_buffer.scala 412:100] + node _T_2675 = eq(_T_2674, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2676 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2677 = and(_T_2675, _T_2676) @[lsu_bus_buffer.scala 412:104] + node _T_2678 = mux(_T_2673, UInt<1>("h00"), _T_2677) @[lsu_bus_buffer.scala 412:72] node _T_2679 = cat(_T_2678, _T_2672) @[Cat.scala 29:58] node _T_2680 = cat(_T_2679, _T_2666) @[Cat.scala 29:58] node _T_2681 = cat(_T_2680, _T_2660) @[Cat.scala 29:58] - node _T_2682 = eq(UInt<2>("h02"), UInt<1>("h00")) @[lsu_bus_buffer.scala 413:76] - node _T_2683 = bits(buf_age[2], 0, 0) @[lsu_bus_buffer.scala 413:100] - node _T_2684 = eq(_T_2683, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] - node _T_2685 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] - node _T_2686 = and(_T_2684, _T_2685) @[lsu_bus_buffer.scala 413:104] - node _T_2687 = mux(_T_2682, UInt<1>("h00"), _T_2686) @[lsu_bus_buffer.scala 413:72] - node _T_2688 = eq(UInt<2>("h02"), UInt<1>("h01")) @[lsu_bus_buffer.scala 413:76] - node _T_2689 = bits(buf_age[2], 1, 1) @[lsu_bus_buffer.scala 413:100] - node _T_2690 = eq(_T_2689, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] - node _T_2691 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] - node _T_2692 = and(_T_2690, _T_2691) @[lsu_bus_buffer.scala 413:104] - node _T_2693 = mux(_T_2688, UInt<1>("h00"), _T_2692) @[lsu_bus_buffer.scala 413:72] - node _T_2694 = eq(UInt<2>("h02"), UInt<2>("h02")) @[lsu_bus_buffer.scala 413:76] - node _T_2695 = bits(buf_age[2], 2, 2) @[lsu_bus_buffer.scala 413:100] - node _T_2696 = eq(_T_2695, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] - node _T_2697 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] - node _T_2698 = and(_T_2696, _T_2697) @[lsu_bus_buffer.scala 413:104] - node _T_2699 = mux(_T_2694, UInt<1>("h00"), _T_2698) @[lsu_bus_buffer.scala 413:72] - node _T_2700 = eq(UInt<2>("h02"), UInt<2>("h03")) @[lsu_bus_buffer.scala 413:76] - node _T_2701 = bits(buf_age[2], 3, 3) @[lsu_bus_buffer.scala 413:100] - node _T_2702 = eq(_T_2701, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] - node _T_2703 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] - node _T_2704 = and(_T_2702, _T_2703) @[lsu_bus_buffer.scala 413:104] - node _T_2705 = mux(_T_2700, UInt<1>("h00"), _T_2704) @[lsu_bus_buffer.scala 413:72] + node _T_2682 = eq(UInt<2>("h02"), UInt<1>("h00")) @[lsu_bus_buffer.scala 412:76] + node _T_2683 = bits(buf_age[2], 0, 0) @[lsu_bus_buffer.scala 412:100] + node _T_2684 = eq(_T_2683, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2685 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2686 = and(_T_2684, _T_2685) @[lsu_bus_buffer.scala 412:104] + node _T_2687 = mux(_T_2682, UInt<1>("h00"), _T_2686) @[lsu_bus_buffer.scala 412:72] + node _T_2688 = eq(UInt<2>("h02"), UInt<1>("h01")) @[lsu_bus_buffer.scala 412:76] + node _T_2689 = bits(buf_age[2], 1, 1) @[lsu_bus_buffer.scala 412:100] + node _T_2690 = eq(_T_2689, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2691 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2692 = and(_T_2690, _T_2691) @[lsu_bus_buffer.scala 412:104] + node _T_2693 = mux(_T_2688, UInt<1>("h00"), _T_2692) @[lsu_bus_buffer.scala 412:72] + node _T_2694 = eq(UInt<2>("h02"), UInt<2>("h02")) @[lsu_bus_buffer.scala 412:76] + node _T_2695 = bits(buf_age[2], 2, 2) @[lsu_bus_buffer.scala 412:100] + node _T_2696 = eq(_T_2695, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2697 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2698 = and(_T_2696, _T_2697) @[lsu_bus_buffer.scala 412:104] + node _T_2699 = mux(_T_2694, UInt<1>("h00"), _T_2698) @[lsu_bus_buffer.scala 412:72] + node _T_2700 = eq(UInt<2>("h02"), UInt<2>("h03")) @[lsu_bus_buffer.scala 412:76] + node _T_2701 = bits(buf_age[2], 3, 3) @[lsu_bus_buffer.scala 412:100] + node _T_2702 = eq(_T_2701, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2703 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2704 = and(_T_2702, _T_2703) @[lsu_bus_buffer.scala 412:104] + node _T_2705 = mux(_T_2700, UInt<1>("h00"), _T_2704) @[lsu_bus_buffer.scala 412:72] node _T_2706 = cat(_T_2705, _T_2699) @[Cat.scala 29:58] node _T_2707 = cat(_T_2706, _T_2693) @[Cat.scala 29:58] node _T_2708 = cat(_T_2707, _T_2687) @[Cat.scala 29:58] - node _T_2709 = eq(UInt<2>("h03"), UInt<1>("h00")) @[lsu_bus_buffer.scala 413:76] - node _T_2710 = bits(buf_age[3], 0, 0) @[lsu_bus_buffer.scala 413:100] - node _T_2711 = eq(_T_2710, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] - node _T_2712 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] - node _T_2713 = and(_T_2711, _T_2712) @[lsu_bus_buffer.scala 413:104] - node _T_2714 = mux(_T_2709, UInt<1>("h00"), _T_2713) @[lsu_bus_buffer.scala 413:72] - node _T_2715 = eq(UInt<2>("h03"), UInt<1>("h01")) @[lsu_bus_buffer.scala 413:76] - node _T_2716 = bits(buf_age[3], 1, 1) @[lsu_bus_buffer.scala 413:100] - node _T_2717 = eq(_T_2716, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] - node _T_2718 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] - node _T_2719 = and(_T_2717, _T_2718) @[lsu_bus_buffer.scala 413:104] - node _T_2720 = mux(_T_2715, UInt<1>("h00"), _T_2719) @[lsu_bus_buffer.scala 413:72] - node _T_2721 = eq(UInt<2>("h03"), UInt<2>("h02")) @[lsu_bus_buffer.scala 413:76] - node _T_2722 = bits(buf_age[3], 2, 2) @[lsu_bus_buffer.scala 413:100] - node _T_2723 = eq(_T_2722, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] - node _T_2724 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] - node _T_2725 = and(_T_2723, _T_2724) @[lsu_bus_buffer.scala 413:104] - node _T_2726 = mux(_T_2721, UInt<1>("h00"), _T_2725) @[lsu_bus_buffer.scala 413:72] - node _T_2727 = eq(UInt<2>("h03"), UInt<2>("h03")) @[lsu_bus_buffer.scala 413:76] - node _T_2728 = bits(buf_age[3], 3, 3) @[lsu_bus_buffer.scala 413:100] - node _T_2729 = eq(_T_2728, UInt<1>("h00")) @[lsu_bus_buffer.scala 413:89] - node _T_2730 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 413:119] - node _T_2731 = and(_T_2729, _T_2730) @[lsu_bus_buffer.scala 413:104] - node _T_2732 = mux(_T_2727, UInt<1>("h00"), _T_2731) @[lsu_bus_buffer.scala 413:72] + node _T_2709 = eq(UInt<2>("h03"), UInt<1>("h00")) @[lsu_bus_buffer.scala 412:76] + node _T_2710 = bits(buf_age[3], 0, 0) @[lsu_bus_buffer.scala 412:100] + node _T_2711 = eq(_T_2710, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2712 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2713 = and(_T_2711, _T_2712) @[lsu_bus_buffer.scala 412:104] + node _T_2714 = mux(_T_2709, UInt<1>("h00"), _T_2713) @[lsu_bus_buffer.scala 412:72] + node _T_2715 = eq(UInt<2>("h03"), UInt<1>("h01")) @[lsu_bus_buffer.scala 412:76] + node _T_2716 = bits(buf_age[3], 1, 1) @[lsu_bus_buffer.scala 412:100] + node _T_2717 = eq(_T_2716, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2718 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2719 = and(_T_2717, _T_2718) @[lsu_bus_buffer.scala 412:104] + node _T_2720 = mux(_T_2715, UInt<1>("h00"), _T_2719) @[lsu_bus_buffer.scala 412:72] + node _T_2721 = eq(UInt<2>("h03"), UInt<2>("h02")) @[lsu_bus_buffer.scala 412:76] + node _T_2722 = bits(buf_age[3], 2, 2) @[lsu_bus_buffer.scala 412:100] + node _T_2723 = eq(_T_2722, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2724 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2725 = and(_T_2723, _T_2724) @[lsu_bus_buffer.scala 412:104] + node _T_2726 = mux(_T_2721, UInt<1>("h00"), _T_2725) @[lsu_bus_buffer.scala 412:72] + node _T_2727 = eq(UInt<2>("h03"), UInt<2>("h03")) @[lsu_bus_buffer.scala 412:76] + node _T_2728 = bits(buf_age[3], 3, 3) @[lsu_bus_buffer.scala 412:100] + node _T_2729 = eq(_T_2728, UInt<1>("h00")) @[lsu_bus_buffer.scala 412:89] + node _T_2730 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 412:119] + node _T_2731 = and(_T_2729, _T_2730) @[lsu_bus_buffer.scala 412:104] + node _T_2732 = mux(_T_2727, UInt<1>("h00"), _T_2731) @[lsu_bus_buffer.scala 412:72] node _T_2733 = cat(_T_2732, _T_2726) @[Cat.scala 29:58] node _T_2734 = cat(_T_2733, _T_2720) @[Cat.scala 29:58] node _T_2735 = cat(_T_2734, _T_2714) @[Cat.scala 29:58] - buf_age_younger[0] <= _T_2654 @[lsu_bus_buffer.scala 413:19] - buf_age_younger[1] <= _T_2681 @[lsu_bus_buffer.scala 413:19] - buf_age_younger[2] <= _T_2708 @[lsu_bus_buffer.scala 413:19] - buf_age_younger[3] <= _T_2735 @[lsu_bus_buffer.scala 413:19] - node _T_2736 = bits(buf_rspageQ[0], 0, 0) @[lsu_bus_buffer.scala 414:83] - node _T_2737 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] - node _T_2738 = and(_T_2736, _T_2737) @[lsu_bus_buffer.scala 414:87] - node _T_2739 = bits(buf_rspageQ[0], 1, 1) @[lsu_bus_buffer.scala 414:83] - node _T_2740 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] - node _T_2741 = and(_T_2739, _T_2740) @[lsu_bus_buffer.scala 414:87] - node _T_2742 = bits(buf_rspageQ[0], 2, 2) @[lsu_bus_buffer.scala 414:83] - node _T_2743 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] - node _T_2744 = and(_T_2742, _T_2743) @[lsu_bus_buffer.scala 414:87] - node _T_2745 = bits(buf_rspageQ[0], 3, 3) @[lsu_bus_buffer.scala 414:83] - node _T_2746 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] - node _T_2747 = and(_T_2745, _T_2746) @[lsu_bus_buffer.scala 414:87] + buf_age_younger[0] <= _T_2654 @[lsu_bus_buffer.scala 412:19] + buf_age_younger[1] <= _T_2681 @[lsu_bus_buffer.scala 412:19] + buf_age_younger[2] <= _T_2708 @[lsu_bus_buffer.scala 412:19] + buf_age_younger[3] <= _T_2735 @[lsu_bus_buffer.scala 412:19] + node _T_2736 = bits(buf_rspageQ[0], 0, 0) @[lsu_bus_buffer.scala 413:83] + node _T_2737 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2738 = and(_T_2736, _T_2737) @[lsu_bus_buffer.scala 413:87] + node _T_2739 = bits(buf_rspageQ[0], 1, 1) @[lsu_bus_buffer.scala 413:83] + node _T_2740 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2741 = and(_T_2739, _T_2740) @[lsu_bus_buffer.scala 413:87] + node _T_2742 = bits(buf_rspageQ[0], 2, 2) @[lsu_bus_buffer.scala 413:83] + node _T_2743 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2744 = and(_T_2742, _T_2743) @[lsu_bus_buffer.scala 413:87] + node _T_2745 = bits(buf_rspageQ[0], 3, 3) @[lsu_bus_buffer.scala 413:83] + node _T_2746 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2747 = and(_T_2745, _T_2746) @[lsu_bus_buffer.scala 413:87] node _T_2748 = cat(_T_2747, _T_2744) @[Cat.scala 29:58] node _T_2749 = cat(_T_2748, _T_2741) @[Cat.scala 29:58] node _T_2750 = cat(_T_2749, _T_2738) @[Cat.scala 29:58] - node _T_2751 = bits(buf_rspageQ[1], 0, 0) @[lsu_bus_buffer.scala 414:83] - node _T_2752 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] - node _T_2753 = and(_T_2751, _T_2752) @[lsu_bus_buffer.scala 414:87] - node _T_2754 = bits(buf_rspageQ[1], 1, 1) @[lsu_bus_buffer.scala 414:83] - node _T_2755 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] - node _T_2756 = and(_T_2754, _T_2755) @[lsu_bus_buffer.scala 414:87] - node _T_2757 = bits(buf_rspageQ[1], 2, 2) @[lsu_bus_buffer.scala 414:83] - node _T_2758 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] - node _T_2759 = and(_T_2757, _T_2758) @[lsu_bus_buffer.scala 414:87] - node _T_2760 = bits(buf_rspageQ[1], 3, 3) @[lsu_bus_buffer.scala 414:83] - node _T_2761 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] - node _T_2762 = and(_T_2760, _T_2761) @[lsu_bus_buffer.scala 414:87] + node _T_2751 = bits(buf_rspageQ[1], 0, 0) @[lsu_bus_buffer.scala 413:83] + node _T_2752 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2753 = and(_T_2751, _T_2752) @[lsu_bus_buffer.scala 413:87] + node _T_2754 = bits(buf_rspageQ[1], 1, 1) @[lsu_bus_buffer.scala 413:83] + node _T_2755 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2756 = and(_T_2754, _T_2755) @[lsu_bus_buffer.scala 413:87] + node _T_2757 = bits(buf_rspageQ[1], 2, 2) @[lsu_bus_buffer.scala 413:83] + node _T_2758 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2759 = and(_T_2757, _T_2758) @[lsu_bus_buffer.scala 413:87] + node _T_2760 = bits(buf_rspageQ[1], 3, 3) @[lsu_bus_buffer.scala 413:83] + node _T_2761 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2762 = and(_T_2760, _T_2761) @[lsu_bus_buffer.scala 413:87] node _T_2763 = cat(_T_2762, _T_2759) @[Cat.scala 29:58] node _T_2764 = cat(_T_2763, _T_2756) @[Cat.scala 29:58] node _T_2765 = cat(_T_2764, _T_2753) @[Cat.scala 29:58] - node _T_2766 = bits(buf_rspageQ[2], 0, 0) @[lsu_bus_buffer.scala 414:83] - node _T_2767 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] - node _T_2768 = and(_T_2766, _T_2767) @[lsu_bus_buffer.scala 414:87] - node _T_2769 = bits(buf_rspageQ[2], 1, 1) @[lsu_bus_buffer.scala 414:83] - node _T_2770 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] - node _T_2771 = and(_T_2769, _T_2770) @[lsu_bus_buffer.scala 414:87] - node _T_2772 = bits(buf_rspageQ[2], 2, 2) @[lsu_bus_buffer.scala 414:83] - node _T_2773 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] - node _T_2774 = and(_T_2772, _T_2773) @[lsu_bus_buffer.scala 414:87] - node _T_2775 = bits(buf_rspageQ[2], 3, 3) @[lsu_bus_buffer.scala 414:83] - node _T_2776 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] - node _T_2777 = and(_T_2775, _T_2776) @[lsu_bus_buffer.scala 414:87] + node _T_2766 = bits(buf_rspageQ[2], 0, 0) @[lsu_bus_buffer.scala 413:83] + node _T_2767 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2768 = and(_T_2766, _T_2767) @[lsu_bus_buffer.scala 413:87] + node _T_2769 = bits(buf_rspageQ[2], 1, 1) @[lsu_bus_buffer.scala 413:83] + node _T_2770 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2771 = and(_T_2769, _T_2770) @[lsu_bus_buffer.scala 413:87] + node _T_2772 = bits(buf_rspageQ[2], 2, 2) @[lsu_bus_buffer.scala 413:83] + node _T_2773 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2774 = and(_T_2772, _T_2773) @[lsu_bus_buffer.scala 413:87] + node _T_2775 = bits(buf_rspageQ[2], 3, 3) @[lsu_bus_buffer.scala 413:83] + node _T_2776 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2777 = and(_T_2775, _T_2776) @[lsu_bus_buffer.scala 413:87] node _T_2778 = cat(_T_2777, _T_2774) @[Cat.scala 29:58] node _T_2779 = cat(_T_2778, _T_2771) @[Cat.scala 29:58] node _T_2780 = cat(_T_2779, _T_2768) @[Cat.scala 29:58] - node _T_2781 = bits(buf_rspageQ[3], 0, 0) @[lsu_bus_buffer.scala 414:83] - node _T_2782 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] - node _T_2783 = and(_T_2781, _T_2782) @[lsu_bus_buffer.scala 414:87] - node _T_2784 = bits(buf_rspageQ[3], 1, 1) @[lsu_bus_buffer.scala 414:83] - node _T_2785 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] - node _T_2786 = and(_T_2784, _T_2785) @[lsu_bus_buffer.scala 414:87] - node _T_2787 = bits(buf_rspageQ[3], 2, 2) @[lsu_bus_buffer.scala 414:83] - node _T_2788 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] - node _T_2789 = and(_T_2787, _T_2788) @[lsu_bus_buffer.scala 414:87] - node _T_2790 = bits(buf_rspageQ[3], 3, 3) @[lsu_bus_buffer.scala 414:83] - node _T_2791 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 414:102] - node _T_2792 = and(_T_2790, _T_2791) @[lsu_bus_buffer.scala 414:87] + node _T_2781 = bits(buf_rspageQ[3], 0, 0) @[lsu_bus_buffer.scala 413:83] + node _T_2782 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2783 = and(_T_2781, _T_2782) @[lsu_bus_buffer.scala 413:87] + node _T_2784 = bits(buf_rspageQ[3], 1, 1) @[lsu_bus_buffer.scala 413:83] + node _T_2785 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2786 = and(_T_2784, _T_2785) @[lsu_bus_buffer.scala 413:87] + node _T_2787 = bits(buf_rspageQ[3], 2, 2) @[lsu_bus_buffer.scala 413:83] + node _T_2788 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2789 = and(_T_2787, _T_2788) @[lsu_bus_buffer.scala 413:87] + node _T_2790 = bits(buf_rspageQ[3], 3, 3) @[lsu_bus_buffer.scala 413:83] + node _T_2791 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 413:102] + node _T_2792 = and(_T_2790, _T_2791) @[lsu_bus_buffer.scala 413:87] node _T_2793 = cat(_T_2792, _T_2789) @[Cat.scala 29:58] node _T_2794 = cat(_T_2793, _T_2786) @[Cat.scala 29:58] node _T_2795 = cat(_T_2794, _T_2783) @[Cat.scala 29:58] - buf_rsp_pickage[0] <= _T_2750 @[lsu_bus_buffer.scala 414:19] - buf_rsp_pickage[1] <= _T_2765 @[lsu_bus_buffer.scala 414:19] - buf_rsp_pickage[2] <= _T_2780 @[lsu_bus_buffer.scala 414:19] - buf_rsp_pickage[3] <= _T_2795 @[lsu_bus_buffer.scala 414:19] - node _T_2796 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] - node _T_2797 = and(_T_2796, buf_state_en[0]) @[lsu_bus_buffer.scala 416:93] - node _T_2798 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] - node _T_2799 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] - node _T_2800 = or(_T_2798, _T_2799) @[lsu_bus_buffer.scala 417:32] - node _T_2801 = eq(_T_2800, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] - node _T_2802 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] - node _T_2803 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] - node _T_2804 = and(_T_2802, _T_2803) @[lsu_bus_buffer.scala 418:41] - node _T_2805 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:82] - node _T_2806 = and(_T_2804, _T_2805) @[lsu_bus_buffer.scala 418:71] - node _T_2807 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:101] - node _T_2808 = and(_T_2806, _T_2807) @[lsu_bus_buffer.scala 418:90] - node _T_2809 = or(_T_2801, _T_2808) @[lsu_bus_buffer.scala 417:59] - node _T_2810 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] - node _T_2811 = and(_T_2810, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] - node _T_2812 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:63] - node _T_2813 = and(_T_2811, _T_2812) @[lsu_bus_buffer.scala 419:52] - node _T_2814 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:82] - node _T_2815 = and(_T_2813, _T_2814) @[lsu_bus_buffer.scala 419:71] - node _T_2816 = or(_T_2809, _T_2815) @[lsu_bus_buffer.scala 418:110] - node _T_2817 = and(_T_2797, _T_2816) @[lsu_bus_buffer.scala 416:112] - node _T_2818 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] - node _T_2819 = and(_T_2818, buf_state_en[0]) @[lsu_bus_buffer.scala 416:93] - node _T_2820 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] - node _T_2821 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] - node _T_2822 = or(_T_2820, _T_2821) @[lsu_bus_buffer.scala 417:32] - node _T_2823 = eq(_T_2822, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] - node _T_2824 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] - node _T_2825 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] - node _T_2826 = and(_T_2824, _T_2825) @[lsu_bus_buffer.scala 418:41] - node _T_2827 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:82] - node _T_2828 = and(_T_2826, _T_2827) @[lsu_bus_buffer.scala 418:71] - node _T_2829 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:101] - node _T_2830 = and(_T_2828, _T_2829) @[lsu_bus_buffer.scala 418:90] - node _T_2831 = or(_T_2823, _T_2830) @[lsu_bus_buffer.scala 417:59] - node _T_2832 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] - node _T_2833 = and(_T_2832, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] - node _T_2834 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:63] - node _T_2835 = and(_T_2833, _T_2834) @[lsu_bus_buffer.scala 419:52] - node _T_2836 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 419:82] - node _T_2837 = and(_T_2835, _T_2836) @[lsu_bus_buffer.scala 419:71] - node _T_2838 = or(_T_2831, _T_2837) @[lsu_bus_buffer.scala 418:110] - node _T_2839 = and(_T_2819, _T_2838) @[lsu_bus_buffer.scala 416:112] - node _T_2840 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] - node _T_2841 = and(_T_2840, buf_state_en[0]) @[lsu_bus_buffer.scala 416:93] - node _T_2842 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] - node _T_2843 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] - node _T_2844 = or(_T_2842, _T_2843) @[lsu_bus_buffer.scala 417:32] - node _T_2845 = eq(_T_2844, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] - node _T_2846 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] - node _T_2847 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] - node _T_2848 = and(_T_2846, _T_2847) @[lsu_bus_buffer.scala 418:41] - node _T_2849 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:82] - node _T_2850 = and(_T_2848, _T_2849) @[lsu_bus_buffer.scala 418:71] - node _T_2851 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:101] - node _T_2852 = and(_T_2850, _T_2851) @[lsu_bus_buffer.scala 418:90] - node _T_2853 = or(_T_2845, _T_2852) @[lsu_bus_buffer.scala 417:59] - node _T_2854 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] - node _T_2855 = and(_T_2854, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] - node _T_2856 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:63] - node _T_2857 = and(_T_2855, _T_2856) @[lsu_bus_buffer.scala 419:52] - node _T_2858 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 419:82] - node _T_2859 = and(_T_2857, _T_2858) @[lsu_bus_buffer.scala 419:71] - node _T_2860 = or(_T_2853, _T_2859) @[lsu_bus_buffer.scala 418:110] - node _T_2861 = and(_T_2841, _T_2860) @[lsu_bus_buffer.scala 416:112] - node _T_2862 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] - node _T_2863 = and(_T_2862, buf_state_en[0]) @[lsu_bus_buffer.scala 416:93] - node _T_2864 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] - node _T_2865 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] - node _T_2866 = or(_T_2864, _T_2865) @[lsu_bus_buffer.scala 417:32] - node _T_2867 = eq(_T_2866, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] - node _T_2868 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] - node _T_2869 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] - node _T_2870 = and(_T_2868, _T_2869) @[lsu_bus_buffer.scala 418:41] - node _T_2871 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:82] - node _T_2872 = and(_T_2870, _T_2871) @[lsu_bus_buffer.scala 418:71] - node _T_2873 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:101] - node _T_2874 = and(_T_2872, _T_2873) @[lsu_bus_buffer.scala 418:90] - node _T_2875 = or(_T_2867, _T_2874) @[lsu_bus_buffer.scala 417:59] - node _T_2876 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] - node _T_2877 = and(_T_2876, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] - node _T_2878 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:63] - node _T_2879 = and(_T_2877, _T_2878) @[lsu_bus_buffer.scala 419:52] - node _T_2880 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 419:82] - node _T_2881 = and(_T_2879, _T_2880) @[lsu_bus_buffer.scala 419:71] - node _T_2882 = or(_T_2875, _T_2881) @[lsu_bus_buffer.scala 418:110] - node _T_2883 = and(_T_2863, _T_2882) @[lsu_bus_buffer.scala 416:112] + buf_rsp_pickage[0] <= _T_2750 @[lsu_bus_buffer.scala 413:19] + buf_rsp_pickage[1] <= _T_2765 @[lsu_bus_buffer.scala 413:19] + buf_rsp_pickage[2] <= _T_2780 @[lsu_bus_buffer.scala 413:19] + buf_rsp_pickage[3] <= _T_2795 @[lsu_bus_buffer.scala 413:19] + node _T_2796 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_2797 = and(_T_2796, buf_state_en[0]) @[lsu_bus_buffer.scala 415:93] + node _T_2798 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_2799 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_2800 = or(_T_2798, _T_2799) @[lsu_bus_buffer.scala 416:32] + node _T_2801 = eq(_T_2800, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_2802 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_2803 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_2804 = and(_T_2802, _T_2803) @[lsu_bus_buffer.scala 417:41] + node _T_2805 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:82] + node _T_2806 = and(_T_2804, _T_2805) @[lsu_bus_buffer.scala 417:71] + node _T_2807 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:101] + node _T_2808 = and(_T_2806, _T_2807) @[lsu_bus_buffer.scala 417:90] + node _T_2809 = or(_T_2801, _T_2808) @[lsu_bus_buffer.scala 416:59] + node _T_2810 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_2811 = and(_T_2810, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_2812 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:63] + node _T_2813 = and(_T_2811, _T_2812) @[lsu_bus_buffer.scala 418:52] + node _T_2814 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:82] + node _T_2815 = and(_T_2813, _T_2814) @[lsu_bus_buffer.scala 418:71] + node _T_2816 = or(_T_2809, _T_2815) @[lsu_bus_buffer.scala 417:110] + node _T_2817 = and(_T_2797, _T_2816) @[lsu_bus_buffer.scala 415:112] + node _T_2818 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_2819 = and(_T_2818, buf_state_en[0]) @[lsu_bus_buffer.scala 415:93] + node _T_2820 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_2821 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_2822 = or(_T_2820, _T_2821) @[lsu_bus_buffer.scala 416:32] + node _T_2823 = eq(_T_2822, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_2824 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_2825 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_2826 = and(_T_2824, _T_2825) @[lsu_bus_buffer.scala 417:41] + node _T_2827 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:82] + node _T_2828 = and(_T_2826, _T_2827) @[lsu_bus_buffer.scala 417:71] + node _T_2829 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 417:101] + node _T_2830 = and(_T_2828, _T_2829) @[lsu_bus_buffer.scala 417:90] + node _T_2831 = or(_T_2823, _T_2830) @[lsu_bus_buffer.scala 416:59] + node _T_2832 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_2833 = and(_T_2832, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_2834 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:63] + node _T_2835 = and(_T_2833, _T_2834) @[lsu_bus_buffer.scala 418:52] + node _T_2836 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:82] + node _T_2837 = and(_T_2835, _T_2836) @[lsu_bus_buffer.scala 418:71] + node _T_2838 = or(_T_2831, _T_2837) @[lsu_bus_buffer.scala 417:110] + node _T_2839 = and(_T_2819, _T_2838) @[lsu_bus_buffer.scala 415:112] + node _T_2840 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_2841 = and(_T_2840, buf_state_en[0]) @[lsu_bus_buffer.scala 415:93] + node _T_2842 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_2843 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_2844 = or(_T_2842, _T_2843) @[lsu_bus_buffer.scala 416:32] + node _T_2845 = eq(_T_2844, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_2846 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_2847 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_2848 = and(_T_2846, _T_2847) @[lsu_bus_buffer.scala 417:41] + node _T_2849 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:82] + node _T_2850 = and(_T_2848, _T_2849) @[lsu_bus_buffer.scala 417:71] + node _T_2851 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 417:101] + node _T_2852 = and(_T_2850, _T_2851) @[lsu_bus_buffer.scala 417:90] + node _T_2853 = or(_T_2845, _T_2852) @[lsu_bus_buffer.scala 416:59] + node _T_2854 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_2855 = and(_T_2854, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_2856 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:63] + node _T_2857 = and(_T_2855, _T_2856) @[lsu_bus_buffer.scala 418:52] + node _T_2858 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:82] + node _T_2859 = and(_T_2857, _T_2858) @[lsu_bus_buffer.scala 418:71] + node _T_2860 = or(_T_2853, _T_2859) @[lsu_bus_buffer.scala 417:110] + node _T_2861 = and(_T_2841, _T_2860) @[lsu_bus_buffer.scala 415:112] + node _T_2862 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_2863 = and(_T_2862, buf_state_en[0]) @[lsu_bus_buffer.scala 415:93] + node _T_2864 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_2865 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_2866 = or(_T_2864, _T_2865) @[lsu_bus_buffer.scala 416:32] + node _T_2867 = eq(_T_2866, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_2868 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_2869 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_2870 = and(_T_2868, _T_2869) @[lsu_bus_buffer.scala 417:41] + node _T_2871 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:82] + node _T_2872 = and(_T_2870, _T_2871) @[lsu_bus_buffer.scala 417:71] + node _T_2873 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 417:101] + node _T_2874 = and(_T_2872, _T_2873) @[lsu_bus_buffer.scala 417:90] + node _T_2875 = or(_T_2867, _T_2874) @[lsu_bus_buffer.scala 416:59] + node _T_2876 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_2877 = and(_T_2876, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_2878 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:63] + node _T_2879 = and(_T_2877, _T_2878) @[lsu_bus_buffer.scala 418:52] + node _T_2880 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:82] + node _T_2881 = and(_T_2879, _T_2880) @[lsu_bus_buffer.scala 418:71] + node _T_2882 = or(_T_2875, _T_2881) @[lsu_bus_buffer.scala 417:110] + node _T_2883 = and(_T_2863, _T_2882) @[lsu_bus_buffer.scala 415:112] node _T_2884 = cat(_T_2883, _T_2861) @[Cat.scala 29:58] node _T_2885 = cat(_T_2884, _T_2839) @[Cat.scala 29:58] node _T_2886 = cat(_T_2885, _T_2817) @[Cat.scala 29:58] - node _T_2887 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] - node _T_2888 = and(_T_2887, buf_state_en[1]) @[lsu_bus_buffer.scala 416:93] - node _T_2889 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] - node _T_2890 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] - node _T_2891 = or(_T_2889, _T_2890) @[lsu_bus_buffer.scala 417:32] - node _T_2892 = eq(_T_2891, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] - node _T_2893 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] - node _T_2894 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] - node _T_2895 = and(_T_2893, _T_2894) @[lsu_bus_buffer.scala 418:41] - node _T_2896 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:82] - node _T_2897 = and(_T_2895, _T_2896) @[lsu_bus_buffer.scala 418:71] - node _T_2898 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:101] - node _T_2899 = and(_T_2897, _T_2898) @[lsu_bus_buffer.scala 418:90] - node _T_2900 = or(_T_2892, _T_2899) @[lsu_bus_buffer.scala 417:59] - node _T_2901 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] - node _T_2902 = and(_T_2901, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] - node _T_2903 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 419:63] - node _T_2904 = and(_T_2902, _T_2903) @[lsu_bus_buffer.scala 419:52] - node _T_2905 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:82] - node _T_2906 = and(_T_2904, _T_2905) @[lsu_bus_buffer.scala 419:71] - node _T_2907 = or(_T_2900, _T_2906) @[lsu_bus_buffer.scala 418:110] - node _T_2908 = and(_T_2888, _T_2907) @[lsu_bus_buffer.scala 416:112] - node _T_2909 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] - node _T_2910 = and(_T_2909, buf_state_en[1]) @[lsu_bus_buffer.scala 416:93] - node _T_2911 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] - node _T_2912 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] - node _T_2913 = or(_T_2911, _T_2912) @[lsu_bus_buffer.scala 417:32] - node _T_2914 = eq(_T_2913, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] - node _T_2915 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] - node _T_2916 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] - node _T_2917 = and(_T_2915, _T_2916) @[lsu_bus_buffer.scala 418:41] - node _T_2918 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:82] - node _T_2919 = and(_T_2917, _T_2918) @[lsu_bus_buffer.scala 418:71] - node _T_2920 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:101] - node _T_2921 = and(_T_2919, _T_2920) @[lsu_bus_buffer.scala 418:90] - node _T_2922 = or(_T_2914, _T_2921) @[lsu_bus_buffer.scala 417:59] - node _T_2923 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] - node _T_2924 = and(_T_2923, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] - node _T_2925 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 419:63] - node _T_2926 = and(_T_2924, _T_2925) @[lsu_bus_buffer.scala 419:52] - node _T_2927 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 419:82] - node _T_2928 = and(_T_2926, _T_2927) @[lsu_bus_buffer.scala 419:71] - node _T_2929 = or(_T_2922, _T_2928) @[lsu_bus_buffer.scala 418:110] - node _T_2930 = and(_T_2910, _T_2929) @[lsu_bus_buffer.scala 416:112] - node _T_2931 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] - node _T_2932 = and(_T_2931, buf_state_en[1]) @[lsu_bus_buffer.scala 416:93] - node _T_2933 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] - node _T_2934 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] - node _T_2935 = or(_T_2933, _T_2934) @[lsu_bus_buffer.scala 417:32] - node _T_2936 = eq(_T_2935, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] - node _T_2937 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] - node _T_2938 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] - node _T_2939 = and(_T_2937, _T_2938) @[lsu_bus_buffer.scala 418:41] - node _T_2940 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:82] - node _T_2941 = and(_T_2939, _T_2940) @[lsu_bus_buffer.scala 418:71] - node _T_2942 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:101] - node _T_2943 = and(_T_2941, _T_2942) @[lsu_bus_buffer.scala 418:90] - node _T_2944 = or(_T_2936, _T_2943) @[lsu_bus_buffer.scala 417:59] - node _T_2945 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] - node _T_2946 = and(_T_2945, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] - node _T_2947 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 419:63] - node _T_2948 = and(_T_2946, _T_2947) @[lsu_bus_buffer.scala 419:52] - node _T_2949 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 419:82] - node _T_2950 = and(_T_2948, _T_2949) @[lsu_bus_buffer.scala 419:71] - node _T_2951 = or(_T_2944, _T_2950) @[lsu_bus_buffer.scala 418:110] - node _T_2952 = and(_T_2932, _T_2951) @[lsu_bus_buffer.scala 416:112] - node _T_2953 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] - node _T_2954 = and(_T_2953, buf_state_en[1]) @[lsu_bus_buffer.scala 416:93] - node _T_2955 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] - node _T_2956 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] - node _T_2957 = or(_T_2955, _T_2956) @[lsu_bus_buffer.scala 417:32] - node _T_2958 = eq(_T_2957, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] - node _T_2959 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] - node _T_2960 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] - node _T_2961 = and(_T_2959, _T_2960) @[lsu_bus_buffer.scala 418:41] - node _T_2962 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:82] - node _T_2963 = and(_T_2961, _T_2962) @[lsu_bus_buffer.scala 418:71] - node _T_2964 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:101] - node _T_2965 = and(_T_2963, _T_2964) @[lsu_bus_buffer.scala 418:90] - node _T_2966 = or(_T_2958, _T_2965) @[lsu_bus_buffer.scala 417:59] - node _T_2967 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] - node _T_2968 = and(_T_2967, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] - node _T_2969 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 419:63] - node _T_2970 = and(_T_2968, _T_2969) @[lsu_bus_buffer.scala 419:52] - node _T_2971 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 419:82] - node _T_2972 = and(_T_2970, _T_2971) @[lsu_bus_buffer.scala 419:71] - node _T_2973 = or(_T_2966, _T_2972) @[lsu_bus_buffer.scala 418:110] - node _T_2974 = and(_T_2954, _T_2973) @[lsu_bus_buffer.scala 416:112] + node _T_2887 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_2888 = and(_T_2887, buf_state_en[1]) @[lsu_bus_buffer.scala 415:93] + node _T_2889 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_2890 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_2891 = or(_T_2889, _T_2890) @[lsu_bus_buffer.scala 416:32] + node _T_2892 = eq(_T_2891, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_2893 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_2894 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_2895 = and(_T_2893, _T_2894) @[lsu_bus_buffer.scala 417:41] + node _T_2896 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 417:82] + node _T_2897 = and(_T_2895, _T_2896) @[lsu_bus_buffer.scala 417:71] + node _T_2898 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:101] + node _T_2899 = and(_T_2897, _T_2898) @[lsu_bus_buffer.scala 417:90] + node _T_2900 = or(_T_2892, _T_2899) @[lsu_bus_buffer.scala 416:59] + node _T_2901 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_2902 = and(_T_2901, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_2903 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:63] + node _T_2904 = and(_T_2902, _T_2903) @[lsu_bus_buffer.scala 418:52] + node _T_2905 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:82] + node _T_2906 = and(_T_2904, _T_2905) @[lsu_bus_buffer.scala 418:71] + node _T_2907 = or(_T_2900, _T_2906) @[lsu_bus_buffer.scala 417:110] + node _T_2908 = and(_T_2888, _T_2907) @[lsu_bus_buffer.scala 415:112] + node _T_2909 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_2910 = and(_T_2909, buf_state_en[1]) @[lsu_bus_buffer.scala 415:93] + node _T_2911 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_2912 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_2913 = or(_T_2911, _T_2912) @[lsu_bus_buffer.scala 416:32] + node _T_2914 = eq(_T_2913, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_2915 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_2916 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_2917 = and(_T_2915, _T_2916) @[lsu_bus_buffer.scala 417:41] + node _T_2918 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 417:82] + node _T_2919 = and(_T_2917, _T_2918) @[lsu_bus_buffer.scala 417:71] + node _T_2920 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 417:101] + node _T_2921 = and(_T_2919, _T_2920) @[lsu_bus_buffer.scala 417:90] + node _T_2922 = or(_T_2914, _T_2921) @[lsu_bus_buffer.scala 416:59] + node _T_2923 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_2924 = and(_T_2923, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_2925 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:63] + node _T_2926 = and(_T_2924, _T_2925) @[lsu_bus_buffer.scala 418:52] + node _T_2927 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:82] + node _T_2928 = and(_T_2926, _T_2927) @[lsu_bus_buffer.scala 418:71] + node _T_2929 = or(_T_2922, _T_2928) @[lsu_bus_buffer.scala 417:110] + node _T_2930 = and(_T_2910, _T_2929) @[lsu_bus_buffer.scala 415:112] + node _T_2931 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_2932 = and(_T_2931, buf_state_en[1]) @[lsu_bus_buffer.scala 415:93] + node _T_2933 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_2934 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_2935 = or(_T_2933, _T_2934) @[lsu_bus_buffer.scala 416:32] + node _T_2936 = eq(_T_2935, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_2937 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_2938 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_2939 = and(_T_2937, _T_2938) @[lsu_bus_buffer.scala 417:41] + node _T_2940 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 417:82] + node _T_2941 = and(_T_2939, _T_2940) @[lsu_bus_buffer.scala 417:71] + node _T_2942 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 417:101] + node _T_2943 = and(_T_2941, _T_2942) @[lsu_bus_buffer.scala 417:90] + node _T_2944 = or(_T_2936, _T_2943) @[lsu_bus_buffer.scala 416:59] + node _T_2945 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_2946 = and(_T_2945, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_2947 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:63] + node _T_2948 = and(_T_2946, _T_2947) @[lsu_bus_buffer.scala 418:52] + node _T_2949 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:82] + node _T_2950 = and(_T_2948, _T_2949) @[lsu_bus_buffer.scala 418:71] + node _T_2951 = or(_T_2944, _T_2950) @[lsu_bus_buffer.scala 417:110] + node _T_2952 = and(_T_2932, _T_2951) @[lsu_bus_buffer.scala 415:112] + node _T_2953 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_2954 = and(_T_2953, buf_state_en[1]) @[lsu_bus_buffer.scala 415:93] + node _T_2955 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_2956 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_2957 = or(_T_2955, _T_2956) @[lsu_bus_buffer.scala 416:32] + node _T_2958 = eq(_T_2957, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_2959 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_2960 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_2961 = and(_T_2959, _T_2960) @[lsu_bus_buffer.scala 417:41] + node _T_2962 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 417:82] + node _T_2963 = and(_T_2961, _T_2962) @[lsu_bus_buffer.scala 417:71] + node _T_2964 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 417:101] + node _T_2965 = and(_T_2963, _T_2964) @[lsu_bus_buffer.scala 417:90] + node _T_2966 = or(_T_2958, _T_2965) @[lsu_bus_buffer.scala 416:59] + node _T_2967 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_2968 = and(_T_2967, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_2969 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:63] + node _T_2970 = and(_T_2968, _T_2969) @[lsu_bus_buffer.scala 418:52] + node _T_2971 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:82] + node _T_2972 = and(_T_2970, _T_2971) @[lsu_bus_buffer.scala 418:71] + node _T_2973 = or(_T_2966, _T_2972) @[lsu_bus_buffer.scala 417:110] + node _T_2974 = and(_T_2954, _T_2973) @[lsu_bus_buffer.scala 415:112] node _T_2975 = cat(_T_2974, _T_2952) @[Cat.scala 29:58] node _T_2976 = cat(_T_2975, _T_2930) @[Cat.scala 29:58] node _T_2977 = cat(_T_2976, _T_2908) @[Cat.scala 29:58] - node _T_2978 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] - node _T_2979 = and(_T_2978, buf_state_en[2]) @[lsu_bus_buffer.scala 416:93] - node _T_2980 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] - node _T_2981 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] - node _T_2982 = or(_T_2980, _T_2981) @[lsu_bus_buffer.scala 417:32] - node _T_2983 = eq(_T_2982, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] - node _T_2984 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] - node _T_2985 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] - node _T_2986 = and(_T_2984, _T_2985) @[lsu_bus_buffer.scala 418:41] - node _T_2987 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:82] - node _T_2988 = and(_T_2986, _T_2987) @[lsu_bus_buffer.scala 418:71] - node _T_2989 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:101] - node _T_2990 = and(_T_2988, _T_2989) @[lsu_bus_buffer.scala 418:90] - node _T_2991 = or(_T_2983, _T_2990) @[lsu_bus_buffer.scala 417:59] - node _T_2992 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] - node _T_2993 = and(_T_2992, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] - node _T_2994 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 419:63] - node _T_2995 = and(_T_2993, _T_2994) @[lsu_bus_buffer.scala 419:52] - node _T_2996 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:82] - node _T_2997 = and(_T_2995, _T_2996) @[lsu_bus_buffer.scala 419:71] - node _T_2998 = or(_T_2991, _T_2997) @[lsu_bus_buffer.scala 418:110] - node _T_2999 = and(_T_2979, _T_2998) @[lsu_bus_buffer.scala 416:112] - node _T_3000 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] - node _T_3001 = and(_T_3000, buf_state_en[2]) @[lsu_bus_buffer.scala 416:93] - node _T_3002 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] - node _T_3003 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] - node _T_3004 = or(_T_3002, _T_3003) @[lsu_bus_buffer.scala 417:32] - node _T_3005 = eq(_T_3004, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] - node _T_3006 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] - node _T_3007 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] - node _T_3008 = and(_T_3006, _T_3007) @[lsu_bus_buffer.scala 418:41] - node _T_3009 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:82] - node _T_3010 = and(_T_3008, _T_3009) @[lsu_bus_buffer.scala 418:71] - node _T_3011 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:101] - node _T_3012 = and(_T_3010, _T_3011) @[lsu_bus_buffer.scala 418:90] - node _T_3013 = or(_T_3005, _T_3012) @[lsu_bus_buffer.scala 417:59] - node _T_3014 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] - node _T_3015 = and(_T_3014, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] - node _T_3016 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 419:63] - node _T_3017 = and(_T_3015, _T_3016) @[lsu_bus_buffer.scala 419:52] - node _T_3018 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 419:82] - node _T_3019 = and(_T_3017, _T_3018) @[lsu_bus_buffer.scala 419:71] - node _T_3020 = or(_T_3013, _T_3019) @[lsu_bus_buffer.scala 418:110] - node _T_3021 = and(_T_3001, _T_3020) @[lsu_bus_buffer.scala 416:112] - node _T_3022 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] - node _T_3023 = and(_T_3022, buf_state_en[2]) @[lsu_bus_buffer.scala 416:93] - node _T_3024 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] - node _T_3025 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] - node _T_3026 = or(_T_3024, _T_3025) @[lsu_bus_buffer.scala 417:32] - node _T_3027 = eq(_T_3026, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] - node _T_3028 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] - node _T_3029 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] - node _T_3030 = and(_T_3028, _T_3029) @[lsu_bus_buffer.scala 418:41] - node _T_3031 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:82] - node _T_3032 = and(_T_3030, _T_3031) @[lsu_bus_buffer.scala 418:71] - node _T_3033 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:101] - node _T_3034 = and(_T_3032, _T_3033) @[lsu_bus_buffer.scala 418:90] - node _T_3035 = or(_T_3027, _T_3034) @[lsu_bus_buffer.scala 417:59] - node _T_3036 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] - node _T_3037 = and(_T_3036, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] - node _T_3038 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 419:63] - node _T_3039 = and(_T_3037, _T_3038) @[lsu_bus_buffer.scala 419:52] - node _T_3040 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 419:82] - node _T_3041 = and(_T_3039, _T_3040) @[lsu_bus_buffer.scala 419:71] - node _T_3042 = or(_T_3035, _T_3041) @[lsu_bus_buffer.scala 418:110] - node _T_3043 = and(_T_3023, _T_3042) @[lsu_bus_buffer.scala 416:112] - node _T_3044 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] - node _T_3045 = and(_T_3044, buf_state_en[2]) @[lsu_bus_buffer.scala 416:93] - node _T_3046 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] - node _T_3047 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] - node _T_3048 = or(_T_3046, _T_3047) @[lsu_bus_buffer.scala 417:32] - node _T_3049 = eq(_T_3048, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] - node _T_3050 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] - node _T_3051 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] - node _T_3052 = and(_T_3050, _T_3051) @[lsu_bus_buffer.scala 418:41] - node _T_3053 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:82] - node _T_3054 = and(_T_3052, _T_3053) @[lsu_bus_buffer.scala 418:71] - node _T_3055 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:101] - node _T_3056 = and(_T_3054, _T_3055) @[lsu_bus_buffer.scala 418:90] - node _T_3057 = or(_T_3049, _T_3056) @[lsu_bus_buffer.scala 417:59] - node _T_3058 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] - node _T_3059 = and(_T_3058, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] - node _T_3060 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 419:63] - node _T_3061 = and(_T_3059, _T_3060) @[lsu_bus_buffer.scala 419:52] - node _T_3062 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 419:82] - node _T_3063 = and(_T_3061, _T_3062) @[lsu_bus_buffer.scala 419:71] - node _T_3064 = or(_T_3057, _T_3063) @[lsu_bus_buffer.scala 418:110] - node _T_3065 = and(_T_3045, _T_3064) @[lsu_bus_buffer.scala 416:112] + node _T_2978 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_2979 = and(_T_2978, buf_state_en[2]) @[lsu_bus_buffer.scala 415:93] + node _T_2980 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_2981 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_2982 = or(_T_2980, _T_2981) @[lsu_bus_buffer.scala 416:32] + node _T_2983 = eq(_T_2982, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_2984 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_2985 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_2986 = and(_T_2984, _T_2985) @[lsu_bus_buffer.scala 417:41] + node _T_2987 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 417:82] + node _T_2988 = and(_T_2986, _T_2987) @[lsu_bus_buffer.scala 417:71] + node _T_2989 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:101] + node _T_2990 = and(_T_2988, _T_2989) @[lsu_bus_buffer.scala 417:90] + node _T_2991 = or(_T_2983, _T_2990) @[lsu_bus_buffer.scala 416:59] + node _T_2992 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_2993 = and(_T_2992, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_2994 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:63] + node _T_2995 = and(_T_2993, _T_2994) @[lsu_bus_buffer.scala 418:52] + node _T_2996 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:82] + node _T_2997 = and(_T_2995, _T_2996) @[lsu_bus_buffer.scala 418:71] + node _T_2998 = or(_T_2991, _T_2997) @[lsu_bus_buffer.scala 417:110] + node _T_2999 = and(_T_2979, _T_2998) @[lsu_bus_buffer.scala 415:112] + node _T_3000 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_3001 = and(_T_3000, buf_state_en[2]) @[lsu_bus_buffer.scala 415:93] + node _T_3002 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_3003 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_3004 = or(_T_3002, _T_3003) @[lsu_bus_buffer.scala 416:32] + node _T_3005 = eq(_T_3004, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_3006 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_3007 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_3008 = and(_T_3006, _T_3007) @[lsu_bus_buffer.scala 417:41] + node _T_3009 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 417:82] + node _T_3010 = and(_T_3008, _T_3009) @[lsu_bus_buffer.scala 417:71] + node _T_3011 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 417:101] + node _T_3012 = and(_T_3010, _T_3011) @[lsu_bus_buffer.scala 417:90] + node _T_3013 = or(_T_3005, _T_3012) @[lsu_bus_buffer.scala 416:59] + node _T_3014 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_3015 = and(_T_3014, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_3016 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:63] + node _T_3017 = and(_T_3015, _T_3016) @[lsu_bus_buffer.scala 418:52] + node _T_3018 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:82] + node _T_3019 = and(_T_3017, _T_3018) @[lsu_bus_buffer.scala 418:71] + node _T_3020 = or(_T_3013, _T_3019) @[lsu_bus_buffer.scala 417:110] + node _T_3021 = and(_T_3001, _T_3020) @[lsu_bus_buffer.scala 415:112] + node _T_3022 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_3023 = and(_T_3022, buf_state_en[2]) @[lsu_bus_buffer.scala 415:93] + node _T_3024 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_3025 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_3026 = or(_T_3024, _T_3025) @[lsu_bus_buffer.scala 416:32] + node _T_3027 = eq(_T_3026, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_3028 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_3029 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_3030 = and(_T_3028, _T_3029) @[lsu_bus_buffer.scala 417:41] + node _T_3031 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 417:82] + node _T_3032 = and(_T_3030, _T_3031) @[lsu_bus_buffer.scala 417:71] + node _T_3033 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 417:101] + node _T_3034 = and(_T_3032, _T_3033) @[lsu_bus_buffer.scala 417:90] + node _T_3035 = or(_T_3027, _T_3034) @[lsu_bus_buffer.scala 416:59] + node _T_3036 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_3037 = and(_T_3036, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_3038 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:63] + node _T_3039 = and(_T_3037, _T_3038) @[lsu_bus_buffer.scala 418:52] + node _T_3040 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:82] + node _T_3041 = and(_T_3039, _T_3040) @[lsu_bus_buffer.scala 418:71] + node _T_3042 = or(_T_3035, _T_3041) @[lsu_bus_buffer.scala 417:110] + node _T_3043 = and(_T_3023, _T_3042) @[lsu_bus_buffer.scala 415:112] + node _T_3044 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_3045 = and(_T_3044, buf_state_en[2]) @[lsu_bus_buffer.scala 415:93] + node _T_3046 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_3047 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_3048 = or(_T_3046, _T_3047) @[lsu_bus_buffer.scala 416:32] + node _T_3049 = eq(_T_3048, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_3050 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_3051 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_3052 = and(_T_3050, _T_3051) @[lsu_bus_buffer.scala 417:41] + node _T_3053 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 417:82] + node _T_3054 = and(_T_3052, _T_3053) @[lsu_bus_buffer.scala 417:71] + node _T_3055 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 417:101] + node _T_3056 = and(_T_3054, _T_3055) @[lsu_bus_buffer.scala 417:90] + node _T_3057 = or(_T_3049, _T_3056) @[lsu_bus_buffer.scala 416:59] + node _T_3058 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_3059 = and(_T_3058, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_3060 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:63] + node _T_3061 = and(_T_3059, _T_3060) @[lsu_bus_buffer.scala 418:52] + node _T_3062 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:82] + node _T_3063 = and(_T_3061, _T_3062) @[lsu_bus_buffer.scala 418:71] + node _T_3064 = or(_T_3057, _T_3063) @[lsu_bus_buffer.scala 417:110] + node _T_3065 = and(_T_3045, _T_3064) @[lsu_bus_buffer.scala 415:112] node _T_3066 = cat(_T_3065, _T_3043) @[Cat.scala 29:58] node _T_3067 = cat(_T_3066, _T_3021) @[Cat.scala 29:58] node _T_3068 = cat(_T_3067, _T_2999) @[Cat.scala 29:58] - node _T_3069 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] - node _T_3070 = and(_T_3069, buf_state_en[3]) @[lsu_bus_buffer.scala 416:93] - node _T_3071 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] - node _T_3072 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] - node _T_3073 = or(_T_3071, _T_3072) @[lsu_bus_buffer.scala 417:32] - node _T_3074 = eq(_T_3073, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] - node _T_3075 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] - node _T_3076 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] - node _T_3077 = and(_T_3075, _T_3076) @[lsu_bus_buffer.scala 418:41] - node _T_3078 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:82] - node _T_3079 = and(_T_3077, _T_3078) @[lsu_bus_buffer.scala 418:71] - node _T_3080 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:101] - node _T_3081 = and(_T_3079, _T_3080) @[lsu_bus_buffer.scala 418:90] - node _T_3082 = or(_T_3074, _T_3081) @[lsu_bus_buffer.scala 417:59] - node _T_3083 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] - node _T_3084 = and(_T_3083, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] - node _T_3085 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 419:63] - node _T_3086 = and(_T_3084, _T_3085) @[lsu_bus_buffer.scala 419:52] - node _T_3087 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 419:82] - node _T_3088 = and(_T_3086, _T_3087) @[lsu_bus_buffer.scala 419:71] - node _T_3089 = or(_T_3082, _T_3088) @[lsu_bus_buffer.scala 418:110] - node _T_3090 = and(_T_3070, _T_3089) @[lsu_bus_buffer.scala 416:112] - node _T_3091 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] - node _T_3092 = and(_T_3091, buf_state_en[3]) @[lsu_bus_buffer.scala 416:93] - node _T_3093 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] - node _T_3094 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] - node _T_3095 = or(_T_3093, _T_3094) @[lsu_bus_buffer.scala 417:32] - node _T_3096 = eq(_T_3095, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] - node _T_3097 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] - node _T_3098 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] - node _T_3099 = and(_T_3097, _T_3098) @[lsu_bus_buffer.scala 418:41] - node _T_3100 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:82] - node _T_3101 = and(_T_3099, _T_3100) @[lsu_bus_buffer.scala 418:71] - node _T_3102 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:101] - node _T_3103 = and(_T_3101, _T_3102) @[lsu_bus_buffer.scala 418:90] - node _T_3104 = or(_T_3096, _T_3103) @[lsu_bus_buffer.scala 417:59] - node _T_3105 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] - node _T_3106 = and(_T_3105, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] - node _T_3107 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 419:63] - node _T_3108 = and(_T_3106, _T_3107) @[lsu_bus_buffer.scala 419:52] - node _T_3109 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 419:82] - node _T_3110 = and(_T_3108, _T_3109) @[lsu_bus_buffer.scala 419:71] - node _T_3111 = or(_T_3104, _T_3110) @[lsu_bus_buffer.scala 418:110] - node _T_3112 = and(_T_3092, _T_3111) @[lsu_bus_buffer.scala 416:112] - node _T_3113 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] - node _T_3114 = and(_T_3113, buf_state_en[3]) @[lsu_bus_buffer.scala 416:93] - node _T_3115 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] - node _T_3116 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] - node _T_3117 = or(_T_3115, _T_3116) @[lsu_bus_buffer.scala 417:32] - node _T_3118 = eq(_T_3117, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] - node _T_3119 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] - node _T_3120 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] - node _T_3121 = and(_T_3119, _T_3120) @[lsu_bus_buffer.scala 418:41] - node _T_3122 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:82] - node _T_3123 = and(_T_3121, _T_3122) @[lsu_bus_buffer.scala 418:71] - node _T_3124 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:101] - node _T_3125 = and(_T_3123, _T_3124) @[lsu_bus_buffer.scala 418:90] - node _T_3126 = or(_T_3118, _T_3125) @[lsu_bus_buffer.scala 417:59] - node _T_3127 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] - node _T_3128 = and(_T_3127, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] - node _T_3129 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 419:63] - node _T_3130 = and(_T_3128, _T_3129) @[lsu_bus_buffer.scala 419:52] - node _T_3131 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 419:82] - node _T_3132 = and(_T_3130, _T_3131) @[lsu_bus_buffer.scala 419:71] - node _T_3133 = or(_T_3126, _T_3132) @[lsu_bus_buffer.scala 418:110] - node _T_3134 = and(_T_3114, _T_3133) @[lsu_bus_buffer.scala 416:112] - node _T_3135 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:82] - node _T_3136 = and(_T_3135, buf_state_en[3]) @[lsu_bus_buffer.scala 416:93] - node _T_3137 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 417:21] - node _T_3138 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 417:47] - node _T_3139 = or(_T_3137, _T_3138) @[lsu_bus_buffer.scala 417:32] - node _T_3140 = eq(_T_3139, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:6] - node _T_3141 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:23] - node _T_3142 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:53] - node _T_3143 = and(_T_3141, _T_3142) @[lsu_bus_buffer.scala 418:41] - node _T_3144 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:82] - node _T_3145 = and(_T_3143, _T_3144) @[lsu_bus_buffer.scala 418:71] - node _T_3146 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:101] - node _T_3147 = and(_T_3145, _T_3146) @[lsu_bus_buffer.scala 418:90] - node _T_3148 = or(_T_3140, _T_3147) @[lsu_bus_buffer.scala 417:59] - node _T_3149 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 419:17] - node _T_3150 = and(_T_3149, io.ldst_dual_r) @[lsu_bus_buffer.scala 419:35] - node _T_3151 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 419:63] - node _T_3152 = and(_T_3150, _T_3151) @[lsu_bus_buffer.scala 419:52] - node _T_3153 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 419:82] - node _T_3154 = and(_T_3152, _T_3153) @[lsu_bus_buffer.scala 419:71] - node _T_3155 = or(_T_3148, _T_3154) @[lsu_bus_buffer.scala 418:110] - node _T_3156 = and(_T_3136, _T_3155) @[lsu_bus_buffer.scala 416:112] + node _T_3069 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_3070 = and(_T_3069, buf_state_en[3]) @[lsu_bus_buffer.scala 415:93] + node _T_3071 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_3072 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_3073 = or(_T_3071, _T_3072) @[lsu_bus_buffer.scala 416:32] + node _T_3074 = eq(_T_3073, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_3075 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_3076 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_3077 = and(_T_3075, _T_3076) @[lsu_bus_buffer.scala 417:41] + node _T_3078 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 417:82] + node _T_3079 = and(_T_3077, _T_3078) @[lsu_bus_buffer.scala 417:71] + node _T_3080 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 417:101] + node _T_3081 = and(_T_3079, _T_3080) @[lsu_bus_buffer.scala 417:90] + node _T_3082 = or(_T_3074, _T_3081) @[lsu_bus_buffer.scala 416:59] + node _T_3083 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_3084 = and(_T_3083, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_3085 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:63] + node _T_3086 = and(_T_3084, _T_3085) @[lsu_bus_buffer.scala 418:52] + node _T_3087 = eq(WrPtr0_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 418:82] + node _T_3088 = and(_T_3086, _T_3087) @[lsu_bus_buffer.scala 418:71] + node _T_3089 = or(_T_3082, _T_3088) @[lsu_bus_buffer.scala 417:110] + node _T_3090 = and(_T_3070, _T_3089) @[lsu_bus_buffer.scala 415:112] + node _T_3091 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_3092 = and(_T_3091, buf_state_en[3]) @[lsu_bus_buffer.scala 415:93] + node _T_3093 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_3094 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_3095 = or(_T_3093, _T_3094) @[lsu_bus_buffer.scala 416:32] + node _T_3096 = eq(_T_3095, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_3097 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_3098 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_3099 = and(_T_3097, _T_3098) @[lsu_bus_buffer.scala 417:41] + node _T_3100 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 417:82] + node _T_3101 = and(_T_3099, _T_3100) @[lsu_bus_buffer.scala 417:71] + node _T_3102 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 417:101] + node _T_3103 = and(_T_3101, _T_3102) @[lsu_bus_buffer.scala 417:90] + node _T_3104 = or(_T_3096, _T_3103) @[lsu_bus_buffer.scala 416:59] + node _T_3105 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_3106 = and(_T_3105, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_3107 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:63] + node _T_3108 = and(_T_3106, _T_3107) @[lsu_bus_buffer.scala 418:52] + node _T_3109 = eq(WrPtr0_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 418:82] + node _T_3110 = and(_T_3108, _T_3109) @[lsu_bus_buffer.scala 418:71] + node _T_3111 = or(_T_3104, _T_3110) @[lsu_bus_buffer.scala 417:110] + node _T_3112 = and(_T_3092, _T_3111) @[lsu_bus_buffer.scala 415:112] + node _T_3113 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_3114 = and(_T_3113, buf_state_en[3]) @[lsu_bus_buffer.scala 415:93] + node _T_3115 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_3116 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_3117 = or(_T_3115, _T_3116) @[lsu_bus_buffer.scala 416:32] + node _T_3118 = eq(_T_3117, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_3119 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_3120 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_3121 = and(_T_3119, _T_3120) @[lsu_bus_buffer.scala 417:41] + node _T_3122 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 417:82] + node _T_3123 = and(_T_3121, _T_3122) @[lsu_bus_buffer.scala 417:71] + node _T_3124 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 417:101] + node _T_3125 = and(_T_3123, _T_3124) @[lsu_bus_buffer.scala 417:90] + node _T_3126 = or(_T_3118, _T_3125) @[lsu_bus_buffer.scala 416:59] + node _T_3127 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_3128 = and(_T_3127, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_3129 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:63] + node _T_3130 = and(_T_3128, _T_3129) @[lsu_bus_buffer.scala 418:52] + node _T_3131 = eq(WrPtr0_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 418:82] + node _T_3132 = and(_T_3130, _T_3131) @[lsu_bus_buffer.scala 418:71] + node _T_3133 = or(_T_3126, _T_3132) @[lsu_bus_buffer.scala 417:110] + node _T_3134 = and(_T_3114, _T_3133) @[lsu_bus_buffer.scala 415:112] + node _T_3135 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 415:82] + node _T_3136 = and(_T_3135, buf_state_en[3]) @[lsu_bus_buffer.scala 415:93] + node _T_3137 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 416:21] + node _T_3138 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 416:47] + node _T_3139 = or(_T_3137, _T_3138) @[lsu_bus_buffer.scala 416:32] + node _T_3140 = eq(_T_3139, UInt<1>("h00")) @[lsu_bus_buffer.scala 416:6] + node _T_3141 = and(ibuf_drain_vld, io.lsu_busreq_r) @[lsu_bus_buffer.scala 417:23] + node _T_3142 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 417:53] + node _T_3143 = and(_T_3141, _T_3142) @[lsu_bus_buffer.scala 417:41] + node _T_3144 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 417:82] + node _T_3145 = and(_T_3143, _T_3144) @[lsu_bus_buffer.scala 417:71] + node _T_3146 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 417:101] + node _T_3147 = and(_T_3145, _T_3146) @[lsu_bus_buffer.scala 417:90] + node _T_3148 = or(_T_3140, _T_3147) @[lsu_bus_buffer.scala 416:59] + node _T_3149 = and(ibuf_byp, io.lsu_busreq_r) @[lsu_bus_buffer.scala 418:17] + node _T_3150 = and(_T_3149, io.ldst_dual_r) @[lsu_bus_buffer.scala 418:35] + node _T_3151 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:63] + node _T_3152 = and(_T_3150, _T_3151) @[lsu_bus_buffer.scala 418:52] + node _T_3153 = eq(WrPtr0_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 418:82] + node _T_3154 = and(_T_3152, _T_3153) @[lsu_bus_buffer.scala 418:71] + node _T_3155 = or(_T_3148, _T_3154) @[lsu_bus_buffer.scala 417:110] + node _T_3156 = and(_T_3136, _T_3155) @[lsu_bus_buffer.scala 415:112] node _T_3157 = cat(_T_3156, _T_3134) @[Cat.scala 29:58] node _T_3158 = cat(_T_3157, _T_3112) @[Cat.scala 29:58] node _T_3159 = cat(_T_3158, _T_3090) @[Cat.scala 29:58] - buf_rspage_set[0] <= _T_2886 @[lsu_bus_buffer.scala 416:18] - buf_rspage_set[1] <= _T_2977 @[lsu_bus_buffer.scala 416:18] - buf_rspage_set[2] <= _T_3068 @[lsu_bus_buffer.scala 416:18] - buf_rspage_set[3] <= _T_3159 @[lsu_bus_buffer.scala 416:18] - node _T_3160 = bits(buf_rspage_set[0], 0, 0) @[lsu_bus_buffer.scala 420:84] - node _T_3161 = bits(buf_rspage[0], 0, 0) @[lsu_bus_buffer.scala 420:103] - node _T_3162 = or(_T_3160, _T_3161) @[lsu_bus_buffer.scala 420:88] - node _T_3163 = bits(buf_rspage_set[0], 1, 1) @[lsu_bus_buffer.scala 420:84] - node _T_3164 = bits(buf_rspage[0], 1, 1) @[lsu_bus_buffer.scala 420:103] - node _T_3165 = or(_T_3163, _T_3164) @[lsu_bus_buffer.scala 420:88] - node _T_3166 = bits(buf_rspage_set[0], 2, 2) @[lsu_bus_buffer.scala 420:84] - node _T_3167 = bits(buf_rspage[0], 2, 2) @[lsu_bus_buffer.scala 420:103] - node _T_3168 = or(_T_3166, _T_3167) @[lsu_bus_buffer.scala 420:88] - node _T_3169 = bits(buf_rspage_set[0], 3, 3) @[lsu_bus_buffer.scala 420:84] - node _T_3170 = bits(buf_rspage[0], 3, 3) @[lsu_bus_buffer.scala 420:103] - node _T_3171 = or(_T_3169, _T_3170) @[lsu_bus_buffer.scala 420:88] + buf_rspage_set[0] <= _T_2886 @[lsu_bus_buffer.scala 415:18] + buf_rspage_set[1] <= _T_2977 @[lsu_bus_buffer.scala 415:18] + buf_rspage_set[2] <= _T_3068 @[lsu_bus_buffer.scala 415:18] + buf_rspage_set[3] <= _T_3159 @[lsu_bus_buffer.scala 415:18] + node _T_3160 = bits(buf_rspage_set[0], 0, 0) @[lsu_bus_buffer.scala 419:84] + node _T_3161 = bits(buf_rspage[0], 0, 0) @[lsu_bus_buffer.scala 419:103] + node _T_3162 = or(_T_3160, _T_3161) @[lsu_bus_buffer.scala 419:88] + node _T_3163 = bits(buf_rspage_set[0], 1, 1) @[lsu_bus_buffer.scala 419:84] + node _T_3164 = bits(buf_rspage[0], 1, 1) @[lsu_bus_buffer.scala 419:103] + node _T_3165 = or(_T_3163, _T_3164) @[lsu_bus_buffer.scala 419:88] + node _T_3166 = bits(buf_rspage_set[0], 2, 2) @[lsu_bus_buffer.scala 419:84] + node _T_3167 = bits(buf_rspage[0], 2, 2) @[lsu_bus_buffer.scala 419:103] + node _T_3168 = or(_T_3166, _T_3167) @[lsu_bus_buffer.scala 419:88] + node _T_3169 = bits(buf_rspage_set[0], 3, 3) @[lsu_bus_buffer.scala 419:84] + node _T_3170 = bits(buf_rspage[0], 3, 3) @[lsu_bus_buffer.scala 419:103] + node _T_3171 = or(_T_3169, _T_3170) @[lsu_bus_buffer.scala 419:88] node _T_3172 = cat(_T_3171, _T_3168) @[Cat.scala 29:58] node _T_3173 = cat(_T_3172, _T_3165) @[Cat.scala 29:58] node _T_3174 = cat(_T_3173, _T_3162) @[Cat.scala 29:58] - node _T_3175 = bits(buf_rspage_set[1], 0, 0) @[lsu_bus_buffer.scala 420:84] - node _T_3176 = bits(buf_rspage[1], 0, 0) @[lsu_bus_buffer.scala 420:103] - node _T_3177 = or(_T_3175, _T_3176) @[lsu_bus_buffer.scala 420:88] - node _T_3178 = bits(buf_rspage_set[1], 1, 1) @[lsu_bus_buffer.scala 420:84] - node _T_3179 = bits(buf_rspage[1], 1, 1) @[lsu_bus_buffer.scala 420:103] - node _T_3180 = or(_T_3178, _T_3179) @[lsu_bus_buffer.scala 420:88] - node _T_3181 = bits(buf_rspage_set[1], 2, 2) @[lsu_bus_buffer.scala 420:84] - node _T_3182 = bits(buf_rspage[1], 2, 2) @[lsu_bus_buffer.scala 420:103] - node _T_3183 = or(_T_3181, _T_3182) @[lsu_bus_buffer.scala 420:88] - node _T_3184 = bits(buf_rspage_set[1], 3, 3) @[lsu_bus_buffer.scala 420:84] - node _T_3185 = bits(buf_rspage[1], 3, 3) @[lsu_bus_buffer.scala 420:103] - node _T_3186 = or(_T_3184, _T_3185) @[lsu_bus_buffer.scala 420:88] + node _T_3175 = bits(buf_rspage_set[1], 0, 0) @[lsu_bus_buffer.scala 419:84] + node _T_3176 = bits(buf_rspage[1], 0, 0) @[lsu_bus_buffer.scala 419:103] + node _T_3177 = or(_T_3175, _T_3176) @[lsu_bus_buffer.scala 419:88] + node _T_3178 = bits(buf_rspage_set[1], 1, 1) @[lsu_bus_buffer.scala 419:84] + node _T_3179 = bits(buf_rspage[1], 1, 1) @[lsu_bus_buffer.scala 419:103] + node _T_3180 = or(_T_3178, _T_3179) @[lsu_bus_buffer.scala 419:88] + node _T_3181 = bits(buf_rspage_set[1], 2, 2) @[lsu_bus_buffer.scala 419:84] + node _T_3182 = bits(buf_rspage[1], 2, 2) @[lsu_bus_buffer.scala 419:103] + node _T_3183 = or(_T_3181, _T_3182) @[lsu_bus_buffer.scala 419:88] + node _T_3184 = bits(buf_rspage_set[1], 3, 3) @[lsu_bus_buffer.scala 419:84] + node _T_3185 = bits(buf_rspage[1], 3, 3) @[lsu_bus_buffer.scala 419:103] + node _T_3186 = or(_T_3184, _T_3185) @[lsu_bus_buffer.scala 419:88] node _T_3187 = cat(_T_3186, _T_3183) @[Cat.scala 29:58] node _T_3188 = cat(_T_3187, _T_3180) @[Cat.scala 29:58] node _T_3189 = cat(_T_3188, _T_3177) @[Cat.scala 29:58] - node _T_3190 = bits(buf_rspage_set[2], 0, 0) @[lsu_bus_buffer.scala 420:84] - node _T_3191 = bits(buf_rspage[2], 0, 0) @[lsu_bus_buffer.scala 420:103] - node _T_3192 = or(_T_3190, _T_3191) @[lsu_bus_buffer.scala 420:88] - node _T_3193 = bits(buf_rspage_set[2], 1, 1) @[lsu_bus_buffer.scala 420:84] - node _T_3194 = bits(buf_rspage[2], 1, 1) @[lsu_bus_buffer.scala 420:103] - node _T_3195 = or(_T_3193, _T_3194) @[lsu_bus_buffer.scala 420:88] - node _T_3196 = bits(buf_rspage_set[2], 2, 2) @[lsu_bus_buffer.scala 420:84] - node _T_3197 = bits(buf_rspage[2], 2, 2) @[lsu_bus_buffer.scala 420:103] - node _T_3198 = or(_T_3196, _T_3197) @[lsu_bus_buffer.scala 420:88] - node _T_3199 = bits(buf_rspage_set[2], 3, 3) @[lsu_bus_buffer.scala 420:84] - node _T_3200 = bits(buf_rspage[2], 3, 3) @[lsu_bus_buffer.scala 420:103] - node _T_3201 = or(_T_3199, _T_3200) @[lsu_bus_buffer.scala 420:88] + node _T_3190 = bits(buf_rspage_set[2], 0, 0) @[lsu_bus_buffer.scala 419:84] + node _T_3191 = bits(buf_rspage[2], 0, 0) @[lsu_bus_buffer.scala 419:103] + node _T_3192 = or(_T_3190, _T_3191) @[lsu_bus_buffer.scala 419:88] + node _T_3193 = bits(buf_rspage_set[2], 1, 1) @[lsu_bus_buffer.scala 419:84] + node _T_3194 = bits(buf_rspage[2], 1, 1) @[lsu_bus_buffer.scala 419:103] + node _T_3195 = or(_T_3193, _T_3194) @[lsu_bus_buffer.scala 419:88] + node _T_3196 = bits(buf_rspage_set[2], 2, 2) @[lsu_bus_buffer.scala 419:84] + node _T_3197 = bits(buf_rspage[2], 2, 2) @[lsu_bus_buffer.scala 419:103] + node _T_3198 = or(_T_3196, _T_3197) @[lsu_bus_buffer.scala 419:88] + node _T_3199 = bits(buf_rspage_set[2], 3, 3) @[lsu_bus_buffer.scala 419:84] + node _T_3200 = bits(buf_rspage[2], 3, 3) @[lsu_bus_buffer.scala 419:103] + node _T_3201 = or(_T_3199, _T_3200) @[lsu_bus_buffer.scala 419:88] node _T_3202 = cat(_T_3201, _T_3198) @[Cat.scala 29:58] node _T_3203 = cat(_T_3202, _T_3195) @[Cat.scala 29:58] node _T_3204 = cat(_T_3203, _T_3192) @[Cat.scala 29:58] - node _T_3205 = bits(buf_rspage_set[3], 0, 0) @[lsu_bus_buffer.scala 420:84] - node _T_3206 = bits(buf_rspage[3], 0, 0) @[lsu_bus_buffer.scala 420:103] - node _T_3207 = or(_T_3205, _T_3206) @[lsu_bus_buffer.scala 420:88] - node _T_3208 = bits(buf_rspage_set[3], 1, 1) @[lsu_bus_buffer.scala 420:84] - node _T_3209 = bits(buf_rspage[3], 1, 1) @[lsu_bus_buffer.scala 420:103] - node _T_3210 = or(_T_3208, _T_3209) @[lsu_bus_buffer.scala 420:88] - node _T_3211 = bits(buf_rspage_set[3], 2, 2) @[lsu_bus_buffer.scala 420:84] - node _T_3212 = bits(buf_rspage[3], 2, 2) @[lsu_bus_buffer.scala 420:103] - node _T_3213 = or(_T_3211, _T_3212) @[lsu_bus_buffer.scala 420:88] - node _T_3214 = bits(buf_rspage_set[3], 3, 3) @[lsu_bus_buffer.scala 420:84] - node _T_3215 = bits(buf_rspage[3], 3, 3) @[lsu_bus_buffer.scala 420:103] - node _T_3216 = or(_T_3214, _T_3215) @[lsu_bus_buffer.scala 420:88] + node _T_3205 = bits(buf_rspage_set[3], 0, 0) @[lsu_bus_buffer.scala 419:84] + node _T_3206 = bits(buf_rspage[3], 0, 0) @[lsu_bus_buffer.scala 419:103] + node _T_3207 = or(_T_3205, _T_3206) @[lsu_bus_buffer.scala 419:88] + node _T_3208 = bits(buf_rspage_set[3], 1, 1) @[lsu_bus_buffer.scala 419:84] + node _T_3209 = bits(buf_rspage[3], 1, 1) @[lsu_bus_buffer.scala 419:103] + node _T_3210 = or(_T_3208, _T_3209) @[lsu_bus_buffer.scala 419:88] + node _T_3211 = bits(buf_rspage_set[3], 2, 2) @[lsu_bus_buffer.scala 419:84] + node _T_3212 = bits(buf_rspage[3], 2, 2) @[lsu_bus_buffer.scala 419:103] + node _T_3213 = or(_T_3211, _T_3212) @[lsu_bus_buffer.scala 419:88] + node _T_3214 = bits(buf_rspage_set[3], 3, 3) @[lsu_bus_buffer.scala 419:84] + node _T_3215 = bits(buf_rspage[3], 3, 3) @[lsu_bus_buffer.scala 419:103] + node _T_3216 = or(_T_3214, _T_3215) @[lsu_bus_buffer.scala 419:88] node _T_3217 = cat(_T_3216, _T_3213) @[Cat.scala 29:58] node _T_3218 = cat(_T_3217, _T_3210) @[Cat.scala 29:58] node _T_3219 = cat(_T_3218, _T_3207) @[Cat.scala 29:58] - buf_rspage_in[0] <= _T_3174 @[lsu_bus_buffer.scala 420:17] - buf_rspage_in[1] <= _T_3189 @[lsu_bus_buffer.scala 420:17] - buf_rspage_in[2] <= _T_3204 @[lsu_bus_buffer.scala 420:17] - buf_rspage_in[3] <= _T_3219 @[lsu_bus_buffer.scala 420:17] - node _T_3220 = bits(buf_rspageQ[0], 0, 0) @[lsu_bus_buffer.scala 421:78] - node _T_3221 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] - node _T_3222 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] - node _T_3223 = or(_T_3221, _T_3222) @[lsu_bus_buffer.scala 421:110] - node _T_3224 = eq(_T_3223, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] - node _T_3225 = and(_T_3220, _T_3224) @[lsu_bus_buffer.scala 421:82] - node _T_3226 = bits(buf_rspageQ[0], 1, 1) @[lsu_bus_buffer.scala 421:78] - node _T_3227 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] - node _T_3228 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] - node _T_3229 = or(_T_3227, _T_3228) @[lsu_bus_buffer.scala 421:110] - node _T_3230 = eq(_T_3229, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] - node _T_3231 = and(_T_3226, _T_3230) @[lsu_bus_buffer.scala 421:82] - node _T_3232 = bits(buf_rspageQ[0], 2, 2) @[lsu_bus_buffer.scala 421:78] - node _T_3233 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] - node _T_3234 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] - node _T_3235 = or(_T_3233, _T_3234) @[lsu_bus_buffer.scala 421:110] - node _T_3236 = eq(_T_3235, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] - node _T_3237 = and(_T_3232, _T_3236) @[lsu_bus_buffer.scala 421:82] - node _T_3238 = bits(buf_rspageQ[0], 3, 3) @[lsu_bus_buffer.scala 421:78] - node _T_3239 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] - node _T_3240 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] - node _T_3241 = or(_T_3239, _T_3240) @[lsu_bus_buffer.scala 421:110] - node _T_3242 = eq(_T_3241, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] - node _T_3243 = and(_T_3238, _T_3242) @[lsu_bus_buffer.scala 421:82] + buf_rspage_in[0] <= _T_3174 @[lsu_bus_buffer.scala 419:17] + buf_rspage_in[1] <= _T_3189 @[lsu_bus_buffer.scala 419:17] + buf_rspage_in[2] <= _T_3204 @[lsu_bus_buffer.scala 419:17] + buf_rspage_in[3] <= _T_3219 @[lsu_bus_buffer.scala 419:17] + node _T_3220 = bits(buf_rspageQ[0], 0, 0) @[lsu_bus_buffer.scala 420:78] + node _T_3221 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3222 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3223 = or(_T_3221, _T_3222) @[lsu_bus_buffer.scala 420:110] + node _T_3224 = eq(_T_3223, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3225 = and(_T_3220, _T_3224) @[lsu_bus_buffer.scala 420:82] + node _T_3226 = bits(buf_rspageQ[0], 1, 1) @[lsu_bus_buffer.scala 420:78] + node _T_3227 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3228 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3229 = or(_T_3227, _T_3228) @[lsu_bus_buffer.scala 420:110] + node _T_3230 = eq(_T_3229, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3231 = and(_T_3226, _T_3230) @[lsu_bus_buffer.scala 420:82] + node _T_3232 = bits(buf_rspageQ[0], 2, 2) @[lsu_bus_buffer.scala 420:78] + node _T_3233 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3234 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3235 = or(_T_3233, _T_3234) @[lsu_bus_buffer.scala 420:110] + node _T_3236 = eq(_T_3235, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3237 = and(_T_3232, _T_3236) @[lsu_bus_buffer.scala 420:82] + node _T_3238 = bits(buf_rspageQ[0], 3, 3) @[lsu_bus_buffer.scala 420:78] + node _T_3239 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3240 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3241 = or(_T_3239, _T_3240) @[lsu_bus_buffer.scala 420:110] + node _T_3242 = eq(_T_3241, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3243 = and(_T_3238, _T_3242) @[lsu_bus_buffer.scala 420:82] node _T_3244 = cat(_T_3243, _T_3237) @[Cat.scala 29:58] node _T_3245 = cat(_T_3244, _T_3231) @[Cat.scala 29:58] node _T_3246 = cat(_T_3245, _T_3225) @[Cat.scala 29:58] - node _T_3247 = bits(buf_rspageQ[1], 0, 0) @[lsu_bus_buffer.scala 421:78] - node _T_3248 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] - node _T_3249 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] - node _T_3250 = or(_T_3248, _T_3249) @[lsu_bus_buffer.scala 421:110] - node _T_3251 = eq(_T_3250, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] - node _T_3252 = and(_T_3247, _T_3251) @[lsu_bus_buffer.scala 421:82] - node _T_3253 = bits(buf_rspageQ[1], 1, 1) @[lsu_bus_buffer.scala 421:78] - node _T_3254 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] - node _T_3255 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] - node _T_3256 = or(_T_3254, _T_3255) @[lsu_bus_buffer.scala 421:110] - node _T_3257 = eq(_T_3256, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] - node _T_3258 = and(_T_3253, _T_3257) @[lsu_bus_buffer.scala 421:82] - node _T_3259 = bits(buf_rspageQ[1], 2, 2) @[lsu_bus_buffer.scala 421:78] - node _T_3260 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] - node _T_3261 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] - node _T_3262 = or(_T_3260, _T_3261) @[lsu_bus_buffer.scala 421:110] - node _T_3263 = eq(_T_3262, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] - node _T_3264 = and(_T_3259, _T_3263) @[lsu_bus_buffer.scala 421:82] - node _T_3265 = bits(buf_rspageQ[1], 3, 3) @[lsu_bus_buffer.scala 421:78] - node _T_3266 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] - node _T_3267 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] - node _T_3268 = or(_T_3266, _T_3267) @[lsu_bus_buffer.scala 421:110] - node _T_3269 = eq(_T_3268, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] - node _T_3270 = and(_T_3265, _T_3269) @[lsu_bus_buffer.scala 421:82] + node _T_3247 = bits(buf_rspageQ[1], 0, 0) @[lsu_bus_buffer.scala 420:78] + node _T_3248 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3249 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3250 = or(_T_3248, _T_3249) @[lsu_bus_buffer.scala 420:110] + node _T_3251 = eq(_T_3250, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3252 = and(_T_3247, _T_3251) @[lsu_bus_buffer.scala 420:82] + node _T_3253 = bits(buf_rspageQ[1], 1, 1) @[lsu_bus_buffer.scala 420:78] + node _T_3254 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3255 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3256 = or(_T_3254, _T_3255) @[lsu_bus_buffer.scala 420:110] + node _T_3257 = eq(_T_3256, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3258 = and(_T_3253, _T_3257) @[lsu_bus_buffer.scala 420:82] + node _T_3259 = bits(buf_rspageQ[1], 2, 2) @[lsu_bus_buffer.scala 420:78] + node _T_3260 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3261 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3262 = or(_T_3260, _T_3261) @[lsu_bus_buffer.scala 420:110] + node _T_3263 = eq(_T_3262, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3264 = and(_T_3259, _T_3263) @[lsu_bus_buffer.scala 420:82] + node _T_3265 = bits(buf_rspageQ[1], 3, 3) @[lsu_bus_buffer.scala 420:78] + node _T_3266 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3267 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3268 = or(_T_3266, _T_3267) @[lsu_bus_buffer.scala 420:110] + node _T_3269 = eq(_T_3268, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3270 = and(_T_3265, _T_3269) @[lsu_bus_buffer.scala 420:82] node _T_3271 = cat(_T_3270, _T_3264) @[Cat.scala 29:58] node _T_3272 = cat(_T_3271, _T_3258) @[Cat.scala 29:58] node _T_3273 = cat(_T_3272, _T_3252) @[Cat.scala 29:58] - node _T_3274 = bits(buf_rspageQ[2], 0, 0) @[lsu_bus_buffer.scala 421:78] - node _T_3275 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] - node _T_3276 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] - node _T_3277 = or(_T_3275, _T_3276) @[lsu_bus_buffer.scala 421:110] - node _T_3278 = eq(_T_3277, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] - node _T_3279 = and(_T_3274, _T_3278) @[lsu_bus_buffer.scala 421:82] - node _T_3280 = bits(buf_rspageQ[2], 1, 1) @[lsu_bus_buffer.scala 421:78] - node _T_3281 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] - node _T_3282 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] - node _T_3283 = or(_T_3281, _T_3282) @[lsu_bus_buffer.scala 421:110] - node _T_3284 = eq(_T_3283, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] - node _T_3285 = and(_T_3280, _T_3284) @[lsu_bus_buffer.scala 421:82] - node _T_3286 = bits(buf_rspageQ[2], 2, 2) @[lsu_bus_buffer.scala 421:78] - node _T_3287 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] - node _T_3288 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] - node _T_3289 = or(_T_3287, _T_3288) @[lsu_bus_buffer.scala 421:110] - node _T_3290 = eq(_T_3289, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] - node _T_3291 = and(_T_3286, _T_3290) @[lsu_bus_buffer.scala 421:82] - node _T_3292 = bits(buf_rspageQ[2], 3, 3) @[lsu_bus_buffer.scala 421:78] - node _T_3293 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] - node _T_3294 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] - node _T_3295 = or(_T_3293, _T_3294) @[lsu_bus_buffer.scala 421:110] - node _T_3296 = eq(_T_3295, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] - node _T_3297 = and(_T_3292, _T_3296) @[lsu_bus_buffer.scala 421:82] + node _T_3274 = bits(buf_rspageQ[2], 0, 0) @[lsu_bus_buffer.scala 420:78] + node _T_3275 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3276 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3277 = or(_T_3275, _T_3276) @[lsu_bus_buffer.scala 420:110] + node _T_3278 = eq(_T_3277, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3279 = and(_T_3274, _T_3278) @[lsu_bus_buffer.scala 420:82] + node _T_3280 = bits(buf_rspageQ[2], 1, 1) @[lsu_bus_buffer.scala 420:78] + node _T_3281 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3282 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3283 = or(_T_3281, _T_3282) @[lsu_bus_buffer.scala 420:110] + node _T_3284 = eq(_T_3283, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3285 = and(_T_3280, _T_3284) @[lsu_bus_buffer.scala 420:82] + node _T_3286 = bits(buf_rspageQ[2], 2, 2) @[lsu_bus_buffer.scala 420:78] + node _T_3287 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3288 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3289 = or(_T_3287, _T_3288) @[lsu_bus_buffer.scala 420:110] + node _T_3290 = eq(_T_3289, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3291 = and(_T_3286, _T_3290) @[lsu_bus_buffer.scala 420:82] + node _T_3292 = bits(buf_rspageQ[2], 3, 3) @[lsu_bus_buffer.scala 420:78] + node _T_3293 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3294 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3295 = or(_T_3293, _T_3294) @[lsu_bus_buffer.scala 420:110] + node _T_3296 = eq(_T_3295, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3297 = and(_T_3292, _T_3296) @[lsu_bus_buffer.scala 420:82] node _T_3298 = cat(_T_3297, _T_3291) @[Cat.scala 29:58] node _T_3299 = cat(_T_3298, _T_3285) @[Cat.scala 29:58] node _T_3300 = cat(_T_3299, _T_3279) @[Cat.scala 29:58] - node _T_3301 = bits(buf_rspageQ[3], 0, 0) @[lsu_bus_buffer.scala 421:78] - node _T_3302 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] - node _T_3303 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] - node _T_3304 = or(_T_3302, _T_3303) @[lsu_bus_buffer.scala 421:110] - node _T_3305 = eq(_T_3304, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] - node _T_3306 = and(_T_3301, _T_3305) @[lsu_bus_buffer.scala 421:82] - node _T_3307 = bits(buf_rspageQ[3], 1, 1) @[lsu_bus_buffer.scala 421:78] - node _T_3308 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] - node _T_3309 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] - node _T_3310 = or(_T_3308, _T_3309) @[lsu_bus_buffer.scala 421:110] - node _T_3311 = eq(_T_3310, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] - node _T_3312 = and(_T_3307, _T_3311) @[lsu_bus_buffer.scala 421:82] - node _T_3313 = bits(buf_rspageQ[3], 2, 2) @[lsu_bus_buffer.scala 421:78] - node _T_3314 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] - node _T_3315 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] - node _T_3316 = or(_T_3314, _T_3315) @[lsu_bus_buffer.scala 421:110] - node _T_3317 = eq(_T_3316, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] - node _T_3318 = and(_T_3313, _T_3317) @[lsu_bus_buffer.scala 421:82] - node _T_3319 = bits(buf_rspageQ[3], 3, 3) @[lsu_bus_buffer.scala 421:78] - node _T_3320 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 421:99] - node _T_3321 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 421:125] - node _T_3322 = or(_T_3320, _T_3321) @[lsu_bus_buffer.scala 421:110] - node _T_3323 = eq(_T_3322, UInt<1>("h00")) @[lsu_bus_buffer.scala 421:84] - node _T_3324 = and(_T_3319, _T_3323) @[lsu_bus_buffer.scala 421:82] + node _T_3301 = bits(buf_rspageQ[3], 0, 0) @[lsu_bus_buffer.scala 420:78] + node _T_3302 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3303 = eq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3304 = or(_T_3302, _T_3303) @[lsu_bus_buffer.scala 420:110] + node _T_3305 = eq(_T_3304, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3306 = and(_T_3301, _T_3305) @[lsu_bus_buffer.scala 420:82] + node _T_3307 = bits(buf_rspageQ[3], 1, 1) @[lsu_bus_buffer.scala 420:78] + node _T_3308 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3309 = eq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3310 = or(_T_3308, _T_3309) @[lsu_bus_buffer.scala 420:110] + node _T_3311 = eq(_T_3310, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3312 = and(_T_3307, _T_3311) @[lsu_bus_buffer.scala 420:82] + node _T_3313 = bits(buf_rspageQ[3], 2, 2) @[lsu_bus_buffer.scala 420:78] + node _T_3314 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3315 = eq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3316 = or(_T_3314, _T_3315) @[lsu_bus_buffer.scala 420:110] + node _T_3317 = eq(_T_3316, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3318 = and(_T_3313, _T_3317) @[lsu_bus_buffer.scala 420:82] + node _T_3319 = bits(buf_rspageQ[3], 3, 3) @[lsu_bus_buffer.scala 420:78] + node _T_3320 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 420:99] + node _T_3321 = eq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 420:125] + node _T_3322 = or(_T_3320, _T_3321) @[lsu_bus_buffer.scala 420:110] + node _T_3323 = eq(_T_3322, UInt<1>("h00")) @[lsu_bus_buffer.scala 420:84] + node _T_3324 = and(_T_3319, _T_3323) @[lsu_bus_buffer.scala 420:82] node _T_3325 = cat(_T_3324, _T_3318) @[Cat.scala 29:58] node _T_3326 = cat(_T_3325, _T_3312) @[Cat.scala 29:58] node _T_3327 = cat(_T_3326, _T_3306) @[Cat.scala 29:58] - buf_rspage[0] <= _T_3246 @[lsu_bus_buffer.scala 421:14] - buf_rspage[1] <= _T_3273 @[lsu_bus_buffer.scala 421:14] - buf_rspage[2] <= _T_3300 @[lsu_bus_buffer.scala 421:14] - buf_rspage[3] <= _T_3327 @[lsu_bus_buffer.scala 421:14] - node _T_3328 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 426:75] - node _T_3329 = and(ibuf_drain_vld, _T_3328) @[lsu_bus_buffer.scala 426:63] - node _T_3330 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 426:75] - node _T_3331 = and(ibuf_drain_vld, _T_3330) @[lsu_bus_buffer.scala 426:63] - node _T_3332 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 426:75] - node _T_3333 = and(ibuf_drain_vld, _T_3332) @[lsu_bus_buffer.scala 426:63] - node _T_3334 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 426:75] - node _T_3335 = and(ibuf_drain_vld, _T_3334) @[lsu_bus_buffer.scala 426:63] + buf_rspage[0] <= _T_3246 @[lsu_bus_buffer.scala 420:14] + buf_rspage[1] <= _T_3273 @[lsu_bus_buffer.scala 420:14] + buf_rspage[2] <= _T_3300 @[lsu_bus_buffer.scala 420:14] + buf_rspage[3] <= _T_3327 @[lsu_bus_buffer.scala 420:14] + node _T_3328 = eq(ibuf_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 425:75] + node _T_3329 = and(ibuf_drain_vld, _T_3328) @[lsu_bus_buffer.scala 425:63] + node _T_3330 = eq(ibuf_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 425:75] + node _T_3331 = and(ibuf_drain_vld, _T_3330) @[lsu_bus_buffer.scala 425:63] + node _T_3332 = eq(ibuf_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 425:75] + node _T_3333 = and(ibuf_drain_vld, _T_3332) @[lsu_bus_buffer.scala 425:63] + node _T_3334 = eq(ibuf_tag, UInt<2>("h03")) @[lsu_bus_buffer.scala 425:75] + node _T_3335 = and(ibuf_drain_vld, _T_3334) @[lsu_bus_buffer.scala 425:63] node _T_3336 = cat(_T_3335, _T_3333) @[Cat.scala 29:58] node _T_3337 = cat(_T_3336, _T_3331) @[Cat.scala 29:58] node _T_3338 = cat(_T_3337, _T_3329) @[Cat.scala 29:58] - ibuf_drainvec_vld <= _T_3338 @[lsu_bus_buffer.scala 426:21] - node _T_3339 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 427:64] - node _T_3340 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 427:84] - node _T_3341 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 428:18] - node _T_3342 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 428:46] - node _T_3343 = and(_T_3341, _T_3342) @[lsu_bus_buffer.scala 428:35] - node _T_3344 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 428:71] - node _T_3345 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 428:94] - node _T_3346 = mux(_T_3343, _T_3344, _T_3345) @[lsu_bus_buffer.scala 428:8] - node _T_3347 = mux(_T_3339, _T_3340, _T_3346) @[lsu_bus_buffer.scala 427:46] - node _T_3348 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 427:64] - node _T_3349 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 427:84] - node _T_3350 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 428:18] - node _T_3351 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 428:46] - node _T_3352 = and(_T_3350, _T_3351) @[lsu_bus_buffer.scala 428:35] - node _T_3353 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 428:71] - node _T_3354 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 428:94] - node _T_3355 = mux(_T_3352, _T_3353, _T_3354) @[lsu_bus_buffer.scala 428:8] - node _T_3356 = mux(_T_3348, _T_3349, _T_3355) @[lsu_bus_buffer.scala 427:46] - node _T_3357 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 427:64] - node _T_3358 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 427:84] - node _T_3359 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 428:18] - node _T_3360 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 428:46] - node _T_3361 = and(_T_3359, _T_3360) @[lsu_bus_buffer.scala 428:35] - node _T_3362 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 428:71] - node _T_3363 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 428:94] - node _T_3364 = mux(_T_3361, _T_3362, _T_3363) @[lsu_bus_buffer.scala 428:8] - node _T_3365 = mux(_T_3357, _T_3358, _T_3364) @[lsu_bus_buffer.scala 427:46] - node _T_3366 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 427:64] - node _T_3367 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 427:84] - node _T_3368 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 428:18] - node _T_3369 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 428:46] - node _T_3370 = and(_T_3368, _T_3369) @[lsu_bus_buffer.scala 428:35] - node _T_3371 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 428:71] - node _T_3372 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 428:94] - node _T_3373 = mux(_T_3370, _T_3371, _T_3372) @[lsu_bus_buffer.scala 428:8] - node _T_3374 = mux(_T_3366, _T_3367, _T_3373) @[lsu_bus_buffer.scala 427:46] - buf_byteen_in[0] <= _T_3347 @[lsu_bus_buffer.scala 427:17] - buf_byteen_in[1] <= _T_3356 @[lsu_bus_buffer.scala 427:17] - buf_byteen_in[2] <= _T_3365 @[lsu_bus_buffer.scala 427:17] - buf_byteen_in[3] <= _T_3374 @[lsu_bus_buffer.scala 427:17] - node _T_3375 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 429:62] - node _T_3376 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:91] - node _T_3377 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 429:119] - node _T_3378 = and(_T_3376, _T_3377) @[lsu_bus_buffer.scala 429:108] - node _T_3379 = mux(_T_3378, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 429:81] - node _T_3380 = mux(_T_3375, ibuf_addr, _T_3379) @[lsu_bus_buffer.scala 429:44] - node _T_3381 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 429:62] - node _T_3382 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:91] - node _T_3383 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 429:119] - node _T_3384 = and(_T_3382, _T_3383) @[lsu_bus_buffer.scala 429:108] - node _T_3385 = mux(_T_3384, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 429:81] - node _T_3386 = mux(_T_3381, ibuf_addr, _T_3385) @[lsu_bus_buffer.scala 429:44] - node _T_3387 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 429:62] - node _T_3388 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:91] - node _T_3389 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 429:119] - node _T_3390 = and(_T_3388, _T_3389) @[lsu_bus_buffer.scala 429:108] - node _T_3391 = mux(_T_3390, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 429:81] - node _T_3392 = mux(_T_3387, ibuf_addr, _T_3391) @[lsu_bus_buffer.scala 429:44] - node _T_3393 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 429:62] - node _T_3394 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:91] - node _T_3395 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 429:119] - node _T_3396 = and(_T_3394, _T_3395) @[lsu_bus_buffer.scala 429:108] - node _T_3397 = mux(_T_3396, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 429:81] - node _T_3398 = mux(_T_3393, ibuf_addr, _T_3397) @[lsu_bus_buffer.scala 429:44] - buf_addr_in[0] <= _T_3380 @[lsu_bus_buffer.scala 429:15] - buf_addr_in[1] <= _T_3386 @[lsu_bus_buffer.scala 429:15] - buf_addr_in[2] <= _T_3392 @[lsu_bus_buffer.scala 429:15] - buf_addr_in[3] <= _T_3398 @[lsu_bus_buffer.scala 429:15] - node _T_3399 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 430:63] - node _T_3400 = mux(_T_3399, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:45] - node _T_3401 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 430:63] - node _T_3402 = mux(_T_3401, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:45] - node _T_3403 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 430:63] - node _T_3404 = mux(_T_3403, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:45] - node _T_3405 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 430:63] - node _T_3406 = mux(_T_3405, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 430:45] + ibuf_drainvec_vld <= _T_3338 @[lsu_bus_buffer.scala 425:21] + node _T_3339 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 426:64] + node _T_3340 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 426:84] + node _T_3341 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 427:18] + node _T_3342 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 427:46] + node _T_3343 = and(_T_3341, _T_3342) @[lsu_bus_buffer.scala 427:35] + node _T_3344 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 427:71] + node _T_3345 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 427:94] + node _T_3346 = mux(_T_3343, _T_3344, _T_3345) @[lsu_bus_buffer.scala 427:8] + node _T_3347 = mux(_T_3339, _T_3340, _T_3346) @[lsu_bus_buffer.scala 426:46] + node _T_3348 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 426:64] + node _T_3349 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 426:84] + node _T_3350 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 427:18] + node _T_3351 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 427:46] + node _T_3352 = and(_T_3350, _T_3351) @[lsu_bus_buffer.scala 427:35] + node _T_3353 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 427:71] + node _T_3354 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 427:94] + node _T_3355 = mux(_T_3352, _T_3353, _T_3354) @[lsu_bus_buffer.scala 427:8] + node _T_3356 = mux(_T_3348, _T_3349, _T_3355) @[lsu_bus_buffer.scala 426:46] + node _T_3357 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 426:64] + node _T_3358 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 426:84] + node _T_3359 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 427:18] + node _T_3360 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 427:46] + node _T_3361 = and(_T_3359, _T_3360) @[lsu_bus_buffer.scala 427:35] + node _T_3362 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 427:71] + node _T_3363 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 427:94] + node _T_3364 = mux(_T_3361, _T_3362, _T_3363) @[lsu_bus_buffer.scala 427:8] + node _T_3365 = mux(_T_3357, _T_3358, _T_3364) @[lsu_bus_buffer.scala 426:46] + node _T_3366 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 426:64] + node _T_3367 = bits(ibuf_byteen_out, 3, 0) @[lsu_bus_buffer.scala 426:84] + node _T_3368 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 427:18] + node _T_3369 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 427:46] + node _T_3370 = and(_T_3368, _T_3369) @[lsu_bus_buffer.scala 427:35] + node _T_3371 = bits(ldst_byteen_hi_r, 3, 0) @[lsu_bus_buffer.scala 427:71] + node _T_3372 = bits(ldst_byteen_lo_r, 3, 0) @[lsu_bus_buffer.scala 427:94] + node _T_3373 = mux(_T_3370, _T_3371, _T_3372) @[lsu_bus_buffer.scala 427:8] + node _T_3374 = mux(_T_3366, _T_3367, _T_3373) @[lsu_bus_buffer.scala 426:46] + buf_byteen_in[0] <= _T_3347 @[lsu_bus_buffer.scala 426:17] + buf_byteen_in[1] <= _T_3356 @[lsu_bus_buffer.scala 426:17] + buf_byteen_in[2] <= _T_3365 @[lsu_bus_buffer.scala 426:17] + buf_byteen_in[3] <= _T_3374 @[lsu_bus_buffer.scala 426:17] + node _T_3375 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 428:62] + node _T_3376 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 428:91] + node _T_3377 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 428:119] + node _T_3378 = and(_T_3376, _T_3377) @[lsu_bus_buffer.scala 428:108] + node _T_3379 = mux(_T_3378, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 428:81] + node _T_3380 = mux(_T_3375, ibuf_addr, _T_3379) @[lsu_bus_buffer.scala 428:44] + node _T_3381 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 428:62] + node _T_3382 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 428:91] + node _T_3383 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 428:119] + node _T_3384 = and(_T_3382, _T_3383) @[lsu_bus_buffer.scala 428:108] + node _T_3385 = mux(_T_3384, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 428:81] + node _T_3386 = mux(_T_3381, ibuf_addr, _T_3385) @[lsu_bus_buffer.scala 428:44] + node _T_3387 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 428:62] + node _T_3388 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 428:91] + node _T_3389 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 428:119] + node _T_3390 = and(_T_3388, _T_3389) @[lsu_bus_buffer.scala 428:108] + node _T_3391 = mux(_T_3390, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 428:81] + node _T_3392 = mux(_T_3387, ibuf_addr, _T_3391) @[lsu_bus_buffer.scala 428:44] + node _T_3393 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 428:62] + node _T_3394 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 428:91] + node _T_3395 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 428:119] + node _T_3396 = and(_T_3394, _T_3395) @[lsu_bus_buffer.scala 428:108] + node _T_3397 = mux(_T_3396, io.end_addr_r, io.lsu_addr_r) @[lsu_bus_buffer.scala 428:81] + node _T_3398 = mux(_T_3393, ibuf_addr, _T_3397) @[lsu_bus_buffer.scala 428:44] + buf_addr_in[0] <= _T_3380 @[lsu_bus_buffer.scala 428:15] + buf_addr_in[1] <= _T_3386 @[lsu_bus_buffer.scala 428:15] + buf_addr_in[2] <= _T_3392 @[lsu_bus_buffer.scala 428:15] + buf_addr_in[3] <= _T_3398 @[lsu_bus_buffer.scala 428:15] + node _T_3399 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 429:63] + node _T_3400 = mux(_T_3399, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:45] + node _T_3401 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 429:63] + node _T_3402 = mux(_T_3401, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:45] + node _T_3403 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 429:63] + node _T_3404 = mux(_T_3403, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:45] + node _T_3405 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 429:63] + node _T_3406 = mux(_T_3405, ibuf_dual, io.ldst_dual_r) @[lsu_bus_buffer.scala 429:45] node _T_3407 = cat(_T_3406, _T_3404) @[Cat.scala 29:58] node _T_3408 = cat(_T_3407, _T_3402) @[Cat.scala 29:58] node _T_3409 = cat(_T_3408, _T_3400) @[Cat.scala 29:58] - buf_dual_in <= _T_3409 @[lsu_bus_buffer.scala 430:15] - node _T_3410 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 431:65] - node _T_3411 = mux(_T_3410, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 431:47] - node _T_3412 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 431:65] - node _T_3413 = mux(_T_3412, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 431:47] - node _T_3414 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 431:65] - node _T_3415 = mux(_T_3414, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 431:47] - node _T_3416 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 431:65] - node _T_3417 = mux(_T_3416, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 431:47] + buf_dual_in <= _T_3409 @[lsu_bus_buffer.scala 429:15] + node _T_3410 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 430:65] + node _T_3411 = mux(_T_3410, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 430:47] + node _T_3412 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 430:65] + node _T_3413 = mux(_T_3412, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 430:47] + node _T_3414 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 430:65] + node _T_3415 = mux(_T_3414, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 430:47] + node _T_3416 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 430:65] + node _T_3417 = mux(_T_3416, ibuf_samedw, ldst_samedw_r) @[lsu_bus_buffer.scala 430:47] node _T_3418 = cat(_T_3417, _T_3415) @[Cat.scala 29:58] node _T_3419 = cat(_T_3418, _T_3413) @[Cat.scala 29:58] node _T_3420 = cat(_T_3419, _T_3411) @[Cat.scala 29:58] - buf_samedw_in <= _T_3420 @[lsu_bus_buffer.scala 431:17] - node _T_3421 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 432:66] - node _T_3422 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 432:84] - node _T_3423 = mux(_T_3421, _T_3422, io.no_dword_merge_r) @[lsu_bus_buffer.scala 432:48] - node _T_3424 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 432:66] - node _T_3425 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 432:84] - node _T_3426 = mux(_T_3424, _T_3425, io.no_dword_merge_r) @[lsu_bus_buffer.scala 432:48] - node _T_3427 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 432:66] - node _T_3428 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 432:84] - node _T_3429 = mux(_T_3427, _T_3428, io.no_dword_merge_r) @[lsu_bus_buffer.scala 432:48] - node _T_3430 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 432:66] - node _T_3431 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 432:84] - node _T_3432 = mux(_T_3430, _T_3431, io.no_dword_merge_r) @[lsu_bus_buffer.scala 432:48] + buf_samedw_in <= _T_3420 @[lsu_bus_buffer.scala 430:17] + node _T_3421 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 431:66] + node _T_3422 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 431:84] + node _T_3423 = mux(_T_3421, _T_3422, io.no_dword_merge_r) @[lsu_bus_buffer.scala 431:48] + node _T_3424 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 431:66] + node _T_3425 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 431:84] + node _T_3426 = mux(_T_3424, _T_3425, io.no_dword_merge_r) @[lsu_bus_buffer.scala 431:48] + node _T_3427 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 431:66] + node _T_3428 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 431:84] + node _T_3429 = mux(_T_3427, _T_3428, io.no_dword_merge_r) @[lsu_bus_buffer.scala 431:48] + node _T_3430 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 431:66] + node _T_3431 = or(ibuf_nomerge, ibuf_force_drain) @[lsu_bus_buffer.scala 431:84] + node _T_3432 = mux(_T_3430, _T_3431, io.no_dword_merge_r) @[lsu_bus_buffer.scala 431:48] node _T_3433 = cat(_T_3432, _T_3429) @[Cat.scala 29:58] node _T_3434 = cat(_T_3433, _T_3426) @[Cat.scala 29:58] node _T_3435 = cat(_T_3434, _T_3423) @[Cat.scala 29:58] - buf_nomerge_in <= _T_3435 @[lsu_bus_buffer.scala 432:18] - node _T_3436 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 433:65] - node _T_3437 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 433:90] - node _T_3438 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 433:118] - node _T_3439 = and(_T_3437, _T_3438) @[lsu_bus_buffer.scala 433:107] - node _T_3440 = mux(_T_3436, ibuf_dual, _T_3439) @[lsu_bus_buffer.scala 433:47] - node _T_3441 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 433:65] - node _T_3442 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 433:90] - node _T_3443 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 433:118] - node _T_3444 = and(_T_3442, _T_3443) @[lsu_bus_buffer.scala 433:107] - node _T_3445 = mux(_T_3441, ibuf_dual, _T_3444) @[lsu_bus_buffer.scala 433:47] - node _T_3446 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 433:65] - node _T_3447 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 433:90] - node _T_3448 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 433:118] - node _T_3449 = and(_T_3447, _T_3448) @[lsu_bus_buffer.scala 433:107] - node _T_3450 = mux(_T_3446, ibuf_dual, _T_3449) @[lsu_bus_buffer.scala 433:47] - node _T_3451 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 433:65] - node _T_3452 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 433:90] - node _T_3453 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 433:118] - node _T_3454 = and(_T_3452, _T_3453) @[lsu_bus_buffer.scala 433:107] - node _T_3455 = mux(_T_3451, ibuf_dual, _T_3454) @[lsu_bus_buffer.scala 433:47] + buf_nomerge_in <= _T_3435 @[lsu_bus_buffer.scala 431:18] + node _T_3436 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 432:65] + node _T_3437 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 432:90] + node _T_3438 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 432:118] + node _T_3439 = and(_T_3437, _T_3438) @[lsu_bus_buffer.scala 432:107] + node _T_3440 = mux(_T_3436, ibuf_dual, _T_3439) @[lsu_bus_buffer.scala 432:47] + node _T_3441 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 432:65] + node _T_3442 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 432:90] + node _T_3443 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 432:118] + node _T_3444 = and(_T_3442, _T_3443) @[lsu_bus_buffer.scala 432:107] + node _T_3445 = mux(_T_3441, ibuf_dual, _T_3444) @[lsu_bus_buffer.scala 432:47] + node _T_3446 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 432:65] + node _T_3447 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 432:90] + node _T_3448 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 432:118] + node _T_3449 = and(_T_3447, _T_3448) @[lsu_bus_buffer.scala 432:107] + node _T_3450 = mux(_T_3446, ibuf_dual, _T_3449) @[lsu_bus_buffer.scala 432:47] + node _T_3451 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 432:65] + node _T_3452 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 432:90] + node _T_3453 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 432:118] + node _T_3454 = and(_T_3452, _T_3453) @[lsu_bus_buffer.scala 432:107] + node _T_3455 = mux(_T_3451, ibuf_dual, _T_3454) @[lsu_bus_buffer.scala 432:47] node _T_3456 = cat(_T_3455, _T_3450) @[Cat.scala 29:58] node _T_3457 = cat(_T_3456, _T_3445) @[Cat.scala 29:58] node _T_3458 = cat(_T_3457, _T_3440) @[Cat.scala 29:58] - buf_dualhi_in <= _T_3458 @[lsu_bus_buffer.scala 433:17] - node _T_3459 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 434:65] - node _T_3460 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:97] - node _T_3461 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 434:125] - node _T_3462 = and(_T_3460, _T_3461) @[lsu_bus_buffer.scala 434:114] - node _T_3463 = mux(_T_3462, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 434:87] - node _T_3464 = mux(_T_3459, ibuf_dualtag, _T_3463) @[lsu_bus_buffer.scala 434:47] - node _T_3465 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 434:65] - node _T_3466 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:97] - node _T_3467 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 434:125] - node _T_3468 = and(_T_3466, _T_3467) @[lsu_bus_buffer.scala 434:114] - node _T_3469 = mux(_T_3468, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 434:87] - node _T_3470 = mux(_T_3465, ibuf_dualtag, _T_3469) @[lsu_bus_buffer.scala 434:47] - node _T_3471 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 434:65] - node _T_3472 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:97] - node _T_3473 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 434:125] - node _T_3474 = and(_T_3472, _T_3473) @[lsu_bus_buffer.scala 434:114] - node _T_3475 = mux(_T_3474, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 434:87] - node _T_3476 = mux(_T_3471, ibuf_dualtag, _T_3475) @[lsu_bus_buffer.scala 434:47] - node _T_3477 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 434:65] - node _T_3478 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 434:97] - node _T_3479 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 434:125] - node _T_3480 = and(_T_3478, _T_3479) @[lsu_bus_buffer.scala 434:114] - node _T_3481 = mux(_T_3480, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 434:87] - node _T_3482 = mux(_T_3477, ibuf_dualtag, _T_3481) @[lsu_bus_buffer.scala 434:47] - buf_dualtag_in[0] <= _T_3464 @[lsu_bus_buffer.scala 434:18] - buf_dualtag_in[1] <= _T_3470 @[lsu_bus_buffer.scala 434:18] - buf_dualtag_in[2] <= _T_3476 @[lsu_bus_buffer.scala 434:18] - buf_dualtag_in[3] <= _T_3482 @[lsu_bus_buffer.scala 434:18] - node _T_3483 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 435:69] - node _T_3484 = mux(_T_3483, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 435:51] - node _T_3485 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 435:69] - node _T_3486 = mux(_T_3485, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 435:51] - node _T_3487 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 435:69] - node _T_3488 = mux(_T_3487, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 435:51] - node _T_3489 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 435:69] - node _T_3490 = mux(_T_3489, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 435:51] + buf_dualhi_in <= _T_3458 @[lsu_bus_buffer.scala 432:17] + node _T_3459 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 433:65] + node _T_3460 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 433:97] + node _T_3461 = eq(WrPtr1_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 433:125] + node _T_3462 = and(_T_3460, _T_3461) @[lsu_bus_buffer.scala 433:114] + node _T_3463 = mux(_T_3462, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 433:87] + node _T_3464 = mux(_T_3459, ibuf_dualtag, _T_3463) @[lsu_bus_buffer.scala 433:47] + node _T_3465 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 433:65] + node _T_3466 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 433:97] + node _T_3467 = eq(WrPtr1_r, UInt<1>("h01")) @[lsu_bus_buffer.scala 433:125] + node _T_3468 = and(_T_3466, _T_3467) @[lsu_bus_buffer.scala 433:114] + node _T_3469 = mux(_T_3468, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 433:87] + node _T_3470 = mux(_T_3465, ibuf_dualtag, _T_3469) @[lsu_bus_buffer.scala 433:47] + node _T_3471 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 433:65] + node _T_3472 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 433:97] + node _T_3473 = eq(WrPtr1_r, UInt<2>("h02")) @[lsu_bus_buffer.scala 433:125] + node _T_3474 = and(_T_3472, _T_3473) @[lsu_bus_buffer.scala 433:114] + node _T_3475 = mux(_T_3474, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 433:87] + node _T_3476 = mux(_T_3471, ibuf_dualtag, _T_3475) @[lsu_bus_buffer.scala 433:47] + node _T_3477 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 433:65] + node _T_3478 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 433:97] + node _T_3479 = eq(WrPtr1_r, UInt<2>("h03")) @[lsu_bus_buffer.scala 433:125] + node _T_3480 = and(_T_3478, _T_3479) @[lsu_bus_buffer.scala 433:114] + node _T_3481 = mux(_T_3480, WrPtr0_r, WrPtr1_r) @[lsu_bus_buffer.scala 433:87] + node _T_3482 = mux(_T_3477, ibuf_dualtag, _T_3481) @[lsu_bus_buffer.scala 433:47] + buf_dualtag_in[0] <= _T_3464 @[lsu_bus_buffer.scala 433:18] + buf_dualtag_in[1] <= _T_3470 @[lsu_bus_buffer.scala 433:18] + buf_dualtag_in[2] <= _T_3476 @[lsu_bus_buffer.scala 433:18] + buf_dualtag_in[3] <= _T_3482 @[lsu_bus_buffer.scala 433:18] + node _T_3483 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 434:69] + node _T_3484 = mux(_T_3483, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 434:51] + node _T_3485 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 434:69] + node _T_3486 = mux(_T_3485, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 434:51] + node _T_3487 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 434:69] + node _T_3488 = mux(_T_3487, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 434:51] + node _T_3489 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 434:69] + node _T_3490 = mux(_T_3489, ibuf_sideeffect, io.is_sideeffects_r) @[lsu_bus_buffer.scala 434:51] node _T_3491 = cat(_T_3490, _T_3488) @[Cat.scala 29:58] node _T_3492 = cat(_T_3491, _T_3486) @[Cat.scala 29:58] node _T_3493 = cat(_T_3492, _T_3484) @[Cat.scala 29:58] - buf_sideeffect_in <= _T_3493 @[lsu_bus_buffer.scala 435:21] - node _T_3494 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 436:65] - node _T_3495 = mux(_T_3494, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 436:47] - node _T_3496 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 436:65] - node _T_3497 = mux(_T_3496, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 436:47] - node _T_3498 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 436:65] - node _T_3499 = mux(_T_3498, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 436:47] - node _T_3500 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 436:65] - node _T_3501 = mux(_T_3500, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 436:47] + buf_sideeffect_in <= _T_3493 @[lsu_bus_buffer.scala 434:21] + node _T_3494 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 435:65] + node _T_3495 = mux(_T_3494, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 435:47] + node _T_3496 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 435:65] + node _T_3497 = mux(_T_3496, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 435:47] + node _T_3498 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 435:65] + node _T_3499 = mux(_T_3498, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 435:47] + node _T_3500 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 435:65] + node _T_3501 = mux(_T_3500, ibuf_unsign, io.lsu_pkt_r.bits.unsign) @[lsu_bus_buffer.scala 435:47] node _T_3502 = cat(_T_3501, _T_3499) @[Cat.scala 29:58] node _T_3503 = cat(_T_3502, _T_3497) @[Cat.scala 29:58] node _T_3504 = cat(_T_3503, _T_3495) @[Cat.scala 29:58] - buf_unsign_in <= _T_3504 @[lsu_bus_buffer.scala 436:17] - node _T_3505 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 437:60] + buf_unsign_in <= _T_3504 @[lsu_bus_buffer.scala 435:17] + node _T_3505 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 436:60] node _T_3506 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] - node _T_3507 = mux(_T_3505, ibuf_sz, _T_3506) @[lsu_bus_buffer.scala 437:42] - node _T_3508 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 437:60] + node _T_3507 = mux(_T_3505, ibuf_sz, _T_3506) @[lsu_bus_buffer.scala 436:42] + node _T_3508 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 436:60] node _T_3509 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] - node _T_3510 = mux(_T_3508, ibuf_sz, _T_3509) @[lsu_bus_buffer.scala 437:42] - node _T_3511 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 437:60] + node _T_3510 = mux(_T_3508, ibuf_sz, _T_3509) @[lsu_bus_buffer.scala 436:42] + node _T_3511 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 436:60] node _T_3512 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] - node _T_3513 = mux(_T_3511, ibuf_sz, _T_3512) @[lsu_bus_buffer.scala 437:42] - node _T_3514 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 437:60] + node _T_3513 = mux(_T_3511, ibuf_sz, _T_3512) @[lsu_bus_buffer.scala 436:42] + node _T_3514 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 436:60] node _T_3515 = cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half) @[Cat.scala 29:58] - node _T_3516 = mux(_T_3514, ibuf_sz, _T_3515) @[lsu_bus_buffer.scala 437:42] - buf_sz_in[0] <= _T_3507 @[lsu_bus_buffer.scala 437:13] - buf_sz_in[1] <= _T_3510 @[lsu_bus_buffer.scala 437:13] - buf_sz_in[2] <= _T_3513 @[lsu_bus_buffer.scala 437:13] - buf_sz_in[3] <= _T_3516 @[lsu_bus_buffer.scala 437:13] - node _T_3517 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 438:64] - node _T_3518 = mux(_T_3517, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 438:46] - node _T_3519 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 438:64] - node _T_3520 = mux(_T_3519, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 438:46] - node _T_3521 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 438:64] - node _T_3522 = mux(_T_3521, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 438:46] - node _T_3523 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 438:64] - node _T_3524 = mux(_T_3523, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 438:46] + node _T_3516 = mux(_T_3514, ibuf_sz, _T_3515) @[lsu_bus_buffer.scala 436:42] + buf_sz_in[0] <= _T_3507 @[lsu_bus_buffer.scala 436:13] + buf_sz_in[1] <= _T_3510 @[lsu_bus_buffer.scala 436:13] + buf_sz_in[2] <= _T_3513 @[lsu_bus_buffer.scala 436:13] + buf_sz_in[3] <= _T_3516 @[lsu_bus_buffer.scala 436:13] + node _T_3517 = bits(ibuf_drainvec_vld, 0, 0) @[lsu_bus_buffer.scala 437:64] + node _T_3518 = mux(_T_3517, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 437:46] + node _T_3519 = bits(ibuf_drainvec_vld, 1, 1) @[lsu_bus_buffer.scala 437:64] + node _T_3520 = mux(_T_3519, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 437:46] + node _T_3521 = bits(ibuf_drainvec_vld, 2, 2) @[lsu_bus_buffer.scala 437:64] + node _T_3522 = mux(_T_3521, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 437:46] + node _T_3523 = bits(ibuf_drainvec_vld, 3, 3) @[lsu_bus_buffer.scala 437:64] + node _T_3524 = mux(_T_3523, ibuf_write, io.lsu_pkt_r.bits.store) @[lsu_bus_buffer.scala 437:46] node _T_3525 = cat(_T_3524, _T_3522) @[Cat.scala 29:58] node _T_3526 = cat(_T_3525, _T_3520) @[Cat.scala 29:58] node _T_3527 = cat(_T_3526, _T_3518) @[Cat.scala 29:58] - buf_write_in <= _T_3527 @[lsu_bus_buffer.scala 438:16] + buf_write_in <= _T_3527 @[lsu_bus_buffer.scala 437:16] node _T_3528 = eq(UInt<3>("h00"), buf_state[0]) @[Conditional.scala 37:30] when _T_3528 : @[Conditional.scala 40:58] - node _T_3529 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 443:56] - node _T_3530 = mux(_T_3529, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 443:31] - buf_nxtstate[0] <= _T_3530 @[lsu_bus_buffer.scala 443:25] - node _T_3531 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 444:45] - node _T_3532 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 444:77] - node _T_3533 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 444:97] - node _T_3534 = and(_T_3532, _T_3533) @[lsu_bus_buffer.scala 444:95] - node _T_3535 = eq(UInt<1>("h00"), WrPtr0_r) @[lsu_bus_buffer.scala 444:117] - node _T_3536 = and(_T_3534, _T_3535) @[lsu_bus_buffer.scala 444:112] - node _T_3537 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 444:144] - node _T_3538 = eq(UInt<1>("h00"), WrPtr1_r) @[lsu_bus_buffer.scala 444:166] - node _T_3539 = and(_T_3537, _T_3538) @[lsu_bus_buffer.scala 444:161] - node _T_3540 = or(_T_3536, _T_3539) @[lsu_bus_buffer.scala 444:132] - node _T_3541 = and(_T_3531, _T_3540) @[lsu_bus_buffer.scala 444:63] - node _T_3542 = eq(UInt<1>("h00"), ibuf_tag) @[lsu_bus_buffer.scala 444:206] - node _T_3543 = and(ibuf_drain_vld, _T_3542) @[lsu_bus_buffer.scala 444:201] - node _T_3544 = or(_T_3541, _T_3543) @[lsu_bus_buffer.scala 444:183] - buf_state_en[0] <= _T_3544 @[lsu_bus_buffer.scala 444:25] - buf_wr_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 445:22] - buf_data_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 446:24] - node _T_3545 = eq(UInt<1>("h00"), ibuf_tag) @[lsu_bus_buffer.scala 447:52] - node _T_3546 = and(ibuf_drain_vld, _T_3545) @[lsu_bus_buffer.scala 447:47] - node _T_3547 = bits(_T_3546, 0, 0) @[lsu_bus_buffer.scala 447:73] - node _T_3548 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 447:90] - node _T_3549 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 447:114] - node _T_3550 = mux(_T_3547, _T_3548, _T_3549) @[lsu_bus_buffer.scala 447:30] - buf_data_in[0] <= _T_3550 @[lsu_bus_buffer.scala 447:24] + node _T_3529 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 442:56] + node _T_3530 = mux(_T_3529, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 442:31] + buf_nxtstate[0] <= _T_3530 @[lsu_bus_buffer.scala 442:25] + node _T_3531 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 443:45] + node _T_3532 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:77] + node _T_3533 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 443:97] + node _T_3534 = and(_T_3532, _T_3533) @[lsu_bus_buffer.scala 443:95] + node _T_3535 = eq(UInt<1>("h00"), WrPtr0_r) @[lsu_bus_buffer.scala 443:117] + node _T_3536 = and(_T_3534, _T_3535) @[lsu_bus_buffer.scala 443:112] + node _T_3537 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:144] + node _T_3538 = eq(UInt<1>("h00"), WrPtr1_r) @[lsu_bus_buffer.scala 443:166] + node _T_3539 = and(_T_3537, _T_3538) @[lsu_bus_buffer.scala 443:161] + node _T_3540 = or(_T_3536, _T_3539) @[lsu_bus_buffer.scala 443:132] + node _T_3541 = and(_T_3531, _T_3540) @[lsu_bus_buffer.scala 443:63] + node _T_3542 = eq(UInt<1>("h00"), ibuf_tag) @[lsu_bus_buffer.scala 443:206] + node _T_3543 = and(ibuf_drain_vld, _T_3542) @[lsu_bus_buffer.scala 443:201] + node _T_3544 = or(_T_3541, _T_3543) @[lsu_bus_buffer.scala 443:183] + buf_state_en[0] <= _T_3544 @[lsu_bus_buffer.scala 443:25] + buf_wr_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 444:22] + buf_data_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 445:24] + node _T_3545 = eq(UInt<1>("h00"), ibuf_tag) @[lsu_bus_buffer.scala 446:52] + node _T_3546 = and(ibuf_drain_vld, _T_3545) @[lsu_bus_buffer.scala 446:47] + node _T_3547 = bits(_T_3546, 0, 0) @[lsu_bus_buffer.scala 446:73] + node _T_3548 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 446:90] + node _T_3549 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 446:114] + node _T_3550 = mux(_T_3547, _T_3548, _T_3549) @[lsu_bus_buffer.scala 446:30] + buf_data_in[0] <= _T_3550 @[lsu_bus_buffer.scala 446:24] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_3551 = eq(UInt<3>("h01"), buf_state[0]) @[Conditional.scala 37:30] when _T_3551 : @[Conditional.scala 39:67] - node _T_3552 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 450:60] - node _T_3553 = mux(_T_3552, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 450:31] - buf_nxtstate[0] <= _T_3553 @[lsu_bus_buffer.scala 450:25] - node _T_3554 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 451:46] - buf_state_en[0] <= _T_3554 @[lsu_bus_buffer.scala 451:25] + node _T_3552 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 449:60] + node _T_3553 = mux(_T_3552, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 449:31] + buf_nxtstate[0] <= _T_3553 @[lsu_bus_buffer.scala 449:25] + node _T_3554 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 450:46] + buf_state_en[0] <= _T_3554 @[lsu_bus_buffer.scala 450:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3555 = eq(UInt<3>("h02"), buf_state[0]) @[Conditional.scala 37:30] when _T_3555 : @[Conditional.scala 39:67] - node _T_3556 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 454:60] - node _T_3557 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 454:89] - node _T_3558 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 454:124] - node _T_3559 = and(_T_3557, _T_3558) @[lsu_bus_buffer.scala 454:104] - node _T_3560 = mux(_T_3559, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 454:75] - node _T_3561 = mux(_T_3556, UInt<3>("h00"), _T_3560) @[lsu_bus_buffer.scala 454:31] - buf_nxtstate[0] <= _T_3561 @[lsu_bus_buffer.scala 454:25] - node _T_3562 = eq(obuf_tag0, UInt<3>("h00")) @[lsu_bus_buffer.scala 455:48] - node _T_3563 = eq(obuf_tag1, UInt<3>("h00")) @[lsu_bus_buffer.scala 455:104] - node _T_3564 = and(obuf_merge, _T_3563) @[lsu_bus_buffer.scala 455:91] - node _T_3565 = or(_T_3562, _T_3564) @[lsu_bus_buffer.scala 455:77] - node _T_3566 = and(_T_3565, obuf_valid) @[lsu_bus_buffer.scala 455:135] - node _T_3567 = and(_T_3566, obuf_wr_enQ) @[lsu_bus_buffer.scala 455:148] - buf_cmd_state_bus_en[0] <= _T_3567 @[lsu_bus_buffer.scala 455:33] - buf_state_bus_en[0] <= buf_cmd_state_bus_en[0] @[lsu_bus_buffer.scala 456:29] - node _T_3568 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 457:49] - node _T_3569 = or(_T_3568, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 457:70] - buf_state_en[0] <= _T_3569 @[lsu_bus_buffer.scala 457:25] - buf_ldfwd_in[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 458:25] - node _T_3570 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 459:56] - node _T_3571 = eq(_T_3570, UInt<1>("h00")) @[lsu_bus_buffer.scala 459:46] - node _T_3572 = and(buf_state_en[0], _T_3571) @[lsu_bus_buffer.scala 459:44] - node _T_3573 = and(_T_3572, obuf_nosend) @[lsu_bus_buffer.scala 459:60] - node _T_3574 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 459:76] - node _T_3575 = and(_T_3573, _T_3574) @[lsu_bus_buffer.scala 459:74] - buf_ldfwd_en[0] <= _T_3575 @[lsu_bus_buffer.scala 459:25] - node _T_3576 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 460:46] - buf_ldfwdtag_in[0] <= _T_3576 @[lsu_bus_buffer.scala 460:28] - node _T_3577 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 461:47] - node _T_3578 = and(_T_3577, obuf_nosend) @[lsu_bus_buffer.scala 461:67] - node _T_3579 = and(_T_3578, bus_rsp_read) @[lsu_bus_buffer.scala 461:81] - buf_data_en[0] <= _T_3579 @[lsu_bus_buffer.scala 461:24] - node _T_3580 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:48] - node _T_3581 = and(_T_3580, obuf_nosend) @[lsu_bus_buffer.scala 462:68] - node _T_3582 = and(_T_3581, bus_rsp_read_error) @[lsu_bus_buffer.scala 462:82] - buf_error_en[0] <= _T_3582 @[lsu_bus_buffer.scala 462:25] - node _T_3583 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 463:61] - node _T_3584 = bits(buf_addr[0], 2, 2) @[lsu_bus_buffer.scala 463:85] - node _T_3585 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 463:103] - node _T_3586 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 463:126] - node _T_3587 = mux(_T_3584, _T_3585, _T_3586) @[lsu_bus_buffer.scala 463:73] - node _T_3588 = mux(buf_error_en[0], _T_3583, _T_3587) @[lsu_bus_buffer.scala 463:30] - buf_data_in[0] <= _T_3588 @[lsu_bus_buffer.scala 463:24] + node _T_3556 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_3557 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 453:89] + node _T_3558 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 453:124] + node _T_3559 = and(_T_3557, _T_3558) @[lsu_bus_buffer.scala 453:104] + node _T_3560 = mux(_T_3559, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 453:75] + node _T_3561 = mux(_T_3556, UInt<3>("h00"), _T_3560) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[0] <= _T_3561 @[lsu_bus_buffer.scala 453:25] + node _T_3562 = eq(obuf_tag0, UInt<3>("h00")) @[lsu_bus_buffer.scala 454:48] + node _T_3563 = eq(obuf_tag1, UInt<3>("h00")) @[lsu_bus_buffer.scala 454:104] + node _T_3564 = and(obuf_merge, _T_3563) @[lsu_bus_buffer.scala 454:91] + node _T_3565 = or(_T_3562, _T_3564) @[lsu_bus_buffer.scala 454:77] + node _T_3566 = and(_T_3565, obuf_valid) @[lsu_bus_buffer.scala 454:135] + node _T_3567 = and(_T_3566, obuf_wr_enQ) @[lsu_bus_buffer.scala 454:148] + buf_cmd_state_bus_en[0] <= _T_3567 @[lsu_bus_buffer.scala 454:33] + buf_state_bus_en[0] <= buf_cmd_state_bus_en[0] @[lsu_bus_buffer.scala 455:29] + node _T_3568 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 456:49] + node _T_3569 = or(_T_3568, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 456:70] + buf_state_en[0] <= _T_3569 @[lsu_bus_buffer.scala 456:25] + buf_ldfwd_in[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 457:25] + node _T_3570 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 458:56] + node _T_3571 = eq(_T_3570, UInt<1>("h00")) @[lsu_bus_buffer.scala 458:46] + node _T_3572 = and(buf_state_en[0], _T_3571) @[lsu_bus_buffer.scala 458:44] + node _T_3573 = and(_T_3572, obuf_nosend) @[lsu_bus_buffer.scala 458:60] + node _T_3574 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 458:76] + node _T_3575 = and(_T_3573, _T_3574) @[lsu_bus_buffer.scala 458:74] + buf_ldfwd_en[0] <= _T_3575 @[lsu_bus_buffer.scala 458:25] + node _T_3576 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 459:46] + buf_ldfwdtag_in[0] <= _T_3576 @[lsu_bus_buffer.scala 459:28] + node _T_3577 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 460:47] + node _T_3578 = and(_T_3577, obuf_nosend) @[lsu_bus_buffer.scala 460:67] + node _T_3579 = and(_T_3578, bus_rsp_read) @[lsu_bus_buffer.scala 460:81] + buf_data_en[0] <= _T_3579 @[lsu_bus_buffer.scala 460:24] + node _T_3580 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 461:48] + node _T_3581 = and(_T_3580, obuf_nosend) @[lsu_bus_buffer.scala 461:68] + node _T_3582 = and(_T_3581, bus_rsp_read_error) @[lsu_bus_buffer.scala 461:82] + buf_error_en[0] <= _T_3582 @[lsu_bus_buffer.scala 461:25] + node _T_3583 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 462:61] + node _T_3584 = bits(buf_addr[0], 2, 2) @[lsu_bus_buffer.scala 462:85] + node _T_3585 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 462:103] + node _T_3586 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 462:126] + node _T_3587 = mux(_T_3584, _T_3585, _T_3586) @[lsu_bus_buffer.scala 462:73] + node _T_3588 = mux(buf_error_en[0], _T_3583, _T_3587) @[lsu_bus_buffer.scala 462:30] + buf_data_in[0] <= _T_3588 @[lsu_bus_buffer.scala 462:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3589 = eq(UInt<3>("h03"), buf_state[0]) @[Conditional.scala 37:30] when _T_3589 : @[Conditional.scala 39:67] - node _T_3590 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 466:67] - node _T_3591 = and(UInt<1>("h01"), bus_rsp_write_error) @[lsu_bus_buffer.scala 466:94] - node _T_3592 = eq(_T_3591, UInt<1>("h00")) @[lsu_bus_buffer.scala 466:73] - node _T_3593 = and(_T_3590, _T_3592) @[lsu_bus_buffer.scala 466:71] - node _T_3594 = or(io.dec_tlu_force_halt, _T_3593) @[lsu_bus_buffer.scala 466:55] - node _T_3595 = bits(_T_3594, 0, 0) @[lsu_bus_buffer.scala 466:125] - node _T_3596 = eq(buf_samedw[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 467:30] - node _T_3597 = and(buf_dual[0], _T_3596) @[lsu_bus_buffer.scala 467:28] - node _T_3598 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 467:57] - node _T_3599 = eq(_T_3598, UInt<1>("h00")) @[lsu_bus_buffer.scala 467:47] - node _T_3600 = and(_T_3597, _T_3599) @[lsu_bus_buffer.scala 467:45] - node _T_3601 = neq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[lsu_bus_buffer.scala 467:90] - node _T_3602 = and(_T_3600, _T_3601) @[lsu_bus_buffer.scala 467:61] - node _T_3603 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 468:27] - node _T_3604 = or(_T_3603, any_done_wait_state) @[lsu_bus_buffer.scala 468:31] - node _T_3605 = eq(buf_samedw[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 468:70] - node _T_3606 = and(buf_dual[0], _T_3605) @[lsu_bus_buffer.scala 468:68] - node _T_3607 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 468:97] - node _T_3608 = eq(_T_3607, UInt<1>("h00")) @[lsu_bus_buffer.scala 468:87] - node _T_3609 = and(_T_3606, _T_3608) @[lsu_bus_buffer.scala 468:85] + node _T_3590 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 465:67] + node _T_3591 = and(UInt<1>("h01"), bus_rsp_write_error) @[lsu_bus_buffer.scala 465:94] + node _T_3592 = eq(_T_3591, UInt<1>("h00")) @[lsu_bus_buffer.scala 465:73] + node _T_3593 = and(_T_3590, _T_3592) @[lsu_bus_buffer.scala 465:71] + node _T_3594 = or(io.dec_tlu_force_halt, _T_3593) @[lsu_bus_buffer.scala 465:55] + node _T_3595 = bits(_T_3594, 0, 0) @[lsu_bus_buffer.scala 465:125] + node _T_3596 = eq(buf_samedw[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 466:30] + node _T_3597 = and(buf_dual[0], _T_3596) @[lsu_bus_buffer.scala 466:28] + node _T_3598 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 466:57] + node _T_3599 = eq(_T_3598, UInt<1>("h00")) @[lsu_bus_buffer.scala 466:47] + node _T_3600 = and(_T_3597, _T_3599) @[lsu_bus_buffer.scala 466:45] + node _T_3601 = neq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[lsu_bus_buffer.scala 466:90] + node _T_3602 = and(_T_3600, _T_3601) @[lsu_bus_buffer.scala 466:61] + node _T_3603 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 467:27] + node _T_3604 = or(_T_3603, any_done_wait_state) @[lsu_bus_buffer.scala 467:31] + node _T_3605 = eq(buf_samedw[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 467:70] + node _T_3606 = and(buf_dual[0], _T_3605) @[lsu_bus_buffer.scala 467:68] + node _T_3607 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 467:97] + node _T_3608 = eq(_T_3607, UInt<1>("h00")) @[lsu_bus_buffer.scala 467:87] + node _T_3609 = and(_T_3606, _T_3608) @[lsu_bus_buffer.scala 467:85] node _T_3610 = eq(buf_dualtag[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] node _T_3611 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 57:129] node _T_3612 = eq(buf_dualtag[0], UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] @@ -99167,265 +99164,265 @@ circuit quasar_wrapper : node _T_3624 = or(_T_3623, _T_3621) @[Mux.scala 27:72] wire _T_3625 : UInt<1> @[Mux.scala 27:72] _T_3625 <= _T_3624 @[Mux.scala 27:72] - node _T_3626 = and(_T_3609, _T_3625) @[lsu_bus_buffer.scala 468:101] - node _T_3627 = eq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[lsu_bus_buffer.scala 468:167] - node _T_3628 = and(_T_3626, _T_3627) @[lsu_bus_buffer.scala 468:138] - node _T_3629 = and(_T_3628, any_done_wait_state) @[lsu_bus_buffer.scala 468:187] - node _T_3630 = or(_T_3604, _T_3629) @[lsu_bus_buffer.scala 468:53] - node _T_3631 = mux(_T_3630, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 468:16] - node _T_3632 = mux(_T_3602, UInt<3>("h04"), _T_3631) @[lsu_bus_buffer.scala 467:14] - node _T_3633 = mux(_T_3595, UInt<3>("h00"), _T_3632) @[lsu_bus_buffer.scala 466:31] - buf_nxtstate[0] <= _T_3633 @[lsu_bus_buffer.scala 466:25] - node _T_3634 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 469:73] - node _T_3635 = and(bus_rsp_write, _T_3634) @[lsu_bus_buffer.scala 469:52] - node _T_3636 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 470:46] - node _T_3637 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 471:23] - node _T_3638 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[lsu_bus_buffer.scala 471:47] - node _T_3639 = and(_T_3637, _T_3638) @[lsu_bus_buffer.scala 471:27] - node _T_3640 = or(_T_3636, _T_3639) @[lsu_bus_buffer.scala 470:77] - node _T_3641 = and(buf_dual[0], buf_dualhi[0]) @[lsu_bus_buffer.scala 472:26] - node _T_3642 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 472:54] - node _T_3643 = not(_T_3642) @[lsu_bus_buffer.scala 472:44] - node _T_3644 = and(_T_3641, _T_3643) @[lsu_bus_buffer.scala 472:42] - node _T_3645 = and(_T_3644, buf_samedw[0]) @[lsu_bus_buffer.scala 472:58] - node _T_3646 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[lsu_bus_buffer.scala 472:94] - node _T_3647 = and(_T_3645, _T_3646) @[lsu_bus_buffer.scala 472:74] - node _T_3648 = or(_T_3640, _T_3647) @[lsu_bus_buffer.scala 471:71] - node _T_3649 = and(bus_rsp_read, _T_3648) @[lsu_bus_buffer.scala 470:25] - node _T_3650 = or(_T_3635, _T_3649) @[lsu_bus_buffer.scala 469:105] - buf_resp_state_bus_en[0] <= _T_3650 @[lsu_bus_buffer.scala 469:34] - buf_state_bus_en[0] <= buf_resp_state_bus_en[0] @[lsu_bus_buffer.scala 473:29] - node _T_3651 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 474:49] - node _T_3652 = or(_T_3651, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 474:70] - buf_state_en[0] <= _T_3652 @[lsu_bus_buffer.scala 474:25] - node _T_3653 = and(buf_state_bus_en[0], bus_rsp_read) @[lsu_bus_buffer.scala 475:47] - node _T_3654 = and(_T_3653, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 475:62] - buf_data_en[0] <= _T_3654 @[lsu_bus_buffer.scala 475:24] - node _T_3655 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 476:48] - node _T_3656 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 476:111] - node _T_3657 = and(bus_rsp_read_error, _T_3656) @[lsu_bus_buffer.scala 476:91] - node _T_3658 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 477:42] - node _T_3659 = and(bus_rsp_read_error, _T_3658) @[lsu_bus_buffer.scala 477:31] - node _T_3660 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[lsu_bus_buffer.scala 477:66] - node _T_3661 = and(_T_3659, _T_3660) @[lsu_bus_buffer.scala 477:46] - node _T_3662 = or(_T_3657, _T_3661) @[lsu_bus_buffer.scala 476:143] - node _T_3663 = and(bus_rsp_write_error, UInt<1>("h01")) @[lsu_bus_buffer.scala 478:32] - node _T_3664 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 478:74] - node _T_3665 = and(_T_3663, _T_3664) @[lsu_bus_buffer.scala 478:53] - node _T_3666 = or(_T_3662, _T_3665) @[lsu_bus_buffer.scala 477:88] - node _T_3667 = and(_T_3655, _T_3666) @[lsu_bus_buffer.scala 476:68] - buf_error_en[0] <= _T_3667 @[lsu_bus_buffer.scala 476:25] - node _T_3668 = eq(buf_error_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 479:50] - node _T_3669 = and(buf_state_en[0], _T_3668) @[lsu_bus_buffer.scala 479:48] - node _T_3670 = bits(buf_addr[0], 2, 2) @[lsu_bus_buffer.scala 479:84] - node _T_3671 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 479:102] - node _T_3672 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 479:125] - node _T_3673 = mux(_T_3670, _T_3671, _T_3672) @[lsu_bus_buffer.scala 479:72] - node _T_3674 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 479:148] - node _T_3675 = mux(_T_3669, _T_3673, _T_3674) @[lsu_bus_buffer.scala 479:30] - buf_data_in[0] <= _T_3675 @[lsu_bus_buffer.scala 479:24] + node _T_3626 = and(_T_3609, _T_3625) @[lsu_bus_buffer.scala 467:101] + node _T_3627 = eq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[lsu_bus_buffer.scala 467:167] + node _T_3628 = and(_T_3626, _T_3627) @[lsu_bus_buffer.scala 467:138] + node _T_3629 = and(_T_3628, any_done_wait_state) @[lsu_bus_buffer.scala 467:187] + node _T_3630 = or(_T_3604, _T_3629) @[lsu_bus_buffer.scala 467:53] + node _T_3631 = mux(_T_3630, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 467:16] + node _T_3632 = mux(_T_3602, UInt<3>("h04"), _T_3631) @[lsu_bus_buffer.scala 466:14] + node _T_3633 = mux(_T_3595, UInt<3>("h00"), _T_3632) @[lsu_bus_buffer.scala 465:31] + buf_nxtstate[0] <= _T_3633 @[lsu_bus_buffer.scala 465:25] + node _T_3634 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 468:73] + node _T_3635 = and(bus_rsp_write, _T_3634) @[lsu_bus_buffer.scala 468:52] + node _T_3636 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 469:46] + node _T_3637 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 470:23] + node _T_3638 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[lsu_bus_buffer.scala 470:47] + node _T_3639 = and(_T_3637, _T_3638) @[lsu_bus_buffer.scala 470:27] + node _T_3640 = or(_T_3636, _T_3639) @[lsu_bus_buffer.scala 469:77] + node _T_3641 = and(buf_dual[0], buf_dualhi[0]) @[lsu_bus_buffer.scala 471:26] + node _T_3642 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 471:54] + node _T_3643 = not(_T_3642) @[lsu_bus_buffer.scala 471:44] + node _T_3644 = and(_T_3641, _T_3643) @[lsu_bus_buffer.scala 471:42] + node _T_3645 = and(_T_3644, buf_samedw[0]) @[lsu_bus_buffer.scala 471:58] + node _T_3646 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[lsu_bus_buffer.scala 471:94] + node _T_3647 = and(_T_3645, _T_3646) @[lsu_bus_buffer.scala 471:74] + node _T_3648 = or(_T_3640, _T_3647) @[lsu_bus_buffer.scala 470:71] + node _T_3649 = and(bus_rsp_read, _T_3648) @[lsu_bus_buffer.scala 469:25] + node _T_3650 = or(_T_3635, _T_3649) @[lsu_bus_buffer.scala 468:105] + buf_resp_state_bus_en[0] <= _T_3650 @[lsu_bus_buffer.scala 468:34] + buf_state_bus_en[0] <= buf_resp_state_bus_en[0] @[lsu_bus_buffer.scala 472:29] + node _T_3651 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 473:49] + node _T_3652 = or(_T_3651, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 473:70] + buf_state_en[0] <= _T_3652 @[lsu_bus_buffer.scala 473:25] + node _T_3653 = and(buf_state_bus_en[0], bus_rsp_read) @[lsu_bus_buffer.scala 474:47] + node _T_3654 = and(_T_3653, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 474:62] + buf_data_en[0] <= _T_3654 @[lsu_bus_buffer.scala 474:24] + node _T_3655 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 475:48] + node _T_3656 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 475:111] + node _T_3657 = and(bus_rsp_read_error, _T_3656) @[lsu_bus_buffer.scala 475:91] + node _T_3658 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 476:42] + node _T_3659 = and(bus_rsp_read_error, _T_3658) @[lsu_bus_buffer.scala 476:31] + node _T_3660 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[lsu_bus_buffer.scala 476:66] + node _T_3661 = and(_T_3659, _T_3660) @[lsu_bus_buffer.scala 476:46] + node _T_3662 = or(_T_3657, _T_3661) @[lsu_bus_buffer.scala 475:143] + node _T_3663 = and(bus_rsp_write_error, UInt<1>("h01")) @[lsu_bus_buffer.scala 477:32] + node _T_3664 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[lsu_bus_buffer.scala 477:74] + node _T_3665 = and(_T_3663, _T_3664) @[lsu_bus_buffer.scala 477:53] + node _T_3666 = or(_T_3662, _T_3665) @[lsu_bus_buffer.scala 476:88] + node _T_3667 = and(_T_3655, _T_3666) @[lsu_bus_buffer.scala 475:68] + buf_error_en[0] <= _T_3667 @[lsu_bus_buffer.scala 475:25] + node _T_3668 = eq(buf_error_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 478:50] + node _T_3669 = and(buf_state_en[0], _T_3668) @[lsu_bus_buffer.scala 478:48] + node _T_3670 = bits(buf_addr[0], 2, 2) @[lsu_bus_buffer.scala 478:84] + node _T_3671 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 478:102] + node _T_3672 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 478:125] + node _T_3673 = mux(_T_3670, _T_3671, _T_3672) @[lsu_bus_buffer.scala 478:72] + node _T_3674 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 478:148] + node _T_3675 = mux(_T_3669, _T_3673, _T_3674) @[lsu_bus_buffer.scala 478:30] + buf_data_in[0] <= _T_3675 @[lsu_bus_buffer.scala 478:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3676 = eq(UInt<3>("h04"), buf_state[0]) @[Conditional.scala 37:30] when _T_3676 : @[Conditional.scala 39:67] - node _T_3677 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 482:60] - node _T_3678 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 482:86] - node _T_3679 = dshr(buf_ldfwd, buf_dualtag[0]) @[lsu_bus_buffer.scala 482:101] - node _T_3680 = bits(_T_3679, 0, 0) @[lsu_bus_buffer.scala 482:101] - node _T_3681 = or(_T_3678, _T_3680) @[lsu_bus_buffer.scala 482:90] - node _T_3682 = or(_T_3681, any_done_wait_state) @[lsu_bus_buffer.scala 482:118] - node _T_3683 = mux(_T_3682, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 482:75] - node _T_3684 = mux(_T_3677, UInt<3>("h00"), _T_3683) @[lsu_bus_buffer.scala 482:31] - buf_nxtstate[0] <= _T_3684 @[lsu_bus_buffer.scala 482:25] - node _T_3685 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[lsu_bus_buffer.scala 483:66] - node _T_3686 = dshr(buf_ldfwd, buf_dualtag[0]) @[lsu_bus_buffer.scala 484:21] - node _T_3687 = bits(_T_3686, 0, 0) @[lsu_bus_buffer.scala 484:21] - node _T_3688 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[0]]) @[lsu_bus_buffer.scala 484:58] - node _T_3689 = and(_T_3687, _T_3688) @[lsu_bus_buffer.scala 484:38] - node _T_3690 = or(_T_3685, _T_3689) @[lsu_bus_buffer.scala 483:95] - node _T_3691 = and(bus_rsp_read, _T_3690) @[lsu_bus_buffer.scala 483:45] - buf_state_bus_en[0] <= _T_3691 @[lsu_bus_buffer.scala 483:29] - node _T_3692 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 485:49] - node _T_3693 = or(_T_3692, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 485:70] - buf_state_en[0] <= _T_3693 @[lsu_bus_buffer.scala 485:25] + node _T_3677 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 481:60] + node _T_3678 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 481:86] + node _T_3679 = dshr(buf_ldfwd, buf_dualtag[0]) @[lsu_bus_buffer.scala 481:101] + node _T_3680 = bits(_T_3679, 0, 0) @[lsu_bus_buffer.scala 481:101] + node _T_3681 = or(_T_3678, _T_3680) @[lsu_bus_buffer.scala 481:90] + node _T_3682 = or(_T_3681, any_done_wait_state) @[lsu_bus_buffer.scala 481:118] + node _T_3683 = mux(_T_3682, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 481:75] + node _T_3684 = mux(_T_3677, UInt<3>("h00"), _T_3683) @[lsu_bus_buffer.scala 481:31] + buf_nxtstate[0] <= _T_3684 @[lsu_bus_buffer.scala 481:25] + node _T_3685 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[lsu_bus_buffer.scala 482:66] + node _T_3686 = dshr(buf_ldfwd, buf_dualtag[0]) @[lsu_bus_buffer.scala 483:21] + node _T_3687 = bits(_T_3686, 0, 0) @[lsu_bus_buffer.scala 483:21] + node _T_3688 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[0]]) @[lsu_bus_buffer.scala 483:58] + node _T_3689 = and(_T_3687, _T_3688) @[lsu_bus_buffer.scala 483:38] + node _T_3690 = or(_T_3685, _T_3689) @[lsu_bus_buffer.scala 482:95] + node _T_3691 = and(bus_rsp_read, _T_3690) @[lsu_bus_buffer.scala 482:45] + buf_state_bus_en[0] <= _T_3691 @[lsu_bus_buffer.scala 482:29] + node _T_3692 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 484:49] + node _T_3693 = or(_T_3692, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 484:70] + buf_state_en[0] <= _T_3693 @[lsu_bus_buffer.scala 484:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3694 = eq(UInt<3>("h05"), buf_state[0]) @[Conditional.scala 37:30] when _T_3694 : @[Conditional.scala 39:67] - node _T_3695 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 488:60] - node _T_3696 = mux(_T_3695, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 488:31] - buf_nxtstate[0] <= _T_3696 @[lsu_bus_buffer.scala 488:25] - node _T_3697 = eq(RspPtr, UInt<2>("h00")) @[lsu_bus_buffer.scala 489:37] - node _T_3698 = eq(buf_dualtag[0], RspPtr) @[lsu_bus_buffer.scala 489:98] - node _T_3699 = and(buf_dual[0], _T_3698) @[lsu_bus_buffer.scala 489:80] - node _T_3700 = or(_T_3697, _T_3699) @[lsu_bus_buffer.scala 489:65] - node _T_3701 = or(_T_3700, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 489:112] - buf_state_en[0] <= _T_3701 @[lsu_bus_buffer.scala 489:25] + node _T_3695 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 487:60] + node _T_3696 = mux(_T_3695, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 487:31] + buf_nxtstate[0] <= _T_3696 @[lsu_bus_buffer.scala 487:25] + node _T_3697 = eq(RspPtr, UInt<2>("h00")) @[lsu_bus_buffer.scala 488:37] + node _T_3698 = eq(buf_dualtag[0], RspPtr) @[lsu_bus_buffer.scala 488:98] + node _T_3699 = and(buf_dual[0], _T_3698) @[lsu_bus_buffer.scala 488:80] + node _T_3700 = or(_T_3697, _T_3699) @[lsu_bus_buffer.scala 488:65] + node _T_3701 = or(_T_3700, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 488:112] + buf_state_en[0] <= _T_3701 @[lsu_bus_buffer.scala 488:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3702 = eq(UInt<3>("h06"), buf_state[0]) @[Conditional.scala 37:30] when _T_3702 : @[Conditional.scala 39:67] - buf_nxtstate[0] <= UInt<3>("h00") @[lsu_bus_buffer.scala 492:25] - buf_rst[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 493:20] - buf_state_en[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 494:25] - buf_ldfwd_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 495:25] - buf_ldfwd_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 496:25] + buf_nxtstate[0] <= UInt<3>("h00") @[lsu_bus_buffer.scala 491:25] + buf_rst[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 492:20] + buf_state_en[0] <= UInt<1>("h01") @[lsu_bus_buffer.scala 493:25] + buf_ldfwd_in[0] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:25] + buf_ldfwd_en[0] <= buf_state_en[0] @[lsu_bus_buffer.scala 495:25] skip @[Conditional.scala 39:67] - node _T_3703 = bits(buf_state_en[0], 0, 0) @[lsu_bus_buffer.scala 499:108] + node _T_3703 = bits(buf_state_en[0], 0, 0) @[lsu_bus_buffer.scala 498:108] reg _T_3704 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3703 : @[Reg.scala 28:19] _T_3704 <= buf_nxtstate[0] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_state[0] <= _T_3704 @[lsu_bus_buffer.scala 499:18] - reg _T_3705 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 500:60] - _T_3705 <= buf_age_in_0 @[lsu_bus_buffer.scala 500:60] - buf_ageQ[0] <= _T_3705 @[lsu_bus_buffer.scala 500:17] - reg _T_3706 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 501:63] - _T_3706 <= buf_rspage_in[0] @[lsu_bus_buffer.scala 501:63] - buf_rspageQ[0] <= _T_3706 @[lsu_bus_buffer.scala 501:20] - node _T_3707 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 502:109] + buf_state[0] <= _T_3704 @[lsu_bus_buffer.scala 498:18] + reg _T_3705 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 499:60] + _T_3705 <= buf_age_in_0 @[lsu_bus_buffer.scala 499:60] + buf_ageQ[0] <= _T_3705 @[lsu_bus_buffer.scala 499:17] + reg _T_3706 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 500:63] + _T_3706 <= buf_rspage_in[0] @[lsu_bus_buffer.scala 500:63] + buf_rspageQ[0] <= _T_3706 @[lsu_bus_buffer.scala 500:20] + node _T_3707 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 501:109] reg _T_3708 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3707 : @[Reg.scala 28:19] _T_3708 <= buf_dualtag_in[0] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dualtag[0] <= _T_3708 @[lsu_bus_buffer.scala 502:20] - node _T_3709 = bits(buf_dual_in, 0, 0) @[lsu_bus_buffer.scala 503:74] - node _T_3710 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 503:107] + buf_dualtag[0] <= _T_3708 @[lsu_bus_buffer.scala 501:20] + node _T_3709 = bits(buf_dual_in, 0, 0) @[lsu_bus_buffer.scala 502:74] + node _T_3710 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 502:107] reg _T_3711 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3710 : @[Reg.scala 28:19] _T_3711 <= _T_3709 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dual[0] <= _T_3711 @[lsu_bus_buffer.scala 503:17] - node _T_3712 = bits(buf_samedw_in, 0, 0) @[lsu_bus_buffer.scala 504:78] - node _T_3713 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 504:111] + buf_dual[0] <= _T_3711 @[lsu_bus_buffer.scala 502:17] + node _T_3712 = bits(buf_samedw_in, 0, 0) @[lsu_bus_buffer.scala 503:78] + node _T_3713 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 503:111] reg _T_3714 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3713 : @[Reg.scala 28:19] _T_3714 <= _T_3712 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_samedw[0] <= _T_3714 @[lsu_bus_buffer.scala 504:19] - node _T_3715 = bits(buf_nomerge_in, 0, 0) @[lsu_bus_buffer.scala 505:80] - node _T_3716 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 505:113] + buf_samedw[0] <= _T_3714 @[lsu_bus_buffer.scala 503:19] + node _T_3715 = bits(buf_nomerge_in, 0, 0) @[lsu_bus_buffer.scala 504:80] + node _T_3716 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 504:113] reg _T_3717 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3716 : @[Reg.scala 28:19] _T_3717 <= _T_3715 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_nomerge[0] <= _T_3717 @[lsu_bus_buffer.scala 505:20] - node _T_3718 = bits(buf_dualhi_in, 0, 0) @[lsu_bus_buffer.scala 506:78] - node _T_3719 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 506:111] + buf_nomerge[0] <= _T_3717 @[lsu_bus_buffer.scala 504:20] + node _T_3718 = bits(buf_dualhi_in, 0, 0) @[lsu_bus_buffer.scala 505:78] + node _T_3719 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 505:111] reg _T_3720 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3719 : @[Reg.scala 28:19] _T_3720 <= _T_3718 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dualhi[0] <= _T_3720 @[lsu_bus_buffer.scala 506:19] + buf_dualhi[0] <= _T_3720 @[lsu_bus_buffer.scala 505:19] node _T_3721 = eq(UInt<3>("h00"), buf_state[1]) @[Conditional.scala 37:30] when _T_3721 : @[Conditional.scala 40:58] - node _T_3722 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 443:56] - node _T_3723 = mux(_T_3722, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 443:31] - buf_nxtstate[1] <= _T_3723 @[lsu_bus_buffer.scala 443:25] - node _T_3724 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 444:45] - node _T_3725 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 444:77] - node _T_3726 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 444:97] - node _T_3727 = and(_T_3725, _T_3726) @[lsu_bus_buffer.scala 444:95] - node _T_3728 = eq(UInt<1>("h01"), WrPtr0_r) @[lsu_bus_buffer.scala 444:117] - node _T_3729 = and(_T_3727, _T_3728) @[lsu_bus_buffer.scala 444:112] - node _T_3730 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 444:144] - node _T_3731 = eq(UInt<1>("h01"), WrPtr1_r) @[lsu_bus_buffer.scala 444:166] - node _T_3732 = and(_T_3730, _T_3731) @[lsu_bus_buffer.scala 444:161] - node _T_3733 = or(_T_3729, _T_3732) @[lsu_bus_buffer.scala 444:132] - node _T_3734 = and(_T_3724, _T_3733) @[lsu_bus_buffer.scala 444:63] - node _T_3735 = eq(UInt<1>("h01"), ibuf_tag) @[lsu_bus_buffer.scala 444:206] - node _T_3736 = and(ibuf_drain_vld, _T_3735) @[lsu_bus_buffer.scala 444:201] - node _T_3737 = or(_T_3734, _T_3736) @[lsu_bus_buffer.scala 444:183] - buf_state_en[1] <= _T_3737 @[lsu_bus_buffer.scala 444:25] - buf_wr_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 445:22] - buf_data_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 446:24] - node _T_3738 = eq(UInt<1>("h01"), ibuf_tag) @[lsu_bus_buffer.scala 447:52] - node _T_3739 = and(ibuf_drain_vld, _T_3738) @[lsu_bus_buffer.scala 447:47] - node _T_3740 = bits(_T_3739, 0, 0) @[lsu_bus_buffer.scala 447:73] - node _T_3741 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 447:90] - node _T_3742 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 447:114] - node _T_3743 = mux(_T_3740, _T_3741, _T_3742) @[lsu_bus_buffer.scala 447:30] - buf_data_in[1] <= _T_3743 @[lsu_bus_buffer.scala 447:24] + node _T_3722 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 442:56] + node _T_3723 = mux(_T_3722, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 442:31] + buf_nxtstate[1] <= _T_3723 @[lsu_bus_buffer.scala 442:25] + node _T_3724 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 443:45] + node _T_3725 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:77] + node _T_3726 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 443:97] + node _T_3727 = and(_T_3725, _T_3726) @[lsu_bus_buffer.scala 443:95] + node _T_3728 = eq(UInt<1>("h01"), WrPtr0_r) @[lsu_bus_buffer.scala 443:117] + node _T_3729 = and(_T_3727, _T_3728) @[lsu_bus_buffer.scala 443:112] + node _T_3730 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:144] + node _T_3731 = eq(UInt<1>("h01"), WrPtr1_r) @[lsu_bus_buffer.scala 443:166] + node _T_3732 = and(_T_3730, _T_3731) @[lsu_bus_buffer.scala 443:161] + node _T_3733 = or(_T_3729, _T_3732) @[lsu_bus_buffer.scala 443:132] + node _T_3734 = and(_T_3724, _T_3733) @[lsu_bus_buffer.scala 443:63] + node _T_3735 = eq(UInt<1>("h01"), ibuf_tag) @[lsu_bus_buffer.scala 443:206] + node _T_3736 = and(ibuf_drain_vld, _T_3735) @[lsu_bus_buffer.scala 443:201] + node _T_3737 = or(_T_3734, _T_3736) @[lsu_bus_buffer.scala 443:183] + buf_state_en[1] <= _T_3737 @[lsu_bus_buffer.scala 443:25] + buf_wr_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 444:22] + buf_data_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 445:24] + node _T_3738 = eq(UInt<1>("h01"), ibuf_tag) @[lsu_bus_buffer.scala 446:52] + node _T_3739 = and(ibuf_drain_vld, _T_3738) @[lsu_bus_buffer.scala 446:47] + node _T_3740 = bits(_T_3739, 0, 0) @[lsu_bus_buffer.scala 446:73] + node _T_3741 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 446:90] + node _T_3742 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 446:114] + node _T_3743 = mux(_T_3740, _T_3741, _T_3742) @[lsu_bus_buffer.scala 446:30] + buf_data_in[1] <= _T_3743 @[lsu_bus_buffer.scala 446:24] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_3744 = eq(UInt<3>("h01"), buf_state[1]) @[Conditional.scala 37:30] when _T_3744 : @[Conditional.scala 39:67] - node _T_3745 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 450:60] - node _T_3746 = mux(_T_3745, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 450:31] - buf_nxtstate[1] <= _T_3746 @[lsu_bus_buffer.scala 450:25] - node _T_3747 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 451:46] - buf_state_en[1] <= _T_3747 @[lsu_bus_buffer.scala 451:25] + node _T_3745 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 449:60] + node _T_3746 = mux(_T_3745, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 449:31] + buf_nxtstate[1] <= _T_3746 @[lsu_bus_buffer.scala 449:25] + node _T_3747 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 450:46] + buf_state_en[1] <= _T_3747 @[lsu_bus_buffer.scala 450:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3748 = eq(UInt<3>("h02"), buf_state[1]) @[Conditional.scala 37:30] when _T_3748 : @[Conditional.scala 39:67] - node _T_3749 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 454:60] - node _T_3750 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 454:89] - node _T_3751 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 454:124] - node _T_3752 = and(_T_3750, _T_3751) @[lsu_bus_buffer.scala 454:104] - node _T_3753 = mux(_T_3752, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 454:75] - node _T_3754 = mux(_T_3749, UInt<3>("h00"), _T_3753) @[lsu_bus_buffer.scala 454:31] - buf_nxtstate[1] <= _T_3754 @[lsu_bus_buffer.scala 454:25] - node _T_3755 = eq(obuf_tag0, UInt<3>("h01")) @[lsu_bus_buffer.scala 455:48] - node _T_3756 = eq(obuf_tag1, UInt<3>("h01")) @[lsu_bus_buffer.scala 455:104] - node _T_3757 = and(obuf_merge, _T_3756) @[lsu_bus_buffer.scala 455:91] - node _T_3758 = or(_T_3755, _T_3757) @[lsu_bus_buffer.scala 455:77] - node _T_3759 = and(_T_3758, obuf_valid) @[lsu_bus_buffer.scala 455:135] - node _T_3760 = and(_T_3759, obuf_wr_enQ) @[lsu_bus_buffer.scala 455:148] - buf_cmd_state_bus_en[1] <= _T_3760 @[lsu_bus_buffer.scala 455:33] - buf_state_bus_en[1] <= buf_cmd_state_bus_en[1] @[lsu_bus_buffer.scala 456:29] - node _T_3761 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 457:49] - node _T_3762 = or(_T_3761, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 457:70] - buf_state_en[1] <= _T_3762 @[lsu_bus_buffer.scala 457:25] - buf_ldfwd_in[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 458:25] - node _T_3763 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 459:56] - node _T_3764 = eq(_T_3763, UInt<1>("h00")) @[lsu_bus_buffer.scala 459:46] - node _T_3765 = and(buf_state_en[1], _T_3764) @[lsu_bus_buffer.scala 459:44] - node _T_3766 = and(_T_3765, obuf_nosend) @[lsu_bus_buffer.scala 459:60] - node _T_3767 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 459:76] - node _T_3768 = and(_T_3766, _T_3767) @[lsu_bus_buffer.scala 459:74] - buf_ldfwd_en[1] <= _T_3768 @[lsu_bus_buffer.scala 459:25] - node _T_3769 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 460:46] - buf_ldfwdtag_in[1] <= _T_3769 @[lsu_bus_buffer.scala 460:28] - node _T_3770 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 461:47] - node _T_3771 = and(_T_3770, obuf_nosend) @[lsu_bus_buffer.scala 461:67] - node _T_3772 = and(_T_3771, bus_rsp_read) @[lsu_bus_buffer.scala 461:81] - buf_data_en[1] <= _T_3772 @[lsu_bus_buffer.scala 461:24] - node _T_3773 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:48] - node _T_3774 = and(_T_3773, obuf_nosend) @[lsu_bus_buffer.scala 462:68] - node _T_3775 = and(_T_3774, bus_rsp_read_error) @[lsu_bus_buffer.scala 462:82] - buf_error_en[1] <= _T_3775 @[lsu_bus_buffer.scala 462:25] - node _T_3776 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 463:61] - node _T_3777 = bits(buf_addr[1], 2, 2) @[lsu_bus_buffer.scala 463:85] - node _T_3778 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 463:103] - node _T_3779 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 463:126] - node _T_3780 = mux(_T_3777, _T_3778, _T_3779) @[lsu_bus_buffer.scala 463:73] - node _T_3781 = mux(buf_error_en[1], _T_3776, _T_3780) @[lsu_bus_buffer.scala 463:30] - buf_data_in[1] <= _T_3781 @[lsu_bus_buffer.scala 463:24] + node _T_3749 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_3750 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 453:89] + node _T_3751 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 453:124] + node _T_3752 = and(_T_3750, _T_3751) @[lsu_bus_buffer.scala 453:104] + node _T_3753 = mux(_T_3752, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 453:75] + node _T_3754 = mux(_T_3749, UInt<3>("h00"), _T_3753) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[1] <= _T_3754 @[lsu_bus_buffer.scala 453:25] + node _T_3755 = eq(obuf_tag0, UInt<3>("h01")) @[lsu_bus_buffer.scala 454:48] + node _T_3756 = eq(obuf_tag1, UInt<3>("h01")) @[lsu_bus_buffer.scala 454:104] + node _T_3757 = and(obuf_merge, _T_3756) @[lsu_bus_buffer.scala 454:91] + node _T_3758 = or(_T_3755, _T_3757) @[lsu_bus_buffer.scala 454:77] + node _T_3759 = and(_T_3758, obuf_valid) @[lsu_bus_buffer.scala 454:135] + node _T_3760 = and(_T_3759, obuf_wr_enQ) @[lsu_bus_buffer.scala 454:148] + buf_cmd_state_bus_en[1] <= _T_3760 @[lsu_bus_buffer.scala 454:33] + buf_state_bus_en[1] <= buf_cmd_state_bus_en[1] @[lsu_bus_buffer.scala 455:29] + node _T_3761 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 456:49] + node _T_3762 = or(_T_3761, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 456:70] + buf_state_en[1] <= _T_3762 @[lsu_bus_buffer.scala 456:25] + buf_ldfwd_in[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 457:25] + node _T_3763 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 458:56] + node _T_3764 = eq(_T_3763, UInt<1>("h00")) @[lsu_bus_buffer.scala 458:46] + node _T_3765 = and(buf_state_en[1], _T_3764) @[lsu_bus_buffer.scala 458:44] + node _T_3766 = and(_T_3765, obuf_nosend) @[lsu_bus_buffer.scala 458:60] + node _T_3767 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 458:76] + node _T_3768 = and(_T_3766, _T_3767) @[lsu_bus_buffer.scala 458:74] + buf_ldfwd_en[1] <= _T_3768 @[lsu_bus_buffer.scala 458:25] + node _T_3769 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 459:46] + buf_ldfwdtag_in[1] <= _T_3769 @[lsu_bus_buffer.scala 459:28] + node _T_3770 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 460:47] + node _T_3771 = and(_T_3770, obuf_nosend) @[lsu_bus_buffer.scala 460:67] + node _T_3772 = and(_T_3771, bus_rsp_read) @[lsu_bus_buffer.scala 460:81] + buf_data_en[1] <= _T_3772 @[lsu_bus_buffer.scala 460:24] + node _T_3773 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 461:48] + node _T_3774 = and(_T_3773, obuf_nosend) @[lsu_bus_buffer.scala 461:68] + node _T_3775 = and(_T_3774, bus_rsp_read_error) @[lsu_bus_buffer.scala 461:82] + buf_error_en[1] <= _T_3775 @[lsu_bus_buffer.scala 461:25] + node _T_3776 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 462:61] + node _T_3777 = bits(buf_addr[1], 2, 2) @[lsu_bus_buffer.scala 462:85] + node _T_3778 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 462:103] + node _T_3779 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 462:126] + node _T_3780 = mux(_T_3777, _T_3778, _T_3779) @[lsu_bus_buffer.scala 462:73] + node _T_3781 = mux(buf_error_en[1], _T_3776, _T_3780) @[lsu_bus_buffer.scala 462:30] + buf_data_in[1] <= _T_3781 @[lsu_bus_buffer.scala 462:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3782 = eq(UInt<3>("h03"), buf_state[1]) @[Conditional.scala 37:30] when _T_3782 : @[Conditional.scala 39:67] - node _T_3783 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 466:67] - node _T_3784 = and(UInt<1>("h01"), bus_rsp_write_error) @[lsu_bus_buffer.scala 466:94] - node _T_3785 = eq(_T_3784, UInt<1>("h00")) @[lsu_bus_buffer.scala 466:73] - node _T_3786 = and(_T_3783, _T_3785) @[lsu_bus_buffer.scala 466:71] - node _T_3787 = or(io.dec_tlu_force_halt, _T_3786) @[lsu_bus_buffer.scala 466:55] - node _T_3788 = bits(_T_3787, 0, 0) @[lsu_bus_buffer.scala 466:125] - node _T_3789 = eq(buf_samedw[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 467:30] - node _T_3790 = and(buf_dual[1], _T_3789) @[lsu_bus_buffer.scala 467:28] - node _T_3791 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 467:57] - node _T_3792 = eq(_T_3791, UInt<1>("h00")) @[lsu_bus_buffer.scala 467:47] - node _T_3793 = and(_T_3790, _T_3792) @[lsu_bus_buffer.scala 467:45] - node _T_3794 = neq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[lsu_bus_buffer.scala 467:90] - node _T_3795 = and(_T_3793, _T_3794) @[lsu_bus_buffer.scala 467:61] - node _T_3796 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 468:27] - node _T_3797 = or(_T_3796, any_done_wait_state) @[lsu_bus_buffer.scala 468:31] - node _T_3798 = eq(buf_samedw[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 468:70] - node _T_3799 = and(buf_dual[1], _T_3798) @[lsu_bus_buffer.scala 468:68] - node _T_3800 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 468:97] - node _T_3801 = eq(_T_3800, UInt<1>("h00")) @[lsu_bus_buffer.scala 468:87] - node _T_3802 = and(_T_3799, _T_3801) @[lsu_bus_buffer.scala 468:85] + node _T_3783 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 465:67] + node _T_3784 = and(UInt<1>("h01"), bus_rsp_write_error) @[lsu_bus_buffer.scala 465:94] + node _T_3785 = eq(_T_3784, UInt<1>("h00")) @[lsu_bus_buffer.scala 465:73] + node _T_3786 = and(_T_3783, _T_3785) @[lsu_bus_buffer.scala 465:71] + node _T_3787 = or(io.dec_tlu_force_halt, _T_3786) @[lsu_bus_buffer.scala 465:55] + node _T_3788 = bits(_T_3787, 0, 0) @[lsu_bus_buffer.scala 465:125] + node _T_3789 = eq(buf_samedw[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 466:30] + node _T_3790 = and(buf_dual[1], _T_3789) @[lsu_bus_buffer.scala 466:28] + node _T_3791 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 466:57] + node _T_3792 = eq(_T_3791, UInt<1>("h00")) @[lsu_bus_buffer.scala 466:47] + node _T_3793 = and(_T_3790, _T_3792) @[lsu_bus_buffer.scala 466:45] + node _T_3794 = neq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[lsu_bus_buffer.scala 466:90] + node _T_3795 = and(_T_3793, _T_3794) @[lsu_bus_buffer.scala 466:61] + node _T_3796 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 467:27] + node _T_3797 = or(_T_3796, any_done_wait_state) @[lsu_bus_buffer.scala 467:31] + node _T_3798 = eq(buf_samedw[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 467:70] + node _T_3799 = and(buf_dual[1], _T_3798) @[lsu_bus_buffer.scala 467:68] + node _T_3800 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 467:97] + node _T_3801 = eq(_T_3800, UInt<1>("h00")) @[lsu_bus_buffer.scala 467:87] + node _T_3802 = and(_T_3799, _T_3801) @[lsu_bus_buffer.scala 467:85] node _T_3803 = eq(buf_dualtag[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] node _T_3804 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 57:129] node _T_3805 = eq(buf_dualtag[1], UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] @@ -99443,265 +99440,265 @@ circuit quasar_wrapper : node _T_3817 = or(_T_3816, _T_3814) @[Mux.scala 27:72] wire _T_3818 : UInt<1> @[Mux.scala 27:72] _T_3818 <= _T_3817 @[Mux.scala 27:72] - node _T_3819 = and(_T_3802, _T_3818) @[lsu_bus_buffer.scala 468:101] - node _T_3820 = eq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[lsu_bus_buffer.scala 468:167] - node _T_3821 = and(_T_3819, _T_3820) @[lsu_bus_buffer.scala 468:138] - node _T_3822 = and(_T_3821, any_done_wait_state) @[lsu_bus_buffer.scala 468:187] - node _T_3823 = or(_T_3797, _T_3822) @[lsu_bus_buffer.scala 468:53] - node _T_3824 = mux(_T_3823, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 468:16] - node _T_3825 = mux(_T_3795, UInt<3>("h04"), _T_3824) @[lsu_bus_buffer.scala 467:14] - node _T_3826 = mux(_T_3788, UInt<3>("h00"), _T_3825) @[lsu_bus_buffer.scala 466:31] - buf_nxtstate[1] <= _T_3826 @[lsu_bus_buffer.scala 466:25] - node _T_3827 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 469:73] - node _T_3828 = and(bus_rsp_write, _T_3827) @[lsu_bus_buffer.scala 469:52] - node _T_3829 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 470:46] - node _T_3830 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 471:23] - node _T_3831 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[lsu_bus_buffer.scala 471:47] - node _T_3832 = and(_T_3830, _T_3831) @[lsu_bus_buffer.scala 471:27] - node _T_3833 = or(_T_3829, _T_3832) @[lsu_bus_buffer.scala 470:77] - node _T_3834 = and(buf_dual[1], buf_dualhi[1]) @[lsu_bus_buffer.scala 472:26] - node _T_3835 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 472:54] - node _T_3836 = not(_T_3835) @[lsu_bus_buffer.scala 472:44] - node _T_3837 = and(_T_3834, _T_3836) @[lsu_bus_buffer.scala 472:42] - node _T_3838 = and(_T_3837, buf_samedw[1]) @[lsu_bus_buffer.scala 472:58] - node _T_3839 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[lsu_bus_buffer.scala 472:94] - node _T_3840 = and(_T_3838, _T_3839) @[lsu_bus_buffer.scala 472:74] - node _T_3841 = or(_T_3833, _T_3840) @[lsu_bus_buffer.scala 471:71] - node _T_3842 = and(bus_rsp_read, _T_3841) @[lsu_bus_buffer.scala 470:25] - node _T_3843 = or(_T_3828, _T_3842) @[lsu_bus_buffer.scala 469:105] - buf_resp_state_bus_en[1] <= _T_3843 @[lsu_bus_buffer.scala 469:34] - buf_state_bus_en[1] <= buf_resp_state_bus_en[1] @[lsu_bus_buffer.scala 473:29] - node _T_3844 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 474:49] - node _T_3845 = or(_T_3844, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 474:70] - buf_state_en[1] <= _T_3845 @[lsu_bus_buffer.scala 474:25] - node _T_3846 = and(buf_state_bus_en[1], bus_rsp_read) @[lsu_bus_buffer.scala 475:47] - node _T_3847 = and(_T_3846, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 475:62] - buf_data_en[1] <= _T_3847 @[lsu_bus_buffer.scala 475:24] - node _T_3848 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 476:48] - node _T_3849 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 476:111] - node _T_3850 = and(bus_rsp_read_error, _T_3849) @[lsu_bus_buffer.scala 476:91] - node _T_3851 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 477:42] - node _T_3852 = and(bus_rsp_read_error, _T_3851) @[lsu_bus_buffer.scala 477:31] - node _T_3853 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[lsu_bus_buffer.scala 477:66] - node _T_3854 = and(_T_3852, _T_3853) @[lsu_bus_buffer.scala 477:46] - node _T_3855 = or(_T_3850, _T_3854) @[lsu_bus_buffer.scala 476:143] - node _T_3856 = and(bus_rsp_write_error, UInt<1>("h01")) @[lsu_bus_buffer.scala 478:32] - node _T_3857 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 478:74] - node _T_3858 = and(_T_3856, _T_3857) @[lsu_bus_buffer.scala 478:53] - node _T_3859 = or(_T_3855, _T_3858) @[lsu_bus_buffer.scala 477:88] - node _T_3860 = and(_T_3848, _T_3859) @[lsu_bus_buffer.scala 476:68] - buf_error_en[1] <= _T_3860 @[lsu_bus_buffer.scala 476:25] - node _T_3861 = eq(buf_error_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 479:50] - node _T_3862 = and(buf_state_en[1], _T_3861) @[lsu_bus_buffer.scala 479:48] - node _T_3863 = bits(buf_addr[1], 2, 2) @[lsu_bus_buffer.scala 479:84] - node _T_3864 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 479:102] - node _T_3865 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 479:125] - node _T_3866 = mux(_T_3863, _T_3864, _T_3865) @[lsu_bus_buffer.scala 479:72] - node _T_3867 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 479:148] - node _T_3868 = mux(_T_3862, _T_3866, _T_3867) @[lsu_bus_buffer.scala 479:30] - buf_data_in[1] <= _T_3868 @[lsu_bus_buffer.scala 479:24] + node _T_3819 = and(_T_3802, _T_3818) @[lsu_bus_buffer.scala 467:101] + node _T_3820 = eq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[lsu_bus_buffer.scala 467:167] + node _T_3821 = and(_T_3819, _T_3820) @[lsu_bus_buffer.scala 467:138] + node _T_3822 = and(_T_3821, any_done_wait_state) @[lsu_bus_buffer.scala 467:187] + node _T_3823 = or(_T_3797, _T_3822) @[lsu_bus_buffer.scala 467:53] + node _T_3824 = mux(_T_3823, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 467:16] + node _T_3825 = mux(_T_3795, UInt<3>("h04"), _T_3824) @[lsu_bus_buffer.scala 466:14] + node _T_3826 = mux(_T_3788, UInt<3>("h00"), _T_3825) @[lsu_bus_buffer.scala 465:31] + buf_nxtstate[1] <= _T_3826 @[lsu_bus_buffer.scala 465:25] + node _T_3827 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 468:73] + node _T_3828 = and(bus_rsp_write, _T_3827) @[lsu_bus_buffer.scala 468:52] + node _T_3829 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 469:46] + node _T_3830 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 470:23] + node _T_3831 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[lsu_bus_buffer.scala 470:47] + node _T_3832 = and(_T_3830, _T_3831) @[lsu_bus_buffer.scala 470:27] + node _T_3833 = or(_T_3829, _T_3832) @[lsu_bus_buffer.scala 469:77] + node _T_3834 = and(buf_dual[1], buf_dualhi[1]) @[lsu_bus_buffer.scala 471:26] + node _T_3835 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 471:54] + node _T_3836 = not(_T_3835) @[lsu_bus_buffer.scala 471:44] + node _T_3837 = and(_T_3834, _T_3836) @[lsu_bus_buffer.scala 471:42] + node _T_3838 = and(_T_3837, buf_samedw[1]) @[lsu_bus_buffer.scala 471:58] + node _T_3839 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[lsu_bus_buffer.scala 471:94] + node _T_3840 = and(_T_3838, _T_3839) @[lsu_bus_buffer.scala 471:74] + node _T_3841 = or(_T_3833, _T_3840) @[lsu_bus_buffer.scala 470:71] + node _T_3842 = and(bus_rsp_read, _T_3841) @[lsu_bus_buffer.scala 469:25] + node _T_3843 = or(_T_3828, _T_3842) @[lsu_bus_buffer.scala 468:105] + buf_resp_state_bus_en[1] <= _T_3843 @[lsu_bus_buffer.scala 468:34] + buf_state_bus_en[1] <= buf_resp_state_bus_en[1] @[lsu_bus_buffer.scala 472:29] + node _T_3844 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 473:49] + node _T_3845 = or(_T_3844, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 473:70] + buf_state_en[1] <= _T_3845 @[lsu_bus_buffer.scala 473:25] + node _T_3846 = and(buf_state_bus_en[1], bus_rsp_read) @[lsu_bus_buffer.scala 474:47] + node _T_3847 = and(_T_3846, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 474:62] + buf_data_en[1] <= _T_3847 @[lsu_bus_buffer.scala 474:24] + node _T_3848 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 475:48] + node _T_3849 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 475:111] + node _T_3850 = and(bus_rsp_read_error, _T_3849) @[lsu_bus_buffer.scala 475:91] + node _T_3851 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 476:42] + node _T_3852 = and(bus_rsp_read_error, _T_3851) @[lsu_bus_buffer.scala 476:31] + node _T_3853 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[lsu_bus_buffer.scala 476:66] + node _T_3854 = and(_T_3852, _T_3853) @[lsu_bus_buffer.scala 476:46] + node _T_3855 = or(_T_3850, _T_3854) @[lsu_bus_buffer.scala 475:143] + node _T_3856 = and(bus_rsp_write_error, UInt<1>("h01")) @[lsu_bus_buffer.scala 477:32] + node _T_3857 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[lsu_bus_buffer.scala 477:74] + node _T_3858 = and(_T_3856, _T_3857) @[lsu_bus_buffer.scala 477:53] + node _T_3859 = or(_T_3855, _T_3858) @[lsu_bus_buffer.scala 476:88] + node _T_3860 = and(_T_3848, _T_3859) @[lsu_bus_buffer.scala 475:68] + buf_error_en[1] <= _T_3860 @[lsu_bus_buffer.scala 475:25] + node _T_3861 = eq(buf_error_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 478:50] + node _T_3862 = and(buf_state_en[1], _T_3861) @[lsu_bus_buffer.scala 478:48] + node _T_3863 = bits(buf_addr[1], 2, 2) @[lsu_bus_buffer.scala 478:84] + node _T_3864 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 478:102] + node _T_3865 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 478:125] + node _T_3866 = mux(_T_3863, _T_3864, _T_3865) @[lsu_bus_buffer.scala 478:72] + node _T_3867 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 478:148] + node _T_3868 = mux(_T_3862, _T_3866, _T_3867) @[lsu_bus_buffer.scala 478:30] + buf_data_in[1] <= _T_3868 @[lsu_bus_buffer.scala 478:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3869 = eq(UInt<3>("h04"), buf_state[1]) @[Conditional.scala 37:30] when _T_3869 : @[Conditional.scala 39:67] - node _T_3870 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 482:60] - node _T_3871 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 482:86] - node _T_3872 = dshr(buf_ldfwd, buf_dualtag[1]) @[lsu_bus_buffer.scala 482:101] - node _T_3873 = bits(_T_3872, 0, 0) @[lsu_bus_buffer.scala 482:101] - node _T_3874 = or(_T_3871, _T_3873) @[lsu_bus_buffer.scala 482:90] - node _T_3875 = or(_T_3874, any_done_wait_state) @[lsu_bus_buffer.scala 482:118] - node _T_3876 = mux(_T_3875, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 482:75] - node _T_3877 = mux(_T_3870, UInt<3>("h00"), _T_3876) @[lsu_bus_buffer.scala 482:31] - buf_nxtstate[1] <= _T_3877 @[lsu_bus_buffer.scala 482:25] - node _T_3878 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[lsu_bus_buffer.scala 483:66] - node _T_3879 = dshr(buf_ldfwd, buf_dualtag[1]) @[lsu_bus_buffer.scala 484:21] - node _T_3880 = bits(_T_3879, 0, 0) @[lsu_bus_buffer.scala 484:21] - node _T_3881 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[1]]) @[lsu_bus_buffer.scala 484:58] - node _T_3882 = and(_T_3880, _T_3881) @[lsu_bus_buffer.scala 484:38] - node _T_3883 = or(_T_3878, _T_3882) @[lsu_bus_buffer.scala 483:95] - node _T_3884 = and(bus_rsp_read, _T_3883) @[lsu_bus_buffer.scala 483:45] - buf_state_bus_en[1] <= _T_3884 @[lsu_bus_buffer.scala 483:29] - node _T_3885 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 485:49] - node _T_3886 = or(_T_3885, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 485:70] - buf_state_en[1] <= _T_3886 @[lsu_bus_buffer.scala 485:25] + node _T_3870 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 481:60] + node _T_3871 = bits(buf_ldfwd, 1, 1) @[lsu_bus_buffer.scala 481:86] + node _T_3872 = dshr(buf_ldfwd, buf_dualtag[1]) @[lsu_bus_buffer.scala 481:101] + node _T_3873 = bits(_T_3872, 0, 0) @[lsu_bus_buffer.scala 481:101] + node _T_3874 = or(_T_3871, _T_3873) @[lsu_bus_buffer.scala 481:90] + node _T_3875 = or(_T_3874, any_done_wait_state) @[lsu_bus_buffer.scala 481:118] + node _T_3876 = mux(_T_3875, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 481:75] + node _T_3877 = mux(_T_3870, UInt<3>("h00"), _T_3876) @[lsu_bus_buffer.scala 481:31] + buf_nxtstate[1] <= _T_3877 @[lsu_bus_buffer.scala 481:25] + node _T_3878 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[lsu_bus_buffer.scala 482:66] + node _T_3879 = dshr(buf_ldfwd, buf_dualtag[1]) @[lsu_bus_buffer.scala 483:21] + node _T_3880 = bits(_T_3879, 0, 0) @[lsu_bus_buffer.scala 483:21] + node _T_3881 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[1]]) @[lsu_bus_buffer.scala 483:58] + node _T_3882 = and(_T_3880, _T_3881) @[lsu_bus_buffer.scala 483:38] + node _T_3883 = or(_T_3878, _T_3882) @[lsu_bus_buffer.scala 482:95] + node _T_3884 = and(bus_rsp_read, _T_3883) @[lsu_bus_buffer.scala 482:45] + buf_state_bus_en[1] <= _T_3884 @[lsu_bus_buffer.scala 482:29] + node _T_3885 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 484:49] + node _T_3886 = or(_T_3885, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 484:70] + buf_state_en[1] <= _T_3886 @[lsu_bus_buffer.scala 484:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3887 = eq(UInt<3>("h05"), buf_state[1]) @[Conditional.scala 37:30] when _T_3887 : @[Conditional.scala 39:67] - node _T_3888 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 488:60] - node _T_3889 = mux(_T_3888, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 488:31] - buf_nxtstate[1] <= _T_3889 @[lsu_bus_buffer.scala 488:25] - node _T_3890 = eq(RspPtr, UInt<2>("h01")) @[lsu_bus_buffer.scala 489:37] - node _T_3891 = eq(buf_dualtag[1], RspPtr) @[lsu_bus_buffer.scala 489:98] - node _T_3892 = and(buf_dual[1], _T_3891) @[lsu_bus_buffer.scala 489:80] - node _T_3893 = or(_T_3890, _T_3892) @[lsu_bus_buffer.scala 489:65] - node _T_3894 = or(_T_3893, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 489:112] - buf_state_en[1] <= _T_3894 @[lsu_bus_buffer.scala 489:25] + node _T_3888 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 487:60] + node _T_3889 = mux(_T_3888, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 487:31] + buf_nxtstate[1] <= _T_3889 @[lsu_bus_buffer.scala 487:25] + node _T_3890 = eq(RspPtr, UInt<2>("h01")) @[lsu_bus_buffer.scala 488:37] + node _T_3891 = eq(buf_dualtag[1], RspPtr) @[lsu_bus_buffer.scala 488:98] + node _T_3892 = and(buf_dual[1], _T_3891) @[lsu_bus_buffer.scala 488:80] + node _T_3893 = or(_T_3890, _T_3892) @[lsu_bus_buffer.scala 488:65] + node _T_3894 = or(_T_3893, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 488:112] + buf_state_en[1] <= _T_3894 @[lsu_bus_buffer.scala 488:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3895 = eq(UInt<3>("h06"), buf_state[1]) @[Conditional.scala 37:30] when _T_3895 : @[Conditional.scala 39:67] - buf_nxtstate[1] <= UInt<3>("h00") @[lsu_bus_buffer.scala 492:25] - buf_rst[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 493:20] - buf_state_en[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 494:25] - buf_ldfwd_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 495:25] - buf_ldfwd_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 496:25] + buf_nxtstate[1] <= UInt<3>("h00") @[lsu_bus_buffer.scala 491:25] + buf_rst[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 492:20] + buf_state_en[1] <= UInt<1>("h01") @[lsu_bus_buffer.scala 493:25] + buf_ldfwd_in[1] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:25] + buf_ldfwd_en[1] <= buf_state_en[1] @[lsu_bus_buffer.scala 495:25] skip @[Conditional.scala 39:67] - node _T_3896 = bits(buf_state_en[1], 0, 0) @[lsu_bus_buffer.scala 499:108] + node _T_3896 = bits(buf_state_en[1], 0, 0) @[lsu_bus_buffer.scala 498:108] reg _T_3897 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3896 : @[Reg.scala 28:19] _T_3897 <= buf_nxtstate[1] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_state[1] <= _T_3897 @[lsu_bus_buffer.scala 499:18] - reg _T_3898 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 500:60] - _T_3898 <= buf_age_in_1 @[lsu_bus_buffer.scala 500:60] - buf_ageQ[1] <= _T_3898 @[lsu_bus_buffer.scala 500:17] - reg _T_3899 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 501:63] - _T_3899 <= buf_rspage_in[1] @[lsu_bus_buffer.scala 501:63] - buf_rspageQ[1] <= _T_3899 @[lsu_bus_buffer.scala 501:20] - node _T_3900 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 502:109] + buf_state[1] <= _T_3897 @[lsu_bus_buffer.scala 498:18] + reg _T_3898 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 499:60] + _T_3898 <= buf_age_in_1 @[lsu_bus_buffer.scala 499:60] + buf_ageQ[1] <= _T_3898 @[lsu_bus_buffer.scala 499:17] + reg _T_3899 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 500:63] + _T_3899 <= buf_rspage_in[1] @[lsu_bus_buffer.scala 500:63] + buf_rspageQ[1] <= _T_3899 @[lsu_bus_buffer.scala 500:20] + node _T_3900 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 501:109] reg _T_3901 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3900 : @[Reg.scala 28:19] _T_3901 <= buf_dualtag_in[1] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dualtag[1] <= _T_3901 @[lsu_bus_buffer.scala 502:20] - node _T_3902 = bits(buf_dual_in, 1, 1) @[lsu_bus_buffer.scala 503:74] - node _T_3903 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 503:107] + buf_dualtag[1] <= _T_3901 @[lsu_bus_buffer.scala 501:20] + node _T_3902 = bits(buf_dual_in, 1, 1) @[lsu_bus_buffer.scala 502:74] + node _T_3903 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 502:107] reg _T_3904 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3903 : @[Reg.scala 28:19] _T_3904 <= _T_3902 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dual[1] <= _T_3904 @[lsu_bus_buffer.scala 503:17] - node _T_3905 = bits(buf_samedw_in, 1, 1) @[lsu_bus_buffer.scala 504:78] - node _T_3906 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 504:111] + buf_dual[1] <= _T_3904 @[lsu_bus_buffer.scala 502:17] + node _T_3905 = bits(buf_samedw_in, 1, 1) @[lsu_bus_buffer.scala 503:78] + node _T_3906 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 503:111] reg _T_3907 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3906 : @[Reg.scala 28:19] _T_3907 <= _T_3905 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_samedw[1] <= _T_3907 @[lsu_bus_buffer.scala 504:19] - node _T_3908 = bits(buf_nomerge_in, 1, 1) @[lsu_bus_buffer.scala 505:80] - node _T_3909 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 505:113] + buf_samedw[1] <= _T_3907 @[lsu_bus_buffer.scala 503:19] + node _T_3908 = bits(buf_nomerge_in, 1, 1) @[lsu_bus_buffer.scala 504:80] + node _T_3909 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 504:113] reg _T_3910 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3909 : @[Reg.scala 28:19] _T_3910 <= _T_3908 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_nomerge[1] <= _T_3910 @[lsu_bus_buffer.scala 505:20] - node _T_3911 = bits(buf_dualhi_in, 1, 1) @[lsu_bus_buffer.scala 506:78] - node _T_3912 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 506:111] + buf_nomerge[1] <= _T_3910 @[lsu_bus_buffer.scala 504:20] + node _T_3911 = bits(buf_dualhi_in, 1, 1) @[lsu_bus_buffer.scala 505:78] + node _T_3912 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 505:111] reg _T_3913 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_3912 : @[Reg.scala 28:19] _T_3913 <= _T_3911 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dualhi[1] <= _T_3913 @[lsu_bus_buffer.scala 506:19] + buf_dualhi[1] <= _T_3913 @[lsu_bus_buffer.scala 505:19] node _T_3914 = eq(UInt<3>("h00"), buf_state[2]) @[Conditional.scala 37:30] when _T_3914 : @[Conditional.scala 40:58] - node _T_3915 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 443:56] - node _T_3916 = mux(_T_3915, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 443:31] - buf_nxtstate[2] <= _T_3916 @[lsu_bus_buffer.scala 443:25] - node _T_3917 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 444:45] - node _T_3918 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 444:77] - node _T_3919 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 444:97] - node _T_3920 = and(_T_3918, _T_3919) @[lsu_bus_buffer.scala 444:95] - node _T_3921 = eq(UInt<2>("h02"), WrPtr0_r) @[lsu_bus_buffer.scala 444:117] - node _T_3922 = and(_T_3920, _T_3921) @[lsu_bus_buffer.scala 444:112] - node _T_3923 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 444:144] - node _T_3924 = eq(UInt<2>("h02"), WrPtr1_r) @[lsu_bus_buffer.scala 444:166] - node _T_3925 = and(_T_3923, _T_3924) @[lsu_bus_buffer.scala 444:161] - node _T_3926 = or(_T_3922, _T_3925) @[lsu_bus_buffer.scala 444:132] - node _T_3927 = and(_T_3917, _T_3926) @[lsu_bus_buffer.scala 444:63] - node _T_3928 = eq(UInt<2>("h02"), ibuf_tag) @[lsu_bus_buffer.scala 444:206] - node _T_3929 = and(ibuf_drain_vld, _T_3928) @[lsu_bus_buffer.scala 444:201] - node _T_3930 = or(_T_3927, _T_3929) @[lsu_bus_buffer.scala 444:183] - buf_state_en[2] <= _T_3930 @[lsu_bus_buffer.scala 444:25] - buf_wr_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 445:22] - buf_data_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 446:24] - node _T_3931 = eq(UInt<2>("h02"), ibuf_tag) @[lsu_bus_buffer.scala 447:52] - node _T_3932 = and(ibuf_drain_vld, _T_3931) @[lsu_bus_buffer.scala 447:47] - node _T_3933 = bits(_T_3932, 0, 0) @[lsu_bus_buffer.scala 447:73] - node _T_3934 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 447:90] - node _T_3935 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 447:114] - node _T_3936 = mux(_T_3933, _T_3934, _T_3935) @[lsu_bus_buffer.scala 447:30] - buf_data_in[2] <= _T_3936 @[lsu_bus_buffer.scala 447:24] + node _T_3915 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 442:56] + node _T_3916 = mux(_T_3915, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 442:31] + buf_nxtstate[2] <= _T_3916 @[lsu_bus_buffer.scala 442:25] + node _T_3917 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 443:45] + node _T_3918 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:77] + node _T_3919 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 443:97] + node _T_3920 = and(_T_3918, _T_3919) @[lsu_bus_buffer.scala 443:95] + node _T_3921 = eq(UInt<2>("h02"), WrPtr0_r) @[lsu_bus_buffer.scala 443:117] + node _T_3922 = and(_T_3920, _T_3921) @[lsu_bus_buffer.scala 443:112] + node _T_3923 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:144] + node _T_3924 = eq(UInt<2>("h02"), WrPtr1_r) @[lsu_bus_buffer.scala 443:166] + node _T_3925 = and(_T_3923, _T_3924) @[lsu_bus_buffer.scala 443:161] + node _T_3926 = or(_T_3922, _T_3925) @[lsu_bus_buffer.scala 443:132] + node _T_3927 = and(_T_3917, _T_3926) @[lsu_bus_buffer.scala 443:63] + node _T_3928 = eq(UInt<2>("h02"), ibuf_tag) @[lsu_bus_buffer.scala 443:206] + node _T_3929 = and(ibuf_drain_vld, _T_3928) @[lsu_bus_buffer.scala 443:201] + node _T_3930 = or(_T_3927, _T_3929) @[lsu_bus_buffer.scala 443:183] + buf_state_en[2] <= _T_3930 @[lsu_bus_buffer.scala 443:25] + buf_wr_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 444:22] + buf_data_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 445:24] + node _T_3931 = eq(UInt<2>("h02"), ibuf_tag) @[lsu_bus_buffer.scala 446:52] + node _T_3932 = and(ibuf_drain_vld, _T_3931) @[lsu_bus_buffer.scala 446:47] + node _T_3933 = bits(_T_3932, 0, 0) @[lsu_bus_buffer.scala 446:73] + node _T_3934 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 446:90] + node _T_3935 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 446:114] + node _T_3936 = mux(_T_3933, _T_3934, _T_3935) @[lsu_bus_buffer.scala 446:30] + buf_data_in[2] <= _T_3936 @[lsu_bus_buffer.scala 446:24] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_3937 = eq(UInt<3>("h01"), buf_state[2]) @[Conditional.scala 37:30] when _T_3937 : @[Conditional.scala 39:67] - node _T_3938 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 450:60] - node _T_3939 = mux(_T_3938, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 450:31] - buf_nxtstate[2] <= _T_3939 @[lsu_bus_buffer.scala 450:25] - node _T_3940 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 451:46] - buf_state_en[2] <= _T_3940 @[lsu_bus_buffer.scala 451:25] + node _T_3938 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 449:60] + node _T_3939 = mux(_T_3938, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 449:31] + buf_nxtstate[2] <= _T_3939 @[lsu_bus_buffer.scala 449:25] + node _T_3940 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 450:46] + buf_state_en[2] <= _T_3940 @[lsu_bus_buffer.scala 450:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3941 = eq(UInt<3>("h02"), buf_state[2]) @[Conditional.scala 37:30] when _T_3941 : @[Conditional.scala 39:67] - node _T_3942 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 454:60] - node _T_3943 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 454:89] - node _T_3944 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 454:124] - node _T_3945 = and(_T_3943, _T_3944) @[lsu_bus_buffer.scala 454:104] - node _T_3946 = mux(_T_3945, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 454:75] - node _T_3947 = mux(_T_3942, UInt<3>("h00"), _T_3946) @[lsu_bus_buffer.scala 454:31] - buf_nxtstate[2] <= _T_3947 @[lsu_bus_buffer.scala 454:25] - node _T_3948 = eq(obuf_tag0, UInt<3>("h02")) @[lsu_bus_buffer.scala 455:48] - node _T_3949 = eq(obuf_tag1, UInt<3>("h02")) @[lsu_bus_buffer.scala 455:104] - node _T_3950 = and(obuf_merge, _T_3949) @[lsu_bus_buffer.scala 455:91] - node _T_3951 = or(_T_3948, _T_3950) @[lsu_bus_buffer.scala 455:77] - node _T_3952 = and(_T_3951, obuf_valid) @[lsu_bus_buffer.scala 455:135] - node _T_3953 = and(_T_3952, obuf_wr_enQ) @[lsu_bus_buffer.scala 455:148] - buf_cmd_state_bus_en[2] <= _T_3953 @[lsu_bus_buffer.scala 455:33] - buf_state_bus_en[2] <= buf_cmd_state_bus_en[2] @[lsu_bus_buffer.scala 456:29] - node _T_3954 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 457:49] - node _T_3955 = or(_T_3954, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 457:70] - buf_state_en[2] <= _T_3955 @[lsu_bus_buffer.scala 457:25] - buf_ldfwd_in[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 458:25] - node _T_3956 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 459:56] - node _T_3957 = eq(_T_3956, UInt<1>("h00")) @[lsu_bus_buffer.scala 459:46] - node _T_3958 = and(buf_state_en[2], _T_3957) @[lsu_bus_buffer.scala 459:44] - node _T_3959 = and(_T_3958, obuf_nosend) @[lsu_bus_buffer.scala 459:60] - node _T_3960 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 459:76] - node _T_3961 = and(_T_3959, _T_3960) @[lsu_bus_buffer.scala 459:74] - buf_ldfwd_en[2] <= _T_3961 @[lsu_bus_buffer.scala 459:25] - node _T_3962 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 460:46] - buf_ldfwdtag_in[2] <= _T_3962 @[lsu_bus_buffer.scala 460:28] - node _T_3963 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 461:47] - node _T_3964 = and(_T_3963, obuf_nosend) @[lsu_bus_buffer.scala 461:67] - node _T_3965 = and(_T_3964, bus_rsp_read) @[lsu_bus_buffer.scala 461:81] - buf_data_en[2] <= _T_3965 @[lsu_bus_buffer.scala 461:24] - node _T_3966 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:48] - node _T_3967 = and(_T_3966, obuf_nosend) @[lsu_bus_buffer.scala 462:68] - node _T_3968 = and(_T_3967, bus_rsp_read_error) @[lsu_bus_buffer.scala 462:82] - buf_error_en[2] <= _T_3968 @[lsu_bus_buffer.scala 462:25] - node _T_3969 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 463:61] - node _T_3970 = bits(buf_addr[2], 2, 2) @[lsu_bus_buffer.scala 463:85] - node _T_3971 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 463:103] - node _T_3972 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 463:126] - node _T_3973 = mux(_T_3970, _T_3971, _T_3972) @[lsu_bus_buffer.scala 463:73] - node _T_3974 = mux(buf_error_en[2], _T_3969, _T_3973) @[lsu_bus_buffer.scala 463:30] - buf_data_in[2] <= _T_3974 @[lsu_bus_buffer.scala 463:24] + node _T_3942 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_3943 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 453:89] + node _T_3944 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 453:124] + node _T_3945 = and(_T_3943, _T_3944) @[lsu_bus_buffer.scala 453:104] + node _T_3946 = mux(_T_3945, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 453:75] + node _T_3947 = mux(_T_3942, UInt<3>("h00"), _T_3946) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[2] <= _T_3947 @[lsu_bus_buffer.scala 453:25] + node _T_3948 = eq(obuf_tag0, UInt<3>("h02")) @[lsu_bus_buffer.scala 454:48] + node _T_3949 = eq(obuf_tag1, UInt<3>("h02")) @[lsu_bus_buffer.scala 454:104] + node _T_3950 = and(obuf_merge, _T_3949) @[lsu_bus_buffer.scala 454:91] + node _T_3951 = or(_T_3948, _T_3950) @[lsu_bus_buffer.scala 454:77] + node _T_3952 = and(_T_3951, obuf_valid) @[lsu_bus_buffer.scala 454:135] + node _T_3953 = and(_T_3952, obuf_wr_enQ) @[lsu_bus_buffer.scala 454:148] + buf_cmd_state_bus_en[2] <= _T_3953 @[lsu_bus_buffer.scala 454:33] + buf_state_bus_en[2] <= buf_cmd_state_bus_en[2] @[lsu_bus_buffer.scala 455:29] + node _T_3954 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 456:49] + node _T_3955 = or(_T_3954, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 456:70] + buf_state_en[2] <= _T_3955 @[lsu_bus_buffer.scala 456:25] + buf_ldfwd_in[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 457:25] + node _T_3956 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 458:56] + node _T_3957 = eq(_T_3956, UInt<1>("h00")) @[lsu_bus_buffer.scala 458:46] + node _T_3958 = and(buf_state_en[2], _T_3957) @[lsu_bus_buffer.scala 458:44] + node _T_3959 = and(_T_3958, obuf_nosend) @[lsu_bus_buffer.scala 458:60] + node _T_3960 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 458:76] + node _T_3961 = and(_T_3959, _T_3960) @[lsu_bus_buffer.scala 458:74] + buf_ldfwd_en[2] <= _T_3961 @[lsu_bus_buffer.scala 458:25] + node _T_3962 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 459:46] + buf_ldfwdtag_in[2] <= _T_3962 @[lsu_bus_buffer.scala 459:28] + node _T_3963 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 460:47] + node _T_3964 = and(_T_3963, obuf_nosend) @[lsu_bus_buffer.scala 460:67] + node _T_3965 = and(_T_3964, bus_rsp_read) @[lsu_bus_buffer.scala 460:81] + buf_data_en[2] <= _T_3965 @[lsu_bus_buffer.scala 460:24] + node _T_3966 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 461:48] + node _T_3967 = and(_T_3966, obuf_nosend) @[lsu_bus_buffer.scala 461:68] + node _T_3968 = and(_T_3967, bus_rsp_read_error) @[lsu_bus_buffer.scala 461:82] + buf_error_en[2] <= _T_3968 @[lsu_bus_buffer.scala 461:25] + node _T_3969 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 462:61] + node _T_3970 = bits(buf_addr[2], 2, 2) @[lsu_bus_buffer.scala 462:85] + node _T_3971 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 462:103] + node _T_3972 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 462:126] + node _T_3973 = mux(_T_3970, _T_3971, _T_3972) @[lsu_bus_buffer.scala 462:73] + node _T_3974 = mux(buf_error_en[2], _T_3969, _T_3973) @[lsu_bus_buffer.scala 462:30] + buf_data_in[2] <= _T_3974 @[lsu_bus_buffer.scala 462:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_3975 = eq(UInt<3>("h03"), buf_state[2]) @[Conditional.scala 37:30] when _T_3975 : @[Conditional.scala 39:67] - node _T_3976 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 466:67] - node _T_3977 = and(UInt<1>("h01"), bus_rsp_write_error) @[lsu_bus_buffer.scala 466:94] - node _T_3978 = eq(_T_3977, UInt<1>("h00")) @[lsu_bus_buffer.scala 466:73] - node _T_3979 = and(_T_3976, _T_3978) @[lsu_bus_buffer.scala 466:71] - node _T_3980 = or(io.dec_tlu_force_halt, _T_3979) @[lsu_bus_buffer.scala 466:55] - node _T_3981 = bits(_T_3980, 0, 0) @[lsu_bus_buffer.scala 466:125] - node _T_3982 = eq(buf_samedw[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 467:30] - node _T_3983 = and(buf_dual[2], _T_3982) @[lsu_bus_buffer.scala 467:28] - node _T_3984 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 467:57] - node _T_3985 = eq(_T_3984, UInt<1>("h00")) @[lsu_bus_buffer.scala 467:47] - node _T_3986 = and(_T_3983, _T_3985) @[lsu_bus_buffer.scala 467:45] - node _T_3987 = neq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[lsu_bus_buffer.scala 467:90] - node _T_3988 = and(_T_3986, _T_3987) @[lsu_bus_buffer.scala 467:61] - node _T_3989 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 468:27] - node _T_3990 = or(_T_3989, any_done_wait_state) @[lsu_bus_buffer.scala 468:31] - node _T_3991 = eq(buf_samedw[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 468:70] - node _T_3992 = and(buf_dual[2], _T_3991) @[lsu_bus_buffer.scala 468:68] - node _T_3993 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 468:97] - node _T_3994 = eq(_T_3993, UInt<1>("h00")) @[lsu_bus_buffer.scala 468:87] - node _T_3995 = and(_T_3992, _T_3994) @[lsu_bus_buffer.scala 468:85] + node _T_3976 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 465:67] + node _T_3977 = and(UInt<1>("h01"), bus_rsp_write_error) @[lsu_bus_buffer.scala 465:94] + node _T_3978 = eq(_T_3977, UInt<1>("h00")) @[lsu_bus_buffer.scala 465:73] + node _T_3979 = and(_T_3976, _T_3978) @[lsu_bus_buffer.scala 465:71] + node _T_3980 = or(io.dec_tlu_force_halt, _T_3979) @[lsu_bus_buffer.scala 465:55] + node _T_3981 = bits(_T_3980, 0, 0) @[lsu_bus_buffer.scala 465:125] + node _T_3982 = eq(buf_samedw[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 466:30] + node _T_3983 = and(buf_dual[2], _T_3982) @[lsu_bus_buffer.scala 466:28] + node _T_3984 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 466:57] + node _T_3985 = eq(_T_3984, UInt<1>("h00")) @[lsu_bus_buffer.scala 466:47] + node _T_3986 = and(_T_3983, _T_3985) @[lsu_bus_buffer.scala 466:45] + node _T_3987 = neq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[lsu_bus_buffer.scala 466:90] + node _T_3988 = and(_T_3986, _T_3987) @[lsu_bus_buffer.scala 466:61] + node _T_3989 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 467:27] + node _T_3990 = or(_T_3989, any_done_wait_state) @[lsu_bus_buffer.scala 467:31] + node _T_3991 = eq(buf_samedw[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 467:70] + node _T_3992 = and(buf_dual[2], _T_3991) @[lsu_bus_buffer.scala 467:68] + node _T_3993 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 467:97] + node _T_3994 = eq(_T_3993, UInt<1>("h00")) @[lsu_bus_buffer.scala 467:87] + node _T_3995 = and(_T_3992, _T_3994) @[lsu_bus_buffer.scala 467:85] node _T_3996 = eq(buf_dualtag[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] node _T_3997 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 57:129] node _T_3998 = eq(buf_dualtag[2], UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] @@ -99719,265 +99716,265 @@ circuit quasar_wrapper : node _T_4010 = or(_T_4009, _T_4007) @[Mux.scala 27:72] wire _T_4011 : UInt<1> @[Mux.scala 27:72] _T_4011 <= _T_4010 @[Mux.scala 27:72] - node _T_4012 = and(_T_3995, _T_4011) @[lsu_bus_buffer.scala 468:101] - node _T_4013 = eq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[lsu_bus_buffer.scala 468:167] - node _T_4014 = and(_T_4012, _T_4013) @[lsu_bus_buffer.scala 468:138] - node _T_4015 = and(_T_4014, any_done_wait_state) @[lsu_bus_buffer.scala 468:187] - node _T_4016 = or(_T_3990, _T_4015) @[lsu_bus_buffer.scala 468:53] - node _T_4017 = mux(_T_4016, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 468:16] - node _T_4018 = mux(_T_3988, UInt<3>("h04"), _T_4017) @[lsu_bus_buffer.scala 467:14] - node _T_4019 = mux(_T_3981, UInt<3>("h00"), _T_4018) @[lsu_bus_buffer.scala 466:31] - buf_nxtstate[2] <= _T_4019 @[lsu_bus_buffer.scala 466:25] - node _T_4020 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 469:73] - node _T_4021 = and(bus_rsp_write, _T_4020) @[lsu_bus_buffer.scala 469:52] - node _T_4022 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 470:46] - node _T_4023 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 471:23] - node _T_4024 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[lsu_bus_buffer.scala 471:47] - node _T_4025 = and(_T_4023, _T_4024) @[lsu_bus_buffer.scala 471:27] - node _T_4026 = or(_T_4022, _T_4025) @[lsu_bus_buffer.scala 470:77] - node _T_4027 = and(buf_dual[2], buf_dualhi[2]) @[lsu_bus_buffer.scala 472:26] - node _T_4028 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 472:54] - node _T_4029 = not(_T_4028) @[lsu_bus_buffer.scala 472:44] - node _T_4030 = and(_T_4027, _T_4029) @[lsu_bus_buffer.scala 472:42] - node _T_4031 = and(_T_4030, buf_samedw[2]) @[lsu_bus_buffer.scala 472:58] - node _T_4032 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[lsu_bus_buffer.scala 472:94] - node _T_4033 = and(_T_4031, _T_4032) @[lsu_bus_buffer.scala 472:74] - node _T_4034 = or(_T_4026, _T_4033) @[lsu_bus_buffer.scala 471:71] - node _T_4035 = and(bus_rsp_read, _T_4034) @[lsu_bus_buffer.scala 470:25] - node _T_4036 = or(_T_4021, _T_4035) @[lsu_bus_buffer.scala 469:105] - buf_resp_state_bus_en[2] <= _T_4036 @[lsu_bus_buffer.scala 469:34] - buf_state_bus_en[2] <= buf_resp_state_bus_en[2] @[lsu_bus_buffer.scala 473:29] - node _T_4037 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 474:49] - node _T_4038 = or(_T_4037, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 474:70] - buf_state_en[2] <= _T_4038 @[lsu_bus_buffer.scala 474:25] - node _T_4039 = and(buf_state_bus_en[2], bus_rsp_read) @[lsu_bus_buffer.scala 475:47] - node _T_4040 = and(_T_4039, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 475:62] - buf_data_en[2] <= _T_4040 @[lsu_bus_buffer.scala 475:24] - node _T_4041 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 476:48] - node _T_4042 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 476:111] - node _T_4043 = and(bus_rsp_read_error, _T_4042) @[lsu_bus_buffer.scala 476:91] - node _T_4044 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 477:42] - node _T_4045 = and(bus_rsp_read_error, _T_4044) @[lsu_bus_buffer.scala 477:31] - node _T_4046 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[lsu_bus_buffer.scala 477:66] - node _T_4047 = and(_T_4045, _T_4046) @[lsu_bus_buffer.scala 477:46] - node _T_4048 = or(_T_4043, _T_4047) @[lsu_bus_buffer.scala 476:143] - node _T_4049 = and(bus_rsp_write_error, UInt<1>("h01")) @[lsu_bus_buffer.scala 478:32] - node _T_4050 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 478:74] - node _T_4051 = and(_T_4049, _T_4050) @[lsu_bus_buffer.scala 478:53] - node _T_4052 = or(_T_4048, _T_4051) @[lsu_bus_buffer.scala 477:88] - node _T_4053 = and(_T_4041, _T_4052) @[lsu_bus_buffer.scala 476:68] - buf_error_en[2] <= _T_4053 @[lsu_bus_buffer.scala 476:25] - node _T_4054 = eq(buf_error_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 479:50] - node _T_4055 = and(buf_state_en[2], _T_4054) @[lsu_bus_buffer.scala 479:48] - node _T_4056 = bits(buf_addr[2], 2, 2) @[lsu_bus_buffer.scala 479:84] - node _T_4057 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 479:102] - node _T_4058 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 479:125] - node _T_4059 = mux(_T_4056, _T_4057, _T_4058) @[lsu_bus_buffer.scala 479:72] - node _T_4060 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 479:148] - node _T_4061 = mux(_T_4055, _T_4059, _T_4060) @[lsu_bus_buffer.scala 479:30] - buf_data_in[2] <= _T_4061 @[lsu_bus_buffer.scala 479:24] + node _T_4012 = and(_T_3995, _T_4011) @[lsu_bus_buffer.scala 467:101] + node _T_4013 = eq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[lsu_bus_buffer.scala 467:167] + node _T_4014 = and(_T_4012, _T_4013) @[lsu_bus_buffer.scala 467:138] + node _T_4015 = and(_T_4014, any_done_wait_state) @[lsu_bus_buffer.scala 467:187] + node _T_4016 = or(_T_3990, _T_4015) @[lsu_bus_buffer.scala 467:53] + node _T_4017 = mux(_T_4016, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 467:16] + node _T_4018 = mux(_T_3988, UInt<3>("h04"), _T_4017) @[lsu_bus_buffer.scala 466:14] + node _T_4019 = mux(_T_3981, UInt<3>("h00"), _T_4018) @[lsu_bus_buffer.scala 465:31] + buf_nxtstate[2] <= _T_4019 @[lsu_bus_buffer.scala 465:25] + node _T_4020 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 468:73] + node _T_4021 = and(bus_rsp_write, _T_4020) @[lsu_bus_buffer.scala 468:52] + node _T_4022 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 469:46] + node _T_4023 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 470:23] + node _T_4024 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[lsu_bus_buffer.scala 470:47] + node _T_4025 = and(_T_4023, _T_4024) @[lsu_bus_buffer.scala 470:27] + node _T_4026 = or(_T_4022, _T_4025) @[lsu_bus_buffer.scala 469:77] + node _T_4027 = and(buf_dual[2], buf_dualhi[2]) @[lsu_bus_buffer.scala 471:26] + node _T_4028 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 471:54] + node _T_4029 = not(_T_4028) @[lsu_bus_buffer.scala 471:44] + node _T_4030 = and(_T_4027, _T_4029) @[lsu_bus_buffer.scala 471:42] + node _T_4031 = and(_T_4030, buf_samedw[2]) @[lsu_bus_buffer.scala 471:58] + node _T_4032 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[lsu_bus_buffer.scala 471:94] + node _T_4033 = and(_T_4031, _T_4032) @[lsu_bus_buffer.scala 471:74] + node _T_4034 = or(_T_4026, _T_4033) @[lsu_bus_buffer.scala 470:71] + node _T_4035 = and(bus_rsp_read, _T_4034) @[lsu_bus_buffer.scala 469:25] + node _T_4036 = or(_T_4021, _T_4035) @[lsu_bus_buffer.scala 468:105] + buf_resp_state_bus_en[2] <= _T_4036 @[lsu_bus_buffer.scala 468:34] + buf_state_bus_en[2] <= buf_resp_state_bus_en[2] @[lsu_bus_buffer.scala 472:29] + node _T_4037 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 473:49] + node _T_4038 = or(_T_4037, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 473:70] + buf_state_en[2] <= _T_4038 @[lsu_bus_buffer.scala 473:25] + node _T_4039 = and(buf_state_bus_en[2], bus_rsp_read) @[lsu_bus_buffer.scala 474:47] + node _T_4040 = and(_T_4039, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 474:62] + buf_data_en[2] <= _T_4040 @[lsu_bus_buffer.scala 474:24] + node _T_4041 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 475:48] + node _T_4042 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 475:111] + node _T_4043 = and(bus_rsp_read_error, _T_4042) @[lsu_bus_buffer.scala 475:91] + node _T_4044 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 476:42] + node _T_4045 = and(bus_rsp_read_error, _T_4044) @[lsu_bus_buffer.scala 476:31] + node _T_4046 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[lsu_bus_buffer.scala 476:66] + node _T_4047 = and(_T_4045, _T_4046) @[lsu_bus_buffer.scala 476:46] + node _T_4048 = or(_T_4043, _T_4047) @[lsu_bus_buffer.scala 475:143] + node _T_4049 = and(bus_rsp_write_error, UInt<1>("h01")) @[lsu_bus_buffer.scala 477:32] + node _T_4050 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[lsu_bus_buffer.scala 477:74] + node _T_4051 = and(_T_4049, _T_4050) @[lsu_bus_buffer.scala 477:53] + node _T_4052 = or(_T_4048, _T_4051) @[lsu_bus_buffer.scala 476:88] + node _T_4053 = and(_T_4041, _T_4052) @[lsu_bus_buffer.scala 475:68] + buf_error_en[2] <= _T_4053 @[lsu_bus_buffer.scala 475:25] + node _T_4054 = eq(buf_error_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 478:50] + node _T_4055 = and(buf_state_en[2], _T_4054) @[lsu_bus_buffer.scala 478:48] + node _T_4056 = bits(buf_addr[2], 2, 2) @[lsu_bus_buffer.scala 478:84] + node _T_4057 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 478:102] + node _T_4058 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 478:125] + node _T_4059 = mux(_T_4056, _T_4057, _T_4058) @[lsu_bus_buffer.scala 478:72] + node _T_4060 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 478:148] + node _T_4061 = mux(_T_4055, _T_4059, _T_4060) @[lsu_bus_buffer.scala 478:30] + buf_data_in[2] <= _T_4061 @[lsu_bus_buffer.scala 478:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_4062 = eq(UInt<3>("h04"), buf_state[2]) @[Conditional.scala 37:30] when _T_4062 : @[Conditional.scala 39:67] - node _T_4063 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 482:60] - node _T_4064 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 482:86] - node _T_4065 = dshr(buf_ldfwd, buf_dualtag[2]) @[lsu_bus_buffer.scala 482:101] - node _T_4066 = bits(_T_4065, 0, 0) @[lsu_bus_buffer.scala 482:101] - node _T_4067 = or(_T_4064, _T_4066) @[lsu_bus_buffer.scala 482:90] - node _T_4068 = or(_T_4067, any_done_wait_state) @[lsu_bus_buffer.scala 482:118] - node _T_4069 = mux(_T_4068, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 482:75] - node _T_4070 = mux(_T_4063, UInt<3>("h00"), _T_4069) @[lsu_bus_buffer.scala 482:31] - buf_nxtstate[2] <= _T_4070 @[lsu_bus_buffer.scala 482:25] - node _T_4071 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[lsu_bus_buffer.scala 483:66] - node _T_4072 = dshr(buf_ldfwd, buf_dualtag[2]) @[lsu_bus_buffer.scala 484:21] - node _T_4073 = bits(_T_4072, 0, 0) @[lsu_bus_buffer.scala 484:21] - node _T_4074 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[2]]) @[lsu_bus_buffer.scala 484:58] - node _T_4075 = and(_T_4073, _T_4074) @[lsu_bus_buffer.scala 484:38] - node _T_4076 = or(_T_4071, _T_4075) @[lsu_bus_buffer.scala 483:95] - node _T_4077 = and(bus_rsp_read, _T_4076) @[lsu_bus_buffer.scala 483:45] - buf_state_bus_en[2] <= _T_4077 @[lsu_bus_buffer.scala 483:29] - node _T_4078 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 485:49] - node _T_4079 = or(_T_4078, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 485:70] - buf_state_en[2] <= _T_4079 @[lsu_bus_buffer.scala 485:25] + node _T_4063 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 481:60] + node _T_4064 = bits(buf_ldfwd, 2, 2) @[lsu_bus_buffer.scala 481:86] + node _T_4065 = dshr(buf_ldfwd, buf_dualtag[2]) @[lsu_bus_buffer.scala 481:101] + node _T_4066 = bits(_T_4065, 0, 0) @[lsu_bus_buffer.scala 481:101] + node _T_4067 = or(_T_4064, _T_4066) @[lsu_bus_buffer.scala 481:90] + node _T_4068 = or(_T_4067, any_done_wait_state) @[lsu_bus_buffer.scala 481:118] + node _T_4069 = mux(_T_4068, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 481:75] + node _T_4070 = mux(_T_4063, UInt<3>("h00"), _T_4069) @[lsu_bus_buffer.scala 481:31] + buf_nxtstate[2] <= _T_4070 @[lsu_bus_buffer.scala 481:25] + node _T_4071 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[lsu_bus_buffer.scala 482:66] + node _T_4072 = dshr(buf_ldfwd, buf_dualtag[2]) @[lsu_bus_buffer.scala 483:21] + node _T_4073 = bits(_T_4072, 0, 0) @[lsu_bus_buffer.scala 483:21] + node _T_4074 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[2]]) @[lsu_bus_buffer.scala 483:58] + node _T_4075 = and(_T_4073, _T_4074) @[lsu_bus_buffer.scala 483:38] + node _T_4076 = or(_T_4071, _T_4075) @[lsu_bus_buffer.scala 482:95] + node _T_4077 = and(bus_rsp_read, _T_4076) @[lsu_bus_buffer.scala 482:45] + buf_state_bus_en[2] <= _T_4077 @[lsu_bus_buffer.scala 482:29] + node _T_4078 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 484:49] + node _T_4079 = or(_T_4078, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 484:70] + buf_state_en[2] <= _T_4079 @[lsu_bus_buffer.scala 484:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_4080 = eq(UInt<3>("h05"), buf_state[2]) @[Conditional.scala 37:30] when _T_4080 : @[Conditional.scala 39:67] - node _T_4081 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 488:60] - node _T_4082 = mux(_T_4081, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 488:31] - buf_nxtstate[2] <= _T_4082 @[lsu_bus_buffer.scala 488:25] - node _T_4083 = eq(RspPtr, UInt<2>("h02")) @[lsu_bus_buffer.scala 489:37] - node _T_4084 = eq(buf_dualtag[2], RspPtr) @[lsu_bus_buffer.scala 489:98] - node _T_4085 = and(buf_dual[2], _T_4084) @[lsu_bus_buffer.scala 489:80] - node _T_4086 = or(_T_4083, _T_4085) @[lsu_bus_buffer.scala 489:65] - node _T_4087 = or(_T_4086, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 489:112] - buf_state_en[2] <= _T_4087 @[lsu_bus_buffer.scala 489:25] + node _T_4081 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 487:60] + node _T_4082 = mux(_T_4081, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 487:31] + buf_nxtstate[2] <= _T_4082 @[lsu_bus_buffer.scala 487:25] + node _T_4083 = eq(RspPtr, UInt<2>("h02")) @[lsu_bus_buffer.scala 488:37] + node _T_4084 = eq(buf_dualtag[2], RspPtr) @[lsu_bus_buffer.scala 488:98] + node _T_4085 = and(buf_dual[2], _T_4084) @[lsu_bus_buffer.scala 488:80] + node _T_4086 = or(_T_4083, _T_4085) @[lsu_bus_buffer.scala 488:65] + node _T_4087 = or(_T_4086, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 488:112] + buf_state_en[2] <= _T_4087 @[lsu_bus_buffer.scala 488:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_4088 = eq(UInt<3>("h06"), buf_state[2]) @[Conditional.scala 37:30] when _T_4088 : @[Conditional.scala 39:67] - buf_nxtstate[2] <= UInt<3>("h00") @[lsu_bus_buffer.scala 492:25] - buf_rst[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 493:20] - buf_state_en[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 494:25] - buf_ldfwd_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 495:25] - buf_ldfwd_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 496:25] + buf_nxtstate[2] <= UInt<3>("h00") @[lsu_bus_buffer.scala 491:25] + buf_rst[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 492:20] + buf_state_en[2] <= UInt<1>("h01") @[lsu_bus_buffer.scala 493:25] + buf_ldfwd_in[2] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:25] + buf_ldfwd_en[2] <= buf_state_en[2] @[lsu_bus_buffer.scala 495:25] skip @[Conditional.scala 39:67] - node _T_4089 = bits(buf_state_en[2], 0, 0) @[lsu_bus_buffer.scala 499:108] + node _T_4089 = bits(buf_state_en[2], 0, 0) @[lsu_bus_buffer.scala 498:108] reg _T_4090 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4089 : @[Reg.scala 28:19] _T_4090 <= buf_nxtstate[2] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_state[2] <= _T_4090 @[lsu_bus_buffer.scala 499:18] - reg _T_4091 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 500:60] - _T_4091 <= buf_age_in_2 @[lsu_bus_buffer.scala 500:60] - buf_ageQ[2] <= _T_4091 @[lsu_bus_buffer.scala 500:17] - reg _T_4092 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 501:63] - _T_4092 <= buf_rspage_in[2] @[lsu_bus_buffer.scala 501:63] - buf_rspageQ[2] <= _T_4092 @[lsu_bus_buffer.scala 501:20] - node _T_4093 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 502:109] + buf_state[2] <= _T_4090 @[lsu_bus_buffer.scala 498:18] + reg _T_4091 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 499:60] + _T_4091 <= buf_age_in_2 @[lsu_bus_buffer.scala 499:60] + buf_ageQ[2] <= _T_4091 @[lsu_bus_buffer.scala 499:17] + reg _T_4092 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 500:63] + _T_4092 <= buf_rspage_in[2] @[lsu_bus_buffer.scala 500:63] + buf_rspageQ[2] <= _T_4092 @[lsu_bus_buffer.scala 500:20] + node _T_4093 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 501:109] reg _T_4094 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4093 : @[Reg.scala 28:19] _T_4094 <= buf_dualtag_in[2] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dualtag[2] <= _T_4094 @[lsu_bus_buffer.scala 502:20] - node _T_4095 = bits(buf_dual_in, 2, 2) @[lsu_bus_buffer.scala 503:74] - node _T_4096 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 503:107] + buf_dualtag[2] <= _T_4094 @[lsu_bus_buffer.scala 501:20] + node _T_4095 = bits(buf_dual_in, 2, 2) @[lsu_bus_buffer.scala 502:74] + node _T_4096 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 502:107] reg _T_4097 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4096 : @[Reg.scala 28:19] _T_4097 <= _T_4095 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dual[2] <= _T_4097 @[lsu_bus_buffer.scala 503:17] - node _T_4098 = bits(buf_samedw_in, 2, 2) @[lsu_bus_buffer.scala 504:78] - node _T_4099 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 504:111] + buf_dual[2] <= _T_4097 @[lsu_bus_buffer.scala 502:17] + node _T_4098 = bits(buf_samedw_in, 2, 2) @[lsu_bus_buffer.scala 503:78] + node _T_4099 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 503:111] reg _T_4100 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4099 : @[Reg.scala 28:19] _T_4100 <= _T_4098 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_samedw[2] <= _T_4100 @[lsu_bus_buffer.scala 504:19] - node _T_4101 = bits(buf_nomerge_in, 2, 2) @[lsu_bus_buffer.scala 505:80] - node _T_4102 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 505:113] + buf_samedw[2] <= _T_4100 @[lsu_bus_buffer.scala 503:19] + node _T_4101 = bits(buf_nomerge_in, 2, 2) @[lsu_bus_buffer.scala 504:80] + node _T_4102 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 504:113] reg _T_4103 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4102 : @[Reg.scala 28:19] _T_4103 <= _T_4101 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_nomerge[2] <= _T_4103 @[lsu_bus_buffer.scala 505:20] - node _T_4104 = bits(buf_dualhi_in, 2, 2) @[lsu_bus_buffer.scala 506:78] - node _T_4105 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 506:111] + buf_nomerge[2] <= _T_4103 @[lsu_bus_buffer.scala 504:20] + node _T_4104 = bits(buf_dualhi_in, 2, 2) @[lsu_bus_buffer.scala 505:78] + node _T_4105 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 505:111] reg _T_4106 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4105 : @[Reg.scala 28:19] _T_4106 <= _T_4104 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dualhi[2] <= _T_4106 @[lsu_bus_buffer.scala 506:19] + buf_dualhi[2] <= _T_4106 @[lsu_bus_buffer.scala 505:19] node _T_4107 = eq(UInt<3>("h00"), buf_state[3]) @[Conditional.scala 37:30] when _T_4107 : @[Conditional.scala 40:58] - node _T_4108 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 443:56] - node _T_4109 = mux(_T_4108, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 443:31] - buf_nxtstate[3] <= _T_4109 @[lsu_bus_buffer.scala 443:25] - node _T_4110 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 444:45] - node _T_4111 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 444:77] - node _T_4112 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 444:97] - node _T_4113 = and(_T_4111, _T_4112) @[lsu_bus_buffer.scala 444:95] - node _T_4114 = eq(UInt<2>("h03"), WrPtr0_r) @[lsu_bus_buffer.scala 444:117] - node _T_4115 = and(_T_4113, _T_4114) @[lsu_bus_buffer.scala 444:112] - node _T_4116 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 444:144] - node _T_4117 = eq(UInt<2>("h03"), WrPtr1_r) @[lsu_bus_buffer.scala 444:166] - node _T_4118 = and(_T_4116, _T_4117) @[lsu_bus_buffer.scala 444:161] - node _T_4119 = or(_T_4115, _T_4118) @[lsu_bus_buffer.scala 444:132] - node _T_4120 = and(_T_4110, _T_4119) @[lsu_bus_buffer.scala 444:63] - node _T_4121 = eq(UInt<2>("h03"), ibuf_tag) @[lsu_bus_buffer.scala 444:206] - node _T_4122 = and(ibuf_drain_vld, _T_4121) @[lsu_bus_buffer.scala 444:201] - node _T_4123 = or(_T_4120, _T_4122) @[lsu_bus_buffer.scala 444:183] - buf_state_en[3] <= _T_4123 @[lsu_bus_buffer.scala 444:25] - buf_wr_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 445:22] - buf_data_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 446:24] - node _T_4124 = eq(UInt<2>("h03"), ibuf_tag) @[lsu_bus_buffer.scala 447:52] - node _T_4125 = and(ibuf_drain_vld, _T_4124) @[lsu_bus_buffer.scala 447:47] - node _T_4126 = bits(_T_4125, 0, 0) @[lsu_bus_buffer.scala 447:73] - node _T_4127 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 447:90] - node _T_4128 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 447:114] - node _T_4129 = mux(_T_4126, _T_4127, _T_4128) @[lsu_bus_buffer.scala 447:30] - buf_data_in[3] <= _T_4129 @[lsu_bus_buffer.scala 447:24] + node _T_4108 = bits(io.lsu_bus_clk_en, 0, 0) @[lsu_bus_buffer.scala 442:56] + node _T_4109 = mux(_T_4108, UInt<3>("h02"), UInt<3>("h01")) @[lsu_bus_buffer.scala 442:31] + buf_nxtstate[3] <= _T_4109 @[lsu_bus_buffer.scala 442:25] + node _T_4110 = and(io.lsu_busreq_r, io.lsu_commit_r) @[lsu_bus_buffer.scala 443:45] + node _T_4111 = or(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:77] + node _T_4112 = eq(ibuf_merge_en, UInt<1>("h00")) @[lsu_bus_buffer.scala 443:97] + node _T_4113 = and(_T_4111, _T_4112) @[lsu_bus_buffer.scala 443:95] + node _T_4114 = eq(UInt<2>("h03"), WrPtr0_r) @[lsu_bus_buffer.scala 443:117] + node _T_4115 = and(_T_4113, _T_4114) @[lsu_bus_buffer.scala 443:112] + node _T_4116 = and(ibuf_byp, io.ldst_dual_r) @[lsu_bus_buffer.scala 443:144] + node _T_4117 = eq(UInt<2>("h03"), WrPtr1_r) @[lsu_bus_buffer.scala 443:166] + node _T_4118 = and(_T_4116, _T_4117) @[lsu_bus_buffer.scala 443:161] + node _T_4119 = or(_T_4115, _T_4118) @[lsu_bus_buffer.scala 443:132] + node _T_4120 = and(_T_4110, _T_4119) @[lsu_bus_buffer.scala 443:63] + node _T_4121 = eq(UInt<2>("h03"), ibuf_tag) @[lsu_bus_buffer.scala 443:206] + node _T_4122 = and(ibuf_drain_vld, _T_4121) @[lsu_bus_buffer.scala 443:201] + node _T_4123 = or(_T_4120, _T_4122) @[lsu_bus_buffer.scala 443:183] + buf_state_en[3] <= _T_4123 @[lsu_bus_buffer.scala 443:25] + buf_wr_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 444:22] + buf_data_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 445:24] + node _T_4124 = eq(UInt<2>("h03"), ibuf_tag) @[lsu_bus_buffer.scala 446:52] + node _T_4125 = and(ibuf_drain_vld, _T_4124) @[lsu_bus_buffer.scala 446:47] + node _T_4126 = bits(_T_4125, 0, 0) @[lsu_bus_buffer.scala 446:73] + node _T_4127 = bits(ibuf_data_out, 31, 0) @[lsu_bus_buffer.scala 446:90] + node _T_4128 = bits(store_data_lo_r, 31, 0) @[lsu_bus_buffer.scala 446:114] + node _T_4129 = mux(_T_4126, _T_4127, _T_4128) @[lsu_bus_buffer.scala 446:30] + buf_data_in[3] <= _T_4129 @[lsu_bus_buffer.scala 446:24] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_4130 = eq(UInt<3>("h01"), buf_state[3]) @[Conditional.scala 37:30] when _T_4130 : @[Conditional.scala 39:67] - node _T_4131 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 450:60] - node _T_4132 = mux(_T_4131, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 450:31] - buf_nxtstate[3] <= _T_4132 @[lsu_bus_buffer.scala 450:25] - node _T_4133 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 451:46] - buf_state_en[3] <= _T_4133 @[lsu_bus_buffer.scala 451:25] + node _T_4131 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 449:60] + node _T_4132 = mux(_T_4131, UInt<3>("h00"), UInt<3>("h02")) @[lsu_bus_buffer.scala 449:31] + buf_nxtstate[3] <= _T_4132 @[lsu_bus_buffer.scala 449:25] + node _T_4133 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 450:46] + buf_state_en[3] <= _T_4133 @[lsu_bus_buffer.scala 450:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_4134 = eq(UInt<3>("h02"), buf_state[3]) @[Conditional.scala 37:30] when _T_4134 : @[Conditional.scala 39:67] - node _T_4135 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 454:60] - node _T_4136 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 454:89] - node _T_4137 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 454:124] - node _T_4138 = and(_T_4136, _T_4137) @[lsu_bus_buffer.scala 454:104] - node _T_4139 = mux(_T_4138, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 454:75] - node _T_4140 = mux(_T_4135, UInt<3>("h00"), _T_4139) @[lsu_bus_buffer.scala 454:31] - buf_nxtstate[3] <= _T_4140 @[lsu_bus_buffer.scala 454:25] - node _T_4141 = eq(obuf_tag0, UInt<3>("h03")) @[lsu_bus_buffer.scala 455:48] - node _T_4142 = eq(obuf_tag1, UInt<3>("h03")) @[lsu_bus_buffer.scala 455:104] - node _T_4143 = and(obuf_merge, _T_4142) @[lsu_bus_buffer.scala 455:91] - node _T_4144 = or(_T_4141, _T_4143) @[lsu_bus_buffer.scala 455:77] - node _T_4145 = and(_T_4144, obuf_valid) @[lsu_bus_buffer.scala 455:135] - node _T_4146 = and(_T_4145, obuf_wr_enQ) @[lsu_bus_buffer.scala 455:148] - buf_cmd_state_bus_en[3] <= _T_4146 @[lsu_bus_buffer.scala 455:33] - buf_state_bus_en[3] <= buf_cmd_state_bus_en[3] @[lsu_bus_buffer.scala 456:29] - node _T_4147 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 457:49] - node _T_4148 = or(_T_4147, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 457:70] - buf_state_en[3] <= _T_4148 @[lsu_bus_buffer.scala 457:25] - buf_ldfwd_in[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 458:25] - node _T_4149 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 459:56] - node _T_4150 = eq(_T_4149, UInt<1>("h00")) @[lsu_bus_buffer.scala 459:46] - node _T_4151 = and(buf_state_en[3], _T_4150) @[lsu_bus_buffer.scala 459:44] - node _T_4152 = and(_T_4151, obuf_nosend) @[lsu_bus_buffer.scala 459:60] - node _T_4153 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 459:76] - node _T_4154 = and(_T_4152, _T_4153) @[lsu_bus_buffer.scala 459:74] - buf_ldfwd_en[3] <= _T_4154 @[lsu_bus_buffer.scala 459:25] - node _T_4155 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 460:46] - buf_ldfwdtag_in[3] <= _T_4155 @[lsu_bus_buffer.scala 460:28] - node _T_4156 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 461:47] - node _T_4157 = and(_T_4156, obuf_nosend) @[lsu_bus_buffer.scala 461:67] - node _T_4158 = and(_T_4157, bus_rsp_read) @[lsu_bus_buffer.scala 461:81] - buf_data_en[3] <= _T_4158 @[lsu_bus_buffer.scala 461:24] - node _T_4159 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 462:48] - node _T_4160 = and(_T_4159, obuf_nosend) @[lsu_bus_buffer.scala 462:68] - node _T_4161 = and(_T_4160, bus_rsp_read_error) @[lsu_bus_buffer.scala 462:82] - buf_error_en[3] <= _T_4161 @[lsu_bus_buffer.scala 462:25] - node _T_4162 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 463:61] - node _T_4163 = bits(buf_addr[3], 2, 2) @[lsu_bus_buffer.scala 463:85] - node _T_4164 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 463:103] - node _T_4165 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 463:126] - node _T_4166 = mux(_T_4163, _T_4164, _T_4165) @[lsu_bus_buffer.scala 463:73] - node _T_4167 = mux(buf_error_en[3], _T_4162, _T_4166) @[lsu_bus_buffer.scala 463:30] - buf_data_in[3] <= _T_4167 @[lsu_bus_buffer.scala 463:24] + node _T_4135 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 453:60] + node _T_4136 = and(obuf_nosend, bus_rsp_read) @[lsu_bus_buffer.scala 453:89] + node _T_4137 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[lsu_bus_buffer.scala 453:124] + node _T_4138 = and(_T_4136, _T_4137) @[lsu_bus_buffer.scala 453:104] + node _T_4139 = mux(_T_4138, UInt<3>("h05"), UInt<3>("h03")) @[lsu_bus_buffer.scala 453:75] + node _T_4140 = mux(_T_4135, UInt<3>("h00"), _T_4139) @[lsu_bus_buffer.scala 453:31] + buf_nxtstate[3] <= _T_4140 @[lsu_bus_buffer.scala 453:25] + node _T_4141 = eq(obuf_tag0, UInt<3>("h03")) @[lsu_bus_buffer.scala 454:48] + node _T_4142 = eq(obuf_tag1, UInt<3>("h03")) @[lsu_bus_buffer.scala 454:104] + node _T_4143 = and(obuf_merge, _T_4142) @[lsu_bus_buffer.scala 454:91] + node _T_4144 = or(_T_4141, _T_4143) @[lsu_bus_buffer.scala 454:77] + node _T_4145 = and(_T_4144, obuf_valid) @[lsu_bus_buffer.scala 454:135] + node _T_4146 = and(_T_4145, obuf_wr_enQ) @[lsu_bus_buffer.scala 454:148] + buf_cmd_state_bus_en[3] <= _T_4146 @[lsu_bus_buffer.scala 454:33] + buf_state_bus_en[3] <= buf_cmd_state_bus_en[3] @[lsu_bus_buffer.scala 455:29] + node _T_4147 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 456:49] + node _T_4148 = or(_T_4147, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 456:70] + buf_state_en[3] <= _T_4148 @[lsu_bus_buffer.scala 456:25] + buf_ldfwd_in[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 457:25] + node _T_4149 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 458:56] + node _T_4150 = eq(_T_4149, UInt<1>("h00")) @[lsu_bus_buffer.scala 458:46] + node _T_4151 = and(buf_state_en[3], _T_4150) @[lsu_bus_buffer.scala 458:44] + node _T_4152 = and(_T_4151, obuf_nosend) @[lsu_bus_buffer.scala 458:60] + node _T_4153 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[lsu_bus_buffer.scala 458:76] + node _T_4154 = and(_T_4152, _T_4153) @[lsu_bus_buffer.scala 458:74] + buf_ldfwd_en[3] <= _T_4154 @[lsu_bus_buffer.scala 458:25] + node _T_4155 = bits(obuf_rdrsp_tag, 1, 0) @[lsu_bus_buffer.scala 459:46] + buf_ldfwdtag_in[3] <= _T_4155 @[lsu_bus_buffer.scala 459:28] + node _T_4156 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 460:47] + node _T_4157 = and(_T_4156, obuf_nosend) @[lsu_bus_buffer.scala 460:67] + node _T_4158 = and(_T_4157, bus_rsp_read) @[lsu_bus_buffer.scala 460:81] + buf_data_en[3] <= _T_4158 @[lsu_bus_buffer.scala 460:24] + node _T_4159 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 461:48] + node _T_4160 = and(_T_4159, obuf_nosend) @[lsu_bus_buffer.scala 461:68] + node _T_4161 = and(_T_4160, bus_rsp_read_error) @[lsu_bus_buffer.scala 461:82] + buf_error_en[3] <= _T_4161 @[lsu_bus_buffer.scala 461:25] + node _T_4162 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 462:61] + node _T_4163 = bits(buf_addr[3], 2, 2) @[lsu_bus_buffer.scala 462:85] + node _T_4164 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 462:103] + node _T_4165 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 462:126] + node _T_4166 = mux(_T_4163, _T_4164, _T_4165) @[lsu_bus_buffer.scala 462:73] + node _T_4167 = mux(buf_error_en[3], _T_4162, _T_4166) @[lsu_bus_buffer.scala 462:30] + buf_data_in[3] <= _T_4167 @[lsu_bus_buffer.scala 462:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_4168 = eq(UInt<3>("h03"), buf_state[3]) @[Conditional.scala 37:30] when _T_4168 : @[Conditional.scala 39:67] - node _T_4169 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 466:67] - node _T_4170 = and(UInt<1>("h01"), bus_rsp_write_error) @[lsu_bus_buffer.scala 466:94] - node _T_4171 = eq(_T_4170, UInt<1>("h00")) @[lsu_bus_buffer.scala 466:73] - node _T_4172 = and(_T_4169, _T_4171) @[lsu_bus_buffer.scala 466:71] - node _T_4173 = or(io.dec_tlu_force_halt, _T_4172) @[lsu_bus_buffer.scala 466:55] - node _T_4174 = bits(_T_4173, 0, 0) @[lsu_bus_buffer.scala 466:125] - node _T_4175 = eq(buf_samedw[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 467:30] - node _T_4176 = and(buf_dual[3], _T_4175) @[lsu_bus_buffer.scala 467:28] - node _T_4177 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 467:57] - node _T_4178 = eq(_T_4177, UInt<1>("h00")) @[lsu_bus_buffer.scala 467:47] - node _T_4179 = and(_T_4176, _T_4178) @[lsu_bus_buffer.scala 467:45] - node _T_4180 = neq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[lsu_bus_buffer.scala 467:90] - node _T_4181 = and(_T_4179, _T_4180) @[lsu_bus_buffer.scala 467:61] - node _T_4182 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 468:27] - node _T_4183 = or(_T_4182, any_done_wait_state) @[lsu_bus_buffer.scala 468:31] - node _T_4184 = eq(buf_samedw[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 468:70] - node _T_4185 = and(buf_dual[3], _T_4184) @[lsu_bus_buffer.scala 468:68] - node _T_4186 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 468:97] - node _T_4187 = eq(_T_4186, UInt<1>("h00")) @[lsu_bus_buffer.scala 468:87] - node _T_4188 = and(_T_4185, _T_4187) @[lsu_bus_buffer.scala 468:85] + node _T_4169 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 465:67] + node _T_4170 = and(UInt<1>("h01"), bus_rsp_write_error) @[lsu_bus_buffer.scala 465:94] + node _T_4171 = eq(_T_4170, UInt<1>("h00")) @[lsu_bus_buffer.scala 465:73] + node _T_4172 = and(_T_4169, _T_4171) @[lsu_bus_buffer.scala 465:71] + node _T_4173 = or(io.dec_tlu_force_halt, _T_4172) @[lsu_bus_buffer.scala 465:55] + node _T_4174 = bits(_T_4173, 0, 0) @[lsu_bus_buffer.scala 465:125] + node _T_4175 = eq(buf_samedw[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 466:30] + node _T_4176 = and(buf_dual[3], _T_4175) @[lsu_bus_buffer.scala 466:28] + node _T_4177 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 466:57] + node _T_4178 = eq(_T_4177, UInt<1>("h00")) @[lsu_bus_buffer.scala 466:47] + node _T_4179 = and(_T_4176, _T_4178) @[lsu_bus_buffer.scala 466:45] + node _T_4180 = neq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[lsu_bus_buffer.scala 466:90] + node _T_4181 = and(_T_4179, _T_4180) @[lsu_bus_buffer.scala 466:61] + node _T_4182 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 467:27] + node _T_4183 = or(_T_4182, any_done_wait_state) @[lsu_bus_buffer.scala 467:31] + node _T_4184 = eq(buf_samedw[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 467:70] + node _T_4185 = and(buf_dual[3], _T_4184) @[lsu_bus_buffer.scala 467:68] + node _T_4186 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 467:97] + node _T_4187 = eq(_T_4186, UInt<1>("h00")) @[lsu_bus_buffer.scala 467:87] + node _T_4188 = and(_T_4185, _T_4187) @[lsu_bus_buffer.scala 467:85] node _T_4189 = eq(buf_dualtag[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 57:118] node _T_4190 = bits(buf_ldfwd, 0, 0) @[lsu_bus_buffer.scala 57:129] node _T_4191 = eq(buf_dualtag[3], UInt<1>("h01")) @[lsu_bus_buffer.scala 57:118] @@ -99995,172 +99992,172 @@ circuit quasar_wrapper : node _T_4203 = or(_T_4202, _T_4200) @[Mux.scala 27:72] wire _T_4204 : UInt<1> @[Mux.scala 27:72] _T_4204 <= _T_4203 @[Mux.scala 27:72] - node _T_4205 = and(_T_4188, _T_4204) @[lsu_bus_buffer.scala 468:101] - node _T_4206 = eq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[lsu_bus_buffer.scala 468:167] - node _T_4207 = and(_T_4205, _T_4206) @[lsu_bus_buffer.scala 468:138] - node _T_4208 = and(_T_4207, any_done_wait_state) @[lsu_bus_buffer.scala 468:187] - node _T_4209 = or(_T_4183, _T_4208) @[lsu_bus_buffer.scala 468:53] - node _T_4210 = mux(_T_4209, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 468:16] - node _T_4211 = mux(_T_4181, UInt<3>("h04"), _T_4210) @[lsu_bus_buffer.scala 467:14] - node _T_4212 = mux(_T_4174, UInt<3>("h00"), _T_4211) @[lsu_bus_buffer.scala 466:31] - buf_nxtstate[3] <= _T_4212 @[lsu_bus_buffer.scala 466:25] - node _T_4213 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 469:73] - node _T_4214 = and(bus_rsp_write, _T_4213) @[lsu_bus_buffer.scala 469:52] - node _T_4215 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 470:46] - node _T_4216 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 471:23] - node _T_4217 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[lsu_bus_buffer.scala 471:47] - node _T_4218 = and(_T_4216, _T_4217) @[lsu_bus_buffer.scala 471:27] - node _T_4219 = or(_T_4215, _T_4218) @[lsu_bus_buffer.scala 470:77] - node _T_4220 = and(buf_dual[3], buf_dualhi[3]) @[lsu_bus_buffer.scala 472:26] - node _T_4221 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 472:54] - node _T_4222 = not(_T_4221) @[lsu_bus_buffer.scala 472:44] - node _T_4223 = and(_T_4220, _T_4222) @[lsu_bus_buffer.scala 472:42] - node _T_4224 = and(_T_4223, buf_samedw[3]) @[lsu_bus_buffer.scala 472:58] - node _T_4225 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[lsu_bus_buffer.scala 472:94] - node _T_4226 = and(_T_4224, _T_4225) @[lsu_bus_buffer.scala 472:74] - node _T_4227 = or(_T_4219, _T_4226) @[lsu_bus_buffer.scala 471:71] - node _T_4228 = and(bus_rsp_read, _T_4227) @[lsu_bus_buffer.scala 470:25] - node _T_4229 = or(_T_4214, _T_4228) @[lsu_bus_buffer.scala 469:105] - buf_resp_state_bus_en[3] <= _T_4229 @[lsu_bus_buffer.scala 469:34] - buf_state_bus_en[3] <= buf_resp_state_bus_en[3] @[lsu_bus_buffer.scala 473:29] - node _T_4230 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 474:49] - node _T_4231 = or(_T_4230, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 474:70] - buf_state_en[3] <= _T_4231 @[lsu_bus_buffer.scala 474:25] - node _T_4232 = and(buf_state_bus_en[3], bus_rsp_read) @[lsu_bus_buffer.scala 475:47] - node _T_4233 = and(_T_4232, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 475:62] - buf_data_en[3] <= _T_4233 @[lsu_bus_buffer.scala 475:24] - node _T_4234 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 476:48] - node _T_4235 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 476:111] - node _T_4236 = and(bus_rsp_read_error, _T_4235) @[lsu_bus_buffer.scala 476:91] - node _T_4237 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 477:42] - node _T_4238 = and(bus_rsp_read_error, _T_4237) @[lsu_bus_buffer.scala 477:31] - node _T_4239 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[lsu_bus_buffer.scala 477:66] - node _T_4240 = and(_T_4238, _T_4239) @[lsu_bus_buffer.scala 477:46] - node _T_4241 = or(_T_4236, _T_4240) @[lsu_bus_buffer.scala 476:143] - node _T_4242 = and(bus_rsp_write_error, UInt<1>("h01")) @[lsu_bus_buffer.scala 478:32] - node _T_4243 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 478:74] - node _T_4244 = and(_T_4242, _T_4243) @[lsu_bus_buffer.scala 478:53] - node _T_4245 = or(_T_4241, _T_4244) @[lsu_bus_buffer.scala 477:88] - node _T_4246 = and(_T_4234, _T_4245) @[lsu_bus_buffer.scala 476:68] - buf_error_en[3] <= _T_4246 @[lsu_bus_buffer.scala 476:25] - node _T_4247 = eq(buf_error_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 479:50] - node _T_4248 = and(buf_state_en[3], _T_4247) @[lsu_bus_buffer.scala 479:48] - node _T_4249 = bits(buf_addr[3], 2, 2) @[lsu_bus_buffer.scala 479:84] - node _T_4250 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 479:102] - node _T_4251 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 479:125] - node _T_4252 = mux(_T_4249, _T_4250, _T_4251) @[lsu_bus_buffer.scala 479:72] - node _T_4253 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 479:148] - node _T_4254 = mux(_T_4248, _T_4252, _T_4253) @[lsu_bus_buffer.scala 479:30] - buf_data_in[3] <= _T_4254 @[lsu_bus_buffer.scala 479:24] + node _T_4205 = and(_T_4188, _T_4204) @[lsu_bus_buffer.scala 467:101] + node _T_4206 = eq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[lsu_bus_buffer.scala 467:167] + node _T_4207 = and(_T_4205, _T_4206) @[lsu_bus_buffer.scala 467:138] + node _T_4208 = and(_T_4207, any_done_wait_state) @[lsu_bus_buffer.scala 467:187] + node _T_4209 = or(_T_4183, _T_4208) @[lsu_bus_buffer.scala 467:53] + node _T_4210 = mux(_T_4209, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 467:16] + node _T_4211 = mux(_T_4181, UInt<3>("h04"), _T_4210) @[lsu_bus_buffer.scala 466:14] + node _T_4212 = mux(_T_4174, UInt<3>("h00"), _T_4211) @[lsu_bus_buffer.scala 465:31] + buf_nxtstate[3] <= _T_4212 @[lsu_bus_buffer.scala 465:25] + node _T_4213 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 468:73] + node _T_4214 = and(bus_rsp_write, _T_4213) @[lsu_bus_buffer.scala 468:52] + node _T_4215 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 469:46] + node _T_4216 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 470:23] + node _T_4217 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[lsu_bus_buffer.scala 470:47] + node _T_4218 = and(_T_4216, _T_4217) @[lsu_bus_buffer.scala 470:27] + node _T_4219 = or(_T_4215, _T_4218) @[lsu_bus_buffer.scala 469:77] + node _T_4220 = and(buf_dual[3], buf_dualhi[3]) @[lsu_bus_buffer.scala 471:26] + node _T_4221 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 471:54] + node _T_4222 = not(_T_4221) @[lsu_bus_buffer.scala 471:44] + node _T_4223 = and(_T_4220, _T_4222) @[lsu_bus_buffer.scala 471:42] + node _T_4224 = and(_T_4223, buf_samedw[3]) @[lsu_bus_buffer.scala 471:58] + node _T_4225 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[lsu_bus_buffer.scala 471:94] + node _T_4226 = and(_T_4224, _T_4225) @[lsu_bus_buffer.scala 471:74] + node _T_4227 = or(_T_4219, _T_4226) @[lsu_bus_buffer.scala 470:71] + node _T_4228 = and(bus_rsp_read, _T_4227) @[lsu_bus_buffer.scala 469:25] + node _T_4229 = or(_T_4214, _T_4228) @[lsu_bus_buffer.scala 468:105] + buf_resp_state_bus_en[3] <= _T_4229 @[lsu_bus_buffer.scala 468:34] + buf_state_bus_en[3] <= buf_resp_state_bus_en[3] @[lsu_bus_buffer.scala 472:29] + node _T_4230 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 473:49] + node _T_4231 = or(_T_4230, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 473:70] + buf_state_en[3] <= _T_4231 @[lsu_bus_buffer.scala 473:25] + node _T_4232 = and(buf_state_bus_en[3], bus_rsp_read) @[lsu_bus_buffer.scala 474:47] + node _T_4233 = and(_T_4232, io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 474:62] + buf_data_en[3] <= _T_4233 @[lsu_bus_buffer.scala 474:24] + node _T_4234 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 475:48] + node _T_4235 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 475:111] + node _T_4236 = and(bus_rsp_read_error, _T_4235) @[lsu_bus_buffer.scala 475:91] + node _T_4237 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 476:42] + node _T_4238 = and(bus_rsp_read_error, _T_4237) @[lsu_bus_buffer.scala 476:31] + node _T_4239 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[lsu_bus_buffer.scala 476:66] + node _T_4240 = and(_T_4238, _T_4239) @[lsu_bus_buffer.scala 476:46] + node _T_4241 = or(_T_4236, _T_4240) @[lsu_bus_buffer.scala 475:143] + node _T_4242 = and(bus_rsp_write_error, UInt<1>("h01")) @[lsu_bus_buffer.scala 477:32] + node _T_4243 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[lsu_bus_buffer.scala 477:74] + node _T_4244 = and(_T_4242, _T_4243) @[lsu_bus_buffer.scala 477:53] + node _T_4245 = or(_T_4241, _T_4244) @[lsu_bus_buffer.scala 476:88] + node _T_4246 = and(_T_4234, _T_4245) @[lsu_bus_buffer.scala 475:68] + buf_error_en[3] <= _T_4246 @[lsu_bus_buffer.scala 475:25] + node _T_4247 = eq(buf_error_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 478:50] + node _T_4248 = and(buf_state_en[3], _T_4247) @[lsu_bus_buffer.scala 478:48] + node _T_4249 = bits(buf_addr[3], 2, 2) @[lsu_bus_buffer.scala 478:84] + node _T_4250 = bits(bus_rsp_rdata, 63, 32) @[lsu_bus_buffer.scala 478:102] + node _T_4251 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 478:125] + node _T_4252 = mux(_T_4249, _T_4250, _T_4251) @[lsu_bus_buffer.scala 478:72] + node _T_4253 = bits(bus_rsp_rdata, 31, 0) @[lsu_bus_buffer.scala 478:148] + node _T_4254 = mux(_T_4248, _T_4252, _T_4253) @[lsu_bus_buffer.scala 478:30] + buf_data_in[3] <= _T_4254 @[lsu_bus_buffer.scala 478:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_4255 = eq(UInt<3>("h04"), buf_state[3]) @[Conditional.scala 37:30] when _T_4255 : @[Conditional.scala 39:67] - node _T_4256 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 482:60] - node _T_4257 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 482:86] - node _T_4258 = dshr(buf_ldfwd, buf_dualtag[3]) @[lsu_bus_buffer.scala 482:101] - node _T_4259 = bits(_T_4258, 0, 0) @[lsu_bus_buffer.scala 482:101] - node _T_4260 = or(_T_4257, _T_4259) @[lsu_bus_buffer.scala 482:90] - node _T_4261 = or(_T_4260, any_done_wait_state) @[lsu_bus_buffer.scala 482:118] - node _T_4262 = mux(_T_4261, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 482:75] - node _T_4263 = mux(_T_4256, UInt<3>("h00"), _T_4262) @[lsu_bus_buffer.scala 482:31] - buf_nxtstate[3] <= _T_4263 @[lsu_bus_buffer.scala 482:25] - node _T_4264 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[lsu_bus_buffer.scala 483:66] - node _T_4265 = dshr(buf_ldfwd, buf_dualtag[3]) @[lsu_bus_buffer.scala 484:21] - node _T_4266 = bits(_T_4265, 0, 0) @[lsu_bus_buffer.scala 484:21] - node _T_4267 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[3]]) @[lsu_bus_buffer.scala 484:58] - node _T_4268 = and(_T_4266, _T_4267) @[lsu_bus_buffer.scala 484:38] - node _T_4269 = or(_T_4264, _T_4268) @[lsu_bus_buffer.scala 483:95] - node _T_4270 = and(bus_rsp_read, _T_4269) @[lsu_bus_buffer.scala 483:45] - buf_state_bus_en[3] <= _T_4270 @[lsu_bus_buffer.scala 483:29] - node _T_4271 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 485:49] - node _T_4272 = or(_T_4271, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 485:70] - buf_state_en[3] <= _T_4272 @[lsu_bus_buffer.scala 485:25] + node _T_4256 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 481:60] + node _T_4257 = bits(buf_ldfwd, 3, 3) @[lsu_bus_buffer.scala 481:86] + node _T_4258 = dshr(buf_ldfwd, buf_dualtag[3]) @[lsu_bus_buffer.scala 481:101] + node _T_4259 = bits(_T_4258, 0, 0) @[lsu_bus_buffer.scala 481:101] + node _T_4260 = or(_T_4257, _T_4259) @[lsu_bus_buffer.scala 481:90] + node _T_4261 = or(_T_4260, any_done_wait_state) @[lsu_bus_buffer.scala 481:118] + node _T_4262 = mux(_T_4261, UInt<3>("h05"), UInt<3>("h06")) @[lsu_bus_buffer.scala 481:75] + node _T_4263 = mux(_T_4256, UInt<3>("h00"), _T_4262) @[lsu_bus_buffer.scala 481:31] + buf_nxtstate[3] <= _T_4263 @[lsu_bus_buffer.scala 481:25] + node _T_4264 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[lsu_bus_buffer.scala 482:66] + node _T_4265 = dshr(buf_ldfwd, buf_dualtag[3]) @[lsu_bus_buffer.scala 483:21] + node _T_4266 = bits(_T_4265, 0, 0) @[lsu_bus_buffer.scala 483:21] + node _T_4267 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[3]]) @[lsu_bus_buffer.scala 483:58] + node _T_4268 = and(_T_4266, _T_4267) @[lsu_bus_buffer.scala 483:38] + node _T_4269 = or(_T_4264, _T_4268) @[lsu_bus_buffer.scala 482:95] + node _T_4270 = and(bus_rsp_read, _T_4269) @[lsu_bus_buffer.scala 482:45] + buf_state_bus_en[3] <= _T_4270 @[lsu_bus_buffer.scala 482:29] + node _T_4271 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[lsu_bus_buffer.scala 484:49] + node _T_4272 = or(_T_4271, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 484:70] + buf_state_en[3] <= _T_4272 @[lsu_bus_buffer.scala 484:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_4273 = eq(UInt<3>("h05"), buf_state[3]) @[Conditional.scala 37:30] when _T_4273 : @[Conditional.scala 39:67] - node _T_4274 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 488:60] - node _T_4275 = mux(_T_4274, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 488:31] - buf_nxtstate[3] <= _T_4275 @[lsu_bus_buffer.scala 488:25] - node _T_4276 = eq(RspPtr, UInt<2>("h03")) @[lsu_bus_buffer.scala 489:37] - node _T_4277 = eq(buf_dualtag[3], RspPtr) @[lsu_bus_buffer.scala 489:98] - node _T_4278 = and(buf_dual[3], _T_4277) @[lsu_bus_buffer.scala 489:80] - node _T_4279 = or(_T_4276, _T_4278) @[lsu_bus_buffer.scala 489:65] - node _T_4280 = or(_T_4279, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 489:112] - buf_state_en[3] <= _T_4280 @[lsu_bus_buffer.scala 489:25] + node _T_4274 = bits(io.dec_tlu_force_halt, 0, 0) @[lsu_bus_buffer.scala 487:60] + node _T_4275 = mux(_T_4274, UInt<3>("h00"), UInt<3>("h06")) @[lsu_bus_buffer.scala 487:31] + buf_nxtstate[3] <= _T_4275 @[lsu_bus_buffer.scala 487:25] + node _T_4276 = eq(RspPtr, UInt<2>("h03")) @[lsu_bus_buffer.scala 488:37] + node _T_4277 = eq(buf_dualtag[3], RspPtr) @[lsu_bus_buffer.scala 488:98] + node _T_4278 = and(buf_dual[3], _T_4277) @[lsu_bus_buffer.scala 488:80] + node _T_4279 = or(_T_4276, _T_4278) @[lsu_bus_buffer.scala 488:65] + node _T_4280 = or(_T_4279, io.dec_tlu_force_halt) @[lsu_bus_buffer.scala 488:112] + buf_state_en[3] <= _T_4280 @[lsu_bus_buffer.scala 488:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_4281 = eq(UInt<3>("h06"), buf_state[3]) @[Conditional.scala 37:30] when _T_4281 : @[Conditional.scala 39:67] - buf_nxtstate[3] <= UInt<3>("h00") @[lsu_bus_buffer.scala 492:25] - buf_rst[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 493:20] - buf_state_en[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 494:25] - buf_ldfwd_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 495:25] - buf_ldfwd_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 496:25] + buf_nxtstate[3] <= UInt<3>("h00") @[lsu_bus_buffer.scala 491:25] + buf_rst[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 492:20] + buf_state_en[3] <= UInt<1>("h01") @[lsu_bus_buffer.scala 493:25] + buf_ldfwd_in[3] <= UInt<1>("h00") @[lsu_bus_buffer.scala 494:25] + buf_ldfwd_en[3] <= buf_state_en[3] @[lsu_bus_buffer.scala 495:25] skip @[Conditional.scala 39:67] - node _T_4282 = bits(buf_state_en[3], 0, 0) @[lsu_bus_buffer.scala 499:108] + node _T_4282 = bits(buf_state_en[3], 0, 0) @[lsu_bus_buffer.scala 498:108] reg _T_4283 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4282 : @[Reg.scala 28:19] _T_4283 <= buf_nxtstate[3] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_state[3] <= _T_4283 @[lsu_bus_buffer.scala 499:18] - reg _T_4284 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 500:60] - _T_4284 <= buf_age_in_3 @[lsu_bus_buffer.scala 500:60] - buf_ageQ[3] <= _T_4284 @[lsu_bus_buffer.scala 500:17] - reg _T_4285 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 501:63] - _T_4285 <= buf_rspage_in[3] @[lsu_bus_buffer.scala 501:63] - buf_rspageQ[3] <= _T_4285 @[lsu_bus_buffer.scala 501:20] - node _T_4286 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 502:109] + buf_state[3] <= _T_4283 @[lsu_bus_buffer.scala 498:18] + reg _T_4284 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 499:60] + _T_4284 <= buf_age_in_3 @[lsu_bus_buffer.scala 499:60] + buf_ageQ[3] <= _T_4284 @[lsu_bus_buffer.scala 499:17] + reg _T_4285 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 500:63] + _T_4285 <= buf_rspage_in[3] @[lsu_bus_buffer.scala 500:63] + buf_rspageQ[3] <= _T_4285 @[lsu_bus_buffer.scala 500:20] + node _T_4286 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 501:109] reg _T_4287 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4286 : @[Reg.scala 28:19] _T_4287 <= buf_dualtag_in[3] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dualtag[3] <= _T_4287 @[lsu_bus_buffer.scala 502:20] - node _T_4288 = bits(buf_dual_in, 3, 3) @[lsu_bus_buffer.scala 503:74] - node _T_4289 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 503:107] + buf_dualtag[3] <= _T_4287 @[lsu_bus_buffer.scala 501:20] + node _T_4288 = bits(buf_dual_in, 3, 3) @[lsu_bus_buffer.scala 502:74] + node _T_4289 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 502:107] reg _T_4290 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4289 : @[Reg.scala 28:19] _T_4290 <= _T_4288 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dual[3] <= _T_4290 @[lsu_bus_buffer.scala 503:17] - node _T_4291 = bits(buf_samedw_in, 3, 3) @[lsu_bus_buffer.scala 504:78] - node _T_4292 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 504:111] + buf_dual[3] <= _T_4290 @[lsu_bus_buffer.scala 502:17] + node _T_4291 = bits(buf_samedw_in, 3, 3) @[lsu_bus_buffer.scala 503:78] + node _T_4292 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 503:111] reg _T_4293 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4292 : @[Reg.scala 28:19] _T_4293 <= _T_4291 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_samedw[3] <= _T_4293 @[lsu_bus_buffer.scala 504:19] - node _T_4294 = bits(buf_nomerge_in, 3, 3) @[lsu_bus_buffer.scala 505:80] - node _T_4295 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 505:113] + buf_samedw[3] <= _T_4293 @[lsu_bus_buffer.scala 503:19] + node _T_4294 = bits(buf_nomerge_in, 3, 3) @[lsu_bus_buffer.scala 504:80] + node _T_4295 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 504:113] reg _T_4296 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4295 : @[Reg.scala 28:19] _T_4296 <= _T_4294 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_nomerge[3] <= _T_4296 @[lsu_bus_buffer.scala 505:20] - node _T_4297 = bits(buf_dualhi_in, 3, 3) @[lsu_bus_buffer.scala 506:78] - node _T_4298 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 506:111] + buf_nomerge[3] <= _T_4296 @[lsu_bus_buffer.scala 504:20] + node _T_4297 = bits(buf_dualhi_in, 3, 3) @[lsu_bus_buffer.scala 505:78] + node _T_4298 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 505:111] reg _T_4299 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4298 : @[Reg.scala 28:19] _T_4299 <= _T_4297 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dualhi[3] <= _T_4299 @[lsu_bus_buffer.scala 506:19] - node _T_4300 = bits(buf_ldfwd_en[0], 0, 0) @[lsu_bus_buffer.scala 509:131] + buf_dualhi[3] <= _T_4299 @[lsu_bus_buffer.scala 505:19] + node _T_4300 = bits(buf_ldfwd_en[0], 0, 0) @[lsu_bus_buffer.scala 508:131] reg _T_4301 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4300 : @[Reg.scala 28:19] _T_4301 <= buf_ldfwd_in[0] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4302 = bits(buf_ldfwd_en[1], 0, 0) @[lsu_bus_buffer.scala 509:131] + node _T_4302 = bits(buf_ldfwd_en[1], 0, 0) @[lsu_bus_buffer.scala 508:131] reg _T_4303 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4302 : @[Reg.scala 28:19] _T_4303 <= buf_ldfwd_in[1] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4304 = bits(buf_ldfwd_en[2], 0, 0) @[lsu_bus_buffer.scala 509:131] + node _T_4304 = bits(buf_ldfwd_en[2], 0, 0) @[lsu_bus_buffer.scala 508:131] reg _T_4305 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4304 : @[Reg.scala 28:19] _T_4305 <= buf_ldfwd_in[2] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4306 = bits(buf_ldfwd_en[3], 0, 0) @[lsu_bus_buffer.scala 509:131] + node _T_4306 = bits(buf_ldfwd_en[3], 0, 0) @[lsu_bus_buffer.scala 508:131] reg _T_4307 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4306 : @[Reg.scala 28:19] _T_4307 <= buf_ldfwd_in[3] @[Reg.scala 28:23] @@ -100168,51 +100165,51 @@ circuit quasar_wrapper : node _T_4308 = cat(_T_4307, _T_4305) @[Cat.scala 29:58] node _T_4309 = cat(_T_4308, _T_4303) @[Cat.scala 29:58] node _T_4310 = cat(_T_4309, _T_4301) @[Cat.scala 29:58] - buf_ldfwd <= _T_4310 @[lsu_bus_buffer.scala 509:13] - node _T_4311 = bits(buf_ldfwd_en[0], 0, 0) @[lsu_bus_buffer.scala 510:132] + buf_ldfwd <= _T_4310 @[lsu_bus_buffer.scala 508:13] + node _T_4311 = bits(buf_ldfwd_en[0], 0, 0) @[lsu_bus_buffer.scala 509:132] reg _T_4312 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4311 : @[Reg.scala 28:19] _T_4312 <= buf_ldfwdtag_in[0] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4313 = bits(buf_ldfwd_en[1], 0, 0) @[lsu_bus_buffer.scala 510:132] + node _T_4313 = bits(buf_ldfwd_en[1], 0, 0) @[lsu_bus_buffer.scala 509:132] reg _T_4314 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4313 : @[Reg.scala 28:19] _T_4314 <= buf_ldfwdtag_in[1] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4315 = bits(buf_ldfwd_en[2], 0, 0) @[lsu_bus_buffer.scala 510:132] + node _T_4315 = bits(buf_ldfwd_en[2], 0, 0) @[lsu_bus_buffer.scala 509:132] reg _T_4316 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4315 : @[Reg.scala 28:19] _T_4316 <= buf_ldfwdtag_in[2] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4317 = bits(buf_ldfwd_en[3], 0, 0) @[lsu_bus_buffer.scala 510:132] + node _T_4317 = bits(buf_ldfwd_en[3], 0, 0) @[lsu_bus_buffer.scala 509:132] reg _T_4318 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4317 : @[Reg.scala 28:19] _T_4318 <= buf_ldfwdtag_in[3] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_ldfwdtag[0] <= _T_4312 @[lsu_bus_buffer.scala 510:16] - buf_ldfwdtag[1] <= _T_4314 @[lsu_bus_buffer.scala 510:16] - buf_ldfwdtag[2] <= _T_4316 @[lsu_bus_buffer.scala 510:16] - buf_ldfwdtag[3] <= _T_4318 @[lsu_bus_buffer.scala 510:16] - node _T_4319 = bits(buf_sideeffect_in, 0, 0) @[lsu_bus_buffer.scala 511:105] - node _T_4320 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 511:138] + buf_ldfwdtag[0] <= _T_4312 @[lsu_bus_buffer.scala 509:16] + buf_ldfwdtag[1] <= _T_4314 @[lsu_bus_buffer.scala 509:16] + buf_ldfwdtag[2] <= _T_4316 @[lsu_bus_buffer.scala 509:16] + buf_ldfwdtag[3] <= _T_4318 @[lsu_bus_buffer.scala 509:16] + node _T_4319 = bits(buf_sideeffect_in, 0, 0) @[lsu_bus_buffer.scala 510:105] + node _T_4320 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 510:138] reg _T_4321 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4320 : @[Reg.scala 28:19] _T_4321 <= _T_4319 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4322 = bits(buf_sideeffect_in, 1, 1) @[lsu_bus_buffer.scala 511:105] - node _T_4323 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 511:138] + node _T_4322 = bits(buf_sideeffect_in, 1, 1) @[lsu_bus_buffer.scala 510:105] + node _T_4323 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 510:138] reg _T_4324 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4323 : @[Reg.scala 28:19] _T_4324 <= _T_4322 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4325 = bits(buf_sideeffect_in, 2, 2) @[lsu_bus_buffer.scala 511:105] - node _T_4326 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 511:138] + node _T_4325 = bits(buf_sideeffect_in, 2, 2) @[lsu_bus_buffer.scala 510:105] + node _T_4326 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 510:138] reg _T_4327 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4326 : @[Reg.scala 28:19] _T_4327 <= _T_4325 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4328 = bits(buf_sideeffect_in, 3, 3) @[lsu_bus_buffer.scala 511:105] - node _T_4329 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 511:138] + node _T_4328 = bits(buf_sideeffect_in, 3, 3) @[lsu_bus_buffer.scala 510:105] + node _T_4329 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 510:138] reg _T_4330 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4329 : @[Reg.scala 28:19] _T_4330 <= _T_4328 @[Reg.scala 28:23] @@ -100220,27 +100217,27 @@ circuit quasar_wrapper : node _T_4331 = cat(_T_4330, _T_4327) @[Cat.scala 29:58] node _T_4332 = cat(_T_4331, _T_4324) @[Cat.scala 29:58] node _T_4333 = cat(_T_4332, _T_4321) @[Cat.scala 29:58] - buf_sideeffect <= _T_4333 @[lsu_bus_buffer.scala 511:18] - node _T_4334 = bits(buf_unsign_in, 0, 0) @[lsu_bus_buffer.scala 512:97] - node _T_4335 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 512:130] + buf_sideeffect <= _T_4333 @[lsu_bus_buffer.scala 510:18] + node _T_4334 = bits(buf_unsign_in, 0, 0) @[lsu_bus_buffer.scala 511:97] + node _T_4335 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 511:130] reg _T_4336 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4335 : @[Reg.scala 28:19] _T_4336 <= _T_4334 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4337 = bits(buf_unsign_in, 1, 1) @[lsu_bus_buffer.scala 512:97] - node _T_4338 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 512:130] + node _T_4337 = bits(buf_unsign_in, 1, 1) @[lsu_bus_buffer.scala 511:97] + node _T_4338 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 511:130] reg _T_4339 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4338 : @[Reg.scala 28:19] _T_4339 <= _T_4337 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4340 = bits(buf_unsign_in, 2, 2) @[lsu_bus_buffer.scala 512:97] - node _T_4341 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 512:130] + node _T_4340 = bits(buf_unsign_in, 2, 2) @[lsu_bus_buffer.scala 511:97] + node _T_4341 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 511:130] reg _T_4342 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4341 : @[Reg.scala 28:19] _T_4342 <= _T_4340 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4343 = bits(buf_unsign_in, 3, 3) @[lsu_bus_buffer.scala 512:97] - node _T_4344 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 512:130] + node _T_4343 = bits(buf_unsign_in, 3, 3) @[lsu_bus_buffer.scala 511:97] + node _T_4344 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 511:130] reg _T_4345 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4344 : @[Reg.scala 28:19] _T_4345 <= _T_4343 @[Reg.scala 28:23] @@ -100248,27 +100245,27 @@ circuit quasar_wrapper : node _T_4346 = cat(_T_4345, _T_4342) @[Cat.scala 29:58] node _T_4347 = cat(_T_4346, _T_4339) @[Cat.scala 29:58] node _T_4348 = cat(_T_4347, _T_4336) @[Cat.scala 29:58] - buf_unsign <= _T_4348 @[lsu_bus_buffer.scala 512:14] - node _T_4349 = bits(buf_write_in, 0, 0) @[lsu_bus_buffer.scala 513:95] - node _T_4350 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 513:128] + buf_unsign <= _T_4348 @[lsu_bus_buffer.scala 511:14] + node _T_4349 = bits(buf_write_in, 0, 0) @[lsu_bus_buffer.scala 512:95] + node _T_4350 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 512:128] reg _T_4351 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4350 : @[Reg.scala 28:19] _T_4351 <= _T_4349 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4352 = bits(buf_write_in, 1, 1) @[lsu_bus_buffer.scala 513:95] - node _T_4353 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 513:128] + node _T_4352 = bits(buf_write_in, 1, 1) @[lsu_bus_buffer.scala 512:95] + node _T_4353 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 512:128] reg _T_4354 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4353 : @[Reg.scala 28:19] _T_4354 <= _T_4352 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4355 = bits(buf_write_in, 2, 2) @[lsu_bus_buffer.scala 513:95] - node _T_4356 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 513:128] + node _T_4355 = bits(buf_write_in, 2, 2) @[lsu_bus_buffer.scala 512:95] + node _T_4356 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 512:128] reg _T_4357 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4356 : @[Reg.scala 28:19] _T_4357 <= _T_4355 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4358 = bits(buf_write_in, 3, 3) @[lsu_bus_buffer.scala 513:95] - node _T_4359 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 513:128] + node _T_4358 = bits(buf_write_in, 3, 3) @[lsu_bus_buffer.scala 512:95] + node _T_4359 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 512:128] reg _T_4360 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4359 : @[Reg.scala 28:19] _T_4360 <= _T_4358 @[Reg.scala 28:23] @@ -100276,32 +100273,32 @@ circuit quasar_wrapper : node _T_4361 = cat(_T_4360, _T_4357) @[Cat.scala 29:58] node _T_4362 = cat(_T_4361, _T_4354) @[Cat.scala 29:58] node _T_4363 = cat(_T_4362, _T_4351) @[Cat.scala 29:58] - buf_write <= _T_4363 @[lsu_bus_buffer.scala 513:13] - node _T_4364 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 514:117] + buf_write <= _T_4363 @[lsu_bus_buffer.scala 512:13] + node _T_4364 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 513:117] reg _T_4365 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4364 : @[Reg.scala 28:19] _T_4365 <= buf_sz_in[0] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4366 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 514:117] + node _T_4366 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 513:117] reg _T_4367 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4366 : @[Reg.scala 28:19] _T_4367 <= buf_sz_in[1] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4368 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 514:117] + node _T_4368 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 513:117] reg _T_4369 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4368 : @[Reg.scala 28:19] _T_4369 <= buf_sz_in[2] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4370 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 514:117] + node _T_4370 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 513:117] reg _T_4371 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4370 : @[Reg.scala 28:19] _T_4371 <= buf_sz_in[3] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_sz[0] <= _T_4365 @[lsu_bus_buffer.scala 514:10] - buf_sz[1] <= _T_4367 @[lsu_bus_buffer.scala 514:10] - buf_sz[2] <= _T_4369 @[lsu_bus_buffer.scala 514:10] - buf_sz[3] <= _T_4371 @[lsu_bus_buffer.scala 514:10] - node _T_4372 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 515:80] + buf_sz[0] <= _T_4365 @[lsu_bus_buffer.scala 513:10] + buf_sz[1] <= _T_4367 @[lsu_bus_buffer.scala 513:10] + buf_sz[2] <= _T_4369 @[lsu_bus_buffer.scala 513:10] + buf_sz[3] <= _T_4371 @[lsu_bus_buffer.scala 513:10] + node _T_4372 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 514:80] inst rvclkhdr_4 of rvclkhdr_816 @[lib.scala 352:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -100310,7 +100307,7 @@ circuit quasar_wrapper : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_4373 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_4373 <= buf_addr_in[0] @[lib.scala 358:16] - node _T_4374 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 515:80] + node _T_4374 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 514:80] inst rvclkhdr_5 of rvclkhdr_817 @[lib.scala 352:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -100319,7 +100316,7 @@ circuit quasar_wrapper : rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_4375 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_4375 <= buf_addr_in[1] @[lib.scala 358:16] - node _T_4376 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 515:80] + node _T_4376 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 514:80] inst rvclkhdr_6 of rvclkhdr_818 @[lib.scala 352:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset @@ -100328,7 +100325,7 @@ circuit quasar_wrapper : rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_4377 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_4377 <= buf_addr_in[2] @[lib.scala 358:16] - node _T_4378 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 515:80] + node _T_4378 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 514:80] inst rvclkhdr_7 of rvclkhdr_819 @[lib.scala 352:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset @@ -100337,34 +100334,34 @@ circuit quasar_wrapper : rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_4379 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_4379 <= buf_addr_in[3] @[lib.scala 358:16] - buf_addr[0] <= _T_4373 @[lsu_bus_buffer.scala 515:12] - buf_addr[1] <= _T_4375 @[lsu_bus_buffer.scala 515:12] - buf_addr[2] <= _T_4377 @[lsu_bus_buffer.scala 515:12] - buf_addr[3] <= _T_4379 @[lsu_bus_buffer.scala 515:12] - node _T_4380 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 516:125] + buf_addr[0] <= _T_4373 @[lsu_bus_buffer.scala 514:12] + buf_addr[1] <= _T_4375 @[lsu_bus_buffer.scala 514:12] + buf_addr[2] <= _T_4377 @[lsu_bus_buffer.scala 514:12] + buf_addr[3] <= _T_4379 @[lsu_bus_buffer.scala 514:12] + node _T_4380 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 515:125] reg _T_4381 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4380 : @[Reg.scala 28:19] _T_4381 <= buf_byteen_in[0] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4382 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 516:125] + node _T_4382 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 515:125] reg _T_4383 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4382 : @[Reg.scala 28:19] _T_4383 <= buf_byteen_in[1] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4384 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 516:125] + node _T_4384 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 515:125] reg _T_4385 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4384 : @[Reg.scala 28:19] _T_4385 <= buf_byteen_in[2] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_4386 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 516:125] + node _T_4386 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 515:125] reg _T_4387 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_4386 : @[Reg.scala 28:19] _T_4387 <= buf_byteen_in[3] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_byteen[0] <= _T_4381 @[lsu_bus_buffer.scala 516:14] - buf_byteen[1] <= _T_4383 @[lsu_bus_buffer.scala 516:14] - buf_byteen[2] <= _T_4385 @[lsu_bus_buffer.scala 516:14] - buf_byteen[3] <= _T_4387 @[lsu_bus_buffer.scala 516:14] + buf_byteen[0] <= _T_4381 @[lsu_bus_buffer.scala 515:14] + buf_byteen[1] <= _T_4383 @[lsu_bus_buffer.scala 515:14] + buf_byteen[2] <= _T_4385 @[lsu_bus_buffer.scala 515:14] + buf_byteen[3] <= _T_4387 @[lsu_bus_buffer.scala 515:14] inst rvclkhdr_8 of rvclkhdr_820 @[lib.scala 352:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset @@ -100397,175 +100394,175 @@ circuit quasar_wrapper : rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_4391 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_4391 <= buf_data_in[3] @[lib.scala 358:16] - buf_data[0] <= _T_4388 @[lsu_bus_buffer.scala 517:12] - buf_data[1] <= _T_4389 @[lsu_bus_buffer.scala 517:12] - buf_data[2] <= _T_4390 @[lsu_bus_buffer.scala 517:12] - buf_data[3] <= _T_4391 @[lsu_bus_buffer.scala 517:12] - node _T_4392 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 518:119] - node _T_4393 = mux(buf_error_en[0], UInt<1>("h01"), _T_4392) @[lsu_bus_buffer.scala 518:84] - node _T_4394 = eq(buf_rst[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 518:126] - node _T_4395 = and(_T_4393, _T_4394) @[lsu_bus_buffer.scala 518:124] - reg _T_4396 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 518:80] - _T_4396 <= _T_4395 @[lsu_bus_buffer.scala 518:80] - node _T_4397 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 518:119] - node _T_4398 = mux(buf_error_en[1], UInt<1>("h01"), _T_4397) @[lsu_bus_buffer.scala 518:84] - node _T_4399 = eq(buf_rst[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 518:126] - node _T_4400 = and(_T_4398, _T_4399) @[lsu_bus_buffer.scala 518:124] - reg _T_4401 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 518:80] - _T_4401 <= _T_4400 @[lsu_bus_buffer.scala 518:80] - node _T_4402 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 518:119] - node _T_4403 = mux(buf_error_en[2], UInt<1>("h01"), _T_4402) @[lsu_bus_buffer.scala 518:84] - node _T_4404 = eq(buf_rst[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 518:126] - node _T_4405 = and(_T_4403, _T_4404) @[lsu_bus_buffer.scala 518:124] - reg _T_4406 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 518:80] - _T_4406 <= _T_4405 @[lsu_bus_buffer.scala 518:80] - node _T_4407 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 518:119] - node _T_4408 = mux(buf_error_en[3], UInt<1>("h01"), _T_4407) @[lsu_bus_buffer.scala 518:84] - node _T_4409 = eq(buf_rst[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 518:126] - node _T_4410 = and(_T_4408, _T_4409) @[lsu_bus_buffer.scala 518:124] - reg _T_4411 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 518:80] - _T_4411 <= _T_4410 @[lsu_bus_buffer.scala 518:80] + buf_data[0] <= _T_4388 @[lsu_bus_buffer.scala 516:12] + buf_data[1] <= _T_4389 @[lsu_bus_buffer.scala 516:12] + buf_data[2] <= _T_4390 @[lsu_bus_buffer.scala 516:12] + buf_data[3] <= _T_4391 @[lsu_bus_buffer.scala 516:12] + node _T_4392 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 517:119] + node _T_4393 = mux(buf_error_en[0], UInt<1>("h01"), _T_4392) @[lsu_bus_buffer.scala 517:84] + node _T_4394 = eq(buf_rst[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 517:126] + node _T_4395 = and(_T_4393, _T_4394) @[lsu_bus_buffer.scala 517:124] + reg _T_4396 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 517:80] + _T_4396 <= _T_4395 @[lsu_bus_buffer.scala 517:80] + node _T_4397 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 517:119] + node _T_4398 = mux(buf_error_en[1], UInt<1>("h01"), _T_4397) @[lsu_bus_buffer.scala 517:84] + node _T_4399 = eq(buf_rst[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 517:126] + node _T_4400 = and(_T_4398, _T_4399) @[lsu_bus_buffer.scala 517:124] + reg _T_4401 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 517:80] + _T_4401 <= _T_4400 @[lsu_bus_buffer.scala 517:80] + node _T_4402 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 517:119] + node _T_4403 = mux(buf_error_en[2], UInt<1>("h01"), _T_4402) @[lsu_bus_buffer.scala 517:84] + node _T_4404 = eq(buf_rst[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 517:126] + node _T_4405 = and(_T_4403, _T_4404) @[lsu_bus_buffer.scala 517:124] + reg _T_4406 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 517:80] + _T_4406 <= _T_4405 @[lsu_bus_buffer.scala 517:80] + node _T_4407 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 517:119] + node _T_4408 = mux(buf_error_en[3], UInt<1>("h01"), _T_4407) @[lsu_bus_buffer.scala 517:84] + node _T_4409 = eq(buf_rst[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 517:126] + node _T_4410 = and(_T_4408, _T_4409) @[lsu_bus_buffer.scala 517:124] + reg _T_4411 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 517:80] + _T_4411 <= _T_4410 @[lsu_bus_buffer.scala 517:80] node _T_4412 = cat(_T_4411, _T_4406) @[Cat.scala 29:58] node _T_4413 = cat(_T_4412, _T_4401) @[Cat.scala 29:58] node _T_4414 = cat(_T_4413, _T_4396) @[Cat.scala 29:58] - buf_error <= _T_4414 @[lsu_bus_buffer.scala 518:13] + buf_error <= _T_4414 @[lsu_bus_buffer.scala 517:13] node _T_4415 = cat(io.lsu_busreq_m, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_4416 = mux(io.ldst_dual_m, _T_4415, io.lsu_busreq_m) @[lsu_bus_buffer.scala 521:28] + node _T_4416 = mux(io.ldst_dual_m, _T_4415, io.lsu_busreq_m) @[lsu_bus_buffer.scala 520:28] node _T_4417 = cat(io.lsu_busreq_r, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_4418 = mux(io.ldst_dual_r, _T_4417, io.lsu_busreq_r) @[lsu_bus_buffer.scala 521:94] - node _T_4419 = add(_T_4416, _T_4418) @[lsu_bus_buffer.scala 521:88] - node _T_4420 = add(_T_4419, ibuf_valid) @[lsu_bus_buffer.scala 521:154] - node _T_4421 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 521:190] - node _T_4422 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 521:190] - node _T_4423 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 521:190] - node _T_4424 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 521:190] - node _T_4425 = add(_T_4421, _T_4422) @[lsu_bus_buffer.scala 521:217] - node _T_4426 = add(_T_4425, _T_4423) @[lsu_bus_buffer.scala 521:217] - node _T_4427 = add(_T_4426, _T_4424) @[lsu_bus_buffer.scala 521:217] - node _T_4428 = add(_T_4420, _T_4427) @[lsu_bus_buffer.scala 521:169] - node buf_numvld_any = tail(_T_4428, 1) @[lsu_bus_buffer.scala 521:169] - node _T_4429 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 522:60] - node _T_4430 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 522:79] - node _T_4431 = and(_T_4429, _T_4430) @[lsu_bus_buffer.scala 522:64] - node _T_4432 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 522:91] - node _T_4433 = and(_T_4431, _T_4432) @[lsu_bus_buffer.scala 522:89] - node _T_4434 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 522:60] - node _T_4435 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 522:79] - node _T_4436 = and(_T_4434, _T_4435) @[lsu_bus_buffer.scala 522:64] - node _T_4437 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 522:91] - node _T_4438 = and(_T_4436, _T_4437) @[lsu_bus_buffer.scala 522:89] - node _T_4439 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 522:60] - node _T_4440 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 522:79] - node _T_4441 = and(_T_4439, _T_4440) @[lsu_bus_buffer.scala 522:64] - node _T_4442 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 522:91] - node _T_4443 = and(_T_4441, _T_4442) @[lsu_bus_buffer.scala 522:89] - node _T_4444 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 522:60] - node _T_4445 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 522:79] - node _T_4446 = and(_T_4444, _T_4445) @[lsu_bus_buffer.scala 522:64] - node _T_4447 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 522:91] - node _T_4448 = and(_T_4446, _T_4447) @[lsu_bus_buffer.scala 522:89] - node _T_4449 = add(_T_4448, _T_4443) @[lsu_bus_buffer.scala 522:142] - node _T_4450 = add(_T_4449, _T_4438) @[lsu_bus_buffer.scala 522:142] - node _T_4451 = add(_T_4450, _T_4433) @[lsu_bus_buffer.scala 522:142] - buf_numvld_wrcmd_any <= _T_4451 @[lsu_bus_buffer.scala 522:24] - node _T_4452 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 523:63] - node _T_4453 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:75] - node _T_4454 = and(_T_4452, _T_4453) @[lsu_bus_buffer.scala 523:73] - node _T_4455 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 523:63] - node _T_4456 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:75] - node _T_4457 = and(_T_4455, _T_4456) @[lsu_bus_buffer.scala 523:73] - node _T_4458 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 523:63] - node _T_4459 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:75] - node _T_4460 = and(_T_4458, _T_4459) @[lsu_bus_buffer.scala 523:73] - node _T_4461 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 523:63] - node _T_4462 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:75] - node _T_4463 = and(_T_4461, _T_4462) @[lsu_bus_buffer.scala 523:73] - node _T_4464 = add(_T_4463, _T_4460) @[lsu_bus_buffer.scala 523:126] - node _T_4465 = add(_T_4464, _T_4457) @[lsu_bus_buffer.scala 523:126] - node _T_4466 = add(_T_4465, _T_4454) @[lsu_bus_buffer.scala 523:126] - buf_numvld_cmd_any <= _T_4466 @[lsu_bus_buffer.scala 523:22] - node _T_4467 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 524:63] - node _T_4468 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 524:90] - node _T_4469 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 524:102] - node _T_4470 = and(_T_4468, _T_4469) @[lsu_bus_buffer.scala 524:100] - node _T_4471 = or(_T_4467, _T_4470) @[lsu_bus_buffer.scala 524:74] - node _T_4472 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 524:63] - node _T_4473 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 524:90] - node _T_4474 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 524:102] - node _T_4475 = and(_T_4473, _T_4474) @[lsu_bus_buffer.scala 524:100] - node _T_4476 = or(_T_4472, _T_4475) @[lsu_bus_buffer.scala 524:74] - node _T_4477 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 524:63] - node _T_4478 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 524:90] - node _T_4479 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 524:102] - node _T_4480 = and(_T_4478, _T_4479) @[lsu_bus_buffer.scala 524:100] - node _T_4481 = or(_T_4477, _T_4480) @[lsu_bus_buffer.scala 524:74] - node _T_4482 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 524:63] - node _T_4483 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 524:90] - node _T_4484 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 524:102] - node _T_4485 = and(_T_4483, _T_4484) @[lsu_bus_buffer.scala 524:100] - node _T_4486 = or(_T_4482, _T_4485) @[lsu_bus_buffer.scala 524:74] - node _T_4487 = add(_T_4486, _T_4481) @[lsu_bus_buffer.scala 524:154] - node _T_4488 = add(_T_4487, _T_4476) @[lsu_bus_buffer.scala 524:154] - node _T_4489 = add(_T_4488, _T_4471) @[lsu_bus_buffer.scala 524:154] - buf_numvld_pend_any <= _T_4489 @[lsu_bus_buffer.scala 524:23] - node _T_4490 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 525:61] - node _T_4491 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 525:61] - node _T_4492 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 525:61] - node _T_4493 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 525:61] - node _T_4494 = or(_T_4493, _T_4492) @[lsu_bus_buffer.scala 525:93] - node _T_4495 = or(_T_4494, _T_4491) @[lsu_bus_buffer.scala 525:93] - node _T_4496 = or(_T_4495, _T_4490) @[lsu_bus_buffer.scala 525:93] - any_done_wait_state <= _T_4496 @[lsu_bus_buffer.scala 525:23] - node _T_4497 = orr(buf_numvld_pend_any) @[lsu_bus_buffer.scala 526:53] - io.lsu_bus_buffer_pend_any <= _T_4497 @[lsu_bus_buffer.scala 526:30] - node _T_4498 = and(io.ldst_dual_d, io.dec_lsu_valid_raw_d) @[lsu_bus_buffer.scala 527:52] - node _T_4499 = geq(buf_numvld_any, UInt<2>("h03")) @[lsu_bus_buffer.scala 527:92] - node _T_4500 = eq(buf_numvld_any, UInt<3>("h04")) @[lsu_bus_buffer.scala 527:121] - node _T_4501 = mux(_T_4498, _T_4499, _T_4500) @[lsu_bus_buffer.scala 527:36] - io.lsu_bus_buffer_full_any <= _T_4501 @[lsu_bus_buffer.scala 527:30] - node _T_4502 = orr(buf_state[0]) @[lsu_bus_buffer.scala 528:52] - node _T_4503 = orr(buf_state[1]) @[lsu_bus_buffer.scala 528:52] - node _T_4504 = orr(buf_state[2]) @[lsu_bus_buffer.scala 528:52] - node _T_4505 = orr(buf_state[3]) @[lsu_bus_buffer.scala 528:52] - node _T_4506 = or(_T_4502, _T_4503) @[lsu_bus_buffer.scala 528:65] - node _T_4507 = or(_T_4506, _T_4504) @[lsu_bus_buffer.scala 528:65] - node _T_4508 = or(_T_4507, _T_4505) @[lsu_bus_buffer.scala 528:65] - node _T_4509 = eq(_T_4508, UInt<1>("h00")) @[lsu_bus_buffer.scala 528:34] - node _T_4510 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 528:72] - node _T_4511 = and(_T_4509, _T_4510) @[lsu_bus_buffer.scala 528:70] - node _T_4512 = eq(obuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 528:86] - node _T_4513 = and(_T_4511, _T_4512) @[lsu_bus_buffer.scala 528:84] - io.lsu_bus_buffer_empty_any <= _T_4513 @[lsu_bus_buffer.scala 528:31] - node _T_4514 = and(io.lsu_busreq_m, io.lsu_pkt_m.valid) @[lsu_bus_buffer.scala 530:64] - node _T_4515 = and(_T_4514, io.lsu_pkt_m.bits.load) @[lsu_bus_buffer.scala 530:85] - node _T_4516 = eq(io.flush_m_up, UInt<1>("h00")) @[lsu_bus_buffer.scala 530:112] - node _T_4517 = and(_T_4515, _T_4516) @[lsu_bus_buffer.scala 530:110] - node _T_4518 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 530:129] - node _T_4519 = and(_T_4517, _T_4518) @[lsu_bus_buffer.scala 530:127] - io.dctl_busbuff.lsu_nonblock_load_valid_m <= _T_4519 @[lsu_bus_buffer.scala 530:45] - io.dctl_busbuff.lsu_nonblock_load_tag_m <= WrPtr0_m @[lsu_bus_buffer.scala 531:43] + node _T_4418 = mux(io.ldst_dual_r, _T_4417, io.lsu_busreq_r) @[lsu_bus_buffer.scala 520:94] + node _T_4419 = add(_T_4416, _T_4418) @[lsu_bus_buffer.scala 520:88] + node _T_4420 = add(_T_4419, ibuf_valid) @[lsu_bus_buffer.scala 520:154] + node _T_4421 = neq(buf_state[0], UInt<3>("h00")) @[lsu_bus_buffer.scala 520:190] + node _T_4422 = neq(buf_state[1], UInt<3>("h00")) @[lsu_bus_buffer.scala 520:190] + node _T_4423 = neq(buf_state[2], UInt<3>("h00")) @[lsu_bus_buffer.scala 520:190] + node _T_4424 = neq(buf_state[3], UInt<3>("h00")) @[lsu_bus_buffer.scala 520:190] + node _T_4425 = add(_T_4421, _T_4422) @[lsu_bus_buffer.scala 520:217] + node _T_4426 = add(_T_4425, _T_4423) @[lsu_bus_buffer.scala 520:217] + node _T_4427 = add(_T_4426, _T_4424) @[lsu_bus_buffer.scala 520:217] + node _T_4428 = add(_T_4420, _T_4427) @[lsu_bus_buffer.scala 520:169] + node buf_numvld_any = tail(_T_4428, 1) @[lsu_bus_buffer.scala 520:169] + node _T_4429 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 521:60] + node _T_4430 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 521:79] + node _T_4431 = and(_T_4429, _T_4430) @[lsu_bus_buffer.scala 521:64] + node _T_4432 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 521:91] + node _T_4433 = and(_T_4431, _T_4432) @[lsu_bus_buffer.scala 521:89] + node _T_4434 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 521:60] + node _T_4435 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 521:79] + node _T_4436 = and(_T_4434, _T_4435) @[lsu_bus_buffer.scala 521:64] + node _T_4437 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 521:91] + node _T_4438 = and(_T_4436, _T_4437) @[lsu_bus_buffer.scala 521:89] + node _T_4439 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 521:60] + node _T_4440 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 521:79] + node _T_4441 = and(_T_4439, _T_4440) @[lsu_bus_buffer.scala 521:64] + node _T_4442 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 521:91] + node _T_4443 = and(_T_4441, _T_4442) @[lsu_bus_buffer.scala 521:89] + node _T_4444 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 521:60] + node _T_4445 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 521:79] + node _T_4446 = and(_T_4444, _T_4445) @[lsu_bus_buffer.scala 521:64] + node _T_4447 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 521:91] + node _T_4448 = and(_T_4446, _T_4447) @[lsu_bus_buffer.scala 521:89] + node _T_4449 = add(_T_4448, _T_4443) @[lsu_bus_buffer.scala 521:142] + node _T_4450 = add(_T_4449, _T_4438) @[lsu_bus_buffer.scala 521:142] + node _T_4451 = add(_T_4450, _T_4433) @[lsu_bus_buffer.scala 521:142] + buf_numvld_wrcmd_any <= _T_4451 @[lsu_bus_buffer.scala 521:24] + node _T_4452 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 522:63] + node _T_4453 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 522:75] + node _T_4454 = and(_T_4452, _T_4453) @[lsu_bus_buffer.scala 522:73] + node _T_4455 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 522:63] + node _T_4456 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 522:75] + node _T_4457 = and(_T_4455, _T_4456) @[lsu_bus_buffer.scala 522:73] + node _T_4458 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 522:63] + node _T_4459 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 522:75] + node _T_4460 = and(_T_4458, _T_4459) @[lsu_bus_buffer.scala 522:73] + node _T_4461 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 522:63] + node _T_4462 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 522:75] + node _T_4463 = and(_T_4461, _T_4462) @[lsu_bus_buffer.scala 522:73] + node _T_4464 = add(_T_4463, _T_4460) @[lsu_bus_buffer.scala 522:126] + node _T_4465 = add(_T_4464, _T_4457) @[lsu_bus_buffer.scala 522:126] + node _T_4466 = add(_T_4465, _T_4454) @[lsu_bus_buffer.scala 522:126] + buf_numvld_cmd_any <= _T_4466 @[lsu_bus_buffer.scala 522:22] + node _T_4467 = eq(buf_state[0], UInt<3>("h01")) @[lsu_bus_buffer.scala 523:63] + node _T_4468 = eq(buf_state[0], UInt<3>("h02")) @[lsu_bus_buffer.scala 523:90] + node _T_4469 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:102] + node _T_4470 = and(_T_4468, _T_4469) @[lsu_bus_buffer.scala 523:100] + node _T_4471 = or(_T_4467, _T_4470) @[lsu_bus_buffer.scala 523:74] + node _T_4472 = eq(buf_state[1], UInt<3>("h01")) @[lsu_bus_buffer.scala 523:63] + node _T_4473 = eq(buf_state[1], UInt<3>("h02")) @[lsu_bus_buffer.scala 523:90] + node _T_4474 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:102] + node _T_4475 = and(_T_4473, _T_4474) @[lsu_bus_buffer.scala 523:100] + node _T_4476 = or(_T_4472, _T_4475) @[lsu_bus_buffer.scala 523:74] + node _T_4477 = eq(buf_state[2], UInt<3>("h01")) @[lsu_bus_buffer.scala 523:63] + node _T_4478 = eq(buf_state[2], UInt<3>("h02")) @[lsu_bus_buffer.scala 523:90] + node _T_4479 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:102] + node _T_4480 = and(_T_4478, _T_4479) @[lsu_bus_buffer.scala 523:100] + node _T_4481 = or(_T_4477, _T_4480) @[lsu_bus_buffer.scala 523:74] + node _T_4482 = eq(buf_state[3], UInt<3>("h01")) @[lsu_bus_buffer.scala 523:63] + node _T_4483 = eq(buf_state[3], UInt<3>("h02")) @[lsu_bus_buffer.scala 523:90] + node _T_4484 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:102] + node _T_4485 = and(_T_4483, _T_4484) @[lsu_bus_buffer.scala 523:100] + node _T_4486 = or(_T_4482, _T_4485) @[lsu_bus_buffer.scala 523:74] + node _T_4487 = add(_T_4486, _T_4481) @[lsu_bus_buffer.scala 523:154] + node _T_4488 = add(_T_4487, _T_4476) @[lsu_bus_buffer.scala 523:154] + node _T_4489 = add(_T_4488, _T_4471) @[lsu_bus_buffer.scala 523:154] + buf_numvld_pend_any <= _T_4489 @[lsu_bus_buffer.scala 523:23] + node _T_4490 = eq(buf_state[0], UInt<3>("h05")) @[lsu_bus_buffer.scala 524:61] + node _T_4491 = eq(buf_state[1], UInt<3>("h05")) @[lsu_bus_buffer.scala 524:61] + node _T_4492 = eq(buf_state[2], UInt<3>("h05")) @[lsu_bus_buffer.scala 524:61] + node _T_4493 = eq(buf_state[3], UInt<3>("h05")) @[lsu_bus_buffer.scala 524:61] + node _T_4494 = or(_T_4493, _T_4492) @[lsu_bus_buffer.scala 524:93] + node _T_4495 = or(_T_4494, _T_4491) @[lsu_bus_buffer.scala 524:93] + node _T_4496 = or(_T_4495, _T_4490) @[lsu_bus_buffer.scala 524:93] + any_done_wait_state <= _T_4496 @[lsu_bus_buffer.scala 524:23] + node _T_4497 = orr(buf_numvld_pend_any) @[lsu_bus_buffer.scala 525:53] + io.lsu_bus_buffer_pend_any <= _T_4497 @[lsu_bus_buffer.scala 525:30] + node _T_4498 = and(io.ldst_dual_d, io.dec_lsu_valid_raw_d) @[lsu_bus_buffer.scala 526:52] + node _T_4499 = geq(buf_numvld_any, UInt<2>("h03")) @[lsu_bus_buffer.scala 526:92] + node _T_4500 = eq(buf_numvld_any, UInt<3>("h04")) @[lsu_bus_buffer.scala 526:121] + node _T_4501 = mux(_T_4498, _T_4499, _T_4500) @[lsu_bus_buffer.scala 526:36] + io.lsu_bus_buffer_full_any <= _T_4501 @[lsu_bus_buffer.scala 526:30] + node _T_4502 = orr(buf_state[0]) @[lsu_bus_buffer.scala 527:52] + node _T_4503 = orr(buf_state[1]) @[lsu_bus_buffer.scala 527:52] + node _T_4504 = orr(buf_state[2]) @[lsu_bus_buffer.scala 527:52] + node _T_4505 = orr(buf_state[3]) @[lsu_bus_buffer.scala 527:52] + node _T_4506 = or(_T_4502, _T_4503) @[lsu_bus_buffer.scala 527:65] + node _T_4507 = or(_T_4506, _T_4504) @[lsu_bus_buffer.scala 527:65] + node _T_4508 = or(_T_4507, _T_4505) @[lsu_bus_buffer.scala 527:65] + node _T_4509 = eq(_T_4508, UInt<1>("h00")) @[lsu_bus_buffer.scala 527:34] + node _T_4510 = eq(ibuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 527:72] + node _T_4511 = and(_T_4509, _T_4510) @[lsu_bus_buffer.scala 527:70] + node _T_4512 = eq(obuf_valid, UInt<1>("h00")) @[lsu_bus_buffer.scala 527:86] + node _T_4513 = and(_T_4511, _T_4512) @[lsu_bus_buffer.scala 527:84] + io.lsu_bus_buffer_empty_any <= _T_4513 @[lsu_bus_buffer.scala 527:31] + node _T_4514 = and(io.lsu_busreq_m, io.lsu_pkt_m.valid) @[lsu_bus_buffer.scala 529:64] + node _T_4515 = and(_T_4514, io.lsu_pkt_m.bits.load) @[lsu_bus_buffer.scala 529:85] + node _T_4516 = eq(io.flush_m_up, UInt<1>("h00")) @[lsu_bus_buffer.scala 529:112] + node _T_4517 = and(_T_4515, _T_4516) @[lsu_bus_buffer.scala 529:110] + node _T_4518 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 529:129] + node _T_4519 = and(_T_4517, _T_4518) @[lsu_bus_buffer.scala 529:127] + io.dctl_busbuff.lsu_nonblock_load_valid_m <= _T_4519 @[lsu_bus_buffer.scala 529:45] + io.dctl_busbuff.lsu_nonblock_load_tag_m <= WrPtr0_m @[lsu_bus_buffer.scala 530:43] wire lsu_nonblock_load_valid_r : UInt<1> lsu_nonblock_load_valid_r <= UInt<1>("h00") - node _T_4520 = eq(io.lsu_commit_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 533:74] - node _T_4521 = and(lsu_nonblock_load_valid_r, _T_4520) @[lsu_bus_buffer.scala 533:72] - io.dctl_busbuff.lsu_nonblock_load_inv_r <= _T_4521 @[lsu_bus_buffer.scala 533:43] - io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= WrPtr0_r @[lsu_bus_buffer.scala 534:47] - node _T_4522 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 535:80] - node _T_4523 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 535:127] - node _T_4524 = and(UInt<1>("h01"), _T_4523) @[lsu_bus_buffer.scala 535:116] - node _T_4525 = eq(_T_4524, UInt<1>("h00")) @[lsu_bus_buffer.scala 535:95] - node _T_4526 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 535:80] - node _T_4527 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 535:127] - node _T_4528 = and(UInt<1>("h01"), _T_4527) @[lsu_bus_buffer.scala 535:116] - node _T_4529 = eq(_T_4528, UInt<1>("h00")) @[lsu_bus_buffer.scala 535:95] - node _T_4530 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 535:80] - node _T_4531 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 535:127] - node _T_4532 = and(UInt<1>("h01"), _T_4531) @[lsu_bus_buffer.scala 535:116] - node _T_4533 = eq(_T_4532, UInt<1>("h00")) @[lsu_bus_buffer.scala 535:95] - node _T_4534 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 535:80] - node _T_4535 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 535:127] - node _T_4536 = and(UInt<1>("h01"), _T_4535) @[lsu_bus_buffer.scala 535:116] - node _T_4537 = eq(_T_4536, UInt<1>("h00")) @[lsu_bus_buffer.scala 535:95] + node _T_4520 = eq(io.lsu_commit_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 532:74] + node _T_4521 = and(lsu_nonblock_load_valid_r, _T_4520) @[lsu_bus_buffer.scala 532:72] + io.dctl_busbuff.lsu_nonblock_load_inv_r <= _T_4521 @[lsu_bus_buffer.scala 532:43] + io.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= WrPtr0_r @[lsu_bus_buffer.scala 533:47] + node _T_4522 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 534:80] + node _T_4523 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 534:127] + node _T_4524 = and(UInt<1>("h01"), _T_4523) @[lsu_bus_buffer.scala 534:116] + node _T_4525 = eq(_T_4524, UInt<1>("h00")) @[lsu_bus_buffer.scala 534:95] + node _T_4526 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 534:80] + node _T_4527 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 534:127] + node _T_4528 = and(UInt<1>("h01"), _T_4527) @[lsu_bus_buffer.scala 534:116] + node _T_4529 = eq(_T_4528, UInt<1>("h00")) @[lsu_bus_buffer.scala 534:95] + node _T_4530 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 534:80] + node _T_4531 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 534:127] + node _T_4532 = and(UInt<1>("h01"), _T_4531) @[lsu_bus_buffer.scala 534:116] + node _T_4533 = eq(_T_4532, UInt<1>("h00")) @[lsu_bus_buffer.scala 534:95] + node _T_4534 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 534:80] + node _T_4535 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 534:127] + node _T_4536 = and(UInt<1>("h01"), _T_4535) @[lsu_bus_buffer.scala 534:116] + node _T_4537 = eq(_T_4536, UInt<1>("h00")) @[lsu_bus_buffer.scala 534:95] node _T_4538 = mux(_T_4522, _T_4525, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4539 = mux(_T_4526, _T_4529, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4540 = mux(_T_4530, _T_4533, UInt<1>("h00")) @[Mux.scala 27:72] @@ -100575,26 +100572,26 @@ circuit quasar_wrapper : node _T_4544 = or(_T_4543, _T_4541) @[Mux.scala 27:72] wire lsu_nonblock_load_data_ready : UInt<1> @[Mux.scala 27:72] lsu_nonblock_load_data_ready <= _T_4544 @[Mux.scala 27:72] - node _T_4545 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 536:93] - node _T_4546 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 536:117] - node _T_4547 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 536:133] - node _T_4548 = eq(_T_4547, UInt<1>("h00")) @[lsu_bus_buffer.scala 536:123] - node _T_4549 = and(_T_4546, _T_4548) @[lsu_bus_buffer.scala 536:121] - node _T_4550 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 536:93] - node _T_4551 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 536:117] - node _T_4552 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 536:133] - node _T_4553 = eq(_T_4552, UInt<1>("h00")) @[lsu_bus_buffer.scala 536:123] - node _T_4554 = and(_T_4551, _T_4553) @[lsu_bus_buffer.scala 536:121] - node _T_4555 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 536:93] - node _T_4556 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 536:117] - node _T_4557 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 536:133] - node _T_4558 = eq(_T_4557, UInt<1>("h00")) @[lsu_bus_buffer.scala 536:123] - node _T_4559 = and(_T_4556, _T_4558) @[lsu_bus_buffer.scala 536:121] - node _T_4560 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 536:93] - node _T_4561 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 536:117] - node _T_4562 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 536:133] - node _T_4563 = eq(_T_4562, UInt<1>("h00")) @[lsu_bus_buffer.scala 536:123] - node _T_4564 = and(_T_4561, _T_4563) @[lsu_bus_buffer.scala 536:121] + node _T_4545 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 535:93] + node _T_4546 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 535:117] + node _T_4547 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 535:133] + node _T_4548 = eq(_T_4547, UInt<1>("h00")) @[lsu_bus_buffer.scala 535:123] + node _T_4549 = and(_T_4546, _T_4548) @[lsu_bus_buffer.scala 535:121] + node _T_4550 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 535:93] + node _T_4551 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 535:117] + node _T_4552 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 535:133] + node _T_4553 = eq(_T_4552, UInt<1>("h00")) @[lsu_bus_buffer.scala 535:123] + node _T_4554 = and(_T_4551, _T_4553) @[lsu_bus_buffer.scala 535:121] + node _T_4555 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 535:93] + node _T_4556 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 535:117] + node _T_4557 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 535:133] + node _T_4558 = eq(_T_4557, UInt<1>("h00")) @[lsu_bus_buffer.scala 535:123] + node _T_4559 = and(_T_4556, _T_4558) @[lsu_bus_buffer.scala 535:121] + node _T_4560 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 535:93] + node _T_4561 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 535:117] + node _T_4562 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 535:133] + node _T_4563 = eq(_T_4562, UInt<1>("h00")) @[lsu_bus_buffer.scala 535:123] + node _T_4564 = and(_T_4561, _T_4563) @[lsu_bus_buffer.scala 535:121] node _T_4565 = mux(_T_4545, _T_4549, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4566 = mux(_T_4550, _T_4554, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4567 = mux(_T_4555, _T_4559, UInt<1>("h00")) @[Mux.scala 27:72] @@ -100604,39 +100601,39 @@ circuit quasar_wrapper : node _T_4571 = or(_T_4570, _T_4568) @[Mux.scala 27:72] wire _T_4572 : UInt<1> @[Mux.scala 27:72] _T_4572 <= _T_4571 @[Mux.scala 27:72] - io.dctl_busbuff.lsu_nonblock_load_data_error <= _T_4572 @[lsu_bus_buffer.scala 536:48] - node _T_4573 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 537:92] - node _T_4574 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 537:115] - node _T_4575 = eq(_T_4574, UInt<1>("h00")) @[lsu_bus_buffer.scala 537:105] - node _T_4576 = and(_T_4573, _T_4575) @[lsu_bus_buffer.scala 537:103] - node _T_4577 = eq(buf_dual[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:122] - node _T_4578 = eq(buf_dualhi[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:137] - node _T_4579 = or(_T_4577, _T_4578) @[lsu_bus_buffer.scala 537:135] - node _T_4580 = and(_T_4576, _T_4579) @[lsu_bus_buffer.scala 537:119] - node _T_4581 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 537:92] - node _T_4582 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 537:115] - node _T_4583 = eq(_T_4582, UInt<1>("h00")) @[lsu_bus_buffer.scala 537:105] - node _T_4584 = and(_T_4581, _T_4583) @[lsu_bus_buffer.scala 537:103] - node _T_4585 = eq(buf_dual[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:122] - node _T_4586 = eq(buf_dualhi[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:137] - node _T_4587 = or(_T_4585, _T_4586) @[lsu_bus_buffer.scala 537:135] - node _T_4588 = and(_T_4584, _T_4587) @[lsu_bus_buffer.scala 537:119] - node _T_4589 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 537:92] - node _T_4590 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 537:115] - node _T_4591 = eq(_T_4590, UInt<1>("h00")) @[lsu_bus_buffer.scala 537:105] - node _T_4592 = and(_T_4589, _T_4591) @[lsu_bus_buffer.scala 537:103] - node _T_4593 = eq(buf_dual[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:122] - node _T_4594 = eq(buf_dualhi[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:137] - node _T_4595 = or(_T_4593, _T_4594) @[lsu_bus_buffer.scala 537:135] - node _T_4596 = and(_T_4592, _T_4595) @[lsu_bus_buffer.scala 537:119] - node _T_4597 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 537:92] - node _T_4598 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 537:115] - node _T_4599 = eq(_T_4598, UInt<1>("h00")) @[lsu_bus_buffer.scala 537:105] - node _T_4600 = and(_T_4597, _T_4599) @[lsu_bus_buffer.scala 537:103] - node _T_4601 = eq(buf_dual[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:122] - node _T_4602 = eq(buf_dualhi[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:137] - node _T_4603 = or(_T_4601, _T_4602) @[lsu_bus_buffer.scala 537:135] - node _T_4604 = and(_T_4600, _T_4603) @[lsu_bus_buffer.scala 537:119] + io.dctl_busbuff.lsu_nonblock_load_data_error <= _T_4572 @[lsu_bus_buffer.scala 535:48] + node _T_4573 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 536:92] + node _T_4574 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 536:115] + node _T_4575 = eq(_T_4574, UInt<1>("h00")) @[lsu_bus_buffer.scala 536:105] + node _T_4576 = and(_T_4573, _T_4575) @[lsu_bus_buffer.scala 536:103] + node _T_4577 = eq(buf_dual[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 536:122] + node _T_4578 = eq(buf_dualhi[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 536:137] + node _T_4579 = or(_T_4577, _T_4578) @[lsu_bus_buffer.scala 536:135] + node _T_4580 = and(_T_4576, _T_4579) @[lsu_bus_buffer.scala 536:119] + node _T_4581 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 536:92] + node _T_4582 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 536:115] + node _T_4583 = eq(_T_4582, UInt<1>("h00")) @[lsu_bus_buffer.scala 536:105] + node _T_4584 = and(_T_4581, _T_4583) @[lsu_bus_buffer.scala 536:103] + node _T_4585 = eq(buf_dual[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 536:122] + node _T_4586 = eq(buf_dualhi[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 536:137] + node _T_4587 = or(_T_4585, _T_4586) @[lsu_bus_buffer.scala 536:135] + node _T_4588 = and(_T_4584, _T_4587) @[lsu_bus_buffer.scala 536:119] + node _T_4589 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 536:92] + node _T_4590 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 536:115] + node _T_4591 = eq(_T_4590, UInt<1>("h00")) @[lsu_bus_buffer.scala 536:105] + node _T_4592 = and(_T_4589, _T_4591) @[lsu_bus_buffer.scala 536:103] + node _T_4593 = eq(buf_dual[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 536:122] + node _T_4594 = eq(buf_dualhi[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 536:137] + node _T_4595 = or(_T_4593, _T_4594) @[lsu_bus_buffer.scala 536:135] + node _T_4596 = and(_T_4592, _T_4595) @[lsu_bus_buffer.scala 536:119] + node _T_4597 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 536:92] + node _T_4598 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 536:115] + node _T_4599 = eq(_T_4598, UInt<1>("h00")) @[lsu_bus_buffer.scala 536:105] + node _T_4600 = and(_T_4597, _T_4599) @[lsu_bus_buffer.scala 536:103] + node _T_4601 = eq(buf_dual[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 536:122] + node _T_4602 = eq(buf_dualhi[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 536:137] + node _T_4603 = or(_T_4601, _T_4602) @[lsu_bus_buffer.scala 536:135] + node _T_4604 = and(_T_4600, _T_4603) @[lsu_bus_buffer.scala 536:119] node _T_4605 = mux(_T_4580, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_4606 = mux(_T_4588, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_4607 = mux(_T_4596, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -100646,39 +100643,39 @@ circuit quasar_wrapper : node _T_4611 = or(_T_4610, _T_4608) @[Mux.scala 27:72] wire _T_4612 : UInt<2> @[Mux.scala 27:72] _T_4612 <= _T_4611 @[Mux.scala 27:72] - io.dctl_busbuff.lsu_nonblock_load_data_tag <= _T_4612 @[lsu_bus_buffer.scala 537:46] - node _T_4613 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 538:78] - node _T_4614 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 538:101] - node _T_4615 = eq(_T_4614, UInt<1>("h00")) @[lsu_bus_buffer.scala 538:91] - node _T_4616 = and(_T_4613, _T_4615) @[lsu_bus_buffer.scala 538:89] - node _T_4617 = eq(buf_dual[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 538:108] - node _T_4618 = eq(buf_dualhi[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 538:123] - node _T_4619 = or(_T_4617, _T_4618) @[lsu_bus_buffer.scala 538:121] - node _T_4620 = and(_T_4616, _T_4619) @[lsu_bus_buffer.scala 538:105] - node _T_4621 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 538:78] - node _T_4622 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 538:101] - node _T_4623 = eq(_T_4622, UInt<1>("h00")) @[lsu_bus_buffer.scala 538:91] - node _T_4624 = and(_T_4621, _T_4623) @[lsu_bus_buffer.scala 538:89] - node _T_4625 = eq(buf_dual[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 538:108] - node _T_4626 = eq(buf_dualhi[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 538:123] - node _T_4627 = or(_T_4625, _T_4626) @[lsu_bus_buffer.scala 538:121] - node _T_4628 = and(_T_4624, _T_4627) @[lsu_bus_buffer.scala 538:105] - node _T_4629 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 538:78] - node _T_4630 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 538:101] - node _T_4631 = eq(_T_4630, UInt<1>("h00")) @[lsu_bus_buffer.scala 538:91] - node _T_4632 = and(_T_4629, _T_4631) @[lsu_bus_buffer.scala 538:89] - node _T_4633 = eq(buf_dual[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 538:108] - node _T_4634 = eq(buf_dualhi[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 538:123] - node _T_4635 = or(_T_4633, _T_4634) @[lsu_bus_buffer.scala 538:121] - node _T_4636 = and(_T_4632, _T_4635) @[lsu_bus_buffer.scala 538:105] - node _T_4637 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 538:78] - node _T_4638 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 538:101] - node _T_4639 = eq(_T_4638, UInt<1>("h00")) @[lsu_bus_buffer.scala 538:91] - node _T_4640 = and(_T_4637, _T_4639) @[lsu_bus_buffer.scala 538:89] - node _T_4641 = eq(buf_dual[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 538:108] - node _T_4642 = eq(buf_dualhi[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 538:123] - node _T_4643 = or(_T_4641, _T_4642) @[lsu_bus_buffer.scala 538:121] - node _T_4644 = and(_T_4640, _T_4643) @[lsu_bus_buffer.scala 538:105] + io.dctl_busbuff.lsu_nonblock_load_data_tag <= _T_4612 @[lsu_bus_buffer.scala 536:46] + node _T_4613 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 537:78] + node _T_4614 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 537:101] + node _T_4615 = eq(_T_4614, UInt<1>("h00")) @[lsu_bus_buffer.scala 537:91] + node _T_4616 = and(_T_4613, _T_4615) @[lsu_bus_buffer.scala 537:89] + node _T_4617 = eq(buf_dual[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:108] + node _T_4618 = eq(buf_dualhi[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:123] + node _T_4619 = or(_T_4617, _T_4618) @[lsu_bus_buffer.scala 537:121] + node _T_4620 = and(_T_4616, _T_4619) @[lsu_bus_buffer.scala 537:105] + node _T_4621 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 537:78] + node _T_4622 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 537:101] + node _T_4623 = eq(_T_4622, UInt<1>("h00")) @[lsu_bus_buffer.scala 537:91] + node _T_4624 = and(_T_4621, _T_4623) @[lsu_bus_buffer.scala 537:89] + node _T_4625 = eq(buf_dual[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:108] + node _T_4626 = eq(buf_dualhi[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:123] + node _T_4627 = or(_T_4625, _T_4626) @[lsu_bus_buffer.scala 537:121] + node _T_4628 = and(_T_4624, _T_4627) @[lsu_bus_buffer.scala 537:105] + node _T_4629 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 537:78] + node _T_4630 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 537:101] + node _T_4631 = eq(_T_4630, UInt<1>("h00")) @[lsu_bus_buffer.scala 537:91] + node _T_4632 = and(_T_4629, _T_4631) @[lsu_bus_buffer.scala 537:89] + node _T_4633 = eq(buf_dual[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:108] + node _T_4634 = eq(buf_dualhi[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:123] + node _T_4635 = or(_T_4633, _T_4634) @[lsu_bus_buffer.scala 537:121] + node _T_4636 = and(_T_4632, _T_4635) @[lsu_bus_buffer.scala 537:105] + node _T_4637 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 537:78] + node _T_4638 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 537:101] + node _T_4639 = eq(_T_4638, UInt<1>("h00")) @[lsu_bus_buffer.scala 537:91] + node _T_4640 = and(_T_4637, _T_4639) @[lsu_bus_buffer.scala 537:89] + node _T_4641 = eq(buf_dual[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:108] + node _T_4642 = eq(buf_dualhi[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 537:123] + node _T_4643 = or(_T_4641, _T_4642) @[lsu_bus_buffer.scala 537:121] + node _T_4644 = and(_T_4640, _T_4643) @[lsu_bus_buffer.scala 537:105] node _T_4645 = mux(_T_4620, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_4646 = mux(_T_4628, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_4647 = mux(_T_4636, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -100688,30 +100685,30 @@ circuit quasar_wrapper : node _T_4651 = or(_T_4650, _T_4648) @[Mux.scala 27:72] wire lsu_nonblock_load_data_lo : UInt<32> @[Mux.scala 27:72] lsu_nonblock_load_data_lo <= _T_4651 @[Mux.scala 27:72] - node _T_4652 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 539:78] - node _T_4653 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 539:101] - node _T_4654 = eq(_T_4653, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:91] - node _T_4655 = and(_T_4652, _T_4654) @[lsu_bus_buffer.scala 539:89] - node _T_4656 = and(buf_dual[0], buf_dualhi[0]) @[lsu_bus_buffer.scala 539:120] - node _T_4657 = and(_T_4655, _T_4656) @[lsu_bus_buffer.scala 539:105] - node _T_4658 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 539:78] - node _T_4659 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 539:101] - node _T_4660 = eq(_T_4659, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:91] - node _T_4661 = and(_T_4658, _T_4660) @[lsu_bus_buffer.scala 539:89] - node _T_4662 = and(buf_dual[1], buf_dualhi[1]) @[lsu_bus_buffer.scala 539:120] - node _T_4663 = and(_T_4661, _T_4662) @[lsu_bus_buffer.scala 539:105] - node _T_4664 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 539:78] - node _T_4665 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 539:101] - node _T_4666 = eq(_T_4665, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:91] - node _T_4667 = and(_T_4664, _T_4666) @[lsu_bus_buffer.scala 539:89] - node _T_4668 = and(buf_dual[2], buf_dualhi[2]) @[lsu_bus_buffer.scala 539:120] - node _T_4669 = and(_T_4667, _T_4668) @[lsu_bus_buffer.scala 539:105] - node _T_4670 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 539:78] - node _T_4671 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 539:101] - node _T_4672 = eq(_T_4671, UInt<1>("h00")) @[lsu_bus_buffer.scala 539:91] - node _T_4673 = and(_T_4670, _T_4672) @[lsu_bus_buffer.scala 539:89] - node _T_4674 = and(buf_dual[3], buf_dualhi[3]) @[lsu_bus_buffer.scala 539:120] - node _T_4675 = and(_T_4673, _T_4674) @[lsu_bus_buffer.scala 539:105] + node _T_4652 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 538:78] + node _T_4653 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 538:101] + node _T_4654 = eq(_T_4653, UInt<1>("h00")) @[lsu_bus_buffer.scala 538:91] + node _T_4655 = and(_T_4652, _T_4654) @[lsu_bus_buffer.scala 538:89] + node _T_4656 = and(buf_dual[0], buf_dualhi[0]) @[lsu_bus_buffer.scala 538:120] + node _T_4657 = and(_T_4655, _T_4656) @[lsu_bus_buffer.scala 538:105] + node _T_4658 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 538:78] + node _T_4659 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 538:101] + node _T_4660 = eq(_T_4659, UInt<1>("h00")) @[lsu_bus_buffer.scala 538:91] + node _T_4661 = and(_T_4658, _T_4660) @[lsu_bus_buffer.scala 538:89] + node _T_4662 = and(buf_dual[1], buf_dualhi[1]) @[lsu_bus_buffer.scala 538:120] + node _T_4663 = and(_T_4661, _T_4662) @[lsu_bus_buffer.scala 538:105] + node _T_4664 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 538:78] + node _T_4665 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 538:101] + node _T_4666 = eq(_T_4665, UInt<1>("h00")) @[lsu_bus_buffer.scala 538:91] + node _T_4667 = and(_T_4664, _T_4666) @[lsu_bus_buffer.scala 538:89] + node _T_4668 = and(buf_dual[2], buf_dualhi[2]) @[lsu_bus_buffer.scala 538:120] + node _T_4669 = and(_T_4667, _T_4668) @[lsu_bus_buffer.scala 538:105] + node _T_4670 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 538:78] + node _T_4671 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 538:101] + node _T_4672 = eq(_T_4671, UInt<1>("h00")) @[lsu_bus_buffer.scala 538:91] + node _T_4673 = and(_T_4670, _T_4672) @[lsu_bus_buffer.scala 538:89] + node _T_4674 = and(buf_dual[3], buf_dualhi[3]) @[lsu_bus_buffer.scala 538:120] + node _T_4675 = and(_T_4673, _T_4674) @[lsu_bus_buffer.scala 538:105] node _T_4676 = mux(_T_4657, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_4677 = mux(_T_4663, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_4678 = mux(_T_4669, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] @@ -100734,7 +100731,7 @@ circuit quasar_wrapper : node _T_4693 = or(_T_4692, _T_4690) @[Mux.scala 27:72] wire _T_4694 : UInt<32> @[Mux.scala 27:72] _T_4694 <= _T_4693 @[Mux.scala 27:72] - node lsu_nonblock_addr_offset = bits(_T_4694, 1, 0) @[lsu_bus_buffer.scala 540:96] + node lsu_nonblock_addr_offset = bits(_T_4694, 1, 0) @[lsu_bus_buffer.scala 539:96] node _T_4695 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[lsu_bus_buffer.scala 58:123] node _T_4696 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[lsu_bus_buffer.scala 58:123] node _T_4697 = eq(io.dctl_busbuff.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[lsu_bus_buffer.scala 58:123] @@ -100786,36 +100783,36 @@ circuit quasar_wrapper : wire lsu_nonblock_dual : UInt<1> @[Mux.scala 27:72] lsu_nonblock_dual <= _T_4738 @[Mux.scala 27:72] node _T_4739 = cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) @[Cat.scala 29:58] - node _T_4740 = mul(lsu_nonblock_addr_offset, UInt<4>("h08")) @[lsu_bus_buffer.scala 544:121] - node lsu_nonblock_data_unalgn = dshr(_T_4739, _T_4740) @[lsu_bus_buffer.scala 544:92] - node _T_4741 = eq(io.dctl_busbuff.lsu_nonblock_load_data_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:82] - node _T_4742 = and(lsu_nonblock_load_data_ready, _T_4741) @[lsu_bus_buffer.scala 546:80] - io.dctl_busbuff.lsu_nonblock_load_data_valid <= _T_4742 @[lsu_bus_buffer.scala 546:48] - node _T_4743 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[lsu_bus_buffer.scala 547:94] - node _T_4744 = and(lsu_nonblock_unsign, _T_4743) @[lsu_bus_buffer.scala 547:76] - node _T_4745 = bits(lsu_nonblock_data_unalgn, 7, 0) @[lsu_bus_buffer.scala 547:144] + node _T_4740 = mul(lsu_nonblock_addr_offset, UInt<4>("h08")) @[lsu_bus_buffer.scala 543:121] + node lsu_nonblock_data_unalgn = dshr(_T_4739, _T_4740) @[lsu_bus_buffer.scala 543:92] + node _T_4741 = eq(io.dctl_busbuff.lsu_nonblock_load_data_error, UInt<1>("h00")) @[lsu_bus_buffer.scala 545:82] + node _T_4742 = and(lsu_nonblock_load_data_ready, _T_4741) @[lsu_bus_buffer.scala 545:80] + io.dctl_busbuff.lsu_nonblock_load_data_valid <= _T_4742 @[lsu_bus_buffer.scala 545:48] + node _T_4743 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[lsu_bus_buffer.scala 546:94] + node _T_4744 = and(lsu_nonblock_unsign, _T_4743) @[lsu_bus_buffer.scala 546:76] + node _T_4745 = bits(lsu_nonblock_data_unalgn, 7, 0) @[lsu_bus_buffer.scala 546:144] node _T_4746 = cat(UInt<24>("h00"), _T_4745) @[Cat.scala 29:58] - node _T_4747 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[lsu_bus_buffer.scala 548:45] - node _T_4748 = and(lsu_nonblock_unsign, _T_4747) @[lsu_bus_buffer.scala 548:26] - node _T_4749 = bits(lsu_nonblock_data_unalgn, 15, 0) @[lsu_bus_buffer.scala 548:95] + node _T_4747 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[lsu_bus_buffer.scala 547:45] + node _T_4748 = and(lsu_nonblock_unsign, _T_4747) @[lsu_bus_buffer.scala 547:26] + node _T_4749 = bits(lsu_nonblock_data_unalgn, 15, 0) @[lsu_bus_buffer.scala 547:95] node _T_4750 = cat(UInt<16>("h00"), _T_4749) @[Cat.scala 29:58] - node _T_4751 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:6] - node _T_4752 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:45] - node _T_4753 = and(_T_4751, _T_4752) @[lsu_bus_buffer.scala 549:27] - node _T_4754 = bits(lsu_nonblock_data_unalgn, 7, 7) @[lsu_bus_buffer.scala 549:93] + node _T_4751 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:6] + node _T_4752 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[lsu_bus_buffer.scala 548:45] + node _T_4753 = and(_T_4751, _T_4752) @[lsu_bus_buffer.scala 548:27] + node _T_4754 = bits(lsu_nonblock_data_unalgn, 7, 7) @[lsu_bus_buffer.scala 548:93] node _T_4755 = bits(_T_4754, 0, 0) @[Bitwise.scala 72:15] node _T_4756 = mux(_T_4755, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] - node _T_4757 = bits(lsu_nonblock_data_unalgn, 7, 0) @[lsu_bus_buffer.scala 549:123] + node _T_4757 = bits(lsu_nonblock_data_unalgn, 7, 0) @[lsu_bus_buffer.scala 548:123] node _T_4758 = cat(_T_4756, _T_4757) @[Cat.scala 29:58] - node _T_4759 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[lsu_bus_buffer.scala 550:6] - node _T_4760 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[lsu_bus_buffer.scala 550:45] - node _T_4761 = and(_T_4759, _T_4760) @[lsu_bus_buffer.scala 550:27] - node _T_4762 = bits(lsu_nonblock_data_unalgn, 15, 15) @[lsu_bus_buffer.scala 550:93] + node _T_4759 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[lsu_bus_buffer.scala 549:6] + node _T_4760 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[lsu_bus_buffer.scala 549:45] + node _T_4761 = and(_T_4759, _T_4760) @[lsu_bus_buffer.scala 549:27] + node _T_4762 = bits(lsu_nonblock_data_unalgn, 15, 15) @[lsu_bus_buffer.scala 549:93] node _T_4763 = bits(_T_4762, 0, 0) @[Bitwise.scala 72:15] node _T_4764 = mux(_T_4763, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] - node _T_4765 = bits(lsu_nonblock_data_unalgn, 15, 0) @[lsu_bus_buffer.scala 550:124] + node _T_4765 = bits(lsu_nonblock_data_unalgn, 15, 0) @[lsu_bus_buffer.scala 549:124] node _T_4766 = cat(_T_4764, _T_4765) @[Cat.scala 29:58] - node _T_4767 = eq(lsu_nonblock_sz, UInt<2>("h02")) @[lsu_bus_buffer.scala 551:21] + node _T_4767 = eq(lsu_nonblock_sz, UInt<2>("h02")) @[lsu_bus_buffer.scala 550:21] node _T_4768 = mux(_T_4744, _T_4746, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4769 = mux(_T_4748, _T_4750, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4770 = mux(_T_4753, _T_4758, UInt<1>("h00")) @[Mux.scala 27:72] @@ -100827,75 +100824,75 @@ circuit quasar_wrapper : node _T_4776 = or(_T_4775, _T_4772) @[Mux.scala 27:72] wire _T_4777 : UInt<64> @[Mux.scala 27:72] _T_4777 <= _T_4776 @[Mux.scala 27:72] - io.dctl_busbuff.lsu_nonblock_load_data <= _T_4777 @[lsu_bus_buffer.scala 547:42] - node _T_4778 = eq(buf_state[0], UInt<3>("h03")) @[lsu_bus_buffer.scala 552:62] - node _T_4779 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 552:89] - node _T_4780 = and(_T_4778, _T_4779) @[lsu_bus_buffer.scala 552:73] - node _T_4781 = and(_T_4780, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 552:93] - node _T_4782 = eq(buf_state[1], UInt<3>("h03")) @[lsu_bus_buffer.scala 552:62] - node _T_4783 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 552:89] - node _T_4784 = and(_T_4782, _T_4783) @[lsu_bus_buffer.scala 552:73] - node _T_4785 = and(_T_4784, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 552:93] - node _T_4786 = eq(buf_state[2], UInt<3>("h03")) @[lsu_bus_buffer.scala 552:62] - node _T_4787 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 552:89] - node _T_4788 = and(_T_4786, _T_4787) @[lsu_bus_buffer.scala 552:73] - node _T_4789 = and(_T_4788, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 552:93] - node _T_4790 = eq(buf_state[3], UInt<3>("h03")) @[lsu_bus_buffer.scala 552:62] - node _T_4791 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 552:89] - node _T_4792 = and(_T_4790, _T_4791) @[lsu_bus_buffer.scala 552:73] - node _T_4793 = and(_T_4792, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 552:93] - node _T_4794 = or(_T_4781, _T_4785) @[lsu_bus_buffer.scala 552:153] - node _T_4795 = or(_T_4794, _T_4789) @[lsu_bus_buffer.scala 552:153] - node _T_4796 = or(_T_4795, _T_4793) @[lsu_bus_buffer.scala 552:153] - bus_sideeffect_pend <= _T_4796 @[lsu_bus_buffer.scala 552:23] - node _T_4797 = eq(buf_state[0], UInt<3>("h03")) @[lsu_bus_buffer.scala 553:71] - node _T_4798 = and(UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 554:25] - node _T_4799 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 554:50] - node _T_4800 = bits(buf_addr[0], 31, 3) @[lsu_bus_buffer.scala 554:70] - node _T_4801 = eq(_T_4799, _T_4800) @[lsu_bus_buffer.scala 554:56] - node _T_4802 = and(_T_4798, _T_4801) @[lsu_bus_buffer.scala 554:38] - node _T_4803 = eq(obuf_tag0, UInt<1>("h00")) @[lsu_bus_buffer.scala 554:92] - node _T_4804 = eq(obuf_tag1, UInt<1>("h00")) @[lsu_bus_buffer.scala 554:126] - node _T_4805 = and(obuf_merge, _T_4804) @[lsu_bus_buffer.scala 554:114] - node _T_4806 = or(_T_4803, _T_4805) @[lsu_bus_buffer.scala 554:100] - node _T_4807 = eq(_T_4806, UInt<1>("h00")) @[lsu_bus_buffer.scala 554:80] - node _T_4808 = and(_T_4802, _T_4807) @[lsu_bus_buffer.scala 554:78] - node _T_4809 = eq(buf_state[1], UInt<3>("h03")) @[lsu_bus_buffer.scala 553:71] - node _T_4810 = and(UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 554:25] - node _T_4811 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 554:50] - node _T_4812 = bits(buf_addr[1], 31, 3) @[lsu_bus_buffer.scala 554:70] - node _T_4813 = eq(_T_4811, _T_4812) @[lsu_bus_buffer.scala 554:56] - node _T_4814 = and(_T_4810, _T_4813) @[lsu_bus_buffer.scala 554:38] - node _T_4815 = eq(obuf_tag0, UInt<1>("h01")) @[lsu_bus_buffer.scala 554:92] - node _T_4816 = eq(obuf_tag1, UInt<1>("h01")) @[lsu_bus_buffer.scala 554:126] - node _T_4817 = and(obuf_merge, _T_4816) @[lsu_bus_buffer.scala 554:114] - node _T_4818 = or(_T_4815, _T_4817) @[lsu_bus_buffer.scala 554:100] - node _T_4819 = eq(_T_4818, UInt<1>("h00")) @[lsu_bus_buffer.scala 554:80] - node _T_4820 = and(_T_4814, _T_4819) @[lsu_bus_buffer.scala 554:78] - node _T_4821 = eq(buf_state[2], UInt<3>("h03")) @[lsu_bus_buffer.scala 553:71] - node _T_4822 = and(UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 554:25] - node _T_4823 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 554:50] - node _T_4824 = bits(buf_addr[2], 31, 3) @[lsu_bus_buffer.scala 554:70] - node _T_4825 = eq(_T_4823, _T_4824) @[lsu_bus_buffer.scala 554:56] - node _T_4826 = and(_T_4822, _T_4825) @[lsu_bus_buffer.scala 554:38] - node _T_4827 = eq(obuf_tag0, UInt<2>("h02")) @[lsu_bus_buffer.scala 554:92] - node _T_4828 = eq(obuf_tag1, UInt<2>("h02")) @[lsu_bus_buffer.scala 554:126] - node _T_4829 = and(obuf_merge, _T_4828) @[lsu_bus_buffer.scala 554:114] - node _T_4830 = or(_T_4827, _T_4829) @[lsu_bus_buffer.scala 554:100] - node _T_4831 = eq(_T_4830, UInt<1>("h00")) @[lsu_bus_buffer.scala 554:80] - node _T_4832 = and(_T_4826, _T_4831) @[lsu_bus_buffer.scala 554:78] - node _T_4833 = eq(buf_state[3], UInt<3>("h03")) @[lsu_bus_buffer.scala 553:71] - node _T_4834 = and(UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 554:25] - node _T_4835 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 554:50] - node _T_4836 = bits(buf_addr[3], 31, 3) @[lsu_bus_buffer.scala 554:70] - node _T_4837 = eq(_T_4835, _T_4836) @[lsu_bus_buffer.scala 554:56] - node _T_4838 = and(_T_4834, _T_4837) @[lsu_bus_buffer.scala 554:38] - node _T_4839 = eq(obuf_tag0, UInt<2>("h03")) @[lsu_bus_buffer.scala 554:92] - node _T_4840 = eq(obuf_tag1, UInt<2>("h03")) @[lsu_bus_buffer.scala 554:126] - node _T_4841 = and(obuf_merge, _T_4840) @[lsu_bus_buffer.scala 554:114] - node _T_4842 = or(_T_4839, _T_4841) @[lsu_bus_buffer.scala 554:100] - node _T_4843 = eq(_T_4842, UInt<1>("h00")) @[lsu_bus_buffer.scala 554:80] - node _T_4844 = and(_T_4838, _T_4843) @[lsu_bus_buffer.scala 554:78] + io.dctl_busbuff.lsu_nonblock_load_data <= _T_4777 @[lsu_bus_buffer.scala 546:42] + node _T_4778 = eq(buf_state[0], UInt<3>("h03")) @[lsu_bus_buffer.scala 551:62] + node _T_4779 = bits(buf_sideeffect, 0, 0) @[lsu_bus_buffer.scala 551:89] + node _T_4780 = and(_T_4778, _T_4779) @[lsu_bus_buffer.scala 551:73] + node _T_4781 = and(_T_4780, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 551:93] + node _T_4782 = eq(buf_state[1], UInt<3>("h03")) @[lsu_bus_buffer.scala 551:62] + node _T_4783 = bits(buf_sideeffect, 1, 1) @[lsu_bus_buffer.scala 551:89] + node _T_4784 = and(_T_4782, _T_4783) @[lsu_bus_buffer.scala 551:73] + node _T_4785 = and(_T_4784, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 551:93] + node _T_4786 = eq(buf_state[2], UInt<3>("h03")) @[lsu_bus_buffer.scala 551:62] + node _T_4787 = bits(buf_sideeffect, 2, 2) @[lsu_bus_buffer.scala 551:89] + node _T_4788 = and(_T_4786, _T_4787) @[lsu_bus_buffer.scala 551:73] + node _T_4789 = and(_T_4788, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 551:93] + node _T_4790 = eq(buf_state[3], UInt<3>("h03")) @[lsu_bus_buffer.scala 551:62] + node _T_4791 = bits(buf_sideeffect, 3, 3) @[lsu_bus_buffer.scala 551:89] + node _T_4792 = and(_T_4790, _T_4791) @[lsu_bus_buffer.scala 551:73] + node _T_4793 = and(_T_4792, io.tlu_busbuff.dec_tlu_sideeffect_posted_disable) @[lsu_bus_buffer.scala 551:93] + node _T_4794 = or(_T_4781, _T_4785) @[lsu_bus_buffer.scala 551:153] + node _T_4795 = or(_T_4794, _T_4789) @[lsu_bus_buffer.scala 551:153] + node _T_4796 = or(_T_4795, _T_4793) @[lsu_bus_buffer.scala 551:153] + bus_sideeffect_pend <= _T_4796 @[lsu_bus_buffer.scala 551:23] + node _T_4797 = eq(buf_state[0], UInt<3>("h03")) @[lsu_bus_buffer.scala 552:71] + node _T_4798 = and(UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 553:25] + node _T_4799 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 553:50] + node _T_4800 = bits(buf_addr[0], 31, 3) @[lsu_bus_buffer.scala 553:70] + node _T_4801 = eq(_T_4799, _T_4800) @[lsu_bus_buffer.scala 553:56] + node _T_4802 = and(_T_4798, _T_4801) @[lsu_bus_buffer.scala 553:38] + node _T_4803 = eq(obuf_tag0, UInt<1>("h00")) @[lsu_bus_buffer.scala 553:92] + node _T_4804 = eq(obuf_tag1, UInt<1>("h00")) @[lsu_bus_buffer.scala 553:126] + node _T_4805 = and(obuf_merge, _T_4804) @[lsu_bus_buffer.scala 553:114] + node _T_4806 = or(_T_4803, _T_4805) @[lsu_bus_buffer.scala 553:100] + node _T_4807 = eq(_T_4806, UInt<1>("h00")) @[lsu_bus_buffer.scala 553:80] + node _T_4808 = and(_T_4802, _T_4807) @[lsu_bus_buffer.scala 553:78] + node _T_4809 = eq(buf_state[1], UInt<3>("h03")) @[lsu_bus_buffer.scala 552:71] + node _T_4810 = and(UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 553:25] + node _T_4811 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 553:50] + node _T_4812 = bits(buf_addr[1], 31, 3) @[lsu_bus_buffer.scala 553:70] + node _T_4813 = eq(_T_4811, _T_4812) @[lsu_bus_buffer.scala 553:56] + node _T_4814 = and(_T_4810, _T_4813) @[lsu_bus_buffer.scala 553:38] + node _T_4815 = eq(obuf_tag0, UInt<1>("h01")) @[lsu_bus_buffer.scala 553:92] + node _T_4816 = eq(obuf_tag1, UInt<1>("h01")) @[lsu_bus_buffer.scala 553:126] + node _T_4817 = and(obuf_merge, _T_4816) @[lsu_bus_buffer.scala 553:114] + node _T_4818 = or(_T_4815, _T_4817) @[lsu_bus_buffer.scala 553:100] + node _T_4819 = eq(_T_4818, UInt<1>("h00")) @[lsu_bus_buffer.scala 553:80] + node _T_4820 = and(_T_4814, _T_4819) @[lsu_bus_buffer.scala 553:78] + node _T_4821 = eq(buf_state[2], UInt<3>("h03")) @[lsu_bus_buffer.scala 552:71] + node _T_4822 = and(UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 553:25] + node _T_4823 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 553:50] + node _T_4824 = bits(buf_addr[2], 31, 3) @[lsu_bus_buffer.scala 553:70] + node _T_4825 = eq(_T_4823, _T_4824) @[lsu_bus_buffer.scala 553:56] + node _T_4826 = and(_T_4822, _T_4825) @[lsu_bus_buffer.scala 553:38] + node _T_4827 = eq(obuf_tag0, UInt<2>("h02")) @[lsu_bus_buffer.scala 553:92] + node _T_4828 = eq(obuf_tag1, UInt<2>("h02")) @[lsu_bus_buffer.scala 553:126] + node _T_4829 = and(obuf_merge, _T_4828) @[lsu_bus_buffer.scala 553:114] + node _T_4830 = or(_T_4827, _T_4829) @[lsu_bus_buffer.scala 553:100] + node _T_4831 = eq(_T_4830, UInt<1>("h00")) @[lsu_bus_buffer.scala 553:80] + node _T_4832 = and(_T_4826, _T_4831) @[lsu_bus_buffer.scala 553:78] + node _T_4833 = eq(buf_state[3], UInt<3>("h03")) @[lsu_bus_buffer.scala 552:71] + node _T_4834 = and(UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 553:25] + node _T_4835 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 553:50] + node _T_4836 = bits(buf_addr[3], 31, 3) @[lsu_bus_buffer.scala 553:70] + node _T_4837 = eq(_T_4835, _T_4836) @[lsu_bus_buffer.scala 553:56] + node _T_4838 = and(_T_4834, _T_4837) @[lsu_bus_buffer.scala 553:38] + node _T_4839 = eq(obuf_tag0, UInt<2>("h03")) @[lsu_bus_buffer.scala 553:92] + node _T_4840 = eq(obuf_tag1, UInt<2>("h03")) @[lsu_bus_buffer.scala 553:126] + node _T_4841 = and(obuf_merge, _T_4840) @[lsu_bus_buffer.scala 553:114] + node _T_4842 = or(_T_4839, _T_4841) @[lsu_bus_buffer.scala 553:100] + node _T_4843 = eq(_T_4842, UInt<1>("h00")) @[lsu_bus_buffer.scala 553:80] + node _T_4844 = and(_T_4838, _T_4843) @[lsu_bus_buffer.scala 553:78] node _T_4845 = mux(_T_4797, _T_4808, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4846 = mux(_T_4809, _T_4820, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4847 = mux(_T_4821, _T_4832, UInt<1>("h00")) @[Mux.scala 27:72] @@ -100905,117 +100902,117 @@ circuit quasar_wrapper : node _T_4851 = or(_T_4850, _T_4848) @[Mux.scala 27:72] wire _T_4852 : UInt<1> @[Mux.scala 27:72] _T_4852 <= _T_4851 @[Mux.scala 27:72] - bus_addr_match_pending <= _T_4852 @[lsu_bus_buffer.scala 553:26] - node _T_4853 = or(obuf_cmd_done, obuf_data_done) @[lsu_bus_buffer.scala 556:54] - node _T_4854 = mux(obuf_cmd_done, io.lsu_axi.w.ready, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 556:75] - node _T_4855 = and(io.lsu_axi.aw.ready, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 556:153] - node _T_4856 = mux(_T_4853, _T_4854, _T_4855) @[lsu_bus_buffer.scala 556:39] - node _T_4857 = mux(obuf_write, _T_4856, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 556:23] - bus_cmd_ready <= _T_4857 @[lsu_bus_buffer.scala 556:17] - node _T_4858 = and(io.lsu_axi.aw.valid, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 557:40] - bus_wcmd_sent <= _T_4858 @[lsu_bus_buffer.scala 557:17] - node _T_4859 = and(io.lsu_axi.w.valid, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 558:40] - bus_wdata_sent <= _T_4859 @[lsu_bus_buffer.scala 558:18] - node _T_4860 = or(obuf_cmd_done, bus_wcmd_sent) @[lsu_bus_buffer.scala 559:35] - node _T_4861 = or(obuf_data_done, bus_wdata_sent) @[lsu_bus_buffer.scala 559:70] - node _T_4862 = and(_T_4860, _T_4861) @[lsu_bus_buffer.scala 559:52] - node _T_4863 = and(io.lsu_axi.ar.valid, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 559:112] - node _T_4864 = or(_T_4862, _T_4863) @[lsu_bus_buffer.scala 559:89] - bus_cmd_sent <= _T_4864 @[lsu_bus_buffer.scala 559:16] - node _T_4865 = and(io.lsu_axi.r.valid, io.lsu_axi.r.ready) @[lsu_bus_buffer.scala 560:38] - bus_rsp_read <= _T_4865 @[lsu_bus_buffer.scala 560:16] - node _T_4866 = and(io.lsu_axi.b.valid, io.lsu_axi.b.ready) @[lsu_bus_buffer.scala 561:39] - bus_rsp_write <= _T_4866 @[lsu_bus_buffer.scala 561:17] - bus_rsp_read_tag <= io.lsu_axi.r.bits.id @[lsu_bus_buffer.scala 562:20] - bus_rsp_write_tag <= io.lsu_axi.b.bits.id @[lsu_bus_buffer.scala 563:21] - node _T_4867 = neq(io.lsu_axi.b.bits.resp, UInt<1>("h00")) @[lsu_bus_buffer.scala 564:66] - node _T_4868 = and(bus_rsp_write, _T_4867) @[lsu_bus_buffer.scala 564:40] - bus_rsp_write_error <= _T_4868 @[lsu_bus_buffer.scala 564:23] - node _T_4869 = neq(io.lsu_axi.r.bits.resp, UInt<1>("h00")) @[lsu_bus_buffer.scala 565:64] - node _T_4870 = and(bus_rsp_read, _T_4869) @[lsu_bus_buffer.scala 565:38] - bus_rsp_read_error <= _T_4870 @[lsu_bus_buffer.scala 565:22] - bus_rsp_rdata <= io.lsu_axi.r.bits.data @[lsu_bus_buffer.scala 566:17] - node _T_4871 = and(obuf_valid, obuf_write) @[lsu_bus_buffer.scala 569:37] - node _T_4872 = eq(obuf_cmd_done, UInt<1>("h00")) @[lsu_bus_buffer.scala 569:52] - node _T_4873 = and(_T_4871, _T_4872) @[lsu_bus_buffer.scala 569:50] - node _T_4874 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 569:69] - node _T_4875 = and(_T_4873, _T_4874) @[lsu_bus_buffer.scala 569:67] - io.lsu_axi.aw.valid <= _T_4875 @[lsu_bus_buffer.scala 569:23] - io.lsu_axi.aw.bits.id <= obuf_tag0 @[lsu_bus_buffer.scala 570:25] - node _T_4876 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 571:75] + bus_addr_match_pending <= _T_4852 @[lsu_bus_buffer.scala 552:26] + node _T_4853 = or(obuf_cmd_done, obuf_data_done) @[lsu_bus_buffer.scala 555:54] + node _T_4854 = mux(obuf_cmd_done, io.lsu_axi.w.ready, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 555:75] + node _T_4855 = and(io.lsu_axi.aw.ready, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 555:153] + node _T_4856 = mux(_T_4853, _T_4854, _T_4855) @[lsu_bus_buffer.scala 555:39] + node _T_4857 = mux(obuf_write, _T_4856, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 555:23] + bus_cmd_ready <= _T_4857 @[lsu_bus_buffer.scala 555:17] + node _T_4858 = and(io.lsu_axi.aw.valid, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 556:40] + bus_wcmd_sent <= _T_4858 @[lsu_bus_buffer.scala 556:17] + node _T_4859 = and(io.lsu_axi.w.valid, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 557:40] + bus_wdata_sent <= _T_4859 @[lsu_bus_buffer.scala 557:18] + node _T_4860 = or(obuf_cmd_done, bus_wcmd_sent) @[lsu_bus_buffer.scala 558:35] + node _T_4861 = or(obuf_data_done, bus_wdata_sent) @[lsu_bus_buffer.scala 558:70] + node _T_4862 = and(_T_4860, _T_4861) @[lsu_bus_buffer.scala 558:52] + node _T_4863 = and(io.lsu_axi.ar.valid, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 558:112] + node _T_4864 = or(_T_4862, _T_4863) @[lsu_bus_buffer.scala 558:89] + bus_cmd_sent <= _T_4864 @[lsu_bus_buffer.scala 558:16] + node _T_4865 = and(io.lsu_axi.r.valid, io.lsu_axi.r.ready) @[lsu_bus_buffer.scala 559:38] + bus_rsp_read <= _T_4865 @[lsu_bus_buffer.scala 559:16] + node _T_4866 = and(io.lsu_axi.b.valid, io.lsu_axi.b.ready) @[lsu_bus_buffer.scala 560:39] + bus_rsp_write <= _T_4866 @[lsu_bus_buffer.scala 560:17] + bus_rsp_read_tag <= io.lsu_axi.r.bits.id @[lsu_bus_buffer.scala 561:20] + bus_rsp_write_tag <= io.lsu_axi.b.bits.id @[lsu_bus_buffer.scala 562:21] + node _T_4867 = neq(io.lsu_axi.b.bits.resp, UInt<1>("h00")) @[lsu_bus_buffer.scala 563:66] + node _T_4868 = and(bus_rsp_write, _T_4867) @[lsu_bus_buffer.scala 563:40] + bus_rsp_write_error <= _T_4868 @[lsu_bus_buffer.scala 563:23] + node _T_4869 = neq(io.lsu_axi.r.bits.resp, UInt<1>("h00")) @[lsu_bus_buffer.scala 564:64] + node _T_4870 = and(bus_rsp_read, _T_4869) @[lsu_bus_buffer.scala 564:38] + bus_rsp_read_error <= _T_4870 @[lsu_bus_buffer.scala 564:22] + bus_rsp_rdata <= io.lsu_axi.r.bits.data @[lsu_bus_buffer.scala 565:17] + node _T_4871 = and(obuf_valid, obuf_write) @[lsu_bus_buffer.scala 568:37] + node _T_4872 = eq(obuf_cmd_done, UInt<1>("h00")) @[lsu_bus_buffer.scala 568:52] + node _T_4873 = and(_T_4871, _T_4872) @[lsu_bus_buffer.scala 568:50] + node _T_4874 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 568:69] + node _T_4875 = and(_T_4873, _T_4874) @[lsu_bus_buffer.scala 568:67] + io.lsu_axi.aw.valid <= _T_4875 @[lsu_bus_buffer.scala 568:23] + io.lsu_axi.aw.bits.id <= obuf_tag0 @[lsu_bus_buffer.scala 569:25] + node _T_4876 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 570:75] node _T_4877 = cat(_T_4876, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_4878 = mux(obuf_sideeffect, obuf_addr, _T_4877) @[lsu_bus_buffer.scala 571:33] - io.lsu_axi.aw.bits.addr <= _T_4878 @[lsu_bus_buffer.scala 571:27] + node _T_4878 = mux(obuf_sideeffect, obuf_addr, _T_4877) @[lsu_bus_buffer.scala 570:33] + io.lsu_axi.aw.bits.addr <= _T_4878 @[lsu_bus_buffer.scala 570:27] node _T_4879 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] - node _T_4880 = mux(obuf_sideeffect, _T_4879, UInt<3>("h03")) @[lsu_bus_buffer.scala 572:33] - io.lsu_axi.aw.bits.size <= _T_4880 @[lsu_bus_buffer.scala 572:27] - io.lsu_axi.aw.bits.prot <= UInt<1>("h00") @[lsu_bus_buffer.scala 573:27] - node _T_4881 = mux(obuf_sideeffect, UInt<1>("h00"), UInt<4>("h0f")) @[lsu_bus_buffer.scala 574:34] - io.lsu_axi.aw.bits.cache <= _T_4881 @[lsu_bus_buffer.scala 574:28] - node _T_4882 = bits(obuf_addr, 31, 28) @[lsu_bus_buffer.scala 575:41] - io.lsu_axi.aw.bits.region <= _T_4882 @[lsu_bus_buffer.scala 575:29] - io.lsu_axi.aw.bits.len <= UInt<1>("h00") @[lsu_bus_buffer.scala 576:26] - io.lsu_axi.aw.bits.burst <= UInt<2>("h01") @[lsu_bus_buffer.scala 577:28] - io.lsu_axi.aw.bits.qos <= UInt<1>("h00") @[lsu_bus_buffer.scala 578:26] - io.lsu_axi.aw.bits.lock <= UInt<1>("h00") @[lsu_bus_buffer.scala 579:27] - node _T_4883 = and(obuf_valid, obuf_write) @[lsu_bus_buffer.scala 581:36] - node _T_4884 = eq(obuf_data_done, UInt<1>("h00")) @[lsu_bus_buffer.scala 581:51] - node _T_4885 = and(_T_4883, _T_4884) @[lsu_bus_buffer.scala 581:49] - node _T_4886 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 581:69] - node _T_4887 = and(_T_4885, _T_4886) @[lsu_bus_buffer.scala 581:67] - io.lsu_axi.w.valid <= _T_4887 @[lsu_bus_buffer.scala 581:22] + node _T_4880 = mux(obuf_sideeffect, _T_4879, UInt<3>("h03")) @[lsu_bus_buffer.scala 571:33] + io.lsu_axi.aw.bits.size <= _T_4880 @[lsu_bus_buffer.scala 571:27] + io.lsu_axi.aw.bits.prot <= UInt<1>("h00") @[lsu_bus_buffer.scala 572:27] + node _T_4881 = mux(obuf_sideeffect, UInt<1>("h00"), UInt<4>("h0f")) @[lsu_bus_buffer.scala 573:34] + io.lsu_axi.aw.bits.cache <= _T_4881 @[lsu_bus_buffer.scala 573:28] + node _T_4882 = bits(obuf_addr, 31, 28) @[lsu_bus_buffer.scala 574:41] + io.lsu_axi.aw.bits.region <= _T_4882 @[lsu_bus_buffer.scala 574:29] + io.lsu_axi.aw.bits.len <= UInt<1>("h00") @[lsu_bus_buffer.scala 575:26] + io.lsu_axi.aw.bits.burst <= UInt<2>("h01") @[lsu_bus_buffer.scala 576:28] + io.lsu_axi.aw.bits.qos <= UInt<1>("h00") @[lsu_bus_buffer.scala 577:26] + io.lsu_axi.aw.bits.lock <= UInt<1>("h00") @[lsu_bus_buffer.scala 578:27] + node _T_4883 = and(obuf_valid, obuf_write) @[lsu_bus_buffer.scala 580:36] + node _T_4884 = eq(obuf_data_done, UInt<1>("h00")) @[lsu_bus_buffer.scala 580:51] + node _T_4885 = and(_T_4883, _T_4884) @[lsu_bus_buffer.scala 580:49] + node _T_4886 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 580:69] + node _T_4887 = and(_T_4885, _T_4886) @[lsu_bus_buffer.scala 580:67] + io.lsu_axi.w.valid <= _T_4887 @[lsu_bus_buffer.scala 580:22] node _T_4888 = bits(obuf_write, 0, 0) @[Bitwise.scala 72:15] node _T_4889 = mux(_T_4888, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_4890 = and(obuf_byteen, _T_4889) @[lsu_bus_buffer.scala 582:41] - io.lsu_axi.w.bits.strb <= _T_4890 @[lsu_bus_buffer.scala 582:26] - io.lsu_axi.w.bits.data <= obuf_data @[lsu_bus_buffer.scala 583:26] - io.lsu_axi.w.bits.last <= UInt<1>("h01") @[lsu_bus_buffer.scala 584:26] - node _T_4891 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 586:39] - node _T_4892 = and(obuf_valid, _T_4891) @[lsu_bus_buffer.scala 586:37] - node _T_4893 = eq(obuf_nosend, UInt<1>("h00")) @[lsu_bus_buffer.scala 586:53] - node _T_4894 = and(_T_4892, _T_4893) @[lsu_bus_buffer.scala 586:51] - node _T_4895 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 586:68] - node _T_4896 = and(_T_4894, _T_4895) @[lsu_bus_buffer.scala 586:66] - io.lsu_axi.ar.valid <= _T_4896 @[lsu_bus_buffer.scala 586:23] - io.lsu_axi.ar.bits.id <= obuf_tag0 @[lsu_bus_buffer.scala 587:25] - node _T_4897 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 588:75] + node _T_4890 = and(obuf_byteen, _T_4889) @[lsu_bus_buffer.scala 581:41] + io.lsu_axi.w.bits.strb <= _T_4890 @[lsu_bus_buffer.scala 581:26] + io.lsu_axi.w.bits.data <= obuf_data @[lsu_bus_buffer.scala 582:26] + io.lsu_axi.w.bits.last <= UInt<1>("h01") @[lsu_bus_buffer.scala 583:26] + node _T_4891 = eq(obuf_write, UInt<1>("h00")) @[lsu_bus_buffer.scala 585:39] + node _T_4892 = and(obuf_valid, _T_4891) @[lsu_bus_buffer.scala 585:37] + node _T_4893 = eq(obuf_nosend, UInt<1>("h00")) @[lsu_bus_buffer.scala 585:53] + node _T_4894 = and(_T_4892, _T_4893) @[lsu_bus_buffer.scala 585:51] + node _T_4895 = eq(bus_addr_match_pending, UInt<1>("h00")) @[lsu_bus_buffer.scala 585:68] + node _T_4896 = and(_T_4894, _T_4895) @[lsu_bus_buffer.scala 585:66] + io.lsu_axi.ar.valid <= _T_4896 @[lsu_bus_buffer.scala 585:23] + io.lsu_axi.ar.bits.id <= obuf_tag0 @[lsu_bus_buffer.scala 586:25] + node _T_4897 = bits(obuf_addr, 31, 3) @[lsu_bus_buffer.scala 587:75] node _T_4898 = cat(_T_4897, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_4899 = mux(obuf_sideeffect, obuf_addr, _T_4898) @[lsu_bus_buffer.scala 588:33] - io.lsu_axi.ar.bits.addr <= _T_4899 @[lsu_bus_buffer.scala 588:27] + node _T_4899 = mux(obuf_sideeffect, obuf_addr, _T_4898) @[lsu_bus_buffer.scala 587:33] + io.lsu_axi.ar.bits.addr <= _T_4899 @[lsu_bus_buffer.scala 587:27] node _T_4900 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] - node _T_4901 = mux(obuf_sideeffect, _T_4900, UInt<3>("h03")) @[lsu_bus_buffer.scala 589:33] - io.lsu_axi.ar.bits.size <= _T_4901 @[lsu_bus_buffer.scala 589:27] - io.lsu_axi.ar.bits.prot <= UInt<1>("h00") @[lsu_bus_buffer.scala 590:27] - node _T_4902 = mux(obuf_sideeffect, UInt<4>("h00"), UInt<4>("h0f")) @[lsu_bus_buffer.scala 591:34] - io.lsu_axi.ar.bits.cache <= _T_4902 @[lsu_bus_buffer.scala 591:28] - node _T_4903 = bits(obuf_addr, 31, 28) @[lsu_bus_buffer.scala 592:41] - io.lsu_axi.ar.bits.region <= _T_4903 @[lsu_bus_buffer.scala 592:29] - io.lsu_axi.ar.bits.len <= UInt<1>("h00") @[lsu_bus_buffer.scala 593:26] - io.lsu_axi.ar.bits.burst <= UInt<2>("h01") @[lsu_bus_buffer.scala 594:28] - io.lsu_axi.ar.bits.qos <= UInt<1>("h00") @[lsu_bus_buffer.scala 595:26] - io.lsu_axi.ar.bits.lock <= UInt<1>("h00") @[lsu_bus_buffer.scala 596:27] - io.lsu_axi.b.ready <= UInt<1>("h01") @[lsu_bus_buffer.scala 597:22] - io.lsu_axi.r.ready <= UInt<1>("h01") @[lsu_bus_buffer.scala 598:22] - node _T_4904 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 599:93] - node _T_4905 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 599:137] - node _T_4906 = and(io.lsu_bus_clk_en_q, _T_4905) @[lsu_bus_buffer.scala 599:126] - node _T_4907 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 599:152] - node _T_4908 = and(_T_4906, _T_4907) @[lsu_bus_buffer.scala 599:141] - node _T_4909 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 599:93] - node _T_4910 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 599:137] - node _T_4911 = and(io.lsu_bus_clk_en_q, _T_4910) @[lsu_bus_buffer.scala 599:126] - node _T_4912 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 599:152] - node _T_4913 = and(_T_4911, _T_4912) @[lsu_bus_buffer.scala 599:141] - node _T_4914 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 599:93] - node _T_4915 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 599:137] - node _T_4916 = and(io.lsu_bus_clk_en_q, _T_4915) @[lsu_bus_buffer.scala 599:126] - node _T_4917 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 599:152] - node _T_4918 = and(_T_4916, _T_4917) @[lsu_bus_buffer.scala 599:141] - node _T_4919 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 599:93] - node _T_4920 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 599:137] - node _T_4921 = and(io.lsu_bus_clk_en_q, _T_4920) @[lsu_bus_buffer.scala 599:126] - node _T_4922 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 599:152] - node _T_4923 = and(_T_4921, _T_4922) @[lsu_bus_buffer.scala 599:141] + node _T_4901 = mux(obuf_sideeffect, _T_4900, UInt<3>("h03")) @[lsu_bus_buffer.scala 588:33] + io.lsu_axi.ar.bits.size <= _T_4901 @[lsu_bus_buffer.scala 588:27] + io.lsu_axi.ar.bits.prot <= UInt<1>("h00") @[lsu_bus_buffer.scala 589:27] + node _T_4902 = mux(obuf_sideeffect, UInt<4>("h00"), UInt<4>("h0f")) @[lsu_bus_buffer.scala 590:34] + io.lsu_axi.ar.bits.cache <= _T_4902 @[lsu_bus_buffer.scala 590:28] + node _T_4903 = bits(obuf_addr, 31, 28) @[lsu_bus_buffer.scala 591:41] + io.lsu_axi.ar.bits.region <= _T_4903 @[lsu_bus_buffer.scala 591:29] + io.lsu_axi.ar.bits.len <= UInt<1>("h00") @[lsu_bus_buffer.scala 592:26] + io.lsu_axi.ar.bits.burst <= UInt<2>("h01") @[lsu_bus_buffer.scala 593:28] + io.lsu_axi.ar.bits.qos <= UInt<1>("h00") @[lsu_bus_buffer.scala 594:26] + io.lsu_axi.ar.bits.lock <= UInt<1>("h00") @[lsu_bus_buffer.scala 595:27] + io.lsu_axi.b.ready <= UInt<1>("h01") @[lsu_bus_buffer.scala 596:22] + io.lsu_axi.r.ready <= UInt<1>("h01") @[lsu_bus_buffer.scala 597:22] + node _T_4904 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 598:93] + node _T_4905 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 598:137] + node _T_4906 = and(io.lsu_bus_clk_en_q, _T_4905) @[lsu_bus_buffer.scala 598:126] + node _T_4907 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 598:152] + node _T_4908 = and(_T_4906, _T_4907) @[lsu_bus_buffer.scala 598:141] + node _T_4909 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 598:93] + node _T_4910 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 598:137] + node _T_4911 = and(io.lsu_bus_clk_en_q, _T_4910) @[lsu_bus_buffer.scala 598:126] + node _T_4912 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 598:152] + node _T_4913 = and(_T_4911, _T_4912) @[lsu_bus_buffer.scala 598:141] + node _T_4914 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 598:93] + node _T_4915 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 598:137] + node _T_4916 = and(io.lsu_bus_clk_en_q, _T_4915) @[lsu_bus_buffer.scala 598:126] + node _T_4917 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 598:152] + node _T_4918 = and(_T_4916, _T_4917) @[lsu_bus_buffer.scala 598:141] + node _T_4919 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 598:93] + node _T_4920 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 598:137] + node _T_4921 = and(io.lsu_bus_clk_en_q, _T_4920) @[lsu_bus_buffer.scala 598:126] + node _T_4922 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 598:152] + node _T_4923 = and(_T_4921, _T_4922) @[lsu_bus_buffer.scala 598:141] node _T_4924 = mux(_T_4904, _T_4908, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4925 = mux(_T_4909, _T_4913, UInt<1>("h00")) @[Mux.scala 27:72] node _T_4926 = mux(_T_4914, _T_4918, UInt<1>("h00")) @[Mux.scala 27:72] @@ -101025,27 +101022,27 @@ circuit quasar_wrapper : node _T_4930 = or(_T_4929, _T_4927) @[Mux.scala 27:72] wire _T_4931 : UInt<1> @[Mux.scala 27:72] _T_4931 <= _T_4930 @[Mux.scala 27:72] - io.tlu_busbuff.lsu_imprecise_error_store_any <= _T_4931 @[lsu_bus_buffer.scala 599:48] - node _T_4932 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 600:82] - node _T_4933 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 600:104] - node _T_4934 = and(_T_4932, _T_4933) @[lsu_bus_buffer.scala 600:93] - node _T_4935 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 600:119] - node _T_4936 = and(_T_4934, _T_4935) @[lsu_bus_buffer.scala 600:108] - node _T_4937 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 600:82] - node _T_4938 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 600:104] - node _T_4939 = and(_T_4937, _T_4938) @[lsu_bus_buffer.scala 600:93] - node _T_4940 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 600:119] - node _T_4941 = and(_T_4939, _T_4940) @[lsu_bus_buffer.scala 600:108] - node _T_4942 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 600:82] - node _T_4943 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 600:104] - node _T_4944 = and(_T_4942, _T_4943) @[lsu_bus_buffer.scala 600:93] - node _T_4945 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 600:119] - node _T_4946 = and(_T_4944, _T_4945) @[lsu_bus_buffer.scala 600:108] - node _T_4947 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 600:82] - node _T_4948 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 600:104] - node _T_4949 = and(_T_4947, _T_4948) @[lsu_bus_buffer.scala 600:93] - node _T_4950 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 600:119] - node _T_4951 = and(_T_4949, _T_4950) @[lsu_bus_buffer.scala 600:108] + io.tlu_busbuff.lsu_imprecise_error_store_any <= _T_4931 @[lsu_bus_buffer.scala 598:48] + node _T_4932 = eq(buf_state[0], UInt<3>("h06")) @[lsu_bus_buffer.scala 599:82] + node _T_4933 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 599:104] + node _T_4934 = and(_T_4932, _T_4933) @[lsu_bus_buffer.scala 599:93] + node _T_4935 = bits(buf_write, 0, 0) @[lsu_bus_buffer.scala 599:119] + node _T_4936 = and(_T_4934, _T_4935) @[lsu_bus_buffer.scala 599:108] + node _T_4937 = eq(buf_state[1], UInt<3>("h06")) @[lsu_bus_buffer.scala 599:82] + node _T_4938 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 599:104] + node _T_4939 = and(_T_4937, _T_4938) @[lsu_bus_buffer.scala 599:93] + node _T_4940 = bits(buf_write, 1, 1) @[lsu_bus_buffer.scala 599:119] + node _T_4941 = and(_T_4939, _T_4940) @[lsu_bus_buffer.scala 599:108] + node _T_4942 = eq(buf_state[2], UInt<3>("h06")) @[lsu_bus_buffer.scala 599:82] + node _T_4943 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 599:104] + node _T_4944 = and(_T_4942, _T_4943) @[lsu_bus_buffer.scala 599:93] + node _T_4945 = bits(buf_write, 2, 2) @[lsu_bus_buffer.scala 599:119] + node _T_4946 = and(_T_4944, _T_4945) @[lsu_bus_buffer.scala 599:108] + node _T_4947 = eq(buf_state[3], UInt<3>("h06")) @[lsu_bus_buffer.scala 599:82] + node _T_4948 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 599:104] + node _T_4949 = and(_T_4947, _T_4948) @[lsu_bus_buffer.scala 599:93] + node _T_4950 = bits(buf_write, 3, 3) @[lsu_bus_buffer.scala 599:119] + node _T_4951 = and(_T_4949, _T_4950) @[lsu_bus_buffer.scala 599:108] node _T_4952 = mux(_T_4936, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_4953 = mux(_T_4941, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_4954 = mux(_T_4946, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -101055,49 +101052,49 @@ circuit quasar_wrapper : node _T_4958 = or(_T_4957, _T_4955) @[Mux.scala 27:72] wire lsu_imprecise_error_store_tag : UInt<2> @[Mux.scala 27:72] lsu_imprecise_error_store_tag <= _T_4958 @[Mux.scala 27:72] - node _T_4959 = eq(io.tlu_busbuff.lsu_imprecise_error_store_any, UInt<1>("h00")) @[lsu_bus_buffer.scala 602:97] - node _T_4960 = and(io.dctl_busbuff.lsu_nonblock_load_data_error, _T_4959) @[lsu_bus_buffer.scala 602:95] - io.tlu_busbuff.lsu_imprecise_error_load_any <= _T_4960 @[lsu_bus_buffer.scala 602:47] - node _T_4961 = mux(io.tlu_busbuff.lsu_imprecise_error_store_any, buf_addr[lsu_imprecise_error_store_tag], buf_addr[io.dctl_busbuff.lsu_nonblock_load_data_tag]) @[lsu_bus_buffer.scala 603:53] - io.tlu_busbuff.lsu_imprecise_error_addr_any <= _T_4961 @[lsu_bus_buffer.scala 603:47] - lsu_bus_cntr_overflow <= UInt<1>("h00") @[lsu_bus_buffer.scala 604:25] - io.lsu_bus_idle_any <= UInt<1>("h01") @[lsu_bus_buffer.scala 606:23] - node _T_4962 = and(io.lsu_axi.aw.valid, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 609:59] - node _T_4963 = and(io.lsu_axi.w.valid, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 609:104] - node _T_4964 = or(_T_4962, _T_4963) @[lsu_bus_buffer.scala 609:82] - node _T_4965 = and(io.lsu_axi.ar.valid, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 609:149] - node _T_4966 = or(_T_4964, _T_4965) @[lsu_bus_buffer.scala 609:126] - io.tlu_busbuff.lsu_pmu_bus_trxn <= _T_4966 @[lsu_bus_buffer.scala 609:35] - node _T_4967 = and(io.lsu_busreq_r, io.ldst_dual_r) @[lsu_bus_buffer.scala 610:60] - node _T_4968 = and(_T_4967, io.lsu_commit_r) @[lsu_bus_buffer.scala 610:77] - io.tlu_busbuff.lsu_pmu_bus_misaligned <= _T_4968 @[lsu_bus_buffer.scala 610:41] - node _T_4969 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[lsu_bus_buffer.scala 611:83] - io.tlu_busbuff.lsu_pmu_bus_error <= _T_4969 @[lsu_bus_buffer.scala 611:36] - node _T_4970 = eq(io.lsu_axi.aw.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 613:61] - node _T_4971 = and(io.lsu_axi.aw.valid, _T_4970) @[lsu_bus_buffer.scala 613:59] - node _T_4972 = eq(io.lsu_axi.w.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 613:107] - node _T_4973 = and(io.lsu_axi.w.valid, _T_4972) @[lsu_bus_buffer.scala 613:105] - node _T_4974 = or(_T_4971, _T_4973) @[lsu_bus_buffer.scala 613:83] - node _T_4975 = eq(io.lsu_axi.ar.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 613:153] - node _T_4976 = and(io.lsu_axi.ar.valid, _T_4975) @[lsu_bus_buffer.scala 613:151] - node _T_4977 = or(_T_4974, _T_4976) @[lsu_bus_buffer.scala 613:128] - io.tlu_busbuff.lsu_pmu_bus_busy <= _T_4977 @[lsu_bus_buffer.scala 613:35] - reg _T_4978 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 615:49] - _T_4978 <= WrPtr0_m @[lsu_bus_buffer.scala 615:49] - WrPtr0_r <= _T_4978 @[lsu_bus_buffer.scala 615:12] - reg _T_4979 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 616:49] - _T_4979 <= WrPtr1_m @[lsu_bus_buffer.scala 616:49] - WrPtr1_r <= _T_4979 @[lsu_bus_buffer.scala 616:12] - node _T_4980 = eq(io.flush_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 617:75] - node _T_4981 = and(io.lsu_busreq_m, _T_4980) @[lsu_bus_buffer.scala 617:73] - node _T_4982 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 617:89] - node _T_4983 = and(_T_4981, _T_4982) @[lsu_bus_buffer.scala 617:87] - reg _T_4984 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 617:56] - _T_4984 <= _T_4983 @[lsu_bus_buffer.scala 617:56] - io.lsu_busreq_r <= _T_4984 @[lsu_bus_buffer.scala 617:19] - reg _T_4985 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 618:66] - _T_4985 <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu_bus_buffer.scala 618:66] - lsu_nonblock_load_valid_r <= _T_4985 @[lsu_bus_buffer.scala 618:29] + node _T_4959 = eq(io.tlu_busbuff.lsu_imprecise_error_store_any, UInt<1>("h00")) @[lsu_bus_buffer.scala 601:97] + node _T_4960 = and(io.dctl_busbuff.lsu_nonblock_load_data_error, _T_4959) @[lsu_bus_buffer.scala 601:95] + io.tlu_busbuff.lsu_imprecise_error_load_any <= _T_4960 @[lsu_bus_buffer.scala 601:47] + node _T_4961 = mux(io.tlu_busbuff.lsu_imprecise_error_store_any, buf_addr[lsu_imprecise_error_store_tag], buf_addr[io.dctl_busbuff.lsu_nonblock_load_data_tag]) @[lsu_bus_buffer.scala 602:53] + io.tlu_busbuff.lsu_imprecise_error_addr_any <= _T_4961 @[lsu_bus_buffer.scala 602:47] + lsu_bus_cntr_overflow <= UInt<1>("h00") @[lsu_bus_buffer.scala 603:25] + io.lsu_bus_idle_any <= UInt<1>("h01") @[lsu_bus_buffer.scala 605:23] + node _T_4962 = and(io.lsu_axi.aw.valid, io.lsu_axi.aw.ready) @[lsu_bus_buffer.scala 608:59] + node _T_4963 = and(io.lsu_axi.w.valid, io.lsu_axi.w.ready) @[lsu_bus_buffer.scala 608:104] + node _T_4964 = or(_T_4962, _T_4963) @[lsu_bus_buffer.scala 608:82] + node _T_4965 = and(io.lsu_axi.ar.valid, io.lsu_axi.ar.ready) @[lsu_bus_buffer.scala 608:149] + node _T_4966 = or(_T_4964, _T_4965) @[lsu_bus_buffer.scala 608:126] + io.tlu_busbuff.lsu_pmu_bus_trxn <= _T_4966 @[lsu_bus_buffer.scala 608:35] + node _T_4967 = and(io.lsu_busreq_r, io.ldst_dual_r) @[lsu_bus_buffer.scala 609:60] + node _T_4968 = and(_T_4967, io.lsu_commit_r) @[lsu_bus_buffer.scala 609:77] + io.tlu_busbuff.lsu_pmu_bus_misaligned <= _T_4968 @[lsu_bus_buffer.scala 609:41] + node _T_4969 = or(io.tlu_busbuff.lsu_imprecise_error_load_any, io.tlu_busbuff.lsu_imprecise_error_store_any) @[lsu_bus_buffer.scala 610:83] + io.tlu_busbuff.lsu_pmu_bus_error <= _T_4969 @[lsu_bus_buffer.scala 610:36] + node _T_4970 = eq(io.lsu_axi.aw.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 612:61] + node _T_4971 = and(io.lsu_axi.aw.valid, _T_4970) @[lsu_bus_buffer.scala 612:59] + node _T_4972 = eq(io.lsu_axi.w.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 612:107] + node _T_4973 = and(io.lsu_axi.w.valid, _T_4972) @[lsu_bus_buffer.scala 612:105] + node _T_4974 = or(_T_4971, _T_4973) @[lsu_bus_buffer.scala 612:83] + node _T_4975 = eq(io.lsu_axi.ar.ready, UInt<1>("h00")) @[lsu_bus_buffer.scala 612:153] + node _T_4976 = and(io.lsu_axi.ar.valid, _T_4975) @[lsu_bus_buffer.scala 612:151] + node _T_4977 = or(_T_4974, _T_4976) @[lsu_bus_buffer.scala 612:128] + io.tlu_busbuff.lsu_pmu_bus_busy <= _T_4977 @[lsu_bus_buffer.scala 612:35] + reg _T_4978 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 614:49] + _T_4978 <= WrPtr0_m @[lsu_bus_buffer.scala 614:49] + WrPtr0_r <= _T_4978 @[lsu_bus_buffer.scala 614:12] + reg _T_4979 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 615:49] + _T_4979 <= WrPtr1_m @[lsu_bus_buffer.scala 615:49] + WrPtr1_r <= _T_4979 @[lsu_bus_buffer.scala 615:12] + node _T_4980 = eq(io.flush_r, UInt<1>("h00")) @[lsu_bus_buffer.scala 616:75] + node _T_4981 = and(io.lsu_busreq_m, _T_4980) @[lsu_bus_buffer.scala 616:73] + node _T_4982 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[lsu_bus_buffer.scala 616:89] + node _T_4983 = and(_T_4981, _T_4982) @[lsu_bus_buffer.scala 616:87] + reg _T_4984 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 616:56] + _T_4984 <= _T_4983 @[lsu_bus_buffer.scala 616:56] + io.lsu_busreq_r <= _T_4984 @[lsu_bus_buffer.scala 616:19] + reg _T_4985 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 617:66] + _T_4985 <= io.dctl_busbuff.lsu_nonblock_load_valid_m @[lsu_bus_buffer.scala 617:66] + lsu_nonblock_load_valid_r <= _T_4985 @[lsu_bus_buffer.scala 617:29] module lsu_bus_intf : input clock : Clock @@ -102478,119 +102475,119 @@ circuit quasar_wrapper : module pic_ctrl : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, flip extintsrc_req : UInt<32>, flip lsu_pic : {picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>}, flip meicurpl : UInt<4>, flip meipt : UInt<4>, mexintpend : UInt<1>, claimid : UInt<8>, pl : UInt<4>, mhwakeup : UInt<1>} + output io : {flip scan_mode : UInt<1>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, flip extintsrc_req : UInt<32>, flip lsu_pic : {picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>}, flip dec_pic : {flip pic_claimid : UInt<8>, flip pic_pl : UInt<4>, flip mhwakeup : UInt<1>, dec_tlu_meicurpl : UInt<4>, dec_tlu_meipt : UInt<4>, flip mexintpend : UInt<1>}} wire GW_CONFIG : UInt<32> GW_CONFIG <= UInt<1>("h00") wire intpend_rd_out : UInt<32> intpend_rd_out <= UInt<32>("h00") - wire intpriority_reg_inv : UInt<4>[32] @[pic_ctrl.scala 66:42] + wire intpriority_reg_inv : UInt<4>[32] @[pic_ctrl.scala 67:42] wire intpend_reg_extended : UInt<64> intpend_reg_extended <= UInt<64>("h00") wire selected_int_priority : UInt<4> selected_int_priority <= UInt<4>("h00") - wire intpend_w_prior_en : UInt<4>[32] @[pic_ctrl.scala 69:42] - wire intpend_id : UInt<8>[32] @[pic_ctrl.scala 70:42] - wire levelx_intpend_w_prior_en : UInt<4>[10][4] @[pic_ctrl.scala 71:42] - levelx_intpend_w_prior_en[0][0] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[0][1] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[0][2] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[0][3] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[0][4] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[0][5] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[0][6] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[0][7] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[0][8] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[0][9] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[1][0] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[1][1] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[1][2] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[1][3] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[1][4] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[1][5] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[1][6] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[1][7] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[1][8] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[1][9] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[2][0] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[2][1] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[2][2] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[2][3] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[2][4] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[2][5] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[2][6] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[2][7] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[2][8] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[2][9] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[3][0] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[3][1] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[3][2] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[3][3] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[3][4] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[3][5] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[3][6] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[3][7] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[3][8] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - levelx_intpend_w_prior_en[3][9] <= UInt<1>("h00") @[pic_ctrl.scala 72:158] - wire levelx_intpend_id : UInt<8>[10][4] @[pic_ctrl.scala 73:42] - levelx_intpend_id[0][0] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[0][1] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[0][2] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[0][3] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[0][4] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[0][5] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[0][6] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[0][7] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[0][8] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[0][9] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[1][0] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[1][1] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[1][2] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[1][3] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[1][4] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[1][5] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[1][6] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[1][7] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[1][8] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[1][9] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[2][0] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[2][1] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[2][2] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[2][3] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[2][4] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[2][5] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[2][6] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[2][7] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[2][8] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[2][9] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[3][0] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[3][1] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[3][2] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[3][3] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[3][4] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[3][5] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[3][6] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[3][7] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[3][8] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - levelx_intpend_id[3][9] <= UInt<1>("h00") @[pic_ctrl.scala 74:150] - wire l2_intpend_w_prior_en_ff : UInt<4>[8] @[pic_ctrl.scala 75:42] - l2_intpend_w_prior_en_ff[0] <= UInt<1>("h00") @[pic_ctrl.scala 76:109] - l2_intpend_w_prior_en_ff[1] <= UInt<1>("h00") @[pic_ctrl.scala 76:109] - l2_intpend_w_prior_en_ff[2] <= UInt<1>("h00") @[pic_ctrl.scala 76:109] - l2_intpend_w_prior_en_ff[3] <= UInt<1>("h00") @[pic_ctrl.scala 76:109] - l2_intpend_w_prior_en_ff[4] <= UInt<1>("h00") @[pic_ctrl.scala 76:109] - l2_intpend_w_prior_en_ff[5] <= UInt<1>("h00") @[pic_ctrl.scala 76:109] - l2_intpend_w_prior_en_ff[6] <= UInt<1>("h00") @[pic_ctrl.scala 76:109] - l2_intpend_w_prior_en_ff[7] <= UInt<1>("h00") @[pic_ctrl.scala 76:109] - wire l2_intpend_id_ff : UInt<8>[8] @[pic_ctrl.scala 77:42] - l2_intpend_id_ff[0] <= UInt<1>("h00") @[pic_ctrl.scala 78:101] - l2_intpend_id_ff[1] <= UInt<1>("h00") @[pic_ctrl.scala 78:101] - l2_intpend_id_ff[2] <= UInt<1>("h00") @[pic_ctrl.scala 78:101] - l2_intpend_id_ff[3] <= UInt<1>("h00") @[pic_ctrl.scala 78:101] - l2_intpend_id_ff[4] <= UInt<1>("h00") @[pic_ctrl.scala 78:101] - l2_intpend_id_ff[5] <= UInt<1>("h00") @[pic_ctrl.scala 78:101] - l2_intpend_id_ff[6] <= UInt<1>("h00") @[pic_ctrl.scala 78:101] - l2_intpend_id_ff[7] <= UInt<1>("h00") @[pic_ctrl.scala 78:101] + wire intpend_w_prior_en : UInt<4>[32] @[pic_ctrl.scala 70:42] + wire intpend_id : UInt<8>[32] @[pic_ctrl.scala 71:42] + wire levelx_intpend_w_prior_en : UInt<4>[10][4] @[pic_ctrl.scala 72:42] + levelx_intpend_w_prior_en[0][0] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[0][1] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[0][2] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[0][3] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[0][4] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[0][5] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[0][6] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[0][7] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[0][8] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[0][9] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[1][0] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[1][1] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[1][2] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[1][3] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[1][4] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[1][5] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[1][6] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[1][7] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[1][8] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[1][9] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[2][0] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[2][1] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[2][2] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[2][3] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[2][4] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[2][5] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[2][6] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[2][7] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[2][8] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[2][9] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[3][0] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[3][1] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[3][2] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[3][3] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[3][4] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[3][5] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[3][6] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[3][7] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[3][8] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + levelx_intpend_w_prior_en[3][9] <= UInt<1>("h00") @[pic_ctrl.scala 73:158] + wire levelx_intpend_id : UInt<8>[10][4] @[pic_ctrl.scala 74:42] + levelx_intpend_id[0][0] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[0][1] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[0][2] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[0][3] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[0][4] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[0][5] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[0][6] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[0][7] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[0][8] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[0][9] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[1][0] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[1][1] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[1][2] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[1][3] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[1][4] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[1][5] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[1][6] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[1][7] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[1][8] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[1][9] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[2][0] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[2][1] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[2][2] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[2][3] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[2][4] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[2][5] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[2][6] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[2][7] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[2][8] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[2][9] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[3][0] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[3][1] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[3][2] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[3][3] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[3][4] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[3][5] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[3][6] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[3][7] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[3][8] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + levelx_intpend_id[3][9] <= UInt<1>("h00") @[pic_ctrl.scala 75:150] + wire l2_intpend_w_prior_en_ff : UInt<4>[8] @[pic_ctrl.scala 76:42] + l2_intpend_w_prior_en_ff[0] <= UInt<1>("h00") @[pic_ctrl.scala 77:109] + l2_intpend_w_prior_en_ff[1] <= UInt<1>("h00") @[pic_ctrl.scala 77:109] + l2_intpend_w_prior_en_ff[2] <= UInt<1>("h00") @[pic_ctrl.scala 77:109] + l2_intpend_w_prior_en_ff[3] <= UInt<1>("h00") @[pic_ctrl.scala 77:109] + l2_intpend_w_prior_en_ff[4] <= UInt<1>("h00") @[pic_ctrl.scala 77:109] + l2_intpend_w_prior_en_ff[5] <= UInt<1>("h00") @[pic_ctrl.scala 77:109] + l2_intpend_w_prior_en_ff[6] <= UInt<1>("h00") @[pic_ctrl.scala 77:109] + l2_intpend_w_prior_en_ff[7] <= UInt<1>("h00") @[pic_ctrl.scala 77:109] + wire l2_intpend_id_ff : UInt<8>[8] @[pic_ctrl.scala 78:42] + l2_intpend_id_ff[0] <= UInt<1>("h00") @[pic_ctrl.scala 79:101] + l2_intpend_id_ff[1] <= UInt<1>("h00") @[pic_ctrl.scala 79:101] + l2_intpend_id_ff[2] <= UInt<1>("h00") @[pic_ctrl.scala 79:101] + l2_intpend_id_ff[3] <= UInt<1>("h00") @[pic_ctrl.scala 79:101] + l2_intpend_id_ff[4] <= UInt<1>("h00") @[pic_ctrl.scala 79:101] + l2_intpend_id_ff[5] <= UInt<1>("h00") @[pic_ctrl.scala 79:101] + l2_intpend_id_ff[6] <= UInt<1>("h00") @[pic_ctrl.scala 79:101] + l2_intpend_id_ff[7] <= UInt<1>("h00") @[pic_ctrl.scala 79:101] wire config_reg : UInt<1> config_reg <= UInt<1>("h00") wire intpriord : UInt<1> @@ -102615,3268 +102612,3268 @@ circuit quasar_wrapper : picm_mken_ff <= UInt<1>("h00") wire claimid_in : UInt<8> claimid_in <= UInt<8>("h00") - wire pic_raddr_c1_clk : Clock @[pic_ctrl.scala 94:42] - wire pic_data_c1_clk : Clock @[pic_ctrl.scala 95:42] - wire pic_pri_c1_clk : Clock @[pic_ctrl.scala 96:42] - wire pic_int_c1_clk : Clock @[pic_ctrl.scala 97:42] - wire gw_config_c1_clk : Clock @[pic_ctrl.scala 98:42] - reg _T : UInt, pic_raddr_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 100:56] - _T <= io.lsu_pic.picm_rdaddr @[pic_ctrl.scala 100:56] - picm_raddr_ff <= _T @[pic_ctrl.scala 100:46] - reg _T_1 : UInt, pic_data_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 101:57] - _T_1 <= io.lsu_pic.picm_wraddr @[pic_ctrl.scala 101:57] - picm_waddr_ff <= _T_1 @[pic_ctrl.scala 101:46] - reg _T_2 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 102:55] - _T_2 <= io.lsu_pic.picm_wren @[pic_ctrl.scala 102:55] - picm_wren_ff <= _T_2 @[pic_ctrl.scala 102:45] - reg _T_3 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 103:55] - _T_3 <= io.lsu_pic.picm_rden @[pic_ctrl.scala 103:55] - picm_rden_ff <= _T_3 @[pic_ctrl.scala 103:45] - reg _T_4 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 104:55] - _T_4 <= io.lsu_pic.picm_mken @[pic_ctrl.scala 104:55] - picm_mken_ff <= _T_4 @[pic_ctrl.scala 104:45] - reg _T_5 : UInt, pic_data_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 105:58] - _T_5 <= io.lsu_pic.picm_wr_data @[pic_ctrl.scala 105:58] - picm_wr_data_ff <= _T_5 @[pic_ctrl.scala 105:48] - node _T_6 = xor(picm_raddr_ff, UInt<32>("h0f00c2000")) @[pic_ctrl.scala 107:59] - node temp_raddr_intenable_base_match = not(_T_6) @[pic_ctrl.scala 107:43] - node _T_7 = bits(temp_raddr_intenable_base_match, 31, 7) @[pic_ctrl.scala 108:71] - node raddr_intenable_base_match = andr(_T_7) @[pic_ctrl.scala 108:89] - node _T_8 = bits(picm_raddr_ff, 31, 7) @[pic_ctrl.scala 110:53] - node raddr_intpriority_base_match = eq(_T_8, UInt<25>("h01e01800")) @[pic_ctrl.scala 110:71] - node _T_9 = bits(picm_raddr_ff, 31, 7) @[pic_ctrl.scala 111:53] - node raddr_config_gw_base_match = eq(_T_9, UInt<25>("h01e01880")) @[pic_ctrl.scala 111:71] - node _T_10 = bits(picm_raddr_ff, 31, 0) @[pic_ctrl.scala 112:53] - node raddr_config_pic_match = eq(_T_10, UInt<32>("h0f00c3000")) @[pic_ctrl.scala 112:71] - node _T_11 = bits(picm_raddr_ff, 31, 6) @[pic_ctrl.scala 113:53] - node addr_intpend_base_match = eq(_T_11, UInt<26>("h03c03040")) @[pic_ctrl.scala 113:71] - node _T_12 = bits(picm_waddr_ff, 31, 0) @[pic_ctrl.scala 115:53] - node waddr_config_pic_match = eq(_T_12, UInt<32>("h0f00c3000")) @[pic_ctrl.scala 115:71] - node _T_13 = bits(picm_waddr_ff, 31, 7) @[pic_ctrl.scala 116:53] - node addr_clear_gw_base_match = eq(_T_13, UInt<25>("h01e018a0")) @[pic_ctrl.scala 116:71] - node _T_14 = bits(picm_waddr_ff, 31, 7) @[pic_ctrl.scala 117:53] - node waddr_intpriority_base_match = eq(_T_14, UInt<25>("h01e01800")) @[pic_ctrl.scala 117:71] - node _T_15 = bits(picm_waddr_ff, 31, 7) @[pic_ctrl.scala 118:53] - node waddr_intenable_base_match = eq(_T_15, UInt<25>("h01e01840")) @[pic_ctrl.scala 118:71] - node _T_16 = bits(picm_waddr_ff, 31, 7) @[pic_ctrl.scala 119:53] - node waddr_config_gw_base_match = eq(_T_16, UInt<25>("h01e01880")) @[pic_ctrl.scala 119:71] - node _T_17 = and(picm_rden_ff, picm_wren_ff) @[pic_ctrl.scala 120:53] - node _T_18 = eq(picm_raddr_ff, picm_waddr_ff) @[pic_ctrl.scala 120:86] - node picm_bypass_ff = and(_T_17, _T_18) @[pic_ctrl.scala 120:68] - node _T_19 = or(io.lsu_pic.picm_mken, io.lsu_pic.picm_rden) @[pic_ctrl.scala 124:50] - node pic_raddr_c1_clken = or(_T_19, io.clk_override) @[pic_ctrl.scala 124:73] - node pic_data_c1_clken = or(io.lsu_pic.picm_wren, io.clk_override) @[pic_ctrl.scala 125:50] - node _T_20 = and(waddr_intpriority_base_match, picm_wren_ff) @[pic_ctrl.scala 126:59] - node _T_21 = and(raddr_intpriority_base_match, picm_rden_ff) @[pic_ctrl.scala 126:108] - node _T_22 = or(_T_20, _T_21) @[pic_ctrl.scala 126:76] - node pic_pri_c1_clken = or(_T_22, io.clk_override) @[pic_ctrl.scala 126:124] - node _T_23 = and(waddr_intenable_base_match, picm_wren_ff) @[pic_ctrl.scala 127:57] - node _T_24 = and(raddr_intenable_base_match, picm_rden_ff) @[pic_ctrl.scala 127:104] - node _T_25 = or(_T_23, _T_24) @[pic_ctrl.scala 127:74] - node pic_int_c1_clken = or(_T_25, io.clk_override) @[pic_ctrl.scala 127:120] - node _T_26 = and(waddr_config_gw_base_match, picm_wren_ff) @[pic_ctrl.scala 128:59] - node _T_27 = and(raddr_config_gw_base_match, picm_rden_ff) @[pic_ctrl.scala 128:108] - node _T_28 = or(_T_26, _T_27) @[pic_ctrl.scala 128:76] - node gw_config_c1_clken = or(_T_28, io.clk_override) @[pic_ctrl.scala 128:124] + wire pic_raddr_c1_clk : Clock @[pic_ctrl.scala 95:42] + wire pic_data_c1_clk : Clock @[pic_ctrl.scala 96:42] + wire pic_pri_c1_clk : Clock @[pic_ctrl.scala 97:42] + wire pic_int_c1_clk : Clock @[pic_ctrl.scala 98:42] + wire gw_config_c1_clk : Clock @[pic_ctrl.scala 99:42] + reg _T : UInt, pic_raddr_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 101:56] + _T <= io.lsu_pic.picm_rdaddr @[pic_ctrl.scala 101:56] + picm_raddr_ff <= _T @[pic_ctrl.scala 101:46] + reg _T_1 : UInt, pic_data_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 102:57] + _T_1 <= io.lsu_pic.picm_wraddr @[pic_ctrl.scala 102:57] + picm_waddr_ff <= _T_1 @[pic_ctrl.scala 102:46] + reg _T_2 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 103:55] + _T_2 <= io.lsu_pic.picm_wren @[pic_ctrl.scala 103:55] + picm_wren_ff <= _T_2 @[pic_ctrl.scala 103:45] + reg _T_3 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 104:55] + _T_3 <= io.lsu_pic.picm_rden @[pic_ctrl.scala 104:55] + picm_rden_ff <= _T_3 @[pic_ctrl.scala 104:45] + reg _T_4 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 105:55] + _T_4 <= io.lsu_pic.picm_mken @[pic_ctrl.scala 105:55] + picm_mken_ff <= _T_4 @[pic_ctrl.scala 105:45] + reg _T_5 : UInt, pic_data_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 106:58] + _T_5 <= io.lsu_pic.picm_wr_data @[pic_ctrl.scala 106:58] + picm_wr_data_ff <= _T_5 @[pic_ctrl.scala 106:48] + node _T_6 = xor(picm_raddr_ff, UInt<32>("h0f00c2000")) @[pic_ctrl.scala 108:59] + node temp_raddr_intenable_base_match = not(_T_6) @[pic_ctrl.scala 108:43] + node _T_7 = bits(temp_raddr_intenable_base_match, 31, 7) @[pic_ctrl.scala 109:71] + node raddr_intenable_base_match = andr(_T_7) @[pic_ctrl.scala 109:89] + node _T_8 = bits(picm_raddr_ff, 31, 7) @[pic_ctrl.scala 111:53] + node raddr_intpriority_base_match = eq(_T_8, UInt<25>("h01e01800")) @[pic_ctrl.scala 111:71] + node _T_9 = bits(picm_raddr_ff, 31, 7) @[pic_ctrl.scala 112:53] + node raddr_config_gw_base_match = eq(_T_9, UInt<25>("h01e01880")) @[pic_ctrl.scala 112:71] + node _T_10 = bits(picm_raddr_ff, 31, 0) @[pic_ctrl.scala 113:53] + node raddr_config_pic_match = eq(_T_10, UInt<32>("h0f00c3000")) @[pic_ctrl.scala 113:71] + node _T_11 = bits(picm_raddr_ff, 31, 6) @[pic_ctrl.scala 114:53] + node addr_intpend_base_match = eq(_T_11, UInt<26>("h03c03040")) @[pic_ctrl.scala 114:71] + node _T_12 = bits(picm_waddr_ff, 31, 0) @[pic_ctrl.scala 116:53] + node waddr_config_pic_match = eq(_T_12, UInt<32>("h0f00c3000")) @[pic_ctrl.scala 116:71] + node _T_13 = bits(picm_waddr_ff, 31, 7) @[pic_ctrl.scala 117:53] + node addr_clear_gw_base_match = eq(_T_13, UInt<25>("h01e018a0")) @[pic_ctrl.scala 117:71] + node _T_14 = bits(picm_waddr_ff, 31, 7) @[pic_ctrl.scala 118:53] + node waddr_intpriority_base_match = eq(_T_14, UInt<25>("h01e01800")) @[pic_ctrl.scala 118:71] + node _T_15 = bits(picm_waddr_ff, 31, 7) @[pic_ctrl.scala 119:53] + node waddr_intenable_base_match = eq(_T_15, UInt<25>("h01e01840")) @[pic_ctrl.scala 119:71] + node _T_16 = bits(picm_waddr_ff, 31, 7) @[pic_ctrl.scala 120:53] + node waddr_config_gw_base_match = eq(_T_16, UInt<25>("h01e01880")) @[pic_ctrl.scala 120:71] + node _T_17 = and(picm_rden_ff, picm_wren_ff) @[pic_ctrl.scala 121:53] + node _T_18 = eq(picm_raddr_ff, picm_waddr_ff) @[pic_ctrl.scala 121:86] + node picm_bypass_ff = and(_T_17, _T_18) @[pic_ctrl.scala 121:68] + node _T_19 = or(io.lsu_pic.picm_mken, io.lsu_pic.picm_rden) @[pic_ctrl.scala 125:50] + node pic_raddr_c1_clken = or(_T_19, io.clk_override) @[pic_ctrl.scala 125:73] + node pic_data_c1_clken = or(io.lsu_pic.picm_wren, io.clk_override) @[pic_ctrl.scala 126:50] + node _T_20 = and(waddr_intpriority_base_match, picm_wren_ff) @[pic_ctrl.scala 127:59] + node _T_21 = and(raddr_intpriority_base_match, picm_rden_ff) @[pic_ctrl.scala 127:108] + node _T_22 = or(_T_20, _T_21) @[pic_ctrl.scala 127:76] + node pic_pri_c1_clken = or(_T_22, io.clk_override) @[pic_ctrl.scala 127:124] + node _T_23 = and(waddr_intenable_base_match, picm_wren_ff) @[pic_ctrl.scala 128:57] + node _T_24 = and(raddr_intenable_base_match, picm_rden_ff) @[pic_ctrl.scala 128:104] + node _T_25 = or(_T_23, _T_24) @[pic_ctrl.scala 128:74] + node pic_int_c1_clken = or(_T_25, io.clk_override) @[pic_ctrl.scala 128:120] + node _T_26 = and(waddr_config_gw_base_match, picm_wren_ff) @[pic_ctrl.scala 129:59] + node _T_27 = and(raddr_config_gw_base_match, picm_rden_ff) @[pic_ctrl.scala 129:108] + node _T_28 = or(_T_26, _T_27) @[pic_ctrl.scala 129:76] + node gw_config_c1_clken = or(_T_28, io.clk_override) @[pic_ctrl.scala 129:124] inst rvclkhdr of rvclkhdr_824 @[lib.scala 327:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 328:17] rvclkhdr.io.en <= pic_raddr_c1_clken @[lib.scala 329:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - pic_raddr_c1_clk <= rvclkhdr.io.l1clk @[pic_ctrl.scala 131:21] + pic_raddr_c1_clk <= rvclkhdr.io.l1clk @[pic_ctrl.scala 132:21] inst rvclkhdr_1 of rvclkhdr_825 @[lib.scala 327:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 328:17] rvclkhdr_1.io.en <= pic_data_c1_clken @[lib.scala 329:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - pic_data_c1_clk <= rvclkhdr_1.io.l1clk @[pic_ctrl.scala 132:21] - node _T_29 = bits(pic_pri_c1_clken, 0, 0) @[pic_ctrl.scala 133:56] + pic_data_c1_clk <= rvclkhdr_1.io.l1clk @[pic_ctrl.scala 133:21] + node _T_29 = bits(pic_pri_c1_clken, 0, 0) @[pic_ctrl.scala 134:56] inst rvclkhdr_2 of rvclkhdr_826 @[lib.scala 327:22] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[lib.scala 328:17] rvclkhdr_2.io.en <= _T_29 @[lib.scala 329:16] rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - pic_pri_c1_clk <= rvclkhdr_2.io.l1clk @[pic_ctrl.scala 133:21] - node _T_30 = bits(pic_int_c1_clken, 0, 0) @[pic_ctrl.scala 134:56] + pic_pri_c1_clk <= rvclkhdr_2.io.l1clk @[pic_ctrl.scala 134:21] + node _T_30 = bits(pic_int_c1_clken, 0, 0) @[pic_ctrl.scala 135:56] inst rvclkhdr_3 of rvclkhdr_827 @[lib.scala 327:22] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[lib.scala 328:17] rvclkhdr_3.io.en <= _T_30 @[lib.scala 329:16] rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - pic_int_c1_clk <= rvclkhdr_3.io.l1clk @[pic_ctrl.scala 134:21] - node _T_31 = bits(gw_config_c1_clken, 0, 0) @[pic_ctrl.scala 135:58] + pic_int_c1_clk <= rvclkhdr_3.io.l1clk @[pic_ctrl.scala 135:21] + node _T_31 = bits(gw_config_c1_clken, 0, 0) @[pic_ctrl.scala 136:58] inst rvclkhdr_4 of rvclkhdr_828 @[lib.scala 327:22] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset rvclkhdr_4.io.clk <= clock @[lib.scala 328:17] rvclkhdr_4.io.en <= _T_31 @[lib.scala 329:16] rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - gw_config_c1_clk <= rvclkhdr_4.io.l1clk @[pic_ctrl.scala 135:21] - node _T_32 = bits(io.extintsrc_req, 31, 1) @[pic_ctrl.scala 138:58] + gw_config_c1_clk <= rvclkhdr_4.io.l1clk @[pic_ctrl.scala 136:21] + node _T_32 = bits(io.extintsrc_req, 31, 1) @[pic_ctrl.scala 139:58] reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 21:81] _T_33 <= _T_32 @[lib.scala 21:81] reg _T_34 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 21:58] _T_34 <= _T_33 @[lib.scala 21:58] - node _T_35 = bits(io.extintsrc_req, 0, 0) @[pic_ctrl.scala 138:113] + node _T_35 = bits(io.extintsrc_req, 0, 0) @[pic_ctrl.scala 139:113] node extintsrc_req_sync = cat(_T_34, _T_35) @[Cat.scala 29:58] - node _T_36 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_37 = eq(_T_36, UInt<1>("h01")) @[pic_ctrl.scala 140:139] - node _T_38 = and(waddr_intpriority_base_match, _T_37) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_1 = and(_T_38, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_39 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_40 = eq(_T_39, UInt<2>("h02")) @[pic_ctrl.scala 140:139] - node _T_41 = and(waddr_intpriority_base_match, _T_40) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_2 = and(_T_41, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_42 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_43 = eq(_T_42, UInt<2>("h03")) @[pic_ctrl.scala 140:139] - node _T_44 = and(waddr_intpriority_base_match, _T_43) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_3 = and(_T_44, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_45 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_46 = eq(_T_45, UInt<3>("h04")) @[pic_ctrl.scala 140:139] - node _T_47 = and(waddr_intpriority_base_match, _T_46) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_4 = and(_T_47, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_48 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_49 = eq(_T_48, UInt<3>("h05")) @[pic_ctrl.scala 140:139] - node _T_50 = and(waddr_intpriority_base_match, _T_49) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_5 = and(_T_50, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_51 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_52 = eq(_T_51, UInt<3>("h06")) @[pic_ctrl.scala 140:139] - node _T_53 = and(waddr_intpriority_base_match, _T_52) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_6 = and(_T_53, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_54 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_55 = eq(_T_54, UInt<3>("h07")) @[pic_ctrl.scala 140:139] - node _T_56 = and(waddr_intpriority_base_match, _T_55) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_7 = and(_T_56, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_57 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_58 = eq(_T_57, UInt<4>("h08")) @[pic_ctrl.scala 140:139] - node _T_59 = and(waddr_intpriority_base_match, _T_58) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_8 = and(_T_59, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_60 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_61 = eq(_T_60, UInt<4>("h09")) @[pic_ctrl.scala 140:139] - node _T_62 = and(waddr_intpriority_base_match, _T_61) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_9 = and(_T_62, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_63 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_64 = eq(_T_63, UInt<4>("h0a")) @[pic_ctrl.scala 140:139] - node _T_65 = and(waddr_intpriority_base_match, _T_64) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_10 = and(_T_65, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_66 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_67 = eq(_T_66, UInt<4>("h0b")) @[pic_ctrl.scala 140:139] - node _T_68 = and(waddr_intpriority_base_match, _T_67) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_11 = and(_T_68, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_69 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_70 = eq(_T_69, UInt<4>("h0c")) @[pic_ctrl.scala 140:139] - node _T_71 = and(waddr_intpriority_base_match, _T_70) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_12 = and(_T_71, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_72 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_73 = eq(_T_72, UInt<4>("h0d")) @[pic_ctrl.scala 140:139] - node _T_74 = and(waddr_intpriority_base_match, _T_73) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_13 = and(_T_74, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_75 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_76 = eq(_T_75, UInt<4>("h0e")) @[pic_ctrl.scala 140:139] - node _T_77 = and(waddr_intpriority_base_match, _T_76) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_14 = and(_T_77, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_78 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_79 = eq(_T_78, UInt<4>("h0f")) @[pic_ctrl.scala 140:139] - node _T_80 = and(waddr_intpriority_base_match, _T_79) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_15 = and(_T_80, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_81 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_82 = eq(_T_81, UInt<5>("h010")) @[pic_ctrl.scala 140:139] - node _T_83 = and(waddr_intpriority_base_match, _T_82) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_16 = and(_T_83, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_84 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_85 = eq(_T_84, UInt<5>("h011")) @[pic_ctrl.scala 140:139] - node _T_86 = and(waddr_intpriority_base_match, _T_85) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_17 = and(_T_86, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_87 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_88 = eq(_T_87, UInt<5>("h012")) @[pic_ctrl.scala 140:139] - node _T_89 = and(waddr_intpriority_base_match, _T_88) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_18 = and(_T_89, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_90 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_91 = eq(_T_90, UInt<5>("h013")) @[pic_ctrl.scala 140:139] - node _T_92 = and(waddr_intpriority_base_match, _T_91) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_19 = and(_T_92, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_93 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_94 = eq(_T_93, UInt<5>("h014")) @[pic_ctrl.scala 140:139] - node _T_95 = and(waddr_intpriority_base_match, _T_94) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_20 = and(_T_95, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_96 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_97 = eq(_T_96, UInt<5>("h015")) @[pic_ctrl.scala 140:139] - node _T_98 = and(waddr_intpriority_base_match, _T_97) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_21 = and(_T_98, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_99 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_100 = eq(_T_99, UInt<5>("h016")) @[pic_ctrl.scala 140:139] - node _T_101 = and(waddr_intpriority_base_match, _T_100) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_22 = and(_T_101, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_102 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_103 = eq(_T_102, UInt<5>("h017")) @[pic_ctrl.scala 140:139] - node _T_104 = and(waddr_intpriority_base_match, _T_103) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_23 = and(_T_104, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_105 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_106 = eq(_T_105, UInt<5>("h018")) @[pic_ctrl.scala 140:139] - node _T_107 = and(waddr_intpriority_base_match, _T_106) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_24 = and(_T_107, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_108 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_109 = eq(_T_108, UInt<5>("h019")) @[pic_ctrl.scala 140:139] - node _T_110 = and(waddr_intpriority_base_match, _T_109) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_25 = and(_T_110, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_111 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_112 = eq(_T_111, UInt<5>("h01a")) @[pic_ctrl.scala 140:139] - node _T_113 = and(waddr_intpriority_base_match, _T_112) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_26 = and(_T_113, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_114 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_115 = eq(_T_114, UInt<5>("h01b")) @[pic_ctrl.scala 140:139] - node _T_116 = and(waddr_intpriority_base_match, _T_115) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_27 = and(_T_116, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_117 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_118 = eq(_T_117, UInt<5>("h01c")) @[pic_ctrl.scala 140:139] - node _T_119 = and(waddr_intpriority_base_match, _T_118) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_28 = and(_T_119, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_120 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_121 = eq(_T_120, UInt<5>("h01d")) @[pic_ctrl.scala 140:139] - node _T_122 = and(waddr_intpriority_base_match, _T_121) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_29 = and(_T_122, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_123 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_124 = eq(_T_123, UInt<5>("h01e")) @[pic_ctrl.scala 140:139] - node _T_125 = and(waddr_intpriority_base_match, _T_124) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_30 = and(_T_125, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_126 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 140:122] - node _T_127 = eq(_T_126, UInt<5>("h01f")) @[pic_ctrl.scala 140:139] - node _T_128 = and(waddr_intpriority_base_match, _T_127) @[pic_ctrl.scala 140:106] - node intpriority_reg_we_31 = and(_T_128, picm_wren_ff) @[pic_ctrl.scala 140:153] - node _T_129 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_130 = eq(_T_129, UInt<1>("h01")) @[pic_ctrl.scala 141:139] - node _T_131 = and(raddr_intpriority_base_match, _T_130) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_1 = and(_T_131, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_132 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_133 = eq(_T_132, UInt<2>("h02")) @[pic_ctrl.scala 141:139] - node _T_134 = and(raddr_intpriority_base_match, _T_133) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_2 = and(_T_134, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_135 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_136 = eq(_T_135, UInt<2>("h03")) @[pic_ctrl.scala 141:139] - node _T_137 = and(raddr_intpriority_base_match, _T_136) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_3 = and(_T_137, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_138 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_139 = eq(_T_138, UInt<3>("h04")) @[pic_ctrl.scala 141:139] - node _T_140 = and(raddr_intpriority_base_match, _T_139) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_4 = and(_T_140, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_141 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_142 = eq(_T_141, UInt<3>("h05")) @[pic_ctrl.scala 141:139] - node _T_143 = and(raddr_intpriority_base_match, _T_142) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_5 = and(_T_143, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_144 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_145 = eq(_T_144, UInt<3>("h06")) @[pic_ctrl.scala 141:139] - node _T_146 = and(raddr_intpriority_base_match, _T_145) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_6 = and(_T_146, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_147 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_148 = eq(_T_147, UInt<3>("h07")) @[pic_ctrl.scala 141:139] - node _T_149 = and(raddr_intpriority_base_match, _T_148) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_7 = and(_T_149, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_150 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_151 = eq(_T_150, UInt<4>("h08")) @[pic_ctrl.scala 141:139] - node _T_152 = and(raddr_intpriority_base_match, _T_151) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_8 = and(_T_152, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_153 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_154 = eq(_T_153, UInt<4>("h09")) @[pic_ctrl.scala 141:139] - node _T_155 = and(raddr_intpriority_base_match, _T_154) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_9 = and(_T_155, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_156 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_157 = eq(_T_156, UInt<4>("h0a")) @[pic_ctrl.scala 141:139] - node _T_158 = and(raddr_intpriority_base_match, _T_157) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_10 = and(_T_158, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_159 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_160 = eq(_T_159, UInt<4>("h0b")) @[pic_ctrl.scala 141:139] - node _T_161 = and(raddr_intpriority_base_match, _T_160) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_11 = and(_T_161, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_162 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_163 = eq(_T_162, UInt<4>("h0c")) @[pic_ctrl.scala 141:139] - node _T_164 = and(raddr_intpriority_base_match, _T_163) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_12 = and(_T_164, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_165 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_166 = eq(_T_165, UInt<4>("h0d")) @[pic_ctrl.scala 141:139] - node _T_167 = and(raddr_intpriority_base_match, _T_166) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_13 = and(_T_167, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_168 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_169 = eq(_T_168, UInt<4>("h0e")) @[pic_ctrl.scala 141:139] - node _T_170 = and(raddr_intpriority_base_match, _T_169) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_14 = and(_T_170, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_171 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_172 = eq(_T_171, UInt<4>("h0f")) @[pic_ctrl.scala 141:139] - node _T_173 = and(raddr_intpriority_base_match, _T_172) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_15 = and(_T_173, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_174 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_175 = eq(_T_174, UInt<5>("h010")) @[pic_ctrl.scala 141:139] - node _T_176 = and(raddr_intpriority_base_match, _T_175) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_16 = and(_T_176, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_177 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_178 = eq(_T_177, UInt<5>("h011")) @[pic_ctrl.scala 141:139] - node _T_179 = and(raddr_intpriority_base_match, _T_178) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_17 = and(_T_179, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_180 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_181 = eq(_T_180, UInt<5>("h012")) @[pic_ctrl.scala 141:139] - node _T_182 = and(raddr_intpriority_base_match, _T_181) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_18 = and(_T_182, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_183 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_184 = eq(_T_183, UInt<5>("h013")) @[pic_ctrl.scala 141:139] - node _T_185 = and(raddr_intpriority_base_match, _T_184) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_19 = and(_T_185, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_186 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_187 = eq(_T_186, UInt<5>("h014")) @[pic_ctrl.scala 141:139] - node _T_188 = and(raddr_intpriority_base_match, _T_187) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_20 = and(_T_188, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_189 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_190 = eq(_T_189, UInt<5>("h015")) @[pic_ctrl.scala 141:139] - node _T_191 = and(raddr_intpriority_base_match, _T_190) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_21 = and(_T_191, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_192 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_193 = eq(_T_192, UInt<5>("h016")) @[pic_ctrl.scala 141:139] - node _T_194 = and(raddr_intpriority_base_match, _T_193) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_22 = and(_T_194, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_195 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_196 = eq(_T_195, UInt<5>("h017")) @[pic_ctrl.scala 141:139] - node _T_197 = and(raddr_intpriority_base_match, _T_196) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_23 = and(_T_197, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_198 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_199 = eq(_T_198, UInt<5>("h018")) @[pic_ctrl.scala 141:139] - node _T_200 = and(raddr_intpriority_base_match, _T_199) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_24 = and(_T_200, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_201 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_202 = eq(_T_201, UInt<5>("h019")) @[pic_ctrl.scala 141:139] - node _T_203 = and(raddr_intpriority_base_match, _T_202) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_25 = and(_T_203, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_204 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_205 = eq(_T_204, UInt<5>("h01a")) @[pic_ctrl.scala 141:139] - node _T_206 = and(raddr_intpriority_base_match, _T_205) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_26 = and(_T_206, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_207 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_208 = eq(_T_207, UInt<5>("h01b")) @[pic_ctrl.scala 141:139] - node _T_209 = and(raddr_intpriority_base_match, _T_208) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_27 = and(_T_209, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_210 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_211 = eq(_T_210, UInt<5>("h01c")) @[pic_ctrl.scala 141:139] - node _T_212 = and(raddr_intpriority_base_match, _T_211) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_28 = and(_T_212, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_213 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_214 = eq(_T_213, UInt<5>("h01d")) @[pic_ctrl.scala 141:139] - node _T_215 = and(raddr_intpriority_base_match, _T_214) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_29 = and(_T_215, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_216 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_217 = eq(_T_216, UInt<5>("h01e")) @[pic_ctrl.scala 141:139] - node _T_218 = and(raddr_intpriority_base_match, _T_217) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_30 = and(_T_218, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_219 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 141:122] - node _T_220 = eq(_T_219, UInt<5>("h01f")) @[pic_ctrl.scala 141:139] - node _T_221 = and(raddr_intpriority_base_match, _T_220) @[pic_ctrl.scala 141:106] - node intpriority_reg_re_31 = and(_T_221, picm_rden_ff) @[pic_ctrl.scala 141:153] - node _T_222 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_223 = eq(_T_222, UInt<1>("h01")) @[pic_ctrl.scala 142:139] - node _T_224 = and(waddr_intenable_base_match, _T_223) @[pic_ctrl.scala 142:106] - node intenable_reg_we_1 = and(_T_224, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_225 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_226 = eq(_T_225, UInt<2>("h02")) @[pic_ctrl.scala 142:139] - node _T_227 = and(waddr_intenable_base_match, _T_226) @[pic_ctrl.scala 142:106] - node intenable_reg_we_2 = and(_T_227, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_228 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_229 = eq(_T_228, UInt<2>("h03")) @[pic_ctrl.scala 142:139] - node _T_230 = and(waddr_intenable_base_match, _T_229) @[pic_ctrl.scala 142:106] - node intenable_reg_we_3 = and(_T_230, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_231 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_232 = eq(_T_231, UInt<3>("h04")) @[pic_ctrl.scala 142:139] - node _T_233 = and(waddr_intenable_base_match, _T_232) @[pic_ctrl.scala 142:106] - node intenable_reg_we_4 = and(_T_233, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_234 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_235 = eq(_T_234, UInt<3>("h05")) @[pic_ctrl.scala 142:139] - node _T_236 = and(waddr_intenable_base_match, _T_235) @[pic_ctrl.scala 142:106] - node intenable_reg_we_5 = and(_T_236, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_237 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_238 = eq(_T_237, UInt<3>("h06")) @[pic_ctrl.scala 142:139] - node _T_239 = and(waddr_intenable_base_match, _T_238) @[pic_ctrl.scala 142:106] - node intenable_reg_we_6 = and(_T_239, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_240 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_241 = eq(_T_240, UInt<3>("h07")) @[pic_ctrl.scala 142:139] - node _T_242 = and(waddr_intenable_base_match, _T_241) @[pic_ctrl.scala 142:106] - node intenable_reg_we_7 = and(_T_242, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_243 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_244 = eq(_T_243, UInt<4>("h08")) @[pic_ctrl.scala 142:139] - node _T_245 = and(waddr_intenable_base_match, _T_244) @[pic_ctrl.scala 142:106] - node intenable_reg_we_8 = and(_T_245, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_246 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_247 = eq(_T_246, UInt<4>("h09")) @[pic_ctrl.scala 142:139] - node _T_248 = and(waddr_intenable_base_match, _T_247) @[pic_ctrl.scala 142:106] - node intenable_reg_we_9 = and(_T_248, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_249 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_250 = eq(_T_249, UInt<4>("h0a")) @[pic_ctrl.scala 142:139] - node _T_251 = and(waddr_intenable_base_match, _T_250) @[pic_ctrl.scala 142:106] - node intenable_reg_we_10 = and(_T_251, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_252 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_253 = eq(_T_252, UInt<4>("h0b")) @[pic_ctrl.scala 142:139] - node _T_254 = and(waddr_intenable_base_match, _T_253) @[pic_ctrl.scala 142:106] - node intenable_reg_we_11 = and(_T_254, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_255 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_256 = eq(_T_255, UInt<4>("h0c")) @[pic_ctrl.scala 142:139] - node _T_257 = and(waddr_intenable_base_match, _T_256) @[pic_ctrl.scala 142:106] - node intenable_reg_we_12 = and(_T_257, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_258 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_259 = eq(_T_258, UInt<4>("h0d")) @[pic_ctrl.scala 142:139] - node _T_260 = and(waddr_intenable_base_match, _T_259) @[pic_ctrl.scala 142:106] - node intenable_reg_we_13 = and(_T_260, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_261 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_262 = eq(_T_261, UInt<4>("h0e")) @[pic_ctrl.scala 142:139] - node _T_263 = and(waddr_intenable_base_match, _T_262) @[pic_ctrl.scala 142:106] - node intenable_reg_we_14 = and(_T_263, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_264 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_265 = eq(_T_264, UInt<4>("h0f")) @[pic_ctrl.scala 142:139] - node _T_266 = and(waddr_intenable_base_match, _T_265) @[pic_ctrl.scala 142:106] - node intenable_reg_we_15 = and(_T_266, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_267 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_268 = eq(_T_267, UInt<5>("h010")) @[pic_ctrl.scala 142:139] - node _T_269 = and(waddr_intenable_base_match, _T_268) @[pic_ctrl.scala 142:106] - node intenable_reg_we_16 = and(_T_269, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_270 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_271 = eq(_T_270, UInt<5>("h011")) @[pic_ctrl.scala 142:139] - node _T_272 = and(waddr_intenable_base_match, _T_271) @[pic_ctrl.scala 142:106] - node intenable_reg_we_17 = and(_T_272, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_273 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_274 = eq(_T_273, UInt<5>("h012")) @[pic_ctrl.scala 142:139] - node _T_275 = and(waddr_intenable_base_match, _T_274) @[pic_ctrl.scala 142:106] - node intenable_reg_we_18 = and(_T_275, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_276 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_277 = eq(_T_276, UInt<5>("h013")) @[pic_ctrl.scala 142:139] - node _T_278 = and(waddr_intenable_base_match, _T_277) @[pic_ctrl.scala 142:106] - node intenable_reg_we_19 = and(_T_278, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_279 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_280 = eq(_T_279, UInt<5>("h014")) @[pic_ctrl.scala 142:139] - node _T_281 = and(waddr_intenable_base_match, _T_280) @[pic_ctrl.scala 142:106] - node intenable_reg_we_20 = and(_T_281, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_282 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_283 = eq(_T_282, UInt<5>("h015")) @[pic_ctrl.scala 142:139] - node _T_284 = and(waddr_intenable_base_match, _T_283) @[pic_ctrl.scala 142:106] - node intenable_reg_we_21 = and(_T_284, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_285 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_286 = eq(_T_285, UInt<5>("h016")) @[pic_ctrl.scala 142:139] - node _T_287 = and(waddr_intenable_base_match, _T_286) @[pic_ctrl.scala 142:106] - node intenable_reg_we_22 = and(_T_287, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_288 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_289 = eq(_T_288, UInt<5>("h017")) @[pic_ctrl.scala 142:139] - node _T_290 = and(waddr_intenable_base_match, _T_289) @[pic_ctrl.scala 142:106] - node intenable_reg_we_23 = and(_T_290, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_291 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_292 = eq(_T_291, UInt<5>("h018")) @[pic_ctrl.scala 142:139] - node _T_293 = and(waddr_intenable_base_match, _T_292) @[pic_ctrl.scala 142:106] - node intenable_reg_we_24 = and(_T_293, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_294 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_295 = eq(_T_294, UInt<5>("h019")) @[pic_ctrl.scala 142:139] - node _T_296 = and(waddr_intenable_base_match, _T_295) @[pic_ctrl.scala 142:106] - node intenable_reg_we_25 = and(_T_296, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_297 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_298 = eq(_T_297, UInt<5>("h01a")) @[pic_ctrl.scala 142:139] - node _T_299 = and(waddr_intenable_base_match, _T_298) @[pic_ctrl.scala 142:106] - node intenable_reg_we_26 = and(_T_299, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_300 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_301 = eq(_T_300, UInt<5>("h01b")) @[pic_ctrl.scala 142:139] - node _T_302 = and(waddr_intenable_base_match, _T_301) @[pic_ctrl.scala 142:106] - node intenable_reg_we_27 = and(_T_302, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_303 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_304 = eq(_T_303, UInt<5>("h01c")) @[pic_ctrl.scala 142:139] - node _T_305 = and(waddr_intenable_base_match, _T_304) @[pic_ctrl.scala 142:106] - node intenable_reg_we_28 = and(_T_305, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_306 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_307 = eq(_T_306, UInt<5>("h01d")) @[pic_ctrl.scala 142:139] - node _T_308 = and(waddr_intenable_base_match, _T_307) @[pic_ctrl.scala 142:106] - node intenable_reg_we_29 = and(_T_308, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_309 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_310 = eq(_T_309, UInt<5>("h01e")) @[pic_ctrl.scala 142:139] - node _T_311 = and(waddr_intenable_base_match, _T_310) @[pic_ctrl.scala 142:106] - node intenable_reg_we_30 = and(_T_311, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_312 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 142:122] - node _T_313 = eq(_T_312, UInt<5>("h01f")) @[pic_ctrl.scala 142:139] - node _T_314 = and(waddr_intenable_base_match, _T_313) @[pic_ctrl.scala 142:106] - node intenable_reg_we_31 = and(_T_314, picm_wren_ff) @[pic_ctrl.scala 142:153] - node _T_315 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_316 = eq(_T_315, UInt<1>("h01")) @[pic_ctrl.scala 143:139] - node _T_317 = and(raddr_intenable_base_match, _T_316) @[pic_ctrl.scala 143:106] - node intenable_reg_re_1 = and(_T_317, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_318 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_319 = eq(_T_318, UInt<2>("h02")) @[pic_ctrl.scala 143:139] - node _T_320 = and(raddr_intenable_base_match, _T_319) @[pic_ctrl.scala 143:106] - node intenable_reg_re_2 = and(_T_320, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_321 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_322 = eq(_T_321, UInt<2>("h03")) @[pic_ctrl.scala 143:139] - node _T_323 = and(raddr_intenable_base_match, _T_322) @[pic_ctrl.scala 143:106] - node intenable_reg_re_3 = and(_T_323, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_324 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_325 = eq(_T_324, UInt<3>("h04")) @[pic_ctrl.scala 143:139] - node _T_326 = and(raddr_intenable_base_match, _T_325) @[pic_ctrl.scala 143:106] - node intenable_reg_re_4 = and(_T_326, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_327 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_328 = eq(_T_327, UInt<3>("h05")) @[pic_ctrl.scala 143:139] - node _T_329 = and(raddr_intenable_base_match, _T_328) @[pic_ctrl.scala 143:106] - node intenable_reg_re_5 = and(_T_329, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_330 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_331 = eq(_T_330, UInt<3>("h06")) @[pic_ctrl.scala 143:139] - node _T_332 = and(raddr_intenable_base_match, _T_331) @[pic_ctrl.scala 143:106] - node intenable_reg_re_6 = and(_T_332, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_333 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_334 = eq(_T_333, UInt<3>("h07")) @[pic_ctrl.scala 143:139] - node _T_335 = and(raddr_intenable_base_match, _T_334) @[pic_ctrl.scala 143:106] - node intenable_reg_re_7 = and(_T_335, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_336 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_337 = eq(_T_336, UInt<4>("h08")) @[pic_ctrl.scala 143:139] - node _T_338 = and(raddr_intenable_base_match, _T_337) @[pic_ctrl.scala 143:106] - node intenable_reg_re_8 = and(_T_338, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_339 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_340 = eq(_T_339, UInt<4>("h09")) @[pic_ctrl.scala 143:139] - node _T_341 = and(raddr_intenable_base_match, _T_340) @[pic_ctrl.scala 143:106] - node intenable_reg_re_9 = and(_T_341, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_342 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_343 = eq(_T_342, UInt<4>("h0a")) @[pic_ctrl.scala 143:139] - node _T_344 = and(raddr_intenable_base_match, _T_343) @[pic_ctrl.scala 143:106] - node intenable_reg_re_10 = and(_T_344, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_345 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_346 = eq(_T_345, UInt<4>("h0b")) @[pic_ctrl.scala 143:139] - node _T_347 = and(raddr_intenable_base_match, _T_346) @[pic_ctrl.scala 143:106] - node intenable_reg_re_11 = and(_T_347, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_348 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_349 = eq(_T_348, UInt<4>("h0c")) @[pic_ctrl.scala 143:139] - node _T_350 = and(raddr_intenable_base_match, _T_349) @[pic_ctrl.scala 143:106] - node intenable_reg_re_12 = and(_T_350, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_351 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_352 = eq(_T_351, UInt<4>("h0d")) @[pic_ctrl.scala 143:139] - node _T_353 = and(raddr_intenable_base_match, _T_352) @[pic_ctrl.scala 143:106] - node intenable_reg_re_13 = and(_T_353, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_354 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_355 = eq(_T_354, UInt<4>("h0e")) @[pic_ctrl.scala 143:139] - node _T_356 = and(raddr_intenable_base_match, _T_355) @[pic_ctrl.scala 143:106] - node intenable_reg_re_14 = and(_T_356, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_357 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_358 = eq(_T_357, UInt<4>("h0f")) @[pic_ctrl.scala 143:139] - node _T_359 = and(raddr_intenable_base_match, _T_358) @[pic_ctrl.scala 143:106] - node intenable_reg_re_15 = and(_T_359, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_360 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_361 = eq(_T_360, UInt<5>("h010")) @[pic_ctrl.scala 143:139] - node _T_362 = and(raddr_intenable_base_match, _T_361) @[pic_ctrl.scala 143:106] - node intenable_reg_re_16 = and(_T_362, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_363 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_364 = eq(_T_363, UInt<5>("h011")) @[pic_ctrl.scala 143:139] - node _T_365 = and(raddr_intenable_base_match, _T_364) @[pic_ctrl.scala 143:106] - node intenable_reg_re_17 = and(_T_365, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_366 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_367 = eq(_T_366, UInt<5>("h012")) @[pic_ctrl.scala 143:139] - node _T_368 = and(raddr_intenable_base_match, _T_367) @[pic_ctrl.scala 143:106] - node intenable_reg_re_18 = and(_T_368, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_369 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_370 = eq(_T_369, UInt<5>("h013")) @[pic_ctrl.scala 143:139] - node _T_371 = and(raddr_intenable_base_match, _T_370) @[pic_ctrl.scala 143:106] - node intenable_reg_re_19 = and(_T_371, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_372 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_373 = eq(_T_372, UInt<5>("h014")) @[pic_ctrl.scala 143:139] - node _T_374 = and(raddr_intenable_base_match, _T_373) @[pic_ctrl.scala 143:106] - node intenable_reg_re_20 = and(_T_374, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_375 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_376 = eq(_T_375, UInt<5>("h015")) @[pic_ctrl.scala 143:139] - node _T_377 = and(raddr_intenable_base_match, _T_376) @[pic_ctrl.scala 143:106] - node intenable_reg_re_21 = and(_T_377, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_378 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_379 = eq(_T_378, UInt<5>("h016")) @[pic_ctrl.scala 143:139] - node _T_380 = and(raddr_intenable_base_match, _T_379) @[pic_ctrl.scala 143:106] - node intenable_reg_re_22 = and(_T_380, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_381 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_382 = eq(_T_381, UInt<5>("h017")) @[pic_ctrl.scala 143:139] - node _T_383 = and(raddr_intenable_base_match, _T_382) @[pic_ctrl.scala 143:106] - node intenable_reg_re_23 = and(_T_383, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_384 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_385 = eq(_T_384, UInt<5>("h018")) @[pic_ctrl.scala 143:139] - node _T_386 = and(raddr_intenable_base_match, _T_385) @[pic_ctrl.scala 143:106] - node intenable_reg_re_24 = and(_T_386, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_387 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_388 = eq(_T_387, UInt<5>("h019")) @[pic_ctrl.scala 143:139] - node _T_389 = and(raddr_intenable_base_match, _T_388) @[pic_ctrl.scala 143:106] - node intenable_reg_re_25 = and(_T_389, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_390 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_391 = eq(_T_390, UInt<5>("h01a")) @[pic_ctrl.scala 143:139] - node _T_392 = and(raddr_intenable_base_match, _T_391) @[pic_ctrl.scala 143:106] - node intenable_reg_re_26 = and(_T_392, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_393 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_394 = eq(_T_393, UInt<5>("h01b")) @[pic_ctrl.scala 143:139] - node _T_395 = and(raddr_intenable_base_match, _T_394) @[pic_ctrl.scala 143:106] - node intenable_reg_re_27 = and(_T_395, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_396 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_397 = eq(_T_396, UInt<5>("h01c")) @[pic_ctrl.scala 143:139] - node _T_398 = and(raddr_intenable_base_match, _T_397) @[pic_ctrl.scala 143:106] - node intenable_reg_re_28 = and(_T_398, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_399 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_400 = eq(_T_399, UInt<5>("h01d")) @[pic_ctrl.scala 143:139] - node _T_401 = and(raddr_intenable_base_match, _T_400) @[pic_ctrl.scala 143:106] - node intenable_reg_re_29 = and(_T_401, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_402 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_403 = eq(_T_402, UInt<5>("h01e")) @[pic_ctrl.scala 143:139] - node _T_404 = and(raddr_intenable_base_match, _T_403) @[pic_ctrl.scala 143:106] - node intenable_reg_re_30 = and(_T_404, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_405 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 143:122] - node _T_406 = eq(_T_405, UInt<5>("h01f")) @[pic_ctrl.scala 143:139] - node _T_407 = and(raddr_intenable_base_match, _T_406) @[pic_ctrl.scala 143:106] - node intenable_reg_re_31 = and(_T_407, picm_rden_ff) @[pic_ctrl.scala 143:153] - node _T_408 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_409 = eq(_T_408, UInt<1>("h01")) @[pic_ctrl.scala 144:139] - node _T_410 = and(waddr_config_gw_base_match, _T_409) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_1 = and(_T_410, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_411 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_412 = eq(_T_411, UInt<2>("h02")) @[pic_ctrl.scala 144:139] - node _T_413 = and(waddr_config_gw_base_match, _T_412) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_2 = and(_T_413, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_414 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_415 = eq(_T_414, UInt<2>("h03")) @[pic_ctrl.scala 144:139] - node _T_416 = and(waddr_config_gw_base_match, _T_415) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_3 = and(_T_416, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_417 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_418 = eq(_T_417, UInt<3>("h04")) @[pic_ctrl.scala 144:139] - node _T_419 = and(waddr_config_gw_base_match, _T_418) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_4 = and(_T_419, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_420 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_421 = eq(_T_420, UInt<3>("h05")) @[pic_ctrl.scala 144:139] - node _T_422 = and(waddr_config_gw_base_match, _T_421) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_5 = and(_T_422, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_423 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_424 = eq(_T_423, UInt<3>("h06")) @[pic_ctrl.scala 144:139] - node _T_425 = and(waddr_config_gw_base_match, _T_424) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_6 = and(_T_425, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_426 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_427 = eq(_T_426, UInt<3>("h07")) @[pic_ctrl.scala 144:139] - node _T_428 = and(waddr_config_gw_base_match, _T_427) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_7 = and(_T_428, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_429 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_430 = eq(_T_429, UInt<4>("h08")) @[pic_ctrl.scala 144:139] - node _T_431 = and(waddr_config_gw_base_match, _T_430) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_8 = and(_T_431, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_432 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_433 = eq(_T_432, UInt<4>("h09")) @[pic_ctrl.scala 144:139] - node _T_434 = and(waddr_config_gw_base_match, _T_433) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_9 = and(_T_434, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_435 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_436 = eq(_T_435, UInt<4>("h0a")) @[pic_ctrl.scala 144:139] - node _T_437 = and(waddr_config_gw_base_match, _T_436) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_10 = and(_T_437, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_438 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_439 = eq(_T_438, UInt<4>("h0b")) @[pic_ctrl.scala 144:139] - node _T_440 = and(waddr_config_gw_base_match, _T_439) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_11 = and(_T_440, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_441 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_442 = eq(_T_441, UInt<4>("h0c")) @[pic_ctrl.scala 144:139] - node _T_443 = and(waddr_config_gw_base_match, _T_442) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_12 = and(_T_443, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_444 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_445 = eq(_T_444, UInt<4>("h0d")) @[pic_ctrl.scala 144:139] - node _T_446 = and(waddr_config_gw_base_match, _T_445) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_13 = and(_T_446, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_447 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_448 = eq(_T_447, UInt<4>("h0e")) @[pic_ctrl.scala 144:139] - node _T_449 = and(waddr_config_gw_base_match, _T_448) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_14 = and(_T_449, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_450 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_451 = eq(_T_450, UInt<4>("h0f")) @[pic_ctrl.scala 144:139] - node _T_452 = and(waddr_config_gw_base_match, _T_451) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_15 = and(_T_452, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_453 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_454 = eq(_T_453, UInt<5>("h010")) @[pic_ctrl.scala 144:139] - node _T_455 = and(waddr_config_gw_base_match, _T_454) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_16 = and(_T_455, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_456 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_457 = eq(_T_456, UInt<5>("h011")) @[pic_ctrl.scala 144:139] - node _T_458 = and(waddr_config_gw_base_match, _T_457) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_17 = and(_T_458, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_459 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_460 = eq(_T_459, UInt<5>("h012")) @[pic_ctrl.scala 144:139] - node _T_461 = and(waddr_config_gw_base_match, _T_460) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_18 = and(_T_461, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_462 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_463 = eq(_T_462, UInt<5>("h013")) @[pic_ctrl.scala 144:139] - node _T_464 = and(waddr_config_gw_base_match, _T_463) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_19 = and(_T_464, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_465 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_466 = eq(_T_465, UInt<5>("h014")) @[pic_ctrl.scala 144:139] - node _T_467 = and(waddr_config_gw_base_match, _T_466) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_20 = and(_T_467, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_468 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_469 = eq(_T_468, UInt<5>("h015")) @[pic_ctrl.scala 144:139] - node _T_470 = and(waddr_config_gw_base_match, _T_469) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_21 = and(_T_470, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_471 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_472 = eq(_T_471, UInt<5>("h016")) @[pic_ctrl.scala 144:139] - node _T_473 = and(waddr_config_gw_base_match, _T_472) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_22 = and(_T_473, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_474 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_475 = eq(_T_474, UInt<5>("h017")) @[pic_ctrl.scala 144:139] - node _T_476 = and(waddr_config_gw_base_match, _T_475) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_23 = and(_T_476, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_477 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_478 = eq(_T_477, UInt<5>("h018")) @[pic_ctrl.scala 144:139] - node _T_479 = and(waddr_config_gw_base_match, _T_478) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_24 = and(_T_479, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_480 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_481 = eq(_T_480, UInt<5>("h019")) @[pic_ctrl.scala 144:139] - node _T_482 = and(waddr_config_gw_base_match, _T_481) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_25 = and(_T_482, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_483 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_484 = eq(_T_483, UInt<5>("h01a")) @[pic_ctrl.scala 144:139] - node _T_485 = and(waddr_config_gw_base_match, _T_484) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_26 = and(_T_485, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_486 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_487 = eq(_T_486, UInt<5>("h01b")) @[pic_ctrl.scala 144:139] - node _T_488 = and(waddr_config_gw_base_match, _T_487) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_27 = and(_T_488, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_489 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_490 = eq(_T_489, UInt<5>("h01c")) @[pic_ctrl.scala 144:139] - node _T_491 = and(waddr_config_gw_base_match, _T_490) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_28 = and(_T_491, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_492 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_493 = eq(_T_492, UInt<5>("h01d")) @[pic_ctrl.scala 144:139] - node _T_494 = and(waddr_config_gw_base_match, _T_493) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_29 = and(_T_494, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_495 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_496 = eq(_T_495, UInt<5>("h01e")) @[pic_ctrl.scala 144:139] - node _T_497 = and(waddr_config_gw_base_match, _T_496) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_30 = and(_T_497, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_498 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 144:122] - node _T_499 = eq(_T_498, UInt<5>("h01f")) @[pic_ctrl.scala 144:139] - node _T_500 = and(waddr_config_gw_base_match, _T_499) @[pic_ctrl.scala 144:106] - node gw_config_reg_we_31 = and(_T_500, picm_wren_ff) @[pic_ctrl.scala 144:153] - node _T_501 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_502 = eq(_T_501, UInt<1>("h01")) @[pic_ctrl.scala 145:139] - node _T_503 = and(raddr_config_gw_base_match, _T_502) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_1 = and(_T_503, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_504 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_505 = eq(_T_504, UInt<2>("h02")) @[pic_ctrl.scala 145:139] - node _T_506 = and(raddr_config_gw_base_match, _T_505) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_2 = and(_T_506, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_507 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_508 = eq(_T_507, UInt<2>("h03")) @[pic_ctrl.scala 145:139] - node _T_509 = and(raddr_config_gw_base_match, _T_508) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_3 = and(_T_509, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_510 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_511 = eq(_T_510, UInt<3>("h04")) @[pic_ctrl.scala 145:139] - node _T_512 = and(raddr_config_gw_base_match, _T_511) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_4 = and(_T_512, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_513 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_514 = eq(_T_513, UInt<3>("h05")) @[pic_ctrl.scala 145:139] - node _T_515 = and(raddr_config_gw_base_match, _T_514) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_5 = and(_T_515, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_516 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_517 = eq(_T_516, UInt<3>("h06")) @[pic_ctrl.scala 145:139] - node _T_518 = and(raddr_config_gw_base_match, _T_517) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_6 = and(_T_518, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_519 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_520 = eq(_T_519, UInt<3>("h07")) @[pic_ctrl.scala 145:139] - node _T_521 = and(raddr_config_gw_base_match, _T_520) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_7 = and(_T_521, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_522 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_523 = eq(_T_522, UInt<4>("h08")) @[pic_ctrl.scala 145:139] - node _T_524 = and(raddr_config_gw_base_match, _T_523) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_8 = and(_T_524, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_525 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_526 = eq(_T_525, UInt<4>("h09")) @[pic_ctrl.scala 145:139] - node _T_527 = and(raddr_config_gw_base_match, _T_526) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_9 = and(_T_527, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_528 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_529 = eq(_T_528, UInt<4>("h0a")) @[pic_ctrl.scala 145:139] - node _T_530 = and(raddr_config_gw_base_match, _T_529) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_10 = and(_T_530, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_531 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_532 = eq(_T_531, UInt<4>("h0b")) @[pic_ctrl.scala 145:139] - node _T_533 = and(raddr_config_gw_base_match, _T_532) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_11 = and(_T_533, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_534 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_535 = eq(_T_534, UInt<4>("h0c")) @[pic_ctrl.scala 145:139] - node _T_536 = and(raddr_config_gw_base_match, _T_535) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_12 = and(_T_536, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_537 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_538 = eq(_T_537, UInt<4>("h0d")) @[pic_ctrl.scala 145:139] - node _T_539 = and(raddr_config_gw_base_match, _T_538) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_13 = and(_T_539, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_540 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_541 = eq(_T_540, UInt<4>("h0e")) @[pic_ctrl.scala 145:139] - node _T_542 = and(raddr_config_gw_base_match, _T_541) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_14 = and(_T_542, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_543 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_544 = eq(_T_543, UInt<4>("h0f")) @[pic_ctrl.scala 145:139] - node _T_545 = and(raddr_config_gw_base_match, _T_544) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_15 = and(_T_545, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_546 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_547 = eq(_T_546, UInt<5>("h010")) @[pic_ctrl.scala 145:139] - node _T_548 = and(raddr_config_gw_base_match, _T_547) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_16 = and(_T_548, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_549 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_550 = eq(_T_549, UInt<5>("h011")) @[pic_ctrl.scala 145:139] - node _T_551 = and(raddr_config_gw_base_match, _T_550) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_17 = and(_T_551, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_552 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_553 = eq(_T_552, UInt<5>("h012")) @[pic_ctrl.scala 145:139] - node _T_554 = and(raddr_config_gw_base_match, _T_553) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_18 = and(_T_554, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_555 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_556 = eq(_T_555, UInt<5>("h013")) @[pic_ctrl.scala 145:139] - node _T_557 = and(raddr_config_gw_base_match, _T_556) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_19 = and(_T_557, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_558 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_559 = eq(_T_558, UInt<5>("h014")) @[pic_ctrl.scala 145:139] - node _T_560 = and(raddr_config_gw_base_match, _T_559) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_20 = and(_T_560, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_561 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_562 = eq(_T_561, UInt<5>("h015")) @[pic_ctrl.scala 145:139] - node _T_563 = and(raddr_config_gw_base_match, _T_562) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_21 = and(_T_563, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_564 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_565 = eq(_T_564, UInt<5>("h016")) @[pic_ctrl.scala 145:139] - node _T_566 = and(raddr_config_gw_base_match, _T_565) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_22 = and(_T_566, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_567 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_568 = eq(_T_567, UInt<5>("h017")) @[pic_ctrl.scala 145:139] - node _T_569 = and(raddr_config_gw_base_match, _T_568) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_23 = and(_T_569, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_570 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_571 = eq(_T_570, UInt<5>("h018")) @[pic_ctrl.scala 145:139] - node _T_572 = and(raddr_config_gw_base_match, _T_571) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_24 = and(_T_572, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_573 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_574 = eq(_T_573, UInt<5>("h019")) @[pic_ctrl.scala 145:139] - node _T_575 = and(raddr_config_gw_base_match, _T_574) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_25 = and(_T_575, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_576 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_577 = eq(_T_576, UInt<5>("h01a")) @[pic_ctrl.scala 145:139] - node _T_578 = and(raddr_config_gw_base_match, _T_577) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_26 = and(_T_578, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_579 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_580 = eq(_T_579, UInt<5>("h01b")) @[pic_ctrl.scala 145:139] - node _T_581 = and(raddr_config_gw_base_match, _T_580) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_27 = and(_T_581, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_582 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_583 = eq(_T_582, UInt<5>("h01c")) @[pic_ctrl.scala 145:139] - node _T_584 = and(raddr_config_gw_base_match, _T_583) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_28 = and(_T_584, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_585 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_586 = eq(_T_585, UInt<5>("h01d")) @[pic_ctrl.scala 145:139] - node _T_587 = and(raddr_config_gw_base_match, _T_586) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_29 = and(_T_587, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_588 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_589 = eq(_T_588, UInt<5>("h01e")) @[pic_ctrl.scala 145:139] - node _T_590 = and(raddr_config_gw_base_match, _T_589) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_30 = and(_T_590, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_591 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 145:122] - node _T_592 = eq(_T_591, UInt<5>("h01f")) @[pic_ctrl.scala 145:139] - node _T_593 = and(raddr_config_gw_base_match, _T_592) @[pic_ctrl.scala 145:106] - node gw_config_reg_re_31 = and(_T_593, picm_rden_ff) @[pic_ctrl.scala 145:153] - node _T_594 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_595 = eq(_T_594, UInt<1>("h01")) @[pic_ctrl.scala 146:139] - node _T_596 = and(addr_clear_gw_base_match, _T_595) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_1 = and(_T_596, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_597 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_598 = eq(_T_597, UInt<2>("h02")) @[pic_ctrl.scala 146:139] - node _T_599 = and(addr_clear_gw_base_match, _T_598) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_2 = and(_T_599, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_600 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_601 = eq(_T_600, UInt<2>("h03")) @[pic_ctrl.scala 146:139] - node _T_602 = and(addr_clear_gw_base_match, _T_601) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_3 = and(_T_602, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_603 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_604 = eq(_T_603, UInt<3>("h04")) @[pic_ctrl.scala 146:139] - node _T_605 = and(addr_clear_gw_base_match, _T_604) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_4 = and(_T_605, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_606 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_607 = eq(_T_606, UInt<3>("h05")) @[pic_ctrl.scala 146:139] - node _T_608 = and(addr_clear_gw_base_match, _T_607) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_5 = and(_T_608, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_609 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_610 = eq(_T_609, UInt<3>("h06")) @[pic_ctrl.scala 146:139] - node _T_611 = and(addr_clear_gw_base_match, _T_610) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_6 = and(_T_611, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_612 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_613 = eq(_T_612, UInt<3>("h07")) @[pic_ctrl.scala 146:139] - node _T_614 = and(addr_clear_gw_base_match, _T_613) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_7 = and(_T_614, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_615 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_616 = eq(_T_615, UInt<4>("h08")) @[pic_ctrl.scala 146:139] - node _T_617 = and(addr_clear_gw_base_match, _T_616) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_8 = and(_T_617, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_618 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_619 = eq(_T_618, UInt<4>("h09")) @[pic_ctrl.scala 146:139] - node _T_620 = and(addr_clear_gw_base_match, _T_619) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_9 = and(_T_620, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_621 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_622 = eq(_T_621, UInt<4>("h0a")) @[pic_ctrl.scala 146:139] - node _T_623 = and(addr_clear_gw_base_match, _T_622) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_10 = and(_T_623, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_624 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_625 = eq(_T_624, UInt<4>("h0b")) @[pic_ctrl.scala 146:139] - node _T_626 = and(addr_clear_gw_base_match, _T_625) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_11 = and(_T_626, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_627 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_628 = eq(_T_627, UInt<4>("h0c")) @[pic_ctrl.scala 146:139] - node _T_629 = and(addr_clear_gw_base_match, _T_628) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_12 = and(_T_629, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_630 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_631 = eq(_T_630, UInt<4>("h0d")) @[pic_ctrl.scala 146:139] - node _T_632 = and(addr_clear_gw_base_match, _T_631) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_13 = and(_T_632, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_633 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_634 = eq(_T_633, UInt<4>("h0e")) @[pic_ctrl.scala 146:139] - node _T_635 = and(addr_clear_gw_base_match, _T_634) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_14 = and(_T_635, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_636 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_637 = eq(_T_636, UInt<4>("h0f")) @[pic_ctrl.scala 146:139] - node _T_638 = and(addr_clear_gw_base_match, _T_637) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_15 = and(_T_638, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_639 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_640 = eq(_T_639, UInt<5>("h010")) @[pic_ctrl.scala 146:139] - node _T_641 = and(addr_clear_gw_base_match, _T_640) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_16 = and(_T_641, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_642 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_643 = eq(_T_642, UInt<5>("h011")) @[pic_ctrl.scala 146:139] - node _T_644 = and(addr_clear_gw_base_match, _T_643) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_17 = and(_T_644, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_645 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_646 = eq(_T_645, UInt<5>("h012")) @[pic_ctrl.scala 146:139] - node _T_647 = and(addr_clear_gw_base_match, _T_646) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_18 = and(_T_647, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_648 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_649 = eq(_T_648, UInt<5>("h013")) @[pic_ctrl.scala 146:139] - node _T_650 = and(addr_clear_gw_base_match, _T_649) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_19 = and(_T_650, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_651 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_652 = eq(_T_651, UInt<5>("h014")) @[pic_ctrl.scala 146:139] - node _T_653 = and(addr_clear_gw_base_match, _T_652) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_20 = and(_T_653, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_654 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_655 = eq(_T_654, UInt<5>("h015")) @[pic_ctrl.scala 146:139] - node _T_656 = and(addr_clear_gw_base_match, _T_655) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_21 = and(_T_656, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_657 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_658 = eq(_T_657, UInt<5>("h016")) @[pic_ctrl.scala 146:139] - node _T_659 = and(addr_clear_gw_base_match, _T_658) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_22 = and(_T_659, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_660 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_661 = eq(_T_660, UInt<5>("h017")) @[pic_ctrl.scala 146:139] - node _T_662 = and(addr_clear_gw_base_match, _T_661) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_23 = and(_T_662, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_663 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_664 = eq(_T_663, UInt<5>("h018")) @[pic_ctrl.scala 146:139] - node _T_665 = and(addr_clear_gw_base_match, _T_664) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_24 = and(_T_665, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_666 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_667 = eq(_T_666, UInt<5>("h019")) @[pic_ctrl.scala 146:139] - node _T_668 = and(addr_clear_gw_base_match, _T_667) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_25 = and(_T_668, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_669 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_670 = eq(_T_669, UInt<5>("h01a")) @[pic_ctrl.scala 146:139] - node _T_671 = and(addr_clear_gw_base_match, _T_670) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_26 = and(_T_671, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_672 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_673 = eq(_T_672, UInt<5>("h01b")) @[pic_ctrl.scala 146:139] - node _T_674 = and(addr_clear_gw_base_match, _T_673) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_27 = and(_T_674, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_675 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_676 = eq(_T_675, UInt<5>("h01c")) @[pic_ctrl.scala 146:139] - node _T_677 = and(addr_clear_gw_base_match, _T_676) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_28 = and(_T_677, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_678 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_679 = eq(_T_678, UInt<5>("h01d")) @[pic_ctrl.scala 146:139] - node _T_680 = and(addr_clear_gw_base_match, _T_679) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_29 = and(_T_680, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_681 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_682 = eq(_T_681, UInt<5>("h01e")) @[pic_ctrl.scala 146:139] - node _T_683 = and(addr_clear_gw_base_match, _T_682) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_30 = and(_T_683, picm_wren_ff) @[pic_ctrl.scala 146:153] - node _T_684 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 146:122] - node _T_685 = eq(_T_684, UInt<5>("h01f")) @[pic_ctrl.scala 146:139] - node _T_686 = and(addr_clear_gw_base_match, _T_685) @[pic_ctrl.scala 146:106] - node gw_clear_reg_we_31 = and(_T_686, picm_wren_ff) @[pic_ctrl.scala 146:153] - wire intpriority_reg : UInt<4>[32] @[pic_ctrl.scala 147:32] - intpriority_reg[0] <= UInt<4>("h00") @[pic_ctrl.scala 148:208] - node _T_687 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_688 = bits(intpriority_reg_we_1, 0, 0) @[pic_ctrl.scala 148:174] + node _T_36 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_37 = eq(_T_36, UInt<1>("h01")) @[pic_ctrl.scala 141:139] + node _T_38 = and(waddr_intpriority_base_match, _T_37) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_1 = and(_T_38, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_39 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_40 = eq(_T_39, UInt<2>("h02")) @[pic_ctrl.scala 141:139] + node _T_41 = and(waddr_intpriority_base_match, _T_40) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_2 = and(_T_41, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_42 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_43 = eq(_T_42, UInt<2>("h03")) @[pic_ctrl.scala 141:139] + node _T_44 = and(waddr_intpriority_base_match, _T_43) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_3 = and(_T_44, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_45 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_46 = eq(_T_45, UInt<3>("h04")) @[pic_ctrl.scala 141:139] + node _T_47 = and(waddr_intpriority_base_match, _T_46) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_4 = and(_T_47, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_48 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_49 = eq(_T_48, UInt<3>("h05")) @[pic_ctrl.scala 141:139] + node _T_50 = and(waddr_intpriority_base_match, _T_49) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_5 = and(_T_50, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_51 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_52 = eq(_T_51, UInt<3>("h06")) @[pic_ctrl.scala 141:139] + node _T_53 = and(waddr_intpriority_base_match, _T_52) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_6 = and(_T_53, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_54 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_55 = eq(_T_54, UInt<3>("h07")) @[pic_ctrl.scala 141:139] + node _T_56 = and(waddr_intpriority_base_match, _T_55) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_7 = and(_T_56, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_57 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_58 = eq(_T_57, UInt<4>("h08")) @[pic_ctrl.scala 141:139] + node _T_59 = and(waddr_intpriority_base_match, _T_58) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_8 = and(_T_59, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_60 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_61 = eq(_T_60, UInt<4>("h09")) @[pic_ctrl.scala 141:139] + node _T_62 = and(waddr_intpriority_base_match, _T_61) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_9 = and(_T_62, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_63 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_64 = eq(_T_63, UInt<4>("h0a")) @[pic_ctrl.scala 141:139] + node _T_65 = and(waddr_intpriority_base_match, _T_64) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_10 = and(_T_65, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_66 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_67 = eq(_T_66, UInt<4>("h0b")) @[pic_ctrl.scala 141:139] + node _T_68 = and(waddr_intpriority_base_match, _T_67) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_11 = and(_T_68, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_69 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_70 = eq(_T_69, UInt<4>("h0c")) @[pic_ctrl.scala 141:139] + node _T_71 = and(waddr_intpriority_base_match, _T_70) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_12 = and(_T_71, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_72 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_73 = eq(_T_72, UInt<4>("h0d")) @[pic_ctrl.scala 141:139] + node _T_74 = and(waddr_intpriority_base_match, _T_73) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_13 = and(_T_74, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_75 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_76 = eq(_T_75, UInt<4>("h0e")) @[pic_ctrl.scala 141:139] + node _T_77 = and(waddr_intpriority_base_match, _T_76) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_14 = and(_T_77, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_78 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_79 = eq(_T_78, UInt<4>("h0f")) @[pic_ctrl.scala 141:139] + node _T_80 = and(waddr_intpriority_base_match, _T_79) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_15 = and(_T_80, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_81 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_82 = eq(_T_81, UInt<5>("h010")) @[pic_ctrl.scala 141:139] + node _T_83 = and(waddr_intpriority_base_match, _T_82) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_16 = and(_T_83, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_84 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_85 = eq(_T_84, UInt<5>("h011")) @[pic_ctrl.scala 141:139] + node _T_86 = and(waddr_intpriority_base_match, _T_85) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_17 = and(_T_86, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_87 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_88 = eq(_T_87, UInt<5>("h012")) @[pic_ctrl.scala 141:139] + node _T_89 = and(waddr_intpriority_base_match, _T_88) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_18 = and(_T_89, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_90 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_91 = eq(_T_90, UInt<5>("h013")) @[pic_ctrl.scala 141:139] + node _T_92 = and(waddr_intpriority_base_match, _T_91) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_19 = and(_T_92, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_93 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_94 = eq(_T_93, UInt<5>("h014")) @[pic_ctrl.scala 141:139] + node _T_95 = and(waddr_intpriority_base_match, _T_94) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_20 = and(_T_95, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_96 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_97 = eq(_T_96, UInt<5>("h015")) @[pic_ctrl.scala 141:139] + node _T_98 = and(waddr_intpriority_base_match, _T_97) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_21 = and(_T_98, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_99 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_100 = eq(_T_99, UInt<5>("h016")) @[pic_ctrl.scala 141:139] + node _T_101 = and(waddr_intpriority_base_match, _T_100) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_22 = and(_T_101, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_102 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_103 = eq(_T_102, UInt<5>("h017")) @[pic_ctrl.scala 141:139] + node _T_104 = and(waddr_intpriority_base_match, _T_103) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_23 = and(_T_104, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_105 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_106 = eq(_T_105, UInt<5>("h018")) @[pic_ctrl.scala 141:139] + node _T_107 = and(waddr_intpriority_base_match, _T_106) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_24 = and(_T_107, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_108 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_109 = eq(_T_108, UInt<5>("h019")) @[pic_ctrl.scala 141:139] + node _T_110 = and(waddr_intpriority_base_match, _T_109) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_25 = and(_T_110, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_111 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_112 = eq(_T_111, UInt<5>("h01a")) @[pic_ctrl.scala 141:139] + node _T_113 = and(waddr_intpriority_base_match, _T_112) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_26 = and(_T_113, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_114 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_115 = eq(_T_114, UInt<5>("h01b")) @[pic_ctrl.scala 141:139] + node _T_116 = and(waddr_intpriority_base_match, _T_115) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_27 = and(_T_116, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_117 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_118 = eq(_T_117, UInt<5>("h01c")) @[pic_ctrl.scala 141:139] + node _T_119 = and(waddr_intpriority_base_match, _T_118) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_28 = and(_T_119, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_120 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_121 = eq(_T_120, UInt<5>("h01d")) @[pic_ctrl.scala 141:139] + node _T_122 = and(waddr_intpriority_base_match, _T_121) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_29 = and(_T_122, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_123 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_124 = eq(_T_123, UInt<5>("h01e")) @[pic_ctrl.scala 141:139] + node _T_125 = and(waddr_intpriority_base_match, _T_124) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_30 = and(_T_125, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_126 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 141:122] + node _T_127 = eq(_T_126, UInt<5>("h01f")) @[pic_ctrl.scala 141:139] + node _T_128 = and(waddr_intpriority_base_match, _T_127) @[pic_ctrl.scala 141:106] + node intpriority_reg_we_31 = and(_T_128, picm_wren_ff) @[pic_ctrl.scala 141:153] + node _T_129 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_130 = eq(_T_129, UInt<1>("h01")) @[pic_ctrl.scala 142:139] + node _T_131 = and(raddr_intpriority_base_match, _T_130) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_1 = and(_T_131, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_132 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_133 = eq(_T_132, UInt<2>("h02")) @[pic_ctrl.scala 142:139] + node _T_134 = and(raddr_intpriority_base_match, _T_133) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_2 = and(_T_134, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_135 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_136 = eq(_T_135, UInt<2>("h03")) @[pic_ctrl.scala 142:139] + node _T_137 = and(raddr_intpriority_base_match, _T_136) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_3 = and(_T_137, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_138 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_139 = eq(_T_138, UInt<3>("h04")) @[pic_ctrl.scala 142:139] + node _T_140 = and(raddr_intpriority_base_match, _T_139) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_4 = and(_T_140, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_141 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_142 = eq(_T_141, UInt<3>("h05")) @[pic_ctrl.scala 142:139] + node _T_143 = and(raddr_intpriority_base_match, _T_142) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_5 = and(_T_143, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_144 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_145 = eq(_T_144, UInt<3>("h06")) @[pic_ctrl.scala 142:139] + node _T_146 = and(raddr_intpriority_base_match, _T_145) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_6 = and(_T_146, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_147 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_148 = eq(_T_147, UInt<3>("h07")) @[pic_ctrl.scala 142:139] + node _T_149 = and(raddr_intpriority_base_match, _T_148) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_7 = and(_T_149, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_150 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_151 = eq(_T_150, UInt<4>("h08")) @[pic_ctrl.scala 142:139] + node _T_152 = and(raddr_intpriority_base_match, _T_151) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_8 = and(_T_152, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_153 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_154 = eq(_T_153, UInt<4>("h09")) @[pic_ctrl.scala 142:139] + node _T_155 = and(raddr_intpriority_base_match, _T_154) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_9 = and(_T_155, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_156 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_157 = eq(_T_156, UInt<4>("h0a")) @[pic_ctrl.scala 142:139] + node _T_158 = and(raddr_intpriority_base_match, _T_157) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_10 = and(_T_158, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_159 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_160 = eq(_T_159, UInt<4>("h0b")) @[pic_ctrl.scala 142:139] + node _T_161 = and(raddr_intpriority_base_match, _T_160) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_11 = and(_T_161, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_162 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_163 = eq(_T_162, UInt<4>("h0c")) @[pic_ctrl.scala 142:139] + node _T_164 = and(raddr_intpriority_base_match, _T_163) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_12 = and(_T_164, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_165 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_166 = eq(_T_165, UInt<4>("h0d")) @[pic_ctrl.scala 142:139] + node _T_167 = and(raddr_intpriority_base_match, _T_166) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_13 = and(_T_167, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_168 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_169 = eq(_T_168, UInt<4>("h0e")) @[pic_ctrl.scala 142:139] + node _T_170 = and(raddr_intpriority_base_match, _T_169) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_14 = and(_T_170, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_171 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_172 = eq(_T_171, UInt<4>("h0f")) @[pic_ctrl.scala 142:139] + node _T_173 = and(raddr_intpriority_base_match, _T_172) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_15 = and(_T_173, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_174 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_175 = eq(_T_174, UInt<5>("h010")) @[pic_ctrl.scala 142:139] + node _T_176 = and(raddr_intpriority_base_match, _T_175) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_16 = and(_T_176, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_177 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_178 = eq(_T_177, UInt<5>("h011")) @[pic_ctrl.scala 142:139] + node _T_179 = and(raddr_intpriority_base_match, _T_178) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_17 = and(_T_179, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_180 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_181 = eq(_T_180, UInt<5>("h012")) @[pic_ctrl.scala 142:139] + node _T_182 = and(raddr_intpriority_base_match, _T_181) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_18 = and(_T_182, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_183 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_184 = eq(_T_183, UInt<5>("h013")) @[pic_ctrl.scala 142:139] + node _T_185 = and(raddr_intpriority_base_match, _T_184) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_19 = and(_T_185, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_186 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_187 = eq(_T_186, UInt<5>("h014")) @[pic_ctrl.scala 142:139] + node _T_188 = and(raddr_intpriority_base_match, _T_187) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_20 = and(_T_188, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_189 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_190 = eq(_T_189, UInt<5>("h015")) @[pic_ctrl.scala 142:139] + node _T_191 = and(raddr_intpriority_base_match, _T_190) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_21 = and(_T_191, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_192 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_193 = eq(_T_192, UInt<5>("h016")) @[pic_ctrl.scala 142:139] + node _T_194 = and(raddr_intpriority_base_match, _T_193) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_22 = and(_T_194, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_195 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_196 = eq(_T_195, UInt<5>("h017")) @[pic_ctrl.scala 142:139] + node _T_197 = and(raddr_intpriority_base_match, _T_196) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_23 = and(_T_197, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_198 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_199 = eq(_T_198, UInt<5>("h018")) @[pic_ctrl.scala 142:139] + node _T_200 = and(raddr_intpriority_base_match, _T_199) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_24 = and(_T_200, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_201 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_202 = eq(_T_201, UInt<5>("h019")) @[pic_ctrl.scala 142:139] + node _T_203 = and(raddr_intpriority_base_match, _T_202) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_25 = and(_T_203, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_204 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_205 = eq(_T_204, UInt<5>("h01a")) @[pic_ctrl.scala 142:139] + node _T_206 = and(raddr_intpriority_base_match, _T_205) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_26 = and(_T_206, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_207 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_208 = eq(_T_207, UInt<5>("h01b")) @[pic_ctrl.scala 142:139] + node _T_209 = and(raddr_intpriority_base_match, _T_208) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_27 = and(_T_209, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_210 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_211 = eq(_T_210, UInt<5>("h01c")) @[pic_ctrl.scala 142:139] + node _T_212 = and(raddr_intpriority_base_match, _T_211) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_28 = and(_T_212, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_213 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_214 = eq(_T_213, UInt<5>("h01d")) @[pic_ctrl.scala 142:139] + node _T_215 = and(raddr_intpriority_base_match, _T_214) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_29 = and(_T_215, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_216 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_217 = eq(_T_216, UInt<5>("h01e")) @[pic_ctrl.scala 142:139] + node _T_218 = and(raddr_intpriority_base_match, _T_217) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_30 = and(_T_218, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_219 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 142:122] + node _T_220 = eq(_T_219, UInt<5>("h01f")) @[pic_ctrl.scala 142:139] + node _T_221 = and(raddr_intpriority_base_match, _T_220) @[pic_ctrl.scala 142:106] + node intpriority_reg_re_31 = and(_T_221, picm_rden_ff) @[pic_ctrl.scala 142:153] + node _T_222 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_223 = eq(_T_222, UInt<1>("h01")) @[pic_ctrl.scala 143:139] + node _T_224 = and(waddr_intenable_base_match, _T_223) @[pic_ctrl.scala 143:106] + node intenable_reg_we_1 = and(_T_224, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_225 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_226 = eq(_T_225, UInt<2>("h02")) @[pic_ctrl.scala 143:139] + node _T_227 = and(waddr_intenable_base_match, _T_226) @[pic_ctrl.scala 143:106] + node intenable_reg_we_2 = and(_T_227, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_228 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_229 = eq(_T_228, UInt<2>("h03")) @[pic_ctrl.scala 143:139] + node _T_230 = and(waddr_intenable_base_match, _T_229) @[pic_ctrl.scala 143:106] + node intenable_reg_we_3 = and(_T_230, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_231 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_232 = eq(_T_231, UInt<3>("h04")) @[pic_ctrl.scala 143:139] + node _T_233 = and(waddr_intenable_base_match, _T_232) @[pic_ctrl.scala 143:106] + node intenable_reg_we_4 = and(_T_233, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_234 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_235 = eq(_T_234, UInt<3>("h05")) @[pic_ctrl.scala 143:139] + node _T_236 = and(waddr_intenable_base_match, _T_235) @[pic_ctrl.scala 143:106] + node intenable_reg_we_5 = and(_T_236, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_237 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_238 = eq(_T_237, UInt<3>("h06")) @[pic_ctrl.scala 143:139] + node _T_239 = and(waddr_intenable_base_match, _T_238) @[pic_ctrl.scala 143:106] + node intenable_reg_we_6 = and(_T_239, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_240 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_241 = eq(_T_240, UInt<3>("h07")) @[pic_ctrl.scala 143:139] + node _T_242 = and(waddr_intenable_base_match, _T_241) @[pic_ctrl.scala 143:106] + node intenable_reg_we_7 = and(_T_242, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_243 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_244 = eq(_T_243, UInt<4>("h08")) @[pic_ctrl.scala 143:139] + node _T_245 = and(waddr_intenable_base_match, _T_244) @[pic_ctrl.scala 143:106] + node intenable_reg_we_8 = and(_T_245, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_246 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_247 = eq(_T_246, UInt<4>("h09")) @[pic_ctrl.scala 143:139] + node _T_248 = and(waddr_intenable_base_match, _T_247) @[pic_ctrl.scala 143:106] + node intenable_reg_we_9 = and(_T_248, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_249 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_250 = eq(_T_249, UInt<4>("h0a")) @[pic_ctrl.scala 143:139] + node _T_251 = and(waddr_intenable_base_match, _T_250) @[pic_ctrl.scala 143:106] + node intenable_reg_we_10 = and(_T_251, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_252 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_253 = eq(_T_252, UInt<4>("h0b")) @[pic_ctrl.scala 143:139] + node _T_254 = and(waddr_intenable_base_match, _T_253) @[pic_ctrl.scala 143:106] + node intenable_reg_we_11 = and(_T_254, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_255 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_256 = eq(_T_255, UInt<4>("h0c")) @[pic_ctrl.scala 143:139] + node _T_257 = and(waddr_intenable_base_match, _T_256) @[pic_ctrl.scala 143:106] + node intenable_reg_we_12 = and(_T_257, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_258 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_259 = eq(_T_258, UInt<4>("h0d")) @[pic_ctrl.scala 143:139] + node _T_260 = and(waddr_intenable_base_match, _T_259) @[pic_ctrl.scala 143:106] + node intenable_reg_we_13 = and(_T_260, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_261 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_262 = eq(_T_261, UInt<4>("h0e")) @[pic_ctrl.scala 143:139] + node _T_263 = and(waddr_intenable_base_match, _T_262) @[pic_ctrl.scala 143:106] + node intenable_reg_we_14 = and(_T_263, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_264 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_265 = eq(_T_264, UInt<4>("h0f")) @[pic_ctrl.scala 143:139] + node _T_266 = and(waddr_intenable_base_match, _T_265) @[pic_ctrl.scala 143:106] + node intenable_reg_we_15 = and(_T_266, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_267 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_268 = eq(_T_267, UInt<5>("h010")) @[pic_ctrl.scala 143:139] + node _T_269 = and(waddr_intenable_base_match, _T_268) @[pic_ctrl.scala 143:106] + node intenable_reg_we_16 = and(_T_269, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_270 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_271 = eq(_T_270, UInt<5>("h011")) @[pic_ctrl.scala 143:139] + node _T_272 = and(waddr_intenable_base_match, _T_271) @[pic_ctrl.scala 143:106] + node intenable_reg_we_17 = and(_T_272, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_273 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_274 = eq(_T_273, UInt<5>("h012")) @[pic_ctrl.scala 143:139] + node _T_275 = and(waddr_intenable_base_match, _T_274) @[pic_ctrl.scala 143:106] + node intenable_reg_we_18 = and(_T_275, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_276 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_277 = eq(_T_276, UInt<5>("h013")) @[pic_ctrl.scala 143:139] + node _T_278 = and(waddr_intenable_base_match, _T_277) @[pic_ctrl.scala 143:106] + node intenable_reg_we_19 = and(_T_278, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_279 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_280 = eq(_T_279, UInt<5>("h014")) @[pic_ctrl.scala 143:139] + node _T_281 = and(waddr_intenable_base_match, _T_280) @[pic_ctrl.scala 143:106] + node intenable_reg_we_20 = and(_T_281, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_282 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_283 = eq(_T_282, UInt<5>("h015")) @[pic_ctrl.scala 143:139] + node _T_284 = and(waddr_intenable_base_match, _T_283) @[pic_ctrl.scala 143:106] + node intenable_reg_we_21 = and(_T_284, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_285 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_286 = eq(_T_285, UInt<5>("h016")) @[pic_ctrl.scala 143:139] + node _T_287 = and(waddr_intenable_base_match, _T_286) @[pic_ctrl.scala 143:106] + node intenable_reg_we_22 = and(_T_287, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_288 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_289 = eq(_T_288, UInt<5>("h017")) @[pic_ctrl.scala 143:139] + node _T_290 = and(waddr_intenable_base_match, _T_289) @[pic_ctrl.scala 143:106] + node intenable_reg_we_23 = and(_T_290, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_291 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_292 = eq(_T_291, UInt<5>("h018")) @[pic_ctrl.scala 143:139] + node _T_293 = and(waddr_intenable_base_match, _T_292) @[pic_ctrl.scala 143:106] + node intenable_reg_we_24 = and(_T_293, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_294 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_295 = eq(_T_294, UInt<5>("h019")) @[pic_ctrl.scala 143:139] + node _T_296 = and(waddr_intenable_base_match, _T_295) @[pic_ctrl.scala 143:106] + node intenable_reg_we_25 = and(_T_296, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_297 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_298 = eq(_T_297, UInt<5>("h01a")) @[pic_ctrl.scala 143:139] + node _T_299 = and(waddr_intenable_base_match, _T_298) @[pic_ctrl.scala 143:106] + node intenable_reg_we_26 = and(_T_299, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_300 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_301 = eq(_T_300, UInt<5>("h01b")) @[pic_ctrl.scala 143:139] + node _T_302 = and(waddr_intenable_base_match, _T_301) @[pic_ctrl.scala 143:106] + node intenable_reg_we_27 = and(_T_302, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_303 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_304 = eq(_T_303, UInt<5>("h01c")) @[pic_ctrl.scala 143:139] + node _T_305 = and(waddr_intenable_base_match, _T_304) @[pic_ctrl.scala 143:106] + node intenable_reg_we_28 = and(_T_305, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_306 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_307 = eq(_T_306, UInt<5>("h01d")) @[pic_ctrl.scala 143:139] + node _T_308 = and(waddr_intenable_base_match, _T_307) @[pic_ctrl.scala 143:106] + node intenable_reg_we_29 = and(_T_308, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_309 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_310 = eq(_T_309, UInt<5>("h01e")) @[pic_ctrl.scala 143:139] + node _T_311 = and(waddr_intenable_base_match, _T_310) @[pic_ctrl.scala 143:106] + node intenable_reg_we_30 = and(_T_311, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_312 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 143:122] + node _T_313 = eq(_T_312, UInt<5>("h01f")) @[pic_ctrl.scala 143:139] + node _T_314 = and(waddr_intenable_base_match, _T_313) @[pic_ctrl.scala 143:106] + node intenable_reg_we_31 = and(_T_314, picm_wren_ff) @[pic_ctrl.scala 143:153] + node _T_315 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_316 = eq(_T_315, UInt<1>("h01")) @[pic_ctrl.scala 144:139] + node _T_317 = and(raddr_intenable_base_match, _T_316) @[pic_ctrl.scala 144:106] + node intenable_reg_re_1 = and(_T_317, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_318 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_319 = eq(_T_318, UInt<2>("h02")) @[pic_ctrl.scala 144:139] + node _T_320 = and(raddr_intenable_base_match, _T_319) @[pic_ctrl.scala 144:106] + node intenable_reg_re_2 = and(_T_320, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_321 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_322 = eq(_T_321, UInt<2>("h03")) @[pic_ctrl.scala 144:139] + node _T_323 = and(raddr_intenable_base_match, _T_322) @[pic_ctrl.scala 144:106] + node intenable_reg_re_3 = and(_T_323, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_324 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_325 = eq(_T_324, UInt<3>("h04")) @[pic_ctrl.scala 144:139] + node _T_326 = and(raddr_intenable_base_match, _T_325) @[pic_ctrl.scala 144:106] + node intenable_reg_re_4 = and(_T_326, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_327 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_328 = eq(_T_327, UInt<3>("h05")) @[pic_ctrl.scala 144:139] + node _T_329 = and(raddr_intenable_base_match, _T_328) @[pic_ctrl.scala 144:106] + node intenable_reg_re_5 = and(_T_329, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_330 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_331 = eq(_T_330, UInt<3>("h06")) @[pic_ctrl.scala 144:139] + node _T_332 = and(raddr_intenable_base_match, _T_331) @[pic_ctrl.scala 144:106] + node intenable_reg_re_6 = and(_T_332, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_333 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_334 = eq(_T_333, UInt<3>("h07")) @[pic_ctrl.scala 144:139] + node _T_335 = and(raddr_intenable_base_match, _T_334) @[pic_ctrl.scala 144:106] + node intenable_reg_re_7 = and(_T_335, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_336 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_337 = eq(_T_336, UInt<4>("h08")) @[pic_ctrl.scala 144:139] + node _T_338 = and(raddr_intenable_base_match, _T_337) @[pic_ctrl.scala 144:106] + node intenable_reg_re_8 = and(_T_338, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_339 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_340 = eq(_T_339, UInt<4>("h09")) @[pic_ctrl.scala 144:139] + node _T_341 = and(raddr_intenable_base_match, _T_340) @[pic_ctrl.scala 144:106] + node intenable_reg_re_9 = and(_T_341, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_342 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_343 = eq(_T_342, UInt<4>("h0a")) @[pic_ctrl.scala 144:139] + node _T_344 = and(raddr_intenable_base_match, _T_343) @[pic_ctrl.scala 144:106] + node intenable_reg_re_10 = and(_T_344, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_345 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_346 = eq(_T_345, UInt<4>("h0b")) @[pic_ctrl.scala 144:139] + node _T_347 = and(raddr_intenable_base_match, _T_346) @[pic_ctrl.scala 144:106] + node intenable_reg_re_11 = and(_T_347, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_348 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_349 = eq(_T_348, UInt<4>("h0c")) @[pic_ctrl.scala 144:139] + node _T_350 = and(raddr_intenable_base_match, _T_349) @[pic_ctrl.scala 144:106] + node intenable_reg_re_12 = and(_T_350, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_351 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_352 = eq(_T_351, UInt<4>("h0d")) @[pic_ctrl.scala 144:139] + node _T_353 = and(raddr_intenable_base_match, _T_352) @[pic_ctrl.scala 144:106] + node intenable_reg_re_13 = and(_T_353, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_354 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_355 = eq(_T_354, UInt<4>("h0e")) @[pic_ctrl.scala 144:139] + node _T_356 = and(raddr_intenable_base_match, _T_355) @[pic_ctrl.scala 144:106] + node intenable_reg_re_14 = and(_T_356, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_357 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_358 = eq(_T_357, UInt<4>("h0f")) @[pic_ctrl.scala 144:139] + node _T_359 = and(raddr_intenable_base_match, _T_358) @[pic_ctrl.scala 144:106] + node intenable_reg_re_15 = and(_T_359, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_360 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_361 = eq(_T_360, UInt<5>("h010")) @[pic_ctrl.scala 144:139] + node _T_362 = and(raddr_intenable_base_match, _T_361) @[pic_ctrl.scala 144:106] + node intenable_reg_re_16 = and(_T_362, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_363 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_364 = eq(_T_363, UInt<5>("h011")) @[pic_ctrl.scala 144:139] + node _T_365 = and(raddr_intenable_base_match, _T_364) @[pic_ctrl.scala 144:106] + node intenable_reg_re_17 = and(_T_365, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_366 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_367 = eq(_T_366, UInt<5>("h012")) @[pic_ctrl.scala 144:139] + node _T_368 = and(raddr_intenable_base_match, _T_367) @[pic_ctrl.scala 144:106] + node intenable_reg_re_18 = and(_T_368, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_369 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_370 = eq(_T_369, UInt<5>("h013")) @[pic_ctrl.scala 144:139] + node _T_371 = and(raddr_intenable_base_match, _T_370) @[pic_ctrl.scala 144:106] + node intenable_reg_re_19 = and(_T_371, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_372 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_373 = eq(_T_372, UInt<5>("h014")) @[pic_ctrl.scala 144:139] + node _T_374 = and(raddr_intenable_base_match, _T_373) @[pic_ctrl.scala 144:106] + node intenable_reg_re_20 = and(_T_374, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_375 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_376 = eq(_T_375, UInt<5>("h015")) @[pic_ctrl.scala 144:139] + node _T_377 = and(raddr_intenable_base_match, _T_376) @[pic_ctrl.scala 144:106] + node intenable_reg_re_21 = and(_T_377, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_378 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_379 = eq(_T_378, UInt<5>("h016")) @[pic_ctrl.scala 144:139] + node _T_380 = and(raddr_intenable_base_match, _T_379) @[pic_ctrl.scala 144:106] + node intenable_reg_re_22 = and(_T_380, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_381 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_382 = eq(_T_381, UInt<5>("h017")) @[pic_ctrl.scala 144:139] + node _T_383 = and(raddr_intenable_base_match, _T_382) @[pic_ctrl.scala 144:106] + node intenable_reg_re_23 = and(_T_383, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_384 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_385 = eq(_T_384, UInt<5>("h018")) @[pic_ctrl.scala 144:139] + node _T_386 = and(raddr_intenable_base_match, _T_385) @[pic_ctrl.scala 144:106] + node intenable_reg_re_24 = and(_T_386, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_387 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_388 = eq(_T_387, UInt<5>("h019")) @[pic_ctrl.scala 144:139] + node _T_389 = and(raddr_intenable_base_match, _T_388) @[pic_ctrl.scala 144:106] + node intenable_reg_re_25 = and(_T_389, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_390 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_391 = eq(_T_390, UInt<5>("h01a")) @[pic_ctrl.scala 144:139] + node _T_392 = and(raddr_intenable_base_match, _T_391) @[pic_ctrl.scala 144:106] + node intenable_reg_re_26 = and(_T_392, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_393 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_394 = eq(_T_393, UInt<5>("h01b")) @[pic_ctrl.scala 144:139] + node _T_395 = and(raddr_intenable_base_match, _T_394) @[pic_ctrl.scala 144:106] + node intenable_reg_re_27 = and(_T_395, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_396 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_397 = eq(_T_396, UInt<5>("h01c")) @[pic_ctrl.scala 144:139] + node _T_398 = and(raddr_intenable_base_match, _T_397) @[pic_ctrl.scala 144:106] + node intenable_reg_re_28 = and(_T_398, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_399 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_400 = eq(_T_399, UInt<5>("h01d")) @[pic_ctrl.scala 144:139] + node _T_401 = and(raddr_intenable_base_match, _T_400) @[pic_ctrl.scala 144:106] + node intenable_reg_re_29 = and(_T_401, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_402 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_403 = eq(_T_402, UInt<5>("h01e")) @[pic_ctrl.scala 144:139] + node _T_404 = and(raddr_intenable_base_match, _T_403) @[pic_ctrl.scala 144:106] + node intenable_reg_re_30 = and(_T_404, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_405 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 144:122] + node _T_406 = eq(_T_405, UInt<5>("h01f")) @[pic_ctrl.scala 144:139] + node _T_407 = and(raddr_intenable_base_match, _T_406) @[pic_ctrl.scala 144:106] + node intenable_reg_re_31 = and(_T_407, picm_rden_ff) @[pic_ctrl.scala 144:153] + node _T_408 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_409 = eq(_T_408, UInt<1>("h01")) @[pic_ctrl.scala 145:139] + node _T_410 = and(waddr_config_gw_base_match, _T_409) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_1 = and(_T_410, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_411 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_412 = eq(_T_411, UInt<2>("h02")) @[pic_ctrl.scala 145:139] + node _T_413 = and(waddr_config_gw_base_match, _T_412) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_2 = and(_T_413, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_414 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_415 = eq(_T_414, UInt<2>("h03")) @[pic_ctrl.scala 145:139] + node _T_416 = and(waddr_config_gw_base_match, _T_415) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_3 = and(_T_416, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_417 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_418 = eq(_T_417, UInt<3>("h04")) @[pic_ctrl.scala 145:139] + node _T_419 = and(waddr_config_gw_base_match, _T_418) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_4 = and(_T_419, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_420 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_421 = eq(_T_420, UInt<3>("h05")) @[pic_ctrl.scala 145:139] + node _T_422 = and(waddr_config_gw_base_match, _T_421) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_5 = and(_T_422, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_423 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_424 = eq(_T_423, UInt<3>("h06")) @[pic_ctrl.scala 145:139] + node _T_425 = and(waddr_config_gw_base_match, _T_424) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_6 = and(_T_425, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_426 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_427 = eq(_T_426, UInt<3>("h07")) @[pic_ctrl.scala 145:139] + node _T_428 = and(waddr_config_gw_base_match, _T_427) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_7 = and(_T_428, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_429 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_430 = eq(_T_429, UInt<4>("h08")) @[pic_ctrl.scala 145:139] + node _T_431 = and(waddr_config_gw_base_match, _T_430) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_8 = and(_T_431, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_432 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_433 = eq(_T_432, UInt<4>("h09")) @[pic_ctrl.scala 145:139] + node _T_434 = and(waddr_config_gw_base_match, _T_433) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_9 = and(_T_434, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_435 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_436 = eq(_T_435, UInt<4>("h0a")) @[pic_ctrl.scala 145:139] + node _T_437 = and(waddr_config_gw_base_match, _T_436) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_10 = and(_T_437, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_438 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_439 = eq(_T_438, UInt<4>("h0b")) @[pic_ctrl.scala 145:139] + node _T_440 = and(waddr_config_gw_base_match, _T_439) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_11 = and(_T_440, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_441 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_442 = eq(_T_441, UInt<4>("h0c")) @[pic_ctrl.scala 145:139] + node _T_443 = and(waddr_config_gw_base_match, _T_442) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_12 = and(_T_443, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_444 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_445 = eq(_T_444, UInt<4>("h0d")) @[pic_ctrl.scala 145:139] + node _T_446 = and(waddr_config_gw_base_match, _T_445) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_13 = and(_T_446, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_447 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_448 = eq(_T_447, UInt<4>("h0e")) @[pic_ctrl.scala 145:139] + node _T_449 = and(waddr_config_gw_base_match, _T_448) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_14 = and(_T_449, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_450 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_451 = eq(_T_450, UInt<4>("h0f")) @[pic_ctrl.scala 145:139] + node _T_452 = and(waddr_config_gw_base_match, _T_451) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_15 = and(_T_452, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_453 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_454 = eq(_T_453, UInt<5>("h010")) @[pic_ctrl.scala 145:139] + node _T_455 = and(waddr_config_gw_base_match, _T_454) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_16 = and(_T_455, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_456 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_457 = eq(_T_456, UInt<5>("h011")) @[pic_ctrl.scala 145:139] + node _T_458 = and(waddr_config_gw_base_match, _T_457) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_17 = and(_T_458, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_459 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_460 = eq(_T_459, UInt<5>("h012")) @[pic_ctrl.scala 145:139] + node _T_461 = and(waddr_config_gw_base_match, _T_460) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_18 = and(_T_461, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_462 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_463 = eq(_T_462, UInt<5>("h013")) @[pic_ctrl.scala 145:139] + node _T_464 = and(waddr_config_gw_base_match, _T_463) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_19 = and(_T_464, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_465 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_466 = eq(_T_465, UInt<5>("h014")) @[pic_ctrl.scala 145:139] + node _T_467 = and(waddr_config_gw_base_match, _T_466) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_20 = and(_T_467, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_468 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_469 = eq(_T_468, UInt<5>("h015")) @[pic_ctrl.scala 145:139] + node _T_470 = and(waddr_config_gw_base_match, _T_469) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_21 = and(_T_470, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_471 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_472 = eq(_T_471, UInt<5>("h016")) @[pic_ctrl.scala 145:139] + node _T_473 = and(waddr_config_gw_base_match, _T_472) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_22 = and(_T_473, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_474 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_475 = eq(_T_474, UInt<5>("h017")) @[pic_ctrl.scala 145:139] + node _T_476 = and(waddr_config_gw_base_match, _T_475) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_23 = and(_T_476, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_477 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_478 = eq(_T_477, UInt<5>("h018")) @[pic_ctrl.scala 145:139] + node _T_479 = and(waddr_config_gw_base_match, _T_478) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_24 = and(_T_479, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_480 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_481 = eq(_T_480, UInt<5>("h019")) @[pic_ctrl.scala 145:139] + node _T_482 = and(waddr_config_gw_base_match, _T_481) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_25 = and(_T_482, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_483 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_484 = eq(_T_483, UInt<5>("h01a")) @[pic_ctrl.scala 145:139] + node _T_485 = and(waddr_config_gw_base_match, _T_484) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_26 = and(_T_485, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_486 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_487 = eq(_T_486, UInt<5>("h01b")) @[pic_ctrl.scala 145:139] + node _T_488 = and(waddr_config_gw_base_match, _T_487) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_27 = and(_T_488, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_489 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_490 = eq(_T_489, UInt<5>("h01c")) @[pic_ctrl.scala 145:139] + node _T_491 = and(waddr_config_gw_base_match, _T_490) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_28 = and(_T_491, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_492 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_493 = eq(_T_492, UInt<5>("h01d")) @[pic_ctrl.scala 145:139] + node _T_494 = and(waddr_config_gw_base_match, _T_493) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_29 = and(_T_494, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_495 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_496 = eq(_T_495, UInt<5>("h01e")) @[pic_ctrl.scala 145:139] + node _T_497 = and(waddr_config_gw_base_match, _T_496) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_30 = and(_T_497, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_498 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 145:122] + node _T_499 = eq(_T_498, UInt<5>("h01f")) @[pic_ctrl.scala 145:139] + node _T_500 = and(waddr_config_gw_base_match, _T_499) @[pic_ctrl.scala 145:106] + node gw_config_reg_we_31 = and(_T_500, picm_wren_ff) @[pic_ctrl.scala 145:153] + node _T_501 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_502 = eq(_T_501, UInt<1>("h01")) @[pic_ctrl.scala 146:139] + node _T_503 = and(raddr_config_gw_base_match, _T_502) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_1 = and(_T_503, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_504 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_505 = eq(_T_504, UInt<2>("h02")) @[pic_ctrl.scala 146:139] + node _T_506 = and(raddr_config_gw_base_match, _T_505) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_2 = and(_T_506, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_507 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_508 = eq(_T_507, UInt<2>("h03")) @[pic_ctrl.scala 146:139] + node _T_509 = and(raddr_config_gw_base_match, _T_508) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_3 = and(_T_509, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_510 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_511 = eq(_T_510, UInt<3>("h04")) @[pic_ctrl.scala 146:139] + node _T_512 = and(raddr_config_gw_base_match, _T_511) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_4 = and(_T_512, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_513 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_514 = eq(_T_513, UInt<3>("h05")) @[pic_ctrl.scala 146:139] + node _T_515 = and(raddr_config_gw_base_match, _T_514) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_5 = and(_T_515, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_516 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_517 = eq(_T_516, UInt<3>("h06")) @[pic_ctrl.scala 146:139] + node _T_518 = and(raddr_config_gw_base_match, _T_517) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_6 = and(_T_518, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_519 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_520 = eq(_T_519, UInt<3>("h07")) @[pic_ctrl.scala 146:139] + node _T_521 = and(raddr_config_gw_base_match, _T_520) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_7 = and(_T_521, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_522 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_523 = eq(_T_522, UInt<4>("h08")) @[pic_ctrl.scala 146:139] + node _T_524 = and(raddr_config_gw_base_match, _T_523) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_8 = and(_T_524, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_525 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_526 = eq(_T_525, UInt<4>("h09")) @[pic_ctrl.scala 146:139] + node _T_527 = and(raddr_config_gw_base_match, _T_526) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_9 = and(_T_527, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_528 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_529 = eq(_T_528, UInt<4>("h0a")) @[pic_ctrl.scala 146:139] + node _T_530 = and(raddr_config_gw_base_match, _T_529) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_10 = and(_T_530, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_531 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_532 = eq(_T_531, UInt<4>("h0b")) @[pic_ctrl.scala 146:139] + node _T_533 = and(raddr_config_gw_base_match, _T_532) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_11 = and(_T_533, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_534 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_535 = eq(_T_534, UInt<4>("h0c")) @[pic_ctrl.scala 146:139] + node _T_536 = and(raddr_config_gw_base_match, _T_535) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_12 = and(_T_536, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_537 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_538 = eq(_T_537, UInt<4>("h0d")) @[pic_ctrl.scala 146:139] + node _T_539 = and(raddr_config_gw_base_match, _T_538) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_13 = and(_T_539, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_540 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_541 = eq(_T_540, UInt<4>("h0e")) @[pic_ctrl.scala 146:139] + node _T_542 = and(raddr_config_gw_base_match, _T_541) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_14 = and(_T_542, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_543 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_544 = eq(_T_543, UInt<4>("h0f")) @[pic_ctrl.scala 146:139] + node _T_545 = and(raddr_config_gw_base_match, _T_544) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_15 = and(_T_545, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_546 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_547 = eq(_T_546, UInt<5>("h010")) @[pic_ctrl.scala 146:139] + node _T_548 = and(raddr_config_gw_base_match, _T_547) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_16 = and(_T_548, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_549 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_550 = eq(_T_549, UInt<5>("h011")) @[pic_ctrl.scala 146:139] + node _T_551 = and(raddr_config_gw_base_match, _T_550) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_17 = and(_T_551, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_552 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_553 = eq(_T_552, UInt<5>("h012")) @[pic_ctrl.scala 146:139] + node _T_554 = and(raddr_config_gw_base_match, _T_553) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_18 = and(_T_554, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_555 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_556 = eq(_T_555, UInt<5>("h013")) @[pic_ctrl.scala 146:139] + node _T_557 = and(raddr_config_gw_base_match, _T_556) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_19 = and(_T_557, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_558 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_559 = eq(_T_558, UInt<5>("h014")) @[pic_ctrl.scala 146:139] + node _T_560 = and(raddr_config_gw_base_match, _T_559) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_20 = and(_T_560, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_561 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_562 = eq(_T_561, UInt<5>("h015")) @[pic_ctrl.scala 146:139] + node _T_563 = and(raddr_config_gw_base_match, _T_562) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_21 = and(_T_563, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_564 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_565 = eq(_T_564, UInt<5>("h016")) @[pic_ctrl.scala 146:139] + node _T_566 = and(raddr_config_gw_base_match, _T_565) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_22 = and(_T_566, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_567 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_568 = eq(_T_567, UInt<5>("h017")) @[pic_ctrl.scala 146:139] + node _T_569 = and(raddr_config_gw_base_match, _T_568) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_23 = and(_T_569, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_570 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_571 = eq(_T_570, UInt<5>("h018")) @[pic_ctrl.scala 146:139] + node _T_572 = and(raddr_config_gw_base_match, _T_571) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_24 = and(_T_572, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_573 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_574 = eq(_T_573, UInt<5>("h019")) @[pic_ctrl.scala 146:139] + node _T_575 = and(raddr_config_gw_base_match, _T_574) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_25 = and(_T_575, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_576 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_577 = eq(_T_576, UInt<5>("h01a")) @[pic_ctrl.scala 146:139] + node _T_578 = and(raddr_config_gw_base_match, _T_577) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_26 = and(_T_578, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_579 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_580 = eq(_T_579, UInt<5>("h01b")) @[pic_ctrl.scala 146:139] + node _T_581 = and(raddr_config_gw_base_match, _T_580) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_27 = and(_T_581, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_582 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_583 = eq(_T_582, UInt<5>("h01c")) @[pic_ctrl.scala 146:139] + node _T_584 = and(raddr_config_gw_base_match, _T_583) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_28 = and(_T_584, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_585 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_586 = eq(_T_585, UInt<5>("h01d")) @[pic_ctrl.scala 146:139] + node _T_587 = and(raddr_config_gw_base_match, _T_586) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_29 = and(_T_587, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_588 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_589 = eq(_T_588, UInt<5>("h01e")) @[pic_ctrl.scala 146:139] + node _T_590 = and(raddr_config_gw_base_match, _T_589) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_30 = and(_T_590, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_591 = bits(picm_raddr_ff, 6, 2) @[pic_ctrl.scala 146:122] + node _T_592 = eq(_T_591, UInt<5>("h01f")) @[pic_ctrl.scala 146:139] + node _T_593 = and(raddr_config_gw_base_match, _T_592) @[pic_ctrl.scala 146:106] + node gw_config_reg_re_31 = and(_T_593, picm_rden_ff) @[pic_ctrl.scala 146:153] + node _T_594 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_595 = eq(_T_594, UInt<1>("h01")) @[pic_ctrl.scala 147:139] + node _T_596 = and(addr_clear_gw_base_match, _T_595) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_1 = and(_T_596, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_597 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_598 = eq(_T_597, UInt<2>("h02")) @[pic_ctrl.scala 147:139] + node _T_599 = and(addr_clear_gw_base_match, _T_598) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_2 = and(_T_599, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_600 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_601 = eq(_T_600, UInt<2>("h03")) @[pic_ctrl.scala 147:139] + node _T_602 = and(addr_clear_gw_base_match, _T_601) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_3 = and(_T_602, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_603 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_604 = eq(_T_603, UInt<3>("h04")) @[pic_ctrl.scala 147:139] + node _T_605 = and(addr_clear_gw_base_match, _T_604) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_4 = and(_T_605, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_606 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_607 = eq(_T_606, UInt<3>("h05")) @[pic_ctrl.scala 147:139] + node _T_608 = and(addr_clear_gw_base_match, _T_607) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_5 = and(_T_608, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_609 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_610 = eq(_T_609, UInt<3>("h06")) @[pic_ctrl.scala 147:139] + node _T_611 = and(addr_clear_gw_base_match, _T_610) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_6 = and(_T_611, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_612 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_613 = eq(_T_612, UInt<3>("h07")) @[pic_ctrl.scala 147:139] + node _T_614 = and(addr_clear_gw_base_match, _T_613) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_7 = and(_T_614, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_615 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_616 = eq(_T_615, UInt<4>("h08")) @[pic_ctrl.scala 147:139] + node _T_617 = and(addr_clear_gw_base_match, _T_616) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_8 = and(_T_617, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_618 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_619 = eq(_T_618, UInt<4>("h09")) @[pic_ctrl.scala 147:139] + node _T_620 = and(addr_clear_gw_base_match, _T_619) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_9 = and(_T_620, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_621 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_622 = eq(_T_621, UInt<4>("h0a")) @[pic_ctrl.scala 147:139] + node _T_623 = and(addr_clear_gw_base_match, _T_622) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_10 = and(_T_623, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_624 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_625 = eq(_T_624, UInt<4>("h0b")) @[pic_ctrl.scala 147:139] + node _T_626 = and(addr_clear_gw_base_match, _T_625) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_11 = and(_T_626, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_627 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_628 = eq(_T_627, UInt<4>("h0c")) @[pic_ctrl.scala 147:139] + node _T_629 = and(addr_clear_gw_base_match, _T_628) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_12 = and(_T_629, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_630 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_631 = eq(_T_630, UInt<4>("h0d")) @[pic_ctrl.scala 147:139] + node _T_632 = and(addr_clear_gw_base_match, _T_631) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_13 = and(_T_632, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_633 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_634 = eq(_T_633, UInt<4>("h0e")) @[pic_ctrl.scala 147:139] + node _T_635 = and(addr_clear_gw_base_match, _T_634) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_14 = and(_T_635, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_636 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_637 = eq(_T_636, UInt<4>("h0f")) @[pic_ctrl.scala 147:139] + node _T_638 = and(addr_clear_gw_base_match, _T_637) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_15 = and(_T_638, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_639 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_640 = eq(_T_639, UInt<5>("h010")) @[pic_ctrl.scala 147:139] + node _T_641 = and(addr_clear_gw_base_match, _T_640) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_16 = and(_T_641, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_642 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_643 = eq(_T_642, UInt<5>("h011")) @[pic_ctrl.scala 147:139] + node _T_644 = and(addr_clear_gw_base_match, _T_643) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_17 = and(_T_644, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_645 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_646 = eq(_T_645, UInt<5>("h012")) @[pic_ctrl.scala 147:139] + node _T_647 = and(addr_clear_gw_base_match, _T_646) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_18 = and(_T_647, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_648 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_649 = eq(_T_648, UInt<5>("h013")) @[pic_ctrl.scala 147:139] + node _T_650 = and(addr_clear_gw_base_match, _T_649) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_19 = and(_T_650, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_651 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_652 = eq(_T_651, UInt<5>("h014")) @[pic_ctrl.scala 147:139] + node _T_653 = and(addr_clear_gw_base_match, _T_652) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_20 = and(_T_653, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_654 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_655 = eq(_T_654, UInt<5>("h015")) @[pic_ctrl.scala 147:139] + node _T_656 = and(addr_clear_gw_base_match, _T_655) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_21 = and(_T_656, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_657 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_658 = eq(_T_657, UInt<5>("h016")) @[pic_ctrl.scala 147:139] + node _T_659 = and(addr_clear_gw_base_match, _T_658) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_22 = and(_T_659, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_660 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_661 = eq(_T_660, UInt<5>("h017")) @[pic_ctrl.scala 147:139] + node _T_662 = and(addr_clear_gw_base_match, _T_661) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_23 = and(_T_662, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_663 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_664 = eq(_T_663, UInt<5>("h018")) @[pic_ctrl.scala 147:139] + node _T_665 = and(addr_clear_gw_base_match, _T_664) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_24 = and(_T_665, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_666 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_667 = eq(_T_666, UInt<5>("h019")) @[pic_ctrl.scala 147:139] + node _T_668 = and(addr_clear_gw_base_match, _T_667) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_25 = and(_T_668, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_669 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_670 = eq(_T_669, UInt<5>("h01a")) @[pic_ctrl.scala 147:139] + node _T_671 = and(addr_clear_gw_base_match, _T_670) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_26 = and(_T_671, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_672 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_673 = eq(_T_672, UInt<5>("h01b")) @[pic_ctrl.scala 147:139] + node _T_674 = and(addr_clear_gw_base_match, _T_673) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_27 = and(_T_674, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_675 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_676 = eq(_T_675, UInt<5>("h01c")) @[pic_ctrl.scala 147:139] + node _T_677 = and(addr_clear_gw_base_match, _T_676) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_28 = and(_T_677, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_678 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_679 = eq(_T_678, UInt<5>("h01d")) @[pic_ctrl.scala 147:139] + node _T_680 = and(addr_clear_gw_base_match, _T_679) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_29 = and(_T_680, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_681 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_682 = eq(_T_681, UInt<5>("h01e")) @[pic_ctrl.scala 147:139] + node _T_683 = and(addr_clear_gw_base_match, _T_682) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_30 = and(_T_683, picm_wren_ff) @[pic_ctrl.scala 147:153] + node _T_684 = bits(picm_waddr_ff, 6, 2) @[pic_ctrl.scala 147:122] + node _T_685 = eq(_T_684, UInt<5>("h01f")) @[pic_ctrl.scala 147:139] + node _T_686 = and(addr_clear_gw_base_match, _T_685) @[pic_ctrl.scala 147:106] + node gw_clear_reg_we_31 = and(_T_686, picm_wren_ff) @[pic_ctrl.scala 147:153] + wire intpriority_reg : UInt<4>[32] @[pic_ctrl.scala 148:32] + intpriority_reg[0] <= UInt<4>("h00") @[pic_ctrl.scala 149:208] + node _T_687 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_688 = bits(intpriority_reg_we_1, 0, 0) @[pic_ctrl.scala 149:174] reg _T_689 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_688 : @[Reg.scala 28:19] _T_689 <= _T_687 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[1] <= _T_689 @[pic_ctrl.scala 148:71] - node _T_690 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_691 = bits(intpriority_reg_we_2, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[1] <= _T_689 @[pic_ctrl.scala 149:71] + node _T_690 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_691 = bits(intpriority_reg_we_2, 0, 0) @[pic_ctrl.scala 149:174] reg _T_692 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_691 : @[Reg.scala 28:19] _T_692 <= _T_690 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[2] <= _T_692 @[pic_ctrl.scala 148:71] - node _T_693 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_694 = bits(intpriority_reg_we_3, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[2] <= _T_692 @[pic_ctrl.scala 149:71] + node _T_693 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_694 = bits(intpriority_reg_we_3, 0, 0) @[pic_ctrl.scala 149:174] reg _T_695 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_694 : @[Reg.scala 28:19] _T_695 <= _T_693 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[3] <= _T_695 @[pic_ctrl.scala 148:71] - node _T_696 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_697 = bits(intpriority_reg_we_4, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[3] <= _T_695 @[pic_ctrl.scala 149:71] + node _T_696 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_697 = bits(intpriority_reg_we_4, 0, 0) @[pic_ctrl.scala 149:174] reg _T_698 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_697 : @[Reg.scala 28:19] _T_698 <= _T_696 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[4] <= _T_698 @[pic_ctrl.scala 148:71] - node _T_699 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_700 = bits(intpriority_reg_we_5, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[4] <= _T_698 @[pic_ctrl.scala 149:71] + node _T_699 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_700 = bits(intpriority_reg_we_5, 0, 0) @[pic_ctrl.scala 149:174] reg _T_701 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_700 : @[Reg.scala 28:19] _T_701 <= _T_699 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[5] <= _T_701 @[pic_ctrl.scala 148:71] - node _T_702 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_703 = bits(intpriority_reg_we_6, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[5] <= _T_701 @[pic_ctrl.scala 149:71] + node _T_702 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_703 = bits(intpriority_reg_we_6, 0, 0) @[pic_ctrl.scala 149:174] reg _T_704 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_703 : @[Reg.scala 28:19] _T_704 <= _T_702 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[6] <= _T_704 @[pic_ctrl.scala 148:71] - node _T_705 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_706 = bits(intpriority_reg_we_7, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[6] <= _T_704 @[pic_ctrl.scala 149:71] + node _T_705 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_706 = bits(intpriority_reg_we_7, 0, 0) @[pic_ctrl.scala 149:174] reg _T_707 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_706 : @[Reg.scala 28:19] _T_707 <= _T_705 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[7] <= _T_707 @[pic_ctrl.scala 148:71] - node _T_708 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_709 = bits(intpriority_reg_we_8, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[7] <= _T_707 @[pic_ctrl.scala 149:71] + node _T_708 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_709 = bits(intpriority_reg_we_8, 0, 0) @[pic_ctrl.scala 149:174] reg _T_710 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_709 : @[Reg.scala 28:19] _T_710 <= _T_708 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[8] <= _T_710 @[pic_ctrl.scala 148:71] - node _T_711 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_712 = bits(intpriority_reg_we_9, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[8] <= _T_710 @[pic_ctrl.scala 149:71] + node _T_711 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_712 = bits(intpriority_reg_we_9, 0, 0) @[pic_ctrl.scala 149:174] reg _T_713 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_712 : @[Reg.scala 28:19] _T_713 <= _T_711 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[9] <= _T_713 @[pic_ctrl.scala 148:71] - node _T_714 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_715 = bits(intpriority_reg_we_10, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[9] <= _T_713 @[pic_ctrl.scala 149:71] + node _T_714 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_715 = bits(intpriority_reg_we_10, 0, 0) @[pic_ctrl.scala 149:174] reg _T_716 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_715 : @[Reg.scala 28:19] _T_716 <= _T_714 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[10] <= _T_716 @[pic_ctrl.scala 148:71] - node _T_717 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_718 = bits(intpriority_reg_we_11, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[10] <= _T_716 @[pic_ctrl.scala 149:71] + node _T_717 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_718 = bits(intpriority_reg_we_11, 0, 0) @[pic_ctrl.scala 149:174] reg _T_719 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_718 : @[Reg.scala 28:19] _T_719 <= _T_717 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[11] <= _T_719 @[pic_ctrl.scala 148:71] - node _T_720 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_721 = bits(intpriority_reg_we_12, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[11] <= _T_719 @[pic_ctrl.scala 149:71] + node _T_720 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_721 = bits(intpriority_reg_we_12, 0, 0) @[pic_ctrl.scala 149:174] reg _T_722 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_721 : @[Reg.scala 28:19] _T_722 <= _T_720 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[12] <= _T_722 @[pic_ctrl.scala 148:71] - node _T_723 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_724 = bits(intpriority_reg_we_13, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[12] <= _T_722 @[pic_ctrl.scala 149:71] + node _T_723 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_724 = bits(intpriority_reg_we_13, 0, 0) @[pic_ctrl.scala 149:174] reg _T_725 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_724 : @[Reg.scala 28:19] _T_725 <= _T_723 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[13] <= _T_725 @[pic_ctrl.scala 148:71] - node _T_726 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_727 = bits(intpriority_reg_we_14, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[13] <= _T_725 @[pic_ctrl.scala 149:71] + node _T_726 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_727 = bits(intpriority_reg_we_14, 0, 0) @[pic_ctrl.scala 149:174] reg _T_728 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_727 : @[Reg.scala 28:19] _T_728 <= _T_726 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[14] <= _T_728 @[pic_ctrl.scala 148:71] - node _T_729 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_730 = bits(intpriority_reg_we_15, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[14] <= _T_728 @[pic_ctrl.scala 149:71] + node _T_729 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_730 = bits(intpriority_reg_we_15, 0, 0) @[pic_ctrl.scala 149:174] reg _T_731 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_730 : @[Reg.scala 28:19] _T_731 <= _T_729 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[15] <= _T_731 @[pic_ctrl.scala 148:71] - node _T_732 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_733 = bits(intpriority_reg_we_16, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[15] <= _T_731 @[pic_ctrl.scala 149:71] + node _T_732 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_733 = bits(intpriority_reg_we_16, 0, 0) @[pic_ctrl.scala 149:174] reg _T_734 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_733 : @[Reg.scala 28:19] _T_734 <= _T_732 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[16] <= _T_734 @[pic_ctrl.scala 148:71] - node _T_735 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_736 = bits(intpriority_reg_we_17, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[16] <= _T_734 @[pic_ctrl.scala 149:71] + node _T_735 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_736 = bits(intpriority_reg_we_17, 0, 0) @[pic_ctrl.scala 149:174] reg _T_737 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_736 : @[Reg.scala 28:19] _T_737 <= _T_735 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[17] <= _T_737 @[pic_ctrl.scala 148:71] - node _T_738 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_739 = bits(intpriority_reg_we_18, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[17] <= _T_737 @[pic_ctrl.scala 149:71] + node _T_738 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_739 = bits(intpriority_reg_we_18, 0, 0) @[pic_ctrl.scala 149:174] reg _T_740 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_739 : @[Reg.scala 28:19] _T_740 <= _T_738 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[18] <= _T_740 @[pic_ctrl.scala 148:71] - node _T_741 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_742 = bits(intpriority_reg_we_19, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[18] <= _T_740 @[pic_ctrl.scala 149:71] + node _T_741 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_742 = bits(intpriority_reg_we_19, 0, 0) @[pic_ctrl.scala 149:174] reg _T_743 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_742 : @[Reg.scala 28:19] _T_743 <= _T_741 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[19] <= _T_743 @[pic_ctrl.scala 148:71] - node _T_744 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_745 = bits(intpriority_reg_we_20, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[19] <= _T_743 @[pic_ctrl.scala 149:71] + node _T_744 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_745 = bits(intpriority_reg_we_20, 0, 0) @[pic_ctrl.scala 149:174] reg _T_746 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_745 : @[Reg.scala 28:19] _T_746 <= _T_744 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[20] <= _T_746 @[pic_ctrl.scala 148:71] - node _T_747 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_748 = bits(intpriority_reg_we_21, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[20] <= _T_746 @[pic_ctrl.scala 149:71] + node _T_747 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_748 = bits(intpriority_reg_we_21, 0, 0) @[pic_ctrl.scala 149:174] reg _T_749 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_748 : @[Reg.scala 28:19] _T_749 <= _T_747 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[21] <= _T_749 @[pic_ctrl.scala 148:71] - node _T_750 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_751 = bits(intpriority_reg_we_22, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[21] <= _T_749 @[pic_ctrl.scala 149:71] + node _T_750 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_751 = bits(intpriority_reg_we_22, 0, 0) @[pic_ctrl.scala 149:174] reg _T_752 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_751 : @[Reg.scala 28:19] _T_752 <= _T_750 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[22] <= _T_752 @[pic_ctrl.scala 148:71] - node _T_753 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_754 = bits(intpriority_reg_we_23, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[22] <= _T_752 @[pic_ctrl.scala 149:71] + node _T_753 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_754 = bits(intpriority_reg_we_23, 0, 0) @[pic_ctrl.scala 149:174] reg _T_755 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_754 : @[Reg.scala 28:19] _T_755 <= _T_753 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[23] <= _T_755 @[pic_ctrl.scala 148:71] - node _T_756 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_757 = bits(intpriority_reg_we_24, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[23] <= _T_755 @[pic_ctrl.scala 149:71] + node _T_756 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_757 = bits(intpriority_reg_we_24, 0, 0) @[pic_ctrl.scala 149:174] reg _T_758 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_757 : @[Reg.scala 28:19] _T_758 <= _T_756 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[24] <= _T_758 @[pic_ctrl.scala 148:71] - node _T_759 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_760 = bits(intpriority_reg_we_25, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[24] <= _T_758 @[pic_ctrl.scala 149:71] + node _T_759 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_760 = bits(intpriority_reg_we_25, 0, 0) @[pic_ctrl.scala 149:174] reg _T_761 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_760 : @[Reg.scala 28:19] _T_761 <= _T_759 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[25] <= _T_761 @[pic_ctrl.scala 148:71] - node _T_762 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_763 = bits(intpriority_reg_we_26, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[25] <= _T_761 @[pic_ctrl.scala 149:71] + node _T_762 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_763 = bits(intpriority_reg_we_26, 0, 0) @[pic_ctrl.scala 149:174] reg _T_764 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_763 : @[Reg.scala 28:19] _T_764 <= _T_762 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[26] <= _T_764 @[pic_ctrl.scala 148:71] - node _T_765 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_766 = bits(intpriority_reg_we_27, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[26] <= _T_764 @[pic_ctrl.scala 149:71] + node _T_765 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_766 = bits(intpriority_reg_we_27, 0, 0) @[pic_ctrl.scala 149:174] reg _T_767 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_766 : @[Reg.scala 28:19] _T_767 <= _T_765 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[27] <= _T_767 @[pic_ctrl.scala 148:71] - node _T_768 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_769 = bits(intpriority_reg_we_28, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[27] <= _T_767 @[pic_ctrl.scala 149:71] + node _T_768 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_769 = bits(intpriority_reg_we_28, 0, 0) @[pic_ctrl.scala 149:174] reg _T_770 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_769 : @[Reg.scala 28:19] _T_770 <= _T_768 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[28] <= _T_770 @[pic_ctrl.scala 148:71] - node _T_771 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_772 = bits(intpriority_reg_we_29, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[28] <= _T_770 @[pic_ctrl.scala 149:71] + node _T_771 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_772 = bits(intpriority_reg_we_29, 0, 0) @[pic_ctrl.scala 149:174] reg _T_773 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_772 : @[Reg.scala 28:19] _T_773 <= _T_771 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[29] <= _T_773 @[pic_ctrl.scala 148:71] - node _T_774 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_775 = bits(intpriority_reg_we_30, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[29] <= _T_773 @[pic_ctrl.scala 149:71] + node _T_774 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_775 = bits(intpriority_reg_we_30, 0, 0) @[pic_ctrl.scala 149:174] reg _T_776 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_775 : @[Reg.scala 28:19] _T_776 <= _T_774 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[30] <= _T_776 @[pic_ctrl.scala 148:71] - node _T_777 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 148:125] - node _T_778 = bits(intpriority_reg_we_31, 0, 0) @[pic_ctrl.scala 148:174] + intpriority_reg[30] <= _T_776 @[pic_ctrl.scala 149:71] + node _T_777 = bits(picm_wr_data_ff, 3, 0) @[pic_ctrl.scala 149:125] + node _T_778 = bits(intpriority_reg_we_31, 0, 0) @[pic_ctrl.scala 149:174] reg _T_779 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_778 : @[Reg.scala 28:19] _T_779 <= _T_777 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intpriority_reg[31] <= _T_779 @[pic_ctrl.scala 148:71] - wire intenable_reg : UInt<1>[32] @[pic_ctrl.scala 149:32] - intenable_reg[0] <= UInt<1>("h00") @[pic_ctrl.scala 150:182] - node _T_780 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_781 = bits(intenable_reg_we_1, 0, 0) @[pic_ctrl.scala 150:150] + intpriority_reg[31] <= _T_779 @[pic_ctrl.scala 149:71] + wire intenable_reg : UInt<1>[32] @[pic_ctrl.scala 150:32] + intenable_reg[0] <= UInt<1>("h00") @[pic_ctrl.scala 151:182] + node _T_780 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_781 = bits(intenable_reg_we_1, 0, 0) @[pic_ctrl.scala 151:150] reg _T_782 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_781 : @[Reg.scala 28:19] _T_782 <= _T_780 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[1] <= _T_782 @[pic_ctrl.scala 150:68] - node _T_783 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_784 = bits(intenable_reg_we_2, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[1] <= _T_782 @[pic_ctrl.scala 151:68] + node _T_783 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_784 = bits(intenable_reg_we_2, 0, 0) @[pic_ctrl.scala 151:150] reg _T_785 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_784 : @[Reg.scala 28:19] _T_785 <= _T_783 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[2] <= _T_785 @[pic_ctrl.scala 150:68] - node _T_786 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_787 = bits(intenable_reg_we_3, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[2] <= _T_785 @[pic_ctrl.scala 151:68] + node _T_786 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_787 = bits(intenable_reg_we_3, 0, 0) @[pic_ctrl.scala 151:150] reg _T_788 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_787 : @[Reg.scala 28:19] _T_788 <= _T_786 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[3] <= _T_788 @[pic_ctrl.scala 150:68] - node _T_789 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_790 = bits(intenable_reg_we_4, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[3] <= _T_788 @[pic_ctrl.scala 151:68] + node _T_789 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_790 = bits(intenable_reg_we_4, 0, 0) @[pic_ctrl.scala 151:150] reg _T_791 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_790 : @[Reg.scala 28:19] _T_791 <= _T_789 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[4] <= _T_791 @[pic_ctrl.scala 150:68] - node _T_792 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_793 = bits(intenable_reg_we_5, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[4] <= _T_791 @[pic_ctrl.scala 151:68] + node _T_792 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_793 = bits(intenable_reg_we_5, 0, 0) @[pic_ctrl.scala 151:150] reg _T_794 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_793 : @[Reg.scala 28:19] _T_794 <= _T_792 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[5] <= _T_794 @[pic_ctrl.scala 150:68] - node _T_795 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_796 = bits(intenable_reg_we_6, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[5] <= _T_794 @[pic_ctrl.scala 151:68] + node _T_795 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_796 = bits(intenable_reg_we_6, 0, 0) @[pic_ctrl.scala 151:150] reg _T_797 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_796 : @[Reg.scala 28:19] _T_797 <= _T_795 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[6] <= _T_797 @[pic_ctrl.scala 150:68] - node _T_798 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_799 = bits(intenable_reg_we_7, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[6] <= _T_797 @[pic_ctrl.scala 151:68] + node _T_798 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_799 = bits(intenable_reg_we_7, 0, 0) @[pic_ctrl.scala 151:150] reg _T_800 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_799 : @[Reg.scala 28:19] _T_800 <= _T_798 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[7] <= _T_800 @[pic_ctrl.scala 150:68] - node _T_801 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_802 = bits(intenable_reg_we_8, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[7] <= _T_800 @[pic_ctrl.scala 151:68] + node _T_801 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_802 = bits(intenable_reg_we_8, 0, 0) @[pic_ctrl.scala 151:150] reg _T_803 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_802 : @[Reg.scala 28:19] _T_803 <= _T_801 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[8] <= _T_803 @[pic_ctrl.scala 150:68] - node _T_804 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_805 = bits(intenable_reg_we_9, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[8] <= _T_803 @[pic_ctrl.scala 151:68] + node _T_804 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_805 = bits(intenable_reg_we_9, 0, 0) @[pic_ctrl.scala 151:150] reg _T_806 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_805 : @[Reg.scala 28:19] _T_806 <= _T_804 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[9] <= _T_806 @[pic_ctrl.scala 150:68] - node _T_807 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_808 = bits(intenable_reg_we_10, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[9] <= _T_806 @[pic_ctrl.scala 151:68] + node _T_807 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_808 = bits(intenable_reg_we_10, 0, 0) @[pic_ctrl.scala 151:150] reg _T_809 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_808 : @[Reg.scala 28:19] _T_809 <= _T_807 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[10] <= _T_809 @[pic_ctrl.scala 150:68] - node _T_810 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_811 = bits(intenable_reg_we_11, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[10] <= _T_809 @[pic_ctrl.scala 151:68] + node _T_810 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_811 = bits(intenable_reg_we_11, 0, 0) @[pic_ctrl.scala 151:150] reg _T_812 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_811 : @[Reg.scala 28:19] _T_812 <= _T_810 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[11] <= _T_812 @[pic_ctrl.scala 150:68] - node _T_813 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_814 = bits(intenable_reg_we_12, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[11] <= _T_812 @[pic_ctrl.scala 151:68] + node _T_813 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_814 = bits(intenable_reg_we_12, 0, 0) @[pic_ctrl.scala 151:150] reg _T_815 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_814 : @[Reg.scala 28:19] _T_815 <= _T_813 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[12] <= _T_815 @[pic_ctrl.scala 150:68] - node _T_816 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_817 = bits(intenable_reg_we_13, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[12] <= _T_815 @[pic_ctrl.scala 151:68] + node _T_816 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_817 = bits(intenable_reg_we_13, 0, 0) @[pic_ctrl.scala 151:150] reg _T_818 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_817 : @[Reg.scala 28:19] _T_818 <= _T_816 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[13] <= _T_818 @[pic_ctrl.scala 150:68] - node _T_819 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_820 = bits(intenable_reg_we_14, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[13] <= _T_818 @[pic_ctrl.scala 151:68] + node _T_819 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_820 = bits(intenable_reg_we_14, 0, 0) @[pic_ctrl.scala 151:150] reg _T_821 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_820 : @[Reg.scala 28:19] _T_821 <= _T_819 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[14] <= _T_821 @[pic_ctrl.scala 150:68] - node _T_822 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_823 = bits(intenable_reg_we_15, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[14] <= _T_821 @[pic_ctrl.scala 151:68] + node _T_822 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_823 = bits(intenable_reg_we_15, 0, 0) @[pic_ctrl.scala 151:150] reg _T_824 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_823 : @[Reg.scala 28:19] _T_824 <= _T_822 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[15] <= _T_824 @[pic_ctrl.scala 150:68] - node _T_825 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_826 = bits(intenable_reg_we_16, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[15] <= _T_824 @[pic_ctrl.scala 151:68] + node _T_825 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_826 = bits(intenable_reg_we_16, 0, 0) @[pic_ctrl.scala 151:150] reg _T_827 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_826 : @[Reg.scala 28:19] _T_827 <= _T_825 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[16] <= _T_827 @[pic_ctrl.scala 150:68] - node _T_828 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_829 = bits(intenable_reg_we_17, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[16] <= _T_827 @[pic_ctrl.scala 151:68] + node _T_828 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_829 = bits(intenable_reg_we_17, 0, 0) @[pic_ctrl.scala 151:150] reg _T_830 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_829 : @[Reg.scala 28:19] _T_830 <= _T_828 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[17] <= _T_830 @[pic_ctrl.scala 150:68] - node _T_831 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_832 = bits(intenable_reg_we_18, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[17] <= _T_830 @[pic_ctrl.scala 151:68] + node _T_831 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_832 = bits(intenable_reg_we_18, 0, 0) @[pic_ctrl.scala 151:150] reg _T_833 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_832 : @[Reg.scala 28:19] _T_833 <= _T_831 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[18] <= _T_833 @[pic_ctrl.scala 150:68] - node _T_834 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_835 = bits(intenable_reg_we_19, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[18] <= _T_833 @[pic_ctrl.scala 151:68] + node _T_834 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_835 = bits(intenable_reg_we_19, 0, 0) @[pic_ctrl.scala 151:150] reg _T_836 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_835 : @[Reg.scala 28:19] _T_836 <= _T_834 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[19] <= _T_836 @[pic_ctrl.scala 150:68] - node _T_837 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_838 = bits(intenable_reg_we_20, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[19] <= _T_836 @[pic_ctrl.scala 151:68] + node _T_837 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_838 = bits(intenable_reg_we_20, 0, 0) @[pic_ctrl.scala 151:150] reg _T_839 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_838 : @[Reg.scala 28:19] _T_839 <= _T_837 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[20] <= _T_839 @[pic_ctrl.scala 150:68] - node _T_840 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_841 = bits(intenable_reg_we_21, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[20] <= _T_839 @[pic_ctrl.scala 151:68] + node _T_840 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_841 = bits(intenable_reg_we_21, 0, 0) @[pic_ctrl.scala 151:150] reg _T_842 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_841 : @[Reg.scala 28:19] _T_842 <= _T_840 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[21] <= _T_842 @[pic_ctrl.scala 150:68] - node _T_843 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_844 = bits(intenable_reg_we_22, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[21] <= _T_842 @[pic_ctrl.scala 151:68] + node _T_843 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_844 = bits(intenable_reg_we_22, 0, 0) @[pic_ctrl.scala 151:150] reg _T_845 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_844 : @[Reg.scala 28:19] _T_845 <= _T_843 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[22] <= _T_845 @[pic_ctrl.scala 150:68] - node _T_846 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_847 = bits(intenable_reg_we_23, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[22] <= _T_845 @[pic_ctrl.scala 151:68] + node _T_846 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_847 = bits(intenable_reg_we_23, 0, 0) @[pic_ctrl.scala 151:150] reg _T_848 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_847 : @[Reg.scala 28:19] _T_848 <= _T_846 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[23] <= _T_848 @[pic_ctrl.scala 150:68] - node _T_849 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_850 = bits(intenable_reg_we_24, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[23] <= _T_848 @[pic_ctrl.scala 151:68] + node _T_849 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_850 = bits(intenable_reg_we_24, 0, 0) @[pic_ctrl.scala 151:150] reg _T_851 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_850 : @[Reg.scala 28:19] _T_851 <= _T_849 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[24] <= _T_851 @[pic_ctrl.scala 150:68] - node _T_852 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_853 = bits(intenable_reg_we_25, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[24] <= _T_851 @[pic_ctrl.scala 151:68] + node _T_852 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_853 = bits(intenable_reg_we_25, 0, 0) @[pic_ctrl.scala 151:150] reg _T_854 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_853 : @[Reg.scala 28:19] _T_854 <= _T_852 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[25] <= _T_854 @[pic_ctrl.scala 150:68] - node _T_855 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_856 = bits(intenable_reg_we_26, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[25] <= _T_854 @[pic_ctrl.scala 151:68] + node _T_855 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_856 = bits(intenable_reg_we_26, 0, 0) @[pic_ctrl.scala 151:150] reg _T_857 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_856 : @[Reg.scala 28:19] _T_857 <= _T_855 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[26] <= _T_857 @[pic_ctrl.scala 150:68] - node _T_858 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_859 = bits(intenable_reg_we_27, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[26] <= _T_857 @[pic_ctrl.scala 151:68] + node _T_858 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_859 = bits(intenable_reg_we_27, 0, 0) @[pic_ctrl.scala 151:150] reg _T_860 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_859 : @[Reg.scala 28:19] _T_860 <= _T_858 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[27] <= _T_860 @[pic_ctrl.scala 150:68] - node _T_861 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_862 = bits(intenable_reg_we_28, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[27] <= _T_860 @[pic_ctrl.scala 151:68] + node _T_861 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_862 = bits(intenable_reg_we_28, 0, 0) @[pic_ctrl.scala 151:150] reg _T_863 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_862 : @[Reg.scala 28:19] _T_863 <= _T_861 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[28] <= _T_863 @[pic_ctrl.scala 150:68] - node _T_864 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_865 = bits(intenable_reg_we_29, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[28] <= _T_863 @[pic_ctrl.scala 151:68] + node _T_864 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_865 = bits(intenable_reg_we_29, 0, 0) @[pic_ctrl.scala 151:150] reg _T_866 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_865 : @[Reg.scala 28:19] _T_866 <= _T_864 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[29] <= _T_866 @[pic_ctrl.scala 150:68] - node _T_867 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_868 = bits(intenable_reg_we_30, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[29] <= _T_866 @[pic_ctrl.scala 151:68] + node _T_867 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_868 = bits(intenable_reg_we_30, 0, 0) @[pic_ctrl.scala 151:150] reg _T_869 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_868 : @[Reg.scala 28:19] _T_869 <= _T_867 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[30] <= _T_869 @[pic_ctrl.scala 150:68] - node _T_870 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 150:122] - node _T_871 = bits(intenable_reg_we_31, 0, 0) @[pic_ctrl.scala 150:150] + intenable_reg[30] <= _T_869 @[pic_ctrl.scala 151:68] + node _T_870 = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 151:122] + node _T_871 = bits(intenable_reg_we_31, 0, 0) @[pic_ctrl.scala 151:150] reg _T_872 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_871 : @[Reg.scala 28:19] _T_872 <= _T_870 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - intenable_reg[31] <= _T_872 @[pic_ctrl.scala 150:68] - wire gw_config_reg : UInt<2>[32] @[pic_ctrl.scala 151:32] - gw_config_reg[0] <= UInt<2>("h00") @[pic_ctrl.scala 152:190] - node _T_873 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_874 = bits(gw_config_reg_we_1, 0, 0) @[pic_ctrl.scala 152:156] + intenable_reg[31] <= _T_872 @[pic_ctrl.scala 151:68] + wire gw_config_reg : UInt<2>[32] @[pic_ctrl.scala 152:32] + gw_config_reg[0] <= UInt<2>("h00") @[pic_ctrl.scala 153:190] + node _T_873 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_874 = bits(gw_config_reg_we_1, 0, 0) @[pic_ctrl.scala 153:156] reg _T_875 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_874 : @[Reg.scala 28:19] _T_875 <= _T_873 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[1] <= _T_875 @[pic_ctrl.scala 152:70] - node _T_876 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_877 = bits(gw_config_reg_we_2, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[1] <= _T_875 @[pic_ctrl.scala 153:70] + node _T_876 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_877 = bits(gw_config_reg_we_2, 0, 0) @[pic_ctrl.scala 153:156] reg _T_878 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_877 : @[Reg.scala 28:19] _T_878 <= _T_876 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[2] <= _T_878 @[pic_ctrl.scala 152:70] - node _T_879 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_880 = bits(gw_config_reg_we_3, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[2] <= _T_878 @[pic_ctrl.scala 153:70] + node _T_879 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_880 = bits(gw_config_reg_we_3, 0, 0) @[pic_ctrl.scala 153:156] reg _T_881 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_880 : @[Reg.scala 28:19] _T_881 <= _T_879 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[3] <= _T_881 @[pic_ctrl.scala 152:70] - node _T_882 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_883 = bits(gw_config_reg_we_4, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[3] <= _T_881 @[pic_ctrl.scala 153:70] + node _T_882 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_883 = bits(gw_config_reg_we_4, 0, 0) @[pic_ctrl.scala 153:156] reg _T_884 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_883 : @[Reg.scala 28:19] _T_884 <= _T_882 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[4] <= _T_884 @[pic_ctrl.scala 152:70] - node _T_885 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_886 = bits(gw_config_reg_we_5, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[4] <= _T_884 @[pic_ctrl.scala 153:70] + node _T_885 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_886 = bits(gw_config_reg_we_5, 0, 0) @[pic_ctrl.scala 153:156] reg _T_887 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_886 : @[Reg.scala 28:19] _T_887 <= _T_885 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[5] <= _T_887 @[pic_ctrl.scala 152:70] - node _T_888 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_889 = bits(gw_config_reg_we_6, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[5] <= _T_887 @[pic_ctrl.scala 153:70] + node _T_888 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_889 = bits(gw_config_reg_we_6, 0, 0) @[pic_ctrl.scala 153:156] reg _T_890 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_889 : @[Reg.scala 28:19] _T_890 <= _T_888 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[6] <= _T_890 @[pic_ctrl.scala 152:70] - node _T_891 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_892 = bits(gw_config_reg_we_7, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[6] <= _T_890 @[pic_ctrl.scala 153:70] + node _T_891 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_892 = bits(gw_config_reg_we_7, 0, 0) @[pic_ctrl.scala 153:156] reg _T_893 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_892 : @[Reg.scala 28:19] _T_893 <= _T_891 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[7] <= _T_893 @[pic_ctrl.scala 152:70] - node _T_894 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_895 = bits(gw_config_reg_we_8, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[7] <= _T_893 @[pic_ctrl.scala 153:70] + node _T_894 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_895 = bits(gw_config_reg_we_8, 0, 0) @[pic_ctrl.scala 153:156] reg _T_896 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_895 : @[Reg.scala 28:19] _T_896 <= _T_894 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[8] <= _T_896 @[pic_ctrl.scala 152:70] - node _T_897 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_898 = bits(gw_config_reg_we_9, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[8] <= _T_896 @[pic_ctrl.scala 153:70] + node _T_897 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_898 = bits(gw_config_reg_we_9, 0, 0) @[pic_ctrl.scala 153:156] reg _T_899 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_898 : @[Reg.scala 28:19] _T_899 <= _T_897 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[9] <= _T_899 @[pic_ctrl.scala 152:70] - node _T_900 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_901 = bits(gw_config_reg_we_10, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[9] <= _T_899 @[pic_ctrl.scala 153:70] + node _T_900 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_901 = bits(gw_config_reg_we_10, 0, 0) @[pic_ctrl.scala 153:156] reg _T_902 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_901 : @[Reg.scala 28:19] _T_902 <= _T_900 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[10] <= _T_902 @[pic_ctrl.scala 152:70] - node _T_903 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_904 = bits(gw_config_reg_we_11, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[10] <= _T_902 @[pic_ctrl.scala 153:70] + node _T_903 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_904 = bits(gw_config_reg_we_11, 0, 0) @[pic_ctrl.scala 153:156] reg _T_905 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_904 : @[Reg.scala 28:19] _T_905 <= _T_903 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[11] <= _T_905 @[pic_ctrl.scala 152:70] - node _T_906 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_907 = bits(gw_config_reg_we_12, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[11] <= _T_905 @[pic_ctrl.scala 153:70] + node _T_906 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_907 = bits(gw_config_reg_we_12, 0, 0) @[pic_ctrl.scala 153:156] reg _T_908 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_907 : @[Reg.scala 28:19] _T_908 <= _T_906 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[12] <= _T_908 @[pic_ctrl.scala 152:70] - node _T_909 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_910 = bits(gw_config_reg_we_13, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[12] <= _T_908 @[pic_ctrl.scala 153:70] + node _T_909 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_910 = bits(gw_config_reg_we_13, 0, 0) @[pic_ctrl.scala 153:156] reg _T_911 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_910 : @[Reg.scala 28:19] _T_911 <= _T_909 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[13] <= _T_911 @[pic_ctrl.scala 152:70] - node _T_912 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_913 = bits(gw_config_reg_we_14, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[13] <= _T_911 @[pic_ctrl.scala 153:70] + node _T_912 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_913 = bits(gw_config_reg_we_14, 0, 0) @[pic_ctrl.scala 153:156] reg _T_914 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_913 : @[Reg.scala 28:19] _T_914 <= _T_912 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[14] <= _T_914 @[pic_ctrl.scala 152:70] - node _T_915 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_916 = bits(gw_config_reg_we_15, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[14] <= _T_914 @[pic_ctrl.scala 153:70] + node _T_915 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_916 = bits(gw_config_reg_we_15, 0, 0) @[pic_ctrl.scala 153:156] reg _T_917 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_916 : @[Reg.scala 28:19] _T_917 <= _T_915 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[15] <= _T_917 @[pic_ctrl.scala 152:70] - node _T_918 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_919 = bits(gw_config_reg_we_16, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[15] <= _T_917 @[pic_ctrl.scala 153:70] + node _T_918 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_919 = bits(gw_config_reg_we_16, 0, 0) @[pic_ctrl.scala 153:156] reg _T_920 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_919 : @[Reg.scala 28:19] _T_920 <= _T_918 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[16] <= _T_920 @[pic_ctrl.scala 152:70] - node _T_921 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_922 = bits(gw_config_reg_we_17, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[16] <= _T_920 @[pic_ctrl.scala 153:70] + node _T_921 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_922 = bits(gw_config_reg_we_17, 0, 0) @[pic_ctrl.scala 153:156] reg _T_923 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_922 : @[Reg.scala 28:19] _T_923 <= _T_921 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[17] <= _T_923 @[pic_ctrl.scala 152:70] - node _T_924 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_925 = bits(gw_config_reg_we_18, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[17] <= _T_923 @[pic_ctrl.scala 153:70] + node _T_924 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_925 = bits(gw_config_reg_we_18, 0, 0) @[pic_ctrl.scala 153:156] reg _T_926 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_925 : @[Reg.scala 28:19] _T_926 <= _T_924 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[18] <= _T_926 @[pic_ctrl.scala 152:70] - node _T_927 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_928 = bits(gw_config_reg_we_19, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[18] <= _T_926 @[pic_ctrl.scala 153:70] + node _T_927 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_928 = bits(gw_config_reg_we_19, 0, 0) @[pic_ctrl.scala 153:156] reg _T_929 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_928 : @[Reg.scala 28:19] _T_929 <= _T_927 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[19] <= _T_929 @[pic_ctrl.scala 152:70] - node _T_930 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_931 = bits(gw_config_reg_we_20, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[19] <= _T_929 @[pic_ctrl.scala 153:70] + node _T_930 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_931 = bits(gw_config_reg_we_20, 0, 0) @[pic_ctrl.scala 153:156] reg _T_932 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_931 : @[Reg.scala 28:19] _T_932 <= _T_930 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[20] <= _T_932 @[pic_ctrl.scala 152:70] - node _T_933 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_934 = bits(gw_config_reg_we_21, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[20] <= _T_932 @[pic_ctrl.scala 153:70] + node _T_933 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_934 = bits(gw_config_reg_we_21, 0, 0) @[pic_ctrl.scala 153:156] reg _T_935 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_934 : @[Reg.scala 28:19] _T_935 <= _T_933 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[21] <= _T_935 @[pic_ctrl.scala 152:70] - node _T_936 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_937 = bits(gw_config_reg_we_22, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[21] <= _T_935 @[pic_ctrl.scala 153:70] + node _T_936 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_937 = bits(gw_config_reg_we_22, 0, 0) @[pic_ctrl.scala 153:156] reg _T_938 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_937 : @[Reg.scala 28:19] _T_938 <= _T_936 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[22] <= _T_938 @[pic_ctrl.scala 152:70] - node _T_939 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_940 = bits(gw_config_reg_we_23, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[22] <= _T_938 @[pic_ctrl.scala 153:70] + node _T_939 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_940 = bits(gw_config_reg_we_23, 0, 0) @[pic_ctrl.scala 153:156] reg _T_941 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_940 : @[Reg.scala 28:19] _T_941 <= _T_939 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[23] <= _T_941 @[pic_ctrl.scala 152:70] - node _T_942 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_943 = bits(gw_config_reg_we_24, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[23] <= _T_941 @[pic_ctrl.scala 153:70] + node _T_942 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_943 = bits(gw_config_reg_we_24, 0, 0) @[pic_ctrl.scala 153:156] reg _T_944 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_943 : @[Reg.scala 28:19] _T_944 <= _T_942 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[24] <= _T_944 @[pic_ctrl.scala 152:70] - node _T_945 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_946 = bits(gw_config_reg_we_25, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[24] <= _T_944 @[pic_ctrl.scala 153:70] + node _T_945 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_946 = bits(gw_config_reg_we_25, 0, 0) @[pic_ctrl.scala 153:156] reg _T_947 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_946 : @[Reg.scala 28:19] _T_947 <= _T_945 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[25] <= _T_947 @[pic_ctrl.scala 152:70] - node _T_948 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_949 = bits(gw_config_reg_we_26, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[25] <= _T_947 @[pic_ctrl.scala 153:70] + node _T_948 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_949 = bits(gw_config_reg_we_26, 0, 0) @[pic_ctrl.scala 153:156] reg _T_950 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_949 : @[Reg.scala 28:19] _T_950 <= _T_948 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[26] <= _T_950 @[pic_ctrl.scala 152:70] - node _T_951 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_952 = bits(gw_config_reg_we_27, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[26] <= _T_950 @[pic_ctrl.scala 153:70] + node _T_951 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_952 = bits(gw_config_reg_we_27, 0, 0) @[pic_ctrl.scala 153:156] reg _T_953 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_952 : @[Reg.scala 28:19] _T_953 <= _T_951 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[27] <= _T_953 @[pic_ctrl.scala 152:70] - node _T_954 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_955 = bits(gw_config_reg_we_28, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[27] <= _T_953 @[pic_ctrl.scala 153:70] + node _T_954 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_955 = bits(gw_config_reg_we_28, 0, 0) @[pic_ctrl.scala 153:156] reg _T_956 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_955 : @[Reg.scala 28:19] _T_956 <= _T_954 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[28] <= _T_956 @[pic_ctrl.scala 152:70] - node _T_957 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_958 = bits(gw_config_reg_we_29, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[28] <= _T_956 @[pic_ctrl.scala 153:70] + node _T_957 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_958 = bits(gw_config_reg_we_29, 0, 0) @[pic_ctrl.scala 153:156] reg _T_959 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_958 : @[Reg.scala 28:19] _T_959 <= _T_957 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[29] <= _T_959 @[pic_ctrl.scala 152:70] - node _T_960 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_961 = bits(gw_config_reg_we_30, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[29] <= _T_959 @[pic_ctrl.scala 153:70] + node _T_960 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_961 = bits(gw_config_reg_we_30, 0, 0) @[pic_ctrl.scala 153:156] reg _T_962 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_961 : @[Reg.scala 28:19] _T_962 <= _T_960 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[30] <= _T_962 @[pic_ctrl.scala 152:70] - node _T_963 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 152:126] - node _T_964 = bits(gw_config_reg_we_31, 0, 0) @[pic_ctrl.scala 152:156] + gw_config_reg[30] <= _T_962 @[pic_ctrl.scala 153:70] + node _T_963 = bits(picm_wr_data_ff, 1, 0) @[pic_ctrl.scala 153:126] + node _T_964 = bits(gw_config_reg_we_31, 0, 0) @[pic_ctrl.scala 153:156] reg _T_965 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_964 : @[Reg.scala 28:19] _T_965 <= _T_963 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - gw_config_reg[31] <= _T_965 @[pic_ctrl.scala 152:70] - node _T_966 = bits(extintsrc_req_sync, 1, 1) @[pic_ctrl.scala 155:52] - node _T_967 = bits(gw_config_reg[1], 0, 0) @[pic_ctrl.scala 155:73] - node _T_968 = bits(gw_config_reg[1], 1, 1) @[pic_ctrl.scala 155:94] - node _T_969 = bits(gw_clear_reg_we_1, 0, 0) @[pic_ctrl.scala 155:124] + gw_config_reg[31] <= _T_965 @[pic_ctrl.scala 153:70] + node _T_966 = bits(extintsrc_req_sync, 1, 1) @[pic_ctrl.scala 156:52] + node _T_967 = bits(gw_config_reg[1], 0, 0) @[pic_ctrl.scala 156:73] + node _T_968 = bits(gw_config_reg[1], 1, 1) @[pic_ctrl.scala 156:94] + node _T_969 = bits(gw_clear_reg_we_1, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending : UInt<1> gw_int_pending <= UInt<1>("h00") - node _T_970 = xor(_T_966, _T_967) @[pic_ctrl.scala 30:50] - node _T_971 = eq(_T_969, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_972 = and(gw_int_pending, _T_971) @[pic_ctrl.scala 30:90] - node gw_int_pending_in = or(_T_970, _T_972) @[pic_ctrl.scala 30:72] - reg _T_973 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_973 <= gw_int_pending_in @[pic_ctrl.scala 31:45] - gw_int_pending <= _T_973 @[pic_ctrl.scala 31:20] - node _T_974 = bits(_T_968, 0, 0) @[pic_ctrl.scala 32:30] - node _T_975 = xor(_T_966, _T_967) @[pic_ctrl.scala 32:55] - node _T_976 = or(_T_975, gw_int_pending) @[pic_ctrl.scala 32:78] - node _T_977 = xor(_T_966, _T_967) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_1 = mux(_T_974, _T_976, _T_977) @[pic_ctrl.scala 32:8] - node _T_978 = bits(extintsrc_req_sync, 2, 2) @[pic_ctrl.scala 155:52] - node _T_979 = bits(gw_config_reg[2], 0, 0) @[pic_ctrl.scala 155:73] - node _T_980 = bits(gw_config_reg[2], 1, 1) @[pic_ctrl.scala 155:94] - node _T_981 = bits(gw_clear_reg_we_2, 0, 0) @[pic_ctrl.scala 155:124] + node _T_970 = xor(_T_966, _T_967) @[pic_ctrl.scala 31:50] + node _T_971 = eq(_T_969, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_972 = and(gw_int_pending, _T_971) @[pic_ctrl.scala 31:90] + node gw_int_pending_in = or(_T_970, _T_972) @[pic_ctrl.scala 31:72] + reg _T_973 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_973 <= gw_int_pending_in @[pic_ctrl.scala 32:45] + gw_int_pending <= _T_973 @[pic_ctrl.scala 32:20] + node _T_974 = bits(_T_968, 0, 0) @[pic_ctrl.scala 33:30] + node _T_975 = xor(_T_966, _T_967) @[pic_ctrl.scala 33:55] + node _T_976 = or(_T_975, gw_int_pending) @[pic_ctrl.scala 33:78] + node _T_977 = xor(_T_966, _T_967) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_1 = mux(_T_974, _T_976, _T_977) @[pic_ctrl.scala 33:8] + node _T_978 = bits(extintsrc_req_sync, 2, 2) @[pic_ctrl.scala 156:52] + node _T_979 = bits(gw_config_reg[2], 0, 0) @[pic_ctrl.scala 156:73] + node _T_980 = bits(gw_config_reg[2], 1, 1) @[pic_ctrl.scala 156:94] + node _T_981 = bits(gw_clear_reg_we_2, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_1 : UInt<1> gw_int_pending_1 <= UInt<1>("h00") - node _T_982 = xor(_T_978, _T_979) @[pic_ctrl.scala 30:50] - node _T_983 = eq(_T_981, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_984 = and(gw_int_pending_1, _T_983) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_1 = or(_T_982, _T_984) @[pic_ctrl.scala 30:72] - reg _T_985 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_985 <= gw_int_pending_in_1 @[pic_ctrl.scala 31:45] - gw_int_pending_1 <= _T_985 @[pic_ctrl.scala 31:20] - node _T_986 = bits(_T_980, 0, 0) @[pic_ctrl.scala 32:30] - node _T_987 = xor(_T_978, _T_979) @[pic_ctrl.scala 32:55] - node _T_988 = or(_T_987, gw_int_pending_1) @[pic_ctrl.scala 32:78] - node _T_989 = xor(_T_978, _T_979) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_2 = mux(_T_986, _T_988, _T_989) @[pic_ctrl.scala 32:8] - node _T_990 = bits(extintsrc_req_sync, 3, 3) @[pic_ctrl.scala 155:52] - node _T_991 = bits(gw_config_reg[3], 0, 0) @[pic_ctrl.scala 155:73] - node _T_992 = bits(gw_config_reg[3], 1, 1) @[pic_ctrl.scala 155:94] - node _T_993 = bits(gw_clear_reg_we_3, 0, 0) @[pic_ctrl.scala 155:124] + node _T_982 = xor(_T_978, _T_979) @[pic_ctrl.scala 31:50] + node _T_983 = eq(_T_981, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_984 = and(gw_int_pending_1, _T_983) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_1 = or(_T_982, _T_984) @[pic_ctrl.scala 31:72] + reg _T_985 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_985 <= gw_int_pending_in_1 @[pic_ctrl.scala 32:45] + gw_int_pending_1 <= _T_985 @[pic_ctrl.scala 32:20] + node _T_986 = bits(_T_980, 0, 0) @[pic_ctrl.scala 33:30] + node _T_987 = xor(_T_978, _T_979) @[pic_ctrl.scala 33:55] + node _T_988 = or(_T_987, gw_int_pending_1) @[pic_ctrl.scala 33:78] + node _T_989 = xor(_T_978, _T_979) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_2 = mux(_T_986, _T_988, _T_989) @[pic_ctrl.scala 33:8] + node _T_990 = bits(extintsrc_req_sync, 3, 3) @[pic_ctrl.scala 156:52] + node _T_991 = bits(gw_config_reg[3], 0, 0) @[pic_ctrl.scala 156:73] + node _T_992 = bits(gw_config_reg[3], 1, 1) @[pic_ctrl.scala 156:94] + node _T_993 = bits(gw_clear_reg_we_3, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_2 : UInt<1> gw_int_pending_2 <= UInt<1>("h00") - node _T_994 = xor(_T_990, _T_991) @[pic_ctrl.scala 30:50] - node _T_995 = eq(_T_993, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_996 = and(gw_int_pending_2, _T_995) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_2 = or(_T_994, _T_996) @[pic_ctrl.scala 30:72] - reg _T_997 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_997 <= gw_int_pending_in_2 @[pic_ctrl.scala 31:45] - gw_int_pending_2 <= _T_997 @[pic_ctrl.scala 31:20] - node _T_998 = bits(_T_992, 0, 0) @[pic_ctrl.scala 32:30] - node _T_999 = xor(_T_990, _T_991) @[pic_ctrl.scala 32:55] - node _T_1000 = or(_T_999, gw_int_pending_2) @[pic_ctrl.scala 32:78] - node _T_1001 = xor(_T_990, _T_991) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_3 = mux(_T_998, _T_1000, _T_1001) @[pic_ctrl.scala 32:8] - node _T_1002 = bits(extintsrc_req_sync, 4, 4) @[pic_ctrl.scala 155:52] - node _T_1003 = bits(gw_config_reg[4], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1004 = bits(gw_config_reg[4], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1005 = bits(gw_clear_reg_we_4, 0, 0) @[pic_ctrl.scala 155:124] + node _T_994 = xor(_T_990, _T_991) @[pic_ctrl.scala 31:50] + node _T_995 = eq(_T_993, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_996 = and(gw_int_pending_2, _T_995) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_2 = or(_T_994, _T_996) @[pic_ctrl.scala 31:72] + reg _T_997 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_997 <= gw_int_pending_in_2 @[pic_ctrl.scala 32:45] + gw_int_pending_2 <= _T_997 @[pic_ctrl.scala 32:20] + node _T_998 = bits(_T_992, 0, 0) @[pic_ctrl.scala 33:30] + node _T_999 = xor(_T_990, _T_991) @[pic_ctrl.scala 33:55] + node _T_1000 = or(_T_999, gw_int_pending_2) @[pic_ctrl.scala 33:78] + node _T_1001 = xor(_T_990, _T_991) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_3 = mux(_T_998, _T_1000, _T_1001) @[pic_ctrl.scala 33:8] + node _T_1002 = bits(extintsrc_req_sync, 4, 4) @[pic_ctrl.scala 156:52] + node _T_1003 = bits(gw_config_reg[4], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1004 = bits(gw_config_reg[4], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1005 = bits(gw_clear_reg_we_4, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_3 : UInt<1> gw_int_pending_3 <= UInt<1>("h00") - node _T_1006 = xor(_T_1002, _T_1003) @[pic_ctrl.scala 30:50] - node _T_1007 = eq(_T_1005, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1008 = and(gw_int_pending_3, _T_1007) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_3 = or(_T_1006, _T_1008) @[pic_ctrl.scala 30:72] - reg _T_1009 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1009 <= gw_int_pending_in_3 @[pic_ctrl.scala 31:45] - gw_int_pending_3 <= _T_1009 @[pic_ctrl.scala 31:20] - node _T_1010 = bits(_T_1004, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1011 = xor(_T_1002, _T_1003) @[pic_ctrl.scala 32:55] - node _T_1012 = or(_T_1011, gw_int_pending_3) @[pic_ctrl.scala 32:78] - node _T_1013 = xor(_T_1002, _T_1003) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_4 = mux(_T_1010, _T_1012, _T_1013) @[pic_ctrl.scala 32:8] - node _T_1014 = bits(extintsrc_req_sync, 5, 5) @[pic_ctrl.scala 155:52] - node _T_1015 = bits(gw_config_reg[5], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1016 = bits(gw_config_reg[5], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1017 = bits(gw_clear_reg_we_5, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1006 = xor(_T_1002, _T_1003) @[pic_ctrl.scala 31:50] + node _T_1007 = eq(_T_1005, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1008 = and(gw_int_pending_3, _T_1007) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_3 = or(_T_1006, _T_1008) @[pic_ctrl.scala 31:72] + reg _T_1009 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1009 <= gw_int_pending_in_3 @[pic_ctrl.scala 32:45] + gw_int_pending_3 <= _T_1009 @[pic_ctrl.scala 32:20] + node _T_1010 = bits(_T_1004, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1011 = xor(_T_1002, _T_1003) @[pic_ctrl.scala 33:55] + node _T_1012 = or(_T_1011, gw_int_pending_3) @[pic_ctrl.scala 33:78] + node _T_1013 = xor(_T_1002, _T_1003) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_4 = mux(_T_1010, _T_1012, _T_1013) @[pic_ctrl.scala 33:8] + node _T_1014 = bits(extintsrc_req_sync, 5, 5) @[pic_ctrl.scala 156:52] + node _T_1015 = bits(gw_config_reg[5], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1016 = bits(gw_config_reg[5], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1017 = bits(gw_clear_reg_we_5, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_4 : UInt<1> gw_int_pending_4 <= UInt<1>("h00") - node _T_1018 = xor(_T_1014, _T_1015) @[pic_ctrl.scala 30:50] - node _T_1019 = eq(_T_1017, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1020 = and(gw_int_pending_4, _T_1019) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_4 = or(_T_1018, _T_1020) @[pic_ctrl.scala 30:72] - reg _T_1021 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1021 <= gw_int_pending_in_4 @[pic_ctrl.scala 31:45] - gw_int_pending_4 <= _T_1021 @[pic_ctrl.scala 31:20] - node _T_1022 = bits(_T_1016, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1023 = xor(_T_1014, _T_1015) @[pic_ctrl.scala 32:55] - node _T_1024 = or(_T_1023, gw_int_pending_4) @[pic_ctrl.scala 32:78] - node _T_1025 = xor(_T_1014, _T_1015) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_5 = mux(_T_1022, _T_1024, _T_1025) @[pic_ctrl.scala 32:8] - node _T_1026 = bits(extintsrc_req_sync, 6, 6) @[pic_ctrl.scala 155:52] - node _T_1027 = bits(gw_config_reg[6], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1028 = bits(gw_config_reg[6], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1029 = bits(gw_clear_reg_we_6, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1018 = xor(_T_1014, _T_1015) @[pic_ctrl.scala 31:50] + node _T_1019 = eq(_T_1017, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1020 = and(gw_int_pending_4, _T_1019) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_4 = or(_T_1018, _T_1020) @[pic_ctrl.scala 31:72] + reg _T_1021 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1021 <= gw_int_pending_in_4 @[pic_ctrl.scala 32:45] + gw_int_pending_4 <= _T_1021 @[pic_ctrl.scala 32:20] + node _T_1022 = bits(_T_1016, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1023 = xor(_T_1014, _T_1015) @[pic_ctrl.scala 33:55] + node _T_1024 = or(_T_1023, gw_int_pending_4) @[pic_ctrl.scala 33:78] + node _T_1025 = xor(_T_1014, _T_1015) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_5 = mux(_T_1022, _T_1024, _T_1025) @[pic_ctrl.scala 33:8] + node _T_1026 = bits(extintsrc_req_sync, 6, 6) @[pic_ctrl.scala 156:52] + node _T_1027 = bits(gw_config_reg[6], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1028 = bits(gw_config_reg[6], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1029 = bits(gw_clear_reg_we_6, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_5 : UInt<1> gw_int_pending_5 <= UInt<1>("h00") - node _T_1030 = xor(_T_1026, _T_1027) @[pic_ctrl.scala 30:50] - node _T_1031 = eq(_T_1029, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1032 = and(gw_int_pending_5, _T_1031) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_5 = or(_T_1030, _T_1032) @[pic_ctrl.scala 30:72] - reg _T_1033 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1033 <= gw_int_pending_in_5 @[pic_ctrl.scala 31:45] - gw_int_pending_5 <= _T_1033 @[pic_ctrl.scala 31:20] - node _T_1034 = bits(_T_1028, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1035 = xor(_T_1026, _T_1027) @[pic_ctrl.scala 32:55] - node _T_1036 = or(_T_1035, gw_int_pending_5) @[pic_ctrl.scala 32:78] - node _T_1037 = xor(_T_1026, _T_1027) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_6 = mux(_T_1034, _T_1036, _T_1037) @[pic_ctrl.scala 32:8] - node _T_1038 = bits(extintsrc_req_sync, 7, 7) @[pic_ctrl.scala 155:52] - node _T_1039 = bits(gw_config_reg[7], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1040 = bits(gw_config_reg[7], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1041 = bits(gw_clear_reg_we_7, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1030 = xor(_T_1026, _T_1027) @[pic_ctrl.scala 31:50] + node _T_1031 = eq(_T_1029, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1032 = and(gw_int_pending_5, _T_1031) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_5 = or(_T_1030, _T_1032) @[pic_ctrl.scala 31:72] + reg _T_1033 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1033 <= gw_int_pending_in_5 @[pic_ctrl.scala 32:45] + gw_int_pending_5 <= _T_1033 @[pic_ctrl.scala 32:20] + node _T_1034 = bits(_T_1028, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1035 = xor(_T_1026, _T_1027) @[pic_ctrl.scala 33:55] + node _T_1036 = or(_T_1035, gw_int_pending_5) @[pic_ctrl.scala 33:78] + node _T_1037 = xor(_T_1026, _T_1027) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_6 = mux(_T_1034, _T_1036, _T_1037) @[pic_ctrl.scala 33:8] + node _T_1038 = bits(extintsrc_req_sync, 7, 7) @[pic_ctrl.scala 156:52] + node _T_1039 = bits(gw_config_reg[7], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1040 = bits(gw_config_reg[7], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1041 = bits(gw_clear_reg_we_7, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_6 : UInt<1> gw_int_pending_6 <= UInt<1>("h00") - node _T_1042 = xor(_T_1038, _T_1039) @[pic_ctrl.scala 30:50] - node _T_1043 = eq(_T_1041, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1044 = and(gw_int_pending_6, _T_1043) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_6 = or(_T_1042, _T_1044) @[pic_ctrl.scala 30:72] - reg _T_1045 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1045 <= gw_int_pending_in_6 @[pic_ctrl.scala 31:45] - gw_int_pending_6 <= _T_1045 @[pic_ctrl.scala 31:20] - node _T_1046 = bits(_T_1040, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1047 = xor(_T_1038, _T_1039) @[pic_ctrl.scala 32:55] - node _T_1048 = or(_T_1047, gw_int_pending_6) @[pic_ctrl.scala 32:78] - node _T_1049 = xor(_T_1038, _T_1039) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_7 = mux(_T_1046, _T_1048, _T_1049) @[pic_ctrl.scala 32:8] - node _T_1050 = bits(extintsrc_req_sync, 8, 8) @[pic_ctrl.scala 155:52] - node _T_1051 = bits(gw_config_reg[8], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1052 = bits(gw_config_reg[8], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1053 = bits(gw_clear_reg_we_8, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1042 = xor(_T_1038, _T_1039) @[pic_ctrl.scala 31:50] + node _T_1043 = eq(_T_1041, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1044 = and(gw_int_pending_6, _T_1043) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_6 = or(_T_1042, _T_1044) @[pic_ctrl.scala 31:72] + reg _T_1045 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1045 <= gw_int_pending_in_6 @[pic_ctrl.scala 32:45] + gw_int_pending_6 <= _T_1045 @[pic_ctrl.scala 32:20] + node _T_1046 = bits(_T_1040, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1047 = xor(_T_1038, _T_1039) @[pic_ctrl.scala 33:55] + node _T_1048 = or(_T_1047, gw_int_pending_6) @[pic_ctrl.scala 33:78] + node _T_1049 = xor(_T_1038, _T_1039) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_7 = mux(_T_1046, _T_1048, _T_1049) @[pic_ctrl.scala 33:8] + node _T_1050 = bits(extintsrc_req_sync, 8, 8) @[pic_ctrl.scala 156:52] + node _T_1051 = bits(gw_config_reg[8], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1052 = bits(gw_config_reg[8], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1053 = bits(gw_clear_reg_we_8, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_7 : UInt<1> gw_int_pending_7 <= UInt<1>("h00") - node _T_1054 = xor(_T_1050, _T_1051) @[pic_ctrl.scala 30:50] - node _T_1055 = eq(_T_1053, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1056 = and(gw_int_pending_7, _T_1055) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_7 = or(_T_1054, _T_1056) @[pic_ctrl.scala 30:72] - reg _T_1057 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1057 <= gw_int_pending_in_7 @[pic_ctrl.scala 31:45] - gw_int_pending_7 <= _T_1057 @[pic_ctrl.scala 31:20] - node _T_1058 = bits(_T_1052, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1059 = xor(_T_1050, _T_1051) @[pic_ctrl.scala 32:55] - node _T_1060 = or(_T_1059, gw_int_pending_7) @[pic_ctrl.scala 32:78] - node _T_1061 = xor(_T_1050, _T_1051) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_8 = mux(_T_1058, _T_1060, _T_1061) @[pic_ctrl.scala 32:8] - node _T_1062 = bits(extintsrc_req_sync, 9, 9) @[pic_ctrl.scala 155:52] - node _T_1063 = bits(gw_config_reg[9], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1064 = bits(gw_config_reg[9], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1065 = bits(gw_clear_reg_we_9, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1054 = xor(_T_1050, _T_1051) @[pic_ctrl.scala 31:50] + node _T_1055 = eq(_T_1053, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1056 = and(gw_int_pending_7, _T_1055) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_7 = or(_T_1054, _T_1056) @[pic_ctrl.scala 31:72] + reg _T_1057 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1057 <= gw_int_pending_in_7 @[pic_ctrl.scala 32:45] + gw_int_pending_7 <= _T_1057 @[pic_ctrl.scala 32:20] + node _T_1058 = bits(_T_1052, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1059 = xor(_T_1050, _T_1051) @[pic_ctrl.scala 33:55] + node _T_1060 = or(_T_1059, gw_int_pending_7) @[pic_ctrl.scala 33:78] + node _T_1061 = xor(_T_1050, _T_1051) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_8 = mux(_T_1058, _T_1060, _T_1061) @[pic_ctrl.scala 33:8] + node _T_1062 = bits(extintsrc_req_sync, 9, 9) @[pic_ctrl.scala 156:52] + node _T_1063 = bits(gw_config_reg[9], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1064 = bits(gw_config_reg[9], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1065 = bits(gw_clear_reg_we_9, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_8 : UInt<1> gw_int_pending_8 <= UInt<1>("h00") - node _T_1066 = xor(_T_1062, _T_1063) @[pic_ctrl.scala 30:50] - node _T_1067 = eq(_T_1065, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1068 = and(gw_int_pending_8, _T_1067) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_8 = or(_T_1066, _T_1068) @[pic_ctrl.scala 30:72] - reg _T_1069 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1069 <= gw_int_pending_in_8 @[pic_ctrl.scala 31:45] - gw_int_pending_8 <= _T_1069 @[pic_ctrl.scala 31:20] - node _T_1070 = bits(_T_1064, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1071 = xor(_T_1062, _T_1063) @[pic_ctrl.scala 32:55] - node _T_1072 = or(_T_1071, gw_int_pending_8) @[pic_ctrl.scala 32:78] - node _T_1073 = xor(_T_1062, _T_1063) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_9 = mux(_T_1070, _T_1072, _T_1073) @[pic_ctrl.scala 32:8] - node _T_1074 = bits(extintsrc_req_sync, 10, 10) @[pic_ctrl.scala 155:52] - node _T_1075 = bits(gw_config_reg[10], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1076 = bits(gw_config_reg[10], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1077 = bits(gw_clear_reg_we_10, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1066 = xor(_T_1062, _T_1063) @[pic_ctrl.scala 31:50] + node _T_1067 = eq(_T_1065, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1068 = and(gw_int_pending_8, _T_1067) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_8 = or(_T_1066, _T_1068) @[pic_ctrl.scala 31:72] + reg _T_1069 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1069 <= gw_int_pending_in_8 @[pic_ctrl.scala 32:45] + gw_int_pending_8 <= _T_1069 @[pic_ctrl.scala 32:20] + node _T_1070 = bits(_T_1064, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1071 = xor(_T_1062, _T_1063) @[pic_ctrl.scala 33:55] + node _T_1072 = or(_T_1071, gw_int_pending_8) @[pic_ctrl.scala 33:78] + node _T_1073 = xor(_T_1062, _T_1063) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_9 = mux(_T_1070, _T_1072, _T_1073) @[pic_ctrl.scala 33:8] + node _T_1074 = bits(extintsrc_req_sync, 10, 10) @[pic_ctrl.scala 156:52] + node _T_1075 = bits(gw_config_reg[10], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1076 = bits(gw_config_reg[10], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1077 = bits(gw_clear_reg_we_10, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_9 : UInt<1> gw_int_pending_9 <= UInt<1>("h00") - node _T_1078 = xor(_T_1074, _T_1075) @[pic_ctrl.scala 30:50] - node _T_1079 = eq(_T_1077, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1080 = and(gw_int_pending_9, _T_1079) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_9 = or(_T_1078, _T_1080) @[pic_ctrl.scala 30:72] - reg _T_1081 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1081 <= gw_int_pending_in_9 @[pic_ctrl.scala 31:45] - gw_int_pending_9 <= _T_1081 @[pic_ctrl.scala 31:20] - node _T_1082 = bits(_T_1076, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1083 = xor(_T_1074, _T_1075) @[pic_ctrl.scala 32:55] - node _T_1084 = or(_T_1083, gw_int_pending_9) @[pic_ctrl.scala 32:78] - node _T_1085 = xor(_T_1074, _T_1075) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_10 = mux(_T_1082, _T_1084, _T_1085) @[pic_ctrl.scala 32:8] - node _T_1086 = bits(extintsrc_req_sync, 11, 11) @[pic_ctrl.scala 155:52] - node _T_1087 = bits(gw_config_reg[11], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1088 = bits(gw_config_reg[11], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1089 = bits(gw_clear_reg_we_11, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1078 = xor(_T_1074, _T_1075) @[pic_ctrl.scala 31:50] + node _T_1079 = eq(_T_1077, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1080 = and(gw_int_pending_9, _T_1079) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_9 = or(_T_1078, _T_1080) @[pic_ctrl.scala 31:72] + reg _T_1081 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1081 <= gw_int_pending_in_9 @[pic_ctrl.scala 32:45] + gw_int_pending_9 <= _T_1081 @[pic_ctrl.scala 32:20] + node _T_1082 = bits(_T_1076, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1083 = xor(_T_1074, _T_1075) @[pic_ctrl.scala 33:55] + node _T_1084 = or(_T_1083, gw_int_pending_9) @[pic_ctrl.scala 33:78] + node _T_1085 = xor(_T_1074, _T_1075) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_10 = mux(_T_1082, _T_1084, _T_1085) @[pic_ctrl.scala 33:8] + node _T_1086 = bits(extintsrc_req_sync, 11, 11) @[pic_ctrl.scala 156:52] + node _T_1087 = bits(gw_config_reg[11], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1088 = bits(gw_config_reg[11], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1089 = bits(gw_clear_reg_we_11, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_10 : UInt<1> gw_int_pending_10 <= UInt<1>("h00") - node _T_1090 = xor(_T_1086, _T_1087) @[pic_ctrl.scala 30:50] - node _T_1091 = eq(_T_1089, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1092 = and(gw_int_pending_10, _T_1091) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_10 = or(_T_1090, _T_1092) @[pic_ctrl.scala 30:72] - reg _T_1093 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1093 <= gw_int_pending_in_10 @[pic_ctrl.scala 31:45] - gw_int_pending_10 <= _T_1093 @[pic_ctrl.scala 31:20] - node _T_1094 = bits(_T_1088, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1095 = xor(_T_1086, _T_1087) @[pic_ctrl.scala 32:55] - node _T_1096 = or(_T_1095, gw_int_pending_10) @[pic_ctrl.scala 32:78] - node _T_1097 = xor(_T_1086, _T_1087) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_11 = mux(_T_1094, _T_1096, _T_1097) @[pic_ctrl.scala 32:8] - node _T_1098 = bits(extintsrc_req_sync, 12, 12) @[pic_ctrl.scala 155:52] - node _T_1099 = bits(gw_config_reg[12], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1100 = bits(gw_config_reg[12], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1101 = bits(gw_clear_reg_we_12, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1090 = xor(_T_1086, _T_1087) @[pic_ctrl.scala 31:50] + node _T_1091 = eq(_T_1089, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1092 = and(gw_int_pending_10, _T_1091) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_10 = or(_T_1090, _T_1092) @[pic_ctrl.scala 31:72] + reg _T_1093 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1093 <= gw_int_pending_in_10 @[pic_ctrl.scala 32:45] + gw_int_pending_10 <= _T_1093 @[pic_ctrl.scala 32:20] + node _T_1094 = bits(_T_1088, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1095 = xor(_T_1086, _T_1087) @[pic_ctrl.scala 33:55] + node _T_1096 = or(_T_1095, gw_int_pending_10) @[pic_ctrl.scala 33:78] + node _T_1097 = xor(_T_1086, _T_1087) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_11 = mux(_T_1094, _T_1096, _T_1097) @[pic_ctrl.scala 33:8] + node _T_1098 = bits(extintsrc_req_sync, 12, 12) @[pic_ctrl.scala 156:52] + node _T_1099 = bits(gw_config_reg[12], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1100 = bits(gw_config_reg[12], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1101 = bits(gw_clear_reg_we_12, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_11 : UInt<1> gw_int_pending_11 <= UInt<1>("h00") - node _T_1102 = xor(_T_1098, _T_1099) @[pic_ctrl.scala 30:50] - node _T_1103 = eq(_T_1101, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1104 = and(gw_int_pending_11, _T_1103) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_11 = or(_T_1102, _T_1104) @[pic_ctrl.scala 30:72] - reg _T_1105 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1105 <= gw_int_pending_in_11 @[pic_ctrl.scala 31:45] - gw_int_pending_11 <= _T_1105 @[pic_ctrl.scala 31:20] - node _T_1106 = bits(_T_1100, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1107 = xor(_T_1098, _T_1099) @[pic_ctrl.scala 32:55] - node _T_1108 = or(_T_1107, gw_int_pending_11) @[pic_ctrl.scala 32:78] - node _T_1109 = xor(_T_1098, _T_1099) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_12 = mux(_T_1106, _T_1108, _T_1109) @[pic_ctrl.scala 32:8] - node _T_1110 = bits(extintsrc_req_sync, 13, 13) @[pic_ctrl.scala 155:52] - node _T_1111 = bits(gw_config_reg[13], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1112 = bits(gw_config_reg[13], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1113 = bits(gw_clear_reg_we_13, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1102 = xor(_T_1098, _T_1099) @[pic_ctrl.scala 31:50] + node _T_1103 = eq(_T_1101, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1104 = and(gw_int_pending_11, _T_1103) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_11 = or(_T_1102, _T_1104) @[pic_ctrl.scala 31:72] + reg _T_1105 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1105 <= gw_int_pending_in_11 @[pic_ctrl.scala 32:45] + gw_int_pending_11 <= _T_1105 @[pic_ctrl.scala 32:20] + node _T_1106 = bits(_T_1100, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1107 = xor(_T_1098, _T_1099) @[pic_ctrl.scala 33:55] + node _T_1108 = or(_T_1107, gw_int_pending_11) @[pic_ctrl.scala 33:78] + node _T_1109 = xor(_T_1098, _T_1099) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_12 = mux(_T_1106, _T_1108, _T_1109) @[pic_ctrl.scala 33:8] + node _T_1110 = bits(extintsrc_req_sync, 13, 13) @[pic_ctrl.scala 156:52] + node _T_1111 = bits(gw_config_reg[13], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1112 = bits(gw_config_reg[13], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1113 = bits(gw_clear_reg_we_13, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_12 : UInt<1> gw_int_pending_12 <= UInt<1>("h00") - node _T_1114 = xor(_T_1110, _T_1111) @[pic_ctrl.scala 30:50] - node _T_1115 = eq(_T_1113, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1116 = and(gw_int_pending_12, _T_1115) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_12 = or(_T_1114, _T_1116) @[pic_ctrl.scala 30:72] - reg _T_1117 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1117 <= gw_int_pending_in_12 @[pic_ctrl.scala 31:45] - gw_int_pending_12 <= _T_1117 @[pic_ctrl.scala 31:20] - node _T_1118 = bits(_T_1112, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1119 = xor(_T_1110, _T_1111) @[pic_ctrl.scala 32:55] - node _T_1120 = or(_T_1119, gw_int_pending_12) @[pic_ctrl.scala 32:78] - node _T_1121 = xor(_T_1110, _T_1111) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_13 = mux(_T_1118, _T_1120, _T_1121) @[pic_ctrl.scala 32:8] - node _T_1122 = bits(extintsrc_req_sync, 14, 14) @[pic_ctrl.scala 155:52] - node _T_1123 = bits(gw_config_reg[14], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1124 = bits(gw_config_reg[14], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1125 = bits(gw_clear_reg_we_14, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1114 = xor(_T_1110, _T_1111) @[pic_ctrl.scala 31:50] + node _T_1115 = eq(_T_1113, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1116 = and(gw_int_pending_12, _T_1115) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_12 = or(_T_1114, _T_1116) @[pic_ctrl.scala 31:72] + reg _T_1117 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1117 <= gw_int_pending_in_12 @[pic_ctrl.scala 32:45] + gw_int_pending_12 <= _T_1117 @[pic_ctrl.scala 32:20] + node _T_1118 = bits(_T_1112, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1119 = xor(_T_1110, _T_1111) @[pic_ctrl.scala 33:55] + node _T_1120 = or(_T_1119, gw_int_pending_12) @[pic_ctrl.scala 33:78] + node _T_1121 = xor(_T_1110, _T_1111) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_13 = mux(_T_1118, _T_1120, _T_1121) @[pic_ctrl.scala 33:8] + node _T_1122 = bits(extintsrc_req_sync, 14, 14) @[pic_ctrl.scala 156:52] + node _T_1123 = bits(gw_config_reg[14], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1124 = bits(gw_config_reg[14], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1125 = bits(gw_clear_reg_we_14, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_13 : UInt<1> gw_int_pending_13 <= UInt<1>("h00") - node _T_1126 = xor(_T_1122, _T_1123) @[pic_ctrl.scala 30:50] - node _T_1127 = eq(_T_1125, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1128 = and(gw_int_pending_13, _T_1127) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_13 = or(_T_1126, _T_1128) @[pic_ctrl.scala 30:72] - reg _T_1129 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1129 <= gw_int_pending_in_13 @[pic_ctrl.scala 31:45] - gw_int_pending_13 <= _T_1129 @[pic_ctrl.scala 31:20] - node _T_1130 = bits(_T_1124, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1131 = xor(_T_1122, _T_1123) @[pic_ctrl.scala 32:55] - node _T_1132 = or(_T_1131, gw_int_pending_13) @[pic_ctrl.scala 32:78] - node _T_1133 = xor(_T_1122, _T_1123) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_14 = mux(_T_1130, _T_1132, _T_1133) @[pic_ctrl.scala 32:8] - node _T_1134 = bits(extintsrc_req_sync, 15, 15) @[pic_ctrl.scala 155:52] - node _T_1135 = bits(gw_config_reg[15], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1136 = bits(gw_config_reg[15], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1137 = bits(gw_clear_reg_we_15, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1126 = xor(_T_1122, _T_1123) @[pic_ctrl.scala 31:50] + node _T_1127 = eq(_T_1125, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1128 = and(gw_int_pending_13, _T_1127) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_13 = or(_T_1126, _T_1128) @[pic_ctrl.scala 31:72] + reg _T_1129 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1129 <= gw_int_pending_in_13 @[pic_ctrl.scala 32:45] + gw_int_pending_13 <= _T_1129 @[pic_ctrl.scala 32:20] + node _T_1130 = bits(_T_1124, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1131 = xor(_T_1122, _T_1123) @[pic_ctrl.scala 33:55] + node _T_1132 = or(_T_1131, gw_int_pending_13) @[pic_ctrl.scala 33:78] + node _T_1133 = xor(_T_1122, _T_1123) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_14 = mux(_T_1130, _T_1132, _T_1133) @[pic_ctrl.scala 33:8] + node _T_1134 = bits(extintsrc_req_sync, 15, 15) @[pic_ctrl.scala 156:52] + node _T_1135 = bits(gw_config_reg[15], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1136 = bits(gw_config_reg[15], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1137 = bits(gw_clear_reg_we_15, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_14 : UInt<1> gw_int_pending_14 <= UInt<1>("h00") - node _T_1138 = xor(_T_1134, _T_1135) @[pic_ctrl.scala 30:50] - node _T_1139 = eq(_T_1137, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1140 = and(gw_int_pending_14, _T_1139) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_14 = or(_T_1138, _T_1140) @[pic_ctrl.scala 30:72] - reg _T_1141 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1141 <= gw_int_pending_in_14 @[pic_ctrl.scala 31:45] - gw_int_pending_14 <= _T_1141 @[pic_ctrl.scala 31:20] - node _T_1142 = bits(_T_1136, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1143 = xor(_T_1134, _T_1135) @[pic_ctrl.scala 32:55] - node _T_1144 = or(_T_1143, gw_int_pending_14) @[pic_ctrl.scala 32:78] - node _T_1145 = xor(_T_1134, _T_1135) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_15 = mux(_T_1142, _T_1144, _T_1145) @[pic_ctrl.scala 32:8] - node _T_1146 = bits(extintsrc_req_sync, 16, 16) @[pic_ctrl.scala 155:52] - node _T_1147 = bits(gw_config_reg[16], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1148 = bits(gw_config_reg[16], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1149 = bits(gw_clear_reg_we_16, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1138 = xor(_T_1134, _T_1135) @[pic_ctrl.scala 31:50] + node _T_1139 = eq(_T_1137, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1140 = and(gw_int_pending_14, _T_1139) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_14 = or(_T_1138, _T_1140) @[pic_ctrl.scala 31:72] + reg _T_1141 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1141 <= gw_int_pending_in_14 @[pic_ctrl.scala 32:45] + gw_int_pending_14 <= _T_1141 @[pic_ctrl.scala 32:20] + node _T_1142 = bits(_T_1136, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1143 = xor(_T_1134, _T_1135) @[pic_ctrl.scala 33:55] + node _T_1144 = or(_T_1143, gw_int_pending_14) @[pic_ctrl.scala 33:78] + node _T_1145 = xor(_T_1134, _T_1135) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_15 = mux(_T_1142, _T_1144, _T_1145) @[pic_ctrl.scala 33:8] + node _T_1146 = bits(extintsrc_req_sync, 16, 16) @[pic_ctrl.scala 156:52] + node _T_1147 = bits(gw_config_reg[16], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1148 = bits(gw_config_reg[16], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1149 = bits(gw_clear_reg_we_16, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_15 : UInt<1> gw_int_pending_15 <= UInt<1>("h00") - node _T_1150 = xor(_T_1146, _T_1147) @[pic_ctrl.scala 30:50] - node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1152 = and(gw_int_pending_15, _T_1151) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_15 = or(_T_1150, _T_1152) @[pic_ctrl.scala 30:72] - reg _T_1153 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1153 <= gw_int_pending_in_15 @[pic_ctrl.scala 31:45] - gw_int_pending_15 <= _T_1153 @[pic_ctrl.scala 31:20] - node _T_1154 = bits(_T_1148, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1155 = xor(_T_1146, _T_1147) @[pic_ctrl.scala 32:55] - node _T_1156 = or(_T_1155, gw_int_pending_15) @[pic_ctrl.scala 32:78] - node _T_1157 = xor(_T_1146, _T_1147) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_16 = mux(_T_1154, _T_1156, _T_1157) @[pic_ctrl.scala 32:8] - node _T_1158 = bits(extintsrc_req_sync, 17, 17) @[pic_ctrl.scala 155:52] - node _T_1159 = bits(gw_config_reg[17], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1160 = bits(gw_config_reg[17], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1161 = bits(gw_clear_reg_we_17, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1150 = xor(_T_1146, _T_1147) @[pic_ctrl.scala 31:50] + node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1152 = and(gw_int_pending_15, _T_1151) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_15 = or(_T_1150, _T_1152) @[pic_ctrl.scala 31:72] + reg _T_1153 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1153 <= gw_int_pending_in_15 @[pic_ctrl.scala 32:45] + gw_int_pending_15 <= _T_1153 @[pic_ctrl.scala 32:20] + node _T_1154 = bits(_T_1148, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1155 = xor(_T_1146, _T_1147) @[pic_ctrl.scala 33:55] + node _T_1156 = or(_T_1155, gw_int_pending_15) @[pic_ctrl.scala 33:78] + node _T_1157 = xor(_T_1146, _T_1147) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_16 = mux(_T_1154, _T_1156, _T_1157) @[pic_ctrl.scala 33:8] + node _T_1158 = bits(extintsrc_req_sync, 17, 17) @[pic_ctrl.scala 156:52] + node _T_1159 = bits(gw_config_reg[17], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1160 = bits(gw_config_reg[17], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1161 = bits(gw_clear_reg_we_17, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_16 : UInt<1> gw_int_pending_16 <= UInt<1>("h00") - node _T_1162 = xor(_T_1158, _T_1159) @[pic_ctrl.scala 30:50] - node _T_1163 = eq(_T_1161, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1164 = and(gw_int_pending_16, _T_1163) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_16 = or(_T_1162, _T_1164) @[pic_ctrl.scala 30:72] - reg _T_1165 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1165 <= gw_int_pending_in_16 @[pic_ctrl.scala 31:45] - gw_int_pending_16 <= _T_1165 @[pic_ctrl.scala 31:20] - node _T_1166 = bits(_T_1160, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1167 = xor(_T_1158, _T_1159) @[pic_ctrl.scala 32:55] - node _T_1168 = or(_T_1167, gw_int_pending_16) @[pic_ctrl.scala 32:78] - node _T_1169 = xor(_T_1158, _T_1159) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_17 = mux(_T_1166, _T_1168, _T_1169) @[pic_ctrl.scala 32:8] - node _T_1170 = bits(extintsrc_req_sync, 18, 18) @[pic_ctrl.scala 155:52] - node _T_1171 = bits(gw_config_reg[18], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1172 = bits(gw_config_reg[18], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1173 = bits(gw_clear_reg_we_18, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1162 = xor(_T_1158, _T_1159) @[pic_ctrl.scala 31:50] + node _T_1163 = eq(_T_1161, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1164 = and(gw_int_pending_16, _T_1163) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_16 = or(_T_1162, _T_1164) @[pic_ctrl.scala 31:72] + reg _T_1165 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1165 <= gw_int_pending_in_16 @[pic_ctrl.scala 32:45] + gw_int_pending_16 <= _T_1165 @[pic_ctrl.scala 32:20] + node _T_1166 = bits(_T_1160, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1167 = xor(_T_1158, _T_1159) @[pic_ctrl.scala 33:55] + node _T_1168 = or(_T_1167, gw_int_pending_16) @[pic_ctrl.scala 33:78] + node _T_1169 = xor(_T_1158, _T_1159) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_17 = mux(_T_1166, _T_1168, _T_1169) @[pic_ctrl.scala 33:8] + node _T_1170 = bits(extintsrc_req_sync, 18, 18) @[pic_ctrl.scala 156:52] + node _T_1171 = bits(gw_config_reg[18], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1172 = bits(gw_config_reg[18], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1173 = bits(gw_clear_reg_we_18, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_17 : UInt<1> gw_int_pending_17 <= UInt<1>("h00") - node _T_1174 = xor(_T_1170, _T_1171) @[pic_ctrl.scala 30:50] - node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1176 = and(gw_int_pending_17, _T_1175) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_17 = or(_T_1174, _T_1176) @[pic_ctrl.scala 30:72] - reg _T_1177 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1177 <= gw_int_pending_in_17 @[pic_ctrl.scala 31:45] - gw_int_pending_17 <= _T_1177 @[pic_ctrl.scala 31:20] - node _T_1178 = bits(_T_1172, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1179 = xor(_T_1170, _T_1171) @[pic_ctrl.scala 32:55] - node _T_1180 = or(_T_1179, gw_int_pending_17) @[pic_ctrl.scala 32:78] - node _T_1181 = xor(_T_1170, _T_1171) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_18 = mux(_T_1178, _T_1180, _T_1181) @[pic_ctrl.scala 32:8] - node _T_1182 = bits(extintsrc_req_sync, 19, 19) @[pic_ctrl.scala 155:52] - node _T_1183 = bits(gw_config_reg[19], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1184 = bits(gw_config_reg[19], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1185 = bits(gw_clear_reg_we_19, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1174 = xor(_T_1170, _T_1171) @[pic_ctrl.scala 31:50] + node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1176 = and(gw_int_pending_17, _T_1175) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_17 = or(_T_1174, _T_1176) @[pic_ctrl.scala 31:72] + reg _T_1177 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1177 <= gw_int_pending_in_17 @[pic_ctrl.scala 32:45] + gw_int_pending_17 <= _T_1177 @[pic_ctrl.scala 32:20] + node _T_1178 = bits(_T_1172, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1179 = xor(_T_1170, _T_1171) @[pic_ctrl.scala 33:55] + node _T_1180 = or(_T_1179, gw_int_pending_17) @[pic_ctrl.scala 33:78] + node _T_1181 = xor(_T_1170, _T_1171) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_18 = mux(_T_1178, _T_1180, _T_1181) @[pic_ctrl.scala 33:8] + node _T_1182 = bits(extintsrc_req_sync, 19, 19) @[pic_ctrl.scala 156:52] + node _T_1183 = bits(gw_config_reg[19], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1184 = bits(gw_config_reg[19], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1185 = bits(gw_clear_reg_we_19, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_18 : UInt<1> gw_int_pending_18 <= UInt<1>("h00") - node _T_1186 = xor(_T_1182, _T_1183) @[pic_ctrl.scala 30:50] - node _T_1187 = eq(_T_1185, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1188 = and(gw_int_pending_18, _T_1187) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_18 = or(_T_1186, _T_1188) @[pic_ctrl.scala 30:72] - reg _T_1189 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1189 <= gw_int_pending_in_18 @[pic_ctrl.scala 31:45] - gw_int_pending_18 <= _T_1189 @[pic_ctrl.scala 31:20] - node _T_1190 = bits(_T_1184, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1191 = xor(_T_1182, _T_1183) @[pic_ctrl.scala 32:55] - node _T_1192 = or(_T_1191, gw_int_pending_18) @[pic_ctrl.scala 32:78] - node _T_1193 = xor(_T_1182, _T_1183) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_19 = mux(_T_1190, _T_1192, _T_1193) @[pic_ctrl.scala 32:8] - node _T_1194 = bits(extintsrc_req_sync, 20, 20) @[pic_ctrl.scala 155:52] - node _T_1195 = bits(gw_config_reg[20], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1196 = bits(gw_config_reg[20], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1197 = bits(gw_clear_reg_we_20, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1186 = xor(_T_1182, _T_1183) @[pic_ctrl.scala 31:50] + node _T_1187 = eq(_T_1185, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1188 = and(gw_int_pending_18, _T_1187) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_18 = or(_T_1186, _T_1188) @[pic_ctrl.scala 31:72] + reg _T_1189 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1189 <= gw_int_pending_in_18 @[pic_ctrl.scala 32:45] + gw_int_pending_18 <= _T_1189 @[pic_ctrl.scala 32:20] + node _T_1190 = bits(_T_1184, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1191 = xor(_T_1182, _T_1183) @[pic_ctrl.scala 33:55] + node _T_1192 = or(_T_1191, gw_int_pending_18) @[pic_ctrl.scala 33:78] + node _T_1193 = xor(_T_1182, _T_1183) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_19 = mux(_T_1190, _T_1192, _T_1193) @[pic_ctrl.scala 33:8] + node _T_1194 = bits(extintsrc_req_sync, 20, 20) @[pic_ctrl.scala 156:52] + node _T_1195 = bits(gw_config_reg[20], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1196 = bits(gw_config_reg[20], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1197 = bits(gw_clear_reg_we_20, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_19 : UInt<1> gw_int_pending_19 <= UInt<1>("h00") - node _T_1198 = xor(_T_1194, _T_1195) @[pic_ctrl.scala 30:50] - node _T_1199 = eq(_T_1197, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1200 = and(gw_int_pending_19, _T_1199) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_19 = or(_T_1198, _T_1200) @[pic_ctrl.scala 30:72] - reg _T_1201 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1201 <= gw_int_pending_in_19 @[pic_ctrl.scala 31:45] - gw_int_pending_19 <= _T_1201 @[pic_ctrl.scala 31:20] - node _T_1202 = bits(_T_1196, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1203 = xor(_T_1194, _T_1195) @[pic_ctrl.scala 32:55] - node _T_1204 = or(_T_1203, gw_int_pending_19) @[pic_ctrl.scala 32:78] - node _T_1205 = xor(_T_1194, _T_1195) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_20 = mux(_T_1202, _T_1204, _T_1205) @[pic_ctrl.scala 32:8] - node _T_1206 = bits(extintsrc_req_sync, 21, 21) @[pic_ctrl.scala 155:52] - node _T_1207 = bits(gw_config_reg[21], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1208 = bits(gw_config_reg[21], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1209 = bits(gw_clear_reg_we_21, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1198 = xor(_T_1194, _T_1195) @[pic_ctrl.scala 31:50] + node _T_1199 = eq(_T_1197, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1200 = and(gw_int_pending_19, _T_1199) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_19 = or(_T_1198, _T_1200) @[pic_ctrl.scala 31:72] + reg _T_1201 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1201 <= gw_int_pending_in_19 @[pic_ctrl.scala 32:45] + gw_int_pending_19 <= _T_1201 @[pic_ctrl.scala 32:20] + node _T_1202 = bits(_T_1196, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1203 = xor(_T_1194, _T_1195) @[pic_ctrl.scala 33:55] + node _T_1204 = or(_T_1203, gw_int_pending_19) @[pic_ctrl.scala 33:78] + node _T_1205 = xor(_T_1194, _T_1195) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_20 = mux(_T_1202, _T_1204, _T_1205) @[pic_ctrl.scala 33:8] + node _T_1206 = bits(extintsrc_req_sync, 21, 21) @[pic_ctrl.scala 156:52] + node _T_1207 = bits(gw_config_reg[21], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1208 = bits(gw_config_reg[21], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1209 = bits(gw_clear_reg_we_21, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_20 : UInt<1> gw_int_pending_20 <= UInt<1>("h00") - node _T_1210 = xor(_T_1206, _T_1207) @[pic_ctrl.scala 30:50] - node _T_1211 = eq(_T_1209, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1212 = and(gw_int_pending_20, _T_1211) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_20 = or(_T_1210, _T_1212) @[pic_ctrl.scala 30:72] - reg _T_1213 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1213 <= gw_int_pending_in_20 @[pic_ctrl.scala 31:45] - gw_int_pending_20 <= _T_1213 @[pic_ctrl.scala 31:20] - node _T_1214 = bits(_T_1208, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1215 = xor(_T_1206, _T_1207) @[pic_ctrl.scala 32:55] - node _T_1216 = or(_T_1215, gw_int_pending_20) @[pic_ctrl.scala 32:78] - node _T_1217 = xor(_T_1206, _T_1207) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_21 = mux(_T_1214, _T_1216, _T_1217) @[pic_ctrl.scala 32:8] - node _T_1218 = bits(extintsrc_req_sync, 22, 22) @[pic_ctrl.scala 155:52] - node _T_1219 = bits(gw_config_reg[22], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1220 = bits(gw_config_reg[22], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1221 = bits(gw_clear_reg_we_22, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1210 = xor(_T_1206, _T_1207) @[pic_ctrl.scala 31:50] + node _T_1211 = eq(_T_1209, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1212 = and(gw_int_pending_20, _T_1211) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_20 = or(_T_1210, _T_1212) @[pic_ctrl.scala 31:72] + reg _T_1213 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1213 <= gw_int_pending_in_20 @[pic_ctrl.scala 32:45] + gw_int_pending_20 <= _T_1213 @[pic_ctrl.scala 32:20] + node _T_1214 = bits(_T_1208, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1215 = xor(_T_1206, _T_1207) @[pic_ctrl.scala 33:55] + node _T_1216 = or(_T_1215, gw_int_pending_20) @[pic_ctrl.scala 33:78] + node _T_1217 = xor(_T_1206, _T_1207) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_21 = mux(_T_1214, _T_1216, _T_1217) @[pic_ctrl.scala 33:8] + node _T_1218 = bits(extintsrc_req_sync, 22, 22) @[pic_ctrl.scala 156:52] + node _T_1219 = bits(gw_config_reg[22], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1220 = bits(gw_config_reg[22], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1221 = bits(gw_clear_reg_we_22, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_21 : UInt<1> gw_int_pending_21 <= UInt<1>("h00") - node _T_1222 = xor(_T_1218, _T_1219) @[pic_ctrl.scala 30:50] - node _T_1223 = eq(_T_1221, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1224 = and(gw_int_pending_21, _T_1223) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_21 = or(_T_1222, _T_1224) @[pic_ctrl.scala 30:72] - reg _T_1225 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1225 <= gw_int_pending_in_21 @[pic_ctrl.scala 31:45] - gw_int_pending_21 <= _T_1225 @[pic_ctrl.scala 31:20] - node _T_1226 = bits(_T_1220, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1227 = xor(_T_1218, _T_1219) @[pic_ctrl.scala 32:55] - node _T_1228 = or(_T_1227, gw_int_pending_21) @[pic_ctrl.scala 32:78] - node _T_1229 = xor(_T_1218, _T_1219) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_22 = mux(_T_1226, _T_1228, _T_1229) @[pic_ctrl.scala 32:8] - node _T_1230 = bits(extintsrc_req_sync, 23, 23) @[pic_ctrl.scala 155:52] - node _T_1231 = bits(gw_config_reg[23], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1232 = bits(gw_config_reg[23], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1233 = bits(gw_clear_reg_we_23, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1222 = xor(_T_1218, _T_1219) @[pic_ctrl.scala 31:50] + node _T_1223 = eq(_T_1221, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1224 = and(gw_int_pending_21, _T_1223) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_21 = or(_T_1222, _T_1224) @[pic_ctrl.scala 31:72] + reg _T_1225 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1225 <= gw_int_pending_in_21 @[pic_ctrl.scala 32:45] + gw_int_pending_21 <= _T_1225 @[pic_ctrl.scala 32:20] + node _T_1226 = bits(_T_1220, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1227 = xor(_T_1218, _T_1219) @[pic_ctrl.scala 33:55] + node _T_1228 = or(_T_1227, gw_int_pending_21) @[pic_ctrl.scala 33:78] + node _T_1229 = xor(_T_1218, _T_1219) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_22 = mux(_T_1226, _T_1228, _T_1229) @[pic_ctrl.scala 33:8] + node _T_1230 = bits(extintsrc_req_sync, 23, 23) @[pic_ctrl.scala 156:52] + node _T_1231 = bits(gw_config_reg[23], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1232 = bits(gw_config_reg[23], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1233 = bits(gw_clear_reg_we_23, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_22 : UInt<1> gw_int_pending_22 <= UInt<1>("h00") - node _T_1234 = xor(_T_1230, _T_1231) @[pic_ctrl.scala 30:50] - node _T_1235 = eq(_T_1233, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1236 = and(gw_int_pending_22, _T_1235) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_22 = or(_T_1234, _T_1236) @[pic_ctrl.scala 30:72] - reg _T_1237 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1237 <= gw_int_pending_in_22 @[pic_ctrl.scala 31:45] - gw_int_pending_22 <= _T_1237 @[pic_ctrl.scala 31:20] - node _T_1238 = bits(_T_1232, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1239 = xor(_T_1230, _T_1231) @[pic_ctrl.scala 32:55] - node _T_1240 = or(_T_1239, gw_int_pending_22) @[pic_ctrl.scala 32:78] - node _T_1241 = xor(_T_1230, _T_1231) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_23 = mux(_T_1238, _T_1240, _T_1241) @[pic_ctrl.scala 32:8] - node _T_1242 = bits(extintsrc_req_sync, 24, 24) @[pic_ctrl.scala 155:52] - node _T_1243 = bits(gw_config_reg[24], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1244 = bits(gw_config_reg[24], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1245 = bits(gw_clear_reg_we_24, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1234 = xor(_T_1230, _T_1231) @[pic_ctrl.scala 31:50] + node _T_1235 = eq(_T_1233, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1236 = and(gw_int_pending_22, _T_1235) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_22 = or(_T_1234, _T_1236) @[pic_ctrl.scala 31:72] + reg _T_1237 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1237 <= gw_int_pending_in_22 @[pic_ctrl.scala 32:45] + gw_int_pending_22 <= _T_1237 @[pic_ctrl.scala 32:20] + node _T_1238 = bits(_T_1232, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1239 = xor(_T_1230, _T_1231) @[pic_ctrl.scala 33:55] + node _T_1240 = or(_T_1239, gw_int_pending_22) @[pic_ctrl.scala 33:78] + node _T_1241 = xor(_T_1230, _T_1231) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_23 = mux(_T_1238, _T_1240, _T_1241) @[pic_ctrl.scala 33:8] + node _T_1242 = bits(extintsrc_req_sync, 24, 24) @[pic_ctrl.scala 156:52] + node _T_1243 = bits(gw_config_reg[24], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1244 = bits(gw_config_reg[24], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1245 = bits(gw_clear_reg_we_24, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_23 : UInt<1> gw_int_pending_23 <= UInt<1>("h00") - node _T_1246 = xor(_T_1242, _T_1243) @[pic_ctrl.scala 30:50] - node _T_1247 = eq(_T_1245, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1248 = and(gw_int_pending_23, _T_1247) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_23 = or(_T_1246, _T_1248) @[pic_ctrl.scala 30:72] - reg _T_1249 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1249 <= gw_int_pending_in_23 @[pic_ctrl.scala 31:45] - gw_int_pending_23 <= _T_1249 @[pic_ctrl.scala 31:20] - node _T_1250 = bits(_T_1244, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1251 = xor(_T_1242, _T_1243) @[pic_ctrl.scala 32:55] - node _T_1252 = or(_T_1251, gw_int_pending_23) @[pic_ctrl.scala 32:78] - node _T_1253 = xor(_T_1242, _T_1243) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_24 = mux(_T_1250, _T_1252, _T_1253) @[pic_ctrl.scala 32:8] - node _T_1254 = bits(extintsrc_req_sync, 25, 25) @[pic_ctrl.scala 155:52] - node _T_1255 = bits(gw_config_reg[25], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1256 = bits(gw_config_reg[25], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1257 = bits(gw_clear_reg_we_25, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1246 = xor(_T_1242, _T_1243) @[pic_ctrl.scala 31:50] + node _T_1247 = eq(_T_1245, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1248 = and(gw_int_pending_23, _T_1247) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_23 = or(_T_1246, _T_1248) @[pic_ctrl.scala 31:72] + reg _T_1249 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1249 <= gw_int_pending_in_23 @[pic_ctrl.scala 32:45] + gw_int_pending_23 <= _T_1249 @[pic_ctrl.scala 32:20] + node _T_1250 = bits(_T_1244, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1251 = xor(_T_1242, _T_1243) @[pic_ctrl.scala 33:55] + node _T_1252 = or(_T_1251, gw_int_pending_23) @[pic_ctrl.scala 33:78] + node _T_1253 = xor(_T_1242, _T_1243) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_24 = mux(_T_1250, _T_1252, _T_1253) @[pic_ctrl.scala 33:8] + node _T_1254 = bits(extintsrc_req_sync, 25, 25) @[pic_ctrl.scala 156:52] + node _T_1255 = bits(gw_config_reg[25], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1256 = bits(gw_config_reg[25], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1257 = bits(gw_clear_reg_we_25, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_24 : UInt<1> gw_int_pending_24 <= UInt<1>("h00") - node _T_1258 = xor(_T_1254, _T_1255) @[pic_ctrl.scala 30:50] - node _T_1259 = eq(_T_1257, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1260 = and(gw_int_pending_24, _T_1259) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_24 = or(_T_1258, _T_1260) @[pic_ctrl.scala 30:72] - reg _T_1261 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1261 <= gw_int_pending_in_24 @[pic_ctrl.scala 31:45] - gw_int_pending_24 <= _T_1261 @[pic_ctrl.scala 31:20] - node _T_1262 = bits(_T_1256, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1263 = xor(_T_1254, _T_1255) @[pic_ctrl.scala 32:55] - node _T_1264 = or(_T_1263, gw_int_pending_24) @[pic_ctrl.scala 32:78] - node _T_1265 = xor(_T_1254, _T_1255) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_25 = mux(_T_1262, _T_1264, _T_1265) @[pic_ctrl.scala 32:8] - node _T_1266 = bits(extintsrc_req_sync, 26, 26) @[pic_ctrl.scala 155:52] - node _T_1267 = bits(gw_config_reg[26], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1268 = bits(gw_config_reg[26], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1269 = bits(gw_clear_reg_we_26, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1258 = xor(_T_1254, _T_1255) @[pic_ctrl.scala 31:50] + node _T_1259 = eq(_T_1257, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1260 = and(gw_int_pending_24, _T_1259) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_24 = or(_T_1258, _T_1260) @[pic_ctrl.scala 31:72] + reg _T_1261 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1261 <= gw_int_pending_in_24 @[pic_ctrl.scala 32:45] + gw_int_pending_24 <= _T_1261 @[pic_ctrl.scala 32:20] + node _T_1262 = bits(_T_1256, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1263 = xor(_T_1254, _T_1255) @[pic_ctrl.scala 33:55] + node _T_1264 = or(_T_1263, gw_int_pending_24) @[pic_ctrl.scala 33:78] + node _T_1265 = xor(_T_1254, _T_1255) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_25 = mux(_T_1262, _T_1264, _T_1265) @[pic_ctrl.scala 33:8] + node _T_1266 = bits(extintsrc_req_sync, 26, 26) @[pic_ctrl.scala 156:52] + node _T_1267 = bits(gw_config_reg[26], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1268 = bits(gw_config_reg[26], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1269 = bits(gw_clear_reg_we_26, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_25 : UInt<1> gw_int_pending_25 <= UInt<1>("h00") - node _T_1270 = xor(_T_1266, _T_1267) @[pic_ctrl.scala 30:50] - node _T_1271 = eq(_T_1269, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1272 = and(gw_int_pending_25, _T_1271) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_25 = or(_T_1270, _T_1272) @[pic_ctrl.scala 30:72] - reg _T_1273 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1273 <= gw_int_pending_in_25 @[pic_ctrl.scala 31:45] - gw_int_pending_25 <= _T_1273 @[pic_ctrl.scala 31:20] - node _T_1274 = bits(_T_1268, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1275 = xor(_T_1266, _T_1267) @[pic_ctrl.scala 32:55] - node _T_1276 = or(_T_1275, gw_int_pending_25) @[pic_ctrl.scala 32:78] - node _T_1277 = xor(_T_1266, _T_1267) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_26 = mux(_T_1274, _T_1276, _T_1277) @[pic_ctrl.scala 32:8] - node _T_1278 = bits(extintsrc_req_sync, 27, 27) @[pic_ctrl.scala 155:52] - node _T_1279 = bits(gw_config_reg[27], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1280 = bits(gw_config_reg[27], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1281 = bits(gw_clear_reg_we_27, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1270 = xor(_T_1266, _T_1267) @[pic_ctrl.scala 31:50] + node _T_1271 = eq(_T_1269, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1272 = and(gw_int_pending_25, _T_1271) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_25 = or(_T_1270, _T_1272) @[pic_ctrl.scala 31:72] + reg _T_1273 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1273 <= gw_int_pending_in_25 @[pic_ctrl.scala 32:45] + gw_int_pending_25 <= _T_1273 @[pic_ctrl.scala 32:20] + node _T_1274 = bits(_T_1268, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1275 = xor(_T_1266, _T_1267) @[pic_ctrl.scala 33:55] + node _T_1276 = or(_T_1275, gw_int_pending_25) @[pic_ctrl.scala 33:78] + node _T_1277 = xor(_T_1266, _T_1267) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_26 = mux(_T_1274, _T_1276, _T_1277) @[pic_ctrl.scala 33:8] + node _T_1278 = bits(extintsrc_req_sync, 27, 27) @[pic_ctrl.scala 156:52] + node _T_1279 = bits(gw_config_reg[27], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1280 = bits(gw_config_reg[27], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1281 = bits(gw_clear_reg_we_27, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_26 : UInt<1> gw_int_pending_26 <= UInt<1>("h00") - node _T_1282 = xor(_T_1278, _T_1279) @[pic_ctrl.scala 30:50] - node _T_1283 = eq(_T_1281, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1284 = and(gw_int_pending_26, _T_1283) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_26 = or(_T_1282, _T_1284) @[pic_ctrl.scala 30:72] - reg _T_1285 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1285 <= gw_int_pending_in_26 @[pic_ctrl.scala 31:45] - gw_int_pending_26 <= _T_1285 @[pic_ctrl.scala 31:20] - node _T_1286 = bits(_T_1280, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1287 = xor(_T_1278, _T_1279) @[pic_ctrl.scala 32:55] - node _T_1288 = or(_T_1287, gw_int_pending_26) @[pic_ctrl.scala 32:78] - node _T_1289 = xor(_T_1278, _T_1279) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_27 = mux(_T_1286, _T_1288, _T_1289) @[pic_ctrl.scala 32:8] - node _T_1290 = bits(extintsrc_req_sync, 28, 28) @[pic_ctrl.scala 155:52] - node _T_1291 = bits(gw_config_reg[28], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1292 = bits(gw_config_reg[28], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1293 = bits(gw_clear_reg_we_28, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1282 = xor(_T_1278, _T_1279) @[pic_ctrl.scala 31:50] + node _T_1283 = eq(_T_1281, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1284 = and(gw_int_pending_26, _T_1283) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_26 = or(_T_1282, _T_1284) @[pic_ctrl.scala 31:72] + reg _T_1285 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1285 <= gw_int_pending_in_26 @[pic_ctrl.scala 32:45] + gw_int_pending_26 <= _T_1285 @[pic_ctrl.scala 32:20] + node _T_1286 = bits(_T_1280, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1287 = xor(_T_1278, _T_1279) @[pic_ctrl.scala 33:55] + node _T_1288 = or(_T_1287, gw_int_pending_26) @[pic_ctrl.scala 33:78] + node _T_1289 = xor(_T_1278, _T_1279) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_27 = mux(_T_1286, _T_1288, _T_1289) @[pic_ctrl.scala 33:8] + node _T_1290 = bits(extintsrc_req_sync, 28, 28) @[pic_ctrl.scala 156:52] + node _T_1291 = bits(gw_config_reg[28], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1292 = bits(gw_config_reg[28], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1293 = bits(gw_clear_reg_we_28, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_27 : UInt<1> gw_int_pending_27 <= UInt<1>("h00") - node _T_1294 = xor(_T_1290, _T_1291) @[pic_ctrl.scala 30:50] - node _T_1295 = eq(_T_1293, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1296 = and(gw_int_pending_27, _T_1295) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_27 = or(_T_1294, _T_1296) @[pic_ctrl.scala 30:72] - reg _T_1297 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1297 <= gw_int_pending_in_27 @[pic_ctrl.scala 31:45] - gw_int_pending_27 <= _T_1297 @[pic_ctrl.scala 31:20] - node _T_1298 = bits(_T_1292, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1299 = xor(_T_1290, _T_1291) @[pic_ctrl.scala 32:55] - node _T_1300 = or(_T_1299, gw_int_pending_27) @[pic_ctrl.scala 32:78] - node _T_1301 = xor(_T_1290, _T_1291) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_28 = mux(_T_1298, _T_1300, _T_1301) @[pic_ctrl.scala 32:8] - node _T_1302 = bits(extintsrc_req_sync, 29, 29) @[pic_ctrl.scala 155:52] - node _T_1303 = bits(gw_config_reg[29], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1304 = bits(gw_config_reg[29], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1305 = bits(gw_clear_reg_we_29, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1294 = xor(_T_1290, _T_1291) @[pic_ctrl.scala 31:50] + node _T_1295 = eq(_T_1293, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1296 = and(gw_int_pending_27, _T_1295) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_27 = or(_T_1294, _T_1296) @[pic_ctrl.scala 31:72] + reg _T_1297 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1297 <= gw_int_pending_in_27 @[pic_ctrl.scala 32:45] + gw_int_pending_27 <= _T_1297 @[pic_ctrl.scala 32:20] + node _T_1298 = bits(_T_1292, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1299 = xor(_T_1290, _T_1291) @[pic_ctrl.scala 33:55] + node _T_1300 = or(_T_1299, gw_int_pending_27) @[pic_ctrl.scala 33:78] + node _T_1301 = xor(_T_1290, _T_1291) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_28 = mux(_T_1298, _T_1300, _T_1301) @[pic_ctrl.scala 33:8] + node _T_1302 = bits(extintsrc_req_sync, 29, 29) @[pic_ctrl.scala 156:52] + node _T_1303 = bits(gw_config_reg[29], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1304 = bits(gw_config_reg[29], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1305 = bits(gw_clear_reg_we_29, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_28 : UInt<1> gw_int_pending_28 <= UInt<1>("h00") - node _T_1306 = xor(_T_1302, _T_1303) @[pic_ctrl.scala 30:50] - node _T_1307 = eq(_T_1305, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1308 = and(gw_int_pending_28, _T_1307) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_28 = or(_T_1306, _T_1308) @[pic_ctrl.scala 30:72] - reg _T_1309 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1309 <= gw_int_pending_in_28 @[pic_ctrl.scala 31:45] - gw_int_pending_28 <= _T_1309 @[pic_ctrl.scala 31:20] - node _T_1310 = bits(_T_1304, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1311 = xor(_T_1302, _T_1303) @[pic_ctrl.scala 32:55] - node _T_1312 = or(_T_1311, gw_int_pending_28) @[pic_ctrl.scala 32:78] - node _T_1313 = xor(_T_1302, _T_1303) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_29 = mux(_T_1310, _T_1312, _T_1313) @[pic_ctrl.scala 32:8] - node _T_1314 = bits(extintsrc_req_sync, 30, 30) @[pic_ctrl.scala 155:52] - node _T_1315 = bits(gw_config_reg[30], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1316 = bits(gw_config_reg[30], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1317 = bits(gw_clear_reg_we_30, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1306 = xor(_T_1302, _T_1303) @[pic_ctrl.scala 31:50] + node _T_1307 = eq(_T_1305, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1308 = and(gw_int_pending_28, _T_1307) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_28 = or(_T_1306, _T_1308) @[pic_ctrl.scala 31:72] + reg _T_1309 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1309 <= gw_int_pending_in_28 @[pic_ctrl.scala 32:45] + gw_int_pending_28 <= _T_1309 @[pic_ctrl.scala 32:20] + node _T_1310 = bits(_T_1304, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1311 = xor(_T_1302, _T_1303) @[pic_ctrl.scala 33:55] + node _T_1312 = or(_T_1311, gw_int_pending_28) @[pic_ctrl.scala 33:78] + node _T_1313 = xor(_T_1302, _T_1303) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_29 = mux(_T_1310, _T_1312, _T_1313) @[pic_ctrl.scala 33:8] + node _T_1314 = bits(extintsrc_req_sync, 30, 30) @[pic_ctrl.scala 156:52] + node _T_1315 = bits(gw_config_reg[30], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1316 = bits(gw_config_reg[30], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1317 = bits(gw_clear_reg_we_30, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_29 : UInt<1> gw_int_pending_29 <= UInt<1>("h00") - node _T_1318 = xor(_T_1314, _T_1315) @[pic_ctrl.scala 30:50] - node _T_1319 = eq(_T_1317, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1320 = and(gw_int_pending_29, _T_1319) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_29 = or(_T_1318, _T_1320) @[pic_ctrl.scala 30:72] - reg _T_1321 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1321 <= gw_int_pending_in_29 @[pic_ctrl.scala 31:45] - gw_int_pending_29 <= _T_1321 @[pic_ctrl.scala 31:20] - node _T_1322 = bits(_T_1316, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1323 = xor(_T_1314, _T_1315) @[pic_ctrl.scala 32:55] - node _T_1324 = or(_T_1323, gw_int_pending_29) @[pic_ctrl.scala 32:78] - node _T_1325 = xor(_T_1314, _T_1315) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_30 = mux(_T_1322, _T_1324, _T_1325) @[pic_ctrl.scala 32:8] - node _T_1326 = bits(extintsrc_req_sync, 31, 31) @[pic_ctrl.scala 155:52] - node _T_1327 = bits(gw_config_reg[31], 0, 0) @[pic_ctrl.scala 155:73] - node _T_1328 = bits(gw_config_reg[31], 1, 1) @[pic_ctrl.scala 155:94] - node _T_1329 = bits(gw_clear_reg_we_31, 0, 0) @[pic_ctrl.scala 155:124] + node _T_1318 = xor(_T_1314, _T_1315) @[pic_ctrl.scala 31:50] + node _T_1319 = eq(_T_1317, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1320 = and(gw_int_pending_29, _T_1319) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_29 = or(_T_1318, _T_1320) @[pic_ctrl.scala 31:72] + reg _T_1321 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1321 <= gw_int_pending_in_29 @[pic_ctrl.scala 32:45] + gw_int_pending_29 <= _T_1321 @[pic_ctrl.scala 32:20] + node _T_1322 = bits(_T_1316, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1323 = xor(_T_1314, _T_1315) @[pic_ctrl.scala 33:55] + node _T_1324 = or(_T_1323, gw_int_pending_29) @[pic_ctrl.scala 33:78] + node _T_1325 = xor(_T_1314, _T_1315) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_30 = mux(_T_1322, _T_1324, _T_1325) @[pic_ctrl.scala 33:8] + node _T_1326 = bits(extintsrc_req_sync, 31, 31) @[pic_ctrl.scala 156:52] + node _T_1327 = bits(gw_config_reg[31], 0, 0) @[pic_ctrl.scala 156:73] + node _T_1328 = bits(gw_config_reg[31], 1, 1) @[pic_ctrl.scala 156:94] + node _T_1329 = bits(gw_clear_reg_we_31, 0, 0) @[pic_ctrl.scala 156:124] wire gw_int_pending_30 : UInt<1> gw_int_pending_30 <= UInt<1>("h00") - node _T_1330 = xor(_T_1326, _T_1327) @[pic_ctrl.scala 30:50] - node _T_1331 = eq(_T_1329, UInt<1>("h00")) @[pic_ctrl.scala 30:92] - node _T_1332 = and(gw_int_pending_30, _T_1331) @[pic_ctrl.scala 30:90] - node gw_int_pending_in_30 = or(_T_1330, _T_1332) @[pic_ctrl.scala 30:72] - reg _T_1333 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 31:45] - _T_1333 <= gw_int_pending_in_30 @[pic_ctrl.scala 31:45] - gw_int_pending_30 <= _T_1333 @[pic_ctrl.scala 31:20] - node _T_1334 = bits(_T_1328, 0, 0) @[pic_ctrl.scala 32:30] - node _T_1335 = xor(_T_1326, _T_1327) @[pic_ctrl.scala 32:55] - node _T_1336 = or(_T_1335, gw_int_pending_30) @[pic_ctrl.scala 32:78] - node _T_1337 = xor(_T_1326, _T_1327) @[pic_ctrl.scala 32:117] - node extintsrc_req_gw_31 = mux(_T_1334, _T_1336, _T_1337) @[pic_ctrl.scala 32:8] - node _T_1338 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1339 = not(intpriority_reg[0]) @[pic_ctrl.scala 159:90] - node _T_1340 = mux(_T_1338, _T_1339, intpriority_reg[0]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[0] <= _T_1340 @[pic_ctrl.scala 159:65] - node _T_1341 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1342 = not(intpriority_reg[1]) @[pic_ctrl.scala 159:90] - node _T_1343 = mux(_T_1341, _T_1342, intpriority_reg[1]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[1] <= _T_1343 @[pic_ctrl.scala 159:65] - node _T_1344 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1345 = not(intpriority_reg[2]) @[pic_ctrl.scala 159:90] - node _T_1346 = mux(_T_1344, _T_1345, intpriority_reg[2]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[2] <= _T_1346 @[pic_ctrl.scala 159:65] - node _T_1347 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1348 = not(intpriority_reg[3]) @[pic_ctrl.scala 159:90] - node _T_1349 = mux(_T_1347, _T_1348, intpriority_reg[3]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[3] <= _T_1349 @[pic_ctrl.scala 159:65] - node _T_1350 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1351 = not(intpriority_reg[4]) @[pic_ctrl.scala 159:90] - node _T_1352 = mux(_T_1350, _T_1351, intpriority_reg[4]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[4] <= _T_1352 @[pic_ctrl.scala 159:65] - node _T_1353 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1354 = not(intpriority_reg[5]) @[pic_ctrl.scala 159:90] - node _T_1355 = mux(_T_1353, _T_1354, intpriority_reg[5]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[5] <= _T_1355 @[pic_ctrl.scala 159:65] - node _T_1356 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1357 = not(intpriority_reg[6]) @[pic_ctrl.scala 159:90] - node _T_1358 = mux(_T_1356, _T_1357, intpriority_reg[6]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[6] <= _T_1358 @[pic_ctrl.scala 159:65] - node _T_1359 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1360 = not(intpriority_reg[7]) @[pic_ctrl.scala 159:90] - node _T_1361 = mux(_T_1359, _T_1360, intpriority_reg[7]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[7] <= _T_1361 @[pic_ctrl.scala 159:65] - node _T_1362 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1363 = not(intpriority_reg[8]) @[pic_ctrl.scala 159:90] - node _T_1364 = mux(_T_1362, _T_1363, intpriority_reg[8]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[8] <= _T_1364 @[pic_ctrl.scala 159:65] - node _T_1365 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1366 = not(intpriority_reg[9]) @[pic_ctrl.scala 159:90] - node _T_1367 = mux(_T_1365, _T_1366, intpriority_reg[9]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[9] <= _T_1367 @[pic_ctrl.scala 159:65] - node _T_1368 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1369 = not(intpriority_reg[10]) @[pic_ctrl.scala 159:90] - node _T_1370 = mux(_T_1368, _T_1369, intpriority_reg[10]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[10] <= _T_1370 @[pic_ctrl.scala 159:65] - node _T_1371 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1372 = not(intpriority_reg[11]) @[pic_ctrl.scala 159:90] - node _T_1373 = mux(_T_1371, _T_1372, intpriority_reg[11]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[11] <= _T_1373 @[pic_ctrl.scala 159:65] - node _T_1374 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1375 = not(intpriority_reg[12]) @[pic_ctrl.scala 159:90] - node _T_1376 = mux(_T_1374, _T_1375, intpriority_reg[12]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[12] <= _T_1376 @[pic_ctrl.scala 159:65] - node _T_1377 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1378 = not(intpriority_reg[13]) @[pic_ctrl.scala 159:90] - node _T_1379 = mux(_T_1377, _T_1378, intpriority_reg[13]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[13] <= _T_1379 @[pic_ctrl.scala 159:65] - node _T_1380 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1381 = not(intpriority_reg[14]) @[pic_ctrl.scala 159:90] - node _T_1382 = mux(_T_1380, _T_1381, intpriority_reg[14]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[14] <= _T_1382 @[pic_ctrl.scala 159:65] - node _T_1383 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1384 = not(intpriority_reg[15]) @[pic_ctrl.scala 159:90] - node _T_1385 = mux(_T_1383, _T_1384, intpriority_reg[15]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[15] <= _T_1385 @[pic_ctrl.scala 159:65] - node _T_1386 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1387 = not(intpriority_reg[16]) @[pic_ctrl.scala 159:90] - node _T_1388 = mux(_T_1386, _T_1387, intpriority_reg[16]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[16] <= _T_1388 @[pic_ctrl.scala 159:65] - node _T_1389 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1390 = not(intpriority_reg[17]) @[pic_ctrl.scala 159:90] - node _T_1391 = mux(_T_1389, _T_1390, intpriority_reg[17]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[17] <= _T_1391 @[pic_ctrl.scala 159:65] - node _T_1392 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1393 = not(intpriority_reg[18]) @[pic_ctrl.scala 159:90] - node _T_1394 = mux(_T_1392, _T_1393, intpriority_reg[18]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[18] <= _T_1394 @[pic_ctrl.scala 159:65] - node _T_1395 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1396 = not(intpriority_reg[19]) @[pic_ctrl.scala 159:90] - node _T_1397 = mux(_T_1395, _T_1396, intpriority_reg[19]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[19] <= _T_1397 @[pic_ctrl.scala 159:65] - node _T_1398 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1399 = not(intpriority_reg[20]) @[pic_ctrl.scala 159:90] - node _T_1400 = mux(_T_1398, _T_1399, intpriority_reg[20]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[20] <= _T_1400 @[pic_ctrl.scala 159:65] - node _T_1401 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1402 = not(intpriority_reg[21]) @[pic_ctrl.scala 159:90] - node _T_1403 = mux(_T_1401, _T_1402, intpriority_reg[21]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[21] <= _T_1403 @[pic_ctrl.scala 159:65] - node _T_1404 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1405 = not(intpriority_reg[22]) @[pic_ctrl.scala 159:90] - node _T_1406 = mux(_T_1404, _T_1405, intpriority_reg[22]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[22] <= _T_1406 @[pic_ctrl.scala 159:65] - node _T_1407 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1408 = not(intpriority_reg[23]) @[pic_ctrl.scala 159:90] - node _T_1409 = mux(_T_1407, _T_1408, intpriority_reg[23]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[23] <= _T_1409 @[pic_ctrl.scala 159:65] - node _T_1410 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1411 = not(intpriority_reg[24]) @[pic_ctrl.scala 159:90] - node _T_1412 = mux(_T_1410, _T_1411, intpriority_reg[24]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[24] <= _T_1412 @[pic_ctrl.scala 159:65] - node _T_1413 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1414 = not(intpriority_reg[25]) @[pic_ctrl.scala 159:90] - node _T_1415 = mux(_T_1413, _T_1414, intpriority_reg[25]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[25] <= _T_1415 @[pic_ctrl.scala 159:65] - node _T_1416 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1417 = not(intpriority_reg[26]) @[pic_ctrl.scala 159:90] - node _T_1418 = mux(_T_1416, _T_1417, intpriority_reg[26]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[26] <= _T_1418 @[pic_ctrl.scala 159:65] - node _T_1419 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1420 = not(intpriority_reg[27]) @[pic_ctrl.scala 159:90] - node _T_1421 = mux(_T_1419, _T_1420, intpriority_reg[27]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[27] <= _T_1421 @[pic_ctrl.scala 159:65] - node _T_1422 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1423 = not(intpriority_reg[28]) @[pic_ctrl.scala 159:90] - node _T_1424 = mux(_T_1422, _T_1423, intpriority_reg[28]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[28] <= _T_1424 @[pic_ctrl.scala 159:65] - node _T_1425 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1426 = not(intpriority_reg[29]) @[pic_ctrl.scala 159:90] - node _T_1427 = mux(_T_1425, _T_1426, intpriority_reg[29]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[29] <= _T_1427 @[pic_ctrl.scala 159:65] - node _T_1428 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1429 = not(intpriority_reg[30]) @[pic_ctrl.scala 159:90] - node _T_1430 = mux(_T_1428, _T_1429, intpriority_reg[30]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[30] <= _T_1430 @[pic_ctrl.scala 159:65] - node _T_1431 = bits(intpriord, 0, 0) @[pic_ctrl.scala 159:82] - node _T_1432 = not(intpriority_reg[31]) @[pic_ctrl.scala 159:90] - node _T_1433 = mux(_T_1431, _T_1432, intpriority_reg[31]) @[pic_ctrl.scala 159:71] - intpriority_reg_inv[31] <= _T_1433 @[pic_ctrl.scala 159:65] - node _T_1434 = and(UInt<1>("h00"), intenable_reg[0]) @[pic_ctrl.scala 160:110] + node _T_1330 = xor(_T_1326, _T_1327) @[pic_ctrl.scala 31:50] + node _T_1331 = eq(_T_1329, UInt<1>("h00")) @[pic_ctrl.scala 31:92] + node _T_1332 = and(gw_int_pending_30, _T_1331) @[pic_ctrl.scala 31:90] + node gw_int_pending_in_30 = or(_T_1330, _T_1332) @[pic_ctrl.scala 31:72] + reg _T_1333 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 32:45] + _T_1333 <= gw_int_pending_in_30 @[pic_ctrl.scala 32:45] + gw_int_pending_30 <= _T_1333 @[pic_ctrl.scala 32:20] + node _T_1334 = bits(_T_1328, 0, 0) @[pic_ctrl.scala 33:30] + node _T_1335 = xor(_T_1326, _T_1327) @[pic_ctrl.scala 33:55] + node _T_1336 = or(_T_1335, gw_int_pending_30) @[pic_ctrl.scala 33:78] + node _T_1337 = xor(_T_1326, _T_1327) @[pic_ctrl.scala 33:117] + node extintsrc_req_gw_31 = mux(_T_1334, _T_1336, _T_1337) @[pic_ctrl.scala 33:8] + node _T_1338 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1339 = not(intpriority_reg[0]) @[pic_ctrl.scala 160:90] + node _T_1340 = mux(_T_1338, _T_1339, intpriority_reg[0]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[0] <= _T_1340 @[pic_ctrl.scala 160:65] + node _T_1341 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1342 = not(intpriority_reg[1]) @[pic_ctrl.scala 160:90] + node _T_1343 = mux(_T_1341, _T_1342, intpriority_reg[1]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[1] <= _T_1343 @[pic_ctrl.scala 160:65] + node _T_1344 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1345 = not(intpriority_reg[2]) @[pic_ctrl.scala 160:90] + node _T_1346 = mux(_T_1344, _T_1345, intpriority_reg[2]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[2] <= _T_1346 @[pic_ctrl.scala 160:65] + node _T_1347 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1348 = not(intpriority_reg[3]) @[pic_ctrl.scala 160:90] + node _T_1349 = mux(_T_1347, _T_1348, intpriority_reg[3]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[3] <= _T_1349 @[pic_ctrl.scala 160:65] + node _T_1350 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1351 = not(intpriority_reg[4]) @[pic_ctrl.scala 160:90] + node _T_1352 = mux(_T_1350, _T_1351, intpriority_reg[4]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[4] <= _T_1352 @[pic_ctrl.scala 160:65] + node _T_1353 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1354 = not(intpriority_reg[5]) @[pic_ctrl.scala 160:90] + node _T_1355 = mux(_T_1353, _T_1354, intpriority_reg[5]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[5] <= _T_1355 @[pic_ctrl.scala 160:65] + node _T_1356 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1357 = not(intpriority_reg[6]) @[pic_ctrl.scala 160:90] + node _T_1358 = mux(_T_1356, _T_1357, intpriority_reg[6]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[6] <= _T_1358 @[pic_ctrl.scala 160:65] + node _T_1359 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1360 = not(intpriority_reg[7]) @[pic_ctrl.scala 160:90] + node _T_1361 = mux(_T_1359, _T_1360, intpriority_reg[7]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[7] <= _T_1361 @[pic_ctrl.scala 160:65] + node _T_1362 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1363 = not(intpriority_reg[8]) @[pic_ctrl.scala 160:90] + node _T_1364 = mux(_T_1362, _T_1363, intpriority_reg[8]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[8] <= _T_1364 @[pic_ctrl.scala 160:65] + node _T_1365 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1366 = not(intpriority_reg[9]) @[pic_ctrl.scala 160:90] + node _T_1367 = mux(_T_1365, _T_1366, intpriority_reg[9]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[9] <= _T_1367 @[pic_ctrl.scala 160:65] + node _T_1368 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1369 = not(intpriority_reg[10]) @[pic_ctrl.scala 160:90] + node _T_1370 = mux(_T_1368, _T_1369, intpriority_reg[10]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[10] <= _T_1370 @[pic_ctrl.scala 160:65] + node _T_1371 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1372 = not(intpriority_reg[11]) @[pic_ctrl.scala 160:90] + node _T_1373 = mux(_T_1371, _T_1372, intpriority_reg[11]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[11] <= _T_1373 @[pic_ctrl.scala 160:65] + node _T_1374 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1375 = not(intpriority_reg[12]) @[pic_ctrl.scala 160:90] + node _T_1376 = mux(_T_1374, _T_1375, intpriority_reg[12]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[12] <= _T_1376 @[pic_ctrl.scala 160:65] + node _T_1377 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1378 = not(intpriority_reg[13]) @[pic_ctrl.scala 160:90] + node _T_1379 = mux(_T_1377, _T_1378, intpriority_reg[13]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[13] <= _T_1379 @[pic_ctrl.scala 160:65] + node _T_1380 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1381 = not(intpriority_reg[14]) @[pic_ctrl.scala 160:90] + node _T_1382 = mux(_T_1380, _T_1381, intpriority_reg[14]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[14] <= _T_1382 @[pic_ctrl.scala 160:65] + node _T_1383 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1384 = not(intpriority_reg[15]) @[pic_ctrl.scala 160:90] + node _T_1385 = mux(_T_1383, _T_1384, intpriority_reg[15]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[15] <= _T_1385 @[pic_ctrl.scala 160:65] + node _T_1386 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1387 = not(intpriority_reg[16]) @[pic_ctrl.scala 160:90] + node _T_1388 = mux(_T_1386, _T_1387, intpriority_reg[16]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[16] <= _T_1388 @[pic_ctrl.scala 160:65] + node _T_1389 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1390 = not(intpriority_reg[17]) @[pic_ctrl.scala 160:90] + node _T_1391 = mux(_T_1389, _T_1390, intpriority_reg[17]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[17] <= _T_1391 @[pic_ctrl.scala 160:65] + node _T_1392 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1393 = not(intpriority_reg[18]) @[pic_ctrl.scala 160:90] + node _T_1394 = mux(_T_1392, _T_1393, intpriority_reg[18]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[18] <= _T_1394 @[pic_ctrl.scala 160:65] + node _T_1395 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1396 = not(intpriority_reg[19]) @[pic_ctrl.scala 160:90] + node _T_1397 = mux(_T_1395, _T_1396, intpriority_reg[19]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[19] <= _T_1397 @[pic_ctrl.scala 160:65] + node _T_1398 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1399 = not(intpriority_reg[20]) @[pic_ctrl.scala 160:90] + node _T_1400 = mux(_T_1398, _T_1399, intpriority_reg[20]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[20] <= _T_1400 @[pic_ctrl.scala 160:65] + node _T_1401 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1402 = not(intpriority_reg[21]) @[pic_ctrl.scala 160:90] + node _T_1403 = mux(_T_1401, _T_1402, intpriority_reg[21]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[21] <= _T_1403 @[pic_ctrl.scala 160:65] + node _T_1404 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1405 = not(intpriority_reg[22]) @[pic_ctrl.scala 160:90] + node _T_1406 = mux(_T_1404, _T_1405, intpriority_reg[22]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[22] <= _T_1406 @[pic_ctrl.scala 160:65] + node _T_1407 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1408 = not(intpriority_reg[23]) @[pic_ctrl.scala 160:90] + node _T_1409 = mux(_T_1407, _T_1408, intpriority_reg[23]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[23] <= _T_1409 @[pic_ctrl.scala 160:65] + node _T_1410 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1411 = not(intpriority_reg[24]) @[pic_ctrl.scala 160:90] + node _T_1412 = mux(_T_1410, _T_1411, intpriority_reg[24]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[24] <= _T_1412 @[pic_ctrl.scala 160:65] + node _T_1413 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1414 = not(intpriority_reg[25]) @[pic_ctrl.scala 160:90] + node _T_1415 = mux(_T_1413, _T_1414, intpriority_reg[25]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[25] <= _T_1415 @[pic_ctrl.scala 160:65] + node _T_1416 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1417 = not(intpriority_reg[26]) @[pic_ctrl.scala 160:90] + node _T_1418 = mux(_T_1416, _T_1417, intpriority_reg[26]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[26] <= _T_1418 @[pic_ctrl.scala 160:65] + node _T_1419 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1420 = not(intpriority_reg[27]) @[pic_ctrl.scala 160:90] + node _T_1421 = mux(_T_1419, _T_1420, intpriority_reg[27]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[27] <= _T_1421 @[pic_ctrl.scala 160:65] + node _T_1422 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1423 = not(intpriority_reg[28]) @[pic_ctrl.scala 160:90] + node _T_1424 = mux(_T_1422, _T_1423, intpriority_reg[28]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[28] <= _T_1424 @[pic_ctrl.scala 160:65] + node _T_1425 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1426 = not(intpriority_reg[29]) @[pic_ctrl.scala 160:90] + node _T_1427 = mux(_T_1425, _T_1426, intpriority_reg[29]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[29] <= _T_1427 @[pic_ctrl.scala 160:65] + node _T_1428 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1429 = not(intpriority_reg[30]) @[pic_ctrl.scala 160:90] + node _T_1430 = mux(_T_1428, _T_1429, intpriority_reg[30]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[30] <= _T_1430 @[pic_ctrl.scala 160:65] + node _T_1431 = bits(intpriord, 0, 0) @[pic_ctrl.scala 160:82] + node _T_1432 = not(intpriority_reg[31]) @[pic_ctrl.scala 160:90] + node _T_1433 = mux(_T_1431, _T_1432, intpriority_reg[31]) @[pic_ctrl.scala 160:71] + intpriority_reg_inv[31] <= _T_1433 @[pic_ctrl.scala 160:65] + node _T_1434 = and(UInt<1>("h00"), intenable_reg[0]) @[pic_ctrl.scala 161:110] node _T_1435 = bits(_T_1434, 0, 0) @[Bitwise.scala 72:15] node _T_1436 = mux(_T_1435, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1437 = and(_T_1436, intpriority_reg_inv[0]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[0] <= _T_1437 @[pic_ctrl.scala 160:64] - node _T_1438 = and(extintsrc_req_gw_1, intenable_reg[1]) @[pic_ctrl.scala 160:110] + node _T_1437 = and(_T_1436, intpriority_reg_inv[0]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[0] <= _T_1437 @[pic_ctrl.scala 161:64] + node _T_1438 = and(extintsrc_req_gw_1, intenable_reg[1]) @[pic_ctrl.scala 161:110] node _T_1439 = bits(_T_1438, 0, 0) @[Bitwise.scala 72:15] node _T_1440 = mux(_T_1439, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1441 = and(_T_1440, intpriority_reg_inv[1]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[1] <= _T_1441 @[pic_ctrl.scala 160:64] - node _T_1442 = and(extintsrc_req_gw_2, intenable_reg[2]) @[pic_ctrl.scala 160:110] + node _T_1441 = and(_T_1440, intpriority_reg_inv[1]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[1] <= _T_1441 @[pic_ctrl.scala 161:64] + node _T_1442 = and(extintsrc_req_gw_2, intenable_reg[2]) @[pic_ctrl.scala 161:110] node _T_1443 = bits(_T_1442, 0, 0) @[Bitwise.scala 72:15] node _T_1444 = mux(_T_1443, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1445 = and(_T_1444, intpriority_reg_inv[2]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[2] <= _T_1445 @[pic_ctrl.scala 160:64] - node _T_1446 = and(extintsrc_req_gw_3, intenable_reg[3]) @[pic_ctrl.scala 160:110] + node _T_1445 = and(_T_1444, intpriority_reg_inv[2]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[2] <= _T_1445 @[pic_ctrl.scala 161:64] + node _T_1446 = and(extintsrc_req_gw_3, intenable_reg[3]) @[pic_ctrl.scala 161:110] node _T_1447 = bits(_T_1446, 0, 0) @[Bitwise.scala 72:15] node _T_1448 = mux(_T_1447, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1449 = and(_T_1448, intpriority_reg_inv[3]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[3] <= _T_1449 @[pic_ctrl.scala 160:64] - node _T_1450 = and(extintsrc_req_gw_4, intenable_reg[4]) @[pic_ctrl.scala 160:110] + node _T_1449 = and(_T_1448, intpriority_reg_inv[3]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[3] <= _T_1449 @[pic_ctrl.scala 161:64] + node _T_1450 = and(extintsrc_req_gw_4, intenable_reg[4]) @[pic_ctrl.scala 161:110] node _T_1451 = bits(_T_1450, 0, 0) @[Bitwise.scala 72:15] node _T_1452 = mux(_T_1451, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1453 = and(_T_1452, intpriority_reg_inv[4]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[4] <= _T_1453 @[pic_ctrl.scala 160:64] - node _T_1454 = and(extintsrc_req_gw_5, intenable_reg[5]) @[pic_ctrl.scala 160:110] + node _T_1453 = and(_T_1452, intpriority_reg_inv[4]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[4] <= _T_1453 @[pic_ctrl.scala 161:64] + node _T_1454 = and(extintsrc_req_gw_5, intenable_reg[5]) @[pic_ctrl.scala 161:110] node _T_1455 = bits(_T_1454, 0, 0) @[Bitwise.scala 72:15] node _T_1456 = mux(_T_1455, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1457 = and(_T_1456, intpriority_reg_inv[5]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[5] <= _T_1457 @[pic_ctrl.scala 160:64] - node _T_1458 = and(extintsrc_req_gw_6, intenable_reg[6]) @[pic_ctrl.scala 160:110] + node _T_1457 = and(_T_1456, intpriority_reg_inv[5]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[5] <= _T_1457 @[pic_ctrl.scala 161:64] + node _T_1458 = and(extintsrc_req_gw_6, intenable_reg[6]) @[pic_ctrl.scala 161:110] node _T_1459 = bits(_T_1458, 0, 0) @[Bitwise.scala 72:15] node _T_1460 = mux(_T_1459, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1461 = and(_T_1460, intpriority_reg_inv[6]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[6] <= _T_1461 @[pic_ctrl.scala 160:64] - node _T_1462 = and(extintsrc_req_gw_7, intenable_reg[7]) @[pic_ctrl.scala 160:110] + node _T_1461 = and(_T_1460, intpriority_reg_inv[6]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[6] <= _T_1461 @[pic_ctrl.scala 161:64] + node _T_1462 = and(extintsrc_req_gw_7, intenable_reg[7]) @[pic_ctrl.scala 161:110] node _T_1463 = bits(_T_1462, 0, 0) @[Bitwise.scala 72:15] node _T_1464 = mux(_T_1463, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1465 = and(_T_1464, intpriority_reg_inv[7]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[7] <= _T_1465 @[pic_ctrl.scala 160:64] - node _T_1466 = and(extintsrc_req_gw_8, intenable_reg[8]) @[pic_ctrl.scala 160:110] + node _T_1465 = and(_T_1464, intpriority_reg_inv[7]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[7] <= _T_1465 @[pic_ctrl.scala 161:64] + node _T_1466 = and(extintsrc_req_gw_8, intenable_reg[8]) @[pic_ctrl.scala 161:110] node _T_1467 = bits(_T_1466, 0, 0) @[Bitwise.scala 72:15] node _T_1468 = mux(_T_1467, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1469 = and(_T_1468, intpriority_reg_inv[8]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[8] <= _T_1469 @[pic_ctrl.scala 160:64] - node _T_1470 = and(extintsrc_req_gw_9, intenable_reg[9]) @[pic_ctrl.scala 160:110] + node _T_1469 = and(_T_1468, intpriority_reg_inv[8]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[8] <= _T_1469 @[pic_ctrl.scala 161:64] + node _T_1470 = and(extintsrc_req_gw_9, intenable_reg[9]) @[pic_ctrl.scala 161:110] node _T_1471 = bits(_T_1470, 0, 0) @[Bitwise.scala 72:15] node _T_1472 = mux(_T_1471, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1473 = and(_T_1472, intpriority_reg_inv[9]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[9] <= _T_1473 @[pic_ctrl.scala 160:64] - node _T_1474 = and(extintsrc_req_gw_10, intenable_reg[10]) @[pic_ctrl.scala 160:110] + node _T_1473 = and(_T_1472, intpriority_reg_inv[9]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[9] <= _T_1473 @[pic_ctrl.scala 161:64] + node _T_1474 = and(extintsrc_req_gw_10, intenable_reg[10]) @[pic_ctrl.scala 161:110] node _T_1475 = bits(_T_1474, 0, 0) @[Bitwise.scala 72:15] node _T_1476 = mux(_T_1475, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1477 = and(_T_1476, intpriority_reg_inv[10]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[10] <= _T_1477 @[pic_ctrl.scala 160:64] - node _T_1478 = and(extintsrc_req_gw_11, intenable_reg[11]) @[pic_ctrl.scala 160:110] + node _T_1477 = and(_T_1476, intpriority_reg_inv[10]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[10] <= _T_1477 @[pic_ctrl.scala 161:64] + node _T_1478 = and(extintsrc_req_gw_11, intenable_reg[11]) @[pic_ctrl.scala 161:110] node _T_1479 = bits(_T_1478, 0, 0) @[Bitwise.scala 72:15] node _T_1480 = mux(_T_1479, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1481 = and(_T_1480, intpriority_reg_inv[11]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[11] <= _T_1481 @[pic_ctrl.scala 160:64] - node _T_1482 = and(extintsrc_req_gw_12, intenable_reg[12]) @[pic_ctrl.scala 160:110] + node _T_1481 = and(_T_1480, intpriority_reg_inv[11]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[11] <= _T_1481 @[pic_ctrl.scala 161:64] + node _T_1482 = and(extintsrc_req_gw_12, intenable_reg[12]) @[pic_ctrl.scala 161:110] node _T_1483 = bits(_T_1482, 0, 0) @[Bitwise.scala 72:15] node _T_1484 = mux(_T_1483, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1485 = and(_T_1484, intpriority_reg_inv[12]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[12] <= _T_1485 @[pic_ctrl.scala 160:64] - node _T_1486 = and(extintsrc_req_gw_13, intenable_reg[13]) @[pic_ctrl.scala 160:110] + node _T_1485 = and(_T_1484, intpriority_reg_inv[12]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[12] <= _T_1485 @[pic_ctrl.scala 161:64] + node _T_1486 = and(extintsrc_req_gw_13, intenable_reg[13]) @[pic_ctrl.scala 161:110] node _T_1487 = bits(_T_1486, 0, 0) @[Bitwise.scala 72:15] node _T_1488 = mux(_T_1487, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1489 = and(_T_1488, intpriority_reg_inv[13]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[13] <= _T_1489 @[pic_ctrl.scala 160:64] - node _T_1490 = and(extintsrc_req_gw_14, intenable_reg[14]) @[pic_ctrl.scala 160:110] + node _T_1489 = and(_T_1488, intpriority_reg_inv[13]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[13] <= _T_1489 @[pic_ctrl.scala 161:64] + node _T_1490 = and(extintsrc_req_gw_14, intenable_reg[14]) @[pic_ctrl.scala 161:110] node _T_1491 = bits(_T_1490, 0, 0) @[Bitwise.scala 72:15] node _T_1492 = mux(_T_1491, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1493 = and(_T_1492, intpriority_reg_inv[14]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[14] <= _T_1493 @[pic_ctrl.scala 160:64] - node _T_1494 = and(extintsrc_req_gw_15, intenable_reg[15]) @[pic_ctrl.scala 160:110] + node _T_1493 = and(_T_1492, intpriority_reg_inv[14]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[14] <= _T_1493 @[pic_ctrl.scala 161:64] + node _T_1494 = and(extintsrc_req_gw_15, intenable_reg[15]) @[pic_ctrl.scala 161:110] node _T_1495 = bits(_T_1494, 0, 0) @[Bitwise.scala 72:15] node _T_1496 = mux(_T_1495, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1497 = and(_T_1496, intpriority_reg_inv[15]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[15] <= _T_1497 @[pic_ctrl.scala 160:64] - node _T_1498 = and(extintsrc_req_gw_16, intenable_reg[16]) @[pic_ctrl.scala 160:110] + node _T_1497 = and(_T_1496, intpriority_reg_inv[15]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[15] <= _T_1497 @[pic_ctrl.scala 161:64] + node _T_1498 = and(extintsrc_req_gw_16, intenable_reg[16]) @[pic_ctrl.scala 161:110] node _T_1499 = bits(_T_1498, 0, 0) @[Bitwise.scala 72:15] node _T_1500 = mux(_T_1499, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1501 = and(_T_1500, intpriority_reg_inv[16]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[16] <= _T_1501 @[pic_ctrl.scala 160:64] - node _T_1502 = and(extintsrc_req_gw_17, intenable_reg[17]) @[pic_ctrl.scala 160:110] + node _T_1501 = and(_T_1500, intpriority_reg_inv[16]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[16] <= _T_1501 @[pic_ctrl.scala 161:64] + node _T_1502 = and(extintsrc_req_gw_17, intenable_reg[17]) @[pic_ctrl.scala 161:110] node _T_1503 = bits(_T_1502, 0, 0) @[Bitwise.scala 72:15] node _T_1504 = mux(_T_1503, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1505 = and(_T_1504, intpriority_reg_inv[17]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[17] <= _T_1505 @[pic_ctrl.scala 160:64] - node _T_1506 = and(extintsrc_req_gw_18, intenable_reg[18]) @[pic_ctrl.scala 160:110] + node _T_1505 = and(_T_1504, intpriority_reg_inv[17]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[17] <= _T_1505 @[pic_ctrl.scala 161:64] + node _T_1506 = and(extintsrc_req_gw_18, intenable_reg[18]) @[pic_ctrl.scala 161:110] node _T_1507 = bits(_T_1506, 0, 0) @[Bitwise.scala 72:15] node _T_1508 = mux(_T_1507, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1509 = and(_T_1508, intpriority_reg_inv[18]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[18] <= _T_1509 @[pic_ctrl.scala 160:64] - node _T_1510 = and(extintsrc_req_gw_19, intenable_reg[19]) @[pic_ctrl.scala 160:110] + node _T_1509 = and(_T_1508, intpriority_reg_inv[18]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[18] <= _T_1509 @[pic_ctrl.scala 161:64] + node _T_1510 = and(extintsrc_req_gw_19, intenable_reg[19]) @[pic_ctrl.scala 161:110] node _T_1511 = bits(_T_1510, 0, 0) @[Bitwise.scala 72:15] node _T_1512 = mux(_T_1511, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1513 = and(_T_1512, intpriority_reg_inv[19]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[19] <= _T_1513 @[pic_ctrl.scala 160:64] - node _T_1514 = and(extintsrc_req_gw_20, intenable_reg[20]) @[pic_ctrl.scala 160:110] + node _T_1513 = and(_T_1512, intpriority_reg_inv[19]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[19] <= _T_1513 @[pic_ctrl.scala 161:64] + node _T_1514 = and(extintsrc_req_gw_20, intenable_reg[20]) @[pic_ctrl.scala 161:110] node _T_1515 = bits(_T_1514, 0, 0) @[Bitwise.scala 72:15] node _T_1516 = mux(_T_1515, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1517 = and(_T_1516, intpriority_reg_inv[20]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[20] <= _T_1517 @[pic_ctrl.scala 160:64] - node _T_1518 = and(extintsrc_req_gw_21, intenable_reg[21]) @[pic_ctrl.scala 160:110] + node _T_1517 = and(_T_1516, intpriority_reg_inv[20]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[20] <= _T_1517 @[pic_ctrl.scala 161:64] + node _T_1518 = and(extintsrc_req_gw_21, intenable_reg[21]) @[pic_ctrl.scala 161:110] node _T_1519 = bits(_T_1518, 0, 0) @[Bitwise.scala 72:15] node _T_1520 = mux(_T_1519, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1521 = and(_T_1520, intpriority_reg_inv[21]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[21] <= _T_1521 @[pic_ctrl.scala 160:64] - node _T_1522 = and(extintsrc_req_gw_22, intenable_reg[22]) @[pic_ctrl.scala 160:110] + node _T_1521 = and(_T_1520, intpriority_reg_inv[21]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[21] <= _T_1521 @[pic_ctrl.scala 161:64] + node _T_1522 = and(extintsrc_req_gw_22, intenable_reg[22]) @[pic_ctrl.scala 161:110] node _T_1523 = bits(_T_1522, 0, 0) @[Bitwise.scala 72:15] node _T_1524 = mux(_T_1523, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1525 = and(_T_1524, intpriority_reg_inv[22]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[22] <= _T_1525 @[pic_ctrl.scala 160:64] - node _T_1526 = and(extintsrc_req_gw_23, intenable_reg[23]) @[pic_ctrl.scala 160:110] + node _T_1525 = and(_T_1524, intpriority_reg_inv[22]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[22] <= _T_1525 @[pic_ctrl.scala 161:64] + node _T_1526 = and(extintsrc_req_gw_23, intenable_reg[23]) @[pic_ctrl.scala 161:110] node _T_1527 = bits(_T_1526, 0, 0) @[Bitwise.scala 72:15] node _T_1528 = mux(_T_1527, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1529 = and(_T_1528, intpriority_reg_inv[23]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[23] <= _T_1529 @[pic_ctrl.scala 160:64] - node _T_1530 = and(extintsrc_req_gw_24, intenable_reg[24]) @[pic_ctrl.scala 160:110] + node _T_1529 = and(_T_1528, intpriority_reg_inv[23]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[23] <= _T_1529 @[pic_ctrl.scala 161:64] + node _T_1530 = and(extintsrc_req_gw_24, intenable_reg[24]) @[pic_ctrl.scala 161:110] node _T_1531 = bits(_T_1530, 0, 0) @[Bitwise.scala 72:15] node _T_1532 = mux(_T_1531, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1533 = and(_T_1532, intpriority_reg_inv[24]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[24] <= _T_1533 @[pic_ctrl.scala 160:64] - node _T_1534 = and(extintsrc_req_gw_25, intenable_reg[25]) @[pic_ctrl.scala 160:110] + node _T_1533 = and(_T_1532, intpriority_reg_inv[24]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[24] <= _T_1533 @[pic_ctrl.scala 161:64] + node _T_1534 = and(extintsrc_req_gw_25, intenable_reg[25]) @[pic_ctrl.scala 161:110] node _T_1535 = bits(_T_1534, 0, 0) @[Bitwise.scala 72:15] node _T_1536 = mux(_T_1535, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1537 = and(_T_1536, intpriority_reg_inv[25]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[25] <= _T_1537 @[pic_ctrl.scala 160:64] - node _T_1538 = and(extintsrc_req_gw_26, intenable_reg[26]) @[pic_ctrl.scala 160:110] + node _T_1537 = and(_T_1536, intpriority_reg_inv[25]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[25] <= _T_1537 @[pic_ctrl.scala 161:64] + node _T_1538 = and(extintsrc_req_gw_26, intenable_reg[26]) @[pic_ctrl.scala 161:110] node _T_1539 = bits(_T_1538, 0, 0) @[Bitwise.scala 72:15] node _T_1540 = mux(_T_1539, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1541 = and(_T_1540, intpriority_reg_inv[26]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[26] <= _T_1541 @[pic_ctrl.scala 160:64] - node _T_1542 = and(extintsrc_req_gw_27, intenable_reg[27]) @[pic_ctrl.scala 160:110] + node _T_1541 = and(_T_1540, intpriority_reg_inv[26]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[26] <= _T_1541 @[pic_ctrl.scala 161:64] + node _T_1542 = and(extintsrc_req_gw_27, intenable_reg[27]) @[pic_ctrl.scala 161:110] node _T_1543 = bits(_T_1542, 0, 0) @[Bitwise.scala 72:15] node _T_1544 = mux(_T_1543, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1545 = and(_T_1544, intpriority_reg_inv[27]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[27] <= _T_1545 @[pic_ctrl.scala 160:64] - node _T_1546 = and(extintsrc_req_gw_28, intenable_reg[28]) @[pic_ctrl.scala 160:110] + node _T_1545 = and(_T_1544, intpriority_reg_inv[27]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[27] <= _T_1545 @[pic_ctrl.scala 161:64] + node _T_1546 = and(extintsrc_req_gw_28, intenable_reg[28]) @[pic_ctrl.scala 161:110] node _T_1547 = bits(_T_1546, 0, 0) @[Bitwise.scala 72:15] node _T_1548 = mux(_T_1547, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1549 = and(_T_1548, intpriority_reg_inv[28]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[28] <= _T_1549 @[pic_ctrl.scala 160:64] - node _T_1550 = and(extintsrc_req_gw_29, intenable_reg[29]) @[pic_ctrl.scala 160:110] + node _T_1549 = and(_T_1548, intpriority_reg_inv[28]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[28] <= _T_1549 @[pic_ctrl.scala 161:64] + node _T_1550 = and(extintsrc_req_gw_29, intenable_reg[29]) @[pic_ctrl.scala 161:110] node _T_1551 = bits(_T_1550, 0, 0) @[Bitwise.scala 72:15] node _T_1552 = mux(_T_1551, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1553 = and(_T_1552, intpriority_reg_inv[29]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[29] <= _T_1553 @[pic_ctrl.scala 160:64] - node _T_1554 = and(extintsrc_req_gw_30, intenable_reg[30]) @[pic_ctrl.scala 160:110] + node _T_1553 = and(_T_1552, intpriority_reg_inv[29]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[29] <= _T_1553 @[pic_ctrl.scala 161:64] + node _T_1554 = and(extintsrc_req_gw_30, intenable_reg[30]) @[pic_ctrl.scala 161:110] node _T_1555 = bits(_T_1554, 0, 0) @[Bitwise.scala 72:15] node _T_1556 = mux(_T_1555, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1557 = and(_T_1556, intpriority_reg_inv[30]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[30] <= _T_1557 @[pic_ctrl.scala 160:64] - node _T_1558 = and(extintsrc_req_gw_31, intenable_reg[31]) @[pic_ctrl.scala 160:110] + node _T_1557 = and(_T_1556, intpriority_reg_inv[30]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[30] <= _T_1557 @[pic_ctrl.scala 161:64] + node _T_1558 = and(extintsrc_req_gw_31, intenable_reg[31]) @[pic_ctrl.scala 161:110] node _T_1559 = bits(_T_1558, 0, 0) @[Bitwise.scala 72:15] node _T_1560 = mux(_T_1559, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_1561 = and(_T_1560, intpriority_reg_inv[31]) @[pic_ctrl.scala 160:130] - intpend_w_prior_en[31] <= _T_1561 @[pic_ctrl.scala 160:64] - intpend_id[0] <= UInt<1>("h00") @[pic_ctrl.scala 161:56] - intpend_id[1] <= UInt<1>("h01") @[pic_ctrl.scala 161:56] - intpend_id[2] <= UInt<2>("h02") @[pic_ctrl.scala 161:56] - intpend_id[3] <= UInt<2>("h03") @[pic_ctrl.scala 161:56] - intpend_id[4] <= UInt<3>("h04") @[pic_ctrl.scala 161:56] - intpend_id[5] <= UInt<3>("h05") @[pic_ctrl.scala 161:56] - intpend_id[6] <= UInt<3>("h06") @[pic_ctrl.scala 161:56] - intpend_id[7] <= UInt<3>("h07") @[pic_ctrl.scala 161:56] - intpend_id[8] <= UInt<4>("h08") @[pic_ctrl.scala 161:56] - intpend_id[9] <= UInt<4>("h09") @[pic_ctrl.scala 161:56] - intpend_id[10] <= UInt<4>("h0a") @[pic_ctrl.scala 161:56] - intpend_id[11] <= UInt<4>("h0b") @[pic_ctrl.scala 161:56] - intpend_id[12] <= UInt<4>("h0c") @[pic_ctrl.scala 161:56] - intpend_id[13] <= UInt<4>("h0d") @[pic_ctrl.scala 161:56] - intpend_id[14] <= UInt<4>("h0e") @[pic_ctrl.scala 161:56] - intpend_id[15] <= UInt<4>("h0f") @[pic_ctrl.scala 161:56] - intpend_id[16] <= UInt<5>("h010") @[pic_ctrl.scala 161:56] - intpend_id[17] <= UInt<5>("h011") @[pic_ctrl.scala 161:56] - intpend_id[18] <= UInt<5>("h012") @[pic_ctrl.scala 161:56] - intpend_id[19] <= UInt<5>("h013") @[pic_ctrl.scala 161:56] - intpend_id[20] <= UInt<5>("h014") @[pic_ctrl.scala 161:56] - intpend_id[21] <= UInt<5>("h015") @[pic_ctrl.scala 161:56] - intpend_id[22] <= UInt<5>("h016") @[pic_ctrl.scala 161:56] - intpend_id[23] <= UInt<5>("h017") @[pic_ctrl.scala 161:56] - intpend_id[24] <= UInt<5>("h018") @[pic_ctrl.scala 161:56] - intpend_id[25] <= UInt<5>("h019") @[pic_ctrl.scala 161:56] - intpend_id[26] <= UInt<5>("h01a") @[pic_ctrl.scala 161:56] - intpend_id[27] <= UInt<5>("h01b") @[pic_ctrl.scala 161:56] - intpend_id[28] <= UInt<5>("h01c") @[pic_ctrl.scala 161:56] - intpend_id[29] <= UInt<5>("h01d") @[pic_ctrl.scala 161:56] - intpend_id[30] <= UInt<5>("h01e") @[pic_ctrl.scala 161:56] - intpend_id[31] <= UInt<5>("h01f") @[pic_ctrl.scala 161:56] - wire level_intpend_w_prior_en : UInt<4>[34][6] @[pic_ctrl.scala 212:40] - wire level_intpend_id : UInt<8>[34][6] @[pic_ctrl.scala 213:32] - level_intpend_w_prior_en[0][0] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][0] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][1] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][1] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][2] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][2] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][3] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][3] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][4] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][4] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][5] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][5] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][6] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][6] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][7] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][7] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][8] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][8] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][9] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][9] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][10] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][10] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][11] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][11] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][12] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][12] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][13] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][13] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][14] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][14] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][15] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][15] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][16] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][16] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][17] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][17] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][18] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][18] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][19] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][19] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][20] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][20] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][21] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][21] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][22] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][22] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][23] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][23] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][24] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][24] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][25] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][25] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][26] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][26] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][27] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][27] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][28] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][28] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][29] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][29] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][30] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][30] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][31] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][31] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][32] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][32] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[0][33] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[0][33] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][0] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][0] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][1] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][1] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][2] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][2] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][3] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][3] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][4] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][4] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][5] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][5] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][6] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][6] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][7] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][7] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][8] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][8] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][9] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][9] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][10] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][10] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][11] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][11] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][12] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][12] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][13] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][13] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][14] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][14] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][15] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][15] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][16] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][16] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][17] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][17] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][18] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][18] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][19] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][19] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][20] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][20] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][21] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][21] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][22] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][22] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][23] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][23] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][24] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][24] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][25] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][25] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][26] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][26] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][27] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][27] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][28] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][28] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][29] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][29] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][30] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][30] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][31] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][31] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][32] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][32] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[1][33] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[1][33] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][0] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][0] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][1] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][1] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][2] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][2] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][3] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][3] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][4] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][4] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][5] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][5] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][6] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][6] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][7] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][7] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][8] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][8] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][9] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][9] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][10] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][10] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][11] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][11] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][12] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][12] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][13] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][13] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][14] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][14] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][15] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][15] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][16] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][16] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][17] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][17] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][18] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][18] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][19] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][19] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][20] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][20] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][21] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][21] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][22] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][22] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][23] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][23] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][24] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][24] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][25] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][25] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][26] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][26] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][27] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][27] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][28] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][28] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][29] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][29] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][30] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][30] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][31] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][31] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][32] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][32] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[2][33] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[2][33] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][0] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][0] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][1] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][1] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][2] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][2] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][3] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][3] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][4] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][4] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][5] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][5] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][6] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][6] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][7] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][7] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][8] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][8] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][9] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][9] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][10] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][10] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][11] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][11] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][12] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][12] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][13] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][13] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][14] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][14] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][15] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][15] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][16] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][16] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][17] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][17] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][18] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][18] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][19] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][19] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][20] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][20] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][21] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][21] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][22] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][22] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][23] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][23] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][24] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][24] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][25] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][25] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][26] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][26] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][27] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][27] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][28] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][28] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][29] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][29] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][30] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][30] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][31] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][31] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][32] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][32] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[3][33] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[3][33] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][0] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][0] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][1] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][1] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][2] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][2] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][3] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][3] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][4] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][4] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][5] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][5] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][6] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][6] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][7] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][7] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][8] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][8] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][9] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][9] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][10] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][10] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][11] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][11] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][12] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][12] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][13] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][13] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][14] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][14] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][15] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][15] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][16] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][16] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][17] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][17] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][18] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][18] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][19] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][19] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][20] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][20] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][21] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][21] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][22] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][22] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][23] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][23] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][24] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][24] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][25] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][25] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][26] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][26] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][27] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][27] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][28] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][28] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][29] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][29] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][30] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][30] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][31] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][31] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][32] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][32] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[4][33] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[4][33] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][0] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][0] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][1] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][1] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][2] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][2] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][3] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][3] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][4] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][4] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][5] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][5] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][6] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][6] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][7] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][7] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][8] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][8] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][9] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][9] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][10] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][10] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][11] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][11] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][12] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][12] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][13] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][13] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][14] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][14] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][15] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][15] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][16] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][16] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][17] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][17] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][18] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][18] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][19] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][19] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][20] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][20] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][21] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][21] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][22] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][22] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][23] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][23] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][24] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][24] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][25] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][25] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][26] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][26] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][27] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][27] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][28] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][28] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][29] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][29] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][30] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][30] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][31] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][31] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][32] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][32] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] - level_intpend_w_prior_en[5][33] <= UInt<1>("h00") @[pic_ctrl.scala 216:38] - level_intpend_id[5][33] <= UInt<1>("h00") @[pic_ctrl.scala 217:30] + node _T_1561 = and(_T_1560, intpriority_reg_inv[31]) @[pic_ctrl.scala 161:130] + intpend_w_prior_en[31] <= _T_1561 @[pic_ctrl.scala 161:64] + intpend_id[0] <= UInt<1>("h00") @[pic_ctrl.scala 162:56] + intpend_id[1] <= UInt<1>("h01") @[pic_ctrl.scala 162:56] + intpend_id[2] <= UInt<2>("h02") @[pic_ctrl.scala 162:56] + intpend_id[3] <= UInt<2>("h03") @[pic_ctrl.scala 162:56] + intpend_id[4] <= UInt<3>("h04") @[pic_ctrl.scala 162:56] + intpend_id[5] <= UInt<3>("h05") @[pic_ctrl.scala 162:56] + intpend_id[6] <= UInt<3>("h06") @[pic_ctrl.scala 162:56] + intpend_id[7] <= UInt<3>("h07") @[pic_ctrl.scala 162:56] + intpend_id[8] <= UInt<4>("h08") @[pic_ctrl.scala 162:56] + intpend_id[9] <= UInt<4>("h09") @[pic_ctrl.scala 162:56] + intpend_id[10] <= UInt<4>("h0a") @[pic_ctrl.scala 162:56] + intpend_id[11] <= UInt<4>("h0b") @[pic_ctrl.scala 162:56] + intpend_id[12] <= UInt<4>("h0c") @[pic_ctrl.scala 162:56] + intpend_id[13] <= UInt<4>("h0d") @[pic_ctrl.scala 162:56] + intpend_id[14] <= UInt<4>("h0e") @[pic_ctrl.scala 162:56] + intpend_id[15] <= UInt<4>("h0f") @[pic_ctrl.scala 162:56] + intpend_id[16] <= UInt<5>("h010") @[pic_ctrl.scala 162:56] + intpend_id[17] <= UInt<5>("h011") @[pic_ctrl.scala 162:56] + intpend_id[18] <= UInt<5>("h012") @[pic_ctrl.scala 162:56] + intpend_id[19] <= UInt<5>("h013") @[pic_ctrl.scala 162:56] + intpend_id[20] <= UInt<5>("h014") @[pic_ctrl.scala 162:56] + intpend_id[21] <= UInt<5>("h015") @[pic_ctrl.scala 162:56] + intpend_id[22] <= UInt<5>("h016") @[pic_ctrl.scala 162:56] + intpend_id[23] <= UInt<5>("h017") @[pic_ctrl.scala 162:56] + intpend_id[24] <= UInt<5>("h018") @[pic_ctrl.scala 162:56] + intpend_id[25] <= UInt<5>("h019") @[pic_ctrl.scala 162:56] + intpend_id[26] <= UInt<5>("h01a") @[pic_ctrl.scala 162:56] + intpend_id[27] <= UInt<5>("h01b") @[pic_ctrl.scala 162:56] + intpend_id[28] <= UInt<5>("h01c") @[pic_ctrl.scala 162:56] + intpend_id[29] <= UInt<5>("h01d") @[pic_ctrl.scala 162:56] + intpend_id[30] <= UInt<5>("h01e") @[pic_ctrl.scala 162:56] + intpend_id[31] <= UInt<5>("h01f") @[pic_ctrl.scala 162:56] + wire level_intpend_w_prior_en : UInt<4>[34][6] @[pic_ctrl.scala 213:40] + wire level_intpend_id : UInt<8>[34][6] @[pic_ctrl.scala 214:32] + level_intpend_w_prior_en[0][0] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][0] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][1] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][1] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][2] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][2] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][3] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][3] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][4] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][4] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][5] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][5] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][6] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][6] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][7] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][7] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][8] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][8] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][9] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][9] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][10] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][10] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][11] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][11] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][12] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][12] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][13] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][13] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][14] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][14] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][15] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][15] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][16] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][16] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][17] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][17] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][18] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][18] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][19] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][19] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][20] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][20] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][21] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][21] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][22] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][22] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][23] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][23] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][24] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][24] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][25] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][25] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][26] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][26] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][27] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][27] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][28] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][28] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][29] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][29] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][30] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][30] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][31] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][31] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][32] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][32] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[0][33] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[0][33] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][0] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][0] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][1] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][1] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][2] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][2] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][3] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][3] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][4] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][4] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][5] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][5] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][6] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][6] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][7] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][7] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][8] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][8] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][9] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][9] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][10] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][10] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][11] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][11] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][12] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][12] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][13] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][13] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][14] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][14] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][15] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][15] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][16] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][16] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][17] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][17] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][18] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][18] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][19] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][19] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][20] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][20] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][21] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][21] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][22] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][22] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][23] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][23] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][24] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][24] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][25] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][25] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][26] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][26] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][27] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][27] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][28] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][28] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][29] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][29] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][30] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][30] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][31] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][31] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][32] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][32] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[1][33] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[1][33] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][0] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][0] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][1] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][1] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][2] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][2] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][3] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][3] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][4] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][4] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][5] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][5] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][6] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][6] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][7] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][7] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][8] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][8] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][9] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][9] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][10] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][10] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][11] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][11] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][12] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][12] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][13] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][13] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][14] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][14] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][15] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][15] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][16] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][16] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][17] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][17] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][18] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][18] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][19] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][19] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][20] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][20] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][21] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][21] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][22] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][22] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][23] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][23] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][24] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][24] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][25] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][25] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][26] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][26] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][27] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][27] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][28] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][28] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][29] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][29] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][30] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][30] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][31] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][31] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][32] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][32] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[2][33] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[2][33] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][0] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][0] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][1] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][1] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][2] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][2] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][3] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][3] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][4] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][4] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][5] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][5] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][6] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][6] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][7] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][7] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][8] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][8] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][9] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][9] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][10] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][10] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][11] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][11] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][12] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][12] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][13] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][13] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][14] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][14] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][15] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][15] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][16] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][16] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][17] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][17] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][18] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][18] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][19] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][19] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][20] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][20] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][21] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][21] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][22] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][22] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][23] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][23] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][24] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][24] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][25] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][25] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][26] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][26] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][27] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][27] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][28] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][28] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][29] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][29] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][30] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][30] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][31] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][31] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][32] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][32] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[3][33] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[3][33] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][0] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][0] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][1] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][1] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][2] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][2] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][3] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][3] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][4] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][4] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][5] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][5] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][6] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][6] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][7] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][7] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][8] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][8] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][9] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][9] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][10] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][10] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][11] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][11] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][12] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][12] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][13] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][13] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][14] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][14] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][15] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][15] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][16] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][16] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][17] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][17] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][18] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][18] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][19] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][19] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][20] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][20] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][21] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][21] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][22] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][22] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][23] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][23] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][24] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][24] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][25] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][25] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][26] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][26] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][27] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][27] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][28] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][28] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][29] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][29] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][30] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][30] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][31] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][31] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][32] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][32] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[4][33] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[4][33] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][0] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][0] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][1] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][1] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][2] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][2] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][3] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][3] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][4] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][4] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][5] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][5] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][6] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][6] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][7] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][7] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][8] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][8] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][9] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][9] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][10] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][10] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][11] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][11] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][12] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][12] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][13] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][13] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][14] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][14] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][15] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][15] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][16] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][16] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][17] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][17] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][18] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][18] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][19] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][19] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][20] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][20] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][21] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][21] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][22] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][22] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][23] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][23] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][24] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][24] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][25] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][25] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][26] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][26] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][27] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][27] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][28] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][28] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][29] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][29] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][30] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][30] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][31] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][31] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][32] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][32] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] + level_intpend_w_prior_en[5][33] <= UInt<1>("h00") @[pic_ctrl.scala 217:38] + level_intpend_id[5][33] <= UInt<1>("h00") @[pic_ctrl.scala 218:30] node _T_1562 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] node _T_1563 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - level_intpend_w_prior_en[0][0] <= intpend_w_prior_en[0] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][1] <= intpend_w_prior_en[1] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][2] <= intpend_w_prior_en[2] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][3] <= intpend_w_prior_en[3] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][4] <= intpend_w_prior_en[4] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][5] <= intpend_w_prior_en[5] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][6] <= intpend_w_prior_en[6] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][7] <= intpend_w_prior_en[7] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][8] <= intpend_w_prior_en[8] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][9] <= intpend_w_prior_en[9] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][10] <= intpend_w_prior_en[10] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][11] <= intpend_w_prior_en[11] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][12] <= intpend_w_prior_en[12] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][13] <= intpend_w_prior_en[13] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][14] <= intpend_w_prior_en[14] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][15] <= intpend_w_prior_en[15] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][16] <= intpend_w_prior_en[16] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][17] <= intpend_w_prior_en[17] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][18] <= intpend_w_prior_en[18] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][19] <= intpend_w_prior_en[19] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][20] <= intpend_w_prior_en[20] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][21] <= intpend_w_prior_en[21] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][22] <= intpend_w_prior_en[22] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][23] <= intpend_w_prior_en[23] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][24] <= intpend_w_prior_en[24] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][25] <= intpend_w_prior_en[25] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][26] <= intpend_w_prior_en[26] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][27] <= intpend_w_prior_en[27] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][28] <= intpend_w_prior_en[28] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][29] <= intpend_w_prior_en[29] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][30] <= intpend_w_prior_en[30] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][31] <= intpend_w_prior_en[31] @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][32] <= _T_1562 @[pic_ctrl.scala 219:33] - level_intpend_w_prior_en[0][33] <= _T_1563 @[pic_ctrl.scala 219:33] + level_intpend_w_prior_en[0][0] <= intpend_w_prior_en[0] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][1] <= intpend_w_prior_en[1] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][2] <= intpend_w_prior_en[2] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][3] <= intpend_w_prior_en[3] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][4] <= intpend_w_prior_en[4] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][5] <= intpend_w_prior_en[5] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][6] <= intpend_w_prior_en[6] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][7] <= intpend_w_prior_en[7] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][8] <= intpend_w_prior_en[8] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][9] <= intpend_w_prior_en[9] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][10] <= intpend_w_prior_en[10] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][11] <= intpend_w_prior_en[11] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][12] <= intpend_w_prior_en[12] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][13] <= intpend_w_prior_en[13] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][14] <= intpend_w_prior_en[14] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][15] <= intpend_w_prior_en[15] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][16] <= intpend_w_prior_en[16] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][17] <= intpend_w_prior_en[17] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][18] <= intpend_w_prior_en[18] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][19] <= intpend_w_prior_en[19] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][20] <= intpend_w_prior_en[20] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][21] <= intpend_w_prior_en[21] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][22] <= intpend_w_prior_en[22] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][23] <= intpend_w_prior_en[23] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][24] <= intpend_w_prior_en[24] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][25] <= intpend_w_prior_en[25] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][26] <= intpend_w_prior_en[26] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][27] <= intpend_w_prior_en[27] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][28] <= intpend_w_prior_en[28] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][29] <= intpend_w_prior_en[29] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][30] <= intpend_w_prior_en[30] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][31] <= intpend_w_prior_en[31] @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][32] <= _T_1562 @[pic_ctrl.scala 220:33] + level_intpend_w_prior_en[0][33] <= _T_1563 @[pic_ctrl.scala 220:33] node _T_1564 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] node _T_1565 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - level_intpend_id[0][0] <= intpend_id[0] @[pic_ctrl.scala 220:33] - level_intpend_id[0][1] <= intpend_id[1] @[pic_ctrl.scala 220:33] - level_intpend_id[0][2] <= intpend_id[2] @[pic_ctrl.scala 220:33] - level_intpend_id[0][3] <= intpend_id[3] @[pic_ctrl.scala 220:33] - level_intpend_id[0][4] <= intpend_id[4] @[pic_ctrl.scala 220:33] - level_intpend_id[0][5] <= intpend_id[5] @[pic_ctrl.scala 220:33] - level_intpend_id[0][6] <= intpend_id[6] @[pic_ctrl.scala 220:33] - level_intpend_id[0][7] <= intpend_id[7] @[pic_ctrl.scala 220:33] - level_intpend_id[0][8] <= intpend_id[8] @[pic_ctrl.scala 220:33] - level_intpend_id[0][9] <= intpend_id[9] @[pic_ctrl.scala 220:33] - level_intpend_id[0][10] <= intpend_id[10] @[pic_ctrl.scala 220:33] - level_intpend_id[0][11] <= intpend_id[11] @[pic_ctrl.scala 220:33] - level_intpend_id[0][12] <= intpend_id[12] @[pic_ctrl.scala 220:33] - level_intpend_id[0][13] <= intpend_id[13] @[pic_ctrl.scala 220:33] - level_intpend_id[0][14] <= intpend_id[14] @[pic_ctrl.scala 220:33] - level_intpend_id[0][15] <= intpend_id[15] @[pic_ctrl.scala 220:33] - level_intpend_id[0][16] <= intpend_id[16] @[pic_ctrl.scala 220:33] - level_intpend_id[0][17] <= intpend_id[17] @[pic_ctrl.scala 220:33] - level_intpend_id[0][18] <= intpend_id[18] @[pic_ctrl.scala 220:33] - level_intpend_id[0][19] <= intpend_id[19] @[pic_ctrl.scala 220:33] - level_intpend_id[0][20] <= intpend_id[20] @[pic_ctrl.scala 220:33] - level_intpend_id[0][21] <= intpend_id[21] @[pic_ctrl.scala 220:33] - level_intpend_id[0][22] <= intpend_id[22] @[pic_ctrl.scala 220:33] - level_intpend_id[0][23] <= intpend_id[23] @[pic_ctrl.scala 220:33] - level_intpend_id[0][24] <= intpend_id[24] @[pic_ctrl.scala 220:33] - level_intpend_id[0][25] <= intpend_id[25] @[pic_ctrl.scala 220:33] - level_intpend_id[0][26] <= intpend_id[26] @[pic_ctrl.scala 220:33] - level_intpend_id[0][27] <= intpend_id[27] @[pic_ctrl.scala 220:33] - level_intpend_id[0][28] <= intpend_id[28] @[pic_ctrl.scala 220:33] - level_intpend_id[0][29] <= intpend_id[29] @[pic_ctrl.scala 220:33] - level_intpend_id[0][30] <= intpend_id[30] @[pic_ctrl.scala 220:33] - level_intpend_id[0][31] <= intpend_id[31] @[pic_ctrl.scala 220:33] - level_intpend_id[0][32] <= _T_1564 @[pic_ctrl.scala 220:33] - level_intpend_id[0][33] <= _T_1565 @[pic_ctrl.scala 220:33] - node _T_1566 = lt(level_intpend_w_prior_en[0][0], level_intpend_w_prior_en[0][1]) @[pic_ctrl.scala 26:20] - node out_id = mux(_T_1566, level_intpend_id[0][1], level_intpend_id[0][0]) @[pic_ctrl.scala 26:9] - node _T_1567 = lt(level_intpend_w_prior_en[0][0], level_intpend_w_prior_en[0][1]) @[pic_ctrl.scala 26:60] - node out_priority = mux(_T_1567, level_intpend_w_prior_en[0][1], level_intpend_w_prior_en[0][0]) @[pic_ctrl.scala 26:49] - level_intpend_id[1][0] <= out_id @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[1][0] <= out_priority @[pic_ctrl.scala 232:41] - node _T_1568 = lt(level_intpend_w_prior_en[0][2], level_intpend_w_prior_en[0][3]) @[pic_ctrl.scala 26:20] - node out_id_1 = mux(_T_1568, level_intpend_id[0][3], level_intpend_id[0][2]) @[pic_ctrl.scala 26:9] - node _T_1569 = lt(level_intpend_w_prior_en[0][2], level_intpend_w_prior_en[0][3]) @[pic_ctrl.scala 26:60] - node out_priority_1 = mux(_T_1569, level_intpend_w_prior_en[0][3], level_intpend_w_prior_en[0][2]) @[pic_ctrl.scala 26:49] - level_intpend_id[1][1] <= out_id_1 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[1][1] <= out_priority_1 @[pic_ctrl.scala 232:41] - node _T_1570 = lt(level_intpend_w_prior_en[0][4], level_intpend_w_prior_en[0][5]) @[pic_ctrl.scala 26:20] - node out_id_2 = mux(_T_1570, level_intpend_id[0][5], level_intpend_id[0][4]) @[pic_ctrl.scala 26:9] - node _T_1571 = lt(level_intpend_w_prior_en[0][4], level_intpend_w_prior_en[0][5]) @[pic_ctrl.scala 26:60] - node out_priority_2 = mux(_T_1571, level_intpend_w_prior_en[0][5], level_intpend_w_prior_en[0][4]) @[pic_ctrl.scala 26:49] - level_intpend_id[1][2] <= out_id_2 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[1][2] <= out_priority_2 @[pic_ctrl.scala 232:41] - node _T_1572 = lt(level_intpend_w_prior_en[0][6], level_intpend_w_prior_en[0][7]) @[pic_ctrl.scala 26:20] - node out_id_3 = mux(_T_1572, level_intpend_id[0][7], level_intpend_id[0][6]) @[pic_ctrl.scala 26:9] - node _T_1573 = lt(level_intpend_w_prior_en[0][6], level_intpend_w_prior_en[0][7]) @[pic_ctrl.scala 26:60] - node out_priority_3 = mux(_T_1573, level_intpend_w_prior_en[0][7], level_intpend_w_prior_en[0][6]) @[pic_ctrl.scala 26:49] - level_intpend_id[1][3] <= out_id_3 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[1][3] <= out_priority_3 @[pic_ctrl.scala 232:41] - node _T_1574 = lt(level_intpend_w_prior_en[0][8], level_intpend_w_prior_en[0][9]) @[pic_ctrl.scala 26:20] - node out_id_4 = mux(_T_1574, level_intpend_id[0][9], level_intpend_id[0][8]) @[pic_ctrl.scala 26:9] - node _T_1575 = lt(level_intpend_w_prior_en[0][8], level_intpend_w_prior_en[0][9]) @[pic_ctrl.scala 26:60] - node out_priority_4 = mux(_T_1575, level_intpend_w_prior_en[0][9], level_intpend_w_prior_en[0][8]) @[pic_ctrl.scala 26:49] - level_intpend_id[1][4] <= out_id_4 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[1][4] <= out_priority_4 @[pic_ctrl.scala 232:41] - node _T_1576 = lt(level_intpend_w_prior_en[0][10], level_intpend_w_prior_en[0][11]) @[pic_ctrl.scala 26:20] - node out_id_5 = mux(_T_1576, level_intpend_id[0][11], level_intpend_id[0][10]) @[pic_ctrl.scala 26:9] - node _T_1577 = lt(level_intpend_w_prior_en[0][10], level_intpend_w_prior_en[0][11]) @[pic_ctrl.scala 26:60] - node out_priority_5 = mux(_T_1577, level_intpend_w_prior_en[0][11], level_intpend_w_prior_en[0][10]) @[pic_ctrl.scala 26:49] - level_intpend_id[1][5] <= out_id_5 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[1][5] <= out_priority_5 @[pic_ctrl.scala 232:41] - node _T_1578 = lt(level_intpend_w_prior_en[0][12], level_intpend_w_prior_en[0][13]) @[pic_ctrl.scala 26:20] - node out_id_6 = mux(_T_1578, level_intpend_id[0][13], level_intpend_id[0][12]) @[pic_ctrl.scala 26:9] - node _T_1579 = lt(level_intpend_w_prior_en[0][12], level_intpend_w_prior_en[0][13]) @[pic_ctrl.scala 26:60] - node out_priority_6 = mux(_T_1579, level_intpend_w_prior_en[0][13], level_intpend_w_prior_en[0][12]) @[pic_ctrl.scala 26:49] - level_intpend_id[1][6] <= out_id_6 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[1][6] <= out_priority_6 @[pic_ctrl.scala 232:41] - node _T_1580 = lt(level_intpend_w_prior_en[0][14], level_intpend_w_prior_en[0][15]) @[pic_ctrl.scala 26:20] - node out_id_7 = mux(_T_1580, level_intpend_id[0][15], level_intpend_id[0][14]) @[pic_ctrl.scala 26:9] - node _T_1581 = lt(level_intpend_w_prior_en[0][14], level_intpend_w_prior_en[0][15]) @[pic_ctrl.scala 26:60] - node out_priority_7 = mux(_T_1581, level_intpend_w_prior_en[0][15], level_intpend_w_prior_en[0][14]) @[pic_ctrl.scala 26:49] - level_intpend_id[1][7] <= out_id_7 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[1][7] <= out_priority_7 @[pic_ctrl.scala 232:41] - node _T_1582 = lt(level_intpend_w_prior_en[0][16], level_intpend_w_prior_en[0][17]) @[pic_ctrl.scala 26:20] - node out_id_8 = mux(_T_1582, level_intpend_id[0][17], level_intpend_id[0][16]) @[pic_ctrl.scala 26:9] - node _T_1583 = lt(level_intpend_w_prior_en[0][16], level_intpend_w_prior_en[0][17]) @[pic_ctrl.scala 26:60] - node out_priority_8 = mux(_T_1583, level_intpend_w_prior_en[0][17], level_intpend_w_prior_en[0][16]) @[pic_ctrl.scala 26:49] - level_intpend_id[1][8] <= out_id_8 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[1][8] <= out_priority_8 @[pic_ctrl.scala 232:41] - node _T_1584 = lt(level_intpend_w_prior_en[0][18], level_intpend_w_prior_en[0][19]) @[pic_ctrl.scala 26:20] - node out_id_9 = mux(_T_1584, level_intpend_id[0][19], level_intpend_id[0][18]) @[pic_ctrl.scala 26:9] - node _T_1585 = lt(level_intpend_w_prior_en[0][18], level_intpend_w_prior_en[0][19]) @[pic_ctrl.scala 26:60] - node out_priority_9 = mux(_T_1585, level_intpend_w_prior_en[0][19], level_intpend_w_prior_en[0][18]) @[pic_ctrl.scala 26:49] - level_intpend_id[1][9] <= out_id_9 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[1][9] <= out_priority_9 @[pic_ctrl.scala 232:41] - node _T_1586 = lt(level_intpend_w_prior_en[0][20], level_intpend_w_prior_en[0][21]) @[pic_ctrl.scala 26:20] - node out_id_10 = mux(_T_1586, level_intpend_id[0][21], level_intpend_id[0][20]) @[pic_ctrl.scala 26:9] - node _T_1587 = lt(level_intpend_w_prior_en[0][20], level_intpend_w_prior_en[0][21]) @[pic_ctrl.scala 26:60] - node out_priority_10 = mux(_T_1587, level_intpend_w_prior_en[0][21], level_intpend_w_prior_en[0][20]) @[pic_ctrl.scala 26:49] - level_intpend_id[1][10] <= out_id_10 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[1][10] <= out_priority_10 @[pic_ctrl.scala 232:41] - node _T_1588 = lt(level_intpend_w_prior_en[0][22], level_intpend_w_prior_en[0][23]) @[pic_ctrl.scala 26:20] - node out_id_11 = mux(_T_1588, level_intpend_id[0][23], level_intpend_id[0][22]) @[pic_ctrl.scala 26:9] - node _T_1589 = lt(level_intpend_w_prior_en[0][22], level_intpend_w_prior_en[0][23]) @[pic_ctrl.scala 26:60] - node out_priority_11 = mux(_T_1589, level_intpend_w_prior_en[0][23], level_intpend_w_prior_en[0][22]) @[pic_ctrl.scala 26:49] - level_intpend_id[1][11] <= out_id_11 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[1][11] <= out_priority_11 @[pic_ctrl.scala 232:41] - node _T_1590 = lt(level_intpend_w_prior_en[0][24], level_intpend_w_prior_en[0][25]) @[pic_ctrl.scala 26:20] - node out_id_12 = mux(_T_1590, level_intpend_id[0][25], level_intpend_id[0][24]) @[pic_ctrl.scala 26:9] - node _T_1591 = lt(level_intpend_w_prior_en[0][24], level_intpend_w_prior_en[0][25]) @[pic_ctrl.scala 26:60] - node out_priority_12 = mux(_T_1591, level_intpend_w_prior_en[0][25], level_intpend_w_prior_en[0][24]) @[pic_ctrl.scala 26:49] - level_intpend_id[1][12] <= out_id_12 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[1][12] <= out_priority_12 @[pic_ctrl.scala 232:41] - node _T_1592 = lt(level_intpend_w_prior_en[0][26], level_intpend_w_prior_en[0][27]) @[pic_ctrl.scala 26:20] - node out_id_13 = mux(_T_1592, level_intpend_id[0][27], level_intpend_id[0][26]) @[pic_ctrl.scala 26:9] - node _T_1593 = lt(level_intpend_w_prior_en[0][26], level_intpend_w_prior_en[0][27]) @[pic_ctrl.scala 26:60] - node out_priority_13 = mux(_T_1593, level_intpend_w_prior_en[0][27], level_intpend_w_prior_en[0][26]) @[pic_ctrl.scala 26:49] - level_intpend_id[1][13] <= out_id_13 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[1][13] <= out_priority_13 @[pic_ctrl.scala 232:41] - node _T_1594 = lt(level_intpend_w_prior_en[0][28], level_intpend_w_prior_en[0][29]) @[pic_ctrl.scala 26:20] - node out_id_14 = mux(_T_1594, level_intpend_id[0][29], level_intpend_id[0][28]) @[pic_ctrl.scala 26:9] - node _T_1595 = lt(level_intpend_w_prior_en[0][28], level_intpend_w_prior_en[0][29]) @[pic_ctrl.scala 26:60] - node out_priority_14 = mux(_T_1595, level_intpend_w_prior_en[0][29], level_intpend_w_prior_en[0][28]) @[pic_ctrl.scala 26:49] - level_intpend_id[1][14] <= out_id_14 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[1][14] <= out_priority_14 @[pic_ctrl.scala 232:41] - node _T_1596 = lt(level_intpend_w_prior_en[0][30], level_intpend_w_prior_en[0][31]) @[pic_ctrl.scala 26:20] - node out_id_15 = mux(_T_1596, level_intpend_id[0][31], level_intpend_id[0][30]) @[pic_ctrl.scala 26:9] - node _T_1597 = lt(level_intpend_w_prior_en[0][30], level_intpend_w_prior_en[0][31]) @[pic_ctrl.scala 26:60] - node out_priority_15 = mux(_T_1597, level_intpend_w_prior_en[0][31], level_intpend_w_prior_en[0][30]) @[pic_ctrl.scala 26:49] - level_intpend_id[1][15] <= out_id_15 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[1][15] <= out_priority_15 @[pic_ctrl.scala 232:41] - level_intpend_w_prior_en[1][17] <= UInt<1>("h00") @[pic_ctrl.scala 227:44] - level_intpend_id[1][17] <= UInt<1>("h00") @[pic_ctrl.scala 228:44] - node _T_1598 = lt(level_intpend_w_prior_en[0][32], level_intpend_w_prior_en[0][33]) @[pic_ctrl.scala 26:20] - node out_id_16 = mux(_T_1598, level_intpend_id[0][33], level_intpend_id[0][32]) @[pic_ctrl.scala 26:9] - node _T_1599 = lt(level_intpend_w_prior_en[0][32], level_intpend_w_prior_en[0][33]) @[pic_ctrl.scala 26:60] - node out_priority_16 = mux(_T_1599, level_intpend_w_prior_en[0][33], level_intpend_w_prior_en[0][32]) @[pic_ctrl.scala 26:49] - level_intpend_id[1][16] <= out_id_16 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[1][16] <= out_priority_16 @[pic_ctrl.scala 232:41] - node _T_1600 = lt(level_intpend_w_prior_en[1][0], level_intpend_w_prior_en[1][1]) @[pic_ctrl.scala 26:20] - node out_id_17 = mux(_T_1600, level_intpend_id[1][1], level_intpend_id[1][0]) @[pic_ctrl.scala 26:9] - node _T_1601 = lt(level_intpend_w_prior_en[1][0], level_intpend_w_prior_en[1][1]) @[pic_ctrl.scala 26:60] - node out_priority_17 = mux(_T_1601, level_intpend_w_prior_en[1][1], level_intpend_w_prior_en[1][0]) @[pic_ctrl.scala 26:49] - level_intpend_id[2][0] <= out_id_17 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[2][0] <= out_priority_17 @[pic_ctrl.scala 232:41] - node _T_1602 = lt(level_intpend_w_prior_en[1][2], level_intpend_w_prior_en[1][3]) @[pic_ctrl.scala 26:20] - node out_id_18 = mux(_T_1602, level_intpend_id[1][3], level_intpend_id[1][2]) @[pic_ctrl.scala 26:9] - node _T_1603 = lt(level_intpend_w_prior_en[1][2], level_intpend_w_prior_en[1][3]) @[pic_ctrl.scala 26:60] - node out_priority_18 = mux(_T_1603, level_intpend_w_prior_en[1][3], level_intpend_w_prior_en[1][2]) @[pic_ctrl.scala 26:49] - level_intpend_id[2][1] <= out_id_18 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[2][1] <= out_priority_18 @[pic_ctrl.scala 232:41] - node _T_1604 = lt(level_intpend_w_prior_en[1][4], level_intpend_w_prior_en[1][5]) @[pic_ctrl.scala 26:20] - node out_id_19 = mux(_T_1604, level_intpend_id[1][5], level_intpend_id[1][4]) @[pic_ctrl.scala 26:9] - node _T_1605 = lt(level_intpend_w_prior_en[1][4], level_intpend_w_prior_en[1][5]) @[pic_ctrl.scala 26:60] - node out_priority_19 = mux(_T_1605, level_intpend_w_prior_en[1][5], level_intpend_w_prior_en[1][4]) @[pic_ctrl.scala 26:49] - level_intpend_id[2][2] <= out_id_19 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[2][2] <= out_priority_19 @[pic_ctrl.scala 232:41] - node _T_1606 = lt(level_intpend_w_prior_en[1][6], level_intpend_w_prior_en[1][7]) @[pic_ctrl.scala 26:20] - node out_id_20 = mux(_T_1606, level_intpend_id[1][7], level_intpend_id[1][6]) @[pic_ctrl.scala 26:9] - node _T_1607 = lt(level_intpend_w_prior_en[1][6], level_intpend_w_prior_en[1][7]) @[pic_ctrl.scala 26:60] - node out_priority_20 = mux(_T_1607, level_intpend_w_prior_en[1][7], level_intpend_w_prior_en[1][6]) @[pic_ctrl.scala 26:49] - level_intpend_id[2][3] <= out_id_20 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[2][3] <= out_priority_20 @[pic_ctrl.scala 232:41] - node _T_1608 = lt(level_intpend_w_prior_en[1][8], level_intpend_w_prior_en[1][9]) @[pic_ctrl.scala 26:20] - node out_id_21 = mux(_T_1608, level_intpend_id[1][9], level_intpend_id[1][8]) @[pic_ctrl.scala 26:9] - node _T_1609 = lt(level_intpend_w_prior_en[1][8], level_intpend_w_prior_en[1][9]) @[pic_ctrl.scala 26:60] - node out_priority_21 = mux(_T_1609, level_intpend_w_prior_en[1][9], level_intpend_w_prior_en[1][8]) @[pic_ctrl.scala 26:49] - level_intpend_id[2][4] <= out_id_21 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[2][4] <= out_priority_21 @[pic_ctrl.scala 232:41] - node _T_1610 = lt(level_intpend_w_prior_en[1][10], level_intpend_w_prior_en[1][11]) @[pic_ctrl.scala 26:20] - node out_id_22 = mux(_T_1610, level_intpend_id[1][11], level_intpend_id[1][10]) @[pic_ctrl.scala 26:9] - node _T_1611 = lt(level_intpend_w_prior_en[1][10], level_intpend_w_prior_en[1][11]) @[pic_ctrl.scala 26:60] - node out_priority_22 = mux(_T_1611, level_intpend_w_prior_en[1][11], level_intpend_w_prior_en[1][10]) @[pic_ctrl.scala 26:49] - level_intpend_id[2][5] <= out_id_22 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[2][5] <= out_priority_22 @[pic_ctrl.scala 232:41] - node _T_1612 = lt(level_intpend_w_prior_en[1][12], level_intpend_w_prior_en[1][13]) @[pic_ctrl.scala 26:20] - node out_id_23 = mux(_T_1612, level_intpend_id[1][13], level_intpend_id[1][12]) @[pic_ctrl.scala 26:9] - node _T_1613 = lt(level_intpend_w_prior_en[1][12], level_intpend_w_prior_en[1][13]) @[pic_ctrl.scala 26:60] - node out_priority_23 = mux(_T_1613, level_intpend_w_prior_en[1][13], level_intpend_w_prior_en[1][12]) @[pic_ctrl.scala 26:49] - level_intpend_id[2][6] <= out_id_23 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[2][6] <= out_priority_23 @[pic_ctrl.scala 232:41] - node _T_1614 = lt(level_intpend_w_prior_en[1][14], level_intpend_w_prior_en[1][15]) @[pic_ctrl.scala 26:20] - node out_id_24 = mux(_T_1614, level_intpend_id[1][15], level_intpend_id[1][14]) @[pic_ctrl.scala 26:9] - node _T_1615 = lt(level_intpend_w_prior_en[1][14], level_intpend_w_prior_en[1][15]) @[pic_ctrl.scala 26:60] - node out_priority_24 = mux(_T_1615, level_intpend_w_prior_en[1][15], level_intpend_w_prior_en[1][14]) @[pic_ctrl.scala 26:49] - level_intpend_id[2][7] <= out_id_24 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[2][7] <= out_priority_24 @[pic_ctrl.scala 232:41] - level_intpend_w_prior_en[2][9] <= UInt<1>("h00") @[pic_ctrl.scala 227:44] - level_intpend_id[2][9] <= UInt<1>("h00") @[pic_ctrl.scala 228:44] - node _T_1616 = lt(level_intpend_w_prior_en[1][16], level_intpend_w_prior_en[1][17]) @[pic_ctrl.scala 26:20] - node out_id_25 = mux(_T_1616, level_intpend_id[1][17], level_intpend_id[1][16]) @[pic_ctrl.scala 26:9] - node _T_1617 = lt(level_intpend_w_prior_en[1][16], level_intpend_w_prior_en[1][17]) @[pic_ctrl.scala 26:60] - node out_priority_25 = mux(_T_1617, level_intpend_w_prior_en[1][17], level_intpend_w_prior_en[1][16]) @[pic_ctrl.scala 26:49] - level_intpend_id[2][8] <= out_id_25 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[2][8] <= out_priority_25 @[pic_ctrl.scala 232:41] - node _T_1618 = lt(level_intpend_w_prior_en[2][0], level_intpend_w_prior_en[2][1]) @[pic_ctrl.scala 26:20] - node out_id_26 = mux(_T_1618, level_intpend_id[2][1], level_intpend_id[2][0]) @[pic_ctrl.scala 26:9] - node _T_1619 = lt(level_intpend_w_prior_en[2][0], level_intpend_w_prior_en[2][1]) @[pic_ctrl.scala 26:60] - node out_priority_26 = mux(_T_1619, level_intpend_w_prior_en[2][1], level_intpend_w_prior_en[2][0]) @[pic_ctrl.scala 26:49] - level_intpend_id[3][0] <= out_id_26 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[3][0] <= out_priority_26 @[pic_ctrl.scala 232:41] - node _T_1620 = lt(level_intpend_w_prior_en[2][2], level_intpend_w_prior_en[2][3]) @[pic_ctrl.scala 26:20] - node out_id_27 = mux(_T_1620, level_intpend_id[2][3], level_intpend_id[2][2]) @[pic_ctrl.scala 26:9] - node _T_1621 = lt(level_intpend_w_prior_en[2][2], level_intpend_w_prior_en[2][3]) @[pic_ctrl.scala 26:60] - node out_priority_27 = mux(_T_1621, level_intpend_w_prior_en[2][3], level_intpend_w_prior_en[2][2]) @[pic_ctrl.scala 26:49] - level_intpend_id[3][1] <= out_id_27 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[3][1] <= out_priority_27 @[pic_ctrl.scala 232:41] - node _T_1622 = lt(level_intpend_w_prior_en[2][4], level_intpend_w_prior_en[2][5]) @[pic_ctrl.scala 26:20] - node out_id_28 = mux(_T_1622, level_intpend_id[2][5], level_intpend_id[2][4]) @[pic_ctrl.scala 26:9] - node _T_1623 = lt(level_intpend_w_prior_en[2][4], level_intpend_w_prior_en[2][5]) @[pic_ctrl.scala 26:60] - node out_priority_28 = mux(_T_1623, level_intpend_w_prior_en[2][5], level_intpend_w_prior_en[2][4]) @[pic_ctrl.scala 26:49] - level_intpend_id[3][2] <= out_id_28 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[3][2] <= out_priority_28 @[pic_ctrl.scala 232:41] - node _T_1624 = lt(level_intpend_w_prior_en[2][6], level_intpend_w_prior_en[2][7]) @[pic_ctrl.scala 26:20] - node out_id_29 = mux(_T_1624, level_intpend_id[2][7], level_intpend_id[2][6]) @[pic_ctrl.scala 26:9] - node _T_1625 = lt(level_intpend_w_prior_en[2][6], level_intpend_w_prior_en[2][7]) @[pic_ctrl.scala 26:60] - node out_priority_29 = mux(_T_1625, level_intpend_w_prior_en[2][7], level_intpend_w_prior_en[2][6]) @[pic_ctrl.scala 26:49] - level_intpend_id[3][3] <= out_id_29 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[3][3] <= out_priority_29 @[pic_ctrl.scala 232:41] - level_intpend_w_prior_en[3][5] <= UInt<1>("h00") @[pic_ctrl.scala 227:44] - level_intpend_id[3][5] <= UInt<1>("h00") @[pic_ctrl.scala 228:44] - node _T_1626 = lt(level_intpend_w_prior_en[2][8], level_intpend_w_prior_en[2][9]) @[pic_ctrl.scala 26:20] - node out_id_30 = mux(_T_1626, level_intpend_id[2][9], level_intpend_id[2][8]) @[pic_ctrl.scala 26:9] - node _T_1627 = lt(level_intpend_w_prior_en[2][8], level_intpend_w_prior_en[2][9]) @[pic_ctrl.scala 26:60] - node out_priority_30 = mux(_T_1627, level_intpend_w_prior_en[2][9], level_intpend_w_prior_en[2][8]) @[pic_ctrl.scala 26:49] - level_intpend_id[3][4] <= out_id_30 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[3][4] <= out_priority_30 @[pic_ctrl.scala 232:41] - node _T_1628 = lt(level_intpend_w_prior_en[3][0], level_intpend_w_prior_en[3][1]) @[pic_ctrl.scala 26:20] - node out_id_31 = mux(_T_1628, level_intpend_id[3][1], level_intpend_id[3][0]) @[pic_ctrl.scala 26:9] - node _T_1629 = lt(level_intpend_w_prior_en[3][0], level_intpend_w_prior_en[3][1]) @[pic_ctrl.scala 26:60] - node out_priority_31 = mux(_T_1629, level_intpend_w_prior_en[3][1], level_intpend_w_prior_en[3][0]) @[pic_ctrl.scala 26:49] - level_intpend_id[4][0] <= out_id_31 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[4][0] <= out_priority_31 @[pic_ctrl.scala 232:41] - node _T_1630 = lt(level_intpend_w_prior_en[3][2], level_intpend_w_prior_en[3][3]) @[pic_ctrl.scala 26:20] - node out_id_32 = mux(_T_1630, level_intpend_id[3][3], level_intpend_id[3][2]) @[pic_ctrl.scala 26:9] - node _T_1631 = lt(level_intpend_w_prior_en[3][2], level_intpend_w_prior_en[3][3]) @[pic_ctrl.scala 26:60] - node out_priority_32 = mux(_T_1631, level_intpend_w_prior_en[3][3], level_intpend_w_prior_en[3][2]) @[pic_ctrl.scala 26:49] - level_intpend_id[4][1] <= out_id_32 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[4][1] <= out_priority_32 @[pic_ctrl.scala 232:41] - level_intpend_w_prior_en[4][3] <= UInt<1>("h00") @[pic_ctrl.scala 227:44] - level_intpend_id[4][3] <= UInt<1>("h00") @[pic_ctrl.scala 228:44] - node _T_1632 = lt(level_intpend_w_prior_en[3][4], level_intpend_w_prior_en[3][5]) @[pic_ctrl.scala 26:20] - node out_id_33 = mux(_T_1632, level_intpend_id[3][5], level_intpend_id[3][4]) @[pic_ctrl.scala 26:9] - node _T_1633 = lt(level_intpend_w_prior_en[3][4], level_intpend_w_prior_en[3][5]) @[pic_ctrl.scala 26:60] - node out_priority_33 = mux(_T_1633, level_intpend_w_prior_en[3][5], level_intpend_w_prior_en[3][4]) @[pic_ctrl.scala 26:49] - level_intpend_id[4][2] <= out_id_33 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[4][2] <= out_priority_33 @[pic_ctrl.scala 232:41] - node _T_1634 = lt(level_intpend_w_prior_en[4][0], level_intpend_w_prior_en[4][1]) @[pic_ctrl.scala 26:20] - node out_id_34 = mux(_T_1634, level_intpend_id[4][1], level_intpend_id[4][0]) @[pic_ctrl.scala 26:9] - node _T_1635 = lt(level_intpend_w_prior_en[4][0], level_intpend_w_prior_en[4][1]) @[pic_ctrl.scala 26:60] - node out_priority_34 = mux(_T_1635, level_intpend_w_prior_en[4][1], level_intpend_w_prior_en[4][0]) @[pic_ctrl.scala 26:49] - level_intpend_id[5][0] <= out_id_34 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[5][0] <= out_priority_34 @[pic_ctrl.scala 232:41] - level_intpend_w_prior_en[5][2] <= UInt<1>("h00") @[pic_ctrl.scala 227:44] - level_intpend_id[5][2] <= UInt<1>("h00") @[pic_ctrl.scala 228:44] - node _T_1636 = lt(level_intpend_w_prior_en[4][2], level_intpend_w_prior_en[4][3]) @[pic_ctrl.scala 26:20] - node out_id_35 = mux(_T_1636, level_intpend_id[4][3], level_intpend_id[4][2]) @[pic_ctrl.scala 26:9] - node _T_1637 = lt(level_intpend_w_prior_en[4][2], level_intpend_w_prior_en[4][3]) @[pic_ctrl.scala 26:60] - node out_priority_35 = mux(_T_1637, level_intpend_w_prior_en[4][3], level_intpend_w_prior_en[4][2]) @[pic_ctrl.scala 26:49] - level_intpend_id[5][1] <= out_id_35 @[pic_ctrl.scala 231:41] - level_intpend_w_prior_en[5][1] <= out_priority_35 @[pic_ctrl.scala 232:41] - claimid_in <= level_intpend_id[5][0] @[pic_ctrl.scala 235:29] - selected_int_priority <= level_intpend_w_prior_en[5][0] @[pic_ctrl.scala 236:29] - node config_reg_we = and(waddr_config_pic_match, picm_wren_ff) @[pic_ctrl.scala 248:47] - node config_reg_re = and(raddr_config_pic_match, picm_rden_ff) @[pic_ctrl.scala 249:47] - node config_reg_in = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 250:39] - node _T_1638 = bits(config_reg_we, 0, 0) @[pic_ctrl.scala 251:82] + level_intpend_id[0][0] <= intpend_id[0] @[pic_ctrl.scala 221:33] + level_intpend_id[0][1] <= intpend_id[1] @[pic_ctrl.scala 221:33] + level_intpend_id[0][2] <= intpend_id[2] @[pic_ctrl.scala 221:33] + level_intpend_id[0][3] <= intpend_id[3] @[pic_ctrl.scala 221:33] + level_intpend_id[0][4] <= intpend_id[4] @[pic_ctrl.scala 221:33] + level_intpend_id[0][5] <= intpend_id[5] @[pic_ctrl.scala 221:33] + level_intpend_id[0][6] <= intpend_id[6] @[pic_ctrl.scala 221:33] + level_intpend_id[0][7] <= intpend_id[7] @[pic_ctrl.scala 221:33] + level_intpend_id[0][8] <= intpend_id[8] @[pic_ctrl.scala 221:33] + level_intpend_id[0][9] <= intpend_id[9] @[pic_ctrl.scala 221:33] + level_intpend_id[0][10] <= intpend_id[10] @[pic_ctrl.scala 221:33] + level_intpend_id[0][11] <= intpend_id[11] @[pic_ctrl.scala 221:33] + level_intpend_id[0][12] <= intpend_id[12] @[pic_ctrl.scala 221:33] + level_intpend_id[0][13] <= intpend_id[13] @[pic_ctrl.scala 221:33] + level_intpend_id[0][14] <= intpend_id[14] @[pic_ctrl.scala 221:33] + level_intpend_id[0][15] <= intpend_id[15] @[pic_ctrl.scala 221:33] + level_intpend_id[0][16] <= intpend_id[16] @[pic_ctrl.scala 221:33] + level_intpend_id[0][17] <= intpend_id[17] @[pic_ctrl.scala 221:33] + level_intpend_id[0][18] <= intpend_id[18] @[pic_ctrl.scala 221:33] + level_intpend_id[0][19] <= intpend_id[19] @[pic_ctrl.scala 221:33] + level_intpend_id[0][20] <= intpend_id[20] @[pic_ctrl.scala 221:33] + level_intpend_id[0][21] <= intpend_id[21] @[pic_ctrl.scala 221:33] + level_intpend_id[0][22] <= intpend_id[22] @[pic_ctrl.scala 221:33] + level_intpend_id[0][23] <= intpend_id[23] @[pic_ctrl.scala 221:33] + level_intpend_id[0][24] <= intpend_id[24] @[pic_ctrl.scala 221:33] + level_intpend_id[0][25] <= intpend_id[25] @[pic_ctrl.scala 221:33] + level_intpend_id[0][26] <= intpend_id[26] @[pic_ctrl.scala 221:33] + level_intpend_id[0][27] <= intpend_id[27] @[pic_ctrl.scala 221:33] + level_intpend_id[0][28] <= intpend_id[28] @[pic_ctrl.scala 221:33] + level_intpend_id[0][29] <= intpend_id[29] @[pic_ctrl.scala 221:33] + level_intpend_id[0][30] <= intpend_id[30] @[pic_ctrl.scala 221:33] + level_intpend_id[0][31] <= intpend_id[31] @[pic_ctrl.scala 221:33] + level_intpend_id[0][32] <= _T_1564 @[pic_ctrl.scala 221:33] + level_intpend_id[0][33] <= _T_1565 @[pic_ctrl.scala 221:33] + node _T_1566 = lt(level_intpend_w_prior_en[0][0], level_intpend_w_prior_en[0][1]) @[pic_ctrl.scala 27:20] + node out_id = mux(_T_1566, level_intpend_id[0][1], level_intpend_id[0][0]) @[pic_ctrl.scala 27:9] + node _T_1567 = lt(level_intpend_w_prior_en[0][0], level_intpend_w_prior_en[0][1]) @[pic_ctrl.scala 27:60] + node out_priority = mux(_T_1567, level_intpend_w_prior_en[0][1], level_intpend_w_prior_en[0][0]) @[pic_ctrl.scala 27:49] + level_intpend_id[1][0] <= out_id @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[1][0] <= out_priority @[pic_ctrl.scala 233:41] + node _T_1568 = lt(level_intpend_w_prior_en[0][2], level_intpend_w_prior_en[0][3]) @[pic_ctrl.scala 27:20] + node out_id_1 = mux(_T_1568, level_intpend_id[0][3], level_intpend_id[0][2]) @[pic_ctrl.scala 27:9] + node _T_1569 = lt(level_intpend_w_prior_en[0][2], level_intpend_w_prior_en[0][3]) @[pic_ctrl.scala 27:60] + node out_priority_1 = mux(_T_1569, level_intpend_w_prior_en[0][3], level_intpend_w_prior_en[0][2]) @[pic_ctrl.scala 27:49] + level_intpend_id[1][1] <= out_id_1 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[1][1] <= out_priority_1 @[pic_ctrl.scala 233:41] + node _T_1570 = lt(level_intpend_w_prior_en[0][4], level_intpend_w_prior_en[0][5]) @[pic_ctrl.scala 27:20] + node out_id_2 = mux(_T_1570, level_intpend_id[0][5], level_intpend_id[0][4]) @[pic_ctrl.scala 27:9] + node _T_1571 = lt(level_intpend_w_prior_en[0][4], level_intpend_w_prior_en[0][5]) @[pic_ctrl.scala 27:60] + node out_priority_2 = mux(_T_1571, level_intpend_w_prior_en[0][5], level_intpend_w_prior_en[0][4]) @[pic_ctrl.scala 27:49] + level_intpend_id[1][2] <= out_id_2 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[1][2] <= out_priority_2 @[pic_ctrl.scala 233:41] + node _T_1572 = lt(level_intpend_w_prior_en[0][6], level_intpend_w_prior_en[0][7]) @[pic_ctrl.scala 27:20] + node out_id_3 = mux(_T_1572, level_intpend_id[0][7], level_intpend_id[0][6]) @[pic_ctrl.scala 27:9] + node _T_1573 = lt(level_intpend_w_prior_en[0][6], level_intpend_w_prior_en[0][7]) @[pic_ctrl.scala 27:60] + node out_priority_3 = mux(_T_1573, level_intpend_w_prior_en[0][7], level_intpend_w_prior_en[0][6]) @[pic_ctrl.scala 27:49] + level_intpend_id[1][3] <= out_id_3 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[1][3] <= out_priority_3 @[pic_ctrl.scala 233:41] + node _T_1574 = lt(level_intpend_w_prior_en[0][8], level_intpend_w_prior_en[0][9]) @[pic_ctrl.scala 27:20] + node out_id_4 = mux(_T_1574, level_intpend_id[0][9], level_intpend_id[0][8]) @[pic_ctrl.scala 27:9] + node _T_1575 = lt(level_intpend_w_prior_en[0][8], level_intpend_w_prior_en[0][9]) @[pic_ctrl.scala 27:60] + node out_priority_4 = mux(_T_1575, level_intpend_w_prior_en[0][9], level_intpend_w_prior_en[0][8]) @[pic_ctrl.scala 27:49] + level_intpend_id[1][4] <= out_id_4 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[1][4] <= out_priority_4 @[pic_ctrl.scala 233:41] + node _T_1576 = lt(level_intpend_w_prior_en[0][10], level_intpend_w_prior_en[0][11]) @[pic_ctrl.scala 27:20] + node out_id_5 = mux(_T_1576, level_intpend_id[0][11], level_intpend_id[0][10]) @[pic_ctrl.scala 27:9] + node _T_1577 = lt(level_intpend_w_prior_en[0][10], level_intpend_w_prior_en[0][11]) @[pic_ctrl.scala 27:60] + node out_priority_5 = mux(_T_1577, level_intpend_w_prior_en[0][11], level_intpend_w_prior_en[0][10]) @[pic_ctrl.scala 27:49] + level_intpend_id[1][5] <= out_id_5 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[1][5] <= out_priority_5 @[pic_ctrl.scala 233:41] + node _T_1578 = lt(level_intpend_w_prior_en[0][12], level_intpend_w_prior_en[0][13]) @[pic_ctrl.scala 27:20] + node out_id_6 = mux(_T_1578, level_intpend_id[0][13], level_intpend_id[0][12]) @[pic_ctrl.scala 27:9] + node _T_1579 = lt(level_intpend_w_prior_en[0][12], level_intpend_w_prior_en[0][13]) @[pic_ctrl.scala 27:60] + node out_priority_6 = mux(_T_1579, level_intpend_w_prior_en[0][13], level_intpend_w_prior_en[0][12]) @[pic_ctrl.scala 27:49] + level_intpend_id[1][6] <= out_id_6 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[1][6] <= out_priority_6 @[pic_ctrl.scala 233:41] + node _T_1580 = lt(level_intpend_w_prior_en[0][14], level_intpend_w_prior_en[0][15]) @[pic_ctrl.scala 27:20] + node out_id_7 = mux(_T_1580, level_intpend_id[0][15], level_intpend_id[0][14]) @[pic_ctrl.scala 27:9] + node _T_1581 = lt(level_intpend_w_prior_en[0][14], level_intpend_w_prior_en[0][15]) @[pic_ctrl.scala 27:60] + node out_priority_7 = mux(_T_1581, level_intpend_w_prior_en[0][15], level_intpend_w_prior_en[0][14]) @[pic_ctrl.scala 27:49] + level_intpend_id[1][7] <= out_id_7 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[1][7] <= out_priority_7 @[pic_ctrl.scala 233:41] + node _T_1582 = lt(level_intpend_w_prior_en[0][16], level_intpend_w_prior_en[0][17]) @[pic_ctrl.scala 27:20] + node out_id_8 = mux(_T_1582, level_intpend_id[0][17], level_intpend_id[0][16]) @[pic_ctrl.scala 27:9] + node _T_1583 = lt(level_intpend_w_prior_en[0][16], level_intpend_w_prior_en[0][17]) @[pic_ctrl.scala 27:60] + node out_priority_8 = mux(_T_1583, level_intpend_w_prior_en[0][17], level_intpend_w_prior_en[0][16]) @[pic_ctrl.scala 27:49] + level_intpend_id[1][8] <= out_id_8 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[1][8] <= out_priority_8 @[pic_ctrl.scala 233:41] + node _T_1584 = lt(level_intpend_w_prior_en[0][18], level_intpend_w_prior_en[0][19]) @[pic_ctrl.scala 27:20] + node out_id_9 = mux(_T_1584, level_intpend_id[0][19], level_intpend_id[0][18]) @[pic_ctrl.scala 27:9] + node _T_1585 = lt(level_intpend_w_prior_en[0][18], level_intpend_w_prior_en[0][19]) @[pic_ctrl.scala 27:60] + node out_priority_9 = mux(_T_1585, level_intpend_w_prior_en[0][19], level_intpend_w_prior_en[0][18]) @[pic_ctrl.scala 27:49] + level_intpend_id[1][9] <= out_id_9 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[1][9] <= out_priority_9 @[pic_ctrl.scala 233:41] + node _T_1586 = lt(level_intpend_w_prior_en[0][20], level_intpend_w_prior_en[0][21]) @[pic_ctrl.scala 27:20] + node out_id_10 = mux(_T_1586, level_intpend_id[0][21], level_intpend_id[0][20]) @[pic_ctrl.scala 27:9] + node _T_1587 = lt(level_intpend_w_prior_en[0][20], level_intpend_w_prior_en[0][21]) @[pic_ctrl.scala 27:60] + node out_priority_10 = mux(_T_1587, level_intpend_w_prior_en[0][21], level_intpend_w_prior_en[0][20]) @[pic_ctrl.scala 27:49] + level_intpend_id[1][10] <= out_id_10 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[1][10] <= out_priority_10 @[pic_ctrl.scala 233:41] + node _T_1588 = lt(level_intpend_w_prior_en[0][22], level_intpend_w_prior_en[0][23]) @[pic_ctrl.scala 27:20] + node out_id_11 = mux(_T_1588, level_intpend_id[0][23], level_intpend_id[0][22]) @[pic_ctrl.scala 27:9] + node _T_1589 = lt(level_intpend_w_prior_en[0][22], level_intpend_w_prior_en[0][23]) @[pic_ctrl.scala 27:60] + node out_priority_11 = mux(_T_1589, level_intpend_w_prior_en[0][23], level_intpend_w_prior_en[0][22]) @[pic_ctrl.scala 27:49] + level_intpend_id[1][11] <= out_id_11 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[1][11] <= out_priority_11 @[pic_ctrl.scala 233:41] + node _T_1590 = lt(level_intpend_w_prior_en[0][24], level_intpend_w_prior_en[0][25]) @[pic_ctrl.scala 27:20] + node out_id_12 = mux(_T_1590, level_intpend_id[0][25], level_intpend_id[0][24]) @[pic_ctrl.scala 27:9] + node _T_1591 = lt(level_intpend_w_prior_en[0][24], level_intpend_w_prior_en[0][25]) @[pic_ctrl.scala 27:60] + node out_priority_12 = mux(_T_1591, level_intpend_w_prior_en[0][25], level_intpend_w_prior_en[0][24]) @[pic_ctrl.scala 27:49] + level_intpend_id[1][12] <= out_id_12 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[1][12] <= out_priority_12 @[pic_ctrl.scala 233:41] + node _T_1592 = lt(level_intpend_w_prior_en[0][26], level_intpend_w_prior_en[0][27]) @[pic_ctrl.scala 27:20] + node out_id_13 = mux(_T_1592, level_intpend_id[0][27], level_intpend_id[0][26]) @[pic_ctrl.scala 27:9] + node _T_1593 = lt(level_intpend_w_prior_en[0][26], level_intpend_w_prior_en[0][27]) @[pic_ctrl.scala 27:60] + node out_priority_13 = mux(_T_1593, level_intpend_w_prior_en[0][27], level_intpend_w_prior_en[0][26]) @[pic_ctrl.scala 27:49] + level_intpend_id[1][13] <= out_id_13 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[1][13] <= out_priority_13 @[pic_ctrl.scala 233:41] + node _T_1594 = lt(level_intpend_w_prior_en[0][28], level_intpend_w_prior_en[0][29]) @[pic_ctrl.scala 27:20] + node out_id_14 = mux(_T_1594, level_intpend_id[0][29], level_intpend_id[0][28]) @[pic_ctrl.scala 27:9] + node _T_1595 = lt(level_intpend_w_prior_en[0][28], level_intpend_w_prior_en[0][29]) @[pic_ctrl.scala 27:60] + node out_priority_14 = mux(_T_1595, level_intpend_w_prior_en[0][29], level_intpend_w_prior_en[0][28]) @[pic_ctrl.scala 27:49] + level_intpend_id[1][14] <= out_id_14 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[1][14] <= out_priority_14 @[pic_ctrl.scala 233:41] + node _T_1596 = lt(level_intpend_w_prior_en[0][30], level_intpend_w_prior_en[0][31]) @[pic_ctrl.scala 27:20] + node out_id_15 = mux(_T_1596, level_intpend_id[0][31], level_intpend_id[0][30]) @[pic_ctrl.scala 27:9] + node _T_1597 = lt(level_intpend_w_prior_en[0][30], level_intpend_w_prior_en[0][31]) @[pic_ctrl.scala 27:60] + node out_priority_15 = mux(_T_1597, level_intpend_w_prior_en[0][31], level_intpend_w_prior_en[0][30]) @[pic_ctrl.scala 27:49] + level_intpend_id[1][15] <= out_id_15 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[1][15] <= out_priority_15 @[pic_ctrl.scala 233:41] + level_intpend_w_prior_en[1][17] <= UInt<1>("h00") @[pic_ctrl.scala 228:44] + level_intpend_id[1][17] <= UInt<1>("h00") @[pic_ctrl.scala 229:44] + node _T_1598 = lt(level_intpend_w_prior_en[0][32], level_intpend_w_prior_en[0][33]) @[pic_ctrl.scala 27:20] + node out_id_16 = mux(_T_1598, level_intpend_id[0][33], level_intpend_id[0][32]) @[pic_ctrl.scala 27:9] + node _T_1599 = lt(level_intpend_w_prior_en[0][32], level_intpend_w_prior_en[0][33]) @[pic_ctrl.scala 27:60] + node out_priority_16 = mux(_T_1599, level_intpend_w_prior_en[0][33], level_intpend_w_prior_en[0][32]) @[pic_ctrl.scala 27:49] + level_intpend_id[1][16] <= out_id_16 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[1][16] <= out_priority_16 @[pic_ctrl.scala 233:41] + node _T_1600 = lt(level_intpend_w_prior_en[1][0], level_intpend_w_prior_en[1][1]) @[pic_ctrl.scala 27:20] + node out_id_17 = mux(_T_1600, level_intpend_id[1][1], level_intpend_id[1][0]) @[pic_ctrl.scala 27:9] + node _T_1601 = lt(level_intpend_w_prior_en[1][0], level_intpend_w_prior_en[1][1]) @[pic_ctrl.scala 27:60] + node out_priority_17 = mux(_T_1601, level_intpend_w_prior_en[1][1], level_intpend_w_prior_en[1][0]) @[pic_ctrl.scala 27:49] + level_intpend_id[2][0] <= out_id_17 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[2][0] <= out_priority_17 @[pic_ctrl.scala 233:41] + node _T_1602 = lt(level_intpend_w_prior_en[1][2], level_intpend_w_prior_en[1][3]) @[pic_ctrl.scala 27:20] + node out_id_18 = mux(_T_1602, level_intpend_id[1][3], level_intpend_id[1][2]) @[pic_ctrl.scala 27:9] + node _T_1603 = lt(level_intpend_w_prior_en[1][2], level_intpend_w_prior_en[1][3]) @[pic_ctrl.scala 27:60] + node out_priority_18 = mux(_T_1603, level_intpend_w_prior_en[1][3], level_intpend_w_prior_en[1][2]) @[pic_ctrl.scala 27:49] + level_intpend_id[2][1] <= out_id_18 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[2][1] <= out_priority_18 @[pic_ctrl.scala 233:41] + node _T_1604 = lt(level_intpend_w_prior_en[1][4], level_intpend_w_prior_en[1][5]) @[pic_ctrl.scala 27:20] + node out_id_19 = mux(_T_1604, level_intpend_id[1][5], level_intpend_id[1][4]) @[pic_ctrl.scala 27:9] + node _T_1605 = lt(level_intpend_w_prior_en[1][4], level_intpend_w_prior_en[1][5]) @[pic_ctrl.scala 27:60] + node out_priority_19 = mux(_T_1605, level_intpend_w_prior_en[1][5], level_intpend_w_prior_en[1][4]) @[pic_ctrl.scala 27:49] + level_intpend_id[2][2] <= out_id_19 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[2][2] <= out_priority_19 @[pic_ctrl.scala 233:41] + node _T_1606 = lt(level_intpend_w_prior_en[1][6], level_intpend_w_prior_en[1][7]) @[pic_ctrl.scala 27:20] + node out_id_20 = mux(_T_1606, level_intpend_id[1][7], level_intpend_id[1][6]) @[pic_ctrl.scala 27:9] + node _T_1607 = lt(level_intpend_w_prior_en[1][6], level_intpend_w_prior_en[1][7]) @[pic_ctrl.scala 27:60] + node out_priority_20 = mux(_T_1607, level_intpend_w_prior_en[1][7], level_intpend_w_prior_en[1][6]) @[pic_ctrl.scala 27:49] + level_intpend_id[2][3] <= out_id_20 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[2][3] <= out_priority_20 @[pic_ctrl.scala 233:41] + node _T_1608 = lt(level_intpend_w_prior_en[1][8], level_intpend_w_prior_en[1][9]) @[pic_ctrl.scala 27:20] + node out_id_21 = mux(_T_1608, level_intpend_id[1][9], level_intpend_id[1][8]) @[pic_ctrl.scala 27:9] + node _T_1609 = lt(level_intpend_w_prior_en[1][8], level_intpend_w_prior_en[1][9]) @[pic_ctrl.scala 27:60] + node out_priority_21 = mux(_T_1609, level_intpend_w_prior_en[1][9], level_intpend_w_prior_en[1][8]) @[pic_ctrl.scala 27:49] + level_intpend_id[2][4] <= out_id_21 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[2][4] <= out_priority_21 @[pic_ctrl.scala 233:41] + node _T_1610 = lt(level_intpend_w_prior_en[1][10], level_intpend_w_prior_en[1][11]) @[pic_ctrl.scala 27:20] + node out_id_22 = mux(_T_1610, level_intpend_id[1][11], level_intpend_id[1][10]) @[pic_ctrl.scala 27:9] + node _T_1611 = lt(level_intpend_w_prior_en[1][10], level_intpend_w_prior_en[1][11]) @[pic_ctrl.scala 27:60] + node out_priority_22 = mux(_T_1611, level_intpend_w_prior_en[1][11], level_intpend_w_prior_en[1][10]) @[pic_ctrl.scala 27:49] + level_intpend_id[2][5] <= out_id_22 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[2][5] <= out_priority_22 @[pic_ctrl.scala 233:41] + node _T_1612 = lt(level_intpend_w_prior_en[1][12], level_intpend_w_prior_en[1][13]) @[pic_ctrl.scala 27:20] + node out_id_23 = mux(_T_1612, level_intpend_id[1][13], level_intpend_id[1][12]) @[pic_ctrl.scala 27:9] + node _T_1613 = lt(level_intpend_w_prior_en[1][12], level_intpend_w_prior_en[1][13]) @[pic_ctrl.scala 27:60] + node out_priority_23 = mux(_T_1613, level_intpend_w_prior_en[1][13], level_intpend_w_prior_en[1][12]) @[pic_ctrl.scala 27:49] + level_intpend_id[2][6] <= out_id_23 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[2][6] <= out_priority_23 @[pic_ctrl.scala 233:41] + node _T_1614 = lt(level_intpend_w_prior_en[1][14], level_intpend_w_prior_en[1][15]) @[pic_ctrl.scala 27:20] + node out_id_24 = mux(_T_1614, level_intpend_id[1][15], level_intpend_id[1][14]) @[pic_ctrl.scala 27:9] + node _T_1615 = lt(level_intpend_w_prior_en[1][14], level_intpend_w_prior_en[1][15]) @[pic_ctrl.scala 27:60] + node out_priority_24 = mux(_T_1615, level_intpend_w_prior_en[1][15], level_intpend_w_prior_en[1][14]) @[pic_ctrl.scala 27:49] + level_intpend_id[2][7] <= out_id_24 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[2][7] <= out_priority_24 @[pic_ctrl.scala 233:41] + level_intpend_w_prior_en[2][9] <= UInt<1>("h00") @[pic_ctrl.scala 228:44] + level_intpend_id[2][9] <= UInt<1>("h00") @[pic_ctrl.scala 229:44] + node _T_1616 = lt(level_intpend_w_prior_en[1][16], level_intpend_w_prior_en[1][17]) @[pic_ctrl.scala 27:20] + node out_id_25 = mux(_T_1616, level_intpend_id[1][17], level_intpend_id[1][16]) @[pic_ctrl.scala 27:9] + node _T_1617 = lt(level_intpend_w_prior_en[1][16], level_intpend_w_prior_en[1][17]) @[pic_ctrl.scala 27:60] + node out_priority_25 = mux(_T_1617, level_intpend_w_prior_en[1][17], level_intpend_w_prior_en[1][16]) @[pic_ctrl.scala 27:49] + level_intpend_id[2][8] <= out_id_25 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[2][8] <= out_priority_25 @[pic_ctrl.scala 233:41] + node _T_1618 = lt(level_intpend_w_prior_en[2][0], level_intpend_w_prior_en[2][1]) @[pic_ctrl.scala 27:20] + node out_id_26 = mux(_T_1618, level_intpend_id[2][1], level_intpend_id[2][0]) @[pic_ctrl.scala 27:9] + node _T_1619 = lt(level_intpend_w_prior_en[2][0], level_intpend_w_prior_en[2][1]) @[pic_ctrl.scala 27:60] + node out_priority_26 = mux(_T_1619, level_intpend_w_prior_en[2][1], level_intpend_w_prior_en[2][0]) @[pic_ctrl.scala 27:49] + level_intpend_id[3][0] <= out_id_26 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[3][0] <= out_priority_26 @[pic_ctrl.scala 233:41] + node _T_1620 = lt(level_intpend_w_prior_en[2][2], level_intpend_w_prior_en[2][3]) @[pic_ctrl.scala 27:20] + node out_id_27 = mux(_T_1620, level_intpend_id[2][3], level_intpend_id[2][2]) @[pic_ctrl.scala 27:9] + node _T_1621 = lt(level_intpend_w_prior_en[2][2], level_intpend_w_prior_en[2][3]) @[pic_ctrl.scala 27:60] + node out_priority_27 = mux(_T_1621, level_intpend_w_prior_en[2][3], level_intpend_w_prior_en[2][2]) @[pic_ctrl.scala 27:49] + level_intpend_id[3][1] <= out_id_27 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[3][1] <= out_priority_27 @[pic_ctrl.scala 233:41] + node _T_1622 = lt(level_intpend_w_prior_en[2][4], level_intpend_w_prior_en[2][5]) @[pic_ctrl.scala 27:20] + node out_id_28 = mux(_T_1622, level_intpend_id[2][5], level_intpend_id[2][4]) @[pic_ctrl.scala 27:9] + node _T_1623 = lt(level_intpend_w_prior_en[2][4], level_intpend_w_prior_en[2][5]) @[pic_ctrl.scala 27:60] + node out_priority_28 = mux(_T_1623, level_intpend_w_prior_en[2][5], level_intpend_w_prior_en[2][4]) @[pic_ctrl.scala 27:49] + level_intpend_id[3][2] <= out_id_28 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[3][2] <= out_priority_28 @[pic_ctrl.scala 233:41] + node _T_1624 = lt(level_intpend_w_prior_en[2][6], level_intpend_w_prior_en[2][7]) @[pic_ctrl.scala 27:20] + node out_id_29 = mux(_T_1624, level_intpend_id[2][7], level_intpend_id[2][6]) @[pic_ctrl.scala 27:9] + node _T_1625 = lt(level_intpend_w_prior_en[2][6], level_intpend_w_prior_en[2][7]) @[pic_ctrl.scala 27:60] + node out_priority_29 = mux(_T_1625, level_intpend_w_prior_en[2][7], level_intpend_w_prior_en[2][6]) @[pic_ctrl.scala 27:49] + level_intpend_id[3][3] <= out_id_29 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[3][3] <= out_priority_29 @[pic_ctrl.scala 233:41] + level_intpend_w_prior_en[3][5] <= UInt<1>("h00") @[pic_ctrl.scala 228:44] + level_intpend_id[3][5] <= UInt<1>("h00") @[pic_ctrl.scala 229:44] + node _T_1626 = lt(level_intpend_w_prior_en[2][8], level_intpend_w_prior_en[2][9]) @[pic_ctrl.scala 27:20] + node out_id_30 = mux(_T_1626, level_intpend_id[2][9], level_intpend_id[2][8]) @[pic_ctrl.scala 27:9] + node _T_1627 = lt(level_intpend_w_prior_en[2][8], level_intpend_w_prior_en[2][9]) @[pic_ctrl.scala 27:60] + node out_priority_30 = mux(_T_1627, level_intpend_w_prior_en[2][9], level_intpend_w_prior_en[2][8]) @[pic_ctrl.scala 27:49] + level_intpend_id[3][4] <= out_id_30 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[3][4] <= out_priority_30 @[pic_ctrl.scala 233:41] + node _T_1628 = lt(level_intpend_w_prior_en[3][0], level_intpend_w_prior_en[3][1]) @[pic_ctrl.scala 27:20] + node out_id_31 = mux(_T_1628, level_intpend_id[3][1], level_intpend_id[3][0]) @[pic_ctrl.scala 27:9] + node _T_1629 = lt(level_intpend_w_prior_en[3][0], level_intpend_w_prior_en[3][1]) @[pic_ctrl.scala 27:60] + node out_priority_31 = mux(_T_1629, level_intpend_w_prior_en[3][1], level_intpend_w_prior_en[3][0]) @[pic_ctrl.scala 27:49] + level_intpend_id[4][0] <= out_id_31 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[4][0] <= out_priority_31 @[pic_ctrl.scala 233:41] + node _T_1630 = lt(level_intpend_w_prior_en[3][2], level_intpend_w_prior_en[3][3]) @[pic_ctrl.scala 27:20] + node out_id_32 = mux(_T_1630, level_intpend_id[3][3], level_intpend_id[3][2]) @[pic_ctrl.scala 27:9] + node _T_1631 = lt(level_intpend_w_prior_en[3][2], level_intpend_w_prior_en[3][3]) @[pic_ctrl.scala 27:60] + node out_priority_32 = mux(_T_1631, level_intpend_w_prior_en[3][3], level_intpend_w_prior_en[3][2]) @[pic_ctrl.scala 27:49] + level_intpend_id[4][1] <= out_id_32 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[4][1] <= out_priority_32 @[pic_ctrl.scala 233:41] + level_intpend_w_prior_en[4][3] <= UInt<1>("h00") @[pic_ctrl.scala 228:44] + level_intpend_id[4][3] <= UInt<1>("h00") @[pic_ctrl.scala 229:44] + node _T_1632 = lt(level_intpend_w_prior_en[3][4], level_intpend_w_prior_en[3][5]) @[pic_ctrl.scala 27:20] + node out_id_33 = mux(_T_1632, level_intpend_id[3][5], level_intpend_id[3][4]) @[pic_ctrl.scala 27:9] + node _T_1633 = lt(level_intpend_w_prior_en[3][4], level_intpend_w_prior_en[3][5]) @[pic_ctrl.scala 27:60] + node out_priority_33 = mux(_T_1633, level_intpend_w_prior_en[3][5], level_intpend_w_prior_en[3][4]) @[pic_ctrl.scala 27:49] + level_intpend_id[4][2] <= out_id_33 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[4][2] <= out_priority_33 @[pic_ctrl.scala 233:41] + node _T_1634 = lt(level_intpend_w_prior_en[4][0], level_intpend_w_prior_en[4][1]) @[pic_ctrl.scala 27:20] + node out_id_34 = mux(_T_1634, level_intpend_id[4][1], level_intpend_id[4][0]) @[pic_ctrl.scala 27:9] + node _T_1635 = lt(level_intpend_w_prior_en[4][0], level_intpend_w_prior_en[4][1]) @[pic_ctrl.scala 27:60] + node out_priority_34 = mux(_T_1635, level_intpend_w_prior_en[4][1], level_intpend_w_prior_en[4][0]) @[pic_ctrl.scala 27:49] + level_intpend_id[5][0] <= out_id_34 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[5][0] <= out_priority_34 @[pic_ctrl.scala 233:41] + level_intpend_w_prior_en[5][2] <= UInt<1>("h00") @[pic_ctrl.scala 228:44] + level_intpend_id[5][2] <= UInt<1>("h00") @[pic_ctrl.scala 229:44] + node _T_1636 = lt(level_intpend_w_prior_en[4][2], level_intpend_w_prior_en[4][3]) @[pic_ctrl.scala 27:20] + node out_id_35 = mux(_T_1636, level_intpend_id[4][3], level_intpend_id[4][2]) @[pic_ctrl.scala 27:9] + node _T_1637 = lt(level_intpend_w_prior_en[4][2], level_intpend_w_prior_en[4][3]) @[pic_ctrl.scala 27:60] + node out_priority_35 = mux(_T_1637, level_intpend_w_prior_en[4][3], level_intpend_w_prior_en[4][2]) @[pic_ctrl.scala 27:49] + level_intpend_id[5][1] <= out_id_35 @[pic_ctrl.scala 232:41] + level_intpend_w_prior_en[5][1] <= out_priority_35 @[pic_ctrl.scala 233:41] + claimid_in <= level_intpend_id[5][0] @[pic_ctrl.scala 236:29] + selected_int_priority <= level_intpend_w_prior_en[5][0] @[pic_ctrl.scala 237:29] + node config_reg_we = and(waddr_config_pic_match, picm_wren_ff) @[pic_ctrl.scala 249:47] + node config_reg_re = and(raddr_config_pic_match, picm_rden_ff) @[pic_ctrl.scala 250:47] + node config_reg_in = bits(picm_wr_data_ff, 0, 0) @[pic_ctrl.scala 251:39] + node _T_1638 = bits(config_reg_we, 0, 0) @[pic_ctrl.scala 252:82] reg _T_1639 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1638 : @[Reg.scala 28:19] _T_1639 <= config_reg_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - config_reg <= _T_1639 @[pic_ctrl.scala 251:37] - intpriord <= config_reg @[pic_ctrl.scala 252:14] - node _T_1640 = bits(intpriord, 0, 0) @[pic_ctrl.scala 260:31] - node _T_1641 = not(selected_int_priority) @[pic_ctrl.scala 260:38] - node pl_in_q = mux(_T_1640, _T_1641, selected_int_priority) @[pic_ctrl.scala 260:20] - reg _T_1642 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 261:47] - _T_1642 <= claimid_in @[pic_ctrl.scala 261:47] - io.claimid <= _T_1642 @[pic_ctrl.scala 261:37] - reg _T_1643 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 262:42] - _T_1643 <= pl_in_q @[pic_ctrl.scala 262:42] - io.pl <= _T_1643 @[pic_ctrl.scala 262:32] - node _T_1644 = bits(intpriord, 0, 0) @[pic_ctrl.scala 263:33] - node _T_1645 = not(io.meipt) @[pic_ctrl.scala 263:40] - node meipt_inv = mux(_T_1644, _T_1645, io.meipt) @[pic_ctrl.scala 263:22] - node _T_1646 = bits(intpriord, 0, 0) @[pic_ctrl.scala 264:36] - node _T_1647 = not(io.meicurpl) @[pic_ctrl.scala 264:43] - node meicurpl_inv = mux(_T_1646, _T_1647, io.meicurpl) @[pic_ctrl.scala 264:25] - node _T_1648 = gt(selected_int_priority, meipt_inv) @[pic_ctrl.scala 265:47] - node _T_1649 = gt(selected_int_priority, meicurpl_inv) @[pic_ctrl.scala 265:86] - node mexintpend_in = and(_T_1648, _T_1649) @[pic_ctrl.scala 265:60] - reg _T_1650 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 266:50] - _T_1650 <= mexintpend_in @[pic_ctrl.scala 266:50] - io.mexintpend <= _T_1650 @[pic_ctrl.scala 266:17] - node _T_1651 = bits(intpriord, 0, 0) @[pic_ctrl.scala 267:30] - node maxint = mux(_T_1651, UInt<1>("h00"), UInt<4>("h0f")) @[pic_ctrl.scala 267:19] - node mhwakeup_in = eq(pl_in_q, maxint) @[pic_ctrl.scala 268:29] - reg _T_1652 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 269:48] - _T_1652 <= mhwakeup_in @[pic_ctrl.scala 269:48] - io.mhwakeup <= _T_1652 @[pic_ctrl.scala 269:15] - node intpend_reg_read = and(addr_intpend_base_match, picm_rden_ff) @[pic_ctrl.scala 275:60] - node intpriority_reg_read = and(raddr_intpriority_base_match, picm_rden_ff) @[pic_ctrl.scala 276:60] - node intenable_reg_read = and(raddr_intenable_base_match, picm_rden_ff) @[pic_ctrl.scala 277:60] - node gw_config_reg_read = and(raddr_config_gw_base_match, picm_rden_ff) @[pic_ctrl.scala 278:60] + config_reg <= _T_1639 @[pic_ctrl.scala 252:37] + intpriord <= config_reg @[pic_ctrl.scala 253:14] + node _T_1640 = bits(intpriord, 0, 0) @[pic_ctrl.scala 261:31] + node _T_1641 = not(selected_int_priority) @[pic_ctrl.scala 261:38] + node pl_in_q = mux(_T_1640, _T_1641, selected_int_priority) @[pic_ctrl.scala 261:20] + reg _T_1642 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 262:59] + _T_1642 <= claimid_in @[pic_ctrl.scala 262:59] + io.dec_pic.pic_claimid <= _T_1642 @[pic_ctrl.scala 262:49] + reg _T_1643 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 263:54] + _T_1643 <= pl_in_q @[pic_ctrl.scala 263:54] + io.dec_pic.pic_pl <= _T_1643 @[pic_ctrl.scala 263:44] + node _T_1644 = bits(intpriord, 0, 0) @[pic_ctrl.scala 264:33] + node _T_1645 = not(io.dec_pic.dec_tlu_meipt) @[pic_ctrl.scala 264:40] + node meipt_inv = mux(_T_1644, _T_1645, io.dec_pic.dec_tlu_meipt) @[pic_ctrl.scala 264:22] + node _T_1646 = bits(intpriord, 0, 0) @[pic_ctrl.scala 265:36] + node _T_1647 = not(io.dec_pic.dec_tlu_meicurpl) @[pic_ctrl.scala 265:43] + node meicurpl_inv = mux(_T_1646, _T_1647, io.dec_pic.dec_tlu_meicurpl) @[pic_ctrl.scala 265:25] + node _T_1648 = gt(selected_int_priority, meipt_inv) @[pic_ctrl.scala 266:47] + node _T_1649 = gt(selected_int_priority, meicurpl_inv) @[pic_ctrl.scala 266:86] + node mexintpend_in = and(_T_1648, _T_1649) @[pic_ctrl.scala 266:60] + reg _T_1650 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 267:58] + _T_1650 <= mexintpend_in @[pic_ctrl.scala 267:58] + io.dec_pic.mexintpend <= _T_1650 @[pic_ctrl.scala 267:25] + node _T_1651 = bits(intpriord, 0, 0) @[pic_ctrl.scala 268:30] + node maxint = mux(_T_1651, UInt<1>("h00"), UInt<4>("h0f")) @[pic_ctrl.scala 268:19] + node mhwakeup_in = eq(pl_in_q, maxint) @[pic_ctrl.scala 269:29] + reg _T_1652 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[pic_ctrl.scala 270:56] + _T_1652 <= mhwakeup_in @[pic_ctrl.scala 270:56] + io.dec_pic.mhwakeup <= _T_1652 @[pic_ctrl.scala 270:23] + node intpend_reg_read = and(addr_intpend_base_match, picm_rden_ff) @[pic_ctrl.scala 276:60] + node intpriority_reg_read = and(raddr_intpriority_base_match, picm_rden_ff) @[pic_ctrl.scala 277:60] + node intenable_reg_read = and(raddr_intenable_base_match, picm_rden_ff) @[pic_ctrl.scala 278:60] + node gw_config_reg_read = and(raddr_config_gw_base_match, picm_rden_ff) @[pic_ctrl.scala 279:60] node _T_1653 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] node _T_1654 = cat(extintsrc_req_gw_31, extintsrc_req_gw_30) @[Cat.scala 29:58] node _T_1655 = cat(_T_1654, extintsrc_req_gw_29) @[Cat.scala 29:58] @@ -105910,57 +105907,57 @@ circuit quasar_wrapper : node _T_1683 = cat(_T_1682, extintsrc_req_gw_1) @[Cat.scala 29:58] node _T_1684 = cat(_T_1683, UInt<1>("h00")) @[Cat.scala 29:58] node _T_1685 = cat(_T_1653, _T_1684) @[Cat.scala 29:58] - intpend_reg_extended <= _T_1685 @[pic_ctrl.scala 280:25] - wire intpend_rd_part_out : UInt<32>[2] @[pic_ctrl.scala 282:33] - node _T_1686 = bits(picm_raddr_ff, 5, 2) @[pic_ctrl.scala 283:101] - node _T_1687 = eq(_T_1686, UInt<1>("h00")) @[pic_ctrl.scala 283:107] - node _T_1688 = and(intpend_reg_read, _T_1687) @[pic_ctrl.scala 283:85] + intpend_reg_extended <= _T_1685 @[pic_ctrl.scala 281:25] + wire intpend_rd_part_out : UInt<32>[2] @[pic_ctrl.scala 283:33] + node _T_1686 = bits(picm_raddr_ff, 5, 2) @[pic_ctrl.scala 284:101] + node _T_1687 = eq(_T_1686, UInt<1>("h00")) @[pic_ctrl.scala 284:107] + node _T_1688 = and(intpend_reg_read, _T_1687) @[pic_ctrl.scala 284:85] node _T_1689 = bits(_T_1688, 0, 0) @[Bitwise.scala 72:15] node _T_1690 = mux(_T_1689, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_1691 = bits(intpend_reg_extended, 31, 0) @[pic_ctrl.scala 283:145] - node _T_1692 = and(_T_1690, _T_1691) @[pic_ctrl.scala 283:123] - intpend_rd_part_out[0] <= _T_1692 @[pic_ctrl.scala 283:56] - node _T_1693 = bits(picm_raddr_ff, 5, 2) @[pic_ctrl.scala 283:101] - node _T_1694 = eq(_T_1693, UInt<1>("h01")) @[pic_ctrl.scala 283:107] - node _T_1695 = and(intpend_reg_read, _T_1694) @[pic_ctrl.scala 283:85] + node _T_1691 = bits(intpend_reg_extended, 31, 0) @[pic_ctrl.scala 284:145] + node _T_1692 = and(_T_1690, _T_1691) @[pic_ctrl.scala 284:123] + intpend_rd_part_out[0] <= _T_1692 @[pic_ctrl.scala 284:56] + node _T_1693 = bits(picm_raddr_ff, 5, 2) @[pic_ctrl.scala 284:101] + node _T_1694 = eq(_T_1693, UInt<1>("h01")) @[pic_ctrl.scala 284:107] + node _T_1695 = and(intpend_reg_read, _T_1694) @[pic_ctrl.scala 284:85] node _T_1696 = bits(_T_1695, 0, 0) @[Bitwise.scala 72:15] node _T_1697 = mux(_T_1696, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_1698 = bits(intpend_reg_extended, 63, 32) @[pic_ctrl.scala 283:145] - node _T_1699 = and(_T_1697, _T_1698) @[pic_ctrl.scala 283:123] - intpend_rd_part_out[1] <= _T_1699 @[pic_ctrl.scala 283:56] - node _T_1700 = or(intpend_rd_part_out[0], intpend_rd_part_out[1]) @[pic_ctrl.scala 284:58] - intpend_rd_out <= _T_1700 @[pic_ctrl.scala 284:26] - node _T_1701 = bits(intenable_reg_re_1, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1702 = bits(intenable_reg_re_2, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1703 = bits(intenable_reg_re_3, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1704 = bits(intenable_reg_re_4, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1705 = bits(intenable_reg_re_5, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1706 = bits(intenable_reg_re_6, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1707 = bits(intenable_reg_re_7, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1708 = bits(intenable_reg_re_8, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1709 = bits(intenable_reg_re_9, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1710 = bits(intenable_reg_re_10, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1711 = bits(intenable_reg_re_11, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1712 = bits(intenable_reg_re_12, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1713 = bits(intenable_reg_re_13, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1714 = bits(intenable_reg_re_14, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1715 = bits(intenable_reg_re_15, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1716 = bits(intenable_reg_re_16, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1717 = bits(intenable_reg_re_17, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1718 = bits(intenable_reg_re_18, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1719 = bits(intenable_reg_re_19, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1720 = bits(intenable_reg_re_20, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1721 = bits(intenable_reg_re_21, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1722 = bits(intenable_reg_re_22, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1723 = bits(intenable_reg_re_23, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1724 = bits(intenable_reg_re_24, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1725 = bits(intenable_reg_re_25, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1726 = bits(intenable_reg_re_26, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1727 = bits(intenable_reg_re_27, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1728 = bits(intenable_reg_re_28, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1729 = bits(intenable_reg_re_29, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1730 = bits(intenable_reg_re_30, 0, 0) @[pic_ctrl.scala 286:97] - node _T_1731 = bits(intenable_reg_re_31, 0, 0) @[pic_ctrl.scala 286:97] + node _T_1698 = bits(intpend_reg_extended, 63, 32) @[pic_ctrl.scala 284:145] + node _T_1699 = and(_T_1697, _T_1698) @[pic_ctrl.scala 284:123] + intpend_rd_part_out[1] <= _T_1699 @[pic_ctrl.scala 284:56] + node _T_1700 = or(intpend_rd_part_out[0], intpend_rd_part_out[1]) @[pic_ctrl.scala 285:58] + intpend_rd_out <= _T_1700 @[pic_ctrl.scala 285:26] + node _T_1701 = bits(intenable_reg_re_1, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1702 = bits(intenable_reg_re_2, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1703 = bits(intenable_reg_re_3, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1704 = bits(intenable_reg_re_4, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1705 = bits(intenable_reg_re_5, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1706 = bits(intenable_reg_re_6, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1707 = bits(intenable_reg_re_7, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1708 = bits(intenable_reg_re_8, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1709 = bits(intenable_reg_re_9, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1710 = bits(intenable_reg_re_10, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1711 = bits(intenable_reg_re_11, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1712 = bits(intenable_reg_re_12, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1713 = bits(intenable_reg_re_13, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1714 = bits(intenable_reg_re_14, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1715 = bits(intenable_reg_re_15, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1716 = bits(intenable_reg_re_16, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1717 = bits(intenable_reg_re_17, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1718 = bits(intenable_reg_re_18, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1719 = bits(intenable_reg_re_19, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1720 = bits(intenable_reg_re_20, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1721 = bits(intenable_reg_re_21, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1722 = bits(intenable_reg_re_22, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1723 = bits(intenable_reg_re_23, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1724 = bits(intenable_reg_re_24, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1725 = bits(intenable_reg_re_25, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1726 = bits(intenable_reg_re_26, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1727 = bits(intenable_reg_re_27, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1728 = bits(intenable_reg_re_28, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1729 = bits(intenable_reg_re_29, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1730 = bits(intenable_reg_re_30, 0, 0) @[pic_ctrl.scala 287:97] + node _T_1731 = bits(intenable_reg_re_31, 0, 0) @[pic_ctrl.scala 287:97] node _T_1732 = mux(_T_1731, intenable_reg[31], UInt<1>("h00")) @[Mux.scala 98:16] node _T_1733 = mux(_T_1730, intenable_reg[30], _T_1732) @[Mux.scala 98:16] node _T_1734 = mux(_T_1729, intenable_reg[29], _T_1733) @[Mux.scala 98:16] @@ -105993,37 +105990,37 @@ circuit quasar_wrapper : node _T_1761 = mux(_T_1702, intenable_reg[2], _T_1760) @[Mux.scala 98:16] node _T_1762 = mux(_T_1701, intenable_reg[1], _T_1761) @[Mux.scala 98:16] node intenable_rd_out = mux(UInt<1>("h00"), intenable_reg[0], _T_1762) @[Mux.scala 98:16] - node _T_1763 = bits(intpriority_reg_re_1, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1764 = bits(intpriority_reg_re_2, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1765 = bits(intpriority_reg_re_3, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1766 = bits(intpriority_reg_re_4, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1767 = bits(intpriority_reg_re_5, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1768 = bits(intpriority_reg_re_6, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1769 = bits(intpriority_reg_re_7, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1770 = bits(intpriority_reg_re_8, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1771 = bits(intpriority_reg_re_9, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1772 = bits(intpriority_reg_re_10, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1773 = bits(intpriority_reg_re_11, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1774 = bits(intpriority_reg_re_12, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1775 = bits(intpriority_reg_re_13, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1776 = bits(intpriority_reg_re_14, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1777 = bits(intpriority_reg_re_15, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1778 = bits(intpriority_reg_re_16, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1779 = bits(intpriority_reg_re_17, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1780 = bits(intpriority_reg_re_18, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1781 = bits(intpriority_reg_re_19, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1782 = bits(intpriority_reg_re_20, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1783 = bits(intpriority_reg_re_21, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1784 = bits(intpriority_reg_re_22, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1785 = bits(intpriority_reg_re_23, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1786 = bits(intpriority_reg_re_24, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1787 = bits(intpriority_reg_re_25, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1788 = bits(intpriority_reg_re_26, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1789 = bits(intpriority_reg_re_27, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1790 = bits(intpriority_reg_re_28, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1791 = bits(intpriority_reg_re_29, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1792 = bits(intpriority_reg_re_30, 0, 0) @[pic_ctrl.scala 287:102] - node _T_1793 = bits(intpriority_reg_re_31, 0, 0) @[pic_ctrl.scala 287:102] + node _T_1763 = bits(intpriority_reg_re_1, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1764 = bits(intpriority_reg_re_2, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1765 = bits(intpriority_reg_re_3, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1766 = bits(intpriority_reg_re_4, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1767 = bits(intpriority_reg_re_5, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1768 = bits(intpriority_reg_re_6, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1769 = bits(intpriority_reg_re_7, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1770 = bits(intpriority_reg_re_8, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1771 = bits(intpriority_reg_re_9, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1772 = bits(intpriority_reg_re_10, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1773 = bits(intpriority_reg_re_11, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1774 = bits(intpriority_reg_re_12, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1775 = bits(intpriority_reg_re_13, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1776 = bits(intpriority_reg_re_14, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1777 = bits(intpriority_reg_re_15, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1778 = bits(intpriority_reg_re_16, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1779 = bits(intpriority_reg_re_17, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1780 = bits(intpriority_reg_re_18, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1781 = bits(intpriority_reg_re_19, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1782 = bits(intpriority_reg_re_20, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1783 = bits(intpriority_reg_re_21, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1784 = bits(intpriority_reg_re_22, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1785 = bits(intpriority_reg_re_23, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1786 = bits(intpriority_reg_re_24, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1787 = bits(intpriority_reg_re_25, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1788 = bits(intpriority_reg_re_26, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1789 = bits(intpriority_reg_re_27, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1790 = bits(intpriority_reg_re_28, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1791 = bits(intpriority_reg_re_29, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1792 = bits(intpriority_reg_re_30, 0, 0) @[pic_ctrl.scala 288:102] + node _T_1793 = bits(intpriority_reg_re_31, 0, 0) @[pic_ctrl.scala 288:102] node _T_1794 = mux(_T_1793, intpriority_reg[31], UInt<1>("h00")) @[Mux.scala 98:16] node _T_1795 = mux(_T_1792, intpriority_reg[30], _T_1794) @[Mux.scala 98:16] node _T_1796 = mux(_T_1791, intpriority_reg[29], _T_1795) @[Mux.scala 98:16] @@ -106056,37 +106053,37 @@ circuit quasar_wrapper : node _T_1823 = mux(_T_1764, intpriority_reg[2], _T_1822) @[Mux.scala 98:16] node _T_1824 = mux(_T_1763, intpriority_reg[1], _T_1823) @[Mux.scala 98:16] node intpriority_rd_out = mux(UInt<1>("h00"), intpriority_reg[0], _T_1824) @[Mux.scala 98:16] - node _T_1825 = bits(gw_config_reg_re_1, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1826 = bits(gw_config_reg_re_2, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1827 = bits(gw_config_reg_re_3, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1828 = bits(gw_config_reg_re_4, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1829 = bits(gw_config_reg_re_5, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1830 = bits(gw_config_reg_re_6, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1831 = bits(gw_config_reg_re_7, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1832 = bits(gw_config_reg_re_8, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1833 = bits(gw_config_reg_re_9, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1834 = bits(gw_config_reg_re_10, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1835 = bits(gw_config_reg_re_11, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1836 = bits(gw_config_reg_re_12, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1837 = bits(gw_config_reg_re_13, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1838 = bits(gw_config_reg_re_14, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1839 = bits(gw_config_reg_re_15, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1840 = bits(gw_config_reg_re_16, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1841 = bits(gw_config_reg_re_17, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1842 = bits(gw_config_reg_re_18, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1843 = bits(gw_config_reg_re_19, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1844 = bits(gw_config_reg_re_20, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1845 = bits(gw_config_reg_re_21, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1846 = bits(gw_config_reg_re_22, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1847 = bits(gw_config_reg_re_23, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1848 = bits(gw_config_reg_re_24, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1849 = bits(gw_config_reg_re_25, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1850 = bits(gw_config_reg_re_26, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1851 = bits(gw_config_reg_re_27, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1852 = bits(gw_config_reg_re_28, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1853 = bits(gw_config_reg_re_29, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1854 = bits(gw_config_reg_re_30, 0, 0) @[pic_ctrl.scala 288:100] - node _T_1855 = bits(gw_config_reg_re_31, 0, 0) @[pic_ctrl.scala 288:100] + node _T_1825 = bits(gw_config_reg_re_1, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1826 = bits(gw_config_reg_re_2, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1827 = bits(gw_config_reg_re_3, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1828 = bits(gw_config_reg_re_4, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1829 = bits(gw_config_reg_re_5, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1830 = bits(gw_config_reg_re_6, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1831 = bits(gw_config_reg_re_7, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1832 = bits(gw_config_reg_re_8, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1833 = bits(gw_config_reg_re_9, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1834 = bits(gw_config_reg_re_10, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1835 = bits(gw_config_reg_re_11, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1836 = bits(gw_config_reg_re_12, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1837 = bits(gw_config_reg_re_13, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1838 = bits(gw_config_reg_re_14, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1839 = bits(gw_config_reg_re_15, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1840 = bits(gw_config_reg_re_16, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1841 = bits(gw_config_reg_re_17, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1842 = bits(gw_config_reg_re_18, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1843 = bits(gw_config_reg_re_19, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1844 = bits(gw_config_reg_re_20, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1845 = bits(gw_config_reg_re_21, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1846 = bits(gw_config_reg_re_22, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1847 = bits(gw_config_reg_re_23, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1848 = bits(gw_config_reg_re_24, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1849 = bits(gw_config_reg_re_25, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1850 = bits(gw_config_reg_re_26, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1851 = bits(gw_config_reg_re_27, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1852 = bits(gw_config_reg_re_28, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1853 = bits(gw_config_reg_re_29, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1854 = bits(gw_config_reg_re_30, 0, 0) @[pic_ctrl.scala 289:100] + node _T_1855 = bits(gw_config_reg_re_31, 0, 0) @[pic_ctrl.scala 289:100] node _T_1856 = mux(_T_1855, gw_config_reg[31], UInt<1>("h00")) @[Mux.scala 98:16] node _T_1857 = mux(_T_1854, gw_config_reg[30], _T_1856) @[Mux.scala 98:16] node _T_1858 = mux(_T_1853, gw_config_reg[29], _T_1857) @[Mux.scala 98:16] @@ -106121,37 +106118,37 @@ circuit quasar_wrapper : node gw_config_rd_out = mux(UInt<1>("h00"), gw_config_reg[0], _T_1886) @[Mux.scala 98:16] wire picm_rd_data_in : UInt<32> picm_rd_data_in <= UInt<1>("h00") - node _T_1887 = bits(intpend_reg_read, 0, 0) @[pic_ctrl.scala 293:22] - node _T_1888 = bits(intpriority_reg_read, 0, 0) @[pic_ctrl.scala 294:26] + node _T_1887 = bits(intpend_reg_read, 0, 0) @[pic_ctrl.scala 294:22] + node _T_1888 = bits(intpriority_reg_read, 0, 0) @[pic_ctrl.scala 295:26] node _T_1889 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] node _T_1890 = cat(_T_1889, intpriority_rd_out) @[Cat.scala 29:58] - node _T_1891 = bits(intenable_reg_read, 0, 0) @[pic_ctrl.scala 295:24] + node _T_1891 = bits(intenable_reg_read, 0, 0) @[pic_ctrl.scala 296:24] node _T_1892 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] node _T_1893 = cat(_T_1892, intenable_rd_out) @[Cat.scala 29:58] - node _T_1894 = bits(gw_config_reg_read, 0, 0) @[pic_ctrl.scala 296:24] + node _T_1894 = bits(gw_config_reg_read, 0, 0) @[pic_ctrl.scala 297:24] node _T_1895 = mux(UInt<1>("h00"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12] node _T_1896 = cat(_T_1895, gw_config_rd_out) @[Cat.scala 29:58] - node _T_1897 = bits(config_reg_re, 0, 0) @[pic_ctrl.scala 297:19] + node _T_1897 = bits(config_reg_re, 0, 0) @[pic_ctrl.scala 298:19] node _T_1898 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] node _T_1899 = cat(_T_1898, config_reg) @[Cat.scala 29:58] - node _T_1900 = bits(mask, 3, 3) @[pic_ctrl.scala 298:25] - node _T_1901 = and(picm_mken_ff, _T_1900) @[pic_ctrl.scala 298:19] - node _T_1902 = bits(_T_1901, 0, 0) @[pic_ctrl.scala 298:30] + node _T_1900 = bits(mask, 3, 3) @[pic_ctrl.scala 299:25] + node _T_1901 = and(picm_mken_ff, _T_1900) @[pic_ctrl.scala 299:19] + node _T_1902 = bits(_T_1901, 0, 0) @[pic_ctrl.scala 299:30] node _T_1903 = mux(UInt<1>("h00"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12] node _T_1904 = cat(_T_1903, UInt<2>("h03")) @[Cat.scala 29:58] - node _T_1905 = bits(mask, 2, 2) @[pic_ctrl.scala 299:25] - node _T_1906 = and(picm_mken_ff, _T_1905) @[pic_ctrl.scala 299:19] - node _T_1907 = bits(_T_1906, 0, 0) @[pic_ctrl.scala 299:30] + node _T_1905 = bits(mask, 2, 2) @[pic_ctrl.scala 300:25] + node _T_1906 = and(picm_mken_ff, _T_1905) @[pic_ctrl.scala 300:19] + node _T_1907 = bits(_T_1906, 0, 0) @[pic_ctrl.scala 300:30] node _T_1908 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] node _T_1909 = cat(_T_1908, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_1910 = bits(mask, 1, 1) @[pic_ctrl.scala 300:25] - node _T_1911 = and(picm_mken_ff, _T_1910) @[pic_ctrl.scala 300:19] - node _T_1912 = bits(_T_1911, 0, 0) @[pic_ctrl.scala 300:30] + node _T_1910 = bits(mask, 1, 1) @[pic_ctrl.scala 301:25] + node _T_1911 = and(picm_mken_ff, _T_1910) @[pic_ctrl.scala 301:19] + node _T_1912 = bits(_T_1911, 0, 0) @[pic_ctrl.scala 301:30] node _T_1913 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] node _T_1914 = cat(_T_1913, UInt<4>("h0f")) @[Cat.scala 29:58] - node _T_1915 = bits(mask, 0, 0) @[pic_ctrl.scala 301:25] - node _T_1916 = and(picm_mken_ff, _T_1915) @[pic_ctrl.scala 301:19] - node _T_1917 = bits(_T_1916, 0, 0) @[pic_ctrl.scala 301:30] + node _T_1915 = bits(mask, 0, 0) @[pic_ctrl.scala 302:25] + node _T_1916 = and(picm_mken_ff, _T_1915) @[pic_ctrl.scala 302:19] + node _T_1917 = bits(_T_1916, 0, 0) @[pic_ctrl.scala 302:30] node _T_1918 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] node _T_1919 = mux(_T_1887, intpend_rd_out, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1920 = mux(_T_1888, _T_1890, UInt<1>("h00")) @[Mux.scala 27:72] @@ -106172,480 +106169,480 @@ circuit quasar_wrapper : node _T_1935 = or(_T_1934, _T_1927) @[Mux.scala 27:72] wire _T_1936 : UInt<32> @[Mux.scala 27:72] _T_1936 <= _T_1935 @[Mux.scala 27:72] - picm_rd_data_in <= _T_1936 @[pic_ctrl.scala 292:19] - node _T_1937 = bits(picm_bypass_ff, 0, 0) @[pic_ctrl.scala 304:49] - node _T_1938 = mux(_T_1937, picm_wr_data_ff, picm_rd_data_in) @[pic_ctrl.scala 304:33] - io.lsu_pic.picm_rd_data <= _T_1938 @[pic_ctrl.scala 304:27] - node address = bits(picm_raddr_ff, 14, 0) @[pic_ctrl.scala 305:30] - mask <= UInt<4>("h01") @[pic_ctrl.scala 307:8] + picm_rd_data_in <= _T_1936 @[pic_ctrl.scala 293:19] + node _T_1937 = bits(picm_bypass_ff, 0, 0) @[pic_ctrl.scala 305:49] + node _T_1938 = mux(_T_1937, picm_wr_data_ff, picm_rd_data_in) @[pic_ctrl.scala 305:33] + io.lsu_pic.picm_rd_data <= _T_1938 @[pic_ctrl.scala 305:27] + node address = bits(picm_raddr_ff, 14, 0) @[pic_ctrl.scala 306:30] + mask <= UInt<4>("h01") @[pic_ctrl.scala 308:8] node _T_1939 = eq(UInt<15>("h03000"), address) @[Conditional.scala 37:30] when _T_1939 : @[Conditional.scala 40:58] - mask <= UInt<4>("h04") @[pic_ctrl.scala 309:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 310:44] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] node _T_1940 = eq(UInt<15>("h04004"), address) @[Conditional.scala 37:30] when _T_1940 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 310:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 311:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1941 = eq(UInt<15>("h04008"), address) @[Conditional.scala 37:30] when _T_1941 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 311:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 312:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1942 = eq(UInt<15>("h0400c"), address) @[Conditional.scala 37:30] when _T_1942 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 312:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 313:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1943 = eq(UInt<15>("h04010"), address) @[Conditional.scala 37:30] when _T_1943 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 313:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 314:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1944 = eq(UInt<15>("h04014"), address) @[Conditional.scala 37:30] when _T_1944 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 314:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 315:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1945 = eq(UInt<15>("h04018"), address) @[Conditional.scala 37:30] when _T_1945 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 315:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 316:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1946 = eq(UInt<15>("h0401c"), address) @[Conditional.scala 37:30] when _T_1946 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 316:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 317:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1947 = eq(UInt<15>("h04020"), address) @[Conditional.scala 37:30] when _T_1947 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 317:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 318:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1948 = eq(UInt<15>("h04024"), address) @[Conditional.scala 37:30] when _T_1948 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 318:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 319:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1949 = eq(UInt<15>("h04028"), address) @[Conditional.scala 37:30] when _T_1949 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 319:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 320:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1950 = eq(UInt<15>("h0402c"), address) @[Conditional.scala 37:30] when _T_1950 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 320:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 321:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1951 = eq(UInt<15>("h04030"), address) @[Conditional.scala 37:30] when _T_1951 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 321:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 322:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1952 = eq(UInt<15>("h04034"), address) @[Conditional.scala 37:30] when _T_1952 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 322:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 323:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1953 = eq(UInt<15>("h04038"), address) @[Conditional.scala 37:30] when _T_1953 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 323:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 324:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1954 = eq(UInt<15>("h0403c"), address) @[Conditional.scala 37:30] when _T_1954 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 324:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 325:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1955 = eq(UInt<15>("h04040"), address) @[Conditional.scala 37:30] when _T_1955 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 325:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 326:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1956 = eq(UInt<15>("h04044"), address) @[Conditional.scala 37:30] when _T_1956 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 326:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 327:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1957 = eq(UInt<15>("h04048"), address) @[Conditional.scala 37:30] when _T_1957 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 327:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 328:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1958 = eq(UInt<15>("h0404c"), address) @[Conditional.scala 37:30] when _T_1958 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 328:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 329:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1959 = eq(UInt<15>("h04050"), address) @[Conditional.scala 37:30] when _T_1959 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 329:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 330:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1960 = eq(UInt<15>("h04054"), address) @[Conditional.scala 37:30] when _T_1960 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 330:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 331:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1961 = eq(UInt<15>("h04058"), address) @[Conditional.scala 37:30] when _T_1961 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 331:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 332:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1962 = eq(UInt<15>("h0405c"), address) @[Conditional.scala 37:30] when _T_1962 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 332:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 333:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1963 = eq(UInt<15>("h04060"), address) @[Conditional.scala 37:30] when _T_1963 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 333:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 334:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1964 = eq(UInt<15>("h04064"), address) @[Conditional.scala 37:30] when _T_1964 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 334:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 335:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1965 = eq(UInt<15>("h04068"), address) @[Conditional.scala 37:30] when _T_1965 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 335:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 336:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1966 = eq(UInt<15>("h0406c"), address) @[Conditional.scala 37:30] when _T_1966 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 336:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 337:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1967 = eq(UInt<15>("h04070"), address) @[Conditional.scala 37:30] when _T_1967 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 337:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 338:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1968 = eq(UInt<15>("h04074"), address) @[Conditional.scala 37:30] when _T_1968 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 338:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 339:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1969 = eq(UInt<15>("h04078"), address) @[Conditional.scala 37:30] when _T_1969 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 339:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 340:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1970 = eq(UInt<15>("h0407c"), address) @[Conditional.scala 37:30] when _T_1970 : @[Conditional.scala 39:67] - mask <= UInt<4>("h08") @[pic_ctrl.scala 340:44] + mask <= UInt<4>("h08") @[pic_ctrl.scala 341:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1971 = eq(UInt<15>("h02004"), address) @[Conditional.scala 37:30] when _T_1971 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 341:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 342:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1972 = eq(UInt<15>("h02008"), address) @[Conditional.scala 37:30] when _T_1972 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 342:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 343:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1973 = eq(UInt<15>("h0200c"), address) @[Conditional.scala 37:30] when _T_1973 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 343:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 344:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1974 = eq(UInt<15>("h02010"), address) @[Conditional.scala 37:30] when _T_1974 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 344:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 345:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1975 = eq(UInt<15>("h02014"), address) @[Conditional.scala 37:30] when _T_1975 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 345:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 346:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1976 = eq(UInt<15>("h02018"), address) @[Conditional.scala 37:30] when _T_1976 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 346:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 347:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1977 = eq(UInt<15>("h0201c"), address) @[Conditional.scala 37:30] when _T_1977 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 347:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 348:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1978 = eq(UInt<15>("h02020"), address) @[Conditional.scala 37:30] when _T_1978 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 348:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 349:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1979 = eq(UInt<15>("h02024"), address) @[Conditional.scala 37:30] when _T_1979 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 349:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 350:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1980 = eq(UInt<15>("h02028"), address) @[Conditional.scala 37:30] when _T_1980 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 350:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 351:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1981 = eq(UInt<15>("h0202c"), address) @[Conditional.scala 37:30] when _T_1981 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 351:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 352:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1982 = eq(UInt<15>("h02030"), address) @[Conditional.scala 37:30] when _T_1982 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 352:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 353:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1983 = eq(UInt<15>("h02034"), address) @[Conditional.scala 37:30] when _T_1983 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 353:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 354:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1984 = eq(UInt<15>("h02038"), address) @[Conditional.scala 37:30] when _T_1984 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 354:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 355:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1985 = eq(UInt<15>("h0203c"), address) @[Conditional.scala 37:30] when _T_1985 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 355:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 356:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1986 = eq(UInt<15>("h02040"), address) @[Conditional.scala 37:30] when _T_1986 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 356:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 357:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1987 = eq(UInt<15>("h02044"), address) @[Conditional.scala 37:30] when _T_1987 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 357:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 358:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1988 = eq(UInt<15>("h02048"), address) @[Conditional.scala 37:30] when _T_1988 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 358:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 359:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1989 = eq(UInt<15>("h0204c"), address) @[Conditional.scala 37:30] when _T_1989 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 359:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 360:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1990 = eq(UInt<15>("h02050"), address) @[Conditional.scala 37:30] when _T_1990 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 360:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 361:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1991 = eq(UInt<15>("h02054"), address) @[Conditional.scala 37:30] when _T_1991 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 361:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 362:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1992 = eq(UInt<15>("h02058"), address) @[Conditional.scala 37:30] when _T_1992 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 362:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 363:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1993 = eq(UInt<15>("h0205c"), address) @[Conditional.scala 37:30] when _T_1993 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 363:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 364:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1994 = eq(UInt<15>("h02060"), address) @[Conditional.scala 37:30] when _T_1994 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 364:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 365:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1995 = eq(UInt<15>("h02064"), address) @[Conditional.scala 37:30] when _T_1995 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 365:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 366:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1996 = eq(UInt<15>("h02068"), address) @[Conditional.scala 37:30] when _T_1996 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 366:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 367:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1997 = eq(UInt<15>("h0206c"), address) @[Conditional.scala 37:30] when _T_1997 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 367:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 368:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1998 = eq(UInt<15>("h02070"), address) @[Conditional.scala 37:30] when _T_1998 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 368:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 369:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_1999 = eq(UInt<15>("h02074"), address) @[Conditional.scala 37:30] when _T_1999 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 369:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 370:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2000 = eq(UInt<15>("h02078"), address) @[Conditional.scala 37:30] when _T_2000 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 370:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 371:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2001 = eq(UInt<15>("h0207c"), address) @[Conditional.scala 37:30] when _T_2001 : @[Conditional.scala 39:67] - mask <= UInt<4>("h04") @[pic_ctrl.scala 371:44] + mask <= UInt<4>("h04") @[pic_ctrl.scala 372:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2002 = eq(UInt<15>("h04"), address) @[Conditional.scala 37:30] when _T_2002 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 372:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 373:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2003 = eq(UInt<15>("h08"), address) @[Conditional.scala 37:30] when _T_2003 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 373:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 374:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2004 = eq(UInt<15>("h0c"), address) @[Conditional.scala 37:30] when _T_2004 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 374:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 375:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2005 = eq(UInt<15>("h010"), address) @[Conditional.scala 37:30] when _T_2005 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 375:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 376:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2006 = eq(UInt<15>("h014"), address) @[Conditional.scala 37:30] when _T_2006 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 376:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 377:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2007 = eq(UInt<15>("h018"), address) @[Conditional.scala 37:30] when _T_2007 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 377:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 378:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2008 = eq(UInt<15>("h01c"), address) @[Conditional.scala 37:30] when _T_2008 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 378:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 379:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2009 = eq(UInt<15>("h020"), address) @[Conditional.scala 37:30] when _T_2009 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 379:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 380:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2010 = eq(UInt<15>("h024"), address) @[Conditional.scala 37:30] when _T_2010 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 380:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 381:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2011 = eq(UInt<15>("h028"), address) @[Conditional.scala 37:30] when _T_2011 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 381:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 382:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2012 = eq(UInt<15>("h02c"), address) @[Conditional.scala 37:30] when _T_2012 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 382:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 383:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2013 = eq(UInt<15>("h030"), address) @[Conditional.scala 37:30] when _T_2013 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 383:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 384:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2014 = eq(UInt<15>("h034"), address) @[Conditional.scala 37:30] when _T_2014 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 384:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 385:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2015 = eq(UInt<15>("h038"), address) @[Conditional.scala 37:30] when _T_2015 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 385:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 386:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2016 = eq(UInt<15>("h03c"), address) @[Conditional.scala 37:30] when _T_2016 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 386:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 387:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2017 = eq(UInt<15>("h040"), address) @[Conditional.scala 37:30] when _T_2017 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 387:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 388:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2018 = eq(UInt<15>("h044"), address) @[Conditional.scala 37:30] when _T_2018 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 388:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 389:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2019 = eq(UInt<15>("h048"), address) @[Conditional.scala 37:30] when _T_2019 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 389:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 390:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2020 = eq(UInt<15>("h04c"), address) @[Conditional.scala 37:30] when _T_2020 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 390:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 391:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2021 = eq(UInt<15>("h050"), address) @[Conditional.scala 37:30] when _T_2021 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 391:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 392:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2022 = eq(UInt<15>("h054"), address) @[Conditional.scala 37:30] when _T_2022 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 392:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 393:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2023 = eq(UInt<15>("h058"), address) @[Conditional.scala 37:30] when _T_2023 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 393:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 394:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2024 = eq(UInt<15>("h05c"), address) @[Conditional.scala 37:30] when _T_2024 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 394:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 395:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2025 = eq(UInt<15>("h060"), address) @[Conditional.scala 37:30] when _T_2025 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 395:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 396:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2026 = eq(UInt<15>("h064"), address) @[Conditional.scala 37:30] when _T_2026 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 396:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 397:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2027 = eq(UInt<15>("h068"), address) @[Conditional.scala 37:30] when _T_2027 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 397:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 398:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2028 = eq(UInt<15>("h06c"), address) @[Conditional.scala 37:30] when _T_2028 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 398:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 399:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2029 = eq(UInt<15>("h070"), address) @[Conditional.scala 37:30] when _T_2029 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 399:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 400:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2030 = eq(UInt<15>("h074"), address) @[Conditional.scala 37:30] when _T_2030 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 400:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 401:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2031 = eq(UInt<15>("h078"), address) @[Conditional.scala 37:30] when _T_2031 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 401:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 402:44] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] node _T_2032 = eq(UInt<15>("h07c"), address) @[Conditional.scala 37:30] when _T_2032 : @[Conditional.scala 39:67] - mask <= UInt<4>("h02") @[pic_ctrl.scala 402:44] + mask <= UInt<4>("h02") @[pic_ctrl.scala 403:44] skip @[Conditional.scala 39:67] extmodule gated_latch_829 : @@ -107035,24 +107032,24 @@ circuit quasar_wrapper : module dma_ctrl : input clock : Clock input reset : AsyncReset - output io : {flip free_clk : Clock, flip dma_bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>, flip dbg_cmd_size : UInt<2>, dma_dbg_rddata : UInt<32>, dma_dbg_cmd_done : UInt<1>, dma_dbg_cmd_fail : UInt<1>, dbg_dma : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}}, dbg_dma_io : {flip dbg_dma_bubble : UInt<1>, dma_dbg_ready : UInt<1>}, flip iccm_dma_rvalid : UInt<1>, flip iccm_dma_ecc_error : UInt<1>, flip iccm_dma_rtag : UInt<3>, flip iccm_dma_rdata : UInt<64>, dma_dccm_stall_any : UInt<1>, flip iccm_ready : UInt<1>, flip dec_tlu_dma_qos_prty : UInt<3>, dma_pmu_dccm_read : UInt<1>, dma_pmu_dccm_write : UInt<1>, dma_pmu_any_read : UInt<1>, dma_pmu_any_write : UInt<1>, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_dma : {dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, dma_dccm_ctl : {flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>}, dccm_ready : UInt<1>, flip dma_mem_tag : UInt<3>}, flip ifu_dma : {dma_ifc : {flip dma_iccm_stall_any : UInt<1>}, dma_mem_ctl : {flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>}}} + output io : {flip free_clk : Clock, flip dma_bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>, flip dbg_cmd_size : UInt<2>, dma_dbg_rddata : UInt<32>, dma_dbg_cmd_done : UInt<1>, dma_dbg_cmd_fail : UInt<1>, dbg_dma : {dbg_ib : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>}, dbg_dctl : {flip dbg_cmd_wrdata : UInt<2>}}, dbg_dma_io : {flip dbg_dma_bubble : UInt<1>, dma_dbg_ready : UInt<1>}, flip dec_dma : {dctl_dma : {flip dma_dccm_stall_any : UInt<1>}, tlu_dma : {flip dma_pmu_dccm_read : UInt<1>, flip dma_pmu_dccm_write : UInt<1>, flip dma_pmu_any_read : UInt<1>, flip dma_pmu_any_write : UInt<1>, dec_tlu_dma_qos_prty : UInt<3>, flip dma_dccm_stall_any : UInt<1>, flip dma_iccm_stall_any : UInt<1>}}, flip iccm_dma_rvalid : UInt<1>, flip iccm_dma_ecc_error : UInt<1>, flip iccm_dma_rtag : UInt<3>, flip iccm_dma_rdata : UInt<64>, flip iccm_ready : UInt<1>, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_dma : {dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, dma_dccm_ctl : {flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>}, dccm_ready : UInt<1>, flip dma_mem_tag : UInt<3>}, flip ifu_dma : {dma_ifc : {flip dma_iccm_stall_any : UInt<1>}, dma_mem_ctl : {flip dma_iccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, flip dma_mem_tag : UInt<3>}}} - wire fifo_error : UInt<2>[5] @[dma_ctrl.scala 42:24] + wire fifo_error : UInt<2>[5] @[dma_ctrl.scala 36:24] wire fifo_error_bus : UInt<5> fifo_error_bus <= UInt<1>("h00") wire fifo_done : UInt<5> fifo_done <= UInt<1>("h00") - wire fifo_addr : UInt<32>[5] @[dma_ctrl.scala 48:23] - wire fifo_sz : UInt<3>[5] @[dma_ctrl.scala 50:21] - wire fifo_byteen : UInt<8>[5] @[dma_ctrl.scala 52:25] - wire fifo_data : UInt<64>[5] @[dma_ctrl.scala 54:23] - wire fifo_tag : UInt<1>[5] @[dma_ctrl.scala 56:22] - wire fifo_mid : UInt<1>[5] @[dma_ctrl.scala 58:22] - wire fifo_prty : UInt<2>[5] @[dma_ctrl.scala 60:23] + wire fifo_addr : UInt<32>[5] @[dma_ctrl.scala 42:23] + wire fifo_sz : UInt<3>[5] @[dma_ctrl.scala 44:21] + wire fifo_byteen : UInt<8>[5] @[dma_ctrl.scala 46:25] + wire fifo_data : UInt<64>[5] @[dma_ctrl.scala 48:23] + wire fifo_tag : UInt<1>[5] @[dma_ctrl.scala 50:22] + wire fifo_mid : UInt<1>[5] @[dma_ctrl.scala 52:22] + wire fifo_prty : UInt<2>[5] @[dma_ctrl.scala 54:23] wire fifo_error_en : UInt<5> fifo_error_en <= UInt<1>("h00") - wire fifo_error_in : UInt<2>[5] @[dma_ctrl.scala 64:27] - wire fifo_data_in : UInt<64>[5] @[dma_ctrl.scala 66:26] + wire fifo_error_in : UInt<2>[5] @[dma_ctrl.scala 58:27] + wire fifo_data_in : UInt<64>[5] @[dma_ctrl.scala 60:26] wire RspPtr : UInt<3> RspPtr <= UInt<1>("h00") wire WrPtr : UInt<3> @@ -107159,888 +107156,888 @@ circuit quasar_wrapper : wrbuf_data_vld <= UInt<1>("h00") wire rdbuf_vld : UInt<1> rdbuf_vld <= UInt<1>("h00") - wire dma_free_clk : Clock @[dma_ctrl.scala 174:26] - wire dma_bus_clk : Clock @[dma_ctrl.scala 176:25] - wire dma_buffer_c1_clk : Clock @[dma_ctrl.scala 178:31] + wire dma_free_clk : Clock @[dma_ctrl.scala 168:26] + wire dma_bus_clk : Clock @[dma_ctrl.scala 170:25] + wire dma_buffer_c1_clk : Clock @[dma_ctrl.scala 172:31] wire fifo_byteen_in : UInt<8> fifo_byteen_in <= UInt<1>("h00") - node _T = bits(dma_mem_addr_int, 31, 0) @[dma_ctrl.scala 187:95] + node _T = bits(dma_mem_addr_int, 31, 0) @[dma_ctrl.scala 181:95] node _T_1 = bits(_T, 31, 28) @[lib.scala 340:27] node dma_mem_addr_in_dccm_region_nc = eq(_T_1, UInt<4>("h0f")) @[lib.scala 340:49] wire dma_mem_addr_in_dccm : UInt<1> @[lib.scala 341:26] node _T_2 = bits(_T, 31, 16) @[lib.scala 345:24] node _T_3 = eq(_T_2, UInt<16>("h0f004")) @[lib.scala 345:39] dma_mem_addr_in_dccm <= _T_3 @[lib.scala 345:16] - node _T_4 = bits(dma_mem_addr_int, 31, 0) @[dma_ctrl.scala 191:93] + node _T_4 = bits(dma_mem_addr_int, 31, 0) @[dma_ctrl.scala 185:93] node _T_5 = bits(_T_4, 31, 28) @[lib.scala 340:27] node dma_mem_addr_in_pic_region_nc = eq(_T_5, UInt<4>("h0f")) @[lib.scala 340:49] wire dma_mem_addr_in_pic : UInt<1> @[lib.scala 341:26] node _T_6 = bits(_T_4, 31, 15) @[lib.scala 345:24] node _T_7 = eq(_T_6, UInt<17>("h01e018")) @[lib.scala 345:39] dma_mem_addr_in_pic <= _T_7 @[lib.scala 345:16] - node _T_8 = bits(dma_mem_addr_int, 31, 0) @[dma_ctrl.scala 195:111] + node _T_8 = bits(dma_mem_addr_int, 31, 0) @[dma_ctrl.scala 189:111] node _T_9 = bits(_T_8, 31, 28) @[lib.scala 340:27] node dma_mem_addr_in_iccm_region_nc = eq(_T_9, UInt<4>("h0e")) @[lib.scala 340:49] wire dma_mem_addr_in_iccm : UInt<1> @[lib.scala 341:26] node _T_10 = bits(_T_8, 31, 16) @[lib.scala 345:24] node _T_11 = eq(_T_10, UInt<16>("h0ee00")) @[lib.scala 345:39] dma_mem_addr_in_iccm <= _T_11 @[lib.scala 345:16] - node _T_12 = bits(io.dbg_dma.dbg_ib.dbg_cmd_valid, 0, 0) @[dma_ctrl.scala 199:66] - node _T_13 = bits(io.dbg_dma.dbg_ib.dbg_cmd_addr, 31, 0) @[dma_ctrl.scala 199:104] - node _T_14 = bits(bus_cmd_addr, 31, 0) @[dma_ctrl.scala 199:124] - node fifo_addr_in = mux(_T_12, _T_13, _T_14) @[dma_ctrl.scala 199:33] - node _T_15 = bits(io.dbg_dma.dbg_ib.dbg_cmd_valid, 0, 0) @[dma_ctrl.scala 201:67] - node _T_16 = bits(io.dbg_dma.dbg_ib.dbg_cmd_addr, 2, 2) @[dma_ctrl.scala 201:123] - node _T_17 = mul(UInt<3>("h04"), _T_16) @[dma_ctrl.scala 201:91] - node _T_18 = dshl(UInt<4>("h0f"), _T_17) @[dma_ctrl.scala 201:83] - node _T_19 = bits(bus_cmd_byteen, 7, 0) @[dma_ctrl.scala 201:143] - node _T_20 = mux(_T_15, _T_18, _T_19) @[dma_ctrl.scala 201:34] - fifo_byteen_in <= _T_20 @[dma_ctrl.scala 201:28] - node _T_21 = bits(io.dbg_dma.dbg_ib.dbg_cmd_valid, 0, 0) @[dma_ctrl.scala 203:66] - node _T_22 = bits(io.dbg_cmd_size, 1, 0) @[dma_ctrl.scala 203:98] + node _T_12 = bits(io.dbg_dma.dbg_ib.dbg_cmd_valid, 0, 0) @[dma_ctrl.scala 193:66] + node _T_13 = bits(io.dbg_dma.dbg_ib.dbg_cmd_addr, 31, 0) @[dma_ctrl.scala 193:104] + node _T_14 = bits(bus_cmd_addr, 31, 0) @[dma_ctrl.scala 193:124] + node fifo_addr_in = mux(_T_12, _T_13, _T_14) @[dma_ctrl.scala 193:33] + node _T_15 = bits(io.dbg_dma.dbg_ib.dbg_cmd_valid, 0, 0) @[dma_ctrl.scala 195:67] + node _T_16 = bits(io.dbg_dma.dbg_ib.dbg_cmd_addr, 2, 2) @[dma_ctrl.scala 195:123] + node _T_17 = mul(UInt<3>("h04"), _T_16) @[dma_ctrl.scala 195:91] + node _T_18 = dshl(UInt<4>("h0f"), _T_17) @[dma_ctrl.scala 195:83] + node _T_19 = bits(bus_cmd_byteen, 7, 0) @[dma_ctrl.scala 195:143] + node _T_20 = mux(_T_15, _T_18, _T_19) @[dma_ctrl.scala 195:34] + fifo_byteen_in <= _T_20 @[dma_ctrl.scala 195:28] + node _T_21 = bits(io.dbg_dma.dbg_ib.dbg_cmd_valid, 0, 0) @[dma_ctrl.scala 197:66] + node _T_22 = bits(io.dbg_cmd_size, 1, 0) @[dma_ctrl.scala 197:98] node _T_23 = cat(UInt<1>("h00"), _T_22) @[Cat.scala 29:58] - node _T_24 = bits(bus_cmd_sz, 2, 0) @[dma_ctrl.scala 203:116] - node fifo_sz_in = mux(_T_21, _T_23, _T_24) @[dma_ctrl.scala 203:33] - node _T_25 = bits(io.dbg_dma.dbg_ib.dbg_cmd_valid, 0, 0) @[dma_ctrl.scala 205:66] - node fifo_write_in = mux(_T_25, io.dbg_dma.dbg_ib.dbg_cmd_write, bus_cmd_write) @[dma_ctrl.scala 205:33] - node _T_26 = eq(io.dbg_dma.dbg_ib.dbg_cmd_valid, UInt<1>("h00")) @[dma_ctrl.scala 207:30] - node fifo_posted_write_in = and(_T_26, bus_cmd_posted_write) @[dma_ctrl.scala 207:63] - node _T_27 = bits(axi_mstr_prty_en, 0, 0) @[dma_ctrl.scala 212:73] - node _T_28 = and(_T_27, io.dma_bus_clk_en) @[dma_ctrl.scala 212:80] - node _T_29 = bits(io.dbg_dma.dbg_ib.dbg_cmd_type, 1, 1) @[dma_ctrl.scala 212:168] - node _T_30 = bits(_T_29, 0, 0) @[dma_ctrl.scala 212:172] - node _T_31 = and(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_30) @[dma_ctrl.scala 212:136] - node _T_32 = or(_T_28, _T_31) @[dma_ctrl.scala 212:101] - node _T_33 = eq(UInt<1>("h00"), WrPtr) @[dma_ctrl.scala 212:188] - node _T_34 = and(_T_32, _T_33) @[dma_ctrl.scala 212:181] - node _T_35 = bits(axi_mstr_prty_en, 0, 0) @[dma_ctrl.scala 212:73] - node _T_36 = and(_T_35, io.dma_bus_clk_en) @[dma_ctrl.scala 212:80] - node _T_37 = bits(io.dbg_dma.dbg_ib.dbg_cmd_type, 1, 1) @[dma_ctrl.scala 212:168] - node _T_38 = bits(_T_37, 0, 0) @[dma_ctrl.scala 212:172] - node _T_39 = and(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_38) @[dma_ctrl.scala 212:136] - node _T_40 = or(_T_36, _T_39) @[dma_ctrl.scala 212:101] - node _T_41 = eq(UInt<1>("h01"), WrPtr) @[dma_ctrl.scala 212:188] - node _T_42 = and(_T_40, _T_41) @[dma_ctrl.scala 212:181] - node _T_43 = bits(axi_mstr_prty_en, 0, 0) @[dma_ctrl.scala 212:73] - node _T_44 = and(_T_43, io.dma_bus_clk_en) @[dma_ctrl.scala 212:80] - node _T_45 = bits(io.dbg_dma.dbg_ib.dbg_cmd_type, 1, 1) @[dma_ctrl.scala 212:168] - node _T_46 = bits(_T_45, 0, 0) @[dma_ctrl.scala 212:172] - node _T_47 = and(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_46) @[dma_ctrl.scala 212:136] - node _T_48 = or(_T_44, _T_47) @[dma_ctrl.scala 212:101] - node _T_49 = eq(UInt<2>("h02"), WrPtr) @[dma_ctrl.scala 212:188] - node _T_50 = and(_T_48, _T_49) @[dma_ctrl.scala 212:181] - node _T_51 = bits(axi_mstr_prty_en, 0, 0) @[dma_ctrl.scala 212:73] - node _T_52 = and(_T_51, io.dma_bus_clk_en) @[dma_ctrl.scala 212:80] - node _T_53 = bits(io.dbg_dma.dbg_ib.dbg_cmd_type, 1, 1) @[dma_ctrl.scala 212:168] - node _T_54 = bits(_T_53, 0, 0) @[dma_ctrl.scala 212:172] - node _T_55 = and(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_54) @[dma_ctrl.scala 212:136] - node _T_56 = or(_T_52, _T_55) @[dma_ctrl.scala 212:101] - node _T_57 = eq(UInt<2>("h03"), WrPtr) @[dma_ctrl.scala 212:188] - node _T_58 = and(_T_56, _T_57) @[dma_ctrl.scala 212:181] - node _T_59 = bits(axi_mstr_prty_en, 0, 0) @[dma_ctrl.scala 212:73] - node _T_60 = and(_T_59, io.dma_bus_clk_en) @[dma_ctrl.scala 212:80] - node _T_61 = bits(io.dbg_dma.dbg_ib.dbg_cmd_type, 1, 1) @[dma_ctrl.scala 212:168] - node _T_62 = bits(_T_61, 0, 0) @[dma_ctrl.scala 212:172] - node _T_63 = and(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_62) @[dma_ctrl.scala 212:136] - node _T_64 = or(_T_60, _T_63) @[dma_ctrl.scala 212:101] - node _T_65 = eq(UInt<3>("h04"), WrPtr) @[dma_ctrl.scala 212:188] - node _T_66 = and(_T_64, _T_65) @[dma_ctrl.scala 212:181] + node _T_24 = bits(bus_cmd_sz, 2, 0) @[dma_ctrl.scala 197:116] + node fifo_sz_in = mux(_T_21, _T_23, _T_24) @[dma_ctrl.scala 197:33] + node _T_25 = bits(io.dbg_dma.dbg_ib.dbg_cmd_valid, 0, 0) @[dma_ctrl.scala 199:66] + node fifo_write_in = mux(_T_25, io.dbg_dma.dbg_ib.dbg_cmd_write, bus_cmd_write) @[dma_ctrl.scala 199:33] + node _T_26 = eq(io.dbg_dma.dbg_ib.dbg_cmd_valid, UInt<1>("h00")) @[dma_ctrl.scala 201:30] + node fifo_posted_write_in = and(_T_26, bus_cmd_posted_write) @[dma_ctrl.scala 201:63] + node _T_27 = bits(axi_mstr_prty_en, 0, 0) @[dma_ctrl.scala 206:73] + node _T_28 = and(_T_27, io.dma_bus_clk_en) @[dma_ctrl.scala 206:80] + node _T_29 = bits(io.dbg_dma.dbg_ib.dbg_cmd_type, 1, 1) @[dma_ctrl.scala 206:168] + node _T_30 = bits(_T_29, 0, 0) @[dma_ctrl.scala 206:172] + node _T_31 = and(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_30) @[dma_ctrl.scala 206:136] + node _T_32 = or(_T_28, _T_31) @[dma_ctrl.scala 206:101] + node _T_33 = eq(UInt<1>("h00"), WrPtr) @[dma_ctrl.scala 206:188] + node _T_34 = and(_T_32, _T_33) @[dma_ctrl.scala 206:181] + node _T_35 = bits(axi_mstr_prty_en, 0, 0) @[dma_ctrl.scala 206:73] + node _T_36 = and(_T_35, io.dma_bus_clk_en) @[dma_ctrl.scala 206:80] + node _T_37 = bits(io.dbg_dma.dbg_ib.dbg_cmd_type, 1, 1) @[dma_ctrl.scala 206:168] + node _T_38 = bits(_T_37, 0, 0) @[dma_ctrl.scala 206:172] + node _T_39 = and(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_38) @[dma_ctrl.scala 206:136] + node _T_40 = or(_T_36, _T_39) @[dma_ctrl.scala 206:101] + node _T_41 = eq(UInt<1>("h01"), WrPtr) @[dma_ctrl.scala 206:188] + node _T_42 = and(_T_40, _T_41) @[dma_ctrl.scala 206:181] + node _T_43 = bits(axi_mstr_prty_en, 0, 0) @[dma_ctrl.scala 206:73] + node _T_44 = and(_T_43, io.dma_bus_clk_en) @[dma_ctrl.scala 206:80] + node _T_45 = bits(io.dbg_dma.dbg_ib.dbg_cmd_type, 1, 1) @[dma_ctrl.scala 206:168] + node _T_46 = bits(_T_45, 0, 0) @[dma_ctrl.scala 206:172] + node _T_47 = and(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_46) @[dma_ctrl.scala 206:136] + node _T_48 = or(_T_44, _T_47) @[dma_ctrl.scala 206:101] + node _T_49 = eq(UInt<2>("h02"), WrPtr) @[dma_ctrl.scala 206:188] + node _T_50 = and(_T_48, _T_49) @[dma_ctrl.scala 206:181] + node _T_51 = bits(axi_mstr_prty_en, 0, 0) @[dma_ctrl.scala 206:73] + node _T_52 = and(_T_51, io.dma_bus_clk_en) @[dma_ctrl.scala 206:80] + node _T_53 = bits(io.dbg_dma.dbg_ib.dbg_cmd_type, 1, 1) @[dma_ctrl.scala 206:168] + node _T_54 = bits(_T_53, 0, 0) @[dma_ctrl.scala 206:172] + node _T_55 = and(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_54) @[dma_ctrl.scala 206:136] + node _T_56 = or(_T_52, _T_55) @[dma_ctrl.scala 206:101] + node _T_57 = eq(UInt<2>("h03"), WrPtr) @[dma_ctrl.scala 206:188] + node _T_58 = and(_T_56, _T_57) @[dma_ctrl.scala 206:181] + node _T_59 = bits(axi_mstr_prty_en, 0, 0) @[dma_ctrl.scala 206:73] + node _T_60 = and(_T_59, io.dma_bus_clk_en) @[dma_ctrl.scala 206:80] + node _T_61 = bits(io.dbg_dma.dbg_ib.dbg_cmd_type, 1, 1) @[dma_ctrl.scala 206:168] + node _T_62 = bits(_T_61, 0, 0) @[dma_ctrl.scala 206:172] + node _T_63 = and(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_62) @[dma_ctrl.scala 206:136] + node _T_64 = or(_T_60, _T_63) @[dma_ctrl.scala 206:101] + node _T_65 = eq(UInt<3>("h04"), WrPtr) @[dma_ctrl.scala 206:188] + node _T_66 = and(_T_64, _T_65) @[dma_ctrl.scala 206:181] node _T_67 = cat(_T_66, _T_58) @[Cat.scala 29:58] node _T_68 = cat(_T_67, _T_50) @[Cat.scala 29:58] node _T_69 = cat(_T_68, _T_42) @[Cat.scala 29:58] node _T_70 = cat(_T_69, _T_34) @[Cat.scala 29:58] - fifo_cmd_en <= _T_70 @[dma_ctrl.scala 212:21] - node _T_71 = and(axi_mstr_prty_en, fifo_write_in) @[dma_ctrl.scala 214:73] - node _T_72 = and(_T_71, io.dma_bus_clk_en) @[dma_ctrl.scala 214:89] - node _T_73 = bits(io.dbg_dma.dbg_ib.dbg_cmd_type, 1, 1) @[dma_ctrl.scala 214:177] - node _T_74 = and(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_73) @[dma_ctrl.scala 214:145] - node _T_75 = and(_T_74, io.dbg_dma.dbg_ib.dbg_cmd_write) @[dma_ctrl.scala 214:181] - node _T_76 = or(_T_72, _T_75) @[dma_ctrl.scala 214:110] - node _T_77 = eq(UInt<1>("h00"), WrPtr) @[dma_ctrl.scala 214:224] - node _T_78 = and(_T_76, _T_77) @[dma_ctrl.scala 214:217] - node _T_79 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 214:258] - node _T_80 = eq(UInt<1>("h00"), RdPtr) @[dma_ctrl.scala 214:288] - node _T_81 = and(_T_79, _T_80) @[dma_ctrl.scala 214:281] - node _T_82 = or(_T_78, _T_81) @[dma_ctrl.scala 214:236] - node _T_83 = eq(UInt<1>("h00"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 214:350] - node _T_84 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_83) @[dma_ctrl.scala 214:343] - node _T_85 = or(_T_82, _T_84) @[dma_ctrl.scala 214:300] - node _T_86 = eq(UInt<1>("h00"), io.iccm_dma_rtag) @[dma_ctrl.scala 214:423] - node _T_87 = and(io.iccm_dma_rvalid, _T_86) @[dma_ctrl.scala 214:416] - node _T_88 = or(_T_85, _T_87) @[dma_ctrl.scala 214:394] - node _T_89 = and(axi_mstr_prty_en, fifo_write_in) @[dma_ctrl.scala 214:73] - node _T_90 = and(_T_89, io.dma_bus_clk_en) @[dma_ctrl.scala 214:89] - node _T_91 = bits(io.dbg_dma.dbg_ib.dbg_cmd_type, 1, 1) @[dma_ctrl.scala 214:177] - node _T_92 = and(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_91) @[dma_ctrl.scala 214:145] - node _T_93 = and(_T_92, io.dbg_dma.dbg_ib.dbg_cmd_write) @[dma_ctrl.scala 214:181] - node _T_94 = or(_T_90, _T_93) @[dma_ctrl.scala 214:110] - node _T_95 = eq(UInt<1>("h01"), WrPtr) @[dma_ctrl.scala 214:224] - node _T_96 = and(_T_94, _T_95) @[dma_ctrl.scala 214:217] - node _T_97 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 214:258] - node _T_98 = eq(UInt<1>("h01"), RdPtr) @[dma_ctrl.scala 214:288] - node _T_99 = and(_T_97, _T_98) @[dma_ctrl.scala 214:281] - node _T_100 = or(_T_96, _T_99) @[dma_ctrl.scala 214:236] - node _T_101 = eq(UInt<1>("h01"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 214:350] - node _T_102 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_101) @[dma_ctrl.scala 214:343] - node _T_103 = or(_T_100, _T_102) @[dma_ctrl.scala 214:300] - node _T_104 = eq(UInt<1>("h01"), io.iccm_dma_rtag) @[dma_ctrl.scala 214:423] - node _T_105 = and(io.iccm_dma_rvalid, _T_104) @[dma_ctrl.scala 214:416] - node _T_106 = or(_T_103, _T_105) @[dma_ctrl.scala 214:394] - node _T_107 = and(axi_mstr_prty_en, fifo_write_in) @[dma_ctrl.scala 214:73] - node _T_108 = and(_T_107, io.dma_bus_clk_en) @[dma_ctrl.scala 214:89] - node _T_109 = bits(io.dbg_dma.dbg_ib.dbg_cmd_type, 1, 1) @[dma_ctrl.scala 214:177] - node _T_110 = and(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_109) @[dma_ctrl.scala 214:145] - node _T_111 = and(_T_110, io.dbg_dma.dbg_ib.dbg_cmd_write) @[dma_ctrl.scala 214:181] - node _T_112 = or(_T_108, _T_111) @[dma_ctrl.scala 214:110] - node _T_113 = eq(UInt<2>("h02"), WrPtr) @[dma_ctrl.scala 214:224] - node _T_114 = and(_T_112, _T_113) @[dma_ctrl.scala 214:217] - node _T_115 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 214:258] - node _T_116 = eq(UInt<2>("h02"), RdPtr) @[dma_ctrl.scala 214:288] - node _T_117 = and(_T_115, _T_116) @[dma_ctrl.scala 214:281] - node _T_118 = or(_T_114, _T_117) @[dma_ctrl.scala 214:236] - node _T_119 = eq(UInt<2>("h02"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 214:350] - node _T_120 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_119) @[dma_ctrl.scala 214:343] - node _T_121 = or(_T_118, _T_120) @[dma_ctrl.scala 214:300] - node _T_122 = eq(UInt<2>("h02"), io.iccm_dma_rtag) @[dma_ctrl.scala 214:423] - node _T_123 = and(io.iccm_dma_rvalid, _T_122) @[dma_ctrl.scala 214:416] - node _T_124 = or(_T_121, _T_123) @[dma_ctrl.scala 214:394] - node _T_125 = and(axi_mstr_prty_en, fifo_write_in) @[dma_ctrl.scala 214:73] - node _T_126 = and(_T_125, io.dma_bus_clk_en) @[dma_ctrl.scala 214:89] - node _T_127 = bits(io.dbg_dma.dbg_ib.dbg_cmd_type, 1, 1) @[dma_ctrl.scala 214:177] - node _T_128 = and(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_127) @[dma_ctrl.scala 214:145] - node _T_129 = and(_T_128, io.dbg_dma.dbg_ib.dbg_cmd_write) @[dma_ctrl.scala 214:181] - node _T_130 = or(_T_126, _T_129) @[dma_ctrl.scala 214:110] - node _T_131 = eq(UInt<2>("h03"), WrPtr) @[dma_ctrl.scala 214:224] - node _T_132 = and(_T_130, _T_131) @[dma_ctrl.scala 214:217] - node _T_133 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 214:258] - node _T_134 = eq(UInt<2>("h03"), RdPtr) @[dma_ctrl.scala 214:288] - node _T_135 = and(_T_133, _T_134) @[dma_ctrl.scala 214:281] - node _T_136 = or(_T_132, _T_135) @[dma_ctrl.scala 214:236] - node _T_137 = eq(UInt<2>("h03"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 214:350] - node _T_138 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_137) @[dma_ctrl.scala 214:343] - node _T_139 = or(_T_136, _T_138) @[dma_ctrl.scala 214:300] - node _T_140 = eq(UInt<2>("h03"), io.iccm_dma_rtag) @[dma_ctrl.scala 214:423] - node _T_141 = and(io.iccm_dma_rvalid, _T_140) @[dma_ctrl.scala 214:416] - node _T_142 = or(_T_139, _T_141) @[dma_ctrl.scala 214:394] - node _T_143 = and(axi_mstr_prty_en, fifo_write_in) @[dma_ctrl.scala 214:73] - node _T_144 = and(_T_143, io.dma_bus_clk_en) @[dma_ctrl.scala 214:89] - node _T_145 = bits(io.dbg_dma.dbg_ib.dbg_cmd_type, 1, 1) @[dma_ctrl.scala 214:177] - node _T_146 = and(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_145) @[dma_ctrl.scala 214:145] - node _T_147 = and(_T_146, io.dbg_dma.dbg_ib.dbg_cmd_write) @[dma_ctrl.scala 214:181] - node _T_148 = or(_T_144, _T_147) @[dma_ctrl.scala 214:110] - node _T_149 = eq(UInt<3>("h04"), WrPtr) @[dma_ctrl.scala 214:224] - node _T_150 = and(_T_148, _T_149) @[dma_ctrl.scala 214:217] - node _T_151 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 214:258] - node _T_152 = eq(UInt<3>("h04"), RdPtr) @[dma_ctrl.scala 214:288] - node _T_153 = and(_T_151, _T_152) @[dma_ctrl.scala 214:281] - node _T_154 = or(_T_150, _T_153) @[dma_ctrl.scala 214:236] - node _T_155 = eq(UInt<3>("h04"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 214:350] - node _T_156 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_155) @[dma_ctrl.scala 214:343] - node _T_157 = or(_T_154, _T_156) @[dma_ctrl.scala 214:300] - node _T_158 = eq(UInt<3>("h04"), io.iccm_dma_rtag) @[dma_ctrl.scala 214:423] - node _T_159 = and(io.iccm_dma_rvalid, _T_158) @[dma_ctrl.scala 214:416] - node _T_160 = or(_T_157, _T_159) @[dma_ctrl.scala 214:394] + fifo_cmd_en <= _T_70 @[dma_ctrl.scala 206:21] + node _T_71 = and(axi_mstr_prty_en, fifo_write_in) @[dma_ctrl.scala 208:73] + node _T_72 = and(_T_71, io.dma_bus_clk_en) @[dma_ctrl.scala 208:89] + node _T_73 = bits(io.dbg_dma.dbg_ib.dbg_cmd_type, 1, 1) @[dma_ctrl.scala 208:177] + node _T_74 = and(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_73) @[dma_ctrl.scala 208:145] + node _T_75 = and(_T_74, io.dbg_dma.dbg_ib.dbg_cmd_write) @[dma_ctrl.scala 208:181] + node _T_76 = or(_T_72, _T_75) @[dma_ctrl.scala 208:110] + node _T_77 = eq(UInt<1>("h00"), WrPtr) @[dma_ctrl.scala 208:224] + node _T_78 = and(_T_76, _T_77) @[dma_ctrl.scala 208:217] + node _T_79 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 208:258] + node _T_80 = eq(UInt<1>("h00"), RdPtr) @[dma_ctrl.scala 208:288] + node _T_81 = and(_T_79, _T_80) @[dma_ctrl.scala 208:281] + node _T_82 = or(_T_78, _T_81) @[dma_ctrl.scala 208:236] + node _T_83 = eq(UInt<1>("h00"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 208:350] + node _T_84 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_83) @[dma_ctrl.scala 208:343] + node _T_85 = or(_T_82, _T_84) @[dma_ctrl.scala 208:300] + node _T_86 = eq(UInt<1>("h00"), io.iccm_dma_rtag) @[dma_ctrl.scala 208:423] + node _T_87 = and(io.iccm_dma_rvalid, _T_86) @[dma_ctrl.scala 208:416] + node _T_88 = or(_T_85, _T_87) @[dma_ctrl.scala 208:394] + node _T_89 = and(axi_mstr_prty_en, fifo_write_in) @[dma_ctrl.scala 208:73] + node _T_90 = and(_T_89, io.dma_bus_clk_en) @[dma_ctrl.scala 208:89] + node _T_91 = bits(io.dbg_dma.dbg_ib.dbg_cmd_type, 1, 1) @[dma_ctrl.scala 208:177] + node _T_92 = and(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_91) @[dma_ctrl.scala 208:145] + node _T_93 = and(_T_92, io.dbg_dma.dbg_ib.dbg_cmd_write) @[dma_ctrl.scala 208:181] + node _T_94 = or(_T_90, _T_93) @[dma_ctrl.scala 208:110] + node _T_95 = eq(UInt<1>("h01"), WrPtr) @[dma_ctrl.scala 208:224] + node _T_96 = and(_T_94, _T_95) @[dma_ctrl.scala 208:217] + node _T_97 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 208:258] + node _T_98 = eq(UInt<1>("h01"), RdPtr) @[dma_ctrl.scala 208:288] + node _T_99 = and(_T_97, _T_98) @[dma_ctrl.scala 208:281] + node _T_100 = or(_T_96, _T_99) @[dma_ctrl.scala 208:236] + node _T_101 = eq(UInt<1>("h01"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 208:350] + node _T_102 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_101) @[dma_ctrl.scala 208:343] + node _T_103 = or(_T_100, _T_102) @[dma_ctrl.scala 208:300] + node _T_104 = eq(UInt<1>("h01"), io.iccm_dma_rtag) @[dma_ctrl.scala 208:423] + node _T_105 = and(io.iccm_dma_rvalid, _T_104) @[dma_ctrl.scala 208:416] + node _T_106 = or(_T_103, _T_105) @[dma_ctrl.scala 208:394] + node _T_107 = and(axi_mstr_prty_en, fifo_write_in) @[dma_ctrl.scala 208:73] + node _T_108 = and(_T_107, io.dma_bus_clk_en) @[dma_ctrl.scala 208:89] + node _T_109 = bits(io.dbg_dma.dbg_ib.dbg_cmd_type, 1, 1) @[dma_ctrl.scala 208:177] + node _T_110 = and(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_109) @[dma_ctrl.scala 208:145] + node _T_111 = and(_T_110, io.dbg_dma.dbg_ib.dbg_cmd_write) @[dma_ctrl.scala 208:181] + node _T_112 = or(_T_108, _T_111) @[dma_ctrl.scala 208:110] + node _T_113 = eq(UInt<2>("h02"), WrPtr) @[dma_ctrl.scala 208:224] + node _T_114 = and(_T_112, _T_113) @[dma_ctrl.scala 208:217] + node _T_115 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 208:258] + node _T_116 = eq(UInt<2>("h02"), RdPtr) @[dma_ctrl.scala 208:288] + node _T_117 = and(_T_115, _T_116) @[dma_ctrl.scala 208:281] + node _T_118 = or(_T_114, _T_117) @[dma_ctrl.scala 208:236] + node _T_119 = eq(UInt<2>("h02"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 208:350] + node _T_120 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_119) @[dma_ctrl.scala 208:343] + node _T_121 = or(_T_118, _T_120) @[dma_ctrl.scala 208:300] + node _T_122 = eq(UInt<2>("h02"), io.iccm_dma_rtag) @[dma_ctrl.scala 208:423] + node _T_123 = and(io.iccm_dma_rvalid, _T_122) @[dma_ctrl.scala 208:416] + node _T_124 = or(_T_121, _T_123) @[dma_ctrl.scala 208:394] + node _T_125 = and(axi_mstr_prty_en, fifo_write_in) @[dma_ctrl.scala 208:73] + node _T_126 = and(_T_125, io.dma_bus_clk_en) @[dma_ctrl.scala 208:89] + node _T_127 = bits(io.dbg_dma.dbg_ib.dbg_cmd_type, 1, 1) @[dma_ctrl.scala 208:177] + node _T_128 = and(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_127) @[dma_ctrl.scala 208:145] + node _T_129 = and(_T_128, io.dbg_dma.dbg_ib.dbg_cmd_write) @[dma_ctrl.scala 208:181] + node _T_130 = or(_T_126, _T_129) @[dma_ctrl.scala 208:110] + node _T_131 = eq(UInt<2>("h03"), WrPtr) @[dma_ctrl.scala 208:224] + node _T_132 = and(_T_130, _T_131) @[dma_ctrl.scala 208:217] + node _T_133 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 208:258] + node _T_134 = eq(UInt<2>("h03"), RdPtr) @[dma_ctrl.scala 208:288] + node _T_135 = and(_T_133, _T_134) @[dma_ctrl.scala 208:281] + node _T_136 = or(_T_132, _T_135) @[dma_ctrl.scala 208:236] + node _T_137 = eq(UInt<2>("h03"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 208:350] + node _T_138 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_137) @[dma_ctrl.scala 208:343] + node _T_139 = or(_T_136, _T_138) @[dma_ctrl.scala 208:300] + node _T_140 = eq(UInt<2>("h03"), io.iccm_dma_rtag) @[dma_ctrl.scala 208:423] + node _T_141 = and(io.iccm_dma_rvalid, _T_140) @[dma_ctrl.scala 208:416] + node _T_142 = or(_T_139, _T_141) @[dma_ctrl.scala 208:394] + node _T_143 = and(axi_mstr_prty_en, fifo_write_in) @[dma_ctrl.scala 208:73] + node _T_144 = and(_T_143, io.dma_bus_clk_en) @[dma_ctrl.scala 208:89] + node _T_145 = bits(io.dbg_dma.dbg_ib.dbg_cmd_type, 1, 1) @[dma_ctrl.scala 208:177] + node _T_146 = and(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_145) @[dma_ctrl.scala 208:145] + node _T_147 = and(_T_146, io.dbg_dma.dbg_ib.dbg_cmd_write) @[dma_ctrl.scala 208:181] + node _T_148 = or(_T_144, _T_147) @[dma_ctrl.scala 208:110] + node _T_149 = eq(UInt<3>("h04"), WrPtr) @[dma_ctrl.scala 208:224] + node _T_150 = and(_T_148, _T_149) @[dma_ctrl.scala 208:217] + node _T_151 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 208:258] + node _T_152 = eq(UInt<3>("h04"), RdPtr) @[dma_ctrl.scala 208:288] + node _T_153 = and(_T_151, _T_152) @[dma_ctrl.scala 208:281] + node _T_154 = or(_T_150, _T_153) @[dma_ctrl.scala 208:236] + node _T_155 = eq(UInt<3>("h04"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 208:350] + node _T_156 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_155) @[dma_ctrl.scala 208:343] + node _T_157 = or(_T_154, _T_156) @[dma_ctrl.scala 208:300] + node _T_158 = eq(UInt<3>("h04"), io.iccm_dma_rtag) @[dma_ctrl.scala 208:423] + node _T_159 = and(io.iccm_dma_rvalid, _T_158) @[dma_ctrl.scala 208:416] + node _T_160 = or(_T_157, _T_159) @[dma_ctrl.scala 208:394] node _T_161 = cat(_T_160, _T_142) @[Cat.scala 29:58] node _T_162 = cat(_T_161, _T_124) @[Cat.scala 29:58] node _T_163 = cat(_T_162, _T_106) @[Cat.scala 29:58] node _T_164 = cat(_T_163, _T_88) @[Cat.scala 29:58] - fifo_data_en <= _T_164 @[dma_ctrl.scala 214:21] - node _T_165 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 216:95] - node _T_166 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 216:136] - node _T_167 = and(_T_165, _T_166) @[dma_ctrl.scala 216:134] - node _T_168 = eq(UInt<1>("h00"), RdPtr) @[dma_ctrl.scala 216:181] - node _T_169 = and(_T_167, _T_168) @[dma_ctrl.scala 216:174] - node _T_170 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 216:95] - node _T_171 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 216:136] - node _T_172 = and(_T_170, _T_171) @[dma_ctrl.scala 216:134] - node _T_173 = eq(UInt<1>("h01"), RdPtr) @[dma_ctrl.scala 216:181] - node _T_174 = and(_T_172, _T_173) @[dma_ctrl.scala 216:174] - node _T_175 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 216:95] - node _T_176 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 216:136] - node _T_177 = and(_T_175, _T_176) @[dma_ctrl.scala 216:134] - node _T_178 = eq(UInt<2>("h02"), RdPtr) @[dma_ctrl.scala 216:181] - node _T_179 = and(_T_177, _T_178) @[dma_ctrl.scala 216:174] - node _T_180 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 216:95] - node _T_181 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 216:136] - node _T_182 = and(_T_180, _T_181) @[dma_ctrl.scala 216:134] - node _T_183 = eq(UInt<2>("h03"), RdPtr) @[dma_ctrl.scala 216:181] - node _T_184 = and(_T_182, _T_183) @[dma_ctrl.scala 216:174] - node _T_185 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 216:95] - node _T_186 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 216:136] - node _T_187 = and(_T_185, _T_186) @[dma_ctrl.scala 216:134] - node _T_188 = eq(UInt<3>("h04"), RdPtr) @[dma_ctrl.scala 216:181] - node _T_189 = and(_T_187, _T_188) @[dma_ctrl.scala 216:174] + fifo_data_en <= _T_164 @[dma_ctrl.scala 208:21] + node _T_165 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 210:95] + node _T_166 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 210:136] + node _T_167 = and(_T_165, _T_166) @[dma_ctrl.scala 210:134] + node _T_168 = eq(UInt<1>("h00"), RdPtr) @[dma_ctrl.scala 210:181] + node _T_169 = and(_T_167, _T_168) @[dma_ctrl.scala 210:174] + node _T_170 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 210:95] + node _T_171 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 210:136] + node _T_172 = and(_T_170, _T_171) @[dma_ctrl.scala 210:134] + node _T_173 = eq(UInt<1>("h01"), RdPtr) @[dma_ctrl.scala 210:181] + node _T_174 = and(_T_172, _T_173) @[dma_ctrl.scala 210:174] + node _T_175 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 210:95] + node _T_176 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 210:136] + node _T_177 = and(_T_175, _T_176) @[dma_ctrl.scala 210:134] + node _T_178 = eq(UInt<2>("h02"), RdPtr) @[dma_ctrl.scala 210:181] + node _T_179 = and(_T_177, _T_178) @[dma_ctrl.scala 210:174] + node _T_180 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 210:95] + node _T_181 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 210:136] + node _T_182 = and(_T_180, _T_181) @[dma_ctrl.scala 210:134] + node _T_183 = eq(UInt<2>("h03"), RdPtr) @[dma_ctrl.scala 210:181] + node _T_184 = and(_T_182, _T_183) @[dma_ctrl.scala 210:174] + node _T_185 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 210:95] + node _T_186 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 210:136] + node _T_187 = and(_T_185, _T_186) @[dma_ctrl.scala 210:134] + node _T_188 = eq(UInt<3>("h04"), RdPtr) @[dma_ctrl.scala 210:181] + node _T_189 = and(_T_187, _T_188) @[dma_ctrl.scala 210:174] node _T_190 = cat(_T_189, _T_184) @[Cat.scala 29:58] node _T_191 = cat(_T_190, _T_179) @[Cat.scala 29:58] node _T_192 = cat(_T_191, _T_174) @[Cat.scala 29:58] node _T_193 = cat(_T_192, _T_169) @[Cat.scala 29:58] - fifo_pend_en <= _T_193 @[dma_ctrl.scala 216:21] - node _T_194 = bits(dma_address_error, 0, 0) @[dma_ctrl.scala 218:78] - node _T_195 = bits(dma_alignment_error, 0, 0) @[dma_ctrl.scala 218:107] - node _T_196 = or(_T_194, _T_195) @[dma_ctrl.scala 218:85] - node _T_197 = or(_T_196, dma_dbg_cmd_error) @[dma_ctrl.scala 218:114] - node _T_198 = eq(UInt<1>("h00"), RdPtr) @[dma_ctrl.scala 218:142] - node _T_199 = and(_T_197, _T_198) @[dma_ctrl.scala 218:135] - node _T_200 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error) @[dma_ctrl.scala 218:198] - node _T_201 = eq(UInt<1>("h00"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 218:251] - node _T_202 = and(_T_200, _T_201) @[dma_ctrl.scala 218:244] - node _T_203 = or(_T_199, _T_202) @[dma_ctrl.scala 218:154] - node _T_204 = and(io.iccm_dma_rvalid, io.iccm_dma_ecc_error) @[dma_ctrl.scala 218:318] - node _T_205 = eq(UInt<1>("h00"), io.iccm_dma_rtag) @[dma_ctrl.scala 218:350] - node _T_206 = and(_T_204, _T_205) @[dma_ctrl.scala 218:343] - node _T_207 = or(_T_203, _T_206) @[dma_ctrl.scala 218:295] - node _T_208 = bits(dma_address_error, 0, 0) @[dma_ctrl.scala 218:78] - node _T_209 = bits(dma_alignment_error, 0, 0) @[dma_ctrl.scala 218:107] - node _T_210 = or(_T_208, _T_209) @[dma_ctrl.scala 218:85] - node _T_211 = or(_T_210, dma_dbg_cmd_error) @[dma_ctrl.scala 218:114] - node _T_212 = eq(UInt<1>("h01"), RdPtr) @[dma_ctrl.scala 218:142] - node _T_213 = and(_T_211, _T_212) @[dma_ctrl.scala 218:135] - node _T_214 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error) @[dma_ctrl.scala 218:198] - node _T_215 = eq(UInt<1>("h01"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 218:251] - node _T_216 = and(_T_214, _T_215) @[dma_ctrl.scala 218:244] - node _T_217 = or(_T_213, _T_216) @[dma_ctrl.scala 218:154] - node _T_218 = and(io.iccm_dma_rvalid, io.iccm_dma_ecc_error) @[dma_ctrl.scala 218:318] - node _T_219 = eq(UInt<1>("h01"), io.iccm_dma_rtag) @[dma_ctrl.scala 218:350] - node _T_220 = and(_T_218, _T_219) @[dma_ctrl.scala 218:343] - node _T_221 = or(_T_217, _T_220) @[dma_ctrl.scala 218:295] - node _T_222 = bits(dma_address_error, 0, 0) @[dma_ctrl.scala 218:78] - node _T_223 = bits(dma_alignment_error, 0, 0) @[dma_ctrl.scala 218:107] - node _T_224 = or(_T_222, _T_223) @[dma_ctrl.scala 218:85] - node _T_225 = or(_T_224, dma_dbg_cmd_error) @[dma_ctrl.scala 218:114] - node _T_226 = eq(UInt<2>("h02"), RdPtr) @[dma_ctrl.scala 218:142] - node _T_227 = and(_T_225, _T_226) @[dma_ctrl.scala 218:135] - node _T_228 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error) @[dma_ctrl.scala 218:198] - node _T_229 = eq(UInt<2>("h02"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 218:251] - node _T_230 = and(_T_228, _T_229) @[dma_ctrl.scala 218:244] - node _T_231 = or(_T_227, _T_230) @[dma_ctrl.scala 218:154] - node _T_232 = and(io.iccm_dma_rvalid, io.iccm_dma_ecc_error) @[dma_ctrl.scala 218:318] - node _T_233 = eq(UInt<2>("h02"), io.iccm_dma_rtag) @[dma_ctrl.scala 218:350] - node _T_234 = and(_T_232, _T_233) @[dma_ctrl.scala 218:343] - node _T_235 = or(_T_231, _T_234) @[dma_ctrl.scala 218:295] - node _T_236 = bits(dma_address_error, 0, 0) @[dma_ctrl.scala 218:78] - node _T_237 = bits(dma_alignment_error, 0, 0) @[dma_ctrl.scala 218:107] - node _T_238 = or(_T_236, _T_237) @[dma_ctrl.scala 218:85] - node _T_239 = or(_T_238, dma_dbg_cmd_error) @[dma_ctrl.scala 218:114] - node _T_240 = eq(UInt<2>("h03"), RdPtr) @[dma_ctrl.scala 218:142] - node _T_241 = and(_T_239, _T_240) @[dma_ctrl.scala 218:135] - node _T_242 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error) @[dma_ctrl.scala 218:198] - node _T_243 = eq(UInt<2>("h03"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 218:251] - node _T_244 = and(_T_242, _T_243) @[dma_ctrl.scala 218:244] - node _T_245 = or(_T_241, _T_244) @[dma_ctrl.scala 218:154] - node _T_246 = and(io.iccm_dma_rvalid, io.iccm_dma_ecc_error) @[dma_ctrl.scala 218:318] - node _T_247 = eq(UInt<2>("h03"), io.iccm_dma_rtag) @[dma_ctrl.scala 218:350] - node _T_248 = and(_T_246, _T_247) @[dma_ctrl.scala 218:343] - node _T_249 = or(_T_245, _T_248) @[dma_ctrl.scala 218:295] - node _T_250 = bits(dma_address_error, 0, 0) @[dma_ctrl.scala 218:78] - node _T_251 = bits(dma_alignment_error, 0, 0) @[dma_ctrl.scala 218:107] - node _T_252 = or(_T_250, _T_251) @[dma_ctrl.scala 218:85] - node _T_253 = or(_T_252, dma_dbg_cmd_error) @[dma_ctrl.scala 218:114] - node _T_254 = eq(UInt<3>("h04"), RdPtr) @[dma_ctrl.scala 218:142] - node _T_255 = and(_T_253, _T_254) @[dma_ctrl.scala 218:135] - node _T_256 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error) @[dma_ctrl.scala 218:198] - node _T_257 = eq(UInt<3>("h04"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 218:251] - node _T_258 = and(_T_256, _T_257) @[dma_ctrl.scala 218:244] - node _T_259 = or(_T_255, _T_258) @[dma_ctrl.scala 218:154] - node _T_260 = and(io.iccm_dma_rvalid, io.iccm_dma_ecc_error) @[dma_ctrl.scala 218:318] - node _T_261 = eq(UInt<3>("h04"), io.iccm_dma_rtag) @[dma_ctrl.scala 218:350] - node _T_262 = and(_T_260, _T_261) @[dma_ctrl.scala 218:343] - node _T_263 = or(_T_259, _T_262) @[dma_ctrl.scala 218:295] + fifo_pend_en <= _T_193 @[dma_ctrl.scala 210:21] + node _T_194 = bits(dma_address_error, 0, 0) @[dma_ctrl.scala 212:78] + node _T_195 = bits(dma_alignment_error, 0, 0) @[dma_ctrl.scala 212:107] + node _T_196 = or(_T_194, _T_195) @[dma_ctrl.scala 212:85] + node _T_197 = or(_T_196, dma_dbg_cmd_error) @[dma_ctrl.scala 212:114] + node _T_198 = eq(UInt<1>("h00"), RdPtr) @[dma_ctrl.scala 212:142] + node _T_199 = and(_T_197, _T_198) @[dma_ctrl.scala 212:135] + node _T_200 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error) @[dma_ctrl.scala 212:198] + node _T_201 = eq(UInt<1>("h00"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 212:251] + node _T_202 = and(_T_200, _T_201) @[dma_ctrl.scala 212:244] + node _T_203 = or(_T_199, _T_202) @[dma_ctrl.scala 212:154] + node _T_204 = and(io.iccm_dma_rvalid, io.iccm_dma_ecc_error) @[dma_ctrl.scala 212:318] + node _T_205 = eq(UInt<1>("h00"), io.iccm_dma_rtag) @[dma_ctrl.scala 212:350] + node _T_206 = and(_T_204, _T_205) @[dma_ctrl.scala 212:343] + node _T_207 = or(_T_203, _T_206) @[dma_ctrl.scala 212:295] + node _T_208 = bits(dma_address_error, 0, 0) @[dma_ctrl.scala 212:78] + node _T_209 = bits(dma_alignment_error, 0, 0) @[dma_ctrl.scala 212:107] + node _T_210 = or(_T_208, _T_209) @[dma_ctrl.scala 212:85] + node _T_211 = or(_T_210, dma_dbg_cmd_error) @[dma_ctrl.scala 212:114] + node _T_212 = eq(UInt<1>("h01"), RdPtr) @[dma_ctrl.scala 212:142] + node _T_213 = and(_T_211, _T_212) @[dma_ctrl.scala 212:135] + node _T_214 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error) @[dma_ctrl.scala 212:198] + node _T_215 = eq(UInt<1>("h01"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 212:251] + node _T_216 = and(_T_214, _T_215) @[dma_ctrl.scala 212:244] + node _T_217 = or(_T_213, _T_216) @[dma_ctrl.scala 212:154] + node _T_218 = and(io.iccm_dma_rvalid, io.iccm_dma_ecc_error) @[dma_ctrl.scala 212:318] + node _T_219 = eq(UInt<1>("h01"), io.iccm_dma_rtag) @[dma_ctrl.scala 212:350] + node _T_220 = and(_T_218, _T_219) @[dma_ctrl.scala 212:343] + node _T_221 = or(_T_217, _T_220) @[dma_ctrl.scala 212:295] + node _T_222 = bits(dma_address_error, 0, 0) @[dma_ctrl.scala 212:78] + node _T_223 = bits(dma_alignment_error, 0, 0) @[dma_ctrl.scala 212:107] + node _T_224 = or(_T_222, _T_223) @[dma_ctrl.scala 212:85] + node _T_225 = or(_T_224, dma_dbg_cmd_error) @[dma_ctrl.scala 212:114] + node _T_226 = eq(UInt<2>("h02"), RdPtr) @[dma_ctrl.scala 212:142] + node _T_227 = and(_T_225, _T_226) @[dma_ctrl.scala 212:135] + node _T_228 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error) @[dma_ctrl.scala 212:198] + node _T_229 = eq(UInt<2>("h02"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 212:251] + node _T_230 = and(_T_228, _T_229) @[dma_ctrl.scala 212:244] + node _T_231 = or(_T_227, _T_230) @[dma_ctrl.scala 212:154] + node _T_232 = and(io.iccm_dma_rvalid, io.iccm_dma_ecc_error) @[dma_ctrl.scala 212:318] + node _T_233 = eq(UInt<2>("h02"), io.iccm_dma_rtag) @[dma_ctrl.scala 212:350] + node _T_234 = and(_T_232, _T_233) @[dma_ctrl.scala 212:343] + node _T_235 = or(_T_231, _T_234) @[dma_ctrl.scala 212:295] + node _T_236 = bits(dma_address_error, 0, 0) @[dma_ctrl.scala 212:78] + node _T_237 = bits(dma_alignment_error, 0, 0) @[dma_ctrl.scala 212:107] + node _T_238 = or(_T_236, _T_237) @[dma_ctrl.scala 212:85] + node _T_239 = or(_T_238, dma_dbg_cmd_error) @[dma_ctrl.scala 212:114] + node _T_240 = eq(UInt<2>("h03"), RdPtr) @[dma_ctrl.scala 212:142] + node _T_241 = and(_T_239, _T_240) @[dma_ctrl.scala 212:135] + node _T_242 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error) @[dma_ctrl.scala 212:198] + node _T_243 = eq(UInt<2>("h03"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 212:251] + node _T_244 = and(_T_242, _T_243) @[dma_ctrl.scala 212:244] + node _T_245 = or(_T_241, _T_244) @[dma_ctrl.scala 212:154] + node _T_246 = and(io.iccm_dma_rvalid, io.iccm_dma_ecc_error) @[dma_ctrl.scala 212:318] + node _T_247 = eq(UInt<2>("h03"), io.iccm_dma_rtag) @[dma_ctrl.scala 212:350] + node _T_248 = and(_T_246, _T_247) @[dma_ctrl.scala 212:343] + node _T_249 = or(_T_245, _T_248) @[dma_ctrl.scala 212:295] + node _T_250 = bits(dma_address_error, 0, 0) @[dma_ctrl.scala 212:78] + node _T_251 = bits(dma_alignment_error, 0, 0) @[dma_ctrl.scala 212:107] + node _T_252 = or(_T_250, _T_251) @[dma_ctrl.scala 212:85] + node _T_253 = or(_T_252, dma_dbg_cmd_error) @[dma_ctrl.scala 212:114] + node _T_254 = eq(UInt<3>("h04"), RdPtr) @[dma_ctrl.scala 212:142] + node _T_255 = and(_T_253, _T_254) @[dma_ctrl.scala 212:135] + node _T_256 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error) @[dma_ctrl.scala 212:198] + node _T_257 = eq(UInt<3>("h04"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 212:251] + node _T_258 = and(_T_256, _T_257) @[dma_ctrl.scala 212:244] + node _T_259 = or(_T_255, _T_258) @[dma_ctrl.scala 212:154] + node _T_260 = and(io.iccm_dma_rvalid, io.iccm_dma_ecc_error) @[dma_ctrl.scala 212:318] + node _T_261 = eq(UInt<3>("h04"), io.iccm_dma_rtag) @[dma_ctrl.scala 212:350] + node _T_262 = and(_T_260, _T_261) @[dma_ctrl.scala 212:343] + node _T_263 = or(_T_259, _T_262) @[dma_ctrl.scala 212:295] node _T_264 = cat(_T_263, _T_249) @[Cat.scala 29:58] node _T_265 = cat(_T_264, _T_235) @[Cat.scala 29:58] node _T_266 = cat(_T_265, _T_221) @[Cat.scala 29:58] node _T_267 = cat(_T_266, _T_207) @[Cat.scala 29:58] - fifo_error_en <= _T_267 @[dma_ctrl.scala 218:21] - node _T_268 = bits(fifo_error_in[0], 1, 0) @[dma_ctrl.scala 220:77] - node _T_269 = orr(_T_268) @[dma_ctrl.scala 220:83] - node _T_270 = bits(fifo_error_en, 0, 0) @[dma_ctrl.scala 220:103] - node _T_271 = and(_T_269, _T_270) @[dma_ctrl.scala 220:88] - node _T_272 = orr(fifo_error[0]) @[dma_ctrl.scala 220:125] - node _T_273 = or(_T_271, _T_272) @[dma_ctrl.scala 220:108] - node _T_274 = and(_T_273, io.dma_bus_clk_en) @[dma_ctrl.scala 220:131] - node _T_275 = bits(fifo_error_in[1], 1, 0) @[dma_ctrl.scala 220:77] - node _T_276 = orr(_T_275) @[dma_ctrl.scala 220:83] - node _T_277 = bits(fifo_error_en, 1, 1) @[dma_ctrl.scala 220:103] - node _T_278 = and(_T_276, _T_277) @[dma_ctrl.scala 220:88] - node _T_279 = orr(fifo_error[1]) @[dma_ctrl.scala 220:125] - node _T_280 = or(_T_278, _T_279) @[dma_ctrl.scala 220:108] - node _T_281 = and(_T_280, io.dma_bus_clk_en) @[dma_ctrl.scala 220:131] - node _T_282 = bits(fifo_error_in[2], 1, 0) @[dma_ctrl.scala 220:77] - node _T_283 = orr(_T_282) @[dma_ctrl.scala 220:83] - node _T_284 = bits(fifo_error_en, 2, 2) @[dma_ctrl.scala 220:103] - node _T_285 = and(_T_283, _T_284) @[dma_ctrl.scala 220:88] - node _T_286 = orr(fifo_error[2]) @[dma_ctrl.scala 220:125] - node _T_287 = or(_T_285, _T_286) @[dma_ctrl.scala 220:108] - node _T_288 = and(_T_287, io.dma_bus_clk_en) @[dma_ctrl.scala 220:131] - node _T_289 = bits(fifo_error_in[3], 1, 0) @[dma_ctrl.scala 220:77] - node _T_290 = orr(_T_289) @[dma_ctrl.scala 220:83] - node _T_291 = bits(fifo_error_en, 3, 3) @[dma_ctrl.scala 220:103] - node _T_292 = and(_T_290, _T_291) @[dma_ctrl.scala 220:88] - node _T_293 = orr(fifo_error[3]) @[dma_ctrl.scala 220:125] - node _T_294 = or(_T_292, _T_293) @[dma_ctrl.scala 220:108] - node _T_295 = and(_T_294, io.dma_bus_clk_en) @[dma_ctrl.scala 220:131] - node _T_296 = bits(fifo_error_in[4], 1, 0) @[dma_ctrl.scala 220:77] - node _T_297 = orr(_T_296) @[dma_ctrl.scala 220:83] - node _T_298 = bits(fifo_error_en, 4, 4) @[dma_ctrl.scala 220:103] - node _T_299 = and(_T_297, _T_298) @[dma_ctrl.scala 220:88] - node _T_300 = orr(fifo_error[4]) @[dma_ctrl.scala 220:125] - node _T_301 = or(_T_299, _T_300) @[dma_ctrl.scala 220:108] - node _T_302 = and(_T_301, io.dma_bus_clk_en) @[dma_ctrl.scala 220:131] + fifo_error_en <= _T_267 @[dma_ctrl.scala 212:21] + node _T_268 = bits(fifo_error_in[0], 1, 0) @[dma_ctrl.scala 214:77] + node _T_269 = orr(_T_268) @[dma_ctrl.scala 214:83] + node _T_270 = bits(fifo_error_en, 0, 0) @[dma_ctrl.scala 214:103] + node _T_271 = and(_T_269, _T_270) @[dma_ctrl.scala 214:88] + node _T_272 = orr(fifo_error[0]) @[dma_ctrl.scala 214:125] + node _T_273 = or(_T_271, _T_272) @[dma_ctrl.scala 214:108] + node _T_274 = and(_T_273, io.dma_bus_clk_en) @[dma_ctrl.scala 214:131] + node _T_275 = bits(fifo_error_in[1], 1, 0) @[dma_ctrl.scala 214:77] + node _T_276 = orr(_T_275) @[dma_ctrl.scala 214:83] + node _T_277 = bits(fifo_error_en, 1, 1) @[dma_ctrl.scala 214:103] + node _T_278 = and(_T_276, _T_277) @[dma_ctrl.scala 214:88] + node _T_279 = orr(fifo_error[1]) @[dma_ctrl.scala 214:125] + node _T_280 = or(_T_278, _T_279) @[dma_ctrl.scala 214:108] + node _T_281 = and(_T_280, io.dma_bus_clk_en) @[dma_ctrl.scala 214:131] + node _T_282 = bits(fifo_error_in[2], 1, 0) @[dma_ctrl.scala 214:77] + node _T_283 = orr(_T_282) @[dma_ctrl.scala 214:83] + node _T_284 = bits(fifo_error_en, 2, 2) @[dma_ctrl.scala 214:103] + node _T_285 = and(_T_283, _T_284) @[dma_ctrl.scala 214:88] + node _T_286 = orr(fifo_error[2]) @[dma_ctrl.scala 214:125] + node _T_287 = or(_T_285, _T_286) @[dma_ctrl.scala 214:108] + node _T_288 = and(_T_287, io.dma_bus_clk_en) @[dma_ctrl.scala 214:131] + node _T_289 = bits(fifo_error_in[3], 1, 0) @[dma_ctrl.scala 214:77] + node _T_290 = orr(_T_289) @[dma_ctrl.scala 214:83] + node _T_291 = bits(fifo_error_en, 3, 3) @[dma_ctrl.scala 214:103] + node _T_292 = and(_T_290, _T_291) @[dma_ctrl.scala 214:88] + node _T_293 = orr(fifo_error[3]) @[dma_ctrl.scala 214:125] + node _T_294 = or(_T_292, _T_293) @[dma_ctrl.scala 214:108] + node _T_295 = and(_T_294, io.dma_bus_clk_en) @[dma_ctrl.scala 214:131] + node _T_296 = bits(fifo_error_in[4], 1, 0) @[dma_ctrl.scala 214:77] + node _T_297 = orr(_T_296) @[dma_ctrl.scala 214:83] + node _T_298 = bits(fifo_error_en, 4, 4) @[dma_ctrl.scala 214:103] + node _T_299 = and(_T_297, _T_298) @[dma_ctrl.scala 214:88] + node _T_300 = orr(fifo_error[4]) @[dma_ctrl.scala 214:125] + node _T_301 = or(_T_299, _T_300) @[dma_ctrl.scala 214:108] + node _T_302 = and(_T_301, io.dma_bus_clk_en) @[dma_ctrl.scala 214:131] node _T_303 = cat(_T_302, _T_295) @[Cat.scala 29:58] node _T_304 = cat(_T_303, _T_288) @[Cat.scala 29:58] node _T_305 = cat(_T_304, _T_281) @[Cat.scala 29:58] node _T_306 = cat(_T_305, _T_274) @[Cat.scala 29:58] - fifo_error_bus_en <= _T_306 @[dma_ctrl.scala 220:21] - node _T_307 = orr(fifo_error[0]) @[dma_ctrl.scala 222:74] - node _T_308 = bits(fifo_error_en, 0, 0) @[dma_ctrl.scala 222:93] - node _T_309 = or(_T_307, _T_308) @[dma_ctrl.scala 222:78] - node _T_310 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 222:137] - node _T_311 = and(_T_310, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 222:176] - node _T_312 = or(_T_309, _T_311) @[dma_ctrl.scala 222:97] - node _T_313 = eq(UInt<1>("h00"), RdPtr) @[dma_ctrl.scala 222:224] - node _T_314 = and(_T_312, _T_313) @[dma_ctrl.scala 222:217] - node _T_315 = eq(UInt<1>("h00"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 222:286] - node _T_316 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_315) @[dma_ctrl.scala 222:279] - node _T_317 = or(_T_314, _T_316) @[dma_ctrl.scala 222:236] - node _T_318 = eq(UInt<1>("h00"), io.iccm_dma_rtag) @[dma_ctrl.scala 222:359] - node _T_319 = and(io.iccm_dma_rvalid, _T_318) @[dma_ctrl.scala 222:352] - node _T_320 = or(_T_317, _T_319) @[dma_ctrl.scala 222:330] - node _T_321 = orr(fifo_error[1]) @[dma_ctrl.scala 222:74] - node _T_322 = bits(fifo_error_en, 1, 1) @[dma_ctrl.scala 222:93] - node _T_323 = or(_T_321, _T_322) @[dma_ctrl.scala 222:78] - node _T_324 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 222:137] - node _T_325 = and(_T_324, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 222:176] - node _T_326 = or(_T_323, _T_325) @[dma_ctrl.scala 222:97] - node _T_327 = eq(UInt<1>("h01"), RdPtr) @[dma_ctrl.scala 222:224] - node _T_328 = and(_T_326, _T_327) @[dma_ctrl.scala 222:217] - node _T_329 = eq(UInt<1>("h01"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 222:286] - node _T_330 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_329) @[dma_ctrl.scala 222:279] - node _T_331 = or(_T_328, _T_330) @[dma_ctrl.scala 222:236] - node _T_332 = eq(UInt<1>("h01"), io.iccm_dma_rtag) @[dma_ctrl.scala 222:359] - node _T_333 = and(io.iccm_dma_rvalid, _T_332) @[dma_ctrl.scala 222:352] - node _T_334 = or(_T_331, _T_333) @[dma_ctrl.scala 222:330] - node _T_335 = orr(fifo_error[2]) @[dma_ctrl.scala 222:74] - node _T_336 = bits(fifo_error_en, 2, 2) @[dma_ctrl.scala 222:93] - node _T_337 = or(_T_335, _T_336) @[dma_ctrl.scala 222:78] - node _T_338 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 222:137] - node _T_339 = and(_T_338, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 222:176] - node _T_340 = or(_T_337, _T_339) @[dma_ctrl.scala 222:97] - node _T_341 = eq(UInt<2>("h02"), RdPtr) @[dma_ctrl.scala 222:224] - node _T_342 = and(_T_340, _T_341) @[dma_ctrl.scala 222:217] - node _T_343 = eq(UInt<2>("h02"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 222:286] - node _T_344 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_343) @[dma_ctrl.scala 222:279] - node _T_345 = or(_T_342, _T_344) @[dma_ctrl.scala 222:236] - node _T_346 = eq(UInt<2>("h02"), io.iccm_dma_rtag) @[dma_ctrl.scala 222:359] - node _T_347 = and(io.iccm_dma_rvalid, _T_346) @[dma_ctrl.scala 222:352] - node _T_348 = or(_T_345, _T_347) @[dma_ctrl.scala 222:330] - node _T_349 = orr(fifo_error[3]) @[dma_ctrl.scala 222:74] - node _T_350 = bits(fifo_error_en, 3, 3) @[dma_ctrl.scala 222:93] - node _T_351 = or(_T_349, _T_350) @[dma_ctrl.scala 222:78] - node _T_352 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 222:137] - node _T_353 = and(_T_352, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 222:176] - node _T_354 = or(_T_351, _T_353) @[dma_ctrl.scala 222:97] - node _T_355 = eq(UInt<2>("h03"), RdPtr) @[dma_ctrl.scala 222:224] - node _T_356 = and(_T_354, _T_355) @[dma_ctrl.scala 222:217] - node _T_357 = eq(UInt<2>("h03"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 222:286] - node _T_358 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_357) @[dma_ctrl.scala 222:279] - node _T_359 = or(_T_356, _T_358) @[dma_ctrl.scala 222:236] - node _T_360 = eq(UInt<2>("h03"), io.iccm_dma_rtag) @[dma_ctrl.scala 222:359] - node _T_361 = and(io.iccm_dma_rvalid, _T_360) @[dma_ctrl.scala 222:352] - node _T_362 = or(_T_359, _T_361) @[dma_ctrl.scala 222:330] - node _T_363 = orr(fifo_error[4]) @[dma_ctrl.scala 222:74] - node _T_364 = bits(fifo_error_en, 4, 4) @[dma_ctrl.scala 222:93] - node _T_365 = or(_T_363, _T_364) @[dma_ctrl.scala 222:78] - node _T_366 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 222:137] - node _T_367 = and(_T_366, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 222:176] - node _T_368 = or(_T_365, _T_367) @[dma_ctrl.scala 222:97] - node _T_369 = eq(UInt<3>("h04"), RdPtr) @[dma_ctrl.scala 222:224] - node _T_370 = and(_T_368, _T_369) @[dma_ctrl.scala 222:217] - node _T_371 = eq(UInt<3>("h04"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 222:286] - node _T_372 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_371) @[dma_ctrl.scala 222:279] - node _T_373 = or(_T_370, _T_372) @[dma_ctrl.scala 222:236] - node _T_374 = eq(UInt<3>("h04"), io.iccm_dma_rtag) @[dma_ctrl.scala 222:359] - node _T_375 = and(io.iccm_dma_rvalid, _T_374) @[dma_ctrl.scala 222:352] - node _T_376 = or(_T_373, _T_375) @[dma_ctrl.scala 222:330] + fifo_error_bus_en <= _T_306 @[dma_ctrl.scala 214:21] + node _T_307 = orr(fifo_error[0]) @[dma_ctrl.scala 216:74] + node _T_308 = bits(fifo_error_en, 0, 0) @[dma_ctrl.scala 216:93] + node _T_309 = or(_T_307, _T_308) @[dma_ctrl.scala 216:78] + node _T_310 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 216:137] + node _T_311 = and(_T_310, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 216:176] + node _T_312 = or(_T_309, _T_311) @[dma_ctrl.scala 216:97] + node _T_313 = eq(UInt<1>("h00"), RdPtr) @[dma_ctrl.scala 216:224] + node _T_314 = and(_T_312, _T_313) @[dma_ctrl.scala 216:217] + node _T_315 = eq(UInt<1>("h00"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 216:286] + node _T_316 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_315) @[dma_ctrl.scala 216:279] + node _T_317 = or(_T_314, _T_316) @[dma_ctrl.scala 216:236] + node _T_318 = eq(UInt<1>("h00"), io.iccm_dma_rtag) @[dma_ctrl.scala 216:359] + node _T_319 = and(io.iccm_dma_rvalid, _T_318) @[dma_ctrl.scala 216:352] + node _T_320 = or(_T_317, _T_319) @[dma_ctrl.scala 216:330] + node _T_321 = orr(fifo_error[1]) @[dma_ctrl.scala 216:74] + node _T_322 = bits(fifo_error_en, 1, 1) @[dma_ctrl.scala 216:93] + node _T_323 = or(_T_321, _T_322) @[dma_ctrl.scala 216:78] + node _T_324 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 216:137] + node _T_325 = and(_T_324, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 216:176] + node _T_326 = or(_T_323, _T_325) @[dma_ctrl.scala 216:97] + node _T_327 = eq(UInt<1>("h01"), RdPtr) @[dma_ctrl.scala 216:224] + node _T_328 = and(_T_326, _T_327) @[dma_ctrl.scala 216:217] + node _T_329 = eq(UInt<1>("h01"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 216:286] + node _T_330 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_329) @[dma_ctrl.scala 216:279] + node _T_331 = or(_T_328, _T_330) @[dma_ctrl.scala 216:236] + node _T_332 = eq(UInt<1>("h01"), io.iccm_dma_rtag) @[dma_ctrl.scala 216:359] + node _T_333 = and(io.iccm_dma_rvalid, _T_332) @[dma_ctrl.scala 216:352] + node _T_334 = or(_T_331, _T_333) @[dma_ctrl.scala 216:330] + node _T_335 = orr(fifo_error[2]) @[dma_ctrl.scala 216:74] + node _T_336 = bits(fifo_error_en, 2, 2) @[dma_ctrl.scala 216:93] + node _T_337 = or(_T_335, _T_336) @[dma_ctrl.scala 216:78] + node _T_338 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 216:137] + node _T_339 = and(_T_338, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 216:176] + node _T_340 = or(_T_337, _T_339) @[dma_ctrl.scala 216:97] + node _T_341 = eq(UInt<2>("h02"), RdPtr) @[dma_ctrl.scala 216:224] + node _T_342 = and(_T_340, _T_341) @[dma_ctrl.scala 216:217] + node _T_343 = eq(UInt<2>("h02"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 216:286] + node _T_344 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_343) @[dma_ctrl.scala 216:279] + node _T_345 = or(_T_342, _T_344) @[dma_ctrl.scala 216:236] + node _T_346 = eq(UInt<2>("h02"), io.iccm_dma_rtag) @[dma_ctrl.scala 216:359] + node _T_347 = and(io.iccm_dma_rvalid, _T_346) @[dma_ctrl.scala 216:352] + node _T_348 = or(_T_345, _T_347) @[dma_ctrl.scala 216:330] + node _T_349 = orr(fifo_error[3]) @[dma_ctrl.scala 216:74] + node _T_350 = bits(fifo_error_en, 3, 3) @[dma_ctrl.scala 216:93] + node _T_351 = or(_T_349, _T_350) @[dma_ctrl.scala 216:78] + node _T_352 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 216:137] + node _T_353 = and(_T_352, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 216:176] + node _T_354 = or(_T_351, _T_353) @[dma_ctrl.scala 216:97] + node _T_355 = eq(UInt<2>("h03"), RdPtr) @[dma_ctrl.scala 216:224] + node _T_356 = and(_T_354, _T_355) @[dma_ctrl.scala 216:217] + node _T_357 = eq(UInt<2>("h03"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 216:286] + node _T_358 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_357) @[dma_ctrl.scala 216:279] + node _T_359 = or(_T_356, _T_358) @[dma_ctrl.scala 216:236] + node _T_360 = eq(UInt<2>("h03"), io.iccm_dma_rtag) @[dma_ctrl.scala 216:359] + node _T_361 = and(io.iccm_dma_rvalid, _T_360) @[dma_ctrl.scala 216:352] + node _T_362 = or(_T_359, _T_361) @[dma_ctrl.scala 216:330] + node _T_363 = orr(fifo_error[4]) @[dma_ctrl.scala 216:74] + node _T_364 = bits(fifo_error_en, 4, 4) @[dma_ctrl.scala 216:93] + node _T_365 = or(_T_363, _T_364) @[dma_ctrl.scala 216:78] + node _T_366 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 216:137] + node _T_367 = and(_T_366, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 216:176] + node _T_368 = or(_T_365, _T_367) @[dma_ctrl.scala 216:97] + node _T_369 = eq(UInt<3>("h04"), RdPtr) @[dma_ctrl.scala 216:224] + node _T_370 = and(_T_368, _T_369) @[dma_ctrl.scala 216:217] + node _T_371 = eq(UInt<3>("h04"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 216:286] + node _T_372 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_371) @[dma_ctrl.scala 216:279] + node _T_373 = or(_T_370, _T_372) @[dma_ctrl.scala 216:236] + node _T_374 = eq(UInt<3>("h04"), io.iccm_dma_rtag) @[dma_ctrl.scala 216:359] + node _T_375 = and(io.iccm_dma_rvalid, _T_374) @[dma_ctrl.scala 216:352] + node _T_376 = or(_T_373, _T_375) @[dma_ctrl.scala 216:330] node _T_377 = cat(_T_376, _T_362) @[Cat.scala 29:58] node _T_378 = cat(_T_377, _T_348) @[Cat.scala 29:58] node _T_379 = cat(_T_378, _T_334) @[Cat.scala 29:58] node _T_380 = cat(_T_379, _T_320) @[Cat.scala 29:58] - fifo_done_en <= _T_380 @[dma_ctrl.scala 222:21] - node _T_381 = bits(fifo_done_en, 0, 0) @[dma_ctrl.scala 224:71] - node _T_382 = bits(fifo_done, 0, 0) @[dma_ctrl.scala 224:86] - node _T_383 = or(_T_381, _T_382) @[dma_ctrl.scala 224:75] - node _T_384 = and(_T_383, io.dma_bus_clk_en) @[dma_ctrl.scala 224:91] - node _T_385 = bits(fifo_done_en, 1, 1) @[dma_ctrl.scala 224:71] - node _T_386 = bits(fifo_done, 1, 1) @[dma_ctrl.scala 224:86] - node _T_387 = or(_T_385, _T_386) @[dma_ctrl.scala 224:75] - node _T_388 = and(_T_387, io.dma_bus_clk_en) @[dma_ctrl.scala 224:91] - node _T_389 = bits(fifo_done_en, 2, 2) @[dma_ctrl.scala 224:71] - node _T_390 = bits(fifo_done, 2, 2) @[dma_ctrl.scala 224:86] - node _T_391 = or(_T_389, _T_390) @[dma_ctrl.scala 224:75] - node _T_392 = and(_T_391, io.dma_bus_clk_en) @[dma_ctrl.scala 224:91] - node _T_393 = bits(fifo_done_en, 3, 3) @[dma_ctrl.scala 224:71] - node _T_394 = bits(fifo_done, 3, 3) @[dma_ctrl.scala 224:86] - node _T_395 = or(_T_393, _T_394) @[dma_ctrl.scala 224:75] - node _T_396 = and(_T_395, io.dma_bus_clk_en) @[dma_ctrl.scala 224:91] - node _T_397 = bits(fifo_done_en, 4, 4) @[dma_ctrl.scala 224:71] - node _T_398 = bits(fifo_done, 4, 4) @[dma_ctrl.scala 224:86] - node _T_399 = or(_T_397, _T_398) @[dma_ctrl.scala 224:75] - node _T_400 = and(_T_399, io.dma_bus_clk_en) @[dma_ctrl.scala 224:91] + fifo_done_en <= _T_380 @[dma_ctrl.scala 216:21] + node _T_381 = bits(fifo_done_en, 0, 0) @[dma_ctrl.scala 218:71] + node _T_382 = bits(fifo_done, 0, 0) @[dma_ctrl.scala 218:86] + node _T_383 = or(_T_381, _T_382) @[dma_ctrl.scala 218:75] + node _T_384 = and(_T_383, io.dma_bus_clk_en) @[dma_ctrl.scala 218:91] + node _T_385 = bits(fifo_done_en, 1, 1) @[dma_ctrl.scala 218:71] + node _T_386 = bits(fifo_done, 1, 1) @[dma_ctrl.scala 218:86] + node _T_387 = or(_T_385, _T_386) @[dma_ctrl.scala 218:75] + node _T_388 = and(_T_387, io.dma_bus_clk_en) @[dma_ctrl.scala 218:91] + node _T_389 = bits(fifo_done_en, 2, 2) @[dma_ctrl.scala 218:71] + node _T_390 = bits(fifo_done, 2, 2) @[dma_ctrl.scala 218:86] + node _T_391 = or(_T_389, _T_390) @[dma_ctrl.scala 218:75] + node _T_392 = and(_T_391, io.dma_bus_clk_en) @[dma_ctrl.scala 218:91] + node _T_393 = bits(fifo_done_en, 3, 3) @[dma_ctrl.scala 218:71] + node _T_394 = bits(fifo_done, 3, 3) @[dma_ctrl.scala 218:86] + node _T_395 = or(_T_393, _T_394) @[dma_ctrl.scala 218:75] + node _T_396 = and(_T_395, io.dma_bus_clk_en) @[dma_ctrl.scala 218:91] + node _T_397 = bits(fifo_done_en, 4, 4) @[dma_ctrl.scala 218:71] + node _T_398 = bits(fifo_done, 4, 4) @[dma_ctrl.scala 218:86] + node _T_399 = or(_T_397, _T_398) @[dma_ctrl.scala 218:75] + node _T_400 = and(_T_399, io.dma_bus_clk_en) @[dma_ctrl.scala 218:91] node _T_401 = cat(_T_400, _T_396) @[Cat.scala 29:58] node _T_402 = cat(_T_401, _T_392) @[Cat.scala 29:58] node _T_403 = cat(_T_402, _T_388) @[Cat.scala 29:58] node _T_404 = cat(_T_403, _T_384) @[Cat.scala 29:58] - fifo_done_bus_en <= _T_404 @[dma_ctrl.scala 224:21] - node _T_405 = or(bus_rsp_sent, bus_posted_write_done) @[dma_ctrl.scala 226:74] - node _T_406 = and(_T_405, io.dma_bus_clk_en) @[dma_ctrl.scala 226:99] - node _T_407 = or(_T_406, io.dma_dbg_cmd_done) @[dma_ctrl.scala 226:120] - node _T_408 = eq(UInt<1>("h00"), RspPtr) @[dma_ctrl.scala 226:150] - node _T_409 = and(_T_407, _T_408) @[dma_ctrl.scala 226:143] - node _T_410 = or(bus_rsp_sent, bus_posted_write_done) @[dma_ctrl.scala 226:74] - node _T_411 = and(_T_410, io.dma_bus_clk_en) @[dma_ctrl.scala 226:99] - node _T_412 = or(_T_411, io.dma_dbg_cmd_done) @[dma_ctrl.scala 226:120] - node _T_413 = eq(UInt<1>("h01"), RspPtr) @[dma_ctrl.scala 226:150] - node _T_414 = and(_T_412, _T_413) @[dma_ctrl.scala 226:143] - node _T_415 = or(bus_rsp_sent, bus_posted_write_done) @[dma_ctrl.scala 226:74] - node _T_416 = and(_T_415, io.dma_bus_clk_en) @[dma_ctrl.scala 226:99] - node _T_417 = or(_T_416, io.dma_dbg_cmd_done) @[dma_ctrl.scala 226:120] - node _T_418 = eq(UInt<2>("h02"), RspPtr) @[dma_ctrl.scala 226:150] - node _T_419 = and(_T_417, _T_418) @[dma_ctrl.scala 226:143] - node _T_420 = or(bus_rsp_sent, bus_posted_write_done) @[dma_ctrl.scala 226:74] - node _T_421 = and(_T_420, io.dma_bus_clk_en) @[dma_ctrl.scala 226:99] - node _T_422 = or(_T_421, io.dma_dbg_cmd_done) @[dma_ctrl.scala 226:120] - node _T_423 = eq(UInt<2>("h03"), RspPtr) @[dma_ctrl.scala 226:150] - node _T_424 = and(_T_422, _T_423) @[dma_ctrl.scala 226:143] - node _T_425 = or(bus_rsp_sent, bus_posted_write_done) @[dma_ctrl.scala 226:74] - node _T_426 = and(_T_425, io.dma_bus_clk_en) @[dma_ctrl.scala 226:99] - node _T_427 = or(_T_426, io.dma_dbg_cmd_done) @[dma_ctrl.scala 226:120] - node _T_428 = eq(UInt<3>("h04"), RspPtr) @[dma_ctrl.scala 226:150] - node _T_429 = and(_T_427, _T_428) @[dma_ctrl.scala 226:143] + fifo_done_bus_en <= _T_404 @[dma_ctrl.scala 218:21] + node _T_405 = or(bus_rsp_sent, bus_posted_write_done) @[dma_ctrl.scala 220:74] + node _T_406 = and(_T_405, io.dma_bus_clk_en) @[dma_ctrl.scala 220:99] + node _T_407 = or(_T_406, io.dma_dbg_cmd_done) @[dma_ctrl.scala 220:120] + node _T_408 = eq(UInt<1>("h00"), RspPtr) @[dma_ctrl.scala 220:150] + node _T_409 = and(_T_407, _T_408) @[dma_ctrl.scala 220:143] + node _T_410 = or(bus_rsp_sent, bus_posted_write_done) @[dma_ctrl.scala 220:74] + node _T_411 = and(_T_410, io.dma_bus_clk_en) @[dma_ctrl.scala 220:99] + node _T_412 = or(_T_411, io.dma_dbg_cmd_done) @[dma_ctrl.scala 220:120] + node _T_413 = eq(UInt<1>("h01"), RspPtr) @[dma_ctrl.scala 220:150] + node _T_414 = and(_T_412, _T_413) @[dma_ctrl.scala 220:143] + node _T_415 = or(bus_rsp_sent, bus_posted_write_done) @[dma_ctrl.scala 220:74] + node _T_416 = and(_T_415, io.dma_bus_clk_en) @[dma_ctrl.scala 220:99] + node _T_417 = or(_T_416, io.dma_dbg_cmd_done) @[dma_ctrl.scala 220:120] + node _T_418 = eq(UInt<2>("h02"), RspPtr) @[dma_ctrl.scala 220:150] + node _T_419 = and(_T_417, _T_418) @[dma_ctrl.scala 220:143] + node _T_420 = or(bus_rsp_sent, bus_posted_write_done) @[dma_ctrl.scala 220:74] + node _T_421 = and(_T_420, io.dma_bus_clk_en) @[dma_ctrl.scala 220:99] + node _T_422 = or(_T_421, io.dma_dbg_cmd_done) @[dma_ctrl.scala 220:120] + node _T_423 = eq(UInt<2>("h03"), RspPtr) @[dma_ctrl.scala 220:150] + node _T_424 = and(_T_422, _T_423) @[dma_ctrl.scala 220:143] + node _T_425 = or(bus_rsp_sent, bus_posted_write_done) @[dma_ctrl.scala 220:74] + node _T_426 = and(_T_425, io.dma_bus_clk_en) @[dma_ctrl.scala 220:99] + node _T_427 = or(_T_426, io.dma_dbg_cmd_done) @[dma_ctrl.scala 220:120] + node _T_428 = eq(UInt<3>("h04"), RspPtr) @[dma_ctrl.scala 220:150] + node _T_429 = and(_T_427, _T_428) @[dma_ctrl.scala 220:143] node _T_430 = cat(_T_429, _T_424) @[Cat.scala 29:58] node _T_431 = cat(_T_430, _T_419) @[Cat.scala 29:58] node _T_432 = cat(_T_431, _T_414) @[Cat.scala 29:58] node _T_433 = cat(_T_432, _T_409) @[Cat.scala 29:58] - fifo_reset <= _T_433 @[dma_ctrl.scala 226:21] - node _T_434 = eq(UInt<1>("h00"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 228:108] - node _T_435 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_434) @[dma_ctrl.scala 228:101] + fifo_reset <= _T_433 @[dma_ctrl.scala 220:21] + node _T_434 = eq(UInt<1>("h00"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 222:108] + node _T_435 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_434) @[dma_ctrl.scala 222:101] node _T_436 = cat(UInt<1>("h00"), io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error) @[Cat.scala 29:58] - node _T_437 = eq(UInt<1>("h00"), io.iccm_dma_rtag) @[dma_ctrl.scala 228:236] - node _T_438 = and(io.iccm_dma_rvalid, _T_437) @[dma_ctrl.scala 228:229] + node _T_437 = eq(UInt<1>("h00"), io.iccm_dma_rtag) @[dma_ctrl.scala 222:236] + node _T_438 = and(io.iccm_dma_rvalid, _T_437) @[dma_ctrl.scala 222:229] node _T_439 = cat(UInt<1>("h00"), io.iccm_dma_ecc_error) @[Cat.scala 29:58] - node _T_440 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 228:318] - node _T_441 = or(_T_440, dma_dbg_cmd_error) @[dma_ctrl.scala 228:340] + node _T_440 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 222:318] + node _T_441 = or(_T_440, dma_dbg_cmd_error) @[dma_ctrl.scala 222:340] node _T_442 = cat(_T_441, dma_alignment_error) @[Cat.scala 29:58] - node _T_443 = mux(_T_438, _T_439, _T_442) @[dma_ctrl.scala 228:209] - node _T_444 = mux(_T_435, _T_436, _T_443) @[dma_ctrl.scala 228:60] - fifo_error_in[0] <= _T_444 @[dma_ctrl.scala 228:53] - node _T_445 = eq(UInt<1>("h01"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 228:108] - node _T_446 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_445) @[dma_ctrl.scala 228:101] + node _T_443 = mux(_T_438, _T_439, _T_442) @[dma_ctrl.scala 222:209] + node _T_444 = mux(_T_435, _T_436, _T_443) @[dma_ctrl.scala 222:60] + fifo_error_in[0] <= _T_444 @[dma_ctrl.scala 222:53] + node _T_445 = eq(UInt<1>("h01"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 222:108] + node _T_446 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_445) @[dma_ctrl.scala 222:101] node _T_447 = cat(UInt<1>("h00"), io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error) @[Cat.scala 29:58] - node _T_448 = eq(UInt<1>("h01"), io.iccm_dma_rtag) @[dma_ctrl.scala 228:236] - node _T_449 = and(io.iccm_dma_rvalid, _T_448) @[dma_ctrl.scala 228:229] + node _T_448 = eq(UInt<1>("h01"), io.iccm_dma_rtag) @[dma_ctrl.scala 222:236] + node _T_449 = and(io.iccm_dma_rvalid, _T_448) @[dma_ctrl.scala 222:229] node _T_450 = cat(UInt<1>("h00"), io.iccm_dma_ecc_error) @[Cat.scala 29:58] - node _T_451 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 228:318] - node _T_452 = or(_T_451, dma_dbg_cmd_error) @[dma_ctrl.scala 228:340] + node _T_451 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 222:318] + node _T_452 = or(_T_451, dma_dbg_cmd_error) @[dma_ctrl.scala 222:340] node _T_453 = cat(_T_452, dma_alignment_error) @[Cat.scala 29:58] - node _T_454 = mux(_T_449, _T_450, _T_453) @[dma_ctrl.scala 228:209] - node _T_455 = mux(_T_446, _T_447, _T_454) @[dma_ctrl.scala 228:60] - fifo_error_in[1] <= _T_455 @[dma_ctrl.scala 228:53] - node _T_456 = eq(UInt<2>("h02"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 228:108] - node _T_457 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_456) @[dma_ctrl.scala 228:101] + node _T_454 = mux(_T_449, _T_450, _T_453) @[dma_ctrl.scala 222:209] + node _T_455 = mux(_T_446, _T_447, _T_454) @[dma_ctrl.scala 222:60] + fifo_error_in[1] <= _T_455 @[dma_ctrl.scala 222:53] + node _T_456 = eq(UInt<2>("h02"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 222:108] + node _T_457 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_456) @[dma_ctrl.scala 222:101] node _T_458 = cat(UInt<1>("h00"), io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error) @[Cat.scala 29:58] - node _T_459 = eq(UInt<2>("h02"), io.iccm_dma_rtag) @[dma_ctrl.scala 228:236] - node _T_460 = and(io.iccm_dma_rvalid, _T_459) @[dma_ctrl.scala 228:229] + node _T_459 = eq(UInt<2>("h02"), io.iccm_dma_rtag) @[dma_ctrl.scala 222:236] + node _T_460 = and(io.iccm_dma_rvalid, _T_459) @[dma_ctrl.scala 222:229] node _T_461 = cat(UInt<1>("h00"), io.iccm_dma_ecc_error) @[Cat.scala 29:58] - node _T_462 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 228:318] - node _T_463 = or(_T_462, dma_dbg_cmd_error) @[dma_ctrl.scala 228:340] + node _T_462 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 222:318] + node _T_463 = or(_T_462, dma_dbg_cmd_error) @[dma_ctrl.scala 222:340] node _T_464 = cat(_T_463, dma_alignment_error) @[Cat.scala 29:58] - node _T_465 = mux(_T_460, _T_461, _T_464) @[dma_ctrl.scala 228:209] - node _T_466 = mux(_T_457, _T_458, _T_465) @[dma_ctrl.scala 228:60] - fifo_error_in[2] <= _T_466 @[dma_ctrl.scala 228:53] - node _T_467 = eq(UInt<2>("h03"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 228:108] - node _T_468 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_467) @[dma_ctrl.scala 228:101] + node _T_465 = mux(_T_460, _T_461, _T_464) @[dma_ctrl.scala 222:209] + node _T_466 = mux(_T_457, _T_458, _T_465) @[dma_ctrl.scala 222:60] + fifo_error_in[2] <= _T_466 @[dma_ctrl.scala 222:53] + node _T_467 = eq(UInt<2>("h03"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 222:108] + node _T_468 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_467) @[dma_ctrl.scala 222:101] node _T_469 = cat(UInt<1>("h00"), io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error) @[Cat.scala 29:58] - node _T_470 = eq(UInt<2>("h03"), io.iccm_dma_rtag) @[dma_ctrl.scala 228:236] - node _T_471 = and(io.iccm_dma_rvalid, _T_470) @[dma_ctrl.scala 228:229] + node _T_470 = eq(UInt<2>("h03"), io.iccm_dma_rtag) @[dma_ctrl.scala 222:236] + node _T_471 = and(io.iccm_dma_rvalid, _T_470) @[dma_ctrl.scala 222:229] node _T_472 = cat(UInt<1>("h00"), io.iccm_dma_ecc_error) @[Cat.scala 29:58] - node _T_473 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 228:318] - node _T_474 = or(_T_473, dma_dbg_cmd_error) @[dma_ctrl.scala 228:340] + node _T_473 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 222:318] + node _T_474 = or(_T_473, dma_dbg_cmd_error) @[dma_ctrl.scala 222:340] node _T_475 = cat(_T_474, dma_alignment_error) @[Cat.scala 29:58] - node _T_476 = mux(_T_471, _T_472, _T_475) @[dma_ctrl.scala 228:209] - node _T_477 = mux(_T_468, _T_469, _T_476) @[dma_ctrl.scala 228:60] - fifo_error_in[3] <= _T_477 @[dma_ctrl.scala 228:53] - node _T_478 = eq(UInt<3>("h04"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 228:108] - node _T_479 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_478) @[dma_ctrl.scala 228:101] + node _T_476 = mux(_T_471, _T_472, _T_475) @[dma_ctrl.scala 222:209] + node _T_477 = mux(_T_468, _T_469, _T_476) @[dma_ctrl.scala 222:60] + fifo_error_in[3] <= _T_477 @[dma_ctrl.scala 222:53] + node _T_478 = eq(UInt<3>("h04"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 222:108] + node _T_479 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_478) @[dma_ctrl.scala 222:101] node _T_480 = cat(UInt<1>("h00"), io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error) @[Cat.scala 29:58] - node _T_481 = eq(UInt<3>("h04"), io.iccm_dma_rtag) @[dma_ctrl.scala 228:236] - node _T_482 = and(io.iccm_dma_rvalid, _T_481) @[dma_ctrl.scala 228:229] + node _T_481 = eq(UInt<3>("h04"), io.iccm_dma_rtag) @[dma_ctrl.scala 222:236] + node _T_482 = and(io.iccm_dma_rvalid, _T_481) @[dma_ctrl.scala 222:229] node _T_483 = cat(UInt<1>("h00"), io.iccm_dma_ecc_error) @[Cat.scala 29:58] - node _T_484 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 228:318] - node _T_485 = or(_T_484, dma_dbg_cmd_error) @[dma_ctrl.scala 228:340] + node _T_484 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 222:318] + node _T_485 = or(_T_484, dma_dbg_cmd_error) @[dma_ctrl.scala 222:340] node _T_486 = cat(_T_485, dma_alignment_error) @[Cat.scala 29:58] - node _T_487 = mux(_T_482, _T_483, _T_486) @[dma_ctrl.scala 228:209] - node _T_488 = mux(_T_479, _T_480, _T_487) @[dma_ctrl.scala 228:60] - fifo_error_in[4] <= _T_488 @[dma_ctrl.scala 228:53] - node _T_489 = bits(fifo_error_en, 0, 0) @[dma_ctrl.scala 230:73] - node _T_490 = orr(fifo_error_in[0]) @[dma_ctrl.scala 230:97] - node _T_491 = and(_T_489, _T_490) @[dma_ctrl.scala 230:77] + node _T_487 = mux(_T_482, _T_483, _T_486) @[dma_ctrl.scala 222:209] + node _T_488 = mux(_T_479, _T_480, _T_487) @[dma_ctrl.scala 222:60] + fifo_error_in[4] <= _T_488 @[dma_ctrl.scala 222:53] + node _T_489 = bits(fifo_error_en, 0, 0) @[dma_ctrl.scala 224:73] + node _T_490 = orr(fifo_error_in[0]) @[dma_ctrl.scala 224:97] + node _T_491 = and(_T_489, _T_490) @[dma_ctrl.scala 224:77] node _T_492 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] node _T_493 = cat(_T_492, fifo_addr[0]) @[Cat.scala 29:58] - node _T_494 = eq(UInt<1>("h00"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 230:188] - node _T_495 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_494) @[dma_ctrl.scala 230:181] - node _T_496 = eq(UInt<1>("h00"), io.iccm_dma_rtag) @[dma_ctrl.scala 230:302] - node _T_497 = and(io.iccm_dma_rvalid, _T_496) @[dma_ctrl.scala 230:295] + node _T_494 = eq(UInt<1>("h00"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 224:188] + node _T_495 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_494) @[dma_ctrl.scala 224:181] + node _T_496 = eq(UInt<1>("h00"), io.iccm_dma_rtag) @[dma_ctrl.scala 224:302] + node _T_497 = and(io.iccm_dma_rvalid, _T_496) @[dma_ctrl.scala 224:295] node _T_498 = cat(io.dbg_dma.dbg_dctl.dbg_cmd_wrdata, io.dbg_dma.dbg_dctl.dbg_cmd_wrdata) @[Cat.scala 29:58] - node _T_499 = bits(bus_cmd_wdata, 63, 0) @[dma_ctrl.scala 230:439] - node _T_500 = mux(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_498, _T_499) @[dma_ctrl.scala 230:347] - node _T_501 = mux(_T_497, io.iccm_dma_rdata, _T_500) @[dma_ctrl.scala 230:275] - node _T_502 = mux(_T_495, io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata, _T_501) @[dma_ctrl.scala 230:140] - node _T_503 = mux(_T_491, _T_493, _T_502) @[dma_ctrl.scala 230:59] - fifo_data_in[0] <= _T_503 @[dma_ctrl.scala 230:52] - node _T_504 = bits(fifo_error_en, 1, 1) @[dma_ctrl.scala 230:73] - node _T_505 = orr(fifo_error_in[1]) @[dma_ctrl.scala 230:97] - node _T_506 = and(_T_504, _T_505) @[dma_ctrl.scala 230:77] + node _T_499 = bits(bus_cmd_wdata, 63, 0) @[dma_ctrl.scala 224:439] + node _T_500 = mux(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_498, _T_499) @[dma_ctrl.scala 224:347] + node _T_501 = mux(_T_497, io.iccm_dma_rdata, _T_500) @[dma_ctrl.scala 224:275] + node _T_502 = mux(_T_495, io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata, _T_501) @[dma_ctrl.scala 224:140] + node _T_503 = mux(_T_491, _T_493, _T_502) @[dma_ctrl.scala 224:59] + fifo_data_in[0] <= _T_503 @[dma_ctrl.scala 224:52] + node _T_504 = bits(fifo_error_en, 1, 1) @[dma_ctrl.scala 224:73] + node _T_505 = orr(fifo_error_in[1]) @[dma_ctrl.scala 224:97] + node _T_506 = and(_T_504, _T_505) @[dma_ctrl.scala 224:77] node _T_507 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] node _T_508 = cat(_T_507, fifo_addr[1]) @[Cat.scala 29:58] - node _T_509 = eq(UInt<1>("h01"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 230:188] - node _T_510 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_509) @[dma_ctrl.scala 230:181] - node _T_511 = eq(UInt<1>("h01"), io.iccm_dma_rtag) @[dma_ctrl.scala 230:302] - node _T_512 = and(io.iccm_dma_rvalid, _T_511) @[dma_ctrl.scala 230:295] + node _T_509 = eq(UInt<1>("h01"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 224:188] + node _T_510 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_509) @[dma_ctrl.scala 224:181] + node _T_511 = eq(UInt<1>("h01"), io.iccm_dma_rtag) @[dma_ctrl.scala 224:302] + node _T_512 = and(io.iccm_dma_rvalid, _T_511) @[dma_ctrl.scala 224:295] node _T_513 = cat(io.dbg_dma.dbg_dctl.dbg_cmd_wrdata, io.dbg_dma.dbg_dctl.dbg_cmd_wrdata) @[Cat.scala 29:58] - node _T_514 = bits(bus_cmd_wdata, 63, 0) @[dma_ctrl.scala 230:439] - node _T_515 = mux(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_513, _T_514) @[dma_ctrl.scala 230:347] - node _T_516 = mux(_T_512, io.iccm_dma_rdata, _T_515) @[dma_ctrl.scala 230:275] - node _T_517 = mux(_T_510, io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata, _T_516) @[dma_ctrl.scala 230:140] - node _T_518 = mux(_T_506, _T_508, _T_517) @[dma_ctrl.scala 230:59] - fifo_data_in[1] <= _T_518 @[dma_ctrl.scala 230:52] - node _T_519 = bits(fifo_error_en, 2, 2) @[dma_ctrl.scala 230:73] - node _T_520 = orr(fifo_error_in[2]) @[dma_ctrl.scala 230:97] - node _T_521 = and(_T_519, _T_520) @[dma_ctrl.scala 230:77] + node _T_514 = bits(bus_cmd_wdata, 63, 0) @[dma_ctrl.scala 224:439] + node _T_515 = mux(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_513, _T_514) @[dma_ctrl.scala 224:347] + node _T_516 = mux(_T_512, io.iccm_dma_rdata, _T_515) @[dma_ctrl.scala 224:275] + node _T_517 = mux(_T_510, io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata, _T_516) @[dma_ctrl.scala 224:140] + node _T_518 = mux(_T_506, _T_508, _T_517) @[dma_ctrl.scala 224:59] + fifo_data_in[1] <= _T_518 @[dma_ctrl.scala 224:52] + node _T_519 = bits(fifo_error_en, 2, 2) @[dma_ctrl.scala 224:73] + node _T_520 = orr(fifo_error_in[2]) @[dma_ctrl.scala 224:97] + node _T_521 = and(_T_519, _T_520) @[dma_ctrl.scala 224:77] node _T_522 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] node _T_523 = cat(_T_522, fifo_addr[2]) @[Cat.scala 29:58] - node _T_524 = eq(UInt<2>("h02"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 230:188] - node _T_525 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_524) @[dma_ctrl.scala 230:181] - node _T_526 = eq(UInt<2>("h02"), io.iccm_dma_rtag) @[dma_ctrl.scala 230:302] - node _T_527 = and(io.iccm_dma_rvalid, _T_526) @[dma_ctrl.scala 230:295] + node _T_524 = eq(UInt<2>("h02"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 224:188] + node _T_525 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_524) @[dma_ctrl.scala 224:181] + node _T_526 = eq(UInt<2>("h02"), io.iccm_dma_rtag) @[dma_ctrl.scala 224:302] + node _T_527 = and(io.iccm_dma_rvalid, _T_526) @[dma_ctrl.scala 224:295] node _T_528 = cat(io.dbg_dma.dbg_dctl.dbg_cmd_wrdata, io.dbg_dma.dbg_dctl.dbg_cmd_wrdata) @[Cat.scala 29:58] - node _T_529 = bits(bus_cmd_wdata, 63, 0) @[dma_ctrl.scala 230:439] - node _T_530 = mux(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_528, _T_529) @[dma_ctrl.scala 230:347] - node _T_531 = mux(_T_527, io.iccm_dma_rdata, _T_530) @[dma_ctrl.scala 230:275] - node _T_532 = mux(_T_525, io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata, _T_531) @[dma_ctrl.scala 230:140] - node _T_533 = mux(_T_521, _T_523, _T_532) @[dma_ctrl.scala 230:59] - fifo_data_in[2] <= _T_533 @[dma_ctrl.scala 230:52] - node _T_534 = bits(fifo_error_en, 3, 3) @[dma_ctrl.scala 230:73] - node _T_535 = orr(fifo_error_in[3]) @[dma_ctrl.scala 230:97] - node _T_536 = and(_T_534, _T_535) @[dma_ctrl.scala 230:77] + node _T_529 = bits(bus_cmd_wdata, 63, 0) @[dma_ctrl.scala 224:439] + node _T_530 = mux(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_528, _T_529) @[dma_ctrl.scala 224:347] + node _T_531 = mux(_T_527, io.iccm_dma_rdata, _T_530) @[dma_ctrl.scala 224:275] + node _T_532 = mux(_T_525, io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata, _T_531) @[dma_ctrl.scala 224:140] + node _T_533 = mux(_T_521, _T_523, _T_532) @[dma_ctrl.scala 224:59] + fifo_data_in[2] <= _T_533 @[dma_ctrl.scala 224:52] + node _T_534 = bits(fifo_error_en, 3, 3) @[dma_ctrl.scala 224:73] + node _T_535 = orr(fifo_error_in[3]) @[dma_ctrl.scala 224:97] + node _T_536 = and(_T_534, _T_535) @[dma_ctrl.scala 224:77] node _T_537 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] node _T_538 = cat(_T_537, fifo_addr[3]) @[Cat.scala 29:58] - node _T_539 = eq(UInt<2>("h03"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 230:188] - node _T_540 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_539) @[dma_ctrl.scala 230:181] - node _T_541 = eq(UInt<2>("h03"), io.iccm_dma_rtag) @[dma_ctrl.scala 230:302] - node _T_542 = and(io.iccm_dma_rvalid, _T_541) @[dma_ctrl.scala 230:295] + node _T_539 = eq(UInt<2>("h03"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 224:188] + node _T_540 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_539) @[dma_ctrl.scala 224:181] + node _T_541 = eq(UInt<2>("h03"), io.iccm_dma_rtag) @[dma_ctrl.scala 224:302] + node _T_542 = and(io.iccm_dma_rvalid, _T_541) @[dma_ctrl.scala 224:295] node _T_543 = cat(io.dbg_dma.dbg_dctl.dbg_cmd_wrdata, io.dbg_dma.dbg_dctl.dbg_cmd_wrdata) @[Cat.scala 29:58] - node _T_544 = bits(bus_cmd_wdata, 63, 0) @[dma_ctrl.scala 230:439] - node _T_545 = mux(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_543, _T_544) @[dma_ctrl.scala 230:347] - node _T_546 = mux(_T_542, io.iccm_dma_rdata, _T_545) @[dma_ctrl.scala 230:275] - node _T_547 = mux(_T_540, io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata, _T_546) @[dma_ctrl.scala 230:140] - node _T_548 = mux(_T_536, _T_538, _T_547) @[dma_ctrl.scala 230:59] - fifo_data_in[3] <= _T_548 @[dma_ctrl.scala 230:52] - node _T_549 = bits(fifo_error_en, 4, 4) @[dma_ctrl.scala 230:73] - node _T_550 = orr(fifo_error_in[4]) @[dma_ctrl.scala 230:97] - node _T_551 = and(_T_549, _T_550) @[dma_ctrl.scala 230:77] + node _T_544 = bits(bus_cmd_wdata, 63, 0) @[dma_ctrl.scala 224:439] + node _T_545 = mux(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_543, _T_544) @[dma_ctrl.scala 224:347] + node _T_546 = mux(_T_542, io.iccm_dma_rdata, _T_545) @[dma_ctrl.scala 224:275] + node _T_547 = mux(_T_540, io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata, _T_546) @[dma_ctrl.scala 224:140] + node _T_548 = mux(_T_536, _T_538, _T_547) @[dma_ctrl.scala 224:59] + fifo_data_in[3] <= _T_548 @[dma_ctrl.scala 224:52] + node _T_549 = bits(fifo_error_en, 4, 4) @[dma_ctrl.scala 224:73] + node _T_550 = orr(fifo_error_in[4]) @[dma_ctrl.scala 224:97] + node _T_551 = and(_T_549, _T_550) @[dma_ctrl.scala 224:77] node _T_552 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] node _T_553 = cat(_T_552, fifo_addr[4]) @[Cat.scala 29:58] - node _T_554 = eq(UInt<3>("h04"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 230:188] - node _T_555 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_554) @[dma_ctrl.scala 230:181] - node _T_556 = eq(UInt<3>("h04"), io.iccm_dma_rtag) @[dma_ctrl.scala 230:302] - node _T_557 = and(io.iccm_dma_rvalid, _T_556) @[dma_ctrl.scala 230:295] + node _T_554 = eq(UInt<3>("h04"), io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag) @[dma_ctrl.scala 224:188] + node _T_555 = and(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid, _T_554) @[dma_ctrl.scala 224:181] + node _T_556 = eq(UInt<3>("h04"), io.iccm_dma_rtag) @[dma_ctrl.scala 224:302] + node _T_557 = and(io.iccm_dma_rvalid, _T_556) @[dma_ctrl.scala 224:295] node _T_558 = cat(io.dbg_dma.dbg_dctl.dbg_cmd_wrdata, io.dbg_dma.dbg_dctl.dbg_cmd_wrdata) @[Cat.scala 29:58] - node _T_559 = bits(bus_cmd_wdata, 63, 0) @[dma_ctrl.scala 230:439] - node _T_560 = mux(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_558, _T_559) @[dma_ctrl.scala 230:347] - node _T_561 = mux(_T_557, io.iccm_dma_rdata, _T_560) @[dma_ctrl.scala 230:275] - node _T_562 = mux(_T_555, io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata, _T_561) @[dma_ctrl.scala 230:140] - node _T_563 = mux(_T_551, _T_553, _T_562) @[dma_ctrl.scala 230:59] - fifo_data_in[4] <= _T_563 @[dma_ctrl.scala 230:52] - node _T_564 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 232:98] - node _T_565 = bits(fifo_valid, 0, 0) @[dma_ctrl.scala 232:118] - node _T_566 = mux(_T_564, UInt<1>("h01"), _T_565) @[dma_ctrl.scala 232:86] - node _T_567 = bits(fifo_reset, 0, 0) @[dma_ctrl.scala 232:136] - node _T_568 = eq(_T_567, UInt<1>("h00")) @[dma_ctrl.scala 232:125] - node _T_569 = and(_T_566, _T_568) @[dma_ctrl.scala 232:123] - reg _T_570 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 232:82] - _T_570 <= _T_569 @[dma_ctrl.scala 232:82] - node _T_571 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 232:98] - node _T_572 = bits(fifo_valid, 1, 1) @[dma_ctrl.scala 232:118] - node _T_573 = mux(_T_571, UInt<1>("h01"), _T_572) @[dma_ctrl.scala 232:86] - node _T_574 = bits(fifo_reset, 1, 1) @[dma_ctrl.scala 232:136] - node _T_575 = eq(_T_574, UInt<1>("h00")) @[dma_ctrl.scala 232:125] - node _T_576 = and(_T_573, _T_575) @[dma_ctrl.scala 232:123] - reg _T_577 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 232:82] - _T_577 <= _T_576 @[dma_ctrl.scala 232:82] - node _T_578 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 232:98] - node _T_579 = bits(fifo_valid, 2, 2) @[dma_ctrl.scala 232:118] - node _T_580 = mux(_T_578, UInt<1>("h01"), _T_579) @[dma_ctrl.scala 232:86] - node _T_581 = bits(fifo_reset, 2, 2) @[dma_ctrl.scala 232:136] - node _T_582 = eq(_T_581, UInt<1>("h00")) @[dma_ctrl.scala 232:125] - node _T_583 = and(_T_580, _T_582) @[dma_ctrl.scala 232:123] - reg _T_584 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 232:82] - _T_584 <= _T_583 @[dma_ctrl.scala 232:82] - node _T_585 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 232:98] - node _T_586 = bits(fifo_valid, 3, 3) @[dma_ctrl.scala 232:118] - node _T_587 = mux(_T_585, UInt<1>("h01"), _T_586) @[dma_ctrl.scala 232:86] - node _T_588 = bits(fifo_reset, 3, 3) @[dma_ctrl.scala 232:136] - node _T_589 = eq(_T_588, UInt<1>("h00")) @[dma_ctrl.scala 232:125] - node _T_590 = and(_T_587, _T_589) @[dma_ctrl.scala 232:123] - reg _T_591 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 232:82] - _T_591 <= _T_590 @[dma_ctrl.scala 232:82] - node _T_592 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 232:98] - node _T_593 = bits(fifo_valid, 4, 4) @[dma_ctrl.scala 232:118] - node _T_594 = mux(_T_592, UInt<1>("h01"), _T_593) @[dma_ctrl.scala 232:86] - node _T_595 = bits(fifo_reset, 4, 4) @[dma_ctrl.scala 232:136] - node _T_596 = eq(_T_595, UInt<1>("h00")) @[dma_ctrl.scala 232:125] - node _T_597 = and(_T_594, _T_596) @[dma_ctrl.scala 232:123] - reg _T_598 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 232:82] - _T_598 <= _T_597 @[dma_ctrl.scala 232:82] + node _T_559 = bits(bus_cmd_wdata, 63, 0) @[dma_ctrl.scala 224:439] + node _T_560 = mux(io.dbg_dma.dbg_ib.dbg_cmd_valid, _T_558, _T_559) @[dma_ctrl.scala 224:347] + node _T_561 = mux(_T_557, io.iccm_dma_rdata, _T_560) @[dma_ctrl.scala 224:275] + node _T_562 = mux(_T_555, io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata, _T_561) @[dma_ctrl.scala 224:140] + node _T_563 = mux(_T_551, _T_553, _T_562) @[dma_ctrl.scala 224:59] + fifo_data_in[4] <= _T_563 @[dma_ctrl.scala 224:52] + node _T_564 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 226:98] + node _T_565 = bits(fifo_valid, 0, 0) @[dma_ctrl.scala 226:118] + node _T_566 = mux(_T_564, UInt<1>("h01"), _T_565) @[dma_ctrl.scala 226:86] + node _T_567 = bits(fifo_reset, 0, 0) @[dma_ctrl.scala 226:136] + node _T_568 = eq(_T_567, UInt<1>("h00")) @[dma_ctrl.scala 226:125] + node _T_569 = and(_T_566, _T_568) @[dma_ctrl.scala 226:123] + reg _T_570 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 226:82] + _T_570 <= _T_569 @[dma_ctrl.scala 226:82] + node _T_571 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 226:98] + node _T_572 = bits(fifo_valid, 1, 1) @[dma_ctrl.scala 226:118] + node _T_573 = mux(_T_571, UInt<1>("h01"), _T_572) @[dma_ctrl.scala 226:86] + node _T_574 = bits(fifo_reset, 1, 1) @[dma_ctrl.scala 226:136] + node _T_575 = eq(_T_574, UInt<1>("h00")) @[dma_ctrl.scala 226:125] + node _T_576 = and(_T_573, _T_575) @[dma_ctrl.scala 226:123] + reg _T_577 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 226:82] + _T_577 <= _T_576 @[dma_ctrl.scala 226:82] + node _T_578 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 226:98] + node _T_579 = bits(fifo_valid, 2, 2) @[dma_ctrl.scala 226:118] + node _T_580 = mux(_T_578, UInt<1>("h01"), _T_579) @[dma_ctrl.scala 226:86] + node _T_581 = bits(fifo_reset, 2, 2) @[dma_ctrl.scala 226:136] + node _T_582 = eq(_T_581, UInt<1>("h00")) @[dma_ctrl.scala 226:125] + node _T_583 = and(_T_580, _T_582) @[dma_ctrl.scala 226:123] + reg _T_584 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 226:82] + _T_584 <= _T_583 @[dma_ctrl.scala 226:82] + node _T_585 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 226:98] + node _T_586 = bits(fifo_valid, 3, 3) @[dma_ctrl.scala 226:118] + node _T_587 = mux(_T_585, UInt<1>("h01"), _T_586) @[dma_ctrl.scala 226:86] + node _T_588 = bits(fifo_reset, 3, 3) @[dma_ctrl.scala 226:136] + node _T_589 = eq(_T_588, UInt<1>("h00")) @[dma_ctrl.scala 226:125] + node _T_590 = and(_T_587, _T_589) @[dma_ctrl.scala 226:123] + reg _T_591 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 226:82] + _T_591 <= _T_590 @[dma_ctrl.scala 226:82] + node _T_592 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 226:98] + node _T_593 = bits(fifo_valid, 4, 4) @[dma_ctrl.scala 226:118] + node _T_594 = mux(_T_592, UInt<1>("h01"), _T_593) @[dma_ctrl.scala 226:86] + node _T_595 = bits(fifo_reset, 4, 4) @[dma_ctrl.scala 226:136] + node _T_596 = eq(_T_595, UInt<1>("h00")) @[dma_ctrl.scala 226:125] + node _T_597 = and(_T_594, _T_596) @[dma_ctrl.scala 226:123] + reg _T_598 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 226:82] + _T_598 <= _T_597 @[dma_ctrl.scala 226:82] node _T_599 = cat(_T_598, _T_591) @[Cat.scala 29:58] node _T_600 = cat(_T_599, _T_584) @[Cat.scala 29:58] node _T_601 = cat(_T_600, _T_577) @[Cat.scala 29:58] node _T_602 = cat(_T_601, _T_570) @[Cat.scala 29:58] - fifo_valid <= _T_602 @[dma_ctrl.scala 232:14] - node _T_603 = bits(fifo_error_en, 0, 0) @[dma_ctrl.scala 234:103] - node _T_604 = bits(_T_603, 0, 0) @[dma_ctrl.scala 234:113] - node _T_605 = mux(_T_604, fifo_error_in[0], fifo_error[0]) @[dma_ctrl.scala 234:89] - node _T_606 = bits(fifo_reset, 0, 0) @[dma_ctrl.scala 234:196] - node _T_607 = eq(_T_606, UInt<1>("h00")) @[dma_ctrl.scala 234:185] + fifo_valid <= _T_602 @[dma_ctrl.scala 226:14] + node _T_603 = bits(fifo_error_en, 0, 0) @[dma_ctrl.scala 228:103] + node _T_604 = bits(_T_603, 0, 0) @[dma_ctrl.scala 228:113] + node _T_605 = mux(_T_604, fifo_error_in[0], fifo_error[0]) @[dma_ctrl.scala 228:89] + node _T_606 = bits(fifo_reset, 0, 0) @[dma_ctrl.scala 228:196] + node _T_607 = eq(_T_606, UInt<1>("h00")) @[dma_ctrl.scala 228:185] node _T_608 = bits(_T_607, 0, 0) @[Bitwise.scala 72:15] node _T_609 = mux(_T_608, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_610 = and(_T_605, _T_609) @[dma_ctrl.scala 234:150] - reg _T_611 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 234:85] - _T_611 <= _T_610 @[dma_ctrl.scala 234:85] - fifo_error[0] <= _T_611 @[dma_ctrl.scala 234:50] - node _T_612 = bits(fifo_error_en, 1, 1) @[dma_ctrl.scala 234:103] - node _T_613 = bits(_T_612, 0, 0) @[dma_ctrl.scala 234:113] - node _T_614 = mux(_T_613, fifo_error_in[1], fifo_error[1]) @[dma_ctrl.scala 234:89] - node _T_615 = bits(fifo_reset, 1, 1) @[dma_ctrl.scala 234:196] - node _T_616 = eq(_T_615, UInt<1>("h00")) @[dma_ctrl.scala 234:185] + node _T_610 = and(_T_605, _T_609) @[dma_ctrl.scala 228:150] + reg _T_611 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 228:85] + _T_611 <= _T_610 @[dma_ctrl.scala 228:85] + fifo_error[0] <= _T_611 @[dma_ctrl.scala 228:50] + node _T_612 = bits(fifo_error_en, 1, 1) @[dma_ctrl.scala 228:103] + node _T_613 = bits(_T_612, 0, 0) @[dma_ctrl.scala 228:113] + node _T_614 = mux(_T_613, fifo_error_in[1], fifo_error[1]) @[dma_ctrl.scala 228:89] + node _T_615 = bits(fifo_reset, 1, 1) @[dma_ctrl.scala 228:196] + node _T_616 = eq(_T_615, UInt<1>("h00")) @[dma_ctrl.scala 228:185] node _T_617 = bits(_T_616, 0, 0) @[Bitwise.scala 72:15] node _T_618 = mux(_T_617, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_619 = and(_T_614, _T_618) @[dma_ctrl.scala 234:150] - reg _T_620 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 234:85] - _T_620 <= _T_619 @[dma_ctrl.scala 234:85] - fifo_error[1] <= _T_620 @[dma_ctrl.scala 234:50] - node _T_621 = bits(fifo_error_en, 2, 2) @[dma_ctrl.scala 234:103] - node _T_622 = bits(_T_621, 0, 0) @[dma_ctrl.scala 234:113] - node _T_623 = mux(_T_622, fifo_error_in[2], fifo_error[2]) @[dma_ctrl.scala 234:89] - node _T_624 = bits(fifo_reset, 2, 2) @[dma_ctrl.scala 234:196] - node _T_625 = eq(_T_624, UInt<1>("h00")) @[dma_ctrl.scala 234:185] + node _T_619 = and(_T_614, _T_618) @[dma_ctrl.scala 228:150] + reg _T_620 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 228:85] + _T_620 <= _T_619 @[dma_ctrl.scala 228:85] + fifo_error[1] <= _T_620 @[dma_ctrl.scala 228:50] + node _T_621 = bits(fifo_error_en, 2, 2) @[dma_ctrl.scala 228:103] + node _T_622 = bits(_T_621, 0, 0) @[dma_ctrl.scala 228:113] + node _T_623 = mux(_T_622, fifo_error_in[2], fifo_error[2]) @[dma_ctrl.scala 228:89] + node _T_624 = bits(fifo_reset, 2, 2) @[dma_ctrl.scala 228:196] + node _T_625 = eq(_T_624, UInt<1>("h00")) @[dma_ctrl.scala 228:185] node _T_626 = bits(_T_625, 0, 0) @[Bitwise.scala 72:15] node _T_627 = mux(_T_626, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_628 = and(_T_623, _T_627) @[dma_ctrl.scala 234:150] - reg _T_629 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 234:85] - _T_629 <= _T_628 @[dma_ctrl.scala 234:85] - fifo_error[2] <= _T_629 @[dma_ctrl.scala 234:50] - node _T_630 = bits(fifo_error_en, 3, 3) @[dma_ctrl.scala 234:103] - node _T_631 = bits(_T_630, 0, 0) @[dma_ctrl.scala 234:113] - node _T_632 = mux(_T_631, fifo_error_in[3], fifo_error[3]) @[dma_ctrl.scala 234:89] - node _T_633 = bits(fifo_reset, 3, 3) @[dma_ctrl.scala 234:196] - node _T_634 = eq(_T_633, UInt<1>("h00")) @[dma_ctrl.scala 234:185] + node _T_628 = and(_T_623, _T_627) @[dma_ctrl.scala 228:150] + reg _T_629 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 228:85] + _T_629 <= _T_628 @[dma_ctrl.scala 228:85] + fifo_error[2] <= _T_629 @[dma_ctrl.scala 228:50] + node _T_630 = bits(fifo_error_en, 3, 3) @[dma_ctrl.scala 228:103] + node _T_631 = bits(_T_630, 0, 0) @[dma_ctrl.scala 228:113] + node _T_632 = mux(_T_631, fifo_error_in[3], fifo_error[3]) @[dma_ctrl.scala 228:89] + node _T_633 = bits(fifo_reset, 3, 3) @[dma_ctrl.scala 228:196] + node _T_634 = eq(_T_633, UInt<1>("h00")) @[dma_ctrl.scala 228:185] node _T_635 = bits(_T_634, 0, 0) @[Bitwise.scala 72:15] node _T_636 = mux(_T_635, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_637 = and(_T_632, _T_636) @[dma_ctrl.scala 234:150] - reg _T_638 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 234:85] - _T_638 <= _T_637 @[dma_ctrl.scala 234:85] - fifo_error[3] <= _T_638 @[dma_ctrl.scala 234:50] - node _T_639 = bits(fifo_error_en, 4, 4) @[dma_ctrl.scala 234:103] - node _T_640 = bits(_T_639, 0, 0) @[dma_ctrl.scala 234:113] - node _T_641 = mux(_T_640, fifo_error_in[4], fifo_error[4]) @[dma_ctrl.scala 234:89] - node _T_642 = bits(fifo_reset, 4, 4) @[dma_ctrl.scala 234:196] - node _T_643 = eq(_T_642, UInt<1>("h00")) @[dma_ctrl.scala 234:185] + node _T_637 = and(_T_632, _T_636) @[dma_ctrl.scala 228:150] + reg _T_638 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 228:85] + _T_638 <= _T_637 @[dma_ctrl.scala 228:85] + fifo_error[3] <= _T_638 @[dma_ctrl.scala 228:50] + node _T_639 = bits(fifo_error_en, 4, 4) @[dma_ctrl.scala 228:103] + node _T_640 = bits(_T_639, 0, 0) @[dma_ctrl.scala 228:113] + node _T_641 = mux(_T_640, fifo_error_in[4], fifo_error[4]) @[dma_ctrl.scala 228:89] + node _T_642 = bits(fifo_reset, 4, 4) @[dma_ctrl.scala 228:196] + node _T_643 = eq(_T_642, UInt<1>("h00")) @[dma_ctrl.scala 228:185] node _T_644 = bits(_T_643, 0, 0) @[Bitwise.scala 72:15] node _T_645 = mux(_T_644, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_646 = and(_T_641, _T_645) @[dma_ctrl.scala 234:150] - reg _T_647 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 234:85] - _T_647 <= _T_646 @[dma_ctrl.scala 234:85] - fifo_error[4] <= _T_647 @[dma_ctrl.scala 234:50] - node _T_648 = bits(fifo_error_bus_en, 0, 0) @[dma_ctrl.scala 236:111] - node _T_649 = bits(fifo_error_bus, 0, 0) @[dma_ctrl.scala 236:135] - node _T_650 = mux(_T_648, UInt<1>("h01"), _T_649) @[dma_ctrl.scala 236:93] - node _T_651 = bits(fifo_reset, 0, 0) @[dma_ctrl.scala 236:153] - node _T_652 = eq(_T_651, UInt<1>("h00")) @[dma_ctrl.scala 236:142] - node _T_653 = and(_T_650, _T_652) @[dma_ctrl.scala 236:140] - reg _T_654 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 236:89] - _T_654 <= _T_653 @[dma_ctrl.scala 236:89] - node _T_655 = bits(fifo_error_bus_en, 1, 1) @[dma_ctrl.scala 236:111] - node _T_656 = bits(fifo_error_bus, 1, 1) @[dma_ctrl.scala 236:135] - node _T_657 = mux(_T_655, UInt<1>("h01"), _T_656) @[dma_ctrl.scala 236:93] - node _T_658 = bits(fifo_reset, 1, 1) @[dma_ctrl.scala 236:153] - node _T_659 = eq(_T_658, UInt<1>("h00")) @[dma_ctrl.scala 236:142] - node _T_660 = and(_T_657, _T_659) @[dma_ctrl.scala 236:140] - reg _T_661 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 236:89] - _T_661 <= _T_660 @[dma_ctrl.scala 236:89] - node _T_662 = bits(fifo_error_bus_en, 2, 2) @[dma_ctrl.scala 236:111] - node _T_663 = bits(fifo_error_bus, 2, 2) @[dma_ctrl.scala 236:135] - node _T_664 = mux(_T_662, UInt<1>("h01"), _T_663) @[dma_ctrl.scala 236:93] - node _T_665 = bits(fifo_reset, 2, 2) @[dma_ctrl.scala 236:153] - node _T_666 = eq(_T_665, UInt<1>("h00")) @[dma_ctrl.scala 236:142] - node _T_667 = and(_T_664, _T_666) @[dma_ctrl.scala 236:140] - reg _T_668 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 236:89] - _T_668 <= _T_667 @[dma_ctrl.scala 236:89] - node _T_669 = bits(fifo_error_bus_en, 3, 3) @[dma_ctrl.scala 236:111] - node _T_670 = bits(fifo_error_bus, 3, 3) @[dma_ctrl.scala 236:135] - node _T_671 = mux(_T_669, UInt<1>("h01"), _T_670) @[dma_ctrl.scala 236:93] - node _T_672 = bits(fifo_reset, 3, 3) @[dma_ctrl.scala 236:153] - node _T_673 = eq(_T_672, UInt<1>("h00")) @[dma_ctrl.scala 236:142] - node _T_674 = and(_T_671, _T_673) @[dma_ctrl.scala 236:140] - reg _T_675 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 236:89] - _T_675 <= _T_674 @[dma_ctrl.scala 236:89] - node _T_676 = bits(fifo_error_bus_en, 4, 4) @[dma_ctrl.scala 236:111] - node _T_677 = bits(fifo_error_bus, 4, 4) @[dma_ctrl.scala 236:135] - node _T_678 = mux(_T_676, UInt<1>("h01"), _T_677) @[dma_ctrl.scala 236:93] - node _T_679 = bits(fifo_reset, 4, 4) @[dma_ctrl.scala 236:153] - node _T_680 = eq(_T_679, UInt<1>("h00")) @[dma_ctrl.scala 236:142] - node _T_681 = and(_T_678, _T_680) @[dma_ctrl.scala 236:140] - reg _T_682 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 236:89] - _T_682 <= _T_681 @[dma_ctrl.scala 236:89] + node _T_646 = and(_T_641, _T_645) @[dma_ctrl.scala 228:150] + reg _T_647 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 228:85] + _T_647 <= _T_646 @[dma_ctrl.scala 228:85] + fifo_error[4] <= _T_647 @[dma_ctrl.scala 228:50] + node _T_648 = bits(fifo_error_bus_en, 0, 0) @[dma_ctrl.scala 230:111] + node _T_649 = bits(fifo_error_bus, 0, 0) @[dma_ctrl.scala 230:135] + node _T_650 = mux(_T_648, UInt<1>("h01"), _T_649) @[dma_ctrl.scala 230:93] + node _T_651 = bits(fifo_reset, 0, 0) @[dma_ctrl.scala 230:153] + node _T_652 = eq(_T_651, UInt<1>("h00")) @[dma_ctrl.scala 230:142] + node _T_653 = and(_T_650, _T_652) @[dma_ctrl.scala 230:140] + reg _T_654 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 230:89] + _T_654 <= _T_653 @[dma_ctrl.scala 230:89] + node _T_655 = bits(fifo_error_bus_en, 1, 1) @[dma_ctrl.scala 230:111] + node _T_656 = bits(fifo_error_bus, 1, 1) @[dma_ctrl.scala 230:135] + node _T_657 = mux(_T_655, UInt<1>("h01"), _T_656) @[dma_ctrl.scala 230:93] + node _T_658 = bits(fifo_reset, 1, 1) @[dma_ctrl.scala 230:153] + node _T_659 = eq(_T_658, UInt<1>("h00")) @[dma_ctrl.scala 230:142] + node _T_660 = and(_T_657, _T_659) @[dma_ctrl.scala 230:140] + reg _T_661 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 230:89] + _T_661 <= _T_660 @[dma_ctrl.scala 230:89] + node _T_662 = bits(fifo_error_bus_en, 2, 2) @[dma_ctrl.scala 230:111] + node _T_663 = bits(fifo_error_bus, 2, 2) @[dma_ctrl.scala 230:135] + node _T_664 = mux(_T_662, UInt<1>("h01"), _T_663) @[dma_ctrl.scala 230:93] + node _T_665 = bits(fifo_reset, 2, 2) @[dma_ctrl.scala 230:153] + node _T_666 = eq(_T_665, UInt<1>("h00")) @[dma_ctrl.scala 230:142] + node _T_667 = and(_T_664, _T_666) @[dma_ctrl.scala 230:140] + reg _T_668 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 230:89] + _T_668 <= _T_667 @[dma_ctrl.scala 230:89] + node _T_669 = bits(fifo_error_bus_en, 3, 3) @[dma_ctrl.scala 230:111] + node _T_670 = bits(fifo_error_bus, 3, 3) @[dma_ctrl.scala 230:135] + node _T_671 = mux(_T_669, UInt<1>("h01"), _T_670) @[dma_ctrl.scala 230:93] + node _T_672 = bits(fifo_reset, 3, 3) @[dma_ctrl.scala 230:153] + node _T_673 = eq(_T_672, UInt<1>("h00")) @[dma_ctrl.scala 230:142] + node _T_674 = and(_T_671, _T_673) @[dma_ctrl.scala 230:140] + reg _T_675 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 230:89] + _T_675 <= _T_674 @[dma_ctrl.scala 230:89] + node _T_676 = bits(fifo_error_bus_en, 4, 4) @[dma_ctrl.scala 230:111] + node _T_677 = bits(fifo_error_bus, 4, 4) @[dma_ctrl.scala 230:135] + node _T_678 = mux(_T_676, UInt<1>("h01"), _T_677) @[dma_ctrl.scala 230:93] + node _T_679 = bits(fifo_reset, 4, 4) @[dma_ctrl.scala 230:153] + node _T_680 = eq(_T_679, UInt<1>("h00")) @[dma_ctrl.scala 230:142] + node _T_681 = and(_T_678, _T_680) @[dma_ctrl.scala 230:140] + reg _T_682 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 230:89] + _T_682 <= _T_681 @[dma_ctrl.scala 230:89] node _T_683 = cat(_T_682, _T_675) @[Cat.scala 29:58] node _T_684 = cat(_T_683, _T_668) @[Cat.scala 29:58] node _T_685 = cat(_T_684, _T_661) @[Cat.scala 29:58] node _T_686 = cat(_T_685, _T_654) @[Cat.scala 29:58] - fifo_error_bus <= _T_686 @[dma_ctrl.scala 236:21] - node _T_687 = bits(fifo_pend_en, 0, 0) @[dma_ctrl.scala 238:106] - node _T_688 = bits(fifo_rpend, 0, 0) @[dma_ctrl.scala 238:126] - node _T_689 = mux(_T_687, UInt<1>("h01"), _T_688) @[dma_ctrl.scala 238:93] - node _T_690 = bits(fifo_reset, 0, 0) @[dma_ctrl.scala 238:144] - node _T_691 = eq(_T_690, UInt<1>("h00")) @[dma_ctrl.scala 238:133] - node _T_692 = and(_T_689, _T_691) @[dma_ctrl.scala 238:131] - reg _T_693 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 238:89] - _T_693 <= _T_692 @[dma_ctrl.scala 238:89] - node _T_694 = bits(fifo_pend_en, 1, 1) @[dma_ctrl.scala 238:106] - node _T_695 = bits(fifo_rpend, 1, 1) @[dma_ctrl.scala 238:126] - node _T_696 = mux(_T_694, UInt<1>("h01"), _T_695) @[dma_ctrl.scala 238:93] - node _T_697 = bits(fifo_reset, 1, 1) @[dma_ctrl.scala 238:144] - node _T_698 = eq(_T_697, UInt<1>("h00")) @[dma_ctrl.scala 238:133] - node _T_699 = and(_T_696, _T_698) @[dma_ctrl.scala 238:131] - reg _T_700 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 238:89] - _T_700 <= _T_699 @[dma_ctrl.scala 238:89] - node _T_701 = bits(fifo_pend_en, 2, 2) @[dma_ctrl.scala 238:106] - node _T_702 = bits(fifo_rpend, 2, 2) @[dma_ctrl.scala 238:126] - node _T_703 = mux(_T_701, UInt<1>("h01"), _T_702) @[dma_ctrl.scala 238:93] - node _T_704 = bits(fifo_reset, 2, 2) @[dma_ctrl.scala 238:144] - node _T_705 = eq(_T_704, UInt<1>("h00")) @[dma_ctrl.scala 238:133] - node _T_706 = and(_T_703, _T_705) @[dma_ctrl.scala 238:131] - reg _T_707 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 238:89] - _T_707 <= _T_706 @[dma_ctrl.scala 238:89] - node _T_708 = bits(fifo_pend_en, 3, 3) @[dma_ctrl.scala 238:106] - node _T_709 = bits(fifo_rpend, 3, 3) @[dma_ctrl.scala 238:126] - node _T_710 = mux(_T_708, UInt<1>("h01"), _T_709) @[dma_ctrl.scala 238:93] - node _T_711 = bits(fifo_reset, 3, 3) @[dma_ctrl.scala 238:144] - node _T_712 = eq(_T_711, UInt<1>("h00")) @[dma_ctrl.scala 238:133] - node _T_713 = and(_T_710, _T_712) @[dma_ctrl.scala 238:131] - reg _T_714 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 238:89] - _T_714 <= _T_713 @[dma_ctrl.scala 238:89] - node _T_715 = bits(fifo_pend_en, 4, 4) @[dma_ctrl.scala 238:106] - node _T_716 = bits(fifo_rpend, 4, 4) @[dma_ctrl.scala 238:126] - node _T_717 = mux(_T_715, UInt<1>("h01"), _T_716) @[dma_ctrl.scala 238:93] - node _T_718 = bits(fifo_reset, 4, 4) @[dma_ctrl.scala 238:144] - node _T_719 = eq(_T_718, UInt<1>("h00")) @[dma_ctrl.scala 238:133] - node _T_720 = and(_T_717, _T_719) @[dma_ctrl.scala 238:131] - reg _T_721 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 238:89] - _T_721 <= _T_720 @[dma_ctrl.scala 238:89] + fifo_error_bus <= _T_686 @[dma_ctrl.scala 230:21] + node _T_687 = bits(fifo_pend_en, 0, 0) @[dma_ctrl.scala 232:106] + node _T_688 = bits(fifo_rpend, 0, 0) @[dma_ctrl.scala 232:126] + node _T_689 = mux(_T_687, UInt<1>("h01"), _T_688) @[dma_ctrl.scala 232:93] + node _T_690 = bits(fifo_reset, 0, 0) @[dma_ctrl.scala 232:144] + node _T_691 = eq(_T_690, UInt<1>("h00")) @[dma_ctrl.scala 232:133] + node _T_692 = and(_T_689, _T_691) @[dma_ctrl.scala 232:131] + reg _T_693 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 232:89] + _T_693 <= _T_692 @[dma_ctrl.scala 232:89] + node _T_694 = bits(fifo_pend_en, 1, 1) @[dma_ctrl.scala 232:106] + node _T_695 = bits(fifo_rpend, 1, 1) @[dma_ctrl.scala 232:126] + node _T_696 = mux(_T_694, UInt<1>("h01"), _T_695) @[dma_ctrl.scala 232:93] + node _T_697 = bits(fifo_reset, 1, 1) @[dma_ctrl.scala 232:144] + node _T_698 = eq(_T_697, UInt<1>("h00")) @[dma_ctrl.scala 232:133] + node _T_699 = and(_T_696, _T_698) @[dma_ctrl.scala 232:131] + reg _T_700 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 232:89] + _T_700 <= _T_699 @[dma_ctrl.scala 232:89] + node _T_701 = bits(fifo_pend_en, 2, 2) @[dma_ctrl.scala 232:106] + node _T_702 = bits(fifo_rpend, 2, 2) @[dma_ctrl.scala 232:126] + node _T_703 = mux(_T_701, UInt<1>("h01"), _T_702) @[dma_ctrl.scala 232:93] + node _T_704 = bits(fifo_reset, 2, 2) @[dma_ctrl.scala 232:144] + node _T_705 = eq(_T_704, UInt<1>("h00")) @[dma_ctrl.scala 232:133] + node _T_706 = and(_T_703, _T_705) @[dma_ctrl.scala 232:131] + reg _T_707 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 232:89] + _T_707 <= _T_706 @[dma_ctrl.scala 232:89] + node _T_708 = bits(fifo_pend_en, 3, 3) @[dma_ctrl.scala 232:106] + node _T_709 = bits(fifo_rpend, 3, 3) @[dma_ctrl.scala 232:126] + node _T_710 = mux(_T_708, UInt<1>("h01"), _T_709) @[dma_ctrl.scala 232:93] + node _T_711 = bits(fifo_reset, 3, 3) @[dma_ctrl.scala 232:144] + node _T_712 = eq(_T_711, UInt<1>("h00")) @[dma_ctrl.scala 232:133] + node _T_713 = and(_T_710, _T_712) @[dma_ctrl.scala 232:131] + reg _T_714 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 232:89] + _T_714 <= _T_713 @[dma_ctrl.scala 232:89] + node _T_715 = bits(fifo_pend_en, 4, 4) @[dma_ctrl.scala 232:106] + node _T_716 = bits(fifo_rpend, 4, 4) @[dma_ctrl.scala 232:126] + node _T_717 = mux(_T_715, UInt<1>("h01"), _T_716) @[dma_ctrl.scala 232:93] + node _T_718 = bits(fifo_reset, 4, 4) @[dma_ctrl.scala 232:144] + node _T_719 = eq(_T_718, UInt<1>("h00")) @[dma_ctrl.scala 232:133] + node _T_720 = and(_T_717, _T_719) @[dma_ctrl.scala 232:131] + reg _T_721 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 232:89] + _T_721 <= _T_720 @[dma_ctrl.scala 232:89] node _T_722 = cat(_T_721, _T_714) @[Cat.scala 29:58] node _T_723 = cat(_T_722, _T_707) @[Cat.scala 29:58] node _T_724 = cat(_T_723, _T_700) @[Cat.scala 29:58] node _T_725 = cat(_T_724, _T_693) @[Cat.scala 29:58] - fifo_rpend <= _T_725 @[dma_ctrl.scala 238:21] - node _T_726 = bits(fifo_done_en, 0, 0) @[dma_ctrl.scala 240:106] - node _T_727 = bits(fifo_done, 0, 0) @[dma_ctrl.scala 240:125] - node _T_728 = mux(_T_726, UInt<1>("h01"), _T_727) @[dma_ctrl.scala 240:93] - node _T_729 = bits(fifo_reset, 0, 0) @[dma_ctrl.scala 240:143] - node _T_730 = eq(_T_729, UInt<1>("h00")) @[dma_ctrl.scala 240:132] - node _T_731 = and(_T_728, _T_730) @[dma_ctrl.scala 240:130] - reg _T_732 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 240:89] - _T_732 <= _T_731 @[dma_ctrl.scala 240:89] - node _T_733 = bits(fifo_done_en, 1, 1) @[dma_ctrl.scala 240:106] - node _T_734 = bits(fifo_done, 1, 1) @[dma_ctrl.scala 240:125] - node _T_735 = mux(_T_733, UInt<1>("h01"), _T_734) @[dma_ctrl.scala 240:93] - node _T_736 = bits(fifo_reset, 1, 1) @[dma_ctrl.scala 240:143] - node _T_737 = eq(_T_736, UInt<1>("h00")) @[dma_ctrl.scala 240:132] - node _T_738 = and(_T_735, _T_737) @[dma_ctrl.scala 240:130] - reg _T_739 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 240:89] - _T_739 <= _T_738 @[dma_ctrl.scala 240:89] - node _T_740 = bits(fifo_done_en, 2, 2) @[dma_ctrl.scala 240:106] - node _T_741 = bits(fifo_done, 2, 2) @[dma_ctrl.scala 240:125] - node _T_742 = mux(_T_740, UInt<1>("h01"), _T_741) @[dma_ctrl.scala 240:93] - node _T_743 = bits(fifo_reset, 2, 2) @[dma_ctrl.scala 240:143] - node _T_744 = eq(_T_743, UInt<1>("h00")) @[dma_ctrl.scala 240:132] - node _T_745 = and(_T_742, _T_744) @[dma_ctrl.scala 240:130] - reg _T_746 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 240:89] - _T_746 <= _T_745 @[dma_ctrl.scala 240:89] - node _T_747 = bits(fifo_done_en, 3, 3) @[dma_ctrl.scala 240:106] - node _T_748 = bits(fifo_done, 3, 3) @[dma_ctrl.scala 240:125] - node _T_749 = mux(_T_747, UInt<1>("h01"), _T_748) @[dma_ctrl.scala 240:93] - node _T_750 = bits(fifo_reset, 3, 3) @[dma_ctrl.scala 240:143] - node _T_751 = eq(_T_750, UInt<1>("h00")) @[dma_ctrl.scala 240:132] - node _T_752 = and(_T_749, _T_751) @[dma_ctrl.scala 240:130] - reg _T_753 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 240:89] - _T_753 <= _T_752 @[dma_ctrl.scala 240:89] - node _T_754 = bits(fifo_done_en, 4, 4) @[dma_ctrl.scala 240:106] - node _T_755 = bits(fifo_done, 4, 4) @[dma_ctrl.scala 240:125] - node _T_756 = mux(_T_754, UInt<1>("h01"), _T_755) @[dma_ctrl.scala 240:93] - node _T_757 = bits(fifo_reset, 4, 4) @[dma_ctrl.scala 240:143] - node _T_758 = eq(_T_757, UInt<1>("h00")) @[dma_ctrl.scala 240:132] - node _T_759 = and(_T_756, _T_758) @[dma_ctrl.scala 240:130] - reg _T_760 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 240:89] - _T_760 <= _T_759 @[dma_ctrl.scala 240:89] + fifo_rpend <= _T_725 @[dma_ctrl.scala 232:21] + node _T_726 = bits(fifo_done_en, 0, 0) @[dma_ctrl.scala 234:106] + node _T_727 = bits(fifo_done, 0, 0) @[dma_ctrl.scala 234:125] + node _T_728 = mux(_T_726, UInt<1>("h01"), _T_727) @[dma_ctrl.scala 234:93] + node _T_729 = bits(fifo_reset, 0, 0) @[dma_ctrl.scala 234:143] + node _T_730 = eq(_T_729, UInt<1>("h00")) @[dma_ctrl.scala 234:132] + node _T_731 = and(_T_728, _T_730) @[dma_ctrl.scala 234:130] + reg _T_732 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 234:89] + _T_732 <= _T_731 @[dma_ctrl.scala 234:89] + node _T_733 = bits(fifo_done_en, 1, 1) @[dma_ctrl.scala 234:106] + node _T_734 = bits(fifo_done, 1, 1) @[dma_ctrl.scala 234:125] + node _T_735 = mux(_T_733, UInt<1>("h01"), _T_734) @[dma_ctrl.scala 234:93] + node _T_736 = bits(fifo_reset, 1, 1) @[dma_ctrl.scala 234:143] + node _T_737 = eq(_T_736, UInt<1>("h00")) @[dma_ctrl.scala 234:132] + node _T_738 = and(_T_735, _T_737) @[dma_ctrl.scala 234:130] + reg _T_739 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 234:89] + _T_739 <= _T_738 @[dma_ctrl.scala 234:89] + node _T_740 = bits(fifo_done_en, 2, 2) @[dma_ctrl.scala 234:106] + node _T_741 = bits(fifo_done, 2, 2) @[dma_ctrl.scala 234:125] + node _T_742 = mux(_T_740, UInt<1>("h01"), _T_741) @[dma_ctrl.scala 234:93] + node _T_743 = bits(fifo_reset, 2, 2) @[dma_ctrl.scala 234:143] + node _T_744 = eq(_T_743, UInt<1>("h00")) @[dma_ctrl.scala 234:132] + node _T_745 = and(_T_742, _T_744) @[dma_ctrl.scala 234:130] + reg _T_746 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 234:89] + _T_746 <= _T_745 @[dma_ctrl.scala 234:89] + node _T_747 = bits(fifo_done_en, 3, 3) @[dma_ctrl.scala 234:106] + node _T_748 = bits(fifo_done, 3, 3) @[dma_ctrl.scala 234:125] + node _T_749 = mux(_T_747, UInt<1>("h01"), _T_748) @[dma_ctrl.scala 234:93] + node _T_750 = bits(fifo_reset, 3, 3) @[dma_ctrl.scala 234:143] + node _T_751 = eq(_T_750, UInt<1>("h00")) @[dma_ctrl.scala 234:132] + node _T_752 = and(_T_749, _T_751) @[dma_ctrl.scala 234:130] + reg _T_753 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 234:89] + _T_753 <= _T_752 @[dma_ctrl.scala 234:89] + node _T_754 = bits(fifo_done_en, 4, 4) @[dma_ctrl.scala 234:106] + node _T_755 = bits(fifo_done, 4, 4) @[dma_ctrl.scala 234:125] + node _T_756 = mux(_T_754, UInt<1>("h01"), _T_755) @[dma_ctrl.scala 234:93] + node _T_757 = bits(fifo_reset, 4, 4) @[dma_ctrl.scala 234:143] + node _T_758 = eq(_T_757, UInt<1>("h00")) @[dma_ctrl.scala 234:132] + node _T_759 = and(_T_756, _T_758) @[dma_ctrl.scala 234:130] + reg _T_760 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 234:89] + _T_760 <= _T_759 @[dma_ctrl.scala 234:89] node _T_761 = cat(_T_760, _T_753) @[Cat.scala 29:58] node _T_762 = cat(_T_761, _T_746) @[Cat.scala 29:58] node _T_763 = cat(_T_762, _T_739) @[Cat.scala 29:58] node _T_764 = cat(_T_763, _T_732) @[Cat.scala 29:58] - fifo_done <= _T_764 @[dma_ctrl.scala 240:21] - node _T_765 = bits(fifo_done_bus_en, 0, 0) @[dma_ctrl.scala 242:110] - node _T_766 = bits(fifo_done_bus, 0, 0) @[dma_ctrl.scala 242:133] - node _T_767 = mux(_T_765, UInt<1>("h01"), _T_766) @[dma_ctrl.scala 242:93] - node _T_768 = bits(fifo_reset, 0, 0) @[dma_ctrl.scala 242:151] - node _T_769 = eq(_T_768, UInt<1>("h00")) @[dma_ctrl.scala 242:140] - node _T_770 = and(_T_767, _T_769) @[dma_ctrl.scala 242:138] - reg _T_771 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 242:89] - _T_771 <= _T_770 @[dma_ctrl.scala 242:89] - node _T_772 = bits(fifo_done_bus_en, 1, 1) @[dma_ctrl.scala 242:110] - node _T_773 = bits(fifo_done_bus, 1, 1) @[dma_ctrl.scala 242:133] - node _T_774 = mux(_T_772, UInt<1>("h01"), _T_773) @[dma_ctrl.scala 242:93] - node _T_775 = bits(fifo_reset, 1, 1) @[dma_ctrl.scala 242:151] - node _T_776 = eq(_T_775, UInt<1>("h00")) @[dma_ctrl.scala 242:140] - node _T_777 = and(_T_774, _T_776) @[dma_ctrl.scala 242:138] - reg _T_778 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 242:89] - _T_778 <= _T_777 @[dma_ctrl.scala 242:89] - node _T_779 = bits(fifo_done_bus_en, 2, 2) @[dma_ctrl.scala 242:110] - node _T_780 = bits(fifo_done_bus, 2, 2) @[dma_ctrl.scala 242:133] - node _T_781 = mux(_T_779, UInt<1>("h01"), _T_780) @[dma_ctrl.scala 242:93] - node _T_782 = bits(fifo_reset, 2, 2) @[dma_ctrl.scala 242:151] - node _T_783 = eq(_T_782, UInt<1>("h00")) @[dma_ctrl.scala 242:140] - node _T_784 = and(_T_781, _T_783) @[dma_ctrl.scala 242:138] - reg _T_785 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 242:89] - _T_785 <= _T_784 @[dma_ctrl.scala 242:89] - node _T_786 = bits(fifo_done_bus_en, 3, 3) @[dma_ctrl.scala 242:110] - node _T_787 = bits(fifo_done_bus, 3, 3) @[dma_ctrl.scala 242:133] - node _T_788 = mux(_T_786, UInt<1>("h01"), _T_787) @[dma_ctrl.scala 242:93] - node _T_789 = bits(fifo_reset, 3, 3) @[dma_ctrl.scala 242:151] - node _T_790 = eq(_T_789, UInt<1>("h00")) @[dma_ctrl.scala 242:140] - node _T_791 = and(_T_788, _T_790) @[dma_ctrl.scala 242:138] - reg _T_792 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 242:89] - _T_792 <= _T_791 @[dma_ctrl.scala 242:89] - node _T_793 = bits(fifo_done_bus_en, 4, 4) @[dma_ctrl.scala 242:110] - node _T_794 = bits(fifo_done_bus, 4, 4) @[dma_ctrl.scala 242:133] - node _T_795 = mux(_T_793, UInt<1>("h01"), _T_794) @[dma_ctrl.scala 242:93] - node _T_796 = bits(fifo_reset, 4, 4) @[dma_ctrl.scala 242:151] - node _T_797 = eq(_T_796, UInt<1>("h00")) @[dma_ctrl.scala 242:140] - node _T_798 = and(_T_795, _T_797) @[dma_ctrl.scala 242:138] - reg _T_799 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 242:89] - _T_799 <= _T_798 @[dma_ctrl.scala 242:89] + fifo_done <= _T_764 @[dma_ctrl.scala 234:21] + node _T_765 = bits(fifo_done_bus_en, 0, 0) @[dma_ctrl.scala 236:110] + node _T_766 = bits(fifo_done_bus, 0, 0) @[dma_ctrl.scala 236:133] + node _T_767 = mux(_T_765, UInt<1>("h01"), _T_766) @[dma_ctrl.scala 236:93] + node _T_768 = bits(fifo_reset, 0, 0) @[dma_ctrl.scala 236:151] + node _T_769 = eq(_T_768, UInt<1>("h00")) @[dma_ctrl.scala 236:140] + node _T_770 = and(_T_767, _T_769) @[dma_ctrl.scala 236:138] + reg _T_771 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 236:89] + _T_771 <= _T_770 @[dma_ctrl.scala 236:89] + node _T_772 = bits(fifo_done_bus_en, 1, 1) @[dma_ctrl.scala 236:110] + node _T_773 = bits(fifo_done_bus, 1, 1) @[dma_ctrl.scala 236:133] + node _T_774 = mux(_T_772, UInt<1>("h01"), _T_773) @[dma_ctrl.scala 236:93] + node _T_775 = bits(fifo_reset, 1, 1) @[dma_ctrl.scala 236:151] + node _T_776 = eq(_T_775, UInt<1>("h00")) @[dma_ctrl.scala 236:140] + node _T_777 = and(_T_774, _T_776) @[dma_ctrl.scala 236:138] + reg _T_778 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 236:89] + _T_778 <= _T_777 @[dma_ctrl.scala 236:89] + node _T_779 = bits(fifo_done_bus_en, 2, 2) @[dma_ctrl.scala 236:110] + node _T_780 = bits(fifo_done_bus, 2, 2) @[dma_ctrl.scala 236:133] + node _T_781 = mux(_T_779, UInt<1>("h01"), _T_780) @[dma_ctrl.scala 236:93] + node _T_782 = bits(fifo_reset, 2, 2) @[dma_ctrl.scala 236:151] + node _T_783 = eq(_T_782, UInt<1>("h00")) @[dma_ctrl.scala 236:140] + node _T_784 = and(_T_781, _T_783) @[dma_ctrl.scala 236:138] + reg _T_785 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 236:89] + _T_785 <= _T_784 @[dma_ctrl.scala 236:89] + node _T_786 = bits(fifo_done_bus_en, 3, 3) @[dma_ctrl.scala 236:110] + node _T_787 = bits(fifo_done_bus, 3, 3) @[dma_ctrl.scala 236:133] + node _T_788 = mux(_T_786, UInt<1>("h01"), _T_787) @[dma_ctrl.scala 236:93] + node _T_789 = bits(fifo_reset, 3, 3) @[dma_ctrl.scala 236:151] + node _T_790 = eq(_T_789, UInt<1>("h00")) @[dma_ctrl.scala 236:140] + node _T_791 = and(_T_788, _T_790) @[dma_ctrl.scala 236:138] + reg _T_792 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 236:89] + _T_792 <= _T_791 @[dma_ctrl.scala 236:89] + node _T_793 = bits(fifo_done_bus_en, 4, 4) @[dma_ctrl.scala 236:110] + node _T_794 = bits(fifo_done_bus, 4, 4) @[dma_ctrl.scala 236:133] + node _T_795 = mux(_T_793, UInt<1>("h01"), _T_794) @[dma_ctrl.scala 236:93] + node _T_796 = bits(fifo_reset, 4, 4) @[dma_ctrl.scala 236:151] + node _T_797 = eq(_T_796, UInt<1>("h00")) @[dma_ctrl.scala 236:140] + node _T_798 = and(_T_795, _T_797) @[dma_ctrl.scala 236:138] + reg _T_799 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 236:89] + _T_799 <= _T_798 @[dma_ctrl.scala 236:89] node _T_800 = cat(_T_799, _T_792) @[Cat.scala 29:58] node _T_801 = cat(_T_800, _T_785) @[Cat.scala 29:58] node _T_802 = cat(_T_801, _T_778) @[Cat.scala 29:58] node _T_803 = cat(_T_802, _T_771) @[Cat.scala 29:58] - fifo_done_bus <= _T_803 @[dma_ctrl.scala 242:21] - node _T_804 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 244:84] + fifo_done_bus <= _T_803 @[dma_ctrl.scala 236:21] + node _T_804 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 238:84] inst rvclkhdr of rvclkhdr_829 @[lib.scala 352:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset @@ -108049,8 +108046,8 @@ circuit quasar_wrapper : rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_805 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_805 <= fifo_addr_in @[lib.scala 358:16] - fifo_addr[0] <= _T_805 @[dma_ctrl.scala 244:49] - node _T_806 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 244:84] + fifo_addr[0] <= _T_805 @[dma_ctrl.scala 238:49] + node _T_806 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 238:84] inst rvclkhdr_1 of rvclkhdr_830 @[lib.scala 352:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset @@ -108059,8 +108056,8 @@ circuit quasar_wrapper : rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_807 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_807 <= fifo_addr_in @[lib.scala 358:16] - fifo_addr[1] <= _T_807 @[dma_ctrl.scala 244:49] - node _T_808 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 244:84] + fifo_addr[1] <= _T_807 @[dma_ctrl.scala 238:49] + node _T_808 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 238:84] inst rvclkhdr_2 of rvclkhdr_831 @[lib.scala 352:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset @@ -108069,8 +108066,8 @@ circuit quasar_wrapper : rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_809 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_809 <= fifo_addr_in @[lib.scala 358:16] - fifo_addr[2] <= _T_809 @[dma_ctrl.scala 244:49] - node _T_810 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 244:84] + fifo_addr[2] <= _T_809 @[dma_ctrl.scala 238:49] + node _T_810 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 238:84] inst rvclkhdr_3 of rvclkhdr_832 @[lib.scala 352:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset @@ -108079,8 +108076,8 @@ circuit quasar_wrapper : rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_811 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_811 <= fifo_addr_in @[lib.scala 358:16] - fifo_addr[3] <= _T_811 @[dma_ctrl.scala 244:49] - node _T_812 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 244:84] + fifo_addr[3] <= _T_811 @[dma_ctrl.scala 238:49] + node _T_812 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 238:84] inst rvclkhdr_4 of rvclkhdr_833 @[lib.scala 352:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset @@ -108089,103 +108086,103 @@ circuit quasar_wrapper : rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_813 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_813 <= fifo_addr_in @[lib.scala 358:16] - fifo_addr[4] <= _T_813 @[dma_ctrl.scala 244:49] - node _T_814 = bits(fifo_sz_in, 2, 0) @[dma_ctrl.scala 246:100] - node _T_815 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 246:123] + fifo_addr[4] <= _T_813 @[dma_ctrl.scala 238:49] + node _T_814 = bits(fifo_sz_in, 2, 0) @[dma_ctrl.scala 240:100] + node _T_815 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 240:123] reg _T_816 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_815 : @[Reg.scala 28:19] _T_816 <= _T_814 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_sz[0] <= _T_816 @[dma_ctrl.scala 246:47] - node _T_817 = bits(fifo_sz_in, 2, 0) @[dma_ctrl.scala 246:100] - node _T_818 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 246:123] + fifo_sz[0] <= _T_816 @[dma_ctrl.scala 240:47] + node _T_817 = bits(fifo_sz_in, 2, 0) @[dma_ctrl.scala 240:100] + node _T_818 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 240:123] reg _T_819 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_818 : @[Reg.scala 28:19] _T_819 <= _T_817 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_sz[1] <= _T_819 @[dma_ctrl.scala 246:47] - node _T_820 = bits(fifo_sz_in, 2, 0) @[dma_ctrl.scala 246:100] - node _T_821 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 246:123] + fifo_sz[1] <= _T_819 @[dma_ctrl.scala 240:47] + node _T_820 = bits(fifo_sz_in, 2, 0) @[dma_ctrl.scala 240:100] + node _T_821 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 240:123] reg _T_822 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_821 : @[Reg.scala 28:19] _T_822 <= _T_820 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_sz[2] <= _T_822 @[dma_ctrl.scala 246:47] - node _T_823 = bits(fifo_sz_in, 2, 0) @[dma_ctrl.scala 246:100] - node _T_824 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 246:123] + fifo_sz[2] <= _T_822 @[dma_ctrl.scala 240:47] + node _T_823 = bits(fifo_sz_in, 2, 0) @[dma_ctrl.scala 240:100] + node _T_824 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 240:123] reg _T_825 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_824 : @[Reg.scala 28:19] _T_825 <= _T_823 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_sz[3] <= _T_825 @[dma_ctrl.scala 246:47] - node _T_826 = bits(fifo_sz_in, 2, 0) @[dma_ctrl.scala 246:100] - node _T_827 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 246:123] + fifo_sz[3] <= _T_825 @[dma_ctrl.scala 240:47] + node _T_826 = bits(fifo_sz_in, 2, 0) @[dma_ctrl.scala 240:100] + node _T_827 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 240:123] reg _T_828 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_827 : @[Reg.scala 28:19] _T_828 <= _T_826 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_sz[4] <= _T_828 @[dma_ctrl.scala 246:47] - node _T_829 = bits(fifo_byteen_in, 7, 0) @[dma_ctrl.scala 248:108] - node _T_830 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 248:131] - node _T_831 = bits(_T_830, 0, 0) @[dma_ctrl.scala 248:141] + fifo_sz[4] <= _T_828 @[dma_ctrl.scala 240:47] + node _T_829 = bits(fifo_byteen_in, 7, 0) @[dma_ctrl.scala 242:108] + node _T_830 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 242:131] + node _T_831 = bits(_T_830, 0, 0) @[dma_ctrl.scala 242:141] reg _T_832 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_831 : @[Reg.scala 28:19] _T_832 <= _T_829 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_byteen[0] <= _T_832 @[dma_ctrl.scala 248:51] - node _T_833 = bits(fifo_byteen_in, 7, 0) @[dma_ctrl.scala 248:108] - node _T_834 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 248:131] - node _T_835 = bits(_T_834, 0, 0) @[dma_ctrl.scala 248:141] + fifo_byteen[0] <= _T_832 @[dma_ctrl.scala 242:51] + node _T_833 = bits(fifo_byteen_in, 7, 0) @[dma_ctrl.scala 242:108] + node _T_834 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 242:131] + node _T_835 = bits(_T_834, 0, 0) @[dma_ctrl.scala 242:141] reg _T_836 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_835 : @[Reg.scala 28:19] _T_836 <= _T_833 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_byteen[1] <= _T_836 @[dma_ctrl.scala 248:51] - node _T_837 = bits(fifo_byteen_in, 7, 0) @[dma_ctrl.scala 248:108] - node _T_838 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 248:131] - node _T_839 = bits(_T_838, 0, 0) @[dma_ctrl.scala 248:141] + fifo_byteen[1] <= _T_836 @[dma_ctrl.scala 242:51] + node _T_837 = bits(fifo_byteen_in, 7, 0) @[dma_ctrl.scala 242:108] + node _T_838 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 242:131] + node _T_839 = bits(_T_838, 0, 0) @[dma_ctrl.scala 242:141] reg _T_840 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_839 : @[Reg.scala 28:19] _T_840 <= _T_837 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_byteen[2] <= _T_840 @[dma_ctrl.scala 248:51] - node _T_841 = bits(fifo_byteen_in, 7, 0) @[dma_ctrl.scala 248:108] - node _T_842 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 248:131] - node _T_843 = bits(_T_842, 0, 0) @[dma_ctrl.scala 248:141] + fifo_byteen[2] <= _T_840 @[dma_ctrl.scala 242:51] + node _T_841 = bits(fifo_byteen_in, 7, 0) @[dma_ctrl.scala 242:108] + node _T_842 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 242:131] + node _T_843 = bits(_T_842, 0, 0) @[dma_ctrl.scala 242:141] reg _T_844 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_843 : @[Reg.scala 28:19] _T_844 <= _T_841 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_byteen[3] <= _T_844 @[dma_ctrl.scala 248:51] - node _T_845 = bits(fifo_byteen_in, 7, 0) @[dma_ctrl.scala 248:108] - node _T_846 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 248:131] - node _T_847 = bits(_T_846, 0, 0) @[dma_ctrl.scala 248:141] + fifo_byteen[3] <= _T_844 @[dma_ctrl.scala 242:51] + node _T_845 = bits(fifo_byteen_in, 7, 0) @[dma_ctrl.scala 242:108] + node _T_846 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 242:131] + node _T_847 = bits(_T_846, 0, 0) @[dma_ctrl.scala 242:141] reg _T_848 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_847 : @[Reg.scala 28:19] _T_848 <= _T_845 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_byteen[4] <= _T_848 @[dma_ctrl.scala 248:51] - node _T_849 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 250:129] + fifo_byteen[4] <= _T_848 @[dma_ctrl.scala 242:51] + node _T_849 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 244:129] reg _T_850 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_849 : @[Reg.scala 28:19] _T_850 <= fifo_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_851 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 250:129] + node _T_851 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 244:129] reg _T_852 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_851 : @[Reg.scala 28:19] _T_852 <= fifo_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_853 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 250:129] + node _T_853 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 244:129] reg _T_854 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_853 : @[Reg.scala 28:19] _T_854 <= fifo_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_855 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 250:129] + node _T_855 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 244:129] reg _T_856 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_855 : @[Reg.scala 28:19] _T_856 <= fifo_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_857 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 250:129] + node _T_857 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 244:129] reg _T_858 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_857 : @[Reg.scala 28:19] _T_858 <= fifo_write_in @[Reg.scala 28:23] @@ -108194,28 +108191,28 @@ circuit quasar_wrapper : node _T_860 = cat(_T_859, _T_854) @[Cat.scala 29:58] node _T_861 = cat(_T_860, _T_852) @[Cat.scala 29:58] node _T_862 = cat(_T_861, _T_850) @[Cat.scala 29:58] - fifo_write <= _T_862 @[dma_ctrl.scala 250:21] - node _T_863 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 252:136] + fifo_write <= _T_862 @[dma_ctrl.scala 244:21] + node _T_863 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 246:136] reg _T_864 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_863 : @[Reg.scala 28:19] _T_864 <= fifo_posted_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_865 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 252:136] + node _T_865 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 246:136] reg _T_866 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_865 : @[Reg.scala 28:19] _T_866 <= fifo_posted_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_867 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 252:136] + node _T_867 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 246:136] reg _T_868 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_867 : @[Reg.scala 28:19] _T_868 <= fifo_posted_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_869 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 252:136] + node _T_869 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 246:136] reg _T_870 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_869 : @[Reg.scala 28:19] _T_870 <= fifo_posted_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_871 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 252:136] + node _T_871 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 246:136] reg _T_872 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_871 : @[Reg.scala 28:19] _T_872 <= fifo_posted_write_in @[Reg.scala 28:23] @@ -108224,28 +108221,28 @@ circuit quasar_wrapper : node _T_874 = cat(_T_873, _T_868) @[Cat.scala 29:58] node _T_875 = cat(_T_874, _T_866) @[Cat.scala 29:58] node _T_876 = cat(_T_875, _T_864) @[Cat.scala 29:58] - fifo_posted_write <= _T_876 @[dma_ctrl.scala 252:21] - node _T_877 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 254:126] + fifo_posted_write <= _T_876 @[dma_ctrl.scala 246:21] + node _T_877 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 248:126] reg _T_878 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_877 : @[Reg.scala 28:19] _T_878 <= io.dbg_dma.dbg_ib.dbg_cmd_valid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_879 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 254:126] + node _T_879 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 248:126] reg _T_880 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_879 : @[Reg.scala 28:19] _T_880 <= io.dbg_dma.dbg_ib.dbg_cmd_valid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_881 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 254:126] + node _T_881 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 248:126] reg _T_882 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_881 : @[Reg.scala 28:19] _T_882 <= io.dbg_dma.dbg_ib.dbg_cmd_valid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_883 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 254:126] + node _T_883 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 248:126] reg _T_884 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_883 : @[Reg.scala 28:19] _T_884 <= io.dbg_dma.dbg_ib.dbg_cmd_valid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_885 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 254:126] + node _T_885 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 248:126] reg _T_886 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_885 : @[Reg.scala 28:19] _T_886 <= io.dbg_dma.dbg_ib.dbg_cmd_valid @[Reg.scala 28:23] @@ -108254,8 +108251,8 @@ circuit quasar_wrapper : node _T_888 = cat(_T_887, _T_882) @[Cat.scala 29:58] node _T_889 = cat(_T_888, _T_880) @[Cat.scala 29:58] node _T_890 = cat(_T_889, _T_878) @[Cat.scala 29:58] - fifo_dbg <= _T_890 @[dma_ctrl.scala 254:21] - node _T_891 = bits(fifo_data_en, 0, 0) @[dma_ctrl.scala 256:88] + fifo_dbg <= _T_890 @[dma_ctrl.scala 248:21] + node _T_891 = bits(fifo_data_en, 0, 0) @[dma_ctrl.scala 250:88] inst rvclkhdr_5 of rvclkhdr_834 @[lib.scala 352:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset @@ -108264,8 +108261,8 @@ circuit quasar_wrapper : rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_892 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_892 <= fifo_data_in[0] @[lib.scala 358:16] - fifo_data[0] <= _T_892 @[dma_ctrl.scala 256:49] - node _T_893 = bits(fifo_data_en, 1, 1) @[dma_ctrl.scala 256:88] + fifo_data[0] <= _T_892 @[dma_ctrl.scala 250:49] + node _T_893 = bits(fifo_data_en, 1, 1) @[dma_ctrl.scala 250:88] inst rvclkhdr_6 of rvclkhdr_835 @[lib.scala 352:23] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset @@ -108274,8 +108271,8 @@ circuit quasar_wrapper : rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_894 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_894 <= fifo_data_in[1] @[lib.scala 358:16] - fifo_data[1] <= _T_894 @[dma_ctrl.scala 256:49] - node _T_895 = bits(fifo_data_en, 2, 2) @[dma_ctrl.scala 256:88] + fifo_data[1] <= _T_894 @[dma_ctrl.scala 250:49] + node _T_895 = bits(fifo_data_en, 2, 2) @[dma_ctrl.scala 250:88] inst rvclkhdr_7 of rvclkhdr_836 @[lib.scala 352:23] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset @@ -108284,8 +108281,8 @@ circuit quasar_wrapper : rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_896 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_896 <= fifo_data_in[2] @[lib.scala 358:16] - fifo_data[2] <= _T_896 @[dma_ctrl.scala 256:49] - node _T_897 = bits(fifo_data_en, 3, 3) @[dma_ctrl.scala 256:88] + fifo_data[2] <= _T_896 @[dma_ctrl.scala 250:49] + node _T_897 = bits(fifo_data_en, 3, 3) @[dma_ctrl.scala 250:88] inst rvclkhdr_8 of rvclkhdr_837 @[lib.scala 352:23] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset @@ -108294,8 +108291,8 @@ circuit quasar_wrapper : rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_898 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_898 <= fifo_data_in[3] @[lib.scala 358:16] - fifo_data[3] <= _T_898 @[dma_ctrl.scala 256:49] - node _T_899 = bits(fifo_data_en, 4, 4) @[dma_ctrl.scala 256:88] + fifo_data[3] <= _T_898 @[dma_ctrl.scala 250:49] + node _T_899 = bits(fifo_data_en, 4, 4) @[dma_ctrl.scala 250:88] inst rvclkhdr_9 of rvclkhdr_838 @[lib.scala 352:23] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset @@ -108304,142 +108301,142 @@ circuit quasar_wrapper : rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg _T_900 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] _T_900 <= fifo_data_in[4] @[lib.scala 358:16] - fifo_data[4] <= _T_900 @[dma_ctrl.scala 256:49] - node _T_901 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 258:120] + fifo_data[4] <= _T_900 @[dma_ctrl.scala 250:49] + node _T_901 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 252:120] reg _T_902 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_901 : @[Reg.scala 28:19] _T_902 <= bus_cmd_tag @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_tag[0] <= _T_902 @[dma_ctrl.scala 258:48] - node _T_903 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 258:120] + fifo_tag[0] <= _T_902 @[dma_ctrl.scala 252:48] + node _T_903 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 252:120] reg _T_904 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_903 : @[Reg.scala 28:19] _T_904 <= bus_cmd_tag @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_tag[1] <= _T_904 @[dma_ctrl.scala 258:48] - node _T_905 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 258:120] + fifo_tag[1] <= _T_904 @[dma_ctrl.scala 252:48] + node _T_905 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 252:120] reg _T_906 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_905 : @[Reg.scala 28:19] _T_906 <= bus_cmd_tag @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_tag[2] <= _T_906 @[dma_ctrl.scala 258:48] - node _T_907 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 258:120] + fifo_tag[2] <= _T_906 @[dma_ctrl.scala 252:48] + node _T_907 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 252:120] reg _T_908 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_907 : @[Reg.scala 28:19] _T_908 <= bus_cmd_tag @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_tag[3] <= _T_908 @[dma_ctrl.scala 258:48] - node _T_909 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 258:120] + fifo_tag[3] <= _T_908 @[dma_ctrl.scala 252:48] + node _T_909 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 252:120] reg _T_910 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_909 : @[Reg.scala 28:19] _T_910 <= bus_cmd_tag @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_tag[4] <= _T_910 @[dma_ctrl.scala 258:48] - node _T_911 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 260:120] + fifo_tag[4] <= _T_910 @[dma_ctrl.scala 252:48] + node _T_911 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 254:120] reg _T_912 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_911 : @[Reg.scala 28:19] _T_912 <= bus_cmd_mid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_mid[0] <= _T_912 @[dma_ctrl.scala 260:48] - node _T_913 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 260:120] + fifo_mid[0] <= _T_912 @[dma_ctrl.scala 254:48] + node _T_913 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 254:120] reg _T_914 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_913 : @[Reg.scala 28:19] _T_914 <= bus_cmd_mid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_mid[1] <= _T_914 @[dma_ctrl.scala 260:48] - node _T_915 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 260:120] + fifo_mid[1] <= _T_914 @[dma_ctrl.scala 254:48] + node _T_915 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 254:120] reg _T_916 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_915 : @[Reg.scala 28:19] _T_916 <= bus_cmd_mid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_mid[2] <= _T_916 @[dma_ctrl.scala 260:48] - node _T_917 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 260:120] + fifo_mid[2] <= _T_916 @[dma_ctrl.scala 254:48] + node _T_917 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 254:120] reg _T_918 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_917 : @[Reg.scala 28:19] _T_918 <= bus_cmd_mid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_mid[3] <= _T_918 @[dma_ctrl.scala 260:48] - node _T_919 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 260:120] + fifo_mid[3] <= _T_918 @[dma_ctrl.scala 254:48] + node _T_919 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 254:120] reg _T_920 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_919 : @[Reg.scala 28:19] _T_920 <= bus_cmd_mid @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_mid[4] <= _T_920 @[dma_ctrl.scala 260:48] - node _T_921 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 262:122] + fifo_mid[4] <= _T_920 @[dma_ctrl.scala 254:48] + node _T_921 = bits(fifo_cmd_en, 0, 0) @[dma_ctrl.scala 256:122] reg _T_922 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_921 : @[Reg.scala 28:19] _T_922 <= bus_cmd_prty @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_prty[0] <= _T_922 @[dma_ctrl.scala 262:49] - node _T_923 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 262:122] + fifo_prty[0] <= _T_922 @[dma_ctrl.scala 256:49] + node _T_923 = bits(fifo_cmd_en, 1, 1) @[dma_ctrl.scala 256:122] reg _T_924 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_923 : @[Reg.scala 28:19] _T_924 <= bus_cmd_prty @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_prty[1] <= _T_924 @[dma_ctrl.scala 262:49] - node _T_925 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 262:122] + fifo_prty[1] <= _T_924 @[dma_ctrl.scala 256:49] + node _T_925 = bits(fifo_cmd_en, 2, 2) @[dma_ctrl.scala 256:122] reg _T_926 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_925 : @[Reg.scala 28:19] _T_926 <= bus_cmd_prty @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_prty[2] <= _T_926 @[dma_ctrl.scala 262:49] - node _T_927 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 262:122] + fifo_prty[2] <= _T_926 @[dma_ctrl.scala 256:49] + node _T_927 = bits(fifo_cmd_en, 3, 3) @[dma_ctrl.scala 256:122] reg _T_928 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_927 : @[Reg.scala 28:19] _T_928 <= bus_cmd_prty @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_prty[3] <= _T_928 @[dma_ctrl.scala 262:49] - node _T_929 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 262:122] + fifo_prty[3] <= _T_928 @[dma_ctrl.scala 256:49] + node _T_929 = bits(fifo_cmd_en, 4, 4) @[dma_ctrl.scala 256:122] reg _T_930 : UInt, dma_buffer_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_929 : @[Reg.scala 28:19] _T_930 <= bus_cmd_prty @[Reg.scala 28:23] skip @[Reg.scala 28:19] - fifo_prty[4] <= _T_930 @[dma_ctrl.scala 262:49] - node _T_931 = eq(WrPtr, UInt<3>("h04")) @[dma_ctrl.scala 266:30] - node _T_932 = bits(_T_931, 0, 0) @[dma_ctrl.scala 266:57] - node _T_933 = add(WrPtr, UInt<1>("h01")) @[dma_ctrl.scala 266:76] - node _T_934 = tail(_T_933, 1) @[dma_ctrl.scala 266:76] - node _T_935 = mux(_T_932, UInt<1>("h00"), _T_934) @[dma_ctrl.scala 266:22] - NxtWrPtr <= _T_935 @[dma_ctrl.scala 266:16] - node _T_936 = eq(RdPtr, UInt<3>("h04")) @[dma_ctrl.scala 268:30] - node _T_937 = bits(_T_936, 0, 0) @[dma_ctrl.scala 268:57] - node _T_938 = add(RdPtr, UInt<1>("h01")) @[dma_ctrl.scala 268:76] - node _T_939 = tail(_T_938, 1) @[dma_ctrl.scala 268:76] - node _T_940 = mux(_T_937, UInt<1>("h00"), _T_939) @[dma_ctrl.scala 268:22] - NxtRdPtr <= _T_940 @[dma_ctrl.scala 268:16] - node _T_941 = eq(RspPtr, UInt<3>("h04")) @[dma_ctrl.scala 270:31] - node _T_942 = bits(_T_941, 0, 0) @[dma_ctrl.scala 270:58] - node _T_943 = add(RspPtr, UInt<1>("h01")) @[dma_ctrl.scala 270:78] - node _T_944 = tail(_T_943, 1) @[dma_ctrl.scala 270:78] - node _T_945 = mux(_T_942, UInt<1>("h00"), _T_944) @[dma_ctrl.scala 270:22] - NxtRspPtr <= _T_945 @[dma_ctrl.scala 270:16] - node WrPtrEn = orr(fifo_cmd_en) @[dma_ctrl.scala 272:30] - node _T_946 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 274:55] - node _T_947 = bits(dma_address_error, 0, 0) @[dma_ctrl.scala 274:114] - node _T_948 = bits(dma_alignment_error, 0, 0) @[dma_ctrl.scala 274:143] - node _T_949 = or(_T_947, _T_948) @[dma_ctrl.scala 274:121] - node _T_950 = or(_T_949, dma_dbg_cmd_error) @[dma_ctrl.scala 274:150] - node RdPtrEn = or(_T_946, _T_950) @[dma_ctrl.scala 274:93] - node _T_951 = or(bus_rsp_sent, bus_posted_write_done) @[dma_ctrl.scala 276:55] - node _T_952 = and(_T_951, io.dma_bus_clk_en) @[dma_ctrl.scala 276:80] - node RspPtrEn = or(io.dma_dbg_cmd_done, _T_952) @[dma_ctrl.scala 276:39] + fifo_prty[4] <= _T_930 @[dma_ctrl.scala 256:49] + node _T_931 = eq(WrPtr, UInt<3>("h04")) @[dma_ctrl.scala 260:30] + node _T_932 = bits(_T_931, 0, 0) @[dma_ctrl.scala 260:57] + node _T_933 = add(WrPtr, UInt<1>("h01")) @[dma_ctrl.scala 260:76] + node _T_934 = tail(_T_933, 1) @[dma_ctrl.scala 260:76] + node _T_935 = mux(_T_932, UInt<1>("h00"), _T_934) @[dma_ctrl.scala 260:22] + NxtWrPtr <= _T_935 @[dma_ctrl.scala 260:16] + node _T_936 = eq(RdPtr, UInt<3>("h04")) @[dma_ctrl.scala 262:30] + node _T_937 = bits(_T_936, 0, 0) @[dma_ctrl.scala 262:57] + node _T_938 = add(RdPtr, UInt<1>("h01")) @[dma_ctrl.scala 262:76] + node _T_939 = tail(_T_938, 1) @[dma_ctrl.scala 262:76] + node _T_940 = mux(_T_937, UInt<1>("h00"), _T_939) @[dma_ctrl.scala 262:22] + NxtRdPtr <= _T_940 @[dma_ctrl.scala 262:16] + node _T_941 = eq(RspPtr, UInt<3>("h04")) @[dma_ctrl.scala 264:31] + node _T_942 = bits(_T_941, 0, 0) @[dma_ctrl.scala 264:58] + node _T_943 = add(RspPtr, UInt<1>("h01")) @[dma_ctrl.scala 264:78] + node _T_944 = tail(_T_943, 1) @[dma_ctrl.scala 264:78] + node _T_945 = mux(_T_942, UInt<1>("h00"), _T_944) @[dma_ctrl.scala 264:22] + NxtRspPtr <= _T_945 @[dma_ctrl.scala 264:16] + node WrPtrEn = orr(fifo_cmd_en) @[dma_ctrl.scala 266:30] + node _T_946 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 268:55] + node _T_947 = bits(dma_address_error, 0, 0) @[dma_ctrl.scala 268:114] + node _T_948 = bits(dma_alignment_error, 0, 0) @[dma_ctrl.scala 268:143] + node _T_949 = or(_T_947, _T_948) @[dma_ctrl.scala 268:121] + node _T_950 = or(_T_949, dma_dbg_cmd_error) @[dma_ctrl.scala 268:150] + node RdPtrEn = or(_T_946, _T_950) @[dma_ctrl.scala 268:93] + node _T_951 = or(bus_rsp_sent, bus_posted_write_done) @[dma_ctrl.scala 270:55] + node _T_952 = and(_T_951, io.dma_bus_clk_en) @[dma_ctrl.scala 270:80] + node RspPtrEn = or(io.dma_dbg_cmd_done, _T_952) @[dma_ctrl.scala 270:39] reg _T_953 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when WrPtrEn : @[Reg.scala 28:19] _T_953 <= NxtWrPtr @[Reg.scala 28:23] skip @[Reg.scala 28:19] - WrPtr <= _T_953 @[dma_ctrl.scala 278:16] - node _T_954 = bits(RdPtrEn, 0, 0) @[dma_ctrl.scala 283:38] + WrPtr <= _T_953 @[dma_ctrl.scala 272:16] + node _T_954 = bits(RdPtrEn, 0, 0) @[dma_ctrl.scala 277:38] reg _T_955 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_954 : @[Reg.scala 28:19] _T_955 <= NxtRdPtr @[Reg.scala 28:23] skip @[Reg.scala 28:19] - RdPtr <= _T_955 @[dma_ctrl.scala 282:16] - node _T_956 = bits(RspPtrEn, 0, 0) @[dma_ctrl.scala 287:40] + RdPtr <= _T_955 @[dma_ctrl.scala 276:16] + node _T_956 = bits(RspPtrEn, 0, 0) @[dma_ctrl.scala 281:40] reg _T_957 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_956 : @[Reg.scala 28:19] _T_957 <= NxtRspPtr @[Reg.scala 28:23] skip @[Reg.scala 28:19] - RspPtr <= _T_957 @[dma_ctrl.scala 286:16] + RspPtr <= _T_957 @[dma_ctrl.scala 280:16] wire num_fifo_vld_tmp : UInt<4> num_fifo_vld_tmp <= UInt<1>("h00") wire num_fifo_vld_tmp2 : UInt<4> @@ -108448,109 +108445,109 @@ circuit quasar_wrapper : node _T_959 = cat(_T_958, axi_mstr_prty_en) @[Cat.scala 29:58] node _T_960 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] node _T_961 = cat(_T_960, bus_rsp_sent) @[Cat.scala 29:58] - node _T_962 = sub(_T_959, _T_961) @[dma_ctrl.scala 297:62] - node _T_963 = tail(_T_962, 1) @[dma_ctrl.scala 297:62] - num_fifo_vld_tmp <= _T_963 @[dma_ctrl.scala 297:25] + node _T_962 = sub(_T_959, _T_961) @[dma_ctrl.scala 291:62] + node _T_963 = tail(_T_962, 1) @[dma_ctrl.scala 291:62] + num_fifo_vld_tmp <= _T_963 @[dma_ctrl.scala 291:25] node _T_964 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_965 = bits(fifo_valid, 0, 0) @[dma_ctrl.scala 299:88] + node _T_965 = bits(fifo_valid, 0, 0) @[dma_ctrl.scala 293:88] node _T_966 = cat(_T_964, _T_965) @[Cat.scala 29:58] node _T_967 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_968 = bits(fifo_valid, 1, 1) @[dma_ctrl.scala 299:88] + node _T_968 = bits(fifo_valid, 1, 1) @[dma_ctrl.scala 293:88] node _T_969 = cat(_T_967, _T_968) @[Cat.scala 29:58] node _T_970 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_971 = bits(fifo_valid, 2, 2) @[dma_ctrl.scala 299:88] + node _T_971 = bits(fifo_valid, 2, 2) @[dma_ctrl.scala 293:88] node _T_972 = cat(_T_970, _T_971) @[Cat.scala 29:58] node _T_973 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_974 = bits(fifo_valid, 3, 3) @[dma_ctrl.scala 299:88] + node _T_974 = bits(fifo_valid, 3, 3) @[dma_ctrl.scala 293:88] node _T_975 = cat(_T_973, _T_974) @[Cat.scala 29:58] node _T_976 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_977 = bits(fifo_valid, 4, 4) @[dma_ctrl.scala 299:88] + node _T_977 = bits(fifo_valid, 4, 4) @[dma_ctrl.scala 293:88] node _T_978 = cat(_T_976, _T_977) @[Cat.scala 29:58] - node _T_979 = add(_T_966, _T_969) @[dma_ctrl.scala 299:102] - node _T_980 = tail(_T_979, 1) @[dma_ctrl.scala 299:102] - node _T_981 = add(_T_980, _T_972) @[dma_ctrl.scala 299:102] - node _T_982 = tail(_T_981, 1) @[dma_ctrl.scala 299:102] - node _T_983 = add(_T_982, _T_975) @[dma_ctrl.scala 299:102] - node _T_984 = tail(_T_983, 1) @[dma_ctrl.scala 299:102] - node _T_985 = add(_T_984, _T_978) @[dma_ctrl.scala 299:102] - node _T_986 = tail(_T_985, 1) @[dma_ctrl.scala 299:102] - num_fifo_vld_tmp2 <= _T_986 @[dma_ctrl.scala 299:25] - node _T_987 = add(num_fifo_vld_tmp, num_fifo_vld_tmp2) @[dma_ctrl.scala 301:45] - node _T_988 = tail(_T_987, 1) @[dma_ctrl.scala 301:45] - num_fifo_vld <= _T_988 @[dma_ctrl.scala 301:25] - node fifo_full_spec = geq(num_fifo_vld_tmp2, UInt<3>("h05")) @[dma_ctrl.scala 303:46] - node _T_989 = or(fifo_full, dbg_dma_bubble_bus) @[dma_ctrl.scala 305:39] - node dma_fifo_ready = not(_T_989) @[dma_ctrl.scala 305:27] - node _T_990 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 309:38] - node _T_991 = bits(_T_990, 0, 0) @[dma_ctrl.scala 309:38] - node _T_992 = dshr(fifo_done, RdPtr) @[dma_ctrl.scala 309:58] - node _T_993 = bits(_T_992, 0, 0) @[dma_ctrl.scala 309:58] - node _T_994 = eq(_T_993, UInt<1>("h00")) @[dma_ctrl.scala 309:48] - node _T_995 = and(_T_991, _T_994) @[dma_ctrl.scala 309:46] - node _T_996 = dshr(fifo_dbg, RdPtr) @[dma_ctrl.scala 309:77] - node _T_997 = bits(_T_996, 0, 0) @[dma_ctrl.scala 309:77] - node _T_998 = eq(_T_997, UInt<1>("h00")) @[dma_ctrl.scala 309:68] - node _T_999 = and(_T_995, _T_998) @[dma_ctrl.scala 309:66] - node _T_1000 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_iccm) @[dma_ctrl.scala 309:111] - node _T_1001 = not(_T_1000) @[dma_ctrl.scala 309:88] - node _T_1002 = and(_T_999, _T_1001) @[dma_ctrl.scala 309:85] - dma_address_error <= _T_1002 @[dma_ctrl.scala 309:25] - node _T_1003 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 310:38] - node _T_1004 = bits(_T_1003, 0, 0) @[dma_ctrl.scala 310:38] - node _T_1005 = dshr(fifo_done, RdPtr) @[dma_ctrl.scala 310:58] - node _T_1006 = bits(_T_1005, 0, 0) @[dma_ctrl.scala 310:58] - node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[dma_ctrl.scala 310:48] - node _T_1008 = and(_T_1004, _T_1007) @[dma_ctrl.scala 310:46] - node _T_1009 = eq(dma_address_error, UInt<1>("h00")) @[dma_ctrl.scala 310:68] - node _T_1010 = and(_T_1008, _T_1009) @[dma_ctrl.scala 310:66] - node _T_1011 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 311:22] - node _T_1012 = eq(_T_1011, UInt<1>("h01")) @[dma_ctrl.scala 311:28] - node _T_1013 = bits(dma_mem_addr_int, 0, 0) @[dma_ctrl.scala 311:55] - node _T_1014 = and(_T_1012, _T_1013) @[dma_ctrl.scala 311:37] - node _T_1015 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 312:23] - node _T_1016 = eq(_T_1015, UInt<2>("h02")) @[dma_ctrl.scala 312:29] - node _T_1017 = bits(dma_mem_addr_int, 1, 0) @[dma_ctrl.scala 312:57] - node _T_1018 = orr(_T_1017) @[dma_ctrl.scala 312:64] - node _T_1019 = and(_T_1016, _T_1018) @[dma_ctrl.scala 312:38] - node _T_1020 = or(_T_1014, _T_1019) @[dma_ctrl.scala 311:60] - node _T_1021 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 313:23] - node _T_1022 = eq(_T_1021, UInt<2>("h03")) @[dma_ctrl.scala 313:29] - node _T_1023 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 313:57] - node _T_1024 = orr(_T_1023) @[dma_ctrl.scala 313:64] - node _T_1025 = and(_T_1022, _T_1024) @[dma_ctrl.scala 313:38] - node _T_1026 = or(_T_1020, _T_1025) @[dma_ctrl.scala 312:70] - node _T_1027 = bits(dma_mem_sz_int, 1, 0) @[dma_ctrl.scala 314:48] - node _T_1028 = eq(_T_1027, UInt<2>("h02")) @[dma_ctrl.scala 314:55] - node _T_1029 = bits(dma_mem_sz_int, 1, 0) @[dma_ctrl.scala 314:81] - node _T_1030 = eq(_T_1029, UInt<2>("h03")) @[dma_ctrl.scala 314:88] - node _T_1031 = or(_T_1028, _T_1030) @[dma_ctrl.scala 314:64] - node _T_1032 = not(_T_1031) @[dma_ctrl.scala 314:31] - node _T_1033 = and(dma_mem_addr_in_iccm, _T_1032) @[dma_ctrl.scala 314:29] - node _T_1034 = or(_T_1026, _T_1033) @[dma_ctrl.scala 313:70] - node _T_1035 = and(dma_mem_addr_in_dccm, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 315:29] - node _T_1036 = bits(dma_mem_sz_int, 1, 0) @[dma_ctrl.scala 315:87] - node _T_1037 = eq(_T_1036, UInt<2>("h02")) @[dma_ctrl.scala 315:94] - node _T_1038 = bits(dma_mem_sz_int, 1, 0) @[dma_ctrl.scala 315:120] - node _T_1039 = eq(_T_1038, UInt<2>("h03")) @[dma_ctrl.scala 315:127] - node _T_1040 = or(_T_1037, _T_1039) @[dma_ctrl.scala 315:103] - node _T_1041 = not(_T_1040) @[dma_ctrl.scala 315:70] - node _T_1042 = and(_T_1035, _T_1041) @[dma_ctrl.scala 315:68] - node _T_1043 = or(_T_1034, _T_1042) @[dma_ctrl.scala 314:108] - node _T_1044 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 316:62] - node _T_1045 = eq(_T_1044, UInt<2>("h02")) @[dma_ctrl.scala 316:69] - node _T_1046 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1045) @[dma_ctrl.scala 316:45] - node _T_1047 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 316:108] - node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[dma_ctrl.scala 316:114] - node _T_1049 = bits(dma_mem_byteen, 3, 0) @[dma_ctrl.scala 316:141] - node _T_1050 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 317:26] - node _T_1051 = eq(_T_1050, UInt<1>("h01")) @[dma_ctrl.scala 317:32] - node _T_1052 = bits(dma_mem_byteen, 4, 1) @[dma_ctrl.scala 317:59] - node _T_1053 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 318:26] - node _T_1054 = eq(_T_1053, UInt<2>("h02")) @[dma_ctrl.scala 318:32] - node _T_1055 = bits(dma_mem_byteen, 5, 2) @[dma_ctrl.scala 318:59] - node _T_1056 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 319:26] - node _T_1057 = eq(_T_1056, UInt<2>("h03")) @[dma_ctrl.scala 319:32] - node _T_1058 = bits(dma_mem_byteen, 6, 3) @[dma_ctrl.scala 319:59] + node _T_979 = add(_T_966, _T_969) @[dma_ctrl.scala 293:102] + node _T_980 = tail(_T_979, 1) @[dma_ctrl.scala 293:102] + node _T_981 = add(_T_980, _T_972) @[dma_ctrl.scala 293:102] + node _T_982 = tail(_T_981, 1) @[dma_ctrl.scala 293:102] + node _T_983 = add(_T_982, _T_975) @[dma_ctrl.scala 293:102] + node _T_984 = tail(_T_983, 1) @[dma_ctrl.scala 293:102] + node _T_985 = add(_T_984, _T_978) @[dma_ctrl.scala 293:102] + node _T_986 = tail(_T_985, 1) @[dma_ctrl.scala 293:102] + num_fifo_vld_tmp2 <= _T_986 @[dma_ctrl.scala 293:25] + node _T_987 = add(num_fifo_vld_tmp, num_fifo_vld_tmp2) @[dma_ctrl.scala 295:45] + node _T_988 = tail(_T_987, 1) @[dma_ctrl.scala 295:45] + num_fifo_vld <= _T_988 @[dma_ctrl.scala 295:25] + node fifo_full_spec = geq(num_fifo_vld_tmp2, UInt<3>("h05")) @[dma_ctrl.scala 297:46] + node _T_989 = or(fifo_full, dbg_dma_bubble_bus) @[dma_ctrl.scala 299:39] + node dma_fifo_ready = not(_T_989) @[dma_ctrl.scala 299:27] + node _T_990 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 303:38] + node _T_991 = bits(_T_990, 0, 0) @[dma_ctrl.scala 303:38] + node _T_992 = dshr(fifo_done, RdPtr) @[dma_ctrl.scala 303:58] + node _T_993 = bits(_T_992, 0, 0) @[dma_ctrl.scala 303:58] + node _T_994 = eq(_T_993, UInt<1>("h00")) @[dma_ctrl.scala 303:48] + node _T_995 = and(_T_991, _T_994) @[dma_ctrl.scala 303:46] + node _T_996 = dshr(fifo_dbg, RdPtr) @[dma_ctrl.scala 303:77] + node _T_997 = bits(_T_996, 0, 0) @[dma_ctrl.scala 303:77] + node _T_998 = eq(_T_997, UInt<1>("h00")) @[dma_ctrl.scala 303:68] + node _T_999 = and(_T_995, _T_998) @[dma_ctrl.scala 303:66] + node _T_1000 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_iccm) @[dma_ctrl.scala 303:111] + node _T_1001 = not(_T_1000) @[dma_ctrl.scala 303:88] + node _T_1002 = and(_T_999, _T_1001) @[dma_ctrl.scala 303:85] + dma_address_error <= _T_1002 @[dma_ctrl.scala 303:25] + node _T_1003 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 304:38] + node _T_1004 = bits(_T_1003, 0, 0) @[dma_ctrl.scala 304:38] + node _T_1005 = dshr(fifo_done, RdPtr) @[dma_ctrl.scala 304:58] + node _T_1006 = bits(_T_1005, 0, 0) @[dma_ctrl.scala 304:58] + node _T_1007 = eq(_T_1006, UInt<1>("h00")) @[dma_ctrl.scala 304:48] + node _T_1008 = and(_T_1004, _T_1007) @[dma_ctrl.scala 304:46] + node _T_1009 = eq(dma_address_error, UInt<1>("h00")) @[dma_ctrl.scala 304:68] + node _T_1010 = and(_T_1008, _T_1009) @[dma_ctrl.scala 304:66] + node _T_1011 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 305:22] + node _T_1012 = eq(_T_1011, UInt<1>("h01")) @[dma_ctrl.scala 305:28] + node _T_1013 = bits(dma_mem_addr_int, 0, 0) @[dma_ctrl.scala 305:55] + node _T_1014 = and(_T_1012, _T_1013) @[dma_ctrl.scala 305:37] + node _T_1015 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 306:23] + node _T_1016 = eq(_T_1015, UInt<2>("h02")) @[dma_ctrl.scala 306:29] + node _T_1017 = bits(dma_mem_addr_int, 1, 0) @[dma_ctrl.scala 306:57] + node _T_1018 = orr(_T_1017) @[dma_ctrl.scala 306:64] + node _T_1019 = and(_T_1016, _T_1018) @[dma_ctrl.scala 306:38] + node _T_1020 = or(_T_1014, _T_1019) @[dma_ctrl.scala 305:60] + node _T_1021 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 307:23] + node _T_1022 = eq(_T_1021, UInt<2>("h03")) @[dma_ctrl.scala 307:29] + node _T_1023 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 307:57] + node _T_1024 = orr(_T_1023) @[dma_ctrl.scala 307:64] + node _T_1025 = and(_T_1022, _T_1024) @[dma_ctrl.scala 307:38] + node _T_1026 = or(_T_1020, _T_1025) @[dma_ctrl.scala 306:70] + node _T_1027 = bits(dma_mem_sz_int, 1, 0) @[dma_ctrl.scala 308:48] + node _T_1028 = eq(_T_1027, UInt<2>("h02")) @[dma_ctrl.scala 308:55] + node _T_1029 = bits(dma_mem_sz_int, 1, 0) @[dma_ctrl.scala 308:81] + node _T_1030 = eq(_T_1029, UInt<2>("h03")) @[dma_ctrl.scala 308:88] + node _T_1031 = or(_T_1028, _T_1030) @[dma_ctrl.scala 308:64] + node _T_1032 = not(_T_1031) @[dma_ctrl.scala 308:31] + node _T_1033 = and(dma_mem_addr_in_iccm, _T_1032) @[dma_ctrl.scala 308:29] + node _T_1034 = or(_T_1026, _T_1033) @[dma_ctrl.scala 307:70] + node _T_1035 = and(dma_mem_addr_in_dccm, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 309:29] + node _T_1036 = bits(dma_mem_sz_int, 1, 0) @[dma_ctrl.scala 309:87] + node _T_1037 = eq(_T_1036, UInt<2>("h02")) @[dma_ctrl.scala 309:94] + node _T_1038 = bits(dma_mem_sz_int, 1, 0) @[dma_ctrl.scala 309:120] + node _T_1039 = eq(_T_1038, UInt<2>("h03")) @[dma_ctrl.scala 309:127] + node _T_1040 = or(_T_1037, _T_1039) @[dma_ctrl.scala 309:103] + node _T_1041 = not(_T_1040) @[dma_ctrl.scala 309:70] + node _T_1042 = and(_T_1035, _T_1041) @[dma_ctrl.scala 309:68] + node _T_1043 = or(_T_1034, _T_1042) @[dma_ctrl.scala 308:108] + node _T_1044 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 310:62] + node _T_1045 = eq(_T_1044, UInt<2>("h02")) @[dma_ctrl.scala 310:69] + node _T_1046 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1045) @[dma_ctrl.scala 310:45] + node _T_1047 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 310:108] + node _T_1048 = eq(_T_1047, UInt<1>("h00")) @[dma_ctrl.scala 310:114] + node _T_1049 = bits(dma_mem_byteen, 3, 0) @[dma_ctrl.scala 310:141] + node _T_1050 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 311:26] + node _T_1051 = eq(_T_1050, UInt<1>("h01")) @[dma_ctrl.scala 311:32] + node _T_1052 = bits(dma_mem_byteen, 4, 1) @[dma_ctrl.scala 311:59] + node _T_1053 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 312:26] + node _T_1054 = eq(_T_1053, UInt<2>("h02")) @[dma_ctrl.scala 312:32] + node _T_1055 = bits(dma_mem_byteen, 5, 2) @[dma_ctrl.scala 312:59] + node _T_1056 = bits(dma_mem_addr_int, 2, 0) @[dma_ctrl.scala 313:26] + node _T_1057 = eq(_T_1056, UInt<2>("h03")) @[dma_ctrl.scala 313:32] + node _T_1058 = bits(dma_mem_byteen, 6, 3) @[dma_ctrl.scala 313:59] node _T_1059 = mux(_T_1048, _T_1049, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1060 = mux(_T_1051, _T_1052, UInt<1>("h00")) @[Mux.scala 27:72] node _T_1061 = mux(_T_1054, _T_1055, UInt<1>("h00")) @[Mux.scala 27:72] @@ -108560,219 +108557,221 @@ circuit quasar_wrapper : node _T_1065 = or(_T_1064, _T_1062) @[Mux.scala 27:72] wire _T_1066 : UInt<4> @[Mux.scala 27:72] _T_1066 <= _T_1065 @[Mux.scala 27:72] - node _T_1067 = neq(_T_1066, UInt<4>("h0f")) @[dma_ctrl.scala 319:68] - node _T_1068 = and(_T_1046, _T_1067) @[dma_ctrl.scala 316:78] - node _T_1069 = or(_T_1043, _T_1068) @[dma_ctrl.scala 315:145] - node _T_1070 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 320:62] - node _T_1071 = eq(_T_1070, UInt<2>("h03")) @[dma_ctrl.scala 320:69] - node _T_1072 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1071) @[dma_ctrl.scala 320:45] - node _T_1073 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 320:97] - node _T_1074 = eq(_T_1073, UInt<4>("h0f")) @[dma_ctrl.scala 320:103] - node _T_1075 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 320:133] - node _T_1076 = eq(_T_1075, UInt<8>("h0f0")) @[dma_ctrl.scala 320:139] - node _T_1077 = or(_T_1074, _T_1076) @[dma_ctrl.scala 320:116] - node _T_1078 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 320:169] - node _T_1079 = eq(_T_1078, UInt<8>("h0ff")) @[dma_ctrl.scala 320:175] - node _T_1080 = or(_T_1077, _T_1079) @[dma_ctrl.scala 320:152] - node _T_1081 = eq(_T_1080, UInt<1>("h00")) @[dma_ctrl.scala 320:80] - node _T_1082 = and(_T_1072, _T_1081) @[dma_ctrl.scala 320:78] - node _T_1083 = or(_T_1069, _T_1082) @[dma_ctrl.scala 319:79] - node _T_1084 = and(_T_1010, _T_1083) @[dma_ctrl.scala 310:87] - dma_alignment_error <= _T_1084 @[dma_ctrl.scala 310:25] - node _T_1085 = and(fifo_empty, dbg_dma_bubble_bus) @[dma_ctrl.scala 325:50] - io.dbg_dma_io.dma_dbg_ready <= _T_1085 @[dma_ctrl.scala 325:36] - node _T_1086 = dshr(fifo_valid, RspPtr) @[dma_ctrl.scala 326:39] - node _T_1087 = bits(_T_1086, 0, 0) @[dma_ctrl.scala 326:39] - node _T_1088 = dshr(fifo_dbg, RspPtr) @[dma_ctrl.scala 326:58] - node _T_1089 = bits(_T_1088, 0, 0) @[dma_ctrl.scala 326:58] - node _T_1090 = and(_T_1087, _T_1089) @[dma_ctrl.scala 326:48] - node _T_1091 = dshr(fifo_done, RspPtr) @[dma_ctrl.scala 326:78] - node _T_1092 = bits(_T_1091, 0, 0) @[dma_ctrl.scala 326:78] - node _T_1093 = and(_T_1090, _T_1092) @[dma_ctrl.scala 326:67] - io.dma_dbg_cmd_done <= _T_1093 @[dma_ctrl.scala 326:25] - node _T_1094 = bits(fifo_addr[RspPtr], 2, 2) @[dma_ctrl.scala 327:49] - node _T_1095 = bits(fifo_data[RspPtr], 63, 32) @[dma_ctrl.scala 327:71] - node _T_1096 = bits(fifo_data[RspPtr], 31, 0) @[dma_ctrl.scala 327:98] - node _T_1097 = mux(_T_1094, _T_1095, _T_1096) @[dma_ctrl.scala 327:31] - io.dma_dbg_rddata <= _T_1097 @[dma_ctrl.scala 327:25] - node _T_1098 = orr(fifo_error[RspPtr]) @[dma_ctrl.scala 328:47] - io.dma_dbg_cmd_fail <= _T_1098 @[dma_ctrl.scala 328:25] - node _T_1099 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 330:38] - node _T_1100 = bits(_T_1099, 0, 0) @[dma_ctrl.scala 330:38] - node _T_1101 = dshr(fifo_done, RdPtr) @[dma_ctrl.scala 330:58] - node _T_1102 = bits(_T_1101, 0, 0) @[dma_ctrl.scala 330:58] - node _T_1103 = eq(_T_1102, UInt<1>("h00")) @[dma_ctrl.scala 330:48] - node _T_1104 = and(_T_1100, _T_1103) @[dma_ctrl.scala 330:46] - node _T_1105 = dshr(fifo_dbg, RdPtr) @[dma_ctrl.scala 330:76] - node _T_1106 = bits(_T_1105, 0, 0) @[dma_ctrl.scala 330:76] - node _T_1107 = and(_T_1104, _T_1106) @[dma_ctrl.scala 330:66] - node _T_1108 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_iccm) @[dma_ctrl.scala 330:111] - node _T_1109 = or(_T_1108, dma_mem_addr_in_pic) @[dma_ctrl.scala 330:134] - node _T_1110 = not(_T_1109) @[dma_ctrl.scala 330:88] - node _T_1111 = bits(_T_1110, 0, 0) @[dma_ctrl.scala 330:164] - node _T_1112 = bits(dma_mem_sz_int, 1, 0) @[dma_ctrl.scala 330:184] - node _T_1113 = neq(_T_1112, UInt<2>("h02")) @[dma_ctrl.scala 330:191] - node _T_1114 = or(_T_1111, _T_1113) @[dma_ctrl.scala 330:167] - node _T_1115 = and(_T_1107, _T_1114) @[dma_ctrl.scala 330:84] - dma_dbg_cmd_error <= _T_1115 @[dma_ctrl.scala 330:25] - node _T_1116 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_pic) @[dma_ctrl.scala 334:64] - node _T_1117 = and(dma_mem_req, _T_1116) @[dma_ctrl.scala 334:40] - node _T_1118 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 334:105] - node _T_1119 = and(_T_1117, _T_1118) @[dma_ctrl.scala 334:87] - io.dma_dccm_stall_any <= _T_1119 @[dma_ctrl.scala 334:25] - node _T_1120 = and(dma_mem_req, dma_mem_addr_in_iccm) @[dma_ctrl.scala 335:56] - node _T_1121 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 335:97] - node _T_1122 = and(_T_1120, _T_1121) @[dma_ctrl.scala 335:79] - io.ifu_dma.dma_ifc.dma_iccm_stall_any <= _T_1122 @[dma_ctrl.scala 335:41] - node _T_1123 = orr(fifo_valid) @[dma_ctrl.scala 339:30] - node _T_1124 = not(_T_1123) @[dma_ctrl.scala 339:17] - fifo_empty <= _T_1124 @[dma_ctrl.scala 339:14] - dma_nack_count_csr <= io.dec_tlu_dma_qos_prty @[dma_ctrl.scala 343:22] - node _T_1125 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 344:45] - node _T_1126 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 344:115] - node _T_1127 = eq(_T_1126, UInt<1>("h00")) @[dma_ctrl.scala 344:77] + node _T_1067 = neq(_T_1066, UInt<4>("h0f")) @[dma_ctrl.scala 313:68] + node _T_1068 = and(_T_1046, _T_1067) @[dma_ctrl.scala 310:78] + node _T_1069 = or(_T_1043, _T_1068) @[dma_ctrl.scala 309:145] + node _T_1070 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 314:62] + node _T_1071 = eq(_T_1070, UInt<2>("h03")) @[dma_ctrl.scala 314:69] + node _T_1072 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1071) @[dma_ctrl.scala 314:45] + node _T_1073 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 314:97] + node _T_1074 = eq(_T_1073, UInt<4>("h0f")) @[dma_ctrl.scala 314:103] + node _T_1075 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 314:133] + node _T_1076 = eq(_T_1075, UInt<8>("h0f0")) @[dma_ctrl.scala 314:139] + node _T_1077 = or(_T_1074, _T_1076) @[dma_ctrl.scala 314:116] + node _T_1078 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 314:169] + node _T_1079 = eq(_T_1078, UInt<8>("h0ff")) @[dma_ctrl.scala 314:175] + node _T_1080 = or(_T_1077, _T_1079) @[dma_ctrl.scala 314:152] + node _T_1081 = eq(_T_1080, UInt<1>("h00")) @[dma_ctrl.scala 314:80] + node _T_1082 = and(_T_1072, _T_1081) @[dma_ctrl.scala 314:78] + node _T_1083 = or(_T_1069, _T_1082) @[dma_ctrl.scala 313:79] + node _T_1084 = and(_T_1010, _T_1083) @[dma_ctrl.scala 304:87] + dma_alignment_error <= _T_1084 @[dma_ctrl.scala 304:25] + node _T_1085 = and(fifo_empty, dbg_dma_bubble_bus) @[dma_ctrl.scala 319:50] + io.dbg_dma_io.dma_dbg_ready <= _T_1085 @[dma_ctrl.scala 319:36] + node _T_1086 = dshr(fifo_valid, RspPtr) @[dma_ctrl.scala 320:39] + node _T_1087 = bits(_T_1086, 0, 0) @[dma_ctrl.scala 320:39] + node _T_1088 = dshr(fifo_dbg, RspPtr) @[dma_ctrl.scala 320:58] + node _T_1089 = bits(_T_1088, 0, 0) @[dma_ctrl.scala 320:58] + node _T_1090 = and(_T_1087, _T_1089) @[dma_ctrl.scala 320:48] + node _T_1091 = dshr(fifo_done, RspPtr) @[dma_ctrl.scala 320:78] + node _T_1092 = bits(_T_1091, 0, 0) @[dma_ctrl.scala 320:78] + node _T_1093 = and(_T_1090, _T_1092) @[dma_ctrl.scala 320:67] + io.dma_dbg_cmd_done <= _T_1093 @[dma_ctrl.scala 320:25] + node _T_1094 = bits(fifo_addr[RspPtr], 2, 2) @[dma_ctrl.scala 321:49] + node _T_1095 = bits(fifo_data[RspPtr], 63, 32) @[dma_ctrl.scala 321:71] + node _T_1096 = bits(fifo_data[RspPtr], 31, 0) @[dma_ctrl.scala 321:98] + node _T_1097 = mux(_T_1094, _T_1095, _T_1096) @[dma_ctrl.scala 321:31] + io.dma_dbg_rddata <= _T_1097 @[dma_ctrl.scala 321:25] + node _T_1098 = orr(fifo_error[RspPtr]) @[dma_ctrl.scala 322:47] + io.dma_dbg_cmd_fail <= _T_1098 @[dma_ctrl.scala 322:25] + node _T_1099 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 324:38] + node _T_1100 = bits(_T_1099, 0, 0) @[dma_ctrl.scala 324:38] + node _T_1101 = dshr(fifo_done, RdPtr) @[dma_ctrl.scala 324:58] + node _T_1102 = bits(_T_1101, 0, 0) @[dma_ctrl.scala 324:58] + node _T_1103 = eq(_T_1102, UInt<1>("h00")) @[dma_ctrl.scala 324:48] + node _T_1104 = and(_T_1100, _T_1103) @[dma_ctrl.scala 324:46] + node _T_1105 = dshr(fifo_dbg, RdPtr) @[dma_ctrl.scala 324:76] + node _T_1106 = bits(_T_1105, 0, 0) @[dma_ctrl.scala 324:76] + node _T_1107 = and(_T_1104, _T_1106) @[dma_ctrl.scala 324:66] + node _T_1108 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_iccm) @[dma_ctrl.scala 324:111] + node _T_1109 = or(_T_1108, dma_mem_addr_in_pic) @[dma_ctrl.scala 324:134] + node _T_1110 = not(_T_1109) @[dma_ctrl.scala 324:88] + node _T_1111 = bits(_T_1110, 0, 0) @[dma_ctrl.scala 324:164] + node _T_1112 = bits(dma_mem_sz_int, 1, 0) @[dma_ctrl.scala 324:184] + node _T_1113 = neq(_T_1112, UInt<2>("h02")) @[dma_ctrl.scala 324:191] + node _T_1114 = or(_T_1111, _T_1113) @[dma_ctrl.scala 324:167] + node _T_1115 = and(_T_1107, _T_1114) @[dma_ctrl.scala 324:84] + dma_dbg_cmd_error <= _T_1115 @[dma_ctrl.scala 324:25] + node _T_1116 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_pic) @[dma_ctrl.scala 328:80] + node _T_1117 = and(dma_mem_req, _T_1116) @[dma_ctrl.scala 328:56] + node _T_1118 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 328:121] + node _T_1119 = and(_T_1117, _T_1118) @[dma_ctrl.scala 328:103] + io.dec_dma.tlu_dma.dma_dccm_stall_any <= _T_1119 @[dma_ctrl.scala 328:41] + node _T_1120 = and(dma_mem_req, dma_mem_addr_in_iccm) @[dma_ctrl.scala 329:56] + node _T_1121 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 329:97] + node _T_1122 = and(_T_1120, _T_1121) @[dma_ctrl.scala 329:79] + io.ifu_dma.dma_ifc.dma_iccm_stall_any <= _T_1122 @[dma_ctrl.scala 329:41] + io.dec_dma.tlu_dma.dma_iccm_stall_any <= io.ifu_dma.dma_ifc.dma_iccm_stall_any @[dma_ctrl.scala 330:41] + io.dec_dma.dctl_dma.dma_dccm_stall_any <= io.dec_dma.tlu_dma.dma_dccm_stall_any @[dma_ctrl.scala 331:42] + node _T_1123 = orr(fifo_valid) @[dma_ctrl.scala 334:30] + node _T_1124 = not(_T_1123) @[dma_ctrl.scala 334:17] + fifo_empty <= _T_1124 @[dma_ctrl.scala 334:14] + dma_nack_count_csr <= io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty @[dma_ctrl.scala 338:22] + node _T_1125 = geq(dma_nack_count, dma_nack_count_csr) @[dma_ctrl.scala 339:45] + node _T_1126 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 339:115] + node _T_1127 = eq(_T_1126, UInt<1>("h00")) @[dma_ctrl.scala 339:77] node _T_1128 = bits(_T_1127, 0, 0) @[Bitwise.scala 72:15] node _T_1129 = mux(_T_1128, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_1130 = bits(dma_nack_count, 2, 0) @[dma_ctrl.scala 344:171] - node _T_1131 = and(_T_1129, _T_1130) @[dma_ctrl.scala 344:155] - node _T_1132 = bits(dma_mem_req, 0, 0) @[dma_ctrl.scala 344:196] - node _T_1133 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 344:243] - node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[dma_ctrl.scala 344:205] - node _T_1135 = and(_T_1132, _T_1134) @[dma_ctrl.scala 344:203] - node _T_1136 = bits(dma_nack_count, 2, 0) @[dma_ctrl.scala 344:298] - node _T_1137 = add(_T_1136, UInt<1>("h01")) @[dma_ctrl.scala 344:304] - node _T_1138 = tail(_T_1137, 1) @[dma_ctrl.scala 344:304] - node _T_1139 = mux(_T_1135, _T_1138, UInt<1>("h00")) @[dma_ctrl.scala 344:182] - node dma_nack_count_d = mux(_T_1125, _T_1131, _T_1139) @[dma_ctrl.scala 344:29] - node _T_1140 = bits(dma_nack_count_d, 2, 0) @[dma_ctrl.scala 347:31] - node _T_1141 = bits(dma_mem_req, 0, 0) @[dma_ctrl.scala 347:55] + node _T_1130 = bits(dma_nack_count, 2, 0) @[dma_ctrl.scala 339:171] + node _T_1131 = and(_T_1129, _T_1130) @[dma_ctrl.scala 339:155] + node _T_1132 = bits(dma_mem_req, 0, 0) @[dma_ctrl.scala 339:196] + node _T_1133 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 339:243] + node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[dma_ctrl.scala 339:205] + node _T_1135 = and(_T_1132, _T_1134) @[dma_ctrl.scala 339:203] + node _T_1136 = bits(dma_nack_count, 2, 0) @[dma_ctrl.scala 339:298] + node _T_1137 = add(_T_1136, UInt<1>("h01")) @[dma_ctrl.scala 339:304] + node _T_1138 = tail(_T_1137, 1) @[dma_ctrl.scala 339:304] + node _T_1139 = mux(_T_1135, _T_1138, UInt<1>("h00")) @[dma_ctrl.scala 339:182] + node dma_nack_count_d = mux(_T_1125, _T_1131, _T_1139) @[dma_ctrl.scala 339:29] + node _T_1140 = bits(dma_nack_count_d, 2, 0) @[dma_ctrl.scala 342:31] + node _T_1141 = bits(dma_mem_req, 0, 0) @[dma_ctrl.scala 342:55] reg _T_1142 : UInt, dma_free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1141 : @[Reg.scala 28:19] _T_1142 <= _T_1140 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - dma_nack_count <= _T_1142 @[dma_ctrl.scala 346:22] - node _T_1143 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 352:33] - node _T_1144 = bits(_T_1143, 0, 0) @[dma_ctrl.scala 352:33] - node _T_1145 = dshr(fifo_rpend, RdPtr) @[dma_ctrl.scala 352:54] - node _T_1146 = bits(_T_1145, 0, 0) @[dma_ctrl.scala 352:54] - node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[dma_ctrl.scala 352:43] - node _T_1148 = and(_T_1144, _T_1147) @[dma_ctrl.scala 352:41] - node _T_1149 = dshr(fifo_done, RdPtr) @[dma_ctrl.scala 352:74] - node _T_1150 = bits(_T_1149, 0, 0) @[dma_ctrl.scala 352:74] - node _T_1151 = eq(_T_1150, UInt<1>("h00")) @[dma_ctrl.scala 352:64] - node _T_1152 = and(_T_1148, _T_1151) @[dma_ctrl.scala 352:62] - node _T_1153 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 352:104] - node _T_1154 = or(_T_1153, dma_dbg_cmd_error) @[dma_ctrl.scala 352:126] - node _T_1155 = eq(_T_1154, UInt<1>("h00")) @[dma_ctrl.scala 352:84] - node _T_1156 = and(_T_1152, _T_1155) @[dma_ctrl.scala 352:82] - dma_mem_req <= _T_1156 @[dma_ctrl.scala 352:20] - node _T_1157 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_pic) @[dma_ctrl.scala 353:79] - node _T_1158 = and(dma_mem_req, _T_1157) @[dma_ctrl.scala 353:55] - node _T_1159 = and(_T_1158, io.lsu_dma.dccm_ready) @[dma_ctrl.scala 353:102] - io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= _T_1159 @[dma_ctrl.scala 353:40] - node _T_1160 = and(dma_mem_req, dma_mem_addr_in_iccm) @[dma_ctrl.scala 354:55] - node _T_1161 = and(_T_1160, io.iccm_ready) @[dma_ctrl.scala 354:78] - io.ifu_dma.dma_mem_ctl.dma_iccm_req <= _T_1161 @[dma_ctrl.scala 354:40] - io.lsu_dma.dma_mem_tag <= RdPtr @[dma_ctrl.scala 355:28] - dma_mem_addr_int <= fifo_addr[RdPtr] @[dma_ctrl.scala 356:20] - dma_mem_sz_int <= fifo_sz[RdPtr] @[dma_ctrl.scala 357:20] - node _T_1162 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 358:101] - node _T_1163 = eq(_T_1162, UInt<8>("h0f0")) @[dma_ctrl.scala 358:107] - node _T_1164 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1163) @[dma_ctrl.scala 358:84] - node _T_1165 = bits(dma_mem_addr_int, 31, 3) @[dma_ctrl.scala 358:141] - node _T_1166 = bits(dma_mem_addr_int, 1, 0) @[dma_ctrl.scala 358:171] + dma_nack_count <= _T_1142 @[dma_ctrl.scala 341:22] + node _T_1143 = dshr(fifo_valid, RdPtr) @[dma_ctrl.scala 347:33] + node _T_1144 = bits(_T_1143, 0, 0) @[dma_ctrl.scala 347:33] + node _T_1145 = dshr(fifo_rpend, RdPtr) @[dma_ctrl.scala 347:54] + node _T_1146 = bits(_T_1145, 0, 0) @[dma_ctrl.scala 347:54] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[dma_ctrl.scala 347:43] + node _T_1148 = and(_T_1144, _T_1147) @[dma_ctrl.scala 347:41] + node _T_1149 = dshr(fifo_done, RdPtr) @[dma_ctrl.scala 347:74] + node _T_1150 = bits(_T_1149, 0, 0) @[dma_ctrl.scala 347:74] + node _T_1151 = eq(_T_1150, UInt<1>("h00")) @[dma_ctrl.scala 347:64] + node _T_1152 = and(_T_1148, _T_1151) @[dma_ctrl.scala 347:62] + node _T_1153 = or(dma_address_error, dma_alignment_error) @[dma_ctrl.scala 347:104] + node _T_1154 = or(_T_1153, dma_dbg_cmd_error) @[dma_ctrl.scala 347:126] + node _T_1155 = eq(_T_1154, UInt<1>("h00")) @[dma_ctrl.scala 347:84] + node _T_1156 = and(_T_1152, _T_1155) @[dma_ctrl.scala 347:82] + dma_mem_req <= _T_1156 @[dma_ctrl.scala 347:20] + node _T_1157 = or(dma_mem_addr_in_dccm, dma_mem_addr_in_pic) @[dma_ctrl.scala 348:79] + node _T_1158 = and(dma_mem_req, _T_1157) @[dma_ctrl.scala 348:55] + node _T_1159 = and(_T_1158, io.lsu_dma.dccm_ready) @[dma_ctrl.scala 348:102] + io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= _T_1159 @[dma_ctrl.scala 348:40] + node _T_1160 = and(dma_mem_req, dma_mem_addr_in_iccm) @[dma_ctrl.scala 349:55] + node _T_1161 = and(_T_1160, io.iccm_ready) @[dma_ctrl.scala 349:78] + io.ifu_dma.dma_mem_ctl.dma_iccm_req <= _T_1161 @[dma_ctrl.scala 349:40] + io.lsu_dma.dma_mem_tag <= RdPtr @[dma_ctrl.scala 350:28] + dma_mem_addr_int <= fifo_addr[RdPtr] @[dma_ctrl.scala 351:20] + dma_mem_sz_int <= fifo_sz[RdPtr] @[dma_ctrl.scala 352:20] + node _T_1162 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 353:101] + node _T_1163 = eq(_T_1162, UInt<8>("h0f0")) @[dma_ctrl.scala 353:107] + node _T_1164 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1163) @[dma_ctrl.scala 353:84] + node _T_1165 = bits(dma_mem_addr_int, 31, 3) @[dma_ctrl.scala 353:141] + node _T_1166 = bits(dma_mem_addr_int, 1, 0) @[dma_ctrl.scala 353:171] node _T_1167 = cat(_T_1165, UInt<1>("h01")) @[Cat.scala 29:58] node _T_1168 = cat(_T_1167, _T_1166) @[Cat.scala 29:58] - node _T_1169 = bits(dma_mem_addr_int, 31, 0) @[dma_ctrl.scala 358:196] - node _T_1170 = mux(_T_1164, _T_1168, _T_1169) @[dma_ctrl.scala 358:46] - io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= _T_1170 @[dma_ctrl.scala 358:40] - node _T_1171 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 359:102] - node _T_1172 = eq(_T_1171, UInt<4>("h0f")) @[dma_ctrl.scala 359:108] - node _T_1173 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 359:138] - node _T_1174 = eq(_T_1173, UInt<8>("h0f0")) @[dma_ctrl.scala 359:144] - node _T_1175 = or(_T_1172, _T_1174) @[dma_ctrl.scala 359:121] - node _T_1176 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1175) @[dma_ctrl.scala 359:84] - node _T_1177 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 359:178] - node _T_1178 = mux(_T_1176, UInt<2>("h02"), _T_1177) @[dma_ctrl.scala 359:46] - io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= _T_1178 @[dma_ctrl.scala 359:40] - dma_mem_byteen <= fifo_byteen[RdPtr] @[dma_ctrl.scala 360:20] - node _T_1179 = dshr(fifo_write, RdPtr) @[dma_ctrl.scala 361:53] - node _T_1180 = bits(_T_1179, 0, 0) @[dma_ctrl.scala 361:53] - io.lsu_dma.dma_lsc_ctl.dma_mem_write <= _T_1180 @[dma_ctrl.scala 361:40] - io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= fifo_data[RdPtr] @[dma_ctrl.scala 362:40] - node _T_1181 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 366:67] - node _T_1182 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, _T_1181) @[dma_ctrl.scala 366:65] - io.dma_pmu_dccm_read <= _T_1182 @[dma_ctrl.scala 366:26] - node _T_1183 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 367:65] - io.dma_pmu_dccm_write <= _T_1183 @[dma_ctrl.scala 367:26] - node _T_1184 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 368:66] - node _T_1185 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 368:107] - node _T_1186 = and(_T_1184, _T_1185) @[dma_ctrl.scala 368:105] - io.dma_pmu_any_read <= _T_1186 @[dma_ctrl.scala 368:26] - node _T_1187 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 369:66] - node _T_1188 = and(_T_1187, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 369:105] - io.dma_pmu_any_write <= _T_1188 @[dma_ctrl.scala 369:26] - reg _T_1189 : UInt<1>, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 374:12] - _T_1189 <= fifo_full_spec @[dma_ctrl.scala 374:12] - fifo_full <= _T_1189 @[dma_ctrl.scala 373:22] - reg _T_1190 : UInt<1>, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 378:12] - _T_1190 <= io.dbg_dma_io.dbg_dma_bubble @[dma_ctrl.scala 378:12] - dbg_dma_bubble_bus <= _T_1190 @[dma_ctrl.scala 377:22] - reg _T_1191 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 382:12] - _T_1191 <= io.dma_dbg_cmd_done @[dma_ctrl.scala 382:12] - dma_dbg_cmd_done_q <= _T_1191 @[dma_ctrl.scala 381:22] - node _T_1192 = and(bus_cmd_valid, io.dma_bus_clk_en) @[dma_ctrl.scala 387:44] - node _T_1193 = or(_T_1192, io.dbg_dma.dbg_ib.dbg_cmd_valid) @[dma_ctrl.scala 387:65] - node dma_buffer_c1_clken = or(_T_1193, io.clk_override) @[dma_ctrl.scala 387:99] - node _T_1194 = or(bus_cmd_valid, bus_rsp_valid) @[dma_ctrl.scala 388:44] - node _T_1195 = or(_T_1194, io.dbg_dma.dbg_ib.dbg_cmd_valid) @[dma_ctrl.scala 388:60] - node _T_1196 = or(_T_1195, io.dma_dbg_cmd_done) @[dma_ctrl.scala 388:94] - node _T_1197 = or(_T_1196, dma_dbg_cmd_done_q) @[dma_ctrl.scala 388:116] - node _T_1198 = orr(fifo_valid) @[dma_ctrl.scala 388:151] - node _T_1199 = or(_T_1197, _T_1198) @[dma_ctrl.scala 388:137] - node dma_free_clken = or(_T_1199, io.clk_override) @[dma_ctrl.scala 388:156] - inst dma_buffer_c1cgc of rvclkhdr_839 @[dma_ctrl.scala 390:32] + node _T_1169 = bits(dma_mem_addr_int, 31, 0) @[dma_ctrl.scala 353:196] + node _T_1170 = mux(_T_1164, _T_1168, _T_1169) @[dma_ctrl.scala 353:46] + io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= _T_1170 @[dma_ctrl.scala 353:40] + node _T_1171 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 354:102] + node _T_1172 = eq(_T_1171, UInt<4>("h0f")) @[dma_ctrl.scala 354:108] + node _T_1173 = bits(dma_mem_byteen, 7, 0) @[dma_ctrl.scala 354:138] + node _T_1174 = eq(_T_1173, UInt<8>("h0f0")) @[dma_ctrl.scala 354:144] + node _T_1175 = or(_T_1172, _T_1174) @[dma_ctrl.scala 354:121] + node _T_1176 = and(io.lsu_dma.dma_lsc_ctl.dma_mem_write, _T_1175) @[dma_ctrl.scala 354:84] + node _T_1177 = bits(dma_mem_sz_int, 2, 0) @[dma_ctrl.scala 354:178] + node _T_1178 = mux(_T_1176, UInt<2>("h02"), _T_1177) @[dma_ctrl.scala 354:46] + io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= _T_1178 @[dma_ctrl.scala 354:40] + dma_mem_byteen <= fifo_byteen[RdPtr] @[dma_ctrl.scala 355:20] + node _T_1179 = dshr(fifo_write, RdPtr) @[dma_ctrl.scala 356:53] + node _T_1180 = bits(_T_1179, 0, 0) @[dma_ctrl.scala 356:53] + io.lsu_dma.dma_lsc_ctl.dma_mem_write <= _T_1180 @[dma_ctrl.scala 356:40] + io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= fifo_data[RdPtr] @[dma_ctrl.scala 357:40] + node _T_1181 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 361:83] + node _T_1182 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, _T_1181) @[dma_ctrl.scala 361:81] + io.dec_dma.tlu_dma.dma_pmu_dccm_read <= _T_1182 @[dma_ctrl.scala 361:42] + node _T_1183 = and(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 362:81] + io.dec_dma.tlu_dma.dma_pmu_dccm_write <= _T_1183 @[dma_ctrl.scala 362:42] + node _T_1184 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 363:82] + node _T_1185 = eq(io.lsu_dma.dma_lsc_ctl.dma_mem_write, UInt<1>("h00")) @[dma_ctrl.scala 363:123] + node _T_1186 = and(_T_1184, _T_1185) @[dma_ctrl.scala 363:121] + io.dec_dma.tlu_dma.dma_pmu_any_read <= _T_1186 @[dma_ctrl.scala 363:42] + node _T_1187 = or(io.lsu_dma.dma_lsc_ctl.dma_dccm_req, io.ifu_dma.dma_mem_ctl.dma_iccm_req) @[dma_ctrl.scala 364:82] + node _T_1188 = and(_T_1187, io.lsu_dma.dma_lsc_ctl.dma_mem_write) @[dma_ctrl.scala 364:121] + io.dec_dma.tlu_dma.dma_pmu_any_write <= _T_1188 @[dma_ctrl.scala 364:42] + reg _T_1189 : UInt<1>, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 369:12] + _T_1189 <= fifo_full_spec @[dma_ctrl.scala 369:12] + fifo_full <= _T_1189 @[dma_ctrl.scala 368:22] + reg _T_1190 : UInt<1>, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 373:12] + _T_1190 <= io.dbg_dma_io.dbg_dma_bubble @[dma_ctrl.scala 373:12] + dbg_dma_bubble_bus <= _T_1190 @[dma_ctrl.scala 372:22] + reg _T_1191 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 377:12] + _T_1191 <= io.dma_dbg_cmd_done @[dma_ctrl.scala 377:12] + dma_dbg_cmd_done_q <= _T_1191 @[dma_ctrl.scala 376:22] + node _T_1192 = and(bus_cmd_valid, io.dma_bus_clk_en) @[dma_ctrl.scala 382:44] + node _T_1193 = or(_T_1192, io.dbg_dma.dbg_ib.dbg_cmd_valid) @[dma_ctrl.scala 382:65] + node dma_buffer_c1_clken = or(_T_1193, io.clk_override) @[dma_ctrl.scala 382:99] + node _T_1194 = or(bus_cmd_valid, bus_rsp_valid) @[dma_ctrl.scala 383:44] + node _T_1195 = or(_T_1194, io.dbg_dma.dbg_ib.dbg_cmd_valid) @[dma_ctrl.scala 383:60] + node _T_1196 = or(_T_1195, io.dma_dbg_cmd_done) @[dma_ctrl.scala 383:94] + node _T_1197 = or(_T_1196, dma_dbg_cmd_done_q) @[dma_ctrl.scala 383:116] + node _T_1198 = orr(fifo_valid) @[dma_ctrl.scala 383:151] + node _T_1199 = or(_T_1197, _T_1198) @[dma_ctrl.scala 383:137] + node dma_free_clken = or(_T_1199, io.clk_override) @[dma_ctrl.scala 383:156] + inst dma_buffer_c1cgc of rvclkhdr_839 @[dma_ctrl.scala 385:32] dma_buffer_c1cgc.clock <= clock dma_buffer_c1cgc.reset <= reset - dma_buffer_c1cgc.io.en <= dma_buffer_c1_clken @[dma_ctrl.scala 391:33] - dma_buffer_c1cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 392:33] - dma_buffer_c1cgc.io.clk <= clock @[dma_ctrl.scala 393:33] - dma_buffer_c1_clk <= dma_buffer_c1cgc.io.l1clk @[dma_ctrl.scala 394:33] - inst dma_free_cgc of rvclkhdr_840 @[dma_ctrl.scala 396:28] + dma_buffer_c1cgc.io.en <= dma_buffer_c1_clken @[dma_ctrl.scala 386:33] + dma_buffer_c1cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 387:33] + dma_buffer_c1cgc.io.clk <= clock @[dma_ctrl.scala 388:33] + dma_buffer_c1_clk <= dma_buffer_c1cgc.io.l1clk @[dma_ctrl.scala 389:33] + inst dma_free_cgc of rvclkhdr_840 @[dma_ctrl.scala 391:28] dma_free_cgc.clock <= clock dma_free_cgc.reset <= reset - dma_free_cgc.io.en <= dma_free_clken @[dma_ctrl.scala 397:29] - dma_free_cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 398:29] - dma_free_cgc.io.clk <= clock @[dma_ctrl.scala 399:29] - dma_free_clk <= dma_free_cgc.io.l1clk @[dma_ctrl.scala 400:29] - inst dma_bus_cgc of rvclkhdr_841 @[dma_ctrl.scala 402:27] + dma_free_cgc.io.en <= dma_free_clken @[dma_ctrl.scala 392:29] + dma_free_cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 393:29] + dma_free_cgc.io.clk <= clock @[dma_ctrl.scala 394:29] + dma_free_clk <= dma_free_cgc.io.l1clk @[dma_ctrl.scala 395:29] + inst dma_bus_cgc of rvclkhdr_841 @[dma_ctrl.scala 397:27] dma_bus_cgc.clock <= clock dma_bus_cgc.reset <= reset - dma_bus_cgc.io.en <= io.dma_bus_clk_en @[dma_ctrl.scala 403:28] - dma_bus_cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 404:28] - dma_bus_cgc.io.clk <= clock @[dma_ctrl.scala 405:28] - dma_bus_clk <= dma_bus_cgc.io.l1clk @[dma_ctrl.scala 406:28] - node wrbuf_en = and(io.dma_axi.aw.valid, io.dma_axi.aw.ready) @[dma_ctrl.scala 410:47] - node wrbuf_data_en = and(io.dma_axi.w.valid, io.dma_axi.w.ready) @[dma_ctrl.scala 411:46] - node wrbuf_cmd_sent = and(axi_mstr_prty_en, bus_cmd_write) @[dma_ctrl.scala 412:40] - node _T_1200 = bits(wrbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 413:42] - node _T_1201 = eq(wrbuf_en, UInt<1>("h00")) @[dma_ctrl.scala 413:51] - node wrbuf_rst = and(_T_1200, _T_1201) @[dma_ctrl.scala 413:49] - node _T_1202 = bits(wrbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 414:42] - node _T_1203 = eq(wrbuf_data_en, UInt<1>("h00")) @[dma_ctrl.scala 414:51] - node wrbuf_data_rst = and(_T_1202, _T_1203) @[dma_ctrl.scala 414:49] - node _T_1204 = mux(wrbuf_en, UInt<1>("h01"), wrbuf_vld) @[dma_ctrl.scala 416:63] - node _T_1205 = eq(wrbuf_rst, UInt<1>("h00")) @[dma_ctrl.scala 416:92] - node _T_1206 = and(_T_1204, _T_1205) @[dma_ctrl.scala 416:90] - reg _T_1207 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 416:59] - _T_1207 <= _T_1206 @[dma_ctrl.scala 416:59] - wrbuf_vld <= _T_1207 @[dma_ctrl.scala 416:25] - node _T_1208 = mux(wrbuf_data_en, UInt<1>("h01"), wrbuf_data_vld) @[dma_ctrl.scala 418:63] - node _T_1209 = eq(wrbuf_data_rst, UInt<1>("h00")) @[dma_ctrl.scala 418:102] - node _T_1210 = and(_T_1208, _T_1209) @[dma_ctrl.scala 418:100] - reg _T_1211 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 418:59] - _T_1211 <= _T_1210 @[dma_ctrl.scala 418:59] - wrbuf_data_vld <= _T_1211 @[dma_ctrl.scala 418:25] + dma_bus_cgc.io.en <= io.dma_bus_clk_en @[dma_ctrl.scala 398:28] + dma_bus_cgc.io.scan_mode <= io.scan_mode @[dma_ctrl.scala 399:28] + dma_bus_cgc.io.clk <= clock @[dma_ctrl.scala 400:28] + dma_bus_clk <= dma_bus_cgc.io.l1clk @[dma_ctrl.scala 401:28] + node wrbuf_en = and(io.dma_axi.aw.valid, io.dma_axi.aw.ready) @[dma_ctrl.scala 405:47] + node wrbuf_data_en = and(io.dma_axi.w.valid, io.dma_axi.w.ready) @[dma_ctrl.scala 406:46] + node wrbuf_cmd_sent = and(axi_mstr_prty_en, bus_cmd_write) @[dma_ctrl.scala 407:40] + node _T_1200 = bits(wrbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 408:42] + node _T_1201 = eq(wrbuf_en, UInt<1>("h00")) @[dma_ctrl.scala 408:51] + node wrbuf_rst = and(_T_1200, _T_1201) @[dma_ctrl.scala 408:49] + node _T_1202 = bits(wrbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 409:42] + node _T_1203 = eq(wrbuf_data_en, UInt<1>("h00")) @[dma_ctrl.scala 409:51] + node wrbuf_data_rst = and(_T_1202, _T_1203) @[dma_ctrl.scala 409:49] + node _T_1204 = mux(wrbuf_en, UInt<1>("h01"), wrbuf_vld) @[dma_ctrl.scala 411:63] + node _T_1205 = eq(wrbuf_rst, UInt<1>("h00")) @[dma_ctrl.scala 411:92] + node _T_1206 = and(_T_1204, _T_1205) @[dma_ctrl.scala 411:90] + reg _T_1207 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 411:59] + _T_1207 <= _T_1206 @[dma_ctrl.scala 411:59] + wrbuf_vld <= _T_1207 @[dma_ctrl.scala 411:25] + node _T_1208 = mux(wrbuf_data_en, UInt<1>("h01"), wrbuf_data_vld) @[dma_ctrl.scala 413:63] + node _T_1209 = eq(wrbuf_data_rst, UInt<1>("h00")) @[dma_ctrl.scala 413:102] + node _T_1210 = and(_T_1208, _T_1209) @[dma_ctrl.scala 413:100] + reg _T_1211 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 413:59] + _T_1211 <= _T_1210 @[dma_ctrl.scala 413:59] + wrbuf_data_vld <= _T_1211 @[dma_ctrl.scala 413:25] reg wrbuf_tag : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when wrbuf_en : @[Reg.scala 28:19] wrbuf_tag <= io.dma_axi.aw.bits.id @[Reg.scala 28:23] @@ -108781,7 +108780,7 @@ circuit quasar_wrapper : when wrbuf_en : @[Reg.scala 28:19] wrbuf_sz <= io.dma_axi.aw.bits.size @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_1212 = and(wrbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 428:68] + node _T_1212 = and(wrbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 423:68] inst rvclkhdr_10 of rvclkhdr_842 @[lib.scala 352:23] rvclkhdr_10.clock <= clock rvclkhdr_10.reset <= reset @@ -108790,7 +108789,7 @@ circuit quasar_wrapper : rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg wrbuf_addr : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] wrbuf_addr <= io.dma_axi.aw.bits.addr @[lib.scala 358:16] - node _T_1213 = and(wrbuf_data_en, io.dma_bus_clk_en) @[dma_ctrl.scala 430:72] + node _T_1213 = and(wrbuf_data_en, io.dma_bus_clk_en) @[dma_ctrl.scala 425:72] inst rvclkhdr_11 of rvclkhdr_843 @[lib.scala 352:23] rvclkhdr_11.clock <= clock rvclkhdr_11.reset <= reset @@ -108803,18 +108802,18 @@ circuit quasar_wrapper : when wrbuf_data_en : @[Reg.scala 28:19] wrbuf_byteen <= io.dma_axi.w.bits.strb @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node rdbuf_en = and(io.dma_axi.ar.valid, io.dma_axi.ar.ready) @[dma_ctrl.scala 438:59] - node _T_1214 = eq(bus_cmd_write, UInt<1>("h00")) @[dma_ctrl.scala 439:44] - node rdbuf_cmd_sent = and(axi_mstr_prty_en, _T_1214) @[dma_ctrl.scala 439:42] - node _T_1215 = bits(rdbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 440:54] - node _T_1216 = eq(rdbuf_en, UInt<1>("h00")) @[dma_ctrl.scala 440:63] - node rdbuf_rst = and(_T_1215, _T_1216) @[dma_ctrl.scala 440:61] - node _T_1217 = mux(rdbuf_en, UInt<1>("h01"), rdbuf_vld) @[dma_ctrl.scala 442:51] - node _T_1218 = eq(rdbuf_rst, UInt<1>("h00")) @[dma_ctrl.scala 442:80] - node _T_1219 = and(_T_1217, _T_1218) @[dma_ctrl.scala 442:78] - reg _T_1220 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 442:47] - _T_1220 <= _T_1219 @[dma_ctrl.scala 442:47] - rdbuf_vld <= _T_1220 @[dma_ctrl.scala 442:13] + node rdbuf_en = and(io.dma_axi.ar.valid, io.dma_axi.ar.ready) @[dma_ctrl.scala 433:59] + node _T_1214 = eq(bus_cmd_write, UInt<1>("h00")) @[dma_ctrl.scala 434:44] + node rdbuf_cmd_sent = and(axi_mstr_prty_en, _T_1214) @[dma_ctrl.scala 434:42] + node _T_1215 = bits(rdbuf_cmd_sent, 0, 0) @[dma_ctrl.scala 435:54] + node _T_1216 = eq(rdbuf_en, UInt<1>("h00")) @[dma_ctrl.scala 435:63] + node rdbuf_rst = and(_T_1215, _T_1216) @[dma_ctrl.scala 435:61] + node _T_1217 = mux(rdbuf_en, UInt<1>("h01"), rdbuf_vld) @[dma_ctrl.scala 437:51] + node _T_1218 = eq(rdbuf_rst, UInt<1>("h00")) @[dma_ctrl.scala 437:80] + node _T_1219 = and(_T_1217, _T_1218) @[dma_ctrl.scala 437:78] + reg _T_1220 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[dma_ctrl.scala 437:47] + _T_1220 <= _T_1219 @[dma_ctrl.scala 437:47] + rdbuf_vld <= _T_1220 @[dma_ctrl.scala 437:13] reg rdbuf_tag : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when rdbuf_en : @[Reg.scala 28:19] rdbuf_tag <= io.dma_axi.ar.bits.id @[Reg.scala 28:23] @@ -108823,7 +108822,7 @@ circuit quasar_wrapper : when rdbuf_en : @[Reg.scala 28:19] rdbuf_sz <= io.dma_axi.ar.bits.size @[Reg.scala 28:23] skip @[Reg.scala 28:19] - node _T_1221 = and(rdbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 452:61] + node _T_1221 = and(rdbuf_en, io.dma_bus_clk_en) @[dma_ctrl.scala 447:61] inst rvclkhdr_12 of rvclkhdr_844 @[lib.scala 352:23] rvclkhdr_12.clock <= clock rvclkhdr_12.reset <= reset @@ -108832,93 +108831,93 @@ circuit quasar_wrapper : rvclkhdr_12.io.scan_mode <= io.scan_mode @[lib.scala 356:24] reg rdbuf_addr : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 358:16] rdbuf_addr <= io.dma_axi.ar.bits.addr @[lib.scala 358:16] - node _T_1222 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 454:44] - node _T_1223 = and(wrbuf_vld, _T_1222) @[dma_ctrl.scala 454:42] - node _T_1224 = not(_T_1223) @[dma_ctrl.scala 454:30] - io.dma_axi.aw.ready <= _T_1224 @[dma_ctrl.scala 454:27] - node _T_1225 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 455:49] - node _T_1226 = and(wrbuf_data_vld, _T_1225) @[dma_ctrl.scala 455:47] - node _T_1227 = not(_T_1226) @[dma_ctrl.scala 455:30] - io.dma_axi.w.ready <= _T_1227 @[dma_ctrl.scala 455:27] - node _T_1228 = eq(rdbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 456:44] - node _T_1229 = and(rdbuf_vld, _T_1228) @[dma_ctrl.scala 456:42] - node _T_1230 = not(_T_1229) @[dma_ctrl.scala 456:30] - io.dma_axi.ar.ready <= _T_1230 @[dma_ctrl.scala 456:27] - node _T_1231 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 460:51] - node _T_1232 = or(_T_1231, rdbuf_vld) @[dma_ctrl.scala 460:69] - bus_cmd_valid <= _T_1232 @[dma_ctrl.scala 460:37] - node _T_1233 = and(bus_cmd_valid, dma_fifo_ready) @[dma_ctrl.scala 461:54] - axi_mstr_prty_en <= _T_1233 @[dma_ctrl.scala 461:37] - bus_cmd_write <= axi_mstr_sel @[dma_ctrl.scala 462:37] - bus_cmd_posted_write <= UInt<1>("h00") @[dma_ctrl.scala 463:25] - node _T_1234 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 464:57] - node _T_1235 = mux(_T_1234, wrbuf_addr, rdbuf_addr) @[dma_ctrl.scala 464:43] - bus_cmd_addr <= _T_1235 @[dma_ctrl.scala 464:37] - node _T_1236 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 465:59] - node _T_1237 = mux(_T_1236, wrbuf_sz, rdbuf_sz) @[dma_ctrl.scala 465:45] - bus_cmd_sz <= _T_1237 @[dma_ctrl.scala 465:39] - bus_cmd_wdata <= wrbuf_data @[dma_ctrl.scala 466:37] - bus_cmd_byteen <= wrbuf_byteen @[dma_ctrl.scala 467:37] - node _T_1238 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 468:57] - node _T_1239 = mux(_T_1238, wrbuf_tag, rdbuf_tag) @[dma_ctrl.scala 468:43] - bus_cmd_tag <= _T_1239 @[dma_ctrl.scala 468:37] - bus_cmd_mid <= UInt<1>("h00") @[dma_ctrl.scala 469:37] - bus_cmd_prty <= UInt<1>("h00") @[dma_ctrl.scala 470:37] - node _T_1240 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 474:43] - node _T_1241 = and(_T_1240, rdbuf_vld) @[dma_ctrl.scala 474:60] - node _T_1242 = eq(_T_1241, UInt<1>("h01")) @[dma_ctrl.scala 474:73] - node _T_1243 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 474:111] - node _T_1244 = mux(_T_1242, axi_mstr_priority, _T_1243) @[dma_ctrl.scala 474:31] - axi_mstr_sel <= _T_1244 @[dma_ctrl.scala 474:25] - node axi_mstr_prty_in = not(axi_mstr_priority) @[dma_ctrl.scala 475:27] - node _T_1245 = bits(axi_mstr_prty_en, 0, 0) @[dma_ctrl.scala 479:55] + node _T_1222 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 449:44] + node _T_1223 = and(wrbuf_vld, _T_1222) @[dma_ctrl.scala 449:42] + node _T_1224 = not(_T_1223) @[dma_ctrl.scala 449:30] + io.dma_axi.aw.ready <= _T_1224 @[dma_ctrl.scala 449:27] + node _T_1225 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 450:49] + node _T_1226 = and(wrbuf_data_vld, _T_1225) @[dma_ctrl.scala 450:47] + node _T_1227 = not(_T_1226) @[dma_ctrl.scala 450:30] + io.dma_axi.w.ready <= _T_1227 @[dma_ctrl.scala 450:27] + node _T_1228 = eq(rdbuf_cmd_sent, UInt<1>("h00")) @[dma_ctrl.scala 451:44] + node _T_1229 = and(rdbuf_vld, _T_1228) @[dma_ctrl.scala 451:42] + node _T_1230 = not(_T_1229) @[dma_ctrl.scala 451:30] + io.dma_axi.ar.ready <= _T_1230 @[dma_ctrl.scala 451:27] + node _T_1231 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 455:51] + node _T_1232 = or(_T_1231, rdbuf_vld) @[dma_ctrl.scala 455:69] + bus_cmd_valid <= _T_1232 @[dma_ctrl.scala 455:37] + node _T_1233 = and(bus_cmd_valid, dma_fifo_ready) @[dma_ctrl.scala 456:54] + axi_mstr_prty_en <= _T_1233 @[dma_ctrl.scala 456:37] + bus_cmd_write <= axi_mstr_sel @[dma_ctrl.scala 457:37] + bus_cmd_posted_write <= UInt<1>("h00") @[dma_ctrl.scala 458:25] + node _T_1234 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 459:57] + node _T_1235 = mux(_T_1234, wrbuf_addr, rdbuf_addr) @[dma_ctrl.scala 459:43] + bus_cmd_addr <= _T_1235 @[dma_ctrl.scala 459:37] + node _T_1236 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 460:59] + node _T_1237 = mux(_T_1236, wrbuf_sz, rdbuf_sz) @[dma_ctrl.scala 460:45] + bus_cmd_sz <= _T_1237 @[dma_ctrl.scala 460:39] + bus_cmd_wdata <= wrbuf_data @[dma_ctrl.scala 461:37] + bus_cmd_byteen <= wrbuf_byteen @[dma_ctrl.scala 462:37] + node _T_1238 = bits(axi_mstr_sel, 0, 0) @[dma_ctrl.scala 463:57] + node _T_1239 = mux(_T_1238, wrbuf_tag, rdbuf_tag) @[dma_ctrl.scala 463:43] + bus_cmd_tag <= _T_1239 @[dma_ctrl.scala 463:37] + bus_cmd_mid <= UInt<1>("h00") @[dma_ctrl.scala 464:37] + bus_cmd_prty <= UInt<1>("h00") @[dma_ctrl.scala 465:37] + node _T_1240 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 469:43] + node _T_1241 = and(_T_1240, rdbuf_vld) @[dma_ctrl.scala 469:60] + node _T_1242 = eq(_T_1241, UInt<1>("h01")) @[dma_ctrl.scala 469:73] + node _T_1243 = and(wrbuf_vld, wrbuf_data_vld) @[dma_ctrl.scala 469:111] + node _T_1244 = mux(_T_1242, axi_mstr_priority, _T_1243) @[dma_ctrl.scala 469:31] + axi_mstr_sel <= _T_1244 @[dma_ctrl.scala 469:25] + node axi_mstr_prty_in = not(axi_mstr_priority) @[dma_ctrl.scala 470:27] + node _T_1245 = bits(axi_mstr_prty_en, 0, 0) @[dma_ctrl.scala 474:55] reg _T_1246 : UInt, dma_bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_1245 : @[Reg.scala 28:19] _T_1246 <= axi_mstr_prty_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - axi_mstr_priority <= _T_1246 @[dma_ctrl.scala 478:27] - node _T_1247 = dshr(fifo_valid, RspPtr) @[dma_ctrl.scala 482:39] - node _T_1248 = bits(_T_1247, 0, 0) @[dma_ctrl.scala 482:39] - node _T_1249 = dshr(fifo_dbg, RspPtr) @[dma_ctrl.scala 482:59] - node _T_1250 = bits(_T_1249, 0, 0) @[dma_ctrl.scala 482:59] - node _T_1251 = eq(_T_1250, UInt<1>("h00")) @[dma_ctrl.scala 482:50] - node _T_1252 = and(_T_1248, _T_1251) @[dma_ctrl.scala 482:48] - node _T_1253 = dshr(fifo_done_bus, RspPtr) @[dma_ctrl.scala 482:83] - node _T_1254 = bits(_T_1253, 0, 0) @[dma_ctrl.scala 482:83] - node axi_rsp_valid = and(_T_1252, _T_1254) @[dma_ctrl.scala 482:68] - node _T_1255 = dshr(fifo_write, RspPtr) @[dma_ctrl.scala 484:39] - node axi_rsp_write = bits(_T_1255, 0, 0) @[dma_ctrl.scala 484:39] - node _T_1256 = bits(fifo_error[RspPtr], 0, 0) @[dma_ctrl.scala 485:51] - node _T_1257 = bits(fifo_error[RspPtr], 1, 1) @[dma_ctrl.scala 485:83] - node _T_1258 = mux(_T_1257, UInt<2>("h03"), UInt<1>("h00")) @[dma_ctrl.scala 485:64] - node axi_rsp_error = mux(_T_1256, UInt<2>("h02"), _T_1258) @[dma_ctrl.scala 485:32] - node _T_1259 = and(axi_rsp_valid, axi_rsp_write) @[dma_ctrl.scala 491:44] - io.dma_axi.b.valid <= _T_1259 @[dma_ctrl.scala 491:27] - node _T_1260 = bits(axi_rsp_error, 1, 0) @[dma_ctrl.scala 492:57] - io.dma_axi.b.bits.resp <= _T_1260 @[dma_ctrl.scala 492:41] - io.dma_axi.b.bits.id <= fifo_tag[RspPtr] @[dma_ctrl.scala 493:33] - node _T_1261 = eq(axi_rsp_write, UInt<1>("h00")) @[dma_ctrl.scala 495:46] - node _T_1262 = and(axi_rsp_valid, _T_1261) @[dma_ctrl.scala 495:44] - io.dma_axi.r.valid <= _T_1262 @[dma_ctrl.scala 495:27] - io.dma_axi.r.bits.resp <= axi_rsp_error @[dma_ctrl.scala 496:41] - node _T_1263 = bits(fifo_data[RspPtr], 63, 0) @[dma_ctrl.scala 497:59] - io.dma_axi.r.bits.data <= _T_1263 @[dma_ctrl.scala 497:43] - io.dma_axi.r.bits.last <= UInt<1>("h01") @[dma_ctrl.scala 498:41] - io.dma_axi.r.bits.id <= fifo_tag[RspPtr] @[dma_ctrl.scala 499:37] - bus_posted_write_done <= UInt<1>("h00") @[dma_ctrl.scala 501:25] - node _T_1264 = or(io.dma_axi.b.valid, io.dma_axi.r.valid) @[dma_ctrl.scala 502:60] - bus_rsp_valid <= _T_1264 @[dma_ctrl.scala 502:37] - node _T_1265 = and(io.dma_axi.b.valid, io.dma_axi.b.ready) @[dma_ctrl.scala 503:61] - node _T_1266 = and(io.dma_axi.r.valid, io.dma_axi.r.ready) @[dma_ctrl.scala 503:105] - node _T_1267 = or(_T_1265, _T_1266) @[dma_ctrl.scala 503:83] - bus_rsp_sent <= _T_1267 @[dma_ctrl.scala 503:37] - io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[dma_ctrl.scala 504:40] - io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[dma_ctrl.scala 505:41] - io.ifu_dma.dma_mem_ctl.dma_mem_sz <= io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[dma_ctrl.scala 506:37] - io.ifu_dma.dma_mem_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[dma_ctrl.scala 507:39] - io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[dma_ctrl.scala 508:40] - io.ifu_dma.dma_mem_ctl.dma_mem_write <= io.lsu_dma.dma_lsc_ctl.dma_mem_write @[dma_ctrl.scala 509:40] - io.ifu_dma.dma_mem_ctl.dma_mem_tag <= io.lsu_dma.dma_mem_tag @[dma_ctrl.scala 510:38] + axi_mstr_priority <= _T_1246 @[dma_ctrl.scala 473:27] + node _T_1247 = dshr(fifo_valid, RspPtr) @[dma_ctrl.scala 477:39] + node _T_1248 = bits(_T_1247, 0, 0) @[dma_ctrl.scala 477:39] + node _T_1249 = dshr(fifo_dbg, RspPtr) @[dma_ctrl.scala 477:59] + node _T_1250 = bits(_T_1249, 0, 0) @[dma_ctrl.scala 477:59] + node _T_1251 = eq(_T_1250, UInt<1>("h00")) @[dma_ctrl.scala 477:50] + node _T_1252 = and(_T_1248, _T_1251) @[dma_ctrl.scala 477:48] + node _T_1253 = dshr(fifo_done_bus, RspPtr) @[dma_ctrl.scala 477:83] + node _T_1254 = bits(_T_1253, 0, 0) @[dma_ctrl.scala 477:83] + node axi_rsp_valid = and(_T_1252, _T_1254) @[dma_ctrl.scala 477:68] + node _T_1255 = dshr(fifo_write, RspPtr) @[dma_ctrl.scala 479:39] + node axi_rsp_write = bits(_T_1255, 0, 0) @[dma_ctrl.scala 479:39] + node _T_1256 = bits(fifo_error[RspPtr], 0, 0) @[dma_ctrl.scala 480:51] + node _T_1257 = bits(fifo_error[RspPtr], 1, 1) @[dma_ctrl.scala 480:83] + node _T_1258 = mux(_T_1257, UInt<2>("h03"), UInt<1>("h00")) @[dma_ctrl.scala 480:64] + node axi_rsp_error = mux(_T_1256, UInt<2>("h02"), _T_1258) @[dma_ctrl.scala 480:32] + node _T_1259 = and(axi_rsp_valid, axi_rsp_write) @[dma_ctrl.scala 486:44] + io.dma_axi.b.valid <= _T_1259 @[dma_ctrl.scala 486:27] + node _T_1260 = bits(axi_rsp_error, 1, 0) @[dma_ctrl.scala 487:57] + io.dma_axi.b.bits.resp <= _T_1260 @[dma_ctrl.scala 487:41] + io.dma_axi.b.bits.id <= fifo_tag[RspPtr] @[dma_ctrl.scala 488:33] + node _T_1261 = eq(axi_rsp_write, UInt<1>("h00")) @[dma_ctrl.scala 490:46] + node _T_1262 = and(axi_rsp_valid, _T_1261) @[dma_ctrl.scala 490:44] + io.dma_axi.r.valid <= _T_1262 @[dma_ctrl.scala 490:27] + io.dma_axi.r.bits.resp <= axi_rsp_error @[dma_ctrl.scala 491:41] + node _T_1263 = bits(fifo_data[RspPtr], 63, 0) @[dma_ctrl.scala 492:59] + io.dma_axi.r.bits.data <= _T_1263 @[dma_ctrl.scala 492:43] + io.dma_axi.r.bits.last <= UInt<1>("h01") @[dma_ctrl.scala 493:41] + io.dma_axi.r.bits.id <= fifo_tag[RspPtr] @[dma_ctrl.scala 494:37] + bus_posted_write_done <= UInt<1>("h00") @[dma_ctrl.scala 496:25] + node _T_1264 = or(io.dma_axi.b.valid, io.dma_axi.r.valid) @[dma_ctrl.scala 497:60] + bus_rsp_valid <= _T_1264 @[dma_ctrl.scala 497:37] + node _T_1265 = and(io.dma_axi.b.valid, io.dma_axi.b.ready) @[dma_ctrl.scala 498:61] + node _T_1266 = and(io.dma_axi.r.valid, io.dma_axi.r.ready) @[dma_ctrl.scala 498:105] + node _T_1267 = or(_T_1265, _T_1266) @[dma_ctrl.scala 498:83] + bus_rsp_sent <= _T_1267 @[dma_ctrl.scala 498:37] + io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[dma_ctrl.scala 499:40] + io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[dma_ctrl.scala 500:41] + io.ifu_dma.dma_mem_ctl.dma_mem_sz <= io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[dma_ctrl.scala 501:37] + io.ifu_dma.dma_mem_ctl.dma_mem_addr <= io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[dma_ctrl.scala 502:39] + io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[dma_ctrl.scala 503:40] + io.ifu_dma.dma_mem_ctl.dma_mem_write <= io.lsu_dma.dma_lsc_ctl.dma_mem_write @[dma_ctrl.scala 504:40] + io.ifu_dma.dma_mem_ctl.dma_mem_tag <= io.lsu_dma.dma_mem_tag @[dma_ctrl.scala 505:38] extmodule gated_latch_845 : output Q : Clock @@ -113762,909 +113761,908 @@ circuit quasar_wrapper : module quasar : input clock : Clock input reset : AsyncReset - output io : {lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, core_rst_l : AsyncReset, trace_rv_i_insn_ip : UInt<32>, trace_rv_i_address_ip : UInt<32>, trace_rv_i_valid_ip : UInt<2>, trace_rv_i_exception_ip : UInt<2>, trace_rv_i_ecause_ip : UInt<5>, trace_rv_i_interrupt_ip : UInt<2>, trace_rv_i_tval_ip : UInt<32>, dccm_clk_override : UInt<1>, icm_clk_override : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, ic : {rw_addr : UInt<31>, tag_valid : UInt<2>, wr_en : UInt<2>, rd_en : UInt<1>, wr_data : UInt<71>[2], debug_wr_data : UInt<71>, debug_addr : UInt<10>, flip rd_data : UInt<64>, flip debug_rd_data : UInt<71>, flip tag_debug_rd_data : UInt<26>, flip eccerr : UInt<2>, flip parerr : UInt<2>, flip rd_hit : UInt<2>, flip tag_perr : UInt<1>, debug_rd_en : UInt<1>, debug_wr_en : UInt<1>, debug_tag_array : UInt<1>, debug_way : UInt<2>, premux_data : UInt<64>, sel_premux_data : UInt<1>}, iccm : {rw_addr : UInt<15>, buf_correct_ecc : UInt<1>, correction_state : UInt<1>, wren : UInt<1>, rden : UInt<1>, wr_size : UInt<3>, wr_data : UInt<78>, flip rd_data : UInt<64>, flip rd_data_ecc : UInt<78>}, haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>, lsu_haddr : UInt<32>, lsu_hburst : UInt<3>, lsu_hmastlock : UInt<1>, lsu_hprot : UInt<4>, lsu_hsize : UInt<3>, lsu_htrans : UInt<2>, lsu_hwrite : UInt<1>, lsu_hwdata : UInt<64>, flip lsu_hrdata : UInt<64>, flip lsu_hready : UInt<1>, flip lsu_hresp : UInt<1>, sb_haddr : UInt<32>, sb_hburst : UInt<3>, sb_hmastlock : UInt<1>, sb_hprot : UInt<4>, sb_hsize : UInt<3>, sb_htrans : UInt<2>, sb_hwrite : UInt<1>, sb_hwdata : UInt<64>, flip sb_hrdata : UInt<64>, flip sb_hready : UInt<1>, flip sb_hresp : UInt<1>, flip dma_hsel : UInt<1>, flip dma_haddr : UInt<32>, flip dma_hburst : UInt<3>, flip dma_hmastlock : UInt<1>, flip dma_hprot : UInt<4>, flip dma_hsize : UInt<3>, flip dma_htrans : UInt<2>, flip dma_hwrite : UInt<1>, flip dma_hwdata : UInt<64>, flip dma_hreadyin : UInt<1>, dma_hrdata : UInt<64>, dma_hreadyout : UInt<1>, dma_hresp : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, flip dmi_hard_reset : UInt<1>, flip extintsrc_req : UInt<31>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip scan_mode : UInt<1>} + output io : {lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, core_rst_l : AsyncReset, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dccm_clk_override : UInt<1>, icm_clk_override : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, ic : {rw_addr : UInt<31>, tag_valid : UInt<2>, wr_en : UInt<2>, rd_en : UInt<1>, wr_data : UInt<71>[2], debug_wr_data : UInt<71>, debug_addr : UInt<10>, flip rd_data : UInt<64>, flip debug_rd_data : UInt<71>, flip tag_debug_rd_data : UInt<26>, flip eccerr : UInt<2>, flip parerr : UInt<2>, flip rd_hit : UInt<2>, flip tag_perr : UInt<1>, debug_rd_en : UInt<1>, debug_wr_en : UInt<1>, debug_tag_array : UInt<1>, debug_way : UInt<2>, premux_data : UInt<64>, sel_premux_data : UInt<1>}, iccm : {rw_addr : UInt<15>, buf_correct_ecc : UInt<1>, correction_state : UInt<1>, wren : UInt<1>, rden : UInt<1>, wr_size : UInt<3>, wr_data : UInt<78>, flip rd_data : UInt<64>, flip rd_data_ecc : UInt<78>}, haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>, lsu_haddr : UInt<32>, lsu_hburst : UInt<3>, lsu_hmastlock : UInt<1>, lsu_hprot : UInt<4>, lsu_hsize : UInt<3>, lsu_htrans : UInt<2>, lsu_hwrite : UInt<1>, lsu_hwdata : UInt<64>, flip lsu_hrdata : UInt<64>, flip lsu_hready : UInt<1>, flip lsu_hresp : UInt<1>, sb_haddr : UInt<32>, sb_hburst : UInt<3>, sb_hmastlock : UInt<1>, sb_hprot : UInt<4>, sb_hsize : UInt<3>, sb_htrans : UInt<2>, sb_hwrite : UInt<1>, sb_hwdata : UInt<64>, flip sb_hrdata : UInt<64>, flip sb_hready : UInt<1>, flip sb_hresp : UInt<1>, flip dma_hsel : UInt<1>, flip dma_haddr : UInt<32>, flip dma_hburst : UInt<3>, flip dma_hmastlock : UInt<1>, flip dma_hprot : UInt<4>, flip dma_hsize : UInt<3>, flip dma_htrans : UInt<2>, flip dma_hwrite : UInt<1>, flip dma_hwdata : UInt<64>, flip dma_hreadyin : UInt<1>, dma_hrdata : UInt<64>, dma_hreadyout : UInt<1>, dma_hresp : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, flip dmi_hard_reset : UInt<1>, flip extintsrc_req : UInt<31>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip scan_mode : UInt<1>} - inst ifu of ifu @[quasar.scala 122:19] + inst ifu of ifu @[quasar.scala 116:19] ifu.clock <= clock ifu.reset <= reset - inst dec of dec @[quasar.scala 123:19] + inst dec of dec @[quasar.scala 117:19] dec.clock <= clock dec.reset <= reset - inst dbg of dbg @[quasar.scala 124:19] + inst dbg of dbg @[quasar.scala 118:19] dbg.clock <= clock dbg.reset <= reset - inst exu of exu @[quasar.scala 125:19] + inst exu of exu @[quasar.scala 119:19] exu.clock <= clock exu.reset <= reset - inst lsu of lsu @[quasar.scala 126:19] + inst lsu of lsu @[quasar.scala 120:19] lsu.clock <= clock lsu.reset <= reset - inst pic_ctrl_inst of pic_ctrl @[quasar.scala 127:29] + inst pic_ctrl_inst of pic_ctrl @[quasar.scala 121:29] pic_ctrl_inst.clock <= clock pic_ctrl_inst.reset <= reset - inst dma_ctrl of dma_ctrl @[quasar.scala 128:24] + inst dma_ctrl of dma_ctrl @[quasar.scala 122:24] dma_ctrl.clock <= clock dma_ctrl.reset <= reset - node _T = asUInt(reset) @[quasar.scala 130:33] - node _T_1 = bits(dbg.io.dbg_core_rst_l, 0, 0) @[quasar.scala 130:67] - node _T_2 = or(_T_1, io.scan_mode) @[quasar.scala 130:70] - node _T_3 = and(_T, _T_2) @[quasar.scala 130:36] - node _T_4 = asAsyncReset(_T_3) @[quasar.scala 130:99] - io.core_rst_l <= _T_4 @[quasar.scala 130:17] - node _T_5 = eq(dec.io.dec_pause_state_cg, UInt<1>("h00")) @[quasar.scala 131:23] - node _T_6 = or(_T_5, dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[quasar.scala 131:50] - node active_state = or(_T_6, dec.io.dec_tlu_misc_clk_override) @[quasar.scala 131:98] + node _T = asUInt(reset) @[quasar.scala 124:33] + node _T_1 = bits(dbg.io.dbg_core_rst_l, 0, 0) @[quasar.scala 124:67] + node _T_2 = or(_T_1, io.scan_mode) @[quasar.scala 124:70] + node _T_3 = and(_T, _T_2) @[quasar.scala 124:36] + node _T_4 = asAsyncReset(_T_3) @[quasar.scala 124:99] + io.core_rst_l <= _T_4 @[quasar.scala 124:17] + node _T_5 = eq(dec.io.dec_pause_state_cg, UInt<1>("h00")) @[quasar.scala 125:23] + node _T_6 = or(_T_5, dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) @[quasar.scala 125:50] + node active_state = or(_T_6, dec.io.dec_tlu_misc_clk_override) @[quasar.scala 125:98] inst rvclkhdr of rvclkhdr_845 @[lib.scala 327:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[lib.scala 328:17] rvclkhdr.io.en <= UInt<1>("h01") @[lib.scala 329:16] rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node _T_7 = bits(active_state, 0, 0) @[quasar.scala 133:49] + node _T_7 = bits(active_state, 0, 0) @[quasar.scala 127:49] inst rvclkhdr_1 of rvclkhdr_846 @[lib.scala 327:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[lib.scala 328:17] rvclkhdr_1.io.en <= _T_7 @[lib.scala 329:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 330:23] - node core_dbg_cmd_done = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 134:56] - node core_dbg_cmd_fail = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 135:56] - node core_dbg_rddata = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 136:28] - ifu.io.ifu_dec.dec_bp.dec_tlu_bpred_disable <= dec.io.ifu_dec.dec_bp.dec_tlu_bpred_disable @[quasar.scala 139:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb <= dec.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb @[quasar.scala 139:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_flush_lower_wb <= dec.io.ifu_dec.dec_bp.dec_tlu_flush_lower_wb @[quasar.scala 139:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle @[quasar.scala 139:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way @[quasar.scala 139:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[quasar.scala 139:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error @[quasar.scala 139:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist @[quasar.scala 139:18] - ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid @[quasar.scala 139:18] - dec.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall <= ifu.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall @[quasar.scala 139:18] - ifu.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 139:18] - ifu.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb <= dec.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb @[quasar.scala 139:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle @[quasar.scala 139:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[quasar.scala 139:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data @[quasar.scala 139:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[quasar.scala 139:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start @[quasar.scala 139:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn @[quasar.scala 139:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy @[quasar.scala 139:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error @[quasar.scala 139:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit @[quasar.scala 139:18] - dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss @[quasar.scala 139:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 139:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 139:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 139:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 139:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 139:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb @[quasar.scala 139:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 139:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt @[quasar.scala 139:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb @[quasar.scala 139:18] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_lower_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_lower_wb @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned <= ifu.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf @[quasar.scala 139:18] - dec.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst <= ifu.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst @[quasar.scala 139:18] - ifu.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d <= dec.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d @[quasar.scala 139:18] - ifu.reset <= io.core_rst_l @[quasar.scala 141:13] - ifu.io.scan_mode <= io.scan_mode @[quasar.scala 142:20] - ifu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 143:19] - ifu.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 144:21] - ifu.io.exu_flush_final <= dec.io.exu_flush_final @[quasar.scala 146:26] - ifu.io.exu_flush_path_final <= exu.io.exu_flush_path_final @[quasar.scala 147:31] - ifu.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 149:25] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_tag <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_tag @[quasar.scala 150:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_wdata @[quasar.scala 150:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_write <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_write @[quasar.scala 150:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_sz <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_sz @[quasar.scala 150:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_mem_addr <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_addr @[quasar.scala 150:18] - ifu.io.ifu_dma.dma_mem_ctl.dma_iccm_req <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_iccm_req @[quasar.scala 150:18] - ifu.io.ifu_dma.dma_ifc.dma_iccm_stall_any <= dma_ctrl.io.ifu_dma.dma_ifc.dma_iccm_stall_any @[quasar.scala 150:18] - io.ic.sel_premux_data <= ifu.io.ic.sel_premux_data @[quasar.scala 151:13] - io.ic.premux_data <= ifu.io.ic.premux_data @[quasar.scala 151:13] - io.ic.debug_way <= ifu.io.ic.debug_way @[quasar.scala 151:13] - io.ic.debug_tag_array <= ifu.io.ic.debug_tag_array @[quasar.scala 151:13] - io.ic.debug_wr_en <= ifu.io.ic.debug_wr_en @[quasar.scala 151:13] - io.ic.debug_rd_en <= ifu.io.ic.debug_rd_en @[quasar.scala 151:13] - ifu.io.ic.tag_perr <= io.ic.tag_perr @[quasar.scala 151:13] - ifu.io.ic.rd_hit <= io.ic.rd_hit @[quasar.scala 151:13] - ifu.io.ic.parerr <= io.ic.parerr @[quasar.scala 151:13] - ifu.io.ic.eccerr <= io.ic.eccerr @[quasar.scala 151:13] - ifu.io.ic.tag_debug_rd_data <= io.ic.tag_debug_rd_data @[quasar.scala 151:13] - ifu.io.ic.debug_rd_data <= io.ic.debug_rd_data @[quasar.scala 151:13] - ifu.io.ic.rd_data <= io.ic.rd_data @[quasar.scala 151:13] - io.ic.debug_addr <= ifu.io.ic.debug_addr @[quasar.scala 151:13] - io.ic.debug_wr_data <= ifu.io.ic.debug_wr_data @[quasar.scala 151:13] - io.ic.wr_data[0] <= ifu.io.ic.wr_data[0] @[quasar.scala 151:13] - io.ic.wr_data[1] <= ifu.io.ic.wr_data[1] @[quasar.scala 151:13] - io.ic.rd_en <= ifu.io.ic.rd_en @[quasar.scala 151:13] - io.ic.wr_en <= ifu.io.ic.wr_en @[quasar.scala 151:13] - io.ic.tag_valid <= ifu.io.ic.tag_valid @[quasar.scala 151:13] - io.ic.rw_addr <= ifu.io.ic.rw_addr @[quasar.scala 151:13] - ifu.io.iccm.rd_data_ecc <= io.iccm.rd_data_ecc @[quasar.scala 152:15] - ifu.io.iccm.rd_data <= io.iccm.rd_data @[quasar.scala 152:15] - io.iccm.wr_data <= ifu.io.iccm.wr_data @[quasar.scala 152:15] - io.iccm.wr_size <= ifu.io.iccm.wr_size @[quasar.scala 152:15] - io.iccm.rden <= ifu.io.iccm.rden @[quasar.scala 152:15] - io.iccm.wren <= ifu.io.iccm.wren @[quasar.scala 152:15] - io.iccm.correction_state <= ifu.io.iccm.correction_state @[quasar.scala 152:15] - io.iccm.buf_correct_ecc <= ifu.io.iccm.buf_correct_ecc @[quasar.scala 152:15] - io.iccm.rw_addr <= ifu.io.iccm.rw_addr @[quasar.scala 152:15] - ifu.io.exu_ifu.exu_bp.exu_mp_btag <= exu.io.exu_bp.exu_mp_btag @[quasar.scala 153:25] - ifu.io.exu_ifu.exu_bp.exu_mp_index <= exu.io.exu_bp.exu_mp_index @[quasar.scala 153:25] - ifu.io.exu_ifu.exu_bp.exu_mp_fghr <= exu.io.exu_bp.exu_mp_fghr @[quasar.scala 153:25] - ifu.io.exu_ifu.exu_bp.exu_mp_eghr <= exu.io.exu_bp.exu_mp_eghr @[quasar.scala 153:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.way <= exu.io.exu_bp.exu_mp_pkt.bits.way @[quasar.scala 153:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pja <= exu.io.exu_bp.exu_mp_pkt.bits.pja @[quasar.scala 153:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pret <= exu.io.exu_bp.exu_mp_pkt.bits.pret @[quasar.scala 153:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pcall <= exu.io.exu_bp.exu_mp_pkt.bits.pcall @[quasar.scala 153:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.prett <= exu.io.exu_bp.exu_mp_pkt.bits.prett @[quasar.scala 153:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_start_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_start_error @[quasar.scala 153:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_error @[quasar.scala 153:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.toffset <= exu.io.exu_bp.exu_mp_pkt.bits.toffset @[quasar.scala 153:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.hist <= exu.io.exu_bp.exu_mp_pkt.bits.hist @[quasar.scala 153:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pc4 <= exu.io.exu_bp.exu_mp_pkt.bits.pc4 @[quasar.scala 153:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.boffset <= exu.io.exu_bp.exu_mp_pkt.bits.boffset @[quasar.scala 153:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.ataken <= exu.io.exu_bp.exu_mp_pkt.bits.ataken @[quasar.scala 153:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.misp <= exu.io.exu_bp.exu_mp_pkt.bits.misp @[quasar.scala 153:25] - ifu.io.exu_ifu.exu_bp.exu_mp_pkt.valid <= exu.io.exu_bp.exu_mp_pkt.valid @[quasar.scala 153:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 153:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 153:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.exu_bp.exu_i0_br_index_r @[quasar.scala 153:25] - ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 154:42] - ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 155:43] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_lower_wb <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 156:54] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 157:51] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 157:51] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 157:51] - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 157:51] - dec.reset <= io.core_rst_l @[quasar.scala 160:13] - dec.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 161:19] - dec.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 162:21] - dec.io.lsu_fastint_stall_any <= lsu.io.lsu_fastint_stall_any @[quasar.scala 163:32] - dec.io.rst_vec <= io.rst_vec @[quasar.scala 164:18] - dec.io.nmi_int <= io.nmi_int @[quasar.scala 165:18] - dec.io.nmi_vec <= io.nmi_vec @[quasar.scala 166:18] - dec.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar.scala 167:25] - dec.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar.scala 168:24] - dec.io.core_id <= io.core_id @[quasar.scala 169:18] - dec.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar.scala 170:29] - dec.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar.scala 171:28] - dec.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar.scala 172:28] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data @[quasar.scala 173:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag @[quasar.scala 173:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error @[quasar.scala 173:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid @[quasar.scala 173:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[quasar.scala 173:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r @[quasar.scala 173:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m @[quasar.scala 173:18] - dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m @[quasar.scala 173:18] - dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any @[quasar.scala 173:18] - dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any @[quasar.scala 173:18] - dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any @[quasar.scala 173:18] - lsu.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[quasar.scala 173:18] - lsu.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable @[quasar.scala 173:18] - lsu.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable @[quasar.scala 173:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy @[quasar.scala 173:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error @[quasar.scala 173:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned @[quasar.scala 173:18] - dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn @[quasar.scala 173:18] - dec.io.lsu_tlu.lsu_pmu_store_external_m <= lsu.io.lsu_tlu.lsu_pmu_store_external_m @[quasar.scala 174:18] - dec.io.lsu_tlu.lsu_pmu_load_external_m <= lsu.io.lsu_tlu.lsu_pmu_load_external_m @[quasar.scala 174:18] - dec.io.lsu_pmu_misaligned_m <= lsu.io.lsu_pmu_misaligned_m @[quasar.scala 175:31] - dec.io.dma_pmu_dccm_read <= dma_ctrl.io.dma_pmu_dccm_read @[quasar.scala 176:28] - dec.io.dma_pmu_dccm_write <= dma_ctrl.io.dma_pmu_dccm_write @[quasar.scala 177:29] - dec.io.dma_pmu_any_read <= dma_ctrl.io.dma_pmu_any_read @[quasar.scala 178:27] - dec.io.dma_pmu_any_write <= dma_ctrl.io.dma_pmu_any_write @[quasar.scala 179:28] - dec.io.lsu_fir_addr <= lsu.io.lsu_fir_addr @[quasar.scala 180:23] - dec.io.lsu_fir_error <= lsu.io.lsu_fir_error @[quasar.scala 181:24] - dec.io.lsu_trigger_match_m <= lsu.io.lsu_trigger_match_m @[quasar.scala 182:30] - dec.io.dec_dbg.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 183:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_addr @[quasar.scala 183:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_type @[quasar.scala 183:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_write @[quasar.scala 183:18] - dec.io.dec_dbg.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_valid @[quasar.scala 183:18] - dec.io.lsu_idle_any <= lsu.io.lsu_idle_any @[quasar.scala 184:23] - dec.io.lsu_error_pkt_r.bits.addr <= lsu.io.lsu_error_pkt_r.bits.addr @[quasar.scala 185:26] - dec.io.lsu_error_pkt_r.bits.mscause <= lsu.io.lsu_error_pkt_r.bits.mscause @[quasar.scala 185:26] - dec.io.lsu_error_pkt_r.bits.exc_type <= lsu.io.lsu_error_pkt_r.bits.exc_type @[quasar.scala 185:26] - dec.io.lsu_error_pkt_r.bits.inst_type <= lsu.io.lsu_error_pkt_r.bits.inst_type @[quasar.scala 185:26] - dec.io.lsu_error_pkt_r.bits.single_ecc_error <= lsu.io.lsu_error_pkt_r.bits.single_ecc_error @[quasar.scala 185:26] - dec.io.lsu_error_pkt_r.valid <= lsu.io.lsu_error_pkt_r.valid @[quasar.scala 185:26] - dec.io.lsu_single_ecc_error_incr <= lsu.io.lsu_single_ecc_error_incr @[quasar.scala 186:36] - dec.io.exu_div_result <= exu.io.exu_div_result @[quasar.scala 187:25] - dec.io.exu_div_wren <= exu.io.exu_div_wren @[quasar.scala 188:23] - dec.io.lsu_result_m <= lsu.io.lsu_result_m @[quasar.scala 189:23] - dec.io.lsu_result_corr_r <= lsu.io.lsu_result_corr_r @[quasar.scala 190:28] - dec.io.lsu_load_stall_any <= lsu.io.lsu_load_stall_any @[quasar.scala 191:29] - dec.io.lsu_store_stall_any <= lsu.io.lsu_store_stall_any @[quasar.scala 192:30] - dec.io.dma_dccm_stall_any <= dma_ctrl.io.dma_dccm_stall_any @[quasar.scala 193:29] - dec.io.dma_iccm_stall_any <= dma_ctrl.io.ifu_dma.dma_ifc.dma_iccm_stall_any @[quasar.scala 194:29] - dec.io.iccm_dma_sb_error <= ifu.io.iccm_dma_sb_error @[quasar.scala 195:28] - dec.io.exu_flush_final <= exu.io.exu_flush_final @[quasar.scala 196:26] - dec.io.mexintpend <= pic_ctrl_inst.io.mexintpend @[quasar.scala 197:21] - dec.io.soft_int <= io.soft_int @[quasar.scala 198:19] - dec.io.pic_claimid <= pic_ctrl_inst.io.claimid @[quasar.scala 199:22] - dec.io.pic_pl <= pic_ctrl_inst.io.pl @[quasar.scala 200:17] - dec.io.mhwakeup <= pic_ctrl_inst.io.mhwakeup @[quasar.scala 201:19] - dec.io.dbg_halt_req <= dbg.io.dbg_halt_req @[quasar.scala 202:23] - dec.io.dbg_resume_req <= dbg.io.dbg_resume_req @[quasar.scala 203:25] - dec.io.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 204:26] - dec.io.timer_int <= io.timer_int @[quasar.scala 205:20] - dec.io.scan_mode <= io.scan_mode @[quasar.scala 206:20] - exu.io.dec_exu.gpr_exu.gpr_i0_rs2_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs2_d @[quasar.scala 209:18] - exu.io.dec_exu.gpr_exu.gpr_i0_rs1_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs1_d @[quasar.scala 209:18] - exu.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d <= dec.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d @[quasar.scala 209:18] - exu.io.dec_exu.ib_exu.dec_i0_pc_d <= dec.io.dec_exu.ib_exu.dec_i0_pc_d @[quasar.scala 209:18] - dec.io.dec_exu.tlu_exu.exu_npc_r <= exu.io.dec_exu.tlu_exu.exu_npc_r @[quasar.scala 209:18] - dec.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 @[quasar.scala 209:18] - dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken @[quasar.scala 209:18] - dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp @[quasar.scala 209:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_middle_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_middle_r @[quasar.scala 209:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_mp_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_mp_r @[quasar.scala 209:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_valid_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_valid_r @[quasar.scala 209:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 209:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_start_error_r @[quasar.scala 209:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_error_r @[quasar.scala 209:18] - dec.io.dec_exu.tlu_exu.exu_i0_br_hist_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_hist_r @[quasar.scala 209:18] - exu.io.dec_exu.tlu_exu.dec_tlu_flush_path_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_path_r @[quasar.scala 209:18] - exu.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 209:18] - exu.io.dec_exu.tlu_exu.dec_tlu_meihap <= dec.io.dec_exu.tlu_exu.dec_tlu_meihap @[quasar.scala 209:18] - dec.io.dec_exu.decode_exu.exu_csr_rs1_x <= exu.io.dec_exu.decode_exu.exu_csr_rs1_x @[quasar.scala 209:18] - dec.io.dec_exu.decode_exu.exu_i0_result_x <= exu.io.dec_exu.decode_exu.exu_i0_result_x @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_extint_stall <= dec.io.dec_exu.decode_exu.dec_extint_stall @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.pred_correct_npc_x <= dec.io.dec_exu.decode_exu.pred_correct_npc_x @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.mul_p.bits.bfp <= dec.io.dec_exu.decode_exu.mul_p.bits.bfp @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_w @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_h @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.mul_p.bits.crc32_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_b @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.mul_p.bits.unshfl <= dec.io.dec_exu.decode_exu.mul_p.bits.unshfl @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.mul_p.bits.shfl <= dec.io.dec_exu.decode_exu.mul_p.bits.shfl @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.mul_p.bits.grev <= dec.io.dec_exu.decode_exu.mul_p.bits.grev @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.mul_p.bits.clmulr <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulr @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.mul_p.bits.clmulh <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulh @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.mul_p.bits.clmul <= dec.io.dec_exu.decode_exu.mul_p.bits.clmul @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.mul_p.bits.bdep <= dec.io.dec_exu.decode_exu.mul_p.bits.bdep @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.mul_p.bits.bext <= dec.io.dec_exu.decode_exu.mul_p.bits.bext @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.mul_p.bits.low <= dec.io.dec_exu.decode_exu.mul_p.bits.low @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.mul_p.bits.rs2_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.mul_p.bits.rs1_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.mul_p.valid <= dec.io.dec_exu.decode_exu.mul_p.valid @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_select_pc_d <= dec.io.dec_exu.decode_exu.dec_i0_select_pc_d @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_immed_d <= dec.io.dec_exu.decode_exu.dec_i0_immed_d @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_rs2_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_en_d @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_rs1_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_en_d @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_predict_btag_d <= dec.io.dec_exu.decode_exu.i0_predict_btag_d @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_predict_index_d <= dec.io.dec_exu.decode_exu.i0_predict_index_d @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_predict_fghr_d <= dec.io.dec_exu.decode_exu.i0_predict_fghr_d @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_ap.csr_imm <= dec.io.dec_exu.decode_exu.i0_ap.csr_imm @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_ap.csr_write <= dec.io.dec_exu.decode_exu.i0_ap.csr_write @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_ap.predict_nt <= dec.io.dec_exu.decode_exu.i0_ap.predict_nt @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_ap.predict_t <= dec.io.dec_exu.decode_exu.i0_ap.predict_t @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_ap.jal <= dec.io.dec_exu.decode_exu.i0_ap.jal @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_ap.unsign <= dec.io.dec_exu.decode_exu.i0_ap.unsign @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_ap.slt <= dec.io.dec_exu.decode_exu.i0_ap.slt @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_ap.sub <= dec.io.dec_exu.decode_exu.i0_ap.sub @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_ap.add <= dec.io.dec_exu.decode_exu.i0_ap.add @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_ap.bge <= dec.io.dec_exu.decode_exu.i0_ap.bge @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_ap.blt <= dec.io.dec_exu.decode_exu.i0_ap.blt @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_ap.bne <= dec.io.dec_exu.decode_exu.i0_ap.bne @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_ap.beq <= dec.io.dec_exu.decode_exu.i0_ap.beq @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_ap.sra <= dec.io.dec_exu.decode_exu.i0_ap.sra @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_ap.srl <= dec.io.dec_exu.decode_exu.i0_ap.srl @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_ap.sll <= dec.io.dec_exu.decode_exu.i0_ap.sll @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_ap.lxor <= dec.io.dec_exu.decode_exu.i0_ap.lxor @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_ap.lor <= dec.io.dec_exu.decode_exu.i0_ap.lor @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.i0_ap.land <= dec.io.dec_exu.decode_exu.i0_ap.land @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_ctl_en <= dec.io.dec_exu.decode_exu.dec_ctl_en @[quasar.scala 209:18] - exu.io.dec_exu.decode_exu.dec_data_en <= dec.io.dec_exu.decode_exu.dec_data_en @[quasar.scala 209:18] - exu.io.dec_exu.dec_div.dec_div_cancel <= dec.io.dec_exu.dec_div.dec_div_cancel @[quasar.scala 209:18] - exu.io.dec_exu.dec_div.div_p.bits.rem <= dec.io.dec_exu.dec_div.div_p.bits.rem @[quasar.scala 209:18] - exu.io.dec_exu.dec_div.div_p.bits.unsign <= dec.io.dec_exu.dec_div.div_p.bits.unsign @[quasar.scala 209:18] - exu.io.dec_exu.dec_div.div_p.valid <= dec.io.dec_exu.dec_div.div_p.valid @[quasar.scala 209:18] - dec.io.dec_exu.dec_alu.exu_i0_pc_x <= exu.io.dec_exu.dec_alu.exu_i0_pc_x @[quasar.scala 209:18] - exu.io.dec_exu.dec_alu.dec_i0_br_immed_d <= dec.io.dec_exu.dec_alu.dec_i0_br_immed_d @[quasar.scala 209:18] - exu.io.dec_exu.dec_alu.dec_csr_ren_d <= dec.io.dec_exu.dec_alu.dec_csr_ren_d @[quasar.scala 209:18] - exu.io.dec_exu.dec_alu.dec_i0_alu_decode_d <= dec.io.dec_exu.dec_alu.dec_i0_alu_decode_d @[quasar.scala 209:18] - exu.reset <= io.core_rst_l @[quasar.scala 210:13] - exu.io.scan_mode <= io.scan_mode @[quasar.scala 211:20] - exu.io.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 212:25] - lsu.reset <= io.core_rst_l @[quasar.scala 215:13] - lsu.io.clk_override <= dec.io.dec_tlu_lsu_clk_override @[quasar.scala 216:23] - lsu.io.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 217:32] - lsu.io.dec_tlu_i0_kill_writeb_r <= dec.io.dec_tlu_i0_kill_writeb_r @[quasar.scala 218:35] - lsu.io.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 219:29] - lsu.io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 220:35] - lsu.io.lsu_exu.exu_lsu_rs2_d <= exu.io.lsu_exu.exu_lsu_rs2_d @[quasar.scala 221:18] - lsu.io.lsu_exu.exu_lsu_rs1_d <= exu.io.lsu_exu.exu_lsu_rs1_d @[quasar.scala 221:18] - lsu.io.dec_lsu_offset_d <= dec.io.dec_lsu_offset_d @[quasar.scala 222:27] - lsu.io.lsu_p.bits.store_data_bypass_m <= dec.io.lsu_p.bits.store_data_bypass_m @[quasar.scala 223:16] - lsu.io.lsu_p.bits.load_ldst_bypass_d <= dec.io.lsu_p.bits.load_ldst_bypass_d @[quasar.scala 223:16] - lsu.io.lsu_p.bits.store_data_bypass_d <= dec.io.lsu_p.bits.store_data_bypass_d @[quasar.scala 223:16] - lsu.io.lsu_p.bits.dma <= dec.io.lsu_p.bits.dma @[quasar.scala 223:16] - lsu.io.lsu_p.bits.unsign <= dec.io.lsu_p.bits.unsign @[quasar.scala 223:16] - lsu.io.lsu_p.bits.store <= dec.io.lsu_p.bits.store @[quasar.scala 223:16] - lsu.io.lsu_p.bits.load <= dec.io.lsu_p.bits.load @[quasar.scala 223:16] - lsu.io.lsu_p.bits.dword <= dec.io.lsu_p.bits.dword @[quasar.scala 223:16] - lsu.io.lsu_p.bits.word <= dec.io.lsu_p.bits.word @[quasar.scala 223:16] - lsu.io.lsu_p.bits.half <= dec.io.lsu_p.bits.half @[quasar.scala 223:16] - lsu.io.lsu_p.bits.by <= dec.io.lsu_p.bits.by @[quasar.scala 223:16] - lsu.io.lsu_p.bits.fast_int <= dec.io.lsu_p.bits.fast_int @[quasar.scala 223:16] - lsu.io.lsu_p.valid <= dec.io.lsu_p.valid @[quasar.scala 223:16] - lsu.io.dec_lsu_valid_raw_d <= dec.io.dec_lsu_valid_raw_d @[quasar.scala 224:30] - lsu.io.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 225:26] - lsu.io.trigger_pkt_any[0].tdata2 <= dec.io.trigger_pkt_any[0].tdata2 @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[0].m <= dec.io.trigger_pkt_any[0].m @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[0].execute <= dec.io.trigger_pkt_any[0].execute @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[0].load <= dec.io.trigger_pkt_any[0].load @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[0].store <= dec.io.trigger_pkt_any[0].store @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[0].match_pkt <= dec.io.trigger_pkt_any[0].match_pkt @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[0].select <= dec.io.trigger_pkt_any[0].select @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[1].tdata2 <= dec.io.trigger_pkt_any[1].tdata2 @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[1].m <= dec.io.trigger_pkt_any[1].m @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[1].execute <= dec.io.trigger_pkt_any[1].execute @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[1].load <= dec.io.trigger_pkt_any[1].load @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[1].store <= dec.io.trigger_pkt_any[1].store @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[1].match_pkt <= dec.io.trigger_pkt_any[1].match_pkt @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[1].select <= dec.io.trigger_pkt_any[1].select @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[2].tdata2 <= dec.io.trigger_pkt_any[2].tdata2 @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[2].m <= dec.io.trigger_pkt_any[2].m @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[2].execute <= dec.io.trigger_pkt_any[2].execute @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[2].load <= dec.io.trigger_pkt_any[2].load @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[2].store <= dec.io.trigger_pkt_any[2].store @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[2].match_pkt <= dec.io.trigger_pkt_any[2].match_pkt @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[2].select <= dec.io.trigger_pkt_any[2].select @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[3].tdata2 <= dec.io.trigger_pkt_any[3].tdata2 @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[3].m <= dec.io.trigger_pkt_any[3].m @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[3].execute <= dec.io.trigger_pkt_any[3].execute @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[3].load <= dec.io.trigger_pkt_any[3].load @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[3].store <= dec.io.trigger_pkt_any[3].store @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[3].match_pkt <= dec.io.trigger_pkt_any[3].match_pkt @[quasar.scala 226:26] - lsu.io.trigger_pkt_any[3].select <= dec.io.trigger_pkt_any[3].select @[quasar.scala 226:26] - lsu.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 228:25] - lsu.io.lsu_dma.dma_mem_tag <= dma_ctrl.io.lsu_dma.dma_mem_tag @[quasar.scala 229:18] - dma_ctrl.io.lsu_dma.dccm_ready <= lsu.io.lsu_dma.dccm_ready @[quasar.scala 229:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata @[quasar.scala 229:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag @[quasar.scala 229:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error @[quasar.scala 229:18] - dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid @[quasar.scala 229:18] - lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata @[quasar.scala 229:18] - lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_addr @[quasar.scala 229:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[quasar.scala 229:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_write <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_write @[quasar.scala 229:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[quasar.scala 229:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[quasar.scala 229:18] - lsu.io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[quasar.scala 229:18] - lsu.io.scan_mode <= io.scan_mode @[quasar.scala 230:20] - lsu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 231:19] - dbg.reset <= io.core_rst_l @[quasar.scala 234:13] - node _T_8 = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 235:32] - dbg.io.core_dbg_rddata <= _T_8 @[quasar.scala 235:26] - node _T_9 = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 236:60] - dbg.io.core_dbg_cmd_done <= _T_9 @[quasar.scala 236:28] - node _T_10 = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 237:60] - dbg.io.core_dbg_cmd_fail <= _T_10 @[quasar.scala 237:28] - dbg.io.dec_tlu_debug_mode <= dec.io.dec_tlu_debug_mode @[quasar.scala 238:29] - dbg.io.dec_tlu_dbg_halted <= dec.io.dec_tlu_dbg_halted @[quasar.scala 239:29] - dbg.io.dec_tlu_mpc_halted_only <= dec.io.dec_tlu_mpc_halted_only @[quasar.scala 240:34] - dbg.io.dec_tlu_resume_ack <= dec.io.dec_tlu_resume_ack @[quasar.scala 241:29] - dbg.io.dmi_reg_en <= io.dmi_reg_en @[quasar.scala 242:21] - dbg.io.dmi_reg_addr <= io.dmi_reg_addr @[quasar.scala 243:23] - dbg.io.dmi_reg_wr_en <= io.dmi_reg_wr_en @[quasar.scala 244:24] - dbg.io.dmi_reg_wdata <= io.dmi_reg_wdata @[quasar.scala 245:24] - dbg.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 246:17] - dbg.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 246:17] - dbg.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 246:17] - dbg.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 246:17] - dbg.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar.scala 246:17] - io.sb_axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 246:17] - io.sb_axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 246:17] - io.sb_axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 246:17] - io.sb_axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 246:17] - io.sb_axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 246:17] - io.sb_axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 246:17] - io.sb_axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 246:17] - io.sb_axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 246:17] - io.sb_axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 246:17] - io.sb_axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 246:17] - io.sb_axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 246:17] - io.sb_axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 246:17] - dbg.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 246:17] - dbg.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 246:17] - dbg.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 246:17] - dbg.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar.scala 246:17] - io.sb_axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 246:17] - io.sb_axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 246:17] - io.sb_axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 246:17] - io.sb_axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 246:17] - io.sb_axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 246:17] - dbg.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar.scala 246:17] - io.sb_axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 246:17] - io.sb_axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 246:17] - io.sb_axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 246:17] - io.sb_axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 246:17] - io.sb_axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 246:17] - io.sb_axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 246:17] - io.sb_axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 246:17] - io.sb_axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 246:17] - io.sb_axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 246:17] - io.sb_axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 246:17] - io.sb_axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 246:17] - dbg.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 246:17] - dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 247:25] - node _T_11 = asUInt(io.dbg_rst_l) @[quasar.scala 248:42] - dbg.io.dbg_rst_l <= _T_11 @[quasar.scala 248:20] - dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 249:23] - dbg.io.scan_mode <= io.scan_mode @[quasar.scala 250:20] - dma_ctrl.reset <= io.core_rst_l @[quasar.scala 254:18] - dma_ctrl.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 255:24] - dma_ctrl.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 256:30] - dma_ctrl.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 257:28] - dma_ctrl.io.scan_mode <= io.scan_mode @[quasar.scala 258:25] - dma_ctrl.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 259:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_addr @[quasar.scala 259:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_type @[quasar.scala 259:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_write @[quasar.scala 259:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_valid @[quasar.scala 259:23] - dbg.io.dbg_dma_io.dma_dbg_ready <= dma_ctrl.io.dbg_dma_io.dma_dbg_ready @[quasar.scala 260:26] - dma_ctrl.io.dbg_dma_io.dbg_dma_bubble <= dbg.io.dbg_dma_io.dbg_dma_bubble @[quasar.scala 260:26] - dma_ctrl.io.dbg_cmd_size <= dbg.io.dbg_cmd_size @[quasar.scala 261:28] - dma_ctrl.io.iccm_dma_rvalid <= ifu.io.iccm_dma_rvalid @[quasar.scala 262:31] - dma_ctrl.io.iccm_dma_rtag <= ifu.io.iccm_dma_rtag @[quasar.scala 263:29] - dma_ctrl.io.iccm_dma_rdata <= ifu.io.iccm_dma_rdata @[quasar.scala 264:30] - dma_ctrl.io.iccm_ready <= ifu.io.iccm_ready @[quasar.scala 265:26] - dma_ctrl.io.dec_tlu_dma_qos_prty <= dec.io.dec_tlu_dma_qos_prty @[quasar.scala 266:36] - dma_ctrl.io.iccm_dma_ecc_error <= ifu.io.iccm_dma_ecc_error @[quasar.scala 267:34] - pic_ctrl_inst.io.scan_mode <= io.scan_mode @[quasar.scala 270:30] - pic_ctrl_inst.reset <= io.core_rst_l @[quasar.scala 271:23] - pic_ctrl_inst.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 272:29] - pic_ctrl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 273:31] - pic_ctrl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[quasar.scala 274:33] - pic_ctrl_inst.io.extintsrc_req <= io.extintsrc_req @[quasar.scala 275:34] - lsu.io.lsu_pic.picm_rd_data <= pic_ctrl_inst.io.lsu_pic.picm_rd_data @[quasar.scala 276:28] - pic_ctrl_inst.io.lsu_pic.picm_wr_data <= lsu.io.lsu_pic.picm_wr_data @[quasar.scala 276:28] - pic_ctrl_inst.io.lsu_pic.picm_wraddr <= lsu.io.lsu_pic.picm_wraddr @[quasar.scala 276:28] - pic_ctrl_inst.io.lsu_pic.picm_rdaddr <= lsu.io.lsu_pic.picm_rdaddr @[quasar.scala 276:28] - pic_ctrl_inst.io.lsu_pic.picm_mken <= lsu.io.lsu_pic.picm_mken @[quasar.scala 276:28] - pic_ctrl_inst.io.lsu_pic.picm_rden <= lsu.io.lsu_pic.picm_rden @[quasar.scala 276:28] - pic_ctrl_inst.io.lsu_pic.picm_wren <= lsu.io.lsu_pic.picm_wren @[quasar.scala 276:28] - pic_ctrl_inst.io.meicurpl <= dec.io.dec_tlu_meicurpl @[quasar.scala 277:29] - pic_ctrl_inst.io.meipt <= dec.io.dec_tlu_meipt @[quasar.scala 278:26] - io.trace_rv_i_insn_ip <= dec.io.rv_trace_pkt.rv_i_insn_ip @[quasar.scala 280:25] - io.trace_rv_i_address_ip <= dec.io.rv_trace_pkt.rv_i_address_ip @[quasar.scala 281:28] - io.trace_rv_i_valid_ip <= dec.io.rv_trace_pkt.rv_i_valid_ip @[quasar.scala 282:26] - io.trace_rv_i_exception_ip <= dec.io.rv_trace_pkt.rv_i_exception_ip @[quasar.scala 283:30] - io.trace_rv_i_ecause_ip <= dec.io.rv_trace_pkt.rv_i_ecause_ip @[quasar.scala 284:27] - io.trace_rv_i_interrupt_ip <= dec.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar.scala 285:30] - io.trace_rv_i_tval_ip <= dec.io.rv_trace_pkt.rv_i_tval_ip @[quasar.scala 286:25] - io.dccm_clk_override <= dec.io.dec_tlu_dccm_clk_override @[quasar.scala 289:24] - io.icm_clk_override <= dec.io.dec_tlu_icm_clk_override @[quasar.scala 290:23] - io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 291:31] - io.o_cpu_halt_ack <= dec.io.o_cpu_halt_ack @[quasar.scala 292:21] - io.o_cpu_halt_status <= dec.io.o_cpu_halt_status @[quasar.scala 293:24] - io.o_cpu_run_ack <= dec.io.o_cpu_run_ack @[quasar.scala 294:20] - io.o_debug_mode_status <= dec.io.o_debug_mode_status @[quasar.scala 295:26] - io.mpc_debug_halt_ack <= dec.io.mpc_debug_halt_ack @[quasar.scala 296:25] - io.mpc_debug_run_ack <= dec.io.mpc_debug_run_ack @[quasar.scala 297:24] - io.debug_brkpt_status <= dec.io.debug_brkpt_status @[quasar.scala 298:25] - io.dec_tlu_perfcnt0 <= dec.io.dec_tlu_perfcnt0 @[quasar.scala 299:23] - io.dec_tlu_perfcnt1 <= dec.io.dec_tlu_perfcnt1 @[quasar.scala 300:23] - io.dec_tlu_perfcnt2 <= dec.io.dec_tlu_perfcnt2 @[quasar.scala 301:23] - io.dec_tlu_perfcnt3 <= dec.io.dec_tlu_perfcnt3 @[quasar.scala 302:23] - lsu.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[quasar.scala 304:11] - lsu.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[quasar.scala 304:11] - io.dccm.wr_data_hi <= lsu.io.dccm.wr_data_hi @[quasar.scala 304:11] - io.dccm.wr_data_lo <= lsu.io.dccm.wr_data_lo @[quasar.scala 304:11] - io.dccm.rd_addr_hi <= lsu.io.dccm.rd_addr_hi @[quasar.scala 304:11] - io.dccm.rd_addr_lo <= lsu.io.dccm.rd_addr_lo @[quasar.scala 304:11] - io.dccm.wr_addr_hi <= lsu.io.dccm.wr_addr_hi @[quasar.scala 304:11] - io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 304:11] - io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 304:11] - io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 304:11] - lsu.io.axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 307:14] - lsu.io.axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 307:14] - lsu.io.axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 307:14] - lsu.io.axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 307:14] - lsu.io.axi.r.valid <= io.lsu_axi.r.valid @[quasar.scala 307:14] - io.lsu_axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 307:14] - io.lsu_axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 307:14] - io.lsu_axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 307:14] - io.lsu_axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 307:14] - io.lsu_axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 307:14] - io.lsu_axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 307:14] - io.lsu_axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 307:14] - io.lsu_axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 307:14] - io.lsu_axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 307:14] - io.lsu_axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 307:14] - io.lsu_axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 307:14] - io.lsu_axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 307:14] - lsu.io.axi.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 307:14] - lsu.io.axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 307:14] - lsu.io.axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 307:14] - lsu.io.axi.b.valid <= io.lsu_axi.b.valid @[quasar.scala 307:14] - io.lsu_axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 307:14] - io.lsu_axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 307:14] - io.lsu_axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 307:14] - io.lsu_axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 307:14] - io.lsu_axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 307:14] - lsu.io.axi.w.ready <= io.lsu_axi.w.ready @[quasar.scala 307:14] - io.lsu_axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 307:14] - io.lsu_axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 307:14] - io.lsu_axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 307:14] - io.lsu_axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 307:14] - io.lsu_axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 307:14] - io.lsu_axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 307:14] - io.lsu_axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 307:14] - io.lsu_axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 307:14] - io.lsu_axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 307:14] - io.lsu_axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 307:14] - io.lsu_axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 307:14] - lsu.io.axi.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 307:14] - ifu.io.ifu.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 310:14] - ifu.io.ifu.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 310:14] - ifu.io.ifu.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 310:14] - ifu.io.ifu.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 310:14] - ifu.io.ifu.r.valid <= io.ifu_axi.r.valid @[quasar.scala 310:14] - io.ifu_axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 310:14] - io.ifu_axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 310:14] - io.ifu_axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 310:14] - io.ifu_axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 310:14] - io.ifu_axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 310:14] - io.ifu_axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 310:14] - io.ifu_axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 310:14] - io.ifu_axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 310:14] - io.ifu_axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 310:14] - io.ifu_axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 310:14] - io.ifu_axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 310:14] - io.ifu_axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 310:14] - ifu.io.ifu.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 310:14] - ifu.io.ifu.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 310:14] - ifu.io.ifu.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 310:14] - ifu.io.ifu.b.valid <= io.ifu_axi.b.valid @[quasar.scala 310:14] - io.ifu_axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 310:14] - io.ifu_axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 310:14] - io.ifu_axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 310:14] - io.ifu_axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 310:14] - io.ifu_axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 310:14] - ifu.io.ifu.w.ready <= io.ifu_axi.w.ready @[quasar.scala 310:14] - io.ifu_axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 310:14] - io.ifu_axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 310:14] - io.ifu_axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 310:14] - io.ifu_axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 310:14] - io.ifu_axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 310:14] - io.ifu_axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 310:14] - io.ifu_axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 310:14] - io.ifu_axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 310:14] - io.ifu_axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 310:14] - io.ifu_axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 310:14] - io.ifu_axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 310:14] - ifu.io.ifu.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 310:14] - io.dma_axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 311:14] - io.dma_axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 311:14] - io.dma_axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 311:14] - io.dma_axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 311:14] - io.dma_axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 311:14] - io.dma_axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 311:14] - io.dma_axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 311:14] - io.dma_axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 311:14] - io.dma_axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar.scala 311:14] - io.dma_axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 311:14] - dma_ctrl.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 311:14] - io.dma_axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 311:14] - when UInt<1>("h00") : @[quasar.scala 317:26] - inst axi4_to_ahb of axi4_to_ahb @[quasar.scala 318:33] + node core_dbg_cmd_done = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 128:56] + node core_dbg_cmd_fail = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 129:56] + node core_dbg_rddata = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 130:28] + ifu.io.ifu_dec.dec_bp.dec_tlu_bpred_disable <= dec.io.ifu_dec.dec_bp.dec_tlu_bpred_disable @[quasar.scala 133:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb <= dec.io.ifu_dec.dec_bp.dec_tlu_flush_leak_one_wb @[quasar.scala 133:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.middle @[quasar.scala 133:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.way @[quasar.scala 133:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_start_error @[quasar.scala 133:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.br_error @[quasar.scala 133:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.bits.hist @[quasar.scala 133:18] + ifu.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid <= dec.io.ifu_dec.dec_bp.dec_tlu_br0_r_pkt.valid @[quasar.scala 133:18] + dec.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall <= ifu.io.ifu_dec.dec_ifc.ifu_pmu_fetch_stall @[quasar.scala 133:18] + ifu.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 133:18] + ifu.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb <= dec.io.ifu_dec.dec_ifc.dec_tlu_flush_noredir_wb @[quasar.scala 133:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_miss_state_idle @[quasar.scala 133:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data_valid @[quasar.scala 133:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_debug_rd_data @[quasar.scala 133:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_iccm_rd_ecc_single_err @[quasar.scala 133:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_ic_error_start @[quasar.scala 133:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_trxn @[quasar.scala 133:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_busy @[quasar.scala 133:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_bus_error @[quasar.scala 133:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_hit @[quasar.scala 133:18] + dec.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss <= ifu.io.ifu_dec.dec_mem_ctrl.ifu_pmu_ic_miss @[quasar.scala 133:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 133:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 133:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 133:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 133:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 133:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_fence_i_wb @[quasar.scala 133:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 133:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_i0_commit_cmt @[quasar.scala 133:18] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_err_wb @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned <= ifu.io.ifu_dec.dec_aln.ifu_pmu_instr_aligned @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.ret @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.way @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.prett @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.bank @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_start_error @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.br_error @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.hist @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.bits.toffset @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid <= ifu.io.ifu_dec.dec_aln.aln_ib.i0_brp.valid @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_f1 @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf <= ifu.io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf @[quasar.scala 133:18] + dec.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst <= ifu.io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst @[quasar.scala 133:18] + ifu.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d <= dec.io.ifu_dec.dec_aln.aln_dec.dec_i0_decode_d @[quasar.scala 133:18] + ifu.reset <= io.core_rst_l @[quasar.scala 135:13] + ifu.io.scan_mode <= io.scan_mode @[quasar.scala 136:20] + ifu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 137:19] + ifu.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 138:21] + ifu.io.exu_flush_final <= dec.io.exu_flush_final @[quasar.scala 140:26] + ifu.io.exu_flush_path_final <= exu.io.exu_flush_path_final @[quasar.scala 141:31] + ifu.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 143:25] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_tag <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_tag @[quasar.scala 144:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_wdata <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_wdata @[quasar.scala 144:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_write <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_write @[quasar.scala 144:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_sz <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_sz @[quasar.scala 144:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_mem_addr <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_mem_addr @[quasar.scala 144:18] + ifu.io.ifu_dma.dma_mem_ctl.dma_iccm_req <= dma_ctrl.io.ifu_dma.dma_mem_ctl.dma_iccm_req @[quasar.scala 144:18] + ifu.io.ifu_dma.dma_ifc.dma_iccm_stall_any <= dma_ctrl.io.ifu_dma.dma_ifc.dma_iccm_stall_any @[quasar.scala 144:18] + io.ic.sel_premux_data <= ifu.io.ic.sel_premux_data @[quasar.scala 145:13] + io.ic.premux_data <= ifu.io.ic.premux_data @[quasar.scala 145:13] + io.ic.debug_way <= ifu.io.ic.debug_way @[quasar.scala 145:13] + io.ic.debug_tag_array <= ifu.io.ic.debug_tag_array @[quasar.scala 145:13] + io.ic.debug_wr_en <= ifu.io.ic.debug_wr_en @[quasar.scala 145:13] + io.ic.debug_rd_en <= ifu.io.ic.debug_rd_en @[quasar.scala 145:13] + ifu.io.ic.tag_perr <= io.ic.tag_perr @[quasar.scala 145:13] + ifu.io.ic.rd_hit <= io.ic.rd_hit @[quasar.scala 145:13] + ifu.io.ic.parerr <= io.ic.parerr @[quasar.scala 145:13] + ifu.io.ic.eccerr <= io.ic.eccerr @[quasar.scala 145:13] + ifu.io.ic.tag_debug_rd_data <= io.ic.tag_debug_rd_data @[quasar.scala 145:13] + ifu.io.ic.debug_rd_data <= io.ic.debug_rd_data @[quasar.scala 145:13] + ifu.io.ic.rd_data <= io.ic.rd_data @[quasar.scala 145:13] + io.ic.debug_addr <= ifu.io.ic.debug_addr @[quasar.scala 145:13] + io.ic.debug_wr_data <= ifu.io.ic.debug_wr_data @[quasar.scala 145:13] + io.ic.wr_data[0] <= ifu.io.ic.wr_data[0] @[quasar.scala 145:13] + io.ic.wr_data[1] <= ifu.io.ic.wr_data[1] @[quasar.scala 145:13] + io.ic.rd_en <= ifu.io.ic.rd_en @[quasar.scala 145:13] + io.ic.wr_en <= ifu.io.ic.wr_en @[quasar.scala 145:13] + io.ic.tag_valid <= ifu.io.ic.tag_valid @[quasar.scala 145:13] + io.ic.rw_addr <= ifu.io.ic.rw_addr @[quasar.scala 145:13] + ifu.io.iccm.rd_data_ecc <= io.iccm.rd_data_ecc @[quasar.scala 146:15] + ifu.io.iccm.rd_data <= io.iccm.rd_data @[quasar.scala 146:15] + io.iccm.wr_data <= ifu.io.iccm.wr_data @[quasar.scala 146:15] + io.iccm.wr_size <= ifu.io.iccm.wr_size @[quasar.scala 146:15] + io.iccm.rden <= ifu.io.iccm.rden @[quasar.scala 146:15] + io.iccm.wren <= ifu.io.iccm.wren @[quasar.scala 146:15] + io.iccm.correction_state <= ifu.io.iccm.correction_state @[quasar.scala 146:15] + io.iccm.buf_correct_ecc <= ifu.io.iccm.buf_correct_ecc @[quasar.scala 146:15] + io.iccm.rw_addr <= ifu.io.iccm.rw_addr @[quasar.scala 146:15] + ifu.io.exu_ifu.exu_bp.exu_mp_btag <= exu.io.exu_bp.exu_mp_btag @[quasar.scala 147:25] + ifu.io.exu_ifu.exu_bp.exu_mp_index <= exu.io.exu_bp.exu_mp_index @[quasar.scala 147:25] + ifu.io.exu_ifu.exu_bp.exu_mp_fghr <= exu.io.exu_bp.exu_mp_fghr @[quasar.scala 147:25] + ifu.io.exu_ifu.exu_bp.exu_mp_eghr <= exu.io.exu_bp.exu_mp_eghr @[quasar.scala 147:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.way <= exu.io.exu_bp.exu_mp_pkt.bits.way @[quasar.scala 147:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pja <= exu.io.exu_bp.exu_mp_pkt.bits.pja @[quasar.scala 147:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pret <= exu.io.exu_bp.exu_mp_pkt.bits.pret @[quasar.scala 147:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pcall <= exu.io.exu_bp.exu_mp_pkt.bits.pcall @[quasar.scala 147:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.prett <= exu.io.exu_bp.exu_mp_pkt.bits.prett @[quasar.scala 147:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_start_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_start_error @[quasar.scala 147:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.br_error <= exu.io.exu_bp.exu_mp_pkt.bits.br_error @[quasar.scala 147:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.toffset <= exu.io.exu_bp.exu_mp_pkt.bits.toffset @[quasar.scala 147:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.hist <= exu.io.exu_bp.exu_mp_pkt.bits.hist @[quasar.scala 147:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.pc4 <= exu.io.exu_bp.exu_mp_pkt.bits.pc4 @[quasar.scala 147:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.boffset <= exu.io.exu_bp.exu_mp_pkt.bits.boffset @[quasar.scala 147:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.ataken <= exu.io.exu_bp.exu_mp_pkt.bits.ataken @[quasar.scala 147:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.bits.misp <= exu.io.exu_bp.exu_mp_pkt.bits.misp @[quasar.scala 147:25] + ifu.io.exu_ifu.exu_bp.exu_mp_pkt.valid <= exu.io.exu_bp.exu_mp_pkt.valid @[quasar.scala 147:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 147:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 147:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.exu_bp.exu_i0_br_index_r @[quasar.scala 147:25] + ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r <= exu.io.exu_bp.exu_i0_br_fghr_r @[quasar.scala 148:42] + ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 149:43] + ifu.io.dec_tlu_flush_lower_wb <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 150:33] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wr_valid @[quasar.scala 151:51] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_rd_valid @[quasar.scala 151:51] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_dicawics @[quasar.scala 151:51] + ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt.icache_wrdata @[quasar.scala 151:51] + dec.reset <= io.core_rst_l @[quasar.scala 154:13] + dec.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 155:19] + dec.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 156:21] + dec.io.lsu_fastint_stall_any <= lsu.io.lsu_fastint_stall_any @[quasar.scala 157:32] + dec.io.rst_vec <= io.rst_vec @[quasar.scala 158:18] + dec.io.nmi_int <= io.nmi_int @[quasar.scala 159:18] + dec.io.nmi_vec <= io.nmi_vec @[quasar.scala 160:18] + dec.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar.scala 161:25] + dec.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar.scala 162:24] + dec.io.core_id <= io.core_id @[quasar.scala 163:18] + dec.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar.scala 164:29] + dec.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar.scala 165:28] + dec.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar.scala 166:28] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data @[quasar.scala 167:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_tag @[quasar.scala 167:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_error @[quasar.scala 167:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_data_valid @[quasar.scala 167:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_tag_r @[quasar.scala 167:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_inv_r @[quasar.scala 167:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_tag_m @[quasar.scala 167:18] + dec.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m <= lsu.io.lsu_dec.dctl_busbuff.lsu_nonblock_load_valid_m @[quasar.scala 167:18] + dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_addr_any @[quasar.scala 167:18] + dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_store_any @[quasar.scala 167:18] + dec.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any <= lsu.io.lsu_dec.tlu_busbuff.lsu_imprecise_error_load_any @[quasar.scala 167:18] + lsu.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_sideeffect_posted_disable @[quasar.scala 167:18] + lsu.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_wb_coalescing_disable @[quasar.scala 167:18] + lsu.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable <= dec.io.lsu_dec.tlu_busbuff.dec_tlu_external_ldfwd_disable @[quasar.scala 167:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_busy @[quasar.scala 167:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_error @[quasar.scala 167:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_misaligned @[quasar.scala 167:18] + dec.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn <= lsu.io.lsu_dec.tlu_busbuff.lsu_pmu_bus_trxn @[quasar.scala 167:18] + dec.io.lsu_tlu.lsu_pmu_store_external_m <= lsu.io.lsu_tlu.lsu_pmu_store_external_m @[quasar.scala 168:18] + dec.io.lsu_tlu.lsu_pmu_load_external_m <= lsu.io.lsu_tlu.lsu_pmu_load_external_m @[quasar.scala 168:18] + dec.io.lsu_pmu_misaligned_m <= lsu.io.lsu_pmu_misaligned_m @[quasar.scala 169:31] + dec.io.dec_dma.tlu_dma.dma_iccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_iccm_stall_any @[quasar.scala 170:18] + dec.io.dec_dma.tlu_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.tlu_dma.dma_dccm_stall_any @[quasar.scala 170:18] + dma_ctrl.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty <= dec.io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty @[quasar.scala 170:18] + dec.io.dec_dma.tlu_dma.dma_pmu_any_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_write @[quasar.scala 170:18] + dec.io.dec_dma.tlu_dma.dma_pmu_any_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_any_read @[quasar.scala 170:18] + dec.io.dec_dma.tlu_dma.dma_pmu_dccm_write <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_write @[quasar.scala 170:18] + dec.io.dec_dma.tlu_dma.dma_pmu_dccm_read <= dma_ctrl.io.dec_dma.tlu_dma.dma_pmu_dccm_read @[quasar.scala 170:18] + dec.io.dec_dma.dctl_dma.dma_dccm_stall_any <= dma_ctrl.io.dec_dma.dctl_dma.dma_dccm_stall_any @[quasar.scala 170:18] + dec.io.lsu_fir_addr <= lsu.io.lsu_fir_addr @[quasar.scala 172:23] + dec.io.lsu_fir_error <= lsu.io.lsu_fir_error @[quasar.scala 173:24] + dec.io.lsu_trigger_match_m <= lsu.io.lsu_trigger_match_m @[quasar.scala 174:30] + dec.io.dec_dbg.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 175:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_addr @[quasar.scala 175:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_type @[quasar.scala 175:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_write @[quasar.scala 175:18] + dec.io.dec_dbg.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dec.dbg_ib.dbg_cmd_valid @[quasar.scala 175:18] + dec.io.lsu_idle_any <= lsu.io.lsu_idle_any @[quasar.scala 176:23] + dec.io.lsu_error_pkt_r.bits.addr <= lsu.io.lsu_error_pkt_r.bits.addr @[quasar.scala 177:26] + dec.io.lsu_error_pkt_r.bits.mscause <= lsu.io.lsu_error_pkt_r.bits.mscause @[quasar.scala 177:26] + dec.io.lsu_error_pkt_r.bits.exc_type <= lsu.io.lsu_error_pkt_r.bits.exc_type @[quasar.scala 177:26] + dec.io.lsu_error_pkt_r.bits.inst_type <= lsu.io.lsu_error_pkt_r.bits.inst_type @[quasar.scala 177:26] + dec.io.lsu_error_pkt_r.bits.single_ecc_error <= lsu.io.lsu_error_pkt_r.bits.single_ecc_error @[quasar.scala 177:26] + dec.io.lsu_error_pkt_r.valid <= lsu.io.lsu_error_pkt_r.valid @[quasar.scala 177:26] + dec.io.lsu_single_ecc_error_incr <= lsu.io.lsu_single_ecc_error_incr @[quasar.scala 178:36] + dec.io.exu_div_result <= exu.io.exu_div_result @[quasar.scala 179:25] + dec.io.exu_div_wren <= exu.io.exu_div_wren @[quasar.scala 180:23] + dec.io.lsu_result_m <= lsu.io.lsu_result_m @[quasar.scala 181:23] + dec.io.lsu_result_corr_r <= lsu.io.lsu_result_corr_r @[quasar.scala 182:28] + dec.io.lsu_load_stall_any <= lsu.io.lsu_load_stall_any @[quasar.scala 183:29] + dec.io.lsu_store_stall_any <= lsu.io.lsu_store_stall_any @[quasar.scala 184:30] + dec.io.iccm_dma_sb_error <= ifu.io.iccm_dma_sb_error @[quasar.scala 185:28] + dec.io.exu_flush_final <= exu.io.exu_flush_final @[quasar.scala 186:26] + dec.io.soft_int <= io.soft_int @[quasar.scala 188:19] + dec.io.dbg_halt_req <= dbg.io.dbg_halt_req @[quasar.scala 189:23] + dec.io.dbg_resume_req <= dbg.io.dbg_resume_req @[quasar.scala 190:25] + dec.io.exu_i0_br_way_r <= exu.io.exu_bp.exu_i0_br_way_r @[quasar.scala 191:26] + dec.io.timer_int <= io.timer_int @[quasar.scala 192:20] + dec.io.scan_mode <= io.scan_mode @[quasar.scala 193:20] + exu.io.dec_exu.gpr_exu.gpr_i0_rs2_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs2_d @[quasar.scala 196:18] + exu.io.dec_exu.gpr_exu.gpr_i0_rs1_d <= dec.io.dec_exu.gpr_exu.gpr_i0_rs1_d @[quasar.scala 196:18] + exu.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d <= dec.io.dec_exu.ib_exu.dec_debug_wdata_rs1_d @[quasar.scala 196:18] + exu.io.dec_exu.ib_exu.dec_i0_pc_d <= dec.io.dec_exu.ib_exu.dec_i0_pc_d @[quasar.scala 196:18] + dec.io.dec_exu.tlu_exu.exu_npc_r <= exu.io.dec_exu.tlu_exu.exu_npc_r @[quasar.scala 196:18] + dec.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_pc4 @[quasar.scala 196:18] + dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_ataken @[quasar.scala 196:18] + dec.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp <= exu.io.dec_exu.tlu_exu.exu_pmu_i0_br_misp @[quasar.scala 196:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_middle_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_middle_r @[quasar.scala 196:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_mp_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_mp_r @[quasar.scala 196:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_valid_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_valid_r @[quasar.scala 196:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_index_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_index_r @[quasar.scala 196:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_start_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_start_error_r @[quasar.scala 196:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_error_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_error_r @[quasar.scala 196:18] + dec.io.dec_exu.tlu_exu.exu_i0_br_hist_r <= exu.io.dec_exu.tlu_exu.exu_i0_br_hist_r @[quasar.scala 196:18] + exu.io.dec_exu.tlu_exu.dec_tlu_flush_path_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_path_r @[quasar.scala 196:18] + exu.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 196:18] + exu.io.dec_exu.tlu_exu.dec_tlu_meihap <= dec.io.dec_exu.tlu_exu.dec_tlu_meihap @[quasar.scala 196:18] + dec.io.dec_exu.decode_exu.exu_csr_rs1_x <= exu.io.dec_exu.decode_exu.exu_csr_rs1_x @[quasar.scala 196:18] + dec.io.dec_exu.decode_exu.exu_i0_result_x <= exu.io.dec_exu.decode_exu.exu_i0_result_x @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_extint_stall <= dec.io.dec_exu.decode_exu.dec_extint_stall @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.pred_correct_npc_x <= dec.io.dec_exu.decode_exu.pred_correct_npc_x @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.mul_p.bits.bfp <= dec.io.dec_exu.decode_exu.mul_p.bits.bfp @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_w @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_h @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32c_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32c_b @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32_w <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_w @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32_h <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_h @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.mul_p.bits.crc32_b <= dec.io.dec_exu.decode_exu.mul_p.bits.crc32_b @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.mul_p.bits.unshfl <= dec.io.dec_exu.decode_exu.mul_p.bits.unshfl @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.mul_p.bits.shfl <= dec.io.dec_exu.decode_exu.mul_p.bits.shfl @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.mul_p.bits.grev <= dec.io.dec_exu.decode_exu.mul_p.bits.grev @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.mul_p.bits.clmulr <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulr @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.mul_p.bits.clmulh <= dec.io.dec_exu.decode_exu.mul_p.bits.clmulh @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.mul_p.bits.clmul <= dec.io.dec_exu.decode_exu.mul_p.bits.clmul @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.mul_p.bits.bdep <= dec.io.dec_exu.decode_exu.mul_p.bits.bdep @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.mul_p.bits.bext <= dec.io.dec_exu.decode_exu.mul_p.bits.bext @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.mul_p.bits.low <= dec.io.dec_exu.decode_exu.mul_p.bits.low @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.mul_p.bits.rs2_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs2_sign @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.mul_p.bits.rs1_sign <= dec.io.dec_exu.decode_exu.mul_p.bits.rs1_sign @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.mul_p.valid <= dec.io.dec_exu.decode_exu.mul_p.valid @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_en_d @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_en_d @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_select_pc_d <= dec.io.dec_exu.decode_exu.dec_i0_select_pc_d @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_bypass_data_d @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_bypass_data_d @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_immed_d <= dec.io.dec_exu.decode_exu.dec_i0_immed_d @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_rs2_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs2_en_d @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_rs1_en_d <= dec.io.dec_exu.decode_exu.dec_i0_rs1_en_d @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_predict_btag_d <= dec.io.dec_exu.decode_exu.i0_predict_btag_d @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_predict_index_d <= dec.io.dec_exu.decode_exu.i0_predict_index_d @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_predict_fghr_d <= dec.io.dec_exu.decode_exu.i0_predict_fghr_d @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.way @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pja @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pret @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pcall @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.prett @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_start_error @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.br_error @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.toffset @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.hist @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.pc4 @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.boffset @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.ataken @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.bits.misp @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid <= dec.io.dec_exu.decode_exu.dec_i0_predict_p_d.valid @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_ap.csr_imm <= dec.io.dec_exu.decode_exu.i0_ap.csr_imm @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_ap.csr_write <= dec.io.dec_exu.decode_exu.i0_ap.csr_write @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_ap.predict_nt <= dec.io.dec_exu.decode_exu.i0_ap.predict_nt @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_ap.predict_t <= dec.io.dec_exu.decode_exu.i0_ap.predict_t @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_ap.jal <= dec.io.dec_exu.decode_exu.i0_ap.jal @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_ap.unsign <= dec.io.dec_exu.decode_exu.i0_ap.unsign @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_ap.slt <= dec.io.dec_exu.decode_exu.i0_ap.slt @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_ap.sub <= dec.io.dec_exu.decode_exu.i0_ap.sub @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_ap.add <= dec.io.dec_exu.decode_exu.i0_ap.add @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_ap.bge <= dec.io.dec_exu.decode_exu.i0_ap.bge @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_ap.blt <= dec.io.dec_exu.decode_exu.i0_ap.blt @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_ap.bne <= dec.io.dec_exu.decode_exu.i0_ap.bne @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_ap.beq <= dec.io.dec_exu.decode_exu.i0_ap.beq @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_ap.sra <= dec.io.dec_exu.decode_exu.i0_ap.sra @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_ap.srl <= dec.io.dec_exu.decode_exu.i0_ap.srl @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_ap.sll <= dec.io.dec_exu.decode_exu.i0_ap.sll @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_ap.lxor <= dec.io.dec_exu.decode_exu.i0_ap.lxor @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_ap.lor <= dec.io.dec_exu.decode_exu.i0_ap.lor @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.i0_ap.land <= dec.io.dec_exu.decode_exu.i0_ap.land @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_ctl_en <= dec.io.dec_exu.decode_exu.dec_ctl_en @[quasar.scala 196:18] + exu.io.dec_exu.decode_exu.dec_data_en <= dec.io.dec_exu.decode_exu.dec_data_en @[quasar.scala 196:18] + exu.io.dec_exu.dec_div.dec_div_cancel <= dec.io.dec_exu.dec_div.dec_div_cancel @[quasar.scala 196:18] + exu.io.dec_exu.dec_div.div_p.bits.rem <= dec.io.dec_exu.dec_div.div_p.bits.rem @[quasar.scala 196:18] + exu.io.dec_exu.dec_div.div_p.bits.unsign <= dec.io.dec_exu.dec_div.div_p.bits.unsign @[quasar.scala 196:18] + exu.io.dec_exu.dec_div.div_p.valid <= dec.io.dec_exu.dec_div.div_p.valid @[quasar.scala 196:18] + dec.io.dec_exu.dec_alu.exu_i0_pc_x <= exu.io.dec_exu.dec_alu.exu_i0_pc_x @[quasar.scala 196:18] + exu.io.dec_exu.dec_alu.dec_i0_br_immed_d <= dec.io.dec_exu.dec_alu.dec_i0_br_immed_d @[quasar.scala 196:18] + exu.io.dec_exu.dec_alu.dec_csr_ren_d <= dec.io.dec_exu.dec_alu.dec_csr_ren_d @[quasar.scala 196:18] + exu.io.dec_exu.dec_alu.dec_i0_alu_decode_d <= dec.io.dec_exu.dec_alu.dec_i0_alu_decode_d @[quasar.scala 196:18] + exu.reset <= io.core_rst_l @[quasar.scala 197:13] + exu.io.scan_mode <= io.scan_mode @[quasar.scala 198:20] + exu.io.dbg_cmd_wrdata <= dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 199:25] + lsu.reset <= io.core_rst_l @[quasar.scala 202:13] + lsu.io.clk_override <= dec.io.dec_tlu_lsu_clk_override @[quasar.scala 203:23] + lsu.io.dec_tlu_flush_lower_r <= dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r @[quasar.scala 204:32] + lsu.io.dec_tlu_i0_kill_writeb_r <= dec.io.dec_tlu_i0_kill_writeb_r @[quasar.scala 205:35] + lsu.io.dec_tlu_force_halt <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt @[quasar.scala 206:29] + lsu.io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 207:35] + lsu.io.lsu_exu.exu_lsu_rs2_d <= exu.io.lsu_exu.exu_lsu_rs2_d @[quasar.scala 208:18] + lsu.io.lsu_exu.exu_lsu_rs1_d <= exu.io.lsu_exu.exu_lsu_rs1_d @[quasar.scala 208:18] + lsu.io.dec_lsu_offset_d <= dec.io.dec_lsu_offset_d @[quasar.scala 209:27] + lsu.io.lsu_p.bits.store_data_bypass_m <= dec.io.lsu_p.bits.store_data_bypass_m @[quasar.scala 210:16] + lsu.io.lsu_p.bits.load_ldst_bypass_d <= dec.io.lsu_p.bits.load_ldst_bypass_d @[quasar.scala 210:16] + lsu.io.lsu_p.bits.store_data_bypass_d <= dec.io.lsu_p.bits.store_data_bypass_d @[quasar.scala 210:16] + lsu.io.lsu_p.bits.dma <= dec.io.lsu_p.bits.dma @[quasar.scala 210:16] + lsu.io.lsu_p.bits.unsign <= dec.io.lsu_p.bits.unsign @[quasar.scala 210:16] + lsu.io.lsu_p.bits.store <= dec.io.lsu_p.bits.store @[quasar.scala 210:16] + lsu.io.lsu_p.bits.load <= dec.io.lsu_p.bits.load @[quasar.scala 210:16] + lsu.io.lsu_p.bits.dword <= dec.io.lsu_p.bits.dword @[quasar.scala 210:16] + lsu.io.lsu_p.bits.word <= dec.io.lsu_p.bits.word @[quasar.scala 210:16] + lsu.io.lsu_p.bits.half <= dec.io.lsu_p.bits.half @[quasar.scala 210:16] + lsu.io.lsu_p.bits.by <= dec.io.lsu_p.bits.by @[quasar.scala 210:16] + lsu.io.lsu_p.bits.fast_int <= dec.io.lsu_p.bits.fast_int @[quasar.scala 210:16] + lsu.io.lsu_p.valid <= dec.io.lsu_p.valid @[quasar.scala 210:16] + lsu.io.dec_lsu_valid_raw_d <= dec.io.dec_lsu_valid_raw_d @[quasar.scala 211:30] + lsu.io.dec_tlu_mrac_ff <= dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff @[quasar.scala 212:26] + lsu.io.trigger_pkt_any[0].tdata2 <= dec.io.trigger_pkt_any[0].tdata2 @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[0].m <= dec.io.trigger_pkt_any[0].m @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[0].execute <= dec.io.trigger_pkt_any[0].execute @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[0].load <= dec.io.trigger_pkt_any[0].load @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[0].store <= dec.io.trigger_pkt_any[0].store @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[0].match_pkt <= dec.io.trigger_pkt_any[0].match_pkt @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[0].select <= dec.io.trigger_pkt_any[0].select @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[1].tdata2 <= dec.io.trigger_pkt_any[1].tdata2 @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[1].m <= dec.io.trigger_pkt_any[1].m @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[1].execute <= dec.io.trigger_pkt_any[1].execute @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[1].load <= dec.io.trigger_pkt_any[1].load @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[1].store <= dec.io.trigger_pkt_any[1].store @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[1].match_pkt <= dec.io.trigger_pkt_any[1].match_pkt @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[1].select <= dec.io.trigger_pkt_any[1].select @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[2].tdata2 <= dec.io.trigger_pkt_any[2].tdata2 @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[2].m <= dec.io.trigger_pkt_any[2].m @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[2].execute <= dec.io.trigger_pkt_any[2].execute @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[2].load <= dec.io.trigger_pkt_any[2].load @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[2].store <= dec.io.trigger_pkt_any[2].store @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[2].match_pkt <= dec.io.trigger_pkt_any[2].match_pkt @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[2].select <= dec.io.trigger_pkt_any[2].select @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[3].tdata2 <= dec.io.trigger_pkt_any[3].tdata2 @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[3].m <= dec.io.trigger_pkt_any[3].m @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[3].execute <= dec.io.trigger_pkt_any[3].execute @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[3].load <= dec.io.trigger_pkt_any[3].load @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[3].store <= dec.io.trigger_pkt_any[3].store @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[3].match_pkt <= dec.io.trigger_pkt_any[3].match_pkt @[quasar.scala 213:26] + lsu.io.trigger_pkt_any[3].select <= dec.io.trigger_pkt_any[3].select @[quasar.scala 213:26] + lsu.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 215:25] + lsu.io.lsu_dma.dma_mem_tag <= dma_ctrl.io.lsu_dma.dma_mem_tag @[quasar.scala 216:18] + dma_ctrl.io.lsu_dma.dccm_ready <= lsu.io.lsu_dma.dccm_ready @[quasar.scala 216:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata @[quasar.scala 216:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag @[quasar.scala 216:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error @[quasar.scala 216:18] + dma_ctrl.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid <= lsu.io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid @[quasar.scala 216:18] + lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_wdata @[quasar.scala 216:18] + lsu.io.lsu_dma.dma_dccm_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_dccm_ctl.dma_mem_addr @[quasar.scala 216:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_wdata @[quasar.scala 216:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_write <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_write @[quasar.scala 216:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_sz <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_sz @[quasar.scala 216:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_mem_addr <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_mem_addr @[quasar.scala 216:18] + lsu.io.lsu_dma.dma_lsc_ctl.dma_dccm_req <= dma_ctrl.io.lsu_dma.dma_lsc_ctl.dma_dccm_req @[quasar.scala 216:18] + lsu.io.scan_mode <= io.scan_mode @[quasar.scala 217:20] + lsu.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 218:19] + dbg.reset <= io.core_rst_l @[quasar.scala 221:13] + node _T_8 = mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata) @[quasar.scala 222:32] + dbg.io.core_dbg_rddata <= _T_8 @[quasar.scala 222:26] + node _T_9 = or(dma_ctrl.io.dma_dbg_cmd_done, dec.io.dec_dbg_cmd_done) @[quasar.scala 223:60] + dbg.io.core_dbg_cmd_done <= _T_9 @[quasar.scala 223:28] + node _T_10 = or(dma_ctrl.io.dma_dbg_cmd_fail, dec.io.dec_dbg_cmd_fail) @[quasar.scala 224:60] + dbg.io.core_dbg_cmd_fail <= _T_10 @[quasar.scala 224:28] + dbg.io.dec_tlu_debug_mode <= dec.io.dec_tlu_debug_mode @[quasar.scala 225:29] + dbg.io.dec_tlu_dbg_halted <= dec.io.dec_tlu_dbg_halted @[quasar.scala 226:29] + dbg.io.dec_tlu_mpc_halted_only <= dec.io.dec_tlu_mpc_halted_only @[quasar.scala 227:34] + dbg.io.dec_tlu_resume_ack <= dec.io.dec_tlu_resume_ack @[quasar.scala 228:29] + dbg.io.dmi_reg_en <= io.dmi_reg_en @[quasar.scala 229:21] + dbg.io.dmi_reg_addr <= io.dmi_reg_addr @[quasar.scala 230:23] + dbg.io.dmi_reg_wr_en <= io.dmi_reg_wr_en @[quasar.scala 231:24] + dbg.io.dmi_reg_wdata <= io.dmi_reg_wdata @[quasar.scala 232:24] + dbg.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 233:17] + dbg.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 233:17] + dbg.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 233:17] + dbg.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 233:17] + dbg.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar.scala 233:17] + io.sb_axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 233:17] + io.sb_axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 233:17] + io.sb_axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 233:17] + io.sb_axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 233:17] + io.sb_axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 233:17] + io.sb_axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 233:17] + io.sb_axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 233:17] + io.sb_axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 233:17] + io.sb_axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 233:17] + io.sb_axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 233:17] + io.sb_axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 233:17] + io.sb_axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 233:17] + dbg.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 233:17] + dbg.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 233:17] + dbg.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 233:17] + dbg.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar.scala 233:17] + io.sb_axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 233:17] + io.sb_axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 233:17] + io.sb_axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 233:17] + io.sb_axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 233:17] + io.sb_axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 233:17] + dbg.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar.scala 233:17] + io.sb_axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 233:17] + io.sb_axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 233:17] + io.sb_axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 233:17] + io.sb_axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 233:17] + io.sb_axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 233:17] + io.sb_axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 233:17] + io.sb_axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 233:17] + io.sb_axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 233:17] + io.sb_axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 233:17] + io.sb_axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 233:17] + io.sb_axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 233:17] + dbg.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 233:17] + dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 234:25] + node _T_11 = asUInt(io.dbg_rst_l) @[quasar.scala 235:42] + dbg.io.dbg_rst_l <= _T_11 @[quasar.scala 235:20] + dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 236:23] + dbg.io.scan_mode <= io.scan_mode @[quasar.scala 237:20] + dma_ctrl.reset <= io.core_rst_l @[quasar.scala 241:18] + dma_ctrl.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 242:24] + dma_ctrl.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 243:30] + dma_ctrl.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 244:28] + dma_ctrl.io.scan_mode <= io.scan_mode @[quasar.scala 245:25] + dma_ctrl.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 246:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_addr @[quasar.scala 246:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_type @[quasar.scala 246:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_write @[quasar.scala 246:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_valid @[quasar.scala 246:23] + dbg.io.dbg_dma_io.dma_dbg_ready <= dma_ctrl.io.dbg_dma_io.dma_dbg_ready @[quasar.scala 247:26] + dma_ctrl.io.dbg_dma_io.dbg_dma_bubble <= dbg.io.dbg_dma_io.dbg_dma_bubble @[quasar.scala 247:26] + dma_ctrl.io.dbg_cmd_size <= dbg.io.dbg_cmd_size @[quasar.scala 248:28] + dma_ctrl.io.iccm_dma_rvalid <= ifu.io.iccm_dma_rvalid @[quasar.scala 249:31] + dma_ctrl.io.iccm_dma_rtag <= ifu.io.iccm_dma_rtag @[quasar.scala 250:29] + dma_ctrl.io.iccm_dma_rdata <= ifu.io.iccm_dma_rdata @[quasar.scala 251:30] + dma_ctrl.io.iccm_ready <= ifu.io.iccm_ready @[quasar.scala 252:26] + dma_ctrl.io.iccm_dma_ecc_error <= ifu.io.iccm_dma_ecc_error @[quasar.scala 253:34] + pic_ctrl_inst.io.scan_mode <= io.scan_mode @[quasar.scala 256:30] + pic_ctrl_inst.reset <= io.core_rst_l @[quasar.scala 257:23] + pic_ctrl_inst.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 258:29] + pic_ctrl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 259:31] + pic_ctrl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[quasar.scala 260:33] + pic_ctrl_inst.io.extintsrc_req <= io.extintsrc_req @[quasar.scala 261:34] + lsu.io.lsu_pic.picm_rd_data <= pic_ctrl_inst.io.lsu_pic.picm_rd_data @[quasar.scala 262:28] + pic_ctrl_inst.io.lsu_pic.picm_wr_data <= lsu.io.lsu_pic.picm_wr_data @[quasar.scala 262:28] + pic_ctrl_inst.io.lsu_pic.picm_wraddr <= lsu.io.lsu_pic.picm_wraddr @[quasar.scala 262:28] + pic_ctrl_inst.io.lsu_pic.picm_rdaddr <= lsu.io.lsu_pic.picm_rdaddr @[quasar.scala 262:28] + pic_ctrl_inst.io.lsu_pic.picm_mken <= lsu.io.lsu_pic.picm_mken @[quasar.scala 262:28] + pic_ctrl_inst.io.lsu_pic.picm_rden <= lsu.io.lsu_pic.picm_rden @[quasar.scala 262:28] + pic_ctrl_inst.io.lsu_pic.picm_wren <= lsu.io.lsu_pic.picm_wren @[quasar.scala 262:28] + dec.io.dec_pic.mexintpend <= pic_ctrl_inst.io.dec_pic.mexintpend @[quasar.scala 263:28] + pic_ctrl_inst.io.dec_pic.dec_tlu_meipt <= dec.io.dec_pic.dec_tlu_meipt @[quasar.scala 263:28] + pic_ctrl_inst.io.dec_pic.dec_tlu_meicurpl <= dec.io.dec_pic.dec_tlu_meicurpl @[quasar.scala 263:28] + dec.io.dec_pic.mhwakeup <= pic_ctrl_inst.io.dec_pic.mhwakeup @[quasar.scala 263:28] + dec.io.dec_pic.pic_pl <= pic_ctrl_inst.io.dec_pic.pic_pl @[quasar.scala 263:28] + dec.io.dec_pic.pic_claimid <= pic_ctrl_inst.io.dec_pic.pic_claimid @[quasar.scala 263:28] + io.rv_trace_pkt.rv_i_tval_ip <= dec.io.rv_trace_pkt.rv_i_tval_ip @[quasar.scala 265:19] + io.rv_trace_pkt.rv_i_interrupt_ip <= dec.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar.scala 265:19] + io.rv_trace_pkt.rv_i_ecause_ip <= dec.io.rv_trace_pkt.rv_i_ecause_ip @[quasar.scala 265:19] + io.rv_trace_pkt.rv_i_exception_ip <= dec.io.rv_trace_pkt.rv_i_exception_ip @[quasar.scala 265:19] + io.rv_trace_pkt.rv_i_address_ip <= dec.io.rv_trace_pkt.rv_i_address_ip @[quasar.scala 265:19] + io.rv_trace_pkt.rv_i_insn_ip <= dec.io.rv_trace_pkt.rv_i_insn_ip @[quasar.scala 265:19] + io.rv_trace_pkt.rv_i_valid_ip <= dec.io.rv_trace_pkt.rv_i_valid_ip @[quasar.scala 265:19] + io.dccm_clk_override <= dec.io.dec_tlu_dccm_clk_override @[quasar.scala 268:24] + io.icm_clk_override <= dec.io.dec_tlu_icm_clk_override @[quasar.scala 269:23] + io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 270:31] + io.o_cpu_halt_ack <= dec.io.o_cpu_halt_ack @[quasar.scala 271:21] + io.o_cpu_halt_status <= dec.io.o_cpu_halt_status @[quasar.scala 272:24] + io.o_cpu_run_ack <= dec.io.o_cpu_run_ack @[quasar.scala 273:20] + io.o_debug_mode_status <= dec.io.o_debug_mode_status @[quasar.scala 274:26] + io.mpc_debug_halt_ack <= dec.io.mpc_debug_halt_ack @[quasar.scala 275:25] + io.mpc_debug_run_ack <= dec.io.mpc_debug_run_ack @[quasar.scala 276:24] + io.debug_brkpt_status <= dec.io.debug_brkpt_status @[quasar.scala 277:25] + io.dec_tlu_perfcnt0 <= dec.io.dec_tlu_perfcnt0 @[quasar.scala 278:23] + io.dec_tlu_perfcnt1 <= dec.io.dec_tlu_perfcnt1 @[quasar.scala 279:23] + io.dec_tlu_perfcnt2 <= dec.io.dec_tlu_perfcnt2 @[quasar.scala 280:23] + io.dec_tlu_perfcnt3 <= dec.io.dec_tlu_perfcnt3 @[quasar.scala 281:23] + lsu.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[quasar.scala 283:11] + lsu.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[quasar.scala 283:11] + io.dccm.wr_data_hi <= lsu.io.dccm.wr_data_hi @[quasar.scala 283:11] + io.dccm.wr_data_lo <= lsu.io.dccm.wr_data_lo @[quasar.scala 283:11] + io.dccm.rd_addr_hi <= lsu.io.dccm.rd_addr_hi @[quasar.scala 283:11] + io.dccm.rd_addr_lo <= lsu.io.dccm.rd_addr_lo @[quasar.scala 283:11] + io.dccm.wr_addr_hi <= lsu.io.dccm.wr_addr_hi @[quasar.scala 283:11] + io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 283:11] + io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 283:11] + io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 283:11] + lsu.io.axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 286:14] + lsu.io.axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 286:14] + lsu.io.axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 286:14] + lsu.io.axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 286:14] + lsu.io.axi.r.valid <= io.lsu_axi.r.valid @[quasar.scala 286:14] + io.lsu_axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 286:14] + io.lsu_axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 286:14] + io.lsu_axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 286:14] + io.lsu_axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 286:14] + io.lsu_axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 286:14] + io.lsu_axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 286:14] + io.lsu_axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 286:14] + io.lsu_axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 286:14] + io.lsu_axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 286:14] + io.lsu_axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 286:14] + io.lsu_axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 286:14] + io.lsu_axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 286:14] + lsu.io.axi.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 286:14] + lsu.io.axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 286:14] + lsu.io.axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 286:14] + lsu.io.axi.b.valid <= io.lsu_axi.b.valid @[quasar.scala 286:14] + io.lsu_axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 286:14] + io.lsu_axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 286:14] + io.lsu_axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 286:14] + io.lsu_axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 286:14] + io.lsu_axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 286:14] + lsu.io.axi.w.ready <= io.lsu_axi.w.ready @[quasar.scala 286:14] + io.lsu_axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 286:14] + io.lsu_axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 286:14] + io.lsu_axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 286:14] + io.lsu_axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 286:14] + io.lsu_axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 286:14] + io.lsu_axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 286:14] + io.lsu_axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 286:14] + io.lsu_axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 286:14] + io.lsu_axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 286:14] + io.lsu_axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 286:14] + io.lsu_axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 286:14] + lsu.io.axi.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 286:14] + ifu.io.ifu.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 289:14] + ifu.io.ifu.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 289:14] + ifu.io.ifu.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 289:14] + ifu.io.ifu.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 289:14] + ifu.io.ifu.r.valid <= io.ifu_axi.r.valid @[quasar.scala 289:14] + io.ifu_axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 289:14] + io.ifu_axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 289:14] + io.ifu_axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 289:14] + io.ifu_axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 289:14] + io.ifu_axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 289:14] + io.ifu_axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 289:14] + io.ifu_axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 289:14] + io.ifu_axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 289:14] + io.ifu_axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 289:14] + io.ifu_axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 289:14] + io.ifu_axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 289:14] + io.ifu_axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 289:14] + ifu.io.ifu.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 289:14] + ifu.io.ifu.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 289:14] + ifu.io.ifu.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 289:14] + ifu.io.ifu.b.valid <= io.ifu_axi.b.valid @[quasar.scala 289:14] + io.ifu_axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 289:14] + io.ifu_axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 289:14] + io.ifu_axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 289:14] + io.ifu_axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 289:14] + io.ifu_axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 289:14] + ifu.io.ifu.w.ready <= io.ifu_axi.w.ready @[quasar.scala 289:14] + io.ifu_axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 289:14] + io.ifu_axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 289:14] + io.ifu_axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 289:14] + io.ifu_axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 289:14] + io.ifu_axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 289:14] + io.ifu_axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 289:14] + io.ifu_axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 289:14] + io.ifu_axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 289:14] + io.ifu_axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 289:14] + io.ifu_axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 289:14] + io.ifu_axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 289:14] + ifu.io.ifu.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 289:14] + io.dma_axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 290:14] + io.dma_axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 290:14] + io.dma_axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 290:14] + io.dma_axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 290:14] + io.dma_axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 290:14] + io.dma_axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 290:14] + io.dma_axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 290:14] + io.dma_axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 290:14] + io.dma_axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar.scala 290:14] + io.dma_axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 290:14] + dma_ctrl.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 290:14] + io.dma_axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 290:14] + when UInt<1>("h01") : @[quasar.scala 296:26] + inst axi4_to_ahb of axi4_to_ahb @[quasar.scala 297:33] axi4_to_ahb.clock <= clock axi4_to_ahb.reset <= reset - axi4_to_ahb.io.axi_awvalid <= io.lsu_axi.aw.valid @[quasar.scala 319:36] - axi4_to_ahb.io.scan_mode <= io.scan_mode @[quasar.scala 320:34] - axi4_to_ahb.io.bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 321:35] - axi4_to_ahb.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 322:37] - axi4_to_ahb.io.axi_awid <= io.lsu_axi.aw.bits.id @[quasar.scala 323:33] - axi4_to_ahb.io.axi_awaddr <= io.lsu_axi.aw.bits.addr @[quasar.scala 324:35] - axi4_to_ahb.io.axi_awsize <= io.lsu_axi.aw.bits.size @[quasar.scala 325:35] - axi4_to_ahb.io.axi_awprot <= io.lsu_axi.aw.bits.prot @[quasar.scala 326:35] - axi4_to_ahb.io.axi_wvalid <= io.lsu_axi.w.valid @[quasar.scala 328:35] - axi4_to_ahb.io.axi_wdata <= io.lsu_axi.w.bits.data @[quasar.scala 329:34] - axi4_to_ahb.io.axi_wstrb <= io.lsu_axi.w.bits.strb @[quasar.scala 330:34] - axi4_to_ahb.io.axi_wlast <= io.lsu_axi.w.bits.last @[quasar.scala 331:34] - axi4_to_ahb.io.axi_bready <= io.lsu_axi.b.ready @[quasar.scala 332:35] - axi4_to_ahb.io.axi_arvalid <= io.lsu_axi.ar.valid @[quasar.scala 334:36] - axi4_to_ahb.io.axi_arid <= io.lsu_axi.ar.bits.id @[quasar.scala 335:33] - axi4_to_ahb.io.axi_araddr <= io.lsu_axi.ar.bits.addr @[quasar.scala 336:35] - axi4_to_ahb.io.axi_arsize <= io.lsu_axi.ar.bits.size @[quasar.scala 337:35] - axi4_to_ahb.io.axi_arprot <= io.lsu_axi.ar.bits.prot @[quasar.scala 338:35] - axi4_to_ahb.io.axi_rready <= io.lsu_axi.r.ready @[quasar.scala 340:35] - axi4_to_ahb.io.ahb_hrdata <= io.lsu_hrdata @[quasar.scala 341:35] - axi4_to_ahb.io.ahb_hready <= io.lsu_hready @[quasar.scala 342:35] - axi4_to_ahb.io.ahb_hresp <= io.lsu_hresp @[quasar.scala 343:34] - inst axi4_to_ahb_1 of axi4_to_ahb_1 @[quasar.scala 345:33] + axi4_to_ahb.io.axi_awvalid <= io.lsu_axi.aw.valid @[quasar.scala 298:36] + axi4_to_ahb.io.scan_mode <= io.scan_mode @[quasar.scala 299:34] + axi4_to_ahb.io.bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 300:35] + axi4_to_ahb.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 301:37] + axi4_to_ahb.io.axi_awid <= io.lsu_axi.aw.bits.id @[quasar.scala 302:33] + axi4_to_ahb.io.axi_awaddr <= io.lsu_axi.aw.bits.addr @[quasar.scala 303:35] + axi4_to_ahb.io.axi_awsize <= io.lsu_axi.aw.bits.size @[quasar.scala 304:35] + axi4_to_ahb.io.axi_awprot <= io.lsu_axi.aw.bits.prot @[quasar.scala 305:35] + axi4_to_ahb.io.axi_wvalid <= io.lsu_axi.w.valid @[quasar.scala 307:35] + axi4_to_ahb.io.axi_wdata <= io.lsu_axi.w.bits.data @[quasar.scala 308:34] + axi4_to_ahb.io.axi_wstrb <= io.lsu_axi.w.bits.strb @[quasar.scala 309:34] + axi4_to_ahb.io.axi_wlast <= io.lsu_axi.w.bits.last @[quasar.scala 310:34] + axi4_to_ahb.io.axi_bready <= io.lsu_axi.b.ready @[quasar.scala 311:35] + axi4_to_ahb.io.axi_arvalid <= io.lsu_axi.ar.valid @[quasar.scala 313:36] + axi4_to_ahb.io.axi_arid <= io.lsu_axi.ar.bits.id @[quasar.scala 314:33] + axi4_to_ahb.io.axi_araddr <= io.lsu_axi.ar.bits.addr @[quasar.scala 315:35] + axi4_to_ahb.io.axi_arsize <= io.lsu_axi.ar.bits.size @[quasar.scala 316:35] + axi4_to_ahb.io.axi_arprot <= io.lsu_axi.ar.bits.prot @[quasar.scala 317:35] + axi4_to_ahb.io.axi_rready <= io.lsu_axi.r.ready @[quasar.scala 319:35] + axi4_to_ahb.io.ahb_hrdata <= io.lsu_hrdata @[quasar.scala 320:35] + axi4_to_ahb.io.ahb_hready <= io.lsu_hready @[quasar.scala 321:35] + axi4_to_ahb.io.ahb_hresp <= io.lsu_hresp @[quasar.scala 322:34] + inst axi4_to_ahb_1 of axi4_to_ahb_1 @[quasar.scala 324:33] axi4_to_ahb_1.clock <= clock axi4_to_ahb_1.reset <= reset - axi4_to_ahb_1.io.axi_awvalid <= io.ifu_axi.aw.valid @[quasar.scala 346:36] - axi4_to_ahb_1.io.scan_mode <= io.scan_mode @[quasar.scala 347:34] - axi4_to_ahb_1.io.bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 348:35] - axi4_to_ahb_1.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 349:37] - axi4_to_ahb_1.io.axi_awid <= io.ifu_axi.aw.bits.id @[quasar.scala 350:33] - axi4_to_ahb_1.io.axi_awaddr <= io.ifu_axi.aw.bits.addr @[quasar.scala 351:35] - axi4_to_ahb_1.io.axi_awsize <= io.ifu_axi.aw.bits.size @[quasar.scala 352:35] - axi4_to_ahb_1.io.axi_awprot <= io.ifu_axi.aw.bits.prot @[quasar.scala 353:35] - axi4_to_ahb_1.io.axi_wvalid <= io.ifu_axi.w.valid @[quasar.scala 355:35] - axi4_to_ahb_1.io.axi_wdata <= io.ifu_axi.w.bits.data @[quasar.scala 356:34] - axi4_to_ahb_1.io.axi_wstrb <= io.ifu_axi.w.bits.strb @[quasar.scala 357:34] - axi4_to_ahb_1.io.axi_wlast <= io.ifu_axi.w.bits.last @[quasar.scala 358:34] - axi4_to_ahb_1.io.axi_bready <= io.ifu_axi.b.ready @[quasar.scala 359:35] - axi4_to_ahb_1.io.axi_arvalid <= io.ifu_axi.ar.valid @[quasar.scala 361:36] - axi4_to_ahb_1.io.axi_arid <= io.ifu_axi.ar.bits.id @[quasar.scala 362:33] - axi4_to_ahb_1.io.axi_araddr <= io.ifu_axi.ar.bits.addr @[quasar.scala 363:35] - axi4_to_ahb_1.io.axi_arsize <= io.ifu_axi.ar.bits.size @[quasar.scala 364:35] - axi4_to_ahb_1.io.axi_arprot <= io.ifu_axi.ar.bits.prot @[quasar.scala 365:35] - axi4_to_ahb_1.io.axi_rready <= io.ifu_axi.r.ready @[quasar.scala 367:35] - axi4_to_ahb_1.io.ahb_hrdata <= io.hrdata @[quasar.scala 369:35] - axi4_to_ahb_1.io.ahb_hready <= io.hready @[quasar.scala 370:35] - axi4_to_ahb_1.io.ahb_hresp <= io.hresp @[quasar.scala 371:34] - inst axi4_to_ahb_2 of axi4_to_ahb_2 @[quasar.scala 373:32] + axi4_to_ahb_1.io.axi_awvalid <= io.ifu_axi.aw.valid @[quasar.scala 325:36] + axi4_to_ahb_1.io.scan_mode <= io.scan_mode @[quasar.scala 326:34] + axi4_to_ahb_1.io.bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 327:35] + axi4_to_ahb_1.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 328:37] + axi4_to_ahb_1.io.axi_awid <= io.ifu_axi.aw.bits.id @[quasar.scala 329:33] + axi4_to_ahb_1.io.axi_awaddr <= io.ifu_axi.aw.bits.addr @[quasar.scala 330:35] + axi4_to_ahb_1.io.axi_awsize <= io.ifu_axi.aw.bits.size @[quasar.scala 331:35] + axi4_to_ahb_1.io.axi_awprot <= io.ifu_axi.aw.bits.prot @[quasar.scala 332:35] + axi4_to_ahb_1.io.axi_wvalid <= io.ifu_axi.w.valid @[quasar.scala 334:35] + axi4_to_ahb_1.io.axi_wdata <= io.ifu_axi.w.bits.data @[quasar.scala 335:34] + axi4_to_ahb_1.io.axi_wstrb <= io.ifu_axi.w.bits.strb @[quasar.scala 336:34] + axi4_to_ahb_1.io.axi_wlast <= io.ifu_axi.w.bits.last @[quasar.scala 337:34] + axi4_to_ahb_1.io.axi_bready <= io.ifu_axi.b.ready @[quasar.scala 338:35] + axi4_to_ahb_1.io.axi_arvalid <= io.ifu_axi.ar.valid @[quasar.scala 340:36] + axi4_to_ahb_1.io.axi_arid <= io.ifu_axi.ar.bits.id @[quasar.scala 341:33] + axi4_to_ahb_1.io.axi_araddr <= io.ifu_axi.ar.bits.addr @[quasar.scala 342:35] + axi4_to_ahb_1.io.axi_arsize <= io.ifu_axi.ar.bits.size @[quasar.scala 343:35] + axi4_to_ahb_1.io.axi_arprot <= io.ifu_axi.ar.bits.prot @[quasar.scala 344:35] + axi4_to_ahb_1.io.axi_rready <= io.ifu_axi.r.ready @[quasar.scala 346:35] + axi4_to_ahb_1.io.ahb_hrdata <= io.hrdata @[quasar.scala 348:35] + axi4_to_ahb_1.io.ahb_hready <= io.hready @[quasar.scala 349:35] + axi4_to_ahb_1.io.ahb_hresp <= io.hresp @[quasar.scala 350:34] + inst axi4_to_ahb_2 of axi4_to_ahb_2 @[quasar.scala 352:32] axi4_to_ahb_2.clock <= clock axi4_to_ahb_2.reset <= reset - axi4_to_ahb_2.io.axi_awvalid <= io.sb_axi.aw.valid @[quasar.scala 374:35] - axi4_to_ahb_2.io.scan_mode <= io.scan_mode @[quasar.scala 375:33] - axi4_to_ahb_2.io.bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 376:34] - axi4_to_ahb_2.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 377:36] - axi4_to_ahb_2.io.axi_awid <= io.sb_axi.aw.bits.id @[quasar.scala 378:32] - axi4_to_ahb_2.io.axi_awaddr <= io.sb_axi.aw.bits.addr @[quasar.scala 379:34] - axi4_to_ahb_2.io.axi_awsize <= io.sb_axi.aw.bits.size @[quasar.scala 380:34] - axi4_to_ahb_2.io.axi_awprot <= io.sb_axi.aw.bits.prot @[quasar.scala 381:34] - axi4_to_ahb_2.io.axi_wvalid <= io.sb_axi.w.valid @[quasar.scala 383:34] - axi4_to_ahb_2.io.axi_wdata <= io.sb_axi.w.bits.data @[quasar.scala 384:33] - axi4_to_ahb_2.io.axi_wstrb <= io.sb_axi.w.bits.strb @[quasar.scala 385:33] - axi4_to_ahb_2.io.axi_wlast <= io.sb_axi.w.bits.last @[quasar.scala 386:33] - axi4_to_ahb_2.io.axi_bready <= io.sb_axi.b.ready @[quasar.scala 387:34] - axi4_to_ahb_2.io.axi_arvalid <= io.sb_axi.ar.valid @[quasar.scala 389:35] - axi4_to_ahb_2.io.axi_arid <= io.sb_axi.ar.bits.id @[quasar.scala 390:32] - axi4_to_ahb_2.io.axi_araddr <= io.sb_axi.ar.bits.addr @[quasar.scala 391:34] - axi4_to_ahb_2.io.axi_arsize <= io.sb_axi.ar.bits.size @[quasar.scala 392:34] - axi4_to_ahb_2.io.axi_arprot <= io.sb_axi.ar.bits.prot @[quasar.scala 393:34] - axi4_to_ahb_2.io.axi_rready <= io.sb_axi.r.ready @[quasar.scala 395:34] - axi4_to_ahb_2.io.ahb_hrdata <= io.sb_hrdata @[quasar.scala 396:34] - axi4_to_ahb_2.io.ahb_hready <= io.sb_hready @[quasar.scala 397:34] - axi4_to_ahb_2.io.ahb_hresp <= io.sb_hresp @[quasar.scala 398:33] - inst ahb_to_axi4 of ahb_to_axi4 @[quasar.scala 400:33] + axi4_to_ahb_2.io.axi_awvalid <= io.sb_axi.aw.valid @[quasar.scala 353:35] + axi4_to_ahb_2.io.scan_mode <= io.scan_mode @[quasar.scala 354:33] + axi4_to_ahb_2.io.bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 355:34] + axi4_to_ahb_2.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 356:36] + axi4_to_ahb_2.io.axi_awid <= io.sb_axi.aw.bits.id @[quasar.scala 357:32] + axi4_to_ahb_2.io.axi_awaddr <= io.sb_axi.aw.bits.addr @[quasar.scala 358:34] + axi4_to_ahb_2.io.axi_awsize <= io.sb_axi.aw.bits.size @[quasar.scala 359:34] + axi4_to_ahb_2.io.axi_awprot <= io.sb_axi.aw.bits.prot @[quasar.scala 360:34] + axi4_to_ahb_2.io.axi_wvalid <= io.sb_axi.w.valid @[quasar.scala 362:34] + axi4_to_ahb_2.io.axi_wdata <= io.sb_axi.w.bits.data @[quasar.scala 363:33] + axi4_to_ahb_2.io.axi_wstrb <= io.sb_axi.w.bits.strb @[quasar.scala 364:33] + axi4_to_ahb_2.io.axi_wlast <= io.sb_axi.w.bits.last @[quasar.scala 365:33] + axi4_to_ahb_2.io.axi_bready <= io.sb_axi.b.ready @[quasar.scala 366:34] + axi4_to_ahb_2.io.axi_arvalid <= io.sb_axi.ar.valid @[quasar.scala 368:35] + axi4_to_ahb_2.io.axi_arid <= io.sb_axi.ar.bits.id @[quasar.scala 369:32] + axi4_to_ahb_2.io.axi_araddr <= io.sb_axi.ar.bits.addr @[quasar.scala 370:34] + axi4_to_ahb_2.io.axi_arsize <= io.sb_axi.ar.bits.size @[quasar.scala 371:34] + axi4_to_ahb_2.io.axi_arprot <= io.sb_axi.ar.bits.prot @[quasar.scala 372:34] + axi4_to_ahb_2.io.axi_rready <= io.sb_axi.r.ready @[quasar.scala 374:34] + axi4_to_ahb_2.io.ahb_hrdata <= io.sb_hrdata @[quasar.scala 375:34] + axi4_to_ahb_2.io.ahb_hready <= io.sb_hready @[quasar.scala 376:34] + axi4_to_ahb_2.io.ahb_hresp <= io.sb_hresp @[quasar.scala 377:33] + inst ahb_to_axi4 of ahb_to_axi4 @[quasar.scala 379:33] ahb_to_axi4.clock <= clock ahb_to_axi4.reset <= reset - ahb_to_axi4.io.scan_mode <= io.scan_mode @[quasar.scala 401:34] - ahb_to_axi4.io.bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 402:35] - ahb_to_axi4.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 403:37] - ahb_to_axi4.io.axi_awready <= io.dma_axi.aw.ready @[quasar.scala 404:36] - ahb_to_axi4.io.axi_wready <= io.dma_axi.w.ready @[quasar.scala 405:35] - ahb_to_axi4.io.axi_bvalid <= io.dma_axi.b.valid @[quasar.scala 406:35] - ahb_to_axi4.io.axi_bresp <= io.dma_axi.b.bits.resp @[quasar.scala 407:34] - ahb_to_axi4.io.axi_bid <= io.dma_axi.b.bits.id @[quasar.scala 408:32] - ahb_to_axi4.io.axi_arready <= io.dma_axi.ar.ready @[quasar.scala 411:36] - ahb_to_axi4.io.axi_rvalid <= io.dma_axi.ar.valid @[quasar.scala 412:35] - ahb_to_axi4.io.axi_rid <= io.dma_axi.r.bits.id @[quasar.scala 413:32] - ahb_to_axi4.io.axi_rdata <= io.dma_axi.r.bits.data @[quasar.scala 414:34] - ahb_to_axi4.io.axi_rresp <= io.dma_axi.r.bits.resp @[quasar.scala 415:34] - ahb_to_axi4.io.ahb_haddr <= io.dma_haddr @[quasar.scala 418:34] - ahb_to_axi4.io.ahb_hburst <= io.dma_hburst @[quasar.scala 419:35] - ahb_to_axi4.io.ahb_hmastlock <= io.dma_hmastlock @[quasar.scala 420:38] - ahb_to_axi4.io.ahb_hprot <= io.dma_hprot @[quasar.scala 421:34] - ahb_to_axi4.io.ahb_hsize <= io.dma_hsize @[quasar.scala 422:34] - ahb_to_axi4.io.ahb_htrans <= io.dma_htrans @[quasar.scala 423:35] - ahb_to_axi4.io.ahb_hwrite <= io.dma_hwrite @[quasar.scala 424:35] - ahb_to_axi4.io.ahb_hwdata <= io.dma_hwdata @[quasar.scala 425:35] - ahb_to_axi4.io.ahb_hsel <= io.dma_hsel @[quasar.scala 426:33] - ahb_to_axi4.io.ahb_hreadyin <= io.dma_hreadyin @[quasar.scala 427:37] - node _T_12 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_awready, io.lsu_axi.aw.ready) @[quasar.scala 428:31] - lsu.io.axi.aw.ready <= _T_12 @[quasar.scala 428:25] - node _T_13 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_wready, io.lsu_axi.w.ready) @[quasar.scala 429:30] - lsu.io.axi.w.ready <= _T_13 @[quasar.scala 429:24] - node _T_14 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bvalid, io.lsu_axi.b.valid) @[quasar.scala 430:30] - lsu.io.axi.b.valid <= _T_14 @[quasar.scala 430:24] - node _T_15 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bresp, io.lsu_axi.b.bits.resp) @[quasar.scala 431:34] - lsu.io.axi.b.bits.resp <= _T_15 @[quasar.scala 431:28] - node _T_16 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_bid, io.lsu_axi.b.bits.id) @[quasar.scala 432:32] - lsu.io.axi.b.bits.id <= _T_16 @[quasar.scala 432:26] - node _T_17 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_arready, io.lsu_axi.ar.ready) @[quasar.scala 433:31] - lsu.io.axi.ar.ready <= _T_17 @[quasar.scala 433:25] - node _T_18 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rvalid, io.lsu_axi.r.valid) @[quasar.scala 434:30] - lsu.io.axi.r.valid <= _T_18 @[quasar.scala 434:24] - node _T_19 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rid, io.lsu_axi.r.bits.id) @[quasar.scala 435:32] - lsu.io.axi.r.bits.id <= _T_19 @[quasar.scala 435:26] - node _T_20 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rdata, io.lsu_axi.r.bits.data) @[quasar.scala 436:34] - lsu.io.axi.r.bits.data <= _T_20 @[quasar.scala 436:28] - node _T_21 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rresp, io.lsu_axi.r.bits.resp) @[quasar.scala 437:34] - lsu.io.axi.r.bits.resp <= _T_21 @[quasar.scala 437:28] - node _T_22 = mux(UInt<1>("h00"), axi4_to_ahb.io.axi_rlast, io.lsu_axi.r.bits.last) @[quasar.scala 438:34] - lsu.io.axi.r.bits.last <= _T_22 @[quasar.scala 438:28] - node _T_23 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_awready, io.ifu_axi.aw.ready) @[quasar.scala 440:31] - ifu.io.ifu.aw.ready <= _T_23 @[quasar.scala 440:25] - node _T_24 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_wready, io.ifu_axi.w.ready) @[quasar.scala 441:30] - ifu.io.ifu.w.ready <= _T_24 @[quasar.scala 441:24] - node _T_25 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_arready, io.ifu_axi.ar.ready) @[quasar.scala 442:31] - ifu.io.ifu.ar.ready <= _T_25 @[quasar.scala 442:25] - node _T_26 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rvalid, io.ifu_axi.r.valid) @[quasar.scala 443:30] - ifu.io.ifu.r.valid <= _T_26 @[quasar.scala 443:24] - node _T_27 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rid, io.ifu_axi.r.bits.id) @[quasar.scala 444:32] - ifu.io.ifu.r.bits.id <= _T_27 @[quasar.scala 444:26] - node _T_28 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rdata, io.ifu_axi.r.bits.data) @[quasar.scala 445:34] - ifu.io.ifu.r.bits.data <= _T_28 @[quasar.scala 445:28] - node _T_29 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rresp, io.ifu_axi.r.bits.resp) @[quasar.scala 446:34] - ifu.io.ifu.r.bits.resp <= _T_29 @[quasar.scala 446:28] - node _T_30 = mux(UInt<1>("h00"), axi4_to_ahb_1.io.axi_rlast, io.ifu_axi.r.bits.last) @[quasar.scala 447:34] - ifu.io.ifu.r.bits.last <= _T_30 @[quasar.scala 447:28] - node _T_31 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_awready, io.sb_axi.aw.ready) @[quasar.scala 449:34] - dbg.io.sb_axi.aw.ready <= _T_31 @[quasar.scala 449:28] - node _T_32 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_wready, io.sb_axi.w.ready) @[quasar.scala 450:33] - dbg.io.sb_axi.w.ready <= _T_32 @[quasar.scala 450:27] - node _T_33 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_bvalid, io.sb_axi.b.valid) @[quasar.scala 451:33] - dbg.io.sb_axi.b.valid <= _T_33 @[quasar.scala 451:27] - node _T_34 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_bresp, io.sb_axi.b.bits.resp) @[quasar.scala 452:37] - dbg.io.sb_axi.b.bits.resp <= _T_34 @[quasar.scala 452:31] - node _T_35 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_arready, io.sb_axi.ar.ready) @[quasar.scala 453:34] - dbg.io.sb_axi.ar.ready <= _T_35 @[quasar.scala 453:28] - node _T_36 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rvalid, io.sb_axi.r.valid) @[quasar.scala 454:33] - dbg.io.sb_axi.r.valid <= _T_36 @[quasar.scala 454:27] - node _T_37 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rid, io.sb_axi.r.bits.id) @[quasar.scala 455:35] - dbg.io.sb_axi.r.bits.id <= _T_37 @[quasar.scala 455:29] - node _T_38 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rdata, io.sb_axi.r.bits.data) @[quasar.scala 456:37] - dbg.io.sb_axi.r.bits.data <= _T_38 @[quasar.scala 456:31] - node _T_39 = mux(UInt<1>("h00"), axi4_to_ahb_2.io.axi_rresp, io.sb_axi.r.bits.resp) @[quasar.scala 457:37] - dbg.io.sb_axi.r.bits.resp <= _T_39 @[quasar.scala 457:31] - node _T_40 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awvalid, io.dma_axi.aw.valid) @[quasar.scala 459:40] - dma_ctrl.io.dma_axi.aw.valid <= _T_40 @[quasar.scala 459:34] - node _T_41 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awid, io.dma_axi.aw.bits.id) @[quasar.scala 460:42] - dma_ctrl.io.dma_axi.aw.bits.id <= _T_41 @[quasar.scala 460:36] - node _T_42 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awaddr, io.dma_axi.aw.bits.addr) @[quasar.scala 461:44] - dma_ctrl.io.dma_axi.aw.bits.addr <= _T_42 @[quasar.scala 461:38] - node _T_43 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_awsize, io.dma_axi.aw.bits.size) @[quasar.scala 462:44] - dma_ctrl.io.dma_axi.aw.bits.size <= _T_43 @[quasar.scala 462:38] - node _T_44 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wvalid, io.dma_axi.w.valid) @[quasar.scala 463:39] - dma_ctrl.io.dma_axi.w.valid <= _T_44 @[quasar.scala 463:33] - node _T_45 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wdata, io.dma_axi.w.bits.data) @[quasar.scala 464:43] - dma_ctrl.io.dma_axi.w.bits.data <= _T_45 @[quasar.scala 464:37] - node _T_46 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_wstrb, io.dma_axi.w.bits.strb) @[quasar.scala 465:43] - dma_ctrl.io.dma_axi.w.bits.strb <= _T_46 @[quasar.scala 465:37] - node _T_47 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_bready, io.dma_axi.b.ready) @[quasar.scala 466:39] - dma_ctrl.io.dma_axi.b.ready <= _T_47 @[quasar.scala 466:33] - node _T_48 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arvalid, io.dma_axi.ar.valid) @[quasar.scala 467:40] - dma_ctrl.io.dma_axi.ar.valid <= _T_48 @[quasar.scala 467:34] - node _T_49 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arid, io.dma_axi.ar.bits.id) @[quasar.scala 468:42] - dma_ctrl.io.dma_axi.ar.bits.id <= _T_49 @[quasar.scala 468:36] - node _T_50 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_araddr, io.dma_axi.aw.bits.addr) @[quasar.scala 469:44] - dma_ctrl.io.dma_axi.ar.bits.addr <= _T_50 @[quasar.scala 469:38] - node _T_51 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_arsize, io.dma_axi.aw.bits.size) @[quasar.scala 470:44] - dma_ctrl.io.dma_axi.ar.bits.size <= _T_51 @[quasar.scala 470:38] - node _T_52 = mux(UInt<1>("h00"), ahb_to_axi4.io.axi_rready, io.dma_axi.r.ready) @[quasar.scala 471:39] - dma_ctrl.io.dma_axi.r.ready <= _T_52 @[quasar.scala 471:33] - io.haddr <= axi4_to_ahb_1.io.ahb_haddr @[quasar.scala 473:14] - io.hburst <= axi4_to_ahb_1.io.ahb_hburst @[quasar.scala 474:15] - io.hmastlock <= axi4_to_ahb_1.io.ahb_hmastlock @[quasar.scala 475:18] - io.hprot <= axi4_to_ahb_1.io.ahb_hprot @[quasar.scala 476:14] - io.hsize <= axi4_to_ahb_1.io.ahb_hsize @[quasar.scala 477:14] - io.htrans <= axi4_to_ahb_1.io.ahb_htrans @[quasar.scala 478:15] - io.hwrite <= axi4_to_ahb_1.io.ahb_hwrite @[quasar.scala 479:15] - io.lsu_haddr <= axi4_to_ahb.io.ahb_haddr @[quasar.scala 482:18] - io.lsu_hburst <= axi4_to_ahb.io.ahb_hburst @[quasar.scala 483:19] - io.lsu_hmastlock <= axi4_to_ahb.io.ahb_hmastlock @[quasar.scala 484:22] - io.lsu_hprot <= axi4_to_ahb.io.ahb_hprot @[quasar.scala 485:18] - io.lsu_hsize <= axi4_to_ahb.io.ahb_hsize @[quasar.scala 486:18] - io.lsu_htrans <= axi4_to_ahb.io.ahb_htrans @[quasar.scala 487:19] - io.lsu_hwrite <= axi4_to_ahb.io.ahb_hwrite @[quasar.scala 488:19] - io.lsu_hwdata <= axi4_to_ahb.io.ahb_hwdata @[quasar.scala 489:19] - io.sb_haddr <= axi4_to_ahb_2.io.ahb_haddr @[quasar.scala 491:17] - io.sb_hburst <= axi4_to_ahb_2.io.ahb_hburst @[quasar.scala 492:18] - io.sb_hmastlock <= axi4_to_ahb_2.io.ahb_hmastlock @[quasar.scala 493:21] - io.sb_hprot <= axi4_to_ahb_2.io.ahb_hprot @[quasar.scala 494:17] - io.sb_hsize <= axi4_to_ahb_2.io.ahb_hsize @[quasar.scala 495:17] - io.sb_htrans <= axi4_to_ahb_2.io.ahb_htrans @[quasar.scala 496:18] - io.sb_hwrite <= axi4_to_ahb_2.io.ahb_hwrite @[quasar.scala 497:18] - io.sb_hwdata <= axi4_to_ahb_2.io.ahb_hwdata @[quasar.scala 498:18] - io.dma_hrdata <= ahb_to_axi4.io.ahb_hrdata @[quasar.scala 500:19] - io.dma_hreadyout <= ahb_to_axi4.io.ahb_hreadyout @[quasar.scala 501:22] - io.dma_hresp <= ahb_to_axi4.io.ahb_hresp @[quasar.scala 502:18] - skip @[quasar.scala 317:26] - else : @[quasar.scala 506:17] - io.haddr <= UInt<1>("h00") @[quasar.scala 508:18] - io.hburst <= UInt<1>("h00") @[quasar.scala 509:19] - io.hmastlock <= UInt<1>("h00") @[quasar.scala 510:22] - io.hprot <= UInt<1>("h00") @[quasar.scala 511:18] - io.hsize <= UInt<1>("h00") @[quasar.scala 512:18] - io.htrans <= UInt<1>("h00") @[quasar.scala 513:19] - io.hwrite <= UInt<1>("h00") @[quasar.scala 514:19] - io.lsu_haddr <= UInt<1>("h00") @[quasar.scala 517:22] - io.lsu_hburst <= UInt<1>("h00") @[quasar.scala 518:23] - io.lsu_hmastlock <= UInt<1>("h00") @[quasar.scala 519:26] - io.lsu_hprot <= UInt<1>("h00") @[quasar.scala 520:22] - io.lsu_hsize <= UInt<1>("h00") @[quasar.scala 521:22] - io.lsu_htrans <= UInt<1>("h00") @[quasar.scala 522:23] - io.lsu_hwrite <= UInt<1>("h00") @[quasar.scala 523:23] - io.lsu_hwdata <= UInt<1>("h00") @[quasar.scala 524:23] - io.sb_haddr <= UInt<1>("h00") @[quasar.scala 526:21] - io.sb_hburst <= UInt<1>("h00") @[quasar.scala 527:22] - io.sb_hmastlock <= UInt<1>("h00") @[quasar.scala 528:25] - io.sb_hprot <= UInt<1>("h00") @[quasar.scala 529:21] - io.sb_hsize <= UInt<1>("h00") @[quasar.scala 530:21] - io.sb_htrans <= UInt<1>("h00") @[quasar.scala 531:22] - io.sb_hwrite <= UInt<1>("h00") @[quasar.scala 532:22] - io.sb_hwdata <= UInt<1>("h00") @[quasar.scala 533:22] - io.dma_hrdata <= UInt<1>("h00") @[quasar.scala 535:23] - io.dma_hreadyout <= UInt<1>("h00") @[quasar.scala 536:26] - io.dma_hresp <= UInt<1>("h00") @[quasar.scala 537:22] - skip @[quasar.scala 506:17] - io.dmi_reg_rdata <= UInt<1>("h00") @[quasar.scala 539:20] + ahb_to_axi4.io.scan_mode <= io.scan_mode @[quasar.scala 380:34] + ahb_to_axi4.io.bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 381:35] + ahb_to_axi4.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 382:37] + ahb_to_axi4.io.axi_awready <= io.dma_axi.aw.ready @[quasar.scala 383:36] + ahb_to_axi4.io.axi_wready <= io.dma_axi.w.ready @[quasar.scala 384:35] + ahb_to_axi4.io.axi_bvalid <= io.dma_axi.b.valid @[quasar.scala 385:35] + ahb_to_axi4.io.axi_bresp <= io.dma_axi.b.bits.resp @[quasar.scala 386:34] + ahb_to_axi4.io.axi_bid <= io.dma_axi.b.bits.id @[quasar.scala 387:32] + ahb_to_axi4.io.axi_arready <= io.dma_axi.ar.ready @[quasar.scala 390:36] + ahb_to_axi4.io.axi_rvalid <= io.dma_axi.ar.valid @[quasar.scala 391:35] + ahb_to_axi4.io.axi_rid <= io.dma_axi.r.bits.id @[quasar.scala 392:32] + ahb_to_axi4.io.axi_rdata <= io.dma_axi.r.bits.data @[quasar.scala 393:34] + ahb_to_axi4.io.axi_rresp <= io.dma_axi.r.bits.resp @[quasar.scala 394:34] + ahb_to_axi4.io.ahb_haddr <= io.dma_haddr @[quasar.scala 397:34] + ahb_to_axi4.io.ahb_hburst <= io.dma_hburst @[quasar.scala 398:35] + ahb_to_axi4.io.ahb_hmastlock <= io.dma_hmastlock @[quasar.scala 399:38] + ahb_to_axi4.io.ahb_hprot <= io.dma_hprot @[quasar.scala 400:34] + ahb_to_axi4.io.ahb_hsize <= io.dma_hsize @[quasar.scala 401:34] + ahb_to_axi4.io.ahb_htrans <= io.dma_htrans @[quasar.scala 402:35] + ahb_to_axi4.io.ahb_hwrite <= io.dma_hwrite @[quasar.scala 403:35] + ahb_to_axi4.io.ahb_hwdata <= io.dma_hwdata @[quasar.scala 404:35] + ahb_to_axi4.io.ahb_hsel <= io.dma_hsel @[quasar.scala 405:33] + ahb_to_axi4.io.ahb_hreadyin <= io.dma_hreadyin @[quasar.scala 406:37] + node _T_12 = mux(UInt<1>("h01"), axi4_to_ahb.io.axi_awready, io.lsu_axi.aw.ready) @[quasar.scala 407:31] + lsu.io.axi.aw.ready <= _T_12 @[quasar.scala 407:25] + node _T_13 = mux(UInt<1>("h01"), axi4_to_ahb.io.axi_wready, io.lsu_axi.w.ready) @[quasar.scala 408:30] + lsu.io.axi.w.ready <= _T_13 @[quasar.scala 408:24] + node _T_14 = mux(UInt<1>("h01"), axi4_to_ahb.io.axi_bvalid, io.lsu_axi.b.valid) @[quasar.scala 409:30] + lsu.io.axi.b.valid <= _T_14 @[quasar.scala 409:24] + node _T_15 = mux(UInt<1>("h01"), axi4_to_ahb.io.axi_bresp, io.lsu_axi.b.bits.resp) @[quasar.scala 410:34] + lsu.io.axi.b.bits.resp <= _T_15 @[quasar.scala 410:28] + node _T_16 = mux(UInt<1>("h01"), axi4_to_ahb.io.axi_bid, io.lsu_axi.b.bits.id) @[quasar.scala 411:32] + lsu.io.axi.b.bits.id <= _T_16 @[quasar.scala 411:26] + node _T_17 = mux(UInt<1>("h01"), axi4_to_ahb.io.axi_arready, io.lsu_axi.ar.ready) @[quasar.scala 412:31] + lsu.io.axi.ar.ready <= _T_17 @[quasar.scala 412:25] + node _T_18 = mux(UInt<1>("h01"), axi4_to_ahb.io.axi_rvalid, io.lsu_axi.r.valid) @[quasar.scala 413:30] + lsu.io.axi.r.valid <= _T_18 @[quasar.scala 413:24] + node _T_19 = mux(UInt<1>("h01"), axi4_to_ahb.io.axi_rid, io.lsu_axi.r.bits.id) @[quasar.scala 414:32] + lsu.io.axi.r.bits.id <= _T_19 @[quasar.scala 414:26] + node _T_20 = mux(UInt<1>("h01"), axi4_to_ahb.io.axi_rdata, io.lsu_axi.r.bits.data) @[quasar.scala 415:34] + lsu.io.axi.r.bits.data <= _T_20 @[quasar.scala 415:28] + node _T_21 = mux(UInt<1>("h01"), axi4_to_ahb.io.axi_rresp, io.lsu_axi.r.bits.resp) @[quasar.scala 416:34] + lsu.io.axi.r.bits.resp <= _T_21 @[quasar.scala 416:28] + node _T_22 = mux(UInt<1>("h01"), axi4_to_ahb.io.axi_rlast, io.lsu_axi.r.bits.last) @[quasar.scala 417:34] + lsu.io.axi.r.bits.last <= _T_22 @[quasar.scala 417:28] + node _T_23 = mux(UInt<1>("h01"), axi4_to_ahb_1.io.axi_awready, io.ifu_axi.aw.ready) @[quasar.scala 419:31] + ifu.io.ifu.aw.ready <= _T_23 @[quasar.scala 419:25] + node _T_24 = mux(UInt<1>("h01"), axi4_to_ahb_1.io.axi_wready, io.ifu_axi.w.ready) @[quasar.scala 420:30] + ifu.io.ifu.w.ready <= _T_24 @[quasar.scala 420:24] + node _T_25 = mux(UInt<1>("h01"), axi4_to_ahb_1.io.axi_arready, io.ifu_axi.ar.ready) @[quasar.scala 421:31] + ifu.io.ifu.ar.ready <= _T_25 @[quasar.scala 421:25] + node _T_26 = mux(UInt<1>("h01"), axi4_to_ahb_1.io.axi_rvalid, io.ifu_axi.r.valid) @[quasar.scala 422:30] + ifu.io.ifu.r.valid <= _T_26 @[quasar.scala 422:24] + node _T_27 = mux(UInt<1>("h01"), axi4_to_ahb_1.io.axi_rid, io.ifu_axi.r.bits.id) @[quasar.scala 423:32] + ifu.io.ifu.r.bits.id <= _T_27 @[quasar.scala 423:26] + node _T_28 = mux(UInt<1>("h01"), axi4_to_ahb_1.io.axi_rdata, io.ifu_axi.r.bits.data) @[quasar.scala 424:34] + ifu.io.ifu.r.bits.data <= _T_28 @[quasar.scala 424:28] + node _T_29 = mux(UInt<1>("h01"), axi4_to_ahb_1.io.axi_rresp, io.ifu_axi.r.bits.resp) @[quasar.scala 425:34] + ifu.io.ifu.r.bits.resp <= _T_29 @[quasar.scala 425:28] + node _T_30 = mux(UInt<1>("h01"), axi4_to_ahb_1.io.axi_rlast, io.ifu_axi.r.bits.last) @[quasar.scala 426:34] + ifu.io.ifu.r.bits.last <= _T_30 @[quasar.scala 426:28] + node _T_31 = mux(UInt<1>("h01"), axi4_to_ahb_2.io.axi_awready, io.sb_axi.aw.ready) @[quasar.scala 428:34] + dbg.io.sb_axi.aw.ready <= _T_31 @[quasar.scala 428:28] + node _T_32 = mux(UInt<1>("h01"), axi4_to_ahb_2.io.axi_wready, io.sb_axi.w.ready) @[quasar.scala 429:33] + dbg.io.sb_axi.w.ready <= _T_32 @[quasar.scala 429:27] + node _T_33 = mux(UInt<1>("h01"), axi4_to_ahb_2.io.axi_bvalid, io.sb_axi.b.valid) @[quasar.scala 430:33] + dbg.io.sb_axi.b.valid <= _T_33 @[quasar.scala 430:27] + node _T_34 = mux(UInt<1>("h01"), axi4_to_ahb_2.io.axi_bresp, io.sb_axi.b.bits.resp) @[quasar.scala 431:37] + dbg.io.sb_axi.b.bits.resp <= _T_34 @[quasar.scala 431:31] + node _T_35 = mux(UInt<1>("h01"), axi4_to_ahb_2.io.axi_arready, io.sb_axi.ar.ready) @[quasar.scala 432:34] + dbg.io.sb_axi.ar.ready <= _T_35 @[quasar.scala 432:28] + node _T_36 = mux(UInt<1>("h01"), axi4_to_ahb_2.io.axi_rvalid, io.sb_axi.r.valid) @[quasar.scala 433:33] + dbg.io.sb_axi.r.valid <= _T_36 @[quasar.scala 433:27] + node _T_37 = mux(UInt<1>("h01"), axi4_to_ahb_2.io.axi_rid, io.sb_axi.r.bits.id) @[quasar.scala 434:35] + dbg.io.sb_axi.r.bits.id <= _T_37 @[quasar.scala 434:29] + node _T_38 = mux(UInt<1>("h01"), axi4_to_ahb_2.io.axi_rdata, io.sb_axi.r.bits.data) @[quasar.scala 435:37] + dbg.io.sb_axi.r.bits.data <= _T_38 @[quasar.scala 435:31] + node _T_39 = mux(UInt<1>("h01"), axi4_to_ahb_2.io.axi_rresp, io.sb_axi.r.bits.resp) @[quasar.scala 436:37] + dbg.io.sb_axi.r.bits.resp <= _T_39 @[quasar.scala 436:31] + node _T_40 = mux(UInt<1>("h01"), ahb_to_axi4.io.axi_awvalid, io.dma_axi.aw.valid) @[quasar.scala 438:40] + dma_ctrl.io.dma_axi.aw.valid <= _T_40 @[quasar.scala 438:34] + node _T_41 = mux(UInt<1>("h01"), ahb_to_axi4.io.axi_awid, io.dma_axi.aw.bits.id) @[quasar.scala 439:42] + dma_ctrl.io.dma_axi.aw.bits.id <= _T_41 @[quasar.scala 439:36] + node _T_42 = mux(UInt<1>("h01"), ahb_to_axi4.io.axi_awaddr, io.dma_axi.aw.bits.addr) @[quasar.scala 440:44] + dma_ctrl.io.dma_axi.aw.bits.addr <= _T_42 @[quasar.scala 440:38] + node _T_43 = mux(UInt<1>("h01"), ahb_to_axi4.io.axi_awsize, io.dma_axi.aw.bits.size) @[quasar.scala 441:44] + dma_ctrl.io.dma_axi.aw.bits.size <= _T_43 @[quasar.scala 441:38] + node _T_44 = mux(UInt<1>("h01"), ahb_to_axi4.io.axi_wvalid, io.dma_axi.w.valid) @[quasar.scala 442:39] + dma_ctrl.io.dma_axi.w.valid <= _T_44 @[quasar.scala 442:33] + node _T_45 = mux(UInt<1>("h01"), ahb_to_axi4.io.axi_wdata, io.dma_axi.w.bits.data) @[quasar.scala 443:43] + dma_ctrl.io.dma_axi.w.bits.data <= _T_45 @[quasar.scala 443:37] + node _T_46 = mux(UInt<1>("h01"), ahb_to_axi4.io.axi_wstrb, io.dma_axi.w.bits.strb) @[quasar.scala 444:43] + dma_ctrl.io.dma_axi.w.bits.strb <= _T_46 @[quasar.scala 444:37] + node _T_47 = mux(UInt<1>("h01"), ahb_to_axi4.io.axi_bready, io.dma_axi.b.ready) @[quasar.scala 445:39] + dma_ctrl.io.dma_axi.b.ready <= _T_47 @[quasar.scala 445:33] + node _T_48 = mux(UInt<1>("h01"), ahb_to_axi4.io.axi_arvalid, io.dma_axi.ar.valid) @[quasar.scala 446:40] + dma_ctrl.io.dma_axi.ar.valid <= _T_48 @[quasar.scala 446:34] + node _T_49 = mux(UInt<1>("h01"), ahb_to_axi4.io.axi_arid, io.dma_axi.ar.bits.id) @[quasar.scala 447:42] + dma_ctrl.io.dma_axi.ar.bits.id <= _T_49 @[quasar.scala 447:36] + node _T_50 = mux(UInt<1>("h01"), ahb_to_axi4.io.axi_araddr, io.dma_axi.aw.bits.addr) @[quasar.scala 448:44] + dma_ctrl.io.dma_axi.ar.bits.addr <= _T_50 @[quasar.scala 448:38] + node _T_51 = mux(UInt<1>("h01"), ahb_to_axi4.io.axi_arsize, io.dma_axi.aw.bits.size) @[quasar.scala 449:44] + dma_ctrl.io.dma_axi.ar.bits.size <= _T_51 @[quasar.scala 449:38] + node _T_52 = mux(UInt<1>("h01"), ahb_to_axi4.io.axi_rready, io.dma_axi.r.ready) @[quasar.scala 450:39] + dma_ctrl.io.dma_axi.r.ready <= _T_52 @[quasar.scala 450:33] + io.haddr <= axi4_to_ahb_1.io.ahb_haddr @[quasar.scala 452:14] + io.hburst <= axi4_to_ahb_1.io.ahb_hburst @[quasar.scala 453:15] + io.hmastlock <= axi4_to_ahb_1.io.ahb_hmastlock @[quasar.scala 454:18] + io.hprot <= axi4_to_ahb_1.io.ahb_hprot @[quasar.scala 455:14] + io.hsize <= axi4_to_ahb_1.io.ahb_hsize @[quasar.scala 456:14] + io.htrans <= axi4_to_ahb_1.io.ahb_htrans @[quasar.scala 457:15] + io.hwrite <= axi4_to_ahb_1.io.ahb_hwrite @[quasar.scala 458:15] + io.lsu_haddr <= axi4_to_ahb.io.ahb_haddr @[quasar.scala 461:18] + io.lsu_hburst <= axi4_to_ahb.io.ahb_hburst @[quasar.scala 462:19] + io.lsu_hmastlock <= axi4_to_ahb.io.ahb_hmastlock @[quasar.scala 463:22] + io.lsu_hprot <= axi4_to_ahb.io.ahb_hprot @[quasar.scala 464:18] + io.lsu_hsize <= axi4_to_ahb.io.ahb_hsize @[quasar.scala 465:18] + io.lsu_htrans <= axi4_to_ahb.io.ahb_htrans @[quasar.scala 466:19] + io.lsu_hwrite <= axi4_to_ahb.io.ahb_hwrite @[quasar.scala 467:19] + io.lsu_hwdata <= axi4_to_ahb.io.ahb_hwdata @[quasar.scala 468:19] + io.sb_haddr <= axi4_to_ahb_2.io.ahb_haddr @[quasar.scala 470:17] + io.sb_hburst <= axi4_to_ahb_2.io.ahb_hburst @[quasar.scala 471:18] + io.sb_hmastlock <= axi4_to_ahb_2.io.ahb_hmastlock @[quasar.scala 472:21] + io.sb_hprot <= axi4_to_ahb_2.io.ahb_hprot @[quasar.scala 473:17] + io.sb_hsize <= axi4_to_ahb_2.io.ahb_hsize @[quasar.scala 474:17] + io.sb_htrans <= axi4_to_ahb_2.io.ahb_htrans @[quasar.scala 475:18] + io.sb_hwrite <= axi4_to_ahb_2.io.ahb_hwrite @[quasar.scala 476:18] + io.sb_hwdata <= axi4_to_ahb_2.io.ahb_hwdata @[quasar.scala 477:18] + io.dma_hrdata <= ahb_to_axi4.io.ahb_hrdata @[quasar.scala 479:19] + io.dma_hreadyout <= ahb_to_axi4.io.ahb_hreadyout @[quasar.scala 480:22] + io.dma_hresp <= ahb_to_axi4.io.ahb_hresp @[quasar.scala 481:18] + skip @[quasar.scala 296:26] + else : @[quasar.scala 485:17] + io.haddr <= UInt<1>("h00") @[quasar.scala 487:18] + io.hburst <= UInt<1>("h00") @[quasar.scala 488:19] + io.hmastlock <= UInt<1>("h00") @[quasar.scala 489:22] + io.hprot <= UInt<1>("h00") @[quasar.scala 490:18] + io.hsize <= UInt<1>("h00") @[quasar.scala 491:18] + io.htrans <= UInt<1>("h00") @[quasar.scala 492:19] + io.hwrite <= UInt<1>("h00") @[quasar.scala 493:19] + io.lsu_haddr <= UInt<1>("h00") @[quasar.scala 496:22] + io.lsu_hburst <= UInt<1>("h00") @[quasar.scala 497:23] + io.lsu_hmastlock <= UInt<1>("h00") @[quasar.scala 498:26] + io.lsu_hprot <= UInt<1>("h00") @[quasar.scala 499:22] + io.lsu_hsize <= UInt<1>("h00") @[quasar.scala 500:22] + io.lsu_htrans <= UInt<1>("h00") @[quasar.scala 501:23] + io.lsu_hwrite <= UInt<1>("h00") @[quasar.scala 502:23] + io.lsu_hwdata <= UInt<1>("h00") @[quasar.scala 503:23] + io.sb_haddr <= UInt<1>("h00") @[quasar.scala 505:21] + io.sb_hburst <= UInt<1>("h00") @[quasar.scala 506:22] + io.sb_hmastlock <= UInt<1>("h00") @[quasar.scala 507:25] + io.sb_hprot <= UInt<1>("h00") @[quasar.scala 508:21] + io.sb_hsize <= UInt<1>("h00") @[quasar.scala 509:21] + io.sb_htrans <= UInt<1>("h00") @[quasar.scala 510:22] + io.sb_hwrite <= UInt<1>("h00") @[quasar.scala 511:22] + io.sb_hwdata <= UInt<1>("h00") @[quasar.scala 512:22] + io.dma_hrdata <= UInt<1>("h00") @[quasar.scala 514:23] + io.dma_hreadyout <= UInt<1>("h00") @[quasar.scala 515:26] + io.dma_hresp <= UInt<1>("h00") @[quasar.scala 516:22] + skip @[quasar.scala 485:17] + io.dmi_reg_rdata <= UInt<1>("h00") @[quasar.scala 518:20] module quasar_wrapper : input clock : Clock input reset : AsyncReset - output io : {flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip jtag_id : UInt<31>, trace_rv_i_insn_ip : UInt<32>, trace_rv_i_address_ip : UInt<32>, trace_rv_i_valid_ip : UInt<2>, trace_rv_i_exception_ip : UInt<2>, trace_rv_i_ecause_ip : UInt<5>, trace_rv_i_interrupt_ip : UInt<2>, trace_rv_i_tval_ip : UInt<32>, lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_hsel : UInt<1>, flip dma_haddr : UInt<32>, flip dma_hburst : UInt<3>, flip dma_hmastlock : UInt<1>, flip dma_hprot : UInt<4>, flip dma_hsize : UInt<3>, flip dma_htrans : UInt<2>, flip dma_hwrite : UInt<1>, flip dma_hwdata : UInt<64>, flip dma_hreadyin : UInt<1>, dma_hrdata : UInt<64>, dma_hreadyout : UInt<1>, dma_hresp : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip extintsrc_req : UInt<31>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip jtag_tck : Clock, flip jtag_tms : UInt<1>, flip jtag_tdi : UInt<1>, flip jtag_trst_n : UInt<1>, jtag_tdo : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_debug_mode_status : UInt<1>, o_cpu_run_ack : UInt<1>, flip mbist_mode : UInt<1>, flip scan_mode : UInt<1>} + output io : {flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, flip jtag_id : UInt<31>, lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_hsel : UInt<1>, flip dma_haddr : UInt<32>, flip dma_hburst : UInt<3>, flip dma_hmastlock : UInt<1>, flip dma_hprot : UInt<4>, flip dma_hsize : UInt<3>, flip dma_htrans : UInt<2>, flip dma_hwrite : UInt<1>, flip dma_hwdata : UInt<64>, flip dma_hreadyin : UInt<1>, dma_hrdata : UInt<64>, dma_hreadyout : UInt<1>, dma_hresp : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip extintsrc_req : UInt<31>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip jtag_tck : Clock, flip jtag_tms : UInt<1>, flip jtag_tdi : UInt<1>, flip jtag_trst_n : UInt<1>, jtag_tdo : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_debug_mode_status : UInt<1>, o_cpu_run_ack : UInt<1>, flip mbist_mode : UInt<1>, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, flip scan_mode : UInt<1>} - inst mem of mem @[quasar_wrapper.scala 85:19] + inst mem of mem @[quasar_wrapper.scala 78:19] mem.scan_mode is invalid mem.ic is invalid mem.iccm is invalid @@ -114674,7 +114672,7 @@ circuit quasar_wrapper : mem.dccm_clk_override is invalid mem.rst_l is invalid mem.clk is invalid - inst dmi_wrapper of dmi_wrapper @[quasar_wrapper.scala 86:27] + inst dmi_wrapper of dmi_wrapper @[quasar_wrapper.scala 79:27] dmi_wrapper.dmi_hard_reset is invalid dmi_wrapper.reg_wr_en is invalid dmi_wrapper.reg_en is invalid @@ -114690,282 +114688,282 @@ circuit quasar_wrapper : dmi_wrapper.tms is invalid dmi_wrapper.tck is invalid dmi_wrapper.trst_n is invalid - inst swerv of quasar @[quasar_wrapper.scala 87:21] + inst swerv of quasar @[quasar_wrapper.scala 80:21] swerv.clock <= clock swerv.reset <= reset - dmi_wrapper.trst_n <= io.jtag_trst_n @[quasar_wrapper.scala 88:25] - dmi_wrapper.tck <= io.jtag_tck @[quasar_wrapper.scala 89:22] - dmi_wrapper.tms <= io.jtag_tms @[quasar_wrapper.scala 90:22] - dmi_wrapper.tdi <= io.jtag_tdi @[quasar_wrapper.scala 91:22] - dmi_wrapper.core_clk <= clock @[quasar_wrapper.scala 92:27] - dmi_wrapper.jtag_id <= io.jtag_id @[quasar_wrapper.scala 93:26] - dmi_wrapper.rd_data <= swerv.io.dmi_reg_rdata @[quasar_wrapper.scala 94:26] - dmi_wrapper.core_rst_n <= io.dbg_rst_l @[quasar_wrapper.scala 97:29] - swerv.io.dmi_reg_wdata <= dmi_wrapper.reg_wr_data @[quasar_wrapper.scala 98:26] - swerv.io.dmi_reg_addr <= dmi_wrapper.reg_wr_addr @[quasar_wrapper.scala 99:25] - swerv.io.dmi_reg_en <= dmi_wrapper.reg_en @[quasar_wrapper.scala 100:23] - swerv.io.dmi_reg_wr_en <= dmi_wrapper.reg_wr_en @[quasar_wrapper.scala 101:26] - swerv.io.dmi_hard_reset <= dmi_wrapper.dmi_hard_reset @[quasar_wrapper.scala 102:27] - io.jtag_tdo <= dmi_wrapper.tdo @[quasar_wrapper.scala 103:15] - mem.dccm_clk_override <= swerv.io.dccm_clk_override @[quasar_wrapper.scala 106:28] - mem.icm_clk_override <= swerv.io.icm_clk_override @[quasar_wrapper.scala 107:27] - mem.dec_tlu_core_ecc_disable <= swerv.io.dec_tlu_core_ecc_disable @[quasar_wrapper.scala 108:35] - swerv.io.dccm.rd_data_hi <= mem.dccm.rd_data_hi @[quasar_wrapper.scala 109:15] - swerv.io.dccm.rd_data_lo <= mem.dccm.rd_data_lo @[quasar_wrapper.scala 109:15] - mem.dccm.wr_data_hi <= swerv.io.dccm.wr_data_hi @[quasar_wrapper.scala 109:15] - mem.dccm.wr_data_lo <= swerv.io.dccm.wr_data_lo @[quasar_wrapper.scala 109:15] - mem.dccm.rd_addr_hi <= swerv.io.dccm.rd_addr_hi @[quasar_wrapper.scala 109:15] - mem.dccm.rd_addr_lo <= swerv.io.dccm.rd_addr_lo @[quasar_wrapper.scala 109:15] - mem.dccm.wr_addr_hi <= swerv.io.dccm.wr_addr_hi @[quasar_wrapper.scala 109:15] - mem.dccm.wr_addr_lo <= swerv.io.dccm.wr_addr_lo @[quasar_wrapper.scala 109:15] - mem.dccm.rden <= swerv.io.dccm.rden @[quasar_wrapper.scala 109:15] - mem.dccm.wren <= swerv.io.dccm.wren @[quasar_wrapper.scala 109:15] - mem.rst_l <= reset @[quasar_wrapper.scala 110:16] - mem.clk <= clock @[quasar_wrapper.scala 111:14] - mem.scan_mode <= io.scan_mode @[quasar_wrapper.scala 112:20] - swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 114:22] - mem.ic.sel_premux_data <= swerv.io.ic.sel_premux_data @[quasar_wrapper.scala 115:15] - mem.ic.premux_data <= swerv.io.ic.premux_data @[quasar_wrapper.scala 115:15] - mem.ic.debug_way <= swerv.io.ic.debug_way @[quasar_wrapper.scala 115:15] - mem.ic.debug_tag_array <= swerv.io.ic.debug_tag_array @[quasar_wrapper.scala 115:15] - mem.ic.debug_wr_en <= swerv.io.ic.debug_wr_en @[quasar_wrapper.scala 115:15] - mem.ic.debug_rd_en <= swerv.io.ic.debug_rd_en @[quasar_wrapper.scala 115:15] - swerv.io.ic.tag_perr <= mem.ic.tag_perr @[quasar_wrapper.scala 115:15] - swerv.io.ic.rd_hit <= mem.ic.rd_hit @[quasar_wrapper.scala 115:15] - swerv.io.ic.parerr <= mem.ic.parerr @[quasar_wrapper.scala 115:15] - swerv.io.ic.eccerr <= mem.ic.eccerr @[quasar_wrapper.scala 115:15] - swerv.io.ic.tag_debug_rd_data <= mem.ic.tag_debug_rd_data @[quasar_wrapper.scala 115:15] - swerv.io.ic.debug_rd_data <= mem.ic.debug_rd_data @[quasar_wrapper.scala 115:15] - swerv.io.ic.rd_data <= mem.ic.rd_data @[quasar_wrapper.scala 115:15] - mem.ic.debug_addr <= swerv.io.ic.debug_addr @[quasar_wrapper.scala 115:15] - mem.ic.debug_wr_data <= swerv.io.ic.debug_wr_data @[quasar_wrapper.scala 115:15] - mem.ic.wr_data[0] <= swerv.io.ic.wr_data[0] @[quasar_wrapper.scala 115:15] - mem.ic.wr_data[1] <= swerv.io.ic.wr_data[1] @[quasar_wrapper.scala 115:15] - mem.ic.rd_en <= swerv.io.ic.rd_en @[quasar_wrapper.scala 115:15] - mem.ic.wr_en <= swerv.io.ic.wr_en @[quasar_wrapper.scala 115:15] - mem.ic.tag_valid <= swerv.io.ic.tag_valid @[quasar_wrapper.scala 115:15] - mem.ic.rw_addr <= swerv.io.ic.rw_addr @[quasar_wrapper.scala 115:15] - swerv.io.iccm.rd_data_ecc <= mem.iccm.rd_data_ecc @[quasar_wrapper.scala 116:17] - swerv.io.iccm.rd_data <= mem.iccm.rd_data @[quasar_wrapper.scala 116:17] - mem.iccm.wr_data <= swerv.io.iccm.wr_data @[quasar_wrapper.scala 116:17] - mem.iccm.wr_size <= swerv.io.iccm.wr_size @[quasar_wrapper.scala 116:17] - mem.iccm.rden <= swerv.io.iccm.rden @[quasar_wrapper.scala 116:17] - mem.iccm.wren <= swerv.io.iccm.wren @[quasar_wrapper.scala 116:17] - mem.iccm.correction_state <= swerv.io.iccm.correction_state @[quasar_wrapper.scala 116:17] - mem.iccm.buf_correct_ecc <= swerv.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 116:17] - mem.iccm.rw_addr <= swerv.io.iccm.rw_addr @[quasar_wrapper.scala 116:17] - swerv.io.sb_hready <= UInt<1>("h00") @[quasar_wrapper.scala 117:22] - swerv.io.hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 118:19] - swerv.io.sb_hresp <= UInt<1>("h00") @[quasar_wrapper.scala 119:21] - swerv.io.lsu_hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 120:23] - swerv.io.lsu_hresp <= UInt<1>("h00") @[quasar_wrapper.scala 121:22] - swerv.io.lsu_hready <= UInt<1>("h00") @[quasar_wrapper.scala 122:23] - swerv.io.hready <= UInt<1>("h00") @[quasar_wrapper.scala 123:19] - swerv.io.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 124:18] - swerv.io.sb_hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 125:22] - swerv.io.scan_mode <= io.scan_mode @[quasar_wrapper.scala 126:22] - swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 128:22] - swerv.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 129:20] - swerv.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 130:20] - swerv.io.nmi_vec <= io.nmi_vec @[quasar_wrapper.scala 131:20] - swerv.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar_wrapper.scala 134:27] - swerv.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar_wrapper.scala 135:26] - swerv.io.core_id <= io.core_id @[quasar_wrapper.scala 136:20] - swerv.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar_wrapper.scala 139:31] - swerv.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar_wrapper.scala 140:30] - swerv.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar_wrapper.scala 141:30] - swerv.io.lsu_axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar_wrapper.scala 145:20] - swerv.io.lsu_axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar_wrapper.scala 145:20] - swerv.io.lsu_axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar_wrapper.scala 145:20] - swerv.io.lsu_axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar_wrapper.scala 145:20] - swerv.io.lsu_axi.r.valid <= io.lsu_axi.r.valid @[quasar_wrapper.scala 145:20] - io.lsu_axi.r.ready <= swerv.io.lsu_axi.r.ready @[quasar_wrapper.scala 145:20] - io.lsu_axi.ar.bits.qos <= swerv.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 145:20] - io.lsu_axi.ar.bits.prot <= swerv.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 145:20] - io.lsu_axi.ar.bits.cache <= swerv.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 145:20] - io.lsu_axi.ar.bits.lock <= swerv.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 145:20] - io.lsu_axi.ar.bits.burst <= swerv.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 145:20] - io.lsu_axi.ar.bits.size <= swerv.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 145:20] - io.lsu_axi.ar.bits.len <= swerv.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 145:20] - io.lsu_axi.ar.bits.region <= swerv.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 145:20] - io.lsu_axi.ar.bits.addr <= swerv.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 145:20] - io.lsu_axi.ar.bits.id <= swerv.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 145:20] - io.lsu_axi.ar.valid <= swerv.io.lsu_axi.ar.valid @[quasar_wrapper.scala 145:20] - swerv.io.lsu_axi.ar.ready <= io.lsu_axi.ar.ready @[quasar_wrapper.scala 145:20] - swerv.io.lsu_axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar_wrapper.scala 145:20] - swerv.io.lsu_axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar_wrapper.scala 145:20] - swerv.io.lsu_axi.b.valid <= io.lsu_axi.b.valid @[quasar_wrapper.scala 145:20] - io.lsu_axi.b.ready <= swerv.io.lsu_axi.b.ready @[quasar_wrapper.scala 145:20] - io.lsu_axi.w.bits.last <= swerv.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 145:20] - io.lsu_axi.w.bits.strb <= swerv.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 145:20] - io.lsu_axi.w.bits.data <= swerv.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 145:20] - io.lsu_axi.w.valid <= swerv.io.lsu_axi.w.valid @[quasar_wrapper.scala 145:20] - swerv.io.lsu_axi.w.ready <= io.lsu_axi.w.ready @[quasar_wrapper.scala 145:20] - io.lsu_axi.aw.bits.qos <= swerv.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 145:20] - io.lsu_axi.aw.bits.prot <= swerv.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 145:20] - io.lsu_axi.aw.bits.cache <= swerv.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 145:20] - io.lsu_axi.aw.bits.lock <= swerv.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 145:20] - io.lsu_axi.aw.bits.burst <= swerv.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 145:20] - io.lsu_axi.aw.bits.size <= swerv.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 145:20] - io.lsu_axi.aw.bits.len <= swerv.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 145:20] - io.lsu_axi.aw.bits.region <= swerv.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 145:20] - io.lsu_axi.aw.bits.addr <= swerv.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 145:20] - io.lsu_axi.aw.bits.id <= swerv.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 145:20] - io.lsu_axi.aw.valid <= swerv.io.lsu_axi.aw.valid @[quasar_wrapper.scala 145:20] - swerv.io.lsu_axi.aw.ready <= io.lsu_axi.aw.ready @[quasar_wrapper.scala 145:20] - swerv.io.ifu_axi.r.bits.last <= io.ifu_axi.r.bits.last @[quasar_wrapper.scala 148:20] - swerv.io.ifu_axi.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar_wrapper.scala 148:20] - swerv.io.ifu_axi.r.bits.data <= io.ifu_axi.r.bits.data @[quasar_wrapper.scala 148:20] - swerv.io.ifu_axi.r.bits.id <= io.ifu_axi.r.bits.id @[quasar_wrapper.scala 148:20] - swerv.io.ifu_axi.r.valid <= io.ifu_axi.r.valid @[quasar_wrapper.scala 148:20] - io.ifu_axi.r.ready <= swerv.io.ifu_axi.r.ready @[quasar_wrapper.scala 148:20] - io.ifu_axi.ar.bits.qos <= swerv.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 148:20] - io.ifu_axi.ar.bits.prot <= swerv.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 148:20] - io.ifu_axi.ar.bits.cache <= swerv.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 148:20] - io.ifu_axi.ar.bits.lock <= swerv.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 148:20] - io.ifu_axi.ar.bits.burst <= swerv.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 148:20] - io.ifu_axi.ar.bits.size <= swerv.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 148:20] - io.ifu_axi.ar.bits.len <= swerv.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 148:20] - io.ifu_axi.ar.bits.region <= swerv.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 148:20] - io.ifu_axi.ar.bits.addr <= swerv.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 148:20] - io.ifu_axi.ar.bits.id <= swerv.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 148:20] - io.ifu_axi.ar.valid <= swerv.io.ifu_axi.ar.valid @[quasar_wrapper.scala 148:20] - swerv.io.ifu_axi.ar.ready <= io.ifu_axi.ar.ready @[quasar_wrapper.scala 148:20] - swerv.io.ifu_axi.b.bits.id <= io.ifu_axi.b.bits.id @[quasar_wrapper.scala 148:20] - swerv.io.ifu_axi.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar_wrapper.scala 148:20] - swerv.io.ifu_axi.b.valid <= io.ifu_axi.b.valid @[quasar_wrapper.scala 148:20] - io.ifu_axi.b.ready <= swerv.io.ifu_axi.b.ready @[quasar_wrapper.scala 148:20] - io.ifu_axi.w.bits.last <= swerv.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 148:20] - io.ifu_axi.w.bits.strb <= swerv.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 148:20] - io.ifu_axi.w.bits.data <= swerv.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 148:20] - io.ifu_axi.w.valid <= swerv.io.ifu_axi.w.valid @[quasar_wrapper.scala 148:20] - swerv.io.ifu_axi.w.ready <= io.ifu_axi.w.ready @[quasar_wrapper.scala 148:20] - io.ifu_axi.aw.bits.qos <= swerv.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 148:20] - io.ifu_axi.aw.bits.prot <= swerv.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 148:20] - io.ifu_axi.aw.bits.cache <= swerv.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 148:20] - io.ifu_axi.aw.bits.lock <= swerv.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 148:20] - io.ifu_axi.aw.bits.burst <= swerv.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 148:20] - io.ifu_axi.aw.bits.size <= swerv.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 148:20] - io.ifu_axi.aw.bits.len <= swerv.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 148:20] - io.ifu_axi.aw.bits.region <= swerv.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 148:20] - io.ifu_axi.aw.bits.addr <= swerv.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 148:20] - io.ifu_axi.aw.bits.id <= swerv.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 148:20] - io.ifu_axi.aw.valid <= swerv.io.ifu_axi.aw.valid @[quasar_wrapper.scala 148:20] - swerv.io.ifu_axi.aw.ready <= io.ifu_axi.aw.ready @[quasar_wrapper.scala 148:20] - swerv.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar_wrapper.scala 151:19] - swerv.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar_wrapper.scala 151:19] - swerv.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar_wrapper.scala 151:19] - swerv.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar_wrapper.scala 151:19] - swerv.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar_wrapper.scala 151:19] - io.sb_axi.r.ready <= swerv.io.sb_axi.r.ready @[quasar_wrapper.scala 151:19] - io.sb_axi.ar.bits.qos <= swerv.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 151:19] - io.sb_axi.ar.bits.prot <= swerv.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 151:19] - io.sb_axi.ar.bits.cache <= swerv.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 151:19] - io.sb_axi.ar.bits.lock <= swerv.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 151:19] - io.sb_axi.ar.bits.burst <= swerv.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 151:19] - io.sb_axi.ar.bits.size <= swerv.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 151:19] - io.sb_axi.ar.bits.len <= swerv.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 151:19] - io.sb_axi.ar.bits.region <= swerv.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 151:19] - io.sb_axi.ar.bits.addr <= swerv.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 151:19] - io.sb_axi.ar.bits.id <= swerv.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 151:19] - io.sb_axi.ar.valid <= swerv.io.sb_axi.ar.valid @[quasar_wrapper.scala 151:19] - swerv.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar_wrapper.scala 151:19] - swerv.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar_wrapper.scala 151:19] - swerv.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar_wrapper.scala 151:19] - swerv.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar_wrapper.scala 151:19] - io.sb_axi.b.ready <= swerv.io.sb_axi.b.ready @[quasar_wrapper.scala 151:19] - io.sb_axi.w.bits.last <= swerv.io.sb_axi.w.bits.last @[quasar_wrapper.scala 151:19] - io.sb_axi.w.bits.strb <= swerv.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 151:19] - io.sb_axi.w.bits.data <= swerv.io.sb_axi.w.bits.data @[quasar_wrapper.scala 151:19] - io.sb_axi.w.valid <= swerv.io.sb_axi.w.valid @[quasar_wrapper.scala 151:19] - swerv.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar_wrapper.scala 151:19] - io.sb_axi.aw.bits.qos <= swerv.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 151:19] - io.sb_axi.aw.bits.prot <= swerv.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 151:19] - io.sb_axi.aw.bits.cache <= swerv.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 151:19] - io.sb_axi.aw.bits.lock <= swerv.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 151:19] - io.sb_axi.aw.bits.burst <= swerv.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 151:19] - io.sb_axi.aw.bits.size <= swerv.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 151:19] - io.sb_axi.aw.bits.len <= swerv.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 151:19] - io.sb_axi.aw.bits.region <= swerv.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 151:19] - io.sb_axi.aw.bits.addr <= swerv.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 151:19] - io.sb_axi.aw.bits.id <= swerv.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 151:19] - io.sb_axi.aw.valid <= swerv.io.sb_axi.aw.valid @[quasar_wrapper.scala 151:19] - swerv.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar_wrapper.scala 151:19] - io.dma_axi.r.bits.last <= swerv.io.dma_axi.r.bits.last @[quasar_wrapper.scala 155:20] - io.dma_axi.r.bits.resp <= swerv.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 155:20] - io.dma_axi.r.bits.data <= swerv.io.dma_axi.r.bits.data @[quasar_wrapper.scala 155:20] - io.dma_axi.r.bits.id <= swerv.io.dma_axi.r.bits.id @[quasar_wrapper.scala 155:20] - io.dma_axi.r.valid <= swerv.io.dma_axi.r.valid @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar_wrapper.scala 155:20] - io.dma_axi.ar.ready <= swerv.io.dma_axi.ar.ready @[quasar_wrapper.scala 155:20] - io.dma_axi.b.bits.id <= swerv.io.dma_axi.b.bits.id @[quasar_wrapper.scala 155:20] - io.dma_axi.b.bits.resp <= swerv.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 155:20] - io.dma_axi.b.valid <= swerv.io.dma_axi.b.valid @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar_wrapper.scala 155:20] - io.dma_axi.w.ready <= swerv.io.dma_axi.w.ready @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar_wrapper.scala 155:20] - swerv.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar_wrapper.scala 155:20] - io.dma_axi.aw.ready <= swerv.io.dma_axi.aw.ready @[quasar_wrapper.scala 155:20] - swerv.io.dma_hsel <= io.dma_hsel @[quasar_wrapper.scala 158:21] - swerv.io.dma_haddr <= io.dma_haddr @[quasar_wrapper.scala 159:22] - swerv.io.dma_hburst <= io.dma_hburst @[quasar_wrapper.scala 160:23] - swerv.io.dma_hmastlock <= io.dma_hmastlock @[quasar_wrapper.scala 161:26] - swerv.io.dma_hprot <= io.dma_hprot @[quasar_wrapper.scala 162:22] - swerv.io.dma_hsize <= io.dma_hsize @[quasar_wrapper.scala 163:22] - swerv.io.dma_htrans <= io.dma_htrans @[quasar_wrapper.scala 164:23] - swerv.io.dma_hwrite <= io.dma_hwrite @[quasar_wrapper.scala 165:23] - swerv.io.dma_hwdata <= io.dma_hwdata @[quasar_wrapper.scala 166:23] - swerv.io.dma_hreadyin <= io.dma_hreadyin @[quasar_wrapper.scala 167:25] - swerv.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar_wrapper.scala 185:27] - swerv.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar_wrapper.scala 186:27] - swerv.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar_wrapper.scala 187:27] - swerv.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar_wrapper.scala 188:27] - swerv.io.timer_int <= io.timer_int @[quasar_wrapper.scala 190:22] - swerv.io.soft_int <= io.soft_int @[quasar_wrapper.scala 191:21] - swerv.io.extintsrc_req <= io.extintsrc_req @[quasar_wrapper.scala 192:26] - io.trace_rv_i_insn_ip <= swerv.io.trace_rv_i_insn_ip @[quasar_wrapper.scala 196:25] - io.trace_rv_i_address_ip <= swerv.io.trace_rv_i_address_ip @[quasar_wrapper.scala 197:28] - io.trace_rv_i_valid_ip <= swerv.io.trace_rv_i_valid_ip @[quasar_wrapper.scala 198:26] - io.trace_rv_i_exception_ip <= swerv.io.trace_rv_i_exception_ip @[quasar_wrapper.scala 199:30] - io.trace_rv_i_ecause_ip <= swerv.io.trace_rv_i_ecause_ip @[quasar_wrapper.scala 200:27] - io.trace_rv_i_interrupt_ip <= swerv.io.trace_rv_i_interrupt_ip @[quasar_wrapper.scala 201:30] - io.trace_rv_i_tval_ip <= swerv.io.trace_rv_i_tval_ip @[quasar_wrapper.scala 202:25] - io.o_cpu_halt_ack <= swerv.io.o_cpu_halt_ack @[quasar_wrapper.scala 205:21] - io.o_cpu_halt_status <= swerv.io.o_cpu_halt_status @[quasar_wrapper.scala 206:24] - io.o_cpu_run_ack <= swerv.io.o_cpu_run_ack @[quasar_wrapper.scala 207:20] - io.o_debug_mode_status <= swerv.io.o_debug_mode_status @[quasar_wrapper.scala 208:26] - io.mpc_debug_halt_ack <= swerv.io.mpc_debug_halt_ack @[quasar_wrapper.scala 210:25] - io.mpc_debug_run_ack <= swerv.io.mpc_debug_run_ack @[quasar_wrapper.scala 211:24] - io.debug_brkpt_status <= swerv.io.debug_brkpt_status @[quasar_wrapper.scala 212:25] - io.dec_tlu_perfcnt0 <= swerv.io.dec_tlu_perfcnt0 @[quasar_wrapper.scala 214:23] - io.dec_tlu_perfcnt1 <= swerv.io.dec_tlu_perfcnt1 @[quasar_wrapper.scala 215:23] - io.dec_tlu_perfcnt2 <= swerv.io.dec_tlu_perfcnt2 @[quasar_wrapper.scala 216:23] - io.dec_tlu_perfcnt3 <= swerv.io.dec_tlu_perfcnt3 @[quasar_wrapper.scala 217:23] - io.dma_hrdata <= swerv.io.dma_hrdata @[quasar_wrapper.scala 224:17] - io.dma_hreadyout <= swerv.io.dma_hreadyout @[quasar_wrapper.scala 225:20] - io.dma_hresp <= swerv.io.dma_hresp @[quasar_wrapper.scala 226:16] + dmi_wrapper.trst_n <= io.jtag_trst_n @[quasar_wrapper.scala 81:25] + dmi_wrapper.tck <= io.jtag_tck @[quasar_wrapper.scala 82:22] + dmi_wrapper.tms <= io.jtag_tms @[quasar_wrapper.scala 83:22] + dmi_wrapper.tdi <= io.jtag_tdi @[quasar_wrapper.scala 84:22] + dmi_wrapper.core_clk <= clock @[quasar_wrapper.scala 85:27] + dmi_wrapper.jtag_id <= io.jtag_id @[quasar_wrapper.scala 86:26] + dmi_wrapper.rd_data <= swerv.io.dmi_reg_rdata @[quasar_wrapper.scala 87:26] + dmi_wrapper.core_rst_n <= io.dbg_rst_l @[quasar_wrapper.scala 90:29] + swerv.io.dmi_reg_wdata <= dmi_wrapper.reg_wr_data @[quasar_wrapper.scala 91:26] + swerv.io.dmi_reg_addr <= dmi_wrapper.reg_wr_addr @[quasar_wrapper.scala 92:25] + swerv.io.dmi_reg_en <= dmi_wrapper.reg_en @[quasar_wrapper.scala 93:23] + swerv.io.dmi_reg_wr_en <= dmi_wrapper.reg_wr_en @[quasar_wrapper.scala 94:26] + swerv.io.dmi_hard_reset <= dmi_wrapper.dmi_hard_reset @[quasar_wrapper.scala 95:27] + io.jtag_tdo <= dmi_wrapper.tdo @[quasar_wrapper.scala 96:15] + mem.dccm_clk_override <= swerv.io.dccm_clk_override @[quasar_wrapper.scala 99:28] + mem.icm_clk_override <= swerv.io.icm_clk_override @[quasar_wrapper.scala 100:27] + mem.dec_tlu_core_ecc_disable <= swerv.io.dec_tlu_core_ecc_disable @[quasar_wrapper.scala 101:35] + swerv.io.dccm.rd_data_hi <= mem.dccm.rd_data_hi @[quasar_wrapper.scala 102:15] + swerv.io.dccm.rd_data_lo <= mem.dccm.rd_data_lo @[quasar_wrapper.scala 102:15] + mem.dccm.wr_data_hi <= swerv.io.dccm.wr_data_hi @[quasar_wrapper.scala 102:15] + mem.dccm.wr_data_lo <= swerv.io.dccm.wr_data_lo @[quasar_wrapper.scala 102:15] + mem.dccm.rd_addr_hi <= swerv.io.dccm.rd_addr_hi @[quasar_wrapper.scala 102:15] + mem.dccm.rd_addr_lo <= swerv.io.dccm.rd_addr_lo @[quasar_wrapper.scala 102:15] + mem.dccm.wr_addr_hi <= swerv.io.dccm.wr_addr_hi @[quasar_wrapper.scala 102:15] + mem.dccm.wr_addr_lo <= swerv.io.dccm.wr_addr_lo @[quasar_wrapper.scala 102:15] + mem.dccm.rden <= swerv.io.dccm.rden @[quasar_wrapper.scala 102:15] + mem.dccm.wren <= swerv.io.dccm.wren @[quasar_wrapper.scala 102:15] + mem.rst_l <= reset @[quasar_wrapper.scala 103:16] + mem.clk <= clock @[quasar_wrapper.scala 104:14] + mem.scan_mode <= io.scan_mode @[quasar_wrapper.scala 105:20] + swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 107:22] + mem.ic.sel_premux_data <= swerv.io.ic.sel_premux_data @[quasar_wrapper.scala 108:15] + mem.ic.premux_data <= swerv.io.ic.premux_data @[quasar_wrapper.scala 108:15] + mem.ic.debug_way <= swerv.io.ic.debug_way @[quasar_wrapper.scala 108:15] + mem.ic.debug_tag_array <= swerv.io.ic.debug_tag_array @[quasar_wrapper.scala 108:15] + mem.ic.debug_wr_en <= swerv.io.ic.debug_wr_en @[quasar_wrapper.scala 108:15] + mem.ic.debug_rd_en <= swerv.io.ic.debug_rd_en @[quasar_wrapper.scala 108:15] + swerv.io.ic.tag_perr <= mem.ic.tag_perr @[quasar_wrapper.scala 108:15] + swerv.io.ic.rd_hit <= mem.ic.rd_hit @[quasar_wrapper.scala 108:15] + swerv.io.ic.parerr <= mem.ic.parerr @[quasar_wrapper.scala 108:15] + swerv.io.ic.eccerr <= mem.ic.eccerr @[quasar_wrapper.scala 108:15] + swerv.io.ic.tag_debug_rd_data <= mem.ic.tag_debug_rd_data @[quasar_wrapper.scala 108:15] + swerv.io.ic.debug_rd_data <= mem.ic.debug_rd_data @[quasar_wrapper.scala 108:15] + swerv.io.ic.rd_data <= mem.ic.rd_data @[quasar_wrapper.scala 108:15] + mem.ic.debug_addr <= swerv.io.ic.debug_addr @[quasar_wrapper.scala 108:15] + mem.ic.debug_wr_data <= swerv.io.ic.debug_wr_data @[quasar_wrapper.scala 108:15] + mem.ic.wr_data[0] <= swerv.io.ic.wr_data[0] @[quasar_wrapper.scala 108:15] + mem.ic.wr_data[1] <= swerv.io.ic.wr_data[1] @[quasar_wrapper.scala 108:15] + mem.ic.rd_en <= swerv.io.ic.rd_en @[quasar_wrapper.scala 108:15] + mem.ic.wr_en <= swerv.io.ic.wr_en @[quasar_wrapper.scala 108:15] + mem.ic.tag_valid <= swerv.io.ic.tag_valid @[quasar_wrapper.scala 108:15] + mem.ic.rw_addr <= swerv.io.ic.rw_addr @[quasar_wrapper.scala 108:15] + swerv.io.iccm.rd_data_ecc <= mem.iccm.rd_data_ecc @[quasar_wrapper.scala 109:17] + swerv.io.iccm.rd_data <= mem.iccm.rd_data @[quasar_wrapper.scala 109:17] + mem.iccm.wr_data <= swerv.io.iccm.wr_data @[quasar_wrapper.scala 109:17] + mem.iccm.wr_size <= swerv.io.iccm.wr_size @[quasar_wrapper.scala 109:17] + mem.iccm.rden <= swerv.io.iccm.rden @[quasar_wrapper.scala 109:17] + mem.iccm.wren <= swerv.io.iccm.wren @[quasar_wrapper.scala 109:17] + mem.iccm.correction_state <= swerv.io.iccm.correction_state @[quasar_wrapper.scala 109:17] + mem.iccm.buf_correct_ecc <= swerv.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 109:17] + mem.iccm.rw_addr <= swerv.io.iccm.rw_addr @[quasar_wrapper.scala 109:17] + swerv.io.sb_hready <= UInt<1>("h00") @[quasar_wrapper.scala 110:22] + swerv.io.hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 111:19] + swerv.io.sb_hresp <= UInt<1>("h00") @[quasar_wrapper.scala 112:21] + swerv.io.lsu_hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 113:23] + swerv.io.lsu_hresp <= UInt<1>("h00") @[quasar_wrapper.scala 114:22] + swerv.io.lsu_hready <= UInt<1>("h00") @[quasar_wrapper.scala 115:23] + swerv.io.hready <= UInt<1>("h00") @[quasar_wrapper.scala 116:19] + swerv.io.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 117:18] + swerv.io.sb_hrdata <= UInt<1>("h00") @[quasar_wrapper.scala 118:22] + swerv.io.scan_mode <= io.scan_mode @[quasar_wrapper.scala 119:22] + swerv.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 121:22] + swerv.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 122:20] + swerv.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 123:20] + swerv.io.nmi_vec <= io.nmi_vec @[quasar_wrapper.scala 124:20] + swerv.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar_wrapper.scala 127:27] + swerv.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar_wrapper.scala 128:26] + swerv.io.core_id <= io.core_id @[quasar_wrapper.scala 129:20] + swerv.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar_wrapper.scala 132:31] + swerv.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar_wrapper.scala 133:30] + swerv.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar_wrapper.scala 134:30] + swerv.io.lsu_axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar_wrapper.scala 138:20] + swerv.io.lsu_axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar_wrapper.scala 138:20] + swerv.io.lsu_axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar_wrapper.scala 138:20] + swerv.io.lsu_axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar_wrapper.scala 138:20] + swerv.io.lsu_axi.r.valid <= io.lsu_axi.r.valid @[quasar_wrapper.scala 138:20] + io.lsu_axi.r.ready <= swerv.io.lsu_axi.r.ready @[quasar_wrapper.scala 138:20] + io.lsu_axi.ar.bits.qos <= swerv.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 138:20] + io.lsu_axi.ar.bits.prot <= swerv.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 138:20] + io.lsu_axi.ar.bits.cache <= swerv.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 138:20] + io.lsu_axi.ar.bits.lock <= swerv.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 138:20] + io.lsu_axi.ar.bits.burst <= swerv.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 138:20] + io.lsu_axi.ar.bits.size <= swerv.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 138:20] + io.lsu_axi.ar.bits.len <= swerv.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 138:20] + io.lsu_axi.ar.bits.region <= swerv.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 138:20] + io.lsu_axi.ar.bits.addr <= swerv.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 138:20] + io.lsu_axi.ar.bits.id <= swerv.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 138:20] + io.lsu_axi.ar.valid <= swerv.io.lsu_axi.ar.valid @[quasar_wrapper.scala 138:20] + swerv.io.lsu_axi.ar.ready <= io.lsu_axi.ar.ready @[quasar_wrapper.scala 138:20] + swerv.io.lsu_axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar_wrapper.scala 138:20] + swerv.io.lsu_axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar_wrapper.scala 138:20] + swerv.io.lsu_axi.b.valid <= io.lsu_axi.b.valid @[quasar_wrapper.scala 138:20] + io.lsu_axi.b.ready <= swerv.io.lsu_axi.b.ready @[quasar_wrapper.scala 138:20] + io.lsu_axi.w.bits.last <= swerv.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 138:20] + io.lsu_axi.w.bits.strb <= swerv.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 138:20] + io.lsu_axi.w.bits.data <= swerv.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 138:20] + io.lsu_axi.w.valid <= swerv.io.lsu_axi.w.valid @[quasar_wrapper.scala 138:20] + swerv.io.lsu_axi.w.ready <= io.lsu_axi.w.ready @[quasar_wrapper.scala 138:20] + io.lsu_axi.aw.bits.qos <= swerv.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 138:20] + io.lsu_axi.aw.bits.prot <= swerv.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 138:20] + io.lsu_axi.aw.bits.cache <= swerv.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 138:20] + io.lsu_axi.aw.bits.lock <= swerv.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 138:20] + io.lsu_axi.aw.bits.burst <= swerv.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 138:20] + io.lsu_axi.aw.bits.size <= swerv.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 138:20] + io.lsu_axi.aw.bits.len <= swerv.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 138:20] + io.lsu_axi.aw.bits.region <= swerv.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 138:20] + io.lsu_axi.aw.bits.addr <= swerv.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 138:20] + io.lsu_axi.aw.bits.id <= swerv.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 138:20] + io.lsu_axi.aw.valid <= swerv.io.lsu_axi.aw.valid @[quasar_wrapper.scala 138:20] + swerv.io.lsu_axi.aw.ready <= io.lsu_axi.aw.ready @[quasar_wrapper.scala 138:20] + swerv.io.ifu_axi.r.bits.last <= io.ifu_axi.r.bits.last @[quasar_wrapper.scala 141:20] + swerv.io.ifu_axi.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar_wrapper.scala 141:20] + swerv.io.ifu_axi.r.bits.data <= io.ifu_axi.r.bits.data @[quasar_wrapper.scala 141:20] + swerv.io.ifu_axi.r.bits.id <= io.ifu_axi.r.bits.id @[quasar_wrapper.scala 141:20] + swerv.io.ifu_axi.r.valid <= io.ifu_axi.r.valid @[quasar_wrapper.scala 141:20] + io.ifu_axi.r.ready <= swerv.io.ifu_axi.r.ready @[quasar_wrapper.scala 141:20] + io.ifu_axi.ar.bits.qos <= swerv.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 141:20] + io.ifu_axi.ar.bits.prot <= swerv.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 141:20] + io.ifu_axi.ar.bits.cache <= swerv.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 141:20] + io.ifu_axi.ar.bits.lock <= swerv.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 141:20] + io.ifu_axi.ar.bits.burst <= swerv.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 141:20] + io.ifu_axi.ar.bits.size <= swerv.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 141:20] + io.ifu_axi.ar.bits.len <= swerv.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 141:20] + io.ifu_axi.ar.bits.region <= swerv.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 141:20] + io.ifu_axi.ar.bits.addr <= swerv.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 141:20] + io.ifu_axi.ar.bits.id <= swerv.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 141:20] + io.ifu_axi.ar.valid <= swerv.io.ifu_axi.ar.valid @[quasar_wrapper.scala 141:20] + swerv.io.ifu_axi.ar.ready <= io.ifu_axi.ar.ready @[quasar_wrapper.scala 141:20] + swerv.io.ifu_axi.b.bits.id <= io.ifu_axi.b.bits.id @[quasar_wrapper.scala 141:20] + swerv.io.ifu_axi.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar_wrapper.scala 141:20] + swerv.io.ifu_axi.b.valid <= io.ifu_axi.b.valid @[quasar_wrapper.scala 141:20] + io.ifu_axi.b.ready <= swerv.io.ifu_axi.b.ready @[quasar_wrapper.scala 141:20] + io.ifu_axi.w.bits.last <= swerv.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 141:20] + io.ifu_axi.w.bits.strb <= swerv.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 141:20] + io.ifu_axi.w.bits.data <= swerv.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 141:20] + io.ifu_axi.w.valid <= swerv.io.ifu_axi.w.valid @[quasar_wrapper.scala 141:20] + swerv.io.ifu_axi.w.ready <= io.ifu_axi.w.ready @[quasar_wrapper.scala 141:20] + io.ifu_axi.aw.bits.qos <= swerv.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 141:20] + io.ifu_axi.aw.bits.prot <= swerv.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 141:20] + io.ifu_axi.aw.bits.cache <= swerv.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 141:20] + io.ifu_axi.aw.bits.lock <= swerv.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 141:20] + io.ifu_axi.aw.bits.burst <= swerv.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 141:20] + io.ifu_axi.aw.bits.size <= swerv.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 141:20] + io.ifu_axi.aw.bits.len <= swerv.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 141:20] + io.ifu_axi.aw.bits.region <= swerv.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 141:20] + io.ifu_axi.aw.bits.addr <= swerv.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 141:20] + io.ifu_axi.aw.bits.id <= swerv.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 141:20] + io.ifu_axi.aw.valid <= swerv.io.ifu_axi.aw.valid @[quasar_wrapper.scala 141:20] + swerv.io.ifu_axi.aw.ready <= io.ifu_axi.aw.ready @[quasar_wrapper.scala 141:20] + swerv.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar_wrapper.scala 144:19] + swerv.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar_wrapper.scala 144:19] + swerv.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar_wrapper.scala 144:19] + swerv.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar_wrapper.scala 144:19] + swerv.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar_wrapper.scala 144:19] + io.sb_axi.r.ready <= swerv.io.sb_axi.r.ready @[quasar_wrapper.scala 144:19] + io.sb_axi.ar.bits.qos <= swerv.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 144:19] + io.sb_axi.ar.bits.prot <= swerv.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 144:19] + io.sb_axi.ar.bits.cache <= swerv.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 144:19] + io.sb_axi.ar.bits.lock <= swerv.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 144:19] + io.sb_axi.ar.bits.burst <= swerv.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 144:19] + io.sb_axi.ar.bits.size <= swerv.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 144:19] + io.sb_axi.ar.bits.len <= swerv.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 144:19] + io.sb_axi.ar.bits.region <= swerv.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 144:19] + io.sb_axi.ar.bits.addr <= swerv.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 144:19] + io.sb_axi.ar.bits.id <= swerv.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 144:19] + io.sb_axi.ar.valid <= swerv.io.sb_axi.ar.valid @[quasar_wrapper.scala 144:19] + swerv.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar_wrapper.scala 144:19] + swerv.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar_wrapper.scala 144:19] + swerv.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar_wrapper.scala 144:19] + swerv.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar_wrapper.scala 144:19] + io.sb_axi.b.ready <= swerv.io.sb_axi.b.ready @[quasar_wrapper.scala 144:19] + io.sb_axi.w.bits.last <= swerv.io.sb_axi.w.bits.last @[quasar_wrapper.scala 144:19] + io.sb_axi.w.bits.strb <= swerv.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 144:19] + io.sb_axi.w.bits.data <= swerv.io.sb_axi.w.bits.data @[quasar_wrapper.scala 144:19] + io.sb_axi.w.valid <= swerv.io.sb_axi.w.valid @[quasar_wrapper.scala 144:19] + swerv.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar_wrapper.scala 144:19] + io.sb_axi.aw.bits.qos <= swerv.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 144:19] + io.sb_axi.aw.bits.prot <= swerv.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 144:19] + io.sb_axi.aw.bits.cache <= swerv.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 144:19] + io.sb_axi.aw.bits.lock <= swerv.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 144:19] + io.sb_axi.aw.bits.burst <= swerv.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 144:19] + io.sb_axi.aw.bits.size <= swerv.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 144:19] + io.sb_axi.aw.bits.len <= swerv.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 144:19] + io.sb_axi.aw.bits.region <= swerv.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 144:19] + io.sb_axi.aw.bits.addr <= swerv.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 144:19] + io.sb_axi.aw.bits.id <= swerv.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 144:19] + io.sb_axi.aw.valid <= swerv.io.sb_axi.aw.valid @[quasar_wrapper.scala 144:19] + swerv.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar_wrapper.scala 144:19] + io.dma_axi.r.bits.last <= swerv.io.dma_axi.r.bits.last @[quasar_wrapper.scala 148:20] + io.dma_axi.r.bits.resp <= swerv.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 148:20] + io.dma_axi.r.bits.data <= swerv.io.dma_axi.r.bits.data @[quasar_wrapper.scala 148:20] + io.dma_axi.r.bits.id <= swerv.io.dma_axi.r.bits.id @[quasar_wrapper.scala 148:20] + io.dma_axi.r.valid <= swerv.io.dma_axi.r.valid @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar_wrapper.scala 148:20] + io.dma_axi.ar.ready <= swerv.io.dma_axi.ar.ready @[quasar_wrapper.scala 148:20] + io.dma_axi.b.bits.id <= swerv.io.dma_axi.b.bits.id @[quasar_wrapper.scala 148:20] + io.dma_axi.b.bits.resp <= swerv.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 148:20] + io.dma_axi.b.valid <= swerv.io.dma_axi.b.valid @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar_wrapper.scala 148:20] + io.dma_axi.w.ready <= swerv.io.dma_axi.w.ready @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar_wrapper.scala 148:20] + swerv.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar_wrapper.scala 148:20] + io.dma_axi.aw.ready <= swerv.io.dma_axi.aw.ready @[quasar_wrapper.scala 148:20] + swerv.io.dma_hsel <= io.dma_hsel @[quasar_wrapper.scala 151:21] + swerv.io.dma_haddr <= io.dma_haddr @[quasar_wrapper.scala 152:22] + swerv.io.dma_hburst <= io.dma_hburst @[quasar_wrapper.scala 153:23] + swerv.io.dma_hmastlock <= io.dma_hmastlock @[quasar_wrapper.scala 154:26] + swerv.io.dma_hprot <= io.dma_hprot @[quasar_wrapper.scala 155:22] + swerv.io.dma_hsize <= io.dma_hsize @[quasar_wrapper.scala 156:22] + swerv.io.dma_htrans <= io.dma_htrans @[quasar_wrapper.scala 157:23] + swerv.io.dma_hwrite <= io.dma_hwrite @[quasar_wrapper.scala 158:23] + swerv.io.dma_hwdata <= io.dma_hwdata @[quasar_wrapper.scala 159:23] + swerv.io.dma_hreadyin <= io.dma_hreadyin @[quasar_wrapper.scala 160:25] + swerv.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar_wrapper.scala 178:27] + swerv.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar_wrapper.scala 179:27] + swerv.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar_wrapper.scala 180:27] + swerv.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar_wrapper.scala 181:27] + swerv.io.timer_int <= io.timer_int @[quasar_wrapper.scala 183:22] + swerv.io.soft_int <= io.soft_int @[quasar_wrapper.scala 184:21] + swerv.io.extintsrc_req <= io.extintsrc_req @[quasar_wrapper.scala 185:26] + io.rv_trace_pkt.rv_i_tval_ip <= swerv.io.rv_trace_pkt.rv_i_tval_ip @[quasar_wrapper.scala 189:19] + io.rv_trace_pkt.rv_i_interrupt_ip <= swerv.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar_wrapper.scala 189:19] + io.rv_trace_pkt.rv_i_ecause_ip <= swerv.io.rv_trace_pkt.rv_i_ecause_ip @[quasar_wrapper.scala 189:19] + io.rv_trace_pkt.rv_i_exception_ip <= swerv.io.rv_trace_pkt.rv_i_exception_ip @[quasar_wrapper.scala 189:19] + io.rv_trace_pkt.rv_i_address_ip <= swerv.io.rv_trace_pkt.rv_i_address_ip @[quasar_wrapper.scala 189:19] + io.rv_trace_pkt.rv_i_insn_ip <= swerv.io.rv_trace_pkt.rv_i_insn_ip @[quasar_wrapper.scala 189:19] + io.rv_trace_pkt.rv_i_valid_ip <= swerv.io.rv_trace_pkt.rv_i_valid_ip @[quasar_wrapper.scala 189:19] + io.o_cpu_halt_ack <= swerv.io.o_cpu_halt_ack @[quasar_wrapper.scala 192:21] + io.o_cpu_halt_status <= swerv.io.o_cpu_halt_status @[quasar_wrapper.scala 193:24] + io.o_cpu_run_ack <= swerv.io.o_cpu_run_ack @[quasar_wrapper.scala 194:20] + io.o_debug_mode_status <= swerv.io.o_debug_mode_status @[quasar_wrapper.scala 195:26] + io.mpc_debug_halt_ack <= swerv.io.mpc_debug_halt_ack @[quasar_wrapper.scala 197:25] + io.mpc_debug_run_ack <= swerv.io.mpc_debug_run_ack @[quasar_wrapper.scala 198:24] + io.debug_brkpt_status <= swerv.io.debug_brkpt_status @[quasar_wrapper.scala 199:25] + io.dec_tlu_perfcnt0 <= swerv.io.dec_tlu_perfcnt0 @[quasar_wrapper.scala 201:23] + io.dec_tlu_perfcnt1 <= swerv.io.dec_tlu_perfcnt1 @[quasar_wrapper.scala 202:23] + io.dec_tlu_perfcnt2 <= swerv.io.dec_tlu_perfcnt2 @[quasar_wrapper.scala 203:23] + io.dec_tlu_perfcnt3 <= swerv.io.dec_tlu_perfcnt3 @[quasar_wrapper.scala 204:23] + io.dma_hrdata <= swerv.io.dma_hrdata @[quasar_wrapper.scala 211:17] + io.dma_hreadyout <= swerv.io.dma_hreadyout @[quasar_wrapper.scala 212:20] + io.dma_hresp <= swerv.io.dma_hresp @[quasar_wrapper.scala 213:16] diff --git a/quasar_wrapper.v b/quasar_wrapper.v index 0bf346af..899d97f5 100644 --- a/quasar_wrapper.v +++ b/quasar_wrapper.v @@ -25,7 +25,6 @@ module ifu_mem_ctl( input io_free_clk, input io_active_clk, input io_exu_flush_final, - input io_dec_mem_ctrl_dec_tlu_flush_lower_wb, input io_dec_mem_ctrl_dec_tlu_flush_err_wb, input io_dec_mem_ctrl_dec_tlu_i0_commit_cmt, input io_dec_mem_ctrl_dec_tlu_force_halt, @@ -109,6 +108,7 @@ module ifu_mem_ctl( output [63:0] io_iccm_dma_rdata, output [2:0] io_iccm_dma_rtag, output io_iccm_ready, + input io_dec_tlu_flush_lower_wb, output io_iccm_rd_ecc_double_err, output io_iccm_dma_sb_error, output io_ic_hit_f, @@ -3360,7 +3360,7 @@ module ifu_mem_ctl( wire _T_2509 = _T_2508 | io_iccm_dma_sb_error; // @[ifu_mem_ctl.scala 418:105] wire _T_2511 = _T_2509 & _T_2623; // @[ifu_mem_ctl.scala 418:129] wire _T_2512 = 3'h1 == perr_state; // @[Conditional.scala 37:30] - wire _T_2513 = io_dec_mem_ctrl_dec_tlu_flush_lower_wb | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 423:63] + wire _T_2513 = io_dec_tlu_flush_lower_wb | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 423:50] wire _T_2515 = 3'h2 == perr_state; // @[Conditional.scala 37:30] wire _T_2522 = 3'h4 == perr_state; // @[Conditional.scala 37:30] wire _T_2524 = 3'h3 == perr_state; // @[Conditional.scala 37:30] @@ -3369,7 +3369,7 @@ module ifu_mem_ctl( wire _GEN_25 = _T_2512 ? _T_2513 : _GEN_23; // @[Conditional.scala 39:67] wire perr_state_en = _T_2500 ? _T_2511 : _GEN_25; // @[Conditional.scala 40:58] wire perr_sb_write_status = _T_2500 & perr_state_en; // @[Conditional.scala 40:58] - wire _T_2514 = io_dec_mem_ctrl_dec_tlu_flush_lower_wb & io_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu_mem_ctl.scala 424:69] + wire _T_2514 = io_dec_tlu_flush_lower_wb & io_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu_mem_ctl.scala 424:56] wire _GEN_26 = _T_2512 & _T_2514; // @[Conditional.scala 39:67] wire perr_sel_invalidate = _T_2500 ? 1'h0 : _GEN_26; // @[Conditional.scala 40:58] wire [1:0] perr_err_inv_way = perr_sel_invalidate ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] @@ -3377,20 +3377,20 @@ module ifu_mem_ctl( wire _T_2497 = ~dma_sb_err_state_ff; // @[ifu_mem_ctl.scala 408:49] wire _T_2502 = io_dec_mem_ctrl_ifu_ic_error_start & _T_319; // @[ifu_mem_ctl.scala 417:104] wire _T_2516 = ~io_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu_mem_ctl.scala 427:30] - wire _T_2517 = _T_2516 & io_dec_mem_ctrl_dec_tlu_flush_lower_wb; // @[ifu_mem_ctl.scala 427:68] - wire _T_2518 = _T_2517 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 427:111] + wire _T_2517 = _T_2516 & io_dec_tlu_flush_lower_wb; // @[ifu_mem_ctl.scala 427:68] + wire _T_2518 = _T_2517 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 427:98] wire _T_2527 = perr_state == 3'h2; // @[ifu_mem_ctl.scala 447:79] wire _T_2528 = io_dec_mem_ctrl_dec_tlu_flush_err_wb & _T_2527; // @[ifu_mem_ctl.scala 447:65] wire _T_2530 = _T_2528 & _T_2623; // @[ifu_mem_ctl.scala 447:94] - wire _T_2532 = io_dec_mem_ctrl_dec_tlu_flush_lower_wb | io_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu_mem_ctl.scala 450:72] - wire _T_2533 = _T_2532 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 450:112] - wire _T_2547 = _T_2532 | io_ifu_fetch_val[0]; // @[ifu_mem_ctl.scala 453:107] - wire _T_2548 = _T_2547 | ifu_bp_hit_taken_q_f; // @[ifu_mem_ctl.scala 453:129] - wire _T_2549 = _T_2548 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 453:152] - wire _T_2569 = _T_2547 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 460:129] - wire _T_2577 = io_dec_mem_ctrl_dec_tlu_flush_lower_wb & _T_2516; // @[ifu_mem_ctl.scala 465:73] - wire _T_2578 = _T_2577 | io_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu_mem_ctl.scala 465:114] - wire _T_2579 = _T_2578 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 465:154] + wire _T_2532 = io_dec_tlu_flush_lower_wb | io_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu_mem_ctl.scala 450:59] + wire _T_2533 = _T_2532 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 450:99] + wire _T_2547 = _T_2532 | io_ifu_fetch_val[0]; // @[ifu_mem_ctl.scala 453:94] + wire _T_2548 = _T_2547 | ifu_bp_hit_taken_q_f; // @[ifu_mem_ctl.scala 453:116] + wire _T_2549 = _T_2548 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 453:139] + wire _T_2569 = _T_2547 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 460:116] + wire _T_2577 = io_dec_tlu_flush_lower_wb & _T_2516; // @[ifu_mem_ctl.scala 465:60] + wire _T_2578 = _T_2577 | io_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu_mem_ctl.scala 465:101] + wire _T_2579 = _T_2578 | io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu_mem_ctl.scala 465:141] wire _GEN_33 = _T_2575 & _T_2533; // @[Conditional.scala 39:67] wire _GEN_36 = _T_2558 ? _T_2569 : _GEN_33; // @[Conditional.scala 39:67] wire _GEN_38 = _T_2558 | _T_2575; // @[Conditional.scala 39:67] @@ -11878,9 +11878,9 @@ module ifu_bp_ctl( input io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error, input io_dec_bp_dec_tlu_br0_r_pkt_bits_way, input io_dec_bp_dec_tlu_br0_r_pkt_bits_middle, - input io_dec_bp_dec_tlu_flush_lower_wb, input io_dec_bp_dec_tlu_flush_leak_one_wb, input io_dec_bp_dec_tlu_bpred_disable, + input io_dec_tlu_flush_lower_wb, input [7:0] io_exu_bp_exu_i0_br_index_r, input [7:0] io_exu_bp_exu_i0_br_fghr_r, input io_exu_bp_exu_mp_pkt_bits_misp, @@ -15167,1061 +15167,1061 @@ module ifu_bp_ctl( wire rvclkhdr_553_io_clk; // @[lib.scala 327:22] wire rvclkhdr_553_io_en; // @[lib.scala 327:22] wire rvclkhdr_553_io_scan_mode; // @[lib.scala 327:22] - wire _T_40 = io_dec_bp_dec_tlu_flush_leak_one_wb & io_dec_bp_dec_tlu_flush_lower_wb; // @[ifu_bp_ctl.scala 122:54] - reg leak_one_f_d1; // @[ifu_bp_ctl.scala 116:56] - wire _T_41 = ~io_dec_bp_dec_tlu_flush_lower_wb; // @[ifu_bp_ctl.scala 122:109] - wire _T_42 = leak_one_f_d1 & _T_41; // @[ifu_bp_ctl.scala 122:107] - wire leak_one_f = _T_40 | _T_42; // @[ifu_bp_ctl.scala 122:90] - wire _T = ~leak_one_f; // @[ifu_bp_ctl.scala 59:58] - wire exu_mp_valid = io_exu_bp_exu_mp_pkt_bits_misp & _T; // @[ifu_bp_ctl.scala 59:56] - wire dec_tlu_error_wb = io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error | io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[ifu_bp_ctl.scala 81:50] + wire _T_40 = io_dec_bp_dec_tlu_flush_leak_one_wb & io_dec_tlu_flush_lower_wb; // @[ifu_bp_ctl.scala 123:54] + reg leak_one_f_d1; // @[ifu_bp_ctl.scala 117:56] + wire _T_41 = ~io_dec_tlu_flush_lower_wb; // @[ifu_bp_ctl.scala 123:102] + wire _T_42 = leak_one_f_d1 & _T_41; // @[ifu_bp_ctl.scala 123:100] + wire leak_one_f = _T_40 | _T_42; // @[ifu_bp_ctl.scala 123:83] + wire _T = ~leak_one_f; // @[ifu_bp_ctl.scala 60:58] + wire exu_mp_valid = io_exu_bp_exu_mp_pkt_bits_misp & _T; // @[ifu_bp_ctl.scala 60:56] + wire dec_tlu_error_wb = io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error | io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[ifu_bp_ctl.scala 82:50] wire [7:0] _T_4 = io_ifc_fetch_addr_f[8:1] ^ io_ifc_fetch_addr_f[16:9]; // @[lib.scala 35:47] wire [7:0] btb_rd_addr_f = _T_4 ^ io_ifc_fetch_addr_f[24:17]; // @[lib.scala 35:85] - wire [29:0] fetch_addr_p1_f = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[ifu_bp_ctl.scala 89:51] + wire [29:0] fetch_addr_p1_f = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[ifu_bp_ctl.scala 90:51] wire [30:0] _T_8 = {fetch_addr_p1_f,1'h0}; // @[Cat.scala 29:58] wire [7:0] _T_11 = _T_8[8:1] ^ _T_8[16:9]; // @[lib.scala 35:47] wire [7:0] btb_rd_addr_p1_f = _T_11 ^ _T_8[24:17]; // @[lib.scala 35:85] - wire _T_144 = ~io_ifc_fetch_addr_f[0]; // @[ifu_bp_ctl.scala 173:40] - wire _T_2112 = btb_rd_addr_f == 8'h0; // @[ifu_bp_ctl.scala 417:77] + wire _T_144 = ~io_ifc_fetch_addr_f[0]; // @[ifu_bp_ctl.scala 174:40] + wire _T_2112 = btb_rd_addr_f == 8'h0; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_0; // @[lib.scala 358:16] wire [21:0] _T_2624 = _T_2112 ? btb_bank0_rd_data_way0_out_0 : 22'h0; // @[Mux.scala 27:72] - wire _T_2114 = btb_rd_addr_f == 8'h1; // @[ifu_bp_ctl.scala 417:77] + wire _T_2114 = btb_rd_addr_f == 8'h1; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_1; // @[lib.scala 358:16] wire [21:0] _T_2625 = _T_2114 ? btb_bank0_rd_data_way0_out_1 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2880 = _T_2624 | _T_2625; // @[Mux.scala 27:72] - wire _T_2116 = btb_rd_addr_f == 8'h2; // @[ifu_bp_ctl.scala 417:77] + wire _T_2116 = btb_rd_addr_f == 8'h2; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_2; // @[lib.scala 358:16] wire [21:0] _T_2626 = _T_2116 ? btb_bank0_rd_data_way0_out_2 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2881 = _T_2880 | _T_2626; // @[Mux.scala 27:72] - wire _T_2118 = btb_rd_addr_f == 8'h3; // @[ifu_bp_ctl.scala 417:77] + wire _T_2118 = btb_rd_addr_f == 8'h3; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_3; // @[lib.scala 358:16] wire [21:0] _T_2627 = _T_2118 ? btb_bank0_rd_data_way0_out_3 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2882 = _T_2881 | _T_2627; // @[Mux.scala 27:72] - wire _T_2120 = btb_rd_addr_f == 8'h4; // @[ifu_bp_ctl.scala 417:77] + wire _T_2120 = btb_rd_addr_f == 8'h4; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_4; // @[lib.scala 358:16] wire [21:0] _T_2628 = _T_2120 ? btb_bank0_rd_data_way0_out_4 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2883 = _T_2882 | _T_2628; // @[Mux.scala 27:72] - wire _T_2122 = btb_rd_addr_f == 8'h5; // @[ifu_bp_ctl.scala 417:77] + wire _T_2122 = btb_rd_addr_f == 8'h5; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_5; // @[lib.scala 358:16] wire [21:0] _T_2629 = _T_2122 ? btb_bank0_rd_data_way0_out_5 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2884 = _T_2883 | _T_2629; // @[Mux.scala 27:72] - wire _T_2124 = btb_rd_addr_f == 8'h6; // @[ifu_bp_ctl.scala 417:77] + wire _T_2124 = btb_rd_addr_f == 8'h6; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_6; // @[lib.scala 358:16] wire [21:0] _T_2630 = _T_2124 ? btb_bank0_rd_data_way0_out_6 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2885 = _T_2884 | _T_2630; // @[Mux.scala 27:72] - wire _T_2126 = btb_rd_addr_f == 8'h7; // @[ifu_bp_ctl.scala 417:77] + wire _T_2126 = btb_rd_addr_f == 8'h7; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_7; // @[lib.scala 358:16] wire [21:0] _T_2631 = _T_2126 ? btb_bank0_rd_data_way0_out_7 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2886 = _T_2885 | _T_2631; // @[Mux.scala 27:72] - wire _T_2128 = btb_rd_addr_f == 8'h8; // @[ifu_bp_ctl.scala 417:77] + wire _T_2128 = btb_rd_addr_f == 8'h8; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_8; // @[lib.scala 358:16] wire [21:0] _T_2632 = _T_2128 ? btb_bank0_rd_data_way0_out_8 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2887 = _T_2886 | _T_2632; // @[Mux.scala 27:72] - wire _T_2130 = btb_rd_addr_f == 8'h9; // @[ifu_bp_ctl.scala 417:77] + wire _T_2130 = btb_rd_addr_f == 8'h9; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_9; // @[lib.scala 358:16] wire [21:0] _T_2633 = _T_2130 ? btb_bank0_rd_data_way0_out_9 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2888 = _T_2887 | _T_2633; // @[Mux.scala 27:72] - wire _T_2132 = btb_rd_addr_f == 8'ha; // @[ifu_bp_ctl.scala 417:77] + wire _T_2132 = btb_rd_addr_f == 8'ha; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_10; // @[lib.scala 358:16] wire [21:0] _T_2634 = _T_2132 ? btb_bank0_rd_data_way0_out_10 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2889 = _T_2888 | _T_2634; // @[Mux.scala 27:72] - wire _T_2134 = btb_rd_addr_f == 8'hb; // @[ifu_bp_ctl.scala 417:77] + wire _T_2134 = btb_rd_addr_f == 8'hb; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_11; // @[lib.scala 358:16] wire [21:0] _T_2635 = _T_2134 ? btb_bank0_rd_data_way0_out_11 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2890 = _T_2889 | _T_2635; // @[Mux.scala 27:72] - wire _T_2136 = btb_rd_addr_f == 8'hc; // @[ifu_bp_ctl.scala 417:77] + wire _T_2136 = btb_rd_addr_f == 8'hc; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_12; // @[lib.scala 358:16] wire [21:0] _T_2636 = _T_2136 ? btb_bank0_rd_data_way0_out_12 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2891 = _T_2890 | _T_2636; // @[Mux.scala 27:72] - wire _T_2138 = btb_rd_addr_f == 8'hd; // @[ifu_bp_ctl.scala 417:77] + wire _T_2138 = btb_rd_addr_f == 8'hd; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_13; // @[lib.scala 358:16] wire [21:0] _T_2637 = _T_2138 ? btb_bank0_rd_data_way0_out_13 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2892 = _T_2891 | _T_2637; // @[Mux.scala 27:72] - wire _T_2140 = btb_rd_addr_f == 8'he; // @[ifu_bp_ctl.scala 417:77] + wire _T_2140 = btb_rd_addr_f == 8'he; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_14; // @[lib.scala 358:16] wire [21:0] _T_2638 = _T_2140 ? btb_bank0_rd_data_way0_out_14 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2893 = _T_2892 | _T_2638; // @[Mux.scala 27:72] - wire _T_2142 = btb_rd_addr_f == 8'hf; // @[ifu_bp_ctl.scala 417:77] + wire _T_2142 = btb_rd_addr_f == 8'hf; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_15; // @[lib.scala 358:16] wire [21:0] _T_2639 = _T_2142 ? btb_bank0_rd_data_way0_out_15 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2894 = _T_2893 | _T_2639; // @[Mux.scala 27:72] - wire _T_2144 = btb_rd_addr_f == 8'h10; // @[ifu_bp_ctl.scala 417:77] + wire _T_2144 = btb_rd_addr_f == 8'h10; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_16; // @[lib.scala 358:16] wire [21:0] _T_2640 = _T_2144 ? btb_bank0_rd_data_way0_out_16 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2895 = _T_2894 | _T_2640; // @[Mux.scala 27:72] - wire _T_2146 = btb_rd_addr_f == 8'h11; // @[ifu_bp_ctl.scala 417:77] + wire _T_2146 = btb_rd_addr_f == 8'h11; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_17; // @[lib.scala 358:16] wire [21:0] _T_2641 = _T_2146 ? btb_bank0_rd_data_way0_out_17 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2896 = _T_2895 | _T_2641; // @[Mux.scala 27:72] - wire _T_2148 = btb_rd_addr_f == 8'h12; // @[ifu_bp_ctl.scala 417:77] + wire _T_2148 = btb_rd_addr_f == 8'h12; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_18; // @[lib.scala 358:16] wire [21:0] _T_2642 = _T_2148 ? btb_bank0_rd_data_way0_out_18 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2897 = _T_2896 | _T_2642; // @[Mux.scala 27:72] - wire _T_2150 = btb_rd_addr_f == 8'h13; // @[ifu_bp_ctl.scala 417:77] + wire _T_2150 = btb_rd_addr_f == 8'h13; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_19; // @[lib.scala 358:16] wire [21:0] _T_2643 = _T_2150 ? btb_bank0_rd_data_way0_out_19 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2898 = _T_2897 | _T_2643; // @[Mux.scala 27:72] - wire _T_2152 = btb_rd_addr_f == 8'h14; // @[ifu_bp_ctl.scala 417:77] + wire _T_2152 = btb_rd_addr_f == 8'h14; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_20; // @[lib.scala 358:16] wire [21:0] _T_2644 = _T_2152 ? btb_bank0_rd_data_way0_out_20 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2899 = _T_2898 | _T_2644; // @[Mux.scala 27:72] - wire _T_2154 = btb_rd_addr_f == 8'h15; // @[ifu_bp_ctl.scala 417:77] + wire _T_2154 = btb_rd_addr_f == 8'h15; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_21; // @[lib.scala 358:16] wire [21:0] _T_2645 = _T_2154 ? btb_bank0_rd_data_way0_out_21 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2900 = _T_2899 | _T_2645; // @[Mux.scala 27:72] - wire _T_2156 = btb_rd_addr_f == 8'h16; // @[ifu_bp_ctl.scala 417:77] + wire _T_2156 = btb_rd_addr_f == 8'h16; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_22; // @[lib.scala 358:16] wire [21:0] _T_2646 = _T_2156 ? btb_bank0_rd_data_way0_out_22 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2901 = _T_2900 | _T_2646; // @[Mux.scala 27:72] - wire _T_2158 = btb_rd_addr_f == 8'h17; // @[ifu_bp_ctl.scala 417:77] + wire _T_2158 = btb_rd_addr_f == 8'h17; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_23; // @[lib.scala 358:16] wire [21:0] _T_2647 = _T_2158 ? btb_bank0_rd_data_way0_out_23 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2902 = _T_2901 | _T_2647; // @[Mux.scala 27:72] - wire _T_2160 = btb_rd_addr_f == 8'h18; // @[ifu_bp_ctl.scala 417:77] + wire _T_2160 = btb_rd_addr_f == 8'h18; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_24; // @[lib.scala 358:16] wire [21:0] _T_2648 = _T_2160 ? btb_bank0_rd_data_way0_out_24 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2903 = _T_2902 | _T_2648; // @[Mux.scala 27:72] - wire _T_2162 = btb_rd_addr_f == 8'h19; // @[ifu_bp_ctl.scala 417:77] + wire _T_2162 = btb_rd_addr_f == 8'h19; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_25; // @[lib.scala 358:16] wire [21:0] _T_2649 = _T_2162 ? btb_bank0_rd_data_way0_out_25 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2904 = _T_2903 | _T_2649; // @[Mux.scala 27:72] - wire _T_2164 = btb_rd_addr_f == 8'h1a; // @[ifu_bp_ctl.scala 417:77] + wire _T_2164 = btb_rd_addr_f == 8'h1a; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_26; // @[lib.scala 358:16] wire [21:0] _T_2650 = _T_2164 ? btb_bank0_rd_data_way0_out_26 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2905 = _T_2904 | _T_2650; // @[Mux.scala 27:72] - wire _T_2166 = btb_rd_addr_f == 8'h1b; // @[ifu_bp_ctl.scala 417:77] + wire _T_2166 = btb_rd_addr_f == 8'h1b; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_27; // @[lib.scala 358:16] wire [21:0] _T_2651 = _T_2166 ? btb_bank0_rd_data_way0_out_27 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2906 = _T_2905 | _T_2651; // @[Mux.scala 27:72] - wire _T_2168 = btb_rd_addr_f == 8'h1c; // @[ifu_bp_ctl.scala 417:77] + wire _T_2168 = btb_rd_addr_f == 8'h1c; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_28; // @[lib.scala 358:16] wire [21:0] _T_2652 = _T_2168 ? btb_bank0_rd_data_way0_out_28 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2907 = _T_2906 | _T_2652; // @[Mux.scala 27:72] - wire _T_2170 = btb_rd_addr_f == 8'h1d; // @[ifu_bp_ctl.scala 417:77] + wire _T_2170 = btb_rd_addr_f == 8'h1d; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_29; // @[lib.scala 358:16] wire [21:0] _T_2653 = _T_2170 ? btb_bank0_rd_data_way0_out_29 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2908 = _T_2907 | _T_2653; // @[Mux.scala 27:72] - wire _T_2172 = btb_rd_addr_f == 8'h1e; // @[ifu_bp_ctl.scala 417:77] + wire _T_2172 = btb_rd_addr_f == 8'h1e; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_30; // @[lib.scala 358:16] wire [21:0] _T_2654 = _T_2172 ? btb_bank0_rd_data_way0_out_30 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2909 = _T_2908 | _T_2654; // @[Mux.scala 27:72] - wire _T_2174 = btb_rd_addr_f == 8'h1f; // @[ifu_bp_ctl.scala 417:77] + wire _T_2174 = btb_rd_addr_f == 8'h1f; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_31; // @[lib.scala 358:16] wire [21:0] _T_2655 = _T_2174 ? btb_bank0_rd_data_way0_out_31 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2910 = _T_2909 | _T_2655; // @[Mux.scala 27:72] - wire _T_2176 = btb_rd_addr_f == 8'h20; // @[ifu_bp_ctl.scala 417:77] + wire _T_2176 = btb_rd_addr_f == 8'h20; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_32; // @[lib.scala 358:16] wire [21:0] _T_2656 = _T_2176 ? btb_bank0_rd_data_way0_out_32 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2911 = _T_2910 | _T_2656; // @[Mux.scala 27:72] - wire _T_2178 = btb_rd_addr_f == 8'h21; // @[ifu_bp_ctl.scala 417:77] + wire _T_2178 = btb_rd_addr_f == 8'h21; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_33; // @[lib.scala 358:16] wire [21:0] _T_2657 = _T_2178 ? btb_bank0_rd_data_way0_out_33 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2912 = _T_2911 | _T_2657; // @[Mux.scala 27:72] - wire _T_2180 = btb_rd_addr_f == 8'h22; // @[ifu_bp_ctl.scala 417:77] + wire _T_2180 = btb_rd_addr_f == 8'h22; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_34; // @[lib.scala 358:16] wire [21:0] _T_2658 = _T_2180 ? btb_bank0_rd_data_way0_out_34 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2913 = _T_2912 | _T_2658; // @[Mux.scala 27:72] - wire _T_2182 = btb_rd_addr_f == 8'h23; // @[ifu_bp_ctl.scala 417:77] + wire _T_2182 = btb_rd_addr_f == 8'h23; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_35; // @[lib.scala 358:16] wire [21:0] _T_2659 = _T_2182 ? btb_bank0_rd_data_way0_out_35 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2914 = _T_2913 | _T_2659; // @[Mux.scala 27:72] - wire _T_2184 = btb_rd_addr_f == 8'h24; // @[ifu_bp_ctl.scala 417:77] + wire _T_2184 = btb_rd_addr_f == 8'h24; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_36; // @[lib.scala 358:16] wire [21:0] _T_2660 = _T_2184 ? btb_bank0_rd_data_way0_out_36 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2915 = _T_2914 | _T_2660; // @[Mux.scala 27:72] - wire _T_2186 = btb_rd_addr_f == 8'h25; // @[ifu_bp_ctl.scala 417:77] + wire _T_2186 = btb_rd_addr_f == 8'h25; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_37; // @[lib.scala 358:16] wire [21:0] _T_2661 = _T_2186 ? btb_bank0_rd_data_way0_out_37 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2916 = _T_2915 | _T_2661; // @[Mux.scala 27:72] - wire _T_2188 = btb_rd_addr_f == 8'h26; // @[ifu_bp_ctl.scala 417:77] + wire _T_2188 = btb_rd_addr_f == 8'h26; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_38; // @[lib.scala 358:16] wire [21:0] _T_2662 = _T_2188 ? btb_bank0_rd_data_way0_out_38 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2917 = _T_2916 | _T_2662; // @[Mux.scala 27:72] - wire _T_2190 = btb_rd_addr_f == 8'h27; // @[ifu_bp_ctl.scala 417:77] + wire _T_2190 = btb_rd_addr_f == 8'h27; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_39; // @[lib.scala 358:16] wire [21:0] _T_2663 = _T_2190 ? btb_bank0_rd_data_way0_out_39 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2918 = _T_2917 | _T_2663; // @[Mux.scala 27:72] - wire _T_2192 = btb_rd_addr_f == 8'h28; // @[ifu_bp_ctl.scala 417:77] + wire _T_2192 = btb_rd_addr_f == 8'h28; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_40; // @[lib.scala 358:16] wire [21:0] _T_2664 = _T_2192 ? btb_bank0_rd_data_way0_out_40 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2919 = _T_2918 | _T_2664; // @[Mux.scala 27:72] - wire _T_2194 = btb_rd_addr_f == 8'h29; // @[ifu_bp_ctl.scala 417:77] + wire _T_2194 = btb_rd_addr_f == 8'h29; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_41; // @[lib.scala 358:16] wire [21:0] _T_2665 = _T_2194 ? btb_bank0_rd_data_way0_out_41 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2920 = _T_2919 | _T_2665; // @[Mux.scala 27:72] - wire _T_2196 = btb_rd_addr_f == 8'h2a; // @[ifu_bp_ctl.scala 417:77] + wire _T_2196 = btb_rd_addr_f == 8'h2a; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_42; // @[lib.scala 358:16] wire [21:0] _T_2666 = _T_2196 ? btb_bank0_rd_data_way0_out_42 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2921 = _T_2920 | _T_2666; // @[Mux.scala 27:72] - wire _T_2198 = btb_rd_addr_f == 8'h2b; // @[ifu_bp_ctl.scala 417:77] + wire _T_2198 = btb_rd_addr_f == 8'h2b; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_43; // @[lib.scala 358:16] wire [21:0] _T_2667 = _T_2198 ? btb_bank0_rd_data_way0_out_43 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2922 = _T_2921 | _T_2667; // @[Mux.scala 27:72] - wire _T_2200 = btb_rd_addr_f == 8'h2c; // @[ifu_bp_ctl.scala 417:77] + wire _T_2200 = btb_rd_addr_f == 8'h2c; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_44; // @[lib.scala 358:16] wire [21:0] _T_2668 = _T_2200 ? btb_bank0_rd_data_way0_out_44 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2923 = _T_2922 | _T_2668; // @[Mux.scala 27:72] - wire _T_2202 = btb_rd_addr_f == 8'h2d; // @[ifu_bp_ctl.scala 417:77] + wire _T_2202 = btb_rd_addr_f == 8'h2d; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_45; // @[lib.scala 358:16] wire [21:0] _T_2669 = _T_2202 ? btb_bank0_rd_data_way0_out_45 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2924 = _T_2923 | _T_2669; // @[Mux.scala 27:72] - wire _T_2204 = btb_rd_addr_f == 8'h2e; // @[ifu_bp_ctl.scala 417:77] + wire _T_2204 = btb_rd_addr_f == 8'h2e; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_46; // @[lib.scala 358:16] wire [21:0] _T_2670 = _T_2204 ? btb_bank0_rd_data_way0_out_46 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2925 = _T_2924 | _T_2670; // @[Mux.scala 27:72] - wire _T_2206 = btb_rd_addr_f == 8'h2f; // @[ifu_bp_ctl.scala 417:77] + wire _T_2206 = btb_rd_addr_f == 8'h2f; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_47; // @[lib.scala 358:16] wire [21:0] _T_2671 = _T_2206 ? btb_bank0_rd_data_way0_out_47 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2926 = _T_2925 | _T_2671; // @[Mux.scala 27:72] - wire _T_2208 = btb_rd_addr_f == 8'h30; // @[ifu_bp_ctl.scala 417:77] + wire _T_2208 = btb_rd_addr_f == 8'h30; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_48; // @[lib.scala 358:16] wire [21:0] _T_2672 = _T_2208 ? btb_bank0_rd_data_way0_out_48 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2927 = _T_2926 | _T_2672; // @[Mux.scala 27:72] - wire _T_2210 = btb_rd_addr_f == 8'h31; // @[ifu_bp_ctl.scala 417:77] + wire _T_2210 = btb_rd_addr_f == 8'h31; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_49; // @[lib.scala 358:16] wire [21:0] _T_2673 = _T_2210 ? btb_bank0_rd_data_way0_out_49 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2928 = _T_2927 | _T_2673; // @[Mux.scala 27:72] - wire _T_2212 = btb_rd_addr_f == 8'h32; // @[ifu_bp_ctl.scala 417:77] + wire _T_2212 = btb_rd_addr_f == 8'h32; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_50; // @[lib.scala 358:16] wire [21:0] _T_2674 = _T_2212 ? btb_bank0_rd_data_way0_out_50 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2929 = _T_2928 | _T_2674; // @[Mux.scala 27:72] - wire _T_2214 = btb_rd_addr_f == 8'h33; // @[ifu_bp_ctl.scala 417:77] + wire _T_2214 = btb_rd_addr_f == 8'h33; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_51; // @[lib.scala 358:16] wire [21:0] _T_2675 = _T_2214 ? btb_bank0_rd_data_way0_out_51 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2930 = _T_2929 | _T_2675; // @[Mux.scala 27:72] - wire _T_2216 = btb_rd_addr_f == 8'h34; // @[ifu_bp_ctl.scala 417:77] + wire _T_2216 = btb_rd_addr_f == 8'h34; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_52; // @[lib.scala 358:16] wire [21:0] _T_2676 = _T_2216 ? btb_bank0_rd_data_way0_out_52 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2931 = _T_2930 | _T_2676; // @[Mux.scala 27:72] - wire _T_2218 = btb_rd_addr_f == 8'h35; // @[ifu_bp_ctl.scala 417:77] + wire _T_2218 = btb_rd_addr_f == 8'h35; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_53; // @[lib.scala 358:16] wire [21:0] _T_2677 = _T_2218 ? btb_bank0_rd_data_way0_out_53 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2932 = _T_2931 | _T_2677; // @[Mux.scala 27:72] - wire _T_2220 = btb_rd_addr_f == 8'h36; // @[ifu_bp_ctl.scala 417:77] + wire _T_2220 = btb_rd_addr_f == 8'h36; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_54; // @[lib.scala 358:16] wire [21:0] _T_2678 = _T_2220 ? btb_bank0_rd_data_way0_out_54 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2933 = _T_2932 | _T_2678; // @[Mux.scala 27:72] - wire _T_2222 = btb_rd_addr_f == 8'h37; // @[ifu_bp_ctl.scala 417:77] + wire _T_2222 = btb_rd_addr_f == 8'h37; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_55; // @[lib.scala 358:16] wire [21:0] _T_2679 = _T_2222 ? btb_bank0_rd_data_way0_out_55 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2934 = _T_2933 | _T_2679; // @[Mux.scala 27:72] - wire _T_2224 = btb_rd_addr_f == 8'h38; // @[ifu_bp_ctl.scala 417:77] + wire _T_2224 = btb_rd_addr_f == 8'h38; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_56; // @[lib.scala 358:16] wire [21:0] _T_2680 = _T_2224 ? btb_bank0_rd_data_way0_out_56 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2935 = _T_2934 | _T_2680; // @[Mux.scala 27:72] - wire _T_2226 = btb_rd_addr_f == 8'h39; // @[ifu_bp_ctl.scala 417:77] + wire _T_2226 = btb_rd_addr_f == 8'h39; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_57; // @[lib.scala 358:16] wire [21:0] _T_2681 = _T_2226 ? btb_bank0_rd_data_way0_out_57 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2936 = _T_2935 | _T_2681; // @[Mux.scala 27:72] - wire _T_2228 = btb_rd_addr_f == 8'h3a; // @[ifu_bp_ctl.scala 417:77] + wire _T_2228 = btb_rd_addr_f == 8'h3a; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_58; // @[lib.scala 358:16] wire [21:0] _T_2682 = _T_2228 ? btb_bank0_rd_data_way0_out_58 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2937 = _T_2936 | _T_2682; // @[Mux.scala 27:72] - wire _T_2230 = btb_rd_addr_f == 8'h3b; // @[ifu_bp_ctl.scala 417:77] + wire _T_2230 = btb_rd_addr_f == 8'h3b; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_59; // @[lib.scala 358:16] wire [21:0] _T_2683 = _T_2230 ? btb_bank0_rd_data_way0_out_59 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2938 = _T_2937 | _T_2683; // @[Mux.scala 27:72] - wire _T_2232 = btb_rd_addr_f == 8'h3c; // @[ifu_bp_ctl.scala 417:77] + wire _T_2232 = btb_rd_addr_f == 8'h3c; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_60; // @[lib.scala 358:16] wire [21:0] _T_2684 = _T_2232 ? btb_bank0_rd_data_way0_out_60 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2939 = _T_2938 | _T_2684; // @[Mux.scala 27:72] - wire _T_2234 = btb_rd_addr_f == 8'h3d; // @[ifu_bp_ctl.scala 417:77] + wire _T_2234 = btb_rd_addr_f == 8'h3d; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_61; // @[lib.scala 358:16] wire [21:0] _T_2685 = _T_2234 ? btb_bank0_rd_data_way0_out_61 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2940 = _T_2939 | _T_2685; // @[Mux.scala 27:72] - wire _T_2236 = btb_rd_addr_f == 8'h3e; // @[ifu_bp_ctl.scala 417:77] + wire _T_2236 = btb_rd_addr_f == 8'h3e; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_62; // @[lib.scala 358:16] wire [21:0] _T_2686 = _T_2236 ? btb_bank0_rd_data_way0_out_62 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2941 = _T_2940 | _T_2686; // @[Mux.scala 27:72] - wire _T_2238 = btb_rd_addr_f == 8'h3f; // @[ifu_bp_ctl.scala 417:77] + wire _T_2238 = btb_rd_addr_f == 8'h3f; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_63; // @[lib.scala 358:16] wire [21:0] _T_2687 = _T_2238 ? btb_bank0_rd_data_way0_out_63 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2942 = _T_2941 | _T_2687; // @[Mux.scala 27:72] - wire _T_2240 = btb_rd_addr_f == 8'h40; // @[ifu_bp_ctl.scala 417:77] + wire _T_2240 = btb_rd_addr_f == 8'h40; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_64; // @[lib.scala 358:16] wire [21:0] _T_2688 = _T_2240 ? btb_bank0_rd_data_way0_out_64 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2943 = _T_2942 | _T_2688; // @[Mux.scala 27:72] - wire _T_2242 = btb_rd_addr_f == 8'h41; // @[ifu_bp_ctl.scala 417:77] + wire _T_2242 = btb_rd_addr_f == 8'h41; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_65; // @[lib.scala 358:16] wire [21:0] _T_2689 = _T_2242 ? btb_bank0_rd_data_way0_out_65 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2944 = _T_2943 | _T_2689; // @[Mux.scala 27:72] - wire _T_2244 = btb_rd_addr_f == 8'h42; // @[ifu_bp_ctl.scala 417:77] + wire _T_2244 = btb_rd_addr_f == 8'h42; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_66; // @[lib.scala 358:16] wire [21:0] _T_2690 = _T_2244 ? btb_bank0_rd_data_way0_out_66 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2945 = _T_2944 | _T_2690; // @[Mux.scala 27:72] - wire _T_2246 = btb_rd_addr_f == 8'h43; // @[ifu_bp_ctl.scala 417:77] + wire _T_2246 = btb_rd_addr_f == 8'h43; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_67; // @[lib.scala 358:16] wire [21:0] _T_2691 = _T_2246 ? btb_bank0_rd_data_way0_out_67 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2946 = _T_2945 | _T_2691; // @[Mux.scala 27:72] - wire _T_2248 = btb_rd_addr_f == 8'h44; // @[ifu_bp_ctl.scala 417:77] + wire _T_2248 = btb_rd_addr_f == 8'h44; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_68; // @[lib.scala 358:16] wire [21:0] _T_2692 = _T_2248 ? btb_bank0_rd_data_way0_out_68 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2947 = _T_2946 | _T_2692; // @[Mux.scala 27:72] - wire _T_2250 = btb_rd_addr_f == 8'h45; // @[ifu_bp_ctl.scala 417:77] + wire _T_2250 = btb_rd_addr_f == 8'h45; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_69; // @[lib.scala 358:16] wire [21:0] _T_2693 = _T_2250 ? btb_bank0_rd_data_way0_out_69 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2948 = _T_2947 | _T_2693; // @[Mux.scala 27:72] - wire _T_2252 = btb_rd_addr_f == 8'h46; // @[ifu_bp_ctl.scala 417:77] + wire _T_2252 = btb_rd_addr_f == 8'h46; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_70; // @[lib.scala 358:16] wire [21:0] _T_2694 = _T_2252 ? btb_bank0_rd_data_way0_out_70 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2949 = _T_2948 | _T_2694; // @[Mux.scala 27:72] - wire _T_2254 = btb_rd_addr_f == 8'h47; // @[ifu_bp_ctl.scala 417:77] + wire _T_2254 = btb_rd_addr_f == 8'h47; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_71; // @[lib.scala 358:16] wire [21:0] _T_2695 = _T_2254 ? btb_bank0_rd_data_way0_out_71 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2950 = _T_2949 | _T_2695; // @[Mux.scala 27:72] - wire _T_2256 = btb_rd_addr_f == 8'h48; // @[ifu_bp_ctl.scala 417:77] + wire _T_2256 = btb_rd_addr_f == 8'h48; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_72; // @[lib.scala 358:16] wire [21:0] _T_2696 = _T_2256 ? btb_bank0_rd_data_way0_out_72 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2951 = _T_2950 | _T_2696; // @[Mux.scala 27:72] - wire _T_2258 = btb_rd_addr_f == 8'h49; // @[ifu_bp_ctl.scala 417:77] + wire _T_2258 = btb_rd_addr_f == 8'h49; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_73; // @[lib.scala 358:16] wire [21:0] _T_2697 = _T_2258 ? btb_bank0_rd_data_way0_out_73 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2952 = _T_2951 | _T_2697; // @[Mux.scala 27:72] - wire _T_2260 = btb_rd_addr_f == 8'h4a; // @[ifu_bp_ctl.scala 417:77] + wire _T_2260 = btb_rd_addr_f == 8'h4a; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_74; // @[lib.scala 358:16] wire [21:0] _T_2698 = _T_2260 ? btb_bank0_rd_data_way0_out_74 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2953 = _T_2952 | _T_2698; // @[Mux.scala 27:72] - wire _T_2262 = btb_rd_addr_f == 8'h4b; // @[ifu_bp_ctl.scala 417:77] + wire _T_2262 = btb_rd_addr_f == 8'h4b; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_75; // @[lib.scala 358:16] wire [21:0] _T_2699 = _T_2262 ? btb_bank0_rd_data_way0_out_75 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2954 = _T_2953 | _T_2699; // @[Mux.scala 27:72] - wire _T_2264 = btb_rd_addr_f == 8'h4c; // @[ifu_bp_ctl.scala 417:77] + wire _T_2264 = btb_rd_addr_f == 8'h4c; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_76; // @[lib.scala 358:16] wire [21:0] _T_2700 = _T_2264 ? btb_bank0_rd_data_way0_out_76 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2955 = _T_2954 | _T_2700; // @[Mux.scala 27:72] - wire _T_2266 = btb_rd_addr_f == 8'h4d; // @[ifu_bp_ctl.scala 417:77] + wire _T_2266 = btb_rd_addr_f == 8'h4d; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_77; // @[lib.scala 358:16] wire [21:0] _T_2701 = _T_2266 ? btb_bank0_rd_data_way0_out_77 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2956 = _T_2955 | _T_2701; // @[Mux.scala 27:72] - wire _T_2268 = btb_rd_addr_f == 8'h4e; // @[ifu_bp_ctl.scala 417:77] + wire _T_2268 = btb_rd_addr_f == 8'h4e; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_78; // @[lib.scala 358:16] wire [21:0] _T_2702 = _T_2268 ? btb_bank0_rd_data_way0_out_78 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2957 = _T_2956 | _T_2702; // @[Mux.scala 27:72] - wire _T_2270 = btb_rd_addr_f == 8'h4f; // @[ifu_bp_ctl.scala 417:77] + wire _T_2270 = btb_rd_addr_f == 8'h4f; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_79; // @[lib.scala 358:16] wire [21:0] _T_2703 = _T_2270 ? btb_bank0_rd_data_way0_out_79 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2958 = _T_2957 | _T_2703; // @[Mux.scala 27:72] - wire _T_2272 = btb_rd_addr_f == 8'h50; // @[ifu_bp_ctl.scala 417:77] + wire _T_2272 = btb_rd_addr_f == 8'h50; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_80; // @[lib.scala 358:16] wire [21:0] _T_2704 = _T_2272 ? btb_bank0_rd_data_way0_out_80 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2959 = _T_2958 | _T_2704; // @[Mux.scala 27:72] - wire _T_2274 = btb_rd_addr_f == 8'h51; // @[ifu_bp_ctl.scala 417:77] + wire _T_2274 = btb_rd_addr_f == 8'h51; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_81; // @[lib.scala 358:16] wire [21:0] _T_2705 = _T_2274 ? btb_bank0_rd_data_way0_out_81 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2960 = _T_2959 | _T_2705; // @[Mux.scala 27:72] - wire _T_2276 = btb_rd_addr_f == 8'h52; // @[ifu_bp_ctl.scala 417:77] + wire _T_2276 = btb_rd_addr_f == 8'h52; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_82; // @[lib.scala 358:16] wire [21:0] _T_2706 = _T_2276 ? btb_bank0_rd_data_way0_out_82 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2961 = _T_2960 | _T_2706; // @[Mux.scala 27:72] - wire _T_2278 = btb_rd_addr_f == 8'h53; // @[ifu_bp_ctl.scala 417:77] + wire _T_2278 = btb_rd_addr_f == 8'h53; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_83; // @[lib.scala 358:16] wire [21:0] _T_2707 = _T_2278 ? btb_bank0_rd_data_way0_out_83 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2962 = _T_2961 | _T_2707; // @[Mux.scala 27:72] - wire _T_2280 = btb_rd_addr_f == 8'h54; // @[ifu_bp_ctl.scala 417:77] + wire _T_2280 = btb_rd_addr_f == 8'h54; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_84; // @[lib.scala 358:16] wire [21:0] _T_2708 = _T_2280 ? btb_bank0_rd_data_way0_out_84 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2963 = _T_2962 | _T_2708; // @[Mux.scala 27:72] - wire _T_2282 = btb_rd_addr_f == 8'h55; // @[ifu_bp_ctl.scala 417:77] + wire _T_2282 = btb_rd_addr_f == 8'h55; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_85; // @[lib.scala 358:16] wire [21:0] _T_2709 = _T_2282 ? btb_bank0_rd_data_way0_out_85 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2964 = _T_2963 | _T_2709; // @[Mux.scala 27:72] - wire _T_2284 = btb_rd_addr_f == 8'h56; // @[ifu_bp_ctl.scala 417:77] + wire _T_2284 = btb_rd_addr_f == 8'h56; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_86; // @[lib.scala 358:16] wire [21:0] _T_2710 = _T_2284 ? btb_bank0_rd_data_way0_out_86 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2965 = _T_2964 | _T_2710; // @[Mux.scala 27:72] - wire _T_2286 = btb_rd_addr_f == 8'h57; // @[ifu_bp_ctl.scala 417:77] + wire _T_2286 = btb_rd_addr_f == 8'h57; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_87; // @[lib.scala 358:16] wire [21:0] _T_2711 = _T_2286 ? btb_bank0_rd_data_way0_out_87 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2966 = _T_2965 | _T_2711; // @[Mux.scala 27:72] - wire _T_2288 = btb_rd_addr_f == 8'h58; // @[ifu_bp_ctl.scala 417:77] + wire _T_2288 = btb_rd_addr_f == 8'h58; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_88; // @[lib.scala 358:16] wire [21:0] _T_2712 = _T_2288 ? btb_bank0_rd_data_way0_out_88 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2967 = _T_2966 | _T_2712; // @[Mux.scala 27:72] - wire _T_2290 = btb_rd_addr_f == 8'h59; // @[ifu_bp_ctl.scala 417:77] + wire _T_2290 = btb_rd_addr_f == 8'h59; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_89; // @[lib.scala 358:16] wire [21:0] _T_2713 = _T_2290 ? btb_bank0_rd_data_way0_out_89 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2968 = _T_2967 | _T_2713; // @[Mux.scala 27:72] - wire _T_2292 = btb_rd_addr_f == 8'h5a; // @[ifu_bp_ctl.scala 417:77] + wire _T_2292 = btb_rd_addr_f == 8'h5a; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_90; // @[lib.scala 358:16] wire [21:0] _T_2714 = _T_2292 ? btb_bank0_rd_data_way0_out_90 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2969 = _T_2968 | _T_2714; // @[Mux.scala 27:72] - wire _T_2294 = btb_rd_addr_f == 8'h5b; // @[ifu_bp_ctl.scala 417:77] + wire _T_2294 = btb_rd_addr_f == 8'h5b; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_91; // @[lib.scala 358:16] wire [21:0] _T_2715 = _T_2294 ? btb_bank0_rd_data_way0_out_91 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2970 = _T_2969 | _T_2715; // @[Mux.scala 27:72] - wire _T_2296 = btb_rd_addr_f == 8'h5c; // @[ifu_bp_ctl.scala 417:77] + wire _T_2296 = btb_rd_addr_f == 8'h5c; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_92; // @[lib.scala 358:16] wire [21:0] _T_2716 = _T_2296 ? btb_bank0_rd_data_way0_out_92 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2971 = _T_2970 | _T_2716; // @[Mux.scala 27:72] - wire _T_2298 = btb_rd_addr_f == 8'h5d; // @[ifu_bp_ctl.scala 417:77] + wire _T_2298 = btb_rd_addr_f == 8'h5d; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_93; // @[lib.scala 358:16] wire [21:0] _T_2717 = _T_2298 ? btb_bank0_rd_data_way0_out_93 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2972 = _T_2971 | _T_2717; // @[Mux.scala 27:72] - wire _T_2300 = btb_rd_addr_f == 8'h5e; // @[ifu_bp_ctl.scala 417:77] + wire _T_2300 = btb_rd_addr_f == 8'h5e; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_94; // @[lib.scala 358:16] wire [21:0] _T_2718 = _T_2300 ? btb_bank0_rd_data_way0_out_94 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2973 = _T_2972 | _T_2718; // @[Mux.scala 27:72] - wire _T_2302 = btb_rd_addr_f == 8'h5f; // @[ifu_bp_ctl.scala 417:77] + wire _T_2302 = btb_rd_addr_f == 8'h5f; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_95; // @[lib.scala 358:16] wire [21:0] _T_2719 = _T_2302 ? btb_bank0_rd_data_way0_out_95 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2974 = _T_2973 | _T_2719; // @[Mux.scala 27:72] - wire _T_2304 = btb_rd_addr_f == 8'h60; // @[ifu_bp_ctl.scala 417:77] + wire _T_2304 = btb_rd_addr_f == 8'h60; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_96; // @[lib.scala 358:16] wire [21:0] _T_2720 = _T_2304 ? btb_bank0_rd_data_way0_out_96 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2975 = _T_2974 | _T_2720; // @[Mux.scala 27:72] - wire _T_2306 = btb_rd_addr_f == 8'h61; // @[ifu_bp_ctl.scala 417:77] + wire _T_2306 = btb_rd_addr_f == 8'h61; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_97; // @[lib.scala 358:16] wire [21:0] _T_2721 = _T_2306 ? btb_bank0_rd_data_way0_out_97 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2976 = _T_2975 | _T_2721; // @[Mux.scala 27:72] - wire _T_2308 = btb_rd_addr_f == 8'h62; // @[ifu_bp_ctl.scala 417:77] + wire _T_2308 = btb_rd_addr_f == 8'h62; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_98; // @[lib.scala 358:16] wire [21:0] _T_2722 = _T_2308 ? btb_bank0_rd_data_way0_out_98 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2977 = _T_2976 | _T_2722; // @[Mux.scala 27:72] - wire _T_2310 = btb_rd_addr_f == 8'h63; // @[ifu_bp_ctl.scala 417:77] + wire _T_2310 = btb_rd_addr_f == 8'h63; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_99; // @[lib.scala 358:16] wire [21:0] _T_2723 = _T_2310 ? btb_bank0_rd_data_way0_out_99 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2978 = _T_2977 | _T_2723; // @[Mux.scala 27:72] - wire _T_2312 = btb_rd_addr_f == 8'h64; // @[ifu_bp_ctl.scala 417:77] + wire _T_2312 = btb_rd_addr_f == 8'h64; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_100; // @[lib.scala 358:16] wire [21:0] _T_2724 = _T_2312 ? btb_bank0_rd_data_way0_out_100 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2979 = _T_2978 | _T_2724; // @[Mux.scala 27:72] - wire _T_2314 = btb_rd_addr_f == 8'h65; // @[ifu_bp_ctl.scala 417:77] + wire _T_2314 = btb_rd_addr_f == 8'h65; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_101; // @[lib.scala 358:16] wire [21:0] _T_2725 = _T_2314 ? btb_bank0_rd_data_way0_out_101 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2980 = _T_2979 | _T_2725; // @[Mux.scala 27:72] - wire _T_2316 = btb_rd_addr_f == 8'h66; // @[ifu_bp_ctl.scala 417:77] + wire _T_2316 = btb_rd_addr_f == 8'h66; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_102; // @[lib.scala 358:16] wire [21:0] _T_2726 = _T_2316 ? btb_bank0_rd_data_way0_out_102 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2981 = _T_2980 | _T_2726; // @[Mux.scala 27:72] - wire _T_2318 = btb_rd_addr_f == 8'h67; // @[ifu_bp_ctl.scala 417:77] + wire _T_2318 = btb_rd_addr_f == 8'h67; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_103; // @[lib.scala 358:16] wire [21:0] _T_2727 = _T_2318 ? btb_bank0_rd_data_way0_out_103 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2982 = _T_2981 | _T_2727; // @[Mux.scala 27:72] - wire _T_2320 = btb_rd_addr_f == 8'h68; // @[ifu_bp_ctl.scala 417:77] + wire _T_2320 = btb_rd_addr_f == 8'h68; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_104; // @[lib.scala 358:16] wire [21:0] _T_2728 = _T_2320 ? btb_bank0_rd_data_way0_out_104 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2983 = _T_2982 | _T_2728; // @[Mux.scala 27:72] - wire _T_2322 = btb_rd_addr_f == 8'h69; // @[ifu_bp_ctl.scala 417:77] + wire _T_2322 = btb_rd_addr_f == 8'h69; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_105; // @[lib.scala 358:16] wire [21:0] _T_2729 = _T_2322 ? btb_bank0_rd_data_way0_out_105 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2984 = _T_2983 | _T_2729; // @[Mux.scala 27:72] - wire _T_2324 = btb_rd_addr_f == 8'h6a; // @[ifu_bp_ctl.scala 417:77] + wire _T_2324 = btb_rd_addr_f == 8'h6a; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_106; // @[lib.scala 358:16] wire [21:0] _T_2730 = _T_2324 ? btb_bank0_rd_data_way0_out_106 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2985 = _T_2984 | _T_2730; // @[Mux.scala 27:72] - wire _T_2326 = btb_rd_addr_f == 8'h6b; // @[ifu_bp_ctl.scala 417:77] + wire _T_2326 = btb_rd_addr_f == 8'h6b; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_107; // @[lib.scala 358:16] wire [21:0] _T_2731 = _T_2326 ? btb_bank0_rd_data_way0_out_107 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2986 = _T_2985 | _T_2731; // @[Mux.scala 27:72] - wire _T_2328 = btb_rd_addr_f == 8'h6c; // @[ifu_bp_ctl.scala 417:77] + wire _T_2328 = btb_rd_addr_f == 8'h6c; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_108; // @[lib.scala 358:16] wire [21:0] _T_2732 = _T_2328 ? btb_bank0_rd_data_way0_out_108 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2987 = _T_2986 | _T_2732; // @[Mux.scala 27:72] - wire _T_2330 = btb_rd_addr_f == 8'h6d; // @[ifu_bp_ctl.scala 417:77] + wire _T_2330 = btb_rd_addr_f == 8'h6d; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_109; // @[lib.scala 358:16] wire [21:0] _T_2733 = _T_2330 ? btb_bank0_rd_data_way0_out_109 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2988 = _T_2987 | _T_2733; // @[Mux.scala 27:72] - wire _T_2332 = btb_rd_addr_f == 8'h6e; // @[ifu_bp_ctl.scala 417:77] + wire _T_2332 = btb_rd_addr_f == 8'h6e; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_110; // @[lib.scala 358:16] wire [21:0] _T_2734 = _T_2332 ? btb_bank0_rd_data_way0_out_110 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2989 = _T_2988 | _T_2734; // @[Mux.scala 27:72] - wire _T_2334 = btb_rd_addr_f == 8'h6f; // @[ifu_bp_ctl.scala 417:77] + wire _T_2334 = btb_rd_addr_f == 8'h6f; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_111; // @[lib.scala 358:16] wire [21:0] _T_2735 = _T_2334 ? btb_bank0_rd_data_way0_out_111 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2990 = _T_2989 | _T_2735; // @[Mux.scala 27:72] - wire _T_2336 = btb_rd_addr_f == 8'h70; // @[ifu_bp_ctl.scala 417:77] + wire _T_2336 = btb_rd_addr_f == 8'h70; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_112; // @[lib.scala 358:16] wire [21:0] _T_2736 = _T_2336 ? btb_bank0_rd_data_way0_out_112 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2991 = _T_2990 | _T_2736; // @[Mux.scala 27:72] - wire _T_2338 = btb_rd_addr_f == 8'h71; // @[ifu_bp_ctl.scala 417:77] + wire _T_2338 = btb_rd_addr_f == 8'h71; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_113; // @[lib.scala 358:16] wire [21:0] _T_2737 = _T_2338 ? btb_bank0_rd_data_way0_out_113 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2992 = _T_2991 | _T_2737; // @[Mux.scala 27:72] - wire _T_2340 = btb_rd_addr_f == 8'h72; // @[ifu_bp_ctl.scala 417:77] + wire _T_2340 = btb_rd_addr_f == 8'h72; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_114; // @[lib.scala 358:16] wire [21:0] _T_2738 = _T_2340 ? btb_bank0_rd_data_way0_out_114 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2993 = _T_2992 | _T_2738; // @[Mux.scala 27:72] - wire _T_2342 = btb_rd_addr_f == 8'h73; // @[ifu_bp_ctl.scala 417:77] + wire _T_2342 = btb_rd_addr_f == 8'h73; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_115; // @[lib.scala 358:16] wire [21:0] _T_2739 = _T_2342 ? btb_bank0_rd_data_way0_out_115 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2994 = _T_2993 | _T_2739; // @[Mux.scala 27:72] - wire _T_2344 = btb_rd_addr_f == 8'h74; // @[ifu_bp_ctl.scala 417:77] + wire _T_2344 = btb_rd_addr_f == 8'h74; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_116; // @[lib.scala 358:16] wire [21:0] _T_2740 = _T_2344 ? btb_bank0_rd_data_way0_out_116 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2995 = _T_2994 | _T_2740; // @[Mux.scala 27:72] - wire _T_2346 = btb_rd_addr_f == 8'h75; // @[ifu_bp_ctl.scala 417:77] + wire _T_2346 = btb_rd_addr_f == 8'h75; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_117; // @[lib.scala 358:16] wire [21:0] _T_2741 = _T_2346 ? btb_bank0_rd_data_way0_out_117 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2996 = _T_2995 | _T_2741; // @[Mux.scala 27:72] - wire _T_2348 = btb_rd_addr_f == 8'h76; // @[ifu_bp_ctl.scala 417:77] + wire _T_2348 = btb_rd_addr_f == 8'h76; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_118; // @[lib.scala 358:16] wire [21:0] _T_2742 = _T_2348 ? btb_bank0_rd_data_way0_out_118 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2997 = _T_2996 | _T_2742; // @[Mux.scala 27:72] - wire _T_2350 = btb_rd_addr_f == 8'h77; // @[ifu_bp_ctl.scala 417:77] + wire _T_2350 = btb_rd_addr_f == 8'h77; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_119; // @[lib.scala 358:16] wire [21:0] _T_2743 = _T_2350 ? btb_bank0_rd_data_way0_out_119 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2998 = _T_2997 | _T_2743; // @[Mux.scala 27:72] - wire _T_2352 = btb_rd_addr_f == 8'h78; // @[ifu_bp_ctl.scala 417:77] + wire _T_2352 = btb_rd_addr_f == 8'h78; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_120; // @[lib.scala 358:16] wire [21:0] _T_2744 = _T_2352 ? btb_bank0_rd_data_way0_out_120 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_2999 = _T_2998 | _T_2744; // @[Mux.scala 27:72] - wire _T_2354 = btb_rd_addr_f == 8'h79; // @[ifu_bp_ctl.scala 417:77] + wire _T_2354 = btb_rd_addr_f == 8'h79; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_121; // @[lib.scala 358:16] wire [21:0] _T_2745 = _T_2354 ? btb_bank0_rd_data_way0_out_121 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3000 = _T_2999 | _T_2745; // @[Mux.scala 27:72] - wire _T_2356 = btb_rd_addr_f == 8'h7a; // @[ifu_bp_ctl.scala 417:77] + wire _T_2356 = btb_rd_addr_f == 8'h7a; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_122; // @[lib.scala 358:16] wire [21:0] _T_2746 = _T_2356 ? btb_bank0_rd_data_way0_out_122 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3001 = _T_3000 | _T_2746; // @[Mux.scala 27:72] - wire _T_2358 = btb_rd_addr_f == 8'h7b; // @[ifu_bp_ctl.scala 417:77] + wire _T_2358 = btb_rd_addr_f == 8'h7b; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_123; // @[lib.scala 358:16] wire [21:0] _T_2747 = _T_2358 ? btb_bank0_rd_data_way0_out_123 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3002 = _T_3001 | _T_2747; // @[Mux.scala 27:72] - wire _T_2360 = btb_rd_addr_f == 8'h7c; // @[ifu_bp_ctl.scala 417:77] + wire _T_2360 = btb_rd_addr_f == 8'h7c; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_124; // @[lib.scala 358:16] wire [21:0] _T_2748 = _T_2360 ? btb_bank0_rd_data_way0_out_124 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3003 = _T_3002 | _T_2748; // @[Mux.scala 27:72] - wire _T_2362 = btb_rd_addr_f == 8'h7d; // @[ifu_bp_ctl.scala 417:77] + wire _T_2362 = btb_rd_addr_f == 8'h7d; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_125; // @[lib.scala 358:16] wire [21:0] _T_2749 = _T_2362 ? btb_bank0_rd_data_way0_out_125 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3004 = _T_3003 | _T_2749; // @[Mux.scala 27:72] - wire _T_2364 = btb_rd_addr_f == 8'h7e; // @[ifu_bp_ctl.scala 417:77] + wire _T_2364 = btb_rd_addr_f == 8'h7e; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_126; // @[lib.scala 358:16] wire [21:0] _T_2750 = _T_2364 ? btb_bank0_rd_data_way0_out_126 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3005 = _T_3004 | _T_2750; // @[Mux.scala 27:72] - wire _T_2366 = btb_rd_addr_f == 8'h7f; // @[ifu_bp_ctl.scala 417:77] + wire _T_2366 = btb_rd_addr_f == 8'h7f; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_127; // @[lib.scala 358:16] wire [21:0] _T_2751 = _T_2366 ? btb_bank0_rd_data_way0_out_127 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3006 = _T_3005 | _T_2751; // @[Mux.scala 27:72] - wire _T_2368 = btb_rd_addr_f == 8'h80; // @[ifu_bp_ctl.scala 417:77] + wire _T_2368 = btb_rd_addr_f == 8'h80; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_128; // @[lib.scala 358:16] wire [21:0] _T_2752 = _T_2368 ? btb_bank0_rd_data_way0_out_128 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3007 = _T_3006 | _T_2752; // @[Mux.scala 27:72] - wire _T_2370 = btb_rd_addr_f == 8'h81; // @[ifu_bp_ctl.scala 417:77] + wire _T_2370 = btb_rd_addr_f == 8'h81; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_129; // @[lib.scala 358:16] wire [21:0] _T_2753 = _T_2370 ? btb_bank0_rd_data_way0_out_129 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3008 = _T_3007 | _T_2753; // @[Mux.scala 27:72] - wire _T_2372 = btb_rd_addr_f == 8'h82; // @[ifu_bp_ctl.scala 417:77] + wire _T_2372 = btb_rd_addr_f == 8'h82; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_130; // @[lib.scala 358:16] wire [21:0] _T_2754 = _T_2372 ? btb_bank0_rd_data_way0_out_130 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3009 = _T_3008 | _T_2754; // @[Mux.scala 27:72] - wire _T_2374 = btb_rd_addr_f == 8'h83; // @[ifu_bp_ctl.scala 417:77] + wire _T_2374 = btb_rd_addr_f == 8'h83; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_131; // @[lib.scala 358:16] wire [21:0] _T_2755 = _T_2374 ? btb_bank0_rd_data_way0_out_131 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3010 = _T_3009 | _T_2755; // @[Mux.scala 27:72] - wire _T_2376 = btb_rd_addr_f == 8'h84; // @[ifu_bp_ctl.scala 417:77] + wire _T_2376 = btb_rd_addr_f == 8'h84; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_132; // @[lib.scala 358:16] wire [21:0] _T_2756 = _T_2376 ? btb_bank0_rd_data_way0_out_132 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3011 = _T_3010 | _T_2756; // @[Mux.scala 27:72] - wire _T_2378 = btb_rd_addr_f == 8'h85; // @[ifu_bp_ctl.scala 417:77] + wire _T_2378 = btb_rd_addr_f == 8'h85; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_133; // @[lib.scala 358:16] wire [21:0] _T_2757 = _T_2378 ? btb_bank0_rd_data_way0_out_133 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3012 = _T_3011 | _T_2757; // @[Mux.scala 27:72] - wire _T_2380 = btb_rd_addr_f == 8'h86; // @[ifu_bp_ctl.scala 417:77] + wire _T_2380 = btb_rd_addr_f == 8'h86; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_134; // @[lib.scala 358:16] wire [21:0] _T_2758 = _T_2380 ? btb_bank0_rd_data_way0_out_134 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3013 = _T_3012 | _T_2758; // @[Mux.scala 27:72] - wire _T_2382 = btb_rd_addr_f == 8'h87; // @[ifu_bp_ctl.scala 417:77] + wire _T_2382 = btb_rd_addr_f == 8'h87; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_135; // @[lib.scala 358:16] wire [21:0] _T_2759 = _T_2382 ? btb_bank0_rd_data_way0_out_135 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3014 = _T_3013 | _T_2759; // @[Mux.scala 27:72] - wire _T_2384 = btb_rd_addr_f == 8'h88; // @[ifu_bp_ctl.scala 417:77] + wire _T_2384 = btb_rd_addr_f == 8'h88; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_136; // @[lib.scala 358:16] wire [21:0] _T_2760 = _T_2384 ? btb_bank0_rd_data_way0_out_136 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3015 = _T_3014 | _T_2760; // @[Mux.scala 27:72] - wire _T_2386 = btb_rd_addr_f == 8'h89; // @[ifu_bp_ctl.scala 417:77] + wire _T_2386 = btb_rd_addr_f == 8'h89; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_137; // @[lib.scala 358:16] wire [21:0] _T_2761 = _T_2386 ? btb_bank0_rd_data_way0_out_137 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3016 = _T_3015 | _T_2761; // @[Mux.scala 27:72] - wire _T_2388 = btb_rd_addr_f == 8'h8a; // @[ifu_bp_ctl.scala 417:77] + wire _T_2388 = btb_rd_addr_f == 8'h8a; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_138; // @[lib.scala 358:16] wire [21:0] _T_2762 = _T_2388 ? btb_bank0_rd_data_way0_out_138 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3017 = _T_3016 | _T_2762; // @[Mux.scala 27:72] - wire _T_2390 = btb_rd_addr_f == 8'h8b; // @[ifu_bp_ctl.scala 417:77] + wire _T_2390 = btb_rd_addr_f == 8'h8b; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_139; // @[lib.scala 358:16] wire [21:0] _T_2763 = _T_2390 ? btb_bank0_rd_data_way0_out_139 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3018 = _T_3017 | _T_2763; // @[Mux.scala 27:72] - wire _T_2392 = btb_rd_addr_f == 8'h8c; // @[ifu_bp_ctl.scala 417:77] + wire _T_2392 = btb_rd_addr_f == 8'h8c; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_140; // @[lib.scala 358:16] wire [21:0] _T_2764 = _T_2392 ? btb_bank0_rd_data_way0_out_140 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3019 = _T_3018 | _T_2764; // @[Mux.scala 27:72] - wire _T_2394 = btb_rd_addr_f == 8'h8d; // @[ifu_bp_ctl.scala 417:77] + wire _T_2394 = btb_rd_addr_f == 8'h8d; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_141; // @[lib.scala 358:16] wire [21:0] _T_2765 = _T_2394 ? btb_bank0_rd_data_way0_out_141 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3020 = _T_3019 | _T_2765; // @[Mux.scala 27:72] - wire _T_2396 = btb_rd_addr_f == 8'h8e; // @[ifu_bp_ctl.scala 417:77] + wire _T_2396 = btb_rd_addr_f == 8'h8e; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_142; // @[lib.scala 358:16] wire [21:0] _T_2766 = _T_2396 ? btb_bank0_rd_data_way0_out_142 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3021 = _T_3020 | _T_2766; // @[Mux.scala 27:72] - wire _T_2398 = btb_rd_addr_f == 8'h8f; // @[ifu_bp_ctl.scala 417:77] + wire _T_2398 = btb_rd_addr_f == 8'h8f; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_143; // @[lib.scala 358:16] wire [21:0] _T_2767 = _T_2398 ? btb_bank0_rd_data_way0_out_143 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3022 = _T_3021 | _T_2767; // @[Mux.scala 27:72] - wire _T_2400 = btb_rd_addr_f == 8'h90; // @[ifu_bp_ctl.scala 417:77] + wire _T_2400 = btb_rd_addr_f == 8'h90; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_144; // @[lib.scala 358:16] wire [21:0] _T_2768 = _T_2400 ? btb_bank0_rd_data_way0_out_144 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3023 = _T_3022 | _T_2768; // @[Mux.scala 27:72] - wire _T_2402 = btb_rd_addr_f == 8'h91; // @[ifu_bp_ctl.scala 417:77] + wire _T_2402 = btb_rd_addr_f == 8'h91; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_145; // @[lib.scala 358:16] wire [21:0] _T_2769 = _T_2402 ? btb_bank0_rd_data_way0_out_145 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3024 = _T_3023 | _T_2769; // @[Mux.scala 27:72] - wire _T_2404 = btb_rd_addr_f == 8'h92; // @[ifu_bp_ctl.scala 417:77] + wire _T_2404 = btb_rd_addr_f == 8'h92; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_146; // @[lib.scala 358:16] wire [21:0] _T_2770 = _T_2404 ? btb_bank0_rd_data_way0_out_146 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3025 = _T_3024 | _T_2770; // @[Mux.scala 27:72] - wire _T_2406 = btb_rd_addr_f == 8'h93; // @[ifu_bp_ctl.scala 417:77] + wire _T_2406 = btb_rd_addr_f == 8'h93; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_147; // @[lib.scala 358:16] wire [21:0] _T_2771 = _T_2406 ? btb_bank0_rd_data_way0_out_147 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3026 = _T_3025 | _T_2771; // @[Mux.scala 27:72] - wire _T_2408 = btb_rd_addr_f == 8'h94; // @[ifu_bp_ctl.scala 417:77] + wire _T_2408 = btb_rd_addr_f == 8'h94; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_148; // @[lib.scala 358:16] wire [21:0] _T_2772 = _T_2408 ? btb_bank0_rd_data_way0_out_148 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3027 = _T_3026 | _T_2772; // @[Mux.scala 27:72] - wire _T_2410 = btb_rd_addr_f == 8'h95; // @[ifu_bp_ctl.scala 417:77] + wire _T_2410 = btb_rd_addr_f == 8'h95; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_149; // @[lib.scala 358:16] wire [21:0] _T_2773 = _T_2410 ? btb_bank0_rd_data_way0_out_149 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3028 = _T_3027 | _T_2773; // @[Mux.scala 27:72] - wire _T_2412 = btb_rd_addr_f == 8'h96; // @[ifu_bp_ctl.scala 417:77] + wire _T_2412 = btb_rd_addr_f == 8'h96; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_150; // @[lib.scala 358:16] wire [21:0] _T_2774 = _T_2412 ? btb_bank0_rd_data_way0_out_150 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3029 = _T_3028 | _T_2774; // @[Mux.scala 27:72] - wire _T_2414 = btb_rd_addr_f == 8'h97; // @[ifu_bp_ctl.scala 417:77] + wire _T_2414 = btb_rd_addr_f == 8'h97; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_151; // @[lib.scala 358:16] wire [21:0] _T_2775 = _T_2414 ? btb_bank0_rd_data_way0_out_151 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3030 = _T_3029 | _T_2775; // @[Mux.scala 27:72] - wire _T_2416 = btb_rd_addr_f == 8'h98; // @[ifu_bp_ctl.scala 417:77] + wire _T_2416 = btb_rd_addr_f == 8'h98; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_152; // @[lib.scala 358:16] wire [21:0] _T_2776 = _T_2416 ? btb_bank0_rd_data_way0_out_152 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3031 = _T_3030 | _T_2776; // @[Mux.scala 27:72] - wire _T_2418 = btb_rd_addr_f == 8'h99; // @[ifu_bp_ctl.scala 417:77] + wire _T_2418 = btb_rd_addr_f == 8'h99; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_153; // @[lib.scala 358:16] wire [21:0] _T_2777 = _T_2418 ? btb_bank0_rd_data_way0_out_153 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3032 = _T_3031 | _T_2777; // @[Mux.scala 27:72] - wire _T_2420 = btb_rd_addr_f == 8'h9a; // @[ifu_bp_ctl.scala 417:77] + wire _T_2420 = btb_rd_addr_f == 8'h9a; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_154; // @[lib.scala 358:16] wire [21:0] _T_2778 = _T_2420 ? btb_bank0_rd_data_way0_out_154 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3033 = _T_3032 | _T_2778; // @[Mux.scala 27:72] - wire _T_2422 = btb_rd_addr_f == 8'h9b; // @[ifu_bp_ctl.scala 417:77] + wire _T_2422 = btb_rd_addr_f == 8'h9b; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_155; // @[lib.scala 358:16] wire [21:0] _T_2779 = _T_2422 ? btb_bank0_rd_data_way0_out_155 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3034 = _T_3033 | _T_2779; // @[Mux.scala 27:72] - wire _T_2424 = btb_rd_addr_f == 8'h9c; // @[ifu_bp_ctl.scala 417:77] + wire _T_2424 = btb_rd_addr_f == 8'h9c; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_156; // @[lib.scala 358:16] wire [21:0] _T_2780 = _T_2424 ? btb_bank0_rd_data_way0_out_156 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3035 = _T_3034 | _T_2780; // @[Mux.scala 27:72] - wire _T_2426 = btb_rd_addr_f == 8'h9d; // @[ifu_bp_ctl.scala 417:77] + wire _T_2426 = btb_rd_addr_f == 8'h9d; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_157; // @[lib.scala 358:16] wire [21:0] _T_2781 = _T_2426 ? btb_bank0_rd_data_way0_out_157 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3036 = _T_3035 | _T_2781; // @[Mux.scala 27:72] - wire _T_2428 = btb_rd_addr_f == 8'h9e; // @[ifu_bp_ctl.scala 417:77] + wire _T_2428 = btb_rd_addr_f == 8'h9e; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_158; // @[lib.scala 358:16] wire [21:0] _T_2782 = _T_2428 ? btb_bank0_rd_data_way0_out_158 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3037 = _T_3036 | _T_2782; // @[Mux.scala 27:72] - wire _T_2430 = btb_rd_addr_f == 8'h9f; // @[ifu_bp_ctl.scala 417:77] + wire _T_2430 = btb_rd_addr_f == 8'h9f; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_159; // @[lib.scala 358:16] wire [21:0] _T_2783 = _T_2430 ? btb_bank0_rd_data_way0_out_159 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3038 = _T_3037 | _T_2783; // @[Mux.scala 27:72] - wire _T_2432 = btb_rd_addr_f == 8'ha0; // @[ifu_bp_ctl.scala 417:77] + wire _T_2432 = btb_rd_addr_f == 8'ha0; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_160; // @[lib.scala 358:16] wire [21:0] _T_2784 = _T_2432 ? btb_bank0_rd_data_way0_out_160 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3039 = _T_3038 | _T_2784; // @[Mux.scala 27:72] - wire _T_2434 = btb_rd_addr_f == 8'ha1; // @[ifu_bp_ctl.scala 417:77] + wire _T_2434 = btb_rd_addr_f == 8'ha1; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_161; // @[lib.scala 358:16] wire [21:0] _T_2785 = _T_2434 ? btb_bank0_rd_data_way0_out_161 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3040 = _T_3039 | _T_2785; // @[Mux.scala 27:72] - wire _T_2436 = btb_rd_addr_f == 8'ha2; // @[ifu_bp_ctl.scala 417:77] + wire _T_2436 = btb_rd_addr_f == 8'ha2; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_162; // @[lib.scala 358:16] wire [21:0] _T_2786 = _T_2436 ? btb_bank0_rd_data_way0_out_162 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3041 = _T_3040 | _T_2786; // @[Mux.scala 27:72] - wire _T_2438 = btb_rd_addr_f == 8'ha3; // @[ifu_bp_ctl.scala 417:77] + wire _T_2438 = btb_rd_addr_f == 8'ha3; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_163; // @[lib.scala 358:16] wire [21:0] _T_2787 = _T_2438 ? btb_bank0_rd_data_way0_out_163 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3042 = _T_3041 | _T_2787; // @[Mux.scala 27:72] - wire _T_2440 = btb_rd_addr_f == 8'ha4; // @[ifu_bp_ctl.scala 417:77] + wire _T_2440 = btb_rd_addr_f == 8'ha4; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_164; // @[lib.scala 358:16] wire [21:0] _T_2788 = _T_2440 ? btb_bank0_rd_data_way0_out_164 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3043 = _T_3042 | _T_2788; // @[Mux.scala 27:72] - wire _T_2442 = btb_rd_addr_f == 8'ha5; // @[ifu_bp_ctl.scala 417:77] + wire _T_2442 = btb_rd_addr_f == 8'ha5; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_165; // @[lib.scala 358:16] wire [21:0] _T_2789 = _T_2442 ? btb_bank0_rd_data_way0_out_165 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3044 = _T_3043 | _T_2789; // @[Mux.scala 27:72] - wire _T_2444 = btb_rd_addr_f == 8'ha6; // @[ifu_bp_ctl.scala 417:77] + wire _T_2444 = btb_rd_addr_f == 8'ha6; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_166; // @[lib.scala 358:16] wire [21:0] _T_2790 = _T_2444 ? btb_bank0_rd_data_way0_out_166 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3045 = _T_3044 | _T_2790; // @[Mux.scala 27:72] - wire _T_2446 = btb_rd_addr_f == 8'ha7; // @[ifu_bp_ctl.scala 417:77] + wire _T_2446 = btb_rd_addr_f == 8'ha7; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_167; // @[lib.scala 358:16] wire [21:0] _T_2791 = _T_2446 ? btb_bank0_rd_data_way0_out_167 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3046 = _T_3045 | _T_2791; // @[Mux.scala 27:72] - wire _T_2448 = btb_rd_addr_f == 8'ha8; // @[ifu_bp_ctl.scala 417:77] + wire _T_2448 = btb_rd_addr_f == 8'ha8; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_168; // @[lib.scala 358:16] wire [21:0] _T_2792 = _T_2448 ? btb_bank0_rd_data_way0_out_168 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3047 = _T_3046 | _T_2792; // @[Mux.scala 27:72] - wire _T_2450 = btb_rd_addr_f == 8'ha9; // @[ifu_bp_ctl.scala 417:77] + wire _T_2450 = btb_rd_addr_f == 8'ha9; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_169; // @[lib.scala 358:16] wire [21:0] _T_2793 = _T_2450 ? btb_bank0_rd_data_way0_out_169 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3048 = _T_3047 | _T_2793; // @[Mux.scala 27:72] - wire _T_2452 = btb_rd_addr_f == 8'haa; // @[ifu_bp_ctl.scala 417:77] + wire _T_2452 = btb_rd_addr_f == 8'haa; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_170; // @[lib.scala 358:16] wire [21:0] _T_2794 = _T_2452 ? btb_bank0_rd_data_way0_out_170 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3049 = _T_3048 | _T_2794; // @[Mux.scala 27:72] - wire _T_2454 = btb_rd_addr_f == 8'hab; // @[ifu_bp_ctl.scala 417:77] + wire _T_2454 = btb_rd_addr_f == 8'hab; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_171; // @[lib.scala 358:16] wire [21:0] _T_2795 = _T_2454 ? btb_bank0_rd_data_way0_out_171 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3050 = _T_3049 | _T_2795; // @[Mux.scala 27:72] - wire _T_2456 = btb_rd_addr_f == 8'hac; // @[ifu_bp_ctl.scala 417:77] + wire _T_2456 = btb_rd_addr_f == 8'hac; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_172; // @[lib.scala 358:16] wire [21:0] _T_2796 = _T_2456 ? btb_bank0_rd_data_way0_out_172 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3051 = _T_3050 | _T_2796; // @[Mux.scala 27:72] - wire _T_2458 = btb_rd_addr_f == 8'had; // @[ifu_bp_ctl.scala 417:77] + wire _T_2458 = btb_rd_addr_f == 8'had; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_173; // @[lib.scala 358:16] wire [21:0] _T_2797 = _T_2458 ? btb_bank0_rd_data_way0_out_173 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3052 = _T_3051 | _T_2797; // @[Mux.scala 27:72] - wire _T_2460 = btb_rd_addr_f == 8'hae; // @[ifu_bp_ctl.scala 417:77] + wire _T_2460 = btb_rd_addr_f == 8'hae; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_174; // @[lib.scala 358:16] wire [21:0] _T_2798 = _T_2460 ? btb_bank0_rd_data_way0_out_174 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3053 = _T_3052 | _T_2798; // @[Mux.scala 27:72] - wire _T_2462 = btb_rd_addr_f == 8'haf; // @[ifu_bp_ctl.scala 417:77] + wire _T_2462 = btb_rd_addr_f == 8'haf; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_175; // @[lib.scala 358:16] wire [21:0] _T_2799 = _T_2462 ? btb_bank0_rd_data_way0_out_175 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3054 = _T_3053 | _T_2799; // @[Mux.scala 27:72] - wire _T_2464 = btb_rd_addr_f == 8'hb0; // @[ifu_bp_ctl.scala 417:77] + wire _T_2464 = btb_rd_addr_f == 8'hb0; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_176; // @[lib.scala 358:16] wire [21:0] _T_2800 = _T_2464 ? btb_bank0_rd_data_way0_out_176 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3055 = _T_3054 | _T_2800; // @[Mux.scala 27:72] - wire _T_2466 = btb_rd_addr_f == 8'hb1; // @[ifu_bp_ctl.scala 417:77] + wire _T_2466 = btb_rd_addr_f == 8'hb1; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_177; // @[lib.scala 358:16] wire [21:0] _T_2801 = _T_2466 ? btb_bank0_rd_data_way0_out_177 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3056 = _T_3055 | _T_2801; // @[Mux.scala 27:72] - wire _T_2468 = btb_rd_addr_f == 8'hb2; // @[ifu_bp_ctl.scala 417:77] + wire _T_2468 = btb_rd_addr_f == 8'hb2; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_178; // @[lib.scala 358:16] wire [21:0] _T_2802 = _T_2468 ? btb_bank0_rd_data_way0_out_178 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3057 = _T_3056 | _T_2802; // @[Mux.scala 27:72] - wire _T_2470 = btb_rd_addr_f == 8'hb3; // @[ifu_bp_ctl.scala 417:77] + wire _T_2470 = btb_rd_addr_f == 8'hb3; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_179; // @[lib.scala 358:16] wire [21:0] _T_2803 = _T_2470 ? btb_bank0_rd_data_way0_out_179 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3058 = _T_3057 | _T_2803; // @[Mux.scala 27:72] - wire _T_2472 = btb_rd_addr_f == 8'hb4; // @[ifu_bp_ctl.scala 417:77] + wire _T_2472 = btb_rd_addr_f == 8'hb4; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_180; // @[lib.scala 358:16] wire [21:0] _T_2804 = _T_2472 ? btb_bank0_rd_data_way0_out_180 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3059 = _T_3058 | _T_2804; // @[Mux.scala 27:72] - wire _T_2474 = btb_rd_addr_f == 8'hb5; // @[ifu_bp_ctl.scala 417:77] + wire _T_2474 = btb_rd_addr_f == 8'hb5; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_181; // @[lib.scala 358:16] wire [21:0] _T_2805 = _T_2474 ? btb_bank0_rd_data_way0_out_181 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3060 = _T_3059 | _T_2805; // @[Mux.scala 27:72] - wire _T_2476 = btb_rd_addr_f == 8'hb6; // @[ifu_bp_ctl.scala 417:77] + wire _T_2476 = btb_rd_addr_f == 8'hb6; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_182; // @[lib.scala 358:16] wire [21:0] _T_2806 = _T_2476 ? btb_bank0_rd_data_way0_out_182 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3061 = _T_3060 | _T_2806; // @[Mux.scala 27:72] - wire _T_2478 = btb_rd_addr_f == 8'hb7; // @[ifu_bp_ctl.scala 417:77] + wire _T_2478 = btb_rd_addr_f == 8'hb7; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_183; // @[lib.scala 358:16] wire [21:0] _T_2807 = _T_2478 ? btb_bank0_rd_data_way0_out_183 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3062 = _T_3061 | _T_2807; // @[Mux.scala 27:72] - wire _T_2480 = btb_rd_addr_f == 8'hb8; // @[ifu_bp_ctl.scala 417:77] + wire _T_2480 = btb_rd_addr_f == 8'hb8; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_184; // @[lib.scala 358:16] wire [21:0] _T_2808 = _T_2480 ? btb_bank0_rd_data_way0_out_184 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3063 = _T_3062 | _T_2808; // @[Mux.scala 27:72] - wire _T_2482 = btb_rd_addr_f == 8'hb9; // @[ifu_bp_ctl.scala 417:77] + wire _T_2482 = btb_rd_addr_f == 8'hb9; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_185; // @[lib.scala 358:16] wire [21:0] _T_2809 = _T_2482 ? btb_bank0_rd_data_way0_out_185 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3064 = _T_3063 | _T_2809; // @[Mux.scala 27:72] - wire _T_2484 = btb_rd_addr_f == 8'hba; // @[ifu_bp_ctl.scala 417:77] + wire _T_2484 = btb_rd_addr_f == 8'hba; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_186; // @[lib.scala 358:16] wire [21:0] _T_2810 = _T_2484 ? btb_bank0_rd_data_way0_out_186 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3065 = _T_3064 | _T_2810; // @[Mux.scala 27:72] - wire _T_2486 = btb_rd_addr_f == 8'hbb; // @[ifu_bp_ctl.scala 417:77] + wire _T_2486 = btb_rd_addr_f == 8'hbb; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_187; // @[lib.scala 358:16] wire [21:0] _T_2811 = _T_2486 ? btb_bank0_rd_data_way0_out_187 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3066 = _T_3065 | _T_2811; // @[Mux.scala 27:72] - wire _T_2488 = btb_rd_addr_f == 8'hbc; // @[ifu_bp_ctl.scala 417:77] + wire _T_2488 = btb_rd_addr_f == 8'hbc; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_188; // @[lib.scala 358:16] wire [21:0] _T_2812 = _T_2488 ? btb_bank0_rd_data_way0_out_188 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3067 = _T_3066 | _T_2812; // @[Mux.scala 27:72] - wire _T_2490 = btb_rd_addr_f == 8'hbd; // @[ifu_bp_ctl.scala 417:77] + wire _T_2490 = btb_rd_addr_f == 8'hbd; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_189; // @[lib.scala 358:16] wire [21:0] _T_2813 = _T_2490 ? btb_bank0_rd_data_way0_out_189 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3068 = _T_3067 | _T_2813; // @[Mux.scala 27:72] - wire _T_2492 = btb_rd_addr_f == 8'hbe; // @[ifu_bp_ctl.scala 417:77] + wire _T_2492 = btb_rd_addr_f == 8'hbe; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_190; // @[lib.scala 358:16] wire [21:0] _T_2814 = _T_2492 ? btb_bank0_rd_data_way0_out_190 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3069 = _T_3068 | _T_2814; // @[Mux.scala 27:72] - wire _T_2494 = btb_rd_addr_f == 8'hbf; // @[ifu_bp_ctl.scala 417:77] + wire _T_2494 = btb_rd_addr_f == 8'hbf; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_191; // @[lib.scala 358:16] wire [21:0] _T_2815 = _T_2494 ? btb_bank0_rd_data_way0_out_191 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3070 = _T_3069 | _T_2815; // @[Mux.scala 27:72] - wire _T_2496 = btb_rd_addr_f == 8'hc0; // @[ifu_bp_ctl.scala 417:77] + wire _T_2496 = btb_rd_addr_f == 8'hc0; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_192; // @[lib.scala 358:16] wire [21:0] _T_2816 = _T_2496 ? btb_bank0_rd_data_way0_out_192 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3071 = _T_3070 | _T_2816; // @[Mux.scala 27:72] - wire _T_2498 = btb_rd_addr_f == 8'hc1; // @[ifu_bp_ctl.scala 417:77] + wire _T_2498 = btb_rd_addr_f == 8'hc1; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_193; // @[lib.scala 358:16] wire [21:0] _T_2817 = _T_2498 ? btb_bank0_rd_data_way0_out_193 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3072 = _T_3071 | _T_2817; // @[Mux.scala 27:72] - wire _T_2500 = btb_rd_addr_f == 8'hc2; // @[ifu_bp_ctl.scala 417:77] + wire _T_2500 = btb_rd_addr_f == 8'hc2; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_194; // @[lib.scala 358:16] wire [21:0] _T_2818 = _T_2500 ? btb_bank0_rd_data_way0_out_194 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3073 = _T_3072 | _T_2818; // @[Mux.scala 27:72] - wire _T_2502 = btb_rd_addr_f == 8'hc3; // @[ifu_bp_ctl.scala 417:77] + wire _T_2502 = btb_rd_addr_f == 8'hc3; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_195; // @[lib.scala 358:16] wire [21:0] _T_2819 = _T_2502 ? btb_bank0_rd_data_way0_out_195 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3074 = _T_3073 | _T_2819; // @[Mux.scala 27:72] - wire _T_2504 = btb_rd_addr_f == 8'hc4; // @[ifu_bp_ctl.scala 417:77] + wire _T_2504 = btb_rd_addr_f == 8'hc4; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_196; // @[lib.scala 358:16] wire [21:0] _T_2820 = _T_2504 ? btb_bank0_rd_data_way0_out_196 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3075 = _T_3074 | _T_2820; // @[Mux.scala 27:72] - wire _T_2506 = btb_rd_addr_f == 8'hc5; // @[ifu_bp_ctl.scala 417:77] + wire _T_2506 = btb_rd_addr_f == 8'hc5; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_197; // @[lib.scala 358:16] wire [21:0] _T_2821 = _T_2506 ? btb_bank0_rd_data_way0_out_197 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3076 = _T_3075 | _T_2821; // @[Mux.scala 27:72] - wire _T_2508 = btb_rd_addr_f == 8'hc6; // @[ifu_bp_ctl.scala 417:77] + wire _T_2508 = btb_rd_addr_f == 8'hc6; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_198; // @[lib.scala 358:16] wire [21:0] _T_2822 = _T_2508 ? btb_bank0_rd_data_way0_out_198 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3077 = _T_3076 | _T_2822; // @[Mux.scala 27:72] - wire _T_2510 = btb_rd_addr_f == 8'hc7; // @[ifu_bp_ctl.scala 417:77] + wire _T_2510 = btb_rd_addr_f == 8'hc7; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_199; // @[lib.scala 358:16] wire [21:0] _T_2823 = _T_2510 ? btb_bank0_rd_data_way0_out_199 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3078 = _T_3077 | _T_2823; // @[Mux.scala 27:72] - wire _T_2512 = btb_rd_addr_f == 8'hc8; // @[ifu_bp_ctl.scala 417:77] + wire _T_2512 = btb_rd_addr_f == 8'hc8; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_200; // @[lib.scala 358:16] wire [21:0] _T_2824 = _T_2512 ? btb_bank0_rd_data_way0_out_200 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3079 = _T_3078 | _T_2824; // @[Mux.scala 27:72] - wire _T_2514 = btb_rd_addr_f == 8'hc9; // @[ifu_bp_ctl.scala 417:77] + wire _T_2514 = btb_rd_addr_f == 8'hc9; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_201; // @[lib.scala 358:16] wire [21:0] _T_2825 = _T_2514 ? btb_bank0_rd_data_way0_out_201 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3080 = _T_3079 | _T_2825; // @[Mux.scala 27:72] - wire _T_2516 = btb_rd_addr_f == 8'hca; // @[ifu_bp_ctl.scala 417:77] + wire _T_2516 = btb_rd_addr_f == 8'hca; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_202; // @[lib.scala 358:16] wire [21:0] _T_2826 = _T_2516 ? btb_bank0_rd_data_way0_out_202 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3081 = _T_3080 | _T_2826; // @[Mux.scala 27:72] - wire _T_2518 = btb_rd_addr_f == 8'hcb; // @[ifu_bp_ctl.scala 417:77] + wire _T_2518 = btb_rd_addr_f == 8'hcb; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_203; // @[lib.scala 358:16] wire [21:0] _T_2827 = _T_2518 ? btb_bank0_rd_data_way0_out_203 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3082 = _T_3081 | _T_2827; // @[Mux.scala 27:72] - wire _T_2520 = btb_rd_addr_f == 8'hcc; // @[ifu_bp_ctl.scala 417:77] + wire _T_2520 = btb_rd_addr_f == 8'hcc; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_204; // @[lib.scala 358:16] wire [21:0] _T_2828 = _T_2520 ? btb_bank0_rd_data_way0_out_204 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3083 = _T_3082 | _T_2828; // @[Mux.scala 27:72] - wire _T_2522 = btb_rd_addr_f == 8'hcd; // @[ifu_bp_ctl.scala 417:77] + wire _T_2522 = btb_rd_addr_f == 8'hcd; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_205; // @[lib.scala 358:16] wire [21:0] _T_2829 = _T_2522 ? btb_bank0_rd_data_way0_out_205 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3084 = _T_3083 | _T_2829; // @[Mux.scala 27:72] - wire _T_2524 = btb_rd_addr_f == 8'hce; // @[ifu_bp_ctl.scala 417:77] + wire _T_2524 = btb_rd_addr_f == 8'hce; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_206; // @[lib.scala 358:16] wire [21:0] _T_2830 = _T_2524 ? btb_bank0_rd_data_way0_out_206 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3085 = _T_3084 | _T_2830; // @[Mux.scala 27:72] - wire _T_2526 = btb_rd_addr_f == 8'hcf; // @[ifu_bp_ctl.scala 417:77] + wire _T_2526 = btb_rd_addr_f == 8'hcf; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_207; // @[lib.scala 358:16] wire [21:0] _T_2831 = _T_2526 ? btb_bank0_rd_data_way0_out_207 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3086 = _T_3085 | _T_2831; // @[Mux.scala 27:72] - wire _T_2528 = btb_rd_addr_f == 8'hd0; // @[ifu_bp_ctl.scala 417:77] + wire _T_2528 = btb_rd_addr_f == 8'hd0; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_208; // @[lib.scala 358:16] wire [21:0] _T_2832 = _T_2528 ? btb_bank0_rd_data_way0_out_208 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3087 = _T_3086 | _T_2832; // @[Mux.scala 27:72] - wire _T_2530 = btb_rd_addr_f == 8'hd1; // @[ifu_bp_ctl.scala 417:77] + wire _T_2530 = btb_rd_addr_f == 8'hd1; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_209; // @[lib.scala 358:16] wire [21:0] _T_2833 = _T_2530 ? btb_bank0_rd_data_way0_out_209 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3088 = _T_3087 | _T_2833; // @[Mux.scala 27:72] - wire _T_2532 = btb_rd_addr_f == 8'hd2; // @[ifu_bp_ctl.scala 417:77] + wire _T_2532 = btb_rd_addr_f == 8'hd2; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_210; // @[lib.scala 358:16] wire [21:0] _T_2834 = _T_2532 ? btb_bank0_rd_data_way0_out_210 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3089 = _T_3088 | _T_2834; // @[Mux.scala 27:72] - wire _T_2534 = btb_rd_addr_f == 8'hd3; // @[ifu_bp_ctl.scala 417:77] + wire _T_2534 = btb_rd_addr_f == 8'hd3; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_211; // @[lib.scala 358:16] wire [21:0] _T_2835 = _T_2534 ? btb_bank0_rd_data_way0_out_211 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3090 = _T_3089 | _T_2835; // @[Mux.scala 27:72] - wire _T_2536 = btb_rd_addr_f == 8'hd4; // @[ifu_bp_ctl.scala 417:77] + wire _T_2536 = btb_rd_addr_f == 8'hd4; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_212; // @[lib.scala 358:16] wire [21:0] _T_2836 = _T_2536 ? btb_bank0_rd_data_way0_out_212 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3091 = _T_3090 | _T_2836; // @[Mux.scala 27:72] - wire _T_2538 = btb_rd_addr_f == 8'hd5; // @[ifu_bp_ctl.scala 417:77] + wire _T_2538 = btb_rd_addr_f == 8'hd5; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_213; // @[lib.scala 358:16] wire [21:0] _T_2837 = _T_2538 ? btb_bank0_rd_data_way0_out_213 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3092 = _T_3091 | _T_2837; // @[Mux.scala 27:72] - wire _T_2540 = btb_rd_addr_f == 8'hd6; // @[ifu_bp_ctl.scala 417:77] + wire _T_2540 = btb_rd_addr_f == 8'hd6; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_214; // @[lib.scala 358:16] wire [21:0] _T_2838 = _T_2540 ? btb_bank0_rd_data_way0_out_214 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3093 = _T_3092 | _T_2838; // @[Mux.scala 27:72] - wire _T_2542 = btb_rd_addr_f == 8'hd7; // @[ifu_bp_ctl.scala 417:77] + wire _T_2542 = btb_rd_addr_f == 8'hd7; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_215; // @[lib.scala 358:16] wire [21:0] _T_2839 = _T_2542 ? btb_bank0_rd_data_way0_out_215 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3094 = _T_3093 | _T_2839; // @[Mux.scala 27:72] - wire _T_2544 = btb_rd_addr_f == 8'hd8; // @[ifu_bp_ctl.scala 417:77] + wire _T_2544 = btb_rd_addr_f == 8'hd8; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_216; // @[lib.scala 358:16] wire [21:0] _T_2840 = _T_2544 ? btb_bank0_rd_data_way0_out_216 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3095 = _T_3094 | _T_2840; // @[Mux.scala 27:72] - wire _T_2546 = btb_rd_addr_f == 8'hd9; // @[ifu_bp_ctl.scala 417:77] + wire _T_2546 = btb_rd_addr_f == 8'hd9; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_217; // @[lib.scala 358:16] wire [21:0] _T_2841 = _T_2546 ? btb_bank0_rd_data_way0_out_217 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3096 = _T_3095 | _T_2841; // @[Mux.scala 27:72] - wire _T_2548 = btb_rd_addr_f == 8'hda; // @[ifu_bp_ctl.scala 417:77] + wire _T_2548 = btb_rd_addr_f == 8'hda; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_218; // @[lib.scala 358:16] wire [21:0] _T_2842 = _T_2548 ? btb_bank0_rd_data_way0_out_218 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3097 = _T_3096 | _T_2842; // @[Mux.scala 27:72] - wire _T_2550 = btb_rd_addr_f == 8'hdb; // @[ifu_bp_ctl.scala 417:77] + wire _T_2550 = btb_rd_addr_f == 8'hdb; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_219; // @[lib.scala 358:16] wire [21:0] _T_2843 = _T_2550 ? btb_bank0_rd_data_way0_out_219 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3098 = _T_3097 | _T_2843; // @[Mux.scala 27:72] - wire _T_2552 = btb_rd_addr_f == 8'hdc; // @[ifu_bp_ctl.scala 417:77] + wire _T_2552 = btb_rd_addr_f == 8'hdc; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_220; // @[lib.scala 358:16] wire [21:0] _T_2844 = _T_2552 ? btb_bank0_rd_data_way0_out_220 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3099 = _T_3098 | _T_2844; // @[Mux.scala 27:72] - wire _T_2554 = btb_rd_addr_f == 8'hdd; // @[ifu_bp_ctl.scala 417:77] + wire _T_2554 = btb_rd_addr_f == 8'hdd; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_221; // @[lib.scala 358:16] wire [21:0] _T_2845 = _T_2554 ? btb_bank0_rd_data_way0_out_221 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3100 = _T_3099 | _T_2845; // @[Mux.scala 27:72] - wire _T_2556 = btb_rd_addr_f == 8'hde; // @[ifu_bp_ctl.scala 417:77] + wire _T_2556 = btb_rd_addr_f == 8'hde; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_222; // @[lib.scala 358:16] wire [21:0] _T_2846 = _T_2556 ? btb_bank0_rd_data_way0_out_222 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3101 = _T_3100 | _T_2846; // @[Mux.scala 27:72] - wire _T_2558 = btb_rd_addr_f == 8'hdf; // @[ifu_bp_ctl.scala 417:77] + wire _T_2558 = btb_rd_addr_f == 8'hdf; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_223; // @[lib.scala 358:16] wire [21:0] _T_2847 = _T_2558 ? btb_bank0_rd_data_way0_out_223 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3102 = _T_3101 | _T_2847; // @[Mux.scala 27:72] - wire _T_2560 = btb_rd_addr_f == 8'he0; // @[ifu_bp_ctl.scala 417:77] + wire _T_2560 = btb_rd_addr_f == 8'he0; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_224; // @[lib.scala 358:16] wire [21:0] _T_2848 = _T_2560 ? btb_bank0_rd_data_way0_out_224 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3103 = _T_3102 | _T_2848; // @[Mux.scala 27:72] - wire _T_2562 = btb_rd_addr_f == 8'he1; // @[ifu_bp_ctl.scala 417:77] + wire _T_2562 = btb_rd_addr_f == 8'he1; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_225; // @[lib.scala 358:16] wire [21:0] _T_2849 = _T_2562 ? btb_bank0_rd_data_way0_out_225 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3104 = _T_3103 | _T_2849; // @[Mux.scala 27:72] - wire _T_2564 = btb_rd_addr_f == 8'he2; // @[ifu_bp_ctl.scala 417:77] + wire _T_2564 = btb_rd_addr_f == 8'he2; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_226; // @[lib.scala 358:16] wire [21:0] _T_2850 = _T_2564 ? btb_bank0_rd_data_way0_out_226 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3105 = _T_3104 | _T_2850; // @[Mux.scala 27:72] - wire _T_2566 = btb_rd_addr_f == 8'he3; // @[ifu_bp_ctl.scala 417:77] + wire _T_2566 = btb_rd_addr_f == 8'he3; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_227; // @[lib.scala 358:16] wire [21:0] _T_2851 = _T_2566 ? btb_bank0_rd_data_way0_out_227 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3106 = _T_3105 | _T_2851; // @[Mux.scala 27:72] - wire _T_2568 = btb_rd_addr_f == 8'he4; // @[ifu_bp_ctl.scala 417:77] + wire _T_2568 = btb_rd_addr_f == 8'he4; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_228; // @[lib.scala 358:16] wire [21:0] _T_2852 = _T_2568 ? btb_bank0_rd_data_way0_out_228 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3107 = _T_3106 | _T_2852; // @[Mux.scala 27:72] - wire _T_2570 = btb_rd_addr_f == 8'he5; // @[ifu_bp_ctl.scala 417:77] + wire _T_2570 = btb_rd_addr_f == 8'he5; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_229; // @[lib.scala 358:16] wire [21:0] _T_2853 = _T_2570 ? btb_bank0_rd_data_way0_out_229 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3108 = _T_3107 | _T_2853; // @[Mux.scala 27:72] - wire _T_2572 = btb_rd_addr_f == 8'he6; // @[ifu_bp_ctl.scala 417:77] + wire _T_2572 = btb_rd_addr_f == 8'he6; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_230; // @[lib.scala 358:16] wire [21:0] _T_2854 = _T_2572 ? btb_bank0_rd_data_way0_out_230 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3109 = _T_3108 | _T_2854; // @[Mux.scala 27:72] - wire _T_2574 = btb_rd_addr_f == 8'he7; // @[ifu_bp_ctl.scala 417:77] + wire _T_2574 = btb_rd_addr_f == 8'he7; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_231; // @[lib.scala 358:16] wire [21:0] _T_2855 = _T_2574 ? btb_bank0_rd_data_way0_out_231 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3110 = _T_3109 | _T_2855; // @[Mux.scala 27:72] - wire _T_2576 = btb_rd_addr_f == 8'he8; // @[ifu_bp_ctl.scala 417:77] + wire _T_2576 = btb_rd_addr_f == 8'he8; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_232; // @[lib.scala 358:16] wire [21:0] _T_2856 = _T_2576 ? btb_bank0_rd_data_way0_out_232 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3111 = _T_3110 | _T_2856; // @[Mux.scala 27:72] - wire _T_2578 = btb_rd_addr_f == 8'he9; // @[ifu_bp_ctl.scala 417:77] + wire _T_2578 = btb_rd_addr_f == 8'he9; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_233; // @[lib.scala 358:16] wire [21:0] _T_2857 = _T_2578 ? btb_bank0_rd_data_way0_out_233 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3112 = _T_3111 | _T_2857; // @[Mux.scala 27:72] - wire _T_2580 = btb_rd_addr_f == 8'hea; // @[ifu_bp_ctl.scala 417:77] + wire _T_2580 = btb_rd_addr_f == 8'hea; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_234; // @[lib.scala 358:16] wire [21:0] _T_2858 = _T_2580 ? btb_bank0_rd_data_way0_out_234 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3113 = _T_3112 | _T_2858; // @[Mux.scala 27:72] - wire _T_2582 = btb_rd_addr_f == 8'heb; // @[ifu_bp_ctl.scala 417:77] + wire _T_2582 = btb_rd_addr_f == 8'heb; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_235; // @[lib.scala 358:16] wire [21:0] _T_2859 = _T_2582 ? btb_bank0_rd_data_way0_out_235 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3114 = _T_3113 | _T_2859; // @[Mux.scala 27:72] - wire _T_2584 = btb_rd_addr_f == 8'hec; // @[ifu_bp_ctl.scala 417:77] + wire _T_2584 = btb_rd_addr_f == 8'hec; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_236; // @[lib.scala 358:16] wire [21:0] _T_2860 = _T_2584 ? btb_bank0_rd_data_way0_out_236 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3115 = _T_3114 | _T_2860; // @[Mux.scala 27:72] - wire _T_2586 = btb_rd_addr_f == 8'hed; // @[ifu_bp_ctl.scala 417:77] + wire _T_2586 = btb_rd_addr_f == 8'hed; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_237; // @[lib.scala 358:16] wire [21:0] _T_2861 = _T_2586 ? btb_bank0_rd_data_way0_out_237 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3116 = _T_3115 | _T_2861; // @[Mux.scala 27:72] - wire _T_2588 = btb_rd_addr_f == 8'hee; // @[ifu_bp_ctl.scala 417:77] + wire _T_2588 = btb_rd_addr_f == 8'hee; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_238; // @[lib.scala 358:16] wire [21:0] _T_2862 = _T_2588 ? btb_bank0_rd_data_way0_out_238 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3117 = _T_3116 | _T_2862; // @[Mux.scala 27:72] - wire _T_2590 = btb_rd_addr_f == 8'hef; // @[ifu_bp_ctl.scala 417:77] + wire _T_2590 = btb_rd_addr_f == 8'hef; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_239; // @[lib.scala 358:16] wire [21:0] _T_2863 = _T_2590 ? btb_bank0_rd_data_way0_out_239 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3118 = _T_3117 | _T_2863; // @[Mux.scala 27:72] - wire _T_2592 = btb_rd_addr_f == 8'hf0; // @[ifu_bp_ctl.scala 417:77] + wire _T_2592 = btb_rd_addr_f == 8'hf0; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_240; // @[lib.scala 358:16] wire [21:0] _T_2864 = _T_2592 ? btb_bank0_rd_data_way0_out_240 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3119 = _T_3118 | _T_2864; // @[Mux.scala 27:72] - wire _T_2594 = btb_rd_addr_f == 8'hf1; // @[ifu_bp_ctl.scala 417:77] + wire _T_2594 = btb_rd_addr_f == 8'hf1; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_241; // @[lib.scala 358:16] wire [21:0] _T_2865 = _T_2594 ? btb_bank0_rd_data_way0_out_241 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3120 = _T_3119 | _T_2865; // @[Mux.scala 27:72] - wire _T_2596 = btb_rd_addr_f == 8'hf2; // @[ifu_bp_ctl.scala 417:77] + wire _T_2596 = btb_rd_addr_f == 8'hf2; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_242; // @[lib.scala 358:16] wire [21:0] _T_2866 = _T_2596 ? btb_bank0_rd_data_way0_out_242 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3121 = _T_3120 | _T_2866; // @[Mux.scala 27:72] - wire _T_2598 = btb_rd_addr_f == 8'hf3; // @[ifu_bp_ctl.scala 417:77] + wire _T_2598 = btb_rd_addr_f == 8'hf3; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_243; // @[lib.scala 358:16] wire [21:0] _T_2867 = _T_2598 ? btb_bank0_rd_data_way0_out_243 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3122 = _T_3121 | _T_2867; // @[Mux.scala 27:72] - wire _T_2600 = btb_rd_addr_f == 8'hf4; // @[ifu_bp_ctl.scala 417:77] + wire _T_2600 = btb_rd_addr_f == 8'hf4; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_244; // @[lib.scala 358:16] wire [21:0] _T_2868 = _T_2600 ? btb_bank0_rd_data_way0_out_244 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3123 = _T_3122 | _T_2868; // @[Mux.scala 27:72] - wire _T_2602 = btb_rd_addr_f == 8'hf5; // @[ifu_bp_ctl.scala 417:77] + wire _T_2602 = btb_rd_addr_f == 8'hf5; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_245; // @[lib.scala 358:16] wire [21:0] _T_2869 = _T_2602 ? btb_bank0_rd_data_way0_out_245 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3124 = _T_3123 | _T_2869; // @[Mux.scala 27:72] - wire _T_2604 = btb_rd_addr_f == 8'hf6; // @[ifu_bp_ctl.scala 417:77] + wire _T_2604 = btb_rd_addr_f == 8'hf6; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_246; // @[lib.scala 358:16] wire [21:0] _T_2870 = _T_2604 ? btb_bank0_rd_data_way0_out_246 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3125 = _T_3124 | _T_2870; // @[Mux.scala 27:72] - wire _T_2606 = btb_rd_addr_f == 8'hf7; // @[ifu_bp_ctl.scala 417:77] + wire _T_2606 = btb_rd_addr_f == 8'hf7; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_247; // @[lib.scala 358:16] wire [21:0] _T_2871 = _T_2606 ? btb_bank0_rd_data_way0_out_247 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3126 = _T_3125 | _T_2871; // @[Mux.scala 27:72] - wire _T_2608 = btb_rd_addr_f == 8'hf8; // @[ifu_bp_ctl.scala 417:77] + wire _T_2608 = btb_rd_addr_f == 8'hf8; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_248; // @[lib.scala 358:16] wire [21:0] _T_2872 = _T_2608 ? btb_bank0_rd_data_way0_out_248 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3127 = _T_3126 | _T_2872; // @[Mux.scala 27:72] - wire _T_2610 = btb_rd_addr_f == 8'hf9; // @[ifu_bp_ctl.scala 417:77] + wire _T_2610 = btb_rd_addr_f == 8'hf9; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_249; // @[lib.scala 358:16] wire [21:0] _T_2873 = _T_2610 ? btb_bank0_rd_data_way0_out_249 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3128 = _T_3127 | _T_2873; // @[Mux.scala 27:72] - wire _T_2612 = btb_rd_addr_f == 8'hfa; // @[ifu_bp_ctl.scala 417:77] + wire _T_2612 = btb_rd_addr_f == 8'hfa; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_250; // @[lib.scala 358:16] wire [21:0] _T_2874 = _T_2612 ? btb_bank0_rd_data_way0_out_250 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3129 = _T_3128 | _T_2874; // @[Mux.scala 27:72] - wire _T_2614 = btb_rd_addr_f == 8'hfb; // @[ifu_bp_ctl.scala 417:77] + wire _T_2614 = btb_rd_addr_f == 8'hfb; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_251; // @[lib.scala 358:16] wire [21:0] _T_2875 = _T_2614 ? btb_bank0_rd_data_way0_out_251 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3130 = _T_3129 | _T_2875; // @[Mux.scala 27:72] - wire _T_2616 = btb_rd_addr_f == 8'hfc; // @[ifu_bp_ctl.scala 417:77] + wire _T_2616 = btb_rd_addr_f == 8'hfc; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_252; // @[lib.scala 358:16] wire [21:0] _T_2876 = _T_2616 ? btb_bank0_rd_data_way0_out_252 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3131 = _T_3130 | _T_2876; // @[Mux.scala 27:72] - wire _T_2618 = btb_rd_addr_f == 8'hfd; // @[ifu_bp_ctl.scala 417:77] + wire _T_2618 = btb_rd_addr_f == 8'hfd; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_253; // @[lib.scala 358:16] wire [21:0] _T_2877 = _T_2618 ? btb_bank0_rd_data_way0_out_253 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3132 = _T_3131 | _T_2877; // @[Mux.scala 27:72] - wire _T_2620 = btb_rd_addr_f == 8'hfe; // @[ifu_bp_ctl.scala 417:77] + wire _T_2620 = btb_rd_addr_f == 8'hfe; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_254; // @[lib.scala 358:16] wire [21:0] _T_2878 = _T_2620 ? btb_bank0_rd_data_way0_out_254 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_3133 = _T_3132 | _T_2878; // @[Mux.scala 27:72] - wire _T_2622 = btb_rd_addr_f == 8'hff; // @[ifu_bp_ctl.scala 417:77] + wire _T_2622 = btb_rd_addr_f == 8'hff; // @[ifu_bp_ctl.scala 418:77] reg [21:0] btb_bank0_rd_data_way0_out_255; // @[lib.scala 358:16] wire [21:0] _T_2879 = _T_2622 ? btb_bank0_rd_data_way0_out_255 : 22'h0; // @[Mux.scala 27:72] wire [21:0] btb_bank0_rd_data_way0_f = _T_3133 | _T_2879; // @[Mux.scala 27:72] wire [4:0] _T_25 = io_ifc_fetch_addr_f[13:9] ^ io_ifc_fetch_addr_f[18:14]; // @[lib.scala 26:111] wire [4:0] fetch_rd_tag_f = _T_25 ^ io_ifc_fetch_addr_f[23:19]; // @[lib.scala 26:111] - wire _T_46 = btb_bank0_rd_data_way0_f[21:17] == fetch_rd_tag_f; // @[ifu_bp_ctl.scala 126:97] - wire _T_47 = btb_bank0_rd_data_way0_f[0] & _T_46; // @[ifu_bp_ctl.scala 126:55] - reg dec_tlu_way_wb_f; // @[ifu_bp_ctl.scala 117:59] - wire _T_19 = io_exu_bp_exu_i0_br_index_r == btb_rd_addr_f; // @[ifu_bp_ctl.scala 101:72] - wire branch_error_collision_f = dec_tlu_error_wb & _T_19; // @[ifu_bp_ctl.scala 101:51] - wire branch_error_bank_conflict_f = branch_error_collision_f & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 105:63] - wire _T_48 = dec_tlu_way_wb_f & branch_error_bank_conflict_f; // @[ifu_bp_ctl.scala 127:44] - wire _T_49 = ~_T_48; // @[ifu_bp_ctl.scala 127:25] - wire _T_50 = _T_47 & _T_49; // @[ifu_bp_ctl.scala 126:117] - wire _T_51 = _T_50 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 127:76] - wire tag_match_way0_f = _T_51 & _T; // @[ifu_bp_ctl.scala 127:97] - wire _T_82 = btb_bank0_rd_data_way0_f[3] ^ btb_bank0_rd_data_way0_f[4]; // @[ifu_bp_ctl.scala 141:91] - wire _T_83 = tag_match_way0_f & _T_82; // @[ifu_bp_ctl.scala 141:56] - wire _T_87 = ~_T_82; // @[ifu_bp_ctl.scala 142:58] - wire _T_88 = tag_match_way0_f & _T_87; // @[ifu_bp_ctl.scala 142:56] + wire _T_46 = btb_bank0_rd_data_way0_f[21:17] == fetch_rd_tag_f; // @[ifu_bp_ctl.scala 127:97] + wire _T_47 = btb_bank0_rd_data_way0_f[0] & _T_46; // @[ifu_bp_ctl.scala 127:55] + reg dec_tlu_way_wb_f; // @[ifu_bp_ctl.scala 118:59] + wire _T_19 = io_exu_bp_exu_i0_br_index_r == btb_rd_addr_f; // @[ifu_bp_ctl.scala 102:72] + wire branch_error_collision_f = dec_tlu_error_wb & _T_19; // @[ifu_bp_ctl.scala 102:51] + wire branch_error_bank_conflict_f = branch_error_collision_f & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 106:63] + wire _T_48 = dec_tlu_way_wb_f & branch_error_bank_conflict_f; // @[ifu_bp_ctl.scala 128:44] + wire _T_49 = ~_T_48; // @[ifu_bp_ctl.scala 128:25] + wire _T_50 = _T_47 & _T_49; // @[ifu_bp_ctl.scala 127:117] + wire _T_51 = _T_50 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 128:76] + wire tag_match_way0_f = _T_51 & _T; // @[ifu_bp_ctl.scala 128:97] + wire _T_82 = btb_bank0_rd_data_way0_f[3] ^ btb_bank0_rd_data_way0_f[4]; // @[ifu_bp_ctl.scala 142:91] + wire _T_83 = tag_match_way0_f & _T_82; // @[ifu_bp_ctl.scala 142:56] + wire _T_87 = ~_T_82; // @[ifu_bp_ctl.scala 143:58] + wire _T_88 = tag_match_way0_f & _T_87; // @[ifu_bp_ctl.scala 143:56] wire [1:0] tag_match_way0_expanded_f = {_T_83,_T_88}; // @[Cat.scala 29:58] wire [21:0] _T_127 = tag_match_way0_expanded_f[1] ? btb_bank0_rd_data_way0_f : 22'h0; // @[Mux.scala 27:72] reg [21:0] btb_bank0_rd_data_way1_out_0; // @[lib.scala 358:16] @@ -16991,802 +16991,802 @@ module ifu_bp_ctl( reg [21:0] btb_bank0_rd_data_way1_out_255; // @[lib.scala 358:16] wire [21:0] _T_3903 = _T_2622 ? btb_bank0_rd_data_way1_out_255 : 22'h0; // @[Mux.scala 27:72] wire [21:0] btb_bank0_rd_data_way1_f = _T_4157 | _T_3903; // @[Mux.scala 27:72] - wire _T_55 = btb_bank0_rd_data_way1_f[21:17] == fetch_rd_tag_f; // @[ifu_bp_ctl.scala 130:97] - wire _T_56 = btb_bank0_rd_data_way1_f[0] & _T_55; // @[ifu_bp_ctl.scala 130:55] - wire _T_59 = _T_56 & _T_49; // @[ifu_bp_ctl.scala 130:117] - wire _T_60 = _T_59 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 131:76] - wire tag_match_way1_f = _T_60 & _T; // @[ifu_bp_ctl.scala 131:97] - wire _T_91 = btb_bank0_rd_data_way1_f[3] ^ btb_bank0_rd_data_way1_f[4]; // @[ifu_bp_ctl.scala 144:91] - wire _T_92 = tag_match_way1_f & _T_91; // @[ifu_bp_ctl.scala 144:56] - wire _T_96 = ~_T_91; // @[ifu_bp_ctl.scala 145:58] - wire _T_97 = tag_match_way1_f & _T_96; // @[ifu_bp_ctl.scala 145:56] + wire _T_55 = btb_bank0_rd_data_way1_f[21:17] == fetch_rd_tag_f; // @[ifu_bp_ctl.scala 131:97] + wire _T_56 = btb_bank0_rd_data_way1_f[0] & _T_55; // @[ifu_bp_ctl.scala 131:55] + wire _T_59 = _T_56 & _T_49; // @[ifu_bp_ctl.scala 131:117] + wire _T_60 = _T_59 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 132:76] + wire tag_match_way1_f = _T_60 & _T; // @[ifu_bp_ctl.scala 132:97] + wire _T_91 = btb_bank0_rd_data_way1_f[3] ^ btb_bank0_rd_data_way1_f[4]; // @[ifu_bp_ctl.scala 145:91] + wire _T_92 = tag_match_way1_f & _T_91; // @[ifu_bp_ctl.scala 145:56] + wire _T_96 = ~_T_91; // @[ifu_bp_ctl.scala 146:58] + wire _T_97 = tag_match_way1_f & _T_96; // @[ifu_bp_ctl.scala 146:56] wire [1:0] tag_match_way1_expanded_f = {_T_92,_T_97}; // @[Cat.scala 29:58] wire [21:0] _T_128 = tag_match_way1_expanded_f[1] ? btb_bank0_rd_data_way1_f : 22'h0; // @[Mux.scala 27:72] wire [21:0] btb_bank0o_rd_data_f = _T_127 | _T_128; // @[Mux.scala 27:72] wire [21:0] _T_146 = _T_144 ? btb_bank0o_rd_data_f : 22'h0; // @[Mux.scala 27:72] - wire _T_4160 = btb_rd_addr_p1_f == 8'h0; // @[ifu_bp_ctl.scala 421:83] + wire _T_4160 = btb_rd_addr_p1_f == 8'h0; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4672 = _T_4160 ? btb_bank0_rd_data_way0_out_0 : 22'h0; // @[Mux.scala 27:72] - wire _T_4162 = btb_rd_addr_p1_f == 8'h1; // @[ifu_bp_ctl.scala 421:83] + wire _T_4162 = btb_rd_addr_p1_f == 8'h1; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4673 = _T_4162 ? btb_bank0_rd_data_way0_out_1 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4928 = _T_4672 | _T_4673; // @[Mux.scala 27:72] - wire _T_4164 = btb_rd_addr_p1_f == 8'h2; // @[ifu_bp_ctl.scala 421:83] + wire _T_4164 = btb_rd_addr_p1_f == 8'h2; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4674 = _T_4164 ? btb_bank0_rd_data_way0_out_2 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4929 = _T_4928 | _T_4674; // @[Mux.scala 27:72] - wire _T_4166 = btb_rd_addr_p1_f == 8'h3; // @[ifu_bp_ctl.scala 421:83] + wire _T_4166 = btb_rd_addr_p1_f == 8'h3; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4675 = _T_4166 ? btb_bank0_rd_data_way0_out_3 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4930 = _T_4929 | _T_4675; // @[Mux.scala 27:72] - wire _T_4168 = btb_rd_addr_p1_f == 8'h4; // @[ifu_bp_ctl.scala 421:83] + wire _T_4168 = btb_rd_addr_p1_f == 8'h4; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4676 = _T_4168 ? btb_bank0_rd_data_way0_out_4 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4931 = _T_4930 | _T_4676; // @[Mux.scala 27:72] - wire _T_4170 = btb_rd_addr_p1_f == 8'h5; // @[ifu_bp_ctl.scala 421:83] + wire _T_4170 = btb_rd_addr_p1_f == 8'h5; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4677 = _T_4170 ? btb_bank0_rd_data_way0_out_5 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4932 = _T_4931 | _T_4677; // @[Mux.scala 27:72] - wire _T_4172 = btb_rd_addr_p1_f == 8'h6; // @[ifu_bp_ctl.scala 421:83] + wire _T_4172 = btb_rd_addr_p1_f == 8'h6; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4678 = _T_4172 ? btb_bank0_rd_data_way0_out_6 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4933 = _T_4932 | _T_4678; // @[Mux.scala 27:72] - wire _T_4174 = btb_rd_addr_p1_f == 8'h7; // @[ifu_bp_ctl.scala 421:83] + wire _T_4174 = btb_rd_addr_p1_f == 8'h7; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4679 = _T_4174 ? btb_bank0_rd_data_way0_out_7 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4934 = _T_4933 | _T_4679; // @[Mux.scala 27:72] - wire _T_4176 = btb_rd_addr_p1_f == 8'h8; // @[ifu_bp_ctl.scala 421:83] + wire _T_4176 = btb_rd_addr_p1_f == 8'h8; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4680 = _T_4176 ? btb_bank0_rd_data_way0_out_8 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4935 = _T_4934 | _T_4680; // @[Mux.scala 27:72] - wire _T_4178 = btb_rd_addr_p1_f == 8'h9; // @[ifu_bp_ctl.scala 421:83] + wire _T_4178 = btb_rd_addr_p1_f == 8'h9; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4681 = _T_4178 ? btb_bank0_rd_data_way0_out_9 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4936 = _T_4935 | _T_4681; // @[Mux.scala 27:72] - wire _T_4180 = btb_rd_addr_p1_f == 8'ha; // @[ifu_bp_ctl.scala 421:83] + wire _T_4180 = btb_rd_addr_p1_f == 8'ha; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4682 = _T_4180 ? btb_bank0_rd_data_way0_out_10 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4937 = _T_4936 | _T_4682; // @[Mux.scala 27:72] - wire _T_4182 = btb_rd_addr_p1_f == 8'hb; // @[ifu_bp_ctl.scala 421:83] + wire _T_4182 = btb_rd_addr_p1_f == 8'hb; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4683 = _T_4182 ? btb_bank0_rd_data_way0_out_11 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4938 = _T_4937 | _T_4683; // @[Mux.scala 27:72] - wire _T_4184 = btb_rd_addr_p1_f == 8'hc; // @[ifu_bp_ctl.scala 421:83] + wire _T_4184 = btb_rd_addr_p1_f == 8'hc; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4684 = _T_4184 ? btb_bank0_rd_data_way0_out_12 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4939 = _T_4938 | _T_4684; // @[Mux.scala 27:72] - wire _T_4186 = btb_rd_addr_p1_f == 8'hd; // @[ifu_bp_ctl.scala 421:83] + wire _T_4186 = btb_rd_addr_p1_f == 8'hd; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4685 = _T_4186 ? btb_bank0_rd_data_way0_out_13 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4940 = _T_4939 | _T_4685; // @[Mux.scala 27:72] - wire _T_4188 = btb_rd_addr_p1_f == 8'he; // @[ifu_bp_ctl.scala 421:83] + wire _T_4188 = btb_rd_addr_p1_f == 8'he; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4686 = _T_4188 ? btb_bank0_rd_data_way0_out_14 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4941 = _T_4940 | _T_4686; // @[Mux.scala 27:72] - wire _T_4190 = btb_rd_addr_p1_f == 8'hf; // @[ifu_bp_ctl.scala 421:83] + wire _T_4190 = btb_rd_addr_p1_f == 8'hf; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4687 = _T_4190 ? btb_bank0_rd_data_way0_out_15 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4942 = _T_4941 | _T_4687; // @[Mux.scala 27:72] - wire _T_4192 = btb_rd_addr_p1_f == 8'h10; // @[ifu_bp_ctl.scala 421:83] + wire _T_4192 = btb_rd_addr_p1_f == 8'h10; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4688 = _T_4192 ? btb_bank0_rd_data_way0_out_16 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4943 = _T_4942 | _T_4688; // @[Mux.scala 27:72] - wire _T_4194 = btb_rd_addr_p1_f == 8'h11; // @[ifu_bp_ctl.scala 421:83] + wire _T_4194 = btb_rd_addr_p1_f == 8'h11; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4689 = _T_4194 ? btb_bank0_rd_data_way0_out_17 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4944 = _T_4943 | _T_4689; // @[Mux.scala 27:72] - wire _T_4196 = btb_rd_addr_p1_f == 8'h12; // @[ifu_bp_ctl.scala 421:83] + wire _T_4196 = btb_rd_addr_p1_f == 8'h12; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4690 = _T_4196 ? btb_bank0_rd_data_way0_out_18 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4945 = _T_4944 | _T_4690; // @[Mux.scala 27:72] - wire _T_4198 = btb_rd_addr_p1_f == 8'h13; // @[ifu_bp_ctl.scala 421:83] + wire _T_4198 = btb_rd_addr_p1_f == 8'h13; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4691 = _T_4198 ? btb_bank0_rd_data_way0_out_19 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4946 = _T_4945 | _T_4691; // @[Mux.scala 27:72] - wire _T_4200 = btb_rd_addr_p1_f == 8'h14; // @[ifu_bp_ctl.scala 421:83] + wire _T_4200 = btb_rd_addr_p1_f == 8'h14; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4692 = _T_4200 ? btb_bank0_rd_data_way0_out_20 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4947 = _T_4946 | _T_4692; // @[Mux.scala 27:72] - wire _T_4202 = btb_rd_addr_p1_f == 8'h15; // @[ifu_bp_ctl.scala 421:83] + wire _T_4202 = btb_rd_addr_p1_f == 8'h15; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4693 = _T_4202 ? btb_bank0_rd_data_way0_out_21 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4948 = _T_4947 | _T_4693; // @[Mux.scala 27:72] - wire _T_4204 = btb_rd_addr_p1_f == 8'h16; // @[ifu_bp_ctl.scala 421:83] + wire _T_4204 = btb_rd_addr_p1_f == 8'h16; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4694 = _T_4204 ? btb_bank0_rd_data_way0_out_22 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4949 = _T_4948 | _T_4694; // @[Mux.scala 27:72] - wire _T_4206 = btb_rd_addr_p1_f == 8'h17; // @[ifu_bp_ctl.scala 421:83] + wire _T_4206 = btb_rd_addr_p1_f == 8'h17; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4695 = _T_4206 ? btb_bank0_rd_data_way0_out_23 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4950 = _T_4949 | _T_4695; // @[Mux.scala 27:72] - wire _T_4208 = btb_rd_addr_p1_f == 8'h18; // @[ifu_bp_ctl.scala 421:83] + wire _T_4208 = btb_rd_addr_p1_f == 8'h18; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4696 = _T_4208 ? btb_bank0_rd_data_way0_out_24 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4951 = _T_4950 | _T_4696; // @[Mux.scala 27:72] - wire _T_4210 = btb_rd_addr_p1_f == 8'h19; // @[ifu_bp_ctl.scala 421:83] + wire _T_4210 = btb_rd_addr_p1_f == 8'h19; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4697 = _T_4210 ? btb_bank0_rd_data_way0_out_25 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4952 = _T_4951 | _T_4697; // @[Mux.scala 27:72] - wire _T_4212 = btb_rd_addr_p1_f == 8'h1a; // @[ifu_bp_ctl.scala 421:83] + wire _T_4212 = btb_rd_addr_p1_f == 8'h1a; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4698 = _T_4212 ? btb_bank0_rd_data_way0_out_26 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4953 = _T_4952 | _T_4698; // @[Mux.scala 27:72] - wire _T_4214 = btb_rd_addr_p1_f == 8'h1b; // @[ifu_bp_ctl.scala 421:83] + wire _T_4214 = btb_rd_addr_p1_f == 8'h1b; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4699 = _T_4214 ? btb_bank0_rd_data_way0_out_27 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4954 = _T_4953 | _T_4699; // @[Mux.scala 27:72] - wire _T_4216 = btb_rd_addr_p1_f == 8'h1c; // @[ifu_bp_ctl.scala 421:83] + wire _T_4216 = btb_rd_addr_p1_f == 8'h1c; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4700 = _T_4216 ? btb_bank0_rd_data_way0_out_28 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4955 = _T_4954 | _T_4700; // @[Mux.scala 27:72] - wire _T_4218 = btb_rd_addr_p1_f == 8'h1d; // @[ifu_bp_ctl.scala 421:83] + wire _T_4218 = btb_rd_addr_p1_f == 8'h1d; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4701 = _T_4218 ? btb_bank0_rd_data_way0_out_29 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4956 = _T_4955 | _T_4701; // @[Mux.scala 27:72] - wire _T_4220 = btb_rd_addr_p1_f == 8'h1e; // @[ifu_bp_ctl.scala 421:83] + wire _T_4220 = btb_rd_addr_p1_f == 8'h1e; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4702 = _T_4220 ? btb_bank0_rd_data_way0_out_30 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4957 = _T_4956 | _T_4702; // @[Mux.scala 27:72] - wire _T_4222 = btb_rd_addr_p1_f == 8'h1f; // @[ifu_bp_ctl.scala 421:83] + wire _T_4222 = btb_rd_addr_p1_f == 8'h1f; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4703 = _T_4222 ? btb_bank0_rd_data_way0_out_31 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4958 = _T_4957 | _T_4703; // @[Mux.scala 27:72] - wire _T_4224 = btb_rd_addr_p1_f == 8'h20; // @[ifu_bp_ctl.scala 421:83] + wire _T_4224 = btb_rd_addr_p1_f == 8'h20; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4704 = _T_4224 ? btb_bank0_rd_data_way0_out_32 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4959 = _T_4958 | _T_4704; // @[Mux.scala 27:72] - wire _T_4226 = btb_rd_addr_p1_f == 8'h21; // @[ifu_bp_ctl.scala 421:83] + wire _T_4226 = btb_rd_addr_p1_f == 8'h21; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4705 = _T_4226 ? btb_bank0_rd_data_way0_out_33 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4960 = _T_4959 | _T_4705; // @[Mux.scala 27:72] - wire _T_4228 = btb_rd_addr_p1_f == 8'h22; // @[ifu_bp_ctl.scala 421:83] + wire _T_4228 = btb_rd_addr_p1_f == 8'h22; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4706 = _T_4228 ? btb_bank0_rd_data_way0_out_34 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4961 = _T_4960 | _T_4706; // @[Mux.scala 27:72] - wire _T_4230 = btb_rd_addr_p1_f == 8'h23; // @[ifu_bp_ctl.scala 421:83] + wire _T_4230 = btb_rd_addr_p1_f == 8'h23; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4707 = _T_4230 ? btb_bank0_rd_data_way0_out_35 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4962 = _T_4961 | _T_4707; // @[Mux.scala 27:72] - wire _T_4232 = btb_rd_addr_p1_f == 8'h24; // @[ifu_bp_ctl.scala 421:83] + wire _T_4232 = btb_rd_addr_p1_f == 8'h24; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4708 = _T_4232 ? btb_bank0_rd_data_way0_out_36 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4963 = _T_4962 | _T_4708; // @[Mux.scala 27:72] - wire _T_4234 = btb_rd_addr_p1_f == 8'h25; // @[ifu_bp_ctl.scala 421:83] + wire _T_4234 = btb_rd_addr_p1_f == 8'h25; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4709 = _T_4234 ? btb_bank0_rd_data_way0_out_37 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4964 = _T_4963 | _T_4709; // @[Mux.scala 27:72] - wire _T_4236 = btb_rd_addr_p1_f == 8'h26; // @[ifu_bp_ctl.scala 421:83] + wire _T_4236 = btb_rd_addr_p1_f == 8'h26; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4710 = _T_4236 ? btb_bank0_rd_data_way0_out_38 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4965 = _T_4964 | _T_4710; // @[Mux.scala 27:72] - wire _T_4238 = btb_rd_addr_p1_f == 8'h27; // @[ifu_bp_ctl.scala 421:83] + wire _T_4238 = btb_rd_addr_p1_f == 8'h27; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4711 = _T_4238 ? btb_bank0_rd_data_way0_out_39 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4966 = _T_4965 | _T_4711; // @[Mux.scala 27:72] - wire _T_4240 = btb_rd_addr_p1_f == 8'h28; // @[ifu_bp_ctl.scala 421:83] + wire _T_4240 = btb_rd_addr_p1_f == 8'h28; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4712 = _T_4240 ? btb_bank0_rd_data_way0_out_40 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4967 = _T_4966 | _T_4712; // @[Mux.scala 27:72] - wire _T_4242 = btb_rd_addr_p1_f == 8'h29; // @[ifu_bp_ctl.scala 421:83] + wire _T_4242 = btb_rd_addr_p1_f == 8'h29; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4713 = _T_4242 ? btb_bank0_rd_data_way0_out_41 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4968 = _T_4967 | _T_4713; // @[Mux.scala 27:72] - wire _T_4244 = btb_rd_addr_p1_f == 8'h2a; // @[ifu_bp_ctl.scala 421:83] + wire _T_4244 = btb_rd_addr_p1_f == 8'h2a; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4714 = _T_4244 ? btb_bank0_rd_data_way0_out_42 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4969 = _T_4968 | _T_4714; // @[Mux.scala 27:72] - wire _T_4246 = btb_rd_addr_p1_f == 8'h2b; // @[ifu_bp_ctl.scala 421:83] + wire _T_4246 = btb_rd_addr_p1_f == 8'h2b; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4715 = _T_4246 ? btb_bank0_rd_data_way0_out_43 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4970 = _T_4969 | _T_4715; // @[Mux.scala 27:72] - wire _T_4248 = btb_rd_addr_p1_f == 8'h2c; // @[ifu_bp_ctl.scala 421:83] + wire _T_4248 = btb_rd_addr_p1_f == 8'h2c; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4716 = _T_4248 ? btb_bank0_rd_data_way0_out_44 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4971 = _T_4970 | _T_4716; // @[Mux.scala 27:72] - wire _T_4250 = btb_rd_addr_p1_f == 8'h2d; // @[ifu_bp_ctl.scala 421:83] + wire _T_4250 = btb_rd_addr_p1_f == 8'h2d; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4717 = _T_4250 ? btb_bank0_rd_data_way0_out_45 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4972 = _T_4971 | _T_4717; // @[Mux.scala 27:72] - wire _T_4252 = btb_rd_addr_p1_f == 8'h2e; // @[ifu_bp_ctl.scala 421:83] + wire _T_4252 = btb_rd_addr_p1_f == 8'h2e; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4718 = _T_4252 ? btb_bank0_rd_data_way0_out_46 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4973 = _T_4972 | _T_4718; // @[Mux.scala 27:72] - wire _T_4254 = btb_rd_addr_p1_f == 8'h2f; // @[ifu_bp_ctl.scala 421:83] + wire _T_4254 = btb_rd_addr_p1_f == 8'h2f; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4719 = _T_4254 ? btb_bank0_rd_data_way0_out_47 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4974 = _T_4973 | _T_4719; // @[Mux.scala 27:72] - wire _T_4256 = btb_rd_addr_p1_f == 8'h30; // @[ifu_bp_ctl.scala 421:83] + wire _T_4256 = btb_rd_addr_p1_f == 8'h30; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4720 = _T_4256 ? btb_bank0_rd_data_way0_out_48 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4975 = _T_4974 | _T_4720; // @[Mux.scala 27:72] - wire _T_4258 = btb_rd_addr_p1_f == 8'h31; // @[ifu_bp_ctl.scala 421:83] + wire _T_4258 = btb_rd_addr_p1_f == 8'h31; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4721 = _T_4258 ? btb_bank0_rd_data_way0_out_49 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4976 = _T_4975 | _T_4721; // @[Mux.scala 27:72] - wire _T_4260 = btb_rd_addr_p1_f == 8'h32; // @[ifu_bp_ctl.scala 421:83] + wire _T_4260 = btb_rd_addr_p1_f == 8'h32; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4722 = _T_4260 ? btb_bank0_rd_data_way0_out_50 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4977 = _T_4976 | _T_4722; // @[Mux.scala 27:72] - wire _T_4262 = btb_rd_addr_p1_f == 8'h33; // @[ifu_bp_ctl.scala 421:83] + wire _T_4262 = btb_rd_addr_p1_f == 8'h33; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4723 = _T_4262 ? btb_bank0_rd_data_way0_out_51 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4978 = _T_4977 | _T_4723; // @[Mux.scala 27:72] - wire _T_4264 = btb_rd_addr_p1_f == 8'h34; // @[ifu_bp_ctl.scala 421:83] + wire _T_4264 = btb_rd_addr_p1_f == 8'h34; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4724 = _T_4264 ? btb_bank0_rd_data_way0_out_52 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4979 = _T_4978 | _T_4724; // @[Mux.scala 27:72] - wire _T_4266 = btb_rd_addr_p1_f == 8'h35; // @[ifu_bp_ctl.scala 421:83] + wire _T_4266 = btb_rd_addr_p1_f == 8'h35; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4725 = _T_4266 ? btb_bank0_rd_data_way0_out_53 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4980 = _T_4979 | _T_4725; // @[Mux.scala 27:72] - wire _T_4268 = btb_rd_addr_p1_f == 8'h36; // @[ifu_bp_ctl.scala 421:83] + wire _T_4268 = btb_rd_addr_p1_f == 8'h36; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4726 = _T_4268 ? btb_bank0_rd_data_way0_out_54 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4981 = _T_4980 | _T_4726; // @[Mux.scala 27:72] - wire _T_4270 = btb_rd_addr_p1_f == 8'h37; // @[ifu_bp_ctl.scala 421:83] + wire _T_4270 = btb_rd_addr_p1_f == 8'h37; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4727 = _T_4270 ? btb_bank0_rd_data_way0_out_55 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4982 = _T_4981 | _T_4727; // @[Mux.scala 27:72] - wire _T_4272 = btb_rd_addr_p1_f == 8'h38; // @[ifu_bp_ctl.scala 421:83] + wire _T_4272 = btb_rd_addr_p1_f == 8'h38; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4728 = _T_4272 ? btb_bank0_rd_data_way0_out_56 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4983 = _T_4982 | _T_4728; // @[Mux.scala 27:72] - wire _T_4274 = btb_rd_addr_p1_f == 8'h39; // @[ifu_bp_ctl.scala 421:83] + wire _T_4274 = btb_rd_addr_p1_f == 8'h39; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4729 = _T_4274 ? btb_bank0_rd_data_way0_out_57 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4984 = _T_4983 | _T_4729; // @[Mux.scala 27:72] - wire _T_4276 = btb_rd_addr_p1_f == 8'h3a; // @[ifu_bp_ctl.scala 421:83] + wire _T_4276 = btb_rd_addr_p1_f == 8'h3a; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4730 = _T_4276 ? btb_bank0_rd_data_way0_out_58 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4985 = _T_4984 | _T_4730; // @[Mux.scala 27:72] - wire _T_4278 = btb_rd_addr_p1_f == 8'h3b; // @[ifu_bp_ctl.scala 421:83] + wire _T_4278 = btb_rd_addr_p1_f == 8'h3b; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4731 = _T_4278 ? btb_bank0_rd_data_way0_out_59 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4986 = _T_4985 | _T_4731; // @[Mux.scala 27:72] - wire _T_4280 = btb_rd_addr_p1_f == 8'h3c; // @[ifu_bp_ctl.scala 421:83] + wire _T_4280 = btb_rd_addr_p1_f == 8'h3c; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4732 = _T_4280 ? btb_bank0_rd_data_way0_out_60 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4987 = _T_4986 | _T_4732; // @[Mux.scala 27:72] - wire _T_4282 = btb_rd_addr_p1_f == 8'h3d; // @[ifu_bp_ctl.scala 421:83] + wire _T_4282 = btb_rd_addr_p1_f == 8'h3d; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4733 = _T_4282 ? btb_bank0_rd_data_way0_out_61 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4988 = _T_4987 | _T_4733; // @[Mux.scala 27:72] - wire _T_4284 = btb_rd_addr_p1_f == 8'h3e; // @[ifu_bp_ctl.scala 421:83] + wire _T_4284 = btb_rd_addr_p1_f == 8'h3e; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4734 = _T_4284 ? btb_bank0_rd_data_way0_out_62 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4989 = _T_4988 | _T_4734; // @[Mux.scala 27:72] - wire _T_4286 = btb_rd_addr_p1_f == 8'h3f; // @[ifu_bp_ctl.scala 421:83] + wire _T_4286 = btb_rd_addr_p1_f == 8'h3f; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4735 = _T_4286 ? btb_bank0_rd_data_way0_out_63 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4990 = _T_4989 | _T_4735; // @[Mux.scala 27:72] - wire _T_4288 = btb_rd_addr_p1_f == 8'h40; // @[ifu_bp_ctl.scala 421:83] + wire _T_4288 = btb_rd_addr_p1_f == 8'h40; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4736 = _T_4288 ? btb_bank0_rd_data_way0_out_64 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4991 = _T_4990 | _T_4736; // @[Mux.scala 27:72] - wire _T_4290 = btb_rd_addr_p1_f == 8'h41; // @[ifu_bp_ctl.scala 421:83] + wire _T_4290 = btb_rd_addr_p1_f == 8'h41; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4737 = _T_4290 ? btb_bank0_rd_data_way0_out_65 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4992 = _T_4991 | _T_4737; // @[Mux.scala 27:72] - wire _T_4292 = btb_rd_addr_p1_f == 8'h42; // @[ifu_bp_ctl.scala 421:83] + wire _T_4292 = btb_rd_addr_p1_f == 8'h42; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4738 = _T_4292 ? btb_bank0_rd_data_way0_out_66 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4993 = _T_4992 | _T_4738; // @[Mux.scala 27:72] - wire _T_4294 = btb_rd_addr_p1_f == 8'h43; // @[ifu_bp_ctl.scala 421:83] + wire _T_4294 = btb_rd_addr_p1_f == 8'h43; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4739 = _T_4294 ? btb_bank0_rd_data_way0_out_67 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4994 = _T_4993 | _T_4739; // @[Mux.scala 27:72] - wire _T_4296 = btb_rd_addr_p1_f == 8'h44; // @[ifu_bp_ctl.scala 421:83] + wire _T_4296 = btb_rd_addr_p1_f == 8'h44; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4740 = _T_4296 ? btb_bank0_rd_data_way0_out_68 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4995 = _T_4994 | _T_4740; // @[Mux.scala 27:72] - wire _T_4298 = btb_rd_addr_p1_f == 8'h45; // @[ifu_bp_ctl.scala 421:83] + wire _T_4298 = btb_rd_addr_p1_f == 8'h45; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4741 = _T_4298 ? btb_bank0_rd_data_way0_out_69 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4996 = _T_4995 | _T_4741; // @[Mux.scala 27:72] - wire _T_4300 = btb_rd_addr_p1_f == 8'h46; // @[ifu_bp_ctl.scala 421:83] + wire _T_4300 = btb_rd_addr_p1_f == 8'h46; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4742 = _T_4300 ? btb_bank0_rd_data_way0_out_70 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4997 = _T_4996 | _T_4742; // @[Mux.scala 27:72] - wire _T_4302 = btb_rd_addr_p1_f == 8'h47; // @[ifu_bp_ctl.scala 421:83] + wire _T_4302 = btb_rd_addr_p1_f == 8'h47; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4743 = _T_4302 ? btb_bank0_rd_data_way0_out_71 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4998 = _T_4997 | _T_4743; // @[Mux.scala 27:72] - wire _T_4304 = btb_rd_addr_p1_f == 8'h48; // @[ifu_bp_ctl.scala 421:83] + wire _T_4304 = btb_rd_addr_p1_f == 8'h48; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4744 = _T_4304 ? btb_bank0_rd_data_way0_out_72 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_4999 = _T_4998 | _T_4744; // @[Mux.scala 27:72] - wire _T_4306 = btb_rd_addr_p1_f == 8'h49; // @[ifu_bp_ctl.scala 421:83] + wire _T_4306 = btb_rd_addr_p1_f == 8'h49; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4745 = _T_4306 ? btb_bank0_rd_data_way0_out_73 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5000 = _T_4999 | _T_4745; // @[Mux.scala 27:72] - wire _T_4308 = btb_rd_addr_p1_f == 8'h4a; // @[ifu_bp_ctl.scala 421:83] + wire _T_4308 = btb_rd_addr_p1_f == 8'h4a; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4746 = _T_4308 ? btb_bank0_rd_data_way0_out_74 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5001 = _T_5000 | _T_4746; // @[Mux.scala 27:72] - wire _T_4310 = btb_rd_addr_p1_f == 8'h4b; // @[ifu_bp_ctl.scala 421:83] + wire _T_4310 = btb_rd_addr_p1_f == 8'h4b; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4747 = _T_4310 ? btb_bank0_rd_data_way0_out_75 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5002 = _T_5001 | _T_4747; // @[Mux.scala 27:72] - wire _T_4312 = btb_rd_addr_p1_f == 8'h4c; // @[ifu_bp_ctl.scala 421:83] + wire _T_4312 = btb_rd_addr_p1_f == 8'h4c; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4748 = _T_4312 ? btb_bank0_rd_data_way0_out_76 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5003 = _T_5002 | _T_4748; // @[Mux.scala 27:72] - wire _T_4314 = btb_rd_addr_p1_f == 8'h4d; // @[ifu_bp_ctl.scala 421:83] + wire _T_4314 = btb_rd_addr_p1_f == 8'h4d; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4749 = _T_4314 ? btb_bank0_rd_data_way0_out_77 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5004 = _T_5003 | _T_4749; // @[Mux.scala 27:72] - wire _T_4316 = btb_rd_addr_p1_f == 8'h4e; // @[ifu_bp_ctl.scala 421:83] + wire _T_4316 = btb_rd_addr_p1_f == 8'h4e; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4750 = _T_4316 ? btb_bank0_rd_data_way0_out_78 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5005 = _T_5004 | _T_4750; // @[Mux.scala 27:72] - wire _T_4318 = btb_rd_addr_p1_f == 8'h4f; // @[ifu_bp_ctl.scala 421:83] + wire _T_4318 = btb_rd_addr_p1_f == 8'h4f; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4751 = _T_4318 ? btb_bank0_rd_data_way0_out_79 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5006 = _T_5005 | _T_4751; // @[Mux.scala 27:72] - wire _T_4320 = btb_rd_addr_p1_f == 8'h50; // @[ifu_bp_ctl.scala 421:83] + wire _T_4320 = btb_rd_addr_p1_f == 8'h50; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4752 = _T_4320 ? btb_bank0_rd_data_way0_out_80 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5007 = _T_5006 | _T_4752; // @[Mux.scala 27:72] - wire _T_4322 = btb_rd_addr_p1_f == 8'h51; // @[ifu_bp_ctl.scala 421:83] + wire _T_4322 = btb_rd_addr_p1_f == 8'h51; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4753 = _T_4322 ? btb_bank0_rd_data_way0_out_81 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5008 = _T_5007 | _T_4753; // @[Mux.scala 27:72] - wire _T_4324 = btb_rd_addr_p1_f == 8'h52; // @[ifu_bp_ctl.scala 421:83] + wire _T_4324 = btb_rd_addr_p1_f == 8'h52; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4754 = _T_4324 ? btb_bank0_rd_data_way0_out_82 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5009 = _T_5008 | _T_4754; // @[Mux.scala 27:72] - wire _T_4326 = btb_rd_addr_p1_f == 8'h53; // @[ifu_bp_ctl.scala 421:83] + wire _T_4326 = btb_rd_addr_p1_f == 8'h53; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4755 = _T_4326 ? btb_bank0_rd_data_way0_out_83 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5010 = _T_5009 | _T_4755; // @[Mux.scala 27:72] - wire _T_4328 = btb_rd_addr_p1_f == 8'h54; // @[ifu_bp_ctl.scala 421:83] + wire _T_4328 = btb_rd_addr_p1_f == 8'h54; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4756 = _T_4328 ? btb_bank0_rd_data_way0_out_84 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5011 = _T_5010 | _T_4756; // @[Mux.scala 27:72] - wire _T_4330 = btb_rd_addr_p1_f == 8'h55; // @[ifu_bp_ctl.scala 421:83] + wire _T_4330 = btb_rd_addr_p1_f == 8'h55; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4757 = _T_4330 ? btb_bank0_rd_data_way0_out_85 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5012 = _T_5011 | _T_4757; // @[Mux.scala 27:72] - wire _T_4332 = btb_rd_addr_p1_f == 8'h56; // @[ifu_bp_ctl.scala 421:83] + wire _T_4332 = btb_rd_addr_p1_f == 8'h56; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4758 = _T_4332 ? btb_bank0_rd_data_way0_out_86 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5013 = _T_5012 | _T_4758; // @[Mux.scala 27:72] - wire _T_4334 = btb_rd_addr_p1_f == 8'h57; // @[ifu_bp_ctl.scala 421:83] + wire _T_4334 = btb_rd_addr_p1_f == 8'h57; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4759 = _T_4334 ? btb_bank0_rd_data_way0_out_87 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5014 = _T_5013 | _T_4759; // @[Mux.scala 27:72] - wire _T_4336 = btb_rd_addr_p1_f == 8'h58; // @[ifu_bp_ctl.scala 421:83] + wire _T_4336 = btb_rd_addr_p1_f == 8'h58; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4760 = _T_4336 ? btb_bank0_rd_data_way0_out_88 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5015 = _T_5014 | _T_4760; // @[Mux.scala 27:72] - wire _T_4338 = btb_rd_addr_p1_f == 8'h59; // @[ifu_bp_ctl.scala 421:83] + wire _T_4338 = btb_rd_addr_p1_f == 8'h59; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4761 = _T_4338 ? btb_bank0_rd_data_way0_out_89 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5016 = _T_5015 | _T_4761; // @[Mux.scala 27:72] - wire _T_4340 = btb_rd_addr_p1_f == 8'h5a; // @[ifu_bp_ctl.scala 421:83] + wire _T_4340 = btb_rd_addr_p1_f == 8'h5a; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4762 = _T_4340 ? btb_bank0_rd_data_way0_out_90 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5017 = _T_5016 | _T_4762; // @[Mux.scala 27:72] - wire _T_4342 = btb_rd_addr_p1_f == 8'h5b; // @[ifu_bp_ctl.scala 421:83] + wire _T_4342 = btb_rd_addr_p1_f == 8'h5b; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4763 = _T_4342 ? btb_bank0_rd_data_way0_out_91 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5018 = _T_5017 | _T_4763; // @[Mux.scala 27:72] - wire _T_4344 = btb_rd_addr_p1_f == 8'h5c; // @[ifu_bp_ctl.scala 421:83] + wire _T_4344 = btb_rd_addr_p1_f == 8'h5c; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4764 = _T_4344 ? btb_bank0_rd_data_way0_out_92 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5019 = _T_5018 | _T_4764; // @[Mux.scala 27:72] - wire _T_4346 = btb_rd_addr_p1_f == 8'h5d; // @[ifu_bp_ctl.scala 421:83] + wire _T_4346 = btb_rd_addr_p1_f == 8'h5d; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4765 = _T_4346 ? btb_bank0_rd_data_way0_out_93 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5020 = _T_5019 | _T_4765; // @[Mux.scala 27:72] - wire _T_4348 = btb_rd_addr_p1_f == 8'h5e; // @[ifu_bp_ctl.scala 421:83] + wire _T_4348 = btb_rd_addr_p1_f == 8'h5e; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4766 = _T_4348 ? btb_bank0_rd_data_way0_out_94 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5021 = _T_5020 | _T_4766; // @[Mux.scala 27:72] - wire _T_4350 = btb_rd_addr_p1_f == 8'h5f; // @[ifu_bp_ctl.scala 421:83] + wire _T_4350 = btb_rd_addr_p1_f == 8'h5f; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4767 = _T_4350 ? btb_bank0_rd_data_way0_out_95 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5022 = _T_5021 | _T_4767; // @[Mux.scala 27:72] - wire _T_4352 = btb_rd_addr_p1_f == 8'h60; // @[ifu_bp_ctl.scala 421:83] + wire _T_4352 = btb_rd_addr_p1_f == 8'h60; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4768 = _T_4352 ? btb_bank0_rd_data_way0_out_96 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5023 = _T_5022 | _T_4768; // @[Mux.scala 27:72] - wire _T_4354 = btb_rd_addr_p1_f == 8'h61; // @[ifu_bp_ctl.scala 421:83] + wire _T_4354 = btb_rd_addr_p1_f == 8'h61; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4769 = _T_4354 ? btb_bank0_rd_data_way0_out_97 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5024 = _T_5023 | _T_4769; // @[Mux.scala 27:72] - wire _T_4356 = btb_rd_addr_p1_f == 8'h62; // @[ifu_bp_ctl.scala 421:83] + wire _T_4356 = btb_rd_addr_p1_f == 8'h62; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4770 = _T_4356 ? btb_bank0_rd_data_way0_out_98 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5025 = _T_5024 | _T_4770; // @[Mux.scala 27:72] - wire _T_4358 = btb_rd_addr_p1_f == 8'h63; // @[ifu_bp_ctl.scala 421:83] + wire _T_4358 = btb_rd_addr_p1_f == 8'h63; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4771 = _T_4358 ? btb_bank0_rd_data_way0_out_99 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5026 = _T_5025 | _T_4771; // @[Mux.scala 27:72] - wire _T_4360 = btb_rd_addr_p1_f == 8'h64; // @[ifu_bp_ctl.scala 421:83] + wire _T_4360 = btb_rd_addr_p1_f == 8'h64; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4772 = _T_4360 ? btb_bank0_rd_data_way0_out_100 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5027 = _T_5026 | _T_4772; // @[Mux.scala 27:72] - wire _T_4362 = btb_rd_addr_p1_f == 8'h65; // @[ifu_bp_ctl.scala 421:83] + wire _T_4362 = btb_rd_addr_p1_f == 8'h65; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4773 = _T_4362 ? btb_bank0_rd_data_way0_out_101 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5028 = _T_5027 | _T_4773; // @[Mux.scala 27:72] - wire _T_4364 = btb_rd_addr_p1_f == 8'h66; // @[ifu_bp_ctl.scala 421:83] + wire _T_4364 = btb_rd_addr_p1_f == 8'h66; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4774 = _T_4364 ? btb_bank0_rd_data_way0_out_102 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5029 = _T_5028 | _T_4774; // @[Mux.scala 27:72] - wire _T_4366 = btb_rd_addr_p1_f == 8'h67; // @[ifu_bp_ctl.scala 421:83] + wire _T_4366 = btb_rd_addr_p1_f == 8'h67; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4775 = _T_4366 ? btb_bank0_rd_data_way0_out_103 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5030 = _T_5029 | _T_4775; // @[Mux.scala 27:72] - wire _T_4368 = btb_rd_addr_p1_f == 8'h68; // @[ifu_bp_ctl.scala 421:83] + wire _T_4368 = btb_rd_addr_p1_f == 8'h68; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4776 = _T_4368 ? btb_bank0_rd_data_way0_out_104 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5031 = _T_5030 | _T_4776; // @[Mux.scala 27:72] - wire _T_4370 = btb_rd_addr_p1_f == 8'h69; // @[ifu_bp_ctl.scala 421:83] + wire _T_4370 = btb_rd_addr_p1_f == 8'h69; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4777 = _T_4370 ? btb_bank0_rd_data_way0_out_105 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5032 = _T_5031 | _T_4777; // @[Mux.scala 27:72] - wire _T_4372 = btb_rd_addr_p1_f == 8'h6a; // @[ifu_bp_ctl.scala 421:83] + wire _T_4372 = btb_rd_addr_p1_f == 8'h6a; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4778 = _T_4372 ? btb_bank0_rd_data_way0_out_106 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5033 = _T_5032 | _T_4778; // @[Mux.scala 27:72] - wire _T_4374 = btb_rd_addr_p1_f == 8'h6b; // @[ifu_bp_ctl.scala 421:83] + wire _T_4374 = btb_rd_addr_p1_f == 8'h6b; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4779 = _T_4374 ? btb_bank0_rd_data_way0_out_107 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5034 = _T_5033 | _T_4779; // @[Mux.scala 27:72] - wire _T_4376 = btb_rd_addr_p1_f == 8'h6c; // @[ifu_bp_ctl.scala 421:83] + wire _T_4376 = btb_rd_addr_p1_f == 8'h6c; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4780 = _T_4376 ? btb_bank0_rd_data_way0_out_108 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5035 = _T_5034 | _T_4780; // @[Mux.scala 27:72] - wire _T_4378 = btb_rd_addr_p1_f == 8'h6d; // @[ifu_bp_ctl.scala 421:83] + wire _T_4378 = btb_rd_addr_p1_f == 8'h6d; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4781 = _T_4378 ? btb_bank0_rd_data_way0_out_109 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5036 = _T_5035 | _T_4781; // @[Mux.scala 27:72] - wire _T_4380 = btb_rd_addr_p1_f == 8'h6e; // @[ifu_bp_ctl.scala 421:83] + wire _T_4380 = btb_rd_addr_p1_f == 8'h6e; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4782 = _T_4380 ? btb_bank0_rd_data_way0_out_110 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5037 = _T_5036 | _T_4782; // @[Mux.scala 27:72] - wire _T_4382 = btb_rd_addr_p1_f == 8'h6f; // @[ifu_bp_ctl.scala 421:83] + wire _T_4382 = btb_rd_addr_p1_f == 8'h6f; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4783 = _T_4382 ? btb_bank0_rd_data_way0_out_111 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5038 = _T_5037 | _T_4783; // @[Mux.scala 27:72] - wire _T_4384 = btb_rd_addr_p1_f == 8'h70; // @[ifu_bp_ctl.scala 421:83] + wire _T_4384 = btb_rd_addr_p1_f == 8'h70; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4784 = _T_4384 ? btb_bank0_rd_data_way0_out_112 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5039 = _T_5038 | _T_4784; // @[Mux.scala 27:72] - wire _T_4386 = btb_rd_addr_p1_f == 8'h71; // @[ifu_bp_ctl.scala 421:83] + wire _T_4386 = btb_rd_addr_p1_f == 8'h71; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4785 = _T_4386 ? btb_bank0_rd_data_way0_out_113 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5040 = _T_5039 | _T_4785; // @[Mux.scala 27:72] - wire _T_4388 = btb_rd_addr_p1_f == 8'h72; // @[ifu_bp_ctl.scala 421:83] + wire _T_4388 = btb_rd_addr_p1_f == 8'h72; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4786 = _T_4388 ? btb_bank0_rd_data_way0_out_114 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5041 = _T_5040 | _T_4786; // @[Mux.scala 27:72] - wire _T_4390 = btb_rd_addr_p1_f == 8'h73; // @[ifu_bp_ctl.scala 421:83] + wire _T_4390 = btb_rd_addr_p1_f == 8'h73; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4787 = _T_4390 ? btb_bank0_rd_data_way0_out_115 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5042 = _T_5041 | _T_4787; // @[Mux.scala 27:72] - wire _T_4392 = btb_rd_addr_p1_f == 8'h74; // @[ifu_bp_ctl.scala 421:83] + wire _T_4392 = btb_rd_addr_p1_f == 8'h74; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4788 = _T_4392 ? btb_bank0_rd_data_way0_out_116 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5043 = _T_5042 | _T_4788; // @[Mux.scala 27:72] - wire _T_4394 = btb_rd_addr_p1_f == 8'h75; // @[ifu_bp_ctl.scala 421:83] + wire _T_4394 = btb_rd_addr_p1_f == 8'h75; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4789 = _T_4394 ? btb_bank0_rd_data_way0_out_117 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5044 = _T_5043 | _T_4789; // @[Mux.scala 27:72] - wire _T_4396 = btb_rd_addr_p1_f == 8'h76; // @[ifu_bp_ctl.scala 421:83] + wire _T_4396 = btb_rd_addr_p1_f == 8'h76; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4790 = _T_4396 ? btb_bank0_rd_data_way0_out_118 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5045 = _T_5044 | _T_4790; // @[Mux.scala 27:72] - wire _T_4398 = btb_rd_addr_p1_f == 8'h77; // @[ifu_bp_ctl.scala 421:83] + wire _T_4398 = btb_rd_addr_p1_f == 8'h77; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4791 = _T_4398 ? btb_bank0_rd_data_way0_out_119 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5046 = _T_5045 | _T_4791; // @[Mux.scala 27:72] - wire _T_4400 = btb_rd_addr_p1_f == 8'h78; // @[ifu_bp_ctl.scala 421:83] + wire _T_4400 = btb_rd_addr_p1_f == 8'h78; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4792 = _T_4400 ? btb_bank0_rd_data_way0_out_120 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5047 = _T_5046 | _T_4792; // @[Mux.scala 27:72] - wire _T_4402 = btb_rd_addr_p1_f == 8'h79; // @[ifu_bp_ctl.scala 421:83] + wire _T_4402 = btb_rd_addr_p1_f == 8'h79; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4793 = _T_4402 ? btb_bank0_rd_data_way0_out_121 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5048 = _T_5047 | _T_4793; // @[Mux.scala 27:72] - wire _T_4404 = btb_rd_addr_p1_f == 8'h7a; // @[ifu_bp_ctl.scala 421:83] + wire _T_4404 = btb_rd_addr_p1_f == 8'h7a; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4794 = _T_4404 ? btb_bank0_rd_data_way0_out_122 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5049 = _T_5048 | _T_4794; // @[Mux.scala 27:72] - wire _T_4406 = btb_rd_addr_p1_f == 8'h7b; // @[ifu_bp_ctl.scala 421:83] + wire _T_4406 = btb_rd_addr_p1_f == 8'h7b; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4795 = _T_4406 ? btb_bank0_rd_data_way0_out_123 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5050 = _T_5049 | _T_4795; // @[Mux.scala 27:72] - wire _T_4408 = btb_rd_addr_p1_f == 8'h7c; // @[ifu_bp_ctl.scala 421:83] + wire _T_4408 = btb_rd_addr_p1_f == 8'h7c; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4796 = _T_4408 ? btb_bank0_rd_data_way0_out_124 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5051 = _T_5050 | _T_4796; // @[Mux.scala 27:72] - wire _T_4410 = btb_rd_addr_p1_f == 8'h7d; // @[ifu_bp_ctl.scala 421:83] + wire _T_4410 = btb_rd_addr_p1_f == 8'h7d; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4797 = _T_4410 ? btb_bank0_rd_data_way0_out_125 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5052 = _T_5051 | _T_4797; // @[Mux.scala 27:72] - wire _T_4412 = btb_rd_addr_p1_f == 8'h7e; // @[ifu_bp_ctl.scala 421:83] + wire _T_4412 = btb_rd_addr_p1_f == 8'h7e; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4798 = _T_4412 ? btb_bank0_rd_data_way0_out_126 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5053 = _T_5052 | _T_4798; // @[Mux.scala 27:72] - wire _T_4414 = btb_rd_addr_p1_f == 8'h7f; // @[ifu_bp_ctl.scala 421:83] + wire _T_4414 = btb_rd_addr_p1_f == 8'h7f; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4799 = _T_4414 ? btb_bank0_rd_data_way0_out_127 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5054 = _T_5053 | _T_4799; // @[Mux.scala 27:72] - wire _T_4416 = btb_rd_addr_p1_f == 8'h80; // @[ifu_bp_ctl.scala 421:83] + wire _T_4416 = btb_rd_addr_p1_f == 8'h80; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4800 = _T_4416 ? btb_bank0_rd_data_way0_out_128 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5055 = _T_5054 | _T_4800; // @[Mux.scala 27:72] - wire _T_4418 = btb_rd_addr_p1_f == 8'h81; // @[ifu_bp_ctl.scala 421:83] + wire _T_4418 = btb_rd_addr_p1_f == 8'h81; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4801 = _T_4418 ? btb_bank0_rd_data_way0_out_129 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5056 = _T_5055 | _T_4801; // @[Mux.scala 27:72] - wire _T_4420 = btb_rd_addr_p1_f == 8'h82; // @[ifu_bp_ctl.scala 421:83] + wire _T_4420 = btb_rd_addr_p1_f == 8'h82; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4802 = _T_4420 ? btb_bank0_rd_data_way0_out_130 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5057 = _T_5056 | _T_4802; // @[Mux.scala 27:72] - wire _T_4422 = btb_rd_addr_p1_f == 8'h83; // @[ifu_bp_ctl.scala 421:83] + wire _T_4422 = btb_rd_addr_p1_f == 8'h83; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4803 = _T_4422 ? btb_bank0_rd_data_way0_out_131 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5058 = _T_5057 | _T_4803; // @[Mux.scala 27:72] - wire _T_4424 = btb_rd_addr_p1_f == 8'h84; // @[ifu_bp_ctl.scala 421:83] + wire _T_4424 = btb_rd_addr_p1_f == 8'h84; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4804 = _T_4424 ? btb_bank0_rd_data_way0_out_132 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5059 = _T_5058 | _T_4804; // @[Mux.scala 27:72] - wire _T_4426 = btb_rd_addr_p1_f == 8'h85; // @[ifu_bp_ctl.scala 421:83] + wire _T_4426 = btb_rd_addr_p1_f == 8'h85; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4805 = _T_4426 ? btb_bank0_rd_data_way0_out_133 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5060 = _T_5059 | _T_4805; // @[Mux.scala 27:72] - wire _T_4428 = btb_rd_addr_p1_f == 8'h86; // @[ifu_bp_ctl.scala 421:83] + wire _T_4428 = btb_rd_addr_p1_f == 8'h86; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4806 = _T_4428 ? btb_bank0_rd_data_way0_out_134 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5061 = _T_5060 | _T_4806; // @[Mux.scala 27:72] - wire _T_4430 = btb_rd_addr_p1_f == 8'h87; // @[ifu_bp_ctl.scala 421:83] + wire _T_4430 = btb_rd_addr_p1_f == 8'h87; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4807 = _T_4430 ? btb_bank0_rd_data_way0_out_135 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5062 = _T_5061 | _T_4807; // @[Mux.scala 27:72] - wire _T_4432 = btb_rd_addr_p1_f == 8'h88; // @[ifu_bp_ctl.scala 421:83] + wire _T_4432 = btb_rd_addr_p1_f == 8'h88; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4808 = _T_4432 ? btb_bank0_rd_data_way0_out_136 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5063 = _T_5062 | _T_4808; // @[Mux.scala 27:72] - wire _T_4434 = btb_rd_addr_p1_f == 8'h89; // @[ifu_bp_ctl.scala 421:83] + wire _T_4434 = btb_rd_addr_p1_f == 8'h89; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4809 = _T_4434 ? btb_bank0_rd_data_way0_out_137 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5064 = _T_5063 | _T_4809; // @[Mux.scala 27:72] - wire _T_4436 = btb_rd_addr_p1_f == 8'h8a; // @[ifu_bp_ctl.scala 421:83] + wire _T_4436 = btb_rd_addr_p1_f == 8'h8a; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4810 = _T_4436 ? btb_bank0_rd_data_way0_out_138 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5065 = _T_5064 | _T_4810; // @[Mux.scala 27:72] - wire _T_4438 = btb_rd_addr_p1_f == 8'h8b; // @[ifu_bp_ctl.scala 421:83] + wire _T_4438 = btb_rd_addr_p1_f == 8'h8b; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4811 = _T_4438 ? btb_bank0_rd_data_way0_out_139 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5066 = _T_5065 | _T_4811; // @[Mux.scala 27:72] - wire _T_4440 = btb_rd_addr_p1_f == 8'h8c; // @[ifu_bp_ctl.scala 421:83] + wire _T_4440 = btb_rd_addr_p1_f == 8'h8c; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4812 = _T_4440 ? btb_bank0_rd_data_way0_out_140 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5067 = _T_5066 | _T_4812; // @[Mux.scala 27:72] - wire _T_4442 = btb_rd_addr_p1_f == 8'h8d; // @[ifu_bp_ctl.scala 421:83] + wire _T_4442 = btb_rd_addr_p1_f == 8'h8d; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4813 = _T_4442 ? btb_bank0_rd_data_way0_out_141 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5068 = _T_5067 | _T_4813; // @[Mux.scala 27:72] - wire _T_4444 = btb_rd_addr_p1_f == 8'h8e; // @[ifu_bp_ctl.scala 421:83] + wire _T_4444 = btb_rd_addr_p1_f == 8'h8e; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4814 = _T_4444 ? btb_bank0_rd_data_way0_out_142 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5069 = _T_5068 | _T_4814; // @[Mux.scala 27:72] - wire _T_4446 = btb_rd_addr_p1_f == 8'h8f; // @[ifu_bp_ctl.scala 421:83] + wire _T_4446 = btb_rd_addr_p1_f == 8'h8f; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4815 = _T_4446 ? btb_bank0_rd_data_way0_out_143 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5070 = _T_5069 | _T_4815; // @[Mux.scala 27:72] - wire _T_4448 = btb_rd_addr_p1_f == 8'h90; // @[ifu_bp_ctl.scala 421:83] + wire _T_4448 = btb_rd_addr_p1_f == 8'h90; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4816 = _T_4448 ? btb_bank0_rd_data_way0_out_144 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5071 = _T_5070 | _T_4816; // @[Mux.scala 27:72] - wire _T_4450 = btb_rd_addr_p1_f == 8'h91; // @[ifu_bp_ctl.scala 421:83] + wire _T_4450 = btb_rd_addr_p1_f == 8'h91; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4817 = _T_4450 ? btb_bank0_rd_data_way0_out_145 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5072 = _T_5071 | _T_4817; // @[Mux.scala 27:72] - wire _T_4452 = btb_rd_addr_p1_f == 8'h92; // @[ifu_bp_ctl.scala 421:83] + wire _T_4452 = btb_rd_addr_p1_f == 8'h92; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4818 = _T_4452 ? btb_bank0_rd_data_way0_out_146 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5073 = _T_5072 | _T_4818; // @[Mux.scala 27:72] - wire _T_4454 = btb_rd_addr_p1_f == 8'h93; // @[ifu_bp_ctl.scala 421:83] + wire _T_4454 = btb_rd_addr_p1_f == 8'h93; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4819 = _T_4454 ? btb_bank0_rd_data_way0_out_147 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5074 = _T_5073 | _T_4819; // @[Mux.scala 27:72] - wire _T_4456 = btb_rd_addr_p1_f == 8'h94; // @[ifu_bp_ctl.scala 421:83] + wire _T_4456 = btb_rd_addr_p1_f == 8'h94; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4820 = _T_4456 ? btb_bank0_rd_data_way0_out_148 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5075 = _T_5074 | _T_4820; // @[Mux.scala 27:72] - wire _T_4458 = btb_rd_addr_p1_f == 8'h95; // @[ifu_bp_ctl.scala 421:83] + wire _T_4458 = btb_rd_addr_p1_f == 8'h95; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4821 = _T_4458 ? btb_bank0_rd_data_way0_out_149 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5076 = _T_5075 | _T_4821; // @[Mux.scala 27:72] - wire _T_4460 = btb_rd_addr_p1_f == 8'h96; // @[ifu_bp_ctl.scala 421:83] + wire _T_4460 = btb_rd_addr_p1_f == 8'h96; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4822 = _T_4460 ? btb_bank0_rd_data_way0_out_150 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5077 = _T_5076 | _T_4822; // @[Mux.scala 27:72] - wire _T_4462 = btb_rd_addr_p1_f == 8'h97; // @[ifu_bp_ctl.scala 421:83] + wire _T_4462 = btb_rd_addr_p1_f == 8'h97; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4823 = _T_4462 ? btb_bank0_rd_data_way0_out_151 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5078 = _T_5077 | _T_4823; // @[Mux.scala 27:72] - wire _T_4464 = btb_rd_addr_p1_f == 8'h98; // @[ifu_bp_ctl.scala 421:83] + wire _T_4464 = btb_rd_addr_p1_f == 8'h98; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4824 = _T_4464 ? btb_bank0_rd_data_way0_out_152 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5079 = _T_5078 | _T_4824; // @[Mux.scala 27:72] - wire _T_4466 = btb_rd_addr_p1_f == 8'h99; // @[ifu_bp_ctl.scala 421:83] + wire _T_4466 = btb_rd_addr_p1_f == 8'h99; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4825 = _T_4466 ? btb_bank0_rd_data_way0_out_153 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5080 = _T_5079 | _T_4825; // @[Mux.scala 27:72] - wire _T_4468 = btb_rd_addr_p1_f == 8'h9a; // @[ifu_bp_ctl.scala 421:83] + wire _T_4468 = btb_rd_addr_p1_f == 8'h9a; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4826 = _T_4468 ? btb_bank0_rd_data_way0_out_154 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5081 = _T_5080 | _T_4826; // @[Mux.scala 27:72] - wire _T_4470 = btb_rd_addr_p1_f == 8'h9b; // @[ifu_bp_ctl.scala 421:83] + wire _T_4470 = btb_rd_addr_p1_f == 8'h9b; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4827 = _T_4470 ? btb_bank0_rd_data_way0_out_155 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5082 = _T_5081 | _T_4827; // @[Mux.scala 27:72] - wire _T_4472 = btb_rd_addr_p1_f == 8'h9c; // @[ifu_bp_ctl.scala 421:83] + wire _T_4472 = btb_rd_addr_p1_f == 8'h9c; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4828 = _T_4472 ? btb_bank0_rd_data_way0_out_156 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5083 = _T_5082 | _T_4828; // @[Mux.scala 27:72] - wire _T_4474 = btb_rd_addr_p1_f == 8'h9d; // @[ifu_bp_ctl.scala 421:83] + wire _T_4474 = btb_rd_addr_p1_f == 8'h9d; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4829 = _T_4474 ? btb_bank0_rd_data_way0_out_157 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5084 = _T_5083 | _T_4829; // @[Mux.scala 27:72] - wire _T_4476 = btb_rd_addr_p1_f == 8'h9e; // @[ifu_bp_ctl.scala 421:83] + wire _T_4476 = btb_rd_addr_p1_f == 8'h9e; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4830 = _T_4476 ? btb_bank0_rd_data_way0_out_158 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5085 = _T_5084 | _T_4830; // @[Mux.scala 27:72] - wire _T_4478 = btb_rd_addr_p1_f == 8'h9f; // @[ifu_bp_ctl.scala 421:83] + wire _T_4478 = btb_rd_addr_p1_f == 8'h9f; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4831 = _T_4478 ? btb_bank0_rd_data_way0_out_159 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5086 = _T_5085 | _T_4831; // @[Mux.scala 27:72] - wire _T_4480 = btb_rd_addr_p1_f == 8'ha0; // @[ifu_bp_ctl.scala 421:83] + wire _T_4480 = btb_rd_addr_p1_f == 8'ha0; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4832 = _T_4480 ? btb_bank0_rd_data_way0_out_160 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5087 = _T_5086 | _T_4832; // @[Mux.scala 27:72] - wire _T_4482 = btb_rd_addr_p1_f == 8'ha1; // @[ifu_bp_ctl.scala 421:83] + wire _T_4482 = btb_rd_addr_p1_f == 8'ha1; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4833 = _T_4482 ? btb_bank0_rd_data_way0_out_161 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5088 = _T_5087 | _T_4833; // @[Mux.scala 27:72] - wire _T_4484 = btb_rd_addr_p1_f == 8'ha2; // @[ifu_bp_ctl.scala 421:83] + wire _T_4484 = btb_rd_addr_p1_f == 8'ha2; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4834 = _T_4484 ? btb_bank0_rd_data_way0_out_162 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5089 = _T_5088 | _T_4834; // @[Mux.scala 27:72] - wire _T_4486 = btb_rd_addr_p1_f == 8'ha3; // @[ifu_bp_ctl.scala 421:83] + wire _T_4486 = btb_rd_addr_p1_f == 8'ha3; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4835 = _T_4486 ? btb_bank0_rd_data_way0_out_163 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5090 = _T_5089 | _T_4835; // @[Mux.scala 27:72] - wire _T_4488 = btb_rd_addr_p1_f == 8'ha4; // @[ifu_bp_ctl.scala 421:83] + wire _T_4488 = btb_rd_addr_p1_f == 8'ha4; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4836 = _T_4488 ? btb_bank0_rd_data_way0_out_164 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5091 = _T_5090 | _T_4836; // @[Mux.scala 27:72] - wire _T_4490 = btb_rd_addr_p1_f == 8'ha5; // @[ifu_bp_ctl.scala 421:83] + wire _T_4490 = btb_rd_addr_p1_f == 8'ha5; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4837 = _T_4490 ? btb_bank0_rd_data_way0_out_165 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5092 = _T_5091 | _T_4837; // @[Mux.scala 27:72] - wire _T_4492 = btb_rd_addr_p1_f == 8'ha6; // @[ifu_bp_ctl.scala 421:83] + wire _T_4492 = btb_rd_addr_p1_f == 8'ha6; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4838 = _T_4492 ? btb_bank0_rd_data_way0_out_166 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5093 = _T_5092 | _T_4838; // @[Mux.scala 27:72] - wire _T_4494 = btb_rd_addr_p1_f == 8'ha7; // @[ifu_bp_ctl.scala 421:83] + wire _T_4494 = btb_rd_addr_p1_f == 8'ha7; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4839 = _T_4494 ? btb_bank0_rd_data_way0_out_167 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5094 = _T_5093 | _T_4839; // @[Mux.scala 27:72] - wire _T_4496 = btb_rd_addr_p1_f == 8'ha8; // @[ifu_bp_ctl.scala 421:83] + wire _T_4496 = btb_rd_addr_p1_f == 8'ha8; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4840 = _T_4496 ? btb_bank0_rd_data_way0_out_168 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5095 = _T_5094 | _T_4840; // @[Mux.scala 27:72] - wire _T_4498 = btb_rd_addr_p1_f == 8'ha9; // @[ifu_bp_ctl.scala 421:83] + wire _T_4498 = btb_rd_addr_p1_f == 8'ha9; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4841 = _T_4498 ? btb_bank0_rd_data_way0_out_169 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5096 = _T_5095 | _T_4841; // @[Mux.scala 27:72] - wire _T_4500 = btb_rd_addr_p1_f == 8'haa; // @[ifu_bp_ctl.scala 421:83] + wire _T_4500 = btb_rd_addr_p1_f == 8'haa; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4842 = _T_4500 ? btb_bank0_rd_data_way0_out_170 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5097 = _T_5096 | _T_4842; // @[Mux.scala 27:72] - wire _T_4502 = btb_rd_addr_p1_f == 8'hab; // @[ifu_bp_ctl.scala 421:83] + wire _T_4502 = btb_rd_addr_p1_f == 8'hab; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4843 = _T_4502 ? btb_bank0_rd_data_way0_out_171 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5098 = _T_5097 | _T_4843; // @[Mux.scala 27:72] - wire _T_4504 = btb_rd_addr_p1_f == 8'hac; // @[ifu_bp_ctl.scala 421:83] + wire _T_4504 = btb_rd_addr_p1_f == 8'hac; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4844 = _T_4504 ? btb_bank0_rd_data_way0_out_172 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5099 = _T_5098 | _T_4844; // @[Mux.scala 27:72] - wire _T_4506 = btb_rd_addr_p1_f == 8'had; // @[ifu_bp_ctl.scala 421:83] + wire _T_4506 = btb_rd_addr_p1_f == 8'had; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4845 = _T_4506 ? btb_bank0_rd_data_way0_out_173 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5100 = _T_5099 | _T_4845; // @[Mux.scala 27:72] - wire _T_4508 = btb_rd_addr_p1_f == 8'hae; // @[ifu_bp_ctl.scala 421:83] + wire _T_4508 = btb_rd_addr_p1_f == 8'hae; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4846 = _T_4508 ? btb_bank0_rd_data_way0_out_174 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5101 = _T_5100 | _T_4846; // @[Mux.scala 27:72] - wire _T_4510 = btb_rd_addr_p1_f == 8'haf; // @[ifu_bp_ctl.scala 421:83] + wire _T_4510 = btb_rd_addr_p1_f == 8'haf; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4847 = _T_4510 ? btb_bank0_rd_data_way0_out_175 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5102 = _T_5101 | _T_4847; // @[Mux.scala 27:72] - wire _T_4512 = btb_rd_addr_p1_f == 8'hb0; // @[ifu_bp_ctl.scala 421:83] + wire _T_4512 = btb_rd_addr_p1_f == 8'hb0; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4848 = _T_4512 ? btb_bank0_rd_data_way0_out_176 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5103 = _T_5102 | _T_4848; // @[Mux.scala 27:72] - wire _T_4514 = btb_rd_addr_p1_f == 8'hb1; // @[ifu_bp_ctl.scala 421:83] + wire _T_4514 = btb_rd_addr_p1_f == 8'hb1; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4849 = _T_4514 ? btb_bank0_rd_data_way0_out_177 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5104 = _T_5103 | _T_4849; // @[Mux.scala 27:72] - wire _T_4516 = btb_rd_addr_p1_f == 8'hb2; // @[ifu_bp_ctl.scala 421:83] + wire _T_4516 = btb_rd_addr_p1_f == 8'hb2; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4850 = _T_4516 ? btb_bank0_rd_data_way0_out_178 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5105 = _T_5104 | _T_4850; // @[Mux.scala 27:72] - wire _T_4518 = btb_rd_addr_p1_f == 8'hb3; // @[ifu_bp_ctl.scala 421:83] + wire _T_4518 = btb_rd_addr_p1_f == 8'hb3; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4851 = _T_4518 ? btb_bank0_rd_data_way0_out_179 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5106 = _T_5105 | _T_4851; // @[Mux.scala 27:72] - wire _T_4520 = btb_rd_addr_p1_f == 8'hb4; // @[ifu_bp_ctl.scala 421:83] + wire _T_4520 = btb_rd_addr_p1_f == 8'hb4; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4852 = _T_4520 ? btb_bank0_rd_data_way0_out_180 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5107 = _T_5106 | _T_4852; // @[Mux.scala 27:72] - wire _T_4522 = btb_rd_addr_p1_f == 8'hb5; // @[ifu_bp_ctl.scala 421:83] + wire _T_4522 = btb_rd_addr_p1_f == 8'hb5; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4853 = _T_4522 ? btb_bank0_rd_data_way0_out_181 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5108 = _T_5107 | _T_4853; // @[Mux.scala 27:72] - wire _T_4524 = btb_rd_addr_p1_f == 8'hb6; // @[ifu_bp_ctl.scala 421:83] + wire _T_4524 = btb_rd_addr_p1_f == 8'hb6; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4854 = _T_4524 ? btb_bank0_rd_data_way0_out_182 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5109 = _T_5108 | _T_4854; // @[Mux.scala 27:72] - wire _T_4526 = btb_rd_addr_p1_f == 8'hb7; // @[ifu_bp_ctl.scala 421:83] + wire _T_4526 = btb_rd_addr_p1_f == 8'hb7; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4855 = _T_4526 ? btb_bank0_rd_data_way0_out_183 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5110 = _T_5109 | _T_4855; // @[Mux.scala 27:72] - wire _T_4528 = btb_rd_addr_p1_f == 8'hb8; // @[ifu_bp_ctl.scala 421:83] + wire _T_4528 = btb_rd_addr_p1_f == 8'hb8; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4856 = _T_4528 ? btb_bank0_rd_data_way0_out_184 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5111 = _T_5110 | _T_4856; // @[Mux.scala 27:72] - wire _T_4530 = btb_rd_addr_p1_f == 8'hb9; // @[ifu_bp_ctl.scala 421:83] + wire _T_4530 = btb_rd_addr_p1_f == 8'hb9; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4857 = _T_4530 ? btb_bank0_rd_data_way0_out_185 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5112 = _T_5111 | _T_4857; // @[Mux.scala 27:72] - wire _T_4532 = btb_rd_addr_p1_f == 8'hba; // @[ifu_bp_ctl.scala 421:83] + wire _T_4532 = btb_rd_addr_p1_f == 8'hba; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4858 = _T_4532 ? btb_bank0_rd_data_way0_out_186 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5113 = _T_5112 | _T_4858; // @[Mux.scala 27:72] - wire _T_4534 = btb_rd_addr_p1_f == 8'hbb; // @[ifu_bp_ctl.scala 421:83] + wire _T_4534 = btb_rd_addr_p1_f == 8'hbb; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4859 = _T_4534 ? btb_bank0_rd_data_way0_out_187 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5114 = _T_5113 | _T_4859; // @[Mux.scala 27:72] - wire _T_4536 = btb_rd_addr_p1_f == 8'hbc; // @[ifu_bp_ctl.scala 421:83] + wire _T_4536 = btb_rd_addr_p1_f == 8'hbc; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4860 = _T_4536 ? btb_bank0_rd_data_way0_out_188 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5115 = _T_5114 | _T_4860; // @[Mux.scala 27:72] - wire _T_4538 = btb_rd_addr_p1_f == 8'hbd; // @[ifu_bp_ctl.scala 421:83] + wire _T_4538 = btb_rd_addr_p1_f == 8'hbd; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4861 = _T_4538 ? btb_bank0_rd_data_way0_out_189 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5116 = _T_5115 | _T_4861; // @[Mux.scala 27:72] - wire _T_4540 = btb_rd_addr_p1_f == 8'hbe; // @[ifu_bp_ctl.scala 421:83] + wire _T_4540 = btb_rd_addr_p1_f == 8'hbe; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4862 = _T_4540 ? btb_bank0_rd_data_way0_out_190 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5117 = _T_5116 | _T_4862; // @[Mux.scala 27:72] - wire _T_4542 = btb_rd_addr_p1_f == 8'hbf; // @[ifu_bp_ctl.scala 421:83] + wire _T_4542 = btb_rd_addr_p1_f == 8'hbf; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4863 = _T_4542 ? btb_bank0_rd_data_way0_out_191 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5118 = _T_5117 | _T_4863; // @[Mux.scala 27:72] - wire _T_4544 = btb_rd_addr_p1_f == 8'hc0; // @[ifu_bp_ctl.scala 421:83] + wire _T_4544 = btb_rd_addr_p1_f == 8'hc0; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4864 = _T_4544 ? btb_bank0_rd_data_way0_out_192 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5119 = _T_5118 | _T_4864; // @[Mux.scala 27:72] - wire _T_4546 = btb_rd_addr_p1_f == 8'hc1; // @[ifu_bp_ctl.scala 421:83] + wire _T_4546 = btb_rd_addr_p1_f == 8'hc1; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4865 = _T_4546 ? btb_bank0_rd_data_way0_out_193 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5120 = _T_5119 | _T_4865; // @[Mux.scala 27:72] - wire _T_4548 = btb_rd_addr_p1_f == 8'hc2; // @[ifu_bp_ctl.scala 421:83] + wire _T_4548 = btb_rd_addr_p1_f == 8'hc2; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4866 = _T_4548 ? btb_bank0_rd_data_way0_out_194 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5121 = _T_5120 | _T_4866; // @[Mux.scala 27:72] - wire _T_4550 = btb_rd_addr_p1_f == 8'hc3; // @[ifu_bp_ctl.scala 421:83] + wire _T_4550 = btb_rd_addr_p1_f == 8'hc3; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4867 = _T_4550 ? btb_bank0_rd_data_way0_out_195 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5122 = _T_5121 | _T_4867; // @[Mux.scala 27:72] - wire _T_4552 = btb_rd_addr_p1_f == 8'hc4; // @[ifu_bp_ctl.scala 421:83] + wire _T_4552 = btb_rd_addr_p1_f == 8'hc4; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4868 = _T_4552 ? btb_bank0_rd_data_way0_out_196 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5123 = _T_5122 | _T_4868; // @[Mux.scala 27:72] - wire _T_4554 = btb_rd_addr_p1_f == 8'hc5; // @[ifu_bp_ctl.scala 421:83] + wire _T_4554 = btb_rd_addr_p1_f == 8'hc5; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4869 = _T_4554 ? btb_bank0_rd_data_way0_out_197 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5124 = _T_5123 | _T_4869; // @[Mux.scala 27:72] - wire _T_4556 = btb_rd_addr_p1_f == 8'hc6; // @[ifu_bp_ctl.scala 421:83] + wire _T_4556 = btb_rd_addr_p1_f == 8'hc6; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4870 = _T_4556 ? btb_bank0_rd_data_way0_out_198 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5125 = _T_5124 | _T_4870; // @[Mux.scala 27:72] - wire _T_4558 = btb_rd_addr_p1_f == 8'hc7; // @[ifu_bp_ctl.scala 421:83] + wire _T_4558 = btb_rd_addr_p1_f == 8'hc7; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4871 = _T_4558 ? btb_bank0_rd_data_way0_out_199 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5126 = _T_5125 | _T_4871; // @[Mux.scala 27:72] - wire _T_4560 = btb_rd_addr_p1_f == 8'hc8; // @[ifu_bp_ctl.scala 421:83] + wire _T_4560 = btb_rd_addr_p1_f == 8'hc8; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4872 = _T_4560 ? btb_bank0_rd_data_way0_out_200 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5127 = _T_5126 | _T_4872; // @[Mux.scala 27:72] - wire _T_4562 = btb_rd_addr_p1_f == 8'hc9; // @[ifu_bp_ctl.scala 421:83] + wire _T_4562 = btb_rd_addr_p1_f == 8'hc9; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4873 = _T_4562 ? btb_bank0_rd_data_way0_out_201 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5128 = _T_5127 | _T_4873; // @[Mux.scala 27:72] - wire _T_4564 = btb_rd_addr_p1_f == 8'hca; // @[ifu_bp_ctl.scala 421:83] + wire _T_4564 = btb_rd_addr_p1_f == 8'hca; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4874 = _T_4564 ? btb_bank0_rd_data_way0_out_202 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5129 = _T_5128 | _T_4874; // @[Mux.scala 27:72] - wire _T_4566 = btb_rd_addr_p1_f == 8'hcb; // @[ifu_bp_ctl.scala 421:83] + wire _T_4566 = btb_rd_addr_p1_f == 8'hcb; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4875 = _T_4566 ? btb_bank0_rd_data_way0_out_203 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5130 = _T_5129 | _T_4875; // @[Mux.scala 27:72] - wire _T_4568 = btb_rd_addr_p1_f == 8'hcc; // @[ifu_bp_ctl.scala 421:83] + wire _T_4568 = btb_rd_addr_p1_f == 8'hcc; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4876 = _T_4568 ? btb_bank0_rd_data_way0_out_204 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5131 = _T_5130 | _T_4876; // @[Mux.scala 27:72] - wire _T_4570 = btb_rd_addr_p1_f == 8'hcd; // @[ifu_bp_ctl.scala 421:83] + wire _T_4570 = btb_rd_addr_p1_f == 8'hcd; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4877 = _T_4570 ? btb_bank0_rd_data_way0_out_205 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5132 = _T_5131 | _T_4877; // @[Mux.scala 27:72] - wire _T_4572 = btb_rd_addr_p1_f == 8'hce; // @[ifu_bp_ctl.scala 421:83] + wire _T_4572 = btb_rd_addr_p1_f == 8'hce; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4878 = _T_4572 ? btb_bank0_rd_data_way0_out_206 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5133 = _T_5132 | _T_4878; // @[Mux.scala 27:72] - wire _T_4574 = btb_rd_addr_p1_f == 8'hcf; // @[ifu_bp_ctl.scala 421:83] + wire _T_4574 = btb_rd_addr_p1_f == 8'hcf; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4879 = _T_4574 ? btb_bank0_rd_data_way0_out_207 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5134 = _T_5133 | _T_4879; // @[Mux.scala 27:72] - wire _T_4576 = btb_rd_addr_p1_f == 8'hd0; // @[ifu_bp_ctl.scala 421:83] + wire _T_4576 = btb_rd_addr_p1_f == 8'hd0; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4880 = _T_4576 ? btb_bank0_rd_data_way0_out_208 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5135 = _T_5134 | _T_4880; // @[Mux.scala 27:72] - wire _T_4578 = btb_rd_addr_p1_f == 8'hd1; // @[ifu_bp_ctl.scala 421:83] + wire _T_4578 = btb_rd_addr_p1_f == 8'hd1; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4881 = _T_4578 ? btb_bank0_rd_data_way0_out_209 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5136 = _T_5135 | _T_4881; // @[Mux.scala 27:72] - wire _T_4580 = btb_rd_addr_p1_f == 8'hd2; // @[ifu_bp_ctl.scala 421:83] + wire _T_4580 = btb_rd_addr_p1_f == 8'hd2; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4882 = _T_4580 ? btb_bank0_rd_data_way0_out_210 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5137 = _T_5136 | _T_4882; // @[Mux.scala 27:72] - wire _T_4582 = btb_rd_addr_p1_f == 8'hd3; // @[ifu_bp_ctl.scala 421:83] + wire _T_4582 = btb_rd_addr_p1_f == 8'hd3; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4883 = _T_4582 ? btb_bank0_rd_data_way0_out_211 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5138 = _T_5137 | _T_4883; // @[Mux.scala 27:72] - wire _T_4584 = btb_rd_addr_p1_f == 8'hd4; // @[ifu_bp_ctl.scala 421:83] + wire _T_4584 = btb_rd_addr_p1_f == 8'hd4; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4884 = _T_4584 ? btb_bank0_rd_data_way0_out_212 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5139 = _T_5138 | _T_4884; // @[Mux.scala 27:72] - wire _T_4586 = btb_rd_addr_p1_f == 8'hd5; // @[ifu_bp_ctl.scala 421:83] + wire _T_4586 = btb_rd_addr_p1_f == 8'hd5; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4885 = _T_4586 ? btb_bank0_rd_data_way0_out_213 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5140 = _T_5139 | _T_4885; // @[Mux.scala 27:72] - wire _T_4588 = btb_rd_addr_p1_f == 8'hd6; // @[ifu_bp_ctl.scala 421:83] + wire _T_4588 = btb_rd_addr_p1_f == 8'hd6; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4886 = _T_4588 ? btb_bank0_rd_data_way0_out_214 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5141 = _T_5140 | _T_4886; // @[Mux.scala 27:72] - wire _T_4590 = btb_rd_addr_p1_f == 8'hd7; // @[ifu_bp_ctl.scala 421:83] + wire _T_4590 = btb_rd_addr_p1_f == 8'hd7; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4887 = _T_4590 ? btb_bank0_rd_data_way0_out_215 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5142 = _T_5141 | _T_4887; // @[Mux.scala 27:72] - wire _T_4592 = btb_rd_addr_p1_f == 8'hd8; // @[ifu_bp_ctl.scala 421:83] + wire _T_4592 = btb_rd_addr_p1_f == 8'hd8; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4888 = _T_4592 ? btb_bank0_rd_data_way0_out_216 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5143 = _T_5142 | _T_4888; // @[Mux.scala 27:72] - wire _T_4594 = btb_rd_addr_p1_f == 8'hd9; // @[ifu_bp_ctl.scala 421:83] + wire _T_4594 = btb_rd_addr_p1_f == 8'hd9; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4889 = _T_4594 ? btb_bank0_rd_data_way0_out_217 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5144 = _T_5143 | _T_4889; // @[Mux.scala 27:72] - wire _T_4596 = btb_rd_addr_p1_f == 8'hda; // @[ifu_bp_ctl.scala 421:83] + wire _T_4596 = btb_rd_addr_p1_f == 8'hda; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4890 = _T_4596 ? btb_bank0_rd_data_way0_out_218 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5145 = _T_5144 | _T_4890; // @[Mux.scala 27:72] - wire _T_4598 = btb_rd_addr_p1_f == 8'hdb; // @[ifu_bp_ctl.scala 421:83] + wire _T_4598 = btb_rd_addr_p1_f == 8'hdb; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4891 = _T_4598 ? btb_bank0_rd_data_way0_out_219 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5146 = _T_5145 | _T_4891; // @[Mux.scala 27:72] - wire _T_4600 = btb_rd_addr_p1_f == 8'hdc; // @[ifu_bp_ctl.scala 421:83] + wire _T_4600 = btb_rd_addr_p1_f == 8'hdc; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4892 = _T_4600 ? btb_bank0_rd_data_way0_out_220 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5147 = _T_5146 | _T_4892; // @[Mux.scala 27:72] - wire _T_4602 = btb_rd_addr_p1_f == 8'hdd; // @[ifu_bp_ctl.scala 421:83] + wire _T_4602 = btb_rd_addr_p1_f == 8'hdd; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4893 = _T_4602 ? btb_bank0_rd_data_way0_out_221 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5148 = _T_5147 | _T_4893; // @[Mux.scala 27:72] - wire _T_4604 = btb_rd_addr_p1_f == 8'hde; // @[ifu_bp_ctl.scala 421:83] + wire _T_4604 = btb_rd_addr_p1_f == 8'hde; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4894 = _T_4604 ? btb_bank0_rd_data_way0_out_222 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5149 = _T_5148 | _T_4894; // @[Mux.scala 27:72] - wire _T_4606 = btb_rd_addr_p1_f == 8'hdf; // @[ifu_bp_ctl.scala 421:83] + wire _T_4606 = btb_rd_addr_p1_f == 8'hdf; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4895 = _T_4606 ? btb_bank0_rd_data_way0_out_223 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5150 = _T_5149 | _T_4895; // @[Mux.scala 27:72] - wire _T_4608 = btb_rd_addr_p1_f == 8'he0; // @[ifu_bp_ctl.scala 421:83] + wire _T_4608 = btb_rd_addr_p1_f == 8'he0; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4896 = _T_4608 ? btb_bank0_rd_data_way0_out_224 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5151 = _T_5150 | _T_4896; // @[Mux.scala 27:72] - wire _T_4610 = btb_rd_addr_p1_f == 8'he1; // @[ifu_bp_ctl.scala 421:83] + wire _T_4610 = btb_rd_addr_p1_f == 8'he1; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4897 = _T_4610 ? btb_bank0_rd_data_way0_out_225 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5152 = _T_5151 | _T_4897; // @[Mux.scala 27:72] - wire _T_4612 = btb_rd_addr_p1_f == 8'he2; // @[ifu_bp_ctl.scala 421:83] + wire _T_4612 = btb_rd_addr_p1_f == 8'he2; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4898 = _T_4612 ? btb_bank0_rd_data_way0_out_226 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5153 = _T_5152 | _T_4898; // @[Mux.scala 27:72] - wire _T_4614 = btb_rd_addr_p1_f == 8'he3; // @[ifu_bp_ctl.scala 421:83] + wire _T_4614 = btb_rd_addr_p1_f == 8'he3; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4899 = _T_4614 ? btb_bank0_rd_data_way0_out_227 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5154 = _T_5153 | _T_4899; // @[Mux.scala 27:72] - wire _T_4616 = btb_rd_addr_p1_f == 8'he4; // @[ifu_bp_ctl.scala 421:83] + wire _T_4616 = btb_rd_addr_p1_f == 8'he4; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4900 = _T_4616 ? btb_bank0_rd_data_way0_out_228 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5155 = _T_5154 | _T_4900; // @[Mux.scala 27:72] - wire _T_4618 = btb_rd_addr_p1_f == 8'he5; // @[ifu_bp_ctl.scala 421:83] + wire _T_4618 = btb_rd_addr_p1_f == 8'he5; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4901 = _T_4618 ? btb_bank0_rd_data_way0_out_229 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5156 = _T_5155 | _T_4901; // @[Mux.scala 27:72] - wire _T_4620 = btb_rd_addr_p1_f == 8'he6; // @[ifu_bp_ctl.scala 421:83] + wire _T_4620 = btb_rd_addr_p1_f == 8'he6; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4902 = _T_4620 ? btb_bank0_rd_data_way0_out_230 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5157 = _T_5156 | _T_4902; // @[Mux.scala 27:72] - wire _T_4622 = btb_rd_addr_p1_f == 8'he7; // @[ifu_bp_ctl.scala 421:83] + wire _T_4622 = btb_rd_addr_p1_f == 8'he7; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4903 = _T_4622 ? btb_bank0_rd_data_way0_out_231 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5158 = _T_5157 | _T_4903; // @[Mux.scala 27:72] - wire _T_4624 = btb_rd_addr_p1_f == 8'he8; // @[ifu_bp_ctl.scala 421:83] + wire _T_4624 = btb_rd_addr_p1_f == 8'he8; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4904 = _T_4624 ? btb_bank0_rd_data_way0_out_232 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5159 = _T_5158 | _T_4904; // @[Mux.scala 27:72] - wire _T_4626 = btb_rd_addr_p1_f == 8'he9; // @[ifu_bp_ctl.scala 421:83] + wire _T_4626 = btb_rd_addr_p1_f == 8'he9; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4905 = _T_4626 ? btb_bank0_rd_data_way0_out_233 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5160 = _T_5159 | _T_4905; // @[Mux.scala 27:72] - wire _T_4628 = btb_rd_addr_p1_f == 8'hea; // @[ifu_bp_ctl.scala 421:83] + wire _T_4628 = btb_rd_addr_p1_f == 8'hea; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4906 = _T_4628 ? btb_bank0_rd_data_way0_out_234 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5161 = _T_5160 | _T_4906; // @[Mux.scala 27:72] - wire _T_4630 = btb_rd_addr_p1_f == 8'heb; // @[ifu_bp_ctl.scala 421:83] + wire _T_4630 = btb_rd_addr_p1_f == 8'heb; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4907 = _T_4630 ? btb_bank0_rd_data_way0_out_235 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5162 = _T_5161 | _T_4907; // @[Mux.scala 27:72] - wire _T_4632 = btb_rd_addr_p1_f == 8'hec; // @[ifu_bp_ctl.scala 421:83] + wire _T_4632 = btb_rd_addr_p1_f == 8'hec; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4908 = _T_4632 ? btb_bank0_rd_data_way0_out_236 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5163 = _T_5162 | _T_4908; // @[Mux.scala 27:72] - wire _T_4634 = btb_rd_addr_p1_f == 8'hed; // @[ifu_bp_ctl.scala 421:83] + wire _T_4634 = btb_rd_addr_p1_f == 8'hed; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4909 = _T_4634 ? btb_bank0_rd_data_way0_out_237 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5164 = _T_5163 | _T_4909; // @[Mux.scala 27:72] - wire _T_4636 = btb_rd_addr_p1_f == 8'hee; // @[ifu_bp_ctl.scala 421:83] + wire _T_4636 = btb_rd_addr_p1_f == 8'hee; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4910 = _T_4636 ? btb_bank0_rd_data_way0_out_238 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5165 = _T_5164 | _T_4910; // @[Mux.scala 27:72] - wire _T_4638 = btb_rd_addr_p1_f == 8'hef; // @[ifu_bp_ctl.scala 421:83] + wire _T_4638 = btb_rd_addr_p1_f == 8'hef; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4911 = _T_4638 ? btb_bank0_rd_data_way0_out_239 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5166 = _T_5165 | _T_4911; // @[Mux.scala 27:72] - wire _T_4640 = btb_rd_addr_p1_f == 8'hf0; // @[ifu_bp_ctl.scala 421:83] + wire _T_4640 = btb_rd_addr_p1_f == 8'hf0; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4912 = _T_4640 ? btb_bank0_rd_data_way0_out_240 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5167 = _T_5166 | _T_4912; // @[Mux.scala 27:72] - wire _T_4642 = btb_rd_addr_p1_f == 8'hf1; // @[ifu_bp_ctl.scala 421:83] + wire _T_4642 = btb_rd_addr_p1_f == 8'hf1; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4913 = _T_4642 ? btb_bank0_rd_data_way0_out_241 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5168 = _T_5167 | _T_4913; // @[Mux.scala 27:72] - wire _T_4644 = btb_rd_addr_p1_f == 8'hf2; // @[ifu_bp_ctl.scala 421:83] + wire _T_4644 = btb_rd_addr_p1_f == 8'hf2; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4914 = _T_4644 ? btb_bank0_rd_data_way0_out_242 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5169 = _T_5168 | _T_4914; // @[Mux.scala 27:72] - wire _T_4646 = btb_rd_addr_p1_f == 8'hf3; // @[ifu_bp_ctl.scala 421:83] + wire _T_4646 = btb_rd_addr_p1_f == 8'hf3; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4915 = _T_4646 ? btb_bank0_rd_data_way0_out_243 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5170 = _T_5169 | _T_4915; // @[Mux.scala 27:72] - wire _T_4648 = btb_rd_addr_p1_f == 8'hf4; // @[ifu_bp_ctl.scala 421:83] + wire _T_4648 = btb_rd_addr_p1_f == 8'hf4; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4916 = _T_4648 ? btb_bank0_rd_data_way0_out_244 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5171 = _T_5170 | _T_4916; // @[Mux.scala 27:72] - wire _T_4650 = btb_rd_addr_p1_f == 8'hf5; // @[ifu_bp_ctl.scala 421:83] + wire _T_4650 = btb_rd_addr_p1_f == 8'hf5; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4917 = _T_4650 ? btb_bank0_rd_data_way0_out_245 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5172 = _T_5171 | _T_4917; // @[Mux.scala 27:72] - wire _T_4652 = btb_rd_addr_p1_f == 8'hf6; // @[ifu_bp_ctl.scala 421:83] + wire _T_4652 = btb_rd_addr_p1_f == 8'hf6; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4918 = _T_4652 ? btb_bank0_rd_data_way0_out_246 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5173 = _T_5172 | _T_4918; // @[Mux.scala 27:72] - wire _T_4654 = btb_rd_addr_p1_f == 8'hf7; // @[ifu_bp_ctl.scala 421:83] + wire _T_4654 = btb_rd_addr_p1_f == 8'hf7; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4919 = _T_4654 ? btb_bank0_rd_data_way0_out_247 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5174 = _T_5173 | _T_4919; // @[Mux.scala 27:72] - wire _T_4656 = btb_rd_addr_p1_f == 8'hf8; // @[ifu_bp_ctl.scala 421:83] + wire _T_4656 = btb_rd_addr_p1_f == 8'hf8; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4920 = _T_4656 ? btb_bank0_rd_data_way0_out_248 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5175 = _T_5174 | _T_4920; // @[Mux.scala 27:72] - wire _T_4658 = btb_rd_addr_p1_f == 8'hf9; // @[ifu_bp_ctl.scala 421:83] + wire _T_4658 = btb_rd_addr_p1_f == 8'hf9; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4921 = _T_4658 ? btb_bank0_rd_data_way0_out_249 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5176 = _T_5175 | _T_4921; // @[Mux.scala 27:72] - wire _T_4660 = btb_rd_addr_p1_f == 8'hfa; // @[ifu_bp_ctl.scala 421:83] + wire _T_4660 = btb_rd_addr_p1_f == 8'hfa; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4922 = _T_4660 ? btb_bank0_rd_data_way0_out_250 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5177 = _T_5176 | _T_4922; // @[Mux.scala 27:72] - wire _T_4662 = btb_rd_addr_p1_f == 8'hfb; // @[ifu_bp_ctl.scala 421:83] + wire _T_4662 = btb_rd_addr_p1_f == 8'hfb; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4923 = _T_4662 ? btb_bank0_rd_data_way0_out_251 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5178 = _T_5177 | _T_4923; // @[Mux.scala 27:72] - wire _T_4664 = btb_rd_addr_p1_f == 8'hfc; // @[ifu_bp_ctl.scala 421:83] + wire _T_4664 = btb_rd_addr_p1_f == 8'hfc; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4924 = _T_4664 ? btb_bank0_rd_data_way0_out_252 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5179 = _T_5178 | _T_4924; // @[Mux.scala 27:72] - wire _T_4666 = btb_rd_addr_p1_f == 8'hfd; // @[ifu_bp_ctl.scala 421:83] + wire _T_4666 = btb_rd_addr_p1_f == 8'hfd; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4925 = _T_4666 ? btb_bank0_rd_data_way0_out_253 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5180 = _T_5179 | _T_4925; // @[Mux.scala 27:72] - wire _T_4668 = btb_rd_addr_p1_f == 8'hfe; // @[ifu_bp_ctl.scala 421:83] + wire _T_4668 = btb_rd_addr_p1_f == 8'hfe; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4926 = _T_4668 ? btb_bank0_rd_data_way0_out_254 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5181 = _T_5180 | _T_4926; // @[Mux.scala 27:72] - wire _T_4670 = btb_rd_addr_p1_f == 8'hff; // @[ifu_bp_ctl.scala 421:83] + wire _T_4670 = btb_rd_addr_p1_f == 8'hff; // @[ifu_bp_ctl.scala 422:83] wire [21:0] _T_4927 = _T_4670 ? btb_bank0_rd_data_way0_out_255 : 22'h0; // @[Mux.scala 27:72] wire [21:0] btb_bank0_rd_data_way0_p1_f = _T_5181 | _T_4927; // @[Mux.scala 27:72] wire [4:0] _T_31 = _T_8[13:9] ^ _T_8[18:14]; // @[lib.scala 26:111] wire [4:0] fetch_rd_tag_p1_f = _T_31 ^ _T_8[23:19]; // @[lib.scala 26:111] - wire _T_64 = btb_bank0_rd_data_way0_p1_f[21:17] == fetch_rd_tag_p1_f; // @[ifu_bp_ctl.scala 134:106] - wire _T_65 = btb_bank0_rd_data_way0_p1_f[0] & _T_64; // @[ifu_bp_ctl.scala 134:61] - wire _T_20 = io_exu_bp_exu_i0_br_index_r == btb_rd_addr_p1_f; // @[ifu_bp_ctl.scala 102:75] - wire branch_error_collision_p1_f = dec_tlu_error_wb & _T_20; // @[ifu_bp_ctl.scala 102:54] - wire branch_error_bank_conflict_p1_f = branch_error_collision_p1_f & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 106:69] - wire _T_66 = dec_tlu_way_wb_f & branch_error_bank_conflict_p1_f; // @[ifu_bp_ctl.scala 135:24] - wire _T_67 = ~_T_66; // @[ifu_bp_ctl.scala 135:5] - wire _T_68 = _T_65 & _T_67; // @[ifu_bp_ctl.scala 134:129] - wire _T_69 = _T_68 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 135:59] - wire tag_match_way0_p1_f = _T_69 & _T; // @[ifu_bp_ctl.scala 135:80] - wire _T_100 = btb_bank0_rd_data_way0_p1_f[3] ^ btb_bank0_rd_data_way0_p1_f[4]; // @[ifu_bp_ctl.scala 147:100] - wire _T_101 = tag_match_way0_p1_f & _T_100; // @[ifu_bp_ctl.scala 147:62] - wire _T_105 = ~_T_100; // @[ifu_bp_ctl.scala 148:64] - wire _T_106 = tag_match_way0_p1_f & _T_105; // @[ifu_bp_ctl.scala 148:62] + wire _T_64 = btb_bank0_rd_data_way0_p1_f[21:17] == fetch_rd_tag_p1_f; // @[ifu_bp_ctl.scala 135:106] + wire _T_65 = btb_bank0_rd_data_way0_p1_f[0] & _T_64; // @[ifu_bp_ctl.scala 135:61] + wire _T_20 = io_exu_bp_exu_i0_br_index_r == btb_rd_addr_p1_f; // @[ifu_bp_ctl.scala 103:75] + wire branch_error_collision_p1_f = dec_tlu_error_wb & _T_20; // @[ifu_bp_ctl.scala 103:54] + wire branch_error_bank_conflict_p1_f = branch_error_collision_p1_f & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 107:69] + wire _T_66 = dec_tlu_way_wb_f & branch_error_bank_conflict_p1_f; // @[ifu_bp_ctl.scala 136:24] + wire _T_67 = ~_T_66; // @[ifu_bp_ctl.scala 136:5] + wire _T_68 = _T_65 & _T_67; // @[ifu_bp_ctl.scala 135:129] + wire _T_69 = _T_68 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 136:59] + wire tag_match_way0_p1_f = _T_69 & _T; // @[ifu_bp_ctl.scala 136:80] + wire _T_100 = btb_bank0_rd_data_way0_p1_f[3] ^ btb_bank0_rd_data_way0_p1_f[4]; // @[ifu_bp_ctl.scala 148:100] + wire _T_101 = tag_match_way0_p1_f & _T_100; // @[ifu_bp_ctl.scala 148:62] + wire _T_105 = ~_T_100; // @[ifu_bp_ctl.scala 149:64] + wire _T_106 = tag_match_way0_p1_f & _T_105; // @[ifu_bp_ctl.scala 149:62] wire [1:0] tag_match_way0_expanded_p1_f = {_T_101,_T_106}; // @[Cat.scala 29:58] wire [21:0] _T_134 = tag_match_way0_expanded_p1_f[0] ? btb_bank0_rd_data_way0_p1_f : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_5696 = _T_4160 ? btb_bank0_rd_data_way1_out_0 : 22'h0; // @[Mux.scala 27:72] @@ -18300,2098 +18300,2098 @@ module ifu_bp_ctl( wire [21:0] _T_6205 = _T_6204 | _T_5950; // @[Mux.scala 27:72] wire [21:0] _T_5951 = _T_4670 ? btb_bank0_rd_data_way1_out_255 : 22'h0; // @[Mux.scala 27:72] wire [21:0] btb_bank0_rd_data_way1_p1_f = _T_6205 | _T_5951; // @[Mux.scala 27:72] - wire _T_73 = btb_bank0_rd_data_way1_p1_f[21:17] == fetch_rd_tag_p1_f; // @[ifu_bp_ctl.scala 137:106] - wire _T_74 = btb_bank0_rd_data_way1_p1_f[0] & _T_73; // @[ifu_bp_ctl.scala 137:61] - wire _T_77 = _T_74 & _T_67; // @[ifu_bp_ctl.scala 137:129] - wire _T_78 = _T_77 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 138:59] - wire tag_match_way1_p1_f = _T_78 & _T; // @[ifu_bp_ctl.scala 138:80] - wire _T_109 = btb_bank0_rd_data_way1_p1_f[3] ^ btb_bank0_rd_data_way1_p1_f[4]; // @[ifu_bp_ctl.scala 150:100] - wire _T_110 = tag_match_way1_p1_f & _T_109; // @[ifu_bp_ctl.scala 150:62] - wire _T_114 = ~_T_109; // @[ifu_bp_ctl.scala 151:64] - wire _T_115 = tag_match_way1_p1_f & _T_114; // @[ifu_bp_ctl.scala 151:62] + wire _T_73 = btb_bank0_rd_data_way1_p1_f[21:17] == fetch_rd_tag_p1_f; // @[ifu_bp_ctl.scala 138:106] + wire _T_74 = btb_bank0_rd_data_way1_p1_f[0] & _T_73; // @[ifu_bp_ctl.scala 138:61] + wire _T_77 = _T_74 & _T_67; // @[ifu_bp_ctl.scala 138:129] + wire _T_78 = _T_77 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 139:59] + wire tag_match_way1_p1_f = _T_78 & _T; // @[ifu_bp_ctl.scala 139:80] + wire _T_109 = btb_bank0_rd_data_way1_p1_f[3] ^ btb_bank0_rd_data_way1_p1_f[4]; // @[ifu_bp_ctl.scala 151:100] + wire _T_110 = tag_match_way1_p1_f & _T_109; // @[ifu_bp_ctl.scala 151:62] + wire _T_114 = ~_T_109; // @[ifu_bp_ctl.scala 152:64] + wire _T_115 = tag_match_way1_p1_f & _T_114; // @[ifu_bp_ctl.scala 152:62] wire [1:0] tag_match_way1_expanded_p1_f = {_T_110,_T_115}; // @[Cat.scala 29:58] wire [21:0] _T_135 = tag_match_way1_expanded_p1_f[0] ? btb_bank0_rd_data_way1_p1_f : 22'h0; // @[Mux.scala 27:72] wire [21:0] btb_bank0e_rd_data_p1_f = _T_134 | _T_135; // @[Mux.scala 27:72] wire [21:0] _T_147 = io_ifc_fetch_addr_f[0] ? btb_bank0e_rd_data_p1_f : 22'h0; // @[Mux.scala 27:72] wire [21:0] btb_vbank1_rd_data_f = _T_146 | _T_147; // @[Mux.scala 27:72] - wire _T_243 = btb_vbank1_rd_data_f[2] | btb_vbank1_rd_data_f[1]; // @[ifu_bp_ctl.scala 263:59] + wire _T_243 = btb_vbank1_rd_data_f[2] | btb_vbank1_rd_data_f[1]; // @[ifu_bp_ctl.scala 264:59] wire [21:0] _T_120 = tag_match_way0_expanded_f[0] ? btb_bank0_rd_data_way0_f : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_121 = tag_match_way1_expanded_f[0] ? btb_bank0_rd_data_way1_f : 22'h0; // @[Mux.scala 27:72] wire [21:0] btb_bank0e_rd_data_f = _T_120 | _T_121; // @[Mux.scala 27:72] wire [21:0] _T_140 = _T_144 ? btb_bank0e_rd_data_f : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_141 = io_ifc_fetch_addr_f[0] ? btb_bank0o_rd_data_f : 22'h0; // @[Mux.scala 27:72] wire [21:0] btb_vbank0_rd_data_f = _T_140 | _T_141; // @[Mux.scala 27:72] - wire _T_246 = btb_vbank0_rd_data_f[2] | btb_vbank0_rd_data_f[1]; // @[ifu_bp_ctl.scala 264:59] + wire _T_246 = btb_vbank0_rd_data_f[2] | btb_vbank0_rd_data_f[1]; // @[ifu_bp_ctl.scala 265:59] wire [1:0] bht_force_taken_f = {_T_243,_T_246}; // @[Cat.scala 29:58] wire [9:0] _T_570 = {btb_rd_addr_f,2'h0}; // @[Cat.scala 29:58] - reg [7:0] fghr; // @[ifu_bp_ctl.scala 322:44] + reg [7:0] fghr; // @[ifu_bp_ctl.scala 323:44] wire [7:0] bht_rd_addr_f = _T_570[9:2] ^ fghr; // @[lib.scala 40:35] - wire _T_21408 = bht_rd_addr_f == 8'h0; // @[ifu_bp_ctl.scala 454:79] + wire _T_21408 = bht_rd_addr_f == 8'h0; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_0; // @[Reg.scala 27:20] wire [1:0] _T_21920 = _T_21408 ? bht_bank_rd_data_out_1_0 : 2'h0; // @[Mux.scala 27:72] - wire _T_21410 = bht_rd_addr_f == 8'h1; // @[ifu_bp_ctl.scala 454:79] + wire _T_21410 = bht_rd_addr_f == 8'h1; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_1; // @[Reg.scala 27:20] wire [1:0] _T_21921 = _T_21410 ? bht_bank_rd_data_out_1_1 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22176 = _T_21920 | _T_21921; // @[Mux.scala 27:72] - wire _T_21412 = bht_rd_addr_f == 8'h2; // @[ifu_bp_ctl.scala 454:79] + wire _T_21412 = bht_rd_addr_f == 8'h2; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_2; // @[Reg.scala 27:20] wire [1:0] _T_21922 = _T_21412 ? bht_bank_rd_data_out_1_2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22177 = _T_22176 | _T_21922; // @[Mux.scala 27:72] - wire _T_21414 = bht_rd_addr_f == 8'h3; // @[ifu_bp_ctl.scala 454:79] + wire _T_21414 = bht_rd_addr_f == 8'h3; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_3; // @[Reg.scala 27:20] wire [1:0] _T_21923 = _T_21414 ? bht_bank_rd_data_out_1_3 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22178 = _T_22177 | _T_21923; // @[Mux.scala 27:72] - wire _T_21416 = bht_rd_addr_f == 8'h4; // @[ifu_bp_ctl.scala 454:79] + wire _T_21416 = bht_rd_addr_f == 8'h4; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_4; // @[Reg.scala 27:20] wire [1:0] _T_21924 = _T_21416 ? bht_bank_rd_data_out_1_4 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22179 = _T_22178 | _T_21924; // @[Mux.scala 27:72] - wire _T_21418 = bht_rd_addr_f == 8'h5; // @[ifu_bp_ctl.scala 454:79] + wire _T_21418 = bht_rd_addr_f == 8'h5; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_5; // @[Reg.scala 27:20] wire [1:0] _T_21925 = _T_21418 ? bht_bank_rd_data_out_1_5 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22180 = _T_22179 | _T_21925; // @[Mux.scala 27:72] - wire _T_21420 = bht_rd_addr_f == 8'h6; // @[ifu_bp_ctl.scala 454:79] + wire _T_21420 = bht_rd_addr_f == 8'h6; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_6; // @[Reg.scala 27:20] wire [1:0] _T_21926 = _T_21420 ? bht_bank_rd_data_out_1_6 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22181 = _T_22180 | _T_21926; // @[Mux.scala 27:72] - wire _T_21422 = bht_rd_addr_f == 8'h7; // @[ifu_bp_ctl.scala 454:79] + wire _T_21422 = bht_rd_addr_f == 8'h7; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_7; // @[Reg.scala 27:20] wire [1:0] _T_21927 = _T_21422 ? bht_bank_rd_data_out_1_7 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22182 = _T_22181 | _T_21927; // @[Mux.scala 27:72] - wire _T_21424 = bht_rd_addr_f == 8'h8; // @[ifu_bp_ctl.scala 454:79] + wire _T_21424 = bht_rd_addr_f == 8'h8; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_8; // @[Reg.scala 27:20] wire [1:0] _T_21928 = _T_21424 ? bht_bank_rd_data_out_1_8 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22183 = _T_22182 | _T_21928; // @[Mux.scala 27:72] - wire _T_21426 = bht_rd_addr_f == 8'h9; // @[ifu_bp_ctl.scala 454:79] + wire _T_21426 = bht_rd_addr_f == 8'h9; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_9; // @[Reg.scala 27:20] wire [1:0] _T_21929 = _T_21426 ? bht_bank_rd_data_out_1_9 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22184 = _T_22183 | _T_21929; // @[Mux.scala 27:72] - wire _T_21428 = bht_rd_addr_f == 8'ha; // @[ifu_bp_ctl.scala 454:79] + wire _T_21428 = bht_rd_addr_f == 8'ha; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_10; // @[Reg.scala 27:20] wire [1:0] _T_21930 = _T_21428 ? bht_bank_rd_data_out_1_10 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22185 = _T_22184 | _T_21930; // @[Mux.scala 27:72] - wire _T_21430 = bht_rd_addr_f == 8'hb; // @[ifu_bp_ctl.scala 454:79] + wire _T_21430 = bht_rd_addr_f == 8'hb; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_11; // @[Reg.scala 27:20] wire [1:0] _T_21931 = _T_21430 ? bht_bank_rd_data_out_1_11 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22186 = _T_22185 | _T_21931; // @[Mux.scala 27:72] - wire _T_21432 = bht_rd_addr_f == 8'hc; // @[ifu_bp_ctl.scala 454:79] + wire _T_21432 = bht_rd_addr_f == 8'hc; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_12; // @[Reg.scala 27:20] wire [1:0] _T_21932 = _T_21432 ? bht_bank_rd_data_out_1_12 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22187 = _T_22186 | _T_21932; // @[Mux.scala 27:72] - wire _T_21434 = bht_rd_addr_f == 8'hd; // @[ifu_bp_ctl.scala 454:79] + wire _T_21434 = bht_rd_addr_f == 8'hd; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_13; // @[Reg.scala 27:20] wire [1:0] _T_21933 = _T_21434 ? bht_bank_rd_data_out_1_13 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22188 = _T_22187 | _T_21933; // @[Mux.scala 27:72] - wire _T_21436 = bht_rd_addr_f == 8'he; // @[ifu_bp_ctl.scala 454:79] + wire _T_21436 = bht_rd_addr_f == 8'he; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_14; // @[Reg.scala 27:20] wire [1:0] _T_21934 = _T_21436 ? bht_bank_rd_data_out_1_14 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22189 = _T_22188 | _T_21934; // @[Mux.scala 27:72] - wire _T_21438 = bht_rd_addr_f == 8'hf; // @[ifu_bp_ctl.scala 454:79] + wire _T_21438 = bht_rd_addr_f == 8'hf; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_15; // @[Reg.scala 27:20] wire [1:0] _T_21935 = _T_21438 ? bht_bank_rd_data_out_1_15 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22190 = _T_22189 | _T_21935; // @[Mux.scala 27:72] - wire _T_21440 = bht_rd_addr_f == 8'h10; // @[ifu_bp_ctl.scala 454:79] + wire _T_21440 = bht_rd_addr_f == 8'h10; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_16; // @[Reg.scala 27:20] wire [1:0] _T_21936 = _T_21440 ? bht_bank_rd_data_out_1_16 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22191 = _T_22190 | _T_21936; // @[Mux.scala 27:72] - wire _T_21442 = bht_rd_addr_f == 8'h11; // @[ifu_bp_ctl.scala 454:79] + wire _T_21442 = bht_rd_addr_f == 8'h11; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_17; // @[Reg.scala 27:20] wire [1:0] _T_21937 = _T_21442 ? bht_bank_rd_data_out_1_17 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22192 = _T_22191 | _T_21937; // @[Mux.scala 27:72] - wire _T_21444 = bht_rd_addr_f == 8'h12; // @[ifu_bp_ctl.scala 454:79] + wire _T_21444 = bht_rd_addr_f == 8'h12; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_18; // @[Reg.scala 27:20] wire [1:0] _T_21938 = _T_21444 ? bht_bank_rd_data_out_1_18 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22193 = _T_22192 | _T_21938; // @[Mux.scala 27:72] - wire _T_21446 = bht_rd_addr_f == 8'h13; // @[ifu_bp_ctl.scala 454:79] + wire _T_21446 = bht_rd_addr_f == 8'h13; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_19; // @[Reg.scala 27:20] wire [1:0] _T_21939 = _T_21446 ? bht_bank_rd_data_out_1_19 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22194 = _T_22193 | _T_21939; // @[Mux.scala 27:72] - wire _T_21448 = bht_rd_addr_f == 8'h14; // @[ifu_bp_ctl.scala 454:79] + wire _T_21448 = bht_rd_addr_f == 8'h14; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_20; // @[Reg.scala 27:20] wire [1:0] _T_21940 = _T_21448 ? bht_bank_rd_data_out_1_20 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22195 = _T_22194 | _T_21940; // @[Mux.scala 27:72] - wire _T_21450 = bht_rd_addr_f == 8'h15; // @[ifu_bp_ctl.scala 454:79] + wire _T_21450 = bht_rd_addr_f == 8'h15; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_21; // @[Reg.scala 27:20] wire [1:0] _T_21941 = _T_21450 ? bht_bank_rd_data_out_1_21 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22196 = _T_22195 | _T_21941; // @[Mux.scala 27:72] - wire _T_21452 = bht_rd_addr_f == 8'h16; // @[ifu_bp_ctl.scala 454:79] + wire _T_21452 = bht_rd_addr_f == 8'h16; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_22; // @[Reg.scala 27:20] wire [1:0] _T_21942 = _T_21452 ? bht_bank_rd_data_out_1_22 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22197 = _T_22196 | _T_21942; // @[Mux.scala 27:72] - wire _T_21454 = bht_rd_addr_f == 8'h17; // @[ifu_bp_ctl.scala 454:79] + wire _T_21454 = bht_rd_addr_f == 8'h17; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_23; // @[Reg.scala 27:20] wire [1:0] _T_21943 = _T_21454 ? bht_bank_rd_data_out_1_23 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22198 = _T_22197 | _T_21943; // @[Mux.scala 27:72] - wire _T_21456 = bht_rd_addr_f == 8'h18; // @[ifu_bp_ctl.scala 454:79] + wire _T_21456 = bht_rd_addr_f == 8'h18; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_24; // @[Reg.scala 27:20] wire [1:0] _T_21944 = _T_21456 ? bht_bank_rd_data_out_1_24 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22199 = _T_22198 | _T_21944; // @[Mux.scala 27:72] - wire _T_21458 = bht_rd_addr_f == 8'h19; // @[ifu_bp_ctl.scala 454:79] + wire _T_21458 = bht_rd_addr_f == 8'h19; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_25; // @[Reg.scala 27:20] wire [1:0] _T_21945 = _T_21458 ? bht_bank_rd_data_out_1_25 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22200 = _T_22199 | _T_21945; // @[Mux.scala 27:72] - wire _T_21460 = bht_rd_addr_f == 8'h1a; // @[ifu_bp_ctl.scala 454:79] + wire _T_21460 = bht_rd_addr_f == 8'h1a; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_26; // @[Reg.scala 27:20] wire [1:0] _T_21946 = _T_21460 ? bht_bank_rd_data_out_1_26 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22201 = _T_22200 | _T_21946; // @[Mux.scala 27:72] - wire _T_21462 = bht_rd_addr_f == 8'h1b; // @[ifu_bp_ctl.scala 454:79] + wire _T_21462 = bht_rd_addr_f == 8'h1b; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_27; // @[Reg.scala 27:20] wire [1:0] _T_21947 = _T_21462 ? bht_bank_rd_data_out_1_27 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22202 = _T_22201 | _T_21947; // @[Mux.scala 27:72] - wire _T_21464 = bht_rd_addr_f == 8'h1c; // @[ifu_bp_ctl.scala 454:79] + wire _T_21464 = bht_rd_addr_f == 8'h1c; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_28; // @[Reg.scala 27:20] wire [1:0] _T_21948 = _T_21464 ? bht_bank_rd_data_out_1_28 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22203 = _T_22202 | _T_21948; // @[Mux.scala 27:72] - wire _T_21466 = bht_rd_addr_f == 8'h1d; // @[ifu_bp_ctl.scala 454:79] + wire _T_21466 = bht_rd_addr_f == 8'h1d; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_29; // @[Reg.scala 27:20] wire [1:0] _T_21949 = _T_21466 ? bht_bank_rd_data_out_1_29 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22204 = _T_22203 | _T_21949; // @[Mux.scala 27:72] - wire _T_21468 = bht_rd_addr_f == 8'h1e; // @[ifu_bp_ctl.scala 454:79] + wire _T_21468 = bht_rd_addr_f == 8'h1e; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_30; // @[Reg.scala 27:20] wire [1:0] _T_21950 = _T_21468 ? bht_bank_rd_data_out_1_30 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22205 = _T_22204 | _T_21950; // @[Mux.scala 27:72] - wire _T_21470 = bht_rd_addr_f == 8'h1f; // @[ifu_bp_ctl.scala 454:79] + wire _T_21470 = bht_rd_addr_f == 8'h1f; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_31; // @[Reg.scala 27:20] wire [1:0] _T_21951 = _T_21470 ? bht_bank_rd_data_out_1_31 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22206 = _T_22205 | _T_21951; // @[Mux.scala 27:72] - wire _T_21472 = bht_rd_addr_f == 8'h20; // @[ifu_bp_ctl.scala 454:79] + wire _T_21472 = bht_rd_addr_f == 8'h20; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_32; // @[Reg.scala 27:20] wire [1:0] _T_21952 = _T_21472 ? bht_bank_rd_data_out_1_32 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22207 = _T_22206 | _T_21952; // @[Mux.scala 27:72] - wire _T_21474 = bht_rd_addr_f == 8'h21; // @[ifu_bp_ctl.scala 454:79] + wire _T_21474 = bht_rd_addr_f == 8'h21; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_33; // @[Reg.scala 27:20] wire [1:0] _T_21953 = _T_21474 ? bht_bank_rd_data_out_1_33 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22208 = _T_22207 | _T_21953; // @[Mux.scala 27:72] - wire _T_21476 = bht_rd_addr_f == 8'h22; // @[ifu_bp_ctl.scala 454:79] + wire _T_21476 = bht_rd_addr_f == 8'h22; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_34; // @[Reg.scala 27:20] wire [1:0] _T_21954 = _T_21476 ? bht_bank_rd_data_out_1_34 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22209 = _T_22208 | _T_21954; // @[Mux.scala 27:72] - wire _T_21478 = bht_rd_addr_f == 8'h23; // @[ifu_bp_ctl.scala 454:79] + wire _T_21478 = bht_rd_addr_f == 8'h23; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_35; // @[Reg.scala 27:20] wire [1:0] _T_21955 = _T_21478 ? bht_bank_rd_data_out_1_35 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22210 = _T_22209 | _T_21955; // @[Mux.scala 27:72] - wire _T_21480 = bht_rd_addr_f == 8'h24; // @[ifu_bp_ctl.scala 454:79] + wire _T_21480 = bht_rd_addr_f == 8'h24; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_36; // @[Reg.scala 27:20] wire [1:0] _T_21956 = _T_21480 ? bht_bank_rd_data_out_1_36 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22211 = _T_22210 | _T_21956; // @[Mux.scala 27:72] - wire _T_21482 = bht_rd_addr_f == 8'h25; // @[ifu_bp_ctl.scala 454:79] + wire _T_21482 = bht_rd_addr_f == 8'h25; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_37; // @[Reg.scala 27:20] wire [1:0] _T_21957 = _T_21482 ? bht_bank_rd_data_out_1_37 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22212 = _T_22211 | _T_21957; // @[Mux.scala 27:72] - wire _T_21484 = bht_rd_addr_f == 8'h26; // @[ifu_bp_ctl.scala 454:79] + wire _T_21484 = bht_rd_addr_f == 8'h26; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_38; // @[Reg.scala 27:20] wire [1:0] _T_21958 = _T_21484 ? bht_bank_rd_data_out_1_38 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22213 = _T_22212 | _T_21958; // @[Mux.scala 27:72] - wire _T_21486 = bht_rd_addr_f == 8'h27; // @[ifu_bp_ctl.scala 454:79] + wire _T_21486 = bht_rd_addr_f == 8'h27; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_39; // @[Reg.scala 27:20] wire [1:0] _T_21959 = _T_21486 ? bht_bank_rd_data_out_1_39 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22214 = _T_22213 | _T_21959; // @[Mux.scala 27:72] - wire _T_21488 = bht_rd_addr_f == 8'h28; // @[ifu_bp_ctl.scala 454:79] + wire _T_21488 = bht_rd_addr_f == 8'h28; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_40; // @[Reg.scala 27:20] wire [1:0] _T_21960 = _T_21488 ? bht_bank_rd_data_out_1_40 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22215 = _T_22214 | _T_21960; // @[Mux.scala 27:72] - wire _T_21490 = bht_rd_addr_f == 8'h29; // @[ifu_bp_ctl.scala 454:79] + wire _T_21490 = bht_rd_addr_f == 8'h29; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_41; // @[Reg.scala 27:20] wire [1:0] _T_21961 = _T_21490 ? bht_bank_rd_data_out_1_41 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22216 = _T_22215 | _T_21961; // @[Mux.scala 27:72] - wire _T_21492 = bht_rd_addr_f == 8'h2a; // @[ifu_bp_ctl.scala 454:79] + wire _T_21492 = bht_rd_addr_f == 8'h2a; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_42; // @[Reg.scala 27:20] wire [1:0] _T_21962 = _T_21492 ? bht_bank_rd_data_out_1_42 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22217 = _T_22216 | _T_21962; // @[Mux.scala 27:72] - wire _T_21494 = bht_rd_addr_f == 8'h2b; // @[ifu_bp_ctl.scala 454:79] + wire _T_21494 = bht_rd_addr_f == 8'h2b; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_43; // @[Reg.scala 27:20] wire [1:0] _T_21963 = _T_21494 ? bht_bank_rd_data_out_1_43 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22218 = _T_22217 | _T_21963; // @[Mux.scala 27:72] - wire _T_21496 = bht_rd_addr_f == 8'h2c; // @[ifu_bp_ctl.scala 454:79] + wire _T_21496 = bht_rd_addr_f == 8'h2c; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_44; // @[Reg.scala 27:20] wire [1:0] _T_21964 = _T_21496 ? bht_bank_rd_data_out_1_44 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22219 = _T_22218 | _T_21964; // @[Mux.scala 27:72] - wire _T_21498 = bht_rd_addr_f == 8'h2d; // @[ifu_bp_ctl.scala 454:79] + wire _T_21498 = bht_rd_addr_f == 8'h2d; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_45; // @[Reg.scala 27:20] wire [1:0] _T_21965 = _T_21498 ? bht_bank_rd_data_out_1_45 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22220 = _T_22219 | _T_21965; // @[Mux.scala 27:72] - wire _T_21500 = bht_rd_addr_f == 8'h2e; // @[ifu_bp_ctl.scala 454:79] + wire _T_21500 = bht_rd_addr_f == 8'h2e; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_46; // @[Reg.scala 27:20] wire [1:0] _T_21966 = _T_21500 ? bht_bank_rd_data_out_1_46 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22221 = _T_22220 | _T_21966; // @[Mux.scala 27:72] - wire _T_21502 = bht_rd_addr_f == 8'h2f; // @[ifu_bp_ctl.scala 454:79] + wire _T_21502 = bht_rd_addr_f == 8'h2f; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_47; // @[Reg.scala 27:20] wire [1:0] _T_21967 = _T_21502 ? bht_bank_rd_data_out_1_47 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22222 = _T_22221 | _T_21967; // @[Mux.scala 27:72] - wire _T_21504 = bht_rd_addr_f == 8'h30; // @[ifu_bp_ctl.scala 454:79] + wire _T_21504 = bht_rd_addr_f == 8'h30; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_48; // @[Reg.scala 27:20] wire [1:0] _T_21968 = _T_21504 ? bht_bank_rd_data_out_1_48 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22223 = _T_22222 | _T_21968; // @[Mux.scala 27:72] - wire _T_21506 = bht_rd_addr_f == 8'h31; // @[ifu_bp_ctl.scala 454:79] + wire _T_21506 = bht_rd_addr_f == 8'h31; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_49; // @[Reg.scala 27:20] wire [1:0] _T_21969 = _T_21506 ? bht_bank_rd_data_out_1_49 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22224 = _T_22223 | _T_21969; // @[Mux.scala 27:72] - wire _T_21508 = bht_rd_addr_f == 8'h32; // @[ifu_bp_ctl.scala 454:79] + wire _T_21508 = bht_rd_addr_f == 8'h32; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_50; // @[Reg.scala 27:20] wire [1:0] _T_21970 = _T_21508 ? bht_bank_rd_data_out_1_50 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22225 = _T_22224 | _T_21970; // @[Mux.scala 27:72] - wire _T_21510 = bht_rd_addr_f == 8'h33; // @[ifu_bp_ctl.scala 454:79] + wire _T_21510 = bht_rd_addr_f == 8'h33; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_51; // @[Reg.scala 27:20] wire [1:0] _T_21971 = _T_21510 ? bht_bank_rd_data_out_1_51 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22226 = _T_22225 | _T_21971; // @[Mux.scala 27:72] - wire _T_21512 = bht_rd_addr_f == 8'h34; // @[ifu_bp_ctl.scala 454:79] + wire _T_21512 = bht_rd_addr_f == 8'h34; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_52; // @[Reg.scala 27:20] wire [1:0] _T_21972 = _T_21512 ? bht_bank_rd_data_out_1_52 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22227 = _T_22226 | _T_21972; // @[Mux.scala 27:72] - wire _T_21514 = bht_rd_addr_f == 8'h35; // @[ifu_bp_ctl.scala 454:79] + wire _T_21514 = bht_rd_addr_f == 8'h35; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_53; // @[Reg.scala 27:20] wire [1:0] _T_21973 = _T_21514 ? bht_bank_rd_data_out_1_53 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22228 = _T_22227 | _T_21973; // @[Mux.scala 27:72] - wire _T_21516 = bht_rd_addr_f == 8'h36; // @[ifu_bp_ctl.scala 454:79] + wire _T_21516 = bht_rd_addr_f == 8'h36; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_54; // @[Reg.scala 27:20] wire [1:0] _T_21974 = _T_21516 ? bht_bank_rd_data_out_1_54 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22229 = _T_22228 | _T_21974; // @[Mux.scala 27:72] - wire _T_21518 = bht_rd_addr_f == 8'h37; // @[ifu_bp_ctl.scala 454:79] + wire _T_21518 = bht_rd_addr_f == 8'h37; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_55; // @[Reg.scala 27:20] wire [1:0] _T_21975 = _T_21518 ? bht_bank_rd_data_out_1_55 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22230 = _T_22229 | _T_21975; // @[Mux.scala 27:72] - wire _T_21520 = bht_rd_addr_f == 8'h38; // @[ifu_bp_ctl.scala 454:79] + wire _T_21520 = bht_rd_addr_f == 8'h38; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_56; // @[Reg.scala 27:20] wire [1:0] _T_21976 = _T_21520 ? bht_bank_rd_data_out_1_56 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22231 = _T_22230 | _T_21976; // @[Mux.scala 27:72] - wire _T_21522 = bht_rd_addr_f == 8'h39; // @[ifu_bp_ctl.scala 454:79] + wire _T_21522 = bht_rd_addr_f == 8'h39; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_57; // @[Reg.scala 27:20] wire [1:0] _T_21977 = _T_21522 ? bht_bank_rd_data_out_1_57 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22232 = _T_22231 | _T_21977; // @[Mux.scala 27:72] - wire _T_21524 = bht_rd_addr_f == 8'h3a; // @[ifu_bp_ctl.scala 454:79] + wire _T_21524 = bht_rd_addr_f == 8'h3a; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_58; // @[Reg.scala 27:20] wire [1:0] _T_21978 = _T_21524 ? bht_bank_rd_data_out_1_58 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22233 = _T_22232 | _T_21978; // @[Mux.scala 27:72] - wire _T_21526 = bht_rd_addr_f == 8'h3b; // @[ifu_bp_ctl.scala 454:79] + wire _T_21526 = bht_rd_addr_f == 8'h3b; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_59; // @[Reg.scala 27:20] wire [1:0] _T_21979 = _T_21526 ? bht_bank_rd_data_out_1_59 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22234 = _T_22233 | _T_21979; // @[Mux.scala 27:72] - wire _T_21528 = bht_rd_addr_f == 8'h3c; // @[ifu_bp_ctl.scala 454:79] + wire _T_21528 = bht_rd_addr_f == 8'h3c; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_60; // @[Reg.scala 27:20] wire [1:0] _T_21980 = _T_21528 ? bht_bank_rd_data_out_1_60 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22235 = _T_22234 | _T_21980; // @[Mux.scala 27:72] - wire _T_21530 = bht_rd_addr_f == 8'h3d; // @[ifu_bp_ctl.scala 454:79] + wire _T_21530 = bht_rd_addr_f == 8'h3d; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_61; // @[Reg.scala 27:20] wire [1:0] _T_21981 = _T_21530 ? bht_bank_rd_data_out_1_61 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22236 = _T_22235 | _T_21981; // @[Mux.scala 27:72] - wire _T_21532 = bht_rd_addr_f == 8'h3e; // @[ifu_bp_ctl.scala 454:79] + wire _T_21532 = bht_rd_addr_f == 8'h3e; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_62; // @[Reg.scala 27:20] wire [1:0] _T_21982 = _T_21532 ? bht_bank_rd_data_out_1_62 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22237 = _T_22236 | _T_21982; // @[Mux.scala 27:72] - wire _T_21534 = bht_rd_addr_f == 8'h3f; // @[ifu_bp_ctl.scala 454:79] + wire _T_21534 = bht_rd_addr_f == 8'h3f; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_63; // @[Reg.scala 27:20] wire [1:0] _T_21983 = _T_21534 ? bht_bank_rd_data_out_1_63 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22238 = _T_22237 | _T_21983; // @[Mux.scala 27:72] - wire _T_21536 = bht_rd_addr_f == 8'h40; // @[ifu_bp_ctl.scala 454:79] + wire _T_21536 = bht_rd_addr_f == 8'h40; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_64; // @[Reg.scala 27:20] wire [1:0] _T_21984 = _T_21536 ? bht_bank_rd_data_out_1_64 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22239 = _T_22238 | _T_21984; // @[Mux.scala 27:72] - wire _T_21538 = bht_rd_addr_f == 8'h41; // @[ifu_bp_ctl.scala 454:79] + wire _T_21538 = bht_rd_addr_f == 8'h41; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_65; // @[Reg.scala 27:20] wire [1:0] _T_21985 = _T_21538 ? bht_bank_rd_data_out_1_65 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22240 = _T_22239 | _T_21985; // @[Mux.scala 27:72] - wire _T_21540 = bht_rd_addr_f == 8'h42; // @[ifu_bp_ctl.scala 454:79] + wire _T_21540 = bht_rd_addr_f == 8'h42; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_66; // @[Reg.scala 27:20] wire [1:0] _T_21986 = _T_21540 ? bht_bank_rd_data_out_1_66 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22241 = _T_22240 | _T_21986; // @[Mux.scala 27:72] - wire _T_21542 = bht_rd_addr_f == 8'h43; // @[ifu_bp_ctl.scala 454:79] + wire _T_21542 = bht_rd_addr_f == 8'h43; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_67; // @[Reg.scala 27:20] wire [1:0] _T_21987 = _T_21542 ? bht_bank_rd_data_out_1_67 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22242 = _T_22241 | _T_21987; // @[Mux.scala 27:72] - wire _T_21544 = bht_rd_addr_f == 8'h44; // @[ifu_bp_ctl.scala 454:79] + wire _T_21544 = bht_rd_addr_f == 8'h44; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_68; // @[Reg.scala 27:20] wire [1:0] _T_21988 = _T_21544 ? bht_bank_rd_data_out_1_68 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22243 = _T_22242 | _T_21988; // @[Mux.scala 27:72] - wire _T_21546 = bht_rd_addr_f == 8'h45; // @[ifu_bp_ctl.scala 454:79] + wire _T_21546 = bht_rd_addr_f == 8'h45; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_69; // @[Reg.scala 27:20] wire [1:0] _T_21989 = _T_21546 ? bht_bank_rd_data_out_1_69 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22244 = _T_22243 | _T_21989; // @[Mux.scala 27:72] - wire _T_21548 = bht_rd_addr_f == 8'h46; // @[ifu_bp_ctl.scala 454:79] + wire _T_21548 = bht_rd_addr_f == 8'h46; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_70; // @[Reg.scala 27:20] wire [1:0] _T_21990 = _T_21548 ? bht_bank_rd_data_out_1_70 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22245 = _T_22244 | _T_21990; // @[Mux.scala 27:72] - wire _T_21550 = bht_rd_addr_f == 8'h47; // @[ifu_bp_ctl.scala 454:79] + wire _T_21550 = bht_rd_addr_f == 8'h47; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_71; // @[Reg.scala 27:20] wire [1:0] _T_21991 = _T_21550 ? bht_bank_rd_data_out_1_71 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22246 = _T_22245 | _T_21991; // @[Mux.scala 27:72] - wire _T_21552 = bht_rd_addr_f == 8'h48; // @[ifu_bp_ctl.scala 454:79] + wire _T_21552 = bht_rd_addr_f == 8'h48; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_72; // @[Reg.scala 27:20] wire [1:0] _T_21992 = _T_21552 ? bht_bank_rd_data_out_1_72 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22247 = _T_22246 | _T_21992; // @[Mux.scala 27:72] - wire _T_21554 = bht_rd_addr_f == 8'h49; // @[ifu_bp_ctl.scala 454:79] + wire _T_21554 = bht_rd_addr_f == 8'h49; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_73; // @[Reg.scala 27:20] wire [1:0] _T_21993 = _T_21554 ? bht_bank_rd_data_out_1_73 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22248 = _T_22247 | _T_21993; // @[Mux.scala 27:72] - wire _T_21556 = bht_rd_addr_f == 8'h4a; // @[ifu_bp_ctl.scala 454:79] + wire _T_21556 = bht_rd_addr_f == 8'h4a; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_74; // @[Reg.scala 27:20] wire [1:0] _T_21994 = _T_21556 ? bht_bank_rd_data_out_1_74 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22249 = _T_22248 | _T_21994; // @[Mux.scala 27:72] - wire _T_21558 = bht_rd_addr_f == 8'h4b; // @[ifu_bp_ctl.scala 454:79] + wire _T_21558 = bht_rd_addr_f == 8'h4b; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_75; // @[Reg.scala 27:20] wire [1:0] _T_21995 = _T_21558 ? bht_bank_rd_data_out_1_75 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22250 = _T_22249 | _T_21995; // @[Mux.scala 27:72] - wire _T_21560 = bht_rd_addr_f == 8'h4c; // @[ifu_bp_ctl.scala 454:79] + wire _T_21560 = bht_rd_addr_f == 8'h4c; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_76; // @[Reg.scala 27:20] wire [1:0] _T_21996 = _T_21560 ? bht_bank_rd_data_out_1_76 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22251 = _T_22250 | _T_21996; // @[Mux.scala 27:72] - wire _T_21562 = bht_rd_addr_f == 8'h4d; // @[ifu_bp_ctl.scala 454:79] + wire _T_21562 = bht_rd_addr_f == 8'h4d; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_77; // @[Reg.scala 27:20] wire [1:0] _T_21997 = _T_21562 ? bht_bank_rd_data_out_1_77 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22252 = _T_22251 | _T_21997; // @[Mux.scala 27:72] - wire _T_21564 = bht_rd_addr_f == 8'h4e; // @[ifu_bp_ctl.scala 454:79] + wire _T_21564 = bht_rd_addr_f == 8'h4e; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_78; // @[Reg.scala 27:20] wire [1:0] _T_21998 = _T_21564 ? bht_bank_rd_data_out_1_78 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22253 = _T_22252 | _T_21998; // @[Mux.scala 27:72] - wire _T_21566 = bht_rd_addr_f == 8'h4f; // @[ifu_bp_ctl.scala 454:79] + wire _T_21566 = bht_rd_addr_f == 8'h4f; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_79; // @[Reg.scala 27:20] wire [1:0] _T_21999 = _T_21566 ? bht_bank_rd_data_out_1_79 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22254 = _T_22253 | _T_21999; // @[Mux.scala 27:72] - wire _T_21568 = bht_rd_addr_f == 8'h50; // @[ifu_bp_ctl.scala 454:79] + wire _T_21568 = bht_rd_addr_f == 8'h50; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_80; // @[Reg.scala 27:20] wire [1:0] _T_22000 = _T_21568 ? bht_bank_rd_data_out_1_80 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22255 = _T_22254 | _T_22000; // @[Mux.scala 27:72] - wire _T_21570 = bht_rd_addr_f == 8'h51; // @[ifu_bp_ctl.scala 454:79] + wire _T_21570 = bht_rd_addr_f == 8'h51; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_81; // @[Reg.scala 27:20] wire [1:0] _T_22001 = _T_21570 ? bht_bank_rd_data_out_1_81 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22256 = _T_22255 | _T_22001; // @[Mux.scala 27:72] - wire _T_21572 = bht_rd_addr_f == 8'h52; // @[ifu_bp_ctl.scala 454:79] + wire _T_21572 = bht_rd_addr_f == 8'h52; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_82; // @[Reg.scala 27:20] wire [1:0] _T_22002 = _T_21572 ? bht_bank_rd_data_out_1_82 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22257 = _T_22256 | _T_22002; // @[Mux.scala 27:72] - wire _T_21574 = bht_rd_addr_f == 8'h53; // @[ifu_bp_ctl.scala 454:79] + wire _T_21574 = bht_rd_addr_f == 8'h53; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_83; // @[Reg.scala 27:20] wire [1:0] _T_22003 = _T_21574 ? bht_bank_rd_data_out_1_83 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22258 = _T_22257 | _T_22003; // @[Mux.scala 27:72] - wire _T_21576 = bht_rd_addr_f == 8'h54; // @[ifu_bp_ctl.scala 454:79] + wire _T_21576 = bht_rd_addr_f == 8'h54; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_84; // @[Reg.scala 27:20] wire [1:0] _T_22004 = _T_21576 ? bht_bank_rd_data_out_1_84 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22259 = _T_22258 | _T_22004; // @[Mux.scala 27:72] - wire _T_21578 = bht_rd_addr_f == 8'h55; // @[ifu_bp_ctl.scala 454:79] + wire _T_21578 = bht_rd_addr_f == 8'h55; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_85; // @[Reg.scala 27:20] wire [1:0] _T_22005 = _T_21578 ? bht_bank_rd_data_out_1_85 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22260 = _T_22259 | _T_22005; // @[Mux.scala 27:72] - wire _T_21580 = bht_rd_addr_f == 8'h56; // @[ifu_bp_ctl.scala 454:79] + wire _T_21580 = bht_rd_addr_f == 8'h56; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_86; // @[Reg.scala 27:20] wire [1:0] _T_22006 = _T_21580 ? bht_bank_rd_data_out_1_86 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22261 = _T_22260 | _T_22006; // @[Mux.scala 27:72] - wire _T_21582 = bht_rd_addr_f == 8'h57; // @[ifu_bp_ctl.scala 454:79] + wire _T_21582 = bht_rd_addr_f == 8'h57; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_87; // @[Reg.scala 27:20] wire [1:0] _T_22007 = _T_21582 ? bht_bank_rd_data_out_1_87 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22262 = _T_22261 | _T_22007; // @[Mux.scala 27:72] - wire _T_21584 = bht_rd_addr_f == 8'h58; // @[ifu_bp_ctl.scala 454:79] + wire _T_21584 = bht_rd_addr_f == 8'h58; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_88; // @[Reg.scala 27:20] wire [1:0] _T_22008 = _T_21584 ? bht_bank_rd_data_out_1_88 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22263 = _T_22262 | _T_22008; // @[Mux.scala 27:72] - wire _T_21586 = bht_rd_addr_f == 8'h59; // @[ifu_bp_ctl.scala 454:79] + wire _T_21586 = bht_rd_addr_f == 8'h59; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_89; // @[Reg.scala 27:20] wire [1:0] _T_22009 = _T_21586 ? bht_bank_rd_data_out_1_89 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22264 = _T_22263 | _T_22009; // @[Mux.scala 27:72] - wire _T_21588 = bht_rd_addr_f == 8'h5a; // @[ifu_bp_ctl.scala 454:79] + wire _T_21588 = bht_rd_addr_f == 8'h5a; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_90; // @[Reg.scala 27:20] wire [1:0] _T_22010 = _T_21588 ? bht_bank_rd_data_out_1_90 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22265 = _T_22264 | _T_22010; // @[Mux.scala 27:72] - wire _T_21590 = bht_rd_addr_f == 8'h5b; // @[ifu_bp_ctl.scala 454:79] + wire _T_21590 = bht_rd_addr_f == 8'h5b; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_91; // @[Reg.scala 27:20] wire [1:0] _T_22011 = _T_21590 ? bht_bank_rd_data_out_1_91 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22266 = _T_22265 | _T_22011; // @[Mux.scala 27:72] - wire _T_21592 = bht_rd_addr_f == 8'h5c; // @[ifu_bp_ctl.scala 454:79] + wire _T_21592 = bht_rd_addr_f == 8'h5c; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_92; // @[Reg.scala 27:20] wire [1:0] _T_22012 = _T_21592 ? bht_bank_rd_data_out_1_92 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22267 = _T_22266 | _T_22012; // @[Mux.scala 27:72] - wire _T_21594 = bht_rd_addr_f == 8'h5d; // @[ifu_bp_ctl.scala 454:79] + wire _T_21594 = bht_rd_addr_f == 8'h5d; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_93; // @[Reg.scala 27:20] wire [1:0] _T_22013 = _T_21594 ? bht_bank_rd_data_out_1_93 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22268 = _T_22267 | _T_22013; // @[Mux.scala 27:72] - wire _T_21596 = bht_rd_addr_f == 8'h5e; // @[ifu_bp_ctl.scala 454:79] + wire _T_21596 = bht_rd_addr_f == 8'h5e; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_94; // @[Reg.scala 27:20] wire [1:0] _T_22014 = _T_21596 ? bht_bank_rd_data_out_1_94 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22269 = _T_22268 | _T_22014; // @[Mux.scala 27:72] - wire _T_21598 = bht_rd_addr_f == 8'h5f; // @[ifu_bp_ctl.scala 454:79] + wire _T_21598 = bht_rd_addr_f == 8'h5f; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_95; // @[Reg.scala 27:20] wire [1:0] _T_22015 = _T_21598 ? bht_bank_rd_data_out_1_95 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22270 = _T_22269 | _T_22015; // @[Mux.scala 27:72] - wire _T_21600 = bht_rd_addr_f == 8'h60; // @[ifu_bp_ctl.scala 454:79] + wire _T_21600 = bht_rd_addr_f == 8'h60; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_96; // @[Reg.scala 27:20] wire [1:0] _T_22016 = _T_21600 ? bht_bank_rd_data_out_1_96 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22271 = _T_22270 | _T_22016; // @[Mux.scala 27:72] - wire _T_21602 = bht_rd_addr_f == 8'h61; // @[ifu_bp_ctl.scala 454:79] + wire _T_21602 = bht_rd_addr_f == 8'h61; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_97; // @[Reg.scala 27:20] wire [1:0] _T_22017 = _T_21602 ? bht_bank_rd_data_out_1_97 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22272 = _T_22271 | _T_22017; // @[Mux.scala 27:72] - wire _T_21604 = bht_rd_addr_f == 8'h62; // @[ifu_bp_ctl.scala 454:79] + wire _T_21604 = bht_rd_addr_f == 8'h62; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_98; // @[Reg.scala 27:20] wire [1:0] _T_22018 = _T_21604 ? bht_bank_rd_data_out_1_98 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22273 = _T_22272 | _T_22018; // @[Mux.scala 27:72] - wire _T_21606 = bht_rd_addr_f == 8'h63; // @[ifu_bp_ctl.scala 454:79] + wire _T_21606 = bht_rd_addr_f == 8'h63; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_99; // @[Reg.scala 27:20] wire [1:0] _T_22019 = _T_21606 ? bht_bank_rd_data_out_1_99 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22274 = _T_22273 | _T_22019; // @[Mux.scala 27:72] - wire _T_21608 = bht_rd_addr_f == 8'h64; // @[ifu_bp_ctl.scala 454:79] + wire _T_21608 = bht_rd_addr_f == 8'h64; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_100; // @[Reg.scala 27:20] wire [1:0] _T_22020 = _T_21608 ? bht_bank_rd_data_out_1_100 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22275 = _T_22274 | _T_22020; // @[Mux.scala 27:72] - wire _T_21610 = bht_rd_addr_f == 8'h65; // @[ifu_bp_ctl.scala 454:79] + wire _T_21610 = bht_rd_addr_f == 8'h65; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_101; // @[Reg.scala 27:20] wire [1:0] _T_22021 = _T_21610 ? bht_bank_rd_data_out_1_101 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22276 = _T_22275 | _T_22021; // @[Mux.scala 27:72] - wire _T_21612 = bht_rd_addr_f == 8'h66; // @[ifu_bp_ctl.scala 454:79] + wire _T_21612 = bht_rd_addr_f == 8'h66; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_102; // @[Reg.scala 27:20] wire [1:0] _T_22022 = _T_21612 ? bht_bank_rd_data_out_1_102 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22277 = _T_22276 | _T_22022; // @[Mux.scala 27:72] - wire _T_21614 = bht_rd_addr_f == 8'h67; // @[ifu_bp_ctl.scala 454:79] + wire _T_21614 = bht_rd_addr_f == 8'h67; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_103; // @[Reg.scala 27:20] wire [1:0] _T_22023 = _T_21614 ? bht_bank_rd_data_out_1_103 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22278 = _T_22277 | _T_22023; // @[Mux.scala 27:72] - wire _T_21616 = bht_rd_addr_f == 8'h68; // @[ifu_bp_ctl.scala 454:79] + wire _T_21616 = bht_rd_addr_f == 8'h68; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_104; // @[Reg.scala 27:20] wire [1:0] _T_22024 = _T_21616 ? bht_bank_rd_data_out_1_104 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22279 = _T_22278 | _T_22024; // @[Mux.scala 27:72] - wire _T_21618 = bht_rd_addr_f == 8'h69; // @[ifu_bp_ctl.scala 454:79] + wire _T_21618 = bht_rd_addr_f == 8'h69; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_105; // @[Reg.scala 27:20] wire [1:0] _T_22025 = _T_21618 ? bht_bank_rd_data_out_1_105 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22280 = _T_22279 | _T_22025; // @[Mux.scala 27:72] - wire _T_21620 = bht_rd_addr_f == 8'h6a; // @[ifu_bp_ctl.scala 454:79] + wire _T_21620 = bht_rd_addr_f == 8'h6a; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_106; // @[Reg.scala 27:20] wire [1:0] _T_22026 = _T_21620 ? bht_bank_rd_data_out_1_106 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22281 = _T_22280 | _T_22026; // @[Mux.scala 27:72] - wire _T_21622 = bht_rd_addr_f == 8'h6b; // @[ifu_bp_ctl.scala 454:79] + wire _T_21622 = bht_rd_addr_f == 8'h6b; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_107; // @[Reg.scala 27:20] wire [1:0] _T_22027 = _T_21622 ? bht_bank_rd_data_out_1_107 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22282 = _T_22281 | _T_22027; // @[Mux.scala 27:72] - wire _T_21624 = bht_rd_addr_f == 8'h6c; // @[ifu_bp_ctl.scala 454:79] + wire _T_21624 = bht_rd_addr_f == 8'h6c; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_108; // @[Reg.scala 27:20] wire [1:0] _T_22028 = _T_21624 ? bht_bank_rd_data_out_1_108 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22283 = _T_22282 | _T_22028; // @[Mux.scala 27:72] - wire _T_21626 = bht_rd_addr_f == 8'h6d; // @[ifu_bp_ctl.scala 454:79] + wire _T_21626 = bht_rd_addr_f == 8'h6d; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_109; // @[Reg.scala 27:20] wire [1:0] _T_22029 = _T_21626 ? bht_bank_rd_data_out_1_109 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22284 = _T_22283 | _T_22029; // @[Mux.scala 27:72] - wire _T_21628 = bht_rd_addr_f == 8'h6e; // @[ifu_bp_ctl.scala 454:79] + wire _T_21628 = bht_rd_addr_f == 8'h6e; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_110; // @[Reg.scala 27:20] wire [1:0] _T_22030 = _T_21628 ? bht_bank_rd_data_out_1_110 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22285 = _T_22284 | _T_22030; // @[Mux.scala 27:72] - wire _T_21630 = bht_rd_addr_f == 8'h6f; // @[ifu_bp_ctl.scala 454:79] + wire _T_21630 = bht_rd_addr_f == 8'h6f; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_111; // @[Reg.scala 27:20] wire [1:0] _T_22031 = _T_21630 ? bht_bank_rd_data_out_1_111 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22286 = _T_22285 | _T_22031; // @[Mux.scala 27:72] - wire _T_21632 = bht_rd_addr_f == 8'h70; // @[ifu_bp_ctl.scala 454:79] + wire _T_21632 = bht_rd_addr_f == 8'h70; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_112; // @[Reg.scala 27:20] wire [1:0] _T_22032 = _T_21632 ? bht_bank_rd_data_out_1_112 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22287 = _T_22286 | _T_22032; // @[Mux.scala 27:72] - wire _T_21634 = bht_rd_addr_f == 8'h71; // @[ifu_bp_ctl.scala 454:79] + wire _T_21634 = bht_rd_addr_f == 8'h71; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_113; // @[Reg.scala 27:20] wire [1:0] _T_22033 = _T_21634 ? bht_bank_rd_data_out_1_113 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22288 = _T_22287 | _T_22033; // @[Mux.scala 27:72] - wire _T_21636 = bht_rd_addr_f == 8'h72; // @[ifu_bp_ctl.scala 454:79] + wire _T_21636 = bht_rd_addr_f == 8'h72; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_114; // @[Reg.scala 27:20] wire [1:0] _T_22034 = _T_21636 ? bht_bank_rd_data_out_1_114 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22289 = _T_22288 | _T_22034; // @[Mux.scala 27:72] - wire _T_21638 = bht_rd_addr_f == 8'h73; // @[ifu_bp_ctl.scala 454:79] + wire _T_21638 = bht_rd_addr_f == 8'h73; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_115; // @[Reg.scala 27:20] wire [1:0] _T_22035 = _T_21638 ? bht_bank_rd_data_out_1_115 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22290 = _T_22289 | _T_22035; // @[Mux.scala 27:72] - wire _T_21640 = bht_rd_addr_f == 8'h74; // @[ifu_bp_ctl.scala 454:79] + wire _T_21640 = bht_rd_addr_f == 8'h74; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_116; // @[Reg.scala 27:20] wire [1:0] _T_22036 = _T_21640 ? bht_bank_rd_data_out_1_116 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22291 = _T_22290 | _T_22036; // @[Mux.scala 27:72] - wire _T_21642 = bht_rd_addr_f == 8'h75; // @[ifu_bp_ctl.scala 454:79] + wire _T_21642 = bht_rd_addr_f == 8'h75; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_117; // @[Reg.scala 27:20] wire [1:0] _T_22037 = _T_21642 ? bht_bank_rd_data_out_1_117 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22292 = _T_22291 | _T_22037; // @[Mux.scala 27:72] - wire _T_21644 = bht_rd_addr_f == 8'h76; // @[ifu_bp_ctl.scala 454:79] + wire _T_21644 = bht_rd_addr_f == 8'h76; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_118; // @[Reg.scala 27:20] wire [1:0] _T_22038 = _T_21644 ? bht_bank_rd_data_out_1_118 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22293 = _T_22292 | _T_22038; // @[Mux.scala 27:72] - wire _T_21646 = bht_rd_addr_f == 8'h77; // @[ifu_bp_ctl.scala 454:79] + wire _T_21646 = bht_rd_addr_f == 8'h77; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_119; // @[Reg.scala 27:20] wire [1:0] _T_22039 = _T_21646 ? bht_bank_rd_data_out_1_119 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22294 = _T_22293 | _T_22039; // @[Mux.scala 27:72] - wire _T_21648 = bht_rd_addr_f == 8'h78; // @[ifu_bp_ctl.scala 454:79] + wire _T_21648 = bht_rd_addr_f == 8'h78; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_120; // @[Reg.scala 27:20] wire [1:0] _T_22040 = _T_21648 ? bht_bank_rd_data_out_1_120 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22295 = _T_22294 | _T_22040; // @[Mux.scala 27:72] - wire _T_21650 = bht_rd_addr_f == 8'h79; // @[ifu_bp_ctl.scala 454:79] + wire _T_21650 = bht_rd_addr_f == 8'h79; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_121; // @[Reg.scala 27:20] wire [1:0] _T_22041 = _T_21650 ? bht_bank_rd_data_out_1_121 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22296 = _T_22295 | _T_22041; // @[Mux.scala 27:72] - wire _T_21652 = bht_rd_addr_f == 8'h7a; // @[ifu_bp_ctl.scala 454:79] + wire _T_21652 = bht_rd_addr_f == 8'h7a; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_122; // @[Reg.scala 27:20] wire [1:0] _T_22042 = _T_21652 ? bht_bank_rd_data_out_1_122 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22297 = _T_22296 | _T_22042; // @[Mux.scala 27:72] - wire _T_21654 = bht_rd_addr_f == 8'h7b; // @[ifu_bp_ctl.scala 454:79] + wire _T_21654 = bht_rd_addr_f == 8'h7b; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_123; // @[Reg.scala 27:20] wire [1:0] _T_22043 = _T_21654 ? bht_bank_rd_data_out_1_123 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22298 = _T_22297 | _T_22043; // @[Mux.scala 27:72] - wire _T_21656 = bht_rd_addr_f == 8'h7c; // @[ifu_bp_ctl.scala 454:79] + wire _T_21656 = bht_rd_addr_f == 8'h7c; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_124; // @[Reg.scala 27:20] wire [1:0] _T_22044 = _T_21656 ? bht_bank_rd_data_out_1_124 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22299 = _T_22298 | _T_22044; // @[Mux.scala 27:72] - wire _T_21658 = bht_rd_addr_f == 8'h7d; // @[ifu_bp_ctl.scala 454:79] + wire _T_21658 = bht_rd_addr_f == 8'h7d; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_125; // @[Reg.scala 27:20] wire [1:0] _T_22045 = _T_21658 ? bht_bank_rd_data_out_1_125 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22300 = _T_22299 | _T_22045; // @[Mux.scala 27:72] - wire _T_21660 = bht_rd_addr_f == 8'h7e; // @[ifu_bp_ctl.scala 454:79] + wire _T_21660 = bht_rd_addr_f == 8'h7e; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_126; // @[Reg.scala 27:20] wire [1:0] _T_22046 = _T_21660 ? bht_bank_rd_data_out_1_126 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22301 = _T_22300 | _T_22046; // @[Mux.scala 27:72] - wire _T_21662 = bht_rd_addr_f == 8'h7f; // @[ifu_bp_ctl.scala 454:79] + wire _T_21662 = bht_rd_addr_f == 8'h7f; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_127; // @[Reg.scala 27:20] wire [1:0] _T_22047 = _T_21662 ? bht_bank_rd_data_out_1_127 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22302 = _T_22301 | _T_22047; // @[Mux.scala 27:72] - wire _T_21664 = bht_rd_addr_f == 8'h80; // @[ifu_bp_ctl.scala 454:79] + wire _T_21664 = bht_rd_addr_f == 8'h80; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_128; // @[Reg.scala 27:20] wire [1:0] _T_22048 = _T_21664 ? bht_bank_rd_data_out_1_128 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22303 = _T_22302 | _T_22048; // @[Mux.scala 27:72] - wire _T_21666 = bht_rd_addr_f == 8'h81; // @[ifu_bp_ctl.scala 454:79] + wire _T_21666 = bht_rd_addr_f == 8'h81; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_129; // @[Reg.scala 27:20] wire [1:0] _T_22049 = _T_21666 ? bht_bank_rd_data_out_1_129 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22304 = _T_22303 | _T_22049; // @[Mux.scala 27:72] - wire _T_21668 = bht_rd_addr_f == 8'h82; // @[ifu_bp_ctl.scala 454:79] + wire _T_21668 = bht_rd_addr_f == 8'h82; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_130; // @[Reg.scala 27:20] wire [1:0] _T_22050 = _T_21668 ? bht_bank_rd_data_out_1_130 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22305 = _T_22304 | _T_22050; // @[Mux.scala 27:72] - wire _T_21670 = bht_rd_addr_f == 8'h83; // @[ifu_bp_ctl.scala 454:79] + wire _T_21670 = bht_rd_addr_f == 8'h83; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_131; // @[Reg.scala 27:20] wire [1:0] _T_22051 = _T_21670 ? bht_bank_rd_data_out_1_131 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22306 = _T_22305 | _T_22051; // @[Mux.scala 27:72] - wire _T_21672 = bht_rd_addr_f == 8'h84; // @[ifu_bp_ctl.scala 454:79] + wire _T_21672 = bht_rd_addr_f == 8'h84; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_132; // @[Reg.scala 27:20] wire [1:0] _T_22052 = _T_21672 ? bht_bank_rd_data_out_1_132 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22307 = _T_22306 | _T_22052; // @[Mux.scala 27:72] - wire _T_21674 = bht_rd_addr_f == 8'h85; // @[ifu_bp_ctl.scala 454:79] + wire _T_21674 = bht_rd_addr_f == 8'h85; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_133; // @[Reg.scala 27:20] wire [1:0] _T_22053 = _T_21674 ? bht_bank_rd_data_out_1_133 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22308 = _T_22307 | _T_22053; // @[Mux.scala 27:72] - wire _T_21676 = bht_rd_addr_f == 8'h86; // @[ifu_bp_ctl.scala 454:79] + wire _T_21676 = bht_rd_addr_f == 8'h86; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_134; // @[Reg.scala 27:20] wire [1:0] _T_22054 = _T_21676 ? bht_bank_rd_data_out_1_134 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22309 = _T_22308 | _T_22054; // @[Mux.scala 27:72] - wire _T_21678 = bht_rd_addr_f == 8'h87; // @[ifu_bp_ctl.scala 454:79] + wire _T_21678 = bht_rd_addr_f == 8'h87; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_135; // @[Reg.scala 27:20] wire [1:0] _T_22055 = _T_21678 ? bht_bank_rd_data_out_1_135 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22310 = _T_22309 | _T_22055; // @[Mux.scala 27:72] - wire _T_21680 = bht_rd_addr_f == 8'h88; // @[ifu_bp_ctl.scala 454:79] + wire _T_21680 = bht_rd_addr_f == 8'h88; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_136; // @[Reg.scala 27:20] wire [1:0] _T_22056 = _T_21680 ? bht_bank_rd_data_out_1_136 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22311 = _T_22310 | _T_22056; // @[Mux.scala 27:72] - wire _T_21682 = bht_rd_addr_f == 8'h89; // @[ifu_bp_ctl.scala 454:79] + wire _T_21682 = bht_rd_addr_f == 8'h89; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_137; // @[Reg.scala 27:20] wire [1:0] _T_22057 = _T_21682 ? bht_bank_rd_data_out_1_137 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22312 = _T_22311 | _T_22057; // @[Mux.scala 27:72] - wire _T_21684 = bht_rd_addr_f == 8'h8a; // @[ifu_bp_ctl.scala 454:79] + wire _T_21684 = bht_rd_addr_f == 8'h8a; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_138; // @[Reg.scala 27:20] wire [1:0] _T_22058 = _T_21684 ? bht_bank_rd_data_out_1_138 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22313 = _T_22312 | _T_22058; // @[Mux.scala 27:72] - wire _T_21686 = bht_rd_addr_f == 8'h8b; // @[ifu_bp_ctl.scala 454:79] + wire _T_21686 = bht_rd_addr_f == 8'h8b; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_139; // @[Reg.scala 27:20] wire [1:0] _T_22059 = _T_21686 ? bht_bank_rd_data_out_1_139 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22314 = _T_22313 | _T_22059; // @[Mux.scala 27:72] - wire _T_21688 = bht_rd_addr_f == 8'h8c; // @[ifu_bp_ctl.scala 454:79] + wire _T_21688 = bht_rd_addr_f == 8'h8c; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_140; // @[Reg.scala 27:20] wire [1:0] _T_22060 = _T_21688 ? bht_bank_rd_data_out_1_140 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22315 = _T_22314 | _T_22060; // @[Mux.scala 27:72] - wire _T_21690 = bht_rd_addr_f == 8'h8d; // @[ifu_bp_ctl.scala 454:79] + wire _T_21690 = bht_rd_addr_f == 8'h8d; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_141; // @[Reg.scala 27:20] wire [1:0] _T_22061 = _T_21690 ? bht_bank_rd_data_out_1_141 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22316 = _T_22315 | _T_22061; // @[Mux.scala 27:72] - wire _T_21692 = bht_rd_addr_f == 8'h8e; // @[ifu_bp_ctl.scala 454:79] + wire _T_21692 = bht_rd_addr_f == 8'h8e; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_142; // @[Reg.scala 27:20] wire [1:0] _T_22062 = _T_21692 ? bht_bank_rd_data_out_1_142 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22317 = _T_22316 | _T_22062; // @[Mux.scala 27:72] - wire _T_21694 = bht_rd_addr_f == 8'h8f; // @[ifu_bp_ctl.scala 454:79] + wire _T_21694 = bht_rd_addr_f == 8'h8f; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_143; // @[Reg.scala 27:20] wire [1:0] _T_22063 = _T_21694 ? bht_bank_rd_data_out_1_143 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22318 = _T_22317 | _T_22063; // @[Mux.scala 27:72] - wire _T_21696 = bht_rd_addr_f == 8'h90; // @[ifu_bp_ctl.scala 454:79] + wire _T_21696 = bht_rd_addr_f == 8'h90; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_144; // @[Reg.scala 27:20] wire [1:0] _T_22064 = _T_21696 ? bht_bank_rd_data_out_1_144 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22319 = _T_22318 | _T_22064; // @[Mux.scala 27:72] - wire _T_21698 = bht_rd_addr_f == 8'h91; // @[ifu_bp_ctl.scala 454:79] + wire _T_21698 = bht_rd_addr_f == 8'h91; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_145; // @[Reg.scala 27:20] wire [1:0] _T_22065 = _T_21698 ? bht_bank_rd_data_out_1_145 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22320 = _T_22319 | _T_22065; // @[Mux.scala 27:72] - wire _T_21700 = bht_rd_addr_f == 8'h92; // @[ifu_bp_ctl.scala 454:79] + wire _T_21700 = bht_rd_addr_f == 8'h92; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_146; // @[Reg.scala 27:20] wire [1:0] _T_22066 = _T_21700 ? bht_bank_rd_data_out_1_146 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22321 = _T_22320 | _T_22066; // @[Mux.scala 27:72] - wire _T_21702 = bht_rd_addr_f == 8'h93; // @[ifu_bp_ctl.scala 454:79] + wire _T_21702 = bht_rd_addr_f == 8'h93; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_147; // @[Reg.scala 27:20] wire [1:0] _T_22067 = _T_21702 ? bht_bank_rd_data_out_1_147 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22322 = _T_22321 | _T_22067; // @[Mux.scala 27:72] - wire _T_21704 = bht_rd_addr_f == 8'h94; // @[ifu_bp_ctl.scala 454:79] + wire _T_21704 = bht_rd_addr_f == 8'h94; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_148; // @[Reg.scala 27:20] wire [1:0] _T_22068 = _T_21704 ? bht_bank_rd_data_out_1_148 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22323 = _T_22322 | _T_22068; // @[Mux.scala 27:72] - wire _T_21706 = bht_rd_addr_f == 8'h95; // @[ifu_bp_ctl.scala 454:79] + wire _T_21706 = bht_rd_addr_f == 8'h95; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_149; // @[Reg.scala 27:20] wire [1:0] _T_22069 = _T_21706 ? bht_bank_rd_data_out_1_149 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22324 = _T_22323 | _T_22069; // @[Mux.scala 27:72] - wire _T_21708 = bht_rd_addr_f == 8'h96; // @[ifu_bp_ctl.scala 454:79] + wire _T_21708 = bht_rd_addr_f == 8'h96; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_150; // @[Reg.scala 27:20] wire [1:0] _T_22070 = _T_21708 ? bht_bank_rd_data_out_1_150 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22325 = _T_22324 | _T_22070; // @[Mux.scala 27:72] - wire _T_21710 = bht_rd_addr_f == 8'h97; // @[ifu_bp_ctl.scala 454:79] + wire _T_21710 = bht_rd_addr_f == 8'h97; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_151; // @[Reg.scala 27:20] wire [1:0] _T_22071 = _T_21710 ? bht_bank_rd_data_out_1_151 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22326 = _T_22325 | _T_22071; // @[Mux.scala 27:72] - wire _T_21712 = bht_rd_addr_f == 8'h98; // @[ifu_bp_ctl.scala 454:79] + wire _T_21712 = bht_rd_addr_f == 8'h98; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_152; // @[Reg.scala 27:20] wire [1:0] _T_22072 = _T_21712 ? bht_bank_rd_data_out_1_152 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22327 = _T_22326 | _T_22072; // @[Mux.scala 27:72] - wire _T_21714 = bht_rd_addr_f == 8'h99; // @[ifu_bp_ctl.scala 454:79] + wire _T_21714 = bht_rd_addr_f == 8'h99; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_153; // @[Reg.scala 27:20] wire [1:0] _T_22073 = _T_21714 ? bht_bank_rd_data_out_1_153 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22328 = _T_22327 | _T_22073; // @[Mux.scala 27:72] - wire _T_21716 = bht_rd_addr_f == 8'h9a; // @[ifu_bp_ctl.scala 454:79] + wire _T_21716 = bht_rd_addr_f == 8'h9a; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_154; // @[Reg.scala 27:20] wire [1:0] _T_22074 = _T_21716 ? bht_bank_rd_data_out_1_154 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22329 = _T_22328 | _T_22074; // @[Mux.scala 27:72] - wire _T_21718 = bht_rd_addr_f == 8'h9b; // @[ifu_bp_ctl.scala 454:79] + wire _T_21718 = bht_rd_addr_f == 8'h9b; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_155; // @[Reg.scala 27:20] wire [1:0] _T_22075 = _T_21718 ? bht_bank_rd_data_out_1_155 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22330 = _T_22329 | _T_22075; // @[Mux.scala 27:72] - wire _T_21720 = bht_rd_addr_f == 8'h9c; // @[ifu_bp_ctl.scala 454:79] + wire _T_21720 = bht_rd_addr_f == 8'h9c; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_156; // @[Reg.scala 27:20] wire [1:0] _T_22076 = _T_21720 ? bht_bank_rd_data_out_1_156 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22331 = _T_22330 | _T_22076; // @[Mux.scala 27:72] - wire _T_21722 = bht_rd_addr_f == 8'h9d; // @[ifu_bp_ctl.scala 454:79] + wire _T_21722 = bht_rd_addr_f == 8'h9d; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_157; // @[Reg.scala 27:20] wire [1:0] _T_22077 = _T_21722 ? bht_bank_rd_data_out_1_157 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22332 = _T_22331 | _T_22077; // @[Mux.scala 27:72] - wire _T_21724 = bht_rd_addr_f == 8'h9e; // @[ifu_bp_ctl.scala 454:79] + wire _T_21724 = bht_rd_addr_f == 8'h9e; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_158; // @[Reg.scala 27:20] wire [1:0] _T_22078 = _T_21724 ? bht_bank_rd_data_out_1_158 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22333 = _T_22332 | _T_22078; // @[Mux.scala 27:72] - wire _T_21726 = bht_rd_addr_f == 8'h9f; // @[ifu_bp_ctl.scala 454:79] + wire _T_21726 = bht_rd_addr_f == 8'h9f; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_159; // @[Reg.scala 27:20] wire [1:0] _T_22079 = _T_21726 ? bht_bank_rd_data_out_1_159 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22334 = _T_22333 | _T_22079; // @[Mux.scala 27:72] - wire _T_21728 = bht_rd_addr_f == 8'ha0; // @[ifu_bp_ctl.scala 454:79] + wire _T_21728 = bht_rd_addr_f == 8'ha0; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_160; // @[Reg.scala 27:20] wire [1:0] _T_22080 = _T_21728 ? bht_bank_rd_data_out_1_160 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22335 = _T_22334 | _T_22080; // @[Mux.scala 27:72] - wire _T_21730 = bht_rd_addr_f == 8'ha1; // @[ifu_bp_ctl.scala 454:79] + wire _T_21730 = bht_rd_addr_f == 8'ha1; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_161; // @[Reg.scala 27:20] wire [1:0] _T_22081 = _T_21730 ? bht_bank_rd_data_out_1_161 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22336 = _T_22335 | _T_22081; // @[Mux.scala 27:72] - wire _T_21732 = bht_rd_addr_f == 8'ha2; // @[ifu_bp_ctl.scala 454:79] + wire _T_21732 = bht_rd_addr_f == 8'ha2; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_162; // @[Reg.scala 27:20] wire [1:0] _T_22082 = _T_21732 ? bht_bank_rd_data_out_1_162 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22337 = _T_22336 | _T_22082; // @[Mux.scala 27:72] - wire _T_21734 = bht_rd_addr_f == 8'ha3; // @[ifu_bp_ctl.scala 454:79] + wire _T_21734 = bht_rd_addr_f == 8'ha3; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_163; // @[Reg.scala 27:20] wire [1:0] _T_22083 = _T_21734 ? bht_bank_rd_data_out_1_163 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22338 = _T_22337 | _T_22083; // @[Mux.scala 27:72] - wire _T_21736 = bht_rd_addr_f == 8'ha4; // @[ifu_bp_ctl.scala 454:79] + wire _T_21736 = bht_rd_addr_f == 8'ha4; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_164; // @[Reg.scala 27:20] wire [1:0] _T_22084 = _T_21736 ? bht_bank_rd_data_out_1_164 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22339 = _T_22338 | _T_22084; // @[Mux.scala 27:72] - wire _T_21738 = bht_rd_addr_f == 8'ha5; // @[ifu_bp_ctl.scala 454:79] + wire _T_21738 = bht_rd_addr_f == 8'ha5; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_165; // @[Reg.scala 27:20] wire [1:0] _T_22085 = _T_21738 ? bht_bank_rd_data_out_1_165 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22340 = _T_22339 | _T_22085; // @[Mux.scala 27:72] - wire _T_21740 = bht_rd_addr_f == 8'ha6; // @[ifu_bp_ctl.scala 454:79] + wire _T_21740 = bht_rd_addr_f == 8'ha6; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_166; // @[Reg.scala 27:20] wire [1:0] _T_22086 = _T_21740 ? bht_bank_rd_data_out_1_166 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22341 = _T_22340 | _T_22086; // @[Mux.scala 27:72] - wire _T_21742 = bht_rd_addr_f == 8'ha7; // @[ifu_bp_ctl.scala 454:79] + wire _T_21742 = bht_rd_addr_f == 8'ha7; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_167; // @[Reg.scala 27:20] wire [1:0] _T_22087 = _T_21742 ? bht_bank_rd_data_out_1_167 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22342 = _T_22341 | _T_22087; // @[Mux.scala 27:72] - wire _T_21744 = bht_rd_addr_f == 8'ha8; // @[ifu_bp_ctl.scala 454:79] + wire _T_21744 = bht_rd_addr_f == 8'ha8; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_168; // @[Reg.scala 27:20] wire [1:0] _T_22088 = _T_21744 ? bht_bank_rd_data_out_1_168 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22343 = _T_22342 | _T_22088; // @[Mux.scala 27:72] - wire _T_21746 = bht_rd_addr_f == 8'ha9; // @[ifu_bp_ctl.scala 454:79] + wire _T_21746 = bht_rd_addr_f == 8'ha9; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_169; // @[Reg.scala 27:20] wire [1:0] _T_22089 = _T_21746 ? bht_bank_rd_data_out_1_169 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22344 = _T_22343 | _T_22089; // @[Mux.scala 27:72] - wire _T_21748 = bht_rd_addr_f == 8'haa; // @[ifu_bp_ctl.scala 454:79] + wire _T_21748 = bht_rd_addr_f == 8'haa; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_170; // @[Reg.scala 27:20] wire [1:0] _T_22090 = _T_21748 ? bht_bank_rd_data_out_1_170 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22345 = _T_22344 | _T_22090; // @[Mux.scala 27:72] - wire _T_21750 = bht_rd_addr_f == 8'hab; // @[ifu_bp_ctl.scala 454:79] + wire _T_21750 = bht_rd_addr_f == 8'hab; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_171; // @[Reg.scala 27:20] wire [1:0] _T_22091 = _T_21750 ? bht_bank_rd_data_out_1_171 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22346 = _T_22345 | _T_22091; // @[Mux.scala 27:72] - wire _T_21752 = bht_rd_addr_f == 8'hac; // @[ifu_bp_ctl.scala 454:79] + wire _T_21752 = bht_rd_addr_f == 8'hac; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_172; // @[Reg.scala 27:20] wire [1:0] _T_22092 = _T_21752 ? bht_bank_rd_data_out_1_172 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22347 = _T_22346 | _T_22092; // @[Mux.scala 27:72] - wire _T_21754 = bht_rd_addr_f == 8'had; // @[ifu_bp_ctl.scala 454:79] + wire _T_21754 = bht_rd_addr_f == 8'had; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_173; // @[Reg.scala 27:20] wire [1:0] _T_22093 = _T_21754 ? bht_bank_rd_data_out_1_173 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22348 = _T_22347 | _T_22093; // @[Mux.scala 27:72] - wire _T_21756 = bht_rd_addr_f == 8'hae; // @[ifu_bp_ctl.scala 454:79] + wire _T_21756 = bht_rd_addr_f == 8'hae; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_174; // @[Reg.scala 27:20] wire [1:0] _T_22094 = _T_21756 ? bht_bank_rd_data_out_1_174 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22349 = _T_22348 | _T_22094; // @[Mux.scala 27:72] - wire _T_21758 = bht_rd_addr_f == 8'haf; // @[ifu_bp_ctl.scala 454:79] + wire _T_21758 = bht_rd_addr_f == 8'haf; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_175; // @[Reg.scala 27:20] wire [1:0] _T_22095 = _T_21758 ? bht_bank_rd_data_out_1_175 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22350 = _T_22349 | _T_22095; // @[Mux.scala 27:72] - wire _T_21760 = bht_rd_addr_f == 8'hb0; // @[ifu_bp_ctl.scala 454:79] + wire _T_21760 = bht_rd_addr_f == 8'hb0; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_176; // @[Reg.scala 27:20] wire [1:0] _T_22096 = _T_21760 ? bht_bank_rd_data_out_1_176 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22351 = _T_22350 | _T_22096; // @[Mux.scala 27:72] - wire _T_21762 = bht_rd_addr_f == 8'hb1; // @[ifu_bp_ctl.scala 454:79] + wire _T_21762 = bht_rd_addr_f == 8'hb1; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_177; // @[Reg.scala 27:20] wire [1:0] _T_22097 = _T_21762 ? bht_bank_rd_data_out_1_177 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22352 = _T_22351 | _T_22097; // @[Mux.scala 27:72] - wire _T_21764 = bht_rd_addr_f == 8'hb2; // @[ifu_bp_ctl.scala 454:79] + wire _T_21764 = bht_rd_addr_f == 8'hb2; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_178; // @[Reg.scala 27:20] wire [1:0] _T_22098 = _T_21764 ? bht_bank_rd_data_out_1_178 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22353 = _T_22352 | _T_22098; // @[Mux.scala 27:72] - wire _T_21766 = bht_rd_addr_f == 8'hb3; // @[ifu_bp_ctl.scala 454:79] + wire _T_21766 = bht_rd_addr_f == 8'hb3; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_179; // @[Reg.scala 27:20] wire [1:0] _T_22099 = _T_21766 ? bht_bank_rd_data_out_1_179 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22354 = _T_22353 | _T_22099; // @[Mux.scala 27:72] - wire _T_21768 = bht_rd_addr_f == 8'hb4; // @[ifu_bp_ctl.scala 454:79] + wire _T_21768 = bht_rd_addr_f == 8'hb4; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_180; // @[Reg.scala 27:20] wire [1:0] _T_22100 = _T_21768 ? bht_bank_rd_data_out_1_180 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22355 = _T_22354 | _T_22100; // @[Mux.scala 27:72] - wire _T_21770 = bht_rd_addr_f == 8'hb5; // @[ifu_bp_ctl.scala 454:79] + wire _T_21770 = bht_rd_addr_f == 8'hb5; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_181; // @[Reg.scala 27:20] wire [1:0] _T_22101 = _T_21770 ? bht_bank_rd_data_out_1_181 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22356 = _T_22355 | _T_22101; // @[Mux.scala 27:72] - wire _T_21772 = bht_rd_addr_f == 8'hb6; // @[ifu_bp_ctl.scala 454:79] + wire _T_21772 = bht_rd_addr_f == 8'hb6; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_182; // @[Reg.scala 27:20] wire [1:0] _T_22102 = _T_21772 ? bht_bank_rd_data_out_1_182 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22357 = _T_22356 | _T_22102; // @[Mux.scala 27:72] - wire _T_21774 = bht_rd_addr_f == 8'hb7; // @[ifu_bp_ctl.scala 454:79] + wire _T_21774 = bht_rd_addr_f == 8'hb7; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_183; // @[Reg.scala 27:20] wire [1:0] _T_22103 = _T_21774 ? bht_bank_rd_data_out_1_183 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22358 = _T_22357 | _T_22103; // @[Mux.scala 27:72] - wire _T_21776 = bht_rd_addr_f == 8'hb8; // @[ifu_bp_ctl.scala 454:79] + wire _T_21776 = bht_rd_addr_f == 8'hb8; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_184; // @[Reg.scala 27:20] wire [1:0] _T_22104 = _T_21776 ? bht_bank_rd_data_out_1_184 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22359 = _T_22358 | _T_22104; // @[Mux.scala 27:72] - wire _T_21778 = bht_rd_addr_f == 8'hb9; // @[ifu_bp_ctl.scala 454:79] + wire _T_21778 = bht_rd_addr_f == 8'hb9; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_185; // @[Reg.scala 27:20] wire [1:0] _T_22105 = _T_21778 ? bht_bank_rd_data_out_1_185 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22360 = _T_22359 | _T_22105; // @[Mux.scala 27:72] - wire _T_21780 = bht_rd_addr_f == 8'hba; // @[ifu_bp_ctl.scala 454:79] + wire _T_21780 = bht_rd_addr_f == 8'hba; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_186; // @[Reg.scala 27:20] wire [1:0] _T_22106 = _T_21780 ? bht_bank_rd_data_out_1_186 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22361 = _T_22360 | _T_22106; // @[Mux.scala 27:72] - wire _T_21782 = bht_rd_addr_f == 8'hbb; // @[ifu_bp_ctl.scala 454:79] + wire _T_21782 = bht_rd_addr_f == 8'hbb; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_187; // @[Reg.scala 27:20] wire [1:0] _T_22107 = _T_21782 ? bht_bank_rd_data_out_1_187 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22362 = _T_22361 | _T_22107; // @[Mux.scala 27:72] - wire _T_21784 = bht_rd_addr_f == 8'hbc; // @[ifu_bp_ctl.scala 454:79] + wire _T_21784 = bht_rd_addr_f == 8'hbc; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_188; // @[Reg.scala 27:20] wire [1:0] _T_22108 = _T_21784 ? bht_bank_rd_data_out_1_188 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22363 = _T_22362 | _T_22108; // @[Mux.scala 27:72] - wire _T_21786 = bht_rd_addr_f == 8'hbd; // @[ifu_bp_ctl.scala 454:79] + wire _T_21786 = bht_rd_addr_f == 8'hbd; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_189; // @[Reg.scala 27:20] wire [1:0] _T_22109 = _T_21786 ? bht_bank_rd_data_out_1_189 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22364 = _T_22363 | _T_22109; // @[Mux.scala 27:72] - wire _T_21788 = bht_rd_addr_f == 8'hbe; // @[ifu_bp_ctl.scala 454:79] + wire _T_21788 = bht_rd_addr_f == 8'hbe; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_190; // @[Reg.scala 27:20] wire [1:0] _T_22110 = _T_21788 ? bht_bank_rd_data_out_1_190 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22365 = _T_22364 | _T_22110; // @[Mux.scala 27:72] - wire _T_21790 = bht_rd_addr_f == 8'hbf; // @[ifu_bp_ctl.scala 454:79] + wire _T_21790 = bht_rd_addr_f == 8'hbf; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_191; // @[Reg.scala 27:20] wire [1:0] _T_22111 = _T_21790 ? bht_bank_rd_data_out_1_191 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22366 = _T_22365 | _T_22111; // @[Mux.scala 27:72] - wire _T_21792 = bht_rd_addr_f == 8'hc0; // @[ifu_bp_ctl.scala 454:79] + wire _T_21792 = bht_rd_addr_f == 8'hc0; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_192; // @[Reg.scala 27:20] wire [1:0] _T_22112 = _T_21792 ? bht_bank_rd_data_out_1_192 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22367 = _T_22366 | _T_22112; // @[Mux.scala 27:72] - wire _T_21794 = bht_rd_addr_f == 8'hc1; // @[ifu_bp_ctl.scala 454:79] + wire _T_21794 = bht_rd_addr_f == 8'hc1; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_193; // @[Reg.scala 27:20] wire [1:0] _T_22113 = _T_21794 ? bht_bank_rd_data_out_1_193 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22368 = _T_22367 | _T_22113; // @[Mux.scala 27:72] - wire _T_21796 = bht_rd_addr_f == 8'hc2; // @[ifu_bp_ctl.scala 454:79] + wire _T_21796 = bht_rd_addr_f == 8'hc2; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_194; // @[Reg.scala 27:20] wire [1:0] _T_22114 = _T_21796 ? bht_bank_rd_data_out_1_194 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22369 = _T_22368 | _T_22114; // @[Mux.scala 27:72] - wire _T_21798 = bht_rd_addr_f == 8'hc3; // @[ifu_bp_ctl.scala 454:79] + wire _T_21798 = bht_rd_addr_f == 8'hc3; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_195; // @[Reg.scala 27:20] wire [1:0] _T_22115 = _T_21798 ? bht_bank_rd_data_out_1_195 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22370 = _T_22369 | _T_22115; // @[Mux.scala 27:72] - wire _T_21800 = bht_rd_addr_f == 8'hc4; // @[ifu_bp_ctl.scala 454:79] + wire _T_21800 = bht_rd_addr_f == 8'hc4; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_196; // @[Reg.scala 27:20] wire [1:0] _T_22116 = _T_21800 ? bht_bank_rd_data_out_1_196 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22371 = _T_22370 | _T_22116; // @[Mux.scala 27:72] - wire _T_21802 = bht_rd_addr_f == 8'hc5; // @[ifu_bp_ctl.scala 454:79] + wire _T_21802 = bht_rd_addr_f == 8'hc5; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_197; // @[Reg.scala 27:20] wire [1:0] _T_22117 = _T_21802 ? bht_bank_rd_data_out_1_197 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22372 = _T_22371 | _T_22117; // @[Mux.scala 27:72] - wire _T_21804 = bht_rd_addr_f == 8'hc6; // @[ifu_bp_ctl.scala 454:79] + wire _T_21804 = bht_rd_addr_f == 8'hc6; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_198; // @[Reg.scala 27:20] wire [1:0] _T_22118 = _T_21804 ? bht_bank_rd_data_out_1_198 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22373 = _T_22372 | _T_22118; // @[Mux.scala 27:72] - wire _T_21806 = bht_rd_addr_f == 8'hc7; // @[ifu_bp_ctl.scala 454:79] + wire _T_21806 = bht_rd_addr_f == 8'hc7; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_199; // @[Reg.scala 27:20] wire [1:0] _T_22119 = _T_21806 ? bht_bank_rd_data_out_1_199 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22374 = _T_22373 | _T_22119; // @[Mux.scala 27:72] - wire _T_21808 = bht_rd_addr_f == 8'hc8; // @[ifu_bp_ctl.scala 454:79] + wire _T_21808 = bht_rd_addr_f == 8'hc8; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_200; // @[Reg.scala 27:20] wire [1:0] _T_22120 = _T_21808 ? bht_bank_rd_data_out_1_200 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22375 = _T_22374 | _T_22120; // @[Mux.scala 27:72] - wire _T_21810 = bht_rd_addr_f == 8'hc9; // @[ifu_bp_ctl.scala 454:79] + wire _T_21810 = bht_rd_addr_f == 8'hc9; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_201; // @[Reg.scala 27:20] wire [1:0] _T_22121 = _T_21810 ? bht_bank_rd_data_out_1_201 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22376 = _T_22375 | _T_22121; // @[Mux.scala 27:72] - wire _T_21812 = bht_rd_addr_f == 8'hca; // @[ifu_bp_ctl.scala 454:79] + wire _T_21812 = bht_rd_addr_f == 8'hca; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_202; // @[Reg.scala 27:20] wire [1:0] _T_22122 = _T_21812 ? bht_bank_rd_data_out_1_202 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22377 = _T_22376 | _T_22122; // @[Mux.scala 27:72] - wire _T_21814 = bht_rd_addr_f == 8'hcb; // @[ifu_bp_ctl.scala 454:79] + wire _T_21814 = bht_rd_addr_f == 8'hcb; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_203; // @[Reg.scala 27:20] wire [1:0] _T_22123 = _T_21814 ? bht_bank_rd_data_out_1_203 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22378 = _T_22377 | _T_22123; // @[Mux.scala 27:72] - wire _T_21816 = bht_rd_addr_f == 8'hcc; // @[ifu_bp_ctl.scala 454:79] + wire _T_21816 = bht_rd_addr_f == 8'hcc; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_204; // @[Reg.scala 27:20] wire [1:0] _T_22124 = _T_21816 ? bht_bank_rd_data_out_1_204 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22379 = _T_22378 | _T_22124; // @[Mux.scala 27:72] - wire _T_21818 = bht_rd_addr_f == 8'hcd; // @[ifu_bp_ctl.scala 454:79] + wire _T_21818 = bht_rd_addr_f == 8'hcd; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_205; // @[Reg.scala 27:20] wire [1:0] _T_22125 = _T_21818 ? bht_bank_rd_data_out_1_205 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22380 = _T_22379 | _T_22125; // @[Mux.scala 27:72] - wire _T_21820 = bht_rd_addr_f == 8'hce; // @[ifu_bp_ctl.scala 454:79] + wire _T_21820 = bht_rd_addr_f == 8'hce; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_206; // @[Reg.scala 27:20] wire [1:0] _T_22126 = _T_21820 ? bht_bank_rd_data_out_1_206 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22381 = _T_22380 | _T_22126; // @[Mux.scala 27:72] - wire _T_21822 = bht_rd_addr_f == 8'hcf; // @[ifu_bp_ctl.scala 454:79] + wire _T_21822 = bht_rd_addr_f == 8'hcf; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_207; // @[Reg.scala 27:20] wire [1:0] _T_22127 = _T_21822 ? bht_bank_rd_data_out_1_207 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22382 = _T_22381 | _T_22127; // @[Mux.scala 27:72] - wire _T_21824 = bht_rd_addr_f == 8'hd0; // @[ifu_bp_ctl.scala 454:79] + wire _T_21824 = bht_rd_addr_f == 8'hd0; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_208; // @[Reg.scala 27:20] wire [1:0] _T_22128 = _T_21824 ? bht_bank_rd_data_out_1_208 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22383 = _T_22382 | _T_22128; // @[Mux.scala 27:72] - wire _T_21826 = bht_rd_addr_f == 8'hd1; // @[ifu_bp_ctl.scala 454:79] + wire _T_21826 = bht_rd_addr_f == 8'hd1; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_209; // @[Reg.scala 27:20] wire [1:0] _T_22129 = _T_21826 ? bht_bank_rd_data_out_1_209 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22384 = _T_22383 | _T_22129; // @[Mux.scala 27:72] - wire _T_21828 = bht_rd_addr_f == 8'hd2; // @[ifu_bp_ctl.scala 454:79] + wire _T_21828 = bht_rd_addr_f == 8'hd2; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_210; // @[Reg.scala 27:20] wire [1:0] _T_22130 = _T_21828 ? bht_bank_rd_data_out_1_210 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22385 = _T_22384 | _T_22130; // @[Mux.scala 27:72] - wire _T_21830 = bht_rd_addr_f == 8'hd3; // @[ifu_bp_ctl.scala 454:79] + wire _T_21830 = bht_rd_addr_f == 8'hd3; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_211; // @[Reg.scala 27:20] wire [1:0] _T_22131 = _T_21830 ? bht_bank_rd_data_out_1_211 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22386 = _T_22385 | _T_22131; // @[Mux.scala 27:72] - wire _T_21832 = bht_rd_addr_f == 8'hd4; // @[ifu_bp_ctl.scala 454:79] + wire _T_21832 = bht_rd_addr_f == 8'hd4; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_212; // @[Reg.scala 27:20] wire [1:0] _T_22132 = _T_21832 ? bht_bank_rd_data_out_1_212 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22387 = _T_22386 | _T_22132; // @[Mux.scala 27:72] - wire _T_21834 = bht_rd_addr_f == 8'hd5; // @[ifu_bp_ctl.scala 454:79] + wire _T_21834 = bht_rd_addr_f == 8'hd5; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_213; // @[Reg.scala 27:20] wire [1:0] _T_22133 = _T_21834 ? bht_bank_rd_data_out_1_213 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22388 = _T_22387 | _T_22133; // @[Mux.scala 27:72] - wire _T_21836 = bht_rd_addr_f == 8'hd6; // @[ifu_bp_ctl.scala 454:79] + wire _T_21836 = bht_rd_addr_f == 8'hd6; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_214; // @[Reg.scala 27:20] wire [1:0] _T_22134 = _T_21836 ? bht_bank_rd_data_out_1_214 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22389 = _T_22388 | _T_22134; // @[Mux.scala 27:72] - wire _T_21838 = bht_rd_addr_f == 8'hd7; // @[ifu_bp_ctl.scala 454:79] + wire _T_21838 = bht_rd_addr_f == 8'hd7; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_215; // @[Reg.scala 27:20] wire [1:0] _T_22135 = _T_21838 ? bht_bank_rd_data_out_1_215 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22390 = _T_22389 | _T_22135; // @[Mux.scala 27:72] - wire _T_21840 = bht_rd_addr_f == 8'hd8; // @[ifu_bp_ctl.scala 454:79] + wire _T_21840 = bht_rd_addr_f == 8'hd8; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_216; // @[Reg.scala 27:20] wire [1:0] _T_22136 = _T_21840 ? bht_bank_rd_data_out_1_216 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22391 = _T_22390 | _T_22136; // @[Mux.scala 27:72] - wire _T_21842 = bht_rd_addr_f == 8'hd9; // @[ifu_bp_ctl.scala 454:79] + wire _T_21842 = bht_rd_addr_f == 8'hd9; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_217; // @[Reg.scala 27:20] wire [1:0] _T_22137 = _T_21842 ? bht_bank_rd_data_out_1_217 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22392 = _T_22391 | _T_22137; // @[Mux.scala 27:72] - wire _T_21844 = bht_rd_addr_f == 8'hda; // @[ifu_bp_ctl.scala 454:79] + wire _T_21844 = bht_rd_addr_f == 8'hda; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_218; // @[Reg.scala 27:20] wire [1:0] _T_22138 = _T_21844 ? bht_bank_rd_data_out_1_218 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22393 = _T_22392 | _T_22138; // @[Mux.scala 27:72] - wire _T_21846 = bht_rd_addr_f == 8'hdb; // @[ifu_bp_ctl.scala 454:79] + wire _T_21846 = bht_rd_addr_f == 8'hdb; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_219; // @[Reg.scala 27:20] wire [1:0] _T_22139 = _T_21846 ? bht_bank_rd_data_out_1_219 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22394 = _T_22393 | _T_22139; // @[Mux.scala 27:72] - wire _T_21848 = bht_rd_addr_f == 8'hdc; // @[ifu_bp_ctl.scala 454:79] + wire _T_21848 = bht_rd_addr_f == 8'hdc; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_220; // @[Reg.scala 27:20] wire [1:0] _T_22140 = _T_21848 ? bht_bank_rd_data_out_1_220 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22395 = _T_22394 | _T_22140; // @[Mux.scala 27:72] - wire _T_21850 = bht_rd_addr_f == 8'hdd; // @[ifu_bp_ctl.scala 454:79] + wire _T_21850 = bht_rd_addr_f == 8'hdd; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_221; // @[Reg.scala 27:20] wire [1:0] _T_22141 = _T_21850 ? bht_bank_rd_data_out_1_221 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22396 = _T_22395 | _T_22141; // @[Mux.scala 27:72] - wire _T_21852 = bht_rd_addr_f == 8'hde; // @[ifu_bp_ctl.scala 454:79] + wire _T_21852 = bht_rd_addr_f == 8'hde; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_222; // @[Reg.scala 27:20] wire [1:0] _T_22142 = _T_21852 ? bht_bank_rd_data_out_1_222 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22397 = _T_22396 | _T_22142; // @[Mux.scala 27:72] - wire _T_21854 = bht_rd_addr_f == 8'hdf; // @[ifu_bp_ctl.scala 454:79] + wire _T_21854 = bht_rd_addr_f == 8'hdf; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_223; // @[Reg.scala 27:20] wire [1:0] _T_22143 = _T_21854 ? bht_bank_rd_data_out_1_223 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22398 = _T_22397 | _T_22143; // @[Mux.scala 27:72] - wire _T_21856 = bht_rd_addr_f == 8'he0; // @[ifu_bp_ctl.scala 454:79] + wire _T_21856 = bht_rd_addr_f == 8'he0; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_224; // @[Reg.scala 27:20] wire [1:0] _T_22144 = _T_21856 ? bht_bank_rd_data_out_1_224 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22399 = _T_22398 | _T_22144; // @[Mux.scala 27:72] - wire _T_21858 = bht_rd_addr_f == 8'he1; // @[ifu_bp_ctl.scala 454:79] + wire _T_21858 = bht_rd_addr_f == 8'he1; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_225; // @[Reg.scala 27:20] wire [1:0] _T_22145 = _T_21858 ? bht_bank_rd_data_out_1_225 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22400 = _T_22399 | _T_22145; // @[Mux.scala 27:72] - wire _T_21860 = bht_rd_addr_f == 8'he2; // @[ifu_bp_ctl.scala 454:79] + wire _T_21860 = bht_rd_addr_f == 8'he2; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_226; // @[Reg.scala 27:20] wire [1:0] _T_22146 = _T_21860 ? bht_bank_rd_data_out_1_226 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22401 = _T_22400 | _T_22146; // @[Mux.scala 27:72] - wire _T_21862 = bht_rd_addr_f == 8'he3; // @[ifu_bp_ctl.scala 454:79] + wire _T_21862 = bht_rd_addr_f == 8'he3; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_227; // @[Reg.scala 27:20] wire [1:0] _T_22147 = _T_21862 ? bht_bank_rd_data_out_1_227 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22402 = _T_22401 | _T_22147; // @[Mux.scala 27:72] - wire _T_21864 = bht_rd_addr_f == 8'he4; // @[ifu_bp_ctl.scala 454:79] + wire _T_21864 = bht_rd_addr_f == 8'he4; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_228; // @[Reg.scala 27:20] wire [1:0] _T_22148 = _T_21864 ? bht_bank_rd_data_out_1_228 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22403 = _T_22402 | _T_22148; // @[Mux.scala 27:72] - wire _T_21866 = bht_rd_addr_f == 8'he5; // @[ifu_bp_ctl.scala 454:79] + wire _T_21866 = bht_rd_addr_f == 8'he5; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_229; // @[Reg.scala 27:20] wire [1:0] _T_22149 = _T_21866 ? bht_bank_rd_data_out_1_229 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22404 = _T_22403 | _T_22149; // @[Mux.scala 27:72] - wire _T_21868 = bht_rd_addr_f == 8'he6; // @[ifu_bp_ctl.scala 454:79] + wire _T_21868 = bht_rd_addr_f == 8'he6; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_230; // @[Reg.scala 27:20] wire [1:0] _T_22150 = _T_21868 ? bht_bank_rd_data_out_1_230 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22405 = _T_22404 | _T_22150; // @[Mux.scala 27:72] - wire _T_21870 = bht_rd_addr_f == 8'he7; // @[ifu_bp_ctl.scala 454:79] + wire _T_21870 = bht_rd_addr_f == 8'he7; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_231; // @[Reg.scala 27:20] wire [1:0] _T_22151 = _T_21870 ? bht_bank_rd_data_out_1_231 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22406 = _T_22405 | _T_22151; // @[Mux.scala 27:72] - wire _T_21872 = bht_rd_addr_f == 8'he8; // @[ifu_bp_ctl.scala 454:79] + wire _T_21872 = bht_rd_addr_f == 8'he8; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_232; // @[Reg.scala 27:20] wire [1:0] _T_22152 = _T_21872 ? bht_bank_rd_data_out_1_232 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22407 = _T_22406 | _T_22152; // @[Mux.scala 27:72] - wire _T_21874 = bht_rd_addr_f == 8'he9; // @[ifu_bp_ctl.scala 454:79] + wire _T_21874 = bht_rd_addr_f == 8'he9; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_233; // @[Reg.scala 27:20] wire [1:0] _T_22153 = _T_21874 ? bht_bank_rd_data_out_1_233 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22408 = _T_22407 | _T_22153; // @[Mux.scala 27:72] - wire _T_21876 = bht_rd_addr_f == 8'hea; // @[ifu_bp_ctl.scala 454:79] + wire _T_21876 = bht_rd_addr_f == 8'hea; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_234; // @[Reg.scala 27:20] wire [1:0] _T_22154 = _T_21876 ? bht_bank_rd_data_out_1_234 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22409 = _T_22408 | _T_22154; // @[Mux.scala 27:72] - wire _T_21878 = bht_rd_addr_f == 8'heb; // @[ifu_bp_ctl.scala 454:79] + wire _T_21878 = bht_rd_addr_f == 8'heb; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_235; // @[Reg.scala 27:20] wire [1:0] _T_22155 = _T_21878 ? bht_bank_rd_data_out_1_235 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22410 = _T_22409 | _T_22155; // @[Mux.scala 27:72] - wire _T_21880 = bht_rd_addr_f == 8'hec; // @[ifu_bp_ctl.scala 454:79] + wire _T_21880 = bht_rd_addr_f == 8'hec; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_236; // @[Reg.scala 27:20] wire [1:0] _T_22156 = _T_21880 ? bht_bank_rd_data_out_1_236 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22411 = _T_22410 | _T_22156; // @[Mux.scala 27:72] - wire _T_21882 = bht_rd_addr_f == 8'hed; // @[ifu_bp_ctl.scala 454:79] + wire _T_21882 = bht_rd_addr_f == 8'hed; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_237; // @[Reg.scala 27:20] wire [1:0] _T_22157 = _T_21882 ? bht_bank_rd_data_out_1_237 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22412 = _T_22411 | _T_22157; // @[Mux.scala 27:72] - wire _T_21884 = bht_rd_addr_f == 8'hee; // @[ifu_bp_ctl.scala 454:79] + wire _T_21884 = bht_rd_addr_f == 8'hee; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_238; // @[Reg.scala 27:20] wire [1:0] _T_22158 = _T_21884 ? bht_bank_rd_data_out_1_238 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22413 = _T_22412 | _T_22158; // @[Mux.scala 27:72] - wire _T_21886 = bht_rd_addr_f == 8'hef; // @[ifu_bp_ctl.scala 454:79] + wire _T_21886 = bht_rd_addr_f == 8'hef; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_239; // @[Reg.scala 27:20] wire [1:0] _T_22159 = _T_21886 ? bht_bank_rd_data_out_1_239 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22414 = _T_22413 | _T_22159; // @[Mux.scala 27:72] - wire _T_21888 = bht_rd_addr_f == 8'hf0; // @[ifu_bp_ctl.scala 454:79] + wire _T_21888 = bht_rd_addr_f == 8'hf0; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_240; // @[Reg.scala 27:20] wire [1:0] _T_22160 = _T_21888 ? bht_bank_rd_data_out_1_240 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22415 = _T_22414 | _T_22160; // @[Mux.scala 27:72] - wire _T_21890 = bht_rd_addr_f == 8'hf1; // @[ifu_bp_ctl.scala 454:79] + wire _T_21890 = bht_rd_addr_f == 8'hf1; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_241; // @[Reg.scala 27:20] wire [1:0] _T_22161 = _T_21890 ? bht_bank_rd_data_out_1_241 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22416 = _T_22415 | _T_22161; // @[Mux.scala 27:72] - wire _T_21892 = bht_rd_addr_f == 8'hf2; // @[ifu_bp_ctl.scala 454:79] + wire _T_21892 = bht_rd_addr_f == 8'hf2; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_242; // @[Reg.scala 27:20] wire [1:0] _T_22162 = _T_21892 ? bht_bank_rd_data_out_1_242 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22417 = _T_22416 | _T_22162; // @[Mux.scala 27:72] - wire _T_21894 = bht_rd_addr_f == 8'hf3; // @[ifu_bp_ctl.scala 454:79] + wire _T_21894 = bht_rd_addr_f == 8'hf3; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_243; // @[Reg.scala 27:20] wire [1:0] _T_22163 = _T_21894 ? bht_bank_rd_data_out_1_243 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22418 = _T_22417 | _T_22163; // @[Mux.scala 27:72] - wire _T_21896 = bht_rd_addr_f == 8'hf4; // @[ifu_bp_ctl.scala 454:79] + wire _T_21896 = bht_rd_addr_f == 8'hf4; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_244; // @[Reg.scala 27:20] wire [1:0] _T_22164 = _T_21896 ? bht_bank_rd_data_out_1_244 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22419 = _T_22418 | _T_22164; // @[Mux.scala 27:72] - wire _T_21898 = bht_rd_addr_f == 8'hf5; // @[ifu_bp_ctl.scala 454:79] + wire _T_21898 = bht_rd_addr_f == 8'hf5; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_245; // @[Reg.scala 27:20] wire [1:0] _T_22165 = _T_21898 ? bht_bank_rd_data_out_1_245 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22420 = _T_22419 | _T_22165; // @[Mux.scala 27:72] - wire _T_21900 = bht_rd_addr_f == 8'hf6; // @[ifu_bp_ctl.scala 454:79] + wire _T_21900 = bht_rd_addr_f == 8'hf6; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_246; // @[Reg.scala 27:20] wire [1:0] _T_22166 = _T_21900 ? bht_bank_rd_data_out_1_246 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22421 = _T_22420 | _T_22166; // @[Mux.scala 27:72] - wire _T_21902 = bht_rd_addr_f == 8'hf7; // @[ifu_bp_ctl.scala 454:79] + wire _T_21902 = bht_rd_addr_f == 8'hf7; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_247; // @[Reg.scala 27:20] wire [1:0] _T_22167 = _T_21902 ? bht_bank_rd_data_out_1_247 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22422 = _T_22421 | _T_22167; // @[Mux.scala 27:72] - wire _T_21904 = bht_rd_addr_f == 8'hf8; // @[ifu_bp_ctl.scala 454:79] + wire _T_21904 = bht_rd_addr_f == 8'hf8; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_248; // @[Reg.scala 27:20] wire [1:0] _T_22168 = _T_21904 ? bht_bank_rd_data_out_1_248 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22423 = _T_22422 | _T_22168; // @[Mux.scala 27:72] - wire _T_21906 = bht_rd_addr_f == 8'hf9; // @[ifu_bp_ctl.scala 454:79] + wire _T_21906 = bht_rd_addr_f == 8'hf9; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_249; // @[Reg.scala 27:20] wire [1:0] _T_22169 = _T_21906 ? bht_bank_rd_data_out_1_249 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22424 = _T_22423 | _T_22169; // @[Mux.scala 27:72] - wire _T_21908 = bht_rd_addr_f == 8'hfa; // @[ifu_bp_ctl.scala 454:79] + wire _T_21908 = bht_rd_addr_f == 8'hfa; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_250; // @[Reg.scala 27:20] wire [1:0] _T_22170 = _T_21908 ? bht_bank_rd_data_out_1_250 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22425 = _T_22424 | _T_22170; // @[Mux.scala 27:72] - wire _T_21910 = bht_rd_addr_f == 8'hfb; // @[ifu_bp_ctl.scala 454:79] + wire _T_21910 = bht_rd_addr_f == 8'hfb; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_251; // @[Reg.scala 27:20] wire [1:0] _T_22171 = _T_21910 ? bht_bank_rd_data_out_1_251 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22426 = _T_22425 | _T_22171; // @[Mux.scala 27:72] - wire _T_21912 = bht_rd_addr_f == 8'hfc; // @[ifu_bp_ctl.scala 454:79] + wire _T_21912 = bht_rd_addr_f == 8'hfc; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_252; // @[Reg.scala 27:20] wire [1:0] _T_22172 = _T_21912 ? bht_bank_rd_data_out_1_252 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22427 = _T_22426 | _T_22172; // @[Mux.scala 27:72] - wire _T_21914 = bht_rd_addr_f == 8'hfd; // @[ifu_bp_ctl.scala 454:79] + wire _T_21914 = bht_rd_addr_f == 8'hfd; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_253; // @[Reg.scala 27:20] wire [1:0] _T_22173 = _T_21914 ? bht_bank_rd_data_out_1_253 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22428 = _T_22427 | _T_22173; // @[Mux.scala 27:72] - wire _T_21916 = bht_rd_addr_f == 8'hfe; // @[ifu_bp_ctl.scala 454:79] + wire _T_21916 = bht_rd_addr_f == 8'hfe; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_254; // @[Reg.scala 27:20] wire [1:0] _T_22174 = _T_21916 ? bht_bank_rd_data_out_1_254 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_22429 = _T_22428 | _T_22174; // @[Mux.scala 27:72] - wire _T_21918 = bht_rd_addr_f == 8'hff; // @[ifu_bp_ctl.scala 454:79] + wire _T_21918 = bht_rd_addr_f == 8'hff; // @[ifu_bp_ctl.scala 455:79] reg [1:0] bht_bank_rd_data_out_1_255; // @[Reg.scala 27:20] wire [1:0] _T_22175 = _T_21918 ? bht_bank_rd_data_out_1_255 : 2'h0; // @[Mux.scala 27:72] wire [1:0] bht_bank1_rd_data_f = _T_22429 | _T_22175; // @[Mux.scala 27:72] wire [1:0] _T_260 = _T_144 ? bht_bank1_rd_data_f : 2'h0; // @[Mux.scala 27:72] wire [9:0] _T_573 = {btb_rd_addr_p1_f,2'h0}; // @[Cat.scala 29:58] wire [7:0] bht_rd_addr_hashed_p1_f = _T_573[9:2] ^ fghr; // @[lib.scala 40:35] - wire _T_22432 = bht_rd_addr_hashed_p1_f == 8'h0; // @[ifu_bp_ctl.scala 455:85] + wire _T_22432 = bht_rd_addr_hashed_p1_f == 8'h0; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_0; // @[Reg.scala 27:20] wire [1:0] _T_22944 = _T_22432 ? bht_bank_rd_data_out_0_0 : 2'h0; // @[Mux.scala 27:72] - wire _T_22434 = bht_rd_addr_hashed_p1_f == 8'h1; // @[ifu_bp_ctl.scala 455:85] + wire _T_22434 = bht_rd_addr_hashed_p1_f == 8'h1; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_1; // @[Reg.scala 27:20] wire [1:0] _T_22945 = _T_22434 ? bht_bank_rd_data_out_0_1 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23200 = _T_22944 | _T_22945; // @[Mux.scala 27:72] - wire _T_22436 = bht_rd_addr_hashed_p1_f == 8'h2; // @[ifu_bp_ctl.scala 455:85] + wire _T_22436 = bht_rd_addr_hashed_p1_f == 8'h2; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_2; // @[Reg.scala 27:20] wire [1:0] _T_22946 = _T_22436 ? bht_bank_rd_data_out_0_2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23201 = _T_23200 | _T_22946; // @[Mux.scala 27:72] - wire _T_22438 = bht_rd_addr_hashed_p1_f == 8'h3; // @[ifu_bp_ctl.scala 455:85] + wire _T_22438 = bht_rd_addr_hashed_p1_f == 8'h3; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_3; // @[Reg.scala 27:20] wire [1:0] _T_22947 = _T_22438 ? bht_bank_rd_data_out_0_3 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23202 = _T_23201 | _T_22947; // @[Mux.scala 27:72] - wire _T_22440 = bht_rd_addr_hashed_p1_f == 8'h4; // @[ifu_bp_ctl.scala 455:85] + wire _T_22440 = bht_rd_addr_hashed_p1_f == 8'h4; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_4; // @[Reg.scala 27:20] wire [1:0] _T_22948 = _T_22440 ? bht_bank_rd_data_out_0_4 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23203 = _T_23202 | _T_22948; // @[Mux.scala 27:72] - wire _T_22442 = bht_rd_addr_hashed_p1_f == 8'h5; // @[ifu_bp_ctl.scala 455:85] + wire _T_22442 = bht_rd_addr_hashed_p1_f == 8'h5; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_5; // @[Reg.scala 27:20] wire [1:0] _T_22949 = _T_22442 ? bht_bank_rd_data_out_0_5 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23204 = _T_23203 | _T_22949; // @[Mux.scala 27:72] - wire _T_22444 = bht_rd_addr_hashed_p1_f == 8'h6; // @[ifu_bp_ctl.scala 455:85] + wire _T_22444 = bht_rd_addr_hashed_p1_f == 8'h6; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_6; // @[Reg.scala 27:20] wire [1:0] _T_22950 = _T_22444 ? bht_bank_rd_data_out_0_6 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23205 = _T_23204 | _T_22950; // @[Mux.scala 27:72] - wire _T_22446 = bht_rd_addr_hashed_p1_f == 8'h7; // @[ifu_bp_ctl.scala 455:85] + wire _T_22446 = bht_rd_addr_hashed_p1_f == 8'h7; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_7; // @[Reg.scala 27:20] wire [1:0] _T_22951 = _T_22446 ? bht_bank_rd_data_out_0_7 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23206 = _T_23205 | _T_22951; // @[Mux.scala 27:72] - wire _T_22448 = bht_rd_addr_hashed_p1_f == 8'h8; // @[ifu_bp_ctl.scala 455:85] + wire _T_22448 = bht_rd_addr_hashed_p1_f == 8'h8; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_8; // @[Reg.scala 27:20] wire [1:0] _T_22952 = _T_22448 ? bht_bank_rd_data_out_0_8 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23207 = _T_23206 | _T_22952; // @[Mux.scala 27:72] - wire _T_22450 = bht_rd_addr_hashed_p1_f == 8'h9; // @[ifu_bp_ctl.scala 455:85] + wire _T_22450 = bht_rd_addr_hashed_p1_f == 8'h9; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_9; // @[Reg.scala 27:20] wire [1:0] _T_22953 = _T_22450 ? bht_bank_rd_data_out_0_9 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23208 = _T_23207 | _T_22953; // @[Mux.scala 27:72] - wire _T_22452 = bht_rd_addr_hashed_p1_f == 8'ha; // @[ifu_bp_ctl.scala 455:85] + wire _T_22452 = bht_rd_addr_hashed_p1_f == 8'ha; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_10; // @[Reg.scala 27:20] wire [1:0] _T_22954 = _T_22452 ? bht_bank_rd_data_out_0_10 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23209 = _T_23208 | _T_22954; // @[Mux.scala 27:72] - wire _T_22454 = bht_rd_addr_hashed_p1_f == 8'hb; // @[ifu_bp_ctl.scala 455:85] + wire _T_22454 = bht_rd_addr_hashed_p1_f == 8'hb; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_11; // @[Reg.scala 27:20] wire [1:0] _T_22955 = _T_22454 ? bht_bank_rd_data_out_0_11 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23210 = _T_23209 | _T_22955; // @[Mux.scala 27:72] - wire _T_22456 = bht_rd_addr_hashed_p1_f == 8'hc; // @[ifu_bp_ctl.scala 455:85] + wire _T_22456 = bht_rd_addr_hashed_p1_f == 8'hc; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_12; // @[Reg.scala 27:20] wire [1:0] _T_22956 = _T_22456 ? bht_bank_rd_data_out_0_12 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23211 = _T_23210 | _T_22956; // @[Mux.scala 27:72] - wire _T_22458 = bht_rd_addr_hashed_p1_f == 8'hd; // @[ifu_bp_ctl.scala 455:85] + wire _T_22458 = bht_rd_addr_hashed_p1_f == 8'hd; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_13; // @[Reg.scala 27:20] wire [1:0] _T_22957 = _T_22458 ? bht_bank_rd_data_out_0_13 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23212 = _T_23211 | _T_22957; // @[Mux.scala 27:72] - wire _T_22460 = bht_rd_addr_hashed_p1_f == 8'he; // @[ifu_bp_ctl.scala 455:85] + wire _T_22460 = bht_rd_addr_hashed_p1_f == 8'he; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_14; // @[Reg.scala 27:20] wire [1:0] _T_22958 = _T_22460 ? bht_bank_rd_data_out_0_14 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23213 = _T_23212 | _T_22958; // @[Mux.scala 27:72] - wire _T_22462 = bht_rd_addr_hashed_p1_f == 8'hf; // @[ifu_bp_ctl.scala 455:85] + wire _T_22462 = bht_rd_addr_hashed_p1_f == 8'hf; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_15; // @[Reg.scala 27:20] wire [1:0] _T_22959 = _T_22462 ? bht_bank_rd_data_out_0_15 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23214 = _T_23213 | _T_22959; // @[Mux.scala 27:72] - wire _T_22464 = bht_rd_addr_hashed_p1_f == 8'h10; // @[ifu_bp_ctl.scala 455:85] + wire _T_22464 = bht_rd_addr_hashed_p1_f == 8'h10; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_16; // @[Reg.scala 27:20] wire [1:0] _T_22960 = _T_22464 ? bht_bank_rd_data_out_0_16 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23215 = _T_23214 | _T_22960; // @[Mux.scala 27:72] - wire _T_22466 = bht_rd_addr_hashed_p1_f == 8'h11; // @[ifu_bp_ctl.scala 455:85] + wire _T_22466 = bht_rd_addr_hashed_p1_f == 8'h11; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_17; // @[Reg.scala 27:20] wire [1:0] _T_22961 = _T_22466 ? bht_bank_rd_data_out_0_17 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23216 = _T_23215 | _T_22961; // @[Mux.scala 27:72] - wire _T_22468 = bht_rd_addr_hashed_p1_f == 8'h12; // @[ifu_bp_ctl.scala 455:85] + wire _T_22468 = bht_rd_addr_hashed_p1_f == 8'h12; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_18; // @[Reg.scala 27:20] wire [1:0] _T_22962 = _T_22468 ? bht_bank_rd_data_out_0_18 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23217 = _T_23216 | _T_22962; // @[Mux.scala 27:72] - wire _T_22470 = bht_rd_addr_hashed_p1_f == 8'h13; // @[ifu_bp_ctl.scala 455:85] + wire _T_22470 = bht_rd_addr_hashed_p1_f == 8'h13; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_19; // @[Reg.scala 27:20] wire [1:0] _T_22963 = _T_22470 ? bht_bank_rd_data_out_0_19 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23218 = _T_23217 | _T_22963; // @[Mux.scala 27:72] - wire _T_22472 = bht_rd_addr_hashed_p1_f == 8'h14; // @[ifu_bp_ctl.scala 455:85] + wire _T_22472 = bht_rd_addr_hashed_p1_f == 8'h14; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_20; // @[Reg.scala 27:20] wire [1:0] _T_22964 = _T_22472 ? bht_bank_rd_data_out_0_20 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23219 = _T_23218 | _T_22964; // @[Mux.scala 27:72] - wire _T_22474 = bht_rd_addr_hashed_p1_f == 8'h15; // @[ifu_bp_ctl.scala 455:85] + wire _T_22474 = bht_rd_addr_hashed_p1_f == 8'h15; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_21; // @[Reg.scala 27:20] wire [1:0] _T_22965 = _T_22474 ? bht_bank_rd_data_out_0_21 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23220 = _T_23219 | _T_22965; // @[Mux.scala 27:72] - wire _T_22476 = bht_rd_addr_hashed_p1_f == 8'h16; // @[ifu_bp_ctl.scala 455:85] + wire _T_22476 = bht_rd_addr_hashed_p1_f == 8'h16; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_22; // @[Reg.scala 27:20] wire [1:0] _T_22966 = _T_22476 ? bht_bank_rd_data_out_0_22 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23221 = _T_23220 | _T_22966; // @[Mux.scala 27:72] - wire _T_22478 = bht_rd_addr_hashed_p1_f == 8'h17; // @[ifu_bp_ctl.scala 455:85] + wire _T_22478 = bht_rd_addr_hashed_p1_f == 8'h17; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_23; // @[Reg.scala 27:20] wire [1:0] _T_22967 = _T_22478 ? bht_bank_rd_data_out_0_23 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23222 = _T_23221 | _T_22967; // @[Mux.scala 27:72] - wire _T_22480 = bht_rd_addr_hashed_p1_f == 8'h18; // @[ifu_bp_ctl.scala 455:85] + wire _T_22480 = bht_rd_addr_hashed_p1_f == 8'h18; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_24; // @[Reg.scala 27:20] wire [1:0] _T_22968 = _T_22480 ? bht_bank_rd_data_out_0_24 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23223 = _T_23222 | _T_22968; // @[Mux.scala 27:72] - wire _T_22482 = bht_rd_addr_hashed_p1_f == 8'h19; // @[ifu_bp_ctl.scala 455:85] + wire _T_22482 = bht_rd_addr_hashed_p1_f == 8'h19; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_25; // @[Reg.scala 27:20] wire [1:0] _T_22969 = _T_22482 ? bht_bank_rd_data_out_0_25 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23224 = _T_23223 | _T_22969; // @[Mux.scala 27:72] - wire _T_22484 = bht_rd_addr_hashed_p1_f == 8'h1a; // @[ifu_bp_ctl.scala 455:85] + wire _T_22484 = bht_rd_addr_hashed_p1_f == 8'h1a; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_26; // @[Reg.scala 27:20] wire [1:0] _T_22970 = _T_22484 ? bht_bank_rd_data_out_0_26 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23225 = _T_23224 | _T_22970; // @[Mux.scala 27:72] - wire _T_22486 = bht_rd_addr_hashed_p1_f == 8'h1b; // @[ifu_bp_ctl.scala 455:85] + wire _T_22486 = bht_rd_addr_hashed_p1_f == 8'h1b; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_27; // @[Reg.scala 27:20] wire [1:0] _T_22971 = _T_22486 ? bht_bank_rd_data_out_0_27 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23226 = _T_23225 | _T_22971; // @[Mux.scala 27:72] - wire _T_22488 = bht_rd_addr_hashed_p1_f == 8'h1c; // @[ifu_bp_ctl.scala 455:85] + wire _T_22488 = bht_rd_addr_hashed_p1_f == 8'h1c; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_28; // @[Reg.scala 27:20] wire [1:0] _T_22972 = _T_22488 ? bht_bank_rd_data_out_0_28 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23227 = _T_23226 | _T_22972; // @[Mux.scala 27:72] - wire _T_22490 = bht_rd_addr_hashed_p1_f == 8'h1d; // @[ifu_bp_ctl.scala 455:85] + wire _T_22490 = bht_rd_addr_hashed_p1_f == 8'h1d; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_29; // @[Reg.scala 27:20] wire [1:0] _T_22973 = _T_22490 ? bht_bank_rd_data_out_0_29 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23228 = _T_23227 | _T_22973; // @[Mux.scala 27:72] - wire _T_22492 = bht_rd_addr_hashed_p1_f == 8'h1e; // @[ifu_bp_ctl.scala 455:85] + wire _T_22492 = bht_rd_addr_hashed_p1_f == 8'h1e; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_30; // @[Reg.scala 27:20] wire [1:0] _T_22974 = _T_22492 ? bht_bank_rd_data_out_0_30 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23229 = _T_23228 | _T_22974; // @[Mux.scala 27:72] - wire _T_22494 = bht_rd_addr_hashed_p1_f == 8'h1f; // @[ifu_bp_ctl.scala 455:85] + wire _T_22494 = bht_rd_addr_hashed_p1_f == 8'h1f; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_31; // @[Reg.scala 27:20] wire [1:0] _T_22975 = _T_22494 ? bht_bank_rd_data_out_0_31 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23230 = _T_23229 | _T_22975; // @[Mux.scala 27:72] - wire _T_22496 = bht_rd_addr_hashed_p1_f == 8'h20; // @[ifu_bp_ctl.scala 455:85] + wire _T_22496 = bht_rd_addr_hashed_p1_f == 8'h20; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_32; // @[Reg.scala 27:20] wire [1:0] _T_22976 = _T_22496 ? bht_bank_rd_data_out_0_32 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23231 = _T_23230 | _T_22976; // @[Mux.scala 27:72] - wire _T_22498 = bht_rd_addr_hashed_p1_f == 8'h21; // @[ifu_bp_ctl.scala 455:85] + wire _T_22498 = bht_rd_addr_hashed_p1_f == 8'h21; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_33; // @[Reg.scala 27:20] wire [1:0] _T_22977 = _T_22498 ? bht_bank_rd_data_out_0_33 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23232 = _T_23231 | _T_22977; // @[Mux.scala 27:72] - wire _T_22500 = bht_rd_addr_hashed_p1_f == 8'h22; // @[ifu_bp_ctl.scala 455:85] + wire _T_22500 = bht_rd_addr_hashed_p1_f == 8'h22; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_34; // @[Reg.scala 27:20] wire [1:0] _T_22978 = _T_22500 ? bht_bank_rd_data_out_0_34 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23233 = _T_23232 | _T_22978; // @[Mux.scala 27:72] - wire _T_22502 = bht_rd_addr_hashed_p1_f == 8'h23; // @[ifu_bp_ctl.scala 455:85] + wire _T_22502 = bht_rd_addr_hashed_p1_f == 8'h23; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_35; // @[Reg.scala 27:20] wire [1:0] _T_22979 = _T_22502 ? bht_bank_rd_data_out_0_35 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23234 = _T_23233 | _T_22979; // @[Mux.scala 27:72] - wire _T_22504 = bht_rd_addr_hashed_p1_f == 8'h24; // @[ifu_bp_ctl.scala 455:85] + wire _T_22504 = bht_rd_addr_hashed_p1_f == 8'h24; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_36; // @[Reg.scala 27:20] wire [1:0] _T_22980 = _T_22504 ? bht_bank_rd_data_out_0_36 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23235 = _T_23234 | _T_22980; // @[Mux.scala 27:72] - wire _T_22506 = bht_rd_addr_hashed_p1_f == 8'h25; // @[ifu_bp_ctl.scala 455:85] + wire _T_22506 = bht_rd_addr_hashed_p1_f == 8'h25; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_37; // @[Reg.scala 27:20] wire [1:0] _T_22981 = _T_22506 ? bht_bank_rd_data_out_0_37 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23236 = _T_23235 | _T_22981; // @[Mux.scala 27:72] - wire _T_22508 = bht_rd_addr_hashed_p1_f == 8'h26; // @[ifu_bp_ctl.scala 455:85] + wire _T_22508 = bht_rd_addr_hashed_p1_f == 8'h26; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_38; // @[Reg.scala 27:20] wire [1:0] _T_22982 = _T_22508 ? bht_bank_rd_data_out_0_38 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23237 = _T_23236 | _T_22982; // @[Mux.scala 27:72] - wire _T_22510 = bht_rd_addr_hashed_p1_f == 8'h27; // @[ifu_bp_ctl.scala 455:85] + wire _T_22510 = bht_rd_addr_hashed_p1_f == 8'h27; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_39; // @[Reg.scala 27:20] wire [1:0] _T_22983 = _T_22510 ? bht_bank_rd_data_out_0_39 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23238 = _T_23237 | _T_22983; // @[Mux.scala 27:72] - wire _T_22512 = bht_rd_addr_hashed_p1_f == 8'h28; // @[ifu_bp_ctl.scala 455:85] + wire _T_22512 = bht_rd_addr_hashed_p1_f == 8'h28; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_40; // @[Reg.scala 27:20] wire [1:0] _T_22984 = _T_22512 ? bht_bank_rd_data_out_0_40 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23239 = _T_23238 | _T_22984; // @[Mux.scala 27:72] - wire _T_22514 = bht_rd_addr_hashed_p1_f == 8'h29; // @[ifu_bp_ctl.scala 455:85] + wire _T_22514 = bht_rd_addr_hashed_p1_f == 8'h29; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_41; // @[Reg.scala 27:20] wire [1:0] _T_22985 = _T_22514 ? bht_bank_rd_data_out_0_41 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23240 = _T_23239 | _T_22985; // @[Mux.scala 27:72] - wire _T_22516 = bht_rd_addr_hashed_p1_f == 8'h2a; // @[ifu_bp_ctl.scala 455:85] + wire _T_22516 = bht_rd_addr_hashed_p1_f == 8'h2a; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_42; // @[Reg.scala 27:20] wire [1:0] _T_22986 = _T_22516 ? bht_bank_rd_data_out_0_42 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23241 = _T_23240 | _T_22986; // @[Mux.scala 27:72] - wire _T_22518 = bht_rd_addr_hashed_p1_f == 8'h2b; // @[ifu_bp_ctl.scala 455:85] + wire _T_22518 = bht_rd_addr_hashed_p1_f == 8'h2b; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_43; // @[Reg.scala 27:20] wire [1:0] _T_22987 = _T_22518 ? bht_bank_rd_data_out_0_43 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23242 = _T_23241 | _T_22987; // @[Mux.scala 27:72] - wire _T_22520 = bht_rd_addr_hashed_p1_f == 8'h2c; // @[ifu_bp_ctl.scala 455:85] + wire _T_22520 = bht_rd_addr_hashed_p1_f == 8'h2c; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_44; // @[Reg.scala 27:20] wire [1:0] _T_22988 = _T_22520 ? bht_bank_rd_data_out_0_44 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23243 = _T_23242 | _T_22988; // @[Mux.scala 27:72] - wire _T_22522 = bht_rd_addr_hashed_p1_f == 8'h2d; // @[ifu_bp_ctl.scala 455:85] + wire _T_22522 = bht_rd_addr_hashed_p1_f == 8'h2d; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_45; // @[Reg.scala 27:20] wire [1:0] _T_22989 = _T_22522 ? bht_bank_rd_data_out_0_45 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23244 = _T_23243 | _T_22989; // @[Mux.scala 27:72] - wire _T_22524 = bht_rd_addr_hashed_p1_f == 8'h2e; // @[ifu_bp_ctl.scala 455:85] + wire _T_22524 = bht_rd_addr_hashed_p1_f == 8'h2e; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_46; // @[Reg.scala 27:20] wire [1:0] _T_22990 = _T_22524 ? bht_bank_rd_data_out_0_46 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23245 = _T_23244 | _T_22990; // @[Mux.scala 27:72] - wire _T_22526 = bht_rd_addr_hashed_p1_f == 8'h2f; // @[ifu_bp_ctl.scala 455:85] + wire _T_22526 = bht_rd_addr_hashed_p1_f == 8'h2f; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_47; // @[Reg.scala 27:20] wire [1:0] _T_22991 = _T_22526 ? bht_bank_rd_data_out_0_47 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23246 = _T_23245 | _T_22991; // @[Mux.scala 27:72] - wire _T_22528 = bht_rd_addr_hashed_p1_f == 8'h30; // @[ifu_bp_ctl.scala 455:85] + wire _T_22528 = bht_rd_addr_hashed_p1_f == 8'h30; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_48; // @[Reg.scala 27:20] wire [1:0] _T_22992 = _T_22528 ? bht_bank_rd_data_out_0_48 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23247 = _T_23246 | _T_22992; // @[Mux.scala 27:72] - wire _T_22530 = bht_rd_addr_hashed_p1_f == 8'h31; // @[ifu_bp_ctl.scala 455:85] + wire _T_22530 = bht_rd_addr_hashed_p1_f == 8'h31; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_49; // @[Reg.scala 27:20] wire [1:0] _T_22993 = _T_22530 ? bht_bank_rd_data_out_0_49 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23248 = _T_23247 | _T_22993; // @[Mux.scala 27:72] - wire _T_22532 = bht_rd_addr_hashed_p1_f == 8'h32; // @[ifu_bp_ctl.scala 455:85] + wire _T_22532 = bht_rd_addr_hashed_p1_f == 8'h32; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_50; // @[Reg.scala 27:20] wire [1:0] _T_22994 = _T_22532 ? bht_bank_rd_data_out_0_50 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23249 = _T_23248 | _T_22994; // @[Mux.scala 27:72] - wire _T_22534 = bht_rd_addr_hashed_p1_f == 8'h33; // @[ifu_bp_ctl.scala 455:85] + wire _T_22534 = bht_rd_addr_hashed_p1_f == 8'h33; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_51; // @[Reg.scala 27:20] wire [1:0] _T_22995 = _T_22534 ? bht_bank_rd_data_out_0_51 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23250 = _T_23249 | _T_22995; // @[Mux.scala 27:72] - wire _T_22536 = bht_rd_addr_hashed_p1_f == 8'h34; // @[ifu_bp_ctl.scala 455:85] + wire _T_22536 = bht_rd_addr_hashed_p1_f == 8'h34; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_52; // @[Reg.scala 27:20] wire [1:0] _T_22996 = _T_22536 ? bht_bank_rd_data_out_0_52 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23251 = _T_23250 | _T_22996; // @[Mux.scala 27:72] - wire _T_22538 = bht_rd_addr_hashed_p1_f == 8'h35; // @[ifu_bp_ctl.scala 455:85] + wire _T_22538 = bht_rd_addr_hashed_p1_f == 8'h35; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_53; // @[Reg.scala 27:20] wire [1:0] _T_22997 = _T_22538 ? bht_bank_rd_data_out_0_53 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23252 = _T_23251 | _T_22997; // @[Mux.scala 27:72] - wire _T_22540 = bht_rd_addr_hashed_p1_f == 8'h36; // @[ifu_bp_ctl.scala 455:85] + wire _T_22540 = bht_rd_addr_hashed_p1_f == 8'h36; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_54; // @[Reg.scala 27:20] wire [1:0] _T_22998 = _T_22540 ? bht_bank_rd_data_out_0_54 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23253 = _T_23252 | _T_22998; // @[Mux.scala 27:72] - wire _T_22542 = bht_rd_addr_hashed_p1_f == 8'h37; // @[ifu_bp_ctl.scala 455:85] + wire _T_22542 = bht_rd_addr_hashed_p1_f == 8'h37; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_55; // @[Reg.scala 27:20] wire [1:0] _T_22999 = _T_22542 ? bht_bank_rd_data_out_0_55 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23254 = _T_23253 | _T_22999; // @[Mux.scala 27:72] - wire _T_22544 = bht_rd_addr_hashed_p1_f == 8'h38; // @[ifu_bp_ctl.scala 455:85] + wire _T_22544 = bht_rd_addr_hashed_p1_f == 8'h38; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_56; // @[Reg.scala 27:20] wire [1:0] _T_23000 = _T_22544 ? bht_bank_rd_data_out_0_56 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23255 = _T_23254 | _T_23000; // @[Mux.scala 27:72] - wire _T_22546 = bht_rd_addr_hashed_p1_f == 8'h39; // @[ifu_bp_ctl.scala 455:85] + wire _T_22546 = bht_rd_addr_hashed_p1_f == 8'h39; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_57; // @[Reg.scala 27:20] wire [1:0] _T_23001 = _T_22546 ? bht_bank_rd_data_out_0_57 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23256 = _T_23255 | _T_23001; // @[Mux.scala 27:72] - wire _T_22548 = bht_rd_addr_hashed_p1_f == 8'h3a; // @[ifu_bp_ctl.scala 455:85] + wire _T_22548 = bht_rd_addr_hashed_p1_f == 8'h3a; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_58; // @[Reg.scala 27:20] wire [1:0] _T_23002 = _T_22548 ? bht_bank_rd_data_out_0_58 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23257 = _T_23256 | _T_23002; // @[Mux.scala 27:72] - wire _T_22550 = bht_rd_addr_hashed_p1_f == 8'h3b; // @[ifu_bp_ctl.scala 455:85] + wire _T_22550 = bht_rd_addr_hashed_p1_f == 8'h3b; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_59; // @[Reg.scala 27:20] wire [1:0] _T_23003 = _T_22550 ? bht_bank_rd_data_out_0_59 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23258 = _T_23257 | _T_23003; // @[Mux.scala 27:72] - wire _T_22552 = bht_rd_addr_hashed_p1_f == 8'h3c; // @[ifu_bp_ctl.scala 455:85] + wire _T_22552 = bht_rd_addr_hashed_p1_f == 8'h3c; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_60; // @[Reg.scala 27:20] wire [1:0] _T_23004 = _T_22552 ? bht_bank_rd_data_out_0_60 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23259 = _T_23258 | _T_23004; // @[Mux.scala 27:72] - wire _T_22554 = bht_rd_addr_hashed_p1_f == 8'h3d; // @[ifu_bp_ctl.scala 455:85] + wire _T_22554 = bht_rd_addr_hashed_p1_f == 8'h3d; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_61; // @[Reg.scala 27:20] wire [1:0] _T_23005 = _T_22554 ? bht_bank_rd_data_out_0_61 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23260 = _T_23259 | _T_23005; // @[Mux.scala 27:72] - wire _T_22556 = bht_rd_addr_hashed_p1_f == 8'h3e; // @[ifu_bp_ctl.scala 455:85] + wire _T_22556 = bht_rd_addr_hashed_p1_f == 8'h3e; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_62; // @[Reg.scala 27:20] wire [1:0] _T_23006 = _T_22556 ? bht_bank_rd_data_out_0_62 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23261 = _T_23260 | _T_23006; // @[Mux.scala 27:72] - wire _T_22558 = bht_rd_addr_hashed_p1_f == 8'h3f; // @[ifu_bp_ctl.scala 455:85] + wire _T_22558 = bht_rd_addr_hashed_p1_f == 8'h3f; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_63; // @[Reg.scala 27:20] wire [1:0] _T_23007 = _T_22558 ? bht_bank_rd_data_out_0_63 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23262 = _T_23261 | _T_23007; // @[Mux.scala 27:72] - wire _T_22560 = bht_rd_addr_hashed_p1_f == 8'h40; // @[ifu_bp_ctl.scala 455:85] + wire _T_22560 = bht_rd_addr_hashed_p1_f == 8'h40; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_64; // @[Reg.scala 27:20] wire [1:0] _T_23008 = _T_22560 ? bht_bank_rd_data_out_0_64 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23263 = _T_23262 | _T_23008; // @[Mux.scala 27:72] - wire _T_22562 = bht_rd_addr_hashed_p1_f == 8'h41; // @[ifu_bp_ctl.scala 455:85] + wire _T_22562 = bht_rd_addr_hashed_p1_f == 8'h41; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_65; // @[Reg.scala 27:20] wire [1:0] _T_23009 = _T_22562 ? bht_bank_rd_data_out_0_65 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23264 = _T_23263 | _T_23009; // @[Mux.scala 27:72] - wire _T_22564 = bht_rd_addr_hashed_p1_f == 8'h42; // @[ifu_bp_ctl.scala 455:85] + wire _T_22564 = bht_rd_addr_hashed_p1_f == 8'h42; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_66; // @[Reg.scala 27:20] wire [1:0] _T_23010 = _T_22564 ? bht_bank_rd_data_out_0_66 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23265 = _T_23264 | _T_23010; // @[Mux.scala 27:72] - wire _T_22566 = bht_rd_addr_hashed_p1_f == 8'h43; // @[ifu_bp_ctl.scala 455:85] + wire _T_22566 = bht_rd_addr_hashed_p1_f == 8'h43; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_67; // @[Reg.scala 27:20] wire [1:0] _T_23011 = _T_22566 ? bht_bank_rd_data_out_0_67 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23266 = _T_23265 | _T_23011; // @[Mux.scala 27:72] - wire _T_22568 = bht_rd_addr_hashed_p1_f == 8'h44; // @[ifu_bp_ctl.scala 455:85] + wire _T_22568 = bht_rd_addr_hashed_p1_f == 8'h44; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_68; // @[Reg.scala 27:20] wire [1:0] _T_23012 = _T_22568 ? bht_bank_rd_data_out_0_68 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23267 = _T_23266 | _T_23012; // @[Mux.scala 27:72] - wire _T_22570 = bht_rd_addr_hashed_p1_f == 8'h45; // @[ifu_bp_ctl.scala 455:85] + wire _T_22570 = bht_rd_addr_hashed_p1_f == 8'h45; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_69; // @[Reg.scala 27:20] wire [1:0] _T_23013 = _T_22570 ? bht_bank_rd_data_out_0_69 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23268 = _T_23267 | _T_23013; // @[Mux.scala 27:72] - wire _T_22572 = bht_rd_addr_hashed_p1_f == 8'h46; // @[ifu_bp_ctl.scala 455:85] + wire _T_22572 = bht_rd_addr_hashed_p1_f == 8'h46; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_70; // @[Reg.scala 27:20] wire [1:0] _T_23014 = _T_22572 ? bht_bank_rd_data_out_0_70 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23269 = _T_23268 | _T_23014; // @[Mux.scala 27:72] - wire _T_22574 = bht_rd_addr_hashed_p1_f == 8'h47; // @[ifu_bp_ctl.scala 455:85] + wire _T_22574 = bht_rd_addr_hashed_p1_f == 8'h47; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_71; // @[Reg.scala 27:20] wire [1:0] _T_23015 = _T_22574 ? bht_bank_rd_data_out_0_71 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23270 = _T_23269 | _T_23015; // @[Mux.scala 27:72] - wire _T_22576 = bht_rd_addr_hashed_p1_f == 8'h48; // @[ifu_bp_ctl.scala 455:85] + wire _T_22576 = bht_rd_addr_hashed_p1_f == 8'h48; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_72; // @[Reg.scala 27:20] wire [1:0] _T_23016 = _T_22576 ? bht_bank_rd_data_out_0_72 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23271 = _T_23270 | _T_23016; // @[Mux.scala 27:72] - wire _T_22578 = bht_rd_addr_hashed_p1_f == 8'h49; // @[ifu_bp_ctl.scala 455:85] + wire _T_22578 = bht_rd_addr_hashed_p1_f == 8'h49; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_73; // @[Reg.scala 27:20] wire [1:0] _T_23017 = _T_22578 ? bht_bank_rd_data_out_0_73 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23272 = _T_23271 | _T_23017; // @[Mux.scala 27:72] - wire _T_22580 = bht_rd_addr_hashed_p1_f == 8'h4a; // @[ifu_bp_ctl.scala 455:85] + wire _T_22580 = bht_rd_addr_hashed_p1_f == 8'h4a; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_74; // @[Reg.scala 27:20] wire [1:0] _T_23018 = _T_22580 ? bht_bank_rd_data_out_0_74 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23273 = _T_23272 | _T_23018; // @[Mux.scala 27:72] - wire _T_22582 = bht_rd_addr_hashed_p1_f == 8'h4b; // @[ifu_bp_ctl.scala 455:85] + wire _T_22582 = bht_rd_addr_hashed_p1_f == 8'h4b; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_75; // @[Reg.scala 27:20] wire [1:0] _T_23019 = _T_22582 ? bht_bank_rd_data_out_0_75 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23274 = _T_23273 | _T_23019; // @[Mux.scala 27:72] - wire _T_22584 = bht_rd_addr_hashed_p1_f == 8'h4c; // @[ifu_bp_ctl.scala 455:85] + wire _T_22584 = bht_rd_addr_hashed_p1_f == 8'h4c; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_76; // @[Reg.scala 27:20] wire [1:0] _T_23020 = _T_22584 ? bht_bank_rd_data_out_0_76 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23275 = _T_23274 | _T_23020; // @[Mux.scala 27:72] - wire _T_22586 = bht_rd_addr_hashed_p1_f == 8'h4d; // @[ifu_bp_ctl.scala 455:85] + wire _T_22586 = bht_rd_addr_hashed_p1_f == 8'h4d; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_77; // @[Reg.scala 27:20] wire [1:0] _T_23021 = _T_22586 ? bht_bank_rd_data_out_0_77 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23276 = _T_23275 | _T_23021; // @[Mux.scala 27:72] - wire _T_22588 = bht_rd_addr_hashed_p1_f == 8'h4e; // @[ifu_bp_ctl.scala 455:85] + wire _T_22588 = bht_rd_addr_hashed_p1_f == 8'h4e; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_78; // @[Reg.scala 27:20] wire [1:0] _T_23022 = _T_22588 ? bht_bank_rd_data_out_0_78 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23277 = _T_23276 | _T_23022; // @[Mux.scala 27:72] - wire _T_22590 = bht_rd_addr_hashed_p1_f == 8'h4f; // @[ifu_bp_ctl.scala 455:85] + wire _T_22590 = bht_rd_addr_hashed_p1_f == 8'h4f; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_79; // @[Reg.scala 27:20] wire [1:0] _T_23023 = _T_22590 ? bht_bank_rd_data_out_0_79 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23278 = _T_23277 | _T_23023; // @[Mux.scala 27:72] - wire _T_22592 = bht_rd_addr_hashed_p1_f == 8'h50; // @[ifu_bp_ctl.scala 455:85] + wire _T_22592 = bht_rd_addr_hashed_p1_f == 8'h50; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_80; // @[Reg.scala 27:20] wire [1:0] _T_23024 = _T_22592 ? bht_bank_rd_data_out_0_80 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23279 = _T_23278 | _T_23024; // @[Mux.scala 27:72] - wire _T_22594 = bht_rd_addr_hashed_p1_f == 8'h51; // @[ifu_bp_ctl.scala 455:85] + wire _T_22594 = bht_rd_addr_hashed_p1_f == 8'h51; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_81; // @[Reg.scala 27:20] wire [1:0] _T_23025 = _T_22594 ? bht_bank_rd_data_out_0_81 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23280 = _T_23279 | _T_23025; // @[Mux.scala 27:72] - wire _T_22596 = bht_rd_addr_hashed_p1_f == 8'h52; // @[ifu_bp_ctl.scala 455:85] + wire _T_22596 = bht_rd_addr_hashed_p1_f == 8'h52; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_82; // @[Reg.scala 27:20] wire [1:0] _T_23026 = _T_22596 ? bht_bank_rd_data_out_0_82 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23281 = _T_23280 | _T_23026; // @[Mux.scala 27:72] - wire _T_22598 = bht_rd_addr_hashed_p1_f == 8'h53; // @[ifu_bp_ctl.scala 455:85] + wire _T_22598 = bht_rd_addr_hashed_p1_f == 8'h53; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_83; // @[Reg.scala 27:20] wire [1:0] _T_23027 = _T_22598 ? bht_bank_rd_data_out_0_83 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23282 = _T_23281 | _T_23027; // @[Mux.scala 27:72] - wire _T_22600 = bht_rd_addr_hashed_p1_f == 8'h54; // @[ifu_bp_ctl.scala 455:85] + wire _T_22600 = bht_rd_addr_hashed_p1_f == 8'h54; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_84; // @[Reg.scala 27:20] wire [1:0] _T_23028 = _T_22600 ? bht_bank_rd_data_out_0_84 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23283 = _T_23282 | _T_23028; // @[Mux.scala 27:72] - wire _T_22602 = bht_rd_addr_hashed_p1_f == 8'h55; // @[ifu_bp_ctl.scala 455:85] + wire _T_22602 = bht_rd_addr_hashed_p1_f == 8'h55; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_85; // @[Reg.scala 27:20] wire [1:0] _T_23029 = _T_22602 ? bht_bank_rd_data_out_0_85 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23284 = _T_23283 | _T_23029; // @[Mux.scala 27:72] - wire _T_22604 = bht_rd_addr_hashed_p1_f == 8'h56; // @[ifu_bp_ctl.scala 455:85] + wire _T_22604 = bht_rd_addr_hashed_p1_f == 8'h56; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_86; // @[Reg.scala 27:20] wire [1:0] _T_23030 = _T_22604 ? bht_bank_rd_data_out_0_86 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23285 = _T_23284 | _T_23030; // @[Mux.scala 27:72] - wire _T_22606 = bht_rd_addr_hashed_p1_f == 8'h57; // @[ifu_bp_ctl.scala 455:85] + wire _T_22606 = bht_rd_addr_hashed_p1_f == 8'h57; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_87; // @[Reg.scala 27:20] wire [1:0] _T_23031 = _T_22606 ? bht_bank_rd_data_out_0_87 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23286 = _T_23285 | _T_23031; // @[Mux.scala 27:72] - wire _T_22608 = bht_rd_addr_hashed_p1_f == 8'h58; // @[ifu_bp_ctl.scala 455:85] + wire _T_22608 = bht_rd_addr_hashed_p1_f == 8'h58; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_88; // @[Reg.scala 27:20] wire [1:0] _T_23032 = _T_22608 ? bht_bank_rd_data_out_0_88 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23287 = _T_23286 | _T_23032; // @[Mux.scala 27:72] - wire _T_22610 = bht_rd_addr_hashed_p1_f == 8'h59; // @[ifu_bp_ctl.scala 455:85] + wire _T_22610 = bht_rd_addr_hashed_p1_f == 8'h59; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_89; // @[Reg.scala 27:20] wire [1:0] _T_23033 = _T_22610 ? bht_bank_rd_data_out_0_89 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23288 = _T_23287 | _T_23033; // @[Mux.scala 27:72] - wire _T_22612 = bht_rd_addr_hashed_p1_f == 8'h5a; // @[ifu_bp_ctl.scala 455:85] + wire _T_22612 = bht_rd_addr_hashed_p1_f == 8'h5a; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_90; // @[Reg.scala 27:20] wire [1:0] _T_23034 = _T_22612 ? bht_bank_rd_data_out_0_90 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23289 = _T_23288 | _T_23034; // @[Mux.scala 27:72] - wire _T_22614 = bht_rd_addr_hashed_p1_f == 8'h5b; // @[ifu_bp_ctl.scala 455:85] + wire _T_22614 = bht_rd_addr_hashed_p1_f == 8'h5b; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_91; // @[Reg.scala 27:20] wire [1:0] _T_23035 = _T_22614 ? bht_bank_rd_data_out_0_91 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23290 = _T_23289 | _T_23035; // @[Mux.scala 27:72] - wire _T_22616 = bht_rd_addr_hashed_p1_f == 8'h5c; // @[ifu_bp_ctl.scala 455:85] + wire _T_22616 = bht_rd_addr_hashed_p1_f == 8'h5c; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_92; // @[Reg.scala 27:20] wire [1:0] _T_23036 = _T_22616 ? bht_bank_rd_data_out_0_92 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23291 = _T_23290 | _T_23036; // @[Mux.scala 27:72] - wire _T_22618 = bht_rd_addr_hashed_p1_f == 8'h5d; // @[ifu_bp_ctl.scala 455:85] + wire _T_22618 = bht_rd_addr_hashed_p1_f == 8'h5d; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_93; // @[Reg.scala 27:20] wire [1:0] _T_23037 = _T_22618 ? bht_bank_rd_data_out_0_93 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23292 = _T_23291 | _T_23037; // @[Mux.scala 27:72] - wire _T_22620 = bht_rd_addr_hashed_p1_f == 8'h5e; // @[ifu_bp_ctl.scala 455:85] + wire _T_22620 = bht_rd_addr_hashed_p1_f == 8'h5e; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_94; // @[Reg.scala 27:20] wire [1:0] _T_23038 = _T_22620 ? bht_bank_rd_data_out_0_94 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23293 = _T_23292 | _T_23038; // @[Mux.scala 27:72] - wire _T_22622 = bht_rd_addr_hashed_p1_f == 8'h5f; // @[ifu_bp_ctl.scala 455:85] + wire _T_22622 = bht_rd_addr_hashed_p1_f == 8'h5f; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_95; // @[Reg.scala 27:20] wire [1:0] _T_23039 = _T_22622 ? bht_bank_rd_data_out_0_95 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23294 = _T_23293 | _T_23039; // @[Mux.scala 27:72] - wire _T_22624 = bht_rd_addr_hashed_p1_f == 8'h60; // @[ifu_bp_ctl.scala 455:85] + wire _T_22624 = bht_rd_addr_hashed_p1_f == 8'h60; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_96; // @[Reg.scala 27:20] wire [1:0] _T_23040 = _T_22624 ? bht_bank_rd_data_out_0_96 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23295 = _T_23294 | _T_23040; // @[Mux.scala 27:72] - wire _T_22626 = bht_rd_addr_hashed_p1_f == 8'h61; // @[ifu_bp_ctl.scala 455:85] + wire _T_22626 = bht_rd_addr_hashed_p1_f == 8'h61; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_97; // @[Reg.scala 27:20] wire [1:0] _T_23041 = _T_22626 ? bht_bank_rd_data_out_0_97 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23296 = _T_23295 | _T_23041; // @[Mux.scala 27:72] - wire _T_22628 = bht_rd_addr_hashed_p1_f == 8'h62; // @[ifu_bp_ctl.scala 455:85] + wire _T_22628 = bht_rd_addr_hashed_p1_f == 8'h62; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_98; // @[Reg.scala 27:20] wire [1:0] _T_23042 = _T_22628 ? bht_bank_rd_data_out_0_98 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23297 = _T_23296 | _T_23042; // @[Mux.scala 27:72] - wire _T_22630 = bht_rd_addr_hashed_p1_f == 8'h63; // @[ifu_bp_ctl.scala 455:85] + wire _T_22630 = bht_rd_addr_hashed_p1_f == 8'h63; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_99; // @[Reg.scala 27:20] wire [1:0] _T_23043 = _T_22630 ? bht_bank_rd_data_out_0_99 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23298 = _T_23297 | _T_23043; // @[Mux.scala 27:72] - wire _T_22632 = bht_rd_addr_hashed_p1_f == 8'h64; // @[ifu_bp_ctl.scala 455:85] + wire _T_22632 = bht_rd_addr_hashed_p1_f == 8'h64; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_100; // @[Reg.scala 27:20] wire [1:0] _T_23044 = _T_22632 ? bht_bank_rd_data_out_0_100 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23299 = _T_23298 | _T_23044; // @[Mux.scala 27:72] - wire _T_22634 = bht_rd_addr_hashed_p1_f == 8'h65; // @[ifu_bp_ctl.scala 455:85] + wire _T_22634 = bht_rd_addr_hashed_p1_f == 8'h65; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_101; // @[Reg.scala 27:20] wire [1:0] _T_23045 = _T_22634 ? bht_bank_rd_data_out_0_101 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23300 = _T_23299 | _T_23045; // @[Mux.scala 27:72] - wire _T_22636 = bht_rd_addr_hashed_p1_f == 8'h66; // @[ifu_bp_ctl.scala 455:85] + wire _T_22636 = bht_rd_addr_hashed_p1_f == 8'h66; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_102; // @[Reg.scala 27:20] wire [1:0] _T_23046 = _T_22636 ? bht_bank_rd_data_out_0_102 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23301 = _T_23300 | _T_23046; // @[Mux.scala 27:72] - wire _T_22638 = bht_rd_addr_hashed_p1_f == 8'h67; // @[ifu_bp_ctl.scala 455:85] + wire _T_22638 = bht_rd_addr_hashed_p1_f == 8'h67; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_103; // @[Reg.scala 27:20] wire [1:0] _T_23047 = _T_22638 ? bht_bank_rd_data_out_0_103 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23302 = _T_23301 | _T_23047; // @[Mux.scala 27:72] - wire _T_22640 = bht_rd_addr_hashed_p1_f == 8'h68; // @[ifu_bp_ctl.scala 455:85] + wire _T_22640 = bht_rd_addr_hashed_p1_f == 8'h68; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_104; // @[Reg.scala 27:20] wire [1:0] _T_23048 = _T_22640 ? bht_bank_rd_data_out_0_104 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23303 = _T_23302 | _T_23048; // @[Mux.scala 27:72] - wire _T_22642 = bht_rd_addr_hashed_p1_f == 8'h69; // @[ifu_bp_ctl.scala 455:85] + wire _T_22642 = bht_rd_addr_hashed_p1_f == 8'h69; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_105; // @[Reg.scala 27:20] wire [1:0] _T_23049 = _T_22642 ? bht_bank_rd_data_out_0_105 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23304 = _T_23303 | _T_23049; // @[Mux.scala 27:72] - wire _T_22644 = bht_rd_addr_hashed_p1_f == 8'h6a; // @[ifu_bp_ctl.scala 455:85] + wire _T_22644 = bht_rd_addr_hashed_p1_f == 8'h6a; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_106; // @[Reg.scala 27:20] wire [1:0] _T_23050 = _T_22644 ? bht_bank_rd_data_out_0_106 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23305 = _T_23304 | _T_23050; // @[Mux.scala 27:72] - wire _T_22646 = bht_rd_addr_hashed_p1_f == 8'h6b; // @[ifu_bp_ctl.scala 455:85] + wire _T_22646 = bht_rd_addr_hashed_p1_f == 8'h6b; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_107; // @[Reg.scala 27:20] wire [1:0] _T_23051 = _T_22646 ? bht_bank_rd_data_out_0_107 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23306 = _T_23305 | _T_23051; // @[Mux.scala 27:72] - wire _T_22648 = bht_rd_addr_hashed_p1_f == 8'h6c; // @[ifu_bp_ctl.scala 455:85] + wire _T_22648 = bht_rd_addr_hashed_p1_f == 8'h6c; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_108; // @[Reg.scala 27:20] wire [1:0] _T_23052 = _T_22648 ? bht_bank_rd_data_out_0_108 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23307 = _T_23306 | _T_23052; // @[Mux.scala 27:72] - wire _T_22650 = bht_rd_addr_hashed_p1_f == 8'h6d; // @[ifu_bp_ctl.scala 455:85] + wire _T_22650 = bht_rd_addr_hashed_p1_f == 8'h6d; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_109; // @[Reg.scala 27:20] wire [1:0] _T_23053 = _T_22650 ? bht_bank_rd_data_out_0_109 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23308 = _T_23307 | _T_23053; // @[Mux.scala 27:72] - wire _T_22652 = bht_rd_addr_hashed_p1_f == 8'h6e; // @[ifu_bp_ctl.scala 455:85] + wire _T_22652 = bht_rd_addr_hashed_p1_f == 8'h6e; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_110; // @[Reg.scala 27:20] wire [1:0] _T_23054 = _T_22652 ? bht_bank_rd_data_out_0_110 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23309 = _T_23308 | _T_23054; // @[Mux.scala 27:72] - wire _T_22654 = bht_rd_addr_hashed_p1_f == 8'h6f; // @[ifu_bp_ctl.scala 455:85] + wire _T_22654 = bht_rd_addr_hashed_p1_f == 8'h6f; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_111; // @[Reg.scala 27:20] wire [1:0] _T_23055 = _T_22654 ? bht_bank_rd_data_out_0_111 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23310 = _T_23309 | _T_23055; // @[Mux.scala 27:72] - wire _T_22656 = bht_rd_addr_hashed_p1_f == 8'h70; // @[ifu_bp_ctl.scala 455:85] + wire _T_22656 = bht_rd_addr_hashed_p1_f == 8'h70; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_112; // @[Reg.scala 27:20] wire [1:0] _T_23056 = _T_22656 ? bht_bank_rd_data_out_0_112 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23311 = _T_23310 | _T_23056; // @[Mux.scala 27:72] - wire _T_22658 = bht_rd_addr_hashed_p1_f == 8'h71; // @[ifu_bp_ctl.scala 455:85] + wire _T_22658 = bht_rd_addr_hashed_p1_f == 8'h71; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_113; // @[Reg.scala 27:20] wire [1:0] _T_23057 = _T_22658 ? bht_bank_rd_data_out_0_113 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23312 = _T_23311 | _T_23057; // @[Mux.scala 27:72] - wire _T_22660 = bht_rd_addr_hashed_p1_f == 8'h72; // @[ifu_bp_ctl.scala 455:85] + wire _T_22660 = bht_rd_addr_hashed_p1_f == 8'h72; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_114; // @[Reg.scala 27:20] wire [1:0] _T_23058 = _T_22660 ? bht_bank_rd_data_out_0_114 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23313 = _T_23312 | _T_23058; // @[Mux.scala 27:72] - wire _T_22662 = bht_rd_addr_hashed_p1_f == 8'h73; // @[ifu_bp_ctl.scala 455:85] + wire _T_22662 = bht_rd_addr_hashed_p1_f == 8'h73; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_115; // @[Reg.scala 27:20] wire [1:0] _T_23059 = _T_22662 ? bht_bank_rd_data_out_0_115 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23314 = _T_23313 | _T_23059; // @[Mux.scala 27:72] - wire _T_22664 = bht_rd_addr_hashed_p1_f == 8'h74; // @[ifu_bp_ctl.scala 455:85] + wire _T_22664 = bht_rd_addr_hashed_p1_f == 8'h74; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_116; // @[Reg.scala 27:20] wire [1:0] _T_23060 = _T_22664 ? bht_bank_rd_data_out_0_116 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23315 = _T_23314 | _T_23060; // @[Mux.scala 27:72] - wire _T_22666 = bht_rd_addr_hashed_p1_f == 8'h75; // @[ifu_bp_ctl.scala 455:85] + wire _T_22666 = bht_rd_addr_hashed_p1_f == 8'h75; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_117; // @[Reg.scala 27:20] wire [1:0] _T_23061 = _T_22666 ? bht_bank_rd_data_out_0_117 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23316 = _T_23315 | _T_23061; // @[Mux.scala 27:72] - wire _T_22668 = bht_rd_addr_hashed_p1_f == 8'h76; // @[ifu_bp_ctl.scala 455:85] + wire _T_22668 = bht_rd_addr_hashed_p1_f == 8'h76; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_118; // @[Reg.scala 27:20] wire [1:0] _T_23062 = _T_22668 ? bht_bank_rd_data_out_0_118 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23317 = _T_23316 | _T_23062; // @[Mux.scala 27:72] - wire _T_22670 = bht_rd_addr_hashed_p1_f == 8'h77; // @[ifu_bp_ctl.scala 455:85] + wire _T_22670 = bht_rd_addr_hashed_p1_f == 8'h77; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_119; // @[Reg.scala 27:20] wire [1:0] _T_23063 = _T_22670 ? bht_bank_rd_data_out_0_119 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23318 = _T_23317 | _T_23063; // @[Mux.scala 27:72] - wire _T_22672 = bht_rd_addr_hashed_p1_f == 8'h78; // @[ifu_bp_ctl.scala 455:85] + wire _T_22672 = bht_rd_addr_hashed_p1_f == 8'h78; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_120; // @[Reg.scala 27:20] wire [1:0] _T_23064 = _T_22672 ? bht_bank_rd_data_out_0_120 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23319 = _T_23318 | _T_23064; // @[Mux.scala 27:72] - wire _T_22674 = bht_rd_addr_hashed_p1_f == 8'h79; // @[ifu_bp_ctl.scala 455:85] + wire _T_22674 = bht_rd_addr_hashed_p1_f == 8'h79; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_121; // @[Reg.scala 27:20] wire [1:0] _T_23065 = _T_22674 ? bht_bank_rd_data_out_0_121 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23320 = _T_23319 | _T_23065; // @[Mux.scala 27:72] - wire _T_22676 = bht_rd_addr_hashed_p1_f == 8'h7a; // @[ifu_bp_ctl.scala 455:85] + wire _T_22676 = bht_rd_addr_hashed_p1_f == 8'h7a; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_122; // @[Reg.scala 27:20] wire [1:0] _T_23066 = _T_22676 ? bht_bank_rd_data_out_0_122 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23321 = _T_23320 | _T_23066; // @[Mux.scala 27:72] - wire _T_22678 = bht_rd_addr_hashed_p1_f == 8'h7b; // @[ifu_bp_ctl.scala 455:85] + wire _T_22678 = bht_rd_addr_hashed_p1_f == 8'h7b; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_123; // @[Reg.scala 27:20] wire [1:0] _T_23067 = _T_22678 ? bht_bank_rd_data_out_0_123 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23322 = _T_23321 | _T_23067; // @[Mux.scala 27:72] - wire _T_22680 = bht_rd_addr_hashed_p1_f == 8'h7c; // @[ifu_bp_ctl.scala 455:85] + wire _T_22680 = bht_rd_addr_hashed_p1_f == 8'h7c; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_124; // @[Reg.scala 27:20] wire [1:0] _T_23068 = _T_22680 ? bht_bank_rd_data_out_0_124 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23323 = _T_23322 | _T_23068; // @[Mux.scala 27:72] - wire _T_22682 = bht_rd_addr_hashed_p1_f == 8'h7d; // @[ifu_bp_ctl.scala 455:85] + wire _T_22682 = bht_rd_addr_hashed_p1_f == 8'h7d; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_125; // @[Reg.scala 27:20] wire [1:0] _T_23069 = _T_22682 ? bht_bank_rd_data_out_0_125 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23324 = _T_23323 | _T_23069; // @[Mux.scala 27:72] - wire _T_22684 = bht_rd_addr_hashed_p1_f == 8'h7e; // @[ifu_bp_ctl.scala 455:85] + wire _T_22684 = bht_rd_addr_hashed_p1_f == 8'h7e; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_126; // @[Reg.scala 27:20] wire [1:0] _T_23070 = _T_22684 ? bht_bank_rd_data_out_0_126 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23325 = _T_23324 | _T_23070; // @[Mux.scala 27:72] - wire _T_22686 = bht_rd_addr_hashed_p1_f == 8'h7f; // @[ifu_bp_ctl.scala 455:85] + wire _T_22686 = bht_rd_addr_hashed_p1_f == 8'h7f; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_127; // @[Reg.scala 27:20] wire [1:0] _T_23071 = _T_22686 ? bht_bank_rd_data_out_0_127 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23326 = _T_23325 | _T_23071; // @[Mux.scala 27:72] - wire _T_22688 = bht_rd_addr_hashed_p1_f == 8'h80; // @[ifu_bp_ctl.scala 455:85] + wire _T_22688 = bht_rd_addr_hashed_p1_f == 8'h80; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_128; // @[Reg.scala 27:20] wire [1:0] _T_23072 = _T_22688 ? bht_bank_rd_data_out_0_128 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23327 = _T_23326 | _T_23072; // @[Mux.scala 27:72] - wire _T_22690 = bht_rd_addr_hashed_p1_f == 8'h81; // @[ifu_bp_ctl.scala 455:85] + wire _T_22690 = bht_rd_addr_hashed_p1_f == 8'h81; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_129; // @[Reg.scala 27:20] wire [1:0] _T_23073 = _T_22690 ? bht_bank_rd_data_out_0_129 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23328 = _T_23327 | _T_23073; // @[Mux.scala 27:72] - wire _T_22692 = bht_rd_addr_hashed_p1_f == 8'h82; // @[ifu_bp_ctl.scala 455:85] + wire _T_22692 = bht_rd_addr_hashed_p1_f == 8'h82; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_130; // @[Reg.scala 27:20] wire [1:0] _T_23074 = _T_22692 ? bht_bank_rd_data_out_0_130 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23329 = _T_23328 | _T_23074; // @[Mux.scala 27:72] - wire _T_22694 = bht_rd_addr_hashed_p1_f == 8'h83; // @[ifu_bp_ctl.scala 455:85] + wire _T_22694 = bht_rd_addr_hashed_p1_f == 8'h83; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_131; // @[Reg.scala 27:20] wire [1:0] _T_23075 = _T_22694 ? bht_bank_rd_data_out_0_131 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23330 = _T_23329 | _T_23075; // @[Mux.scala 27:72] - wire _T_22696 = bht_rd_addr_hashed_p1_f == 8'h84; // @[ifu_bp_ctl.scala 455:85] + wire _T_22696 = bht_rd_addr_hashed_p1_f == 8'h84; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_132; // @[Reg.scala 27:20] wire [1:0] _T_23076 = _T_22696 ? bht_bank_rd_data_out_0_132 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23331 = _T_23330 | _T_23076; // @[Mux.scala 27:72] - wire _T_22698 = bht_rd_addr_hashed_p1_f == 8'h85; // @[ifu_bp_ctl.scala 455:85] + wire _T_22698 = bht_rd_addr_hashed_p1_f == 8'h85; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_133; // @[Reg.scala 27:20] wire [1:0] _T_23077 = _T_22698 ? bht_bank_rd_data_out_0_133 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23332 = _T_23331 | _T_23077; // @[Mux.scala 27:72] - wire _T_22700 = bht_rd_addr_hashed_p1_f == 8'h86; // @[ifu_bp_ctl.scala 455:85] + wire _T_22700 = bht_rd_addr_hashed_p1_f == 8'h86; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_134; // @[Reg.scala 27:20] wire [1:0] _T_23078 = _T_22700 ? bht_bank_rd_data_out_0_134 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23333 = _T_23332 | _T_23078; // @[Mux.scala 27:72] - wire _T_22702 = bht_rd_addr_hashed_p1_f == 8'h87; // @[ifu_bp_ctl.scala 455:85] + wire _T_22702 = bht_rd_addr_hashed_p1_f == 8'h87; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_135; // @[Reg.scala 27:20] wire [1:0] _T_23079 = _T_22702 ? bht_bank_rd_data_out_0_135 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23334 = _T_23333 | _T_23079; // @[Mux.scala 27:72] - wire _T_22704 = bht_rd_addr_hashed_p1_f == 8'h88; // @[ifu_bp_ctl.scala 455:85] + wire _T_22704 = bht_rd_addr_hashed_p1_f == 8'h88; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_136; // @[Reg.scala 27:20] wire [1:0] _T_23080 = _T_22704 ? bht_bank_rd_data_out_0_136 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23335 = _T_23334 | _T_23080; // @[Mux.scala 27:72] - wire _T_22706 = bht_rd_addr_hashed_p1_f == 8'h89; // @[ifu_bp_ctl.scala 455:85] + wire _T_22706 = bht_rd_addr_hashed_p1_f == 8'h89; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_137; // @[Reg.scala 27:20] wire [1:0] _T_23081 = _T_22706 ? bht_bank_rd_data_out_0_137 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23336 = _T_23335 | _T_23081; // @[Mux.scala 27:72] - wire _T_22708 = bht_rd_addr_hashed_p1_f == 8'h8a; // @[ifu_bp_ctl.scala 455:85] + wire _T_22708 = bht_rd_addr_hashed_p1_f == 8'h8a; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_138; // @[Reg.scala 27:20] wire [1:0] _T_23082 = _T_22708 ? bht_bank_rd_data_out_0_138 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23337 = _T_23336 | _T_23082; // @[Mux.scala 27:72] - wire _T_22710 = bht_rd_addr_hashed_p1_f == 8'h8b; // @[ifu_bp_ctl.scala 455:85] + wire _T_22710 = bht_rd_addr_hashed_p1_f == 8'h8b; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_139; // @[Reg.scala 27:20] wire [1:0] _T_23083 = _T_22710 ? bht_bank_rd_data_out_0_139 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23338 = _T_23337 | _T_23083; // @[Mux.scala 27:72] - wire _T_22712 = bht_rd_addr_hashed_p1_f == 8'h8c; // @[ifu_bp_ctl.scala 455:85] + wire _T_22712 = bht_rd_addr_hashed_p1_f == 8'h8c; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_140; // @[Reg.scala 27:20] wire [1:0] _T_23084 = _T_22712 ? bht_bank_rd_data_out_0_140 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23339 = _T_23338 | _T_23084; // @[Mux.scala 27:72] - wire _T_22714 = bht_rd_addr_hashed_p1_f == 8'h8d; // @[ifu_bp_ctl.scala 455:85] + wire _T_22714 = bht_rd_addr_hashed_p1_f == 8'h8d; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_141; // @[Reg.scala 27:20] wire [1:0] _T_23085 = _T_22714 ? bht_bank_rd_data_out_0_141 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23340 = _T_23339 | _T_23085; // @[Mux.scala 27:72] - wire _T_22716 = bht_rd_addr_hashed_p1_f == 8'h8e; // @[ifu_bp_ctl.scala 455:85] + wire _T_22716 = bht_rd_addr_hashed_p1_f == 8'h8e; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_142; // @[Reg.scala 27:20] wire [1:0] _T_23086 = _T_22716 ? bht_bank_rd_data_out_0_142 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23341 = _T_23340 | _T_23086; // @[Mux.scala 27:72] - wire _T_22718 = bht_rd_addr_hashed_p1_f == 8'h8f; // @[ifu_bp_ctl.scala 455:85] + wire _T_22718 = bht_rd_addr_hashed_p1_f == 8'h8f; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_143; // @[Reg.scala 27:20] wire [1:0] _T_23087 = _T_22718 ? bht_bank_rd_data_out_0_143 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23342 = _T_23341 | _T_23087; // @[Mux.scala 27:72] - wire _T_22720 = bht_rd_addr_hashed_p1_f == 8'h90; // @[ifu_bp_ctl.scala 455:85] + wire _T_22720 = bht_rd_addr_hashed_p1_f == 8'h90; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_144; // @[Reg.scala 27:20] wire [1:0] _T_23088 = _T_22720 ? bht_bank_rd_data_out_0_144 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23343 = _T_23342 | _T_23088; // @[Mux.scala 27:72] - wire _T_22722 = bht_rd_addr_hashed_p1_f == 8'h91; // @[ifu_bp_ctl.scala 455:85] + wire _T_22722 = bht_rd_addr_hashed_p1_f == 8'h91; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_145; // @[Reg.scala 27:20] wire [1:0] _T_23089 = _T_22722 ? bht_bank_rd_data_out_0_145 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23344 = _T_23343 | _T_23089; // @[Mux.scala 27:72] - wire _T_22724 = bht_rd_addr_hashed_p1_f == 8'h92; // @[ifu_bp_ctl.scala 455:85] + wire _T_22724 = bht_rd_addr_hashed_p1_f == 8'h92; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_146; // @[Reg.scala 27:20] wire [1:0] _T_23090 = _T_22724 ? bht_bank_rd_data_out_0_146 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23345 = _T_23344 | _T_23090; // @[Mux.scala 27:72] - wire _T_22726 = bht_rd_addr_hashed_p1_f == 8'h93; // @[ifu_bp_ctl.scala 455:85] + wire _T_22726 = bht_rd_addr_hashed_p1_f == 8'h93; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_147; // @[Reg.scala 27:20] wire [1:0] _T_23091 = _T_22726 ? bht_bank_rd_data_out_0_147 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23346 = _T_23345 | _T_23091; // @[Mux.scala 27:72] - wire _T_22728 = bht_rd_addr_hashed_p1_f == 8'h94; // @[ifu_bp_ctl.scala 455:85] + wire _T_22728 = bht_rd_addr_hashed_p1_f == 8'h94; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_148; // @[Reg.scala 27:20] wire [1:0] _T_23092 = _T_22728 ? bht_bank_rd_data_out_0_148 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23347 = _T_23346 | _T_23092; // @[Mux.scala 27:72] - wire _T_22730 = bht_rd_addr_hashed_p1_f == 8'h95; // @[ifu_bp_ctl.scala 455:85] + wire _T_22730 = bht_rd_addr_hashed_p1_f == 8'h95; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_149; // @[Reg.scala 27:20] wire [1:0] _T_23093 = _T_22730 ? bht_bank_rd_data_out_0_149 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23348 = _T_23347 | _T_23093; // @[Mux.scala 27:72] - wire _T_22732 = bht_rd_addr_hashed_p1_f == 8'h96; // @[ifu_bp_ctl.scala 455:85] + wire _T_22732 = bht_rd_addr_hashed_p1_f == 8'h96; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_150; // @[Reg.scala 27:20] wire [1:0] _T_23094 = _T_22732 ? bht_bank_rd_data_out_0_150 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23349 = _T_23348 | _T_23094; // @[Mux.scala 27:72] - wire _T_22734 = bht_rd_addr_hashed_p1_f == 8'h97; // @[ifu_bp_ctl.scala 455:85] + wire _T_22734 = bht_rd_addr_hashed_p1_f == 8'h97; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_151; // @[Reg.scala 27:20] wire [1:0] _T_23095 = _T_22734 ? bht_bank_rd_data_out_0_151 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23350 = _T_23349 | _T_23095; // @[Mux.scala 27:72] - wire _T_22736 = bht_rd_addr_hashed_p1_f == 8'h98; // @[ifu_bp_ctl.scala 455:85] + wire _T_22736 = bht_rd_addr_hashed_p1_f == 8'h98; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_152; // @[Reg.scala 27:20] wire [1:0] _T_23096 = _T_22736 ? bht_bank_rd_data_out_0_152 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23351 = _T_23350 | _T_23096; // @[Mux.scala 27:72] - wire _T_22738 = bht_rd_addr_hashed_p1_f == 8'h99; // @[ifu_bp_ctl.scala 455:85] + wire _T_22738 = bht_rd_addr_hashed_p1_f == 8'h99; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_153; // @[Reg.scala 27:20] wire [1:0] _T_23097 = _T_22738 ? bht_bank_rd_data_out_0_153 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23352 = _T_23351 | _T_23097; // @[Mux.scala 27:72] - wire _T_22740 = bht_rd_addr_hashed_p1_f == 8'h9a; // @[ifu_bp_ctl.scala 455:85] + wire _T_22740 = bht_rd_addr_hashed_p1_f == 8'h9a; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_154; // @[Reg.scala 27:20] wire [1:0] _T_23098 = _T_22740 ? bht_bank_rd_data_out_0_154 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23353 = _T_23352 | _T_23098; // @[Mux.scala 27:72] - wire _T_22742 = bht_rd_addr_hashed_p1_f == 8'h9b; // @[ifu_bp_ctl.scala 455:85] + wire _T_22742 = bht_rd_addr_hashed_p1_f == 8'h9b; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_155; // @[Reg.scala 27:20] wire [1:0] _T_23099 = _T_22742 ? bht_bank_rd_data_out_0_155 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23354 = _T_23353 | _T_23099; // @[Mux.scala 27:72] - wire _T_22744 = bht_rd_addr_hashed_p1_f == 8'h9c; // @[ifu_bp_ctl.scala 455:85] + wire _T_22744 = bht_rd_addr_hashed_p1_f == 8'h9c; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_156; // @[Reg.scala 27:20] wire [1:0] _T_23100 = _T_22744 ? bht_bank_rd_data_out_0_156 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23355 = _T_23354 | _T_23100; // @[Mux.scala 27:72] - wire _T_22746 = bht_rd_addr_hashed_p1_f == 8'h9d; // @[ifu_bp_ctl.scala 455:85] + wire _T_22746 = bht_rd_addr_hashed_p1_f == 8'h9d; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_157; // @[Reg.scala 27:20] wire [1:0] _T_23101 = _T_22746 ? bht_bank_rd_data_out_0_157 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23356 = _T_23355 | _T_23101; // @[Mux.scala 27:72] - wire _T_22748 = bht_rd_addr_hashed_p1_f == 8'h9e; // @[ifu_bp_ctl.scala 455:85] + wire _T_22748 = bht_rd_addr_hashed_p1_f == 8'h9e; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_158; // @[Reg.scala 27:20] wire [1:0] _T_23102 = _T_22748 ? bht_bank_rd_data_out_0_158 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23357 = _T_23356 | _T_23102; // @[Mux.scala 27:72] - wire _T_22750 = bht_rd_addr_hashed_p1_f == 8'h9f; // @[ifu_bp_ctl.scala 455:85] + wire _T_22750 = bht_rd_addr_hashed_p1_f == 8'h9f; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_159; // @[Reg.scala 27:20] wire [1:0] _T_23103 = _T_22750 ? bht_bank_rd_data_out_0_159 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23358 = _T_23357 | _T_23103; // @[Mux.scala 27:72] - wire _T_22752 = bht_rd_addr_hashed_p1_f == 8'ha0; // @[ifu_bp_ctl.scala 455:85] + wire _T_22752 = bht_rd_addr_hashed_p1_f == 8'ha0; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_160; // @[Reg.scala 27:20] wire [1:0] _T_23104 = _T_22752 ? bht_bank_rd_data_out_0_160 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23359 = _T_23358 | _T_23104; // @[Mux.scala 27:72] - wire _T_22754 = bht_rd_addr_hashed_p1_f == 8'ha1; // @[ifu_bp_ctl.scala 455:85] + wire _T_22754 = bht_rd_addr_hashed_p1_f == 8'ha1; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_161; // @[Reg.scala 27:20] wire [1:0] _T_23105 = _T_22754 ? bht_bank_rd_data_out_0_161 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23360 = _T_23359 | _T_23105; // @[Mux.scala 27:72] - wire _T_22756 = bht_rd_addr_hashed_p1_f == 8'ha2; // @[ifu_bp_ctl.scala 455:85] + wire _T_22756 = bht_rd_addr_hashed_p1_f == 8'ha2; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_162; // @[Reg.scala 27:20] wire [1:0] _T_23106 = _T_22756 ? bht_bank_rd_data_out_0_162 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23361 = _T_23360 | _T_23106; // @[Mux.scala 27:72] - wire _T_22758 = bht_rd_addr_hashed_p1_f == 8'ha3; // @[ifu_bp_ctl.scala 455:85] + wire _T_22758 = bht_rd_addr_hashed_p1_f == 8'ha3; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_163; // @[Reg.scala 27:20] wire [1:0] _T_23107 = _T_22758 ? bht_bank_rd_data_out_0_163 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23362 = _T_23361 | _T_23107; // @[Mux.scala 27:72] - wire _T_22760 = bht_rd_addr_hashed_p1_f == 8'ha4; // @[ifu_bp_ctl.scala 455:85] + wire _T_22760 = bht_rd_addr_hashed_p1_f == 8'ha4; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_164; // @[Reg.scala 27:20] wire [1:0] _T_23108 = _T_22760 ? bht_bank_rd_data_out_0_164 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23363 = _T_23362 | _T_23108; // @[Mux.scala 27:72] - wire _T_22762 = bht_rd_addr_hashed_p1_f == 8'ha5; // @[ifu_bp_ctl.scala 455:85] + wire _T_22762 = bht_rd_addr_hashed_p1_f == 8'ha5; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_165; // @[Reg.scala 27:20] wire [1:0] _T_23109 = _T_22762 ? bht_bank_rd_data_out_0_165 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23364 = _T_23363 | _T_23109; // @[Mux.scala 27:72] - wire _T_22764 = bht_rd_addr_hashed_p1_f == 8'ha6; // @[ifu_bp_ctl.scala 455:85] + wire _T_22764 = bht_rd_addr_hashed_p1_f == 8'ha6; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_166; // @[Reg.scala 27:20] wire [1:0] _T_23110 = _T_22764 ? bht_bank_rd_data_out_0_166 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23365 = _T_23364 | _T_23110; // @[Mux.scala 27:72] - wire _T_22766 = bht_rd_addr_hashed_p1_f == 8'ha7; // @[ifu_bp_ctl.scala 455:85] + wire _T_22766 = bht_rd_addr_hashed_p1_f == 8'ha7; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_167; // @[Reg.scala 27:20] wire [1:0] _T_23111 = _T_22766 ? bht_bank_rd_data_out_0_167 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23366 = _T_23365 | _T_23111; // @[Mux.scala 27:72] - wire _T_22768 = bht_rd_addr_hashed_p1_f == 8'ha8; // @[ifu_bp_ctl.scala 455:85] + wire _T_22768 = bht_rd_addr_hashed_p1_f == 8'ha8; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_168; // @[Reg.scala 27:20] wire [1:0] _T_23112 = _T_22768 ? bht_bank_rd_data_out_0_168 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23367 = _T_23366 | _T_23112; // @[Mux.scala 27:72] - wire _T_22770 = bht_rd_addr_hashed_p1_f == 8'ha9; // @[ifu_bp_ctl.scala 455:85] + wire _T_22770 = bht_rd_addr_hashed_p1_f == 8'ha9; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_169; // @[Reg.scala 27:20] wire [1:0] _T_23113 = _T_22770 ? bht_bank_rd_data_out_0_169 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23368 = _T_23367 | _T_23113; // @[Mux.scala 27:72] - wire _T_22772 = bht_rd_addr_hashed_p1_f == 8'haa; // @[ifu_bp_ctl.scala 455:85] + wire _T_22772 = bht_rd_addr_hashed_p1_f == 8'haa; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_170; // @[Reg.scala 27:20] wire [1:0] _T_23114 = _T_22772 ? bht_bank_rd_data_out_0_170 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23369 = _T_23368 | _T_23114; // @[Mux.scala 27:72] - wire _T_22774 = bht_rd_addr_hashed_p1_f == 8'hab; // @[ifu_bp_ctl.scala 455:85] + wire _T_22774 = bht_rd_addr_hashed_p1_f == 8'hab; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_171; // @[Reg.scala 27:20] wire [1:0] _T_23115 = _T_22774 ? bht_bank_rd_data_out_0_171 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23370 = _T_23369 | _T_23115; // @[Mux.scala 27:72] - wire _T_22776 = bht_rd_addr_hashed_p1_f == 8'hac; // @[ifu_bp_ctl.scala 455:85] + wire _T_22776 = bht_rd_addr_hashed_p1_f == 8'hac; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_172; // @[Reg.scala 27:20] wire [1:0] _T_23116 = _T_22776 ? bht_bank_rd_data_out_0_172 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23371 = _T_23370 | _T_23116; // @[Mux.scala 27:72] - wire _T_22778 = bht_rd_addr_hashed_p1_f == 8'had; // @[ifu_bp_ctl.scala 455:85] + wire _T_22778 = bht_rd_addr_hashed_p1_f == 8'had; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_173; // @[Reg.scala 27:20] wire [1:0] _T_23117 = _T_22778 ? bht_bank_rd_data_out_0_173 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23372 = _T_23371 | _T_23117; // @[Mux.scala 27:72] - wire _T_22780 = bht_rd_addr_hashed_p1_f == 8'hae; // @[ifu_bp_ctl.scala 455:85] + wire _T_22780 = bht_rd_addr_hashed_p1_f == 8'hae; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_174; // @[Reg.scala 27:20] wire [1:0] _T_23118 = _T_22780 ? bht_bank_rd_data_out_0_174 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23373 = _T_23372 | _T_23118; // @[Mux.scala 27:72] - wire _T_22782 = bht_rd_addr_hashed_p1_f == 8'haf; // @[ifu_bp_ctl.scala 455:85] + wire _T_22782 = bht_rd_addr_hashed_p1_f == 8'haf; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_175; // @[Reg.scala 27:20] wire [1:0] _T_23119 = _T_22782 ? bht_bank_rd_data_out_0_175 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23374 = _T_23373 | _T_23119; // @[Mux.scala 27:72] - wire _T_22784 = bht_rd_addr_hashed_p1_f == 8'hb0; // @[ifu_bp_ctl.scala 455:85] + wire _T_22784 = bht_rd_addr_hashed_p1_f == 8'hb0; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_176; // @[Reg.scala 27:20] wire [1:0] _T_23120 = _T_22784 ? bht_bank_rd_data_out_0_176 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23375 = _T_23374 | _T_23120; // @[Mux.scala 27:72] - wire _T_22786 = bht_rd_addr_hashed_p1_f == 8'hb1; // @[ifu_bp_ctl.scala 455:85] + wire _T_22786 = bht_rd_addr_hashed_p1_f == 8'hb1; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_177; // @[Reg.scala 27:20] wire [1:0] _T_23121 = _T_22786 ? bht_bank_rd_data_out_0_177 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23376 = _T_23375 | _T_23121; // @[Mux.scala 27:72] - wire _T_22788 = bht_rd_addr_hashed_p1_f == 8'hb2; // @[ifu_bp_ctl.scala 455:85] + wire _T_22788 = bht_rd_addr_hashed_p1_f == 8'hb2; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_178; // @[Reg.scala 27:20] wire [1:0] _T_23122 = _T_22788 ? bht_bank_rd_data_out_0_178 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23377 = _T_23376 | _T_23122; // @[Mux.scala 27:72] - wire _T_22790 = bht_rd_addr_hashed_p1_f == 8'hb3; // @[ifu_bp_ctl.scala 455:85] + wire _T_22790 = bht_rd_addr_hashed_p1_f == 8'hb3; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_179; // @[Reg.scala 27:20] wire [1:0] _T_23123 = _T_22790 ? bht_bank_rd_data_out_0_179 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23378 = _T_23377 | _T_23123; // @[Mux.scala 27:72] - wire _T_22792 = bht_rd_addr_hashed_p1_f == 8'hb4; // @[ifu_bp_ctl.scala 455:85] + wire _T_22792 = bht_rd_addr_hashed_p1_f == 8'hb4; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_180; // @[Reg.scala 27:20] wire [1:0] _T_23124 = _T_22792 ? bht_bank_rd_data_out_0_180 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23379 = _T_23378 | _T_23124; // @[Mux.scala 27:72] - wire _T_22794 = bht_rd_addr_hashed_p1_f == 8'hb5; // @[ifu_bp_ctl.scala 455:85] + wire _T_22794 = bht_rd_addr_hashed_p1_f == 8'hb5; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_181; // @[Reg.scala 27:20] wire [1:0] _T_23125 = _T_22794 ? bht_bank_rd_data_out_0_181 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23380 = _T_23379 | _T_23125; // @[Mux.scala 27:72] - wire _T_22796 = bht_rd_addr_hashed_p1_f == 8'hb6; // @[ifu_bp_ctl.scala 455:85] + wire _T_22796 = bht_rd_addr_hashed_p1_f == 8'hb6; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_182; // @[Reg.scala 27:20] wire [1:0] _T_23126 = _T_22796 ? bht_bank_rd_data_out_0_182 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23381 = _T_23380 | _T_23126; // @[Mux.scala 27:72] - wire _T_22798 = bht_rd_addr_hashed_p1_f == 8'hb7; // @[ifu_bp_ctl.scala 455:85] + wire _T_22798 = bht_rd_addr_hashed_p1_f == 8'hb7; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_183; // @[Reg.scala 27:20] wire [1:0] _T_23127 = _T_22798 ? bht_bank_rd_data_out_0_183 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23382 = _T_23381 | _T_23127; // @[Mux.scala 27:72] - wire _T_22800 = bht_rd_addr_hashed_p1_f == 8'hb8; // @[ifu_bp_ctl.scala 455:85] + wire _T_22800 = bht_rd_addr_hashed_p1_f == 8'hb8; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_184; // @[Reg.scala 27:20] wire [1:0] _T_23128 = _T_22800 ? bht_bank_rd_data_out_0_184 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23383 = _T_23382 | _T_23128; // @[Mux.scala 27:72] - wire _T_22802 = bht_rd_addr_hashed_p1_f == 8'hb9; // @[ifu_bp_ctl.scala 455:85] + wire _T_22802 = bht_rd_addr_hashed_p1_f == 8'hb9; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_185; // @[Reg.scala 27:20] wire [1:0] _T_23129 = _T_22802 ? bht_bank_rd_data_out_0_185 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23384 = _T_23383 | _T_23129; // @[Mux.scala 27:72] - wire _T_22804 = bht_rd_addr_hashed_p1_f == 8'hba; // @[ifu_bp_ctl.scala 455:85] + wire _T_22804 = bht_rd_addr_hashed_p1_f == 8'hba; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_186; // @[Reg.scala 27:20] wire [1:0] _T_23130 = _T_22804 ? bht_bank_rd_data_out_0_186 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23385 = _T_23384 | _T_23130; // @[Mux.scala 27:72] - wire _T_22806 = bht_rd_addr_hashed_p1_f == 8'hbb; // @[ifu_bp_ctl.scala 455:85] + wire _T_22806 = bht_rd_addr_hashed_p1_f == 8'hbb; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_187; // @[Reg.scala 27:20] wire [1:0] _T_23131 = _T_22806 ? bht_bank_rd_data_out_0_187 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23386 = _T_23385 | _T_23131; // @[Mux.scala 27:72] - wire _T_22808 = bht_rd_addr_hashed_p1_f == 8'hbc; // @[ifu_bp_ctl.scala 455:85] + wire _T_22808 = bht_rd_addr_hashed_p1_f == 8'hbc; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_188; // @[Reg.scala 27:20] wire [1:0] _T_23132 = _T_22808 ? bht_bank_rd_data_out_0_188 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23387 = _T_23386 | _T_23132; // @[Mux.scala 27:72] - wire _T_22810 = bht_rd_addr_hashed_p1_f == 8'hbd; // @[ifu_bp_ctl.scala 455:85] + wire _T_22810 = bht_rd_addr_hashed_p1_f == 8'hbd; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_189; // @[Reg.scala 27:20] wire [1:0] _T_23133 = _T_22810 ? bht_bank_rd_data_out_0_189 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23388 = _T_23387 | _T_23133; // @[Mux.scala 27:72] - wire _T_22812 = bht_rd_addr_hashed_p1_f == 8'hbe; // @[ifu_bp_ctl.scala 455:85] + wire _T_22812 = bht_rd_addr_hashed_p1_f == 8'hbe; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_190; // @[Reg.scala 27:20] wire [1:0] _T_23134 = _T_22812 ? bht_bank_rd_data_out_0_190 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23389 = _T_23388 | _T_23134; // @[Mux.scala 27:72] - wire _T_22814 = bht_rd_addr_hashed_p1_f == 8'hbf; // @[ifu_bp_ctl.scala 455:85] + wire _T_22814 = bht_rd_addr_hashed_p1_f == 8'hbf; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_191; // @[Reg.scala 27:20] wire [1:0] _T_23135 = _T_22814 ? bht_bank_rd_data_out_0_191 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23390 = _T_23389 | _T_23135; // @[Mux.scala 27:72] - wire _T_22816 = bht_rd_addr_hashed_p1_f == 8'hc0; // @[ifu_bp_ctl.scala 455:85] + wire _T_22816 = bht_rd_addr_hashed_p1_f == 8'hc0; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_192; // @[Reg.scala 27:20] wire [1:0] _T_23136 = _T_22816 ? bht_bank_rd_data_out_0_192 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23391 = _T_23390 | _T_23136; // @[Mux.scala 27:72] - wire _T_22818 = bht_rd_addr_hashed_p1_f == 8'hc1; // @[ifu_bp_ctl.scala 455:85] + wire _T_22818 = bht_rd_addr_hashed_p1_f == 8'hc1; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_193; // @[Reg.scala 27:20] wire [1:0] _T_23137 = _T_22818 ? bht_bank_rd_data_out_0_193 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23392 = _T_23391 | _T_23137; // @[Mux.scala 27:72] - wire _T_22820 = bht_rd_addr_hashed_p1_f == 8'hc2; // @[ifu_bp_ctl.scala 455:85] + wire _T_22820 = bht_rd_addr_hashed_p1_f == 8'hc2; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_194; // @[Reg.scala 27:20] wire [1:0] _T_23138 = _T_22820 ? bht_bank_rd_data_out_0_194 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23393 = _T_23392 | _T_23138; // @[Mux.scala 27:72] - wire _T_22822 = bht_rd_addr_hashed_p1_f == 8'hc3; // @[ifu_bp_ctl.scala 455:85] + wire _T_22822 = bht_rd_addr_hashed_p1_f == 8'hc3; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_195; // @[Reg.scala 27:20] wire [1:0] _T_23139 = _T_22822 ? bht_bank_rd_data_out_0_195 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23394 = _T_23393 | _T_23139; // @[Mux.scala 27:72] - wire _T_22824 = bht_rd_addr_hashed_p1_f == 8'hc4; // @[ifu_bp_ctl.scala 455:85] + wire _T_22824 = bht_rd_addr_hashed_p1_f == 8'hc4; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_196; // @[Reg.scala 27:20] wire [1:0] _T_23140 = _T_22824 ? bht_bank_rd_data_out_0_196 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23395 = _T_23394 | _T_23140; // @[Mux.scala 27:72] - wire _T_22826 = bht_rd_addr_hashed_p1_f == 8'hc5; // @[ifu_bp_ctl.scala 455:85] + wire _T_22826 = bht_rd_addr_hashed_p1_f == 8'hc5; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_197; // @[Reg.scala 27:20] wire [1:0] _T_23141 = _T_22826 ? bht_bank_rd_data_out_0_197 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23396 = _T_23395 | _T_23141; // @[Mux.scala 27:72] - wire _T_22828 = bht_rd_addr_hashed_p1_f == 8'hc6; // @[ifu_bp_ctl.scala 455:85] + wire _T_22828 = bht_rd_addr_hashed_p1_f == 8'hc6; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_198; // @[Reg.scala 27:20] wire [1:0] _T_23142 = _T_22828 ? bht_bank_rd_data_out_0_198 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23397 = _T_23396 | _T_23142; // @[Mux.scala 27:72] - wire _T_22830 = bht_rd_addr_hashed_p1_f == 8'hc7; // @[ifu_bp_ctl.scala 455:85] + wire _T_22830 = bht_rd_addr_hashed_p1_f == 8'hc7; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_199; // @[Reg.scala 27:20] wire [1:0] _T_23143 = _T_22830 ? bht_bank_rd_data_out_0_199 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23398 = _T_23397 | _T_23143; // @[Mux.scala 27:72] - wire _T_22832 = bht_rd_addr_hashed_p1_f == 8'hc8; // @[ifu_bp_ctl.scala 455:85] + wire _T_22832 = bht_rd_addr_hashed_p1_f == 8'hc8; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_200; // @[Reg.scala 27:20] wire [1:0] _T_23144 = _T_22832 ? bht_bank_rd_data_out_0_200 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23399 = _T_23398 | _T_23144; // @[Mux.scala 27:72] - wire _T_22834 = bht_rd_addr_hashed_p1_f == 8'hc9; // @[ifu_bp_ctl.scala 455:85] + wire _T_22834 = bht_rd_addr_hashed_p1_f == 8'hc9; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_201; // @[Reg.scala 27:20] wire [1:0] _T_23145 = _T_22834 ? bht_bank_rd_data_out_0_201 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23400 = _T_23399 | _T_23145; // @[Mux.scala 27:72] - wire _T_22836 = bht_rd_addr_hashed_p1_f == 8'hca; // @[ifu_bp_ctl.scala 455:85] + wire _T_22836 = bht_rd_addr_hashed_p1_f == 8'hca; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_202; // @[Reg.scala 27:20] wire [1:0] _T_23146 = _T_22836 ? bht_bank_rd_data_out_0_202 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23401 = _T_23400 | _T_23146; // @[Mux.scala 27:72] - wire _T_22838 = bht_rd_addr_hashed_p1_f == 8'hcb; // @[ifu_bp_ctl.scala 455:85] + wire _T_22838 = bht_rd_addr_hashed_p1_f == 8'hcb; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_203; // @[Reg.scala 27:20] wire [1:0] _T_23147 = _T_22838 ? bht_bank_rd_data_out_0_203 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23402 = _T_23401 | _T_23147; // @[Mux.scala 27:72] - wire _T_22840 = bht_rd_addr_hashed_p1_f == 8'hcc; // @[ifu_bp_ctl.scala 455:85] + wire _T_22840 = bht_rd_addr_hashed_p1_f == 8'hcc; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_204; // @[Reg.scala 27:20] wire [1:0] _T_23148 = _T_22840 ? bht_bank_rd_data_out_0_204 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23403 = _T_23402 | _T_23148; // @[Mux.scala 27:72] - wire _T_22842 = bht_rd_addr_hashed_p1_f == 8'hcd; // @[ifu_bp_ctl.scala 455:85] + wire _T_22842 = bht_rd_addr_hashed_p1_f == 8'hcd; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_205; // @[Reg.scala 27:20] wire [1:0] _T_23149 = _T_22842 ? bht_bank_rd_data_out_0_205 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23404 = _T_23403 | _T_23149; // @[Mux.scala 27:72] - wire _T_22844 = bht_rd_addr_hashed_p1_f == 8'hce; // @[ifu_bp_ctl.scala 455:85] + wire _T_22844 = bht_rd_addr_hashed_p1_f == 8'hce; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_206; // @[Reg.scala 27:20] wire [1:0] _T_23150 = _T_22844 ? bht_bank_rd_data_out_0_206 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23405 = _T_23404 | _T_23150; // @[Mux.scala 27:72] - wire _T_22846 = bht_rd_addr_hashed_p1_f == 8'hcf; // @[ifu_bp_ctl.scala 455:85] + wire _T_22846 = bht_rd_addr_hashed_p1_f == 8'hcf; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_207; // @[Reg.scala 27:20] wire [1:0] _T_23151 = _T_22846 ? bht_bank_rd_data_out_0_207 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23406 = _T_23405 | _T_23151; // @[Mux.scala 27:72] - wire _T_22848 = bht_rd_addr_hashed_p1_f == 8'hd0; // @[ifu_bp_ctl.scala 455:85] + wire _T_22848 = bht_rd_addr_hashed_p1_f == 8'hd0; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_208; // @[Reg.scala 27:20] wire [1:0] _T_23152 = _T_22848 ? bht_bank_rd_data_out_0_208 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23407 = _T_23406 | _T_23152; // @[Mux.scala 27:72] - wire _T_22850 = bht_rd_addr_hashed_p1_f == 8'hd1; // @[ifu_bp_ctl.scala 455:85] + wire _T_22850 = bht_rd_addr_hashed_p1_f == 8'hd1; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_209; // @[Reg.scala 27:20] wire [1:0] _T_23153 = _T_22850 ? bht_bank_rd_data_out_0_209 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23408 = _T_23407 | _T_23153; // @[Mux.scala 27:72] - wire _T_22852 = bht_rd_addr_hashed_p1_f == 8'hd2; // @[ifu_bp_ctl.scala 455:85] + wire _T_22852 = bht_rd_addr_hashed_p1_f == 8'hd2; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_210; // @[Reg.scala 27:20] wire [1:0] _T_23154 = _T_22852 ? bht_bank_rd_data_out_0_210 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23409 = _T_23408 | _T_23154; // @[Mux.scala 27:72] - wire _T_22854 = bht_rd_addr_hashed_p1_f == 8'hd3; // @[ifu_bp_ctl.scala 455:85] + wire _T_22854 = bht_rd_addr_hashed_p1_f == 8'hd3; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_211; // @[Reg.scala 27:20] wire [1:0] _T_23155 = _T_22854 ? bht_bank_rd_data_out_0_211 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23410 = _T_23409 | _T_23155; // @[Mux.scala 27:72] - wire _T_22856 = bht_rd_addr_hashed_p1_f == 8'hd4; // @[ifu_bp_ctl.scala 455:85] + wire _T_22856 = bht_rd_addr_hashed_p1_f == 8'hd4; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_212; // @[Reg.scala 27:20] wire [1:0] _T_23156 = _T_22856 ? bht_bank_rd_data_out_0_212 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23411 = _T_23410 | _T_23156; // @[Mux.scala 27:72] - wire _T_22858 = bht_rd_addr_hashed_p1_f == 8'hd5; // @[ifu_bp_ctl.scala 455:85] + wire _T_22858 = bht_rd_addr_hashed_p1_f == 8'hd5; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_213; // @[Reg.scala 27:20] wire [1:0] _T_23157 = _T_22858 ? bht_bank_rd_data_out_0_213 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23412 = _T_23411 | _T_23157; // @[Mux.scala 27:72] - wire _T_22860 = bht_rd_addr_hashed_p1_f == 8'hd6; // @[ifu_bp_ctl.scala 455:85] + wire _T_22860 = bht_rd_addr_hashed_p1_f == 8'hd6; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_214; // @[Reg.scala 27:20] wire [1:0] _T_23158 = _T_22860 ? bht_bank_rd_data_out_0_214 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23413 = _T_23412 | _T_23158; // @[Mux.scala 27:72] - wire _T_22862 = bht_rd_addr_hashed_p1_f == 8'hd7; // @[ifu_bp_ctl.scala 455:85] + wire _T_22862 = bht_rd_addr_hashed_p1_f == 8'hd7; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_215; // @[Reg.scala 27:20] wire [1:0] _T_23159 = _T_22862 ? bht_bank_rd_data_out_0_215 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23414 = _T_23413 | _T_23159; // @[Mux.scala 27:72] - wire _T_22864 = bht_rd_addr_hashed_p1_f == 8'hd8; // @[ifu_bp_ctl.scala 455:85] + wire _T_22864 = bht_rd_addr_hashed_p1_f == 8'hd8; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_216; // @[Reg.scala 27:20] wire [1:0] _T_23160 = _T_22864 ? bht_bank_rd_data_out_0_216 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23415 = _T_23414 | _T_23160; // @[Mux.scala 27:72] - wire _T_22866 = bht_rd_addr_hashed_p1_f == 8'hd9; // @[ifu_bp_ctl.scala 455:85] + wire _T_22866 = bht_rd_addr_hashed_p1_f == 8'hd9; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_217; // @[Reg.scala 27:20] wire [1:0] _T_23161 = _T_22866 ? bht_bank_rd_data_out_0_217 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23416 = _T_23415 | _T_23161; // @[Mux.scala 27:72] - wire _T_22868 = bht_rd_addr_hashed_p1_f == 8'hda; // @[ifu_bp_ctl.scala 455:85] + wire _T_22868 = bht_rd_addr_hashed_p1_f == 8'hda; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_218; // @[Reg.scala 27:20] wire [1:0] _T_23162 = _T_22868 ? bht_bank_rd_data_out_0_218 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23417 = _T_23416 | _T_23162; // @[Mux.scala 27:72] - wire _T_22870 = bht_rd_addr_hashed_p1_f == 8'hdb; // @[ifu_bp_ctl.scala 455:85] + wire _T_22870 = bht_rd_addr_hashed_p1_f == 8'hdb; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_219; // @[Reg.scala 27:20] wire [1:0] _T_23163 = _T_22870 ? bht_bank_rd_data_out_0_219 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23418 = _T_23417 | _T_23163; // @[Mux.scala 27:72] - wire _T_22872 = bht_rd_addr_hashed_p1_f == 8'hdc; // @[ifu_bp_ctl.scala 455:85] + wire _T_22872 = bht_rd_addr_hashed_p1_f == 8'hdc; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_220; // @[Reg.scala 27:20] wire [1:0] _T_23164 = _T_22872 ? bht_bank_rd_data_out_0_220 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23419 = _T_23418 | _T_23164; // @[Mux.scala 27:72] - wire _T_22874 = bht_rd_addr_hashed_p1_f == 8'hdd; // @[ifu_bp_ctl.scala 455:85] + wire _T_22874 = bht_rd_addr_hashed_p1_f == 8'hdd; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_221; // @[Reg.scala 27:20] wire [1:0] _T_23165 = _T_22874 ? bht_bank_rd_data_out_0_221 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23420 = _T_23419 | _T_23165; // @[Mux.scala 27:72] - wire _T_22876 = bht_rd_addr_hashed_p1_f == 8'hde; // @[ifu_bp_ctl.scala 455:85] + wire _T_22876 = bht_rd_addr_hashed_p1_f == 8'hde; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_222; // @[Reg.scala 27:20] wire [1:0] _T_23166 = _T_22876 ? bht_bank_rd_data_out_0_222 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23421 = _T_23420 | _T_23166; // @[Mux.scala 27:72] - wire _T_22878 = bht_rd_addr_hashed_p1_f == 8'hdf; // @[ifu_bp_ctl.scala 455:85] + wire _T_22878 = bht_rd_addr_hashed_p1_f == 8'hdf; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_223; // @[Reg.scala 27:20] wire [1:0] _T_23167 = _T_22878 ? bht_bank_rd_data_out_0_223 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23422 = _T_23421 | _T_23167; // @[Mux.scala 27:72] - wire _T_22880 = bht_rd_addr_hashed_p1_f == 8'he0; // @[ifu_bp_ctl.scala 455:85] + wire _T_22880 = bht_rd_addr_hashed_p1_f == 8'he0; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_224; // @[Reg.scala 27:20] wire [1:0] _T_23168 = _T_22880 ? bht_bank_rd_data_out_0_224 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23423 = _T_23422 | _T_23168; // @[Mux.scala 27:72] - wire _T_22882 = bht_rd_addr_hashed_p1_f == 8'he1; // @[ifu_bp_ctl.scala 455:85] + wire _T_22882 = bht_rd_addr_hashed_p1_f == 8'he1; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_225; // @[Reg.scala 27:20] wire [1:0] _T_23169 = _T_22882 ? bht_bank_rd_data_out_0_225 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23424 = _T_23423 | _T_23169; // @[Mux.scala 27:72] - wire _T_22884 = bht_rd_addr_hashed_p1_f == 8'he2; // @[ifu_bp_ctl.scala 455:85] + wire _T_22884 = bht_rd_addr_hashed_p1_f == 8'he2; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_226; // @[Reg.scala 27:20] wire [1:0] _T_23170 = _T_22884 ? bht_bank_rd_data_out_0_226 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23425 = _T_23424 | _T_23170; // @[Mux.scala 27:72] - wire _T_22886 = bht_rd_addr_hashed_p1_f == 8'he3; // @[ifu_bp_ctl.scala 455:85] + wire _T_22886 = bht_rd_addr_hashed_p1_f == 8'he3; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_227; // @[Reg.scala 27:20] wire [1:0] _T_23171 = _T_22886 ? bht_bank_rd_data_out_0_227 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23426 = _T_23425 | _T_23171; // @[Mux.scala 27:72] - wire _T_22888 = bht_rd_addr_hashed_p1_f == 8'he4; // @[ifu_bp_ctl.scala 455:85] + wire _T_22888 = bht_rd_addr_hashed_p1_f == 8'he4; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_228; // @[Reg.scala 27:20] wire [1:0] _T_23172 = _T_22888 ? bht_bank_rd_data_out_0_228 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23427 = _T_23426 | _T_23172; // @[Mux.scala 27:72] - wire _T_22890 = bht_rd_addr_hashed_p1_f == 8'he5; // @[ifu_bp_ctl.scala 455:85] + wire _T_22890 = bht_rd_addr_hashed_p1_f == 8'he5; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_229; // @[Reg.scala 27:20] wire [1:0] _T_23173 = _T_22890 ? bht_bank_rd_data_out_0_229 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23428 = _T_23427 | _T_23173; // @[Mux.scala 27:72] - wire _T_22892 = bht_rd_addr_hashed_p1_f == 8'he6; // @[ifu_bp_ctl.scala 455:85] + wire _T_22892 = bht_rd_addr_hashed_p1_f == 8'he6; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_230; // @[Reg.scala 27:20] wire [1:0] _T_23174 = _T_22892 ? bht_bank_rd_data_out_0_230 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23429 = _T_23428 | _T_23174; // @[Mux.scala 27:72] - wire _T_22894 = bht_rd_addr_hashed_p1_f == 8'he7; // @[ifu_bp_ctl.scala 455:85] + wire _T_22894 = bht_rd_addr_hashed_p1_f == 8'he7; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_231; // @[Reg.scala 27:20] wire [1:0] _T_23175 = _T_22894 ? bht_bank_rd_data_out_0_231 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23430 = _T_23429 | _T_23175; // @[Mux.scala 27:72] - wire _T_22896 = bht_rd_addr_hashed_p1_f == 8'he8; // @[ifu_bp_ctl.scala 455:85] + wire _T_22896 = bht_rd_addr_hashed_p1_f == 8'he8; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_232; // @[Reg.scala 27:20] wire [1:0] _T_23176 = _T_22896 ? bht_bank_rd_data_out_0_232 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23431 = _T_23430 | _T_23176; // @[Mux.scala 27:72] - wire _T_22898 = bht_rd_addr_hashed_p1_f == 8'he9; // @[ifu_bp_ctl.scala 455:85] + wire _T_22898 = bht_rd_addr_hashed_p1_f == 8'he9; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_233; // @[Reg.scala 27:20] wire [1:0] _T_23177 = _T_22898 ? bht_bank_rd_data_out_0_233 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23432 = _T_23431 | _T_23177; // @[Mux.scala 27:72] - wire _T_22900 = bht_rd_addr_hashed_p1_f == 8'hea; // @[ifu_bp_ctl.scala 455:85] + wire _T_22900 = bht_rd_addr_hashed_p1_f == 8'hea; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_234; // @[Reg.scala 27:20] wire [1:0] _T_23178 = _T_22900 ? bht_bank_rd_data_out_0_234 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23433 = _T_23432 | _T_23178; // @[Mux.scala 27:72] - wire _T_22902 = bht_rd_addr_hashed_p1_f == 8'heb; // @[ifu_bp_ctl.scala 455:85] + wire _T_22902 = bht_rd_addr_hashed_p1_f == 8'heb; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_235; // @[Reg.scala 27:20] wire [1:0] _T_23179 = _T_22902 ? bht_bank_rd_data_out_0_235 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23434 = _T_23433 | _T_23179; // @[Mux.scala 27:72] - wire _T_22904 = bht_rd_addr_hashed_p1_f == 8'hec; // @[ifu_bp_ctl.scala 455:85] + wire _T_22904 = bht_rd_addr_hashed_p1_f == 8'hec; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_236; // @[Reg.scala 27:20] wire [1:0] _T_23180 = _T_22904 ? bht_bank_rd_data_out_0_236 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23435 = _T_23434 | _T_23180; // @[Mux.scala 27:72] - wire _T_22906 = bht_rd_addr_hashed_p1_f == 8'hed; // @[ifu_bp_ctl.scala 455:85] + wire _T_22906 = bht_rd_addr_hashed_p1_f == 8'hed; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_237; // @[Reg.scala 27:20] wire [1:0] _T_23181 = _T_22906 ? bht_bank_rd_data_out_0_237 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23436 = _T_23435 | _T_23181; // @[Mux.scala 27:72] - wire _T_22908 = bht_rd_addr_hashed_p1_f == 8'hee; // @[ifu_bp_ctl.scala 455:85] + wire _T_22908 = bht_rd_addr_hashed_p1_f == 8'hee; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_238; // @[Reg.scala 27:20] wire [1:0] _T_23182 = _T_22908 ? bht_bank_rd_data_out_0_238 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23437 = _T_23436 | _T_23182; // @[Mux.scala 27:72] - wire _T_22910 = bht_rd_addr_hashed_p1_f == 8'hef; // @[ifu_bp_ctl.scala 455:85] + wire _T_22910 = bht_rd_addr_hashed_p1_f == 8'hef; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_239; // @[Reg.scala 27:20] wire [1:0] _T_23183 = _T_22910 ? bht_bank_rd_data_out_0_239 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23438 = _T_23437 | _T_23183; // @[Mux.scala 27:72] - wire _T_22912 = bht_rd_addr_hashed_p1_f == 8'hf0; // @[ifu_bp_ctl.scala 455:85] + wire _T_22912 = bht_rd_addr_hashed_p1_f == 8'hf0; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_240; // @[Reg.scala 27:20] wire [1:0] _T_23184 = _T_22912 ? bht_bank_rd_data_out_0_240 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23439 = _T_23438 | _T_23184; // @[Mux.scala 27:72] - wire _T_22914 = bht_rd_addr_hashed_p1_f == 8'hf1; // @[ifu_bp_ctl.scala 455:85] + wire _T_22914 = bht_rd_addr_hashed_p1_f == 8'hf1; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_241; // @[Reg.scala 27:20] wire [1:0] _T_23185 = _T_22914 ? bht_bank_rd_data_out_0_241 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23440 = _T_23439 | _T_23185; // @[Mux.scala 27:72] - wire _T_22916 = bht_rd_addr_hashed_p1_f == 8'hf2; // @[ifu_bp_ctl.scala 455:85] + wire _T_22916 = bht_rd_addr_hashed_p1_f == 8'hf2; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_242; // @[Reg.scala 27:20] wire [1:0] _T_23186 = _T_22916 ? bht_bank_rd_data_out_0_242 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23441 = _T_23440 | _T_23186; // @[Mux.scala 27:72] - wire _T_22918 = bht_rd_addr_hashed_p1_f == 8'hf3; // @[ifu_bp_ctl.scala 455:85] + wire _T_22918 = bht_rd_addr_hashed_p1_f == 8'hf3; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_243; // @[Reg.scala 27:20] wire [1:0] _T_23187 = _T_22918 ? bht_bank_rd_data_out_0_243 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23442 = _T_23441 | _T_23187; // @[Mux.scala 27:72] - wire _T_22920 = bht_rd_addr_hashed_p1_f == 8'hf4; // @[ifu_bp_ctl.scala 455:85] + wire _T_22920 = bht_rd_addr_hashed_p1_f == 8'hf4; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_244; // @[Reg.scala 27:20] wire [1:0] _T_23188 = _T_22920 ? bht_bank_rd_data_out_0_244 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23443 = _T_23442 | _T_23188; // @[Mux.scala 27:72] - wire _T_22922 = bht_rd_addr_hashed_p1_f == 8'hf5; // @[ifu_bp_ctl.scala 455:85] + wire _T_22922 = bht_rd_addr_hashed_p1_f == 8'hf5; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_245; // @[Reg.scala 27:20] wire [1:0] _T_23189 = _T_22922 ? bht_bank_rd_data_out_0_245 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23444 = _T_23443 | _T_23189; // @[Mux.scala 27:72] - wire _T_22924 = bht_rd_addr_hashed_p1_f == 8'hf6; // @[ifu_bp_ctl.scala 455:85] + wire _T_22924 = bht_rd_addr_hashed_p1_f == 8'hf6; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_246; // @[Reg.scala 27:20] wire [1:0] _T_23190 = _T_22924 ? bht_bank_rd_data_out_0_246 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23445 = _T_23444 | _T_23190; // @[Mux.scala 27:72] - wire _T_22926 = bht_rd_addr_hashed_p1_f == 8'hf7; // @[ifu_bp_ctl.scala 455:85] + wire _T_22926 = bht_rd_addr_hashed_p1_f == 8'hf7; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_247; // @[Reg.scala 27:20] wire [1:0] _T_23191 = _T_22926 ? bht_bank_rd_data_out_0_247 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23446 = _T_23445 | _T_23191; // @[Mux.scala 27:72] - wire _T_22928 = bht_rd_addr_hashed_p1_f == 8'hf8; // @[ifu_bp_ctl.scala 455:85] + wire _T_22928 = bht_rd_addr_hashed_p1_f == 8'hf8; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_248; // @[Reg.scala 27:20] wire [1:0] _T_23192 = _T_22928 ? bht_bank_rd_data_out_0_248 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23447 = _T_23446 | _T_23192; // @[Mux.scala 27:72] - wire _T_22930 = bht_rd_addr_hashed_p1_f == 8'hf9; // @[ifu_bp_ctl.scala 455:85] + wire _T_22930 = bht_rd_addr_hashed_p1_f == 8'hf9; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_249; // @[Reg.scala 27:20] wire [1:0] _T_23193 = _T_22930 ? bht_bank_rd_data_out_0_249 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23448 = _T_23447 | _T_23193; // @[Mux.scala 27:72] - wire _T_22932 = bht_rd_addr_hashed_p1_f == 8'hfa; // @[ifu_bp_ctl.scala 455:85] + wire _T_22932 = bht_rd_addr_hashed_p1_f == 8'hfa; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_250; // @[Reg.scala 27:20] wire [1:0] _T_23194 = _T_22932 ? bht_bank_rd_data_out_0_250 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23449 = _T_23448 | _T_23194; // @[Mux.scala 27:72] - wire _T_22934 = bht_rd_addr_hashed_p1_f == 8'hfb; // @[ifu_bp_ctl.scala 455:85] + wire _T_22934 = bht_rd_addr_hashed_p1_f == 8'hfb; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_251; // @[Reg.scala 27:20] wire [1:0] _T_23195 = _T_22934 ? bht_bank_rd_data_out_0_251 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23450 = _T_23449 | _T_23195; // @[Mux.scala 27:72] - wire _T_22936 = bht_rd_addr_hashed_p1_f == 8'hfc; // @[ifu_bp_ctl.scala 455:85] + wire _T_22936 = bht_rd_addr_hashed_p1_f == 8'hfc; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_252; // @[Reg.scala 27:20] wire [1:0] _T_23196 = _T_22936 ? bht_bank_rd_data_out_0_252 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23451 = _T_23450 | _T_23196; // @[Mux.scala 27:72] - wire _T_22938 = bht_rd_addr_hashed_p1_f == 8'hfd; // @[ifu_bp_ctl.scala 455:85] + wire _T_22938 = bht_rd_addr_hashed_p1_f == 8'hfd; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_253; // @[Reg.scala 27:20] wire [1:0] _T_23197 = _T_22938 ? bht_bank_rd_data_out_0_253 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23452 = _T_23451 | _T_23197; // @[Mux.scala 27:72] - wire _T_22940 = bht_rd_addr_hashed_p1_f == 8'hfe; // @[ifu_bp_ctl.scala 455:85] + wire _T_22940 = bht_rd_addr_hashed_p1_f == 8'hfe; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_254; // @[Reg.scala 27:20] wire [1:0] _T_23198 = _T_22940 ? bht_bank_rd_data_out_0_254 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_23453 = _T_23452 | _T_23198; // @[Mux.scala 27:72] - wire _T_22942 = bht_rd_addr_hashed_p1_f == 8'hff; // @[ifu_bp_ctl.scala 455:85] + wire _T_22942 = bht_rd_addr_hashed_p1_f == 8'hff; // @[ifu_bp_ctl.scala 456:85] reg [1:0] bht_bank_rd_data_out_0_255; // @[Reg.scala 27:20] wire [1:0] _T_23199 = _T_22942 ? bht_bank_rd_data_out_0_255 : 2'h0; // @[Mux.scala 27:72] wire [1:0] bht_bank0_rd_data_p1_f = _T_23453 | _T_23199; // @[Mux.scala 27:72] wire [1:0] _T_261 = io_ifc_fetch_addr_f[0] ? bht_bank0_rd_data_p1_f : 2'h0; // @[Mux.scala 27:72] wire [1:0] bht_vbank1_rd_data_f = _T_260 | _T_261; // @[Mux.scala 27:72] - wire _T_265 = bht_force_taken_f[1] | bht_vbank1_rd_data_f[1]; // @[ifu_bp_ctl.scala 280:42] - wire [1:0] wayhit_f = tag_match_way0_expanded_f | tag_match_way1_expanded_f; // @[ifu_bp_ctl.scala 154:44] + wire _T_265 = bht_force_taken_f[1] | bht_vbank1_rd_data_f[1]; // @[ifu_bp_ctl.scala 281:42] + wire [1:0] wayhit_f = tag_match_way0_expanded_f | tag_match_way1_expanded_f; // @[ifu_bp_ctl.scala 155:44] wire [1:0] _T_159 = _T_144 ? wayhit_f : 2'h0; // @[Mux.scala 27:72] - wire [1:0] wayhit_p1_f = tag_match_way0_expanded_p1_f | tag_match_way1_expanded_p1_f; // @[ifu_bp_ctl.scala 156:50] + wire [1:0] wayhit_p1_f = tag_match_way0_expanded_p1_f | tag_match_way1_expanded_p1_f; // @[ifu_bp_ctl.scala 157:50] wire [1:0] _T_158 = {wayhit_p1_f[0],wayhit_f[1]}; // @[Cat.scala 29:58] wire [1:0] _T_160 = io_ifc_fetch_addr_f[0] ? _T_158 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_161 = _T_159 | _T_160; // @[Mux.scala 27:72] - wire eoc_near = &io_ifc_fetch_addr_f[4:2]; // @[ifu_bp_ctl.scala 240:64] - wire _T_219 = ~eoc_near; // @[ifu_bp_ctl.scala 243:15] - wire [1:0] _T_221 = ~io_ifc_fetch_addr_f[1:0]; // @[ifu_bp_ctl.scala 243:28] - wire _T_222 = |_T_221; // @[ifu_bp_ctl.scala 243:58] - wire eoc_mask = _T_219 | _T_222; // @[ifu_bp_ctl.scala 243:25] + wire eoc_near = &io_ifc_fetch_addr_f[4:2]; // @[ifu_bp_ctl.scala 241:64] + wire _T_219 = ~eoc_near; // @[ifu_bp_ctl.scala 244:15] + wire [1:0] _T_221 = ~io_ifc_fetch_addr_f[1:0]; // @[ifu_bp_ctl.scala 244:28] + wire _T_222 = |_T_221; // @[ifu_bp_ctl.scala 244:58] + wire eoc_mask = _T_219 | _T_222; // @[ifu_bp_ctl.scala 244:25] wire [1:0] _T_163 = {eoc_mask,1'h1}; // @[Cat.scala 29:58] - wire [1:0] bht_valid_f = _T_161 & _T_163; // @[ifu_bp_ctl.scala 202:71] - wire _T_267 = _T_265 & bht_valid_f[1]; // @[ifu_bp_ctl.scala 280:69] + wire [1:0] bht_valid_f = _T_161 & _T_163; // @[ifu_bp_ctl.scala 203:71] + wire _T_267 = _T_265 & bht_valid_f[1]; // @[ifu_bp_ctl.scala 281:69] wire [1:0] _T_20896 = _T_21408 ? bht_bank_rd_data_out_0_0 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_20897 = _T_21410 ? bht_bank_rd_data_out_0_1 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_21152 = _T_20896 | _T_20897; // @[Mux.scala 27:72] @@ -20906,52 +20906,52 @@ module ifu_bp_ctl( wire [1:0] _T_252 = _T_144 ? bht_bank0_rd_data_f : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_253 = io_ifc_fetch_addr_f[0] ? bht_bank1_rd_data_f : 2'h0; // @[Mux.scala 27:72] wire [1:0] bht_vbank0_rd_data_f = _T_252 | _T_253; // @[Mux.scala 27:72] - wire _T_270 = bht_force_taken_f[0] | bht_vbank0_rd_data_f[1]; // @[ifu_bp_ctl.scala 281:45] - wire _T_272 = _T_270 & bht_valid_f[0]; // @[ifu_bp_ctl.scala 281:72] + wire _T_270 = bht_force_taken_f[0] | bht_vbank0_rd_data_f[1]; // @[ifu_bp_ctl.scala 282:45] + wire _T_272 = _T_270 & bht_valid_f[0]; // @[ifu_bp_ctl.scala 282:72] wire [1:0] bht_dir_f = {_T_267,_T_272}; // @[Cat.scala 29:58] - wire _T_14 = ~bht_dir_f[0]; // @[ifu_bp_ctl.scala 95:23] + wire _T_14 = ~bht_dir_f[0]; // @[ifu_bp_ctl.scala 96:23] wire [1:0] btb_sel_f = {_T_14,bht_dir_f[0]}; // @[Cat.scala 29:58] wire [1:0] fetch_start_f = {io_ifc_fetch_addr_f[0],_T_144}; // @[Cat.scala 29:58] - wire _T_32 = io_exu_bp_exu_mp_btag == fetch_rd_tag_f; // @[ifu_bp_ctl.scala 113:53] - wire _T_33 = _T_32 & exu_mp_valid; // @[ifu_bp_ctl.scala 113:73] - wire _T_34 = _T_33 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 113:88] - wire _T_35 = io_exu_bp_exu_mp_index == btb_rd_addr_f; // @[ifu_bp_ctl.scala 113:124] - wire fetch_mp_collision_f = _T_34 & _T_35; // @[ifu_bp_ctl.scala 113:109] - wire _T_36 = io_exu_bp_exu_mp_btag == fetch_rd_tag_p1_f; // @[ifu_bp_ctl.scala 114:56] - wire _T_37 = _T_36 & exu_mp_valid; // @[ifu_bp_ctl.scala 114:79] - wire _T_38 = _T_37 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 114:94] - wire _T_39 = io_exu_bp_exu_mp_index == btb_rd_addr_p1_f; // @[ifu_bp_ctl.scala 114:130] - wire fetch_mp_collision_p1_f = _T_38 & _T_39; // @[ifu_bp_ctl.scala 114:115] - reg exu_mp_way_f; // @[ifu_bp_ctl.scala 118:55] - reg exu_flush_final_d1; // @[ifu_bp_ctl.scala 119:61] - wire [255:0] mp_wrindex_dec = 256'h1 << io_exu_bp_exu_mp_index; // @[ifu_bp_ctl.scala 190:28] - wire [255:0] fetch_wrindex_dec = 256'h1 << btb_rd_addr_f; // @[ifu_bp_ctl.scala 193:31] - wire [255:0] fetch_wrindex_p1_dec = 256'h1 << btb_rd_addr_p1_f; // @[ifu_bp_ctl.scala 196:34] + wire _T_32 = io_exu_bp_exu_mp_btag == fetch_rd_tag_f; // @[ifu_bp_ctl.scala 114:53] + wire _T_33 = _T_32 & exu_mp_valid; // @[ifu_bp_ctl.scala 114:73] + wire _T_34 = _T_33 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 114:88] + wire _T_35 = io_exu_bp_exu_mp_index == btb_rd_addr_f; // @[ifu_bp_ctl.scala 114:124] + wire fetch_mp_collision_f = _T_34 & _T_35; // @[ifu_bp_ctl.scala 114:109] + wire _T_36 = io_exu_bp_exu_mp_btag == fetch_rd_tag_p1_f; // @[ifu_bp_ctl.scala 115:56] + wire _T_37 = _T_36 & exu_mp_valid; // @[ifu_bp_ctl.scala 115:79] + wire _T_38 = _T_37 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 115:94] + wire _T_39 = io_exu_bp_exu_mp_index == btb_rd_addr_p1_f; // @[ifu_bp_ctl.scala 115:130] + wire fetch_mp_collision_p1_f = _T_38 & _T_39; // @[ifu_bp_ctl.scala 115:115] + reg exu_mp_way_f; // @[ifu_bp_ctl.scala 119:55] + reg exu_flush_final_d1; // @[ifu_bp_ctl.scala 120:61] + wire [255:0] mp_wrindex_dec = 256'h1 << io_exu_bp_exu_mp_index; // @[ifu_bp_ctl.scala 191:28] + wire [255:0] fetch_wrindex_dec = 256'h1 << btb_rd_addr_f; // @[ifu_bp_ctl.scala 194:31] + wire [255:0] fetch_wrindex_p1_dec = 256'h1 << btb_rd_addr_p1_f; // @[ifu_bp_ctl.scala 197:34] wire [255:0] _T_150 = exu_mp_valid ? 256'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff : 256'h0; // @[Bitwise.scala 72:12] - wire [255:0] mp_wrlru_b0 = mp_wrindex_dec & _T_150; // @[ifu_bp_ctl.scala 199:36] - wire _T_166 = bht_valid_f[0] | bht_valid_f[1]; // @[ifu_bp_ctl.scala 205:42] - wire _T_167 = _T_166 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 205:58] - wire lru_update_valid_f = _T_167 & _T; // @[ifu_bp_ctl.scala 205:79] + wire [255:0] mp_wrlru_b0 = mp_wrindex_dec & _T_150; // @[ifu_bp_ctl.scala 200:36] + wire _T_166 = bht_valid_f[0] | bht_valid_f[1]; // @[ifu_bp_ctl.scala 206:42] + wire _T_167 = _T_166 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 206:58] + wire lru_update_valid_f = _T_167 & _T; // @[ifu_bp_ctl.scala 206:79] wire [255:0] _T_170 = lru_update_valid_f ? 256'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff : 256'h0; // @[Bitwise.scala 72:12] - wire [255:0] fetch_wrlru_b0 = fetch_wrindex_dec & _T_170; // @[ifu_bp_ctl.scala 207:42] - wire [255:0] fetch_wrlru_p1_b0 = fetch_wrindex_p1_dec & _T_170; // @[ifu_bp_ctl.scala 208:48] - wire [255:0] _T_173 = ~mp_wrlru_b0; // @[ifu_bp_ctl.scala 210:25] - wire [255:0] _T_174 = ~fetch_wrlru_b0; // @[ifu_bp_ctl.scala 210:40] - wire [255:0] btb_lru_b0_hold = _T_173 & _T_174; // @[ifu_bp_ctl.scala 210:38] - wire _T_176 = ~io_exu_bp_exu_mp_pkt_bits_way; // @[ifu_bp_ctl.scala 217:40] + wire [255:0] fetch_wrlru_b0 = fetch_wrindex_dec & _T_170; // @[ifu_bp_ctl.scala 208:42] + wire [255:0] fetch_wrlru_p1_b0 = fetch_wrindex_p1_dec & _T_170; // @[ifu_bp_ctl.scala 209:48] + wire [255:0] _T_173 = ~mp_wrlru_b0; // @[ifu_bp_ctl.scala 211:25] + wire [255:0] _T_174 = ~fetch_wrlru_b0; // @[ifu_bp_ctl.scala 211:40] + wire [255:0] btb_lru_b0_hold = _T_173 & _T_174; // @[ifu_bp_ctl.scala 211:38] + wire _T_176 = ~io_exu_bp_exu_mp_pkt_bits_way; // @[ifu_bp_ctl.scala 218:40] wire [255:0] _T_179 = _T_176 ? mp_wrlru_b0 : 256'h0; // @[Mux.scala 27:72] wire [255:0] _T_180 = tag_match_way0_f ? fetch_wrlru_b0 : 256'h0; // @[Mux.scala 27:72] wire [255:0] _T_181 = tag_match_way0_p1_f ? fetch_wrlru_p1_b0 : 256'h0; // @[Mux.scala 27:72] wire [255:0] _T_182 = _T_179 | _T_180; // @[Mux.scala 27:72] wire [255:0] _T_183 = _T_182 | _T_181; // @[Mux.scala 27:72] reg [255:0] btb_lru_b0_f; // @[lib.scala 358:16] - wire [255:0] _T_185 = btb_lru_b0_hold & btb_lru_b0_f; // @[ifu_bp_ctl.scala 219:102] - wire [255:0] _T_187 = fetch_wrindex_dec & btb_lru_b0_f; // @[ifu_bp_ctl.scala 222:78] - wire _T_188 = |_T_187; // @[ifu_bp_ctl.scala 222:94] - wire btb_lru_rd_f = fetch_mp_collision_f ? exu_mp_way_f : _T_188; // @[ifu_bp_ctl.scala 222:25] - wire [255:0] _T_190 = fetch_wrindex_p1_dec & btb_lru_b0_f; // @[ifu_bp_ctl.scala 224:87] - wire _T_191 = |_T_190; // @[ifu_bp_ctl.scala 224:103] - wire btb_lru_rd_p1_f = fetch_mp_collision_p1_f ? exu_mp_way_f : _T_191; // @[ifu_bp_ctl.scala 224:28] + wire [255:0] _T_185 = btb_lru_b0_hold & btb_lru_b0_f; // @[ifu_bp_ctl.scala 220:102] + wire [255:0] _T_187 = fetch_wrindex_dec & btb_lru_b0_f; // @[ifu_bp_ctl.scala 223:78] + wire _T_188 = |_T_187; // @[ifu_bp_ctl.scala 223:94] + wire btb_lru_rd_f = fetch_mp_collision_f ? exu_mp_way_f : _T_188; // @[ifu_bp_ctl.scala 223:25] + wire [255:0] _T_190 = fetch_wrindex_p1_dec & btb_lru_b0_f; // @[ifu_bp_ctl.scala 225:87] + wire _T_191 = |_T_190; // @[ifu_bp_ctl.scala 225:103] + wire btb_lru_rd_p1_f = fetch_mp_collision_p1_f ? exu_mp_way_f : _T_191; // @[ifu_bp_ctl.scala 225:28] wire [1:0] _T_194 = {btb_lru_rd_f,btb_lru_rd_f}; // @[Cat.scala 29:58] wire [1:0] _T_197 = {btb_lru_rd_p1_f,btb_lru_rd_f}; // @[Cat.scala 29:58] wire [1:0] _T_198 = _T_144 ? _T_194 : 2'h0; // @[Mux.scala 27:72] @@ -20961,79 +20961,79 @@ module ifu_bp_ctl( wire [1:0] _T_209 = _T_144 ? tag_match_way1_expanded_f : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_210 = io_ifc_fetch_addr_f[0] ? _T_208 : 2'h0; // @[Mux.scala 27:72] wire [1:0] tag_match_vway1_expanded_f = _T_209 | _T_210; // @[Mux.scala 27:72] - wire [1:0] _T_212 = ~bht_valid_f; // @[ifu_bp_ctl.scala 234:52] - wire [1:0] _T_213 = _T_212 & btb_vlru_rd_f; // @[ifu_bp_ctl.scala 234:63] + wire [1:0] _T_212 = ~bht_valid_f; // @[ifu_bp_ctl.scala 235:52] + wire [1:0] _T_213 = _T_212 & btb_vlru_rd_f; // @[ifu_bp_ctl.scala 235:63] wire [15:0] _T_230 = btb_sel_f[1] ? btb_vbank1_rd_data_f[16:1] : 16'h0; // @[Mux.scala 27:72] wire [15:0] _T_231 = btb_sel_f[0] ? btb_vbank0_rd_data_f[16:1] : 16'h0; // @[Mux.scala 27:72] wire [15:0] btb_sel_data_f = _T_230 | _T_231; // @[Mux.scala 27:72] - wire [11:0] btb_rd_tgt_f = btb_sel_data_f[15:4]; // @[ifu_bp_ctl.scala 250:36] - wire btb_rd_pc4_f = btb_sel_data_f[3]; // @[ifu_bp_ctl.scala 251:36] - wire btb_rd_call_f = btb_sel_data_f[1]; // @[ifu_bp_ctl.scala 252:37] - wire btb_rd_ret_f = btb_sel_data_f[0]; // @[ifu_bp_ctl.scala 253:36] + wire [11:0] btb_rd_tgt_f = btb_sel_data_f[15:4]; // @[ifu_bp_ctl.scala 251:36] + wire btb_rd_pc4_f = btb_sel_data_f[3]; // @[ifu_bp_ctl.scala 252:36] + wire btb_rd_call_f = btb_sel_data_f[1]; // @[ifu_bp_ctl.scala 253:37] + wire btb_rd_ret_f = btb_sel_data_f[0]; // @[ifu_bp_ctl.scala 254:36] wire [1:0] _T_280 = {bht_vbank1_rd_data_f[1],bht_vbank0_rd_data_f[1]}; // @[Cat.scala 29:58] - wire [1:0] hist1_raw = bht_force_taken_f | _T_280; // @[ifu_bp_ctl.scala 287:34] - wire [1:0] _T_234 = bht_valid_f & hist1_raw; // @[ifu_bp_ctl.scala 260:39] - wire _T_235 = |_T_234; // @[ifu_bp_ctl.scala 260:52] - wire _T_236 = _T_235 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 260:56] - wire _T_237 = ~leak_one_f_d1; // @[ifu_bp_ctl.scala 260:79] - wire _T_238 = _T_236 & _T_237; // @[ifu_bp_ctl.scala 260:77] - wire _T_239 = ~io_dec_bp_dec_tlu_bpred_disable; // @[ifu_bp_ctl.scala 260:96] - wire _T_275 = io_ifu_bp_hit_taken_f & btb_sel_f[1]; // @[ifu_bp_ctl.scala 284:51] - wire _T_276 = ~io_ifu_bp_hit_taken_f; // @[ifu_bp_ctl.scala 284:69] - wire _T_286 = bht_valid_f[1] & btb_vbank1_rd_data_f[4]; // @[ifu_bp_ctl.scala 293:34] - wire _T_289 = bht_valid_f[0] & btb_vbank0_rd_data_f[4]; // @[ifu_bp_ctl.scala 294:34] - wire _T_292 = ~btb_vbank1_rd_data_f[2]; // @[ifu_bp_ctl.scala 297:37] - wire _T_293 = bht_valid_f[1] & _T_292; // @[ifu_bp_ctl.scala 297:35] - wire _T_295 = _T_293 & btb_vbank1_rd_data_f[1]; // @[ifu_bp_ctl.scala 297:65] - wire _T_298 = ~btb_vbank0_rd_data_f[2]; // @[ifu_bp_ctl.scala 298:37] - wire _T_299 = bht_valid_f[0] & _T_298; // @[ifu_bp_ctl.scala 298:35] - wire _T_301 = _T_299 & btb_vbank0_rd_data_f[1]; // @[ifu_bp_ctl.scala 298:65] - wire [1:0] num_valids = bht_valid_f[1] + bht_valid_f[0]; // @[ifu_bp_ctl.scala 301:35] - wire [1:0] _T_304 = btb_sel_f & bht_dir_f; // @[ifu_bp_ctl.scala 304:28] - wire final_h = |_T_304; // @[ifu_bp_ctl.scala 304:41] - wire _T_305 = num_valids == 2'h2; // @[ifu_bp_ctl.scala 308:41] + wire [1:0] hist1_raw = bht_force_taken_f | _T_280; // @[ifu_bp_ctl.scala 288:34] + wire [1:0] _T_234 = bht_valid_f & hist1_raw; // @[ifu_bp_ctl.scala 261:39] + wire _T_235 = |_T_234; // @[ifu_bp_ctl.scala 261:52] + wire _T_236 = _T_235 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 261:56] + wire _T_237 = ~leak_one_f_d1; // @[ifu_bp_ctl.scala 261:79] + wire _T_238 = _T_236 & _T_237; // @[ifu_bp_ctl.scala 261:77] + wire _T_239 = ~io_dec_bp_dec_tlu_bpred_disable; // @[ifu_bp_ctl.scala 261:96] + wire _T_275 = io_ifu_bp_hit_taken_f & btb_sel_f[1]; // @[ifu_bp_ctl.scala 285:51] + wire _T_276 = ~io_ifu_bp_hit_taken_f; // @[ifu_bp_ctl.scala 285:69] + wire _T_286 = bht_valid_f[1] & btb_vbank1_rd_data_f[4]; // @[ifu_bp_ctl.scala 294:34] + wire _T_289 = bht_valid_f[0] & btb_vbank0_rd_data_f[4]; // @[ifu_bp_ctl.scala 295:34] + wire _T_292 = ~btb_vbank1_rd_data_f[2]; // @[ifu_bp_ctl.scala 298:37] + wire _T_293 = bht_valid_f[1] & _T_292; // @[ifu_bp_ctl.scala 298:35] + wire _T_295 = _T_293 & btb_vbank1_rd_data_f[1]; // @[ifu_bp_ctl.scala 298:65] + wire _T_298 = ~btb_vbank0_rd_data_f[2]; // @[ifu_bp_ctl.scala 299:37] + wire _T_299 = bht_valid_f[0] & _T_298; // @[ifu_bp_ctl.scala 299:35] + wire _T_301 = _T_299 & btb_vbank0_rd_data_f[1]; // @[ifu_bp_ctl.scala 299:65] + wire [1:0] num_valids = bht_valid_f[1] + bht_valid_f[0]; // @[ifu_bp_ctl.scala 302:35] + wire [1:0] _T_304 = btb_sel_f & bht_dir_f; // @[ifu_bp_ctl.scala 305:28] + wire final_h = |_T_304; // @[ifu_bp_ctl.scala 305:41] + wire _T_305 = num_valids == 2'h2; // @[ifu_bp_ctl.scala 309:41] wire [7:0] _T_309 = {fghr[5:0],1'h0,final_h}; // @[Cat.scala 29:58] - wire _T_310 = num_valids == 2'h1; // @[ifu_bp_ctl.scala 309:41] + wire _T_310 = num_valids == 2'h1; // @[ifu_bp_ctl.scala 310:41] wire [7:0] _T_313 = {fghr[6:0],final_h}; // @[Cat.scala 29:58] - wire _T_314 = num_valids == 2'h0; // @[ifu_bp_ctl.scala 310:41] + wire _T_314 = num_valids == 2'h0; // @[ifu_bp_ctl.scala 311:41] wire [7:0] _T_317 = _T_305 ? _T_309 : 8'h0; // @[Mux.scala 27:72] wire [7:0] _T_318 = _T_310 ? _T_313 : 8'h0; // @[Mux.scala 27:72] wire [7:0] _T_319 = _T_314 ? fghr : 8'h0; // @[Mux.scala 27:72] wire [7:0] _T_320 = _T_317 | _T_318; // @[Mux.scala 27:72] wire [7:0] merged_ghr = _T_320 | _T_319; // @[Mux.scala 27:72] - wire _T_323 = ~exu_flush_final_d1; // @[ifu_bp_ctl.scala 319:27] - wire _T_324 = _T_323 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 319:47] - wire _T_325 = _T_324 & io_ic_hit_f; // @[ifu_bp_ctl.scala 319:70] - wire _T_327 = _T_325 & _T_237; // @[ifu_bp_ctl.scala 319:84] - wire _T_330 = io_ifc_fetch_req_f & io_ic_hit_f; // @[ifu_bp_ctl.scala 320:70] - wire _T_332 = _T_330 & _T_237; // @[ifu_bp_ctl.scala 320:84] - wire _T_333 = ~_T_332; // @[ifu_bp_ctl.scala 320:49] - wire _T_334 = _T_323 & _T_333; // @[ifu_bp_ctl.scala 320:47] + wire _T_323 = ~exu_flush_final_d1; // @[ifu_bp_ctl.scala 320:27] + wire _T_324 = _T_323 & io_ifc_fetch_req_f; // @[ifu_bp_ctl.scala 320:47] + wire _T_325 = _T_324 & io_ic_hit_f; // @[ifu_bp_ctl.scala 320:70] + wire _T_327 = _T_325 & _T_237; // @[ifu_bp_ctl.scala 320:84] + wire _T_330 = io_ifc_fetch_req_f & io_ic_hit_f; // @[ifu_bp_ctl.scala 321:70] + wire _T_332 = _T_330 & _T_237; // @[ifu_bp_ctl.scala 321:84] + wire _T_333 = ~_T_332; // @[ifu_bp_ctl.scala 321:49] + wire _T_334 = _T_323 & _T_333; // @[ifu_bp_ctl.scala 321:47] wire [7:0] _T_336 = exu_flush_final_d1 ? io_exu_bp_exu_mp_fghr : 8'h0; // @[Mux.scala 27:72] wire [7:0] _T_337 = _T_327 ? merged_ghr : 8'h0; // @[Mux.scala 27:72] wire [7:0] _T_338 = _T_334 ? fghr : 8'h0; // @[Mux.scala 27:72] wire [7:0] _T_339 = _T_336 | _T_337; // @[Mux.scala 27:72] wire [1:0] _T_344 = io_dec_bp_dec_tlu_bpred_disable ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_345 = ~_T_344; // @[ifu_bp_ctl.scala 329:36] - wire _T_349 = ~fetch_start_f[0]; // @[ifu_bp_ctl.scala 333:36] - wire _T_350 = bht_dir_f[0] & _T_349; // @[ifu_bp_ctl.scala 333:34] - wire _T_354 = _T_14 & fetch_start_f[0]; // @[ifu_bp_ctl.scala 333:72] - wire _T_355 = _T_350 | _T_354; // @[ifu_bp_ctl.scala 333:55] - wire _T_358 = bht_dir_f[0] & fetch_start_f[0]; // @[ifu_bp_ctl.scala 334:34] - wire _T_363 = _T_14 & _T_349; // @[ifu_bp_ctl.scala 334:71] - wire _T_364 = _T_358 | _T_363; // @[ifu_bp_ctl.scala 334:54] + wire [1:0] _T_345 = ~_T_344; // @[ifu_bp_ctl.scala 330:36] + wire _T_349 = ~fetch_start_f[0]; // @[ifu_bp_ctl.scala 334:36] + wire _T_350 = bht_dir_f[0] & _T_349; // @[ifu_bp_ctl.scala 334:34] + wire _T_354 = _T_14 & fetch_start_f[0]; // @[ifu_bp_ctl.scala 334:72] + wire _T_355 = _T_350 | _T_354; // @[ifu_bp_ctl.scala 334:55] + wire _T_358 = bht_dir_f[0] & fetch_start_f[0]; // @[ifu_bp_ctl.scala 335:34] + wire _T_363 = _T_14 & _T_349; // @[ifu_bp_ctl.scala 335:71] + wire _T_364 = _T_358 | _T_363; // @[ifu_bp_ctl.scala 335:54] wire [1:0] bloc_f = {_T_355,_T_364}; // @[Cat.scala 29:58] - wire _T_368 = _T_14 & io_ifc_fetch_addr_f[0]; // @[ifu_bp_ctl.scala 336:35] - wire _T_369 = ~btb_rd_pc4_f; // @[ifu_bp_ctl.scala 336:62] - wire use_fa_plus = _T_368 & _T_369; // @[ifu_bp_ctl.scala 336:60] - wire _T_372 = fetch_start_f[0] & btb_sel_f[0]; // @[ifu_bp_ctl.scala 338:44] - wire btb_fg_crossing_f = _T_372 & btb_rd_pc4_f; // @[ifu_bp_ctl.scala 338:59] - wire bp_total_branch_offset_f = bloc_f[1] ^ btb_rd_pc4_f; // @[ifu_bp_ctl.scala 339:43] - wire _T_376 = io_ifc_fetch_req_f & _T_276; // @[ifu_bp_ctl.scala 341:85] + wire _T_368 = _T_14 & io_ifc_fetch_addr_f[0]; // @[ifu_bp_ctl.scala 337:35] + wire _T_369 = ~btb_rd_pc4_f; // @[ifu_bp_ctl.scala 337:62] + wire use_fa_plus = _T_368 & _T_369; // @[ifu_bp_ctl.scala 337:60] + wire _T_372 = fetch_start_f[0] & btb_sel_f[0]; // @[ifu_bp_ctl.scala 339:44] + wire btb_fg_crossing_f = _T_372 & btb_rd_pc4_f; // @[ifu_bp_ctl.scala 339:59] + wire bp_total_branch_offset_f = bloc_f[1] ^ btb_rd_pc4_f; // @[ifu_bp_ctl.scala 340:43] + wire _T_376 = io_ifc_fetch_req_f & _T_276; // @[ifu_bp_ctl.scala 342:85] reg [29:0] ifc_fetch_adder_prior; // @[lib.scala 358:16] - wire _T_381 = ~btb_fg_crossing_f; // @[ifu_bp_ctl.scala 347:32] - wire _T_382 = ~use_fa_plus; // @[ifu_bp_ctl.scala 347:53] - wire _T_383 = _T_381 & _T_382; // @[ifu_bp_ctl.scala 347:51] + wire _T_381 = ~btb_fg_crossing_f; // @[ifu_bp_ctl.scala 348:32] + wire _T_382 = ~use_fa_plus; // @[ifu_bp_ctl.scala 348:53] + wire _T_383 = _T_381 & _T_382; // @[ifu_bp_ctl.scala 348:51] wire [29:0] _T_386 = use_fa_plus ? fetch_addr_p1_f : 30'h0; // @[Mux.scala 27:72] wire [29:0] _T_387 = btb_fg_crossing_f ? ifc_fetch_adder_prior : 30'h0; // @[Mux.scala 27:72] wire [29:0] _T_388 = _T_383 ? io_ifc_fetch_addr_f[30:1] : 30'h0; // @[Mux.scala 27:72] @@ -21055,10 +21055,10 @@ module ifu_bp_ctl( wire [18:0] _T_421 = _T_418 | _T_419; // @[Mux.scala 27:72] wire [18:0] _T_422 = _T_421 | _T_420; // @[Mux.scala 27:72] wire [31:0] bp_btb_target_adder_f = {_T_422,_T_397[11:0],1'h0}; // @[Cat.scala 29:58] - wire _T_426 = ~btb_rd_call_f; // @[ifu_bp_ctl.scala 356:49] - wire _T_427 = btb_rd_ret_f & _T_426; // @[ifu_bp_ctl.scala 356:47] + wire _T_426 = ~btb_rd_call_f; // @[ifu_bp_ctl.scala 357:49] + wire _T_427 = btb_rd_ret_f & _T_426; // @[ifu_bp_ctl.scala 357:47] reg [31:0] rets_out_0; // @[lib.scala 358:16] - wire _T_429 = _T_427 & rets_out_0[0]; // @[ifu_bp_ctl.scala 356:64] + wire _T_429 = _T_427 & rets_out_0[0]; // @[ifu_bp_ctl.scala 357:64] wire [12:0] _T_440 = {11'h0,_T_369,1'h0}; // @[Cat.scala 29:58] wire [12:0] _T_443 = _T_393[12:1] + _T_440[12:1]; // @[lib.scala 52:31] wire _T_452 = ~_T_443[12]; // @[lib.scala 56:28] @@ -21072,13 +21072,13 @@ module ifu_bp_ctl( wire [18:0] _T_467 = _T_464 | _T_465; // @[Mux.scala 27:72] wire [18:0] _T_468 = _T_467 | _T_466; // @[Mux.scala 27:72] wire [31:0] bp_rs_call_target_f = {_T_468,_T_443[11:0],1'h0}; // @[Cat.scala 29:58] - wire _T_472 = ~btb_rd_ret_f; // @[ifu_bp_ctl.scala 362:33] - wire _T_473 = btb_rd_call_f & _T_472; // @[ifu_bp_ctl.scala 362:31] - wire rs_push = _T_473 & io_ifu_bp_hit_taken_f; // @[ifu_bp_ctl.scala 362:47] - wire rs_pop = _T_427 & io_ifu_bp_hit_taken_f; // @[ifu_bp_ctl.scala 363:46] - wire _T_476 = ~rs_push; // @[ifu_bp_ctl.scala 364:17] - wire _T_477 = ~rs_pop; // @[ifu_bp_ctl.scala 364:28] - wire rs_hold = _T_476 & _T_477; // @[ifu_bp_ctl.scala 364:26] + wire _T_472 = ~btb_rd_ret_f; // @[ifu_bp_ctl.scala 363:33] + wire _T_473 = btb_rd_call_f & _T_472; // @[ifu_bp_ctl.scala 363:31] + wire rs_push = _T_473 & io_ifu_bp_hit_taken_f; // @[ifu_bp_ctl.scala 363:47] + wire rs_pop = _T_427 & io_ifu_bp_hit_taken_f; // @[ifu_bp_ctl.scala 364:46] + wire _T_476 = ~rs_push; // @[ifu_bp_ctl.scala 365:17] + wire _T_477 = ~rs_pop; // @[ifu_bp_ctl.scala 365:28] + wire rs_hold = _T_476 & _T_477; // @[ifu_bp_ctl.scala 365:26] wire [31:0] _T_480 = {bp_rs_call_target_f[31:1],1'h1}; // @[Cat.scala 29:58] wire [31:0] _T_482 = rs_push ? _T_480 : 32'h0; // @[Mux.scala 27:72] reg [31:0] rets_out_1; // @[lib.scala 358:16] @@ -21101,2026 +21101,2026 @@ module ifu_bp_ctl( wire [31:0] _T_512 = rs_push ? rets_out_5 : 32'h0; // @[Mux.scala 27:72] reg [31:0] rets_out_7; // @[lib.scala 358:16] wire [31:0] _T_513 = rs_pop ? rets_out_7 : 32'h0; // @[Mux.scala 27:72] - wire _T_531 = ~dec_tlu_error_wb; // @[ifu_bp_ctl.scala 379:35] - wire btb_valid = exu_mp_valid & _T_531; // @[ifu_bp_ctl.scala 379:32] - wire _T_532 = io_exu_bp_exu_mp_pkt_bits_pcall | io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu_bp_ctl.scala 383:89] - wire _T_533 = io_exu_bp_exu_mp_pkt_bits_pret | io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu_bp_ctl.scala 383:113] + wire _T_531 = ~dec_tlu_error_wb; // @[ifu_bp_ctl.scala 380:35] + wire btb_valid = exu_mp_valid & _T_531; // @[ifu_bp_ctl.scala 380:32] + wire _T_532 = io_exu_bp_exu_mp_pkt_bits_pcall | io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu_bp_ctl.scala 384:89] + wire _T_533 = io_exu_bp_exu_mp_pkt_bits_pret | io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu_bp_ctl.scala 384:113] wire [2:0] _T_535 = {_T_532,_T_533,btb_valid}; // @[Cat.scala 29:58] wire [18:0] _T_538 = {io_exu_bp_exu_mp_btag,io_exu_bp_exu_mp_pkt_bits_toffset,io_exu_bp_exu_mp_pkt_bits_pc4,io_exu_bp_exu_mp_pkt_bits_boffset}; // @[Cat.scala 29:58] - wire exu_mp_valid_write = exu_mp_valid & io_exu_bp_exu_mp_pkt_bits_ataken; // @[ifu_bp_ctl.scala 384:41] - wire _T_540 = _T_176 & exu_mp_valid_write; // @[ifu_bp_ctl.scala 387:39] - wire _T_542 = _T_540 & _T_531; // @[ifu_bp_ctl.scala 387:60] - wire _T_543 = ~io_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[ifu_bp_ctl.scala 387:87] - wire _T_544 = _T_543 & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 387:104] - wire btb_wr_en_way0 = _T_542 | _T_544; // @[ifu_bp_ctl.scala 387:83] - wire _T_545 = io_exu_bp_exu_mp_pkt_bits_way & exu_mp_valid_write; // @[ifu_bp_ctl.scala 388:36] - wire _T_547 = _T_545 & _T_531; // @[ifu_bp_ctl.scala 388:57] - wire _T_548 = io_dec_bp_dec_tlu_br0_r_pkt_bits_way & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 388:98] - wire btb_wr_en_way1 = _T_547 | _T_548; // @[ifu_bp_ctl.scala 388:80] - wire [7:0] btb_wr_addr = dec_tlu_error_wb ? io_exu_bp_exu_i0_br_index_r : io_exu_bp_exu_mp_index; // @[ifu_bp_ctl.scala 391:24] - wire middle_of_bank = io_exu_bp_exu_mp_pkt_bits_pc4 ^ io_exu_bp_exu_mp_pkt_bits_boffset; // @[ifu_bp_ctl.scala 392:35] - wire _T_550 = ~io_exu_bp_exu_mp_pkt_bits_pcall; // @[ifu_bp_ctl.scala 395:43] - wire _T_551 = exu_mp_valid & _T_550; // @[ifu_bp_ctl.scala 395:41] - wire _T_552 = ~io_exu_bp_exu_mp_pkt_bits_pret; // @[ifu_bp_ctl.scala 395:58] - wire _T_553 = _T_551 & _T_552; // @[ifu_bp_ctl.scala 395:56] - wire _T_554 = ~io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu_bp_ctl.scala 395:72] - wire _T_555 = _T_553 & _T_554; // @[ifu_bp_ctl.scala 395:70] + wire exu_mp_valid_write = exu_mp_valid & io_exu_bp_exu_mp_pkt_bits_ataken; // @[ifu_bp_ctl.scala 385:41] + wire _T_540 = _T_176 & exu_mp_valid_write; // @[ifu_bp_ctl.scala 388:39] + wire _T_542 = _T_540 & _T_531; // @[ifu_bp_ctl.scala 388:60] + wire _T_543 = ~io_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[ifu_bp_ctl.scala 388:87] + wire _T_544 = _T_543 & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 388:104] + wire btb_wr_en_way0 = _T_542 | _T_544; // @[ifu_bp_ctl.scala 388:83] + wire _T_545 = io_exu_bp_exu_mp_pkt_bits_way & exu_mp_valid_write; // @[ifu_bp_ctl.scala 389:36] + wire _T_547 = _T_545 & _T_531; // @[ifu_bp_ctl.scala 389:57] + wire _T_548 = io_dec_bp_dec_tlu_br0_r_pkt_bits_way & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 389:98] + wire btb_wr_en_way1 = _T_547 | _T_548; // @[ifu_bp_ctl.scala 389:80] + wire [7:0] btb_wr_addr = dec_tlu_error_wb ? io_exu_bp_exu_i0_br_index_r : io_exu_bp_exu_mp_index; // @[ifu_bp_ctl.scala 392:24] + wire middle_of_bank = io_exu_bp_exu_mp_pkt_bits_pc4 ^ io_exu_bp_exu_mp_pkt_bits_boffset; // @[ifu_bp_ctl.scala 393:35] + wire _T_550 = ~io_exu_bp_exu_mp_pkt_bits_pcall; // @[ifu_bp_ctl.scala 396:43] + wire _T_551 = exu_mp_valid & _T_550; // @[ifu_bp_ctl.scala 396:41] + wire _T_552 = ~io_exu_bp_exu_mp_pkt_bits_pret; // @[ifu_bp_ctl.scala 396:58] + wire _T_553 = _T_551 & _T_552; // @[ifu_bp_ctl.scala 396:56] + wire _T_554 = ~io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu_bp_ctl.scala 396:72] + wire _T_555 = _T_553 & _T_554; // @[ifu_bp_ctl.scala 396:70] wire [1:0] _T_557 = _T_555 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_558 = ~middle_of_bank; // @[ifu_bp_ctl.scala 395:106] + wire _T_558 = ~middle_of_bank; // @[ifu_bp_ctl.scala 396:106] wire [1:0] _T_559 = {middle_of_bank,_T_558}; // @[Cat.scala 29:58] - wire [1:0] bht_wr_en0 = _T_557 & _T_559; // @[ifu_bp_ctl.scala 395:84] + wire [1:0] bht_wr_en0 = _T_557 & _T_559; // @[ifu_bp_ctl.scala 396:84] wire [1:0] _T_561 = io_dec_bp_dec_tlu_br0_r_pkt_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_562 = ~io_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[ifu_bp_ctl.scala 396:75] + wire _T_562 = ~io_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[ifu_bp_ctl.scala 397:75] wire [1:0] _T_563 = {io_dec_bp_dec_tlu_br0_r_pkt_bits_middle,_T_562}; // @[Cat.scala 29:58] - wire [1:0] bht_wr_en2 = _T_561 & _T_563; // @[ifu_bp_ctl.scala 396:46] + wire [1:0] bht_wr_en2 = _T_561 & _T_563; // @[ifu_bp_ctl.scala 397:46] wire [9:0] _T_564 = {io_exu_bp_exu_mp_index,2'h0}; // @[Cat.scala 29:58] wire [7:0] bht_wr_addr0 = _T_564[9:2] ^ io_exu_bp_exu_mp_eghr; // @[lib.scala 40:35] wire [9:0] _T_567 = {io_exu_bp_exu_i0_br_index_r,2'h0}; // @[Cat.scala 29:58] wire [7:0] bht_wr_addr2 = _T_567[9:2] ^ io_exu_bp_exu_i0_br_fghr_r; // @[lib.scala 40:35] - wire _T_576 = btb_wr_addr == 8'h0; // @[ifu_bp_ctl.scala 414:95] - wire _T_579 = btb_wr_addr == 8'h1; // @[ifu_bp_ctl.scala 414:95] - wire _T_582 = btb_wr_addr == 8'h2; // @[ifu_bp_ctl.scala 414:95] - wire _T_585 = btb_wr_addr == 8'h3; // @[ifu_bp_ctl.scala 414:95] - wire _T_588 = btb_wr_addr == 8'h4; // @[ifu_bp_ctl.scala 414:95] - wire _T_591 = btb_wr_addr == 8'h5; // @[ifu_bp_ctl.scala 414:95] - wire _T_594 = btb_wr_addr == 8'h6; // @[ifu_bp_ctl.scala 414:95] - wire _T_597 = btb_wr_addr == 8'h7; // @[ifu_bp_ctl.scala 414:95] - wire _T_600 = btb_wr_addr == 8'h8; // @[ifu_bp_ctl.scala 414:95] - wire _T_603 = btb_wr_addr == 8'h9; // @[ifu_bp_ctl.scala 414:95] - wire _T_606 = btb_wr_addr == 8'ha; // @[ifu_bp_ctl.scala 414:95] - wire _T_609 = btb_wr_addr == 8'hb; // @[ifu_bp_ctl.scala 414:95] - wire _T_612 = btb_wr_addr == 8'hc; // @[ifu_bp_ctl.scala 414:95] - wire _T_615 = btb_wr_addr == 8'hd; // @[ifu_bp_ctl.scala 414:95] - wire _T_618 = btb_wr_addr == 8'he; // @[ifu_bp_ctl.scala 414:95] - wire _T_621 = btb_wr_addr == 8'hf; // @[ifu_bp_ctl.scala 414:95] - wire _T_624 = btb_wr_addr == 8'h10; // @[ifu_bp_ctl.scala 414:95] - wire _T_627 = btb_wr_addr == 8'h11; // @[ifu_bp_ctl.scala 414:95] - wire _T_630 = btb_wr_addr == 8'h12; // @[ifu_bp_ctl.scala 414:95] - wire _T_633 = btb_wr_addr == 8'h13; // @[ifu_bp_ctl.scala 414:95] - wire _T_636 = btb_wr_addr == 8'h14; // @[ifu_bp_ctl.scala 414:95] - wire _T_639 = btb_wr_addr == 8'h15; // @[ifu_bp_ctl.scala 414:95] - wire _T_642 = btb_wr_addr == 8'h16; // @[ifu_bp_ctl.scala 414:95] - wire _T_645 = btb_wr_addr == 8'h17; // @[ifu_bp_ctl.scala 414:95] - wire _T_648 = btb_wr_addr == 8'h18; // @[ifu_bp_ctl.scala 414:95] - wire _T_651 = btb_wr_addr == 8'h19; // @[ifu_bp_ctl.scala 414:95] - wire _T_654 = btb_wr_addr == 8'h1a; // @[ifu_bp_ctl.scala 414:95] - wire _T_657 = btb_wr_addr == 8'h1b; // @[ifu_bp_ctl.scala 414:95] - wire _T_660 = btb_wr_addr == 8'h1c; // @[ifu_bp_ctl.scala 414:95] - wire _T_663 = btb_wr_addr == 8'h1d; // @[ifu_bp_ctl.scala 414:95] - wire _T_666 = btb_wr_addr == 8'h1e; // @[ifu_bp_ctl.scala 414:95] - wire _T_669 = btb_wr_addr == 8'h1f; // @[ifu_bp_ctl.scala 414:95] - wire _T_672 = btb_wr_addr == 8'h20; // @[ifu_bp_ctl.scala 414:95] - wire _T_675 = btb_wr_addr == 8'h21; // @[ifu_bp_ctl.scala 414:95] - wire _T_678 = btb_wr_addr == 8'h22; // @[ifu_bp_ctl.scala 414:95] - wire _T_681 = btb_wr_addr == 8'h23; // @[ifu_bp_ctl.scala 414:95] - wire _T_684 = btb_wr_addr == 8'h24; // @[ifu_bp_ctl.scala 414:95] - wire _T_687 = btb_wr_addr == 8'h25; // @[ifu_bp_ctl.scala 414:95] - wire _T_690 = btb_wr_addr == 8'h26; // @[ifu_bp_ctl.scala 414:95] - wire _T_693 = btb_wr_addr == 8'h27; // @[ifu_bp_ctl.scala 414:95] - wire _T_696 = btb_wr_addr == 8'h28; // @[ifu_bp_ctl.scala 414:95] - wire _T_699 = btb_wr_addr == 8'h29; // @[ifu_bp_ctl.scala 414:95] - wire _T_702 = btb_wr_addr == 8'h2a; // @[ifu_bp_ctl.scala 414:95] - wire _T_705 = btb_wr_addr == 8'h2b; // @[ifu_bp_ctl.scala 414:95] - wire _T_708 = btb_wr_addr == 8'h2c; // @[ifu_bp_ctl.scala 414:95] - wire _T_711 = btb_wr_addr == 8'h2d; // @[ifu_bp_ctl.scala 414:95] - wire _T_714 = btb_wr_addr == 8'h2e; // @[ifu_bp_ctl.scala 414:95] - wire _T_717 = btb_wr_addr == 8'h2f; // @[ifu_bp_ctl.scala 414:95] - wire _T_720 = btb_wr_addr == 8'h30; // @[ifu_bp_ctl.scala 414:95] - wire _T_723 = btb_wr_addr == 8'h31; // @[ifu_bp_ctl.scala 414:95] - wire _T_726 = btb_wr_addr == 8'h32; // @[ifu_bp_ctl.scala 414:95] - wire _T_729 = btb_wr_addr == 8'h33; // @[ifu_bp_ctl.scala 414:95] - wire _T_732 = btb_wr_addr == 8'h34; // @[ifu_bp_ctl.scala 414:95] - wire _T_735 = btb_wr_addr == 8'h35; // @[ifu_bp_ctl.scala 414:95] - wire _T_738 = btb_wr_addr == 8'h36; // @[ifu_bp_ctl.scala 414:95] - wire _T_741 = btb_wr_addr == 8'h37; // @[ifu_bp_ctl.scala 414:95] - wire _T_744 = btb_wr_addr == 8'h38; // @[ifu_bp_ctl.scala 414:95] - wire _T_747 = btb_wr_addr == 8'h39; // @[ifu_bp_ctl.scala 414:95] - wire _T_750 = btb_wr_addr == 8'h3a; // @[ifu_bp_ctl.scala 414:95] - wire _T_753 = btb_wr_addr == 8'h3b; // @[ifu_bp_ctl.scala 414:95] - wire _T_756 = btb_wr_addr == 8'h3c; // @[ifu_bp_ctl.scala 414:95] - wire _T_759 = btb_wr_addr == 8'h3d; // @[ifu_bp_ctl.scala 414:95] - wire _T_762 = btb_wr_addr == 8'h3e; // @[ifu_bp_ctl.scala 414:95] - wire _T_765 = btb_wr_addr == 8'h3f; // @[ifu_bp_ctl.scala 414:95] - wire _T_768 = btb_wr_addr == 8'h40; // @[ifu_bp_ctl.scala 414:95] - wire _T_771 = btb_wr_addr == 8'h41; // @[ifu_bp_ctl.scala 414:95] - wire _T_774 = btb_wr_addr == 8'h42; // @[ifu_bp_ctl.scala 414:95] - wire _T_777 = btb_wr_addr == 8'h43; // @[ifu_bp_ctl.scala 414:95] - wire _T_780 = btb_wr_addr == 8'h44; // @[ifu_bp_ctl.scala 414:95] - wire _T_783 = btb_wr_addr == 8'h45; // @[ifu_bp_ctl.scala 414:95] - wire _T_786 = btb_wr_addr == 8'h46; // @[ifu_bp_ctl.scala 414:95] - wire _T_789 = btb_wr_addr == 8'h47; // @[ifu_bp_ctl.scala 414:95] - wire _T_792 = btb_wr_addr == 8'h48; // @[ifu_bp_ctl.scala 414:95] - wire _T_795 = btb_wr_addr == 8'h49; // @[ifu_bp_ctl.scala 414:95] - wire _T_798 = btb_wr_addr == 8'h4a; // @[ifu_bp_ctl.scala 414:95] - wire _T_801 = btb_wr_addr == 8'h4b; // @[ifu_bp_ctl.scala 414:95] - wire _T_804 = btb_wr_addr == 8'h4c; // @[ifu_bp_ctl.scala 414:95] - wire _T_807 = btb_wr_addr == 8'h4d; // @[ifu_bp_ctl.scala 414:95] - wire _T_810 = btb_wr_addr == 8'h4e; // @[ifu_bp_ctl.scala 414:95] - wire _T_813 = btb_wr_addr == 8'h4f; // @[ifu_bp_ctl.scala 414:95] - wire _T_816 = btb_wr_addr == 8'h50; // @[ifu_bp_ctl.scala 414:95] - wire _T_819 = btb_wr_addr == 8'h51; // @[ifu_bp_ctl.scala 414:95] - wire _T_822 = btb_wr_addr == 8'h52; // @[ifu_bp_ctl.scala 414:95] - wire _T_825 = btb_wr_addr == 8'h53; // @[ifu_bp_ctl.scala 414:95] - wire _T_828 = btb_wr_addr == 8'h54; // @[ifu_bp_ctl.scala 414:95] - wire _T_831 = btb_wr_addr == 8'h55; // @[ifu_bp_ctl.scala 414:95] - wire _T_834 = btb_wr_addr == 8'h56; // @[ifu_bp_ctl.scala 414:95] - wire _T_837 = btb_wr_addr == 8'h57; // @[ifu_bp_ctl.scala 414:95] - wire _T_840 = btb_wr_addr == 8'h58; // @[ifu_bp_ctl.scala 414:95] - wire _T_843 = btb_wr_addr == 8'h59; // @[ifu_bp_ctl.scala 414:95] - wire _T_846 = btb_wr_addr == 8'h5a; // @[ifu_bp_ctl.scala 414:95] - wire _T_849 = btb_wr_addr == 8'h5b; // @[ifu_bp_ctl.scala 414:95] - wire _T_852 = btb_wr_addr == 8'h5c; // @[ifu_bp_ctl.scala 414:95] - wire _T_855 = btb_wr_addr == 8'h5d; // @[ifu_bp_ctl.scala 414:95] - wire _T_858 = btb_wr_addr == 8'h5e; // @[ifu_bp_ctl.scala 414:95] - wire _T_861 = btb_wr_addr == 8'h5f; // @[ifu_bp_ctl.scala 414:95] - wire _T_864 = btb_wr_addr == 8'h60; // @[ifu_bp_ctl.scala 414:95] - wire _T_867 = btb_wr_addr == 8'h61; // @[ifu_bp_ctl.scala 414:95] - wire _T_870 = btb_wr_addr == 8'h62; // @[ifu_bp_ctl.scala 414:95] - wire _T_873 = btb_wr_addr == 8'h63; // @[ifu_bp_ctl.scala 414:95] - wire _T_876 = btb_wr_addr == 8'h64; // @[ifu_bp_ctl.scala 414:95] - wire _T_879 = btb_wr_addr == 8'h65; // @[ifu_bp_ctl.scala 414:95] - wire _T_882 = btb_wr_addr == 8'h66; // @[ifu_bp_ctl.scala 414:95] - wire _T_885 = btb_wr_addr == 8'h67; // @[ifu_bp_ctl.scala 414:95] - wire _T_888 = btb_wr_addr == 8'h68; // @[ifu_bp_ctl.scala 414:95] - wire _T_891 = btb_wr_addr == 8'h69; // @[ifu_bp_ctl.scala 414:95] - wire _T_894 = btb_wr_addr == 8'h6a; // @[ifu_bp_ctl.scala 414:95] - wire _T_897 = btb_wr_addr == 8'h6b; // @[ifu_bp_ctl.scala 414:95] - wire _T_900 = btb_wr_addr == 8'h6c; // @[ifu_bp_ctl.scala 414:95] - wire _T_903 = btb_wr_addr == 8'h6d; // @[ifu_bp_ctl.scala 414:95] - wire _T_906 = btb_wr_addr == 8'h6e; // @[ifu_bp_ctl.scala 414:95] - wire _T_909 = btb_wr_addr == 8'h6f; // @[ifu_bp_ctl.scala 414:95] - wire _T_912 = btb_wr_addr == 8'h70; // @[ifu_bp_ctl.scala 414:95] - wire _T_915 = btb_wr_addr == 8'h71; // @[ifu_bp_ctl.scala 414:95] - wire _T_918 = btb_wr_addr == 8'h72; // @[ifu_bp_ctl.scala 414:95] - wire _T_921 = btb_wr_addr == 8'h73; // @[ifu_bp_ctl.scala 414:95] - wire _T_924 = btb_wr_addr == 8'h74; // @[ifu_bp_ctl.scala 414:95] - wire _T_927 = btb_wr_addr == 8'h75; // @[ifu_bp_ctl.scala 414:95] - wire _T_930 = btb_wr_addr == 8'h76; // @[ifu_bp_ctl.scala 414:95] - wire _T_933 = btb_wr_addr == 8'h77; // @[ifu_bp_ctl.scala 414:95] - wire _T_936 = btb_wr_addr == 8'h78; // @[ifu_bp_ctl.scala 414:95] - wire _T_939 = btb_wr_addr == 8'h79; // @[ifu_bp_ctl.scala 414:95] - wire _T_942 = btb_wr_addr == 8'h7a; // @[ifu_bp_ctl.scala 414:95] - wire _T_945 = btb_wr_addr == 8'h7b; // @[ifu_bp_ctl.scala 414:95] - wire _T_948 = btb_wr_addr == 8'h7c; // @[ifu_bp_ctl.scala 414:95] - wire _T_951 = btb_wr_addr == 8'h7d; // @[ifu_bp_ctl.scala 414:95] - wire _T_954 = btb_wr_addr == 8'h7e; // @[ifu_bp_ctl.scala 414:95] - wire _T_957 = btb_wr_addr == 8'h7f; // @[ifu_bp_ctl.scala 414:95] - wire _T_960 = btb_wr_addr == 8'h80; // @[ifu_bp_ctl.scala 414:95] - wire _T_963 = btb_wr_addr == 8'h81; // @[ifu_bp_ctl.scala 414:95] - wire _T_966 = btb_wr_addr == 8'h82; // @[ifu_bp_ctl.scala 414:95] - wire _T_969 = btb_wr_addr == 8'h83; // @[ifu_bp_ctl.scala 414:95] - wire _T_972 = btb_wr_addr == 8'h84; // @[ifu_bp_ctl.scala 414:95] - wire _T_975 = btb_wr_addr == 8'h85; // @[ifu_bp_ctl.scala 414:95] - wire _T_978 = btb_wr_addr == 8'h86; // @[ifu_bp_ctl.scala 414:95] - wire _T_981 = btb_wr_addr == 8'h87; // @[ifu_bp_ctl.scala 414:95] - wire _T_984 = btb_wr_addr == 8'h88; // @[ifu_bp_ctl.scala 414:95] - wire _T_987 = btb_wr_addr == 8'h89; // @[ifu_bp_ctl.scala 414:95] - wire _T_990 = btb_wr_addr == 8'h8a; // @[ifu_bp_ctl.scala 414:95] - wire _T_993 = btb_wr_addr == 8'h8b; // @[ifu_bp_ctl.scala 414:95] - wire _T_996 = btb_wr_addr == 8'h8c; // @[ifu_bp_ctl.scala 414:95] - wire _T_999 = btb_wr_addr == 8'h8d; // @[ifu_bp_ctl.scala 414:95] - wire _T_1002 = btb_wr_addr == 8'h8e; // @[ifu_bp_ctl.scala 414:95] - wire _T_1005 = btb_wr_addr == 8'h8f; // @[ifu_bp_ctl.scala 414:95] - wire _T_1008 = btb_wr_addr == 8'h90; // @[ifu_bp_ctl.scala 414:95] - wire _T_1011 = btb_wr_addr == 8'h91; // @[ifu_bp_ctl.scala 414:95] - wire _T_1014 = btb_wr_addr == 8'h92; // @[ifu_bp_ctl.scala 414:95] - wire _T_1017 = btb_wr_addr == 8'h93; // @[ifu_bp_ctl.scala 414:95] - wire _T_1020 = btb_wr_addr == 8'h94; // @[ifu_bp_ctl.scala 414:95] - wire _T_1023 = btb_wr_addr == 8'h95; // @[ifu_bp_ctl.scala 414:95] - wire _T_1026 = btb_wr_addr == 8'h96; // @[ifu_bp_ctl.scala 414:95] - wire _T_1029 = btb_wr_addr == 8'h97; // @[ifu_bp_ctl.scala 414:95] - wire _T_1032 = btb_wr_addr == 8'h98; // @[ifu_bp_ctl.scala 414:95] - wire _T_1035 = btb_wr_addr == 8'h99; // @[ifu_bp_ctl.scala 414:95] - wire _T_1038 = btb_wr_addr == 8'h9a; // @[ifu_bp_ctl.scala 414:95] - wire _T_1041 = btb_wr_addr == 8'h9b; // @[ifu_bp_ctl.scala 414:95] - wire _T_1044 = btb_wr_addr == 8'h9c; // @[ifu_bp_ctl.scala 414:95] - wire _T_1047 = btb_wr_addr == 8'h9d; // @[ifu_bp_ctl.scala 414:95] - wire _T_1050 = btb_wr_addr == 8'h9e; // @[ifu_bp_ctl.scala 414:95] - wire _T_1053 = btb_wr_addr == 8'h9f; // @[ifu_bp_ctl.scala 414:95] - wire _T_1056 = btb_wr_addr == 8'ha0; // @[ifu_bp_ctl.scala 414:95] - wire _T_1059 = btb_wr_addr == 8'ha1; // @[ifu_bp_ctl.scala 414:95] - wire _T_1062 = btb_wr_addr == 8'ha2; // @[ifu_bp_ctl.scala 414:95] - wire _T_1065 = btb_wr_addr == 8'ha3; // @[ifu_bp_ctl.scala 414:95] - wire _T_1068 = btb_wr_addr == 8'ha4; // @[ifu_bp_ctl.scala 414:95] - wire _T_1071 = btb_wr_addr == 8'ha5; // @[ifu_bp_ctl.scala 414:95] - wire _T_1074 = btb_wr_addr == 8'ha6; // @[ifu_bp_ctl.scala 414:95] - wire _T_1077 = btb_wr_addr == 8'ha7; // @[ifu_bp_ctl.scala 414:95] - wire _T_1080 = btb_wr_addr == 8'ha8; // @[ifu_bp_ctl.scala 414:95] - wire _T_1083 = btb_wr_addr == 8'ha9; // @[ifu_bp_ctl.scala 414:95] - wire _T_1086 = btb_wr_addr == 8'haa; // @[ifu_bp_ctl.scala 414:95] - wire _T_1089 = btb_wr_addr == 8'hab; // @[ifu_bp_ctl.scala 414:95] - wire _T_1092 = btb_wr_addr == 8'hac; // @[ifu_bp_ctl.scala 414:95] - wire _T_1095 = btb_wr_addr == 8'had; // @[ifu_bp_ctl.scala 414:95] - wire _T_1098 = btb_wr_addr == 8'hae; // @[ifu_bp_ctl.scala 414:95] - wire _T_1101 = btb_wr_addr == 8'haf; // @[ifu_bp_ctl.scala 414:95] - wire _T_1104 = btb_wr_addr == 8'hb0; // @[ifu_bp_ctl.scala 414:95] - wire _T_1107 = btb_wr_addr == 8'hb1; // @[ifu_bp_ctl.scala 414:95] - wire _T_1110 = btb_wr_addr == 8'hb2; // @[ifu_bp_ctl.scala 414:95] - wire _T_1113 = btb_wr_addr == 8'hb3; // @[ifu_bp_ctl.scala 414:95] - wire _T_1116 = btb_wr_addr == 8'hb4; // @[ifu_bp_ctl.scala 414:95] - wire _T_1119 = btb_wr_addr == 8'hb5; // @[ifu_bp_ctl.scala 414:95] - wire _T_1122 = btb_wr_addr == 8'hb6; // @[ifu_bp_ctl.scala 414:95] - wire _T_1125 = btb_wr_addr == 8'hb7; // @[ifu_bp_ctl.scala 414:95] - wire _T_1128 = btb_wr_addr == 8'hb8; // @[ifu_bp_ctl.scala 414:95] - wire _T_1131 = btb_wr_addr == 8'hb9; // @[ifu_bp_ctl.scala 414:95] - wire _T_1134 = btb_wr_addr == 8'hba; // @[ifu_bp_ctl.scala 414:95] - wire _T_1137 = btb_wr_addr == 8'hbb; // @[ifu_bp_ctl.scala 414:95] - wire _T_1140 = btb_wr_addr == 8'hbc; // @[ifu_bp_ctl.scala 414:95] - wire _T_1143 = btb_wr_addr == 8'hbd; // @[ifu_bp_ctl.scala 414:95] - wire _T_1146 = btb_wr_addr == 8'hbe; // @[ifu_bp_ctl.scala 414:95] - wire _T_1149 = btb_wr_addr == 8'hbf; // @[ifu_bp_ctl.scala 414:95] - wire _T_1152 = btb_wr_addr == 8'hc0; // @[ifu_bp_ctl.scala 414:95] - wire _T_1155 = btb_wr_addr == 8'hc1; // @[ifu_bp_ctl.scala 414:95] - wire _T_1158 = btb_wr_addr == 8'hc2; // @[ifu_bp_ctl.scala 414:95] - wire _T_1161 = btb_wr_addr == 8'hc3; // @[ifu_bp_ctl.scala 414:95] - wire _T_1164 = btb_wr_addr == 8'hc4; // @[ifu_bp_ctl.scala 414:95] - wire _T_1167 = btb_wr_addr == 8'hc5; // @[ifu_bp_ctl.scala 414:95] - wire _T_1170 = btb_wr_addr == 8'hc6; // @[ifu_bp_ctl.scala 414:95] - wire _T_1173 = btb_wr_addr == 8'hc7; // @[ifu_bp_ctl.scala 414:95] - wire _T_1176 = btb_wr_addr == 8'hc8; // @[ifu_bp_ctl.scala 414:95] - wire _T_1179 = btb_wr_addr == 8'hc9; // @[ifu_bp_ctl.scala 414:95] - wire _T_1182 = btb_wr_addr == 8'hca; // @[ifu_bp_ctl.scala 414:95] - wire _T_1185 = btb_wr_addr == 8'hcb; // @[ifu_bp_ctl.scala 414:95] - wire _T_1188 = btb_wr_addr == 8'hcc; // @[ifu_bp_ctl.scala 414:95] - wire _T_1191 = btb_wr_addr == 8'hcd; // @[ifu_bp_ctl.scala 414:95] - wire _T_1194 = btb_wr_addr == 8'hce; // @[ifu_bp_ctl.scala 414:95] - wire _T_1197 = btb_wr_addr == 8'hcf; // @[ifu_bp_ctl.scala 414:95] - wire _T_1200 = btb_wr_addr == 8'hd0; // @[ifu_bp_ctl.scala 414:95] - wire _T_1203 = btb_wr_addr == 8'hd1; // @[ifu_bp_ctl.scala 414:95] - wire _T_1206 = btb_wr_addr == 8'hd2; // @[ifu_bp_ctl.scala 414:95] - wire _T_1209 = btb_wr_addr == 8'hd3; // @[ifu_bp_ctl.scala 414:95] - wire _T_1212 = btb_wr_addr == 8'hd4; // @[ifu_bp_ctl.scala 414:95] - wire _T_1215 = btb_wr_addr == 8'hd5; // @[ifu_bp_ctl.scala 414:95] - wire _T_1218 = btb_wr_addr == 8'hd6; // @[ifu_bp_ctl.scala 414:95] - wire _T_1221 = btb_wr_addr == 8'hd7; // @[ifu_bp_ctl.scala 414:95] - wire _T_1224 = btb_wr_addr == 8'hd8; // @[ifu_bp_ctl.scala 414:95] - wire _T_1227 = btb_wr_addr == 8'hd9; // @[ifu_bp_ctl.scala 414:95] - wire _T_1230 = btb_wr_addr == 8'hda; // @[ifu_bp_ctl.scala 414:95] - wire _T_1233 = btb_wr_addr == 8'hdb; // @[ifu_bp_ctl.scala 414:95] - wire _T_1236 = btb_wr_addr == 8'hdc; // @[ifu_bp_ctl.scala 414:95] - wire _T_1239 = btb_wr_addr == 8'hdd; // @[ifu_bp_ctl.scala 414:95] - wire _T_1242 = btb_wr_addr == 8'hde; // @[ifu_bp_ctl.scala 414:95] - wire _T_1245 = btb_wr_addr == 8'hdf; // @[ifu_bp_ctl.scala 414:95] - wire _T_1248 = btb_wr_addr == 8'he0; // @[ifu_bp_ctl.scala 414:95] - wire _T_1251 = btb_wr_addr == 8'he1; // @[ifu_bp_ctl.scala 414:95] - wire _T_1254 = btb_wr_addr == 8'he2; // @[ifu_bp_ctl.scala 414:95] - wire _T_1257 = btb_wr_addr == 8'he3; // @[ifu_bp_ctl.scala 414:95] - wire _T_1260 = btb_wr_addr == 8'he4; // @[ifu_bp_ctl.scala 414:95] - wire _T_1263 = btb_wr_addr == 8'he5; // @[ifu_bp_ctl.scala 414:95] - wire _T_1266 = btb_wr_addr == 8'he6; // @[ifu_bp_ctl.scala 414:95] - wire _T_1269 = btb_wr_addr == 8'he7; // @[ifu_bp_ctl.scala 414:95] - wire _T_1272 = btb_wr_addr == 8'he8; // @[ifu_bp_ctl.scala 414:95] - wire _T_1275 = btb_wr_addr == 8'he9; // @[ifu_bp_ctl.scala 414:95] - wire _T_1278 = btb_wr_addr == 8'hea; // @[ifu_bp_ctl.scala 414:95] - wire _T_1281 = btb_wr_addr == 8'heb; // @[ifu_bp_ctl.scala 414:95] - wire _T_1284 = btb_wr_addr == 8'hec; // @[ifu_bp_ctl.scala 414:95] - wire _T_1287 = btb_wr_addr == 8'hed; // @[ifu_bp_ctl.scala 414:95] - wire _T_1290 = btb_wr_addr == 8'hee; // @[ifu_bp_ctl.scala 414:95] - wire _T_1293 = btb_wr_addr == 8'hef; // @[ifu_bp_ctl.scala 414:95] - wire _T_1296 = btb_wr_addr == 8'hf0; // @[ifu_bp_ctl.scala 414:95] - wire _T_1299 = btb_wr_addr == 8'hf1; // @[ifu_bp_ctl.scala 414:95] - wire _T_1302 = btb_wr_addr == 8'hf2; // @[ifu_bp_ctl.scala 414:95] - wire _T_1305 = btb_wr_addr == 8'hf3; // @[ifu_bp_ctl.scala 414:95] - wire _T_1308 = btb_wr_addr == 8'hf4; // @[ifu_bp_ctl.scala 414:95] - wire _T_1311 = btb_wr_addr == 8'hf5; // @[ifu_bp_ctl.scala 414:95] - wire _T_1314 = btb_wr_addr == 8'hf6; // @[ifu_bp_ctl.scala 414:95] - wire _T_1317 = btb_wr_addr == 8'hf7; // @[ifu_bp_ctl.scala 414:95] - wire _T_1320 = btb_wr_addr == 8'hf8; // @[ifu_bp_ctl.scala 414:95] - wire _T_1323 = btb_wr_addr == 8'hf9; // @[ifu_bp_ctl.scala 414:95] - wire _T_1326 = btb_wr_addr == 8'hfa; // @[ifu_bp_ctl.scala 414:95] - wire _T_1329 = btb_wr_addr == 8'hfb; // @[ifu_bp_ctl.scala 414:95] - wire _T_1332 = btb_wr_addr == 8'hfc; // @[ifu_bp_ctl.scala 414:95] - wire _T_1335 = btb_wr_addr == 8'hfd; // @[ifu_bp_ctl.scala 414:95] - wire _T_1338 = btb_wr_addr == 8'hfe; // @[ifu_bp_ctl.scala 414:95] - wire _T_1341 = btb_wr_addr == 8'hff; // @[ifu_bp_ctl.scala 414:95] - wire _T_6210 = bht_wr_addr0[7:4] == 4'h0; // @[ifu_bp_ctl.scala 428:109] - wire _T_6212 = bht_wr_en0[0] & _T_6210; // @[ifu_bp_ctl.scala 428:44] - wire _T_6215 = bht_wr_addr2[7:4] == 4'h0; // @[ifu_bp_ctl.scala 429:109] - wire _T_6217 = bht_wr_en2[0] & _T_6215; // @[ifu_bp_ctl.scala 429:44] - wire _T_6221 = bht_wr_addr0[7:4] == 4'h1; // @[ifu_bp_ctl.scala 428:109] - wire _T_6223 = bht_wr_en0[0] & _T_6221; // @[ifu_bp_ctl.scala 428:44] - wire _T_6226 = bht_wr_addr2[7:4] == 4'h1; // @[ifu_bp_ctl.scala 429:109] - wire _T_6228 = bht_wr_en2[0] & _T_6226; // @[ifu_bp_ctl.scala 429:44] - wire _T_6232 = bht_wr_addr0[7:4] == 4'h2; // @[ifu_bp_ctl.scala 428:109] - wire _T_6234 = bht_wr_en0[0] & _T_6232; // @[ifu_bp_ctl.scala 428:44] - wire _T_6237 = bht_wr_addr2[7:4] == 4'h2; // @[ifu_bp_ctl.scala 429:109] - wire _T_6239 = bht_wr_en2[0] & _T_6237; // @[ifu_bp_ctl.scala 429:44] - wire _T_6243 = bht_wr_addr0[7:4] == 4'h3; // @[ifu_bp_ctl.scala 428:109] - wire _T_6245 = bht_wr_en0[0] & _T_6243; // @[ifu_bp_ctl.scala 428:44] - wire _T_6248 = bht_wr_addr2[7:4] == 4'h3; // @[ifu_bp_ctl.scala 429:109] - wire _T_6250 = bht_wr_en2[0] & _T_6248; // @[ifu_bp_ctl.scala 429:44] - wire _T_6254 = bht_wr_addr0[7:4] == 4'h4; // @[ifu_bp_ctl.scala 428:109] - wire _T_6256 = bht_wr_en0[0] & _T_6254; // @[ifu_bp_ctl.scala 428:44] - wire _T_6259 = bht_wr_addr2[7:4] == 4'h4; // @[ifu_bp_ctl.scala 429:109] - wire _T_6261 = bht_wr_en2[0] & _T_6259; // @[ifu_bp_ctl.scala 429:44] - wire _T_6265 = bht_wr_addr0[7:4] == 4'h5; // @[ifu_bp_ctl.scala 428:109] - wire _T_6267 = bht_wr_en0[0] & _T_6265; // @[ifu_bp_ctl.scala 428:44] - wire _T_6270 = bht_wr_addr2[7:4] == 4'h5; // @[ifu_bp_ctl.scala 429:109] - wire _T_6272 = bht_wr_en2[0] & _T_6270; // @[ifu_bp_ctl.scala 429:44] - wire _T_6276 = bht_wr_addr0[7:4] == 4'h6; // @[ifu_bp_ctl.scala 428:109] - wire _T_6278 = bht_wr_en0[0] & _T_6276; // @[ifu_bp_ctl.scala 428:44] - wire _T_6281 = bht_wr_addr2[7:4] == 4'h6; // @[ifu_bp_ctl.scala 429:109] - wire _T_6283 = bht_wr_en2[0] & _T_6281; // @[ifu_bp_ctl.scala 429:44] - wire _T_6287 = bht_wr_addr0[7:4] == 4'h7; // @[ifu_bp_ctl.scala 428:109] - wire _T_6289 = bht_wr_en0[0] & _T_6287; // @[ifu_bp_ctl.scala 428:44] - wire _T_6292 = bht_wr_addr2[7:4] == 4'h7; // @[ifu_bp_ctl.scala 429:109] - wire _T_6294 = bht_wr_en2[0] & _T_6292; // @[ifu_bp_ctl.scala 429:44] - wire _T_6298 = bht_wr_addr0[7:4] == 4'h8; // @[ifu_bp_ctl.scala 428:109] - wire _T_6300 = bht_wr_en0[0] & _T_6298; // @[ifu_bp_ctl.scala 428:44] - wire _T_6303 = bht_wr_addr2[7:4] == 4'h8; // @[ifu_bp_ctl.scala 429:109] - wire _T_6305 = bht_wr_en2[0] & _T_6303; // @[ifu_bp_ctl.scala 429:44] - wire _T_6309 = bht_wr_addr0[7:4] == 4'h9; // @[ifu_bp_ctl.scala 428:109] - wire _T_6311 = bht_wr_en0[0] & _T_6309; // @[ifu_bp_ctl.scala 428:44] - wire _T_6314 = bht_wr_addr2[7:4] == 4'h9; // @[ifu_bp_ctl.scala 429:109] - wire _T_6316 = bht_wr_en2[0] & _T_6314; // @[ifu_bp_ctl.scala 429:44] - wire _T_6320 = bht_wr_addr0[7:4] == 4'ha; // @[ifu_bp_ctl.scala 428:109] - wire _T_6322 = bht_wr_en0[0] & _T_6320; // @[ifu_bp_ctl.scala 428:44] - wire _T_6325 = bht_wr_addr2[7:4] == 4'ha; // @[ifu_bp_ctl.scala 429:109] - wire _T_6327 = bht_wr_en2[0] & _T_6325; // @[ifu_bp_ctl.scala 429:44] - wire _T_6331 = bht_wr_addr0[7:4] == 4'hb; // @[ifu_bp_ctl.scala 428:109] - wire _T_6333 = bht_wr_en0[0] & _T_6331; // @[ifu_bp_ctl.scala 428:44] - wire _T_6336 = bht_wr_addr2[7:4] == 4'hb; // @[ifu_bp_ctl.scala 429:109] - wire _T_6338 = bht_wr_en2[0] & _T_6336; // @[ifu_bp_ctl.scala 429:44] - wire _T_6342 = bht_wr_addr0[7:4] == 4'hc; // @[ifu_bp_ctl.scala 428:109] - wire _T_6344 = bht_wr_en0[0] & _T_6342; // @[ifu_bp_ctl.scala 428:44] - wire _T_6347 = bht_wr_addr2[7:4] == 4'hc; // @[ifu_bp_ctl.scala 429:109] - wire _T_6349 = bht_wr_en2[0] & _T_6347; // @[ifu_bp_ctl.scala 429:44] - wire _T_6353 = bht_wr_addr0[7:4] == 4'hd; // @[ifu_bp_ctl.scala 428:109] - wire _T_6355 = bht_wr_en0[0] & _T_6353; // @[ifu_bp_ctl.scala 428:44] - wire _T_6358 = bht_wr_addr2[7:4] == 4'hd; // @[ifu_bp_ctl.scala 429:109] - wire _T_6360 = bht_wr_en2[0] & _T_6358; // @[ifu_bp_ctl.scala 429:44] - wire _T_6364 = bht_wr_addr0[7:4] == 4'he; // @[ifu_bp_ctl.scala 428:109] - wire _T_6366 = bht_wr_en0[0] & _T_6364; // @[ifu_bp_ctl.scala 428:44] - wire _T_6369 = bht_wr_addr2[7:4] == 4'he; // @[ifu_bp_ctl.scala 429:109] - wire _T_6371 = bht_wr_en2[0] & _T_6369; // @[ifu_bp_ctl.scala 429:44] - wire _T_6375 = bht_wr_addr0[7:4] == 4'hf; // @[ifu_bp_ctl.scala 428:109] - wire _T_6377 = bht_wr_en0[0] & _T_6375; // @[ifu_bp_ctl.scala 428:44] - wire _T_6380 = bht_wr_addr2[7:4] == 4'hf; // @[ifu_bp_ctl.scala 429:109] - wire _T_6382 = bht_wr_en2[0] & _T_6380; // @[ifu_bp_ctl.scala 429:44] - wire _T_6388 = bht_wr_en0[1] & _T_6210; // @[ifu_bp_ctl.scala 428:44] - wire _T_6393 = bht_wr_en2[1] & _T_6215; // @[ifu_bp_ctl.scala 429:44] - wire _T_6399 = bht_wr_en0[1] & _T_6221; // @[ifu_bp_ctl.scala 428:44] - wire _T_6404 = bht_wr_en2[1] & _T_6226; // @[ifu_bp_ctl.scala 429:44] - wire _T_6410 = bht_wr_en0[1] & _T_6232; // @[ifu_bp_ctl.scala 428:44] - wire _T_6415 = bht_wr_en2[1] & _T_6237; // @[ifu_bp_ctl.scala 429:44] - wire _T_6421 = bht_wr_en0[1] & _T_6243; // @[ifu_bp_ctl.scala 428:44] - wire _T_6426 = bht_wr_en2[1] & _T_6248; // @[ifu_bp_ctl.scala 429:44] - wire _T_6432 = bht_wr_en0[1] & _T_6254; // @[ifu_bp_ctl.scala 428:44] - wire _T_6437 = bht_wr_en2[1] & _T_6259; // @[ifu_bp_ctl.scala 429:44] - wire _T_6443 = bht_wr_en0[1] & _T_6265; // @[ifu_bp_ctl.scala 428:44] - wire _T_6448 = bht_wr_en2[1] & _T_6270; // @[ifu_bp_ctl.scala 429:44] - wire _T_6454 = bht_wr_en0[1] & _T_6276; // @[ifu_bp_ctl.scala 428:44] - wire _T_6459 = bht_wr_en2[1] & _T_6281; // @[ifu_bp_ctl.scala 429:44] - wire _T_6465 = bht_wr_en0[1] & _T_6287; // @[ifu_bp_ctl.scala 428:44] - wire _T_6470 = bht_wr_en2[1] & _T_6292; // @[ifu_bp_ctl.scala 429:44] - wire _T_6476 = bht_wr_en0[1] & _T_6298; // @[ifu_bp_ctl.scala 428:44] - wire _T_6481 = bht_wr_en2[1] & _T_6303; // @[ifu_bp_ctl.scala 429:44] - wire _T_6487 = bht_wr_en0[1] & _T_6309; // @[ifu_bp_ctl.scala 428:44] - wire _T_6492 = bht_wr_en2[1] & _T_6314; // @[ifu_bp_ctl.scala 429:44] - wire _T_6498 = bht_wr_en0[1] & _T_6320; // @[ifu_bp_ctl.scala 428:44] - wire _T_6503 = bht_wr_en2[1] & _T_6325; // @[ifu_bp_ctl.scala 429:44] - wire _T_6509 = bht_wr_en0[1] & _T_6331; // @[ifu_bp_ctl.scala 428:44] - wire _T_6514 = bht_wr_en2[1] & _T_6336; // @[ifu_bp_ctl.scala 429:44] - wire _T_6520 = bht_wr_en0[1] & _T_6342; // @[ifu_bp_ctl.scala 428:44] - wire _T_6525 = bht_wr_en2[1] & _T_6347; // @[ifu_bp_ctl.scala 429:44] - wire _T_6531 = bht_wr_en0[1] & _T_6353; // @[ifu_bp_ctl.scala 428:44] - wire _T_6536 = bht_wr_en2[1] & _T_6358; // @[ifu_bp_ctl.scala 429:44] - wire _T_6542 = bht_wr_en0[1] & _T_6364; // @[ifu_bp_ctl.scala 428:44] - wire _T_6547 = bht_wr_en2[1] & _T_6369; // @[ifu_bp_ctl.scala 429:44] - wire _T_6553 = bht_wr_en0[1] & _T_6375; // @[ifu_bp_ctl.scala 428:44] - wire _T_6558 = bht_wr_en2[1] & _T_6380; // @[ifu_bp_ctl.scala 429:44] - wire _T_6562 = bht_wr_addr2[3:0] == 4'h0; // @[ifu_bp_ctl.scala 434:74] - wire _T_6563 = bht_wr_en2[0] & _T_6562; // @[ifu_bp_ctl.scala 434:23] - wire _T_6566 = _T_6563 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_6571 = bht_wr_addr2[3:0] == 4'h1; // @[ifu_bp_ctl.scala 434:74] - wire _T_6572 = bht_wr_en2[0] & _T_6571; // @[ifu_bp_ctl.scala 434:23] - wire _T_6575 = _T_6572 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_6580 = bht_wr_addr2[3:0] == 4'h2; // @[ifu_bp_ctl.scala 434:74] - wire _T_6581 = bht_wr_en2[0] & _T_6580; // @[ifu_bp_ctl.scala 434:23] - wire _T_6584 = _T_6581 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_6589 = bht_wr_addr2[3:0] == 4'h3; // @[ifu_bp_ctl.scala 434:74] - wire _T_6590 = bht_wr_en2[0] & _T_6589; // @[ifu_bp_ctl.scala 434:23] - wire _T_6593 = _T_6590 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_6598 = bht_wr_addr2[3:0] == 4'h4; // @[ifu_bp_ctl.scala 434:74] - wire _T_6599 = bht_wr_en2[0] & _T_6598; // @[ifu_bp_ctl.scala 434:23] - wire _T_6602 = _T_6599 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_6607 = bht_wr_addr2[3:0] == 4'h5; // @[ifu_bp_ctl.scala 434:74] - wire _T_6608 = bht_wr_en2[0] & _T_6607; // @[ifu_bp_ctl.scala 434:23] - wire _T_6611 = _T_6608 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_6616 = bht_wr_addr2[3:0] == 4'h6; // @[ifu_bp_ctl.scala 434:74] - wire _T_6617 = bht_wr_en2[0] & _T_6616; // @[ifu_bp_ctl.scala 434:23] - wire _T_6620 = _T_6617 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_6625 = bht_wr_addr2[3:0] == 4'h7; // @[ifu_bp_ctl.scala 434:74] - wire _T_6626 = bht_wr_en2[0] & _T_6625; // @[ifu_bp_ctl.scala 434:23] - wire _T_6629 = _T_6626 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_6634 = bht_wr_addr2[3:0] == 4'h8; // @[ifu_bp_ctl.scala 434:74] - wire _T_6635 = bht_wr_en2[0] & _T_6634; // @[ifu_bp_ctl.scala 434:23] - wire _T_6638 = _T_6635 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_6643 = bht_wr_addr2[3:0] == 4'h9; // @[ifu_bp_ctl.scala 434:74] - wire _T_6644 = bht_wr_en2[0] & _T_6643; // @[ifu_bp_ctl.scala 434:23] - wire _T_6647 = _T_6644 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_6652 = bht_wr_addr2[3:0] == 4'ha; // @[ifu_bp_ctl.scala 434:74] - wire _T_6653 = bht_wr_en2[0] & _T_6652; // @[ifu_bp_ctl.scala 434:23] - wire _T_6656 = _T_6653 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_6661 = bht_wr_addr2[3:0] == 4'hb; // @[ifu_bp_ctl.scala 434:74] - wire _T_6662 = bht_wr_en2[0] & _T_6661; // @[ifu_bp_ctl.scala 434:23] - wire _T_6665 = _T_6662 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_6670 = bht_wr_addr2[3:0] == 4'hc; // @[ifu_bp_ctl.scala 434:74] - wire _T_6671 = bht_wr_en2[0] & _T_6670; // @[ifu_bp_ctl.scala 434:23] - wire _T_6674 = _T_6671 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_6679 = bht_wr_addr2[3:0] == 4'hd; // @[ifu_bp_ctl.scala 434:74] - wire _T_6680 = bht_wr_en2[0] & _T_6679; // @[ifu_bp_ctl.scala 434:23] - wire _T_6683 = _T_6680 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_6688 = bht_wr_addr2[3:0] == 4'he; // @[ifu_bp_ctl.scala 434:74] - wire _T_6689 = bht_wr_en2[0] & _T_6688; // @[ifu_bp_ctl.scala 434:23] - wire _T_6692 = _T_6689 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_6697 = bht_wr_addr2[3:0] == 4'hf; // @[ifu_bp_ctl.scala 434:74] - wire _T_6698 = bht_wr_en2[0] & _T_6697; // @[ifu_bp_ctl.scala 434:23] - wire _T_6701 = _T_6698 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_6710 = _T_6563 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_6719 = _T_6572 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_6728 = _T_6581 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_6737 = _T_6590 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_6746 = _T_6599 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_6755 = _T_6608 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_6764 = _T_6617 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_6773 = _T_6626 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_6782 = _T_6635 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_6791 = _T_6644 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_6800 = _T_6653 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_6809 = _T_6662 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_6818 = _T_6671 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_6827 = _T_6680 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_6836 = _T_6689 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_6845 = _T_6698 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_6854 = _T_6563 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_6863 = _T_6572 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_6872 = _T_6581 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_6881 = _T_6590 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_6890 = _T_6599 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_6899 = _T_6608 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_6908 = _T_6617 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_6917 = _T_6626 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_6926 = _T_6635 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_6935 = _T_6644 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_6944 = _T_6653 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_6953 = _T_6662 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_6962 = _T_6671 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_6971 = _T_6680 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_6980 = _T_6689 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_6989 = _T_6698 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_6998 = _T_6563 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_7007 = _T_6572 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_7016 = _T_6581 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_7025 = _T_6590 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_7034 = _T_6599 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_7043 = _T_6608 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_7052 = _T_6617 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_7061 = _T_6626 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_7070 = _T_6635 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_7079 = _T_6644 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_7088 = _T_6653 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_7097 = _T_6662 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_7106 = _T_6671 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_7115 = _T_6680 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_7124 = _T_6689 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_7133 = _T_6698 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_7142 = _T_6563 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_7151 = _T_6572 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_7160 = _T_6581 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_7169 = _T_6590 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_7178 = _T_6599 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_7187 = _T_6608 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_7196 = _T_6617 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_7205 = _T_6626 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_7214 = _T_6635 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_7223 = _T_6644 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_7232 = _T_6653 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_7241 = _T_6662 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_7250 = _T_6671 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_7259 = _T_6680 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_7268 = _T_6689 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_7277 = _T_6698 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_7286 = _T_6563 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_7295 = _T_6572 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_7304 = _T_6581 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_7313 = _T_6590 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_7322 = _T_6599 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_7331 = _T_6608 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_7340 = _T_6617 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_7349 = _T_6626 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_7358 = _T_6635 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_7367 = _T_6644 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_7376 = _T_6653 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_7385 = _T_6662 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_7394 = _T_6671 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_7403 = _T_6680 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_7412 = _T_6689 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_7421 = _T_6698 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_7430 = _T_6563 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_7439 = _T_6572 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_7448 = _T_6581 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_7457 = _T_6590 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_7466 = _T_6599 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_7475 = _T_6608 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_7484 = _T_6617 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_7493 = _T_6626 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_7502 = _T_6635 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_7511 = _T_6644 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_7520 = _T_6653 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_7529 = _T_6662 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_7538 = _T_6671 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_7547 = _T_6680 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_7556 = _T_6689 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_7565 = _T_6698 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_7574 = _T_6563 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_7583 = _T_6572 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_7592 = _T_6581 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_7601 = _T_6590 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_7610 = _T_6599 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_7619 = _T_6608 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_7628 = _T_6617 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_7637 = _T_6626 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_7646 = _T_6635 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_7655 = _T_6644 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_7664 = _T_6653 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_7673 = _T_6662 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_7682 = _T_6671 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_7691 = _T_6680 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_7700 = _T_6689 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_7709 = _T_6698 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_7718 = _T_6563 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_7727 = _T_6572 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_7736 = _T_6581 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_7745 = _T_6590 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_7754 = _T_6599 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_7763 = _T_6608 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_7772 = _T_6617 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_7781 = _T_6626 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_7790 = _T_6635 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_7799 = _T_6644 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_7808 = _T_6653 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_7817 = _T_6662 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_7826 = _T_6671 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_7835 = _T_6680 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_7844 = _T_6689 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_7853 = _T_6698 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_7862 = _T_6563 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_7871 = _T_6572 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_7880 = _T_6581 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_7889 = _T_6590 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_7898 = _T_6599 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_7907 = _T_6608 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_7916 = _T_6617 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_7925 = _T_6626 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_7934 = _T_6635 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_7943 = _T_6644 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_7952 = _T_6653 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_7961 = _T_6662 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_7970 = _T_6671 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_7979 = _T_6680 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_7988 = _T_6689 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_7997 = _T_6698 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_8006 = _T_6563 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_8015 = _T_6572 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_8024 = _T_6581 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_8033 = _T_6590 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_8042 = _T_6599 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_8051 = _T_6608 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_8060 = _T_6617 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_8069 = _T_6626 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_8078 = _T_6635 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_8087 = _T_6644 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_8096 = _T_6653 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_8105 = _T_6662 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_8114 = _T_6671 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_8123 = _T_6680 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_8132 = _T_6689 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_8141 = _T_6698 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_8150 = _T_6563 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_8159 = _T_6572 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_8168 = _T_6581 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_8177 = _T_6590 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_8186 = _T_6599 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_8195 = _T_6608 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_8204 = _T_6617 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_8213 = _T_6626 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_8222 = _T_6635 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_8231 = _T_6644 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_8240 = _T_6653 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_8249 = _T_6662 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_8258 = _T_6671 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_8267 = _T_6680 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_8276 = _T_6689 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_8285 = _T_6698 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_8294 = _T_6563 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_8303 = _T_6572 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_8312 = _T_6581 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_8321 = _T_6590 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_8330 = _T_6599 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_8339 = _T_6608 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_8348 = _T_6617 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_8357 = _T_6626 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_8366 = _T_6635 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_8375 = _T_6644 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_8384 = _T_6653 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_8393 = _T_6662 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_8402 = _T_6671 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_8411 = _T_6680 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_8420 = _T_6689 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_8429 = _T_6698 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_8438 = _T_6563 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_8447 = _T_6572 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_8456 = _T_6581 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_8465 = _T_6590 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_8474 = _T_6599 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_8483 = _T_6608 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_8492 = _T_6617 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_8501 = _T_6626 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_8510 = _T_6635 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_8519 = _T_6644 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_8528 = _T_6653 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_8537 = _T_6662 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_8546 = _T_6671 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_8555 = _T_6680 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_8564 = _T_6689 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_8573 = _T_6698 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_8582 = _T_6563 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_8591 = _T_6572 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_8600 = _T_6581 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_8609 = _T_6590 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_8618 = _T_6599 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_8627 = _T_6608 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_8636 = _T_6617 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_8645 = _T_6626 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_8654 = _T_6635 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_8663 = _T_6644 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_8672 = _T_6653 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_8681 = _T_6662 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_8690 = _T_6671 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_8699 = _T_6680 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_8708 = _T_6689 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_8717 = _T_6698 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_8726 = _T_6563 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_8735 = _T_6572 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_8744 = _T_6581 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_8753 = _T_6590 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_8762 = _T_6599 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_8771 = _T_6608 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_8780 = _T_6617 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_8789 = _T_6626 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_8798 = _T_6635 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_8807 = _T_6644 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_8816 = _T_6653 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_8825 = _T_6662 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_8834 = _T_6671 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_8843 = _T_6680 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_8852 = _T_6689 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_8861 = _T_6698 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_8867 = bht_wr_en2[1] & _T_6562; // @[ifu_bp_ctl.scala 434:23] - wire _T_8870 = _T_8867 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_8876 = bht_wr_en2[1] & _T_6571; // @[ifu_bp_ctl.scala 434:23] - wire _T_8879 = _T_8876 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_8885 = bht_wr_en2[1] & _T_6580; // @[ifu_bp_ctl.scala 434:23] - wire _T_8888 = _T_8885 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_8894 = bht_wr_en2[1] & _T_6589; // @[ifu_bp_ctl.scala 434:23] - wire _T_8897 = _T_8894 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_8903 = bht_wr_en2[1] & _T_6598; // @[ifu_bp_ctl.scala 434:23] - wire _T_8906 = _T_8903 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_8912 = bht_wr_en2[1] & _T_6607; // @[ifu_bp_ctl.scala 434:23] - wire _T_8915 = _T_8912 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_8921 = bht_wr_en2[1] & _T_6616; // @[ifu_bp_ctl.scala 434:23] - wire _T_8924 = _T_8921 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_8930 = bht_wr_en2[1] & _T_6625; // @[ifu_bp_ctl.scala 434:23] - wire _T_8933 = _T_8930 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_8939 = bht_wr_en2[1] & _T_6634; // @[ifu_bp_ctl.scala 434:23] - wire _T_8942 = _T_8939 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_8948 = bht_wr_en2[1] & _T_6643; // @[ifu_bp_ctl.scala 434:23] - wire _T_8951 = _T_8948 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_8957 = bht_wr_en2[1] & _T_6652; // @[ifu_bp_ctl.scala 434:23] - wire _T_8960 = _T_8957 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_8966 = bht_wr_en2[1] & _T_6661; // @[ifu_bp_ctl.scala 434:23] - wire _T_8969 = _T_8966 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_8975 = bht_wr_en2[1] & _T_6670; // @[ifu_bp_ctl.scala 434:23] - wire _T_8978 = _T_8975 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_8984 = bht_wr_en2[1] & _T_6679; // @[ifu_bp_ctl.scala 434:23] - wire _T_8987 = _T_8984 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_8993 = bht_wr_en2[1] & _T_6688; // @[ifu_bp_ctl.scala 434:23] - wire _T_8996 = _T_8993 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_9002 = bht_wr_en2[1] & _T_6697; // @[ifu_bp_ctl.scala 434:23] - wire _T_9005 = _T_9002 & _T_6215; // @[ifu_bp_ctl.scala 434:81] - wire _T_9014 = _T_8867 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_9023 = _T_8876 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_9032 = _T_8885 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_9041 = _T_8894 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_9050 = _T_8903 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_9059 = _T_8912 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_9068 = _T_8921 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_9077 = _T_8930 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_9086 = _T_8939 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_9095 = _T_8948 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_9104 = _T_8957 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_9113 = _T_8966 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_9122 = _T_8975 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_9131 = _T_8984 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_9140 = _T_8993 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_9149 = _T_9002 & _T_6226; // @[ifu_bp_ctl.scala 434:81] - wire _T_9158 = _T_8867 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_9167 = _T_8876 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_9176 = _T_8885 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_9185 = _T_8894 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_9194 = _T_8903 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_9203 = _T_8912 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_9212 = _T_8921 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_9221 = _T_8930 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_9230 = _T_8939 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_9239 = _T_8948 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_9248 = _T_8957 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_9257 = _T_8966 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_9266 = _T_8975 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_9275 = _T_8984 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_9284 = _T_8993 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_9293 = _T_9002 & _T_6237; // @[ifu_bp_ctl.scala 434:81] - wire _T_9302 = _T_8867 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_9311 = _T_8876 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_9320 = _T_8885 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_9329 = _T_8894 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_9338 = _T_8903 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_9347 = _T_8912 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_9356 = _T_8921 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_9365 = _T_8930 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_9374 = _T_8939 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_9383 = _T_8948 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_9392 = _T_8957 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_9401 = _T_8966 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_9410 = _T_8975 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_9419 = _T_8984 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_9428 = _T_8993 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_9437 = _T_9002 & _T_6248; // @[ifu_bp_ctl.scala 434:81] - wire _T_9446 = _T_8867 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_9455 = _T_8876 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_9464 = _T_8885 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_9473 = _T_8894 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_9482 = _T_8903 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_9491 = _T_8912 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_9500 = _T_8921 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_9509 = _T_8930 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_9518 = _T_8939 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_9527 = _T_8948 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_9536 = _T_8957 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_9545 = _T_8966 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_9554 = _T_8975 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_9563 = _T_8984 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_9572 = _T_8993 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_9581 = _T_9002 & _T_6259; // @[ifu_bp_ctl.scala 434:81] - wire _T_9590 = _T_8867 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_9599 = _T_8876 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_9608 = _T_8885 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_9617 = _T_8894 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_9626 = _T_8903 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_9635 = _T_8912 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_9644 = _T_8921 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_9653 = _T_8930 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_9662 = _T_8939 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_9671 = _T_8948 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_9680 = _T_8957 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_9689 = _T_8966 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_9698 = _T_8975 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_9707 = _T_8984 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_9716 = _T_8993 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_9725 = _T_9002 & _T_6270; // @[ifu_bp_ctl.scala 434:81] - wire _T_9734 = _T_8867 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_9743 = _T_8876 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_9752 = _T_8885 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_9761 = _T_8894 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_9770 = _T_8903 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_9779 = _T_8912 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_9788 = _T_8921 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_9797 = _T_8930 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_9806 = _T_8939 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_9815 = _T_8948 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_9824 = _T_8957 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_9833 = _T_8966 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_9842 = _T_8975 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_9851 = _T_8984 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_9860 = _T_8993 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_9869 = _T_9002 & _T_6281; // @[ifu_bp_ctl.scala 434:81] - wire _T_9878 = _T_8867 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_9887 = _T_8876 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_9896 = _T_8885 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_9905 = _T_8894 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_9914 = _T_8903 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_9923 = _T_8912 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_9932 = _T_8921 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_9941 = _T_8930 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_9950 = _T_8939 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_9959 = _T_8948 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_9968 = _T_8957 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_9977 = _T_8966 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_9986 = _T_8975 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_9995 = _T_8984 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_10004 = _T_8993 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_10013 = _T_9002 & _T_6292; // @[ifu_bp_ctl.scala 434:81] - wire _T_10022 = _T_8867 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_10031 = _T_8876 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_10040 = _T_8885 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_10049 = _T_8894 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_10058 = _T_8903 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_10067 = _T_8912 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_10076 = _T_8921 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_10085 = _T_8930 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_10094 = _T_8939 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_10103 = _T_8948 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_10112 = _T_8957 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_10121 = _T_8966 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_10130 = _T_8975 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_10139 = _T_8984 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_10148 = _T_8993 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_10157 = _T_9002 & _T_6303; // @[ifu_bp_ctl.scala 434:81] - wire _T_10166 = _T_8867 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_10175 = _T_8876 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_10184 = _T_8885 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_10193 = _T_8894 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_10202 = _T_8903 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_10211 = _T_8912 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_10220 = _T_8921 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_10229 = _T_8930 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_10238 = _T_8939 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_10247 = _T_8948 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_10256 = _T_8957 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_10265 = _T_8966 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_10274 = _T_8975 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_10283 = _T_8984 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_10292 = _T_8993 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_10301 = _T_9002 & _T_6314; // @[ifu_bp_ctl.scala 434:81] - wire _T_10310 = _T_8867 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_10319 = _T_8876 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_10328 = _T_8885 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_10337 = _T_8894 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_10346 = _T_8903 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_10355 = _T_8912 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_10364 = _T_8921 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_10373 = _T_8930 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_10382 = _T_8939 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_10391 = _T_8948 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_10400 = _T_8957 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_10409 = _T_8966 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_10418 = _T_8975 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_10427 = _T_8984 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_10436 = _T_8993 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_10445 = _T_9002 & _T_6325; // @[ifu_bp_ctl.scala 434:81] - wire _T_10454 = _T_8867 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_10463 = _T_8876 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_10472 = _T_8885 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_10481 = _T_8894 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_10490 = _T_8903 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_10499 = _T_8912 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_10508 = _T_8921 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_10517 = _T_8930 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_10526 = _T_8939 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_10535 = _T_8948 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_10544 = _T_8957 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_10553 = _T_8966 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_10562 = _T_8975 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_10571 = _T_8984 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_10580 = _T_8993 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_10589 = _T_9002 & _T_6336; // @[ifu_bp_ctl.scala 434:81] - wire _T_10598 = _T_8867 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_10607 = _T_8876 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_10616 = _T_8885 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_10625 = _T_8894 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_10634 = _T_8903 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_10643 = _T_8912 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_10652 = _T_8921 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_10661 = _T_8930 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_10670 = _T_8939 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_10679 = _T_8948 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_10688 = _T_8957 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_10697 = _T_8966 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_10706 = _T_8975 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_10715 = _T_8984 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_10724 = _T_8993 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_10733 = _T_9002 & _T_6347; // @[ifu_bp_ctl.scala 434:81] - wire _T_10742 = _T_8867 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_10751 = _T_8876 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_10760 = _T_8885 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_10769 = _T_8894 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_10778 = _T_8903 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_10787 = _T_8912 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_10796 = _T_8921 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_10805 = _T_8930 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_10814 = _T_8939 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_10823 = _T_8948 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_10832 = _T_8957 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_10841 = _T_8966 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_10850 = _T_8975 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_10859 = _T_8984 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_10868 = _T_8993 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_10877 = _T_9002 & _T_6358; // @[ifu_bp_ctl.scala 434:81] - wire _T_10886 = _T_8867 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_10895 = _T_8876 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_10904 = _T_8885 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_10913 = _T_8894 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_10922 = _T_8903 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_10931 = _T_8912 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_10940 = _T_8921 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_10949 = _T_8930 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_10958 = _T_8939 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_10967 = _T_8948 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_10976 = _T_8957 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_10985 = _T_8966 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_10994 = _T_8975 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_11003 = _T_8984 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_11012 = _T_8993 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_11021 = _T_9002 & _T_6369; // @[ifu_bp_ctl.scala 434:81] - wire _T_11030 = _T_8867 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_11039 = _T_8876 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_11048 = _T_8885 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_11057 = _T_8894 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_11066 = _T_8903 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_11075 = _T_8912 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_11084 = _T_8921 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_11093 = _T_8930 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_11102 = _T_8939 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_11111 = _T_8948 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_11120 = _T_8957 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_11129 = _T_8966 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_11138 = _T_8975 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_11147 = _T_8984 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_11156 = _T_8993 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_11165 = _T_9002 & _T_6380; // @[ifu_bp_ctl.scala 434:81] - wire _T_11170 = bht_wr_addr0[3:0] == 4'h0; // @[ifu_bp_ctl.scala 442:97] - wire _T_11171 = bht_wr_en0[0] & _T_11170; // @[ifu_bp_ctl.scala 442:45] - wire _T_11175 = _T_11171 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_0_0 = _T_11175 | _T_6566; // @[ifu_bp_ctl.scala 442:223] - wire _T_11187 = bht_wr_addr0[3:0] == 4'h1; // @[ifu_bp_ctl.scala 442:97] - wire _T_11188 = bht_wr_en0[0] & _T_11187; // @[ifu_bp_ctl.scala 442:45] - wire _T_11192 = _T_11188 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_0_1 = _T_11192 | _T_6575; // @[ifu_bp_ctl.scala 442:223] - wire _T_11204 = bht_wr_addr0[3:0] == 4'h2; // @[ifu_bp_ctl.scala 442:97] - wire _T_11205 = bht_wr_en0[0] & _T_11204; // @[ifu_bp_ctl.scala 442:45] - wire _T_11209 = _T_11205 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_0_2 = _T_11209 | _T_6584; // @[ifu_bp_ctl.scala 442:223] - wire _T_11221 = bht_wr_addr0[3:0] == 4'h3; // @[ifu_bp_ctl.scala 442:97] - wire _T_11222 = bht_wr_en0[0] & _T_11221; // @[ifu_bp_ctl.scala 442:45] - wire _T_11226 = _T_11222 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_0_3 = _T_11226 | _T_6593; // @[ifu_bp_ctl.scala 442:223] - wire _T_11238 = bht_wr_addr0[3:0] == 4'h4; // @[ifu_bp_ctl.scala 442:97] - wire _T_11239 = bht_wr_en0[0] & _T_11238; // @[ifu_bp_ctl.scala 442:45] - wire _T_11243 = _T_11239 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_0_4 = _T_11243 | _T_6602; // @[ifu_bp_ctl.scala 442:223] - wire _T_11255 = bht_wr_addr0[3:0] == 4'h5; // @[ifu_bp_ctl.scala 442:97] - wire _T_11256 = bht_wr_en0[0] & _T_11255; // @[ifu_bp_ctl.scala 442:45] - wire _T_11260 = _T_11256 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_0_5 = _T_11260 | _T_6611; // @[ifu_bp_ctl.scala 442:223] - wire _T_11272 = bht_wr_addr0[3:0] == 4'h6; // @[ifu_bp_ctl.scala 442:97] - wire _T_11273 = bht_wr_en0[0] & _T_11272; // @[ifu_bp_ctl.scala 442:45] - wire _T_11277 = _T_11273 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_0_6 = _T_11277 | _T_6620; // @[ifu_bp_ctl.scala 442:223] - wire _T_11289 = bht_wr_addr0[3:0] == 4'h7; // @[ifu_bp_ctl.scala 442:97] - wire _T_11290 = bht_wr_en0[0] & _T_11289; // @[ifu_bp_ctl.scala 442:45] - wire _T_11294 = _T_11290 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_0_7 = _T_11294 | _T_6629; // @[ifu_bp_ctl.scala 442:223] - wire _T_11306 = bht_wr_addr0[3:0] == 4'h8; // @[ifu_bp_ctl.scala 442:97] - wire _T_11307 = bht_wr_en0[0] & _T_11306; // @[ifu_bp_ctl.scala 442:45] - wire _T_11311 = _T_11307 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_0_8 = _T_11311 | _T_6638; // @[ifu_bp_ctl.scala 442:223] - wire _T_11323 = bht_wr_addr0[3:0] == 4'h9; // @[ifu_bp_ctl.scala 442:97] - wire _T_11324 = bht_wr_en0[0] & _T_11323; // @[ifu_bp_ctl.scala 442:45] - wire _T_11328 = _T_11324 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_0_9 = _T_11328 | _T_6647; // @[ifu_bp_ctl.scala 442:223] - wire _T_11340 = bht_wr_addr0[3:0] == 4'ha; // @[ifu_bp_ctl.scala 442:97] - wire _T_11341 = bht_wr_en0[0] & _T_11340; // @[ifu_bp_ctl.scala 442:45] - wire _T_11345 = _T_11341 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_0_10 = _T_11345 | _T_6656; // @[ifu_bp_ctl.scala 442:223] - wire _T_11357 = bht_wr_addr0[3:0] == 4'hb; // @[ifu_bp_ctl.scala 442:97] - wire _T_11358 = bht_wr_en0[0] & _T_11357; // @[ifu_bp_ctl.scala 442:45] - wire _T_11362 = _T_11358 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_0_11 = _T_11362 | _T_6665; // @[ifu_bp_ctl.scala 442:223] - wire _T_11374 = bht_wr_addr0[3:0] == 4'hc; // @[ifu_bp_ctl.scala 442:97] - wire _T_11375 = bht_wr_en0[0] & _T_11374; // @[ifu_bp_ctl.scala 442:45] - wire _T_11379 = _T_11375 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_0_12 = _T_11379 | _T_6674; // @[ifu_bp_ctl.scala 442:223] - wire _T_11391 = bht_wr_addr0[3:0] == 4'hd; // @[ifu_bp_ctl.scala 442:97] - wire _T_11392 = bht_wr_en0[0] & _T_11391; // @[ifu_bp_ctl.scala 442:45] - wire _T_11396 = _T_11392 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_0_13 = _T_11396 | _T_6683; // @[ifu_bp_ctl.scala 442:223] - wire _T_11408 = bht_wr_addr0[3:0] == 4'he; // @[ifu_bp_ctl.scala 442:97] - wire _T_11409 = bht_wr_en0[0] & _T_11408; // @[ifu_bp_ctl.scala 442:45] - wire _T_11413 = _T_11409 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_0_14 = _T_11413 | _T_6692; // @[ifu_bp_ctl.scala 442:223] - wire _T_11425 = bht_wr_addr0[3:0] == 4'hf; // @[ifu_bp_ctl.scala 442:97] - wire _T_11426 = bht_wr_en0[0] & _T_11425; // @[ifu_bp_ctl.scala 442:45] - wire _T_11430 = _T_11426 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_0_15 = _T_11430 | _T_6701; // @[ifu_bp_ctl.scala 442:223] - wire _T_11447 = _T_11171 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_1_0 = _T_11447 | _T_6710; // @[ifu_bp_ctl.scala 442:223] - wire _T_11464 = _T_11188 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_1_1 = _T_11464 | _T_6719; // @[ifu_bp_ctl.scala 442:223] - wire _T_11481 = _T_11205 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_1_2 = _T_11481 | _T_6728; // @[ifu_bp_ctl.scala 442:223] - wire _T_11498 = _T_11222 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_1_3 = _T_11498 | _T_6737; // @[ifu_bp_ctl.scala 442:223] - wire _T_11515 = _T_11239 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_1_4 = _T_11515 | _T_6746; // @[ifu_bp_ctl.scala 442:223] - wire _T_11532 = _T_11256 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_1_5 = _T_11532 | _T_6755; // @[ifu_bp_ctl.scala 442:223] - wire _T_11549 = _T_11273 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_1_6 = _T_11549 | _T_6764; // @[ifu_bp_ctl.scala 442:223] - wire _T_11566 = _T_11290 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_1_7 = _T_11566 | _T_6773; // @[ifu_bp_ctl.scala 442:223] - wire _T_11583 = _T_11307 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_1_8 = _T_11583 | _T_6782; // @[ifu_bp_ctl.scala 442:223] - wire _T_11600 = _T_11324 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_1_9 = _T_11600 | _T_6791; // @[ifu_bp_ctl.scala 442:223] - wire _T_11617 = _T_11341 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_1_10 = _T_11617 | _T_6800; // @[ifu_bp_ctl.scala 442:223] - wire _T_11634 = _T_11358 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_1_11 = _T_11634 | _T_6809; // @[ifu_bp_ctl.scala 442:223] - wire _T_11651 = _T_11375 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_1_12 = _T_11651 | _T_6818; // @[ifu_bp_ctl.scala 442:223] - wire _T_11668 = _T_11392 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_1_13 = _T_11668 | _T_6827; // @[ifu_bp_ctl.scala 442:223] - wire _T_11685 = _T_11409 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_1_14 = _T_11685 | _T_6836; // @[ifu_bp_ctl.scala 442:223] - wire _T_11702 = _T_11426 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_1_15 = _T_11702 | _T_6845; // @[ifu_bp_ctl.scala 442:223] - wire _T_11719 = _T_11171 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_2_0 = _T_11719 | _T_6854; // @[ifu_bp_ctl.scala 442:223] - wire _T_11736 = _T_11188 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_2_1 = _T_11736 | _T_6863; // @[ifu_bp_ctl.scala 442:223] - wire _T_11753 = _T_11205 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_2_2 = _T_11753 | _T_6872; // @[ifu_bp_ctl.scala 442:223] - wire _T_11770 = _T_11222 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_2_3 = _T_11770 | _T_6881; // @[ifu_bp_ctl.scala 442:223] - wire _T_11787 = _T_11239 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_2_4 = _T_11787 | _T_6890; // @[ifu_bp_ctl.scala 442:223] - wire _T_11804 = _T_11256 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_2_5 = _T_11804 | _T_6899; // @[ifu_bp_ctl.scala 442:223] - wire _T_11821 = _T_11273 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_2_6 = _T_11821 | _T_6908; // @[ifu_bp_ctl.scala 442:223] - wire _T_11838 = _T_11290 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_2_7 = _T_11838 | _T_6917; // @[ifu_bp_ctl.scala 442:223] - wire _T_11855 = _T_11307 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_2_8 = _T_11855 | _T_6926; // @[ifu_bp_ctl.scala 442:223] - wire _T_11872 = _T_11324 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_2_9 = _T_11872 | _T_6935; // @[ifu_bp_ctl.scala 442:223] - wire _T_11889 = _T_11341 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_2_10 = _T_11889 | _T_6944; // @[ifu_bp_ctl.scala 442:223] - wire _T_11906 = _T_11358 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_2_11 = _T_11906 | _T_6953; // @[ifu_bp_ctl.scala 442:223] - wire _T_11923 = _T_11375 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_2_12 = _T_11923 | _T_6962; // @[ifu_bp_ctl.scala 442:223] - wire _T_11940 = _T_11392 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_2_13 = _T_11940 | _T_6971; // @[ifu_bp_ctl.scala 442:223] - wire _T_11957 = _T_11409 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_2_14 = _T_11957 | _T_6980; // @[ifu_bp_ctl.scala 442:223] - wire _T_11974 = _T_11426 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_2_15 = _T_11974 | _T_6989; // @[ifu_bp_ctl.scala 442:223] - wire _T_11991 = _T_11171 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_3_0 = _T_11991 | _T_6998; // @[ifu_bp_ctl.scala 442:223] - wire _T_12008 = _T_11188 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_3_1 = _T_12008 | _T_7007; // @[ifu_bp_ctl.scala 442:223] - wire _T_12025 = _T_11205 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_3_2 = _T_12025 | _T_7016; // @[ifu_bp_ctl.scala 442:223] - wire _T_12042 = _T_11222 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_3_3 = _T_12042 | _T_7025; // @[ifu_bp_ctl.scala 442:223] - wire _T_12059 = _T_11239 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_3_4 = _T_12059 | _T_7034; // @[ifu_bp_ctl.scala 442:223] - wire _T_12076 = _T_11256 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_3_5 = _T_12076 | _T_7043; // @[ifu_bp_ctl.scala 442:223] - wire _T_12093 = _T_11273 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_3_6 = _T_12093 | _T_7052; // @[ifu_bp_ctl.scala 442:223] - wire _T_12110 = _T_11290 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_3_7 = _T_12110 | _T_7061; // @[ifu_bp_ctl.scala 442:223] - wire _T_12127 = _T_11307 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_3_8 = _T_12127 | _T_7070; // @[ifu_bp_ctl.scala 442:223] - wire _T_12144 = _T_11324 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_3_9 = _T_12144 | _T_7079; // @[ifu_bp_ctl.scala 442:223] - wire _T_12161 = _T_11341 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_3_10 = _T_12161 | _T_7088; // @[ifu_bp_ctl.scala 442:223] - wire _T_12178 = _T_11358 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_3_11 = _T_12178 | _T_7097; // @[ifu_bp_ctl.scala 442:223] - wire _T_12195 = _T_11375 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_3_12 = _T_12195 | _T_7106; // @[ifu_bp_ctl.scala 442:223] - wire _T_12212 = _T_11392 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_3_13 = _T_12212 | _T_7115; // @[ifu_bp_ctl.scala 442:223] - wire _T_12229 = _T_11409 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_3_14 = _T_12229 | _T_7124; // @[ifu_bp_ctl.scala 442:223] - wire _T_12246 = _T_11426 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_3_15 = _T_12246 | _T_7133; // @[ifu_bp_ctl.scala 442:223] - wire _T_12263 = _T_11171 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_4_0 = _T_12263 | _T_7142; // @[ifu_bp_ctl.scala 442:223] - wire _T_12280 = _T_11188 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_4_1 = _T_12280 | _T_7151; // @[ifu_bp_ctl.scala 442:223] - wire _T_12297 = _T_11205 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_4_2 = _T_12297 | _T_7160; // @[ifu_bp_ctl.scala 442:223] - wire _T_12314 = _T_11222 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_4_3 = _T_12314 | _T_7169; // @[ifu_bp_ctl.scala 442:223] - wire _T_12331 = _T_11239 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_4_4 = _T_12331 | _T_7178; // @[ifu_bp_ctl.scala 442:223] - wire _T_12348 = _T_11256 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_4_5 = _T_12348 | _T_7187; // @[ifu_bp_ctl.scala 442:223] - wire _T_12365 = _T_11273 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_4_6 = _T_12365 | _T_7196; // @[ifu_bp_ctl.scala 442:223] - wire _T_12382 = _T_11290 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_4_7 = _T_12382 | _T_7205; // @[ifu_bp_ctl.scala 442:223] - wire _T_12399 = _T_11307 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_4_8 = _T_12399 | _T_7214; // @[ifu_bp_ctl.scala 442:223] - wire _T_12416 = _T_11324 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_4_9 = _T_12416 | _T_7223; // @[ifu_bp_ctl.scala 442:223] - wire _T_12433 = _T_11341 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_4_10 = _T_12433 | _T_7232; // @[ifu_bp_ctl.scala 442:223] - wire _T_12450 = _T_11358 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_4_11 = _T_12450 | _T_7241; // @[ifu_bp_ctl.scala 442:223] - wire _T_12467 = _T_11375 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_4_12 = _T_12467 | _T_7250; // @[ifu_bp_ctl.scala 442:223] - wire _T_12484 = _T_11392 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_4_13 = _T_12484 | _T_7259; // @[ifu_bp_ctl.scala 442:223] - wire _T_12501 = _T_11409 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_4_14 = _T_12501 | _T_7268; // @[ifu_bp_ctl.scala 442:223] - wire _T_12518 = _T_11426 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_4_15 = _T_12518 | _T_7277; // @[ifu_bp_ctl.scala 442:223] - wire _T_12535 = _T_11171 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_5_0 = _T_12535 | _T_7286; // @[ifu_bp_ctl.scala 442:223] - wire _T_12552 = _T_11188 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_5_1 = _T_12552 | _T_7295; // @[ifu_bp_ctl.scala 442:223] - wire _T_12569 = _T_11205 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_5_2 = _T_12569 | _T_7304; // @[ifu_bp_ctl.scala 442:223] - wire _T_12586 = _T_11222 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_5_3 = _T_12586 | _T_7313; // @[ifu_bp_ctl.scala 442:223] - wire _T_12603 = _T_11239 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_5_4 = _T_12603 | _T_7322; // @[ifu_bp_ctl.scala 442:223] - wire _T_12620 = _T_11256 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_5_5 = _T_12620 | _T_7331; // @[ifu_bp_ctl.scala 442:223] - wire _T_12637 = _T_11273 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_5_6 = _T_12637 | _T_7340; // @[ifu_bp_ctl.scala 442:223] - wire _T_12654 = _T_11290 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_5_7 = _T_12654 | _T_7349; // @[ifu_bp_ctl.scala 442:223] - wire _T_12671 = _T_11307 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_5_8 = _T_12671 | _T_7358; // @[ifu_bp_ctl.scala 442:223] - wire _T_12688 = _T_11324 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_5_9 = _T_12688 | _T_7367; // @[ifu_bp_ctl.scala 442:223] - wire _T_12705 = _T_11341 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_5_10 = _T_12705 | _T_7376; // @[ifu_bp_ctl.scala 442:223] - wire _T_12722 = _T_11358 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_5_11 = _T_12722 | _T_7385; // @[ifu_bp_ctl.scala 442:223] - wire _T_12739 = _T_11375 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_5_12 = _T_12739 | _T_7394; // @[ifu_bp_ctl.scala 442:223] - wire _T_12756 = _T_11392 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_5_13 = _T_12756 | _T_7403; // @[ifu_bp_ctl.scala 442:223] - wire _T_12773 = _T_11409 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_5_14 = _T_12773 | _T_7412; // @[ifu_bp_ctl.scala 442:223] - wire _T_12790 = _T_11426 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_5_15 = _T_12790 | _T_7421; // @[ifu_bp_ctl.scala 442:223] - wire _T_12807 = _T_11171 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_6_0 = _T_12807 | _T_7430; // @[ifu_bp_ctl.scala 442:223] - wire _T_12824 = _T_11188 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_6_1 = _T_12824 | _T_7439; // @[ifu_bp_ctl.scala 442:223] - wire _T_12841 = _T_11205 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_6_2 = _T_12841 | _T_7448; // @[ifu_bp_ctl.scala 442:223] - wire _T_12858 = _T_11222 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_6_3 = _T_12858 | _T_7457; // @[ifu_bp_ctl.scala 442:223] - wire _T_12875 = _T_11239 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_6_4 = _T_12875 | _T_7466; // @[ifu_bp_ctl.scala 442:223] - wire _T_12892 = _T_11256 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_6_5 = _T_12892 | _T_7475; // @[ifu_bp_ctl.scala 442:223] - wire _T_12909 = _T_11273 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_6_6 = _T_12909 | _T_7484; // @[ifu_bp_ctl.scala 442:223] - wire _T_12926 = _T_11290 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_6_7 = _T_12926 | _T_7493; // @[ifu_bp_ctl.scala 442:223] - wire _T_12943 = _T_11307 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_6_8 = _T_12943 | _T_7502; // @[ifu_bp_ctl.scala 442:223] - wire _T_12960 = _T_11324 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_6_9 = _T_12960 | _T_7511; // @[ifu_bp_ctl.scala 442:223] - wire _T_12977 = _T_11341 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_6_10 = _T_12977 | _T_7520; // @[ifu_bp_ctl.scala 442:223] - wire _T_12994 = _T_11358 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_6_11 = _T_12994 | _T_7529; // @[ifu_bp_ctl.scala 442:223] - wire _T_13011 = _T_11375 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_6_12 = _T_13011 | _T_7538; // @[ifu_bp_ctl.scala 442:223] - wire _T_13028 = _T_11392 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_6_13 = _T_13028 | _T_7547; // @[ifu_bp_ctl.scala 442:223] - wire _T_13045 = _T_11409 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_6_14 = _T_13045 | _T_7556; // @[ifu_bp_ctl.scala 442:223] - wire _T_13062 = _T_11426 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_6_15 = _T_13062 | _T_7565; // @[ifu_bp_ctl.scala 442:223] - wire _T_13079 = _T_11171 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_7_0 = _T_13079 | _T_7574; // @[ifu_bp_ctl.scala 442:223] - wire _T_13096 = _T_11188 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_7_1 = _T_13096 | _T_7583; // @[ifu_bp_ctl.scala 442:223] - wire _T_13113 = _T_11205 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_7_2 = _T_13113 | _T_7592; // @[ifu_bp_ctl.scala 442:223] - wire _T_13130 = _T_11222 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_7_3 = _T_13130 | _T_7601; // @[ifu_bp_ctl.scala 442:223] - wire _T_13147 = _T_11239 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_7_4 = _T_13147 | _T_7610; // @[ifu_bp_ctl.scala 442:223] - wire _T_13164 = _T_11256 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_7_5 = _T_13164 | _T_7619; // @[ifu_bp_ctl.scala 442:223] - wire _T_13181 = _T_11273 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_7_6 = _T_13181 | _T_7628; // @[ifu_bp_ctl.scala 442:223] - wire _T_13198 = _T_11290 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_7_7 = _T_13198 | _T_7637; // @[ifu_bp_ctl.scala 442:223] - wire _T_13215 = _T_11307 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_7_8 = _T_13215 | _T_7646; // @[ifu_bp_ctl.scala 442:223] - wire _T_13232 = _T_11324 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_7_9 = _T_13232 | _T_7655; // @[ifu_bp_ctl.scala 442:223] - wire _T_13249 = _T_11341 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_7_10 = _T_13249 | _T_7664; // @[ifu_bp_ctl.scala 442:223] - wire _T_13266 = _T_11358 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_7_11 = _T_13266 | _T_7673; // @[ifu_bp_ctl.scala 442:223] - wire _T_13283 = _T_11375 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_7_12 = _T_13283 | _T_7682; // @[ifu_bp_ctl.scala 442:223] - wire _T_13300 = _T_11392 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_7_13 = _T_13300 | _T_7691; // @[ifu_bp_ctl.scala 442:223] - wire _T_13317 = _T_11409 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_7_14 = _T_13317 | _T_7700; // @[ifu_bp_ctl.scala 442:223] - wire _T_13334 = _T_11426 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_7_15 = _T_13334 | _T_7709; // @[ifu_bp_ctl.scala 442:223] - wire _T_13351 = _T_11171 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_8_0 = _T_13351 | _T_7718; // @[ifu_bp_ctl.scala 442:223] - wire _T_13368 = _T_11188 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_8_1 = _T_13368 | _T_7727; // @[ifu_bp_ctl.scala 442:223] - wire _T_13385 = _T_11205 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_8_2 = _T_13385 | _T_7736; // @[ifu_bp_ctl.scala 442:223] - wire _T_13402 = _T_11222 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_8_3 = _T_13402 | _T_7745; // @[ifu_bp_ctl.scala 442:223] - wire _T_13419 = _T_11239 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_8_4 = _T_13419 | _T_7754; // @[ifu_bp_ctl.scala 442:223] - wire _T_13436 = _T_11256 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_8_5 = _T_13436 | _T_7763; // @[ifu_bp_ctl.scala 442:223] - wire _T_13453 = _T_11273 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_8_6 = _T_13453 | _T_7772; // @[ifu_bp_ctl.scala 442:223] - wire _T_13470 = _T_11290 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_8_7 = _T_13470 | _T_7781; // @[ifu_bp_ctl.scala 442:223] - wire _T_13487 = _T_11307 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_8_8 = _T_13487 | _T_7790; // @[ifu_bp_ctl.scala 442:223] - wire _T_13504 = _T_11324 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_8_9 = _T_13504 | _T_7799; // @[ifu_bp_ctl.scala 442:223] - wire _T_13521 = _T_11341 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_8_10 = _T_13521 | _T_7808; // @[ifu_bp_ctl.scala 442:223] - wire _T_13538 = _T_11358 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_8_11 = _T_13538 | _T_7817; // @[ifu_bp_ctl.scala 442:223] - wire _T_13555 = _T_11375 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_8_12 = _T_13555 | _T_7826; // @[ifu_bp_ctl.scala 442:223] - wire _T_13572 = _T_11392 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_8_13 = _T_13572 | _T_7835; // @[ifu_bp_ctl.scala 442:223] - wire _T_13589 = _T_11409 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_8_14 = _T_13589 | _T_7844; // @[ifu_bp_ctl.scala 442:223] - wire _T_13606 = _T_11426 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_8_15 = _T_13606 | _T_7853; // @[ifu_bp_ctl.scala 442:223] - wire _T_13623 = _T_11171 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_9_0 = _T_13623 | _T_7862; // @[ifu_bp_ctl.scala 442:223] - wire _T_13640 = _T_11188 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_9_1 = _T_13640 | _T_7871; // @[ifu_bp_ctl.scala 442:223] - wire _T_13657 = _T_11205 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_9_2 = _T_13657 | _T_7880; // @[ifu_bp_ctl.scala 442:223] - wire _T_13674 = _T_11222 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_9_3 = _T_13674 | _T_7889; // @[ifu_bp_ctl.scala 442:223] - wire _T_13691 = _T_11239 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_9_4 = _T_13691 | _T_7898; // @[ifu_bp_ctl.scala 442:223] - wire _T_13708 = _T_11256 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_9_5 = _T_13708 | _T_7907; // @[ifu_bp_ctl.scala 442:223] - wire _T_13725 = _T_11273 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_9_6 = _T_13725 | _T_7916; // @[ifu_bp_ctl.scala 442:223] - wire _T_13742 = _T_11290 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_9_7 = _T_13742 | _T_7925; // @[ifu_bp_ctl.scala 442:223] - wire _T_13759 = _T_11307 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_9_8 = _T_13759 | _T_7934; // @[ifu_bp_ctl.scala 442:223] - wire _T_13776 = _T_11324 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_9_9 = _T_13776 | _T_7943; // @[ifu_bp_ctl.scala 442:223] - wire _T_13793 = _T_11341 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_9_10 = _T_13793 | _T_7952; // @[ifu_bp_ctl.scala 442:223] - wire _T_13810 = _T_11358 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_9_11 = _T_13810 | _T_7961; // @[ifu_bp_ctl.scala 442:223] - wire _T_13827 = _T_11375 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_9_12 = _T_13827 | _T_7970; // @[ifu_bp_ctl.scala 442:223] - wire _T_13844 = _T_11392 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_9_13 = _T_13844 | _T_7979; // @[ifu_bp_ctl.scala 442:223] - wire _T_13861 = _T_11409 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_9_14 = _T_13861 | _T_7988; // @[ifu_bp_ctl.scala 442:223] - wire _T_13878 = _T_11426 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_9_15 = _T_13878 | _T_7997; // @[ifu_bp_ctl.scala 442:223] - wire _T_13895 = _T_11171 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_10_0 = _T_13895 | _T_8006; // @[ifu_bp_ctl.scala 442:223] - wire _T_13912 = _T_11188 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_10_1 = _T_13912 | _T_8015; // @[ifu_bp_ctl.scala 442:223] - wire _T_13929 = _T_11205 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_10_2 = _T_13929 | _T_8024; // @[ifu_bp_ctl.scala 442:223] - wire _T_13946 = _T_11222 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_10_3 = _T_13946 | _T_8033; // @[ifu_bp_ctl.scala 442:223] - wire _T_13963 = _T_11239 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_10_4 = _T_13963 | _T_8042; // @[ifu_bp_ctl.scala 442:223] - wire _T_13980 = _T_11256 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_10_5 = _T_13980 | _T_8051; // @[ifu_bp_ctl.scala 442:223] - wire _T_13997 = _T_11273 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_10_6 = _T_13997 | _T_8060; // @[ifu_bp_ctl.scala 442:223] - wire _T_14014 = _T_11290 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_10_7 = _T_14014 | _T_8069; // @[ifu_bp_ctl.scala 442:223] - wire _T_14031 = _T_11307 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_10_8 = _T_14031 | _T_8078; // @[ifu_bp_ctl.scala 442:223] - wire _T_14048 = _T_11324 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_10_9 = _T_14048 | _T_8087; // @[ifu_bp_ctl.scala 442:223] - wire _T_14065 = _T_11341 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_10_10 = _T_14065 | _T_8096; // @[ifu_bp_ctl.scala 442:223] - wire _T_14082 = _T_11358 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_10_11 = _T_14082 | _T_8105; // @[ifu_bp_ctl.scala 442:223] - wire _T_14099 = _T_11375 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_10_12 = _T_14099 | _T_8114; // @[ifu_bp_ctl.scala 442:223] - wire _T_14116 = _T_11392 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_10_13 = _T_14116 | _T_8123; // @[ifu_bp_ctl.scala 442:223] - wire _T_14133 = _T_11409 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_10_14 = _T_14133 | _T_8132; // @[ifu_bp_ctl.scala 442:223] - wire _T_14150 = _T_11426 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_10_15 = _T_14150 | _T_8141; // @[ifu_bp_ctl.scala 442:223] - wire _T_14167 = _T_11171 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_11_0 = _T_14167 | _T_8150; // @[ifu_bp_ctl.scala 442:223] - wire _T_14184 = _T_11188 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_11_1 = _T_14184 | _T_8159; // @[ifu_bp_ctl.scala 442:223] - wire _T_14201 = _T_11205 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_11_2 = _T_14201 | _T_8168; // @[ifu_bp_ctl.scala 442:223] - wire _T_14218 = _T_11222 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_11_3 = _T_14218 | _T_8177; // @[ifu_bp_ctl.scala 442:223] - wire _T_14235 = _T_11239 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_11_4 = _T_14235 | _T_8186; // @[ifu_bp_ctl.scala 442:223] - wire _T_14252 = _T_11256 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_11_5 = _T_14252 | _T_8195; // @[ifu_bp_ctl.scala 442:223] - wire _T_14269 = _T_11273 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_11_6 = _T_14269 | _T_8204; // @[ifu_bp_ctl.scala 442:223] - wire _T_14286 = _T_11290 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_11_7 = _T_14286 | _T_8213; // @[ifu_bp_ctl.scala 442:223] - wire _T_14303 = _T_11307 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_11_8 = _T_14303 | _T_8222; // @[ifu_bp_ctl.scala 442:223] - wire _T_14320 = _T_11324 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_11_9 = _T_14320 | _T_8231; // @[ifu_bp_ctl.scala 442:223] - wire _T_14337 = _T_11341 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_11_10 = _T_14337 | _T_8240; // @[ifu_bp_ctl.scala 442:223] - wire _T_14354 = _T_11358 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_11_11 = _T_14354 | _T_8249; // @[ifu_bp_ctl.scala 442:223] - wire _T_14371 = _T_11375 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_11_12 = _T_14371 | _T_8258; // @[ifu_bp_ctl.scala 442:223] - wire _T_14388 = _T_11392 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_11_13 = _T_14388 | _T_8267; // @[ifu_bp_ctl.scala 442:223] - wire _T_14405 = _T_11409 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_11_14 = _T_14405 | _T_8276; // @[ifu_bp_ctl.scala 442:223] - wire _T_14422 = _T_11426 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_11_15 = _T_14422 | _T_8285; // @[ifu_bp_ctl.scala 442:223] - wire _T_14439 = _T_11171 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_12_0 = _T_14439 | _T_8294; // @[ifu_bp_ctl.scala 442:223] - wire _T_14456 = _T_11188 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_12_1 = _T_14456 | _T_8303; // @[ifu_bp_ctl.scala 442:223] - wire _T_14473 = _T_11205 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_12_2 = _T_14473 | _T_8312; // @[ifu_bp_ctl.scala 442:223] - wire _T_14490 = _T_11222 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_12_3 = _T_14490 | _T_8321; // @[ifu_bp_ctl.scala 442:223] - wire _T_14507 = _T_11239 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_12_4 = _T_14507 | _T_8330; // @[ifu_bp_ctl.scala 442:223] - wire _T_14524 = _T_11256 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_12_5 = _T_14524 | _T_8339; // @[ifu_bp_ctl.scala 442:223] - wire _T_14541 = _T_11273 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_12_6 = _T_14541 | _T_8348; // @[ifu_bp_ctl.scala 442:223] - wire _T_14558 = _T_11290 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_12_7 = _T_14558 | _T_8357; // @[ifu_bp_ctl.scala 442:223] - wire _T_14575 = _T_11307 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_12_8 = _T_14575 | _T_8366; // @[ifu_bp_ctl.scala 442:223] - wire _T_14592 = _T_11324 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_12_9 = _T_14592 | _T_8375; // @[ifu_bp_ctl.scala 442:223] - wire _T_14609 = _T_11341 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_12_10 = _T_14609 | _T_8384; // @[ifu_bp_ctl.scala 442:223] - wire _T_14626 = _T_11358 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_12_11 = _T_14626 | _T_8393; // @[ifu_bp_ctl.scala 442:223] - wire _T_14643 = _T_11375 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_12_12 = _T_14643 | _T_8402; // @[ifu_bp_ctl.scala 442:223] - wire _T_14660 = _T_11392 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_12_13 = _T_14660 | _T_8411; // @[ifu_bp_ctl.scala 442:223] - wire _T_14677 = _T_11409 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_12_14 = _T_14677 | _T_8420; // @[ifu_bp_ctl.scala 442:223] - wire _T_14694 = _T_11426 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_12_15 = _T_14694 | _T_8429; // @[ifu_bp_ctl.scala 442:223] - wire _T_14711 = _T_11171 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_13_0 = _T_14711 | _T_8438; // @[ifu_bp_ctl.scala 442:223] - wire _T_14728 = _T_11188 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_13_1 = _T_14728 | _T_8447; // @[ifu_bp_ctl.scala 442:223] - wire _T_14745 = _T_11205 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_13_2 = _T_14745 | _T_8456; // @[ifu_bp_ctl.scala 442:223] - wire _T_14762 = _T_11222 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_13_3 = _T_14762 | _T_8465; // @[ifu_bp_ctl.scala 442:223] - wire _T_14779 = _T_11239 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_13_4 = _T_14779 | _T_8474; // @[ifu_bp_ctl.scala 442:223] - wire _T_14796 = _T_11256 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_13_5 = _T_14796 | _T_8483; // @[ifu_bp_ctl.scala 442:223] - wire _T_14813 = _T_11273 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_13_6 = _T_14813 | _T_8492; // @[ifu_bp_ctl.scala 442:223] - wire _T_14830 = _T_11290 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_13_7 = _T_14830 | _T_8501; // @[ifu_bp_ctl.scala 442:223] - wire _T_14847 = _T_11307 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_13_8 = _T_14847 | _T_8510; // @[ifu_bp_ctl.scala 442:223] - wire _T_14864 = _T_11324 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_13_9 = _T_14864 | _T_8519; // @[ifu_bp_ctl.scala 442:223] - wire _T_14881 = _T_11341 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_13_10 = _T_14881 | _T_8528; // @[ifu_bp_ctl.scala 442:223] - wire _T_14898 = _T_11358 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_13_11 = _T_14898 | _T_8537; // @[ifu_bp_ctl.scala 442:223] - wire _T_14915 = _T_11375 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_13_12 = _T_14915 | _T_8546; // @[ifu_bp_ctl.scala 442:223] - wire _T_14932 = _T_11392 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_13_13 = _T_14932 | _T_8555; // @[ifu_bp_ctl.scala 442:223] - wire _T_14949 = _T_11409 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_13_14 = _T_14949 | _T_8564; // @[ifu_bp_ctl.scala 442:223] - wire _T_14966 = _T_11426 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_13_15 = _T_14966 | _T_8573; // @[ifu_bp_ctl.scala 442:223] - wire _T_14983 = _T_11171 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_14_0 = _T_14983 | _T_8582; // @[ifu_bp_ctl.scala 442:223] - wire _T_15000 = _T_11188 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_14_1 = _T_15000 | _T_8591; // @[ifu_bp_ctl.scala 442:223] - wire _T_15017 = _T_11205 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_14_2 = _T_15017 | _T_8600; // @[ifu_bp_ctl.scala 442:223] - wire _T_15034 = _T_11222 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_14_3 = _T_15034 | _T_8609; // @[ifu_bp_ctl.scala 442:223] - wire _T_15051 = _T_11239 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_14_4 = _T_15051 | _T_8618; // @[ifu_bp_ctl.scala 442:223] - wire _T_15068 = _T_11256 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_14_5 = _T_15068 | _T_8627; // @[ifu_bp_ctl.scala 442:223] - wire _T_15085 = _T_11273 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_14_6 = _T_15085 | _T_8636; // @[ifu_bp_ctl.scala 442:223] - wire _T_15102 = _T_11290 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_14_7 = _T_15102 | _T_8645; // @[ifu_bp_ctl.scala 442:223] - wire _T_15119 = _T_11307 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_14_8 = _T_15119 | _T_8654; // @[ifu_bp_ctl.scala 442:223] - wire _T_15136 = _T_11324 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_14_9 = _T_15136 | _T_8663; // @[ifu_bp_ctl.scala 442:223] - wire _T_15153 = _T_11341 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_14_10 = _T_15153 | _T_8672; // @[ifu_bp_ctl.scala 442:223] - wire _T_15170 = _T_11358 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_14_11 = _T_15170 | _T_8681; // @[ifu_bp_ctl.scala 442:223] - wire _T_15187 = _T_11375 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_14_12 = _T_15187 | _T_8690; // @[ifu_bp_ctl.scala 442:223] - wire _T_15204 = _T_11392 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_14_13 = _T_15204 | _T_8699; // @[ifu_bp_ctl.scala 442:223] - wire _T_15221 = _T_11409 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_14_14 = _T_15221 | _T_8708; // @[ifu_bp_ctl.scala 442:223] - wire _T_15238 = _T_11426 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_14_15 = _T_15238 | _T_8717; // @[ifu_bp_ctl.scala 442:223] - wire _T_15255 = _T_11171 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_15_0 = _T_15255 | _T_8726; // @[ifu_bp_ctl.scala 442:223] - wire _T_15272 = _T_11188 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_15_1 = _T_15272 | _T_8735; // @[ifu_bp_ctl.scala 442:223] - wire _T_15289 = _T_11205 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_15_2 = _T_15289 | _T_8744; // @[ifu_bp_ctl.scala 442:223] - wire _T_15306 = _T_11222 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_15_3 = _T_15306 | _T_8753; // @[ifu_bp_ctl.scala 442:223] - wire _T_15323 = _T_11239 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_15_4 = _T_15323 | _T_8762; // @[ifu_bp_ctl.scala 442:223] - wire _T_15340 = _T_11256 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_15_5 = _T_15340 | _T_8771; // @[ifu_bp_ctl.scala 442:223] - wire _T_15357 = _T_11273 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_15_6 = _T_15357 | _T_8780; // @[ifu_bp_ctl.scala 442:223] - wire _T_15374 = _T_11290 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_15_7 = _T_15374 | _T_8789; // @[ifu_bp_ctl.scala 442:223] - wire _T_15391 = _T_11307 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_15_8 = _T_15391 | _T_8798; // @[ifu_bp_ctl.scala 442:223] - wire _T_15408 = _T_11324 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_15_9 = _T_15408 | _T_8807; // @[ifu_bp_ctl.scala 442:223] - wire _T_15425 = _T_11341 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_15_10 = _T_15425 | _T_8816; // @[ifu_bp_ctl.scala 442:223] - wire _T_15442 = _T_11358 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_15_11 = _T_15442 | _T_8825; // @[ifu_bp_ctl.scala 442:223] - wire _T_15459 = _T_11375 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_15_12 = _T_15459 | _T_8834; // @[ifu_bp_ctl.scala 442:223] - wire _T_15476 = _T_11392 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_15_13 = _T_15476 | _T_8843; // @[ifu_bp_ctl.scala 442:223] - wire _T_15493 = _T_11409 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_15_14 = _T_15493 | _T_8852; // @[ifu_bp_ctl.scala 442:223] - wire _T_15510 = _T_11426 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_0_15_15 = _T_15510 | _T_8861; // @[ifu_bp_ctl.scala 442:223] - wire _T_15523 = bht_wr_en0[1] & _T_11170; // @[ifu_bp_ctl.scala 442:45] - wire _T_15527 = _T_15523 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_0_0 = _T_15527 | _T_8870; // @[ifu_bp_ctl.scala 442:223] - wire _T_15540 = bht_wr_en0[1] & _T_11187; // @[ifu_bp_ctl.scala 442:45] - wire _T_15544 = _T_15540 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_0_1 = _T_15544 | _T_8879; // @[ifu_bp_ctl.scala 442:223] - wire _T_15557 = bht_wr_en0[1] & _T_11204; // @[ifu_bp_ctl.scala 442:45] - wire _T_15561 = _T_15557 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_0_2 = _T_15561 | _T_8888; // @[ifu_bp_ctl.scala 442:223] - wire _T_15574 = bht_wr_en0[1] & _T_11221; // @[ifu_bp_ctl.scala 442:45] - wire _T_15578 = _T_15574 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_0_3 = _T_15578 | _T_8897; // @[ifu_bp_ctl.scala 442:223] - wire _T_15591 = bht_wr_en0[1] & _T_11238; // @[ifu_bp_ctl.scala 442:45] - wire _T_15595 = _T_15591 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_0_4 = _T_15595 | _T_8906; // @[ifu_bp_ctl.scala 442:223] - wire _T_15608 = bht_wr_en0[1] & _T_11255; // @[ifu_bp_ctl.scala 442:45] - wire _T_15612 = _T_15608 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_0_5 = _T_15612 | _T_8915; // @[ifu_bp_ctl.scala 442:223] - wire _T_15625 = bht_wr_en0[1] & _T_11272; // @[ifu_bp_ctl.scala 442:45] - wire _T_15629 = _T_15625 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_0_6 = _T_15629 | _T_8924; // @[ifu_bp_ctl.scala 442:223] - wire _T_15642 = bht_wr_en0[1] & _T_11289; // @[ifu_bp_ctl.scala 442:45] - wire _T_15646 = _T_15642 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_0_7 = _T_15646 | _T_8933; // @[ifu_bp_ctl.scala 442:223] - wire _T_15659 = bht_wr_en0[1] & _T_11306; // @[ifu_bp_ctl.scala 442:45] - wire _T_15663 = _T_15659 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_0_8 = _T_15663 | _T_8942; // @[ifu_bp_ctl.scala 442:223] - wire _T_15676 = bht_wr_en0[1] & _T_11323; // @[ifu_bp_ctl.scala 442:45] - wire _T_15680 = _T_15676 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_0_9 = _T_15680 | _T_8951; // @[ifu_bp_ctl.scala 442:223] - wire _T_15693 = bht_wr_en0[1] & _T_11340; // @[ifu_bp_ctl.scala 442:45] - wire _T_15697 = _T_15693 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_0_10 = _T_15697 | _T_8960; // @[ifu_bp_ctl.scala 442:223] - wire _T_15710 = bht_wr_en0[1] & _T_11357; // @[ifu_bp_ctl.scala 442:45] - wire _T_15714 = _T_15710 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_0_11 = _T_15714 | _T_8969; // @[ifu_bp_ctl.scala 442:223] - wire _T_15727 = bht_wr_en0[1] & _T_11374; // @[ifu_bp_ctl.scala 442:45] - wire _T_15731 = _T_15727 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_0_12 = _T_15731 | _T_8978; // @[ifu_bp_ctl.scala 442:223] - wire _T_15744 = bht_wr_en0[1] & _T_11391; // @[ifu_bp_ctl.scala 442:45] - wire _T_15748 = _T_15744 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_0_13 = _T_15748 | _T_8987; // @[ifu_bp_ctl.scala 442:223] - wire _T_15761 = bht_wr_en0[1] & _T_11408; // @[ifu_bp_ctl.scala 442:45] - wire _T_15765 = _T_15761 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_0_14 = _T_15765 | _T_8996; // @[ifu_bp_ctl.scala 442:223] - wire _T_15778 = bht_wr_en0[1] & _T_11425; // @[ifu_bp_ctl.scala 442:45] - wire _T_15782 = _T_15778 & _T_6210; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_0_15 = _T_15782 | _T_9005; // @[ifu_bp_ctl.scala 442:223] - wire _T_15799 = _T_15523 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_1_0 = _T_15799 | _T_9014; // @[ifu_bp_ctl.scala 442:223] - wire _T_15816 = _T_15540 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_1_1 = _T_15816 | _T_9023; // @[ifu_bp_ctl.scala 442:223] - wire _T_15833 = _T_15557 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_1_2 = _T_15833 | _T_9032; // @[ifu_bp_ctl.scala 442:223] - wire _T_15850 = _T_15574 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_1_3 = _T_15850 | _T_9041; // @[ifu_bp_ctl.scala 442:223] - wire _T_15867 = _T_15591 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_1_4 = _T_15867 | _T_9050; // @[ifu_bp_ctl.scala 442:223] - wire _T_15884 = _T_15608 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_1_5 = _T_15884 | _T_9059; // @[ifu_bp_ctl.scala 442:223] - wire _T_15901 = _T_15625 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_1_6 = _T_15901 | _T_9068; // @[ifu_bp_ctl.scala 442:223] - wire _T_15918 = _T_15642 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_1_7 = _T_15918 | _T_9077; // @[ifu_bp_ctl.scala 442:223] - wire _T_15935 = _T_15659 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_1_8 = _T_15935 | _T_9086; // @[ifu_bp_ctl.scala 442:223] - wire _T_15952 = _T_15676 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_1_9 = _T_15952 | _T_9095; // @[ifu_bp_ctl.scala 442:223] - wire _T_15969 = _T_15693 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_1_10 = _T_15969 | _T_9104; // @[ifu_bp_ctl.scala 442:223] - wire _T_15986 = _T_15710 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_1_11 = _T_15986 | _T_9113; // @[ifu_bp_ctl.scala 442:223] - wire _T_16003 = _T_15727 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_1_12 = _T_16003 | _T_9122; // @[ifu_bp_ctl.scala 442:223] - wire _T_16020 = _T_15744 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_1_13 = _T_16020 | _T_9131; // @[ifu_bp_ctl.scala 442:223] - wire _T_16037 = _T_15761 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_1_14 = _T_16037 | _T_9140; // @[ifu_bp_ctl.scala 442:223] - wire _T_16054 = _T_15778 & _T_6221; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_1_15 = _T_16054 | _T_9149; // @[ifu_bp_ctl.scala 442:223] - wire _T_16071 = _T_15523 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_2_0 = _T_16071 | _T_9158; // @[ifu_bp_ctl.scala 442:223] - wire _T_16088 = _T_15540 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_2_1 = _T_16088 | _T_9167; // @[ifu_bp_ctl.scala 442:223] - wire _T_16105 = _T_15557 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_2_2 = _T_16105 | _T_9176; // @[ifu_bp_ctl.scala 442:223] - wire _T_16122 = _T_15574 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_2_3 = _T_16122 | _T_9185; // @[ifu_bp_ctl.scala 442:223] - wire _T_16139 = _T_15591 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_2_4 = _T_16139 | _T_9194; // @[ifu_bp_ctl.scala 442:223] - wire _T_16156 = _T_15608 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_2_5 = _T_16156 | _T_9203; // @[ifu_bp_ctl.scala 442:223] - wire _T_16173 = _T_15625 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_2_6 = _T_16173 | _T_9212; // @[ifu_bp_ctl.scala 442:223] - wire _T_16190 = _T_15642 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_2_7 = _T_16190 | _T_9221; // @[ifu_bp_ctl.scala 442:223] - wire _T_16207 = _T_15659 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_2_8 = _T_16207 | _T_9230; // @[ifu_bp_ctl.scala 442:223] - wire _T_16224 = _T_15676 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_2_9 = _T_16224 | _T_9239; // @[ifu_bp_ctl.scala 442:223] - wire _T_16241 = _T_15693 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_2_10 = _T_16241 | _T_9248; // @[ifu_bp_ctl.scala 442:223] - wire _T_16258 = _T_15710 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_2_11 = _T_16258 | _T_9257; // @[ifu_bp_ctl.scala 442:223] - wire _T_16275 = _T_15727 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_2_12 = _T_16275 | _T_9266; // @[ifu_bp_ctl.scala 442:223] - wire _T_16292 = _T_15744 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_2_13 = _T_16292 | _T_9275; // @[ifu_bp_ctl.scala 442:223] - wire _T_16309 = _T_15761 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_2_14 = _T_16309 | _T_9284; // @[ifu_bp_ctl.scala 442:223] - wire _T_16326 = _T_15778 & _T_6232; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_2_15 = _T_16326 | _T_9293; // @[ifu_bp_ctl.scala 442:223] - wire _T_16343 = _T_15523 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_3_0 = _T_16343 | _T_9302; // @[ifu_bp_ctl.scala 442:223] - wire _T_16360 = _T_15540 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_3_1 = _T_16360 | _T_9311; // @[ifu_bp_ctl.scala 442:223] - wire _T_16377 = _T_15557 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_3_2 = _T_16377 | _T_9320; // @[ifu_bp_ctl.scala 442:223] - wire _T_16394 = _T_15574 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_3_3 = _T_16394 | _T_9329; // @[ifu_bp_ctl.scala 442:223] - wire _T_16411 = _T_15591 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_3_4 = _T_16411 | _T_9338; // @[ifu_bp_ctl.scala 442:223] - wire _T_16428 = _T_15608 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_3_5 = _T_16428 | _T_9347; // @[ifu_bp_ctl.scala 442:223] - wire _T_16445 = _T_15625 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_3_6 = _T_16445 | _T_9356; // @[ifu_bp_ctl.scala 442:223] - wire _T_16462 = _T_15642 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_3_7 = _T_16462 | _T_9365; // @[ifu_bp_ctl.scala 442:223] - wire _T_16479 = _T_15659 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_3_8 = _T_16479 | _T_9374; // @[ifu_bp_ctl.scala 442:223] - wire _T_16496 = _T_15676 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_3_9 = _T_16496 | _T_9383; // @[ifu_bp_ctl.scala 442:223] - wire _T_16513 = _T_15693 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_3_10 = _T_16513 | _T_9392; // @[ifu_bp_ctl.scala 442:223] - wire _T_16530 = _T_15710 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_3_11 = _T_16530 | _T_9401; // @[ifu_bp_ctl.scala 442:223] - wire _T_16547 = _T_15727 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_3_12 = _T_16547 | _T_9410; // @[ifu_bp_ctl.scala 442:223] - wire _T_16564 = _T_15744 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_3_13 = _T_16564 | _T_9419; // @[ifu_bp_ctl.scala 442:223] - wire _T_16581 = _T_15761 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_3_14 = _T_16581 | _T_9428; // @[ifu_bp_ctl.scala 442:223] - wire _T_16598 = _T_15778 & _T_6243; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_3_15 = _T_16598 | _T_9437; // @[ifu_bp_ctl.scala 442:223] - wire _T_16615 = _T_15523 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_4_0 = _T_16615 | _T_9446; // @[ifu_bp_ctl.scala 442:223] - wire _T_16632 = _T_15540 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_4_1 = _T_16632 | _T_9455; // @[ifu_bp_ctl.scala 442:223] - wire _T_16649 = _T_15557 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_4_2 = _T_16649 | _T_9464; // @[ifu_bp_ctl.scala 442:223] - wire _T_16666 = _T_15574 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_4_3 = _T_16666 | _T_9473; // @[ifu_bp_ctl.scala 442:223] - wire _T_16683 = _T_15591 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_4_4 = _T_16683 | _T_9482; // @[ifu_bp_ctl.scala 442:223] - wire _T_16700 = _T_15608 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_4_5 = _T_16700 | _T_9491; // @[ifu_bp_ctl.scala 442:223] - wire _T_16717 = _T_15625 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_4_6 = _T_16717 | _T_9500; // @[ifu_bp_ctl.scala 442:223] - wire _T_16734 = _T_15642 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_4_7 = _T_16734 | _T_9509; // @[ifu_bp_ctl.scala 442:223] - wire _T_16751 = _T_15659 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_4_8 = _T_16751 | _T_9518; // @[ifu_bp_ctl.scala 442:223] - wire _T_16768 = _T_15676 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_4_9 = _T_16768 | _T_9527; // @[ifu_bp_ctl.scala 442:223] - wire _T_16785 = _T_15693 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_4_10 = _T_16785 | _T_9536; // @[ifu_bp_ctl.scala 442:223] - wire _T_16802 = _T_15710 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_4_11 = _T_16802 | _T_9545; // @[ifu_bp_ctl.scala 442:223] - wire _T_16819 = _T_15727 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_4_12 = _T_16819 | _T_9554; // @[ifu_bp_ctl.scala 442:223] - wire _T_16836 = _T_15744 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_4_13 = _T_16836 | _T_9563; // @[ifu_bp_ctl.scala 442:223] - wire _T_16853 = _T_15761 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_4_14 = _T_16853 | _T_9572; // @[ifu_bp_ctl.scala 442:223] - wire _T_16870 = _T_15778 & _T_6254; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_4_15 = _T_16870 | _T_9581; // @[ifu_bp_ctl.scala 442:223] - wire _T_16887 = _T_15523 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_5_0 = _T_16887 | _T_9590; // @[ifu_bp_ctl.scala 442:223] - wire _T_16904 = _T_15540 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_5_1 = _T_16904 | _T_9599; // @[ifu_bp_ctl.scala 442:223] - wire _T_16921 = _T_15557 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_5_2 = _T_16921 | _T_9608; // @[ifu_bp_ctl.scala 442:223] - wire _T_16938 = _T_15574 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_5_3 = _T_16938 | _T_9617; // @[ifu_bp_ctl.scala 442:223] - wire _T_16955 = _T_15591 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_5_4 = _T_16955 | _T_9626; // @[ifu_bp_ctl.scala 442:223] - wire _T_16972 = _T_15608 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_5_5 = _T_16972 | _T_9635; // @[ifu_bp_ctl.scala 442:223] - wire _T_16989 = _T_15625 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_5_6 = _T_16989 | _T_9644; // @[ifu_bp_ctl.scala 442:223] - wire _T_17006 = _T_15642 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_5_7 = _T_17006 | _T_9653; // @[ifu_bp_ctl.scala 442:223] - wire _T_17023 = _T_15659 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_5_8 = _T_17023 | _T_9662; // @[ifu_bp_ctl.scala 442:223] - wire _T_17040 = _T_15676 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_5_9 = _T_17040 | _T_9671; // @[ifu_bp_ctl.scala 442:223] - wire _T_17057 = _T_15693 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_5_10 = _T_17057 | _T_9680; // @[ifu_bp_ctl.scala 442:223] - wire _T_17074 = _T_15710 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_5_11 = _T_17074 | _T_9689; // @[ifu_bp_ctl.scala 442:223] - wire _T_17091 = _T_15727 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_5_12 = _T_17091 | _T_9698; // @[ifu_bp_ctl.scala 442:223] - wire _T_17108 = _T_15744 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_5_13 = _T_17108 | _T_9707; // @[ifu_bp_ctl.scala 442:223] - wire _T_17125 = _T_15761 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_5_14 = _T_17125 | _T_9716; // @[ifu_bp_ctl.scala 442:223] - wire _T_17142 = _T_15778 & _T_6265; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_5_15 = _T_17142 | _T_9725; // @[ifu_bp_ctl.scala 442:223] - wire _T_17159 = _T_15523 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_6_0 = _T_17159 | _T_9734; // @[ifu_bp_ctl.scala 442:223] - wire _T_17176 = _T_15540 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_6_1 = _T_17176 | _T_9743; // @[ifu_bp_ctl.scala 442:223] - wire _T_17193 = _T_15557 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_6_2 = _T_17193 | _T_9752; // @[ifu_bp_ctl.scala 442:223] - wire _T_17210 = _T_15574 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_6_3 = _T_17210 | _T_9761; // @[ifu_bp_ctl.scala 442:223] - wire _T_17227 = _T_15591 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_6_4 = _T_17227 | _T_9770; // @[ifu_bp_ctl.scala 442:223] - wire _T_17244 = _T_15608 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_6_5 = _T_17244 | _T_9779; // @[ifu_bp_ctl.scala 442:223] - wire _T_17261 = _T_15625 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_6_6 = _T_17261 | _T_9788; // @[ifu_bp_ctl.scala 442:223] - wire _T_17278 = _T_15642 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_6_7 = _T_17278 | _T_9797; // @[ifu_bp_ctl.scala 442:223] - wire _T_17295 = _T_15659 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_6_8 = _T_17295 | _T_9806; // @[ifu_bp_ctl.scala 442:223] - wire _T_17312 = _T_15676 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_6_9 = _T_17312 | _T_9815; // @[ifu_bp_ctl.scala 442:223] - wire _T_17329 = _T_15693 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_6_10 = _T_17329 | _T_9824; // @[ifu_bp_ctl.scala 442:223] - wire _T_17346 = _T_15710 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_6_11 = _T_17346 | _T_9833; // @[ifu_bp_ctl.scala 442:223] - wire _T_17363 = _T_15727 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_6_12 = _T_17363 | _T_9842; // @[ifu_bp_ctl.scala 442:223] - wire _T_17380 = _T_15744 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_6_13 = _T_17380 | _T_9851; // @[ifu_bp_ctl.scala 442:223] - wire _T_17397 = _T_15761 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_6_14 = _T_17397 | _T_9860; // @[ifu_bp_ctl.scala 442:223] - wire _T_17414 = _T_15778 & _T_6276; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_6_15 = _T_17414 | _T_9869; // @[ifu_bp_ctl.scala 442:223] - wire _T_17431 = _T_15523 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_7_0 = _T_17431 | _T_9878; // @[ifu_bp_ctl.scala 442:223] - wire _T_17448 = _T_15540 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_7_1 = _T_17448 | _T_9887; // @[ifu_bp_ctl.scala 442:223] - wire _T_17465 = _T_15557 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_7_2 = _T_17465 | _T_9896; // @[ifu_bp_ctl.scala 442:223] - wire _T_17482 = _T_15574 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_7_3 = _T_17482 | _T_9905; // @[ifu_bp_ctl.scala 442:223] - wire _T_17499 = _T_15591 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_7_4 = _T_17499 | _T_9914; // @[ifu_bp_ctl.scala 442:223] - wire _T_17516 = _T_15608 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_7_5 = _T_17516 | _T_9923; // @[ifu_bp_ctl.scala 442:223] - wire _T_17533 = _T_15625 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_7_6 = _T_17533 | _T_9932; // @[ifu_bp_ctl.scala 442:223] - wire _T_17550 = _T_15642 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_7_7 = _T_17550 | _T_9941; // @[ifu_bp_ctl.scala 442:223] - wire _T_17567 = _T_15659 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_7_8 = _T_17567 | _T_9950; // @[ifu_bp_ctl.scala 442:223] - wire _T_17584 = _T_15676 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_7_9 = _T_17584 | _T_9959; // @[ifu_bp_ctl.scala 442:223] - wire _T_17601 = _T_15693 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_7_10 = _T_17601 | _T_9968; // @[ifu_bp_ctl.scala 442:223] - wire _T_17618 = _T_15710 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_7_11 = _T_17618 | _T_9977; // @[ifu_bp_ctl.scala 442:223] - wire _T_17635 = _T_15727 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_7_12 = _T_17635 | _T_9986; // @[ifu_bp_ctl.scala 442:223] - wire _T_17652 = _T_15744 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_7_13 = _T_17652 | _T_9995; // @[ifu_bp_ctl.scala 442:223] - wire _T_17669 = _T_15761 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_7_14 = _T_17669 | _T_10004; // @[ifu_bp_ctl.scala 442:223] - wire _T_17686 = _T_15778 & _T_6287; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_7_15 = _T_17686 | _T_10013; // @[ifu_bp_ctl.scala 442:223] - wire _T_17703 = _T_15523 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_8_0 = _T_17703 | _T_10022; // @[ifu_bp_ctl.scala 442:223] - wire _T_17720 = _T_15540 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_8_1 = _T_17720 | _T_10031; // @[ifu_bp_ctl.scala 442:223] - wire _T_17737 = _T_15557 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_8_2 = _T_17737 | _T_10040; // @[ifu_bp_ctl.scala 442:223] - wire _T_17754 = _T_15574 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_8_3 = _T_17754 | _T_10049; // @[ifu_bp_ctl.scala 442:223] - wire _T_17771 = _T_15591 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_8_4 = _T_17771 | _T_10058; // @[ifu_bp_ctl.scala 442:223] - wire _T_17788 = _T_15608 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_8_5 = _T_17788 | _T_10067; // @[ifu_bp_ctl.scala 442:223] - wire _T_17805 = _T_15625 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_8_6 = _T_17805 | _T_10076; // @[ifu_bp_ctl.scala 442:223] - wire _T_17822 = _T_15642 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_8_7 = _T_17822 | _T_10085; // @[ifu_bp_ctl.scala 442:223] - wire _T_17839 = _T_15659 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_8_8 = _T_17839 | _T_10094; // @[ifu_bp_ctl.scala 442:223] - wire _T_17856 = _T_15676 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_8_9 = _T_17856 | _T_10103; // @[ifu_bp_ctl.scala 442:223] - wire _T_17873 = _T_15693 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_8_10 = _T_17873 | _T_10112; // @[ifu_bp_ctl.scala 442:223] - wire _T_17890 = _T_15710 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_8_11 = _T_17890 | _T_10121; // @[ifu_bp_ctl.scala 442:223] - wire _T_17907 = _T_15727 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_8_12 = _T_17907 | _T_10130; // @[ifu_bp_ctl.scala 442:223] - wire _T_17924 = _T_15744 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_8_13 = _T_17924 | _T_10139; // @[ifu_bp_ctl.scala 442:223] - wire _T_17941 = _T_15761 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_8_14 = _T_17941 | _T_10148; // @[ifu_bp_ctl.scala 442:223] - wire _T_17958 = _T_15778 & _T_6298; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_8_15 = _T_17958 | _T_10157; // @[ifu_bp_ctl.scala 442:223] - wire _T_17975 = _T_15523 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_9_0 = _T_17975 | _T_10166; // @[ifu_bp_ctl.scala 442:223] - wire _T_17992 = _T_15540 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_9_1 = _T_17992 | _T_10175; // @[ifu_bp_ctl.scala 442:223] - wire _T_18009 = _T_15557 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_9_2 = _T_18009 | _T_10184; // @[ifu_bp_ctl.scala 442:223] - wire _T_18026 = _T_15574 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_9_3 = _T_18026 | _T_10193; // @[ifu_bp_ctl.scala 442:223] - wire _T_18043 = _T_15591 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_9_4 = _T_18043 | _T_10202; // @[ifu_bp_ctl.scala 442:223] - wire _T_18060 = _T_15608 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_9_5 = _T_18060 | _T_10211; // @[ifu_bp_ctl.scala 442:223] - wire _T_18077 = _T_15625 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_9_6 = _T_18077 | _T_10220; // @[ifu_bp_ctl.scala 442:223] - wire _T_18094 = _T_15642 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_9_7 = _T_18094 | _T_10229; // @[ifu_bp_ctl.scala 442:223] - wire _T_18111 = _T_15659 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_9_8 = _T_18111 | _T_10238; // @[ifu_bp_ctl.scala 442:223] - wire _T_18128 = _T_15676 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_9_9 = _T_18128 | _T_10247; // @[ifu_bp_ctl.scala 442:223] - wire _T_18145 = _T_15693 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_9_10 = _T_18145 | _T_10256; // @[ifu_bp_ctl.scala 442:223] - wire _T_18162 = _T_15710 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_9_11 = _T_18162 | _T_10265; // @[ifu_bp_ctl.scala 442:223] - wire _T_18179 = _T_15727 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_9_12 = _T_18179 | _T_10274; // @[ifu_bp_ctl.scala 442:223] - wire _T_18196 = _T_15744 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_9_13 = _T_18196 | _T_10283; // @[ifu_bp_ctl.scala 442:223] - wire _T_18213 = _T_15761 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_9_14 = _T_18213 | _T_10292; // @[ifu_bp_ctl.scala 442:223] - wire _T_18230 = _T_15778 & _T_6309; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_9_15 = _T_18230 | _T_10301; // @[ifu_bp_ctl.scala 442:223] - wire _T_18247 = _T_15523 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_10_0 = _T_18247 | _T_10310; // @[ifu_bp_ctl.scala 442:223] - wire _T_18264 = _T_15540 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_10_1 = _T_18264 | _T_10319; // @[ifu_bp_ctl.scala 442:223] - wire _T_18281 = _T_15557 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_10_2 = _T_18281 | _T_10328; // @[ifu_bp_ctl.scala 442:223] - wire _T_18298 = _T_15574 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_10_3 = _T_18298 | _T_10337; // @[ifu_bp_ctl.scala 442:223] - wire _T_18315 = _T_15591 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_10_4 = _T_18315 | _T_10346; // @[ifu_bp_ctl.scala 442:223] - wire _T_18332 = _T_15608 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_10_5 = _T_18332 | _T_10355; // @[ifu_bp_ctl.scala 442:223] - wire _T_18349 = _T_15625 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_10_6 = _T_18349 | _T_10364; // @[ifu_bp_ctl.scala 442:223] - wire _T_18366 = _T_15642 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_10_7 = _T_18366 | _T_10373; // @[ifu_bp_ctl.scala 442:223] - wire _T_18383 = _T_15659 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_10_8 = _T_18383 | _T_10382; // @[ifu_bp_ctl.scala 442:223] - wire _T_18400 = _T_15676 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_10_9 = _T_18400 | _T_10391; // @[ifu_bp_ctl.scala 442:223] - wire _T_18417 = _T_15693 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_10_10 = _T_18417 | _T_10400; // @[ifu_bp_ctl.scala 442:223] - wire _T_18434 = _T_15710 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_10_11 = _T_18434 | _T_10409; // @[ifu_bp_ctl.scala 442:223] - wire _T_18451 = _T_15727 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_10_12 = _T_18451 | _T_10418; // @[ifu_bp_ctl.scala 442:223] - wire _T_18468 = _T_15744 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_10_13 = _T_18468 | _T_10427; // @[ifu_bp_ctl.scala 442:223] - wire _T_18485 = _T_15761 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_10_14 = _T_18485 | _T_10436; // @[ifu_bp_ctl.scala 442:223] - wire _T_18502 = _T_15778 & _T_6320; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_10_15 = _T_18502 | _T_10445; // @[ifu_bp_ctl.scala 442:223] - wire _T_18519 = _T_15523 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_11_0 = _T_18519 | _T_10454; // @[ifu_bp_ctl.scala 442:223] - wire _T_18536 = _T_15540 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_11_1 = _T_18536 | _T_10463; // @[ifu_bp_ctl.scala 442:223] - wire _T_18553 = _T_15557 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_11_2 = _T_18553 | _T_10472; // @[ifu_bp_ctl.scala 442:223] - wire _T_18570 = _T_15574 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_11_3 = _T_18570 | _T_10481; // @[ifu_bp_ctl.scala 442:223] - wire _T_18587 = _T_15591 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_11_4 = _T_18587 | _T_10490; // @[ifu_bp_ctl.scala 442:223] - wire _T_18604 = _T_15608 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_11_5 = _T_18604 | _T_10499; // @[ifu_bp_ctl.scala 442:223] - wire _T_18621 = _T_15625 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_11_6 = _T_18621 | _T_10508; // @[ifu_bp_ctl.scala 442:223] - wire _T_18638 = _T_15642 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_11_7 = _T_18638 | _T_10517; // @[ifu_bp_ctl.scala 442:223] - wire _T_18655 = _T_15659 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_11_8 = _T_18655 | _T_10526; // @[ifu_bp_ctl.scala 442:223] - wire _T_18672 = _T_15676 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_11_9 = _T_18672 | _T_10535; // @[ifu_bp_ctl.scala 442:223] - wire _T_18689 = _T_15693 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_11_10 = _T_18689 | _T_10544; // @[ifu_bp_ctl.scala 442:223] - wire _T_18706 = _T_15710 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_11_11 = _T_18706 | _T_10553; // @[ifu_bp_ctl.scala 442:223] - wire _T_18723 = _T_15727 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_11_12 = _T_18723 | _T_10562; // @[ifu_bp_ctl.scala 442:223] - wire _T_18740 = _T_15744 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_11_13 = _T_18740 | _T_10571; // @[ifu_bp_ctl.scala 442:223] - wire _T_18757 = _T_15761 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_11_14 = _T_18757 | _T_10580; // @[ifu_bp_ctl.scala 442:223] - wire _T_18774 = _T_15778 & _T_6331; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_11_15 = _T_18774 | _T_10589; // @[ifu_bp_ctl.scala 442:223] - wire _T_18791 = _T_15523 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_12_0 = _T_18791 | _T_10598; // @[ifu_bp_ctl.scala 442:223] - wire _T_18808 = _T_15540 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_12_1 = _T_18808 | _T_10607; // @[ifu_bp_ctl.scala 442:223] - wire _T_18825 = _T_15557 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_12_2 = _T_18825 | _T_10616; // @[ifu_bp_ctl.scala 442:223] - wire _T_18842 = _T_15574 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_12_3 = _T_18842 | _T_10625; // @[ifu_bp_ctl.scala 442:223] - wire _T_18859 = _T_15591 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_12_4 = _T_18859 | _T_10634; // @[ifu_bp_ctl.scala 442:223] - wire _T_18876 = _T_15608 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_12_5 = _T_18876 | _T_10643; // @[ifu_bp_ctl.scala 442:223] - wire _T_18893 = _T_15625 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_12_6 = _T_18893 | _T_10652; // @[ifu_bp_ctl.scala 442:223] - wire _T_18910 = _T_15642 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_12_7 = _T_18910 | _T_10661; // @[ifu_bp_ctl.scala 442:223] - wire _T_18927 = _T_15659 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_12_8 = _T_18927 | _T_10670; // @[ifu_bp_ctl.scala 442:223] - wire _T_18944 = _T_15676 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_12_9 = _T_18944 | _T_10679; // @[ifu_bp_ctl.scala 442:223] - wire _T_18961 = _T_15693 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_12_10 = _T_18961 | _T_10688; // @[ifu_bp_ctl.scala 442:223] - wire _T_18978 = _T_15710 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_12_11 = _T_18978 | _T_10697; // @[ifu_bp_ctl.scala 442:223] - wire _T_18995 = _T_15727 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_12_12 = _T_18995 | _T_10706; // @[ifu_bp_ctl.scala 442:223] - wire _T_19012 = _T_15744 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_12_13 = _T_19012 | _T_10715; // @[ifu_bp_ctl.scala 442:223] - wire _T_19029 = _T_15761 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_12_14 = _T_19029 | _T_10724; // @[ifu_bp_ctl.scala 442:223] - wire _T_19046 = _T_15778 & _T_6342; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_12_15 = _T_19046 | _T_10733; // @[ifu_bp_ctl.scala 442:223] - wire _T_19063 = _T_15523 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_13_0 = _T_19063 | _T_10742; // @[ifu_bp_ctl.scala 442:223] - wire _T_19080 = _T_15540 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_13_1 = _T_19080 | _T_10751; // @[ifu_bp_ctl.scala 442:223] - wire _T_19097 = _T_15557 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_13_2 = _T_19097 | _T_10760; // @[ifu_bp_ctl.scala 442:223] - wire _T_19114 = _T_15574 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_13_3 = _T_19114 | _T_10769; // @[ifu_bp_ctl.scala 442:223] - wire _T_19131 = _T_15591 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_13_4 = _T_19131 | _T_10778; // @[ifu_bp_ctl.scala 442:223] - wire _T_19148 = _T_15608 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_13_5 = _T_19148 | _T_10787; // @[ifu_bp_ctl.scala 442:223] - wire _T_19165 = _T_15625 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_13_6 = _T_19165 | _T_10796; // @[ifu_bp_ctl.scala 442:223] - wire _T_19182 = _T_15642 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_13_7 = _T_19182 | _T_10805; // @[ifu_bp_ctl.scala 442:223] - wire _T_19199 = _T_15659 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_13_8 = _T_19199 | _T_10814; // @[ifu_bp_ctl.scala 442:223] - wire _T_19216 = _T_15676 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_13_9 = _T_19216 | _T_10823; // @[ifu_bp_ctl.scala 442:223] - wire _T_19233 = _T_15693 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_13_10 = _T_19233 | _T_10832; // @[ifu_bp_ctl.scala 442:223] - wire _T_19250 = _T_15710 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_13_11 = _T_19250 | _T_10841; // @[ifu_bp_ctl.scala 442:223] - wire _T_19267 = _T_15727 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_13_12 = _T_19267 | _T_10850; // @[ifu_bp_ctl.scala 442:223] - wire _T_19284 = _T_15744 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_13_13 = _T_19284 | _T_10859; // @[ifu_bp_ctl.scala 442:223] - wire _T_19301 = _T_15761 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_13_14 = _T_19301 | _T_10868; // @[ifu_bp_ctl.scala 442:223] - wire _T_19318 = _T_15778 & _T_6353; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_13_15 = _T_19318 | _T_10877; // @[ifu_bp_ctl.scala 442:223] - wire _T_19335 = _T_15523 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_14_0 = _T_19335 | _T_10886; // @[ifu_bp_ctl.scala 442:223] - wire _T_19352 = _T_15540 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_14_1 = _T_19352 | _T_10895; // @[ifu_bp_ctl.scala 442:223] - wire _T_19369 = _T_15557 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_14_2 = _T_19369 | _T_10904; // @[ifu_bp_ctl.scala 442:223] - wire _T_19386 = _T_15574 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_14_3 = _T_19386 | _T_10913; // @[ifu_bp_ctl.scala 442:223] - wire _T_19403 = _T_15591 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_14_4 = _T_19403 | _T_10922; // @[ifu_bp_ctl.scala 442:223] - wire _T_19420 = _T_15608 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_14_5 = _T_19420 | _T_10931; // @[ifu_bp_ctl.scala 442:223] - wire _T_19437 = _T_15625 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_14_6 = _T_19437 | _T_10940; // @[ifu_bp_ctl.scala 442:223] - wire _T_19454 = _T_15642 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_14_7 = _T_19454 | _T_10949; // @[ifu_bp_ctl.scala 442:223] - wire _T_19471 = _T_15659 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_14_8 = _T_19471 | _T_10958; // @[ifu_bp_ctl.scala 442:223] - wire _T_19488 = _T_15676 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_14_9 = _T_19488 | _T_10967; // @[ifu_bp_ctl.scala 442:223] - wire _T_19505 = _T_15693 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_14_10 = _T_19505 | _T_10976; // @[ifu_bp_ctl.scala 442:223] - wire _T_19522 = _T_15710 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_14_11 = _T_19522 | _T_10985; // @[ifu_bp_ctl.scala 442:223] - wire _T_19539 = _T_15727 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_14_12 = _T_19539 | _T_10994; // @[ifu_bp_ctl.scala 442:223] - wire _T_19556 = _T_15744 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_14_13 = _T_19556 | _T_11003; // @[ifu_bp_ctl.scala 442:223] - wire _T_19573 = _T_15761 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_14_14 = _T_19573 | _T_11012; // @[ifu_bp_ctl.scala 442:223] - wire _T_19590 = _T_15778 & _T_6364; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_14_15 = _T_19590 | _T_11021; // @[ifu_bp_ctl.scala 442:223] - wire _T_19607 = _T_15523 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_15_0 = _T_19607 | _T_11030; // @[ifu_bp_ctl.scala 442:223] - wire _T_19624 = _T_15540 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_15_1 = _T_19624 | _T_11039; // @[ifu_bp_ctl.scala 442:223] - wire _T_19641 = _T_15557 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_15_2 = _T_19641 | _T_11048; // @[ifu_bp_ctl.scala 442:223] - wire _T_19658 = _T_15574 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_15_3 = _T_19658 | _T_11057; // @[ifu_bp_ctl.scala 442:223] - wire _T_19675 = _T_15591 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_15_4 = _T_19675 | _T_11066; // @[ifu_bp_ctl.scala 442:223] - wire _T_19692 = _T_15608 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_15_5 = _T_19692 | _T_11075; // @[ifu_bp_ctl.scala 442:223] - wire _T_19709 = _T_15625 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_15_6 = _T_19709 | _T_11084; // @[ifu_bp_ctl.scala 442:223] - wire _T_19726 = _T_15642 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_15_7 = _T_19726 | _T_11093; // @[ifu_bp_ctl.scala 442:223] - wire _T_19743 = _T_15659 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_15_8 = _T_19743 | _T_11102; // @[ifu_bp_ctl.scala 442:223] - wire _T_19760 = _T_15676 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_15_9 = _T_19760 | _T_11111; // @[ifu_bp_ctl.scala 442:223] - wire _T_19777 = _T_15693 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_15_10 = _T_19777 | _T_11120; // @[ifu_bp_ctl.scala 442:223] - wire _T_19794 = _T_15710 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_15_11 = _T_19794 | _T_11129; // @[ifu_bp_ctl.scala 442:223] - wire _T_19811 = _T_15727 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_15_12 = _T_19811 | _T_11138; // @[ifu_bp_ctl.scala 442:223] - wire _T_19828 = _T_15744 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_15_13 = _T_19828 | _T_11147; // @[ifu_bp_ctl.scala 442:223] - wire _T_19845 = _T_15761 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_15_14 = _T_19845 | _T_11156; // @[ifu_bp_ctl.scala 442:223] - wire _T_19862 = _T_15778 & _T_6375; // @[ifu_bp_ctl.scala 442:110] - wire bht_bank_sel_1_15_15 = _T_19862 | _T_11165; // @[ifu_bp_ctl.scala 442:223] + wire _T_576 = btb_wr_addr == 8'h0; // @[ifu_bp_ctl.scala 415:95] + wire _T_579 = btb_wr_addr == 8'h1; // @[ifu_bp_ctl.scala 415:95] + wire _T_582 = btb_wr_addr == 8'h2; // @[ifu_bp_ctl.scala 415:95] + wire _T_585 = btb_wr_addr == 8'h3; // @[ifu_bp_ctl.scala 415:95] + wire _T_588 = btb_wr_addr == 8'h4; // @[ifu_bp_ctl.scala 415:95] + wire _T_591 = btb_wr_addr == 8'h5; // @[ifu_bp_ctl.scala 415:95] + wire _T_594 = btb_wr_addr == 8'h6; // @[ifu_bp_ctl.scala 415:95] + wire _T_597 = btb_wr_addr == 8'h7; // @[ifu_bp_ctl.scala 415:95] + wire _T_600 = btb_wr_addr == 8'h8; // @[ifu_bp_ctl.scala 415:95] + wire _T_603 = btb_wr_addr == 8'h9; // @[ifu_bp_ctl.scala 415:95] + wire _T_606 = btb_wr_addr == 8'ha; // @[ifu_bp_ctl.scala 415:95] + wire _T_609 = btb_wr_addr == 8'hb; // @[ifu_bp_ctl.scala 415:95] + wire _T_612 = btb_wr_addr == 8'hc; // @[ifu_bp_ctl.scala 415:95] + wire _T_615 = btb_wr_addr == 8'hd; // @[ifu_bp_ctl.scala 415:95] + wire _T_618 = btb_wr_addr == 8'he; // @[ifu_bp_ctl.scala 415:95] + wire _T_621 = btb_wr_addr == 8'hf; // @[ifu_bp_ctl.scala 415:95] + wire _T_624 = btb_wr_addr == 8'h10; // @[ifu_bp_ctl.scala 415:95] + wire _T_627 = btb_wr_addr == 8'h11; // @[ifu_bp_ctl.scala 415:95] + wire _T_630 = btb_wr_addr == 8'h12; // @[ifu_bp_ctl.scala 415:95] + wire _T_633 = btb_wr_addr == 8'h13; // @[ifu_bp_ctl.scala 415:95] + wire _T_636 = btb_wr_addr == 8'h14; // @[ifu_bp_ctl.scala 415:95] + wire _T_639 = btb_wr_addr == 8'h15; // @[ifu_bp_ctl.scala 415:95] + wire _T_642 = btb_wr_addr == 8'h16; // @[ifu_bp_ctl.scala 415:95] + wire _T_645 = btb_wr_addr == 8'h17; // @[ifu_bp_ctl.scala 415:95] + wire _T_648 = btb_wr_addr == 8'h18; // @[ifu_bp_ctl.scala 415:95] + wire _T_651 = btb_wr_addr == 8'h19; // @[ifu_bp_ctl.scala 415:95] + wire _T_654 = btb_wr_addr == 8'h1a; // @[ifu_bp_ctl.scala 415:95] + wire _T_657 = btb_wr_addr == 8'h1b; // @[ifu_bp_ctl.scala 415:95] + wire _T_660 = btb_wr_addr == 8'h1c; // @[ifu_bp_ctl.scala 415:95] + wire _T_663 = btb_wr_addr == 8'h1d; // @[ifu_bp_ctl.scala 415:95] + wire _T_666 = btb_wr_addr == 8'h1e; // @[ifu_bp_ctl.scala 415:95] + wire _T_669 = btb_wr_addr == 8'h1f; // @[ifu_bp_ctl.scala 415:95] + wire _T_672 = btb_wr_addr == 8'h20; // @[ifu_bp_ctl.scala 415:95] + wire _T_675 = btb_wr_addr == 8'h21; // @[ifu_bp_ctl.scala 415:95] + wire _T_678 = btb_wr_addr == 8'h22; // @[ifu_bp_ctl.scala 415:95] + wire _T_681 = btb_wr_addr == 8'h23; // @[ifu_bp_ctl.scala 415:95] + wire _T_684 = btb_wr_addr == 8'h24; // @[ifu_bp_ctl.scala 415:95] + wire _T_687 = btb_wr_addr == 8'h25; // @[ifu_bp_ctl.scala 415:95] + wire _T_690 = btb_wr_addr == 8'h26; // @[ifu_bp_ctl.scala 415:95] + wire _T_693 = btb_wr_addr == 8'h27; // @[ifu_bp_ctl.scala 415:95] + wire _T_696 = btb_wr_addr == 8'h28; // @[ifu_bp_ctl.scala 415:95] + wire _T_699 = btb_wr_addr == 8'h29; // @[ifu_bp_ctl.scala 415:95] + wire _T_702 = btb_wr_addr == 8'h2a; // @[ifu_bp_ctl.scala 415:95] + wire _T_705 = btb_wr_addr == 8'h2b; // @[ifu_bp_ctl.scala 415:95] + wire _T_708 = btb_wr_addr == 8'h2c; // @[ifu_bp_ctl.scala 415:95] + wire _T_711 = btb_wr_addr == 8'h2d; // @[ifu_bp_ctl.scala 415:95] + wire _T_714 = btb_wr_addr == 8'h2e; // @[ifu_bp_ctl.scala 415:95] + wire _T_717 = btb_wr_addr == 8'h2f; // @[ifu_bp_ctl.scala 415:95] + wire _T_720 = btb_wr_addr == 8'h30; // @[ifu_bp_ctl.scala 415:95] + wire _T_723 = btb_wr_addr == 8'h31; // @[ifu_bp_ctl.scala 415:95] + wire _T_726 = btb_wr_addr == 8'h32; // @[ifu_bp_ctl.scala 415:95] + wire _T_729 = btb_wr_addr == 8'h33; // @[ifu_bp_ctl.scala 415:95] + wire _T_732 = btb_wr_addr == 8'h34; // @[ifu_bp_ctl.scala 415:95] + wire _T_735 = btb_wr_addr == 8'h35; // @[ifu_bp_ctl.scala 415:95] + wire _T_738 = btb_wr_addr == 8'h36; // @[ifu_bp_ctl.scala 415:95] + wire _T_741 = btb_wr_addr == 8'h37; // @[ifu_bp_ctl.scala 415:95] + wire _T_744 = btb_wr_addr == 8'h38; // @[ifu_bp_ctl.scala 415:95] + wire _T_747 = btb_wr_addr == 8'h39; // @[ifu_bp_ctl.scala 415:95] + wire _T_750 = btb_wr_addr == 8'h3a; // @[ifu_bp_ctl.scala 415:95] + wire _T_753 = btb_wr_addr == 8'h3b; // @[ifu_bp_ctl.scala 415:95] + wire _T_756 = btb_wr_addr == 8'h3c; // @[ifu_bp_ctl.scala 415:95] + wire _T_759 = btb_wr_addr == 8'h3d; // @[ifu_bp_ctl.scala 415:95] + wire _T_762 = btb_wr_addr == 8'h3e; // @[ifu_bp_ctl.scala 415:95] + wire _T_765 = btb_wr_addr == 8'h3f; // @[ifu_bp_ctl.scala 415:95] + wire _T_768 = btb_wr_addr == 8'h40; // @[ifu_bp_ctl.scala 415:95] + wire _T_771 = btb_wr_addr == 8'h41; // @[ifu_bp_ctl.scala 415:95] + wire _T_774 = btb_wr_addr == 8'h42; // @[ifu_bp_ctl.scala 415:95] + wire _T_777 = btb_wr_addr == 8'h43; // @[ifu_bp_ctl.scala 415:95] + wire _T_780 = btb_wr_addr == 8'h44; // @[ifu_bp_ctl.scala 415:95] + wire _T_783 = btb_wr_addr == 8'h45; // @[ifu_bp_ctl.scala 415:95] + wire _T_786 = btb_wr_addr == 8'h46; // @[ifu_bp_ctl.scala 415:95] + wire _T_789 = btb_wr_addr == 8'h47; // @[ifu_bp_ctl.scala 415:95] + wire _T_792 = btb_wr_addr == 8'h48; // @[ifu_bp_ctl.scala 415:95] + wire _T_795 = btb_wr_addr == 8'h49; // @[ifu_bp_ctl.scala 415:95] + wire _T_798 = btb_wr_addr == 8'h4a; // @[ifu_bp_ctl.scala 415:95] + wire _T_801 = btb_wr_addr == 8'h4b; // @[ifu_bp_ctl.scala 415:95] + wire _T_804 = btb_wr_addr == 8'h4c; // @[ifu_bp_ctl.scala 415:95] + wire _T_807 = btb_wr_addr == 8'h4d; // @[ifu_bp_ctl.scala 415:95] + wire _T_810 = btb_wr_addr == 8'h4e; // @[ifu_bp_ctl.scala 415:95] + wire _T_813 = btb_wr_addr == 8'h4f; // @[ifu_bp_ctl.scala 415:95] + wire _T_816 = btb_wr_addr == 8'h50; // @[ifu_bp_ctl.scala 415:95] + wire _T_819 = btb_wr_addr == 8'h51; // @[ifu_bp_ctl.scala 415:95] + wire _T_822 = btb_wr_addr == 8'h52; // @[ifu_bp_ctl.scala 415:95] + wire _T_825 = btb_wr_addr == 8'h53; // @[ifu_bp_ctl.scala 415:95] + wire _T_828 = btb_wr_addr == 8'h54; // @[ifu_bp_ctl.scala 415:95] + wire _T_831 = btb_wr_addr == 8'h55; // @[ifu_bp_ctl.scala 415:95] + wire _T_834 = btb_wr_addr == 8'h56; // @[ifu_bp_ctl.scala 415:95] + wire _T_837 = btb_wr_addr == 8'h57; // @[ifu_bp_ctl.scala 415:95] + wire _T_840 = btb_wr_addr == 8'h58; // @[ifu_bp_ctl.scala 415:95] + wire _T_843 = btb_wr_addr == 8'h59; // @[ifu_bp_ctl.scala 415:95] + wire _T_846 = btb_wr_addr == 8'h5a; // @[ifu_bp_ctl.scala 415:95] + wire _T_849 = btb_wr_addr == 8'h5b; // @[ifu_bp_ctl.scala 415:95] + wire _T_852 = btb_wr_addr == 8'h5c; // @[ifu_bp_ctl.scala 415:95] + wire _T_855 = btb_wr_addr == 8'h5d; // @[ifu_bp_ctl.scala 415:95] + wire _T_858 = btb_wr_addr == 8'h5e; // @[ifu_bp_ctl.scala 415:95] + wire _T_861 = btb_wr_addr == 8'h5f; // @[ifu_bp_ctl.scala 415:95] + wire _T_864 = btb_wr_addr == 8'h60; // @[ifu_bp_ctl.scala 415:95] + wire _T_867 = btb_wr_addr == 8'h61; // @[ifu_bp_ctl.scala 415:95] + wire _T_870 = btb_wr_addr == 8'h62; // @[ifu_bp_ctl.scala 415:95] + wire _T_873 = btb_wr_addr == 8'h63; // @[ifu_bp_ctl.scala 415:95] + wire _T_876 = btb_wr_addr == 8'h64; // @[ifu_bp_ctl.scala 415:95] + wire _T_879 = btb_wr_addr == 8'h65; // @[ifu_bp_ctl.scala 415:95] + wire _T_882 = btb_wr_addr == 8'h66; // @[ifu_bp_ctl.scala 415:95] + wire _T_885 = btb_wr_addr == 8'h67; // @[ifu_bp_ctl.scala 415:95] + wire _T_888 = btb_wr_addr == 8'h68; // @[ifu_bp_ctl.scala 415:95] + wire _T_891 = btb_wr_addr == 8'h69; // @[ifu_bp_ctl.scala 415:95] + wire _T_894 = btb_wr_addr == 8'h6a; // @[ifu_bp_ctl.scala 415:95] + wire _T_897 = btb_wr_addr == 8'h6b; // @[ifu_bp_ctl.scala 415:95] + wire _T_900 = btb_wr_addr == 8'h6c; // @[ifu_bp_ctl.scala 415:95] + wire _T_903 = btb_wr_addr == 8'h6d; // @[ifu_bp_ctl.scala 415:95] + wire _T_906 = btb_wr_addr == 8'h6e; // @[ifu_bp_ctl.scala 415:95] + wire _T_909 = btb_wr_addr == 8'h6f; // @[ifu_bp_ctl.scala 415:95] + wire _T_912 = btb_wr_addr == 8'h70; // @[ifu_bp_ctl.scala 415:95] + wire _T_915 = btb_wr_addr == 8'h71; // @[ifu_bp_ctl.scala 415:95] + wire _T_918 = btb_wr_addr == 8'h72; // @[ifu_bp_ctl.scala 415:95] + wire _T_921 = btb_wr_addr == 8'h73; // @[ifu_bp_ctl.scala 415:95] + wire _T_924 = btb_wr_addr == 8'h74; // @[ifu_bp_ctl.scala 415:95] + wire _T_927 = btb_wr_addr == 8'h75; // @[ifu_bp_ctl.scala 415:95] + wire _T_930 = btb_wr_addr == 8'h76; // @[ifu_bp_ctl.scala 415:95] + wire _T_933 = btb_wr_addr == 8'h77; // @[ifu_bp_ctl.scala 415:95] + wire _T_936 = btb_wr_addr == 8'h78; // @[ifu_bp_ctl.scala 415:95] + wire _T_939 = btb_wr_addr == 8'h79; // @[ifu_bp_ctl.scala 415:95] + wire _T_942 = btb_wr_addr == 8'h7a; // @[ifu_bp_ctl.scala 415:95] + wire _T_945 = btb_wr_addr == 8'h7b; // @[ifu_bp_ctl.scala 415:95] + wire _T_948 = btb_wr_addr == 8'h7c; // @[ifu_bp_ctl.scala 415:95] + wire _T_951 = btb_wr_addr == 8'h7d; // @[ifu_bp_ctl.scala 415:95] + wire _T_954 = btb_wr_addr == 8'h7e; // @[ifu_bp_ctl.scala 415:95] + wire _T_957 = btb_wr_addr == 8'h7f; // @[ifu_bp_ctl.scala 415:95] + wire _T_960 = btb_wr_addr == 8'h80; // @[ifu_bp_ctl.scala 415:95] + wire _T_963 = btb_wr_addr == 8'h81; // @[ifu_bp_ctl.scala 415:95] + wire _T_966 = btb_wr_addr == 8'h82; // @[ifu_bp_ctl.scala 415:95] + wire _T_969 = btb_wr_addr == 8'h83; // @[ifu_bp_ctl.scala 415:95] + wire _T_972 = btb_wr_addr == 8'h84; // @[ifu_bp_ctl.scala 415:95] + wire _T_975 = btb_wr_addr == 8'h85; // @[ifu_bp_ctl.scala 415:95] + wire _T_978 = btb_wr_addr == 8'h86; // @[ifu_bp_ctl.scala 415:95] + wire _T_981 = btb_wr_addr == 8'h87; // @[ifu_bp_ctl.scala 415:95] + wire _T_984 = btb_wr_addr == 8'h88; // @[ifu_bp_ctl.scala 415:95] + wire _T_987 = btb_wr_addr == 8'h89; // @[ifu_bp_ctl.scala 415:95] + wire _T_990 = btb_wr_addr == 8'h8a; // @[ifu_bp_ctl.scala 415:95] + wire _T_993 = btb_wr_addr == 8'h8b; // @[ifu_bp_ctl.scala 415:95] + wire _T_996 = btb_wr_addr == 8'h8c; // @[ifu_bp_ctl.scala 415:95] + wire _T_999 = btb_wr_addr == 8'h8d; // @[ifu_bp_ctl.scala 415:95] + wire _T_1002 = btb_wr_addr == 8'h8e; // @[ifu_bp_ctl.scala 415:95] + wire _T_1005 = btb_wr_addr == 8'h8f; // @[ifu_bp_ctl.scala 415:95] + wire _T_1008 = btb_wr_addr == 8'h90; // @[ifu_bp_ctl.scala 415:95] + wire _T_1011 = btb_wr_addr == 8'h91; // @[ifu_bp_ctl.scala 415:95] + wire _T_1014 = btb_wr_addr == 8'h92; // @[ifu_bp_ctl.scala 415:95] + wire _T_1017 = btb_wr_addr == 8'h93; // @[ifu_bp_ctl.scala 415:95] + wire _T_1020 = btb_wr_addr == 8'h94; // @[ifu_bp_ctl.scala 415:95] + wire _T_1023 = btb_wr_addr == 8'h95; // @[ifu_bp_ctl.scala 415:95] + wire _T_1026 = btb_wr_addr == 8'h96; // @[ifu_bp_ctl.scala 415:95] + wire _T_1029 = btb_wr_addr == 8'h97; // @[ifu_bp_ctl.scala 415:95] + wire _T_1032 = btb_wr_addr == 8'h98; // @[ifu_bp_ctl.scala 415:95] + wire _T_1035 = btb_wr_addr == 8'h99; // @[ifu_bp_ctl.scala 415:95] + wire _T_1038 = btb_wr_addr == 8'h9a; // @[ifu_bp_ctl.scala 415:95] + wire _T_1041 = btb_wr_addr == 8'h9b; // @[ifu_bp_ctl.scala 415:95] + wire _T_1044 = btb_wr_addr == 8'h9c; // @[ifu_bp_ctl.scala 415:95] + wire _T_1047 = btb_wr_addr == 8'h9d; // @[ifu_bp_ctl.scala 415:95] + wire _T_1050 = btb_wr_addr == 8'h9e; // @[ifu_bp_ctl.scala 415:95] + wire _T_1053 = btb_wr_addr == 8'h9f; // @[ifu_bp_ctl.scala 415:95] + wire _T_1056 = btb_wr_addr == 8'ha0; // @[ifu_bp_ctl.scala 415:95] + wire _T_1059 = btb_wr_addr == 8'ha1; // @[ifu_bp_ctl.scala 415:95] + wire _T_1062 = btb_wr_addr == 8'ha2; // @[ifu_bp_ctl.scala 415:95] + wire _T_1065 = btb_wr_addr == 8'ha3; // @[ifu_bp_ctl.scala 415:95] + wire _T_1068 = btb_wr_addr == 8'ha4; // @[ifu_bp_ctl.scala 415:95] + wire _T_1071 = btb_wr_addr == 8'ha5; // @[ifu_bp_ctl.scala 415:95] + wire _T_1074 = btb_wr_addr == 8'ha6; // @[ifu_bp_ctl.scala 415:95] + wire _T_1077 = btb_wr_addr == 8'ha7; // @[ifu_bp_ctl.scala 415:95] + wire _T_1080 = btb_wr_addr == 8'ha8; // @[ifu_bp_ctl.scala 415:95] + wire _T_1083 = btb_wr_addr == 8'ha9; // @[ifu_bp_ctl.scala 415:95] + wire _T_1086 = btb_wr_addr == 8'haa; // @[ifu_bp_ctl.scala 415:95] + wire _T_1089 = btb_wr_addr == 8'hab; // @[ifu_bp_ctl.scala 415:95] + wire _T_1092 = btb_wr_addr == 8'hac; // @[ifu_bp_ctl.scala 415:95] + wire _T_1095 = btb_wr_addr == 8'had; // @[ifu_bp_ctl.scala 415:95] + wire _T_1098 = btb_wr_addr == 8'hae; // @[ifu_bp_ctl.scala 415:95] + wire _T_1101 = btb_wr_addr == 8'haf; // @[ifu_bp_ctl.scala 415:95] + wire _T_1104 = btb_wr_addr == 8'hb0; // @[ifu_bp_ctl.scala 415:95] + wire _T_1107 = btb_wr_addr == 8'hb1; // @[ifu_bp_ctl.scala 415:95] + wire _T_1110 = btb_wr_addr == 8'hb2; // @[ifu_bp_ctl.scala 415:95] + wire _T_1113 = btb_wr_addr == 8'hb3; // @[ifu_bp_ctl.scala 415:95] + wire _T_1116 = btb_wr_addr == 8'hb4; // @[ifu_bp_ctl.scala 415:95] + wire _T_1119 = btb_wr_addr == 8'hb5; // @[ifu_bp_ctl.scala 415:95] + wire _T_1122 = btb_wr_addr == 8'hb6; // @[ifu_bp_ctl.scala 415:95] + wire _T_1125 = btb_wr_addr == 8'hb7; // @[ifu_bp_ctl.scala 415:95] + wire _T_1128 = btb_wr_addr == 8'hb8; // @[ifu_bp_ctl.scala 415:95] + wire _T_1131 = btb_wr_addr == 8'hb9; // @[ifu_bp_ctl.scala 415:95] + wire _T_1134 = btb_wr_addr == 8'hba; // @[ifu_bp_ctl.scala 415:95] + wire _T_1137 = btb_wr_addr == 8'hbb; // @[ifu_bp_ctl.scala 415:95] + wire _T_1140 = btb_wr_addr == 8'hbc; // @[ifu_bp_ctl.scala 415:95] + wire _T_1143 = btb_wr_addr == 8'hbd; // @[ifu_bp_ctl.scala 415:95] + wire _T_1146 = btb_wr_addr == 8'hbe; // @[ifu_bp_ctl.scala 415:95] + wire _T_1149 = btb_wr_addr == 8'hbf; // @[ifu_bp_ctl.scala 415:95] + wire _T_1152 = btb_wr_addr == 8'hc0; // @[ifu_bp_ctl.scala 415:95] + wire _T_1155 = btb_wr_addr == 8'hc1; // @[ifu_bp_ctl.scala 415:95] + wire _T_1158 = btb_wr_addr == 8'hc2; // @[ifu_bp_ctl.scala 415:95] + wire _T_1161 = btb_wr_addr == 8'hc3; // @[ifu_bp_ctl.scala 415:95] + wire _T_1164 = btb_wr_addr == 8'hc4; // @[ifu_bp_ctl.scala 415:95] + wire _T_1167 = btb_wr_addr == 8'hc5; // @[ifu_bp_ctl.scala 415:95] + wire _T_1170 = btb_wr_addr == 8'hc6; // @[ifu_bp_ctl.scala 415:95] + wire _T_1173 = btb_wr_addr == 8'hc7; // @[ifu_bp_ctl.scala 415:95] + wire _T_1176 = btb_wr_addr == 8'hc8; // @[ifu_bp_ctl.scala 415:95] + wire _T_1179 = btb_wr_addr == 8'hc9; // @[ifu_bp_ctl.scala 415:95] + wire _T_1182 = btb_wr_addr == 8'hca; // @[ifu_bp_ctl.scala 415:95] + wire _T_1185 = btb_wr_addr == 8'hcb; // @[ifu_bp_ctl.scala 415:95] + wire _T_1188 = btb_wr_addr == 8'hcc; // @[ifu_bp_ctl.scala 415:95] + wire _T_1191 = btb_wr_addr == 8'hcd; // @[ifu_bp_ctl.scala 415:95] + wire _T_1194 = btb_wr_addr == 8'hce; // @[ifu_bp_ctl.scala 415:95] + wire _T_1197 = btb_wr_addr == 8'hcf; // @[ifu_bp_ctl.scala 415:95] + wire _T_1200 = btb_wr_addr == 8'hd0; // @[ifu_bp_ctl.scala 415:95] + wire _T_1203 = btb_wr_addr == 8'hd1; // @[ifu_bp_ctl.scala 415:95] + wire _T_1206 = btb_wr_addr == 8'hd2; // @[ifu_bp_ctl.scala 415:95] + wire _T_1209 = btb_wr_addr == 8'hd3; // @[ifu_bp_ctl.scala 415:95] + wire _T_1212 = btb_wr_addr == 8'hd4; // @[ifu_bp_ctl.scala 415:95] + wire _T_1215 = btb_wr_addr == 8'hd5; // @[ifu_bp_ctl.scala 415:95] + wire _T_1218 = btb_wr_addr == 8'hd6; // @[ifu_bp_ctl.scala 415:95] + wire _T_1221 = btb_wr_addr == 8'hd7; // @[ifu_bp_ctl.scala 415:95] + wire _T_1224 = btb_wr_addr == 8'hd8; // @[ifu_bp_ctl.scala 415:95] + wire _T_1227 = btb_wr_addr == 8'hd9; // @[ifu_bp_ctl.scala 415:95] + wire _T_1230 = btb_wr_addr == 8'hda; // @[ifu_bp_ctl.scala 415:95] + wire _T_1233 = btb_wr_addr == 8'hdb; // @[ifu_bp_ctl.scala 415:95] + wire _T_1236 = btb_wr_addr == 8'hdc; // @[ifu_bp_ctl.scala 415:95] + wire _T_1239 = btb_wr_addr == 8'hdd; // @[ifu_bp_ctl.scala 415:95] + wire _T_1242 = btb_wr_addr == 8'hde; // @[ifu_bp_ctl.scala 415:95] + wire _T_1245 = btb_wr_addr == 8'hdf; // @[ifu_bp_ctl.scala 415:95] + wire _T_1248 = btb_wr_addr == 8'he0; // @[ifu_bp_ctl.scala 415:95] + wire _T_1251 = btb_wr_addr == 8'he1; // @[ifu_bp_ctl.scala 415:95] + wire _T_1254 = btb_wr_addr == 8'he2; // @[ifu_bp_ctl.scala 415:95] + wire _T_1257 = btb_wr_addr == 8'he3; // @[ifu_bp_ctl.scala 415:95] + wire _T_1260 = btb_wr_addr == 8'he4; // @[ifu_bp_ctl.scala 415:95] + wire _T_1263 = btb_wr_addr == 8'he5; // @[ifu_bp_ctl.scala 415:95] + wire _T_1266 = btb_wr_addr == 8'he6; // @[ifu_bp_ctl.scala 415:95] + wire _T_1269 = btb_wr_addr == 8'he7; // @[ifu_bp_ctl.scala 415:95] + wire _T_1272 = btb_wr_addr == 8'he8; // @[ifu_bp_ctl.scala 415:95] + wire _T_1275 = btb_wr_addr == 8'he9; // @[ifu_bp_ctl.scala 415:95] + wire _T_1278 = btb_wr_addr == 8'hea; // @[ifu_bp_ctl.scala 415:95] + wire _T_1281 = btb_wr_addr == 8'heb; // @[ifu_bp_ctl.scala 415:95] + wire _T_1284 = btb_wr_addr == 8'hec; // @[ifu_bp_ctl.scala 415:95] + wire _T_1287 = btb_wr_addr == 8'hed; // @[ifu_bp_ctl.scala 415:95] + wire _T_1290 = btb_wr_addr == 8'hee; // @[ifu_bp_ctl.scala 415:95] + wire _T_1293 = btb_wr_addr == 8'hef; // @[ifu_bp_ctl.scala 415:95] + wire _T_1296 = btb_wr_addr == 8'hf0; // @[ifu_bp_ctl.scala 415:95] + wire _T_1299 = btb_wr_addr == 8'hf1; // @[ifu_bp_ctl.scala 415:95] + wire _T_1302 = btb_wr_addr == 8'hf2; // @[ifu_bp_ctl.scala 415:95] + wire _T_1305 = btb_wr_addr == 8'hf3; // @[ifu_bp_ctl.scala 415:95] + wire _T_1308 = btb_wr_addr == 8'hf4; // @[ifu_bp_ctl.scala 415:95] + wire _T_1311 = btb_wr_addr == 8'hf5; // @[ifu_bp_ctl.scala 415:95] + wire _T_1314 = btb_wr_addr == 8'hf6; // @[ifu_bp_ctl.scala 415:95] + wire _T_1317 = btb_wr_addr == 8'hf7; // @[ifu_bp_ctl.scala 415:95] + wire _T_1320 = btb_wr_addr == 8'hf8; // @[ifu_bp_ctl.scala 415:95] + wire _T_1323 = btb_wr_addr == 8'hf9; // @[ifu_bp_ctl.scala 415:95] + wire _T_1326 = btb_wr_addr == 8'hfa; // @[ifu_bp_ctl.scala 415:95] + wire _T_1329 = btb_wr_addr == 8'hfb; // @[ifu_bp_ctl.scala 415:95] + wire _T_1332 = btb_wr_addr == 8'hfc; // @[ifu_bp_ctl.scala 415:95] + wire _T_1335 = btb_wr_addr == 8'hfd; // @[ifu_bp_ctl.scala 415:95] + wire _T_1338 = btb_wr_addr == 8'hfe; // @[ifu_bp_ctl.scala 415:95] + wire _T_1341 = btb_wr_addr == 8'hff; // @[ifu_bp_ctl.scala 415:95] + wire _T_6210 = bht_wr_addr0[7:4] == 4'h0; // @[ifu_bp_ctl.scala 429:109] + wire _T_6212 = bht_wr_en0[0] & _T_6210; // @[ifu_bp_ctl.scala 429:44] + wire _T_6215 = bht_wr_addr2[7:4] == 4'h0; // @[ifu_bp_ctl.scala 430:109] + wire _T_6217 = bht_wr_en2[0] & _T_6215; // @[ifu_bp_ctl.scala 430:44] + wire _T_6221 = bht_wr_addr0[7:4] == 4'h1; // @[ifu_bp_ctl.scala 429:109] + wire _T_6223 = bht_wr_en0[0] & _T_6221; // @[ifu_bp_ctl.scala 429:44] + wire _T_6226 = bht_wr_addr2[7:4] == 4'h1; // @[ifu_bp_ctl.scala 430:109] + wire _T_6228 = bht_wr_en2[0] & _T_6226; // @[ifu_bp_ctl.scala 430:44] + wire _T_6232 = bht_wr_addr0[7:4] == 4'h2; // @[ifu_bp_ctl.scala 429:109] + wire _T_6234 = bht_wr_en0[0] & _T_6232; // @[ifu_bp_ctl.scala 429:44] + wire _T_6237 = bht_wr_addr2[7:4] == 4'h2; // @[ifu_bp_ctl.scala 430:109] + wire _T_6239 = bht_wr_en2[0] & _T_6237; // @[ifu_bp_ctl.scala 430:44] + wire _T_6243 = bht_wr_addr0[7:4] == 4'h3; // @[ifu_bp_ctl.scala 429:109] + wire _T_6245 = bht_wr_en0[0] & _T_6243; // @[ifu_bp_ctl.scala 429:44] + wire _T_6248 = bht_wr_addr2[7:4] == 4'h3; // @[ifu_bp_ctl.scala 430:109] + wire _T_6250 = bht_wr_en2[0] & _T_6248; // @[ifu_bp_ctl.scala 430:44] + wire _T_6254 = bht_wr_addr0[7:4] == 4'h4; // @[ifu_bp_ctl.scala 429:109] + wire _T_6256 = bht_wr_en0[0] & _T_6254; // @[ifu_bp_ctl.scala 429:44] + wire _T_6259 = bht_wr_addr2[7:4] == 4'h4; // @[ifu_bp_ctl.scala 430:109] + wire _T_6261 = bht_wr_en2[0] & _T_6259; // @[ifu_bp_ctl.scala 430:44] + wire _T_6265 = bht_wr_addr0[7:4] == 4'h5; // @[ifu_bp_ctl.scala 429:109] + wire _T_6267 = bht_wr_en0[0] & _T_6265; // @[ifu_bp_ctl.scala 429:44] + wire _T_6270 = bht_wr_addr2[7:4] == 4'h5; // @[ifu_bp_ctl.scala 430:109] + wire _T_6272 = bht_wr_en2[0] & _T_6270; // @[ifu_bp_ctl.scala 430:44] + wire _T_6276 = bht_wr_addr0[7:4] == 4'h6; // @[ifu_bp_ctl.scala 429:109] + wire _T_6278 = bht_wr_en0[0] & _T_6276; // @[ifu_bp_ctl.scala 429:44] + wire _T_6281 = bht_wr_addr2[7:4] == 4'h6; // @[ifu_bp_ctl.scala 430:109] + wire _T_6283 = bht_wr_en2[0] & _T_6281; // @[ifu_bp_ctl.scala 430:44] + wire _T_6287 = bht_wr_addr0[7:4] == 4'h7; // @[ifu_bp_ctl.scala 429:109] + wire _T_6289 = bht_wr_en0[0] & _T_6287; // @[ifu_bp_ctl.scala 429:44] + wire _T_6292 = bht_wr_addr2[7:4] == 4'h7; // @[ifu_bp_ctl.scala 430:109] + wire _T_6294 = bht_wr_en2[0] & _T_6292; // @[ifu_bp_ctl.scala 430:44] + wire _T_6298 = bht_wr_addr0[7:4] == 4'h8; // @[ifu_bp_ctl.scala 429:109] + wire _T_6300 = bht_wr_en0[0] & _T_6298; // @[ifu_bp_ctl.scala 429:44] + wire _T_6303 = bht_wr_addr2[7:4] == 4'h8; // @[ifu_bp_ctl.scala 430:109] + wire _T_6305 = bht_wr_en2[0] & _T_6303; // @[ifu_bp_ctl.scala 430:44] + wire _T_6309 = bht_wr_addr0[7:4] == 4'h9; // @[ifu_bp_ctl.scala 429:109] + wire _T_6311 = bht_wr_en0[0] & _T_6309; // @[ifu_bp_ctl.scala 429:44] + wire _T_6314 = bht_wr_addr2[7:4] == 4'h9; // @[ifu_bp_ctl.scala 430:109] + wire _T_6316 = bht_wr_en2[0] & _T_6314; // @[ifu_bp_ctl.scala 430:44] + wire _T_6320 = bht_wr_addr0[7:4] == 4'ha; // @[ifu_bp_ctl.scala 429:109] + wire _T_6322 = bht_wr_en0[0] & _T_6320; // @[ifu_bp_ctl.scala 429:44] + wire _T_6325 = bht_wr_addr2[7:4] == 4'ha; // @[ifu_bp_ctl.scala 430:109] + wire _T_6327 = bht_wr_en2[0] & _T_6325; // @[ifu_bp_ctl.scala 430:44] + wire _T_6331 = bht_wr_addr0[7:4] == 4'hb; // @[ifu_bp_ctl.scala 429:109] + wire _T_6333 = bht_wr_en0[0] & _T_6331; // @[ifu_bp_ctl.scala 429:44] + wire _T_6336 = bht_wr_addr2[7:4] == 4'hb; // @[ifu_bp_ctl.scala 430:109] + wire _T_6338 = bht_wr_en2[0] & _T_6336; // @[ifu_bp_ctl.scala 430:44] + wire _T_6342 = bht_wr_addr0[7:4] == 4'hc; // @[ifu_bp_ctl.scala 429:109] + wire _T_6344 = bht_wr_en0[0] & _T_6342; // @[ifu_bp_ctl.scala 429:44] + wire _T_6347 = bht_wr_addr2[7:4] == 4'hc; // @[ifu_bp_ctl.scala 430:109] + wire _T_6349 = bht_wr_en2[0] & _T_6347; // @[ifu_bp_ctl.scala 430:44] + wire _T_6353 = bht_wr_addr0[7:4] == 4'hd; // @[ifu_bp_ctl.scala 429:109] + wire _T_6355 = bht_wr_en0[0] & _T_6353; // @[ifu_bp_ctl.scala 429:44] + wire _T_6358 = bht_wr_addr2[7:4] == 4'hd; // @[ifu_bp_ctl.scala 430:109] + wire _T_6360 = bht_wr_en2[0] & _T_6358; // @[ifu_bp_ctl.scala 430:44] + wire _T_6364 = bht_wr_addr0[7:4] == 4'he; // @[ifu_bp_ctl.scala 429:109] + wire _T_6366 = bht_wr_en0[0] & _T_6364; // @[ifu_bp_ctl.scala 429:44] + wire _T_6369 = bht_wr_addr2[7:4] == 4'he; // @[ifu_bp_ctl.scala 430:109] + wire _T_6371 = bht_wr_en2[0] & _T_6369; // @[ifu_bp_ctl.scala 430:44] + wire _T_6375 = bht_wr_addr0[7:4] == 4'hf; // @[ifu_bp_ctl.scala 429:109] + wire _T_6377 = bht_wr_en0[0] & _T_6375; // @[ifu_bp_ctl.scala 429:44] + wire _T_6380 = bht_wr_addr2[7:4] == 4'hf; // @[ifu_bp_ctl.scala 430:109] + wire _T_6382 = bht_wr_en2[0] & _T_6380; // @[ifu_bp_ctl.scala 430:44] + wire _T_6388 = bht_wr_en0[1] & _T_6210; // @[ifu_bp_ctl.scala 429:44] + wire _T_6393 = bht_wr_en2[1] & _T_6215; // @[ifu_bp_ctl.scala 430:44] + wire _T_6399 = bht_wr_en0[1] & _T_6221; // @[ifu_bp_ctl.scala 429:44] + wire _T_6404 = bht_wr_en2[1] & _T_6226; // @[ifu_bp_ctl.scala 430:44] + wire _T_6410 = bht_wr_en0[1] & _T_6232; // @[ifu_bp_ctl.scala 429:44] + wire _T_6415 = bht_wr_en2[1] & _T_6237; // @[ifu_bp_ctl.scala 430:44] + wire _T_6421 = bht_wr_en0[1] & _T_6243; // @[ifu_bp_ctl.scala 429:44] + wire _T_6426 = bht_wr_en2[1] & _T_6248; // @[ifu_bp_ctl.scala 430:44] + wire _T_6432 = bht_wr_en0[1] & _T_6254; // @[ifu_bp_ctl.scala 429:44] + wire _T_6437 = bht_wr_en2[1] & _T_6259; // @[ifu_bp_ctl.scala 430:44] + wire _T_6443 = bht_wr_en0[1] & _T_6265; // @[ifu_bp_ctl.scala 429:44] + wire _T_6448 = bht_wr_en2[1] & _T_6270; // @[ifu_bp_ctl.scala 430:44] + wire _T_6454 = bht_wr_en0[1] & _T_6276; // @[ifu_bp_ctl.scala 429:44] + wire _T_6459 = bht_wr_en2[1] & _T_6281; // @[ifu_bp_ctl.scala 430:44] + wire _T_6465 = bht_wr_en0[1] & _T_6287; // @[ifu_bp_ctl.scala 429:44] + wire _T_6470 = bht_wr_en2[1] & _T_6292; // @[ifu_bp_ctl.scala 430:44] + wire _T_6476 = bht_wr_en0[1] & _T_6298; // @[ifu_bp_ctl.scala 429:44] + wire _T_6481 = bht_wr_en2[1] & _T_6303; // @[ifu_bp_ctl.scala 430:44] + wire _T_6487 = bht_wr_en0[1] & _T_6309; // @[ifu_bp_ctl.scala 429:44] + wire _T_6492 = bht_wr_en2[1] & _T_6314; // @[ifu_bp_ctl.scala 430:44] + wire _T_6498 = bht_wr_en0[1] & _T_6320; // @[ifu_bp_ctl.scala 429:44] + wire _T_6503 = bht_wr_en2[1] & _T_6325; // @[ifu_bp_ctl.scala 430:44] + wire _T_6509 = bht_wr_en0[1] & _T_6331; // @[ifu_bp_ctl.scala 429:44] + wire _T_6514 = bht_wr_en2[1] & _T_6336; // @[ifu_bp_ctl.scala 430:44] + wire _T_6520 = bht_wr_en0[1] & _T_6342; // @[ifu_bp_ctl.scala 429:44] + wire _T_6525 = bht_wr_en2[1] & _T_6347; // @[ifu_bp_ctl.scala 430:44] + wire _T_6531 = bht_wr_en0[1] & _T_6353; // @[ifu_bp_ctl.scala 429:44] + wire _T_6536 = bht_wr_en2[1] & _T_6358; // @[ifu_bp_ctl.scala 430:44] + wire _T_6542 = bht_wr_en0[1] & _T_6364; // @[ifu_bp_ctl.scala 429:44] + wire _T_6547 = bht_wr_en2[1] & _T_6369; // @[ifu_bp_ctl.scala 430:44] + wire _T_6553 = bht_wr_en0[1] & _T_6375; // @[ifu_bp_ctl.scala 429:44] + wire _T_6558 = bht_wr_en2[1] & _T_6380; // @[ifu_bp_ctl.scala 430:44] + wire _T_6562 = bht_wr_addr2[3:0] == 4'h0; // @[ifu_bp_ctl.scala 435:74] + wire _T_6563 = bht_wr_en2[0] & _T_6562; // @[ifu_bp_ctl.scala 435:23] + wire _T_6566 = _T_6563 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_6571 = bht_wr_addr2[3:0] == 4'h1; // @[ifu_bp_ctl.scala 435:74] + wire _T_6572 = bht_wr_en2[0] & _T_6571; // @[ifu_bp_ctl.scala 435:23] + wire _T_6575 = _T_6572 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_6580 = bht_wr_addr2[3:0] == 4'h2; // @[ifu_bp_ctl.scala 435:74] + wire _T_6581 = bht_wr_en2[0] & _T_6580; // @[ifu_bp_ctl.scala 435:23] + wire _T_6584 = _T_6581 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_6589 = bht_wr_addr2[3:0] == 4'h3; // @[ifu_bp_ctl.scala 435:74] + wire _T_6590 = bht_wr_en2[0] & _T_6589; // @[ifu_bp_ctl.scala 435:23] + wire _T_6593 = _T_6590 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_6598 = bht_wr_addr2[3:0] == 4'h4; // @[ifu_bp_ctl.scala 435:74] + wire _T_6599 = bht_wr_en2[0] & _T_6598; // @[ifu_bp_ctl.scala 435:23] + wire _T_6602 = _T_6599 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_6607 = bht_wr_addr2[3:0] == 4'h5; // @[ifu_bp_ctl.scala 435:74] + wire _T_6608 = bht_wr_en2[0] & _T_6607; // @[ifu_bp_ctl.scala 435:23] + wire _T_6611 = _T_6608 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_6616 = bht_wr_addr2[3:0] == 4'h6; // @[ifu_bp_ctl.scala 435:74] + wire _T_6617 = bht_wr_en2[0] & _T_6616; // @[ifu_bp_ctl.scala 435:23] + wire _T_6620 = _T_6617 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_6625 = bht_wr_addr2[3:0] == 4'h7; // @[ifu_bp_ctl.scala 435:74] + wire _T_6626 = bht_wr_en2[0] & _T_6625; // @[ifu_bp_ctl.scala 435:23] + wire _T_6629 = _T_6626 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_6634 = bht_wr_addr2[3:0] == 4'h8; // @[ifu_bp_ctl.scala 435:74] + wire _T_6635 = bht_wr_en2[0] & _T_6634; // @[ifu_bp_ctl.scala 435:23] + wire _T_6638 = _T_6635 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_6643 = bht_wr_addr2[3:0] == 4'h9; // @[ifu_bp_ctl.scala 435:74] + wire _T_6644 = bht_wr_en2[0] & _T_6643; // @[ifu_bp_ctl.scala 435:23] + wire _T_6647 = _T_6644 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_6652 = bht_wr_addr2[3:0] == 4'ha; // @[ifu_bp_ctl.scala 435:74] + wire _T_6653 = bht_wr_en2[0] & _T_6652; // @[ifu_bp_ctl.scala 435:23] + wire _T_6656 = _T_6653 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_6661 = bht_wr_addr2[3:0] == 4'hb; // @[ifu_bp_ctl.scala 435:74] + wire _T_6662 = bht_wr_en2[0] & _T_6661; // @[ifu_bp_ctl.scala 435:23] + wire _T_6665 = _T_6662 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_6670 = bht_wr_addr2[3:0] == 4'hc; // @[ifu_bp_ctl.scala 435:74] + wire _T_6671 = bht_wr_en2[0] & _T_6670; // @[ifu_bp_ctl.scala 435:23] + wire _T_6674 = _T_6671 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_6679 = bht_wr_addr2[3:0] == 4'hd; // @[ifu_bp_ctl.scala 435:74] + wire _T_6680 = bht_wr_en2[0] & _T_6679; // @[ifu_bp_ctl.scala 435:23] + wire _T_6683 = _T_6680 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_6688 = bht_wr_addr2[3:0] == 4'he; // @[ifu_bp_ctl.scala 435:74] + wire _T_6689 = bht_wr_en2[0] & _T_6688; // @[ifu_bp_ctl.scala 435:23] + wire _T_6692 = _T_6689 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_6697 = bht_wr_addr2[3:0] == 4'hf; // @[ifu_bp_ctl.scala 435:74] + wire _T_6698 = bht_wr_en2[0] & _T_6697; // @[ifu_bp_ctl.scala 435:23] + wire _T_6701 = _T_6698 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_6710 = _T_6563 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_6719 = _T_6572 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_6728 = _T_6581 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_6737 = _T_6590 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_6746 = _T_6599 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_6755 = _T_6608 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_6764 = _T_6617 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_6773 = _T_6626 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_6782 = _T_6635 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_6791 = _T_6644 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_6800 = _T_6653 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_6809 = _T_6662 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_6818 = _T_6671 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_6827 = _T_6680 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_6836 = _T_6689 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_6845 = _T_6698 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_6854 = _T_6563 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_6863 = _T_6572 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_6872 = _T_6581 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_6881 = _T_6590 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_6890 = _T_6599 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_6899 = _T_6608 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_6908 = _T_6617 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_6917 = _T_6626 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_6926 = _T_6635 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_6935 = _T_6644 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_6944 = _T_6653 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_6953 = _T_6662 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_6962 = _T_6671 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_6971 = _T_6680 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_6980 = _T_6689 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_6989 = _T_6698 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_6998 = _T_6563 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_7007 = _T_6572 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_7016 = _T_6581 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_7025 = _T_6590 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_7034 = _T_6599 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_7043 = _T_6608 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_7052 = _T_6617 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_7061 = _T_6626 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_7070 = _T_6635 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_7079 = _T_6644 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_7088 = _T_6653 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_7097 = _T_6662 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_7106 = _T_6671 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_7115 = _T_6680 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_7124 = _T_6689 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_7133 = _T_6698 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_7142 = _T_6563 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_7151 = _T_6572 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_7160 = _T_6581 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_7169 = _T_6590 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_7178 = _T_6599 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_7187 = _T_6608 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_7196 = _T_6617 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_7205 = _T_6626 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_7214 = _T_6635 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_7223 = _T_6644 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_7232 = _T_6653 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_7241 = _T_6662 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_7250 = _T_6671 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_7259 = _T_6680 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_7268 = _T_6689 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_7277 = _T_6698 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_7286 = _T_6563 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_7295 = _T_6572 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_7304 = _T_6581 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_7313 = _T_6590 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_7322 = _T_6599 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_7331 = _T_6608 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_7340 = _T_6617 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_7349 = _T_6626 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_7358 = _T_6635 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_7367 = _T_6644 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_7376 = _T_6653 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_7385 = _T_6662 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_7394 = _T_6671 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_7403 = _T_6680 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_7412 = _T_6689 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_7421 = _T_6698 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_7430 = _T_6563 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_7439 = _T_6572 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_7448 = _T_6581 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_7457 = _T_6590 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_7466 = _T_6599 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_7475 = _T_6608 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_7484 = _T_6617 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_7493 = _T_6626 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_7502 = _T_6635 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_7511 = _T_6644 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_7520 = _T_6653 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_7529 = _T_6662 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_7538 = _T_6671 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_7547 = _T_6680 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_7556 = _T_6689 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_7565 = _T_6698 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_7574 = _T_6563 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_7583 = _T_6572 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_7592 = _T_6581 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_7601 = _T_6590 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_7610 = _T_6599 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_7619 = _T_6608 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_7628 = _T_6617 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_7637 = _T_6626 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_7646 = _T_6635 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_7655 = _T_6644 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_7664 = _T_6653 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_7673 = _T_6662 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_7682 = _T_6671 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_7691 = _T_6680 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_7700 = _T_6689 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_7709 = _T_6698 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_7718 = _T_6563 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_7727 = _T_6572 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_7736 = _T_6581 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_7745 = _T_6590 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_7754 = _T_6599 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_7763 = _T_6608 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_7772 = _T_6617 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_7781 = _T_6626 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_7790 = _T_6635 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_7799 = _T_6644 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_7808 = _T_6653 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_7817 = _T_6662 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_7826 = _T_6671 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_7835 = _T_6680 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_7844 = _T_6689 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_7853 = _T_6698 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_7862 = _T_6563 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_7871 = _T_6572 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_7880 = _T_6581 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_7889 = _T_6590 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_7898 = _T_6599 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_7907 = _T_6608 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_7916 = _T_6617 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_7925 = _T_6626 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_7934 = _T_6635 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_7943 = _T_6644 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_7952 = _T_6653 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_7961 = _T_6662 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_7970 = _T_6671 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_7979 = _T_6680 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_7988 = _T_6689 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_7997 = _T_6698 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_8006 = _T_6563 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_8015 = _T_6572 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_8024 = _T_6581 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_8033 = _T_6590 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_8042 = _T_6599 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_8051 = _T_6608 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_8060 = _T_6617 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_8069 = _T_6626 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_8078 = _T_6635 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_8087 = _T_6644 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_8096 = _T_6653 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_8105 = _T_6662 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_8114 = _T_6671 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_8123 = _T_6680 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_8132 = _T_6689 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_8141 = _T_6698 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_8150 = _T_6563 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_8159 = _T_6572 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_8168 = _T_6581 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_8177 = _T_6590 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_8186 = _T_6599 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_8195 = _T_6608 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_8204 = _T_6617 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_8213 = _T_6626 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_8222 = _T_6635 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_8231 = _T_6644 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_8240 = _T_6653 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_8249 = _T_6662 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_8258 = _T_6671 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_8267 = _T_6680 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_8276 = _T_6689 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_8285 = _T_6698 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_8294 = _T_6563 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_8303 = _T_6572 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_8312 = _T_6581 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_8321 = _T_6590 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_8330 = _T_6599 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_8339 = _T_6608 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_8348 = _T_6617 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_8357 = _T_6626 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_8366 = _T_6635 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_8375 = _T_6644 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_8384 = _T_6653 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_8393 = _T_6662 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_8402 = _T_6671 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_8411 = _T_6680 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_8420 = _T_6689 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_8429 = _T_6698 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_8438 = _T_6563 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_8447 = _T_6572 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_8456 = _T_6581 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_8465 = _T_6590 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_8474 = _T_6599 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_8483 = _T_6608 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_8492 = _T_6617 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_8501 = _T_6626 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_8510 = _T_6635 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_8519 = _T_6644 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_8528 = _T_6653 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_8537 = _T_6662 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_8546 = _T_6671 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_8555 = _T_6680 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_8564 = _T_6689 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_8573 = _T_6698 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_8582 = _T_6563 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_8591 = _T_6572 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_8600 = _T_6581 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_8609 = _T_6590 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_8618 = _T_6599 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_8627 = _T_6608 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_8636 = _T_6617 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_8645 = _T_6626 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_8654 = _T_6635 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_8663 = _T_6644 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_8672 = _T_6653 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_8681 = _T_6662 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_8690 = _T_6671 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_8699 = _T_6680 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_8708 = _T_6689 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_8717 = _T_6698 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_8726 = _T_6563 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_8735 = _T_6572 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_8744 = _T_6581 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_8753 = _T_6590 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_8762 = _T_6599 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_8771 = _T_6608 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_8780 = _T_6617 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_8789 = _T_6626 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_8798 = _T_6635 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_8807 = _T_6644 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_8816 = _T_6653 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_8825 = _T_6662 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_8834 = _T_6671 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_8843 = _T_6680 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_8852 = _T_6689 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_8861 = _T_6698 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_8867 = bht_wr_en2[1] & _T_6562; // @[ifu_bp_ctl.scala 435:23] + wire _T_8870 = _T_8867 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_8876 = bht_wr_en2[1] & _T_6571; // @[ifu_bp_ctl.scala 435:23] + wire _T_8879 = _T_8876 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_8885 = bht_wr_en2[1] & _T_6580; // @[ifu_bp_ctl.scala 435:23] + wire _T_8888 = _T_8885 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_8894 = bht_wr_en2[1] & _T_6589; // @[ifu_bp_ctl.scala 435:23] + wire _T_8897 = _T_8894 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_8903 = bht_wr_en2[1] & _T_6598; // @[ifu_bp_ctl.scala 435:23] + wire _T_8906 = _T_8903 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_8912 = bht_wr_en2[1] & _T_6607; // @[ifu_bp_ctl.scala 435:23] + wire _T_8915 = _T_8912 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_8921 = bht_wr_en2[1] & _T_6616; // @[ifu_bp_ctl.scala 435:23] + wire _T_8924 = _T_8921 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_8930 = bht_wr_en2[1] & _T_6625; // @[ifu_bp_ctl.scala 435:23] + wire _T_8933 = _T_8930 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_8939 = bht_wr_en2[1] & _T_6634; // @[ifu_bp_ctl.scala 435:23] + wire _T_8942 = _T_8939 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_8948 = bht_wr_en2[1] & _T_6643; // @[ifu_bp_ctl.scala 435:23] + wire _T_8951 = _T_8948 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_8957 = bht_wr_en2[1] & _T_6652; // @[ifu_bp_ctl.scala 435:23] + wire _T_8960 = _T_8957 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_8966 = bht_wr_en2[1] & _T_6661; // @[ifu_bp_ctl.scala 435:23] + wire _T_8969 = _T_8966 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_8975 = bht_wr_en2[1] & _T_6670; // @[ifu_bp_ctl.scala 435:23] + wire _T_8978 = _T_8975 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_8984 = bht_wr_en2[1] & _T_6679; // @[ifu_bp_ctl.scala 435:23] + wire _T_8987 = _T_8984 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_8993 = bht_wr_en2[1] & _T_6688; // @[ifu_bp_ctl.scala 435:23] + wire _T_8996 = _T_8993 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_9002 = bht_wr_en2[1] & _T_6697; // @[ifu_bp_ctl.scala 435:23] + wire _T_9005 = _T_9002 & _T_6215; // @[ifu_bp_ctl.scala 435:81] + wire _T_9014 = _T_8867 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_9023 = _T_8876 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_9032 = _T_8885 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_9041 = _T_8894 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_9050 = _T_8903 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_9059 = _T_8912 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_9068 = _T_8921 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_9077 = _T_8930 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_9086 = _T_8939 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_9095 = _T_8948 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_9104 = _T_8957 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_9113 = _T_8966 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_9122 = _T_8975 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_9131 = _T_8984 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_9140 = _T_8993 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_9149 = _T_9002 & _T_6226; // @[ifu_bp_ctl.scala 435:81] + wire _T_9158 = _T_8867 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_9167 = _T_8876 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_9176 = _T_8885 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_9185 = _T_8894 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_9194 = _T_8903 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_9203 = _T_8912 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_9212 = _T_8921 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_9221 = _T_8930 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_9230 = _T_8939 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_9239 = _T_8948 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_9248 = _T_8957 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_9257 = _T_8966 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_9266 = _T_8975 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_9275 = _T_8984 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_9284 = _T_8993 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_9293 = _T_9002 & _T_6237; // @[ifu_bp_ctl.scala 435:81] + wire _T_9302 = _T_8867 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_9311 = _T_8876 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_9320 = _T_8885 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_9329 = _T_8894 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_9338 = _T_8903 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_9347 = _T_8912 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_9356 = _T_8921 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_9365 = _T_8930 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_9374 = _T_8939 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_9383 = _T_8948 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_9392 = _T_8957 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_9401 = _T_8966 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_9410 = _T_8975 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_9419 = _T_8984 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_9428 = _T_8993 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_9437 = _T_9002 & _T_6248; // @[ifu_bp_ctl.scala 435:81] + wire _T_9446 = _T_8867 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_9455 = _T_8876 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_9464 = _T_8885 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_9473 = _T_8894 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_9482 = _T_8903 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_9491 = _T_8912 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_9500 = _T_8921 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_9509 = _T_8930 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_9518 = _T_8939 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_9527 = _T_8948 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_9536 = _T_8957 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_9545 = _T_8966 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_9554 = _T_8975 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_9563 = _T_8984 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_9572 = _T_8993 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_9581 = _T_9002 & _T_6259; // @[ifu_bp_ctl.scala 435:81] + wire _T_9590 = _T_8867 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_9599 = _T_8876 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_9608 = _T_8885 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_9617 = _T_8894 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_9626 = _T_8903 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_9635 = _T_8912 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_9644 = _T_8921 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_9653 = _T_8930 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_9662 = _T_8939 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_9671 = _T_8948 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_9680 = _T_8957 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_9689 = _T_8966 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_9698 = _T_8975 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_9707 = _T_8984 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_9716 = _T_8993 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_9725 = _T_9002 & _T_6270; // @[ifu_bp_ctl.scala 435:81] + wire _T_9734 = _T_8867 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_9743 = _T_8876 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_9752 = _T_8885 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_9761 = _T_8894 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_9770 = _T_8903 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_9779 = _T_8912 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_9788 = _T_8921 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_9797 = _T_8930 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_9806 = _T_8939 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_9815 = _T_8948 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_9824 = _T_8957 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_9833 = _T_8966 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_9842 = _T_8975 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_9851 = _T_8984 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_9860 = _T_8993 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_9869 = _T_9002 & _T_6281; // @[ifu_bp_ctl.scala 435:81] + wire _T_9878 = _T_8867 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_9887 = _T_8876 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_9896 = _T_8885 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_9905 = _T_8894 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_9914 = _T_8903 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_9923 = _T_8912 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_9932 = _T_8921 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_9941 = _T_8930 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_9950 = _T_8939 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_9959 = _T_8948 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_9968 = _T_8957 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_9977 = _T_8966 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_9986 = _T_8975 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_9995 = _T_8984 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_10004 = _T_8993 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_10013 = _T_9002 & _T_6292; // @[ifu_bp_ctl.scala 435:81] + wire _T_10022 = _T_8867 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_10031 = _T_8876 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_10040 = _T_8885 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_10049 = _T_8894 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_10058 = _T_8903 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_10067 = _T_8912 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_10076 = _T_8921 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_10085 = _T_8930 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_10094 = _T_8939 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_10103 = _T_8948 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_10112 = _T_8957 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_10121 = _T_8966 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_10130 = _T_8975 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_10139 = _T_8984 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_10148 = _T_8993 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_10157 = _T_9002 & _T_6303; // @[ifu_bp_ctl.scala 435:81] + wire _T_10166 = _T_8867 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_10175 = _T_8876 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_10184 = _T_8885 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_10193 = _T_8894 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_10202 = _T_8903 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_10211 = _T_8912 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_10220 = _T_8921 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_10229 = _T_8930 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_10238 = _T_8939 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_10247 = _T_8948 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_10256 = _T_8957 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_10265 = _T_8966 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_10274 = _T_8975 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_10283 = _T_8984 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_10292 = _T_8993 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_10301 = _T_9002 & _T_6314; // @[ifu_bp_ctl.scala 435:81] + wire _T_10310 = _T_8867 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_10319 = _T_8876 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_10328 = _T_8885 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_10337 = _T_8894 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_10346 = _T_8903 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_10355 = _T_8912 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_10364 = _T_8921 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_10373 = _T_8930 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_10382 = _T_8939 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_10391 = _T_8948 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_10400 = _T_8957 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_10409 = _T_8966 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_10418 = _T_8975 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_10427 = _T_8984 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_10436 = _T_8993 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_10445 = _T_9002 & _T_6325; // @[ifu_bp_ctl.scala 435:81] + wire _T_10454 = _T_8867 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_10463 = _T_8876 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_10472 = _T_8885 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_10481 = _T_8894 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_10490 = _T_8903 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_10499 = _T_8912 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_10508 = _T_8921 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_10517 = _T_8930 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_10526 = _T_8939 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_10535 = _T_8948 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_10544 = _T_8957 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_10553 = _T_8966 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_10562 = _T_8975 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_10571 = _T_8984 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_10580 = _T_8993 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_10589 = _T_9002 & _T_6336; // @[ifu_bp_ctl.scala 435:81] + wire _T_10598 = _T_8867 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_10607 = _T_8876 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_10616 = _T_8885 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_10625 = _T_8894 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_10634 = _T_8903 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_10643 = _T_8912 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_10652 = _T_8921 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_10661 = _T_8930 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_10670 = _T_8939 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_10679 = _T_8948 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_10688 = _T_8957 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_10697 = _T_8966 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_10706 = _T_8975 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_10715 = _T_8984 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_10724 = _T_8993 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_10733 = _T_9002 & _T_6347; // @[ifu_bp_ctl.scala 435:81] + wire _T_10742 = _T_8867 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_10751 = _T_8876 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_10760 = _T_8885 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_10769 = _T_8894 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_10778 = _T_8903 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_10787 = _T_8912 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_10796 = _T_8921 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_10805 = _T_8930 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_10814 = _T_8939 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_10823 = _T_8948 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_10832 = _T_8957 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_10841 = _T_8966 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_10850 = _T_8975 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_10859 = _T_8984 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_10868 = _T_8993 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_10877 = _T_9002 & _T_6358; // @[ifu_bp_ctl.scala 435:81] + wire _T_10886 = _T_8867 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_10895 = _T_8876 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_10904 = _T_8885 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_10913 = _T_8894 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_10922 = _T_8903 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_10931 = _T_8912 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_10940 = _T_8921 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_10949 = _T_8930 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_10958 = _T_8939 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_10967 = _T_8948 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_10976 = _T_8957 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_10985 = _T_8966 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_10994 = _T_8975 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_11003 = _T_8984 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_11012 = _T_8993 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_11021 = _T_9002 & _T_6369; // @[ifu_bp_ctl.scala 435:81] + wire _T_11030 = _T_8867 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_11039 = _T_8876 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_11048 = _T_8885 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_11057 = _T_8894 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_11066 = _T_8903 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_11075 = _T_8912 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_11084 = _T_8921 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_11093 = _T_8930 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_11102 = _T_8939 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_11111 = _T_8948 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_11120 = _T_8957 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_11129 = _T_8966 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_11138 = _T_8975 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_11147 = _T_8984 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_11156 = _T_8993 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_11165 = _T_9002 & _T_6380; // @[ifu_bp_ctl.scala 435:81] + wire _T_11170 = bht_wr_addr0[3:0] == 4'h0; // @[ifu_bp_ctl.scala 443:97] + wire _T_11171 = bht_wr_en0[0] & _T_11170; // @[ifu_bp_ctl.scala 443:45] + wire _T_11175 = _T_11171 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_0_0 = _T_11175 | _T_6566; // @[ifu_bp_ctl.scala 443:223] + wire _T_11187 = bht_wr_addr0[3:0] == 4'h1; // @[ifu_bp_ctl.scala 443:97] + wire _T_11188 = bht_wr_en0[0] & _T_11187; // @[ifu_bp_ctl.scala 443:45] + wire _T_11192 = _T_11188 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_0_1 = _T_11192 | _T_6575; // @[ifu_bp_ctl.scala 443:223] + wire _T_11204 = bht_wr_addr0[3:0] == 4'h2; // @[ifu_bp_ctl.scala 443:97] + wire _T_11205 = bht_wr_en0[0] & _T_11204; // @[ifu_bp_ctl.scala 443:45] + wire _T_11209 = _T_11205 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_0_2 = _T_11209 | _T_6584; // @[ifu_bp_ctl.scala 443:223] + wire _T_11221 = bht_wr_addr0[3:0] == 4'h3; // @[ifu_bp_ctl.scala 443:97] + wire _T_11222 = bht_wr_en0[0] & _T_11221; // @[ifu_bp_ctl.scala 443:45] + wire _T_11226 = _T_11222 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_0_3 = _T_11226 | _T_6593; // @[ifu_bp_ctl.scala 443:223] + wire _T_11238 = bht_wr_addr0[3:0] == 4'h4; // @[ifu_bp_ctl.scala 443:97] + wire _T_11239 = bht_wr_en0[0] & _T_11238; // @[ifu_bp_ctl.scala 443:45] + wire _T_11243 = _T_11239 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_0_4 = _T_11243 | _T_6602; // @[ifu_bp_ctl.scala 443:223] + wire _T_11255 = bht_wr_addr0[3:0] == 4'h5; // @[ifu_bp_ctl.scala 443:97] + wire _T_11256 = bht_wr_en0[0] & _T_11255; // @[ifu_bp_ctl.scala 443:45] + wire _T_11260 = _T_11256 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_0_5 = _T_11260 | _T_6611; // @[ifu_bp_ctl.scala 443:223] + wire _T_11272 = bht_wr_addr0[3:0] == 4'h6; // @[ifu_bp_ctl.scala 443:97] + wire _T_11273 = bht_wr_en0[0] & _T_11272; // @[ifu_bp_ctl.scala 443:45] + wire _T_11277 = _T_11273 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_0_6 = _T_11277 | _T_6620; // @[ifu_bp_ctl.scala 443:223] + wire _T_11289 = bht_wr_addr0[3:0] == 4'h7; // @[ifu_bp_ctl.scala 443:97] + wire _T_11290 = bht_wr_en0[0] & _T_11289; // @[ifu_bp_ctl.scala 443:45] + wire _T_11294 = _T_11290 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_0_7 = _T_11294 | _T_6629; // @[ifu_bp_ctl.scala 443:223] + wire _T_11306 = bht_wr_addr0[3:0] == 4'h8; // @[ifu_bp_ctl.scala 443:97] + wire _T_11307 = bht_wr_en0[0] & _T_11306; // @[ifu_bp_ctl.scala 443:45] + wire _T_11311 = _T_11307 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_0_8 = _T_11311 | _T_6638; // @[ifu_bp_ctl.scala 443:223] + wire _T_11323 = bht_wr_addr0[3:0] == 4'h9; // @[ifu_bp_ctl.scala 443:97] + wire _T_11324 = bht_wr_en0[0] & _T_11323; // @[ifu_bp_ctl.scala 443:45] + wire _T_11328 = _T_11324 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_0_9 = _T_11328 | _T_6647; // @[ifu_bp_ctl.scala 443:223] + wire _T_11340 = bht_wr_addr0[3:0] == 4'ha; // @[ifu_bp_ctl.scala 443:97] + wire _T_11341 = bht_wr_en0[0] & _T_11340; // @[ifu_bp_ctl.scala 443:45] + wire _T_11345 = _T_11341 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_0_10 = _T_11345 | _T_6656; // @[ifu_bp_ctl.scala 443:223] + wire _T_11357 = bht_wr_addr0[3:0] == 4'hb; // @[ifu_bp_ctl.scala 443:97] + wire _T_11358 = bht_wr_en0[0] & _T_11357; // @[ifu_bp_ctl.scala 443:45] + wire _T_11362 = _T_11358 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_0_11 = _T_11362 | _T_6665; // @[ifu_bp_ctl.scala 443:223] + wire _T_11374 = bht_wr_addr0[3:0] == 4'hc; // @[ifu_bp_ctl.scala 443:97] + wire _T_11375 = bht_wr_en0[0] & _T_11374; // @[ifu_bp_ctl.scala 443:45] + wire _T_11379 = _T_11375 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_0_12 = _T_11379 | _T_6674; // @[ifu_bp_ctl.scala 443:223] + wire _T_11391 = bht_wr_addr0[3:0] == 4'hd; // @[ifu_bp_ctl.scala 443:97] + wire _T_11392 = bht_wr_en0[0] & _T_11391; // @[ifu_bp_ctl.scala 443:45] + wire _T_11396 = _T_11392 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_0_13 = _T_11396 | _T_6683; // @[ifu_bp_ctl.scala 443:223] + wire _T_11408 = bht_wr_addr0[3:0] == 4'he; // @[ifu_bp_ctl.scala 443:97] + wire _T_11409 = bht_wr_en0[0] & _T_11408; // @[ifu_bp_ctl.scala 443:45] + wire _T_11413 = _T_11409 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_0_14 = _T_11413 | _T_6692; // @[ifu_bp_ctl.scala 443:223] + wire _T_11425 = bht_wr_addr0[3:0] == 4'hf; // @[ifu_bp_ctl.scala 443:97] + wire _T_11426 = bht_wr_en0[0] & _T_11425; // @[ifu_bp_ctl.scala 443:45] + wire _T_11430 = _T_11426 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_0_15 = _T_11430 | _T_6701; // @[ifu_bp_ctl.scala 443:223] + wire _T_11447 = _T_11171 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_1_0 = _T_11447 | _T_6710; // @[ifu_bp_ctl.scala 443:223] + wire _T_11464 = _T_11188 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_1_1 = _T_11464 | _T_6719; // @[ifu_bp_ctl.scala 443:223] + wire _T_11481 = _T_11205 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_1_2 = _T_11481 | _T_6728; // @[ifu_bp_ctl.scala 443:223] + wire _T_11498 = _T_11222 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_1_3 = _T_11498 | _T_6737; // @[ifu_bp_ctl.scala 443:223] + wire _T_11515 = _T_11239 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_1_4 = _T_11515 | _T_6746; // @[ifu_bp_ctl.scala 443:223] + wire _T_11532 = _T_11256 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_1_5 = _T_11532 | _T_6755; // @[ifu_bp_ctl.scala 443:223] + wire _T_11549 = _T_11273 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_1_6 = _T_11549 | _T_6764; // @[ifu_bp_ctl.scala 443:223] + wire _T_11566 = _T_11290 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_1_7 = _T_11566 | _T_6773; // @[ifu_bp_ctl.scala 443:223] + wire _T_11583 = _T_11307 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_1_8 = _T_11583 | _T_6782; // @[ifu_bp_ctl.scala 443:223] + wire _T_11600 = _T_11324 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_1_9 = _T_11600 | _T_6791; // @[ifu_bp_ctl.scala 443:223] + wire _T_11617 = _T_11341 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_1_10 = _T_11617 | _T_6800; // @[ifu_bp_ctl.scala 443:223] + wire _T_11634 = _T_11358 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_1_11 = _T_11634 | _T_6809; // @[ifu_bp_ctl.scala 443:223] + wire _T_11651 = _T_11375 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_1_12 = _T_11651 | _T_6818; // @[ifu_bp_ctl.scala 443:223] + wire _T_11668 = _T_11392 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_1_13 = _T_11668 | _T_6827; // @[ifu_bp_ctl.scala 443:223] + wire _T_11685 = _T_11409 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_1_14 = _T_11685 | _T_6836; // @[ifu_bp_ctl.scala 443:223] + wire _T_11702 = _T_11426 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_1_15 = _T_11702 | _T_6845; // @[ifu_bp_ctl.scala 443:223] + wire _T_11719 = _T_11171 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_2_0 = _T_11719 | _T_6854; // @[ifu_bp_ctl.scala 443:223] + wire _T_11736 = _T_11188 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_2_1 = _T_11736 | _T_6863; // @[ifu_bp_ctl.scala 443:223] + wire _T_11753 = _T_11205 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_2_2 = _T_11753 | _T_6872; // @[ifu_bp_ctl.scala 443:223] + wire _T_11770 = _T_11222 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_2_3 = _T_11770 | _T_6881; // @[ifu_bp_ctl.scala 443:223] + wire _T_11787 = _T_11239 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_2_4 = _T_11787 | _T_6890; // @[ifu_bp_ctl.scala 443:223] + wire _T_11804 = _T_11256 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_2_5 = _T_11804 | _T_6899; // @[ifu_bp_ctl.scala 443:223] + wire _T_11821 = _T_11273 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_2_6 = _T_11821 | _T_6908; // @[ifu_bp_ctl.scala 443:223] + wire _T_11838 = _T_11290 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_2_7 = _T_11838 | _T_6917; // @[ifu_bp_ctl.scala 443:223] + wire _T_11855 = _T_11307 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_2_8 = _T_11855 | _T_6926; // @[ifu_bp_ctl.scala 443:223] + wire _T_11872 = _T_11324 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_2_9 = _T_11872 | _T_6935; // @[ifu_bp_ctl.scala 443:223] + wire _T_11889 = _T_11341 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_2_10 = _T_11889 | _T_6944; // @[ifu_bp_ctl.scala 443:223] + wire _T_11906 = _T_11358 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_2_11 = _T_11906 | _T_6953; // @[ifu_bp_ctl.scala 443:223] + wire _T_11923 = _T_11375 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_2_12 = _T_11923 | _T_6962; // @[ifu_bp_ctl.scala 443:223] + wire _T_11940 = _T_11392 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_2_13 = _T_11940 | _T_6971; // @[ifu_bp_ctl.scala 443:223] + wire _T_11957 = _T_11409 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_2_14 = _T_11957 | _T_6980; // @[ifu_bp_ctl.scala 443:223] + wire _T_11974 = _T_11426 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_2_15 = _T_11974 | _T_6989; // @[ifu_bp_ctl.scala 443:223] + wire _T_11991 = _T_11171 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_3_0 = _T_11991 | _T_6998; // @[ifu_bp_ctl.scala 443:223] + wire _T_12008 = _T_11188 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_3_1 = _T_12008 | _T_7007; // @[ifu_bp_ctl.scala 443:223] + wire _T_12025 = _T_11205 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_3_2 = _T_12025 | _T_7016; // @[ifu_bp_ctl.scala 443:223] + wire _T_12042 = _T_11222 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_3_3 = _T_12042 | _T_7025; // @[ifu_bp_ctl.scala 443:223] + wire _T_12059 = _T_11239 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_3_4 = _T_12059 | _T_7034; // @[ifu_bp_ctl.scala 443:223] + wire _T_12076 = _T_11256 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_3_5 = _T_12076 | _T_7043; // @[ifu_bp_ctl.scala 443:223] + wire _T_12093 = _T_11273 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_3_6 = _T_12093 | _T_7052; // @[ifu_bp_ctl.scala 443:223] + wire _T_12110 = _T_11290 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_3_7 = _T_12110 | _T_7061; // @[ifu_bp_ctl.scala 443:223] + wire _T_12127 = _T_11307 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_3_8 = _T_12127 | _T_7070; // @[ifu_bp_ctl.scala 443:223] + wire _T_12144 = _T_11324 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_3_9 = _T_12144 | _T_7079; // @[ifu_bp_ctl.scala 443:223] + wire _T_12161 = _T_11341 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_3_10 = _T_12161 | _T_7088; // @[ifu_bp_ctl.scala 443:223] + wire _T_12178 = _T_11358 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_3_11 = _T_12178 | _T_7097; // @[ifu_bp_ctl.scala 443:223] + wire _T_12195 = _T_11375 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_3_12 = _T_12195 | _T_7106; // @[ifu_bp_ctl.scala 443:223] + wire _T_12212 = _T_11392 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_3_13 = _T_12212 | _T_7115; // @[ifu_bp_ctl.scala 443:223] + wire _T_12229 = _T_11409 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_3_14 = _T_12229 | _T_7124; // @[ifu_bp_ctl.scala 443:223] + wire _T_12246 = _T_11426 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_3_15 = _T_12246 | _T_7133; // @[ifu_bp_ctl.scala 443:223] + wire _T_12263 = _T_11171 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_4_0 = _T_12263 | _T_7142; // @[ifu_bp_ctl.scala 443:223] + wire _T_12280 = _T_11188 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_4_1 = _T_12280 | _T_7151; // @[ifu_bp_ctl.scala 443:223] + wire _T_12297 = _T_11205 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_4_2 = _T_12297 | _T_7160; // @[ifu_bp_ctl.scala 443:223] + wire _T_12314 = _T_11222 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_4_3 = _T_12314 | _T_7169; // @[ifu_bp_ctl.scala 443:223] + wire _T_12331 = _T_11239 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_4_4 = _T_12331 | _T_7178; // @[ifu_bp_ctl.scala 443:223] + wire _T_12348 = _T_11256 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_4_5 = _T_12348 | _T_7187; // @[ifu_bp_ctl.scala 443:223] + wire _T_12365 = _T_11273 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_4_6 = _T_12365 | _T_7196; // @[ifu_bp_ctl.scala 443:223] + wire _T_12382 = _T_11290 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_4_7 = _T_12382 | _T_7205; // @[ifu_bp_ctl.scala 443:223] + wire _T_12399 = _T_11307 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_4_8 = _T_12399 | _T_7214; // @[ifu_bp_ctl.scala 443:223] + wire _T_12416 = _T_11324 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_4_9 = _T_12416 | _T_7223; // @[ifu_bp_ctl.scala 443:223] + wire _T_12433 = _T_11341 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_4_10 = _T_12433 | _T_7232; // @[ifu_bp_ctl.scala 443:223] + wire _T_12450 = _T_11358 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_4_11 = _T_12450 | _T_7241; // @[ifu_bp_ctl.scala 443:223] + wire _T_12467 = _T_11375 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_4_12 = _T_12467 | _T_7250; // @[ifu_bp_ctl.scala 443:223] + wire _T_12484 = _T_11392 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_4_13 = _T_12484 | _T_7259; // @[ifu_bp_ctl.scala 443:223] + wire _T_12501 = _T_11409 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_4_14 = _T_12501 | _T_7268; // @[ifu_bp_ctl.scala 443:223] + wire _T_12518 = _T_11426 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_4_15 = _T_12518 | _T_7277; // @[ifu_bp_ctl.scala 443:223] + wire _T_12535 = _T_11171 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_5_0 = _T_12535 | _T_7286; // @[ifu_bp_ctl.scala 443:223] + wire _T_12552 = _T_11188 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_5_1 = _T_12552 | _T_7295; // @[ifu_bp_ctl.scala 443:223] + wire _T_12569 = _T_11205 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_5_2 = _T_12569 | _T_7304; // @[ifu_bp_ctl.scala 443:223] + wire _T_12586 = _T_11222 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_5_3 = _T_12586 | _T_7313; // @[ifu_bp_ctl.scala 443:223] + wire _T_12603 = _T_11239 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_5_4 = _T_12603 | _T_7322; // @[ifu_bp_ctl.scala 443:223] + wire _T_12620 = _T_11256 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_5_5 = _T_12620 | _T_7331; // @[ifu_bp_ctl.scala 443:223] + wire _T_12637 = _T_11273 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_5_6 = _T_12637 | _T_7340; // @[ifu_bp_ctl.scala 443:223] + wire _T_12654 = _T_11290 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_5_7 = _T_12654 | _T_7349; // @[ifu_bp_ctl.scala 443:223] + wire _T_12671 = _T_11307 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_5_8 = _T_12671 | _T_7358; // @[ifu_bp_ctl.scala 443:223] + wire _T_12688 = _T_11324 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_5_9 = _T_12688 | _T_7367; // @[ifu_bp_ctl.scala 443:223] + wire _T_12705 = _T_11341 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_5_10 = _T_12705 | _T_7376; // @[ifu_bp_ctl.scala 443:223] + wire _T_12722 = _T_11358 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_5_11 = _T_12722 | _T_7385; // @[ifu_bp_ctl.scala 443:223] + wire _T_12739 = _T_11375 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_5_12 = _T_12739 | _T_7394; // @[ifu_bp_ctl.scala 443:223] + wire _T_12756 = _T_11392 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_5_13 = _T_12756 | _T_7403; // @[ifu_bp_ctl.scala 443:223] + wire _T_12773 = _T_11409 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_5_14 = _T_12773 | _T_7412; // @[ifu_bp_ctl.scala 443:223] + wire _T_12790 = _T_11426 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_5_15 = _T_12790 | _T_7421; // @[ifu_bp_ctl.scala 443:223] + wire _T_12807 = _T_11171 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_6_0 = _T_12807 | _T_7430; // @[ifu_bp_ctl.scala 443:223] + wire _T_12824 = _T_11188 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_6_1 = _T_12824 | _T_7439; // @[ifu_bp_ctl.scala 443:223] + wire _T_12841 = _T_11205 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_6_2 = _T_12841 | _T_7448; // @[ifu_bp_ctl.scala 443:223] + wire _T_12858 = _T_11222 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_6_3 = _T_12858 | _T_7457; // @[ifu_bp_ctl.scala 443:223] + wire _T_12875 = _T_11239 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_6_4 = _T_12875 | _T_7466; // @[ifu_bp_ctl.scala 443:223] + wire _T_12892 = _T_11256 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_6_5 = _T_12892 | _T_7475; // @[ifu_bp_ctl.scala 443:223] + wire _T_12909 = _T_11273 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_6_6 = _T_12909 | _T_7484; // @[ifu_bp_ctl.scala 443:223] + wire _T_12926 = _T_11290 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_6_7 = _T_12926 | _T_7493; // @[ifu_bp_ctl.scala 443:223] + wire _T_12943 = _T_11307 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_6_8 = _T_12943 | _T_7502; // @[ifu_bp_ctl.scala 443:223] + wire _T_12960 = _T_11324 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_6_9 = _T_12960 | _T_7511; // @[ifu_bp_ctl.scala 443:223] + wire _T_12977 = _T_11341 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_6_10 = _T_12977 | _T_7520; // @[ifu_bp_ctl.scala 443:223] + wire _T_12994 = _T_11358 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_6_11 = _T_12994 | _T_7529; // @[ifu_bp_ctl.scala 443:223] + wire _T_13011 = _T_11375 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_6_12 = _T_13011 | _T_7538; // @[ifu_bp_ctl.scala 443:223] + wire _T_13028 = _T_11392 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_6_13 = _T_13028 | _T_7547; // @[ifu_bp_ctl.scala 443:223] + wire _T_13045 = _T_11409 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_6_14 = _T_13045 | _T_7556; // @[ifu_bp_ctl.scala 443:223] + wire _T_13062 = _T_11426 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_6_15 = _T_13062 | _T_7565; // @[ifu_bp_ctl.scala 443:223] + wire _T_13079 = _T_11171 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_7_0 = _T_13079 | _T_7574; // @[ifu_bp_ctl.scala 443:223] + wire _T_13096 = _T_11188 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_7_1 = _T_13096 | _T_7583; // @[ifu_bp_ctl.scala 443:223] + wire _T_13113 = _T_11205 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_7_2 = _T_13113 | _T_7592; // @[ifu_bp_ctl.scala 443:223] + wire _T_13130 = _T_11222 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_7_3 = _T_13130 | _T_7601; // @[ifu_bp_ctl.scala 443:223] + wire _T_13147 = _T_11239 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_7_4 = _T_13147 | _T_7610; // @[ifu_bp_ctl.scala 443:223] + wire _T_13164 = _T_11256 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_7_5 = _T_13164 | _T_7619; // @[ifu_bp_ctl.scala 443:223] + wire _T_13181 = _T_11273 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_7_6 = _T_13181 | _T_7628; // @[ifu_bp_ctl.scala 443:223] + wire _T_13198 = _T_11290 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_7_7 = _T_13198 | _T_7637; // @[ifu_bp_ctl.scala 443:223] + wire _T_13215 = _T_11307 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_7_8 = _T_13215 | _T_7646; // @[ifu_bp_ctl.scala 443:223] + wire _T_13232 = _T_11324 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_7_9 = _T_13232 | _T_7655; // @[ifu_bp_ctl.scala 443:223] + wire _T_13249 = _T_11341 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_7_10 = _T_13249 | _T_7664; // @[ifu_bp_ctl.scala 443:223] + wire _T_13266 = _T_11358 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_7_11 = _T_13266 | _T_7673; // @[ifu_bp_ctl.scala 443:223] + wire _T_13283 = _T_11375 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_7_12 = _T_13283 | _T_7682; // @[ifu_bp_ctl.scala 443:223] + wire _T_13300 = _T_11392 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_7_13 = _T_13300 | _T_7691; // @[ifu_bp_ctl.scala 443:223] + wire _T_13317 = _T_11409 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_7_14 = _T_13317 | _T_7700; // @[ifu_bp_ctl.scala 443:223] + wire _T_13334 = _T_11426 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_7_15 = _T_13334 | _T_7709; // @[ifu_bp_ctl.scala 443:223] + wire _T_13351 = _T_11171 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_8_0 = _T_13351 | _T_7718; // @[ifu_bp_ctl.scala 443:223] + wire _T_13368 = _T_11188 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_8_1 = _T_13368 | _T_7727; // @[ifu_bp_ctl.scala 443:223] + wire _T_13385 = _T_11205 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_8_2 = _T_13385 | _T_7736; // @[ifu_bp_ctl.scala 443:223] + wire _T_13402 = _T_11222 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_8_3 = _T_13402 | _T_7745; // @[ifu_bp_ctl.scala 443:223] + wire _T_13419 = _T_11239 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_8_4 = _T_13419 | _T_7754; // @[ifu_bp_ctl.scala 443:223] + wire _T_13436 = _T_11256 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_8_5 = _T_13436 | _T_7763; // @[ifu_bp_ctl.scala 443:223] + wire _T_13453 = _T_11273 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_8_6 = _T_13453 | _T_7772; // @[ifu_bp_ctl.scala 443:223] + wire _T_13470 = _T_11290 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_8_7 = _T_13470 | _T_7781; // @[ifu_bp_ctl.scala 443:223] + wire _T_13487 = _T_11307 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_8_8 = _T_13487 | _T_7790; // @[ifu_bp_ctl.scala 443:223] + wire _T_13504 = _T_11324 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_8_9 = _T_13504 | _T_7799; // @[ifu_bp_ctl.scala 443:223] + wire _T_13521 = _T_11341 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_8_10 = _T_13521 | _T_7808; // @[ifu_bp_ctl.scala 443:223] + wire _T_13538 = _T_11358 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_8_11 = _T_13538 | _T_7817; // @[ifu_bp_ctl.scala 443:223] + wire _T_13555 = _T_11375 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_8_12 = _T_13555 | _T_7826; // @[ifu_bp_ctl.scala 443:223] + wire _T_13572 = _T_11392 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_8_13 = _T_13572 | _T_7835; // @[ifu_bp_ctl.scala 443:223] + wire _T_13589 = _T_11409 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_8_14 = _T_13589 | _T_7844; // @[ifu_bp_ctl.scala 443:223] + wire _T_13606 = _T_11426 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_8_15 = _T_13606 | _T_7853; // @[ifu_bp_ctl.scala 443:223] + wire _T_13623 = _T_11171 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_9_0 = _T_13623 | _T_7862; // @[ifu_bp_ctl.scala 443:223] + wire _T_13640 = _T_11188 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_9_1 = _T_13640 | _T_7871; // @[ifu_bp_ctl.scala 443:223] + wire _T_13657 = _T_11205 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_9_2 = _T_13657 | _T_7880; // @[ifu_bp_ctl.scala 443:223] + wire _T_13674 = _T_11222 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_9_3 = _T_13674 | _T_7889; // @[ifu_bp_ctl.scala 443:223] + wire _T_13691 = _T_11239 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_9_4 = _T_13691 | _T_7898; // @[ifu_bp_ctl.scala 443:223] + wire _T_13708 = _T_11256 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_9_5 = _T_13708 | _T_7907; // @[ifu_bp_ctl.scala 443:223] + wire _T_13725 = _T_11273 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_9_6 = _T_13725 | _T_7916; // @[ifu_bp_ctl.scala 443:223] + wire _T_13742 = _T_11290 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_9_7 = _T_13742 | _T_7925; // @[ifu_bp_ctl.scala 443:223] + wire _T_13759 = _T_11307 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_9_8 = _T_13759 | _T_7934; // @[ifu_bp_ctl.scala 443:223] + wire _T_13776 = _T_11324 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_9_9 = _T_13776 | _T_7943; // @[ifu_bp_ctl.scala 443:223] + wire _T_13793 = _T_11341 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_9_10 = _T_13793 | _T_7952; // @[ifu_bp_ctl.scala 443:223] + wire _T_13810 = _T_11358 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_9_11 = _T_13810 | _T_7961; // @[ifu_bp_ctl.scala 443:223] + wire _T_13827 = _T_11375 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_9_12 = _T_13827 | _T_7970; // @[ifu_bp_ctl.scala 443:223] + wire _T_13844 = _T_11392 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_9_13 = _T_13844 | _T_7979; // @[ifu_bp_ctl.scala 443:223] + wire _T_13861 = _T_11409 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_9_14 = _T_13861 | _T_7988; // @[ifu_bp_ctl.scala 443:223] + wire _T_13878 = _T_11426 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_9_15 = _T_13878 | _T_7997; // @[ifu_bp_ctl.scala 443:223] + wire _T_13895 = _T_11171 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_10_0 = _T_13895 | _T_8006; // @[ifu_bp_ctl.scala 443:223] + wire _T_13912 = _T_11188 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_10_1 = _T_13912 | _T_8015; // @[ifu_bp_ctl.scala 443:223] + wire _T_13929 = _T_11205 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_10_2 = _T_13929 | _T_8024; // @[ifu_bp_ctl.scala 443:223] + wire _T_13946 = _T_11222 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_10_3 = _T_13946 | _T_8033; // @[ifu_bp_ctl.scala 443:223] + wire _T_13963 = _T_11239 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_10_4 = _T_13963 | _T_8042; // @[ifu_bp_ctl.scala 443:223] + wire _T_13980 = _T_11256 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_10_5 = _T_13980 | _T_8051; // @[ifu_bp_ctl.scala 443:223] + wire _T_13997 = _T_11273 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_10_6 = _T_13997 | _T_8060; // @[ifu_bp_ctl.scala 443:223] + wire _T_14014 = _T_11290 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_10_7 = _T_14014 | _T_8069; // @[ifu_bp_ctl.scala 443:223] + wire _T_14031 = _T_11307 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_10_8 = _T_14031 | _T_8078; // @[ifu_bp_ctl.scala 443:223] + wire _T_14048 = _T_11324 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_10_9 = _T_14048 | _T_8087; // @[ifu_bp_ctl.scala 443:223] + wire _T_14065 = _T_11341 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_10_10 = _T_14065 | _T_8096; // @[ifu_bp_ctl.scala 443:223] + wire _T_14082 = _T_11358 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_10_11 = _T_14082 | _T_8105; // @[ifu_bp_ctl.scala 443:223] + wire _T_14099 = _T_11375 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_10_12 = _T_14099 | _T_8114; // @[ifu_bp_ctl.scala 443:223] + wire _T_14116 = _T_11392 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_10_13 = _T_14116 | _T_8123; // @[ifu_bp_ctl.scala 443:223] + wire _T_14133 = _T_11409 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_10_14 = _T_14133 | _T_8132; // @[ifu_bp_ctl.scala 443:223] + wire _T_14150 = _T_11426 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_10_15 = _T_14150 | _T_8141; // @[ifu_bp_ctl.scala 443:223] + wire _T_14167 = _T_11171 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_11_0 = _T_14167 | _T_8150; // @[ifu_bp_ctl.scala 443:223] + wire _T_14184 = _T_11188 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_11_1 = _T_14184 | _T_8159; // @[ifu_bp_ctl.scala 443:223] + wire _T_14201 = _T_11205 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_11_2 = _T_14201 | _T_8168; // @[ifu_bp_ctl.scala 443:223] + wire _T_14218 = _T_11222 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_11_3 = _T_14218 | _T_8177; // @[ifu_bp_ctl.scala 443:223] + wire _T_14235 = _T_11239 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_11_4 = _T_14235 | _T_8186; // @[ifu_bp_ctl.scala 443:223] + wire _T_14252 = _T_11256 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_11_5 = _T_14252 | _T_8195; // @[ifu_bp_ctl.scala 443:223] + wire _T_14269 = _T_11273 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_11_6 = _T_14269 | _T_8204; // @[ifu_bp_ctl.scala 443:223] + wire _T_14286 = _T_11290 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_11_7 = _T_14286 | _T_8213; // @[ifu_bp_ctl.scala 443:223] + wire _T_14303 = _T_11307 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_11_8 = _T_14303 | _T_8222; // @[ifu_bp_ctl.scala 443:223] + wire _T_14320 = _T_11324 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_11_9 = _T_14320 | _T_8231; // @[ifu_bp_ctl.scala 443:223] + wire _T_14337 = _T_11341 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_11_10 = _T_14337 | _T_8240; // @[ifu_bp_ctl.scala 443:223] + wire _T_14354 = _T_11358 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_11_11 = _T_14354 | _T_8249; // @[ifu_bp_ctl.scala 443:223] + wire _T_14371 = _T_11375 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_11_12 = _T_14371 | _T_8258; // @[ifu_bp_ctl.scala 443:223] + wire _T_14388 = _T_11392 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_11_13 = _T_14388 | _T_8267; // @[ifu_bp_ctl.scala 443:223] + wire _T_14405 = _T_11409 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_11_14 = _T_14405 | _T_8276; // @[ifu_bp_ctl.scala 443:223] + wire _T_14422 = _T_11426 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_11_15 = _T_14422 | _T_8285; // @[ifu_bp_ctl.scala 443:223] + wire _T_14439 = _T_11171 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_12_0 = _T_14439 | _T_8294; // @[ifu_bp_ctl.scala 443:223] + wire _T_14456 = _T_11188 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_12_1 = _T_14456 | _T_8303; // @[ifu_bp_ctl.scala 443:223] + wire _T_14473 = _T_11205 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_12_2 = _T_14473 | _T_8312; // @[ifu_bp_ctl.scala 443:223] + wire _T_14490 = _T_11222 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_12_3 = _T_14490 | _T_8321; // @[ifu_bp_ctl.scala 443:223] + wire _T_14507 = _T_11239 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_12_4 = _T_14507 | _T_8330; // @[ifu_bp_ctl.scala 443:223] + wire _T_14524 = _T_11256 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_12_5 = _T_14524 | _T_8339; // @[ifu_bp_ctl.scala 443:223] + wire _T_14541 = _T_11273 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_12_6 = _T_14541 | _T_8348; // @[ifu_bp_ctl.scala 443:223] + wire _T_14558 = _T_11290 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_12_7 = _T_14558 | _T_8357; // @[ifu_bp_ctl.scala 443:223] + wire _T_14575 = _T_11307 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_12_8 = _T_14575 | _T_8366; // @[ifu_bp_ctl.scala 443:223] + wire _T_14592 = _T_11324 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_12_9 = _T_14592 | _T_8375; // @[ifu_bp_ctl.scala 443:223] + wire _T_14609 = _T_11341 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_12_10 = _T_14609 | _T_8384; // @[ifu_bp_ctl.scala 443:223] + wire _T_14626 = _T_11358 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_12_11 = _T_14626 | _T_8393; // @[ifu_bp_ctl.scala 443:223] + wire _T_14643 = _T_11375 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_12_12 = _T_14643 | _T_8402; // @[ifu_bp_ctl.scala 443:223] + wire _T_14660 = _T_11392 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_12_13 = _T_14660 | _T_8411; // @[ifu_bp_ctl.scala 443:223] + wire _T_14677 = _T_11409 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_12_14 = _T_14677 | _T_8420; // @[ifu_bp_ctl.scala 443:223] + wire _T_14694 = _T_11426 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_12_15 = _T_14694 | _T_8429; // @[ifu_bp_ctl.scala 443:223] + wire _T_14711 = _T_11171 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_13_0 = _T_14711 | _T_8438; // @[ifu_bp_ctl.scala 443:223] + wire _T_14728 = _T_11188 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_13_1 = _T_14728 | _T_8447; // @[ifu_bp_ctl.scala 443:223] + wire _T_14745 = _T_11205 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_13_2 = _T_14745 | _T_8456; // @[ifu_bp_ctl.scala 443:223] + wire _T_14762 = _T_11222 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_13_3 = _T_14762 | _T_8465; // @[ifu_bp_ctl.scala 443:223] + wire _T_14779 = _T_11239 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_13_4 = _T_14779 | _T_8474; // @[ifu_bp_ctl.scala 443:223] + wire _T_14796 = _T_11256 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_13_5 = _T_14796 | _T_8483; // @[ifu_bp_ctl.scala 443:223] + wire _T_14813 = _T_11273 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_13_6 = _T_14813 | _T_8492; // @[ifu_bp_ctl.scala 443:223] + wire _T_14830 = _T_11290 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_13_7 = _T_14830 | _T_8501; // @[ifu_bp_ctl.scala 443:223] + wire _T_14847 = _T_11307 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_13_8 = _T_14847 | _T_8510; // @[ifu_bp_ctl.scala 443:223] + wire _T_14864 = _T_11324 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_13_9 = _T_14864 | _T_8519; // @[ifu_bp_ctl.scala 443:223] + wire _T_14881 = _T_11341 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_13_10 = _T_14881 | _T_8528; // @[ifu_bp_ctl.scala 443:223] + wire _T_14898 = _T_11358 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_13_11 = _T_14898 | _T_8537; // @[ifu_bp_ctl.scala 443:223] + wire _T_14915 = _T_11375 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_13_12 = _T_14915 | _T_8546; // @[ifu_bp_ctl.scala 443:223] + wire _T_14932 = _T_11392 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_13_13 = _T_14932 | _T_8555; // @[ifu_bp_ctl.scala 443:223] + wire _T_14949 = _T_11409 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_13_14 = _T_14949 | _T_8564; // @[ifu_bp_ctl.scala 443:223] + wire _T_14966 = _T_11426 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_13_15 = _T_14966 | _T_8573; // @[ifu_bp_ctl.scala 443:223] + wire _T_14983 = _T_11171 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_14_0 = _T_14983 | _T_8582; // @[ifu_bp_ctl.scala 443:223] + wire _T_15000 = _T_11188 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_14_1 = _T_15000 | _T_8591; // @[ifu_bp_ctl.scala 443:223] + wire _T_15017 = _T_11205 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_14_2 = _T_15017 | _T_8600; // @[ifu_bp_ctl.scala 443:223] + wire _T_15034 = _T_11222 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_14_3 = _T_15034 | _T_8609; // @[ifu_bp_ctl.scala 443:223] + wire _T_15051 = _T_11239 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_14_4 = _T_15051 | _T_8618; // @[ifu_bp_ctl.scala 443:223] + wire _T_15068 = _T_11256 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_14_5 = _T_15068 | _T_8627; // @[ifu_bp_ctl.scala 443:223] + wire _T_15085 = _T_11273 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_14_6 = _T_15085 | _T_8636; // @[ifu_bp_ctl.scala 443:223] + wire _T_15102 = _T_11290 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_14_7 = _T_15102 | _T_8645; // @[ifu_bp_ctl.scala 443:223] + wire _T_15119 = _T_11307 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_14_8 = _T_15119 | _T_8654; // @[ifu_bp_ctl.scala 443:223] + wire _T_15136 = _T_11324 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_14_9 = _T_15136 | _T_8663; // @[ifu_bp_ctl.scala 443:223] + wire _T_15153 = _T_11341 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_14_10 = _T_15153 | _T_8672; // @[ifu_bp_ctl.scala 443:223] + wire _T_15170 = _T_11358 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_14_11 = _T_15170 | _T_8681; // @[ifu_bp_ctl.scala 443:223] + wire _T_15187 = _T_11375 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_14_12 = _T_15187 | _T_8690; // @[ifu_bp_ctl.scala 443:223] + wire _T_15204 = _T_11392 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_14_13 = _T_15204 | _T_8699; // @[ifu_bp_ctl.scala 443:223] + wire _T_15221 = _T_11409 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_14_14 = _T_15221 | _T_8708; // @[ifu_bp_ctl.scala 443:223] + wire _T_15238 = _T_11426 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_14_15 = _T_15238 | _T_8717; // @[ifu_bp_ctl.scala 443:223] + wire _T_15255 = _T_11171 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_15_0 = _T_15255 | _T_8726; // @[ifu_bp_ctl.scala 443:223] + wire _T_15272 = _T_11188 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_15_1 = _T_15272 | _T_8735; // @[ifu_bp_ctl.scala 443:223] + wire _T_15289 = _T_11205 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_15_2 = _T_15289 | _T_8744; // @[ifu_bp_ctl.scala 443:223] + wire _T_15306 = _T_11222 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_15_3 = _T_15306 | _T_8753; // @[ifu_bp_ctl.scala 443:223] + wire _T_15323 = _T_11239 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_15_4 = _T_15323 | _T_8762; // @[ifu_bp_ctl.scala 443:223] + wire _T_15340 = _T_11256 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_15_5 = _T_15340 | _T_8771; // @[ifu_bp_ctl.scala 443:223] + wire _T_15357 = _T_11273 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_15_6 = _T_15357 | _T_8780; // @[ifu_bp_ctl.scala 443:223] + wire _T_15374 = _T_11290 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_15_7 = _T_15374 | _T_8789; // @[ifu_bp_ctl.scala 443:223] + wire _T_15391 = _T_11307 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_15_8 = _T_15391 | _T_8798; // @[ifu_bp_ctl.scala 443:223] + wire _T_15408 = _T_11324 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_15_9 = _T_15408 | _T_8807; // @[ifu_bp_ctl.scala 443:223] + wire _T_15425 = _T_11341 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_15_10 = _T_15425 | _T_8816; // @[ifu_bp_ctl.scala 443:223] + wire _T_15442 = _T_11358 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_15_11 = _T_15442 | _T_8825; // @[ifu_bp_ctl.scala 443:223] + wire _T_15459 = _T_11375 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_15_12 = _T_15459 | _T_8834; // @[ifu_bp_ctl.scala 443:223] + wire _T_15476 = _T_11392 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_15_13 = _T_15476 | _T_8843; // @[ifu_bp_ctl.scala 443:223] + wire _T_15493 = _T_11409 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_15_14 = _T_15493 | _T_8852; // @[ifu_bp_ctl.scala 443:223] + wire _T_15510 = _T_11426 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_0_15_15 = _T_15510 | _T_8861; // @[ifu_bp_ctl.scala 443:223] + wire _T_15523 = bht_wr_en0[1] & _T_11170; // @[ifu_bp_ctl.scala 443:45] + wire _T_15527 = _T_15523 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_0_0 = _T_15527 | _T_8870; // @[ifu_bp_ctl.scala 443:223] + wire _T_15540 = bht_wr_en0[1] & _T_11187; // @[ifu_bp_ctl.scala 443:45] + wire _T_15544 = _T_15540 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_0_1 = _T_15544 | _T_8879; // @[ifu_bp_ctl.scala 443:223] + wire _T_15557 = bht_wr_en0[1] & _T_11204; // @[ifu_bp_ctl.scala 443:45] + wire _T_15561 = _T_15557 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_0_2 = _T_15561 | _T_8888; // @[ifu_bp_ctl.scala 443:223] + wire _T_15574 = bht_wr_en0[1] & _T_11221; // @[ifu_bp_ctl.scala 443:45] + wire _T_15578 = _T_15574 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_0_3 = _T_15578 | _T_8897; // @[ifu_bp_ctl.scala 443:223] + wire _T_15591 = bht_wr_en0[1] & _T_11238; // @[ifu_bp_ctl.scala 443:45] + wire _T_15595 = _T_15591 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_0_4 = _T_15595 | _T_8906; // @[ifu_bp_ctl.scala 443:223] + wire _T_15608 = bht_wr_en0[1] & _T_11255; // @[ifu_bp_ctl.scala 443:45] + wire _T_15612 = _T_15608 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_0_5 = _T_15612 | _T_8915; // @[ifu_bp_ctl.scala 443:223] + wire _T_15625 = bht_wr_en0[1] & _T_11272; // @[ifu_bp_ctl.scala 443:45] + wire _T_15629 = _T_15625 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_0_6 = _T_15629 | _T_8924; // @[ifu_bp_ctl.scala 443:223] + wire _T_15642 = bht_wr_en0[1] & _T_11289; // @[ifu_bp_ctl.scala 443:45] + wire _T_15646 = _T_15642 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_0_7 = _T_15646 | _T_8933; // @[ifu_bp_ctl.scala 443:223] + wire _T_15659 = bht_wr_en0[1] & _T_11306; // @[ifu_bp_ctl.scala 443:45] + wire _T_15663 = _T_15659 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_0_8 = _T_15663 | _T_8942; // @[ifu_bp_ctl.scala 443:223] + wire _T_15676 = bht_wr_en0[1] & _T_11323; // @[ifu_bp_ctl.scala 443:45] + wire _T_15680 = _T_15676 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_0_9 = _T_15680 | _T_8951; // @[ifu_bp_ctl.scala 443:223] + wire _T_15693 = bht_wr_en0[1] & _T_11340; // @[ifu_bp_ctl.scala 443:45] + wire _T_15697 = _T_15693 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_0_10 = _T_15697 | _T_8960; // @[ifu_bp_ctl.scala 443:223] + wire _T_15710 = bht_wr_en0[1] & _T_11357; // @[ifu_bp_ctl.scala 443:45] + wire _T_15714 = _T_15710 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_0_11 = _T_15714 | _T_8969; // @[ifu_bp_ctl.scala 443:223] + wire _T_15727 = bht_wr_en0[1] & _T_11374; // @[ifu_bp_ctl.scala 443:45] + wire _T_15731 = _T_15727 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_0_12 = _T_15731 | _T_8978; // @[ifu_bp_ctl.scala 443:223] + wire _T_15744 = bht_wr_en0[1] & _T_11391; // @[ifu_bp_ctl.scala 443:45] + wire _T_15748 = _T_15744 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_0_13 = _T_15748 | _T_8987; // @[ifu_bp_ctl.scala 443:223] + wire _T_15761 = bht_wr_en0[1] & _T_11408; // @[ifu_bp_ctl.scala 443:45] + wire _T_15765 = _T_15761 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_0_14 = _T_15765 | _T_8996; // @[ifu_bp_ctl.scala 443:223] + wire _T_15778 = bht_wr_en0[1] & _T_11425; // @[ifu_bp_ctl.scala 443:45] + wire _T_15782 = _T_15778 & _T_6210; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_0_15 = _T_15782 | _T_9005; // @[ifu_bp_ctl.scala 443:223] + wire _T_15799 = _T_15523 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_1_0 = _T_15799 | _T_9014; // @[ifu_bp_ctl.scala 443:223] + wire _T_15816 = _T_15540 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_1_1 = _T_15816 | _T_9023; // @[ifu_bp_ctl.scala 443:223] + wire _T_15833 = _T_15557 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_1_2 = _T_15833 | _T_9032; // @[ifu_bp_ctl.scala 443:223] + wire _T_15850 = _T_15574 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_1_3 = _T_15850 | _T_9041; // @[ifu_bp_ctl.scala 443:223] + wire _T_15867 = _T_15591 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_1_4 = _T_15867 | _T_9050; // @[ifu_bp_ctl.scala 443:223] + wire _T_15884 = _T_15608 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_1_5 = _T_15884 | _T_9059; // @[ifu_bp_ctl.scala 443:223] + wire _T_15901 = _T_15625 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_1_6 = _T_15901 | _T_9068; // @[ifu_bp_ctl.scala 443:223] + wire _T_15918 = _T_15642 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_1_7 = _T_15918 | _T_9077; // @[ifu_bp_ctl.scala 443:223] + wire _T_15935 = _T_15659 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_1_8 = _T_15935 | _T_9086; // @[ifu_bp_ctl.scala 443:223] + wire _T_15952 = _T_15676 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_1_9 = _T_15952 | _T_9095; // @[ifu_bp_ctl.scala 443:223] + wire _T_15969 = _T_15693 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_1_10 = _T_15969 | _T_9104; // @[ifu_bp_ctl.scala 443:223] + wire _T_15986 = _T_15710 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_1_11 = _T_15986 | _T_9113; // @[ifu_bp_ctl.scala 443:223] + wire _T_16003 = _T_15727 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_1_12 = _T_16003 | _T_9122; // @[ifu_bp_ctl.scala 443:223] + wire _T_16020 = _T_15744 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_1_13 = _T_16020 | _T_9131; // @[ifu_bp_ctl.scala 443:223] + wire _T_16037 = _T_15761 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_1_14 = _T_16037 | _T_9140; // @[ifu_bp_ctl.scala 443:223] + wire _T_16054 = _T_15778 & _T_6221; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_1_15 = _T_16054 | _T_9149; // @[ifu_bp_ctl.scala 443:223] + wire _T_16071 = _T_15523 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_2_0 = _T_16071 | _T_9158; // @[ifu_bp_ctl.scala 443:223] + wire _T_16088 = _T_15540 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_2_1 = _T_16088 | _T_9167; // @[ifu_bp_ctl.scala 443:223] + wire _T_16105 = _T_15557 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_2_2 = _T_16105 | _T_9176; // @[ifu_bp_ctl.scala 443:223] + wire _T_16122 = _T_15574 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_2_3 = _T_16122 | _T_9185; // @[ifu_bp_ctl.scala 443:223] + wire _T_16139 = _T_15591 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_2_4 = _T_16139 | _T_9194; // @[ifu_bp_ctl.scala 443:223] + wire _T_16156 = _T_15608 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_2_5 = _T_16156 | _T_9203; // @[ifu_bp_ctl.scala 443:223] + wire _T_16173 = _T_15625 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_2_6 = _T_16173 | _T_9212; // @[ifu_bp_ctl.scala 443:223] + wire _T_16190 = _T_15642 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_2_7 = _T_16190 | _T_9221; // @[ifu_bp_ctl.scala 443:223] + wire _T_16207 = _T_15659 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_2_8 = _T_16207 | _T_9230; // @[ifu_bp_ctl.scala 443:223] + wire _T_16224 = _T_15676 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_2_9 = _T_16224 | _T_9239; // @[ifu_bp_ctl.scala 443:223] + wire _T_16241 = _T_15693 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_2_10 = _T_16241 | _T_9248; // @[ifu_bp_ctl.scala 443:223] + wire _T_16258 = _T_15710 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_2_11 = _T_16258 | _T_9257; // @[ifu_bp_ctl.scala 443:223] + wire _T_16275 = _T_15727 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_2_12 = _T_16275 | _T_9266; // @[ifu_bp_ctl.scala 443:223] + wire _T_16292 = _T_15744 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_2_13 = _T_16292 | _T_9275; // @[ifu_bp_ctl.scala 443:223] + wire _T_16309 = _T_15761 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_2_14 = _T_16309 | _T_9284; // @[ifu_bp_ctl.scala 443:223] + wire _T_16326 = _T_15778 & _T_6232; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_2_15 = _T_16326 | _T_9293; // @[ifu_bp_ctl.scala 443:223] + wire _T_16343 = _T_15523 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_3_0 = _T_16343 | _T_9302; // @[ifu_bp_ctl.scala 443:223] + wire _T_16360 = _T_15540 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_3_1 = _T_16360 | _T_9311; // @[ifu_bp_ctl.scala 443:223] + wire _T_16377 = _T_15557 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_3_2 = _T_16377 | _T_9320; // @[ifu_bp_ctl.scala 443:223] + wire _T_16394 = _T_15574 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_3_3 = _T_16394 | _T_9329; // @[ifu_bp_ctl.scala 443:223] + wire _T_16411 = _T_15591 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_3_4 = _T_16411 | _T_9338; // @[ifu_bp_ctl.scala 443:223] + wire _T_16428 = _T_15608 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_3_5 = _T_16428 | _T_9347; // @[ifu_bp_ctl.scala 443:223] + wire _T_16445 = _T_15625 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_3_6 = _T_16445 | _T_9356; // @[ifu_bp_ctl.scala 443:223] + wire _T_16462 = _T_15642 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_3_7 = _T_16462 | _T_9365; // @[ifu_bp_ctl.scala 443:223] + wire _T_16479 = _T_15659 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_3_8 = _T_16479 | _T_9374; // @[ifu_bp_ctl.scala 443:223] + wire _T_16496 = _T_15676 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_3_9 = _T_16496 | _T_9383; // @[ifu_bp_ctl.scala 443:223] + wire _T_16513 = _T_15693 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_3_10 = _T_16513 | _T_9392; // @[ifu_bp_ctl.scala 443:223] + wire _T_16530 = _T_15710 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_3_11 = _T_16530 | _T_9401; // @[ifu_bp_ctl.scala 443:223] + wire _T_16547 = _T_15727 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_3_12 = _T_16547 | _T_9410; // @[ifu_bp_ctl.scala 443:223] + wire _T_16564 = _T_15744 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_3_13 = _T_16564 | _T_9419; // @[ifu_bp_ctl.scala 443:223] + wire _T_16581 = _T_15761 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_3_14 = _T_16581 | _T_9428; // @[ifu_bp_ctl.scala 443:223] + wire _T_16598 = _T_15778 & _T_6243; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_3_15 = _T_16598 | _T_9437; // @[ifu_bp_ctl.scala 443:223] + wire _T_16615 = _T_15523 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_4_0 = _T_16615 | _T_9446; // @[ifu_bp_ctl.scala 443:223] + wire _T_16632 = _T_15540 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_4_1 = _T_16632 | _T_9455; // @[ifu_bp_ctl.scala 443:223] + wire _T_16649 = _T_15557 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_4_2 = _T_16649 | _T_9464; // @[ifu_bp_ctl.scala 443:223] + wire _T_16666 = _T_15574 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_4_3 = _T_16666 | _T_9473; // @[ifu_bp_ctl.scala 443:223] + wire _T_16683 = _T_15591 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_4_4 = _T_16683 | _T_9482; // @[ifu_bp_ctl.scala 443:223] + wire _T_16700 = _T_15608 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_4_5 = _T_16700 | _T_9491; // @[ifu_bp_ctl.scala 443:223] + wire _T_16717 = _T_15625 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_4_6 = _T_16717 | _T_9500; // @[ifu_bp_ctl.scala 443:223] + wire _T_16734 = _T_15642 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_4_7 = _T_16734 | _T_9509; // @[ifu_bp_ctl.scala 443:223] + wire _T_16751 = _T_15659 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_4_8 = _T_16751 | _T_9518; // @[ifu_bp_ctl.scala 443:223] + wire _T_16768 = _T_15676 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_4_9 = _T_16768 | _T_9527; // @[ifu_bp_ctl.scala 443:223] + wire _T_16785 = _T_15693 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_4_10 = _T_16785 | _T_9536; // @[ifu_bp_ctl.scala 443:223] + wire _T_16802 = _T_15710 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_4_11 = _T_16802 | _T_9545; // @[ifu_bp_ctl.scala 443:223] + wire _T_16819 = _T_15727 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_4_12 = _T_16819 | _T_9554; // @[ifu_bp_ctl.scala 443:223] + wire _T_16836 = _T_15744 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_4_13 = _T_16836 | _T_9563; // @[ifu_bp_ctl.scala 443:223] + wire _T_16853 = _T_15761 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_4_14 = _T_16853 | _T_9572; // @[ifu_bp_ctl.scala 443:223] + wire _T_16870 = _T_15778 & _T_6254; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_4_15 = _T_16870 | _T_9581; // @[ifu_bp_ctl.scala 443:223] + wire _T_16887 = _T_15523 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_5_0 = _T_16887 | _T_9590; // @[ifu_bp_ctl.scala 443:223] + wire _T_16904 = _T_15540 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_5_1 = _T_16904 | _T_9599; // @[ifu_bp_ctl.scala 443:223] + wire _T_16921 = _T_15557 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_5_2 = _T_16921 | _T_9608; // @[ifu_bp_ctl.scala 443:223] + wire _T_16938 = _T_15574 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_5_3 = _T_16938 | _T_9617; // @[ifu_bp_ctl.scala 443:223] + wire _T_16955 = _T_15591 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_5_4 = _T_16955 | _T_9626; // @[ifu_bp_ctl.scala 443:223] + wire _T_16972 = _T_15608 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_5_5 = _T_16972 | _T_9635; // @[ifu_bp_ctl.scala 443:223] + wire _T_16989 = _T_15625 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_5_6 = _T_16989 | _T_9644; // @[ifu_bp_ctl.scala 443:223] + wire _T_17006 = _T_15642 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_5_7 = _T_17006 | _T_9653; // @[ifu_bp_ctl.scala 443:223] + wire _T_17023 = _T_15659 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_5_8 = _T_17023 | _T_9662; // @[ifu_bp_ctl.scala 443:223] + wire _T_17040 = _T_15676 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_5_9 = _T_17040 | _T_9671; // @[ifu_bp_ctl.scala 443:223] + wire _T_17057 = _T_15693 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_5_10 = _T_17057 | _T_9680; // @[ifu_bp_ctl.scala 443:223] + wire _T_17074 = _T_15710 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_5_11 = _T_17074 | _T_9689; // @[ifu_bp_ctl.scala 443:223] + wire _T_17091 = _T_15727 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_5_12 = _T_17091 | _T_9698; // @[ifu_bp_ctl.scala 443:223] + wire _T_17108 = _T_15744 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_5_13 = _T_17108 | _T_9707; // @[ifu_bp_ctl.scala 443:223] + wire _T_17125 = _T_15761 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_5_14 = _T_17125 | _T_9716; // @[ifu_bp_ctl.scala 443:223] + wire _T_17142 = _T_15778 & _T_6265; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_5_15 = _T_17142 | _T_9725; // @[ifu_bp_ctl.scala 443:223] + wire _T_17159 = _T_15523 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_6_0 = _T_17159 | _T_9734; // @[ifu_bp_ctl.scala 443:223] + wire _T_17176 = _T_15540 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_6_1 = _T_17176 | _T_9743; // @[ifu_bp_ctl.scala 443:223] + wire _T_17193 = _T_15557 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_6_2 = _T_17193 | _T_9752; // @[ifu_bp_ctl.scala 443:223] + wire _T_17210 = _T_15574 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_6_3 = _T_17210 | _T_9761; // @[ifu_bp_ctl.scala 443:223] + wire _T_17227 = _T_15591 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_6_4 = _T_17227 | _T_9770; // @[ifu_bp_ctl.scala 443:223] + wire _T_17244 = _T_15608 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_6_5 = _T_17244 | _T_9779; // @[ifu_bp_ctl.scala 443:223] + wire _T_17261 = _T_15625 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_6_6 = _T_17261 | _T_9788; // @[ifu_bp_ctl.scala 443:223] + wire _T_17278 = _T_15642 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_6_7 = _T_17278 | _T_9797; // @[ifu_bp_ctl.scala 443:223] + wire _T_17295 = _T_15659 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_6_8 = _T_17295 | _T_9806; // @[ifu_bp_ctl.scala 443:223] + wire _T_17312 = _T_15676 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_6_9 = _T_17312 | _T_9815; // @[ifu_bp_ctl.scala 443:223] + wire _T_17329 = _T_15693 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_6_10 = _T_17329 | _T_9824; // @[ifu_bp_ctl.scala 443:223] + wire _T_17346 = _T_15710 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_6_11 = _T_17346 | _T_9833; // @[ifu_bp_ctl.scala 443:223] + wire _T_17363 = _T_15727 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_6_12 = _T_17363 | _T_9842; // @[ifu_bp_ctl.scala 443:223] + wire _T_17380 = _T_15744 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_6_13 = _T_17380 | _T_9851; // @[ifu_bp_ctl.scala 443:223] + wire _T_17397 = _T_15761 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_6_14 = _T_17397 | _T_9860; // @[ifu_bp_ctl.scala 443:223] + wire _T_17414 = _T_15778 & _T_6276; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_6_15 = _T_17414 | _T_9869; // @[ifu_bp_ctl.scala 443:223] + wire _T_17431 = _T_15523 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_7_0 = _T_17431 | _T_9878; // @[ifu_bp_ctl.scala 443:223] + wire _T_17448 = _T_15540 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_7_1 = _T_17448 | _T_9887; // @[ifu_bp_ctl.scala 443:223] + wire _T_17465 = _T_15557 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_7_2 = _T_17465 | _T_9896; // @[ifu_bp_ctl.scala 443:223] + wire _T_17482 = _T_15574 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_7_3 = _T_17482 | _T_9905; // @[ifu_bp_ctl.scala 443:223] + wire _T_17499 = _T_15591 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_7_4 = _T_17499 | _T_9914; // @[ifu_bp_ctl.scala 443:223] + wire _T_17516 = _T_15608 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_7_5 = _T_17516 | _T_9923; // @[ifu_bp_ctl.scala 443:223] + wire _T_17533 = _T_15625 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_7_6 = _T_17533 | _T_9932; // @[ifu_bp_ctl.scala 443:223] + wire _T_17550 = _T_15642 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_7_7 = _T_17550 | _T_9941; // @[ifu_bp_ctl.scala 443:223] + wire _T_17567 = _T_15659 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_7_8 = _T_17567 | _T_9950; // @[ifu_bp_ctl.scala 443:223] + wire _T_17584 = _T_15676 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_7_9 = _T_17584 | _T_9959; // @[ifu_bp_ctl.scala 443:223] + wire _T_17601 = _T_15693 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_7_10 = _T_17601 | _T_9968; // @[ifu_bp_ctl.scala 443:223] + wire _T_17618 = _T_15710 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_7_11 = _T_17618 | _T_9977; // @[ifu_bp_ctl.scala 443:223] + wire _T_17635 = _T_15727 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_7_12 = _T_17635 | _T_9986; // @[ifu_bp_ctl.scala 443:223] + wire _T_17652 = _T_15744 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_7_13 = _T_17652 | _T_9995; // @[ifu_bp_ctl.scala 443:223] + wire _T_17669 = _T_15761 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_7_14 = _T_17669 | _T_10004; // @[ifu_bp_ctl.scala 443:223] + wire _T_17686 = _T_15778 & _T_6287; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_7_15 = _T_17686 | _T_10013; // @[ifu_bp_ctl.scala 443:223] + wire _T_17703 = _T_15523 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_8_0 = _T_17703 | _T_10022; // @[ifu_bp_ctl.scala 443:223] + wire _T_17720 = _T_15540 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_8_1 = _T_17720 | _T_10031; // @[ifu_bp_ctl.scala 443:223] + wire _T_17737 = _T_15557 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_8_2 = _T_17737 | _T_10040; // @[ifu_bp_ctl.scala 443:223] + wire _T_17754 = _T_15574 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_8_3 = _T_17754 | _T_10049; // @[ifu_bp_ctl.scala 443:223] + wire _T_17771 = _T_15591 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_8_4 = _T_17771 | _T_10058; // @[ifu_bp_ctl.scala 443:223] + wire _T_17788 = _T_15608 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_8_5 = _T_17788 | _T_10067; // @[ifu_bp_ctl.scala 443:223] + wire _T_17805 = _T_15625 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_8_6 = _T_17805 | _T_10076; // @[ifu_bp_ctl.scala 443:223] + wire _T_17822 = _T_15642 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_8_7 = _T_17822 | _T_10085; // @[ifu_bp_ctl.scala 443:223] + wire _T_17839 = _T_15659 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_8_8 = _T_17839 | _T_10094; // @[ifu_bp_ctl.scala 443:223] + wire _T_17856 = _T_15676 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_8_9 = _T_17856 | _T_10103; // @[ifu_bp_ctl.scala 443:223] + wire _T_17873 = _T_15693 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_8_10 = _T_17873 | _T_10112; // @[ifu_bp_ctl.scala 443:223] + wire _T_17890 = _T_15710 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_8_11 = _T_17890 | _T_10121; // @[ifu_bp_ctl.scala 443:223] + wire _T_17907 = _T_15727 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_8_12 = _T_17907 | _T_10130; // @[ifu_bp_ctl.scala 443:223] + wire _T_17924 = _T_15744 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_8_13 = _T_17924 | _T_10139; // @[ifu_bp_ctl.scala 443:223] + wire _T_17941 = _T_15761 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_8_14 = _T_17941 | _T_10148; // @[ifu_bp_ctl.scala 443:223] + wire _T_17958 = _T_15778 & _T_6298; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_8_15 = _T_17958 | _T_10157; // @[ifu_bp_ctl.scala 443:223] + wire _T_17975 = _T_15523 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_9_0 = _T_17975 | _T_10166; // @[ifu_bp_ctl.scala 443:223] + wire _T_17992 = _T_15540 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_9_1 = _T_17992 | _T_10175; // @[ifu_bp_ctl.scala 443:223] + wire _T_18009 = _T_15557 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_9_2 = _T_18009 | _T_10184; // @[ifu_bp_ctl.scala 443:223] + wire _T_18026 = _T_15574 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_9_3 = _T_18026 | _T_10193; // @[ifu_bp_ctl.scala 443:223] + wire _T_18043 = _T_15591 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_9_4 = _T_18043 | _T_10202; // @[ifu_bp_ctl.scala 443:223] + wire _T_18060 = _T_15608 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_9_5 = _T_18060 | _T_10211; // @[ifu_bp_ctl.scala 443:223] + wire _T_18077 = _T_15625 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_9_6 = _T_18077 | _T_10220; // @[ifu_bp_ctl.scala 443:223] + wire _T_18094 = _T_15642 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_9_7 = _T_18094 | _T_10229; // @[ifu_bp_ctl.scala 443:223] + wire _T_18111 = _T_15659 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_9_8 = _T_18111 | _T_10238; // @[ifu_bp_ctl.scala 443:223] + wire _T_18128 = _T_15676 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_9_9 = _T_18128 | _T_10247; // @[ifu_bp_ctl.scala 443:223] + wire _T_18145 = _T_15693 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_9_10 = _T_18145 | _T_10256; // @[ifu_bp_ctl.scala 443:223] + wire _T_18162 = _T_15710 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_9_11 = _T_18162 | _T_10265; // @[ifu_bp_ctl.scala 443:223] + wire _T_18179 = _T_15727 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_9_12 = _T_18179 | _T_10274; // @[ifu_bp_ctl.scala 443:223] + wire _T_18196 = _T_15744 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_9_13 = _T_18196 | _T_10283; // @[ifu_bp_ctl.scala 443:223] + wire _T_18213 = _T_15761 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_9_14 = _T_18213 | _T_10292; // @[ifu_bp_ctl.scala 443:223] + wire _T_18230 = _T_15778 & _T_6309; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_9_15 = _T_18230 | _T_10301; // @[ifu_bp_ctl.scala 443:223] + wire _T_18247 = _T_15523 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_10_0 = _T_18247 | _T_10310; // @[ifu_bp_ctl.scala 443:223] + wire _T_18264 = _T_15540 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_10_1 = _T_18264 | _T_10319; // @[ifu_bp_ctl.scala 443:223] + wire _T_18281 = _T_15557 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_10_2 = _T_18281 | _T_10328; // @[ifu_bp_ctl.scala 443:223] + wire _T_18298 = _T_15574 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_10_3 = _T_18298 | _T_10337; // @[ifu_bp_ctl.scala 443:223] + wire _T_18315 = _T_15591 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_10_4 = _T_18315 | _T_10346; // @[ifu_bp_ctl.scala 443:223] + wire _T_18332 = _T_15608 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_10_5 = _T_18332 | _T_10355; // @[ifu_bp_ctl.scala 443:223] + wire _T_18349 = _T_15625 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_10_6 = _T_18349 | _T_10364; // @[ifu_bp_ctl.scala 443:223] + wire _T_18366 = _T_15642 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_10_7 = _T_18366 | _T_10373; // @[ifu_bp_ctl.scala 443:223] + wire _T_18383 = _T_15659 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_10_8 = _T_18383 | _T_10382; // @[ifu_bp_ctl.scala 443:223] + wire _T_18400 = _T_15676 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_10_9 = _T_18400 | _T_10391; // @[ifu_bp_ctl.scala 443:223] + wire _T_18417 = _T_15693 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_10_10 = _T_18417 | _T_10400; // @[ifu_bp_ctl.scala 443:223] + wire _T_18434 = _T_15710 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_10_11 = _T_18434 | _T_10409; // @[ifu_bp_ctl.scala 443:223] + wire _T_18451 = _T_15727 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_10_12 = _T_18451 | _T_10418; // @[ifu_bp_ctl.scala 443:223] + wire _T_18468 = _T_15744 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_10_13 = _T_18468 | _T_10427; // @[ifu_bp_ctl.scala 443:223] + wire _T_18485 = _T_15761 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_10_14 = _T_18485 | _T_10436; // @[ifu_bp_ctl.scala 443:223] + wire _T_18502 = _T_15778 & _T_6320; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_10_15 = _T_18502 | _T_10445; // @[ifu_bp_ctl.scala 443:223] + wire _T_18519 = _T_15523 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_11_0 = _T_18519 | _T_10454; // @[ifu_bp_ctl.scala 443:223] + wire _T_18536 = _T_15540 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_11_1 = _T_18536 | _T_10463; // @[ifu_bp_ctl.scala 443:223] + wire _T_18553 = _T_15557 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_11_2 = _T_18553 | _T_10472; // @[ifu_bp_ctl.scala 443:223] + wire _T_18570 = _T_15574 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_11_3 = _T_18570 | _T_10481; // @[ifu_bp_ctl.scala 443:223] + wire _T_18587 = _T_15591 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_11_4 = _T_18587 | _T_10490; // @[ifu_bp_ctl.scala 443:223] + wire _T_18604 = _T_15608 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_11_5 = _T_18604 | _T_10499; // @[ifu_bp_ctl.scala 443:223] + wire _T_18621 = _T_15625 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_11_6 = _T_18621 | _T_10508; // @[ifu_bp_ctl.scala 443:223] + wire _T_18638 = _T_15642 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_11_7 = _T_18638 | _T_10517; // @[ifu_bp_ctl.scala 443:223] + wire _T_18655 = _T_15659 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_11_8 = _T_18655 | _T_10526; // @[ifu_bp_ctl.scala 443:223] + wire _T_18672 = _T_15676 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_11_9 = _T_18672 | _T_10535; // @[ifu_bp_ctl.scala 443:223] + wire _T_18689 = _T_15693 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_11_10 = _T_18689 | _T_10544; // @[ifu_bp_ctl.scala 443:223] + wire _T_18706 = _T_15710 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_11_11 = _T_18706 | _T_10553; // @[ifu_bp_ctl.scala 443:223] + wire _T_18723 = _T_15727 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_11_12 = _T_18723 | _T_10562; // @[ifu_bp_ctl.scala 443:223] + wire _T_18740 = _T_15744 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_11_13 = _T_18740 | _T_10571; // @[ifu_bp_ctl.scala 443:223] + wire _T_18757 = _T_15761 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_11_14 = _T_18757 | _T_10580; // @[ifu_bp_ctl.scala 443:223] + wire _T_18774 = _T_15778 & _T_6331; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_11_15 = _T_18774 | _T_10589; // @[ifu_bp_ctl.scala 443:223] + wire _T_18791 = _T_15523 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_12_0 = _T_18791 | _T_10598; // @[ifu_bp_ctl.scala 443:223] + wire _T_18808 = _T_15540 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_12_1 = _T_18808 | _T_10607; // @[ifu_bp_ctl.scala 443:223] + wire _T_18825 = _T_15557 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_12_2 = _T_18825 | _T_10616; // @[ifu_bp_ctl.scala 443:223] + wire _T_18842 = _T_15574 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_12_3 = _T_18842 | _T_10625; // @[ifu_bp_ctl.scala 443:223] + wire _T_18859 = _T_15591 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_12_4 = _T_18859 | _T_10634; // @[ifu_bp_ctl.scala 443:223] + wire _T_18876 = _T_15608 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_12_5 = _T_18876 | _T_10643; // @[ifu_bp_ctl.scala 443:223] + wire _T_18893 = _T_15625 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_12_6 = _T_18893 | _T_10652; // @[ifu_bp_ctl.scala 443:223] + wire _T_18910 = _T_15642 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_12_7 = _T_18910 | _T_10661; // @[ifu_bp_ctl.scala 443:223] + wire _T_18927 = _T_15659 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_12_8 = _T_18927 | _T_10670; // @[ifu_bp_ctl.scala 443:223] + wire _T_18944 = _T_15676 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_12_9 = _T_18944 | _T_10679; // @[ifu_bp_ctl.scala 443:223] + wire _T_18961 = _T_15693 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_12_10 = _T_18961 | _T_10688; // @[ifu_bp_ctl.scala 443:223] + wire _T_18978 = _T_15710 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_12_11 = _T_18978 | _T_10697; // @[ifu_bp_ctl.scala 443:223] + wire _T_18995 = _T_15727 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_12_12 = _T_18995 | _T_10706; // @[ifu_bp_ctl.scala 443:223] + wire _T_19012 = _T_15744 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_12_13 = _T_19012 | _T_10715; // @[ifu_bp_ctl.scala 443:223] + wire _T_19029 = _T_15761 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_12_14 = _T_19029 | _T_10724; // @[ifu_bp_ctl.scala 443:223] + wire _T_19046 = _T_15778 & _T_6342; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_12_15 = _T_19046 | _T_10733; // @[ifu_bp_ctl.scala 443:223] + wire _T_19063 = _T_15523 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_13_0 = _T_19063 | _T_10742; // @[ifu_bp_ctl.scala 443:223] + wire _T_19080 = _T_15540 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_13_1 = _T_19080 | _T_10751; // @[ifu_bp_ctl.scala 443:223] + wire _T_19097 = _T_15557 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_13_2 = _T_19097 | _T_10760; // @[ifu_bp_ctl.scala 443:223] + wire _T_19114 = _T_15574 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_13_3 = _T_19114 | _T_10769; // @[ifu_bp_ctl.scala 443:223] + wire _T_19131 = _T_15591 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_13_4 = _T_19131 | _T_10778; // @[ifu_bp_ctl.scala 443:223] + wire _T_19148 = _T_15608 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_13_5 = _T_19148 | _T_10787; // @[ifu_bp_ctl.scala 443:223] + wire _T_19165 = _T_15625 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_13_6 = _T_19165 | _T_10796; // @[ifu_bp_ctl.scala 443:223] + wire _T_19182 = _T_15642 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_13_7 = _T_19182 | _T_10805; // @[ifu_bp_ctl.scala 443:223] + wire _T_19199 = _T_15659 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_13_8 = _T_19199 | _T_10814; // @[ifu_bp_ctl.scala 443:223] + wire _T_19216 = _T_15676 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_13_9 = _T_19216 | _T_10823; // @[ifu_bp_ctl.scala 443:223] + wire _T_19233 = _T_15693 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_13_10 = _T_19233 | _T_10832; // @[ifu_bp_ctl.scala 443:223] + wire _T_19250 = _T_15710 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_13_11 = _T_19250 | _T_10841; // @[ifu_bp_ctl.scala 443:223] + wire _T_19267 = _T_15727 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_13_12 = _T_19267 | _T_10850; // @[ifu_bp_ctl.scala 443:223] + wire _T_19284 = _T_15744 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_13_13 = _T_19284 | _T_10859; // @[ifu_bp_ctl.scala 443:223] + wire _T_19301 = _T_15761 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_13_14 = _T_19301 | _T_10868; // @[ifu_bp_ctl.scala 443:223] + wire _T_19318 = _T_15778 & _T_6353; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_13_15 = _T_19318 | _T_10877; // @[ifu_bp_ctl.scala 443:223] + wire _T_19335 = _T_15523 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_14_0 = _T_19335 | _T_10886; // @[ifu_bp_ctl.scala 443:223] + wire _T_19352 = _T_15540 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_14_1 = _T_19352 | _T_10895; // @[ifu_bp_ctl.scala 443:223] + wire _T_19369 = _T_15557 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_14_2 = _T_19369 | _T_10904; // @[ifu_bp_ctl.scala 443:223] + wire _T_19386 = _T_15574 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_14_3 = _T_19386 | _T_10913; // @[ifu_bp_ctl.scala 443:223] + wire _T_19403 = _T_15591 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_14_4 = _T_19403 | _T_10922; // @[ifu_bp_ctl.scala 443:223] + wire _T_19420 = _T_15608 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_14_5 = _T_19420 | _T_10931; // @[ifu_bp_ctl.scala 443:223] + wire _T_19437 = _T_15625 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_14_6 = _T_19437 | _T_10940; // @[ifu_bp_ctl.scala 443:223] + wire _T_19454 = _T_15642 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_14_7 = _T_19454 | _T_10949; // @[ifu_bp_ctl.scala 443:223] + wire _T_19471 = _T_15659 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_14_8 = _T_19471 | _T_10958; // @[ifu_bp_ctl.scala 443:223] + wire _T_19488 = _T_15676 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_14_9 = _T_19488 | _T_10967; // @[ifu_bp_ctl.scala 443:223] + wire _T_19505 = _T_15693 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_14_10 = _T_19505 | _T_10976; // @[ifu_bp_ctl.scala 443:223] + wire _T_19522 = _T_15710 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_14_11 = _T_19522 | _T_10985; // @[ifu_bp_ctl.scala 443:223] + wire _T_19539 = _T_15727 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_14_12 = _T_19539 | _T_10994; // @[ifu_bp_ctl.scala 443:223] + wire _T_19556 = _T_15744 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_14_13 = _T_19556 | _T_11003; // @[ifu_bp_ctl.scala 443:223] + wire _T_19573 = _T_15761 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_14_14 = _T_19573 | _T_11012; // @[ifu_bp_ctl.scala 443:223] + wire _T_19590 = _T_15778 & _T_6364; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_14_15 = _T_19590 | _T_11021; // @[ifu_bp_ctl.scala 443:223] + wire _T_19607 = _T_15523 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_15_0 = _T_19607 | _T_11030; // @[ifu_bp_ctl.scala 443:223] + wire _T_19624 = _T_15540 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_15_1 = _T_19624 | _T_11039; // @[ifu_bp_ctl.scala 443:223] + wire _T_19641 = _T_15557 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_15_2 = _T_19641 | _T_11048; // @[ifu_bp_ctl.scala 443:223] + wire _T_19658 = _T_15574 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_15_3 = _T_19658 | _T_11057; // @[ifu_bp_ctl.scala 443:223] + wire _T_19675 = _T_15591 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_15_4 = _T_19675 | _T_11066; // @[ifu_bp_ctl.scala 443:223] + wire _T_19692 = _T_15608 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_15_5 = _T_19692 | _T_11075; // @[ifu_bp_ctl.scala 443:223] + wire _T_19709 = _T_15625 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_15_6 = _T_19709 | _T_11084; // @[ifu_bp_ctl.scala 443:223] + wire _T_19726 = _T_15642 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_15_7 = _T_19726 | _T_11093; // @[ifu_bp_ctl.scala 443:223] + wire _T_19743 = _T_15659 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_15_8 = _T_19743 | _T_11102; // @[ifu_bp_ctl.scala 443:223] + wire _T_19760 = _T_15676 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_15_9 = _T_19760 | _T_11111; // @[ifu_bp_ctl.scala 443:223] + wire _T_19777 = _T_15693 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_15_10 = _T_19777 | _T_11120; // @[ifu_bp_ctl.scala 443:223] + wire _T_19794 = _T_15710 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_15_11 = _T_19794 | _T_11129; // @[ifu_bp_ctl.scala 443:223] + wire _T_19811 = _T_15727 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_15_12 = _T_19811 | _T_11138; // @[ifu_bp_ctl.scala 443:223] + wire _T_19828 = _T_15744 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_15_13 = _T_19828 | _T_11147; // @[ifu_bp_ctl.scala 443:223] + wire _T_19845 = _T_15761 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_15_14 = _T_19845 | _T_11156; // @[ifu_bp_ctl.scala 443:223] + wire _T_19862 = _T_15778 & _T_6375; // @[ifu_bp_ctl.scala 443:110] + wire bht_bank_sel_1_15_15 = _T_19862 | _T_11165; // @[ifu_bp_ctl.scala 443:223] rvclkhdr rvclkhdr ( // @[lib.scala 352:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -26445,17 +26445,17 @@ module ifu_bp_ctl( .io_en(rvclkhdr_553_io_en), .io_scan_mode(rvclkhdr_553_io_scan_mode) ); - assign io_ifu_bp_hit_taken_f = _T_238 & _T_239; // @[ifu_bp_ctl.scala 260:25] - assign io_ifu_bp_btb_target_f = _T_429 ? rets_out_0[31:1] : bp_btb_target_adder_f[31:1]; // @[ifu_bp_ctl.scala 356:26] - assign io_ifu_bp_inst_mask_f = _T_275 | _T_276; // @[ifu_bp_ctl.scala 284:25] - assign io_ifu_bp_fghr_f = fghr; // @[ifu_bp_ctl.scala 324:20] - assign io_ifu_bp_way_f = tag_match_vway1_expanded_f | _T_213; // @[ifu_bp_ctl.scala 234:19] - assign io_ifu_bp_ret_f = {_T_295,_T_301}; // @[ifu_bp_ctl.scala 330:19] - assign io_ifu_bp_hist1_f = bht_force_taken_f | _T_280; // @[ifu_bp_ctl.scala 325:21] - assign io_ifu_bp_hist0_f = {bht_vbank1_rd_data_f[0],bht_vbank0_rd_data_f[0]}; // @[ifu_bp_ctl.scala 326:21] - assign io_ifu_bp_pc4_f = {_T_286,_T_289}; // @[ifu_bp_ctl.scala 327:19] - assign io_ifu_bp_valid_f = bht_valid_f & _T_345; // @[ifu_bp_ctl.scala 329:21] - assign io_ifu_bp_poffset_f = btb_sel_data_f[15:4]; // @[ifu_bp_ctl.scala 343:23] + assign io_ifu_bp_hit_taken_f = _T_238 & _T_239; // @[ifu_bp_ctl.scala 261:25] + assign io_ifu_bp_btb_target_f = _T_429 ? rets_out_0[31:1] : bp_btb_target_adder_f[31:1]; // @[ifu_bp_ctl.scala 357:26] + assign io_ifu_bp_inst_mask_f = _T_275 | _T_276; // @[ifu_bp_ctl.scala 285:25] + assign io_ifu_bp_fghr_f = fghr; // @[ifu_bp_ctl.scala 325:20] + assign io_ifu_bp_way_f = tag_match_vway1_expanded_f | _T_213; // @[ifu_bp_ctl.scala 235:19] + assign io_ifu_bp_ret_f = {_T_295,_T_301}; // @[ifu_bp_ctl.scala 331:19] + assign io_ifu_bp_hist1_f = bht_force_taken_f | _T_280; // @[ifu_bp_ctl.scala 326:21] + assign io_ifu_bp_hist0_f = {bht_vbank1_rd_data_f[0],bht_vbank0_rd_data_f[0]}; // @[ifu_bp_ctl.scala 327:21] + assign io_ifu_bp_pc4_f = {_T_286,_T_289}; // @[ifu_bp_ctl.scala 328:19] + assign io_ifu_bp_valid_f = bht_valid_f & _T_345; // @[ifu_bp_ctl.scala 330:21] + assign io_ifu_bp_poffset_f = btb_sel_data_f[15:4]; // @[ifu_bp_ctl.scala 344:23] assign rvclkhdr_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_io_en = io_ifc_fetch_req_f | exu_mp_valid; // @[lib.scala 355:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] @@ -44454,7 +44454,6 @@ module ifu( output io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way, output io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret, output io_ifu_dec_dec_aln_ifu_pmu_instr_aligned, - input io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_lower_wb, input io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb, input io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt, input io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt, @@ -44483,7 +44482,6 @@ module ifu( input io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error, input io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way, input io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle, - input io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb, input io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb, input io_ifu_dec_dec_bp_dec_tlu_bpred_disable, input [7:0] io_exu_ifu_exu_bp_exu_i0_br_index_r, @@ -44554,230 +44552,230 @@ module ifu( output [2:0] io_iccm_dma_rtag, output io_iccm_ready, output io_iccm_dma_sb_error, + input io_dec_tlu_flush_lower_wb, input io_scan_mode ); - wire mem_ctl_clock; // @[ifu.scala 37:23] - wire mem_ctl_reset; // @[ifu.scala 37:23] - wire mem_ctl_io_free_clk; // @[ifu.scala 37:23] - wire mem_ctl_io_active_clk; // @[ifu.scala 37:23] - wire mem_ctl_io_exu_flush_final; // @[ifu.scala 37:23] - wire mem_ctl_io_dec_mem_ctrl_dec_tlu_flush_lower_wb; // @[ifu.scala 37:23] - wire mem_ctl_io_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu.scala 37:23] - wire mem_ctl_io_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu.scala 37:23] - wire mem_ctl_io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu.scala 37:23] - wire mem_ctl_io_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[ifu.scala 37:23] - wire [70:0] mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[ifu.scala 37:23] - wire [16:0] mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[ifu.scala 37:23] - wire mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[ifu.scala 37:23] - wire mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[ifu.scala 37:23] - wire mem_ctl_io_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[ifu.scala 37:23] - wire mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_miss; // @[ifu.scala 37:23] - wire mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_hit; // @[ifu.scala 37:23] - wire mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_error; // @[ifu.scala 37:23] - wire mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_busy; // @[ifu.scala 37:23] - wire mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[ifu.scala 37:23] - wire mem_ctl_io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu.scala 37:23] - wire mem_ctl_io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[ifu.scala 37:23] - wire [70:0] mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[ifu.scala 37:23] - wire mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[ifu.scala 37:23] - wire mem_ctl_io_dec_mem_ctrl_ifu_miss_state_idle; // @[ifu.scala 37:23] - wire [30:0] mem_ctl_io_ifc_fetch_addr_bf; // @[ifu.scala 37:23] - wire mem_ctl_io_ifc_fetch_uncacheable_bf; // @[ifu.scala 37:23] - wire mem_ctl_io_ifc_fetch_req_bf; // @[ifu.scala 37:23] - wire mem_ctl_io_ifc_fetch_req_bf_raw; // @[ifu.scala 37:23] - wire mem_ctl_io_ifc_iccm_access_bf; // @[ifu.scala 37:23] - wire mem_ctl_io_ifc_region_acc_fault_bf; // @[ifu.scala 37:23] - wire mem_ctl_io_ifc_dma_access_ok; // @[ifu.scala 37:23] - wire mem_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 37:23] - wire mem_ctl_io_ifu_bp_inst_mask_f; // @[ifu.scala 37:23] - wire mem_ctl_io_ifu_axi_ar_ready; // @[ifu.scala 37:23] - wire mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 37:23] - wire [2:0] mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 37:23] - wire [31:0] mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 37:23] - wire [3:0] mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 37:23] - wire mem_ctl_io_ifu_axi_r_ready; // @[ifu.scala 37:23] - wire mem_ctl_io_ifu_axi_r_valid; // @[ifu.scala 37:23] - wire [2:0] mem_ctl_io_ifu_axi_r_bits_id; // @[ifu.scala 37:23] - wire [63:0] mem_ctl_io_ifu_axi_r_bits_data; // @[ifu.scala 37:23] - wire [1:0] mem_ctl_io_ifu_axi_r_bits_resp; // @[ifu.scala 37:23] - wire mem_ctl_io_ifu_bus_clk_en; // @[ifu.scala 37:23] - wire mem_ctl_io_dma_mem_ctl_dma_iccm_req; // @[ifu.scala 37:23] - wire [31:0] mem_ctl_io_dma_mem_ctl_dma_mem_addr; // @[ifu.scala 37:23] - wire [2:0] mem_ctl_io_dma_mem_ctl_dma_mem_sz; // @[ifu.scala 37:23] - wire mem_ctl_io_dma_mem_ctl_dma_mem_write; // @[ifu.scala 37:23] - wire [63:0] mem_ctl_io_dma_mem_ctl_dma_mem_wdata; // @[ifu.scala 37:23] - wire [2:0] mem_ctl_io_dma_mem_ctl_dma_mem_tag; // @[ifu.scala 37:23] - wire [14:0] mem_ctl_io_iccm_rw_addr; // @[ifu.scala 37:23] - wire mem_ctl_io_iccm_buf_correct_ecc; // @[ifu.scala 37:23] - wire mem_ctl_io_iccm_correction_state; // @[ifu.scala 37:23] - wire mem_ctl_io_iccm_wren; // @[ifu.scala 37:23] - wire mem_ctl_io_iccm_rden; // @[ifu.scala 37:23] - wire [2:0] mem_ctl_io_iccm_wr_size; // @[ifu.scala 37:23] - wire [77:0] mem_ctl_io_iccm_wr_data; // @[ifu.scala 37:23] - wire [63:0] mem_ctl_io_iccm_rd_data; // @[ifu.scala 37:23] - wire [77:0] mem_ctl_io_iccm_rd_data_ecc; // @[ifu.scala 37:23] - wire [30:0] mem_ctl_io_ic_rw_addr; // @[ifu.scala 37:23] - wire [1:0] mem_ctl_io_ic_tag_valid; // @[ifu.scala 37:23] - wire [1:0] mem_ctl_io_ic_wr_en; // @[ifu.scala 37:23] - wire mem_ctl_io_ic_rd_en; // @[ifu.scala 37:23] - wire [70:0] mem_ctl_io_ic_wr_data_0; // @[ifu.scala 37:23] - wire [70:0] mem_ctl_io_ic_wr_data_1; // @[ifu.scala 37:23] - wire [70:0] mem_ctl_io_ic_debug_wr_data; // @[ifu.scala 37:23] - wire [9:0] mem_ctl_io_ic_debug_addr; // @[ifu.scala 37:23] - wire [63:0] mem_ctl_io_ic_rd_data; // @[ifu.scala 37:23] - wire [70:0] mem_ctl_io_ic_debug_rd_data; // @[ifu.scala 37:23] - wire [25:0] mem_ctl_io_ic_tag_debug_rd_data; // @[ifu.scala 37:23] - wire [1:0] mem_ctl_io_ic_eccerr; // @[ifu.scala 37:23] - wire [1:0] mem_ctl_io_ic_rd_hit; // @[ifu.scala 37:23] - wire mem_ctl_io_ic_tag_perr; // @[ifu.scala 37:23] - wire mem_ctl_io_ic_debug_rd_en; // @[ifu.scala 37:23] - wire mem_ctl_io_ic_debug_wr_en; // @[ifu.scala 37:23] - wire mem_ctl_io_ic_debug_tag_array; // @[ifu.scala 37:23] - wire [1:0] mem_ctl_io_ic_debug_way; // @[ifu.scala 37:23] - wire [63:0] mem_ctl_io_ic_premux_data; // @[ifu.scala 37:23] - wire mem_ctl_io_ic_sel_premux_data; // @[ifu.scala 37:23] - wire [1:0] mem_ctl_io_ifu_fetch_val; // @[ifu.scala 37:23] - wire mem_ctl_io_ifu_ic_mb_empty; // @[ifu.scala 37:23] - wire mem_ctl_io_ic_dma_active; // @[ifu.scala 37:23] - wire mem_ctl_io_ic_write_stall; // @[ifu.scala 37:23] - wire mem_ctl_io_iccm_dma_ecc_error; // @[ifu.scala 37:23] - wire mem_ctl_io_iccm_dma_rvalid; // @[ifu.scala 37:23] - wire [63:0] mem_ctl_io_iccm_dma_rdata; // @[ifu.scala 37:23] - wire [2:0] mem_ctl_io_iccm_dma_rtag; // @[ifu.scala 37:23] - wire mem_ctl_io_iccm_ready; // @[ifu.scala 37:23] - wire mem_ctl_io_iccm_rd_ecc_double_err; // @[ifu.scala 37:23] - wire mem_ctl_io_iccm_dma_sb_error; // @[ifu.scala 37:23] - wire mem_ctl_io_ic_hit_f; // @[ifu.scala 37:23] - wire mem_ctl_io_ic_access_fault_f; // @[ifu.scala 37:23] - wire [1:0] mem_ctl_io_ic_access_fault_type_f; // @[ifu.scala 37:23] - wire mem_ctl_io_ifu_async_error_start; // @[ifu.scala 37:23] - wire [1:0] mem_ctl_io_ic_fetch_val_f; // @[ifu.scala 37:23] - wire [31:0] mem_ctl_io_ic_data_f; // @[ifu.scala 37:23] - wire mem_ctl_io_scan_mode; // @[ifu.scala 37:23] - wire bp_ctl_clock; // @[ifu.scala 38:22] - wire bp_ctl_reset; // @[ifu.scala 38:22] - wire bp_ctl_io_active_clk; // @[ifu.scala 38:22] - wire bp_ctl_io_ic_hit_f; // @[ifu.scala 38:22] - wire bp_ctl_io_exu_flush_final; // @[ifu.scala 38:22] - wire [30:0] bp_ctl_io_ifc_fetch_addr_f; // @[ifu.scala 38:22] - wire bp_ctl_io_ifc_fetch_req_f; // @[ifu.scala 38:22] - wire bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_valid; // @[ifu.scala 38:22] - wire [1:0] bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[ifu.scala 38:22] - wire bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[ifu.scala 38:22] - wire bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[ifu.scala 38:22] - wire bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[ifu.scala 38:22] - wire bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[ifu.scala 38:22] - wire bp_ctl_io_dec_bp_dec_tlu_flush_lower_wb; // @[ifu.scala 38:22] - wire bp_ctl_io_dec_bp_dec_tlu_flush_leak_one_wb; // @[ifu.scala 38:22] - wire bp_ctl_io_dec_bp_dec_tlu_bpred_disable; // @[ifu.scala 38:22] - wire [7:0] bp_ctl_io_exu_bp_exu_i0_br_index_r; // @[ifu.scala 38:22] - wire [7:0] bp_ctl_io_exu_bp_exu_i0_br_fghr_r; // @[ifu.scala 38:22] - wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_misp; // @[ifu.scala 38:22] - wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_ataken; // @[ifu.scala 38:22] - wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_boffset; // @[ifu.scala 38:22] - wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_pc4; // @[ifu.scala 38:22] - wire [1:0] bp_ctl_io_exu_bp_exu_mp_pkt_bits_hist; // @[ifu.scala 38:22] - wire [11:0] bp_ctl_io_exu_bp_exu_mp_pkt_bits_toffset; // @[ifu.scala 38:22] - wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_pcall; // @[ifu.scala 38:22] - wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_pret; // @[ifu.scala 38:22] - wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu.scala 38:22] - wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_way; // @[ifu.scala 38:22] - wire [7:0] bp_ctl_io_exu_bp_exu_mp_eghr; // @[ifu.scala 38:22] - wire [7:0] bp_ctl_io_exu_bp_exu_mp_fghr; // @[ifu.scala 38:22] - wire [7:0] bp_ctl_io_exu_bp_exu_mp_index; // @[ifu.scala 38:22] - wire [4:0] bp_ctl_io_exu_bp_exu_mp_btag; // @[ifu.scala 38:22] - wire bp_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 38:22] - wire [30:0] bp_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 38:22] - wire bp_ctl_io_ifu_bp_inst_mask_f; // @[ifu.scala 38:22] - wire [7:0] bp_ctl_io_ifu_bp_fghr_f; // @[ifu.scala 38:22] - wire [1:0] bp_ctl_io_ifu_bp_way_f; // @[ifu.scala 38:22] - wire [1:0] bp_ctl_io_ifu_bp_ret_f; // @[ifu.scala 38:22] - wire [1:0] bp_ctl_io_ifu_bp_hist1_f; // @[ifu.scala 38:22] - wire [1:0] bp_ctl_io_ifu_bp_hist0_f; // @[ifu.scala 38:22] - wire [1:0] bp_ctl_io_ifu_bp_pc4_f; // @[ifu.scala 38:22] - wire [1:0] bp_ctl_io_ifu_bp_valid_f; // @[ifu.scala 38:22] - wire [11:0] bp_ctl_io_ifu_bp_poffset_f; // @[ifu.scala 38:22] - wire bp_ctl_io_scan_mode; // @[ifu.scala 38:22] - wire aln_ctl_clock; // @[ifu.scala 39:23] - wire aln_ctl_reset; // @[ifu.scala 39:23] - wire aln_ctl_io_scan_mode; // @[ifu.scala 39:23] - wire aln_ctl_io_active_clk; // @[ifu.scala 39:23] - wire aln_ctl_io_ifu_async_error_start; // @[ifu.scala 39:23] - wire aln_ctl_io_iccm_rd_ecc_double_err; // @[ifu.scala 39:23] - wire aln_ctl_io_ic_access_fault_f; // @[ifu.scala 39:23] - wire [1:0] aln_ctl_io_ic_access_fault_type_f; // @[ifu.scala 39:23] - wire [7:0] aln_ctl_io_ifu_bp_fghr_f; // @[ifu.scala 39:23] - wire [30:0] aln_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 39:23] - wire [11:0] aln_ctl_io_ifu_bp_poffset_f; // @[ifu.scala 39:23] - wire [1:0] aln_ctl_io_ifu_bp_hist0_f; // @[ifu.scala 39:23] - wire [1:0] aln_ctl_io_ifu_bp_hist1_f; // @[ifu.scala 39:23] - wire [1:0] aln_ctl_io_ifu_bp_pc4_f; // @[ifu.scala 39:23] - wire [1:0] aln_ctl_io_ifu_bp_way_f; // @[ifu.scala 39:23] - wire [1:0] aln_ctl_io_ifu_bp_valid_f; // @[ifu.scala 39:23] - wire [1:0] aln_ctl_io_ifu_bp_ret_f; // @[ifu.scala 39:23] - wire aln_ctl_io_exu_flush_final; // @[ifu.scala 39:23] - wire aln_ctl_io_dec_aln_aln_dec_dec_i0_decode_d; // @[ifu.scala 39:23] - wire [15:0] aln_ctl_io_dec_aln_aln_dec_ifu_i0_cinst; // @[ifu.scala 39:23] - wire aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf; // @[ifu.scala 39:23] - wire [1:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_type; // @[ifu.scala 39:23] - wire aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[ifu.scala 39:23] - wire aln_ctl_io_dec_aln_aln_ib_ifu_i0_dbecc; // @[ifu.scala 39:23] - wire [7:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_index; // @[ifu.scala 39:23] - wire [7:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[ifu.scala 39:23] - wire [4:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_btag; // @[ifu.scala 39:23] - wire aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid; // @[ifu.scala 39:23] - wire [31:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_instr; // @[ifu.scala 39:23] - wire [30:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc; // @[ifu.scala 39:23] - wire aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc4; // @[ifu.scala 39:23] - wire aln_ctl_io_dec_aln_aln_ib_i0_brp_valid; // @[ifu.scala 39:23] - wire [11:0] aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_toffset; // @[ifu.scala 39:23] - wire [1:0] aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_hist; // @[ifu.scala 39:23] - wire aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_error; // @[ifu.scala 39:23] - wire aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[ifu.scala 39:23] - wire [30:0] aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_prett; // @[ifu.scala 39:23] - wire aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_way; // @[ifu.scala 39:23] - wire aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_ret; // @[ifu.scala 39:23] - wire aln_ctl_io_dec_aln_ifu_pmu_instr_aligned; // @[ifu.scala 39:23] - wire [31:0] aln_ctl_io_ifu_fetch_data_f; // @[ifu.scala 39:23] - wire [1:0] aln_ctl_io_ifu_fetch_val; // @[ifu.scala 39:23] - wire [30:0] aln_ctl_io_ifu_fetch_pc; // @[ifu.scala 39:23] - wire aln_ctl_io_ifu_fb_consume1; // @[ifu.scala 39:23] - wire aln_ctl_io_ifu_fb_consume2; // @[ifu.scala 39:23] - wire ifc_ctl_clock; // @[ifu.scala 40:23] - wire ifc_ctl_reset; // @[ifu.scala 40:23] - wire ifc_ctl_io_exu_flush_final; // @[ifu.scala 40:23] - wire [30:0] ifc_ctl_io_exu_flush_path_final; // @[ifu.scala 40:23] - wire ifc_ctl_io_free_clk; // @[ifu.scala 40:23] - wire ifc_ctl_io_active_clk; // @[ifu.scala 40:23] - wire ifc_ctl_io_scan_mode; // @[ifu.scala 40:23] - wire ifc_ctl_io_ic_hit_f; // @[ifu.scala 40:23] - wire ifc_ctl_io_ifu_ic_mb_empty; // @[ifu.scala 40:23] - wire ifc_ctl_io_ifu_fb_consume1; // @[ifu.scala 40:23] - wire ifc_ctl_io_ifu_fb_consume2; // @[ifu.scala 40:23] - wire ifc_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 40:23] - wire [30:0] ifc_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 40:23] - wire ifc_ctl_io_ic_dma_active; // @[ifu.scala 40:23] - wire ifc_ctl_io_ic_write_stall; // @[ifu.scala 40:23] - wire ifc_ctl_io_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu.scala 40:23] - wire [31:0] ifc_ctl_io_dec_ifc_dec_tlu_mrac_ff; // @[ifu.scala 40:23] - wire ifc_ctl_io_dec_ifc_ifu_pmu_fetch_stall; // @[ifu.scala 40:23] - wire ifc_ctl_io_dma_ifc_dma_iccm_stall_any; // @[ifu.scala 40:23] - wire [30:0] ifc_ctl_io_ifc_fetch_addr_f; // @[ifu.scala 40:23] - wire [30:0] ifc_ctl_io_ifc_fetch_addr_bf; // @[ifu.scala 40:23] - wire ifc_ctl_io_ifc_fetch_req_f; // @[ifu.scala 40:23] - wire ifc_ctl_io_ifc_fetch_uncacheable_bf; // @[ifu.scala 40:23] - wire ifc_ctl_io_ifc_fetch_req_bf; // @[ifu.scala 40:23] - wire ifc_ctl_io_ifc_fetch_req_bf_raw; // @[ifu.scala 40:23] - wire ifc_ctl_io_ifc_iccm_access_bf; // @[ifu.scala 40:23] - wire ifc_ctl_io_ifc_region_acc_fault_bf; // @[ifu.scala 40:23] - wire ifc_ctl_io_ifc_dma_access_ok; // @[ifu.scala 40:23] - ifu_mem_ctl mem_ctl ( // @[ifu.scala 37:23] + wire mem_ctl_clock; // @[ifu.scala 36:23] + wire mem_ctl_reset; // @[ifu.scala 36:23] + wire mem_ctl_io_free_clk; // @[ifu.scala 36:23] + wire mem_ctl_io_active_clk; // @[ifu.scala 36:23] + wire mem_ctl_io_exu_flush_final; // @[ifu.scala 36:23] + wire mem_ctl_io_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu.scala 36:23] + wire mem_ctl_io_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu.scala 36:23] + wire mem_ctl_io_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu.scala 36:23] + wire mem_ctl_io_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[ifu.scala 36:23] + wire [70:0] mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[ifu.scala 36:23] + wire [16:0] mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[ifu.scala 36:23] + wire mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[ifu.scala 36:23] + wire mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[ifu.scala 36:23] + wire mem_ctl_io_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[ifu.scala 36:23] + wire mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_miss; // @[ifu.scala 36:23] + wire mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_hit; // @[ifu.scala 36:23] + wire mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_error; // @[ifu.scala 36:23] + wire mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_busy; // @[ifu.scala 36:23] + wire mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[ifu.scala 36:23] + wire mem_ctl_io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu.scala 36:23] + wire mem_ctl_io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[ifu.scala 36:23] + wire [70:0] mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[ifu.scala 36:23] + wire mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[ifu.scala 36:23] + wire mem_ctl_io_dec_mem_ctrl_ifu_miss_state_idle; // @[ifu.scala 36:23] + wire [30:0] mem_ctl_io_ifc_fetch_addr_bf; // @[ifu.scala 36:23] + wire mem_ctl_io_ifc_fetch_uncacheable_bf; // @[ifu.scala 36:23] + wire mem_ctl_io_ifc_fetch_req_bf; // @[ifu.scala 36:23] + wire mem_ctl_io_ifc_fetch_req_bf_raw; // @[ifu.scala 36:23] + wire mem_ctl_io_ifc_iccm_access_bf; // @[ifu.scala 36:23] + wire mem_ctl_io_ifc_region_acc_fault_bf; // @[ifu.scala 36:23] + wire mem_ctl_io_ifc_dma_access_ok; // @[ifu.scala 36:23] + wire mem_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 36:23] + wire mem_ctl_io_ifu_bp_inst_mask_f; // @[ifu.scala 36:23] + wire mem_ctl_io_ifu_axi_ar_ready; // @[ifu.scala 36:23] + wire mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 36:23] + wire [2:0] mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 36:23] + wire [31:0] mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 36:23] + wire [3:0] mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 36:23] + wire mem_ctl_io_ifu_axi_r_ready; // @[ifu.scala 36:23] + wire mem_ctl_io_ifu_axi_r_valid; // @[ifu.scala 36:23] + wire [2:0] mem_ctl_io_ifu_axi_r_bits_id; // @[ifu.scala 36:23] + wire [63:0] mem_ctl_io_ifu_axi_r_bits_data; // @[ifu.scala 36:23] + wire [1:0] mem_ctl_io_ifu_axi_r_bits_resp; // @[ifu.scala 36:23] + wire mem_ctl_io_ifu_bus_clk_en; // @[ifu.scala 36:23] + wire mem_ctl_io_dma_mem_ctl_dma_iccm_req; // @[ifu.scala 36:23] + wire [31:0] mem_ctl_io_dma_mem_ctl_dma_mem_addr; // @[ifu.scala 36:23] + wire [2:0] mem_ctl_io_dma_mem_ctl_dma_mem_sz; // @[ifu.scala 36:23] + wire mem_ctl_io_dma_mem_ctl_dma_mem_write; // @[ifu.scala 36:23] + wire [63:0] mem_ctl_io_dma_mem_ctl_dma_mem_wdata; // @[ifu.scala 36:23] + wire [2:0] mem_ctl_io_dma_mem_ctl_dma_mem_tag; // @[ifu.scala 36:23] + wire [14:0] mem_ctl_io_iccm_rw_addr; // @[ifu.scala 36:23] + wire mem_ctl_io_iccm_buf_correct_ecc; // @[ifu.scala 36:23] + wire mem_ctl_io_iccm_correction_state; // @[ifu.scala 36:23] + wire mem_ctl_io_iccm_wren; // @[ifu.scala 36:23] + wire mem_ctl_io_iccm_rden; // @[ifu.scala 36:23] + wire [2:0] mem_ctl_io_iccm_wr_size; // @[ifu.scala 36:23] + wire [77:0] mem_ctl_io_iccm_wr_data; // @[ifu.scala 36:23] + wire [63:0] mem_ctl_io_iccm_rd_data; // @[ifu.scala 36:23] + wire [77:0] mem_ctl_io_iccm_rd_data_ecc; // @[ifu.scala 36:23] + wire [30:0] mem_ctl_io_ic_rw_addr; // @[ifu.scala 36:23] + wire [1:0] mem_ctl_io_ic_tag_valid; // @[ifu.scala 36:23] + wire [1:0] mem_ctl_io_ic_wr_en; // @[ifu.scala 36:23] + wire mem_ctl_io_ic_rd_en; // @[ifu.scala 36:23] + wire [70:0] mem_ctl_io_ic_wr_data_0; // @[ifu.scala 36:23] + wire [70:0] mem_ctl_io_ic_wr_data_1; // @[ifu.scala 36:23] + wire [70:0] mem_ctl_io_ic_debug_wr_data; // @[ifu.scala 36:23] + wire [9:0] mem_ctl_io_ic_debug_addr; // @[ifu.scala 36:23] + wire [63:0] mem_ctl_io_ic_rd_data; // @[ifu.scala 36:23] + wire [70:0] mem_ctl_io_ic_debug_rd_data; // @[ifu.scala 36:23] + wire [25:0] mem_ctl_io_ic_tag_debug_rd_data; // @[ifu.scala 36:23] + wire [1:0] mem_ctl_io_ic_eccerr; // @[ifu.scala 36:23] + wire [1:0] mem_ctl_io_ic_rd_hit; // @[ifu.scala 36:23] + wire mem_ctl_io_ic_tag_perr; // @[ifu.scala 36:23] + wire mem_ctl_io_ic_debug_rd_en; // @[ifu.scala 36:23] + wire mem_ctl_io_ic_debug_wr_en; // @[ifu.scala 36:23] + wire mem_ctl_io_ic_debug_tag_array; // @[ifu.scala 36:23] + wire [1:0] mem_ctl_io_ic_debug_way; // @[ifu.scala 36:23] + wire [63:0] mem_ctl_io_ic_premux_data; // @[ifu.scala 36:23] + wire mem_ctl_io_ic_sel_premux_data; // @[ifu.scala 36:23] + wire [1:0] mem_ctl_io_ifu_fetch_val; // @[ifu.scala 36:23] + wire mem_ctl_io_ifu_ic_mb_empty; // @[ifu.scala 36:23] + wire mem_ctl_io_ic_dma_active; // @[ifu.scala 36:23] + wire mem_ctl_io_ic_write_stall; // @[ifu.scala 36:23] + wire mem_ctl_io_iccm_dma_ecc_error; // @[ifu.scala 36:23] + wire mem_ctl_io_iccm_dma_rvalid; // @[ifu.scala 36:23] + wire [63:0] mem_ctl_io_iccm_dma_rdata; // @[ifu.scala 36:23] + wire [2:0] mem_ctl_io_iccm_dma_rtag; // @[ifu.scala 36:23] + wire mem_ctl_io_iccm_ready; // @[ifu.scala 36:23] + wire mem_ctl_io_dec_tlu_flush_lower_wb; // @[ifu.scala 36:23] + wire mem_ctl_io_iccm_rd_ecc_double_err; // @[ifu.scala 36:23] + wire mem_ctl_io_iccm_dma_sb_error; // @[ifu.scala 36:23] + wire mem_ctl_io_ic_hit_f; // @[ifu.scala 36:23] + wire mem_ctl_io_ic_access_fault_f; // @[ifu.scala 36:23] + wire [1:0] mem_ctl_io_ic_access_fault_type_f; // @[ifu.scala 36:23] + wire mem_ctl_io_ifu_async_error_start; // @[ifu.scala 36:23] + wire [1:0] mem_ctl_io_ic_fetch_val_f; // @[ifu.scala 36:23] + wire [31:0] mem_ctl_io_ic_data_f; // @[ifu.scala 36:23] + wire mem_ctl_io_scan_mode; // @[ifu.scala 36:23] + wire bp_ctl_clock; // @[ifu.scala 37:22] + wire bp_ctl_reset; // @[ifu.scala 37:22] + wire bp_ctl_io_active_clk; // @[ifu.scala 37:22] + wire bp_ctl_io_ic_hit_f; // @[ifu.scala 37:22] + wire bp_ctl_io_exu_flush_final; // @[ifu.scala 37:22] + wire [30:0] bp_ctl_io_ifc_fetch_addr_f; // @[ifu.scala 37:22] + wire bp_ctl_io_ifc_fetch_req_f; // @[ifu.scala 37:22] + wire bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_valid; // @[ifu.scala 37:22] + wire [1:0] bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[ifu.scala 37:22] + wire bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[ifu.scala 37:22] + wire bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[ifu.scala 37:22] + wire bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[ifu.scala 37:22] + wire bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[ifu.scala 37:22] + wire bp_ctl_io_dec_bp_dec_tlu_flush_leak_one_wb; // @[ifu.scala 37:22] + wire bp_ctl_io_dec_bp_dec_tlu_bpred_disable; // @[ifu.scala 37:22] + wire bp_ctl_io_dec_tlu_flush_lower_wb; // @[ifu.scala 37:22] + wire [7:0] bp_ctl_io_exu_bp_exu_i0_br_index_r; // @[ifu.scala 37:22] + wire [7:0] bp_ctl_io_exu_bp_exu_i0_br_fghr_r; // @[ifu.scala 37:22] + wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_misp; // @[ifu.scala 37:22] + wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_ataken; // @[ifu.scala 37:22] + wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_boffset; // @[ifu.scala 37:22] + wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_pc4; // @[ifu.scala 37:22] + wire [1:0] bp_ctl_io_exu_bp_exu_mp_pkt_bits_hist; // @[ifu.scala 37:22] + wire [11:0] bp_ctl_io_exu_bp_exu_mp_pkt_bits_toffset; // @[ifu.scala 37:22] + wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_pcall; // @[ifu.scala 37:22] + wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_pret; // @[ifu.scala 37:22] + wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_pja; // @[ifu.scala 37:22] + wire bp_ctl_io_exu_bp_exu_mp_pkt_bits_way; // @[ifu.scala 37:22] + wire [7:0] bp_ctl_io_exu_bp_exu_mp_eghr; // @[ifu.scala 37:22] + wire [7:0] bp_ctl_io_exu_bp_exu_mp_fghr; // @[ifu.scala 37:22] + wire [7:0] bp_ctl_io_exu_bp_exu_mp_index; // @[ifu.scala 37:22] + wire [4:0] bp_ctl_io_exu_bp_exu_mp_btag; // @[ifu.scala 37:22] + wire bp_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 37:22] + wire [30:0] bp_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 37:22] + wire bp_ctl_io_ifu_bp_inst_mask_f; // @[ifu.scala 37:22] + wire [7:0] bp_ctl_io_ifu_bp_fghr_f; // @[ifu.scala 37:22] + wire [1:0] bp_ctl_io_ifu_bp_way_f; // @[ifu.scala 37:22] + wire [1:0] bp_ctl_io_ifu_bp_ret_f; // @[ifu.scala 37:22] + wire [1:0] bp_ctl_io_ifu_bp_hist1_f; // @[ifu.scala 37:22] + wire [1:0] bp_ctl_io_ifu_bp_hist0_f; // @[ifu.scala 37:22] + wire [1:0] bp_ctl_io_ifu_bp_pc4_f; // @[ifu.scala 37:22] + wire [1:0] bp_ctl_io_ifu_bp_valid_f; // @[ifu.scala 37:22] + wire [11:0] bp_ctl_io_ifu_bp_poffset_f; // @[ifu.scala 37:22] + wire bp_ctl_io_scan_mode; // @[ifu.scala 37:22] + wire aln_ctl_clock; // @[ifu.scala 38:23] + wire aln_ctl_reset; // @[ifu.scala 38:23] + wire aln_ctl_io_scan_mode; // @[ifu.scala 38:23] + wire aln_ctl_io_active_clk; // @[ifu.scala 38:23] + wire aln_ctl_io_ifu_async_error_start; // @[ifu.scala 38:23] + wire aln_ctl_io_iccm_rd_ecc_double_err; // @[ifu.scala 38:23] + wire aln_ctl_io_ic_access_fault_f; // @[ifu.scala 38:23] + wire [1:0] aln_ctl_io_ic_access_fault_type_f; // @[ifu.scala 38:23] + wire [7:0] aln_ctl_io_ifu_bp_fghr_f; // @[ifu.scala 38:23] + wire [30:0] aln_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 38:23] + wire [11:0] aln_ctl_io_ifu_bp_poffset_f; // @[ifu.scala 38:23] + wire [1:0] aln_ctl_io_ifu_bp_hist0_f; // @[ifu.scala 38:23] + wire [1:0] aln_ctl_io_ifu_bp_hist1_f; // @[ifu.scala 38:23] + wire [1:0] aln_ctl_io_ifu_bp_pc4_f; // @[ifu.scala 38:23] + wire [1:0] aln_ctl_io_ifu_bp_way_f; // @[ifu.scala 38:23] + wire [1:0] aln_ctl_io_ifu_bp_valid_f; // @[ifu.scala 38:23] + wire [1:0] aln_ctl_io_ifu_bp_ret_f; // @[ifu.scala 38:23] + wire aln_ctl_io_exu_flush_final; // @[ifu.scala 38:23] + wire aln_ctl_io_dec_aln_aln_dec_dec_i0_decode_d; // @[ifu.scala 38:23] + wire [15:0] aln_ctl_io_dec_aln_aln_dec_ifu_i0_cinst; // @[ifu.scala 38:23] + wire aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf; // @[ifu.scala 38:23] + wire [1:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_type; // @[ifu.scala 38:23] + wire aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[ifu.scala 38:23] + wire aln_ctl_io_dec_aln_aln_ib_ifu_i0_dbecc; // @[ifu.scala 38:23] + wire [7:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_index; // @[ifu.scala 38:23] + wire [7:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[ifu.scala 38:23] + wire [4:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_btag; // @[ifu.scala 38:23] + wire aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid; // @[ifu.scala 38:23] + wire [31:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_instr; // @[ifu.scala 38:23] + wire [30:0] aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc; // @[ifu.scala 38:23] + wire aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc4; // @[ifu.scala 38:23] + wire aln_ctl_io_dec_aln_aln_ib_i0_brp_valid; // @[ifu.scala 38:23] + wire [11:0] aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_toffset; // @[ifu.scala 38:23] + wire [1:0] aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_hist; // @[ifu.scala 38:23] + wire aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_error; // @[ifu.scala 38:23] + wire aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[ifu.scala 38:23] + wire [30:0] aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_prett; // @[ifu.scala 38:23] + wire aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_way; // @[ifu.scala 38:23] + wire aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_ret; // @[ifu.scala 38:23] + wire aln_ctl_io_dec_aln_ifu_pmu_instr_aligned; // @[ifu.scala 38:23] + wire [31:0] aln_ctl_io_ifu_fetch_data_f; // @[ifu.scala 38:23] + wire [1:0] aln_ctl_io_ifu_fetch_val; // @[ifu.scala 38:23] + wire [30:0] aln_ctl_io_ifu_fetch_pc; // @[ifu.scala 38:23] + wire aln_ctl_io_ifu_fb_consume1; // @[ifu.scala 38:23] + wire aln_ctl_io_ifu_fb_consume2; // @[ifu.scala 38:23] + wire ifc_ctl_clock; // @[ifu.scala 39:23] + wire ifc_ctl_reset; // @[ifu.scala 39:23] + wire ifc_ctl_io_exu_flush_final; // @[ifu.scala 39:23] + wire [30:0] ifc_ctl_io_exu_flush_path_final; // @[ifu.scala 39:23] + wire ifc_ctl_io_free_clk; // @[ifu.scala 39:23] + wire ifc_ctl_io_active_clk; // @[ifu.scala 39:23] + wire ifc_ctl_io_scan_mode; // @[ifu.scala 39:23] + wire ifc_ctl_io_ic_hit_f; // @[ifu.scala 39:23] + wire ifc_ctl_io_ifu_ic_mb_empty; // @[ifu.scala 39:23] + wire ifc_ctl_io_ifu_fb_consume1; // @[ifu.scala 39:23] + wire ifc_ctl_io_ifu_fb_consume2; // @[ifu.scala 39:23] + wire ifc_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 39:23] + wire [30:0] ifc_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 39:23] + wire ifc_ctl_io_ic_dma_active; // @[ifu.scala 39:23] + wire ifc_ctl_io_ic_write_stall; // @[ifu.scala 39:23] + wire ifc_ctl_io_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu.scala 39:23] + wire [31:0] ifc_ctl_io_dec_ifc_dec_tlu_mrac_ff; // @[ifu.scala 39:23] + wire ifc_ctl_io_dec_ifc_ifu_pmu_fetch_stall; // @[ifu.scala 39:23] + wire ifc_ctl_io_dma_ifc_dma_iccm_stall_any; // @[ifu.scala 39:23] + wire [30:0] ifc_ctl_io_ifc_fetch_addr_f; // @[ifu.scala 39:23] + wire [30:0] ifc_ctl_io_ifc_fetch_addr_bf; // @[ifu.scala 39:23] + wire ifc_ctl_io_ifc_fetch_req_f; // @[ifu.scala 39:23] + wire ifc_ctl_io_ifc_fetch_uncacheable_bf; // @[ifu.scala 39:23] + wire ifc_ctl_io_ifc_fetch_req_bf; // @[ifu.scala 39:23] + wire ifc_ctl_io_ifc_fetch_req_bf_raw; // @[ifu.scala 39:23] + wire ifc_ctl_io_ifc_iccm_access_bf; // @[ifu.scala 39:23] + wire ifc_ctl_io_ifc_region_acc_fault_bf; // @[ifu.scala 39:23] + wire ifc_ctl_io_ifc_dma_access_ok; // @[ifu.scala 39:23] + ifu_mem_ctl mem_ctl ( // @[ifu.scala 36:23] .clock(mem_ctl_clock), .reset(mem_ctl_reset), .io_free_clk(mem_ctl_io_free_clk), .io_active_clk(mem_ctl_io_active_clk), .io_exu_flush_final(mem_ctl_io_exu_flush_final), - .io_dec_mem_ctrl_dec_tlu_flush_lower_wb(mem_ctl_io_dec_mem_ctrl_dec_tlu_flush_lower_wb), .io_dec_mem_ctrl_dec_tlu_flush_err_wb(mem_ctl_io_dec_mem_ctrl_dec_tlu_flush_err_wb), .io_dec_mem_ctrl_dec_tlu_i0_commit_cmt(mem_ctl_io_dec_mem_ctrl_dec_tlu_i0_commit_cmt), .io_dec_mem_ctrl_dec_tlu_force_halt(mem_ctl_io_dec_mem_ctrl_dec_tlu_force_halt), @@ -44861,6 +44859,7 @@ module ifu( .io_iccm_dma_rdata(mem_ctl_io_iccm_dma_rdata), .io_iccm_dma_rtag(mem_ctl_io_iccm_dma_rtag), .io_iccm_ready(mem_ctl_io_iccm_ready), + .io_dec_tlu_flush_lower_wb(mem_ctl_io_dec_tlu_flush_lower_wb), .io_iccm_rd_ecc_double_err(mem_ctl_io_iccm_rd_ecc_double_err), .io_iccm_dma_sb_error(mem_ctl_io_iccm_dma_sb_error), .io_ic_hit_f(mem_ctl_io_ic_hit_f), @@ -44871,7 +44870,7 @@ module ifu( .io_ic_data_f(mem_ctl_io_ic_data_f), .io_scan_mode(mem_ctl_io_scan_mode) ); - ifu_bp_ctl bp_ctl ( // @[ifu.scala 38:22] + ifu_bp_ctl bp_ctl ( // @[ifu.scala 37:22] .clock(bp_ctl_clock), .reset(bp_ctl_reset), .io_active_clk(bp_ctl_io_active_clk), @@ -44885,9 +44884,9 @@ module ifu( .io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error(bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error), .io_dec_bp_dec_tlu_br0_r_pkt_bits_way(bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_way), .io_dec_bp_dec_tlu_br0_r_pkt_bits_middle(bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_middle), - .io_dec_bp_dec_tlu_flush_lower_wb(bp_ctl_io_dec_bp_dec_tlu_flush_lower_wb), .io_dec_bp_dec_tlu_flush_leak_one_wb(bp_ctl_io_dec_bp_dec_tlu_flush_leak_one_wb), .io_dec_bp_dec_tlu_bpred_disable(bp_ctl_io_dec_bp_dec_tlu_bpred_disable), + .io_dec_tlu_flush_lower_wb(bp_ctl_io_dec_tlu_flush_lower_wb), .io_exu_bp_exu_i0_br_index_r(bp_ctl_io_exu_bp_exu_i0_br_index_r), .io_exu_bp_exu_i0_br_fghr_r(bp_ctl_io_exu_bp_exu_i0_br_fghr_r), .io_exu_bp_exu_mp_pkt_bits_misp(bp_ctl_io_exu_bp_exu_mp_pkt_bits_misp), @@ -44917,7 +44916,7 @@ module ifu( .io_ifu_bp_poffset_f(bp_ctl_io_ifu_bp_poffset_f), .io_scan_mode(bp_ctl_io_scan_mode) ); - ifu_aln_ctl aln_ctl ( // @[ifu.scala 39:23] + ifu_aln_ctl aln_ctl ( // @[ifu.scala 38:23] .clock(aln_ctl_clock), .reset(aln_ctl_reset), .io_scan_mode(aln_ctl_io_scan_mode), @@ -44964,7 +44963,7 @@ module ifu( .io_ifu_fb_consume1(aln_ctl_io_ifu_fb_consume1), .io_ifu_fb_consume2(aln_ctl_io_ifu_fb_consume2) ); - ifu_ifc_ctl ifc_ctl ( // @[ifu.scala 40:23] + ifu_ifc_ctl ifc_ctl ( // @[ifu.scala 39:23] .clock(ifc_ctl_clock), .reset(ifc_ctl_reset), .io_exu_flush_final(ifc_ctl_io_exu_flush_final), @@ -44994,63 +44993,63 @@ module ifu( .io_ifc_region_acc_fault_bf(ifc_ctl_io_ifc_region_acc_fault_bf), .io_ifc_dma_access_ok(ifc_ctl_io_ifc_dma_access_ok) ); - assign io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst = aln_ctl_io_dec_aln_aln_dec_ifu_i0_cinst; // @[ifu.scala 76:22] - assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf = aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf; // @[ifu.scala 76:22] - assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type = aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_type; // @[ifu.scala 76:22] - assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1 = aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[ifu.scala 76:22] - assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc = aln_ctl_io_dec_aln_aln_ib_ifu_i0_dbecc; // @[ifu.scala 76:22] - assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index = aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_index; // @[ifu.scala 76:22] - assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr = aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[ifu.scala 76:22] - assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag = aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_btag; // @[ifu.scala 76:22] - assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid = aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid; // @[ifu.scala 76:22] - assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr = aln_ctl_io_dec_aln_aln_ib_ifu_i0_instr; // @[ifu.scala 76:22] - assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc = aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc; // @[ifu.scala 76:22] - assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4 = aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc4; // @[ifu.scala 76:22] - assign io_ifu_dec_dec_aln_aln_ib_i0_brp_valid = aln_ctl_io_dec_aln_aln_ib_i0_brp_valid; // @[ifu.scala 76:22] - assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_toffset; // @[ifu.scala 76:22] - assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_hist; // @[ifu.scala 76:22] - assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_error; // @[ifu.scala 76:22] - assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[ifu.scala 76:22] - assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_prett; // @[ifu.scala 76:22] - assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_way; // @[ifu.scala 76:22] - assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_ret; // @[ifu.scala 76:22] - assign io_ifu_dec_dec_aln_ifu_pmu_instr_aligned = aln_ctl_io_dec_aln_ifu_pmu_instr_aligned; // @[ifu.scala 76:22] - assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss = mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_miss; // @[ifu.scala 95:27] - assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_hit; // @[ifu.scala 95:27] - assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_error; // @[ifu.scala 95:27] - assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_busy; // @[ifu.scala 95:27] - assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[ifu.scala 95:27] - assign io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = mem_ctl_io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu.scala 95:27] - assign io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = mem_ctl_io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[ifu.scala 95:27] - assign io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[ifu.scala 95:27] - assign io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[ifu.scala 95:27] - assign io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle = mem_ctl_io_dec_mem_ctrl_ifu_miss_state_idle; // @[ifu.scala 95:27] - assign io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall = ifc_ctl_io_dec_ifc_ifu_pmu_fetch_stall; // @[ifu.scala 49:22] - assign io_iccm_rw_addr = mem_ctl_io_iccm_rw_addr; // @[ifu.scala 109:19] - assign io_iccm_buf_correct_ecc = mem_ctl_io_iccm_buf_correct_ecc; // @[ifu.scala 109:19] - assign io_iccm_correction_state = mem_ctl_io_iccm_correction_state; // @[ifu.scala 109:19] - assign io_iccm_wren = mem_ctl_io_iccm_wren; // @[ifu.scala 109:19] - assign io_iccm_rden = mem_ctl_io_iccm_rden; // @[ifu.scala 109:19] - assign io_iccm_wr_size = mem_ctl_io_iccm_wr_size; // @[ifu.scala 109:19] - assign io_iccm_wr_data = mem_ctl_io_iccm_wr_data; // @[ifu.scala 109:19] - assign io_ic_rw_addr = mem_ctl_io_ic_rw_addr; // @[ifu.scala 108:17] - assign io_ic_tag_valid = mem_ctl_io_ic_tag_valid; // @[ifu.scala 108:17] - assign io_ic_wr_en = mem_ctl_io_ic_wr_en; // @[ifu.scala 108:17] - assign io_ic_rd_en = mem_ctl_io_ic_rd_en; // @[ifu.scala 108:17] - assign io_ic_wr_data_0 = mem_ctl_io_ic_wr_data_0; // @[ifu.scala 108:17] - assign io_ic_wr_data_1 = mem_ctl_io_ic_wr_data_1; // @[ifu.scala 108:17] - assign io_ic_debug_wr_data = mem_ctl_io_ic_debug_wr_data; // @[ifu.scala 108:17] - assign io_ic_debug_addr = mem_ctl_io_ic_debug_addr; // @[ifu.scala 108:17] - assign io_ic_debug_rd_en = mem_ctl_io_ic_debug_rd_en; // @[ifu.scala 108:17] - assign io_ic_debug_wr_en = mem_ctl_io_ic_debug_wr_en; // @[ifu.scala 108:17] - assign io_ic_debug_tag_array = mem_ctl_io_ic_debug_tag_array; // @[ifu.scala 108:17] - assign io_ic_debug_way = mem_ctl_io_ic_debug_way; // @[ifu.scala 108:17] - assign io_ic_premux_data = mem_ctl_io_ic_premux_data; // @[ifu.scala 108:17] - assign io_ic_sel_premux_data = mem_ctl_io_ic_sel_premux_data; // @[ifu.scala 108:17] - assign io_ifu_ar_valid = mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 105:22] - assign io_ifu_ar_bits_id = mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 105:22] - assign io_ifu_ar_bits_addr = mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 105:22] - assign io_ifu_ar_bits_region = mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 105:22] + assign io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst = aln_ctl_io_dec_aln_aln_dec_ifu_i0_cinst; // @[ifu.scala 75:22] + assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf = aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf; // @[ifu.scala 75:22] + assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type = aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_type; // @[ifu.scala 75:22] + assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1 = aln_ctl_io_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[ifu.scala 75:22] + assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc = aln_ctl_io_dec_aln_aln_ib_ifu_i0_dbecc; // @[ifu.scala 75:22] + assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index = aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_index; // @[ifu.scala 75:22] + assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr = aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[ifu.scala 75:22] + assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag = aln_ctl_io_dec_aln_aln_ib_ifu_i0_bp_btag; // @[ifu.scala 75:22] + assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid = aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid; // @[ifu.scala 75:22] + assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr = aln_ctl_io_dec_aln_aln_ib_ifu_i0_instr; // @[ifu.scala 75:22] + assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc = aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc; // @[ifu.scala 75:22] + assign io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4 = aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc4; // @[ifu.scala 75:22] + assign io_ifu_dec_dec_aln_aln_ib_i0_brp_valid = aln_ctl_io_dec_aln_aln_ib_i0_brp_valid; // @[ifu.scala 75:22] + assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_toffset; // @[ifu.scala 75:22] + assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_hist; // @[ifu.scala 75:22] + assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_error; // @[ifu.scala 75:22] + assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[ifu.scala 75:22] + assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_prett; // @[ifu.scala 75:22] + assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_way; // @[ifu.scala 75:22] + assign io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret = aln_ctl_io_dec_aln_aln_ib_i0_brp_bits_ret; // @[ifu.scala 75:22] + assign io_ifu_dec_dec_aln_ifu_pmu_instr_aligned = aln_ctl_io_dec_aln_ifu_pmu_instr_aligned; // @[ifu.scala 75:22] + assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss = mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_miss; // @[ifu.scala 94:27] + assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = mem_ctl_io_dec_mem_ctrl_ifu_pmu_ic_hit; // @[ifu.scala 94:27] + assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_error; // @[ifu.scala 94:27] + assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_busy; // @[ifu.scala 94:27] + assign io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = mem_ctl_io_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[ifu.scala 94:27] + assign io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = mem_ctl_io_dec_mem_ctrl_ifu_ic_error_start; // @[ifu.scala 94:27] + assign io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = mem_ctl_io_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[ifu.scala 94:27] + assign io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[ifu.scala 94:27] + assign io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = mem_ctl_io_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[ifu.scala 94:27] + assign io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle = mem_ctl_io_dec_mem_ctrl_ifu_miss_state_idle; // @[ifu.scala 94:27] + assign io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall = ifc_ctl_io_dec_ifc_ifu_pmu_fetch_stall; // @[ifu.scala 48:22] + assign io_iccm_rw_addr = mem_ctl_io_iccm_rw_addr; // @[ifu.scala 108:19] + assign io_iccm_buf_correct_ecc = mem_ctl_io_iccm_buf_correct_ecc; // @[ifu.scala 108:19] + assign io_iccm_correction_state = mem_ctl_io_iccm_correction_state; // @[ifu.scala 108:19] + assign io_iccm_wren = mem_ctl_io_iccm_wren; // @[ifu.scala 108:19] + assign io_iccm_rden = mem_ctl_io_iccm_rden; // @[ifu.scala 108:19] + assign io_iccm_wr_size = mem_ctl_io_iccm_wr_size; // @[ifu.scala 108:19] + assign io_iccm_wr_data = mem_ctl_io_iccm_wr_data; // @[ifu.scala 108:19] + assign io_ic_rw_addr = mem_ctl_io_ic_rw_addr; // @[ifu.scala 107:17] + assign io_ic_tag_valid = mem_ctl_io_ic_tag_valid; // @[ifu.scala 107:17] + assign io_ic_wr_en = mem_ctl_io_ic_wr_en; // @[ifu.scala 107:17] + assign io_ic_rd_en = mem_ctl_io_ic_rd_en; // @[ifu.scala 107:17] + assign io_ic_wr_data_0 = mem_ctl_io_ic_wr_data_0; // @[ifu.scala 107:17] + assign io_ic_wr_data_1 = mem_ctl_io_ic_wr_data_1; // @[ifu.scala 107:17] + assign io_ic_debug_wr_data = mem_ctl_io_ic_debug_wr_data; // @[ifu.scala 107:17] + assign io_ic_debug_addr = mem_ctl_io_ic_debug_addr; // @[ifu.scala 107:17] + assign io_ic_debug_rd_en = mem_ctl_io_ic_debug_rd_en; // @[ifu.scala 107:17] + assign io_ic_debug_wr_en = mem_ctl_io_ic_debug_wr_en; // @[ifu.scala 107:17] + assign io_ic_debug_tag_array = mem_ctl_io_ic_debug_tag_array; // @[ifu.scala 107:17] + assign io_ic_debug_way = mem_ctl_io_ic_debug_way; // @[ifu.scala 107:17] + assign io_ic_premux_data = mem_ctl_io_ic_premux_data; // @[ifu.scala 107:17] + assign io_ic_sel_premux_data = mem_ctl_io_ic_sel_premux_data; // @[ifu.scala 107:17] + assign io_ifu_ar_valid = mem_ctl_io_ifu_axi_ar_valid; // @[ifu.scala 104:22] + assign io_ifu_ar_bits_id = mem_ctl_io_ifu_axi_ar_bits_id; // @[ifu.scala 104:22] + assign io_ifu_ar_bits_addr = mem_ctl_io_ifu_axi_ar_bits_addr; // @[ifu.scala 104:22] + assign io_ifu_ar_bits_region = mem_ctl_io_ifu_axi_ar_bits_region; // @[ifu.scala 104:22] assign io_iccm_dma_ecc_error = mem_ctl_io_iccm_dma_ecc_error; // @[ifu.scala 113:25] assign io_iccm_dma_rvalid = mem_ctl_io_iccm_dma_rvalid; // @[ifu.scala 114:22] assign io_iccm_dma_rdata = mem_ctl_io_iccm_dma_rdata; // @[ifu.scala 115:21] @@ -45059,123 +45058,123 @@ module ifu( assign io_iccm_dma_sb_error = mem_ctl_io_iccm_dma_sb_error; // @[ifu.scala 119:24] assign mem_ctl_clock = clock; assign mem_ctl_reset = reset; - assign mem_ctl_io_free_clk = io_free_clk; // @[ifu.scala 92:23] - assign mem_ctl_io_active_clk = io_active_clk; // @[ifu.scala 93:25] - assign mem_ctl_io_exu_flush_final = io_exu_flush_final; // @[ifu.scala 94:30] - assign mem_ctl_io_dec_mem_ctrl_dec_tlu_flush_lower_wb = io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_lower_wb; // @[ifu.scala 95:27] - assign mem_ctl_io_dec_mem_ctrl_dec_tlu_flush_err_wb = io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu.scala 95:27] - assign mem_ctl_io_dec_mem_ctrl_dec_tlu_i0_commit_cmt = io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu.scala 95:27] - assign mem_ctl_io_dec_mem_ctrl_dec_tlu_force_halt = io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu.scala 95:27] - assign mem_ctl_io_dec_mem_ctrl_dec_tlu_fence_i_wb = io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[ifu.scala 95:27] - assign mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[ifu.scala 95:27] - assign mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[ifu.scala 95:27] - assign mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[ifu.scala 95:27] - assign mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[ifu.scala 95:27] - assign mem_ctl_io_dec_mem_ctrl_dec_tlu_core_ecc_disable = io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[ifu.scala 95:27] - assign mem_ctl_io_ifc_fetch_addr_bf = ifc_ctl_io_ifc_fetch_addr_bf; // @[ifu.scala 96:32] - assign mem_ctl_io_ifc_fetch_uncacheable_bf = ifc_ctl_io_ifc_fetch_uncacheable_bf; // @[ifu.scala 97:39] - assign mem_ctl_io_ifc_fetch_req_bf = ifc_ctl_io_ifc_fetch_req_bf; // @[ifu.scala 98:31] - assign mem_ctl_io_ifc_fetch_req_bf_raw = ifc_ctl_io_ifc_fetch_req_bf_raw; // @[ifu.scala 99:35] - assign mem_ctl_io_ifc_iccm_access_bf = ifc_ctl_io_ifc_iccm_access_bf; // @[ifu.scala 100:33] - assign mem_ctl_io_ifc_region_acc_fault_bf = ifc_ctl_io_ifc_region_acc_fault_bf; // @[ifu.scala 101:38] - assign mem_ctl_io_ifc_dma_access_ok = ifc_ctl_io_ifc_dma_access_ok; // @[ifu.scala 102:32] - assign mem_ctl_io_ifu_bp_hit_taken_f = bp_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 103:33] - assign mem_ctl_io_ifu_bp_inst_mask_f = bp_ctl_io_ifu_bp_inst_mask_f; // @[ifu.scala 104:33] - assign mem_ctl_io_ifu_axi_ar_ready = io_ifu_ar_ready; // @[ifu.scala 105:22] - assign mem_ctl_io_ifu_axi_r_valid = io_ifu_r_valid; // @[ifu.scala 105:22] - assign mem_ctl_io_ifu_axi_r_bits_id = io_ifu_r_bits_id; // @[ifu.scala 105:22] - assign mem_ctl_io_ifu_axi_r_bits_data = io_ifu_r_bits_data; // @[ifu.scala 105:22] - assign mem_ctl_io_ifu_axi_r_bits_resp = io_ifu_r_bits_resp; // @[ifu.scala 105:22] - assign mem_ctl_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[ifu.scala 106:29] - assign mem_ctl_io_dma_mem_ctl_dma_iccm_req = io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[ifu.scala 107:26] - assign mem_ctl_io_dma_mem_ctl_dma_mem_addr = io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[ifu.scala 107:26] - assign mem_ctl_io_dma_mem_ctl_dma_mem_sz = io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[ifu.scala 107:26] - assign mem_ctl_io_dma_mem_ctl_dma_mem_write = io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[ifu.scala 107:26] - assign mem_ctl_io_dma_mem_ctl_dma_mem_wdata = io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[ifu.scala 107:26] - assign mem_ctl_io_dma_mem_ctl_dma_mem_tag = io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[ifu.scala 107:26] - assign mem_ctl_io_iccm_rd_data = io_iccm_rd_data; // @[ifu.scala 109:19] - assign mem_ctl_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[ifu.scala 109:19] - assign mem_ctl_io_ic_rd_data = io_ic_rd_data; // @[ifu.scala 108:17] - assign mem_ctl_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[ifu.scala 108:17] - assign mem_ctl_io_ic_tag_debug_rd_data = io_ic_tag_debug_rd_data; // @[ifu.scala 108:17] - assign mem_ctl_io_ic_eccerr = io_ic_eccerr; // @[ifu.scala 108:17] - assign mem_ctl_io_ic_rd_hit = io_ic_rd_hit; // @[ifu.scala 108:17] - assign mem_ctl_io_ic_tag_perr = io_ic_tag_perr; // @[ifu.scala 108:17] - assign mem_ctl_io_ifu_fetch_val = mem_ctl_io_ic_fetch_val_f; // @[ifu.scala 110:28] + assign mem_ctl_io_free_clk = io_free_clk; // @[ifu.scala 91:23] + assign mem_ctl_io_active_clk = io_active_clk; // @[ifu.scala 92:25] + assign mem_ctl_io_exu_flush_final = io_exu_flush_final; // @[ifu.scala 93:30] + assign mem_ctl_io_dec_mem_ctrl_dec_tlu_flush_err_wb = io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[ifu.scala 94:27] + assign mem_ctl_io_dec_mem_ctrl_dec_tlu_i0_commit_cmt = io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[ifu.scala 94:27] + assign mem_ctl_io_dec_mem_ctrl_dec_tlu_force_halt = io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[ifu.scala 94:27] + assign mem_ctl_io_dec_mem_ctrl_dec_tlu_fence_i_wb = io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[ifu.scala 94:27] + assign mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[ifu.scala 94:27] + assign mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[ifu.scala 94:27] + assign mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[ifu.scala 94:27] + assign mem_ctl_io_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[ifu.scala 94:27] + assign mem_ctl_io_dec_mem_ctrl_dec_tlu_core_ecc_disable = io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[ifu.scala 94:27] + assign mem_ctl_io_ifc_fetch_addr_bf = ifc_ctl_io_ifc_fetch_addr_bf; // @[ifu.scala 95:32] + assign mem_ctl_io_ifc_fetch_uncacheable_bf = ifc_ctl_io_ifc_fetch_uncacheable_bf; // @[ifu.scala 96:39] + assign mem_ctl_io_ifc_fetch_req_bf = ifc_ctl_io_ifc_fetch_req_bf; // @[ifu.scala 97:31] + assign mem_ctl_io_ifc_fetch_req_bf_raw = ifc_ctl_io_ifc_fetch_req_bf_raw; // @[ifu.scala 98:35] + assign mem_ctl_io_ifc_iccm_access_bf = ifc_ctl_io_ifc_iccm_access_bf; // @[ifu.scala 99:33] + assign mem_ctl_io_ifc_region_acc_fault_bf = ifc_ctl_io_ifc_region_acc_fault_bf; // @[ifu.scala 100:38] + assign mem_ctl_io_ifc_dma_access_ok = ifc_ctl_io_ifc_dma_access_ok; // @[ifu.scala 101:32] + assign mem_ctl_io_ifu_bp_hit_taken_f = bp_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 102:33] + assign mem_ctl_io_ifu_bp_inst_mask_f = bp_ctl_io_ifu_bp_inst_mask_f; // @[ifu.scala 103:33] + assign mem_ctl_io_ifu_axi_ar_ready = io_ifu_ar_ready; // @[ifu.scala 104:22] + assign mem_ctl_io_ifu_axi_r_valid = io_ifu_r_valid; // @[ifu.scala 104:22] + assign mem_ctl_io_ifu_axi_r_bits_id = io_ifu_r_bits_id; // @[ifu.scala 104:22] + assign mem_ctl_io_ifu_axi_r_bits_data = io_ifu_r_bits_data; // @[ifu.scala 104:22] + assign mem_ctl_io_ifu_axi_r_bits_resp = io_ifu_r_bits_resp; // @[ifu.scala 104:22] + assign mem_ctl_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[ifu.scala 105:29] + assign mem_ctl_io_dma_mem_ctl_dma_iccm_req = io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[ifu.scala 106:26] + assign mem_ctl_io_dma_mem_ctl_dma_mem_addr = io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[ifu.scala 106:26] + assign mem_ctl_io_dma_mem_ctl_dma_mem_sz = io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[ifu.scala 106:26] + assign mem_ctl_io_dma_mem_ctl_dma_mem_write = io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[ifu.scala 106:26] + assign mem_ctl_io_dma_mem_ctl_dma_mem_wdata = io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[ifu.scala 106:26] + assign mem_ctl_io_dma_mem_ctl_dma_mem_tag = io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[ifu.scala 106:26] + assign mem_ctl_io_iccm_rd_data = io_iccm_rd_data; // @[ifu.scala 108:19] + assign mem_ctl_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[ifu.scala 108:19] + assign mem_ctl_io_ic_rd_data = io_ic_rd_data; // @[ifu.scala 107:17] + assign mem_ctl_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[ifu.scala 107:17] + assign mem_ctl_io_ic_tag_debug_rd_data = io_ic_tag_debug_rd_data; // @[ifu.scala 107:17] + assign mem_ctl_io_ic_eccerr = io_ic_eccerr; // @[ifu.scala 107:17] + assign mem_ctl_io_ic_rd_hit = io_ic_rd_hit; // @[ifu.scala 107:17] + assign mem_ctl_io_ic_tag_perr = io_ic_tag_perr; // @[ifu.scala 107:17] + assign mem_ctl_io_ifu_fetch_val = mem_ctl_io_ic_fetch_val_f; // @[ifu.scala 109:28] + assign mem_ctl_io_dec_tlu_flush_lower_wb = io_dec_tlu_flush_lower_wb; // @[ifu.scala 110:37] assign mem_ctl_io_scan_mode = io_scan_mode; // @[ifu.scala 111:24] assign bp_ctl_clock = clock; assign bp_ctl_reset = reset; - assign bp_ctl_io_active_clk = io_active_clk; // @[ifu.scala 83:24] - assign bp_ctl_io_ic_hit_f = mem_ctl_io_ic_hit_f; // @[ifu.scala 84:22] - assign bp_ctl_io_exu_flush_final = io_exu_flush_final; // @[ifu.scala 89:29] - assign bp_ctl_io_ifc_fetch_addr_f = ifc_ctl_io_ifc_fetch_addr_f; // @[ifu.scala 85:30] - assign bp_ctl_io_ifc_fetch_req_f = ifc_ctl_io_ifc_fetch_req_f; // @[ifu.scala 86:29] - assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_valid = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[ifu.scala 87:20] - assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_hist = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[ifu.scala 87:20] - assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[ifu.scala 87:20] - assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[ifu.scala 87:20] - assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_way = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[ifu.scala 87:20] - assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_middle = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[ifu.scala 87:20] - assign bp_ctl_io_dec_bp_dec_tlu_flush_lower_wb = io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb; // @[ifu.scala 87:20] - assign bp_ctl_io_dec_bp_dec_tlu_flush_leak_one_wb = io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[ifu.scala 87:20] - assign bp_ctl_io_dec_bp_dec_tlu_bpred_disable = io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[ifu.scala 87:20] - assign bp_ctl_io_exu_bp_exu_i0_br_index_r = io_exu_ifu_exu_bp_exu_i0_br_index_r; // @[ifu.scala 88:20] - assign bp_ctl_io_exu_bp_exu_i0_br_fghr_r = io_exu_ifu_exu_bp_exu_i0_br_fghr_r; // @[ifu.scala 88:20] - assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_misp = io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp; // @[ifu.scala 88:20] - assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_ataken = io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken; // @[ifu.scala 88:20] - assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_boffset = io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset; // @[ifu.scala 88:20] - assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_pc4 = io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4; // @[ifu.scala 88:20] - assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_hist = io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist; // @[ifu.scala 88:20] - assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_toffset = io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset; // @[ifu.scala 88:20] - assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_pcall = io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall; // @[ifu.scala 88:20] - assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_pret = io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret; // @[ifu.scala 88:20] - assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_pja = io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja; // @[ifu.scala 88:20] - assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_way = io_exu_ifu_exu_bp_exu_mp_pkt_bits_way; // @[ifu.scala 88:20] - assign bp_ctl_io_exu_bp_exu_mp_eghr = io_exu_ifu_exu_bp_exu_mp_eghr; // @[ifu.scala 88:20] - assign bp_ctl_io_exu_bp_exu_mp_fghr = io_exu_ifu_exu_bp_exu_mp_fghr; // @[ifu.scala 88:20] - assign bp_ctl_io_exu_bp_exu_mp_index = io_exu_ifu_exu_bp_exu_mp_index; // @[ifu.scala 88:20] - assign bp_ctl_io_exu_bp_exu_mp_btag = io_exu_ifu_exu_bp_exu_mp_btag; // @[ifu.scala 88:20] - assign bp_ctl_io_scan_mode = io_scan_mode; // @[ifu.scala 82:23] + assign bp_ctl_io_active_clk = io_active_clk; // @[ifu.scala 82:24] + assign bp_ctl_io_ic_hit_f = mem_ctl_io_ic_hit_f; // @[ifu.scala 83:22] + assign bp_ctl_io_exu_flush_final = io_exu_flush_final; // @[ifu.scala 88:29] + assign bp_ctl_io_ifc_fetch_addr_f = ifc_ctl_io_ifc_fetch_addr_f; // @[ifu.scala 84:30] + assign bp_ctl_io_ifc_fetch_req_f = ifc_ctl_io_ifc_fetch_req_f; // @[ifu.scala 85:29] + assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_valid = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[ifu.scala 86:20] + assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_hist = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[ifu.scala 86:20] + assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[ifu.scala 86:20] + assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[ifu.scala 86:20] + assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_way = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[ifu.scala 86:20] + assign bp_ctl_io_dec_bp_dec_tlu_br0_r_pkt_bits_middle = io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[ifu.scala 86:20] + assign bp_ctl_io_dec_bp_dec_tlu_flush_leak_one_wb = io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[ifu.scala 86:20] + assign bp_ctl_io_dec_bp_dec_tlu_bpred_disable = io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[ifu.scala 86:20] + assign bp_ctl_io_dec_tlu_flush_lower_wb = io_dec_tlu_flush_lower_wb; // @[ifu.scala 89:36] + assign bp_ctl_io_exu_bp_exu_i0_br_index_r = io_exu_ifu_exu_bp_exu_i0_br_index_r; // @[ifu.scala 87:20] + assign bp_ctl_io_exu_bp_exu_i0_br_fghr_r = io_exu_ifu_exu_bp_exu_i0_br_fghr_r; // @[ifu.scala 87:20] + assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_misp = io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp; // @[ifu.scala 87:20] + assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_ataken = io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken; // @[ifu.scala 87:20] + assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_boffset = io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset; // @[ifu.scala 87:20] + assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_pc4 = io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4; // @[ifu.scala 87:20] + assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_hist = io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist; // @[ifu.scala 87:20] + assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_toffset = io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset; // @[ifu.scala 87:20] + assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_pcall = io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall; // @[ifu.scala 87:20] + assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_pret = io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret; // @[ifu.scala 87:20] + assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_pja = io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja; // @[ifu.scala 87:20] + assign bp_ctl_io_exu_bp_exu_mp_pkt_bits_way = io_exu_ifu_exu_bp_exu_mp_pkt_bits_way; // @[ifu.scala 87:20] + assign bp_ctl_io_exu_bp_exu_mp_eghr = io_exu_ifu_exu_bp_exu_mp_eghr; // @[ifu.scala 87:20] + assign bp_ctl_io_exu_bp_exu_mp_fghr = io_exu_ifu_exu_bp_exu_mp_fghr; // @[ifu.scala 87:20] + assign bp_ctl_io_exu_bp_exu_mp_index = io_exu_ifu_exu_bp_exu_mp_index; // @[ifu.scala 87:20] + assign bp_ctl_io_exu_bp_exu_mp_btag = io_exu_ifu_exu_bp_exu_mp_btag; // @[ifu.scala 87:20] + assign bp_ctl_io_scan_mode = io_scan_mode; // @[ifu.scala 81:23] assign aln_ctl_clock = clock; assign aln_ctl_reset = reset; - assign aln_ctl_io_scan_mode = io_scan_mode; // @[ifu.scala 60:24] - assign aln_ctl_io_active_clk = io_active_clk; // @[ifu.scala 61:25] - assign aln_ctl_io_ifu_async_error_start = mem_ctl_io_ifu_async_error_start; // @[ifu.scala 62:36] - assign aln_ctl_io_iccm_rd_ecc_double_err = mem_ctl_io_iccm_rd_ecc_double_err; // @[ifu.scala 63:37] - assign aln_ctl_io_ic_access_fault_f = mem_ctl_io_ic_access_fault_f; // @[ifu.scala 64:32] - assign aln_ctl_io_ic_access_fault_type_f = mem_ctl_io_ic_access_fault_type_f; // @[ifu.scala 65:37] - assign aln_ctl_io_ifu_bp_fghr_f = bp_ctl_io_ifu_bp_fghr_f; // @[ifu.scala 66:28] - assign aln_ctl_io_ifu_bp_btb_target_f = bp_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 67:34] - assign aln_ctl_io_ifu_bp_poffset_f = bp_ctl_io_ifu_bp_poffset_f; // @[ifu.scala 68:31] - assign aln_ctl_io_ifu_bp_hist0_f = bp_ctl_io_ifu_bp_hist0_f; // @[ifu.scala 69:29] - assign aln_ctl_io_ifu_bp_hist1_f = bp_ctl_io_ifu_bp_hist1_f; // @[ifu.scala 70:29] - assign aln_ctl_io_ifu_bp_pc4_f = bp_ctl_io_ifu_bp_pc4_f; // @[ifu.scala 71:27] - assign aln_ctl_io_ifu_bp_way_f = bp_ctl_io_ifu_bp_way_f; // @[ifu.scala 72:27] - assign aln_ctl_io_ifu_bp_valid_f = bp_ctl_io_ifu_bp_valid_f; // @[ifu.scala 73:29] - assign aln_ctl_io_ifu_bp_ret_f = bp_ctl_io_ifu_bp_ret_f; // @[ifu.scala 74:27] - assign aln_ctl_io_exu_flush_final = io_exu_flush_final; // @[ifu.scala 75:30] - assign aln_ctl_io_dec_aln_aln_dec_dec_i0_decode_d = io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[ifu.scala 76:22] - assign aln_ctl_io_ifu_fetch_data_f = mem_ctl_io_ic_data_f; // @[ifu.scala 77:31] - assign aln_ctl_io_ifu_fetch_val = mem_ctl_io_ifu_fetch_val; // @[ifu.scala 78:28] - assign aln_ctl_io_ifu_fetch_pc = ifc_ctl_io_ifc_fetch_addr_f; // @[ifu.scala 79:27] + assign aln_ctl_io_scan_mode = io_scan_mode; // @[ifu.scala 59:24] + assign aln_ctl_io_active_clk = io_active_clk; // @[ifu.scala 60:25] + assign aln_ctl_io_ifu_async_error_start = mem_ctl_io_ifu_async_error_start; // @[ifu.scala 61:36] + assign aln_ctl_io_iccm_rd_ecc_double_err = mem_ctl_io_iccm_rd_ecc_double_err; // @[ifu.scala 62:37] + assign aln_ctl_io_ic_access_fault_f = mem_ctl_io_ic_access_fault_f; // @[ifu.scala 63:32] + assign aln_ctl_io_ic_access_fault_type_f = mem_ctl_io_ic_access_fault_type_f; // @[ifu.scala 64:37] + assign aln_ctl_io_ifu_bp_fghr_f = bp_ctl_io_ifu_bp_fghr_f; // @[ifu.scala 65:28] + assign aln_ctl_io_ifu_bp_btb_target_f = bp_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 66:34] + assign aln_ctl_io_ifu_bp_poffset_f = bp_ctl_io_ifu_bp_poffset_f; // @[ifu.scala 67:31] + assign aln_ctl_io_ifu_bp_hist0_f = bp_ctl_io_ifu_bp_hist0_f; // @[ifu.scala 68:29] + assign aln_ctl_io_ifu_bp_hist1_f = bp_ctl_io_ifu_bp_hist1_f; // @[ifu.scala 69:29] + assign aln_ctl_io_ifu_bp_pc4_f = bp_ctl_io_ifu_bp_pc4_f; // @[ifu.scala 70:27] + assign aln_ctl_io_ifu_bp_way_f = bp_ctl_io_ifu_bp_way_f; // @[ifu.scala 71:27] + assign aln_ctl_io_ifu_bp_valid_f = bp_ctl_io_ifu_bp_valid_f; // @[ifu.scala 72:29] + assign aln_ctl_io_ifu_bp_ret_f = bp_ctl_io_ifu_bp_ret_f; // @[ifu.scala 73:27] + assign aln_ctl_io_exu_flush_final = io_exu_flush_final; // @[ifu.scala 74:30] + assign aln_ctl_io_dec_aln_aln_dec_dec_i0_decode_d = io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[ifu.scala 75:22] + assign aln_ctl_io_ifu_fetch_data_f = mem_ctl_io_ic_data_f; // @[ifu.scala 76:31] + assign aln_ctl_io_ifu_fetch_val = mem_ctl_io_ifu_fetch_val; // @[ifu.scala 77:28] + assign aln_ctl_io_ifu_fetch_pc = ifc_ctl_io_ifc_fetch_addr_f; // @[ifu.scala 78:27] assign ifc_ctl_clock = clock; assign ifc_ctl_reset = reset; - assign ifc_ctl_io_exu_flush_final = io_exu_flush_final; // @[ifu.scala 50:30] - assign ifc_ctl_io_exu_flush_path_final = io_exu_flush_path_final; // @[ifu.scala 57:35] - assign ifc_ctl_io_free_clk = io_free_clk; // @[ifu.scala 44:23] - assign ifc_ctl_io_active_clk = io_active_clk; // @[ifu.scala 43:25] - assign ifc_ctl_io_scan_mode = io_scan_mode; // @[ifu.scala 45:24] - assign ifc_ctl_io_ic_hit_f = mem_ctl_io_ic_hit_f; // @[ifu.scala 46:23] - assign ifc_ctl_io_ifu_ic_mb_empty = mem_ctl_io_ifu_ic_mb_empty; // @[ifu.scala 56:30] - assign ifc_ctl_io_ifu_fb_consume1 = aln_ctl_io_ifu_fb_consume1; // @[ifu.scala 47:30] - assign ifc_ctl_io_ifu_fb_consume2 = aln_ctl_io_ifu_fb_consume2; // @[ifu.scala 48:30] - assign ifc_ctl_io_ifu_bp_hit_taken_f = bp_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 51:33] - assign ifc_ctl_io_ifu_bp_btb_target_f = bp_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 52:34] - assign ifc_ctl_io_ic_dma_active = mem_ctl_io_ic_dma_active; // @[ifu.scala 53:28] - assign ifc_ctl_io_ic_write_stall = mem_ctl_io_ic_write_stall; // @[ifu.scala 54:29] - assign ifc_ctl_io_dec_ifc_dec_tlu_flush_noredir_wb = io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu.scala 49:22] - assign ifc_ctl_io_dec_ifc_dec_tlu_mrac_ff = io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[ifu.scala 49:22] - assign ifc_ctl_io_dma_ifc_dma_iccm_stall_any = io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[ifu.scala 55:22] + assign ifc_ctl_io_exu_flush_final = io_exu_flush_final; // @[ifu.scala 49:30] + assign ifc_ctl_io_exu_flush_path_final = io_exu_flush_path_final; // @[ifu.scala 56:35] + assign ifc_ctl_io_free_clk = io_free_clk; // @[ifu.scala 43:23] + assign ifc_ctl_io_active_clk = io_active_clk; // @[ifu.scala 42:25] + assign ifc_ctl_io_scan_mode = io_scan_mode; // @[ifu.scala 44:24] + assign ifc_ctl_io_ic_hit_f = mem_ctl_io_ic_hit_f; // @[ifu.scala 45:23] + assign ifc_ctl_io_ifu_ic_mb_empty = mem_ctl_io_ifu_ic_mb_empty; // @[ifu.scala 55:30] + assign ifc_ctl_io_ifu_fb_consume1 = aln_ctl_io_ifu_fb_consume1; // @[ifu.scala 46:30] + assign ifc_ctl_io_ifu_fb_consume2 = aln_ctl_io_ifu_fb_consume2; // @[ifu.scala 47:30] + assign ifc_ctl_io_ifu_bp_hit_taken_f = bp_ctl_io_ifu_bp_hit_taken_f; // @[ifu.scala 50:33] + assign ifc_ctl_io_ifu_bp_btb_target_f = bp_ctl_io_ifu_bp_btb_target_f; // @[ifu.scala 51:34] + assign ifc_ctl_io_ic_dma_active = mem_ctl_io_ic_dma_active; // @[ifu.scala 52:28] + assign ifc_ctl_io_ic_write_stall = mem_ctl_io_ic_write_stall; // @[ifu.scala 53:29] + assign ifc_ctl_io_dec_ifc_dec_tlu_flush_noredir_wb = io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu.scala 48:22] + assign ifc_ctl_io_dec_ifc_dec_tlu_mrac_ff = io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[ifu.scala 48:22] + assign ifc_ctl_io_dma_ifc_dma_iccm_stall_any = io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[ifu.scala 54:22] endmodule module dec_ib_ctl( input io_ifu_ib_ifu_i0_icaf, @@ -46049,6 +46048,7 @@ module dec_decode_ctl( input io_dctl_busbuff_lsu_nonblock_load_data_error, input [1:0] io_dctl_busbuff_lsu_nonblock_load_data_tag, input [31:0] io_dctl_busbuff_lsu_nonblock_load_data, + input io_dctl_dma_dma_dccm_stall_any, input io_dec_tlu_flush_extint, input io_dec_tlu_force_halt, output [31:0] io_dec_i0_inst_wb1, @@ -46079,7 +46079,6 @@ module dec_decode_ctl( input io_lsu_idle_any, input io_lsu_load_stall_any, input io_lsu_store_stall_any, - input io_dma_dccm_stall_any, input io_exu_div_wren, input io_dec_tlu_i0_kill_writeb_wb, input io_dec_tlu_flush_lower_wb, @@ -46906,9 +46905,9 @@ module dec_decode_ctl( wire i0_nonblock_div_stall = _T_827 | _T_830; // @[dec_decode_ctl.scala 708:113] wire _T_486 = _T_484 | i0_nonblock_div_stall; // @[dec_decode_ctl.scala 514:21] wire i0_block_raw_d = _T_486 | i0_div_prior_div_stall; // @[dec_decode_ctl.scala 514:45] - wire _T_487 = io_lsu_store_stall_any | io_dma_dccm_stall_any; // @[dec_decode_ctl.scala 516:65] + wire _T_487 = io_lsu_store_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 516:65] wire i0_store_stall_d = i0_dp_store & _T_487; // @[dec_decode_ctl.scala 516:39] - wire _T_488 = io_lsu_load_stall_any | io_dma_dccm_stall_any; // @[dec_decode_ctl.scala 517:63] + wire _T_488 = io_lsu_load_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 517:63] wire i0_load_stall_d = i0_dp_load & _T_488; // @[dec_decode_ctl.scala 517:38] wire _T_489 = i0_block_raw_d | i0_store_stall_d; // @[dec_decode_ctl.scala 518:38] wire i0_block_d = _T_489 | i0_load_stall_d; // @[dec_decode_ctl.scala 518:57] @@ -47098,9 +47097,9 @@ module dec_decode_ctl( wire [31:0] _T_987 = _T_984 | _T_985; // @[Mux.scala 27:72] wire _T_990 = i0_dp_raw_load | i0_dp_raw_store; // @[dec_decode_ctl.scala 787:68] wire _T_991 = io_dec_ib0_valid_d & _T_990; // @[dec_decode_ctl.scala 787:50] - wire _T_992 = ~io_dma_dccm_stall_any; // @[dec_decode_ctl.scala 787:89] + wire _T_992 = ~io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 787:89] wire _T_993 = _T_991 & _T_992; // @[dec_decode_ctl.scala 787:87] - wire _T_995 = _T_993 & _T_496; // @[dec_decode_ctl.scala 787:112] + wire _T_995 = _T_993 & _T_496; // @[dec_decode_ctl.scala 787:121] wire _T_997 = ~io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 789:6] wire _T_998 = _T_997 & i0_dp_lsu; // @[dec_decode_ctl.scala 789:38] wire _T_999 = _T_998 & i0_dp_load; // @[dec_decode_ctl.scala 789:50] @@ -50150,56 +50149,56 @@ module dec_timer_ctl( wire rvclkhdr_3_io_scan_mode; // @[lib.scala 352:23] reg [31:0] mitcnt0; // @[lib.scala 358:16] reg [31:0] mitb0_b; // @[lib.scala 358:16] - wire [31:0] mitb0 = ~mitb0_b; // @[dec_tlu_ctl.scala 2717:22] - wire mit0_match_ns = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2678:36] + wire [31:0] mitb0 = ~mitb0_b; // @[dec_tlu_ctl.scala 2713:22] + wire mit0_match_ns = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2674:36] reg [31:0] mitcnt1; // @[lib.scala 358:16] reg [31:0] mitb1_b; // @[lib.scala 358:16] - wire [31:0] mitb1 = ~mitb1_b; // @[dec_tlu_ctl.scala 2726:18] - wire mit1_match_ns = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2679:36] - wire _T = io_dec_csr_wraddr_r == 12'h7d2; // @[dec_tlu_ctl.scala 2689:72] - wire wr_mitcnt0_r = io_dec_csr_wen_r_mod & _T; // @[dec_tlu_ctl.scala 2689:49] - reg [1:0] _T_57; // @[dec_tlu_ctl.scala 2742:67] - reg mitctl0_0_b; // @[dec_tlu_ctl.scala 2741:60] - wire _T_58 = ~mitctl0_0_b; // @[dec_tlu_ctl.scala 2742:90] + wire [31:0] mitb1 = ~mitb1_b; // @[dec_tlu_ctl.scala 2722:18] + wire mit1_match_ns = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2675:36] + wire _T = io_dec_csr_wraddr_r == 12'h7d2; // @[dec_tlu_ctl.scala 2685:72] + wire wr_mitcnt0_r = io_dec_csr_wen_r_mod & _T; // @[dec_tlu_ctl.scala 2685:49] + reg [1:0] _T_57; // @[dec_tlu_ctl.scala 2738:67] + reg mitctl0_0_b; // @[dec_tlu_ctl.scala 2737:60] + wire _T_58 = ~mitctl0_0_b; // @[dec_tlu_ctl.scala 2738:90] wire [2:0] mitctl0 = {_T_57,_T_58}; // @[Cat.scala 29:58] - wire _T_2 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 2691:56] - wire _T_4 = _T_2 | mitctl0[2]; // @[dec_tlu_ctl.scala 2691:76] - wire _T_5 = mitctl0[0] & _T_4; // @[dec_tlu_ctl.scala 2691:53] - wire _T_6 = ~io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2691:112] - wire _T_8 = _T_6 | mitctl0[1]; // @[dec_tlu_ctl.scala 2691:138] - wire _T_9 = _T_5 & _T_8; // @[dec_tlu_ctl.scala 2691:109] - wire _T_10 = ~io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 2691:173] - wire mitcnt0_inc_ok = _T_9 & _T_10; // @[dec_tlu_ctl.scala 2691:171] - wire [31:0] mitcnt0_inc = mitcnt0 + 32'h1; // @[dec_tlu_ctl.scala 2692:35] - wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[dec_tlu_ctl.scala 2694:59] - wire _T_19 = io_dec_csr_wraddr_r == 12'h7d5; // @[dec_tlu_ctl.scala 2701:72] - wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_19; // @[dec_tlu_ctl.scala 2701:49] - reg [2:0] _T_66; // @[dec_tlu_ctl.scala 2756:52] - reg mitctl1_0_b; // @[dec_tlu_ctl.scala 2755:55] - wire _T_67 = ~mitctl1_0_b; // @[dec_tlu_ctl.scala 2756:75] + wire _T_2 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 2687:56] + wire _T_4 = _T_2 | mitctl0[2]; // @[dec_tlu_ctl.scala 2687:76] + wire _T_5 = mitctl0[0] & _T_4; // @[dec_tlu_ctl.scala 2687:53] + wire _T_6 = ~io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2687:112] + wire _T_8 = _T_6 | mitctl0[1]; // @[dec_tlu_ctl.scala 2687:138] + wire _T_9 = _T_5 & _T_8; // @[dec_tlu_ctl.scala 2687:109] + wire _T_10 = ~io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 2687:173] + wire mitcnt0_inc_ok = _T_9 & _T_10; // @[dec_tlu_ctl.scala 2687:171] + wire [31:0] mitcnt0_inc = mitcnt0 + 32'h1; // @[dec_tlu_ctl.scala 2688:35] + wire _T_15 = wr_mitcnt0_r | mitcnt0_inc_ok; // @[dec_tlu_ctl.scala 2690:59] + wire _T_19 = io_dec_csr_wraddr_r == 12'h7d5; // @[dec_tlu_ctl.scala 2697:72] + wire wr_mitcnt1_r = io_dec_csr_wen_r_mod & _T_19; // @[dec_tlu_ctl.scala 2697:49] + reg [2:0] _T_66; // @[dec_tlu_ctl.scala 2752:52] + reg mitctl1_0_b; // @[dec_tlu_ctl.scala 2751:55] + wire _T_67 = ~mitctl1_0_b; // @[dec_tlu_ctl.scala 2752:75] wire [3:0] mitctl1 = {_T_66,_T_67}; // @[Cat.scala 29:58] - wire _T_23 = _T_2 | mitctl1[2]; // @[dec_tlu_ctl.scala 2703:76] - wire _T_24 = mitctl1[0] & _T_23; // @[dec_tlu_ctl.scala 2703:53] - wire _T_27 = _T_6 | mitctl1[1]; // @[dec_tlu_ctl.scala 2703:138] - wire _T_28 = _T_24 & _T_27; // @[dec_tlu_ctl.scala 2703:109] - wire mitcnt1_inc_ok = _T_28 & _T_10; // @[dec_tlu_ctl.scala 2703:171] - wire _T_32 = ~mitctl1[3]; // @[dec_tlu_ctl.scala 2706:60] - wire _T_33 = _T_32 | mit0_match_ns; // @[dec_tlu_ctl.scala 2706:72] + wire _T_23 = _T_2 | mitctl1[2]; // @[dec_tlu_ctl.scala 2699:76] + wire _T_24 = mitctl1[0] & _T_23; // @[dec_tlu_ctl.scala 2699:53] + wire _T_27 = _T_6 | mitctl1[1]; // @[dec_tlu_ctl.scala 2699:138] + wire _T_28 = _T_24 & _T_27; // @[dec_tlu_ctl.scala 2699:109] + wire mitcnt1_inc_ok = _T_28 & _T_10; // @[dec_tlu_ctl.scala 2699:171] + wire _T_32 = ~mitctl1[3]; // @[dec_tlu_ctl.scala 2702:60] + wire _T_33 = _T_32 | mit0_match_ns; // @[dec_tlu_ctl.scala 2702:72] wire [31:0] _T_34 = {31'h0,_T_33}; // @[Cat.scala 29:58] - wire [31:0] mitcnt1_inc = mitcnt1 + _T_34; // @[dec_tlu_ctl.scala 2706:35] - wire _T_39 = wr_mitcnt1_r | mitcnt1_inc_ok; // @[dec_tlu_ctl.scala 2708:60] - wire _T_43 = io_dec_csr_wraddr_r == 12'h7d3; // @[dec_tlu_ctl.scala 2715:70] - wire _T_47 = io_dec_csr_wraddr_r == 12'h7d6; // @[dec_tlu_ctl.scala 2724:69] - wire _T_51 = io_dec_csr_wraddr_r == 12'h7d4; // @[dec_tlu_ctl.scala 2737:72] - wire wr_mitctl0_r = io_dec_csr_wen_r_mod & _T_51; // @[dec_tlu_ctl.scala 2737:49] - wire [2:0] mitctl0_ns = wr_mitctl0_r ? io_dec_csr_wrdata_r[2:0] : mitctl0; // @[dec_tlu_ctl.scala 2738:31] - wire _T_60 = io_dec_csr_wraddr_r == 12'h7d7; // @[dec_tlu_ctl.scala 2752:71] - wire wr_mitctl1_r = io_dec_csr_wen_r_mod & _T_60; // @[dec_tlu_ctl.scala 2752:49] - wire [3:0] mitctl1_ns = wr_mitctl1_r ? io_dec_csr_wrdata_r[3:0] : mitctl1; // @[dec_tlu_ctl.scala 2753:31] - wire _T_69 = io_csr_mitcnt1 | io_csr_mitcnt0; // @[dec_tlu_ctl.scala 2758:51] - wire _T_70 = _T_69 | io_csr_mitb1; // @[dec_tlu_ctl.scala 2758:68] - wire _T_71 = _T_70 | io_csr_mitb0; // @[dec_tlu_ctl.scala 2758:83] - wire _T_72 = _T_71 | io_csr_mitctl0; // @[dec_tlu_ctl.scala 2758:98] + wire [31:0] mitcnt1_inc = mitcnt1 + _T_34; // @[dec_tlu_ctl.scala 2702:35] + wire _T_39 = wr_mitcnt1_r | mitcnt1_inc_ok; // @[dec_tlu_ctl.scala 2704:60] + wire _T_43 = io_dec_csr_wraddr_r == 12'h7d3; // @[dec_tlu_ctl.scala 2711:70] + wire _T_47 = io_dec_csr_wraddr_r == 12'h7d6; // @[dec_tlu_ctl.scala 2720:69] + wire _T_51 = io_dec_csr_wraddr_r == 12'h7d4; // @[dec_tlu_ctl.scala 2733:72] + wire wr_mitctl0_r = io_dec_csr_wen_r_mod & _T_51; // @[dec_tlu_ctl.scala 2733:49] + wire [2:0] mitctl0_ns = wr_mitctl0_r ? io_dec_csr_wrdata_r[2:0] : mitctl0; // @[dec_tlu_ctl.scala 2734:31] + wire _T_60 = io_dec_csr_wraddr_r == 12'h7d7; // @[dec_tlu_ctl.scala 2748:71] + wire wr_mitctl1_r = io_dec_csr_wen_r_mod & _T_60; // @[dec_tlu_ctl.scala 2748:49] + wire [3:0] mitctl1_ns = wr_mitctl1_r ? io_dec_csr_wrdata_r[3:0] : mitctl1; // @[dec_tlu_ctl.scala 2749:31] + wire _T_69 = io_csr_mitcnt1 | io_csr_mitcnt0; // @[dec_tlu_ctl.scala 2754:51] + wire _T_70 = _T_69 | io_csr_mitb1; // @[dec_tlu_ctl.scala 2754:68] + wire _T_71 = _T_70 | io_csr_mitb0; // @[dec_tlu_ctl.scala 2754:83] + wire _T_72 = _T_71 | io_csr_mitctl0; // @[dec_tlu_ctl.scala 2754:98] wire [31:0] _T_81 = {29'h0,_T_57,_T_58}; // @[Cat.scala 29:58] wire [31:0] _T_84 = {28'h0,_T_66,_T_67}; // @[Cat.scala 29:58] wire [31:0] _T_85 = io_csr_mitcnt0 ? mitcnt0 : 32'h0; // @[Mux.scala 27:72] @@ -50236,10 +50235,10 @@ module dec_timer_ctl( .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - assign io_dec_timer_rddata_d = _T_94 | _T_90; // @[dec_tlu_ctl.scala 2759:33] - assign io_dec_timer_read_d = _T_72 | io_csr_mitctl1; // @[dec_tlu_ctl.scala 2758:33] - assign io_dec_timer_t0_pulse = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2681:31] - assign io_dec_timer_t1_pulse = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2682:31] + assign io_dec_timer_rddata_d = _T_94 | _T_90; // @[dec_tlu_ctl.scala 2755:33] + assign io_dec_timer_read_d = _T_72 | io_csr_mitctl1; // @[dec_tlu_ctl.scala 2754:33] + assign io_dec_timer_t0_pulse = mitcnt0 >= mitb0; // @[dec_tlu_ctl.scala 2677:31] + assign io_dec_timer_t1_pulse = mitcnt1 >= mitb1; // @[dec_tlu_ctl.scala 2678:31] assign rvclkhdr_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_io_en = _T_15 | mit0_match_ns; // @[lib.scala 355:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] @@ -50508,7 +50507,6 @@ module csr_tlu( input io_lsu_imprecise_error_load_any, input io_lsu_imprecise_error_store_any, output [31:0] io_dec_tlu_mrac_ff, - output io_dec_tlu_wb_coalescing_disable, output io_dec_tlu_bpred_disable, output io_dec_tlu_sideeffect_posted_disable, output io_dec_tlu_core_ecc_disable, @@ -50888,36 +50886,36 @@ module csr_tlu( wire rvclkhdr_34_io_clk; // @[lib.scala 327:22] wire rvclkhdr_34_io_en; // @[lib.scala 327:22] wire rvclkhdr_34_io_scan_mode; // @[lib.scala 327:22] - wire _T = ~io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 1455:45] - wire _T_1 = io_dec_csr_wen_r & _T; // @[dec_tlu_ctl.scala 1455:43] - wire _T_2 = ~io_rfpc_i0_r; // @[dec_tlu_ctl.scala 1455:68] - wire _T_5 = io_dec_csr_wraddr_r == 12'h300; // @[dec_tlu_ctl.scala 1456:71] - wire wr_mstatus_r = io_dec_csr_wen_r_mod & _T_5; // @[dec_tlu_ctl.scala 1456:42] - wire _T_488 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1842:68] - wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_488; // @[dec_tlu_ctl.scala 1842:39] - wire _T_500 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1850:37] - reg mpmc_b; // @[dec_tlu_ctl.scala 1852:44] - wire mpmc = ~mpmc_b; // @[dec_tlu_ctl.scala 1855:10] - wire _T_501 = ~mpmc; // @[dec_tlu_ctl.scala 1850:62] - wire mpmc_b_ns = wr_mpmc_r ? _T_500 : _T_501; // @[dec_tlu_ctl.scala 1850:18] - wire _T_6 = ~mpmc_b_ns; // @[dec_tlu_ctl.scala 1459:28] - wire set_mie_pmu_fw_halt = _T_6 & io_fw_halt_req; // @[dec_tlu_ctl.scala 1459:39] - wire _T_7 = ~wr_mstatus_r; // @[dec_tlu_ctl.scala 1462:5] - wire _T_8 = _T_7 & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1462:19] + wire _T = ~io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 1451:45] + wire _T_1 = io_dec_csr_wen_r & _T; // @[dec_tlu_ctl.scala 1451:43] + wire _T_2 = ~io_rfpc_i0_r; // @[dec_tlu_ctl.scala 1451:68] + wire _T_5 = io_dec_csr_wraddr_r == 12'h300; // @[dec_tlu_ctl.scala 1452:71] + wire wr_mstatus_r = io_dec_csr_wen_r_mod & _T_5; // @[dec_tlu_ctl.scala 1452:42] + wire _T_488 = io_dec_csr_wraddr_r == 12'h7c6; // @[dec_tlu_ctl.scala 1838:68] + wire wr_mpmc_r = io_dec_csr_wen_r_mod & _T_488; // @[dec_tlu_ctl.scala 1838:39] + wire _T_500 = ~io_dec_csr_wrdata_r[1]; // @[dec_tlu_ctl.scala 1846:37] + reg mpmc_b; // @[dec_tlu_ctl.scala 1848:44] + wire mpmc = ~mpmc_b; // @[dec_tlu_ctl.scala 1851:10] + wire _T_501 = ~mpmc; // @[dec_tlu_ctl.scala 1846:62] + wire mpmc_b_ns = wr_mpmc_r ? _T_500 : _T_501; // @[dec_tlu_ctl.scala 1846:18] + wire _T_6 = ~mpmc_b_ns; // @[dec_tlu_ctl.scala 1455:28] + wire set_mie_pmu_fw_halt = _T_6 & io_fw_halt_req; // @[dec_tlu_ctl.scala 1455:39] + wire _T_7 = ~wr_mstatus_r; // @[dec_tlu_ctl.scala 1458:5] + wire _T_8 = _T_7 & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1458:19] wire [1:0] _T_12 = {io_mstatus[0],1'h0}; // @[Cat.scala 29:58] - wire _T_13 = wr_mstatus_r & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1463:18] + wire _T_13 = wr_mstatus_r & io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1459:18] wire [1:0] _T_16 = {io_dec_csr_wrdata_r[3],1'h0}; // @[Cat.scala 29:58] - wire _T_17 = ~io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1464:17] - wire _T_18 = io_mret_r & _T_17; // @[dec_tlu_ctl.scala 1464:15] + wire _T_17 = ~io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 1460:17] + wire _T_18 = io_mret_r & _T_17; // @[dec_tlu_ctl.scala 1460:15] wire [1:0] _T_21 = {1'h1,io_mstatus[1]}; // @[Cat.scala 29:58] wire [1:0] _T_24 = {io_mstatus[1],1'h1}; // @[Cat.scala 29:58] - wire _T_26 = wr_mstatus_r & _T_17; // @[dec_tlu_ctl.scala 1466:18] + wire _T_26 = wr_mstatus_r & _T_17; // @[dec_tlu_ctl.scala 1462:18] wire [1:0] _T_30 = {io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58] - wire _T_33 = _T_7 & _T_17; // @[dec_tlu_ctl.scala 1467:19] - wire _T_34 = ~io_mret_r; // @[dec_tlu_ctl.scala 1467:46] - wire _T_35 = _T_33 & _T_34; // @[dec_tlu_ctl.scala 1467:44] - wire _T_36 = ~set_mie_pmu_fw_halt; // @[dec_tlu_ctl.scala 1467:59] - wire _T_37 = _T_35 & _T_36; // @[dec_tlu_ctl.scala 1467:57] + wire _T_33 = _T_7 & _T_17; // @[dec_tlu_ctl.scala 1463:19] + wire _T_34 = ~io_mret_r; // @[dec_tlu_ctl.scala 1463:46] + wire _T_35 = _T_33 & _T_34; // @[dec_tlu_ctl.scala 1463:44] + wire _T_36 = ~set_mie_pmu_fw_halt; // @[dec_tlu_ctl.scala 1463:59] + wire _T_37 = _T_35 & _T_36; // @[dec_tlu_ctl.scala 1463:57] wire [1:0] _T_39 = _T_8 ? _T_12 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_40 = _T_13 ? _T_16 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_41 = _T_18 ? _T_21 : 2'h0; // @[Mux.scala 27:72] @@ -50928,155 +50926,155 @@ module csr_tlu( wire [1:0] _T_46 = _T_45 | _T_41; // @[Mux.scala 27:72] wire [1:0] _T_47 = _T_46 | _T_42; // @[Mux.scala 27:72] wire [1:0] _T_48 = _T_47 | _T_43; // @[Mux.scala 27:72] - wire _T_52 = ~io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 1470:50] - wire _T_54 = _T_52 | io_dcsr[11]; // @[dec_tlu_ctl.scala 1470:81] - reg [1:0] _T_56; // @[dec_tlu_ctl.scala 1472:11] - wire _T_58 = io_dec_csr_wraddr_r == 12'h305; // @[dec_tlu_ctl.scala 1481:69] + wire _T_52 = ~io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 1466:50] + wire _T_54 = _T_52 | io_dcsr[11]; // @[dec_tlu_ctl.scala 1466:81] + reg [1:0] _T_56; // @[dec_tlu_ctl.scala 1468:11] + wire _T_58 = io_dec_csr_wraddr_r == 12'h305; // @[dec_tlu_ctl.scala 1477:69] reg [30:0] _T_62; // @[lib.scala 358:16] reg [31:0] mdccmect; // @[lib.scala 358:16] - wire [62:0] _T_564 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1902:41] + wire [62:0] _T_564 = 63'hffffffff << mdccmect[31:27]; // @[dec_tlu_ctl.scala 1898:41] wire [31:0] _T_566 = {5'h0,mdccmect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_9 = {{31'd0}, _T_566}; // @[dec_tlu_ctl.scala 1902:61] - wire [62:0] _T_567 = _T_564 & _GEN_9; // @[dec_tlu_ctl.scala 1902:61] - wire mdccme_ce_req = |_T_567; // @[dec_tlu_ctl.scala 1902:94] + wire [62:0] _GEN_9 = {{31'd0}, _T_566}; // @[dec_tlu_ctl.scala 1898:61] + wire [62:0] _T_567 = _T_564 & _GEN_9; // @[dec_tlu_ctl.scala 1898:61] + wire mdccme_ce_req = |_T_567; // @[dec_tlu_ctl.scala 1898:94] reg [31:0] miccmect; // @[lib.scala 358:16] - wire [62:0] _T_544 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1887:40] + wire [62:0] _T_544 = 63'hffffffff << miccmect[31:27]; // @[dec_tlu_ctl.scala 1883:40] wire [31:0] _T_546 = {5'h0,miccmect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_10 = {{31'd0}, _T_546}; // @[dec_tlu_ctl.scala 1887:60] - wire [62:0] _T_547 = _T_544 & _GEN_10; // @[dec_tlu_ctl.scala 1887:60] - wire miccme_ce_req = |_T_547; // @[dec_tlu_ctl.scala 1887:93] - wire _T_63 = mdccme_ce_req | miccme_ce_req; // @[dec_tlu_ctl.scala 1495:30] + wire [62:0] _GEN_10 = {{31'd0}, _T_546}; // @[dec_tlu_ctl.scala 1883:60] + wire [62:0] _T_547 = _T_544 & _GEN_10; // @[dec_tlu_ctl.scala 1883:60] + wire miccme_ce_req = |_T_547; // @[dec_tlu_ctl.scala 1883:93] + wire _T_63 = mdccme_ce_req | miccme_ce_req; // @[dec_tlu_ctl.scala 1491:30] reg [31:0] micect; // @[lib.scala 358:16] - wire [62:0] _T_522 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1872:39] + wire [62:0] _T_522 = 63'hffffffff << micect[31:27]; // @[dec_tlu_ctl.scala 1868:39] wire [31:0] _T_524 = {5'h0,micect[26:0]}; // @[Cat.scala 29:58] - wire [62:0] _GEN_11 = {{31'd0}, _T_524}; // @[dec_tlu_ctl.scala 1872:57] - wire [62:0] _T_525 = _T_522 & _GEN_11; // @[dec_tlu_ctl.scala 1872:57] - wire mice_ce_req = |_T_525; // @[dec_tlu_ctl.scala 1872:88] - wire ce_int = _T_63 | mice_ce_req; // @[dec_tlu_ctl.scala 1495:46] + wire [62:0] _GEN_11 = {{31'd0}, _T_524}; // @[dec_tlu_ctl.scala 1868:57] + wire [62:0] _T_525 = _T_522 & _GEN_11; // @[dec_tlu_ctl.scala 1868:57] + wire mice_ce_req = |_T_525; // @[dec_tlu_ctl.scala 1868:88] + wire ce_int = _T_63 | mice_ce_req; // @[dec_tlu_ctl.scala 1491:46] wire [2:0] _T_65 = {io_mexintpend,io_timer_int_sync,io_soft_int_sync}; // @[Cat.scala 29:58] wire [2:0] _T_67 = {ce_int,io_dec_timer_t0_pulse,io_dec_timer_t1_pulse}; // @[Cat.scala 29:58] - reg [5:0] _T_68; // @[dec_tlu_ctl.scala 1499:11] - wire _T_70 = io_dec_csr_wraddr_r == 12'h304; // @[dec_tlu_ctl.scala 1511:67] - wire wr_mie_r = io_dec_csr_wen_r_mod & _T_70; // @[dec_tlu_ctl.scala 1511:38] + reg [5:0] _T_68; // @[dec_tlu_ctl.scala 1495:11] + wire _T_70 = io_dec_csr_wraddr_r == 12'h304; // @[dec_tlu_ctl.scala 1507:67] + wire wr_mie_r = io_dec_csr_wen_r_mod & _T_70; // @[dec_tlu_ctl.scala 1507:38] wire [5:0] _T_78 = {io_dec_csr_wrdata_r[30:28],io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7],io_dec_csr_wrdata_r[3]}; // @[Cat.scala 29:58] - reg [5:0] mie; // @[dec_tlu_ctl.scala 1514:11] - wire kill_ebreak_count_r = io_ebreak_to_debug_mode_r & io_dcsr[10]; // @[dec_tlu_ctl.scala 1521:54] - wire _T_83 = io_dec_csr_wraddr_r == 12'hb00; // @[dec_tlu_ctl.scala 1523:71] - wire wr_mcyclel_r = io_dec_csr_wen_r_mod & _T_83; // @[dec_tlu_ctl.scala 1523:42] - wire _T_85 = io_dec_tlu_dbg_halted & io_dcsr[10]; // @[dec_tlu_ctl.scala 1525:71] - wire _T_86 = kill_ebreak_count_r | _T_85; // @[dec_tlu_ctl.scala 1525:46] - wire _T_87 = _T_86 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 1525:94] + reg [5:0] mie; // @[dec_tlu_ctl.scala 1510:11] + wire kill_ebreak_count_r = io_ebreak_to_debug_mode_r & io_dcsr[10]; // @[dec_tlu_ctl.scala 1517:54] + wire _T_83 = io_dec_csr_wraddr_r == 12'hb00; // @[dec_tlu_ctl.scala 1519:71] + wire wr_mcyclel_r = io_dec_csr_wen_r_mod & _T_83; // @[dec_tlu_ctl.scala 1519:42] + wire _T_85 = io_dec_tlu_dbg_halted & io_dcsr[10]; // @[dec_tlu_ctl.scala 1521:71] + wire _T_86 = kill_ebreak_count_r | _T_85; // @[dec_tlu_ctl.scala 1521:46] + wire _T_87 = _T_86 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 1521:94] reg [4:0] temp_ncount6_2; // @[Reg.scala 27:20] reg temp_ncount0; // @[Reg.scala 27:20] wire [6:0] mcountinhibit = {temp_ncount6_2,1'h0,temp_ncount0}; // @[Cat.scala 29:58] - wire _T_89 = _T_87 | mcountinhibit[0]; // @[dec_tlu_ctl.scala 1525:121] - wire mcyclel_cout_in = ~_T_89; // @[dec_tlu_ctl.scala 1525:24] + wire _T_89 = _T_87 | mcountinhibit[0]; // @[dec_tlu_ctl.scala 1521:121] + wire mcyclel_cout_in = ~_T_89; // @[dec_tlu_ctl.scala 1521:24] wire [31:0] _T_90 = {31'h0,mcyclel_cout_in}; // @[Cat.scala 29:58] reg [31:0] mcyclel; // @[lib.scala 358:16] - wire [32:0] mcyclel_inc = mcyclel + _T_90; // @[dec_tlu_ctl.scala 1529:25] - wire mcyclel_cout = mcyclel_inc[32]; // @[dec_tlu_ctl.scala 1531:32] - wire _T_101 = io_dec_csr_wraddr_r == 12'hb80; // @[dec_tlu_ctl.scala 1539:68] - wire wr_mcycleh_r = io_dec_csr_wen_r_mod & _T_101; // @[dec_tlu_ctl.scala 1539:39] - wire _T_98 = ~wr_mcycleh_r; // @[dec_tlu_ctl.scala 1533:71] - reg mcyclel_cout_f; // @[dec_tlu_ctl.scala 1533:54] + wire [32:0] mcyclel_inc = mcyclel + _T_90; // @[dec_tlu_ctl.scala 1525:25] + wire mcyclel_cout = mcyclel_inc[32]; // @[dec_tlu_ctl.scala 1527:32] + wire _T_101 = io_dec_csr_wraddr_r == 12'hb80; // @[dec_tlu_ctl.scala 1535:68] + wire wr_mcycleh_r = io_dec_csr_wen_r_mod & _T_101; // @[dec_tlu_ctl.scala 1535:39] + wire _T_98 = ~wr_mcycleh_r; // @[dec_tlu_ctl.scala 1529:71] + reg mcyclel_cout_f; // @[dec_tlu_ctl.scala 1529:54] wire [31:0] _T_103 = {31'h0,mcyclel_cout_f}; // @[Cat.scala 29:58] reg [31:0] mcycleh; // @[lib.scala 358:16] - wire [31:0] mcycleh_inc = mcycleh + _T_103; // @[dec_tlu_ctl.scala 1541:28] - wire _T_109 = io_ebreak_r | io_ecall_r; // @[dec_tlu_ctl.scala 1558:72] - wire _T_110 = _T_109 | io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 1558:85] - wire _T_111 = _T_110 | io_illegal_r; // @[dec_tlu_ctl.scala 1558:113] - wire _T_113 = _T_111 | mcountinhibit[2]; // @[dec_tlu_ctl.scala 1558:128] - wire _T_115 = ~_T_113; // @[dec_tlu_ctl.scala 1558:58] - wire i0_valid_no_ebreak_ecall_r = io_tlu_i0_commit_cmt & _T_115; // @[dec_tlu_ctl.scala 1558:56] - wire _T_117 = io_dec_csr_wraddr_r == 12'hb02; // @[dec_tlu_ctl.scala 1560:73] - wire wr_minstretl_r = io_dec_csr_wen_r_mod & _T_117; // @[dec_tlu_ctl.scala 1560:44] + wire [31:0] mcycleh_inc = mcycleh + _T_103; // @[dec_tlu_ctl.scala 1537:28] + wire _T_109 = io_ebreak_r | io_ecall_r; // @[dec_tlu_ctl.scala 1554:72] + wire _T_110 = _T_109 | io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 1554:85] + wire _T_111 = _T_110 | io_illegal_r; // @[dec_tlu_ctl.scala 1554:113] + wire _T_113 = _T_111 | mcountinhibit[2]; // @[dec_tlu_ctl.scala 1554:128] + wire _T_115 = ~_T_113; // @[dec_tlu_ctl.scala 1554:58] + wire i0_valid_no_ebreak_ecall_r = io_tlu_i0_commit_cmt & _T_115; // @[dec_tlu_ctl.scala 1554:56] + wire _T_117 = io_dec_csr_wraddr_r == 12'hb02; // @[dec_tlu_ctl.scala 1556:73] + wire wr_minstretl_r = io_dec_csr_wen_r_mod & _T_117; // @[dec_tlu_ctl.scala 1556:44] wire [31:0] _T_118 = {31'h0,i0_valid_no_ebreak_ecall_r}; // @[Cat.scala 29:58] reg [31:0] minstretl; // @[lib.scala 358:16] - wire [32:0] minstretl_inc = minstretl + _T_118; // @[dec_tlu_ctl.scala 1562:29] - wire minstretl_cout = minstretl_inc[32]; // @[dec_tlu_ctl.scala 1563:36] - reg minstret_enable_f; // @[dec_tlu_ctl.scala 1568:56] - wire _T_128 = io_dec_csr_wraddr_r == 12'hb82; // @[dec_tlu_ctl.scala 1577:71] - wire wr_minstreth_r = io_dec_csr_wen_r_mod & _T_128; // @[dec_tlu_ctl.scala 1577:42] - wire _T_125 = ~wr_minstreth_r; // @[dec_tlu_ctl.scala 1569:75] - reg minstretl_cout_f; // @[dec_tlu_ctl.scala 1569:56] + wire [32:0] minstretl_inc = minstretl + _T_118; // @[dec_tlu_ctl.scala 1558:29] + wire minstretl_cout = minstretl_inc[32]; // @[dec_tlu_ctl.scala 1559:36] + reg minstret_enable_f; // @[dec_tlu_ctl.scala 1564:56] + wire _T_128 = io_dec_csr_wraddr_r == 12'hb82; // @[dec_tlu_ctl.scala 1573:71] + wire wr_minstreth_r = io_dec_csr_wen_r_mod & _T_128; // @[dec_tlu_ctl.scala 1573:42] + wire _T_125 = ~wr_minstreth_r; // @[dec_tlu_ctl.scala 1565:75] + reg minstretl_cout_f; // @[dec_tlu_ctl.scala 1565:56] wire [31:0] _T_131 = {31'h0,minstretl_cout_f}; // @[Cat.scala 29:58] reg [31:0] minstreth; // @[lib.scala 358:16] - wire [31:0] minstreth_inc = minstreth + _T_131; // @[dec_tlu_ctl.scala 1580:29] - wire _T_139 = io_dec_csr_wraddr_r == 12'h340; // @[dec_tlu_ctl.scala 1591:72] + wire [31:0] minstreth_inc = minstreth + _T_131; // @[dec_tlu_ctl.scala 1576:29] + wire _T_139 = io_dec_csr_wraddr_r == 12'h340; // @[dec_tlu_ctl.scala 1587:72] reg [31:0] mscratch; // @[lib.scala 358:16] - wire _T_142 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 1602:22] - wire _T_143 = ~io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1602:47] - wire _T_144 = _T_142 & _T_143; // @[dec_tlu_ctl.scala 1602:45] - wire sel_exu_npc_r = _T_144 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1602:72] - wire _T_146 = _T_142 & io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1603:47] - wire _T_147 = ~io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 1603:75] - wire sel_flush_npc_r = _T_146 & _T_147; // @[dec_tlu_ctl.scala 1603:73] - wire _T_148 = ~sel_exu_npc_r; // @[dec_tlu_ctl.scala 1604:23] - wire _T_149 = ~sel_flush_npc_r; // @[dec_tlu_ctl.scala 1604:40] - wire sel_hold_npc_r = _T_148 & _T_149; // @[dec_tlu_ctl.scala 1604:38] - wire _T_151 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 1608:13] - wire _T_152 = _T_151 & io_reset_delayed; // @[dec_tlu_ctl.scala 1608:35] + wire _T_142 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 1598:22] + wire _T_143 = ~io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1598:47] + wire _T_144 = _T_142 & _T_143; // @[dec_tlu_ctl.scala 1598:45] + wire sel_exu_npc_r = _T_144 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1598:72] + wire _T_146 = _T_142 & io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 1599:47] + wire _T_147 = ~io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 1599:75] + wire sel_flush_npc_r = _T_146 & _T_147; // @[dec_tlu_ctl.scala 1599:73] + wire _T_148 = ~sel_exu_npc_r; // @[dec_tlu_ctl.scala 1600:23] + wire _T_149 = ~sel_flush_npc_r; // @[dec_tlu_ctl.scala 1600:40] + wire sel_hold_npc_r = _T_148 & _T_149; // @[dec_tlu_ctl.scala 1600:38] + wire _T_151 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 1604:13] + wire _T_152 = _T_151 & io_reset_delayed; // @[dec_tlu_ctl.scala 1604:35] wire [30:0] _T_156 = sel_exu_npc_r ? io_exu_npc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_157 = _T_152 ? io_rst_vec : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_158 = sel_flush_npc_r ? io_tlu_flush_path_r_d1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_159 = sel_hold_npc_r ? io_npc_r_d1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_160 = _T_156 | _T_157; // @[Mux.scala 27:72] wire [30:0] _T_161 = _T_160 | _T_158; // @[Mux.scala 27:72] - wire _T_164 = sel_exu_npc_r | sel_flush_npc_r; // @[dec_tlu_ctl.scala 1612:48] + wire _T_164 = sel_exu_npc_r | sel_flush_npc_r; // @[dec_tlu_ctl.scala 1608:48] reg [30:0] _T_167; // @[lib.scala 358:16] - wire pc0_valid_r = _T_142 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1615:44] - wire _T_170 = ~pc0_valid_r; // @[dec_tlu_ctl.scala 1619:22] + wire pc0_valid_r = _T_142 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 1611:44] + wire _T_170 = ~pc0_valid_r; // @[dec_tlu_ctl.scala 1615:22] wire [30:0] _T_171 = pc0_valid_r ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] reg [30:0] pc_r_d1; // @[lib.scala 358:16] wire [30:0] _T_172 = _T_170 ? pc_r_d1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] pc_r = _T_171 | _T_172; // @[Mux.scala 27:72] - wire _T_176 = io_dec_csr_wraddr_r == 12'h341; // @[dec_tlu_ctl.scala 1623:68] - wire wr_mepc_r = io_dec_csr_wen_r_mod & _T_176; // @[dec_tlu_ctl.scala 1623:39] - wire _T_177 = io_i0_exception_valid_r | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1626:27] - wire _T_178 = _T_177 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1626:48] - wire _T_182 = wr_mepc_r & _T_17; // @[dec_tlu_ctl.scala 1628:13] - wire _T_185 = ~wr_mepc_r; // @[dec_tlu_ctl.scala 1629:3] - wire _T_187 = _T_185 & _T_17; // @[dec_tlu_ctl.scala 1629:14] + wire _T_176 = io_dec_csr_wraddr_r == 12'h341; // @[dec_tlu_ctl.scala 1619:68] + wire wr_mepc_r = io_dec_csr_wen_r_mod & _T_176; // @[dec_tlu_ctl.scala 1619:39] + wire _T_177 = io_i0_exception_valid_r | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1622:27] + wire _T_178 = _T_177 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1622:48] + wire _T_182 = wr_mepc_r & _T_17; // @[dec_tlu_ctl.scala 1624:13] + wire _T_185 = ~wr_mepc_r; // @[dec_tlu_ctl.scala 1625:3] + wire _T_187 = _T_185 & _T_17; // @[dec_tlu_ctl.scala 1625:14] wire [30:0] _T_189 = _T_178 ? pc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_190 = io_interrupt_valid_r ? io_npc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_191 = _T_182 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_192 = _T_187 ? io_mepc : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_193 = _T_189 | _T_190; // @[Mux.scala 27:72] wire [30:0] _T_194 = _T_193 | _T_191; // @[Mux.scala 27:72] - reg [30:0] _T_196; // @[dec_tlu_ctl.scala 1631:47] - wire _T_198 = io_dec_csr_wraddr_r == 12'h342; // @[dec_tlu_ctl.scala 1638:72] - wire wr_mcause_r = io_dec_csr_wen_r_mod & _T_198; // @[dec_tlu_ctl.scala 1638:43] - wire _T_199 = io_exc_or_int_valid_r & io_take_nmi; // @[dec_tlu_ctl.scala 1639:53] - wire mcause_sel_nmi_store = _T_199 & io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 1639:67] - wire mcause_sel_nmi_load = _T_199 & io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 1640:66] - wire _T_202 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 1641:84] - wire mcause_sel_nmi_ext = _T_199 & _T_202; // @[dec_tlu_ctl.scala 1641:65] - wire _T_203 = &io_lsu_fir_error; // @[dec_tlu_ctl.scala 1647:53] - wire _T_206 = ~io_lsu_fir_error[0]; // @[dec_tlu_ctl.scala 1647:82] - wire _T_207 = io_lsu_fir_error[1] & _T_206; // @[dec_tlu_ctl.scala 1647:80] + reg [30:0] _T_196; // @[dec_tlu_ctl.scala 1627:47] + wire _T_198 = io_dec_csr_wraddr_r == 12'h342; // @[dec_tlu_ctl.scala 1634:72] + wire wr_mcause_r = io_dec_csr_wen_r_mod & _T_198; // @[dec_tlu_ctl.scala 1634:43] + wire _T_199 = io_exc_or_int_valid_r & io_take_nmi; // @[dec_tlu_ctl.scala 1635:53] + wire mcause_sel_nmi_store = _T_199 & io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 1635:67] + wire mcause_sel_nmi_load = _T_199 & io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 1636:66] + wire _T_202 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 1637:84] + wire mcause_sel_nmi_ext = _T_199 & _T_202; // @[dec_tlu_ctl.scala 1637:65] + wire _T_203 = &io_lsu_fir_error; // @[dec_tlu_ctl.scala 1643:53] + wire _T_206 = ~io_lsu_fir_error[0]; // @[dec_tlu_ctl.scala 1643:82] + wire _T_207 = io_lsu_fir_error[1] & _T_206; // @[dec_tlu_ctl.scala 1643:80] wire [31:0] _T_212 = {30'h3c000400,_T_203,_T_207}; // @[Cat.scala 29:58] - wire _T_213 = ~io_take_nmi; // @[dec_tlu_ctl.scala 1653:56] - wire _T_214 = io_exc_or_int_valid_r & _T_213; // @[dec_tlu_ctl.scala 1653:54] + wire _T_213 = ~io_take_nmi; // @[dec_tlu_ctl.scala 1649:56] + wire _T_214 = io_exc_or_int_valid_r & _T_213; // @[dec_tlu_ctl.scala 1649:54] wire [31:0] _T_217 = {io_interrupt_valid_r,26'h0,io_exc_cause_r}; // @[Cat.scala 29:58] - wire _T_219 = wr_mcause_r & _T_17; // @[dec_tlu_ctl.scala 1654:44] - wire _T_221 = ~wr_mcause_r; // @[dec_tlu_ctl.scala 1655:32] - wire _T_223 = _T_221 & _T_17; // @[dec_tlu_ctl.scala 1655:45] + wire _T_219 = wr_mcause_r & _T_17; // @[dec_tlu_ctl.scala 1650:44] + wire _T_221 = ~wr_mcause_r; // @[dec_tlu_ctl.scala 1651:32] + wire _T_223 = _T_221 & _T_17; // @[dec_tlu_ctl.scala 1651:45] wire [31:0] _T_225 = mcause_sel_nmi_store ? 32'hf0000000 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_226 = mcause_sel_nmi_load ? 32'hf0000001 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_227 = mcause_sel_nmi_ext ? _T_212 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_228 = _T_214 ? _T_217 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_229 = _T_219 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72] - reg [31:0] mcause; // @[dec_tlu_ctl.scala 1657:49] + reg [31:0] mcause; // @[dec_tlu_ctl.scala 1653:49] wire [31:0] _T_230 = _T_223 ? mcause : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_231 = _T_225 | _T_226; // @[Mux.scala 27:72] wire [31:0] _T_232 = _T_231 | _T_227; // @[Mux.scala 27:72] wire [31:0] _T_233 = _T_232 | _T_228; // @[Mux.scala 27:72] wire [31:0] _T_234 = _T_233 | _T_229; // @[Mux.scala 27:72] - wire _T_238 = io_dec_csr_wraddr_r == 12'h7ff; // @[dec_tlu_ctl.scala 1664:71] - wire wr_mscause_r = io_dec_csr_wen_r_mod & _T_238; // @[dec_tlu_ctl.scala 1664:42] - wire _T_239 = io_dec_tlu_packet_r_icaf_type == 2'h0; // @[dec_tlu_ctl.scala 1666:56] + wire _T_238 = io_dec_csr_wraddr_r == 12'h7ff; // @[dec_tlu_ctl.scala 1660:71] + wire wr_mscause_r = io_dec_csr_wen_r_mod & _T_238; // @[dec_tlu_ctl.scala 1660:42] + wire _T_239 = io_dec_tlu_packet_r_icaf_type == 2'h0; // @[dec_tlu_ctl.scala 1662:56] wire [3:0] _T_240 = {2'h0,io_dec_tlu_packet_r_icaf_type}; // @[Cat.scala 29:58] - wire [3:0] ifu_mscause = _T_239 ? 4'h9 : _T_240; // @[dec_tlu_ctl.scala 1666:24] + wire [3:0] ifu_mscause = _T_239 ? 4'h9 : _T_240; // @[dec_tlu_ctl.scala 1662:24] wire [3:0] _T_245 = io_lsu_i0_exc_r ? io_lsu_error_pkt_r_bits_mscause : 4'h0; // @[Mux.scala 27:72] wire [1:0] _T_247 = io_ebreak_r ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [3:0] _T_248 = io_inst_acc_r ? ifu_mscause : 4'h0; // @[Mux.scala 27:72] @@ -51085,189 +51083,189 @@ module csr_tlu( wire [3:0] _GEN_13 = {{2'd0}, _T_247}; // @[Mux.scala 27:72] wire [3:0] _T_250 = _T_249 | _GEN_13; // @[Mux.scala 27:72] wire [3:0] mscause_type = _T_250 | _T_248; // @[Mux.scala 27:72] - wire _T_254 = wr_mscause_r & _T_17; // @[dec_tlu_ctl.scala 1677:38] - wire _T_257 = ~wr_mscause_r; // @[dec_tlu_ctl.scala 1678:25] - wire _T_259 = _T_257 & _T_17; // @[dec_tlu_ctl.scala 1678:39] + wire _T_254 = wr_mscause_r & _T_17; // @[dec_tlu_ctl.scala 1673:38] + wire _T_257 = ~wr_mscause_r; // @[dec_tlu_ctl.scala 1674:25] + wire _T_259 = _T_257 & _T_17; // @[dec_tlu_ctl.scala 1674:39] wire [3:0] _T_261 = io_exc_or_int_valid_r ? mscause_type : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_262 = _T_254 ? io_dec_csr_wrdata_r[3:0] : 4'h0; // @[Mux.scala 27:72] - reg [3:0] mscause; // @[dec_tlu_ctl.scala 1680:47] + reg [3:0] mscause; // @[dec_tlu_ctl.scala 1676:47] wire [3:0] _T_263 = _T_259 ? mscause : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_264 = _T_261 | _T_262; // @[Mux.scala 27:72] - wire _T_268 = io_dec_csr_wraddr_r == 12'h343; // @[dec_tlu_ctl.scala 1687:69] - wire wr_mtval_r = io_dec_csr_wen_r_mod & _T_268; // @[dec_tlu_ctl.scala 1687:40] - wire _T_269 = ~io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1688:83] - wire _T_270 = io_inst_acc_r & _T_269; // @[dec_tlu_ctl.scala 1688:81] - wire _T_271 = io_ebreak_r | _T_270; // @[dec_tlu_ctl.scala 1688:64] - wire _T_272 = _T_271 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1688:106] - wire _T_273 = io_exc_or_int_valid_r & _T_272; // @[dec_tlu_ctl.scala 1688:49] - wire mtval_capture_pc_r = _T_273 & _T_213; // @[dec_tlu_ctl.scala 1688:138] - wire _T_275 = io_inst_acc_r & io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1689:72] - wire _T_276 = io_exc_or_int_valid_r & _T_275; // @[dec_tlu_ctl.scala 1689:55] - wire mtval_capture_pc_plus2_r = _T_276 & _T_213; // @[dec_tlu_ctl.scala 1689:96] - wire _T_278 = io_exc_or_int_valid_r & io_illegal_r; // @[dec_tlu_ctl.scala 1690:51] - wire mtval_capture_inst_r = _T_278 & _T_213; // @[dec_tlu_ctl.scala 1690:66] - wire _T_280 = io_exc_or_int_valid_r & io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1691:50] - wire mtval_capture_lsu_r = _T_280 & _T_213; // @[dec_tlu_ctl.scala 1691:71] - wire _T_282 = ~mtval_capture_pc_r; // @[dec_tlu_ctl.scala 1692:46] - wire _T_283 = io_exc_or_int_valid_r & _T_282; // @[dec_tlu_ctl.scala 1692:44] - wire _T_284 = ~mtval_capture_inst_r; // @[dec_tlu_ctl.scala 1692:68] - wire _T_285 = _T_283 & _T_284; // @[dec_tlu_ctl.scala 1692:66] - wire _T_286 = ~mtval_capture_lsu_r; // @[dec_tlu_ctl.scala 1692:92] - wire _T_287 = _T_285 & _T_286; // @[dec_tlu_ctl.scala 1692:90] - wire _T_288 = ~io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1692:115] - wire mtval_clear_r = _T_287 & _T_288; // @[dec_tlu_ctl.scala 1692:113] + wire _T_268 = io_dec_csr_wraddr_r == 12'h343; // @[dec_tlu_ctl.scala 1683:69] + wire wr_mtval_r = io_dec_csr_wen_r_mod & _T_268; // @[dec_tlu_ctl.scala 1683:40] + wire _T_269 = ~io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1684:83] + wire _T_270 = io_inst_acc_r & _T_269; // @[dec_tlu_ctl.scala 1684:81] + wire _T_271 = io_ebreak_r | _T_270; // @[dec_tlu_ctl.scala 1684:64] + wire _T_272 = _T_271 | io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1684:106] + wire _T_273 = io_exc_or_int_valid_r & _T_272; // @[dec_tlu_ctl.scala 1684:49] + wire mtval_capture_pc_r = _T_273 & _T_213; // @[dec_tlu_ctl.scala 1684:138] + wire _T_275 = io_inst_acc_r & io_inst_acc_second_r; // @[dec_tlu_ctl.scala 1685:72] + wire _T_276 = io_exc_or_int_valid_r & _T_275; // @[dec_tlu_ctl.scala 1685:55] + wire mtval_capture_pc_plus2_r = _T_276 & _T_213; // @[dec_tlu_ctl.scala 1685:96] + wire _T_278 = io_exc_or_int_valid_r & io_illegal_r; // @[dec_tlu_ctl.scala 1686:51] + wire mtval_capture_inst_r = _T_278 & _T_213; // @[dec_tlu_ctl.scala 1686:66] + wire _T_280 = io_exc_or_int_valid_r & io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 1687:50] + wire mtval_capture_lsu_r = _T_280 & _T_213; // @[dec_tlu_ctl.scala 1687:71] + wire _T_282 = ~mtval_capture_pc_r; // @[dec_tlu_ctl.scala 1688:46] + wire _T_283 = io_exc_or_int_valid_r & _T_282; // @[dec_tlu_ctl.scala 1688:44] + wire _T_284 = ~mtval_capture_inst_r; // @[dec_tlu_ctl.scala 1688:68] + wire _T_285 = _T_283 & _T_284; // @[dec_tlu_ctl.scala 1688:66] + wire _T_286 = ~mtval_capture_lsu_r; // @[dec_tlu_ctl.scala 1688:92] + wire _T_287 = _T_285 & _T_286; // @[dec_tlu_ctl.scala 1688:90] + wire _T_288 = ~io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 1688:115] + wire mtval_clear_r = _T_287 & _T_288; // @[dec_tlu_ctl.scala 1688:113] wire [31:0] _T_290 = {pc_r,1'h0}; // @[Cat.scala 29:58] - wire [30:0] _T_293 = pc_r + 31'h1; // @[dec_tlu_ctl.scala 1697:83] + wire [30:0] _T_293 = pc_r + 31'h1; // @[dec_tlu_ctl.scala 1693:83] wire [31:0] _T_294 = {_T_293,1'h0}; // @[Cat.scala 29:58] - wire _T_297 = ~io_interrupt_valid_r; // @[dec_tlu_ctl.scala 1700:18] - wire _T_298 = wr_mtval_r & _T_297; // @[dec_tlu_ctl.scala 1700:16] - wire _T_301 = ~wr_mtval_r; // @[dec_tlu_ctl.scala 1701:20] - wire _T_302 = _T_213 & _T_301; // @[dec_tlu_ctl.scala 1701:18] - wire _T_304 = _T_302 & _T_282; // @[dec_tlu_ctl.scala 1701:32] - wire _T_306 = _T_304 & _T_284; // @[dec_tlu_ctl.scala 1701:54] - wire _T_307 = ~mtval_clear_r; // @[dec_tlu_ctl.scala 1701:80] - wire _T_308 = _T_306 & _T_307; // @[dec_tlu_ctl.scala 1701:78] - wire _T_310 = _T_308 & _T_286; // @[dec_tlu_ctl.scala 1701:95] + wire _T_297 = ~io_interrupt_valid_r; // @[dec_tlu_ctl.scala 1696:18] + wire _T_298 = wr_mtval_r & _T_297; // @[dec_tlu_ctl.scala 1696:16] + wire _T_301 = ~wr_mtval_r; // @[dec_tlu_ctl.scala 1697:20] + wire _T_302 = _T_213 & _T_301; // @[dec_tlu_ctl.scala 1697:18] + wire _T_304 = _T_302 & _T_282; // @[dec_tlu_ctl.scala 1697:32] + wire _T_306 = _T_304 & _T_284; // @[dec_tlu_ctl.scala 1697:54] + wire _T_307 = ~mtval_clear_r; // @[dec_tlu_ctl.scala 1697:80] + wire _T_308 = _T_306 & _T_307; // @[dec_tlu_ctl.scala 1697:78] + wire _T_310 = _T_308 & _T_286; // @[dec_tlu_ctl.scala 1697:95] wire [31:0] _T_312 = mtval_capture_pc_r ? _T_290 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_313 = mtval_capture_pc_plus2_r ? _T_294 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_314 = mtval_capture_inst_r ? io_dec_illegal_inst : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_315 = mtval_capture_lsu_r ? io_lsu_error_pkt_addr_r : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_316 = _T_298 ? io_dec_csr_wrdata_r : 32'h0; // @[Mux.scala 27:72] - reg [31:0] mtval; // @[dec_tlu_ctl.scala 1703:46] + reg [31:0] mtval; // @[dec_tlu_ctl.scala 1699:46] wire [31:0] _T_317 = _T_310 ? mtval : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_318 = _T_312 | _T_313; // @[Mux.scala 27:72] wire [31:0] _T_319 = _T_318 | _T_314; // @[Mux.scala 27:72] wire [31:0] _T_320 = _T_319 | _T_315; // @[Mux.scala 27:72] wire [31:0] _T_321 = _T_320 | _T_316; // @[Mux.scala 27:72] - wire _T_325 = io_dec_csr_wraddr_r == 12'h7f8; // @[dec_tlu_ctl.scala 1718:68] + wire _T_325 = io_dec_csr_wraddr_r == 12'h7f8; // @[dec_tlu_ctl.scala 1714:68] reg [8:0] mcgc; // @[lib.scala 358:16] - wire _T_337 = io_dec_csr_wraddr_r == 12'h7f9; // @[dec_tlu_ctl.scala 1748:68] + wire _T_337 = io_dec_csr_wraddr_r == 12'h7f9; // @[dec_tlu_ctl.scala 1744:68] reg [14:0] mfdc_int; // @[lib.scala 358:16] - wire [2:0] _T_341 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1761:19] - wire [2:0] _T_345 = ~mfdc_int[14:12]; // @[dec_tlu_ctl.scala 1762:19] + wire [2:0] _T_341 = ~io_dec_csr_wrdata_r[18:16]; // @[dec_tlu_ctl.scala 1757:19] + wire [2:0] _T_345 = ~mfdc_int[14:12]; // @[dec_tlu_ctl.scala 1758:19] wire [18:0] mfdc = {_T_345,4'h0,mfdc_int[11:0]}; // @[Cat.scala 29:58] - wire _T_357 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1781:77] - wire _T_358 = io_dec_csr_wen_r_mod & _T_357; // @[dec_tlu_ctl.scala 1781:48] - wire _T_360 = _T_358 & _T_297; // @[dec_tlu_ctl.scala 1781:87] - wire _T_361 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1781:113] - wire _T_364 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1788:68] - wire _T_368 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1791:71] - wire _T_369 = io_dec_csr_wrdata_r[30] & _T_368; // @[dec_tlu_ctl.scala 1791:69] - wire _T_373 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1792:73] - wire _T_374 = io_dec_csr_wrdata_r[28] & _T_373; // @[dec_tlu_ctl.scala 1792:71] - wire _T_378 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1793:73] - wire _T_379 = io_dec_csr_wrdata_r[26] & _T_378; // @[dec_tlu_ctl.scala 1793:71] - wire _T_383 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1794:73] - wire _T_384 = io_dec_csr_wrdata_r[24] & _T_383; // @[dec_tlu_ctl.scala 1794:71] - wire _T_388 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1795:73] - wire _T_389 = io_dec_csr_wrdata_r[22] & _T_388; // @[dec_tlu_ctl.scala 1795:71] - wire _T_393 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1796:73] - wire _T_394 = io_dec_csr_wrdata_r[20] & _T_393; // @[dec_tlu_ctl.scala 1796:71] - wire _T_398 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1797:73] - wire _T_399 = io_dec_csr_wrdata_r[18] & _T_398; // @[dec_tlu_ctl.scala 1797:71] - wire _T_403 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1798:73] - wire _T_404 = io_dec_csr_wrdata_r[16] & _T_403; // @[dec_tlu_ctl.scala 1798:71] - wire _T_408 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1799:73] - wire _T_409 = io_dec_csr_wrdata_r[14] & _T_408; // @[dec_tlu_ctl.scala 1799:71] - wire _T_413 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1800:73] - wire _T_414 = io_dec_csr_wrdata_r[12] & _T_413; // @[dec_tlu_ctl.scala 1800:71] - wire _T_418 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1801:73] - wire _T_419 = io_dec_csr_wrdata_r[10] & _T_418; // @[dec_tlu_ctl.scala 1801:71] - wire _T_423 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1802:73] - wire _T_424 = io_dec_csr_wrdata_r[8] & _T_423; // @[dec_tlu_ctl.scala 1802:70] - wire _T_428 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1803:73] - wire _T_429 = io_dec_csr_wrdata_r[6] & _T_428; // @[dec_tlu_ctl.scala 1803:70] - wire _T_433 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1804:73] - wire _T_434 = io_dec_csr_wrdata_r[4] & _T_433; // @[dec_tlu_ctl.scala 1804:70] - wire _T_438 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1805:73] - wire _T_439 = io_dec_csr_wrdata_r[2] & _T_438; // @[dec_tlu_ctl.scala 1805:70] - wire _T_444 = io_dec_csr_wrdata_r[0] & _T_500; // @[dec_tlu_ctl.scala 1806:70] + wire _T_357 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 1777:77] + wire _T_358 = io_dec_csr_wen_r_mod & _T_357; // @[dec_tlu_ctl.scala 1777:48] + wire _T_360 = _T_358 & _T_297; // @[dec_tlu_ctl.scala 1777:87] + wire _T_361 = ~io_take_ext_int_start; // @[dec_tlu_ctl.scala 1777:113] + wire _T_364 = io_dec_csr_wraddr_r == 12'h7c0; // @[dec_tlu_ctl.scala 1784:68] + wire _T_368 = ~io_dec_csr_wrdata_r[31]; // @[dec_tlu_ctl.scala 1787:71] + wire _T_369 = io_dec_csr_wrdata_r[30] & _T_368; // @[dec_tlu_ctl.scala 1787:69] + wire _T_373 = ~io_dec_csr_wrdata_r[29]; // @[dec_tlu_ctl.scala 1788:73] + wire _T_374 = io_dec_csr_wrdata_r[28] & _T_373; // @[dec_tlu_ctl.scala 1788:71] + wire _T_378 = ~io_dec_csr_wrdata_r[27]; // @[dec_tlu_ctl.scala 1789:73] + wire _T_379 = io_dec_csr_wrdata_r[26] & _T_378; // @[dec_tlu_ctl.scala 1789:71] + wire _T_383 = ~io_dec_csr_wrdata_r[25]; // @[dec_tlu_ctl.scala 1790:73] + wire _T_384 = io_dec_csr_wrdata_r[24] & _T_383; // @[dec_tlu_ctl.scala 1790:71] + wire _T_388 = ~io_dec_csr_wrdata_r[23]; // @[dec_tlu_ctl.scala 1791:73] + wire _T_389 = io_dec_csr_wrdata_r[22] & _T_388; // @[dec_tlu_ctl.scala 1791:71] + wire _T_393 = ~io_dec_csr_wrdata_r[21]; // @[dec_tlu_ctl.scala 1792:73] + wire _T_394 = io_dec_csr_wrdata_r[20] & _T_393; // @[dec_tlu_ctl.scala 1792:71] + wire _T_398 = ~io_dec_csr_wrdata_r[19]; // @[dec_tlu_ctl.scala 1793:73] + wire _T_399 = io_dec_csr_wrdata_r[18] & _T_398; // @[dec_tlu_ctl.scala 1793:71] + wire _T_403 = ~io_dec_csr_wrdata_r[17]; // @[dec_tlu_ctl.scala 1794:73] + wire _T_404 = io_dec_csr_wrdata_r[16] & _T_403; // @[dec_tlu_ctl.scala 1794:71] + wire _T_408 = ~io_dec_csr_wrdata_r[15]; // @[dec_tlu_ctl.scala 1795:73] + wire _T_409 = io_dec_csr_wrdata_r[14] & _T_408; // @[dec_tlu_ctl.scala 1795:71] + wire _T_413 = ~io_dec_csr_wrdata_r[13]; // @[dec_tlu_ctl.scala 1796:73] + wire _T_414 = io_dec_csr_wrdata_r[12] & _T_413; // @[dec_tlu_ctl.scala 1796:71] + wire _T_418 = ~io_dec_csr_wrdata_r[11]; // @[dec_tlu_ctl.scala 1797:73] + wire _T_419 = io_dec_csr_wrdata_r[10] & _T_418; // @[dec_tlu_ctl.scala 1797:71] + wire _T_423 = ~io_dec_csr_wrdata_r[9]; // @[dec_tlu_ctl.scala 1798:73] + wire _T_424 = io_dec_csr_wrdata_r[8] & _T_423; // @[dec_tlu_ctl.scala 1798:70] + wire _T_428 = ~io_dec_csr_wrdata_r[7]; // @[dec_tlu_ctl.scala 1799:73] + wire _T_429 = io_dec_csr_wrdata_r[6] & _T_428; // @[dec_tlu_ctl.scala 1799:70] + wire _T_433 = ~io_dec_csr_wrdata_r[5]; // @[dec_tlu_ctl.scala 1800:73] + wire _T_434 = io_dec_csr_wrdata_r[4] & _T_433; // @[dec_tlu_ctl.scala 1800:70] + wire _T_438 = ~io_dec_csr_wrdata_r[3]; // @[dec_tlu_ctl.scala 1801:73] + wire _T_439 = io_dec_csr_wrdata_r[2] & _T_438; // @[dec_tlu_ctl.scala 1801:70] + wire _T_444 = io_dec_csr_wrdata_r[0] & _T_500; // @[dec_tlu_ctl.scala 1802:70] wire [7:0] _T_451 = {io_dec_csr_wrdata_r[7],_T_429,io_dec_csr_wrdata_r[5],_T_434,io_dec_csr_wrdata_r[3],_T_439,io_dec_csr_wrdata_r[1],_T_444}; // @[Cat.scala 29:58] wire [15:0] _T_459 = {io_dec_csr_wrdata_r[15],_T_409,io_dec_csr_wrdata_r[13],_T_414,io_dec_csr_wrdata_r[11],_T_419,io_dec_csr_wrdata_r[9],_T_424,_T_451}; // @[Cat.scala 29:58] wire [7:0] _T_466 = {io_dec_csr_wrdata_r[23],_T_389,io_dec_csr_wrdata_r[21],_T_394,io_dec_csr_wrdata_r[19],_T_399,io_dec_csr_wrdata_r[17],_T_404}; // @[Cat.scala 29:58] wire [15:0] _T_474 = {io_dec_csr_wrdata_r[31],_T_369,io_dec_csr_wrdata_r[29],_T_374,io_dec_csr_wrdata_r[27],_T_379,io_dec_csr_wrdata_r[25],_T_384,_T_466}; // @[Cat.scala 29:58] reg [31:0] mrac; // @[lib.scala 358:16] - wire _T_477 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1819:69] - wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_477; // @[dec_tlu_ctl.scala 1819:40] - wire _T_478 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1829:59] - wire _T_479 = io_mdseac_locked_f & _T_478; // @[dec_tlu_ctl.scala 1829:57] - wire _T_481 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1831:49] - wire _T_482 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1831:86] - wire _T_483 = _T_481 & _T_482; // @[dec_tlu_ctl.scala 1831:84] - wire _T_484 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1831:111] - wire mdseac_en = _T_483 & _T_484; // @[dec_tlu_ctl.scala 1831:109] + wire _T_477 = io_dec_csr_wraddr_r == 12'hbc0; // @[dec_tlu_ctl.scala 1815:69] + wire wr_mdeau_r = io_dec_csr_wen_r_mod & _T_477; // @[dec_tlu_ctl.scala 1815:40] + wire _T_478 = ~wr_mdeau_r; // @[dec_tlu_ctl.scala 1825:59] + wire _T_479 = io_mdseac_locked_f & _T_478; // @[dec_tlu_ctl.scala 1825:57] + wire _T_481 = io_lsu_imprecise_error_store_any | io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 1827:49] + wire _T_482 = ~io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 1827:86] + wire _T_483 = _T_481 & _T_482; // @[dec_tlu_ctl.scala 1827:84] + wire _T_484 = ~io_mdseac_locked_f; // @[dec_tlu_ctl.scala 1827:111] + wire mdseac_en = _T_483 & _T_484; // @[dec_tlu_ctl.scala 1827:109] reg [31:0] mdseac; // @[lib.scala 358:16] - wire _T_490 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1846:30] - wire _T_491 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1846:57] - wire _T_492 = _T_490 & _T_491; // @[dec_tlu_ctl.scala 1846:55] - wire _T_493 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1846:89] - wire _T_506 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1864:48] - wire [4:0] csr_sat = _T_506 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1864:19] - wire _T_509 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1866:70] - wire wr_micect_r = io_dec_csr_wen_r_mod & _T_509; // @[dec_tlu_ctl.scala 1866:41] + wire _T_490 = wr_mpmc_r & io_dec_csr_wrdata_r[0]; // @[dec_tlu_ctl.scala 1842:30] + wire _T_491 = ~io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 1842:57] + wire _T_492 = _T_490 & _T_491; // @[dec_tlu_ctl.scala 1842:55] + wire _T_493 = ~io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 1842:89] + wire _T_506 = io_dec_csr_wrdata_r[31:27] > 5'h1a; // @[dec_tlu_ctl.scala 1860:48] + wire [4:0] csr_sat = _T_506 ? 5'h1a : io_dec_csr_wrdata_r[31:27]; // @[dec_tlu_ctl.scala 1860:19] + wire _T_509 = io_dec_csr_wraddr_r == 12'h7f0; // @[dec_tlu_ctl.scala 1862:70] + wire wr_micect_r = io_dec_csr_wen_r_mod & _T_509; // @[dec_tlu_ctl.scala 1862:41] wire [26:0] _T_510 = {26'h0,io_ic_perr_r_d1}; // @[Cat.scala 29:58] - wire [31:0] _GEN_14 = {{5'd0}, _T_510}; // @[dec_tlu_ctl.scala 1867:23] - wire [31:0] _T_512 = micect + _GEN_14; // @[dec_tlu_ctl.scala 1867:23] + wire [31:0] _GEN_14 = {{5'd0}, _T_510}; // @[dec_tlu_ctl.scala 1863:23] + wire [31:0] _T_512 = micect + _GEN_14; // @[dec_tlu_ctl.scala 1863:23] wire [31:0] _T_515 = {csr_sat,io_dec_csr_wrdata_r[26:0]}; // @[Cat.scala 29:58] - wire [26:0] micect_inc = _T_512[26:0]; // @[dec_tlu_ctl.scala 1867:13] + wire [26:0] micect_inc = _T_512[26:0]; // @[dec_tlu_ctl.scala 1863:13] wire [31:0] _T_517 = {micect[31:27],micect_inc}; // @[Cat.scala 29:58] - wire _T_528 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1881:76] - wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_528; // @[dec_tlu_ctl.scala 1881:47] - wire _T_530 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1882:70] + wire _T_528 = io_dec_csr_wraddr_r == 12'h7f1; // @[dec_tlu_ctl.scala 1877:76] + wire wr_miccmect_r = io_dec_csr_wen_r_mod & _T_528; // @[dec_tlu_ctl.scala 1877:47] + wire _T_530 = io_iccm_sbecc_r_d1 | io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 1878:70] wire [26:0] _T_531 = {26'h0,_T_530}; // @[Cat.scala 29:58] - wire [26:0] miccmect_inc = miccmect[26:0] + _T_531; // @[dec_tlu_ctl.scala 1882:33] + wire [26:0] miccmect_inc = miccmect[26:0] + _T_531; // @[dec_tlu_ctl.scala 1878:33] wire [31:0] _T_538 = {miccmect[31:27],miccmect_inc}; // @[Cat.scala 29:58] - wire _T_539 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 1885:48] - wire _T_550 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1896:76] - wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_550; // @[dec_tlu_ctl.scala 1896:47] + wire _T_539 = wr_miccmect_r | io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 1881:48] + wire _T_550 = io_dec_csr_wraddr_r == 12'h7f2; // @[dec_tlu_ctl.scala 1892:76] + wire wr_mdccmect_r = io_dec_csr_wen_r_mod & _T_550; // @[dec_tlu_ctl.scala 1892:47] wire [26:0] _T_552 = {26'h0,io_lsu_single_ecc_error_r_d1}; // @[Cat.scala 29:58] - wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_552; // @[dec_tlu_ctl.scala 1897:33] + wire [26:0] mdccmect_inc = mdccmect[26:0] + _T_552; // @[dec_tlu_ctl.scala 1893:33] wire [31:0] _T_559 = {mdccmect[31:27],mdccmect_inc}; // @[Cat.scala 29:58] - wire _T_570 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1912:69] - wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_570; // @[dec_tlu_ctl.scala 1912:40] - reg [5:0] mfdht; // @[dec_tlu_ctl.scala 1916:43] - wire _T_575 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1925:69] - wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_575; // @[dec_tlu_ctl.scala 1925:40] - wire _T_578 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1928:43] - wire _T_579 = io_dbg_tlu_halted & _T_578; // @[dec_tlu_ctl.scala 1928:41] - wire _T_581 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1928:78] - wire _T_582 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1928:98] + wire _T_570 = io_dec_csr_wraddr_r == 12'h7ce; // @[dec_tlu_ctl.scala 1908:69] + wire wr_mfdht_r = io_dec_csr_wen_r_mod & _T_570; // @[dec_tlu_ctl.scala 1908:40] + reg [5:0] mfdht; // @[dec_tlu_ctl.scala 1912:43] + wire _T_575 = io_dec_csr_wraddr_r == 12'h7cf; // @[dec_tlu_ctl.scala 1921:69] + wire wr_mfdhs_r = io_dec_csr_wen_r_mod & _T_575; // @[dec_tlu_ctl.scala 1921:40] + wire _T_578 = ~io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1924:43] + wire _T_579 = io_dbg_tlu_halted & _T_578; // @[dec_tlu_ctl.scala 1924:41] + wire _T_581 = ~io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 1924:78] + wire _T_582 = ~io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 1924:98] wire [1:0] _T_583 = {_T_581,_T_582}; // @[Cat.scala 29:58] reg [1:0] mfdhs; // @[Reg.scala 27:20] - wire _T_585 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1930:71] + wire _T_585 = wr_mfdhs_r | io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 1926:71] reg [31:0] force_halt_ctr_f; // @[Reg.scala 27:20] - wire [31:0] _T_590 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1932:74] - wire [62:0] _T_597 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1937:71] - wire [62:0] _GEN_15 = {{31'd0}, force_halt_ctr_f}; // @[dec_tlu_ctl.scala 1937:48] - wire [62:0] _T_598 = _GEN_15 & _T_597; // @[dec_tlu_ctl.scala 1937:48] - wire _T_599 = |_T_598; // @[dec_tlu_ctl.scala 1937:87] - wire _T_602 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1945:69] + wire [31:0] _T_590 = force_halt_ctr_f + 32'h1; // @[dec_tlu_ctl.scala 1928:74] + wire [62:0] _T_597 = 63'hffffffff << mfdht[5:1]; // @[dec_tlu_ctl.scala 1933:71] + wire [62:0] _GEN_15 = {{31'd0}, force_halt_ctr_f}; // @[dec_tlu_ctl.scala 1933:48] + wire [62:0] _T_598 = _GEN_15 & _T_597; // @[dec_tlu_ctl.scala 1933:48] + wire _T_599 = |_T_598; // @[dec_tlu_ctl.scala 1933:87] + wire _T_602 = io_dec_csr_wraddr_r == 12'hbc8; // @[dec_tlu_ctl.scala 1941:69] reg [21:0] meivt; // @[lib.scala 358:16] - wire _T_621 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 1996:69] - wire _T_622 = io_dec_csr_wen_r_mod & _T_621; // @[dec_tlu_ctl.scala 1996:40] - wire wr_meicpct_r = _T_622 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1996:83] + wire _T_621 = io_dec_csr_wraddr_r == 12'hbca; // @[dec_tlu_ctl.scala 1992:69] + wire _T_622 = io_dec_csr_wen_r_mod & _T_621; // @[dec_tlu_ctl.scala 1992:40] + wire wr_meicpct_r = _T_622 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1992:83] reg [7:0] meihap; // @[lib.scala 358:16] - wire _T_608 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 1969:72] - wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_608; // @[dec_tlu_ctl.scala 1969:43] - reg [3:0] meicurpl; // @[dec_tlu_ctl.scala 1972:46] - wire _T_613 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 1984:73] - wire _T_614 = io_dec_csr_wen_r_mod & _T_613; // @[dec_tlu_ctl.scala 1984:44] - wire wr_meicidpl_r = _T_614 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1984:88] - reg [3:0] meicidpl; // @[dec_tlu_ctl.scala 1989:44] - wire _T_625 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 2005:69] - wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_625; // @[dec_tlu_ctl.scala 2005:40] - reg [3:0] meipt; // @[dec_tlu_ctl.scala 2008:43] - wire _T_629 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2036:89] - wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_629; // @[dec_tlu_ctl.scala 2036:66] - wire _T_630 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2039:31] - wire _T_631 = io_dcsr_single_step_done_f & _T_630; // @[dec_tlu_ctl.scala 2039:29] - wire _T_632 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2039:63] - wire _T_633 = _T_631 & _T_632; // @[dec_tlu_ctl.scala 2039:61] - wire _T_634 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2039:98] - wire _T_635 = _T_633 & _T_634; // @[dec_tlu_ctl.scala 2039:96] - wire _T_638 = io_debug_halt_req & _T_630; // @[dec_tlu_ctl.scala 2040:46] - wire _T_640 = _T_638 & _T_632; // @[dec_tlu_ctl.scala 2040:78] - wire _T_643 = io_ebreak_to_debug_mode_r_d1 & _T_632; // @[dec_tlu_ctl.scala 2041:75] + wire _T_608 = io_dec_csr_wraddr_r == 12'hbcc; // @[dec_tlu_ctl.scala 1965:72] + wire wr_meicurpl_r = io_dec_csr_wen_r_mod & _T_608; // @[dec_tlu_ctl.scala 1965:43] + reg [3:0] meicurpl; // @[dec_tlu_ctl.scala 1968:46] + wire _T_613 = io_dec_csr_wraddr_r == 12'hbcb; // @[dec_tlu_ctl.scala 1980:73] + wire _T_614 = io_dec_csr_wen_r_mod & _T_613; // @[dec_tlu_ctl.scala 1980:44] + wire wr_meicidpl_r = _T_614 | io_take_ext_int_start; // @[dec_tlu_ctl.scala 1980:88] + reg [3:0] meicidpl; // @[dec_tlu_ctl.scala 1985:44] + wire _T_625 = io_dec_csr_wraddr_r == 12'hbc9; // @[dec_tlu_ctl.scala 2001:69] + wire wr_meipt_r = io_dec_csr_wen_r_mod & _T_625; // @[dec_tlu_ctl.scala 2001:40] + reg [3:0] meipt; // @[dec_tlu_ctl.scala 2004:43] + wire _T_629 = io_trigger_hit_r_d1 & io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 2032:89] + wire trigger_hit_for_dscr_cause_r_d1 = io_trigger_hit_dmode_r_d1 | _T_629; // @[dec_tlu_ctl.scala 2032:66] + wire _T_630 = ~io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 2035:31] + wire _T_631 = io_dcsr_single_step_done_f & _T_630; // @[dec_tlu_ctl.scala 2035:29] + wire _T_632 = ~trigger_hit_for_dscr_cause_r_d1; // @[dec_tlu_ctl.scala 2035:63] + wire _T_633 = _T_631 & _T_632; // @[dec_tlu_ctl.scala 2035:61] + wire _T_634 = ~io_debug_halt_req; // @[dec_tlu_ctl.scala 2035:98] + wire _T_635 = _T_633 & _T_634; // @[dec_tlu_ctl.scala 2035:96] + wire _T_638 = io_debug_halt_req & _T_630; // @[dec_tlu_ctl.scala 2036:46] + wire _T_640 = _T_638 & _T_632; // @[dec_tlu_ctl.scala 2036:78] + wire _T_643 = io_ebreak_to_debug_mode_r_d1 & _T_632; // @[dec_tlu_ctl.scala 2037:75] wire [2:0] _T_646 = _T_635 ? 3'h4 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_647 = _T_640 ? 3'h3 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_648 = _T_643 ? 3'h1 : 3'h0; // @[Mux.scala 27:72] @@ -51275,102 +51273,102 @@ module csr_tlu( wire [2:0] _T_650 = _T_646 | _T_647; // @[Mux.scala 27:72] wire [2:0] _T_651 = _T_650 | _T_648; // @[Mux.scala 27:72] wire [2:0] dcsr_cause = _T_651 | _T_649; // @[Mux.scala 27:72] - wire _T_653 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2044:46] - wire _T_655 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2044:98] - wire wr_dcsr_r = _T_653 & _T_655; // @[dec_tlu_ctl.scala 2044:69] - wire _T_657 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2050:75] - wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_657; // @[dec_tlu_ctl.scala 2050:59] - wire _T_658 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2051:59] - wire _T_659 = _T_658 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2051:78] - wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_659; // @[dec_tlu_ctl.scala 2051:56] - wire nmi_in_debug_mode = io_nmi_int_detected_f & io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 2053:48] + wire _T_653 = io_allow_dbg_halt_csr_write & io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 2040:46] + wire _T_655 = io_dec_csr_wraddr_r == 12'h7b0; // @[dec_tlu_ctl.scala 2040:98] + wire wr_dcsr_r = _T_653 & _T_655; // @[dec_tlu_ctl.scala 2040:69] + wire _T_657 = io_dcsr[8:6] == 3'h3; // @[dec_tlu_ctl.scala 2046:75] + wire dcsr_cause_upgradeable = io_internal_dbg_halt_mode_f & _T_657; // @[dec_tlu_ctl.scala 2046:59] + wire _T_658 = ~io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 2047:59] + wire _T_659 = _T_658 | dcsr_cause_upgradeable; // @[dec_tlu_ctl.scala 2047:78] + wire enter_debug_halt_req_le = io_enter_debug_halt_req & _T_659; // @[dec_tlu_ctl.scala 2047:56] + wire nmi_in_debug_mode = io_nmi_int_detected_f & io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 2049:48] wire [15:0] _T_665 = {io_dcsr[15:9],dcsr_cause,io_dcsr[5:2],2'h3}; // @[Cat.scala 29:58] - wire _T_671 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2055:145] + wire _T_671 = nmi_in_debug_mode | io_dcsr[3]; // @[dec_tlu_ctl.scala 2051:145] wire [15:0] _T_680 = {io_dec_csr_wrdata_r[15],3'h0,io_dec_csr_wrdata_r[11:10],1'h0,io_dcsr[8:6],2'h0,_T_671,io_dec_csr_wrdata_r[2],2'h3}; // @[Cat.scala 29:58] wire [15:0] _T_685 = {io_dcsr[15:4],nmi_in_debug_mode,io_dcsr[2],2'h3}; // @[Cat.scala 29:58] - wire _T_687 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2057:54] - wire _T_688 = _T_687 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2057:66] + wire _T_687 = enter_debug_halt_req_le | wr_dcsr_r; // @[dec_tlu_ctl.scala 2053:54] + wire _T_688 = _T_687 | io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 2053:66] reg [15:0] _T_691; // @[lib.scala 358:16] - wire _T_694 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2065:97] - wire wr_dpc_r = _T_653 & _T_694; // @[dec_tlu_ctl.scala 2065:68] - wire _T_697 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2066:67] - wire dpc_capture_npc = _T_579 & _T_697; // @[dec_tlu_ctl.scala 2066:65] - wire _T_698 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2070:21] - wire _T_699 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2070:39] - wire _T_700 = _T_698 & _T_699; // @[dec_tlu_ctl.scala 2070:37] - wire _T_701 = _T_700 & wr_dpc_r; // @[dec_tlu_ctl.scala 2070:56] - wire _T_706 = _T_698 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2072:49] + wire _T_694 = io_dec_csr_wraddr_r == 12'h7b1; // @[dec_tlu_ctl.scala 2061:97] + wire wr_dpc_r = _T_653 & _T_694; // @[dec_tlu_ctl.scala 2061:68] + wire _T_697 = ~io_request_debug_mode_done; // @[dec_tlu_ctl.scala 2062:67] + wire dpc_capture_npc = _T_579 & _T_697; // @[dec_tlu_ctl.scala 2062:65] + wire _T_698 = ~io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2066:21] + wire _T_699 = ~dpc_capture_npc; // @[dec_tlu_ctl.scala 2066:39] + wire _T_700 = _T_698 & _T_699; // @[dec_tlu_ctl.scala 2066:37] + wire _T_701 = _T_700 & wr_dpc_r; // @[dec_tlu_ctl.scala 2066:56] + wire _T_706 = _T_698 & dpc_capture_npc; // @[dec_tlu_ctl.scala 2068:49] wire [30:0] _T_708 = _T_701 ? io_dec_csr_wrdata_r[31:1] : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_709 = io_request_debug_mode_r ? pc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_710 = _T_706 ? io_npc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_711 = _T_708 | _T_709; // @[Mux.scala 27:72] - wire _T_713 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2074:36] + wire _T_713 = wr_dpc_r | io_request_debug_mode_r; // @[dec_tlu_ctl.scala 2070:36] reg [30:0] _T_716; // @[lib.scala 358:16] wire [2:0] _T_720 = {io_dec_csr_wrdata_r[24],io_dec_csr_wrdata_r[21:20]}; // @[Cat.scala 29:58] - wire _T_723 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2089:102] + wire _T_723 = io_dec_csr_wraddr_r == 12'h7c8; // @[dec_tlu_ctl.scala 2085:102] reg [16:0] dicawics; // @[lib.scala 358:16] - wire _T_727 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2107:100] - wire wr_dicad0_r = _T_653 & _T_727; // @[dec_tlu_ctl.scala 2107:71] + wire _T_727 = io_dec_csr_wraddr_r == 12'h7c9; // @[dec_tlu_ctl.scala 2103:100] + wire wr_dicad0_r = _T_653 & _T_727; // @[dec_tlu_ctl.scala 2103:71] reg [70:0] dicad0; // @[lib.scala 358:16] - wire _T_733 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2120:101] - wire wr_dicad0h_r = _T_653 & _T_733; // @[dec_tlu_ctl.scala 2120:72] + wire _T_733 = io_dec_csr_wraddr_r == 12'h7cc; // @[dec_tlu_ctl.scala 2116:101] + wire wr_dicad0h_r = _T_653 & _T_733; // @[dec_tlu_ctl.scala 2116:72] reg [31:0] dicad0h; // @[lib.scala 358:16] - wire _T_741 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2147:100] - wire _T_742 = _T_653 & _T_741; // @[dec_tlu_ctl.scala 2147:71] - wire _T_747 = _T_742 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2151:77] + wire _T_741 = io_dec_csr_wraddr_r == 12'h7ca; // @[dec_tlu_ctl.scala 2143:100] + wire _T_742 = _T_653 & _T_741; // @[dec_tlu_ctl.scala 2143:71] + wire _T_747 = _T_742 | io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 2147:77] reg [3:0] _T_749; // @[Reg.scala 27:20] wire [31:0] dicad1 = {28'h0,_T_749}; // @[Cat.scala 29:58] wire [69:0] _T_756 = {2'h0,dicad1[3:0],dicad0h,dicad0[31:0]}; // @[Cat.scala 29:58] - wire _T_757 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2164:52] - wire _T_758 = _T_757 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2164:75] - wire _T_759 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2164:98] - wire _T_760 = _T_758 & _T_759; // @[dec_tlu_ctl.scala 2164:96] - wire _T_762 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2164:149] - wire _T_765 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2165:104] - reg icache_rd_valid_f; // @[dec_tlu_ctl.scala 2167:58] - reg icache_wr_valid_f; // @[dec_tlu_ctl.scala 2168:58] - wire _T_767 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2179:69] - wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_767; // @[dec_tlu_ctl.scala 2179:40] - reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2182:43] - wire tdata_load = io_dec_csr_wrdata_r[0] & _T_398; // @[dec_tlu_ctl.scala 2217:42] - wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_398; // @[dec_tlu_ctl.scala 2219:44] - wire _T_778 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2221:46] - wire tdata_action = _T_778 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2221:69] + wire _T_757 = io_allow_dbg_halt_csr_write & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 2160:52] + wire _T_758 = _T_757 & io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 2160:75] + wire _T_759 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 2160:98] + wire _T_760 = _T_758 & _T_759; // @[dec_tlu_ctl.scala 2160:96] + wire _T_762 = io_dec_csr_rdaddr_d == 12'h7cb; // @[dec_tlu_ctl.scala 2160:149] + wire _T_765 = io_dec_csr_wraddr_r == 12'h7cb; // @[dec_tlu_ctl.scala 2161:104] + reg icache_rd_valid_f; // @[dec_tlu_ctl.scala 2163:58] + reg icache_wr_valid_f; // @[dec_tlu_ctl.scala 2164:58] + wire _T_767 = io_dec_csr_wraddr_r == 12'h7a0; // @[dec_tlu_ctl.scala 2175:69] + wire wr_mtsel_r = io_dec_csr_wen_r_mod & _T_767; // @[dec_tlu_ctl.scala 2175:40] + reg [1:0] mtsel; // @[dec_tlu_ctl.scala 2178:43] + wire tdata_load = io_dec_csr_wrdata_r[0] & _T_398; // @[dec_tlu_ctl.scala 2213:42] + wire tdata_opcode = io_dec_csr_wrdata_r[2] & _T_398; // @[dec_tlu_ctl.scala 2215:44] + wire _T_778 = io_dec_csr_wrdata_r[27] & io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2217:46] + wire tdata_action = _T_778 & io_dec_csr_wrdata_r[12]; // @[dec_tlu_ctl.scala 2217:69] wire [9:0] tdata_wrdata_r = {_T_778,io_dec_csr_wrdata_r[20:19],tdata_action,io_dec_csr_wrdata_r[11],io_dec_csr_wrdata_r[7:6],tdata_opcode,io_dec_csr_wrdata_r[1],tdata_load}; // @[Cat.scala 29:58] - wire _T_793 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2227:99] - wire _T_794 = io_dec_csr_wen_r_mod & _T_793; // @[dec_tlu_ctl.scala 2227:70] - wire _T_795 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2227:121] - wire _T_796 = _T_794 & _T_795; // @[dec_tlu_ctl.scala 2227:112] - wire _T_798 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2227:138] - wire _T_799 = _T_798 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2227:170] - wire wr_mtdata1_t_r_0 = _T_796 & _T_799; // @[dec_tlu_ctl.scala 2227:135] - wire _T_804 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2227:121] - wire _T_805 = _T_794 & _T_804; // @[dec_tlu_ctl.scala 2227:112] - wire _T_807 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2227:138] - wire _T_808 = _T_807 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2227:170] - wire wr_mtdata1_t_r_1 = _T_805 & _T_808; // @[dec_tlu_ctl.scala 2227:135] - wire _T_813 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2227:121] - wire _T_814 = _T_794 & _T_813; // @[dec_tlu_ctl.scala 2227:112] - wire _T_816 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2227:138] - wire _T_817 = _T_816 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2227:170] - wire wr_mtdata1_t_r_2 = _T_814 & _T_817; // @[dec_tlu_ctl.scala 2227:135] - wire _T_822 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2227:121] - wire _T_823 = _T_794 & _T_822; // @[dec_tlu_ctl.scala 2227:112] - wire _T_825 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2227:138] - wire _T_826 = _T_825 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2227:170] - wire wr_mtdata1_t_r_3 = _T_823 & _T_826; // @[dec_tlu_ctl.scala 2227:135] - wire _T_832 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2228:139] + wire _T_793 = io_dec_csr_wraddr_r == 12'h7a1; // @[dec_tlu_ctl.scala 2223:99] + wire _T_794 = io_dec_csr_wen_r_mod & _T_793; // @[dec_tlu_ctl.scala 2223:70] + wire _T_795 = mtsel == 2'h0; // @[dec_tlu_ctl.scala 2223:121] + wire _T_796 = _T_794 & _T_795; // @[dec_tlu_ctl.scala 2223:112] + wire _T_798 = ~io_mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 2223:138] + wire _T_799 = _T_798 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] + wire wr_mtdata1_t_r_0 = _T_796 & _T_799; // @[dec_tlu_ctl.scala 2223:135] + wire _T_804 = mtsel == 2'h1; // @[dec_tlu_ctl.scala 2223:121] + wire _T_805 = _T_794 & _T_804; // @[dec_tlu_ctl.scala 2223:112] + wire _T_807 = ~io_mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 2223:138] + wire _T_808 = _T_807 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] + wire wr_mtdata1_t_r_1 = _T_805 & _T_808; // @[dec_tlu_ctl.scala 2223:135] + wire _T_813 = mtsel == 2'h2; // @[dec_tlu_ctl.scala 2223:121] + wire _T_814 = _T_794 & _T_813; // @[dec_tlu_ctl.scala 2223:112] + wire _T_816 = ~io_mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 2223:138] + wire _T_817 = _T_816 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] + wire wr_mtdata1_t_r_2 = _T_814 & _T_817; // @[dec_tlu_ctl.scala 2223:135] + wire _T_822 = mtsel == 2'h3; // @[dec_tlu_ctl.scala 2223:121] + wire _T_823 = _T_794 & _T_822; // @[dec_tlu_ctl.scala 2223:112] + wire _T_825 = ~io_mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 2223:138] + wire _T_826 = _T_825 | io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 2223:170] + wire wr_mtdata1_t_r_3 = _T_823 & _T_826; // @[dec_tlu_ctl.scala 2223:135] + wire _T_832 = io_update_hit_bit_r[0] | io_mtdata1_t_0[8]; // @[dec_tlu_ctl.scala 2224:139] wire [9:0] _T_835 = {io_mtdata1_t_0[9],_T_832,io_mtdata1_t_0[7:0]}; // @[Cat.scala 29:58] - wire _T_841 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2228:139] + wire _T_841 = io_update_hit_bit_r[1] | io_mtdata1_t_1[8]; // @[dec_tlu_ctl.scala 2224:139] wire [9:0] _T_844 = {io_mtdata1_t_1[9],_T_841,io_mtdata1_t_1[7:0]}; // @[Cat.scala 29:58] - wire _T_850 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2228:139] + wire _T_850 = io_update_hit_bit_r[2] | io_mtdata1_t_2[8]; // @[dec_tlu_ctl.scala 2224:139] wire [9:0] _T_853 = {io_mtdata1_t_2[9],_T_850,io_mtdata1_t_2[7:0]}; // @[Cat.scala 29:58] - wire _T_859 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2228:139] + wire _T_859 = io_update_hit_bit_r[3] | io_mtdata1_t_3[8]; // @[dec_tlu_ctl.scala 2224:139] wire [9:0] _T_862 = {io_mtdata1_t_3[9],_T_859,io_mtdata1_t_3[7:0]}; // @[Cat.scala 29:58] - reg [9:0] _T_864; // @[dec_tlu_ctl.scala 2230:74] - reg [9:0] _T_865; // @[dec_tlu_ctl.scala 2230:74] - reg [9:0] _T_866; // @[dec_tlu_ctl.scala 2230:74] - reg [9:0] _T_867; // @[dec_tlu_ctl.scala 2230:74] + reg [9:0] _T_864; // @[dec_tlu_ctl.scala 2226:74] + reg [9:0] _T_865; // @[dec_tlu_ctl.scala 2226:74] + reg [9:0] _T_866; // @[dec_tlu_ctl.scala 2226:74] + reg [9:0] _T_867; // @[dec_tlu_ctl.scala 2226:74] wire [31:0] _T_882 = {4'h2,io_mtdata1_t_0[9],6'h1f,io_mtdata1_t_0[8:7],6'h0,io_mtdata1_t_0[6:5],3'h0,io_mtdata1_t_0[4:3],3'h0,io_mtdata1_t_0[2:0]}; // @[Cat.scala 29:58] wire [31:0] _T_897 = {4'h2,io_mtdata1_t_1[9],6'h1f,io_mtdata1_t_1[8:7],6'h0,io_mtdata1_t_1[6:5],3'h0,io_mtdata1_t_1[4:3],3'h0,io_mtdata1_t_1[2:0]}; // @[Cat.scala 29:58] wire [31:0] _T_912 = {4'h2,io_mtdata1_t_2[9],6'h1f,io_mtdata1_t_2[8:7],6'h0,io_mtdata1_t_2[6:5],3'h0,io_mtdata1_t_2[4:3],3'h0,io_mtdata1_t_2[2:0]}; // @[Cat.scala 29:58] @@ -51382,12 +51380,12 @@ module csr_tlu( wire [31:0] _T_932 = _T_928 | _T_929; // @[Mux.scala 27:72] wire [31:0] _T_933 = _T_932 | _T_930; // @[Mux.scala 27:72] wire [31:0] mtdata1_tsel_out = _T_933 | _T_931; // @[Mux.scala 27:72] - wire _T_960 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2247:98] - wire _T_961 = io_dec_csr_wen_r_mod & _T_960; // @[dec_tlu_ctl.scala 2247:69] - wire _T_963 = _T_961 & _T_795; // @[dec_tlu_ctl.scala 2247:111] - wire _T_972 = _T_961 & _T_804; // @[dec_tlu_ctl.scala 2247:111] - wire _T_981 = _T_961 & _T_813; // @[dec_tlu_ctl.scala 2247:111] - wire _T_990 = _T_961 & _T_822; // @[dec_tlu_ctl.scala 2247:111] + wire _T_960 = io_dec_csr_wraddr_r == 12'h7a2; // @[dec_tlu_ctl.scala 2243:98] + wire _T_961 = io_dec_csr_wen_r_mod & _T_960; // @[dec_tlu_ctl.scala 2243:69] + wire _T_963 = _T_961 & _T_795; // @[dec_tlu_ctl.scala 2243:111] + wire _T_972 = _T_961 & _T_804; // @[dec_tlu_ctl.scala 2243:111] + wire _T_981 = _T_961 & _T_813; // @[dec_tlu_ctl.scala 2243:111] + wire _T_990 = _T_961 & _T_822; // @[dec_tlu_ctl.scala 2243:111] reg [31:0] mtdata2_t_0; // @[lib.scala 358:16] reg [31:0] mtdata2_t_1; // @[lib.scala 358:16] reg [31:0] mtdata2_t_2; // @[lib.scala 358:16] @@ -51400,106 +51398,106 @@ module csr_tlu( wire [31:0] _T_1012 = _T_1011 | _T_1009; // @[Mux.scala 27:72] wire [31:0] mtdata2_tsel_out = _T_1012 | _T_1010; // @[Mux.scala 27:72] wire [3:0] _T_1015 = io_tlu_i0_commit_cmt ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1015; // @[dec_tlu_ctl.scala 2272:59] - wire _T_1017 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2278:24] + wire [3:0] pmu_i0_itype_qual = io_dec_tlu_packet_r_pmu_i0_itype & _T_1015; // @[dec_tlu_ctl.scala 2268:59] + wire _T_1017 = ~mcountinhibit[3]; // @[dec_tlu_ctl.scala 2274:24] reg [9:0] mhpme3; // @[Reg.scala 27:20] - wire _T_1018 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1020 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1022 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1024 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1026 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2282:96] - wire _T_1027 = io_tlu_i0_commit_cmt & _T_1026; // @[dec_tlu_ctl.scala 2282:94] - wire _T_1028 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1030 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2283:96] - wire _T_1031 = io_tlu_i0_commit_cmt & _T_1030; // @[dec_tlu_ctl.scala 2283:94] - wire _T_1033 = _T_1031 & _T_1026; // @[dec_tlu_ctl.scala 2283:115] - wire _T_1034 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1036 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2284:94] - wire _T_1038 = _T_1036 & _T_1026; // @[dec_tlu_ctl.scala 2284:115] - wire _T_1039 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1041 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1043 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1045 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1047 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2288:91] - wire _T_1048 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1050 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2289:105] - wire _T_1051 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1053 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2290:91] - wire _T_1054 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1056 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2291:91] - wire _T_1057 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1060 = _T_1053 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2292:100] - wire _T_1061 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1065 = _T_1056 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2293:101] - wire _T_1066 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1068 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2294:89] - wire _T_1069 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1071 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2295:89] - wire _T_1072 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1074 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2296:89] - wire _T_1075 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1077 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2297:89] - wire _T_1078 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1080 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2298:89] - wire _T_1081 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1083 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2299:89] - wire _T_1084 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1086 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2300:89] - wire _T_1087 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1089 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2301:89] - wire _T_1090 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1092 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2302:89] - wire _T_1093 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1095 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2303:89] - wire _T_1096 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2303:122] - wire _T_1097 = _T_1095 | _T_1096; // @[dec_tlu_ctl.scala 2303:101] - wire _T_1098 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1100 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2304:95] - wire _T_1101 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1103 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2305:97] - wire _T_1104 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1106 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2306:110] - wire _T_1107 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1111 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1113 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1115 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1117 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1119 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1121 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1123 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2314:98] - wire _T_1124 = _T_1123 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2314:120] - wire _T_1125 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1127 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2315:92] - wire _T_1128 = _T_1127 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2315:117] - wire _T_1129 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1131 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1133 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1135 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2318:97] - wire _T_1136 = _T_1135 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2318:129] - wire _T_1137 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1139 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1141 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1143 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1145 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1147 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1149 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1151 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2326:34] - wire _T_1155 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2326:73] - wire _T_1156 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2327:34] - wire [5:0] _T_1163 = io_mip & mie; // @[dec_tlu_ctl.scala 2327:113] - wire _T_1164 = |_T_1163; // @[dec_tlu_ctl.scala 2327:125] - wire _T_1165 = _T_1155 & _T_1164; // @[dec_tlu_ctl.scala 2327:98] - wire _T_1166 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1168 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2328:91] - wire _T_1169 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1171 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2329:94] - wire _T_1172 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1174 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2330:94] - wire _T_1175 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2332:34] - wire _T_1177 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2333:34] - wire _T_1179 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2334:34] - wire _T_1181 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2335:34] - wire _T_1183 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2336:34] + wire _T_1018 = mhpme3 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1020 = mhpme3 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1022 = mhpme3 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1024 = mhpme3 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1026 = ~io_illegal_r; // @[dec_tlu_ctl.scala 2278:96] + wire _T_1027 = io_tlu_i0_commit_cmt & _T_1026; // @[dec_tlu_ctl.scala 2278:94] + wire _T_1028 = mhpme3 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1030 = ~io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2279:96] + wire _T_1031 = io_tlu_i0_commit_cmt & _T_1030; // @[dec_tlu_ctl.scala 2279:94] + wire _T_1033 = _T_1031 & _T_1026; // @[dec_tlu_ctl.scala 2279:115] + wire _T_1034 = mhpme3 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1036 = io_tlu_i0_commit_cmt & io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 2280:94] + wire _T_1038 = _T_1036 & _T_1026; // @[dec_tlu_ctl.scala 2280:115] + wire _T_1039 = mhpme3 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1041 = mhpme3 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1043 = mhpme3 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1045 = mhpme3 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1047 = pmu_i0_itype_qual == 4'h1; // @[dec_tlu_ctl.scala 2284:91] + wire _T_1048 = mhpme3 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1050 = io_dec_tlu_packet_r_pmu_divide & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2285:105] + wire _T_1051 = mhpme3 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1053 = pmu_i0_itype_qual == 4'h2; // @[dec_tlu_ctl.scala 2286:91] + wire _T_1054 = mhpme3 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1056 = pmu_i0_itype_qual == 4'h3; // @[dec_tlu_ctl.scala 2287:91] + wire _T_1057 = mhpme3 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1060 = _T_1053 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2288:100] + wire _T_1061 = mhpme3 == 10'he; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1065 = _T_1056 & io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 2289:101] + wire _T_1066 = mhpme3 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1068 = pmu_i0_itype_qual == 4'h4; // @[dec_tlu_ctl.scala 2290:89] + wire _T_1069 = mhpme3 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1071 = pmu_i0_itype_qual == 4'h5; // @[dec_tlu_ctl.scala 2291:89] + wire _T_1072 = mhpme3 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1074 = pmu_i0_itype_qual == 4'h6; // @[dec_tlu_ctl.scala 2292:89] + wire _T_1075 = mhpme3 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1077 = pmu_i0_itype_qual == 4'h7; // @[dec_tlu_ctl.scala 2293:89] + wire _T_1078 = mhpme3 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1080 = pmu_i0_itype_qual == 4'h8; // @[dec_tlu_ctl.scala 2294:89] + wire _T_1081 = mhpme3 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1083 = pmu_i0_itype_qual == 4'h9; // @[dec_tlu_ctl.scala 2295:89] + wire _T_1084 = mhpme3 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1086 = pmu_i0_itype_qual == 4'ha; // @[dec_tlu_ctl.scala 2296:89] + wire _T_1087 = mhpme3 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1089 = pmu_i0_itype_qual == 4'hb; // @[dec_tlu_ctl.scala 2297:89] + wire _T_1090 = mhpme3 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1092 = pmu_i0_itype_qual == 4'hc; // @[dec_tlu_ctl.scala 2298:89] + wire _T_1093 = mhpme3 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1095 = pmu_i0_itype_qual == 4'hd; // @[dec_tlu_ctl.scala 2299:89] + wire _T_1096 = pmu_i0_itype_qual == 4'he; // @[dec_tlu_ctl.scala 2299:122] + wire _T_1097 = _T_1095 | _T_1096; // @[dec_tlu_ctl.scala 2299:101] + wire _T_1098 = mhpme3 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1100 = io_exu_pmu_i0_br_misp & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2300:95] + wire _T_1101 = mhpme3 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1103 = io_exu_pmu_i0_br_ataken & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2301:97] + wire _T_1104 = mhpme3 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1106 = io_dec_tlu_packet_r_pmu_i0_br_unpred & io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 2302:110] + wire _T_1107 = mhpme3 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1111 = mhpme3 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1113 = mhpme3 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1115 = mhpme3 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1117 = mhpme3 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1119 = mhpme3 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1121 = mhpme3 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1123 = io_i0_exception_valid_r | io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 2310:98] + wire _T_1124 = _T_1123 | io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 2310:120] + wire _T_1125 = mhpme3 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1127 = io_take_timer_int | io_take_int_timer0_int; // @[dec_tlu_ctl.scala 2311:92] + wire _T_1128 = _T_1127 | io_take_int_timer1_int; // @[dec_tlu_ctl.scala 2311:117] + wire _T_1129 = mhpme3 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1131 = mhpme3 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1133 = mhpme3 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1135 = io_dec_tlu_br0_error_r | io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 2314:97] + wire _T_1136 = _T_1135 & io_rfpc_i0_r; // @[dec_tlu_ctl.scala 2314:129] + wire _T_1137 = mhpme3 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1139 = mhpme3 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1141 = mhpme3 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1143 = mhpme3 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1145 = mhpme3 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1147 = mhpme3 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1149 = mhpme3 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1151 = mhpme3 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1155 = ~io_mstatus[0]; // @[dec_tlu_ctl.scala 2322:73] + wire _T_1156 = mhpme3 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] + wire [5:0] _T_1163 = io_mip & mie; // @[dec_tlu_ctl.scala 2323:113] + wire _T_1164 = |_T_1163; // @[dec_tlu_ctl.scala 2323:125] + wire _T_1165 = _T_1155 & _T_1164; // @[dec_tlu_ctl.scala 2323:98] + wire _T_1166 = mhpme3 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1168 = pmu_i0_itype_qual == 4'hf; // @[dec_tlu_ctl.scala 2324:91] + wire _T_1169 = mhpme3 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1171 = io_tlu_i0_commit_cmt & io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 2325:94] + wire _T_1172 = mhpme3 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] + wire _T_1174 = io_tlu_i0_commit_cmt & io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 2326:94] + wire _T_1175 = mhpme3 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1177 = mhpme3 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1179 = mhpme3 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1181 = mhpme3 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1183 = mhpme3 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] wire _T_1186 = _T_1020 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] wire _T_1187 = _T_1022 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] wire _T_1188 = _T_1024 & _T_1027; // @[Mux.scala 27:72] @@ -51611,65 +51609,65 @@ module csr_tlu( wire _T_1295 = _T_1294 | _T_1239; // @[Mux.scala 27:72] wire _T_1296 = _T_1295 | _T_1240; // @[Mux.scala 27:72] wire _T_1297 = _T_1296 | _T_1241; // @[Mux.scala 27:72] - wire mhpmc_inc_r_0 = _T_1017 & _T_1297; // @[dec_tlu_ctl.scala 2278:44] - wire _T_1301 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2278:24] + wire mhpmc_inc_r_0 = _T_1017 & _T_1297; // @[dec_tlu_ctl.scala 2274:44] + wire _T_1301 = ~mcountinhibit[4]; // @[dec_tlu_ctl.scala 2274:24] reg [9:0] mhpme4; // @[Reg.scala 27:20] - wire _T_1302 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1304 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1306 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1308 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1312 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1318 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1323 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1325 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1327 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1329 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1332 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1335 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1338 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1341 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1345 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1350 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1353 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1356 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1359 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1362 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1365 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1368 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1371 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1374 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1377 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1382 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1385 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1388 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1391 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1395 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1397 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1399 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1401 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1403 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1405 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1409 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1413 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1415 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1417 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1421 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1423 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1425 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1427 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1429 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1431 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1433 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1435 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2326:34] - wire _T_1440 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2327:34] - wire _T_1450 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1453 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1456 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1459 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2332:34] - wire _T_1461 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2333:34] - wire _T_1463 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2334:34] - wire _T_1465 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2335:34] - wire _T_1467 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2336:34] + wire _T_1302 = mhpme4 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1304 = mhpme4 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1306 = mhpme4 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1308 = mhpme4 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1312 = mhpme4 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1318 = mhpme4 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1323 = mhpme4 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1325 = mhpme4 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1327 = mhpme4 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1329 = mhpme4 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1332 = mhpme4 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1335 = mhpme4 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1338 = mhpme4 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1341 = mhpme4 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1345 = mhpme4 == 10'he; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1350 = mhpme4 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1353 = mhpme4 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1356 = mhpme4 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1359 = mhpme4 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1362 = mhpme4 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1365 = mhpme4 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1368 = mhpme4 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1371 = mhpme4 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1374 = mhpme4 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1377 = mhpme4 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1382 = mhpme4 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1385 = mhpme4 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1388 = mhpme4 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1391 = mhpme4 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1395 = mhpme4 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1397 = mhpme4 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1399 = mhpme4 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1401 = mhpme4 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1403 = mhpme4 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1405 = mhpme4 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1409 = mhpme4 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1413 = mhpme4 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1415 = mhpme4 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1417 = mhpme4 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1421 = mhpme4 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1423 = mhpme4 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1425 = mhpme4 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1427 = mhpme4 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1429 = mhpme4 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1431 = mhpme4 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1433 = mhpme4 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1435 = mhpme4 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1440 = mhpme4 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1450 = mhpme4 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1453 = mhpme4 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1456 = mhpme4 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] + wire _T_1459 = mhpme4 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1461 = mhpme4 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1463 = mhpme4 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1465 = mhpme4 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1467 = mhpme4 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] wire _T_1470 = _T_1304 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] wire _T_1471 = _T_1306 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] wire _T_1472 = _T_1308 & _T_1027; // @[Mux.scala 27:72] @@ -51781,65 +51779,65 @@ module csr_tlu( wire _T_1579 = _T_1578 | _T_1523; // @[Mux.scala 27:72] wire _T_1580 = _T_1579 | _T_1524; // @[Mux.scala 27:72] wire _T_1581 = _T_1580 | _T_1525; // @[Mux.scala 27:72] - wire mhpmc_inc_r_1 = _T_1301 & _T_1581; // @[dec_tlu_ctl.scala 2278:44] - wire _T_1585 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2278:24] + wire mhpmc_inc_r_1 = _T_1301 & _T_1581; // @[dec_tlu_ctl.scala 2274:44] + wire _T_1585 = ~mcountinhibit[5]; // @[dec_tlu_ctl.scala 2274:24] reg [9:0] mhpme5; // @[Reg.scala 27:20] - wire _T_1586 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1588 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1590 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1592 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1596 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1602 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1607 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1609 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1611 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1613 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1616 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1619 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1622 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1625 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1629 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1634 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1637 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1640 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1643 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1646 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1649 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1652 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1655 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1658 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1661 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1666 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1669 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1672 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1675 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1679 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1681 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1683 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1685 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1687 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1689 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1693 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1697 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1699 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1701 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1705 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1707 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1709 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1711 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1713 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1715 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2324:34] - wire _T_1717 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2325:34] - wire _T_1719 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2326:34] - wire _T_1724 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2327:34] - wire _T_1734 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2328:34] - wire _T_1737 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2329:34] - wire _T_1740 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2330:34] - wire _T_1743 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2332:34] - wire _T_1745 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2333:34] - wire _T_1747 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2334:34] - wire _T_1749 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2335:34] - wire _T_1751 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2336:34] + wire _T_1586 = mhpme5 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1588 = mhpme5 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1590 = mhpme5 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1592 = mhpme5 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1596 = mhpme5 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1602 = mhpme5 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1607 = mhpme5 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1609 = mhpme5 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1611 = mhpme5 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1613 = mhpme5 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1616 = mhpme5 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1619 = mhpme5 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1622 = mhpme5 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1625 = mhpme5 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1629 = mhpme5 == 10'he; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1634 = mhpme5 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1637 = mhpme5 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1640 = mhpme5 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1643 = mhpme5 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1646 = mhpme5 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1649 = mhpme5 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1652 = mhpme5 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1655 = mhpme5 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1658 = mhpme5 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1661 = mhpme5 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1666 = mhpme5 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1669 = mhpme5 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1672 = mhpme5 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1675 = mhpme5 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1679 = mhpme5 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1681 = mhpme5 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1683 = mhpme5 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1685 = mhpme5 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1687 = mhpme5 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1689 = mhpme5 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1693 = mhpme5 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1697 = mhpme5 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1699 = mhpme5 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1701 = mhpme5 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1705 = mhpme5 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1707 = mhpme5 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1709 = mhpme5 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1711 = mhpme5 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1713 = mhpme5 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1715 = mhpme5 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] + wire _T_1717 = mhpme5 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] + wire _T_1719 = mhpme5 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] + wire _T_1724 = mhpme5 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] + wire _T_1734 = mhpme5 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] + wire _T_1737 = mhpme5 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] + wire _T_1740 = mhpme5 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] + wire _T_1743 = mhpme5 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] + wire _T_1745 = mhpme5 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] + wire _T_1747 = mhpme5 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] + wire _T_1749 = mhpme5 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] + wire _T_1751 = mhpme5 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] wire _T_1754 = _T_1588 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] wire _T_1755 = _T_1590 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] wire _T_1756 = _T_1592 & _T_1027; // @[Mux.scala 27:72] @@ -51951,65 +51949,65 @@ module csr_tlu( wire _T_1863 = _T_1862 | _T_1807; // @[Mux.scala 27:72] wire _T_1864 = _T_1863 | _T_1808; // @[Mux.scala 27:72] wire _T_1865 = _T_1864 | _T_1809; // @[Mux.scala 27:72] - wire mhpmc_inc_r_2 = _T_1585 & _T_1865; // @[dec_tlu_ctl.scala 2278:44] - wire _T_1869 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2278:24] + wire mhpmc_inc_r_2 = _T_1585 & _T_1865; // @[dec_tlu_ctl.scala 2274:44] + wire _T_1869 = ~mcountinhibit[6]; // @[dec_tlu_ctl.scala 2274:24] reg [9:0] mhpme6; // @[Reg.scala 27:20] - wire _T_1870 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2279:34] - wire _T_1872 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2280:34] - wire _T_1874 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2281:34] - wire _T_1876 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2282:34] - wire _T_1880 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2283:34] - wire _T_1886 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2284:34] - wire _T_1891 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2285:34] - wire _T_1893 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2286:34] - wire _T_1895 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2287:34] - wire _T_1897 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2288:34] - wire _T_1900 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2289:34] - wire _T_1903 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2290:34] - wire _T_1906 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2291:34] - wire _T_1909 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2292:34] - wire _T_1913 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2293:34] - wire _T_1918 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2294:34] - wire _T_1921 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2295:34] - wire _T_1924 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2296:34] - wire _T_1927 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2297:34] - wire _T_1930 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2298:34] - wire _T_1933 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2299:34] - wire _T_1936 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2300:34] - wire _T_1939 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2301:34] - wire _T_1942 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2302:34] - wire _T_1945 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2303:34] - wire _T_1950 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2304:34] - wire _T_1953 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2305:34] - wire _T_1956 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2306:34] - wire _T_1959 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2307:34] - wire _T_1963 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2309:34] - wire _T_1965 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2310:34] - wire _T_1967 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2311:34] - wire _T_1969 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2312:34] - wire _T_1971 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2313:34] - wire _T_1973 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2314:34] - wire _T_1977 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2315:34] - wire _T_1981 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2316:34] - wire _T_1983 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2317:34] - wire _T_1985 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2318:34] - wire _T_1989 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2319:34] - wire _T_1991 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2320:34] - wire _T_1993 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2321:34] - wire _T_1995 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2322:34] - wire _T_1997 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2323:34] - wire _T_1999 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2324:34] - wire _T_2001 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2325:34] - wire _T_2003 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2326:34] - wire _T_2008 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2327:34] - wire _T_2018 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2328:34] - wire _T_2021 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2329:34] - wire _T_2024 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2330:34] - wire _T_2027 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2332:34] - wire _T_2029 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2333:34] - wire _T_2031 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2334:34] - wire _T_2033 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2335:34] - wire _T_2035 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2336:34] + wire _T_1870 = mhpme6 == 10'h1; // @[dec_tlu_ctl.scala 2275:34] + wire _T_1872 = mhpme6 == 10'h2; // @[dec_tlu_ctl.scala 2276:34] + wire _T_1874 = mhpme6 == 10'h3; // @[dec_tlu_ctl.scala 2277:34] + wire _T_1876 = mhpme6 == 10'h4; // @[dec_tlu_ctl.scala 2278:34] + wire _T_1880 = mhpme6 == 10'h5; // @[dec_tlu_ctl.scala 2279:34] + wire _T_1886 = mhpme6 == 10'h6; // @[dec_tlu_ctl.scala 2280:34] + wire _T_1891 = mhpme6 == 10'h7; // @[dec_tlu_ctl.scala 2281:34] + wire _T_1893 = mhpme6 == 10'h8; // @[dec_tlu_ctl.scala 2282:34] + wire _T_1895 = mhpme6 == 10'h1e; // @[dec_tlu_ctl.scala 2283:34] + wire _T_1897 = mhpme6 == 10'h9; // @[dec_tlu_ctl.scala 2284:34] + wire _T_1900 = mhpme6 == 10'ha; // @[dec_tlu_ctl.scala 2285:34] + wire _T_1903 = mhpme6 == 10'hb; // @[dec_tlu_ctl.scala 2286:34] + wire _T_1906 = mhpme6 == 10'hc; // @[dec_tlu_ctl.scala 2287:34] + wire _T_1909 = mhpme6 == 10'hd; // @[dec_tlu_ctl.scala 2288:34] + wire _T_1913 = mhpme6 == 10'he; // @[dec_tlu_ctl.scala 2289:34] + wire _T_1918 = mhpme6 == 10'hf; // @[dec_tlu_ctl.scala 2290:34] + wire _T_1921 = mhpme6 == 10'h10; // @[dec_tlu_ctl.scala 2291:34] + wire _T_1924 = mhpme6 == 10'h12; // @[dec_tlu_ctl.scala 2292:34] + wire _T_1927 = mhpme6 == 10'h11; // @[dec_tlu_ctl.scala 2293:34] + wire _T_1930 = mhpme6 == 10'h13; // @[dec_tlu_ctl.scala 2294:34] + wire _T_1933 = mhpme6 == 10'h14; // @[dec_tlu_ctl.scala 2295:34] + wire _T_1936 = mhpme6 == 10'h15; // @[dec_tlu_ctl.scala 2296:34] + wire _T_1939 = mhpme6 == 10'h16; // @[dec_tlu_ctl.scala 2297:34] + wire _T_1942 = mhpme6 == 10'h17; // @[dec_tlu_ctl.scala 2298:34] + wire _T_1945 = mhpme6 == 10'h18; // @[dec_tlu_ctl.scala 2299:34] + wire _T_1950 = mhpme6 == 10'h19; // @[dec_tlu_ctl.scala 2300:34] + wire _T_1953 = mhpme6 == 10'h1a; // @[dec_tlu_ctl.scala 2301:34] + wire _T_1956 = mhpme6 == 10'h1b; // @[dec_tlu_ctl.scala 2302:34] + wire _T_1959 = mhpme6 == 10'h1c; // @[dec_tlu_ctl.scala 2303:34] + wire _T_1963 = mhpme6 == 10'h1f; // @[dec_tlu_ctl.scala 2305:34] + wire _T_1965 = mhpme6 == 10'h20; // @[dec_tlu_ctl.scala 2306:34] + wire _T_1967 = mhpme6 == 10'h22; // @[dec_tlu_ctl.scala 2307:34] + wire _T_1969 = mhpme6 == 10'h23; // @[dec_tlu_ctl.scala 2308:34] + wire _T_1971 = mhpme6 == 10'h24; // @[dec_tlu_ctl.scala 2309:34] + wire _T_1973 = mhpme6 == 10'h25; // @[dec_tlu_ctl.scala 2310:34] + wire _T_1977 = mhpme6 == 10'h26; // @[dec_tlu_ctl.scala 2311:34] + wire _T_1981 = mhpme6 == 10'h27; // @[dec_tlu_ctl.scala 2312:34] + wire _T_1983 = mhpme6 == 10'h28; // @[dec_tlu_ctl.scala 2313:34] + wire _T_1985 = mhpme6 == 10'h29; // @[dec_tlu_ctl.scala 2314:34] + wire _T_1989 = mhpme6 == 10'h2a; // @[dec_tlu_ctl.scala 2315:34] + wire _T_1991 = mhpme6 == 10'h2b; // @[dec_tlu_ctl.scala 2316:34] + wire _T_1993 = mhpme6 == 10'h2c; // @[dec_tlu_ctl.scala 2317:34] + wire _T_1995 = mhpme6 == 10'h2d; // @[dec_tlu_ctl.scala 2318:34] + wire _T_1997 = mhpme6 == 10'h2e; // @[dec_tlu_ctl.scala 2319:34] + wire _T_1999 = mhpme6 == 10'h2f; // @[dec_tlu_ctl.scala 2320:34] + wire _T_2001 = mhpme6 == 10'h30; // @[dec_tlu_ctl.scala 2321:34] + wire _T_2003 = mhpme6 == 10'h31; // @[dec_tlu_ctl.scala 2322:34] + wire _T_2008 = mhpme6 == 10'h32; // @[dec_tlu_ctl.scala 2323:34] + wire _T_2018 = mhpme6 == 10'h36; // @[dec_tlu_ctl.scala 2324:34] + wire _T_2021 = mhpme6 == 10'h37; // @[dec_tlu_ctl.scala 2325:34] + wire _T_2024 = mhpme6 == 10'h38; // @[dec_tlu_ctl.scala 2326:34] + wire _T_2027 = mhpme6 == 10'h200; // @[dec_tlu_ctl.scala 2328:34] + wire _T_2029 = mhpme6 == 10'h201; // @[dec_tlu_ctl.scala 2329:34] + wire _T_2031 = mhpme6 == 10'h202; // @[dec_tlu_ctl.scala 2330:34] + wire _T_2033 = mhpme6 == 10'h203; // @[dec_tlu_ctl.scala 2331:34] + wire _T_2035 = mhpme6 == 10'h204; // @[dec_tlu_ctl.scala 2332:34] wire _T_2038 = _T_1872 & io_ifu_pmu_ic_hit; // @[Mux.scala 27:72] wire _T_2039 = _T_1874 & io_ifu_pmu_ic_miss; // @[Mux.scala 27:72] wire _T_2040 = _T_1876 & _T_1027; // @[Mux.scala 27:72] @@ -52121,103 +52119,103 @@ module csr_tlu( wire _T_2147 = _T_2146 | _T_2091; // @[Mux.scala 27:72] wire _T_2148 = _T_2147 | _T_2092; // @[Mux.scala 27:72] wire _T_2149 = _T_2148 | _T_2093; // @[Mux.scala 27:72] - wire mhpmc_inc_r_3 = _T_1869 & _T_2149; // @[dec_tlu_ctl.scala 2278:44] - reg mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2339:53] - reg mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2340:53] - reg mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2341:53] - reg mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2342:53] - reg perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2343:56] - wire perfcnt_halted = _T_85 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2346:67] - wire _T_2161 = ~_T_85; // @[dec_tlu_ctl.scala 2347:37] + wire mhpmc_inc_r_3 = _T_1869 & _T_2149; // @[dec_tlu_ctl.scala 2274:44] + reg mhpmc_inc_r_d1_0; // @[dec_tlu_ctl.scala 2335:53] + reg mhpmc_inc_r_d1_1; // @[dec_tlu_ctl.scala 2336:53] + reg mhpmc_inc_r_d1_2; // @[dec_tlu_ctl.scala 2337:53] + reg mhpmc_inc_r_d1_3; // @[dec_tlu_ctl.scala 2338:53] + reg perfcnt_halted_d1; // @[dec_tlu_ctl.scala 2339:56] + wire perfcnt_halted = _T_85 | io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 2342:67] + wire _T_2161 = ~_T_85; // @[dec_tlu_ctl.scala 2343:37] wire [3:0] _T_2163 = _T_2161 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] wire [3:0] _T_2170 = {mhpme6[9],mhpme5[9],mhpme4[9],mhpme3[9]}; // @[Cat.scala 29:58] - wire [3:0] perfcnt_during_sleep = _T_2163 & _T_2170; // @[dec_tlu_ctl.scala 2347:86] - wire _T_2172 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2349:67] - wire _T_2173 = perfcnt_halted_d1 & _T_2172; // @[dec_tlu_ctl.scala 2349:65] - wire _T_2174 = ~_T_2173; // @[dec_tlu_ctl.scala 2349:45] - wire _T_2177 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2350:67] - wire _T_2178 = perfcnt_halted_d1 & _T_2177; // @[dec_tlu_ctl.scala 2350:65] - wire _T_2179 = ~_T_2178; // @[dec_tlu_ctl.scala 2350:45] - wire _T_2182 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2351:67] - wire _T_2183 = perfcnt_halted_d1 & _T_2182; // @[dec_tlu_ctl.scala 2351:65] - wire _T_2184 = ~_T_2183; // @[dec_tlu_ctl.scala 2351:45] - wire _T_2187 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2352:67] - wire _T_2188 = perfcnt_halted_d1 & _T_2187; // @[dec_tlu_ctl.scala 2352:65] - wire _T_2189 = ~_T_2188; // @[dec_tlu_ctl.scala 2352:45] - wire _T_2192 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2358:72] - wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2192; // @[dec_tlu_ctl.scala 2358:43] - wire _T_2193 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2359:23] - wire _T_2195 = _T_2193 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2359:39] - wire _T_2196 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2359:86] - wire mhpmc3_wr_en1 = _T_2195 & _T_2196; // @[dec_tlu_ctl.scala 2359:66] + wire [3:0] perfcnt_during_sleep = _T_2163 & _T_2170; // @[dec_tlu_ctl.scala 2343:86] + wire _T_2172 = ~perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2345:67] + wire _T_2173 = perfcnt_halted_d1 & _T_2172; // @[dec_tlu_ctl.scala 2345:65] + wire _T_2174 = ~_T_2173; // @[dec_tlu_ctl.scala 2345:45] + wire _T_2177 = ~perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2346:67] + wire _T_2178 = perfcnt_halted_d1 & _T_2177; // @[dec_tlu_ctl.scala 2346:65] + wire _T_2179 = ~_T_2178; // @[dec_tlu_ctl.scala 2346:45] + wire _T_2182 = ~perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2347:67] + wire _T_2183 = perfcnt_halted_d1 & _T_2182; // @[dec_tlu_ctl.scala 2347:65] + wire _T_2184 = ~_T_2183; // @[dec_tlu_ctl.scala 2347:45] + wire _T_2187 = ~perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2348:67] + wire _T_2188 = perfcnt_halted_d1 & _T_2187; // @[dec_tlu_ctl.scala 2348:65] + wire _T_2189 = ~_T_2188; // @[dec_tlu_ctl.scala 2348:45] + wire _T_2192 = io_dec_csr_wraddr_r == 12'hb03; // @[dec_tlu_ctl.scala 2354:72] + wire mhpmc3_wr_en0 = io_dec_csr_wen_r_mod & _T_2192; // @[dec_tlu_ctl.scala 2354:43] + wire _T_2193 = ~perfcnt_halted; // @[dec_tlu_ctl.scala 2355:23] + wire _T_2195 = _T_2193 | perfcnt_during_sleep[0]; // @[dec_tlu_ctl.scala 2355:39] + wire _T_2196 = |mhpmc_inc_r_0; // @[dec_tlu_ctl.scala 2355:86] + wire mhpmc3_wr_en1 = _T_2195 & _T_2196; // @[dec_tlu_ctl.scala 2355:66] reg [31:0] mhpmc3h; // @[lib.scala 358:16] reg [31:0] mhpmc3; // @[lib.scala 358:16] wire [63:0] _T_2199 = {mhpmc3h,mhpmc3}; // @[Cat.scala 29:58] wire [63:0] _T_2200 = {63'h0,mhpmc_inc_r_0}; // @[Cat.scala 29:58] - wire [63:0] mhpmc3_incr = _T_2199 + _T_2200; // @[dec_tlu_ctl.scala 2363:49] - wire _T_2208 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2368:73] - wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2208; // @[dec_tlu_ctl.scala 2368:44] - wire _T_2214 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2377:72] - wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2214; // @[dec_tlu_ctl.scala 2377:43] - wire _T_2217 = _T_2193 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2378:39] - wire _T_2218 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2378:86] - wire mhpmc4_wr_en1 = _T_2217 & _T_2218; // @[dec_tlu_ctl.scala 2378:66] + wire [63:0] mhpmc3_incr = _T_2199 + _T_2200; // @[dec_tlu_ctl.scala 2359:49] + wire _T_2208 = io_dec_csr_wraddr_r == 12'hb83; // @[dec_tlu_ctl.scala 2364:73] + wire mhpmc3h_wr_en0 = io_dec_csr_wen_r_mod & _T_2208; // @[dec_tlu_ctl.scala 2364:44] + wire _T_2214 = io_dec_csr_wraddr_r == 12'hb04; // @[dec_tlu_ctl.scala 2373:72] + wire mhpmc4_wr_en0 = io_dec_csr_wen_r_mod & _T_2214; // @[dec_tlu_ctl.scala 2373:43] + wire _T_2217 = _T_2193 | perfcnt_during_sleep[1]; // @[dec_tlu_ctl.scala 2374:39] + wire _T_2218 = |mhpmc_inc_r_1; // @[dec_tlu_ctl.scala 2374:86] + wire mhpmc4_wr_en1 = _T_2217 & _T_2218; // @[dec_tlu_ctl.scala 2374:66] reg [31:0] mhpmc4h; // @[lib.scala 358:16] reg [31:0] mhpmc4; // @[lib.scala 358:16] wire [63:0] _T_2221 = {mhpmc4h,mhpmc4}; // @[Cat.scala 29:58] wire [63:0] _T_2222 = {63'h0,mhpmc_inc_r_1}; // @[Cat.scala 29:58] - wire [63:0] mhpmc4_incr = _T_2221 + _T_2222; // @[dec_tlu_ctl.scala 2383:49] - wire _T_2231 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2387:73] - wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2231; // @[dec_tlu_ctl.scala 2387:44] - wire _T_2237 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2396:72] - wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2237; // @[dec_tlu_ctl.scala 2396:43] - wire _T_2240 = _T_2193 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2397:39] - wire _T_2241 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2397:86] - wire mhpmc5_wr_en1 = _T_2240 & _T_2241; // @[dec_tlu_ctl.scala 2397:66] + wire [63:0] mhpmc4_incr = _T_2221 + _T_2222; // @[dec_tlu_ctl.scala 2379:49] + wire _T_2231 = io_dec_csr_wraddr_r == 12'hb84; // @[dec_tlu_ctl.scala 2383:73] + wire mhpmc4h_wr_en0 = io_dec_csr_wen_r_mod & _T_2231; // @[dec_tlu_ctl.scala 2383:44] + wire _T_2237 = io_dec_csr_wraddr_r == 12'hb05; // @[dec_tlu_ctl.scala 2392:72] + wire mhpmc5_wr_en0 = io_dec_csr_wen_r_mod & _T_2237; // @[dec_tlu_ctl.scala 2392:43] + wire _T_2240 = _T_2193 | perfcnt_during_sleep[2]; // @[dec_tlu_ctl.scala 2393:39] + wire _T_2241 = |mhpmc_inc_r_2; // @[dec_tlu_ctl.scala 2393:86] + wire mhpmc5_wr_en1 = _T_2240 & _T_2241; // @[dec_tlu_ctl.scala 2393:66] reg [31:0] mhpmc5h; // @[lib.scala 358:16] reg [31:0] mhpmc5; // @[lib.scala 358:16] wire [63:0] _T_2244 = {mhpmc5h,mhpmc5}; // @[Cat.scala 29:58] wire [63:0] _T_2245 = {63'h0,mhpmc_inc_r_2}; // @[Cat.scala 29:58] - wire [63:0] mhpmc5_incr = _T_2244 + _T_2245; // @[dec_tlu_ctl.scala 2400:49] - wire _T_2253 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2405:73] - wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2253; // @[dec_tlu_ctl.scala 2405:44] - wire _T_2259 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2414:72] - wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2259; // @[dec_tlu_ctl.scala 2414:43] - wire _T_2262 = _T_2193 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2415:39] - wire _T_2263 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2415:86] - wire mhpmc6_wr_en1 = _T_2262 & _T_2263; // @[dec_tlu_ctl.scala 2415:66] + wire [63:0] mhpmc5_incr = _T_2244 + _T_2245; // @[dec_tlu_ctl.scala 2396:49] + wire _T_2253 = io_dec_csr_wraddr_r == 12'hb85; // @[dec_tlu_ctl.scala 2401:73] + wire mhpmc5h_wr_en0 = io_dec_csr_wen_r_mod & _T_2253; // @[dec_tlu_ctl.scala 2401:44] + wire _T_2259 = io_dec_csr_wraddr_r == 12'hb06; // @[dec_tlu_ctl.scala 2410:72] + wire mhpmc6_wr_en0 = io_dec_csr_wen_r_mod & _T_2259; // @[dec_tlu_ctl.scala 2410:43] + wire _T_2262 = _T_2193 | perfcnt_during_sleep[3]; // @[dec_tlu_ctl.scala 2411:39] + wire _T_2263 = |mhpmc_inc_r_3; // @[dec_tlu_ctl.scala 2411:86] + wire mhpmc6_wr_en1 = _T_2262 & _T_2263; // @[dec_tlu_ctl.scala 2411:66] reg [31:0] mhpmc6h; // @[lib.scala 358:16] reg [31:0] mhpmc6; // @[lib.scala 358:16] wire [63:0] _T_2266 = {mhpmc6h,mhpmc6}; // @[Cat.scala 29:58] wire [63:0] _T_2267 = {63'h0,mhpmc_inc_r_3}; // @[Cat.scala 29:58] - wire [63:0] mhpmc6_incr = _T_2266 + _T_2267; // @[dec_tlu_ctl.scala 2418:49] - wire _T_2275 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2423:73] - wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2275; // @[dec_tlu_ctl.scala 2423:44] - wire _T_2281 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2434:56] - wire _T_2283 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2434:102] - wire _T_2284 = _T_2281 | _T_2283; // @[dec_tlu_ctl.scala 2434:71] - wire _T_2287 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2436:70] - wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2287; // @[dec_tlu_ctl.scala 2436:41] - wire _T_2291 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2443:70] - wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2291; // @[dec_tlu_ctl.scala 2443:41] - wire _T_2295 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2450:70] - wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2295; // @[dec_tlu_ctl.scala 2450:41] - wire _T_2299 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2457:70] - wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2299; // @[dec_tlu_ctl.scala 2457:41] - wire _T_2303 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2474:77] - wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2303; // @[dec_tlu_ctl.scala 2474:48] - wire _T_2315 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2489:51] - wire _T_2316 = _T_2315 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2489:78] - wire _T_2317 = _T_2316 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2489:104] - wire _T_2318 = _T_2317 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2489:130] - wire _T_2319 = _T_2318 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2490:32] - reg _T_2322; // @[dec_tlu_ctl.scala 2492:62] - wire _T_2323 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2493:91] - wire _T_2324 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2493:137] - wire _T_2325 = io_trigger_hit_r_d1 & _T_2324; // @[dec_tlu_ctl.scala 2493:135] - reg _T_2327; // @[dec_tlu_ctl.scala 2493:62] - reg [4:0] _T_2328; // @[dec_tlu_ctl.scala 2494:62] - reg _T_2329; // @[dec_tlu_ctl.scala 2495:62] + wire [63:0] mhpmc6_incr = _T_2266 + _T_2267; // @[dec_tlu_ctl.scala 2414:49] + wire _T_2275 = io_dec_csr_wraddr_r == 12'hb86; // @[dec_tlu_ctl.scala 2419:73] + wire mhpmc6h_wr_en0 = io_dec_csr_wen_r_mod & _T_2275; // @[dec_tlu_ctl.scala 2419:44] + wire _T_2281 = io_dec_csr_wrdata_r[9:0] > 10'h204; // @[dec_tlu_ctl.scala 2430:56] + wire _T_2283 = |io_dec_csr_wrdata_r[31:10]; // @[dec_tlu_ctl.scala 2430:102] + wire _T_2284 = _T_2281 | _T_2283; // @[dec_tlu_ctl.scala 2430:71] + wire _T_2287 = io_dec_csr_wraddr_r == 12'h323; // @[dec_tlu_ctl.scala 2432:70] + wire wr_mhpme3_r = io_dec_csr_wen_r_mod & _T_2287; // @[dec_tlu_ctl.scala 2432:41] + wire _T_2291 = io_dec_csr_wraddr_r == 12'h324; // @[dec_tlu_ctl.scala 2439:70] + wire wr_mhpme4_r = io_dec_csr_wen_r_mod & _T_2291; // @[dec_tlu_ctl.scala 2439:41] + wire _T_2295 = io_dec_csr_wraddr_r == 12'h325; // @[dec_tlu_ctl.scala 2446:70] + wire wr_mhpme5_r = io_dec_csr_wen_r_mod & _T_2295; // @[dec_tlu_ctl.scala 2446:41] + wire _T_2299 = io_dec_csr_wraddr_r == 12'h326; // @[dec_tlu_ctl.scala 2453:70] + wire wr_mhpme6_r = io_dec_csr_wen_r_mod & _T_2299; // @[dec_tlu_ctl.scala 2453:41] + wire _T_2303 = io_dec_csr_wraddr_r == 12'h320; // @[dec_tlu_ctl.scala 2470:77] + wire wr_mcountinhibit_r = io_dec_csr_wen_r_mod & _T_2303; // @[dec_tlu_ctl.scala 2470:48] + wire _T_2315 = io_i0_valid_wb | io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 2485:51] + wire _T_2316 = _T_2315 | io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 2485:78] + wire _T_2317 = _T_2316 | io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 2485:104] + wire _T_2318 = _T_2317 | io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 2485:130] + wire _T_2319 = _T_2318 | io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 2486:32] + reg _T_2322; // @[dec_tlu_ctl.scala 2488:62] + wire _T_2323 = io_i0_exception_valid_r_d1 | io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 2489:91] + wire _T_2324 = ~io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 2489:137] + wire _T_2325 = io_trigger_hit_r_d1 & _T_2324; // @[dec_tlu_ctl.scala 2489:135] + reg _T_2327; // @[dec_tlu_ctl.scala 2489:62] + reg [4:0] _T_2328; // @[dec_tlu_ctl.scala 2490:62] + reg _T_2329; // @[dec_tlu_ctl.scala 2491:62] wire [31:0] _T_2335 = {io_core_id,4'h0}; // @[Cat.scala 29:58] wire [31:0] _T_2344 = {21'h3,3'h0,io_mstatus[1],3'h0,io_mstatus[0],3'h0}; // @[Cat.scala 29:58] wire [31:0] _T_2349 = {io_mtvec[30:1],1'h0,io_mtvec[0]}; // @[Cat.scala 29:58] @@ -52247,7 +52245,7 @@ module csr_tlu( wire [31:0] _T_2496 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2497 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2498 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_2499 = io_csr_pkt_csr_mimpid ? 32'h2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_2499 = io_csr_pkt_csr_mimpid ? 32'h1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2500 = io_csr_pkt_csr_mhartid ? _T_2335 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2501 = io_csr_pkt_csr_mstatus ? _T_2344 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2502 = io_csr_pkt_csr_mtvec ? _T_2349 : 32'h0; // @[Mux.scala 27:72] @@ -52564,85 +52562,84 @@ module csr_tlu( .io_en(rvclkhdr_34_io_en), .io_scan_mode(rvclkhdr_34_io_scan_mode) ); - assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {{1'd0}, _T_756}; // @[dec_tlu_ctl.scala 2160:47] - assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2162:41] - assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[dec_tlu_ctl.scala 2170:41] - assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[dec_tlu_ctl.scala 2171:41] - assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[dec_tlu_ctl.scala 2235:40] - assign io_trigger_pkt_any_0_match_pkt = io_mtdata1_t_0[4]; // @[dec_tlu_ctl.scala 2236:43] - assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[dec_tlu_ctl.scala 2237:40] - assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[dec_tlu_ctl.scala 2238:40] - assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[dec_tlu_ctl.scala 2239:40] - assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 2240:40] - assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[dec_tlu_ctl.scala 2253:51] - assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[dec_tlu_ctl.scala 2235:40] - assign io_trigger_pkt_any_1_match_pkt = io_mtdata1_t_1[4]; // @[dec_tlu_ctl.scala 2236:43] - assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[dec_tlu_ctl.scala 2237:40] - assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[dec_tlu_ctl.scala 2238:40] - assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[dec_tlu_ctl.scala 2239:40] - assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 2240:40] - assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[dec_tlu_ctl.scala 2253:51] - assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[dec_tlu_ctl.scala 2235:40] - assign io_trigger_pkt_any_2_match_pkt = io_mtdata1_t_2[4]; // @[dec_tlu_ctl.scala 2236:43] - assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[dec_tlu_ctl.scala 2237:40] - assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[dec_tlu_ctl.scala 2238:40] - assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[dec_tlu_ctl.scala 2239:40] - assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 2240:40] - assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[dec_tlu_ctl.scala 2253:51] - assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[dec_tlu_ctl.scala 2235:40] - assign io_trigger_pkt_any_3_match_pkt = io_mtdata1_t_3[4]; // @[dec_tlu_ctl.scala 2236:43] - assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[dec_tlu_ctl.scala 2237:40] - assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[dec_tlu_ctl.scala 2238:40] - assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2239:40] - assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2240:40] - assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2253:51] - assign io_dec_tlu_int_valid_wb1 = _T_2329; // @[dec_tlu_ctl.scala 2495:30] - assign io_dec_tlu_i0_exc_valid_wb1 = _T_2327; // @[dec_tlu_ctl.scala 2493:30] - assign io_dec_tlu_i0_valid_wb1 = _T_2322; // @[dec_tlu_ctl.scala 2492:30] - assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2497:24] - assign io_dec_tlu_exc_cause_wb1 = _T_2328; // @[dec_tlu_ctl.scala 2494:30] - assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2174; // @[dec_tlu_ctl.scala 2349:22] - assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2179; // @[dec_tlu_ctl.scala 2350:22] - assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2184; // @[dec_tlu_ctl.scala 2351:22] - assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2189; // @[dec_tlu_ctl.scala 2352:22] - assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1722:31] - assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1723:31] - assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1725:31] - assign io_dec_tlu_bus_clk_override = mcgc[3]; // @[dec_tlu_ctl.scala 1726:31] - assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1727:31] - assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1728:31] - assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1729:31] - assign io_dec_csr_rddata_d = _T_2605 | _T_2551; // @[dec_tlu_ctl.scala 2502:21] - assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1772:39] - assign io_dec_tlu_wr_pause_r = _T_360 & _T_361; // @[dec_tlu_ctl.scala 1781:24] - assign io_dec_tlu_meipt = meipt; // @[dec_tlu_ctl.scala 2010:19] - assign io_dec_tlu_meicurpl = meicurpl; // @[dec_tlu_ctl.scala 1974:22] - assign io_dec_tlu_meihap = {meivt,meihap}; // @[dec_tlu_ctl.scala 1960:20] - assign io_dec_tlu_mrac_ff = mrac; // @[dec_tlu_ctl.scala 1811:21] - assign io_dec_tlu_wb_coalescing_disable = mfdc[2]; // @[dec_tlu_ctl.scala 1771:39] - assign io_dec_tlu_bpred_disable = mfdc[3]; // @[dec_tlu_ctl.scala 1770:39] - assign io_dec_tlu_sideeffect_posted_disable = mfdc[6]; // @[dec_tlu_ctl.scala 1769:39] - assign io_dec_tlu_core_ecc_disable = mfdc[8]; // @[dec_tlu_ctl.scala 1768:39] - assign io_dec_tlu_external_ldfwd_disable = mfdc[11]; // @[dec_tlu_ctl.scala 1767:39] - assign io_dec_tlu_dma_qos_prty = mfdc[18:16]; // @[dec_tlu_ctl.scala 1766:39] - assign io_dec_csr_wen_r_mod = _T_1 & _T_2; // @[dec_tlu_ctl.scala 1455:23] - assign io_fw_halt_req = _T_492 & _T_493; // @[dec_tlu_ctl.scala 1846:17] - assign io_mstatus = _T_56; // @[dec_tlu_ctl.scala 1471:13] - assign io_mstatus_mie_ns = io_mstatus[0] & _T_54; // @[dec_tlu_ctl.scala 1470:20] - assign io_dcsr = _T_691; // @[dec_tlu_ctl.scala 2057:10] - assign io_mtvec = _T_62; // @[dec_tlu_ctl.scala 1483:11] - assign io_mip = _T_68; // @[dec_tlu_ctl.scala 1498:9] - assign io_mie_ns = wr_mie_r ? _T_78 : mie; // @[dec_tlu_ctl.scala 1512:12] - assign io_npc_r = _T_161 | _T_159; // @[dec_tlu_ctl.scala 1606:11] - assign io_npc_r_d1 = _T_167; // @[dec_tlu_ctl.scala 1612:14] - assign io_mepc = _T_196; // @[dec_tlu_ctl.scala 1631:10] - assign io_mdseac_locked_ns = mdseac_en | _T_479; // @[dec_tlu_ctl.scala 1829:22] - assign io_force_halt = mfdht[0] & _T_599; // @[dec_tlu_ctl.scala 1937:16] - assign io_dpc = _T_716; // @[dec_tlu_ctl.scala 2074:9] - assign io_mtdata1_t_0 = _T_864; // @[dec_tlu_ctl.scala 2230:39] - assign io_mtdata1_t_1 = _T_865; // @[dec_tlu_ctl.scala 2230:39] - assign io_mtdata1_t_2 = _T_866; // @[dec_tlu_ctl.scala 2230:39] - assign io_mtdata1_t_3 = _T_867; // @[dec_tlu_ctl.scala 2230:39] + assign io_dec_tlu_ic_diag_pkt_icache_wrdata = {{1'd0}, _T_756}; // @[dec_tlu_ctl.scala 2156:47] + assign io_dec_tlu_ic_diag_pkt_icache_dicawics = dicawics; // @[dec_tlu_ctl.scala 2158:41] + assign io_dec_tlu_ic_diag_pkt_icache_rd_valid = icache_rd_valid_f; // @[dec_tlu_ctl.scala 2166:41] + assign io_dec_tlu_ic_diag_pkt_icache_wr_valid = icache_wr_valid_f; // @[dec_tlu_ctl.scala 2167:41] + assign io_trigger_pkt_any_0_select = io_mtdata1_t_0[7]; // @[dec_tlu_ctl.scala 2231:40] + assign io_trigger_pkt_any_0_match_pkt = io_mtdata1_t_0[4]; // @[dec_tlu_ctl.scala 2232:43] + assign io_trigger_pkt_any_0_store = io_mtdata1_t_0[1]; // @[dec_tlu_ctl.scala 2233:40] + assign io_trigger_pkt_any_0_load = io_mtdata1_t_0[0]; // @[dec_tlu_ctl.scala 2234:40] + assign io_trigger_pkt_any_0_execute = io_mtdata1_t_0[2]; // @[dec_tlu_ctl.scala 2235:40] + assign io_trigger_pkt_any_0_m = io_mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 2236:40] + assign io_trigger_pkt_any_0_tdata2 = mtdata2_t_0; // @[dec_tlu_ctl.scala 2249:51] + assign io_trigger_pkt_any_1_select = io_mtdata1_t_1[7]; // @[dec_tlu_ctl.scala 2231:40] + assign io_trigger_pkt_any_1_match_pkt = io_mtdata1_t_1[4]; // @[dec_tlu_ctl.scala 2232:43] + assign io_trigger_pkt_any_1_store = io_mtdata1_t_1[1]; // @[dec_tlu_ctl.scala 2233:40] + assign io_trigger_pkt_any_1_load = io_mtdata1_t_1[0]; // @[dec_tlu_ctl.scala 2234:40] + assign io_trigger_pkt_any_1_execute = io_mtdata1_t_1[2]; // @[dec_tlu_ctl.scala 2235:40] + assign io_trigger_pkt_any_1_m = io_mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 2236:40] + assign io_trigger_pkt_any_1_tdata2 = mtdata2_t_1; // @[dec_tlu_ctl.scala 2249:51] + assign io_trigger_pkt_any_2_select = io_mtdata1_t_2[7]; // @[dec_tlu_ctl.scala 2231:40] + assign io_trigger_pkt_any_2_match_pkt = io_mtdata1_t_2[4]; // @[dec_tlu_ctl.scala 2232:43] + assign io_trigger_pkt_any_2_store = io_mtdata1_t_2[1]; // @[dec_tlu_ctl.scala 2233:40] + assign io_trigger_pkt_any_2_load = io_mtdata1_t_2[0]; // @[dec_tlu_ctl.scala 2234:40] + assign io_trigger_pkt_any_2_execute = io_mtdata1_t_2[2]; // @[dec_tlu_ctl.scala 2235:40] + assign io_trigger_pkt_any_2_m = io_mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 2236:40] + assign io_trigger_pkt_any_2_tdata2 = mtdata2_t_2; // @[dec_tlu_ctl.scala 2249:51] + assign io_trigger_pkt_any_3_select = io_mtdata1_t_3[7]; // @[dec_tlu_ctl.scala 2231:40] + assign io_trigger_pkt_any_3_match_pkt = io_mtdata1_t_3[4]; // @[dec_tlu_ctl.scala 2232:43] + assign io_trigger_pkt_any_3_store = io_mtdata1_t_3[1]; // @[dec_tlu_ctl.scala 2233:40] + assign io_trigger_pkt_any_3_load = io_mtdata1_t_3[0]; // @[dec_tlu_ctl.scala 2234:40] + assign io_trigger_pkt_any_3_execute = io_mtdata1_t_3[2]; // @[dec_tlu_ctl.scala 2235:40] + assign io_trigger_pkt_any_3_m = io_mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 2236:40] + assign io_trigger_pkt_any_3_tdata2 = mtdata2_t_3; // @[dec_tlu_ctl.scala 2249:51] + assign io_dec_tlu_int_valid_wb1 = _T_2329; // @[dec_tlu_ctl.scala 2491:30] + assign io_dec_tlu_i0_exc_valid_wb1 = _T_2327; // @[dec_tlu_ctl.scala 2489:30] + assign io_dec_tlu_i0_valid_wb1 = _T_2322; // @[dec_tlu_ctl.scala 2488:30] + assign io_dec_tlu_mtval_wb1 = mtval; // @[dec_tlu_ctl.scala 2493:24] + assign io_dec_tlu_exc_cause_wb1 = _T_2328; // @[dec_tlu_ctl.scala 2490:30] + assign io_dec_tlu_perfcnt0 = mhpmc_inc_r_d1_0 & _T_2174; // @[dec_tlu_ctl.scala 2345:22] + assign io_dec_tlu_perfcnt1 = mhpmc_inc_r_d1_1 & _T_2179; // @[dec_tlu_ctl.scala 2346:22] + assign io_dec_tlu_perfcnt2 = mhpmc_inc_r_d1_2 & _T_2184; // @[dec_tlu_ctl.scala 2347:22] + assign io_dec_tlu_perfcnt3 = mhpmc_inc_r_d1_3 & _T_2189; // @[dec_tlu_ctl.scala 2348:22] + assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1718:31] + assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1719:31] + assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1721:31] + assign io_dec_tlu_bus_clk_override = mcgc[3]; // @[dec_tlu_ctl.scala 1722:31] + assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1723:31] + assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1724:31] + assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1725:31] + assign io_dec_csr_rddata_d = _T_2605 | _T_2551; // @[dec_tlu_ctl.scala 2498:21] + assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1768:39] + assign io_dec_tlu_wr_pause_r = _T_360 & _T_361; // @[dec_tlu_ctl.scala 1777:24] + assign io_dec_tlu_meipt = meipt; // @[dec_tlu_ctl.scala 2006:19] + assign io_dec_tlu_meicurpl = meicurpl; // @[dec_tlu_ctl.scala 1970:22] + assign io_dec_tlu_meihap = {meivt,meihap}; // @[dec_tlu_ctl.scala 1956:20] + assign io_dec_tlu_mrac_ff = mrac; // @[dec_tlu_ctl.scala 1807:21] + assign io_dec_tlu_bpred_disable = mfdc[3]; // @[dec_tlu_ctl.scala 1766:39] + assign io_dec_tlu_sideeffect_posted_disable = mfdc[6]; // @[dec_tlu_ctl.scala 1765:39] + assign io_dec_tlu_core_ecc_disable = mfdc[8]; // @[dec_tlu_ctl.scala 1764:39] + assign io_dec_tlu_external_ldfwd_disable = mfdc[11]; // @[dec_tlu_ctl.scala 1763:39] + assign io_dec_tlu_dma_qos_prty = mfdc[18:16]; // @[dec_tlu_ctl.scala 1762:39] + assign io_dec_csr_wen_r_mod = _T_1 & _T_2; // @[dec_tlu_ctl.scala 1451:23] + assign io_fw_halt_req = _T_492 & _T_493; // @[dec_tlu_ctl.scala 1842:17] + assign io_mstatus = _T_56; // @[dec_tlu_ctl.scala 1467:13] + assign io_mstatus_mie_ns = io_mstatus[0] & _T_54; // @[dec_tlu_ctl.scala 1466:20] + assign io_dcsr = _T_691; // @[dec_tlu_ctl.scala 2053:10] + assign io_mtvec = _T_62; // @[dec_tlu_ctl.scala 1479:11] + assign io_mip = _T_68; // @[dec_tlu_ctl.scala 1494:9] + assign io_mie_ns = wr_mie_r ? _T_78 : mie; // @[dec_tlu_ctl.scala 1508:12] + assign io_npc_r = _T_161 | _T_159; // @[dec_tlu_ctl.scala 1602:11] + assign io_npc_r_d1 = _T_167; // @[dec_tlu_ctl.scala 1608:14] + assign io_mepc = _T_196; // @[dec_tlu_ctl.scala 1627:10] + assign io_mdseac_locked_ns = mdseac_en | _T_479; // @[dec_tlu_ctl.scala 1825:22] + assign io_force_halt = mfdht[0] & _T_599; // @[dec_tlu_ctl.scala 1933:16] + assign io_dpc = _T_716; // @[dec_tlu_ctl.scala 2070:9] + assign io_mtdata1_t_0 = _T_864; // @[dec_tlu_ctl.scala 2226:39] + assign io_mtdata1_t_1 = _T_865; // @[dec_tlu_ctl.scala 2226:39] + assign io_mtdata1_t_2 = _T_866; // @[dec_tlu_ctl.scala 2226:39] + assign io_mtdata1_t_3 = _T_867; // @[dec_tlu_ctl.scala 2226:39] assign rvclkhdr_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_io_en = io_dec_csr_wen_r_mod & _T_58; // @[lib.scala 355:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] @@ -53827,371 +53824,371 @@ module dec_decode_csr_read( output io_csr_pkt_postsync, output io_csr_pkt_legal ); - wire _T_1 = ~io_dec_csr_rdaddr_d[11]; // @[dec_tlu_ctl.scala 2574:129] - wire _T_3 = ~io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2574:129] - wire _T_5 = ~io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2574:129] - wire _T_7 = ~io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:129] - wire _T_9 = _T_1 & _T_3; // @[dec_tlu_ctl.scala 2574:198] - wire _T_10 = _T_9 & _T_5; // @[dec_tlu_ctl.scala 2574:198] - wire _T_11 = _T_10 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_15 = ~io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2574:129] - wire _T_17 = ~io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:129] - wire _T_19 = io_dec_csr_rdaddr_d[10] & _T_15; // @[dec_tlu_ctl.scala 2574:198] - wire _T_20 = _T_19 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_27 = ~io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2574:165] - wire _T_29 = _T_19 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_36 = io_dec_csr_rdaddr_d[10] & _T_3; // @[dec_tlu_ctl.scala 2574:198] - wire _T_37 = _T_36 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_69 = _T_10 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_70 = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_75 = _T_15 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_94 = ~io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2574:129] - wire _T_96 = ~io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2574:129] - wire _T_101 = io_dec_csr_rdaddr_d[11] & _T_15; // @[dec_tlu_ctl.scala 2574:198] - wire _T_102 = _T_101 & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_103 = _T_102 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_104 = _T_103 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_119 = io_dec_csr_rdaddr_d[7] & _T_3; // @[dec_tlu_ctl.scala 2574:198] - wire _T_120 = _T_119 & _T_5; // @[dec_tlu_ctl.scala 2574:198] - wire _T_121 = _T_120 & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_122 = _T_121 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_123 = _T_122 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_138 = _T_15 & _T_3; // @[dec_tlu_ctl.scala 2574:198] - wire _T_139 = _T_138 & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_140 = _T_139 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_141 = _T_140 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_142 = _T_141 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_145 = ~io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2574:129] - wire _T_156 = _T_145 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_157 = _T_156 & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_158 = _T_157 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_159 = _T_158 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_160 = _T_159 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_172 = _T_75 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_173 = _T_172 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_182 = _T_75 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_183 = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_191 = _T_75 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_196 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_217 = _T_1 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_218 = _T_217 & _T_5; // @[dec_tlu_ctl.scala 2574:198] - wire _T_219 = _T_218 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_220 = _T_219 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_230 = io_dec_csr_rdaddr_d[10] & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_231 = _T_230 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_232 = _T_231 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_240 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_241 = _T_240 & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_258 = _T_145 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_259 = _T_258 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_260 = _T_259 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_261 = _T_260 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_268 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_269 = _T_268 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_281 = _T_268 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_291 = _T_36 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_292 = _T_291 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_299 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_300 = _T_299 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_310 = _T_300 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_311 = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_330 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_331 = _T_330 & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_332 = _T_331 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_342 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_381 = _T_103 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_382 = _T_381 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_397 = _T_103 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_411 = _T_15 & _T_5; // @[dec_tlu_ctl.scala 2574:198] - wire _T_412 = _T_411 & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_413 = _T_412 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_414 = _T_413 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_415 = _T_414 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_426 = io_dec_csr_rdaddr_d[7] & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_427 = _T_426 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_428 = _T_427 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_429 = _T_428 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_444 = _T_119 & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_445 = _T_444 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_446 = _T_445 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_447 = _T_446 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_460 = _T_427 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_461 = _T_460 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_478 = _T_446 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_490 = _T_15 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_491 = _T_490 & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_492 = _T_491 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_493 = _T_492 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_505 = io_dec_csr_rdaddr_d[5] & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_506 = _T_505 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_507 = _T_506 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_508 = _T_507 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_536 = _T_507 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_553 = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2574:198] - wire _T_562 = io_dec_csr_rdaddr_d[6] & _T_5; // @[dec_tlu_ctl.scala 2574:198] - wire _T_563 = _T_562 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_564 = _T_563 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_572 = io_dec_csr_rdaddr_d[6] & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_573 = _T_572 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_574 = _T_573 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_585 = _T_563 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_593 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_594 = _T_593 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_595 = _T_594 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_614 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_615 = _T_614 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_624 = io_dec_csr_rdaddr_d[6] & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_625 = _T_624 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_626 = _T_625 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_668 = _T_196 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_669 = _T_668 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_685 = _T_196 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_693 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_694 = _T_693 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_695 = _T_694 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_703 = _T_624 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_716 = _T_1 & _T_5; // @[dec_tlu_ctl.scala 2574:198] - wire _T_717 = _T_716 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_718 = _T_717 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_719 = _T_718 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_726 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_727 = _T_726 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_737 = _T_230 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_738 = _T_737 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_748 = _T_726 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_749 = _T_748 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_787 = _T_311 | _T_553; // @[dec_tlu_ctl.scala 2642:81] - wire _T_799 = _T_3 & _T_5; // @[dec_tlu_ctl.scala 2574:198] - wire _T_800 = _T_799 & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_801 = _T_800 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_802 = _T_801 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_803 = _T_802 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_804 = _T_787 | _T_803; // @[dec_tlu_ctl.scala 2642:121] - wire _T_813 = io_dec_csr_rdaddr_d[11] & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_814 = _T_813 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_815 = _T_814 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_816 = _T_815 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_817 = _T_804 | _T_816; // @[dec_tlu_ctl.scala 2642:155] - wire _T_828 = _T_814 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_829 = _T_828 & _T_27; // @[dec_tlu_ctl.scala 2574:198] - wire _T_830 = _T_817 | _T_829; // @[dec_tlu_ctl.scala 2643:97] - wire _T_841 = io_dec_csr_rdaddr_d[7] & _T_5; // @[dec_tlu_ctl.scala 2574:198] - wire _T_842 = _T_841 & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_843 = _T_842 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_844 = _T_843 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_845 = _T_844 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_869 = _T_311 | _T_70; // @[dec_tlu_ctl.scala 2644:81] - wire _T_879 = _T_869 | _T_183; // @[dec_tlu_ctl.scala 2644:121] - wire _T_889 = _T_879 | _T_342; // @[dec_tlu_ctl.scala 2644:162] - wire _T_904 = _T_1 & _T_15; // @[dec_tlu_ctl.scala 2574:198] - wire _T_905 = _T_904 & _T_3; // @[dec_tlu_ctl.scala 2574:198] - wire _T_906 = _T_905 & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_907 = _T_906 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_908 = _T_907 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_909 = _T_908 & _T_27; // @[dec_tlu_ctl.scala 2574:198] - wire _T_910 = _T_889 | _T_909; // @[dec_tlu_ctl.scala 2645:105] - wire _T_922 = _T_217 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_923 = _T_922 & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_924 = _T_923 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_925 = _T_924 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_926 = _T_910 | _T_925; // @[dec_tlu_ctl.scala 2645:145] - wire _T_937 = _T_231 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_938 = _T_937 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_955 = _T_1 & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_956 = _T_955 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_957 = _T_956 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_958 = _T_957 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_959 = _T_958 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_960 = _T_959 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_961 = _T_960 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_962 = _T_961 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_963 = _T_962 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_964 = _T_963 & _T_27; // @[dec_tlu_ctl.scala 2574:198] - wire _T_983 = _T_1 & _T_145; // @[dec_tlu_ctl.scala 2574:198] - wire _T_984 = _T_983 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_985 = _T_984 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_986 = _T_985 & _T_15; // @[dec_tlu_ctl.scala 2574:198] - wire _T_987 = _T_986 & _T_3; // @[dec_tlu_ctl.scala 2574:198] - wire _T_988 = _T_987 & _T_5; // @[dec_tlu_ctl.scala 2574:198] - wire _T_989 = _T_988 & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_990 = _T_989 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_991 = _T_990 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_992 = _T_964 | _T_991; // @[dec_tlu_ctl.scala 2647:81] - wire _T_1013 = _T_987 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1014 = _T_1013 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1015 = _T_1014 & _T_27; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1016 = _T_992 | _T_1015; // @[dec_tlu_ctl.scala 2647:129] - wire _T_1032 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1033 = _T_1032 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1034 = _T_1033 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1035 = _T_1034 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1036 = _T_1035 & _T_5; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1037 = _T_1036 & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1038 = _T_1037 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1039 = _T_1038 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1040 = _T_1039 & _T_27; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1041 = _T_1016 | _T_1040; // @[dec_tlu_ctl.scala 2648:105] - wire _T_1053 = io_dec_csr_rdaddr_d[11] & _T_145; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1054 = _T_1053 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1055 = _T_1054 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1056 = _T_1055 & _T_3; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1057 = _T_1056 & _T_5; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1058 = _T_1057 & _T_27; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1059 = _T_1041 | _T_1058; // @[dec_tlu_ctl.scala 2648:153] - wire _T_1078 = _T_959 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1079 = _T_1078 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1080 = _T_1079 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1081 = _T_1080 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1082 = _T_1081 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1083 = _T_1082 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1084 = _T_1059 | _T_1083; // @[dec_tlu_ctl.scala 2649:105] - wire _T_1105 = _T_1079 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1106 = _T_1105 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1107 = _T_1084 | _T_1106; // @[dec_tlu_ctl.scala 2649:153] - wire _T_1125 = _T_1033 & _T_15; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1126 = _T_1125 & _T_3; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1127 = _T_1126 & _T_5; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1128 = _T_1127 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1129 = _T_1128 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1130 = _T_1129 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1131 = _T_1130 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1132 = _T_1107 | _T_1131; // @[dec_tlu_ctl.scala 2650:105] - wire _T_1152 = _T_958 & _T_3; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1153 = _T_1152 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1154 = _T_1153 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1155 = _T_1154 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1156 = _T_1155 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1157 = _T_1132 | _T_1156; // @[dec_tlu_ctl.scala 2650:161] - wire _T_1176 = _T_1013 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1177 = _T_1157 | _T_1176; // @[dec_tlu_ctl.scala 2651:105] - wire _T_1202 = _T_1129 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1203 = _T_1202 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1204 = _T_1203 & _T_27; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1205 = _T_1177 | _T_1204; // @[dec_tlu_ctl.scala 2651:161] - wire _T_1224 = _T_959 & _T_5; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1225 = _T_1224 & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1226 = _T_1225 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1227 = _T_1226 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1228 = _T_1205 | _T_1227; // @[dec_tlu_ctl.scala 2652:97] - wire _T_1248 = _T_1224 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1249 = _T_1248 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1250 = _T_1249 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1251 = _T_1228 | _T_1250; // @[dec_tlu_ctl.scala 2652:153] - wire _T_1275 = _T_1130 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1276 = _T_1251 | _T_1275; // @[dec_tlu_ctl.scala 2653:105] - wire _T_1296 = _T_1013 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1297 = _T_1296 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1298 = _T_1276 | _T_1297; // @[dec_tlu_ctl.scala 2653:161] - wire _T_1315 = _T_1055 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1316 = _T_1315 & _T_5; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1317 = _T_1316 & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1318 = _T_1317 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1319 = _T_1318 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1320 = _T_1298 | _T_1319; // @[dec_tlu_ctl.scala 2654:105] - wire _T_1343 = _T_1318 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1344 = _T_1343 & _T_27; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1345 = _T_1320 | _T_1344; // @[dec_tlu_ctl.scala 2654:161] - wire _T_1361 = _T_1057 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1362 = _T_1345 | _T_1361; // @[dec_tlu_ctl.scala 2655:105] - wire _T_1384 = _T_1249 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1385 = _T_1362 | _T_1384; // @[dec_tlu_ctl.scala 2655:161] - wire _T_1406 = _T_1225 & _T_27; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1407 = _T_1385 | _T_1406; // @[dec_tlu_ctl.scala 2656:105] - wire _T_1430 = _T_1226 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1431 = _T_1407 | _T_1430; // @[dec_tlu_ctl.scala 2656:161] - wire _T_1455 = _T_1153 & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1456 = _T_1455 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1457 = _T_1456 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1458 = _T_1457 & _T_27; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1459 = _T_1431 | _T_1458; // @[dec_tlu_ctl.scala 2657:105] - wire _T_1475 = _T_1057 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1476 = _T_1459 | _T_1475; // @[dec_tlu_ctl.scala 2657:153] - wire _T_1498 = _T_986 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1499 = _T_1498 & _T_5; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1500 = _T_1499 & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1501 = _T_1500 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1502 = _T_1501 & _T_7; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1503 = _T_1476 | _T_1502; // @[dec_tlu_ctl.scala 2658:113] - wire _T_1526 = _T_986 & _T_5; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1527 = _T_1526 & _T_94; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1528 = _T_1527 & _T_96; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1529 = _T_1528 & _T_17; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1530 = _T_1529 & _T_27; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1531 = _T_1503 | _T_1530; // @[dec_tlu_ctl.scala 2658:161] - wire _T_1550 = _T_1013 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1551 = _T_1531 | _T_1550; // @[dec_tlu_ctl.scala 2659:97] - wire _T_1567 = _T_1057 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1568 = _T_1551 | _T_1567; // @[dec_tlu_ctl.scala 2659:153] - wire _T_1587 = _T_1013 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2574:198] - wire _T_1588 = _T_1568 | _T_1587; // @[dec_tlu_ctl.scala 2660:113] - wire _T_1604 = _T_1057 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2574:198] - assign io_csr_pkt_csr_misa = _T_11 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2576:57] - assign io_csr_pkt_csr_mvendorid = _T_20 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2577:57] - assign io_csr_pkt_csr_marchid = _T_29 & _T_27; // @[dec_tlu_ctl.scala 2578:57] - assign io_csr_pkt_csr_mimpid = _T_37 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2579:57] - assign io_csr_pkt_csr_mhartid = _T_19 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2580:57] - assign io_csr_pkt_csr_mstatus = _T_11 & _T_27; // @[dec_tlu_ctl.scala 2581:57] - assign io_csr_pkt_csr_mtvec = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2582:57] - assign io_csr_pkt_csr_mip = _T_75 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2583:65] - assign io_csr_pkt_csr_mie = _T_69 & _T_27; // @[dec_tlu_ctl.scala 2584:65] - assign io_csr_pkt_csr_mcyclel = _T_104 & _T_17; // @[dec_tlu_ctl.scala 2585:57] - assign io_csr_pkt_csr_mcycleh = _T_123 & _T_17; // @[dec_tlu_ctl.scala 2586:57] - assign io_csr_pkt_csr_minstretl = _T_142 & _T_27; // @[dec_tlu_ctl.scala 2587:57] - assign io_csr_pkt_csr_minstreth = _T_160 & _T_27; // @[dec_tlu_ctl.scala 2588:57] - assign io_csr_pkt_csr_mscratch = _T_173 & _T_27; // @[dec_tlu_ctl.scala 2589:57] - assign io_csr_pkt_csr_mepc = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2590:57] - assign io_csr_pkt_csr_mcause = _T_191 & _T_27; // @[dec_tlu_ctl.scala 2591:57] - assign io_csr_pkt_csr_mscause = _T_196 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2592:57] - assign io_csr_pkt_csr_mtval = _T_191 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2593:57] - assign io_csr_pkt_csr_mrac = _T_220 & _T_17; // @[dec_tlu_ctl.scala 2594:57] - assign io_csr_pkt_csr_dmst = _T_232 & _T_17; // @[dec_tlu_ctl.scala 2595:57] - assign io_csr_pkt_csr_mdseac = _T_241 & _T_96; // @[dec_tlu_ctl.scala 2596:57] - assign io_csr_pkt_csr_meihap = _T_240 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2597:57] - assign io_csr_pkt_csr_meivt = _T_261 & _T_27; // @[dec_tlu_ctl.scala 2598:57] - assign io_csr_pkt_csr_meipt = _T_269 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2599:57] - assign io_csr_pkt_csr_meicurpl = _T_268 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2600:57] - assign io_csr_pkt_csr_meicidpl = _T_281 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2601:57] - assign io_csr_pkt_csr_dcsr = _T_292 & _T_27; // @[dec_tlu_ctl.scala 2602:57] - assign io_csr_pkt_csr_mcgc = _T_300 & _T_27; // @[dec_tlu_ctl.scala 2603:57] - assign io_csr_pkt_csr_mfdc = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2604:57] - assign io_csr_pkt_csr_dpc = _T_292 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2605:65] - assign io_csr_pkt_csr_mtsel = _T_332 & _T_27; // @[dec_tlu_ctl.scala 2606:57] - assign io_csr_pkt_csr_mtdata1 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2607:57] - assign io_csr_pkt_csr_mtdata2 = _T_331 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2608:57] - assign io_csr_pkt_csr_mhpmc3 = _T_104 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2609:57] - assign io_csr_pkt_csr_mhpmc4 = _T_382 & _T_27; // @[dec_tlu_ctl.scala 2610:57] - assign io_csr_pkt_csr_mhpmc5 = _T_397 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2611:57] - assign io_csr_pkt_csr_mhpmc6 = _T_415 & _T_27; // @[dec_tlu_ctl.scala 2612:57] - assign io_csr_pkt_csr_mhpmc3h = _T_429 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2613:57] - assign io_csr_pkt_csr_mhpmc4h = _T_447 & _T_27; // @[dec_tlu_ctl.scala 2614:57] - assign io_csr_pkt_csr_mhpmc5h = _T_461 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2615:57] - assign io_csr_pkt_csr_mhpmc6h = _T_478 & _T_27; // @[dec_tlu_ctl.scala 2616:57] - assign io_csr_pkt_csr_mhpme3 = _T_493 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2617:57] - assign io_csr_pkt_csr_mhpme4 = _T_508 & _T_27; // @[dec_tlu_ctl.scala 2618:57] - assign io_csr_pkt_csr_mhpme5 = _T_508 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2619:57] - assign io_csr_pkt_csr_mhpme6 = _T_536 & _T_27; // @[dec_tlu_ctl.scala 2620:57] - assign io_csr_pkt_csr_mcountinhibit = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2621:49] - assign io_csr_pkt_csr_mitctl0 = _T_564 & _T_27; // @[dec_tlu_ctl.scala 2622:57] - assign io_csr_pkt_csr_mitctl1 = _T_574 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2623:57] - assign io_csr_pkt_csr_mitb0 = _T_585 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2624:57] - assign io_csr_pkt_csr_mitb1 = _T_595 & _T_27; // @[dec_tlu_ctl.scala 2625:57] - assign io_csr_pkt_csr_mitcnt0 = _T_585 & _T_27; // @[dec_tlu_ctl.scala 2626:57] - assign io_csr_pkt_csr_mitcnt1 = _T_615 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2627:57] - assign io_csr_pkt_csr_mpmc = _T_626 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2628:57] - assign io_csr_pkt_csr_meicpct = _T_281 & _T_27; // @[dec_tlu_ctl.scala 2630:57] - assign io_csr_pkt_csr_micect = _T_669 & _T_27; // @[dec_tlu_ctl.scala 2632:57] - assign io_csr_pkt_csr_miccmect = _T_668 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2633:57] - assign io_csr_pkt_csr_mdccmect = _T_685 & _T_27; // @[dec_tlu_ctl.scala 2634:57] - assign io_csr_pkt_csr_mfdht = _T_695 & _T_27; // @[dec_tlu_ctl.scala 2635:57] - assign io_csr_pkt_csr_mfdhs = _T_703 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2636:57] - assign io_csr_pkt_csr_dicawics = _T_719 & _T_27; // @[dec_tlu_ctl.scala 2637:57] - assign io_csr_pkt_csr_dicad0h = _T_727 & _T_17; // @[dec_tlu_ctl.scala 2638:57] - assign io_csr_pkt_csr_dicad0 = _T_738 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2639:57] - assign io_csr_pkt_csr_dicad1 = _T_749 & _T_27; // @[dec_tlu_ctl.scala 2640:57] - assign io_csr_pkt_csr_dicago = _T_749 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2641:57] - assign io_csr_pkt_presync = _T_830 | _T_845; // @[dec_tlu_ctl.scala 2642:34] - assign io_csr_pkt_postsync = _T_926 | _T_938; // @[dec_tlu_ctl.scala 2644:30] - assign io_csr_pkt_legal = _T_1588 | _T_1604; // @[dec_tlu_ctl.scala 2647:26] + wire _T_1 = ~io_dec_csr_rdaddr_d[11]; // @[dec_tlu_ctl.scala 2570:129] + wire _T_3 = ~io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2570:129] + wire _T_5 = ~io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2570:129] + wire _T_7 = ~io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:129] + wire _T_9 = _T_1 & _T_3; // @[dec_tlu_ctl.scala 2570:198] + wire _T_10 = _T_9 & _T_5; // @[dec_tlu_ctl.scala 2570:198] + wire _T_11 = _T_10 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_15 = ~io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2570:129] + wire _T_17 = ~io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:129] + wire _T_19 = io_dec_csr_rdaddr_d[10] & _T_15; // @[dec_tlu_ctl.scala 2570:198] + wire _T_20 = _T_19 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_27 = ~io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:165] + wire _T_29 = _T_19 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_36 = io_dec_csr_rdaddr_d[10] & _T_3; // @[dec_tlu_ctl.scala 2570:198] + wire _T_37 = _T_36 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_69 = _T_10 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_70 = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_75 = _T_15 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_94 = ~io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:129] + wire _T_96 = ~io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:129] + wire _T_101 = io_dec_csr_rdaddr_d[11] & _T_15; // @[dec_tlu_ctl.scala 2570:198] + wire _T_102 = _T_101 & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_103 = _T_102 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_104 = _T_103 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_119 = io_dec_csr_rdaddr_d[7] & _T_3; // @[dec_tlu_ctl.scala 2570:198] + wire _T_120 = _T_119 & _T_5; // @[dec_tlu_ctl.scala 2570:198] + wire _T_121 = _T_120 & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_122 = _T_121 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_123 = _T_122 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_138 = _T_15 & _T_3; // @[dec_tlu_ctl.scala 2570:198] + wire _T_139 = _T_138 & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_140 = _T_139 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_141 = _T_140 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_142 = _T_141 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_145 = ~io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2570:129] + wire _T_156 = _T_145 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_157 = _T_156 & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_158 = _T_157 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_159 = _T_158 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_160 = _T_159 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_172 = _T_75 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_173 = _T_172 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_182 = _T_75 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_183 = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_191 = _T_75 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_196 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_217 = _T_1 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_218 = _T_217 & _T_5; // @[dec_tlu_ctl.scala 2570:198] + wire _T_219 = _T_218 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_220 = _T_219 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_230 = io_dec_csr_rdaddr_d[10] & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_231 = _T_230 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_232 = _T_231 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_240 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_241 = _T_240 & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_258 = _T_145 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_259 = _T_258 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_260 = _T_259 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_261 = _T_260 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_268 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_269 = _T_268 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_281 = _T_268 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_291 = _T_36 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_292 = _T_291 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_299 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_300 = _T_299 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_310 = _T_300 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_311 = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_330 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_331 = _T_330 & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_332 = _T_331 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_342 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_381 = _T_103 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_382 = _T_381 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_397 = _T_103 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_411 = _T_15 & _T_5; // @[dec_tlu_ctl.scala 2570:198] + wire _T_412 = _T_411 & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_413 = _T_412 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_414 = _T_413 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_415 = _T_414 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_426 = io_dec_csr_rdaddr_d[7] & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_427 = _T_426 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_428 = _T_427 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_429 = _T_428 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_444 = _T_119 & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_445 = _T_444 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_446 = _T_445 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_447 = _T_446 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_460 = _T_427 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_461 = _T_460 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_478 = _T_446 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_490 = _T_15 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_491 = _T_490 & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_492 = _T_491 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_493 = _T_492 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_505 = io_dec_csr_rdaddr_d[5] & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_506 = _T_505 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_507 = _T_506 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_508 = _T_507 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_536 = _T_507 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_553 = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2570:198] + wire _T_562 = io_dec_csr_rdaddr_d[6] & _T_5; // @[dec_tlu_ctl.scala 2570:198] + wire _T_563 = _T_562 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_564 = _T_563 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_572 = io_dec_csr_rdaddr_d[6] & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_573 = _T_572 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_574 = _T_573 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_585 = _T_563 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_593 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_594 = _T_593 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_595 = _T_594 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_614 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_615 = _T_614 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_624 = io_dec_csr_rdaddr_d[6] & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_625 = _T_624 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_626 = _T_625 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_668 = _T_196 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_669 = _T_668 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_685 = _T_196 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_693 = io_dec_csr_rdaddr_d[6] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_694 = _T_693 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_695 = _T_694 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_703 = _T_624 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_716 = _T_1 & _T_5; // @[dec_tlu_ctl.scala 2570:198] + wire _T_717 = _T_716 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_718 = _T_717 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_719 = _T_718 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_726 = io_dec_csr_rdaddr_d[10] & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_727 = _T_726 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_737 = _T_230 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_738 = _T_737 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_748 = _T_726 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_749 = _T_748 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_787 = _T_311 | _T_553; // @[dec_tlu_ctl.scala 2638:81] + wire _T_799 = _T_3 & _T_5; // @[dec_tlu_ctl.scala 2570:198] + wire _T_800 = _T_799 & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_801 = _T_800 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_802 = _T_801 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_803 = _T_802 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_804 = _T_787 | _T_803; // @[dec_tlu_ctl.scala 2638:121] + wire _T_813 = io_dec_csr_rdaddr_d[11] & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_814 = _T_813 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_815 = _T_814 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_816 = _T_815 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_817 = _T_804 | _T_816; // @[dec_tlu_ctl.scala 2638:155] + wire _T_828 = _T_814 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_829 = _T_828 & _T_27; // @[dec_tlu_ctl.scala 2570:198] + wire _T_830 = _T_817 | _T_829; // @[dec_tlu_ctl.scala 2639:97] + wire _T_841 = io_dec_csr_rdaddr_d[7] & _T_5; // @[dec_tlu_ctl.scala 2570:198] + wire _T_842 = _T_841 & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_843 = _T_842 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_844 = _T_843 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_845 = _T_844 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_869 = _T_311 | _T_70; // @[dec_tlu_ctl.scala 2640:81] + wire _T_879 = _T_869 | _T_183; // @[dec_tlu_ctl.scala 2640:121] + wire _T_889 = _T_879 | _T_342; // @[dec_tlu_ctl.scala 2640:162] + wire _T_904 = _T_1 & _T_15; // @[dec_tlu_ctl.scala 2570:198] + wire _T_905 = _T_904 & _T_3; // @[dec_tlu_ctl.scala 2570:198] + wire _T_906 = _T_905 & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_907 = _T_906 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_908 = _T_907 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_909 = _T_908 & _T_27; // @[dec_tlu_ctl.scala 2570:198] + wire _T_910 = _T_889 | _T_909; // @[dec_tlu_ctl.scala 2641:105] + wire _T_922 = _T_217 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_923 = _T_922 & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_924 = _T_923 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_925 = _T_924 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_926 = _T_910 | _T_925; // @[dec_tlu_ctl.scala 2641:145] + wire _T_937 = _T_231 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_938 = _T_937 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_955 = _T_1 & io_dec_csr_rdaddr_d[10]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_956 = _T_955 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_957 = _T_956 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_958 = _T_957 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_959 = _T_958 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_960 = _T_959 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_961 = _T_960 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_962 = _T_961 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_963 = _T_962 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_964 = _T_963 & _T_27; // @[dec_tlu_ctl.scala 2570:198] + wire _T_983 = _T_1 & _T_145; // @[dec_tlu_ctl.scala 2570:198] + wire _T_984 = _T_983 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_985 = _T_984 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_986 = _T_985 & _T_15; // @[dec_tlu_ctl.scala 2570:198] + wire _T_987 = _T_986 & _T_3; // @[dec_tlu_ctl.scala 2570:198] + wire _T_988 = _T_987 & _T_5; // @[dec_tlu_ctl.scala 2570:198] + wire _T_989 = _T_988 & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_990 = _T_989 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_991 = _T_990 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_992 = _T_964 | _T_991; // @[dec_tlu_ctl.scala 2643:81] + wire _T_1013 = _T_987 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1014 = _T_1013 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1015 = _T_1014 & _T_27; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1016 = _T_992 | _T_1015; // @[dec_tlu_ctl.scala 2643:129] + wire _T_1032 = io_dec_csr_rdaddr_d[11] & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1033 = _T_1032 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1034 = _T_1033 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1035 = _T_1034 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1036 = _T_1035 & _T_5; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1037 = _T_1036 & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1038 = _T_1037 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1039 = _T_1038 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1040 = _T_1039 & _T_27; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1041 = _T_1016 | _T_1040; // @[dec_tlu_ctl.scala 2644:105] + wire _T_1053 = io_dec_csr_rdaddr_d[11] & _T_145; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1054 = _T_1053 & io_dec_csr_rdaddr_d[9]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1055 = _T_1054 & io_dec_csr_rdaddr_d[8]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1056 = _T_1055 & _T_3; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1057 = _T_1056 & _T_5; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1058 = _T_1057 & _T_27; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1059 = _T_1041 | _T_1058; // @[dec_tlu_ctl.scala 2644:153] + wire _T_1078 = _T_959 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1079 = _T_1078 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1080 = _T_1079 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1081 = _T_1080 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1082 = _T_1081 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1083 = _T_1082 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1084 = _T_1059 | _T_1083; // @[dec_tlu_ctl.scala 2645:105] + wire _T_1105 = _T_1079 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1106 = _T_1105 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1107 = _T_1084 | _T_1106; // @[dec_tlu_ctl.scala 2645:153] + wire _T_1125 = _T_1033 & _T_15; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1126 = _T_1125 & _T_3; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1127 = _T_1126 & _T_5; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1128 = _T_1127 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1129 = _T_1128 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1130 = _T_1129 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1131 = _T_1130 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1132 = _T_1107 | _T_1131; // @[dec_tlu_ctl.scala 2646:105] + wire _T_1152 = _T_958 & _T_3; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1153 = _T_1152 & io_dec_csr_rdaddr_d[5]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1154 = _T_1153 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1155 = _T_1154 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1156 = _T_1155 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1157 = _T_1132 | _T_1156; // @[dec_tlu_ctl.scala 2646:161] + wire _T_1176 = _T_1013 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1177 = _T_1157 | _T_1176; // @[dec_tlu_ctl.scala 2647:105] + wire _T_1202 = _T_1129 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1203 = _T_1202 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1204 = _T_1203 & _T_27; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1205 = _T_1177 | _T_1204; // @[dec_tlu_ctl.scala 2647:161] + wire _T_1224 = _T_959 & _T_5; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1225 = _T_1224 & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1226 = _T_1225 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1227 = _T_1226 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1228 = _T_1205 | _T_1227; // @[dec_tlu_ctl.scala 2648:97] + wire _T_1248 = _T_1224 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1249 = _T_1248 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1250 = _T_1249 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1251 = _T_1228 | _T_1250; // @[dec_tlu_ctl.scala 2648:153] + wire _T_1275 = _T_1130 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1276 = _T_1251 | _T_1275; // @[dec_tlu_ctl.scala 2649:105] + wire _T_1296 = _T_1013 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1297 = _T_1296 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1298 = _T_1276 | _T_1297; // @[dec_tlu_ctl.scala 2649:161] + wire _T_1315 = _T_1055 & io_dec_csr_rdaddr_d[7]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1316 = _T_1315 & _T_5; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1317 = _T_1316 & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1318 = _T_1317 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1319 = _T_1318 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1320 = _T_1298 | _T_1319; // @[dec_tlu_ctl.scala 2650:105] + wire _T_1343 = _T_1318 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1344 = _T_1343 & _T_27; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1345 = _T_1320 | _T_1344; // @[dec_tlu_ctl.scala 2650:161] + wire _T_1361 = _T_1057 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1362 = _T_1345 | _T_1361; // @[dec_tlu_ctl.scala 2651:105] + wire _T_1384 = _T_1249 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1385 = _T_1362 | _T_1384; // @[dec_tlu_ctl.scala 2651:161] + wire _T_1406 = _T_1225 & _T_27; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1407 = _T_1385 | _T_1406; // @[dec_tlu_ctl.scala 2652:105] + wire _T_1430 = _T_1226 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1431 = _T_1407 | _T_1430; // @[dec_tlu_ctl.scala 2652:161] + wire _T_1455 = _T_1153 & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1456 = _T_1455 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1457 = _T_1456 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1458 = _T_1457 & _T_27; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1459 = _T_1431 | _T_1458; // @[dec_tlu_ctl.scala 2653:105] + wire _T_1475 = _T_1057 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1476 = _T_1459 | _T_1475; // @[dec_tlu_ctl.scala 2653:153] + wire _T_1498 = _T_986 & io_dec_csr_rdaddr_d[6]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1499 = _T_1498 & _T_5; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1500 = _T_1499 & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1501 = _T_1500 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1502 = _T_1501 & _T_7; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1503 = _T_1476 | _T_1502; // @[dec_tlu_ctl.scala 2654:113] + wire _T_1526 = _T_986 & _T_5; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1527 = _T_1526 & _T_94; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1528 = _T_1527 & _T_96; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1529 = _T_1528 & _T_17; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1530 = _T_1529 & _T_27; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1531 = _T_1503 | _T_1530; // @[dec_tlu_ctl.scala 2654:161] + wire _T_1550 = _T_1013 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1551 = _T_1531 | _T_1550; // @[dec_tlu_ctl.scala 2655:97] + wire _T_1567 = _T_1057 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1568 = _T_1551 | _T_1567; // @[dec_tlu_ctl.scala 2655:153] + wire _T_1587 = _T_1013 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:198] + wire _T_1588 = _T_1568 | _T_1587; // @[dec_tlu_ctl.scala 2656:113] + wire _T_1604 = _T_1057 & io_dec_csr_rdaddr_d[4]; // @[dec_tlu_ctl.scala 2570:198] + assign io_csr_pkt_csr_misa = _T_11 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2572:57] + assign io_csr_pkt_csr_mvendorid = _T_20 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2573:57] + assign io_csr_pkt_csr_marchid = _T_29 & _T_27; // @[dec_tlu_ctl.scala 2574:57] + assign io_csr_pkt_csr_mimpid = _T_37 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2575:57] + assign io_csr_pkt_csr_mhartid = _T_19 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2576:57] + assign io_csr_pkt_csr_mstatus = _T_11 & _T_27; // @[dec_tlu_ctl.scala 2577:57] + assign io_csr_pkt_csr_mtvec = _T_69 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2578:57] + assign io_csr_pkt_csr_mip = _T_75 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2579:65] + assign io_csr_pkt_csr_mie = _T_69 & _T_27; // @[dec_tlu_ctl.scala 2580:65] + assign io_csr_pkt_csr_mcyclel = _T_104 & _T_17; // @[dec_tlu_ctl.scala 2581:57] + assign io_csr_pkt_csr_mcycleh = _T_123 & _T_17; // @[dec_tlu_ctl.scala 2582:57] + assign io_csr_pkt_csr_minstretl = _T_142 & _T_27; // @[dec_tlu_ctl.scala 2583:57] + assign io_csr_pkt_csr_minstreth = _T_160 & _T_27; // @[dec_tlu_ctl.scala 2584:57] + assign io_csr_pkt_csr_mscratch = _T_173 & _T_27; // @[dec_tlu_ctl.scala 2585:57] + assign io_csr_pkt_csr_mepc = _T_182 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2586:57] + assign io_csr_pkt_csr_mcause = _T_191 & _T_27; // @[dec_tlu_ctl.scala 2587:57] + assign io_csr_pkt_csr_mscause = _T_196 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2588:57] + assign io_csr_pkt_csr_mtval = _T_191 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2589:57] + assign io_csr_pkt_csr_mrac = _T_220 & _T_17; // @[dec_tlu_ctl.scala 2590:57] + assign io_csr_pkt_csr_dmst = _T_232 & _T_17; // @[dec_tlu_ctl.scala 2591:57] + assign io_csr_pkt_csr_mdseac = _T_241 & _T_96; // @[dec_tlu_ctl.scala 2592:57] + assign io_csr_pkt_csr_meihap = _T_240 & io_dec_csr_rdaddr_d[3]; // @[dec_tlu_ctl.scala 2593:57] + assign io_csr_pkt_csr_meivt = _T_261 & _T_27; // @[dec_tlu_ctl.scala 2594:57] + assign io_csr_pkt_csr_meipt = _T_269 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2595:57] + assign io_csr_pkt_csr_meicurpl = _T_268 & io_dec_csr_rdaddr_d[2]; // @[dec_tlu_ctl.scala 2596:57] + assign io_csr_pkt_csr_meicidpl = _T_281 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2597:57] + assign io_csr_pkt_csr_dcsr = _T_292 & _T_27; // @[dec_tlu_ctl.scala 2598:57] + assign io_csr_pkt_csr_mcgc = _T_300 & _T_27; // @[dec_tlu_ctl.scala 2599:57] + assign io_csr_pkt_csr_mfdc = _T_310 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2600:57] + assign io_csr_pkt_csr_dpc = _T_292 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2601:65] + assign io_csr_pkt_csr_mtsel = _T_332 & _T_27; // @[dec_tlu_ctl.scala 2602:57] + assign io_csr_pkt_csr_mtdata1 = _T_231 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2603:57] + assign io_csr_pkt_csr_mtdata2 = _T_331 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2604:57] + assign io_csr_pkt_csr_mhpmc3 = _T_104 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2605:57] + assign io_csr_pkt_csr_mhpmc4 = _T_382 & _T_27; // @[dec_tlu_ctl.scala 2606:57] + assign io_csr_pkt_csr_mhpmc5 = _T_397 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2607:57] + assign io_csr_pkt_csr_mhpmc6 = _T_415 & _T_27; // @[dec_tlu_ctl.scala 2608:57] + assign io_csr_pkt_csr_mhpmc3h = _T_429 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2609:57] + assign io_csr_pkt_csr_mhpmc4h = _T_447 & _T_27; // @[dec_tlu_ctl.scala 2610:57] + assign io_csr_pkt_csr_mhpmc5h = _T_461 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2611:57] + assign io_csr_pkt_csr_mhpmc6h = _T_478 & _T_27; // @[dec_tlu_ctl.scala 2612:57] + assign io_csr_pkt_csr_mhpme3 = _T_493 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2613:57] + assign io_csr_pkt_csr_mhpme4 = _T_508 & _T_27; // @[dec_tlu_ctl.scala 2614:57] + assign io_csr_pkt_csr_mhpme5 = _T_508 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2615:57] + assign io_csr_pkt_csr_mhpme6 = _T_536 & _T_27; // @[dec_tlu_ctl.scala 2616:57] + assign io_csr_pkt_csr_mcountinhibit = _T_493 & _T_27; // @[dec_tlu_ctl.scala 2617:49] + assign io_csr_pkt_csr_mitctl0 = _T_564 & _T_27; // @[dec_tlu_ctl.scala 2618:57] + assign io_csr_pkt_csr_mitctl1 = _T_574 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2619:57] + assign io_csr_pkt_csr_mitb0 = _T_585 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2620:57] + assign io_csr_pkt_csr_mitb1 = _T_595 & _T_27; // @[dec_tlu_ctl.scala 2621:57] + assign io_csr_pkt_csr_mitcnt0 = _T_585 & _T_27; // @[dec_tlu_ctl.scala 2622:57] + assign io_csr_pkt_csr_mitcnt1 = _T_615 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2623:57] + assign io_csr_pkt_csr_mpmc = _T_626 & io_dec_csr_rdaddr_d[1]; // @[dec_tlu_ctl.scala 2624:57] + assign io_csr_pkt_csr_meicpct = _T_281 & _T_27; // @[dec_tlu_ctl.scala 2626:57] + assign io_csr_pkt_csr_micect = _T_669 & _T_27; // @[dec_tlu_ctl.scala 2628:57] + assign io_csr_pkt_csr_miccmect = _T_668 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2629:57] + assign io_csr_pkt_csr_mdccmect = _T_685 & _T_27; // @[dec_tlu_ctl.scala 2630:57] + assign io_csr_pkt_csr_mfdht = _T_695 & _T_27; // @[dec_tlu_ctl.scala 2631:57] + assign io_csr_pkt_csr_mfdhs = _T_703 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2632:57] + assign io_csr_pkt_csr_dicawics = _T_719 & _T_27; // @[dec_tlu_ctl.scala 2633:57] + assign io_csr_pkt_csr_dicad0h = _T_727 & _T_17; // @[dec_tlu_ctl.scala 2634:57] + assign io_csr_pkt_csr_dicad0 = _T_738 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2635:57] + assign io_csr_pkt_csr_dicad1 = _T_749 & _T_27; // @[dec_tlu_ctl.scala 2636:57] + assign io_csr_pkt_csr_dicago = _T_749 & io_dec_csr_rdaddr_d[0]; // @[dec_tlu_ctl.scala 2637:57] + assign io_csr_pkt_presync = _T_830 | _T_845; // @[dec_tlu_ctl.scala 2638:34] + assign io_csr_pkt_postsync = _T_926 | _T_938; // @[dec_tlu_ctl.scala 2640:30] + assign io_csr_pkt_legal = _T_1588 | _T_1604; // @[dec_tlu_ctl.scala 2643:26] endmodule module dec_tlu_ctl( input clock, @@ -54209,6 +54206,13 @@ module dec_tlu_ctl( input io_tlu_exu_exu_pmu_i0_br_ataken, input io_tlu_exu_exu_pmu_i0_pc4, input [30:0] io_tlu_exu_exu_npc_r, + input io_tlu_dma_dma_pmu_dccm_read, + input io_tlu_dma_dma_pmu_dccm_write, + input io_tlu_dma_dma_pmu_any_read, + input io_tlu_dma_dma_pmu_any_write, + output [2:0] io_tlu_dma_dec_tlu_dma_qos_prty, + input io_tlu_dma_dma_dccm_stall_any, + input io_tlu_dma_dma_iccm_stall_any, input io_active_clk, input io_free_clk, input io_scan_mode, @@ -54224,12 +54228,6 @@ module dec_tlu_ctl( input io_dec_pmu_presync_stall, input io_dec_pmu_postsync_stall, input io_lsu_store_stall_any, - input io_dma_dccm_stall_any, - input io_dma_iccm_stall_any, - input io_dma_pmu_dccm_read, - input io_dma_pmu_dccm_write, - input io_dma_pmu_any_read, - input io_dma_pmu_any_write, input [30:0] io_lsu_fir_addr, input [1:0] io_lsu_fir_error, input io_iccm_dma_sb_error, @@ -54302,10 +54300,6 @@ module dec_tlu_ctl( output io_trigger_pkt_any_3_execute, output io_trigger_pkt_any_3_m, output [31:0] io_trigger_pkt_any_3_tdata2, - input [7:0] io_pic_claimid, - input [3:0] io_pic_pl, - input io_mhwakeup, - input io_mexintpend, input io_timer_int, input io_soft_int, output io_o_cpu_halt_status, @@ -54319,8 +54313,6 @@ module dec_tlu_ctl( output io_mpc_debug_halt_ack, output io_mpc_debug_run_ack, output io_debug_brkpt_status, - output [3:0] io_dec_tlu_meicurpl, - output [3:0] io_dec_tlu_meipt, output [31:0] io_dec_csr_rddata_d, output io_dec_csr_legal_d, output io_dec_tlu_i0_kill_writeb_wb, @@ -54339,7 +54331,6 @@ module dec_tlu_ctl( output [4:0] io_dec_tlu_exc_cause_wb1, output [31:0] io_dec_tlu_mtval_wb1, output io_dec_tlu_pipelining_disable, - output [2:0] io_dec_tlu_dma_qos_prty, output io_dec_tlu_misc_clk_override, output io_dec_tlu_dec_clk_override, output io_dec_tlu_lsu_clk_override, @@ -54347,6 +54338,7 @@ module dec_tlu_ctl( output io_dec_tlu_pic_clk_override, output io_dec_tlu_dccm_clk_override, output io_dec_tlu_icm_clk_override, + output io_dec_tlu_flush_lower_wb, input io_ifu_pmu_instr_aligned, output io_tlu_bp_dec_tlu_br0_r_pkt_valid, output [1:0] io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist, @@ -54354,7 +54346,6 @@ module dec_tlu_ctl( output io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error, output io_tlu_bp_dec_tlu_br0_r_pkt_bits_way, output io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle, - output io_tlu_bp_dec_tlu_flush_lower_wb, output io_tlu_bp_dec_tlu_flush_leak_one_wb, output io_tlu_bp_dec_tlu_bpred_disable, output io_tlu_ifc_dec_tlu_flush_noredir_wb, @@ -54384,13 +54375,18 @@ module dec_tlu_ctl( input io_tlu_busbuff_lsu_pmu_bus_error, input io_tlu_busbuff_lsu_pmu_bus_busy, output io_tlu_busbuff_dec_tlu_external_ldfwd_disable, - output io_tlu_busbuff_dec_tlu_wb_coalescing_disable, output io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, input io_tlu_busbuff_lsu_imprecise_error_load_any, input io_tlu_busbuff_lsu_imprecise_error_store_any, input [31:0] io_tlu_busbuff_lsu_imprecise_error_addr_any, input io_lsu_tlu_lsu_pmu_load_external_m, - input io_lsu_tlu_lsu_pmu_store_external_m + input io_lsu_tlu_lsu_pmu_store_external_m, + input [7:0] io_dec_pic_pic_claimid, + input [3:0] io_dec_pic_pic_pl, + input io_dec_pic_mhwakeup, + output [3:0] io_dec_pic_dec_tlu_meicurpl, + output [3:0] io_dec_pic_dec_tlu_meipt, + input io_dec_pic_mexintpend ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; @@ -54469,26 +54465,26 @@ module dec_tlu_ctl( reg [31:0] _RAND_73; reg [31:0] _RAND_74; `endif // RANDOMIZE_REG_INIT - wire int_timers_clock; // @[dec_tlu_ctl.scala 279:30] - wire int_timers_reset; // @[dec_tlu_ctl.scala 279:30] - wire int_timers_io_free_clk; // @[dec_tlu_ctl.scala 279:30] - wire int_timers_io_scan_mode; // @[dec_tlu_ctl.scala 279:30] - wire int_timers_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 279:30] - wire [11:0] int_timers_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 279:30] - wire [31:0] int_timers_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 279:30] - wire int_timers_io_csr_mitctl0; // @[dec_tlu_ctl.scala 279:30] - wire int_timers_io_csr_mitctl1; // @[dec_tlu_ctl.scala 279:30] - wire int_timers_io_csr_mitb0; // @[dec_tlu_ctl.scala 279:30] - wire int_timers_io_csr_mitb1; // @[dec_tlu_ctl.scala 279:30] - wire int_timers_io_csr_mitcnt0; // @[dec_tlu_ctl.scala 279:30] - wire int_timers_io_csr_mitcnt1; // @[dec_tlu_ctl.scala 279:30] - wire int_timers_io_dec_pause_state; // @[dec_tlu_ctl.scala 279:30] - wire int_timers_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 279:30] - wire int_timers_io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 279:30] - wire [31:0] int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 279:30] - wire int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 279:30] - wire int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 279:30] - wire int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 279:30] + wire int_timers_clock; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_reset; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_free_clk; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_scan_mode; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 275:30] + wire [11:0] int_timers_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 275:30] + wire [31:0] int_timers_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_csr_mitctl0; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_csr_mitctl1; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_csr_mitb0; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_csr_mitb1; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_csr_mitcnt0; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_csr_mitcnt1; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_dec_pause_state; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_internal_dbg_halt_timers; // @[dec_tlu_ctl.scala 275:30] + wire [31:0] int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 275:30] + wire int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 275:30] wire rvclkhdr_io_l1clk; // @[lib.scala 327:22] wire rvclkhdr_io_clk; // @[lib.scala 327:22] wire rvclkhdr_io_en; // @[lib.scala 327:22] @@ -54505,906 +54501,905 @@ module dec_tlu_ctl( wire rvclkhdr_3_io_clk; // @[lib.scala 327:22] wire rvclkhdr_3_io_en; // @[lib.scala 327:22] wire rvclkhdr_3_io_scan_mode; // @[lib.scala 327:22] - wire csr_clock; // @[dec_tlu_ctl.scala 822:15] - wire csr_reset; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_free_clk; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_active_clk; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_scan_mode; // @[dec_tlu_ctl.scala 822:15] - wire [31:0] csr_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 822:15] - wire [11:0] csr_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 822:15] - wire [11:0] csr_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 822:15] - wire [70:0] csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 822:15] - wire [16:0] csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 822:15] - wire [31:0] csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 822:15] - wire [31:0] csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 822:15] - wire [31:0] csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 822:15] - wire [31:0] csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 822:15] - wire [1:0] csr_io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 822:15] - wire [3:0] csr_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 822:15] - wire [31:0] csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 822:15] - wire [4:0] csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dma_pmu_any_write; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dma_pmu_any_read; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 822:15] - wire [30:0] csr_io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 822:15] - wire [31:0] csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 822:15] - wire [70:0] csr_io_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 822:15] - wire [3:0] csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 822:15] - wire [3:0] csr_io_pic_pl; // @[dec_tlu_ctl.scala 822:15] - wire [3:0] csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 822:15] - wire [29:0] csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 822:15] - wire [7:0] csr_io_pic_claimid; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 822:15] - wire [31:0] csr_io_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 822:15] - wire [31:0] csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_wb_coalescing_disable; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 822:15] - wire [2:0] csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 822:15] - wire [31:0] csr_io_dec_illegal_inst; // @[dec_tlu_ctl.scala 822:15] - wire [3:0] csr_io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_mexintpend; // @[dec_tlu_ctl.scala 822:15] - wire [30:0] csr_io_exu_npc_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 822:15] - wire [30:0] csr_io_rst_vec; // @[dec_tlu_ctl.scala 822:15] - wire [27:0] csr_io_core_id; // @[dec_tlu_ctl.scala 822:15] - wire [31:0] csr_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_rfpc_i0_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 822:15] - wire [1:0] csr_io_mstatus; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_mret_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 822:15] - wire [15:0] csr_io_dcsr; // @[dec_tlu_ctl.scala 822:15] - wire [30:0] csr_io_mtvec; // @[dec_tlu_ctl.scala 822:15] - wire [5:0] csr_io_mip; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_timer_int_sync; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_soft_int_sync; // @[dec_tlu_ctl.scala 822:15] - wire [5:0] csr_io_mie_ns; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_wr_clk; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 822:15] - wire [1:0] csr_io_lsu_fir_error; // @[dec_tlu_ctl.scala 822:15] - wire [30:0] csr_io_npc_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 822:15] - wire [30:0] csr_io_tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 822:15] - wire [30:0] csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_reset_delayed; // @[dec_tlu_ctl.scala 822:15] - wire [30:0] csr_io_mepc; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_interrupt_valid_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_e4e5_int_clk; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_lsu_i0_exc_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_inst_acc_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_inst_acc_second_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_take_nmi; // @[dec_tlu_ctl.scala 822:15] - wire [31:0] csr_io_lsu_error_pkt_addr_r; // @[dec_tlu_ctl.scala 822:15] - wire [4:0] csr_io_exc_cause_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_i0_valid_wb; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_clk_override; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 822:15] - wire [4:0] csr_io_exc_cause_wb; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_ebreak_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_ecall_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_illegal_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_mdseac_locked_ns; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_mdseac_locked_f; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_ic_perr_r_d1; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_debug_halt_req_f; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_force_halt; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_take_ext_int_start; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_trigger_hit_r_d1; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_debug_halt_req; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_allow_dbg_halt_csr_write; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_enter_debug_halt_req; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_request_debug_mode_done; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_request_debug_mode_r; // @[dec_tlu_ctl.scala 822:15] - wire [30:0] csr_io_dpc; // @[dec_tlu_ctl.scala 822:15] - wire [3:0] csr_io_update_hit_bit_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_take_timer_int; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_take_int_timer0_int; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_take_int_timer1_int; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_take_ext_int; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_br0_error_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 822:15] - wire csr_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 822:15] - wire [9:0] csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 822:15] - wire [9:0] csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 822:15] - wire [9:0] csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 822:15] - wire [9:0] csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 822:15] - wire [11:0] csr_read_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 1015:22] - wire csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 1015:22] - reg dbg_halt_state_f; // @[dec_tlu_ctl.scala 371:89] - wire _T = ~dbg_halt_state_f; // @[dec_tlu_ctl.scala 278:39] - reg mpc_halt_state_f; // @[dec_tlu_ctl.scala 366:89] + wire csr_clock; // @[dec_tlu_ctl.scala 818:15] + wire csr_reset; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_free_clk; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_active_clk; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_scan_mode; // @[dec_tlu_ctl.scala 818:15] + wire [31:0] csr_io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 818:15] + wire [11:0] csr_io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 818:15] + wire [11:0] csr_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 818:15] + wire [70:0] csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 818:15] + wire [16:0] csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 818:15] + wire [31:0] csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 818:15] + wire [31:0] csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 818:15] + wire [31:0] csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 818:15] + wire [31:0] csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 818:15] + wire [1:0] csr_io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 818:15] + wire [3:0] csr_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 818:15] + wire [31:0] csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 818:15] + wire [4:0] csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dma_pmu_any_write; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dma_pmu_any_read; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 818:15] + wire [30:0] csr_io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 818:15] + wire [31:0] csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 818:15] + wire [70:0] csr_io_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 818:15] + wire [3:0] csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 818:15] + wire [3:0] csr_io_pic_pl; // @[dec_tlu_ctl.scala 818:15] + wire [3:0] csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 818:15] + wire [29:0] csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 818:15] + wire [7:0] csr_io_pic_claimid; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 818:15] + wire [31:0] csr_io_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 818:15] + wire [31:0] csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 818:15] + wire [2:0] csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 818:15] + wire [31:0] csr_io_dec_illegal_inst; // @[dec_tlu_ctl.scala 818:15] + wire [3:0] csr_io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_mexintpend; // @[dec_tlu_ctl.scala 818:15] + wire [30:0] csr_io_exu_npc_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 818:15] + wire [30:0] csr_io_rst_vec; // @[dec_tlu_ctl.scala 818:15] + wire [27:0] csr_io_core_id; // @[dec_tlu_ctl.scala 818:15] + wire [31:0] csr_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_rfpc_i0_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_i0_trigger_hit_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 818:15] + wire [1:0] csr_io_mstatus; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_exc_or_int_valid_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_mret_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 818:15] + wire [15:0] csr_io_dcsr; // @[dec_tlu_ctl.scala 818:15] + wire [30:0] csr_io_mtvec; // @[dec_tlu_ctl.scala 818:15] + wire [5:0] csr_io_mip; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_timer_int_sync; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_soft_int_sync; // @[dec_tlu_ctl.scala 818:15] + wire [5:0] csr_io_mie_ns; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_wr_clk; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_pmu_fw_halted; // @[dec_tlu_ctl.scala 818:15] + wire [1:0] csr_io_lsu_fir_error; // @[dec_tlu_ctl.scala 818:15] + wire [30:0] csr_io_npc_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 818:15] + wire [30:0] csr_io_tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 818:15] + wire [30:0] csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_reset_delayed; // @[dec_tlu_ctl.scala 818:15] + wire [30:0] csr_io_mepc; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_interrupt_valid_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_i0_exception_valid_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_lsu_exc_valid_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_e4e5_int_clk; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_lsu_i0_exc_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_inst_acc_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_inst_acc_second_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_take_nmi; // @[dec_tlu_ctl.scala 818:15] + wire [31:0] csr_io_lsu_error_pkt_addr_r; // @[dec_tlu_ctl.scala 818:15] + wire [4:0] csr_io_exc_cause_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_i0_valid_wb; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_clk_override; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 818:15] + wire [4:0] csr_io_exc_cause_wb; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_nmi_lsu_store_type; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_nmi_lsu_load_type; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_tlu_i0_commit_cmt; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_ebreak_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_ecall_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_illegal_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_mdseac_locked_ns; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_mdseac_locked_f; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_nmi_int_detected_f; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_ext_int_freeze_d1; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_ic_perr_r_d1; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_lsu_idle_any_f; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dbg_tlu_halted; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_debug_halt_req_f; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_force_halt; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_take_ext_int_start; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_trigger_hit_r_d1; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_debug_halt_req; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_allow_dbg_halt_csr_write; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_internal_dbg_halt_mode_f; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_enter_debug_halt_req; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_request_debug_mode_done; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_request_debug_mode_r; // @[dec_tlu_ctl.scala 818:15] + wire [30:0] csr_io_dpc; // @[dec_tlu_ctl.scala 818:15] + wire [3:0] csr_io_update_hit_bit_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_take_timer_int; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_take_int_timer0_int; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_take_int_timer1_int; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_take_ext_int; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_br0_error_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_br0_start_error_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 818:15] + wire [9:0] csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 818:15] + wire [9:0] csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 818:15] + wire [9:0] csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 818:15] + wire [9:0] csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 818:15] + wire [11:0] csr_read_io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 1011:22] + wire csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 1011:22] + reg dbg_halt_state_f; // @[dec_tlu_ctl.scala 367:89] + wire _T = ~dbg_halt_state_f; // @[dec_tlu_ctl.scala 274:39] + reg mpc_halt_state_f; // @[dec_tlu_ctl.scala 362:89] wire [2:0] _T_3 = {io_i_cpu_run_req,io_mpc_debug_halt_req,io_mpc_debug_run_req}; // @[Cat.scala 29:58] wire [3:0] _T_6 = {io_nmi_int,io_timer_int,io_soft_int,io_i_cpu_halt_req}; // @[Cat.scala 29:58] reg [6:0] _T_8; // @[lib.scala 21:81] reg [6:0] syncro_ff; // @[lib.scala 21:58] - wire nmi_int_sync = syncro_ff[6]; // @[dec_tlu_ctl.scala 306:67] - wire i_cpu_halt_req_sync = syncro_ff[3]; // @[dec_tlu_ctl.scala 309:59] - wire i_cpu_run_req_sync = syncro_ff[2]; // @[dec_tlu_ctl.scala 310:59] - wire mpc_debug_halt_req_sync_raw = syncro_ff[1]; // @[dec_tlu_ctl.scala 311:51] - wire mpc_debug_run_req_sync = syncro_ff[0]; // @[dec_tlu_ctl.scala 312:51] - wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 1008:31] - reg lsu_exc_valid_r_d1; // @[dec_tlu_ctl.scala 617:74] - wire _T_11 = io_lsu_error_pkt_r_valid | lsu_exc_valid_r_d1; // @[dec_tlu_ctl.scala 316:67] - reg e5_valid; // @[dec_tlu_ctl.scala 328:97] - wire e4e5_valid = io_dec_tlu_i0_valid_r | e5_valid; // @[dec_tlu_ctl.scala 319:30] - reg debug_mode_status; // @[dec_tlu_ctl.scala 329:81] - reg i_cpu_run_req_d1_raw; // @[dec_tlu_ctl.scala 577:80] - reg nmi_int_delayed; // @[dec_tlu_ctl.scala 344:72] - wire _T_37 = ~nmi_int_delayed; // @[dec_tlu_ctl.scala 353:45] - wire _T_38 = nmi_int_sync & _T_37; // @[dec_tlu_ctl.scala 353:43] - reg mdseac_locked_f; // @[dec_tlu_ctl.scala 610:89] - wire _T_35 = ~mdseac_locked_f; // @[dec_tlu_ctl.scala 351:32] - wire _T_36 = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 351:96] - wire nmi_lsu_detected = _T_35 & _T_36; // @[dec_tlu_ctl.scala 351:49] - wire _T_39 = _T_38 | nmi_lsu_detected; // @[dec_tlu_ctl.scala 353:63] - reg nmi_int_detected_f; // @[dec_tlu_ctl.scala 345:72] - reg take_nmi_r_d1; // @[dec_tlu_ctl.scala 819:98] - wire _T_40 = ~take_nmi_r_d1; // @[dec_tlu_ctl.scala 353:106] - wire _T_41 = nmi_int_detected_f & _T_40; // @[dec_tlu_ctl.scala 353:104] - wire _T_42 = _T_39 | _T_41; // @[dec_tlu_ctl.scala 353:82] - reg take_ext_int_start_d3; // @[dec_tlu_ctl.scala 750:62] - wire _T_43 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 353:165] - wire _T_44 = take_ext_int_start_d3 & _T_43; // @[dec_tlu_ctl.scala 353:146] - wire nmi_int_detected = _T_42 | _T_44; // @[dec_tlu_ctl.scala 353:122] - wire _T_631 = ~io_dec_csr_stall_int_ff; // @[dec_tlu_ctl.scala 727:23] - wire mstatus_mie_ns = csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 1007:31] - wire _T_632 = _T_631 & mstatus_mie_ns; // @[dec_tlu_ctl.scala 727:48] - wire [5:0] mip = csr_io_mip; // @[dec_tlu_ctl.scala 1013:31] - wire _T_634 = _T_632 & mip[1]; // @[dec_tlu_ctl.scala 727:65] - wire [5:0] mie_ns = csr_io_mie_ns; // @[dec_tlu_ctl.scala 1002:31] - wire timer_int_ready = _T_634 & mie_ns[1]; // @[dec_tlu_ctl.scala 727:83] - wire _T_391 = nmi_int_detected | timer_int_ready; // @[dec_tlu_ctl.scala 604:66] - wire _T_628 = _T_632 & mip[0]; // @[dec_tlu_ctl.scala 726:65] - wire soft_int_ready = _T_628 & mie_ns[0]; // @[dec_tlu_ctl.scala 726:83] - wire _T_392 = _T_391 | soft_int_ready; // @[dec_tlu_ctl.scala 604:84] - reg int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 584:73] - wire _T_393 = _T_392 | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 604:101] - reg int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 585:73] - wire _T_394 = _T_393 | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 604:125] - wire _T_608 = _T_632 & mip[2]; // @[dec_tlu_ctl.scala 723:66] - wire mhwakeup_ready = _T_608 & mie_ns[2]; // @[dec_tlu_ctl.scala 723:84] - wire _T_395 = io_mhwakeup & mhwakeup_ready; // @[dec_tlu_ctl.scala 604:164] - wire _T_396 = _T_394 | _T_395; // @[dec_tlu_ctl.scala 604:149] - wire _T_397 = _T_396 & io_o_cpu_halt_status; // @[dec_tlu_ctl.scala 604:183] - reg i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 576:80] - wire _T_398 = ~i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 604:208] - wire _T_399 = _T_397 & _T_398; // @[dec_tlu_ctl.scala 604:206] - wire i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | _T_399; // @[dec_tlu_ctl.scala 604:45] - wire _T_14 = debug_mode_status | i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 320:50] - wire _T_685 = ~_T_43; // @[dec_tlu_ctl.scala 755:49] - wire take_ext_int = take_ext_int_start_d3 & _T_685; // @[dec_tlu_ctl.scala 755:47] - wire _T_698 = ~soft_int_ready; // @[dec_tlu_ctl.scala 772:40] - wire _T_699 = timer_int_ready & _T_698; // @[dec_tlu_ctl.scala 772:38] - wire _T_617 = ~io_lsu_fastint_stall_any; // @[dec_tlu_ctl.scala 724:104] - wire ext_int_ready = mhwakeup_ready & _T_617; // @[dec_tlu_ctl.scala 724:102] - wire _T_700 = ~ext_int_ready; // @[dec_tlu_ctl.scala 772:58] - wire _T_701 = _T_699 & _T_700; // @[dec_tlu_ctl.scala 772:56] - wire _T_622 = _T_632 & mip[5]; // @[dec_tlu_ctl.scala 725:65] - wire ce_int_ready = _T_622 & mie_ns[5]; // @[dec_tlu_ctl.scala 725:83] - wire _T_702 = ~ce_int_ready; // @[dec_tlu_ctl.scala 772:75] - wire _T_703 = _T_701 & _T_702; // @[dec_tlu_ctl.scala 772:73] - wire _T_152 = ~debug_mode_status; // @[dec_tlu_ctl.scala 427:37] - reg dbg_halt_req_held; // @[dec_tlu_ctl.scala 470:81] - wire _T_106 = io_dbg_halt_req | dbg_halt_req_held; // @[dec_tlu_ctl.scala 404:48] - reg ext_int_freeze_d1; // @[dec_tlu_ctl.scala 751:66] - wire _T_107 = ~ext_int_freeze_d1; // @[dec_tlu_ctl.scala 404:71] - wire dbg_halt_req_final = _T_106 & _T_107; // @[dec_tlu_ctl.scala 404:69] - wire mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & _T_107; // @[dec_tlu_ctl.scala 363:67] - wire _T_109 = dbg_halt_req_final | mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 407:50] - reg reset_detect; // @[dec_tlu_ctl.scala 340:88] - reg reset_detected; // @[dec_tlu_ctl.scala 341:88] - wire reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 342:64] - wire _T_110 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 407:95] - wire _T_111 = reset_delayed & _T_110; // @[dec_tlu_ctl.scala 407:93] - wire _T_112 = _T_109 | _T_111; // @[dec_tlu_ctl.scala 407:76] - wire _T_114 = _T_112 & _T_152; // @[dec_tlu_ctl.scala 407:119] - wire debug_halt_req = _T_114 & _T_107; // @[dec_tlu_ctl.scala 407:147] - wire _T_153 = _T_152 & debug_halt_req; // @[dec_tlu_ctl.scala 427:63] - reg dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 462:81] - wire _T_154 = _T_153 | dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 427:81] - reg trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 461:81] - wire _T_155 = _T_154 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 427:107] - reg ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 676:64] - wire enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 427:132] - reg debug_halt_req_f; // @[dec_tlu_ctl.scala 459:89] - wire force_halt = csr_io_force_halt; // @[dec_tlu_ctl.scala 1005:31] - reg lsu_idle_any_f; // @[dec_tlu_ctl.scala 455:89] - wire _T_142 = io_lsu_idle_any & lsu_idle_any_f; // @[dec_tlu_ctl.scala 421:53] - wire _T_143 = _T_142 & io_tlu_mem_ifu_miss_state_idle; // @[dec_tlu_ctl.scala 421:70] - reg ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 456:81] - wire _T_144 = _T_143 & ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 421:103] - wire _T_145 = ~debug_halt_req; // @[dec_tlu_ctl.scala 421:129] - wire _T_146 = _T_144 & _T_145; // @[dec_tlu_ctl.scala 421:127] - reg debug_halt_req_d1; // @[dec_tlu_ctl.scala 463:89] - wire _T_147 = ~debug_halt_req_d1; // @[dec_tlu_ctl.scala 421:147] - wire _T_148 = _T_146 & _T_147; // @[dec_tlu_ctl.scala 421:145] - wire _T_149 = ~io_dec_div_active; // @[dec_tlu_ctl.scala 421:168] - wire _T_150 = _T_148 & _T_149; // @[dec_tlu_ctl.scala 421:166] - wire core_empty = force_halt | _T_150; // @[dec_tlu_ctl.scala 421:34] - wire _T_163 = debug_halt_req_f & core_empty; // @[dec_tlu_ctl.scala 437:48] - reg dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 453:81] - reg dec_tlu_flush_pause_r_d1; // @[dec_tlu_ctl.scala 469:73] - wire _T_132 = ~dec_tlu_flush_pause_r_d1; // @[dec_tlu_ctl.scala 417:56] - wire _T_133 = dec_tlu_flush_noredir_r_d1 & _T_132; // @[dec_tlu_ctl.scala 417:54] - reg take_ext_int_start_d1; // @[dec_tlu_ctl.scala 748:62] - wire _T_134 = ~take_ext_int_start_d1; // @[dec_tlu_ctl.scala 417:84] - wire _T_135 = _T_133 & _T_134; // @[dec_tlu_ctl.scala 417:82] - reg halt_taken_f; // @[dec_tlu_ctl.scala 454:89] - reg dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 457:89] - wire _T_136 = ~dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 417:126] - wire _T_137 = halt_taken_f & _T_136; // @[dec_tlu_ctl.scala 417:124] - reg pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 583:73] - wire _T_138 = ~pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 417:146] - wire _T_139 = _T_137 & _T_138; // @[dec_tlu_ctl.scala 417:144] - reg interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 813:90] - wire _T_140 = ~interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 417:169] - wire _T_141 = _T_139 & _T_140; // @[dec_tlu_ctl.scala 417:167] - wire halt_taken = _T_135 | _T_141; // @[dec_tlu_ctl.scala 417:108] - wire _T_164 = _T_163 & halt_taken; // @[dec_tlu_ctl.scala 437:61] - reg debug_resume_req_f; // @[dec_tlu_ctl.scala 460:89] - wire _T_165 = ~debug_resume_req_f; // @[dec_tlu_ctl.scala 437:97] - wire _T_166 = dbg_tlu_halted_f & _T_165; // @[dec_tlu_ctl.scala 437:95] - wire dbg_tlu_halted = _T_164 | _T_166; // @[dec_tlu_ctl.scala 437:75] - wire _T_167 = ~dbg_tlu_halted; // @[dec_tlu_ctl.scala 438:73] - wire _T_168 = debug_halt_req_f & _T_167; // @[dec_tlu_ctl.scala 438:71] - wire debug_halt_req_ns = enter_debug_halt_req | _T_168; // @[dec_tlu_ctl.scala 438:51] - wire [15:0] dcsr = csr_io_dcsr; // @[dec_tlu_ctl.scala 1011:31] - wire _T_157 = ~dcsr[2]; // @[dec_tlu_ctl.scala 430:106] - wire _T_158 = debug_resume_req_f & _T_157; // @[dec_tlu_ctl.scala 430:104] - wire _T_159 = ~_T_158; // @[dec_tlu_ctl.scala 430:83] - wire _T_160 = debug_mode_status & _T_159; // @[dec_tlu_ctl.scala 430:81] - wire internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[dec_tlu_ctl.scala 430:53] - wire _T_177 = debug_resume_req_f & dcsr[2]; // @[dec_tlu_ctl.scala 443:60] - reg dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 468:73] - wire _T_178 = ~dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 443:111] - wire _T_179 = dcsr_single_step_running_f & _T_178; // @[dec_tlu_ctl.scala 443:109] - wire dcsr_single_step_running = _T_177 | _T_179; // @[dec_tlu_ctl.scala 443:79] - wire _T_665 = ~dcsr_single_step_running; // @[dec_tlu_ctl.scala 744:55] - wire _T_666 = _T_665 | io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 744:81] - wire _T_667 = internal_dbg_halt_mode & _T_666; // @[dec_tlu_ctl.scala 744:52] - wire _T_346 = ~io_dec_tlu_debug_mode; // @[dec_tlu_ctl.scala 573:62] - wire _T_347 = i_cpu_halt_req_sync & _T_346; // @[dec_tlu_ctl.scala 573:60] - wire i_cpu_halt_req_sync_qual = _T_347 & _T_107; // @[dec_tlu_ctl.scala 573:85] - wire ext_halt_pulse = i_cpu_halt_req_sync_qual & _T_398; // @[dec_tlu_ctl.scala 589:50] - wire fw_halt_req = csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 1009:31] - wire enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req; // @[dec_tlu_ctl.scala 590:48] - reg pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 582:73] - wire _T_371 = pmu_fw_halt_req_f & core_empty; // @[dec_tlu_ctl.scala 595:45] - wire _T_372 = _T_371 & halt_taken; // @[dec_tlu_ctl.scala 595:58] - wire _T_373 = ~enter_debug_halt_req; // @[dec_tlu_ctl.scala 595:73] - wire _T_374 = _T_372 & _T_373; // @[dec_tlu_ctl.scala 595:71] - wire _T_375 = ~i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 595:121] - wire _T_376 = pmu_fw_tlu_halted_f & _T_375; // @[dec_tlu_ctl.scala 595:119] - wire _T_377 = _T_374 | _T_376; // @[dec_tlu_ctl.scala 595:96] - wire _T_378 = ~debug_halt_req_f; // @[dec_tlu_ctl.scala 595:143] - wire pmu_fw_tlu_halted = _T_377 & _T_378; // @[dec_tlu_ctl.scala 595:141] - wire _T_361 = ~pmu_fw_tlu_halted; // @[dec_tlu_ctl.scala 591:72] - wire _T_362 = pmu_fw_halt_req_f & _T_361; // @[dec_tlu_ctl.scala 591:70] - wire _T_363 = enter_pmu_fw_halt_req | _T_362; // @[dec_tlu_ctl.scala 591:49] - wire pmu_fw_halt_req_ns = _T_363 & _T_378; // @[dec_tlu_ctl.scala 591:93] - reg internal_pmu_fw_halt_mode_f; // @[dec_tlu_ctl.scala 581:68] - wire _T_367 = internal_pmu_fw_halt_mode_f & _T_375; // @[dec_tlu_ctl.scala 592:83] - wire _T_369 = _T_367 & _T_378; // @[dec_tlu_ctl.scala 592:103] - wire internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | _T_369; // @[dec_tlu_ctl.scala 592:52] - wire _T_668 = _T_667 | internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 744:107] - wire _T_669 = _T_668 | i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 744:135] - wire _T_738 = ~internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 776:35] - wire _T_739 = nmi_int_detected & _T_738; // @[dec_tlu_ctl.scala 776:33] - wire _T_740 = ~internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 776:65] - wire _T_742 = dcsr_single_step_running_f & dcsr[11]; // @[dec_tlu_ctl.scala 776:119] - wire _T_743 = ~io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 776:141] - wire _T_744 = _T_742 & _T_743; // @[dec_tlu_ctl.scala 776:139] - wire _T_746 = _T_744 & _T_178; // @[dec_tlu_ctl.scala 776:164] - wire _T_747 = _T_740 | _T_746; // @[dec_tlu_ctl.scala 776:89] - wire _T_748 = _T_739 & _T_747; // @[dec_tlu_ctl.scala 776:62] - wire _T_463 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h8; // @[dec_tlu_ctl.scala 662:51] - wire _T_464 = _T_463 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 662:64] - wire _T_297 = io_tlu_bp_dec_tlu_flush_lower_wb | io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 524:65] + wire nmi_int_sync = syncro_ff[6]; // @[dec_tlu_ctl.scala 302:67] + wire i_cpu_halt_req_sync = syncro_ff[3]; // @[dec_tlu_ctl.scala 305:59] + wire i_cpu_run_req_sync = syncro_ff[2]; // @[dec_tlu_ctl.scala 306:59] + wire mpc_debug_halt_req_sync_raw = syncro_ff[1]; // @[dec_tlu_ctl.scala 307:51] + wire mpc_debug_run_req_sync = syncro_ff[0]; // @[dec_tlu_ctl.scala 308:51] + wire dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 1004:31] + reg lsu_exc_valid_r_d1; // @[dec_tlu_ctl.scala 613:74] + wire _T_11 = io_lsu_error_pkt_r_valid | lsu_exc_valid_r_d1; // @[dec_tlu_ctl.scala 312:67] + reg e5_valid; // @[dec_tlu_ctl.scala 324:97] + wire e4e5_valid = io_dec_tlu_i0_valid_r | e5_valid; // @[dec_tlu_ctl.scala 315:30] + reg debug_mode_status; // @[dec_tlu_ctl.scala 325:81] + reg i_cpu_run_req_d1_raw; // @[dec_tlu_ctl.scala 573:80] + reg nmi_int_delayed; // @[dec_tlu_ctl.scala 340:72] + wire _T_37 = ~nmi_int_delayed; // @[dec_tlu_ctl.scala 349:45] + wire _T_38 = nmi_int_sync & _T_37; // @[dec_tlu_ctl.scala 349:43] + reg mdseac_locked_f; // @[dec_tlu_ctl.scala 606:89] + wire _T_35 = ~mdseac_locked_f; // @[dec_tlu_ctl.scala 347:32] + wire _T_36 = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 347:96] + wire nmi_lsu_detected = _T_35 & _T_36; // @[dec_tlu_ctl.scala 347:49] + wire _T_39 = _T_38 | nmi_lsu_detected; // @[dec_tlu_ctl.scala 349:63] + reg nmi_int_detected_f; // @[dec_tlu_ctl.scala 341:72] + reg take_nmi_r_d1; // @[dec_tlu_ctl.scala 815:98] + wire _T_40 = ~take_nmi_r_d1; // @[dec_tlu_ctl.scala 349:106] + wire _T_41 = nmi_int_detected_f & _T_40; // @[dec_tlu_ctl.scala 349:104] + wire _T_42 = _T_39 | _T_41; // @[dec_tlu_ctl.scala 349:82] + reg take_ext_int_start_d3; // @[dec_tlu_ctl.scala 746:62] + wire _T_43 = |io_lsu_fir_error; // @[dec_tlu_ctl.scala 349:165] + wire _T_44 = take_ext_int_start_d3 & _T_43; // @[dec_tlu_ctl.scala 349:146] + wire nmi_int_detected = _T_42 | _T_44; // @[dec_tlu_ctl.scala 349:122] + wire _T_631 = ~io_dec_csr_stall_int_ff; // @[dec_tlu_ctl.scala 723:23] + wire mstatus_mie_ns = csr_io_mstatus_mie_ns; // @[dec_tlu_ctl.scala 1003:31] + wire _T_632 = _T_631 & mstatus_mie_ns; // @[dec_tlu_ctl.scala 723:48] + wire [5:0] mip = csr_io_mip; // @[dec_tlu_ctl.scala 1009:31] + wire _T_634 = _T_632 & mip[1]; // @[dec_tlu_ctl.scala 723:65] + wire [5:0] mie_ns = csr_io_mie_ns; // @[dec_tlu_ctl.scala 998:31] + wire timer_int_ready = _T_634 & mie_ns[1]; // @[dec_tlu_ctl.scala 723:83] + wire _T_391 = nmi_int_detected | timer_int_ready; // @[dec_tlu_ctl.scala 600:66] + wire _T_628 = _T_632 & mip[0]; // @[dec_tlu_ctl.scala 722:65] + wire soft_int_ready = _T_628 & mie_ns[0]; // @[dec_tlu_ctl.scala 722:83] + wire _T_392 = _T_391 | soft_int_ready; // @[dec_tlu_ctl.scala 600:84] + reg int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 580:73] + wire _T_393 = _T_392 | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 600:101] + reg int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 581:73] + wire _T_394 = _T_393 | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 600:125] + wire _T_608 = _T_632 & mip[2]; // @[dec_tlu_ctl.scala 719:66] + wire mhwakeup_ready = _T_608 & mie_ns[2]; // @[dec_tlu_ctl.scala 719:84] + wire _T_395 = io_dec_pic_mhwakeup & mhwakeup_ready; // @[dec_tlu_ctl.scala 600:172] + wire _T_396 = _T_394 | _T_395; // @[dec_tlu_ctl.scala 600:149] + wire _T_397 = _T_396 & io_o_cpu_halt_status; // @[dec_tlu_ctl.scala 600:191] + reg i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 572:80] + wire _T_398 = ~i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 600:216] + wire _T_399 = _T_397 & _T_398; // @[dec_tlu_ctl.scala 600:214] + wire i_cpu_run_req_d1 = i_cpu_run_req_d1_raw | _T_399; // @[dec_tlu_ctl.scala 600:45] + wire _T_14 = debug_mode_status | i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 316:50] + wire _T_685 = ~_T_43; // @[dec_tlu_ctl.scala 751:49] + wire take_ext_int = take_ext_int_start_d3 & _T_685; // @[dec_tlu_ctl.scala 751:47] + wire _T_698 = ~soft_int_ready; // @[dec_tlu_ctl.scala 768:40] + wire _T_699 = timer_int_ready & _T_698; // @[dec_tlu_ctl.scala 768:38] + wire _T_617 = ~io_lsu_fastint_stall_any; // @[dec_tlu_ctl.scala 720:104] + wire ext_int_ready = mhwakeup_ready & _T_617; // @[dec_tlu_ctl.scala 720:102] + wire _T_700 = ~ext_int_ready; // @[dec_tlu_ctl.scala 768:58] + wire _T_701 = _T_699 & _T_700; // @[dec_tlu_ctl.scala 768:56] + wire _T_622 = _T_632 & mip[5]; // @[dec_tlu_ctl.scala 721:65] + wire ce_int_ready = _T_622 & mie_ns[5]; // @[dec_tlu_ctl.scala 721:83] + wire _T_702 = ~ce_int_ready; // @[dec_tlu_ctl.scala 768:75] + wire _T_703 = _T_701 & _T_702; // @[dec_tlu_ctl.scala 768:73] + wire _T_152 = ~debug_mode_status; // @[dec_tlu_ctl.scala 423:37] + reg dbg_halt_req_held; // @[dec_tlu_ctl.scala 466:81] + wire _T_106 = io_dbg_halt_req | dbg_halt_req_held; // @[dec_tlu_ctl.scala 400:48] + reg ext_int_freeze_d1; // @[dec_tlu_ctl.scala 747:66] + wire _T_107 = ~ext_int_freeze_d1; // @[dec_tlu_ctl.scala 400:71] + wire dbg_halt_req_final = _T_106 & _T_107; // @[dec_tlu_ctl.scala 400:69] + wire mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & _T_107; // @[dec_tlu_ctl.scala 359:67] + wire _T_109 = dbg_halt_req_final | mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 403:50] + reg reset_detect; // @[dec_tlu_ctl.scala 336:88] + reg reset_detected; // @[dec_tlu_ctl.scala 337:88] + wire reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 338:64] + wire _T_110 = ~io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 403:95] + wire _T_111 = reset_delayed & _T_110; // @[dec_tlu_ctl.scala 403:93] + wire _T_112 = _T_109 | _T_111; // @[dec_tlu_ctl.scala 403:76] + wire _T_114 = _T_112 & _T_152; // @[dec_tlu_ctl.scala 403:119] + wire debug_halt_req = _T_114 & _T_107; // @[dec_tlu_ctl.scala 403:147] + wire _T_153 = _T_152 & debug_halt_req; // @[dec_tlu_ctl.scala 423:63] + reg dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 458:81] + wire _T_154 = _T_153 | dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 423:81] + reg trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 457:81] + wire _T_155 = _T_154 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 423:107] + reg ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 672:64] + wire enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 423:132] + reg debug_halt_req_f; // @[dec_tlu_ctl.scala 455:89] + wire force_halt = csr_io_force_halt; // @[dec_tlu_ctl.scala 1001:31] + reg lsu_idle_any_f; // @[dec_tlu_ctl.scala 451:89] + wire _T_142 = io_lsu_idle_any & lsu_idle_any_f; // @[dec_tlu_ctl.scala 417:53] + wire _T_143 = _T_142 & io_tlu_mem_ifu_miss_state_idle; // @[dec_tlu_ctl.scala 417:70] + reg ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 452:81] + wire _T_144 = _T_143 & ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 417:103] + wire _T_145 = ~debug_halt_req; // @[dec_tlu_ctl.scala 417:129] + wire _T_146 = _T_144 & _T_145; // @[dec_tlu_ctl.scala 417:127] + reg debug_halt_req_d1; // @[dec_tlu_ctl.scala 459:89] + wire _T_147 = ~debug_halt_req_d1; // @[dec_tlu_ctl.scala 417:147] + wire _T_148 = _T_146 & _T_147; // @[dec_tlu_ctl.scala 417:145] + wire _T_149 = ~io_dec_div_active; // @[dec_tlu_ctl.scala 417:168] + wire _T_150 = _T_148 & _T_149; // @[dec_tlu_ctl.scala 417:166] + wire core_empty = force_halt | _T_150; // @[dec_tlu_ctl.scala 417:34] + wire _T_163 = debug_halt_req_f & core_empty; // @[dec_tlu_ctl.scala 433:48] + reg dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 449:81] + reg dec_tlu_flush_pause_r_d1; // @[dec_tlu_ctl.scala 465:73] + wire _T_132 = ~dec_tlu_flush_pause_r_d1; // @[dec_tlu_ctl.scala 413:56] + wire _T_133 = dec_tlu_flush_noredir_r_d1 & _T_132; // @[dec_tlu_ctl.scala 413:54] + reg take_ext_int_start_d1; // @[dec_tlu_ctl.scala 744:62] + wire _T_134 = ~take_ext_int_start_d1; // @[dec_tlu_ctl.scala 413:84] + wire _T_135 = _T_133 & _T_134; // @[dec_tlu_ctl.scala 413:82] + reg halt_taken_f; // @[dec_tlu_ctl.scala 450:89] + reg dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 453:89] + wire _T_136 = ~dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 413:126] + wire _T_137 = halt_taken_f & _T_136; // @[dec_tlu_ctl.scala 413:124] + reg pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 579:73] + wire _T_138 = ~pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 413:146] + wire _T_139 = _T_137 & _T_138; // @[dec_tlu_ctl.scala 413:144] + reg interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 809:90] + wire _T_140 = ~interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 413:169] + wire _T_141 = _T_139 & _T_140; // @[dec_tlu_ctl.scala 413:167] + wire halt_taken = _T_135 | _T_141; // @[dec_tlu_ctl.scala 413:108] + wire _T_164 = _T_163 & halt_taken; // @[dec_tlu_ctl.scala 433:61] + reg debug_resume_req_f; // @[dec_tlu_ctl.scala 456:89] + wire _T_165 = ~debug_resume_req_f; // @[dec_tlu_ctl.scala 433:97] + wire _T_166 = dbg_tlu_halted_f & _T_165; // @[dec_tlu_ctl.scala 433:95] + wire dbg_tlu_halted = _T_164 | _T_166; // @[dec_tlu_ctl.scala 433:75] + wire _T_167 = ~dbg_tlu_halted; // @[dec_tlu_ctl.scala 434:73] + wire _T_168 = debug_halt_req_f & _T_167; // @[dec_tlu_ctl.scala 434:71] + wire debug_halt_req_ns = enter_debug_halt_req | _T_168; // @[dec_tlu_ctl.scala 434:51] + wire [15:0] dcsr = csr_io_dcsr; // @[dec_tlu_ctl.scala 1007:31] + wire _T_157 = ~dcsr[2]; // @[dec_tlu_ctl.scala 426:106] + wire _T_158 = debug_resume_req_f & _T_157; // @[dec_tlu_ctl.scala 426:104] + wire _T_159 = ~_T_158; // @[dec_tlu_ctl.scala 426:83] + wire _T_160 = debug_mode_status & _T_159; // @[dec_tlu_ctl.scala 426:81] + wire internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[dec_tlu_ctl.scala 426:53] + wire _T_177 = debug_resume_req_f & dcsr[2]; // @[dec_tlu_ctl.scala 439:60] + reg dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 464:73] + wire _T_178 = ~dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 439:111] + wire _T_179 = dcsr_single_step_running_f & _T_178; // @[dec_tlu_ctl.scala 439:109] + wire dcsr_single_step_running = _T_177 | _T_179; // @[dec_tlu_ctl.scala 439:79] + wire _T_665 = ~dcsr_single_step_running; // @[dec_tlu_ctl.scala 740:55] + wire _T_666 = _T_665 | io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 740:81] + wire _T_667 = internal_dbg_halt_mode & _T_666; // @[dec_tlu_ctl.scala 740:52] + wire _T_346 = ~io_dec_tlu_debug_mode; // @[dec_tlu_ctl.scala 569:62] + wire _T_347 = i_cpu_halt_req_sync & _T_346; // @[dec_tlu_ctl.scala 569:60] + wire i_cpu_halt_req_sync_qual = _T_347 & _T_107; // @[dec_tlu_ctl.scala 569:85] + wire ext_halt_pulse = i_cpu_halt_req_sync_qual & _T_398; // @[dec_tlu_ctl.scala 585:50] + wire fw_halt_req = csr_io_fw_halt_req; // @[dec_tlu_ctl.scala 1005:31] + wire enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req; // @[dec_tlu_ctl.scala 586:48] + reg pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 578:73] + wire _T_371 = pmu_fw_halt_req_f & core_empty; // @[dec_tlu_ctl.scala 591:45] + wire _T_372 = _T_371 & halt_taken; // @[dec_tlu_ctl.scala 591:58] + wire _T_373 = ~enter_debug_halt_req; // @[dec_tlu_ctl.scala 591:73] + wire _T_374 = _T_372 & _T_373; // @[dec_tlu_ctl.scala 591:71] + wire _T_375 = ~i_cpu_run_req_d1; // @[dec_tlu_ctl.scala 591:121] + wire _T_376 = pmu_fw_tlu_halted_f & _T_375; // @[dec_tlu_ctl.scala 591:119] + wire _T_377 = _T_374 | _T_376; // @[dec_tlu_ctl.scala 591:96] + wire _T_378 = ~debug_halt_req_f; // @[dec_tlu_ctl.scala 591:143] + wire pmu_fw_tlu_halted = _T_377 & _T_378; // @[dec_tlu_ctl.scala 591:141] + wire _T_361 = ~pmu_fw_tlu_halted; // @[dec_tlu_ctl.scala 587:72] + wire _T_362 = pmu_fw_halt_req_f & _T_361; // @[dec_tlu_ctl.scala 587:70] + wire _T_363 = enter_pmu_fw_halt_req | _T_362; // @[dec_tlu_ctl.scala 587:49] + wire pmu_fw_halt_req_ns = _T_363 & _T_378; // @[dec_tlu_ctl.scala 587:93] + reg internal_pmu_fw_halt_mode_f; // @[dec_tlu_ctl.scala 577:68] + wire _T_367 = internal_pmu_fw_halt_mode_f & _T_375; // @[dec_tlu_ctl.scala 588:83] + wire _T_369 = _T_367 & _T_378; // @[dec_tlu_ctl.scala 588:103] + wire internal_pmu_fw_halt_mode = pmu_fw_halt_req_ns | _T_369; // @[dec_tlu_ctl.scala 588:52] + wire _T_668 = _T_667 | internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 740:107] + wire _T_669 = _T_668 | i_cpu_halt_req_d1; // @[dec_tlu_ctl.scala 740:135] + wire _T_738 = ~internal_pmu_fw_halt_mode; // @[dec_tlu_ctl.scala 772:35] + wire _T_739 = nmi_int_detected & _T_738; // @[dec_tlu_ctl.scala 772:33] + wire _T_740 = ~internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 772:65] + wire _T_742 = dcsr_single_step_running_f & dcsr[11]; // @[dec_tlu_ctl.scala 772:119] + wire _T_743 = ~io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 772:141] + wire _T_744 = _T_742 & _T_743; // @[dec_tlu_ctl.scala 772:139] + wire _T_746 = _T_744 & _T_178; // @[dec_tlu_ctl.scala 772:164] + wire _T_747 = _T_740 | _T_746; // @[dec_tlu_ctl.scala 772:89] + wire _T_748 = _T_739 & _T_747; // @[dec_tlu_ctl.scala 772:62] + wire _T_463 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h8; // @[dec_tlu_ctl.scala 658:51] + wire _T_464 = _T_463 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 658:64] + wire _T_297 = io_dec_tlu_flush_lower_wb | io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 520:58] wire [3:0] _T_299 = _T_297 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_300 = ~_T_299; // @[dec_tlu_ctl.scala 524:23] + wire [3:0] _T_300 = ~_T_299; // @[dec_tlu_ctl.scala 520:23] wire [3:0] _T_292 = io_dec_tlu_i0_valid_r ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_294 = _T_292 & io_dec_tlu_packet_r_i0trigger; // @[dec_tlu_ctl.scala 522:53] - wire [9:0] mtdata1_t_3 = csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 160:67 dec_tlu_ctl.scala 1014:33] - wire [9:0] mtdata1_t_2 = csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 160:67 dec_tlu_ctl.scala 1014:33] - wire [9:0] mtdata1_t_1 = csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 160:67 dec_tlu_ctl.scala 1014:33] - wire [9:0] mtdata1_t_0 = csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 160:67 dec_tlu_ctl.scala 1014:33] + wire [3:0] _T_294 = _T_292 & io_dec_tlu_packet_r_i0trigger; // @[dec_tlu_ctl.scala 518:53] + wire [9:0] mtdata1_t_3 = csr_io_mtdata1_t_3; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1010:33] + wire [9:0] mtdata1_t_2 = csr_io_mtdata1_t_2; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1010:33] + wire [9:0] mtdata1_t_1 = csr_io_mtdata1_t_1; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1010:33] + wire [9:0] mtdata1_t_0 = csr_io_mtdata1_t_0; // @[dec_tlu_ctl.scala 156:67 dec_tlu_ctl.scala 1010:33] wire [3:0] trigger_execute = {mtdata1_t_3[2],mtdata1_t_2[2],mtdata1_t_1[2],mtdata1_t_0[2]}; // @[Cat.scala 29:58] wire [3:0] trigger_data = {mtdata1_t_3[7],mtdata1_t_2[7],mtdata1_t_1[7],mtdata1_t_0[7]}; // @[Cat.scala 29:58] - wire [3:0] _T_279 = trigger_execute & trigger_data; // @[dec_tlu_ctl.scala 514:57] - wire inst_acc_r_raw = io_dec_tlu_packet_r_icaf & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 670:49] + wire [3:0] _T_279 = trigger_execute & trigger_data; // @[dec_tlu_ctl.scala 510:57] + wire inst_acc_r_raw = io_dec_tlu_packet_r_icaf & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 666:49] wire [3:0] _T_281 = inst_acc_r_raw ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_282 = _T_279 & _T_281; // @[dec_tlu_ctl.scala 514:72] - wire _T_283 = io_tlu_exu_exu_i0_br_error_r | io_tlu_exu_exu_i0_br_start_error_r; // @[dec_tlu_ctl.scala 514:137] + wire [3:0] _T_282 = _T_279 & _T_281; // @[dec_tlu_ctl.scala 510:72] + wire _T_283 = io_tlu_exu_exu_i0_br_error_r | io_tlu_exu_exu_i0_br_start_error_r; // @[dec_tlu_ctl.scala 510:137] wire [3:0] _T_285 = _T_283 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_286 = _T_282 | _T_285; // @[dec_tlu_ctl.scala 514:98] - wire [3:0] i0_iside_trigger_has_pri_r = ~_T_286; // @[dec_tlu_ctl.scala 514:38] - wire [3:0] _T_295 = _T_294 & i0_iside_trigger_has_pri_r; // @[dec_tlu_ctl.scala 522:90] + wire [3:0] _T_286 = _T_282 | _T_285; // @[dec_tlu_ctl.scala 510:98] + wire [3:0] i0_iside_trigger_has_pri_r = ~_T_286; // @[dec_tlu_ctl.scala 510:38] + wire [3:0] _T_295 = _T_294 & i0_iside_trigger_has_pri_r; // @[dec_tlu_ctl.scala 518:90] wire [3:0] trigger_store = {mtdata1_t_3[1],mtdata1_t_2[1],mtdata1_t_1[1],mtdata1_t_0[1]}; // @[Cat.scala 29:58] - wire [3:0] _T_287 = trigger_store & trigger_data; // @[dec_tlu_ctl.scala 517:51] + wire [3:0] _T_287 = trigger_store & trigger_data; // @[dec_tlu_ctl.scala 513:51] wire [3:0] _T_289 = io_lsu_error_pkt_r_valid ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_290 = _T_287 & _T_289; // @[dec_tlu_ctl.scala 517:66] - wire [3:0] i0_lsu_trigger_has_pri_r = ~_T_290; // @[dec_tlu_ctl.scala 517:35] - wire [3:0] _T_296 = _T_295 & i0_lsu_trigger_has_pri_r; // @[dec_tlu_ctl.scala 522:119] - wire [1:0] mstatus = csr_io_mstatus; // @[dec_tlu_ctl.scala 1010:31] - wire _T_259 = mtdata1_t_3[6] | mstatus[0]; // @[dec_tlu_ctl.scala 511:62] - wire _T_261 = _T_259 & mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 511:86] - wire _T_264 = mtdata1_t_2[6] | mstatus[0]; // @[dec_tlu_ctl.scala 511:150] - wire _T_266 = _T_264 & mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 511:174] - wire _T_269 = mtdata1_t_1[6] | mstatus[0]; // @[dec_tlu_ctl.scala 511:239] - wire _T_271 = _T_269 & mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 511:263] - wire _T_274 = mtdata1_t_0[6] | mstatus[0]; // @[dec_tlu_ctl.scala 511:328] - wire _T_276 = _T_274 & mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 511:352] + wire [3:0] _T_290 = _T_287 & _T_289; // @[dec_tlu_ctl.scala 513:66] + wire [3:0] i0_lsu_trigger_has_pri_r = ~_T_290; // @[dec_tlu_ctl.scala 513:35] + wire [3:0] _T_296 = _T_295 & i0_lsu_trigger_has_pri_r; // @[dec_tlu_ctl.scala 518:119] + wire [1:0] mstatus = csr_io_mstatus; // @[dec_tlu_ctl.scala 1006:31] + wire _T_259 = mtdata1_t_3[6] | mstatus[0]; // @[dec_tlu_ctl.scala 507:62] + wire _T_261 = _T_259 & mtdata1_t_3[3]; // @[dec_tlu_ctl.scala 507:86] + wire _T_264 = mtdata1_t_2[6] | mstatus[0]; // @[dec_tlu_ctl.scala 507:150] + wire _T_266 = _T_264 & mtdata1_t_2[3]; // @[dec_tlu_ctl.scala 507:174] + wire _T_269 = mtdata1_t_1[6] | mstatus[0]; // @[dec_tlu_ctl.scala 507:239] + wire _T_271 = _T_269 & mtdata1_t_1[3]; // @[dec_tlu_ctl.scala 507:263] + wire _T_274 = mtdata1_t_0[6] | mstatus[0]; // @[dec_tlu_ctl.scala 507:328] + wire _T_276 = _T_274 & mtdata1_t_0[3]; // @[dec_tlu_ctl.scala 507:352] wire [3:0] trigger_enabled = {_T_261,_T_266,_T_271,_T_276}; // @[Cat.scala 29:58] - wire [3:0] i0trigger_qual_r = _T_296 & trigger_enabled; // @[dec_tlu_ctl.scala 522:146] - wire [3:0] i0_trigger_r = _T_300 & i0trigger_qual_r; // @[dec_tlu_ctl.scala 524:91] - wire _T_303 = ~mtdata1_t_2[5]; // @[dec_tlu_ctl.scala 527:60] - wire _T_305 = _T_303 | i0_trigger_r[2]; // @[dec_tlu_ctl.scala 527:89] - wire _T_306 = i0_trigger_r[3] & _T_305; // @[dec_tlu_ctl.scala 527:57] - wire _T_311 = _T_303 | i0_trigger_r[3]; // @[dec_tlu_ctl.scala 527:157] - wire _T_312 = i0_trigger_r[2] & _T_311; // @[dec_tlu_ctl.scala 527:125] - wire _T_315 = ~mtdata1_t_0[5]; // @[dec_tlu_ctl.scala 527:196] - wire _T_317 = _T_315 | i0_trigger_r[0]; // @[dec_tlu_ctl.scala 527:225] - wire _T_318 = i0_trigger_r[1] & _T_317; // @[dec_tlu_ctl.scala 527:193] - wire _T_323 = _T_315 | i0_trigger_r[1]; // @[dec_tlu_ctl.scala 527:293] - wire _T_324 = i0_trigger_r[0] & _T_323; // @[dec_tlu_ctl.scala 527:261] + wire [3:0] i0trigger_qual_r = _T_296 & trigger_enabled; // @[dec_tlu_ctl.scala 518:146] + wire [3:0] i0_trigger_r = _T_300 & i0trigger_qual_r; // @[dec_tlu_ctl.scala 520:84] + wire _T_303 = ~mtdata1_t_2[5]; // @[dec_tlu_ctl.scala 523:60] + wire _T_305 = _T_303 | i0_trigger_r[2]; // @[dec_tlu_ctl.scala 523:89] + wire _T_306 = i0_trigger_r[3] & _T_305; // @[dec_tlu_ctl.scala 523:57] + wire _T_311 = _T_303 | i0_trigger_r[3]; // @[dec_tlu_ctl.scala 523:157] + wire _T_312 = i0_trigger_r[2] & _T_311; // @[dec_tlu_ctl.scala 523:125] + wire _T_315 = ~mtdata1_t_0[5]; // @[dec_tlu_ctl.scala 523:196] + wire _T_317 = _T_315 | i0_trigger_r[0]; // @[dec_tlu_ctl.scala 523:225] + wire _T_318 = i0_trigger_r[1] & _T_317; // @[dec_tlu_ctl.scala 523:193] + wire _T_323 = _T_315 | i0_trigger_r[1]; // @[dec_tlu_ctl.scala 523:293] + wire _T_324 = i0_trigger_r[0] & _T_323; // @[dec_tlu_ctl.scala 523:261] wire [3:0] i0_trigger_chain_masked_r = {_T_306,_T_312,_T_318,_T_324}; // @[Cat.scala 29:58] - wire i0_trigger_hit_raw_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 530:57] - wire _T_465 = ~i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 662:90] - wire _T_466 = _T_464 & _T_465; // @[dec_tlu_ctl.scala 662:88] - wire _T_468 = ~dcsr[15]; // @[dec_tlu_ctl.scala 662:110] - wire _T_469 = _T_466 & _T_468; // @[dec_tlu_ctl.scala 662:108] - reg tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 332:80] - wire _T_429 = ~tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 637:44] - wire _T_430 = io_dec_tlu_i0_valid_r & _T_429; // @[dec_tlu_ctl.scala 637:42] - wire _T_432 = _T_430 & _T_283; // @[dec_tlu_ctl.scala 637:66] - reg ic_perr_r_d1; // @[dec_tlu_ctl.scala 326:89] - reg iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 327:89] - wire _T_433 = ic_perr_r_d1 | iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 637:154] - wire _T_435 = _T_433 & _T_107; // @[dec_tlu_ctl.scala 637:173] - wire _T_436 = _T_432 | _T_435; // @[dec_tlu_ctl.scala 637:137] - wire _T_438 = _T_436 & _T_465; // @[dec_tlu_ctl.scala 637:196] - wire _T_410 = io_dec_tlu_i0_valid_r & _T_465; // @[dec_tlu_ctl.scala 625:47] - wire _T_411 = ~io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 625:70] - wire _T_412 = _T_411 & io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec_tlu_ctl.scala 625:105] - wire lsu_i0_rfnpc_r = _T_410 & _T_412; // @[dec_tlu_ctl.scala 625:67] - wire _T_439 = ~lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 637:220] - wire rfpc_i0_r = _T_438 & _T_439; // @[dec_tlu_ctl.scala 637:217] - wire _T_470 = ~rfpc_i0_r; // @[dec_tlu_ctl.scala 662:132] - wire ebreak_r = _T_469 & _T_470; // @[dec_tlu_ctl.scala 662:130] - wire _T_472 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h9; // @[dec_tlu_ctl.scala 663:51] - wire _T_473 = _T_472 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 663:64] - wire _T_475 = _T_473 & _T_465; // @[dec_tlu_ctl.scala 663:88] - wire ecall_r = _T_475 & _T_470; // @[dec_tlu_ctl.scala 663:108] - wire _T_523 = ebreak_r | ecall_r; // @[dec_tlu_ctl.scala 690:41] - wire _T_478 = ~io_dec_tlu_packet_r_legal; // @[dec_tlu_ctl.scala 664:17] - wire _T_479 = _T_478 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 664:46] - wire _T_481 = _T_479 & _T_465; // @[dec_tlu_ctl.scala 664:70] - wire illegal_r = _T_481 & _T_470; // @[dec_tlu_ctl.scala 664:90] - wire _T_524 = _T_523 | illegal_r; // @[dec_tlu_ctl.scala 690:51] - wire _T_511 = inst_acc_r_raw & _T_470; // @[dec_tlu_ctl.scala 671:33] - wire inst_acc_r = _T_511 & _T_465; // @[dec_tlu_ctl.scala 671:46] - wire _T_525 = _T_524 | inst_acc_r; // @[dec_tlu_ctl.scala 690:63] - wire _T_527 = _T_525 & _T_470; // @[dec_tlu_ctl.scala 690:77] - wire _T_528 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 690:92] - wire i0_exception_valid_r = _T_527 & _T_528; // @[dec_tlu_ctl.scala 690:90] - wire _T_789 = i0_exception_valid_r | rfpc_i0_r; // @[dec_tlu_ctl.scala 789:49] - wire _T_402 = ~io_tlu_bp_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 613:57] - wire lsu_exc_valid_r_raw = io_lsu_error_pkt_r_valid & _T_402; // @[dec_tlu_ctl.scala 613:55] - wire _T_403 = io_lsu_error_pkt_r_valid & lsu_exc_valid_r_raw; // @[dec_tlu_ctl.scala 615:40] - wire _T_405 = _T_403 & _T_465; // @[dec_tlu_ctl.scala 615:62] - wire lsu_exc_valid_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 615:82] - wire _T_790 = _T_789 | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 789:61] - wire _T_490 = io_dec_tlu_packet_r_fence_i & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 667:50] - wire _T_492 = _T_490 & _T_465; // @[dec_tlu_ctl.scala 667:74] - wire fence_i_r = _T_492 & _T_470; // @[dec_tlu_ctl.scala 667:95] - wire _T_791 = _T_790 | fence_i_r; // @[dec_tlu_ctl.scala 789:79] - wire _T_792 = _T_791 | lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 789:91] - wire _T_414 = io_dec_tlu_i0_valid_r & _T_470; // @[dec_tlu_ctl.scala 628:50] - wire _T_415 = ~lsu_exc_valid_r; // @[dec_tlu_ctl.scala 628:65] - wire _T_416 = _T_414 & _T_415; // @[dec_tlu_ctl.scala 628:63] - wire _T_417 = ~inst_acc_r; // @[dec_tlu_ctl.scala 628:82] - wire _T_418 = _T_416 & _T_417; // @[dec_tlu_ctl.scala 628:79] - wire _T_420 = _T_418 & _T_528; // @[dec_tlu_ctl.scala 628:94] - reg request_debug_mode_r_d1; // @[dec_tlu_ctl.scala 466:81] - wire _T_421 = ~request_debug_mode_r_d1; // @[dec_tlu_ctl.scala 628:121] - wire _T_422 = _T_420 & _T_421; // @[dec_tlu_ctl.scala 628:119] - wire tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 628:146] - reg iccm_repair_state_d1; // @[dec_tlu_ctl.scala 325:80] - wire _T_444 = tlu_i0_commit_cmt & iccm_repair_state_d1; // @[dec_tlu_ctl.scala 646:52] - wire _T_484 = io_dec_tlu_packet_r_pmu_i0_itype == 4'hc; // @[dec_tlu_ctl.scala 665:51] - wire _T_485 = _T_484 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 665:64] - wire _T_487 = _T_485 & _T_465; // @[dec_tlu_ctl.scala 665:88] - wire mret_r = _T_487 & _T_470; // @[dec_tlu_ctl.scala 665:108] - wire _T_446 = _T_523 | mret_r; // @[dec_tlu_ctl.scala 646:98] - wire take_reset = reset_delayed & io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 775:32] - wire _T_447 = _T_446 | take_reset; // @[dec_tlu_ctl.scala 646:107] - wire _T_448 = _T_447 | illegal_r; // @[dec_tlu_ctl.scala 646:120] - wire _T_449 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 646:176] - wire _T_450 = dec_csr_wen_r_mod & _T_449; // @[dec_tlu_ctl.scala 646:153] - wire _T_451 = _T_448 | _T_450; // @[dec_tlu_ctl.scala 646:132] - wire _T_452 = ~_T_451; // @[dec_tlu_ctl.scala 646:77] - wire iccm_repair_state_rfnpc = _T_444 & _T_452; // @[dec_tlu_ctl.scala 646:75] - wire _T_793 = _T_792 | iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 789:108] - wire _T_794 = _T_793 | debug_resume_req_f; // @[dec_tlu_ctl.scala 789:135] - wire _T_786 = i_cpu_run_req_d1 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 787:43] - wire _T_211 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 486:28] - reg dec_pause_state_f; // @[dec_tlu_ctl.scala 465:81] - wire _T_212 = _T_211 & dec_pause_state_f; // @[dec_tlu_ctl.scala 486:48] - wire _T_213 = ext_int_ready | ce_int_ready; // @[dec_tlu_ctl.scala 486:86] - wire _T_214 = _T_213 | timer_int_ready; // @[dec_tlu_ctl.scala 486:101] - wire _T_215 = _T_214 | soft_int_ready; // @[dec_tlu_ctl.scala 486:119] - wire _T_216 = _T_215 | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 486:136] - wire _T_217 = _T_216 | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 486:160] - wire _T_218 = _T_217 | nmi_int_detected; // @[dec_tlu_ctl.scala 486:184] - wire _T_219 = _T_218 | ext_int_freeze_d1; // @[dec_tlu_ctl.scala 486:203] - wire _T_220 = ~_T_219; // @[dec_tlu_ctl.scala 486:70] - wire _T_221 = _T_212 & _T_220; // @[dec_tlu_ctl.scala 486:68] - wire _T_223 = _T_221 & _T_140; // @[dec_tlu_ctl.scala 486:224] - wire _T_225 = _T_223 & _T_378; // @[dec_tlu_ctl.scala 486:248] - wire _T_226 = ~pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 486:270] - wire _T_227 = _T_225 & _T_226; // @[dec_tlu_ctl.scala 486:268] - wire _T_228 = ~halt_taken_f; // @[dec_tlu_ctl.scala 486:291] - wire pause_expired_r = _T_227 & _T_228; // @[dec_tlu_ctl.scala 486:289] - wire sel_npc_resume = _T_786 | pause_expired_r; // @[dec_tlu_ctl.scala 787:66] - wire _T_795 = _T_794 | sel_npc_resume; // @[dec_tlu_ctl.scala 789:157] - reg dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 464:81] - wire _T_796 = _T_795 | dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 789:175] - wire synchronous_flush_r = _T_796 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 789:201] - wire _T_749 = ~synchronous_flush_r; // @[dec_tlu_ctl.scala 776:195] - wire _T_750 = _T_748 & _T_749; // @[dec_tlu_ctl.scala 776:193] - wire _T_751 = ~mret_r; // @[dec_tlu_ctl.scala 776:218] - wire _T_752 = _T_750 & _T_751; // @[dec_tlu_ctl.scala 776:216] - wire _T_753 = ~take_reset; // @[dec_tlu_ctl.scala 776:228] - wire _T_754 = _T_752 & _T_753; // @[dec_tlu_ctl.scala 776:226] - wire _T_519 = _T_466 & dcsr[15]; // @[dec_tlu_ctl.scala 674:121] - wire ebreak_to_debug_mode_r = _T_519 & _T_470; // @[dec_tlu_ctl.scala 674:142] - wire _T_755 = ~ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 776:242] - wire _T_756 = _T_754 & _T_755; // @[dec_tlu_ctl.scala 776:240] - wire _T_760 = _T_107 | _T_44; // @[dec_tlu_ctl.scala 776:288] - wire take_nmi = _T_756 & _T_760; // @[dec_tlu_ctl.scala 776:266] - wire _T_670 = _T_669 | take_nmi; // @[dec_tlu_ctl.scala 744:155] - wire _T_671 = _T_670 | ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 744:166] - wire _T_672 = _T_671 | synchronous_flush_r; // @[dec_tlu_ctl.scala 744:191] - reg exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 815:90] - wire _T_673 = _T_672 | exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 744:214] - wire _T_674 = _T_673 | mret_r; // @[dec_tlu_ctl.scala 744:238] - wire block_interrupts = _T_674 | ext_int_freeze_d1; // @[dec_tlu_ctl.scala 744:247] - wire _T_704 = ~block_interrupts; // @[dec_tlu_ctl.scala 772:91] - wire take_timer_int = _T_703 & _T_704; // @[dec_tlu_ctl.scala 772:89] - wire _T_762 = take_ext_int | take_timer_int; // @[dec_tlu_ctl.scala 779:38] - wire _T_693 = soft_int_ready & _T_700; // @[dec_tlu_ctl.scala 771:36] - wire _T_695 = _T_693 & _T_702; // @[dec_tlu_ctl.scala 771:53] - wire take_soft_int = _T_695 & _T_704; // @[dec_tlu_ctl.scala 771:69] - wire _T_763 = _T_762 | take_soft_int; // @[dec_tlu_ctl.scala 779:55] - wire _T_764 = _T_763 | take_nmi; // @[dec_tlu_ctl.scala 779:71] - wire _T_689 = ce_int_ready & _T_700; // @[dec_tlu_ctl.scala 770:33] - wire take_ce_int = _T_689 & _T_704; // @[dec_tlu_ctl.scala 770:50] - wire _T_765 = _T_764 | take_ce_int; // @[dec_tlu_ctl.scala 779:82] - wire int_timer0_int_possible = mstatus_mie_ns & mie_ns[4]; // @[dec_tlu_ctl.scala 730:49] - wire int_timer0_int_ready = mip[4] & int_timer0_int_possible; // @[dec_tlu_ctl.scala 731:47] - wire _T_706 = int_timer0_int_ready | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 773:49] - wire _T_707 = _T_706 & int_timer0_int_possible; // @[dec_tlu_ctl.scala 773:74] - wire _T_709 = _T_707 & _T_631; // @[dec_tlu_ctl.scala 773:100] - wire _T_710 = ~timer_int_ready; // @[dec_tlu_ctl.scala 773:129] - wire _T_711 = _T_709 & _T_710; // @[dec_tlu_ctl.scala 773:127] - wire _T_713 = _T_711 & _T_698; // @[dec_tlu_ctl.scala 773:146] - wire _T_715 = _T_713 & _T_700; // @[dec_tlu_ctl.scala 773:164] - wire _T_717 = _T_715 & _T_702; // @[dec_tlu_ctl.scala 773:181] - wire take_int_timer0_int = _T_717 & _T_704; // @[dec_tlu_ctl.scala 773:197] - wire _T_766 = _T_765 | take_int_timer0_int; // @[dec_tlu_ctl.scala 779:96] - wire int_timer1_int_possible = mstatus_mie_ns & mie_ns[3]; // @[dec_tlu_ctl.scala 732:49] - wire int_timer1_int_ready = mip[3] & int_timer1_int_possible; // @[dec_tlu_ctl.scala 733:47] - wire _T_720 = int_timer1_int_ready | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 774:49] - wire _T_721 = _T_720 & int_timer1_int_possible; // @[dec_tlu_ctl.scala 774:74] - wire _T_723 = _T_721 & _T_631; // @[dec_tlu_ctl.scala 774:100] - wire _T_725 = ~_T_706; // @[dec_tlu_ctl.scala 774:129] - wire _T_726 = _T_723 & _T_725; // @[dec_tlu_ctl.scala 774:127] - wire _T_728 = _T_726 & _T_710; // @[dec_tlu_ctl.scala 774:177] - wire _T_730 = _T_728 & _T_698; // @[dec_tlu_ctl.scala 774:196] - wire _T_732 = _T_730 & _T_700; // @[dec_tlu_ctl.scala 774:214] - wire _T_734 = _T_732 & _T_702; // @[dec_tlu_ctl.scala 774:231] - wire take_int_timer1_int = _T_734 & _T_704; // @[dec_tlu_ctl.scala 774:247] - wire interrupt_valid_r = _T_766 | take_int_timer1_int; // @[dec_tlu_ctl.scala 779:118] - wire _T_15 = _T_14 | interrupt_valid_r; // @[dec_tlu_ctl.scala 320:69] - wire _T_16 = _T_15 | interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 320:89] - wire _T_17 = _T_16 | reset_delayed; // @[dec_tlu_ctl.scala 320:112] - wire _T_18 = _T_17 | pause_expired_r; // @[dec_tlu_ctl.scala 320:128] - reg pause_expired_wb; // @[dec_tlu_ctl.scala 820:90] - wire _T_19 = _T_18 | pause_expired_wb; // @[dec_tlu_ctl.scala 320:146] - wire _T_496 = io_tlu_mem_ifu_ic_error_start & _T_107; // @[dec_tlu_ctl.scala 668:51] - wire _T_498 = _T_152 | dcsr_single_step_running; // @[dec_tlu_ctl.scala 668:101] - wire _T_499 = _T_496 & _T_498; // @[dec_tlu_ctl.scala 668:72] - wire _T_500 = ~internal_pmu_fw_halt_mode_f; // @[dec_tlu_ctl.scala 668:131] - wire ic_perr_r = _T_499 & _T_500; // @[dec_tlu_ctl.scala 668:129] - wire _T_20 = _T_19 | ic_perr_r; // @[dec_tlu_ctl.scala 320:165] - wire _T_21 = _T_20 | ic_perr_r_d1; // @[dec_tlu_ctl.scala 320:177] - wire _T_503 = io_tlu_mem_ifu_iccm_rd_ecc_single_err & _T_107; // @[dec_tlu_ctl.scala 669:59] - wire _T_506 = _T_503 & _T_498; // @[dec_tlu_ctl.scala 669:80] - wire iccm_sbecc_r = _T_506 & _T_500; // @[dec_tlu_ctl.scala 669:137] - wire _T_22 = _T_21 | iccm_sbecc_r; // @[dec_tlu_ctl.scala 320:192] - wire _T_23 = _T_22 | iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 320:207] - wire flush_clkvalid = _T_23 | io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 320:225] - reg lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 330:80] - reg lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 331:72] - reg _T_32; // @[dec_tlu_ctl.scala 333:73] - reg internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 334:72] - reg _T_33; // @[dec_tlu_ctl.scala 335:89] - reg nmi_lsu_load_type_f; // @[dec_tlu_ctl.scala 346:72] - reg nmi_lsu_store_type_f; // @[dec_tlu_ctl.scala 347:72] - wire _T_46 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 355:48] - wire _T_49 = ~_T_41; // @[dec_tlu_ctl.scala 355:96] - wire _T_50 = _T_46 & _T_49; // @[dec_tlu_ctl.scala 355:94] - wire _T_52 = nmi_lsu_load_type_f & _T_40; // @[dec_tlu_ctl.scala 355:159] - wire _T_54 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 356:49] - wire _T_58 = _T_54 & _T_49; // @[dec_tlu_ctl.scala 356:96] - wire _T_60 = nmi_lsu_store_type_f & _T_40; // @[dec_tlu_ctl.scala 356:162] - reg mpc_debug_halt_req_sync_f; // @[dec_tlu_ctl.scala 364:72] - reg mpc_debug_run_req_sync_f; // @[dec_tlu_ctl.scala 365:72] - reg mpc_run_state_f; // @[dec_tlu_ctl.scala 367:88] - reg debug_brkpt_status_f; // @[dec_tlu_ctl.scala 368:80] - reg mpc_debug_halt_ack_f; // @[dec_tlu_ctl.scala 369:80] - reg mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 370:80] - reg dbg_run_state_f; // @[dec_tlu_ctl.scala 372:88] - reg _T_65; // @[dec_tlu_ctl.scala 373:81] - wire _T_66 = ~mpc_debug_halt_req_sync_f; // @[dec_tlu_ctl.scala 377:71] - wire mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & _T_66; // @[dec_tlu_ctl.scala 377:69] - wire _T_67 = ~mpc_debug_run_req_sync_f; // @[dec_tlu_ctl.scala 378:70] - wire mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & _T_67; // @[dec_tlu_ctl.scala 378:68] - wire _T_68 = mpc_halt_state_f | mpc_debug_halt_req_sync_pulse; // @[dec_tlu_ctl.scala 380:48] - wire _T_71 = _T_68 | _T_111; // @[dec_tlu_ctl.scala 380:80] - wire _T_72 = ~mpc_debug_run_req_sync; // @[dec_tlu_ctl.scala 380:125] - wire mpc_halt_state_ns = _T_71 & _T_72; // @[dec_tlu_ctl.scala 380:123] - wire _T_74 = ~mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 381:80] - wire _T_75 = mpc_debug_run_req_sync_pulse & _T_74; // @[dec_tlu_ctl.scala 381:78] - wire _T_76 = mpc_run_state_f | _T_75; // @[dec_tlu_ctl.scala 381:46] - wire _T_77 = ~dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 381:133] - wire _T_78 = debug_mode_status & _T_77; // @[dec_tlu_ctl.scala 381:131] - wire mpc_run_state_ns = _T_76 & _T_78; // @[dec_tlu_ctl.scala 381:103] - wire _T_80 = dbg_halt_req_final | dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 383:70] - wire _T_81 = _T_80 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 383:96] - wire _T_82 = _T_81 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 383:121] - wire _T_83 = dbg_halt_state_f | _T_82; // @[dec_tlu_ctl.scala 383:48] - wire _T_84 = ~io_dbg_resume_req; // @[dec_tlu_ctl.scala 383:153] - wire dbg_halt_state_ns = _T_83 & _T_84; // @[dec_tlu_ctl.scala 383:151] - wire _T_86 = dbg_run_state_f | io_dbg_resume_req; // @[dec_tlu_ctl.scala 384:46] - wire dbg_run_state_ns = _T_86 & _T_78; // @[dec_tlu_ctl.scala 384:67] - wire debug_brkpt_valid = ebreak_to_debug_mode_r_d1 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 390:59] - wire _T_92 = debug_brkpt_valid | debug_brkpt_status_f; // @[dec_tlu_ctl.scala 391:53] - wire _T_94 = internal_dbg_halt_mode & _T_77; // @[dec_tlu_ctl.scala 391:103] - wire _T_96 = mpc_halt_state_f & debug_mode_status; // @[dec_tlu_ctl.scala 394:51] - wire _T_97 = _T_96 & mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 394:78] - wire _T_99 = ~dbg_halt_state_ns; // @[dec_tlu_ctl.scala 395:59] - wire _T_100 = mpc_debug_run_req_sync & _T_99; // @[dec_tlu_ctl.scala 395:57] - wire _T_101 = ~mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 395:80] - wire _T_102 = _T_100 & _T_101; // @[dec_tlu_ctl.scala 395:78] - wire _T_103 = mpc_debug_run_ack_f & mpc_debug_run_req_sync; // @[dec_tlu_ctl.scala 395:129] - wire _T_118 = mpc_run_state_ns & _T_99; // @[dec_tlu_ctl.scala 409:73] - wire _T_119 = ~mpc_halt_state_ns; // @[dec_tlu_ctl.scala 409:117] - wire _T_120 = dbg_run_state_ns & _T_119; // @[dec_tlu_ctl.scala 409:115] - wire _T_121 = _T_118 | _T_120; // @[dec_tlu_ctl.scala 409:95] - wire _T_122 = debug_halt_req_f | pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 414:43] - wire _T_124 = _T_122 & _T_749; // @[dec_tlu_ctl.scala 414:64] - wire _T_126 = _T_124 & _T_751; // @[dec_tlu_ctl.scala 414:87] - wire _T_128 = _T_126 & _T_228; // @[dec_tlu_ctl.scala 414:97] - wire _T_129 = ~dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 414:115] - wire _T_130 = _T_128 & _T_129; // @[dec_tlu_ctl.scala 414:113] - wire take_halt = _T_130 & _T_753; // @[dec_tlu_ctl.scala 414:143] - wire _T_170 = debug_resume_req_f & dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 439:49] - wire _T_172 = io_dec_tlu_i0_valid_r & _T_528; // @[dec_tlu_ctl.scala 441:59] - wire _T_174 = _T_172 & dcsr[2]; // @[dec_tlu_ctl.scala 441:84] - wire _T_329 = mtdata1_t_3[6] & mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 536:61] - wire _T_332 = mtdata1_t_2[6] & mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 536:121] - wire _T_335 = mtdata1_t_1[6] & mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 536:181] - wire _T_338 = mtdata1_t_0[6] & mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 536:241] + wire i0_trigger_hit_raw_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 526:57] + wire _T_465 = ~i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 658:90] + wire _T_466 = _T_464 & _T_465; // @[dec_tlu_ctl.scala 658:88] + wire _T_468 = ~dcsr[15]; // @[dec_tlu_ctl.scala 658:110] + wire _T_469 = _T_466 & _T_468; // @[dec_tlu_ctl.scala 658:108] + reg tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 328:80] + wire _T_429 = ~tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 633:44] + wire _T_430 = io_dec_tlu_i0_valid_r & _T_429; // @[dec_tlu_ctl.scala 633:42] + wire _T_432 = _T_430 & _T_283; // @[dec_tlu_ctl.scala 633:66] + reg ic_perr_r_d1; // @[dec_tlu_ctl.scala 322:89] + reg iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 323:89] + wire _T_433 = ic_perr_r_d1 | iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 633:154] + wire _T_435 = _T_433 & _T_107; // @[dec_tlu_ctl.scala 633:173] + wire _T_436 = _T_432 | _T_435; // @[dec_tlu_ctl.scala 633:137] + wire _T_438 = _T_436 & _T_465; // @[dec_tlu_ctl.scala 633:196] + wire _T_410 = io_dec_tlu_i0_valid_r & _T_465; // @[dec_tlu_ctl.scala 621:47] + wire _T_411 = ~io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 621:70] + wire _T_412 = _T_411 & io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec_tlu_ctl.scala 621:105] + wire lsu_i0_rfnpc_r = _T_410 & _T_412; // @[dec_tlu_ctl.scala 621:67] + wire _T_439 = ~lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 633:220] + wire rfpc_i0_r = _T_438 & _T_439; // @[dec_tlu_ctl.scala 633:217] + wire _T_470 = ~rfpc_i0_r; // @[dec_tlu_ctl.scala 658:132] + wire ebreak_r = _T_469 & _T_470; // @[dec_tlu_ctl.scala 658:130] + wire _T_472 = io_dec_tlu_packet_r_pmu_i0_itype == 4'h9; // @[dec_tlu_ctl.scala 659:51] + wire _T_473 = _T_472 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 659:64] + wire _T_475 = _T_473 & _T_465; // @[dec_tlu_ctl.scala 659:88] + wire ecall_r = _T_475 & _T_470; // @[dec_tlu_ctl.scala 659:108] + wire _T_523 = ebreak_r | ecall_r; // @[dec_tlu_ctl.scala 686:41] + wire _T_478 = ~io_dec_tlu_packet_r_legal; // @[dec_tlu_ctl.scala 660:17] + wire _T_479 = _T_478 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 660:46] + wire _T_481 = _T_479 & _T_465; // @[dec_tlu_ctl.scala 660:70] + wire illegal_r = _T_481 & _T_470; // @[dec_tlu_ctl.scala 660:90] + wire _T_524 = _T_523 | illegal_r; // @[dec_tlu_ctl.scala 686:51] + wire _T_511 = inst_acc_r_raw & _T_470; // @[dec_tlu_ctl.scala 667:33] + wire inst_acc_r = _T_511 & _T_465; // @[dec_tlu_ctl.scala 667:46] + wire _T_525 = _T_524 | inst_acc_r; // @[dec_tlu_ctl.scala 686:63] + wire _T_527 = _T_525 & _T_470; // @[dec_tlu_ctl.scala 686:77] + wire _T_528 = ~io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 686:92] + wire i0_exception_valid_r = _T_527 & _T_528; // @[dec_tlu_ctl.scala 686:90] + wire _T_789 = i0_exception_valid_r | rfpc_i0_r; // @[dec_tlu_ctl.scala 785:49] + wire _T_402 = ~io_dec_tlu_flush_lower_wb; // @[dec_tlu_ctl.scala 609:57] + wire lsu_exc_valid_r_raw = io_lsu_error_pkt_r_valid & _T_402; // @[dec_tlu_ctl.scala 609:55] + wire _T_403 = io_lsu_error_pkt_r_valid & lsu_exc_valid_r_raw; // @[dec_tlu_ctl.scala 611:40] + wire _T_405 = _T_403 & _T_465; // @[dec_tlu_ctl.scala 611:62] + wire lsu_exc_valid_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 611:82] + wire _T_790 = _T_789 | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 785:61] + wire _T_490 = io_dec_tlu_packet_r_fence_i & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 663:50] + wire _T_492 = _T_490 & _T_465; // @[dec_tlu_ctl.scala 663:74] + wire fence_i_r = _T_492 & _T_470; // @[dec_tlu_ctl.scala 663:95] + wire _T_791 = _T_790 | fence_i_r; // @[dec_tlu_ctl.scala 785:79] + wire _T_792 = _T_791 | lsu_i0_rfnpc_r; // @[dec_tlu_ctl.scala 785:91] + wire _T_414 = io_dec_tlu_i0_valid_r & _T_470; // @[dec_tlu_ctl.scala 624:50] + wire _T_415 = ~lsu_exc_valid_r; // @[dec_tlu_ctl.scala 624:65] + wire _T_416 = _T_414 & _T_415; // @[dec_tlu_ctl.scala 624:63] + wire _T_417 = ~inst_acc_r; // @[dec_tlu_ctl.scala 624:82] + wire _T_418 = _T_416 & _T_417; // @[dec_tlu_ctl.scala 624:79] + wire _T_420 = _T_418 & _T_528; // @[dec_tlu_ctl.scala 624:94] + reg request_debug_mode_r_d1; // @[dec_tlu_ctl.scala 462:81] + wire _T_421 = ~request_debug_mode_r_d1; // @[dec_tlu_ctl.scala 624:121] + wire _T_422 = _T_420 & _T_421; // @[dec_tlu_ctl.scala 624:119] + wire tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 624:146] + reg iccm_repair_state_d1; // @[dec_tlu_ctl.scala 321:80] + wire _T_444 = tlu_i0_commit_cmt & iccm_repair_state_d1; // @[dec_tlu_ctl.scala 642:52] + wire _T_484 = io_dec_tlu_packet_r_pmu_i0_itype == 4'hc; // @[dec_tlu_ctl.scala 661:51] + wire _T_485 = _T_484 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 661:64] + wire _T_487 = _T_485 & _T_465; // @[dec_tlu_ctl.scala 661:88] + wire mret_r = _T_487 & _T_470; // @[dec_tlu_ctl.scala 661:108] + wire _T_446 = _T_523 | mret_r; // @[dec_tlu_ctl.scala 642:98] + wire take_reset = reset_delayed & io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 771:32] + wire _T_447 = _T_446 | take_reset; // @[dec_tlu_ctl.scala 642:107] + wire _T_448 = _T_447 | illegal_r; // @[dec_tlu_ctl.scala 642:120] + wire _T_449 = io_dec_csr_wraddr_r == 12'h7c2; // @[dec_tlu_ctl.scala 642:176] + wire _T_450 = dec_csr_wen_r_mod & _T_449; // @[dec_tlu_ctl.scala 642:153] + wire _T_451 = _T_448 | _T_450; // @[dec_tlu_ctl.scala 642:132] + wire _T_452 = ~_T_451; // @[dec_tlu_ctl.scala 642:77] + wire iccm_repair_state_rfnpc = _T_444 & _T_452; // @[dec_tlu_ctl.scala 642:75] + wire _T_793 = _T_792 | iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 785:108] + wire _T_794 = _T_793 | debug_resume_req_f; // @[dec_tlu_ctl.scala 785:135] + wire _T_786 = i_cpu_run_req_d1 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 783:43] + wire _T_211 = ~io_dec_pause_state; // @[dec_tlu_ctl.scala 482:28] + reg dec_pause_state_f; // @[dec_tlu_ctl.scala 461:81] + wire _T_212 = _T_211 & dec_pause_state_f; // @[dec_tlu_ctl.scala 482:48] + wire _T_213 = ext_int_ready | ce_int_ready; // @[dec_tlu_ctl.scala 482:86] + wire _T_214 = _T_213 | timer_int_ready; // @[dec_tlu_ctl.scala 482:101] + wire _T_215 = _T_214 | soft_int_ready; // @[dec_tlu_ctl.scala 482:119] + wire _T_216 = _T_215 | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 482:136] + wire _T_217 = _T_216 | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 482:160] + wire _T_218 = _T_217 | nmi_int_detected; // @[dec_tlu_ctl.scala 482:184] + wire _T_219 = _T_218 | ext_int_freeze_d1; // @[dec_tlu_ctl.scala 482:203] + wire _T_220 = ~_T_219; // @[dec_tlu_ctl.scala 482:70] + wire _T_221 = _T_212 & _T_220; // @[dec_tlu_ctl.scala 482:68] + wire _T_223 = _T_221 & _T_140; // @[dec_tlu_ctl.scala 482:224] + wire _T_225 = _T_223 & _T_378; // @[dec_tlu_ctl.scala 482:248] + wire _T_226 = ~pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 482:270] + wire _T_227 = _T_225 & _T_226; // @[dec_tlu_ctl.scala 482:268] + wire _T_228 = ~halt_taken_f; // @[dec_tlu_ctl.scala 482:291] + wire pause_expired_r = _T_227 & _T_228; // @[dec_tlu_ctl.scala 482:289] + wire sel_npc_resume = _T_786 | pause_expired_r; // @[dec_tlu_ctl.scala 783:66] + wire _T_795 = _T_794 | sel_npc_resume; // @[dec_tlu_ctl.scala 785:157] + reg dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 460:81] + wire _T_796 = _T_795 | dec_tlu_wr_pause_r_d1; // @[dec_tlu_ctl.scala 785:175] + wire synchronous_flush_r = _T_796 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 785:201] + wire _T_749 = ~synchronous_flush_r; // @[dec_tlu_ctl.scala 772:195] + wire _T_750 = _T_748 & _T_749; // @[dec_tlu_ctl.scala 772:193] + wire _T_751 = ~mret_r; // @[dec_tlu_ctl.scala 772:218] + wire _T_752 = _T_750 & _T_751; // @[dec_tlu_ctl.scala 772:216] + wire _T_753 = ~take_reset; // @[dec_tlu_ctl.scala 772:228] + wire _T_754 = _T_752 & _T_753; // @[dec_tlu_ctl.scala 772:226] + wire _T_519 = _T_466 & dcsr[15]; // @[dec_tlu_ctl.scala 670:121] + wire ebreak_to_debug_mode_r = _T_519 & _T_470; // @[dec_tlu_ctl.scala 670:142] + wire _T_755 = ~ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 772:242] + wire _T_756 = _T_754 & _T_755; // @[dec_tlu_ctl.scala 772:240] + wire _T_760 = _T_107 | _T_44; // @[dec_tlu_ctl.scala 772:288] + wire take_nmi = _T_756 & _T_760; // @[dec_tlu_ctl.scala 772:266] + wire _T_670 = _T_669 | take_nmi; // @[dec_tlu_ctl.scala 740:155] + wire _T_671 = _T_670 | ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 740:166] + wire _T_672 = _T_671 | synchronous_flush_r; // @[dec_tlu_ctl.scala 740:191] + reg exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 811:90] + wire _T_673 = _T_672 | exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 740:214] + wire _T_674 = _T_673 | mret_r; // @[dec_tlu_ctl.scala 740:238] + wire block_interrupts = _T_674 | ext_int_freeze_d1; // @[dec_tlu_ctl.scala 740:247] + wire _T_704 = ~block_interrupts; // @[dec_tlu_ctl.scala 768:91] + wire take_timer_int = _T_703 & _T_704; // @[dec_tlu_ctl.scala 768:89] + wire _T_762 = take_ext_int | take_timer_int; // @[dec_tlu_ctl.scala 775:38] + wire _T_693 = soft_int_ready & _T_700; // @[dec_tlu_ctl.scala 767:36] + wire _T_695 = _T_693 & _T_702; // @[dec_tlu_ctl.scala 767:53] + wire take_soft_int = _T_695 & _T_704; // @[dec_tlu_ctl.scala 767:69] + wire _T_763 = _T_762 | take_soft_int; // @[dec_tlu_ctl.scala 775:55] + wire _T_764 = _T_763 | take_nmi; // @[dec_tlu_ctl.scala 775:71] + wire _T_689 = ce_int_ready & _T_700; // @[dec_tlu_ctl.scala 766:33] + wire take_ce_int = _T_689 & _T_704; // @[dec_tlu_ctl.scala 766:50] + wire _T_765 = _T_764 | take_ce_int; // @[dec_tlu_ctl.scala 775:82] + wire int_timer0_int_possible = mstatus_mie_ns & mie_ns[4]; // @[dec_tlu_ctl.scala 726:49] + wire int_timer0_int_ready = mip[4] & int_timer0_int_possible; // @[dec_tlu_ctl.scala 727:47] + wire _T_706 = int_timer0_int_ready | int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 769:49] + wire _T_707 = _T_706 & int_timer0_int_possible; // @[dec_tlu_ctl.scala 769:74] + wire _T_709 = _T_707 & _T_631; // @[dec_tlu_ctl.scala 769:100] + wire _T_710 = ~timer_int_ready; // @[dec_tlu_ctl.scala 769:129] + wire _T_711 = _T_709 & _T_710; // @[dec_tlu_ctl.scala 769:127] + wire _T_713 = _T_711 & _T_698; // @[dec_tlu_ctl.scala 769:146] + wire _T_715 = _T_713 & _T_700; // @[dec_tlu_ctl.scala 769:164] + wire _T_717 = _T_715 & _T_702; // @[dec_tlu_ctl.scala 769:181] + wire take_int_timer0_int = _T_717 & _T_704; // @[dec_tlu_ctl.scala 769:197] + wire _T_766 = _T_765 | take_int_timer0_int; // @[dec_tlu_ctl.scala 775:96] + wire int_timer1_int_possible = mstatus_mie_ns & mie_ns[3]; // @[dec_tlu_ctl.scala 728:49] + wire int_timer1_int_ready = mip[3] & int_timer1_int_possible; // @[dec_tlu_ctl.scala 729:47] + wire _T_720 = int_timer1_int_ready | int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 770:49] + wire _T_721 = _T_720 & int_timer1_int_possible; // @[dec_tlu_ctl.scala 770:74] + wire _T_723 = _T_721 & _T_631; // @[dec_tlu_ctl.scala 770:100] + wire _T_725 = ~_T_706; // @[dec_tlu_ctl.scala 770:129] + wire _T_726 = _T_723 & _T_725; // @[dec_tlu_ctl.scala 770:127] + wire _T_728 = _T_726 & _T_710; // @[dec_tlu_ctl.scala 770:177] + wire _T_730 = _T_728 & _T_698; // @[dec_tlu_ctl.scala 770:196] + wire _T_732 = _T_730 & _T_700; // @[dec_tlu_ctl.scala 770:214] + wire _T_734 = _T_732 & _T_702; // @[dec_tlu_ctl.scala 770:231] + wire take_int_timer1_int = _T_734 & _T_704; // @[dec_tlu_ctl.scala 770:247] + wire interrupt_valid_r = _T_766 | take_int_timer1_int; // @[dec_tlu_ctl.scala 775:118] + wire _T_15 = _T_14 | interrupt_valid_r; // @[dec_tlu_ctl.scala 316:69] + wire _T_16 = _T_15 | interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 316:89] + wire _T_17 = _T_16 | reset_delayed; // @[dec_tlu_ctl.scala 316:112] + wire _T_18 = _T_17 | pause_expired_r; // @[dec_tlu_ctl.scala 316:128] + reg pause_expired_wb; // @[dec_tlu_ctl.scala 816:90] + wire _T_19 = _T_18 | pause_expired_wb; // @[dec_tlu_ctl.scala 316:146] + wire _T_496 = io_tlu_mem_ifu_ic_error_start & _T_107; // @[dec_tlu_ctl.scala 664:51] + wire _T_498 = _T_152 | dcsr_single_step_running; // @[dec_tlu_ctl.scala 664:101] + wire _T_499 = _T_496 & _T_498; // @[dec_tlu_ctl.scala 664:72] + wire _T_500 = ~internal_pmu_fw_halt_mode_f; // @[dec_tlu_ctl.scala 664:131] + wire ic_perr_r = _T_499 & _T_500; // @[dec_tlu_ctl.scala 664:129] + wire _T_20 = _T_19 | ic_perr_r; // @[dec_tlu_ctl.scala 316:165] + wire _T_21 = _T_20 | ic_perr_r_d1; // @[dec_tlu_ctl.scala 316:177] + wire _T_503 = io_tlu_mem_ifu_iccm_rd_ecc_single_err & _T_107; // @[dec_tlu_ctl.scala 665:59] + wire _T_506 = _T_503 & _T_498; // @[dec_tlu_ctl.scala 665:80] + wire iccm_sbecc_r = _T_506 & _T_500; // @[dec_tlu_ctl.scala 665:137] + wire _T_22 = _T_21 | iccm_sbecc_r; // @[dec_tlu_ctl.scala 316:192] + wire _T_23 = _T_22 | iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 316:207] + wire flush_clkvalid = _T_23 | io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 316:225] + reg lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 326:80] + reg lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 327:72] + reg _T_32; // @[dec_tlu_ctl.scala 329:73] + reg internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 330:72] + reg _T_33; // @[dec_tlu_ctl.scala 331:89] + reg nmi_lsu_load_type_f; // @[dec_tlu_ctl.scala 342:72] + reg nmi_lsu_store_type_f; // @[dec_tlu_ctl.scala 343:72] + wire _T_46 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 351:48] + wire _T_49 = ~_T_41; // @[dec_tlu_ctl.scala 351:96] + wire _T_50 = _T_46 & _T_49; // @[dec_tlu_ctl.scala 351:94] + wire _T_52 = nmi_lsu_load_type_f & _T_40; // @[dec_tlu_ctl.scala 351:159] + wire _T_54 = nmi_lsu_detected & io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 352:49] + wire _T_58 = _T_54 & _T_49; // @[dec_tlu_ctl.scala 352:96] + wire _T_60 = nmi_lsu_store_type_f & _T_40; // @[dec_tlu_ctl.scala 352:162] + reg mpc_debug_halt_req_sync_f; // @[dec_tlu_ctl.scala 360:72] + reg mpc_debug_run_req_sync_f; // @[dec_tlu_ctl.scala 361:72] + reg mpc_run_state_f; // @[dec_tlu_ctl.scala 363:88] + reg debug_brkpt_status_f; // @[dec_tlu_ctl.scala 364:80] + reg mpc_debug_halt_ack_f; // @[dec_tlu_ctl.scala 365:80] + reg mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 366:80] + reg dbg_run_state_f; // @[dec_tlu_ctl.scala 368:88] + reg _T_65; // @[dec_tlu_ctl.scala 369:81] + wire _T_66 = ~mpc_debug_halt_req_sync_f; // @[dec_tlu_ctl.scala 373:71] + wire mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & _T_66; // @[dec_tlu_ctl.scala 373:69] + wire _T_67 = ~mpc_debug_run_req_sync_f; // @[dec_tlu_ctl.scala 374:70] + wire mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & _T_67; // @[dec_tlu_ctl.scala 374:68] + wire _T_68 = mpc_halt_state_f | mpc_debug_halt_req_sync_pulse; // @[dec_tlu_ctl.scala 376:48] + wire _T_71 = _T_68 | _T_111; // @[dec_tlu_ctl.scala 376:80] + wire _T_72 = ~mpc_debug_run_req_sync; // @[dec_tlu_ctl.scala 376:125] + wire mpc_halt_state_ns = _T_71 & _T_72; // @[dec_tlu_ctl.scala 376:123] + wire _T_74 = ~mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 377:80] + wire _T_75 = mpc_debug_run_req_sync_pulse & _T_74; // @[dec_tlu_ctl.scala 377:78] + wire _T_76 = mpc_run_state_f | _T_75; // @[dec_tlu_ctl.scala 377:46] + wire _T_77 = ~dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 377:133] + wire _T_78 = debug_mode_status & _T_77; // @[dec_tlu_ctl.scala 377:131] + wire mpc_run_state_ns = _T_76 & _T_78; // @[dec_tlu_ctl.scala 377:103] + wire _T_80 = dbg_halt_req_final | dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 379:70] + wire _T_81 = _T_80 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 379:96] + wire _T_82 = _T_81 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 379:121] + wire _T_83 = dbg_halt_state_f | _T_82; // @[dec_tlu_ctl.scala 379:48] + wire _T_84 = ~io_dbg_resume_req; // @[dec_tlu_ctl.scala 379:153] + wire dbg_halt_state_ns = _T_83 & _T_84; // @[dec_tlu_ctl.scala 379:151] + wire _T_86 = dbg_run_state_f | io_dbg_resume_req; // @[dec_tlu_ctl.scala 380:46] + wire dbg_run_state_ns = _T_86 & _T_78; // @[dec_tlu_ctl.scala 380:67] + wire debug_brkpt_valid = ebreak_to_debug_mode_r_d1 | trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 386:59] + wire _T_92 = debug_brkpt_valid | debug_brkpt_status_f; // @[dec_tlu_ctl.scala 387:53] + wire _T_94 = internal_dbg_halt_mode & _T_77; // @[dec_tlu_ctl.scala 387:103] + wire _T_96 = mpc_halt_state_f & debug_mode_status; // @[dec_tlu_ctl.scala 390:51] + wire _T_97 = _T_96 & mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 390:78] + wire _T_99 = ~dbg_halt_state_ns; // @[dec_tlu_ctl.scala 391:59] + wire _T_100 = mpc_debug_run_req_sync & _T_99; // @[dec_tlu_ctl.scala 391:57] + wire _T_101 = ~mpc_debug_halt_req_sync; // @[dec_tlu_ctl.scala 391:80] + wire _T_102 = _T_100 & _T_101; // @[dec_tlu_ctl.scala 391:78] + wire _T_103 = mpc_debug_run_ack_f & mpc_debug_run_req_sync; // @[dec_tlu_ctl.scala 391:129] + wire _T_118 = mpc_run_state_ns & _T_99; // @[dec_tlu_ctl.scala 405:73] + wire _T_119 = ~mpc_halt_state_ns; // @[dec_tlu_ctl.scala 405:117] + wire _T_120 = dbg_run_state_ns & _T_119; // @[dec_tlu_ctl.scala 405:115] + wire _T_121 = _T_118 | _T_120; // @[dec_tlu_ctl.scala 405:95] + wire _T_122 = debug_halt_req_f | pmu_fw_halt_req_f; // @[dec_tlu_ctl.scala 410:43] + wire _T_124 = _T_122 & _T_749; // @[dec_tlu_ctl.scala 410:64] + wire _T_126 = _T_124 & _T_751; // @[dec_tlu_ctl.scala 410:87] + wire _T_128 = _T_126 & _T_228; // @[dec_tlu_ctl.scala 410:97] + wire _T_129 = ~dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 410:115] + wire _T_130 = _T_128 & _T_129; // @[dec_tlu_ctl.scala 410:113] + wire take_halt = _T_130 & _T_753; // @[dec_tlu_ctl.scala 410:143] + wire _T_170 = debug_resume_req_f & dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 435:49] + wire _T_172 = io_dec_tlu_i0_valid_r & _T_528; // @[dec_tlu_ctl.scala 437:59] + wire _T_174 = _T_172 & dcsr[2]; // @[dec_tlu_ctl.scala 437:84] + wire _T_329 = mtdata1_t_3[6] & mtdata1_t_3[9]; // @[dec_tlu_ctl.scala 532:61] + wire _T_332 = mtdata1_t_2[6] & mtdata1_t_2[9]; // @[dec_tlu_ctl.scala 532:121] + wire _T_335 = mtdata1_t_1[6] & mtdata1_t_1[9]; // @[dec_tlu_ctl.scala 532:181] + wire _T_338 = mtdata1_t_0[6] & mtdata1_t_0[9]; // @[dec_tlu_ctl.scala 532:241] wire [3:0] trigger_action = {_T_329,_T_332,_T_335,_T_338}; // @[Cat.scala 29:58] - wire [3:0] _T_343 = i0_trigger_chain_masked_r & trigger_action; // @[dec_tlu_ctl.scala 542:57] - wire i0_trigger_action_r = |_T_343; // @[dec_tlu_ctl.scala 542:75] - wire trigger_hit_dmode_r = i0_trigger_hit_raw_r & i0_trigger_action_r; // @[dec_tlu_ctl.scala 544:45] - wire _T_180 = trigger_hit_dmode_r | ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 448:57] - wire _T_182 = request_debug_mode_r_d1 & _T_402; // @[dec_tlu_ctl.scala 448:110] - reg request_debug_mode_done_f; // @[dec_tlu_ctl.scala 467:73] - wire _T_183 = request_debug_mode_r_d1 | request_debug_mode_done_f; // @[dec_tlu_ctl.scala 450:64] - reg _T_190; // @[dec_tlu_ctl.scala 458:81] - wire _T_201 = fence_i_r & internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 479:71] - wire _T_202 = take_halt | _T_201; // @[dec_tlu_ctl.scala 479:58] - wire _T_203 = _T_202 | io_dec_tlu_flush_pause_r; // @[dec_tlu_ctl.scala 479:97] - wire _T_204 = i0_trigger_hit_raw_r & trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 479:144] - wire _T_205 = _T_203 | _T_204; // @[dec_tlu_ctl.scala 479:124] - wire take_ext_int_start = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 752:45] - wire _T_207 = ~interrupt_valid_r; // @[dec_tlu_ctl.scala 484:61] - wire _T_208 = dec_tlu_wr_pause_r_d1 & _T_207; // @[dec_tlu_ctl.scala 484:59] - wire _T_209 = ~take_ext_int_start; // @[dec_tlu_ctl.scala 484:82] - wire _T_231 = io_tlu_exu_dec_tlu_flush_lower_r & dcsr[2]; // @[dec_tlu_ctl.scala 488:82] - wire _T_232 = io_dec_tlu_resume_ack | dcsr_single_step_running; // @[dec_tlu_ctl.scala 488:125] - wire _T_233 = _T_231 & _T_232; // @[dec_tlu_ctl.scala 488:100] - wire _T_234 = ~io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec_tlu_ctl.scala 488:155] + wire [3:0] _T_343 = i0_trigger_chain_masked_r & trigger_action; // @[dec_tlu_ctl.scala 538:57] + wire i0_trigger_action_r = |_T_343; // @[dec_tlu_ctl.scala 538:75] + wire trigger_hit_dmode_r = i0_trigger_hit_raw_r & i0_trigger_action_r; // @[dec_tlu_ctl.scala 540:45] + wire _T_180 = trigger_hit_dmode_r | ebreak_to_debug_mode_r; // @[dec_tlu_ctl.scala 444:57] + wire _T_182 = request_debug_mode_r_d1 & _T_402; // @[dec_tlu_ctl.scala 444:110] + reg request_debug_mode_done_f; // @[dec_tlu_ctl.scala 463:73] + wire _T_183 = request_debug_mode_r_d1 | request_debug_mode_done_f; // @[dec_tlu_ctl.scala 446:64] + reg _T_190; // @[dec_tlu_ctl.scala 454:81] + wire _T_201 = fence_i_r & internal_dbg_halt_mode; // @[dec_tlu_ctl.scala 475:71] + wire _T_202 = take_halt | _T_201; // @[dec_tlu_ctl.scala 475:58] + wire _T_203 = _T_202 | io_dec_tlu_flush_pause_r; // @[dec_tlu_ctl.scala 475:97] + wire _T_204 = i0_trigger_hit_raw_r & trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 475:144] + wire _T_205 = _T_203 | _T_204; // @[dec_tlu_ctl.scala 475:124] + wire take_ext_int_start = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 748:45] + wire _T_207 = ~interrupt_valid_r; // @[dec_tlu_ctl.scala 480:61] + wire _T_208 = dec_tlu_wr_pause_r_d1 & _T_207; // @[dec_tlu_ctl.scala 480:59] + wire _T_209 = ~take_ext_int_start; // @[dec_tlu_ctl.scala 480:82] + wire _T_231 = io_tlu_exu_dec_tlu_flush_lower_r & dcsr[2]; // @[dec_tlu_ctl.scala 484:82] + wire _T_232 = io_dec_tlu_resume_ack | dcsr_single_step_running; // @[dec_tlu_ctl.scala 484:125] + wire _T_233 = _T_231 & _T_232; // @[dec_tlu_ctl.scala 484:100] + wire _T_234 = ~io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec_tlu_ctl.scala 484:155] wire [3:0] _T_342 = i0_trigger_hit_raw_r ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire _T_345 = ~trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 546:55] - wire mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[dec_tlu_ctl.scala 546:53] - wire _T_350 = i_cpu_run_req_sync & _T_346; // @[dec_tlu_ctl.scala 574:58] - wire _T_351 = _T_350 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 574:83] - wire i_cpu_run_req_sync_qual = _T_351 & _T_107; // @[dec_tlu_ctl.scala 574:105] - reg _T_353; // @[dec_tlu_ctl.scala 578:81] - reg _T_354; // @[dec_tlu_ctl.scala 579:81] - reg _T_355; // @[dec_tlu_ctl.scala 580:81] - wire _T_384 = io_o_cpu_halt_status & _T_375; // @[dec_tlu_ctl.scala 598:89] - wire _T_386 = _T_384 & _T_152; // @[dec_tlu_ctl.scala 598:109] - wire _T_388 = io_o_cpu_halt_status & i_cpu_run_req_sync_qual; // @[dec_tlu_ctl.scala 599:41] - wire _T_389 = io_o_cpu_run_ack & i_cpu_run_req_sync_qual; // @[dec_tlu_ctl.scala 599:88] - reg lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 611:72] - reg lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 618:73] - wire _T_408 = ~io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 619:40] - wire lsu_exc_ma_r = lsu_exc_valid_r & _T_408; // @[dec_tlu_ctl.scala 619:38] - wire lsu_exc_acc_r = lsu_exc_valid_r & io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 620:38] - wire lsu_exc_st_r = lsu_exc_valid_r & io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 621:38] - wire _T_424 = rfpc_i0_r | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 631:38] - wire _T_425 = _T_424 | inst_acc_r; // @[dec_tlu_ctl.scala 631:53] - wire _T_426 = illegal_r & io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 631:79] - wire _T_427 = _T_425 | _T_426; // @[dec_tlu_ctl.scala 631:66] - wire _T_441 = ~io_tlu_exu_dec_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 640:70] - wire _T_442 = iccm_repair_state_d1 & _T_441; // @[dec_tlu_ctl.scala 640:68] - wire _T_453 = io_tlu_exu_exu_i0_br_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 649:59] - wire _T_455 = io_tlu_exu_exu_i0_br_start_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 650:71] - wire _T_457 = io_tlu_exu_exu_i0_br_valid_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 651:55] - wire _T_459 = _T_457 & _T_429; // @[dec_tlu_ctl.scala 651:79] - wire _T_460 = ~io_tlu_exu_exu_i0_br_mp_r; // @[dec_tlu_ctl.scala 651:106] - wire _T_461 = ~io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 651:135] - wire _T_462 = _T_460 | _T_461; // @[dec_tlu_ctl.scala 651:133] - wire _T_529 = ~take_nmi; // @[dec_tlu_ctl.scala 699:33] - wire _T_530 = take_ext_int & _T_529; // @[dec_tlu_ctl.scala 699:31] - wire _T_533 = take_timer_int & _T_529; // @[dec_tlu_ctl.scala 700:25] - wire _T_536 = take_soft_int & _T_529; // @[dec_tlu_ctl.scala 701:24] - wire _T_539 = take_int_timer0_int & _T_529; // @[dec_tlu_ctl.scala 702:30] - wire _T_542 = take_int_timer1_int & _T_529; // @[dec_tlu_ctl.scala 703:30] - wire _T_545 = take_ce_int & _T_529; // @[dec_tlu_ctl.scala 704:22] - wire _T_548 = illegal_r & _T_529; // @[dec_tlu_ctl.scala 705:20] - wire _T_551 = ecall_r & _T_529; // @[dec_tlu_ctl.scala 706:19] - wire _T_554 = inst_acc_r & _T_529; // @[dec_tlu_ctl.scala 707:22] - wire _T_556 = ebreak_r | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 708:20] - wire _T_558 = _T_556 & _T_529; // @[dec_tlu_ctl.scala 708:40] - wire _T_560 = ~lsu_exc_st_r; // @[dec_tlu_ctl.scala 709:25] - wire _T_561 = lsu_exc_ma_r & _T_560; // @[dec_tlu_ctl.scala 709:23] - wire _T_563 = _T_561 & _T_529; // @[dec_tlu_ctl.scala 709:39] - wire _T_566 = lsu_exc_acc_r & _T_560; // @[dec_tlu_ctl.scala 710:24] - wire _T_568 = _T_566 & _T_529; // @[dec_tlu_ctl.scala 710:40] - wire _T_570 = lsu_exc_ma_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 711:23] - wire _T_572 = _T_570 & _T_529; // @[dec_tlu_ctl.scala 711:38] - wire _T_574 = lsu_exc_acc_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 712:24] - wire _T_576 = _T_574 & _T_529; // @[dec_tlu_ctl.scala 712:39] + wire _T_345 = ~trigger_hit_dmode_r; // @[dec_tlu_ctl.scala 542:55] + wire mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[dec_tlu_ctl.scala 542:53] + wire _T_350 = i_cpu_run_req_sync & _T_346; // @[dec_tlu_ctl.scala 570:58] + wire _T_351 = _T_350 & pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 570:83] + wire i_cpu_run_req_sync_qual = _T_351 & _T_107; // @[dec_tlu_ctl.scala 570:105] + reg _T_353; // @[dec_tlu_ctl.scala 574:81] + reg _T_354; // @[dec_tlu_ctl.scala 575:81] + reg _T_355; // @[dec_tlu_ctl.scala 576:81] + wire _T_384 = io_o_cpu_halt_status & _T_375; // @[dec_tlu_ctl.scala 594:89] + wire _T_386 = _T_384 & _T_152; // @[dec_tlu_ctl.scala 594:109] + wire _T_388 = io_o_cpu_halt_status & i_cpu_run_req_sync_qual; // @[dec_tlu_ctl.scala 595:41] + wire _T_389 = io_o_cpu_run_ack & i_cpu_run_req_sync_qual; // @[dec_tlu_ctl.scala 595:88] + reg lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 607:72] + reg lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 614:73] + wire _T_408 = ~io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 615:40] + wire lsu_exc_ma_r = lsu_exc_valid_r & _T_408; // @[dec_tlu_ctl.scala 615:38] + wire lsu_exc_acc_r = lsu_exc_valid_r & io_lsu_error_pkt_r_bits_exc_type; // @[dec_tlu_ctl.scala 616:38] + wire lsu_exc_st_r = lsu_exc_valid_r & io_lsu_error_pkt_r_bits_inst_type; // @[dec_tlu_ctl.scala 617:38] + wire _T_424 = rfpc_i0_r | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 627:38] + wire _T_425 = _T_424 | inst_acc_r; // @[dec_tlu_ctl.scala 627:53] + wire _T_426 = illegal_r & io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 627:79] + wire _T_427 = _T_425 | _T_426; // @[dec_tlu_ctl.scala 627:66] + wire _T_441 = ~io_tlu_exu_dec_tlu_flush_lower_r; // @[dec_tlu_ctl.scala 636:70] + wire _T_442 = iccm_repair_state_d1 & _T_441; // @[dec_tlu_ctl.scala 636:68] + wire _T_453 = io_tlu_exu_exu_i0_br_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 645:59] + wire _T_455 = io_tlu_exu_exu_i0_br_start_error_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 646:71] + wire _T_457 = io_tlu_exu_exu_i0_br_valid_r & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 647:55] + wire _T_459 = _T_457 & _T_429; // @[dec_tlu_ctl.scala 647:79] + wire _T_460 = ~io_tlu_exu_exu_i0_br_mp_r; // @[dec_tlu_ctl.scala 647:106] + wire _T_461 = ~io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 647:135] + wire _T_462 = _T_460 | _T_461; // @[dec_tlu_ctl.scala 647:133] + wire _T_529 = ~take_nmi; // @[dec_tlu_ctl.scala 695:33] + wire _T_530 = take_ext_int & _T_529; // @[dec_tlu_ctl.scala 695:31] + wire _T_533 = take_timer_int & _T_529; // @[dec_tlu_ctl.scala 696:25] + wire _T_536 = take_soft_int & _T_529; // @[dec_tlu_ctl.scala 697:24] + wire _T_539 = take_int_timer0_int & _T_529; // @[dec_tlu_ctl.scala 698:30] + wire _T_542 = take_int_timer1_int & _T_529; // @[dec_tlu_ctl.scala 699:30] + wire _T_545 = take_ce_int & _T_529; // @[dec_tlu_ctl.scala 700:22] + wire _T_548 = illegal_r & _T_529; // @[dec_tlu_ctl.scala 701:20] + wire _T_551 = ecall_r & _T_529; // @[dec_tlu_ctl.scala 702:19] + wire _T_554 = inst_acc_r & _T_529; // @[dec_tlu_ctl.scala 703:22] + wire _T_556 = ebreak_r | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 704:20] + wire _T_558 = _T_556 & _T_529; // @[dec_tlu_ctl.scala 704:40] + wire _T_560 = ~lsu_exc_st_r; // @[dec_tlu_ctl.scala 705:25] + wire _T_561 = lsu_exc_ma_r & _T_560; // @[dec_tlu_ctl.scala 705:23] + wire _T_563 = _T_561 & _T_529; // @[dec_tlu_ctl.scala 705:39] + wire _T_566 = lsu_exc_acc_r & _T_560; // @[dec_tlu_ctl.scala 706:24] + wire _T_568 = _T_566 & _T_529; // @[dec_tlu_ctl.scala 706:40] + wire _T_570 = lsu_exc_ma_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 707:23] + wire _T_572 = _T_570 & _T_529; // @[dec_tlu_ctl.scala 707:38] + wire _T_574 = lsu_exc_acc_r & lsu_exc_st_r; // @[dec_tlu_ctl.scala 708:24] + wire _T_576 = _T_574 & _T_529; // @[dec_tlu_ctl.scala 708:39] wire [4:0] _T_578 = _T_530 ? 5'hb : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_579 = _T_533 ? 5'h7 : 5'h0; // @[Mux.scala 27:72] wire [4:0] _T_580 = _T_536 ? 5'h3 : 5'h0; // @[Mux.scala 27:72] @@ -55432,66 +55427,66 @@ module dec_tlu_ctl( wire [4:0] _T_602 = _T_601 | _T_589; // @[Mux.scala 27:72] wire [4:0] _T_603 = _T_602 | _T_590; // @[Mux.scala 27:72] wire [4:0] exc_cause_r = _T_603 | _T_591; // @[Mux.scala 27:72] - wire _T_641 = io_dec_csr_stall_int_ff | synchronous_flush_r; // @[dec_tlu_ctl.scala 737:52] - wire _T_642 = _T_641 | exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 737:74] - wire int_timer_stalled = _T_642 | mret_r; // @[dec_tlu_ctl.scala 737:98] - wire _T_643 = pmu_fw_tlu_halted_f | int_timer_stalled; // @[dec_tlu_ctl.scala 739:72] - wire _T_644 = int_timer0_int_ready & _T_643; // @[dec_tlu_ctl.scala 739:49] - wire _T_645 = int_timer0_int_possible & int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 739:121] - wire _T_647 = _T_645 & _T_207; // @[dec_tlu_ctl.scala 739:145] - wire _T_649 = _T_647 & _T_209; // @[dec_tlu_ctl.scala 739:166] - wire _T_651 = _T_649 & _T_152; // @[dec_tlu_ctl.scala 739:188] - wire _T_654 = int_timer1_int_ready & _T_643; // @[dec_tlu_ctl.scala 740:49] - wire _T_655 = int_timer1_int_possible & int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 740:121] - wire _T_657 = _T_655 & _T_207; // @[dec_tlu_ctl.scala 740:145] - wire _T_659 = _T_657 & _T_209; // @[dec_tlu_ctl.scala 740:166] - wire _T_661 = _T_659 & _T_152; // @[dec_tlu_ctl.scala 740:188] - reg take_ext_int_start_d2; // @[dec_tlu_ctl.scala 749:62] - wire _T_681 = take_ext_int_start | take_ext_int_start_d1; // @[dec_tlu_ctl.scala 754:46] - wire _T_682 = _T_681 | take_ext_int_start_d2; // @[dec_tlu_ctl.scala 754:70] - wire csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 275:41 dec_tlu_ctl.scala 1017:16] - wire fast_int_meicpct = csr_pkt_csr_meicpct & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 756:49] - wire [30:0] mtvec = csr_io_mtvec; // @[dec_tlu_ctl.scala 1012:31] + wire _T_641 = io_dec_csr_stall_int_ff | synchronous_flush_r; // @[dec_tlu_ctl.scala 733:52] + wire _T_642 = _T_641 | exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 733:74] + wire int_timer_stalled = _T_642 | mret_r; // @[dec_tlu_ctl.scala 733:98] + wire _T_643 = pmu_fw_tlu_halted_f | int_timer_stalled; // @[dec_tlu_ctl.scala 735:72] + wire _T_644 = int_timer0_int_ready & _T_643; // @[dec_tlu_ctl.scala 735:49] + wire _T_645 = int_timer0_int_possible & int_timer0_int_hold_f; // @[dec_tlu_ctl.scala 735:121] + wire _T_647 = _T_645 & _T_207; // @[dec_tlu_ctl.scala 735:145] + wire _T_649 = _T_647 & _T_209; // @[dec_tlu_ctl.scala 735:166] + wire _T_651 = _T_649 & _T_152; // @[dec_tlu_ctl.scala 735:188] + wire _T_654 = int_timer1_int_ready & _T_643; // @[dec_tlu_ctl.scala 736:49] + wire _T_655 = int_timer1_int_possible & int_timer1_int_hold_f; // @[dec_tlu_ctl.scala 736:121] + wire _T_657 = _T_655 & _T_207; // @[dec_tlu_ctl.scala 736:145] + wire _T_659 = _T_657 & _T_209; // @[dec_tlu_ctl.scala 736:166] + wire _T_661 = _T_659 & _T_152; // @[dec_tlu_ctl.scala 736:188] + reg take_ext_int_start_d2; // @[dec_tlu_ctl.scala 745:62] + wire _T_681 = take_ext_int_start | take_ext_int_start_d1; // @[dec_tlu_ctl.scala 750:46] + wire _T_682 = _T_681 | take_ext_int_start_d2; // @[dec_tlu_ctl.scala 750:70] + wire csr_pkt_csr_meicpct = csr_read_io_csr_pkt_csr_meicpct; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] + wire fast_int_meicpct = csr_pkt_csr_meicpct & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 752:49] + wire [30:0] mtvec = csr_io_mtvec; // @[dec_tlu_ctl.scala 1008:31] wire [30:0] _T_769 = {mtvec[30:1],1'h0}; // @[Cat.scala 29:58] wire [30:0] _T_771 = {25'h0,exc_cause_r,1'h0}; // @[Cat.scala 29:58] - wire [30:0] vectored_path = _T_769 + _T_771; // @[dec_tlu_ctl.scala 784:51] - wire [30:0] _T_778 = mtvec[0] ? vectored_path : _T_769; // @[dec_tlu_ctl.scala 785:61] - wire [30:0] interrupt_path = take_nmi ? io_nmi_vec : _T_778; // @[dec_tlu_ctl.scala 785:28] - wire _T_779 = lsu_i0_rfnpc_r | fence_i_r; // @[dec_tlu_ctl.scala 786:36] - wire _T_780 = _T_779 | iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 786:48] - wire _T_782 = i_cpu_run_req_d1 & _T_207; // @[dec_tlu_ctl.scala 786:94] - wire _T_783 = _T_780 | _T_782; // @[dec_tlu_ctl.scala 786:74] - wire _T_785 = rfpc_i0_r & _T_743; // @[dec_tlu_ctl.scala 786:129] - wire sel_npc_r = _T_783 | _T_785; // @[dec_tlu_ctl.scala 786:116] - wire _T_798 = interrupt_valid_r | mret_r; // @[dec_tlu_ctl.scala 790:43] - wire _T_799 = _T_798 | synchronous_flush_r; // @[dec_tlu_ctl.scala 790:52] - wire _T_800 = _T_799 | take_halt; // @[dec_tlu_ctl.scala 790:74] - wire _T_801 = _T_800 | take_reset; // @[dec_tlu_ctl.scala 790:86] - wire _T_807 = _T_529 & sel_npc_r; // @[dec_tlu_ctl.scala 794:73] - wire _T_810 = _T_529 & rfpc_i0_r; // @[dec_tlu_ctl.scala 795:73] - wire _T_812 = _T_810 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 795:91] - wire _T_813 = ~sel_npc_r; // @[dec_tlu_ctl.scala 795:132] - wire _T_814 = _T_812 & _T_813; // @[dec_tlu_ctl.scala 795:121] - wire _T_816 = ~take_ext_int; // @[dec_tlu_ctl.scala 796:96] - wire _T_817 = interrupt_valid_r & _T_816; // @[dec_tlu_ctl.scala 796:82] - wire _T_818 = i0_exception_valid_r | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 797:80] - wire _T_821 = _T_818 | mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 797:98] - wire _T_823 = _T_821 & _T_207; // @[dec_tlu_ctl.scala 797:143] - wire _T_825 = _T_823 & _T_816; // @[dec_tlu_ctl.scala 797:164] - wire _T_830 = _T_529 & mret_r; // @[dec_tlu_ctl.scala 798:68] - wire _T_833 = _T_529 & debug_resume_req_f; // @[dec_tlu_ctl.scala 799:68] - wire _T_836 = _T_529 & sel_npc_resume; // @[dec_tlu_ctl.scala 800:68] + wire [30:0] vectored_path = _T_769 + _T_771; // @[dec_tlu_ctl.scala 780:51] + wire [30:0] _T_778 = mtvec[0] ? vectored_path : _T_769; // @[dec_tlu_ctl.scala 781:61] + wire [30:0] interrupt_path = take_nmi ? io_nmi_vec : _T_778; // @[dec_tlu_ctl.scala 781:28] + wire _T_779 = lsu_i0_rfnpc_r | fence_i_r; // @[dec_tlu_ctl.scala 782:36] + wire _T_780 = _T_779 | iccm_repair_state_rfnpc; // @[dec_tlu_ctl.scala 782:48] + wire _T_782 = i_cpu_run_req_d1 & _T_207; // @[dec_tlu_ctl.scala 782:94] + wire _T_783 = _T_780 | _T_782; // @[dec_tlu_ctl.scala 782:74] + wire _T_785 = rfpc_i0_r & _T_743; // @[dec_tlu_ctl.scala 782:129] + wire sel_npc_r = _T_783 | _T_785; // @[dec_tlu_ctl.scala 782:116] + wire _T_798 = interrupt_valid_r | mret_r; // @[dec_tlu_ctl.scala 786:43] + wire _T_799 = _T_798 | synchronous_flush_r; // @[dec_tlu_ctl.scala 786:52] + wire _T_800 = _T_799 | take_halt; // @[dec_tlu_ctl.scala 786:74] + wire _T_801 = _T_800 | take_reset; // @[dec_tlu_ctl.scala 786:86] + wire _T_807 = _T_529 & sel_npc_r; // @[dec_tlu_ctl.scala 790:73] + wire _T_810 = _T_529 & rfpc_i0_r; // @[dec_tlu_ctl.scala 791:73] + wire _T_812 = _T_810 & io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 791:91] + wire _T_813 = ~sel_npc_r; // @[dec_tlu_ctl.scala 791:132] + wire _T_814 = _T_812 & _T_813; // @[dec_tlu_ctl.scala 791:121] + wire _T_816 = ~take_ext_int; // @[dec_tlu_ctl.scala 792:96] + wire _T_817 = interrupt_valid_r & _T_816; // @[dec_tlu_ctl.scala 792:82] + wire _T_818 = i0_exception_valid_r | lsu_exc_valid_r; // @[dec_tlu_ctl.scala 793:80] + wire _T_821 = _T_818 | mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 793:98] + wire _T_823 = _T_821 & _T_207; // @[dec_tlu_ctl.scala 793:143] + wire _T_825 = _T_823 & _T_816; // @[dec_tlu_ctl.scala 793:164] + wire _T_830 = _T_529 & mret_r; // @[dec_tlu_ctl.scala 794:68] + wire _T_833 = _T_529 & debug_resume_req_f; // @[dec_tlu_ctl.scala 795:68] + wire _T_836 = _T_529 & sel_npc_resume; // @[dec_tlu_ctl.scala 796:68] wire [30:0] _T_838 = take_ext_int ? io_lsu_fir_addr : 31'h0; // @[Mux.scala 27:72] - wire [30:0] npc_r = csr_io_npc_r; // @[dec_tlu_ctl.scala 1000:31] + wire [30:0] npc_r = csr_io_npc_r; // @[dec_tlu_ctl.scala 996:31] wire [30:0] _T_839 = _T_807 ? npc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_840 = _T_814 ? io_dec_tlu_i0_pc_r : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_841 = _T_817 ? interrupt_path : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_842 = _T_825 ? _T_769 : 31'h0; // @[Mux.scala 27:72] - wire [30:0] mepc = csr_io_mepc; // @[dec_tlu_ctl.scala 1003:31] + wire [30:0] mepc = csr_io_mepc; // @[dec_tlu_ctl.scala 999:31] wire [30:0] _T_843 = _T_830 ? mepc : 31'h0; // @[Mux.scala 27:72] - wire [30:0] dpc = csr_io_dpc; // @[dec_tlu_ctl.scala 1006:31] + wire [30:0] dpc = csr_io_dpc; // @[dec_tlu_ctl.scala 1002:31] wire [30:0] _T_844 = _T_833 ? dpc : 31'h0; // @[Mux.scala 27:72] - wire [30:0] npc_r_d1 = csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 1001:31] + wire [30:0] npc_r_d1 = csr_io_npc_r_d1; // @[dec_tlu_ctl.scala 997:31] wire [30:0] _T_845 = _T_836 ? npc_r_d1 : 31'h0; // @[Mux.scala 27:72] wire [30:0] _T_846 = _T_838 | _T_839; // @[Mux.scala 27:72] wire [30:0] _T_847 = _T_846 | _T_840; // @[Mux.scala 27:72] @@ -55500,54 +55495,54 @@ module dec_tlu_ctl( wire [30:0] _T_850 = _T_849 | _T_843; // @[Mux.scala 27:72] wire [30:0] _T_851 = _T_850 | _T_844; // @[Mux.scala 27:72] wire [30:0] _T_852 = _T_851 | _T_845; // @[Mux.scala 27:72] - reg [30:0] tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 803:64] - wire _T_854 = lsu_exc_valid_r | i0_exception_valid_r; // @[dec_tlu_ctl.scala 811:45] - wire _T_855 = _T_854 | interrupt_valid_r; // @[dec_tlu_ctl.scala 811:68] - reg i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 814:89] - reg [4:0] exc_cause_wb; // @[dec_tlu_ctl.scala 816:89] - wire _T_860 = ~illegal_r; // @[dec_tlu_ctl.scala 817:119] - reg i0_valid_wb; // @[dec_tlu_ctl.scala 817:97] - reg trigger_hit_r_d1; // @[dec_tlu_ctl.scala 818:89] - wire csr_pkt_presync = csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 275:41 dec_tlu_ctl.scala 1017:16] - wire _T_864 = csr_pkt_presync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1019:42] - wire _T_865 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 1019:67] - wire csr_pkt_postsync = csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 275:41 dec_tlu_ctl.scala 1017:16] - wire csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 275:41 dec_tlu_ctl.scala 1017:16] - wire csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 275:41 dec_tlu_ctl.scala 1017:16] - wire _T_874 = csr_pkt_csr_dcsr | csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1024:55] - wire csr_pkt_csr_dmst = csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 275:41 dec_tlu_ctl.scala 1017:16] - wire _T_875 = _T_874 | csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1024:73] - wire csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 275:41 dec_tlu_ctl.scala 1017:16] - wire _T_876 = _T_875 | csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1024:92] - wire csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 275:41 dec_tlu_ctl.scala 1017:16] - wire _T_877 = _T_876 | csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1024:115] - wire csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 275:41 dec_tlu_ctl.scala 1017:16] - wire _T_878 = _T_877 | csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1024:136] - wire csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 275:41 dec_tlu_ctl.scala 1017:16] - wire _T_879 = _T_878 | csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1024:158] - wire csr_pkt_csr_dicago = csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 275:41 dec_tlu_ctl.scala 1017:16] - wire _T_880 = _T_879 | csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1024:179] - wire _T_881 = ~_T_880; // @[dec_tlu_ctl.scala 1024:36] - wire _T_882 = _T_881 | dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1024:201] - wire csr_pkt_legal = csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 275:41 dec_tlu_ctl.scala 1017:16] - wire _T_883 = csr_pkt_legal & _T_882; // @[dec_tlu_ctl.scala 1024:33] - wire _T_884 = ~fast_int_meicpct; // @[dec_tlu_ctl.scala 1024:223] - wire valid_csr = _T_883 & _T_884; // @[dec_tlu_ctl.scala 1024:221] - wire _T_887 = io_dec_csr_any_unq_d & valid_csr; // @[dec_tlu_ctl.scala 1026:46] - wire csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 275:41 dec_tlu_ctl.scala 1017:16] - wire csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 275:41 dec_tlu_ctl.scala 1017:16] - wire _T_888 = csr_pkt_csr_mvendorid | csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1026:107] - wire csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 275:41 dec_tlu_ctl.scala 1017:16] - wire _T_889 = _T_888 | csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1026:129] - wire csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 275:41 dec_tlu_ctl.scala 1017:16] - wire _T_890 = _T_889 | csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1026:150] - wire csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 275:41 dec_tlu_ctl.scala 1017:16] - wire _T_891 = _T_890 | csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1026:172] - wire csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 275:41 dec_tlu_ctl.scala 1017:16] - wire _T_892 = _T_891 | csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1026:193] - wire _T_893 = io_dec_csr_wen_unq_d & _T_892; // @[dec_tlu_ctl.scala 1026:82] - wire _T_894 = ~_T_893; // @[dec_tlu_ctl.scala 1026:59] - dec_timer_ctl int_timers ( // @[dec_tlu_ctl.scala 279:30] + reg [30:0] tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 799:64] + wire _T_854 = lsu_exc_valid_r | i0_exception_valid_r; // @[dec_tlu_ctl.scala 807:45] + wire _T_855 = _T_854 | interrupt_valid_r; // @[dec_tlu_ctl.scala 807:68] + reg i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 810:89] + reg [4:0] exc_cause_wb; // @[dec_tlu_ctl.scala 812:89] + wire _T_860 = ~illegal_r; // @[dec_tlu_ctl.scala 813:119] + reg i0_valid_wb; // @[dec_tlu_ctl.scala 813:97] + reg trigger_hit_r_d1; // @[dec_tlu_ctl.scala 814:89] + wire csr_pkt_presync = csr_read_io_csr_pkt_presync; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] + wire _T_864 = csr_pkt_presync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1015:42] + wire _T_865 = ~io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 1015:67] + wire csr_pkt_postsync = csr_read_io_csr_pkt_postsync; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] + wire csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] + wire csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] + wire _T_874 = csr_pkt_csr_dcsr | csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 1020:55] + wire csr_pkt_csr_dmst = csr_read_io_csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] + wire _T_875 = _T_874 | csr_pkt_csr_dmst; // @[dec_tlu_ctl.scala 1020:73] + wire csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] + wire _T_876 = _T_875 | csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 1020:92] + wire csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] + wire _T_877 = _T_876 | csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 1020:115] + wire csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] + wire _T_878 = _T_877 | csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 1020:136] + wire csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] + wire _T_879 = _T_878 | csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 1020:158] + wire csr_pkt_csr_dicago = csr_read_io_csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] + wire _T_880 = _T_879 | csr_pkt_csr_dicago; // @[dec_tlu_ctl.scala 1020:179] + wire _T_881 = ~_T_880; // @[dec_tlu_ctl.scala 1020:36] + wire _T_882 = _T_881 | dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 1020:201] + wire csr_pkt_legal = csr_read_io_csr_pkt_legal; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] + wire _T_883 = csr_pkt_legal & _T_882; // @[dec_tlu_ctl.scala 1020:33] + wire _T_884 = ~fast_int_meicpct; // @[dec_tlu_ctl.scala 1020:223] + wire valid_csr = _T_883 & _T_884; // @[dec_tlu_ctl.scala 1020:221] + wire _T_887 = io_dec_csr_any_unq_d & valid_csr; // @[dec_tlu_ctl.scala 1022:46] + wire csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] + wire csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] + wire _T_888 = csr_pkt_csr_mvendorid | csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 1022:107] + wire csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] + wire _T_889 = _T_888 | csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 1022:129] + wire csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] + wire _T_890 = _T_889 | csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 1022:150] + wire csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] + wire _T_891 = _T_890 | csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 1022:172] + wire csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 271:41 dec_tlu_ctl.scala 1013:16] + wire _T_892 = _T_891 | csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 1022:193] + wire _T_893 = io_dec_csr_wen_unq_d & _T_892; // @[dec_tlu_ctl.scala 1022:82] + wire _T_894 = ~_T_893; // @[dec_tlu_ctl.scala 1022:59] + dec_timer_ctl int_timers ( // @[dec_tlu_ctl.scala 275:30] .clock(int_timers_clock), .reset(int_timers_reset), .io_free_clk(int_timers_io_free_clk), @@ -55593,7 +55588,7 @@ module dec_tlu_ctl( .io_en(rvclkhdr_3_io_en), .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - csr_tlu csr ( // @[dec_tlu_ctl.scala 822:15] + csr_tlu csr ( // @[dec_tlu_ctl.scala 818:15] .clock(csr_clock), .reset(csr_reset), .io_free_clk(csr_io_free_clk), @@ -55702,7 +55697,6 @@ module dec_tlu_ctl( .io_lsu_imprecise_error_load_any(csr_io_lsu_imprecise_error_load_any), .io_lsu_imprecise_error_store_any(csr_io_lsu_imprecise_error_store_any), .io_dec_tlu_mrac_ff(csr_io_dec_tlu_mrac_ff), - .io_dec_tlu_wb_coalescing_disable(csr_io_dec_tlu_wb_coalescing_disable), .io_dec_tlu_bpred_disable(csr_io_dec_tlu_bpred_disable), .io_dec_tlu_sideeffect_posted_disable(csr_io_dec_tlu_sideeffect_posted_disable), .io_dec_tlu_core_ecc_disable(csr_io_dec_tlu_core_ecc_disable), @@ -55866,7 +55860,7 @@ module dec_tlu_ctl( .io_mtdata1_t_2(csr_io_mtdata1_t_2), .io_mtdata1_t_3(csr_io_mtdata1_t_3) ); - dec_decode_csr_read csr_read ( // @[dec_tlu_ctl.scala 1015:22] + dec_decode_csr_read csr_read ( // @[dec_tlu_ctl.scala 1011:22] .io_dec_csr_rdaddr_d(csr_read_io_dec_csr_rdaddr_d), .io_csr_pkt_csr_misa(csr_read_io_csr_pkt_csr_misa), .io_csr_pkt_csr_mvendorid(csr_read_io_csr_pkt_csr_mvendorid), @@ -55936,119 +55930,118 @@ module dec_tlu_ctl( .io_csr_pkt_postsync(csr_read_io_csr_pkt_postsync), .io_csr_pkt_legal(csr_read_io_csr_pkt_legal) ); - assign io_tlu_exu_dec_tlu_meihap = csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 881:52] - assign io_tlu_exu_dec_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[dec_tlu_ctl.scala 807:49] - assign io_tlu_exu_dec_tlu_flush_path_r = take_reset ? io_rst_vec : _T_852; // @[dec_tlu_ctl.scala 808:49] - assign io_dec_dbg_cmd_done = io_dec_tlu_i0_valid_r & io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 492:29] - assign io_dec_dbg_cmd_fail = illegal_r & io_dec_dbg_cmd_done; // @[dec_tlu_ctl.scala 493:29] - assign io_dec_tlu_dbg_halted = dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 474:41] - assign io_dec_tlu_debug_mode = debug_mode_status; // @[dec_tlu_ctl.scala 475:41] - assign io_dec_tlu_resume_ack = _T_190; // @[dec_tlu_ctl.scala 458:49] - assign io_dec_tlu_debug_stall = debug_halt_req_f; // @[dec_tlu_ctl.scala 473:41] - assign io_dec_tlu_mpc_halted_only = _T_65; // @[dec_tlu_ctl.scala 373:49] - assign io_dec_tlu_flush_extint = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 481:33] - assign io_trigger_pkt_any_0_select = csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_0_match_pkt = csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_0_store = csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_0_load = csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_0_execute = csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_0_m = csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_0_tdata2 = csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_1_select = csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_1_match_pkt = csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_1_store = csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_1_load = csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_1_execute = csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_1_m = csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_1_tdata2 = csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_2_select = csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_2_match_pkt = csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_2_store = csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_2_load = csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_2_execute = csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_2_m = csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_2_tdata2 = csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_3_select = csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_3_match_pkt = csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_3_store = csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_3_load = csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_3_execute = csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_3_m = csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 887:40] - assign io_trigger_pkt_any_3_tdata2 = csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 887:40] - assign io_o_cpu_halt_status = _T_353; // @[dec_tlu_ctl.scala 578:49] - assign io_o_cpu_halt_ack = _T_354; // @[dec_tlu_ctl.scala 579:49] - assign io_o_cpu_run_ack = _T_355; // @[dec_tlu_ctl.scala 580:49] - assign io_o_debug_mode_status = debug_mode_status; // @[dec_tlu_ctl.scala 601:27] - assign io_mpc_debug_halt_ack = mpc_debug_halt_ack_f; // @[dec_tlu_ctl.scala 398:31] - assign io_mpc_debug_run_ack = mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 399:31] - assign io_debug_brkpt_status = debug_brkpt_status_f; // @[dec_tlu_ctl.scala 400:31] - assign io_dec_tlu_meicurpl = csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 880:44] - assign io_dec_tlu_meipt = csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 882:44] - assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 902:40] - assign io_dec_csr_legal_d = _T_887 & _T_894; // @[dec_tlu_ctl.scala 1026:20] - assign io_dec_tlu_i0_kill_writeb_wb = _T_32; // @[dec_tlu_ctl.scala 333:41] - assign io_dec_tlu_i0_kill_writeb_r = _T_427 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 339:41] - assign io_dec_tlu_wr_pause_r = csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 904:40] - assign io_dec_tlu_flush_pause_r = _T_208 & _T_209; // @[dec_tlu_ctl.scala 484:34] - assign io_dec_tlu_presync_d = _T_864 & _T_865; // @[dec_tlu_ctl.scala 1019:23] - assign io_dec_tlu_postsync_d = csr_pkt_postsync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1020:23] - assign io_dec_tlu_perfcnt0 = csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 890:40] - assign io_dec_tlu_perfcnt1 = csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 891:40] - assign io_dec_tlu_perfcnt2 = csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 892:40] - assign io_dec_tlu_perfcnt3 = csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 893:40] - assign io_dec_tlu_i0_exc_valid_wb1 = csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 884:44] - assign io_dec_tlu_i0_valid_wb1 = csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 885:44] - assign io_dec_tlu_int_valid_wb1 = csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 883:44] - assign io_dec_tlu_exc_cause_wb1 = csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 889:40] - assign io_dec_tlu_mtval_wb1 = csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 888:40] - assign io_dec_tlu_pipelining_disable = csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 903:40] - assign io_dec_tlu_dma_qos_prty = csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 911:40] - assign io_dec_tlu_misc_clk_override = csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 894:40] - assign io_dec_tlu_dec_clk_override = csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 895:40] - assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 897:40] - assign io_dec_tlu_bus_clk_override = csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 898:40] - assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 899:40] - assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 900:40] - assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 901:40] - assign io_tlu_bp_dec_tlu_br0_r_pkt_valid = _T_459 & _T_462; // @[dec_tlu_ctl.scala 657:57] - assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist = io_tlu_exu_exu_i0_br_hist_r; // @[dec_tlu_ctl.scala 654:65] - assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error = _T_453 & _T_429; // @[dec_tlu_ctl.scala 655:57] - assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error = _T_455 & _T_429; // @[dec_tlu_ctl.scala 656:57] - assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_way = io_exu_i0_br_way_r; // @[dec_tlu_ctl.scala 658:65] - assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle = io_tlu_exu_exu_i0_br_middle_r; // @[dec_tlu_ctl.scala 659:65] - assign io_tlu_bp_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 805:49] - assign io_tlu_bp_dec_tlu_flush_leak_one_wb = _T_233 & _T_234; // @[dec_tlu_ctl.scala 488:45] - assign io_tlu_bp_dec_tlu_bpred_disable = csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 907:47] - assign io_tlu_ifc_dec_tlu_flush_noredir_wb = _T_205 | take_ext_int_start; // @[dec_tlu_ctl.scala 479:45] - assign io_tlu_ifc_dec_tlu_mrac_ff = csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 905:48] - assign io_tlu_mem_dec_tlu_flush_err_wb = io_tlu_exu_dec_tlu_flush_lower_r & _T_433; // @[dec_tlu_ctl.scala 489:41] - assign io_tlu_mem_dec_tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 632:37] - assign io_tlu_mem_dec_tlu_force_halt = _T_33; // @[dec_tlu_ctl.scala 335:57] - assign io_tlu_mem_dec_tlu_fence_i_wb = _T_492 & _T_470; // @[dec_tlu_ctl.scala 677:39] - assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata = csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 886:52] - assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics = csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 886:52] - assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid = csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 886:52] - assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid = csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 886:52] - assign io_tlu_mem_dec_tlu_core_ecc_disable = csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 909:48] - assign io_tlu_busbuff_dec_tlu_external_ldfwd_disable = csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 910:52] - assign io_tlu_busbuff_dec_tlu_wb_coalescing_disable = csr_io_dec_tlu_wb_coalescing_disable; // @[dec_tlu_ctl.scala 906:52] - assign io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 908:52] + assign io_tlu_exu_dec_tlu_meihap = csr_io_dec_tlu_meihap; // @[dec_tlu_ctl.scala 877:52] + assign io_tlu_exu_dec_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[dec_tlu_ctl.scala 803:49] + assign io_tlu_exu_dec_tlu_flush_path_r = take_reset ? io_rst_vec : _T_852; // @[dec_tlu_ctl.scala 804:49] + assign io_tlu_dma_dec_tlu_dma_qos_prty = csr_io_dec_tlu_dma_qos_prty; // @[dec_tlu_ctl.scala 907:48] + assign io_dec_dbg_cmd_done = io_dec_tlu_i0_valid_r & io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 488:29] + assign io_dec_dbg_cmd_fail = illegal_r & io_dec_dbg_cmd_done; // @[dec_tlu_ctl.scala 489:29] + assign io_dec_tlu_dbg_halted = dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 470:41] + assign io_dec_tlu_debug_mode = debug_mode_status; // @[dec_tlu_ctl.scala 471:41] + assign io_dec_tlu_resume_ack = _T_190; // @[dec_tlu_ctl.scala 454:49] + assign io_dec_tlu_debug_stall = debug_halt_req_f; // @[dec_tlu_ctl.scala 469:41] + assign io_dec_tlu_mpc_halted_only = _T_65; // @[dec_tlu_ctl.scala 369:49] + assign io_dec_tlu_flush_extint = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 477:33] + assign io_trigger_pkt_any_0_select = csr_io_trigger_pkt_any_0_select; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_0_match_pkt = csr_io_trigger_pkt_any_0_match_pkt; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_0_store = csr_io_trigger_pkt_any_0_store; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_0_load = csr_io_trigger_pkt_any_0_load; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_0_execute = csr_io_trigger_pkt_any_0_execute; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_0_m = csr_io_trigger_pkt_any_0_m; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_0_tdata2 = csr_io_trigger_pkt_any_0_tdata2; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_1_select = csr_io_trigger_pkt_any_1_select; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_1_match_pkt = csr_io_trigger_pkt_any_1_match_pkt; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_1_store = csr_io_trigger_pkt_any_1_store; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_1_load = csr_io_trigger_pkt_any_1_load; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_1_execute = csr_io_trigger_pkt_any_1_execute; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_1_m = csr_io_trigger_pkt_any_1_m; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_1_tdata2 = csr_io_trigger_pkt_any_1_tdata2; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_2_select = csr_io_trigger_pkt_any_2_select; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_2_match_pkt = csr_io_trigger_pkt_any_2_match_pkt; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_2_store = csr_io_trigger_pkt_any_2_store; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_2_load = csr_io_trigger_pkt_any_2_load; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_2_execute = csr_io_trigger_pkt_any_2_execute; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_2_m = csr_io_trigger_pkt_any_2_m; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_2_tdata2 = csr_io_trigger_pkt_any_2_tdata2; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_3_select = csr_io_trigger_pkt_any_3_select; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_3_match_pkt = csr_io_trigger_pkt_any_3_match_pkt; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_3_store = csr_io_trigger_pkt_any_3_store; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_3_load = csr_io_trigger_pkt_any_3_load; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_3_execute = csr_io_trigger_pkt_any_3_execute; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_3_m = csr_io_trigger_pkt_any_3_m; // @[dec_tlu_ctl.scala 883:40] + assign io_trigger_pkt_any_3_tdata2 = csr_io_trigger_pkt_any_3_tdata2; // @[dec_tlu_ctl.scala 883:40] + assign io_o_cpu_halt_status = _T_353; // @[dec_tlu_ctl.scala 574:49] + assign io_o_cpu_halt_ack = _T_354; // @[dec_tlu_ctl.scala 575:49] + assign io_o_cpu_run_ack = _T_355; // @[dec_tlu_ctl.scala 576:49] + assign io_o_debug_mode_status = debug_mode_status; // @[dec_tlu_ctl.scala 597:27] + assign io_mpc_debug_halt_ack = mpc_debug_halt_ack_f; // @[dec_tlu_ctl.scala 394:31] + assign io_mpc_debug_run_ack = mpc_debug_run_ack_f; // @[dec_tlu_ctl.scala 395:31] + assign io_debug_brkpt_status = debug_brkpt_status_f; // @[dec_tlu_ctl.scala 396:31] + assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[dec_tlu_ctl.scala 898:40] + assign io_dec_csr_legal_d = _T_887 & _T_894; // @[dec_tlu_ctl.scala 1022:20] + assign io_dec_tlu_i0_kill_writeb_wb = _T_32; // @[dec_tlu_ctl.scala 329:41] + assign io_dec_tlu_i0_kill_writeb_r = _T_427 | i0_trigger_hit_raw_r; // @[dec_tlu_ctl.scala 335:41] + assign io_dec_tlu_wr_pause_r = csr_io_dec_tlu_wr_pause_r; // @[dec_tlu_ctl.scala 900:40] + assign io_dec_tlu_flush_pause_r = _T_208 & _T_209; // @[dec_tlu_ctl.scala 480:34] + assign io_dec_tlu_presync_d = _T_864 & _T_865; // @[dec_tlu_ctl.scala 1015:23] + assign io_dec_tlu_postsync_d = csr_pkt_postsync & io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 1016:23] + assign io_dec_tlu_perfcnt0 = csr_io_dec_tlu_perfcnt0; // @[dec_tlu_ctl.scala 886:40] + assign io_dec_tlu_perfcnt1 = csr_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 887:40] + assign io_dec_tlu_perfcnt2 = csr_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 888:40] + assign io_dec_tlu_perfcnt3 = csr_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 889:40] + assign io_dec_tlu_i0_exc_valid_wb1 = csr_io_dec_tlu_i0_exc_valid_wb1; // @[dec_tlu_ctl.scala 880:44] + assign io_dec_tlu_i0_valid_wb1 = csr_io_dec_tlu_i0_valid_wb1; // @[dec_tlu_ctl.scala 881:44] + assign io_dec_tlu_int_valid_wb1 = csr_io_dec_tlu_int_valid_wb1; // @[dec_tlu_ctl.scala 879:44] + assign io_dec_tlu_exc_cause_wb1 = csr_io_dec_tlu_exc_cause_wb1; // @[dec_tlu_ctl.scala 885:40] + assign io_dec_tlu_mtval_wb1 = csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 884:40] + assign io_dec_tlu_pipelining_disable = csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 899:40] + assign io_dec_tlu_misc_clk_override = csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 890:40] + assign io_dec_tlu_dec_clk_override = csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 891:40] + assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 893:40] + assign io_dec_tlu_bus_clk_override = csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 894:40] + assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 895:40] + assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 896:40] + assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 897:40] + assign io_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 801:41] + assign io_tlu_bp_dec_tlu_br0_r_pkt_valid = _T_459 & _T_462; // @[dec_tlu_ctl.scala 653:57] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist = io_tlu_exu_exu_i0_br_hist_r; // @[dec_tlu_ctl.scala 650:65] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error = _T_453 & _T_429; // @[dec_tlu_ctl.scala 651:57] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error = _T_455 & _T_429; // @[dec_tlu_ctl.scala 652:57] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_way = io_exu_i0_br_way_r; // @[dec_tlu_ctl.scala 654:65] + assign io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle = io_tlu_exu_exu_i0_br_middle_r; // @[dec_tlu_ctl.scala 655:65] + assign io_tlu_bp_dec_tlu_flush_leak_one_wb = _T_233 & _T_234; // @[dec_tlu_ctl.scala 484:45] + assign io_tlu_bp_dec_tlu_bpred_disable = csr_io_dec_tlu_bpred_disable; // @[dec_tlu_ctl.scala 903:47] + assign io_tlu_ifc_dec_tlu_flush_noredir_wb = _T_205 | take_ext_int_start; // @[dec_tlu_ctl.scala 475:45] + assign io_tlu_ifc_dec_tlu_mrac_ff = csr_io_dec_tlu_mrac_ff; // @[dec_tlu_ctl.scala 901:48] + assign io_tlu_mem_dec_tlu_flush_err_wb = io_tlu_exu_dec_tlu_flush_lower_r & _T_433; // @[dec_tlu_ctl.scala 485:41] + assign io_tlu_mem_dec_tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 628:37] + assign io_tlu_mem_dec_tlu_force_halt = _T_33; // @[dec_tlu_ctl.scala 331:57] + assign io_tlu_mem_dec_tlu_fence_i_wb = _T_492 & _T_470; // @[dec_tlu_ctl.scala 673:39] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata = csr_io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec_tlu_ctl.scala 882:52] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics = csr_io_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec_tlu_ctl.scala 882:52] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid = csr_io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec_tlu_ctl.scala 882:52] + assign io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid = csr_io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec_tlu_ctl.scala 882:52] + assign io_tlu_mem_dec_tlu_core_ecc_disable = csr_io_dec_tlu_core_ecc_disable; // @[dec_tlu_ctl.scala 905:48] + assign io_tlu_busbuff_dec_tlu_external_ldfwd_disable = csr_io_dec_tlu_external_ldfwd_disable; // @[dec_tlu_ctl.scala 906:52] + assign io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = csr_io_dec_tlu_sideeffect_posted_disable; // @[dec_tlu_ctl.scala 904:52] + assign io_dec_pic_dec_tlu_meicurpl = csr_io_dec_tlu_meicurpl; // @[dec_tlu_ctl.scala 876:52] + assign io_dec_pic_dec_tlu_meipt = csr_io_dec_tlu_meipt; // @[dec_tlu_ctl.scala 878:52] assign int_timers_clock = clock; assign int_timers_reset = reset; - assign int_timers_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 280:57] - assign int_timers_io_scan_mode = io_scan_mode; // @[dec_tlu_ctl.scala 281:57] - assign int_timers_io_dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 282:49] - assign int_timers_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 284:49] - assign int_timers_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 285:49] - assign int_timers_io_csr_mitctl0 = csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 286:57] - assign int_timers_io_csr_mitctl1 = csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 287:57] - assign int_timers_io_csr_mitb0 = csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 288:57] - assign int_timers_io_csr_mitb1 = csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 289:57] - assign int_timers_io_csr_mitcnt0 = csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 290:57] - assign int_timers_io_csr_mitcnt1 = csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 291:57] - assign int_timers_io_dec_pause_state = io_dec_pause_state; // @[dec_tlu_ctl.scala 292:49] - assign int_timers_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 293:49] - assign int_timers_io_internal_dbg_halt_timers = debug_mode_status & _T_665; // @[dec_tlu_ctl.scala 294:47] + assign int_timers_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 276:57] + assign int_timers_io_scan_mode = io_scan_mode; // @[dec_tlu_ctl.scala 277:57] + assign int_timers_io_dec_csr_wen_r_mod = csr_io_dec_csr_wen_r_mod; // @[dec_tlu_ctl.scala 278:49] + assign int_timers_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 280:49] + assign int_timers_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 281:49] + assign int_timers_io_csr_mitctl0 = csr_read_io_csr_pkt_csr_mitctl0; // @[dec_tlu_ctl.scala 282:57] + assign int_timers_io_csr_mitctl1 = csr_read_io_csr_pkt_csr_mitctl1; // @[dec_tlu_ctl.scala 283:57] + assign int_timers_io_csr_mitb0 = csr_read_io_csr_pkt_csr_mitb0; // @[dec_tlu_ctl.scala 284:57] + assign int_timers_io_csr_mitb1 = csr_read_io_csr_pkt_csr_mitb1; // @[dec_tlu_ctl.scala 285:57] + assign int_timers_io_csr_mitcnt0 = csr_read_io_csr_pkt_csr_mitcnt0; // @[dec_tlu_ctl.scala 286:57] + assign int_timers_io_csr_mitcnt1 = csr_read_io_csr_pkt_csr_mitcnt1; // @[dec_tlu_ctl.scala 287:57] + assign int_timers_io_dec_pause_state = io_dec_pause_state; // @[dec_tlu_ctl.scala 288:49] + assign int_timers_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 289:49] + assign int_timers_io_internal_dbg_halt_timers = debug_mode_status & _T_665; // @[dec_tlu_ctl.scala 290:47] assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17] assign rvclkhdr_io_en = dec_csr_wen_r_mod | io_dec_tlu_dec_clk_override; // @[lib.scala 329:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 330:23] @@ -56063,197 +56056,197 @@ module dec_tlu_ctl( assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 330:23] assign csr_clock = clock; assign csr_reset = reset; - assign csr_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 823:44] - assign csr_io_active_clk = io_active_clk; // @[dec_tlu_ctl.scala 824:44] - assign csr_io_scan_mode = io_scan_mode; // @[dec_tlu_ctl.scala 825:44] - assign csr_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 826:44] - assign csr_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 827:44] - assign csr_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 828:44] - assign csr_io_dec_csr_wen_unq_d = io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 829:44] - assign csr_io_dec_i0_decode_d = io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 830:44] - assign csr_io_ifu_ic_debug_rd_data_valid = io_tlu_mem_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 831:44] - assign csr_io_ifu_pmu_bus_trxn = io_tlu_mem_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 832:44] - assign csr_io_dma_iccm_stall_any = io_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 833:44] - assign csr_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 834:44] - assign csr_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 835:44] - assign csr_io_dec_pmu_presync_stall = io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 836:44] - assign csr_io_dec_pmu_postsync_stall = io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 837:44] - assign csr_io_dec_pmu_decode_stall = io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 838:44] - assign csr_io_ifu_pmu_fetch_stall = io_tlu_ifc_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 839:44] - assign csr_io_dec_tlu_packet_r_icaf_type = io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 840:44] - assign csr_io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 840:44] - assign csr_io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 840:44] - assign csr_io_dec_tlu_packet_r_pmu_divide = io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 840:44] - assign csr_io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 840:44] - assign csr_io_exu_pmu_i0_br_ataken = io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 841:44] - assign csr_io_exu_pmu_i0_br_misp = io_tlu_exu_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 842:44] - assign csr_io_dec_pmu_instr_decoded = io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 843:44] - assign csr_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 844:44] - assign csr_io_exu_pmu_i0_pc4 = io_tlu_exu_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 845:44] - assign csr_io_ifu_pmu_ic_miss = io_tlu_mem_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 846:44] - assign csr_io_ifu_pmu_ic_hit = io_tlu_mem_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 847:44] - assign csr_io_dec_csr_wen_r = io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 848:44] - assign csr_io_dec_tlu_dbg_halted = io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 849:44] - assign csr_io_dma_pmu_dccm_write = io_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 850:44] - assign csr_io_dma_pmu_dccm_read = io_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 851:44] - assign csr_io_dma_pmu_any_write = io_dma_pmu_any_write; // @[dec_tlu_ctl.scala 852:44] - assign csr_io_dma_pmu_any_read = io_dma_pmu_any_read; // @[dec_tlu_ctl.scala 853:44] - assign csr_io_lsu_pmu_bus_busy = io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 854:44] - assign csr_io_dec_tlu_i0_pc_r = io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 855:44] - assign csr_io_dec_tlu_i0_valid_r = io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 856:44] - assign csr_io_dec_csr_any_unq_d = io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 858:44] - assign csr_io_ifu_pmu_bus_busy = io_tlu_mem_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 859:44] - assign csr_io_lsu_pmu_bus_error = io_tlu_busbuff_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 860:44] - assign csr_io_ifu_pmu_bus_error = io_tlu_mem_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 861:44] - assign csr_io_lsu_pmu_bus_misaligned = io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 862:44] - assign csr_io_lsu_pmu_bus_trxn = io_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 863:44] - assign csr_io_ifu_ic_debug_rd_data = io_tlu_mem_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 864:44] - assign csr_io_pic_pl = io_pic_pl; // @[dec_tlu_ctl.scala 865:44] - assign csr_io_pic_claimid = io_pic_claimid; // @[dec_tlu_ctl.scala 866:44] - assign csr_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 867:44] - assign csr_io_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 868:44] - assign csr_io_lsu_imprecise_error_load_any = io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 869:44] - assign csr_io_lsu_imprecise_error_store_any = io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 870:44] - assign csr_io_dec_illegal_inst = io_dec_illegal_inst; // @[dec_tlu_ctl.scala 871:44 dec_tlu_ctl.scala 912:44] - assign csr_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 872:44 dec_tlu_ctl.scala 913:44] - assign csr_io_mexintpend = io_mexintpend; // @[dec_tlu_ctl.scala 873:44 dec_tlu_ctl.scala 914:44] - assign csr_io_exu_npc_r = io_tlu_exu_exu_npc_r; // @[dec_tlu_ctl.scala 874:44 dec_tlu_ctl.scala 915:44] - assign csr_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 875:44 dec_tlu_ctl.scala 916:44] - assign csr_io_rst_vec = io_rst_vec; // @[dec_tlu_ctl.scala 876:44 dec_tlu_ctl.scala 917:44] - assign csr_io_core_id = io_core_id; // @[dec_tlu_ctl.scala 877:44 dec_tlu_ctl.scala 918:44] - assign csr_io_dec_timer_rddata_d = int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 878:44 dec_tlu_ctl.scala 919:44] - assign csr_io_dec_timer_read_d = int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 879:44 dec_tlu_ctl.scala 920:44] - assign csr_io_rfpc_i0_r = _T_438 & _T_439; // @[dec_tlu_ctl.scala 923:39] - assign csr_io_i0_trigger_hit_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 924:39] - assign csr_io_exc_or_int_valid_r = _T_855 | mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 925:39] - assign csr_io_mret_r = _T_487 & _T_470; // @[dec_tlu_ctl.scala 926:39] - assign csr_io_dcsr_single_step_running_f = dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 927:39] - assign csr_io_dec_timer_t0_pulse = int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 928:39] - assign csr_io_dec_timer_t1_pulse = int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 929:39] - assign csr_io_timer_int_sync = syncro_ff[5]; // @[dec_tlu_ctl.scala 930:39] - assign csr_io_soft_int_sync = syncro_ff[4]; // @[dec_tlu_ctl.scala 931:39] - assign csr_io_csr_wr_clk = rvclkhdr_io_l1clk; // @[dec_tlu_ctl.scala 932:39] - assign csr_io_ebreak_to_debug_mode_r = _T_519 & _T_470; // @[dec_tlu_ctl.scala 933:39] - assign csr_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 934:39] - assign csr_io_lsu_fir_error = io_lsu_fir_error; // @[dec_tlu_ctl.scala 935:39] - assign csr_io_tlu_flush_lower_r_d1 = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 936:39] - assign csr_io_dec_tlu_flush_noredir_r_d1 = dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 937:39] - assign csr_io_tlu_flush_path_r_d1 = tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 938:39] - assign csr_io_reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 939:39] - assign csr_io_interrupt_valid_r = _T_766 | take_int_timer1_int; // @[dec_tlu_ctl.scala 940:39] - assign csr_io_i0_exception_valid_r = _T_527 & _T_528; // @[dec_tlu_ctl.scala 941:39] - assign csr_io_lsu_exc_valid_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 942:39] - assign csr_io_mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[dec_tlu_ctl.scala 943:39] - assign csr_io_e4e5_int_clk = rvclkhdr_3_io_l1clk; // @[dec_tlu_ctl.scala 944:39] - assign csr_io_lsu_i0_exc_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 945:39] - assign csr_io_inst_acc_r = _T_511 & _T_465; // @[dec_tlu_ctl.scala 946:39] - assign csr_io_inst_acc_second_r = io_dec_tlu_packet_r_icaf_f1; // @[dec_tlu_ctl.scala 947:39] - assign csr_io_take_nmi = _T_756 & _T_760; // @[dec_tlu_ctl.scala 948:39] - assign csr_io_lsu_error_pkt_addr_r = io_lsu_error_pkt_r_bits_addr; // @[dec_tlu_ctl.scala 949:39] - assign csr_io_exc_cause_r = _T_603 | _T_591; // @[dec_tlu_ctl.scala 950:39] - assign csr_io_i0_valid_wb = i0_valid_wb; // @[dec_tlu_ctl.scala 951:39] - assign csr_io_exc_or_int_valid_r_d1 = exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 952:39] - assign csr_io_interrupt_valid_r_d1 = interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 953:39] - assign csr_io_clk_override = io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 954:39] - assign csr_io_i0_exception_valid_r_d1 = i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 955:39] - assign csr_io_lsu_i0_exc_r_d1 = lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 956:39] - assign csr_io_exc_cause_wb = exc_cause_wb; // @[dec_tlu_ctl.scala 957:39] - assign csr_io_nmi_lsu_store_type = _T_58 | _T_60; // @[dec_tlu_ctl.scala 958:39] - assign csr_io_nmi_lsu_load_type = _T_50 | _T_52; // @[dec_tlu_ctl.scala 959:39] - assign csr_io_tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 960:39] - assign csr_io_ebreak_r = _T_469 & _T_470; // @[dec_tlu_ctl.scala 961:39] - assign csr_io_ecall_r = _T_475 & _T_470; // @[dec_tlu_ctl.scala 962:39] - assign csr_io_illegal_r = _T_481 & _T_470; // @[dec_tlu_ctl.scala 963:39] - assign csr_io_mdseac_locked_f = mdseac_locked_f; // @[dec_tlu_ctl.scala 964:39] - assign csr_io_nmi_int_detected_f = nmi_int_detected_f; // @[dec_tlu_ctl.scala 965:39] - assign csr_io_internal_dbg_halt_mode_f2 = internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 966:39] - assign csr_io_ext_int_freeze_d1 = ext_int_freeze_d1; // @[dec_tlu_ctl.scala 967:39] - assign csr_io_ic_perr_r_d1 = ic_perr_r_d1; // @[dec_tlu_ctl.scala 968:39] - assign csr_io_iccm_sbecc_r_d1 = iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 969:39] - assign csr_io_lsu_single_ecc_error_r_d1 = lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 970:39] - assign csr_io_ifu_miss_state_idle_f = ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 971:39] - assign csr_io_lsu_idle_any_f = lsu_idle_any_f; // @[dec_tlu_ctl.scala 972:39] - assign csr_io_dbg_tlu_halted_f = dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 973:39] - assign csr_io_dbg_tlu_halted = _T_164 | _T_166; // @[dec_tlu_ctl.scala 974:39] - assign csr_io_debug_halt_req_f = debug_halt_req_f; // @[dec_tlu_ctl.scala 975:51] - assign csr_io_take_ext_int_start = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 976:47] - assign csr_io_trigger_hit_dmode_r_d1 = trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 977:43] - assign csr_io_trigger_hit_r_d1 = trigger_hit_r_d1; // @[dec_tlu_ctl.scala 978:43] - assign csr_io_dcsr_single_step_done_f = dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 979:43] - assign csr_io_ebreak_to_debug_mode_r_d1 = ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 980:39] - assign csr_io_debug_halt_req = _T_114 & _T_107; // @[dec_tlu_ctl.scala 981:51] - assign csr_io_allow_dbg_halt_csr_write = debug_mode_status & _T_77; // @[dec_tlu_ctl.scala 982:39] - assign csr_io_internal_dbg_halt_mode_f = debug_mode_status; // @[dec_tlu_ctl.scala 983:39] - assign csr_io_enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 984:39] - assign csr_io_internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[dec_tlu_ctl.scala 985:39] - assign csr_io_request_debug_mode_done = _T_183 & _T_136; // @[dec_tlu_ctl.scala 986:39] - assign csr_io_request_debug_mode_r = _T_180 | _T_182; // @[dec_tlu_ctl.scala 987:39] - assign csr_io_update_hit_bit_r = _T_342 & i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 988:39] - assign csr_io_take_timer_int = _T_703 & _T_704; // @[dec_tlu_ctl.scala 989:39] - assign csr_io_take_int_timer0_int = _T_717 & _T_704; // @[dec_tlu_ctl.scala 990:39] - assign csr_io_take_int_timer1_int = _T_734 & _T_704; // @[dec_tlu_ctl.scala 991:39] - assign csr_io_take_ext_int = take_ext_int_start_d3 & _T_685; // @[dec_tlu_ctl.scala 992:39] - assign csr_io_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[dec_tlu_ctl.scala 993:39] - assign csr_io_dec_tlu_br0_error_r = _T_453 & _T_429; // @[dec_tlu_ctl.scala 994:39] - assign csr_io_dec_tlu_br0_start_error_r = _T_455 & _T_429; // @[dec_tlu_ctl.scala 995:39] - assign csr_io_lsu_pmu_load_external_r = lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 996:39] - assign csr_io_lsu_pmu_store_external_r = lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 997:39] - assign csr_io_csr_pkt_csr_misa = csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mstatus = csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mtvec = csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mip = csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mie = csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mcyclel = csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mcycleh = csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_minstretl = csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_minstreth = csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mscratch = csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mepc = csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mcause = csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mscause = csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mtval = csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mrac = csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_meivt = csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_meipt = csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_meicurpl = csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_meicidpl = csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mcgc = csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mfdc = csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mtsel = csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mtdata1 = csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mtdata2 = csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mhpmc3 = csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mhpmc4 = csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mhpmc5 = csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mhpmc6 = csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mhpmc3h = csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mhpmc4h = csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mhpmc5h = csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mhpmc6h = csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mhpme3 = csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mhpme4 = csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mhpme5 = csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mhpme6 = csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mcountinhibit = csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mpmc = csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_micect = csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_miccmect = csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mdccmect = csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mfdht = csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_mfdhs = csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 998:39] - assign csr_io_csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 998:39] - assign csr_read_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1016:37] + assign csr_io_free_clk = io_free_clk; // @[dec_tlu_ctl.scala 819:44] + assign csr_io_active_clk = io_active_clk; // @[dec_tlu_ctl.scala 820:44] + assign csr_io_scan_mode = io_scan_mode; // @[dec_tlu_ctl.scala 821:44] + assign csr_io_dec_csr_wrdata_r = io_dec_csr_wrdata_r; // @[dec_tlu_ctl.scala 822:44] + assign csr_io_dec_csr_wraddr_r = io_dec_csr_wraddr_r; // @[dec_tlu_ctl.scala 823:44] + assign csr_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 824:44] + assign csr_io_dec_csr_wen_unq_d = io_dec_csr_wen_unq_d; // @[dec_tlu_ctl.scala 825:44] + assign csr_io_dec_i0_decode_d = io_dec_i0_decode_d; // @[dec_tlu_ctl.scala 826:44] + assign csr_io_ifu_ic_debug_rd_data_valid = io_tlu_mem_ifu_ic_debug_rd_data_valid; // @[dec_tlu_ctl.scala 827:44] + assign csr_io_ifu_pmu_bus_trxn = io_tlu_mem_ifu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 828:44] + assign csr_io_dma_iccm_stall_any = io_tlu_dma_dma_iccm_stall_any; // @[dec_tlu_ctl.scala 829:44] + assign csr_io_dma_dccm_stall_any = io_tlu_dma_dma_dccm_stall_any; // @[dec_tlu_ctl.scala 830:44] + assign csr_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec_tlu_ctl.scala 831:44] + assign csr_io_dec_pmu_presync_stall = io_dec_pmu_presync_stall; // @[dec_tlu_ctl.scala 832:44] + assign csr_io_dec_pmu_postsync_stall = io_dec_pmu_postsync_stall; // @[dec_tlu_ctl.scala 833:44] + assign csr_io_dec_pmu_decode_stall = io_dec_pmu_decode_stall; // @[dec_tlu_ctl.scala 834:44] + assign csr_io_ifu_pmu_fetch_stall = io_tlu_ifc_ifu_pmu_fetch_stall; // @[dec_tlu_ctl.scala 835:44] + assign csr_io_dec_tlu_packet_r_icaf_type = io_dec_tlu_packet_r_icaf_type; // @[dec_tlu_ctl.scala 836:44] + assign csr_io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_packet_r_pmu_i0_itype; // @[dec_tlu_ctl.scala 836:44] + assign csr_io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec_tlu_ctl.scala 836:44] + assign csr_io_dec_tlu_packet_r_pmu_divide = io_dec_tlu_packet_r_pmu_divide; // @[dec_tlu_ctl.scala 836:44] + assign csr_io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec_tlu_ctl.scala 836:44] + assign csr_io_exu_pmu_i0_br_ataken = io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec_tlu_ctl.scala 837:44] + assign csr_io_exu_pmu_i0_br_misp = io_tlu_exu_exu_pmu_i0_br_misp; // @[dec_tlu_ctl.scala 838:44] + assign csr_io_dec_pmu_instr_decoded = io_dec_pmu_instr_decoded; // @[dec_tlu_ctl.scala 839:44] + assign csr_io_ifu_pmu_instr_aligned = io_ifu_pmu_instr_aligned; // @[dec_tlu_ctl.scala 840:44] + assign csr_io_exu_pmu_i0_pc4 = io_tlu_exu_exu_pmu_i0_pc4; // @[dec_tlu_ctl.scala 841:44] + assign csr_io_ifu_pmu_ic_miss = io_tlu_mem_ifu_pmu_ic_miss; // @[dec_tlu_ctl.scala 842:44] + assign csr_io_ifu_pmu_ic_hit = io_tlu_mem_ifu_pmu_ic_hit; // @[dec_tlu_ctl.scala 843:44] + assign csr_io_dec_csr_wen_r = io_dec_csr_wen_r; // @[dec_tlu_ctl.scala 844:44] + assign csr_io_dec_tlu_dbg_halted = io_dec_tlu_dbg_halted; // @[dec_tlu_ctl.scala 845:44] + assign csr_io_dma_pmu_dccm_write = io_tlu_dma_dma_pmu_dccm_write; // @[dec_tlu_ctl.scala 846:44] + assign csr_io_dma_pmu_dccm_read = io_tlu_dma_dma_pmu_dccm_read; // @[dec_tlu_ctl.scala 847:44] + assign csr_io_dma_pmu_any_write = io_tlu_dma_dma_pmu_any_write; // @[dec_tlu_ctl.scala 848:44] + assign csr_io_dma_pmu_any_read = io_tlu_dma_dma_pmu_any_read; // @[dec_tlu_ctl.scala 849:44] + assign csr_io_lsu_pmu_bus_busy = io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec_tlu_ctl.scala 850:44] + assign csr_io_dec_tlu_i0_pc_r = io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 851:44] + assign csr_io_dec_tlu_i0_valid_r = io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 852:44] + assign csr_io_dec_csr_any_unq_d = io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 854:44] + assign csr_io_ifu_pmu_bus_busy = io_tlu_mem_ifu_pmu_bus_busy; // @[dec_tlu_ctl.scala 855:44] + assign csr_io_lsu_pmu_bus_error = io_tlu_busbuff_lsu_pmu_bus_error; // @[dec_tlu_ctl.scala 856:44] + assign csr_io_ifu_pmu_bus_error = io_tlu_mem_ifu_pmu_bus_error; // @[dec_tlu_ctl.scala 857:44] + assign csr_io_lsu_pmu_bus_misaligned = io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec_tlu_ctl.scala 858:44] + assign csr_io_lsu_pmu_bus_trxn = io_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec_tlu_ctl.scala 859:44] + assign csr_io_ifu_ic_debug_rd_data = io_tlu_mem_ifu_ic_debug_rd_data; // @[dec_tlu_ctl.scala 860:44] + assign csr_io_pic_pl = io_dec_pic_pic_pl; // @[dec_tlu_ctl.scala 861:44] + assign csr_io_pic_claimid = io_dec_pic_pic_claimid; // @[dec_tlu_ctl.scala 862:44] + assign csr_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[dec_tlu_ctl.scala 863:44] + assign csr_io_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec_tlu_ctl.scala 864:44] + assign csr_io_lsu_imprecise_error_load_any = io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec_tlu_ctl.scala 865:44] + assign csr_io_lsu_imprecise_error_store_any = io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec_tlu_ctl.scala 866:44] + assign csr_io_dec_illegal_inst = io_dec_illegal_inst; // @[dec_tlu_ctl.scala 867:44 dec_tlu_ctl.scala 908:44] + assign csr_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[dec_tlu_ctl.scala 868:44 dec_tlu_ctl.scala 909:44] + assign csr_io_mexintpend = io_dec_pic_mexintpend; // @[dec_tlu_ctl.scala 869:44 dec_tlu_ctl.scala 910:44] + assign csr_io_exu_npc_r = io_tlu_exu_exu_npc_r; // @[dec_tlu_ctl.scala 870:44 dec_tlu_ctl.scala 911:44] + assign csr_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec_tlu_ctl.scala 871:44 dec_tlu_ctl.scala 912:44] + assign csr_io_rst_vec = io_rst_vec; // @[dec_tlu_ctl.scala 872:44 dec_tlu_ctl.scala 913:44] + assign csr_io_core_id = io_core_id; // @[dec_tlu_ctl.scala 873:44 dec_tlu_ctl.scala 914:44] + assign csr_io_dec_timer_rddata_d = int_timers_io_dec_timer_rddata_d; // @[dec_tlu_ctl.scala 874:44 dec_tlu_ctl.scala 915:44] + assign csr_io_dec_timer_read_d = int_timers_io_dec_timer_read_d; // @[dec_tlu_ctl.scala 875:44 dec_tlu_ctl.scala 916:44] + assign csr_io_rfpc_i0_r = _T_438 & _T_439; // @[dec_tlu_ctl.scala 919:39] + assign csr_io_i0_trigger_hit_r = |i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 920:39] + assign csr_io_exc_or_int_valid_r = _T_855 | mepc_trigger_hit_sel_pc_r; // @[dec_tlu_ctl.scala 921:39] + assign csr_io_mret_r = _T_487 & _T_470; // @[dec_tlu_ctl.scala 922:39] + assign csr_io_dcsr_single_step_running_f = dcsr_single_step_running_f; // @[dec_tlu_ctl.scala 923:39] + assign csr_io_dec_timer_t0_pulse = int_timers_io_dec_timer_t0_pulse; // @[dec_tlu_ctl.scala 924:39] + assign csr_io_dec_timer_t1_pulse = int_timers_io_dec_timer_t1_pulse; // @[dec_tlu_ctl.scala 925:39] + assign csr_io_timer_int_sync = syncro_ff[5]; // @[dec_tlu_ctl.scala 926:39] + assign csr_io_soft_int_sync = syncro_ff[4]; // @[dec_tlu_ctl.scala 927:39] + assign csr_io_csr_wr_clk = rvclkhdr_io_l1clk; // @[dec_tlu_ctl.scala 928:39] + assign csr_io_ebreak_to_debug_mode_r = _T_519 & _T_470; // @[dec_tlu_ctl.scala 929:39] + assign csr_io_dec_tlu_pmu_fw_halted = pmu_fw_tlu_halted_f; // @[dec_tlu_ctl.scala 930:39] + assign csr_io_lsu_fir_error = io_lsu_fir_error; // @[dec_tlu_ctl.scala 931:39] + assign csr_io_tlu_flush_lower_r_d1 = tlu_flush_lower_r_d1; // @[dec_tlu_ctl.scala 932:39] + assign csr_io_dec_tlu_flush_noredir_r_d1 = dec_tlu_flush_noredir_r_d1; // @[dec_tlu_ctl.scala 933:39] + assign csr_io_tlu_flush_path_r_d1 = tlu_flush_path_r_d1; // @[dec_tlu_ctl.scala 934:39] + assign csr_io_reset_delayed = reset_detect ^ reset_detected; // @[dec_tlu_ctl.scala 935:39] + assign csr_io_interrupt_valid_r = _T_766 | take_int_timer1_int; // @[dec_tlu_ctl.scala 936:39] + assign csr_io_i0_exception_valid_r = _T_527 & _T_528; // @[dec_tlu_ctl.scala 937:39] + assign csr_io_lsu_exc_valid_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 938:39] + assign csr_io_mepc_trigger_hit_sel_pc_r = i0_trigger_hit_raw_r & _T_345; // @[dec_tlu_ctl.scala 939:39] + assign csr_io_e4e5_int_clk = rvclkhdr_3_io_l1clk; // @[dec_tlu_ctl.scala 940:39] + assign csr_io_lsu_i0_exc_r = _T_405 & _T_470; // @[dec_tlu_ctl.scala 941:39] + assign csr_io_inst_acc_r = _T_511 & _T_465; // @[dec_tlu_ctl.scala 942:39] + assign csr_io_inst_acc_second_r = io_dec_tlu_packet_r_icaf_f1; // @[dec_tlu_ctl.scala 943:39] + assign csr_io_take_nmi = _T_756 & _T_760; // @[dec_tlu_ctl.scala 944:39] + assign csr_io_lsu_error_pkt_addr_r = io_lsu_error_pkt_r_bits_addr; // @[dec_tlu_ctl.scala 945:39] + assign csr_io_exc_cause_r = _T_603 | _T_591; // @[dec_tlu_ctl.scala 946:39] + assign csr_io_i0_valid_wb = i0_valid_wb; // @[dec_tlu_ctl.scala 947:39] + assign csr_io_exc_or_int_valid_r_d1 = exc_or_int_valid_r_d1; // @[dec_tlu_ctl.scala 948:39] + assign csr_io_interrupt_valid_r_d1 = interrupt_valid_r_d1; // @[dec_tlu_ctl.scala 949:39] + assign csr_io_clk_override = io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 950:39] + assign csr_io_i0_exception_valid_r_d1 = i0_exception_valid_r_d1; // @[dec_tlu_ctl.scala 951:39] + assign csr_io_lsu_i0_exc_r_d1 = lsu_i0_exc_r_d1; // @[dec_tlu_ctl.scala 952:39] + assign csr_io_exc_cause_wb = exc_cause_wb; // @[dec_tlu_ctl.scala 953:39] + assign csr_io_nmi_lsu_store_type = _T_58 | _T_60; // @[dec_tlu_ctl.scala 954:39] + assign csr_io_nmi_lsu_load_type = _T_50 | _T_52; // @[dec_tlu_ctl.scala 955:39] + assign csr_io_tlu_i0_commit_cmt = _T_422 & _T_465; // @[dec_tlu_ctl.scala 956:39] + assign csr_io_ebreak_r = _T_469 & _T_470; // @[dec_tlu_ctl.scala 957:39] + assign csr_io_ecall_r = _T_475 & _T_470; // @[dec_tlu_ctl.scala 958:39] + assign csr_io_illegal_r = _T_481 & _T_470; // @[dec_tlu_ctl.scala 959:39] + assign csr_io_mdseac_locked_f = mdseac_locked_f; // @[dec_tlu_ctl.scala 960:39] + assign csr_io_nmi_int_detected_f = nmi_int_detected_f; // @[dec_tlu_ctl.scala 961:39] + assign csr_io_internal_dbg_halt_mode_f2 = internal_dbg_halt_mode_f2; // @[dec_tlu_ctl.scala 962:39] + assign csr_io_ext_int_freeze_d1 = ext_int_freeze_d1; // @[dec_tlu_ctl.scala 963:39] + assign csr_io_ic_perr_r_d1 = ic_perr_r_d1; // @[dec_tlu_ctl.scala 964:39] + assign csr_io_iccm_sbecc_r_d1 = iccm_sbecc_r_d1; // @[dec_tlu_ctl.scala 965:39] + assign csr_io_lsu_single_ecc_error_r_d1 = lsu_single_ecc_error_r_d1; // @[dec_tlu_ctl.scala 966:39] + assign csr_io_ifu_miss_state_idle_f = ifu_miss_state_idle_f; // @[dec_tlu_ctl.scala 967:39] + assign csr_io_lsu_idle_any_f = lsu_idle_any_f; // @[dec_tlu_ctl.scala 968:39] + assign csr_io_dbg_tlu_halted_f = dbg_tlu_halted_f; // @[dec_tlu_ctl.scala 969:39] + assign csr_io_dbg_tlu_halted = _T_164 | _T_166; // @[dec_tlu_ctl.scala 970:39] + assign csr_io_debug_halt_req_f = debug_halt_req_f; // @[dec_tlu_ctl.scala 971:51] + assign csr_io_take_ext_int_start = ext_int_ready & _T_704; // @[dec_tlu_ctl.scala 972:47] + assign csr_io_trigger_hit_dmode_r_d1 = trigger_hit_dmode_r_d1; // @[dec_tlu_ctl.scala 973:43] + assign csr_io_trigger_hit_r_d1 = trigger_hit_r_d1; // @[dec_tlu_ctl.scala 974:43] + assign csr_io_dcsr_single_step_done_f = dcsr_single_step_done_f; // @[dec_tlu_ctl.scala 975:43] + assign csr_io_ebreak_to_debug_mode_r_d1 = ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 976:39] + assign csr_io_debug_halt_req = _T_114 & _T_107; // @[dec_tlu_ctl.scala 977:51] + assign csr_io_allow_dbg_halt_csr_write = debug_mode_status & _T_77; // @[dec_tlu_ctl.scala 978:39] + assign csr_io_internal_dbg_halt_mode_f = debug_mode_status; // @[dec_tlu_ctl.scala 979:39] + assign csr_io_enter_debug_halt_req = _T_155 | ebreak_to_debug_mode_r_d1; // @[dec_tlu_ctl.scala 980:39] + assign csr_io_internal_dbg_halt_mode = debug_halt_req_ns | _T_160; // @[dec_tlu_ctl.scala 981:39] + assign csr_io_request_debug_mode_done = _T_183 & _T_136; // @[dec_tlu_ctl.scala 982:39] + assign csr_io_request_debug_mode_r = _T_180 | _T_182; // @[dec_tlu_ctl.scala 983:39] + assign csr_io_update_hit_bit_r = _T_342 & i0_trigger_chain_masked_r; // @[dec_tlu_ctl.scala 984:39] + assign csr_io_take_timer_int = _T_703 & _T_704; // @[dec_tlu_ctl.scala 985:39] + assign csr_io_take_int_timer0_int = _T_717 & _T_704; // @[dec_tlu_ctl.scala 986:39] + assign csr_io_take_int_timer1_int = _T_734 & _T_704; // @[dec_tlu_ctl.scala 987:39] + assign csr_io_take_ext_int = take_ext_int_start_d3 & _T_685; // @[dec_tlu_ctl.scala 988:39] + assign csr_io_tlu_flush_lower_r = _T_801 | take_ext_int_start; // @[dec_tlu_ctl.scala 989:39] + assign csr_io_dec_tlu_br0_error_r = _T_453 & _T_429; // @[dec_tlu_ctl.scala 990:39] + assign csr_io_dec_tlu_br0_start_error_r = _T_455 & _T_429; // @[dec_tlu_ctl.scala 991:39] + assign csr_io_lsu_pmu_load_external_r = lsu_pmu_load_external_r; // @[dec_tlu_ctl.scala 992:39] + assign csr_io_lsu_pmu_store_external_r = lsu_pmu_store_external_r; // @[dec_tlu_ctl.scala 993:39] + assign csr_io_csr_pkt_csr_misa = csr_read_io_csr_pkt_csr_misa; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mvendorid = csr_read_io_csr_pkt_csr_mvendorid; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_marchid = csr_read_io_csr_pkt_csr_marchid; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mimpid = csr_read_io_csr_pkt_csr_mimpid; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mhartid = csr_read_io_csr_pkt_csr_mhartid; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mstatus = csr_read_io_csr_pkt_csr_mstatus; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mtvec = csr_read_io_csr_pkt_csr_mtvec; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mip = csr_read_io_csr_pkt_csr_mip; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mie = csr_read_io_csr_pkt_csr_mie; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mcyclel = csr_read_io_csr_pkt_csr_mcyclel; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mcycleh = csr_read_io_csr_pkt_csr_mcycleh; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_minstretl = csr_read_io_csr_pkt_csr_minstretl; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_minstreth = csr_read_io_csr_pkt_csr_minstreth; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mscratch = csr_read_io_csr_pkt_csr_mscratch; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mepc = csr_read_io_csr_pkt_csr_mepc; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mcause = csr_read_io_csr_pkt_csr_mcause; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mscause = csr_read_io_csr_pkt_csr_mscause; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mtval = csr_read_io_csr_pkt_csr_mtval; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mrac = csr_read_io_csr_pkt_csr_mrac; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mdseac = csr_read_io_csr_pkt_csr_mdseac; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_meihap = csr_read_io_csr_pkt_csr_meihap; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_meivt = csr_read_io_csr_pkt_csr_meivt; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_meipt = csr_read_io_csr_pkt_csr_meipt; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_meicurpl = csr_read_io_csr_pkt_csr_meicurpl; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_meicidpl = csr_read_io_csr_pkt_csr_meicidpl; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_dcsr = csr_read_io_csr_pkt_csr_dcsr; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mcgc = csr_read_io_csr_pkt_csr_mcgc; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mfdc = csr_read_io_csr_pkt_csr_mfdc; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_dpc = csr_read_io_csr_pkt_csr_dpc; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mtsel = csr_read_io_csr_pkt_csr_mtsel; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mtdata1 = csr_read_io_csr_pkt_csr_mtdata1; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mtdata2 = csr_read_io_csr_pkt_csr_mtdata2; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mhpmc3 = csr_read_io_csr_pkt_csr_mhpmc3; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mhpmc4 = csr_read_io_csr_pkt_csr_mhpmc4; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mhpmc5 = csr_read_io_csr_pkt_csr_mhpmc5; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mhpmc6 = csr_read_io_csr_pkt_csr_mhpmc6; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mhpmc3h = csr_read_io_csr_pkt_csr_mhpmc3h; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mhpmc4h = csr_read_io_csr_pkt_csr_mhpmc4h; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mhpmc5h = csr_read_io_csr_pkt_csr_mhpmc5h; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mhpmc6h = csr_read_io_csr_pkt_csr_mhpmc6h; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mhpme3 = csr_read_io_csr_pkt_csr_mhpme3; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mhpme4 = csr_read_io_csr_pkt_csr_mhpme4; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mhpme5 = csr_read_io_csr_pkt_csr_mhpme5; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mhpme6 = csr_read_io_csr_pkt_csr_mhpme6; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mcountinhibit = csr_read_io_csr_pkt_csr_mcountinhibit; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mpmc = csr_read_io_csr_pkt_csr_mpmc; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_micect = csr_read_io_csr_pkt_csr_micect; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_miccmect = csr_read_io_csr_pkt_csr_miccmect; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mdccmect = csr_read_io_csr_pkt_csr_mdccmect; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mfdht = csr_read_io_csr_pkt_csr_mfdht; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_mfdhs = csr_read_io_csr_pkt_csr_mfdhs; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_dicawics = csr_read_io_csr_pkt_csr_dicawics; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_dicad0h = csr_read_io_csr_pkt_csr_dicad0h; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_dicad0 = csr_read_io_csr_pkt_csr_dicad0; // @[dec_tlu_ctl.scala 994:39] + assign csr_io_csr_pkt_csr_dicad1 = csr_read_io_csr_pkt_csr_dicad1; // @[dec_tlu_ctl.scala 994:39] + assign csr_read_io_dec_csr_rdaddr_d = io_dec_csr_rdaddr_d; // @[dec_tlu_ctl.scala 1012:37] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -57826,10 +57819,6 @@ module dec( output io_mpc_debug_run_ack, output io_debug_brkpt_status, input io_lsu_pmu_misaligned_m, - input io_dma_pmu_dccm_read, - input io_dma_pmu_dccm_write, - input io_dma_pmu_any_read, - input io_dma_pmu_any_write, input [30:0] io_lsu_fir_addr, input [1:0] io_lsu_fir_error, input [3:0] io_lsu_trigger_match_m, @@ -57847,18 +57836,10 @@ module dec( input [31:0] io_lsu_result_corr_r, input io_lsu_load_stall_any, input io_lsu_store_stall_any, - input io_dma_dccm_stall_any, - input io_dma_iccm_stall_any, input io_iccm_dma_sb_error, input io_exu_flush_final, - input io_mexintpend, input io_timer_int, input io_soft_int, - input [7:0] io_pic_claimid, - input [3:0] io_pic_pl, - input io_mhwakeup, - output [3:0] io_dec_tlu_meicurpl, - output [3:0] io_dec_tlu_meipt, input io_dbg_halt_req, input io_dbg_resume_req, output io_dec_tlu_dbg_halted, @@ -57913,7 +57894,6 @@ module dec( output [4:0] io_rv_trace_pkt_rv_i_ecause_ip, output [1:0] io_rv_trace_pkt_rv_i_interrupt_ip, output [31:0] io_rv_trace_pkt_rv_i_tval_ip, - output [2:0] io_dec_tlu_dma_qos_prty, output io_dec_tlu_misc_clk_override, output io_dec_tlu_lsu_clk_override, output io_dec_tlu_bus_clk_override, @@ -57971,7 +57951,6 @@ module dec( output io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error, output io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way, output io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle, - output io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb, output io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb, output io_ifu_dec_dec_bp_dec_tlu_bpred_disable, output io_dec_exu_dec_alu_dec_i0_alu_decode_d, @@ -58055,7 +58034,6 @@ module dec( input io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error, input io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy, output io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable, - output io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable, output io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable, input io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any, input io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any, @@ -58074,459 +58052,472 @@ module dec( input io_dec_dbg_dbg_ib_dbg_cmd_write, input [1:0] io_dec_dbg_dbg_ib_dbg_cmd_type, input [31:0] io_dec_dbg_dbg_ib_dbg_cmd_addr, - input [1:0] io_dec_dbg_dbg_dctl_dbg_cmd_wrdata + input [1:0] io_dec_dbg_dbg_dctl_dbg_cmd_wrdata, + input io_dec_dma_dctl_dma_dma_dccm_stall_any, + input io_dec_dma_tlu_dma_dma_pmu_dccm_read, + input io_dec_dma_tlu_dma_dma_pmu_dccm_write, + input io_dec_dma_tlu_dma_dma_pmu_any_read, + input io_dec_dma_tlu_dma_dma_pmu_any_write, + output [2:0] io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty, + input io_dec_dma_tlu_dma_dma_dccm_stall_any, + input io_dec_dma_tlu_dma_dma_iccm_stall_any, + input [7:0] io_dec_pic_pic_claimid, + input [3:0] io_dec_pic_pic_pl, + input io_dec_pic_mhwakeup, + output [3:0] io_dec_pic_dec_tlu_meicurpl, + output [3:0] io_dec_pic_dec_tlu_meipt, + input io_dec_pic_mexintpend ); - wire instbuff_io_ifu_ib_ifu_i0_icaf; // @[dec.scala 126:24] - wire [1:0] instbuff_io_ifu_ib_ifu_i0_icaf_type; // @[dec.scala 126:24] - wire instbuff_io_ifu_ib_ifu_i0_icaf_f1; // @[dec.scala 126:24] - wire instbuff_io_ifu_ib_ifu_i0_dbecc; // @[dec.scala 126:24] - wire [7:0] instbuff_io_ifu_ib_ifu_i0_bp_index; // @[dec.scala 126:24] - wire [7:0] instbuff_io_ifu_ib_ifu_i0_bp_fghr; // @[dec.scala 126:24] - wire [4:0] instbuff_io_ifu_ib_ifu_i0_bp_btag; // @[dec.scala 126:24] - wire instbuff_io_ifu_ib_ifu_i0_valid; // @[dec.scala 126:24] - wire [31:0] instbuff_io_ifu_ib_ifu_i0_instr; // @[dec.scala 126:24] - wire [30:0] instbuff_io_ifu_ib_ifu_i0_pc; // @[dec.scala 126:24] - wire instbuff_io_ifu_ib_ifu_i0_pc4; // @[dec.scala 126:24] - wire instbuff_io_ifu_ib_i0_brp_valid; // @[dec.scala 126:24] - wire [11:0] instbuff_io_ifu_ib_i0_brp_bits_toffset; // @[dec.scala 126:24] - wire [1:0] instbuff_io_ifu_ib_i0_brp_bits_hist; // @[dec.scala 126:24] - wire instbuff_io_ifu_ib_i0_brp_bits_br_error; // @[dec.scala 126:24] - wire instbuff_io_ifu_ib_i0_brp_bits_br_start_error; // @[dec.scala 126:24] - wire [30:0] instbuff_io_ifu_ib_i0_brp_bits_prett; // @[dec.scala 126:24] - wire instbuff_io_ifu_ib_i0_brp_bits_way; // @[dec.scala 126:24] - wire instbuff_io_ifu_ib_i0_brp_bits_ret; // @[dec.scala 126:24] - wire [30:0] instbuff_io_ib_exu_dec_i0_pc_d; // @[dec.scala 126:24] - wire instbuff_io_ib_exu_dec_debug_wdata_rs1_d; // @[dec.scala 126:24] - wire instbuff_io_dbg_ib_dbg_cmd_valid; // @[dec.scala 126:24] - wire instbuff_io_dbg_ib_dbg_cmd_write; // @[dec.scala 126:24] - wire [1:0] instbuff_io_dbg_ib_dbg_cmd_type; // @[dec.scala 126:24] - wire [31:0] instbuff_io_dbg_ib_dbg_cmd_addr; // @[dec.scala 126:24] - wire instbuff_io_dec_ib0_valid_d; // @[dec.scala 126:24] - wire [1:0] instbuff_io_dec_i0_icaf_type_d; // @[dec.scala 126:24] - wire [31:0] instbuff_io_dec_i0_instr_d; // @[dec.scala 126:24] - wire instbuff_io_dec_i0_pc4_d; // @[dec.scala 126:24] - wire instbuff_io_dec_i0_brp_valid; // @[dec.scala 126:24] - wire [11:0] instbuff_io_dec_i0_brp_bits_toffset; // @[dec.scala 126:24] - wire [1:0] instbuff_io_dec_i0_brp_bits_hist; // @[dec.scala 126:24] - wire instbuff_io_dec_i0_brp_bits_br_error; // @[dec.scala 126:24] - wire instbuff_io_dec_i0_brp_bits_br_start_error; // @[dec.scala 126:24] - wire [30:0] instbuff_io_dec_i0_brp_bits_prett; // @[dec.scala 126:24] - wire instbuff_io_dec_i0_brp_bits_way; // @[dec.scala 126:24] - wire instbuff_io_dec_i0_brp_bits_ret; // @[dec.scala 126:24] - wire [7:0] instbuff_io_dec_i0_bp_index; // @[dec.scala 126:24] - wire [7:0] instbuff_io_dec_i0_bp_fghr; // @[dec.scala 126:24] - wire [4:0] instbuff_io_dec_i0_bp_btag; // @[dec.scala 126:24] - wire instbuff_io_dec_i0_icaf_d; // @[dec.scala 126:24] - wire instbuff_io_dec_i0_icaf_f1_d; // @[dec.scala 126:24] - wire instbuff_io_dec_i0_dbecc_d; // @[dec.scala 126:24] - wire instbuff_io_dec_debug_fence_d; // @[dec.scala 126:24] - wire decode_clock; // @[dec.scala 127:22] - wire decode_reset; // @[dec.scala 127:22] - wire [1:0] decode_io_decode_exu_dec_data_en; // @[dec.scala 127:22] - wire [1:0] decode_io_decode_exu_dec_ctl_en; // @[dec.scala 127:22] - wire decode_io_decode_exu_i0_ap_land; // @[dec.scala 127:22] - wire decode_io_decode_exu_i0_ap_lor; // @[dec.scala 127:22] - wire decode_io_decode_exu_i0_ap_lxor; // @[dec.scala 127:22] - wire decode_io_decode_exu_i0_ap_sll; // @[dec.scala 127:22] - wire decode_io_decode_exu_i0_ap_srl; // @[dec.scala 127:22] - wire decode_io_decode_exu_i0_ap_sra; // @[dec.scala 127:22] - wire decode_io_decode_exu_i0_ap_beq; // @[dec.scala 127:22] - wire decode_io_decode_exu_i0_ap_bne; // @[dec.scala 127:22] - wire decode_io_decode_exu_i0_ap_blt; // @[dec.scala 127:22] - wire decode_io_decode_exu_i0_ap_bge; // @[dec.scala 127:22] - wire decode_io_decode_exu_i0_ap_add; // @[dec.scala 127:22] - wire decode_io_decode_exu_i0_ap_sub; // @[dec.scala 127:22] - wire decode_io_decode_exu_i0_ap_slt; // @[dec.scala 127:22] - wire decode_io_decode_exu_i0_ap_unsign; // @[dec.scala 127:22] - wire decode_io_decode_exu_i0_ap_jal; // @[dec.scala 127:22] - wire decode_io_decode_exu_i0_ap_predict_t; // @[dec.scala 127:22] - wire decode_io_decode_exu_i0_ap_predict_nt; // @[dec.scala 127:22] - wire decode_io_decode_exu_i0_ap_csr_write; // @[dec.scala 127:22] - wire decode_io_decode_exu_i0_ap_csr_imm; // @[dec.scala 127:22] - wire decode_io_decode_exu_dec_i0_predict_p_d_valid; // @[dec.scala 127:22] - wire decode_io_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[dec.scala 127:22] - wire [1:0] decode_io_decode_exu_dec_i0_predict_p_d_bits_hist; // @[dec.scala 127:22] - wire [11:0] decode_io_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[dec.scala 127:22] - wire decode_io_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[dec.scala 127:22] - wire decode_io_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[dec.scala 127:22] - wire [30:0] decode_io_decode_exu_dec_i0_predict_p_d_bits_prett; // @[dec.scala 127:22] - wire decode_io_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[dec.scala 127:22] - wire decode_io_decode_exu_dec_i0_predict_p_d_bits_pret; // @[dec.scala 127:22] - wire decode_io_decode_exu_dec_i0_predict_p_d_bits_pja; // @[dec.scala 127:22] - wire decode_io_decode_exu_dec_i0_predict_p_d_bits_way; // @[dec.scala 127:22] - wire [7:0] decode_io_decode_exu_i0_predict_fghr_d; // @[dec.scala 127:22] - wire [7:0] decode_io_decode_exu_i0_predict_index_d; // @[dec.scala 127:22] - wire [4:0] decode_io_decode_exu_i0_predict_btag_d; // @[dec.scala 127:22] - wire decode_io_decode_exu_dec_i0_rs1_en_d; // @[dec.scala 127:22] - wire decode_io_decode_exu_dec_i0_rs2_en_d; // @[dec.scala 127:22] - wire [31:0] decode_io_decode_exu_dec_i0_immed_d; // @[dec.scala 127:22] - wire [31:0] decode_io_decode_exu_dec_i0_rs1_bypass_data_d; // @[dec.scala 127:22] - wire [31:0] decode_io_decode_exu_dec_i0_rs2_bypass_data_d; // @[dec.scala 127:22] - wire decode_io_decode_exu_dec_i0_select_pc_d; // @[dec.scala 127:22] - wire [1:0] decode_io_decode_exu_dec_i0_rs1_bypass_en_d; // @[dec.scala 127:22] - wire [1:0] decode_io_decode_exu_dec_i0_rs2_bypass_en_d; // @[dec.scala 127:22] - wire decode_io_decode_exu_mul_p_valid; // @[dec.scala 127:22] - wire decode_io_decode_exu_mul_p_bits_rs1_sign; // @[dec.scala 127:22] - wire decode_io_decode_exu_mul_p_bits_rs2_sign; // @[dec.scala 127:22] - wire decode_io_decode_exu_mul_p_bits_low; // @[dec.scala 127:22] - wire [30:0] decode_io_decode_exu_pred_correct_npc_x; // @[dec.scala 127:22] - wire decode_io_decode_exu_dec_extint_stall; // @[dec.scala 127:22] - wire [31:0] decode_io_decode_exu_exu_i0_result_x; // @[dec.scala 127:22] - wire [31:0] decode_io_decode_exu_exu_csr_rs1_x; // @[dec.scala 127:22] - wire decode_io_dec_alu_dec_i0_alu_decode_d; // @[dec.scala 127:22] - wire decode_io_dec_alu_dec_csr_ren_d; // @[dec.scala 127:22] - wire [11:0] decode_io_dec_alu_dec_i0_br_immed_d; // @[dec.scala 127:22] - wire [30:0] decode_io_dec_alu_exu_i0_pc_x; // @[dec.scala 127:22] - wire decode_io_dec_div_div_p_valid; // @[dec.scala 127:22] - wire decode_io_dec_div_div_p_bits_unsign; // @[dec.scala 127:22] - wire decode_io_dec_div_div_p_bits_rem; // @[dec.scala 127:22] - wire decode_io_dec_div_dec_div_cancel; // @[dec.scala 127:22] - wire decode_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec.scala 127:22] - wire [1:0] decode_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[dec.scala 127:22] - wire decode_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[dec.scala 127:22] - wire [1:0] decode_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[dec.scala 127:22] - wire decode_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[dec.scala 127:22] - wire decode_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec.scala 127:22] - wire [1:0] decode_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[dec.scala 127:22] - wire [31:0] decode_io_dctl_busbuff_lsu_nonblock_load_data; // @[dec.scala 127:22] - wire decode_io_dec_tlu_flush_extint; // @[dec.scala 127:22] - wire decode_io_dec_tlu_force_halt; // @[dec.scala 127:22] - wire [31:0] decode_io_dec_i0_inst_wb1; // @[dec.scala 127:22] - wire [30:0] decode_io_dec_i0_pc_wb1; // @[dec.scala 127:22] - wire [3:0] decode_io_dec_i0_trigger_match_d; // @[dec.scala 127:22] - wire decode_io_dec_tlu_wr_pause_r; // @[dec.scala 127:22] - wire decode_io_dec_tlu_pipelining_disable; // @[dec.scala 127:22] - wire [3:0] decode_io_lsu_trigger_match_m; // @[dec.scala 127:22] - wire decode_io_lsu_pmu_misaligned_m; // @[dec.scala 127:22] - wire decode_io_dec_tlu_debug_stall; // @[dec.scala 127:22] - wire decode_io_dec_tlu_flush_leak_one_r; // @[dec.scala 127:22] - wire decode_io_dec_debug_fence_d; // @[dec.scala 127:22] - wire decode_io_dec_i0_icaf_d; // @[dec.scala 127:22] - wire decode_io_dec_i0_icaf_f1_d; // @[dec.scala 127:22] - wire [1:0] decode_io_dec_i0_icaf_type_d; // @[dec.scala 127:22] - wire decode_io_dec_i0_dbecc_d; // @[dec.scala 127:22] - wire decode_io_dec_i0_brp_valid; // @[dec.scala 127:22] - wire [11:0] decode_io_dec_i0_brp_bits_toffset; // @[dec.scala 127:22] - wire [1:0] decode_io_dec_i0_brp_bits_hist; // @[dec.scala 127:22] - wire decode_io_dec_i0_brp_bits_br_error; // @[dec.scala 127:22] - wire decode_io_dec_i0_brp_bits_br_start_error; // @[dec.scala 127:22] - wire [30:0] decode_io_dec_i0_brp_bits_prett; // @[dec.scala 127:22] - wire decode_io_dec_i0_brp_bits_way; // @[dec.scala 127:22] - wire decode_io_dec_i0_brp_bits_ret; // @[dec.scala 127:22] - wire [7:0] decode_io_dec_i0_bp_index; // @[dec.scala 127:22] - wire [7:0] decode_io_dec_i0_bp_fghr; // @[dec.scala 127:22] - wire [4:0] decode_io_dec_i0_bp_btag; // @[dec.scala 127:22] - wire decode_io_lsu_idle_any; // @[dec.scala 127:22] - wire decode_io_lsu_load_stall_any; // @[dec.scala 127:22] - wire decode_io_lsu_store_stall_any; // @[dec.scala 127:22] - wire decode_io_dma_dccm_stall_any; // @[dec.scala 127:22] - wire decode_io_exu_div_wren; // @[dec.scala 127:22] - wire decode_io_dec_tlu_i0_kill_writeb_wb; // @[dec.scala 127:22] - wire decode_io_dec_tlu_flush_lower_wb; // @[dec.scala 127:22] - wire decode_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 127:22] - wire decode_io_dec_tlu_flush_lower_r; // @[dec.scala 127:22] - wire decode_io_dec_tlu_flush_pause_r; // @[dec.scala 127:22] - wire decode_io_dec_tlu_presync_d; // @[dec.scala 127:22] - wire decode_io_dec_tlu_postsync_d; // @[dec.scala 127:22] - wire decode_io_dec_i0_pc4_d; // @[dec.scala 127:22] - wire [31:0] decode_io_dec_csr_rddata_d; // @[dec.scala 127:22] - wire decode_io_dec_csr_legal_d; // @[dec.scala 127:22] - wire [31:0] decode_io_lsu_result_m; // @[dec.scala 127:22] - wire [31:0] decode_io_lsu_result_corr_r; // @[dec.scala 127:22] - wire decode_io_exu_flush_final; // @[dec.scala 127:22] - wire [31:0] decode_io_dec_i0_instr_d; // @[dec.scala 127:22] - wire decode_io_dec_ib0_valid_d; // @[dec.scala 127:22] - wire decode_io_free_clk; // @[dec.scala 127:22] - wire decode_io_active_clk; // @[dec.scala 127:22] - wire decode_io_clk_override; // @[dec.scala 127:22] - wire [4:0] decode_io_dec_i0_rs1_d; // @[dec.scala 127:22] - wire [4:0] decode_io_dec_i0_rs2_d; // @[dec.scala 127:22] - wire [4:0] decode_io_dec_i0_waddr_r; // @[dec.scala 127:22] - wire decode_io_dec_i0_wen_r; // @[dec.scala 127:22] - wire [31:0] decode_io_dec_i0_wdata_r; // @[dec.scala 127:22] - wire decode_io_lsu_p_valid; // @[dec.scala 127:22] - wire decode_io_lsu_p_bits_fast_int; // @[dec.scala 127:22] - wire decode_io_lsu_p_bits_by; // @[dec.scala 127:22] - wire decode_io_lsu_p_bits_half; // @[dec.scala 127:22] - wire decode_io_lsu_p_bits_word; // @[dec.scala 127:22] - wire decode_io_lsu_p_bits_load; // @[dec.scala 127:22] - wire decode_io_lsu_p_bits_store; // @[dec.scala 127:22] - wire decode_io_lsu_p_bits_unsign; // @[dec.scala 127:22] - wire decode_io_lsu_p_bits_store_data_bypass_d; // @[dec.scala 127:22] - wire decode_io_lsu_p_bits_load_ldst_bypass_d; // @[dec.scala 127:22] - wire [4:0] decode_io_div_waddr_wb; // @[dec.scala 127:22] - wire decode_io_dec_lsu_valid_raw_d; // @[dec.scala 127:22] - wire [11:0] decode_io_dec_lsu_offset_d; // @[dec.scala 127:22] - wire decode_io_dec_csr_wen_unq_d; // @[dec.scala 127:22] - wire decode_io_dec_csr_any_unq_d; // @[dec.scala 127:22] - wire [11:0] decode_io_dec_csr_rdaddr_d; // @[dec.scala 127:22] - wire decode_io_dec_csr_wen_r; // @[dec.scala 127:22] - wire [11:0] decode_io_dec_csr_wraddr_r; // @[dec.scala 127:22] - wire [31:0] decode_io_dec_csr_wrdata_r; // @[dec.scala 127:22] - wire decode_io_dec_csr_stall_int_ff; // @[dec.scala 127:22] - wire decode_io_dec_tlu_i0_valid_r; // @[dec.scala 127:22] - wire decode_io_dec_tlu_packet_r_legal; // @[dec.scala 127:22] - wire decode_io_dec_tlu_packet_r_icaf; // @[dec.scala 127:22] - wire decode_io_dec_tlu_packet_r_icaf_f1; // @[dec.scala 127:22] - wire [1:0] decode_io_dec_tlu_packet_r_icaf_type; // @[dec.scala 127:22] - wire decode_io_dec_tlu_packet_r_fence_i; // @[dec.scala 127:22] - wire [3:0] decode_io_dec_tlu_packet_r_i0trigger; // @[dec.scala 127:22] - wire [3:0] decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec.scala 127:22] - wire decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec.scala 127:22] - wire decode_io_dec_tlu_packet_r_pmu_divide; // @[dec.scala 127:22] - wire decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec.scala 127:22] - wire [30:0] decode_io_dec_tlu_i0_pc_r; // @[dec.scala 127:22] - wire [31:0] decode_io_dec_illegal_inst; // @[dec.scala 127:22] - wire decode_io_dec_pmu_instr_decoded; // @[dec.scala 127:22] - wire decode_io_dec_pmu_decode_stall; // @[dec.scala 127:22] - wire decode_io_dec_pmu_presync_stall; // @[dec.scala 127:22] - wire decode_io_dec_pmu_postsync_stall; // @[dec.scala 127:22] - wire decode_io_dec_nonblock_load_wen; // @[dec.scala 127:22] - wire [4:0] decode_io_dec_nonblock_load_waddr; // @[dec.scala 127:22] - wire decode_io_dec_pause_state; // @[dec.scala 127:22] - wire decode_io_dec_pause_state_cg; // @[dec.scala 127:22] - wire decode_io_dec_div_active; // @[dec.scala 127:22] - wire decode_io_scan_mode; // @[dec.scala 127:22] - wire decode_io_dec_aln_dec_i0_decode_d; // @[dec.scala 127:22] - wire [15:0] decode_io_dec_aln_ifu_i0_cinst; // @[dec.scala 127:22] - wire [1:0] decode_io_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 127:22] - wire gpr_clock; // @[dec.scala 128:19] - wire gpr_reset; // @[dec.scala 128:19] - wire [4:0] gpr_io_raddr0; // @[dec.scala 128:19] - wire [4:0] gpr_io_raddr1; // @[dec.scala 128:19] - wire gpr_io_wen0; // @[dec.scala 128:19] - wire [4:0] gpr_io_waddr0; // @[dec.scala 128:19] - wire [31:0] gpr_io_wd0; // @[dec.scala 128:19] - wire gpr_io_wen1; // @[dec.scala 128:19] - wire [4:0] gpr_io_waddr1; // @[dec.scala 128:19] - wire [31:0] gpr_io_wd1; // @[dec.scala 128:19] - wire gpr_io_wen2; // @[dec.scala 128:19] - wire [4:0] gpr_io_waddr2; // @[dec.scala 128:19] - wire [31:0] gpr_io_wd2; // @[dec.scala 128:19] - wire gpr_io_scan_mode; // @[dec.scala 128:19] - wire [31:0] gpr_io_gpr_exu_gpr_i0_rs1_d; // @[dec.scala 128:19] - wire [31:0] gpr_io_gpr_exu_gpr_i0_rs2_d; // @[dec.scala 128:19] - wire tlu_clock; // @[dec.scala 129:19] - wire tlu_reset; // @[dec.scala 129:19] - wire [29:0] tlu_io_tlu_exu_dec_tlu_meihap; // @[dec.scala 129:19] - wire tlu_io_tlu_exu_dec_tlu_flush_lower_r; // @[dec.scala 129:19] - wire [30:0] tlu_io_tlu_exu_dec_tlu_flush_path_r; // @[dec.scala 129:19] - wire [1:0] tlu_io_tlu_exu_exu_i0_br_hist_r; // @[dec.scala 129:19] - wire tlu_io_tlu_exu_exu_i0_br_error_r; // @[dec.scala 129:19] - wire tlu_io_tlu_exu_exu_i0_br_start_error_r; // @[dec.scala 129:19] - wire tlu_io_tlu_exu_exu_i0_br_valid_r; // @[dec.scala 129:19] - wire tlu_io_tlu_exu_exu_i0_br_mp_r; // @[dec.scala 129:19] - wire tlu_io_tlu_exu_exu_i0_br_middle_r; // @[dec.scala 129:19] - wire tlu_io_tlu_exu_exu_pmu_i0_br_misp; // @[dec.scala 129:19] - wire tlu_io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec.scala 129:19] - wire tlu_io_tlu_exu_exu_pmu_i0_pc4; // @[dec.scala 129:19] - wire [30:0] tlu_io_tlu_exu_exu_npc_r; // @[dec.scala 129:19] - wire tlu_io_active_clk; // @[dec.scala 129:19] - wire tlu_io_free_clk; // @[dec.scala 129:19] - wire tlu_io_scan_mode; // @[dec.scala 129:19] - wire [30:0] tlu_io_rst_vec; // @[dec.scala 129:19] - wire tlu_io_nmi_int; // @[dec.scala 129:19] - wire [30:0] tlu_io_nmi_vec; // @[dec.scala 129:19] - wire tlu_io_i_cpu_halt_req; // @[dec.scala 129:19] - wire tlu_io_i_cpu_run_req; // @[dec.scala 129:19] - wire tlu_io_lsu_fastint_stall_any; // @[dec.scala 129:19] - wire tlu_io_lsu_idle_any; // @[dec.scala 129:19] - wire tlu_io_dec_pmu_instr_decoded; // @[dec.scala 129:19] - wire tlu_io_dec_pmu_decode_stall; // @[dec.scala 129:19] - wire tlu_io_dec_pmu_presync_stall; // @[dec.scala 129:19] - wire tlu_io_dec_pmu_postsync_stall; // @[dec.scala 129:19] - wire tlu_io_lsu_store_stall_any; // @[dec.scala 129:19] - wire tlu_io_dma_dccm_stall_any; // @[dec.scala 129:19] - wire tlu_io_dma_iccm_stall_any; // @[dec.scala 129:19] - wire tlu_io_dma_pmu_dccm_read; // @[dec.scala 129:19] - wire tlu_io_dma_pmu_dccm_write; // @[dec.scala 129:19] - wire tlu_io_dma_pmu_any_read; // @[dec.scala 129:19] - wire tlu_io_dma_pmu_any_write; // @[dec.scala 129:19] - wire [30:0] tlu_io_lsu_fir_addr; // @[dec.scala 129:19] - wire [1:0] tlu_io_lsu_fir_error; // @[dec.scala 129:19] - wire tlu_io_iccm_dma_sb_error; // @[dec.scala 129:19] - wire tlu_io_lsu_error_pkt_r_valid; // @[dec.scala 129:19] - wire tlu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec.scala 129:19] - wire tlu_io_lsu_error_pkt_r_bits_inst_type; // @[dec.scala 129:19] - wire tlu_io_lsu_error_pkt_r_bits_exc_type; // @[dec.scala 129:19] - wire [3:0] tlu_io_lsu_error_pkt_r_bits_mscause; // @[dec.scala 129:19] - wire [31:0] tlu_io_lsu_error_pkt_r_bits_addr; // @[dec.scala 129:19] - wire tlu_io_lsu_single_ecc_error_incr; // @[dec.scala 129:19] - wire tlu_io_dec_pause_state; // @[dec.scala 129:19] - wire tlu_io_dec_csr_wen_unq_d; // @[dec.scala 129:19] - wire tlu_io_dec_csr_any_unq_d; // @[dec.scala 129:19] - wire [11:0] tlu_io_dec_csr_rdaddr_d; // @[dec.scala 129:19] - wire tlu_io_dec_csr_wen_r; // @[dec.scala 129:19] - wire [11:0] tlu_io_dec_csr_wraddr_r; // @[dec.scala 129:19] - wire [31:0] tlu_io_dec_csr_wrdata_r; // @[dec.scala 129:19] - wire tlu_io_dec_csr_stall_int_ff; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_i0_valid_r; // @[dec.scala 129:19] - wire [30:0] tlu_io_dec_tlu_i0_pc_r; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_packet_r_legal; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_packet_r_icaf; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_packet_r_icaf_f1; // @[dec.scala 129:19] - wire [1:0] tlu_io_dec_tlu_packet_r_icaf_type; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_packet_r_fence_i; // @[dec.scala 129:19] - wire [3:0] tlu_io_dec_tlu_packet_r_i0trigger; // @[dec.scala 129:19] - wire [3:0] tlu_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_packet_r_pmu_divide; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec.scala 129:19] - wire [31:0] tlu_io_dec_illegal_inst; // @[dec.scala 129:19] - wire tlu_io_dec_i0_decode_d; // @[dec.scala 129:19] - wire tlu_io_exu_i0_br_way_r; // @[dec.scala 129:19] - wire tlu_io_dec_dbg_cmd_done; // @[dec.scala 129:19] - wire tlu_io_dec_dbg_cmd_fail; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_dbg_halted; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_debug_mode; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_resume_ack; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_debug_stall; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_mpc_halted_only; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_flush_extint; // @[dec.scala 129:19] - wire tlu_io_dbg_halt_req; // @[dec.scala 129:19] - wire tlu_io_dbg_resume_req; // @[dec.scala 129:19] - wire tlu_io_dec_div_active; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_0_select; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_0_store; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_0_load; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_0_execute; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_0_m; // @[dec.scala 129:19] - wire [31:0] tlu_io_trigger_pkt_any_0_tdata2; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_1_select; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_1_store; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_1_load; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_1_execute; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_1_m; // @[dec.scala 129:19] - wire [31:0] tlu_io_trigger_pkt_any_1_tdata2; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_2_select; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_2_store; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_2_load; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_2_execute; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_2_m; // @[dec.scala 129:19] - wire [31:0] tlu_io_trigger_pkt_any_2_tdata2; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_3_select; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_3_store; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_3_load; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_3_execute; // @[dec.scala 129:19] - wire tlu_io_trigger_pkt_any_3_m; // @[dec.scala 129:19] - wire [31:0] tlu_io_trigger_pkt_any_3_tdata2; // @[dec.scala 129:19] - wire [7:0] tlu_io_pic_claimid; // @[dec.scala 129:19] - wire [3:0] tlu_io_pic_pl; // @[dec.scala 129:19] - wire tlu_io_mhwakeup; // @[dec.scala 129:19] - wire tlu_io_mexintpend; // @[dec.scala 129:19] - wire tlu_io_timer_int; // @[dec.scala 129:19] - wire tlu_io_soft_int; // @[dec.scala 129:19] - wire tlu_io_o_cpu_halt_status; // @[dec.scala 129:19] - wire tlu_io_o_cpu_halt_ack; // @[dec.scala 129:19] - wire tlu_io_o_cpu_run_ack; // @[dec.scala 129:19] - wire tlu_io_o_debug_mode_status; // @[dec.scala 129:19] - wire [27:0] tlu_io_core_id; // @[dec.scala 129:19] - wire tlu_io_mpc_debug_halt_req; // @[dec.scala 129:19] - wire tlu_io_mpc_debug_run_req; // @[dec.scala 129:19] - wire tlu_io_mpc_reset_run_req; // @[dec.scala 129:19] - wire tlu_io_mpc_debug_halt_ack; // @[dec.scala 129:19] - wire tlu_io_mpc_debug_run_ack; // @[dec.scala 129:19] - wire tlu_io_debug_brkpt_status; // @[dec.scala 129:19] - wire [3:0] tlu_io_dec_tlu_meicurpl; // @[dec.scala 129:19] - wire [3:0] tlu_io_dec_tlu_meipt; // @[dec.scala 129:19] - wire [31:0] tlu_io_dec_csr_rddata_d; // @[dec.scala 129:19] - wire tlu_io_dec_csr_legal_d; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_i0_kill_writeb_wb; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_wr_pause_r; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_flush_pause_r; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_presync_d; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_postsync_d; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_perfcnt0; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_perfcnt1; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_perfcnt2; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_perfcnt3; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_i0_exc_valid_wb1; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_i0_valid_wb1; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_int_valid_wb1; // @[dec.scala 129:19] - wire [4:0] tlu_io_dec_tlu_exc_cause_wb1; // @[dec.scala 129:19] - wire [31:0] tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_pipelining_disable; // @[dec.scala 129:19] - wire [2:0] tlu_io_dec_tlu_dma_qos_prty; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 129:19] - wire tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 129:19] - wire tlu_io_ifu_pmu_instr_aligned; // @[dec.scala 129:19] - wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_valid; // @[dec.scala 129:19] - wire [1:0] tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist; // @[dec.scala 129:19] - wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[dec.scala 129:19] - wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[dec.scala 129:19] - wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_way; // @[dec.scala 129:19] - wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle; // @[dec.scala 129:19] - wire tlu_io_tlu_bp_dec_tlu_flush_lower_wb; // @[dec.scala 129:19] - wire tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb; // @[dec.scala 129:19] - wire tlu_io_tlu_bp_dec_tlu_bpred_disable; // @[dec.scala 129:19] - wire tlu_io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec.scala 129:19] - wire [31:0] tlu_io_tlu_ifc_dec_tlu_mrac_ff; // @[dec.scala 129:19] - wire tlu_io_tlu_ifc_ifu_pmu_fetch_stall; // @[dec.scala 129:19] - wire tlu_io_tlu_mem_dec_tlu_flush_err_wb; // @[dec.scala 129:19] - wire tlu_io_tlu_mem_dec_tlu_i0_commit_cmt; // @[dec.scala 129:19] - wire tlu_io_tlu_mem_dec_tlu_force_halt; // @[dec.scala 129:19] - wire tlu_io_tlu_mem_dec_tlu_fence_i_wb; // @[dec.scala 129:19] - wire [70:0] tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec.scala 129:19] - wire [16:0] tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec.scala 129:19] - wire tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec.scala 129:19] - wire tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec.scala 129:19] - wire tlu_io_tlu_mem_dec_tlu_core_ecc_disable; // @[dec.scala 129:19] - wire tlu_io_tlu_mem_ifu_pmu_ic_miss; // @[dec.scala 129:19] - wire tlu_io_tlu_mem_ifu_pmu_ic_hit; // @[dec.scala 129:19] - wire tlu_io_tlu_mem_ifu_pmu_bus_error; // @[dec.scala 129:19] - wire tlu_io_tlu_mem_ifu_pmu_bus_busy; // @[dec.scala 129:19] - wire tlu_io_tlu_mem_ifu_pmu_bus_trxn; // @[dec.scala 129:19] - wire tlu_io_tlu_mem_ifu_ic_error_start; // @[dec.scala 129:19] - wire tlu_io_tlu_mem_ifu_iccm_rd_ecc_single_err; // @[dec.scala 129:19] - wire [70:0] tlu_io_tlu_mem_ifu_ic_debug_rd_data; // @[dec.scala 129:19] - wire tlu_io_tlu_mem_ifu_ic_debug_rd_data_valid; // @[dec.scala 129:19] - wire tlu_io_tlu_mem_ifu_miss_state_idle; // @[dec.scala 129:19] - wire tlu_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec.scala 129:19] - wire tlu_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec.scala 129:19] - wire tlu_io_tlu_busbuff_lsu_pmu_bus_error; // @[dec.scala 129:19] - wire tlu_io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec.scala 129:19] - wire tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 129:19] - wire tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 129:19] - wire tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 129:19] - wire tlu_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec.scala 129:19] - wire tlu_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec.scala 129:19] - wire [31:0] tlu_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec.scala 129:19] - wire tlu_io_lsu_tlu_lsu_pmu_load_external_m; // @[dec.scala 129:19] - wire tlu_io_lsu_tlu_lsu_pmu_store_external_m; // @[dec.scala 129:19] - wire dec_trigger_io_trigger_pkt_any_0_select; // @[dec.scala 130:27] - wire dec_trigger_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 130:27] - wire dec_trigger_io_trigger_pkt_any_0_execute; // @[dec.scala 130:27] - wire dec_trigger_io_trigger_pkt_any_0_m; // @[dec.scala 130:27] - wire [31:0] dec_trigger_io_trigger_pkt_any_0_tdata2; // @[dec.scala 130:27] - wire dec_trigger_io_trigger_pkt_any_1_select; // @[dec.scala 130:27] - wire dec_trigger_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 130:27] - wire dec_trigger_io_trigger_pkt_any_1_execute; // @[dec.scala 130:27] - wire dec_trigger_io_trigger_pkt_any_1_m; // @[dec.scala 130:27] - wire [31:0] dec_trigger_io_trigger_pkt_any_1_tdata2; // @[dec.scala 130:27] - wire dec_trigger_io_trigger_pkt_any_2_select; // @[dec.scala 130:27] - wire dec_trigger_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 130:27] - wire dec_trigger_io_trigger_pkt_any_2_execute; // @[dec.scala 130:27] - wire dec_trigger_io_trigger_pkt_any_2_m; // @[dec.scala 130:27] - wire [31:0] dec_trigger_io_trigger_pkt_any_2_tdata2; // @[dec.scala 130:27] - wire dec_trigger_io_trigger_pkt_any_3_select; // @[dec.scala 130:27] - wire dec_trigger_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 130:27] - wire dec_trigger_io_trigger_pkt_any_3_execute; // @[dec.scala 130:27] - wire dec_trigger_io_trigger_pkt_any_3_m; // @[dec.scala 130:27] - wire [31:0] dec_trigger_io_trigger_pkt_any_3_tdata2; // @[dec.scala 130:27] - wire [30:0] dec_trigger_io_dec_i0_pc_d; // @[dec.scala 130:27] - wire [3:0] dec_trigger_io_dec_i0_trigger_match_d; // @[dec.scala 130:27] - wire _T_1 = tlu_io_dec_tlu_i0_valid_wb1 | tlu_io_dec_tlu_i0_exc_valid_wb1; // @[dec.scala 309:98] - dec_ib_ctl instbuff ( // @[dec.scala 126:24] + wire instbuff_io_ifu_ib_ifu_i0_icaf; // @[dec.scala 117:24] + wire [1:0] instbuff_io_ifu_ib_ifu_i0_icaf_type; // @[dec.scala 117:24] + wire instbuff_io_ifu_ib_ifu_i0_icaf_f1; // @[dec.scala 117:24] + wire instbuff_io_ifu_ib_ifu_i0_dbecc; // @[dec.scala 117:24] + wire [7:0] instbuff_io_ifu_ib_ifu_i0_bp_index; // @[dec.scala 117:24] + wire [7:0] instbuff_io_ifu_ib_ifu_i0_bp_fghr; // @[dec.scala 117:24] + wire [4:0] instbuff_io_ifu_ib_ifu_i0_bp_btag; // @[dec.scala 117:24] + wire instbuff_io_ifu_ib_ifu_i0_valid; // @[dec.scala 117:24] + wire [31:0] instbuff_io_ifu_ib_ifu_i0_instr; // @[dec.scala 117:24] + wire [30:0] instbuff_io_ifu_ib_ifu_i0_pc; // @[dec.scala 117:24] + wire instbuff_io_ifu_ib_ifu_i0_pc4; // @[dec.scala 117:24] + wire instbuff_io_ifu_ib_i0_brp_valid; // @[dec.scala 117:24] + wire [11:0] instbuff_io_ifu_ib_i0_brp_bits_toffset; // @[dec.scala 117:24] + wire [1:0] instbuff_io_ifu_ib_i0_brp_bits_hist; // @[dec.scala 117:24] + wire instbuff_io_ifu_ib_i0_brp_bits_br_error; // @[dec.scala 117:24] + wire instbuff_io_ifu_ib_i0_brp_bits_br_start_error; // @[dec.scala 117:24] + wire [30:0] instbuff_io_ifu_ib_i0_brp_bits_prett; // @[dec.scala 117:24] + wire instbuff_io_ifu_ib_i0_brp_bits_way; // @[dec.scala 117:24] + wire instbuff_io_ifu_ib_i0_brp_bits_ret; // @[dec.scala 117:24] + wire [30:0] instbuff_io_ib_exu_dec_i0_pc_d; // @[dec.scala 117:24] + wire instbuff_io_ib_exu_dec_debug_wdata_rs1_d; // @[dec.scala 117:24] + wire instbuff_io_dbg_ib_dbg_cmd_valid; // @[dec.scala 117:24] + wire instbuff_io_dbg_ib_dbg_cmd_write; // @[dec.scala 117:24] + wire [1:0] instbuff_io_dbg_ib_dbg_cmd_type; // @[dec.scala 117:24] + wire [31:0] instbuff_io_dbg_ib_dbg_cmd_addr; // @[dec.scala 117:24] + wire instbuff_io_dec_ib0_valid_d; // @[dec.scala 117:24] + wire [1:0] instbuff_io_dec_i0_icaf_type_d; // @[dec.scala 117:24] + wire [31:0] instbuff_io_dec_i0_instr_d; // @[dec.scala 117:24] + wire instbuff_io_dec_i0_pc4_d; // @[dec.scala 117:24] + wire instbuff_io_dec_i0_brp_valid; // @[dec.scala 117:24] + wire [11:0] instbuff_io_dec_i0_brp_bits_toffset; // @[dec.scala 117:24] + wire [1:0] instbuff_io_dec_i0_brp_bits_hist; // @[dec.scala 117:24] + wire instbuff_io_dec_i0_brp_bits_br_error; // @[dec.scala 117:24] + wire instbuff_io_dec_i0_brp_bits_br_start_error; // @[dec.scala 117:24] + wire [30:0] instbuff_io_dec_i0_brp_bits_prett; // @[dec.scala 117:24] + wire instbuff_io_dec_i0_brp_bits_way; // @[dec.scala 117:24] + wire instbuff_io_dec_i0_brp_bits_ret; // @[dec.scala 117:24] + wire [7:0] instbuff_io_dec_i0_bp_index; // @[dec.scala 117:24] + wire [7:0] instbuff_io_dec_i0_bp_fghr; // @[dec.scala 117:24] + wire [4:0] instbuff_io_dec_i0_bp_btag; // @[dec.scala 117:24] + wire instbuff_io_dec_i0_icaf_d; // @[dec.scala 117:24] + wire instbuff_io_dec_i0_icaf_f1_d; // @[dec.scala 117:24] + wire instbuff_io_dec_i0_dbecc_d; // @[dec.scala 117:24] + wire instbuff_io_dec_debug_fence_d; // @[dec.scala 117:24] + wire decode_clock; // @[dec.scala 118:22] + wire decode_reset; // @[dec.scala 118:22] + wire [1:0] decode_io_decode_exu_dec_data_en; // @[dec.scala 118:22] + wire [1:0] decode_io_decode_exu_dec_ctl_en; // @[dec.scala 118:22] + wire decode_io_decode_exu_i0_ap_land; // @[dec.scala 118:22] + wire decode_io_decode_exu_i0_ap_lor; // @[dec.scala 118:22] + wire decode_io_decode_exu_i0_ap_lxor; // @[dec.scala 118:22] + wire decode_io_decode_exu_i0_ap_sll; // @[dec.scala 118:22] + wire decode_io_decode_exu_i0_ap_srl; // @[dec.scala 118:22] + wire decode_io_decode_exu_i0_ap_sra; // @[dec.scala 118:22] + wire decode_io_decode_exu_i0_ap_beq; // @[dec.scala 118:22] + wire decode_io_decode_exu_i0_ap_bne; // @[dec.scala 118:22] + wire decode_io_decode_exu_i0_ap_blt; // @[dec.scala 118:22] + wire decode_io_decode_exu_i0_ap_bge; // @[dec.scala 118:22] + wire decode_io_decode_exu_i0_ap_add; // @[dec.scala 118:22] + wire decode_io_decode_exu_i0_ap_sub; // @[dec.scala 118:22] + wire decode_io_decode_exu_i0_ap_slt; // @[dec.scala 118:22] + wire decode_io_decode_exu_i0_ap_unsign; // @[dec.scala 118:22] + wire decode_io_decode_exu_i0_ap_jal; // @[dec.scala 118:22] + wire decode_io_decode_exu_i0_ap_predict_t; // @[dec.scala 118:22] + wire decode_io_decode_exu_i0_ap_predict_nt; // @[dec.scala 118:22] + wire decode_io_decode_exu_i0_ap_csr_write; // @[dec.scala 118:22] + wire decode_io_decode_exu_i0_ap_csr_imm; // @[dec.scala 118:22] + wire decode_io_decode_exu_dec_i0_predict_p_d_valid; // @[dec.scala 118:22] + wire decode_io_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[dec.scala 118:22] + wire [1:0] decode_io_decode_exu_dec_i0_predict_p_d_bits_hist; // @[dec.scala 118:22] + wire [11:0] decode_io_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[dec.scala 118:22] + wire decode_io_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[dec.scala 118:22] + wire decode_io_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[dec.scala 118:22] + wire [30:0] decode_io_decode_exu_dec_i0_predict_p_d_bits_prett; // @[dec.scala 118:22] + wire decode_io_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[dec.scala 118:22] + wire decode_io_decode_exu_dec_i0_predict_p_d_bits_pret; // @[dec.scala 118:22] + wire decode_io_decode_exu_dec_i0_predict_p_d_bits_pja; // @[dec.scala 118:22] + wire decode_io_decode_exu_dec_i0_predict_p_d_bits_way; // @[dec.scala 118:22] + wire [7:0] decode_io_decode_exu_i0_predict_fghr_d; // @[dec.scala 118:22] + wire [7:0] decode_io_decode_exu_i0_predict_index_d; // @[dec.scala 118:22] + wire [4:0] decode_io_decode_exu_i0_predict_btag_d; // @[dec.scala 118:22] + wire decode_io_decode_exu_dec_i0_rs1_en_d; // @[dec.scala 118:22] + wire decode_io_decode_exu_dec_i0_rs2_en_d; // @[dec.scala 118:22] + wire [31:0] decode_io_decode_exu_dec_i0_immed_d; // @[dec.scala 118:22] + wire [31:0] decode_io_decode_exu_dec_i0_rs1_bypass_data_d; // @[dec.scala 118:22] + wire [31:0] decode_io_decode_exu_dec_i0_rs2_bypass_data_d; // @[dec.scala 118:22] + wire decode_io_decode_exu_dec_i0_select_pc_d; // @[dec.scala 118:22] + wire [1:0] decode_io_decode_exu_dec_i0_rs1_bypass_en_d; // @[dec.scala 118:22] + wire [1:0] decode_io_decode_exu_dec_i0_rs2_bypass_en_d; // @[dec.scala 118:22] + wire decode_io_decode_exu_mul_p_valid; // @[dec.scala 118:22] + wire decode_io_decode_exu_mul_p_bits_rs1_sign; // @[dec.scala 118:22] + wire decode_io_decode_exu_mul_p_bits_rs2_sign; // @[dec.scala 118:22] + wire decode_io_decode_exu_mul_p_bits_low; // @[dec.scala 118:22] + wire [30:0] decode_io_decode_exu_pred_correct_npc_x; // @[dec.scala 118:22] + wire decode_io_decode_exu_dec_extint_stall; // @[dec.scala 118:22] + wire [31:0] decode_io_decode_exu_exu_i0_result_x; // @[dec.scala 118:22] + wire [31:0] decode_io_decode_exu_exu_csr_rs1_x; // @[dec.scala 118:22] + wire decode_io_dec_alu_dec_i0_alu_decode_d; // @[dec.scala 118:22] + wire decode_io_dec_alu_dec_csr_ren_d; // @[dec.scala 118:22] + wire [11:0] decode_io_dec_alu_dec_i0_br_immed_d; // @[dec.scala 118:22] + wire [30:0] decode_io_dec_alu_exu_i0_pc_x; // @[dec.scala 118:22] + wire decode_io_dec_div_div_p_valid; // @[dec.scala 118:22] + wire decode_io_dec_div_div_p_bits_unsign; // @[dec.scala 118:22] + wire decode_io_dec_div_div_p_bits_rem; // @[dec.scala 118:22] + wire decode_io_dec_div_dec_div_cancel; // @[dec.scala 118:22] + wire decode_io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec.scala 118:22] + wire [1:0] decode_io_dctl_busbuff_lsu_nonblock_load_tag_m; // @[dec.scala 118:22] + wire decode_io_dctl_busbuff_lsu_nonblock_load_inv_r; // @[dec.scala 118:22] + wire [1:0] decode_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[dec.scala 118:22] + wire decode_io_dctl_busbuff_lsu_nonblock_load_data_valid; // @[dec.scala 118:22] + wire decode_io_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec.scala 118:22] + wire [1:0] decode_io_dctl_busbuff_lsu_nonblock_load_data_tag; // @[dec.scala 118:22] + wire [31:0] decode_io_dctl_busbuff_lsu_nonblock_load_data; // @[dec.scala 118:22] + wire decode_io_dctl_dma_dma_dccm_stall_any; // @[dec.scala 118:22] + wire decode_io_dec_tlu_flush_extint; // @[dec.scala 118:22] + wire decode_io_dec_tlu_force_halt; // @[dec.scala 118:22] + wire [31:0] decode_io_dec_i0_inst_wb1; // @[dec.scala 118:22] + wire [30:0] decode_io_dec_i0_pc_wb1; // @[dec.scala 118:22] + wire [3:0] decode_io_dec_i0_trigger_match_d; // @[dec.scala 118:22] + wire decode_io_dec_tlu_wr_pause_r; // @[dec.scala 118:22] + wire decode_io_dec_tlu_pipelining_disable; // @[dec.scala 118:22] + wire [3:0] decode_io_lsu_trigger_match_m; // @[dec.scala 118:22] + wire decode_io_lsu_pmu_misaligned_m; // @[dec.scala 118:22] + wire decode_io_dec_tlu_debug_stall; // @[dec.scala 118:22] + wire decode_io_dec_tlu_flush_leak_one_r; // @[dec.scala 118:22] + wire decode_io_dec_debug_fence_d; // @[dec.scala 118:22] + wire decode_io_dec_i0_icaf_d; // @[dec.scala 118:22] + wire decode_io_dec_i0_icaf_f1_d; // @[dec.scala 118:22] + wire [1:0] decode_io_dec_i0_icaf_type_d; // @[dec.scala 118:22] + wire decode_io_dec_i0_dbecc_d; // @[dec.scala 118:22] + wire decode_io_dec_i0_brp_valid; // @[dec.scala 118:22] + wire [11:0] decode_io_dec_i0_brp_bits_toffset; // @[dec.scala 118:22] + wire [1:0] decode_io_dec_i0_brp_bits_hist; // @[dec.scala 118:22] + wire decode_io_dec_i0_brp_bits_br_error; // @[dec.scala 118:22] + wire decode_io_dec_i0_brp_bits_br_start_error; // @[dec.scala 118:22] + wire [30:0] decode_io_dec_i0_brp_bits_prett; // @[dec.scala 118:22] + wire decode_io_dec_i0_brp_bits_way; // @[dec.scala 118:22] + wire decode_io_dec_i0_brp_bits_ret; // @[dec.scala 118:22] + wire [7:0] decode_io_dec_i0_bp_index; // @[dec.scala 118:22] + wire [7:0] decode_io_dec_i0_bp_fghr; // @[dec.scala 118:22] + wire [4:0] decode_io_dec_i0_bp_btag; // @[dec.scala 118:22] + wire decode_io_lsu_idle_any; // @[dec.scala 118:22] + wire decode_io_lsu_load_stall_any; // @[dec.scala 118:22] + wire decode_io_lsu_store_stall_any; // @[dec.scala 118:22] + wire decode_io_exu_div_wren; // @[dec.scala 118:22] + wire decode_io_dec_tlu_i0_kill_writeb_wb; // @[dec.scala 118:22] + wire decode_io_dec_tlu_flush_lower_wb; // @[dec.scala 118:22] + wire decode_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 118:22] + wire decode_io_dec_tlu_flush_lower_r; // @[dec.scala 118:22] + wire decode_io_dec_tlu_flush_pause_r; // @[dec.scala 118:22] + wire decode_io_dec_tlu_presync_d; // @[dec.scala 118:22] + wire decode_io_dec_tlu_postsync_d; // @[dec.scala 118:22] + wire decode_io_dec_i0_pc4_d; // @[dec.scala 118:22] + wire [31:0] decode_io_dec_csr_rddata_d; // @[dec.scala 118:22] + wire decode_io_dec_csr_legal_d; // @[dec.scala 118:22] + wire [31:0] decode_io_lsu_result_m; // @[dec.scala 118:22] + wire [31:0] decode_io_lsu_result_corr_r; // @[dec.scala 118:22] + wire decode_io_exu_flush_final; // @[dec.scala 118:22] + wire [31:0] decode_io_dec_i0_instr_d; // @[dec.scala 118:22] + wire decode_io_dec_ib0_valid_d; // @[dec.scala 118:22] + wire decode_io_free_clk; // @[dec.scala 118:22] + wire decode_io_active_clk; // @[dec.scala 118:22] + wire decode_io_clk_override; // @[dec.scala 118:22] + wire [4:0] decode_io_dec_i0_rs1_d; // @[dec.scala 118:22] + wire [4:0] decode_io_dec_i0_rs2_d; // @[dec.scala 118:22] + wire [4:0] decode_io_dec_i0_waddr_r; // @[dec.scala 118:22] + wire decode_io_dec_i0_wen_r; // @[dec.scala 118:22] + wire [31:0] decode_io_dec_i0_wdata_r; // @[dec.scala 118:22] + wire decode_io_lsu_p_valid; // @[dec.scala 118:22] + wire decode_io_lsu_p_bits_fast_int; // @[dec.scala 118:22] + wire decode_io_lsu_p_bits_by; // @[dec.scala 118:22] + wire decode_io_lsu_p_bits_half; // @[dec.scala 118:22] + wire decode_io_lsu_p_bits_word; // @[dec.scala 118:22] + wire decode_io_lsu_p_bits_load; // @[dec.scala 118:22] + wire decode_io_lsu_p_bits_store; // @[dec.scala 118:22] + wire decode_io_lsu_p_bits_unsign; // @[dec.scala 118:22] + wire decode_io_lsu_p_bits_store_data_bypass_d; // @[dec.scala 118:22] + wire decode_io_lsu_p_bits_load_ldst_bypass_d; // @[dec.scala 118:22] + wire [4:0] decode_io_div_waddr_wb; // @[dec.scala 118:22] + wire decode_io_dec_lsu_valid_raw_d; // @[dec.scala 118:22] + wire [11:0] decode_io_dec_lsu_offset_d; // @[dec.scala 118:22] + wire decode_io_dec_csr_wen_unq_d; // @[dec.scala 118:22] + wire decode_io_dec_csr_any_unq_d; // @[dec.scala 118:22] + wire [11:0] decode_io_dec_csr_rdaddr_d; // @[dec.scala 118:22] + wire decode_io_dec_csr_wen_r; // @[dec.scala 118:22] + wire [11:0] decode_io_dec_csr_wraddr_r; // @[dec.scala 118:22] + wire [31:0] decode_io_dec_csr_wrdata_r; // @[dec.scala 118:22] + wire decode_io_dec_csr_stall_int_ff; // @[dec.scala 118:22] + wire decode_io_dec_tlu_i0_valid_r; // @[dec.scala 118:22] + wire decode_io_dec_tlu_packet_r_legal; // @[dec.scala 118:22] + wire decode_io_dec_tlu_packet_r_icaf; // @[dec.scala 118:22] + wire decode_io_dec_tlu_packet_r_icaf_f1; // @[dec.scala 118:22] + wire [1:0] decode_io_dec_tlu_packet_r_icaf_type; // @[dec.scala 118:22] + wire decode_io_dec_tlu_packet_r_fence_i; // @[dec.scala 118:22] + wire [3:0] decode_io_dec_tlu_packet_r_i0trigger; // @[dec.scala 118:22] + wire [3:0] decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec.scala 118:22] + wire decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec.scala 118:22] + wire decode_io_dec_tlu_packet_r_pmu_divide; // @[dec.scala 118:22] + wire decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec.scala 118:22] + wire [30:0] decode_io_dec_tlu_i0_pc_r; // @[dec.scala 118:22] + wire [31:0] decode_io_dec_illegal_inst; // @[dec.scala 118:22] + wire decode_io_dec_pmu_instr_decoded; // @[dec.scala 118:22] + wire decode_io_dec_pmu_decode_stall; // @[dec.scala 118:22] + wire decode_io_dec_pmu_presync_stall; // @[dec.scala 118:22] + wire decode_io_dec_pmu_postsync_stall; // @[dec.scala 118:22] + wire decode_io_dec_nonblock_load_wen; // @[dec.scala 118:22] + wire [4:0] decode_io_dec_nonblock_load_waddr; // @[dec.scala 118:22] + wire decode_io_dec_pause_state; // @[dec.scala 118:22] + wire decode_io_dec_pause_state_cg; // @[dec.scala 118:22] + wire decode_io_dec_div_active; // @[dec.scala 118:22] + wire decode_io_scan_mode; // @[dec.scala 118:22] + wire decode_io_dec_aln_dec_i0_decode_d; // @[dec.scala 118:22] + wire [15:0] decode_io_dec_aln_ifu_i0_cinst; // @[dec.scala 118:22] + wire [1:0] decode_io_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 118:22] + wire gpr_clock; // @[dec.scala 119:19] + wire gpr_reset; // @[dec.scala 119:19] + wire [4:0] gpr_io_raddr0; // @[dec.scala 119:19] + wire [4:0] gpr_io_raddr1; // @[dec.scala 119:19] + wire gpr_io_wen0; // @[dec.scala 119:19] + wire [4:0] gpr_io_waddr0; // @[dec.scala 119:19] + wire [31:0] gpr_io_wd0; // @[dec.scala 119:19] + wire gpr_io_wen1; // @[dec.scala 119:19] + wire [4:0] gpr_io_waddr1; // @[dec.scala 119:19] + wire [31:0] gpr_io_wd1; // @[dec.scala 119:19] + wire gpr_io_wen2; // @[dec.scala 119:19] + wire [4:0] gpr_io_waddr2; // @[dec.scala 119:19] + wire [31:0] gpr_io_wd2; // @[dec.scala 119:19] + wire gpr_io_scan_mode; // @[dec.scala 119:19] + wire [31:0] gpr_io_gpr_exu_gpr_i0_rs1_d; // @[dec.scala 119:19] + wire [31:0] gpr_io_gpr_exu_gpr_i0_rs2_d; // @[dec.scala 119:19] + wire tlu_clock; // @[dec.scala 120:19] + wire tlu_reset; // @[dec.scala 120:19] + wire [29:0] tlu_io_tlu_exu_dec_tlu_meihap; // @[dec.scala 120:19] + wire tlu_io_tlu_exu_dec_tlu_flush_lower_r; // @[dec.scala 120:19] + wire [30:0] tlu_io_tlu_exu_dec_tlu_flush_path_r; // @[dec.scala 120:19] + wire [1:0] tlu_io_tlu_exu_exu_i0_br_hist_r; // @[dec.scala 120:19] + wire tlu_io_tlu_exu_exu_i0_br_error_r; // @[dec.scala 120:19] + wire tlu_io_tlu_exu_exu_i0_br_start_error_r; // @[dec.scala 120:19] + wire tlu_io_tlu_exu_exu_i0_br_valid_r; // @[dec.scala 120:19] + wire tlu_io_tlu_exu_exu_i0_br_mp_r; // @[dec.scala 120:19] + wire tlu_io_tlu_exu_exu_i0_br_middle_r; // @[dec.scala 120:19] + wire tlu_io_tlu_exu_exu_pmu_i0_br_misp; // @[dec.scala 120:19] + wire tlu_io_tlu_exu_exu_pmu_i0_br_ataken; // @[dec.scala 120:19] + wire tlu_io_tlu_exu_exu_pmu_i0_pc4; // @[dec.scala 120:19] + wire [30:0] tlu_io_tlu_exu_exu_npc_r; // @[dec.scala 120:19] + wire tlu_io_tlu_dma_dma_pmu_dccm_read; // @[dec.scala 120:19] + wire tlu_io_tlu_dma_dma_pmu_dccm_write; // @[dec.scala 120:19] + wire tlu_io_tlu_dma_dma_pmu_any_read; // @[dec.scala 120:19] + wire tlu_io_tlu_dma_dma_pmu_any_write; // @[dec.scala 120:19] + wire [2:0] tlu_io_tlu_dma_dec_tlu_dma_qos_prty; // @[dec.scala 120:19] + wire tlu_io_tlu_dma_dma_dccm_stall_any; // @[dec.scala 120:19] + wire tlu_io_tlu_dma_dma_iccm_stall_any; // @[dec.scala 120:19] + wire tlu_io_active_clk; // @[dec.scala 120:19] + wire tlu_io_free_clk; // @[dec.scala 120:19] + wire tlu_io_scan_mode; // @[dec.scala 120:19] + wire [30:0] tlu_io_rst_vec; // @[dec.scala 120:19] + wire tlu_io_nmi_int; // @[dec.scala 120:19] + wire [30:0] tlu_io_nmi_vec; // @[dec.scala 120:19] + wire tlu_io_i_cpu_halt_req; // @[dec.scala 120:19] + wire tlu_io_i_cpu_run_req; // @[dec.scala 120:19] + wire tlu_io_lsu_fastint_stall_any; // @[dec.scala 120:19] + wire tlu_io_lsu_idle_any; // @[dec.scala 120:19] + wire tlu_io_dec_pmu_instr_decoded; // @[dec.scala 120:19] + wire tlu_io_dec_pmu_decode_stall; // @[dec.scala 120:19] + wire tlu_io_dec_pmu_presync_stall; // @[dec.scala 120:19] + wire tlu_io_dec_pmu_postsync_stall; // @[dec.scala 120:19] + wire tlu_io_lsu_store_stall_any; // @[dec.scala 120:19] + wire [30:0] tlu_io_lsu_fir_addr; // @[dec.scala 120:19] + wire [1:0] tlu_io_lsu_fir_error; // @[dec.scala 120:19] + wire tlu_io_iccm_dma_sb_error; // @[dec.scala 120:19] + wire tlu_io_lsu_error_pkt_r_valid; // @[dec.scala 120:19] + wire tlu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec.scala 120:19] + wire tlu_io_lsu_error_pkt_r_bits_inst_type; // @[dec.scala 120:19] + wire tlu_io_lsu_error_pkt_r_bits_exc_type; // @[dec.scala 120:19] + wire [3:0] tlu_io_lsu_error_pkt_r_bits_mscause; // @[dec.scala 120:19] + wire [31:0] tlu_io_lsu_error_pkt_r_bits_addr; // @[dec.scala 120:19] + wire tlu_io_lsu_single_ecc_error_incr; // @[dec.scala 120:19] + wire tlu_io_dec_pause_state; // @[dec.scala 120:19] + wire tlu_io_dec_csr_wen_unq_d; // @[dec.scala 120:19] + wire tlu_io_dec_csr_any_unq_d; // @[dec.scala 120:19] + wire [11:0] tlu_io_dec_csr_rdaddr_d; // @[dec.scala 120:19] + wire tlu_io_dec_csr_wen_r; // @[dec.scala 120:19] + wire [11:0] tlu_io_dec_csr_wraddr_r; // @[dec.scala 120:19] + wire [31:0] tlu_io_dec_csr_wrdata_r; // @[dec.scala 120:19] + wire tlu_io_dec_csr_stall_int_ff; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_i0_valid_r; // @[dec.scala 120:19] + wire [30:0] tlu_io_dec_tlu_i0_pc_r; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_packet_r_legal; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_packet_r_icaf; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_packet_r_icaf_f1; // @[dec.scala 120:19] + wire [1:0] tlu_io_dec_tlu_packet_r_icaf_type; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_packet_r_fence_i; // @[dec.scala 120:19] + wire [3:0] tlu_io_dec_tlu_packet_r_i0trigger; // @[dec.scala 120:19] + wire [3:0] tlu_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_packet_r_pmu_divide; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec.scala 120:19] + wire [31:0] tlu_io_dec_illegal_inst; // @[dec.scala 120:19] + wire tlu_io_dec_i0_decode_d; // @[dec.scala 120:19] + wire tlu_io_exu_i0_br_way_r; // @[dec.scala 120:19] + wire tlu_io_dec_dbg_cmd_done; // @[dec.scala 120:19] + wire tlu_io_dec_dbg_cmd_fail; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_dbg_halted; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_debug_mode; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_resume_ack; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_debug_stall; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_mpc_halted_only; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_flush_extint; // @[dec.scala 120:19] + wire tlu_io_dbg_halt_req; // @[dec.scala 120:19] + wire tlu_io_dbg_resume_req; // @[dec.scala 120:19] + wire tlu_io_dec_div_active; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_0_select; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_0_store; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_0_load; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_0_execute; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_0_m; // @[dec.scala 120:19] + wire [31:0] tlu_io_trigger_pkt_any_0_tdata2; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_1_select; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_1_store; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_1_load; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_1_execute; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_1_m; // @[dec.scala 120:19] + wire [31:0] tlu_io_trigger_pkt_any_1_tdata2; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_2_select; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_2_store; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_2_load; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_2_execute; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_2_m; // @[dec.scala 120:19] + wire [31:0] tlu_io_trigger_pkt_any_2_tdata2; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_3_select; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_3_store; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_3_load; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_3_execute; // @[dec.scala 120:19] + wire tlu_io_trigger_pkt_any_3_m; // @[dec.scala 120:19] + wire [31:0] tlu_io_trigger_pkt_any_3_tdata2; // @[dec.scala 120:19] + wire tlu_io_timer_int; // @[dec.scala 120:19] + wire tlu_io_soft_int; // @[dec.scala 120:19] + wire tlu_io_o_cpu_halt_status; // @[dec.scala 120:19] + wire tlu_io_o_cpu_halt_ack; // @[dec.scala 120:19] + wire tlu_io_o_cpu_run_ack; // @[dec.scala 120:19] + wire tlu_io_o_debug_mode_status; // @[dec.scala 120:19] + wire [27:0] tlu_io_core_id; // @[dec.scala 120:19] + wire tlu_io_mpc_debug_halt_req; // @[dec.scala 120:19] + wire tlu_io_mpc_debug_run_req; // @[dec.scala 120:19] + wire tlu_io_mpc_reset_run_req; // @[dec.scala 120:19] + wire tlu_io_mpc_debug_halt_ack; // @[dec.scala 120:19] + wire tlu_io_mpc_debug_run_ack; // @[dec.scala 120:19] + wire tlu_io_debug_brkpt_status; // @[dec.scala 120:19] + wire [31:0] tlu_io_dec_csr_rddata_d; // @[dec.scala 120:19] + wire tlu_io_dec_csr_legal_d; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_i0_kill_writeb_wb; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_wr_pause_r; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_flush_pause_r; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_presync_d; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_postsync_d; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_perfcnt0; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_perfcnt1; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_perfcnt2; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_perfcnt3; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_i0_exc_valid_wb1; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_i0_valid_wb1; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_int_valid_wb1; // @[dec.scala 120:19] + wire [4:0] tlu_io_dec_tlu_exc_cause_wb1; // @[dec.scala 120:19] + wire [31:0] tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_pipelining_disable; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_flush_lower_wb; // @[dec.scala 120:19] + wire tlu_io_ifu_pmu_instr_aligned; // @[dec.scala 120:19] + wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_valid; // @[dec.scala 120:19] + wire [1:0] tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist; // @[dec.scala 120:19] + wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[dec.scala 120:19] + wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[dec.scala 120:19] + wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_way; // @[dec.scala 120:19] + wire tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle; // @[dec.scala 120:19] + wire tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb; // @[dec.scala 120:19] + wire tlu_io_tlu_bp_dec_tlu_bpred_disable; // @[dec.scala 120:19] + wire tlu_io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec.scala 120:19] + wire [31:0] tlu_io_tlu_ifc_dec_tlu_mrac_ff; // @[dec.scala 120:19] + wire tlu_io_tlu_ifc_ifu_pmu_fetch_stall; // @[dec.scala 120:19] + wire tlu_io_tlu_mem_dec_tlu_flush_err_wb; // @[dec.scala 120:19] + wire tlu_io_tlu_mem_dec_tlu_i0_commit_cmt; // @[dec.scala 120:19] + wire tlu_io_tlu_mem_dec_tlu_force_halt; // @[dec.scala 120:19] + wire tlu_io_tlu_mem_dec_tlu_fence_i_wb; // @[dec.scala 120:19] + wire [70:0] tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec.scala 120:19] + wire [16:0] tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec.scala 120:19] + wire tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec.scala 120:19] + wire tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec.scala 120:19] + wire tlu_io_tlu_mem_dec_tlu_core_ecc_disable; // @[dec.scala 120:19] + wire tlu_io_tlu_mem_ifu_pmu_ic_miss; // @[dec.scala 120:19] + wire tlu_io_tlu_mem_ifu_pmu_ic_hit; // @[dec.scala 120:19] + wire tlu_io_tlu_mem_ifu_pmu_bus_error; // @[dec.scala 120:19] + wire tlu_io_tlu_mem_ifu_pmu_bus_busy; // @[dec.scala 120:19] + wire tlu_io_tlu_mem_ifu_pmu_bus_trxn; // @[dec.scala 120:19] + wire tlu_io_tlu_mem_ifu_ic_error_start; // @[dec.scala 120:19] + wire tlu_io_tlu_mem_ifu_iccm_rd_ecc_single_err; // @[dec.scala 120:19] + wire [70:0] tlu_io_tlu_mem_ifu_ic_debug_rd_data; // @[dec.scala 120:19] + wire tlu_io_tlu_mem_ifu_ic_debug_rd_data_valid; // @[dec.scala 120:19] + wire tlu_io_tlu_mem_ifu_miss_state_idle; // @[dec.scala 120:19] + wire tlu_io_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec.scala 120:19] + wire tlu_io_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec.scala 120:19] + wire tlu_io_tlu_busbuff_lsu_pmu_bus_error; // @[dec.scala 120:19] + wire tlu_io_tlu_busbuff_lsu_pmu_bus_busy; // @[dec.scala 120:19] + wire tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 120:19] + wire tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 120:19] + wire tlu_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec.scala 120:19] + wire tlu_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec.scala 120:19] + wire [31:0] tlu_io_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec.scala 120:19] + wire tlu_io_lsu_tlu_lsu_pmu_load_external_m; // @[dec.scala 120:19] + wire tlu_io_lsu_tlu_lsu_pmu_store_external_m; // @[dec.scala 120:19] + wire [7:0] tlu_io_dec_pic_pic_claimid; // @[dec.scala 120:19] + wire [3:0] tlu_io_dec_pic_pic_pl; // @[dec.scala 120:19] + wire tlu_io_dec_pic_mhwakeup; // @[dec.scala 120:19] + wire [3:0] tlu_io_dec_pic_dec_tlu_meicurpl; // @[dec.scala 120:19] + wire [3:0] tlu_io_dec_pic_dec_tlu_meipt; // @[dec.scala 120:19] + wire tlu_io_dec_pic_mexintpend; // @[dec.scala 120:19] + wire dec_trigger_io_trigger_pkt_any_0_select; // @[dec.scala 121:27] + wire dec_trigger_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 121:27] + wire dec_trigger_io_trigger_pkt_any_0_execute; // @[dec.scala 121:27] + wire dec_trigger_io_trigger_pkt_any_0_m; // @[dec.scala 121:27] + wire [31:0] dec_trigger_io_trigger_pkt_any_0_tdata2; // @[dec.scala 121:27] + wire dec_trigger_io_trigger_pkt_any_1_select; // @[dec.scala 121:27] + wire dec_trigger_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 121:27] + wire dec_trigger_io_trigger_pkt_any_1_execute; // @[dec.scala 121:27] + wire dec_trigger_io_trigger_pkt_any_1_m; // @[dec.scala 121:27] + wire [31:0] dec_trigger_io_trigger_pkt_any_1_tdata2; // @[dec.scala 121:27] + wire dec_trigger_io_trigger_pkt_any_2_select; // @[dec.scala 121:27] + wire dec_trigger_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 121:27] + wire dec_trigger_io_trigger_pkt_any_2_execute; // @[dec.scala 121:27] + wire dec_trigger_io_trigger_pkt_any_2_m; // @[dec.scala 121:27] + wire [31:0] dec_trigger_io_trigger_pkt_any_2_tdata2; // @[dec.scala 121:27] + wire dec_trigger_io_trigger_pkt_any_3_select; // @[dec.scala 121:27] + wire dec_trigger_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 121:27] + wire dec_trigger_io_trigger_pkt_any_3_execute; // @[dec.scala 121:27] + wire dec_trigger_io_trigger_pkt_any_3_m; // @[dec.scala 121:27] + wire [31:0] dec_trigger_io_trigger_pkt_any_3_tdata2; // @[dec.scala 121:27] + wire [30:0] dec_trigger_io_dec_i0_pc_d; // @[dec.scala 121:27] + wire [3:0] dec_trigger_io_dec_i0_trigger_match_d; // @[dec.scala 121:27] + wire _T_1 = tlu_io_dec_tlu_i0_valid_wb1 | tlu_io_dec_tlu_i0_exc_valid_wb1; // @[dec.scala 296:98] + dec_ib_ctl instbuff ( // @[dec.scala 117:24] .io_ifu_ib_ifu_i0_icaf(instbuff_io_ifu_ib_ifu_i0_icaf), .io_ifu_ib_ifu_i0_icaf_type(instbuff_io_ifu_ib_ifu_i0_icaf_type), .io_ifu_ib_ifu_i0_icaf_f1(instbuff_io_ifu_ib_ifu_i0_icaf_f1), @@ -58572,7 +58563,7 @@ module dec( .io_dec_i0_dbecc_d(instbuff_io_dec_i0_dbecc_d), .io_dec_debug_fence_d(instbuff_io_dec_debug_fence_d) ); - dec_decode_ctl decode ( // @[dec.scala 127:22] + dec_decode_ctl decode ( // @[dec.scala 118:22] .clock(decode_clock), .reset(decode_reset), .io_decode_exu_dec_data_en(decode_io_decode_exu_dec_data_en), @@ -58642,6 +58633,7 @@ module dec( .io_dctl_busbuff_lsu_nonblock_load_data_error(decode_io_dctl_busbuff_lsu_nonblock_load_data_error), .io_dctl_busbuff_lsu_nonblock_load_data_tag(decode_io_dctl_busbuff_lsu_nonblock_load_data_tag), .io_dctl_busbuff_lsu_nonblock_load_data(decode_io_dctl_busbuff_lsu_nonblock_load_data), + .io_dctl_dma_dma_dccm_stall_any(decode_io_dctl_dma_dma_dccm_stall_any), .io_dec_tlu_flush_extint(decode_io_dec_tlu_flush_extint), .io_dec_tlu_force_halt(decode_io_dec_tlu_force_halt), .io_dec_i0_inst_wb1(decode_io_dec_i0_inst_wb1), @@ -58672,7 +58664,6 @@ module dec( .io_lsu_idle_any(decode_io_lsu_idle_any), .io_lsu_load_stall_any(decode_io_lsu_load_stall_any), .io_lsu_store_stall_any(decode_io_lsu_store_stall_any), - .io_dma_dccm_stall_any(decode_io_dma_dccm_stall_any), .io_exu_div_wren(decode_io_exu_div_wren), .io_dec_tlu_i0_kill_writeb_wb(decode_io_dec_tlu_i0_kill_writeb_wb), .io_dec_tlu_flush_lower_wb(decode_io_dec_tlu_flush_lower_wb), @@ -58744,7 +58735,7 @@ module dec( .io_dec_aln_ifu_i0_cinst(decode_io_dec_aln_ifu_i0_cinst), .io_dbg_dctl_dbg_cmd_wrdata(decode_io_dbg_dctl_dbg_cmd_wrdata) ); - dec_gpr_ctl gpr ( // @[dec.scala 128:19] + dec_gpr_ctl gpr ( // @[dec.scala 119:19] .clock(gpr_clock), .reset(gpr_reset), .io_raddr0(gpr_io_raddr0), @@ -58762,7 +58753,7 @@ module dec( .io_gpr_exu_gpr_i0_rs1_d(gpr_io_gpr_exu_gpr_i0_rs1_d), .io_gpr_exu_gpr_i0_rs2_d(gpr_io_gpr_exu_gpr_i0_rs2_d) ); - dec_tlu_ctl tlu ( // @[dec.scala 129:19] + dec_tlu_ctl tlu ( // @[dec.scala 120:19] .clock(tlu_clock), .reset(tlu_reset), .io_tlu_exu_dec_tlu_meihap(tlu_io_tlu_exu_dec_tlu_meihap), @@ -58778,6 +58769,13 @@ module dec( .io_tlu_exu_exu_pmu_i0_br_ataken(tlu_io_tlu_exu_exu_pmu_i0_br_ataken), .io_tlu_exu_exu_pmu_i0_pc4(tlu_io_tlu_exu_exu_pmu_i0_pc4), .io_tlu_exu_exu_npc_r(tlu_io_tlu_exu_exu_npc_r), + .io_tlu_dma_dma_pmu_dccm_read(tlu_io_tlu_dma_dma_pmu_dccm_read), + .io_tlu_dma_dma_pmu_dccm_write(tlu_io_tlu_dma_dma_pmu_dccm_write), + .io_tlu_dma_dma_pmu_any_read(tlu_io_tlu_dma_dma_pmu_any_read), + .io_tlu_dma_dma_pmu_any_write(tlu_io_tlu_dma_dma_pmu_any_write), + .io_tlu_dma_dec_tlu_dma_qos_prty(tlu_io_tlu_dma_dec_tlu_dma_qos_prty), + .io_tlu_dma_dma_dccm_stall_any(tlu_io_tlu_dma_dma_dccm_stall_any), + .io_tlu_dma_dma_iccm_stall_any(tlu_io_tlu_dma_dma_iccm_stall_any), .io_active_clk(tlu_io_active_clk), .io_free_clk(tlu_io_free_clk), .io_scan_mode(tlu_io_scan_mode), @@ -58793,12 +58791,6 @@ module dec( .io_dec_pmu_presync_stall(tlu_io_dec_pmu_presync_stall), .io_dec_pmu_postsync_stall(tlu_io_dec_pmu_postsync_stall), .io_lsu_store_stall_any(tlu_io_lsu_store_stall_any), - .io_dma_dccm_stall_any(tlu_io_dma_dccm_stall_any), - .io_dma_iccm_stall_any(tlu_io_dma_iccm_stall_any), - .io_dma_pmu_dccm_read(tlu_io_dma_pmu_dccm_read), - .io_dma_pmu_dccm_write(tlu_io_dma_pmu_dccm_write), - .io_dma_pmu_any_read(tlu_io_dma_pmu_any_read), - .io_dma_pmu_any_write(tlu_io_dma_pmu_any_write), .io_lsu_fir_addr(tlu_io_lsu_fir_addr), .io_lsu_fir_error(tlu_io_lsu_fir_error), .io_iccm_dma_sb_error(tlu_io_iccm_dma_sb_error), @@ -58871,10 +58863,6 @@ module dec( .io_trigger_pkt_any_3_execute(tlu_io_trigger_pkt_any_3_execute), .io_trigger_pkt_any_3_m(tlu_io_trigger_pkt_any_3_m), .io_trigger_pkt_any_3_tdata2(tlu_io_trigger_pkt_any_3_tdata2), - .io_pic_claimid(tlu_io_pic_claimid), - .io_pic_pl(tlu_io_pic_pl), - .io_mhwakeup(tlu_io_mhwakeup), - .io_mexintpend(tlu_io_mexintpend), .io_timer_int(tlu_io_timer_int), .io_soft_int(tlu_io_soft_int), .io_o_cpu_halt_status(tlu_io_o_cpu_halt_status), @@ -58888,8 +58876,6 @@ module dec( .io_mpc_debug_halt_ack(tlu_io_mpc_debug_halt_ack), .io_mpc_debug_run_ack(tlu_io_mpc_debug_run_ack), .io_debug_brkpt_status(tlu_io_debug_brkpt_status), - .io_dec_tlu_meicurpl(tlu_io_dec_tlu_meicurpl), - .io_dec_tlu_meipt(tlu_io_dec_tlu_meipt), .io_dec_csr_rddata_d(tlu_io_dec_csr_rddata_d), .io_dec_csr_legal_d(tlu_io_dec_csr_legal_d), .io_dec_tlu_i0_kill_writeb_wb(tlu_io_dec_tlu_i0_kill_writeb_wb), @@ -58908,7 +58894,6 @@ module dec( .io_dec_tlu_exc_cause_wb1(tlu_io_dec_tlu_exc_cause_wb1), .io_dec_tlu_mtval_wb1(tlu_io_dec_tlu_mtval_wb1), .io_dec_tlu_pipelining_disable(tlu_io_dec_tlu_pipelining_disable), - .io_dec_tlu_dma_qos_prty(tlu_io_dec_tlu_dma_qos_prty), .io_dec_tlu_misc_clk_override(tlu_io_dec_tlu_misc_clk_override), .io_dec_tlu_dec_clk_override(tlu_io_dec_tlu_dec_clk_override), .io_dec_tlu_lsu_clk_override(tlu_io_dec_tlu_lsu_clk_override), @@ -58916,6 +58901,7 @@ module dec( .io_dec_tlu_pic_clk_override(tlu_io_dec_tlu_pic_clk_override), .io_dec_tlu_dccm_clk_override(tlu_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(tlu_io_dec_tlu_icm_clk_override), + .io_dec_tlu_flush_lower_wb(tlu_io_dec_tlu_flush_lower_wb), .io_ifu_pmu_instr_aligned(tlu_io_ifu_pmu_instr_aligned), .io_tlu_bp_dec_tlu_br0_r_pkt_valid(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_valid), .io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist), @@ -58923,7 +58909,6 @@ module dec( .io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error), .io_tlu_bp_dec_tlu_br0_r_pkt_bits_way(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_way), .io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle(tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle), - .io_tlu_bp_dec_tlu_flush_lower_wb(tlu_io_tlu_bp_dec_tlu_flush_lower_wb), .io_tlu_bp_dec_tlu_flush_leak_one_wb(tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb), .io_tlu_bp_dec_tlu_bpred_disable(tlu_io_tlu_bp_dec_tlu_bpred_disable), .io_tlu_ifc_dec_tlu_flush_noredir_wb(tlu_io_tlu_ifc_dec_tlu_flush_noredir_wb), @@ -58953,15 +58938,20 @@ module dec( .io_tlu_busbuff_lsu_pmu_bus_error(tlu_io_tlu_busbuff_lsu_pmu_bus_error), .io_tlu_busbuff_lsu_pmu_bus_busy(tlu_io_tlu_busbuff_lsu_pmu_bus_busy), .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), - .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_tlu_busbuff_lsu_imprecise_error_load_any(tlu_io_tlu_busbuff_lsu_imprecise_error_load_any), .io_tlu_busbuff_lsu_imprecise_error_store_any(tlu_io_tlu_busbuff_lsu_imprecise_error_store_any), .io_tlu_busbuff_lsu_imprecise_error_addr_any(tlu_io_tlu_busbuff_lsu_imprecise_error_addr_any), .io_lsu_tlu_lsu_pmu_load_external_m(tlu_io_lsu_tlu_lsu_pmu_load_external_m), - .io_lsu_tlu_lsu_pmu_store_external_m(tlu_io_lsu_tlu_lsu_pmu_store_external_m) + .io_lsu_tlu_lsu_pmu_store_external_m(tlu_io_lsu_tlu_lsu_pmu_store_external_m), + .io_dec_pic_pic_claimid(tlu_io_dec_pic_pic_claimid), + .io_dec_pic_pic_pl(tlu_io_dec_pic_pic_pl), + .io_dec_pic_mhwakeup(tlu_io_dec_pic_mhwakeup), + .io_dec_pic_dec_tlu_meicurpl(tlu_io_dec_pic_dec_tlu_meicurpl), + .io_dec_pic_dec_tlu_meipt(tlu_io_dec_pic_dec_tlu_meipt), + .io_dec_pic_mexintpend(tlu_io_dec_pic_mexintpend) ); - dec_trigger dec_trigger ( // @[dec.scala 130:27] + dec_trigger dec_trigger ( // @[dec.scala 121:27] .io_trigger_pkt_any_0_select(dec_trigger_io_trigger_pkt_any_0_select), .io_trigger_pkt_any_0_match_pkt(dec_trigger_io_trigger_pkt_any_0_match_pkt), .io_trigger_pkt_any_0_execute(dec_trigger_io_trigger_pkt_any_0_execute), @@ -58985,383 +58975,381 @@ module dec( .io_dec_i0_pc_d(dec_trigger_io_dec_i0_pc_d), .io_dec_i0_trigger_match_d(dec_trigger_io_dec_i0_trigger_match_d) ); - assign io_dec_pause_state_cg = decode_io_dec_pause_state_cg; // @[dec.scala 196:40] - assign io_o_cpu_halt_status = tlu_io_o_cpu_halt_status; // @[dec.scala 277:29] - assign io_o_cpu_halt_ack = tlu_io_o_cpu_halt_ack; // @[dec.scala 278:29] - assign io_o_cpu_run_ack = tlu_io_o_cpu_run_ack; // @[dec.scala 279:29] - assign io_o_debug_mode_status = tlu_io_o_debug_mode_status; // @[dec.scala 280:29] - assign io_mpc_debug_halt_ack = tlu_io_mpc_debug_halt_ack; // @[dec.scala 281:29] - assign io_mpc_debug_run_ack = tlu_io_mpc_debug_run_ack; // @[dec.scala 282:29] - assign io_debug_brkpt_status = tlu_io_debug_brkpt_status; // @[dec.scala 283:29] - assign io_dec_tlu_meicurpl = tlu_io_dec_tlu_meicurpl; // @[dec.scala 284:29] - assign io_dec_tlu_meipt = tlu_io_dec_tlu_meipt; // @[dec.scala 285:29] - assign io_dec_tlu_dbg_halted = tlu_io_dec_tlu_dbg_halted; // @[dec.scala 272:28] - assign io_dec_tlu_debug_mode = tlu_io_dec_tlu_debug_mode; // @[dec.scala 273:28] - assign io_dec_tlu_resume_ack = tlu_io_dec_tlu_resume_ack; // @[dec.scala 274:28] - assign io_dec_tlu_mpc_halted_only = tlu_io_dec_tlu_mpc_halted_only; // @[dec.scala 275:51] - assign io_dec_dbg_rddata = decode_io_dec_i0_wdata_r; // @[dec.scala 317:21] - assign io_dec_dbg_cmd_done = tlu_io_dec_dbg_cmd_done; // @[dec.scala 270:28] - assign io_dec_dbg_cmd_fail = tlu_io_dec_dbg_cmd_fail; // @[dec.scala 271:28] - assign io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[dec.scala 276:29] - assign io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 276:29] - assign io_trigger_pkt_any_0_store = tlu_io_trigger_pkt_any_0_store; // @[dec.scala 276:29] - assign io_trigger_pkt_any_0_load = tlu_io_trigger_pkt_any_0_load; // @[dec.scala 276:29] - assign io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[dec.scala 276:29] - assign io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[dec.scala 276:29] - assign io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 276:29] - assign io_trigger_pkt_any_1_store = tlu_io_trigger_pkt_any_1_store; // @[dec.scala 276:29] - assign io_trigger_pkt_any_1_load = tlu_io_trigger_pkt_any_1_load; // @[dec.scala 276:29] - assign io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[dec.scala 276:29] - assign io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[dec.scala 276:29] - assign io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 276:29] - assign io_trigger_pkt_any_2_store = tlu_io_trigger_pkt_any_2_store; // @[dec.scala 276:29] - assign io_trigger_pkt_any_2_load = tlu_io_trigger_pkt_any_2_load; // @[dec.scala 276:29] - assign io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[dec.scala 276:29] - assign io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[dec.scala 276:29] - assign io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 276:29] - assign io_trigger_pkt_any_3_store = tlu_io_trigger_pkt_any_3_store; // @[dec.scala 276:29] - assign io_trigger_pkt_any_3_load = tlu_io_trigger_pkt_any_3_load; // @[dec.scala 276:29] - assign io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[dec.scala 276:29] - assign io_lsu_p_valid = decode_io_lsu_p_valid; // @[dec.scala 193:40] - assign io_lsu_p_bits_fast_int = decode_io_lsu_p_bits_fast_int; // @[dec.scala 193:40] - assign io_lsu_p_bits_by = decode_io_lsu_p_bits_by; // @[dec.scala 193:40] - assign io_lsu_p_bits_half = decode_io_lsu_p_bits_half; // @[dec.scala 193:40] - assign io_lsu_p_bits_word = decode_io_lsu_p_bits_word; // @[dec.scala 193:40] - assign io_lsu_p_bits_load = decode_io_lsu_p_bits_load; // @[dec.scala 193:40] - assign io_lsu_p_bits_store = decode_io_lsu_p_bits_store; // @[dec.scala 193:40] - assign io_lsu_p_bits_unsign = decode_io_lsu_p_bits_unsign; // @[dec.scala 193:40] - assign io_lsu_p_bits_store_data_bypass_d = decode_io_lsu_p_bits_store_data_bypass_d; // @[dec.scala 193:40] - assign io_lsu_p_bits_load_ldst_bypass_d = decode_io_lsu_p_bits_load_ldst_bypass_d; // @[dec.scala 193:40] - assign io_dec_lsu_offset_d = decode_io_dec_lsu_offset_d; // @[dec.scala 195:40] - assign io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 286:34] - assign io_dec_tlu_perfcnt0 = tlu_io_dec_tlu_perfcnt0; // @[dec.scala 287:29] - assign io_dec_tlu_perfcnt1 = tlu_io_dec_tlu_perfcnt1; // @[dec.scala 288:29] - assign io_dec_tlu_perfcnt2 = tlu_io_dec_tlu_perfcnt2; // @[dec.scala 289:29] - assign io_dec_tlu_perfcnt3 = tlu_io_dec_tlu_perfcnt3; // @[dec.scala 290:29] - assign io_dec_lsu_valid_raw_d = decode_io_dec_lsu_valid_raw_d; // @[dec.scala 194:40] - assign io_rv_trace_pkt_rv_i_valid_ip = {tlu_io_dec_tlu_int_valid_wb1,_T_1}; // @[dec.scala 309:33] - assign io_rv_trace_pkt_rv_i_insn_ip = decode_io_dec_i0_inst_wb1; // @[dec.scala 307:32] - assign io_rv_trace_pkt_rv_i_address_ip = {decode_io_dec_i0_pc_wb1,1'h0}; // @[dec.scala 308:35] - assign io_rv_trace_pkt_rv_i_exception_ip = {tlu_io_dec_tlu_int_valid_wb1,tlu_io_dec_tlu_i0_exc_valid_wb1}; // @[dec.scala 310:37] - assign io_rv_trace_pkt_rv_i_ecause_ip = tlu_io_dec_tlu_exc_cause_wb1; // @[dec.scala 311:34] - assign io_rv_trace_pkt_rv_i_interrupt_ip = {tlu_io_dec_tlu_int_valid_wb1,1'h0}; // @[dec.scala 312:37] - assign io_rv_trace_pkt_rv_i_tval_ip = tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 313:32] - assign io_dec_tlu_dma_qos_prty = tlu_io_dec_tlu_dma_qos_prty; // @[dec.scala 296:35] - assign io_dec_tlu_misc_clk_override = tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 297:35] - assign io_dec_tlu_lsu_clk_override = tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 299:36] - assign io_dec_tlu_bus_clk_override = tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 300:36] - assign io_dec_tlu_pic_clk_override = tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 301:36] - assign io_dec_tlu_dccm_clk_override = tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 302:36] - assign io_dec_tlu_icm_clk_override = tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 303:36] - assign io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d = decode_io_dec_aln_dec_i0_decode_d; // @[dec.scala 142:21] - assign io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = tlu_io_tlu_mem_dec_tlu_flush_err_wb; // @[dec.scala 210:18] - assign io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = tlu_io_tlu_mem_dec_tlu_i0_commit_cmt; // @[dec.scala 210:18] - assign io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt = tlu_io_tlu_mem_dec_tlu_force_halt; // @[dec.scala 210:18] - assign io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb = tlu_io_tlu_mem_dec_tlu_fence_i_wb; // @[dec.scala 210:18] - assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec.scala 210:18] - assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec.scala 210:18] - assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec.scala 210:18] - assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec.scala 210:18] - assign io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable = tlu_io_tlu_mem_dec_tlu_core_ecc_disable; // @[dec.scala 210:18] - assign io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb = tlu_io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec.scala 211:18] - assign io_ifu_dec_dec_ifc_dec_tlu_mrac_ff = tlu_io_tlu_ifc_dec_tlu_mrac_ff; // @[dec.scala 211:18] - assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_valid; // @[dec.scala 212:18] - assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist; // @[dec.scala 212:18] - assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[dec.scala 212:18] - assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[dec.scala 212:18] - assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_way; // @[dec.scala 212:18] - assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle; // @[dec.scala 212:18] - assign io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb = tlu_io_tlu_bp_dec_tlu_flush_lower_wb; // @[dec.scala 212:18] - assign io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb; // @[dec.scala 212:18] - assign io_ifu_dec_dec_bp_dec_tlu_bpred_disable = tlu_io_tlu_bp_dec_tlu_bpred_disable; // @[dec.scala 212:18] - assign io_dec_exu_dec_alu_dec_i0_alu_decode_d = decode_io_dec_alu_dec_i0_alu_decode_d; // @[dec.scala 144:20] - assign io_dec_exu_dec_alu_dec_csr_ren_d = decode_io_dec_alu_dec_csr_ren_d; // @[dec.scala 144:20] - assign io_dec_exu_dec_alu_dec_i0_br_immed_d = decode_io_dec_alu_dec_i0_br_immed_d; // @[dec.scala 144:20] - assign io_dec_exu_dec_div_div_p_valid = decode_io_dec_div_div_p_valid; // @[dec.scala 145:20] - assign io_dec_exu_dec_div_div_p_bits_unsign = decode_io_dec_div_div_p_bits_unsign; // @[dec.scala 145:20] - assign io_dec_exu_dec_div_div_p_bits_rem = decode_io_dec_div_div_p_bits_rem; // @[dec.scala 145:20] - assign io_dec_exu_dec_div_dec_div_cancel = decode_io_dec_div_dec_div_cancel; // @[dec.scala 145:20] - assign io_dec_exu_decode_exu_dec_data_en = decode_io_decode_exu_dec_data_en; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_dec_ctl_en = decode_io_decode_exu_dec_ctl_en; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_ap_land = decode_io_decode_exu_i0_ap_land; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_ap_lor = decode_io_decode_exu_i0_ap_lor; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_ap_lxor = decode_io_decode_exu_i0_ap_lxor; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_ap_sll = decode_io_decode_exu_i0_ap_sll; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_ap_srl = decode_io_decode_exu_i0_ap_srl; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_ap_sra = decode_io_decode_exu_i0_ap_sra; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_ap_beq = decode_io_decode_exu_i0_ap_beq; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_ap_bne = decode_io_decode_exu_i0_ap_bne; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_ap_blt = decode_io_decode_exu_i0_ap_blt; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_ap_bge = decode_io_decode_exu_i0_ap_bge; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_ap_add = decode_io_decode_exu_i0_ap_add; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_ap_sub = decode_io_decode_exu_i0_ap_sub; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_ap_slt = decode_io_decode_exu_i0_ap_slt; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_ap_unsign = decode_io_decode_exu_i0_ap_unsign; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_ap_jal = decode_io_decode_exu_i0_ap_jal; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_ap_predict_t = decode_io_decode_exu_i0_ap_predict_t; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_ap_predict_nt = decode_io_decode_exu_i0_ap_predict_nt; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_ap_csr_write = decode_io_decode_exu_i0_ap_csr_write; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_ap_csr_imm = decode_io_decode_exu_i0_ap_csr_imm; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_dec_i0_predict_p_d_valid = decode_io_decode_exu_dec_i0_predict_p_d_valid; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4 = decode_io_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist = decode_io_decode_exu_dec_i0_predict_p_d_bits_hist; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset = decode_io_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error = decode_io_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error = decode_io_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett = decode_io_decode_exu_dec_i0_predict_p_d_bits_prett; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall = decode_io_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret = decode_io_decode_exu_dec_i0_predict_p_d_bits_pret; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja = decode_io_decode_exu_dec_i0_predict_p_d_bits_pja; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way = decode_io_decode_exu_dec_i0_predict_p_d_bits_way; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_predict_fghr_d = decode_io_decode_exu_i0_predict_fghr_d; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_predict_index_d = decode_io_decode_exu_i0_predict_index_d; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_i0_predict_btag_d = decode_io_decode_exu_i0_predict_btag_d; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_dec_i0_rs1_en_d = decode_io_decode_exu_dec_i0_rs1_en_d; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_dec_i0_rs2_en_d = decode_io_decode_exu_dec_i0_rs2_en_d; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_dec_i0_immed_d = decode_io_decode_exu_dec_i0_immed_d; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d = decode_io_decode_exu_dec_i0_rs1_bypass_data_d; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d = decode_io_decode_exu_dec_i0_rs2_bypass_data_d; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_dec_i0_select_pc_d = decode_io_decode_exu_dec_i0_select_pc_d; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d = decode_io_decode_exu_dec_i0_rs1_bypass_en_d; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d = decode_io_decode_exu_dec_i0_rs2_bypass_en_d; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_mul_p_valid = decode_io_decode_exu_mul_p_valid; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_mul_p_bits_rs1_sign = decode_io_decode_exu_mul_p_bits_rs1_sign; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_mul_p_bits_rs2_sign = decode_io_decode_exu_mul_p_bits_rs2_sign; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_mul_p_bits_low = decode_io_decode_exu_mul_p_bits_low; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_pred_correct_npc_x = decode_io_decode_exu_pred_correct_npc_x; // @[dec.scala 143:23] - assign io_dec_exu_decode_exu_dec_extint_stall = decode_io_decode_exu_dec_extint_stall; // @[dec.scala 143:23] - assign io_dec_exu_tlu_exu_dec_tlu_meihap = tlu_io_tlu_exu_dec_tlu_meihap; // @[dec.scala 213:18] - assign io_dec_exu_tlu_exu_dec_tlu_flush_lower_r = tlu_io_tlu_exu_dec_tlu_flush_lower_r; // @[dec.scala 213:18] - assign io_dec_exu_tlu_exu_dec_tlu_flush_path_r = tlu_io_tlu_exu_dec_tlu_flush_path_r; // @[dec.scala 213:18] - assign io_dec_exu_ib_exu_dec_i0_pc_d = instbuff_io_ib_exu_dec_i0_pc_d; // @[dec.scala 135:22] - assign io_dec_exu_ib_exu_dec_debug_wdata_rs1_d = instbuff_io_ib_exu_dec_debug_wdata_rs1_d; // @[dec.scala 135:22] - assign io_dec_exu_gpr_exu_gpr_i0_rs1_d = gpr_io_gpr_exu_gpr_i0_rs1_d; // @[dec.scala 209:22] - assign io_dec_exu_gpr_exu_gpr_i0_rs2_d = gpr_io_gpr_exu_gpr_i0_rs2_d; // @[dec.scala 209:22] - assign io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 231:26] - assign io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = tlu_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[dec.scala 231:26] - assign io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 231:26] - assign instbuff_io_ifu_ib_ifu_i0_icaf = io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[dec.scala 134:22] - assign instbuff_io_ifu_ib_ifu_i0_icaf_type = io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[dec.scala 134:22] - assign instbuff_io_ifu_ib_ifu_i0_icaf_f1 = io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[dec.scala 134:22] - assign instbuff_io_ifu_ib_ifu_i0_dbecc = io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[dec.scala 134:22] - assign instbuff_io_ifu_ib_ifu_i0_bp_index = io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[dec.scala 134:22] - assign instbuff_io_ifu_ib_ifu_i0_bp_fghr = io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[dec.scala 134:22] - assign instbuff_io_ifu_ib_ifu_i0_bp_btag = io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[dec.scala 134:22] - assign instbuff_io_ifu_ib_ifu_i0_valid = io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[dec.scala 134:22] - assign instbuff_io_ifu_ib_ifu_i0_instr = io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[dec.scala 134:22] - assign instbuff_io_ifu_ib_ifu_i0_pc = io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[dec.scala 134:22] - assign instbuff_io_ifu_ib_ifu_i0_pc4 = io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[dec.scala 134:22] - assign instbuff_io_ifu_ib_i0_brp_valid = io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[dec.scala 134:22] - assign instbuff_io_ifu_ib_i0_brp_bits_toffset = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[dec.scala 134:22] - assign instbuff_io_ifu_ib_i0_brp_bits_hist = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[dec.scala 134:22] - assign instbuff_io_ifu_ib_i0_brp_bits_br_error = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[dec.scala 134:22] - assign instbuff_io_ifu_ib_i0_brp_bits_br_start_error = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[dec.scala 134:22] - assign instbuff_io_ifu_ib_i0_brp_bits_prett = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[dec.scala 134:22] - assign instbuff_io_ifu_ib_i0_brp_bits_way = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[dec.scala 134:22] - assign instbuff_io_ifu_ib_i0_brp_bits_ret = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[dec.scala 134:22] - assign instbuff_io_dbg_ib_dbg_cmd_valid = io_dec_dbg_dbg_ib_dbg_cmd_valid; // @[dec.scala 136:22] - assign instbuff_io_dbg_ib_dbg_cmd_write = io_dec_dbg_dbg_ib_dbg_cmd_write; // @[dec.scala 136:22] - assign instbuff_io_dbg_ib_dbg_cmd_type = io_dec_dbg_dbg_ib_dbg_cmd_type; // @[dec.scala 136:22] - assign instbuff_io_dbg_ib_dbg_cmd_addr = io_dec_dbg_dbg_ib_dbg_cmd_addr; // @[dec.scala 136:22] + assign io_dec_pause_state_cg = decode_io_dec_pause_state_cg; // @[dec.scala 188:40] + assign io_o_cpu_halt_status = tlu_io_o_cpu_halt_status; // @[dec.scala 265:29] + assign io_o_cpu_halt_ack = tlu_io_o_cpu_halt_ack; // @[dec.scala 266:29] + assign io_o_cpu_run_ack = tlu_io_o_cpu_run_ack; // @[dec.scala 267:29] + assign io_o_debug_mode_status = tlu_io_o_debug_mode_status; // @[dec.scala 268:29] + assign io_mpc_debug_halt_ack = tlu_io_mpc_debug_halt_ack; // @[dec.scala 269:29] + assign io_mpc_debug_run_ack = tlu_io_mpc_debug_run_ack; // @[dec.scala 270:29] + assign io_debug_brkpt_status = tlu_io_debug_brkpt_status; // @[dec.scala 271:29] + assign io_dec_tlu_dbg_halted = tlu_io_dec_tlu_dbg_halted; // @[dec.scala 260:28] + assign io_dec_tlu_debug_mode = tlu_io_dec_tlu_debug_mode; // @[dec.scala 261:28] + assign io_dec_tlu_resume_ack = tlu_io_dec_tlu_resume_ack; // @[dec.scala 262:28] + assign io_dec_tlu_mpc_halted_only = tlu_io_dec_tlu_mpc_halted_only; // @[dec.scala 263:51] + assign io_dec_dbg_rddata = decode_io_dec_i0_wdata_r; // @[dec.scala 304:21] + assign io_dec_dbg_cmd_done = tlu_io_dec_dbg_cmd_done; // @[dec.scala 258:28] + assign io_dec_dbg_cmd_fail = tlu_io_dec_dbg_cmd_fail; // @[dec.scala 259:28] + assign io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[dec.scala 264:29] + assign io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 264:29] + assign io_trigger_pkt_any_0_store = tlu_io_trigger_pkt_any_0_store; // @[dec.scala 264:29] + assign io_trigger_pkt_any_0_load = tlu_io_trigger_pkt_any_0_load; // @[dec.scala 264:29] + assign io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[dec.scala 264:29] + assign io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[dec.scala 264:29] + assign io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 264:29] + assign io_trigger_pkt_any_1_store = tlu_io_trigger_pkt_any_1_store; // @[dec.scala 264:29] + assign io_trigger_pkt_any_1_load = tlu_io_trigger_pkt_any_1_load; // @[dec.scala 264:29] + assign io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[dec.scala 264:29] + assign io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[dec.scala 264:29] + assign io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 264:29] + assign io_trigger_pkt_any_2_store = tlu_io_trigger_pkt_any_2_store; // @[dec.scala 264:29] + assign io_trigger_pkt_any_2_load = tlu_io_trigger_pkt_any_2_load; // @[dec.scala 264:29] + assign io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[dec.scala 264:29] + assign io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[dec.scala 264:29] + assign io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 264:29] + assign io_trigger_pkt_any_3_store = tlu_io_trigger_pkt_any_3_store; // @[dec.scala 264:29] + assign io_trigger_pkt_any_3_load = tlu_io_trigger_pkt_any_3_load; // @[dec.scala 264:29] + assign io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[dec.scala 264:29] + assign io_lsu_p_valid = decode_io_lsu_p_valid; // @[dec.scala 185:40] + assign io_lsu_p_bits_fast_int = decode_io_lsu_p_bits_fast_int; // @[dec.scala 185:40] + assign io_lsu_p_bits_by = decode_io_lsu_p_bits_by; // @[dec.scala 185:40] + assign io_lsu_p_bits_half = decode_io_lsu_p_bits_half; // @[dec.scala 185:40] + assign io_lsu_p_bits_word = decode_io_lsu_p_bits_word; // @[dec.scala 185:40] + assign io_lsu_p_bits_load = decode_io_lsu_p_bits_load; // @[dec.scala 185:40] + assign io_lsu_p_bits_store = decode_io_lsu_p_bits_store; // @[dec.scala 185:40] + assign io_lsu_p_bits_unsign = decode_io_lsu_p_bits_unsign; // @[dec.scala 185:40] + assign io_lsu_p_bits_store_data_bypass_d = decode_io_lsu_p_bits_store_data_bypass_d; // @[dec.scala 185:40] + assign io_lsu_p_bits_load_ldst_bypass_d = decode_io_lsu_p_bits_load_ldst_bypass_d; // @[dec.scala 185:40] + assign io_dec_lsu_offset_d = decode_io_dec_lsu_offset_d; // @[dec.scala 187:40] + assign io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 274:34] + assign io_dec_tlu_perfcnt0 = tlu_io_dec_tlu_perfcnt0; // @[dec.scala 275:29] + assign io_dec_tlu_perfcnt1 = tlu_io_dec_tlu_perfcnt1; // @[dec.scala 276:29] + assign io_dec_tlu_perfcnt2 = tlu_io_dec_tlu_perfcnt2; // @[dec.scala 277:29] + assign io_dec_tlu_perfcnt3 = tlu_io_dec_tlu_perfcnt3; // @[dec.scala 278:29] + assign io_dec_lsu_valid_raw_d = decode_io_dec_lsu_valid_raw_d; // @[dec.scala 186:40] + assign io_rv_trace_pkt_rv_i_valid_ip = {tlu_io_dec_tlu_int_valid_wb1,_T_1}; // @[dec.scala 296:33] + assign io_rv_trace_pkt_rv_i_insn_ip = decode_io_dec_i0_inst_wb1; // @[dec.scala 294:32] + assign io_rv_trace_pkt_rv_i_address_ip = {decode_io_dec_i0_pc_wb1,1'h0}; // @[dec.scala 295:35] + assign io_rv_trace_pkt_rv_i_exception_ip = {tlu_io_dec_tlu_int_valid_wb1,tlu_io_dec_tlu_i0_exc_valid_wb1}; // @[dec.scala 297:37] + assign io_rv_trace_pkt_rv_i_ecause_ip = tlu_io_dec_tlu_exc_cause_wb1; // @[dec.scala 298:34] + assign io_rv_trace_pkt_rv_i_interrupt_ip = {tlu_io_dec_tlu_int_valid_wb1,1'h0}; // @[dec.scala 299:37] + assign io_rv_trace_pkt_rv_i_tval_ip = tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 300:32] + assign io_dec_tlu_misc_clk_override = tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 284:35] + assign io_dec_tlu_lsu_clk_override = tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 286:36] + assign io_dec_tlu_bus_clk_override = tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 287:36] + assign io_dec_tlu_pic_clk_override = tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 288:36] + assign io_dec_tlu_dccm_clk_override = tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 289:36] + assign io_dec_tlu_icm_clk_override = tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 290:36] + assign io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d = decode_io_dec_aln_dec_i0_decode_d; // @[dec.scala 133:21] + assign io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = tlu_io_tlu_mem_dec_tlu_flush_err_wb; // @[dec.scala 202:18] + assign io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = tlu_io_tlu_mem_dec_tlu_i0_commit_cmt; // @[dec.scala 202:18] + assign io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt = tlu_io_tlu_mem_dec_tlu_force_halt; // @[dec.scala 202:18] + assign io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb = tlu_io_tlu_mem_dec_tlu_fence_i_wb; // @[dec.scala 202:18] + assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wrdata; // @[dec.scala 202:18] + assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_dicawics; // @[dec.scala 202:18] + assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[dec.scala 202:18] + assign io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = tlu_io_tlu_mem_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[dec.scala 202:18] + assign io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable = tlu_io_tlu_mem_dec_tlu_core_ecc_disable; // @[dec.scala 202:18] + assign io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb = tlu_io_tlu_ifc_dec_tlu_flush_noredir_wb; // @[dec.scala 203:18] + assign io_ifu_dec_dec_ifc_dec_tlu_mrac_ff = tlu_io_tlu_ifc_dec_tlu_mrac_ff; // @[dec.scala 203:18] + assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_valid; // @[dec.scala 204:18] + assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_hist; // @[dec.scala 204:18] + assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[dec.scala 204:18] + assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[dec.scala 204:18] + assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_way; // @[dec.scala 204:18] + assign io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = tlu_io_tlu_bp_dec_tlu_br0_r_pkt_bits_middle; // @[dec.scala 204:18] + assign io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb; // @[dec.scala 204:18] + assign io_ifu_dec_dec_bp_dec_tlu_bpred_disable = tlu_io_tlu_bp_dec_tlu_bpred_disable; // @[dec.scala 204:18] + assign io_dec_exu_dec_alu_dec_i0_alu_decode_d = decode_io_dec_alu_dec_i0_alu_decode_d; // @[dec.scala 136:20] + assign io_dec_exu_dec_alu_dec_csr_ren_d = decode_io_dec_alu_dec_csr_ren_d; // @[dec.scala 136:20] + assign io_dec_exu_dec_alu_dec_i0_br_immed_d = decode_io_dec_alu_dec_i0_br_immed_d; // @[dec.scala 136:20] + assign io_dec_exu_dec_div_div_p_valid = decode_io_dec_div_div_p_valid; // @[dec.scala 137:20] + assign io_dec_exu_dec_div_div_p_bits_unsign = decode_io_dec_div_div_p_bits_unsign; // @[dec.scala 137:20] + assign io_dec_exu_dec_div_div_p_bits_rem = decode_io_dec_div_div_p_bits_rem; // @[dec.scala 137:20] + assign io_dec_exu_dec_div_dec_div_cancel = decode_io_dec_div_dec_div_cancel; // @[dec.scala 137:20] + assign io_dec_exu_decode_exu_dec_data_en = decode_io_decode_exu_dec_data_en; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_dec_ctl_en = decode_io_decode_exu_dec_ctl_en; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_ap_land = decode_io_decode_exu_i0_ap_land; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_ap_lor = decode_io_decode_exu_i0_ap_lor; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_ap_lxor = decode_io_decode_exu_i0_ap_lxor; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_ap_sll = decode_io_decode_exu_i0_ap_sll; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_ap_srl = decode_io_decode_exu_i0_ap_srl; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_ap_sra = decode_io_decode_exu_i0_ap_sra; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_ap_beq = decode_io_decode_exu_i0_ap_beq; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_ap_bne = decode_io_decode_exu_i0_ap_bne; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_ap_blt = decode_io_decode_exu_i0_ap_blt; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_ap_bge = decode_io_decode_exu_i0_ap_bge; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_ap_add = decode_io_decode_exu_i0_ap_add; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_ap_sub = decode_io_decode_exu_i0_ap_sub; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_ap_slt = decode_io_decode_exu_i0_ap_slt; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_ap_unsign = decode_io_decode_exu_i0_ap_unsign; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_ap_jal = decode_io_decode_exu_i0_ap_jal; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_ap_predict_t = decode_io_decode_exu_i0_ap_predict_t; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_ap_predict_nt = decode_io_decode_exu_i0_ap_predict_nt; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_ap_csr_write = decode_io_decode_exu_i0_ap_csr_write; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_ap_csr_imm = decode_io_decode_exu_i0_ap_csr_imm; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_valid = decode_io_decode_exu_dec_i0_predict_p_d_valid; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4 = decode_io_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist = decode_io_decode_exu_dec_i0_predict_p_d_bits_hist; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset = decode_io_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error = decode_io_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error = decode_io_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett = decode_io_decode_exu_dec_i0_predict_p_d_bits_prett; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall = decode_io_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret = decode_io_decode_exu_dec_i0_predict_p_d_bits_pret; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja = decode_io_decode_exu_dec_i0_predict_p_d_bits_pja; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way = decode_io_decode_exu_dec_i0_predict_p_d_bits_way; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_predict_fghr_d = decode_io_decode_exu_i0_predict_fghr_d; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_predict_index_d = decode_io_decode_exu_i0_predict_index_d; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_i0_predict_btag_d = decode_io_decode_exu_i0_predict_btag_d; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_dec_i0_rs1_en_d = decode_io_decode_exu_dec_i0_rs1_en_d; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_dec_i0_rs2_en_d = decode_io_decode_exu_dec_i0_rs2_en_d; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_dec_i0_immed_d = decode_io_decode_exu_dec_i0_immed_d; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d = decode_io_decode_exu_dec_i0_rs1_bypass_data_d; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d = decode_io_decode_exu_dec_i0_rs2_bypass_data_d; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_dec_i0_select_pc_d = decode_io_decode_exu_dec_i0_select_pc_d; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d = decode_io_decode_exu_dec_i0_rs1_bypass_en_d; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d = decode_io_decode_exu_dec_i0_rs2_bypass_en_d; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_mul_p_valid = decode_io_decode_exu_mul_p_valid; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_mul_p_bits_rs1_sign = decode_io_decode_exu_mul_p_bits_rs1_sign; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_mul_p_bits_rs2_sign = decode_io_decode_exu_mul_p_bits_rs2_sign; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_mul_p_bits_low = decode_io_decode_exu_mul_p_bits_low; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_pred_correct_npc_x = decode_io_decode_exu_pred_correct_npc_x; // @[dec.scala 135:23] + assign io_dec_exu_decode_exu_dec_extint_stall = decode_io_decode_exu_dec_extint_stall; // @[dec.scala 135:23] + assign io_dec_exu_tlu_exu_dec_tlu_meihap = tlu_io_tlu_exu_dec_tlu_meihap; // @[dec.scala 205:18] + assign io_dec_exu_tlu_exu_dec_tlu_flush_lower_r = tlu_io_tlu_exu_dec_tlu_flush_lower_r; // @[dec.scala 205:18] + assign io_dec_exu_tlu_exu_dec_tlu_flush_path_r = tlu_io_tlu_exu_dec_tlu_flush_path_r; // @[dec.scala 205:18] + assign io_dec_exu_ib_exu_dec_i0_pc_d = instbuff_io_ib_exu_dec_i0_pc_d; // @[dec.scala 126:22] + assign io_dec_exu_ib_exu_dec_debug_wdata_rs1_d = instbuff_io_ib_exu_dec_debug_wdata_rs1_d; // @[dec.scala 126:22] + assign io_dec_exu_gpr_exu_gpr_i0_rs1_d = gpr_io_gpr_exu_gpr_i0_rs1_d; // @[dec.scala 201:22] + assign io_dec_exu_gpr_exu_gpr_i0_rs2_d = gpr_io_gpr_exu_gpr_i0_rs2_d; // @[dec.scala 201:22] + assign io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = tlu_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[dec.scala 222:26] + assign io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = tlu_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[dec.scala 222:26] + assign io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = tlu_io_tlu_dma_dec_tlu_dma_qos_prty; // @[dec.scala 206:18] + assign io_dec_pic_dec_tlu_meicurpl = tlu_io_dec_pic_dec_tlu_meicurpl; // @[dec.scala 224:14] + assign io_dec_pic_dec_tlu_meipt = tlu_io_dec_pic_dec_tlu_meipt; // @[dec.scala 224:14] + assign instbuff_io_ifu_ib_ifu_i0_icaf = io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[dec.scala 125:22] + assign instbuff_io_ifu_ib_ifu_i0_icaf_type = io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[dec.scala 125:22] + assign instbuff_io_ifu_ib_ifu_i0_icaf_f1 = io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[dec.scala 125:22] + assign instbuff_io_ifu_ib_ifu_i0_dbecc = io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[dec.scala 125:22] + assign instbuff_io_ifu_ib_ifu_i0_bp_index = io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[dec.scala 125:22] + assign instbuff_io_ifu_ib_ifu_i0_bp_fghr = io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[dec.scala 125:22] + assign instbuff_io_ifu_ib_ifu_i0_bp_btag = io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[dec.scala 125:22] + assign instbuff_io_ifu_ib_ifu_i0_valid = io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[dec.scala 125:22] + assign instbuff_io_ifu_ib_ifu_i0_instr = io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[dec.scala 125:22] + assign instbuff_io_ifu_ib_ifu_i0_pc = io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[dec.scala 125:22] + assign instbuff_io_ifu_ib_ifu_i0_pc4 = io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[dec.scala 125:22] + assign instbuff_io_ifu_ib_i0_brp_valid = io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[dec.scala 125:22] + assign instbuff_io_ifu_ib_i0_brp_bits_toffset = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[dec.scala 125:22] + assign instbuff_io_ifu_ib_i0_brp_bits_hist = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[dec.scala 125:22] + assign instbuff_io_ifu_ib_i0_brp_bits_br_error = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[dec.scala 125:22] + assign instbuff_io_ifu_ib_i0_brp_bits_br_start_error = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[dec.scala 125:22] + assign instbuff_io_ifu_ib_i0_brp_bits_prett = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[dec.scala 125:22] + assign instbuff_io_ifu_ib_i0_brp_bits_way = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[dec.scala 125:22] + assign instbuff_io_ifu_ib_i0_brp_bits_ret = io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[dec.scala 125:22] + assign instbuff_io_dbg_ib_dbg_cmd_valid = io_dec_dbg_dbg_ib_dbg_cmd_valid; // @[dec.scala 127:22] + assign instbuff_io_dbg_ib_dbg_cmd_write = io_dec_dbg_dbg_ib_dbg_cmd_write; // @[dec.scala 127:22] + assign instbuff_io_dbg_ib_dbg_cmd_type = io_dec_dbg_dbg_ib_dbg_cmd_type; // @[dec.scala 127:22] + assign instbuff_io_dbg_ib_dbg_cmd_addr = io_dec_dbg_dbg_ib_dbg_cmd_addr; // @[dec.scala 127:22] assign decode_clock = clock; assign decode_reset = reset; - assign decode_io_decode_exu_exu_i0_result_x = io_dec_exu_decode_exu_exu_i0_result_x; // @[dec.scala 143:23] - assign decode_io_decode_exu_exu_csr_rs1_x = io_dec_exu_decode_exu_exu_csr_rs1_x; // @[dec.scala 143:23] - assign decode_io_dec_alu_exu_i0_pc_x = io_dec_exu_dec_alu_exu_i0_pc_x; // @[dec.scala 144:20] - assign decode_io_dctl_busbuff_lsu_nonblock_load_valid_m = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec.scala 148:26] - assign decode_io_dctl_busbuff_lsu_nonblock_load_tag_m = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[dec.scala 148:26] - assign decode_io_dctl_busbuff_lsu_nonblock_load_inv_r = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[dec.scala 148:26] - assign decode_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[dec.scala 148:26] - assign decode_io_dctl_busbuff_lsu_nonblock_load_data_valid = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[dec.scala 148:26] - assign decode_io_dctl_busbuff_lsu_nonblock_load_data_error = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec.scala 148:26] - assign decode_io_dctl_busbuff_lsu_nonblock_load_data_tag = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[dec.scala 148:26] - assign decode_io_dctl_busbuff_lsu_nonblock_load_data = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[dec.scala 148:26] - assign decode_io_dec_tlu_flush_extint = tlu_io_dec_tlu_flush_extint; // @[dec.scala 146:48] - assign decode_io_dec_tlu_force_halt = tlu_io_tlu_mem_dec_tlu_force_halt; // @[dec.scala 147:48] - assign decode_io_dec_i0_trigger_match_d = dec_trigger_io_dec_i0_trigger_match_d; // @[dec.scala 149:48] - assign decode_io_dec_tlu_wr_pause_r = tlu_io_dec_tlu_wr_pause_r; // @[dec.scala 150:48] - assign decode_io_dec_tlu_pipelining_disable = tlu_io_dec_tlu_pipelining_disable; // @[dec.scala 151:48] - assign decode_io_lsu_trigger_match_m = io_lsu_trigger_match_m; // @[dec.scala 152:48] - assign decode_io_lsu_pmu_misaligned_m = io_lsu_pmu_misaligned_m; // @[dec.scala 153:48] - assign decode_io_dec_tlu_debug_stall = tlu_io_dec_tlu_debug_stall; // @[dec.scala 154:48] - assign decode_io_dec_tlu_flush_leak_one_r = tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb; // @[dec.scala 155:48] - assign decode_io_dec_debug_fence_d = instbuff_io_dec_debug_fence_d; // @[dec.scala 156:48] - assign decode_io_dec_i0_icaf_d = instbuff_io_dec_i0_icaf_d; // @[dec.scala 158:48] - assign decode_io_dec_i0_icaf_f1_d = instbuff_io_dec_i0_icaf_f1_d; // @[dec.scala 159:48] - assign decode_io_dec_i0_icaf_type_d = instbuff_io_dec_i0_icaf_type_d; // @[dec.scala 160:48] - assign decode_io_dec_i0_dbecc_d = instbuff_io_dec_i0_dbecc_d; // @[dec.scala 161:48] - assign decode_io_dec_i0_brp_valid = instbuff_io_dec_i0_brp_valid; // @[dec.scala 162:48] - assign decode_io_dec_i0_brp_bits_toffset = instbuff_io_dec_i0_brp_bits_toffset; // @[dec.scala 162:48] - assign decode_io_dec_i0_brp_bits_hist = instbuff_io_dec_i0_brp_bits_hist; // @[dec.scala 162:48] - assign decode_io_dec_i0_brp_bits_br_error = instbuff_io_dec_i0_brp_bits_br_error; // @[dec.scala 162:48] - assign decode_io_dec_i0_brp_bits_br_start_error = instbuff_io_dec_i0_brp_bits_br_start_error; // @[dec.scala 162:48] - assign decode_io_dec_i0_brp_bits_prett = instbuff_io_dec_i0_brp_bits_prett; // @[dec.scala 162:48] - assign decode_io_dec_i0_brp_bits_way = instbuff_io_dec_i0_brp_bits_way; // @[dec.scala 162:48] - assign decode_io_dec_i0_brp_bits_ret = instbuff_io_dec_i0_brp_bits_ret; // @[dec.scala 162:48] - assign decode_io_dec_i0_bp_index = instbuff_io_dec_i0_bp_index; // @[dec.scala 163:48] - assign decode_io_dec_i0_bp_fghr = instbuff_io_dec_i0_bp_fghr; // @[dec.scala 164:48] - assign decode_io_dec_i0_bp_btag = instbuff_io_dec_i0_bp_btag; // @[dec.scala 165:48] - assign decode_io_lsu_idle_any = io_lsu_idle_any; // @[dec.scala 167:48] - assign decode_io_lsu_load_stall_any = io_lsu_load_stall_any; // @[dec.scala 168:48] - assign decode_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec.scala 169:48] - assign decode_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[dec.scala 170:48] - assign decode_io_exu_div_wren = io_exu_div_wren; // @[dec.scala 171:48] - assign decode_io_dec_tlu_i0_kill_writeb_wb = tlu_io_dec_tlu_i0_kill_writeb_wb; // @[dec.scala 172:48] - assign decode_io_dec_tlu_flush_lower_wb = tlu_io_tlu_bp_dec_tlu_flush_lower_wb; // @[dec.scala 173:48] - assign decode_io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 174:48] - assign decode_io_dec_tlu_flush_lower_r = tlu_io_tlu_exu_dec_tlu_flush_lower_r; // @[dec.scala 175:48] - assign decode_io_dec_tlu_flush_pause_r = tlu_io_dec_tlu_flush_pause_r; // @[dec.scala 176:48] - assign decode_io_dec_tlu_presync_d = tlu_io_dec_tlu_presync_d; // @[dec.scala 177:48] - assign decode_io_dec_tlu_postsync_d = tlu_io_dec_tlu_postsync_d; // @[dec.scala 178:48] - assign decode_io_dec_i0_pc4_d = instbuff_io_dec_i0_pc4_d; // @[dec.scala 179:48] - assign decode_io_dec_csr_rddata_d = tlu_io_dec_csr_rddata_d; // @[dec.scala 180:48] - assign decode_io_dec_csr_legal_d = tlu_io_dec_csr_legal_d; // @[dec.scala 181:48] - assign decode_io_lsu_result_m = io_lsu_result_m; // @[dec.scala 182:48] - assign decode_io_lsu_result_corr_r = io_lsu_result_corr_r; // @[dec.scala 183:48] - assign decode_io_exu_flush_final = io_exu_flush_final; // @[dec.scala 184:48] - assign decode_io_dec_i0_instr_d = instbuff_io_dec_i0_instr_d; // @[dec.scala 185:48] - assign decode_io_dec_ib0_valid_d = instbuff_io_dec_ib0_valid_d; // @[dec.scala 186:48] - assign decode_io_free_clk = io_free_clk; // @[dec.scala 187:48] - assign decode_io_active_clk = io_active_clk; // @[dec.scala 188:48] - assign decode_io_clk_override = tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 189:48] - assign decode_io_scan_mode = io_scan_mode; // @[dec.scala 190:48] - assign decode_io_dec_aln_ifu_i0_cinst = io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[dec.scala 142:21] - assign decode_io_dbg_dctl_dbg_cmd_wrdata = io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 157:22] + assign decode_io_decode_exu_exu_i0_result_x = io_dec_exu_decode_exu_exu_i0_result_x; // @[dec.scala 135:23] + assign decode_io_decode_exu_exu_csr_rs1_x = io_dec_exu_decode_exu_exu_csr_rs1_x; // @[dec.scala 135:23] + assign decode_io_dec_alu_exu_i0_pc_x = io_dec_exu_dec_alu_exu_i0_pc_x; // @[dec.scala 136:20] + assign decode_io_dctl_busbuff_lsu_nonblock_load_valid_m = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec.scala 141:26] + assign decode_io_dctl_busbuff_lsu_nonblock_load_tag_m = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[dec.scala 141:26] + assign decode_io_dctl_busbuff_lsu_nonblock_load_inv_r = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[dec.scala 141:26] + assign decode_io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[dec.scala 141:26] + assign decode_io_dctl_busbuff_lsu_nonblock_load_data_valid = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[dec.scala 141:26] + assign decode_io_dctl_busbuff_lsu_nonblock_load_data_error = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[dec.scala 141:26] + assign decode_io_dctl_busbuff_lsu_nonblock_load_data_tag = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[dec.scala 141:26] + assign decode_io_dctl_busbuff_lsu_nonblock_load_data = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[dec.scala 141:26] + assign decode_io_dctl_dma_dma_dccm_stall_any = io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[dec.scala 138:22] + assign decode_io_dec_tlu_flush_extint = tlu_io_dec_tlu_flush_extint; // @[dec.scala 139:48] + assign decode_io_dec_tlu_force_halt = tlu_io_tlu_mem_dec_tlu_force_halt; // @[dec.scala 140:48] + assign decode_io_dec_i0_trigger_match_d = dec_trigger_io_dec_i0_trigger_match_d; // @[dec.scala 142:48] + assign decode_io_dec_tlu_wr_pause_r = tlu_io_dec_tlu_wr_pause_r; // @[dec.scala 143:48] + assign decode_io_dec_tlu_pipelining_disable = tlu_io_dec_tlu_pipelining_disable; // @[dec.scala 144:48] + assign decode_io_lsu_trigger_match_m = io_lsu_trigger_match_m; // @[dec.scala 145:48] + assign decode_io_lsu_pmu_misaligned_m = io_lsu_pmu_misaligned_m; // @[dec.scala 146:48] + assign decode_io_dec_tlu_debug_stall = tlu_io_dec_tlu_debug_stall; // @[dec.scala 147:48] + assign decode_io_dec_tlu_flush_leak_one_r = tlu_io_tlu_bp_dec_tlu_flush_leak_one_wb; // @[dec.scala 148:48] + assign decode_io_dec_debug_fence_d = instbuff_io_dec_debug_fence_d; // @[dec.scala 149:48] + assign decode_io_dec_i0_icaf_d = instbuff_io_dec_i0_icaf_d; // @[dec.scala 151:48] + assign decode_io_dec_i0_icaf_f1_d = instbuff_io_dec_i0_icaf_f1_d; // @[dec.scala 152:48] + assign decode_io_dec_i0_icaf_type_d = instbuff_io_dec_i0_icaf_type_d; // @[dec.scala 153:48] + assign decode_io_dec_i0_dbecc_d = instbuff_io_dec_i0_dbecc_d; // @[dec.scala 154:48] + assign decode_io_dec_i0_brp_valid = instbuff_io_dec_i0_brp_valid; // @[dec.scala 155:48] + assign decode_io_dec_i0_brp_bits_toffset = instbuff_io_dec_i0_brp_bits_toffset; // @[dec.scala 155:48] + assign decode_io_dec_i0_brp_bits_hist = instbuff_io_dec_i0_brp_bits_hist; // @[dec.scala 155:48] + assign decode_io_dec_i0_brp_bits_br_error = instbuff_io_dec_i0_brp_bits_br_error; // @[dec.scala 155:48] + assign decode_io_dec_i0_brp_bits_br_start_error = instbuff_io_dec_i0_brp_bits_br_start_error; // @[dec.scala 155:48] + assign decode_io_dec_i0_brp_bits_prett = instbuff_io_dec_i0_brp_bits_prett; // @[dec.scala 155:48] + assign decode_io_dec_i0_brp_bits_way = instbuff_io_dec_i0_brp_bits_way; // @[dec.scala 155:48] + assign decode_io_dec_i0_brp_bits_ret = instbuff_io_dec_i0_brp_bits_ret; // @[dec.scala 155:48] + assign decode_io_dec_i0_bp_index = instbuff_io_dec_i0_bp_index; // @[dec.scala 156:48] + assign decode_io_dec_i0_bp_fghr = instbuff_io_dec_i0_bp_fghr; // @[dec.scala 157:48] + assign decode_io_dec_i0_bp_btag = instbuff_io_dec_i0_bp_btag; // @[dec.scala 158:48] + assign decode_io_lsu_idle_any = io_lsu_idle_any; // @[dec.scala 160:48] + assign decode_io_lsu_load_stall_any = io_lsu_load_stall_any; // @[dec.scala 161:48] + assign decode_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec.scala 162:48] + assign decode_io_exu_div_wren = io_exu_div_wren; // @[dec.scala 163:48] + assign decode_io_dec_tlu_i0_kill_writeb_wb = tlu_io_dec_tlu_i0_kill_writeb_wb; // @[dec.scala 164:48] + assign decode_io_dec_tlu_flush_lower_wb = tlu_io_dec_tlu_flush_lower_wb; // @[dec.scala 165:48] + assign decode_io_dec_tlu_i0_kill_writeb_r = tlu_io_dec_tlu_i0_kill_writeb_r; // @[dec.scala 166:48] + assign decode_io_dec_tlu_flush_lower_r = tlu_io_tlu_exu_dec_tlu_flush_lower_r; // @[dec.scala 167:48] + assign decode_io_dec_tlu_flush_pause_r = tlu_io_dec_tlu_flush_pause_r; // @[dec.scala 168:48] + assign decode_io_dec_tlu_presync_d = tlu_io_dec_tlu_presync_d; // @[dec.scala 169:48] + assign decode_io_dec_tlu_postsync_d = tlu_io_dec_tlu_postsync_d; // @[dec.scala 170:48] + assign decode_io_dec_i0_pc4_d = instbuff_io_dec_i0_pc4_d; // @[dec.scala 171:48] + assign decode_io_dec_csr_rddata_d = tlu_io_dec_csr_rddata_d; // @[dec.scala 172:48] + assign decode_io_dec_csr_legal_d = tlu_io_dec_csr_legal_d; // @[dec.scala 173:48] + assign decode_io_lsu_result_m = io_lsu_result_m; // @[dec.scala 174:48] + assign decode_io_lsu_result_corr_r = io_lsu_result_corr_r; // @[dec.scala 175:48] + assign decode_io_exu_flush_final = io_exu_flush_final; // @[dec.scala 176:48] + assign decode_io_dec_i0_instr_d = instbuff_io_dec_i0_instr_d; // @[dec.scala 177:48] + assign decode_io_dec_ib0_valid_d = instbuff_io_dec_ib0_valid_d; // @[dec.scala 178:48] + assign decode_io_free_clk = io_free_clk; // @[dec.scala 179:48] + assign decode_io_active_clk = io_active_clk; // @[dec.scala 180:48] + assign decode_io_clk_override = tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 181:48] + assign decode_io_scan_mode = io_scan_mode; // @[dec.scala 182:48] + assign decode_io_dec_aln_ifu_i0_cinst = io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[dec.scala 133:21] + assign decode_io_dbg_dctl_dbg_cmd_wrdata = io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[dec.scala 150:22] assign gpr_clock = clock; assign gpr_reset = reset; - assign gpr_io_raddr0 = decode_io_dec_i0_rs1_d; // @[dec.scala 197:23] - assign gpr_io_raddr1 = decode_io_dec_i0_rs2_d; // @[dec.scala 198:23] - assign gpr_io_wen0 = decode_io_dec_i0_wen_r; // @[dec.scala 199:23] - assign gpr_io_waddr0 = decode_io_dec_i0_waddr_r; // @[dec.scala 200:23] - assign gpr_io_wd0 = decode_io_dec_i0_wdata_r; // @[dec.scala 201:23] - assign gpr_io_wen1 = decode_io_dec_nonblock_load_wen; // @[dec.scala 202:23] - assign gpr_io_waddr1 = decode_io_dec_nonblock_load_waddr; // @[dec.scala 203:23] - assign gpr_io_wd1 = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[dec.scala 204:23] - assign gpr_io_wen2 = io_exu_div_wren; // @[dec.scala 205:23] - assign gpr_io_waddr2 = decode_io_div_waddr_wb; // @[dec.scala 206:23] - assign gpr_io_wd2 = io_exu_div_result; // @[dec.scala 207:23] - assign gpr_io_scan_mode = io_scan_mode; // @[dec.scala 208:23] + assign gpr_io_raddr0 = decode_io_dec_i0_rs1_d; // @[dec.scala 189:23] + assign gpr_io_raddr1 = decode_io_dec_i0_rs2_d; // @[dec.scala 190:23] + assign gpr_io_wen0 = decode_io_dec_i0_wen_r; // @[dec.scala 191:23] + assign gpr_io_waddr0 = decode_io_dec_i0_waddr_r; // @[dec.scala 192:23] + assign gpr_io_wd0 = decode_io_dec_i0_wdata_r; // @[dec.scala 193:23] + assign gpr_io_wen1 = decode_io_dec_nonblock_load_wen; // @[dec.scala 194:23] + assign gpr_io_waddr1 = decode_io_dec_nonblock_load_waddr; // @[dec.scala 195:23] + assign gpr_io_wd1 = io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[dec.scala 196:23] + assign gpr_io_wen2 = io_exu_div_wren; // @[dec.scala 197:23] + assign gpr_io_waddr2 = decode_io_div_waddr_wb; // @[dec.scala 198:23] + assign gpr_io_wd2 = io_exu_div_result; // @[dec.scala 199:23] + assign gpr_io_scan_mode = io_scan_mode; // @[dec.scala 200:23] assign tlu_clock = clock; assign tlu_reset = reset; - assign tlu_io_tlu_exu_exu_i0_br_hist_r = io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[dec.scala 213:18] - assign tlu_io_tlu_exu_exu_i0_br_error_r = io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[dec.scala 213:18] - assign tlu_io_tlu_exu_exu_i0_br_start_error_r = io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[dec.scala 213:18] - assign tlu_io_tlu_exu_exu_i0_br_valid_r = io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[dec.scala 213:18] - assign tlu_io_tlu_exu_exu_i0_br_mp_r = io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[dec.scala 213:18] - assign tlu_io_tlu_exu_exu_i0_br_middle_r = io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[dec.scala 213:18] - assign tlu_io_tlu_exu_exu_pmu_i0_br_misp = io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[dec.scala 213:18] - assign tlu_io_tlu_exu_exu_pmu_i0_br_ataken = io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[dec.scala 213:18] - assign tlu_io_tlu_exu_exu_pmu_i0_pc4 = io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[dec.scala 213:18] - assign tlu_io_tlu_exu_exu_npc_r = io_dec_exu_tlu_exu_exu_npc_r; // @[dec.scala 213:18] - assign tlu_io_active_clk = io_active_clk; // @[dec.scala 214:45] - assign tlu_io_free_clk = io_free_clk; // @[dec.scala 215:45] - assign tlu_io_scan_mode = io_scan_mode; // @[dec.scala 216:45] - assign tlu_io_rst_vec = io_rst_vec; // @[dec.scala 217:45] - assign tlu_io_nmi_int = io_nmi_int; // @[dec.scala 218:45] - assign tlu_io_nmi_vec = io_nmi_vec; // @[dec.scala 219:45] - assign tlu_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[dec.scala 220:45] - assign tlu_io_i_cpu_run_req = io_i_cpu_run_req; // @[dec.scala 221:45] - assign tlu_io_lsu_fastint_stall_any = io_lsu_fastint_stall_any; // @[dec.scala 222:45] - assign tlu_io_lsu_idle_any = io_lsu_idle_any; // @[dec.scala 258:45] - assign tlu_io_dec_pmu_instr_decoded = decode_io_dec_pmu_instr_decoded; // @[dec.scala 224:45] - assign tlu_io_dec_pmu_decode_stall = decode_io_dec_pmu_decode_stall; // @[dec.scala 225:45] - assign tlu_io_dec_pmu_presync_stall = decode_io_dec_pmu_presync_stall; // @[dec.scala 226:45] - assign tlu_io_dec_pmu_postsync_stall = decode_io_dec_pmu_postsync_stall; // @[dec.scala 227:45] - assign tlu_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec.scala 228:45] - assign tlu_io_dma_dccm_stall_any = io_dma_dccm_stall_any; // @[dec.scala 229:45] - assign tlu_io_dma_iccm_stall_any = io_dma_iccm_stall_any; // @[dec.scala 230:45] - assign tlu_io_dma_pmu_dccm_read = io_dma_pmu_dccm_read; // @[dec.scala 233:45] - assign tlu_io_dma_pmu_dccm_write = io_dma_pmu_dccm_write; // @[dec.scala 234:45] - assign tlu_io_dma_pmu_any_read = io_dma_pmu_any_read; // @[dec.scala 235:45] - assign tlu_io_dma_pmu_any_write = io_dma_pmu_any_write; // @[dec.scala 236:45] - assign tlu_io_lsu_fir_addr = io_lsu_fir_addr; // @[dec.scala 237:45] - assign tlu_io_lsu_fir_error = io_lsu_fir_error; // @[dec.scala 238:45] - assign tlu_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[dec.scala 239:45] - assign tlu_io_lsu_error_pkt_r_valid = io_lsu_error_pkt_r_valid; // @[dec.scala 240:45] - assign tlu_io_lsu_error_pkt_r_bits_single_ecc_error = io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec.scala 240:45] - assign tlu_io_lsu_error_pkt_r_bits_inst_type = io_lsu_error_pkt_r_bits_inst_type; // @[dec.scala 240:45] - assign tlu_io_lsu_error_pkt_r_bits_exc_type = io_lsu_error_pkt_r_bits_exc_type; // @[dec.scala 240:45] - assign tlu_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[dec.scala 240:45] - assign tlu_io_lsu_error_pkt_r_bits_addr = io_lsu_error_pkt_r_bits_addr; // @[dec.scala 240:45] - assign tlu_io_lsu_single_ecc_error_incr = io_lsu_single_ecc_error_incr; // @[dec.scala 241:45] - assign tlu_io_dec_pause_state = decode_io_dec_pause_state; // @[dec.scala 242:45] - assign tlu_io_dec_csr_wen_unq_d = decode_io_dec_csr_wen_unq_d; // @[dec.scala 243:45] - assign tlu_io_dec_csr_any_unq_d = decode_io_dec_csr_any_unq_d; // @[dec.scala 244:45] - assign tlu_io_dec_csr_rdaddr_d = decode_io_dec_csr_rdaddr_d; // @[dec.scala 245:45] - assign tlu_io_dec_csr_wen_r = decode_io_dec_csr_wen_r; // @[dec.scala 246:45] - assign tlu_io_dec_csr_wraddr_r = decode_io_dec_csr_wraddr_r; // @[dec.scala 247:45] - assign tlu_io_dec_csr_wrdata_r = decode_io_dec_csr_wrdata_r; // @[dec.scala 248:45] - assign tlu_io_dec_csr_stall_int_ff = decode_io_dec_csr_stall_int_ff; // @[dec.scala 249:45] - assign tlu_io_dec_tlu_i0_valid_r = decode_io_dec_tlu_i0_valid_r; // @[dec.scala 250:45] - assign tlu_io_dec_tlu_i0_pc_r = decode_io_dec_tlu_i0_pc_r; // @[dec.scala 251:45] - assign tlu_io_dec_tlu_packet_r_legal = decode_io_dec_tlu_packet_r_legal; // @[dec.scala 252:45] - assign tlu_io_dec_tlu_packet_r_icaf = decode_io_dec_tlu_packet_r_icaf; // @[dec.scala 252:45] - assign tlu_io_dec_tlu_packet_r_icaf_f1 = decode_io_dec_tlu_packet_r_icaf_f1; // @[dec.scala 252:45] - assign tlu_io_dec_tlu_packet_r_icaf_type = decode_io_dec_tlu_packet_r_icaf_type; // @[dec.scala 252:45] - assign tlu_io_dec_tlu_packet_r_fence_i = decode_io_dec_tlu_packet_r_fence_i; // @[dec.scala 252:45] - assign tlu_io_dec_tlu_packet_r_i0trigger = decode_io_dec_tlu_packet_r_i0trigger; // @[dec.scala 252:45] - assign tlu_io_dec_tlu_packet_r_pmu_i0_itype = decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec.scala 252:45] - assign tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred = decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec.scala 252:45] - assign tlu_io_dec_tlu_packet_r_pmu_divide = decode_io_dec_tlu_packet_r_pmu_divide; // @[dec.scala 252:45] - assign tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned = decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec.scala 252:45] - assign tlu_io_dec_illegal_inst = decode_io_dec_illegal_inst; // @[dec.scala 253:45] - assign tlu_io_dec_i0_decode_d = decode_io_dec_aln_dec_i0_decode_d; // @[dec.scala 254:45] - assign tlu_io_exu_i0_br_way_r = io_exu_i0_br_way_r; // @[dec.scala 255:45] - assign tlu_io_dbg_halt_req = io_dbg_halt_req; // @[dec.scala 256:45] - assign tlu_io_dbg_resume_req = io_dbg_resume_req; // @[dec.scala 257:45] - assign tlu_io_dec_div_active = decode_io_dec_div_active; // @[dec.scala 259:45] - assign tlu_io_pic_claimid = io_pic_claimid; // @[dec.scala 260:45] - assign tlu_io_pic_pl = io_pic_pl; // @[dec.scala 261:45] - assign tlu_io_mhwakeup = io_mhwakeup; // @[dec.scala 262:45] - assign tlu_io_mexintpend = io_mexintpend; // @[dec.scala 263:45] - assign tlu_io_timer_int = io_timer_int; // @[dec.scala 264:45] - assign tlu_io_soft_int = io_soft_int; // @[dec.scala 265:45] - assign tlu_io_core_id = io_core_id; // @[dec.scala 266:45] - assign tlu_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[dec.scala 267:45] - assign tlu_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[dec.scala 268:45] - assign tlu_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec.scala 269:45] - assign tlu_io_ifu_pmu_instr_aligned = io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[dec.scala 223:45] - assign tlu_io_tlu_ifc_ifu_pmu_fetch_stall = io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[dec.scala 211:18] - assign tlu_io_tlu_mem_ifu_pmu_ic_miss = io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[dec.scala 210:18] - assign tlu_io_tlu_mem_ifu_pmu_ic_hit = io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[dec.scala 210:18] - assign tlu_io_tlu_mem_ifu_pmu_bus_error = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[dec.scala 210:18] - assign tlu_io_tlu_mem_ifu_pmu_bus_busy = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[dec.scala 210:18] - assign tlu_io_tlu_mem_ifu_pmu_bus_trxn = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[dec.scala 210:18] - assign tlu_io_tlu_mem_ifu_ic_error_start = io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[dec.scala 210:18] - assign tlu_io_tlu_mem_ifu_iccm_rd_ecc_single_err = io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[dec.scala 210:18] - assign tlu_io_tlu_mem_ifu_ic_debug_rd_data = io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[dec.scala 210:18] - assign tlu_io_tlu_mem_ifu_ic_debug_rd_data_valid = io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[dec.scala 210:18] - assign tlu_io_tlu_mem_ifu_miss_state_idle = io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[dec.scala 210:18] - assign tlu_io_tlu_busbuff_lsu_pmu_bus_trxn = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec.scala 231:26] - assign tlu_io_tlu_busbuff_lsu_pmu_bus_misaligned = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec.scala 231:26] - assign tlu_io_tlu_busbuff_lsu_pmu_bus_error = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[dec.scala 231:26] - assign tlu_io_tlu_busbuff_lsu_pmu_bus_busy = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[dec.scala 231:26] - assign tlu_io_tlu_busbuff_lsu_imprecise_error_load_any = io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec.scala 231:26] - assign tlu_io_tlu_busbuff_lsu_imprecise_error_store_any = io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec.scala 231:26] - assign tlu_io_tlu_busbuff_lsu_imprecise_error_addr_any = io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec.scala 231:26] - assign tlu_io_lsu_tlu_lsu_pmu_load_external_m = io_lsu_tlu_lsu_pmu_load_external_m; // @[dec.scala 232:14] - assign tlu_io_lsu_tlu_lsu_pmu_store_external_m = io_lsu_tlu_lsu_pmu_store_external_m; // @[dec.scala 232:14] - assign dec_trigger_io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[dec.scala 138:34] - assign dec_trigger_io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 138:34] - assign dec_trigger_io_trigger_pkt_any_0_execute = tlu_io_trigger_pkt_any_0_execute; // @[dec.scala 138:34] - assign dec_trigger_io_trigger_pkt_any_0_m = tlu_io_trigger_pkt_any_0_m; // @[dec.scala 138:34] - assign dec_trigger_io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[dec.scala 138:34] - assign dec_trigger_io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[dec.scala 138:34] - assign dec_trigger_io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 138:34] - assign dec_trigger_io_trigger_pkt_any_1_execute = tlu_io_trigger_pkt_any_1_execute; // @[dec.scala 138:34] - assign dec_trigger_io_trigger_pkt_any_1_m = tlu_io_trigger_pkt_any_1_m; // @[dec.scala 138:34] - assign dec_trigger_io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[dec.scala 138:34] - assign dec_trigger_io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[dec.scala 138:34] - assign dec_trigger_io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 138:34] - assign dec_trigger_io_trigger_pkt_any_2_execute = tlu_io_trigger_pkt_any_2_execute; // @[dec.scala 138:34] - assign dec_trigger_io_trigger_pkt_any_2_m = tlu_io_trigger_pkt_any_2_m; // @[dec.scala 138:34] - assign dec_trigger_io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[dec.scala 138:34] - assign dec_trigger_io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[dec.scala 138:34] - assign dec_trigger_io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 138:34] - assign dec_trigger_io_trigger_pkt_any_3_execute = tlu_io_trigger_pkt_any_3_execute; // @[dec.scala 138:34] - assign dec_trigger_io_trigger_pkt_any_3_m = tlu_io_trigger_pkt_any_3_m; // @[dec.scala 138:34] - assign dec_trigger_io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[dec.scala 138:34] - assign dec_trigger_io_dec_i0_pc_d = instbuff_io_ib_exu_dec_i0_pc_d; // @[dec.scala 137:30] + assign tlu_io_tlu_exu_exu_i0_br_hist_r = io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[dec.scala 205:18] + assign tlu_io_tlu_exu_exu_i0_br_error_r = io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[dec.scala 205:18] + assign tlu_io_tlu_exu_exu_i0_br_start_error_r = io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[dec.scala 205:18] + assign tlu_io_tlu_exu_exu_i0_br_valid_r = io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[dec.scala 205:18] + assign tlu_io_tlu_exu_exu_i0_br_mp_r = io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[dec.scala 205:18] + assign tlu_io_tlu_exu_exu_i0_br_middle_r = io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[dec.scala 205:18] + assign tlu_io_tlu_exu_exu_pmu_i0_br_misp = io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[dec.scala 205:18] + assign tlu_io_tlu_exu_exu_pmu_i0_br_ataken = io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[dec.scala 205:18] + assign tlu_io_tlu_exu_exu_pmu_i0_pc4 = io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[dec.scala 205:18] + assign tlu_io_tlu_exu_exu_npc_r = io_dec_exu_tlu_exu_exu_npc_r; // @[dec.scala 205:18] + assign tlu_io_tlu_dma_dma_pmu_dccm_read = io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[dec.scala 206:18] + assign tlu_io_tlu_dma_dma_pmu_dccm_write = io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[dec.scala 206:18] + assign tlu_io_tlu_dma_dma_pmu_any_read = io_dec_dma_tlu_dma_dma_pmu_any_read; // @[dec.scala 206:18] + assign tlu_io_tlu_dma_dma_pmu_any_write = io_dec_dma_tlu_dma_dma_pmu_any_write; // @[dec.scala 206:18] + assign tlu_io_tlu_dma_dma_dccm_stall_any = io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[dec.scala 206:18] + assign tlu_io_tlu_dma_dma_iccm_stall_any = io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[dec.scala 206:18] + assign tlu_io_active_clk = io_active_clk; // @[dec.scala 207:45] + assign tlu_io_free_clk = io_free_clk; // @[dec.scala 208:45] + assign tlu_io_scan_mode = io_scan_mode; // @[dec.scala 209:45] + assign tlu_io_rst_vec = io_rst_vec; // @[dec.scala 210:45] + assign tlu_io_nmi_int = io_nmi_int; // @[dec.scala 211:45] + assign tlu_io_nmi_vec = io_nmi_vec; // @[dec.scala 212:45] + assign tlu_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[dec.scala 213:45] + assign tlu_io_i_cpu_run_req = io_i_cpu_run_req; // @[dec.scala 214:45] + assign tlu_io_lsu_fastint_stall_any = io_lsu_fastint_stall_any; // @[dec.scala 215:45] + assign tlu_io_lsu_idle_any = io_lsu_idle_any; // @[dec.scala 246:45] + assign tlu_io_dec_pmu_instr_decoded = decode_io_dec_pmu_instr_decoded; // @[dec.scala 217:45] + assign tlu_io_dec_pmu_decode_stall = decode_io_dec_pmu_decode_stall; // @[dec.scala 218:45] + assign tlu_io_dec_pmu_presync_stall = decode_io_dec_pmu_presync_stall; // @[dec.scala 219:45] + assign tlu_io_dec_pmu_postsync_stall = decode_io_dec_pmu_postsync_stall; // @[dec.scala 220:45] + assign tlu_io_lsu_store_stall_any = io_lsu_store_stall_any; // @[dec.scala 221:45] + assign tlu_io_lsu_fir_addr = io_lsu_fir_addr; // @[dec.scala 225:45] + assign tlu_io_lsu_fir_error = io_lsu_fir_error; // @[dec.scala 226:45] + assign tlu_io_iccm_dma_sb_error = io_iccm_dma_sb_error; // @[dec.scala 227:45] + assign tlu_io_lsu_error_pkt_r_valid = io_lsu_error_pkt_r_valid; // @[dec.scala 228:45] + assign tlu_io_lsu_error_pkt_r_bits_single_ecc_error = io_lsu_error_pkt_r_bits_single_ecc_error; // @[dec.scala 228:45] + assign tlu_io_lsu_error_pkt_r_bits_inst_type = io_lsu_error_pkt_r_bits_inst_type; // @[dec.scala 228:45] + assign tlu_io_lsu_error_pkt_r_bits_exc_type = io_lsu_error_pkt_r_bits_exc_type; // @[dec.scala 228:45] + assign tlu_io_lsu_error_pkt_r_bits_mscause = io_lsu_error_pkt_r_bits_mscause; // @[dec.scala 228:45] + assign tlu_io_lsu_error_pkt_r_bits_addr = io_lsu_error_pkt_r_bits_addr; // @[dec.scala 228:45] + assign tlu_io_lsu_single_ecc_error_incr = io_lsu_single_ecc_error_incr; // @[dec.scala 229:45] + assign tlu_io_dec_pause_state = decode_io_dec_pause_state; // @[dec.scala 230:45] + assign tlu_io_dec_csr_wen_unq_d = decode_io_dec_csr_wen_unq_d; // @[dec.scala 231:45] + assign tlu_io_dec_csr_any_unq_d = decode_io_dec_csr_any_unq_d; // @[dec.scala 232:45] + assign tlu_io_dec_csr_rdaddr_d = decode_io_dec_csr_rdaddr_d; // @[dec.scala 233:45] + assign tlu_io_dec_csr_wen_r = decode_io_dec_csr_wen_r; // @[dec.scala 234:45] + assign tlu_io_dec_csr_wraddr_r = decode_io_dec_csr_wraddr_r; // @[dec.scala 235:45] + assign tlu_io_dec_csr_wrdata_r = decode_io_dec_csr_wrdata_r; // @[dec.scala 236:45] + assign tlu_io_dec_csr_stall_int_ff = decode_io_dec_csr_stall_int_ff; // @[dec.scala 237:45] + assign tlu_io_dec_tlu_i0_valid_r = decode_io_dec_tlu_i0_valid_r; // @[dec.scala 238:45] + assign tlu_io_dec_tlu_i0_pc_r = decode_io_dec_tlu_i0_pc_r; // @[dec.scala 239:45] + assign tlu_io_dec_tlu_packet_r_legal = decode_io_dec_tlu_packet_r_legal; // @[dec.scala 240:45] + assign tlu_io_dec_tlu_packet_r_icaf = decode_io_dec_tlu_packet_r_icaf; // @[dec.scala 240:45] + assign tlu_io_dec_tlu_packet_r_icaf_f1 = decode_io_dec_tlu_packet_r_icaf_f1; // @[dec.scala 240:45] + assign tlu_io_dec_tlu_packet_r_icaf_type = decode_io_dec_tlu_packet_r_icaf_type; // @[dec.scala 240:45] + assign tlu_io_dec_tlu_packet_r_fence_i = decode_io_dec_tlu_packet_r_fence_i; // @[dec.scala 240:45] + assign tlu_io_dec_tlu_packet_r_i0trigger = decode_io_dec_tlu_packet_r_i0trigger; // @[dec.scala 240:45] + assign tlu_io_dec_tlu_packet_r_pmu_i0_itype = decode_io_dec_tlu_packet_r_pmu_i0_itype; // @[dec.scala 240:45] + assign tlu_io_dec_tlu_packet_r_pmu_i0_br_unpred = decode_io_dec_tlu_packet_r_pmu_i0_br_unpred; // @[dec.scala 240:45] + assign tlu_io_dec_tlu_packet_r_pmu_divide = decode_io_dec_tlu_packet_r_pmu_divide; // @[dec.scala 240:45] + assign tlu_io_dec_tlu_packet_r_pmu_lsu_misaligned = decode_io_dec_tlu_packet_r_pmu_lsu_misaligned; // @[dec.scala 240:45] + assign tlu_io_dec_illegal_inst = decode_io_dec_illegal_inst; // @[dec.scala 241:45] + assign tlu_io_dec_i0_decode_d = decode_io_dec_aln_dec_i0_decode_d; // @[dec.scala 242:45] + assign tlu_io_exu_i0_br_way_r = io_exu_i0_br_way_r; // @[dec.scala 243:45] + assign tlu_io_dbg_halt_req = io_dbg_halt_req; // @[dec.scala 244:45] + assign tlu_io_dbg_resume_req = io_dbg_resume_req; // @[dec.scala 245:45] + assign tlu_io_dec_div_active = decode_io_dec_div_active; // @[dec.scala 247:45] + assign tlu_io_timer_int = io_timer_int; // @[dec.scala 252:45] + assign tlu_io_soft_int = io_soft_int; // @[dec.scala 253:45] + assign tlu_io_core_id = io_core_id; // @[dec.scala 254:45] + assign tlu_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[dec.scala 255:45] + assign tlu_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[dec.scala 256:45] + assign tlu_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[dec.scala 257:45] + assign tlu_io_ifu_pmu_instr_aligned = io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[dec.scala 216:45] + assign tlu_io_tlu_ifc_ifu_pmu_fetch_stall = io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[dec.scala 203:18] + assign tlu_io_tlu_mem_ifu_pmu_ic_miss = io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[dec.scala 202:18] + assign tlu_io_tlu_mem_ifu_pmu_ic_hit = io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[dec.scala 202:18] + assign tlu_io_tlu_mem_ifu_pmu_bus_error = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[dec.scala 202:18] + assign tlu_io_tlu_mem_ifu_pmu_bus_busy = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[dec.scala 202:18] + assign tlu_io_tlu_mem_ifu_pmu_bus_trxn = io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[dec.scala 202:18] + assign tlu_io_tlu_mem_ifu_ic_error_start = io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[dec.scala 202:18] + assign tlu_io_tlu_mem_ifu_iccm_rd_ecc_single_err = io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[dec.scala 202:18] + assign tlu_io_tlu_mem_ifu_ic_debug_rd_data = io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[dec.scala 202:18] + assign tlu_io_tlu_mem_ifu_ic_debug_rd_data_valid = io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[dec.scala 202:18] + assign tlu_io_tlu_mem_ifu_miss_state_idle = io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[dec.scala 202:18] + assign tlu_io_tlu_busbuff_lsu_pmu_bus_trxn = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[dec.scala 222:26] + assign tlu_io_tlu_busbuff_lsu_pmu_bus_misaligned = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[dec.scala 222:26] + assign tlu_io_tlu_busbuff_lsu_pmu_bus_error = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[dec.scala 222:26] + assign tlu_io_tlu_busbuff_lsu_pmu_bus_busy = io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[dec.scala 222:26] + assign tlu_io_tlu_busbuff_lsu_imprecise_error_load_any = io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[dec.scala 222:26] + assign tlu_io_tlu_busbuff_lsu_imprecise_error_store_any = io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[dec.scala 222:26] + assign tlu_io_tlu_busbuff_lsu_imprecise_error_addr_any = io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[dec.scala 222:26] + assign tlu_io_lsu_tlu_lsu_pmu_load_external_m = io_lsu_tlu_lsu_pmu_load_external_m; // @[dec.scala 223:14] + assign tlu_io_lsu_tlu_lsu_pmu_store_external_m = io_lsu_tlu_lsu_pmu_store_external_m; // @[dec.scala 223:14] + assign tlu_io_dec_pic_pic_claimid = io_dec_pic_pic_claimid; // @[dec.scala 224:14] + assign tlu_io_dec_pic_pic_pl = io_dec_pic_pic_pl; // @[dec.scala 224:14] + assign tlu_io_dec_pic_mhwakeup = io_dec_pic_mhwakeup; // @[dec.scala 224:14] + assign tlu_io_dec_pic_mexintpend = io_dec_pic_mexintpend; // @[dec.scala 224:14] + assign dec_trigger_io_trigger_pkt_any_0_select = tlu_io_trigger_pkt_any_0_select; // @[dec.scala 129:34] + assign dec_trigger_io_trigger_pkt_any_0_match_pkt = tlu_io_trigger_pkt_any_0_match_pkt; // @[dec.scala 129:34] + assign dec_trigger_io_trigger_pkt_any_0_execute = tlu_io_trigger_pkt_any_0_execute; // @[dec.scala 129:34] + assign dec_trigger_io_trigger_pkt_any_0_m = tlu_io_trigger_pkt_any_0_m; // @[dec.scala 129:34] + assign dec_trigger_io_trigger_pkt_any_0_tdata2 = tlu_io_trigger_pkt_any_0_tdata2; // @[dec.scala 129:34] + assign dec_trigger_io_trigger_pkt_any_1_select = tlu_io_trigger_pkt_any_1_select; // @[dec.scala 129:34] + assign dec_trigger_io_trigger_pkt_any_1_match_pkt = tlu_io_trigger_pkt_any_1_match_pkt; // @[dec.scala 129:34] + assign dec_trigger_io_trigger_pkt_any_1_execute = tlu_io_trigger_pkt_any_1_execute; // @[dec.scala 129:34] + assign dec_trigger_io_trigger_pkt_any_1_m = tlu_io_trigger_pkt_any_1_m; // @[dec.scala 129:34] + assign dec_trigger_io_trigger_pkt_any_1_tdata2 = tlu_io_trigger_pkt_any_1_tdata2; // @[dec.scala 129:34] + assign dec_trigger_io_trigger_pkt_any_2_select = tlu_io_trigger_pkt_any_2_select; // @[dec.scala 129:34] + assign dec_trigger_io_trigger_pkt_any_2_match_pkt = tlu_io_trigger_pkt_any_2_match_pkt; // @[dec.scala 129:34] + assign dec_trigger_io_trigger_pkt_any_2_execute = tlu_io_trigger_pkt_any_2_execute; // @[dec.scala 129:34] + assign dec_trigger_io_trigger_pkt_any_2_m = tlu_io_trigger_pkt_any_2_m; // @[dec.scala 129:34] + assign dec_trigger_io_trigger_pkt_any_2_tdata2 = tlu_io_trigger_pkt_any_2_tdata2; // @[dec.scala 129:34] + assign dec_trigger_io_trigger_pkt_any_3_select = tlu_io_trigger_pkt_any_3_select; // @[dec.scala 129:34] + assign dec_trigger_io_trigger_pkt_any_3_match_pkt = tlu_io_trigger_pkt_any_3_match_pkt; // @[dec.scala 129:34] + assign dec_trigger_io_trigger_pkt_any_3_execute = tlu_io_trigger_pkt_any_3_execute; // @[dec.scala 129:34] + assign dec_trigger_io_trigger_pkt_any_3_m = tlu_io_trigger_pkt_any_3_m; // @[dec.scala 129:34] + assign dec_trigger_io_trigger_pkt_any_3_tdata2 = tlu_io_trigger_pkt_any_3_tdata2; // @[dec.scala 129:34] + assign dec_trigger_io_dec_i0_pc_d = instbuff_io_ib_exu_dec_i0_pc_d; // @[dec.scala 128:30] endmodule module rvclkhdr_757( output io_l1clk, @@ -67976,7 +67964,6 @@ module lsu_bus_buffer( output io_tlu_busbuff_lsu_pmu_bus_error, output io_tlu_busbuff_lsu_pmu_bus_busy, input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, - input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, output io_tlu_busbuff_lsu_imprecise_error_load_any, output io_tlu_busbuff_lsu_imprecise_error_store_any, @@ -68139,9 +68126,9 @@ module lsu_bus_buffer( reg [31:0] _RAND_75; reg [31:0] _RAND_76; reg [31:0] _RAND_77; - reg [31:0] _RAND_78; + reg [63:0] _RAND_78; reg [31:0] _RAND_79; - reg [63:0] _RAND_80; + reg [31:0] _RAND_80; reg [31:0] _RAND_81; reg [31:0] _RAND_82; reg [31:0] _RAND_83; @@ -68166,8 +68153,6 @@ module lsu_bus_buffer( reg [31:0] _RAND_102; reg [31:0] _RAND_103; reg [31:0] _RAND_104; - reg [31:0] _RAND_105; - reg [31:0] _RAND_106; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[lib.scala 352:23] wire rvclkhdr_io_clk; // @[lib.scala 352:23] @@ -68281,85 +68266,85 @@ module lsu_bus_buffer( wire _T_87 = ld_addr_hitvec_lo_0 & buf_byteen_0[0]; // @[lsu_bus_buffer.scala 141:95] wire _T_89 = _T_87 & ldst_byteen_lo_m[0]; // @[lsu_bus_buffer.scala 141:114] wire [3:0] ld_byte_hitvec_lo_0 = {_T_101,_T_97,_T_93,_T_89}; // @[Cat.scala 29:58] - reg [3:0] buf_ageQ_3; // @[lsu_bus_buffer.scala 500:60] - wire _T_2621 = buf_state_3 == 3'h2; // @[lsu_bus_buffer.scala 412:93] + reg [3:0] buf_ageQ_3; // @[lsu_bus_buffer.scala 499:60] + wire _T_2621 = buf_state_3 == 3'h2; // @[lsu_bus_buffer.scala 411:93] wire _T_4107 = 3'h0 == buf_state_3; // @[Conditional.scala 37:30] wire _T_4130 = 3'h1 == buf_state_3; // @[Conditional.scala 37:30] wire _T_4134 = 3'h2 == buf_state_3; // @[Conditional.scala 37:30] reg [1:0] _T_1848; // @[Reg.scala 27:20] - wire [2:0] obuf_tag0 = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 352:13] - wire _T_4141 = obuf_tag0 == 3'h3; // @[lsu_bus_buffer.scala 455:48] + wire [2:0] obuf_tag0 = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 351:13] + wire _T_4141 = obuf_tag0 == 3'h3; // @[lsu_bus_buffer.scala 454:48] reg obuf_merge; // @[Reg.scala 27:20] reg [1:0] obuf_tag1; // @[Reg.scala 27:20] - wire [2:0] _GEN_358 = {{1'd0}, obuf_tag1}; // @[lsu_bus_buffer.scala 455:104] - wire _T_4142 = _GEN_358 == 3'h3; // @[lsu_bus_buffer.scala 455:104] - wire _T_4143 = obuf_merge & _T_4142; // @[lsu_bus_buffer.scala 455:91] - wire _T_4144 = _T_4141 | _T_4143; // @[lsu_bus_buffer.scala 455:77] - reg obuf_valid; // @[lsu_bus_buffer.scala 346:54] - wire _T_4145 = _T_4144 & obuf_valid; // @[lsu_bus_buffer.scala 455:135] - reg obuf_wr_enQ; // @[lsu_bus_buffer.scala 345:55] - wire _T_4146 = _T_4145 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 455:148] + wire [2:0] _GEN_358 = {{1'd0}, obuf_tag1}; // @[lsu_bus_buffer.scala 454:104] + wire _T_4142 = _GEN_358 == 3'h3; // @[lsu_bus_buffer.scala 454:104] + wire _T_4143 = obuf_merge & _T_4142; // @[lsu_bus_buffer.scala 454:91] + wire _T_4144 = _T_4141 | _T_4143; // @[lsu_bus_buffer.scala 454:77] + reg obuf_valid; // @[lsu_bus_buffer.scala 345:54] + wire _T_4145 = _T_4144 & obuf_valid; // @[lsu_bus_buffer.scala 454:135] + reg obuf_wr_enQ; // @[lsu_bus_buffer.scala 344:55] + wire _T_4146 = _T_4145 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 454:148] wire _GEN_280 = _T_4134 & _T_4146; // @[Conditional.scala 39:67] wire _GEN_293 = _T_4130 ? 1'h0 : _GEN_280; // @[Conditional.scala 39:67] wire buf_cmd_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_293; // @[Conditional.scala 40:58] - wire _T_2622 = _T_2621 & buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 412:103] - wire _T_2623 = ~_T_2622; // @[lsu_bus_buffer.scala 412:78] - wire _T_2624 = buf_ageQ_3[3] & _T_2623; // @[lsu_bus_buffer.scala 412:76] - wire _T_2616 = buf_state_2 == 3'h2; // @[lsu_bus_buffer.scala 412:93] + wire _T_2622 = _T_2621 & buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 411:103] + wire _T_2623 = ~_T_2622; // @[lsu_bus_buffer.scala 411:78] + wire _T_2624 = buf_ageQ_3[3] & _T_2623; // @[lsu_bus_buffer.scala 411:76] + wire _T_2616 = buf_state_2 == 3'h2; // @[lsu_bus_buffer.scala 411:93] wire _T_3914 = 3'h0 == buf_state_2; // @[Conditional.scala 37:30] wire _T_3937 = 3'h1 == buf_state_2; // @[Conditional.scala 37:30] wire _T_3941 = 3'h2 == buf_state_2; // @[Conditional.scala 37:30] - wire _T_3948 = obuf_tag0 == 3'h2; // @[lsu_bus_buffer.scala 455:48] - wire _T_3949 = _GEN_358 == 3'h2; // @[lsu_bus_buffer.scala 455:104] - wire _T_3950 = obuf_merge & _T_3949; // @[lsu_bus_buffer.scala 455:91] - wire _T_3951 = _T_3948 | _T_3950; // @[lsu_bus_buffer.scala 455:77] - wire _T_3952 = _T_3951 & obuf_valid; // @[lsu_bus_buffer.scala 455:135] - wire _T_3953 = _T_3952 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 455:148] + wire _T_3948 = obuf_tag0 == 3'h2; // @[lsu_bus_buffer.scala 454:48] + wire _T_3949 = _GEN_358 == 3'h2; // @[lsu_bus_buffer.scala 454:104] + wire _T_3950 = obuf_merge & _T_3949; // @[lsu_bus_buffer.scala 454:91] + wire _T_3951 = _T_3948 | _T_3950; // @[lsu_bus_buffer.scala 454:77] + wire _T_3952 = _T_3951 & obuf_valid; // @[lsu_bus_buffer.scala 454:135] + wire _T_3953 = _T_3952 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 454:148] wire _GEN_204 = _T_3941 & _T_3953; // @[Conditional.scala 39:67] wire _GEN_217 = _T_3937 ? 1'h0 : _GEN_204; // @[Conditional.scala 39:67] wire buf_cmd_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_217; // @[Conditional.scala 40:58] - wire _T_2617 = _T_2616 & buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 412:103] - wire _T_2618 = ~_T_2617; // @[lsu_bus_buffer.scala 412:78] - wire _T_2619 = buf_ageQ_3[2] & _T_2618; // @[lsu_bus_buffer.scala 412:76] - wire _T_2611 = buf_state_1 == 3'h2; // @[lsu_bus_buffer.scala 412:93] + wire _T_2617 = _T_2616 & buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 411:103] + wire _T_2618 = ~_T_2617; // @[lsu_bus_buffer.scala 411:78] + wire _T_2619 = buf_ageQ_3[2] & _T_2618; // @[lsu_bus_buffer.scala 411:76] + wire _T_2611 = buf_state_1 == 3'h2; // @[lsu_bus_buffer.scala 411:93] wire _T_3721 = 3'h0 == buf_state_1; // @[Conditional.scala 37:30] wire _T_3744 = 3'h1 == buf_state_1; // @[Conditional.scala 37:30] wire _T_3748 = 3'h2 == buf_state_1; // @[Conditional.scala 37:30] - wire _T_3755 = obuf_tag0 == 3'h1; // @[lsu_bus_buffer.scala 455:48] - wire _T_3756 = _GEN_358 == 3'h1; // @[lsu_bus_buffer.scala 455:104] - wire _T_3757 = obuf_merge & _T_3756; // @[lsu_bus_buffer.scala 455:91] - wire _T_3758 = _T_3755 | _T_3757; // @[lsu_bus_buffer.scala 455:77] - wire _T_3759 = _T_3758 & obuf_valid; // @[lsu_bus_buffer.scala 455:135] - wire _T_3760 = _T_3759 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 455:148] + wire _T_3755 = obuf_tag0 == 3'h1; // @[lsu_bus_buffer.scala 454:48] + wire _T_3756 = _GEN_358 == 3'h1; // @[lsu_bus_buffer.scala 454:104] + wire _T_3757 = obuf_merge & _T_3756; // @[lsu_bus_buffer.scala 454:91] + wire _T_3758 = _T_3755 | _T_3757; // @[lsu_bus_buffer.scala 454:77] + wire _T_3759 = _T_3758 & obuf_valid; // @[lsu_bus_buffer.scala 454:135] + wire _T_3760 = _T_3759 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 454:148] wire _GEN_128 = _T_3748 & _T_3760; // @[Conditional.scala 39:67] wire _GEN_141 = _T_3744 ? 1'h0 : _GEN_128; // @[Conditional.scala 39:67] wire buf_cmd_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_141; // @[Conditional.scala 40:58] - wire _T_2612 = _T_2611 & buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 412:103] - wire _T_2613 = ~_T_2612; // @[lsu_bus_buffer.scala 412:78] - wire _T_2614 = buf_ageQ_3[1] & _T_2613; // @[lsu_bus_buffer.scala 412:76] - wire _T_2606 = buf_state_0 == 3'h2; // @[lsu_bus_buffer.scala 412:93] + wire _T_2612 = _T_2611 & buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 411:103] + wire _T_2613 = ~_T_2612; // @[lsu_bus_buffer.scala 411:78] + wire _T_2614 = buf_ageQ_3[1] & _T_2613; // @[lsu_bus_buffer.scala 411:76] + wire _T_2606 = buf_state_0 == 3'h2; // @[lsu_bus_buffer.scala 411:93] wire _T_3528 = 3'h0 == buf_state_0; // @[Conditional.scala 37:30] wire _T_3551 = 3'h1 == buf_state_0; // @[Conditional.scala 37:30] wire _T_3555 = 3'h2 == buf_state_0; // @[Conditional.scala 37:30] - wire _T_3562 = obuf_tag0 == 3'h0; // @[lsu_bus_buffer.scala 455:48] - wire _T_3563 = _GEN_358 == 3'h0; // @[lsu_bus_buffer.scala 455:104] - wire _T_3564 = obuf_merge & _T_3563; // @[lsu_bus_buffer.scala 455:91] - wire _T_3565 = _T_3562 | _T_3564; // @[lsu_bus_buffer.scala 455:77] - wire _T_3566 = _T_3565 & obuf_valid; // @[lsu_bus_buffer.scala 455:135] - wire _T_3567 = _T_3566 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 455:148] + wire _T_3562 = obuf_tag0 == 3'h0; // @[lsu_bus_buffer.scala 454:48] + wire _T_3563 = _GEN_358 == 3'h0; // @[lsu_bus_buffer.scala 454:104] + wire _T_3564 = obuf_merge & _T_3563; // @[lsu_bus_buffer.scala 454:91] + wire _T_3565 = _T_3562 | _T_3564; // @[lsu_bus_buffer.scala 454:77] + wire _T_3566 = _T_3565 & obuf_valid; // @[lsu_bus_buffer.scala 454:135] + wire _T_3567 = _T_3566 & obuf_wr_enQ; // @[lsu_bus_buffer.scala 454:148] wire _GEN_52 = _T_3555 & _T_3567; // @[Conditional.scala 39:67] wire _GEN_65 = _T_3551 ? 1'h0 : _GEN_52; // @[Conditional.scala 39:67] wire buf_cmd_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_65; // @[Conditional.scala 40:58] - wire _T_2607 = _T_2606 & buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 412:103] - wire _T_2608 = ~_T_2607; // @[lsu_bus_buffer.scala 412:78] - wire _T_2609 = buf_ageQ_3[0] & _T_2608; // @[lsu_bus_buffer.scala 412:76] + wire _T_2607 = _T_2606 & buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 411:103] + wire _T_2608 = ~_T_2607; // @[lsu_bus_buffer.scala 411:78] + wire _T_2609 = buf_ageQ_3[0] & _T_2608; // @[lsu_bus_buffer.scala 411:76] wire [3:0] buf_age_3 = {_T_2624,_T_2619,_T_2614,_T_2609}; // @[Cat.scala 29:58] - wire _T_2723 = ~buf_age_3[2]; // @[lsu_bus_buffer.scala 413:89] - wire _T_2725 = _T_2723 & _T_19; // @[lsu_bus_buffer.scala 413:104] - wire _T_2717 = ~buf_age_3[1]; // @[lsu_bus_buffer.scala 413:89] - wire _T_2719 = _T_2717 & _T_12; // @[lsu_bus_buffer.scala 413:104] - wire _T_2711 = ~buf_age_3[0]; // @[lsu_bus_buffer.scala 413:89] - wire _T_2713 = _T_2711 & _T_5; // @[lsu_bus_buffer.scala 413:104] + wire _T_2723 = ~buf_age_3[2]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2725 = _T_2723 & _T_19; // @[lsu_bus_buffer.scala 412:104] + wire _T_2717 = ~buf_age_3[1]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2719 = _T_2717 & _T_12; // @[lsu_bus_buffer.scala 412:104] + wire _T_2711 = ~buf_age_3[0]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2713 = _T_2711 & _T_5; // @[lsu_bus_buffer.scala 412:104] wire [3:0] buf_age_younger_3 = {1'h0,_T_2725,_T_2719,_T_2713}; // @[Cat.scala 29:58] wire [3:0] _T_255 = ld_byte_hitvec_lo_0 & buf_age_younger_3; // @[lsu_bus_buffer.scala 146:122] wire _T_256 = |_T_255; // @[lsu_bus_buffer.scala 146:144] @@ -68378,54 +68363,54 @@ module lsu_bus_buffer( wire [3:0] ld_byte_ibuf_hit_lo = _T_522 & ldst_byteen_lo_m; // @[lsu_bus_buffer.scala 157:69] wire _T_260 = ~ld_byte_ibuf_hit_lo[0]; // @[lsu_bus_buffer.scala 146:150] wire _T_261 = _T_258 & _T_260; // @[lsu_bus_buffer.scala 146:148] - reg [3:0] buf_ageQ_2; // @[lsu_bus_buffer.scala 500:60] - wire _T_2601 = buf_ageQ_2[3] & _T_2623; // @[lsu_bus_buffer.scala 412:76] - wire _T_2596 = buf_ageQ_2[2] & _T_2618; // @[lsu_bus_buffer.scala 412:76] - wire _T_2591 = buf_ageQ_2[1] & _T_2613; // @[lsu_bus_buffer.scala 412:76] - wire _T_2586 = buf_ageQ_2[0] & _T_2608; // @[lsu_bus_buffer.scala 412:76] + reg [3:0] buf_ageQ_2; // @[lsu_bus_buffer.scala 499:60] + wire _T_2601 = buf_ageQ_2[3] & _T_2623; // @[lsu_bus_buffer.scala 411:76] + wire _T_2596 = buf_ageQ_2[2] & _T_2618; // @[lsu_bus_buffer.scala 411:76] + wire _T_2591 = buf_ageQ_2[1] & _T_2613; // @[lsu_bus_buffer.scala 411:76] + wire _T_2586 = buf_ageQ_2[0] & _T_2608; // @[lsu_bus_buffer.scala 411:76] wire [3:0] buf_age_2 = {_T_2601,_T_2596,_T_2591,_T_2586}; // @[Cat.scala 29:58] - wire _T_2702 = ~buf_age_2[3]; // @[lsu_bus_buffer.scala 413:89] - wire _T_2704 = _T_2702 & _T_26; // @[lsu_bus_buffer.scala 413:104] - wire _T_2690 = ~buf_age_2[1]; // @[lsu_bus_buffer.scala 413:89] - wire _T_2692 = _T_2690 & _T_12; // @[lsu_bus_buffer.scala 413:104] - wire _T_2684 = ~buf_age_2[0]; // @[lsu_bus_buffer.scala 413:89] - wire _T_2686 = _T_2684 & _T_5; // @[lsu_bus_buffer.scala 413:104] + wire _T_2702 = ~buf_age_2[3]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2704 = _T_2702 & _T_26; // @[lsu_bus_buffer.scala 412:104] + wire _T_2690 = ~buf_age_2[1]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2692 = _T_2690 & _T_12; // @[lsu_bus_buffer.scala 412:104] + wire _T_2684 = ~buf_age_2[0]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2686 = _T_2684 & _T_5; // @[lsu_bus_buffer.scala 412:104] wire [3:0] buf_age_younger_2 = {_T_2704,1'h0,_T_2692,_T_2686}; // @[Cat.scala 29:58] wire [3:0] _T_247 = ld_byte_hitvec_lo_0 & buf_age_younger_2; // @[lsu_bus_buffer.scala 146:122] wire _T_248 = |_T_247; // @[lsu_bus_buffer.scala 146:144] wire _T_249 = ~_T_248; // @[lsu_bus_buffer.scala 146:99] wire _T_250 = ld_byte_hitvec_lo_0[2] & _T_249; // @[lsu_bus_buffer.scala 146:97] wire _T_253 = _T_250 & _T_260; // @[lsu_bus_buffer.scala 146:148] - reg [3:0] buf_ageQ_1; // @[lsu_bus_buffer.scala 500:60] - wire _T_2578 = buf_ageQ_1[3] & _T_2623; // @[lsu_bus_buffer.scala 412:76] - wire _T_2573 = buf_ageQ_1[2] & _T_2618; // @[lsu_bus_buffer.scala 412:76] - wire _T_2568 = buf_ageQ_1[1] & _T_2613; // @[lsu_bus_buffer.scala 412:76] - wire _T_2563 = buf_ageQ_1[0] & _T_2608; // @[lsu_bus_buffer.scala 412:76] + reg [3:0] buf_ageQ_1; // @[lsu_bus_buffer.scala 499:60] + wire _T_2578 = buf_ageQ_1[3] & _T_2623; // @[lsu_bus_buffer.scala 411:76] + wire _T_2573 = buf_ageQ_1[2] & _T_2618; // @[lsu_bus_buffer.scala 411:76] + wire _T_2568 = buf_ageQ_1[1] & _T_2613; // @[lsu_bus_buffer.scala 411:76] + wire _T_2563 = buf_ageQ_1[0] & _T_2608; // @[lsu_bus_buffer.scala 411:76] wire [3:0] buf_age_1 = {_T_2578,_T_2573,_T_2568,_T_2563}; // @[Cat.scala 29:58] - wire _T_2675 = ~buf_age_1[3]; // @[lsu_bus_buffer.scala 413:89] - wire _T_2677 = _T_2675 & _T_26; // @[lsu_bus_buffer.scala 413:104] - wire _T_2669 = ~buf_age_1[2]; // @[lsu_bus_buffer.scala 413:89] - wire _T_2671 = _T_2669 & _T_19; // @[lsu_bus_buffer.scala 413:104] - wire _T_2657 = ~buf_age_1[0]; // @[lsu_bus_buffer.scala 413:89] - wire _T_2659 = _T_2657 & _T_5; // @[lsu_bus_buffer.scala 413:104] + wire _T_2675 = ~buf_age_1[3]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2677 = _T_2675 & _T_26; // @[lsu_bus_buffer.scala 412:104] + wire _T_2669 = ~buf_age_1[2]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2671 = _T_2669 & _T_19; // @[lsu_bus_buffer.scala 412:104] + wire _T_2657 = ~buf_age_1[0]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2659 = _T_2657 & _T_5; // @[lsu_bus_buffer.scala 412:104] wire [3:0] buf_age_younger_1 = {_T_2677,_T_2671,1'h0,_T_2659}; // @[Cat.scala 29:58] wire [3:0] _T_239 = ld_byte_hitvec_lo_0 & buf_age_younger_1; // @[lsu_bus_buffer.scala 146:122] wire _T_240 = |_T_239; // @[lsu_bus_buffer.scala 146:144] wire _T_241 = ~_T_240; // @[lsu_bus_buffer.scala 146:99] wire _T_242 = ld_byte_hitvec_lo_0[1] & _T_241; // @[lsu_bus_buffer.scala 146:97] wire _T_245 = _T_242 & _T_260; // @[lsu_bus_buffer.scala 146:148] - reg [3:0] buf_ageQ_0; // @[lsu_bus_buffer.scala 500:60] - wire _T_2555 = buf_ageQ_0[3] & _T_2623; // @[lsu_bus_buffer.scala 412:76] - wire _T_2550 = buf_ageQ_0[2] & _T_2618; // @[lsu_bus_buffer.scala 412:76] - wire _T_2545 = buf_ageQ_0[1] & _T_2613; // @[lsu_bus_buffer.scala 412:76] - wire _T_2540 = buf_ageQ_0[0] & _T_2608; // @[lsu_bus_buffer.scala 412:76] + reg [3:0] buf_ageQ_0; // @[lsu_bus_buffer.scala 499:60] + wire _T_2555 = buf_ageQ_0[3] & _T_2623; // @[lsu_bus_buffer.scala 411:76] + wire _T_2550 = buf_ageQ_0[2] & _T_2618; // @[lsu_bus_buffer.scala 411:76] + wire _T_2545 = buf_ageQ_0[1] & _T_2613; // @[lsu_bus_buffer.scala 411:76] + wire _T_2540 = buf_ageQ_0[0] & _T_2608; // @[lsu_bus_buffer.scala 411:76] wire [3:0] buf_age_0 = {_T_2555,_T_2550,_T_2545,_T_2540}; // @[Cat.scala 29:58] - wire _T_2648 = ~buf_age_0[3]; // @[lsu_bus_buffer.scala 413:89] - wire _T_2650 = _T_2648 & _T_26; // @[lsu_bus_buffer.scala 413:104] - wire _T_2642 = ~buf_age_0[2]; // @[lsu_bus_buffer.scala 413:89] - wire _T_2644 = _T_2642 & _T_19; // @[lsu_bus_buffer.scala 413:104] - wire _T_2636 = ~buf_age_0[1]; // @[lsu_bus_buffer.scala 413:89] - wire _T_2638 = _T_2636 & _T_12; // @[lsu_bus_buffer.scala 413:104] + wire _T_2648 = ~buf_age_0[3]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2650 = _T_2648 & _T_26; // @[lsu_bus_buffer.scala 412:104] + wire _T_2642 = ~buf_age_0[2]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2644 = _T_2642 & _T_19; // @[lsu_bus_buffer.scala 412:104] + wire _T_2636 = ~buf_age_0[1]; // @[lsu_bus_buffer.scala 412:89] + wire _T_2638 = _T_2636 & _T_12; // @[lsu_bus_buffer.scala 412:104] wire [3:0] buf_age_younger_0 = {_T_2650,_T_2644,_T_2638,1'h0}; // @[Cat.scala 29:58] wire [3:0] _T_231 = ld_byte_hitvec_lo_0 & buf_age_younger_0; // @[lsu_bus_buffer.scala 146:122] wire _T_232 = |_T_231; // @[lsu_bus_buffer.scala 146:144] @@ -68841,74 +68826,26 @@ module lsu_bus_buffer( wire _T_854 = ~ibuf_byp; // @[lsu_bus_buffer.scala 207:56] wire ibuf_wr_en = _T_853 & _T_854; // @[lsu_bus_buffer.scala 207:54] wire _T_855 = ~ibuf_wr_en; // @[lsu_bus_buffer.scala 209:36] - reg [2:0] ibuf_timer; // @[lsu_bus_buffer.scala 252:55] - wire _T_864 = ibuf_timer == 3'h7; // @[lsu_bus_buffer.scala 215:62] - wire _T_865 = ibuf_wr_en | _T_864; // @[lsu_bus_buffer.scala 215:48] - wire _T_929 = _T_853 & io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 234:54] - wire _T_930 = _T_929 & ibuf_valid; // @[lsu_bus_buffer.scala 234:80] - wire _T_931 = _T_930 & ibuf_write; // @[lsu_bus_buffer.scala 234:93] - wire _T_934 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[lsu_bus_buffer.scala 234:129] - wire _T_935 = _T_931 & _T_934; // @[lsu_bus_buffer.scala 234:106] - wire _T_936 = ~io_is_sideeffects_r; // @[lsu_bus_buffer.scala 234:152] - wire _T_937 = _T_935 & _T_936; // @[lsu_bus_buffer.scala 234:150] - wire _T_938 = ~io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 234:175] - wire ibuf_merge_en = _T_937 & _T_938; // @[lsu_bus_buffer.scala 234:173] - wire ibuf_merge_in = ~io_ldst_dual_r; // @[lsu_bus_buffer.scala 235:20] - wire _T_866 = ibuf_merge_en & ibuf_merge_in; // @[lsu_bus_buffer.scala 215:98] - wire _T_867 = ~_T_866; // @[lsu_bus_buffer.scala 215:82] - wire _T_868 = _T_865 & _T_867; // @[lsu_bus_buffer.scala 215:80] - wire _T_869 = _T_868 | ibuf_byp; // @[lsu_bus_buffer.scala 216:5] wire _T_857 = ~io_lsu_busreq_r; // @[lsu_bus_buffer.scala 210:44] wire _T_858 = io_lsu_busreq_m & _T_857; // @[lsu_bus_buffer.scala 210:42] wire _T_859 = _T_858 & ibuf_valid; // @[lsu_bus_buffer.scala 210:61] wire _T_862 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[lsu_bus_buffer.scala 210:120] wire _T_863 = io_lsu_pkt_m_bits_load | _T_862; // @[lsu_bus_buffer.scala 210:100] wire ibuf_force_drain = _T_859 & _T_863; // @[lsu_bus_buffer.scala 210:74] - wire _T_870 = _T_869 | ibuf_force_drain; // @[lsu_bus_buffer.scala 216:16] reg ibuf_sideeffect; // @[Reg.scala 27:20] - wire _T_871 = _T_870 | ibuf_sideeffect; // @[lsu_bus_buffer.scala 216:35] - wire _T_872 = ~ibuf_write; // @[lsu_bus_buffer.scala 216:55] - wire _T_873 = _T_871 | _T_872; // @[lsu_bus_buffer.scala 216:53] - wire _T_874 = _T_873 | io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_buffer.scala 216:67] - wire ibuf_drain_vld = ibuf_valid & _T_874; // @[lsu_bus_buffer.scala 215:32] - wire _T_856 = ibuf_drain_vld & _T_855; // @[lsu_bus_buffer.scala 209:34] + wire _T_856 = ibuf_valid & _T_855; // @[lsu_bus_buffer.scala 209:34] wire ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 209:49] - reg [1:0] WrPtr1_r; // @[lsu_bus_buffer.scala 616:49] - reg [1:0] WrPtr0_r; // @[lsu_bus_buffer.scala 615:49] + reg [1:0] WrPtr1_r; // @[lsu_bus_buffer.scala 615:49] + reg [1:0] WrPtr0_r; // @[lsu_bus_buffer.scala 614:49] reg [1:0] ibuf_tag; // @[Reg.scala 27:20] wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_bits_word,io_lsu_pkt_r_bits_half}; // @[Cat.scala 29:58] - wire [3:0] _T_881 = ibuf_byteen | ldst_byteen_lo_r; // @[lsu_bus_buffer.scala 225:77] - wire [7:0] _T_889 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 230:8] wire [7:0] _T_892 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[lsu_bus_buffer.scala 231:8] - wire [7:0] _T_893 = _T_866 ? _T_889 : _T_892; // @[lsu_bus_buffer.scala 229:46] - wire [7:0] _T_898 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 230:8] wire [7:0] _T_901 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[lsu_bus_buffer.scala 231:8] - wire [7:0] _T_902 = _T_866 ? _T_898 : _T_901; // @[lsu_bus_buffer.scala 229:46] - wire [7:0] _T_907 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 230:8] wire [7:0] _T_910 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[lsu_bus_buffer.scala 231:8] - wire [7:0] _T_911 = _T_866 ? _T_907 : _T_910; // @[lsu_bus_buffer.scala 229:46] - wire [7:0] _T_916 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 230:8] wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[lsu_bus_buffer.scala 231:8] - wire [7:0] _T_920 = _T_866 ? _T_916 : _T_919; // @[lsu_bus_buffer.scala 229:46] - wire [23:0] _T_922 = {_T_920,_T_911,_T_902}; // @[Cat.scala 29:58] - wire _T_923 = ibuf_timer < 3'h7; // @[lsu_bus_buffer.scala 232:59] - wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[lsu_bus_buffer.scala 232:93] - wire _T_941 = ~ibuf_merge_in; // @[lsu_bus_buffer.scala 236:65] - wire _T_942 = ibuf_merge_en & _T_941; // @[lsu_bus_buffer.scala 236:63] - wire _T_945 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[lsu_bus_buffer.scala 236:96] - wire _T_947 = _T_942 ? _T_945 : ibuf_byteen[0]; // @[lsu_bus_buffer.scala 236:48] - wire _T_952 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[lsu_bus_buffer.scala 236:96] - wire _T_954 = _T_942 ? _T_952 : ibuf_byteen[1]; // @[lsu_bus_buffer.scala 236:48] - wire _T_959 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[lsu_bus_buffer.scala 236:96] - wire _T_961 = _T_942 ? _T_959 : ibuf_byteen[2]; // @[lsu_bus_buffer.scala 236:48] - wire _T_966 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[lsu_bus_buffer.scala 236:96] - wire _T_968 = _T_942 ? _T_966 : ibuf_byteen[3]; // @[lsu_bus_buffer.scala 236:48] - wire [3:0] ibuf_byteen_out = {_T_968,_T_961,_T_954,_T_947}; // @[Cat.scala 29:58] - wire [7:0] _T_978 = _T_942 ? _T_889 : ibuf_data[7:0]; // @[lsu_bus_buffer.scala 237:45] - wire [7:0] _T_986 = _T_942 ? _T_898 : ibuf_data[15:8]; // @[lsu_bus_buffer.scala 237:45] - wire [7:0] _T_994 = _T_942 ? _T_907 : ibuf_data[23:16]; // @[lsu_bus_buffer.scala 237:45] - wire [7:0] _T_1002 = _T_942 ? _T_916 : ibuf_data[31:24]; // @[lsu_bus_buffer.scala 237:45] - wire [31:0] ibuf_data_out = {_T_1002,_T_994,_T_986,_T_978}; // @[Cat.scala 29:58] + wire [23:0] _T_922 = {_T_919,_T_910,_T_901}; // @[Cat.scala 29:58] + wire [3:0] ibuf_byteen_out = {ibuf_byteen[3],ibuf_byteen[2],ibuf_byteen[1],ibuf_byteen[0]}; // @[Cat.scala 29:58] + wire [31:0] ibuf_data_out = {ibuf_data[31:24],ibuf_data[23:16],ibuf_data[15:8],ibuf_data[7:0]}; // @[Cat.scala 29:58] wire _T_1005 = ibuf_wr_en | ibuf_valid; // @[lsu_bus_buffer.scala 239:58] wire _T_1006 = ~ibuf_rst; // @[lsu_bus_buffer.scala 239:93] reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20] @@ -68917,85 +68854,57 @@ module lsu_bus_buffer( reg ibuf_nomerge; // @[Reg.scala 27:20] reg ibuf_unsign; // @[Reg.scala 27:20] reg [1:0] ibuf_sz; // @[Reg.scala 27:20] - wire _T_4446 = buf_write[3] & _T_2621; // @[lsu_bus_buffer.scala 522:64] - wire _T_4447 = ~buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 522:91] - wire _T_4448 = _T_4446 & _T_4447; // @[lsu_bus_buffer.scala 522:89] - wire _T_4441 = buf_write[2] & _T_2616; // @[lsu_bus_buffer.scala 522:64] - wire _T_4442 = ~buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 522:91] - wire _T_4443 = _T_4441 & _T_4442; // @[lsu_bus_buffer.scala 522:89] - wire [1:0] _T_4449 = _T_4448 + _T_4443; // @[lsu_bus_buffer.scala 522:142] - wire _T_4436 = buf_write[1] & _T_2611; // @[lsu_bus_buffer.scala 522:64] - wire _T_4437 = ~buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 522:91] - wire _T_4438 = _T_4436 & _T_4437; // @[lsu_bus_buffer.scala 522:89] - wire [1:0] _GEN_362 = {{1'd0}, _T_4438}; // @[lsu_bus_buffer.scala 522:142] - wire [2:0] _T_4450 = _T_4449 + _GEN_362; // @[lsu_bus_buffer.scala 522:142] - wire _T_4431 = buf_write[0] & _T_2606; // @[lsu_bus_buffer.scala 522:64] - wire _T_4432 = ~buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 522:91] - wire _T_4433 = _T_4431 & _T_4432; // @[lsu_bus_buffer.scala 522:89] - wire [2:0] _GEN_363 = {{2'd0}, _T_4433}; // @[lsu_bus_buffer.scala 522:142] - wire [3:0] buf_numvld_wrcmd_any = _T_4450 + _GEN_363; // @[lsu_bus_buffer.scala 522:142] - wire _T_1016 = buf_numvld_wrcmd_any == 4'h1; // @[lsu_bus_buffer.scala 262:43] - wire _T_4463 = _T_2621 & _T_4447; // @[lsu_bus_buffer.scala 523:73] - wire _T_4460 = _T_2616 & _T_4442; // @[lsu_bus_buffer.scala 523:73] - wire [1:0] _T_4464 = _T_4463 + _T_4460; // @[lsu_bus_buffer.scala 523:126] - wire _T_4457 = _T_2611 & _T_4437; // @[lsu_bus_buffer.scala 523:73] - wire [1:0] _GEN_364 = {{1'd0}, _T_4457}; // @[lsu_bus_buffer.scala 523:126] - wire [2:0] _T_4465 = _T_4464 + _GEN_364; // @[lsu_bus_buffer.scala 523:126] - wire _T_4454 = _T_2606 & _T_4432; // @[lsu_bus_buffer.scala 523:73] - wire [2:0] _GEN_365 = {{2'd0}, _T_4454}; // @[lsu_bus_buffer.scala 523:126] - wire [3:0] buf_numvld_cmd_any = _T_4465 + _GEN_365; // @[lsu_bus_buffer.scala 523:126] + wire _T_4447 = ~buf_cmd_state_bus_en_3; // @[lsu_bus_buffer.scala 521:91] + wire _T_4442 = ~buf_cmd_state_bus_en_2; // @[lsu_bus_buffer.scala 521:91] + wire _T_4437 = ~buf_cmd_state_bus_en_1; // @[lsu_bus_buffer.scala 521:91] + wire _T_4432 = ~buf_cmd_state_bus_en_0; // @[lsu_bus_buffer.scala 521:91] + wire _T_4463 = _T_2621 & _T_4447; // @[lsu_bus_buffer.scala 522:73] + wire _T_4460 = _T_2616 & _T_4442; // @[lsu_bus_buffer.scala 522:73] + wire [1:0] _T_4464 = _T_4463 + _T_4460; // @[lsu_bus_buffer.scala 522:126] + wire _T_4457 = _T_2611 & _T_4437; // @[lsu_bus_buffer.scala 522:73] + wire [1:0] _GEN_364 = {{1'd0}, _T_4457}; // @[lsu_bus_buffer.scala 522:126] + wire [2:0] _T_4465 = _T_4464 + _GEN_364; // @[lsu_bus_buffer.scala 522:126] + wire _T_4454 = _T_2606 & _T_4432; // @[lsu_bus_buffer.scala 522:73] + wire [2:0] _GEN_365 = {{2'd0}, _T_4454}; // @[lsu_bus_buffer.scala 522:126] + wire [3:0] buf_numvld_cmd_any = _T_4465 + _GEN_365; // @[lsu_bus_buffer.scala 522:126] wire _T_1017 = buf_numvld_cmd_any == 4'h1; // @[lsu_bus_buffer.scala 262:72] - wire _T_1018 = _T_1016 & _T_1017; // @[lsu_bus_buffer.scala 262:51] - reg [2:0] obuf_wr_timer; // @[lsu_bus_buffer.scala 361:54] - wire _T_1019 = obuf_wr_timer != 3'h7; // @[lsu_bus_buffer.scala 262:97] - wire _T_1020 = _T_1018 & _T_1019; // @[lsu_bus_buffer.scala 262:80] - wire _T_1022 = _T_1020 & _T_938; // @[lsu_bus_buffer.scala 262:114] - wire _T_1979 = |buf_age_3; // @[lsu_bus_buffer.scala 378:58] - wire _T_1980 = ~_T_1979; // @[lsu_bus_buffer.scala 378:45] - wire _T_1982 = _T_1980 & _T_2621; // @[lsu_bus_buffer.scala 378:63] - wire _T_1984 = _T_1982 & _T_4447; // @[lsu_bus_buffer.scala 378:88] - wire _T_1973 = |buf_age_2; // @[lsu_bus_buffer.scala 378:58] - wire _T_1974 = ~_T_1973; // @[lsu_bus_buffer.scala 378:45] - wire _T_1976 = _T_1974 & _T_2616; // @[lsu_bus_buffer.scala 378:63] - wire _T_1978 = _T_1976 & _T_4442; // @[lsu_bus_buffer.scala 378:88] - wire _T_1967 = |buf_age_1; // @[lsu_bus_buffer.scala 378:58] - wire _T_1968 = ~_T_1967; // @[lsu_bus_buffer.scala 378:45] - wire _T_1970 = _T_1968 & _T_2611; // @[lsu_bus_buffer.scala 378:63] - wire _T_1972 = _T_1970 & _T_4437; // @[lsu_bus_buffer.scala 378:88] - wire _T_1961 = |buf_age_0; // @[lsu_bus_buffer.scala 378:58] - wire _T_1962 = ~_T_1961; // @[lsu_bus_buffer.scala 378:45] - wire _T_1964 = _T_1962 & _T_2606; // @[lsu_bus_buffer.scala 378:63] - wire _T_1966 = _T_1964 & _T_4432; // @[lsu_bus_buffer.scala 378:88] + wire _T_1979 = |buf_age_3; // @[lsu_bus_buffer.scala 377:58] + wire _T_1980 = ~_T_1979; // @[lsu_bus_buffer.scala 377:45] + wire _T_1982 = _T_1980 & _T_2621; // @[lsu_bus_buffer.scala 377:63] + wire _T_1984 = _T_1982 & _T_4447; // @[lsu_bus_buffer.scala 377:88] + wire _T_1973 = |buf_age_2; // @[lsu_bus_buffer.scala 377:58] + wire _T_1974 = ~_T_1973; // @[lsu_bus_buffer.scala 377:45] + wire _T_1976 = _T_1974 & _T_2616; // @[lsu_bus_buffer.scala 377:63] + wire _T_1978 = _T_1976 & _T_4442; // @[lsu_bus_buffer.scala 377:88] + wire _T_1967 = |buf_age_1; // @[lsu_bus_buffer.scala 377:58] + wire _T_1968 = ~_T_1967; // @[lsu_bus_buffer.scala 377:45] + wire _T_1970 = _T_1968 & _T_2611; // @[lsu_bus_buffer.scala 377:63] + wire _T_1972 = _T_1970 & _T_4437; // @[lsu_bus_buffer.scala 377:88] + wire _T_1961 = |buf_age_0; // @[lsu_bus_buffer.scala 377:58] + wire _T_1962 = ~_T_1961; // @[lsu_bus_buffer.scala 377:45] + wire _T_1964 = _T_1962 & _T_2606; // @[lsu_bus_buffer.scala 377:63] + wire _T_1966 = _T_1964 & _T_4432; // @[lsu_bus_buffer.scala 377:88] wire [3:0] CmdPtr0Dec = {_T_1984,_T_1978,_T_1972,_T_1966}; // @[Cat.scala 29:58] wire [7:0] _T_2054 = {4'h0,_T_1984,_T_1978,_T_1972,_T_1966}; // @[Cat.scala 29:58] - wire _T_2057 = _T_2054[4] | _T_2054[5]; // @[lsu_bus_buffer.scala 386:42] - wire _T_2059 = _T_2057 | _T_2054[6]; // @[lsu_bus_buffer.scala 386:48] - wire _T_2061 = _T_2059 | _T_2054[7]; // @[lsu_bus_buffer.scala 386:54] - wire _T_2064 = _T_2054[2] | _T_2054[3]; // @[lsu_bus_buffer.scala 386:67] - wire _T_2066 = _T_2064 | _T_2054[6]; // @[lsu_bus_buffer.scala 386:73] - wire _T_2068 = _T_2066 | _T_2054[7]; // @[lsu_bus_buffer.scala 386:79] - wire _T_2071 = _T_2054[1] | _T_2054[3]; // @[lsu_bus_buffer.scala 386:92] - wire _T_2073 = _T_2071 | _T_2054[5]; // @[lsu_bus_buffer.scala 386:98] - wire _T_2075 = _T_2073 | _T_2054[7]; // @[lsu_bus_buffer.scala 386:104] + wire _T_2057 = _T_2054[4] | _T_2054[5]; // @[lsu_bus_buffer.scala 385:42] + wire _T_2059 = _T_2057 | _T_2054[6]; // @[lsu_bus_buffer.scala 385:48] + wire _T_2061 = _T_2059 | _T_2054[7]; // @[lsu_bus_buffer.scala 385:54] + wire _T_2064 = _T_2054[2] | _T_2054[3]; // @[lsu_bus_buffer.scala 385:67] + wire _T_2066 = _T_2064 | _T_2054[6]; // @[lsu_bus_buffer.scala 385:73] + wire _T_2068 = _T_2066 | _T_2054[7]; // @[lsu_bus_buffer.scala 385:79] + wire _T_2071 = _T_2054[1] | _T_2054[3]; // @[lsu_bus_buffer.scala 385:92] + wire _T_2073 = _T_2071 | _T_2054[5]; // @[lsu_bus_buffer.scala 385:98] + wire _T_2075 = _T_2073 | _T_2054[7]; // @[lsu_bus_buffer.scala 385:104] wire [2:0] _T_2077 = {_T_2061,_T_2068,_T_2075}; // @[Cat.scala 29:58] - wire [1:0] CmdPtr0 = _T_2077[1:0]; // @[lsu_bus_buffer.scala 391:11] + wire [1:0] CmdPtr0 = _T_2077[1:0]; // @[lsu_bus_buffer.scala 390:11] wire _T_1023 = CmdPtr0 == 2'h0; // @[lsu_bus_buffer.scala 263:114] wire _T_1024 = CmdPtr0 == 2'h1; // @[lsu_bus_buffer.scala 263:114] wire _T_1025 = CmdPtr0 == 2'h2; // @[lsu_bus_buffer.scala 263:114] wire _T_1026 = CmdPtr0 == 2'h3; // @[lsu_bus_buffer.scala 263:114] reg buf_nomerge_0; // @[Reg.scala 27:20] - wire _T_1027 = _T_1023 & buf_nomerge_0; // @[Mux.scala 27:72] reg buf_nomerge_1; // @[Reg.scala 27:20] - wire _T_1028 = _T_1024 & buf_nomerge_1; // @[Mux.scala 27:72] reg buf_nomerge_2; // @[Reg.scala 27:20] - wire _T_1029 = _T_1025 & buf_nomerge_2; // @[Mux.scala 27:72] reg buf_nomerge_3; // @[Reg.scala 27:20] - wire _T_1030 = _T_1026 & buf_nomerge_3; // @[Mux.scala 27:72] - wire _T_1031 = _T_1027 | _T_1028; // @[Mux.scala 27:72] - wire _T_1032 = _T_1031 | _T_1029; // @[Mux.scala 27:72] - wire _T_1033 = _T_1032 | _T_1030; // @[Mux.scala 27:72] - wire _T_1035 = ~_T_1033; // @[lsu_bus_buffer.scala 263:31] - wire _T_1036 = _T_1022 & _T_1035; // @[lsu_bus_buffer.scala 263:29] reg _T_4330; // @[Reg.scala 27:20] reg _T_4327; // @[Reg.scala 27:20] reg _T_4324; // @[Reg.scala 27:20] @@ -69009,7 +68918,6 @@ module lsu_bus_buffer( wire _T_1050 = _T_1049 | _T_1047; // @[Mux.scala 27:72] wire _T_1051 = _T_1050 | _T_1048; // @[Mux.scala 27:72] wire _T_1053 = ~_T_1051; // @[lsu_bus_buffer.scala 264:5] - wire _T_1054 = _T_1036 & _T_1053; // @[lsu_bus_buffer.scala 263:140] wire _T_1065 = _T_858 & _T_852; // @[lsu_bus_buffer.scala 266:58] wire _T_1067 = _T_1065 & _T_1017; // @[lsu_bus_buffer.scala 266:72] wire [29:0] _T_1077 = _T_1023 ? buf_addr_0[31:2] : 30'h0; // @[Mux.scala 27:72] @@ -69021,46 +68929,40 @@ module lsu_bus_buffer( wire [29:0] _T_1083 = _T_1082 | _T_1080; // @[Mux.scala 27:72] wire _T_1085 = io_lsu_addr_m[31:2] != _T_1083; // @[lsu_bus_buffer.scala 266:123] wire obuf_force_wr_en = _T_1067 & _T_1085; // @[lsu_bus_buffer.scala 266:101] - wire _T_1055 = ~obuf_force_wr_en; // @[lsu_bus_buffer.scala 264:119] - wire obuf_wr_wait = _T_1054 & _T_1055; // @[lsu_bus_buffer.scala 264:117] - wire _T_1056 = |buf_numvld_cmd_any; // @[lsu_bus_buffer.scala 265:75] - wire _T_1057 = obuf_wr_timer < 3'h7; // @[lsu_bus_buffer.scala 265:95] - wire _T_1058 = _T_1056 & _T_1057; // @[lsu_bus_buffer.scala 265:79] - wire [2:0] _T_1060 = obuf_wr_timer + 3'h1; // @[lsu_bus_buffer.scala 265:123] - wire _T_4482 = buf_state_3 == 3'h1; // @[lsu_bus_buffer.scala 524:63] - wire _T_4486 = _T_4482 | _T_4463; // @[lsu_bus_buffer.scala 524:74] - wire _T_4477 = buf_state_2 == 3'h1; // @[lsu_bus_buffer.scala 524:63] - wire _T_4481 = _T_4477 | _T_4460; // @[lsu_bus_buffer.scala 524:74] - wire [1:0] _T_4487 = _T_4486 + _T_4481; // @[lsu_bus_buffer.scala 524:154] - wire _T_4472 = buf_state_1 == 3'h1; // @[lsu_bus_buffer.scala 524:63] - wire _T_4476 = _T_4472 | _T_4457; // @[lsu_bus_buffer.scala 524:74] - wire [1:0] _GEN_366 = {{1'd0}, _T_4476}; // @[lsu_bus_buffer.scala 524:154] - wire [2:0] _T_4488 = _T_4487 + _GEN_366; // @[lsu_bus_buffer.scala 524:154] - wire _T_4467 = buf_state_0 == 3'h1; // @[lsu_bus_buffer.scala 524:63] - wire _T_4471 = _T_4467 | _T_4454; // @[lsu_bus_buffer.scala 524:74] - wire [2:0] _GEN_367 = {{2'd0}, _T_4471}; // @[lsu_bus_buffer.scala 524:154] - wire [3:0] buf_numvld_pend_any = _T_4488 + _GEN_367; // @[lsu_bus_buffer.scala 524:154] + wire _T_4482 = buf_state_3 == 3'h1; // @[lsu_bus_buffer.scala 523:63] + wire _T_4486 = _T_4482 | _T_4463; // @[lsu_bus_buffer.scala 523:74] + wire _T_4477 = buf_state_2 == 3'h1; // @[lsu_bus_buffer.scala 523:63] + wire _T_4481 = _T_4477 | _T_4460; // @[lsu_bus_buffer.scala 523:74] + wire [1:0] _T_4487 = _T_4486 + _T_4481; // @[lsu_bus_buffer.scala 523:154] + wire _T_4472 = buf_state_1 == 3'h1; // @[lsu_bus_buffer.scala 523:63] + wire _T_4476 = _T_4472 | _T_4457; // @[lsu_bus_buffer.scala 523:74] + wire [1:0] _GEN_366 = {{1'd0}, _T_4476}; // @[lsu_bus_buffer.scala 523:154] + wire [2:0] _T_4488 = _T_4487 + _GEN_366; // @[lsu_bus_buffer.scala 523:154] + wire _T_4467 = buf_state_0 == 3'h1; // @[lsu_bus_buffer.scala 523:63] + wire _T_4471 = _T_4467 | _T_4454; // @[lsu_bus_buffer.scala 523:74] + wire [2:0] _GEN_367 = {{2'd0}, _T_4471}; // @[lsu_bus_buffer.scala 523:154] + wire [3:0] buf_numvld_pend_any = _T_4488 + _GEN_367; // @[lsu_bus_buffer.scala 523:154] wire _T_1087 = buf_numvld_pend_any == 4'h0; // @[lsu_bus_buffer.scala 268:53] wire _T_1088 = ibuf_byp & _T_1087; // @[lsu_bus_buffer.scala 268:31] wire _T_1089 = ~io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 268:64] wire _T_1090 = _T_1089 | io_no_dword_merge_r; // @[lsu_bus_buffer.scala 268:89] wire ibuf_buf_byp = _T_1088 & _T_1090; // @[lsu_bus_buffer.scala 268:61] wire _T_1091 = ibuf_buf_byp & io_lsu_commit_r; // @[lsu_bus_buffer.scala 283:32] - wire _T_4778 = buf_state_0 == 3'h3; // @[lsu_bus_buffer.scala 552:62] - wire _T_4780 = _T_4778 & buf_sideeffect[0]; // @[lsu_bus_buffer.scala 552:73] - wire _T_4781 = _T_4780 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 552:93] - wire _T_4782 = buf_state_1 == 3'h3; // @[lsu_bus_buffer.scala 552:62] - wire _T_4784 = _T_4782 & buf_sideeffect[1]; // @[lsu_bus_buffer.scala 552:73] - wire _T_4785 = _T_4784 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 552:93] - wire _T_4794 = _T_4781 | _T_4785; // @[lsu_bus_buffer.scala 552:153] - wire _T_4786 = buf_state_2 == 3'h3; // @[lsu_bus_buffer.scala 552:62] - wire _T_4788 = _T_4786 & buf_sideeffect[2]; // @[lsu_bus_buffer.scala 552:73] - wire _T_4789 = _T_4788 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 552:93] - wire _T_4795 = _T_4794 | _T_4789; // @[lsu_bus_buffer.scala 552:153] - wire _T_4790 = buf_state_3 == 3'h3; // @[lsu_bus_buffer.scala 552:62] - wire _T_4792 = _T_4790 & buf_sideeffect[3]; // @[lsu_bus_buffer.scala 552:73] - wire _T_4793 = _T_4792 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 552:93] - wire bus_sideeffect_pend = _T_4795 | _T_4793; // @[lsu_bus_buffer.scala 552:153] + wire _T_4778 = buf_state_0 == 3'h3; // @[lsu_bus_buffer.scala 551:62] + wire _T_4780 = _T_4778 & buf_sideeffect[0]; // @[lsu_bus_buffer.scala 551:73] + wire _T_4781 = _T_4780 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 551:93] + wire _T_4782 = buf_state_1 == 3'h3; // @[lsu_bus_buffer.scala 551:62] + wire _T_4784 = _T_4782 & buf_sideeffect[1]; // @[lsu_bus_buffer.scala 551:73] + wire _T_4785 = _T_4784 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 551:93] + wire _T_4794 = _T_4781 | _T_4785; // @[lsu_bus_buffer.scala 551:153] + wire _T_4786 = buf_state_2 == 3'h3; // @[lsu_bus_buffer.scala 551:62] + wire _T_4788 = _T_4786 & buf_sideeffect[2]; // @[lsu_bus_buffer.scala 551:73] + wire _T_4789 = _T_4788 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 551:93] + wire _T_4795 = _T_4794 | _T_4789; // @[lsu_bus_buffer.scala 551:153] + wire _T_4790 = buf_state_3 == 3'h3; // @[lsu_bus_buffer.scala 551:62] + wire _T_4792 = _T_4790 & buf_sideeffect[3]; // @[lsu_bus_buffer.scala 551:73] + wire _T_4793 = _T_4792 & io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_buffer.scala 551:93] + wire bus_sideeffect_pend = _T_4795 | _T_4793; // @[lsu_bus_buffer.scala 551:153] wire _T_1092 = io_is_sideeffects_r & bus_sideeffect_pend; // @[lsu_bus_buffer.scala 283:74] wire _T_1093 = ~_T_1092; // @[lsu_bus_buffer.scala 283:52] wire _T_1094 = _T_1091 & _T_1093; // @[lsu_bus_buffer.scala 283:50] @@ -69072,7 +68974,7 @@ module lsu_bus_buffer( wire [2:0] _T_1102 = _T_1026 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_1105 = _T_1104 | _T_1102; // @[Mux.scala 27:72] wire _T_1107 = _T_1105 == 3'h2; // @[lsu_bus_buffer.scala 284:36] - wire found_cmdptr0 = |CmdPtr0Dec; // @[lsu_bus_buffer.scala 383:31] + wire found_cmdptr0 = |CmdPtr0Dec; // @[lsu_bus_buffer.scala 382:31] wire _T_1108 = _T_1107 & found_cmdptr0; // @[lsu_bus_buffer.scala 284:47] wire [3:0] _T_1111 = {buf_cmd_state_bus_en_3,buf_cmd_state_bus_en_2,buf_cmd_state_bus_en_1,buf_cmd_state_bus_en_0}; // @[Cat.scala 29:58] wire _T_1120 = _T_1023 & _T_1111[0]; // @[Mux.scala 27:72] @@ -69122,37 +69024,37 @@ module lsu_bus_buffer( wire _T_1204 = ~_T_1202; // @[lsu_bus_buffer.scala 286:150] wire _T_1205 = _T_1187 & _T_1204; // @[lsu_bus_buffer.scala 286:148] wire _T_1206 = ~_T_1205; // @[lsu_bus_buffer.scala 286:8] - wire [3:0] _T_2020 = ~CmdPtr0Dec; // @[lsu_bus_buffer.scala 379:62] - wire [3:0] _T_2021 = buf_age_3 & _T_2020; // @[lsu_bus_buffer.scala 379:59] - wire _T_2022 = |_T_2021; // @[lsu_bus_buffer.scala 379:76] - wire _T_2023 = ~_T_2022; // @[lsu_bus_buffer.scala 379:45] - wire _T_2025 = ~CmdPtr0Dec[3]; // @[lsu_bus_buffer.scala 379:83] - wire _T_2026 = _T_2023 & _T_2025; // @[lsu_bus_buffer.scala 379:81] - wire _T_2028 = _T_2026 & _T_2621; // @[lsu_bus_buffer.scala 379:98] - wire _T_2030 = _T_2028 & _T_4447; // @[lsu_bus_buffer.scala 379:123] - wire [3:0] _T_2010 = buf_age_2 & _T_2020; // @[lsu_bus_buffer.scala 379:59] - wire _T_2011 = |_T_2010; // @[lsu_bus_buffer.scala 379:76] - wire _T_2012 = ~_T_2011; // @[lsu_bus_buffer.scala 379:45] - wire _T_2014 = ~CmdPtr0Dec[2]; // @[lsu_bus_buffer.scala 379:83] - wire _T_2015 = _T_2012 & _T_2014; // @[lsu_bus_buffer.scala 379:81] - wire _T_2017 = _T_2015 & _T_2616; // @[lsu_bus_buffer.scala 379:98] - wire _T_2019 = _T_2017 & _T_4442; // @[lsu_bus_buffer.scala 379:123] - wire [3:0] _T_1999 = buf_age_1 & _T_2020; // @[lsu_bus_buffer.scala 379:59] - wire _T_2000 = |_T_1999; // @[lsu_bus_buffer.scala 379:76] - wire _T_2001 = ~_T_2000; // @[lsu_bus_buffer.scala 379:45] - wire _T_2003 = ~CmdPtr0Dec[1]; // @[lsu_bus_buffer.scala 379:83] - wire _T_2004 = _T_2001 & _T_2003; // @[lsu_bus_buffer.scala 379:81] - wire _T_2006 = _T_2004 & _T_2611; // @[lsu_bus_buffer.scala 379:98] - wire _T_2008 = _T_2006 & _T_4437; // @[lsu_bus_buffer.scala 379:123] - wire [3:0] _T_1988 = buf_age_0 & _T_2020; // @[lsu_bus_buffer.scala 379:59] - wire _T_1989 = |_T_1988; // @[lsu_bus_buffer.scala 379:76] - wire _T_1990 = ~_T_1989; // @[lsu_bus_buffer.scala 379:45] - wire _T_1992 = ~CmdPtr0Dec[0]; // @[lsu_bus_buffer.scala 379:83] - wire _T_1993 = _T_1990 & _T_1992; // @[lsu_bus_buffer.scala 379:81] - wire _T_1995 = _T_1993 & _T_2606; // @[lsu_bus_buffer.scala 379:98] - wire _T_1997 = _T_1995 & _T_4432; // @[lsu_bus_buffer.scala 379:123] + wire [3:0] _T_2020 = ~CmdPtr0Dec; // @[lsu_bus_buffer.scala 378:62] + wire [3:0] _T_2021 = buf_age_3 & _T_2020; // @[lsu_bus_buffer.scala 378:59] + wire _T_2022 = |_T_2021; // @[lsu_bus_buffer.scala 378:76] + wire _T_2023 = ~_T_2022; // @[lsu_bus_buffer.scala 378:45] + wire _T_2025 = ~CmdPtr0Dec[3]; // @[lsu_bus_buffer.scala 378:83] + wire _T_2026 = _T_2023 & _T_2025; // @[lsu_bus_buffer.scala 378:81] + wire _T_2028 = _T_2026 & _T_2621; // @[lsu_bus_buffer.scala 378:98] + wire _T_2030 = _T_2028 & _T_4447; // @[lsu_bus_buffer.scala 378:123] + wire [3:0] _T_2010 = buf_age_2 & _T_2020; // @[lsu_bus_buffer.scala 378:59] + wire _T_2011 = |_T_2010; // @[lsu_bus_buffer.scala 378:76] + wire _T_2012 = ~_T_2011; // @[lsu_bus_buffer.scala 378:45] + wire _T_2014 = ~CmdPtr0Dec[2]; // @[lsu_bus_buffer.scala 378:83] + wire _T_2015 = _T_2012 & _T_2014; // @[lsu_bus_buffer.scala 378:81] + wire _T_2017 = _T_2015 & _T_2616; // @[lsu_bus_buffer.scala 378:98] + wire _T_2019 = _T_2017 & _T_4442; // @[lsu_bus_buffer.scala 378:123] + wire [3:0] _T_1999 = buf_age_1 & _T_2020; // @[lsu_bus_buffer.scala 378:59] + wire _T_2000 = |_T_1999; // @[lsu_bus_buffer.scala 378:76] + wire _T_2001 = ~_T_2000; // @[lsu_bus_buffer.scala 378:45] + wire _T_2003 = ~CmdPtr0Dec[1]; // @[lsu_bus_buffer.scala 378:83] + wire _T_2004 = _T_2001 & _T_2003; // @[lsu_bus_buffer.scala 378:81] + wire _T_2006 = _T_2004 & _T_2611; // @[lsu_bus_buffer.scala 378:98] + wire _T_2008 = _T_2006 & _T_4437; // @[lsu_bus_buffer.scala 378:123] + wire [3:0] _T_1988 = buf_age_0 & _T_2020; // @[lsu_bus_buffer.scala 378:59] + wire _T_1989 = |_T_1988; // @[lsu_bus_buffer.scala 378:76] + wire _T_1990 = ~_T_1989; // @[lsu_bus_buffer.scala 378:45] + wire _T_1992 = ~CmdPtr0Dec[0]; // @[lsu_bus_buffer.scala 378:83] + wire _T_1993 = _T_1990 & _T_1992; // @[lsu_bus_buffer.scala 378:81] + wire _T_1995 = _T_1993 & _T_2606; // @[lsu_bus_buffer.scala 378:98] + wire _T_1997 = _T_1995 & _T_4432; // @[lsu_bus_buffer.scala 378:123] wire [3:0] CmdPtr1Dec = {_T_2030,_T_2019,_T_2008,_T_1997}; // @[Cat.scala 29:58] - wire found_cmdptr1 = |CmdPtr1Dec; // @[lsu_bus_buffer.scala 384:31] + wire found_cmdptr1 = |CmdPtr1Dec; // @[lsu_bus_buffer.scala 383:31] wire _T_1207 = _T_1206 | found_cmdptr1; // @[lsu_bus_buffer.scala 286:181] wire [3:0] _T_1210 = {buf_nomerge_3,buf_nomerge_2,buf_nomerge_1,buf_nomerge_0}; // @[Cat.scala 29:58] wire _T_1219 = _T_1023 & _T_1210[0]; // @[Mux.scala 27:72] @@ -69167,66 +69069,64 @@ module lsu_bus_buffer( wire _T_1229 = _T_1148 & _T_1228; // @[lsu_bus_buffer.scala 285:164] wire _T_1230 = _T_1094 | _T_1229; // @[lsu_bus_buffer.scala 283:98] reg obuf_write; // @[Reg.scala 27:20] - reg obuf_cmd_done; // @[lsu_bus_buffer.scala 348:54] - reg obuf_data_done; // @[lsu_bus_buffer.scala 349:55] - wire _T_4853 = obuf_cmd_done | obuf_data_done; // @[lsu_bus_buffer.scala 556:54] - wire _T_4854 = obuf_cmd_done ? io_lsu_axi_w_ready : io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 556:75] - wire _T_4856 = _T_4853 ? _T_4854 : io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 556:39] - wire bus_cmd_ready = obuf_write ? _T_4856 : io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 556:23] + reg obuf_cmd_done; // @[lsu_bus_buffer.scala 347:54] + reg obuf_data_done; // @[lsu_bus_buffer.scala 348:55] + wire _T_4853 = obuf_cmd_done | obuf_data_done; // @[lsu_bus_buffer.scala 555:54] + wire _T_4854 = obuf_cmd_done ? io_lsu_axi_w_ready : io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 555:75] + wire _T_4856 = _T_4853 ? _T_4854 : io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 555:39] + wire bus_cmd_ready = obuf_write ? _T_4856 : io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 555:23] wire _T_1231 = ~obuf_valid; // @[lsu_bus_buffer.scala 287:48] wire _T_1232 = bus_cmd_ready | _T_1231; // @[lsu_bus_buffer.scala 287:46] reg obuf_nosend; // @[Reg.scala 27:20] wire _T_1233 = _T_1232 | obuf_nosend; // @[lsu_bus_buffer.scala 287:60] wire _T_1234 = _T_1230 & _T_1233; // @[lsu_bus_buffer.scala 287:29] - wire _T_1235 = ~obuf_wr_wait; // @[lsu_bus_buffer.scala 287:77] - wire _T_1236 = _T_1234 & _T_1235; // @[lsu_bus_buffer.scala 287:75] reg [31:0] obuf_addr; // @[lib.scala 358:16] - wire _T_4801 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[lsu_bus_buffer.scala 554:56] - wire _T_4802 = obuf_valid & _T_4801; // @[lsu_bus_buffer.scala 554:38] - wire _T_4804 = obuf_tag1 == 2'h0; // @[lsu_bus_buffer.scala 554:126] - wire _T_4805 = obuf_merge & _T_4804; // @[lsu_bus_buffer.scala 554:114] - wire _T_4806 = _T_3562 | _T_4805; // @[lsu_bus_buffer.scala 554:100] - wire _T_4807 = ~_T_4806; // @[lsu_bus_buffer.scala 554:80] - wire _T_4808 = _T_4802 & _T_4807; // @[lsu_bus_buffer.scala 554:78] + wire _T_4801 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[lsu_bus_buffer.scala 553:56] + wire _T_4802 = obuf_valid & _T_4801; // @[lsu_bus_buffer.scala 553:38] + wire _T_4804 = obuf_tag1 == 2'h0; // @[lsu_bus_buffer.scala 553:126] + wire _T_4805 = obuf_merge & _T_4804; // @[lsu_bus_buffer.scala 553:114] + wire _T_4806 = _T_3562 | _T_4805; // @[lsu_bus_buffer.scala 553:100] + wire _T_4807 = ~_T_4806; // @[lsu_bus_buffer.scala 553:80] + wire _T_4808 = _T_4802 & _T_4807; // @[lsu_bus_buffer.scala 553:78] wire _T_4845 = _T_4778 & _T_4808; // @[Mux.scala 27:72] - wire _T_4813 = obuf_addr[31:3] == buf_addr_1[31:3]; // @[lsu_bus_buffer.scala 554:56] - wire _T_4814 = obuf_valid & _T_4813; // @[lsu_bus_buffer.scala 554:38] - wire _T_4816 = obuf_tag1 == 2'h1; // @[lsu_bus_buffer.scala 554:126] - wire _T_4817 = obuf_merge & _T_4816; // @[lsu_bus_buffer.scala 554:114] - wire _T_4818 = _T_3755 | _T_4817; // @[lsu_bus_buffer.scala 554:100] - wire _T_4819 = ~_T_4818; // @[lsu_bus_buffer.scala 554:80] - wire _T_4820 = _T_4814 & _T_4819; // @[lsu_bus_buffer.scala 554:78] + wire _T_4813 = obuf_addr[31:3] == buf_addr_1[31:3]; // @[lsu_bus_buffer.scala 553:56] + wire _T_4814 = obuf_valid & _T_4813; // @[lsu_bus_buffer.scala 553:38] + wire _T_4816 = obuf_tag1 == 2'h1; // @[lsu_bus_buffer.scala 553:126] + wire _T_4817 = obuf_merge & _T_4816; // @[lsu_bus_buffer.scala 553:114] + wire _T_4818 = _T_3755 | _T_4817; // @[lsu_bus_buffer.scala 553:100] + wire _T_4819 = ~_T_4818; // @[lsu_bus_buffer.scala 553:80] + wire _T_4820 = _T_4814 & _T_4819; // @[lsu_bus_buffer.scala 553:78] wire _T_4846 = _T_4782 & _T_4820; // @[Mux.scala 27:72] wire _T_4849 = _T_4845 | _T_4846; // @[Mux.scala 27:72] - wire _T_4825 = obuf_addr[31:3] == buf_addr_2[31:3]; // @[lsu_bus_buffer.scala 554:56] - wire _T_4826 = obuf_valid & _T_4825; // @[lsu_bus_buffer.scala 554:38] - wire _T_4828 = obuf_tag1 == 2'h2; // @[lsu_bus_buffer.scala 554:126] - wire _T_4829 = obuf_merge & _T_4828; // @[lsu_bus_buffer.scala 554:114] - wire _T_4830 = _T_3948 | _T_4829; // @[lsu_bus_buffer.scala 554:100] - wire _T_4831 = ~_T_4830; // @[lsu_bus_buffer.scala 554:80] - wire _T_4832 = _T_4826 & _T_4831; // @[lsu_bus_buffer.scala 554:78] + wire _T_4825 = obuf_addr[31:3] == buf_addr_2[31:3]; // @[lsu_bus_buffer.scala 553:56] + wire _T_4826 = obuf_valid & _T_4825; // @[lsu_bus_buffer.scala 553:38] + wire _T_4828 = obuf_tag1 == 2'h2; // @[lsu_bus_buffer.scala 553:126] + wire _T_4829 = obuf_merge & _T_4828; // @[lsu_bus_buffer.scala 553:114] + wire _T_4830 = _T_3948 | _T_4829; // @[lsu_bus_buffer.scala 553:100] + wire _T_4831 = ~_T_4830; // @[lsu_bus_buffer.scala 553:80] + wire _T_4832 = _T_4826 & _T_4831; // @[lsu_bus_buffer.scala 553:78] wire _T_4847 = _T_4786 & _T_4832; // @[Mux.scala 27:72] wire _T_4850 = _T_4849 | _T_4847; // @[Mux.scala 27:72] - wire _T_4837 = obuf_addr[31:3] == buf_addr_3[31:3]; // @[lsu_bus_buffer.scala 554:56] - wire _T_4838 = obuf_valid & _T_4837; // @[lsu_bus_buffer.scala 554:38] - wire _T_4840 = obuf_tag1 == 2'h3; // @[lsu_bus_buffer.scala 554:126] - wire _T_4841 = obuf_merge & _T_4840; // @[lsu_bus_buffer.scala 554:114] - wire _T_4842 = _T_4141 | _T_4841; // @[lsu_bus_buffer.scala 554:100] - wire _T_4843 = ~_T_4842; // @[lsu_bus_buffer.scala 554:80] - wire _T_4844 = _T_4838 & _T_4843; // @[lsu_bus_buffer.scala 554:78] + wire _T_4837 = obuf_addr[31:3] == buf_addr_3[31:3]; // @[lsu_bus_buffer.scala 553:56] + wire _T_4838 = obuf_valid & _T_4837; // @[lsu_bus_buffer.scala 553:38] + wire _T_4840 = obuf_tag1 == 2'h3; // @[lsu_bus_buffer.scala 553:126] + wire _T_4841 = obuf_merge & _T_4840; // @[lsu_bus_buffer.scala 553:114] + wire _T_4842 = _T_4141 | _T_4841; // @[lsu_bus_buffer.scala 553:100] + wire _T_4843 = ~_T_4842; // @[lsu_bus_buffer.scala 553:80] + wire _T_4844 = _T_4838 & _T_4843; // @[lsu_bus_buffer.scala 553:78] wire _T_4848 = _T_4790 & _T_4844; // @[Mux.scala 27:72] wire bus_addr_match_pending = _T_4850 | _T_4848; // @[Mux.scala 27:72] wire _T_1239 = ~bus_addr_match_pending; // @[lsu_bus_buffer.scala 287:118] - wire _T_1240 = _T_1236 & _T_1239; // @[lsu_bus_buffer.scala 287:116] + wire _T_1240 = _T_1234 & _T_1239; // @[lsu_bus_buffer.scala 287:116] wire obuf_wr_en = _T_1240 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 287:142] wire _T_1242 = obuf_valid & obuf_nosend; // @[lsu_bus_buffer.scala 289:47] - wire bus_wcmd_sent = io_lsu_axi_aw_valid & io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 557:40] - wire _T_4860 = obuf_cmd_done | bus_wcmd_sent; // @[lsu_bus_buffer.scala 559:35] - wire bus_wdata_sent = io_lsu_axi_w_valid & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 558:40] - wire _T_4861 = obuf_data_done | bus_wdata_sent; // @[lsu_bus_buffer.scala 559:70] - wire _T_4862 = _T_4860 & _T_4861; // @[lsu_bus_buffer.scala 559:52] - wire _T_4863 = io_lsu_axi_ar_valid & io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 559:112] - wire bus_cmd_sent = _T_4862 | _T_4863; // @[lsu_bus_buffer.scala 559:89] + wire bus_wcmd_sent = io_lsu_axi_aw_valid & io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 556:40] + wire _T_4860 = obuf_cmd_done | bus_wcmd_sent; // @[lsu_bus_buffer.scala 558:35] + wire bus_wdata_sent = io_lsu_axi_w_valid & io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 557:40] + wire _T_4861 = obuf_data_done | bus_wdata_sent; // @[lsu_bus_buffer.scala 558:70] + wire _T_4862 = _T_4860 & _T_4861; // @[lsu_bus_buffer.scala 558:52] + wire _T_4863 = io_lsu_axi_ar_valid & io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 558:112] + wire bus_cmd_sent = _T_4862 | _T_4863; // @[lsu_bus_buffer.scala 558:89] wire _T_1243 = bus_cmd_sent | _T_1242; // @[lsu_bus_buffer.scala 289:33] wire _T_1244 = ~obuf_wr_en; // @[lsu_bus_buffer.scala 289:65] wire _T_1245 = _T_1243 & _T_1244; // @[lsu_bus_buffer.scala 289:63] @@ -69254,61 +69154,61 @@ module lsu_bus_buffer( wire [1:0] _T_1302 = _T_1301 | _T_1299; // @[Mux.scala 27:72] wire [1:0] obuf_sz_in = ibuf_buf_byp ? ibuf_sz_in : _T_1302; // @[lsu_bus_buffer.scala 295:23] wire [7:0] _T_2079 = {4'h0,_T_2030,_T_2019,_T_2008,_T_1997}; // @[Cat.scala 29:58] - wire _T_2082 = _T_2079[4] | _T_2079[5]; // @[lsu_bus_buffer.scala 386:42] - wire _T_2084 = _T_2082 | _T_2079[6]; // @[lsu_bus_buffer.scala 386:48] - wire _T_2086 = _T_2084 | _T_2079[7]; // @[lsu_bus_buffer.scala 386:54] - wire _T_2089 = _T_2079[2] | _T_2079[3]; // @[lsu_bus_buffer.scala 386:67] - wire _T_2091 = _T_2089 | _T_2079[6]; // @[lsu_bus_buffer.scala 386:73] - wire _T_2093 = _T_2091 | _T_2079[7]; // @[lsu_bus_buffer.scala 386:79] - wire _T_2096 = _T_2079[1] | _T_2079[3]; // @[lsu_bus_buffer.scala 386:92] - wire _T_2098 = _T_2096 | _T_2079[5]; // @[lsu_bus_buffer.scala 386:98] - wire _T_2100 = _T_2098 | _T_2079[7]; // @[lsu_bus_buffer.scala 386:104] + wire _T_2082 = _T_2079[4] | _T_2079[5]; // @[lsu_bus_buffer.scala 385:42] + wire _T_2084 = _T_2082 | _T_2079[6]; // @[lsu_bus_buffer.scala 385:48] + wire _T_2086 = _T_2084 | _T_2079[7]; // @[lsu_bus_buffer.scala 385:54] + wire _T_2089 = _T_2079[2] | _T_2079[3]; // @[lsu_bus_buffer.scala 385:67] + wire _T_2091 = _T_2089 | _T_2079[6]; // @[lsu_bus_buffer.scala 385:73] + wire _T_2093 = _T_2091 | _T_2079[7]; // @[lsu_bus_buffer.scala 385:79] + wire _T_2096 = _T_2079[1] | _T_2079[3]; // @[lsu_bus_buffer.scala 385:92] + wire _T_2098 = _T_2096 | _T_2079[5]; // @[lsu_bus_buffer.scala 385:98] + wire _T_2100 = _T_2098 | _T_2079[7]; // @[lsu_bus_buffer.scala 385:104] wire [2:0] _T_2102 = {_T_2086,_T_2093,_T_2100}; // @[Cat.scala 29:58] - wire [1:0] CmdPtr1 = _T_2102[1:0]; // @[lsu_bus_buffer.scala 393:11] - wire _T_1304 = obuf_wr_en | obuf_rst; // @[lsu_bus_buffer.scala 304:39] - wire _T_1305 = ~_T_1304; // @[lsu_bus_buffer.scala 304:26] - wire _T_1311 = obuf_sz_in == 2'h0; // @[lsu_bus_buffer.scala 308:72] - wire _T_1314 = ~obuf_addr_in[0]; // @[lsu_bus_buffer.scala 308:98] - wire _T_1315 = obuf_sz_in[0] & _T_1314; // @[lsu_bus_buffer.scala 308:96] - wire _T_1316 = _T_1311 | _T_1315; // @[lsu_bus_buffer.scala 308:79] - wire _T_1319 = |obuf_addr_in[1:0]; // @[lsu_bus_buffer.scala 308:153] - wire _T_1320 = ~_T_1319; // @[lsu_bus_buffer.scala 308:134] - wire _T_1321 = obuf_sz_in[1] & _T_1320; // @[lsu_bus_buffer.scala 308:132] - wire _T_1322 = _T_1316 | _T_1321; // @[lsu_bus_buffer.scala 308:116] - wire obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : _T_1322; // @[lsu_bus_buffer.scala 308:28] - wire _T_1339 = obuf_addr_in[31:3] == obuf_addr[31:3]; // @[lsu_bus_buffer.scala 322:40] - wire _T_1340 = _T_1339 & obuf_aligned_in; // @[lsu_bus_buffer.scala 322:60] + wire [1:0] CmdPtr1 = _T_2102[1:0]; // @[lsu_bus_buffer.scala 392:11] + wire _T_1304 = obuf_wr_en | obuf_rst; // @[lsu_bus_buffer.scala 303:39] + wire _T_1305 = ~_T_1304; // @[lsu_bus_buffer.scala 303:26] + wire _T_1311 = obuf_sz_in == 2'h0; // @[lsu_bus_buffer.scala 307:72] + wire _T_1314 = ~obuf_addr_in[0]; // @[lsu_bus_buffer.scala 307:98] + wire _T_1315 = obuf_sz_in[0] & _T_1314; // @[lsu_bus_buffer.scala 307:96] + wire _T_1316 = _T_1311 | _T_1315; // @[lsu_bus_buffer.scala 307:79] + wire _T_1319 = |obuf_addr_in[1:0]; // @[lsu_bus_buffer.scala 307:153] + wire _T_1320 = ~_T_1319; // @[lsu_bus_buffer.scala 307:134] + wire _T_1321 = obuf_sz_in[1] & _T_1320; // @[lsu_bus_buffer.scala 307:132] + wire _T_1322 = _T_1316 | _T_1321; // @[lsu_bus_buffer.scala 307:116] + wire obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : _T_1322; // @[lsu_bus_buffer.scala 307:28] + wire _T_1339 = obuf_addr_in[31:3] == obuf_addr[31:3]; // @[lsu_bus_buffer.scala 321:40] + wire _T_1340 = _T_1339 & obuf_aligned_in; // @[lsu_bus_buffer.scala 321:60] reg obuf_sideeffect; // @[Reg.scala 27:20] - wire _T_1341 = ~obuf_sideeffect; // @[lsu_bus_buffer.scala 322:80] - wire _T_1342 = _T_1340 & _T_1341; // @[lsu_bus_buffer.scala 322:78] - wire _T_1343 = ~obuf_write; // @[lsu_bus_buffer.scala 322:99] - wire _T_1344 = _T_1342 & _T_1343; // @[lsu_bus_buffer.scala 322:97] - wire _T_1345 = ~obuf_write_in; // @[lsu_bus_buffer.scala 322:113] - wire _T_1346 = _T_1344 & _T_1345; // @[lsu_bus_buffer.scala 322:111] - wire _T_1347 = ~io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_buffer.scala 322:130] - wire _T_1348 = _T_1346 & _T_1347; // @[lsu_bus_buffer.scala 322:128] - wire _T_1349 = ~obuf_nosend; // @[lsu_bus_buffer.scala 323:20] - wire _T_1350 = obuf_valid & _T_1349; // @[lsu_bus_buffer.scala 323:18] - reg obuf_rdrsp_pend; // @[lsu_bus_buffer.scala 350:56] - wire bus_rsp_read = io_lsu_axi_r_valid & io_lsu_axi_r_ready; // @[lsu_bus_buffer.scala 560:38] - reg [2:0] obuf_rdrsp_tag; // @[lsu_bus_buffer.scala 351:55] - wire _T_1351 = io_lsu_axi_r_bits_id == obuf_rdrsp_tag; // @[lsu_bus_buffer.scala 323:90] - wire _T_1352 = bus_rsp_read & _T_1351; // @[lsu_bus_buffer.scala 323:70] - wire _T_1353 = ~_T_1352; // @[lsu_bus_buffer.scala 323:55] - wire _T_1354 = obuf_rdrsp_pend & _T_1353; // @[lsu_bus_buffer.scala 323:53] - wire _T_1355 = _T_1350 | _T_1354; // @[lsu_bus_buffer.scala 323:34] - wire obuf_nosend_in = _T_1348 & _T_1355; // @[lsu_bus_buffer.scala 322:177] - wire _T_1323 = ~obuf_nosend_in; // @[lsu_bus_buffer.scala 316:44] - wire _T_1324 = obuf_wr_en & _T_1323; // @[lsu_bus_buffer.scala 316:42] - wire _T_1325 = ~_T_1324; // @[lsu_bus_buffer.scala 316:29] - wire _T_1326 = _T_1325 & obuf_rdrsp_pend; // @[lsu_bus_buffer.scala 316:61] - wire _T_1330 = _T_1326 & _T_1353; // @[lsu_bus_buffer.scala 316:79] - wire _T_1332 = bus_cmd_sent & _T_1343; // @[lsu_bus_buffer.scala 317:20] - wire _T_1333 = ~io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 317:37] - wire _T_1334 = _T_1332 & _T_1333; // @[lsu_bus_buffer.scala 317:35] + wire _T_1341 = ~obuf_sideeffect; // @[lsu_bus_buffer.scala 321:80] + wire _T_1342 = _T_1340 & _T_1341; // @[lsu_bus_buffer.scala 321:78] + wire _T_1343 = ~obuf_write; // @[lsu_bus_buffer.scala 321:99] + wire _T_1344 = _T_1342 & _T_1343; // @[lsu_bus_buffer.scala 321:97] + wire _T_1345 = ~obuf_write_in; // @[lsu_bus_buffer.scala 321:113] + wire _T_1346 = _T_1344 & _T_1345; // @[lsu_bus_buffer.scala 321:111] + wire _T_1347 = ~io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_buffer.scala 321:130] + wire _T_1348 = _T_1346 & _T_1347; // @[lsu_bus_buffer.scala 321:128] + wire _T_1349 = ~obuf_nosend; // @[lsu_bus_buffer.scala 322:20] + wire _T_1350 = obuf_valid & _T_1349; // @[lsu_bus_buffer.scala 322:18] + reg obuf_rdrsp_pend; // @[lsu_bus_buffer.scala 349:56] + wire bus_rsp_read = io_lsu_axi_r_valid & io_lsu_axi_r_ready; // @[lsu_bus_buffer.scala 559:38] + reg [2:0] obuf_rdrsp_tag; // @[lsu_bus_buffer.scala 350:55] + wire _T_1351 = io_lsu_axi_r_bits_id == obuf_rdrsp_tag; // @[lsu_bus_buffer.scala 322:90] + wire _T_1352 = bus_rsp_read & _T_1351; // @[lsu_bus_buffer.scala 322:70] + wire _T_1353 = ~_T_1352; // @[lsu_bus_buffer.scala 322:55] + wire _T_1354 = obuf_rdrsp_pend & _T_1353; // @[lsu_bus_buffer.scala 322:53] + wire _T_1355 = _T_1350 | _T_1354; // @[lsu_bus_buffer.scala 322:34] + wire obuf_nosend_in = _T_1348 & _T_1355; // @[lsu_bus_buffer.scala 321:177] + wire _T_1323 = ~obuf_nosend_in; // @[lsu_bus_buffer.scala 315:44] + wire _T_1324 = obuf_wr_en & _T_1323; // @[lsu_bus_buffer.scala 315:42] + wire _T_1325 = ~_T_1324; // @[lsu_bus_buffer.scala 315:29] + wire _T_1326 = _T_1325 & obuf_rdrsp_pend; // @[lsu_bus_buffer.scala 315:61] + wire _T_1330 = _T_1326 & _T_1353; // @[lsu_bus_buffer.scala 315:79] + wire _T_1332 = bus_cmd_sent & _T_1343; // @[lsu_bus_buffer.scala 316:20] + wire _T_1333 = ~io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 316:37] + wire _T_1334 = _T_1332 & _T_1333; // @[lsu_bus_buffer.scala 316:35] wire [7:0] _T_1358 = {ldst_byteen_lo_r,4'h0}; // @[Cat.scala 29:58] wire [7:0] _T_1359 = {4'h0,ldst_byteen_lo_r}; // @[Cat.scala 29:58] - wire [7:0] _T_1360 = io_lsu_addr_r[2] ? _T_1358 : _T_1359; // @[lsu_bus_buffer.scala 324:46] + wire [7:0] _T_1360 = io_lsu_addr_r[2] ? _T_1358 : _T_1359; // @[lsu_bus_buffer.scala 323:46] wire [3:0] _T_1379 = _T_1023 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_1380 = _T_1024 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_1381 = _T_1025 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72] @@ -69318,11 +69218,11 @@ module lsu_bus_buffer( wire [3:0] _T_1385 = _T_1384 | _T_1382; // @[Mux.scala 27:72] wire [7:0] _T_1387 = {_T_1385,4'h0}; // @[Cat.scala 29:58] wire [7:0] _T_1400 = {4'h0,_T_1385}; // @[Cat.scala 29:58] - wire [7:0] _T_1401 = _T_1289[2] ? _T_1387 : _T_1400; // @[lsu_bus_buffer.scala 325:8] - wire [7:0] obuf_byteen0_in = ibuf_buf_byp ? _T_1360 : _T_1401; // @[lsu_bus_buffer.scala 324:28] + wire [7:0] _T_1401 = _T_1289[2] ? _T_1387 : _T_1400; // @[lsu_bus_buffer.scala 324:8] + wire [7:0] obuf_byteen0_in = ibuf_buf_byp ? _T_1360 : _T_1401; // @[lsu_bus_buffer.scala 323:28] wire [7:0] _T_1403 = {ldst_byteen_hi_r,4'h0}; // @[Cat.scala 29:58] wire [7:0] _T_1404 = {4'h0,ldst_byteen_hi_r}; // @[Cat.scala 29:58] - wire [7:0] _T_1405 = io_end_addr_r[2] ? _T_1403 : _T_1404; // @[lsu_bus_buffer.scala 326:46] + wire [7:0] _T_1405 = io_end_addr_r[2] ? _T_1403 : _T_1404; // @[lsu_bus_buffer.scala 325:46] wire _T_1406 = CmdPtr1 == 2'h0; // @[lsu_bus_buffer.scala 58:123] wire _T_1407 = CmdPtr1 == 2'h1; // @[lsu_bus_buffer.scala 58:123] wire _T_1408 = CmdPtr1 == 2'h2; // @[lsu_bus_buffer.scala 58:123] @@ -69343,11 +69243,11 @@ module lsu_bus_buffer( wire [3:0] _T_1430 = _T_1429 | _T_1427; // @[Mux.scala 27:72] wire [7:0] _T_1432 = {_T_1430,4'h0}; // @[Cat.scala 29:58] wire [7:0] _T_1445 = {4'h0,_T_1430}; // @[Cat.scala 29:58] - wire [7:0] _T_1446 = _T_1416[2] ? _T_1432 : _T_1445; // @[lsu_bus_buffer.scala 327:8] - wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1405 : _T_1446; // @[lsu_bus_buffer.scala 326:28] + wire [7:0] _T_1446 = _T_1416[2] ? _T_1432 : _T_1445; // @[lsu_bus_buffer.scala 326:8] + wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1405 : _T_1446; // @[lsu_bus_buffer.scala 325:28] wire [63:0] _T_1448 = {store_data_lo_r,32'h0}; // @[Cat.scala 29:58] wire [63:0] _T_1449 = {32'h0,store_data_lo_r}; // @[Cat.scala 29:58] - wire [63:0] _T_1450 = io_lsu_addr_r[2] ? _T_1448 : _T_1449; // @[lsu_bus_buffer.scala 329:44] + wire [63:0] _T_1450 = io_lsu_addr_r[2] ? _T_1448 : _T_1449; // @[lsu_bus_buffer.scala 328:44] wire [31:0] _T_1469 = _T_1023 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1470 = _T_1024 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1471 = _T_1025 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] @@ -69357,11 +69257,11 @@ module lsu_bus_buffer( wire [31:0] _T_1475 = _T_1474 | _T_1472; // @[Mux.scala 27:72] wire [63:0] _T_1477 = {_T_1475,32'h0}; // @[Cat.scala 29:58] wire [63:0] _T_1490 = {32'h0,_T_1475}; // @[Cat.scala 29:58] - wire [63:0] _T_1491 = _T_1289[2] ? _T_1477 : _T_1490; // @[lsu_bus_buffer.scala 330:8] - wire [63:0] obuf_data0_in = ibuf_buf_byp ? _T_1450 : _T_1491; // @[lsu_bus_buffer.scala 329:26] + wire [63:0] _T_1491 = _T_1289[2] ? _T_1477 : _T_1490; // @[lsu_bus_buffer.scala 329:8] + wire [63:0] obuf_data0_in = ibuf_buf_byp ? _T_1450 : _T_1491; // @[lsu_bus_buffer.scala 328:26] wire [63:0] _T_1493 = {store_data_hi_r,32'h0}; // @[Cat.scala 29:58] wire [63:0] _T_1494 = {32'h0,store_data_hi_r}; // @[Cat.scala 29:58] - wire [63:0] _T_1495 = io_lsu_addr_r[2] ? _T_1493 : _T_1494; // @[lsu_bus_buffer.scala 331:44] + wire [63:0] _T_1495 = io_lsu_addr_r[2] ? _T_1493 : _T_1494; // @[lsu_bus_buffer.scala 330:44] wire [31:0] _T_1514 = _T_1406 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1515 = _T_1407 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1516 = _T_1408 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] @@ -69371,12 +69271,12 @@ module lsu_bus_buffer( wire [31:0] _T_1520 = _T_1519 | _T_1517; // @[Mux.scala 27:72] wire [63:0] _T_1522 = {_T_1520,32'h0}; // @[Cat.scala 29:58] wire [63:0] _T_1535 = {32'h0,_T_1520}; // @[Cat.scala 29:58] - wire [63:0] _T_1536 = _T_1416[2] ? _T_1522 : _T_1535; // @[lsu_bus_buffer.scala 332:8] - wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1495 : _T_1536; // @[lsu_bus_buffer.scala 331:26] - wire _T_1621 = CmdPtr0 != CmdPtr1; // @[lsu_bus_buffer.scala 338:30] - wire _T_1622 = _T_1621 & found_cmdptr0; // @[lsu_bus_buffer.scala 338:43] - wire _T_1623 = _T_1622 & found_cmdptr1; // @[lsu_bus_buffer.scala 338:59] - wire _T_1637 = _T_1623 & _T_1107; // @[lsu_bus_buffer.scala 338:75] + wire [63:0] _T_1536 = _T_1416[2] ? _T_1522 : _T_1535; // @[lsu_bus_buffer.scala 331:8] + wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1495 : _T_1536; // @[lsu_bus_buffer.scala 330:26] + wire _T_1621 = CmdPtr0 != CmdPtr1; // @[lsu_bus_buffer.scala 337:30] + wire _T_1622 = _T_1621 & found_cmdptr0; // @[lsu_bus_buffer.scala 337:43] + wire _T_1623 = _T_1622 & found_cmdptr1; // @[lsu_bus_buffer.scala 337:59] + wire _T_1637 = _T_1623 & _T_1107; // @[lsu_bus_buffer.scala 337:75] wire [2:0] _T_1642 = _T_1406 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_1643 = _T_1407 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_1646 = _T_1642 | _T_1643; // @[Mux.scala 27:72] @@ -69384,11 +69284,11 @@ module lsu_bus_buffer( wire [2:0] _T_1647 = _T_1646 | _T_1644; // @[Mux.scala 27:72] wire [2:0] _T_1645 = _T_1409 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72] wire [2:0] _T_1648 = _T_1647 | _T_1645; // @[Mux.scala 27:72] - wire _T_1650 = _T_1648 == 3'h2; // @[lsu_bus_buffer.scala 338:150] - wire _T_1651 = _T_1637 & _T_1650; // @[lsu_bus_buffer.scala 338:118] - wire _T_1672 = _T_1651 & _T_1128; // @[lsu_bus_buffer.scala 338:161] - wire _T_1690 = _T_1672 & _T_1053; // @[lsu_bus_buffer.scala 339:85] - wire _T_1792 = _T_1204 & _T_1166; // @[lsu_bus_buffer.scala 342:38] + wire _T_1650 = _T_1648 == 3'h2; // @[lsu_bus_buffer.scala 337:150] + wire _T_1651 = _T_1637 & _T_1650; // @[lsu_bus_buffer.scala 337:118] + wire _T_1672 = _T_1651 & _T_1128; // @[lsu_bus_buffer.scala 337:161] + wire _T_1690 = _T_1672 & _T_1053; // @[lsu_bus_buffer.scala 338:85] + wire _T_1792 = _T_1204 & _T_1166; // @[lsu_bus_buffer.scala 341:38] reg buf_dualhi_3; // @[Reg.scala 27:20] reg buf_dualhi_2; // @[Reg.scala 27:20] reg buf_dualhi_1; // @[Reg.scala 27:20] @@ -69401,224 +69301,223 @@ module lsu_bus_buffer( wire _T_1809 = _T_1808 | _T_1806; // @[Mux.scala 27:72] wire _T_1807 = _T_1026 & _T_1795[3]; // @[Mux.scala 27:72] wire _T_1810 = _T_1809 | _T_1807; // @[Mux.scala 27:72] - wire _T_1812 = ~_T_1810; // @[lsu_bus_buffer.scala 342:109] - wire _T_1813 = _T_1792 & _T_1812; // @[lsu_bus_buffer.scala 342:107] - wire _T_1833 = _T_1813 & _T_1185; // @[lsu_bus_buffer.scala 342:179] - wire _T_1835 = _T_1690 & _T_1833; // @[lsu_bus_buffer.scala 339:122] - wire _T_1836 = ibuf_buf_byp & ldst_samedw_r; // @[lsu_bus_buffer.scala 343:19] - wire _T_1837 = _T_1836 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 343:35] - wire obuf_merge_en = _T_1835 | _T_1837; // @[lsu_bus_buffer.scala 342:253] - wire _T_1539 = obuf_merge_en & obuf_byteen1_in[0]; // @[lsu_bus_buffer.scala 333:80] - wire _T_1540 = obuf_byteen0_in[0] | _T_1539; // @[lsu_bus_buffer.scala 333:63] - wire _T_1543 = obuf_merge_en & obuf_byteen1_in[1]; // @[lsu_bus_buffer.scala 333:80] - wire _T_1544 = obuf_byteen0_in[1] | _T_1543; // @[lsu_bus_buffer.scala 333:63] - wire _T_1547 = obuf_merge_en & obuf_byteen1_in[2]; // @[lsu_bus_buffer.scala 333:80] - wire _T_1548 = obuf_byteen0_in[2] | _T_1547; // @[lsu_bus_buffer.scala 333:63] - wire _T_1551 = obuf_merge_en & obuf_byteen1_in[3]; // @[lsu_bus_buffer.scala 333:80] - wire _T_1552 = obuf_byteen0_in[3] | _T_1551; // @[lsu_bus_buffer.scala 333:63] - wire _T_1555 = obuf_merge_en & obuf_byteen1_in[4]; // @[lsu_bus_buffer.scala 333:80] - wire _T_1556 = obuf_byteen0_in[4] | _T_1555; // @[lsu_bus_buffer.scala 333:63] - wire _T_1559 = obuf_merge_en & obuf_byteen1_in[5]; // @[lsu_bus_buffer.scala 333:80] - wire _T_1560 = obuf_byteen0_in[5] | _T_1559; // @[lsu_bus_buffer.scala 333:63] - wire _T_1563 = obuf_merge_en & obuf_byteen1_in[6]; // @[lsu_bus_buffer.scala 333:80] - wire _T_1564 = obuf_byteen0_in[6] | _T_1563; // @[lsu_bus_buffer.scala 333:63] - wire _T_1567 = obuf_merge_en & obuf_byteen1_in[7]; // @[lsu_bus_buffer.scala 333:80] - wire _T_1568 = obuf_byteen0_in[7] | _T_1567; // @[lsu_bus_buffer.scala 333:63] + wire _T_1812 = ~_T_1810; // @[lsu_bus_buffer.scala 341:109] + wire _T_1813 = _T_1792 & _T_1812; // @[lsu_bus_buffer.scala 341:107] + wire _T_1833 = _T_1813 & _T_1185; // @[lsu_bus_buffer.scala 341:179] + wire _T_1835 = _T_1690 & _T_1833; // @[lsu_bus_buffer.scala 338:122] + wire _T_1836 = ibuf_buf_byp & ldst_samedw_r; // @[lsu_bus_buffer.scala 342:19] + wire _T_1837 = _T_1836 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 342:35] + wire obuf_merge_en = _T_1835 | _T_1837; // @[lsu_bus_buffer.scala 341:253] + wire _T_1539 = obuf_merge_en & obuf_byteen1_in[0]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1540 = obuf_byteen0_in[0] | _T_1539; // @[lsu_bus_buffer.scala 332:63] + wire _T_1543 = obuf_merge_en & obuf_byteen1_in[1]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1544 = obuf_byteen0_in[1] | _T_1543; // @[lsu_bus_buffer.scala 332:63] + wire _T_1547 = obuf_merge_en & obuf_byteen1_in[2]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1548 = obuf_byteen0_in[2] | _T_1547; // @[lsu_bus_buffer.scala 332:63] + wire _T_1551 = obuf_merge_en & obuf_byteen1_in[3]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1552 = obuf_byteen0_in[3] | _T_1551; // @[lsu_bus_buffer.scala 332:63] + wire _T_1555 = obuf_merge_en & obuf_byteen1_in[4]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1556 = obuf_byteen0_in[4] | _T_1555; // @[lsu_bus_buffer.scala 332:63] + wire _T_1559 = obuf_merge_en & obuf_byteen1_in[5]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1560 = obuf_byteen0_in[5] | _T_1559; // @[lsu_bus_buffer.scala 332:63] + wire _T_1563 = obuf_merge_en & obuf_byteen1_in[6]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1564 = obuf_byteen0_in[6] | _T_1563; // @[lsu_bus_buffer.scala 332:63] + wire _T_1567 = obuf_merge_en & obuf_byteen1_in[7]; // @[lsu_bus_buffer.scala 332:80] + wire _T_1568 = obuf_byteen0_in[7] | _T_1567; // @[lsu_bus_buffer.scala 332:63] wire [7:0] obuf_byteen_in = {_T_1568,_T_1564,_T_1560,_T_1556,_T_1552,_T_1548,_T_1544,_T_1540}; // @[Cat.scala 29:58] - wire [7:0] _T_1579 = _T_1539 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[lsu_bus_buffer.scala 334:44] - wire [7:0] _T_1584 = _T_1543 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[lsu_bus_buffer.scala 334:44] - wire [7:0] _T_1589 = _T_1547 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[lsu_bus_buffer.scala 334:44] - wire [7:0] _T_1594 = _T_1551 ? obuf_data1_in[31:24] : obuf_data0_in[31:24]; // @[lsu_bus_buffer.scala 334:44] - wire [7:0] _T_1599 = _T_1555 ? obuf_data1_in[39:32] : obuf_data0_in[39:32]; // @[lsu_bus_buffer.scala 334:44] - wire [7:0] _T_1604 = _T_1559 ? obuf_data1_in[47:40] : obuf_data0_in[47:40]; // @[lsu_bus_buffer.scala 334:44] - wire [7:0] _T_1609 = _T_1563 ? obuf_data1_in[55:48] : obuf_data0_in[55:48]; // @[lsu_bus_buffer.scala 334:44] - wire [7:0] _T_1614 = _T_1567 ? obuf_data1_in[63:56] : obuf_data0_in[63:56]; // @[lsu_bus_buffer.scala 334:44] + wire [7:0] _T_1579 = _T_1539 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[lsu_bus_buffer.scala 333:44] + wire [7:0] _T_1584 = _T_1543 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[lsu_bus_buffer.scala 333:44] + wire [7:0] _T_1589 = _T_1547 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[lsu_bus_buffer.scala 333:44] + wire [7:0] _T_1594 = _T_1551 ? obuf_data1_in[31:24] : obuf_data0_in[31:24]; // @[lsu_bus_buffer.scala 333:44] + wire [7:0] _T_1599 = _T_1555 ? obuf_data1_in[39:32] : obuf_data0_in[39:32]; // @[lsu_bus_buffer.scala 333:44] + wire [7:0] _T_1604 = _T_1559 ? obuf_data1_in[47:40] : obuf_data0_in[47:40]; // @[lsu_bus_buffer.scala 333:44] + wire [7:0] _T_1609 = _T_1563 ? obuf_data1_in[55:48] : obuf_data0_in[55:48]; // @[lsu_bus_buffer.scala 333:44] + wire [7:0] _T_1614 = _T_1567 ? obuf_data1_in[63:56] : obuf_data0_in[63:56]; // @[lsu_bus_buffer.scala 333:44] wire [55:0] _T_1620 = {_T_1614,_T_1609,_T_1604,_T_1599,_T_1594,_T_1589,_T_1584}; // @[Cat.scala 29:58] - wire _T_1839 = obuf_wr_en | obuf_valid; // @[lsu_bus_buffer.scala 346:58] - wire _T_1840 = ~obuf_rst; // @[lsu_bus_buffer.scala 346:93] + wire _T_1839 = obuf_wr_en | obuf_valid; // @[lsu_bus_buffer.scala 345:58] + wire _T_1840 = ~obuf_rst; // @[lsu_bus_buffer.scala 345:93] reg [1:0] obuf_sz; // @[Reg.scala 27:20] reg [7:0] obuf_byteen; // @[Reg.scala 27:20] reg [63:0] obuf_data; // @[lib.scala 358:16] - wire _T_1853 = buf_state_0 == 3'h0; // @[lsu_bus_buffer.scala 364:65] - wire _T_1854 = ibuf_tag == 2'h0; // @[lsu_bus_buffer.scala 365:30] - wire _T_1855 = ibuf_valid & _T_1854; // @[lsu_bus_buffer.scala 365:19] - wire _T_1856 = WrPtr0_r == 2'h0; // @[lsu_bus_buffer.scala 366:18] - wire _T_1857 = WrPtr1_r == 2'h0; // @[lsu_bus_buffer.scala 366:57] - wire _T_1858 = io_ldst_dual_r & _T_1857; // @[lsu_bus_buffer.scala 366:45] - wire _T_1859 = _T_1856 | _T_1858; // @[lsu_bus_buffer.scala 366:27] - wire _T_1860 = io_lsu_busreq_r & _T_1859; // @[lsu_bus_buffer.scala 365:58] - wire _T_1861 = _T_1855 | _T_1860; // @[lsu_bus_buffer.scala 365:39] - wire _T_1862 = ~_T_1861; // @[lsu_bus_buffer.scala 365:5] - wire _T_1863 = _T_1853 & _T_1862; // @[lsu_bus_buffer.scala 364:76] - wire _T_1864 = buf_state_1 == 3'h0; // @[lsu_bus_buffer.scala 364:65] - wire _T_1865 = ibuf_tag == 2'h1; // @[lsu_bus_buffer.scala 365:30] - wire _T_1866 = ibuf_valid & _T_1865; // @[lsu_bus_buffer.scala 365:19] - wire _T_1867 = WrPtr0_r == 2'h1; // @[lsu_bus_buffer.scala 366:18] - wire _T_1868 = WrPtr1_r == 2'h1; // @[lsu_bus_buffer.scala 366:57] - wire _T_1869 = io_ldst_dual_r & _T_1868; // @[lsu_bus_buffer.scala 366:45] - wire _T_1870 = _T_1867 | _T_1869; // @[lsu_bus_buffer.scala 366:27] - wire _T_1871 = io_lsu_busreq_r & _T_1870; // @[lsu_bus_buffer.scala 365:58] - wire _T_1872 = _T_1866 | _T_1871; // @[lsu_bus_buffer.scala 365:39] - wire _T_1873 = ~_T_1872; // @[lsu_bus_buffer.scala 365:5] - wire _T_1874 = _T_1864 & _T_1873; // @[lsu_bus_buffer.scala 364:76] - wire _T_1875 = buf_state_2 == 3'h0; // @[lsu_bus_buffer.scala 364:65] - wire _T_1876 = ibuf_tag == 2'h2; // @[lsu_bus_buffer.scala 365:30] - wire _T_1877 = ibuf_valid & _T_1876; // @[lsu_bus_buffer.scala 365:19] - wire _T_1878 = WrPtr0_r == 2'h2; // @[lsu_bus_buffer.scala 366:18] - wire _T_1879 = WrPtr1_r == 2'h2; // @[lsu_bus_buffer.scala 366:57] - wire _T_1880 = io_ldst_dual_r & _T_1879; // @[lsu_bus_buffer.scala 366:45] - wire _T_1881 = _T_1878 | _T_1880; // @[lsu_bus_buffer.scala 366:27] - wire _T_1882 = io_lsu_busreq_r & _T_1881; // @[lsu_bus_buffer.scala 365:58] - wire _T_1883 = _T_1877 | _T_1882; // @[lsu_bus_buffer.scala 365:39] - wire _T_1884 = ~_T_1883; // @[lsu_bus_buffer.scala 365:5] - wire _T_1885 = _T_1875 & _T_1884; // @[lsu_bus_buffer.scala 364:76] - wire _T_1886 = buf_state_3 == 3'h0; // @[lsu_bus_buffer.scala 364:65] - wire _T_1887 = ibuf_tag == 2'h3; // @[lsu_bus_buffer.scala 365:30] - wire _T_1889 = WrPtr0_r == 2'h3; // @[lsu_bus_buffer.scala 366:18] - wire _T_1890 = WrPtr1_r == 2'h3; // @[lsu_bus_buffer.scala 366:57] + wire _T_1853 = buf_state_0 == 3'h0; // @[lsu_bus_buffer.scala 363:65] + wire _T_1854 = ibuf_tag == 2'h0; // @[lsu_bus_buffer.scala 364:30] + wire _T_1855 = ibuf_valid & _T_1854; // @[lsu_bus_buffer.scala 364:19] + wire _T_1856 = WrPtr0_r == 2'h0; // @[lsu_bus_buffer.scala 365:18] + wire _T_1857 = WrPtr1_r == 2'h0; // @[lsu_bus_buffer.scala 365:57] + wire _T_1858 = io_ldst_dual_r & _T_1857; // @[lsu_bus_buffer.scala 365:45] + wire _T_1859 = _T_1856 | _T_1858; // @[lsu_bus_buffer.scala 365:27] + wire _T_1860 = io_lsu_busreq_r & _T_1859; // @[lsu_bus_buffer.scala 364:58] + wire _T_1861 = _T_1855 | _T_1860; // @[lsu_bus_buffer.scala 364:39] + wire _T_1862 = ~_T_1861; // @[lsu_bus_buffer.scala 364:5] + wire _T_1863 = _T_1853 & _T_1862; // @[lsu_bus_buffer.scala 363:76] + wire _T_1864 = buf_state_1 == 3'h0; // @[lsu_bus_buffer.scala 363:65] + wire _T_1865 = ibuf_tag == 2'h1; // @[lsu_bus_buffer.scala 364:30] + wire _T_1866 = ibuf_valid & _T_1865; // @[lsu_bus_buffer.scala 364:19] + wire _T_1867 = WrPtr0_r == 2'h1; // @[lsu_bus_buffer.scala 365:18] + wire _T_1868 = WrPtr1_r == 2'h1; // @[lsu_bus_buffer.scala 365:57] + wire _T_1869 = io_ldst_dual_r & _T_1868; // @[lsu_bus_buffer.scala 365:45] + wire _T_1870 = _T_1867 | _T_1869; // @[lsu_bus_buffer.scala 365:27] + wire _T_1871 = io_lsu_busreq_r & _T_1870; // @[lsu_bus_buffer.scala 364:58] + wire _T_1872 = _T_1866 | _T_1871; // @[lsu_bus_buffer.scala 364:39] + wire _T_1873 = ~_T_1872; // @[lsu_bus_buffer.scala 364:5] + wire _T_1874 = _T_1864 & _T_1873; // @[lsu_bus_buffer.scala 363:76] + wire _T_1875 = buf_state_2 == 3'h0; // @[lsu_bus_buffer.scala 363:65] + wire _T_1876 = ibuf_tag == 2'h2; // @[lsu_bus_buffer.scala 364:30] + wire _T_1877 = ibuf_valid & _T_1876; // @[lsu_bus_buffer.scala 364:19] + wire _T_1878 = WrPtr0_r == 2'h2; // @[lsu_bus_buffer.scala 365:18] + wire _T_1879 = WrPtr1_r == 2'h2; // @[lsu_bus_buffer.scala 365:57] + wire _T_1880 = io_ldst_dual_r & _T_1879; // @[lsu_bus_buffer.scala 365:45] + wire _T_1881 = _T_1878 | _T_1880; // @[lsu_bus_buffer.scala 365:27] + wire _T_1882 = io_lsu_busreq_r & _T_1881; // @[lsu_bus_buffer.scala 364:58] + wire _T_1883 = _T_1877 | _T_1882; // @[lsu_bus_buffer.scala 364:39] + wire _T_1884 = ~_T_1883; // @[lsu_bus_buffer.scala 364:5] + wire _T_1885 = _T_1875 & _T_1884; // @[lsu_bus_buffer.scala 363:76] + wire _T_1886 = buf_state_3 == 3'h0; // @[lsu_bus_buffer.scala 363:65] + wire _T_1887 = ibuf_tag == 2'h3; // @[lsu_bus_buffer.scala 364:30] + wire _T_1888 = ibuf_valid & _T_1887; // @[lsu_bus_buffer.scala 364:19] + wire _T_1889 = WrPtr0_r == 2'h3; // @[lsu_bus_buffer.scala 365:18] + wire _T_1890 = WrPtr1_r == 2'h3; // @[lsu_bus_buffer.scala 365:57] wire [1:0] _T_1898 = _T_1885 ? 2'h2 : 2'h3; // @[Mux.scala 98:16] wire [1:0] _T_1899 = _T_1874 ? 2'h1 : _T_1898; // @[Mux.scala 98:16] wire [1:0] WrPtr0_m = _T_1863 ? 2'h0 : _T_1899; // @[Mux.scala 98:16] - wire _T_1904 = WrPtr0_m == 2'h0; // @[lsu_bus_buffer.scala 371:33] - wire _T_1905 = io_lsu_busreq_m & _T_1904; // @[lsu_bus_buffer.scala 371:22] - wire _T_1906 = _T_1855 | _T_1905; // @[lsu_bus_buffer.scala 370:112] - wire _T_1912 = _T_1906 | _T_1860; // @[lsu_bus_buffer.scala 371:42] - wire _T_1913 = ~_T_1912; // @[lsu_bus_buffer.scala 370:78] - wire _T_1914 = _T_1853 & _T_1913; // @[lsu_bus_buffer.scala 370:76] - wire _T_1918 = WrPtr0_m == 2'h1; // @[lsu_bus_buffer.scala 371:33] - wire _T_1919 = io_lsu_busreq_m & _T_1918; // @[lsu_bus_buffer.scala 371:22] - wire _T_1920 = _T_1866 | _T_1919; // @[lsu_bus_buffer.scala 370:112] - wire _T_1926 = _T_1920 | _T_1871; // @[lsu_bus_buffer.scala 371:42] - wire _T_1927 = ~_T_1926; // @[lsu_bus_buffer.scala 370:78] - wire _T_1928 = _T_1864 & _T_1927; // @[lsu_bus_buffer.scala 370:76] - wire _T_1932 = WrPtr0_m == 2'h2; // @[lsu_bus_buffer.scala 371:33] - wire _T_1933 = io_lsu_busreq_m & _T_1932; // @[lsu_bus_buffer.scala 371:22] - wire _T_1934 = _T_1877 | _T_1933; // @[lsu_bus_buffer.scala 370:112] - wire _T_1940 = _T_1934 | _T_1882; // @[lsu_bus_buffer.scala 371:42] - wire _T_1941 = ~_T_1940; // @[lsu_bus_buffer.scala 370:78] - wire _T_1942 = _T_1875 & _T_1941; // @[lsu_bus_buffer.scala 370:76] - reg [3:0] buf_rspageQ_0; // @[lsu_bus_buffer.scala 501:63] - wire _T_2746 = buf_state_3 == 3'h5; // @[lsu_bus_buffer.scala 414:102] - wire _T_2747 = buf_rspageQ_0[3] & _T_2746; // @[lsu_bus_buffer.scala 414:87] - wire _T_2743 = buf_state_2 == 3'h5; // @[lsu_bus_buffer.scala 414:102] - wire _T_2744 = buf_rspageQ_0[2] & _T_2743; // @[lsu_bus_buffer.scala 414:87] - wire _T_2740 = buf_state_1 == 3'h5; // @[lsu_bus_buffer.scala 414:102] - wire _T_2741 = buf_rspageQ_0[1] & _T_2740; // @[lsu_bus_buffer.scala 414:87] - wire _T_2737 = buf_state_0 == 3'h5; // @[lsu_bus_buffer.scala 414:102] - wire _T_2738 = buf_rspageQ_0[0] & _T_2737; // @[lsu_bus_buffer.scala 414:87] + wire _T_1904 = WrPtr0_m == 2'h0; // @[lsu_bus_buffer.scala 370:33] + wire _T_1905 = io_lsu_busreq_m & _T_1904; // @[lsu_bus_buffer.scala 370:22] + wire _T_1906 = _T_1855 | _T_1905; // @[lsu_bus_buffer.scala 369:112] + wire _T_1912 = _T_1906 | _T_1860; // @[lsu_bus_buffer.scala 370:42] + wire _T_1913 = ~_T_1912; // @[lsu_bus_buffer.scala 369:78] + wire _T_1914 = _T_1853 & _T_1913; // @[lsu_bus_buffer.scala 369:76] + wire _T_1918 = WrPtr0_m == 2'h1; // @[lsu_bus_buffer.scala 370:33] + wire _T_1919 = io_lsu_busreq_m & _T_1918; // @[lsu_bus_buffer.scala 370:22] + wire _T_1920 = _T_1866 | _T_1919; // @[lsu_bus_buffer.scala 369:112] + wire _T_1926 = _T_1920 | _T_1871; // @[lsu_bus_buffer.scala 370:42] + wire _T_1927 = ~_T_1926; // @[lsu_bus_buffer.scala 369:78] + wire _T_1928 = _T_1864 & _T_1927; // @[lsu_bus_buffer.scala 369:76] + wire _T_1932 = WrPtr0_m == 2'h2; // @[lsu_bus_buffer.scala 370:33] + wire _T_1933 = io_lsu_busreq_m & _T_1932; // @[lsu_bus_buffer.scala 370:22] + wire _T_1934 = _T_1877 | _T_1933; // @[lsu_bus_buffer.scala 369:112] + wire _T_1940 = _T_1934 | _T_1882; // @[lsu_bus_buffer.scala 370:42] + wire _T_1941 = ~_T_1940; // @[lsu_bus_buffer.scala 369:78] + wire _T_1942 = _T_1875 & _T_1941; // @[lsu_bus_buffer.scala 369:76] + reg [3:0] buf_rspageQ_0; // @[lsu_bus_buffer.scala 500:63] + wire _T_2746 = buf_state_3 == 3'h5; // @[lsu_bus_buffer.scala 413:102] + wire _T_2747 = buf_rspageQ_0[3] & _T_2746; // @[lsu_bus_buffer.scala 413:87] + wire _T_2743 = buf_state_2 == 3'h5; // @[lsu_bus_buffer.scala 413:102] + wire _T_2744 = buf_rspageQ_0[2] & _T_2743; // @[lsu_bus_buffer.scala 413:87] + wire _T_2740 = buf_state_1 == 3'h5; // @[lsu_bus_buffer.scala 413:102] + wire _T_2741 = buf_rspageQ_0[1] & _T_2740; // @[lsu_bus_buffer.scala 413:87] + wire _T_2737 = buf_state_0 == 3'h5; // @[lsu_bus_buffer.scala 413:102] + wire _T_2738 = buf_rspageQ_0[0] & _T_2737; // @[lsu_bus_buffer.scala 413:87] wire [3:0] buf_rsp_pickage_0 = {_T_2747,_T_2744,_T_2741,_T_2738}; // @[Cat.scala 29:58] - wire _T_2033 = |buf_rsp_pickage_0; // @[lsu_bus_buffer.scala 382:65] - wire _T_2034 = ~_T_2033; // @[lsu_bus_buffer.scala 382:44] - wire _T_2036 = _T_2034 & _T_2737; // @[lsu_bus_buffer.scala 382:70] - reg [3:0] buf_rspageQ_1; // @[lsu_bus_buffer.scala 501:63] - wire _T_2762 = buf_rspageQ_1[3] & _T_2746; // @[lsu_bus_buffer.scala 414:87] - wire _T_2759 = buf_rspageQ_1[2] & _T_2743; // @[lsu_bus_buffer.scala 414:87] - wire _T_2756 = buf_rspageQ_1[1] & _T_2740; // @[lsu_bus_buffer.scala 414:87] - wire _T_2753 = buf_rspageQ_1[0] & _T_2737; // @[lsu_bus_buffer.scala 414:87] + wire _T_2033 = |buf_rsp_pickage_0; // @[lsu_bus_buffer.scala 381:65] + wire _T_2034 = ~_T_2033; // @[lsu_bus_buffer.scala 381:44] + wire _T_2036 = _T_2034 & _T_2737; // @[lsu_bus_buffer.scala 381:70] + reg [3:0] buf_rspageQ_1; // @[lsu_bus_buffer.scala 500:63] + wire _T_2762 = buf_rspageQ_1[3] & _T_2746; // @[lsu_bus_buffer.scala 413:87] + wire _T_2759 = buf_rspageQ_1[2] & _T_2743; // @[lsu_bus_buffer.scala 413:87] + wire _T_2756 = buf_rspageQ_1[1] & _T_2740; // @[lsu_bus_buffer.scala 413:87] + wire _T_2753 = buf_rspageQ_1[0] & _T_2737; // @[lsu_bus_buffer.scala 413:87] wire [3:0] buf_rsp_pickage_1 = {_T_2762,_T_2759,_T_2756,_T_2753}; // @[Cat.scala 29:58] - wire _T_2037 = |buf_rsp_pickage_1; // @[lsu_bus_buffer.scala 382:65] - wire _T_2038 = ~_T_2037; // @[lsu_bus_buffer.scala 382:44] - wire _T_2040 = _T_2038 & _T_2740; // @[lsu_bus_buffer.scala 382:70] - reg [3:0] buf_rspageQ_2; // @[lsu_bus_buffer.scala 501:63] - wire _T_2777 = buf_rspageQ_2[3] & _T_2746; // @[lsu_bus_buffer.scala 414:87] - wire _T_2774 = buf_rspageQ_2[2] & _T_2743; // @[lsu_bus_buffer.scala 414:87] - wire _T_2771 = buf_rspageQ_2[1] & _T_2740; // @[lsu_bus_buffer.scala 414:87] - wire _T_2768 = buf_rspageQ_2[0] & _T_2737; // @[lsu_bus_buffer.scala 414:87] + wire _T_2037 = |buf_rsp_pickage_1; // @[lsu_bus_buffer.scala 381:65] + wire _T_2038 = ~_T_2037; // @[lsu_bus_buffer.scala 381:44] + wire _T_2040 = _T_2038 & _T_2740; // @[lsu_bus_buffer.scala 381:70] + reg [3:0] buf_rspageQ_2; // @[lsu_bus_buffer.scala 500:63] + wire _T_2777 = buf_rspageQ_2[3] & _T_2746; // @[lsu_bus_buffer.scala 413:87] + wire _T_2774 = buf_rspageQ_2[2] & _T_2743; // @[lsu_bus_buffer.scala 413:87] + wire _T_2771 = buf_rspageQ_2[1] & _T_2740; // @[lsu_bus_buffer.scala 413:87] + wire _T_2768 = buf_rspageQ_2[0] & _T_2737; // @[lsu_bus_buffer.scala 413:87] wire [3:0] buf_rsp_pickage_2 = {_T_2777,_T_2774,_T_2771,_T_2768}; // @[Cat.scala 29:58] - wire _T_2041 = |buf_rsp_pickage_2; // @[lsu_bus_buffer.scala 382:65] - wire _T_2042 = ~_T_2041; // @[lsu_bus_buffer.scala 382:44] - wire _T_2044 = _T_2042 & _T_2743; // @[lsu_bus_buffer.scala 382:70] - reg [3:0] buf_rspageQ_3; // @[lsu_bus_buffer.scala 501:63] - wire _T_2792 = buf_rspageQ_3[3] & _T_2746; // @[lsu_bus_buffer.scala 414:87] - wire _T_2789 = buf_rspageQ_3[2] & _T_2743; // @[lsu_bus_buffer.scala 414:87] - wire _T_2786 = buf_rspageQ_3[1] & _T_2740; // @[lsu_bus_buffer.scala 414:87] - wire _T_2783 = buf_rspageQ_3[0] & _T_2737; // @[lsu_bus_buffer.scala 414:87] + wire _T_2041 = |buf_rsp_pickage_2; // @[lsu_bus_buffer.scala 381:65] + wire _T_2042 = ~_T_2041; // @[lsu_bus_buffer.scala 381:44] + wire _T_2044 = _T_2042 & _T_2743; // @[lsu_bus_buffer.scala 381:70] + reg [3:0] buf_rspageQ_3; // @[lsu_bus_buffer.scala 500:63] + wire _T_2792 = buf_rspageQ_3[3] & _T_2746; // @[lsu_bus_buffer.scala 413:87] + wire _T_2789 = buf_rspageQ_3[2] & _T_2743; // @[lsu_bus_buffer.scala 413:87] + wire _T_2786 = buf_rspageQ_3[1] & _T_2740; // @[lsu_bus_buffer.scala 413:87] + wire _T_2783 = buf_rspageQ_3[0] & _T_2737; // @[lsu_bus_buffer.scala 413:87] wire [3:0] buf_rsp_pickage_3 = {_T_2792,_T_2789,_T_2786,_T_2783}; // @[Cat.scala 29:58] - wire _T_2045 = |buf_rsp_pickage_3; // @[lsu_bus_buffer.scala 382:65] - wire _T_2046 = ~_T_2045; // @[lsu_bus_buffer.scala 382:44] - wire _T_2048 = _T_2046 & _T_2746; // @[lsu_bus_buffer.scala 382:70] + wire _T_2045 = |buf_rsp_pickage_3; // @[lsu_bus_buffer.scala 381:65] + wire _T_2046 = ~_T_2045; // @[lsu_bus_buffer.scala 381:44] + wire _T_2048 = _T_2046 & _T_2746; // @[lsu_bus_buffer.scala 381:70] wire [7:0] _T_2104 = {4'h0,_T_2048,_T_2044,_T_2040,_T_2036}; // @[Cat.scala 29:58] - wire _T_2107 = _T_2104[4] | _T_2104[5]; // @[lsu_bus_buffer.scala 386:42] - wire _T_2109 = _T_2107 | _T_2104[6]; // @[lsu_bus_buffer.scala 386:48] - wire _T_2111 = _T_2109 | _T_2104[7]; // @[lsu_bus_buffer.scala 386:54] - wire _T_2114 = _T_2104[2] | _T_2104[3]; // @[lsu_bus_buffer.scala 386:67] - wire _T_2116 = _T_2114 | _T_2104[6]; // @[lsu_bus_buffer.scala 386:73] - wire _T_2118 = _T_2116 | _T_2104[7]; // @[lsu_bus_buffer.scala 386:79] - wire _T_2121 = _T_2104[1] | _T_2104[3]; // @[lsu_bus_buffer.scala 386:92] - wire _T_2123 = _T_2121 | _T_2104[5]; // @[lsu_bus_buffer.scala 386:98] - wire _T_2125 = _T_2123 | _T_2104[7]; // @[lsu_bus_buffer.scala 386:104] + wire _T_2107 = _T_2104[4] | _T_2104[5]; // @[lsu_bus_buffer.scala 385:42] + wire _T_2109 = _T_2107 | _T_2104[6]; // @[lsu_bus_buffer.scala 385:48] + wire _T_2111 = _T_2109 | _T_2104[7]; // @[lsu_bus_buffer.scala 385:54] + wire _T_2114 = _T_2104[2] | _T_2104[3]; // @[lsu_bus_buffer.scala 385:67] + wire _T_2116 = _T_2114 | _T_2104[6]; // @[lsu_bus_buffer.scala 385:73] + wire _T_2118 = _T_2116 | _T_2104[7]; // @[lsu_bus_buffer.scala 385:79] + wire _T_2121 = _T_2104[1] | _T_2104[3]; // @[lsu_bus_buffer.scala 385:92] + wire _T_2123 = _T_2121 | _T_2104[5]; // @[lsu_bus_buffer.scala 385:98] + wire _T_2125 = _T_2123 | _T_2104[7]; // @[lsu_bus_buffer.scala 385:104] wire [2:0] _T_2127 = {_T_2111,_T_2118,_T_2125}; // @[Cat.scala 29:58] - wire _T_3532 = ibuf_byp | io_ldst_dual_r; // @[lsu_bus_buffer.scala 444:77] - wire _T_3533 = ~ibuf_merge_en; // @[lsu_bus_buffer.scala 444:97] - wire _T_3534 = _T_3532 & _T_3533; // @[lsu_bus_buffer.scala 444:95] - wire _T_3535 = 2'h0 == WrPtr0_r; // @[lsu_bus_buffer.scala 444:117] - wire _T_3536 = _T_3534 & _T_3535; // @[lsu_bus_buffer.scala 444:112] - wire _T_3537 = ibuf_byp & io_ldst_dual_r; // @[lsu_bus_buffer.scala 444:144] - wire _T_3538 = 2'h0 == WrPtr1_r; // @[lsu_bus_buffer.scala 444:166] - wire _T_3539 = _T_3537 & _T_3538; // @[lsu_bus_buffer.scala 444:161] - wire _T_3540 = _T_3536 | _T_3539; // @[lsu_bus_buffer.scala 444:132] - wire _T_3541 = _T_853 & _T_3540; // @[lsu_bus_buffer.scala 444:63] - wire _T_3542 = 2'h0 == ibuf_tag; // @[lsu_bus_buffer.scala 444:206] - wire _T_3543 = ibuf_drain_vld & _T_3542; // @[lsu_bus_buffer.scala 444:201] - wire _T_3544 = _T_3541 | _T_3543; // @[lsu_bus_buffer.scala 444:183] - wire _T_3554 = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 451:46] + wire _T_3532 = ibuf_byp | io_ldst_dual_r; // @[lsu_bus_buffer.scala 443:77] + wire _T_3535 = 2'h0 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117] + wire _T_3536 = _T_3532 & _T_3535; // @[lsu_bus_buffer.scala 443:112] + wire _T_3537 = ibuf_byp & io_ldst_dual_r; // @[lsu_bus_buffer.scala 443:144] + wire _T_3538 = 2'h0 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166] + wire _T_3539 = _T_3537 & _T_3538; // @[lsu_bus_buffer.scala 443:161] + wire _T_3540 = _T_3536 | _T_3539; // @[lsu_bus_buffer.scala 443:132] + wire _T_3541 = _T_853 & _T_3540; // @[lsu_bus_buffer.scala 443:63] + wire _T_3542 = 2'h0 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206] + wire _T_3543 = ibuf_valid & _T_3542; // @[lsu_bus_buffer.scala 443:201] + wire _T_3544 = _T_3541 | _T_3543; // @[lsu_bus_buffer.scala 443:183] + wire _T_3554 = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 450:46] wire _T_3589 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30] - wire bus_rsp_write = io_lsu_axi_b_valid & io_lsu_axi_b_ready; // @[lsu_bus_buffer.scala 561:39] - wire _T_3634 = io_lsu_axi_b_bits_id == 3'h0; // @[lsu_bus_buffer.scala 469:73] - wire _T_3635 = bus_rsp_write & _T_3634; // @[lsu_bus_buffer.scala 469:52] - wire _T_3636 = io_lsu_axi_r_bits_id == 3'h0; // @[lsu_bus_buffer.scala 470:46] + wire bus_rsp_write = io_lsu_axi_b_valid & io_lsu_axi_b_ready; // @[lsu_bus_buffer.scala 560:39] + wire _T_3634 = io_lsu_axi_b_bits_id == 3'h0; // @[lsu_bus_buffer.scala 468:73] + wire _T_3635 = bus_rsp_write & _T_3634; // @[lsu_bus_buffer.scala 468:52] + wire _T_3636 = io_lsu_axi_r_bits_id == 3'h0; // @[lsu_bus_buffer.scala 469:46] reg _T_4307; // @[Reg.scala 27:20] reg _T_4305; // @[Reg.scala 27:20] reg _T_4303; // @[Reg.scala 27:20] reg _T_4301; // @[Reg.scala 27:20] wire [3:0] buf_ldfwd = {_T_4307,_T_4305,_T_4303,_T_4301}; // @[Cat.scala 29:58] reg [1:0] buf_ldfwdtag_0; // @[Reg.scala 27:20] - wire [2:0] _GEN_368 = {{1'd0}, buf_ldfwdtag_0}; // @[lsu_bus_buffer.scala 471:47] - wire _T_3638 = io_lsu_axi_r_bits_id == _GEN_368; // @[lsu_bus_buffer.scala 471:47] - wire _T_3639 = buf_ldfwd[0] & _T_3638; // @[lsu_bus_buffer.scala 471:27] - wire _T_3640 = _T_3636 | _T_3639; // @[lsu_bus_buffer.scala 470:77] - wire _T_3641 = buf_dual_0 & buf_dualhi_0; // @[lsu_bus_buffer.scala 472:26] - wire _T_3643 = ~buf_write[0]; // @[lsu_bus_buffer.scala 472:44] - wire _T_3644 = _T_3641 & _T_3643; // @[lsu_bus_buffer.scala 472:42] - wire _T_3645 = _T_3644 & buf_samedw_0; // @[lsu_bus_buffer.scala 472:58] + wire [2:0] _GEN_368 = {{1'd0}, buf_ldfwdtag_0}; // @[lsu_bus_buffer.scala 470:47] + wire _T_3638 = io_lsu_axi_r_bits_id == _GEN_368; // @[lsu_bus_buffer.scala 470:47] + wire _T_3639 = buf_ldfwd[0] & _T_3638; // @[lsu_bus_buffer.scala 470:27] + wire _T_3640 = _T_3636 | _T_3639; // @[lsu_bus_buffer.scala 469:77] + wire _T_3641 = buf_dual_0 & buf_dualhi_0; // @[lsu_bus_buffer.scala 471:26] + wire _T_3643 = ~buf_write[0]; // @[lsu_bus_buffer.scala 471:44] + wire _T_3644 = _T_3641 & _T_3643; // @[lsu_bus_buffer.scala 471:42] + wire _T_3645 = _T_3644 & buf_samedw_0; // @[lsu_bus_buffer.scala 471:58] reg [1:0] buf_dualtag_0; // @[Reg.scala 27:20] - wire [2:0] _GEN_369 = {{1'd0}, buf_dualtag_0}; // @[lsu_bus_buffer.scala 472:94] - wire _T_3646 = io_lsu_axi_r_bits_id == _GEN_369; // @[lsu_bus_buffer.scala 472:94] - wire _T_3647 = _T_3645 & _T_3646; // @[lsu_bus_buffer.scala 472:74] - wire _T_3648 = _T_3640 | _T_3647; // @[lsu_bus_buffer.scala 471:71] - wire _T_3649 = bus_rsp_read & _T_3648; // @[lsu_bus_buffer.scala 470:25] - wire _T_3650 = _T_3635 | _T_3649; // @[lsu_bus_buffer.scala 469:105] + wire [2:0] _GEN_369 = {{1'd0}, buf_dualtag_0}; // @[lsu_bus_buffer.scala 471:94] + wire _T_3646 = io_lsu_axi_r_bits_id == _GEN_369; // @[lsu_bus_buffer.scala 471:94] + wire _T_3647 = _T_3645 & _T_3646; // @[lsu_bus_buffer.scala 471:74] + wire _T_3648 = _T_3640 | _T_3647; // @[lsu_bus_buffer.scala 470:71] + wire _T_3649 = bus_rsp_read & _T_3648; // @[lsu_bus_buffer.scala 469:25] + wire _T_3650 = _T_3635 | _T_3649; // @[lsu_bus_buffer.scala 468:105] wire _GEN_42 = _T_3589 & _T_3650; // @[Conditional.scala 39:67] wire _GEN_61 = _T_3555 ? 1'h0 : _GEN_42; // @[Conditional.scala 39:67] wire _GEN_73 = _T_3551 ? 1'h0 : _GEN_61; // @[Conditional.scala 39:67] wire buf_resp_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_73; // @[Conditional.scala 40:58] wire _T_3676 = 3'h4 == buf_state_0; // @[Conditional.scala 37:30] - wire [3:0] _T_3686 = buf_ldfwd >> buf_dualtag_0; // @[lsu_bus_buffer.scala 484:21] + wire [3:0] _T_3686 = buf_ldfwd >> buf_dualtag_0; // @[lsu_bus_buffer.scala 483:21] reg [1:0] buf_ldfwdtag_3; // @[Reg.scala 27:20] reg [1:0] buf_ldfwdtag_2; // @[Reg.scala 27:20] reg [1:0] buf_ldfwdtag_1; // @[Reg.scala 27:20] - wire [1:0] _GEN_23 = 2'h1 == buf_dualtag_0 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 484:58] - wire [1:0] _GEN_24 = 2'h2 == buf_dualtag_0 ? buf_ldfwdtag_2 : _GEN_23; // @[lsu_bus_buffer.scala 484:58] - wire [1:0] _GEN_25 = 2'h3 == buf_dualtag_0 ? buf_ldfwdtag_3 : _GEN_24; // @[lsu_bus_buffer.scala 484:58] - wire [2:0] _GEN_371 = {{1'd0}, _GEN_25}; // @[lsu_bus_buffer.scala 484:58] - wire _T_3688 = io_lsu_axi_r_bits_id == _GEN_371; // @[lsu_bus_buffer.scala 484:58] - wire _T_3689 = _T_3686[0] & _T_3688; // @[lsu_bus_buffer.scala 484:38] - wire _T_3690 = _T_3646 | _T_3689; // @[lsu_bus_buffer.scala 483:95] - wire _T_3691 = bus_rsp_read & _T_3690; // @[lsu_bus_buffer.scala 483:45] + wire [1:0] _GEN_23 = 2'h1 == buf_dualtag_0 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 483:58] + wire [1:0] _GEN_24 = 2'h2 == buf_dualtag_0 ? buf_ldfwdtag_2 : _GEN_23; // @[lsu_bus_buffer.scala 483:58] + wire [1:0] _GEN_25 = 2'h3 == buf_dualtag_0 ? buf_ldfwdtag_3 : _GEN_24; // @[lsu_bus_buffer.scala 483:58] + wire [2:0] _GEN_371 = {{1'd0}, _GEN_25}; // @[lsu_bus_buffer.scala 483:58] + wire _T_3688 = io_lsu_axi_r_bits_id == _GEN_371; // @[lsu_bus_buffer.scala 483:58] + wire _T_3689 = _T_3686[0] & _T_3688; // @[lsu_bus_buffer.scala 483:38] + wire _T_3690 = _T_3646 | _T_3689; // @[lsu_bus_buffer.scala 482:95] + wire _T_3691 = bus_rsp_read & _T_3690; // @[lsu_bus_buffer.scala 482:45] wire _GEN_36 = _T_3676 & _T_3691; // @[Conditional.scala 39:67] wire _GEN_43 = _T_3589 ? buf_resp_state_bus_en_0 : _GEN_36; // @[Conditional.scala 39:67] wire _GEN_53 = _T_3555 ? buf_cmd_state_bus_en_0 : _GEN_43; // @[Conditional.scala 39:67] wire _GEN_66 = _T_3551 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67] wire buf_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_66; // @[Conditional.scala 40:58] - wire _T_3568 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 457:49] - wire _T_3569 = _T_3568 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 457:70] + wire _T_3568 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 456:49] + wire _T_3569 = _T_3568 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 456:70] wire _T_3694 = 3'h5 == buf_state_0; // @[Conditional.scala 37:30] - wire [1:0] RspPtr = _T_2127[1:0]; // @[lsu_bus_buffer.scala 394:10] - wire _T_3697 = RspPtr == 2'h0; // @[lsu_bus_buffer.scala 489:37] - wire _T_3698 = buf_dualtag_0 == RspPtr; // @[lsu_bus_buffer.scala 489:98] - wire _T_3699 = buf_dual_0 & _T_3698; // @[lsu_bus_buffer.scala 489:80] - wire _T_3700 = _T_3697 | _T_3699; // @[lsu_bus_buffer.scala 489:65] - wire _T_3701 = _T_3700 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 489:112] + wire [1:0] RspPtr = _T_2127[1:0]; // @[lsu_bus_buffer.scala 393:10] + wire _T_3697 = RspPtr == 2'h0; // @[lsu_bus_buffer.scala 488:37] + wire _T_3698 = buf_dualtag_0 == RspPtr; // @[lsu_bus_buffer.scala 488:98] + wire _T_3699 = buf_dual_0 & _T_3698; // @[lsu_bus_buffer.scala 488:80] + wire _T_3700 = _T_3697 | _T_3699; // @[lsu_bus_buffer.scala 488:65] + wire _T_3701 = _T_3700 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 488:112] wire _T_3702 = 3'h6 == buf_state_0; // @[Conditional.scala 37:30] wire _GEN_31 = _T_3694 ? _T_3701 : _T_3702; // @[Conditional.scala 39:67] wire _GEN_37 = _T_3676 ? _T_3569 : _GEN_31; // @[Conditional.scala 39:67] @@ -69626,93 +69525,93 @@ module lsu_bus_buffer( wire _GEN_54 = _T_3555 ? _T_3569 : _GEN_44; // @[Conditional.scala 39:67] wire _GEN_64 = _T_3551 ? _T_3554 : _GEN_54; // @[Conditional.scala 39:67] wire buf_state_en_0 = _T_3528 ? _T_3544 : _GEN_64; // @[Conditional.scala 40:58] - wire _T_2129 = _T_1853 & buf_state_en_0; // @[lsu_bus_buffer.scala 406:94] - wire _T_2135 = ibuf_drain_vld & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 408:23] - wire _T_2137 = _T_2135 & _T_3532; // @[lsu_bus_buffer.scala 408:41] - wire _T_2139 = _T_2137 & _T_1856; // @[lsu_bus_buffer.scala 408:71] - wire _T_2141 = _T_2139 & _T_1854; // @[lsu_bus_buffer.scala 408:92] - wire _T_2142 = _T_4471 | _T_2141; // @[lsu_bus_buffer.scala 407:86] - wire _T_2143 = ibuf_byp & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 409:17] - wire _T_2144 = _T_2143 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 409:35] - wire _T_2146 = _T_2144 & _T_1857; // @[lsu_bus_buffer.scala 409:52] - wire _T_2148 = _T_2146 & _T_1856; // @[lsu_bus_buffer.scala 409:73] - wire _T_2149 = _T_2142 | _T_2148; // @[lsu_bus_buffer.scala 408:114] - wire _T_2150 = _T_2129 & _T_2149; // @[lsu_bus_buffer.scala 406:113] - wire _T_2152 = _T_2150 | buf_age_0[0]; // @[lsu_bus_buffer.scala 409:97] - wire _T_2166 = _T_2139 & _T_1865; // @[lsu_bus_buffer.scala 408:92] - wire _T_2167 = _T_4476 | _T_2166; // @[lsu_bus_buffer.scala 407:86] - wire _T_2173 = _T_2146 & _T_1867; // @[lsu_bus_buffer.scala 409:73] - wire _T_2174 = _T_2167 | _T_2173; // @[lsu_bus_buffer.scala 408:114] - wire _T_2175 = _T_2129 & _T_2174; // @[lsu_bus_buffer.scala 406:113] - wire _T_2177 = _T_2175 | buf_age_0[1]; // @[lsu_bus_buffer.scala 409:97] - wire _T_2191 = _T_2139 & _T_1876; // @[lsu_bus_buffer.scala 408:92] - wire _T_2192 = _T_4481 | _T_2191; // @[lsu_bus_buffer.scala 407:86] - wire _T_2198 = _T_2146 & _T_1878; // @[lsu_bus_buffer.scala 409:73] - wire _T_2199 = _T_2192 | _T_2198; // @[lsu_bus_buffer.scala 408:114] - wire _T_2200 = _T_2129 & _T_2199; // @[lsu_bus_buffer.scala 406:113] - wire _T_2202 = _T_2200 | buf_age_0[2]; // @[lsu_bus_buffer.scala 409:97] - wire _T_2216 = _T_2139 & _T_1887; // @[lsu_bus_buffer.scala 408:92] - wire _T_2217 = _T_4486 | _T_2216; // @[lsu_bus_buffer.scala 407:86] - wire _T_2223 = _T_2146 & _T_1889; // @[lsu_bus_buffer.scala 409:73] - wire _T_2224 = _T_2217 | _T_2223; // @[lsu_bus_buffer.scala 408:114] - wire _T_2225 = _T_2129 & _T_2224; // @[lsu_bus_buffer.scala 406:113] - wire _T_2227 = _T_2225 | buf_age_0[3]; // @[lsu_bus_buffer.scala 409:97] + wire _T_2129 = _T_1853 & buf_state_en_0; // @[lsu_bus_buffer.scala 405:94] + wire _T_2135 = ibuf_valid & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 407:23] + wire _T_2137 = _T_2135 & _T_3532; // @[lsu_bus_buffer.scala 407:41] + wire _T_2139 = _T_2137 & _T_1856; // @[lsu_bus_buffer.scala 407:71] + wire _T_2141 = _T_2139 & _T_1854; // @[lsu_bus_buffer.scala 407:92] + wire _T_2142 = _T_4471 | _T_2141; // @[lsu_bus_buffer.scala 406:86] + wire _T_2143 = ibuf_byp & io_lsu_busreq_r; // @[lsu_bus_buffer.scala 408:17] + wire _T_2144 = _T_2143 & io_ldst_dual_r; // @[lsu_bus_buffer.scala 408:35] + wire _T_2146 = _T_2144 & _T_1857; // @[lsu_bus_buffer.scala 408:52] + wire _T_2148 = _T_2146 & _T_1856; // @[lsu_bus_buffer.scala 408:73] + wire _T_2149 = _T_2142 | _T_2148; // @[lsu_bus_buffer.scala 407:114] + wire _T_2150 = _T_2129 & _T_2149; // @[lsu_bus_buffer.scala 405:113] + wire _T_2152 = _T_2150 | buf_age_0[0]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2166 = _T_2139 & _T_1865; // @[lsu_bus_buffer.scala 407:92] + wire _T_2167 = _T_4476 | _T_2166; // @[lsu_bus_buffer.scala 406:86] + wire _T_2173 = _T_2146 & _T_1867; // @[lsu_bus_buffer.scala 408:73] + wire _T_2174 = _T_2167 | _T_2173; // @[lsu_bus_buffer.scala 407:114] + wire _T_2175 = _T_2129 & _T_2174; // @[lsu_bus_buffer.scala 405:113] + wire _T_2177 = _T_2175 | buf_age_0[1]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2191 = _T_2139 & _T_1876; // @[lsu_bus_buffer.scala 407:92] + wire _T_2192 = _T_4481 | _T_2191; // @[lsu_bus_buffer.scala 406:86] + wire _T_2198 = _T_2146 & _T_1878; // @[lsu_bus_buffer.scala 408:73] + wire _T_2199 = _T_2192 | _T_2198; // @[lsu_bus_buffer.scala 407:114] + wire _T_2200 = _T_2129 & _T_2199; // @[lsu_bus_buffer.scala 405:113] + wire _T_2202 = _T_2200 | buf_age_0[2]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2216 = _T_2139 & _T_1887; // @[lsu_bus_buffer.scala 407:92] + wire _T_2217 = _T_4486 | _T_2216; // @[lsu_bus_buffer.scala 406:86] + wire _T_2223 = _T_2146 & _T_1889; // @[lsu_bus_buffer.scala 408:73] + wire _T_2224 = _T_2217 | _T_2223; // @[lsu_bus_buffer.scala 407:114] + wire _T_2225 = _T_2129 & _T_2224; // @[lsu_bus_buffer.scala 405:113] + wire _T_2227 = _T_2225 | buf_age_0[3]; // @[lsu_bus_buffer.scala 408:97] wire [2:0] _T_2229 = {_T_2227,_T_2202,_T_2177}; // @[Cat.scala 29:58] - wire _T_3728 = 2'h1 == WrPtr0_r; // @[lsu_bus_buffer.scala 444:117] - wire _T_3729 = _T_3534 & _T_3728; // @[lsu_bus_buffer.scala 444:112] - wire _T_3731 = 2'h1 == WrPtr1_r; // @[lsu_bus_buffer.scala 444:166] - wire _T_3732 = _T_3537 & _T_3731; // @[lsu_bus_buffer.scala 444:161] - wire _T_3733 = _T_3729 | _T_3732; // @[lsu_bus_buffer.scala 444:132] - wire _T_3734 = _T_853 & _T_3733; // @[lsu_bus_buffer.scala 444:63] - wire _T_3735 = 2'h1 == ibuf_tag; // @[lsu_bus_buffer.scala 444:206] - wire _T_3736 = ibuf_drain_vld & _T_3735; // @[lsu_bus_buffer.scala 444:201] - wire _T_3737 = _T_3734 | _T_3736; // @[lsu_bus_buffer.scala 444:183] + wire _T_3728 = 2'h1 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117] + wire _T_3729 = _T_3532 & _T_3728; // @[lsu_bus_buffer.scala 443:112] + wire _T_3731 = 2'h1 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166] + wire _T_3732 = _T_3537 & _T_3731; // @[lsu_bus_buffer.scala 443:161] + wire _T_3733 = _T_3729 | _T_3732; // @[lsu_bus_buffer.scala 443:132] + wire _T_3734 = _T_853 & _T_3733; // @[lsu_bus_buffer.scala 443:63] + wire _T_3735 = 2'h1 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206] + wire _T_3736 = ibuf_valid & _T_3735; // @[lsu_bus_buffer.scala 443:201] + wire _T_3737 = _T_3734 | _T_3736; // @[lsu_bus_buffer.scala 443:183] wire _T_3782 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30] - wire _T_3827 = io_lsu_axi_b_bits_id == 3'h1; // @[lsu_bus_buffer.scala 469:73] - wire _T_3828 = bus_rsp_write & _T_3827; // @[lsu_bus_buffer.scala 469:52] - wire _T_3829 = io_lsu_axi_r_bits_id == 3'h1; // @[lsu_bus_buffer.scala 470:46] - wire [2:0] _GEN_372 = {{1'd0}, buf_ldfwdtag_1}; // @[lsu_bus_buffer.scala 471:47] - wire _T_3831 = io_lsu_axi_r_bits_id == _GEN_372; // @[lsu_bus_buffer.scala 471:47] - wire _T_3832 = buf_ldfwd[1] & _T_3831; // @[lsu_bus_buffer.scala 471:27] - wire _T_3833 = _T_3829 | _T_3832; // @[lsu_bus_buffer.scala 470:77] - wire _T_3834 = buf_dual_1 & buf_dualhi_1; // @[lsu_bus_buffer.scala 472:26] - wire _T_3836 = ~buf_write[1]; // @[lsu_bus_buffer.scala 472:44] - wire _T_3837 = _T_3834 & _T_3836; // @[lsu_bus_buffer.scala 472:42] - wire _T_3838 = _T_3837 & buf_samedw_1; // @[lsu_bus_buffer.scala 472:58] + wire _T_3827 = io_lsu_axi_b_bits_id == 3'h1; // @[lsu_bus_buffer.scala 468:73] + wire _T_3828 = bus_rsp_write & _T_3827; // @[lsu_bus_buffer.scala 468:52] + wire _T_3829 = io_lsu_axi_r_bits_id == 3'h1; // @[lsu_bus_buffer.scala 469:46] + wire [2:0] _GEN_372 = {{1'd0}, buf_ldfwdtag_1}; // @[lsu_bus_buffer.scala 470:47] + wire _T_3831 = io_lsu_axi_r_bits_id == _GEN_372; // @[lsu_bus_buffer.scala 470:47] + wire _T_3832 = buf_ldfwd[1] & _T_3831; // @[lsu_bus_buffer.scala 470:27] + wire _T_3833 = _T_3829 | _T_3832; // @[lsu_bus_buffer.scala 469:77] + wire _T_3834 = buf_dual_1 & buf_dualhi_1; // @[lsu_bus_buffer.scala 471:26] + wire _T_3836 = ~buf_write[1]; // @[lsu_bus_buffer.scala 471:44] + wire _T_3837 = _T_3834 & _T_3836; // @[lsu_bus_buffer.scala 471:42] + wire _T_3838 = _T_3837 & buf_samedw_1; // @[lsu_bus_buffer.scala 471:58] reg [1:0] buf_dualtag_1; // @[Reg.scala 27:20] - wire [2:0] _GEN_373 = {{1'd0}, buf_dualtag_1}; // @[lsu_bus_buffer.scala 472:94] - wire _T_3839 = io_lsu_axi_r_bits_id == _GEN_373; // @[lsu_bus_buffer.scala 472:94] - wire _T_3840 = _T_3838 & _T_3839; // @[lsu_bus_buffer.scala 472:74] - wire _T_3841 = _T_3833 | _T_3840; // @[lsu_bus_buffer.scala 471:71] - wire _T_3842 = bus_rsp_read & _T_3841; // @[lsu_bus_buffer.scala 470:25] - wire _T_3843 = _T_3828 | _T_3842; // @[lsu_bus_buffer.scala 469:105] + wire [2:0] _GEN_373 = {{1'd0}, buf_dualtag_1}; // @[lsu_bus_buffer.scala 471:94] + wire _T_3839 = io_lsu_axi_r_bits_id == _GEN_373; // @[lsu_bus_buffer.scala 471:94] + wire _T_3840 = _T_3838 & _T_3839; // @[lsu_bus_buffer.scala 471:74] + wire _T_3841 = _T_3833 | _T_3840; // @[lsu_bus_buffer.scala 470:71] + wire _T_3842 = bus_rsp_read & _T_3841; // @[lsu_bus_buffer.scala 469:25] + wire _T_3843 = _T_3828 | _T_3842; // @[lsu_bus_buffer.scala 468:105] wire _GEN_118 = _T_3782 & _T_3843; // @[Conditional.scala 39:67] wire _GEN_137 = _T_3748 ? 1'h0 : _GEN_118; // @[Conditional.scala 39:67] wire _GEN_149 = _T_3744 ? 1'h0 : _GEN_137; // @[Conditional.scala 39:67] wire buf_resp_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_149; // @[Conditional.scala 40:58] wire _T_3869 = 3'h4 == buf_state_1; // @[Conditional.scala 37:30] - wire [3:0] _T_3879 = buf_ldfwd >> buf_dualtag_1; // @[lsu_bus_buffer.scala 484:21] - wire [1:0] _GEN_99 = 2'h1 == buf_dualtag_1 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 484:58] - wire [1:0] _GEN_100 = 2'h2 == buf_dualtag_1 ? buf_ldfwdtag_2 : _GEN_99; // @[lsu_bus_buffer.scala 484:58] - wire [1:0] _GEN_101 = 2'h3 == buf_dualtag_1 ? buf_ldfwdtag_3 : _GEN_100; // @[lsu_bus_buffer.scala 484:58] - wire [2:0] _GEN_375 = {{1'd0}, _GEN_101}; // @[lsu_bus_buffer.scala 484:58] - wire _T_3881 = io_lsu_axi_r_bits_id == _GEN_375; // @[lsu_bus_buffer.scala 484:58] - wire _T_3882 = _T_3879[0] & _T_3881; // @[lsu_bus_buffer.scala 484:38] - wire _T_3883 = _T_3839 | _T_3882; // @[lsu_bus_buffer.scala 483:95] - wire _T_3884 = bus_rsp_read & _T_3883; // @[lsu_bus_buffer.scala 483:45] + wire [3:0] _T_3879 = buf_ldfwd >> buf_dualtag_1; // @[lsu_bus_buffer.scala 483:21] + wire [1:0] _GEN_99 = 2'h1 == buf_dualtag_1 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 483:58] + wire [1:0] _GEN_100 = 2'h2 == buf_dualtag_1 ? buf_ldfwdtag_2 : _GEN_99; // @[lsu_bus_buffer.scala 483:58] + wire [1:0] _GEN_101 = 2'h3 == buf_dualtag_1 ? buf_ldfwdtag_3 : _GEN_100; // @[lsu_bus_buffer.scala 483:58] + wire [2:0] _GEN_375 = {{1'd0}, _GEN_101}; // @[lsu_bus_buffer.scala 483:58] + wire _T_3881 = io_lsu_axi_r_bits_id == _GEN_375; // @[lsu_bus_buffer.scala 483:58] + wire _T_3882 = _T_3879[0] & _T_3881; // @[lsu_bus_buffer.scala 483:38] + wire _T_3883 = _T_3839 | _T_3882; // @[lsu_bus_buffer.scala 482:95] + wire _T_3884 = bus_rsp_read & _T_3883; // @[lsu_bus_buffer.scala 482:45] wire _GEN_112 = _T_3869 & _T_3884; // @[Conditional.scala 39:67] wire _GEN_119 = _T_3782 ? buf_resp_state_bus_en_1 : _GEN_112; // @[Conditional.scala 39:67] wire _GEN_129 = _T_3748 ? buf_cmd_state_bus_en_1 : _GEN_119; // @[Conditional.scala 39:67] wire _GEN_142 = _T_3744 ? 1'h0 : _GEN_129; // @[Conditional.scala 39:67] wire buf_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_142; // @[Conditional.scala 40:58] - wire _T_3761 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 457:49] - wire _T_3762 = _T_3761 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 457:70] + wire _T_3761 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 456:49] + wire _T_3762 = _T_3761 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 456:70] wire _T_3887 = 3'h5 == buf_state_1; // @[Conditional.scala 37:30] - wire _T_3890 = RspPtr == 2'h1; // @[lsu_bus_buffer.scala 489:37] - wire _T_3891 = buf_dualtag_1 == RspPtr; // @[lsu_bus_buffer.scala 489:98] - wire _T_3892 = buf_dual_1 & _T_3891; // @[lsu_bus_buffer.scala 489:80] - wire _T_3893 = _T_3890 | _T_3892; // @[lsu_bus_buffer.scala 489:65] - wire _T_3894 = _T_3893 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 489:112] + wire _T_3890 = RspPtr == 2'h1; // @[lsu_bus_buffer.scala 488:37] + wire _T_3891 = buf_dualtag_1 == RspPtr; // @[lsu_bus_buffer.scala 488:98] + wire _T_3892 = buf_dual_1 & _T_3891; // @[lsu_bus_buffer.scala 488:80] + wire _T_3893 = _T_3890 | _T_3892; // @[lsu_bus_buffer.scala 488:65] + wire _T_3894 = _T_3893 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 488:112] wire _T_3895 = 3'h6 == buf_state_1; // @[Conditional.scala 37:30] wire _GEN_107 = _T_3887 ? _T_3894 : _T_3895; // @[Conditional.scala 39:67] wire _GEN_113 = _T_3869 ? _T_3762 : _GEN_107; // @[Conditional.scala 39:67] @@ -69720,89 +69619,89 @@ module lsu_bus_buffer( wire _GEN_130 = _T_3748 ? _T_3762 : _GEN_120; // @[Conditional.scala 39:67] wire _GEN_140 = _T_3744 ? _T_3554 : _GEN_130; // @[Conditional.scala 39:67] wire buf_state_en_1 = _T_3721 ? _T_3737 : _GEN_140; // @[Conditional.scala 40:58] - wire _T_2231 = _T_1864 & buf_state_en_1; // @[lsu_bus_buffer.scala 406:94] - wire _T_2241 = _T_2137 & _T_1867; // @[lsu_bus_buffer.scala 408:71] - wire _T_2243 = _T_2241 & _T_1854; // @[lsu_bus_buffer.scala 408:92] - wire _T_2244 = _T_4471 | _T_2243; // @[lsu_bus_buffer.scala 407:86] - wire _T_2248 = _T_2144 & _T_1868; // @[lsu_bus_buffer.scala 409:52] - wire _T_2250 = _T_2248 & _T_1856; // @[lsu_bus_buffer.scala 409:73] - wire _T_2251 = _T_2244 | _T_2250; // @[lsu_bus_buffer.scala 408:114] - wire _T_2252 = _T_2231 & _T_2251; // @[lsu_bus_buffer.scala 406:113] - wire _T_2254 = _T_2252 | buf_age_1[0]; // @[lsu_bus_buffer.scala 409:97] - wire _T_2268 = _T_2241 & _T_1865; // @[lsu_bus_buffer.scala 408:92] - wire _T_2269 = _T_4476 | _T_2268; // @[lsu_bus_buffer.scala 407:86] - wire _T_2275 = _T_2248 & _T_1867; // @[lsu_bus_buffer.scala 409:73] - wire _T_2276 = _T_2269 | _T_2275; // @[lsu_bus_buffer.scala 408:114] - wire _T_2277 = _T_2231 & _T_2276; // @[lsu_bus_buffer.scala 406:113] - wire _T_2279 = _T_2277 | buf_age_1[1]; // @[lsu_bus_buffer.scala 409:97] - wire _T_2293 = _T_2241 & _T_1876; // @[lsu_bus_buffer.scala 408:92] - wire _T_2294 = _T_4481 | _T_2293; // @[lsu_bus_buffer.scala 407:86] - wire _T_2300 = _T_2248 & _T_1878; // @[lsu_bus_buffer.scala 409:73] - wire _T_2301 = _T_2294 | _T_2300; // @[lsu_bus_buffer.scala 408:114] - wire _T_2302 = _T_2231 & _T_2301; // @[lsu_bus_buffer.scala 406:113] - wire _T_2304 = _T_2302 | buf_age_1[2]; // @[lsu_bus_buffer.scala 409:97] - wire _T_2318 = _T_2241 & _T_1887; // @[lsu_bus_buffer.scala 408:92] - wire _T_2319 = _T_4486 | _T_2318; // @[lsu_bus_buffer.scala 407:86] - wire _T_2325 = _T_2248 & _T_1889; // @[lsu_bus_buffer.scala 409:73] - wire _T_2326 = _T_2319 | _T_2325; // @[lsu_bus_buffer.scala 408:114] - wire _T_2327 = _T_2231 & _T_2326; // @[lsu_bus_buffer.scala 406:113] - wire _T_2329 = _T_2327 | buf_age_1[3]; // @[lsu_bus_buffer.scala 409:97] + wire _T_2231 = _T_1864 & buf_state_en_1; // @[lsu_bus_buffer.scala 405:94] + wire _T_2241 = _T_2137 & _T_1867; // @[lsu_bus_buffer.scala 407:71] + wire _T_2243 = _T_2241 & _T_1854; // @[lsu_bus_buffer.scala 407:92] + wire _T_2244 = _T_4471 | _T_2243; // @[lsu_bus_buffer.scala 406:86] + wire _T_2248 = _T_2144 & _T_1868; // @[lsu_bus_buffer.scala 408:52] + wire _T_2250 = _T_2248 & _T_1856; // @[lsu_bus_buffer.scala 408:73] + wire _T_2251 = _T_2244 | _T_2250; // @[lsu_bus_buffer.scala 407:114] + wire _T_2252 = _T_2231 & _T_2251; // @[lsu_bus_buffer.scala 405:113] + wire _T_2254 = _T_2252 | buf_age_1[0]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2268 = _T_2241 & _T_1865; // @[lsu_bus_buffer.scala 407:92] + wire _T_2269 = _T_4476 | _T_2268; // @[lsu_bus_buffer.scala 406:86] + wire _T_2275 = _T_2248 & _T_1867; // @[lsu_bus_buffer.scala 408:73] + wire _T_2276 = _T_2269 | _T_2275; // @[lsu_bus_buffer.scala 407:114] + wire _T_2277 = _T_2231 & _T_2276; // @[lsu_bus_buffer.scala 405:113] + wire _T_2279 = _T_2277 | buf_age_1[1]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2293 = _T_2241 & _T_1876; // @[lsu_bus_buffer.scala 407:92] + wire _T_2294 = _T_4481 | _T_2293; // @[lsu_bus_buffer.scala 406:86] + wire _T_2300 = _T_2248 & _T_1878; // @[lsu_bus_buffer.scala 408:73] + wire _T_2301 = _T_2294 | _T_2300; // @[lsu_bus_buffer.scala 407:114] + wire _T_2302 = _T_2231 & _T_2301; // @[lsu_bus_buffer.scala 405:113] + wire _T_2304 = _T_2302 | buf_age_1[2]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2318 = _T_2241 & _T_1887; // @[lsu_bus_buffer.scala 407:92] + wire _T_2319 = _T_4486 | _T_2318; // @[lsu_bus_buffer.scala 406:86] + wire _T_2325 = _T_2248 & _T_1889; // @[lsu_bus_buffer.scala 408:73] + wire _T_2326 = _T_2319 | _T_2325; // @[lsu_bus_buffer.scala 407:114] + wire _T_2327 = _T_2231 & _T_2326; // @[lsu_bus_buffer.scala 405:113] + wire _T_2329 = _T_2327 | buf_age_1[3]; // @[lsu_bus_buffer.scala 408:97] wire [2:0] _T_2331 = {_T_2329,_T_2304,_T_2279}; // @[Cat.scala 29:58] - wire _T_3921 = 2'h2 == WrPtr0_r; // @[lsu_bus_buffer.scala 444:117] - wire _T_3922 = _T_3534 & _T_3921; // @[lsu_bus_buffer.scala 444:112] - wire _T_3924 = 2'h2 == WrPtr1_r; // @[lsu_bus_buffer.scala 444:166] - wire _T_3925 = _T_3537 & _T_3924; // @[lsu_bus_buffer.scala 444:161] - wire _T_3926 = _T_3922 | _T_3925; // @[lsu_bus_buffer.scala 444:132] - wire _T_3927 = _T_853 & _T_3926; // @[lsu_bus_buffer.scala 444:63] - wire _T_3928 = 2'h2 == ibuf_tag; // @[lsu_bus_buffer.scala 444:206] - wire _T_3929 = ibuf_drain_vld & _T_3928; // @[lsu_bus_buffer.scala 444:201] - wire _T_3930 = _T_3927 | _T_3929; // @[lsu_bus_buffer.scala 444:183] + wire _T_3921 = 2'h2 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117] + wire _T_3922 = _T_3532 & _T_3921; // @[lsu_bus_buffer.scala 443:112] + wire _T_3924 = 2'h2 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166] + wire _T_3925 = _T_3537 & _T_3924; // @[lsu_bus_buffer.scala 443:161] + wire _T_3926 = _T_3922 | _T_3925; // @[lsu_bus_buffer.scala 443:132] + wire _T_3927 = _T_853 & _T_3926; // @[lsu_bus_buffer.scala 443:63] + wire _T_3928 = 2'h2 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206] + wire _T_3929 = ibuf_valid & _T_3928; // @[lsu_bus_buffer.scala 443:201] + wire _T_3930 = _T_3927 | _T_3929; // @[lsu_bus_buffer.scala 443:183] wire _T_3975 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30] - wire _T_4020 = io_lsu_axi_b_bits_id == 3'h2; // @[lsu_bus_buffer.scala 469:73] - wire _T_4021 = bus_rsp_write & _T_4020; // @[lsu_bus_buffer.scala 469:52] - wire _T_4022 = io_lsu_axi_r_bits_id == 3'h2; // @[lsu_bus_buffer.scala 470:46] - wire [2:0] _GEN_376 = {{1'd0}, buf_ldfwdtag_2}; // @[lsu_bus_buffer.scala 471:47] - wire _T_4024 = io_lsu_axi_r_bits_id == _GEN_376; // @[lsu_bus_buffer.scala 471:47] - wire _T_4025 = buf_ldfwd[2] & _T_4024; // @[lsu_bus_buffer.scala 471:27] - wire _T_4026 = _T_4022 | _T_4025; // @[lsu_bus_buffer.scala 470:77] - wire _T_4027 = buf_dual_2 & buf_dualhi_2; // @[lsu_bus_buffer.scala 472:26] - wire _T_4029 = ~buf_write[2]; // @[lsu_bus_buffer.scala 472:44] - wire _T_4030 = _T_4027 & _T_4029; // @[lsu_bus_buffer.scala 472:42] - wire _T_4031 = _T_4030 & buf_samedw_2; // @[lsu_bus_buffer.scala 472:58] + wire _T_4020 = io_lsu_axi_b_bits_id == 3'h2; // @[lsu_bus_buffer.scala 468:73] + wire _T_4021 = bus_rsp_write & _T_4020; // @[lsu_bus_buffer.scala 468:52] + wire _T_4022 = io_lsu_axi_r_bits_id == 3'h2; // @[lsu_bus_buffer.scala 469:46] + wire [2:0] _GEN_376 = {{1'd0}, buf_ldfwdtag_2}; // @[lsu_bus_buffer.scala 470:47] + wire _T_4024 = io_lsu_axi_r_bits_id == _GEN_376; // @[lsu_bus_buffer.scala 470:47] + wire _T_4025 = buf_ldfwd[2] & _T_4024; // @[lsu_bus_buffer.scala 470:27] + wire _T_4026 = _T_4022 | _T_4025; // @[lsu_bus_buffer.scala 469:77] + wire _T_4027 = buf_dual_2 & buf_dualhi_2; // @[lsu_bus_buffer.scala 471:26] + wire _T_4029 = ~buf_write[2]; // @[lsu_bus_buffer.scala 471:44] + wire _T_4030 = _T_4027 & _T_4029; // @[lsu_bus_buffer.scala 471:42] + wire _T_4031 = _T_4030 & buf_samedw_2; // @[lsu_bus_buffer.scala 471:58] reg [1:0] buf_dualtag_2; // @[Reg.scala 27:20] - wire [2:0] _GEN_377 = {{1'd0}, buf_dualtag_2}; // @[lsu_bus_buffer.scala 472:94] - wire _T_4032 = io_lsu_axi_r_bits_id == _GEN_377; // @[lsu_bus_buffer.scala 472:94] - wire _T_4033 = _T_4031 & _T_4032; // @[lsu_bus_buffer.scala 472:74] - wire _T_4034 = _T_4026 | _T_4033; // @[lsu_bus_buffer.scala 471:71] - wire _T_4035 = bus_rsp_read & _T_4034; // @[lsu_bus_buffer.scala 470:25] - wire _T_4036 = _T_4021 | _T_4035; // @[lsu_bus_buffer.scala 469:105] + wire [2:0] _GEN_377 = {{1'd0}, buf_dualtag_2}; // @[lsu_bus_buffer.scala 471:94] + wire _T_4032 = io_lsu_axi_r_bits_id == _GEN_377; // @[lsu_bus_buffer.scala 471:94] + wire _T_4033 = _T_4031 & _T_4032; // @[lsu_bus_buffer.scala 471:74] + wire _T_4034 = _T_4026 | _T_4033; // @[lsu_bus_buffer.scala 470:71] + wire _T_4035 = bus_rsp_read & _T_4034; // @[lsu_bus_buffer.scala 469:25] + wire _T_4036 = _T_4021 | _T_4035; // @[lsu_bus_buffer.scala 468:105] wire _GEN_194 = _T_3975 & _T_4036; // @[Conditional.scala 39:67] wire _GEN_213 = _T_3941 ? 1'h0 : _GEN_194; // @[Conditional.scala 39:67] wire _GEN_225 = _T_3937 ? 1'h0 : _GEN_213; // @[Conditional.scala 39:67] wire buf_resp_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_225; // @[Conditional.scala 40:58] wire _T_4062 = 3'h4 == buf_state_2; // @[Conditional.scala 37:30] - wire [3:0] _T_4072 = buf_ldfwd >> buf_dualtag_2; // @[lsu_bus_buffer.scala 484:21] - wire [1:0] _GEN_175 = 2'h1 == buf_dualtag_2 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 484:58] - wire [1:0] _GEN_176 = 2'h2 == buf_dualtag_2 ? buf_ldfwdtag_2 : _GEN_175; // @[lsu_bus_buffer.scala 484:58] - wire [1:0] _GEN_177 = 2'h3 == buf_dualtag_2 ? buf_ldfwdtag_3 : _GEN_176; // @[lsu_bus_buffer.scala 484:58] - wire [2:0] _GEN_379 = {{1'd0}, _GEN_177}; // @[lsu_bus_buffer.scala 484:58] - wire _T_4074 = io_lsu_axi_r_bits_id == _GEN_379; // @[lsu_bus_buffer.scala 484:58] - wire _T_4075 = _T_4072[0] & _T_4074; // @[lsu_bus_buffer.scala 484:38] - wire _T_4076 = _T_4032 | _T_4075; // @[lsu_bus_buffer.scala 483:95] - wire _T_4077 = bus_rsp_read & _T_4076; // @[lsu_bus_buffer.scala 483:45] + wire [3:0] _T_4072 = buf_ldfwd >> buf_dualtag_2; // @[lsu_bus_buffer.scala 483:21] + wire [1:0] _GEN_175 = 2'h1 == buf_dualtag_2 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 483:58] + wire [1:0] _GEN_176 = 2'h2 == buf_dualtag_2 ? buf_ldfwdtag_2 : _GEN_175; // @[lsu_bus_buffer.scala 483:58] + wire [1:0] _GEN_177 = 2'h3 == buf_dualtag_2 ? buf_ldfwdtag_3 : _GEN_176; // @[lsu_bus_buffer.scala 483:58] + wire [2:0] _GEN_379 = {{1'd0}, _GEN_177}; // @[lsu_bus_buffer.scala 483:58] + wire _T_4074 = io_lsu_axi_r_bits_id == _GEN_379; // @[lsu_bus_buffer.scala 483:58] + wire _T_4075 = _T_4072[0] & _T_4074; // @[lsu_bus_buffer.scala 483:38] + wire _T_4076 = _T_4032 | _T_4075; // @[lsu_bus_buffer.scala 482:95] + wire _T_4077 = bus_rsp_read & _T_4076; // @[lsu_bus_buffer.scala 482:45] wire _GEN_188 = _T_4062 & _T_4077; // @[Conditional.scala 39:67] wire _GEN_195 = _T_3975 ? buf_resp_state_bus_en_2 : _GEN_188; // @[Conditional.scala 39:67] wire _GEN_205 = _T_3941 ? buf_cmd_state_bus_en_2 : _GEN_195; // @[Conditional.scala 39:67] wire _GEN_218 = _T_3937 ? 1'h0 : _GEN_205; // @[Conditional.scala 39:67] wire buf_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_218; // @[Conditional.scala 40:58] - wire _T_3954 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 457:49] - wire _T_3955 = _T_3954 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 457:70] + wire _T_3954 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 456:49] + wire _T_3955 = _T_3954 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 456:70] wire _T_4080 = 3'h5 == buf_state_2; // @[Conditional.scala 37:30] - wire _T_4083 = RspPtr == 2'h2; // @[lsu_bus_buffer.scala 489:37] - wire _T_4084 = buf_dualtag_2 == RspPtr; // @[lsu_bus_buffer.scala 489:98] - wire _T_4085 = buf_dual_2 & _T_4084; // @[lsu_bus_buffer.scala 489:80] - wire _T_4086 = _T_4083 | _T_4085; // @[lsu_bus_buffer.scala 489:65] - wire _T_4087 = _T_4086 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 489:112] + wire _T_4083 = RspPtr == 2'h2; // @[lsu_bus_buffer.scala 488:37] + wire _T_4084 = buf_dualtag_2 == RspPtr; // @[lsu_bus_buffer.scala 488:98] + wire _T_4085 = buf_dual_2 & _T_4084; // @[lsu_bus_buffer.scala 488:80] + wire _T_4086 = _T_4083 | _T_4085; // @[lsu_bus_buffer.scala 488:65] + wire _T_4087 = _T_4086 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 488:112] wire _T_4088 = 3'h6 == buf_state_2; // @[Conditional.scala 37:30] wire _GEN_183 = _T_4080 ? _T_4087 : _T_4088; // @[Conditional.scala 39:67] wire _GEN_189 = _T_4062 ? _T_3955 : _GEN_183; // @[Conditional.scala 39:67] @@ -69810,89 +69709,89 @@ module lsu_bus_buffer( wire _GEN_206 = _T_3941 ? _T_3955 : _GEN_196; // @[Conditional.scala 39:67] wire _GEN_216 = _T_3937 ? _T_3554 : _GEN_206; // @[Conditional.scala 39:67] wire buf_state_en_2 = _T_3914 ? _T_3930 : _GEN_216; // @[Conditional.scala 40:58] - wire _T_2333 = _T_1875 & buf_state_en_2; // @[lsu_bus_buffer.scala 406:94] - wire _T_2343 = _T_2137 & _T_1878; // @[lsu_bus_buffer.scala 408:71] - wire _T_2345 = _T_2343 & _T_1854; // @[lsu_bus_buffer.scala 408:92] - wire _T_2346 = _T_4471 | _T_2345; // @[lsu_bus_buffer.scala 407:86] - wire _T_2350 = _T_2144 & _T_1879; // @[lsu_bus_buffer.scala 409:52] - wire _T_2352 = _T_2350 & _T_1856; // @[lsu_bus_buffer.scala 409:73] - wire _T_2353 = _T_2346 | _T_2352; // @[lsu_bus_buffer.scala 408:114] - wire _T_2354 = _T_2333 & _T_2353; // @[lsu_bus_buffer.scala 406:113] - wire _T_2356 = _T_2354 | buf_age_2[0]; // @[lsu_bus_buffer.scala 409:97] - wire _T_2370 = _T_2343 & _T_1865; // @[lsu_bus_buffer.scala 408:92] - wire _T_2371 = _T_4476 | _T_2370; // @[lsu_bus_buffer.scala 407:86] - wire _T_2377 = _T_2350 & _T_1867; // @[lsu_bus_buffer.scala 409:73] - wire _T_2378 = _T_2371 | _T_2377; // @[lsu_bus_buffer.scala 408:114] - wire _T_2379 = _T_2333 & _T_2378; // @[lsu_bus_buffer.scala 406:113] - wire _T_2381 = _T_2379 | buf_age_2[1]; // @[lsu_bus_buffer.scala 409:97] - wire _T_2395 = _T_2343 & _T_1876; // @[lsu_bus_buffer.scala 408:92] - wire _T_2396 = _T_4481 | _T_2395; // @[lsu_bus_buffer.scala 407:86] - wire _T_2402 = _T_2350 & _T_1878; // @[lsu_bus_buffer.scala 409:73] - wire _T_2403 = _T_2396 | _T_2402; // @[lsu_bus_buffer.scala 408:114] - wire _T_2404 = _T_2333 & _T_2403; // @[lsu_bus_buffer.scala 406:113] - wire _T_2406 = _T_2404 | buf_age_2[2]; // @[lsu_bus_buffer.scala 409:97] - wire _T_2420 = _T_2343 & _T_1887; // @[lsu_bus_buffer.scala 408:92] - wire _T_2421 = _T_4486 | _T_2420; // @[lsu_bus_buffer.scala 407:86] - wire _T_2427 = _T_2350 & _T_1889; // @[lsu_bus_buffer.scala 409:73] - wire _T_2428 = _T_2421 | _T_2427; // @[lsu_bus_buffer.scala 408:114] - wire _T_2429 = _T_2333 & _T_2428; // @[lsu_bus_buffer.scala 406:113] - wire _T_2431 = _T_2429 | buf_age_2[3]; // @[lsu_bus_buffer.scala 409:97] + wire _T_2333 = _T_1875 & buf_state_en_2; // @[lsu_bus_buffer.scala 405:94] + wire _T_2343 = _T_2137 & _T_1878; // @[lsu_bus_buffer.scala 407:71] + wire _T_2345 = _T_2343 & _T_1854; // @[lsu_bus_buffer.scala 407:92] + wire _T_2346 = _T_4471 | _T_2345; // @[lsu_bus_buffer.scala 406:86] + wire _T_2350 = _T_2144 & _T_1879; // @[lsu_bus_buffer.scala 408:52] + wire _T_2352 = _T_2350 & _T_1856; // @[lsu_bus_buffer.scala 408:73] + wire _T_2353 = _T_2346 | _T_2352; // @[lsu_bus_buffer.scala 407:114] + wire _T_2354 = _T_2333 & _T_2353; // @[lsu_bus_buffer.scala 405:113] + wire _T_2356 = _T_2354 | buf_age_2[0]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2370 = _T_2343 & _T_1865; // @[lsu_bus_buffer.scala 407:92] + wire _T_2371 = _T_4476 | _T_2370; // @[lsu_bus_buffer.scala 406:86] + wire _T_2377 = _T_2350 & _T_1867; // @[lsu_bus_buffer.scala 408:73] + wire _T_2378 = _T_2371 | _T_2377; // @[lsu_bus_buffer.scala 407:114] + wire _T_2379 = _T_2333 & _T_2378; // @[lsu_bus_buffer.scala 405:113] + wire _T_2381 = _T_2379 | buf_age_2[1]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2395 = _T_2343 & _T_1876; // @[lsu_bus_buffer.scala 407:92] + wire _T_2396 = _T_4481 | _T_2395; // @[lsu_bus_buffer.scala 406:86] + wire _T_2402 = _T_2350 & _T_1878; // @[lsu_bus_buffer.scala 408:73] + wire _T_2403 = _T_2396 | _T_2402; // @[lsu_bus_buffer.scala 407:114] + wire _T_2404 = _T_2333 & _T_2403; // @[lsu_bus_buffer.scala 405:113] + wire _T_2406 = _T_2404 | buf_age_2[2]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2420 = _T_2343 & _T_1887; // @[lsu_bus_buffer.scala 407:92] + wire _T_2421 = _T_4486 | _T_2420; // @[lsu_bus_buffer.scala 406:86] + wire _T_2427 = _T_2350 & _T_1889; // @[lsu_bus_buffer.scala 408:73] + wire _T_2428 = _T_2421 | _T_2427; // @[lsu_bus_buffer.scala 407:114] + wire _T_2429 = _T_2333 & _T_2428; // @[lsu_bus_buffer.scala 405:113] + wire _T_2431 = _T_2429 | buf_age_2[3]; // @[lsu_bus_buffer.scala 408:97] wire [2:0] _T_2433 = {_T_2431,_T_2406,_T_2381}; // @[Cat.scala 29:58] - wire _T_4114 = 2'h3 == WrPtr0_r; // @[lsu_bus_buffer.scala 444:117] - wire _T_4115 = _T_3534 & _T_4114; // @[lsu_bus_buffer.scala 444:112] - wire _T_4117 = 2'h3 == WrPtr1_r; // @[lsu_bus_buffer.scala 444:166] - wire _T_4118 = _T_3537 & _T_4117; // @[lsu_bus_buffer.scala 444:161] - wire _T_4119 = _T_4115 | _T_4118; // @[lsu_bus_buffer.scala 444:132] - wire _T_4120 = _T_853 & _T_4119; // @[lsu_bus_buffer.scala 444:63] - wire _T_4121 = 2'h3 == ibuf_tag; // @[lsu_bus_buffer.scala 444:206] - wire _T_4122 = ibuf_drain_vld & _T_4121; // @[lsu_bus_buffer.scala 444:201] - wire _T_4123 = _T_4120 | _T_4122; // @[lsu_bus_buffer.scala 444:183] + wire _T_4114 = 2'h3 == WrPtr0_r; // @[lsu_bus_buffer.scala 443:117] + wire _T_4115 = _T_3532 & _T_4114; // @[lsu_bus_buffer.scala 443:112] + wire _T_4117 = 2'h3 == WrPtr1_r; // @[lsu_bus_buffer.scala 443:166] + wire _T_4118 = _T_3537 & _T_4117; // @[lsu_bus_buffer.scala 443:161] + wire _T_4119 = _T_4115 | _T_4118; // @[lsu_bus_buffer.scala 443:132] + wire _T_4120 = _T_853 & _T_4119; // @[lsu_bus_buffer.scala 443:63] + wire _T_4121 = 2'h3 == ibuf_tag; // @[lsu_bus_buffer.scala 443:206] + wire _T_4122 = ibuf_valid & _T_4121; // @[lsu_bus_buffer.scala 443:201] + wire _T_4123 = _T_4120 | _T_4122; // @[lsu_bus_buffer.scala 443:183] wire _T_4168 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30] - wire _T_4213 = io_lsu_axi_b_bits_id == 3'h3; // @[lsu_bus_buffer.scala 469:73] - wire _T_4214 = bus_rsp_write & _T_4213; // @[lsu_bus_buffer.scala 469:52] - wire _T_4215 = io_lsu_axi_r_bits_id == 3'h3; // @[lsu_bus_buffer.scala 470:46] - wire [2:0] _GEN_380 = {{1'd0}, buf_ldfwdtag_3}; // @[lsu_bus_buffer.scala 471:47] - wire _T_4217 = io_lsu_axi_r_bits_id == _GEN_380; // @[lsu_bus_buffer.scala 471:47] - wire _T_4218 = buf_ldfwd[3] & _T_4217; // @[lsu_bus_buffer.scala 471:27] - wire _T_4219 = _T_4215 | _T_4218; // @[lsu_bus_buffer.scala 470:77] - wire _T_4220 = buf_dual_3 & buf_dualhi_3; // @[lsu_bus_buffer.scala 472:26] - wire _T_4222 = ~buf_write[3]; // @[lsu_bus_buffer.scala 472:44] - wire _T_4223 = _T_4220 & _T_4222; // @[lsu_bus_buffer.scala 472:42] - wire _T_4224 = _T_4223 & buf_samedw_3; // @[lsu_bus_buffer.scala 472:58] + wire _T_4213 = io_lsu_axi_b_bits_id == 3'h3; // @[lsu_bus_buffer.scala 468:73] + wire _T_4214 = bus_rsp_write & _T_4213; // @[lsu_bus_buffer.scala 468:52] + wire _T_4215 = io_lsu_axi_r_bits_id == 3'h3; // @[lsu_bus_buffer.scala 469:46] + wire [2:0] _GEN_380 = {{1'd0}, buf_ldfwdtag_3}; // @[lsu_bus_buffer.scala 470:47] + wire _T_4217 = io_lsu_axi_r_bits_id == _GEN_380; // @[lsu_bus_buffer.scala 470:47] + wire _T_4218 = buf_ldfwd[3] & _T_4217; // @[lsu_bus_buffer.scala 470:27] + wire _T_4219 = _T_4215 | _T_4218; // @[lsu_bus_buffer.scala 469:77] + wire _T_4220 = buf_dual_3 & buf_dualhi_3; // @[lsu_bus_buffer.scala 471:26] + wire _T_4222 = ~buf_write[3]; // @[lsu_bus_buffer.scala 471:44] + wire _T_4223 = _T_4220 & _T_4222; // @[lsu_bus_buffer.scala 471:42] + wire _T_4224 = _T_4223 & buf_samedw_3; // @[lsu_bus_buffer.scala 471:58] reg [1:0] buf_dualtag_3; // @[Reg.scala 27:20] - wire [2:0] _GEN_381 = {{1'd0}, buf_dualtag_3}; // @[lsu_bus_buffer.scala 472:94] - wire _T_4225 = io_lsu_axi_r_bits_id == _GEN_381; // @[lsu_bus_buffer.scala 472:94] - wire _T_4226 = _T_4224 & _T_4225; // @[lsu_bus_buffer.scala 472:74] - wire _T_4227 = _T_4219 | _T_4226; // @[lsu_bus_buffer.scala 471:71] - wire _T_4228 = bus_rsp_read & _T_4227; // @[lsu_bus_buffer.scala 470:25] - wire _T_4229 = _T_4214 | _T_4228; // @[lsu_bus_buffer.scala 469:105] + wire [2:0] _GEN_381 = {{1'd0}, buf_dualtag_3}; // @[lsu_bus_buffer.scala 471:94] + wire _T_4225 = io_lsu_axi_r_bits_id == _GEN_381; // @[lsu_bus_buffer.scala 471:94] + wire _T_4226 = _T_4224 & _T_4225; // @[lsu_bus_buffer.scala 471:74] + wire _T_4227 = _T_4219 | _T_4226; // @[lsu_bus_buffer.scala 470:71] + wire _T_4228 = bus_rsp_read & _T_4227; // @[lsu_bus_buffer.scala 469:25] + wire _T_4229 = _T_4214 | _T_4228; // @[lsu_bus_buffer.scala 468:105] wire _GEN_270 = _T_4168 & _T_4229; // @[Conditional.scala 39:67] wire _GEN_289 = _T_4134 ? 1'h0 : _GEN_270; // @[Conditional.scala 39:67] wire _GEN_301 = _T_4130 ? 1'h0 : _GEN_289; // @[Conditional.scala 39:67] wire buf_resp_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_301; // @[Conditional.scala 40:58] wire _T_4255 = 3'h4 == buf_state_3; // @[Conditional.scala 37:30] - wire [3:0] _T_4265 = buf_ldfwd >> buf_dualtag_3; // @[lsu_bus_buffer.scala 484:21] - wire [1:0] _GEN_251 = 2'h1 == buf_dualtag_3 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 484:58] - wire [1:0] _GEN_252 = 2'h2 == buf_dualtag_3 ? buf_ldfwdtag_2 : _GEN_251; // @[lsu_bus_buffer.scala 484:58] - wire [1:0] _GEN_253 = 2'h3 == buf_dualtag_3 ? buf_ldfwdtag_3 : _GEN_252; // @[lsu_bus_buffer.scala 484:58] - wire [2:0] _GEN_383 = {{1'd0}, _GEN_253}; // @[lsu_bus_buffer.scala 484:58] - wire _T_4267 = io_lsu_axi_r_bits_id == _GEN_383; // @[lsu_bus_buffer.scala 484:58] - wire _T_4268 = _T_4265[0] & _T_4267; // @[lsu_bus_buffer.scala 484:38] - wire _T_4269 = _T_4225 | _T_4268; // @[lsu_bus_buffer.scala 483:95] - wire _T_4270 = bus_rsp_read & _T_4269; // @[lsu_bus_buffer.scala 483:45] + wire [3:0] _T_4265 = buf_ldfwd >> buf_dualtag_3; // @[lsu_bus_buffer.scala 483:21] + wire [1:0] _GEN_251 = 2'h1 == buf_dualtag_3 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[lsu_bus_buffer.scala 483:58] + wire [1:0] _GEN_252 = 2'h2 == buf_dualtag_3 ? buf_ldfwdtag_2 : _GEN_251; // @[lsu_bus_buffer.scala 483:58] + wire [1:0] _GEN_253 = 2'h3 == buf_dualtag_3 ? buf_ldfwdtag_3 : _GEN_252; // @[lsu_bus_buffer.scala 483:58] + wire [2:0] _GEN_383 = {{1'd0}, _GEN_253}; // @[lsu_bus_buffer.scala 483:58] + wire _T_4267 = io_lsu_axi_r_bits_id == _GEN_383; // @[lsu_bus_buffer.scala 483:58] + wire _T_4268 = _T_4265[0] & _T_4267; // @[lsu_bus_buffer.scala 483:38] + wire _T_4269 = _T_4225 | _T_4268; // @[lsu_bus_buffer.scala 482:95] + wire _T_4270 = bus_rsp_read & _T_4269; // @[lsu_bus_buffer.scala 482:45] wire _GEN_264 = _T_4255 & _T_4270; // @[Conditional.scala 39:67] wire _GEN_271 = _T_4168 ? buf_resp_state_bus_en_3 : _GEN_264; // @[Conditional.scala 39:67] wire _GEN_281 = _T_4134 ? buf_cmd_state_bus_en_3 : _GEN_271; // @[Conditional.scala 39:67] wire _GEN_294 = _T_4130 ? 1'h0 : _GEN_281; // @[Conditional.scala 39:67] wire buf_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_294; // @[Conditional.scala 40:58] - wire _T_4147 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 457:49] - wire _T_4148 = _T_4147 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 457:70] + wire _T_4147 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 456:49] + wire _T_4148 = _T_4147 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 456:70] wire _T_4273 = 3'h5 == buf_state_3; // @[Conditional.scala 37:30] - wire _T_4276 = RspPtr == 2'h3; // @[lsu_bus_buffer.scala 489:37] - wire _T_4277 = buf_dualtag_3 == RspPtr; // @[lsu_bus_buffer.scala 489:98] - wire _T_4278 = buf_dual_3 & _T_4277; // @[lsu_bus_buffer.scala 489:80] - wire _T_4279 = _T_4276 | _T_4278; // @[lsu_bus_buffer.scala 489:65] - wire _T_4280 = _T_4279 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 489:112] + wire _T_4276 = RspPtr == 2'h3; // @[lsu_bus_buffer.scala 488:37] + wire _T_4277 = buf_dualtag_3 == RspPtr; // @[lsu_bus_buffer.scala 488:98] + wire _T_4278 = buf_dual_3 & _T_4277; // @[lsu_bus_buffer.scala 488:80] + wire _T_4279 = _T_4276 | _T_4278; // @[lsu_bus_buffer.scala 488:65] + wire _T_4280 = _T_4279 | io_dec_tlu_force_halt; // @[lsu_bus_buffer.scala 488:112] wire _T_4281 = 3'h6 == buf_state_3; // @[Conditional.scala 37:30] wire _GEN_259 = _T_4273 ? _T_4280 : _T_4281; // @[Conditional.scala 39:67] wire _GEN_265 = _T_4255 ? _T_4148 : _GEN_259; // @[Conditional.scala 39:67] @@ -69900,229 +69799,225 @@ module lsu_bus_buffer( wire _GEN_282 = _T_4134 ? _T_4148 : _GEN_272; // @[Conditional.scala 39:67] wire _GEN_292 = _T_4130 ? _T_3554 : _GEN_282; // @[Conditional.scala 39:67] wire buf_state_en_3 = _T_4107 ? _T_4123 : _GEN_292; // @[Conditional.scala 40:58] - wire _T_2435 = _T_1886 & buf_state_en_3; // @[lsu_bus_buffer.scala 406:94] - wire _T_2445 = _T_2137 & _T_1889; // @[lsu_bus_buffer.scala 408:71] - wire _T_2447 = _T_2445 & _T_1854; // @[lsu_bus_buffer.scala 408:92] - wire _T_2448 = _T_4471 | _T_2447; // @[lsu_bus_buffer.scala 407:86] - wire _T_2452 = _T_2144 & _T_1890; // @[lsu_bus_buffer.scala 409:52] - wire _T_2454 = _T_2452 & _T_1856; // @[lsu_bus_buffer.scala 409:73] - wire _T_2455 = _T_2448 | _T_2454; // @[lsu_bus_buffer.scala 408:114] - wire _T_2456 = _T_2435 & _T_2455; // @[lsu_bus_buffer.scala 406:113] - wire _T_2458 = _T_2456 | buf_age_3[0]; // @[lsu_bus_buffer.scala 409:97] - wire _T_2472 = _T_2445 & _T_1865; // @[lsu_bus_buffer.scala 408:92] - wire _T_2473 = _T_4476 | _T_2472; // @[lsu_bus_buffer.scala 407:86] - wire _T_2479 = _T_2452 & _T_1867; // @[lsu_bus_buffer.scala 409:73] - wire _T_2480 = _T_2473 | _T_2479; // @[lsu_bus_buffer.scala 408:114] - wire _T_2481 = _T_2435 & _T_2480; // @[lsu_bus_buffer.scala 406:113] - wire _T_2483 = _T_2481 | buf_age_3[1]; // @[lsu_bus_buffer.scala 409:97] - wire _T_2497 = _T_2445 & _T_1876; // @[lsu_bus_buffer.scala 408:92] - wire _T_2498 = _T_4481 | _T_2497; // @[lsu_bus_buffer.scala 407:86] - wire _T_2504 = _T_2452 & _T_1878; // @[lsu_bus_buffer.scala 409:73] - wire _T_2505 = _T_2498 | _T_2504; // @[lsu_bus_buffer.scala 408:114] - wire _T_2506 = _T_2435 & _T_2505; // @[lsu_bus_buffer.scala 406:113] - wire _T_2508 = _T_2506 | buf_age_3[2]; // @[lsu_bus_buffer.scala 409:97] - wire _T_2522 = _T_2445 & _T_1887; // @[lsu_bus_buffer.scala 408:92] - wire _T_2523 = _T_4486 | _T_2522; // @[lsu_bus_buffer.scala 407:86] - wire _T_2529 = _T_2452 & _T_1889; // @[lsu_bus_buffer.scala 409:73] - wire _T_2530 = _T_2523 | _T_2529; // @[lsu_bus_buffer.scala 408:114] - wire _T_2531 = _T_2435 & _T_2530; // @[lsu_bus_buffer.scala 406:113] - wire _T_2533 = _T_2531 | buf_age_3[3]; // @[lsu_bus_buffer.scala 409:97] + wire _T_2435 = _T_1886 & buf_state_en_3; // @[lsu_bus_buffer.scala 405:94] + wire _T_2445 = _T_2137 & _T_1889; // @[lsu_bus_buffer.scala 407:71] + wire _T_2447 = _T_2445 & _T_1854; // @[lsu_bus_buffer.scala 407:92] + wire _T_2448 = _T_4471 | _T_2447; // @[lsu_bus_buffer.scala 406:86] + wire _T_2452 = _T_2144 & _T_1890; // @[lsu_bus_buffer.scala 408:52] + wire _T_2454 = _T_2452 & _T_1856; // @[lsu_bus_buffer.scala 408:73] + wire _T_2455 = _T_2448 | _T_2454; // @[lsu_bus_buffer.scala 407:114] + wire _T_2456 = _T_2435 & _T_2455; // @[lsu_bus_buffer.scala 405:113] + wire _T_2458 = _T_2456 | buf_age_3[0]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2472 = _T_2445 & _T_1865; // @[lsu_bus_buffer.scala 407:92] + wire _T_2473 = _T_4476 | _T_2472; // @[lsu_bus_buffer.scala 406:86] + wire _T_2479 = _T_2452 & _T_1867; // @[lsu_bus_buffer.scala 408:73] + wire _T_2480 = _T_2473 | _T_2479; // @[lsu_bus_buffer.scala 407:114] + wire _T_2481 = _T_2435 & _T_2480; // @[lsu_bus_buffer.scala 405:113] + wire _T_2483 = _T_2481 | buf_age_3[1]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2497 = _T_2445 & _T_1876; // @[lsu_bus_buffer.scala 407:92] + wire _T_2498 = _T_4481 | _T_2497; // @[lsu_bus_buffer.scala 406:86] + wire _T_2504 = _T_2452 & _T_1878; // @[lsu_bus_buffer.scala 408:73] + wire _T_2505 = _T_2498 | _T_2504; // @[lsu_bus_buffer.scala 407:114] + wire _T_2506 = _T_2435 & _T_2505; // @[lsu_bus_buffer.scala 405:113] + wire _T_2508 = _T_2506 | buf_age_3[2]; // @[lsu_bus_buffer.scala 408:97] + wire _T_2522 = _T_2445 & _T_1887; // @[lsu_bus_buffer.scala 407:92] + wire _T_2523 = _T_4486 | _T_2522; // @[lsu_bus_buffer.scala 406:86] + wire _T_2529 = _T_2452 & _T_1889; // @[lsu_bus_buffer.scala 408:73] + wire _T_2530 = _T_2523 | _T_2529; // @[lsu_bus_buffer.scala 407:114] + wire _T_2531 = _T_2435 & _T_2530; // @[lsu_bus_buffer.scala 405:113] + wire _T_2533 = _T_2531 | buf_age_3[3]; // @[lsu_bus_buffer.scala 408:97] wire [2:0] _T_2535 = {_T_2533,_T_2508,_T_2483}; // @[Cat.scala 29:58] - wire _T_2799 = buf_state_0 == 3'h6; // @[lsu_bus_buffer.scala 417:47] - wire _T_2800 = _T_1853 | _T_2799; // @[lsu_bus_buffer.scala 417:32] - wire _T_2801 = ~_T_2800; // @[lsu_bus_buffer.scala 417:6] - wire _T_2809 = _T_2801 | _T_2141; // @[lsu_bus_buffer.scala 417:59] - wire _T_2816 = _T_2809 | _T_2148; // @[lsu_bus_buffer.scala 418:110] - wire _T_2817 = _T_2129 & _T_2816; // @[lsu_bus_buffer.scala 416:112] - wire _T_2821 = buf_state_1 == 3'h6; // @[lsu_bus_buffer.scala 417:47] - wire _T_2822 = _T_1864 | _T_2821; // @[lsu_bus_buffer.scala 417:32] - wire _T_2823 = ~_T_2822; // @[lsu_bus_buffer.scala 417:6] - wire _T_2831 = _T_2823 | _T_2166; // @[lsu_bus_buffer.scala 417:59] - wire _T_2838 = _T_2831 | _T_2173; // @[lsu_bus_buffer.scala 418:110] - wire _T_2839 = _T_2129 & _T_2838; // @[lsu_bus_buffer.scala 416:112] - wire _T_2843 = buf_state_2 == 3'h6; // @[lsu_bus_buffer.scala 417:47] - wire _T_2844 = _T_1875 | _T_2843; // @[lsu_bus_buffer.scala 417:32] - wire _T_2845 = ~_T_2844; // @[lsu_bus_buffer.scala 417:6] - wire _T_2853 = _T_2845 | _T_2191; // @[lsu_bus_buffer.scala 417:59] - wire _T_2860 = _T_2853 | _T_2198; // @[lsu_bus_buffer.scala 418:110] - wire _T_2861 = _T_2129 & _T_2860; // @[lsu_bus_buffer.scala 416:112] - wire _T_2865 = buf_state_3 == 3'h6; // @[lsu_bus_buffer.scala 417:47] - wire _T_2866 = _T_1886 | _T_2865; // @[lsu_bus_buffer.scala 417:32] - wire _T_2867 = ~_T_2866; // @[lsu_bus_buffer.scala 417:6] - wire _T_2875 = _T_2867 | _T_2216; // @[lsu_bus_buffer.scala 417:59] - wire _T_2882 = _T_2875 | _T_2223; // @[lsu_bus_buffer.scala 418:110] - wire _T_2883 = _T_2129 & _T_2882; // @[lsu_bus_buffer.scala 416:112] + wire _T_2799 = buf_state_0 == 3'h6; // @[lsu_bus_buffer.scala 416:47] + wire _T_2800 = _T_1853 | _T_2799; // @[lsu_bus_buffer.scala 416:32] + wire _T_2801 = ~_T_2800; // @[lsu_bus_buffer.scala 416:6] + wire _T_2809 = _T_2801 | _T_2141; // @[lsu_bus_buffer.scala 416:59] + wire _T_2816 = _T_2809 | _T_2148; // @[lsu_bus_buffer.scala 417:110] + wire _T_2817 = _T_2129 & _T_2816; // @[lsu_bus_buffer.scala 415:112] + wire _T_2821 = buf_state_1 == 3'h6; // @[lsu_bus_buffer.scala 416:47] + wire _T_2822 = _T_1864 | _T_2821; // @[lsu_bus_buffer.scala 416:32] + wire _T_2823 = ~_T_2822; // @[lsu_bus_buffer.scala 416:6] + wire _T_2831 = _T_2823 | _T_2166; // @[lsu_bus_buffer.scala 416:59] + wire _T_2838 = _T_2831 | _T_2173; // @[lsu_bus_buffer.scala 417:110] + wire _T_2839 = _T_2129 & _T_2838; // @[lsu_bus_buffer.scala 415:112] + wire _T_2843 = buf_state_2 == 3'h6; // @[lsu_bus_buffer.scala 416:47] + wire _T_2844 = _T_1875 | _T_2843; // @[lsu_bus_buffer.scala 416:32] + wire _T_2845 = ~_T_2844; // @[lsu_bus_buffer.scala 416:6] + wire _T_2853 = _T_2845 | _T_2191; // @[lsu_bus_buffer.scala 416:59] + wire _T_2860 = _T_2853 | _T_2198; // @[lsu_bus_buffer.scala 417:110] + wire _T_2861 = _T_2129 & _T_2860; // @[lsu_bus_buffer.scala 415:112] + wire _T_2865 = buf_state_3 == 3'h6; // @[lsu_bus_buffer.scala 416:47] + wire _T_2866 = _T_1886 | _T_2865; // @[lsu_bus_buffer.scala 416:32] + wire _T_2867 = ~_T_2866; // @[lsu_bus_buffer.scala 416:6] + wire _T_2875 = _T_2867 | _T_2216; // @[lsu_bus_buffer.scala 416:59] + wire _T_2882 = _T_2875 | _T_2223; // @[lsu_bus_buffer.scala 417:110] + wire _T_2883 = _T_2129 & _T_2882; // @[lsu_bus_buffer.scala 415:112] wire [3:0] buf_rspage_set_0 = {_T_2883,_T_2861,_T_2839,_T_2817}; // @[Cat.scala 29:58] - wire _T_2900 = _T_2801 | _T_2243; // @[lsu_bus_buffer.scala 417:59] - wire _T_2907 = _T_2900 | _T_2250; // @[lsu_bus_buffer.scala 418:110] - wire _T_2908 = _T_2231 & _T_2907; // @[lsu_bus_buffer.scala 416:112] - wire _T_2922 = _T_2823 | _T_2268; // @[lsu_bus_buffer.scala 417:59] - wire _T_2929 = _T_2922 | _T_2275; // @[lsu_bus_buffer.scala 418:110] - wire _T_2930 = _T_2231 & _T_2929; // @[lsu_bus_buffer.scala 416:112] - wire _T_2944 = _T_2845 | _T_2293; // @[lsu_bus_buffer.scala 417:59] - wire _T_2951 = _T_2944 | _T_2300; // @[lsu_bus_buffer.scala 418:110] - wire _T_2952 = _T_2231 & _T_2951; // @[lsu_bus_buffer.scala 416:112] - wire _T_2966 = _T_2867 | _T_2318; // @[lsu_bus_buffer.scala 417:59] - wire _T_2973 = _T_2966 | _T_2325; // @[lsu_bus_buffer.scala 418:110] - wire _T_2974 = _T_2231 & _T_2973; // @[lsu_bus_buffer.scala 416:112] + wire _T_2900 = _T_2801 | _T_2243; // @[lsu_bus_buffer.scala 416:59] + wire _T_2907 = _T_2900 | _T_2250; // @[lsu_bus_buffer.scala 417:110] + wire _T_2908 = _T_2231 & _T_2907; // @[lsu_bus_buffer.scala 415:112] + wire _T_2922 = _T_2823 | _T_2268; // @[lsu_bus_buffer.scala 416:59] + wire _T_2929 = _T_2922 | _T_2275; // @[lsu_bus_buffer.scala 417:110] + wire _T_2930 = _T_2231 & _T_2929; // @[lsu_bus_buffer.scala 415:112] + wire _T_2944 = _T_2845 | _T_2293; // @[lsu_bus_buffer.scala 416:59] + wire _T_2951 = _T_2944 | _T_2300; // @[lsu_bus_buffer.scala 417:110] + wire _T_2952 = _T_2231 & _T_2951; // @[lsu_bus_buffer.scala 415:112] + wire _T_2966 = _T_2867 | _T_2318; // @[lsu_bus_buffer.scala 416:59] + wire _T_2973 = _T_2966 | _T_2325; // @[lsu_bus_buffer.scala 417:110] + wire _T_2974 = _T_2231 & _T_2973; // @[lsu_bus_buffer.scala 415:112] wire [3:0] buf_rspage_set_1 = {_T_2974,_T_2952,_T_2930,_T_2908}; // @[Cat.scala 29:58] - wire _T_2991 = _T_2801 | _T_2345; // @[lsu_bus_buffer.scala 417:59] - wire _T_2998 = _T_2991 | _T_2352; // @[lsu_bus_buffer.scala 418:110] - wire _T_2999 = _T_2333 & _T_2998; // @[lsu_bus_buffer.scala 416:112] - wire _T_3013 = _T_2823 | _T_2370; // @[lsu_bus_buffer.scala 417:59] - wire _T_3020 = _T_3013 | _T_2377; // @[lsu_bus_buffer.scala 418:110] - wire _T_3021 = _T_2333 & _T_3020; // @[lsu_bus_buffer.scala 416:112] - wire _T_3035 = _T_2845 | _T_2395; // @[lsu_bus_buffer.scala 417:59] - wire _T_3042 = _T_3035 | _T_2402; // @[lsu_bus_buffer.scala 418:110] - wire _T_3043 = _T_2333 & _T_3042; // @[lsu_bus_buffer.scala 416:112] - wire _T_3057 = _T_2867 | _T_2420; // @[lsu_bus_buffer.scala 417:59] - wire _T_3064 = _T_3057 | _T_2427; // @[lsu_bus_buffer.scala 418:110] - wire _T_3065 = _T_2333 & _T_3064; // @[lsu_bus_buffer.scala 416:112] + wire _T_2991 = _T_2801 | _T_2345; // @[lsu_bus_buffer.scala 416:59] + wire _T_2998 = _T_2991 | _T_2352; // @[lsu_bus_buffer.scala 417:110] + wire _T_2999 = _T_2333 & _T_2998; // @[lsu_bus_buffer.scala 415:112] + wire _T_3013 = _T_2823 | _T_2370; // @[lsu_bus_buffer.scala 416:59] + wire _T_3020 = _T_3013 | _T_2377; // @[lsu_bus_buffer.scala 417:110] + wire _T_3021 = _T_2333 & _T_3020; // @[lsu_bus_buffer.scala 415:112] + wire _T_3035 = _T_2845 | _T_2395; // @[lsu_bus_buffer.scala 416:59] + wire _T_3042 = _T_3035 | _T_2402; // @[lsu_bus_buffer.scala 417:110] + wire _T_3043 = _T_2333 & _T_3042; // @[lsu_bus_buffer.scala 415:112] + wire _T_3057 = _T_2867 | _T_2420; // @[lsu_bus_buffer.scala 416:59] + wire _T_3064 = _T_3057 | _T_2427; // @[lsu_bus_buffer.scala 417:110] + wire _T_3065 = _T_2333 & _T_3064; // @[lsu_bus_buffer.scala 415:112] wire [3:0] buf_rspage_set_2 = {_T_3065,_T_3043,_T_3021,_T_2999}; // @[Cat.scala 29:58] - wire _T_3082 = _T_2801 | _T_2447; // @[lsu_bus_buffer.scala 417:59] - wire _T_3089 = _T_3082 | _T_2454; // @[lsu_bus_buffer.scala 418:110] - wire _T_3090 = _T_2435 & _T_3089; // @[lsu_bus_buffer.scala 416:112] - wire _T_3104 = _T_2823 | _T_2472; // @[lsu_bus_buffer.scala 417:59] - wire _T_3111 = _T_3104 | _T_2479; // @[lsu_bus_buffer.scala 418:110] - wire _T_3112 = _T_2435 & _T_3111; // @[lsu_bus_buffer.scala 416:112] - wire _T_3126 = _T_2845 | _T_2497; // @[lsu_bus_buffer.scala 417:59] - wire _T_3133 = _T_3126 | _T_2504; // @[lsu_bus_buffer.scala 418:110] - wire _T_3134 = _T_2435 & _T_3133; // @[lsu_bus_buffer.scala 416:112] - wire _T_3148 = _T_2867 | _T_2522; // @[lsu_bus_buffer.scala 417:59] - wire _T_3155 = _T_3148 | _T_2529; // @[lsu_bus_buffer.scala 418:110] - wire _T_3156 = _T_2435 & _T_3155; // @[lsu_bus_buffer.scala 416:112] + wire _T_3082 = _T_2801 | _T_2447; // @[lsu_bus_buffer.scala 416:59] + wire _T_3089 = _T_3082 | _T_2454; // @[lsu_bus_buffer.scala 417:110] + wire _T_3090 = _T_2435 & _T_3089; // @[lsu_bus_buffer.scala 415:112] + wire _T_3104 = _T_2823 | _T_2472; // @[lsu_bus_buffer.scala 416:59] + wire _T_3111 = _T_3104 | _T_2479; // @[lsu_bus_buffer.scala 417:110] + wire _T_3112 = _T_2435 & _T_3111; // @[lsu_bus_buffer.scala 415:112] + wire _T_3126 = _T_2845 | _T_2497; // @[lsu_bus_buffer.scala 416:59] + wire _T_3133 = _T_3126 | _T_2504; // @[lsu_bus_buffer.scala 417:110] + wire _T_3134 = _T_2435 & _T_3133; // @[lsu_bus_buffer.scala 415:112] + wire _T_3148 = _T_2867 | _T_2522; // @[lsu_bus_buffer.scala 416:59] + wire _T_3155 = _T_3148 | _T_2529; // @[lsu_bus_buffer.scala 417:110] + wire _T_3156 = _T_2435 & _T_3155; // @[lsu_bus_buffer.scala 415:112] wire [3:0] buf_rspage_set_3 = {_T_3156,_T_3134,_T_3112,_T_3090}; // @[Cat.scala 29:58] - wire _T_3241 = _T_2865 | _T_1886; // @[lsu_bus_buffer.scala 421:110] - wire _T_3242 = ~_T_3241; // @[lsu_bus_buffer.scala 421:84] - wire _T_3243 = buf_rspageQ_0[3] & _T_3242; // @[lsu_bus_buffer.scala 421:82] - wire _T_3235 = _T_2843 | _T_1875; // @[lsu_bus_buffer.scala 421:110] - wire _T_3236 = ~_T_3235; // @[lsu_bus_buffer.scala 421:84] - wire _T_3237 = buf_rspageQ_0[2] & _T_3236; // @[lsu_bus_buffer.scala 421:82] - wire _T_3229 = _T_2821 | _T_1864; // @[lsu_bus_buffer.scala 421:110] - wire _T_3230 = ~_T_3229; // @[lsu_bus_buffer.scala 421:84] - wire _T_3231 = buf_rspageQ_0[1] & _T_3230; // @[lsu_bus_buffer.scala 421:82] - wire _T_3223 = _T_2799 | _T_1853; // @[lsu_bus_buffer.scala 421:110] - wire _T_3224 = ~_T_3223; // @[lsu_bus_buffer.scala 421:84] - wire _T_3225 = buf_rspageQ_0[0] & _T_3224; // @[lsu_bus_buffer.scala 421:82] + wire _T_3241 = _T_2865 | _T_1886; // @[lsu_bus_buffer.scala 420:110] + wire _T_3242 = ~_T_3241; // @[lsu_bus_buffer.scala 420:84] + wire _T_3243 = buf_rspageQ_0[3] & _T_3242; // @[lsu_bus_buffer.scala 420:82] + wire _T_3235 = _T_2843 | _T_1875; // @[lsu_bus_buffer.scala 420:110] + wire _T_3236 = ~_T_3235; // @[lsu_bus_buffer.scala 420:84] + wire _T_3237 = buf_rspageQ_0[2] & _T_3236; // @[lsu_bus_buffer.scala 420:82] + wire _T_3229 = _T_2821 | _T_1864; // @[lsu_bus_buffer.scala 420:110] + wire _T_3230 = ~_T_3229; // @[lsu_bus_buffer.scala 420:84] + wire _T_3231 = buf_rspageQ_0[1] & _T_3230; // @[lsu_bus_buffer.scala 420:82] + wire _T_3223 = _T_2799 | _T_1853; // @[lsu_bus_buffer.scala 420:110] + wire _T_3224 = ~_T_3223; // @[lsu_bus_buffer.scala 420:84] + wire _T_3225 = buf_rspageQ_0[0] & _T_3224; // @[lsu_bus_buffer.scala 420:82] wire [3:0] buf_rspage_0 = {_T_3243,_T_3237,_T_3231,_T_3225}; // @[Cat.scala 29:58] - wire _T_3162 = buf_rspage_set_0[0] | buf_rspage_0[0]; // @[lsu_bus_buffer.scala 420:88] - wire _T_3165 = buf_rspage_set_0[1] | buf_rspage_0[1]; // @[lsu_bus_buffer.scala 420:88] - wire _T_3168 = buf_rspage_set_0[2] | buf_rspage_0[2]; // @[lsu_bus_buffer.scala 420:88] - wire _T_3171 = buf_rspage_set_0[3] | buf_rspage_0[3]; // @[lsu_bus_buffer.scala 420:88] + wire _T_3162 = buf_rspage_set_0[0] | buf_rspage_0[0]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3165 = buf_rspage_set_0[1] | buf_rspage_0[1]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3168 = buf_rspage_set_0[2] | buf_rspage_0[2]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3171 = buf_rspage_set_0[3] | buf_rspage_0[3]; // @[lsu_bus_buffer.scala 419:88] wire [2:0] _T_3173 = {_T_3171,_T_3168,_T_3165}; // @[Cat.scala 29:58] - wire _T_3270 = buf_rspageQ_1[3] & _T_3242; // @[lsu_bus_buffer.scala 421:82] - wire _T_3264 = buf_rspageQ_1[2] & _T_3236; // @[lsu_bus_buffer.scala 421:82] - wire _T_3258 = buf_rspageQ_1[1] & _T_3230; // @[lsu_bus_buffer.scala 421:82] - wire _T_3252 = buf_rspageQ_1[0] & _T_3224; // @[lsu_bus_buffer.scala 421:82] + wire _T_3270 = buf_rspageQ_1[3] & _T_3242; // @[lsu_bus_buffer.scala 420:82] + wire _T_3264 = buf_rspageQ_1[2] & _T_3236; // @[lsu_bus_buffer.scala 420:82] + wire _T_3258 = buf_rspageQ_1[1] & _T_3230; // @[lsu_bus_buffer.scala 420:82] + wire _T_3252 = buf_rspageQ_1[0] & _T_3224; // @[lsu_bus_buffer.scala 420:82] wire [3:0] buf_rspage_1 = {_T_3270,_T_3264,_T_3258,_T_3252}; // @[Cat.scala 29:58] - wire _T_3177 = buf_rspage_set_1[0] | buf_rspage_1[0]; // @[lsu_bus_buffer.scala 420:88] - wire _T_3180 = buf_rspage_set_1[1] | buf_rspage_1[1]; // @[lsu_bus_buffer.scala 420:88] - wire _T_3183 = buf_rspage_set_1[2] | buf_rspage_1[2]; // @[lsu_bus_buffer.scala 420:88] - wire _T_3186 = buf_rspage_set_1[3] | buf_rspage_1[3]; // @[lsu_bus_buffer.scala 420:88] + wire _T_3177 = buf_rspage_set_1[0] | buf_rspage_1[0]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3180 = buf_rspage_set_1[1] | buf_rspage_1[1]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3183 = buf_rspage_set_1[2] | buf_rspage_1[2]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3186 = buf_rspage_set_1[3] | buf_rspage_1[3]; // @[lsu_bus_buffer.scala 419:88] wire [2:0] _T_3188 = {_T_3186,_T_3183,_T_3180}; // @[Cat.scala 29:58] - wire _T_3297 = buf_rspageQ_2[3] & _T_3242; // @[lsu_bus_buffer.scala 421:82] - wire _T_3291 = buf_rspageQ_2[2] & _T_3236; // @[lsu_bus_buffer.scala 421:82] - wire _T_3285 = buf_rspageQ_2[1] & _T_3230; // @[lsu_bus_buffer.scala 421:82] - wire _T_3279 = buf_rspageQ_2[0] & _T_3224; // @[lsu_bus_buffer.scala 421:82] + wire _T_3297 = buf_rspageQ_2[3] & _T_3242; // @[lsu_bus_buffer.scala 420:82] + wire _T_3291 = buf_rspageQ_2[2] & _T_3236; // @[lsu_bus_buffer.scala 420:82] + wire _T_3285 = buf_rspageQ_2[1] & _T_3230; // @[lsu_bus_buffer.scala 420:82] + wire _T_3279 = buf_rspageQ_2[0] & _T_3224; // @[lsu_bus_buffer.scala 420:82] wire [3:0] buf_rspage_2 = {_T_3297,_T_3291,_T_3285,_T_3279}; // @[Cat.scala 29:58] - wire _T_3192 = buf_rspage_set_2[0] | buf_rspage_2[0]; // @[lsu_bus_buffer.scala 420:88] - wire _T_3195 = buf_rspage_set_2[1] | buf_rspage_2[1]; // @[lsu_bus_buffer.scala 420:88] - wire _T_3198 = buf_rspage_set_2[2] | buf_rspage_2[2]; // @[lsu_bus_buffer.scala 420:88] - wire _T_3201 = buf_rspage_set_2[3] | buf_rspage_2[3]; // @[lsu_bus_buffer.scala 420:88] + wire _T_3192 = buf_rspage_set_2[0] | buf_rspage_2[0]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3195 = buf_rspage_set_2[1] | buf_rspage_2[1]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3198 = buf_rspage_set_2[2] | buf_rspage_2[2]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3201 = buf_rspage_set_2[3] | buf_rspage_2[3]; // @[lsu_bus_buffer.scala 419:88] wire [2:0] _T_3203 = {_T_3201,_T_3198,_T_3195}; // @[Cat.scala 29:58] - wire _T_3324 = buf_rspageQ_3[3] & _T_3242; // @[lsu_bus_buffer.scala 421:82] - wire _T_3318 = buf_rspageQ_3[2] & _T_3236; // @[lsu_bus_buffer.scala 421:82] - wire _T_3312 = buf_rspageQ_3[1] & _T_3230; // @[lsu_bus_buffer.scala 421:82] - wire _T_3306 = buf_rspageQ_3[0] & _T_3224; // @[lsu_bus_buffer.scala 421:82] + wire _T_3324 = buf_rspageQ_3[3] & _T_3242; // @[lsu_bus_buffer.scala 420:82] + wire _T_3318 = buf_rspageQ_3[2] & _T_3236; // @[lsu_bus_buffer.scala 420:82] + wire _T_3312 = buf_rspageQ_3[1] & _T_3230; // @[lsu_bus_buffer.scala 420:82] + wire _T_3306 = buf_rspageQ_3[0] & _T_3224; // @[lsu_bus_buffer.scala 420:82] wire [3:0] buf_rspage_3 = {_T_3324,_T_3318,_T_3312,_T_3306}; // @[Cat.scala 29:58] - wire _T_3207 = buf_rspage_set_3[0] | buf_rspage_3[0]; // @[lsu_bus_buffer.scala 420:88] - wire _T_3210 = buf_rspage_set_3[1] | buf_rspage_3[1]; // @[lsu_bus_buffer.scala 420:88] - wire _T_3213 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[lsu_bus_buffer.scala 420:88] - wire _T_3216 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[lsu_bus_buffer.scala 420:88] + wire _T_3207 = buf_rspage_set_3[0] | buf_rspage_3[0]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3210 = buf_rspage_set_3[1] | buf_rspage_3[1]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3213 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[lsu_bus_buffer.scala 419:88] + wire _T_3216 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[lsu_bus_buffer.scala 419:88] wire [2:0] _T_3218 = {_T_3216,_T_3213,_T_3210}; // @[Cat.scala 29:58] - wire _T_3329 = ibuf_drain_vld & _T_1854; // @[lsu_bus_buffer.scala 426:63] - wire _T_3331 = ibuf_drain_vld & _T_1865; // @[lsu_bus_buffer.scala 426:63] - wire _T_3333 = ibuf_drain_vld & _T_1876; // @[lsu_bus_buffer.scala 426:63] - wire _T_3335 = ibuf_drain_vld & _T_1887; // @[lsu_bus_buffer.scala 426:63] - wire [3:0] ibuf_drainvec_vld = {_T_3335,_T_3333,_T_3331,_T_3329}; // @[Cat.scala 29:58] - wire _T_3343 = _T_3537 & _T_1857; // @[lsu_bus_buffer.scala 428:35] - wire _T_3352 = _T_3537 & _T_1868; // @[lsu_bus_buffer.scala 428:35] - wire _T_3361 = _T_3537 & _T_1879; // @[lsu_bus_buffer.scala 428:35] - wire _T_3370 = _T_3537 & _T_1890; // @[lsu_bus_buffer.scala 428:35] - wire _T_3400 = ibuf_drainvec_vld[0] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 430:45] - wire _T_3402 = ibuf_drainvec_vld[1] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 430:45] - wire _T_3404 = ibuf_drainvec_vld[2] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 430:45] - wire _T_3406 = ibuf_drainvec_vld[3] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 430:45] + wire [3:0] ibuf_drainvec_vld = {_T_1888,_T_1877,_T_1866,_T_1855}; // @[Cat.scala 29:58] + wire _T_3343 = _T_3537 & _T_1857; // @[lsu_bus_buffer.scala 427:35] + wire _T_3352 = _T_3537 & _T_1868; // @[lsu_bus_buffer.scala 427:35] + wire _T_3361 = _T_3537 & _T_1879; // @[lsu_bus_buffer.scala 427:35] + wire _T_3370 = _T_3537 & _T_1890; // @[lsu_bus_buffer.scala 427:35] + wire _T_3400 = ibuf_drainvec_vld[0] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 429:45] + wire _T_3402 = ibuf_drainvec_vld[1] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 429:45] + wire _T_3404 = ibuf_drainvec_vld[2] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 429:45] + wire _T_3406 = ibuf_drainvec_vld[3] ? ibuf_dual : io_ldst_dual_r; // @[lsu_bus_buffer.scala 429:45] wire [3:0] buf_dual_in = {_T_3406,_T_3404,_T_3402,_T_3400}; // @[Cat.scala 29:58] - wire _T_3411 = ibuf_drainvec_vld[0] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 431:47] - wire _T_3413 = ibuf_drainvec_vld[1] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 431:47] - wire _T_3415 = ibuf_drainvec_vld[2] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 431:47] - wire _T_3417 = ibuf_drainvec_vld[3] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 431:47] + wire _T_3411 = ibuf_drainvec_vld[0] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 430:47] + wire _T_3413 = ibuf_drainvec_vld[1] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 430:47] + wire _T_3415 = ibuf_drainvec_vld[2] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 430:47] + wire _T_3417 = ibuf_drainvec_vld[3] ? ibuf_samedw : ldst_samedw_r; // @[lsu_bus_buffer.scala 430:47] wire [3:0] buf_samedw_in = {_T_3417,_T_3415,_T_3413,_T_3411}; // @[Cat.scala 29:58] - wire _T_3422 = ibuf_nomerge | ibuf_force_drain; // @[lsu_bus_buffer.scala 432:84] - wire _T_3423 = ibuf_drainvec_vld[0] ? _T_3422 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 432:48] - wire _T_3426 = ibuf_drainvec_vld[1] ? _T_3422 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 432:48] - wire _T_3429 = ibuf_drainvec_vld[2] ? _T_3422 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 432:48] - wire _T_3432 = ibuf_drainvec_vld[3] ? _T_3422 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 432:48] + wire _T_3422 = ibuf_nomerge | ibuf_force_drain; // @[lsu_bus_buffer.scala 431:84] + wire _T_3423 = ibuf_drainvec_vld[0] ? _T_3422 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 431:48] + wire _T_3426 = ibuf_drainvec_vld[1] ? _T_3422 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 431:48] + wire _T_3429 = ibuf_drainvec_vld[2] ? _T_3422 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 431:48] + wire _T_3432 = ibuf_drainvec_vld[3] ? _T_3422 : io_no_dword_merge_r; // @[lsu_bus_buffer.scala 431:48] wire [3:0] buf_nomerge_in = {_T_3432,_T_3429,_T_3426,_T_3423}; // @[Cat.scala 29:58] - wire _T_3440 = ibuf_drainvec_vld[0] ? ibuf_dual : _T_3343; // @[lsu_bus_buffer.scala 433:47] - wire _T_3445 = ibuf_drainvec_vld[1] ? ibuf_dual : _T_3352; // @[lsu_bus_buffer.scala 433:47] - wire _T_3450 = ibuf_drainvec_vld[2] ? ibuf_dual : _T_3361; // @[lsu_bus_buffer.scala 433:47] - wire _T_3455 = ibuf_drainvec_vld[3] ? ibuf_dual : _T_3370; // @[lsu_bus_buffer.scala 433:47] + wire _T_3440 = ibuf_drainvec_vld[0] ? ibuf_dual : _T_3343; // @[lsu_bus_buffer.scala 432:47] + wire _T_3445 = ibuf_drainvec_vld[1] ? ibuf_dual : _T_3352; // @[lsu_bus_buffer.scala 432:47] + wire _T_3450 = ibuf_drainvec_vld[2] ? ibuf_dual : _T_3361; // @[lsu_bus_buffer.scala 432:47] + wire _T_3455 = ibuf_drainvec_vld[3] ? ibuf_dual : _T_3370; // @[lsu_bus_buffer.scala 432:47] wire [3:0] buf_dualhi_in = {_T_3455,_T_3450,_T_3445,_T_3440}; // @[Cat.scala 29:58] - wire _T_3484 = ibuf_drainvec_vld[0] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 435:51] - wire _T_3486 = ibuf_drainvec_vld[1] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 435:51] - wire _T_3488 = ibuf_drainvec_vld[2] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 435:51] - wire _T_3490 = ibuf_drainvec_vld[3] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 435:51] + wire _T_3484 = ibuf_drainvec_vld[0] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 434:51] + wire _T_3486 = ibuf_drainvec_vld[1] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 434:51] + wire _T_3488 = ibuf_drainvec_vld[2] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 434:51] + wire _T_3490 = ibuf_drainvec_vld[3] ? ibuf_sideeffect : io_is_sideeffects_r; // @[lsu_bus_buffer.scala 434:51] wire [3:0] buf_sideeffect_in = {_T_3490,_T_3488,_T_3486,_T_3484}; // @[Cat.scala 29:58] - wire _T_3495 = ibuf_drainvec_vld[0] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 436:47] - wire _T_3497 = ibuf_drainvec_vld[1] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 436:47] - wire _T_3499 = ibuf_drainvec_vld[2] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 436:47] - wire _T_3501 = ibuf_drainvec_vld[3] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 436:47] + wire _T_3495 = ibuf_drainvec_vld[0] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 435:47] + wire _T_3497 = ibuf_drainvec_vld[1] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 435:47] + wire _T_3499 = ibuf_drainvec_vld[2] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 435:47] + wire _T_3501 = ibuf_drainvec_vld[3] ? ibuf_unsign : io_lsu_pkt_r_bits_unsign; // @[lsu_bus_buffer.scala 435:47] wire [3:0] buf_unsign_in = {_T_3501,_T_3499,_T_3497,_T_3495}; // @[Cat.scala 29:58] - wire _T_3518 = ibuf_drainvec_vld[0] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 438:46] - wire _T_3520 = ibuf_drainvec_vld[1] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 438:46] - wire _T_3522 = ibuf_drainvec_vld[2] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 438:46] - wire _T_3524 = ibuf_drainvec_vld[3] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 438:46] + wire _T_3518 = ibuf_drainvec_vld[0] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 437:46] + wire _T_3520 = ibuf_drainvec_vld[1] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 437:46] + wire _T_3522 = ibuf_drainvec_vld[2] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 437:46] + wire _T_3524 = ibuf_drainvec_vld[3] ? ibuf_write : io_lsu_pkt_r_bits_store; // @[lsu_bus_buffer.scala 437:46] wire [3:0] buf_write_in = {_T_3524,_T_3522,_T_3520,_T_3518}; // @[Cat.scala 29:58] - wire _T_3557 = obuf_nosend & bus_rsp_read; // @[lsu_bus_buffer.scala 454:89] - wire _T_3559 = _T_3557 & _T_1351; // @[lsu_bus_buffer.scala 454:104] - wire _T_3572 = buf_state_en_0 & _T_3643; // @[lsu_bus_buffer.scala 459:44] - wire _T_3573 = _T_3572 & obuf_nosend; // @[lsu_bus_buffer.scala 459:60] - wire _T_3575 = _T_3573 & _T_1333; // @[lsu_bus_buffer.scala 459:74] - wire _T_3578 = _T_3568 & obuf_nosend; // @[lsu_bus_buffer.scala 461:67] - wire _T_3579 = _T_3578 & bus_rsp_read; // @[lsu_bus_buffer.scala 461:81] - wire _T_4869 = io_lsu_axi_r_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 565:64] - wire bus_rsp_read_error = bus_rsp_read & _T_4869; // @[lsu_bus_buffer.scala 565:38] - wire _T_3582 = _T_3578 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 462:82] - wire _T_3657 = bus_rsp_read_error & _T_3636; // @[lsu_bus_buffer.scala 476:91] - wire _T_3659 = bus_rsp_read_error & buf_ldfwd[0]; // @[lsu_bus_buffer.scala 477:31] - wire _T_3661 = _T_3659 & _T_3638; // @[lsu_bus_buffer.scala 477:46] - wire _T_3662 = _T_3657 | _T_3661; // @[lsu_bus_buffer.scala 476:143] - wire _T_4867 = io_lsu_axi_b_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 564:66] - wire bus_rsp_write_error = bus_rsp_write & _T_4867; // @[lsu_bus_buffer.scala 564:40] - wire _T_3665 = bus_rsp_write_error & _T_3634; // @[lsu_bus_buffer.scala 478:53] - wire _T_3666 = _T_3662 | _T_3665; // @[lsu_bus_buffer.scala 477:88] - wire _T_3667 = _T_3568 & _T_3666; // @[lsu_bus_buffer.scala 476:68] + wire _T_3557 = obuf_nosend & bus_rsp_read; // @[lsu_bus_buffer.scala 453:89] + wire _T_3559 = _T_3557 & _T_1351; // @[lsu_bus_buffer.scala 453:104] + wire _T_3572 = buf_state_en_0 & _T_3643; // @[lsu_bus_buffer.scala 458:44] + wire _T_3573 = _T_3572 & obuf_nosend; // @[lsu_bus_buffer.scala 458:60] + wire _T_3575 = _T_3573 & _T_1333; // @[lsu_bus_buffer.scala 458:74] + wire _T_3578 = _T_3568 & obuf_nosend; // @[lsu_bus_buffer.scala 460:67] + wire _T_3579 = _T_3578 & bus_rsp_read; // @[lsu_bus_buffer.scala 460:81] + wire _T_4869 = io_lsu_axi_r_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 564:64] + wire bus_rsp_read_error = bus_rsp_read & _T_4869; // @[lsu_bus_buffer.scala 564:38] + wire _T_3582 = _T_3578 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 461:82] + wire _T_3657 = bus_rsp_read_error & _T_3636; // @[lsu_bus_buffer.scala 475:91] + wire _T_3659 = bus_rsp_read_error & buf_ldfwd[0]; // @[lsu_bus_buffer.scala 476:31] + wire _T_3661 = _T_3659 & _T_3638; // @[lsu_bus_buffer.scala 476:46] + wire _T_3662 = _T_3657 | _T_3661; // @[lsu_bus_buffer.scala 475:143] + wire _T_4867 = io_lsu_axi_b_bits_resp != 2'h0; // @[lsu_bus_buffer.scala 563:66] + wire bus_rsp_write_error = bus_rsp_write & _T_4867; // @[lsu_bus_buffer.scala 563:40] + wire _T_3665 = bus_rsp_write_error & _T_3634; // @[lsu_bus_buffer.scala 477:53] + wire _T_3666 = _T_3662 | _T_3665; // @[lsu_bus_buffer.scala 476:88] + wire _T_3667 = _T_3568 & _T_3666; // @[lsu_bus_buffer.scala 475:68] wire _GEN_46 = _T_3589 & _T_3667; // @[Conditional.scala 39:67] wire _GEN_59 = _T_3555 ? _T_3582 : _GEN_46; // @[Conditional.scala 39:67] wire _GEN_71 = _T_3551 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] wire buf_error_en_0 = _T_3528 ? 1'h0 : _GEN_71; // @[Conditional.scala 40:58] - wire _T_3592 = ~bus_rsp_write_error; // @[lsu_bus_buffer.scala 466:73] - wire _T_3593 = buf_write[0] & _T_3592; // @[lsu_bus_buffer.scala 466:71] - wire _T_3594 = io_dec_tlu_force_halt | _T_3593; // @[lsu_bus_buffer.scala 466:55] - wire _T_3596 = ~buf_samedw_0; // @[lsu_bus_buffer.scala 467:30] - wire _T_3597 = buf_dual_0 & _T_3596; // @[lsu_bus_buffer.scala 467:28] - wire _T_3600 = _T_3597 & _T_3643; // @[lsu_bus_buffer.scala 467:45] - wire [2:0] _GEN_19 = 2'h1 == buf_dualtag_0 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 467:90] - wire [2:0] _GEN_20 = 2'h2 == buf_dualtag_0 ? buf_state_2 : _GEN_19; // @[lsu_bus_buffer.scala 467:90] - wire [2:0] _GEN_21 = 2'h3 == buf_dualtag_0 ? buf_state_3 : _GEN_20; // @[lsu_bus_buffer.scala 467:90] - wire _T_3601 = _GEN_21 != 3'h4; // @[lsu_bus_buffer.scala 467:90] - wire _T_3602 = _T_3600 & _T_3601; // @[lsu_bus_buffer.scala 467:61] - wire _T_4494 = _T_2746 | _T_2743; // @[lsu_bus_buffer.scala 525:93] - wire _T_4495 = _T_4494 | _T_2740; // @[lsu_bus_buffer.scala 525:93] - wire any_done_wait_state = _T_4495 | _T_2737; // @[lsu_bus_buffer.scala 525:93] - wire _T_3604 = buf_ldfwd[0] | any_done_wait_state; // @[lsu_bus_buffer.scala 468:31] + wire _T_3592 = ~bus_rsp_write_error; // @[lsu_bus_buffer.scala 465:73] + wire _T_3593 = buf_write[0] & _T_3592; // @[lsu_bus_buffer.scala 465:71] + wire _T_3594 = io_dec_tlu_force_halt | _T_3593; // @[lsu_bus_buffer.scala 465:55] + wire _T_3596 = ~buf_samedw_0; // @[lsu_bus_buffer.scala 466:30] + wire _T_3597 = buf_dual_0 & _T_3596; // @[lsu_bus_buffer.scala 466:28] + wire _T_3600 = _T_3597 & _T_3643; // @[lsu_bus_buffer.scala 466:45] + wire [2:0] _GEN_19 = 2'h1 == buf_dualtag_0 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 466:90] + wire [2:0] _GEN_20 = 2'h2 == buf_dualtag_0 ? buf_state_2 : _GEN_19; // @[lsu_bus_buffer.scala 466:90] + wire [2:0] _GEN_21 = 2'h3 == buf_dualtag_0 ? buf_state_3 : _GEN_20; // @[lsu_bus_buffer.scala 466:90] + wire _T_3601 = _GEN_21 != 3'h4; // @[lsu_bus_buffer.scala 466:90] + wire _T_3602 = _T_3600 & _T_3601; // @[lsu_bus_buffer.scala 466:61] + wire _T_4494 = _T_2746 | _T_2743; // @[lsu_bus_buffer.scala 524:93] + wire _T_4495 = _T_4494 | _T_2740; // @[lsu_bus_buffer.scala 524:93] + wire any_done_wait_state = _T_4495 | _T_2737; // @[lsu_bus_buffer.scala 524:93] + wire _T_3604 = buf_ldfwd[0] | any_done_wait_state; // @[lsu_bus_buffer.scala 467:31] wire _T_3610 = buf_dualtag_0 == 2'h0; // @[lsu_bus_buffer.scala 57:118] wire _T_3612 = buf_dualtag_0 == 2'h1; // @[lsu_bus_buffer.scala 57:118] wire _T_3614 = buf_dualtag_0 == 2'h2; // @[lsu_bus_buffer.scala 57:118] @@ -70134,17 +70029,17 @@ module lsu_bus_buffer( wire _T_3622 = _T_3618 | _T_3619; // @[Mux.scala 27:72] wire _T_3623 = _T_3622 | _T_3620; // @[Mux.scala 27:72] wire _T_3624 = _T_3623 | _T_3621; // @[Mux.scala 27:72] - wire _T_3626 = _T_3600 & _T_3624; // @[lsu_bus_buffer.scala 468:101] - wire _T_3627 = _GEN_21 == 3'h4; // @[lsu_bus_buffer.scala 468:167] - wire _T_3628 = _T_3626 & _T_3627; // @[lsu_bus_buffer.scala 468:138] - wire _T_3629 = _T_3628 & any_done_wait_state; // @[lsu_bus_buffer.scala 468:187] - wire _T_3630 = _T_3604 | _T_3629; // @[lsu_bus_buffer.scala 468:53] - wire _T_3653 = buf_state_bus_en_0 & bus_rsp_read; // @[lsu_bus_buffer.scala 475:47] - wire _T_3654 = _T_3653 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 475:62] - wire _T_3668 = ~buf_error_en_0; // @[lsu_bus_buffer.scala 479:50] - wire _T_3669 = buf_state_en_0 & _T_3668; // @[lsu_bus_buffer.scala 479:48] - wire _T_3681 = buf_ldfwd[0] | _T_3686[0]; // @[lsu_bus_buffer.scala 482:90] - wire _T_3682 = _T_3681 | any_done_wait_state; // @[lsu_bus_buffer.scala 482:118] + wire _T_3626 = _T_3600 & _T_3624; // @[lsu_bus_buffer.scala 467:101] + wire _T_3627 = _GEN_21 == 3'h4; // @[lsu_bus_buffer.scala 467:167] + wire _T_3628 = _T_3626 & _T_3627; // @[lsu_bus_buffer.scala 467:138] + wire _T_3629 = _T_3628 & any_done_wait_state; // @[lsu_bus_buffer.scala 467:187] + wire _T_3630 = _T_3604 | _T_3629; // @[lsu_bus_buffer.scala 467:53] + wire _T_3653 = buf_state_bus_en_0 & bus_rsp_read; // @[lsu_bus_buffer.scala 474:47] + wire _T_3654 = _T_3653 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 474:62] + wire _T_3668 = ~buf_error_en_0; // @[lsu_bus_buffer.scala 478:50] + wire _T_3669 = buf_state_en_0 & _T_3668; // @[lsu_bus_buffer.scala 478:48] + wire _T_3681 = buf_ldfwd[0] | _T_3686[0]; // @[lsu_bus_buffer.scala 481:90] + wire _T_3682 = _T_3681 | any_done_wait_state; // @[lsu_bus_buffer.scala 481:118] wire _GEN_29 = _T_3702 & buf_state_en_0; // @[Conditional.scala 39:67] wire _GEN_32 = _T_3694 ? 1'h0 : _T_3702; // @[Conditional.scala 39:67] wire _GEN_34 = _T_3694 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] @@ -70162,34 +70057,34 @@ module lsu_bus_buffer( wire buf_wr_en_0 = _T_3528 & buf_state_en_0; // @[Conditional.scala 40:58] wire buf_ldfwd_en_0 = _T_3528 ? 1'h0 : _GEN_68; // @[Conditional.scala 40:58] wire buf_rst_0 = _T_3528 ? 1'h0 : _GEN_74; // @[Conditional.scala 40:58] - wire _T_3765 = buf_state_en_1 & _T_3836; // @[lsu_bus_buffer.scala 459:44] - wire _T_3766 = _T_3765 & obuf_nosend; // @[lsu_bus_buffer.scala 459:60] - wire _T_3768 = _T_3766 & _T_1333; // @[lsu_bus_buffer.scala 459:74] - wire _T_3771 = _T_3761 & obuf_nosend; // @[lsu_bus_buffer.scala 461:67] - wire _T_3772 = _T_3771 & bus_rsp_read; // @[lsu_bus_buffer.scala 461:81] - wire _T_3775 = _T_3771 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 462:82] - wire _T_3850 = bus_rsp_read_error & _T_3829; // @[lsu_bus_buffer.scala 476:91] - wire _T_3852 = bus_rsp_read_error & buf_ldfwd[1]; // @[lsu_bus_buffer.scala 477:31] - wire _T_3854 = _T_3852 & _T_3831; // @[lsu_bus_buffer.scala 477:46] - wire _T_3855 = _T_3850 | _T_3854; // @[lsu_bus_buffer.scala 476:143] - wire _T_3858 = bus_rsp_write_error & _T_3827; // @[lsu_bus_buffer.scala 478:53] - wire _T_3859 = _T_3855 | _T_3858; // @[lsu_bus_buffer.scala 477:88] - wire _T_3860 = _T_3761 & _T_3859; // @[lsu_bus_buffer.scala 476:68] + wire _T_3765 = buf_state_en_1 & _T_3836; // @[lsu_bus_buffer.scala 458:44] + wire _T_3766 = _T_3765 & obuf_nosend; // @[lsu_bus_buffer.scala 458:60] + wire _T_3768 = _T_3766 & _T_1333; // @[lsu_bus_buffer.scala 458:74] + wire _T_3771 = _T_3761 & obuf_nosend; // @[lsu_bus_buffer.scala 460:67] + wire _T_3772 = _T_3771 & bus_rsp_read; // @[lsu_bus_buffer.scala 460:81] + wire _T_3775 = _T_3771 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 461:82] + wire _T_3850 = bus_rsp_read_error & _T_3829; // @[lsu_bus_buffer.scala 475:91] + wire _T_3852 = bus_rsp_read_error & buf_ldfwd[1]; // @[lsu_bus_buffer.scala 476:31] + wire _T_3854 = _T_3852 & _T_3831; // @[lsu_bus_buffer.scala 476:46] + wire _T_3855 = _T_3850 | _T_3854; // @[lsu_bus_buffer.scala 475:143] + wire _T_3858 = bus_rsp_write_error & _T_3827; // @[lsu_bus_buffer.scala 477:53] + wire _T_3859 = _T_3855 | _T_3858; // @[lsu_bus_buffer.scala 476:88] + wire _T_3860 = _T_3761 & _T_3859; // @[lsu_bus_buffer.scala 475:68] wire _GEN_122 = _T_3782 & _T_3860; // @[Conditional.scala 39:67] wire _GEN_135 = _T_3748 ? _T_3775 : _GEN_122; // @[Conditional.scala 39:67] wire _GEN_147 = _T_3744 ? 1'h0 : _GEN_135; // @[Conditional.scala 39:67] wire buf_error_en_1 = _T_3721 ? 1'h0 : _GEN_147; // @[Conditional.scala 40:58] - wire _T_3786 = buf_write[1] & _T_3592; // @[lsu_bus_buffer.scala 466:71] - wire _T_3787 = io_dec_tlu_force_halt | _T_3786; // @[lsu_bus_buffer.scala 466:55] - wire _T_3789 = ~buf_samedw_1; // @[lsu_bus_buffer.scala 467:30] - wire _T_3790 = buf_dual_1 & _T_3789; // @[lsu_bus_buffer.scala 467:28] - wire _T_3793 = _T_3790 & _T_3836; // @[lsu_bus_buffer.scala 467:45] - wire [2:0] _GEN_95 = 2'h1 == buf_dualtag_1 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 467:90] - wire [2:0] _GEN_96 = 2'h2 == buf_dualtag_1 ? buf_state_2 : _GEN_95; // @[lsu_bus_buffer.scala 467:90] - wire [2:0] _GEN_97 = 2'h3 == buf_dualtag_1 ? buf_state_3 : _GEN_96; // @[lsu_bus_buffer.scala 467:90] - wire _T_3794 = _GEN_97 != 3'h4; // @[lsu_bus_buffer.scala 467:90] - wire _T_3795 = _T_3793 & _T_3794; // @[lsu_bus_buffer.scala 467:61] - wire _T_3797 = buf_ldfwd[1] | any_done_wait_state; // @[lsu_bus_buffer.scala 468:31] + wire _T_3786 = buf_write[1] & _T_3592; // @[lsu_bus_buffer.scala 465:71] + wire _T_3787 = io_dec_tlu_force_halt | _T_3786; // @[lsu_bus_buffer.scala 465:55] + wire _T_3789 = ~buf_samedw_1; // @[lsu_bus_buffer.scala 466:30] + wire _T_3790 = buf_dual_1 & _T_3789; // @[lsu_bus_buffer.scala 466:28] + wire _T_3793 = _T_3790 & _T_3836; // @[lsu_bus_buffer.scala 466:45] + wire [2:0] _GEN_95 = 2'h1 == buf_dualtag_1 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 466:90] + wire [2:0] _GEN_96 = 2'h2 == buf_dualtag_1 ? buf_state_2 : _GEN_95; // @[lsu_bus_buffer.scala 466:90] + wire [2:0] _GEN_97 = 2'h3 == buf_dualtag_1 ? buf_state_3 : _GEN_96; // @[lsu_bus_buffer.scala 466:90] + wire _T_3794 = _GEN_97 != 3'h4; // @[lsu_bus_buffer.scala 466:90] + wire _T_3795 = _T_3793 & _T_3794; // @[lsu_bus_buffer.scala 466:61] + wire _T_3797 = buf_ldfwd[1] | any_done_wait_state; // @[lsu_bus_buffer.scala 467:31] wire _T_3803 = buf_dualtag_1 == 2'h0; // @[lsu_bus_buffer.scala 57:118] wire _T_3805 = buf_dualtag_1 == 2'h1; // @[lsu_bus_buffer.scala 57:118] wire _T_3807 = buf_dualtag_1 == 2'h2; // @[lsu_bus_buffer.scala 57:118] @@ -70201,17 +70096,17 @@ module lsu_bus_buffer( wire _T_3815 = _T_3811 | _T_3812; // @[Mux.scala 27:72] wire _T_3816 = _T_3815 | _T_3813; // @[Mux.scala 27:72] wire _T_3817 = _T_3816 | _T_3814; // @[Mux.scala 27:72] - wire _T_3819 = _T_3793 & _T_3817; // @[lsu_bus_buffer.scala 468:101] - wire _T_3820 = _GEN_97 == 3'h4; // @[lsu_bus_buffer.scala 468:167] - wire _T_3821 = _T_3819 & _T_3820; // @[lsu_bus_buffer.scala 468:138] - wire _T_3822 = _T_3821 & any_done_wait_state; // @[lsu_bus_buffer.scala 468:187] - wire _T_3823 = _T_3797 | _T_3822; // @[lsu_bus_buffer.scala 468:53] - wire _T_3846 = buf_state_bus_en_1 & bus_rsp_read; // @[lsu_bus_buffer.scala 475:47] - wire _T_3847 = _T_3846 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 475:62] - wire _T_3861 = ~buf_error_en_1; // @[lsu_bus_buffer.scala 479:50] - wire _T_3862 = buf_state_en_1 & _T_3861; // @[lsu_bus_buffer.scala 479:48] - wire _T_3874 = buf_ldfwd[1] | _T_3879[0]; // @[lsu_bus_buffer.scala 482:90] - wire _T_3875 = _T_3874 | any_done_wait_state; // @[lsu_bus_buffer.scala 482:118] + wire _T_3819 = _T_3793 & _T_3817; // @[lsu_bus_buffer.scala 467:101] + wire _T_3820 = _GEN_97 == 3'h4; // @[lsu_bus_buffer.scala 467:167] + wire _T_3821 = _T_3819 & _T_3820; // @[lsu_bus_buffer.scala 467:138] + wire _T_3822 = _T_3821 & any_done_wait_state; // @[lsu_bus_buffer.scala 467:187] + wire _T_3823 = _T_3797 | _T_3822; // @[lsu_bus_buffer.scala 467:53] + wire _T_3846 = buf_state_bus_en_1 & bus_rsp_read; // @[lsu_bus_buffer.scala 474:47] + wire _T_3847 = _T_3846 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 474:62] + wire _T_3861 = ~buf_error_en_1; // @[lsu_bus_buffer.scala 478:50] + wire _T_3862 = buf_state_en_1 & _T_3861; // @[lsu_bus_buffer.scala 478:48] + wire _T_3874 = buf_ldfwd[1] | _T_3879[0]; // @[lsu_bus_buffer.scala 481:90] + wire _T_3875 = _T_3874 | any_done_wait_state; // @[lsu_bus_buffer.scala 481:118] wire _GEN_105 = _T_3895 & buf_state_en_1; // @[Conditional.scala 39:67] wire _GEN_108 = _T_3887 ? 1'h0 : _T_3895; // @[Conditional.scala 39:67] wire _GEN_110 = _T_3887 ? 1'h0 : _GEN_105; // @[Conditional.scala 39:67] @@ -70229,34 +70124,34 @@ module lsu_bus_buffer( wire buf_wr_en_1 = _T_3721 & buf_state_en_1; // @[Conditional.scala 40:58] wire buf_ldfwd_en_1 = _T_3721 ? 1'h0 : _GEN_144; // @[Conditional.scala 40:58] wire buf_rst_1 = _T_3721 ? 1'h0 : _GEN_150; // @[Conditional.scala 40:58] - wire _T_3958 = buf_state_en_2 & _T_4029; // @[lsu_bus_buffer.scala 459:44] - wire _T_3959 = _T_3958 & obuf_nosend; // @[lsu_bus_buffer.scala 459:60] - wire _T_3961 = _T_3959 & _T_1333; // @[lsu_bus_buffer.scala 459:74] - wire _T_3964 = _T_3954 & obuf_nosend; // @[lsu_bus_buffer.scala 461:67] - wire _T_3965 = _T_3964 & bus_rsp_read; // @[lsu_bus_buffer.scala 461:81] - wire _T_3968 = _T_3964 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 462:82] - wire _T_4043 = bus_rsp_read_error & _T_4022; // @[lsu_bus_buffer.scala 476:91] - wire _T_4045 = bus_rsp_read_error & buf_ldfwd[2]; // @[lsu_bus_buffer.scala 477:31] - wire _T_4047 = _T_4045 & _T_4024; // @[lsu_bus_buffer.scala 477:46] - wire _T_4048 = _T_4043 | _T_4047; // @[lsu_bus_buffer.scala 476:143] - wire _T_4051 = bus_rsp_write_error & _T_4020; // @[lsu_bus_buffer.scala 478:53] - wire _T_4052 = _T_4048 | _T_4051; // @[lsu_bus_buffer.scala 477:88] - wire _T_4053 = _T_3954 & _T_4052; // @[lsu_bus_buffer.scala 476:68] + wire _T_3958 = buf_state_en_2 & _T_4029; // @[lsu_bus_buffer.scala 458:44] + wire _T_3959 = _T_3958 & obuf_nosend; // @[lsu_bus_buffer.scala 458:60] + wire _T_3961 = _T_3959 & _T_1333; // @[lsu_bus_buffer.scala 458:74] + wire _T_3964 = _T_3954 & obuf_nosend; // @[lsu_bus_buffer.scala 460:67] + wire _T_3965 = _T_3964 & bus_rsp_read; // @[lsu_bus_buffer.scala 460:81] + wire _T_3968 = _T_3964 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 461:82] + wire _T_4043 = bus_rsp_read_error & _T_4022; // @[lsu_bus_buffer.scala 475:91] + wire _T_4045 = bus_rsp_read_error & buf_ldfwd[2]; // @[lsu_bus_buffer.scala 476:31] + wire _T_4047 = _T_4045 & _T_4024; // @[lsu_bus_buffer.scala 476:46] + wire _T_4048 = _T_4043 | _T_4047; // @[lsu_bus_buffer.scala 475:143] + wire _T_4051 = bus_rsp_write_error & _T_4020; // @[lsu_bus_buffer.scala 477:53] + wire _T_4052 = _T_4048 | _T_4051; // @[lsu_bus_buffer.scala 476:88] + wire _T_4053 = _T_3954 & _T_4052; // @[lsu_bus_buffer.scala 475:68] wire _GEN_198 = _T_3975 & _T_4053; // @[Conditional.scala 39:67] wire _GEN_211 = _T_3941 ? _T_3968 : _GEN_198; // @[Conditional.scala 39:67] wire _GEN_223 = _T_3937 ? 1'h0 : _GEN_211; // @[Conditional.scala 39:67] wire buf_error_en_2 = _T_3914 ? 1'h0 : _GEN_223; // @[Conditional.scala 40:58] - wire _T_3979 = buf_write[2] & _T_3592; // @[lsu_bus_buffer.scala 466:71] - wire _T_3980 = io_dec_tlu_force_halt | _T_3979; // @[lsu_bus_buffer.scala 466:55] - wire _T_3982 = ~buf_samedw_2; // @[lsu_bus_buffer.scala 467:30] - wire _T_3983 = buf_dual_2 & _T_3982; // @[lsu_bus_buffer.scala 467:28] - wire _T_3986 = _T_3983 & _T_4029; // @[lsu_bus_buffer.scala 467:45] - wire [2:0] _GEN_171 = 2'h1 == buf_dualtag_2 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 467:90] - wire [2:0] _GEN_172 = 2'h2 == buf_dualtag_2 ? buf_state_2 : _GEN_171; // @[lsu_bus_buffer.scala 467:90] - wire [2:0] _GEN_173 = 2'h3 == buf_dualtag_2 ? buf_state_3 : _GEN_172; // @[lsu_bus_buffer.scala 467:90] - wire _T_3987 = _GEN_173 != 3'h4; // @[lsu_bus_buffer.scala 467:90] - wire _T_3988 = _T_3986 & _T_3987; // @[lsu_bus_buffer.scala 467:61] - wire _T_3990 = buf_ldfwd[2] | any_done_wait_state; // @[lsu_bus_buffer.scala 468:31] + wire _T_3979 = buf_write[2] & _T_3592; // @[lsu_bus_buffer.scala 465:71] + wire _T_3980 = io_dec_tlu_force_halt | _T_3979; // @[lsu_bus_buffer.scala 465:55] + wire _T_3982 = ~buf_samedw_2; // @[lsu_bus_buffer.scala 466:30] + wire _T_3983 = buf_dual_2 & _T_3982; // @[lsu_bus_buffer.scala 466:28] + wire _T_3986 = _T_3983 & _T_4029; // @[lsu_bus_buffer.scala 466:45] + wire [2:0] _GEN_171 = 2'h1 == buf_dualtag_2 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 466:90] + wire [2:0] _GEN_172 = 2'h2 == buf_dualtag_2 ? buf_state_2 : _GEN_171; // @[lsu_bus_buffer.scala 466:90] + wire [2:0] _GEN_173 = 2'h3 == buf_dualtag_2 ? buf_state_3 : _GEN_172; // @[lsu_bus_buffer.scala 466:90] + wire _T_3987 = _GEN_173 != 3'h4; // @[lsu_bus_buffer.scala 466:90] + wire _T_3988 = _T_3986 & _T_3987; // @[lsu_bus_buffer.scala 466:61] + wire _T_3990 = buf_ldfwd[2] | any_done_wait_state; // @[lsu_bus_buffer.scala 467:31] wire _T_3996 = buf_dualtag_2 == 2'h0; // @[lsu_bus_buffer.scala 57:118] wire _T_3998 = buf_dualtag_2 == 2'h1; // @[lsu_bus_buffer.scala 57:118] wire _T_4000 = buf_dualtag_2 == 2'h2; // @[lsu_bus_buffer.scala 57:118] @@ -70268,17 +70163,17 @@ module lsu_bus_buffer( wire _T_4008 = _T_4004 | _T_4005; // @[Mux.scala 27:72] wire _T_4009 = _T_4008 | _T_4006; // @[Mux.scala 27:72] wire _T_4010 = _T_4009 | _T_4007; // @[Mux.scala 27:72] - wire _T_4012 = _T_3986 & _T_4010; // @[lsu_bus_buffer.scala 468:101] - wire _T_4013 = _GEN_173 == 3'h4; // @[lsu_bus_buffer.scala 468:167] - wire _T_4014 = _T_4012 & _T_4013; // @[lsu_bus_buffer.scala 468:138] - wire _T_4015 = _T_4014 & any_done_wait_state; // @[lsu_bus_buffer.scala 468:187] - wire _T_4016 = _T_3990 | _T_4015; // @[lsu_bus_buffer.scala 468:53] - wire _T_4039 = buf_state_bus_en_2 & bus_rsp_read; // @[lsu_bus_buffer.scala 475:47] - wire _T_4040 = _T_4039 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 475:62] - wire _T_4054 = ~buf_error_en_2; // @[lsu_bus_buffer.scala 479:50] - wire _T_4055 = buf_state_en_2 & _T_4054; // @[lsu_bus_buffer.scala 479:48] - wire _T_4067 = buf_ldfwd[2] | _T_4072[0]; // @[lsu_bus_buffer.scala 482:90] - wire _T_4068 = _T_4067 | any_done_wait_state; // @[lsu_bus_buffer.scala 482:118] + wire _T_4012 = _T_3986 & _T_4010; // @[lsu_bus_buffer.scala 467:101] + wire _T_4013 = _GEN_173 == 3'h4; // @[lsu_bus_buffer.scala 467:167] + wire _T_4014 = _T_4012 & _T_4013; // @[lsu_bus_buffer.scala 467:138] + wire _T_4015 = _T_4014 & any_done_wait_state; // @[lsu_bus_buffer.scala 467:187] + wire _T_4016 = _T_3990 | _T_4015; // @[lsu_bus_buffer.scala 467:53] + wire _T_4039 = buf_state_bus_en_2 & bus_rsp_read; // @[lsu_bus_buffer.scala 474:47] + wire _T_4040 = _T_4039 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 474:62] + wire _T_4054 = ~buf_error_en_2; // @[lsu_bus_buffer.scala 478:50] + wire _T_4055 = buf_state_en_2 & _T_4054; // @[lsu_bus_buffer.scala 478:48] + wire _T_4067 = buf_ldfwd[2] | _T_4072[0]; // @[lsu_bus_buffer.scala 481:90] + wire _T_4068 = _T_4067 | any_done_wait_state; // @[lsu_bus_buffer.scala 481:118] wire _GEN_181 = _T_4088 & buf_state_en_2; // @[Conditional.scala 39:67] wire _GEN_184 = _T_4080 ? 1'h0 : _T_4088; // @[Conditional.scala 39:67] wire _GEN_186 = _T_4080 ? 1'h0 : _GEN_181; // @[Conditional.scala 39:67] @@ -70296,34 +70191,34 @@ module lsu_bus_buffer( wire buf_wr_en_2 = _T_3914 & buf_state_en_2; // @[Conditional.scala 40:58] wire buf_ldfwd_en_2 = _T_3914 ? 1'h0 : _GEN_220; // @[Conditional.scala 40:58] wire buf_rst_2 = _T_3914 ? 1'h0 : _GEN_226; // @[Conditional.scala 40:58] - wire _T_4151 = buf_state_en_3 & _T_4222; // @[lsu_bus_buffer.scala 459:44] - wire _T_4152 = _T_4151 & obuf_nosend; // @[lsu_bus_buffer.scala 459:60] - wire _T_4154 = _T_4152 & _T_1333; // @[lsu_bus_buffer.scala 459:74] - wire _T_4157 = _T_4147 & obuf_nosend; // @[lsu_bus_buffer.scala 461:67] - wire _T_4158 = _T_4157 & bus_rsp_read; // @[lsu_bus_buffer.scala 461:81] - wire _T_4161 = _T_4157 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 462:82] - wire _T_4236 = bus_rsp_read_error & _T_4215; // @[lsu_bus_buffer.scala 476:91] - wire _T_4238 = bus_rsp_read_error & buf_ldfwd[3]; // @[lsu_bus_buffer.scala 477:31] - wire _T_4240 = _T_4238 & _T_4217; // @[lsu_bus_buffer.scala 477:46] - wire _T_4241 = _T_4236 | _T_4240; // @[lsu_bus_buffer.scala 476:143] - wire _T_4244 = bus_rsp_write_error & _T_4213; // @[lsu_bus_buffer.scala 478:53] - wire _T_4245 = _T_4241 | _T_4244; // @[lsu_bus_buffer.scala 477:88] - wire _T_4246 = _T_4147 & _T_4245; // @[lsu_bus_buffer.scala 476:68] + wire _T_4151 = buf_state_en_3 & _T_4222; // @[lsu_bus_buffer.scala 458:44] + wire _T_4152 = _T_4151 & obuf_nosend; // @[lsu_bus_buffer.scala 458:60] + wire _T_4154 = _T_4152 & _T_1333; // @[lsu_bus_buffer.scala 458:74] + wire _T_4157 = _T_4147 & obuf_nosend; // @[lsu_bus_buffer.scala 460:67] + wire _T_4158 = _T_4157 & bus_rsp_read; // @[lsu_bus_buffer.scala 460:81] + wire _T_4161 = _T_4157 & bus_rsp_read_error; // @[lsu_bus_buffer.scala 461:82] + wire _T_4236 = bus_rsp_read_error & _T_4215; // @[lsu_bus_buffer.scala 475:91] + wire _T_4238 = bus_rsp_read_error & buf_ldfwd[3]; // @[lsu_bus_buffer.scala 476:31] + wire _T_4240 = _T_4238 & _T_4217; // @[lsu_bus_buffer.scala 476:46] + wire _T_4241 = _T_4236 | _T_4240; // @[lsu_bus_buffer.scala 475:143] + wire _T_4244 = bus_rsp_write_error & _T_4213; // @[lsu_bus_buffer.scala 477:53] + wire _T_4245 = _T_4241 | _T_4244; // @[lsu_bus_buffer.scala 476:88] + wire _T_4246 = _T_4147 & _T_4245; // @[lsu_bus_buffer.scala 475:68] wire _GEN_274 = _T_4168 & _T_4246; // @[Conditional.scala 39:67] wire _GEN_287 = _T_4134 ? _T_4161 : _GEN_274; // @[Conditional.scala 39:67] wire _GEN_299 = _T_4130 ? 1'h0 : _GEN_287; // @[Conditional.scala 39:67] wire buf_error_en_3 = _T_4107 ? 1'h0 : _GEN_299; // @[Conditional.scala 40:58] - wire _T_4172 = buf_write[3] & _T_3592; // @[lsu_bus_buffer.scala 466:71] - wire _T_4173 = io_dec_tlu_force_halt | _T_4172; // @[lsu_bus_buffer.scala 466:55] - wire _T_4175 = ~buf_samedw_3; // @[lsu_bus_buffer.scala 467:30] - wire _T_4176 = buf_dual_3 & _T_4175; // @[lsu_bus_buffer.scala 467:28] - wire _T_4179 = _T_4176 & _T_4222; // @[lsu_bus_buffer.scala 467:45] - wire [2:0] _GEN_247 = 2'h1 == buf_dualtag_3 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 467:90] - wire [2:0] _GEN_248 = 2'h2 == buf_dualtag_3 ? buf_state_2 : _GEN_247; // @[lsu_bus_buffer.scala 467:90] - wire [2:0] _GEN_249 = 2'h3 == buf_dualtag_3 ? buf_state_3 : _GEN_248; // @[lsu_bus_buffer.scala 467:90] - wire _T_4180 = _GEN_249 != 3'h4; // @[lsu_bus_buffer.scala 467:90] - wire _T_4181 = _T_4179 & _T_4180; // @[lsu_bus_buffer.scala 467:61] - wire _T_4183 = buf_ldfwd[3] | any_done_wait_state; // @[lsu_bus_buffer.scala 468:31] + wire _T_4172 = buf_write[3] & _T_3592; // @[lsu_bus_buffer.scala 465:71] + wire _T_4173 = io_dec_tlu_force_halt | _T_4172; // @[lsu_bus_buffer.scala 465:55] + wire _T_4175 = ~buf_samedw_3; // @[lsu_bus_buffer.scala 466:30] + wire _T_4176 = buf_dual_3 & _T_4175; // @[lsu_bus_buffer.scala 466:28] + wire _T_4179 = _T_4176 & _T_4222; // @[lsu_bus_buffer.scala 466:45] + wire [2:0] _GEN_247 = 2'h1 == buf_dualtag_3 ? buf_state_1 : buf_state_0; // @[lsu_bus_buffer.scala 466:90] + wire [2:0] _GEN_248 = 2'h2 == buf_dualtag_3 ? buf_state_2 : _GEN_247; // @[lsu_bus_buffer.scala 466:90] + wire [2:0] _GEN_249 = 2'h3 == buf_dualtag_3 ? buf_state_3 : _GEN_248; // @[lsu_bus_buffer.scala 466:90] + wire _T_4180 = _GEN_249 != 3'h4; // @[lsu_bus_buffer.scala 466:90] + wire _T_4181 = _T_4179 & _T_4180; // @[lsu_bus_buffer.scala 466:61] + wire _T_4183 = buf_ldfwd[3] | any_done_wait_state; // @[lsu_bus_buffer.scala 467:31] wire _T_4189 = buf_dualtag_3 == 2'h0; // @[lsu_bus_buffer.scala 57:118] wire _T_4191 = buf_dualtag_3 == 2'h1; // @[lsu_bus_buffer.scala 57:118] wire _T_4193 = buf_dualtag_3 == 2'h2; // @[lsu_bus_buffer.scala 57:118] @@ -70335,17 +70230,17 @@ module lsu_bus_buffer( wire _T_4201 = _T_4197 | _T_4198; // @[Mux.scala 27:72] wire _T_4202 = _T_4201 | _T_4199; // @[Mux.scala 27:72] wire _T_4203 = _T_4202 | _T_4200; // @[Mux.scala 27:72] - wire _T_4205 = _T_4179 & _T_4203; // @[lsu_bus_buffer.scala 468:101] - wire _T_4206 = _GEN_249 == 3'h4; // @[lsu_bus_buffer.scala 468:167] - wire _T_4207 = _T_4205 & _T_4206; // @[lsu_bus_buffer.scala 468:138] - wire _T_4208 = _T_4207 & any_done_wait_state; // @[lsu_bus_buffer.scala 468:187] - wire _T_4209 = _T_4183 | _T_4208; // @[lsu_bus_buffer.scala 468:53] - wire _T_4232 = buf_state_bus_en_3 & bus_rsp_read; // @[lsu_bus_buffer.scala 475:47] - wire _T_4233 = _T_4232 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 475:62] - wire _T_4247 = ~buf_error_en_3; // @[lsu_bus_buffer.scala 479:50] - wire _T_4248 = buf_state_en_3 & _T_4247; // @[lsu_bus_buffer.scala 479:48] - wire _T_4260 = buf_ldfwd[3] | _T_4265[0]; // @[lsu_bus_buffer.scala 482:90] - wire _T_4261 = _T_4260 | any_done_wait_state; // @[lsu_bus_buffer.scala 482:118] + wire _T_4205 = _T_4179 & _T_4203; // @[lsu_bus_buffer.scala 467:101] + wire _T_4206 = _GEN_249 == 3'h4; // @[lsu_bus_buffer.scala 467:167] + wire _T_4207 = _T_4205 & _T_4206; // @[lsu_bus_buffer.scala 467:138] + wire _T_4208 = _T_4207 & any_done_wait_state; // @[lsu_bus_buffer.scala 467:187] + wire _T_4209 = _T_4183 | _T_4208; // @[lsu_bus_buffer.scala 467:53] + wire _T_4232 = buf_state_bus_en_3 & bus_rsp_read; // @[lsu_bus_buffer.scala 474:47] + wire _T_4233 = _T_4232 & io_lsu_bus_clk_en; // @[lsu_bus_buffer.scala 474:62] + wire _T_4247 = ~buf_error_en_3; // @[lsu_bus_buffer.scala 478:50] + wire _T_4248 = buf_state_en_3 & _T_4247; // @[lsu_bus_buffer.scala 478:48] + wire _T_4260 = buf_ldfwd[3] | _T_4265[0]; // @[lsu_bus_buffer.scala 481:90] + wire _T_4261 = _T_4260 | any_done_wait_state; // @[lsu_bus_buffer.scala 481:118] wire _GEN_257 = _T_4281 & buf_state_en_3; // @[Conditional.scala 39:67] wire _GEN_260 = _T_4273 ? 1'h0 : _T_4281; // @[Conditional.scala 39:67] wire _GEN_262 = _T_4273 ? 1'h0 : _GEN_257; // @[Conditional.scala 39:67] @@ -70368,51 +70263,51 @@ module lsu_bus_buffer( reg _T_4342; // @[Reg.scala 27:20] reg _T_4345; // @[Reg.scala 27:20] wire [3:0] buf_unsign = {_T_4345,_T_4342,_T_4339,_T_4336}; // @[Cat.scala 29:58] - reg _T_4411; // @[lsu_bus_buffer.scala 518:80] - reg _T_4406; // @[lsu_bus_buffer.scala 518:80] - reg _T_4401; // @[lsu_bus_buffer.scala 518:80] - reg _T_4396; // @[lsu_bus_buffer.scala 518:80] + reg _T_4411; // @[lsu_bus_buffer.scala 517:80] + reg _T_4406; // @[lsu_bus_buffer.scala 517:80] + reg _T_4401; // @[lsu_bus_buffer.scala 517:80] + reg _T_4396; // @[lsu_bus_buffer.scala 517:80] wire [3:0] buf_error = {_T_4411,_T_4406,_T_4401,_T_4396}; // @[Cat.scala 29:58] - wire _T_4393 = buf_error_en_0 | buf_error[0]; // @[lsu_bus_buffer.scala 518:84] - wire _T_4394 = ~buf_rst_0; // @[lsu_bus_buffer.scala 518:126] - wire _T_4398 = buf_error_en_1 | buf_error[1]; // @[lsu_bus_buffer.scala 518:84] - wire _T_4399 = ~buf_rst_1; // @[lsu_bus_buffer.scala 518:126] - wire _T_4403 = buf_error_en_2 | buf_error[2]; // @[lsu_bus_buffer.scala 518:84] - wire _T_4404 = ~buf_rst_2; // @[lsu_bus_buffer.scala 518:126] - wire _T_4408 = buf_error_en_3 | buf_error[3]; // @[lsu_bus_buffer.scala 518:84] - wire _T_4409 = ~buf_rst_3; // @[lsu_bus_buffer.scala 518:126] + wire _T_4393 = buf_error_en_0 | buf_error[0]; // @[lsu_bus_buffer.scala 517:84] + wire _T_4394 = ~buf_rst_0; // @[lsu_bus_buffer.scala 517:126] + wire _T_4398 = buf_error_en_1 | buf_error[1]; // @[lsu_bus_buffer.scala 517:84] + wire _T_4399 = ~buf_rst_1; // @[lsu_bus_buffer.scala 517:126] + wire _T_4403 = buf_error_en_2 | buf_error[2]; // @[lsu_bus_buffer.scala 517:84] + wire _T_4404 = ~buf_rst_2; // @[lsu_bus_buffer.scala 517:126] + wire _T_4408 = buf_error_en_3 | buf_error[3]; // @[lsu_bus_buffer.scala 517:84] + wire _T_4409 = ~buf_rst_3; // @[lsu_bus_buffer.scala 517:126] wire [1:0] _T_4415 = {io_lsu_busreq_m,1'h0}; // @[Cat.scala 29:58] - wire [1:0] _T_4416 = io_ldst_dual_m ? _T_4415 : {{1'd0}, io_lsu_busreq_m}; // @[lsu_bus_buffer.scala 521:28] + wire [1:0] _T_4416 = io_ldst_dual_m ? _T_4415 : {{1'd0}, io_lsu_busreq_m}; // @[lsu_bus_buffer.scala 520:28] wire [1:0] _T_4417 = {io_lsu_busreq_r,1'h0}; // @[Cat.scala 29:58] - wire [1:0] _T_4418 = io_ldst_dual_r ? _T_4417 : {{1'd0}, io_lsu_busreq_r}; // @[lsu_bus_buffer.scala 521:94] - wire [2:0] _T_4419 = _T_4416 + _T_4418; // @[lsu_bus_buffer.scala 521:88] - wire [2:0] _GEN_388 = {{2'd0}, ibuf_valid}; // @[lsu_bus_buffer.scala 521:154] - wire [3:0] _T_4420 = _T_4419 + _GEN_388; // @[lsu_bus_buffer.scala 521:154] - wire [1:0] _T_4425 = _T_5 + _T_12; // @[lsu_bus_buffer.scala 521:217] - wire [1:0] _GEN_389 = {{1'd0}, _T_19}; // @[lsu_bus_buffer.scala 521:217] - wire [2:0] _T_4426 = _T_4425 + _GEN_389; // @[lsu_bus_buffer.scala 521:217] - wire [2:0] _GEN_390 = {{2'd0}, _T_26}; // @[lsu_bus_buffer.scala 521:217] - wire [3:0] _T_4427 = _T_4426 + _GEN_390; // @[lsu_bus_buffer.scala 521:217] - wire [3:0] buf_numvld_any = _T_4420 + _T_4427; // @[lsu_bus_buffer.scala 521:169] - wire _T_4498 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[lsu_bus_buffer.scala 527:52] - wire _T_4499 = buf_numvld_any >= 4'h3; // @[lsu_bus_buffer.scala 527:92] - wire _T_4500 = buf_numvld_any == 4'h4; // @[lsu_bus_buffer.scala 527:121] - wire _T_4502 = |buf_state_0; // @[lsu_bus_buffer.scala 528:52] - wire _T_4503 = |buf_state_1; // @[lsu_bus_buffer.scala 528:52] - wire _T_4504 = |buf_state_2; // @[lsu_bus_buffer.scala 528:52] - wire _T_4505 = |buf_state_3; // @[lsu_bus_buffer.scala 528:52] - wire _T_4506 = _T_4502 | _T_4503; // @[lsu_bus_buffer.scala 528:65] - wire _T_4507 = _T_4506 | _T_4504; // @[lsu_bus_buffer.scala 528:65] - wire _T_4508 = _T_4507 | _T_4505; // @[lsu_bus_buffer.scala 528:65] - wire _T_4509 = ~_T_4508; // @[lsu_bus_buffer.scala 528:34] - wire _T_4511 = _T_4509 & _T_852; // @[lsu_bus_buffer.scala 528:70] - wire _T_4514 = io_lsu_busreq_m & io_lsu_pkt_m_valid; // @[lsu_bus_buffer.scala 530:64] - wire _T_4515 = _T_4514 & io_lsu_pkt_m_bits_load; // @[lsu_bus_buffer.scala 530:85] - wire _T_4516 = ~io_flush_m_up; // @[lsu_bus_buffer.scala 530:112] - wire _T_4517 = _T_4515 & _T_4516; // @[lsu_bus_buffer.scala 530:110] - wire _T_4518 = ~io_ld_full_hit_m; // @[lsu_bus_buffer.scala 530:129] - wire _T_4520 = ~io_lsu_commit_r; // @[lsu_bus_buffer.scala 533:74] - reg lsu_nonblock_load_valid_r; // @[lsu_bus_buffer.scala 618:66] + wire [1:0] _T_4418 = io_ldst_dual_r ? _T_4417 : {{1'd0}, io_lsu_busreq_r}; // @[lsu_bus_buffer.scala 520:94] + wire [2:0] _T_4419 = _T_4416 + _T_4418; // @[lsu_bus_buffer.scala 520:88] + wire [2:0] _GEN_388 = {{2'd0}, ibuf_valid}; // @[lsu_bus_buffer.scala 520:154] + wire [3:0] _T_4420 = _T_4419 + _GEN_388; // @[lsu_bus_buffer.scala 520:154] + wire [1:0] _T_4425 = _T_5 + _T_12; // @[lsu_bus_buffer.scala 520:217] + wire [1:0] _GEN_389 = {{1'd0}, _T_19}; // @[lsu_bus_buffer.scala 520:217] + wire [2:0] _T_4426 = _T_4425 + _GEN_389; // @[lsu_bus_buffer.scala 520:217] + wire [2:0] _GEN_390 = {{2'd0}, _T_26}; // @[lsu_bus_buffer.scala 520:217] + wire [3:0] _T_4427 = _T_4426 + _GEN_390; // @[lsu_bus_buffer.scala 520:217] + wire [3:0] buf_numvld_any = _T_4420 + _T_4427; // @[lsu_bus_buffer.scala 520:169] + wire _T_4498 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[lsu_bus_buffer.scala 526:52] + wire _T_4499 = buf_numvld_any >= 4'h3; // @[lsu_bus_buffer.scala 526:92] + wire _T_4500 = buf_numvld_any == 4'h4; // @[lsu_bus_buffer.scala 526:121] + wire _T_4502 = |buf_state_0; // @[lsu_bus_buffer.scala 527:52] + wire _T_4503 = |buf_state_1; // @[lsu_bus_buffer.scala 527:52] + wire _T_4504 = |buf_state_2; // @[lsu_bus_buffer.scala 527:52] + wire _T_4505 = |buf_state_3; // @[lsu_bus_buffer.scala 527:52] + wire _T_4506 = _T_4502 | _T_4503; // @[lsu_bus_buffer.scala 527:65] + wire _T_4507 = _T_4506 | _T_4504; // @[lsu_bus_buffer.scala 527:65] + wire _T_4508 = _T_4507 | _T_4505; // @[lsu_bus_buffer.scala 527:65] + wire _T_4509 = ~_T_4508; // @[lsu_bus_buffer.scala 527:34] + wire _T_4511 = _T_4509 & _T_852; // @[lsu_bus_buffer.scala 527:70] + wire _T_4514 = io_lsu_busreq_m & io_lsu_pkt_m_valid; // @[lsu_bus_buffer.scala 529:64] + wire _T_4515 = _T_4514 & io_lsu_pkt_m_bits_load; // @[lsu_bus_buffer.scala 529:85] + wire _T_4516 = ~io_flush_m_up; // @[lsu_bus_buffer.scala 529:112] + wire _T_4517 = _T_4515 & _T_4516; // @[lsu_bus_buffer.scala 529:110] + wire _T_4518 = ~io_ld_full_hit_m; // @[lsu_bus_buffer.scala 529:129] + wire _T_4520 = ~io_lsu_commit_r; // @[lsu_bus_buffer.scala 532:74] + reg lsu_nonblock_load_valid_r; // @[lsu_bus_buffer.scala 617:66] wire _T_4538 = _T_2799 & _T_3643; // @[Mux.scala 27:72] wire _T_4539 = _T_2821 & _T_3836; // @[Mux.scala 27:72] wire _T_4540 = _T_2843 & _T_4029; // @[Mux.scala 27:72] @@ -70420,32 +70315,32 @@ module lsu_bus_buffer( wire _T_4542 = _T_4538 | _T_4539; // @[Mux.scala 27:72] wire _T_4543 = _T_4542 | _T_4540; // @[Mux.scala 27:72] wire lsu_nonblock_load_data_ready = _T_4543 | _T_4541; // @[Mux.scala 27:72] - wire _T_4549 = buf_error[0] & _T_3643; // @[lsu_bus_buffer.scala 536:121] - wire _T_4554 = buf_error[1] & _T_3836; // @[lsu_bus_buffer.scala 536:121] - wire _T_4559 = buf_error[2] & _T_4029; // @[lsu_bus_buffer.scala 536:121] - wire _T_4564 = buf_error[3] & _T_4222; // @[lsu_bus_buffer.scala 536:121] + wire _T_4549 = buf_error[0] & _T_3643; // @[lsu_bus_buffer.scala 535:121] + wire _T_4554 = buf_error[1] & _T_3836; // @[lsu_bus_buffer.scala 535:121] + wire _T_4559 = buf_error[2] & _T_4029; // @[lsu_bus_buffer.scala 535:121] + wire _T_4564 = buf_error[3] & _T_4222; // @[lsu_bus_buffer.scala 535:121] wire _T_4565 = _T_2799 & _T_4549; // @[Mux.scala 27:72] wire _T_4566 = _T_2821 & _T_4554; // @[Mux.scala 27:72] wire _T_4567 = _T_2843 & _T_4559; // @[Mux.scala 27:72] wire _T_4568 = _T_2865 & _T_4564; // @[Mux.scala 27:72] wire _T_4569 = _T_4565 | _T_4566; // @[Mux.scala 27:72] wire _T_4570 = _T_4569 | _T_4567; // @[Mux.scala 27:72] - wire _T_4577 = ~buf_dual_0; // @[lsu_bus_buffer.scala 537:122] - wire _T_4578 = ~buf_dualhi_0; // @[lsu_bus_buffer.scala 537:137] - wire _T_4579 = _T_4577 | _T_4578; // @[lsu_bus_buffer.scala 537:135] - wire _T_4580 = _T_4538 & _T_4579; // @[lsu_bus_buffer.scala 537:119] - wire _T_4585 = ~buf_dual_1; // @[lsu_bus_buffer.scala 537:122] - wire _T_4586 = ~buf_dualhi_1; // @[lsu_bus_buffer.scala 537:137] - wire _T_4587 = _T_4585 | _T_4586; // @[lsu_bus_buffer.scala 537:135] - wire _T_4588 = _T_4539 & _T_4587; // @[lsu_bus_buffer.scala 537:119] - wire _T_4593 = ~buf_dual_2; // @[lsu_bus_buffer.scala 537:122] - wire _T_4594 = ~buf_dualhi_2; // @[lsu_bus_buffer.scala 537:137] - wire _T_4595 = _T_4593 | _T_4594; // @[lsu_bus_buffer.scala 537:135] - wire _T_4596 = _T_4540 & _T_4595; // @[lsu_bus_buffer.scala 537:119] - wire _T_4601 = ~buf_dual_3; // @[lsu_bus_buffer.scala 537:122] - wire _T_4602 = ~buf_dualhi_3; // @[lsu_bus_buffer.scala 537:137] - wire _T_4603 = _T_4601 | _T_4602; // @[lsu_bus_buffer.scala 537:135] - wire _T_4604 = _T_4541 & _T_4603; // @[lsu_bus_buffer.scala 537:119] + wire _T_4577 = ~buf_dual_0; // @[lsu_bus_buffer.scala 536:122] + wire _T_4578 = ~buf_dualhi_0; // @[lsu_bus_buffer.scala 536:137] + wire _T_4579 = _T_4577 | _T_4578; // @[lsu_bus_buffer.scala 536:135] + wire _T_4580 = _T_4538 & _T_4579; // @[lsu_bus_buffer.scala 536:119] + wire _T_4585 = ~buf_dual_1; // @[lsu_bus_buffer.scala 536:122] + wire _T_4586 = ~buf_dualhi_1; // @[lsu_bus_buffer.scala 536:137] + wire _T_4587 = _T_4585 | _T_4586; // @[lsu_bus_buffer.scala 536:135] + wire _T_4588 = _T_4539 & _T_4587; // @[lsu_bus_buffer.scala 536:119] + wire _T_4593 = ~buf_dual_2; // @[lsu_bus_buffer.scala 536:122] + wire _T_4594 = ~buf_dualhi_2; // @[lsu_bus_buffer.scala 536:137] + wire _T_4595 = _T_4593 | _T_4594; // @[lsu_bus_buffer.scala 536:135] + wire _T_4596 = _T_4540 & _T_4595; // @[lsu_bus_buffer.scala 536:119] + wire _T_4601 = ~buf_dual_3; // @[lsu_bus_buffer.scala 536:122] + wire _T_4602 = ~buf_dualhi_3; // @[lsu_bus_buffer.scala 536:137] + wire _T_4603 = _T_4601 | _T_4602; // @[lsu_bus_buffer.scala 536:135] + wire _T_4604 = _T_4541 & _T_4603; // @[lsu_bus_buffer.scala 536:119] wire [1:0] _T_4607 = _T_4596 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_4608 = _T_4604 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _GEN_391 = {{1'd0}, _T_4588}; // @[Mux.scala 27:72] @@ -70457,10 +70352,10 @@ module lsu_bus_buffer( wire [31:0] _T_4649 = _T_4645 | _T_4646; // @[Mux.scala 27:72] wire [31:0] _T_4650 = _T_4649 | _T_4647; // @[Mux.scala 27:72] wire [31:0] lsu_nonblock_load_data_lo = _T_4650 | _T_4648; // @[Mux.scala 27:72] - wire _T_4657 = _T_4538 & _T_3641; // @[lsu_bus_buffer.scala 539:105] - wire _T_4663 = _T_4539 & _T_3834; // @[lsu_bus_buffer.scala 539:105] - wire _T_4669 = _T_4540 & _T_4027; // @[lsu_bus_buffer.scala 539:105] - wire _T_4675 = _T_4541 & _T_4220; // @[lsu_bus_buffer.scala 539:105] + wire _T_4657 = _T_4538 & _T_3641; // @[lsu_bus_buffer.scala 538:105] + wire _T_4663 = _T_4539 & _T_3834; // @[lsu_bus_buffer.scala 538:105] + wire _T_4669 = _T_4540 & _T_4027; // @[lsu_bus_buffer.scala 538:105] + wire _T_4675 = _T_4541 & _T_4220; // @[lsu_bus_buffer.scala 538:105] wire [31:0] _T_4676 = _T_4657 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_4677 = _T_4663 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_4678 = _T_4669 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] @@ -70479,7 +70374,7 @@ module lsu_bus_buffer( wire [31:0] _T_4691 = _T_4687 | _T_4688; // @[Mux.scala 27:72] wire [31:0] _T_4692 = _T_4691 | _T_4689; // @[Mux.scala 27:72] wire [31:0] _T_4693 = _T_4692 | _T_4690; // @[Mux.scala 27:72] - wire [1:0] lsu_nonblock_addr_offset = _T_4693[1:0]; // @[lsu_bus_buffer.scala 540:96] + wire [1:0] lsu_nonblock_addr_offset = _T_4693[1:0]; // @[lsu_bus_buffer.scala 539:96] wire [1:0] _T_4699 = _T_4683 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_4700 = _T_4684 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_4701 = _T_4685 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72] @@ -70495,24 +70390,24 @@ module lsu_bus_buffer( wire _T_4719 = _T_4718 | _T_4716; // @[Mux.scala 27:72] wire lsu_nonblock_unsign = _T_4719 | _T_4717; // @[Mux.scala 27:72] wire [63:0] _T_4739 = {lsu_nonblock_load_data_hi,lsu_nonblock_load_data_lo}; // @[Cat.scala 29:58] - wire [3:0] _GEN_392 = {{2'd0}, lsu_nonblock_addr_offset}; // @[lsu_bus_buffer.scala 544:121] - wire [5:0] _T_4740 = _GEN_392 * 4'h8; // @[lsu_bus_buffer.scala 544:121] - wire [63:0] lsu_nonblock_data_unalgn = _T_4739 >> _T_4740; // @[lsu_bus_buffer.scala 544:92] - wire _T_4741 = ~io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_buffer.scala 546:82] - wire _T_4743 = lsu_nonblock_sz == 2'h0; // @[lsu_bus_buffer.scala 547:94] - wire _T_4744 = lsu_nonblock_unsign & _T_4743; // @[lsu_bus_buffer.scala 547:76] + wire [3:0] _GEN_392 = {{2'd0}, lsu_nonblock_addr_offset}; // @[lsu_bus_buffer.scala 543:121] + wire [5:0] _T_4740 = _GEN_392 * 4'h8; // @[lsu_bus_buffer.scala 543:121] + wire [63:0] lsu_nonblock_data_unalgn = _T_4739 >> _T_4740; // @[lsu_bus_buffer.scala 543:92] + wire _T_4741 = ~io_dctl_busbuff_lsu_nonblock_load_data_error; // @[lsu_bus_buffer.scala 545:82] + wire _T_4743 = lsu_nonblock_sz == 2'h0; // @[lsu_bus_buffer.scala 546:94] + wire _T_4744 = lsu_nonblock_unsign & _T_4743; // @[lsu_bus_buffer.scala 546:76] wire [31:0] _T_4746 = {24'h0,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] - wire _T_4747 = lsu_nonblock_sz == 2'h1; // @[lsu_bus_buffer.scala 548:45] - wire _T_4748 = lsu_nonblock_unsign & _T_4747; // @[lsu_bus_buffer.scala 548:26] + wire _T_4747 = lsu_nonblock_sz == 2'h1; // @[lsu_bus_buffer.scala 547:45] + wire _T_4748 = lsu_nonblock_unsign & _T_4747; // @[lsu_bus_buffer.scala 547:26] wire [31:0] _T_4750 = {16'h0,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] - wire _T_4751 = ~lsu_nonblock_unsign; // @[lsu_bus_buffer.scala 549:6] - wire _T_4753 = _T_4751 & _T_4743; // @[lsu_bus_buffer.scala 549:27] + wire _T_4751 = ~lsu_nonblock_unsign; // @[lsu_bus_buffer.scala 548:6] + wire _T_4753 = _T_4751 & _T_4743; // @[lsu_bus_buffer.scala 548:27] wire [23:0] _T_4756 = lsu_nonblock_data_unalgn[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_4758 = {_T_4756,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] - wire _T_4761 = _T_4751 & _T_4747; // @[lsu_bus_buffer.scala 550:27] + wire _T_4761 = _T_4751 & _T_4747; // @[lsu_bus_buffer.scala 549:27] wire [15:0] _T_4764 = lsu_nonblock_data_unalgn[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] wire [31:0] _T_4766 = {_T_4764,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] - wire _T_4767 = lsu_nonblock_sz == 2'h2; // @[lsu_bus_buffer.scala 551:21] + wire _T_4767 = lsu_nonblock_sz == 2'h2; // @[lsu_bus_buffer.scala 550:21] wire [31:0] _T_4768 = _T_4744 ? _T_4746 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_4769 = _T_4748 ? _T_4750 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_4770 = _T_4753 ? _T_4758 : 32'h0; // @[Mux.scala 27:72] @@ -70523,60 +70418,60 @@ module lsu_bus_buffer( wire [31:0] _T_4775 = _T_4774 | _T_4771; // @[Mux.scala 27:72] wire [63:0] _GEN_393 = {{32'd0}, _T_4775}; // @[Mux.scala 27:72] wire [63:0] _T_4776 = _GEN_393 | _T_4772; // @[Mux.scala 27:72] - wire _T_4871 = obuf_valid & obuf_write; // @[lsu_bus_buffer.scala 569:37] - wire _T_4872 = ~obuf_cmd_done; // @[lsu_bus_buffer.scala 569:52] - wire _T_4873 = _T_4871 & _T_4872; // @[lsu_bus_buffer.scala 569:50] + wire _T_4871 = obuf_valid & obuf_write; // @[lsu_bus_buffer.scala 568:37] + wire _T_4872 = ~obuf_cmd_done; // @[lsu_bus_buffer.scala 568:52] + wire _T_4873 = _T_4871 & _T_4872; // @[lsu_bus_buffer.scala 568:50] wire [31:0] _T_4877 = {obuf_addr[31:3],3'h0}; // @[Cat.scala 29:58] wire [2:0] _T_4879 = {1'h0,obuf_sz}; // @[Cat.scala 29:58] - wire _T_4884 = ~obuf_data_done; // @[lsu_bus_buffer.scala 581:51] - wire _T_4885 = _T_4871 & _T_4884; // @[lsu_bus_buffer.scala 581:49] + wire _T_4884 = ~obuf_data_done; // @[lsu_bus_buffer.scala 580:51] + wire _T_4885 = _T_4871 & _T_4884; // @[lsu_bus_buffer.scala 580:49] wire [7:0] _T_4889 = obuf_write ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire _T_4892 = obuf_valid & _T_1343; // @[lsu_bus_buffer.scala 586:37] - wire _T_4894 = _T_4892 & _T_1349; // @[lsu_bus_buffer.scala 586:51] - wire _T_4906 = io_lsu_bus_clk_en_q & buf_error[0]; // @[lsu_bus_buffer.scala 599:126] - wire _T_4908 = _T_4906 & buf_write[0]; // @[lsu_bus_buffer.scala 599:141] - wire _T_4911 = io_lsu_bus_clk_en_q & buf_error[1]; // @[lsu_bus_buffer.scala 599:126] - wire _T_4913 = _T_4911 & buf_write[1]; // @[lsu_bus_buffer.scala 599:141] - wire _T_4916 = io_lsu_bus_clk_en_q & buf_error[2]; // @[lsu_bus_buffer.scala 599:126] - wire _T_4918 = _T_4916 & buf_write[2]; // @[lsu_bus_buffer.scala 599:141] - wire _T_4921 = io_lsu_bus_clk_en_q & buf_error[3]; // @[lsu_bus_buffer.scala 599:126] - wire _T_4923 = _T_4921 & buf_write[3]; // @[lsu_bus_buffer.scala 599:141] + wire _T_4892 = obuf_valid & _T_1343; // @[lsu_bus_buffer.scala 585:37] + wire _T_4894 = _T_4892 & _T_1349; // @[lsu_bus_buffer.scala 585:51] + wire _T_4906 = io_lsu_bus_clk_en_q & buf_error[0]; // @[lsu_bus_buffer.scala 598:126] + wire _T_4908 = _T_4906 & buf_write[0]; // @[lsu_bus_buffer.scala 598:141] + wire _T_4911 = io_lsu_bus_clk_en_q & buf_error[1]; // @[lsu_bus_buffer.scala 598:126] + wire _T_4913 = _T_4911 & buf_write[1]; // @[lsu_bus_buffer.scala 598:141] + wire _T_4916 = io_lsu_bus_clk_en_q & buf_error[2]; // @[lsu_bus_buffer.scala 598:126] + wire _T_4918 = _T_4916 & buf_write[2]; // @[lsu_bus_buffer.scala 598:141] + wire _T_4921 = io_lsu_bus_clk_en_q & buf_error[3]; // @[lsu_bus_buffer.scala 598:126] + wire _T_4923 = _T_4921 & buf_write[3]; // @[lsu_bus_buffer.scala 598:141] wire _T_4924 = _T_2799 & _T_4908; // @[Mux.scala 27:72] wire _T_4925 = _T_2821 & _T_4913; // @[Mux.scala 27:72] wire _T_4926 = _T_2843 & _T_4918; // @[Mux.scala 27:72] wire _T_4927 = _T_2865 & _T_4923; // @[Mux.scala 27:72] wire _T_4928 = _T_4924 | _T_4925; // @[Mux.scala 27:72] wire _T_4929 = _T_4928 | _T_4926; // @[Mux.scala 27:72] - wire _T_4939 = _T_2821 & buf_error[1]; // @[lsu_bus_buffer.scala 600:93] - wire _T_4941 = _T_4939 & buf_write[1]; // @[lsu_bus_buffer.scala 600:108] - wire _T_4944 = _T_2843 & buf_error[2]; // @[lsu_bus_buffer.scala 600:93] - wire _T_4946 = _T_4944 & buf_write[2]; // @[lsu_bus_buffer.scala 600:108] - wire _T_4949 = _T_2865 & buf_error[3]; // @[lsu_bus_buffer.scala 600:93] - wire _T_4951 = _T_4949 & buf_write[3]; // @[lsu_bus_buffer.scala 600:108] + wire _T_4939 = _T_2821 & buf_error[1]; // @[lsu_bus_buffer.scala 599:93] + wire _T_4941 = _T_4939 & buf_write[1]; // @[lsu_bus_buffer.scala 599:108] + wire _T_4944 = _T_2843 & buf_error[2]; // @[lsu_bus_buffer.scala 599:93] + wire _T_4946 = _T_4944 & buf_write[2]; // @[lsu_bus_buffer.scala 599:108] + wire _T_4949 = _T_2865 & buf_error[3]; // @[lsu_bus_buffer.scala 599:93] + wire _T_4951 = _T_4949 & buf_write[3]; // @[lsu_bus_buffer.scala 599:108] wire [1:0] _T_4954 = _T_4946 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_4955 = _T_4951 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _GEN_394 = {{1'd0}, _T_4941}; // @[Mux.scala 27:72] wire [1:0] _T_4957 = _GEN_394 | _T_4954; // @[Mux.scala 27:72] wire [1:0] lsu_imprecise_error_store_tag = _T_4957 | _T_4955; // @[Mux.scala 27:72] - wire _T_4959 = ~io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 602:97] - wire [31:0] _GEN_351 = 2'h1 == lsu_imprecise_error_store_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 603:53] - wire [31:0] _GEN_352 = 2'h2 == lsu_imprecise_error_store_tag ? buf_addr_2 : _GEN_351; // @[lsu_bus_buffer.scala 603:53] - wire [31:0] _GEN_353 = 2'h3 == lsu_imprecise_error_store_tag ? buf_addr_3 : _GEN_352; // @[lsu_bus_buffer.scala 603:53] - wire [31:0] _GEN_355 = 2'h1 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 603:53] - wire [31:0] _GEN_356 = 2'h2 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_2 : _GEN_355; // @[lsu_bus_buffer.scala 603:53] - wire [31:0] _GEN_357 = 2'h3 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_3 : _GEN_356; // @[lsu_bus_buffer.scala 603:53] - wire _T_4964 = bus_wcmd_sent | bus_wdata_sent; // @[lsu_bus_buffer.scala 609:82] - wire _T_4967 = io_lsu_busreq_r & io_ldst_dual_r; // @[lsu_bus_buffer.scala 610:60] - wire _T_4970 = ~io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 613:61] - wire _T_4971 = io_lsu_axi_aw_valid & _T_4970; // @[lsu_bus_buffer.scala 613:59] - wire _T_4972 = ~io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 613:107] - wire _T_4973 = io_lsu_axi_w_valid & _T_4972; // @[lsu_bus_buffer.scala 613:105] - wire _T_4974 = _T_4971 | _T_4973; // @[lsu_bus_buffer.scala 613:83] - wire _T_4975 = ~io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 613:153] - wire _T_4976 = io_lsu_axi_ar_valid & _T_4975; // @[lsu_bus_buffer.scala 613:151] - wire _T_4980 = ~io_flush_r; // @[lsu_bus_buffer.scala 617:75] - wire _T_4981 = io_lsu_busreq_m & _T_4980; // @[lsu_bus_buffer.scala 617:73] - reg _T_4984; // @[lsu_bus_buffer.scala 617:56] + wire _T_4959 = ~io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 601:97] + wire [31:0] _GEN_351 = 2'h1 == lsu_imprecise_error_store_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 602:53] + wire [31:0] _GEN_352 = 2'h2 == lsu_imprecise_error_store_tag ? buf_addr_2 : _GEN_351; // @[lsu_bus_buffer.scala 602:53] + wire [31:0] _GEN_353 = 2'h3 == lsu_imprecise_error_store_tag ? buf_addr_3 : _GEN_352; // @[lsu_bus_buffer.scala 602:53] + wire [31:0] _GEN_355 = 2'h1 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_1 : buf_addr_0; // @[lsu_bus_buffer.scala 602:53] + wire [31:0] _GEN_356 = 2'h2 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_2 : _GEN_355; // @[lsu_bus_buffer.scala 602:53] + wire [31:0] _GEN_357 = 2'h3 == io_dctl_busbuff_lsu_nonblock_load_data_tag ? buf_addr_3 : _GEN_356; // @[lsu_bus_buffer.scala 602:53] + wire _T_4964 = bus_wcmd_sent | bus_wdata_sent; // @[lsu_bus_buffer.scala 608:82] + wire _T_4967 = io_lsu_busreq_r & io_ldst_dual_r; // @[lsu_bus_buffer.scala 609:60] + wire _T_4970 = ~io_lsu_axi_aw_ready; // @[lsu_bus_buffer.scala 612:61] + wire _T_4971 = io_lsu_axi_aw_valid & _T_4970; // @[lsu_bus_buffer.scala 612:59] + wire _T_4972 = ~io_lsu_axi_w_ready; // @[lsu_bus_buffer.scala 612:107] + wire _T_4973 = io_lsu_axi_w_valid & _T_4972; // @[lsu_bus_buffer.scala 612:105] + wire _T_4974 = _T_4971 | _T_4973; // @[lsu_bus_buffer.scala 612:83] + wire _T_4975 = ~io_lsu_axi_ar_ready; // @[lsu_bus_buffer.scala 612:153] + wire _T_4976 = io_lsu_axi_ar_valid & _T_4975; // @[lsu_bus_buffer.scala 612:151] + wire _T_4980 = ~io_flush_r; // @[lsu_bus_buffer.scala 616:75] + wire _T_4981 = io_lsu_busreq_m & _T_4980; // @[lsu_bus_buffer.scala 616:73] + reg _T_4984; // @[lsu_bus_buffer.scala 616:56] rvclkhdr rvclkhdr ( // @[lib.scala 352:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -70649,42 +70544,42 @@ module lsu_bus_buffer( .io_en(rvclkhdr_11_io_en), .io_scan_mode(rvclkhdr_11_io_scan_mode) ); - assign io_tlu_busbuff_lsu_pmu_bus_trxn = _T_4964 | _T_4863; // @[lsu_bus_buffer.scala 609:35] - assign io_tlu_busbuff_lsu_pmu_bus_misaligned = _T_4967 & io_lsu_commit_r; // @[lsu_bus_buffer.scala 610:41] - assign io_tlu_busbuff_lsu_pmu_bus_error = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 611:36] - assign io_tlu_busbuff_lsu_pmu_bus_busy = _T_4974 | _T_4976; // @[lsu_bus_buffer.scala 613:35] - assign io_tlu_busbuff_lsu_imprecise_error_load_any = io_dctl_busbuff_lsu_nonblock_load_data_error & _T_4959; // @[lsu_bus_buffer.scala 602:47] - assign io_tlu_busbuff_lsu_imprecise_error_store_any = _T_4929 | _T_4927; // @[lsu_bus_buffer.scala 599:48] - assign io_tlu_busbuff_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_store_any ? _GEN_353 : _GEN_357; // @[lsu_bus_buffer.scala 603:47] - assign io_dctl_busbuff_lsu_nonblock_load_valid_m = _T_4517 & _T_4518; // @[lsu_bus_buffer.scala 530:45] - assign io_dctl_busbuff_lsu_nonblock_load_tag_m = _T_1863 ? 2'h0 : _T_1899; // @[lsu_bus_buffer.scala 531:43] - assign io_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & _T_4520; // @[lsu_bus_buffer.scala 533:43] - assign io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = WrPtr0_r; // @[lsu_bus_buffer.scala 534:47] - assign io_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & _T_4741; // @[lsu_bus_buffer.scala 546:48] - assign io_dctl_busbuff_lsu_nonblock_load_data_error = _T_4570 | _T_4568; // @[lsu_bus_buffer.scala 536:48] - assign io_dctl_busbuff_lsu_nonblock_load_data_tag = _T_4610 | _T_4608; // @[lsu_bus_buffer.scala 537:46] - assign io_dctl_busbuff_lsu_nonblock_load_data = _T_4776[31:0]; // @[lsu_bus_buffer.scala 547:42] - assign io_lsu_axi_aw_valid = _T_4873 & _T_1239; // @[lsu_bus_buffer.scala 569:23] - assign io_lsu_axi_aw_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 570:25] - assign io_lsu_axi_aw_bits_addr = obuf_sideeffect ? obuf_addr : _T_4877; // @[lsu_bus_buffer.scala 571:27] - assign io_lsu_axi_aw_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 575:29] - assign io_lsu_axi_aw_bits_size = obuf_sideeffect ? _T_4879 : 3'h3; // @[lsu_bus_buffer.scala 572:27] - assign io_lsu_axi_aw_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 574:28] - assign io_lsu_axi_w_valid = _T_4885 & _T_1239; // @[lsu_bus_buffer.scala 581:22] - assign io_lsu_axi_w_bits_data = obuf_data; // @[lsu_bus_buffer.scala 583:26] - assign io_lsu_axi_w_bits_strb = obuf_byteen & _T_4889; // @[lsu_bus_buffer.scala 582:26] - assign io_lsu_axi_b_ready = 1'h1; // @[lsu_bus_buffer.scala 597:22] - assign io_lsu_axi_ar_valid = _T_4894 & _T_1239; // @[lsu_bus_buffer.scala 586:23] - assign io_lsu_axi_ar_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 587:25] - assign io_lsu_axi_ar_bits_addr = obuf_sideeffect ? obuf_addr : _T_4877; // @[lsu_bus_buffer.scala 588:27] - assign io_lsu_axi_ar_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 592:29] - assign io_lsu_axi_ar_bits_size = obuf_sideeffect ? _T_4879 : 3'h3; // @[lsu_bus_buffer.scala 589:27] - assign io_lsu_axi_ar_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 591:28] - assign io_lsu_axi_r_ready = 1'h1; // @[lsu_bus_buffer.scala 598:22] - assign io_lsu_busreq_r = _T_4984; // @[lsu_bus_buffer.scala 617:19] - assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[lsu_bus_buffer.scala 526:30] - assign io_lsu_bus_buffer_full_any = _T_4498 ? _T_4499 : _T_4500; // @[lsu_bus_buffer.scala 527:30] - assign io_lsu_bus_buffer_empty_any = _T_4511 & _T_1231; // @[lsu_bus_buffer.scala 528:31] + assign io_tlu_busbuff_lsu_pmu_bus_trxn = _T_4964 | _T_4863; // @[lsu_bus_buffer.scala 608:35] + assign io_tlu_busbuff_lsu_pmu_bus_misaligned = _T_4967 & io_lsu_commit_r; // @[lsu_bus_buffer.scala 609:41] + assign io_tlu_busbuff_lsu_pmu_bus_error = io_tlu_busbuff_lsu_imprecise_error_load_any | io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_buffer.scala 610:36] + assign io_tlu_busbuff_lsu_pmu_bus_busy = _T_4974 | _T_4976; // @[lsu_bus_buffer.scala 612:35] + assign io_tlu_busbuff_lsu_imprecise_error_load_any = io_dctl_busbuff_lsu_nonblock_load_data_error & _T_4959; // @[lsu_bus_buffer.scala 601:47] + assign io_tlu_busbuff_lsu_imprecise_error_store_any = _T_4929 | _T_4927; // @[lsu_bus_buffer.scala 598:48] + assign io_tlu_busbuff_lsu_imprecise_error_addr_any = io_tlu_busbuff_lsu_imprecise_error_store_any ? _GEN_353 : _GEN_357; // @[lsu_bus_buffer.scala 602:47] + assign io_dctl_busbuff_lsu_nonblock_load_valid_m = _T_4517 & _T_4518; // @[lsu_bus_buffer.scala 529:45] + assign io_dctl_busbuff_lsu_nonblock_load_tag_m = _T_1863 ? 2'h0 : _T_1899; // @[lsu_bus_buffer.scala 530:43] + assign io_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & _T_4520; // @[lsu_bus_buffer.scala 532:43] + assign io_dctl_busbuff_lsu_nonblock_load_inv_tag_r = WrPtr0_r; // @[lsu_bus_buffer.scala 533:47] + assign io_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & _T_4741; // @[lsu_bus_buffer.scala 545:48] + assign io_dctl_busbuff_lsu_nonblock_load_data_error = _T_4570 | _T_4568; // @[lsu_bus_buffer.scala 535:48] + assign io_dctl_busbuff_lsu_nonblock_load_data_tag = _T_4610 | _T_4608; // @[lsu_bus_buffer.scala 536:46] + assign io_dctl_busbuff_lsu_nonblock_load_data = _T_4776[31:0]; // @[lsu_bus_buffer.scala 546:42] + assign io_lsu_axi_aw_valid = _T_4873 & _T_1239; // @[lsu_bus_buffer.scala 568:23] + assign io_lsu_axi_aw_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 569:25] + assign io_lsu_axi_aw_bits_addr = obuf_sideeffect ? obuf_addr : _T_4877; // @[lsu_bus_buffer.scala 570:27] + assign io_lsu_axi_aw_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 574:29] + assign io_lsu_axi_aw_bits_size = obuf_sideeffect ? _T_4879 : 3'h3; // @[lsu_bus_buffer.scala 571:27] + assign io_lsu_axi_aw_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 573:28] + assign io_lsu_axi_w_valid = _T_4885 & _T_1239; // @[lsu_bus_buffer.scala 580:22] + assign io_lsu_axi_w_bits_data = obuf_data; // @[lsu_bus_buffer.scala 582:26] + assign io_lsu_axi_w_bits_strb = obuf_byteen & _T_4889; // @[lsu_bus_buffer.scala 581:26] + assign io_lsu_axi_b_ready = 1'h1; // @[lsu_bus_buffer.scala 596:22] + assign io_lsu_axi_ar_valid = _T_4894 & _T_1239; // @[lsu_bus_buffer.scala 585:23] + assign io_lsu_axi_ar_bits_id = {{1'd0}, _T_1848}; // @[lsu_bus_buffer.scala 586:25] + assign io_lsu_axi_ar_bits_addr = obuf_sideeffect ? obuf_addr : _T_4877; // @[lsu_bus_buffer.scala 587:27] + assign io_lsu_axi_ar_bits_region = obuf_addr[31:28]; // @[lsu_bus_buffer.scala 591:29] + assign io_lsu_axi_ar_bits_size = obuf_sideeffect ? _T_4879 : 3'h3; // @[lsu_bus_buffer.scala 588:27] + assign io_lsu_axi_ar_bits_cache = obuf_sideeffect ? 4'h0 : 4'hf; // @[lsu_bus_buffer.scala 590:28] + assign io_lsu_axi_r_ready = 1'h1; // @[lsu_bus_buffer.scala 597:22] + assign io_lsu_busreq_r = _T_4984; // @[lsu_bus_buffer.scala 616:19] + assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[lsu_bus_buffer.scala 525:30] + assign io_lsu_bus_buffer_full_any = _T_4498 ? _T_4499 : _T_4500; // @[lsu_bus_buffer.scala 526:30] + assign io_lsu_bus_buffer_empty_any = _T_4511 & _T_1231; // @[lsu_bus_buffer.scala 527:31] assign io_ld_byte_hit_buf_lo = {_T_69,_T_58}; // @[lsu_bus_buffer.scala 138:25] assign io_ld_byte_hit_buf_hi = {_T_84,_T_73}; // @[lsu_bus_buffer.scala 139:25] assign io_ld_fwddata_buf_lo = _T_650 | _T_651; // @[lsu_bus_buffer.scala 165:24] @@ -70829,151 +70724,147 @@ initial begin _RAND_33 = {1{`RANDOM}}; ibuf_data = _RAND_33[31:0]; _RAND_34 = {1{`RANDOM}}; - ibuf_timer = _RAND_34[2:0]; + ibuf_sideeffect = _RAND_34[0:0]; _RAND_35 = {1{`RANDOM}}; - ibuf_sideeffect = _RAND_35[0:0]; + WrPtr1_r = _RAND_35[1:0]; _RAND_36 = {1{`RANDOM}}; - WrPtr1_r = _RAND_36[1:0]; + WrPtr0_r = _RAND_36[1:0]; _RAND_37 = {1{`RANDOM}}; - WrPtr0_r = _RAND_37[1:0]; + ibuf_tag = _RAND_37[1:0]; _RAND_38 = {1{`RANDOM}}; - ibuf_tag = _RAND_38[1:0]; + ibuf_dualtag = _RAND_38[1:0]; _RAND_39 = {1{`RANDOM}}; - ibuf_dualtag = _RAND_39[1:0]; + ibuf_dual = _RAND_39[0:0]; _RAND_40 = {1{`RANDOM}}; - ibuf_dual = _RAND_40[0:0]; + ibuf_samedw = _RAND_40[0:0]; _RAND_41 = {1{`RANDOM}}; - ibuf_samedw = _RAND_41[0:0]; + ibuf_nomerge = _RAND_41[0:0]; _RAND_42 = {1{`RANDOM}}; - ibuf_nomerge = _RAND_42[0:0]; + ibuf_unsign = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; - ibuf_unsign = _RAND_43[0:0]; + ibuf_sz = _RAND_43[1:0]; _RAND_44 = {1{`RANDOM}}; - ibuf_sz = _RAND_44[1:0]; + buf_nomerge_0 = _RAND_44[0:0]; _RAND_45 = {1{`RANDOM}}; - obuf_wr_timer = _RAND_45[2:0]; + buf_nomerge_1 = _RAND_45[0:0]; _RAND_46 = {1{`RANDOM}}; - buf_nomerge_0 = _RAND_46[0:0]; + buf_nomerge_2 = _RAND_46[0:0]; _RAND_47 = {1{`RANDOM}}; - buf_nomerge_1 = _RAND_47[0:0]; + buf_nomerge_3 = _RAND_47[0:0]; _RAND_48 = {1{`RANDOM}}; - buf_nomerge_2 = _RAND_48[0:0]; + _T_4330 = _RAND_48[0:0]; _RAND_49 = {1{`RANDOM}}; - buf_nomerge_3 = _RAND_49[0:0]; + _T_4327 = _RAND_49[0:0]; _RAND_50 = {1{`RANDOM}}; - _T_4330 = _RAND_50[0:0]; + _T_4324 = _RAND_50[0:0]; _RAND_51 = {1{`RANDOM}}; - _T_4327 = _RAND_51[0:0]; + _T_4321 = _RAND_51[0:0]; _RAND_52 = {1{`RANDOM}}; - _T_4324 = _RAND_52[0:0]; + buf_dual_3 = _RAND_52[0:0]; _RAND_53 = {1{`RANDOM}}; - _T_4321 = _RAND_53[0:0]; + buf_dual_2 = _RAND_53[0:0]; _RAND_54 = {1{`RANDOM}}; - buf_dual_3 = _RAND_54[0:0]; + buf_dual_1 = _RAND_54[0:0]; _RAND_55 = {1{`RANDOM}}; - buf_dual_2 = _RAND_55[0:0]; + buf_dual_0 = _RAND_55[0:0]; _RAND_56 = {1{`RANDOM}}; - buf_dual_1 = _RAND_56[0:0]; + buf_samedw_3 = _RAND_56[0:0]; _RAND_57 = {1{`RANDOM}}; - buf_dual_0 = _RAND_57[0:0]; + buf_samedw_2 = _RAND_57[0:0]; _RAND_58 = {1{`RANDOM}}; - buf_samedw_3 = _RAND_58[0:0]; + buf_samedw_1 = _RAND_58[0:0]; _RAND_59 = {1{`RANDOM}}; - buf_samedw_2 = _RAND_59[0:0]; + buf_samedw_0 = _RAND_59[0:0]; _RAND_60 = {1{`RANDOM}}; - buf_samedw_1 = _RAND_60[0:0]; + obuf_write = _RAND_60[0:0]; _RAND_61 = {1{`RANDOM}}; - buf_samedw_0 = _RAND_61[0:0]; + obuf_cmd_done = _RAND_61[0:0]; _RAND_62 = {1{`RANDOM}}; - obuf_write = _RAND_62[0:0]; + obuf_data_done = _RAND_62[0:0]; _RAND_63 = {1{`RANDOM}}; - obuf_cmd_done = _RAND_63[0:0]; + obuf_nosend = _RAND_63[0:0]; _RAND_64 = {1{`RANDOM}}; - obuf_data_done = _RAND_64[0:0]; + obuf_addr = _RAND_64[31:0]; _RAND_65 = {1{`RANDOM}}; - obuf_nosend = _RAND_65[0:0]; + buf_sz_0 = _RAND_65[1:0]; _RAND_66 = {1{`RANDOM}}; - obuf_addr = _RAND_66[31:0]; + buf_sz_1 = _RAND_66[1:0]; _RAND_67 = {1{`RANDOM}}; - buf_sz_0 = _RAND_67[1:0]; + buf_sz_2 = _RAND_67[1:0]; _RAND_68 = {1{`RANDOM}}; - buf_sz_1 = _RAND_68[1:0]; + buf_sz_3 = _RAND_68[1:0]; _RAND_69 = {1{`RANDOM}}; - buf_sz_2 = _RAND_69[1:0]; + obuf_sideeffect = _RAND_69[0:0]; _RAND_70 = {1{`RANDOM}}; - buf_sz_3 = _RAND_70[1:0]; + obuf_rdrsp_pend = _RAND_70[0:0]; _RAND_71 = {1{`RANDOM}}; - obuf_sideeffect = _RAND_71[0:0]; + obuf_rdrsp_tag = _RAND_71[2:0]; _RAND_72 = {1{`RANDOM}}; - obuf_rdrsp_pend = _RAND_72[0:0]; + buf_dualhi_3 = _RAND_72[0:0]; _RAND_73 = {1{`RANDOM}}; - obuf_rdrsp_tag = _RAND_73[2:0]; + buf_dualhi_2 = _RAND_73[0:0]; _RAND_74 = {1{`RANDOM}}; - buf_dualhi_3 = _RAND_74[0:0]; + buf_dualhi_1 = _RAND_74[0:0]; _RAND_75 = {1{`RANDOM}}; - buf_dualhi_2 = _RAND_75[0:0]; + buf_dualhi_0 = _RAND_75[0:0]; _RAND_76 = {1{`RANDOM}}; - buf_dualhi_1 = _RAND_76[0:0]; + obuf_sz = _RAND_76[1:0]; _RAND_77 = {1{`RANDOM}}; - buf_dualhi_0 = _RAND_77[0:0]; - _RAND_78 = {1{`RANDOM}}; - obuf_sz = _RAND_78[1:0]; + obuf_byteen = _RAND_77[7:0]; + _RAND_78 = {2{`RANDOM}}; + obuf_data = _RAND_78[63:0]; _RAND_79 = {1{`RANDOM}}; - obuf_byteen = _RAND_79[7:0]; - _RAND_80 = {2{`RANDOM}}; - obuf_data = _RAND_80[63:0]; + buf_rspageQ_0 = _RAND_79[3:0]; + _RAND_80 = {1{`RANDOM}}; + buf_rspageQ_1 = _RAND_80[3:0]; _RAND_81 = {1{`RANDOM}}; - buf_rspageQ_0 = _RAND_81[3:0]; + buf_rspageQ_2 = _RAND_81[3:0]; _RAND_82 = {1{`RANDOM}}; - buf_rspageQ_1 = _RAND_82[3:0]; + buf_rspageQ_3 = _RAND_82[3:0]; _RAND_83 = {1{`RANDOM}}; - buf_rspageQ_2 = _RAND_83[3:0]; + _T_4307 = _RAND_83[0:0]; _RAND_84 = {1{`RANDOM}}; - buf_rspageQ_3 = _RAND_84[3:0]; + _T_4305 = _RAND_84[0:0]; _RAND_85 = {1{`RANDOM}}; - _T_4307 = _RAND_85[0:0]; + _T_4303 = _RAND_85[0:0]; _RAND_86 = {1{`RANDOM}}; - _T_4305 = _RAND_86[0:0]; + _T_4301 = _RAND_86[0:0]; _RAND_87 = {1{`RANDOM}}; - _T_4303 = _RAND_87[0:0]; + buf_ldfwdtag_0 = _RAND_87[1:0]; _RAND_88 = {1{`RANDOM}}; - _T_4301 = _RAND_88[0:0]; + buf_dualtag_0 = _RAND_88[1:0]; _RAND_89 = {1{`RANDOM}}; - buf_ldfwdtag_0 = _RAND_89[1:0]; + buf_ldfwdtag_3 = _RAND_89[1:0]; _RAND_90 = {1{`RANDOM}}; - buf_dualtag_0 = _RAND_90[1:0]; + buf_ldfwdtag_2 = _RAND_90[1:0]; _RAND_91 = {1{`RANDOM}}; - buf_ldfwdtag_3 = _RAND_91[1:0]; + buf_ldfwdtag_1 = _RAND_91[1:0]; _RAND_92 = {1{`RANDOM}}; - buf_ldfwdtag_2 = _RAND_92[1:0]; + buf_dualtag_1 = _RAND_92[1:0]; _RAND_93 = {1{`RANDOM}}; - buf_ldfwdtag_1 = _RAND_93[1:0]; + buf_dualtag_2 = _RAND_93[1:0]; _RAND_94 = {1{`RANDOM}}; - buf_dualtag_1 = _RAND_94[1:0]; + buf_dualtag_3 = _RAND_94[1:0]; _RAND_95 = {1{`RANDOM}}; - buf_dualtag_2 = _RAND_95[1:0]; + _T_4336 = _RAND_95[0:0]; _RAND_96 = {1{`RANDOM}}; - buf_dualtag_3 = _RAND_96[1:0]; + _T_4339 = _RAND_96[0:0]; _RAND_97 = {1{`RANDOM}}; - _T_4336 = _RAND_97[0:0]; + _T_4342 = _RAND_97[0:0]; _RAND_98 = {1{`RANDOM}}; - _T_4339 = _RAND_98[0:0]; + _T_4345 = _RAND_98[0:0]; _RAND_99 = {1{`RANDOM}}; - _T_4342 = _RAND_99[0:0]; + _T_4411 = _RAND_99[0:0]; _RAND_100 = {1{`RANDOM}}; - _T_4345 = _RAND_100[0:0]; + _T_4406 = _RAND_100[0:0]; _RAND_101 = {1{`RANDOM}}; - _T_4411 = _RAND_101[0:0]; + _T_4401 = _RAND_101[0:0]; _RAND_102 = {1{`RANDOM}}; - _T_4406 = _RAND_102[0:0]; + _T_4396 = _RAND_102[0:0]; _RAND_103 = {1{`RANDOM}}; - _T_4401 = _RAND_103[0:0]; + lsu_nonblock_load_valid_r = _RAND_103[0:0]; _RAND_104 = {1{`RANDOM}}; - _T_4396 = _RAND_104[0:0]; - _RAND_105 = {1{`RANDOM}}; - lsu_nonblock_load_valid_r = _RAND_105[0:0]; - _RAND_106 = {1{`RANDOM}}; - _T_4984 = _RAND_106[0:0]; + _T_4984 = _RAND_104[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin buf_addr_0 = 32'h0; @@ -71077,9 +70968,6 @@ initial begin if (reset) begin ibuf_data = 32'h0; end - if (reset) begin - ibuf_timer = 3'h0; - end if (reset) begin ibuf_sideeffect = 1'h0; end @@ -71110,9 +70998,6 @@ initial begin if (reset) begin ibuf_sz = 2'h0; end - if (reset) begin - obuf_wr_timer = 3'h0; - end if (reset) begin buf_nomerge_0 = 1'h0; end @@ -71715,9 +71600,7 @@ end // initial if (reset) begin ibuf_byteen <= 4'h0; end else if (ibuf_wr_en) begin - if (_T_866) begin - ibuf_byteen <= _T_881; - end else if (io_ldst_dual_r) begin + if (io_ldst_dual_r) begin ibuf_byteen <= ldst_byteen_hi_r; end else begin ibuf_byteen <= ldst_byteen_lo_r; @@ -71881,16 +71764,7 @@ end // initial if (reset) begin ibuf_data <= 32'h0; end else begin - ibuf_data <= {_T_922,_T_893}; - end - end - always @(posedge io_lsu_free_c2_clk or posedge reset) begin - if (reset) begin - ibuf_timer <= 3'h0; - end else if (ibuf_wr_en) begin - ibuf_timer <= 3'h0; - end else if (_T_923) begin - ibuf_timer <= _T_926; + ibuf_data <= {_T_922,_T_892}; end end always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin @@ -71930,12 +71804,10 @@ end // initial if (reset) begin ibuf_tag <= 2'h0; end else if (ibuf_wr_en) begin - if (!(_T_866)) begin - if (io_ldst_dual_r) begin - ibuf_tag <= WrPtr1_r; - end else begin - ibuf_tag <= WrPtr0_r; - end + if (io_ldst_dual_r) begin + ibuf_tag <= WrPtr1_r; + end else begin + ibuf_tag <= WrPtr0_r; end end end @@ -71981,15 +71853,6 @@ end // initial ibuf_sz <= ibuf_sz_in; end end - always @(posedge io_lsu_busm_clk or posedge reset) begin - if (reset) begin - obuf_wr_timer <= 3'h0; - end else if (obuf_wr_en) begin - obuf_wr_timer <= 3'h0; - end else if (_T_1058) begin - obuf_wr_timer <= _T_1060; - end - end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_nomerge_0 <= 1'h0; @@ -72537,7 +72400,6 @@ module lsu_bus_intf( output io_tlu_busbuff_lsu_pmu_bus_error, output io_tlu_busbuff_lsu_pmu_bus_busy, input io_tlu_busbuff_dec_tlu_external_ldfwd_disable, - input io_tlu_busbuff_dec_tlu_wb_coalescing_disable, input io_tlu_busbuff_dec_tlu_sideeffect_posted_disable, output io_tlu_busbuff_lsu_imprecise_error_load_any, output io_tlu_busbuff_lsu_imprecise_error_store_any, @@ -72632,7 +72494,6 @@ module lsu_bus_intf( wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu_bus_intf.scala 102:39] wire bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu_bus_intf.scala 102:39] wire bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 102:39] - wire bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 102:39] wire bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 102:39] wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu_bus_intf.scala 102:39] wire bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu_bus_intf.scala 102:39] @@ -72905,7 +72766,6 @@ module lsu_bus_intf( .io_tlu_busbuff_lsu_pmu_bus_error(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_error), .io_tlu_busbuff_lsu_pmu_bus_busy(bus_buffer_io_tlu_busbuff_lsu_pmu_bus_busy), .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), - .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_load_any), .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_buffer_io_tlu_busbuff_lsu_imprecise_error_store_any), @@ -73028,7 +72888,6 @@ module lsu_bus_intf( assign bus_buffer_reset = reset; assign bus_buffer_io_scan_mode = io_scan_mode; // @[lsu_bus_intf.scala 104:29] assign bus_buffer_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu_bus_intf.scala 105:18] - assign bus_buffer_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu_bus_intf.scala 105:18] assign bus_buffer_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu_bus_intf.scala 105:18] assign bus_buffer_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[lsu_bus_intf.scala 107:51] assign bus_buffer_io_lsu_c2_r_clk = io_lsu_c2_r_clk; // @[lsu_bus_intf.scala 108:51] @@ -73209,7 +73068,6 @@ module lsu( output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error, output io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy, input io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable, - input io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable, input io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable, output io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any, output io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any, @@ -73679,7 +73537,6 @@ module lsu( wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_error; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 68:30] - wire bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any; // @[lsu.scala 68:30] wire bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any; // @[lsu.scala 68:30] @@ -74164,7 +74021,6 @@ module lsu( .io_tlu_busbuff_lsu_pmu_bus_error(bus_intf_io_tlu_busbuff_lsu_pmu_bus_error), .io_tlu_busbuff_lsu_pmu_bus_busy(bus_intf_io_tlu_busbuff_lsu_pmu_bus_busy), .io_tlu_busbuff_dec_tlu_external_ldfwd_disable(bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable), - .io_tlu_busbuff_dec_tlu_wb_coalescing_disable(bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_tlu_busbuff_dec_tlu_sideeffect_posted_disable(bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_tlu_busbuff_lsu_imprecise_error_load_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_load_any), .io_tlu_busbuff_lsu_imprecise_error_store_any(bus_intf_io_tlu_busbuff_lsu_imprecise_error_store_any), @@ -74529,7 +74385,6 @@ module lsu( assign bus_intf_reset = reset; assign bus_intf_io_scan_mode = io_scan_mode; // @[lsu.scala 285:49] assign bus_intf_io_tlu_busbuff_dec_tlu_external_ldfwd_disable = io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[lsu.scala 286:26] - assign bus_intf_io_tlu_busbuff_dec_tlu_wb_coalescing_disable = io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[lsu.scala 286:26] assign bus_intf_io_tlu_busbuff_dec_tlu_sideeffect_posted_disable = io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[lsu.scala 286:26] assign bus_intf_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[lsu.scala 287:49] assign bus_intf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[lsu.scala 288:49] @@ -74671,12 +74526,12 @@ module pic_ctrl( input [31:0] io_lsu_pic_picm_wraddr, input [31:0] io_lsu_pic_picm_wr_data, output [31:0] io_lsu_pic_picm_rd_data, - input [3:0] io_meicurpl, - input [3:0] io_meipt, - output io_mexintpend, - output [7:0] io_claimid, - output [3:0] io_pl, - output io_mhwakeup + output [7:0] io_dec_pic_pic_claimid, + output [3:0] io_dec_pic_pic_pl, + output io_dec_pic_mhwakeup, + input [3:0] io_dec_pic_dec_tlu_meicurpl, + input [3:0] io_dec_pic_dec_tlu_meipt, + output io_dec_pic_mexintpend ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; @@ -74837,539 +74692,539 @@ module pic_ctrl( wire rvclkhdr_4_io_clk; // @[lib.scala 327:22] wire rvclkhdr_4_io_en; // @[lib.scala 327:22] wire rvclkhdr_4_io_scan_mode; // @[lib.scala 327:22] - wire pic_raddr_c1_clk = rvclkhdr_io_l1clk; // @[pic_ctrl.scala 94:42 pic_ctrl.scala 131:21] - reg [31:0] picm_raddr_ff; // @[pic_ctrl.scala 100:56] - wire pic_data_c1_clk = rvclkhdr_1_io_l1clk; // @[pic_ctrl.scala 95:42 pic_ctrl.scala 132:21] - reg [31:0] picm_waddr_ff; // @[pic_ctrl.scala 101:57] - reg picm_wren_ff; // @[pic_ctrl.scala 102:55] - reg picm_rden_ff; // @[pic_ctrl.scala 103:55] - reg picm_mken_ff; // @[pic_ctrl.scala 104:55] - reg [31:0] picm_wr_data_ff; // @[pic_ctrl.scala 105:58] - wire [31:0] _T_6 = picm_raddr_ff ^ 32'hf00c2000; // @[pic_ctrl.scala 107:59] - wire [31:0] temp_raddr_intenable_base_match = ~_T_6; // @[pic_ctrl.scala 107:43] - wire raddr_intenable_base_match = &temp_raddr_intenable_base_match[31:7]; // @[pic_ctrl.scala 108:89] - wire raddr_intpriority_base_match = picm_raddr_ff[31:7] == 25'h1e01800; // @[pic_ctrl.scala 110:71] - wire raddr_config_gw_base_match = picm_raddr_ff[31:7] == 25'h1e01880; // @[pic_ctrl.scala 111:71] - wire raddr_config_pic_match = picm_raddr_ff == 32'hf00c3000; // @[pic_ctrl.scala 112:71] - wire addr_intpend_base_match = picm_raddr_ff[31:6] == 26'h3c03040; // @[pic_ctrl.scala 113:71] - wire waddr_config_pic_match = picm_waddr_ff == 32'hf00c3000; // @[pic_ctrl.scala 115:71] - wire addr_clear_gw_base_match = picm_waddr_ff[31:7] == 25'h1e018a0; // @[pic_ctrl.scala 116:71] - wire waddr_intpriority_base_match = picm_waddr_ff[31:7] == 25'h1e01800; // @[pic_ctrl.scala 117:71] - wire waddr_intenable_base_match = picm_waddr_ff[31:7] == 25'h1e01840; // @[pic_ctrl.scala 118:71] - wire waddr_config_gw_base_match = picm_waddr_ff[31:7] == 25'h1e01880; // @[pic_ctrl.scala 119:71] - wire _T_17 = picm_rden_ff & picm_wren_ff; // @[pic_ctrl.scala 120:53] - wire _T_18 = picm_raddr_ff == picm_waddr_ff; // @[pic_ctrl.scala 120:86] - wire picm_bypass_ff = _T_17 & _T_18; // @[pic_ctrl.scala 120:68] - wire _T_19 = io_lsu_pic_picm_mken | io_lsu_pic_picm_rden; // @[pic_ctrl.scala 124:50] - wire _T_20 = waddr_intpriority_base_match & picm_wren_ff; // @[pic_ctrl.scala 126:59] - wire _T_21 = raddr_intpriority_base_match & picm_rden_ff; // @[pic_ctrl.scala 126:108] - wire _T_22 = _T_20 | _T_21; // @[pic_ctrl.scala 126:76] - wire _T_23 = waddr_intenable_base_match & picm_wren_ff; // @[pic_ctrl.scala 127:57] - wire _T_24 = raddr_intenable_base_match & picm_rden_ff; // @[pic_ctrl.scala 127:104] - wire _T_25 = _T_23 | _T_24; // @[pic_ctrl.scala 127:74] - wire _T_26 = waddr_config_gw_base_match & picm_wren_ff; // @[pic_ctrl.scala 128:59] - wire _T_27 = raddr_config_gw_base_match & picm_rden_ff; // @[pic_ctrl.scala 128:108] - wire _T_28 = _T_26 | _T_27; // @[pic_ctrl.scala 128:76] + wire pic_raddr_c1_clk = rvclkhdr_io_l1clk; // @[pic_ctrl.scala 95:42 pic_ctrl.scala 132:21] + reg [31:0] picm_raddr_ff; // @[pic_ctrl.scala 101:56] + wire pic_data_c1_clk = rvclkhdr_1_io_l1clk; // @[pic_ctrl.scala 96:42 pic_ctrl.scala 133:21] + reg [31:0] picm_waddr_ff; // @[pic_ctrl.scala 102:57] + reg picm_wren_ff; // @[pic_ctrl.scala 103:55] + reg picm_rden_ff; // @[pic_ctrl.scala 104:55] + reg picm_mken_ff; // @[pic_ctrl.scala 105:55] + reg [31:0] picm_wr_data_ff; // @[pic_ctrl.scala 106:58] + wire [31:0] _T_6 = picm_raddr_ff ^ 32'hf00c2000; // @[pic_ctrl.scala 108:59] + wire [31:0] temp_raddr_intenable_base_match = ~_T_6; // @[pic_ctrl.scala 108:43] + wire raddr_intenable_base_match = &temp_raddr_intenable_base_match[31:7]; // @[pic_ctrl.scala 109:89] + wire raddr_intpriority_base_match = picm_raddr_ff[31:7] == 25'h1e01800; // @[pic_ctrl.scala 111:71] + wire raddr_config_gw_base_match = picm_raddr_ff[31:7] == 25'h1e01880; // @[pic_ctrl.scala 112:71] + wire raddr_config_pic_match = picm_raddr_ff == 32'hf00c3000; // @[pic_ctrl.scala 113:71] + wire addr_intpend_base_match = picm_raddr_ff[31:6] == 26'h3c03040; // @[pic_ctrl.scala 114:71] + wire waddr_config_pic_match = picm_waddr_ff == 32'hf00c3000; // @[pic_ctrl.scala 116:71] + wire addr_clear_gw_base_match = picm_waddr_ff[31:7] == 25'h1e018a0; // @[pic_ctrl.scala 117:71] + wire waddr_intpriority_base_match = picm_waddr_ff[31:7] == 25'h1e01800; // @[pic_ctrl.scala 118:71] + wire waddr_intenable_base_match = picm_waddr_ff[31:7] == 25'h1e01840; // @[pic_ctrl.scala 119:71] + wire waddr_config_gw_base_match = picm_waddr_ff[31:7] == 25'h1e01880; // @[pic_ctrl.scala 120:71] + wire _T_17 = picm_rden_ff & picm_wren_ff; // @[pic_ctrl.scala 121:53] + wire _T_18 = picm_raddr_ff == picm_waddr_ff; // @[pic_ctrl.scala 121:86] + wire picm_bypass_ff = _T_17 & _T_18; // @[pic_ctrl.scala 121:68] + wire _T_19 = io_lsu_pic_picm_mken | io_lsu_pic_picm_rden; // @[pic_ctrl.scala 125:50] + wire _T_20 = waddr_intpriority_base_match & picm_wren_ff; // @[pic_ctrl.scala 127:59] + wire _T_21 = raddr_intpriority_base_match & picm_rden_ff; // @[pic_ctrl.scala 127:108] + wire _T_22 = _T_20 | _T_21; // @[pic_ctrl.scala 127:76] + wire _T_23 = waddr_intenable_base_match & picm_wren_ff; // @[pic_ctrl.scala 128:57] + wire _T_24 = raddr_intenable_base_match & picm_rden_ff; // @[pic_ctrl.scala 128:104] + wire _T_25 = _T_23 | _T_24; // @[pic_ctrl.scala 128:74] + wire _T_26 = waddr_config_gw_base_match & picm_wren_ff; // @[pic_ctrl.scala 129:59] + wire _T_27 = raddr_config_gw_base_match & picm_rden_ff; // @[pic_ctrl.scala 129:108] + wire _T_28 = _T_26 | _T_27; // @[pic_ctrl.scala 129:76] reg [30:0] _T_33; // @[lib.scala 21:81] reg [30:0] _T_34; // @[lib.scala 21:58] wire [31:0] extintsrc_req_sync = {_T_34,io_extintsrc_req[0]}; // @[Cat.scala 29:58] - wire _T_37 = picm_waddr_ff[6:2] == 5'h1; // @[pic_ctrl.scala 140:139] - wire _T_38 = waddr_intpriority_base_match & _T_37; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_1 = _T_38 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_40 = picm_waddr_ff[6:2] == 5'h2; // @[pic_ctrl.scala 140:139] - wire _T_41 = waddr_intpriority_base_match & _T_40; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_2 = _T_41 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_43 = picm_waddr_ff[6:2] == 5'h3; // @[pic_ctrl.scala 140:139] - wire _T_44 = waddr_intpriority_base_match & _T_43; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_3 = _T_44 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_46 = picm_waddr_ff[6:2] == 5'h4; // @[pic_ctrl.scala 140:139] - wire _T_47 = waddr_intpriority_base_match & _T_46; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_4 = _T_47 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_49 = picm_waddr_ff[6:2] == 5'h5; // @[pic_ctrl.scala 140:139] - wire _T_50 = waddr_intpriority_base_match & _T_49; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_5 = _T_50 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_52 = picm_waddr_ff[6:2] == 5'h6; // @[pic_ctrl.scala 140:139] - wire _T_53 = waddr_intpriority_base_match & _T_52; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_6 = _T_53 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_55 = picm_waddr_ff[6:2] == 5'h7; // @[pic_ctrl.scala 140:139] - wire _T_56 = waddr_intpriority_base_match & _T_55; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_7 = _T_56 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_58 = picm_waddr_ff[6:2] == 5'h8; // @[pic_ctrl.scala 140:139] - wire _T_59 = waddr_intpriority_base_match & _T_58; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_8 = _T_59 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_61 = picm_waddr_ff[6:2] == 5'h9; // @[pic_ctrl.scala 140:139] - wire _T_62 = waddr_intpriority_base_match & _T_61; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_9 = _T_62 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_64 = picm_waddr_ff[6:2] == 5'ha; // @[pic_ctrl.scala 140:139] - wire _T_65 = waddr_intpriority_base_match & _T_64; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_10 = _T_65 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_67 = picm_waddr_ff[6:2] == 5'hb; // @[pic_ctrl.scala 140:139] - wire _T_68 = waddr_intpriority_base_match & _T_67; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_11 = _T_68 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_70 = picm_waddr_ff[6:2] == 5'hc; // @[pic_ctrl.scala 140:139] - wire _T_71 = waddr_intpriority_base_match & _T_70; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_12 = _T_71 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_73 = picm_waddr_ff[6:2] == 5'hd; // @[pic_ctrl.scala 140:139] - wire _T_74 = waddr_intpriority_base_match & _T_73; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_13 = _T_74 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_76 = picm_waddr_ff[6:2] == 5'he; // @[pic_ctrl.scala 140:139] - wire _T_77 = waddr_intpriority_base_match & _T_76; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_14 = _T_77 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_79 = picm_waddr_ff[6:2] == 5'hf; // @[pic_ctrl.scala 140:139] - wire _T_80 = waddr_intpriority_base_match & _T_79; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_15 = _T_80 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_82 = picm_waddr_ff[6:2] == 5'h10; // @[pic_ctrl.scala 140:139] - wire _T_83 = waddr_intpriority_base_match & _T_82; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_16 = _T_83 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_85 = picm_waddr_ff[6:2] == 5'h11; // @[pic_ctrl.scala 140:139] - wire _T_86 = waddr_intpriority_base_match & _T_85; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_17 = _T_86 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_88 = picm_waddr_ff[6:2] == 5'h12; // @[pic_ctrl.scala 140:139] - wire _T_89 = waddr_intpriority_base_match & _T_88; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_18 = _T_89 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_91 = picm_waddr_ff[6:2] == 5'h13; // @[pic_ctrl.scala 140:139] - wire _T_92 = waddr_intpriority_base_match & _T_91; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_19 = _T_92 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_94 = picm_waddr_ff[6:2] == 5'h14; // @[pic_ctrl.scala 140:139] - wire _T_95 = waddr_intpriority_base_match & _T_94; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_20 = _T_95 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_97 = picm_waddr_ff[6:2] == 5'h15; // @[pic_ctrl.scala 140:139] - wire _T_98 = waddr_intpriority_base_match & _T_97; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_21 = _T_98 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_100 = picm_waddr_ff[6:2] == 5'h16; // @[pic_ctrl.scala 140:139] - wire _T_101 = waddr_intpriority_base_match & _T_100; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_22 = _T_101 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_103 = picm_waddr_ff[6:2] == 5'h17; // @[pic_ctrl.scala 140:139] - wire _T_104 = waddr_intpriority_base_match & _T_103; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_23 = _T_104 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_106 = picm_waddr_ff[6:2] == 5'h18; // @[pic_ctrl.scala 140:139] - wire _T_107 = waddr_intpriority_base_match & _T_106; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_24 = _T_107 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_109 = picm_waddr_ff[6:2] == 5'h19; // @[pic_ctrl.scala 140:139] - wire _T_110 = waddr_intpriority_base_match & _T_109; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_25 = _T_110 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_112 = picm_waddr_ff[6:2] == 5'h1a; // @[pic_ctrl.scala 140:139] - wire _T_113 = waddr_intpriority_base_match & _T_112; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_26 = _T_113 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_115 = picm_waddr_ff[6:2] == 5'h1b; // @[pic_ctrl.scala 140:139] - wire _T_116 = waddr_intpriority_base_match & _T_115; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_27 = _T_116 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_118 = picm_waddr_ff[6:2] == 5'h1c; // @[pic_ctrl.scala 140:139] - wire _T_119 = waddr_intpriority_base_match & _T_118; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_28 = _T_119 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_121 = picm_waddr_ff[6:2] == 5'h1d; // @[pic_ctrl.scala 140:139] - wire _T_122 = waddr_intpriority_base_match & _T_121; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_29 = _T_122 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_124 = picm_waddr_ff[6:2] == 5'h1e; // @[pic_ctrl.scala 140:139] - wire _T_125 = waddr_intpriority_base_match & _T_124; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_30 = _T_125 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_127 = picm_waddr_ff[6:2] == 5'h1f; // @[pic_ctrl.scala 140:139] - wire _T_128 = waddr_intpriority_base_match & _T_127; // @[pic_ctrl.scala 140:106] - wire intpriority_reg_we_31 = _T_128 & picm_wren_ff; // @[pic_ctrl.scala 140:153] - wire _T_130 = picm_raddr_ff[6:2] == 5'h1; // @[pic_ctrl.scala 141:139] - wire _T_131 = raddr_intpriority_base_match & _T_130; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_1 = _T_131 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_133 = picm_raddr_ff[6:2] == 5'h2; // @[pic_ctrl.scala 141:139] - wire _T_134 = raddr_intpriority_base_match & _T_133; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_2 = _T_134 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_136 = picm_raddr_ff[6:2] == 5'h3; // @[pic_ctrl.scala 141:139] - wire _T_137 = raddr_intpriority_base_match & _T_136; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_3 = _T_137 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_139 = picm_raddr_ff[6:2] == 5'h4; // @[pic_ctrl.scala 141:139] - wire _T_140 = raddr_intpriority_base_match & _T_139; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_4 = _T_140 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_142 = picm_raddr_ff[6:2] == 5'h5; // @[pic_ctrl.scala 141:139] - wire _T_143 = raddr_intpriority_base_match & _T_142; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_5 = _T_143 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_145 = picm_raddr_ff[6:2] == 5'h6; // @[pic_ctrl.scala 141:139] - wire _T_146 = raddr_intpriority_base_match & _T_145; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_6 = _T_146 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_148 = picm_raddr_ff[6:2] == 5'h7; // @[pic_ctrl.scala 141:139] - wire _T_149 = raddr_intpriority_base_match & _T_148; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_7 = _T_149 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_151 = picm_raddr_ff[6:2] == 5'h8; // @[pic_ctrl.scala 141:139] - wire _T_152 = raddr_intpriority_base_match & _T_151; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_8 = _T_152 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_154 = picm_raddr_ff[6:2] == 5'h9; // @[pic_ctrl.scala 141:139] - wire _T_155 = raddr_intpriority_base_match & _T_154; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_9 = _T_155 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_157 = picm_raddr_ff[6:2] == 5'ha; // @[pic_ctrl.scala 141:139] - wire _T_158 = raddr_intpriority_base_match & _T_157; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_10 = _T_158 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_160 = picm_raddr_ff[6:2] == 5'hb; // @[pic_ctrl.scala 141:139] - wire _T_161 = raddr_intpriority_base_match & _T_160; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_11 = _T_161 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_163 = picm_raddr_ff[6:2] == 5'hc; // @[pic_ctrl.scala 141:139] - wire _T_164 = raddr_intpriority_base_match & _T_163; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_12 = _T_164 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_166 = picm_raddr_ff[6:2] == 5'hd; // @[pic_ctrl.scala 141:139] - wire _T_167 = raddr_intpriority_base_match & _T_166; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_13 = _T_167 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_169 = picm_raddr_ff[6:2] == 5'he; // @[pic_ctrl.scala 141:139] - wire _T_170 = raddr_intpriority_base_match & _T_169; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_14 = _T_170 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_172 = picm_raddr_ff[6:2] == 5'hf; // @[pic_ctrl.scala 141:139] - wire _T_173 = raddr_intpriority_base_match & _T_172; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_15 = _T_173 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_175 = picm_raddr_ff[6:2] == 5'h10; // @[pic_ctrl.scala 141:139] - wire _T_176 = raddr_intpriority_base_match & _T_175; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_16 = _T_176 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_178 = picm_raddr_ff[6:2] == 5'h11; // @[pic_ctrl.scala 141:139] - wire _T_179 = raddr_intpriority_base_match & _T_178; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_17 = _T_179 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_181 = picm_raddr_ff[6:2] == 5'h12; // @[pic_ctrl.scala 141:139] - wire _T_182 = raddr_intpriority_base_match & _T_181; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_18 = _T_182 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_184 = picm_raddr_ff[6:2] == 5'h13; // @[pic_ctrl.scala 141:139] - wire _T_185 = raddr_intpriority_base_match & _T_184; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_19 = _T_185 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_187 = picm_raddr_ff[6:2] == 5'h14; // @[pic_ctrl.scala 141:139] - wire _T_188 = raddr_intpriority_base_match & _T_187; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_20 = _T_188 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_190 = picm_raddr_ff[6:2] == 5'h15; // @[pic_ctrl.scala 141:139] - wire _T_191 = raddr_intpriority_base_match & _T_190; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_21 = _T_191 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_193 = picm_raddr_ff[6:2] == 5'h16; // @[pic_ctrl.scala 141:139] - wire _T_194 = raddr_intpriority_base_match & _T_193; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_22 = _T_194 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_196 = picm_raddr_ff[6:2] == 5'h17; // @[pic_ctrl.scala 141:139] - wire _T_197 = raddr_intpriority_base_match & _T_196; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_23 = _T_197 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_199 = picm_raddr_ff[6:2] == 5'h18; // @[pic_ctrl.scala 141:139] - wire _T_200 = raddr_intpriority_base_match & _T_199; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_24 = _T_200 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_202 = picm_raddr_ff[6:2] == 5'h19; // @[pic_ctrl.scala 141:139] - wire _T_203 = raddr_intpriority_base_match & _T_202; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_25 = _T_203 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_205 = picm_raddr_ff[6:2] == 5'h1a; // @[pic_ctrl.scala 141:139] - wire _T_206 = raddr_intpriority_base_match & _T_205; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_26 = _T_206 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_208 = picm_raddr_ff[6:2] == 5'h1b; // @[pic_ctrl.scala 141:139] - wire _T_209 = raddr_intpriority_base_match & _T_208; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_27 = _T_209 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_211 = picm_raddr_ff[6:2] == 5'h1c; // @[pic_ctrl.scala 141:139] - wire _T_212 = raddr_intpriority_base_match & _T_211; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_28 = _T_212 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_214 = picm_raddr_ff[6:2] == 5'h1d; // @[pic_ctrl.scala 141:139] - wire _T_215 = raddr_intpriority_base_match & _T_214; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_29 = _T_215 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_217 = picm_raddr_ff[6:2] == 5'h1e; // @[pic_ctrl.scala 141:139] - wire _T_218 = raddr_intpriority_base_match & _T_217; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_30 = _T_218 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_220 = picm_raddr_ff[6:2] == 5'h1f; // @[pic_ctrl.scala 141:139] - wire _T_221 = raddr_intpriority_base_match & _T_220; // @[pic_ctrl.scala 141:106] - wire intpriority_reg_re_31 = _T_221 & picm_rden_ff; // @[pic_ctrl.scala 141:153] - wire _T_224 = waddr_intenable_base_match & _T_37; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_1 = _T_224 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_227 = waddr_intenable_base_match & _T_40; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_2 = _T_227 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_230 = waddr_intenable_base_match & _T_43; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_3 = _T_230 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_233 = waddr_intenable_base_match & _T_46; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_4 = _T_233 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_236 = waddr_intenable_base_match & _T_49; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_5 = _T_236 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_239 = waddr_intenable_base_match & _T_52; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_6 = _T_239 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_242 = waddr_intenable_base_match & _T_55; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_7 = _T_242 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_245 = waddr_intenable_base_match & _T_58; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_8 = _T_245 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_248 = waddr_intenable_base_match & _T_61; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_9 = _T_248 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_251 = waddr_intenable_base_match & _T_64; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_10 = _T_251 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_254 = waddr_intenable_base_match & _T_67; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_11 = _T_254 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_257 = waddr_intenable_base_match & _T_70; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_12 = _T_257 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_260 = waddr_intenable_base_match & _T_73; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_13 = _T_260 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_263 = waddr_intenable_base_match & _T_76; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_14 = _T_263 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_266 = waddr_intenable_base_match & _T_79; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_15 = _T_266 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_269 = waddr_intenable_base_match & _T_82; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_16 = _T_269 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_272 = waddr_intenable_base_match & _T_85; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_17 = _T_272 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_275 = waddr_intenable_base_match & _T_88; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_18 = _T_275 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_278 = waddr_intenable_base_match & _T_91; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_19 = _T_278 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_281 = waddr_intenable_base_match & _T_94; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_20 = _T_281 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_284 = waddr_intenable_base_match & _T_97; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_21 = _T_284 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_287 = waddr_intenable_base_match & _T_100; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_22 = _T_287 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_290 = waddr_intenable_base_match & _T_103; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_23 = _T_290 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_293 = waddr_intenable_base_match & _T_106; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_24 = _T_293 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_296 = waddr_intenable_base_match & _T_109; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_25 = _T_296 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_299 = waddr_intenable_base_match & _T_112; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_26 = _T_299 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_302 = waddr_intenable_base_match & _T_115; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_27 = _T_302 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_305 = waddr_intenable_base_match & _T_118; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_28 = _T_305 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_308 = waddr_intenable_base_match & _T_121; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_29 = _T_308 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_311 = waddr_intenable_base_match & _T_124; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_30 = _T_311 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_314 = waddr_intenable_base_match & _T_127; // @[pic_ctrl.scala 142:106] - wire intenable_reg_we_31 = _T_314 & picm_wren_ff; // @[pic_ctrl.scala 142:153] - wire _T_317 = raddr_intenable_base_match & _T_130; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_1 = _T_317 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_320 = raddr_intenable_base_match & _T_133; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_2 = _T_320 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_323 = raddr_intenable_base_match & _T_136; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_3 = _T_323 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_326 = raddr_intenable_base_match & _T_139; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_4 = _T_326 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_329 = raddr_intenable_base_match & _T_142; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_5 = _T_329 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_332 = raddr_intenable_base_match & _T_145; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_6 = _T_332 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_335 = raddr_intenable_base_match & _T_148; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_7 = _T_335 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_338 = raddr_intenable_base_match & _T_151; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_8 = _T_338 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_341 = raddr_intenable_base_match & _T_154; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_9 = _T_341 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_344 = raddr_intenable_base_match & _T_157; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_10 = _T_344 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_347 = raddr_intenable_base_match & _T_160; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_11 = _T_347 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_350 = raddr_intenable_base_match & _T_163; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_12 = _T_350 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_353 = raddr_intenable_base_match & _T_166; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_13 = _T_353 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_356 = raddr_intenable_base_match & _T_169; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_14 = _T_356 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_359 = raddr_intenable_base_match & _T_172; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_15 = _T_359 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_362 = raddr_intenable_base_match & _T_175; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_16 = _T_362 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_365 = raddr_intenable_base_match & _T_178; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_17 = _T_365 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_368 = raddr_intenable_base_match & _T_181; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_18 = _T_368 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_371 = raddr_intenable_base_match & _T_184; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_19 = _T_371 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_374 = raddr_intenable_base_match & _T_187; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_20 = _T_374 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_377 = raddr_intenable_base_match & _T_190; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_21 = _T_377 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_380 = raddr_intenable_base_match & _T_193; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_22 = _T_380 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_383 = raddr_intenable_base_match & _T_196; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_23 = _T_383 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_386 = raddr_intenable_base_match & _T_199; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_24 = _T_386 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_389 = raddr_intenable_base_match & _T_202; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_25 = _T_389 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_392 = raddr_intenable_base_match & _T_205; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_26 = _T_392 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_395 = raddr_intenable_base_match & _T_208; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_27 = _T_395 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_398 = raddr_intenable_base_match & _T_211; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_28 = _T_398 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_401 = raddr_intenable_base_match & _T_214; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_29 = _T_401 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_404 = raddr_intenable_base_match & _T_217; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_30 = _T_404 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_407 = raddr_intenable_base_match & _T_220; // @[pic_ctrl.scala 143:106] - wire intenable_reg_re_31 = _T_407 & picm_rden_ff; // @[pic_ctrl.scala 143:153] - wire _T_410 = waddr_config_gw_base_match & _T_37; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_1 = _T_410 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_413 = waddr_config_gw_base_match & _T_40; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_2 = _T_413 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_416 = waddr_config_gw_base_match & _T_43; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_3 = _T_416 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_419 = waddr_config_gw_base_match & _T_46; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_4 = _T_419 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_422 = waddr_config_gw_base_match & _T_49; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_5 = _T_422 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_425 = waddr_config_gw_base_match & _T_52; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_6 = _T_425 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_428 = waddr_config_gw_base_match & _T_55; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_7 = _T_428 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_431 = waddr_config_gw_base_match & _T_58; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_8 = _T_431 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_434 = waddr_config_gw_base_match & _T_61; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_9 = _T_434 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_437 = waddr_config_gw_base_match & _T_64; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_10 = _T_437 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_440 = waddr_config_gw_base_match & _T_67; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_11 = _T_440 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_443 = waddr_config_gw_base_match & _T_70; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_12 = _T_443 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_446 = waddr_config_gw_base_match & _T_73; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_13 = _T_446 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_449 = waddr_config_gw_base_match & _T_76; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_14 = _T_449 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_452 = waddr_config_gw_base_match & _T_79; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_15 = _T_452 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_455 = waddr_config_gw_base_match & _T_82; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_16 = _T_455 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_458 = waddr_config_gw_base_match & _T_85; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_17 = _T_458 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_461 = waddr_config_gw_base_match & _T_88; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_18 = _T_461 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_464 = waddr_config_gw_base_match & _T_91; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_19 = _T_464 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_467 = waddr_config_gw_base_match & _T_94; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_20 = _T_467 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_470 = waddr_config_gw_base_match & _T_97; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_21 = _T_470 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_473 = waddr_config_gw_base_match & _T_100; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_22 = _T_473 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_476 = waddr_config_gw_base_match & _T_103; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_23 = _T_476 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_479 = waddr_config_gw_base_match & _T_106; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_24 = _T_479 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_482 = waddr_config_gw_base_match & _T_109; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_25 = _T_482 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_485 = waddr_config_gw_base_match & _T_112; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_26 = _T_485 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_488 = waddr_config_gw_base_match & _T_115; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_27 = _T_488 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_491 = waddr_config_gw_base_match & _T_118; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_28 = _T_491 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_494 = waddr_config_gw_base_match & _T_121; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_29 = _T_494 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_497 = waddr_config_gw_base_match & _T_124; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_30 = _T_497 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_500 = waddr_config_gw_base_match & _T_127; // @[pic_ctrl.scala 144:106] - wire gw_config_reg_we_31 = _T_500 & picm_wren_ff; // @[pic_ctrl.scala 144:153] - wire _T_503 = raddr_config_gw_base_match & _T_130; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_1 = _T_503 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_506 = raddr_config_gw_base_match & _T_133; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_2 = _T_506 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_509 = raddr_config_gw_base_match & _T_136; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_3 = _T_509 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_512 = raddr_config_gw_base_match & _T_139; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_4 = _T_512 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_515 = raddr_config_gw_base_match & _T_142; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_5 = _T_515 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_518 = raddr_config_gw_base_match & _T_145; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_6 = _T_518 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_521 = raddr_config_gw_base_match & _T_148; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_7 = _T_521 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_524 = raddr_config_gw_base_match & _T_151; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_8 = _T_524 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_527 = raddr_config_gw_base_match & _T_154; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_9 = _T_527 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_530 = raddr_config_gw_base_match & _T_157; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_10 = _T_530 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_533 = raddr_config_gw_base_match & _T_160; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_11 = _T_533 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_536 = raddr_config_gw_base_match & _T_163; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_12 = _T_536 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_539 = raddr_config_gw_base_match & _T_166; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_13 = _T_539 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_542 = raddr_config_gw_base_match & _T_169; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_14 = _T_542 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_545 = raddr_config_gw_base_match & _T_172; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_15 = _T_545 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_548 = raddr_config_gw_base_match & _T_175; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_16 = _T_548 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_551 = raddr_config_gw_base_match & _T_178; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_17 = _T_551 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_554 = raddr_config_gw_base_match & _T_181; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_18 = _T_554 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_557 = raddr_config_gw_base_match & _T_184; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_19 = _T_557 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_560 = raddr_config_gw_base_match & _T_187; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_20 = _T_560 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_563 = raddr_config_gw_base_match & _T_190; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_21 = _T_563 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_566 = raddr_config_gw_base_match & _T_193; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_22 = _T_566 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_569 = raddr_config_gw_base_match & _T_196; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_23 = _T_569 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_572 = raddr_config_gw_base_match & _T_199; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_24 = _T_572 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_575 = raddr_config_gw_base_match & _T_202; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_25 = _T_575 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_578 = raddr_config_gw_base_match & _T_205; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_26 = _T_578 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_581 = raddr_config_gw_base_match & _T_208; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_27 = _T_581 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_584 = raddr_config_gw_base_match & _T_211; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_28 = _T_584 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_587 = raddr_config_gw_base_match & _T_214; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_29 = _T_587 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_590 = raddr_config_gw_base_match & _T_217; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_30 = _T_590 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_593 = raddr_config_gw_base_match & _T_220; // @[pic_ctrl.scala 145:106] - wire gw_config_reg_re_31 = _T_593 & picm_rden_ff; // @[pic_ctrl.scala 145:153] - wire _T_596 = addr_clear_gw_base_match & _T_37; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_1 = _T_596 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_599 = addr_clear_gw_base_match & _T_40; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_2 = _T_599 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_602 = addr_clear_gw_base_match & _T_43; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_3 = _T_602 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_605 = addr_clear_gw_base_match & _T_46; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_4 = _T_605 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_608 = addr_clear_gw_base_match & _T_49; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_5 = _T_608 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_611 = addr_clear_gw_base_match & _T_52; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_6 = _T_611 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_614 = addr_clear_gw_base_match & _T_55; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_7 = _T_614 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_617 = addr_clear_gw_base_match & _T_58; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_8 = _T_617 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_620 = addr_clear_gw_base_match & _T_61; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_9 = _T_620 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_623 = addr_clear_gw_base_match & _T_64; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_10 = _T_623 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_626 = addr_clear_gw_base_match & _T_67; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_11 = _T_626 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_629 = addr_clear_gw_base_match & _T_70; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_12 = _T_629 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_632 = addr_clear_gw_base_match & _T_73; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_13 = _T_632 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_635 = addr_clear_gw_base_match & _T_76; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_14 = _T_635 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_638 = addr_clear_gw_base_match & _T_79; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_15 = _T_638 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_641 = addr_clear_gw_base_match & _T_82; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_16 = _T_641 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_644 = addr_clear_gw_base_match & _T_85; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_17 = _T_644 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_647 = addr_clear_gw_base_match & _T_88; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_18 = _T_647 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_650 = addr_clear_gw_base_match & _T_91; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_19 = _T_650 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_653 = addr_clear_gw_base_match & _T_94; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_20 = _T_653 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_656 = addr_clear_gw_base_match & _T_97; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_21 = _T_656 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_659 = addr_clear_gw_base_match & _T_100; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_22 = _T_659 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_662 = addr_clear_gw_base_match & _T_103; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_23 = _T_662 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_665 = addr_clear_gw_base_match & _T_106; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_24 = _T_665 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_668 = addr_clear_gw_base_match & _T_109; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_25 = _T_668 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_671 = addr_clear_gw_base_match & _T_112; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_26 = _T_671 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_674 = addr_clear_gw_base_match & _T_115; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_27 = _T_674 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_677 = addr_clear_gw_base_match & _T_118; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_28 = _T_677 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_680 = addr_clear_gw_base_match & _T_121; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_29 = _T_680 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_683 = addr_clear_gw_base_match & _T_124; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_30 = _T_683 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire _T_686 = addr_clear_gw_base_match & _T_127; // @[pic_ctrl.scala 146:106] - wire gw_clear_reg_we_31 = _T_686 & picm_wren_ff; // @[pic_ctrl.scala 146:153] - wire pic_pri_c1_clk = rvclkhdr_2_io_l1clk; // @[pic_ctrl.scala 96:42 pic_ctrl.scala 133:21] + wire _T_37 = picm_waddr_ff[6:2] == 5'h1; // @[pic_ctrl.scala 141:139] + wire _T_38 = waddr_intpriority_base_match & _T_37; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_1 = _T_38 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_40 = picm_waddr_ff[6:2] == 5'h2; // @[pic_ctrl.scala 141:139] + wire _T_41 = waddr_intpriority_base_match & _T_40; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_2 = _T_41 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_43 = picm_waddr_ff[6:2] == 5'h3; // @[pic_ctrl.scala 141:139] + wire _T_44 = waddr_intpriority_base_match & _T_43; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_3 = _T_44 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_46 = picm_waddr_ff[6:2] == 5'h4; // @[pic_ctrl.scala 141:139] + wire _T_47 = waddr_intpriority_base_match & _T_46; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_4 = _T_47 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_49 = picm_waddr_ff[6:2] == 5'h5; // @[pic_ctrl.scala 141:139] + wire _T_50 = waddr_intpriority_base_match & _T_49; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_5 = _T_50 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_52 = picm_waddr_ff[6:2] == 5'h6; // @[pic_ctrl.scala 141:139] + wire _T_53 = waddr_intpriority_base_match & _T_52; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_6 = _T_53 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_55 = picm_waddr_ff[6:2] == 5'h7; // @[pic_ctrl.scala 141:139] + wire _T_56 = waddr_intpriority_base_match & _T_55; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_7 = _T_56 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_58 = picm_waddr_ff[6:2] == 5'h8; // @[pic_ctrl.scala 141:139] + wire _T_59 = waddr_intpriority_base_match & _T_58; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_8 = _T_59 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_61 = picm_waddr_ff[6:2] == 5'h9; // @[pic_ctrl.scala 141:139] + wire _T_62 = waddr_intpriority_base_match & _T_61; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_9 = _T_62 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_64 = picm_waddr_ff[6:2] == 5'ha; // @[pic_ctrl.scala 141:139] + wire _T_65 = waddr_intpriority_base_match & _T_64; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_10 = _T_65 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_67 = picm_waddr_ff[6:2] == 5'hb; // @[pic_ctrl.scala 141:139] + wire _T_68 = waddr_intpriority_base_match & _T_67; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_11 = _T_68 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_70 = picm_waddr_ff[6:2] == 5'hc; // @[pic_ctrl.scala 141:139] + wire _T_71 = waddr_intpriority_base_match & _T_70; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_12 = _T_71 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_73 = picm_waddr_ff[6:2] == 5'hd; // @[pic_ctrl.scala 141:139] + wire _T_74 = waddr_intpriority_base_match & _T_73; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_13 = _T_74 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_76 = picm_waddr_ff[6:2] == 5'he; // @[pic_ctrl.scala 141:139] + wire _T_77 = waddr_intpriority_base_match & _T_76; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_14 = _T_77 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_79 = picm_waddr_ff[6:2] == 5'hf; // @[pic_ctrl.scala 141:139] + wire _T_80 = waddr_intpriority_base_match & _T_79; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_15 = _T_80 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_82 = picm_waddr_ff[6:2] == 5'h10; // @[pic_ctrl.scala 141:139] + wire _T_83 = waddr_intpriority_base_match & _T_82; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_16 = _T_83 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_85 = picm_waddr_ff[6:2] == 5'h11; // @[pic_ctrl.scala 141:139] + wire _T_86 = waddr_intpriority_base_match & _T_85; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_17 = _T_86 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_88 = picm_waddr_ff[6:2] == 5'h12; // @[pic_ctrl.scala 141:139] + wire _T_89 = waddr_intpriority_base_match & _T_88; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_18 = _T_89 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_91 = picm_waddr_ff[6:2] == 5'h13; // @[pic_ctrl.scala 141:139] + wire _T_92 = waddr_intpriority_base_match & _T_91; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_19 = _T_92 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_94 = picm_waddr_ff[6:2] == 5'h14; // @[pic_ctrl.scala 141:139] + wire _T_95 = waddr_intpriority_base_match & _T_94; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_20 = _T_95 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_97 = picm_waddr_ff[6:2] == 5'h15; // @[pic_ctrl.scala 141:139] + wire _T_98 = waddr_intpriority_base_match & _T_97; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_21 = _T_98 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_100 = picm_waddr_ff[6:2] == 5'h16; // @[pic_ctrl.scala 141:139] + wire _T_101 = waddr_intpriority_base_match & _T_100; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_22 = _T_101 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_103 = picm_waddr_ff[6:2] == 5'h17; // @[pic_ctrl.scala 141:139] + wire _T_104 = waddr_intpriority_base_match & _T_103; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_23 = _T_104 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_106 = picm_waddr_ff[6:2] == 5'h18; // @[pic_ctrl.scala 141:139] + wire _T_107 = waddr_intpriority_base_match & _T_106; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_24 = _T_107 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_109 = picm_waddr_ff[6:2] == 5'h19; // @[pic_ctrl.scala 141:139] + wire _T_110 = waddr_intpriority_base_match & _T_109; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_25 = _T_110 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_112 = picm_waddr_ff[6:2] == 5'h1a; // @[pic_ctrl.scala 141:139] + wire _T_113 = waddr_intpriority_base_match & _T_112; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_26 = _T_113 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_115 = picm_waddr_ff[6:2] == 5'h1b; // @[pic_ctrl.scala 141:139] + wire _T_116 = waddr_intpriority_base_match & _T_115; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_27 = _T_116 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_118 = picm_waddr_ff[6:2] == 5'h1c; // @[pic_ctrl.scala 141:139] + wire _T_119 = waddr_intpriority_base_match & _T_118; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_28 = _T_119 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_121 = picm_waddr_ff[6:2] == 5'h1d; // @[pic_ctrl.scala 141:139] + wire _T_122 = waddr_intpriority_base_match & _T_121; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_29 = _T_122 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_124 = picm_waddr_ff[6:2] == 5'h1e; // @[pic_ctrl.scala 141:139] + wire _T_125 = waddr_intpriority_base_match & _T_124; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_30 = _T_125 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_127 = picm_waddr_ff[6:2] == 5'h1f; // @[pic_ctrl.scala 141:139] + wire _T_128 = waddr_intpriority_base_match & _T_127; // @[pic_ctrl.scala 141:106] + wire intpriority_reg_we_31 = _T_128 & picm_wren_ff; // @[pic_ctrl.scala 141:153] + wire _T_130 = picm_raddr_ff[6:2] == 5'h1; // @[pic_ctrl.scala 142:139] + wire _T_131 = raddr_intpriority_base_match & _T_130; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_1 = _T_131 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_133 = picm_raddr_ff[6:2] == 5'h2; // @[pic_ctrl.scala 142:139] + wire _T_134 = raddr_intpriority_base_match & _T_133; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_2 = _T_134 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_136 = picm_raddr_ff[6:2] == 5'h3; // @[pic_ctrl.scala 142:139] + wire _T_137 = raddr_intpriority_base_match & _T_136; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_3 = _T_137 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_139 = picm_raddr_ff[6:2] == 5'h4; // @[pic_ctrl.scala 142:139] + wire _T_140 = raddr_intpriority_base_match & _T_139; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_4 = _T_140 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_142 = picm_raddr_ff[6:2] == 5'h5; // @[pic_ctrl.scala 142:139] + wire _T_143 = raddr_intpriority_base_match & _T_142; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_5 = _T_143 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_145 = picm_raddr_ff[6:2] == 5'h6; // @[pic_ctrl.scala 142:139] + wire _T_146 = raddr_intpriority_base_match & _T_145; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_6 = _T_146 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_148 = picm_raddr_ff[6:2] == 5'h7; // @[pic_ctrl.scala 142:139] + wire _T_149 = raddr_intpriority_base_match & _T_148; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_7 = _T_149 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_151 = picm_raddr_ff[6:2] == 5'h8; // @[pic_ctrl.scala 142:139] + wire _T_152 = raddr_intpriority_base_match & _T_151; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_8 = _T_152 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_154 = picm_raddr_ff[6:2] == 5'h9; // @[pic_ctrl.scala 142:139] + wire _T_155 = raddr_intpriority_base_match & _T_154; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_9 = _T_155 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_157 = picm_raddr_ff[6:2] == 5'ha; // @[pic_ctrl.scala 142:139] + wire _T_158 = raddr_intpriority_base_match & _T_157; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_10 = _T_158 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_160 = picm_raddr_ff[6:2] == 5'hb; // @[pic_ctrl.scala 142:139] + wire _T_161 = raddr_intpriority_base_match & _T_160; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_11 = _T_161 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_163 = picm_raddr_ff[6:2] == 5'hc; // @[pic_ctrl.scala 142:139] + wire _T_164 = raddr_intpriority_base_match & _T_163; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_12 = _T_164 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_166 = picm_raddr_ff[6:2] == 5'hd; // @[pic_ctrl.scala 142:139] + wire _T_167 = raddr_intpriority_base_match & _T_166; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_13 = _T_167 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_169 = picm_raddr_ff[6:2] == 5'he; // @[pic_ctrl.scala 142:139] + wire _T_170 = raddr_intpriority_base_match & _T_169; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_14 = _T_170 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_172 = picm_raddr_ff[6:2] == 5'hf; // @[pic_ctrl.scala 142:139] + wire _T_173 = raddr_intpriority_base_match & _T_172; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_15 = _T_173 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_175 = picm_raddr_ff[6:2] == 5'h10; // @[pic_ctrl.scala 142:139] + wire _T_176 = raddr_intpriority_base_match & _T_175; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_16 = _T_176 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_178 = picm_raddr_ff[6:2] == 5'h11; // @[pic_ctrl.scala 142:139] + wire _T_179 = raddr_intpriority_base_match & _T_178; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_17 = _T_179 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_181 = picm_raddr_ff[6:2] == 5'h12; // @[pic_ctrl.scala 142:139] + wire _T_182 = raddr_intpriority_base_match & _T_181; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_18 = _T_182 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_184 = picm_raddr_ff[6:2] == 5'h13; // @[pic_ctrl.scala 142:139] + wire _T_185 = raddr_intpriority_base_match & _T_184; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_19 = _T_185 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_187 = picm_raddr_ff[6:2] == 5'h14; // @[pic_ctrl.scala 142:139] + wire _T_188 = raddr_intpriority_base_match & _T_187; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_20 = _T_188 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_190 = picm_raddr_ff[6:2] == 5'h15; // @[pic_ctrl.scala 142:139] + wire _T_191 = raddr_intpriority_base_match & _T_190; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_21 = _T_191 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_193 = picm_raddr_ff[6:2] == 5'h16; // @[pic_ctrl.scala 142:139] + wire _T_194 = raddr_intpriority_base_match & _T_193; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_22 = _T_194 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_196 = picm_raddr_ff[6:2] == 5'h17; // @[pic_ctrl.scala 142:139] + wire _T_197 = raddr_intpriority_base_match & _T_196; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_23 = _T_197 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_199 = picm_raddr_ff[6:2] == 5'h18; // @[pic_ctrl.scala 142:139] + wire _T_200 = raddr_intpriority_base_match & _T_199; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_24 = _T_200 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_202 = picm_raddr_ff[6:2] == 5'h19; // @[pic_ctrl.scala 142:139] + wire _T_203 = raddr_intpriority_base_match & _T_202; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_25 = _T_203 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_205 = picm_raddr_ff[6:2] == 5'h1a; // @[pic_ctrl.scala 142:139] + wire _T_206 = raddr_intpriority_base_match & _T_205; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_26 = _T_206 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_208 = picm_raddr_ff[6:2] == 5'h1b; // @[pic_ctrl.scala 142:139] + wire _T_209 = raddr_intpriority_base_match & _T_208; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_27 = _T_209 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_211 = picm_raddr_ff[6:2] == 5'h1c; // @[pic_ctrl.scala 142:139] + wire _T_212 = raddr_intpriority_base_match & _T_211; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_28 = _T_212 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_214 = picm_raddr_ff[6:2] == 5'h1d; // @[pic_ctrl.scala 142:139] + wire _T_215 = raddr_intpriority_base_match & _T_214; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_29 = _T_215 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_217 = picm_raddr_ff[6:2] == 5'h1e; // @[pic_ctrl.scala 142:139] + wire _T_218 = raddr_intpriority_base_match & _T_217; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_30 = _T_218 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_220 = picm_raddr_ff[6:2] == 5'h1f; // @[pic_ctrl.scala 142:139] + wire _T_221 = raddr_intpriority_base_match & _T_220; // @[pic_ctrl.scala 142:106] + wire intpriority_reg_re_31 = _T_221 & picm_rden_ff; // @[pic_ctrl.scala 142:153] + wire _T_224 = waddr_intenable_base_match & _T_37; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_1 = _T_224 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_227 = waddr_intenable_base_match & _T_40; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_2 = _T_227 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_230 = waddr_intenable_base_match & _T_43; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_3 = _T_230 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_233 = waddr_intenable_base_match & _T_46; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_4 = _T_233 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_236 = waddr_intenable_base_match & _T_49; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_5 = _T_236 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_239 = waddr_intenable_base_match & _T_52; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_6 = _T_239 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_242 = waddr_intenable_base_match & _T_55; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_7 = _T_242 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_245 = waddr_intenable_base_match & _T_58; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_8 = _T_245 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_248 = waddr_intenable_base_match & _T_61; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_9 = _T_248 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_251 = waddr_intenable_base_match & _T_64; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_10 = _T_251 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_254 = waddr_intenable_base_match & _T_67; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_11 = _T_254 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_257 = waddr_intenable_base_match & _T_70; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_12 = _T_257 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_260 = waddr_intenable_base_match & _T_73; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_13 = _T_260 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_263 = waddr_intenable_base_match & _T_76; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_14 = _T_263 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_266 = waddr_intenable_base_match & _T_79; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_15 = _T_266 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_269 = waddr_intenable_base_match & _T_82; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_16 = _T_269 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_272 = waddr_intenable_base_match & _T_85; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_17 = _T_272 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_275 = waddr_intenable_base_match & _T_88; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_18 = _T_275 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_278 = waddr_intenable_base_match & _T_91; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_19 = _T_278 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_281 = waddr_intenable_base_match & _T_94; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_20 = _T_281 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_284 = waddr_intenable_base_match & _T_97; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_21 = _T_284 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_287 = waddr_intenable_base_match & _T_100; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_22 = _T_287 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_290 = waddr_intenable_base_match & _T_103; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_23 = _T_290 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_293 = waddr_intenable_base_match & _T_106; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_24 = _T_293 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_296 = waddr_intenable_base_match & _T_109; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_25 = _T_296 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_299 = waddr_intenable_base_match & _T_112; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_26 = _T_299 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_302 = waddr_intenable_base_match & _T_115; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_27 = _T_302 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_305 = waddr_intenable_base_match & _T_118; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_28 = _T_305 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_308 = waddr_intenable_base_match & _T_121; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_29 = _T_308 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_311 = waddr_intenable_base_match & _T_124; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_30 = _T_311 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_314 = waddr_intenable_base_match & _T_127; // @[pic_ctrl.scala 143:106] + wire intenable_reg_we_31 = _T_314 & picm_wren_ff; // @[pic_ctrl.scala 143:153] + wire _T_317 = raddr_intenable_base_match & _T_130; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_1 = _T_317 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_320 = raddr_intenable_base_match & _T_133; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_2 = _T_320 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_323 = raddr_intenable_base_match & _T_136; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_3 = _T_323 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_326 = raddr_intenable_base_match & _T_139; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_4 = _T_326 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_329 = raddr_intenable_base_match & _T_142; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_5 = _T_329 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_332 = raddr_intenable_base_match & _T_145; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_6 = _T_332 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_335 = raddr_intenable_base_match & _T_148; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_7 = _T_335 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_338 = raddr_intenable_base_match & _T_151; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_8 = _T_338 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_341 = raddr_intenable_base_match & _T_154; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_9 = _T_341 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_344 = raddr_intenable_base_match & _T_157; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_10 = _T_344 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_347 = raddr_intenable_base_match & _T_160; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_11 = _T_347 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_350 = raddr_intenable_base_match & _T_163; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_12 = _T_350 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_353 = raddr_intenable_base_match & _T_166; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_13 = _T_353 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_356 = raddr_intenable_base_match & _T_169; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_14 = _T_356 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_359 = raddr_intenable_base_match & _T_172; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_15 = _T_359 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_362 = raddr_intenable_base_match & _T_175; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_16 = _T_362 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_365 = raddr_intenable_base_match & _T_178; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_17 = _T_365 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_368 = raddr_intenable_base_match & _T_181; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_18 = _T_368 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_371 = raddr_intenable_base_match & _T_184; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_19 = _T_371 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_374 = raddr_intenable_base_match & _T_187; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_20 = _T_374 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_377 = raddr_intenable_base_match & _T_190; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_21 = _T_377 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_380 = raddr_intenable_base_match & _T_193; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_22 = _T_380 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_383 = raddr_intenable_base_match & _T_196; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_23 = _T_383 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_386 = raddr_intenable_base_match & _T_199; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_24 = _T_386 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_389 = raddr_intenable_base_match & _T_202; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_25 = _T_389 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_392 = raddr_intenable_base_match & _T_205; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_26 = _T_392 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_395 = raddr_intenable_base_match & _T_208; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_27 = _T_395 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_398 = raddr_intenable_base_match & _T_211; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_28 = _T_398 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_401 = raddr_intenable_base_match & _T_214; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_29 = _T_401 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_404 = raddr_intenable_base_match & _T_217; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_30 = _T_404 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_407 = raddr_intenable_base_match & _T_220; // @[pic_ctrl.scala 144:106] + wire intenable_reg_re_31 = _T_407 & picm_rden_ff; // @[pic_ctrl.scala 144:153] + wire _T_410 = waddr_config_gw_base_match & _T_37; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_1 = _T_410 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_413 = waddr_config_gw_base_match & _T_40; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_2 = _T_413 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_416 = waddr_config_gw_base_match & _T_43; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_3 = _T_416 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_419 = waddr_config_gw_base_match & _T_46; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_4 = _T_419 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_422 = waddr_config_gw_base_match & _T_49; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_5 = _T_422 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_425 = waddr_config_gw_base_match & _T_52; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_6 = _T_425 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_428 = waddr_config_gw_base_match & _T_55; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_7 = _T_428 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_431 = waddr_config_gw_base_match & _T_58; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_8 = _T_431 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_434 = waddr_config_gw_base_match & _T_61; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_9 = _T_434 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_437 = waddr_config_gw_base_match & _T_64; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_10 = _T_437 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_440 = waddr_config_gw_base_match & _T_67; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_11 = _T_440 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_443 = waddr_config_gw_base_match & _T_70; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_12 = _T_443 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_446 = waddr_config_gw_base_match & _T_73; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_13 = _T_446 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_449 = waddr_config_gw_base_match & _T_76; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_14 = _T_449 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_452 = waddr_config_gw_base_match & _T_79; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_15 = _T_452 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_455 = waddr_config_gw_base_match & _T_82; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_16 = _T_455 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_458 = waddr_config_gw_base_match & _T_85; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_17 = _T_458 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_461 = waddr_config_gw_base_match & _T_88; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_18 = _T_461 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_464 = waddr_config_gw_base_match & _T_91; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_19 = _T_464 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_467 = waddr_config_gw_base_match & _T_94; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_20 = _T_467 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_470 = waddr_config_gw_base_match & _T_97; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_21 = _T_470 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_473 = waddr_config_gw_base_match & _T_100; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_22 = _T_473 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_476 = waddr_config_gw_base_match & _T_103; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_23 = _T_476 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_479 = waddr_config_gw_base_match & _T_106; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_24 = _T_479 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_482 = waddr_config_gw_base_match & _T_109; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_25 = _T_482 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_485 = waddr_config_gw_base_match & _T_112; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_26 = _T_485 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_488 = waddr_config_gw_base_match & _T_115; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_27 = _T_488 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_491 = waddr_config_gw_base_match & _T_118; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_28 = _T_491 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_494 = waddr_config_gw_base_match & _T_121; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_29 = _T_494 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_497 = waddr_config_gw_base_match & _T_124; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_30 = _T_497 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_500 = waddr_config_gw_base_match & _T_127; // @[pic_ctrl.scala 145:106] + wire gw_config_reg_we_31 = _T_500 & picm_wren_ff; // @[pic_ctrl.scala 145:153] + wire _T_503 = raddr_config_gw_base_match & _T_130; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_1 = _T_503 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_506 = raddr_config_gw_base_match & _T_133; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_2 = _T_506 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_509 = raddr_config_gw_base_match & _T_136; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_3 = _T_509 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_512 = raddr_config_gw_base_match & _T_139; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_4 = _T_512 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_515 = raddr_config_gw_base_match & _T_142; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_5 = _T_515 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_518 = raddr_config_gw_base_match & _T_145; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_6 = _T_518 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_521 = raddr_config_gw_base_match & _T_148; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_7 = _T_521 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_524 = raddr_config_gw_base_match & _T_151; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_8 = _T_524 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_527 = raddr_config_gw_base_match & _T_154; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_9 = _T_527 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_530 = raddr_config_gw_base_match & _T_157; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_10 = _T_530 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_533 = raddr_config_gw_base_match & _T_160; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_11 = _T_533 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_536 = raddr_config_gw_base_match & _T_163; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_12 = _T_536 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_539 = raddr_config_gw_base_match & _T_166; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_13 = _T_539 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_542 = raddr_config_gw_base_match & _T_169; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_14 = _T_542 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_545 = raddr_config_gw_base_match & _T_172; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_15 = _T_545 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_548 = raddr_config_gw_base_match & _T_175; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_16 = _T_548 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_551 = raddr_config_gw_base_match & _T_178; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_17 = _T_551 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_554 = raddr_config_gw_base_match & _T_181; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_18 = _T_554 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_557 = raddr_config_gw_base_match & _T_184; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_19 = _T_557 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_560 = raddr_config_gw_base_match & _T_187; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_20 = _T_560 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_563 = raddr_config_gw_base_match & _T_190; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_21 = _T_563 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_566 = raddr_config_gw_base_match & _T_193; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_22 = _T_566 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_569 = raddr_config_gw_base_match & _T_196; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_23 = _T_569 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_572 = raddr_config_gw_base_match & _T_199; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_24 = _T_572 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_575 = raddr_config_gw_base_match & _T_202; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_25 = _T_575 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_578 = raddr_config_gw_base_match & _T_205; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_26 = _T_578 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_581 = raddr_config_gw_base_match & _T_208; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_27 = _T_581 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_584 = raddr_config_gw_base_match & _T_211; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_28 = _T_584 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_587 = raddr_config_gw_base_match & _T_214; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_29 = _T_587 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_590 = raddr_config_gw_base_match & _T_217; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_30 = _T_590 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_593 = raddr_config_gw_base_match & _T_220; // @[pic_ctrl.scala 146:106] + wire gw_config_reg_re_31 = _T_593 & picm_rden_ff; // @[pic_ctrl.scala 146:153] + wire _T_596 = addr_clear_gw_base_match & _T_37; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_1 = _T_596 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_599 = addr_clear_gw_base_match & _T_40; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_2 = _T_599 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_602 = addr_clear_gw_base_match & _T_43; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_3 = _T_602 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_605 = addr_clear_gw_base_match & _T_46; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_4 = _T_605 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_608 = addr_clear_gw_base_match & _T_49; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_5 = _T_608 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_611 = addr_clear_gw_base_match & _T_52; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_6 = _T_611 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_614 = addr_clear_gw_base_match & _T_55; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_7 = _T_614 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_617 = addr_clear_gw_base_match & _T_58; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_8 = _T_617 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_620 = addr_clear_gw_base_match & _T_61; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_9 = _T_620 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_623 = addr_clear_gw_base_match & _T_64; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_10 = _T_623 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_626 = addr_clear_gw_base_match & _T_67; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_11 = _T_626 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_629 = addr_clear_gw_base_match & _T_70; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_12 = _T_629 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_632 = addr_clear_gw_base_match & _T_73; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_13 = _T_632 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_635 = addr_clear_gw_base_match & _T_76; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_14 = _T_635 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_638 = addr_clear_gw_base_match & _T_79; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_15 = _T_638 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_641 = addr_clear_gw_base_match & _T_82; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_16 = _T_641 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_644 = addr_clear_gw_base_match & _T_85; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_17 = _T_644 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_647 = addr_clear_gw_base_match & _T_88; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_18 = _T_647 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_650 = addr_clear_gw_base_match & _T_91; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_19 = _T_650 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_653 = addr_clear_gw_base_match & _T_94; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_20 = _T_653 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_656 = addr_clear_gw_base_match & _T_97; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_21 = _T_656 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_659 = addr_clear_gw_base_match & _T_100; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_22 = _T_659 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_662 = addr_clear_gw_base_match & _T_103; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_23 = _T_662 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_665 = addr_clear_gw_base_match & _T_106; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_24 = _T_665 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_668 = addr_clear_gw_base_match & _T_109; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_25 = _T_668 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_671 = addr_clear_gw_base_match & _T_112; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_26 = _T_671 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_674 = addr_clear_gw_base_match & _T_115; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_27 = _T_674 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_677 = addr_clear_gw_base_match & _T_118; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_28 = _T_677 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_680 = addr_clear_gw_base_match & _T_121; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_29 = _T_680 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_683 = addr_clear_gw_base_match & _T_124; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_30 = _T_683 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire _T_686 = addr_clear_gw_base_match & _T_127; // @[pic_ctrl.scala 147:106] + wire gw_clear_reg_we_31 = _T_686 & picm_wren_ff; // @[pic_ctrl.scala 147:153] + wire pic_pri_c1_clk = rvclkhdr_2_io_l1clk; // @[pic_ctrl.scala 97:42 pic_ctrl.scala 134:21] reg [3:0] intpriority_reg_1; // @[Reg.scala 27:20] reg [3:0] intpriority_reg_2; // @[Reg.scala 27:20] reg [3:0] intpriority_reg_3; // @[Reg.scala 27:20] @@ -75401,7 +75256,7 @@ module pic_ctrl( reg [3:0] intpriority_reg_29; // @[Reg.scala 27:20] reg [3:0] intpriority_reg_30; // @[Reg.scala 27:20] reg [3:0] intpriority_reg_31; // @[Reg.scala 27:20] - wire pic_int_c1_clk = rvclkhdr_3_io_l1clk; // @[pic_ctrl.scala 97:42 pic_ctrl.scala 134:21] + wire pic_int_c1_clk = rvclkhdr_3_io_l1clk; // @[pic_ctrl.scala 98:42 pic_ctrl.scala 135:21] reg intenable_reg_1; // @[Reg.scala 27:20] reg intenable_reg_2; // @[Reg.scala 27:20] reg intenable_reg_3; // @[Reg.scala 27:20] @@ -75433,7 +75288,7 @@ module pic_ctrl( reg intenable_reg_29; // @[Reg.scala 27:20] reg intenable_reg_30; // @[Reg.scala 27:20] reg intenable_reg_31; // @[Reg.scala 27:20] - wire gw_config_c1_clk = rvclkhdr_4_io_l1clk; // @[pic_ctrl.scala 98:42 pic_ctrl.scala 135:21] + wire gw_config_c1_clk = rvclkhdr_4_io_l1clk; // @[pic_ctrl.scala 99:42 pic_ctrl.scala 136:21] reg [1:0] gw_config_reg_1; // @[Reg.scala 27:20] reg [1:0] gw_config_reg_2; // @[Reg.scala 27:20] reg [1:0] gw_config_reg_3; // @[Reg.scala 27:20] @@ -75465,648 +75320,648 @@ module pic_ctrl( reg [1:0] gw_config_reg_29; // @[Reg.scala 27:20] reg [1:0] gw_config_reg_30; // @[Reg.scala 27:20] reg [1:0] gw_config_reg_31; // @[Reg.scala 27:20] - wire _T_970 = extintsrc_req_sync[1] ^ gw_config_reg_1[0]; // @[pic_ctrl.scala 30:50] - wire _T_971 = ~gw_clear_reg_we_1; // @[pic_ctrl.scala 30:92] - reg gw_int_pending; // @[pic_ctrl.scala 31:45] - wire _T_972 = gw_int_pending & _T_971; // @[pic_ctrl.scala 30:90] - wire _T_976 = _T_970 | gw_int_pending; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_1 = gw_config_reg_1[1] ? _T_976 : _T_970; // @[pic_ctrl.scala 32:8] - wire _T_982 = extintsrc_req_sync[2] ^ gw_config_reg_2[0]; // @[pic_ctrl.scala 30:50] - wire _T_983 = ~gw_clear_reg_we_2; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_1; // @[pic_ctrl.scala 31:45] - wire _T_984 = gw_int_pending_1 & _T_983; // @[pic_ctrl.scala 30:90] - wire _T_988 = _T_982 | gw_int_pending_1; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_2 = gw_config_reg_2[1] ? _T_988 : _T_982; // @[pic_ctrl.scala 32:8] - wire _T_994 = extintsrc_req_sync[3] ^ gw_config_reg_3[0]; // @[pic_ctrl.scala 30:50] - wire _T_995 = ~gw_clear_reg_we_3; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_2; // @[pic_ctrl.scala 31:45] - wire _T_996 = gw_int_pending_2 & _T_995; // @[pic_ctrl.scala 30:90] - wire _T_1000 = _T_994 | gw_int_pending_2; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_3 = gw_config_reg_3[1] ? _T_1000 : _T_994; // @[pic_ctrl.scala 32:8] - wire _T_1006 = extintsrc_req_sync[4] ^ gw_config_reg_4[0]; // @[pic_ctrl.scala 30:50] - wire _T_1007 = ~gw_clear_reg_we_4; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_3; // @[pic_ctrl.scala 31:45] - wire _T_1008 = gw_int_pending_3 & _T_1007; // @[pic_ctrl.scala 30:90] - wire _T_1012 = _T_1006 | gw_int_pending_3; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_4 = gw_config_reg_4[1] ? _T_1012 : _T_1006; // @[pic_ctrl.scala 32:8] - wire _T_1018 = extintsrc_req_sync[5] ^ gw_config_reg_5[0]; // @[pic_ctrl.scala 30:50] - wire _T_1019 = ~gw_clear_reg_we_5; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_4; // @[pic_ctrl.scala 31:45] - wire _T_1020 = gw_int_pending_4 & _T_1019; // @[pic_ctrl.scala 30:90] - wire _T_1024 = _T_1018 | gw_int_pending_4; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_5 = gw_config_reg_5[1] ? _T_1024 : _T_1018; // @[pic_ctrl.scala 32:8] - wire _T_1030 = extintsrc_req_sync[6] ^ gw_config_reg_6[0]; // @[pic_ctrl.scala 30:50] - wire _T_1031 = ~gw_clear_reg_we_6; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_5; // @[pic_ctrl.scala 31:45] - wire _T_1032 = gw_int_pending_5 & _T_1031; // @[pic_ctrl.scala 30:90] - wire _T_1036 = _T_1030 | gw_int_pending_5; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_6 = gw_config_reg_6[1] ? _T_1036 : _T_1030; // @[pic_ctrl.scala 32:8] - wire _T_1042 = extintsrc_req_sync[7] ^ gw_config_reg_7[0]; // @[pic_ctrl.scala 30:50] - wire _T_1043 = ~gw_clear_reg_we_7; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_6; // @[pic_ctrl.scala 31:45] - wire _T_1044 = gw_int_pending_6 & _T_1043; // @[pic_ctrl.scala 30:90] - wire _T_1048 = _T_1042 | gw_int_pending_6; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_7 = gw_config_reg_7[1] ? _T_1048 : _T_1042; // @[pic_ctrl.scala 32:8] - wire _T_1054 = extintsrc_req_sync[8] ^ gw_config_reg_8[0]; // @[pic_ctrl.scala 30:50] - wire _T_1055 = ~gw_clear_reg_we_8; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_7; // @[pic_ctrl.scala 31:45] - wire _T_1056 = gw_int_pending_7 & _T_1055; // @[pic_ctrl.scala 30:90] - wire _T_1060 = _T_1054 | gw_int_pending_7; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_8 = gw_config_reg_8[1] ? _T_1060 : _T_1054; // @[pic_ctrl.scala 32:8] - wire _T_1066 = extintsrc_req_sync[9] ^ gw_config_reg_9[0]; // @[pic_ctrl.scala 30:50] - wire _T_1067 = ~gw_clear_reg_we_9; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_8; // @[pic_ctrl.scala 31:45] - wire _T_1068 = gw_int_pending_8 & _T_1067; // @[pic_ctrl.scala 30:90] - wire _T_1072 = _T_1066 | gw_int_pending_8; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_9 = gw_config_reg_9[1] ? _T_1072 : _T_1066; // @[pic_ctrl.scala 32:8] - wire _T_1078 = extintsrc_req_sync[10] ^ gw_config_reg_10[0]; // @[pic_ctrl.scala 30:50] - wire _T_1079 = ~gw_clear_reg_we_10; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_9; // @[pic_ctrl.scala 31:45] - wire _T_1080 = gw_int_pending_9 & _T_1079; // @[pic_ctrl.scala 30:90] - wire _T_1084 = _T_1078 | gw_int_pending_9; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_10 = gw_config_reg_10[1] ? _T_1084 : _T_1078; // @[pic_ctrl.scala 32:8] - wire _T_1090 = extintsrc_req_sync[11] ^ gw_config_reg_11[0]; // @[pic_ctrl.scala 30:50] - wire _T_1091 = ~gw_clear_reg_we_11; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_10; // @[pic_ctrl.scala 31:45] - wire _T_1092 = gw_int_pending_10 & _T_1091; // @[pic_ctrl.scala 30:90] - wire _T_1096 = _T_1090 | gw_int_pending_10; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_11 = gw_config_reg_11[1] ? _T_1096 : _T_1090; // @[pic_ctrl.scala 32:8] - wire _T_1102 = extintsrc_req_sync[12] ^ gw_config_reg_12[0]; // @[pic_ctrl.scala 30:50] - wire _T_1103 = ~gw_clear_reg_we_12; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_11; // @[pic_ctrl.scala 31:45] - wire _T_1104 = gw_int_pending_11 & _T_1103; // @[pic_ctrl.scala 30:90] - wire _T_1108 = _T_1102 | gw_int_pending_11; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_12 = gw_config_reg_12[1] ? _T_1108 : _T_1102; // @[pic_ctrl.scala 32:8] - wire _T_1114 = extintsrc_req_sync[13] ^ gw_config_reg_13[0]; // @[pic_ctrl.scala 30:50] - wire _T_1115 = ~gw_clear_reg_we_13; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_12; // @[pic_ctrl.scala 31:45] - wire _T_1116 = gw_int_pending_12 & _T_1115; // @[pic_ctrl.scala 30:90] - wire _T_1120 = _T_1114 | gw_int_pending_12; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_13 = gw_config_reg_13[1] ? _T_1120 : _T_1114; // @[pic_ctrl.scala 32:8] - wire _T_1126 = extintsrc_req_sync[14] ^ gw_config_reg_14[0]; // @[pic_ctrl.scala 30:50] - wire _T_1127 = ~gw_clear_reg_we_14; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_13; // @[pic_ctrl.scala 31:45] - wire _T_1128 = gw_int_pending_13 & _T_1127; // @[pic_ctrl.scala 30:90] - wire _T_1132 = _T_1126 | gw_int_pending_13; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_14 = gw_config_reg_14[1] ? _T_1132 : _T_1126; // @[pic_ctrl.scala 32:8] - wire _T_1138 = extintsrc_req_sync[15] ^ gw_config_reg_15[0]; // @[pic_ctrl.scala 30:50] - wire _T_1139 = ~gw_clear_reg_we_15; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_14; // @[pic_ctrl.scala 31:45] - wire _T_1140 = gw_int_pending_14 & _T_1139; // @[pic_ctrl.scala 30:90] - wire _T_1144 = _T_1138 | gw_int_pending_14; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_15 = gw_config_reg_15[1] ? _T_1144 : _T_1138; // @[pic_ctrl.scala 32:8] - wire _T_1150 = extintsrc_req_sync[16] ^ gw_config_reg_16[0]; // @[pic_ctrl.scala 30:50] - wire _T_1151 = ~gw_clear_reg_we_16; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_15; // @[pic_ctrl.scala 31:45] - wire _T_1152 = gw_int_pending_15 & _T_1151; // @[pic_ctrl.scala 30:90] - wire _T_1156 = _T_1150 | gw_int_pending_15; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_16 = gw_config_reg_16[1] ? _T_1156 : _T_1150; // @[pic_ctrl.scala 32:8] - wire _T_1162 = extintsrc_req_sync[17] ^ gw_config_reg_17[0]; // @[pic_ctrl.scala 30:50] - wire _T_1163 = ~gw_clear_reg_we_17; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_16; // @[pic_ctrl.scala 31:45] - wire _T_1164 = gw_int_pending_16 & _T_1163; // @[pic_ctrl.scala 30:90] - wire _T_1168 = _T_1162 | gw_int_pending_16; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_17 = gw_config_reg_17[1] ? _T_1168 : _T_1162; // @[pic_ctrl.scala 32:8] - wire _T_1174 = extintsrc_req_sync[18] ^ gw_config_reg_18[0]; // @[pic_ctrl.scala 30:50] - wire _T_1175 = ~gw_clear_reg_we_18; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_17; // @[pic_ctrl.scala 31:45] - wire _T_1176 = gw_int_pending_17 & _T_1175; // @[pic_ctrl.scala 30:90] - wire _T_1180 = _T_1174 | gw_int_pending_17; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_18 = gw_config_reg_18[1] ? _T_1180 : _T_1174; // @[pic_ctrl.scala 32:8] - wire _T_1186 = extintsrc_req_sync[19] ^ gw_config_reg_19[0]; // @[pic_ctrl.scala 30:50] - wire _T_1187 = ~gw_clear_reg_we_19; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_18; // @[pic_ctrl.scala 31:45] - wire _T_1188 = gw_int_pending_18 & _T_1187; // @[pic_ctrl.scala 30:90] - wire _T_1192 = _T_1186 | gw_int_pending_18; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_19 = gw_config_reg_19[1] ? _T_1192 : _T_1186; // @[pic_ctrl.scala 32:8] - wire _T_1198 = extintsrc_req_sync[20] ^ gw_config_reg_20[0]; // @[pic_ctrl.scala 30:50] - wire _T_1199 = ~gw_clear_reg_we_20; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_19; // @[pic_ctrl.scala 31:45] - wire _T_1200 = gw_int_pending_19 & _T_1199; // @[pic_ctrl.scala 30:90] - wire _T_1204 = _T_1198 | gw_int_pending_19; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_20 = gw_config_reg_20[1] ? _T_1204 : _T_1198; // @[pic_ctrl.scala 32:8] - wire _T_1210 = extintsrc_req_sync[21] ^ gw_config_reg_21[0]; // @[pic_ctrl.scala 30:50] - wire _T_1211 = ~gw_clear_reg_we_21; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_20; // @[pic_ctrl.scala 31:45] - wire _T_1212 = gw_int_pending_20 & _T_1211; // @[pic_ctrl.scala 30:90] - wire _T_1216 = _T_1210 | gw_int_pending_20; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_21 = gw_config_reg_21[1] ? _T_1216 : _T_1210; // @[pic_ctrl.scala 32:8] - wire _T_1222 = extintsrc_req_sync[22] ^ gw_config_reg_22[0]; // @[pic_ctrl.scala 30:50] - wire _T_1223 = ~gw_clear_reg_we_22; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_21; // @[pic_ctrl.scala 31:45] - wire _T_1224 = gw_int_pending_21 & _T_1223; // @[pic_ctrl.scala 30:90] - wire _T_1228 = _T_1222 | gw_int_pending_21; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_22 = gw_config_reg_22[1] ? _T_1228 : _T_1222; // @[pic_ctrl.scala 32:8] - wire _T_1234 = extintsrc_req_sync[23] ^ gw_config_reg_23[0]; // @[pic_ctrl.scala 30:50] - wire _T_1235 = ~gw_clear_reg_we_23; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_22; // @[pic_ctrl.scala 31:45] - wire _T_1236 = gw_int_pending_22 & _T_1235; // @[pic_ctrl.scala 30:90] - wire _T_1240 = _T_1234 | gw_int_pending_22; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_23 = gw_config_reg_23[1] ? _T_1240 : _T_1234; // @[pic_ctrl.scala 32:8] - wire _T_1246 = extintsrc_req_sync[24] ^ gw_config_reg_24[0]; // @[pic_ctrl.scala 30:50] - wire _T_1247 = ~gw_clear_reg_we_24; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_23; // @[pic_ctrl.scala 31:45] - wire _T_1248 = gw_int_pending_23 & _T_1247; // @[pic_ctrl.scala 30:90] - wire _T_1252 = _T_1246 | gw_int_pending_23; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_24 = gw_config_reg_24[1] ? _T_1252 : _T_1246; // @[pic_ctrl.scala 32:8] - wire _T_1258 = extintsrc_req_sync[25] ^ gw_config_reg_25[0]; // @[pic_ctrl.scala 30:50] - wire _T_1259 = ~gw_clear_reg_we_25; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_24; // @[pic_ctrl.scala 31:45] - wire _T_1260 = gw_int_pending_24 & _T_1259; // @[pic_ctrl.scala 30:90] - wire _T_1264 = _T_1258 | gw_int_pending_24; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_25 = gw_config_reg_25[1] ? _T_1264 : _T_1258; // @[pic_ctrl.scala 32:8] - wire _T_1270 = extintsrc_req_sync[26] ^ gw_config_reg_26[0]; // @[pic_ctrl.scala 30:50] - wire _T_1271 = ~gw_clear_reg_we_26; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_25; // @[pic_ctrl.scala 31:45] - wire _T_1272 = gw_int_pending_25 & _T_1271; // @[pic_ctrl.scala 30:90] - wire _T_1276 = _T_1270 | gw_int_pending_25; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_26 = gw_config_reg_26[1] ? _T_1276 : _T_1270; // @[pic_ctrl.scala 32:8] - wire _T_1282 = extintsrc_req_sync[27] ^ gw_config_reg_27[0]; // @[pic_ctrl.scala 30:50] - wire _T_1283 = ~gw_clear_reg_we_27; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_26; // @[pic_ctrl.scala 31:45] - wire _T_1284 = gw_int_pending_26 & _T_1283; // @[pic_ctrl.scala 30:90] - wire _T_1288 = _T_1282 | gw_int_pending_26; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_27 = gw_config_reg_27[1] ? _T_1288 : _T_1282; // @[pic_ctrl.scala 32:8] - wire _T_1294 = extintsrc_req_sync[28] ^ gw_config_reg_28[0]; // @[pic_ctrl.scala 30:50] - wire _T_1295 = ~gw_clear_reg_we_28; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_27; // @[pic_ctrl.scala 31:45] - wire _T_1296 = gw_int_pending_27 & _T_1295; // @[pic_ctrl.scala 30:90] - wire _T_1300 = _T_1294 | gw_int_pending_27; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_28 = gw_config_reg_28[1] ? _T_1300 : _T_1294; // @[pic_ctrl.scala 32:8] - wire _T_1306 = extintsrc_req_sync[29] ^ gw_config_reg_29[0]; // @[pic_ctrl.scala 30:50] - wire _T_1307 = ~gw_clear_reg_we_29; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_28; // @[pic_ctrl.scala 31:45] - wire _T_1308 = gw_int_pending_28 & _T_1307; // @[pic_ctrl.scala 30:90] - wire _T_1312 = _T_1306 | gw_int_pending_28; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_29 = gw_config_reg_29[1] ? _T_1312 : _T_1306; // @[pic_ctrl.scala 32:8] - wire _T_1318 = extintsrc_req_sync[30] ^ gw_config_reg_30[0]; // @[pic_ctrl.scala 30:50] - wire _T_1319 = ~gw_clear_reg_we_30; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_29; // @[pic_ctrl.scala 31:45] - wire _T_1320 = gw_int_pending_29 & _T_1319; // @[pic_ctrl.scala 30:90] - wire _T_1324 = _T_1318 | gw_int_pending_29; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_30 = gw_config_reg_30[1] ? _T_1324 : _T_1318; // @[pic_ctrl.scala 32:8] - wire _T_1330 = extintsrc_req_sync[31] ^ gw_config_reg_31[0]; // @[pic_ctrl.scala 30:50] - wire _T_1331 = ~gw_clear_reg_we_31; // @[pic_ctrl.scala 30:92] - reg gw_int_pending_30; // @[pic_ctrl.scala 31:45] - wire _T_1332 = gw_int_pending_30 & _T_1331; // @[pic_ctrl.scala 30:90] - wire _T_1336 = _T_1330 | gw_int_pending_30; // @[pic_ctrl.scala 32:78] - wire extintsrc_req_gw_31 = gw_config_reg_31[1] ? _T_1336 : _T_1330; // @[pic_ctrl.scala 32:8] + wire _T_970 = extintsrc_req_sync[1] ^ gw_config_reg_1[0]; // @[pic_ctrl.scala 31:50] + wire _T_971 = ~gw_clear_reg_we_1; // @[pic_ctrl.scala 31:92] + reg gw_int_pending; // @[pic_ctrl.scala 32:45] + wire _T_972 = gw_int_pending & _T_971; // @[pic_ctrl.scala 31:90] + wire _T_976 = _T_970 | gw_int_pending; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_1 = gw_config_reg_1[1] ? _T_976 : _T_970; // @[pic_ctrl.scala 33:8] + wire _T_982 = extintsrc_req_sync[2] ^ gw_config_reg_2[0]; // @[pic_ctrl.scala 31:50] + wire _T_983 = ~gw_clear_reg_we_2; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_1; // @[pic_ctrl.scala 32:45] + wire _T_984 = gw_int_pending_1 & _T_983; // @[pic_ctrl.scala 31:90] + wire _T_988 = _T_982 | gw_int_pending_1; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_2 = gw_config_reg_2[1] ? _T_988 : _T_982; // @[pic_ctrl.scala 33:8] + wire _T_994 = extintsrc_req_sync[3] ^ gw_config_reg_3[0]; // @[pic_ctrl.scala 31:50] + wire _T_995 = ~gw_clear_reg_we_3; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_2; // @[pic_ctrl.scala 32:45] + wire _T_996 = gw_int_pending_2 & _T_995; // @[pic_ctrl.scala 31:90] + wire _T_1000 = _T_994 | gw_int_pending_2; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_3 = gw_config_reg_3[1] ? _T_1000 : _T_994; // @[pic_ctrl.scala 33:8] + wire _T_1006 = extintsrc_req_sync[4] ^ gw_config_reg_4[0]; // @[pic_ctrl.scala 31:50] + wire _T_1007 = ~gw_clear_reg_we_4; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_3; // @[pic_ctrl.scala 32:45] + wire _T_1008 = gw_int_pending_3 & _T_1007; // @[pic_ctrl.scala 31:90] + wire _T_1012 = _T_1006 | gw_int_pending_3; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_4 = gw_config_reg_4[1] ? _T_1012 : _T_1006; // @[pic_ctrl.scala 33:8] + wire _T_1018 = extintsrc_req_sync[5] ^ gw_config_reg_5[0]; // @[pic_ctrl.scala 31:50] + wire _T_1019 = ~gw_clear_reg_we_5; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_4; // @[pic_ctrl.scala 32:45] + wire _T_1020 = gw_int_pending_4 & _T_1019; // @[pic_ctrl.scala 31:90] + wire _T_1024 = _T_1018 | gw_int_pending_4; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_5 = gw_config_reg_5[1] ? _T_1024 : _T_1018; // @[pic_ctrl.scala 33:8] + wire _T_1030 = extintsrc_req_sync[6] ^ gw_config_reg_6[0]; // @[pic_ctrl.scala 31:50] + wire _T_1031 = ~gw_clear_reg_we_6; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_5; // @[pic_ctrl.scala 32:45] + wire _T_1032 = gw_int_pending_5 & _T_1031; // @[pic_ctrl.scala 31:90] + wire _T_1036 = _T_1030 | gw_int_pending_5; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_6 = gw_config_reg_6[1] ? _T_1036 : _T_1030; // @[pic_ctrl.scala 33:8] + wire _T_1042 = extintsrc_req_sync[7] ^ gw_config_reg_7[0]; // @[pic_ctrl.scala 31:50] + wire _T_1043 = ~gw_clear_reg_we_7; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_6; // @[pic_ctrl.scala 32:45] + wire _T_1044 = gw_int_pending_6 & _T_1043; // @[pic_ctrl.scala 31:90] + wire _T_1048 = _T_1042 | gw_int_pending_6; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_7 = gw_config_reg_7[1] ? _T_1048 : _T_1042; // @[pic_ctrl.scala 33:8] + wire _T_1054 = extintsrc_req_sync[8] ^ gw_config_reg_8[0]; // @[pic_ctrl.scala 31:50] + wire _T_1055 = ~gw_clear_reg_we_8; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_7; // @[pic_ctrl.scala 32:45] + wire _T_1056 = gw_int_pending_7 & _T_1055; // @[pic_ctrl.scala 31:90] + wire _T_1060 = _T_1054 | gw_int_pending_7; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_8 = gw_config_reg_8[1] ? _T_1060 : _T_1054; // @[pic_ctrl.scala 33:8] + wire _T_1066 = extintsrc_req_sync[9] ^ gw_config_reg_9[0]; // @[pic_ctrl.scala 31:50] + wire _T_1067 = ~gw_clear_reg_we_9; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_8; // @[pic_ctrl.scala 32:45] + wire _T_1068 = gw_int_pending_8 & _T_1067; // @[pic_ctrl.scala 31:90] + wire _T_1072 = _T_1066 | gw_int_pending_8; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_9 = gw_config_reg_9[1] ? _T_1072 : _T_1066; // @[pic_ctrl.scala 33:8] + wire _T_1078 = extintsrc_req_sync[10] ^ gw_config_reg_10[0]; // @[pic_ctrl.scala 31:50] + wire _T_1079 = ~gw_clear_reg_we_10; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_9; // @[pic_ctrl.scala 32:45] + wire _T_1080 = gw_int_pending_9 & _T_1079; // @[pic_ctrl.scala 31:90] + wire _T_1084 = _T_1078 | gw_int_pending_9; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_10 = gw_config_reg_10[1] ? _T_1084 : _T_1078; // @[pic_ctrl.scala 33:8] + wire _T_1090 = extintsrc_req_sync[11] ^ gw_config_reg_11[0]; // @[pic_ctrl.scala 31:50] + wire _T_1091 = ~gw_clear_reg_we_11; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_10; // @[pic_ctrl.scala 32:45] + wire _T_1092 = gw_int_pending_10 & _T_1091; // @[pic_ctrl.scala 31:90] + wire _T_1096 = _T_1090 | gw_int_pending_10; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_11 = gw_config_reg_11[1] ? _T_1096 : _T_1090; // @[pic_ctrl.scala 33:8] + wire _T_1102 = extintsrc_req_sync[12] ^ gw_config_reg_12[0]; // @[pic_ctrl.scala 31:50] + wire _T_1103 = ~gw_clear_reg_we_12; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_11; // @[pic_ctrl.scala 32:45] + wire _T_1104 = gw_int_pending_11 & _T_1103; // @[pic_ctrl.scala 31:90] + wire _T_1108 = _T_1102 | gw_int_pending_11; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_12 = gw_config_reg_12[1] ? _T_1108 : _T_1102; // @[pic_ctrl.scala 33:8] + wire _T_1114 = extintsrc_req_sync[13] ^ gw_config_reg_13[0]; // @[pic_ctrl.scala 31:50] + wire _T_1115 = ~gw_clear_reg_we_13; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_12; // @[pic_ctrl.scala 32:45] + wire _T_1116 = gw_int_pending_12 & _T_1115; // @[pic_ctrl.scala 31:90] + wire _T_1120 = _T_1114 | gw_int_pending_12; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_13 = gw_config_reg_13[1] ? _T_1120 : _T_1114; // @[pic_ctrl.scala 33:8] + wire _T_1126 = extintsrc_req_sync[14] ^ gw_config_reg_14[0]; // @[pic_ctrl.scala 31:50] + wire _T_1127 = ~gw_clear_reg_we_14; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_13; // @[pic_ctrl.scala 32:45] + wire _T_1128 = gw_int_pending_13 & _T_1127; // @[pic_ctrl.scala 31:90] + wire _T_1132 = _T_1126 | gw_int_pending_13; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_14 = gw_config_reg_14[1] ? _T_1132 : _T_1126; // @[pic_ctrl.scala 33:8] + wire _T_1138 = extintsrc_req_sync[15] ^ gw_config_reg_15[0]; // @[pic_ctrl.scala 31:50] + wire _T_1139 = ~gw_clear_reg_we_15; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_14; // @[pic_ctrl.scala 32:45] + wire _T_1140 = gw_int_pending_14 & _T_1139; // @[pic_ctrl.scala 31:90] + wire _T_1144 = _T_1138 | gw_int_pending_14; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_15 = gw_config_reg_15[1] ? _T_1144 : _T_1138; // @[pic_ctrl.scala 33:8] + wire _T_1150 = extintsrc_req_sync[16] ^ gw_config_reg_16[0]; // @[pic_ctrl.scala 31:50] + wire _T_1151 = ~gw_clear_reg_we_16; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_15; // @[pic_ctrl.scala 32:45] + wire _T_1152 = gw_int_pending_15 & _T_1151; // @[pic_ctrl.scala 31:90] + wire _T_1156 = _T_1150 | gw_int_pending_15; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_16 = gw_config_reg_16[1] ? _T_1156 : _T_1150; // @[pic_ctrl.scala 33:8] + wire _T_1162 = extintsrc_req_sync[17] ^ gw_config_reg_17[0]; // @[pic_ctrl.scala 31:50] + wire _T_1163 = ~gw_clear_reg_we_17; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_16; // @[pic_ctrl.scala 32:45] + wire _T_1164 = gw_int_pending_16 & _T_1163; // @[pic_ctrl.scala 31:90] + wire _T_1168 = _T_1162 | gw_int_pending_16; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_17 = gw_config_reg_17[1] ? _T_1168 : _T_1162; // @[pic_ctrl.scala 33:8] + wire _T_1174 = extintsrc_req_sync[18] ^ gw_config_reg_18[0]; // @[pic_ctrl.scala 31:50] + wire _T_1175 = ~gw_clear_reg_we_18; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_17; // @[pic_ctrl.scala 32:45] + wire _T_1176 = gw_int_pending_17 & _T_1175; // @[pic_ctrl.scala 31:90] + wire _T_1180 = _T_1174 | gw_int_pending_17; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_18 = gw_config_reg_18[1] ? _T_1180 : _T_1174; // @[pic_ctrl.scala 33:8] + wire _T_1186 = extintsrc_req_sync[19] ^ gw_config_reg_19[0]; // @[pic_ctrl.scala 31:50] + wire _T_1187 = ~gw_clear_reg_we_19; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_18; // @[pic_ctrl.scala 32:45] + wire _T_1188 = gw_int_pending_18 & _T_1187; // @[pic_ctrl.scala 31:90] + wire _T_1192 = _T_1186 | gw_int_pending_18; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_19 = gw_config_reg_19[1] ? _T_1192 : _T_1186; // @[pic_ctrl.scala 33:8] + wire _T_1198 = extintsrc_req_sync[20] ^ gw_config_reg_20[0]; // @[pic_ctrl.scala 31:50] + wire _T_1199 = ~gw_clear_reg_we_20; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_19; // @[pic_ctrl.scala 32:45] + wire _T_1200 = gw_int_pending_19 & _T_1199; // @[pic_ctrl.scala 31:90] + wire _T_1204 = _T_1198 | gw_int_pending_19; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_20 = gw_config_reg_20[1] ? _T_1204 : _T_1198; // @[pic_ctrl.scala 33:8] + wire _T_1210 = extintsrc_req_sync[21] ^ gw_config_reg_21[0]; // @[pic_ctrl.scala 31:50] + wire _T_1211 = ~gw_clear_reg_we_21; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_20; // @[pic_ctrl.scala 32:45] + wire _T_1212 = gw_int_pending_20 & _T_1211; // @[pic_ctrl.scala 31:90] + wire _T_1216 = _T_1210 | gw_int_pending_20; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_21 = gw_config_reg_21[1] ? _T_1216 : _T_1210; // @[pic_ctrl.scala 33:8] + wire _T_1222 = extintsrc_req_sync[22] ^ gw_config_reg_22[0]; // @[pic_ctrl.scala 31:50] + wire _T_1223 = ~gw_clear_reg_we_22; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_21; // @[pic_ctrl.scala 32:45] + wire _T_1224 = gw_int_pending_21 & _T_1223; // @[pic_ctrl.scala 31:90] + wire _T_1228 = _T_1222 | gw_int_pending_21; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_22 = gw_config_reg_22[1] ? _T_1228 : _T_1222; // @[pic_ctrl.scala 33:8] + wire _T_1234 = extintsrc_req_sync[23] ^ gw_config_reg_23[0]; // @[pic_ctrl.scala 31:50] + wire _T_1235 = ~gw_clear_reg_we_23; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_22; // @[pic_ctrl.scala 32:45] + wire _T_1236 = gw_int_pending_22 & _T_1235; // @[pic_ctrl.scala 31:90] + wire _T_1240 = _T_1234 | gw_int_pending_22; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_23 = gw_config_reg_23[1] ? _T_1240 : _T_1234; // @[pic_ctrl.scala 33:8] + wire _T_1246 = extintsrc_req_sync[24] ^ gw_config_reg_24[0]; // @[pic_ctrl.scala 31:50] + wire _T_1247 = ~gw_clear_reg_we_24; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_23; // @[pic_ctrl.scala 32:45] + wire _T_1248 = gw_int_pending_23 & _T_1247; // @[pic_ctrl.scala 31:90] + wire _T_1252 = _T_1246 | gw_int_pending_23; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_24 = gw_config_reg_24[1] ? _T_1252 : _T_1246; // @[pic_ctrl.scala 33:8] + wire _T_1258 = extintsrc_req_sync[25] ^ gw_config_reg_25[0]; // @[pic_ctrl.scala 31:50] + wire _T_1259 = ~gw_clear_reg_we_25; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_24; // @[pic_ctrl.scala 32:45] + wire _T_1260 = gw_int_pending_24 & _T_1259; // @[pic_ctrl.scala 31:90] + wire _T_1264 = _T_1258 | gw_int_pending_24; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_25 = gw_config_reg_25[1] ? _T_1264 : _T_1258; // @[pic_ctrl.scala 33:8] + wire _T_1270 = extintsrc_req_sync[26] ^ gw_config_reg_26[0]; // @[pic_ctrl.scala 31:50] + wire _T_1271 = ~gw_clear_reg_we_26; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_25; // @[pic_ctrl.scala 32:45] + wire _T_1272 = gw_int_pending_25 & _T_1271; // @[pic_ctrl.scala 31:90] + wire _T_1276 = _T_1270 | gw_int_pending_25; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_26 = gw_config_reg_26[1] ? _T_1276 : _T_1270; // @[pic_ctrl.scala 33:8] + wire _T_1282 = extintsrc_req_sync[27] ^ gw_config_reg_27[0]; // @[pic_ctrl.scala 31:50] + wire _T_1283 = ~gw_clear_reg_we_27; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_26; // @[pic_ctrl.scala 32:45] + wire _T_1284 = gw_int_pending_26 & _T_1283; // @[pic_ctrl.scala 31:90] + wire _T_1288 = _T_1282 | gw_int_pending_26; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_27 = gw_config_reg_27[1] ? _T_1288 : _T_1282; // @[pic_ctrl.scala 33:8] + wire _T_1294 = extintsrc_req_sync[28] ^ gw_config_reg_28[0]; // @[pic_ctrl.scala 31:50] + wire _T_1295 = ~gw_clear_reg_we_28; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_27; // @[pic_ctrl.scala 32:45] + wire _T_1296 = gw_int_pending_27 & _T_1295; // @[pic_ctrl.scala 31:90] + wire _T_1300 = _T_1294 | gw_int_pending_27; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_28 = gw_config_reg_28[1] ? _T_1300 : _T_1294; // @[pic_ctrl.scala 33:8] + wire _T_1306 = extintsrc_req_sync[29] ^ gw_config_reg_29[0]; // @[pic_ctrl.scala 31:50] + wire _T_1307 = ~gw_clear_reg_we_29; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_28; // @[pic_ctrl.scala 32:45] + wire _T_1308 = gw_int_pending_28 & _T_1307; // @[pic_ctrl.scala 31:90] + wire _T_1312 = _T_1306 | gw_int_pending_28; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_29 = gw_config_reg_29[1] ? _T_1312 : _T_1306; // @[pic_ctrl.scala 33:8] + wire _T_1318 = extintsrc_req_sync[30] ^ gw_config_reg_30[0]; // @[pic_ctrl.scala 31:50] + wire _T_1319 = ~gw_clear_reg_we_30; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_29; // @[pic_ctrl.scala 32:45] + wire _T_1320 = gw_int_pending_29 & _T_1319; // @[pic_ctrl.scala 31:90] + wire _T_1324 = _T_1318 | gw_int_pending_29; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_30 = gw_config_reg_30[1] ? _T_1324 : _T_1318; // @[pic_ctrl.scala 33:8] + wire _T_1330 = extintsrc_req_sync[31] ^ gw_config_reg_31[0]; // @[pic_ctrl.scala 31:50] + wire _T_1331 = ~gw_clear_reg_we_31; // @[pic_ctrl.scala 31:92] + reg gw_int_pending_30; // @[pic_ctrl.scala 32:45] + wire _T_1332 = gw_int_pending_30 & _T_1331; // @[pic_ctrl.scala 31:90] + wire _T_1336 = _T_1330 | gw_int_pending_30; // @[pic_ctrl.scala 33:78] + wire extintsrc_req_gw_31 = gw_config_reg_31[1] ? _T_1336 : _T_1330; // @[pic_ctrl.scala 33:8] reg config_reg; // @[Reg.scala 27:20] - wire [3:0] intpriority_reg_0 = 4'h0; // @[pic_ctrl.scala 147:32 pic_ctrl.scala 148:208] - wire [3:0] _T_1342 = ~intpriority_reg_1; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_1 = config_reg ? _T_1342 : intpriority_reg_1; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1345 = ~intpriority_reg_2; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_2 = config_reg ? _T_1345 : intpriority_reg_2; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1348 = ~intpriority_reg_3; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_3 = config_reg ? _T_1348 : intpriority_reg_3; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1351 = ~intpriority_reg_4; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_4 = config_reg ? _T_1351 : intpriority_reg_4; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1354 = ~intpriority_reg_5; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_5 = config_reg ? _T_1354 : intpriority_reg_5; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1357 = ~intpriority_reg_6; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_6 = config_reg ? _T_1357 : intpriority_reg_6; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1360 = ~intpriority_reg_7; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_7 = config_reg ? _T_1360 : intpriority_reg_7; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1363 = ~intpriority_reg_8; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_8 = config_reg ? _T_1363 : intpriority_reg_8; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1366 = ~intpriority_reg_9; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_9 = config_reg ? _T_1366 : intpriority_reg_9; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1369 = ~intpriority_reg_10; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_10 = config_reg ? _T_1369 : intpriority_reg_10; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1372 = ~intpriority_reg_11; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_11 = config_reg ? _T_1372 : intpriority_reg_11; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1375 = ~intpriority_reg_12; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_12 = config_reg ? _T_1375 : intpriority_reg_12; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1378 = ~intpriority_reg_13; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_13 = config_reg ? _T_1378 : intpriority_reg_13; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1381 = ~intpriority_reg_14; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_14 = config_reg ? _T_1381 : intpriority_reg_14; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1384 = ~intpriority_reg_15; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_15 = config_reg ? _T_1384 : intpriority_reg_15; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1387 = ~intpriority_reg_16; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_16 = config_reg ? _T_1387 : intpriority_reg_16; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1390 = ~intpriority_reg_17; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_17 = config_reg ? _T_1390 : intpriority_reg_17; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1393 = ~intpriority_reg_18; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_18 = config_reg ? _T_1393 : intpriority_reg_18; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1396 = ~intpriority_reg_19; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_19 = config_reg ? _T_1396 : intpriority_reg_19; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1399 = ~intpriority_reg_20; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_20 = config_reg ? _T_1399 : intpriority_reg_20; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1402 = ~intpriority_reg_21; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_21 = config_reg ? _T_1402 : intpriority_reg_21; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1405 = ~intpriority_reg_22; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_22 = config_reg ? _T_1405 : intpriority_reg_22; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1408 = ~intpriority_reg_23; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_23 = config_reg ? _T_1408 : intpriority_reg_23; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1411 = ~intpriority_reg_24; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_24 = config_reg ? _T_1411 : intpriority_reg_24; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1414 = ~intpriority_reg_25; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_25 = config_reg ? _T_1414 : intpriority_reg_25; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1417 = ~intpriority_reg_26; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_26 = config_reg ? _T_1417 : intpriority_reg_26; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1420 = ~intpriority_reg_27; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_27 = config_reg ? _T_1420 : intpriority_reg_27; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1423 = ~intpriority_reg_28; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_28 = config_reg ? _T_1423 : intpriority_reg_28; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1426 = ~intpriority_reg_29; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_29 = config_reg ? _T_1426 : intpriority_reg_29; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1429 = ~intpriority_reg_30; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_30 = config_reg ? _T_1429 : intpriority_reg_30; // @[pic_ctrl.scala 159:71] - wire [3:0] _T_1432 = ~intpriority_reg_31; // @[pic_ctrl.scala 159:90] - wire [3:0] intpriority_reg_inv_31 = config_reg ? _T_1432 : intpriority_reg_31; // @[pic_ctrl.scala 159:71] - wire _T_1438 = extintsrc_req_gw_1 & intenable_reg_1; // @[pic_ctrl.scala 160:110] + wire [3:0] intpriority_reg_0 = 4'h0; // @[pic_ctrl.scala 148:32 pic_ctrl.scala 149:208] + wire [3:0] _T_1342 = ~intpriority_reg_1; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_1 = config_reg ? _T_1342 : intpriority_reg_1; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1345 = ~intpriority_reg_2; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_2 = config_reg ? _T_1345 : intpriority_reg_2; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1348 = ~intpriority_reg_3; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_3 = config_reg ? _T_1348 : intpriority_reg_3; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1351 = ~intpriority_reg_4; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_4 = config_reg ? _T_1351 : intpriority_reg_4; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1354 = ~intpriority_reg_5; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_5 = config_reg ? _T_1354 : intpriority_reg_5; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1357 = ~intpriority_reg_6; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_6 = config_reg ? _T_1357 : intpriority_reg_6; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1360 = ~intpriority_reg_7; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_7 = config_reg ? _T_1360 : intpriority_reg_7; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1363 = ~intpriority_reg_8; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_8 = config_reg ? _T_1363 : intpriority_reg_8; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1366 = ~intpriority_reg_9; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_9 = config_reg ? _T_1366 : intpriority_reg_9; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1369 = ~intpriority_reg_10; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_10 = config_reg ? _T_1369 : intpriority_reg_10; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1372 = ~intpriority_reg_11; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_11 = config_reg ? _T_1372 : intpriority_reg_11; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1375 = ~intpriority_reg_12; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_12 = config_reg ? _T_1375 : intpriority_reg_12; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1378 = ~intpriority_reg_13; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_13 = config_reg ? _T_1378 : intpriority_reg_13; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1381 = ~intpriority_reg_14; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_14 = config_reg ? _T_1381 : intpriority_reg_14; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1384 = ~intpriority_reg_15; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_15 = config_reg ? _T_1384 : intpriority_reg_15; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1387 = ~intpriority_reg_16; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_16 = config_reg ? _T_1387 : intpriority_reg_16; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1390 = ~intpriority_reg_17; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_17 = config_reg ? _T_1390 : intpriority_reg_17; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1393 = ~intpriority_reg_18; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_18 = config_reg ? _T_1393 : intpriority_reg_18; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1396 = ~intpriority_reg_19; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_19 = config_reg ? _T_1396 : intpriority_reg_19; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1399 = ~intpriority_reg_20; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_20 = config_reg ? _T_1399 : intpriority_reg_20; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1402 = ~intpriority_reg_21; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_21 = config_reg ? _T_1402 : intpriority_reg_21; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1405 = ~intpriority_reg_22; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_22 = config_reg ? _T_1405 : intpriority_reg_22; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1408 = ~intpriority_reg_23; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_23 = config_reg ? _T_1408 : intpriority_reg_23; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1411 = ~intpriority_reg_24; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_24 = config_reg ? _T_1411 : intpriority_reg_24; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1414 = ~intpriority_reg_25; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_25 = config_reg ? _T_1414 : intpriority_reg_25; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1417 = ~intpriority_reg_26; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_26 = config_reg ? _T_1417 : intpriority_reg_26; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1420 = ~intpriority_reg_27; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_27 = config_reg ? _T_1420 : intpriority_reg_27; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1423 = ~intpriority_reg_28; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_28 = config_reg ? _T_1423 : intpriority_reg_28; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1426 = ~intpriority_reg_29; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_29 = config_reg ? _T_1426 : intpriority_reg_29; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1429 = ~intpriority_reg_30; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_30 = config_reg ? _T_1429 : intpriority_reg_30; // @[pic_ctrl.scala 160:71] + wire [3:0] _T_1432 = ~intpriority_reg_31; // @[pic_ctrl.scala 160:90] + wire [3:0] intpriority_reg_inv_31 = config_reg ? _T_1432 : intpriority_reg_31; // @[pic_ctrl.scala 160:71] + wire _T_1438 = extintsrc_req_gw_1 & intenable_reg_1; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1440 = _T_1438 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_1 = _T_1440 & intpriority_reg_inv_1; // @[pic_ctrl.scala 160:130] - wire _T_1442 = extintsrc_req_gw_2 & intenable_reg_2; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_1 = _T_1440 & intpriority_reg_inv_1; // @[pic_ctrl.scala 161:130] + wire _T_1442 = extintsrc_req_gw_2 & intenable_reg_2; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1444 = _T_1442 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_2 = _T_1444 & intpriority_reg_inv_2; // @[pic_ctrl.scala 160:130] - wire _T_1446 = extintsrc_req_gw_3 & intenable_reg_3; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_2 = _T_1444 & intpriority_reg_inv_2; // @[pic_ctrl.scala 161:130] + wire _T_1446 = extintsrc_req_gw_3 & intenable_reg_3; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1448 = _T_1446 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_3 = _T_1448 & intpriority_reg_inv_3; // @[pic_ctrl.scala 160:130] - wire _T_1450 = extintsrc_req_gw_4 & intenable_reg_4; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_3 = _T_1448 & intpriority_reg_inv_3; // @[pic_ctrl.scala 161:130] + wire _T_1450 = extintsrc_req_gw_4 & intenable_reg_4; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1452 = _T_1450 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_4 = _T_1452 & intpriority_reg_inv_4; // @[pic_ctrl.scala 160:130] - wire _T_1454 = extintsrc_req_gw_5 & intenable_reg_5; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_4 = _T_1452 & intpriority_reg_inv_4; // @[pic_ctrl.scala 161:130] + wire _T_1454 = extintsrc_req_gw_5 & intenable_reg_5; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1456 = _T_1454 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_5 = _T_1456 & intpriority_reg_inv_5; // @[pic_ctrl.scala 160:130] - wire _T_1458 = extintsrc_req_gw_6 & intenable_reg_6; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_5 = _T_1456 & intpriority_reg_inv_5; // @[pic_ctrl.scala 161:130] + wire _T_1458 = extintsrc_req_gw_6 & intenable_reg_6; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1460 = _T_1458 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_6 = _T_1460 & intpriority_reg_inv_6; // @[pic_ctrl.scala 160:130] - wire _T_1462 = extintsrc_req_gw_7 & intenable_reg_7; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_6 = _T_1460 & intpriority_reg_inv_6; // @[pic_ctrl.scala 161:130] + wire _T_1462 = extintsrc_req_gw_7 & intenable_reg_7; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1464 = _T_1462 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_7 = _T_1464 & intpriority_reg_inv_7; // @[pic_ctrl.scala 160:130] - wire _T_1466 = extintsrc_req_gw_8 & intenable_reg_8; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_7 = _T_1464 & intpriority_reg_inv_7; // @[pic_ctrl.scala 161:130] + wire _T_1466 = extintsrc_req_gw_8 & intenable_reg_8; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1468 = _T_1466 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_8 = _T_1468 & intpriority_reg_inv_8; // @[pic_ctrl.scala 160:130] - wire _T_1470 = extintsrc_req_gw_9 & intenable_reg_9; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_8 = _T_1468 & intpriority_reg_inv_8; // @[pic_ctrl.scala 161:130] + wire _T_1470 = extintsrc_req_gw_9 & intenable_reg_9; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1472 = _T_1470 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_9 = _T_1472 & intpriority_reg_inv_9; // @[pic_ctrl.scala 160:130] - wire _T_1474 = extintsrc_req_gw_10 & intenable_reg_10; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_9 = _T_1472 & intpriority_reg_inv_9; // @[pic_ctrl.scala 161:130] + wire _T_1474 = extintsrc_req_gw_10 & intenable_reg_10; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1476 = _T_1474 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_10 = _T_1476 & intpriority_reg_inv_10; // @[pic_ctrl.scala 160:130] - wire _T_1478 = extintsrc_req_gw_11 & intenable_reg_11; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_10 = _T_1476 & intpriority_reg_inv_10; // @[pic_ctrl.scala 161:130] + wire _T_1478 = extintsrc_req_gw_11 & intenable_reg_11; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1480 = _T_1478 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_11 = _T_1480 & intpriority_reg_inv_11; // @[pic_ctrl.scala 160:130] - wire _T_1482 = extintsrc_req_gw_12 & intenable_reg_12; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_11 = _T_1480 & intpriority_reg_inv_11; // @[pic_ctrl.scala 161:130] + wire _T_1482 = extintsrc_req_gw_12 & intenable_reg_12; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1484 = _T_1482 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_12 = _T_1484 & intpriority_reg_inv_12; // @[pic_ctrl.scala 160:130] - wire _T_1486 = extintsrc_req_gw_13 & intenable_reg_13; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_12 = _T_1484 & intpriority_reg_inv_12; // @[pic_ctrl.scala 161:130] + wire _T_1486 = extintsrc_req_gw_13 & intenable_reg_13; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1488 = _T_1486 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_13 = _T_1488 & intpriority_reg_inv_13; // @[pic_ctrl.scala 160:130] - wire _T_1490 = extintsrc_req_gw_14 & intenable_reg_14; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_13 = _T_1488 & intpriority_reg_inv_13; // @[pic_ctrl.scala 161:130] + wire _T_1490 = extintsrc_req_gw_14 & intenable_reg_14; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1492 = _T_1490 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_14 = _T_1492 & intpriority_reg_inv_14; // @[pic_ctrl.scala 160:130] - wire _T_1494 = extintsrc_req_gw_15 & intenable_reg_15; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_14 = _T_1492 & intpriority_reg_inv_14; // @[pic_ctrl.scala 161:130] + wire _T_1494 = extintsrc_req_gw_15 & intenable_reg_15; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1496 = _T_1494 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_15 = _T_1496 & intpriority_reg_inv_15; // @[pic_ctrl.scala 160:130] - wire _T_1498 = extintsrc_req_gw_16 & intenable_reg_16; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_15 = _T_1496 & intpriority_reg_inv_15; // @[pic_ctrl.scala 161:130] + wire _T_1498 = extintsrc_req_gw_16 & intenable_reg_16; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1500 = _T_1498 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_16 = _T_1500 & intpriority_reg_inv_16; // @[pic_ctrl.scala 160:130] - wire _T_1502 = extintsrc_req_gw_17 & intenable_reg_17; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_16 = _T_1500 & intpriority_reg_inv_16; // @[pic_ctrl.scala 161:130] + wire _T_1502 = extintsrc_req_gw_17 & intenable_reg_17; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1504 = _T_1502 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_17 = _T_1504 & intpriority_reg_inv_17; // @[pic_ctrl.scala 160:130] - wire _T_1506 = extintsrc_req_gw_18 & intenable_reg_18; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_17 = _T_1504 & intpriority_reg_inv_17; // @[pic_ctrl.scala 161:130] + wire _T_1506 = extintsrc_req_gw_18 & intenable_reg_18; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1508 = _T_1506 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_18 = _T_1508 & intpriority_reg_inv_18; // @[pic_ctrl.scala 160:130] - wire _T_1510 = extintsrc_req_gw_19 & intenable_reg_19; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_18 = _T_1508 & intpriority_reg_inv_18; // @[pic_ctrl.scala 161:130] + wire _T_1510 = extintsrc_req_gw_19 & intenable_reg_19; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1512 = _T_1510 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_19 = _T_1512 & intpriority_reg_inv_19; // @[pic_ctrl.scala 160:130] - wire _T_1514 = extintsrc_req_gw_20 & intenable_reg_20; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_19 = _T_1512 & intpriority_reg_inv_19; // @[pic_ctrl.scala 161:130] + wire _T_1514 = extintsrc_req_gw_20 & intenable_reg_20; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1516 = _T_1514 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_20 = _T_1516 & intpriority_reg_inv_20; // @[pic_ctrl.scala 160:130] - wire _T_1518 = extintsrc_req_gw_21 & intenable_reg_21; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_20 = _T_1516 & intpriority_reg_inv_20; // @[pic_ctrl.scala 161:130] + wire _T_1518 = extintsrc_req_gw_21 & intenable_reg_21; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1520 = _T_1518 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_21 = _T_1520 & intpriority_reg_inv_21; // @[pic_ctrl.scala 160:130] - wire _T_1522 = extintsrc_req_gw_22 & intenable_reg_22; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_21 = _T_1520 & intpriority_reg_inv_21; // @[pic_ctrl.scala 161:130] + wire _T_1522 = extintsrc_req_gw_22 & intenable_reg_22; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1524 = _T_1522 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_22 = _T_1524 & intpriority_reg_inv_22; // @[pic_ctrl.scala 160:130] - wire _T_1526 = extintsrc_req_gw_23 & intenable_reg_23; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_22 = _T_1524 & intpriority_reg_inv_22; // @[pic_ctrl.scala 161:130] + wire _T_1526 = extintsrc_req_gw_23 & intenable_reg_23; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1528 = _T_1526 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_23 = _T_1528 & intpriority_reg_inv_23; // @[pic_ctrl.scala 160:130] - wire _T_1530 = extintsrc_req_gw_24 & intenable_reg_24; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_23 = _T_1528 & intpriority_reg_inv_23; // @[pic_ctrl.scala 161:130] + wire _T_1530 = extintsrc_req_gw_24 & intenable_reg_24; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1532 = _T_1530 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_24 = _T_1532 & intpriority_reg_inv_24; // @[pic_ctrl.scala 160:130] - wire _T_1534 = extintsrc_req_gw_25 & intenable_reg_25; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_24 = _T_1532 & intpriority_reg_inv_24; // @[pic_ctrl.scala 161:130] + wire _T_1534 = extintsrc_req_gw_25 & intenable_reg_25; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1536 = _T_1534 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_25 = _T_1536 & intpriority_reg_inv_25; // @[pic_ctrl.scala 160:130] - wire _T_1538 = extintsrc_req_gw_26 & intenable_reg_26; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_25 = _T_1536 & intpriority_reg_inv_25; // @[pic_ctrl.scala 161:130] + wire _T_1538 = extintsrc_req_gw_26 & intenable_reg_26; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1540 = _T_1538 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_26 = _T_1540 & intpriority_reg_inv_26; // @[pic_ctrl.scala 160:130] - wire _T_1542 = extintsrc_req_gw_27 & intenable_reg_27; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_26 = _T_1540 & intpriority_reg_inv_26; // @[pic_ctrl.scala 161:130] + wire _T_1542 = extintsrc_req_gw_27 & intenable_reg_27; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1544 = _T_1542 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_27 = _T_1544 & intpriority_reg_inv_27; // @[pic_ctrl.scala 160:130] - wire _T_1546 = extintsrc_req_gw_28 & intenable_reg_28; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_27 = _T_1544 & intpriority_reg_inv_27; // @[pic_ctrl.scala 161:130] + wire _T_1546 = extintsrc_req_gw_28 & intenable_reg_28; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1548 = _T_1546 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_28 = _T_1548 & intpriority_reg_inv_28; // @[pic_ctrl.scala 160:130] - wire _T_1550 = extintsrc_req_gw_29 & intenable_reg_29; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_28 = _T_1548 & intpriority_reg_inv_28; // @[pic_ctrl.scala 161:130] + wire _T_1550 = extintsrc_req_gw_29 & intenable_reg_29; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1552 = _T_1550 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_29 = _T_1552 & intpriority_reg_inv_29; // @[pic_ctrl.scala 160:130] - wire _T_1554 = extintsrc_req_gw_30 & intenable_reg_30; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_29 = _T_1552 & intpriority_reg_inv_29; // @[pic_ctrl.scala 161:130] + wire _T_1554 = extintsrc_req_gw_30 & intenable_reg_30; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1556 = _T_1554 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_30 = _T_1556 & intpriority_reg_inv_30; // @[pic_ctrl.scala 160:130] - wire _T_1558 = extintsrc_req_gw_31 & intenable_reg_31; // @[pic_ctrl.scala 160:110] + wire [3:0] intpend_w_prior_en_30 = _T_1556 & intpriority_reg_inv_30; // @[pic_ctrl.scala 161:130] + wire _T_1558 = extintsrc_req_gw_31 & intenable_reg_31; // @[pic_ctrl.scala 161:110] wire [3:0] _T_1560 = _T_1558 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] intpend_w_prior_en_31 = _T_1560 & intpriority_reg_inv_31; // @[pic_ctrl.scala 160:130] + wire [3:0] intpend_w_prior_en_31 = _T_1560 & intpriority_reg_inv_31; // @[pic_ctrl.scala 161:130] wire [7:0] _T_1564 = 8'hff; // @[Bitwise.scala 72:12] - wire [3:0] level_intpend_w_prior_en_0_0 = 4'h0; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire [3:0] _T_1441 = intpend_w_prior_en_1; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_1 = intpend_w_prior_en_1; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire _T_1566 = intpriority_reg_0 < _T_1441; // @[pic_ctrl.scala 26:20] - wire [7:0] intpend_id_1 = 8'h1; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_1 = 8'h1; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] intpend_id_0 = 8'h0; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_0 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] out_id = _T_1566 ? intpend_id_1 : intpend_id_0; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority = _T_1566 ? _T_1441 : intpriority_reg_0; // @[pic_ctrl.scala 26:49] - wire [3:0] _T_1445 = intpend_w_prior_en_2; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_2 = intpend_w_prior_en_2; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire [3:0] _T_1449 = intpend_w_prior_en_3; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_3 = intpend_w_prior_en_3; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire _T_1568 = _T_1445 < _T_1449; // @[pic_ctrl.scala 26:20] - wire [7:0] intpend_id_3 = 8'h3; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_3 = 8'h3; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] intpend_id_2 = 8'h2; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_2 = 8'h2; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] out_id_1 = _T_1568 ? intpend_id_3 : intpend_id_2; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_1 = _T_1568 ? _T_1449 : _T_1445; // @[pic_ctrl.scala 26:49] - wire [3:0] _T_1453 = intpend_w_prior_en_4; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_4 = intpend_w_prior_en_4; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire [3:0] _T_1457 = intpend_w_prior_en_5; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_5 = intpend_w_prior_en_5; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire _T_1570 = _T_1453 < _T_1457; // @[pic_ctrl.scala 26:20] - wire [7:0] intpend_id_5 = 8'h5; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_5 = 8'h5; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] intpend_id_4 = 8'h4; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_4 = 8'h4; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] out_id_2 = _T_1570 ? intpend_id_5 : intpend_id_4; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_2 = _T_1570 ? _T_1457 : _T_1453; // @[pic_ctrl.scala 26:49] - wire [3:0] _T_1461 = intpend_w_prior_en_6; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_6 = intpend_w_prior_en_6; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire [3:0] _T_1465 = intpend_w_prior_en_7; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_7 = intpend_w_prior_en_7; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire _T_1572 = _T_1461 < _T_1465; // @[pic_ctrl.scala 26:20] - wire [7:0] intpend_id_7 = 8'h7; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_7 = 8'h7; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] intpend_id_6 = 8'h6; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_6 = 8'h6; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] out_id_3 = _T_1572 ? intpend_id_7 : intpend_id_6; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_3 = _T_1572 ? _T_1465 : _T_1461; // @[pic_ctrl.scala 26:49] - wire [3:0] _T_1469 = intpend_w_prior_en_8; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_8 = intpend_w_prior_en_8; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire [3:0] _T_1473 = intpend_w_prior_en_9; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_9 = intpend_w_prior_en_9; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire _T_1574 = _T_1469 < _T_1473; // @[pic_ctrl.scala 26:20] - wire [7:0] intpend_id_9 = 8'h9; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_9 = 8'h9; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] intpend_id_8 = 8'h8; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_8 = 8'h8; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] out_id_4 = _T_1574 ? intpend_id_9 : intpend_id_8; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_4 = _T_1574 ? _T_1473 : _T_1469; // @[pic_ctrl.scala 26:49] - wire [3:0] _T_1477 = intpend_w_prior_en_10; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_10 = intpend_w_prior_en_10; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire [3:0] _T_1481 = intpend_w_prior_en_11; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_11 = intpend_w_prior_en_11; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire _T_1576 = _T_1477 < _T_1481; // @[pic_ctrl.scala 26:20] - wire [7:0] intpend_id_11 = 8'hb; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_11 = 8'hb; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] intpend_id_10 = 8'ha; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_10 = 8'ha; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] out_id_5 = _T_1576 ? intpend_id_11 : intpend_id_10; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_5 = _T_1576 ? _T_1481 : _T_1477; // @[pic_ctrl.scala 26:49] - wire [3:0] _T_1485 = intpend_w_prior_en_12; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_12 = intpend_w_prior_en_12; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire [3:0] _T_1489 = intpend_w_prior_en_13; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_13 = intpend_w_prior_en_13; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire _T_1578 = _T_1485 < _T_1489; // @[pic_ctrl.scala 26:20] - wire [7:0] intpend_id_13 = 8'hd; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_13 = 8'hd; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] intpend_id_12 = 8'hc; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_12 = 8'hc; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] out_id_6 = _T_1578 ? intpend_id_13 : intpend_id_12; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_6 = _T_1578 ? _T_1489 : _T_1485; // @[pic_ctrl.scala 26:49] - wire [3:0] _T_1493 = intpend_w_prior_en_14; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_14 = intpend_w_prior_en_14; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire [3:0] _T_1497 = intpend_w_prior_en_15; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_15 = intpend_w_prior_en_15; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire _T_1580 = _T_1493 < _T_1497; // @[pic_ctrl.scala 26:20] - wire [7:0] intpend_id_15 = 8'hf; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_15 = 8'hf; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] intpend_id_14 = 8'he; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_14 = 8'he; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] out_id_7 = _T_1580 ? intpend_id_15 : intpend_id_14; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_7 = _T_1580 ? _T_1497 : _T_1493; // @[pic_ctrl.scala 26:49] - wire [3:0] _T_1501 = intpend_w_prior_en_16; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_16 = intpend_w_prior_en_16; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire [3:0] _T_1505 = intpend_w_prior_en_17; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_17 = intpend_w_prior_en_17; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire _T_1582 = _T_1501 < _T_1505; // @[pic_ctrl.scala 26:20] - wire [7:0] intpend_id_17 = 8'h11; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_17 = 8'h11; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] intpend_id_16 = 8'h10; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_16 = 8'h10; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] out_id_8 = _T_1582 ? intpend_id_17 : intpend_id_16; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_8 = _T_1582 ? _T_1505 : _T_1501; // @[pic_ctrl.scala 26:49] - wire [3:0] _T_1509 = intpend_w_prior_en_18; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_18 = intpend_w_prior_en_18; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire [3:0] _T_1513 = intpend_w_prior_en_19; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_19 = intpend_w_prior_en_19; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire _T_1584 = _T_1509 < _T_1513; // @[pic_ctrl.scala 26:20] - wire [7:0] intpend_id_19 = 8'h13; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_19 = 8'h13; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] intpend_id_18 = 8'h12; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_18 = 8'h12; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] out_id_9 = _T_1584 ? intpend_id_19 : intpend_id_18; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_9 = _T_1584 ? _T_1513 : _T_1509; // @[pic_ctrl.scala 26:49] - wire [3:0] _T_1517 = intpend_w_prior_en_20; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_20 = intpend_w_prior_en_20; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire [3:0] _T_1521 = intpend_w_prior_en_21; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_21 = intpend_w_prior_en_21; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire _T_1586 = _T_1517 < _T_1521; // @[pic_ctrl.scala 26:20] - wire [7:0] intpend_id_21 = 8'h15; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_21 = 8'h15; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] intpend_id_20 = 8'h14; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_20 = 8'h14; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] out_id_10 = _T_1586 ? intpend_id_21 : intpend_id_20; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_10 = _T_1586 ? _T_1521 : _T_1517; // @[pic_ctrl.scala 26:49] - wire [3:0] _T_1525 = intpend_w_prior_en_22; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_22 = intpend_w_prior_en_22; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire [3:0] _T_1529 = intpend_w_prior_en_23; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_23 = intpend_w_prior_en_23; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire _T_1588 = _T_1525 < _T_1529; // @[pic_ctrl.scala 26:20] - wire [7:0] intpend_id_23 = 8'h17; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_23 = 8'h17; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] intpend_id_22 = 8'h16; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_22 = 8'h16; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] out_id_11 = _T_1588 ? intpend_id_23 : intpend_id_22; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_11 = _T_1588 ? _T_1529 : _T_1525; // @[pic_ctrl.scala 26:49] - wire [3:0] _T_1533 = intpend_w_prior_en_24; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_24 = intpend_w_prior_en_24; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire [3:0] _T_1537 = intpend_w_prior_en_25; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_25 = intpend_w_prior_en_25; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire _T_1590 = _T_1533 < _T_1537; // @[pic_ctrl.scala 26:20] - wire [7:0] intpend_id_25 = 8'h19; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_25 = 8'h19; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] intpend_id_24 = 8'h18; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_24 = 8'h18; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] out_id_12 = _T_1590 ? intpend_id_25 : intpend_id_24; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_12 = _T_1590 ? _T_1537 : _T_1533; // @[pic_ctrl.scala 26:49] - wire [3:0] _T_1541 = intpend_w_prior_en_26; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_26 = intpend_w_prior_en_26; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire [3:0] _T_1545 = intpend_w_prior_en_27; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_27 = intpend_w_prior_en_27; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire _T_1592 = _T_1541 < _T_1545; // @[pic_ctrl.scala 26:20] - wire [7:0] intpend_id_27 = 8'h1b; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_27 = 8'h1b; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] intpend_id_26 = 8'h1a; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_26 = 8'h1a; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] out_id_13 = _T_1592 ? intpend_id_27 : intpend_id_26; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_13 = _T_1592 ? _T_1545 : _T_1541; // @[pic_ctrl.scala 26:49] - wire [3:0] _T_1549 = intpend_w_prior_en_28; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_28 = intpend_w_prior_en_28; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire [3:0] _T_1553 = intpend_w_prior_en_29; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_29 = intpend_w_prior_en_29; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire _T_1594 = _T_1549 < _T_1553; // @[pic_ctrl.scala 26:20] - wire [7:0] intpend_id_29 = 8'h1d; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_29 = 8'h1d; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] intpend_id_28 = 8'h1c; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_28 = 8'h1c; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] out_id_14 = _T_1594 ? intpend_id_29 : intpend_id_28; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_14 = _T_1594 ? _T_1553 : _T_1549; // @[pic_ctrl.scala 26:49] - wire [3:0] _T_1557 = intpend_w_prior_en_30; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_30 = intpend_w_prior_en_30; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire [3:0] _T_1561 = intpend_w_prior_en_31; // @[pic_ctrl.scala 69:42 pic_ctrl.scala 160:64] - wire [3:0] level_intpend_w_prior_en_0_31 = intpend_w_prior_en_31; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire _T_1596 = _T_1557 < _T_1561; // @[pic_ctrl.scala 26:20] - wire [7:0] intpend_id_31 = 8'h1f; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_31 = 8'h1f; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] intpend_id_30 = 8'h1e; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:56] - wire [7:0] level_intpend_id_0_30 = 8'h1e; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] out_id_15 = _T_1596 ? intpend_id_31 : intpend_id_30; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_15 = _T_1596 ? _T_1561 : _T_1557; // @[pic_ctrl.scala 26:49] - wire [3:0] level_intpend_w_prior_en_0_32 = 4'h0; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire [3:0] level_intpend_w_prior_en_0_33 = 4'h0; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 219:33] - wire _T_1598 = intpriority_reg_0 < intpriority_reg_0; // @[pic_ctrl.scala 26:20] - wire [7:0] level_intpend_id_0_33 = 8'hff; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] level_intpend_id_0_32 = 8'hff; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 220:33] - wire [7:0] out_id_16 = _T_1598 ? _T_1564 : _T_1564; // @[pic_ctrl.scala 26:9] - wire _T_1600 = out_priority < out_priority_1; // @[pic_ctrl.scala 26:20] - wire [7:0] level_intpend_id_1_1 = out_id_1; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] level_intpend_id_1_0 = out_id; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] out_id_17 = _T_1600 ? level_intpend_id_1_1 : level_intpend_id_1_0; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_17 = _T_1600 ? out_priority_1 : out_priority; // @[pic_ctrl.scala 26:49] - wire _T_1602 = out_priority_2 < out_priority_3; // @[pic_ctrl.scala 26:20] - wire [7:0] level_intpend_id_1_3 = out_id_3; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] level_intpend_id_1_2 = out_id_2; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] out_id_18 = _T_1602 ? level_intpend_id_1_3 : level_intpend_id_1_2; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_18 = _T_1602 ? out_priority_3 : out_priority_2; // @[pic_ctrl.scala 26:49] - wire _T_1604 = out_priority_4 < out_priority_5; // @[pic_ctrl.scala 26:20] - wire [7:0] level_intpend_id_1_5 = out_id_5; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] level_intpend_id_1_4 = out_id_4; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] out_id_19 = _T_1604 ? level_intpend_id_1_5 : level_intpend_id_1_4; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_19 = _T_1604 ? out_priority_5 : out_priority_4; // @[pic_ctrl.scala 26:49] - wire _T_1606 = out_priority_6 < out_priority_7; // @[pic_ctrl.scala 26:20] - wire [7:0] level_intpend_id_1_7 = out_id_7; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] level_intpend_id_1_6 = out_id_6; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] out_id_20 = _T_1606 ? level_intpend_id_1_7 : level_intpend_id_1_6; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_20 = _T_1606 ? out_priority_7 : out_priority_6; // @[pic_ctrl.scala 26:49] - wire _T_1608 = out_priority_8 < out_priority_9; // @[pic_ctrl.scala 26:20] - wire [7:0] level_intpend_id_1_9 = out_id_9; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] level_intpend_id_1_8 = out_id_8; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] out_id_21 = _T_1608 ? level_intpend_id_1_9 : level_intpend_id_1_8; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_21 = _T_1608 ? out_priority_9 : out_priority_8; // @[pic_ctrl.scala 26:49] - wire _T_1610 = out_priority_10 < out_priority_11; // @[pic_ctrl.scala 26:20] - wire [7:0] level_intpend_id_1_11 = out_id_11; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] level_intpend_id_1_10 = out_id_10; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] out_id_22 = _T_1610 ? level_intpend_id_1_11 : level_intpend_id_1_10; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_22 = _T_1610 ? out_priority_11 : out_priority_10; // @[pic_ctrl.scala 26:49] - wire _T_1612 = out_priority_12 < out_priority_13; // @[pic_ctrl.scala 26:20] - wire [7:0] level_intpend_id_1_13 = out_id_13; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] level_intpend_id_1_12 = out_id_12; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] out_id_23 = _T_1612 ? level_intpend_id_1_13 : level_intpend_id_1_12; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_23 = _T_1612 ? out_priority_13 : out_priority_12; // @[pic_ctrl.scala 26:49] - wire _T_1614 = out_priority_14 < out_priority_15; // @[pic_ctrl.scala 26:20] - wire [7:0] level_intpend_id_1_15 = out_id_15; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] level_intpend_id_1_14 = out_id_14; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] out_id_24 = _T_1614 ? level_intpend_id_1_15 : level_intpend_id_1_14; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_24 = _T_1614 ? out_priority_15 : out_priority_14; // @[pic_ctrl.scala 26:49] - wire [7:0] level_intpend_id_1_17 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 228:44] - wire [7:0] level_intpend_id_1_16 = out_id_16; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] out_id_25 = level_intpend_id_1_16; // @[pic_ctrl.scala 26:9] - wire _T_1618 = out_priority_17 < out_priority_18; // @[pic_ctrl.scala 26:20] - wire [7:0] level_intpend_id_2_1 = out_id_18; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] level_intpend_id_2_0 = out_id_17; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] out_id_26 = _T_1618 ? level_intpend_id_2_1 : level_intpend_id_2_0; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_26 = _T_1618 ? out_priority_18 : out_priority_17; // @[pic_ctrl.scala 26:49] - wire _T_1620 = out_priority_19 < out_priority_20; // @[pic_ctrl.scala 26:20] - wire [7:0] level_intpend_id_2_3 = out_id_20; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] level_intpend_id_2_2 = out_id_19; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] out_id_27 = _T_1620 ? level_intpend_id_2_3 : level_intpend_id_2_2; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_27 = _T_1620 ? out_priority_20 : out_priority_19; // @[pic_ctrl.scala 26:49] - wire _T_1622 = out_priority_21 < out_priority_22; // @[pic_ctrl.scala 26:20] - wire [7:0] level_intpend_id_2_5 = out_id_22; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] level_intpend_id_2_4 = out_id_21; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] out_id_28 = _T_1622 ? level_intpend_id_2_5 : level_intpend_id_2_4; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_28 = _T_1622 ? out_priority_22 : out_priority_21; // @[pic_ctrl.scala 26:49] - wire _T_1624 = out_priority_23 < out_priority_24; // @[pic_ctrl.scala 26:20] - wire [7:0] level_intpend_id_2_7 = out_id_24; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] level_intpend_id_2_6 = out_id_23; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] out_id_29 = _T_1624 ? level_intpend_id_2_7 : level_intpend_id_2_6; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_29 = _T_1624 ? out_priority_24 : out_priority_23; // @[pic_ctrl.scala 26:49] - wire [7:0] level_intpend_id_2_9 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 228:44] - wire [7:0] level_intpend_id_2_8 = level_intpend_id_1_16; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] out_id_30 = out_id_25; // @[pic_ctrl.scala 26:9] - wire _T_1628 = out_priority_26 < out_priority_27; // @[pic_ctrl.scala 26:20] - wire [7:0] level_intpend_id_3_1 = out_id_27; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] level_intpend_id_3_0 = out_id_26; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] out_id_31 = _T_1628 ? level_intpend_id_3_1 : level_intpend_id_3_0; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_31 = _T_1628 ? out_priority_27 : out_priority_26; // @[pic_ctrl.scala 26:49] - wire _T_1630 = out_priority_28 < out_priority_29; // @[pic_ctrl.scala 26:20] - wire [7:0] level_intpend_id_3_3 = out_id_29; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] level_intpend_id_3_2 = out_id_28; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] out_id_32 = _T_1630 ? level_intpend_id_3_3 : level_intpend_id_3_2; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_32 = _T_1630 ? out_priority_29 : out_priority_28; // @[pic_ctrl.scala 26:49] - wire [7:0] level_intpend_id_3_5 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 228:44] - wire [7:0] level_intpend_id_3_4 = out_id_25; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] out_id_33 = out_id_30; // @[pic_ctrl.scala 26:9] - wire _T_1634 = out_priority_31 < out_priority_32; // @[pic_ctrl.scala 26:20] - wire [7:0] level_intpend_id_4_1 = out_id_32; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] level_intpend_id_4_0 = out_id_31; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] out_id_34 = _T_1634 ? level_intpend_id_4_1 : level_intpend_id_4_0; // @[pic_ctrl.scala 26:9] - wire [3:0] out_priority_34 = _T_1634 ? out_priority_32 : out_priority_31; // @[pic_ctrl.scala 26:49] - wire [7:0] level_intpend_id_4_3 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 228:44] - wire [7:0] level_intpend_id_4_2 = out_id_30; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire config_reg_we = waddr_config_pic_match & picm_wren_ff; // @[pic_ctrl.scala 248:47] - wire config_reg_re = raddr_config_pic_match & picm_rden_ff; // @[pic_ctrl.scala 249:47] - wire [3:0] level_intpend_w_prior_en_5_0 = out_priority_34; // @[pic_ctrl.scala 212:40 pic_ctrl.scala 216:38 pic_ctrl.scala 232:41] - wire [3:0] selected_int_priority = out_priority_34; // @[pic_ctrl.scala 236:29] - wire [3:0] _T_1641 = ~level_intpend_w_prior_en_5_0; // @[pic_ctrl.scala 260:38] - wire [3:0] pl_in_q = config_reg ? _T_1641 : level_intpend_w_prior_en_5_0; // @[pic_ctrl.scala 260:20] - reg [7:0] _T_1642; // @[pic_ctrl.scala 261:47] - reg [3:0] _T_1643; // @[pic_ctrl.scala 262:42] - wire [3:0] _T_1645 = ~io_meipt; // @[pic_ctrl.scala 263:40] - wire [3:0] meipt_inv = config_reg ? _T_1645 : io_meipt; // @[pic_ctrl.scala 263:22] - wire [3:0] _T_1647 = ~io_meicurpl; // @[pic_ctrl.scala 264:43] - wire [3:0] meicurpl_inv = config_reg ? _T_1647 : io_meicurpl; // @[pic_ctrl.scala 264:25] - wire _T_1648 = level_intpend_w_prior_en_5_0 > meipt_inv; // @[pic_ctrl.scala 265:47] - wire _T_1649 = level_intpend_w_prior_en_5_0 > meicurpl_inv; // @[pic_ctrl.scala 265:86] - reg _T_1650; // @[pic_ctrl.scala 266:50] - wire [3:0] maxint = config_reg ? 4'h0 : 4'hf; // @[pic_ctrl.scala 267:19] - reg _T_1652; // @[pic_ctrl.scala 269:48] - wire intpend_reg_read = addr_intpend_base_match & picm_rden_ff; // @[pic_ctrl.scala 275:60] + wire [3:0] level_intpend_w_prior_en_0_0 = 4'h0; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire [3:0] _T_1441 = intpend_w_prior_en_1; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_1 = intpend_w_prior_en_1; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire _T_1566 = intpriority_reg_0 < _T_1441; // @[pic_ctrl.scala 27:20] + wire [7:0] intpend_id_1 = 8'h1; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_1 = 8'h1; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] intpend_id_0 = 8'h0; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_0 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] out_id = _T_1566 ? intpend_id_1 : intpend_id_0; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority = _T_1566 ? _T_1441 : intpriority_reg_0; // @[pic_ctrl.scala 27:49] + wire [3:0] _T_1445 = intpend_w_prior_en_2; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_2 = intpend_w_prior_en_2; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire [3:0] _T_1449 = intpend_w_prior_en_3; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_3 = intpend_w_prior_en_3; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire _T_1568 = _T_1445 < _T_1449; // @[pic_ctrl.scala 27:20] + wire [7:0] intpend_id_3 = 8'h3; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_3 = 8'h3; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] intpend_id_2 = 8'h2; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_2 = 8'h2; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] out_id_1 = _T_1568 ? intpend_id_3 : intpend_id_2; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_1 = _T_1568 ? _T_1449 : _T_1445; // @[pic_ctrl.scala 27:49] + wire [3:0] _T_1453 = intpend_w_prior_en_4; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_4 = intpend_w_prior_en_4; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire [3:0] _T_1457 = intpend_w_prior_en_5; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_5 = intpend_w_prior_en_5; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire _T_1570 = _T_1453 < _T_1457; // @[pic_ctrl.scala 27:20] + wire [7:0] intpend_id_5 = 8'h5; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_5 = 8'h5; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] intpend_id_4 = 8'h4; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_4 = 8'h4; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] out_id_2 = _T_1570 ? intpend_id_5 : intpend_id_4; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_2 = _T_1570 ? _T_1457 : _T_1453; // @[pic_ctrl.scala 27:49] + wire [3:0] _T_1461 = intpend_w_prior_en_6; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_6 = intpend_w_prior_en_6; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire [3:0] _T_1465 = intpend_w_prior_en_7; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_7 = intpend_w_prior_en_7; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire _T_1572 = _T_1461 < _T_1465; // @[pic_ctrl.scala 27:20] + wire [7:0] intpend_id_7 = 8'h7; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_7 = 8'h7; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] intpend_id_6 = 8'h6; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_6 = 8'h6; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] out_id_3 = _T_1572 ? intpend_id_7 : intpend_id_6; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_3 = _T_1572 ? _T_1465 : _T_1461; // @[pic_ctrl.scala 27:49] + wire [3:0] _T_1469 = intpend_w_prior_en_8; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_8 = intpend_w_prior_en_8; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire [3:0] _T_1473 = intpend_w_prior_en_9; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_9 = intpend_w_prior_en_9; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire _T_1574 = _T_1469 < _T_1473; // @[pic_ctrl.scala 27:20] + wire [7:0] intpend_id_9 = 8'h9; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_9 = 8'h9; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] intpend_id_8 = 8'h8; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_8 = 8'h8; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] out_id_4 = _T_1574 ? intpend_id_9 : intpend_id_8; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_4 = _T_1574 ? _T_1473 : _T_1469; // @[pic_ctrl.scala 27:49] + wire [3:0] _T_1477 = intpend_w_prior_en_10; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_10 = intpend_w_prior_en_10; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire [3:0] _T_1481 = intpend_w_prior_en_11; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_11 = intpend_w_prior_en_11; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire _T_1576 = _T_1477 < _T_1481; // @[pic_ctrl.scala 27:20] + wire [7:0] intpend_id_11 = 8'hb; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_11 = 8'hb; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] intpend_id_10 = 8'ha; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_10 = 8'ha; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] out_id_5 = _T_1576 ? intpend_id_11 : intpend_id_10; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_5 = _T_1576 ? _T_1481 : _T_1477; // @[pic_ctrl.scala 27:49] + wire [3:0] _T_1485 = intpend_w_prior_en_12; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_12 = intpend_w_prior_en_12; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire [3:0] _T_1489 = intpend_w_prior_en_13; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_13 = intpend_w_prior_en_13; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire _T_1578 = _T_1485 < _T_1489; // @[pic_ctrl.scala 27:20] + wire [7:0] intpend_id_13 = 8'hd; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_13 = 8'hd; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] intpend_id_12 = 8'hc; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_12 = 8'hc; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] out_id_6 = _T_1578 ? intpend_id_13 : intpend_id_12; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_6 = _T_1578 ? _T_1489 : _T_1485; // @[pic_ctrl.scala 27:49] + wire [3:0] _T_1493 = intpend_w_prior_en_14; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_14 = intpend_w_prior_en_14; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire [3:0] _T_1497 = intpend_w_prior_en_15; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_15 = intpend_w_prior_en_15; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire _T_1580 = _T_1493 < _T_1497; // @[pic_ctrl.scala 27:20] + wire [7:0] intpend_id_15 = 8'hf; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_15 = 8'hf; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] intpend_id_14 = 8'he; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_14 = 8'he; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] out_id_7 = _T_1580 ? intpend_id_15 : intpend_id_14; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_7 = _T_1580 ? _T_1497 : _T_1493; // @[pic_ctrl.scala 27:49] + wire [3:0] _T_1501 = intpend_w_prior_en_16; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_16 = intpend_w_prior_en_16; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire [3:0] _T_1505 = intpend_w_prior_en_17; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_17 = intpend_w_prior_en_17; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire _T_1582 = _T_1501 < _T_1505; // @[pic_ctrl.scala 27:20] + wire [7:0] intpend_id_17 = 8'h11; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_17 = 8'h11; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] intpend_id_16 = 8'h10; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_16 = 8'h10; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] out_id_8 = _T_1582 ? intpend_id_17 : intpend_id_16; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_8 = _T_1582 ? _T_1505 : _T_1501; // @[pic_ctrl.scala 27:49] + wire [3:0] _T_1509 = intpend_w_prior_en_18; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_18 = intpend_w_prior_en_18; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire [3:0] _T_1513 = intpend_w_prior_en_19; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_19 = intpend_w_prior_en_19; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire _T_1584 = _T_1509 < _T_1513; // @[pic_ctrl.scala 27:20] + wire [7:0] intpend_id_19 = 8'h13; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_19 = 8'h13; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] intpend_id_18 = 8'h12; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_18 = 8'h12; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] out_id_9 = _T_1584 ? intpend_id_19 : intpend_id_18; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_9 = _T_1584 ? _T_1513 : _T_1509; // @[pic_ctrl.scala 27:49] + wire [3:0] _T_1517 = intpend_w_prior_en_20; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_20 = intpend_w_prior_en_20; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire [3:0] _T_1521 = intpend_w_prior_en_21; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_21 = intpend_w_prior_en_21; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire _T_1586 = _T_1517 < _T_1521; // @[pic_ctrl.scala 27:20] + wire [7:0] intpend_id_21 = 8'h15; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_21 = 8'h15; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] intpend_id_20 = 8'h14; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_20 = 8'h14; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] out_id_10 = _T_1586 ? intpend_id_21 : intpend_id_20; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_10 = _T_1586 ? _T_1521 : _T_1517; // @[pic_ctrl.scala 27:49] + wire [3:0] _T_1525 = intpend_w_prior_en_22; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_22 = intpend_w_prior_en_22; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire [3:0] _T_1529 = intpend_w_prior_en_23; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_23 = intpend_w_prior_en_23; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire _T_1588 = _T_1525 < _T_1529; // @[pic_ctrl.scala 27:20] + wire [7:0] intpend_id_23 = 8'h17; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_23 = 8'h17; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] intpend_id_22 = 8'h16; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_22 = 8'h16; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] out_id_11 = _T_1588 ? intpend_id_23 : intpend_id_22; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_11 = _T_1588 ? _T_1529 : _T_1525; // @[pic_ctrl.scala 27:49] + wire [3:0] _T_1533 = intpend_w_prior_en_24; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_24 = intpend_w_prior_en_24; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire [3:0] _T_1537 = intpend_w_prior_en_25; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_25 = intpend_w_prior_en_25; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire _T_1590 = _T_1533 < _T_1537; // @[pic_ctrl.scala 27:20] + wire [7:0] intpend_id_25 = 8'h19; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_25 = 8'h19; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] intpend_id_24 = 8'h18; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_24 = 8'h18; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] out_id_12 = _T_1590 ? intpend_id_25 : intpend_id_24; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_12 = _T_1590 ? _T_1537 : _T_1533; // @[pic_ctrl.scala 27:49] + wire [3:0] _T_1541 = intpend_w_prior_en_26; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_26 = intpend_w_prior_en_26; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire [3:0] _T_1545 = intpend_w_prior_en_27; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_27 = intpend_w_prior_en_27; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire _T_1592 = _T_1541 < _T_1545; // @[pic_ctrl.scala 27:20] + wire [7:0] intpend_id_27 = 8'h1b; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_27 = 8'h1b; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] intpend_id_26 = 8'h1a; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_26 = 8'h1a; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] out_id_13 = _T_1592 ? intpend_id_27 : intpend_id_26; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_13 = _T_1592 ? _T_1545 : _T_1541; // @[pic_ctrl.scala 27:49] + wire [3:0] _T_1549 = intpend_w_prior_en_28; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_28 = intpend_w_prior_en_28; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire [3:0] _T_1553 = intpend_w_prior_en_29; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_29 = intpend_w_prior_en_29; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire _T_1594 = _T_1549 < _T_1553; // @[pic_ctrl.scala 27:20] + wire [7:0] intpend_id_29 = 8'h1d; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_29 = 8'h1d; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] intpend_id_28 = 8'h1c; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_28 = 8'h1c; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] out_id_14 = _T_1594 ? intpend_id_29 : intpend_id_28; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_14 = _T_1594 ? _T_1553 : _T_1549; // @[pic_ctrl.scala 27:49] + wire [3:0] _T_1557 = intpend_w_prior_en_30; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_30 = intpend_w_prior_en_30; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire [3:0] _T_1561 = intpend_w_prior_en_31; // @[pic_ctrl.scala 70:42 pic_ctrl.scala 161:64] + wire [3:0] level_intpend_w_prior_en_0_31 = intpend_w_prior_en_31; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire _T_1596 = _T_1557 < _T_1561; // @[pic_ctrl.scala 27:20] + wire [7:0] intpend_id_31 = 8'h1f; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_31 = 8'h1f; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] intpend_id_30 = 8'h1e; // @[pic_ctrl.scala 71:42 pic_ctrl.scala 162:56] + wire [7:0] level_intpend_id_0_30 = 8'h1e; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] out_id_15 = _T_1596 ? intpend_id_31 : intpend_id_30; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_15 = _T_1596 ? _T_1561 : _T_1557; // @[pic_ctrl.scala 27:49] + wire [3:0] level_intpend_w_prior_en_0_32 = 4'h0; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire [3:0] level_intpend_w_prior_en_0_33 = 4'h0; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 220:33] + wire _T_1598 = intpriority_reg_0 < intpriority_reg_0; // @[pic_ctrl.scala 27:20] + wire [7:0] level_intpend_id_0_33 = 8'hff; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] level_intpend_id_0_32 = 8'hff; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 221:33] + wire [7:0] out_id_16 = _T_1598 ? _T_1564 : _T_1564; // @[pic_ctrl.scala 27:9] + wire _T_1600 = out_priority < out_priority_1; // @[pic_ctrl.scala 27:20] + wire [7:0] level_intpend_id_1_1 = out_id_1; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] level_intpend_id_1_0 = out_id; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] out_id_17 = _T_1600 ? level_intpend_id_1_1 : level_intpend_id_1_0; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_17 = _T_1600 ? out_priority_1 : out_priority; // @[pic_ctrl.scala 27:49] + wire _T_1602 = out_priority_2 < out_priority_3; // @[pic_ctrl.scala 27:20] + wire [7:0] level_intpend_id_1_3 = out_id_3; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] level_intpend_id_1_2 = out_id_2; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] out_id_18 = _T_1602 ? level_intpend_id_1_3 : level_intpend_id_1_2; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_18 = _T_1602 ? out_priority_3 : out_priority_2; // @[pic_ctrl.scala 27:49] + wire _T_1604 = out_priority_4 < out_priority_5; // @[pic_ctrl.scala 27:20] + wire [7:0] level_intpend_id_1_5 = out_id_5; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] level_intpend_id_1_4 = out_id_4; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] out_id_19 = _T_1604 ? level_intpend_id_1_5 : level_intpend_id_1_4; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_19 = _T_1604 ? out_priority_5 : out_priority_4; // @[pic_ctrl.scala 27:49] + wire _T_1606 = out_priority_6 < out_priority_7; // @[pic_ctrl.scala 27:20] + wire [7:0] level_intpend_id_1_7 = out_id_7; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] level_intpend_id_1_6 = out_id_6; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] out_id_20 = _T_1606 ? level_intpend_id_1_7 : level_intpend_id_1_6; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_20 = _T_1606 ? out_priority_7 : out_priority_6; // @[pic_ctrl.scala 27:49] + wire _T_1608 = out_priority_8 < out_priority_9; // @[pic_ctrl.scala 27:20] + wire [7:0] level_intpend_id_1_9 = out_id_9; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] level_intpend_id_1_8 = out_id_8; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] out_id_21 = _T_1608 ? level_intpend_id_1_9 : level_intpend_id_1_8; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_21 = _T_1608 ? out_priority_9 : out_priority_8; // @[pic_ctrl.scala 27:49] + wire _T_1610 = out_priority_10 < out_priority_11; // @[pic_ctrl.scala 27:20] + wire [7:0] level_intpend_id_1_11 = out_id_11; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] level_intpend_id_1_10 = out_id_10; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] out_id_22 = _T_1610 ? level_intpend_id_1_11 : level_intpend_id_1_10; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_22 = _T_1610 ? out_priority_11 : out_priority_10; // @[pic_ctrl.scala 27:49] + wire _T_1612 = out_priority_12 < out_priority_13; // @[pic_ctrl.scala 27:20] + wire [7:0] level_intpend_id_1_13 = out_id_13; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] level_intpend_id_1_12 = out_id_12; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] out_id_23 = _T_1612 ? level_intpend_id_1_13 : level_intpend_id_1_12; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_23 = _T_1612 ? out_priority_13 : out_priority_12; // @[pic_ctrl.scala 27:49] + wire _T_1614 = out_priority_14 < out_priority_15; // @[pic_ctrl.scala 27:20] + wire [7:0] level_intpend_id_1_15 = out_id_15; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] level_intpend_id_1_14 = out_id_14; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] out_id_24 = _T_1614 ? level_intpend_id_1_15 : level_intpend_id_1_14; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_24 = _T_1614 ? out_priority_15 : out_priority_14; // @[pic_ctrl.scala 27:49] + wire [7:0] level_intpend_id_1_17 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 229:44] + wire [7:0] level_intpend_id_1_16 = out_id_16; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] out_id_25 = level_intpend_id_1_16; // @[pic_ctrl.scala 27:9] + wire _T_1618 = out_priority_17 < out_priority_18; // @[pic_ctrl.scala 27:20] + wire [7:0] level_intpend_id_2_1 = out_id_18; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] level_intpend_id_2_0 = out_id_17; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] out_id_26 = _T_1618 ? level_intpend_id_2_1 : level_intpend_id_2_0; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_26 = _T_1618 ? out_priority_18 : out_priority_17; // @[pic_ctrl.scala 27:49] + wire _T_1620 = out_priority_19 < out_priority_20; // @[pic_ctrl.scala 27:20] + wire [7:0] level_intpend_id_2_3 = out_id_20; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] level_intpend_id_2_2 = out_id_19; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] out_id_27 = _T_1620 ? level_intpend_id_2_3 : level_intpend_id_2_2; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_27 = _T_1620 ? out_priority_20 : out_priority_19; // @[pic_ctrl.scala 27:49] + wire _T_1622 = out_priority_21 < out_priority_22; // @[pic_ctrl.scala 27:20] + wire [7:0] level_intpend_id_2_5 = out_id_22; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] level_intpend_id_2_4 = out_id_21; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] out_id_28 = _T_1622 ? level_intpend_id_2_5 : level_intpend_id_2_4; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_28 = _T_1622 ? out_priority_22 : out_priority_21; // @[pic_ctrl.scala 27:49] + wire _T_1624 = out_priority_23 < out_priority_24; // @[pic_ctrl.scala 27:20] + wire [7:0] level_intpend_id_2_7 = out_id_24; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] level_intpend_id_2_6 = out_id_23; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] out_id_29 = _T_1624 ? level_intpend_id_2_7 : level_intpend_id_2_6; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_29 = _T_1624 ? out_priority_24 : out_priority_23; // @[pic_ctrl.scala 27:49] + wire [7:0] level_intpend_id_2_9 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 229:44] + wire [7:0] level_intpend_id_2_8 = level_intpend_id_1_16; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] out_id_30 = out_id_25; // @[pic_ctrl.scala 27:9] + wire _T_1628 = out_priority_26 < out_priority_27; // @[pic_ctrl.scala 27:20] + wire [7:0] level_intpend_id_3_1 = out_id_27; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] level_intpend_id_3_0 = out_id_26; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] out_id_31 = _T_1628 ? level_intpend_id_3_1 : level_intpend_id_3_0; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_31 = _T_1628 ? out_priority_27 : out_priority_26; // @[pic_ctrl.scala 27:49] + wire _T_1630 = out_priority_28 < out_priority_29; // @[pic_ctrl.scala 27:20] + wire [7:0] level_intpend_id_3_3 = out_id_29; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] level_intpend_id_3_2 = out_id_28; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] out_id_32 = _T_1630 ? level_intpend_id_3_3 : level_intpend_id_3_2; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_32 = _T_1630 ? out_priority_29 : out_priority_28; // @[pic_ctrl.scala 27:49] + wire [7:0] level_intpend_id_3_5 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 229:44] + wire [7:0] level_intpend_id_3_4 = out_id_25; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] out_id_33 = out_id_30; // @[pic_ctrl.scala 27:9] + wire _T_1634 = out_priority_31 < out_priority_32; // @[pic_ctrl.scala 27:20] + wire [7:0] level_intpend_id_4_1 = out_id_32; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] level_intpend_id_4_0 = out_id_31; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] out_id_34 = _T_1634 ? level_intpend_id_4_1 : level_intpend_id_4_0; // @[pic_ctrl.scala 27:9] + wire [3:0] out_priority_34 = _T_1634 ? out_priority_32 : out_priority_31; // @[pic_ctrl.scala 27:49] + wire [7:0] level_intpend_id_4_3 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 229:44] + wire [7:0] level_intpend_id_4_2 = out_id_30; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire config_reg_we = waddr_config_pic_match & picm_wren_ff; // @[pic_ctrl.scala 249:47] + wire config_reg_re = raddr_config_pic_match & picm_rden_ff; // @[pic_ctrl.scala 250:47] + wire [3:0] level_intpend_w_prior_en_5_0 = out_priority_34; // @[pic_ctrl.scala 213:40 pic_ctrl.scala 217:38 pic_ctrl.scala 233:41] + wire [3:0] selected_int_priority = out_priority_34; // @[pic_ctrl.scala 237:29] + wire [3:0] _T_1641 = ~level_intpend_w_prior_en_5_0; // @[pic_ctrl.scala 261:38] + wire [3:0] pl_in_q = config_reg ? _T_1641 : level_intpend_w_prior_en_5_0; // @[pic_ctrl.scala 261:20] + reg [7:0] _T_1642; // @[pic_ctrl.scala 262:59] + reg [3:0] _T_1643; // @[pic_ctrl.scala 263:54] + wire [3:0] _T_1645 = ~io_dec_pic_dec_tlu_meipt; // @[pic_ctrl.scala 264:40] + wire [3:0] meipt_inv = config_reg ? _T_1645 : io_dec_pic_dec_tlu_meipt; // @[pic_ctrl.scala 264:22] + wire [3:0] _T_1647 = ~io_dec_pic_dec_tlu_meicurpl; // @[pic_ctrl.scala 265:43] + wire [3:0] meicurpl_inv = config_reg ? _T_1647 : io_dec_pic_dec_tlu_meicurpl; // @[pic_ctrl.scala 265:25] + wire _T_1648 = level_intpend_w_prior_en_5_0 > meipt_inv; // @[pic_ctrl.scala 266:47] + wire _T_1649 = level_intpend_w_prior_en_5_0 > meicurpl_inv; // @[pic_ctrl.scala 266:86] + reg _T_1650; // @[pic_ctrl.scala 267:58] + wire [3:0] maxint = config_reg ? 4'h0 : 4'hf; // @[pic_ctrl.scala 268:19] + reg _T_1652; // @[pic_ctrl.scala 270:56] + wire intpend_reg_read = addr_intpend_base_match & picm_rden_ff; // @[pic_ctrl.scala 276:60] wire [9:0] _T_1662 = {extintsrc_req_gw_31,extintsrc_req_gw_30,extintsrc_req_gw_29,extintsrc_req_gw_28,extintsrc_req_gw_27,extintsrc_req_gw_26,extintsrc_req_gw_25,extintsrc_req_gw_24,extintsrc_req_gw_23,extintsrc_req_gw_22}; // @[Cat.scala 29:58] wire [18:0] _T_1671 = {_T_1662,extintsrc_req_gw_21,extintsrc_req_gw_20,extintsrc_req_gw_19,extintsrc_req_gw_18,extintsrc_req_gw_17,extintsrc_req_gw_16,extintsrc_req_gw_15,extintsrc_req_gw_14,extintsrc_req_gw_13}; // @[Cat.scala 29:58] wire [27:0] _T_1680 = {_T_1671,extintsrc_req_gw_12,extintsrc_req_gw_11,extintsrc_req_gw_10,extintsrc_req_gw_9,extintsrc_req_gw_8,extintsrc_req_gw_7,extintsrc_req_gw_6,extintsrc_req_gw_5,extintsrc_req_gw_4}; // @[Cat.scala 29:58] wire [63:0] intpend_reg_extended = {32'h0,_T_1680,extintsrc_req_gw_3,extintsrc_req_gw_2,extintsrc_req_gw_1,1'h0}; // @[Cat.scala 29:58] - wire _T_1687 = picm_raddr_ff[5:2] == 4'h0; // @[pic_ctrl.scala 283:107] - wire _T_1688 = intpend_reg_read & _T_1687; // @[pic_ctrl.scala 283:85] + wire _T_1687 = picm_raddr_ff[5:2] == 4'h0; // @[pic_ctrl.scala 284:107] + wire _T_1688 = intpend_reg_read & _T_1687; // @[pic_ctrl.scala 284:85] wire [31:0] _T_1690 = _T_1688 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] intpend_rd_part_out_0 = _T_1690 & intpend_reg_extended[31:0]; // @[pic_ctrl.scala 283:123] - wire _T_1694 = picm_raddr_ff[5:2] == 4'h1; // @[pic_ctrl.scala 283:107] - wire _T_1695 = intpend_reg_read & _T_1694; // @[pic_ctrl.scala 283:85] + wire [31:0] intpend_rd_part_out_0 = _T_1690 & intpend_reg_extended[31:0]; // @[pic_ctrl.scala 284:123] + wire _T_1694 = picm_raddr_ff[5:2] == 4'h1; // @[pic_ctrl.scala 284:107] + wire _T_1695 = intpend_reg_read & _T_1694; // @[pic_ctrl.scala 284:85] wire [31:0] _T_1697 = _T_1695 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] intpend_rd_part_out_1 = _T_1697 & intpend_reg_extended[63:32]; // @[pic_ctrl.scala 283:123] - wire [31:0] intpend_rd_out = intpend_rd_part_out_0 | intpend_rd_part_out_1; // @[pic_ctrl.scala 284:58] + wire [31:0] intpend_rd_part_out_1 = _T_1697 & intpend_reg_extended[63:32]; // @[pic_ctrl.scala 284:123] + wire [31:0] intpend_rd_out = intpend_rd_part_out_0 | intpend_rd_part_out_1; // @[pic_ctrl.scala 285:58] wire _T_1732 = intenable_reg_re_31 & intenable_reg_31; // @[Mux.scala 98:16] wire _T_1733 = intenable_reg_re_30 ? intenable_reg_30 : _T_1732; // @[Mux.scala 98:16] wire _T_1734 = intenable_reg_re_29 ? intenable_reg_29 : _T_1733; // @[Mux.scala 98:16] @@ -76204,7 +76059,7 @@ module pic_ctrl( wire [31:0] _T_1893 = {31'h0,intenable_rd_out}; // @[Cat.scala 29:58] wire [31:0] _T_1896 = {30'h0,gw_config_rd_out}; // @[Cat.scala 29:58] wire [31:0] _T_1899 = {31'h0,config_reg}; // @[Cat.scala 29:58] - wire [14:0] address = picm_raddr_ff[14:0]; // @[pic_ctrl.scala 305:30] + wire [14:0] address = picm_raddr_ff[14:0]; // @[pic_ctrl.scala 306:30] wire _T_1939 = 15'h3000 == address; // @[Conditional.scala 37:30] wire _T_1940 = 15'h4004 == address; // @[Conditional.scala 37:30] wire _T_1941 = 15'h4008 == address; // @[Conditional.scala 37:30] @@ -76393,9 +76248,9 @@ module pic_ctrl( wire [3:0] _GEN_185 = _T_1941 ? 4'h8 : _GEN_184; // @[Conditional.scala 39:67] wire [3:0] _GEN_186 = _T_1940 ? 4'h8 : _GEN_185; // @[Conditional.scala 39:67] wire [3:0] mask = _T_1939 ? 4'h4 : _GEN_186; // @[Conditional.scala 40:58] - wire _T_1901 = picm_mken_ff & mask[3]; // @[pic_ctrl.scala 298:19] - wire _T_1906 = picm_mken_ff & mask[2]; // @[pic_ctrl.scala 299:19] - wire _T_1911 = picm_mken_ff & mask[1]; // @[pic_ctrl.scala 300:19] + wire _T_1901 = picm_mken_ff & mask[3]; // @[pic_ctrl.scala 299:19] + wire _T_1906 = picm_mken_ff & mask[2]; // @[pic_ctrl.scala 300:19] + wire _T_1911 = picm_mken_ff & mask[1]; // @[pic_ctrl.scala 301:19] wire [31:0] _T_1919 = intpend_reg_read ? intpend_rd_out : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1920 = _T_21 ? _T_1890 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_1921 = _T_24 ? _T_1893 : 32'h0; // @[Mux.scala 27:72] @@ -76411,138 +76266,138 @@ module pic_ctrl( wire [31:0] _T_1932 = _T_1931 | _T_1924; // @[Mux.scala 27:72] wire [31:0] _T_1933 = _T_1932 | _T_1925; // @[Mux.scala 27:72] wire [31:0] picm_rd_data_in = _T_1933 | _T_1926; // @[Mux.scala 27:72] - wire [7:0] level_intpend_id_5_0 = out_id_34; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] level_intpend_id_1_18 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_1_19 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_1_20 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_1_21 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_1_22 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_1_23 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_1_24 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_1_25 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_1_26 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_1_27 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_1_28 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_1_29 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_1_30 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_1_31 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_1_32 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_1_33 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_10 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_11 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_12 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_13 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_14 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_15 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_16 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_17 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_18 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_19 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_20 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_21 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_22 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_23 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_24 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_25 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_26 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_27 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_28 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_29 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_30 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_31 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_32 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_2_33 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_6 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_7 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_8 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_9 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_10 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_11 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_12 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_13 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_14 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_15 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_16 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_17 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_18 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_19 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_20 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_21 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_22 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_23 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_24 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_25 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_26 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_27 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_28 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_29 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_30 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_31 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_32 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_3_33 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_4 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_5 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_6 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_7 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_8 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_9 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_10 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_11 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_12 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_13 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_14 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_15 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_16 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_17 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_18 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_19 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_20 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_21 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_22 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_23 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_24 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_25 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_26 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_27 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_28 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_29 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_30 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_31 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_32 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_4_33 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_1 = out_id_33; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 231:41] - wire [7:0] level_intpend_id_5_2 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30 pic_ctrl.scala 228:44] - wire [7:0] level_intpend_id_5_3 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_4 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_5 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_6 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_7 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_8 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_9 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_10 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_11 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_12 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_13 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_14 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_15 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_16 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_17 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_18 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_19 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_20 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_21 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_22 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_23 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_24 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_25 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_26 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_27 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_28 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_29 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_30 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_31 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_32 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] - wire [7:0] level_intpend_id_5_33 = 8'h0; // @[pic_ctrl.scala 213:32 pic_ctrl.scala 217:30] + wire [7:0] level_intpend_id_5_0 = out_id_34; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] level_intpend_id_1_18 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_1_19 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_1_20 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_1_21 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_1_22 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_1_23 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_1_24 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_1_25 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_1_26 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_1_27 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_1_28 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_1_29 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_1_30 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_1_31 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_1_32 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_1_33 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_10 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_11 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_12 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_13 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_14 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_15 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_16 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_17 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_18 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_19 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_20 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_21 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_22 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_23 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_24 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_25 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_26 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_27 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_28 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_29 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_30 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_31 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_32 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_2_33 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_6 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_7 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_8 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_9 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_10 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_11 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_12 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_13 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_14 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_15 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_16 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_17 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_18 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_19 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_20 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_21 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_22 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_23 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_24 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_25 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_26 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_27 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_28 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_29 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_30 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_31 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_32 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_3_33 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_4 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_5 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_6 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_7 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_8 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_9 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_10 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_11 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_12 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_13 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_14 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_15 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_16 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_17 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_18 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_19 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_20 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_21 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_22 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_23 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_24 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_25 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_26 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_27 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_28 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_29 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_30 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_31 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_32 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_4_33 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_1 = out_id_33; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 232:41] + wire [7:0] level_intpend_id_5_2 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30 pic_ctrl.scala 229:44] + wire [7:0] level_intpend_id_5_3 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_4 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_5 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_6 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_7 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_8 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_9 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_10 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_11 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_12 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_13 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_14 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_15 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_16 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_17 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_18 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_19 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_20 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_21 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_22 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_23 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_24 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_25 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_26 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_27 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_28 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_29 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_30 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_31 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_32 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] + wire [7:0] level_intpend_id_5_33 = 8'h0; // @[pic_ctrl.scala 214:32 pic_ctrl.scala 218:30] rvclkhdr rvclkhdr ( // @[lib.scala 327:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -76573,11 +76428,11 @@ module pic_ctrl( .io_en(rvclkhdr_4_io_en), .io_scan_mode(rvclkhdr_4_io_scan_mode) ); - assign io_lsu_pic_picm_rd_data = picm_bypass_ff ? picm_wr_data_ff : picm_rd_data_in; // @[pic_ctrl.scala 304:27] - assign io_mexintpend = _T_1650; // @[pic_ctrl.scala 266:17] - assign io_claimid = _T_1642; // @[pic_ctrl.scala 261:37] - assign io_pl = _T_1643; // @[pic_ctrl.scala 262:32] - assign io_mhwakeup = _T_1652; // @[pic_ctrl.scala 269:15] + assign io_lsu_pic_picm_rd_data = picm_bypass_ff ? picm_wr_data_ff : picm_rd_data_in; // @[pic_ctrl.scala 305:27] + assign io_dec_pic_pic_claimid = _T_1642; // @[pic_ctrl.scala 262:49] + assign io_dec_pic_pic_pl = _T_1643; // @[pic_ctrl.scala 263:44] + assign io_dec_pic_mhwakeup = _T_1652; // @[pic_ctrl.scala 270:23] + assign io_dec_pic_mexintpend = _T_1650; // @[pic_ctrl.scala 267:25] assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17] assign rvclkhdr_io_en = _T_19 | io_clk_override; // @[lib.scala 329:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 330:23] @@ -78300,38 +78155,34 @@ module dma_ctrl( input [1:0] io_dbg_dma_dbg_dctl_dbg_cmd_wrdata, input io_dbg_dma_io_dbg_dma_bubble, output io_dbg_dma_io_dma_dbg_ready, + output io_dec_dma_dctl_dma_dma_dccm_stall_any, + output io_dec_dma_tlu_dma_dma_pmu_dccm_read, + output io_dec_dma_tlu_dma_dma_pmu_dccm_write, + output io_dec_dma_tlu_dma_dma_pmu_any_read, + output io_dec_dma_tlu_dma_dma_pmu_any_write, + input [2:0] io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty, + output io_dec_dma_tlu_dma_dma_dccm_stall_any, + output io_dec_dma_tlu_dma_dma_iccm_stall_any, input io_iccm_dma_rvalid, input io_iccm_dma_ecc_error, input [2:0] io_iccm_dma_rtag, input [63:0] io_iccm_dma_rdata, - output io_dma_dccm_stall_any, input io_iccm_ready, - input [2:0] io_dec_tlu_dma_qos_prty, - output io_dma_pmu_dccm_read, - output io_dma_pmu_dccm_write, - output io_dma_pmu_any_read, - output io_dma_pmu_any_write, output io_dma_axi_aw_ready, input io_dma_axi_aw_valid, - input io_dma_axi_aw_bits_id, input [31:0] io_dma_axi_aw_bits_addr, input [2:0] io_dma_axi_aw_bits_size, output io_dma_axi_w_ready, input io_dma_axi_w_valid, input [63:0] io_dma_axi_w_bits_data, input [7:0] io_dma_axi_w_bits_strb, - input io_dma_axi_b_ready, output io_dma_axi_b_valid, output [1:0] io_dma_axi_b_bits_resp, - output io_dma_axi_b_bits_id, output io_dma_axi_ar_ready, input io_dma_axi_ar_valid, - input io_dma_axi_ar_bits_id, input [31:0] io_dma_axi_ar_bits_addr, input [2:0] io_dma_axi_ar_bits_size, - input io_dma_axi_r_ready, output io_dma_axi_r_valid, - output io_dma_axi_r_bits_id, output [63:0] io_dma_axi_r_bits_data, output [1:0] io_dma_axi_r_bits_resp, output io_lsu_dma_dma_lsc_ctl_dma_dccm_req, @@ -78428,13 +78279,6 @@ module dma_ctrl( reg [63:0] _RAND_69; reg [31:0] _RAND_70; reg [31:0] _RAND_71; - reg [31:0] _RAND_72; - reg [31:0] _RAND_73; - reg [31:0] _RAND_74; - reg [31:0] _RAND_75; - reg [31:0] _RAND_76; - reg [31:0] _RAND_77; - reg [31:0] _RAND_78; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[lib.scala 352:23] wire rvclkhdr_io_clk; // @[lib.scala 352:23] @@ -78476,18 +78320,18 @@ module dma_ctrl( wire rvclkhdr_9_io_clk; // @[lib.scala 352:23] wire rvclkhdr_9_io_en; // @[lib.scala 352:23] wire rvclkhdr_9_io_scan_mode; // @[lib.scala 352:23] - wire dma_buffer_c1cgc_io_l1clk; // @[dma_ctrl.scala 390:32] - wire dma_buffer_c1cgc_io_clk; // @[dma_ctrl.scala 390:32] - wire dma_buffer_c1cgc_io_en; // @[dma_ctrl.scala 390:32] - wire dma_buffer_c1cgc_io_scan_mode; // @[dma_ctrl.scala 390:32] - wire dma_free_cgc_io_l1clk; // @[dma_ctrl.scala 396:28] - wire dma_free_cgc_io_clk; // @[dma_ctrl.scala 396:28] - wire dma_free_cgc_io_en; // @[dma_ctrl.scala 396:28] - wire dma_free_cgc_io_scan_mode; // @[dma_ctrl.scala 396:28] - wire dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 402:27] - wire dma_bus_cgc_io_clk; // @[dma_ctrl.scala 402:27] - wire dma_bus_cgc_io_en; // @[dma_ctrl.scala 402:27] - wire dma_bus_cgc_io_scan_mode; // @[dma_ctrl.scala 402:27] + wire dma_buffer_c1cgc_io_l1clk; // @[dma_ctrl.scala 385:32] + wire dma_buffer_c1cgc_io_clk; // @[dma_ctrl.scala 385:32] + wire dma_buffer_c1cgc_io_en; // @[dma_ctrl.scala 385:32] + wire dma_buffer_c1cgc_io_scan_mode; // @[dma_ctrl.scala 385:32] + wire dma_free_cgc_io_l1clk; // @[dma_ctrl.scala 391:28] + wire dma_free_cgc_io_clk; // @[dma_ctrl.scala 391:28] + wire dma_free_cgc_io_en; // @[dma_ctrl.scala 391:28] + wire dma_free_cgc_io_scan_mode; // @[dma_ctrl.scala 391:28] + wire dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 397:27] + wire dma_bus_cgc_io_clk; // @[dma_ctrl.scala 397:27] + wire dma_bus_cgc_io_en; // @[dma_ctrl.scala 397:27] + wire dma_bus_cgc_io_scan_mode; // @[dma_ctrl.scala 397:27] wire rvclkhdr_10_io_l1clk; // @[lib.scala 352:23] wire rvclkhdr_10_io_clk; // @[lib.scala 352:23] wire rvclkhdr_10_io_en; // @[lib.scala 352:23] @@ -78500,395 +78344,393 @@ module dma_ctrl( wire rvclkhdr_12_io_clk; // @[lib.scala 352:23] wire rvclkhdr_12_io_en; // @[lib.scala 352:23] wire rvclkhdr_12_io_scan_mode; // @[lib.scala 352:23] - wire dma_free_clk = dma_free_cgc_io_l1clk; // @[dma_ctrl.scala 174:26 dma_ctrl.scala 400:29] + wire dma_free_clk = dma_free_cgc_io_l1clk; // @[dma_ctrl.scala 168:26 dma_ctrl.scala 395:29] reg [2:0] RdPtr; // @[Reg.scala 27:20] reg [31:0] fifo_addr_4; // @[lib.scala 358:16] reg [31:0] fifo_addr_3; // @[lib.scala 358:16] reg [31:0] fifo_addr_2; // @[lib.scala 358:16] reg [31:0] fifo_addr_1; // @[lib.scala 358:16] reg [31:0] fifo_addr_0; // @[lib.scala 358:16] - wire [31:0] _GEN_60 = 3'h1 == RdPtr ? fifo_addr_1 : fifo_addr_0; // @[dma_ctrl.scala 356:20] - wire [31:0] _GEN_61 = 3'h2 == RdPtr ? fifo_addr_2 : _GEN_60; // @[dma_ctrl.scala 356:20] - wire [31:0] _GEN_62 = 3'h3 == RdPtr ? fifo_addr_3 : _GEN_61; // @[dma_ctrl.scala 356:20] - wire [31:0] dma_mem_addr_int = 3'h4 == RdPtr ? fifo_addr_4 : _GEN_62; // @[dma_ctrl.scala 356:20] + wire [31:0] _GEN_60 = 3'h1 == RdPtr ? fifo_addr_1 : fifo_addr_0; // @[dma_ctrl.scala 351:20] + wire [31:0] _GEN_61 = 3'h2 == RdPtr ? fifo_addr_2 : _GEN_60; // @[dma_ctrl.scala 351:20] + wire [31:0] _GEN_62 = 3'h3 == RdPtr ? fifo_addr_3 : _GEN_61; // @[dma_ctrl.scala 351:20] + wire [31:0] dma_mem_addr_int = 3'h4 == RdPtr ? fifo_addr_4 : _GEN_62; // @[dma_ctrl.scala 351:20] wire dma_mem_addr_in_dccm = dma_mem_addr_int[31:16] == 16'hf004; // @[lib.scala 345:39] wire dma_mem_addr_in_pic = dma_mem_addr_int[31:15] == 17'h1e018; // @[lib.scala 345:39] wire dma_mem_addr_in_iccm = dma_mem_addr_int[31:16] == 16'hee00; // @[lib.scala 345:39] - wire dma_bus_clk = dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 176:25 dma_ctrl.scala 406:28] - reg wrbuf_vld; // @[dma_ctrl.scala 416:59] - reg wrbuf_data_vld; // @[dma_ctrl.scala 418:59] - wire _T_1240 = wrbuf_vld & wrbuf_data_vld; // @[dma_ctrl.scala 474:43] - reg rdbuf_vld; // @[dma_ctrl.scala 442:47] - wire _T_1241 = _T_1240 & rdbuf_vld; // @[dma_ctrl.scala 474:60] + wire dma_bus_clk = dma_bus_cgc_io_l1clk; // @[dma_ctrl.scala 170:25 dma_ctrl.scala 401:28] + reg wrbuf_vld; // @[dma_ctrl.scala 411:59] + reg wrbuf_data_vld; // @[dma_ctrl.scala 413:59] + wire _T_1240 = wrbuf_vld & wrbuf_data_vld; // @[dma_ctrl.scala 469:43] + reg rdbuf_vld; // @[dma_ctrl.scala 437:47] + wire _T_1241 = _T_1240 & rdbuf_vld; // @[dma_ctrl.scala 469:60] reg axi_mstr_priority; // @[Reg.scala 27:20] - wire axi_mstr_sel = _T_1241 ? axi_mstr_priority : _T_1240; // @[dma_ctrl.scala 474:31] + wire axi_mstr_sel = _T_1241 ? axi_mstr_priority : _T_1240; // @[dma_ctrl.scala 469:31] reg [31:0] wrbuf_addr; // @[lib.scala 358:16] reg [31:0] rdbuf_addr; // @[lib.scala 358:16] - wire [31:0] bus_cmd_addr = axi_mstr_sel ? wrbuf_addr : rdbuf_addr; // @[dma_ctrl.scala 464:43] - wire [2:0] _GEN_90 = {{2'd0}, io_dbg_dma_dbg_ib_dbg_cmd_addr[2]}; // @[dma_ctrl.scala 201:91] - wire [3:0] _T_17 = 3'h4 * _GEN_90; // @[dma_ctrl.scala 201:91] - wire [18:0] _T_18 = 19'hf << _T_17; // @[dma_ctrl.scala 201:83] + wire [31:0] bus_cmd_addr = axi_mstr_sel ? wrbuf_addr : rdbuf_addr; // @[dma_ctrl.scala 459:43] + wire [2:0] _GEN_90 = {{2'd0}, io_dbg_dma_dbg_ib_dbg_cmd_addr[2]}; // @[dma_ctrl.scala 195:91] + wire [3:0] _T_17 = 3'h4 * _GEN_90; // @[dma_ctrl.scala 195:91] + wire [18:0] _T_18 = 19'hf << _T_17; // @[dma_ctrl.scala 195:83] reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] - wire [18:0] _T_20 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_18 : {{11'd0}, wrbuf_byteen}; // @[dma_ctrl.scala 201:34] + wire [18:0] _T_20 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_18 : {{11'd0}, wrbuf_byteen}; // @[dma_ctrl.scala 195:34] wire [2:0] _T_23 = {1'h0,io_dbg_cmd_size}; // @[Cat.scala 29:58] reg [2:0] wrbuf_sz; // @[Reg.scala 27:20] reg [2:0] rdbuf_sz; // @[Reg.scala 27:20] - wire [2:0] bus_cmd_sz = axi_mstr_sel ? wrbuf_sz : rdbuf_sz; // @[dma_ctrl.scala 465:45] - wire [2:0] fifo_sz_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_23 : bus_cmd_sz; // @[dma_ctrl.scala 203:33] - wire fifo_write_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? io_dbg_dma_dbg_ib_dbg_cmd_write : axi_mstr_sel; // @[dma_ctrl.scala 205:33] - wire bus_cmd_valid = _T_1240 | rdbuf_vld; // @[dma_ctrl.scala 460:69] - reg fifo_full; // @[dma_ctrl.scala 374:12] - reg dbg_dma_bubble_bus; // @[dma_ctrl.scala 378:12] - wire _T_989 = fifo_full | dbg_dma_bubble_bus; // @[dma_ctrl.scala 305:39] - wire dma_fifo_ready = ~_T_989; // @[dma_ctrl.scala 305:27] - wire axi_mstr_prty_en = bus_cmd_valid & dma_fifo_ready; // @[dma_ctrl.scala 461:54] - wire _T_28 = axi_mstr_prty_en & io_dma_bus_clk_en; // @[dma_ctrl.scala 212:80] - wire _T_31 = io_dbg_dma_dbg_ib_dbg_cmd_valid & io_dbg_dma_dbg_ib_dbg_cmd_type[1]; // @[dma_ctrl.scala 212:136] - wire _T_32 = _T_28 | _T_31; // @[dma_ctrl.scala 212:101] + wire [2:0] bus_cmd_sz = axi_mstr_sel ? wrbuf_sz : rdbuf_sz; // @[dma_ctrl.scala 460:45] + wire [2:0] fifo_sz_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? _T_23 : bus_cmd_sz; // @[dma_ctrl.scala 197:33] + wire fifo_write_in = io_dbg_dma_dbg_ib_dbg_cmd_valid ? io_dbg_dma_dbg_ib_dbg_cmd_write : axi_mstr_sel; // @[dma_ctrl.scala 199:33] + wire bus_cmd_valid = _T_1240 | rdbuf_vld; // @[dma_ctrl.scala 455:69] + reg fifo_full; // @[dma_ctrl.scala 369:12] + reg dbg_dma_bubble_bus; // @[dma_ctrl.scala 373:12] + wire _T_989 = fifo_full | dbg_dma_bubble_bus; // @[dma_ctrl.scala 299:39] + wire dma_fifo_ready = ~_T_989; // @[dma_ctrl.scala 299:27] + wire axi_mstr_prty_en = bus_cmd_valid & dma_fifo_ready; // @[dma_ctrl.scala 456:54] + wire _T_28 = axi_mstr_prty_en & io_dma_bus_clk_en; // @[dma_ctrl.scala 206:80] + wire _T_31 = io_dbg_dma_dbg_ib_dbg_cmd_valid & io_dbg_dma_dbg_ib_dbg_cmd_type[1]; // @[dma_ctrl.scala 206:136] + wire _T_32 = _T_28 | _T_31; // @[dma_ctrl.scala 206:101] reg [2:0] WrPtr; // @[Reg.scala 27:20] - wire _T_33 = 3'h0 == WrPtr; // @[dma_ctrl.scala 212:188] - wire _T_34 = _T_32 & _T_33; // @[dma_ctrl.scala 212:181] - wire _T_41 = 3'h1 == WrPtr; // @[dma_ctrl.scala 212:188] - wire _T_42 = _T_32 & _T_41; // @[dma_ctrl.scala 212:181] - wire _T_49 = 3'h2 == WrPtr; // @[dma_ctrl.scala 212:188] - wire _T_50 = _T_32 & _T_49; // @[dma_ctrl.scala 212:181] - wire _T_57 = 3'h3 == WrPtr; // @[dma_ctrl.scala 212:188] - wire _T_58 = _T_32 & _T_57; // @[dma_ctrl.scala 212:181] - wire _T_65 = 3'h4 == WrPtr; // @[dma_ctrl.scala 212:188] - wire _T_66 = _T_32 & _T_65; // @[dma_ctrl.scala 212:181] + wire _T_33 = 3'h0 == WrPtr; // @[dma_ctrl.scala 206:188] + wire _T_34 = _T_32 & _T_33; // @[dma_ctrl.scala 206:181] + wire _T_41 = 3'h1 == WrPtr; // @[dma_ctrl.scala 206:188] + wire _T_42 = _T_32 & _T_41; // @[dma_ctrl.scala 206:181] + wire _T_49 = 3'h2 == WrPtr; // @[dma_ctrl.scala 206:188] + wire _T_50 = _T_32 & _T_49; // @[dma_ctrl.scala 206:181] + wire _T_57 = 3'h3 == WrPtr; // @[dma_ctrl.scala 206:188] + wire _T_58 = _T_32 & _T_57; // @[dma_ctrl.scala 206:181] + wire _T_65 = 3'h4 == WrPtr; // @[dma_ctrl.scala 206:188] + wire _T_66 = _T_32 & _T_65; // @[dma_ctrl.scala 206:181] wire [4:0] fifo_cmd_en = {_T_66,_T_58,_T_50,_T_42,_T_34}; // @[Cat.scala 29:58] - wire _T_71 = axi_mstr_prty_en & fifo_write_in; // @[dma_ctrl.scala 214:73] - wire _T_72 = _T_71 & io_dma_bus_clk_en; // @[dma_ctrl.scala 214:89] - wire _T_75 = _T_31 & io_dbg_dma_dbg_ib_dbg_cmd_write; // @[dma_ctrl.scala 214:181] - wire _T_76 = _T_72 | _T_75; // @[dma_ctrl.scala 214:110] - wire _T_78 = _T_76 & _T_33; // @[dma_ctrl.scala 214:217] - reg _T_598; // @[dma_ctrl.scala 232:82] - reg _T_591; // @[dma_ctrl.scala 232:82] - reg _T_584; // @[dma_ctrl.scala 232:82] - reg _T_577; // @[dma_ctrl.scala 232:82] - reg _T_570; // @[dma_ctrl.scala 232:82] + wire _T_71 = axi_mstr_prty_en & fifo_write_in; // @[dma_ctrl.scala 208:73] + wire _T_72 = _T_71 & io_dma_bus_clk_en; // @[dma_ctrl.scala 208:89] + wire _T_75 = _T_31 & io_dbg_dma_dbg_ib_dbg_cmd_write; // @[dma_ctrl.scala 208:181] + wire _T_76 = _T_72 | _T_75; // @[dma_ctrl.scala 208:110] + wire _T_78 = _T_76 & _T_33; // @[dma_ctrl.scala 208:217] + reg _T_598; // @[dma_ctrl.scala 226:82] + reg _T_591; // @[dma_ctrl.scala 226:82] + reg _T_584; // @[dma_ctrl.scala 226:82] + reg _T_577; // @[dma_ctrl.scala 226:82] + reg _T_570; // @[dma_ctrl.scala 226:82] wire [4:0] fifo_valid = {_T_598,_T_591,_T_584,_T_577,_T_570}; // @[Cat.scala 29:58] - wire [4:0] _T_990 = fifo_valid >> RdPtr; // @[dma_ctrl.scala 309:38] - reg _T_760; // @[dma_ctrl.scala 240:89] - reg _T_753; // @[dma_ctrl.scala 240:89] - reg _T_746; // @[dma_ctrl.scala 240:89] - reg _T_739; // @[dma_ctrl.scala 240:89] - reg _T_732; // @[dma_ctrl.scala 240:89] + wire [4:0] _T_990 = fifo_valid >> RdPtr; // @[dma_ctrl.scala 303:38] + reg _T_760; // @[dma_ctrl.scala 234:89] + reg _T_753; // @[dma_ctrl.scala 234:89] + reg _T_746; // @[dma_ctrl.scala 234:89] + reg _T_739; // @[dma_ctrl.scala 234:89] + reg _T_732; // @[dma_ctrl.scala 234:89] wire [4:0] fifo_done = {_T_760,_T_753,_T_746,_T_739,_T_732}; // @[Cat.scala 29:58] - wire [4:0] _T_992 = fifo_done >> RdPtr; // @[dma_ctrl.scala 309:58] - wire _T_994 = ~_T_992[0]; // @[dma_ctrl.scala 309:48] - wire _T_995 = _T_990[0] & _T_994; // @[dma_ctrl.scala 309:46] - wire dma_buffer_c1_clk = dma_buffer_c1cgc_io_l1clk; // @[dma_ctrl.scala 178:31 dma_ctrl.scala 394:33] + wire [4:0] _T_992 = fifo_done >> RdPtr; // @[dma_ctrl.scala 303:58] + wire _T_994 = ~_T_992[0]; // @[dma_ctrl.scala 303:48] + wire _T_995 = _T_990[0] & _T_994; // @[dma_ctrl.scala 303:46] + wire dma_buffer_c1_clk = dma_buffer_c1cgc_io_l1clk; // @[dma_ctrl.scala 172:31 dma_ctrl.scala 389:33] reg _T_886; // @[Reg.scala 27:20] reg _T_884; // @[Reg.scala 27:20] reg _T_882; // @[Reg.scala 27:20] reg _T_880; // @[Reg.scala 27:20] reg _T_878; // @[Reg.scala 27:20] wire [4:0] fifo_dbg = {_T_886,_T_884,_T_882,_T_880,_T_878}; // @[Cat.scala 29:58] - wire [4:0] _T_996 = fifo_dbg >> RdPtr; // @[dma_ctrl.scala 309:77] - wire _T_998 = ~_T_996[0]; // @[dma_ctrl.scala 309:68] - wire _T_999 = _T_995 & _T_998; // @[dma_ctrl.scala 309:66] - wire _T_1000 = dma_mem_addr_in_dccm | dma_mem_addr_in_iccm; // @[dma_ctrl.scala 309:111] - wire _T_1001 = ~_T_1000; // @[dma_ctrl.scala 309:88] - wire dma_address_error = _T_999 & _T_1001; // @[dma_ctrl.scala 309:85] - wire _T_1009 = ~dma_address_error; // @[dma_ctrl.scala 310:68] - wire _T_1010 = _T_995 & _T_1009; // @[dma_ctrl.scala 310:66] + wire [4:0] _T_996 = fifo_dbg >> RdPtr; // @[dma_ctrl.scala 303:77] + wire _T_998 = ~_T_996[0]; // @[dma_ctrl.scala 303:68] + wire _T_999 = _T_995 & _T_998; // @[dma_ctrl.scala 303:66] + wire _T_1000 = dma_mem_addr_in_dccm | dma_mem_addr_in_iccm; // @[dma_ctrl.scala 303:111] + wire _T_1001 = ~_T_1000; // @[dma_ctrl.scala 303:88] + wire dma_address_error = _T_999 & _T_1001; // @[dma_ctrl.scala 303:85] + wire _T_1009 = ~dma_address_error; // @[dma_ctrl.scala 304:68] + wire _T_1010 = _T_995 & _T_1009; // @[dma_ctrl.scala 304:66] reg [2:0] fifo_sz_4; // @[Reg.scala 27:20] reg [2:0] fifo_sz_3; // @[Reg.scala 27:20] reg [2:0] fifo_sz_2; // @[Reg.scala 27:20] reg [2:0] fifo_sz_1; // @[Reg.scala 27:20] reg [2:0] fifo_sz_0; // @[Reg.scala 27:20] - wire [2:0] _GEN_65 = 3'h1 == RdPtr ? fifo_sz_1 : fifo_sz_0; // @[dma_ctrl.scala 357:20] - wire [2:0] _GEN_66 = 3'h2 == RdPtr ? fifo_sz_2 : _GEN_65; // @[dma_ctrl.scala 357:20] - wire [2:0] _GEN_67 = 3'h3 == RdPtr ? fifo_sz_3 : _GEN_66; // @[dma_ctrl.scala 357:20] - wire [2:0] dma_mem_sz_int = 3'h4 == RdPtr ? fifo_sz_4 : _GEN_67; // @[dma_ctrl.scala 357:20] - wire _T_1012 = dma_mem_sz_int == 3'h1; // @[dma_ctrl.scala 311:28] - wire _T_1014 = _T_1012 & dma_mem_addr_int[0]; // @[dma_ctrl.scala 311:37] - wire _T_1016 = dma_mem_sz_int == 3'h2; // @[dma_ctrl.scala 312:29] - wire _T_1018 = |dma_mem_addr_int[1:0]; // @[dma_ctrl.scala 312:64] - wire _T_1019 = _T_1016 & _T_1018; // @[dma_ctrl.scala 312:38] - wire _T_1020 = _T_1014 | _T_1019; // @[dma_ctrl.scala 311:60] - wire _T_1022 = dma_mem_sz_int == 3'h3; // @[dma_ctrl.scala 313:29] - wire _T_1024 = |dma_mem_addr_int[2:0]; // @[dma_ctrl.scala 313:64] - wire _T_1025 = _T_1022 & _T_1024; // @[dma_ctrl.scala 313:38] - wire _T_1026 = _T_1020 | _T_1025; // @[dma_ctrl.scala 312:70] - wire _T_1028 = dma_mem_sz_int[1:0] == 2'h2; // @[dma_ctrl.scala 314:55] - wire _T_1030 = dma_mem_sz_int[1:0] == 2'h3; // @[dma_ctrl.scala 314:88] - wire _T_1031 = _T_1028 | _T_1030; // @[dma_ctrl.scala 314:64] - wire _T_1032 = ~_T_1031; // @[dma_ctrl.scala 314:31] - wire _T_1033 = dma_mem_addr_in_iccm & _T_1032; // @[dma_ctrl.scala 314:29] - wire _T_1034 = _T_1026 | _T_1033; // @[dma_ctrl.scala 313:70] - wire _T_1035 = dma_mem_addr_in_dccm & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 315:29] - wire _T_1042 = _T_1035 & _T_1032; // @[dma_ctrl.scala 315:68] - wire _T_1043 = _T_1034 | _T_1042; // @[dma_ctrl.scala 314:108] - wire _T_1046 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1016; // @[dma_ctrl.scala 316:45] - wire _T_1048 = dma_mem_addr_int[2:0] == 3'h0; // @[dma_ctrl.scala 316:114] + wire [2:0] _GEN_65 = 3'h1 == RdPtr ? fifo_sz_1 : fifo_sz_0; // @[dma_ctrl.scala 352:20] + wire [2:0] _GEN_66 = 3'h2 == RdPtr ? fifo_sz_2 : _GEN_65; // @[dma_ctrl.scala 352:20] + wire [2:0] _GEN_67 = 3'h3 == RdPtr ? fifo_sz_3 : _GEN_66; // @[dma_ctrl.scala 352:20] + wire [2:0] dma_mem_sz_int = 3'h4 == RdPtr ? fifo_sz_4 : _GEN_67; // @[dma_ctrl.scala 352:20] + wire _T_1012 = dma_mem_sz_int == 3'h1; // @[dma_ctrl.scala 305:28] + wire _T_1014 = _T_1012 & dma_mem_addr_int[0]; // @[dma_ctrl.scala 305:37] + wire _T_1016 = dma_mem_sz_int == 3'h2; // @[dma_ctrl.scala 306:29] + wire _T_1018 = |dma_mem_addr_int[1:0]; // @[dma_ctrl.scala 306:64] + wire _T_1019 = _T_1016 & _T_1018; // @[dma_ctrl.scala 306:38] + wire _T_1020 = _T_1014 | _T_1019; // @[dma_ctrl.scala 305:60] + wire _T_1022 = dma_mem_sz_int == 3'h3; // @[dma_ctrl.scala 307:29] + wire _T_1024 = |dma_mem_addr_int[2:0]; // @[dma_ctrl.scala 307:64] + wire _T_1025 = _T_1022 & _T_1024; // @[dma_ctrl.scala 307:38] + wire _T_1026 = _T_1020 | _T_1025; // @[dma_ctrl.scala 306:70] + wire _T_1028 = dma_mem_sz_int[1:0] == 2'h2; // @[dma_ctrl.scala 308:55] + wire _T_1030 = dma_mem_sz_int[1:0] == 2'h3; // @[dma_ctrl.scala 308:88] + wire _T_1031 = _T_1028 | _T_1030; // @[dma_ctrl.scala 308:64] + wire _T_1032 = ~_T_1031; // @[dma_ctrl.scala 308:31] + wire _T_1033 = dma_mem_addr_in_iccm & _T_1032; // @[dma_ctrl.scala 308:29] + wire _T_1034 = _T_1026 | _T_1033; // @[dma_ctrl.scala 307:70] + wire _T_1035 = dma_mem_addr_in_dccm & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 309:29] + wire _T_1042 = _T_1035 & _T_1032; // @[dma_ctrl.scala 309:68] + wire _T_1043 = _T_1034 | _T_1042; // @[dma_ctrl.scala 308:108] + wire _T_1046 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1016; // @[dma_ctrl.scala 310:45] + wire _T_1048 = dma_mem_addr_int[2:0] == 3'h0; // @[dma_ctrl.scala 310:114] reg [7:0] fifo_byteen_4; // @[Reg.scala 27:20] reg [7:0] fifo_byteen_3; // @[Reg.scala 27:20] reg [7:0] fifo_byteen_2; // @[Reg.scala 27:20] reg [7:0] fifo_byteen_1; // @[Reg.scala 27:20] reg [7:0] fifo_byteen_0; // @[Reg.scala 27:20] - wire [7:0] _GEN_70 = 3'h1 == RdPtr ? fifo_byteen_1 : fifo_byteen_0; // @[dma_ctrl.scala 360:20] - wire [7:0] _GEN_71 = 3'h2 == RdPtr ? fifo_byteen_2 : _GEN_70; // @[dma_ctrl.scala 360:20] - wire [7:0] _GEN_72 = 3'h3 == RdPtr ? fifo_byteen_3 : _GEN_71; // @[dma_ctrl.scala 360:20] - wire [7:0] dma_mem_byteen = 3'h4 == RdPtr ? fifo_byteen_4 : _GEN_72; // @[dma_ctrl.scala 360:20] + wire [7:0] _GEN_70 = 3'h1 == RdPtr ? fifo_byteen_1 : fifo_byteen_0; // @[dma_ctrl.scala 355:20] + wire [7:0] _GEN_71 = 3'h2 == RdPtr ? fifo_byteen_2 : _GEN_70; // @[dma_ctrl.scala 355:20] + wire [7:0] _GEN_72 = 3'h3 == RdPtr ? fifo_byteen_3 : _GEN_71; // @[dma_ctrl.scala 355:20] + wire [7:0] dma_mem_byteen = 3'h4 == RdPtr ? fifo_byteen_4 : _GEN_72; // @[dma_ctrl.scala 355:20] wire [3:0] _T_1059 = _T_1048 ? dma_mem_byteen[3:0] : 4'h0; // @[Mux.scala 27:72] - wire _T_1051 = dma_mem_addr_int[2:0] == 3'h1; // @[dma_ctrl.scala 317:32] + wire _T_1051 = dma_mem_addr_int[2:0] == 3'h1; // @[dma_ctrl.scala 311:32] wire [3:0] _T_1060 = _T_1051 ? dma_mem_byteen[4:1] : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_1063 = _T_1059 | _T_1060; // @[Mux.scala 27:72] - wire _T_1054 = dma_mem_addr_int[2:0] == 3'h2; // @[dma_ctrl.scala 318:32] + wire _T_1054 = dma_mem_addr_int[2:0] == 3'h2; // @[dma_ctrl.scala 312:32] wire [3:0] _T_1061 = _T_1054 ? dma_mem_byteen[5:2] : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_1064 = _T_1063 | _T_1061; // @[Mux.scala 27:72] - wire _T_1057 = dma_mem_addr_int[2:0] == 3'h3; // @[dma_ctrl.scala 319:32] + wire _T_1057 = dma_mem_addr_int[2:0] == 3'h3; // @[dma_ctrl.scala 313:32] wire [3:0] _T_1062 = _T_1057 ? dma_mem_byteen[6:3] : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_1065 = _T_1064 | _T_1062; // @[Mux.scala 27:72] - wire _T_1067 = _T_1065 != 4'hf; // @[dma_ctrl.scala 319:68] - wire _T_1068 = _T_1046 & _T_1067; // @[dma_ctrl.scala 316:78] - wire _T_1069 = _T_1043 | _T_1068; // @[dma_ctrl.scala 315:145] - wire _T_1072 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1022; // @[dma_ctrl.scala 320:45] - wire _T_1074 = dma_mem_byteen == 8'hf; // @[dma_ctrl.scala 320:103] - wire _T_1076 = dma_mem_byteen == 8'hf0; // @[dma_ctrl.scala 320:139] - wire _T_1077 = _T_1074 | _T_1076; // @[dma_ctrl.scala 320:116] - wire _T_1079 = dma_mem_byteen == 8'hff; // @[dma_ctrl.scala 320:175] - wire _T_1080 = _T_1077 | _T_1079; // @[dma_ctrl.scala 320:152] - wire _T_1081 = ~_T_1080; // @[dma_ctrl.scala 320:80] - wire _T_1082 = _T_1072 & _T_1081; // @[dma_ctrl.scala 320:78] - wire _T_1083 = _T_1069 | _T_1082; // @[dma_ctrl.scala 319:79] - wire dma_alignment_error = _T_1010 & _T_1083; // @[dma_ctrl.scala 310:87] - wire _T_79 = dma_address_error | dma_alignment_error; // @[dma_ctrl.scala 214:258] - wire _T_80 = 3'h0 == RdPtr; // @[dma_ctrl.scala 214:288] - wire _T_81 = _T_79 & _T_80; // @[dma_ctrl.scala 214:281] - wire _T_82 = _T_78 | _T_81; // @[dma_ctrl.scala 214:236] - wire _T_83 = 3'h0 == io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[dma_ctrl.scala 214:350] - wire _T_84 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_83; // @[dma_ctrl.scala 214:343] - wire _T_85 = _T_82 | _T_84; // @[dma_ctrl.scala 214:300] - wire _T_86 = 3'h0 == io_iccm_dma_rtag; // @[dma_ctrl.scala 214:423] - wire _T_87 = io_iccm_dma_rvalid & _T_86; // @[dma_ctrl.scala 214:416] - wire _T_88 = _T_85 | _T_87; // @[dma_ctrl.scala 214:394] - wire _T_96 = _T_76 & _T_41; // @[dma_ctrl.scala 214:217] - wire _T_98 = 3'h1 == RdPtr; // @[dma_ctrl.scala 214:288] - wire _T_99 = _T_79 & _T_98; // @[dma_ctrl.scala 214:281] - wire _T_100 = _T_96 | _T_99; // @[dma_ctrl.scala 214:236] - wire _T_101 = 3'h1 == io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[dma_ctrl.scala 214:350] - wire _T_102 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_101; // @[dma_ctrl.scala 214:343] - wire _T_103 = _T_100 | _T_102; // @[dma_ctrl.scala 214:300] - wire _T_104 = 3'h1 == io_iccm_dma_rtag; // @[dma_ctrl.scala 214:423] - wire _T_105 = io_iccm_dma_rvalid & _T_104; // @[dma_ctrl.scala 214:416] - wire _T_106 = _T_103 | _T_105; // @[dma_ctrl.scala 214:394] - wire _T_114 = _T_76 & _T_49; // @[dma_ctrl.scala 214:217] - wire _T_116 = 3'h2 == RdPtr; // @[dma_ctrl.scala 214:288] - wire _T_117 = _T_79 & _T_116; // @[dma_ctrl.scala 214:281] - wire _T_118 = _T_114 | _T_117; // @[dma_ctrl.scala 214:236] - wire _T_119 = 3'h2 == io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[dma_ctrl.scala 214:350] - wire _T_120 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_119; // @[dma_ctrl.scala 214:343] - wire _T_121 = _T_118 | _T_120; // @[dma_ctrl.scala 214:300] - wire _T_122 = 3'h2 == io_iccm_dma_rtag; // @[dma_ctrl.scala 214:423] - wire _T_123 = io_iccm_dma_rvalid & _T_122; // @[dma_ctrl.scala 214:416] - wire _T_124 = _T_121 | _T_123; // @[dma_ctrl.scala 214:394] - wire _T_132 = _T_76 & _T_57; // @[dma_ctrl.scala 214:217] - wire _T_134 = 3'h3 == RdPtr; // @[dma_ctrl.scala 214:288] - wire _T_135 = _T_79 & _T_134; // @[dma_ctrl.scala 214:281] - wire _T_136 = _T_132 | _T_135; // @[dma_ctrl.scala 214:236] - wire _T_137 = 3'h3 == io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[dma_ctrl.scala 214:350] - wire _T_138 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_137; // @[dma_ctrl.scala 214:343] - wire _T_139 = _T_136 | _T_138; // @[dma_ctrl.scala 214:300] - wire _T_140 = 3'h3 == io_iccm_dma_rtag; // @[dma_ctrl.scala 214:423] - wire _T_141 = io_iccm_dma_rvalid & _T_140; // @[dma_ctrl.scala 214:416] - wire _T_142 = _T_139 | _T_141; // @[dma_ctrl.scala 214:394] - wire _T_150 = _T_76 & _T_65; // @[dma_ctrl.scala 214:217] - wire _T_152 = 3'h4 == RdPtr; // @[dma_ctrl.scala 214:288] - wire _T_153 = _T_79 & _T_152; // @[dma_ctrl.scala 214:281] - wire _T_154 = _T_150 | _T_153; // @[dma_ctrl.scala 214:236] - wire _T_155 = 3'h4 == io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[dma_ctrl.scala 214:350] - wire _T_156 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_155; // @[dma_ctrl.scala 214:343] - wire _T_157 = _T_154 | _T_156; // @[dma_ctrl.scala 214:300] - wire _T_158 = 3'h4 == io_iccm_dma_rtag; // @[dma_ctrl.scala 214:423] - wire _T_159 = io_iccm_dma_rvalid & _T_158; // @[dma_ctrl.scala 214:416] - wire _T_160 = _T_157 | _T_159; // @[dma_ctrl.scala 214:394] + wire _T_1067 = _T_1065 != 4'hf; // @[dma_ctrl.scala 313:68] + wire _T_1068 = _T_1046 & _T_1067; // @[dma_ctrl.scala 310:78] + wire _T_1069 = _T_1043 | _T_1068; // @[dma_ctrl.scala 309:145] + wire _T_1072 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1022; // @[dma_ctrl.scala 314:45] + wire _T_1074 = dma_mem_byteen == 8'hf; // @[dma_ctrl.scala 314:103] + wire _T_1076 = dma_mem_byteen == 8'hf0; // @[dma_ctrl.scala 314:139] + wire _T_1077 = _T_1074 | _T_1076; // @[dma_ctrl.scala 314:116] + wire _T_1079 = dma_mem_byteen == 8'hff; // @[dma_ctrl.scala 314:175] + wire _T_1080 = _T_1077 | _T_1079; // @[dma_ctrl.scala 314:152] + wire _T_1081 = ~_T_1080; // @[dma_ctrl.scala 314:80] + wire _T_1082 = _T_1072 & _T_1081; // @[dma_ctrl.scala 314:78] + wire _T_1083 = _T_1069 | _T_1082; // @[dma_ctrl.scala 313:79] + wire dma_alignment_error = _T_1010 & _T_1083; // @[dma_ctrl.scala 304:87] + wire _T_79 = dma_address_error | dma_alignment_error; // @[dma_ctrl.scala 208:258] + wire _T_80 = 3'h0 == RdPtr; // @[dma_ctrl.scala 208:288] + wire _T_81 = _T_79 & _T_80; // @[dma_ctrl.scala 208:281] + wire _T_82 = _T_78 | _T_81; // @[dma_ctrl.scala 208:236] + wire _T_83 = 3'h0 == io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[dma_ctrl.scala 208:350] + wire _T_84 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_83; // @[dma_ctrl.scala 208:343] + wire _T_85 = _T_82 | _T_84; // @[dma_ctrl.scala 208:300] + wire _T_86 = 3'h0 == io_iccm_dma_rtag; // @[dma_ctrl.scala 208:423] + wire _T_87 = io_iccm_dma_rvalid & _T_86; // @[dma_ctrl.scala 208:416] + wire _T_88 = _T_85 | _T_87; // @[dma_ctrl.scala 208:394] + wire _T_96 = _T_76 & _T_41; // @[dma_ctrl.scala 208:217] + wire _T_98 = 3'h1 == RdPtr; // @[dma_ctrl.scala 208:288] + wire _T_99 = _T_79 & _T_98; // @[dma_ctrl.scala 208:281] + wire _T_100 = _T_96 | _T_99; // @[dma_ctrl.scala 208:236] + wire _T_101 = 3'h1 == io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[dma_ctrl.scala 208:350] + wire _T_102 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_101; // @[dma_ctrl.scala 208:343] + wire _T_103 = _T_100 | _T_102; // @[dma_ctrl.scala 208:300] + wire _T_104 = 3'h1 == io_iccm_dma_rtag; // @[dma_ctrl.scala 208:423] + wire _T_105 = io_iccm_dma_rvalid & _T_104; // @[dma_ctrl.scala 208:416] + wire _T_106 = _T_103 | _T_105; // @[dma_ctrl.scala 208:394] + wire _T_114 = _T_76 & _T_49; // @[dma_ctrl.scala 208:217] + wire _T_116 = 3'h2 == RdPtr; // @[dma_ctrl.scala 208:288] + wire _T_117 = _T_79 & _T_116; // @[dma_ctrl.scala 208:281] + wire _T_118 = _T_114 | _T_117; // @[dma_ctrl.scala 208:236] + wire _T_119 = 3'h2 == io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[dma_ctrl.scala 208:350] + wire _T_120 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_119; // @[dma_ctrl.scala 208:343] + wire _T_121 = _T_118 | _T_120; // @[dma_ctrl.scala 208:300] + wire _T_122 = 3'h2 == io_iccm_dma_rtag; // @[dma_ctrl.scala 208:423] + wire _T_123 = io_iccm_dma_rvalid & _T_122; // @[dma_ctrl.scala 208:416] + wire _T_124 = _T_121 | _T_123; // @[dma_ctrl.scala 208:394] + wire _T_132 = _T_76 & _T_57; // @[dma_ctrl.scala 208:217] + wire _T_134 = 3'h3 == RdPtr; // @[dma_ctrl.scala 208:288] + wire _T_135 = _T_79 & _T_134; // @[dma_ctrl.scala 208:281] + wire _T_136 = _T_132 | _T_135; // @[dma_ctrl.scala 208:236] + wire _T_137 = 3'h3 == io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[dma_ctrl.scala 208:350] + wire _T_138 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_137; // @[dma_ctrl.scala 208:343] + wire _T_139 = _T_136 | _T_138; // @[dma_ctrl.scala 208:300] + wire _T_140 = 3'h3 == io_iccm_dma_rtag; // @[dma_ctrl.scala 208:423] + wire _T_141 = io_iccm_dma_rvalid & _T_140; // @[dma_ctrl.scala 208:416] + wire _T_142 = _T_139 | _T_141; // @[dma_ctrl.scala 208:394] + wire _T_150 = _T_76 & _T_65; // @[dma_ctrl.scala 208:217] + wire _T_152 = 3'h4 == RdPtr; // @[dma_ctrl.scala 208:288] + wire _T_153 = _T_79 & _T_152; // @[dma_ctrl.scala 208:281] + wire _T_154 = _T_150 | _T_153; // @[dma_ctrl.scala 208:236] + wire _T_155 = 3'h4 == io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[dma_ctrl.scala 208:350] + wire _T_156 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & _T_155; // @[dma_ctrl.scala 208:343] + wire _T_157 = _T_154 | _T_156; // @[dma_ctrl.scala 208:300] + wire _T_158 = 3'h4 == io_iccm_dma_rtag; // @[dma_ctrl.scala 208:423] + wire _T_159 = io_iccm_dma_rvalid & _T_158; // @[dma_ctrl.scala 208:416] + wire _T_160 = _T_157 | _T_159; // @[dma_ctrl.scala 208:394] wire [4:0] fifo_data_en = {_T_160,_T_142,_T_124,_T_106,_T_88}; // @[Cat.scala 29:58] - wire _T_165 = io_lsu_dma_dma_lsc_ctl_dma_dccm_req | io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[dma_ctrl.scala 216:95] - wire _T_166 = ~io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 216:136] - wire _T_167 = _T_165 & _T_166; // @[dma_ctrl.scala 216:134] - wire _T_169 = _T_167 & _T_80; // @[dma_ctrl.scala 216:174] - wire _T_174 = _T_167 & _T_98; // @[dma_ctrl.scala 216:174] - wire _T_179 = _T_167 & _T_116; // @[dma_ctrl.scala 216:174] - wire _T_184 = _T_167 & _T_134; // @[dma_ctrl.scala 216:174] - wire _T_189 = _T_167 & _T_152; // @[dma_ctrl.scala 216:174] + wire _T_165 = io_lsu_dma_dma_lsc_ctl_dma_dccm_req | io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[dma_ctrl.scala 210:95] + wire _T_166 = ~io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 210:136] + wire _T_167 = _T_165 & _T_166; // @[dma_ctrl.scala 210:134] + wire _T_169 = _T_167 & _T_80; // @[dma_ctrl.scala 210:174] + wire _T_174 = _T_167 & _T_98; // @[dma_ctrl.scala 210:174] + wire _T_179 = _T_167 & _T_116; // @[dma_ctrl.scala 210:174] + wire _T_184 = _T_167 & _T_134; // @[dma_ctrl.scala 210:174] + wire _T_189 = _T_167 & _T_152; // @[dma_ctrl.scala 210:174] wire [4:0] fifo_pend_en = {_T_189,_T_184,_T_179,_T_174,_T_169}; // @[Cat.scala 29:58] - wire _T_1107 = _T_995 & _T_996[0]; // @[dma_ctrl.scala 330:66] - wire _T_1109 = _T_1000 | dma_mem_addr_in_pic; // @[dma_ctrl.scala 330:134] - wire _T_1110 = ~_T_1109; // @[dma_ctrl.scala 330:88] - wire _T_1113 = dma_mem_sz_int[1:0] != 2'h2; // @[dma_ctrl.scala 330:191] - wire _T_1114 = _T_1110 | _T_1113; // @[dma_ctrl.scala 330:167] - wire dma_dbg_cmd_error = _T_1107 & _T_1114; // @[dma_ctrl.scala 330:84] - wire _T_197 = _T_79 | dma_dbg_cmd_error; // @[dma_ctrl.scala 218:114] - wire _T_199 = _T_197 & _T_80; // @[dma_ctrl.scala 218:135] - wire _T_200 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[dma_ctrl.scala 218:198] - wire _T_202 = _T_200 & _T_83; // @[dma_ctrl.scala 218:244] - wire _T_203 = _T_199 | _T_202; // @[dma_ctrl.scala 218:154] - wire _T_204 = io_iccm_dma_rvalid & io_iccm_dma_ecc_error; // @[dma_ctrl.scala 218:318] - wire _T_206 = _T_204 & _T_86; // @[dma_ctrl.scala 218:343] - wire _T_207 = _T_203 | _T_206; // @[dma_ctrl.scala 218:295] - wire _T_213 = _T_197 & _T_98; // @[dma_ctrl.scala 218:135] - wire _T_216 = _T_200 & _T_101; // @[dma_ctrl.scala 218:244] - wire _T_217 = _T_213 | _T_216; // @[dma_ctrl.scala 218:154] - wire _T_220 = _T_204 & _T_104; // @[dma_ctrl.scala 218:343] - wire _T_221 = _T_217 | _T_220; // @[dma_ctrl.scala 218:295] - wire _T_227 = _T_197 & _T_116; // @[dma_ctrl.scala 218:135] - wire _T_230 = _T_200 & _T_119; // @[dma_ctrl.scala 218:244] - wire _T_231 = _T_227 | _T_230; // @[dma_ctrl.scala 218:154] - wire _T_234 = _T_204 & _T_122; // @[dma_ctrl.scala 218:343] - wire _T_235 = _T_231 | _T_234; // @[dma_ctrl.scala 218:295] - wire _T_241 = _T_197 & _T_134; // @[dma_ctrl.scala 218:135] - wire _T_244 = _T_200 & _T_137; // @[dma_ctrl.scala 218:244] - wire _T_245 = _T_241 | _T_244; // @[dma_ctrl.scala 218:154] - wire _T_248 = _T_204 & _T_140; // @[dma_ctrl.scala 218:343] - wire _T_249 = _T_245 | _T_248; // @[dma_ctrl.scala 218:295] - wire _T_255 = _T_197 & _T_152; // @[dma_ctrl.scala 218:135] - wire _T_258 = _T_200 & _T_155; // @[dma_ctrl.scala 218:244] - wire _T_259 = _T_255 | _T_258; // @[dma_ctrl.scala 218:154] - wire _T_262 = _T_204 & _T_158; // @[dma_ctrl.scala 218:343] - wire _T_263 = _T_259 | _T_262; // @[dma_ctrl.scala 218:295] + wire _T_1107 = _T_995 & _T_996[0]; // @[dma_ctrl.scala 324:66] + wire _T_1109 = _T_1000 | dma_mem_addr_in_pic; // @[dma_ctrl.scala 324:134] + wire _T_1110 = ~_T_1109; // @[dma_ctrl.scala 324:88] + wire _T_1113 = dma_mem_sz_int[1:0] != 2'h2; // @[dma_ctrl.scala 324:191] + wire _T_1114 = _T_1110 | _T_1113; // @[dma_ctrl.scala 324:167] + wire dma_dbg_cmd_error = _T_1107 & _T_1114; // @[dma_ctrl.scala 324:84] + wire _T_197 = _T_79 | dma_dbg_cmd_error; // @[dma_ctrl.scala 212:114] + wire _T_199 = _T_197 & _T_80; // @[dma_ctrl.scala 212:135] + wire _T_200 = io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid & io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[dma_ctrl.scala 212:198] + wire _T_202 = _T_200 & _T_83; // @[dma_ctrl.scala 212:244] + wire _T_203 = _T_199 | _T_202; // @[dma_ctrl.scala 212:154] + wire _T_204 = io_iccm_dma_rvalid & io_iccm_dma_ecc_error; // @[dma_ctrl.scala 212:318] + wire _T_206 = _T_204 & _T_86; // @[dma_ctrl.scala 212:343] + wire _T_207 = _T_203 | _T_206; // @[dma_ctrl.scala 212:295] + wire _T_213 = _T_197 & _T_98; // @[dma_ctrl.scala 212:135] + wire _T_216 = _T_200 & _T_101; // @[dma_ctrl.scala 212:244] + wire _T_217 = _T_213 | _T_216; // @[dma_ctrl.scala 212:154] + wire _T_220 = _T_204 & _T_104; // @[dma_ctrl.scala 212:343] + wire _T_221 = _T_217 | _T_220; // @[dma_ctrl.scala 212:295] + wire _T_227 = _T_197 & _T_116; // @[dma_ctrl.scala 212:135] + wire _T_230 = _T_200 & _T_119; // @[dma_ctrl.scala 212:244] + wire _T_231 = _T_227 | _T_230; // @[dma_ctrl.scala 212:154] + wire _T_234 = _T_204 & _T_122; // @[dma_ctrl.scala 212:343] + wire _T_235 = _T_231 | _T_234; // @[dma_ctrl.scala 212:295] + wire _T_241 = _T_197 & _T_134; // @[dma_ctrl.scala 212:135] + wire _T_244 = _T_200 & _T_137; // @[dma_ctrl.scala 212:244] + wire _T_245 = _T_241 | _T_244; // @[dma_ctrl.scala 212:154] + wire _T_248 = _T_204 & _T_140; // @[dma_ctrl.scala 212:343] + wire _T_249 = _T_245 | _T_248; // @[dma_ctrl.scala 212:295] + wire _T_255 = _T_197 & _T_152; // @[dma_ctrl.scala 212:135] + wire _T_258 = _T_200 & _T_155; // @[dma_ctrl.scala 212:244] + wire _T_259 = _T_255 | _T_258; // @[dma_ctrl.scala 212:154] + wire _T_262 = _T_204 & _T_158; // @[dma_ctrl.scala 212:343] + wire _T_263 = _T_259 | _T_262; // @[dma_ctrl.scala 212:295] wire [4:0] fifo_error_en = {_T_263,_T_249,_T_235,_T_221,_T_207}; // @[Cat.scala 29:58] wire [1:0] _T_436 = {1'h0,io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error}; // @[Cat.scala 29:58] wire [1:0] _T_439 = {1'h0,io_iccm_dma_ecc_error}; // @[Cat.scala 29:58] wire [1:0] _T_442 = {_T_197,dma_alignment_error}; // @[Cat.scala 29:58] - wire [1:0] _T_443 = _T_87 ? _T_439 : _T_442; // @[dma_ctrl.scala 228:209] - wire [1:0] fifo_error_in_0 = _T_84 ? _T_436 : _T_443; // @[dma_ctrl.scala 228:60] - wire _T_269 = |fifo_error_in_0; // @[dma_ctrl.scala 220:83] - reg [1:0] fifo_error_0; // @[dma_ctrl.scala 234:85] - wire _T_272 = |fifo_error_0; // @[dma_ctrl.scala 220:125] - wire [1:0] _T_454 = _T_105 ? _T_439 : _T_442; // @[dma_ctrl.scala 228:209] - wire [1:0] fifo_error_in_1 = _T_102 ? _T_436 : _T_454; // @[dma_ctrl.scala 228:60] - wire _T_276 = |fifo_error_in_1; // @[dma_ctrl.scala 220:83] - reg [1:0] fifo_error_1; // @[dma_ctrl.scala 234:85] - wire _T_279 = |fifo_error_1; // @[dma_ctrl.scala 220:125] - wire [1:0] _T_465 = _T_123 ? _T_439 : _T_442; // @[dma_ctrl.scala 228:209] - wire [1:0] fifo_error_in_2 = _T_120 ? _T_436 : _T_465; // @[dma_ctrl.scala 228:60] - wire _T_283 = |fifo_error_in_2; // @[dma_ctrl.scala 220:83] - reg [1:0] fifo_error_2; // @[dma_ctrl.scala 234:85] - wire _T_286 = |fifo_error_2; // @[dma_ctrl.scala 220:125] - wire [1:0] _T_476 = _T_141 ? _T_439 : _T_442; // @[dma_ctrl.scala 228:209] - wire [1:0] fifo_error_in_3 = _T_138 ? _T_436 : _T_476; // @[dma_ctrl.scala 228:60] - wire _T_290 = |fifo_error_in_3; // @[dma_ctrl.scala 220:83] - reg [1:0] fifo_error_3; // @[dma_ctrl.scala 234:85] - wire _T_293 = |fifo_error_3; // @[dma_ctrl.scala 220:125] - wire [1:0] _T_487 = _T_159 ? _T_439 : _T_442; // @[dma_ctrl.scala 228:209] - wire [1:0] fifo_error_in_4 = _T_156 ? _T_436 : _T_487; // @[dma_ctrl.scala 228:60] - wire _T_297 = |fifo_error_in_4; // @[dma_ctrl.scala 220:83] - reg [1:0] fifo_error_4; // @[dma_ctrl.scala 234:85] - wire _T_300 = |fifo_error_4; // @[dma_ctrl.scala 220:125] - wire _T_309 = _T_272 | fifo_error_en[0]; // @[dma_ctrl.scala 222:78] - wire _T_311 = _T_165 & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 222:176] - wire _T_312 = _T_309 | _T_311; // @[dma_ctrl.scala 222:97] - wire _T_314 = _T_312 & _T_80; // @[dma_ctrl.scala 222:217] - wire _T_317 = _T_314 | _T_84; // @[dma_ctrl.scala 222:236] - wire _T_320 = _T_317 | _T_87; // @[dma_ctrl.scala 222:330] - wire _T_323 = _T_279 | fifo_error_en[1]; // @[dma_ctrl.scala 222:78] - wire _T_326 = _T_323 | _T_311; // @[dma_ctrl.scala 222:97] - wire _T_328 = _T_326 & _T_98; // @[dma_ctrl.scala 222:217] - wire _T_331 = _T_328 | _T_102; // @[dma_ctrl.scala 222:236] - wire _T_334 = _T_331 | _T_105; // @[dma_ctrl.scala 222:330] - wire _T_337 = _T_286 | fifo_error_en[2]; // @[dma_ctrl.scala 222:78] - wire _T_340 = _T_337 | _T_311; // @[dma_ctrl.scala 222:97] - wire _T_342 = _T_340 & _T_116; // @[dma_ctrl.scala 222:217] - wire _T_345 = _T_342 | _T_120; // @[dma_ctrl.scala 222:236] - wire _T_348 = _T_345 | _T_123; // @[dma_ctrl.scala 222:330] - wire _T_351 = _T_293 | fifo_error_en[3]; // @[dma_ctrl.scala 222:78] - wire _T_354 = _T_351 | _T_311; // @[dma_ctrl.scala 222:97] - wire _T_356 = _T_354 & _T_134; // @[dma_ctrl.scala 222:217] - wire _T_359 = _T_356 | _T_138; // @[dma_ctrl.scala 222:236] - wire _T_362 = _T_359 | _T_141; // @[dma_ctrl.scala 222:330] - wire _T_365 = _T_300 | fifo_error_en[4]; // @[dma_ctrl.scala 222:78] - wire _T_368 = _T_365 | _T_311; // @[dma_ctrl.scala 222:97] - wire _T_370 = _T_368 & _T_152; // @[dma_ctrl.scala 222:217] - wire _T_373 = _T_370 | _T_156; // @[dma_ctrl.scala 222:236] - wire _T_376 = _T_373 | _T_159; // @[dma_ctrl.scala 222:330] + wire [1:0] _T_443 = _T_87 ? _T_439 : _T_442; // @[dma_ctrl.scala 222:209] + wire [1:0] fifo_error_in_0 = _T_84 ? _T_436 : _T_443; // @[dma_ctrl.scala 222:60] + wire _T_269 = |fifo_error_in_0; // @[dma_ctrl.scala 214:83] + reg [1:0] fifo_error_0; // @[dma_ctrl.scala 228:85] + wire _T_272 = |fifo_error_0; // @[dma_ctrl.scala 214:125] + wire [1:0] _T_454 = _T_105 ? _T_439 : _T_442; // @[dma_ctrl.scala 222:209] + wire [1:0] fifo_error_in_1 = _T_102 ? _T_436 : _T_454; // @[dma_ctrl.scala 222:60] + wire _T_276 = |fifo_error_in_1; // @[dma_ctrl.scala 214:83] + reg [1:0] fifo_error_1; // @[dma_ctrl.scala 228:85] + wire _T_279 = |fifo_error_1; // @[dma_ctrl.scala 214:125] + wire [1:0] _T_465 = _T_123 ? _T_439 : _T_442; // @[dma_ctrl.scala 222:209] + wire [1:0] fifo_error_in_2 = _T_120 ? _T_436 : _T_465; // @[dma_ctrl.scala 222:60] + wire _T_283 = |fifo_error_in_2; // @[dma_ctrl.scala 214:83] + reg [1:0] fifo_error_2; // @[dma_ctrl.scala 228:85] + wire _T_286 = |fifo_error_2; // @[dma_ctrl.scala 214:125] + wire [1:0] _T_476 = _T_141 ? _T_439 : _T_442; // @[dma_ctrl.scala 222:209] + wire [1:0] fifo_error_in_3 = _T_138 ? _T_436 : _T_476; // @[dma_ctrl.scala 222:60] + wire _T_290 = |fifo_error_in_3; // @[dma_ctrl.scala 214:83] + reg [1:0] fifo_error_3; // @[dma_ctrl.scala 228:85] + wire _T_293 = |fifo_error_3; // @[dma_ctrl.scala 214:125] + wire [1:0] _T_487 = _T_159 ? _T_439 : _T_442; // @[dma_ctrl.scala 222:209] + wire [1:0] fifo_error_in_4 = _T_156 ? _T_436 : _T_487; // @[dma_ctrl.scala 222:60] + wire _T_297 = |fifo_error_in_4; // @[dma_ctrl.scala 214:83] + reg [1:0] fifo_error_4; // @[dma_ctrl.scala 228:85] + wire _T_300 = |fifo_error_4; // @[dma_ctrl.scala 214:125] + wire _T_309 = _T_272 | fifo_error_en[0]; // @[dma_ctrl.scala 216:78] + wire _T_311 = _T_165 & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 216:176] + wire _T_312 = _T_309 | _T_311; // @[dma_ctrl.scala 216:97] + wire _T_314 = _T_312 & _T_80; // @[dma_ctrl.scala 216:217] + wire _T_317 = _T_314 | _T_84; // @[dma_ctrl.scala 216:236] + wire _T_320 = _T_317 | _T_87; // @[dma_ctrl.scala 216:330] + wire _T_323 = _T_279 | fifo_error_en[1]; // @[dma_ctrl.scala 216:78] + wire _T_326 = _T_323 | _T_311; // @[dma_ctrl.scala 216:97] + wire _T_328 = _T_326 & _T_98; // @[dma_ctrl.scala 216:217] + wire _T_331 = _T_328 | _T_102; // @[dma_ctrl.scala 216:236] + wire _T_334 = _T_331 | _T_105; // @[dma_ctrl.scala 216:330] + wire _T_337 = _T_286 | fifo_error_en[2]; // @[dma_ctrl.scala 216:78] + wire _T_340 = _T_337 | _T_311; // @[dma_ctrl.scala 216:97] + wire _T_342 = _T_340 & _T_116; // @[dma_ctrl.scala 216:217] + wire _T_345 = _T_342 | _T_120; // @[dma_ctrl.scala 216:236] + wire _T_348 = _T_345 | _T_123; // @[dma_ctrl.scala 216:330] + wire _T_351 = _T_293 | fifo_error_en[3]; // @[dma_ctrl.scala 216:78] + wire _T_354 = _T_351 | _T_311; // @[dma_ctrl.scala 216:97] + wire _T_356 = _T_354 & _T_134; // @[dma_ctrl.scala 216:217] + wire _T_359 = _T_356 | _T_138; // @[dma_ctrl.scala 216:236] + wire _T_362 = _T_359 | _T_141; // @[dma_ctrl.scala 216:330] + wire _T_365 = _T_300 | fifo_error_en[4]; // @[dma_ctrl.scala 216:78] + wire _T_368 = _T_365 | _T_311; // @[dma_ctrl.scala 216:97] + wire _T_370 = _T_368 & _T_152; // @[dma_ctrl.scala 216:217] + wire _T_373 = _T_370 | _T_156; // @[dma_ctrl.scala 216:236] + wire _T_376 = _T_373 | _T_159; // @[dma_ctrl.scala 216:330] wire [4:0] fifo_done_en = {_T_376,_T_362,_T_348,_T_334,_T_320}; // @[Cat.scala 29:58] - wire _T_383 = fifo_done_en[0] | fifo_done[0]; // @[dma_ctrl.scala 224:75] - wire _T_384 = _T_383 & io_dma_bus_clk_en; // @[dma_ctrl.scala 224:91] - wire _T_387 = fifo_done_en[1] | fifo_done[1]; // @[dma_ctrl.scala 224:75] - wire _T_388 = _T_387 & io_dma_bus_clk_en; // @[dma_ctrl.scala 224:91] - wire _T_391 = fifo_done_en[2] | fifo_done[2]; // @[dma_ctrl.scala 224:75] - wire _T_392 = _T_391 & io_dma_bus_clk_en; // @[dma_ctrl.scala 224:91] - wire _T_395 = fifo_done_en[3] | fifo_done[3]; // @[dma_ctrl.scala 224:75] - wire _T_396 = _T_395 & io_dma_bus_clk_en; // @[dma_ctrl.scala 224:91] - wire _T_399 = fifo_done_en[4] | fifo_done[4]; // @[dma_ctrl.scala 224:75] - wire _T_400 = _T_399 & io_dma_bus_clk_en; // @[dma_ctrl.scala 224:91] + wire _T_383 = fifo_done_en[0] | fifo_done[0]; // @[dma_ctrl.scala 218:75] + wire _T_384 = _T_383 & io_dma_bus_clk_en; // @[dma_ctrl.scala 218:91] + wire _T_387 = fifo_done_en[1] | fifo_done[1]; // @[dma_ctrl.scala 218:75] + wire _T_388 = _T_387 & io_dma_bus_clk_en; // @[dma_ctrl.scala 218:91] + wire _T_391 = fifo_done_en[2] | fifo_done[2]; // @[dma_ctrl.scala 218:75] + wire _T_392 = _T_391 & io_dma_bus_clk_en; // @[dma_ctrl.scala 218:91] + wire _T_395 = fifo_done_en[3] | fifo_done[3]; // @[dma_ctrl.scala 218:75] + wire _T_396 = _T_395 & io_dma_bus_clk_en; // @[dma_ctrl.scala 218:91] + wire _T_399 = fifo_done_en[4] | fifo_done[4]; // @[dma_ctrl.scala 218:75] + wire _T_400 = _T_399 & io_dma_bus_clk_en; // @[dma_ctrl.scala 218:91] wire [4:0] fifo_done_bus_en = {_T_400,_T_396,_T_392,_T_388,_T_384}; // @[Cat.scala 29:58] - wire _T_1265 = io_dma_axi_b_valid & io_dma_axi_b_ready; // @[dma_ctrl.scala 503:61] - wire _T_1266 = io_dma_axi_r_valid & io_dma_axi_r_ready; // @[dma_ctrl.scala 503:105] - wire bus_rsp_sent = _T_1265 | _T_1266; // @[dma_ctrl.scala 503:83] - wire _T_406 = bus_rsp_sent & io_dma_bus_clk_en; // @[dma_ctrl.scala 226:99] - wire _T_407 = _T_406 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 226:120] + wire bus_rsp_sent = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 498:83] + wire _T_406 = bus_rsp_sent & io_dma_bus_clk_en; // @[dma_ctrl.scala 220:99] + wire _T_407 = _T_406 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 220:120] reg [2:0] RspPtr; // @[Reg.scala 27:20] - wire _T_408 = 3'h0 == RspPtr; // @[dma_ctrl.scala 226:150] - wire _T_409 = _T_407 & _T_408; // @[dma_ctrl.scala 226:143] - wire _T_413 = 3'h1 == RspPtr; // @[dma_ctrl.scala 226:150] - wire _T_414 = _T_407 & _T_413; // @[dma_ctrl.scala 226:143] - wire _T_418 = 3'h2 == RspPtr; // @[dma_ctrl.scala 226:150] - wire _T_419 = _T_407 & _T_418; // @[dma_ctrl.scala 226:143] - wire _T_423 = 3'h3 == RspPtr; // @[dma_ctrl.scala 226:150] - wire _T_424 = _T_407 & _T_423; // @[dma_ctrl.scala 226:143] - wire _T_428 = 3'h4 == RspPtr; // @[dma_ctrl.scala 226:150] - wire _T_429 = _T_407 & _T_428; // @[dma_ctrl.scala 226:143] + wire _T_408 = 3'h0 == RspPtr; // @[dma_ctrl.scala 220:150] + wire _T_409 = _T_407 & _T_408; // @[dma_ctrl.scala 220:143] + wire _T_413 = 3'h1 == RspPtr; // @[dma_ctrl.scala 220:150] + wire _T_414 = _T_407 & _T_413; // @[dma_ctrl.scala 220:143] + wire _T_418 = 3'h2 == RspPtr; // @[dma_ctrl.scala 220:150] + wire _T_419 = _T_407 & _T_418; // @[dma_ctrl.scala 220:143] + wire _T_423 = 3'h3 == RspPtr; // @[dma_ctrl.scala 220:150] + wire _T_424 = _T_407 & _T_423; // @[dma_ctrl.scala 220:143] + wire _T_428 = 3'h4 == RspPtr; // @[dma_ctrl.scala 220:150] + wire _T_429 = _T_407 & _T_428; // @[dma_ctrl.scala 220:143] wire [4:0] fifo_reset = {_T_429,_T_424,_T_419,_T_414,_T_409}; // @[Cat.scala 29:58] - wire _T_491 = fifo_error_en[0] & _T_269; // @[dma_ctrl.scala 230:77] + wire _T_491 = fifo_error_en[0] & _T_269; // @[dma_ctrl.scala 224:77] wire [63:0] _T_493 = {32'h0,fifo_addr_0}; // @[Cat.scala 29:58] wire [3:0] _T_498 = {io_dbg_dma_dbg_dctl_dbg_cmd_wrdata,io_dbg_dma_dbg_dctl_dbg_cmd_wrdata}; // @[Cat.scala 29:58] reg [63:0] wrbuf_data; // @[lib.scala 358:16] - wire [63:0] _T_500 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? {{60'd0}, _T_498} : wrbuf_data; // @[dma_ctrl.scala 230:347] - wire _T_506 = fifo_error_en[1] & _T_276; // @[dma_ctrl.scala 230:77] + wire [63:0] _T_500 = io_dbg_dma_dbg_ib_dbg_cmd_valid ? {{60'd0}, _T_498} : wrbuf_data; // @[dma_ctrl.scala 224:347] + wire _T_506 = fifo_error_en[1] & _T_276; // @[dma_ctrl.scala 224:77] wire [63:0] _T_508 = {32'h0,fifo_addr_1}; // @[Cat.scala 29:58] - wire _T_521 = fifo_error_en[2] & _T_283; // @[dma_ctrl.scala 230:77] + wire _T_521 = fifo_error_en[2] & _T_283; // @[dma_ctrl.scala 224:77] wire [63:0] _T_523 = {32'h0,fifo_addr_2}; // @[Cat.scala 29:58] - wire _T_536 = fifo_error_en[3] & _T_290; // @[dma_ctrl.scala 230:77] + wire _T_536 = fifo_error_en[3] & _T_290; // @[dma_ctrl.scala 224:77] wire [63:0] _T_538 = {32'h0,fifo_addr_3}; // @[Cat.scala 29:58] - wire _T_551 = fifo_error_en[4] & _T_297; // @[dma_ctrl.scala 230:77] + wire _T_551 = fifo_error_en[4] & _T_297; // @[dma_ctrl.scala 224:77] wire [63:0] _T_553 = {32'h0,fifo_addr_4}; // @[Cat.scala 29:58] - wire _T_566 = fifo_cmd_en[0] | fifo_valid[0]; // @[dma_ctrl.scala 232:86] - wire _T_568 = ~fifo_reset[0]; // @[dma_ctrl.scala 232:125] - wire _T_573 = fifo_cmd_en[1] | fifo_valid[1]; // @[dma_ctrl.scala 232:86] - wire _T_575 = ~fifo_reset[1]; // @[dma_ctrl.scala 232:125] - wire _T_580 = fifo_cmd_en[2] | fifo_valid[2]; // @[dma_ctrl.scala 232:86] - wire _T_582 = ~fifo_reset[2]; // @[dma_ctrl.scala 232:125] - wire _T_587 = fifo_cmd_en[3] | fifo_valid[3]; // @[dma_ctrl.scala 232:86] - wire _T_589 = ~fifo_reset[3]; // @[dma_ctrl.scala 232:125] - wire _T_594 = fifo_cmd_en[4] | fifo_valid[4]; // @[dma_ctrl.scala 232:86] - wire _T_596 = ~fifo_reset[4]; // @[dma_ctrl.scala 232:125] - wire [1:0] _T_605 = fifo_error_en[0] ? fifo_error_in_0 : fifo_error_0; // @[dma_ctrl.scala 234:89] + wire _T_566 = fifo_cmd_en[0] | fifo_valid[0]; // @[dma_ctrl.scala 226:86] + wire _T_568 = ~fifo_reset[0]; // @[dma_ctrl.scala 226:125] + wire _T_573 = fifo_cmd_en[1] | fifo_valid[1]; // @[dma_ctrl.scala 226:86] + wire _T_575 = ~fifo_reset[1]; // @[dma_ctrl.scala 226:125] + wire _T_580 = fifo_cmd_en[2] | fifo_valid[2]; // @[dma_ctrl.scala 226:86] + wire _T_582 = ~fifo_reset[2]; // @[dma_ctrl.scala 226:125] + wire _T_587 = fifo_cmd_en[3] | fifo_valid[3]; // @[dma_ctrl.scala 226:86] + wire _T_589 = ~fifo_reset[3]; // @[dma_ctrl.scala 226:125] + wire _T_594 = fifo_cmd_en[4] | fifo_valid[4]; // @[dma_ctrl.scala 226:86] + wire _T_596 = ~fifo_reset[4]; // @[dma_ctrl.scala 226:125] + wire [1:0] _T_605 = fifo_error_en[0] ? fifo_error_in_0 : fifo_error_0; // @[dma_ctrl.scala 228:89] wire [1:0] _T_609 = _T_568 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_614 = fifo_error_en[1] ? fifo_error_in_1 : fifo_error_1; // @[dma_ctrl.scala 234:89] + wire [1:0] _T_614 = fifo_error_en[1] ? fifo_error_in_1 : fifo_error_1; // @[dma_ctrl.scala 228:89] wire [1:0] _T_618 = _T_575 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_623 = fifo_error_en[2] ? fifo_error_in_2 : fifo_error_2; // @[dma_ctrl.scala 234:89] + wire [1:0] _T_623 = fifo_error_en[2] ? fifo_error_in_2 : fifo_error_2; // @[dma_ctrl.scala 228:89] wire [1:0] _T_627 = _T_582 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_632 = fifo_error_en[3] ? fifo_error_in_3 : fifo_error_3; // @[dma_ctrl.scala 234:89] + wire [1:0] _T_632 = fifo_error_en[3] ? fifo_error_in_3 : fifo_error_3; // @[dma_ctrl.scala 228:89] wire [1:0] _T_636 = _T_589 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_641 = fifo_error_en[4] ? fifo_error_in_4 : fifo_error_4; // @[dma_ctrl.scala 234:89] + wire [1:0] _T_641 = fifo_error_en[4] ? fifo_error_in_4 : fifo_error_4; // @[dma_ctrl.scala 228:89] wire [1:0] _T_645 = _T_596 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - reg _T_721; // @[dma_ctrl.scala 238:89] - reg _T_714; // @[dma_ctrl.scala 238:89] - reg _T_707; // @[dma_ctrl.scala 238:89] - reg _T_700; // @[dma_ctrl.scala 238:89] - reg _T_693; // @[dma_ctrl.scala 238:89] + reg _T_721; // @[dma_ctrl.scala 232:89] + reg _T_714; // @[dma_ctrl.scala 232:89] + reg _T_707; // @[dma_ctrl.scala 232:89] + reg _T_700; // @[dma_ctrl.scala 232:89] + reg _T_693; // @[dma_ctrl.scala 232:89] wire [4:0] fifo_rpend = {_T_721,_T_714,_T_707,_T_700,_T_693}; // @[Cat.scala 29:58] - wire _T_689 = fifo_pend_en[0] | fifo_rpend[0]; // @[dma_ctrl.scala 238:93] - wire _T_696 = fifo_pend_en[1] | fifo_rpend[1]; // @[dma_ctrl.scala 238:93] - wire _T_703 = fifo_pend_en[2] | fifo_rpend[2]; // @[dma_ctrl.scala 238:93] - wire _T_710 = fifo_pend_en[3] | fifo_rpend[3]; // @[dma_ctrl.scala 238:93] - wire _T_717 = fifo_pend_en[4] | fifo_rpend[4]; // @[dma_ctrl.scala 238:93] - reg _T_799; // @[dma_ctrl.scala 242:89] - reg _T_792; // @[dma_ctrl.scala 242:89] - reg _T_785; // @[dma_ctrl.scala 242:89] - reg _T_778; // @[dma_ctrl.scala 242:89] - reg _T_771; // @[dma_ctrl.scala 242:89] + wire _T_689 = fifo_pend_en[0] | fifo_rpend[0]; // @[dma_ctrl.scala 232:93] + wire _T_696 = fifo_pend_en[1] | fifo_rpend[1]; // @[dma_ctrl.scala 232:93] + wire _T_703 = fifo_pend_en[2] | fifo_rpend[2]; // @[dma_ctrl.scala 232:93] + wire _T_710 = fifo_pend_en[3] | fifo_rpend[3]; // @[dma_ctrl.scala 232:93] + wire _T_717 = fifo_pend_en[4] | fifo_rpend[4]; // @[dma_ctrl.scala 232:93] + reg _T_799; // @[dma_ctrl.scala 236:89] + reg _T_792; // @[dma_ctrl.scala 236:89] + reg _T_785; // @[dma_ctrl.scala 236:89] + reg _T_778; // @[dma_ctrl.scala 236:89] + reg _T_771; // @[dma_ctrl.scala 236:89] wire [4:0] fifo_done_bus = {_T_799,_T_792,_T_785,_T_778,_T_771}; // @[Cat.scala 29:58] - wire _T_767 = fifo_done_bus_en[0] | fifo_done_bus[0]; // @[dma_ctrl.scala 242:93] - wire _T_774 = fifo_done_bus_en[1] | fifo_done_bus[1]; // @[dma_ctrl.scala 242:93] - wire _T_781 = fifo_done_bus_en[2] | fifo_done_bus[2]; // @[dma_ctrl.scala 242:93] - wire _T_788 = fifo_done_bus_en[3] | fifo_done_bus[3]; // @[dma_ctrl.scala 242:93] - wire _T_795 = fifo_done_bus_en[4] | fifo_done_bus[4]; // @[dma_ctrl.scala 242:93] - wire [7:0] fifo_byteen_in = _T_20[7:0]; // @[dma_ctrl.scala 201:28] + wire _T_767 = fifo_done_bus_en[0] | fifo_done_bus[0]; // @[dma_ctrl.scala 236:93] + wire _T_774 = fifo_done_bus_en[1] | fifo_done_bus[1]; // @[dma_ctrl.scala 236:93] + wire _T_781 = fifo_done_bus_en[2] | fifo_done_bus[2]; // @[dma_ctrl.scala 236:93] + wire _T_788 = fifo_done_bus_en[3] | fifo_done_bus[3]; // @[dma_ctrl.scala 236:93] + wire _T_795 = fifo_done_bus_en[4] | fifo_done_bus[4]; // @[dma_ctrl.scala 236:93] + wire [7:0] fifo_byteen_in = _T_20[7:0]; // @[dma_ctrl.scala 195:28] reg _T_850; // @[Reg.scala 27:20] reg _T_852; // @[Reg.scala 27:20] reg _T_854; // @[Reg.scala 27:20] @@ -78900,117 +78742,105 @@ module dma_ctrl( reg [63:0] fifo_data_2; // @[lib.scala 358:16] reg [63:0] fifo_data_3; // @[lib.scala 358:16] reg [63:0] fifo_data_4; // @[lib.scala 358:16] - reg fifo_tag_0; // @[Reg.scala 27:20] - reg wrbuf_tag; // @[Reg.scala 27:20] - reg rdbuf_tag; // @[Reg.scala 27:20] - wire bus_cmd_tag = axi_mstr_sel ? wrbuf_tag : rdbuf_tag; // @[dma_ctrl.scala 468:43] - reg fifo_tag_1; // @[Reg.scala 27:20] - reg fifo_tag_2; // @[Reg.scala 27:20] - reg fifo_tag_3; // @[Reg.scala 27:20] - reg fifo_tag_4; // @[Reg.scala 27:20] - wire _T_931 = WrPtr == 3'h4; // @[dma_ctrl.scala 266:30] - wire [2:0] _T_934 = WrPtr + 3'h1; // @[dma_ctrl.scala 266:76] - wire _T_936 = RdPtr == 3'h4; // @[dma_ctrl.scala 268:30] - wire [2:0] _T_939 = RdPtr + 3'h1; // @[dma_ctrl.scala 268:76] - wire _T_941 = RspPtr == 3'h4; // @[dma_ctrl.scala 270:31] - wire [2:0] _T_944 = RspPtr + 3'h1; // @[dma_ctrl.scala 270:78] - wire WrPtrEn = |fifo_cmd_en; // @[dma_ctrl.scala 272:30] - wire RdPtrEn = _T_165 | _T_197; // @[dma_ctrl.scala 274:93] - wire RspPtrEn = io_dma_dbg_cmd_done | _T_406; // @[dma_ctrl.scala 276:39] + wire _T_931 = WrPtr == 3'h4; // @[dma_ctrl.scala 260:30] + wire [2:0] _T_934 = WrPtr + 3'h1; // @[dma_ctrl.scala 260:76] + wire _T_936 = RdPtr == 3'h4; // @[dma_ctrl.scala 262:30] + wire [2:0] _T_939 = RdPtr + 3'h1; // @[dma_ctrl.scala 262:76] + wire _T_941 = RspPtr == 3'h4; // @[dma_ctrl.scala 264:31] + wire [2:0] _T_944 = RspPtr + 3'h1; // @[dma_ctrl.scala 264:78] + wire WrPtrEn = |fifo_cmd_en; // @[dma_ctrl.scala 266:30] + wire RdPtrEn = _T_165 | _T_197; // @[dma_ctrl.scala 268:93] + wire RspPtrEn = io_dma_dbg_cmd_done | _T_406; // @[dma_ctrl.scala 270:39] wire [3:0] _T_966 = {3'h0,fifo_valid[0]}; // @[Cat.scala 29:58] wire [3:0] _T_969 = {3'h0,fifo_valid[1]}; // @[Cat.scala 29:58] wire [3:0] _T_972 = {3'h0,fifo_valid[2]}; // @[Cat.scala 29:58] wire [3:0] _T_975 = {3'h0,fifo_valid[3]}; // @[Cat.scala 29:58] wire [3:0] _T_978 = {3'h0,fifo_valid[4]}; // @[Cat.scala 29:58] - wire [3:0] _T_980 = _T_966 + _T_969; // @[dma_ctrl.scala 299:102] - wire [3:0] _T_982 = _T_980 + _T_972; // @[dma_ctrl.scala 299:102] - wire [3:0] _T_984 = _T_982 + _T_975; // @[dma_ctrl.scala 299:102] - wire [3:0] num_fifo_vld_tmp2 = _T_984 + _T_978; // @[dma_ctrl.scala 299:102] - wire _T_1123 = |fifo_valid; // @[dma_ctrl.scala 339:30] - wire fifo_empty = ~_T_1123; // @[dma_ctrl.scala 339:17] - wire [4:0] _T_1086 = fifo_valid >> RspPtr; // @[dma_ctrl.scala 326:39] - wire [4:0] _T_1088 = fifo_dbg >> RspPtr; // @[dma_ctrl.scala 326:58] - wire _T_1090 = _T_1086[0] & _T_1088[0]; // @[dma_ctrl.scala 326:48] - wire [4:0] _T_1091 = fifo_done >> RspPtr; // @[dma_ctrl.scala 326:78] - wire [31:0] _GEN_44 = 3'h1 == RspPtr ? fifo_addr_1 : fifo_addr_0; // @[dma_ctrl.scala 327:49] - wire [31:0] _GEN_45 = 3'h2 == RspPtr ? fifo_addr_2 : _GEN_44; // @[dma_ctrl.scala 327:49] - wire [31:0] _GEN_46 = 3'h3 == RspPtr ? fifo_addr_3 : _GEN_45; // @[dma_ctrl.scala 327:49] - wire [31:0] _GEN_47 = 3'h4 == RspPtr ? fifo_addr_4 : _GEN_46; // @[dma_ctrl.scala 327:49] - wire [63:0] _GEN_49 = 3'h1 == RspPtr ? fifo_data_1 : fifo_data_0; // @[dma_ctrl.scala 327:71] - wire [63:0] _GEN_50 = 3'h2 == RspPtr ? fifo_data_2 : _GEN_49; // @[dma_ctrl.scala 327:71] - wire [63:0] _GEN_51 = 3'h3 == RspPtr ? fifo_data_3 : _GEN_50; // @[dma_ctrl.scala 327:71] - wire [63:0] _GEN_52 = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 327:71] - wire [1:0] _GEN_54 = 3'h1 == RspPtr ? fifo_error_1 : fifo_error_0; // @[dma_ctrl.scala 328:47] - wire [1:0] _GEN_55 = 3'h2 == RspPtr ? fifo_error_2 : _GEN_54; // @[dma_ctrl.scala 328:47] - wire [1:0] _GEN_56 = 3'h3 == RspPtr ? fifo_error_3 : _GEN_55; // @[dma_ctrl.scala 328:47] - wire [1:0] _GEN_57 = 3'h4 == RspPtr ? fifo_error_4 : _GEN_56; // @[dma_ctrl.scala 328:47] - wire _T_1116 = dma_mem_addr_in_dccm | dma_mem_addr_in_pic; // @[dma_ctrl.scala 334:64] - wire [4:0] _T_1145 = fifo_rpend >> RdPtr; // @[dma_ctrl.scala 352:54] - wire _T_1147 = ~_T_1145[0]; // @[dma_ctrl.scala 352:43] - wire _T_1148 = _T_990[0] & _T_1147; // @[dma_ctrl.scala 352:41] - wire _T_1152 = _T_1148 & _T_994; // @[dma_ctrl.scala 352:62] - wire _T_1155 = ~_T_197; // @[dma_ctrl.scala 352:84] - wire dma_mem_req = _T_1152 & _T_1155; // @[dma_ctrl.scala 352:82] - wire _T_1117 = dma_mem_req & _T_1116; // @[dma_ctrl.scala 334:40] + wire [3:0] _T_980 = _T_966 + _T_969; // @[dma_ctrl.scala 293:102] + wire [3:0] _T_982 = _T_980 + _T_972; // @[dma_ctrl.scala 293:102] + wire [3:0] _T_984 = _T_982 + _T_975; // @[dma_ctrl.scala 293:102] + wire [3:0] num_fifo_vld_tmp2 = _T_984 + _T_978; // @[dma_ctrl.scala 293:102] + wire _T_1123 = |fifo_valid; // @[dma_ctrl.scala 334:30] + wire fifo_empty = ~_T_1123; // @[dma_ctrl.scala 334:17] + wire [4:0] _T_1086 = fifo_valid >> RspPtr; // @[dma_ctrl.scala 320:39] + wire [4:0] _T_1088 = fifo_dbg >> RspPtr; // @[dma_ctrl.scala 320:58] + wire _T_1090 = _T_1086[0] & _T_1088[0]; // @[dma_ctrl.scala 320:48] + wire [4:0] _T_1091 = fifo_done >> RspPtr; // @[dma_ctrl.scala 320:78] + wire [31:0] _GEN_44 = 3'h1 == RspPtr ? fifo_addr_1 : fifo_addr_0; // @[dma_ctrl.scala 321:49] + wire [31:0] _GEN_45 = 3'h2 == RspPtr ? fifo_addr_2 : _GEN_44; // @[dma_ctrl.scala 321:49] + wire [31:0] _GEN_46 = 3'h3 == RspPtr ? fifo_addr_3 : _GEN_45; // @[dma_ctrl.scala 321:49] + wire [31:0] _GEN_47 = 3'h4 == RspPtr ? fifo_addr_4 : _GEN_46; // @[dma_ctrl.scala 321:49] + wire [63:0] _GEN_49 = 3'h1 == RspPtr ? fifo_data_1 : fifo_data_0; // @[dma_ctrl.scala 321:71] + wire [63:0] _GEN_50 = 3'h2 == RspPtr ? fifo_data_2 : _GEN_49; // @[dma_ctrl.scala 321:71] + wire [63:0] _GEN_51 = 3'h3 == RspPtr ? fifo_data_3 : _GEN_50; // @[dma_ctrl.scala 321:71] + wire [63:0] _GEN_52 = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 321:71] + wire [1:0] _GEN_54 = 3'h1 == RspPtr ? fifo_error_1 : fifo_error_0; // @[dma_ctrl.scala 322:47] + wire [1:0] _GEN_55 = 3'h2 == RspPtr ? fifo_error_2 : _GEN_54; // @[dma_ctrl.scala 322:47] + wire [1:0] _GEN_56 = 3'h3 == RspPtr ? fifo_error_3 : _GEN_55; // @[dma_ctrl.scala 322:47] + wire [1:0] _GEN_57 = 3'h4 == RspPtr ? fifo_error_4 : _GEN_56; // @[dma_ctrl.scala 322:47] + wire _T_1116 = dma_mem_addr_in_dccm | dma_mem_addr_in_pic; // @[dma_ctrl.scala 328:80] + wire [4:0] _T_1145 = fifo_rpend >> RdPtr; // @[dma_ctrl.scala 347:54] + wire _T_1147 = ~_T_1145[0]; // @[dma_ctrl.scala 347:43] + wire _T_1148 = _T_990[0] & _T_1147; // @[dma_ctrl.scala 347:41] + wire _T_1152 = _T_1148 & _T_994; // @[dma_ctrl.scala 347:62] + wire _T_1155 = ~_T_197; // @[dma_ctrl.scala 347:84] + wire dma_mem_req = _T_1152 & _T_1155; // @[dma_ctrl.scala 347:82] + wire _T_1117 = dma_mem_req & _T_1116; // @[dma_ctrl.scala 328:56] reg [2:0] dma_nack_count; // @[Reg.scala 27:20] - wire _T_1118 = dma_nack_count >= io_dec_tlu_dma_qos_prty; // @[dma_ctrl.scala 334:105] - wire _T_1120 = dma_mem_req & dma_mem_addr_in_iccm; // @[dma_ctrl.scala 335:56] - wire _T_1127 = ~_T_165; // @[dma_ctrl.scala 344:77] + wire _T_1118 = dma_nack_count >= io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[dma_ctrl.scala 328:121] + wire _T_1120 = dma_mem_req & dma_mem_addr_in_iccm; // @[dma_ctrl.scala 329:56] + wire _T_1127 = ~_T_165; // @[dma_ctrl.scala 339:77] wire [2:0] _T_1129 = _T_1127 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_1131 = _T_1129 & dma_nack_count; // @[dma_ctrl.scala 344:155] - wire _T_1135 = dma_mem_req & _T_1127; // @[dma_ctrl.scala 344:203] - wire [2:0] _T_1138 = dma_nack_count + 3'h1; // @[dma_ctrl.scala 344:304] - wire _T_1164 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1076; // @[dma_ctrl.scala 358:84] + wire [2:0] _T_1131 = _T_1129 & dma_nack_count; // @[dma_ctrl.scala 339:155] + wire _T_1135 = dma_mem_req & _T_1127; // @[dma_ctrl.scala 339:203] + wire [2:0] _T_1138 = dma_nack_count + 3'h1; // @[dma_ctrl.scala 339:304] + wire _T_1164 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1076; // @[dma_ctrl.scala 353:84] wire [31:0] _T_1168 = {dma_mem_addr_int[31:3],1'h1,dma_mem_addr_int[1:0]}; // @[Cat.scala 29:58] - wire _T_1176 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1077; // @[dma_ctrl.scala 359:84] - wire [4:0] _T_1179 = fifo_write >> RdPtr; // @[dma_ctrl.scala 361:53] - wire [63:0] _GEN_75 = 3'h1 == RdPtr ? fifo_data_1 : fifo_data_0; // @[dma_ctrl.scala 362:40] - wire [63:0] _GEN_76 = 3'h2 == RdPtr ? fifo_data_2 : _GEN_75; // @[dma_ctrl.scala 362:40] - wire [63:0] _GEN_77 = 3'h3 == RdPtr ? fifo_data_3 : _GEN_76; // @[dma_ctrl.scala 362:40] - reg dma_dbg_cmd_done_q; // @[dma_ctrl.scala 382:12] - wire _T_1192 = bus_cmd_valid & io_dma_bus_clk_en; // @[dma_ctrl.scala 387:44] - wire _T_1193 = _T_1192 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 387:65] - wire bus_rsp_valid = io_dma_axi_b_valid | io_dma_axi_r_valid; // @[dma_ctrl.scala 502:60] - wire _T_1194 = bus_cmd_valid | bus_rsp_valid; // @[dma_ctrl.scala 388:44] - wire _T_1195 = _T_1194 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 388:60] - wire _T_1196 = _T_1195 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 388:94] - wire _T_1197 = _T_1196 | dma_dbg_cmd_done_q; // @[dma_ctrl.scala 388:116] - wire _T_1199 = _T_1197 | _T_1123; // @[dma_ctrl.scala 388:137] - wire wrbuf_en = io_dma_axi_aw_valid & io_dma_axi_aw_ready; // @[dma_ctrl.scala 410:47] - wire wrbuf_data_en = io_dma_axi_w_valid & io_dma_axi_w_ready; // @[dma_ctrl.scala 411:46] - wire wrbuf_cmd_sent = axi_mstr_prty_en & axi_mstr_sel; // @[dma_ctrl.scala 412:40] - wire _T_1201 = ~wrbuf_en; // @[dma_ctrl.scala 413:51] - wire wrbuf_rst = wrbuf_cmd_sent & _T_1201; // @[dma_ctrl.scala 413:49] - wire _T_1203 = ~wrbuf_data_en; // @[dma_ctrl.scala 414:51] - wire wrbuf_data_rst = wrbuf_cmd_sent & _T_1203; // @[dma_ctrl.scala 414:49] - wire _T_1204 = wrbuf_en | wrbuf_vld; // @[dma_ctrl.scala 416:63] - wire _T_1205 = ~wrbuf_rst; // @[dma_ctrl.scala 416:92] - wire _T_1208 = wrbuf_data_en | wrbuf_data_vld; // @[dma_ctrl.scala 418:63] - wire _T_1209 = ~wrbuf_data_rst; // @[dma_ctrl.scala 418:102] - wire rdbuf_en = io_dma_axi_ar_valid & io_dma_axi_ar_ready; // @[dma_ctrl.scala 438:59] - wire _T_1214 = ~axi_mstr_sel; // @[dma_ctrl.scala 439:44] - wire rdbuf_cmd_sent = axi_mstr_prty_en & _T_1214; // @[dma_ctrl.scala 439:42] - wire _T_1216 = ~rdbuf_en; // @[dma_ctrl.scala 440:63] - wire rdbuf_rst = rdbuf_cmd_sent & _T_1216; // @[dma_ctrl.scala 440:61] - wire _T_1217 = rdbuf_en | rdbuf_vld; // @[dma_ctrl.scala 442:51] - wire _T_1218 = ~rdbuf_rst; // @[dma_ctrl.scala 442:80] - wire _T_1222 = ~wrbuf_cmd_sent; // @[dma_ctrl.scala 454:44] - wire _T_1223 = wrbuf_vld & _T_1222; // @[dma_ctrl.scala 454:42] - wire _T_1226 = wrbuf_data_vld & _T_1222; // @[dma_ctrl.scala 455:47] - wire _T_1228 = ~rdbuf_cmd_sent; // @[dma_ctrl.scala 456:44] - wire _T_1229 = rdbuf_vld & _T_1228; // @[dma_ctrl.scala 456:42] - wire axi_mstr_prty_in = ~axi_mstr_priority; // @[dma_ctrl.scala 475:27] - wire _T_1251 = ~_T_1088[0]; // @[dma_ctrl.scala 482:50] - wire _T_1252 = _T_1086[0] & _T_1251; // @[dma_ctrl.scala 482:48] - wire [4:0] _T_1253 = fifo_done_bus >> RspPtr; // @[dma_ctrl.scala 482:83] - wire axi_rsp_valid = _T_1252 & _T_1253[0]; // @[dma_ctrl.scala 482:68] - wire [4:0] _T_1255 = fifo_write >> RspPtr; // @[dma_ctrl.scala 484:39] - wire axi_rsp_write = _T_1255[0]; // @[dma_ctrl.scala 484:39] - wire [1:0] _T_1258 = _GEN_57[1] ? 2'h3 : 2'h0; // @[dma_ctrl.scala 485:64] - wire _GEN_86 = 3'h1 == RspPtr ? fifo_tag_1 : fifo_tag_0; // @[dma_ctrl.scala 493:33] - wire _GEN_87 = 3'h2 == RspPtr ? fifo_tag_2 : _GEN_86; // @[dma_ctrl.scala 493:33] - wire _GEN_88 = 3'h3 == RspPtr ? fifo_tag_3 : _GEN_87; // @[dma_ctrl.scala 493:33] - wire _T_1261 = ~axi_rsp_write; // @[dma_ctrl.scala 495:46] + wire _T_1176 = io_lsu_dma_dma_lsc_ctl_dma_mem_write & _T_1077; // @[dma_ctrl.scala 354:84] + wire [4:0] _T_1179 = fifo_write >> RdPtr; // @[dma_ctrl.scala 356:53] + wire [63:0] _GEN_75 = 3'h1 == RdPtr ? fifo_data_1 : fifo_data_0; // @[dma_ctrl.scala 357:40] + wire [63:0] _GEN_76 = 3'h2 == RdPtr ? fifo_data_2 : _GEN_75; // @[dma_ctrl.scala 357:40] + wire [63:0] _GEN_77 = 3'h3 == RdPtr ? fifo_data_3 : _GEN_76; // @[dma_ctrl.scala 357:40] + reg dma_dbg_cmd_done_q; // @[dma_ctrl.scala 377:12] + wire _T_1192 = bus_cmd_valid & io_dma_bus_clk_en; // @[dma_ctrl.scala 382:44] + wire _T_1193 = _T_1192 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 382:65] + wire _T_1194 = bus_cmd_valid | bus_rsp_sent; // @[dma_ctrl.scala 383:44] + wire _T_1195 = _T_1194 | io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[dma_ctrl.scala 383:60] + wire _T_1196 = _T_1195 | io_dma_dbg_cmd_done; // @[dma_ctrl.scala 383:94] + wire _T_1197 = _T_1196 | dma_dbg_cmd_done_q; // @[dma_ctrl.scala 383:116] + wire _T_1199 = _T_1197 | _T_1123; // @[dma_ctrl.scala 383:137] + wire wrbuf_en = io_dma_axi_aw_valid & io_dma_axi_aw_ready; // @[dma_ctrl.scala 405:47] + wire wrbuf_data_en = io_dma_axi_w_valid & io_dma_axi_w_ready; // @[dma_ctrl.scala 406:46] + wire wrbuf_cmd_sent = axi_mstr_prty_en & axi_mstr_sel; // @[dma_ctrl.scala 407:40] + wire _T_1201 = ~wrbuf_en; // @[dma_ctrl.scala 408:51] + wire wrbuf_rst = wrbuf_cmd_sent & _T_1201; // @[dma_ctrl.scala 408:49] + wire _T_1203 = ~wrbuf_data_en; // @[dma_ctrl.scala 409:51] + wire wrbuf_data_rst = wrbuf_cmd_sent & _T_1203; // @[dma_ctrl.scala 409:49] + wire _T_1204 = wrbuf_en | wrbuf_vld; // @[dma_ctrl.scala 411:63] + wire _T_1205 = ~wrbuf_rst; // @[dma_ctrl.scala 411:92] + wire _T_1208 = wrbuf_data_en | wrbuf_data_vld; // @[dma_ctrl.scala 413:63] + wire _T_1209 = ~wrbuf_data_rst; // @[dma_ctrl.scala 413:102] + wire rdbuf_en = io_dma_axi_ar_valid & io_dma_axi_ar_ready; // @[dma_ctrl.scala 433:59] + wire _T_1214 = ~axi_mstr_sel; // @[dma_ctrl.scala 434:44] + wire rdbuf_cmd_sent = axi_mstr_prty_en & _T_1214; // @[dma_ctrl.scala 434:42] + wire _T_1216 = ~rdbuf_en; // @[dma_ctrl.scala 435:63] + wire rdbuf_rst = rdbuf_cmd_sent & _T_1216; // @[dma_ctrl.scala 435:61] + wire _T_1217 = rdbuf_en | rdbuf_vld; // @[dma_ctrl.scala 437:51] + wire _T_1218 = ~rdbuf_rst; // @[dma_ctrl.scala 437:80] + wire _T_1222 = ~wrbuf_cmd_sent; // @[dma_ctrl.scala 449:44] + wire _T_1223 = wrbuf_vld & _T_1222; // @[dma_ctrl.scala 449:42] + wire _T_1226 = wrbuf_data_vld & _T_1222; // @[dma_ctrl.scala 450:47] + wire _T_1228 = ~rdbuf_cmd_sent; // @[dma_ctrl.scala 451:44] + wire _T_1229 = rdbuf_vld & _T_1228; // @[dma_ctrl.scala 451:42] + wire axi_mstr_prty_in = ~axi_mstr_priority; // @[dma_ctrl.scala 470:27] + wire _T_1251 = ~_T_1088[0]; // @[dma_ctrl.scala 477:50] + wire _T_1252 = _T_1086[0] & _T_1251; // @[dma_ctrl.scala 477:48] + wire [4:0] _T_1253 = fifo_done_bus >> RspPtr; // @[dma_ctrl.scala 477:83] + wire axi_rsp_valid = _T_1252 & _T_1253[0]; // @[dma_ctrl.scala 477:68] + wire [4:0] _T_1255 = fifo_write >> RspPtr; // @[dma_ctrl.scala 479:39] + wire axi_rsp_write = _T_1255[0]; // @[dma_ctrl.scala 479:39] + wire [1:0] _T_1258 = _GEN_57[1] ? 2'h3 : 2'h0; // @[dma_ctrl.scala 480:64] + wire _T_1261 = ~axi_rsp_write; // @[dma_ctrl.scala 490:46] rvclkhdr rvclkhdr ( // @[lib.scala 352:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -79071,19 +78901,19 @@ module dma_ctrl( .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - rvclkhdr dma_buffer_c1cgc ( // @[dma_ctrl.scala 390:32] + rvclkhdr dma_buffer_c1cgc ( // @[dma_ctrl.scala 385:32] .io_l1clk(dma_buffer_c1cgc_io_l1clk), .io_clk(dma_buffer_c1cgc_io_clk), .io_en(dma_buffer_c1cgc_io_en), .io_scan_mode(dma_buffer_c1cgc_io_scan_mode) ); - rvclkhdr dma_free_cgc ( // @[dma_ctrl.scala 396:28] + rvclkhdr dma_free_cgc ( // @[dma_ctrl.scala 391:28] .io_l1clk(dma_free_cgc_io_l1clk), .io_clk(dma_free_cgc_io_clk), .io_en(dma_free_cgc_io_en), .io_scan_mode(dma_free_cgc_io_scan_mode) ); - rvclkhdr dma_bus_cgc ( // @[dma_ctrl.scala 402:27] + rvclkhdr dma_bus_cgc ( // @[dma_ctrl.scala 397:27] .io_l1clk(dma_bus_cgc_io_l1clk), .io_clk(dma_bus_cgc_io_clk), .io_en(dma_bus_cgc_io_en), @@ -79107,40 +78937,40 @@ module dma_ctrl( .io_en(rvclkhdr_12_io_en), .io_scan_mode(rvclkhdr_12_io_scan_mode) ); - assign io_dma_dbg_rddata = _GEN_47[2] ? _GEN_52[63:32] : _GEN_52[31:0]; // @[dma_ctrl.scala 327:25] - assign io_dma_dbg_cmd_done = _T_1090 & _T_1091[0]; // @[dma_ctrl.scala 326:25] - assign io_dma_dbg_cmd_fail = |_GEN_57; // @[dma_ctrl.scala 328:25] - assign io_dbg_dma_io_dma_dbg_ready = fifo_empty & dbg_dma_bubble_bus; // @[dma_ctrl.scala 325:36] - assign io_dma_dccm_stall_any = _T_1117 & _T_1118; // @[dma_ctrl.scala 334:25] - assign io_dma_pmu_dccm_read = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & _T_166; // @[dma_ctrl.scala 366:26] - assign io_dma_pmu_dccm_write = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 367:26] - assign io_dma_pmu_any_read = _T_165 & _T_166; // @[dma_ctrl.scala 368:26] - assign io_dma_pmu_any_write = _T_165 & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 369:26] - assign io_dma_axi_aw_ready = ~_T_1223; // @[dma_ctrl.scala 454:27] - assign io_dma_axi_w_ready = ~_T_1226; // @[dma_ctrl.scala 455:27] - assign io_dma_axi_b_valid = axi_rsp_valid & axi_rsp_write; // @[dma_ctrl.scala 491:27] - assign io_dma_axi_b_bits_resp = _GEN_57[0] ? 2'h2 : _T_1258; // @[dma_ctrl.scala 492:41] - assign io_dma_axi_b_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 493:33] - assign io_dma_axi_ar_ready = ~_T_1229; // @[dma_ctrl.scala 456:27] - assign io_dma_axi_r_valid = axi_rsp_valid & _T_1261; // @[dma_ctrl.scala 495:27] - assign io_dma_axi_r_bits_id = 3'h4 == RspPtr ? fifo_tag_4 : _GEN_88; // @[dma_ctrl.scala 499:37] - assign io_dma_axi_r_bits_data = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 497:43] - assign io_dma_axi_r_bits_resp = _GEN_57[0] ? 2'h2 : _T_1258; // @[dma_ctrl.scala 496:41] - assign io_lsu_dma_dma_lsc_ctl_dma_dccm_req = _T_1117 & io_lsu_dma_dccm_ready; // @[dma_ctrl.scala 353:40] - assign io_lsu_dma_dma_lsc_ctl_dma_mem_addr = _T_1164 ? _T_1168 : dma_mem_addr_int; // @[dma_ctrl.scala 358:40] - assign io_lsu_dma_dma_lsc_ctl_dma_mem_sz = _T_1176 ? 3'h2 : dma_mem_sz_int; // @[dma_ctrl.scala 359:40] - assign io_lsu_dma_dma_lsc_ctl_dma_mem_write = _T_1179[0]; // @[dma_ctrl.scala 361:40] - assign io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = 3'h4 == RdPtr ? fifo_data_4 : _GEN_77; // @[dma_ctrl.scala 362:40] - assign io_lsu_dma_dma_dccm_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[dma_ctrl.scala 504:40] - assign io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[dma_ctrl.scala 505:41] - assign io_lsu_dma_dma_mem_tag = RdPtr; // @[dma_ctrl.scala 355:28] - assign io_ifu_dma_dma_ifc_dma_iccm_stall_any = _T_1120 & _T_1118; // @[dma_ctrl.scala 335:41] - assign io_ifu_dma_dma_mem_ctl_dma_iccm_req = _T_1120 & io_iccm_ready; // @[dma_ctrl.scala 354:40] - assign io_ifu_dma_dma_mem_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[dma_ctrl.scala 507:39] - assign io_ifu_dma_dma_mem_ctl_dma_mem_sz = io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[dma_ctrl.scala 506:37] - assign io_ifu_dma_dma_mem_ctl_dma_mem_write = io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 509:40] - assign io_ifu_dma_dma_mem_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[dma_ctrl.scala 508:40] - assign io_ifu_dma_dma_mem_ctl_dma_mem_tag = io_lsu_dma_dma_mem_tag; // @[dma_ctrl.scala 510:38] + assign io_dma_dbg_rddata = _GEN_47[2] ? _GEN_52[63:32] : _GEN_52[31:0]; // @[dma_ctrl.scala 321:25] + assign io_dma_dbg_cmd_done = _T_1090 & _T_1091[0]; // @[dma_ctrl.scala 320:25] + assign io_dma_dbg_cmd_fail = |_GEN_57; // @[dma_ctrl.scala 322:25] + assign io_dbg_dma_io_dma_dbg_ready = fifo_empty & dbg_dma_bubble_bus; // @[dma_ctrl.scala 319:36] + assign io_dec_dma_dctl_dma_dma_dccm_stall_any = io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[dma_ctrl.scala 331:42] + assign io_dec_dma_tlu_dma_dma_pmu_dccm_read = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & _T_166; // @[dma_ctrl.scala 361:42] + assign io_dec_dma_tlu_dma_dma_pmu_dccm_write = io_lsu_dma_dma_lsc_ctl_dma_dccm_req & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 362:42] + assign io_dec_dma_tlu_dma_dma_pmu_any_read = _T_165 & _T_166; // @[dma_ctrl.scala 363:42] + assign io_dec_dma_tlu_dma_dma_pmu_any_write = _T_165 & io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 364:42] + assign io_dec_dma_tlu_dma_dma_dccm_stall_any = _T_1117 & _T_1118; // @[dma_ctrl.scala 328:41] + assign io_dec_dma_tlu_dma_dma_iccm_stall_any = io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[dma_ctrl.scala 330:41] + assign io_dma_axi_aw_ready = ~_T_1223; // @[dma_ctrl.scala 449:27] + assign io_dma_axi_w_ready = ~_T_1226; // @[dma_ctrl.scala 450:27] + assign io_dma_axi_b_valid = axi_rsp_valid & axi_rsp_write; // @[dma_ctrl.scala 486:27] + assign io_dma_axi_b_bits_resp = _GEN_57[0] ? 2'h2 : _T_1258; // @[dma_ctrl.scala 487:41] + assign io_dma_axi_ar_ready = ~_T_1229; // @[dma_ctrl.scala 451:27] + assign io_dma_axi_r_valid = axi_rsp_valid & _T_1261; // @[dma_ctrl.scala 490:27] + assign io_dma_axi_r_bits_data = 3'h4 == RspPtr ? fifo_data_4 : _GEN_51; // @[dma_ctrl.scala 492:43] + assign io_dma_axi_r_bits_resp = _GEN_57[0] ? 2'h2 : _T_1258; // @[dma_ctrl.scala 491:41] + assign io_lsu_dma_dma_lsc_ctl_dma_dccm_req = _T_1117 & io_lsu_dma_dccm_ready; // @[dma_ctrl.scala 348:40] + assign io_lsu_dma_dma_lsc_ctl_dma_mem_addr = _T_1164 ? _T_1168 : dma_mem_addr_int; // @[dma_ctrl.scala 353:40] + assign io_lsu_dma_dma_lsc_ctl_dma_mem_sz = _T_1176 ? 3'h2 : dma_mem_sz_int; // @[dma_ctrl.scala 354:40] + assign io_lsu_dma_dma_lsc_ctl_dma_mem_write = _T_1179[0]; // @[dma_ctrl.scala 356:40] + assign io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = 3'h4 == RdPtr ? fifo_data_4 : _GEN_77; // @[dma_ctrl.scala 357:40] + assign io_lsu_dma_dma_dccm_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[dma_ctrl.scala 499:40] + assign io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[dma_ctrl.scala 500:41] + assign io_lsu_dma_dma_mem_tag = RdPtr; // @[dma_ctrl.scala 350:28] + assign io_ifu_dma_dma_ifc_dma_iccm_stall_any = _T_1120 & _T_1118; // @[dma_ctrl.scala 329:41] + assign io_ifu_dma_dma_mem_ctl_dma_iccm_req = _T_1120 & io_iccm_ready; // @[dma_ctrl.scala 349:40] + assign io_ifu_dma_dma_mem_ctl_dma_mem_addr = io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[dma_ctrl.scala 502:39] + assign io_ifu_dma_dma_mem_ctl_dma_mem_sz = io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[dma_ctrl.scala 501:37] + assign io_ifu_dma_dma_mem_ctl_dma_mem_write = io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[dma_ctrl.scala 504:40] + assign io_ifu_dma_dma_mem_ctl_dma_mem_wdata = io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[dma_ctrl.scala 503:40] + assign io_ifu_dma_dma_mem_ctl_dma_mem_tag = io_lsu_dma_dma_mem_tag; // @[dma_ctrl.scala 505:38] assign rvclkhdr_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_io_en = fifo_cmd_en[0]; // @[lib.scala 355:17] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] @@ -79171,15 +79001,15 @@ module dma_ctrl( assign rvclkhdr_9_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_9_io_en = fifo_data_en[4]; // @[lib.scala 355:17] assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] - assign dma_buffer_c1cgc_io_clk = clock; // @[dma_ctrl.scala 393:33] - assign dma_buffer_c1cgc_io_en = _T_1193 | io_clk_override; // @[dma_ctrl.scala 391:33] - assign dma_buffer_c1cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 392:33] - assign dma_free_cgc_io_clk = clock; // @[dma_ctrl.scala 399:29] - assign dma_free_cgc_io_en = _T_1199 | io_clk_override; // @[dma_ctrl.scala 397:29] - assign dma_free_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 398:29] - assign dma_bus_cgc_io_clk = clock; // @[dma_ctrl.scala 405:28] - assign dma_bus_cgc_io_en = io_dma_bus_clk_en; // @[dma_ctrl.scala 403:28] - assign dma_bus_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 404:28] + assign dma_buffer_c1cgc_io_clk = clock; // @[dma_ctrl.scala 388:33] + assign dma_buffer_c1cgc_io_en = _T_1193 | io_clk_override; // @[dma_ctrl.scala 386:33] + assign dma_buffer_c1cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 387:33] + assign dma_free_cgc_io_clk = clock; // @[dma_ctrl.scala 394:29] + assign dma_free_cgc_io_en = _T_1199 | io_clk_override; // @[dma_ctrl.scala 392:29] + assign dma_free_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 393:29] + assign dma_bus_cgc_io_clk = clock; // @[dma_ctrl.scala 400:28] + assign dma_bus_cgc_io_en = io_dma_bus_clk_en; // @[dma_ctrl.scala 398:28] + assign dma_bus_cgc_io_scan_mode = io_scan_mode; // @[dma_ctrl.scala 399:28] assign rvclkhdr_10_io_clk = clock; // @[lib.scala 354:18] assign rvclkhdr_10_io_en = wrbuf_en & io_dma_bus_clk_en; // @[lib.scala 355:17] assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[lib.scala 356:24] @@ -79365,23 +79195,9 @@ initial begin _RAND_69 = {2{`RANDOM}}; fifo_data_4 = _RAND_69[63:0]; _RAND_70 = {1{`RANDOM}}; - fifo_tag_0 = _RAND_70[0:0]; + dma_nack_count = _RAND_70[2:0]; _RAND_71 = {1{`RANDOM}}; - wrbuf_tag = _RAND_71[0:0]; - _RAND_72 = {1{`RANDOM}}; - rdbuf_tag = _RAND_72[0:0]; - _RAND_73 = {1{`RANDOM}}; - fifo_tag_1 = _RAND_73[0:0]; - _RAND_74 = {1{`RANDOM}}; - fifo_tag_2 = _RAND_74[0:0]; - _RAND_75 = {1{`RANDOM}}; - fifo_tag_3 = _RAND_75[0:0]; - _RAND_76 = {1{`RANDOM}}; - fifo_tag_4 = _RAND_76[0:0]; - _RAND_77 = {1{`RANDOM}}; - dma_nack_count = _RAND_77[2:0]; - _RAND_78 = {1{`RANDOM}}; - dma_dbg_cmd_done_q = _RAND_78[0:0]; + dma_dbg_cmd_done_q = _RAND_71[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin RdPtr = 3'h0; @@ -79593,27 +79409,6 @@ initial begin if (reset) begin fifo_data_4 = 64'h0; end - if (reset) begin - fifo_tag_0 = 1'h0; - end - if (reset) begin - wrbuf_tag = 1'h0; - end - if (reset) begin - rdbuf_tag = 1'h0; - end - if (reset) begin - fifo_tag_1 = 1'h0; - end - if (reset) begin - fifo_tag_2 = 1'h0; - end - if (reset) begin - fifo_tag_3 = 1'h0; - end - if (reset) begin - fifo_tag_4 = 1'h0; - end if (reset) begin dma_nack_count = 3'h0; end @@ -80232,71 +80027,6 @@ end // initial fifo_data_4 <= _T_500; end end - always @(posedge dma_buffer_c1_clk or posedge reset) begin - if (reset) begin - fifo_tag_0 <= 1'h0; - end else if (fifo_cmd_en[0]) begin - if (axi_mstr_sel) begin - fifo_tag_0 <= wrbuf_tag; - end else begin - fifo_tag_0 <= rdbuf_tag; - end - end - end - always @(posedge dma_bus_clk or posedge reset) begin - if (reset) begin - wrbuf_tag <= 1'h0; - end else if (wrbuf_en) begin - wrbuf_tag <= io_dma_axi_aw_bits_id; - end - end - always @(posedge dma_bus_clk or posedge reset) begin - if (reset) begin - rdbuf_tag <= 1'h0; - end else if (rdbuf_en) begin - rdbuf_tag <= io_dma_axi_ar_bits_id; - end - end - always @(posedge dma_buffer_c1_clk or posedge reset) begin - if (reset) begin - fifo_tag_1 <= 1'h0; - end else if (fifo_cmd_en[1]) begin - if (axi_mstr_sel) begin - fifo_tag_1 <= wrbuf_tag; - end else begin - fifo_tag_1 <= rdbuf_tag; - end - end - end - always @(posedge dma_buffer_c1_clk or posedge reset) begin - if (reset) begin - fifo_tag_2 <= 1'h0; - end else if (fifo_cmd_en[2]) begin - if (axi_mstr_sel) begin - fifo_tag_2 <= wrbuf_tag; - end else begin - fifo_tag_2 <= rdbuf_tag; - end - end - end - always @(posedge dma_buffer_c1_clk or posedge reset) begin - if (reset) begin - fifo_tag_3 <= 1'h0; - end else if (fifo_cmd_en[3]) begin - if (axi_mstr_sel) begin - fifo_tag_3 <= wrbuf_tag; - end else begin - fifo_tag_3 <= rdbuf_tag; - end - end - end - always @(posedge dma_buffer_c1_clk or posedge reset) begin - if (reset) begin - fifo_tag_4 <= 1'h0; - end else if (fifo_cmd_en[4]) begin - fifo_tag_4 <= bus_cmd_tag; - end - end always @(posedge dma_free_clk or posedge reset) begin if (reset) begin dma_nack_count <= 3'h0; @@ -80319,23 +80049,41 @@ end // initial end endmodule module axi4_to_ahb( - input clock, - input reset, - input io_scan_mode, - input io_bus_clk_en, - input io_clk_override, - input io_axi_awvalid, - input io_axi_wvalid, - input io_axi_bready, - input io_axi_arvalid, - input io_axi_rready, - output io_axi_awready, - output io_axi_wready + input clock, + input reset, + input io_scan_mode, + input io_bus_clk_en, + input io_clk_override, + input io_axi_awvalid, + input io_axi_awid, + input io_axi_wvalid, + input [63:0] io_axi_wdata, + input io_axi_bready, + input io_axi_arvalid, + input io_axi_arid, + input io_axi_rready, + output io_axi_awready, + output io_axi_wready, + output io_axi_bvalid, + output [1:0] io_axi_bresp, + output io_axi_bid, + output io_axi_arready, + output io_axi_rvalid, + output io_axi_rid, + output [63:0] io_axi_rdata, + output [1:0] io_axi_rresp ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; reg [31:0] _RAND_1; reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [63:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [63:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[lib.scala 327:22] wire rvclkhdr_io_clk; // @[lib.scala 327:22] @@ -80437,6 +80185,27 @@ module axi4_to_ahb( wire [2:0] _GEN_68 = _T_136 ? _T_154 : _GEN_50; // @[Conditional.scala 39:67] wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] + reg wrbuf_tag; // @[Reg.scala 27:20] + reg [63:0] wrbuf_data; // @[lib.scala 358:16] + wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 309:55] + wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 309:39] + wire _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67] + wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] + wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] + wire _GEN_52 = _T_175 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_136 ? buf_state_en : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] + wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] + wire _T_25 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 188:32] + wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 157:21 axi4_to_ahb.scala 409:12] + reg slvbuf_write; // @[Reg.scala 27:20] + wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 362:23] + wire [3:0] slave_opc = {_T_596,2'h0}; // @[Cat.scala 29:58] + wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 189:49] + reg slvbuf_tag; // @[Reg.scala 27:20] + wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 192:65] + wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 363:91] + reg [63:0] buf_data; // @[lib.scala 358:16] wire _T_44 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 199:56] wire _T_45 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 199:91] wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 199:74] @@ -80465,6 +80234,8 @@ module axi4_to_ahb( wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] + wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 345:33] + reg buf_write; // @[Reg.scala 27:20] wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 368:47] wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 369:50] wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 370:49] @@ -80475,9 +80246,11 @@ module axi4_to_ahb( wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 373:21] wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 374:37] wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 374:20] + wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 375:21] wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 378:55] wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 378:91] wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 379:55] + reg buf_tag; // @[Reg.scala 27:20] wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 404:43] wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 404:58] wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 406:50] @@ -80544,6 +80317,14 @@ module axi4_to_ahb( ); assign io_axi_awready = _T_626 & master_ready; // @[axi4_to_ahb.scala 373:18] assign io_axi_wready = _T_630 & master_ready; // @[axi4_to_ahb.scala 374:17] + assign io_axi_bvalid = _T_25 & slave_opc[3]; // @[axi4_to_ahb.scala 188:17] + assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 189:16] + assign io_axi_bid = slvbuf_tag; // @[axi4_to_ahb.scala 190:14] + assign io_axi_arready = _T_633 & master_ready; // @[axi4_to_ahb.scala 375:18] + assign io_axi_rvalid = _T_25 & _T_35; // @[axi4_to_ahb.scala 192:17] + assign io_axi_rid = slvbuf_tag; // @[axi4_to_ahb.scala 194:14] + assign io_axi_rdata = _T_604 ? buf_data : 64'h0; // @[axi4_to_ahb.scala 195:16] + assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 193:16] assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17] assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 329:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 330:23] @@ -80615,6 +80396,20 @@ initial begin wrbuf_vld = _RAND_1[0:0]; _RAND_2 = {1{`RANDOM}}; wrbuf_data_vld = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + wrbuf_tag = _RAND_3[0:0]; + _RAND_4 = {2{`RANDOM}}; + wrbuf_data = _RAND_4[63:0]; + _RAND_5 = {1{`RANDOM}}; + slvbuf_write = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + slvbuf_tag = _RAND_6[0:0]; + _RAND_7 = {2{`RANDOM}}; + buf_data = _RAND_7[63:0]; + _RAND_8 = {1{`RANDOM}}; + buf_write = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + buf_tag = _RAND_9[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin buf_state = 3'h0; @@ -80625,6 +80420,27 @@ initial begin if (reset) begin wrbuf_data_vld = 1'h0; end + if (reset) begin + wrbuf_tag = 1'h0; + end + if (reset) begin + wrbuf_data = 64'h0; + end + if (reset) begin + slvbuf_write = 1'h0; + end + if (reset) begin + slvbuf_tag = 1'h0; + end + if (reset) begin + buf_data = 64'h0; + end + if (reset) begin + buf_write = 1'h0; + end + if (reset) begin + buf_tag = 1'h0; + end `endif // RANDOMIZE end // initial `ifdef FIRRTL_AFTER_INITIAL @@ -80690,6 +80506,75 @@ end // initial wrbuf_data_vld <= _T_641 & _T_637; end end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_tag <= 1'h0; + end else if (wrbuf_en) begin + wrbuf_tag <= io_axi_awid; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + wrbuf_data <= 64'h0; + end else begin + wrbuf_data <= io_axi_wdata; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + slvbuf_write <= 1'h0; + end else if (slvbuf_wr_en) begin + slvbuf_write <= buf_write; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + slvbuf_tag <= 1'h0; + end else if (slvbuf_wr_en) begin + slvbuf_tag <= buf_tag; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + buf_data <= 64'h0; + end else if (_T_489) begin + buf_data <= 64'h0; + end else begin + buf_data <= wrbuf_data; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_write <= 1'h0; + end else if (buf_wr_en) begin + if (_T_49) begin + buf_write <= _T_51; + end else if (_T_101) begin + buf_write <= 1'h0; + end else if (_T_136) begin + buf_write <= 1'h0; + end else if (_T_175) begin + buf_write <= 1'h0; + end else if (_T_186) begin + buf_write <= 1'h0; + end else if (_T_188) begin + buf_write <= 1'h0; + end else begin + buf_write <= _GEN_8; + end + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_tag <= 1'h0; + end else if (buf_wr_en) begin + if (wr_cmd_vld) begin + buf_tag <= wrbuf_tag; + end else begin + buf_tag <= io_axi_arid; + end + end + end endmodule module ahb_to_axi4( input clock, @@ -80699,15 +80584,25 @@ module ahb_to_axi4( input io_axi_awready, input io_axi_arready, input io_axi_rvalid, + input [63:0] io_axi_rdata, input [1:0] io_axi_rresp, input [31:0] io_ahb_haddr, input [2:0] io_ahb_hsize, input [1:0] io_ahb_htrans, input io_ahb_hwrite, + input [63:0] io_ahb_hwdata, input io_ahb_hsel, input io_ahb_hreadyin, output io_axi_awvalid, + output [31:0] io_axi_awaddr, + output [2:0] io_axi_awsize, + output io_axi_wvalid, + output [63:0] io_axi_wdata, + output [7:0] io_axi_wstrb, output io_axi_arvalid, + output [31:0] io_axi_araddr, + output [2:0] io_axi_arsize, + output [63:0] io_ahb_hrdata, output io_ahb_hreadyout, output io_ahb_hresp ); @@ -80720,8 +80615,13 @@ module ahb_to_axi4( reg [31:0] _RAND_5; reg [31:0] _RAND_6; reg [31:0] _RAND_7; - reg [31:0] _RAND_8; + reg [63:0] _RAND_8; reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [63:0] _RAND_14; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[lib.scala 327:22] wire rvclkhdr_io_clk; // @[lib.scala 327:22] @@ -80798,9 +80698,28 @@ module ahb_to_axi4( wire cmdbuf_wr_en = _T_6 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58] wire buf_rdata_en = _T_6 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58] reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 166:65] + wire _T_45 = ahb_hsize_q == 3'h0; // @[ahb_to_axi4.scala 139:60] + wire [7:0] _T_47 = _T_45 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_49 = 8'h1 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 139:78] + wire [7:0] _T_50 = _T_47 & _T_49; // @[ahb_to_axi4.scala 139:70] wire _T_52 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 140:30] + wire [7:0] _T_54 = _T_52 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [8:0] _T_56 = 9'h3 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 140:48] + wire [8:0] _GEN_23 = {{1'd0}, _T_54}; // @[ahb_to_axi4.scala 140:40] + wire [8:0] _T_57 = _GEN_23 & _T_56; // @[ahb_to_axi4.scala 140:40] + wire [8:0] _GEN_24 = {{1'd0}, _T_50}; // @[ahb_to_axi4.scala 139:109] + wire [8:0] _T_58 = _GEN_24 | _T_57; // @[ahb_to_axi4.scala 139:109] wire _T_60 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 141:30] + wire [7:0] _T_62 = _T_60 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [10:0] _T_64 = 11'hf << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 141:48] + wire [10:0] _GEN_25 = {{3'd0}, _T_62}; // @[ahb_to_axi4.scala 141:40] + wire [10:0] _T_65 = _GEN_25 & _T_64; // @[ahb_to_axi4.scala 141:40] + wire [10:0] _GEN_26 = {{2'd0}, _T_58}; // @[ahb_to_axi4.scala 140:79] + wire [10:0] _T_66 = _GEN_26 | _T_65; // @[ahb_to_axi4.scala 140:79] wire _T_68 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 142:30] + wire [7:0] _T_70 = _T_68 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [10:0] _GEN_27 = {{3'd0}, _T_70}; // @[ahb_to_axi4.scala 141:79] + wire [10:0] _T_72 = _T_66 | _GEN_27; // @[ahb_to_axi4.scala 141:79] reg ahb_hready_q; // @[ahb_to_axi4.scala 164:60] wire _T_73 = ~ahb_hready_q; // @[ahb_to_axi4.scala 145:66] reg ahb_hresp_q; // @[ahb_to_axi4.scala 163:60] @@ -80816,6 +80735,8 @@ module ahb_to_axi4( wire _T_83 = ~buf_read_error; // @[ahb_to_axi4.scala 145:167] wire _T_84 = _T_82 & _T_83; // @[ahb_to_axi4.scala 145:165] wire [1:0] _T_88 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire buf_rdata_clk = rvclkhdr_2_io_l1clk; // @[ahb_to_axi4.scala 87:33 ahb_to_axi4.scala 176:31] + reg [63:0] buf_rdata; // @[ahb_to_axi4.scala 159:66] reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 165:60] wire _T_93 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 149:54] wire _T_94 = buf_state != 2'h0; // @[ahb_to_axi4.scala 149:76] @@ -80847,6 +80768,12 @@ module ahb_to_axi4( wire cmdbuf_rst = _T_146 | _T_148; // @[ahb_to_axi4.scala 178:124] wire _T_156 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 181:66] wire _T_157 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 181:110] + reg [2:0] _T_163; // @[Reg.scala 27:20] + reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20] + wire [7:0] master_wstrb = _T_72[7:0]; // @[ahb_to_axi4.scala 139:31] + reg [31:0] cmdbuf_addr; // @[lib.scala 358:16] + reg [63:0] cmdbuf_wdata; // @[lib.scala 358:16] + wire [1:0] cmdbuf_size = _T_163[1:0]; // @[ahb_to_axi4.scala 187:31] rvclkhdr rvclkhdr ( // @[lib.scala 327:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -80884,7 +80811,15 @@ module ahb_to_axi4( .io_scan_mode(rvclkhdr_5_io_scan_mode) ); assign io_axi_awvalid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 198:27] + assign io_axi_awaddr = cmdbuf_addr; // @[ahb_to_axi4.scala 200:27] + assign io_axi_awsize = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 201:27] + assign io_axi_wvalid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 206:27] + assign io_axi_wdata = cmdbuf_wdata; // @[ahb_to_axi4.scala 207:27] + assign io_axi_wstrb = cmdbuf_wstrb; // @[ahb_to_axi4.scala 208:27] assign io_axi_arvalid = cmdbuf_vld & _T_37; // @[ahb_to_axi4.scala 213:27] + assign io_axi_araddr = cmdbuf_addr; // @[ahb_to_axi4.scala 215:27] + assign io_axi_arsize = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 216:27] + assign io_ahb_hrdata = buf_rdata; // @[ahb_to_axi4.scala 148:31] assign io_ahb_hreadyout = io_ahb_hresp ? _T_74 : _T_84; // @[ahb_to_axi4.scala 145:31] assign io_ahb_hresp = _T_126 | _T_74; // @[ahb_to_axi4.scala 149:31] assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17] @@ -80956,10 +80891,20 @@ initial begin ahb_hresp_q = _RAND_6[0:0]; _RAND_7 = {1{`RANDOM}}; buf_read_error = _RAND_7[0:0]; - _RAND_8 = {1{`RANDOM}}; - ahb_htrans_q = _RAND_8[1:0]; + _RAND_8 = {2{`RANDOM}}; + buf_rdata = _RAND_8[63:0]; _RAND_9 = {1{`RANDOM}}; - ahb_hwrite_q = _RAND_9[0:0]; + ahb_htrans_q = _RAND_9[1:0]; + _RAND_10 = {1{`RANDOM}}; + ahb_hwrite_q = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + _T_163 = _RAND_11[2:0]; + _RAND_12 = {1{`RANDOM}}; + cmdbuf_wstrb = _RAND_12[7:0]; + _RAND_13 = {1{`RANDOM}}; + cmdbuf_addr = _RAND_13[31:0]; + _RAND_14 = {2{`RANDOM}}; + cmdbuf_wdata = _RAND_14[63:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin ahb_haddr_q = 32'h0; @@ -80985,12 +80930,27 @@ initial begin if (reset) begin buf_read_error = 1'h0; end + if (reset) begin + buf_rdata = 64'h0; + end if (reset) begin ahb_htrans_q = 2'h0; end if (reset) begin ahb_hwrite_q = 1'h0; end + if (reset) begin + _T_163 = 3'h0; + end + if (reset) begin + cmdbuf_wstrb = 8'h0; + end + if (reset) begin + cmdbuf_addr = 32'h0; + end + if (reset) begin + cmdbuf_wdata = 64'h0; + end `endif // RANDOMIZE end // initial `ifdef FIRRTL_AFTER_INITIAL @@ -81081,6 +81041,13 @@ end // initial buf_read_error <= _GEN_3; end end + always @(posedge buf_rdata_clk or posedge reset) begin + if (reset) begin + buf_rdata <= 64'h0; + end else begin + buf_rdata <= io_axi_rdata; + end + end always @(posedge ahb_clk or posedge reset) begin if (reset) begin ahb_htrans_q <= 2'h0; @@ -81095,26 +81062,48 @@ end // initial ahb_hwrite_q <= io_ahb_hwrite; end end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + _T_163 <= 3'h0; + end else if (cmdbuf_wr_en) begin + _T_163 <= ahb_hsize_q; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + cmdbuf_wstrb <= 8'h0; + end else if (cmdbuf_wr_en) begin + cmdbuf_wstrb <= master_wstrb; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + cmdbuf_addr <= 32'h0; + end else begin + cmdbuf_addr <= ahb_haddr_q; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + cmdbuf_wdata <= 64'h0; + end else begin + cmdbuf_wdata <= io_ahb_hwdata; + end + end endmodule module quasar( input clock, input reset, - input io_lsu_axi_aw_ready, output io_lsu_axi_aw_valid, output [2:0] io_lsu_axi_aw_bits_id, output [31:0] io_lsu_axi_aw_bits_addr, output [3:0] io_lsu_axi_aw_bits_region, output [2:0] io_lsu_axi_aw_bits_size, output [3:0] io_lsu_axi_aw_bits_cache, - input io_lsu_axi_w_ready, output io_lsu_axi_w_valid, output [63:0] io_lsu_axi_w_bits_data, output [7:0] io_lsu_axi_w_bits_strb, output io_lsu_axi_b_ready, - input io_lsu_axi_b_valid, - input [1:0] io_lsu_axi_b_bits_resp, - input [2:0] io_lsu_axi_b_bits_id, - input io_lsu_axi_ar_ready, output io_lsu_axi_ar_valid, output [2:0] io_lsu_axi_ar_bits_id, output [31:0] io_lsu_axi_ar_bits_addr, @@ -81122,65 +81111,38 @@ module quasar( output [2:0] io_lsu_axi_ar_bits_size, output [3:0] io_lsu_axi_ar_bits_cache, output io_lsu_axi_r_ready, - input io_lsu_axi_r_valid, - input [2:0] io_lsu_axi_r_bits_id, - input [63:0] io_lsu_axi_r_bits_data, - input [1:0] io_lsu_axi_r_bits_resp, output io_ifu_axi_aw_valid, + output [2:0] io_ifu_axi_aw_bits_id, output io_ifu_axi_w_valid, + output [63:0] io_ifu_axi_w_bits_data, output io_ifu_axi_b_ready, - input io_ifu_axi_ar_ready, output io_ifu_axi_ar_valid, output [2:0] io_ifu_axi_ar_bits_id, output [31:0] io_ifu_axi_ar_bits_addr, output [3:0] io_ifu_axi_ar_bits_region, output io_ifu_axi_r_ready, - input io_ifu_axi_r_valid, - input [2:0] io_ifu_axi_r_bits_id, - input [63:0] io_ifu_axi_r_bits_data, - input [1:0] io_ifu_axi_r_bits_resp, - input io_sb_axi_aw_ready, output io_sb_axi_aw_valid, + output io_sb_axi_aw_bits_id, output [31:0] io_sb_axi_aw_bits_addr, output [3:0] io_sb_axi_aw_bits_region, output [2:0] io_sb_axi_aw_bits_size, - input io_sb_axi_w_ready, output io_sb_axi_w_valid, output [63:0] io_sb_axi_w_bits_data, output [7:0] io_sb_axi_w_bits_strb, output io_sb_axi_b_ready, - input io_sb_axi_b_valid, - input [1:0] io_sb_axi_b_bits_resp, - input io_sb_axi_ar_ready, output io_sb_axi_ar_valid, + output io_sb_axi_ar_bits_id, output [31:0] io_sb_axi_ar_bits_addr, output [3:0] io_sb_axi_ar_bits_region, output [2:0] io_sb_axi_ar_bits_size, output io_sb_axi_r_ready, - input io_sb_axi_r_valid, - input [63:0] io_sb_axi_r_bits_data, - input [1:0] io_sb_axi_r_bits_resp, output io_dma_axi_aw_ready, - input io_dma_axi_aw_valid, - input io_dma_axi_aw_bits_id, - input [31:0] io_dma_axi_aw_bits_addr, - input [2:0] io_dma_axi_aw_bits_size, output io_dma_axi_w_ready, - input io_dma_axi_w_valid, - input [63:0] io_dma_axi_w_bits_data, - input [7:0] io_dma_axi_w_bits_strb, - input io_dma_axi_b_ready, output io_dma_axi_b_valid, output [1:0] io_dma_axi_b_bits_resp, - output io_dma_axi_b_bits_id, output io_dma_axi_ar_ready, input io_dma_axi_ar_valid, - input io_dma_axi_ar_bits_id, - input [31:0] io_dma_axi_ar_bits_addr, - input [2:0] io_dma_axi_ar_bits_size, - input io_dma_axi_r_ready, output io_dma_axi_r_valid, - output io_dma_axi_r_bits_id, output [63:0] io_dma_axi_r_bits_data, output [1:0] io_dma_axi_r_bits_resp, input io_dbg_rst_l, @@ -81188,13 +81150,13 @@ module quasar( input io_nmi_int, input [30:0] io_nmi_vec, output io_core_rst_l, - output [31:0] io_trace_rv_i_insn_ip, - output [31:0] io_trace_rv_i_address_ip, - output [1:0] io_trace_rv_i_valid_ip, - output [1:0] io_trace_rv_i_exception_ip, - output [4:0] io_trace_rv_i_ecause_ip, - output [1:0] io_trace_rv_i_interrupt_ip, - output [31:0] io_trace_rv_i_tval_ip, + output [1:0] io_rv_trace_pkt_rv_i_valid_ip, + output [31:0] io_rv_trace_pkt_rv_i_insn_ip, + output [31:0] io_rv_trace_pkt_rv_i_address_ip, + output [1:0] io_rv_trace_pkt_rv_i_exception_ip, + output [4:0] io_rv_trace_pkt_rv_i_ecause_ip, + output [1:0] io_rv_trace_pkt_rv_i_interrupt_ip, + output [31:0] io_rv_trace_pkt_rv_i_tval_ip, output io_dccm_clk_override, output io_icm_clk_override, output io_dec_tlu_core_ecc_disable, @@ -81259,7 +81221,11 @@ module quasar( input [2:0] io_dma_hsize, input [1:0] io_dma_htrans, input io_dma_hwrite, + input [63:0] io_dma_hwdata, input io_dma_hreadyin, + output [63:0] io_dma_hrdata, + output io_dma_hreadyout, + output io_dma_hresp, input io_lsu_bus_clk_en, input io_ifu_bus_clk_en, input io_dbg_bus_clk_en, @@ -81273,792 +81239,785 @@ module quasar( input io_soft_int, input io_scan_mode ); - wire ifu_clock; // @[quasar.scala 122:19] - wire ifu_reset; // @[quasar.scala 122:19] - wire ifu_io_exu_flush_final; // @[quasar.scala 122:19] - wire [30:0] ifu_io_exu_flush_path_final; // @[quasar.scala 122:19] - wire ifu_io_free_clk; // @[quasar.scala 122:19] - wire ifu_io_active_clk; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 122:19] - wire [15:0] ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 122:19] - wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 122:19] - wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 122:19] - wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 122:19] - wire [4:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 122:19] - wire [31:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 122:19] - wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 122:19] - wire [11:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 122:19] - wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 122:19] - wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_lower_wb; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 122:19] - wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 122:19] - wire [16:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 122:19] - wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 122:19] - wire [31:0] ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 122:19] - wire [1:0] ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 122:19] - wire ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 122:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r; // @[quasar.scala 122:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 122:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 122:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 122:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 122:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 122:19] - wire [1:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 122:19] - wire [11:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 122:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 122:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 122:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 122:19] - wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 122:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_eghr; // @[quasar.scala 122:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_fghr; // @[quasar.scala 122:19] - wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_index; // @[quasar.scala 122:19] - wire [4:0] ifu_io_exu_ifu_exu_bp_exu_mp_btag; // @[quasar.scala 122:19] - wire [14:0] ifu_io_iccm_rw_addr; // @[quasar.scala 122:19] - wire ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 122:19] - wire ifu_io_iccm_correction_state; // @[quasar.scala 122:19] - wire ifu_io_iccm_wren; // @[quasar.scala 122:19] - wire ifu_io_iccm_rden; // @[quasar.scala 122:19] - wire [2:0] ifu_io_iccm_wr_size; // @[quasar.scala 122:19] - wire [77:0] ifu_io_iccm_wr_data; // @[quasar.scala 122:19] - wire [63:0] ifu_io_iccm_rd_data; // @[quasar.scala 122:19] - wire [77:0] ifu_io_iccm_rd_data_ecc; // @[quasar.scala 122:19] - wire [30:0] ifu_io_ic_rw_addr; // @[quasar.scala 122:19] - wire [1:0] ifu_io_ic_tag_valid; // @[quasar.scala 122:19] - wire [1:0] ifu_io_ic_wr_en; // @[quasar.scala 122:19] - wire ifu_io_ic_rd_en; // @[quasar.scala 122:19] - wire [70:0] ifu_io_ic_wr_data_0; // @[quasar.scala 122:19] - wire [70:0] ifu_io_ic_wr_data_1; // @[quasar.scala 122:19] - wire [70:0] ifu_io_ic_debug_wr_data; // @[quasar.scala 122:19] - wire [9:0] ifu_io_ic_debug_addr; // @[quasar.scala 122:19] - wire [63:0] ifu_io_ic_rd_data; // @[quasar.scala 122:19] - wire [70:0] ifu_io_ic_debug_rd_data; // @[quasar.scala 122:19] - wire [25:0] ifu_io_ic_tag_debug_rd_data; // @[quasar.scala 122:19] - wire [1:0] ifu_io_ic_eccerr; // @[quasar.scala 122:19] - wire [1:0] ifu_io_ic_rd_hit; // @[quasar.scala 122:19] - wire ifu_io_ic_tag_perr; // @[quasar.scala 122:19] - wire ifu_io_ic_debug_rd_en; // @[quasar.scala 122:19] - wire ifu_io_ic_debug_wr_en; // @[quasar.scala 122:19] - wire ifu_io_ic_debug_tag_array; // @[quasar.scala 122:19] - wire [1:0] ifu_io_ic_debug_way; // @[quasar.scala 122:19] - wire [63:0] ifu_io_ic_premux_data; // @[quasar.scala 122:19] - wire ifu_io_ic_sel_premux_data; // @[quasar.scala 122:19] - wire ifu_io_ifu_ar_ready; // @[quasar.scala 122:19] - wire ifu_io_ifu_ar_valid; // @[quasar.scala 122:19] - wire [2:0] ifu_io_ifu_ar_bits_id; // @[quasar.scala 122:19] - wire [31:0] ifu_io_ifu_ar_bits_addr; // @[quasar.scala 122:19] - wire [3:0] ifu_io_ifu_ar_bits_region; // @[quasar.scala 122:19] - wire ifu_io_ifu_r_valid; // @[quasar.scala 122:19] - wire [2:0] ifu_io_ifu_r_bits_id; // @[quasar.scala 122:19] - wire [63:0] ifu_io_ifu_r_bits_data; // @[quasar.scala 122:19] - wire [1:0] ifu_io_ifu_r_bits_resp; // @[quasar.scala 122:19] - wire ifu_io_ifu_bus_clk_en; // @[quasar.scala 122:19] - wire ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 122:19] - wire ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 122:19] - wire [31:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 122:19] - wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 122:19] - wire ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 122:19] - wire [63:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 122:19] - wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 122:19] - wire ifu_io_iccm_dma_ecc_error; // @[quasar.scala 122:19] - wire ifu_io_iccm_dma_rvalid; // @[quasar.scala 122:19] - wire [63:0] ifu_io_iccm_dma_rdata; // @[quasar.scala 122:19] - wire [2:0] ifu_io_iccm_dma_rtag; // @[quasar.scala 122:19] - wire ifu_io_iccm_ready; // @[quasar.scala 122:19] - wire ifu_io_iccm_dma_sb_error; // @[quasar.scala 122:19] - wire ifu_io_scan_mode; // @[quasar.scala 122:19] - wire dec_clock; // @[quasar.scala 123:19] - wire dec_reset; // @[quasar.scala 123:19] - wire dec_io_free_clk; // @[quasar.scala 123:19] - wire dec_io_active_clk; // @[quasar.scala 123:19] - wire dec_io_lsu_fastint_stall_any; // @[quasar.scala 123:19] - wire dec_io_dec_pause_state_cg; // @[quasar.scala 123:19] - wire [30:0] dec_io_rst_vec; // @[quasar.scala 123:19] - wire dec_io_nmi_int; // @[quasar.scala 123:19] - wire [30:0] dec_io_nmi_vec; // @[quasar.scala 123:19] - wire dec_io_i_cpu_halt_req; // @[quasar.scala 123:19] - wire dec_io_i_cpu_run_req; // @[quasar.scala 123:19] - wire dec_io_o_cpu_halt_status; // @[quasar.scala 123:19] - wire dec_io_o_cpu_halt_ack; // @[quasar.scala 123:19] - wire dec_io_o_cpu_run_ack; // @[quasar.scala 123:19] - wire dec_io_o_debug_mode_status; // @[quasar.scala 123:19] - wire [27:0] dec_io_core_id; // @[quasar.scala 123:19] - wire dec_io_mpc_debug_halt_req; // @[quasar.scala 123:19] - wire dec_io_mpc_debug_run_req; // @[quasar.scala 123:19] - wire dec_io_mpc_reset_run_req; // @[quasar.scala 123:19] - wire dec_io_mpc_debug_halt_ack; // @[quasar.scala 123:19] - wire dec_io_mpc_debug_run_ack; // @[quasar.scala 123:19] - wire dec_io_debug_brkpt_status; // @[quasar.scala 123:19] - wire dec_io_lsu_pmu_misaligned_m; // @[quasar.scala 123:19] - wire dec_io_dma_pmu_dccm_read; // @[quasar.scala 123:19] - wire dec_io_dma_pmu_dccm_write; // @[quasar.scala 123:19] - wire dec_io_dma_pmu_any_read; // @[quasar.scala 123:19] - wire dec_io_dma_pmu_any_write; // @[quasar.scala 123:19] - wire [30:0] dec_io_lsu_fir_addr; // @[quasar.scala 123:19] - wire [1:0] dec_io_lsu_fir_error; // @[quasar.scala 123:19] - wire [3:0] dec_io_lsu_trigger_match_m; // @[quasar.scala 123:19] - wire dec_io_lsu_idle_any; // @[quasar.scala 123:19] - wire dec_io_lsu_error_pkt_r_valid; // @[quasar.scala 123:19] - wire dec_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 123:19] - wire dec_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 123:19] - wire dec_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 123:19] - wire [3:0] dec_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 123:19] - wire [31:0] dec_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 123:19] - wire dec_io_lsu_single_ecc_error_incr; // @[quasar.scala 123:19] - wire [31:0] dec_io_exu_div_result; // @[quasar.scala 123:19] - wire dec_io_exu_div_wren; // @[quasar.scala 123:19] - wire [31:0] dec_io_lsu_result_m; // @[quasar.scala 123:19] - wire [31:0] dec_io_lsu_result_corr_r; // @[quasar.scala 123:19] - wire dec_io_lsu_load_stall_any; // @[quasar.scala 123:19] - wire dec_io_lsu_store_stall_any; // @[quasar.scala 123:19] - wire dec_io_dma_dccm_stall_any; // @[quasar.scala 123:19] - wire dec_io_dma_iccm_stall_any; // @[quasar.scala 123:19] - wire dec_io_iccm_dma_sb_error; // @[quasar.scala 123:19] - wire dec_io_exu_flush_final; // @[quasar.scala 123:19] - wire dec_io_mexintpend; // @[quasar.scala 123:19] - wire dec_io_timer_int; // @[quasar.scala 123:19] - wire dec_io_soft_int; // @[quasar.scala 123:19] - wire [7:0] dec_io_pic_claimid; // @[quasar.scala 123:19] - wire [3:0] dec_io_pic_pl; // @[quasar.scala 123:19] - wire dec_io_mhwakeup; // @[quasar.scala 123:19] - wire [3:0] dec_io_dec_tlu_meicurpl; // @[quasar.scala 123:19] - wire [3:0] dec_io_dec_tlu_meipt; // @[quasar.scala 123:19] - wire dec_io_dbg_halt_req; // @[quasar.scala 123:19] - wire dec_io_dbg_resume_req; // @[quasar.scala 123:19] - wire dec_io_dec_tlu_dbg_halted; // @[quasar.scala 123:19] - wire dec_io_dec_tlu_debug_mode; // @[quasar.scala 123:19] - wire dec_io_dec_tlu_resume_ack; // @[quasar.scala 123:19] - wire dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 123:19] - wire [31:0] dec_io_dec_dbg_rddata; // @[quasar.scala 123:19] - wire dec_io_dec_dbg_cmd_done; // @[quasar.scala 123:19] - wire dec_io_dec_dbg_cmd_fail; // @[quasar.scala 123:19] - wire dec_io_trigger_pkt_any_0_select; // @[quasar.scala 123:19] - wire dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 123:19] - wire dec_io_trigger_pkt_any_0_store; // @[quasar.scala 123:19] - wire dec_io_trigger_pkt_any_0_load; // @[quasar.scala 123:19] - wire [31:0] dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 123:19] - wire dec_io_trigger_pkt_any_1_select; // @[quasar.scala 123:19] - wire dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 123:19] - wire dec_io_trigger_pkt_any_1_store; // @[quasar.scala 123:19] - wire dec_io_trigger_pkt_any_1_load; // @[quasar.scala 123:19] - wire [31:0] dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 123:19] - wire dec_io_trigger_pkt_any_2_select; // @[quasar.scala 123:19] - wire dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 123:19] - wire dec_io_trigger_pkt_any_2_store; // @[quasar.scala 123:19] - wire dec_io_trigger_pkt_any_2_load; // @[quasar.scala 123:19] - wire [31:0] dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 123:19] - wire dec_io_trigger_pkt_any_3_select; // @[quasar.scala 123:19] - wire dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 123:19] - wire dec_io_trigger_pkt_any_3_store; // @[quasar.scala 123:19] - wire dec_io_trigger_pkt_any_3_load; // @[quasar.scala 123:19] - wire [31:0] dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 123:19] - wire dec_io_exu_i0_br_way_r; // @[quasar.scala 123:19] - wire dec_io_lsu_p_valid; // @[quasar.scala 123:19] - wire dec_io_lsu_p_bits_fast_int; // @[quasar.scala 123:19] - wire dec_io_lsu_p_bits_by; // @[quasar.scala 123:19] - wire dec_io_lsu_p_bits_half; // @[quasar.scala 123:19] - wire dec_io_lsu_p_bits_word; // @[quasar.scala 123:19] - wire dec_io_lsu_p_bits_load; // @[quasar.scala 123:19] - wire dec_io_lsu_p_bits_store; // @[quasar.scala 123:19] - wire dec_io_lsu_p_bits_unsign; // @[quasar.scala 123:19] - wire dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 123:19] - wire dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 123:19] - wire [11:0] dec_io_dec_lsu_offset_d; // @[quasar.scala 123:19] - wire dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 123:19] - wire dec_io_dec_tlu_perfcnt0; // @[quasar.scala 123:19] - wire dec_io_dec_tlu_perfcnt1; // @[quasar.scala 123:19] - wire dec_io_dec_tlu_perfcnt2; // @[quasar.scala 123:19] - wire dec_io_dec_tlu_perfcnt3; // @[quasar.scala 123:19] - wire dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 123:19] - wire [1:0] dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 123:19] - wire [31:0] dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 123:19] - wire [31:0] dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 123:19] - wire [1:0] dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 123:19] - wire [4:0] dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 123:19] - wire [1:0] dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 123:19] - wire [31:0] dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 123:19] - wire [2:0] dec_io_dec_tlu_dma_qos_prty; // @[quasar.scala 123:19] - wire dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 123:19] - wire dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 123:19] - wire dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 123:19] - wire dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 123:19] - wire dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 123:19] - wire dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 123:19] - wire dec_io_scan_mode; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 123:19] - wire [15:0] dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 123:19] - wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 123:19] - wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 123:19] - wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 123:19] - wire [4:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 123:19] - wire [31:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 123:19] - wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 123:19] - wire [11:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 123:19] - wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 123:19] - wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 123:19] - wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 123:19] - wire [16:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 123:19] - wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 123:19] - wire [31:0] dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 123:19] - wire [1:0] dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 123:19] - wire dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 123:19] - wire dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 123:19] - wire dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 123:19] - wire [11:0] dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 123:19] - wire [30:0] dec_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 123:19] - wire dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 123:19] - wire dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 123:19] - wire dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 123:19] - wire dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 123:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 123:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 123:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 123:19] - wire [11:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 123:19] - wire [30:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 123:19] - wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 123:19] - wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 123:19] - wire [4:0] dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 123:19] - wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 123:19] - wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 123:19] - wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 123:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 123:19] - wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 123:19] - wire [30:0] dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 123:19] - wire dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 123:19] - wire [31:0] dec_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 123:19] - wire [31:0] dec_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 123:19] - wire [29:0] dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 123:19] - wire dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 123:19] - wire [30:0] dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 123:19] - wire [1:0] dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 123:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 123:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 123:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 123:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 123:19] - wire dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 123:19] - wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 123:19] - wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 123:19] - wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 123:19] - wire [30:0] dec_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 123:19] - wire [30:0] dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 123:19] - wire dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 123:19] - wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 123:19] - wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 123:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 123:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 123:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 123:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 123:19] - wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 123:19] - wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 123:19] - wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 123:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 123:19] - wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 123:19] - wire [31:0] dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 123:19] - wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 123:19] - wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 123:19] - wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 123:19] - wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 123:19] - wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 123:19] - wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 123:19] - wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 123:19] - wire [31:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 123:19] - wire dec_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 123:19] - wire dec_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 123:19] - wire dec_io_dec_dbg_dbg_ib_dbg_cmd_valid; // @[quasar.scala 123:19] - wire dec_io_dec_dbg_dbg_ib_dbg_cmd_write; // @[quasar.scala 123:19] - wire [1:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_type; // @[quasar.scala 123:19] - wire [31:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_addr; // @[quasar.scala 123:19] - wire [1:0] dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 123:19] - wire dbg_clock; // @[quasar.scala 124:19] - wire dbg_reset; // @[quasar.scala 124:19] - wire [1:0] dbg_io_dbg_cmd_size; // @[quasar.scala 124:19] - wire dbg_io_dbg_core_rst_l; // @[quasar.scala 124:19] - wire [31:0] dbg_io_core_dbg_rddata; // @[quasar.scala 124:19] - wire dbg_io_core_dbg_cmd_done; // @[quasar.scala 124:19] - wire dbg_io_core_dbg_cmd_fail; // @[quasar.scala 124:19] - wire dbg_io_dbg_halt_req; // @[quasar.scala 124:19] - wire dbg_io_dbg_resume_req; // @[quasar.scala 124:19] - wire dbg_io_dec_tlu_debug_mode; // @[quasar.scala 124:19] - wire dbg_io_dec_tlu_dbg_halted; // @[quasar.scala 124:19] - wire dbg_io_dec_tlu_mpc_halted_only; // @[quasar.scala 124:19] - wire dbg_io_dec_tlu_resume_ack; // @[quasar.scala 124:19] - wire dbg_io_dmi_reg_en; // @[quasar.scala 124:19] - wire [6:0] dbg_io_dmi_reg_addr; // @[quasar.scala 124:19] - wire dbg_io_dmi_reg_wr_en; // @[quasar.scala 124:19] - wire [31:0] dbg_io_dmi_reg_wdata; // @[quasar.scala 124:19] - wire dbg_io_sb_axi_aw_ready; // @[quasar.scala 124:19] - wire dbg_io_sb_axi_aw_valid; // @[quasar.scala 124:19] - wire [31:0] dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 124:19] - wire [3:0] dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 124:19] - wire [2:0] dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 124:19] - wire dbg_io_sb_axi_w_ready; // @[quasar.scala 124:19] - wire dbg_io_sb_axi_w_valid; // @[quasar.scala 124:19] - wire [63:0] dbg_io_sb_axi_w_bits_data; // @[quasar.scala 124:19] - wire [7:0] dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 124:19] - wire dbg_io_sb_axi_b_ready; // @[quasar.scala 124:19] - wire dbg_io_sb_axi_b_valid; // @[quasar.scala 124:19] - wire [1:0] dbg_io_sb_axi_b_bits_resp; // @[quasar.scala 124:19] - wire dbg_io_sb_axi_ar_ready; // @[quasar.scala 124:19] - wire dbg_io_sb_axi_ar_valid; // @[quasar.scala 124:19] - wire [31:0] dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 124:19] - wire [3:0] dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 124:19] - wire [2:0] dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 124:19] - wire dbg_io_sb_axi_r_ready; // @[quasar.scala 124:19] - wire dbg_io_sb_axi_r_valid; // @[quasar.scala 124:19] - wire [63:0] dbg_io_sb_axi_r_bits_data; // @[quasar.scala 124:19] - wire [1:0] dbg_io_sb_axi_r_bits_resp; // @[quasar.scala 124:19] - wire dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 124:19] - wire dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 124:19] - wire [1:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 124:19] - wire [31:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 124:19] - wire [1:0] dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 124:19] - wire dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 124:19] - wire dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 124:19] - wire [1:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 124:19] - wire [31:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 124:19] - wire [1:0] dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 124:19] - wire dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 124:19] - wire dbg_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 124:19] - wire dbg_io_dbg_bus_clk_en; // @[quasar.scala 124:19] - wire dbg_io_dbg_rst_l; // @[quasar.scala 124:19] - wire dbg_io_clk_override; // @[quasar.scala 124:19] - wire dbg_io_scan_mode; // @[quasar.scala 124:19] - wire exu_clock; // @[quasar.scala 125:19] - wire exu_reset; // @[quasar.scala 125:19] - wire exu_io_scan_mode; // @[quasar.scala 125:19] - wire exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 125:19] - wire exu_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 125:19] - wire [11:0] exu_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 125:19] - wire [30:0] exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 125:19] - wire exu_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 125:19] - wire exu_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 125:19] - wire exu_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 125:19] - wire exu_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 125:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 125:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 125:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 125:19] - wire [11:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 125:19] - wire [30:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 125:19] - wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 125:19] - wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 125:19] - wire [4:0] exu_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 125:19] - wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 125:19] - wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 125:19] - wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 125:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 125:19] - wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 125:19] - wire [30:0] exu_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 125:19] - wire exu_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 125:19] - wire [31:0] exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 125:19] - wire [31:0] exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 125:19] - wire [29:0] exu_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 125:19] - wire exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 125:19] - wire [30:0] exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 125:19] - wire [1:0] exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 125:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 125:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 125:19] - wire [7:0] exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 125:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 125:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 125:19] - wire exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 125:19] - wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 125:19] - wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 125:19] - wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 125:19] - wire [30:0] exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 125:19] - wire [30:0] exu_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 125:19] - wire exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 125:19] - wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 125:19] - wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 125:19] - wire [7:0] exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 125:19] - wire exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 125:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 125:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 125:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 125:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 125:19] - wire [1:0] exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 125:19] - wire [11:0] exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 125:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 125:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 125:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 125:19] - wire exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 125:19] - wire [7:0] exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 125:19] - wire [7:0] exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 125:19] - wire [7:0] exu_io_exu_bp_exu_mp_index; // @[quasar.scala 125:19] - wire [4:0] exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 125:19] - wire exu_io_exu_flush_final; // @[quasar.scala 125:19] - wire [31:0] exu_io_exu_div_result; // @[quasar.scala 125:19] - wire exu_io_exu_div_wren; // @[quasar.scala 125:19] - wire [31:0] exu_io_dbg_cmd_wrdata; // @[quasar.scala 125:19] - wire [31:0] exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 125:19] - wire [31:0] exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 125:19] - wire [30:0] exu_io_exu_flush_path_final; // @[quasar.scala 125:19] - wire lsu_clock; // @[quasar.scala 126:19] - wire lsu_reset; // @[quasar.scala 126:19] - wire lsu_io_clk_override; // @[quasar.scala 126:19] - wire lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 126:19] - wire [31:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 126:19] - wire [2:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 126:19] - wire lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 126:19] - wire [63:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 126:19] - wire [31:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 126:19] - wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 126:19] - wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 126:19] - wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 126:19] - wire [2:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 126:19] - wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 126:19] - wire lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 126:19] - wire [2:0] lsu_io_lsu_dma_dma_mem_tag; // @[quasar.scala 126:19] - wire lsu_io_lsu_pic_picm_wren; // @[quasar.scala 126:19] - wire lsu_io_lsu_pic_picm_rden; // @[quasar.scala 126:19] - wire lsu_io_lsu_pic_picm_mken; // @[quasar.scala 126:19] - wire [31:0] lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 126:19] - wire [31:0] lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 126:19] - wire [31:0] lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 126:19] - wire [31:0] lsu_io_lsu_pic_picm_rd_data; // @[quasar.scala 126:19] - wire [31:0] lsu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 126:19] - wire [31:0] lsu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 126:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 126:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 126:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 126:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 126:19] - wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 126:19] - wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 126:19] - wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 126:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 126:19] - wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 126:19] - wire [31:0] lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 126:19] - wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 126:19] - wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 126:19] - wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 126:19] - wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 126:19] - wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 126:19] - wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 126:19] - wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 126:19] - wire [31:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 126:19] - wire lsu_io_dccm_wren; // @[quasar.scala 126:19] - wire lsu_io_dccm_rden; // @[quasar.scala 126:19] - wire [15:0] lsu_io_dccm_wr_addr_lo; // @[quasar.scala 126:19] - wire [15:0] lsu_io_dccm_wr_addr_hi; // @[quasar.scala 126:19] - wire [15:0] lsu_io_dccm_rd_addr_lo; // @[quasar.scala 126:19] - wire [15:0] lsu_io_dccm_rd_addr_hi; // @[quasar.scala 126:19] - wire [38:0] lsu_io_dccm_wr_data_lo; // @[quasar.scala 126:19] - wire [38:0] lsu_io_dccm_wr_data_hi; // @[quasar.scala 126:19] - wire [38:0] lsu_io_dccm_rd_data_lo; // @[quasar.scala 126:19] - wire [38:0] lsu_io_dccm_rd_data_hi; // @[quasar.scala 126:19] - wire lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 126:19] - wire lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 126:19] - wire lsu_io_axi_aw_ready; // @[quasar.scala 126:19] - wire lsu_io_axi_aw_valid; // @[quasar.scala 126:19] - wire [2:0] lsu_io_axi_aw_bits_id; // @[quasar.scala 126:19] - wire [31:0] lsu_io_axi_aw_bits_addr; // @[quasar.scala 126:19] - wire [3:0] lsu_io_axi_aw_bits_region; // @[quasar.scala 126:19] - wire [2:0] lsu_io_axi_aw_bits_size; // @[quasar.scala 126:19] - wire [3:0] lsu_io_axi_aw_bits_cache; // @[quasar.scala 126:19] - wire lsu_io_axi_w_ready; // @[quasar.scala 126:19] - wire lsu_io_axi_w_valid; // @[quasar.scala 126:19] - wire [63:0] lsu_io_axi_w_bits_data; // @[quasar.scala 126:19] - wire [7:0] lsu_io_axi_w_bits_strb; // @[quasar.scala 126:19] - wire lsu_io_axi_b_valid; // @[quasar.scala 126:19] - wire [1:0] lsu_io_axi_b_bits_resp; // @[quasar.scala 126:19] - wire [2:0] lsu_io_axi_b_bits_id; // @[quasar.scala 126:19] - wire lsu_io_axi_ar_ready; // @[quasar.scala 126:19] - wire lsu_io_axi_ar_valid; // @[quasar.scala 126:19] - wire [2:0] lsu_io_axi_ar_bits_id; // @[quasar.scala 126:19] - wire [31:0] lsu_io_axi_ar_bits_addr; // @[quasar.scala 126:19] - wire [3:0] lsu_io_axi_ar_bits_region; // @[quasar.scala 126:19] - wire [2:0] lsu_io_axi_ar_bits_size; // @[quasar.scala 126:19] - wire [3:0] lsu_io_axi_ar_bits_cache; // @[quasar.scala 126:19] - wire lsu_io_axi_r_valid; // @[quasar.scala 126:19] - wire [2:0] lsu_io_axi_r_bits_id; // @[quasar.scala 126:19] - wire [63:0] lsu_io_axi_r_bits_data; // @[quasar.scala 126:19] - wire [1:0] lsu_io_axi_r_bits_resp; // @[quasar.scala 126:19] - wire lsu_io_dec_tlu_flush_lower_r; // @[quasar.scala 126:19] - wire lsu_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 126:19] - wire lsu_io_dec_tlu_force_halt; // @[quasar.scala 126:19] - wire lsu_io_dec_tlu_core_ecc_disable; // @[quasar.scala 126:19] - wire [11:0] lsu_io_dec_lsu_offset_d; // @[quasar.scala 126:19] - wire lsu_io_lsu_p_valid; // @[quasar.scala 126:19] - wire lsu_io_lsu_p_bits_fast_int; // @[quasar.scala 126:19] - wire lsu_io_lsu_p_bits_by; // @[quasar.scala 126:19] - wire lsu_io_lsu_p_bits_half; // @[quasar.scala 126:19] - wire lsu_io_lsu_p_bits_word; // @[quasar.scala 126:19] - wire lsu_io_lsu_p_bits_load; // @[quasar.scala 126:19] - wire lsu_io_lsu_p_bits_store; // @[quasar.scala 126:19] - wire lsu_io_lsu_p_bits_unsign; // @[quasar.scala 126:19] - wire lsu_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 126:19] - wire lsu_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 126:19] - wire lsu_io_trigger_pkt_any_0_select; // @[quasar.scala 126:19] - wire lsu_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 126:19] - wire lsu_io_trigger_pkt_any_0_store; // @[quasar.scala 126:19] - wire lsu_io_trigger_pkt_any_0_load; // @[quasar.scala 126:19] - wire [31:0] lsu_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 126:19] - wire lsu_io_trigger_pkt_any_1_select; // @[quasar.scala 126:19] - wire lsu_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 126:19] - wire lsu_io_trigger_pkt_any_1_store; // @[quasar.scala 126:19] - wire lsu_io_trigger_pkt_any_1_load; // @[quasar.scala 126:19] - wire [31:0] lsu_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 126:19] - wire lsu_io_trigger_pkt_any_2_select; // @[quasar.scala 126:19] - wire lsu_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 126:19] - wire lsu_io_trigger_pkt_any_2_store; // @[quasar.scala 126:19] - wire lsu_io_trigger_pkt_any_2_load; // @[quasar.scala 126:19] - wire [31:0] lsu_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 126:19] - wire lsu_io_trigger_pkt_any_3_select; // @[quasar.scala 126:19] - wire lsu_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 126:19] - wire lsu_io_trigger_pkt_any_3_store; // @[quasar.scala 126:19] - wire lsu_io_trigger_pkt_any_3_load; // @[quasar.scala 126:19] - wire [31:0] lsu_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 126:19] - wire lsu_io_dec_lsu_valid_raw_d; // @[quasar.scala 126:19] - wire [31:0] lsu_io_dec_tlu_mrac_ff; // @[quasar.scala 126:19] - wire [31:0] lsu_io_lsu_result_m; // @[quasar.scala 126:19] - wire [31:0] lsu_io_lsu_result_corr_r; // @[quasar.scala 126:19] - wire lsu_io_lsu_load_stall_any; // @[quasar.scala 126:19] - wire lsu_io_lsu_store_stall_any; // @[quasar.scala 126:19] - wire lsu_io_lsu_fastint_stall_any; // @[quasar.scala 126:19] - wire lsu_io_lsu_idle_any; // @[quasar.scala 126:19] - wire [30:0] lsu_io_lsu_fir_addr; // @[quasar.scala 126:19] - wire [1:0] lsu_io_lsu_fir_error; // @[quasar.scala 126:19] - wire lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 126:19] - wire lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 126:19] - wire lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 126:19] - wire lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 126:19] - wire lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 126:19] - wire [3:0] lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 126:19] - wire [31:0] lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 126:19] - wire lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 126:19] - wire [3:0] lsu_io_lsu_trigger_match_m; // @[quasar.scala 126:19] - wire lsu_io_lsu_bus_clk_en; // @[quasar.scala 126:19] - wire lsu_io_scan_mode; // @[quasar.scala 126:19] - wire lsu_io_free_clk; // @[quasar.scala 126:19] - wire pic_ctrl_inst_clock; // @[quasar.scala 127:29] - wire pic_ctrl_inst_reset; // @[quasar.scala 127:29] - wire pic_ctrl_inst_io_scan_mode; // @[quasar.scala 127:29] - wire pic_ctrl_inst_io_free_clk; // @[quasar.scala 127:29] - wire pic_ctrl_inst_io_active_clk; // @[quasar.scala 127:29] - wire pic_ctrl_inst_io_clk_override; // @[quasar.scala 127:29] - wire [31:0] pic_ctrl_inst_io_extintsrc_req; // @[quasar.scala 127:29] - wire pic_ctrl_inst_io_lsu_pic_picm_wren; // @[quasar.scala 127:29] - wire pic_ctrl_inst_io_lsu_pic_picm_rden; // @[quasar.scala 127:29] - wire pic_ctrl_inst_io_lsu_pic_picm_mken; // @[quasar.scala 127:29] - wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rdaddr; // @[quasar.scala 127:29] - wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wraddr; // @[quasar.scala 127:29] - wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wr_data; // @[quasar.scala 127:29] - wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 127:29] - wire [3:0] pic_ctrl_inst_io_meicurpl; // @[quasar.scala 127:29] - wire [3:0] pic_ctrl_inst_io_meipt; // @[quasar.scala 127:29] - wire pic_ctrl_inst_io_mexintpend; // @[quasar.scala 127:29] - wire [7:0] pic_ctrl_inst_io_claimid; // @[quasar.scala 127:29] - wire [3:0] pic_ctrl_inst_io_pl; // @[quasar.scala 127:29] - wire pic_ctrl_inst_io_mhwakeup; // @[quasar.scala 127:29] - wire dma_ctrl_clock; // @[quasar.scala 128:24] - wire dma_ctrl_reset; // @[quasar.scala 128:24] - wire dma_ctrl_io_free_clk; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_bus_clk_en; // @[quasar.scala 128:24] - wire dma_ctrl_io_clk_override; // @[quasar.scala 128:24] - wire dma_ctrl_io_scan_mode; // @[quasar.scala 128:24] - wire [1:0] dma_ctrl_io_dbg_cmd_size; // @[quasar.scala 128:24] - wire [31:0] dma_ctrl_io_dma_dbg_rddata; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_dbg_cmd_done; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_dbg_cmd_fail; // @[quasar.scala 128:24] - wire dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 128:24] - wire dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 128:24] - wire [1:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 128:24] - wire [31:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 128:24] - wire [1:0] dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 128:24] - wire dma_ctrl_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 128:24] - wire dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 128:24] - wire dma_ctrl_io_iccm_dma_rvalid; // @[quasar.scala 128:24] - wire dma_ctrl_io_iccm_dma_ecc_error; // @[quasar.scala 128:24] - wire [2:0] dma_ctrl_io_iccm_dma_rtag; // @[quasar.scala 128:24] - wire [63:0] dma_ctrl_io_iccm_dma_rdata; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_dccm_stall_any; // @[quasar.scala 128:24] - wire dma_ctrl_io_iccm_ready; // @[quasar.scala 128:24] - wire [2:0] dma_ctrl_io_dec_tlu_dma_qos_prty; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_pmu_dccm_read; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_pmu_dccm_write; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_pmu_any_read; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_pmu_any_write; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_axi_aw_valid; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_axi_aw_bits_id; // @[quasar.scala 128:24] - wire [31:0] dma_ctrl_io_dma_axi_aw_bits_addr; // @[quasar.scala 128:24] - wire [2:0] dma_ctrl_io_dma_axi_aw_bits_size; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_axi_w_valid; // @[quasar.scala 128:24] - wire [63:0] dma_ctrl_io_dma_axi_w_bits_data; // @[quasar.scala 128:24] - wire [7:0] dma_ctrl_io_dma_axi_w_bits_strb; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_axi_b_ready; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 128:24] - wire [1:0] dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_axi_ar_valid; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_axi_ar_bits_id; // @[quasar.scala 128:24] - wire [31:0] dma_ctrl_io_dma_axi_ar_bits_addr; // @[quasar.scala 128:24] - wire [2:0] dma_ctrl_io_dma_axi_ar_bits_size; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_axi_r_ready; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 128:24] - wire dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 128:24] - wire [63:0] dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 128:24] - wire [1:0] dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 128:24] - wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 128:24] - wire [31:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 128:24] - wire [2:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 128:24] - wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 128:24] - wire [63:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 128:24] - wire [31:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 128:24] - wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 128:24] - wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 128:24] - wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 128:24] - wire [2:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 128:24] - wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 128:24] - wire dma_ctrl_io_lsu_dma_dccm_ready; // @[quasar.scala 128:24] - wire [2:0] dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 128:24] - wire dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 128:24] - wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 128:24] - wire [31:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 128:24] - wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 128:24] - wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 128:24] - wire [63:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 128:24] - wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 128:24] + wire ifu_clock; // @[quasar.scala 116:19] + wire ifu_reset; // @[quasar.scala 116:19] + wire ifu_io_exu_flush_final; // @[quasar.scala 116:19] + wire [30:0] ifu_io_exu_flush_path_final; // @[quasar.scala 116:19] + wire ifu_io_free_clk; // @[quasar.scala 116:19] + wire ifu_io_active_clk; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 116:19] + wire [15:0] ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 116:19] + wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 116:19] + wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 116:19] + wire [7:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 116:19] + wire [4:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 116:19] + wire [31:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 116:19] + wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 116:19] + wire [11:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 116:19] + wire [1:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 116:19] + wire [30:0] ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 116:19] + wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 116:19] + wire [16:0] ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 116:19] + wire [70:0] ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 116:19] + wire [31:0] ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 116:19] + wire [1:0] ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 116:19] + wire ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 116:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r; // @[quasar.scala 116:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 116:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 116:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 116:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 116:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 116:19] + wire [1:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 116:19] + wire [11:0] ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 116:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 116:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 116:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 116:19] + wire ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 116:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_eghr; // @[quasar.scala 116:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_fghr; // @[quasar.scala 116:19] + wire [7:0] ifu_io_exu_ifu_exu_bp_exu_mp_index; // @[quasar.scala 116:19] + wire [4:0] ifu_io_exu_ifu_exu_bp_exu_mp_btag; // @[quasar.scala 116:19] + wire [14:0] ifu_io_iccm_rw_addr; // @[quasar.scala 116:19] + wire ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 116:19] + wire ifu_io_iccm_correction_state; // @[quasar.scala 116:19] + wire ifu_io_iccm_wren; // @[quasar.scala 116:19] + wire ifu_io_iccm_rden; // @[quasar.scala 116:19] + wire [2:0] ifu_io_iccm_wr_size; // @[quasar.scala 116:19] + wire [77:0] ifu_io_iccm_wr_data; // @[quasar.scala 116:19] + wire [63:0] ifu_io_iccm_rd_data; // @[quasar.scala 116:19] + wire [77:0] ifu_io_iccm_rd_data_ecc; // @[quasar.scala 116:19] + wire [30:0] ifu_io_ic_rw_addr; // @[quasar.scala 116:19] + wire [1:0] ifu_io_ic_tag_valid; // @[quasar.scala 116:19] + wire [1:0] ifu_io_ic_wr_en; // @[quasar.scala 116:19] + wire ifu_io_ic_rd_en; // @[quasar.scala 116:19] + wire [70:0] ifu_io_ic_wr_data_0; // @[quasar.scala 116:19] + wire [70:0] ifu_io_ic_wr_data_1; // @[quasar.scala 116:19] + wire [70:0] ifu_io_ic_debug_wr_data; // @[quasar.scala 116:19] + wire [9:0] ifu_io_ic_debug_addr; // @[quasar.scala 116:19] + wire [63:0] ifu_io_ic_rd_data; // @[quasar.scala 116:19] + wire [70:0] ifu_io_ic_debug_rd_data; // @[quasar.scala 116:19] + wire [25:0] ifu_io_ic_tag_debug_rd_data; // @[quasar.scala 116:19] + wire [1:0] ifu_io_ic_eccerr; // @[quasar.scala 116:19] + wire [1:0] ifu_io_ic_rd_hit; // @[quasar.scala 116:19] + wire ifu_io_ic_tag_perr; // @[quasar.scala 116:19] + wire ifu_io_ic_debug_rd_en; // @[quasar.scala 116:19] + wire ifu_io_ic_debug_wr_en; // @[quasar.scala 116:19] + wire ifu_io_ic_debug_tag_array; // @[quasar.scala 116:19] + wire [1:0] ifu_io_ic_debug_way; // @[quasar.scala 116:19] + wire [63:0] ifu_io_ic_premux_data; // @[quasar.scala 116:19] + wire ifu_io_ic_sel_premux_data; // @[quasar.scala 116:19] + wire ifu_io_ifu_ar_ready; // @[quasar.scala 116:19] + wire ifu_io_ifu_ar_valid; // @[quasar.scala 116:19] + wire [2:0] ifu_io_ifu_ar_bits_id; // @[quasar.scala 116:19] + wire [31:0] ifu_io_ifu_ar_bits_addr; // @[quasar.scala 116:19] + wire [3:0] ifu_io_ifu_ar_bits_region; // @[quasar.scala 116:19] + wire ifu_io_ifu_r_valid; // @[quasar.scala 116:19] + wire [2:0] ifu_io_ifu_r_bits_id; // @[quasar.scala 116:19] + wire [63:0] ifu_io_ifu_r_bits_data; // @[quasar.scala 116:19] + wire [1:0] ifu_io_ifu_r_bits_resp; // @[quasar.scala 116:19] + wire ifu_io_ifu_bus_clk_en; // @[quasar.scala 116:19] + wire ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 116:19] + wire ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 116:19] + wire [31:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 116:19] + wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 116:19] + wire ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 116:19] + wire [63:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 116:19] + wire [2:0] ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 116:19] + wire ifu_io_iccm_dma_ecc_error; // @[quasar.scala 116:19] + wire ifu_io_iccm_dma_rvalid; // @[quasar.scala 116:19] + wire [63:0] ifu_io_iccm_dma_rdata; // @[quasar.scala 116:19] + wire [2:0] ifu_io_iccm_dma_rtag; // @[quasar.scala 116:19] + wire ifu_io_iccm_ready; // @[quasar.scala 116:19] + wire ifu_io_iccm_dma_sb_error; // @[quasar.scala 116:19] + wire ifu_io_dec_tlu_flush_lower_wb; // @[quasar.scala 116:19] + wire ifu_io_scan_mode; // @[quasar.scala 116:19] + wire dec_clock; // @[quasar.scala 117:19] + wire dec_reset; // @[quasar.scala 117:19] + wire dec_io_free_clk; // @[quasar.scala 117:19] + wire dec_io_active_clk; // @[quasar.scala 117:19] + wire dec_io_lsu_fastint_stall_any; // @[quasar.scala 117:19] + wire dec_io_dec_pause_state_cg; // @[quasar.scala 117:19] + wire [30:0] dec_io_rst_vec; // @[quasar.scala 117:19] + wire dec_io_nmi_int; // @[quasar.scala 117:19] + wire [30:0] dec_io_nmi_vec; // @[quasar.scala 117:19] + wire dec_io_i_cpu_halt_req; // @[quasar.scala 117:19] + wire dec_io_i_cpu_run_req; // @[quasar.scala 117:19] + wire dec_io_o_cpu_halt_status; // @[quasar.scala 117:19] + wire dec_io_o_cpu_halt_ack; // @[quasar.scala 117:19] + wire dec_io_o_cpu_run_ack; // @[quasar.scala 117:19] + wire dec_io_o_debug_mode_status; // @[quasar.scala 117:19] + wire [27:0] dec_io_core_id; // @[quasar.scala 117:19] + wire dec_io_mpc_debug_halt_req; // @[quasar.scala 117:19] + wire dec_io_mpc_debug_run_req; // @[quasar.scala 117:19] + wire dec_io_mpc_reset_run_req; // @[quasar.scala 117:19] + wire dec_io_mpc_debug_halt_ack; // @[quasar.scala 117:19] + wire dec_io_mpc_debug_run_ack; // @[quasar.scala 117:19] + wire dec_io_debug_brkpt_status; // @[quasar.scala 117:19] + wire dec_io_lsu_pmu_misaligned_m; // @[quasar.scala 117:19] + wire [30:0] dec_io_lsu_fir_addr; // @[quasar.scala 117:19] + wire [1:0] dec_io_lsu_fir_error; // @[quasar.scala 117:19] + wire [3:0] dec_io_lsu_trigger_match_m; // @[quasar.scala 117:19] + wire dec_io_lsu_idle_any; // @[quasar.scala 117:19] + wire dec_io_lsu_error_pkt_r_valid; // @[quasar.scala 117:19] + wire dec_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 117:19] + wire dec_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 117:19] + wire dec_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 117:19] + wire [3:0] dec_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 117:19] + wire [31:0] dec_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 117:19] + wire dec_io_lsu_single_ecc_error_incr; // @[quasar.scala 117:19] + wire [31:0] dec_io_exu_div_result; // @[quasar.scala 117:19] + wire dec_io_exu_div_wren; // @[quasar.scala 117:19] + wire [31:0] dec_io_lsu_result_m; // @[quasar.scala 117:19] + wire [31:0] dec_io_lsu_result_corr_r; // @[quasar.scala 117:19] + wire dec_io_lsu_load_stall_any; // @[quasar.scala 117:19] + wire dec_io_lsu_store_stall_any; // @[quasar.scala 117:19] + wire dec_io_iccm_dma_sb_error; // @[quasar.scala 117:19] + wire dec_io_exu_flush_final; // @[quasar.scala 117:19] + wire dec_io_timer_int; // @[quasar.scala 117:19] + wire dec_io_soft_int; // @[quasar.scala 117:19] + wire dec_io_dbg_halt_req; // @[quasar.scala 117:19] + wire dec_io_dbg_resume_req; // @[quasar.scala 117:19] + wire dec_io_dec_tlu_dbg_halted; // @[quasar.scala 117:19] + wire dec_io_dec_tlu_debug_mode; // @[quasar.scala 117:19] + wire dec_io_dec_tlu_resume_ack; // @[quasar.scala 117:19] + wire dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 117:19] + wire [31:0] dec_io_dec_dbg_rddata; // @[quasar.scala 117:19] + wire dec_io_dec_dbg_cmd_done; // @[quasar.scala 117:19] + wire dec_io_dec_dbg_cmd_fail; // @[quasar.scala 117:19] + wire dec_io_trigger_pkt_any_0_select; // @[quasar.scala 117:19] + wire dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 117:19] + wire dec_io_trigger_pkt_any_0_store; // @[quasar.scala 117:19] + wire dec_io_trigger_pkt_any_0_load; // @[quasar.scala 117:19] + wire [31:0] dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 117:19] + wire dec_io_trigger_pkt_any_1_select; // @[quasar.scala 117:19] + wire dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 117:19] + wire dec_io_trigger_pkt_any_1_store; // @[quasar.scala 117:19] + wire dec_io_trigger_pkt_any_1_load; // @[quasar.scala 117:19] + wire [31:0] dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 117:19] + wire dec_io_trigger_pkt_any_2_select; // @[quasar.scala 117:19] + wire dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 117:19] + wire dec_io_trigger_pkt_any_2_store; // @[quasar.scala 117:19] + wire dec_io_trigger_pkt_any_2_load; // @[quasar.scala 117:19] + wire [31:0] dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 117:19] + wire dec_io_trigger_pkt_any_3_select; // @[quasar.scala 117:19] + wire dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 117:19] + wire dec_io_trigger_pkt_any_3_store; // @[quasar.scala 117:19] + wire dec_io_trigger_pkt_any_3_load; // @[quasar.scala 117:19] + wire [31:0] dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 117:19] + wire dec_io_exu_i0_br_way_r; // @[quasar.scala 117:19] + wire dec_io_lsu_p_valid; // @[quasar.scala 117:19] + wire dec_io_lsu_p_bits_fast_int; // @[quasar.scala 117:19] + wire dec_io_lsu_p_bits_by; // @[quasar.scala 117:19] + wire dec_io_lsu_p_bits_half; // @[quasar.scala 117:19] + wire dec_io_lsu_p_bits_word; // @[quasar.scala 117:19] + wire dec_io_lsu_p_bits_load; // @[quasar.scala 117:19] + wire dec_io_lsu_p_bits_store; // @[quasar.scala 117:19] + wire dec_io_lsu_p_bits_unsign; // @[quasar.scala 117:19] + wire dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 117:19] + wire dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 117:19] + wire [11:0] dec_io_dec_lsu_offset_d; // @[quasar.scala 117:19] + wire dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 117:19] + wire dec_io_dec_tlu_perfcnt0; // @[quasar.scala 117:19] + wire dec_io_dec_tlu_perfcnt1; // @[quasar.scala 117:19] + wire dec_io_dec_tlu_perfcnt2; // @[quasar.scala 117:19] + wire dec_io_dec_tlu_perfcnt3; // @[quasar.scala 117:19] + wire dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 117:19] + wire [1:0] dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 117:19] + wire [31:0] dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 117:19] + wire [31:0] dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 117:19] + wire [1:0] dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 117:19] + wire [4:0] dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 117:19] + wire [1:0] dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 117:19] + wire [31:0] dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 117:19] + wire dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 117:19] + wire dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 117:19] + wire dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 117:19] + wire dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 117:19] + wire dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 117:19] + wire dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 117:19] + wire dec_io_scan_mode; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 117:19] + wire [15:0] dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 117:19] + wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 117:19] + wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 117:19] + wire [7:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 117:19] + wire [4:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 117:19] + wire [31:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 117:19] + wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 117:19] + wire [11:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 117:19] + wire [1:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 117:19] + wire [30:0] dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 117:19] + wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 117:19] + wire [16:0] dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 117:19] + wire [70:0] dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 117:19] + wire [31:0] dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 117:19] + wire [1:0] dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 117:19] + wire dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 117:19] + wire dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 117:19] + wire dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 117:19] + wire [11:0] dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 117:19] + wire [30:0] dec_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 117:19] + wire dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 117:19] + wire dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 117:19] + wire dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 117:19] + wire dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 117:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 117:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 117:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 117:19] + wire [11:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 117:19] + wire [30:0] dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 117:19] + wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 117:19] + wire [7:0] dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 117:19] + wire [4:0] dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 117:19] + wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 117:19] + wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 117:19] + wire [31:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 117:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 117:19] + wire [1:0] dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 117:19] + wire [30:0] dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 117:19] + wire dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 117:19] + wire [31:0] dec_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 117:19] + wire [31:0] dec_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 117:19] + wire [29:0] dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 117:19] + wire dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 117:19] + wire [30:0] dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 117:19] + wire [1:0] dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 117:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 117:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 117:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 117:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 117:19] + wire dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 117:19] + wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 117:19] + wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 117:19] + wire dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 117:19] + wire [30:0] dec_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 117:19] + wire [30:0] dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 117:19] + wire dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 117:19] + wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 117:19] + wire [31:0] dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 117:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 117:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 117:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 117:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 117:19] + wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 117:19] + wire dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 117:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 117:19] + wire dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 117:19] + wire [31:0] dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 117:19] + wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 117:19] + wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 117:19] + wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 117:19] + wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 117:19] + wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 117:19] + wire dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 117:19] + wire [1:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 117:19] + wire [31:0] dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 117:19] + wire dec_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 117:19] + wire dec_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 117:19] + wire dec_io_dec_dbg_dbg_ib_dbg_cmd_valid; // @[quasar.scala 117:19] + wire dec_io_dec_dbg_dbg_ib_dbg_cmd_write; // @[quasar.scala 117:19] + wire [1:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_type; // @[quasar.scala 117:19] + wire [31:0] dec_io_dec_dbg_dbg_ib_dbg_cmd_addr; // @[quasar.scala 117:19] + wire [1:0] dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 117:19] + wire dec_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 117:19] + wire dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 117:19] + wire dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 117:19] + wire dec_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 117:19] + wire dec_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 117:19] + wire [2:0] dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 117:19] + wire dec_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 117:19] + wire dec_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 117:19] + wire [7:0] dec_io_dec_pic_pic_claimid; // @[quasar.scala 117:19] + wire [3:0] dec_io_dec_pic_pic_pl; // @[quasar.scala 117:19] + wire dec_io_dec_pic_mhwakeup; // @[quasar.scala 117:19] + wire [3:0] dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 117:19] + wire [3:0] dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 117:19] + wire dec_io_dec_pic_mexintpend; // @[quasar.scala 117:19] + wire dbg_clock; // @[quasar.scala 118:19] + wire dbg_reset; // @[quasar.scala 118:19] + wire [1:0] dbg_io_dbg_cmd_size; // @[quasar.scala 118:19] + wire dbg_io_dbg_core_rst_l; // @[quasar.scala 118:19] + wire [31:0] dbg_io_core_dbg_rddata; // @[quasar.scala 118:19] + wire dbg_io_core_dbg_cmd_done; // @[quasar.scala 118:19] + wire dbg_io_core_dbg_cmd_fail; // @[quasar.scala 118:19] + wire dbg_io_dbg_halt_req; // @[quasar.scala 118:19] + wire dbg_io_dbg_resume_req; // @[quasar.scala 118:19] + wire dbg_io_dec_tlu_debug_mode; // @[quasar.scala 118:19] + wire dbg_io_dec_tlu_dbg_halted; // @[quasar.scala 118:19] + wire dbg_io_dec_tlu_mpc_halted_only; // @[quasar.scala 118:19] + wire dbg_io_dec_tlu_resume_ack; // @[quasar.scala 118:19] + wire dbg_io_dmi_reg_en; // @[quasar.scala 118:19] + wire [6:0] dbg_io_dmi_reg_addr; // @[quasar.scala 118:19] + wire dbg_io_dmi_reg_wr_en; // @[quasar.scala 118:19] + wire [31:0] dbg_io_dmi_reg_wdata; // @[quasar.scala 118:19] + wire dbg_io_sb_axi_aw_ready; // @[quasar.scala 118:19] + wire dbg_io_sb_axi_aw_valid; // @[quasar.scala 118:19] + wire [31:0] dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 118:19] + wire [3:0] dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 118:19] + wire [2:0] dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 118:19] + wire dbg_io_sb_axi_w_ready; // @[quasar.scala 118:19] + wire dbg_io_sb_axi_w_valid; // @[quasar.scala 118:19] + wire [63:0] dbg_io_sb_axi_w_bits_data; // @[quasar.scala 118:19] + wire [7:0] dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 118:19] + wire dbg_io_sb_axi_b_ready; // @[quasar.scala 118:19] + wire dbg_io_sb_axi_b_valid; // @[quasar.scala 118:19] + wire [1:0] dbg_io_sb_axi_b_bits_resp; // @[quasar.scala 118:19] + wire dbg_io_sb_axi_ar_ready; // @[quasar.scala 118:19] + wire dbg_io_sb_axi_ar_valid; // @[quasar.scala 118:19] + wire [31:0] dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 118:19] + wire [3:0] dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 118:19] + wire [2:0] dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 118:19] + wire dbg_io_sb_axi_r_ready; // @[quasar.scala 118:19] + wire dbg_io_sb_axi_r_valid; // @[quasar.scala 118:19] + wire [63:0] dbg_io_sb_axi_r_bits_data; // @[quasar.scala 118:19] + wire [1:0] dbg_io_sb_axi_r_bits_resp; // @[quasar.scala 118:19] + wire dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 118:19] + wire dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 118:19] + wire [1:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 118:19] + wire [31:0] dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 118:19] + wire [1:0] dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 118:19] + wire dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 118:19] + wire dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 118:19] + wire [1:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 118:19] + wire [31:0] dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 118:19] + wire [1:0] dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 118:19] + wire dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 118:19] + wire dbg_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 118:19] + wire dbg_io_dbg_bus_clk_en; // @[quasar.scala 118:19] + wire dbg_io_dbg_rst_l; // @[quasar.scala 118:19] + wire dbg_io_clk_override; // @[quasar.scala 118:19] + wire dbg_io_scan_mode; // @[quasar.scala 118:19] + wire exu_clock; // @[quasar.scala 119:19] + wire exu_reset; // @[quasar.scala 119:19] + wire exu_io_scan_mode; // @[quasar.scala 119:19] + wire exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 119:19] + wire exu_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 119:19] + wire [11:0] exu_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 119:19] + wire [30:0] exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 119:19] + wire exu_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 119:19] + wire exu_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 119:19] + wire exu_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 119:19] + wire exu_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 119:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 119:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 119:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 119:19] + wire [11:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 119:19] + wire [30:0] exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 119:19] + wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 119:19] + wire [7:0] exu_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 119:19] + wire [4:0] exu_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 119:19] + wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 119:19] + wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 119:19] + wire [31:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 119:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 119:19] + wire [1:0] exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 119:19] + wire [30:0] exu_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 119:19] + wire exu_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 119:19] + wire [31:0] exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 119:19] + wire [31:0] exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 119:19] + wire [29:0] exu_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 119:19] + wire exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 119:19] + wire [30:0] exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 119:19] + wire [1:0] exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 119:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 119:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 119:19] + wire [7:0] exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 119:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 119:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 119:19] + wire exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 119:19] + wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 119:19] + wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 119:19] + wire exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 119:19] + wire [30:0] exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 119:19] + wire [30:0] exu_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 119:19] + wire exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 119:19] + wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 119:19] + wire [31:0] exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 119:19] + wire [7:0] exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 119:19] + wire exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 119:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 119:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 119:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 119:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 119:19] + wire [1:0] exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 119:19] + wire [11:0] exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 119:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 119:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 119:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 119:19] + wire exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 119:19] + wire [7:0] exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 119:19] + wire [7:0] exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 119:19] + wire [7:0] exu_io_exu_bp_exu_mp_index; // @[quasar.scala 119:19] + wire [4:0] exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 119:19] + wire exu_io_exu_flush_final; // @[quasar.scala 119:19] + wire [31:0] exu_io_exu_div_result; // @[quasar.scala 119:19] + wire exu_io_exu_div_wren; // @[quasar.scala 119:19] + wire [31:0] exu_io_dbg_cmd_wrdata; // @[quasar.scala 119:19] + wire [31:0] exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 119:19] + wire [31:0] exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 119:19] + wire [30:0] exu_io_exu_flush_path_final; // @[quasar.scala 119:19] + wire lsu_clock; // @[quasar.scala 120:19] + wire lsu_reset; // @[quasar.scala 120:19] + wire lsu_io_clk_override; // @[quasar.scala 120:19] + wire lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 120:19] + wire [31:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 120:19] + wire [2:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 120:19] + wire lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 120:19] + wire [63:0] lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 120:19] + wire [31:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 120:19] + wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 120:19] + wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 120:19] + wire lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 120:19] + wire [2:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 120:19] + wire [63:0] lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 120:19] + wire lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 120:19] + wire [2:0] lsu_io_lsu_dma_dma_mem_tag; // @[quasar.scala 120:19] + wire lsu_io_lsu_pic_picm_wren; // @[quasar.scala 120:19] + wire lsu_io_lsu_pic_picm_rden; // @[quasar.scala 120:19] + wire lsu_io_lsu_pic_picm_mken; // @[quasar.scala 120:19] + wire [31:0] lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 120:19] + wire [31:0] lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 120:19] + wire [31:0] lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 120:19] + wire [31:0] lsu_io_lsu_pic_picm_rd_data; // @[quasar.scala 120:19] + wire [31:0] lsu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 120:19] + wire [31:0] lsu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 120:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 120:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 120:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 120:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 120:19] + wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 120:19] + wire lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 120:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 120:19] + wire lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 120:19] + wire [31:0] lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 120:19] + wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 120:19] + wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 120:19] + wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 120:19] + wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 120:19] + wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 120:19] + wire lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 120:19] + wire [1:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 120:19] + wire [31:0] lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 120:19] + wire lsu_io_dccm_wren; // @[quasar.scala 120:19] + wire lsu_io_dccm_rden; // @[quasar.scala 120:19] + wire [15:0] lsu_io_dccm_wr_addr_lo; // @[quasar.scala 120:19] + wire [15:0] lsu_io_dccm_wr_addr_hi; // @[quasar.scala 120:19] + wire [15:0] lsu_io_dccm_rd_addr_lo; // @[quasar.scala 120:19] + wire [15:0] lsu_io_dccm_rd_addr_hi; // @[quasar.scala 120:19] + wire [38:0] lsu_io_dccm_wr_data_lo; // @[quasar.scala 120:19] + wire [38:0] lsu_io_dccm_wr_data_hi; // @[quasar.scala 120:19] + wire [38:0] lsu_io_dccm_rd_data_lo; // @[quasar.scala 120:19] + wire [38:0] lsu_io_dccm_rd_data_hi; // @[quasar.scala 120:19] + wire lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 120:19] + wire lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 120:19] + wire lsu_io_axi_aw_ready; // @[quasar.scala 120:19] + wire lsu_io_axi_aw_valid; // @[quasar.scala 120:19] + wire [2:0] lsu_io_axi_aw_bits_id; // @[quasar.scala 120:19] + wire [31:0] lsu_io_axi_aw_bits_addr; // @[quasar.scala 120:19] + wire [3:0] lsu_io_axi_aw_bits_region; // @[quasar.scala 120:19] + wire [2:0] lsu_io_axi_aw_bits_size; // @[quasar.scala 120:19] + wire [3:0] lsu_io_axi_aw_bits_cache; // @[quasar.scala 120:19] + wire lsu_io_axi_w_ready; // @[quasar.scala 120:19] + wire lsu_io_axi_w_valid; // @[quasar.scala 120:19] + wire [63:0] lsu_io_axi_w_bits_data; // @[quasar.scala 120:19] + wire [7:0] lsu_io_axi_w_bits_strb; // @[quasar.scala 120:19] + wire lsu_io_axi_b_valid; // @[quasar.scala 120:19] + wire [1:0] lsu_io_axi_b_bits_resp; // @[quasar.scala 120:19] + wire [2:0] lsu_io_axi_b_bits_id; // @[quasar.scala 120:19] + wire lsu_io_axi_ar_ready; // @[quasar.scala 120:19] + wire lsu_io_axi_ar_valid; // @[quasar.scala 120:19] + wire [2:0] lsu_io_axi_ar_bits_id; // @[quasar.scala 120:19] + wire [31:0] lsu_io_axi_ar_bits_addr; // @[quasar.scala 120:19] + wire [3:0] lsu_io_axi_ar_bits_region; // @[quasar.scala 120:19] + wire [2:0] lsu_io_axi_ar_bits_size; // @[quasar.scala 120:19] + wire [3:0] lsu_io_axi_ar_bits_cache; // @[quasar.scala 120:19] + wire lsu_io_axi_r_valid; // @[quasar.scala 120:19] + wire [2:0] lsu_io_axi_r_bits_id; // @[quasar.scala 120:19] + wire [63:0] lsu_io_axi_r_bits_data; // @[quasar.scala 120:19] + wire [1:0] lsu_io_axi_r_bits_resp; // @[quasar.scala 120:19] + wire lsu_io_dec_tlu_flush_lower_r; // @[quasar.scala 120:19] + wire lsu_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 120:19] + wire lsu_io_dec_tlu_force_halt; // @[quasar.scala 120:19] + wire lsu_io_dec_tlu_core_ecc_disable; // @[quasar.scala 120:19] + wire [11:0] lsu_io_dec_lsu_offset_d; // @[quasar.scala 120:19] + wire lsu_io_lsu_p_valid; // @[quasar.scala 120:19] + wire lsu_io_lsu_p_bits_fast_int; // @[quasar.scala 120:19] + wire lsu_io_lsu_p_bits_by; // @[quasar.scala 120:19] + wire lsu_io_lsu_p_bits_half; // @[quasar.scala 120:19] + wire lsu_io_lsu_p_bits_word; // @[quasar.scala 120:19] + wire lsu_io_lsu_p_bits_load; // @[quasar.scala 120:19] + wire lsu_io_lsu_p_bits_store; // @[quasar.scala 120:19] + wire lsu_io_lsu_p_bits_unsign; // @[quasar.scala 120:19] + wire lsu_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 120:19] + wire lsu_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 120:19] + wire lsu_io_trigger_pkt_any_0_select; // @[quasar.scala 120:19] + wire lsu_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 120:19] + wire lsu_io_trigger_pkt_any_0_store; // @[quasar.scala 120:19] + wire lsu_io_trigger_pkt_any_0_load; // @[quasar.scala 120:19] + wire [31:0] lsu_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 120:19] + wire lsu_io_trigger_pkt_any_1_select; // @[quasar.scala 120:19] + wire lsu_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 120:19] + wire lsu_io_trigger_pkt_any_1_store; // @[quasar.scala 120:19] + wire lsu_io_trigger_pkt_any_1_load; // @[quasar.scala 120:19] + wire [31:0] lsu_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 120:19] + wire lsu_io_trigger_pkt_any_2_select; // @[quasar.scala 120:19] + wire lsu_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 120:19] + wire lsu_io_trigger_pkt_any_2_store; // @[quasar.scala 120:19] + wire lsu_io_trigger_pkt_any_2_load; // @[quasar.scala 120:19] + wire [31:0] lsu_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 120:19] + wire lsu_io_trigger_pkt_any_3_select; // @[quasar.scala 120:19] + wire lsu_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 120:19] + wire lsu_io_trigger_pkt_any_3_store; // @[quasar.scala 120:19] + wire lsu_io_trigger_pkt_any_3_load; // @[quasar.scala 120:19] + wire [31:0] lsu_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 120:19] + wire lsu_io_dec_lsu_valid_raw_d; // @[quasar.scala 120:19] + wire [31:0] lsu_io_dec_tlu_mrac_ff; // @[quasar.scala 120:19] + wire [31:0] lsu_io_lsu_result_m; // @[quasar.scala 120:19] + wire [31:0] lsu_io_lsu_result_corr_r; // @[quasar.scala 120:19] + wire lsu_io_lsu_load_stall_any; // @[quasar.scala 120:19] + wire lsu_io_lsu_store_stall_any; // @[quasar.scala 120:19] + wire lsu_io_lsu_fastint_stall_any; // @[quasar.scala 120:19] + wire lsu_io_lsu_idle_any; // @[quasar.scala 120:19] + wire [30:0] lsu_io_lsu_fir_addr; // @[quasar.scala 120:19] + wire [1:0] lsu_io_lsu_fir_error; // @[quasar.scala 120:19] + wire lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 120:19] + wire lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 120:19] + wire lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 120:19] + wire lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 120:19] + wire lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 120:19] + wire [3:0] lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 120:19] + wire [31:0] lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 120:19] + wire lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 120:19] + wire [3:0] lsu_io_lsu_trigger_match_m; // @[quasar.scala 120:19] + wire lsu_io_lsu_bus_clk_en; // @[quasar.scala 120:19] + wire lsu_io_scan_mode; // @[quasar.scala 120:19] + wire lsu_io_free_clk; // @[quasar.scala 120:19] + wire pic_ctrl_inst_clock; // @[quasar.scala 121:29] + wire pic_ctrl_inst_reset; // @[quasar.scala 121:29] + wire pic_ctrl_inst_io_scan_mode; // @[quasar.scala 121:29] + wire pic_ctrl_inst_io_free_clk; // @[quasar.scala 121:29] + wire pic_ctrl_inst_io_active_clk; // @[quasar.scala 121:29] + wire pic_ctrl_inst_io_clk_override; // @[quasar.scala 121:29] + wire [31:0] pic_ctrl_inst_io_extintsrc_req; // @[quasar.scala 121:29] + wire pic_ctrl_inst_io_lsu_pic_picm_wren; // @[quasar.scala 121:29] + wire pic_ctrl_inst_io_lsu_pic_picm_rden; // @[quasar.scala 121:29] + wire pic_ctrl_inst_io_lsu_pic_picm_mken; // @[quasar.scala 121:29] + wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rdaddr; // @[quasar.scala 121:29] + wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wraddr; // @[quasar.scala 121:29] + wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_wr_data; // @[quasar.scala 121:29] + wire [31:0] pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 121:29] + wire [7:0] pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 121:29] + wire [3:0] pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 121:29] + wire pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 121:29] + wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 121:29] + wire [3:0] pic_ctrl_inst_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 121:29] + wire pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 121:29] + wire dma_ctrl_clock; // @[quasar.scala 122:24] + wire dma_ctrl_reset; // @[quasar.scala 122:24] + wire dma_ctrl_io_free_clk; // @[quasar.scala 122:24] + wire dma_ctrl_io_dma_bus_clk_en; // @[quasar.scala 122:24] + wire dma_ctrl_io_clk_override; // @[quasar.scala 122:24] + wire dma_ctrl_io_scan_mode; // @[quasar.scala 122:24] + wire [1:0] dma_ctrl_io_dbg_cmd_size; // @[quasar.scala 122:24] + wire [31:0] dma_ctrl_io_dma_dbg_rddata; // @[quasar.scala 122:24] + wire dma_ctrl_io_dma_dbg_cmd_done; // @[quasar.scala 122:24] + wire dma_ctrl_io_dma_dbg_cmd_fail; // @[quasar.scala 122:24] + wire dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 122:24] + wire dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 122:24] + wire [1:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 122:24] + wire [31:0] dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 122:24] + wire [1:0] dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 122:24] + wire dma_ctrl_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 122:24] + wire dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 122:24] + wire dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 122:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 122:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 122:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 122:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 122:24] + wire [2:0] dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 122:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 122:24] + wire dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 122:24] + wire dma_ctrl_io_iccm_dma_rvalid; // @[quasar.scala 122:24] + wire dma_ctrl_io_iccm_dma_ecc_error; // @[quasar.scala 122:24] + wire [2:0] dma_ctrl_io_iccm_dma_rtag; // @[quasar.scala 122:24] + wire [63:0] dma_ctrl_io_iccm_dma_rdata; // @[quasar.scala 122:24] + wire dma_ctrl_io_iccm_ready; // @[quasar.scala 122:24] + wire dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 122:24] + wire dma_ctrl_io_dma_axi_aw_valid; // @[quasar.scala 122:24] + wire [31:0] dma_ctrl_io_dma_axi_aw_bits_addr; // @[quasar.scala 122:24] + wire [2:0] dma_ctrl_io_dma_axi_aw_bits_size; // @[quasar.scala 122:24] + wire dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 122:24] + wire dma_ctrl_io_dma_axi_w_valid; // @[quasar.scala 122:24] + wire [63:0] dma_ctrl_io_dma_axi_w_bits_data; // @[quasar.scala 122:24] + wire [7:0] dma_ctrl_io_dma_axi_w_bits_strb; // @[quasar.scala 122:24] + wire dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 122:24] + wire [1:0] dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 122:24] + wire dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 122:24] + wire dma_ctrl_io_dma_axi_ar_valid; // @[quasar.scala 122:24] + wire [31:0] dma_ctrl_io_dma_axi_ar_bits_addr; // @[quasar.scala 122:24] + wire [2:0] dma_ctrl_io_dma_axi_ar_bits_size; // @[quasar.scala 122:24] + wire dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 122:24] + wire [63:0] dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 122:24] + wire [1:0] dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 122:24] + wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 122:24] + wire [31:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 122:24] + wire [2:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 122:24] + wire dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 122:24] + wire [63:0] dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 122:24] + wire [31:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 122:24] + wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 122:24] + wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 122:24] + wire dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 122:24] + wire [2:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 122:24] + wire [63:0] dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 122:24] + wire dma_ctrl_io_lsu_dma_dccm_ready; // @[quasar.scala 122:24] + wire [2:0] dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 122:24] + wire dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 122:24] + wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 122:24] + wire [31:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 122:24] + wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 122:24] + wire dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 122:24] + wire [63:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 122:24] + wire [2:0] dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 122:24] wire rvclkhdr_io_l1clk; // @[lib.scala 327:22] wire rvclkhdr_io_clk; // @[lib.scala 327:22] wire rvclkhdr_io_en; // @[lib.scala 327:22] @@ -82067,65 +82026,108 @@ module quasar( wire rvclkhdr_1_io_clk; // @[lib.scala 327:22] wire rvclkhdr_1_io_en; // @[lib.scala 327:22] wire rvclkhdr_1_io_scan_mode; // @[lib.scala 327:22] - wire axi4_to_ahb_clock; // @[quasar.scala 318:33] - wire axi4_to_ahb_reset; // @[quasar.scala 318:33] - wire axi4_to_ahb_io_scan_mode; // @[quasar.scala 318:33] - wire axi4_to_ahb_io_bus_clk_en; // @[quasar.scala 318:33] - wire axi4_to_ahb_io_clk_override; // @[quasar.scala 318:33] - wire axi4_to_ahb_io_axi_awvalid; // @[quasar.scala 318:33] - wire axi4_to_ahb_io_axi_wvalid; // @[quasar.scala 318:33] - wire axi4_to_ahb_io_axi_bready; // @[quasar.scala 318:33] - wire axi4_to_ahb_io_axi_arvalid; // @[quasar.scala 318:33] - wire axi4_to_ahb_io_axi_rready; // @[quasar.scala 318:33] - wire axi4_to_ahb_io_axi_awready; // @[quasar.scala 318:33] - wire axi4_to_ahb_io_axi_wready; // @[quasar.scala 318:33] - wire axi4_to_ahb_1_clock; // @[quasar.scala 345:33] - wire axi4_to_ahb_1_reset; // @[quasar.scala 345:33] - wire axi4_to_ahb_1_io_scan_mode; // @[quasar.scala 345:33] - wire axi4_to_ahb_1_io_bus_clk_en; // @[quasar.scala 345:33] - wire axi4_to_ahb_1_io_clk_override; // @[quasar.scala 345:33] - wire axi4_to_ahb_1_io_axi_awvalid; // @[quasar.scala 345:33] - wire axi4_to_ahb_1_io_axi_wvalid; // @[quasar.scala 345:33] - wire axi4_to_ahb_1_io_axi_bready; // @[quasar.scala 345:33] - wire axi4_to_ahb_1_io_axi_arvalid; // @[quasar.scala 345:33] - wire axi4_to_ahb_1_io_axi_rready; // @[quasar.scala 345:33] - wire axi4_to_ahb_1_io_axi_awready; // @[quasar.scala 345:33] - wire axi4_to_ahb_1_io_axi_wready; // @[quasar.scala 345:33] - wire axi4_to_ahb_2_clock; // @[quasar.scala 373:32] - wire axi4_to_ahb_2_reset; // @[quasar.scala 373:32] - wire axi4_to_ahb_2_io_scan_mode; // @[quasar.scala 373:32] - wire axi4_to_ahb_2_io_bus_clk_en; // @[quasar.scala 373:32] - wire axi4_to_ahb_2_io_clk_override; // @[quasar.scala 373:32] - wire axi4_to_ahb_2_io_axi_awvalid; // @[quasar.scala 373:32] - wire axi4_to_ahb_2_io_axi_wvalid; // @[quasar.scala 373:32] - wire axi4_to_ahb_2_io_axi_bready; // @[quasar.scala 373:32] - wire axi4_to_ahb_2_io_axi_arvalid; // @[quasar.scala 373:32] - wire axi4_to_ahb_2_io_axi_rready; // @[quasar.scala 373:32] - wire axi4_to_ahb_2_io_axi_awready; // @[quasar.scala 373:32] - wire axi4_to_ahb_2_io_axi_wready; // @[quasar.scala 373:32] - wire ahb_to_axi4_clock; // @[quasar.scala 400:33] - wire ahb_to_axi4_reset; // @[quasar.scala 400:33] - wire ahb_to_axi4_io_scan_mode; // @[quasar.scala 400:33] - wire ahb_to_axi4_io_bus_clk_en; // @[quasar.scala 400:33] - wire ahb_to_axi4_io_axi_awready; // @[quasar.scala 400:33] - wire ahb_to_axi4_io_axi_arready; // @[quasar.scala 400:33] - wire ahb_to_axi4_io_axi_rvalid; // @[quasar.scala 400:33] - wire [1:0] ahb_to_axi4_io_axi_rresp; // @[quasar.scala 400:33] - wire [31:0] ahb_to_axi4_io_ahb_haddr; // @[quasar.scala 400:33] - wire [2:0] ahb_to_axi4_io_ahb_hsize; // @[quasar.scala 400:33] - wire [1:0] ahb_to_axi4_io_ahb_htrans; // @[quasar.scala 400:33] - wire ahb_to_axi4_io_ahb_hwrite; // @[quasar.scala 400:33] - wire ahb_to_axi4_io_ahb_hsel; // @[quasar.scala 400:33] - wire ahb_to_axi4_io_ahb_hreadyin; // @[quasar.scala 400:33] - wire ahb_to_axi4_io_axi_awvalid; // @[quasar.scala 400:33] - wire ahb_to_axi4_io_axi_arvalid; // @[quasar.scala 400:33] - wire ahb_to_axi4_io_ahb_hreadyout; // @[quasar.scala 400:33] - wire ahb_to_axi4_io_ahb_hresp; // @[quasar.scala 400:33] - wire _T_1 = dbg_io_dbg_core_rst_l; // @[quasar.scala 130:67] - wire _T_2 = _T_1 | io_scan_mode; // @[quasar.scala 130:70] - wire _T_5 = ~dec_io_dec_pause_state_cg; // @[quasar.scala 131:23] - wire _T_6 = _T_5 | dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 131:50] - ifu ifu ( // @[quasar.scala 122:19] + wire axi4_to_ahb_clock; // @[quasar.scala 297:33] + wire axi4_to_ahb_reset; // @[quasar.scala 297:33] + wire axi4_to_ahb_io_scan_mode; // @[quasar.scala 297:33] + wire axi4_to_ahb_io_bus_clk_en; // @[quasar.scala 297:33] + wire axi4_to_ahb_io_clk_override; // @[quasar.scala 297:33] + wire axi4_to_ahb_io_axi_awvalid; // @[quasar.scala 297:33] + wire axi4_to_ahb_io_axi_awid; // @[quasar.scala 297:33] + wire axi4_to_ahb_io_axi_wvalid; // @[quasar.scala 297:33] + wire [63:0] axi4_to_ahb_io_axi_wdata; // @[quasar.scala 297:33] + wire axi4_to_ahb_io_axi_bready; // @[quasar.scala 297:33] + wire axi4_to_ahb_io_axi_arvalid; // @[quasar.scala 297:33] + wire axi4_to_ahb_io_axi_arid; // @[quasar.scala 297:33] + wire axi4_to_ahb_io_axi_rready; // @[quasar.scala 297:33] + wire axi4_to_ahb_io_axi_awready; // @[quasar.scala 297:33] + wire axi4_to_ahb_io_axi_wready; // @[quasar.scala 297:33] + wire axi4_to_ahb_io_axi_bvalid; // @[quasar.scala 297:33] + wire [1:0] axi4_to_ahb_io_axi_bresp; // @[quasar.scala 297:33] + wire axi4_to_ahb_io_axi_bid; // @[quasar.scala 297:33] + wire axi4_to_ahb_io_axi_arready; // @[quasar.scala 297:33] + wire axi4_to_ahb_io_axi_rvalid; // @[quasar.scala 297:33] + wire axi4_to_ahb_io_axi_rid; // @[quasar.scala 297:33] + wire [63:0] axi4_to_ahb_io_axi_rdata; // @[quasar.scala 297:33] + wire [1:0] axi4_to_ahb_io_axi_rresp; // @[quasar.scala 297:33] + wire axi4_to_ahb_1_clock; // @[quasar.scala 324:33] + wire axi4_to_ahb_1_reset; // @[quasar.scala 324:33] + wire axi4_to_ahb_1_io_scan_mode; // @[quasar.scala 324:33] + wire axi4_to_ahb_1_io_bus_clk_en; // @[quasar.scala 324:33] + wire axi4_to_ahb_1_io_clk_override; // @[quasar.scala 324:33] + wire axi4_to_ahb_1_io_axi_awvalid; // @[quasar.scala 324:33] + wire axi4_to_ahb_1_io_axi_awid; // @[quasar.scala 324:33] + wire axi4_to_ahb_1_io_axi_wvalid; // @[quasar.scala 324:33] + wire [63:0] axi4_to_ahb_1_io_axi_wdata; // @[quasar.scala 324:33] + wire axi4_to_ahb_1_io_axi_bready; // @[quasar.scala 324:33] + wire axi4_to_ahb_1_io_axi_arvalid; // @[quasar.scala 324:33] + wire axi4_to_ahb_1_io_axi_arid; // @[quasar.scala 324:33] + wire axi4_to_ahb_1_io_axi_rready; // @[quasar.scala 324:33] + wire axi4_to_ahb_1_io_axi_awready; // @[quasar.scala 324:33] + wire axi4_to_ahb_1_io_axi_wready; // @[quasar.scala 324:33] + wire axi4_to_ahb_1_io_axi_bvalid; // @[quasar.scala 324:33] + wire [1:0] axi4_to_ahb_1_io_axi_bresp; // @[quasar.scala 324:33] + wire axi4_to_ahb_1_io_axi_bid; // @[quasar.scala 324:33] + wire axi4_to_ahb_1_io_axi_arready; // @[quasar.scala 324:33] + wire axi4_to_ahb_1_io_axi_rvalid; // @[quasar.scala 324:33] + wire axi4_to_ahb_1_io_axi_rid; // @[quasar.scala 324:33] + wire [63:0] axi4_to_ahb_1_io_axi_rdata; // @[quasar.scala 324:33] + wire [1:0] axi4_to_ahb_1_io_axi_rresp; // @[quasar.scala 324:33] + wire axi4_to_ahb_2_clock; // @[quasar.scala 352:32] + wire axi4_to_ahb_2_reset; // @[quasar.scala 352:32] + wire axi4_to_ahb_2_io_scan_mode; // @[quasar.scala 352:32] + wire axi4_to_ahb_2_io_bus_clk_en; // @[quasar.scala 352:32] + wire axi4_to_ahb_2_io_clk_override; // @[quasar.scala 352:32] + wire axi4_to_ahb_2_io_axi_awvalid; // @[quasar.scala 352:32] + wire axi4_to_ahb_2_io_axi_awid; // @[quasar.scala 352:32] + wire axi4_to_ahb_2_io_axi_wvalid; // @[quasar.scala 352:32] + wire [63:0] axi4_to_ahb_2_io_axi_wdata; // @[quasar.scala 352:32] + wire axi4_to_ahb_2_io_axi_bready; // @[quasar.scala 352:32] + wire axi4_to_ahb_2_io_axi_arvalid; // @[quasar.scala 352:32] + wire axi4_to_ahb_2_io_axi_arid; // @[quasar.scala 352:32] + wire axi4_to_ahb_2_io_axi_rready; // @[quasar.scala 352:32] + wire axi4_to_ahb_2_io_axi_awready; // @[quasar.scala 352:32] + wire axi4_to_ahb_2_io_axi_wready; // @[quasar.scala 352:32] + wire axi4_to_ahb_2_io_axi_bvalid; // @[quasar.scala 352:32] + wire [1:0] axi4_to_ahb_2_io_axi_bresp; // @[quasar.scala 352:32] + wire axi4_to_ahb_2_io_axi_bid; // @[quasar.scala 352:32] + wire axi4_to_ahb_2_io_axi_arready; // @[quasar.scala 352:32] + wire axi4_to_ahb_2_io_axi_rvalid; // @[quasar.scala 352:32] + wire axi4_to_ahb_2_io_axi_rid; // @[quasar.scala 352:32] + wire [63:0] axi4_to_ahb_2_io_axi_rdata; // @[quasar.scala 352:32] + wire [1:0] axi4_to_ahb_2_io_axi_rresp; // @[quasar.scala 352:32] + wire ahb_to_axi4_clock; // @[quasar.scala 379:33] + wire ahb_to_axi4_reset; // @[quasar.scala 379:33] + wire ahb_to_axi4_io_scan_mode; // @[quasar.scala 379:33] + wire ahb_to_axi4_io_bus_clk_en; // @[quasar.scala 379:33] + wire ahb_to_axi4_io_axi_awready; // @[quasar.scala 379:33] + wire ahb_to_axi4_io_axi_arready; // @[quasar.scala 379:33] + wire ahb_to_axi4_io_axi_rvalid; // @[quasar.scala 379:33] + wire [63:0] ahb_to_axi4_io_axi_rdata; // @[quasar.scala 379:33] + wire [1:0] ahb_to_axi4_io_axi_rresp; // @[quasar.scala 379:33] + wire [31:0] ahb_to_axi4_io_ahb_haddr; // @[quasar.scala 379:33] + wire [2:0] ahb_to_axi4_io_ahb_hsize; // @[quasar.scala 379:33] + wire [1:0] ahb_to_axi4_io_ahb_htrans; // @[quasar.scala 379:33] + wire ahb_to_axi4_io_ahb_hwrite; // @[quasar.scala 379:33] + wire [63:0] ahb_to_axi4_io_ahb_hwdata; // @[quasar.scala 379:33] + wire ahb_to_axi4_io_ahb_hsel; // @[quasar.scala 379:33] + wire ahb_to_axi4_io_ahb_hreadyin; // @[quasar.scala 379:33] + wire ahb_to_axi4_io_axi_awvalid; // @[quasar.scala 379:33] + wire [31:0] ahb_to_axi4_io_axi_awaddr; // @[quasar.scala 379:33] + wire [2:0] ahb_to_axi4_io_axi_awsize; // @[quasar.scala 379:33] + wire ahb_to_axi4_io_axi_wvalid; // @[quasar.scala 379:33] + wire [63:0] ahb_to_axi4_io_axi_wdata; // @[quasar.scala 379:33] + wire [7:0] ahb_to_axi4_io_axi_wstrb; // @[quasar.scala 379:33] + wire ahb_to_axi4_io_axi_arvalid; // @[quasar.scala 379:33] + wire [31:0] ahb_to_axi4_io_axi_araddr; // @[quasar.scala 379:33] + wire [2:0] ahb_to_axi4_io_axi_arsize; // @[quasar.scala 379:33] + wire [63:0] ahb_to_axi4_io_ahb_hrdata; // @[quasar.scala 379:33] + wire ahb_to_axi4_io_ahb_hreadyout; // @[quasar.scala 379:33] + wire ahb_to_axi4_io_ahb_hresp; // @[quasar.scala 379:33] + wire _T_1 = dbg_io_dbg_core_rst_l; // @[quasar.scala 124:67] + wire _T_2 = _T_1 | io_scan_mode; // @[quasar.scala 124:70] + wire _T_5 = ~dec_io_dec_pause_state_cg; // @[quasar.scala 125:23] + wire _T_6 = _T_5 | dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 125:50] + ifu ifu ( // @[quasar.scala 116:19] .clock(ifu_clock), .reset(ifu_reset), .io_exu_flush_final(ifu_io_exu_flush_final), @@ -82154,7 +82156,6 @@ module quasar( .io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way(ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way), .io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret(ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret), .io_ifu_dec_dec_aln_ifu_pmu_instr_aligned(ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned), - .io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_lower_wb(ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_lower_wb), .io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb(ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb), .io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt(ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt), .io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt(ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt), @@ -82183,7 +82184,6 @@ module quasar( .io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error(ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error), .io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way(ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way), .io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle(ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle), - .io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb(ifu_io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb), .io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb(ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb), .io_ifu_dec_dec_bp_dec_tlu_bpred_disable(ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable), .io_exu_ifu_exu_bp_exu_i0_br_index_r(ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r), @@ -82254,9 +82254,10 @@ module quasar( .io_iccm_dma_rtag(ifu_io_iccm_dma_rtag), .io_iccm_ready(ifu_io_iccm_ready), .io_iccm_dma_sb_error(ifu_io_iccm_dma_sb_error), + .io_dec_tlu_flush_lower_wb(ifu_io_dec_tlu_flush_lower_wb), .io_scan_mode(ifu_io_scan_mode) ); - dec dec ( // @[quasar.scala 123:19] + dec dec ( // @[quasar.scala 117:19] .clock(dec_clock), .reset(dec_reset), .io_free_clk(dec_io_free_clk), @@ -82280,10 +82281,6 @@ module quasar( .io_mpc_debug_run_ack(dec_io_mpc_debug_run_ack), .io_debug_brkpt_status(dec_io_debug_brkpt_status), .io_lsu_pmu_misaligned_m(dec_io_lsu_pmu_misaligned_m), - .io_dma_pmu_dccm_read(dec_io_dma_pmu_dccm_read), - .io_dma_pmu_dccm_write(dec_io_dma_pmu_dccm_write), - .io_dma_pmu_any_read(dec_io_dma_pmu_any_read), - .io_dma_pmu_any_write(dec_io_dma_pmu_any_write), .io_lsu_fir_addr(dec_io_lsu_fir_addr), .io_lsu_fir_error(dec_io_lsu_fir_error), .io_lsu_trigger_match_m(dec_io_lsu_trigger_match_m), @@ -82301,18 +82298,10 @@ module quasar( .io_lsu_result_corr_r(dec_io_lsu_result_corr_r), .io_lsu_load_stall_any(dec_io_lsu_load_stall_any), .io_lsu_store_stall_any(dec_io_lsu_store_stall_any), - .io_dma_dccm_stall_any(dec_io_dma_dccm_stall_any), - .io_dma_iccm_stall_any(dec_io_dma_iccm_stall_any), .io_iccm_dma_sb_error(dec_io_iccm_dma_sb_error), .io_exu_flush_final(dec_io_exu_flush_final), - .io_mexintpend(dec_io_mexintpend), .io_timer_int(dec_io_timer_int), .io_soft_int(dec_io_soft_int), - .io_pic_claimid(dec_io_pic_claimid), - .io_pic_pl(dec_io_pic_pl), - .io_mhwakeup(dec_io_mhwakeup), - .io_dec_tlu_meicurpl(dec_io_dec_tlu_meicurpl), - .io_dec_tlu_meipt(dec_io_dec_tlu_meipt), .io_dbg_halt_req(dec_io_dbg_halt_req), .io_dbg_resume_req(dec_io_dbg_resume_req), .io_dec_tlu_dbg_halted(dec_io_dec_tlu_dbg_halted), @@ -82367,7 +82356,6 @@ module quasar( .io_rv_trace_pkt_rv_i_ecause_ip(dec_io_rv_trace_pkt_rv_i_ecause_ip), .io_rv_trace_pkt_rv_i_interrupt_ip(dec_io_rv_trace_pkt_rv_i_interrupt_ip), .io_rv_trace_pkt_rv_i_tval_ip(dec_io_rv_trace_pkt_rv_i_tval_ip), - .io_dec_tlu_dma_qos_prty(dec_io_dec_tlu_dma_qos_prty), .io_dec_tlu_misc_clk_override(dec_io_dec_tlu_misc_clk_override), .io_dec_tlu_lsu_clk_override(dec_io_dec_tlu_lsu_clk_override), .io_dec_tlu_bus_clk_override(dec_io_dec_tlu_bus_clk_override), @@ -82425,7 +82413,6 @@ module quasar( .io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error(dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error), .io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way(dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way), .io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle(dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle), - .io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb(dec_io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb), .io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb(dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb), .io_ifu_dec_dec_bp_dec_tlu_bpred_disable(dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable), .io_dec_exu_dec_alu_dec_i0_alu_decode_d(dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d), @@ -82509,7 +82496,6 @@ module quasar( .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error), .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy(dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy), .io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable), - .io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable(dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any(dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any(dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any), @@ -82528,9 +82514,23 @@ module quasar( .io_dec_dbg_dbg_ib_dbg_cmd_write(dec_io_dec_dbg_dbg_ib_dbg_cmd_write), .io_dec_dbg_dbg_ib_dbg_cmd_type(dec_io_dec_dbg_dbg_ib_dbg_cmd_type), .io_dec_dbg_dbg_ib_dbg_cmd_addr(dec_io_dec_dbg_dbg_ib_dbg_cmd_addr), - .io_dec_dbg_dbg_dctl_dbg_cmd_wrdata(dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata) + .io_dec_dbg_dbg_dctl_dbg_cmd_wrdata(dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata), + .io_dec_dma_dctl_dma_dma_dccm_stall_any(dec_io_dec_dma_dctl_dma_dma_dccm_stall_any), + .io_dec_dma_tlu_dma_dma_pmu_dccm_read(dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read), + .io_dec_dma_tlu_dma_dma_pmu_dccm_write(dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write), + .io_dec_dma_tlu_dma_dma_pmu_any_read(dec_io_dec_dma_tlu_dma_dma_pmu_any_read), + .io_dec_dma_tlu_dma_dma_pmu_any_write(dec_io_dec_dma_tlu_dma_dma_pmu_any_write), + .io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty(dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty), + .io_dec_dma_tlu_dma_dma_dccm_stall_any(dec_io_dec_dma_tlu_dma_dma_dccm_stall_any), + .io_dec_dma_tlu_dma_dma_iccm_stall_any(dec_io_dec_dma_tlu_dma_dma_iccm_stall_any), + .io_dec_pic_pic_claimid(dec_io_dec_pic_pic_claimid), + .io_dec_pic_pic_pl(dec_io_dec_pic_pic_pl), + .io_dec_pic_mhwakeup(dec_io_dec_pic_mhwakeup), + .io_dec_pic_dec_tlu_meicurpl(dec_io_dec_pic_dec_tlu_meicurpl), + .io_dec_pic_dec_tlu_meipt(dec_io_dec_pic_dec_tlu_meipt), + .io_dec_pic_mexintpend(dec_io_dec_pic_mexintpend) ); - dbg dbg ( // @[quasar.scala 124:19] + dbg dbg ( // @[quasar.scala 118:19] .clock(dbg_clock), .reset(dbg_reset), .io_dbg_cmd_size(dbg_io_dbg_cmd_size), @@ -82586,7 +82586,7 @@ module quasar( .io_clk_override(dbg_io_clk_override), .io_scan_mode(dbg_io_scan_mode) ); - exu exu ( // @[quasar.scala 125:19] + exu exu ( // @[quasar.scala 119:19] .clock(exu_clock), .reset(exu_reset), .io_scan_mode(exu_io_scan_mode), @@ -82691,7 +82691,7 @@ module quasar( .io_lsu_exu_exu_lsu_rs2_d(exu_io_lsu_exu_exu_lsu_rs2_d), .io_exu_flush_path_final(exu_io_exu_flush_path_final) ); - lsu lsu ( // @[quasar.scala 126:19] + lsu lsu ( // @[quasar.scala 120:19] .clock(lsu_clock), .reset(lsu_reset), .io_clk_override(lsu_io_clk_override), @@ -82722,7 +82722,6 @@ module quasar( .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error), .io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy(lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy), .io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable), - .io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable), .io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable(lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any(lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any), .io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any(lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any), @@ -82830,7 +82829,7 @@ module quasar( .io_scan_mode(lsu_io_scan_mode), .io_free_clk(lsu_io_free_clk) ); - pic_ctrl pic_ctrl_inst ( // @[quasar.scala 127:29] + pic_ctrl pic_ctrl_inst ( // @[quasar.scala 121:29] .clock(pic_ctrl_inst_clock), .reset(pic_ctrl_inst_reset), .io_scan_mode(pic_ctrl_inst_io_scan_mode), @@ -82845,14 +82844,14 @@ module quasar( .io_lsu_pic_picm_wraddr(pic_ctrl_inst_io_lsu_pic_picm_wraddr), .io_lsu_pic_picm_wr_data(pic_ctrl_inst_io_lsu_pic_picm_wr_data), .io_lsu_pic_picm_rd_data(pic_ctrl_inst_io_lsu_pic_picm_rd_data), - .io_meicurpl(pic_ctrl_inst_io_meicurpl), - .io_meipt(pic_ctrl_inst_io_meipt), - .io_mexintpend(pic_ctrl_inst_io_mexintpend), - .io_claimid(pic_ctrl_inst_io_claimid), - .io_pl(pic_ctrl_inst_io_pl), - .io_mhwakeup(pic_ctrl_inst_io_mhwakeup) + .io_dec_pic_pic_claimid(pic_ctrl_inst_io_dec_pic_pic_claimid), + .io_dec_pic_pic_pl(pic_ctrl_inst_io_dec_pic_pic_pl), + .io_dec_pic_mhwakeup(pic_ctrl_inst_io_dec_pic_mhwakeup), + .io_dec_pic_dec_tlu_meicurpl(pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl), + .io_dec_pic_dec_tlu_meipt(pic_ctrl_inst_io_dec_pic_dec_tlu_meipt), + .io_dec_pic_mexintpend(pic_ctrl_inst_io_dec_pic_mexintpend) ); - dma_ctrl dma_ctrl ( // @[quasar.scala 128:24] + dma_ctrl dma_ctrl ( // @[quasar.scala 122:24] .clock(dma_ctrl_clock), .reset(dma_ctrl_reset), .io_free_clk(dma_ctrl_io_free_clk), @@ -82870,38 +82869,34 @@ module quasar( .io_dbg_dma_dbg_dctl_dbg_cmd_wrdata(dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata), .io_dbg_dma_io_dbg_dma_bubble(dma_ctrl_io_dbg_dma_io_dbg_dma_bubble), .io_dbg_dma_io_dma_dbg_ready(dma_ctrl_io_dbg_dma_io_dma_dbg_ready), + .io_dec_dma_dctl_dma_dma_dccm_stall_any(dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any), + .io_dec_dma_tlu_dma_dma_pmu_dccm_read(dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read), + .io_dec_dma_tlu_dma_dma_pmu_dccm_write(dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write), + .io_dec_dma_tlu_dma_dma_pmu_any_read(dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read), + .io_dec_dma_tlu_dma_dma_pmu_any_write(dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write), + .io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty(dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty), + .io_dec_dma_tlu_dma_dma_dccm_stall_any(dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any), + .io_dec_dma_tlu_dma_dma_iccm_stall_any(dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any), .io_iccm_dma_rvalid(dma_ctrl_io_iccm_dma_rvalid), .io_iccm_dma_ecc_error(dma_ctrl_io_iccm_dma_ecc_error), .io_iccm_dma_rtag(dma_ctrl_io_iccm_dma_rtag), .io_iccm_dma_rdata(dma_ctrl_io_iccm_dma_rdata), - .io_dma_dccm_stall_any(dma_ctrl_io_dma_dccm_stall_any), .io_iccm_ready(dma_ctrl_io_iccm_ready), - .io_dec_tlu_dma_qos_prty(dma_ctrl_io_dec_tlu_dma_qos_prty), - .io_dma_pmu_dccm_read(dma_ctrl_io_dma_pmu_dccm_read), - .io_dma_pmu_dccm_write(dma_ctrl_io_dma_pmu_dccm_write), - .io_dma_pmu_any_read(dma_ctrl_io_dma_pmu_any_read), - .io_dma_pmu_any_write(dma_ctrl_io_dma_pmu_any_write), .io_dma_axi_aw_ready(dma_ctrl_io_dma_axi_aw_ready), .io_dma_axi_aw_valid(dma_ctrl_io_dma_axi_aw_valid), - .io_dma_axi_aw_bits_id(dma_ctrl_io_dma_axi_aw_bits_id), .io_dma_axi_aw_bits_addr(dma_ctrl_io_dma_axi_aw_bits_addr), .io_dma_axi_aw_bits_size(dma_ctrl_io_dma_axi_aw_bits_size), .io_dma_axi_w_ready(dma_ctrl_io_dma_axi_w_ready), .io_dma_axi_w_valid(dma_ctrl_io_dma_axi_w_valid), .io_dma_axi_w_bits_data(dma_ctrl_io_dma_axi_w_bits_data), .io_dma_axi_w_bits_strb(dma_ctrl_io_dma_axi_w_bits_strb), - .io_dma_axi_b_ready(dma_ctrl_io_dma_axi_b_ready), .io_dma_axi_b_valid(dma_ctrl_io_dma_axi_b_valid), .io_dma_axi_b_bits_resp(dma_ctrl_io_dma_axi_b_bits_resp), - .io_dma_axi_b_bits_id(dma_ctrl_io_dma_axi_b_bits_id), .io_dma_axi_ar_ready(dma_ctrl_io_dma_axi_ar_ready), .io_dma_axi_ar_valid(dma_ctrl_io_dma_axi_ar_valid), - .io_dma_axi_ar_bits_id(dma_ctrl_io_dma_axi_ar_bits_id), .io_dma_axi_ar_bits_addr(dma_ctrl_io_dma_axi_ar_bits_addr), .io_dma_axi_ar_bits_size(dma_ctrl_io_dma_axi_ar_bits_size), - .io_dma_axi_r_ready(dma_ctrl_io_dma_axi_r_ready), .io_dma_axi_r_valid(dma_ctrl_io_dma_axi_r_valid), - .io_dma_axi_r_bits_id(dma_ctrl_io_dma_axi_r_bits_id), .io_dma_axi_r_bits_data(dma_ctrl_io_dma_axi_r_bits_data), .io_dma_axi_r_bits_resp(dma_ctrl_io_dma_axi_r_bits_resp), .io_lsu_dma_dma_lsc_ctl_dma_dccm_req(dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req), @@ -82937,49 +82932,82 @@ module quasar( .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - axi4_to_ahb axi4_to_ahb ( // @[quasar.scala 318:33] + axi4_to_ahb axi4_to_ahb ( // @[quasar.scala 297:33] .clock(axi4_to_ahb_clock), .reset(axi4_to_ahb_reset), .io_scan_mode(axi4_to_ahb_io_scan_mode), .io_bus_clk_en(axi4_to_ahb_io_bus_clk_en), .io_clk_override(axi4_to_ahb_io_clk_override), .io_axi_awvalid(axi4_to_ahb_io_axi_awvalid), + .io_axi_awid(axi4_to_ahb_io_axi_awid), .io_axi_wvalid(axi4_to_ahb_io_axi_wvalid), + .io_axi_wdata(axi4_to_ahb_io_axi_wdata), .io_axi_bready(axi4_to_ahb_io_axi_bready), .io_axi_arvalid(axi4_to_ahb_io_axi_arvalid), + .io_axi_arid(axi4_to_ahb_io_axi_arid), .io_axi_rready(axi4_to_ahb_io_axi_rready), .io_axi_awready(axi4_to_ahb_io_axi_awready), - .io_axi_wready(axi4_to_ahb_io_axi_wready) + .io_axi_wready(axi4_to_ahb_io_axi_wready), + .io_axi_bvalid(axi4_to_ahb_io_axi_bvalid), + .io_axi_bresp(axi4_to_ahb_io_axi_bresp), + .io_axi_bid(axi4_to_ahb_io_axi_bid), + .io_axi_arready(axi4_to_ahb_io_axi_arready), + .io_axi_rvalid(axi4_to_ahb_io_axi_rvalid), + .io_axi_rid(axi4_to_ahb_io_axi_rid), + .io_axi_rdata(axi4_to_ahb_io_axi_rdata), + .io_axi_rresp(axi4_to_ahb_io_axi_rresp) ); - axi4_to_ahb axi4_to_ahb_1 ( // @[quasar.scala 345:33] + axi4_to_ahb axi4_to_ahb_1 ( // @[quasar.scala 324:33] .clock(axi4_to_ahb_1_clock), .reset(axi4_to_ahb_1_reset), .io_scan_mode(axi4_to_ahb_1_io_scan_mode), .io_bus_clk_en(axi4_to_ahb_1_io_bus_clk_en), .io_clk_override(axi4_to_ahb_1_io_clk_override), .io_axi_awvalid(axi4_to_ahb_1_io_axi_awvalid), + .io_axi_awid(axi4_to_ahb_1_io_axi_awid), .io_axi_wvalid(axi4_to_ahb_1_io_axi_wvalid), + .io_axi_wdata(axi4_to_ahb_1_io_axi_wdata), .io_axi_bready(axi4_to_ahb_1_io_axi_bready), .io_axi_arvalid(axi4_to_ahb_1_io_axi_arvalid), + .io_axi_arid(axi4_to_ahb_1_io_axi_arid), .io_axi_rready(axi4_to_ahb_1_io_axi_rready), .io_axi_awready(axi4_to_ahb_1_io_axi_awready), - .io_axi_wready(axi4_to_ahb_1_io_axi_wready) + .io_axi_wready(axi4_to_ahb_1_io_axi_wready), + .io_axi_bvalid(axi4_to_ahb_1_io_axi_bvalid), + .io_axi_bresp(axi4_to_ahb_1_io_axi_bresp), + .io_axi_bid(axi4_to_ahb_1_io_axi_bid), + .io_axi_arready(axi4_to_ahb_1_io_axi_arready), + .io_axi_rvalid(axi4_to_ahb_1_io_axi_rvalid), + .io_axi_rid(axi4_to_ahb_1_io_axi_rid), + .io_axi_rdata(axi4_to_ahb_1_io_axi_rdata), + .io_axi_rresp(axi4_to_ahb_1_io_axi_rresp) ); - axi4_to_ahb axi4_to_ahb_2 ( // @[quasar.scala 373:32] + axi4_to_ahb axi4_to_ahb_2 ( // @[quasar.scala 352:32] .clock(axi4_to_ahb_2_clock), .reset(axi4_to_ahb_2_reset), .io_scan_mode(axi4_to_ahb_2_io_scan_mode), .io_bus_clk_en(axi4_to_ahb_2_io_bus_clk_en), .io_clk_override(axi4_to_ahb_2_io_clk_override), .io_axi_awvalid(axi4_to_ahb_2_io_axi_awvalid), + .io_axi_awid(axi4_to_ahb_2_io_axi_awid), .io_axi_wvalid(axi4_to_ahb_2_io_axi_wvalid), + .io_axi_wdata(axi4_to_ahb_2_io_axi_wdata), .io_axi_bready(axi4_to_ahb_2_io_axi_bready), .io_axi_arvalid(axi4_to_ahb_2_io_axi_arvalid), + .io_axi_arid(axi4_to_ahb_2_io_axi_arid), .io_axi_rready(axi4_to_ahb_2_io_axi_rready), .io_axi_awready(axi4_to_ahb_2_io_axi_awready), - .io_axi_wready(axi4_to_ahb_2_io_axi_wready) + .io_axi_wready(axi4_to_ahb_2_io_axi_wready), + .io_axi_bvalid(axi4_to_ahb_2_io_axi_bvalid), + .io_axi_bresp(axi4_to_ahb_2_io_axi_bresp), + .io_axi_bid(axi4_to_ahb_2_io_axi_bid), + .io_axi_arready(axi4_to_ahb_2_io_axi_arready), + .io_axi_rvalid(axi4_to_ahb_2_io_axi_rvalid), + .io_axi_rid(axi4_to_ahb_2_io_axi_rid), + .io_axi_rdata(axi4_to_ahb_2_io_axi_rdata), + .io_axi_rresp(axi4_to_ahb_2_io_axi_rresp) ); - ahb_to_axi4 ahb_to_axi4 ( // @[quasar.scala 400:33] + ahb_to_axi4 ahb_to_axi4 ( // @[quasar.scala 379:33] .clock(ahb_to_axi4_clock), .reset(ahb_to_axi4_reset), .io_scan_mode(ahb_to_axi4_io_scan_mode), @@ -82987,514 +83015,524 @@ module quasar( .io_axi_awready(ahb_to_axi4_io_axi_awready), .io_axi_arready(ahb_to_axi4_io_axi_arready), .io_axi_rvalid(ahb_to_axi4_io_axi_rvalid), + .io_axi_rdata(ahb_to_axi4_io_axi_rdata), .io_axi_rresp(ahb_to_axi4_io_axi_rresp), .io_ahb_haddr(ahb_to_axi4_io_ahb_haddr), .io_ahb_hsize(ahb_to_axi4_io_ahb_hsize), .io_ahb_htrans(ahb_to_axi4_io_ahb_htrans), .io_ahb_hwrite(ahb_to_axi4_io_ahb_hwrite), + .io_ahb_hwdata(ahb_to_axi4_io_ahb_hwdata), .io_ahb_hsel(ahb_to_axi4_io_ahb_hsel), .io_ahb_hreadyin(ahb_to_axi4_io_ahb_hreadyin), .io_axi_awvalid(ahb_to_axi4_io_axi_awvalid), + .io_axi_awaddr(ahb_to_axi4_io_axi_awaddr), + .io_axi_awsize(ahb_to_axi4_io_axi_awsize), + .io_axi_wvalid(ahb_to_axi4_io_axi_wvalid), + .io_axi_wdata(ahb_to_axi4_io_axi_wdata), + .io_axi_wstrb(ahb_to_axi4_io_axi_wstrb), .io_axi_arvalid(ahb_to_axi4_io_axi_arvalid), + .io_axi_araddr(ahb_to_axi4_io_axi_araddr), + .io_axi_arsize(ahb_to_axi4_io_axi_arsize), + .io_ahb_hrdata(ahb_to_axi4_io_ahb_hrdata), .io_ahb_hreadyout(ahb_to_axi4_io_ahb_hreadyout), .io_ahb_hresp(ahb_to_axi4_io_ahb_hresp) ); - assign io_lsu_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 307:14] - assign io_lsu_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 307:14] - assign io_lsu_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 307:14] - assign io_lsu_axi_aw_bits_region = lsu_io_axi_aw_bits_region; // @[quasar.scala 307:14] - assign io_lsu_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 307:14] - assign io_lsu_axi_aw_bits_cache = lsu_io_axi_aw_bits_cache; // @[quasar.scala 307:14] - assign io_lsu_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 307:14] - assign io_lsu_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 307:14] - assign io_lsu_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 307:14] - assign io_lsu_axi_b_ready = 1'h1; // @[quasar.scala 307:14] - assign io_lsu_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 307:14] - assign io_lsu_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 307:14] - assign io_lsu_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 307:14] - assign io_lsu_axi_ar_bits_region = lsu_io_axi_ar_bits_region; // @[quasar.scala 307:14] - assign io_lsu_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 307:14] - assign io_lsu_axi_ar_bits_cache = lsu_io_axi_ar_bits_cache; // @[quasar.scala 307:14] - assign io_lsu_axi_r_ready = 1'h1; // @[quasar.scala 307:14] - assign io_ifu_axi_aw_valid = 1'h0; // @[quasar.scala 310:14] - assign io_ifu_axi_w_valid = 1'h0; // @[quasar.scala 310:14] - assign io_ifu_axi_b_ready = 1'h0; // @[quasar.scala 310:14] - assign io_ifu_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 310:14] - assign io_ifu_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 310:14] - assign io_ifu_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 310:14] - assign io_ifu_axi_ar_bits_region = ifu_io_ifu_ar_bits_region; // @[quasar.scala 310:14] - assign io_ifu_axi_r_ready = 1'h1; // @[quasar.scala 310:14] - assign io_sb_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 246:17] - assign io_sb_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 246:17] - assign io_sb_axi_aw_bits_region = dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 246:17] - assign io_sb_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 246:17] - assign io_sb_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 246:17] - assign io_sb_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 246:17] - assign io_sb_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 246:17] - assign io_sb_axi_b_ready = 1'h1; // @[quasar.scala 246:17] - assign io_sb_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 246:17] - assign io_sb_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 246:17] - assign io_sb_axi_ar_bits_region = dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 246:17] - assign io_sb_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 246:17] - assign io_sb_axi_r_ready = 1'h1; // @[quasar.scala 246:17] - assign io_dma_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 311:14] - assign io_dma_axi_w_ready = dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 311:14] - assign io_dma_axi_b_valid = dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 311:14] - assign io_dma_axi_b_bits_resp = dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 311:14] - assign io_dma_axi_b_bits_id = dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 311:14] - assign io_dma_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 311:14] - assign io_dma_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 311:14] - assign io_dma_axi_r_bits_id = dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 311:14] - assign io_dma_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 311:14] - assign io_dma_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 311:14] - assign io_core_rst_l = reset & _T_2; // @[quasar.scala 130:17] - assign io_trace_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 280:25] - assign io_trace_rv_i_address_ip = dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 281:28] - assign io_trace_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 282:26] - assign io_trace_rv_i_exception_ip = dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 283:30] - assign io_trace_rv_i_ecause_ip = dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 284:27] - assign io_trace_rv_i_interrupt_ip = dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 285:30] - assign io_trace_rv_i_tval_ip = dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 286:25] - assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 289:24] - assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 290:23] - assign io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 291:31] - assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[quasar.scala 292:21] - assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[quasar.scala 293:24] - assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[quasar.scala 294:20] - assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[quasar.scala 295:26] - assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[quasar.scala 296:25] - assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[quasar.scala 297:24] - assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[quasar.scala 298:25] - assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[quasar.scala 299:23] - assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[quasar.scala 300:23] - assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[quasar.scala 301:23] - assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[quasar.scala 302:23] - assign io_dccm_wren = lsu_io_dccm_wren; // @[quasar.scala 304:11] - assign io_dccm_rden = lsu_io_dccm_rden; // @[quasar.scala 304:11] - assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[quasar.scala 304:11] - assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[quasar.scala 304:11] - assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[quasar.scala 304:11] - assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[quasar.scala 304:11] - assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[quasar.scala 304:11] - assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[quasar.scala 304:11] - assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[quasar.scala 151:13] - assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[quasar.scala 151:13] - assign io_ic_wr_en = ifu_io_ic_wr_en; // @[quasar.scala 151:13] - assign io_ic_rd_en = ifu_io_ic_rd_en; // @[quasar.scala 151:13] - assign io_ic_wr_data_0 = ifu_io_ic_wr_data_0; // @[quasar.scala 151:13] - assign io_ic_wr_data_1 = ifu_io_ic_wr_data_1; // @[quasar.scala 151:13] - assign io_ic_debug_wr_data = ifu_io_ic_debug_wr_data; // @[quasar.scala 151:13] - assign io_ic_debug_addr = ifu_io_ic_debug_addr; // @[quasar.scala 151:13] - assign io_ic_debug_rd_en = ifu_io_ic_debug_rd_en; // @[quasar.scala 151:13] - assign io_ic_debug_wr_en = ifu_io_ic_debug_wr_en; // @[quasar.scala 151:13] - assign io_ic_debug_tag_array = ifu_io_ic_debug_tag_array; // @[quasar.scala 151:13] - assign io_ic_debug_way = ifu_io_ic_debug_way; // @[quasar.scala 151:13] - assign io_ic_premux_data = ifu_io_ic_premux_data; // @[quasar.scala 151:13] - assign io_ic_sel_premux_data = ifu_io_ic_sel_premux_data; // @[quasar.scala 151:13] - assign io_iccm_rw_addr = ifu_io_iccm_rw_addr; // @[quasar.scala 152:15] - assign io_iccm_buf_correct_ecc = ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 152:15] - assign io_iccm_correction_state = ifu_io_iccm_correction_state; // @[quasar.scala 152:15] - assign io_iccm_wren = ifu_io_iccm_wren; // @[quasar.scala 152:15] - assign io_iccm_rden = ifu_io_iccm_rden; // @[quasar.scala 152:15] - assign io_iccm_wr_size = ifu_io_iccm_wr_size; // @[quasar.scala 152:15] - assign io_iccm_wr_data = ifu_io_iccm_wr_data; // @[quasar.scala 152:15] + assign io_lsu_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 286:14] + assign io_lsu_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 286:14] + assign io_lsu_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 286:14] + assign io_lsu_axi_aw_bits_region = lsu_io_axi_aw_bits_region; // @[quasar.scala 286:14] + assign io_lsu_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 286:14] + assign io_lsu_axi_aw_bits_cache = lsu_io_axi_aw_bits_cache; // @[quasar.scala 286:14] + assign io_lsu_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 286:14] + assign io_lsu_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 286:14] + assign io_lsu_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 286:14] + assign io_lsu_axi_b_ready = 1'h1; // @[quasar.scala 286:14] + assign io_lsu_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 286:14] + assign io_lsu_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 286:14] + assign io_lsu_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 286:14] + assign io_lsu_axi_ar_bits_region = lsu_io_axi_ar_bits_region; // @[quasar.scala 286:14] + assign io_lsu_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 286:14] + assign io_lsu_axi_ar_bits_cache = lsu_io_axi_ar_bits_cache; // @[quasar.scala 286:14] + assign io_lsu_axi_r_ready = 1'h1; // @[quasar.scala 286:14] + assign io_ifu_axi_aw_valid = 1'h0; // @[quasar.scala 289:14] + assign io_ifu_axi_aw_bits_id = 3'h0; // @[quasar.scala 289:14] + assign io_ifu_axi_w_valid = 1'h0; // @[quasar.scala 289:14] + assign io_ifu_axi_w_bits_data = 64'h0; // @[quasar.scala 289:14] + assign io_ifu_axi_b_ready = 1'h0; // @[quasar.scala 289:14] + assign io_ifu_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 289:14] + assign io_ifu_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 289:14] + assign io_ifu_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 289:14] + assign io_ifu_axi_ar_bits_region = ifu_io_ifu_ar_bits_region; // @[quasar.scala 289:14] + assign io_ifu_axi_r_ready = 1'h1; // @[quasar.scala 289:14] + assign io_sb_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 233:17] + assign io_sb_axi_aw_bits_id = 1'h0; // @[quasar.scala 233:17] + assign io_sb_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 233:17] + assign io_sb_axi_aw_bits_region = dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 233:17] + assign io_sb_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 233:17] + assign io_sb_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 233:17] + assign io_sb_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 233:17] + assign io_sb_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 233:17] + assign io_sb_axi_b_ready = 1'h1; // @[quasar.scala 233:17] + assign io_sb_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 233:17] + assign io_sb_axi_ar_bits_id = 1'h0; // @[quasar.scala 233:17] + assign io_sb_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 233:17] + assign io_sb_axi_ar_bits_region = dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 233:17] + assign io_sb_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 233:17] + assign io_sb_axi_r_ready = 1'h1; // @[quasar.scala 233:17] + assign io_dma_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 290:14] + assign io_dma_axi_w_ready = dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 290:14] + assign io_dma_axi_b_valid = dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 290:14] + assign io_dma_axi_b_bits_resp = dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 290:14] + assign io_dma_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 290:14] + assign io_dma_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 290:14] + assign io_dma_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 290:14] + assign io_dma_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 290:14] + assign io_core_rst_l = reset & _T_2; // @[quasar.scala 124:17] + assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 265:19] + assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 265:19] + assign io_rv_trace_pkt_rv_i_address_ip = dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 265:19] + assign io_rv_trace_pkt_rv_i_exception_ip = dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 265:19] + assign io_rv_trace_pkt_rv_i_ecause_ip = dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 265:19] + assign io_rv_trace_pkt_rv_i_interrupt_ip = dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 265:19] + assign io_rv_trace_pkt_rv_i_tval_ip = dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 265:19] + assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 268:24] + assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 269:23] + assign io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 270:31] + assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[quasar.scala 271:21] + assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[quasar.scala 272:24] + assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[quasar.scala 273:20] + assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[quasar.scala 274:26] + assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[quasar.scala 275:25] + assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[quasar.scala 276:24] + assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[quasar.scala 277:25] + assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[quasar.scala 278:23] + assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[quasar.scala 279:23] + assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[quasar.scala 280:23] + assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[quasar.scala 281:23] + assign io_dccm_wren = lsu_io_dccm_wren; // @[quasar.scala 283:11] + assign io_dccm_rden = lsu_io_dccm_rden; // @[quasar.scala 283:11] + assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[quasar.scala 283:11] + assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[quasar.scala 283:11] + assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[quasar.scala 283:11] + assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[quasar.scala 283:11] + assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[quasar.scala 283:11] + assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[quasar.scala 283:11] + assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[quasar.scala 145:13] + assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[quasar.scala 145:13] + assign io_ic_wr_en = ifu_io_ic_wr_en; // @[quasar.scala 145:13] + assign io_ic_rd_en = ifu_io_ic_rd_en; // @[quasar.scala 145:13] + assign io_ic_wr_data_0 = ifu_io_ic_wr_data_0; // @[quasar.scala 145:13] + assign io_ic_wr_data_1 = ifu_io_ic_wr_data_1; // @[quasar.scala 145:13] + assign io_ic_debug_wr_data = ifu_io_ic_debug_wr_data; // @[quasar.scala 145:13] + assign io_ic_debug_addr = ifu_io_ic_debug_addr; // @[quasar.scala 145:13] + assign io_ic_debug_rd_en = ifu_io_ic_debug_rd_en; // @[quasar.scala 145:13] + assign io_ic_debug_wr_en = ifu_io_ic_debug_wr_en; // @[quasar.scala 145:13] + assign io_ic_debug_tag_array = ifu_io_ic_debug_tag_array; // @[quasar.scala 145:13] + assign io_ic_debug_way = ifu_io_ic_debug_way; // @[quasar.scala 145:13] + assign io_ic_premux_data = ifu_io_ic_premux_data; // @[quasar.scala 145:13] + assign io_ic_sel_premux_data = ifu_io_ic_sel_premux_data; // @[quasar.scala 145:13] + assign io_iccm_rw_addr = ifu_io_iccm_rw_addr; // @[quasar.scala 146:15] + assign io_iccm_buf_correct_ecc = ifu_io_iccm_buf_correct_ecc; // @[quasar.scala 146:15] + assign io_iccm_correction_state = ifu_io_iccm_correction_state; // @[quasar.scala 146:15] + assign io_iccm_wren = ifu_io_iccm_wren; // @[quasar.scala 146:15] + assign io_iccm_rden = ifu_io_iccm_rden; // @[quasar.scala 146:15] + assign io_iccm_wr_size = ifu_io_iccm_wr_size; // @[quasar.scala 146:15] + assign io_iccm_wr_data = ifu_io_iccm_wr_data; // @[quasar.scala 146:15] + assign io_dma_hrdata = ahb_to_axi4_io_ahb_hrdata; // @[quasar.scala 479:19 quasar.scala 514:23] + assign io_dma_hreadyout = ahb_to_axi4_io_ahb_hreadyout; // @[quasar.scala 480:22 quasar.scala 515:26] + assign io_dma_hresp = ahb_to_axi4_io_ahb_hresp; // @[quasar.scala 481:18 quasar.scala 516:22] assign ifu_clock = clock; - assign ifu_reset = io_core_rst_l; // @[quasar.scala 141:13] - assign ifu_io_exu_flush_final = dec_io_exu_flush_final; // @[quasar.scala 146:26] - assign ifu_io_exu_flush_path_final = exu_io_exu_flush_path_final; // @[quasar.scala 147:31] - assign ifu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 143:19] - assign ifu_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 144:21] - assign ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d = dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 139:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_lower_wb = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 139:18 quasar.scala 156:54] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 139:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 139:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 139:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 139:18] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 139:18 quasar.scala 157:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 139:18 quasar.scala 157:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 139:18 quasar.scala 157:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 139:18 quasar.scala 157:51] - assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 139:18] - assign ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb = dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 139:18] - assign ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 139:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 139:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 139:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 139:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 139:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 139:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 139:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb = dec_io_ifu_dec_dec_bp_dec_tlu_flush_lower_wb; // @[quasar.scala 139:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 139:18] - assign ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable = dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 139:18] - assign ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r = exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 153:25 quasar.scala 155:43] - assign ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r = exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 153:25 quasar.scala 154:42] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp = exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 153:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken = exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 153:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset = exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 153:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4 = exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 153:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist = exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 153:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset = exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 153:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall = exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 153:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret = exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 153:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja = exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 153:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way = exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 153:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_eghr = exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 153:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_fghr = exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 153:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_index = exu_io_exu_bp_exu_mp_index; // @[quasar.scala 153:25] - assign ifu_io_exu_ifu_exu_bp_exu_mp_btag = exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 153:25] - assign ifu_io_iccm_rd_data = io_iccm_rd_data; // @[quasar.scala 152:15] - assign ifu_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[quasar.scala 152:15] - assign ifu_io_ic_rd_data = io_ic_rd_data; // @[quasar.scala 151:13] - assign ifu_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[quasar.scala 151:13] - assign ifu_io_ic_tag_debug_rd_data = io_ic_tag_debug_rd_data; // @[quasar.scala 151:13] - assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 151:13] - assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 151:13] - assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 151:13] - assign ifu_io_ifu_ar_ready = io_ifu_axi_ar_ready; // @[quasar.scala 310:14 quasar.scala 442:25] - assign ifu_io_ifu_r_valid = io_ifu_axi_r_valid; // @[quasar.scala 310:14 quasar.scala 443:24] - assign ifu_io_ifu_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar.scala 310:14 quasar.scala 444:26] - assign ifu_io_ifu_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar.scala 310:14 quasar.scala 445:28] - assign ifu_io_ifu_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar.scala 310:14 quasar.scala 446:28] - assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 149:25] - assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 150:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 150:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 150:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 150:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 150:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 150:18] - assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 150:18] - assign ifu_io_scan_mode = io_scan_mode; // @[quasar.scala 142:20] + assign ifu_reset = io_core_rst_l; // @[quasar.scala 135:13] + assign ifu_io_exu_flush_final = dec_io_exu_flush_final; // @[quasar.scala 140:26] + assign ifu_io_exu_flush_path_final = exu_io_exu_flush_path_final; // @[quasar.scala 141:31] + assign ifu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 137:19] + assign ifu_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 138:21] + assign ifu_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d = dec_io_ifu_dec_dec_aln_aln_dec_dec_i0_decode_d; // @[quasar.scala 133:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_flush_err_wb; // @[quasar.scala 133:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_i0_commit_cmt; // @[quasar.scala 133:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 133:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_fence_i_wb; // @[quasar.scala 133:18] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wrdata; // @[quasar.scala 133:18 quasar.scala 151:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_dicawics; // @[quasar.scala 133:18 quasar.scala 151:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[quasar.scala 133:18 quasar.scala 151:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[quasar.scala 133:18 quasar.scala 151:51] + assign ifu_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 133:18] + assign ifu_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb = dec_io_ifu_dec_dec_ifc_dec_tlu_flush_noredir_wb; // @[quasar.scala 133:18] + assign ifu_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 133:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_valid; // @[quasar.scala 133:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_hist; // @[quasar.scala 133:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_error; // @[quasar.scala 133:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error; // @[quasar.scala 133:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_way; // @[quasar.scala 133:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle = dec_io_ifu_dec_dec_bp_dec_tlu_br0_r_pkt_bits_middle; // @[quasar.scala 133:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb = dec_io_ifu_dec_dec_bp_dec_tlu_flush_leak_one_wb; // @[quasar.scala 133:18] + assign ifu_io_ifu_dec_dec_bp_dec_tlu_bpred_disable = dec_io_ifu_dec_dec_bp_dec_tlu_bpred_disable; // @[quasar.scala 133:18] + assign ifu_io_exu_ifu_exu_bp_exu_i0_br_index_r = exu_io_dec_exu_tlu_exu_exu_i0_br_index_r; // @[quasar.scala 147:25 quasar.scala 149:43] + assign ifu_io_exu_ifu_exu_bp_exu_i0_br_fghr_r = exu_io_exu_bp_exu_i0_br_fghr_r; // @[quasar.scala 147:25 quasar.scala 148:42] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_misp = exu_io_exu_bp_exu_mp_pkt_bits_misp; // @[quasar.scala 147:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_ataken = exu_io_exu_bp_exu_mp_pkt_bits_ataken; // @[quasar.scala 147:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_boffset = exu_io_exu_bp_exu_mp_pkt_bits_boffset; // @[quasar.scala 147:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pc4 = exu_io_exu_bp_exu_mp_pkt_bits_pc4; // @[quasar.scala 147:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_hist = exu_io_exu_bp_exu_mp_pkt_bits_hist; // @[quasar.scala 147:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_toffset = exu_io_exu_bp_exu_mp_pkt_bits_toffset; // @[quasar.scala 147:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pcall = exu_io_exu_bp_exu_mp_pkt_bits_pcall; // @[quasar.scala 147:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pret = exu_io_exu_bp_exu_mp_pkt_bits_pret; // @[quasar.scala 147:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_pja = exu_io_exu_bp_exu_mp_pkt_bits_pja; // @[quasar.scala 147:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_pkt_bits_way = exu_io_exu_bp_exu_mp_pkt_bits_way; // @[quasar.scala 147:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_eghr = exu_io_exu_bp_exu_mp_eghr; // @[quasar.scala 147:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_fghr = exu_io_exu_bp_exu_mp_fghr; // @[quasar.scala 147:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_index = exu_io_exu_bp_exu_mp_index; // @[quasar.scala 147:25] + assign ifu_io_exu_ifu_exu_bp_exu_mp_btag = exu_io_exu_bp_exu_mp_btag; // @[quasar.scala 147:25] + assign ifu_io_iccm_rd_data = io_iccm_rd_data; // @[quasar.scala 146:15] + assign ifu_io_iccm_rd_data_ecc = io_iccm_rd_data_ecc; // @[quasar.scala 146:15] + assign ifu_io_ic_rd_data = io_ic_rd_data; // @[quasar.scala 145:13] + assign ifu_io_ic_debug_rd_data = io_ic_debug_rd_data; // @[quasar.scala 145:13] + assign ifu_io_ic_tag_debug_rd_data = io_ic_tag_debug_rd_data; // @[quasar.scala 145:13] + assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 145:13] + assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 145:13] + assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 145:13] + assign ifu_io_ifu_ar_ready = axi4_to_ahb_1_io_axi_arready; // @[quasar.scala 289:14 quasar.scala 421:25] + assign ifu_io_ifu_r_valid = axi4_to_ahb_1_io_axi_rvalid; // @[quasar.scala 289:14 quasar.scala 422:24] + assign ifu_io_ifu_r_bits_id = {{2'd0}, axi4_to_ahb_1_io_axi_rid}; // @[quasar.scala 289:14 quasar.scala 423:26] + assign ifu_io_ifu_r_bits_data = axi4_to_ahb_1_io_axi_rdata; // @[quasar.scala 289:14 quasar.scala 424:28] + assign ifu_io_ifu_r_bits_resp = axi4_to_ahb_1_io_axi_rresp; // @[quasar.scala 289:14 quasar.scala 425:28] + assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 143:25] + assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 144:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 144:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_addr = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_addr; // @[quasar.scala 144:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_sz = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_sz; // @[quasar.scala 144:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_write = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_write; // @[quasar.scala 144:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_wdata = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_wdata; // @[quasar.scala 144:18] + assign ifu_io_ifu_dma_dma_mem_ctl_dma_mem_tag = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_mem_tag; // @[quasar.scala 144:18] + assign ifu_io_dec_tlu_flush_lower_wb = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 150:33] + assign ifu_io_scan_mode = io_scan_mode; // @[quasar.scala 136:20] assign dec_clock = clock; - assign dec_reset = io_core_rst_l; // @[quasar.scala 160:13] - assign dec_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 161:19] - assign dec_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 162:21] - assign dec_io_lsu_fastint_stall_any = lsu_io_lsu_fastint_stall_any; // @[quasar.scala 163:32] - assign dec_io_rst_vec = io_rst_vec; // @[quasar.scala 164:18] - assign dec_io_nmi_int = io_nmi_int; // @[quasar.scala 165:18] - assign dec_io_nmi_vec = io_nmi_vec; // @[quasar.scala 166:18] - assign dec_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar.scala 167:25] - assign dec_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar.scala 168:24] - assign dec_io_core_id = io_core_id; // @[quasar.scala 169:18] - assign dec_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar.scala 170:29] - assign dec_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar.scala 171:28] - assign dec_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar.scala 172:28] - assign dec_io_lsu_pmu_misaligned_m = lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 175:31] - assign dec_io_dma_pmu_dccm_read = dma_ctrl_io_dma_pmu_dccm_read; // @[quasar.scala 176:28] - assign dec_io_dma_pmu_dccm_write = dma_ctrl_io_dma_pmu_dccm_write; // @[quasar.scala 177:29] - assign dec_io_dma_pmu_any_read = dma_ctrl_io_dma_pmu_any_read; // @[quasar.scala 178:27] - assign dec_io_dma_pmu_any_write = dma_ctrl_io_dma_pmu_any_write; // @[quasar.scala 179:28] - assign dec_io_lsu_fir_addr = lsu_io_lsu_fir_addr; // @[quasar.scala 180:23] - assign dec_io_lsu_fir_error = lsu_io_lsu_fir_error; // @[quasar.scala 181:24] - assign dec_io_lsu_trigger_match_m = lsu_io_lsu_trigger_match_m; // @[quasar.scala 182:30] - assign dec_io_lsu_idle_any = lsu_io_lsu_idle_any; // @[quasar.scala 184:23] - assign dec_io_lsu_error_pkt_r_valid = lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 185:26] - assign dec_io_lsu_error_pkt_r_bits_single_ecc_error = lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 185:26] - assign dec_io_lsu_error_pkt_r_bits_inst_type = lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 185:26] - assign dec_io_lsu_error_pkt_r_bits_exc_type = lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 185:26] - assign dec_io_lsu_error_pkt_r_bits_mscause = lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 185:26] - assign dec_io_lsu_error_pkt_r_bits_addr = lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 185:26] - assign dec_io_lsu_single_ecc_error_incr = lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 186:36] - assign dec_io_exu_div_result = exu_io_exu_div_result; // @[quasar.scala 187:25] - assign dec_io_exu_div_wren = exu_io_exu_div_wren; // @[quasar.scala 188:23] - assign dec_io_lsu_result_m = lsu_io_lsu_result_m; // @[quasar.scala 189:23] - assign dec_io_lsu_result_corr_r = lsu_io_lsu_result_corr_r; // @[quasar.scala 190:28] - assign dec_io_lsu_load_stall_any = lsu_io_lsu_load_stall_any; // @[quasar.scala 191:29] - assign dec_io_lsu_store_stall_any = lsu_io_lsu_store_stall_any; // @[quasar.scala 192:30] - assign dec_io_dma_dccm_stall_any = dma_ctrl_io_dma_dccm_stall_any; // @[quasar.scala 193:29] - assign dec_io_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 194:29] - assign dec_io_iccm_dma_sb_error = ifu_io_iccm_dma_sb_error; // @[quasar.scala 195:28] - assign dec_io_exu_flush_final = exu_io_exu_flush_final; // @[quasar.scala 196:26] - assign dec_io_mexintpend = pic_ctrl_inst_io_mexintpend; // @[quasar.scala 197:21] - assign dec_io_timer_int = io_timer_int; // @[quasar.scala 205:20] - assign dec_io_soft_int = io_soft_int; // @[quasar.scala 198:19] - assign dec_io_pic_claimid = pic_ctrl_inst_io_claimid; // @[quasar.scala 199:22] - assign dec_io_pic_pl = pic_ctrl_inst_io_pl; // @[quasar.scala 200:17] - assign dec_io_mhwakeup = pic_ctrl_inst_io_mhwakeup; // @[quasar.scala 201:19] - assign dec_io_dbg_halt_req = dbg_io_dbg_halt_req; // @[quasar.scala 202:23] - assign dec_io_dbg_resume_req = dbg_io_dbg_resume_req; // @[quasar.scala 203:25] - assign dec_io_exu_i0_br_way_r = exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 204:26] - assign dec_io_scan_mode = io_scan_mode; // @[quasar.scala 206:20] - assign dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst = ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned = ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle = ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 139:18] - assign dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall = ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 139:18] - assign dec_io_dec_exu_dec_alu_exu_i0_pc_x = exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 209:18] - assign dec_io_dec_exu_decode_exu_exu_i0_result_x = exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 209:18] - assign dec_io_dec_exu_decode_exu_exu_csr_rs1_x = exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 209:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r = exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 209:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 209:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 209:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r = exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 209:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r = exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 209:18] - assign dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r = exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 209:18] - assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 209:18] - assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 209:18] - assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 209:18] - assign dec_io_dec_exu_tlu_exu_exu_npc_r = exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 209:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 173:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 173:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 173:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 173:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 173:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 173:18] - assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 173:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 173:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 173:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 173:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 173:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 173:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 173:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 173:18] - assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 173:18] - assign dec_io_lsu_tlu_lsu_pmu_load_external_m = lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 174:18] - assign dec_io_lsu_tlu_lsu_pmu_store_external_m = lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 174:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 183:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_write = dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 183:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_type = dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 183:18] - assign dec_io_dec_dbg_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 183:18] - assign dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 183:18] + assign dec_reset = io_core_rst_l; // @[quasar.scala 154:13] + assign dec_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 155:19] + assign dec_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 156:21] + assign dec_io_lsu_fastint_stall_any = lsu_io_lsu_fastint_stall_any; // @[quasar.scala 157:32] + assign dec_io_rst_vec = io_rst_vec; // @[quasar.scala 158:18] + assign dec_io_nmi_int = io_nmi_int; // @[quasar.scala 159:18] + assign dec_io_nmi_vec = io_nmi_vec; // @[quasar.scala 160:18] + assign dec_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar.scala 161:25] + assign dec_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar.scala 162:24] + assign dec_io_core_id = io_core_id; // @[quasar.scala 163:18] + assign dec_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar.scala 164:29] + assign dec_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar.scala 165:28] + assign dec_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar.scala 166:28] + assign dec_io_lsu_pmu_misaligned_m = lsu_io_lsu_pmu_misaligned_m; // @[quasar.scala 169:31] + assign dec_io_lsu_fir_addr = lsu_io_lsu_fir_addr; // @[quasar.scala 172:23] + assign dec_io_lsu_fir_error = lsu_io_lsu_fir_error; // @[quasar.scala 173:24] + assign dec_io_lsu_trigger_match_m = lsu_io_lsu_trigger_match_m; // @[quasar.scala 174:30] + assign dec_io_lsu_idle_any = lsu_io_lsu_idle_any; // @[quasar.scala 176:23] + assign dec_io_lsu_error_pkt_r_valid = lsu_io_lsu_error_pkt_r_valid; // @[quasar.scala 177:26] + assign dec_io_lsu_error_pkt_r_bits_single_ecc_error = lsu_io_lsu_error_pkt_r_bits_single_ecc_error; // @[quasar.scala 177:26] + assign dec_io_lsu_error_pkt_r_bits_inst_type = lsu_io_lsu_error_pkt_r_bits_inst_type; // @[quasar.scala 177:26] + assign dec_io_lsu_error_pkt_r_bits_exc_type = lsu_io_lsu_error_pkt_r_bits_exc_type; // @[quasar.scala 177:26] + assign dec_io_lsu_error_pkt_r_bits_mscause = lsu_io_lsu_error_pkt_r_bits_mscause; // @[quasar.scala 177:26] + assign dec_io_lsu_error_pkt_r_bits_addr = lsu_io_lsu_error_pkt_r_bits_addr; // @[quasar.scala 177:26] + assign dec_io_lsu_single_ecc_error_incr = lsu_io_lsu_single_ecc_error_incr; // @[quasar.scala 178:36] + assign dec_io_exu_div_result = exu_io_exu_div_result; // @[quasar.scala 179:25] + assign dec_io_exu_div_wren = exu_io_exu_div_wren; // @[quasar.scala 180:23] + assign dec_io_lsu_result_m = lsu_io_lsu_result_m; // @[quasar.scala 181:23] + assign dec_io_lsu_result_corr_r = lsu_io_lsu_result_corr_r; // @[quasar.scala 182:28] + assign dec_io_lsu_load_stall_any = lsu_io_lsu_load_stall_any; // @[quasar.scala 183:29] + assign dec_io_lsu_store_stall_any = lsu_io_lsu_store_stall_any; // @[quasar.scala 184:30] + assign dec_io_iccm_dma_sb_error = ifu_io_iccm_dma_sb_error; // @[quasar.scala 185:28] + assign dec_io_exu_flush_final = exu_io_exu_flush_final; // @[quasar.scala 186:26] + assign dec_io_timer_int = io_timer_int; // @[quasar.scala 192:20] + assign dec_io_soft_int = io_soft_int; // @[quasar.scala 188:19] + assign dec_io_dbg_halt_req = dbg_io_dbg_halt_req; // @[quasar.scala 189:23] + assign dec_io_dbg_resume_req = dbg_io_dbg_resume_req; // @[quasar.scala 190:25] + assign dec_io_exu_i0_br_way_r = exu_io_exu_bp_exu_i0_br_way_r; // @[quasar.scala 191:26] + assign dec_io_scan_mode = io_scan_mode; // @[quasar.scala 193:20] + assign dec_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst = ifu_io_ifu_dec_dec_aln_aln_dec_ifu_i0_cinst; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_type; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_icaf_f1; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_dbecc; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_index; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_fghr; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_bp_btag; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_valid; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_instr; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4 = ifu_io_ifu_dec_dec_aln_aln_ib_ifu_i0_pc4; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_valid; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_toffset; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_hist; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_error; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_br_start_error; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_prett; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_way; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret = ifu_io_ifu_dec_dec_aln_aln_ib_i0_brp_bits_ret; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned = ifu_io_ifu_dec_dec_aln_ifu_pmu_instr_aligned; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_miss; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_ic_hit; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_error; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_busy; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn = ifu_io_ifu_dec_dec_mem_ctrl_ifu_pmu_bus_trxn; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_error_start; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err = ifu_io_ifu_dec_dec_mem_ctrl_ifu_iccm_rd_ecc_single_err; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid = ifu_io_ifu_dec_dec_mem_ctrl_ifu_ic_debug_rd_data_valid; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle = ifu_io_ifu_dec_dec_mem_ctrl_ifu_miss_state_idle; // @[quasar.scala 133:18] + assign dec_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall = ifu_io_ifu_dec_dec_ifc_ifu_pmu_fetch_stall; // @[quasar.scala 133:18] + assign dec_io_dec_exu_dec_alu_exu_i0_pc_x = exu_io_dec_exu_dec_alu_exu_i0_pc_x; // @[quasar.scala 196:18] + assign dec_io_dec_exu_decode_exu_exu_i0_result_x = exu_io_dec_exu_decode_exu_exu_i0_result_x; // @[quasar.scala 196:18] + assign dec_io_dec_exu_decode_exu_exu_csr_rs1_x = exu_io_dec_exu_decode_exu_exu_csr_rs1_x; // @[quasar.scala 196:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_hist_r = exu_io_dec_exu_tlu_exu_exu_i0_br_hist_r; // @[quasar.scala 196:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_error_r; // @[quasar.scala 196:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_start_error_r = exu_io_dec_exu_tlu_exu_exu_i0_br_start_error_r; // @[quasar.scala 196:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_valid_r = exu_io_dec_exu_tlu_exu_exu_i0_br_valid_r; // @[quasar.scala 196:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_mp_r = exu_io_dec_exu_tlu_exu_exu_i0_br_mp_r; // @[quasar.scala 196:18] + assign dec_io_dec_exu_tlu_exu_exu_i0_br_middle_r = exu_io_dec_exu_tlu_exu_exu_i0_br_middle_r; // @[quasar.scala 196:18] + assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_misp; // @[quasar.scala 196:18] + assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken = exu_io_dec_exu_tlu_exu_exu_pmu_i0_br_ataken; // @[quasar.scala 196:18] + assign dec_io_dec_exu_tlu_exu_exu_pmu_i0_pc4 = exu_io_dec_exu_tlu_exu_exu_pmu_i0_pc4; // @[quasar.scala 196:18] + assign dec_io_dec_exu_tlu_exu_exu_npc_r = exu_io_dec_exu_tlu_exu_exu_npc_r; // @[quasar.scala 196:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_trxn; // @[quasar.scala 167:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_misaligned; // @[quasar.scala 167:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_error; // @[quasar.scala 167:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy = lsu_io_lsu_dec_tlu_busbuff_lsu_pmu_bus_busy; // @[quasar.scala 167:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_load_any; // @[quasar.scala 167:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_store_any; // @[quasar.scala 167:18] + assign dec_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any = lsu_io_lsu_dec_tlu_busbuff_lsu_imprecise_error_addr_any; // @[quasar.scala 167:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_valid_m; // @[quasar.scala 167:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_tag_m; // @[quasar.scala 167:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_r; // @[quasar.scala 167:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_inv_tag_r; // @[quasar.scala 167:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_valid; // @[quasar.scala 167:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_error; // @[quasar.scala 167:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data_tag; // @[quasar.scala 167:18] + assign dec_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data = lsu_io_lsu_dec_dctl_busbuff_lsu_nonblock_load_data; // @[quasar.scala 167:18] + assign dec_io_lsu_tlu_lsu_pmu_load_external_m = lsu_io_lsu_tlu_lsu_pmu_load_external_m; // @[quasar.scala 168:18] + assign dec_io_lsu_tlu_lsu_pmu_store_external_m = lsu_io_lsu_tlu_lsu_pmu_store_external_m; // @[quasar.scala 168:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dec_dbg_ib_dbg_cmd_valid; // @[quasar.scala 175:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_write = dbg_io_dbg_dec_dbg_ib_dbg_cmd_write; // @[quasar.scala 175:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_type = dbg_io_dbg_dec_dbg_ib_dbg_cmd_type; // @[quasar.scala 175:18] + assign dec_io_dec_dbg_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dec_dbg_ib_dbg_cmd_addr; // @[quasar.scala 175:18] + assign dec_io_dec_dbg_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 175:18] + assign dec_io_dec_dma_dctl_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_dctl_dma_dma_dccm_stall_any; // @[quasar.scala 170:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_read; // @[quasar.scala 170:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_dccm_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_dccm_write; // @[quasar.scala 170:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_any_read = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_read; // @[quasar.scala 170:18] + assign dec_io_dec_dma_tlu_dma_dma_pmu_any_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 170:18] + assign dec_io_dec_dma_tlu_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 170:18] + assign dec_io_dec_dma_tlu_dma_dma_iccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 170:18] + assign dec_io_dec_pic_pic_claimid = pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 263:28] + assign dec_io_dec_pic_pic_pl = pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 263:28] + assign dec_io_dec_pic_mhwakeup = pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 263:28] + assign dec_io_dec_pic_mexintpend = pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 263:28] assign dbg_clock = clock; - assign dbg_reset = io_core_rst_l; // @[quasar.scala 234:13] - assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[quasar.scala 235:26] - assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[quasar.scala 236:28] - assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[quasar.scala 237:28] - assign dbg_io_dec_tlu_debug_mode = dec_io_dec_tlu_debug_mode; // @[quasar.scala 238:29] - assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[quasar.scala 239:29] - assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 240:34] - assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[quasar.scala 241:29] - assign dbg_io_dmi_reg_en = io_dmi_reg_en; // @[quasar.scala 242:21] - assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 243:23] - assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 244:24] - assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 245:24] - assign dbg_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar.scala 246:17 quasar.scala 449:28] - assign dbg_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar.scala 246:17 quasar.scala 450:27] - assign dbg_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar.scala 246:17 quasar.scala 451:27] - assign dbg_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar.scala 246:17 quasar.scala 452:31] - assign dbg_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar.scala 246:17 quasar.scala 453:28] - assign dbg_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar.scala 246:17 quasar.scala 454:27] - assign dbg_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar.scala 246:17 quasar.scala 456:31] - assign dbg_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar.scala 246:17 quasar.scala 457:31] - assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 260:26] - assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 247:25] - assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 248:20] - assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 249:23] - assign dbg_io_scan_mode = io_scan_mode; // @[quasar.scala 250:20] + assign dbg_reset = io_core_rst_l; // @[quasar.scala 221:13] + assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[quasar.scala 222:26] + assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[quasar.scala 223:28] + assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[quasar.scala 224:28] + assign dbg_io_dec_tlu_debug_mode = dec_io_dec_tlu_debug_mode; // @[quasar.scala 225:29] + assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[quasar.scala 226:29] + assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 227:34] + assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[quasar.scala 228:29] + assign dbg_io_dmi_reg_en = io_dmi_reg_en; // @[quasar.scala 229:21] + assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 230:23] + assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 231:24] + assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 232:24] + assign dbg_io_sb_axi_aw_ready = axi4_to_ahb_2_io_axi_awready; // @[quasar.scala 233:17 quasar.scala 428:28] + assign dbg_io_sb_axi_w_ready = axi4_to_ahb_2_io_axi_wready; // @[quasar.scala 233:17 quasar.scala 429:27] + assign dbg_io_sb_axi_b_valid = axi4_to_ahb_2_io_axi_bvalid; // @[quasar.scala 233:17 quasar.scala 430:27] + assign dbg_io_sb_axi_b_bits_resp = axi4_to_ahb_2_io_axi_bresp; // @[quasar.scala 233:17 quasar.scala 431:31] + assign dbg_io_sb_axi_ar_ready = axi4_to_ahb_2_io_axi_arready; // @[quasar.scala 233:17 quasar.scala 432:28] + assign dbg_io_sb_axi_r_valid = axi4_to_ahb_2_io_axi_rvalid; // @[quasar.scala 233:17 quasar.scala 433:27] + assign dbg_io_sb_axi_r_bits_data = axi4_to_ahb_2_io_axi_rdata; // @[quasar.scala 233:17 quasar.scala 435:31] + assign dbg_io_sb_axi_r_bits_resp = axi4_to_ahb_2_io_axi_rresp; // @[quasar.scala 233:17 quasar.scala 436:31] + assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 247:26] + assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 234:25] + assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 235:20] + assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 236:23] + assign dbg_io_scan_mode = io_scan_mode; // @[quasar.scala 237:20] assign exu_clock = clock; - assign exu_reset = io_core_rst_l; // @[quasar.scala 210:13] - assign exu_io_scan_mode = io_scan_mode; // @[quasar.scala 211:20] - assign exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d = dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 209:18] - assign exu_io_dec_exu_dec_alu_dec_csr_ren_d = dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 209:18] - assign exu_io_dec_exu_dec_alu_dec_i0_br_immed_d = dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 209:18] - assign exu_io_dec_exu_dec_div_div_p_valid = dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 209:18] - assign exu_io_dec_exu_dec_div_div_p_bits_unsign = dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 209:18] - assign exu_io_dec_exu_dec_div_div_p_bits_rem = dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 209:18] - assign exu_io_dec_exu_dec_div_dec_div_cancel = dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_data_en = dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_ctl_en = dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_ap_land = dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_ap_lor = dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_ap_lxor = dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_ap_sll = dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_ap_srl = dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_ap_sra = dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_ap_beq = dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_ap_bne = dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_ap_blt = dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_ap_bge = dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_ap_add = dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_ap_sub = dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_ap_slt = dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_ap_unsign = dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_ap_jal = dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_ap_predict_t = dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_ap_predict_nt = dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_ap_csr_write = dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_ap_csr_imm = dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4 = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_predict_fghr_d = dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_predict_index_d = dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_i0_predict_btag_d = dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_i0_immed_d = dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_i0_select_pc_d = dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_mul_p_valid = dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_mul_p_bits_low = dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_pred_correct_npc_x = dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 209:18] - assign exu_io_dec_exu_decode_exu_dec_extint_stall = dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 209:18] - assign exu_io_dec_exu_tlu_exu_dec_tlu_meihap = dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 209:18] - assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 209:18] - assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 209:18] - assign exu_io_dec_exu_ib_exu_dec_i0_pc_d = dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 209:18] - assign exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d = dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 209:18] - assign exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 209:18] - assign exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 209:18] - assign exu_io_dbg_cmd_wrdata = {{30'd0}, dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata}; // @[quasar.scala 212:25] + assign exu_reset = io_core_rst_l; // @[quasar.scala 197:13] + assign exu_io_scan_mode = io_scan_mode; // @[quasar.scala 198:20] + assign exu_io_dec_exu_dec_alu_dec_i0_alu_decode_d = dec_io_dec_exu_dec_alu_dec_i0_alu_decode_d; // @[quasar.scala 196:18] + assign exu_io_dec_exu_dec_alu_dec_csr_ren_d = dec_io_dec_exu_dec_alu_dec_csr_ren_d; // @[quasar.scala 196:18] + assign exu_io_dec_exu_dec_alu_dec_i0_br_immed_d = dec_io_dec_exu_dec_alu_dec_i0_br_immed_d; // @[quasar.scala 196:18] + assign exu_io_dec_exu_dec_div_div_p_valid = dec_io_dec_exu_dec_div_div_p_valid; // @[quasar.scala 196:18] + assign exu_io_dec_exu_dec_div_div_p_bits_unsign = dec_io_dec_exu_dec_div_div_p_bits_unsign; // @[quasar.scala 196:18] + assign exu_io_dec_exu_dec_div_div_p_bits_rem = dec_io_dec_exu_dec_div_div_p_bits_rem; // @[quasar.scala 196:18] + assign exu_io_dec_exu_dec_div_dec_div_cancel = dec_io_dec_exu_dec_div_dec_div_cancel; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_data_en = dec_io_dec_exu_decode_exu_dec_data_en; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_ctl_en = dec_io_dec_exu_decode_exu_dec_ctl_en; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_ap_land = dec_io_dec_exu_decode_exu_i0_ap_land; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_ap_lor = dec_io_dec_exu_decode_exu_i0_ap_lor; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_ap_lxor = dec_io_dec_exu_decode_exu_i0_ap_lxor; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_ap_sll = dec_io_dec_exu_decode_exu_i0_ap_sll; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_ap_srl = dec_io_dec_exu_decode_exu_i0_ap_srl; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_ap_sra = dec_io_dec_exu_decode_exu_i0_ap_sra; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_ap_beq = dec_io_dec_exu_decode_exu_i0_ap_beq; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_ap_bne = dec_io_dec_exu_decode_exu_i0_ap_bne; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_ap_blt = dec_io_dec_exu_decode_exu_i0_ap_blt; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_ap_bge = dec_io_dec_exu_decode_exu_i0_ap_bge; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_ap_add = dec_io_dec_exu_decode_exu_i0_ap_add; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_ap_sub = dec_io_dec_exu_decode_exu_i0_ap_sub; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_ap_slt = dec_io_dec_exu_decode_exu_i0_ap_slt; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_ap_unsign = dec_io_dec_exu_decode_exu_i0_ap_unsign; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_ap_jal = dec_io_dec_exu_decode_exu_i0_ap_jal; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_ap_predict_t = dec_io_dec_exu_decode_exu_i0_ap_predict_t; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_ap_predict_nt = dec_io_dec_exu_decode_exu_i0_ap_predict_nt; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_ap_csr_write = dec_io_dec_exu_decode_exu_i0_ap_csr_write; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_ap_csr_imm = dec_io_dec_exu_decode_exu_i0_ap_csr_imm; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_valid; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4 = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pc4; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_hist; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_toffset; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_error; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_br_start_error; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_prett; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pcall; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pret; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_pja; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way = dec_io_dec_exu_decode_exu_dec_i0_predict_p_d_bits_way; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_predict_fghr_d = dec_io_dec_exu_decode_exu_i0_predict_fghr_d; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_predict_index_d = dec_io_dec_exu_decode_exu_i0_predict_index_d; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_i0_predict_btag_d = dec_io_dec_exu_decode_exu_i0_predict_btag_d; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs1_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_en_d; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs2_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_en_d; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_i0_immed_d = dec_io_dec_exu_decode_exu_dec_i0_immed_d; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_data_d; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_data_d; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_i0_select_pc_d = dec_io_dec_exu_decode_exu_dec_i0_select_pc_d; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs1_bypass_en_d; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d = dec_io_dec_exu_decode_exu_dec_i0_rs2_bypass_en_d; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_mul_p_valid = dec_io_dec_exu_decode_exu_mul_p_valid; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_mul_p_bits_rs1_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs1_sign; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_mul_p_bits_rs2_sign = dec_io_dec_exu_decode_exu_mul_p_bits_rs2_sign; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_mul_p_bits_low = dec_io_dec_exu_decode_exu_mul_p_bits_low; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_pred_correct_npc_x = dec_io_dec_exu_decode_exu_pred_correct_npc_x; // @[quasar.scala 196:18] + assign exu_io_dec_exu_decode_exu_dec_extint_stall = dec_io_dec_exu_decode_exu_dec_extint_stall; // @[quasar.scala 196:18] + assign exu_io_dec_exu_tlu_exu_dec_tlu_meihap = dec_io_dec_exu_tlu_exu_dec_tlu_meihap; // @[quasar.scala 196:18] + assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 196:18] + assign exu_io_dec_exu_tlu_exu_dec_tlu_flush_path_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_path_r; // @[quasar.scala 196:18] + assign exu_io_dec_exu_ib_exu_dec_i0_pc_d = dec_io_dec_exu_ib_exu_dec_i0_pc_d; // @[quasar.scala 196:18] + assign exu_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d = dec_io_dec_exu_ib_exu_dec_debug_wdata_rs1_d; // @[quasar.scala 196:18] + assign exu_io_dec_exu_gpr_exu_gpr_i0_rs1_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs1_d; // @[quasar.scala 196:18] + assign exu_io_dec_exu_gpr_exu_gpr_i0_rs2_d = dec_io_dec_exu_gpr_exu_gpr_i0_rs2_d; // @[quasar.scala 196:18] + assign exu_io_dbg_cmd_wrdata = {{30'd0}, dbg_io_dbg_dec_dbg_dctl_dbg_cmd_wrdata}; // @[quasar.scala 199:25] assign lsu_clock = clock; - assign lsu_reset = io_core_rst_l; // @[quasar.scala 215:13] - assign lsu_io_clk_override = dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 216:23] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 229:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 229:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 229:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 229:18] - assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 229:18] - assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 229:18] - assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 229:18] - assign lsu_io_lsu_dma_dma_mem_tag = dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 229:18] - assign lsu_io_lsu_pic_picm_rd_data = pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 276:28] - assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 221:18] - assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 221:18] - assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 173:18] - assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 173:18] - assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 173:18] - assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 304:11] - assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 304:11] - assign lsu_io_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar.scala 307:14 quasar.scala 428:25] - assign lsu_io_axi_w_ready = io_lsu_axi_w_ready; // @[quasar.scala 307:14 quasar.scala 429:24] - assign lsu_io_axi_b_valid = io_lsu_axi_b_valid; // @[quasar.scala 307:14 quasar.scala 430:24] - assign lsu_io_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar.scala 307:14 quasar.scala 431:28] - assign lsu_io_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar.scala 307:14 quasar.scala 432:26] - assign lsu_io_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar.scala 307:14 quasar.scala 433:25] - assign lsu_io_axi_r_valid = io_lsu_axi_r_valid; // @[quasar.scala 307:14 quasar.scala 434:24] - assign lsu_io_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar.scala 307:14 quasar.scala 435:26] - assign lsu_io_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar.scala 307:14 quasar.scala 436:28] - assign lsu_io_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar.scala 307:14 quasar.scala 437:28] - assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 217:32] - assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 218:35] - assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 219:29] - assign lsu_io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 220:35] - assign lsu_io_dec_lsu_offset_d = dec_io_dec_lsu_offset_d; // @[quasar.scala 222:27] - assign lsu_io_lsu_p_valid = dec_io_lsu_p_valid; // @[quasar.scala 223:16] - assign lsu_io_lsu_p_bits_fast_int = dec_io_lsu_p_bits_fast_int; // @[quasar.scala 223:16] - assign lsu_io_lsu_p_bits_by = dec_io_lsu_p_bits_by; // @[quasar.scala 223:16] - assign lsu_io_lsu_p_bits_half = dec_io_lsu_p_bits_half; // @[quasar.scala 223:16] - assign lsu_io_lsu_p_bits_word = dec_io_lsu_p_bits_word; // @[quasar.scala 223:16] - assign lsu_io_lsu_p_bits_load = dec_io_lsu_p_bits_load; // @[quasar.scala 223:16] - assign lsu_io_lsu_p_bits_store = dec_io_lsu_p_bits_store; // @[quasar.scala 223:16] - assign lsu_io_lsu_p_bits_unsign = dec_io_lsu_p_bits_unsign; // @[quasar.scala 223:16] - assign lsu_io_lsu_p_bits_store_data_bypass_d = dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 223:16] - assign lsu_io_lsu_p_bits_load_ldst_bypass_d = dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 223:16] - assign lsu_io_trigger_pkt_any_0_select = dec_io_trigger_pkt_any_0_select; // @[quasar.scala 226:26] - assign lsu_io_trigger_pkt_any_0_match_pkt = dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 226:26] - assign lsu_io_trigger_pkt_any_0_store = dec_io_trigger_pkt_any_0_store; // @[quasar.scala 226:26] - assign lsu_io_trigger_pkt_any_0_load = dec_io_trigger_pkt_any_0_load; // @[quasar.scala 226:26] - assign lsu_io_trigger_pkt_any_0_tdata2 = dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 226:26] - assign lsu_io_trigger_pkt_any_1_select = dec_io_trigger_pkt_any_1_select; // @[quasar.scala 226:26] - assign lsu_io_trigger_pkt_any_1_match_pkt = dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 226:26] - assign lsu_io_trigger_pkt_any_1_store = dec_io_trigger_pkt_any_1_store; // @[quasar.scala 226:26] - assign lsu_io_trigger_pkt_any_1_load = dec_io_trigger_pkt_any_1_load; // @[quasar.scala 226:26] - assign lsu_io_trigger_pkt_any_1_tdata2 = dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 226:26] - assign lsu_io_trigger_pkt_any_2_select = dec_io_trigger_pkt_any_2_select; // @[quasar.scala 226:26] - assign lsu_io_trigger_pkt_any_2_match_pkt = dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 226:26] - assign lsu_io_trigger_pkt_any_2_store = dec_io_trigger_pkt_any_2_store; // @[quasar.scala 226:26] - assign lsu_io_trigger_pkt_any_2_load = dec_io_trigger_pkt_any_2_load; // @[quasar.scala 226:26] - assign lsu_io_trigger_pkt_any_2_tdata2 = dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 226:26] - assign lsu_io_trigger_pkt_any_3_select = dec_io_trigger_pkt_any_3_select; // @[quasar.scala 226:26] - assign lsu_io_trigger_pkt_any_3_match_pkt = dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 226:26] - assign lsu_io_trigger_pkt_any_3_store = dec_io_trigger_pkt_any_3_store; // @[quasar.scala 226:26] - assign lsu_io_trigger_pkt_any_3_load = dec_io_trigger_pkt_any_3_load; // @[quasar.scala 226:26] - assign lsu_io_trigger_pkt_any_3_tdata2 = dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 226:26] - assign lsu_io_dec_lsu_valid_raw_d = dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 224:30] - assign lsu_io_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 225:26] - assign lsu_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 228:25] - assign lsu_io_scan_mode = io_scan_mode; // @[quasar.scala 230:20] - assign lsu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 231:19] + assign lsu_reset = io_core_rst_l; // @[quasar.scala 202:13] + assign lsu_io_clk_override = dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 203:23] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_dccm_req = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_dccm_req; // @[quasar.scala 216:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_addr; // @[quasar.scala 216:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_sz = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_sz; // @[quasar.scala 216:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_write = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_write; // @[quasar.scala 216:18] + assign lsu_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_lsc_ctl_dma_mem_wdata; // @[quasar.scala 216:18] + assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 216:18] + assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 216:18] + assign lsu_io_lsu_dma_dma_mem_tag = dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 216:18] + assign lsu_io_lsu_pic_picm_rd_data = pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 262:28] + assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 208:18] + assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 208:18] + assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 167:18] + assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 167:18] + assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 283:11] + assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 283:11] + assign lsu_io_axi_aw_ready = axi4_to_ahb_io_axi_awready; // @[quasar.scala 286:14 quasar.scala 407:25] + assign lsu_io_axi_w_ready = axi4_to_ahb_io_axi_wready; // @[quasar.scala 286:14 quasar.scala 408:24] + assign lsu_io_axi_b_valid = axi4_to_ahb_io_axi_bvalid; // @[quasar.scala 286:14 quasar.scala 409:24] + assign lsu_io_axi_b_bits_resp = axi4_to_ahb_io_axi_bresp; // @[quasar.scala 286:14 quasar.scala 410:28] + assign lsu_io_axi_b_bits_id = {{2'd0}, axi4_to_ahb_io_axi_bid}; // @[quasar.scala 286:14 quasar.scala 411:26] + assign lsu_io_axi_ar_ready = axi4_to_ahb_io_axi_arready; // @[quasar.scala 286:14 quasar.scala 412:25] + assign lsu_io_axi_r_valid = axi4_to_ahb_io_axi_rvalid; // @[quasar.scala 286:14 quasar.scala 413:24] + assign lsu_io_axi_r_bits_id = {{2'd0}, axi4_to_ahb_io_axi_rid}; // @[quasar.scala 286:14 quasar.scala 414:26] + assign lsu_io_axi_r_bits_data = axi4_to_ahb_io_axi_rdata; // @[quasar.scala 286:14 quasar.scala 415:28] + assign lsu_io_axi_r_bits_resp = axi4_to_ahb_io_axi_rresp; // @[quasar.scala 286:14 quasar.scala 416:28] + assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 204:32] + assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 205:35] + assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 206:29] + assign lsu_io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 207:35] + assign lsu_io_dec_lsu_offset_d = dec_io_dec_lsu_offset_d; // @[quasar.scala 209:27] + assign lsu_io_lsu_p_valid = dec_io_lsu_p_valid; // @[quasar.scala 210:16] + assign lsu_io_lsu_p_bits_fast_int = dec_io_lsu_p_bits_fast_int; // @[quasar.scala 210:16] + assign lsu_io_lsu_p_bits_by = dec_io_lsu_p_bits_by; // @[quasar.scala 210:16] + assign lsu_io_lsu_p_bits_half = dec_io_lsu_p_bits_half; // @[quasar.scala 210:16] + assign lsu_io_lsu_p_bits_word = dec_io_lsu_p_bits_word; // @[quasar.scala 210:16] + assign lsu_io_lsu_p_bits_load = dec_io_lsu_p_bits_load; // @[quasar.scala 210:16] + assign lsu_io_lsu_p_bits_store = dec_io_lsu_p_bits_store; // @[quasar.scala 210:16] + assign lsu_io_lsu_p_bits_unsign = dec_io_lsu_p_bits_unsign; // @[quasar.scala 210:16] + assign lsu_io_lsu_p_bits_store_data_bypass_d = dec_io_lsu_p_bits_store_data_bypass_d; // @[quasar.scala 210:16] + assign lsu_io_lsu_p_bits_load_ldst_bypass_d = dec_io_lsu_p_bits_load_ldst_bypass_d; // @[quasar.scala 210:16] + assign lsu_io_trigger_pkt_any_0_select = dec_io_trigger_pkt_any_0_select; // @[quasar.scala 213:26] + assign lsu_io_trigger_pkt_any_0_match_pkt = dec_io_trigger_pkt_any_0_match_pkt; // @[quasar.scala 213:26] + assign lsu_io_trigger_pkt_any_0_store = dec_io_trigger_pkt_any_0_store; // @[quasar.scala 213:26] + assign lsu_io_trigger_pkt_any_0_load = dec_io_trigger_pkt_any_0_load; // @[quasar.scala 213:26] + assign lsu_io_trigger_pkt_any_0_tdata2 = dec_io_trigger_pkt_any_0_tdata2; // @[quasar.scala 213:26] + assign lsu_io_trigger_pkt_any_1_select = dec_io_trigger_pkt_any_1_select; // @[quasar.scala 213:26] + assign lsu_io_trigger_pkt_any_1_match_pkt = dec_io_trigger_pkt_any_1_match_pkt; // @[quasar.scala 213:26] + assign lsu_io_trigger_pkt_any_1_store = dec_io_trigger_pkt_any_1_store; // @[quasar.scala 213:26] + assign lsu_io_trigger_pkt_any_1_load = dec_io_trigger_pkt_any_1_load; // @[quasar.scala 213:26] + assign lsu_io_trigger_pkt_any_1_tdata2 = dec_io_trigger_pkt_any_1_tdata2; // @[quasar.scala 213:26] + assign lsu_io_trigger_pkt_any_2_select = dec_io_trigger_pkt_any_2_select; // @[quasar.scala 213:26] + assign lsu_io_trigger_pkt_any_2_match_pkt = dec_io_trigger_pkt_any_2_match_pkt; // @[quasar.scala 213:26] + assign lsu_io_trigger_pkt_any_2_store = dec_io_trigger_pkt_any_2_store; // @[quasar.scala 213:26] + assign lsu_io_trigger_pkt_any_2_load = dec_io_trigger_pkt_any_2_load; // @[quasar.scala 213:26] + assign lsu_io_trigger_pkt_any_2_tdata2 = dec_io_trigger_pkt_any_2_tdata2; // @[quasar.scala 213:26] + assign lsu_io_trigger_pkt_any_3_select = dec_io_trigger_pkt_any_3_select; // @[quasar.scala 213:26] + assign lsu_io_trigger_pkt_any_3_match_pkt = dec_io_trigger_pkt_any_3_match_pkt; // @[quasar.scala 213:26] + assign lsu_io_trigger_pkt_any_3_store = dec_io_trigger_pkt_any_3_store; // @[quasar.scala 213:26] + assign lsu_io_trigger_pkt_any_3_load = dec_io_trigger_pkt_any_3_load; // @[quasar.scala 213:26] + assign lsu_io_trigger_pkt_any_3_tdata2 = dec_io_trigger_pkt_any_3_tdata2; // @[quasar.scala 213:26] + assign lsu_io_dec_lsu_valid_raw_d = dec_io_dec_lsu_valid_raw_d; // @[quasar.scala 211:30] + assign lsu_io_dec_tlu_mrac_ff = dec_io_ifu_dec_dec_ifc_dec_tlu_mrac_ff; // @[quasar.scala 212:26] + assign lsu_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 215:25] + assign lsu_io_scan_mode = io_scan_mode; // @[quasar.scala 217:20] + assign lsu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 218:19] assign pic_ctrl_inst_clock = clock; - assign pic_ctrl_inst_reset = io_core_rst_l; // @[quasar.scala 271:23] - assign pic_ctrl_inst_io_scan_mode = io_scan_mode; // @[quasar.scala 270:30] - assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 272:29] - assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 273:31] - assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 274:33] - assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[quasar.scala 275:34] - assign pic_ctrl_inst_io_lsu_pic_picm_wren = lsu_io_lsu_pic_picm_wren; // @[quasar.scala 276:28] - assign pic_ctrl_inst_io_lsu_pic_picm_rden = lsu_io_lsu_pic_picm_rden; // @[quasar.scala 276:28] - assign pic_ctrl_inst_io_lsu_pic_picm_mken = lsu_io_lsu_pic_picm_mken; // @[quasar.scala 276:28] - assign pic_ctrl_inst_io_lsu_pic_picm_rdaddr = lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 276:28] - assign pic_ctrl_inst_io_lsu_pic_picm_wraddr = lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 276:28] - assign pic_ctrl_inst_io_lsu_pic_picm_wr_data = lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 276:28] - assign pic_ctrl_inst_io_meicurpl = dec_io_dec_tlu_meicurpl; // @[quasar.scala 277:29] - assign pic_ctrl_inst_io_meipt = dec_io_dec_tlu_meipt; // @[quasar.scala 278:26] + assign pic_ctrl_inst_reset = io_core_rst_l; // @[quasar.scala 257:23] + assign pic_ctrl_inst_io_scan_mode = io_scan_mode; // @[quasar.scala 256:30] + assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 258:29] + assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 259:31] + assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 260:33] + assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[quasar.scala 261:34] + assign pic_ctrl_inst_io_lsu_pic_picm_wren = lsu_io_lsu_pic_picm_wren; // @[quasar.scala 262:28] + assign pic_ctrl_inst_io_lsu_pic_picm_rden = lsu_io_lsu_pic_picm_rden; // @[quasar.scala 262:28] + assign pic_ctrl_inst_io_lsu_pic_picm_mken = lsu_io_lsu_pic_picm_mken; // @[quasar.scala 262:28] + assign pic_ctrl_inst_io_lsu_pic_picm_rdaddr = lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 262:28] + assign pic_ctrl_inst_io_lsu_pic_picm_wraddr = lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 262:28] + assign pic_ctrl_inst_io_lsu_pic_picm_wr_data = lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 262:28] + assign pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl = dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 263:28] + assign pic_ctrl_inst_io_dec_pic_dec_tlu_meipt = dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 263:28] assign dma_ctrl_clock = clock; - assign dma_ctrl_reset = io_core_rst_l; // @[quasar.scala 254:18] - assign dma_ctrl_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 255:24] - assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 256:30] - assign dma_ctrl_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 257:28] - assign dma_ctrl_io_scan_mode = io_scan_mode; // @[quasar.scala 258:25] - assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[quasar.scala 261:28] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 259:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write = dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 259:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type = dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 259:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 259:23] - assign dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 259:23] - assign dma_ctrl_io_dbg_dma_io_dbg_dma_bubble = dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 260:26] - assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[quasar.scala 262:31] - assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[quasar.scala 267:34] - assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 263:29] - assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 264:30] - assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 265:26] - assign dma_ctrl_io_dec_tlu_dma_qos_prty = dec_io_dec_tlu_dma_qos_prty; // @[quasar.scala 266:36] - assign dma_ctrl_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar.scala 311:14 quasar.scala 459:34] - assign dma_ctrl_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar.scala 311:14 quasar.scala 460:36] - assign dma_ctrl_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar.scala 311:14 quasar.scala 461:38] - assign dma_ctrl_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar.scala 311:14 quasar.scala 462:38] - assign dma_ctrl_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar.scala 311:14 quasar.scala 463:33] - assign dma_ctrl_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar.scala 311:14 quasar.scala 464:37] - assign dma_ctrl_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar.scala 311:14 quasar.scala 465:37] - assign dma_ctrl_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar.scala 311:14 quasar.scala 466:33] - assign dma_ctrl_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar.scala 311:14 quasar.scala 467:34] - assign dma_ctrl_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar.scala 311:14 quasar.scala 468:36] - assign dma_ctrl_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar.scala 311:14 quasar.scala 469:38] - assign dma_ctrl_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar.scala 311:14 quasar.scala 470:38] - assign dma_ctrl_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar.scala 311:14 quasar.scala 471:33] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 229:18] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 229:18] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 229:18] - assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 229:18] - assign dma_ctrl_io_lsu_dma_dccm_ready = lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 229:18] + assign dma_ctrl_reset = io_core_rst_l; // @[quasar.scala 241:18] + assign dma_ctrl_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 242:24] + assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 243:30] + assign dma_ctrl_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 244:28] + assign dma_ctrl_io_scan_mode = io_scan_mode; // @[quasar.scala 245:25] + assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[quasar.scala 248:28] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 246:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write = dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 246:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type = dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 246:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 246:23] + assign dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 246:23] + assign dma_ctrl_io_dbg_dma_io_dbg_dma_bubble = dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 247:26] + assign dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 170:18] + assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[quasar.scala 249:31] + assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[quasar.scala 253:34] + assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 250:29] + assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 251:30] + assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 252:26] + assign dma_ctrl_io_dma_axi_aw_valid = ahb_to_axi4_io_axi_awvalid; // @[quasar.scala 290:14 quasar.scala 438:34] + assign dma_ctrl_io_dma_axi_aw_bits_addr = ahb_to_axi4_io_axi_awaddr; // @[quasar.scala 290:14 quasar.scala 440:38] + assign dma_ctrl_io_dma_axi_aw_bits_size = ahb_to_axi4_io_axi_awsize; // @[quasar.scala 290:14 quasar.scala 441:38] + assign dma_ctrl_io_dma_axi_w_valid = ahb_to_axi4_io_axi_wvalid; // @[quasar.scala 290:14 quasar.scala 442:33] + assign dma_ctrl_io_dma_axi_w_bits_data = ahb_to_axi4_io_axi_wdata; // @[quasar.scala 290:14 quasar.scala 443:37] + assign dma_ctrl_io_dma_axi_w_bits_strb = ahb_to_axi4_io_axi_wstrb; // @[quasar.scala 290:14 quasar.scala 444:37] + assign dma_ctrl_io_dma_axi_ar_valid = ahb_to_axi4_io_axi_arvalid; // @[quasar.scala 290:14 quasar.scala 446:34] + assign dma_ctrl_io_dma_axi_ar_bits_addr = ahb_to_axi4_io_axi_araddr; // @[quasar.scala 290:14 quasar.scala 448:38] + assign dma_ctrl_io_dma_axi_ar_bits_size = ahb_to_axi4_io_axi_arsize; // @[quasar.scala 290:14 quasar.scala 449:38] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 216:18] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 216:18] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 216:18] + assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata; // @[quasar.scala 216:18] + assign dma_ctrl_io_lsu_dma_dccm_ready = lsu_io_lsu_dma_dccm_ready; // @[quasar.scala 216:18] assign rvclkhdr_io_clk = clock; // @[lib.scala 328:17] assign rvclkhdr_io_en = 1'h1; // @[lib.scala 329:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 330:23] @@ -83503,48 +83541,59 @@ module quasar( assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 330:23] assign axi4_to_ahb_clock = clock; assign axi4_to_ahb_reset = reset; - assign axi4_to_ahb_io_scan_mode = io_scan_mode; // @[quasar.scala 320:34] - assign axi4_to_ahb_io_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 321:35] - assign axi4_to_ahb_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 322:37] - assign axi4_to_ahb_io_axi_awvalid = io_lsu_axi_aw_valid; // @[quasar.scala 319:36] - assign axi4_to_ahb_io_axi_wvalid = io_lsu_axi_w_valid; // @[quasar.scala 328:35] - assign axi4_to_ahb_io_axi_bready = io_lsu_axi_b_ready; // @[quasar.scala 332:35] - assign axi4_to_ahb_io_axi_arvalid = io_lsu_axi_ar_valid; // @[quasar.scala 334:36] - assign axi4_to_ahb_io_axi_rready = io_lsu_axi_r_ready; // @[quasar.scala 340:35] + assign axi4_to_ahb_io_scan_mode = io_scan_mode; // @[quasar.scala 299:34] + assign axi4_to_ahb_io_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 300:35] + assign axi4_to_ahb_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 301:37] + assign axi4_to_ahb_io_axi_awvalid = io_lsu_axi_aw_valid; // @[quasar.scala 298:36] + assign axi4_to_ahb_io_axi_awid = io_lsu_axi_aw_bits_id[0]; // @[quasar.scala 302:33] + assign axi4_to_ahb_io_axi_wvalid = io_lsu_axi_w_valid; // @[quasar.scala 307:35] + assign axi4_to_ahb_io_axi_wdata = io_lsu_axi_w_bits_data; // @[quasar.scala 308:34] + assign axi4_to_ahb_io_axi_bready = io_lsu_axi_b_ready; // @[quasar.scala 311:35] + assign axi4_to_ahb_io_axi_arvalid = io_lsu_axi_ar_valid; // @[quasar.scala 313:36] + assign axi4_to_ahb_io_axi_arid = io_lsu_axi_ar_bits_id[0]; // @[quasar.scala 314:33] + assign axi4_to_ahb_io_axi_rready = io_lsu_axi_r_ready; // @[quasar.scala 319:35] assign axi4_to_ahb_1_clock = clock; assign axi4_to_ahb_1_reset = reset; - assign axi4_to_ahb_1_io_scan_mode = io_scan_mode; // @[quasar.scala 347:34] - assign axi4_to_ahb_1_io_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 348:35] - assign axi4_to_ahb_1_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 349:37] - assign axi4_to_ahb_1_io_axi_awvalid = io_ifu_axi_aw_valid; // @[quasar.scala 346:36] - assign axi4_to_ahb_1_io_axi_wvalid = io_ifu_axi_w_valid; // @[quasar.scala 355:35] - assign axi4_to_ahb_1_io_axi_bready = io_ifu_axi_b_ready; // @[quasar.scala 359:35] - assign axi4_to_ahb_1_io_axi_arvalid = io_ifu_axi_ar_valid; // @[quasar.scala 361:36] - assign axi4_to_ahb_1_io_axi_rready = io_ifu_axi_r_ready; // @[quasar.scala 367:35] + assign axi4_to_ahb_1_io_scan_mode = io_scan_mode; // @[quasar.scala 326:34] + assign axi4_to_ahb_1_io_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 327:35] + assign axi4_to_ahb_1_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 328:37] + assign axi4_to_ahb_1_io_axi_awvalid = io_ifu_axi_aw_valid; // @[quasar.scala 325:36] + assign axi4_to_ahb_1_io_axi_awid = io_ifu_axi_aw_bits_id[0]; // @[quasar.scala 329:33] + assign axi4_to_ahb_1_io_axi_wvalid = io_ifu_axi_w_valid; // @[quasar.scala 334:35] + assign axi4_to_ahb_1_io_axi_wdata = io_ifu_axi_w_bits_data; // @[quasar.scala 335:34] + assign axi4_to_ahb_1_io_axi_bready = io_ifu_axi_b_ready; // @[quasar.scala 338:35] + assign axi4_to_ahb_1_io_axi_arvalid = io_ifu_axi_ar_valid; // @[quasar.scala 340:36] + assign axi4_to_ahb_1_io_axi_arid = io_ifu_axi_ar_bits_id[0]; // @[quasar.scala 341:33] + assign axi4_to_ahb_1_io_axi_rready = io_ifu_axi_r_ready; // @[quasar.scala 346:35] assign axi4_to_ahb_2_clock = clock; assign axi4_to_ahb_2_reset = reset; - assign axi4_to_ahb_2_io_scan_mode = io_scan_mode; // @[quasar.scala 375:33] - assign axi4_to_ahb_2_io_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 376:34] - assign axi4_to_ahb_2_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 377:36] - assign axi4_to_ahb_2_io_axi_awvalid = io_sb_axi_aw_valid; // @[quasar.scala 374:35] - assign axi4_to_ahb_2_io_axi_wvalid = io_sb_axi_w_valid; // @[quasar.scala 383:34] - assign axi4_to_ahb_2_io_axi_bready = io_sb_axi_b_ready; // @[quasar.scala 387:34] - assign axi4_to_ahb_2_io_axi_arvalid = io_sb_axi_ar_valid; // @[quasar.scala 389:35] - assign axi4_to_ahb_2_io_axi_rready = io_sb_axi_r_ready; // @[quasar.scala 395:34] + assign axi4_to_ahb_2_io_scan_mode = io_scan_mode; // @[quasar.scala 354:33] + assign axi4_to_ahb_2_io_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 355:34] + assign axi4_to_ahb_2_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 356:36] + assign axi4_to_ahb_2_io_axi_awvalid = io_sb_axi_aw_valid; // @[quasar.scala 353:35] + assign axi4_to_ahb_2_io_axi_awid = io_sb_axi_aw_bits_id; // @[quasar.scala 357:32] + assign axi4_to_ahb_2_io_axi_wvalid = io_sb_axi_w_valid; // @[quasar.scala 362:34] + assign axi4_to_ahb_2_io_axi_wdata = io_sb_axi_w_bits_data; // @[quasar.scala 363:33] + assign axi4_to_ahb_2_io_axi_bready = io_sb_axi_b_ready; // @[quasar.scala 366:34] + assign axi4_to_ahb_2_io_axi_arvalid = io_sb_axi_ar_valid; // @[quasar.scala 368:35] + assign axi4_to_ahb_2_io_axi_arid = io_sb_axi_ar_bits_id; // @[quasar.scala 369:32] + assign axi4_to_ahb_2_io_axi_rready = io_sb_axi_r_ready; // @[quasar.scala 374:34] assign ahb_to_axi4_clock = clock; assign ahb_to_axi4_reset = reset; - assign ahb_to_axi4_io_scan_mode = io_scan_mode; // @[quasar.scala 401:34] - assign ahb_to_axi4_io_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 402:35] - assign ahb_to_axi4_io_axi_awready = io_dma_axi_aw_ready; // @[quasar.scala 404:36] - assign ahb_to_axi4_io_axi_arready = io_dma_axi_ar_ready; // @[quasar.scala 411:36] - assign ahb_to_axi4_io_axi_rvalid = io_dma_axi_ar_valid; // @[quasar.scala 412:35] - assign ahb_to_axi4_io_axi_rresp = io_dma_axi_r_bits_resp; // @[quasar.scala 415:34] - assign ahb_to_axi4_io_ahb_haddr = io_dma_haddr; // @[quasar.scala 418:34] - assign ahb_to_axi4_io_ahb_hsize = io_dma_hsize; // @[quasar.scala 422:34] - assign ahb_to_axi4_io_ahb_htrans = io_dma_htrans; // @[quasar.scala 423:35] - assign ahb_to_axi4_io_ahb_hwrite = io_dma_hwrite; // @[quasar.scala 424:35] - assign ahb_to_axi4_io_ahb_hsel = io_dma_hsel; // @[quasar.scala 426:33] - assign ahb_to_axi4_io_ahb_hreadyin = io_dma_hreadyin; // @[quasar.scala 427:37] + assign ahb_to_axi4_io_scan_mode = io_scan_mode; // @[quasar.scala 380:34] + assign ahb_to_axi4_io_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 381:35] + assign ahb_to_axi4_io_axi_awready = io_dma_axi_aw_ready; // @[quasar.scala 383:36] + assign ahb_to_axi4_io_axi_arready = io_dma_axi_ar_ready; // @[quasar.scala 390:36] + assign ahb_to_axi4_io_axi_rvalid = io_dma_axi_ar_valid; // @[quasar.scala 391:35] + assign ahb_to_axi4_io_axi_rdata = io_dma_axi_r_bits_data; // @[quasar.scala 393:34] + assign ahb_to_axi4_io_axi_rresp = io_dma_axi_r_bits_resp; // @[quasar.scala 394:34] + assign ahb_to_axi4_io_ahb_haddr = io_dma_haddr; // @[quasar.scala 397:34] + assign ahb_to_axi4_io_ahb_hsize = io_dma_hsize; // @[quasar.scala 401:34] + assign ahb_to_axi4_io_ahb_htrans = io_dma_htrans; // @[quasar.scala 402:35] + assign ahb_to_axi4_io_ahb_hwrite = io_dma_hwrite; // @[quasar.scala 403:35] + assign ahb_to_axi4_io_ahb_hwdata = io_dma_hwdata; // @[quasar.scala 404:35] + assign ahb_to_axi4_io_ahb_hsel = io_dma_hsel; // @[quasar.scala 405:33] + assign ahb_to_axi4_io_ahb_hreadyin = io_dma_hreadyin; // @[quasar.scala 406:37] endmodule module quasar_wrapper( input clock, @@ -83554,13 +83603,6 @@ module quasar_wrapper( input io_nmi_int, input [30:0] io_nmi_vec, input [30:0] io_jtag_id, - output [31:0] io_trace_rv_i_insn_ip, - output [31:0] io_trace_rv_i_address_ip, - output [1:0] io_trace_rv_i_valid_ip, - output [1:0] io_trace_rv_i_exception_ip, - output [4:0] io_trace_rv_i_ecause_ip, - output [1:0] io_trace_rv_i_interrupt_ip, - output [31:0] io_trace_rv_i_tval_ip, input io_lsu_axi_aw_ready, output io_lsu_axi_aw_valid, output [2:0] io_lsu_axi_aw_bits_id, @@ -83760,245 +83802,223 @@ module quasar_wrapper( output io_o_debug_mode_status, output io_o_cpu_run_ack, input io_mbist_mode, + output [1:0] io_rv_trace_pkt_rv_i_valid_ip, + output [31:0] io_rv_trace_pkt_rv_i_insn_ip, + output [31:0] io_rv_trace_pkt_rv_i_address_ip, + output [1:0] io_rv_trace_pkt_rv_i_exception_ip, + output [4:0] io_rv_trace_pkt_rv_i_ecause_ip, + output [1:0] io_rv_trace_pkt_rv_i_interrupt_ip, + output [31:0] io_rv_trace_pkt_rv_i_tval_ip, input io_scan_mode ); - wire mem_clk; // @[quasar_wrapper.scala 85:19] - wire mem_rst_l; // @[quasar_wrapper.scala 85:19] - wire mem_dccm_clk_override; // @[quasar_wrapper.scala 85:19] - wire mem_icm_clk_override; // @[quasar_wrapper.scala 85:19] - wire mem_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 85:19] - wire mem_dccm_wren; // @[quasar_wrapper.scala 85:19] - wire mem_dccm_rden; // @[quasar_wrapper.scala 85:19] - wire [15:0] mem_dccm_wr_addr_lo; // @[quasar_wrapper.scala 85:19] - wire [15:0] mem_dccm_wr_addr_hi; // @[quasar_wrapper.scala 85:19] - wire [15:0] mem_dccm_rd_addr_lo; // @[quasar_wrapper.scala 85:19] - wire [15:0] mem_dccm_rd_addr_hi; // @[quasar_wrapper.scala 85:19] - wire [38:0] mem_dccm_wr_data_lo; // @[quasar_wrapper.scala 85:19] - wire [38:0] mem_dccm_wr_data_hi; // @[quasar_wrapper.scala 85:19] - wire [38:0] mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 85:19] - wire [38:0] mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 85:19] - wire [14:0] mem_iccm_rw_addr; // @[quasar_wrapper.scala 85:19] - wire mem_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 85:19] - wire mem_iccm_correction_state; // @[quasar_wrapper.scala 85:19] - wire mem_iccm_wren; // @[quasar_wrapper.scala 85:19] - wire mem_iccm_rden; // @[quasar_wrapper.scala 85:19] - wire [2:0] mem_iccm_wr_size; // @[quasar_wrapper.scala 85:19] - wire [77:0] mem_iccm_wr_data; // @[quasar_wrapper.scala 85:19] - wire [63:0] mem_iccm_rd_data; // @[quasar_wrapper.scala 85:19] - wire [77:0] mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 85:19] - wire [30:0] mem_ic_rw_addr; // @[quasar_wrapper.scala 85:19] - wire [1:0] mem_ic_tag_valid; // @[quasar_wrapper.scala 85:19] - wire [1:0] mem_ic_wr_en; // @[quasar_wrapper.scala 85:19] - wire mem_ic_rd_en; // @[quasar_wrapper.scala 85:19] - wire [70:0] mem_ic_wr_data_0; // @[quasar_wrapper.scala 85:19] - wire [70:0] mem_ic_wr_data_1; // @[quasar_wrapper.scala 85:19] - wire [70:0] mem_ic_debug_wr_data; // @[quasar_wrapper.scala 85:19] - wire [9:0] mem_ic_debug_addr; // @[quasar_wrapper.scala 85:19] - wire [63:0] mem_ic_rd_data; // @[quasar_wrapper.scala 85:19] - wire [70:0] mem_ic_debug_rd_data; // @[quasar_wrapper.scala 85:19] - wire [25:0] mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 85:19] - wire [1:0] mem_ic_eccerr; // @[quasar_wrapper.scala 85:19] - wire [1:0] mem_ic_parerr; // @[quasar_wrapper.scala 85:19] - wire [1:0] mem_ic_rd_hit; // @[quasar_wrapper.scala 85:19] - wire mem_ic_tag_perr; // @[quasar_wrapper.scala 85:19] - wire mem_ic_debug_rd_en; // @[quasar_wrapper.scala 85:19] - wire mem_ic_debug_wr_en; // @[quasar_wrapper.scala 85:19] - wire mem_ic_debug_tag_array; // @[quasar_wrapper.scala 85:19] - wire [1:0] mem_ic_debug_way; // @[quasar_wrapper.scala 85:19] - wire [63:0] mem_ic_premux_data; // @[quasar_wrapper.scala 85:19] - wire mem_ic_sel_premux_data; // @[quasar_wrapper.scala 85:19] - wire mem_scan_mode; // @[quasar_wrapper.scala 85:19] - wire dmi_wrapper_trst_n; // @[quasar_wrapper.scala 86:27] - wire dmi_wrapper_tck; // @[quasar_wrapper.scala 86:27] - wire dmi_wrapper_tms; // @[quasar_wrapper.scala 86:27] - wire dmi_wrapper_tdi; // @[quasar_wrapper.scala 86:27] - wire dmi_wrapper_tdo; // @[quasar_wrapper.scala 86:27] - wire dmi_wrapper_tdoEnable; // @[quasar_wrapper.scala 86:27] - wire dmi_wrapper_core_rst_n; // @[quasar_wrapper.scala 86:27] - wire dmi_wrapper_core_clk; // @[quasar_wrapper.scala 86:27] - wire [30:0] dmi_wrapper_jtag_id; // @[quasar_wrapper.scala 86:27] - wire [31:0] dmi_wrapper_rd_data; // @[quasar_wrapper.scala 86:27] - wire [31:0] dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 86:27] - wire [6:0] dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 86:27] - wire dmi_wrapper_reg_en; // @[quasar_wrapper.scala 86:27] - wire dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 86:27] - wire dmi_wrapper_dmi_hard_reset; // @[quasar_wrapper.scala 86:27] - wire swerv_clock; // @[quasar_wrapper.scala 87:21] - wire swerv_reset; // @[quasar_wrapper.scala 87:21] - wire swerv_io_lsu_axi_aw_ready; // @[quasar_wrapper.scala 87:21] - wire swerv_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 87:21] - wire [2:0] swerv_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 87:21] - wire [31:0] swerv_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 87:21] - wire [3:0] swerv_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 87:21] - wire [2:0] swerv_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 87:21] - wire [3:0] swerv_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 87:21] - wire swerv_io_lsu_axi_w_ready; // @[quasar_wrapper.scala 87:21] - wire swerv_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 87:21] - wire [63:0] swerv_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 87:21] - wire [7:0] swerv_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 87:21] - wire swerv_io_lsu_axi_b_ready; // @[quasar_wrapper.scala 87:21] - wire swerv_io_lsu_axi_b_valid; // @[quasar_wrapper.scala 87:21] - wire [1:0] swerv_io_lsu_axi_b_bits_resp; // @[quasar_wrapper.scala 87:21] - wire [2:0] swerv_io_lsu_axi_b_bits_id; // @[quasar_wrapper.scala 87:21] - wire swerv_io_lsu_axi_ar_ready; // @[quasar_wrapper.scala 87:21] - wire swerv_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 87:21] - wire [2:0] swerv_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 87:21] - wire [31:0] swerv_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 87:21] - wire [3:0] swerv_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 87:21] - wire [2:0] swerv_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 87:21] - wire [3:0] swerv_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 87:21] - wire swerv_io_lsu_axi_r_ready; // @[quasar_wrapper.scala 87:21] - wire swerv_io_lsu_axi_r_valid; // @[quasar_wrapper.scala 87:21] - wire [2:0] swerv_io_lsu_axi_r_bits_id; // @[quasar_wrapper.scala 87:21] - wire [63:0] swerv_io_lsu_axi_r_bits_data; // @[quasar_wrapper.scala 87:21] - wire [1:0] swerv_io_lsu_axi_r_bits_resp; // @[quasar_wrapper.scala 87:21] - wire swerv_io_ifu_axi_aw_valid; // @[quasar_wrapper.scala 87:21] - wire swerv_io_ifu_axi_w_valid; // @[quasar_wrapper.scala 87:21] - wire swerv_io_ifu_axi_b_ready; // @[quasar_wrapper.scala 87:21] - wire swerv_io_ifu_axi_ar_ready; // @[quasar_wrapper.scala 87:21] - wire swerv_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 87:21] - wire [2:0] swerv_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 87:21] - wire [31:0] swerv_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 87:21] - wire [3:0] swerv_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 87:21] - wire swerv_io_ifu_axi_r_ready; // @[quasar_wrapper.scala 87:21] - wire swerv_io_ifu_axi_r_valid; // @[quasar_wrapper.scala 87:21] - wire [2:0] swerv_io_ifu_axi_r_bits_id; // @[quasar_wrapper.scala 87:21] - wire [63:0] swerv_io_ifu_axi_r_bits_data; // @[quasar_wrapper.scala 87:21] - wire [1:0] swerv_io_ifu_axi_r_bits_resp; // @[quasar_wrapper.scala 87:21] - wire swerv_io_sb_axi_aw_ready; // @[quasar_wrapper.scala 87:21] - wire swerv_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 87:21] - wire [31:0] swerv_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 87:21] - wire [3:0] swerv_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 87:21] - wire [2:0] swerv_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 87:21] - wire swerv_io_sb_axi_w_ready; // @[quasar_wrapper.scala 87:21] - wire swerv_io_sb_axi_w_valid; // @[quasar_wrapper.scala 87:21] - wire [63:0] swerv_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 87:21] - wire [7:0] swerv_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 87:21] - wire swerv_io_sb_axi_b_ready; // @[quasar_wrapper.scala 87:21] - wire swerv_io_sb_axi_b_valid; // @[quasar_wrapper.scala 87:21] - wire [1:0] swerv_io_sb_axi_b_bits_resp; // @[quasar_wrapper.scala 87:21] - wire swerv_io_sb_axi_ar_ready; // @[quasar_wrapper.scala 87:21] - wire swerv_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 87:21] - wire [31:0] swerv_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 87:21] - wire [3:0] swerv_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 87:21] - wire [2:0] swerv_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 87:21] - wire swerv_io_sb_axi_r_ready; // @[quasar_wrapper.scala 87:21] - wire swerv_io_sb_axi_r_valid; // @[quasar_wrapper.scala 87:21] - wire [63:0] swerv_io_sb_axi_r_bits_data; // @[quasar_wrapper.scala 87:21] - wire [1:0] swerv_io_sb_axi_r_bits_resp; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dma_axi_aw_valid; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dma_axi_aw_bits_id; // @[quasar_wrapper.scala 87:21] - wire [31:0] swerv_io_dma_axi_aw_bits_addr; // @[quasar_wrapper.scala 87:21] - wire [2:0] swerv_io_dma_axi_aw_bits_size; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dma_axi_w_ready; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dma_axi_w_valid; // @[quasar_wrapper.scala 87:21] - wire [63:0] swerv_io_dma_axi_w_bits_data; // @[quasar_wrapper.scala 87:21] - wire [7:0] swerv_io_dma_axi_w_bits_strb; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dma_axi_b_ready; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dma_axi_b_valid; // @[quasar_wrapper.scala 87:21] - wire [1:0] swerv_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dma_axi_ar_valid; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dma_axi_ar_bits_id; // @[quasar_wrapper.scala 87:21] - wire [31:0] swerv_io_dma_axi_ar_bits_addr; // @[quasar_wrapper.scala 87:21] - wire [2:0] swerv_io_dma_axi_ar_bits_size; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dma_axi_r_ready; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dma_axi_r_valid; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 87:21] - wire [63:0] swerv_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 87:21] - wire [1:0] swerv_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dbg_rst_l; // @[quasar_wrapper.scala 87:21] - wire [30:0] swerv_io_rst_vec; // @[quasar_wrapper.scala 87:21] - wire swerv_io_nmi_int; // @[quasar_wrapper.scala 87:21] - wire [30:0] swerv_io_nmi_vec; // @[quasar_wrapper.scala 87:21] - wire swerv_io_core_rst_l; // @[quasar_wrapper.scala 87:21] - wire [31:0] swerv_io_trace_rv_i_insn_ip; // @[quasar_wrapper.scala 87:21] - wire [31:0] swerv_io_trace_rv_i_address_ip; // @[quasar_wrapper.scala 87:21] - wire [1:0] swerv_io_trace_rv_i_valid_ip; // @[quasar_wrapper.scala 87:21] - wire [1:0] swerv_io_trace_rv_i_exception_ip; // @[quasar_wrapper.scala 87:21] - wire [4:0] swerv_io_trace_rv_i_ecause_ip; // @[quasar_wrapper.scala 87:21] - wire [1:0] swerv_io_trace_rv_i_interrupt_ip; // @[quasar_wrapper.scala 87:21] - wire [31:0] swerv_io_trace_rv_i_tval_ip; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dccm_clk_override; // @[quasar_wrapper.scala 87:21] - wire swerv_io_icm_clk_override; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 87:21] - wire swerv_io_i_cpu_halt_req; // @[quasar_wrapper.scala 87:21] - wire swerv_io_i_cpu_run_req; // @[quasar_wrapper.scala 87:21] - wire swerv_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 87:21] - wire swerv_io_o_cpu_halt_status; // @[quasar_wrapper.scala 87:21] - wire swerv_io_o_cpu_run_ack; // @[quasar_wrapper.scala 87:21] - wire swerv_io_o_debug_mode_status; // @[quasar_wrapper.scala 87:21] - wire [27:0] swerv_io_core_id; // @[quasar_wrapper.scala 87:21] - wire swerv_io_mpc_debug_halt_req; // @[quasar_wrapper.scala 87:21] - wire swerv_io_mpc_debug_run_req; // @[quasar_wrapper.scala 87:21] - wire swerv_io_mpc_reset_run_req; // @[quasar_wrapper.scala 87:21] - wire swerv_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 87:21] - wire swerv_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 87:21] - wire swerv_io_debug_brkpt_status; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dccm_wren; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dccm_rden; // @[quasar_wrapper.scala 87:21] - wire [15:0] swerv_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 87:21] - wire [15:0] swerv_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 87:21] - wire [15:0] swerv_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 87:21] - wire [15:0] swerv_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 87:21] - wire [38:0] swerv_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 87:21] - wire [38:0] swerv_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 87:21] - wire [38:0] swerv_io_dccm_rd_data_lo; // @[quasar_wrapper.scala 87:21] - wire [38:0] swerv_io_dccm_rd_data_hi; // @[quasar_wrapper.scala 87:21] - wire [30:0] swerv_io_ic_rw_addr; // @[quasar_wrapper.scala 87:21] - wire [1:0] swerv_io_ic_tag_valid; // @[quasar_wrapper.scala 87:21] - wire [1:0] swerv_io_ic_wr_en; // @[quasar_wrapper.scala 87:21] - wire swerv_io_ic_rd_en; // @[quasar_wrapper.scala 87:21] - wire [70:0] swerv_io_ic_wr_data_0; // @[quasar_wrapper.scala 87:21] - wire [70:0] swerv_io_ic_wr_data_1; // @[quasar_wrapper.scala 87:21] - wire [70:0] swerv_io_ic_debug_wr_data; // @[quasar_wrapper.scala 87:21] - wire [9:0] swerv_io_ic_debug_addr; // @[quasar_wrapper.scala 87:21] - wire [63:0] swerv_io_ic_rd_data; // @[quasar_wrapper.scala 87:21] - wire [70:0] swerv_io_ic_debug_rd_data; // @[quasar_wrapper.scala 87:21] - wire [25:0] swerv_io_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 87:21] - wire [1:0] swerv_io_ic_eccerr; // @[quasar_wrapper.scala 87:21] - wire [1:0] swerv_io_ic_rd_hit; // @[quasar_wrapper.scala 87:21] - wire swerv_io_ic_tag_perr; // @[quasar_wrapper.scala 87:21] - wire swerv_io_ic_debug_rd_en; // @[quasar_wrapper.scala 87:21] - wire swerv_io_ic_debug_wr_en; // @[quasar_wrapper.scala 87:21] - wire swerv_io_ic_debug_tag_array; // @[quasar_wrapper.scala 87:21] - wire [1:0] swerv_io_ic_debug_way; // @[quasar_wrapper.scala 87:21] - wire [63:0] swerv_io_ic_premux_data; // @[quasar_wrapper.scala 87:21] - wire swerv_io_ic_sel_premux_data; // @[quasar_wrapper.scala 87:21] - wire [14:0] swerv_io_iccm_rw_addr; // @[quasar_wrapper.scala 87:21] - wire swerv_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 87:21] - wire swerv_io_iccm_correction_state; // @[quasar_wrapper.scala 87:21] - wire swerv_io_iccm_wren; // @[quasar_wrapper.scala 87:21] - wire swerv_io_iccm_rden; // @[quasar_wrapper.scala 87:21] - wire [2:0] swerv_io_iccm_wr_size; // @[quasar_wrapper.scala 87:21] - wire [77:0] swerv_io_iccm_wr_data; // @[quasar_wrapper.scala 87:21] - wire [63:0] swerv_io_iccm_rd_data; // @[quasar_wrapper.scala 87:21] - wire [77:0] swerv_io_iccm_rd_data_ecc; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dma_hsel; // @[quasar_wrapper.scala 87:21] - wire [31:0] swerv_io_dma_haddr; // @[quasar_wrapper.scala 87:21] - wire [2:0] swerv_io_dma_hsize; // @[quasar_wrapper.scala 87:21] - wire [1:0] swerv_io_dma_htrans; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dma_hwrite; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dma_hreadyin; // @[quasar_wrapper.scala 87:21] - wire swerv_io_lsu_bus_clk_en; // @[quasar_wrapper.scala 87:21] - wire swerv_io_ifu_bus_clk_en; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dbg_bus_clk_en; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dma_bus_clk_en; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dmi_reg_en; // @[quasar_wrapper.scala 87:21] - wire [6:0] swerv_io_dmi_reg_addr; // @[quasar_wrapper.scala 87:21] - wire swerv_io_dmi_reg_wr_en; // @[quasar_wrapper.scala 87:21] - wire [31:0] swerv_io_dmi_reg_wdata; // @[quasar_wrapper.scala 87:21] - wire [30:0] swerv_io_extintsrc_req; // @[quasar_wrapper.scala 87:21] - wire swerv_io_timer_int; // @[quasar_wrapper.scala 87:21] - wire swerv_io_soft_int; // @[quasar_wrapper.scala 87:21] - wire swerv_io_scan_mode; // @[quasar_wrapper.scala 87:21] - mem #(.ICACHE_BEAT_BITS(3), .ICCM_BITS(16), .ICACHE_BANKS_WAY(2), .ICACHE_NUM_WAYS(2), .DCCM_BYTE_WIDTH(4), .ICCM_BANK_INDEX_LO(4), .ICACHE_BANK_BITS(1), .DCCM_BITS(16), .ICACHE_BEAT_ADDR_HI(5), .ICCM_INDEX_BITS(12), .ICCM_BANK_HI(3), .ICACHE_INDEX_HI(12), .DCCM_NUM_BANKS(4), .ICACHE_BANK_LO(3), .DCCM_ENABLE(1), .ICACHE_TAG_LO(13), .ICACHE_DATA_INDEX_LO(4), .ICCM_NUM_BANKS(4), .ICACHE_ECC(1), .ICACHE_ENABLE(1), .DCCM_BANK_BITS(2), .ICCM_ENABLE(1), .ICCM_BANK_BITS(2), .ICACHE_TAG_DEPTH(128), .ICACHE_WAYPACK(0), .DCCM_SIZE(64), .ICACHE_BANK_HI(3), .DCCM_FDATA_WIDTH(39), .ICACHE_TAG_INDEX_LO(6), .ICACHE_DATA_DEPTH(512)) mem ( // @[quasar_wrapper.scala 85:19] + wire mem_clk; // @[quasar_wrapper.scala 78:19] + wire mem_rst_l; // @[quasar_wrapper.scala 78:19] + wire mem_dccm_clk_override; // @[quasar_wrapper.scala 78:19] + wire mem_icm_clk_override; // @[quasar_wrapper.scala 78:19] + wire mem_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 78:19] + wire mem_dccm_wren; // @[quasar_wrapper.scala 78:19] + wire mem_dccm_rden; // @[quasar_wrapper.scala 78:19] + wire [15:0] mem_dccm_wr_addr_lo; // @[quasar_wrapper.scala 78:19] + wire [15:0] mem_dccm_wr_addr_hi; // @[quasar_wrapper.scala 78:19] + wire [15:0] mem_dccm_rd_addr_lo; // @[quasar_wrapper.scala 78:19] + wire [15:0] mem_dccm_rd_addr_hi; // @[quasar_wrapper.scala 78:19] + wire [38:0] mem_dccm_wr_data_lo; // @[quasar_wrapper.scala 78:19] + wire [38:0] mem_dccm_wr_data_hi; // @[quasar_wrapper.scala 78:19] + wire [38:0] mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 78:19] + wire [38:0] mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 78:19] + wire [14:0] mem_iccm_rw_addr; // @[quasar_wrapper.scala 78:19] + wire mem_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 78:19] + wire mem_iccm_correction_state; // @[quasar_wrapper.scala 78:19] + wire mem_iccm_wren; // @[quasar_wrapper.scala 78:19] + wire mem_iccm_rden; // @[quasar_wrapper.scala 78:19] + wire [2:0] mem_iccm_wr_size; // @[quasar_wrapper.scala 78:19] + wire [77:0] mem_iccm_wr_data; // @[quasar_wrapper.scala 78:19] + wire [63:0] mem_iccm_rd_data; // @[quasar_wrapper.scala 78:19] + wire [77:0] mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 78:19] + wire [30:0] mem_ic_rw_addr; // @[quasar_wrapper.scala 78:19] + wire [1:0] mem_ic_tag_valid; // @[quasar_wrapper.scala 78:19] + wire [1:0] mem_ic_wr_en; // @[quasar_wrapper.scala 78:19] + wire mem_ic_rd_en; // @[quasar_wrapper.scala 78:19] + wire [70:0] mem_ic_wr_data_0; // @[quasar_wrapper.scala 78:19] + wire [70:0] mem_ic_wr_data_1; // @[quasar_wrapper.scala 78:19] + wire [70:0] mem_ic_debug_wr_data; // @[quasar_wrapper.scala 78:19] + wire [9:0] mem_ic_debug_addr; // @[quasar_wrapper.scala 78:19] + wire [63:0] mem_ic_rd_data; // @[quasar_wrapper.scala 78:19] + wire [70:0] mem_ic_debug_rd_data; // @[quasar_wrapper.scala 78:19] + wire [25:0] mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 78:19] + wire [1:0] mem_ic_eccerr; // @[quasar_wrapper.scala 78:19] + wire [1:0] mem_ic_parerr; // @[quasar_wrapper.scala 78:19] + wire [1:0] mem_ic_rd_hit; // @[quasar_wrapper.scala 78:19] + wire mem_ic_tag_perr; // @[quasar_wrapper.scala 78:19] + wire mem_ic_debug_rd_en; // @[quasar_wrapper.scala 78:19] + wire mem_ic_debug_wr_en; // @[quasar_wrapper.scala 78:19] + wire mem_ic_debug_tag_array; // @[quasar_wrapper.scala 78:19] + wire [1:0] mem_ic_debug_way; // @[quasar_wrapper.scala 78:19] + wire [63:0] mem_ic_premux_data; // @[quasar_wrapper.scala 78:19] + wire mem_ic_sel_premux_data; // @[quasar_wrapper.scala 78:19] + wire mem_scan_mode; // @[quasar_wrapper.scala 78:19] + wire dmi_wrapper_trst_n; // @[quasar_wrapper.scala 79:27] + wire dmi_wrapper_tck; // @[quasar_wrapper.scala 79:27] + wire dmi_wrapper_tms; // @[quasar_wrapper.scala 79:27] + wire dmi_wrapper_tdi; // @[quasar_wrapper.scala 79:27] + wire dmi_wrapper_tdo; // @[quasar_wrapper.scala 79:27] + wire dmi_wrapper_tdoEnable; // @[quasar_wrapper.scala 79:27] + wire dmi_wrapper_core_rst_n; // @[quasar_wrapper.scala 79:27] + wire dmi_wrapper_core_clk; // @[quasar_wrapper.scala 79:27] + wire [30:0] dmi_wrapper_jtag_id; // @[quasar_wrapper.scala 79:27] + wire [31:0] dmi_wrapper_rd_data; // @[quasar_wrapper.scala 79:27] + wire [31:0] dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 79:27] + wire [6:0] dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 79:27] + wire dmi_wrapper_reg_en; // @[quasar_wrapper.scala 79:27] + wire dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 79:27] + wire dmi_wrapper_dmi_hard_reset; // @[quasar_wrapper.scala 79:27] + wire swerv_clock; // @[quasar_wrapper.scala 80:21] + wire swerv_reset; // @[quasar_wrapper.scala 80:21] + wire swerv_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 80:21] + wire [2:0] swerv_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 80:21] + wire [31:0] swerv_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 80:21] + wire [3:0] swerv_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 80:21] + wire [2:0] swerv_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 80:21] + wire [3:0] swerv_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 80:21] + wire swerv_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 80:21] + wire [63:0] swerv_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 80:21] + wire [7:0] swerv_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 80:21] + wire swerv_io_lsu_axi_b_ready; // @[quasar_wrapper.scala 80:21] + wire swerv_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 80:21] + wire [2:0] swerv_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 80:21] + wire [31:0] swerv_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 80:21] + wire [3:0] swerv_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 80:21] + wire [2:0] swerv_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 80:21] + wire [3:0] swerv_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 80:21] + wire swerv_io_lsu_axi_r_ready; // @[quasar_wrapper.scala 80:21] + wire swerv_io_ifu_axi_aw_valid; // @[quasar_wrapper.scala 80:21] + wire [2:0] swerv_io_ifu_axi_aw_bits_id; // @[quasar_wrapper.scala 80:21] + wire swerv_io_ifu_axi_w_valid; // @[quasar_wrapper.scala 80:21] + wire [63:0] swerv_io_ifu_axi_w_bits_data; // @[quasar_wrapper.scala 80:21] + wire swerv_io_ifu_axi_b_ready; // @[quasar_wrapper.scala 80:21] + wire swerv_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 80:21] + wire [2:0] swerv_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 80:21] + wire [31:0] swerv_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 80:21] + wire [3:0] swerv_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 80:21] + wire swerv_io_ifu_axi_r_ready; // @[quasar_wrapper.scala 80:21] + wire swerv_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 80:21] + wire swerv_io_sb_axi_aw_bits_id; // @[quasar_wrapper.scala 80:21] + wire [31:0] swerv_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 80:21] + wire [3:0] swerv_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 80:21] + wire [2:0] swerv_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 80:21] + wire swerv_io_sb_axi_w_valid; // @[quasar_wrapper.scala 80:21] + wire [63:0] swerv_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 80:21] + wire [7:0] swerv_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 80:21] + wire swerv_io_sb_axi_b_ready; // @[quasar_wrapper.scala 80:21] + wire swerv_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 80:21] + wire swerv_io_sb_axi_ar_bits_id; // @[quasar_wrapper.scala 80:21] + wire [31:0] swerv_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 80:21] + wire [3:0] swerv_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 80:21] + wire [2:0] swerv_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 80:21] + wire swerv_io_sb_axi_r_ready; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dma_axi_w_ready; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dma_axi_b_valid; // @[quasar_wrapper.scala 80:21] + wire [1:0] swerv_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dma_axi_ar_valid; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dma_axi_r_valid; // @[quasar_wrapper.scala 80:21] + wire [63:0] swerv_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 80:21] + wire [1:0] swerv_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dbg_rst_l; // @[quasar_wrapper.scala 80:21] + wire [30:0] swerv_io_rst_vec; // @[quasar_wrapper.scala 80:21] + wire swerv_io_nmi_int; // @[quasar_wrapper.scala 80:21] + wire [30:0] swerv_io_nmi_vec; // @[quasar_wrapper.scala 80:21] + wire swerv_io_core_rst_l; // @[quasar_wrapper.scala 80:21] + wire [1:0] swerv_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 80:21] + wire [31:0] swerv_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 80:21] + wire [31:0] swerv_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 80:21] + wire [1:0] swerv_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 80:21] + wire [4:0] swerv_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 80:21] + wire [1:0] swerv_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 80:21] + wire [31:0] swerv_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dccm_clk_override; // @[quasar_wrapper.scala 80:21] + wire swerv_io_icm_clk_override; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 80:21] + wire swerv_io_i_cpu_halt_req; // @[quasar_wrapper.scala 80:21] + wire swerv_io_i_cpu_run_req; // @[quasar_wrapper.scala 80:21] + wire swerv_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 80:21] + wire swerv_io_o_cpu_halt_status; // @[quasar_wrapper.scala 80:21] + wire swerv_io_o_cpu_run_ack; // @[quasar_wrapper.scala 80:21] + wire swerv_io_o_debug_mode_status; // @[quasar_wrapper.scala 80:21] + wire [27:0] swerv_io_core_id; // @[quasar_wrapper.scala 80:21] + wire swerv_io_mpc_debug_halt_req; // @[quasar_wrapper.scala 80:21] + wire swerv_io_mpc_debug_run_req; // @[quasar_wrapper.scala 80:21] + wire swerv_io_mpc_reset_run_req; // @[quasar_wrapper.scala 80:21] + wire swerv_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 80:21] + wire swerv_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 80:21] + wire swerv_io_debug_brkpt_status; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dccm_wren; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dccm_rden; // @[quasar_wrapper.scala 80:21] + wire [15:0] swerv_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 80:21] + wire [15:0] swerv_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 80:21] + wire [15:0] swerv_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 80:21] + wire [15:0] swerv_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 80:21] + wire [38:0] swerv_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 80:21] + wire [38:0] swerv_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 80:21] + wire [38:0] swerv_io_dccm_rd_data_lo; // @[quasar_wrapper.scala 80:21] + wire [38:0] swerv_io_dccm_rd_data_hi; // @[quasar_wrapper.scala 80:21] + wire [30:0] swerv_io_ic_rw_addr; // @[quasar_wrapper.scala 80:21] + wire [1:0] swerv_io_ic_tag_valid; // @[quasar_wrapper.scala 80:21] + wire [1:0] swerv_io_ic_wr_en; // @[quasar_wrapper.scala 80:21] + wire swerv_io_ic_rd_en; // @[quasar_wrapper.scala 80:21] + wire [70:0] swerv_io_ic_wr_data_0; // @[quasar_wrapper.scala 80:21] + wire [70:0] swerv_io_ic_wr_data_1; // @[quasar_wrapper.scala 80:21] + wire [70:0] swerv_io_ic_debug_wr_data; // @[quasar_wrapper.scala 80:21] + wire [9:0] swerv_io_ic_debug_addr; // @[quasar_wrapper.scala 80:21] + wire [63:0] swerv_io_ic_rd_data; // @[quasar_wrapper.scala 80:21] + wire [70:0] swerv_io_ic_debug_rd_data; // @[quasar_wrapper.scala 80:21] + wire [25:0] swerv_io_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 80:21] + wire [1:0] swerv_io_ic_eccerr; // @[quasar_wrapper.scala 80:21] + wire [1:0] swerv_io_ic_rd_hit; // @[quasar_wrapper.scala 80:21] + wire swerv_io_ic_tag_perr; // @[quasar_wrapper.scala 80:21] + wire swerv_io_ic_debug_rd_en; // @[quasar_wrapper.scala 80:21] + wire swerv_io_ic_debug_wr_en; // @[quasar_wrapper.scala 80:21] + wire swerv_io_ic_debug_tag_array; // @[quasar_wrapper.scala 80:21] + wire [1:0] swerv_io_ic_debug_way; // @[quasar_wrapper.scala 80:21] + wire [63:0] swerv_io_ic_premux_data; // @[quasar_wrapper.scala 80:21] + wire swerv_io_ic_sel_premux_data; // @[quasar_wrapper.scala 80:21] + wire [14:0] swerv_io_iccm_rw_addr; // @[quasar_wrapper.scala 80:21] + wire swerv_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 80:21] + wire swerv_io_iccm_correction_state; // @[quasar_wrapper.scala 80:21] + wire swerv_io_iccm_wren; // @[quasar_wrapper.scala 80:21] + wire swerv_io_iccm_rden; // @[quasar_wrapper.scala 80:21] + wire [2:0] swerv_io_iccm_wr_size; // @[quasar_wrapper.scala 80:21] + wire [77:0] swerv_io_iccm_wr_data; // @[quasar_wrapper.scala 80:21] + wire [63:0] swerv_io_iccm_rd_data; // @[quasar_wrapper.scala 80:21] + wire [77:0] swerv_io_iccm_rd_data_ecc; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dma_hsel; // @[quasar_wrapper.scala 80:21] + wire [31:0] swerv_io_dma_haddr; // @[quasar_wrapper.scala 80:21] + wire [2:0] swerv_io_dma_hsize; // @[quasar_wrapper.scala 80:21] + wire [1:0] swerv_io_dma_htrans; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dma_hwrite; // @[quasar_wrapper.scala 80:21] + wire [63:0] swerv_io_dma_hwdata; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dma_hreadyin; // @[quasar_wrapper.scala 80:21] + wire [63:0] swerv_io_dma_hrdata; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dma_hreadyout; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dma_hresp; // @[quasar_wrapper.scala 80:21] + wire swerv_io_lsu_bus_clk_en; // @[quasar_wrapper.scala 80:21] + wire swerv_io_ifu_bus_clk_en; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dbg_bus_clk_en; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dma_bus_clk_en; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dmi_reg_en; // @[quasar_wrapper.scala 80:21] + wire [6:0] swerv_io_dmi_reg_addr; // @[quasar_wrapper.scala 80:21] + wire swerv_io_dmi_reg_wr_en; // @[quasar_wrapper.scala 80:21] + wire [31:0] swerv_io_dmi_reg_wdata; // @[quasar_wrapper.scala 80:21] + wire [30:0] swerv_io_extintsrc_req; // @[quasar_wrapper.scala 80:21] + wire swerv_io_timer_int; // @[quasar_wrapper.scala 80:21] + wire swerv_io_soft_int; // @[quasar_wrapper.scala 80:21] + wire swerv_io_scan_mode; // @[quasar_wrapper.scala 80:21] + mem #(.ICACHE_BEAT_BITS(3), .ICCM_BITS(16), .ICACHE_BANKS_WAY(2), .ICACHE_NUM_WAYS(2), .DCCM_BYTE_WIDTH(4), .ICCM_BANK_INDEX_LO(4), .ICACHE_BANK_BITS(1), .DCCM_BITS(16), .ICACHE_BEAT_ADDR_HI(5), .ICCM_INDEX_BITS(12), .ICCM_BANK_HI(3), .ICACHE_INDEX_HI(12), .DCCM_NUM_BANKS(4), .ICACHE_BANK_LO(3), .DCCM_ENABLE(1), .ICACHE_TAG_LO(13), .ICACHE_DATA_INDEX_LO(4), .ICCM_NUM_BANKS(4), .ICACHE_ECC(1), .ICACHE_ENABLE(1), .DCCM_BANK_BITS(2), .ICCM_ENABLE(1), .ICCM_BANK_BITS(2), .ICACHE_TAG_DEPTH(128), .ICACHE_WAYPACK(0), .DCCM_SIZE(64), .ICACHE_BANK_HI(3), .DCCM_FDATA_WIDTH(39), .ICACHE_TAG_INDEX_LO(6), .ICACHE_DATA_DEPTH(512)) mem ( // @[quasar_wrapper.scala 78:19] .clk(mem_clk), .rst_l(mem_rst_l), .dccm_clk_override(mem_dccm_clk_override), @@ -84046,7 +84066,7 @@ module quasar_wrapper( .ic_sel_premux_data(mem_ic_sel_premux_data), .scan_mode(mem_scan_mode) ); - dmi_wrapper dmi_wrapper ( // @[quasar_wrapper.scala 86:27] + dmi_wrapper dmi_wrapper ( // @[quasar_wrapper.scala 79:27] .trst_n(dmi_wrapper_trst_n), .tck(dmi_wrapper_tck), .tms(dmi_wrapper_tms), @@ -84063,25 +84083,19 @@ module quasar_wrapper( .reg_wr_en(dmi_wrapper_reg_wr_en), .dmi_hard_reset(dmi_wrapper_dmi_hard_reset) ); - quasar swerv ( // @[quasar_wrapper.scala 87:21] + quasar swerv ( // @[quasar_wrapper.scala 80:21] .clock(swerv_clock), .reset(swerv_reset), - .io_lsu_axi_aw_ready(swerv_io_lsu_axi_aw_ready), .io_lsu_axi_aw_valid(swerv_io_lsu_axi_aw_valid), .io_lsu_axi_aw_bits_id(swerv_io_lsu_axi_aw_bits_id), .io_lsu_axi_aw_bits_addr(swerv_io_lsu_axi_aw_bits_addr), .io_lsu_axi_aw_bits_region(swerv_io_lsu_axi_aw_bits_region), .io_lsu_axi_aw_bits_size(swerv_io_lsu_axi_aw_bits_size), .io_lsu_axi_aw_bits_cache(swerv_io_lsu_axi_aw_bits_cache), - .io_lsu_axi_w_ready(swerv_io_lsu_axi_w_ready), .io_lsu_axi_w_valid(swerv_io_lsu_axi_w_valid), .io_lsu_axi_w_bits_data(swerv_io_lsu_axi_w_bits_data), .io_lsu_axi_w_bits_strb(swerv_io_lsu_axi_w_bits_strb), .io_lsu_axi_b_ready(swerv_io_lsu_axi_b_ready), - .io_lsu_axi_b_valid(swerv_io_lsu_axi_b_valid), - .io_lsu_axi_b_bits_resp(swerv_io_lsu_axi_b_bits_resp), - .io_lsu_axi_b_bits_id(swerv_io_lsu_axi_b_bits_id), - .io_lsu_axi_ar_ready(swerv_io_lsu_axi_ar_ready), .io_lsu_axi_ar_valid(swerv_io_lsu_axi_ar_valid), .io_lsu_axi_ar_bits_id(swerv_io_lsu_axi_ar_bits_id), .io_lsu_axi_ar_bits_addr(swerv_io_lsu_axi_ar_bits_addr), @@ -84089,65 +84103,38 @@ module quasar_wrapper( .io_lsu_axi_ar_bits_size(swerv_io_lsu_axi_ar_bits_size), .io_lsu_axi_ar_bits_cache(swerv_io_lsu_axi_ar_bits_cache), .io_lsu_axi_r_ready(swerv_io_lsu_axi_r_ready), - .io_lsu_axi_r_valid(swerv_io_lsu_axi_r_valid), - .io_lsu_axi_r_bits_id(swerv_io_lsu_axi_r_bits_id), - .io_lsu_axi_r_bits_data(swerv_io_lsu_axi_r_bits_data), - .io_lsu_axi_r_bits_resp(swerv_io_lsu_axi_r_bits_resp), .io_ifu_axi_aw_valid(swerv_io_ifu_axi_aw_valid), + .io_ifu_axi_aw_bits_id(swerv_io_ifu_axi_aw_bits_id), .io_ifu_axi_w_valid(swerv_io_ifu_axi_w_valid), + .io_ifu_axi_w_bits_data(swerv_io_ifu_axi_w_bits_data), .io_ifu_axi_b_ready(swerv_io_ifu_axi_b_ready), - .io_ifu_axi_ar_ready(swerv_io_ifu_axi_ar_ready), .io_ifu_axi_ar_valid(swerv_io_ifu_axi_ar_valid), .io_ifu_axi_ar_bits_id(swerv_io_ifu_axi_ar_bits_id), .io_ifu_axi_ar_bits_addr(swerv_io_ifu_axi_ar_bits_addr), .io_ifu_axi_ar_bits_region(swerv_io_ifu_axi_ar_bits_region), .io_ifu_axi_r_ready(swerv_io_ifu_axi_r_ready), - .io_ifu_axi_r_valid(swerv_io_ifu_axi_r_valid), - .io_ifu_axi_r_bits_id(swerv_io_ifu_axi_r_bits_id), - .io_ifu_axi_r_bits_data(swerv_io_ifu_axi_r_bits_data), - .io_ifu_axi_r_bits_resp(swerv_io_ifu_axi_r_bits_resp), - .io_sb_axi_aw_ready(swerv_io_sb_axi_aw_ready), .io_sb_axi_aw_valid(swerv_io_sb_axi_aw_valid), + .io_sb_axi_aw_bits_id(swerv_io_sb_axi_aw_bits_id), .io_sb_axi_aw_bits_addr(swerv_io_sb_axi_aw_bits_addr), .io_sb_axi_aw_bits_region(swerv_io_sb_axi_aw_bits_region), .io_sb_axi_aw_bits_size(swerv_io_sb_axi_aw_bits_size), - .io_sb_axi_w_ready(swerv_io_sb_axi_w_ready), .io_sb_axi_w_valid(swerv_io_sb_axi_w_valid), .io_sb_axi_w_bits_data(swerv_io_sb_axi_w_bits_data), .io_sb_axi_w_bits_strb(swerv_io_sb_axi_w_bits_strb), .io_sb_axi_b_ready(swerv_io_sb_axi_b_ready), - .io_sb_axi_b_valid(swerv_io_sb_axi_b_valid), - .io_sb_axi_b_bits_resp(swerv_io_sb_axi_b_bits_resp), - .io_sb_axi_ar_ready(swerv_io_sb_axi_ar_ready), .io_sb_axi_ar_valid(swerv_io_sb_axi_ar_valid), + .io_sb_axi_ar_bits_id(swerv_io_sb_axi_ar_bits_id), .io_sb_axi_ar_bits_addr(swerv_io_sb_axi_ar_bits_addr), .io_sb_axi_ar_bits_region(swerv_io_sb_axi_ar_bits_region), .io_sb_axi_ar_bits_size(swerv_io_sb_axi_ar_bits_size), .io_sb_axi_r_ready(swerv_io_sb_axi_r_ready), - .io_sb_axi_r_valid(swerv_io_sb_axi_r_valid), - .io_sb_axi_r_bits_data(swerv_io_sb_axi_r_bits_data), - .io_sb_axi_r_bits_resp(swerv_io_sb_axi_r_bits_resp), .io_dma_axi_aw_ready(swerv_io_dma_axi_aw_ready), - .io_dma_axi_aw_valid(swerv_io_dma_axi_aw_valid), - .io_dma_axi_aw_bits_id(swerv_io_dma_axi_aw_bits_id), - .io_dma_axi_aw_bits_addr(swerv_io_dma_axi_aw_bits_addr), - .io_dma_axi_aw_bits_size(swerv_io_dma_axi_aw_bits_size), .io_dma_axi_w_ready(swerv_io_dma_axi_w_ready), - .io_dma_axi_w_valid(swerv_io_dma_axi_w_valid), - .io_dma_axi_w_bits_data(swerv_io_dma_axi_w_bits_data), - .io_dma_axi_w_bits_strb(swerv_io_dma_axi_w_bits_strb), - .io_dma_axi_b_ready(swerv_io_dma_axi_b_ready), .io_dma_axi_b_valid(swerv_io_dma_axi_b_valid), .io_dma_axi_b_bits_resp(swerv_io_dma_axi_b_bits_resp), - .io_dma_axi_b_bits_id(swerv_io_dma_axi_b_bits_id), .io_dma_axi_ar_ready(swerv_io_dma_axi_ar_ready), .io_dma_axi_ar_valid(swerv_io_dma_axi_ar_valid), - .io_dma_axi_ar_bits_id(swerv_io_dma_axi_ar_bits_id), - .io_dma_axi_ar_bits_addr(swerv_io_dma_axi_ar_bits_addr), - .io_dma_axi_ar_bits_size(swerv_io_dma_axi_ar_bits_size), - .io_dma_axi_r_ready(swerv_io_dma_axi_r_ready), .io_dma_axi_r_valid(swerv_io_dma_axi_r_valid), - .io_dma_axi_r_bits_id(swerv_io_dma_axi_r_bits_id), .io_dma_axi_r_bits_data(swerv_io_dma_axi_r_bits_data), .io_dma_axi_r_bits_resp(swerv_io_dma_axi_r_bits_resp), .io_dbg_rst_l(swerv_io_dbg_rst_l), @@ -84155,13 +84142,13 @@ module quasar_wrapper( .io_nmi_int(swerv_io_nmi_int), .io_nmi_vec(swerv_io_nmi_vec), .io_core_rst_l(swerv_io_core_rst_l), - .io_trace_rv_i_insn_ip(swerv_io_trace_rv_i_insn_ip), - .io_trace_rv_i_address_ip(swerv_io_trace_rv_i_address_ip), - .io_trace_rv_i_valid_ip(swerv_io_trace_rv_i_valid_ip), - .io_trace_rv_i_exception_ip(swerv_io_trace_rv_i_exception_ip), - .io_trace_rv_i_ecause_ip(swerv_io_trace_rv_i_ecause_ip), - .io_trace_rv_i_interrupt_ip(swerv_io_trace_rv_i_interrupt_ip), - .io_trace_rv_i_tval_ip(swerv_io_trace_rv_i_tval_ip), + .io_rv_trace_pkt_rv_i_valid_ip(swerv_io_rv_trace_pkt_rv_i_valid_ip), + .io_rv_trace_pkt_rv_i_insn_ip(swerv_io_rv_trace_pkt_rv_i_insn_ip), + .io_rv_trace_pkt_rv_i_address_ip(swerv_io_rv_trace_pkt_rv_i_address_ip), + .io_rv_trace_pkt_rv_i_exception_ip(swerv_io_rv_trace_pkt_rv_i_exception_ip), + .io_rv_trace_pkt_rv_i_ecause_ip(swerv_io_rv_trace_pkt_rv_i_ecause_ip), + .io_rv_trace_pkt_rv_i_interrupt_ip(swerv_io_rv_trace_pkt_rv_i_interrupt_ip), + .io_rv_trace_pkt_rv_i_tval_ip(swerv_io_rv_trace_pkt_rv_i_tval_ip), .io_dccm_clk_override(swerv_io_dccm_clk_override), .io_icm_clk_override(swerv_io_icm_clk_override), .io_dec_tlu_core_ecc_disable(swerv_io_dec_tlu_core_ecc_disable), @@ -84226,7 +84213,11 @@ module quasar_wrapper( .io_dma_hsize(swerv_io_dma_hsize), .io_dma_htrans(swerv_io_dma_htrans), .io_dma_hwrite(swerv_io_dma_hwrite), + .io_dma_hwdata(swerv_io_dma_hwdata), .io_dma_hreadyin(swerv_io_dma_hreadyin), + .io_dma_hrdata(swerv_io_dma_hrdata), + .io_dma_hreadyout(swerv_io_dma_hreadyout), + .io_dma_hresp(swerv_io_dma_hresp), .io_lsu_bus_clk_en(swerv_io_lsu_bus_clk_en), .io_ifu_bus_clk_en(swerv_io_ifu_bus_clk_en), .io_dbg_bus_clk_en(swerv_io_dbg_bus_clk_en), @@ -84240,240 +84231,206 @@ module quasar_wrapper( .io_soft_int(swerv_io_soft_int), .io_scan_mode(swerv_io_scan_mode) ); - assign io_trace_rv_i_insn_ip = swerv_io_trace_rv_i_insn_ip; // @[quasar_wrapper.scala 196:25] - assign io_trace_rv_i_address_ip = swerv_io_trace_rv_i_address_ip; // @[quasar_wrapper.scala 197:28] - assign io_trace_rv_i_valid_ip = swerv_io_trace_rv_i_valid_ip; // @[quasar_wrapper.scala 198:26] - assign io_trace_rv_i_exception_ip = swerv_io_trace_rv_i_exception_ip; // @[quasar_wrapper.scala 199:30] - assign io_trace_rv_i_ecause_ip = swerv_io_trace_rv_i_ecause_ip; // @[quasar_wrapper.scala 200:27] - assign io_trace_rv_i_interrupt_ip = swerv_io_trace_rv_i_interrupt_ip; // @[quasar_wrapper.scala 201:30] - assign io_trace_rv_i_tval_ip = swerv_io_trace_rv_i_tval_ip; // @[quasar_wrapper.scala 202:25] - assign io_lsu_axi_aw_valid = swerv_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_aw_bits_id = swerv_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_aw_bits_addr = swerv_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_aw_bits_region = swerv_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_aw_bits_size = swerv_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_aw_bits_cache = swerv_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_w_valid = swerv_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_w_bits_data = swerv_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_w_bits_strb = swerv_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_w_bits_last = 1'h1; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_b_ready = 1'h1; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_ar_valid = swerv_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_ar_bits_id = swerv_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_ar_bits_addr = swerv_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_ar_bits_region = swerv_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_ar_bits_size = swerv_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_ar_bits_cache = swerv_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 145:20] - assign io_lsu_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 145:20] - assign io_ifu_axi_aw_valid = 1'h0; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_w_valid = 1'h0; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_w_bits_data = 64'h0; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_w_bits_last = 1'h0; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_b_ready = 1'h0; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_ar_valid = swerv_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_ar_bits_id = swerv_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_ar_bits_addr = swerv_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_ar_bits_region = swerv_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_ar_bits_size = 3'h3; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_ar_bits_cache = 4'hf; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 148:20] - assign io_ifu_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 148:20] - assign io_sb_axi_aw_valid = swerv_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_aw_bits_id = 1'h0; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_aw_bits_addr = swerv_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_aw_bits_region = swerv_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_aw_bits_size = swerv_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_aw_bits_cache = 4'hf; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_w_valid = swerv_io_sb_axi_w_valid; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_w_bits_data = swerv_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_w_bits_strb = swerv_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_w_bits_last = 1'h1; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_b_ready = 1'h1; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_ar_valid = swerv_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_ar_bits_id = 1'h0; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_ar_bits_addr = swerv_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_ar_bits_region = swerv_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_ar_bits_size = swerv_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 151:19] - assign io_sb_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 151:19] - assign io_dma_axi_aw_ready = swerv_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 155:20] - assign io_dma_axi_w_ready = swerv_io_dma_axi_w_ready; // @[quasar_wrapper.scala 155:20] - assign io_dma_axi_b_valid = swerv_io_dma_axi_b_valid; // @[quasar_wrapper.scala 155:20] - assign io_dma_axi_b_bits_resp = swerv_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 155:20] - assign io_dma_axi_b_bits_id = swerv_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 155:20] - assign io_dma_axi_ar_ready = swerv_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 155:20] - assign io_dma_axi_r_valid = swerv_io_dma_axi_r_valid; // @[quasar_wrapper.scala 155:20] - assign io_dma_axi_r_bits_id = swerv_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 155:20] - assign io_dma_axi_r_bits_data = swerv_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 155:20] - assign io_dma_axi_r_bits_resp = swerv_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 155:20] - assign io_dma_axi_r_bits_last = 1'h1; // @[quasar_wrapper.scala 155:20] - assign io_dma_hrdata = 64'h0; // @[quasar_wrapper.scala 224:17] - assign io_dma_hreadyout = 1'h0; // @[quasar_wrapper.scala 225:20] - assign io_dma_hresp = 1'h0; // @[quasar_wrapper.scala 226:16] - assign io_dec_tlu_perfcnt0 = swerv_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 214:23] - assign io_dec_tlu_perfcnt1 = swerv_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 215:23] - assign io_dec_tlu_perfcnt2 = swerv_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 216:23] - assign io_dec_tlu_perfcnt3 = swerv_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 217:23] - assign io_jtag_tdo = dmi_wrapper_tdo; // @[quasar_wrapper.scala 103:15] - assign io_mpc_debug_halt_ack = swerv_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 210:25] - assign io_mpc_debug_run_ack = swerv_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 211:24] - assign io_debug_brkpt_status = swerv_io_debug_brkpt_status; // @[quasar_wrapper.scala 212:25] - assign io_o_cpu_halt_ack = swerv_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 205:21] - assign io_o_cpu_halt_status = swerv_io_o_cpu_halt_status; // @[quasar_wrapper.scala 206:24] - assign io_o_debug_mode_status = swerv_io_o_debug_mode_status; // @[quasar_wrapper.scala 208:26] - assign io_o_cpu_run_ack = swerv_io_o_cpu_run_ack; // @[quasar_wrapper.scala 207:20] - assign mem_clk = clock; // @[quasar_wrapper.scala 111:14] - assign mem_rst_l = reset; // @[quasar_wrapper.scala 110:16] - assign mem_dccm_clk_override = swerv_io_dccm_clk_override; // @[quasar_wrapper.scala 106:28] - assign mem_icm_clk_override = swerv_io_icm_clk_override; // @[quasar_wrapper.scala 107:27] - assign mem_dec_tlu_core_ecc_disable = swerv_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 108:35] - assign mem_dccm_wren = swerv_io_dccm_wren; // @[quasar_wrapper.scala 109:15] - assign mem_dccm_rden = swerv_io_dccm_rden; // @[quasar_wrapper.scala 109:15] - assign mem_dccm_wr_addr_lo = swerv_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 109:15] - assign mem_dccm_wr_addr_hi = swerv_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 109:15] - assign mem_dccm_rd_addr_lo = swerv_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 109:15] - assign mem_dccm_rd_addr_hi = swerv_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 109:15] - assign mem_dccm_wr_data_lo = swerv_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 109:15] - assign mem_dccm_wr_data_hi = swerv_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 109:15] - assign mem_iccm_rw_addr = swerv_io_iccm_rw_addr; // @[quasar_wrapper.scala 116:17] - assign mem_iccm_buf_correct_ecc = swerv_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 116:17] - assign mem_iccm_correction_state = swerv_io_iccm_correction_state; // @[quasar_wrapper.scala 116:17] - assign mem_iccm_wren = swerv_io_iccm_wren; // @[quasar_wrapper.scala 116:17] - assign mem_iccm_rden = swerv_io_iccm_rden; // @[quasar_wrapper.scala 116:17] - assign mem_iccm_wr_size = swerv_io_iccm_wr_size; // @[quasar_wrapper.scala 116:17] - assign mem_iccm_wr_data = swerv_io_iccm_wr_data; // @[quasar_wrapper.scala 116:17] - assign mem_ic_rw_addr = swerv_io_ic_rw_addr; // @[quasar_wrapper.scala 115:15] - assign mem_ic_tag_valid = swerv_io_ic_tag_valid; // @[quasar_wrapper.scala 115:15] - assign mem_ic_wr_en = swerv_io_ic_wr_en; // @[quasar_wrapper.scala 115:15] - assign mem_ic_rd_en = swerv_io_ic_rd_en; // @[quasar_wrapper.scala 115:15] - assign mem_ic_wr_data_0 = swerv_io_ic_wr_data_0; // @[quasar_wrapper.scala 115:15] - assign mem_ic_wr_data_1 = swerv_io_ic_wr_data_1; // @[quasar_wrapper.scala 115:15] - assign mem_ic_debug_wr_data = swerv_io_ic_debug_wr_data; // @[quasar_wrapper.scala 115:15] - assign mem_ic_debug_addr = swerv_io_ic_debug_addr; // @[quasar_wrapper.scala 115:15] - assign mem_ic_debug_rd_en = swerv_io_ic_debug_rd_en; // @[quasar_wrapper.scala 115:15] - assign mem_ic_debug_wr_en = swerv_io_ic_debug_wr_en; // @[quasar_wrapper.scala 115:15] - assign mem_ic_debug_tag_array = swerv_io_ic_debug_tag_array; // @[quasar_wrapper.scala 115:15] - assign mem_ic_debug_way = swerv_io_ic_debug_way; // @[quasar_wrapper.scala 115:15] - assign mem_ic_premux_data = swerv_io_ic_premux_data; // @[quasar_wrapper.scala 115:15] - assign mem_ic_sel_premux_data = swerv_io_ic_sel_premux_data; // @[quasar_wrapper.scala 115:15] - assign mem_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 112:20] - assign dmi_wrapper_trst_n = io_jtag_trst_n; // @[quasar_wrapper.scala 88:25] - assign dmi_wrapper_tck = io_jtag_tck; // @[quasar_wrapper.scala 89:22] - assign dmi_wrapper_tms = io_jtag_tms; // @[quasar_wrapper.scala 90:22] - assign dmi_wrapper_tdi = io_jtag_tdi; // @[quasar_wrapper.scala 91:22] - assign dmi_wrapper_core_rst_n = io_dbg_rst_l; // @[quasar_wrapper.scala 97:29] - assign dmi_wrapper_core_clk = clock; // @[quasar_wrapper.scala 92:27] - assign dmi_wrapper_jtag_id = io_jtag_id; // @[quasar_wrapper.scala 93:26] - assign dmi_wrapper_rd_data = 32'h0; // @[quasar_wrapper.scala 94:26] + assign io_lsu_axi_aw_valid = swerv_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_aw_bits_id = swerv_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_aw_bits_addr = swerv_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_aw_bits_region = swerv_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_aw_bits_size = swerv_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_aw_bits_cache = swerv_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_w_valid = swerv_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_w_bits_data = swerv_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_w_bits_strb = swerv_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_w_bits_last = 1'h1; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_b_ready = 1'h1; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_ar_valid = swerv_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_ar_bits_id = swerv_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_ar_bits_addr = swerv_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_ar_bits_region = swerv_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_ar_bits_size = swerv_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_ar_bits_cache = swerv_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 138:20] + assign io_lsu_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 138:20] + assign io_ifu_axi_aw_valid = 1'h0; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_w_valid = 1'h0; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_w_bits_data = 64'h0; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_w_bits_last = 1'h0; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_b_ready = 1'h0; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_ar_valid = swerv_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_ar_bits_id = swerv_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_ar_bits_addr = swerv_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_ar_bits_region = swerv_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_ar_bits_size = 3'h3; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_ar_bits_cache = 4'hf; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 141:20] + assign io_ifu_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 141:20] + assign io_sb_axi_aw_valid = swerv_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_aw_bits_id = 1'h0; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_aw_bits_addr = swerv_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_aw_bits_region = swerv_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_aw_bits_size = swerv_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_aw_bits_cache = 4'hf; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_w_valid = swerv_io_sb_axi_w_valid; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_w_bits_data = swerv_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_w_bits_strb = swerv_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_w_bits_last = 1'h1; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_b_ready = 1'h1; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_ar_valid = swerv_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_ar_bits_id = 1'h0; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_ar_bits_addr = swerv_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_ar_bits_region = swerv_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_ar_bits_size = swerv_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 144:19] + assign io_sb_axi_r_ready = 1'h1; // @[quasar_wrapper.scala 144:19] + assign io_dma_axi_aw_ready = swerv_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 148:20] + assign io_dma_axi_w_ready = swerv_io_dma_axi_w_ready; // @[quasar_wrapper.scala 148:20] + assign io_dma_axi_b_valid = swerv_io_dma_axi_b_valid; // @[quasar_wrapper.scala 148:20] + assign io_dma_axi_b_bits_resp = swerv_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 148:20] + assign io_dma_axi_b_bits_id = 1'h0; // @[quasar_wrapper.scala 148:20] + assign io_dma_axi_ar_ready = swerv_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 148:20] + assign io_dma_axi_r_valid = swerv_io_dma_axi_r_valid; // @[quasar_wrapper.scala 148:20] + assign io_dma_axi_r_bits_id = 1'h0; // @[quasar_wrapper.scala 148:20] + assign io_dma_axi_r_bits_data = swerv_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 148:20] + assign io_dma_axi_r_bits_resp = swerv_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 148:20] + assign io_dma_axi_r_bits_last = 1'h1; // @[quasar_wrapper.scala 148:20] + assign io_dma_hrdata = swerv_io_dma_hrdata; // @[quasar_wrapper.scala 211:17] + assign io_dma_hreadyout = swerv_io_dma_hreadyout; // @[quasar_wrapper.scala 212:20] + assign io_dma_hresp = swerv_io_dma_hresp; // @[quasar_wrapper.scala 213:16] + assign io_dec_tlu_perfcnt0 = swerv_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 201:23] + assign io_dec_tlu_perfcnt1 = swerv_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 202:23] + assign io_dec_tlu_perfcnt2 = swerv_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 203:23] + assign io_dec_tlu_perfcnt3 = swerv_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 204:23] + assign io_jtag_tdo = dmi_wrapper_tdo; // @[quasar_wrapper.scala 96:15] + assign io_mpc_debug_halt_ack = swerv_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 197:25] + assign io_mpc_debug_run_ack = swerv_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 198:24] + assign io_debug_brkpt_status = swerv_io_debug_brkpt_status; // @[quasar_wrapper.scala 199:25] + assign io_o_cpu_halt_ack = swerv_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 192:21] + assign io_o_cpu_halt_status = swerv_io_o_cpu_halt_status; // @[quasar_wrapper.scala 193:24] + assign io_o_debug_mode_status = swerv_io_o_debug_mode_status; // @[quasar_wrapper.scala 195:26] + assign io_o_cpu_run_ack = swerv_io_o_cpu_run_ack; // @[quasar_wrapper.scala 194:20] + assign io_rv_trace_pkt_rv_i_valid_ip = swerv_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 189:19] + assign io_rv_trace_pkt_rv_i_insn_ip = swerv_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 189:19] + assign io_rv_trace_pkt_rv_i_address_ip = swerv_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 189:19] + assign io_rv_trace_pkt_rv_i_exception_ip = swerv_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 189:19] + assign io_rv_trace_pkt_rv_i_ecause_ip = swerv_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 189:19] + assign io_rv_trace_pkt_rv_i_interrupt_ip = swerv_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 189:19] + assign io_rv_trace_pkt_rv_i_tval_ip = swerv_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 189:19] + assign mem_clk = clock; // @[quasar_wrapper.scala 104:14] + assign mem_rst_l = reset; // @[quasar_wrapper.scala 103:16] + assign mem_dccm_clk_override = swerv_io_dccm_clk_override; // @[quasar_wrapper.scala 99:28] + assign mem_icm_clk_override = swerv_io_icm_clk_override; // @[quasar_wrapper.scala 100:27] + assign mem_dec_tlu_core_ecc_disable = swerv_io_dec_tlu_core_ecc_disable; // @[quasar_wrapper.scala 101:35] + assign mem_dccm_wren = swerv_io_dccm_wren; // @[quasar_wrapper.scala 102:15] + assign mem_dccm_rden = swerv_io_dccm_rden; // @[quasar_wrapper.scala 102:15] + assign mem_dccm_wr_addr_lo = swerv_io_dccm_wr_addr_lo; // @[quasar_wrapper.scala 102:15] + assign mem_dccm_wr_addr_hi = swerv_io_dccm_wr_addr_hi; // @[quasar_wrapper.scala 102:15] + assign mem_dccm_rd_addr_lo = swerv_io_dccm_rd_addr_lo; // @[quasar_wrapper.scala 102:15] + assign mem_dccm_rd_addr_hi = swerv_io_dccm_rd_addr_hi; // @[quasar_wrapper.scala 102:15] + assign mem_dccm_wr_data_lo = swerv_io_dccm_wr_data_lo; // @[quasar_wrapper.scala 102:15] + assign mem_dccm_wr_data_hi = swerv_io_dccm_wr_data_hi; // @[quasar_wrapper.scala 102:15] + assign mem_iccm_rw_addr = swerv_io_iccm_rw_addr; // @[quasar_wrapper.scala 109:17] + assign mem_iccm_buf_correct_ecc = swerv_io_iccm_buf_correct_ecc; // @[quasar_wrapper.scala 109:17] + assign mem_iccm_correction_state = swerv_io_iccm_correction_state; // @[quasar_wrapper.scala 109:17] + assign mem_iccm_wren = swerv_io_iccm_wren; // @[quasar_wrapper.scala 109:17] + assign mem_iccm_rden = swerv_io_iccm_rden; // @[quasar_wrapper.scala 109:17] + assign mem_iccm_wr_size = swerv_io_iccm_wr_size; // @[quasar_wrapper.scala 109:17] + assign mem_iccm_wr_data = swerv_io_iccm_wr_data; // @[quasar_wrapper.scala 109:17] + assign mem_ic_rw_addr = swerv_io_ic_rw_addr; // @[quasar_wrapper.scala 108:15] + assign mem_ic_tag_valid = swerv_io_ic_tag_valid; // @[quasar_wrapper.scala 108:15] + assign mem_ic_wr_en = swerv_io_ic_wr_en; // @[quasar_wrapper.scala 108:15] + assign mem_ic_rd_en = swerv_io_ic_rd_en; // @[quasar_wrapper.scala 108:15] + assign mem_ic_wr_data_0 = swerv_io_ic_wr_data_0; // @[quasar_wrapper.scala 108:15] + assign mem_ic_wr_data_1 = swerv_io_ic_wr_data_1; // @[quasar_wrapper.scala 108:15] + assign mem_ic_debug_wr_data = swerv_io_ic_debug_wr_data; // @[quasar_wrapper.scala 108:15] + assign mem_ic_debug_addr = swerv_io_ic_debug_addr; // @[quasar_wrapper.scala 108:15] + assign mem_ic_debug_rd_en = swerv_io_ic_debug_rd_en; // @[quasar_wrapper.scala 108:15] + assign mem_ic_debug_wr_en = swerv_io_ic_debug_wr_en; // @[quasar_wrapper.scala 108:15] + assign mem_ic_debug_tag_array = swerv_io_ic_debug_tag_array; // @[quasar_wrapper.scala 108:15] + assign mem_ic_debug_way = swerv_io_ic_debug_way; // @[quasar_wrapper.scala 108:15] + assign mem_ic_premux_data = swerv_io_ic_premux_data; // @[quasar_wrapper.scala 108:15] + assign mem_ic_sel_premux_data = swerv_io_ic_sel_premux_data; // @[quasar_wrapper.scala 108:15] + assign mem_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 105:20] + assign dmi_wrapper_trst_n = io_jtag_trst_n; // @[quasar_wrapper.scala 81:25] + assign dmi_wrapper_tck = io_jtag_tck; // @[quasar_wrapper.scala 82:22] + assign dmi_wrapper_tms = io_jtag_tms; // @[quasar_wrapper.scala 83:22] + assign dmi_wrapper_tdi = io_jtag_tdi; // @[quasar_wrapper.scala 84:22] + assign dmi_wrapper_core_rst_n = io_dbg_rst_l; // @[quasar_wrapper.scala 90:29] + assign dmi_wrapper_core_clk = clock; // @[quasar_wrapper.scala 85:27] + assign dmi_wrapper_jtag_id = io_jtag_id; // @[quasar_wrapper.scala 86:26] + assign dmi_wrapper_rd_data = 32'h0; // @[quasar_wrapper.scala 87:26] assign swerv_clock = clock; assign swerv_reset = reset; - assign swerv_io_lsu_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar_wrapper.scala 145:20] - assign swerv_io_lsu_axi_w_ready = io_lsu_axi_w_ready; // @[quasar_wrapper.scala 145:20] - assign swerv_io_lsu_axi_b_valid = io_lsu_axi_b_valid; // @[quasar_wrapper.scala 145:20] - assign swerv_io_lsu_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar_wrapper.scala 145:20] - assign swerv_io_lsu_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar_wrapper.scala 145:20] - assign swerv_io_lsu_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar_wrapper.scala 145:20] - assign swerv_io_lsu_axi_r_valid = io_lsu_axi_r_valid; // @[quasar_wrapper.scala 145:20] - assign swerv_io_lsu_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar_wrapper.scala 145:20] - assign swerv_io_lsu_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar_wrapper.scala 145:20] - assign swerv_io_lsu_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar_wrapper.scala 145:20] - assign swerv_io_ifu_axi_ar_ready = io_ifu_axi_ar_ready; // @[quasar_wrapper.scala 148:20] - assign swerv_io_ifu_axi_r_valid = io_ifu_axi_r_valid; // @[quasar_wrapper.scala 148:20] - assign swerv_io_ifu_axi_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar_wrapper.scala 148:20] - assign swerv_io_ifu_axi_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar_wrapper.scala 148:20] - assign swerv_io_ifu_axi_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar_wrapper.scala 148:20] - assign swerv_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar_wrapper.scala 151:19] - assign swerv_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar_wrapper.scala 151:19] - assign swerv_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar_wrapper.scala 151:19] - assign swerv_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar_wrapper.scala 151:19] - assign swerv_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar_wrapper.scala 151:19] - assign swerv_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar_wrapper.scala 151:19] - assign swerv_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar_wrapper.scala 151:19] - assign swerv_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar_wrapper.scala 151:19] - assign swerv_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar_wrapper.scala 155:20] - assign swerv_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar_wrapper.scala 155:20] - assign swerv_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar_wrapper.scala 155:20] - assign swerv_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar_wrapper.scala 155:20] - assign swerv_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar_wrapper.scala 155:20] - assign swerv_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar_wrapper.scala 155:20] - assign swerv_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar_wrapper.scala 155:20] - assign swerv_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar_wrapper.scala 155:20] - assign swerv_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar_wrapper.scala 155:20] - assign swerv_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar_wrapper.scala 155:20] - assign swerv_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar_wrapper.scala 155:20] - assign swerv_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar_wrapper.scala 155:20] - assign swerv_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar_wrapper.scala 155:20] - assign swerv_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 114:22 quasar_wrapper.scala 128:22] - assign swerv_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 129:20] - assign swerv_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 130:20] - assign swerv_io_nmi_vec = io_nmi_vec; // @[quasar_wrapper.scala 131:20] - assign swerv_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar_wrapper.scala 134:27] - assign swerv_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar_wrapper.scala 135:26] - assign swerv_io_core_id = io_core_id; // @[quasar_wrapper.scala 136:20] - assign swerv_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar_wrapper.scala 139:31] - assign swerv_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar_wrapper.scala 140:30] - assign swerv_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar_wrapper.scala 141:30] - assign swerv_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 109:15] - assign swerv_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 109:15] - assign swerv_io_ic_rd_data = mem_ic_rd_data; // @[quasar_wrapper.scala 115:15] - assign swerv_io_ic_debug_rd_data = mem_ic_debug_rd_data; // @[quasar_wrapper.scala 115:15] - assign swerv_io_ic_tag_debug_rd_data = mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 115:15] - assign swerv_io_ic_eccerr = mem_ic_eccerr; // @[quasar_wrapper.scala 115:15] - assign swerv_io_ic_rd_hit = mem_ic_rd_hit; // @[quasar_wrapper.scala 115:15] - assign swerv_io_ic_tag_perr = mem_ic_tag_perr; // @[quasar_wrapper.scala 115:15] - assign swerv_io_iccm_rd_data = mem_iccm_rd_data; // @[quasar_wrapper.scala 116:17] - assign swerv_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 116:17] - assign swerv_io_dma_hsel = io_dma_hsel; // @[quasar_wrapper.scala 158:21] - assign swerv_io_dma_haddr = io_dma_haddr; // @[quasar_wrapper.scala 159:22] - assign swerv_io_dma_hsize = io_dma_hsize; // @[quasar_wrapper.scala 163:22] - assign swerv_io_dma_htrans = io_dma_htrans; // @[quasar_wrapper.scala 164:23] - assign swerv_io_dma_hwrite = io_dma_hwrite; // @[quasar_wrapper.scala 165:23] - assign swerv_io_dma_hreadyin = io_dma_hreadyin; // @[quasar_wrapper.scala 167:25] - assign swerv_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar_wrapper.scala 185:27] - assign swerv_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar_wrapper.scala 186:27] - assign swerv_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar_wrapper.scala 187:27] - assign swerv_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar_wrapper.scala 188:27] - assign swerv_io_dmi_reg_en = dmi_wrapper_reg_en; // @[quasar_wrapper.scala 100:23] - assign swerv_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 99:25] - assign swerv_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 101:26] - assign swerv_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 98:26] - assign swerv_io_extintsrc_req = io_extintsrc_req; // @[quasar_wrapper.scala 192:26] - assign swerv_io_timer_int = io_timer_int; // @[quasar_wrapper.scala 190:22] - assign swerv_io_soft_int = io_soft_int; // @[quasar_wrapper.scala 191:21] - assign swerv_io_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 126:22] + assign swerv_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar_wrapper.scala 148:20] + assign swerv_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 107:22 quasar_wrapper.scala 121:22] + assign swerv_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 122:20] + assign swerv_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 123:20] + assign swerv_io_nmi_vec = io_nmi_vec; // @[quasar_wrapper.scala 124:20] + assign swerv_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar_wrapper.scala 127:27] + assign swerv_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar_wrapper.scala 128:26] + assign swerv_io_core_id = io_core_id; // @[quasar_wrapper.scala 129:20] + assign swerv_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar_wrapper.scala 132:31] + assign swerv_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar_wrapper.scala 133:30] + assign swerv_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar_wrapper.scala 134:30] + assign swerv_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 102:15] + assign swerv_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 102:15] + assign swerv_io_ic_rd_data = mem_ic_rd_data; // @[quasar_wrapper.scala 108:15] + assign swerv_io_ic_debug_rd_data = mem_ic_debug_rd_data; // @[quasar_wrapper.scala 108:15] + assign swerv_io_ic_tag_debug_rd_data = mem_ic_tag_debug_rd_data; // @[quasar_wrapper.scala 108:15] + assign swerv_io_ic_eccerr = mem_ic_eccerr; // @[quasar_wrapper.scala 108:15] + assign swerv_io_ic_rd_hit = mem_ic_rd_hit; // @[quasar_wrapper.scala 108:15] + assign swerv_io_ic_tag_perr = mem_ic_tag_perr; // @[quasar_wrapper.scala 108:15] + assign swerv_io_iccm_rd_data = mem_iccm_rd_data; // @[quasar_wrapper.scala 109:17] + assign swerv_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 109:17] + assign swerv_io_dma_hsel = io_dma_hsel; // @[quasar_wrapper.scala 151:21] + assign swerv_io_dma_haddr = io_dma_haddr; // @[quasar_wrapper.scala 152:22] + assign swerv_io_dma_hsize = io_dma_hsize; // @[quasar_wrapper.scala 156:22] + assign swerv_io_dma_htrans = io_dma_htrans; // @[quasar_wrapper.scala 157:23] + assign swerv_io_dma_hwrite = io_dma_hwrite; // @[quasar_wrapper.scala 158:23] + assign swerv_io_dma_hwdata = io_dma_hwdata; // @[quasar_wrapper.scala 159:23] + assign swerv_io_dma_hreadyin = io_dma_hreadyin; // @[quasar_wrapper.scala 160:25] + assign swerv_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar_wrapper.scala 178:27] + assign swerv_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar_wrapper.scala 179:27] + assign swerv_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar_wrapper.scala 180:27] + assign swerv_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar_wrapper.scala 181:27] + assign swerv_io_dmi_reg_en = dmi_wrapper_reg_en; // @[quasar_wrapper.scala 93:23] + assign swerv_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 92:25] + assign swerv_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 94:26] + assign swerv_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 91:26] + assign swerv_io_extintsrc_req = io_extintsrc_req; // @[quasar_wrapper.scala 185:26] + assign swerv_io_timer_int = io_timer_int; // @[quasar_wrapper.scala 183:22] + assign swerv_io_soft_int = io_soft_int; // @[quasar_wrapper.scala 184:21] + assign swerv_io_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 119:22] endmodule diff --git a/src/main/scala/dec/dec.scala b/src/main/scala/dec/dec.scala index 6e89b36b..211d38bc 100644 --- a/src/main/scala/dec/dec.scala +++ b/src/main/scala/dec/dec.scala @@ -32,10 +32,7 @@ class dec_IO extends Bundle with lib { val mpc_debug_run_ack = Output(Bool()) // Run ack val debug_brkpt_status = Output(Bool()) // debug breakpoint val lsu_pmu_misaligned_m = Input(Bool()) // D side load or store misaligned - val dma_pmu_dccm_read = Input(Bool()) // DMA DCCM read - val dma_pmu_dccm_write = Input(Bool()) // DMA DCCM write - val dma_pmu_any_read = Input(Bool()) // DMA read - val dma_pmu_any_write = Input(Bool()) // DMA write + val lsu_fir_addr = Input(UInt(31.W)) //[31:1] Fast int address val lsu_fir_error = Input(UInt(2.W)) //[1:0] Fast int lookup error @@ -51,22 +48,15 @@ class dec_IO extends Bundle with lib { val lsu_load_stall_any = Input(Bool()) // This is for blocking loads val lsu_store_stall_any = Input(Bool()) // This is for blocking stores - val dma_dccm_stall_any = Input(Bool()) // stall any load/store at decode, pmu event - val dma_iccm_stall_any = Input(Bool()) // iccm stalled, pmu event + val iccm_dma_sb_error = Input(Bool()) // ICCM DMA single bit error val exu_flush_final = Input(Bool()) // slot0 flush - val mexintpend = Input(Bool()) // External interrupt pending val timer_int = Input(Bool()) // Timer interrupt pending (from pin) val soft_int = Input(Bool()) // Software interrupt pending (from pin) - val pic_claimid = Input(UInt(8.W)) // PIC claimid - val pic_pl = Input(UInt(4.W)) // PIC priv level - val mhwakeup = Input(Bool()) // High priority wakeup - val dec_tlu_meicurpl = Output(UInt(4.W)) // to PIC, Current priv level - val dec_tlu_meipt = Output(UInt(4.W)) // to PIC // Debug start val dbg_halt_req = Input(Bool()) // DM requests a halt @@ -90,8 +80,7 @@ class dec_IO extends Bundle with lib { val dec_tlu_perfcnt2 = Output(Bool()) // toggles when slot0 perf counter 2 has an event inc val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc val dec_lsu_valid_raw_d = Output(Bool()) - val rv_trace_pkt = Output(new trace_pkt_t) // trace packet - val dec_tlu_dma_qos_prty = Output(UInt(3.W)) // DMA QoS priority coming from MFDC [18:16] + val rv_trace_pkt = (new trace_pkt_t) // trace packet // clock gating overrides from mcgc val dec_tlu_misc_clk_override = Output(Bool()) // override misc clock domain gating @@ -108,6 +97,8 @@ class dec_IO extends Bundle with lib { val lsu_dec = Flipped (new lsu_dec) val lsu_tlu = Flipped (new lsu_tlu) val dec_dbg = new dec_dbg + val dec_dma = new dec_dma + val dec_pic = new dec_pic } class dec extends Module with param with RequireAsyncReset{ val io = IO(new dec_IO) @@ -140,9 +131,11 @@ class dec extends Module with param with RequireAsyncReset{ val dec_i0_trigger_match_d = dec_trigger.io.dec_i0_trigger_match_d dontTouch(dec_i0_trigger_match_d) decode.io.dec_aln <> io.ifu_dec.dec_aln.aln_dec + decode.io.decode_exu<> io.dec_exu.decode_exu decode.io.dec_alu<> io.dec_exu.dec_alu decode.io.dec_div<> io.dec_exu.dec_div + decode.io.dctl_dma <> io.dec_dma.dctl_dma decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint decode.io.dec_tlu_force_halt := tlu.io.tlu_mem.dec_tlu_force_halt decode.io.dctl_busbuff <> io.lsu_dec.dctl_busbuff @@ -167,10 +160,9 @@ class dec extends Module with param with RequireAsyncReset{ decode.io.lsu_idle_any := io.lsu_idle_any decode.io.lsu_load_stall_any := io.lsu_load_stall_any decode.io.lsu_store_stall_any := io.lsu_store_stall_any - decode.io.dma_dccm_stall_any := io.dma_dccm_stall_any decode.io.exu_div_wren := io.exu_div_wren decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb - decode.io.dec_tlu_flush_lower_wb := tlu.io.tlu_bp.dec_tlu_flush_lower_wb + decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb decode.io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r decode.io.dec_tlu_flush_lower_r := tlu.io.tlu_exu.dec_tlu_flush_lower_r decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r @@ -211,6 +203,7 @@ class dec extends Module with param with RequireAsyncReset{ tlu.io.tlu_ifc <> io.ifu_dec.dec_ifc tlu.io.tlu_bp <> io.ifu_dec.dec_bp tlu.io.tlu_exu <> io.dec_exu.tlu_exu + tlu.io.tlu_dma <> io.dec_dma.tlu_dma tlu.io.active_clk := io.active_clk tlu.io.free_clk := io.free_clk tlu.io.scan_mode := io.scan_mode @@ -226,14 +219,9 @@ class dec extends Module with param with RequireAsyncReset{ tlu.io.dec_pmu_presync_stall := decode.io.dec_pmu_presync_stall tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_postsync_stall tlu.io.lsu_store_stall_any := io.lsu_store_stall_any - tlu.io.dma_dccm_stall_any := io.dma_dccm_stall_any - tlu.io.dma_iccm_stall_any := io.dma_iccm_stall_any io.lsu_dec.tlu_busbuff <> tlu.io.tlu_busbuff io.lsu_tlu <> tlu.io.lsu_tlu - tlu.io.dma_pmu_dccm_read := io.dma_pmu_dccm_read - tlu.io.dma_pmu_dccm_write := io.dma_pmu_dccm_write - tlu.io.dma_pmu_any_read := io.dma_pmu_any_read - tlu.io.dma_pmu_any_write := io.dma_pmu_any_write + io.dec_pic <> tlu.io.dec_pic tlu.io.lsu_fir_addr := io.lsu_fir_addr tlu.io.lsu_fir_error := io.lsu_fir_error tlu.io.iccm_dma_sb_error := io.iccm_dma_sb_error @@ -257,10 +245,10 @@ class dec extends Module with param with RequireAsyncReset{ tlu.io.dbg_resume_req := io.dbg_resume_req tlu.io.lsu_idle_any := io.lsu_idle_any tlu.io.dec_div_active := decode.io.dec_div_active - tlu.io.pic_claimid := io.pic_claimid - tlu.io.pic_pl := io.pic_pl - tlu.io.mhwakeup := io.mhwakeup - tlu.io.mexintpend := io.mexintpend +// tlu.io.pic_claimid := io.dec_pic.pic_claimid +// tlu.io.pic_pl := io.dec_pic.pic_pl +// tlu.io.mhwakeup := io.dec_pic.mhwakeup +// tlu.io.mexintpend := io.mexintpend tlu.io.timer_int := io.timer_int tlu.io.soft_int := io.soft_int tlu.io.core_id := io.core_id @@ -281,8 +269,8 @@ class dec extends Module with param with RequireAsyncReset{ io.mpc_debug_halt_ack := tlu.io.mpc_debug_halt_ack io.mpc_debug_run_ack := tlu.io.mpc_debug_run_ack io.debug_brkpt_status := tlu.io.debug_brkpt_status - io.dec_tlu_meicurpl := tlu.io.dec_tlu_meicurpl - io.dec_tlu_meipt := tlu.io.dec_tlu_meipt +// io.dec_pic.dec_tlu_meicurpl := tlu.io.dec_tlu_meicurpl +// io.dec_pic.dec_tlu_meipt := tlu.io.dec_tlu_meipt io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r io.dec_tlu_perfcnt0 := tlu.io.dec_tlu_perfcnt0 io.dec_tlu_perfcnt1 := tlu.io.dec_tlu_perfcnt1 @@ -293,7 +281,6 @@ class dec extends Module with param with RequireAsyncReset{ dec_tlu_int_valid_wb1 := tlu.io.dec_tlu_int_valid_wb1 dec_tlu_exc_cause_wb1 := tlu.io.dec_tlu_exc_cause_wb1 dec_tlu_mtval_wb1 := tlu.io.dec_tlu_mtval_wb1 - io.dec_tlu_dma_qos_prty := tlu.io.dec_tlu_dma_qos_prty io.dec_tlu_misc_clk_override := tlu.io.dec_tlu_misc_clk_override io.dec_tlu_ifu_clk_override := tlu.io.dec_tlu_ifu_clk_override io.dec_tlu_lsu_clk_override := tlu.io.dec_tlu_lsu_clk_override @@ -315,4 +302,8 @@ class dec extends Module with param with RequireAsyncReset{ // debug command read data io.dec_dbg_rddata := decode.io.dec_i0_wdata_r +} + +object dec_main extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new dec())) } \ No newline at end of file diff --git a/src/main/scala/dec/dec_decode_ctl.scala b/src/main/scala/dec/dec_decode_ctl.scala index 0a369303..b4ec20b6 100644 --- a/src/main/scala/dec/dec_decode_ctl.scala +++ b/src/main/scala/dec/dec_decode_ctl.scala @@ -14,6 +14,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{ val dec_alu = Flipped(new dec_alu) val dec_div = Flipped(new dec_div) val dctl_busbuff = Flipped(new dctl_busbuff()) + val dctl_dma = new dctl_dma val dec_tlu_flush_extint = Input(Bool()) val dec_tlu_force_halt = Input(Bool()) // invalidate nonblock load cam on a force halt event val dec_i0_inst_wb1 = Output(UInt(32.W)) // 32b instruction at wb+1 for trace encoder @@ -38,7 +39,6 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{ val lsu_idle_any = Input(Bool()) // lsu idle: if fence instr & !!!!!!!!!!!!!!!!!!!!!!!!!lsu_idle then stall decode val lsu_load_stall_any = Input(Bool()) // stall any load at decode val lsu_store_stall_any = Input(Bool()) // stall any store at decode6 - val dma_dccm_stall_any = Input(Bool()) // stall any load/store at decode val exu_div_wren = Input(Bool()) // nonblocking divide write enable to GPR. val dec_tlu_i0_kill_writeb_wb = Input(Bool()) // I0 is flushed, don't writeback any results to arch state val dec_tlu_flush_lower_wb = Input(Bool()) // trap lower flush @@ -513,8 +513,8 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{ ((i0_dp.fence | debug_fence) & !lsu_idle) | i0_nonblock_load_stall | i0_load_block_d | i0_nonblock_div_stall | i0_div_prior_div_stall - val i0_store_stall_d = i0_dp.store & (io.lsu_store_stall_any | io.dma_dccm_stall_any) - val i0_load_stall_d = i0_dp.load & (io.lsu_load_stall_any | io.dma_dccm_stall_any) + val i0_store_stall_d = i0_dp.store & (io.lsu_store_stall_any | io.dctl_dma.dma_dccm_stall_any) + val i0_load_stall_d = i0_dp.load & (io.lsu_load_stall_any | io.dctl_dma.dma_dccm_stall_any) val i0_block_d = i0_block_raw_d | i0_store_stall_d | i0_load_stall_d val i0_exublock_d = i0_block_raw_d @@ -784,7 +784,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{ i0_rs2bypass(0).asBool -> i0_result_r, (!i0_rs2bypass(1) & !i0_rs2bypass(0) & i0_rs2_nonblock_load_bypass_en_d).asBool -> io.dctl_busbuff.lsu_nonblock_load_data, )) - io.dec_lsu_valid_raw_d := ((io.dec_ib0_valid_d & (i0_dp_raw.load | i0_dp_raw.store) & !io.dma_dccm_stall_any & !i0_block_raw_d) | io.decode_exu.dec_extint_stall) + io.dec_lsu_valid_raw_d := ((io.dec_ib0_valid_d & (i0_dp_raw.load | i0_dp_raw.store) & !io.dctl_dma.dma_dccm_stall_any & !i0_block_raw_d) | io.decode_exu.dec_extint_stall) io.dec_lsu_offset_d := Mux1H(Seq( (!io.decode_exu.dec_extint_stall & i0_dp.lsu & i0_dp.load).asBool -> i0(31,20), (!io.decode_exu.dec_extint_stall & i0_dp.lsu & i0_dp.store).asBool -> Cat(i0(31,25),i0(11,7)))) diff --git a/src/main/scala/dec/dec_tlu_ctl.scala b/src/main/scala/dec/dec_tlu_ctl.scala index 0fd6c3cb..887589a4 100644 --- a/src/main/scala/dec/dec_tlu_ctl.scala +++ b/src/main/scala/dec/dec_tlu_ctl.scala @@ -44,6 +44,7 @@ trait CSR_VAL { class dec_tlu_ctl_IO extends Bundle with lib { val tlu_exu = Flipped(new tlu_exu) + val tlu_dma = new tlu_dma val active_clk = Input(Clock()) val free_clk = Input(Clock()) val scan_mode = Input(Bool()) @@ -60,12 +61,6 @@ class dec_tlu_ctl_IO extends Bundle with lib { val dec_pmu_presync_stall = Input(UInt(1.W))// decode stall due to presync'd inst val dec_pmu_postsync_stall = Input(UInt(1.W))// decode stall due to postsync'd inst val lsu_store_stall_any = Input(UInt(1.W))// SB or WB is full, stall decode - val dma_dccm_stall_any = Input(UInt(1.W))// DMA stall of lsu - val dma_iccm_stall_any = Input(UInt(1.W))// DMA stall of ifu - val dma_pmu_dccm_read = Input(UInt(1.W)) // DMA DCCM read - val dma_pmu_dccm_write = Input(UInt(1.W)) // DMA DCCM write - val dma_pmu_any_read = Input(UInt(1.W)) // DMA read - val dma_pmu_any_write = Input(UInt(1.W)) // DMA write val lsu_fir_addr = Input(UInt(31.W)) // Fast int address val lsu_fir_error = Input(UInt(2.W)) // Fast int lookup error val iccm_dma_sb_error = Input(UInt(1.W)) // I side dma single bit error @@ -99,10 +94,10 @@ class dec_tlu_ctl_IO extends Bundle with lib { val dbg_resume_req = Input(UInt(1.W)) // DM requests a resume val dec_div_active = Input(UInt(1.W)) // oop div is active val trigger_pkt_any = Output(Vec(4,new trigger_pkt_t))// trigger info for trigger blocks - val pic_claimid = Input(UInt(8.W)) // pic claimid for csr - val pic_pl = Input(UInt(4.W)) // pic priv level for csr - val mhwakeup = Input(UInt(1.W)) // high priority external int, wakeup if halted - val mexintpend= Input(UInt(1.W)) // external interrupt pending +// val pic_claimid = Input(UInt(8.W)) // pic claimid for csr +// val pic_pl = Input(UInt(4.W)) // pic priv level for csr +// val mhwakeup = Input(UInt(1.W)) // high priority external int, wakeup if halted +// val mexintpend= Input(UInt(1.W)) // external interrupt pending val timer_int= Input(UInt(1.W)) // timer interrupt pending val soft_int= Input(UInt(1.W)) // software interrupt pending val o_cpu_halt_status = Output(UInt(1.W)) // PMU interface, halted @@ -117,8 +112,8 @@ class dec_tlu_ctl_IO extends Bundle with lib { val mpc_debug_halt_ack = Output(UInt(1.W)) // Halt ack val mpc_debug_run_ack = Output(UInt(1.W)) // Run ack val debug_brkpt_status = Output(UInt(1.W)) // debug breakpoint - val dec_tlu_meicurpl = Output(UInt(4.W)) // to PIC - val dec_tlu_meipt = Output(UInt(4.W)) // to PIC +// val dec_tlu_meicurpl = Output(UInt(4.W)) // to PIC +// val dec_tlu_meipt = Output(UInt(4.W)) // to PIC val dec_csr_rddata_d = Output(UInt(32.W)) // csr read data at wb val dec_csr_legal_d = Output(UInt(1.W)) // csr indicates legal operation val dec_tlu_i0_kill_writeb_wb = Output(UInt(1.W)) // I0 is flushed, don't writeback any results to arch state @@ -137,7 +132,6 @@ class dec_tlu_ctl_IO extends Bundle with lib { val dec_tlu_exc_cause_wb1 = Output(UInt(5.W)) // exception or int cause val dec_tlu_mtval_wb1 = Output(UInt(32.W)) // MTVAL value val dec_tlu_pipelining_disable = Output(UInt(1.W)) // disable pipelining - val dec_tlu_dma_qos_prty = Output(UInt(3.W)) // DMA QoS priority coming from MFDC [18:16] // clock gating overrides from mcgc val dec_tlu_misc_clk_override = Output(UInt(1.W)) // override misc clock domain gating val dec_tlu_dec_clk_override = Output(UInt(1.W)) // override decode clock domain gating @@ -147,12 +141,14 @@ class dec_tlu_ctl_IO extends Bundle with lib { val dec_tlu_pic_clk_override = Output(UInt(1.W)) // override PIC clock domain gating val dec_tlu_dccm_clk_override = Output(UInt(1.W)) // override DCCM clock domain gating val dec_tlu_icm_clk_override = Output(UInt(1.W)) // override ICCM clock domain gating + val dec_tlu_flush_lower_wb = Output(Bool()) val ifu_pmu_instr_aligned = Input(UInt(1.W)) val tlu_bp = Flipped(new dec_bp) val tlu_ifc = Flipped(new dec_ifc) val tlu_mem = Flipped(new dec_mem_ctrl) val tlu_busbuff = Flipped (new tlu_busbuff) val lsu_tlu = Flipped (new lsu_tlu) + val dec_pic = new dec_pic } class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ val io = IO(new dec_tlu_ctl_IO) @@ -445,7 +441,7 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ val dbg_cmd_done_ns = io.dec_tlu_i0_valid_r & io.dec_tlu_dbg_halted // used to hold off commits after an in-pipe debug mode request (triggers, DCSR) - val request_debug_mode_r = (trigger_hit_dmode_r | ebreak_to_debug_mode_r) | (request_debug_mode_r_d1 & ~io.tlu_bp.dec_tlu_flush_lower_wb) + val request_debug_mode_r = (trigger_hit_dmode_r | ebreak_to_debug_mode_r) | (request_debug_mode_r_d1 & ~io.dec_tlu_flush_lower_wb) val request_debug_mode_done = (request_debug_mode_r_d1 | request_debug_mode_done_f) & ~dbg_tlu_halted_f @@ -521,7 +517,7 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ val i0trigger_qual_r = Fill(4,i0_trigger_eval_r) & io.dec_tlu_packet_r.i0trigger(3,0) & i0_iside_trigger_has_pri_r & i0_lsu_trigger_has_pri_r & trigger_enabled // Qual trigger hits - val i0_trigger_r = ~(Fill(4,io.tlu_bp.dec_tlu_flush_lower_wb | io.dec_tlu_dbg_halted)) & i0trigger_qual_r + val i0_trigger_r = ~(Fill(4,io.dec_tlu_flush_lower_wb | io.dec_tlu_dbg_halted)) & i0trigger_qual_r // chaining can mask raw trigger info val i0_trigger_chain_masked_r = Cat(i0_trigger_r(3) & (~mtdata1_t(2)(MTDATA1_CHAIN) | i0_trigger_r(2)), i0_trigger_r(2) & (~mtdata1_t(2)(MTDATA1_CHAIN) | i0_trigger_r(3)), i0_trigger_r(1) & (~mtdata1_t(0)(MTDATA1_CHAIN) | i0_trigger_r(0)), i0_trigger_r(0) & (~mtdata1_t(0)(MTDATA1_CHAIN) | i0_trigger_r(1))) @@ -601,7 +597,7 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ io.o_debug_mode_status := debug_mode_status // high priority interrupts can wakeup from external halt, so can unmasked timer interrupts - i_cpu_run_req_d1 := i_cpu_run_req_d1_raw | ((nmi_int_detected | timer_int_ready | soft_int_ready | int_timer0_int_hold_f | int_timer1_int_hold_f | (io.mhwakeup & mhwakeup_ready)) & io.o_cpu_halt_status & ~i_cpu_halt_req_d1) + i_cpu_run_req_d1 := i_cpu_run_req_d1_raw | ((nmi_int_detected | timer_int_ready | soft_int_ready | int_timer0_int_hold_f | int_timer1_int_hold_f | (io.dec_pic.mhwakeup & mhwakeup_ready)) & io.o_cpu_halt_status & ~i_cpu_halt_req_d1) //-------------------------------------------------------------------------------- //-------------------------------------------------------------------------------- @@ -610,7 +606,7 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ mdseac_locked_f :=withClock(io.free_clk){RegNext(mdseac_locked_ns,0.U)} val lsu_single_ecc_error_r_d1 =withClock(io.free_clk){RegNext(lsu_single_ecc_error_r,0.U)} val lsu_error_pkt_addr_r =io.lsu_error_pkt_r.bits.addr - val lsu_exc_valid_r_raw = io.lsu_error_pkt_r.valid & ~io.tlu_bp.dec_tlu_flush_lower_wb + val lsu_exc_valid_r_raw = io.lsu_error_pkt_r.valid & ~io.dec_tlu_flush_lower_wb lsu_i0_exc_r_raw := io.lsu_error_pkt_r.valid val lsu_i0_exc_r = lsu_i0_exc_r_raw & lsu_exc_valid_r_raw & ~i0_trigger_hit_r & ~rfpc_i0_r val lsu_exc_valid_r = lsu_i0_exc_r @@ -802,8 +798,8 @@ class dec_tlu_ctl extends Module with lib with RequireAsyncReset with CSR_VAL{ val tlu_flush_path_r_d1=withClock(e4e5_int_clk){RegNext(tlu_flush_path_r,0.U)} ///After Combining Code revisit this - io.tlu_bp.dec_tlu_flush_lower_wb := tlu_flush_lower_r_d1 - io.tlu_mem.dec_tlu_flush_lower_wb := io.tlu_bp.dec_tlu_flush_lower_wb + io.dec_tlu_flush_lower_wb := tlu_flush_lower_r_d1 +// io.tlu_mem.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb io.tlu_exu.dec_tlu_flush_lower_r := tlu_flush_lower_r io.tlu_exu.dec_tlu_flush_path_r := tlu_flush_path_r ///After Combining Code revisit this @@ -830,8 +826,8 @@ val csr=Module(new csr_tlu) csr.io.dec_i0_decode_d := io.dec_i0_decode_d csr.io.ifu_ic_debug_rd_data_valid := io.tlu_mem.ifu_ic_debug_rd_data_valid csr.io.ifu_pmu_bus_trxn := io.tlu_mem.ifu_pmu_bus_trxn - csr.io.dma_iccm_stall_any :=io.dma_iccm_stall_any - csr.io.dma_dccm_stall_any :=io.dma_dccm_stall_any + csr.io.dma_iccm_stall_any :=io.tlu_dma.dma_iccm_stall_any + csr.io.dma_dccm_stall_any :=io.tlu_dma.dma_dccm_stall_any csr.io.lsu_store_stall_any :=io.lsu_store_stall_any csr.io.dec_pmu_presync_stall :=io.dec_pmu_presync_stall csr.io.dec_pmu_postsync_stall :=io.dec_pmu_postsync_stall @@ -847,10 +843,10 @@ val csr=Module(new csr_tlu) csr.io.ifu_pmu_ic_hit :=io.tlu_mem.ifu_pmu_ic_hit csr.io.dec_csr_wen_r := io.dec_csr_wen_r csr.io.dec_tlu_dbg_halted := io.dec_tlu_dbg_halted - csr.io.dma_pmu_dccm_write := io.dma_pmu_dccm_write - csr.io.dma_pmu_dccm_read := io.dma_pmu_dccm_read - csr.io.dma_pmu_any_write := io.dma_pmu_any_write - csr.io.dma_pmu_any_read := io.dma_pmu_any_read + csr.io.dma_pmu_dccm_write := io.tlu_dma.dma_pmu_dccm_write + csr.io.dma_pmu_dccm_read := io.tlu_dma.dma_pmu_dccm_read + csr.io.dma_pmu_any_write := io.tlu_dma.dma_pmu_any_write + csr.io.dma_pmu_any_read := io.tlu_dma.dma_pmu_any_read csr.io.lsu_pmu_bus_busy := io.tlu_busbuff.lsu_pmu_bus_busy csr.io.dec_tlu_i0_pc_r := io.dec_tlu_i0_pc_r csr.io.dec_tlu_i0_valid_r := io.dec_tlu_i0_valid_r @@ -862,24 +858,24 @@ val csr=Module(new csr_tlu) csr.io.lsu_pmu_bus_misaligned := io.tlu_busbuff.lsu_pmu_bus_misaligned csr.io.lsu_pmu_bus_trxn := io.tlu_busbuff.lsu_pmu_bus_trxn csr.io.ifu_ic_debug_rd_data := io.tlu_mem.ifu_ic_debug_rd_data - csr.io.pic_pl := io.pic_pl - csr.io.pic_claimid := io.pic_claimid + csr.io.pic_pl := io.dec_pic.pic_pl + csr.io.pic_claimid := io.dec_pic.pic_claimid csr.io.iccm_dma_sb_error := io.iccm_dma_sb_error csr.io.lsu_imprecise_error_addr_any := io.tlu_busbuff.lsu_imprecise_error_addr_any csr.io.lsu_imprecise_error_load_any := io.tlu_busbuff.lsu_imprecise_error_load_any csr.io.lsu_imprecise_error_store_any := io.tlu_busbuff.lsu_imprecise_error_store_any csr.io.dec_illegal_inst := io.dec_illegal_inst csr.io.lsu_error_pkt_r := io.lsu_error_pkt_r - csr.io.mexintpend := io.mexintpend + csr.io.mexintpend := io.dec_pic.mexintpend csr.io.exu_npc_r := io.tlu_exu.exu_npc_r csr.io.mpc_reset_run_req := io.mpc_reset_run_req csr.io.rst_vec := io.rst_vec csr.io.core_id := io.core_id csr.io.dec_timer_rddata_d := dec_timer_rddata_d csr.io.dec_timer_read_d := dec_timer_read_d - io.dec_tlu_meicurpl := csr.io.dec_tlu_meicurpl + io.dec_pic.dec_tlu_meicurpl := csr.io.dec_tlu_meicurpl io.tlu_exu.dec_tlu_meihap := csr.io.dec_tlu_meihap - io.dec_tlu_meipt := csr.io.dec_tlu_meipt + io.dec_pic.dec_tlu_meipt := csr.io.dec_tlu_meipt io.dec_tlu_int_valid_wb1 := csr.io.dec_tlu_int_valid_wb1 io.dec_tlu_i0_exc_valid_wb1 := csr.io.dec_tlu_i0_exc_valid_wb1 io.dec_tlu_i0_valid_wb1 := csr.io.dec_tlu_i0_valid_wb1 @@ -908,10 +904,10 @@ val csr=Module(new csr_tlu) io.tlu_busbuff.dec_tlu_sideeffect_posted_disable := csr.io.dec_tlu_sideeffect_posted_disable io.tlu_mem.dec_tlu_core_ecc_disable := csr.io.dec_tlu_core_ecc_disable io.tlu_busbuff.dec_tlu_external_ldfwd_disable := csr.io.dec_tlu_external_ldfwd_disable - io.dec_tlu_dma_qos_prty := csr.io.dec_tlu_dma_qos_prty + io.tlu_dma.dec_tlu_dma_qos_prty := csr.io.dec_tlu_dma_qos_prty csr.io.dec_illegal_inst := io.dec_illegal_inst csr.io.lsu_error_pkt_r := io.lsu_error_pkt_r - csr.io.mexintpend := io.mexintpend + csr.io.mexintpend := io.dec_pic.mexintpend csr.io.exu_npc_r := io.tlu_exu.exu_npc_r csr.io.mpc_reset_run_req := io.mpc_reset_run_req csr.io.rst_vec := io.rst_vec @@ -2503,7 +2499,7 @@ for(i <- 0 until 4) {io.trigger_pkt_any(i).tdata2 := mtdata2_t(i)} io.csr_pkt.csr_misa.asBool -> 0x40001104.U(32.W), io.csr_pkt.csr_mvendorid.asBool -> 0x00000045.U(32.W), io.csr_pkt.csr_marchid.asBool -> 0x00000010.U(32.W), - io.csr_pkt.csr_mimpid.asBool -> 0x2.U(32.W), + io.csr_pkt.csr_mimpid.asBool -> 0x1.U(32.W), io.csr_pkt.csr_mhartid.asBool -> Cat(io.core_id,0.U(4.W)), io.csr_pkt.csr_mstatus.asBool -> Cat(0.U(19.W), 3.U(2.W), 0.U(3.W), io.mstatus(1), 0.U(3.W), io.mstatus(0), 0.U(3.W)), io.csr_pkt.csr_mtvec.asBool -> Cat(io.mtvec(30,1), 0.U(1.W), io.mtvec(0)), diff --git a/src/main/scala/dma_ctrl.scala b/src/main/scala/dma_ctrl.scala index c00c75cc..6a7ff770 100644 --- a/src/main/scala/dma_ctrl.scala +++ b/src/main/scala/dma_ctrl.scala @@ -18,18 +18,12 @@ class dma_ctrl extends Module with lib with RequireAsyncReset { val dma_dbg_cmd_fail = Output(Bool()) val dbg_dma = new dec_dbg() val dbg_dma_io = new dbg_dma() + val dec_dma = Flipped(new dec_dma()) val iccm_dma_rvalid = Input(Bool()) // iccm data valid for DMA read val iccm_dma_ecc_error = Input(Bool()) // ECC error on DMA read val iccm_dma_rtag = Input(UInt(3.W)) // Tag of the DMA req val iccm_dma_rdata = Input(UInt(64.W)) // iccm data for DMA read - val dma_dccm_stall_any = Output(Bool()) // stall dccm pipe (bubble) so that DMA can proceed val iccm_ready = Input(Bool()) // iccm ready to accept DMA request - val dec_tlu_dma_qos_prty = Input(UInt(3.W)) // DMA QoS priority coming from MFDC [18:15] - // PMU signals - val dma_pmu_dccm_read = Output(Bool()) - val dma_pmu_dccm_write = Output(Bool()) - val dma_pmu_any_read = Output(Bool()) - val dma_pmu_any_write = Output(Bool()) // AXI Write Channels val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG)) val lsu_dma = Flipped(new lsu_dma) @@ -331,16 +325,17 @@ class dma_ctrl extends Module with lib with RequireAsyncReset { // Block the decode if fifo full - io.dma_dccm_stall_any := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & (dma_nack_count >= dma_nack_count_csr) + io.dec_dma.tlu_dma.dma_dccm_stall_any := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & (dma_nack_count >= dma_nack_count_csr) io.ifu_dma.dma_ifc.dma_iccm_stall_any := dma_mem_req & dma_mem_addr_in_iccm & (dma_nack_count >= dma_nack_count_csr); - + io.dec_dma.tlu_dma.dma_iccm_stall_any := io.ifu_dma.dma_ifc.dma_iccm_stall_any + io.dec_dma.dctl_dma.dma_dccm_stall_any := io.dec_dma.tlu_dma.dma_dccm_stall_any // Used to indicate ready to debug fifo_empty := ~(fifo_valid.orR) // Nack counter, stall the lsu pipe if 7 nacks - dma_nack_count_csr := io.dec_tlu_dma_qos_prty + dma_nack_count_csr := io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty val dma_nack_count_d = Mux(dma_nack_count >= dma_nack_count_csr, (Fill(3, !(io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req)) & dma_nack_count(2,0)), Mux((dma_mem_req.asBool & !(io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req)), dma_nack_count(2,0) + 1.U, 0.U)) dma_nack_count := withClock(dma_free_clk) { @@ -363,10 +358,10 @@ class dma_ctrl extends Module with lib with RequireAsyncReset { // PMU outputs - io.dma_pmu_dccm_read := io.lsu_dma.dma_lsc_ctl.dma_dccm_req & !io.lsu_dma.dma_lsc_ctl.dma_mem_write - io.dma_pmu_dccm_write := io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write - io.dma_pmu_any_read := (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & !io.lsu_dma.dma_lsc_ctl.dma_mem_write - io.dma_pmu_any_write := (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & io.lsu_dma.dma_lsc_ctl.dma_mem_write + io.dec_dma.tlu_dma.dma_pmu_dccm_read := io.lsu_dma.dma_lsc_ctl.dma_dccm_req & !io.lsu_dma.dma_lsc_ctl.dma_mem_write + io.dec_dma.tlu_dma.dma_pmu_dccm_write := io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write + io.dec_dma.tlu_dma.dma_pmu_any_read := (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & !io.lsu_dma.dma_lsc_ctl.dma_mem_write + io.dec_dma.tlu_dma.dma_pmu_any_write := (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & io.lsu_dma.dma_lsc_ctl.dma_mem_write // Inputs diff --git a/src/main/scala/ifu/ifu.scala b/src/main/scala/ifu/ifu.scala index 06db2367..cfb1895c 100644 --- a/src/main/scala/ifu/ifu.scala +++ b/src/main/scala/ifu/ifu.scala @@ -30,8 +30,7 @@ class ifu extends Module with lib with RequireAsyncReset { val iccm_ready = Output(Bool()) // Performance counter val iccm_dma_sb_error = Output(Bool()) -// val iccm_buf_correct_ecc = Output(Bool()) - // val iccm_correction_state = Output(Bool()) + val dec_tlu_flush_lower_wb = Input(Bool()) val scan_mode = Input(Bool()) }) val mem_ctl = Module(new ifu_mem_ctl) @@ -87,7 +86,7 @@ class ifu extends Module with lib with RequireAsyncReset { bp_ctl.io.dec_bp <> io.ifu_dec.dec_bp bp_ctl.io.exu_bp <> io.exu_ifu.exu_bp bp_ctl.io.exu_flush_final := io.exu_flush_final - + bp_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb // mem-ctl wiring mem_ctl.io.free_clk := io.free_clk mem_ctl.io.active_clk := io.active_clk @@ -108,6 +107,7 @@ class ifu extends Module with lib with RequireAsyncReset { mem_ctl.io.ic <> io.ic mem_ctl.io.iccm <> io.iccm mem_ctl.io.ifu_fetch_val := mem_ctl.io.ic_fetch_val_f + mem_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb mem_ctl.io.scan_mode := io.scan_mode io.iccm_dma_ecc_error := mem_ctl.io.iccm_dma_ecc_error diff --git a/src/main/scala/ifu/ifu_bp_ctl.scala b/src/main/scala/ifu/ifu_bp_ctl.scala index cf15691a..9e9ff14e 100644 --- a/src/main/scala/ifu/ifu_bp_ctl.scala +++ b/src/main/scala/ifu/ifu_bp_ctl.scala @@ -15,6 +15,7 @@ class ifu_bp_ctl extends Module with lib with RequireAsyncReset { val ifc_fetch_addr_f = Input(UInt(31.W)) val ifc_fetch_req_f = Input(Bool()) // Fetch request generated by the IFC val dec_bp = new dec_bp() + val dec_tlu_flush_lower_wb = Input(Bool()) val exu_bp = Flipped(new exu_bp()) val ifu_bp_hit_taken_f = Output(Bool()) val ifu_bp_btb_target_f = Output(UInt(31.W)) @@ -119,7 +120,7 @@ class ifu_bp_ctl extends Module with lib with RequireAsyncReset { val exu_flush_final_d1 = withClock(io.active_clk) {RegNext(io.exu_flush_final, init = 0.U)} // If there is a flush from the lower pipe wait until the flush gets deasserted from the (decode) side - leak_one_f := (io.dec_bp.dec_tlu_flush_leak_one_wb & io.dec_bp.dec_tlu_flush_lower_wb) | (leak_one_f_d1 & !io.dec_bp.dec_tlu_flush_lower_wb) + leak_one_f := (io.dec_bp.dec_tlu_flush_leak_one_wb & io.dec_tlu_flush_lower_wb) | (leak_one_f_d1 & !io.dec_tlu_flush_lower_wb) // For a tag to match the branch should be valid tag should match and a fetch request should be generated // Also there should be no bank conflict or leak-one diff --git a/src/main/scala/ifu/ifu_mem_ctl.scala b/src/main/scala/ifu/ifu_mem_ctl.scala index 263db522..bd88f99f 100644 --- a/src/main/scala/ifu/ifu_mem_ctl.scala +++ b/src/main/scala/ifu/ifu_mem_ctl.scala @@ -39,7 +39,7 @@ class mem_ctl_io extends Bundle with lib{ val iccm_dma_rtag = Output(UInt(3.W)) val iccm_ready = Output(Bool()) - + val dec_tlu_flush_lower_wb = Input(Bool()) val iccm_rd_ecc_double_err = Output(Bool()) val iccm_dma_sb_error = Output(Bool()) @@ -420,12 +420,12 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { } is(ic_wff_C){ perr_nxtstate := err_idle_C - perr_state_en := io.dec_mem_ctrl.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_force_halt - perr_sel_invalidate := io.dec_mem_ctrl.dec_tlu_flush_lower_wb & io.dec_mem_ctrl.dec_tlu_flush_err_wb + perr_state_en := io.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_force_halt + perr_sel_invalidate := io.dec_tlu_flush_lower_wb & io.dec_mem_ctrl.dec_tlu_flush_err_wb } is(ecc_wff_C){ - perr_nxtstate := Mux(((!io.dec_mem_ctrl.dec_tlu_flush_err_wb & io.dec_mem_ctrl.dec_tlu_flush_lower_wb ) | io.dec_mem_ctrl.dec_tlu_force_halt).asBool(), err_idle_C, ecc_cor_C) - perr_state_en := io.dec_mem_ctrl.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_force_halt + perr_nxtstate := Mux(((!io.dec_mem_ctrl.dec_tlu_flush_err_wb & io.dec_tlu_flush_lower_wb ) | io.dec_mem_ctrl.dec_tlu_force_halt).asBool(), err_idle_C, ecc_cor_C) + perr_state_en := io.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_force_halt } is(dma_sb_err_C){ perr_nxtstate := Mux(io.dec_mem_ctrl.dec_tlu_force_halt, err_idle_C, ecc_cor_C) @@ -447,24 +447,24 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset { err_stop_state_en := io.dec_mem_ctrl.dec_tlu_flush_err_wb & (perr_state === ecc_wff_C) & !io.dec_mem_ctrl.dec_tlu_force_halt } is(err_fetch1_C){ - err_stop_nxtstate := Mux((io.dec_mem_ctrl.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt).asBool(), err_stop_idle_C, + err_stop_nxtstate := Mux((io.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt).asBool(), err_stop_idle_C, Mux(((io.ifu_fetch_val===3.U)|(io.ifu_fetch_val(0)&two_byte_instr)).asBool(), err_stop_fetch_C, Mux(io.ifu_fetch_val(0).asBool(), err_fetch2_C, err_fetch1_C))) - err_stop_state_en := io.dec_mem_ctrl.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.ifu_fetch_val(0) | ifu_bp_hit_taken_q_f | io.dec_mem_ctrl.dec_tlu_force_halt + err_stop_state_en := io.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.ifu_fetch_val(0) | ifu_bp_hit_taken_q_f | io.dec_mem_ctrl.dec_tlu_force_halt err_stop_fetch := ((io.ifu_fetch_val(1,0)===3.U) | (io.ifu_fetch_val(0) & two_byte_instr)) & !(io.exu_flush_final | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt) io.iccm.correction_state := true.B } is(err_fetch2_C){ - err_stop_nxtstate := Mux((io.dec_mem_ctrl.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt).asBool, + err_stop_nxtstate := Mux((io.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt).asBool, err_stop_idle_C, Mux(io.ifu_fetch_val(0).asBool, err_stop_fetch_C, err_fetch2_C)) - err_stop_state_en := io.dec_mem_ctrl.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.ifu_fetch_val(0) | io.dec_mem_ctrl.dec_tlu_force_halt + err_stop_state_en := io.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.ifu_fetch_val(0) | io.dec_mem_ctrl.dec_tlu_force_halt err_stop_fetch := io.ifu_fetch_val(0) & !io.exu_flush_final & !io.dec_mem_ctrl.dec_tlu_i0_commit_cmt io.iccm.correction_state := true.B } is(err_stop_fetch_C){ - err_stop_nxtstate := Mux(((io.dec_mem_ctrl.dec_tlu_flush_lower_wb & !io.dec_mem_ctrl.dec_tlu_flush_err_wb) | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt).asBool, + err_stop_nxtstate := Mux(((io.dec_tlu_flush_lower_wb & !io.dec_mem_ctrl.dec_tlu_flush_err_wb) | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt).asBool, err_stop_idle_C, Mux(io.dec_mem_ctrl.dec_tlu_flush_err_wb.asBool(), err_fetch1_C, err_stop_fetch_C)) - err_stop_state_en := io.dec_mem_ctrl.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt + err_stop_state_en := io.dec_tlu_flush_lower_wb | io.dec_mem_ctrl.dec_tlu_i0_commit_cmt | io.dec_mem_ctrl.dec_tlu_force_halt err_stop_fetch := true.B io.iccm.correction_state := true.B } diff --git a/src/main/scala/include/bundle.scala b/src/main/scala/include/bundle.scala index 1397cbfd..2be96902 100644 --- a/src/main/scala/include/bundle.scala +++ b/src/main/scala/include/bundle.scala @@ -6,9 +6,35 @@ import ifu._ import dec._ import lsu._ import lib._ +class dec_pic extends Bundle{ + val pic_claimid = Input(UInt(8.W)) // PIC claimid + val pic_pl = Input(UInt(4.W)) // PIC priv level + val mhwakeup = Input(Bool()) // High priority wakeup + val dec_tlu_meicurpl = Output(UInt(4.W)) // to PIC, Current priv level + val dec_tlu_meipt = Output(UInt(4.W)) // to PIC + val mexintpend = Input(UInt(1.W)) // external interrupt pending +} + +class dec_dma extends Bundle{ + val dctl_dma = new dctl_dma() + val tlu_dma = new tlu_dma() +} +class dctl_dma extends Bundle{ + val dma_dccm_stall_any = Input(Bool()) // stall any load/store at decode, pmu event +} +class tlu_dma extends Bundle{ + val dma_pmu_dccm_read = Input(Bool()) // DMA DCCM read + val dma_pmu_dccm_write = Input(Bool()) // DMA DCCM write + val dma_pmu_any_read = Input(Bool()) // DMA read + val dma_pmu_any_write = Input(Bool()) // DMA write + val dec_tlu_dma_qos_prty = Output(UInt(3.W)) // DMA QoS priority coming from MFDC [18:16] + val dma_dccm_stall_any = Input(Bool()) // stall any load/store at decode, pmu event + val dma_iccm_stall_any = Input(Bool()) // iccm stalled, pmu event +} + class dec_bp extends Bundle{ val dec_tlu_br0_r_pkt = Flipped(Valid(new br_tlu_pkt_t)) - val dec_tlu_flush_lower_wb = Input(Bool()) +// val dec_tlu_flush_lower_wb = Input(Bool()) val dec_tlu_flush_leak_one_wb = Input(Bool()) val dec_tlu_bpred_disable = Input(Bool()) } @@ -64,22 +90,9 @@ class write_resp(val TAG : Int=3) extends Bundle with lib{ // write_response val resp = UInt(2.W) val id = UInt(TAG.W) } -class ahb_channel extends Bundle with lib{ - val haddr = Output(UInt(32.W)) // [31:0] // ahb bus address - val hburst = Output(UInt(3.W)) // [2:0] // tied to 0 - val hmastlock = Output(Bool()) // tied to 0 - val hprot = Output(UInt(4.W)) // [3:0] // tied to 4'b0011 - val hsize = Output(UInt(3.W)) // [2:0] // size of bus transaction (possible values 0,1,2,3) - val htrans = Output(UInt(2.W)) - val hwrite = Output(Bool()) // ahb bus write - val hwdata = Output(UInt(64.W)) // [63:0] // ahb bus write dat - val hrdata = Input(UInt(64.W)) // [63:0] // ahb bus read data - val hready = Input(Bool()) // slave ready to accept transaction - val hresp = Input(Bool()) // slave response (high indicates erro) -} class dec_mem_ctrl extends Bundle with lib{ - val dec_tlu_flush_lower_wb = Input(Bool()) +// val dec_tlu_flush_lower_wb = Input(Bool()) val dec_tlu_flush_err_wb = Input(Bool()) val dec_tlu_i0_commit_cmt = Input(Bool()) val dec_tlu_force_halt = Input(Bool()) @@ -250,13 +263,13 @@ class dma_ifc extends Bundle{ } class trace_pkt_t extends Bundle{ - val rv_i_valid_ip = UInt(2.W) - val rv_i_insn_ip = UInt(32.W) - val rv_i_address_ip = UInt(32.W) - val rv_i_exception_ip = UInt(2.W) - val rv_i_ecause_ip = UInt(5.W) - val rv_i_interrupt_ip = UInt(2.W) - val rv_i_tval_ip = UInt(32.W) + val rv_i_valid_ip = Output(UInt(2.W) ) + val rv_i_insn_ip = Output(UInt(32.W) ) + val rv_i_address_ip = Output(UInt(32.W) ) + val rv_i_exception_ip = Output(UInt(2.W) ) + val rv_i_ecause_ip = Output(UInt(5.W) ) + val rv_i_interrupt_ip = Output(UInt(2.W) ) + val rv_i_tval_ip = Output(UInt(32.W) ) } diff --git a/src/main/scala/lib/param.scala b/src/main/scala/lib/param.scala index 0917162d..23af6356 100644 --- a/src/main/scala/lib/param.scala +++ b/src/main/scala/lib/param.scala @@ -21,7 +21,7 @@ trait param { val BTB_INDEX3_HI = 0x19 val BTB_INDEX3_LO = 0x12 val BTB_SIZE = 0x200 - val BUILD_AHB_LITE = 0x0 + val BUILD_AHB_LITE = 0x1 val BUILD_AXI4 = 0x1 val BUILD_AXI_NATIVE = 0x1 val BUS_PRTY_DEFAULT = 0x3 diff --git a/src/main/scala/lsu/lsu_bus_buffer.scala b/src/main/scala/lsu/lsu_bus_buffer.scala index 31f6144d..855fdf84 100644 --- a/src/main/scala/lsu/lsu_bus_buffer.scala +++ b/src/main/scala/lsu/lsu_bus_buffer.scala @@ -296,7 +296,6 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib { val obuf_merge_en = WireInit(Bool(), false.B) val obuf_merge_in = obuf_merge_en val obuf_tag0_in = Mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) - //val Cmdptr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U) val obuf_tag1_in = Mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1) val obuf_cmd_done = WireInit(Bool(), false.B) diff --git a/src/main/scala/pic_ctrl.scala b/src/main/scala/pic_ctrl.scala index 424298e6..195085d7 100644 --- a/src/main/scala/pic_ctrl.scala +++ b/src/main/scala/pic_ctrl.scala @@ -13,13 +13,14 @@ class pic_ctrl extends Module with RequireAsyncReset with lib { val clk_override = Input(Bool () ) val extintsrc_req = Input(UInt (PIC_TOTAL_INT_PLUS1.W)) val lsu_pic = Flipped(new lsu_pic()) - val meicurpl = Input(UInt(4.W)) - val meipt = Input(UInt(4.W)) - - val mexintpend = Output(Bool()) - val claimid = Output(UInt(8.W)) - val pl = Output(UInt(4.W)) - val mhwakeup = Output(Bool()) + val dec_pic = Flipped(new dec_pic) +// val dec_tlu_meicurpl = Input(UInt(4.W)) +// val dec_tlu_meipt = Input(UInt(4.W)) +// +// val mexintpend = Output(Bool()) +// val pic_claimid = Output(UInt(8.W)) +// val pic_pl = Output(UInt(4.W)) +// val mhwakeup = Output(Bool()) }) def cmp_and_mux (a_id : UInt, a_priority : UInt, b_id : UInt, b_priority : UInt) = @@ -33,8 +34,8 @@ class pic_ctrl extends Module with RequireAsyncReset with lib { } // io.mexintpend := 0.U - // io.claimid := 0.U - // io.pl := 0.U + // io.pic_claimid := 0.U + // io.pic_pl := 0.U //io.picm_rd_data := 0.U //io.mhwakeup := 0.U @@ -255,18 +256,18 @@ class pic_ctrl extends Module with RequireAsyncReset with lib { val pl_in = selected_int_priority /////////////////////////////////////////////////////////// - /// ClaimId Reg and Corresponding PL + /// pic_claimid Reg and Corresponding pic_pl /////////////////////////////////////////////////////////// val pl_in_q = Mux(intpriord.asBool,~pl_in,pl_in).asUInt - withClock(io.free_clk){io.claimid := RegNext(claimid_in,0.U)} - withClock(io.free_clk){io.pl := RegNext(pl_in_q,0.U)} - val meipt_inv = Mux(intpriord.asBool,~io.meipt,io.meipt) - val meicurpl_inv = Mux(intpriord.asBool,~io.meicurpl,io.meicurpl) + withClock(io.free_clk){io.dec_pic.pic_claimid := RegNext(claimid_in,0.U)} + withClock(io.free_clk){io.dec_pic.pic_pl := RegNext(pl_in_q,0.U)} + val meipt_inv = Mux(intpriord.asBool,~io.dec_pic.dec_tlu_meipt,io.dec_pic.dec_tlu_meipt) + val meicurpl_inv = Mux(intpriord.asBool,~io.dec_pic.dec_tlu_meicurpl,io.dec_pic.dec_tlu_meicurpl) val mexintpend_in = ( selected_int_priority > meipt_inv) & ( selected_int_priority > meicurpl_inv) - io.mexintpend := withClock(io.free_clk){RegNext(mexintpend_in,0.U)} + io.dec_pic.mexintpend := withClock(io.free_clk){RegNext(mexintpend_in,0.U)} val maxint = Mux(intpriord.asBool,0.U,15.U) val mhwakeup_in = pl_in_q === maxint - io.mhwakeup := withClock(io.free_clk){RegNext(mhwakeup_in,0.U)} + io.dec_pic.mhwakeup := withClock(io.free_clk){RegNext(mhwakeup_in,0.U)} ////////////////////////////////////////////////////////////////////////// // Reads of register. diff --git a/src/main/scala/quasar.scala b/src/main/scala/quasar.scala index 240d970f..38816098 100644 --- a/src/main/scala/quasar.scala +++ b/src/main/scala/quasar.scala @@ -19,13 +19,7 @@ class quasar_bundle extends Bundle with lib{ val nmi_int = Input(Bool()) val nmi_vec = Input(UInt(31.W)) val core_rst_l = Output(AsyncReset()) - val trace_rv_i_insn_ip = Output(UInt(32.W)) - val trace_rv_i_address_ip = Output(UInt(32.W)) - val trace_rv_i_valid_ip = Output(UInt(2.W)) - val trace_rv_i_exception_ip = Output(UInt(2.W)) - val trace_rv_i_ecause_ip = Output(UInt(5.W)) - val trace_rv_i_interrupt_ip = Output(UInt(2.W)) - val trace_rv_i_tval_ip = Output(UInt(32.W)) + val rv_trace_pkt = new trace_pkt_t() val dccm_clk_override = Output(Bool()) val icm_clk_override = Output(Bool()) val dec_tlu_core_ecc_disable = Output(Bool()) @@ -153,7 +147,7 @@ class quasar extends Module with RequireAsyncReset with lib { ifu.io.exu_ifu.exu_bp <> exu.io.exu_bp ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r := exu.io.exu_bp.exu_i0_br_fghr_r ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r := exu.io.dec_exu.tlu_exu.exu_i0_br_index_r - ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_flush_lower_wb := dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r + ifu.io.dec_tlu_flush_lower_wb := dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt := dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt // Lets start with Dec @@ -173,10 +167,8 @@ class quasar extends Module with RequireAsyncReset with lib { dec.io.lsu_dec <> lsu.io.lsu_dec dec.io.lsu_tlu <> lsu.io.lsu_tlu dec.io.lsu_pmu_misaligned_m := lsu.io.lsu_pmu_misaligned_m - dec.io.dma_pmu_dccm_read := dma_ctrl.io.dma_pmu_dccm_read - dec.io.dma_pmu_dccm_write := dma_ctrl.io.dma_pmu_dccm_write - dec.io.dma_pmu_any_read := dma_ctrl.io.dma_pmu_any_read - dec.io.dma_pmu_any_write := dma_ctrl.io.dma_pmu_any_write + dec.io.dec_dma <> dma_ctrl.io.dec_dma + dec.io.lsu_fir_addr := lsu.io.lsu_fir_addr dec.io.lsu_fir_error := lsu.io.lsu_fir_error dec.io.lsu_trigger_match_m := lsu.io.lsu_trigger_match_m @@ -190,15 +182,10 @@ class quasar extends Module with RequireAsyncReset with lib { dec.io.lsu_result_corr_r := lsu.io.lsu_result_corr_r dec.io.lsu_load_stall_any := lsu.io.lsu_load_stall_any dec.io.lsu_store_stall_any := lsu.io.lsu_store_stall_any - dec.io.dma_dccm_stall_any := dma_ctrl.io.dma_dccm_stall_any - dec.io.dma_iccm_stall_any := dma_ctrl.io.ifu_dma.dma_ifc.dma_iccm_stall_any dec.io.iccm_dma_sb_error := ifu.io.iccm_dma_sb_error dec.io.exu_flush_final := exu.io.exu_flush_final - dec.io.mexintpend := pic_ctrl_inst.io.mexintpend + dec.io.soft_int := io.soft_int - dec.io.pic_claimid := pic_ctrl_inst.io.claimid - dec.io.pic_pl := pic_ctrl_inst.io.pl - dec.io.mhwakeup := pic_ctrl_inst.io.mhwakeup dec.io.dbg_halt_req := dbg.io.dbg_halt_req dec.io.dbg_resume_req := dbg.io.dbg_resume_req dec.io.exu_i0_br_way_r := exu.io.exu_bp.exu_i0_br_way_r @@ -263,7 +250,6 @@ class quasar extends Module with RequireAsyncReset with lib { dma_ctrl.io.iccm_dma_rtag := ifu.io.iccm_dma_rtag dma_ctrl.io.iccm_dma_rdata := ifu.io.iccm_dma_rdata dma_ctrl.io.iccm_ready := ifu.io.iccm_ready - dma_ctrl.io.dec_tlu_dma_qos_prty := dec.io.dec_tlu_dma_qos_prty dma_ctrl.io.iccm_dma_ecc_error := ifu.io.iccm_dma_ecc_error // PIC lets go @@ -274,16 +260,9 @@ class quasar extends Module with RequireAsyncReset with lib { pic_ctrl_inst.io.clk_override := dec.io.dec_tlu_pic_clk_override pic_ctrl_inst.io.extintsrc_req := io.extintsrc_req pic_ctrl_inst.io.lsu_pic <> lsu.io.lsu_pic - pic_ctrl_inst.io.meicurpl := dec.io.dec_tlu_meicurpl - pic_ctrl_inst.io.meipt := dec.io.dec_tlu_meipt + pic_ctrl_inst.io.dec_pic <> dec.io.dec_pic // Trace Packet - io.trace_rv_i_insn_ip := dec.io.rv_trace_pkt.rv_i_insn_ip - io.trace_rv_i_address_ip := dec.io.rv_trace_pkt.rv_i_address_ip - io.trace_rv_i_valid_ip := dec.io.rv_trace_pkt.rv_i_valid_ip - io.trace_rv_i_exception_ip := dec.io.rv_trace_pkt.rv_i_exception_ip - io.trace_rv_i_ecause_ip := dec.io.rv_trace_pkt.rv_i_ecause_ip - io.trace_rv_i_interrupt_ip := dec.io.rv_trace_pkt.rv_i_interrupt_ip - io.trace_rv_i_tval_ip := dec.io.rv_trace_pkt.rv_i_tval_ip + io.rv_trace_pkt := dec.io.rv_trace_pkt // Outputs io.dccm_clk_override := dec.io.dec_tlu_dccm_clk_override diff --git a/src/main/scala/quasar_wrapper.scala b/src/main/scala/quasar_wrapper.scala index 6e961ef1..0849f34c 100644 --- a/src/main/scala/quasar_wrapper.scala +++ b/src/main/scala/quasar_wrapper.scala @@ -12,14 +12,6 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset { val nmi_vec = Input(UInt(31.W)) val jtag_id = Input(UInt(31.W)) - val trace_rv_i_insn_ip = Output(UInt(32.W)) - val trace_rv_i_address_ip = Output(UInt(32.W)) - val trace_rv_i_valid_ip = Output(UInt(2.W)) - val trace_rv_i_exception_ip = Output(UInt(2.W)) - val trace_rv_i_ecause_ip = Output(UInt(5.W)) - val trace_rv_i_interrupt_ip = Output(UInt(2.W)) - val trace_rv_i_tval_ip = Output(UInt(32.W)) - // AXI Signals val lsu_axi = new axi_channels(LSU_BUS_TAG) val ifu_axi = new axi_channels(IFU_BUS_TAG) @@ -79,6 +71,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset { val o_cpu_run_ack = Output(Bool()) val mbist_mode = Input(Bool()) + val rv_trace_pkt = new trace_pkt_t() val scan_mode = Input(Bool()) }) @@ -193,13 +186,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset { // Outputs val core_rst_l = swerv.io.core_rst_l - io.trace_rv_i_insn_ip := swerv.io.trace_rv_i_insn_ip - io.trace_rv_i_address_ip := swerv.io.trace_rv_i_address_ip - io.trace_rv_i_valid_ip := swerv.io.trace_rv_i_valid_ip - io.trace_rv_i_exception_ip := swerv.io.trace_rv_i_exception_ip - io.trace_rv_i_ecause_ip := swerv.io.trace_rv_i_ecause_ip - io.trace_rv_i_interrupt_ip := swerv.io.trace_rv_i_interrupt_ip - io.trace_rv_i_tval_ip := swerv.io.trace_rv_i_tval_ip + io.rv_trace_pkt := swerv.io.rv_trace_pkt // external halt/run interface io.o_cpu_halt_ack := swerv.io.o_cpu_halt_ack diff --git a/target/scala-2.12/classes/QUASAR_Wrp$.class b/target/scala-2.12/classes/QUASAR_Wrp$.class index 10d3aaf8..56baf53a 100644 Binary files a/target/scala-2.12/classes/QUASAR_Wrp$.class and b/target/scala-2.12/classes/QUASAR_Wrp$.class differ diff --git a/target/scala-2.12/classes/QUASAR_Wrp$delayedInit$body.class b/target/scala-2.12/classes/QUASAR_Wrp$delayedInit$body.class index db602694..35c488d2 100644 Binary files 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