From c87412893834df4ced156da22bd71ef391573c96 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com>
Date: Thu, 7 Jan 2021 12:53:47 +0500
Subject: [PATCH] Divider 5 added

---
 exu_div_new_4bit_fullshortq.anno.json         |   30 +
 exu_div_new_4bit_fullshortq.fir               | 2818 +++++++++++++++++
 exu_div_new_4bit_fullshortq.v                 | 1204 +++++++
 src/main/scala/exu/exu_div_ctl.scala          |  377 +--
 .../exu/div_main4$delayedInit$body.class      |  Bin 744 -> 0 bytes
 .../{div_main4$.class => div_main5$.class}    |  Bin 3905 -> 3906 bytes
 .../exu/div_main5$delayedInit$body.class      |  Bin 0 -> 744 bytes
 .../exu/{div_main4.class => div_main5.class}  |  Bin 787 -> 787 bytes
 .../classes/exu/exu_div_cls$$anon$7.class     |  Bin 1694 -> 1694 bytes
 .../scala-2.12/classes/exu/exu_div_cls.class  |  Bin 11054 -> 11057 bytes
 .../exu_div_existing_1bit_cheapshortq.class   |  Bin 112188 -> 112188 bytes
 .../exu/exu_div_new_1bit_fullshortq.class     |  Bin 104405 -> 104405 bytes
 .../exu/exu_div_new_2bit_fullshortq.class     |  Bin 108459 -> 108459 bytes
 .../exu/exu_div_new_3bit_fullshortq.class     |  Bin 116620 -> 116620 bytes
 .../exu_div_new_4bit_fullshortq$$anon$6.class |  Bin 2817 -> 2817 bytes
 .../exu/exu_div_new_4bit_fullshortq.class     |  Bin 49555 -> 126825 bytes
 16 files changed, 4252 insertions(+), 177 deletions(-)
 create mode 100644 exu_div_new_4bit_fullshortq.anno.json
 create mode 100644 exu_div_new_4bit_fullshortq.fir
 create mode 100644 exu_div_new_4bit_fullshortq.v
 delete mode 100644 target/scala-2.12/classes/exu/div_main4$delayedInit$body.class
 rename target/scala-2.12/classes/exu/{div_main4$.class => div_main5$.class} (73%)
 create mode 100644 target/scala-2.12/classes/exu/div_main5$delayedInit$body.class
 rename target/scala-2.12/classes/exu/{div_main4.class => div_main5.class} (65%)

diff --git a/exu_div_new_4bit_fullshortq.anno.json b/exu_div_new_4bit_fullshortq.anno.json
new file mode 100644
index 00000000..86352af2
--- /dev/null
+++ b/exu_div_new_4bit_fullshortq.anno.json
@@ -0,0 +1,30 @@
+[
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~exu_div_new_4bit_fullshortq|exu_div_new_4bit_fullshortq>io_valid_out",
+    "sources":[
+      "~exu_div_new_4bit_fullshortq|exu_div_new_4bit_fullshortq>io_cancel"
+    ]
+  },
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxResourceAnno",
+    "target":"exu_div_new_4bit_fullshortq.gated_latch",
+    "resourceId":"/vsrc/gated_latch.sv"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"exu_div_new_4bit_fullshortq"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]
\ No newline at end of file
diff --git a/exu_div_new_4bit_fullshortq.fir b/exu_div_new_4bit_fullshortq.fir
new file mode 100644
index 00000000..56a5ece2
--- /dev/null
+++ b/exu_div_new_4bit_fullshortq.fir
@@ -0,0 +1,2818 @@
+;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
+circuit exu_div_new_4bit_fullshortq : 
+  module exu_div_cls : 
+    input clock : Clock
+    input reset : Reset
+    output io : {flip operand : UInt<33>, cls : UInt<5>}
+    
+    wire cls_zeros : UInt<5>
+    cls_zeros <= UInt<5>("h00")
+    wire cls_ones : UInt<5>
+    cls_ones <= UInt<5>("h00")
+    node _T = bits(io.operand, 31, 31) @[exu_div_ctl.scala 958:54]
+    node _T_1 = eq(_T, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_2 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 958:54]
+    node _T_3 = eq(_T_2, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_4 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 958:54]
+    node _T_5 = eq(_T_4, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_6 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 958:54]
+    node _T_7 = eq(_T_6, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_8 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 958:54]
+    node _T_9 = eq(_T_8, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_10 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 958:54]
+    node _T_11 = eq(_T_10, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_12 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 958:54]
+    node _T_13 = eq(_T_12, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_14 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 958:54]
+    node _T_15 = eq(_T_14, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_16 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 958:54]
+    node _T_17 = eq(_T_16, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_18 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 958:54]
+    node _T_19 = eq(_T_18, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_20 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 958:54]
+    node _T_21 = eq(_T_20, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_22 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 958:54]
+    node _T_23 = eq(_T_22, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_24 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 958:54]
+    node _T_25 = eq(_T_24, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_26 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 958:54]
+    node _T_27 = eq(_T_26, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_28 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 958:54]
+    node _T_29 = eq(_T_28, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_30 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 958:54]
+    node _T_31 = eq(_T_30, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_32 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 958:54]
+    node _T_33 = eq(_T_32, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_34 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 958:54]
+    node _T_35 = eq(_T_34, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_36 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 958:54]
+    node _T_37 = eq(_T_36, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_38 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 958:54]
+    node _T_39 = eq(_T_38, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_40 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 958:54]
+    node _T_41 = eq(_T_40, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_42 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 958:54]
+    node _T_43 = eq(_T_42, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_44 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 958:54]
+    node _T_45 = eq(_T_44, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_46 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 958:54]
+    node _T_47 = eq(_T_46, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_48 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 958:54]
+    node _T_49 = eq(_T_48, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_50 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 958:54]
+    node _T_51 = eq(_T_50, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_52 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 958:54]
+    node _T_53 = eq(_T_52, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_54 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 958:54]
+    node _T_55 = eq(_T_54, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_56 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 958:54]
+    node _T_57 = eq(_T_56, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_58 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 958:54]
+    node _T_59 = eq(_T_58, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_60 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 958:54]
+    node _T_61 = eq(_T_60, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_62 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 958:54]
+    node _T_63 = eq(_T_62, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_64 = mux(_T_1, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_65 = mux(_T_3, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_66 = mux(_T_5, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_67 = mux(_T_7, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_68 = mux(_T_9, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_69 = mux(_T_11, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_70 = mux(_T_13, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_71 = mux(_T_15, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_72 = mux(_T_17, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_73 = mux(_T_19, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_74 = mux(_T_21, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_75 = mux(_T_23, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_76 = mux(_T_25, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_77 = mux(_T_27, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_78 = mux(_T_29, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_79 = mux(_T_31, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_80 = mux(_T_33, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_81 = mux(_T_35, UInt<5>("h011"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_82 = mux(_T_37, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_83 = mux(_T_39, UInt<5>("h013"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_84 = mux(_T_41, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_85 = mux(_T_43, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_86 = mux(_T_45, UInt<5>("h016"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_87 = mux(_T_47, UInt<5>("h017"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_88 = mux(_T_49, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_89 = mux(_T_51, UInt<5>("h019"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_90 = mux(_T_53, UInt<5>("h01a"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_91 = mux(_T_55, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_92 = mux(_T_57, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_93 = mux(_T_59, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_94 = mux(_T_61, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_95 = mux(_T_63, UInt<5>("h01f"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_96 = or(_T_64, _T_65) @[Mux.scala 27:72]
+    node _T_97 = or(_T_96, _T_66) @[Mux.scala 27:72]
+    node _T_98 = or(_T_97, _T_67) @[Mux.scala 27:72]
+    node _T_99 = or(_T_98, _T_68) @[Mux.scala 27:72]
+    node _T_100 = or(_T_99, _T_69) @[Mux.scala 27:72]
+    node _T_101 = or(_T_100, _T_70) @[Mux.scala 27:72]
+    node _T_102 = or(_T_101, _T_71) @[Mux.scala 27:72]
+    node _T_103 = or(_T_102, _T_72) @[Mux.scala 27:72]
+    node _T_104 = or(_T_103, _T_73) @[Mux.scala 27:72]
+    node _T_105 = or(_T_104, _T_74) @[Mux.scala 27:72]
+    node _T_106 = or(_T_105, _T_75) @[Mux.scala 27:72]
+    node _T_107 = or(_T_106, _T_76) @[Mux.scala 27:72]
+    node _T_108 = or(_T_107, _T_77) @[Mux.scala 27:72]
+    node _T_109 = or(_T_108, _T_78) @[Mux.scala 27:72]
+    node _T_110 = or(_T_109, _T_79) @[Mux.scala 27:72]
+    node _T_111 = or(_T_110, _T_80) @[Mux.scala 27:72]
+    node _T_112 = or(_T_111, _T_81) @[Mux.scala 27:72]
+    node _T_113 = or(_T_112, _T_82) @[Mux.scala 27:72]
+    node _T_114 = or(_T_113, _T_83) @[Mux.scala 27:72]
+    node _T_115 = or(_T_114, _T_84) @[Mux.scala 27:72]
+    node _T_116 = or(_T_115, _T_85) @[Mux.scala 27:72]
+    node _T_117 = or(_T_116, _T_86) @[Mux.scala 27:72]
+    node _T_118 = or(_T_117, _T_87) @[Mux.scala 27:72]
+    node _T_119 = or(_T_118, _T_88) @[Mux.scala 27:72]
+    node _T_120 = or(_T_119, _T_89) @[Mux.scala 27:72]
+    node _T_121 = or(_T_120, _T_90) @[Mux.scala 27:72]
+    node _T_122 = or(_T_121, _T_91) @[Mux.scala 27:72]
+    node _T_123 = or(_T_122, _T_92) @[Mux.scala 27:72]
+    node _T_124 = or(_T_123, _T_93) @[Mux.scala 27:72]
+    node _T_125 = or(_T_124, _T_94) @[Mux.scala 27:72]
+    node _T_126 = or(_T_125, _T_95) @[Mux.scala 27:72]
+    wire _T_127 : UInt<5> @[Mux.scala 27:72]
+    _T_127 <= _T_126 @[Mux.scala 27:72]
+    cls_zeros <= _T_127 @[exu_div_ctl.scala 958:13]
+    node _T_128 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 960:18]
+    node _T_129 = eq(_T_128, UInt<32>("h0ffffffff")) @[exu_div_ctl.scala 960:25]
+    when _T_129 : @[exu_div_ctl.scala 960:44]
+      cls_ones <= UInt<5>("h01f") @[exu_div_ctl.scala 960:55]
+      skip @[exu_div_ctl.scala 960:44]
+    else : @[exu_div_ctl.scala 961:15]
+      node _T_130 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 961:66]
+      node _T_131 = cat(UInt<1>("h01"), UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_132 = eq(_T_130, _T_131) @[exu_div_ctl.scala 961:76]
+      node _T_133 = bits(_T_132, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_134 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 961:66]
+      node _T_135 = mux(UInt<1>("h01"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+      node _T_136 = cat(_T_135, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_137 = eq(_T_134, _T_136) @[exu_div_ctl.scala 961:76]
+      node _T_138 = bits(_T_137, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_139 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 961:66]
+      node _T_140 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+      node _T_141 = cat(_T_140, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_142 = eq(_T_139, _T_141) @[exu_div_ctl.scala 961:76]
+      node _T_143 = bits(_T_142, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_144 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 961:66]
+      node _T_145 = mux(UInt<1>("h01"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+      node _T_146 = cat(_T_145, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_147 = eq(_T_144, _T_146) @[exu_div_ctl.scala 961:76]
+      node _T_148 = bits(_T_147, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_149 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 961:66]
+      node _T_150 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
+      node _T_151 = cat(_T_150, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_152 = eq(_T_149, _T_151) @[exu_div_ctl.scala 961:76]
+      node _T_153 = bits(_T_152, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_154 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 961:66]
+      node _T_155 = mux(UInt<1>("h01"), UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+      node _T_156 = cat(_T_155, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_157 = eq(_T_154, _T_156) @[exu_div_ctl.scala 961:76]
+      node _T_158 = bits(_T_157, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_159 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 961:66]
+      node _T_160 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12]
+      node _T_161 = cat(_T_160, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_162 = eq(_T_159, _T_161) @[exu_div_ctl.scala 961:76]
+      node _T_163 = bits(_T_162, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_164 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 961:66]
+      node _T_165 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+      node _T_166 = cat(_T_165, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_167 = eq(_T_164, _T_166) @[exu_div_ctl.scala 961:76]
+      node _T_168 = bits(_T_167, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_169 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 961:66]
+      node _T_170 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
+      node _T_171 = cat(_T_170, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_172 = eq(_T_169, _T_171) @[exu_div_ctl.scala 961:76]
+      node _T_173 = bits(_T_172, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_174 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 961:66]
+      node _T_175 = mux(UInt<1>("h01"), UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12]
+      node _T_176 = cat(_T_175, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_177 = eq(_T_174, _T_176) @[exu_div_ctl.scala 961:76]
+      node _T_178 = bits(_T_177, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_179 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 961:66]
+      node _T_180 = mux(UInt<1>("h01"), UInt<11>("h07ff"), UInt<11>("h00")) @[Bitwise.scala 72:12]
+      node _T_181 = cat(_T_180, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_182 = eq(_T_179, _T_181) @[exu_div_ctl.scala 961:76]
+      node _T_183 = bits(_T_182, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_184 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 961:66]
+      node _T_185 = mux(UInt<1>("h01"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
+      node _T_186 = cat(_T_185, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_187 = eq(_T_184, _T_186) @[exu_div_ctl.scala 961:76]
+      node _T_188 = bits(_T_187, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_189 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 961:66]
+      node _T_190 = mux(UInt<1>("h01"), UInt<13>("h01fff"), UInt<13>("h00")) @[Bitwise.scala 72:12]
+      node _T_191 = cat(_T_190, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_192 = eq(_T_189, _T_191) @[exu_div_ctl.scala 961:76]
+      node _T_193 = bits(_T_192, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_194 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 961:66]
+      node _T_195 = mux(UInt<1>("h01"), UInt<14>("h03fff"), UInt<14>("h00")) @[Bitwise.scala 72:12]
+      node _T_196 = cat(_T_195, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_197 = eq(_T_194, _T_196) @[exu_div_ctl.scala 961:76]
+      node _T_198 = bits(_T_197, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_199 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 961:66]
+      node _T_200 = mux(UInt<1>("h01"), UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 72:12]
+      node _T_201 = cat(_T_200, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_202 = eq(_T_199, _T_201) @[exu_div_ctl.scala 961:76]
+      node _T_203 = bits(_T_202, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_204 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 961:66]
+      node _T_205 = mux(UInt<1>("h01"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
+      node _T_206 = cat(_T_205, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_207 = eq(_T_204, _T_206) @[exu_div_ctl.scala 961:76]
+      node _T_208 = bits(_T_207, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_209 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 961:66]
+      node _T_210 = mux(UInt<1>("h01"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12]
+      node _T_211 = cat(_T_210, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_212 = eq(_T_209, _T_211) @[exu_div_ctl.scala 961:76]
+      node _T_213 = bits(_T_212, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_214 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 961:66]
+      node _T_215 = mux(UInt<1>("h01"), UInt<18>("h03ffff"), UInt<18>("h00")) @[Bitwise.scala 72:12]
+      node _T_216 = cat(_T_215, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_217 = eq(_T_214, _T_216) @[exu_div_ctl.scala 961:76]
+      node _T_218 = bits(_T_217, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_219 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 961:66]
+      node _T_220 = mux(UInt<1>("h01"), UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12]
+      node _T_221 = cat(_T_220, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_222 = eq(_T_219, _T_221) @[exu_div_ctl.scala 961:76]
+      node _T_223 = bits(_T_222, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_224 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 961:66]
+      node _T_225 = mux(UInt<1>("h01"), UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
+      node _T_226 = cat(_T_225, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_227 = eq(_T_224, _T_226) @[exu_div_ctl.scala 961:76]
+      node _T_228 = bits(_T_227, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_229 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 961:66]
+      node _T_230 = mux(UInt<1>("h01"), UInt<21>("h01fffff"), UInt<21>("h00")) @[Bitwise.scala 72:12]
+      node _T_231 = cat(_T_230, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_232 = eq(_T_229, _T_231) @[exu_div_ctl.scala 961:76]
+      node _T_233 = bits(_T_232, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_234 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 961:66]
+      node _T_235 = mux(UInt<1>("h01"), UInt<22>("h03fffff"), UInt<22>("h00")) @[Bitwise.scala 72:12]
+      node _T_236 = cat(_T_235, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_237 = eq(_T_234, _T_236) @[exu_div_ctl.scala 961:76]
+      node _T_238 = bits(_T_237, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_239 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 961:66]
+      node _T_240 = mux(UInt<1>("h01"), UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 72:12]
+      node _T_241 = cat(_T_240, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_242 = eq(_T_239, _T_241) @[exu_div_ctl.scala 961:76]
+      node _T_243 = bits(_T_242, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_244 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 961:66]
+      node _T_245 = mux(UInt<1>("h01"), UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
+      node _T_246 = cat(_T_245, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_247 = eq(_T_244, _T_246) @[exu_div_ctl.scala 961:76]
+      node _T_248 = bits(_T_247, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_249 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 961:66]
+      node _T_250 = mux(UInt<1>("h01"), UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 72:12]
+      node _T_251 = cat(_T_250, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_252 = eq(_T_249, _T_251) @[exu_div_ctl.scala 961:76]
+      node _T_253 = bits(_T_252, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_254 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 961:66]
+      node _T_255 = mux(UInt<1>("h01"), UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12]
+      node _T_256 = cat(_T_255, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_257 = eq(_T_254, _T_256) @[exu_div_ctl.scala 961:76]
+      node _T_258 = bits(_T_257, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_259 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 961:66]
+      node _T_260 = mux(UInt<1>("h01"), UInt<27>("h07ffffff"), UInt<27>("h00")) @[Bitwise.scala 72:12]
+      node _T_261 = cat(_T_260, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_262 = eq(_T_259, _T_261) @[exu_div_ctl.scala 961:76]
+      node _T_263 = bits(_T_262, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_264 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 961:66]
+      node _T_265 = mux(UInt<1>("h01"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12]
+      node _T_266 = cat(_T_265, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_267 = eq(_T_264, _T_266) @[exu_div_ctl.scala 961:76]
+      node _T_268 = bits(_T_267, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_269 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 961:66]
+      node _T_270 = mux(UInt<1>("h01"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12]
+      node _T_271 = cat(_T_270, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_272 = eq(_T_269, _T_271) @[exu_div_ctl.scala 961:76]
+      node _T_273 = bits(_T_272, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_274 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 961:66]
+      node _T_275 = mux(UInt<1>("h01"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12]
+      node _T_276 = cat(_T_275, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_277 = eq(_T_274, _T_276) @[exu_div_ctl.scala 961:76]
+      node _T_278 = bits(_T_277, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_279 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 961:66]
+      node _T_280 = mux(UInt<1>("h01"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
+      node _T_281 = cat(_T_280, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_282 = eq(_T_279, _T_281) @[exu_div_ctl.scala 961:76]
+      node _T_283 = bits(_T_282, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_284 = mux(_T_133, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_285 = mux(_T_138, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_286 = mux(_T_143, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_287 = mux(_T_148, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_288 = mux(_T_153, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_289 = mux(_T_158, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_290 = mux(_T_163, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_291 = mux(_T_168, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_292 = mux(_T_173, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_293 = mux(_T_178, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_294 = mux(_T_183, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_295 = mux(_T_188, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_296 = mux(_T_193, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_297 = mux(_T_198, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_298 = mux(_T_203, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_299 = mux(_T_208, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_300 = mux(_T_213, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_301 = mux(_T_218, UInt<5>("h011"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_302 = mux(_T_223, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_303 = mux(_T_228, UInt<5>("h013"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_304 = mux(_T_233, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_305 = mux(_T_238, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_306 = mux(_T_243, UInt<5>("h016"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_307 = mux(_T_248, UInt<5>("h017"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_308 = mux(_T_253, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_309 = mux(_T_258, UInt<5>("h019"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_310 = mux(_T_263, UInt<5>("h01a"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_311 = mux(_T_268, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_312 = mux(_T_273, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_313 = mux(_T_278, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_314 = mux(_T_283, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_315 = or(_T_284, _T_285) @[Mux.scala 27:72]
+      node _T_316 = or(_T_315, _T_286) @[Mux.scala 27:72]
+      node _T_317 = or(_T_316, _T_287) @[Mux.scala 27:72]
+      node _T_318 = or(_T_317, _T_288) @[Mux.scala 27:72]
+      node _T_319 = or(_T_318, _T_289) @[Mux.scala 27:72]
+      node _T_320 = or(_T_319, _T_290) @[Mux.scala 27:72]
+      node _T_321 = or(_T_320, _T_291) @[Mux.scala 27:72]
+      node _T_322 = or(_T_321, _T_292) @[Mux.scala 27:72]
+      node _T_323 = or(_T_322, _T_293) @[Mux.scala 27:72]
+      node _T_324 = or(_T_323, _T_294) @[Mux.scala 27:72]
+      node _T_325 = or(_T_324, _T_295) @[Mux.scala 27:72]
+      node _T_326 = or(_T_325, _T_296) @[Mux.scala 27:72]
+      node _T_327 = or(_T_326, _T_297) @[Mux.scala 27:72]
+      node _T_328 = or(_T_327, _T_298) @[Mux.scala 27:72]
+      node _T_329 = or(_T_328, _T_299) @[Mux.scala 27:72]
+      node _T_330 = or(_T_329, _T_300) @[Mux.scala 27:72]
+      node _T_331 = or(_T_330, _T_301) @[Mux.scala 27:72]
+      node _T_332 = or(_T_331, _T_302) @[Mux.scala 27:72]
+      node _T_333 = or(_T_332, _T_303) @[Mux.scala 27:72]
+      node _T_334 = or(_T_333, _T_304) @[Mux.scala 27:72]
+      node _T_335 = or(_T_334, _T_305) @[Mux.scala 27:72]
+      node _T_336 = or(_T_335, _T_306) @[Mux.scala 27:72]
+      node _T_337 = or(_T_336, _T_307) @[Mux.scala 27:72]
+      node _T_338 = or(_T_337, _T_308) @[Mux.scala 27:72]
+      node _T_339 = or(_T_338, _T_309) @[Mux.scala 27:72]
+      node _T_340 = or(_T_339, _T_310) @[Mux.scala 27:72]
+      node _T_341 = or(_T_340, _T_311) @[Mux.scala 27:72]
+      node _T_342 = or(_T_341, _T_312) @[Mux.scala 27:72]
+      node _T_343 = or(_T_342, _T_313) @[Mux.scala 27:72]
+      node _T_344 = or(_T_343, _T_314) @[Mux.scala 27:72]
+      wire _T_345 : UInt<5> @[Mux.scala 27:72]
+      _T_345 <= _T_344 @[Mux.scala 27:72]
+      cls_ones <= _T_345 @[exu_div_ctl.scala 961:25]
+      skip @[exu_div_ctl.scala 961:15]
+    node _T_346 = bits(io.operand, 32, 32) @[exu_div_ctl.scala 962:27]
+    node _T_347 = mux(_T_346, cls_ones, cls_zeros) @[exu_div_ctl.scala 962:16]
+    io.cls <= _T_347 @[exu_div_ctl.scala 962:10]
+    
+  module exu_div_cls_1 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {flip operand : UInt<33>, cls : UInt<5>}
+    
+    wire cls_zeros : UInt<5>
+    cls_zeros <= UInt<5>("h00")
+    wire cls_ones : UInt<5>
+    cls_ones <= UInt<5>("h00")
+    node _T = bits(io.operand, 31, 31) @[exu_div_ctl.scala 958:54]
+    node _T_1 = eq(_T, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_2 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 958:54]
+    node _T_3 = eq(_T_2, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_4 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 958:54]
+    node _T_5 = eq(_T_4, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_6 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 958:54]
+    node _T_7 = eq(_T_6, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_8 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 958:54]
+    node _T_9 = eq(_T_8, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_10 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 958:54]
+    node _T_11 = eq(_T_10, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_12 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 958:54]
+    node _T_13 = eq(_T_12, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_14 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 958:54]
+    node _T_15 = eq(_T_14, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_16 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 958:54]
+    node _T_17 = eq(_T_16, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_18 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 958:54]
+    node _T_19 = eq(_T_18, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_20 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 958:54]
+    node _T_21 = eq(_T_20, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_22 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 958:54]
+    node _T_23 = eq(_T_22, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_24 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 958:54]
+    node _T_25 = eq(_T_24, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_26 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 958:54]
+    node _T_27 = eq(_T_26, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_28 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 958:54]
+    node _T_29 = eq(_T_28, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_30 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 958:54]
+    node _T_31 = eq(_T_30, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_32 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 958:54]
+    node _T_33 = eq(_T_32, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_34 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 958:54]
+    node _T_35 = eq(_T_34, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_36 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 958:54]
+    node _T_37 = eq(_T_36, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_38 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 958:54]
+    node _T_39 = eq(_T_38, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_40 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 958:54]
+    node _T_41 = eq(_T_40, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_42 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 958:54]
+    node _T_43 = eq(_T_42, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_44 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 958:54]
+    node _T_45 = eq(_T_44, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_46 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 958:54]
+    node _T_47 = eq(_T_46, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_48 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 958:54]
+    node _T_49 = eq(_T_48, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_50 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 958:54]
+    node _T_51 = eq(_T_50, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_52 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 958:54]
+    node _T_53 = eq(_T_52, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_54 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 958:54]
+    node _T_55 = eq(_T_54, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_56 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 958:54]
+    node _T_57 = eq(_T_56, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_58 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 958:54]
+    node _T_59 = eq(_T_58, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_60 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 958:54]
+    node _T_61 = eq(_T_60, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_62 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 958:54]
+    node _T_63 = eq(_T_62, UInt<1>("h01")) @[exu_div_ctl.scala 958:63]
+    node _T_64 = mux(_T_1, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_65 = mux(_T_3, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_66 = mux(_T_5, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_67 = mux(_T_7, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_68 = mux(_T_9, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_69 = mux(_T_11, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_70 = mux(_T_13, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_71 = mux(_T_15, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_72 = mux(_T_17, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_73 = mux(_T_19, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_74 = mux(_T_21, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_75 = mux(_T_23, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_76 = mux(_T_25, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_77 = mux(_T_27, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_78 = mux(_T_29, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_79 = mux(_T_31, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_80 = mux(_T_33, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_81 = mux(_T_35, UInt<5>("h011"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_82 = mux(_T_37, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_83 = mux(_T_39, UInt<5>("h013"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_84 = mux(_T_41, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_85 = mux(_T_43, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_86 = mux(_T_45, UInt<5>("h016"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_87 = mux(_T_47, UInt<5>("h017"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_88 = mux(_T_49, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_89 = mux(_T_51, UInt<5>("h019"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_90 = mux(_T_53, UInt<5>("h01a"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_91 = mux(_T_55, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_92 = mux(_T_57, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_93 = mux(_T_59, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_94 = mux(_T_61, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_95 = mux(_T_63, UInt<5>("h01f"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_96 = or(_T_64, _T_65) @[Mux.scala 27:72]
+    node _T_97 = or(_T_96, _T_66) @[Mux.scala 27:72]
+    node _T_98 = or(_T_97, _T_67) @[Mux.scala 27:72]
+    node _T_99 = or(_T_98, _T_68) @[Mux.scala 27:72]
+    node _T_100 = or(_T_99, _T_69) @[Mux.scala 27:72]
+    node _T_101 = or(_T_100, _T_70) @[Mux.scala 27:72]
+    node _T_102 = or(_T_101, _T_71) @[Mux.scala 27:72]
+    node _T_103 = or(_T_102, _T_72) @[Mux.scala 27:72]
+    node _T_104 = or(_T_103, _T_73) @[Mux.scala 27:72]
+    node _T_105 = or(_T_104, _T_74) @[Mux.scala 27:72]
+    node _T_106 = or(_T_105, _T_75) @[Mux.scala 27:72]
+    node _T_107 = or(_T_106, _T_76) @[Mux.scala 27:72]
+    node _T_108 = or(_T_107, _T_77) @[Mux.scala 27:72]
+    node _T_109 = or(_T_108, _T_78) @[Mux.scala 27:72]
+    node _T_110 = or(_T_109, _T_79) @[Mux.scala 27:72]
+    node _T_111 = or(_T_110, _T_80) @[Mux.scala 27:72]
+    node _T_112 = or(_T_111, _T_81) @[Mux.scala 27:72]
+    node _T_113 = or(_T_112, _T_82) @[Mux.scala 27:72]
+    node _T_114 = or(_T_113, _T_83) @[Mux.scala 27:72]
+    node _T_115 = or(_T_114, _T_84) @[Mux.scala 27:72]
+    node _T_116 = or(_T_115, _T_85) @[Mux.scala 27:72]
+    node _T_117 = or(_T_116, _T_86) @[Mux.scala 27:72]
+    node _T_118 = or(_T_117, _T_87) @[Mux.scala 27:72]
+    node _T_119 = or(_T_118, _T_88) @[Mux.scala 27:72]
+    node _T_120 = or(_T_119, _T_89) @[Mux.scala 27:72]
+    node _T_121 = or(_T_120, _T_90) @[Mux.scala 27:72]
+    node _T_122 = or(_T_121, _T_91) @[Mux.scala 27:72]
+    node _T_123 = or(_T_122, _T_92) @[Mux.scala 27:72]
+    node _T_124 = or(_T_123, _T_93) @[Mux.scala 27:72]
+    node _T_125 = or(_T_124, _T_94) @[Mux.scala 27:72]
+    node _T_126 = or(_T_125, _T_95) @[Mux.scala 27:72]
+    wire _T_127 : UInt<5> @[Mux.scala 27:72]
+    _T_127 <= _T_126 @[Mux.scala 27:72]
+    cls_zeros <= _T_127 @[exu_div_ctl.scala 958:13]
+    node _T_128 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 960:18]
+    node _T_129 = eq(_T_128, UInt<32>("h0ffffffff")) @[exu_div_ctl.scala 960:25]
+    when _T_129 : @[exu_div_ctl.scala 960:44]
+      cls_ones <= UInt<5>("h01f") @[exu_div_ctl.scala 960:55]
+      skip @[exu_div_ctl.scala 960:44]
+    else : @[exu_div_ctl.scala 961:15]
+      node _T_130 = bits(io.operand, 31, 30) @[exu_div_ctl.scala 961:66]
+      node _T_131 = cat(UInt<1>("h01"), UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_132 = eq(_T_130, _T_131) @[exu_div_ctl.scala 961:76]
+      node _T_133 = bits(_T_132, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_134 = bits(io.operand, 31, 29) @[exu_div_ctl.scala 961:66]
+      node _T_135 = mux(UInt<1>("h01"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+      node _T_136 = cat(_T_135, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_137 = eq(_T_134, _T_136) @[exu_div_ctl.scala 961:76]
+      node _T_138 = bits(_T_137, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_139 = bits(io.operand, 31, 28) @[exu_div_ctl.scala 961:66]
+      node _T_140 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+      node _T_141 = cat(_T_140, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_142 = eq(_T_139, _T_141) @[exu_div_ctl.scala 961:76]
+      node _T_143 = bits(_T_142, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_144 = bits(io.operand, 31, 27) @[exu_div_ctl.scala 961:66]
+      node _T_145 = mux(UInt<1>("h01"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+      node _T_146 = cat(_T_145, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_147 = eq(_T_144, _T_146) @[exu_div_ctl.scala 961:76]
+      node _T_148 = bits(_T_147, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_149 = bits(io.operand, 31, 26) @[exu_div_ctl.scala 961:66]
+      node _T_150 = mux(UInt<1>("h01"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
+      node _T_151 = cat(_T_150, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_152 = eq(_T_149, _T_151) @[exu_div_ctl.scala 961:76]
+      node _T_153 = bits(_T_152, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_154 = bits(io.operand, 31, 25) @[exu_div_ctl.scala 961:66]
+      node _T_155 = mux(UInt<1>("h01"), UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+      node _T_156 = cat(_T_155, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_157 = eq(_T_154, _T_156) @[exu_div_ctl.scala 961:76]
+      node _T_158 = bits(_T_157, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_159 = bits(io.operand, 31, 24) @[exu_div_ctl.scala 961:66]
+      node _T_160 = mux(UInt<1>("h01"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12]
+      node _T_161 = cat(_T_160, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_162 = eq(_T_159, _T_161) @[exu_div_ctl.scala 961:76]
+      node _T_163 = bits(_T_162, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_164 = bits(io.operand, 31, 23) @[exu_div_ctl.scala 961:66]
+      node _T_165 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+      node _T_166 = cat(_T_165, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_167 = eq(_T_164, _T_166) @[exu_div_ctl.scala 961:76]
+      node _T_168 = bits(_T_167, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_169 = bits(io.operand, 31, 22) @[exu_div_ctl.scala 961:66]
+      node _T_170 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
+      node _T_171 = cat(_T_170, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_172 = eq(_T_169, _T_171) @[exu_div_ctl.scala 961:76]
+      node _T_173 = bits(_T_172, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_174 = bits(io.operand, 31, 21) @[exu_div_ctl.scala 961:66]
+      node _T_175 = mux(UInt<1>("h01"), UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12]
+      node _T_176 = cat(_T_175, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_177 = eq(_T_174, _T_176) @[exu_div_ctl.scala 961:76]
+      node _T_178 = bits(_T_177, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_179 = bits(io.operand, 31, 20) @[exu_div_ctl.scala 961:66]
+      node _T_180 = mux(UInt<1>("h01"), UInt<11>("h07ff"), UInt<11>("h00")) @[Bitwise.scala 72:12]
+      node _T_181 = cat(_T_180, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_182 = eq(_T_179, _T_181) @[exu_div_ctl.scala 961:76]
+      node _T_183 = bits(_T_182, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_184 = bits(io.operand, 31, 19) @[exu_div_ctl.scala 961:66]
+      node _T_185 = mux(UInt<1>("h01"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
+      node _T_186 = cat(_T_185, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_187 = eq(_T_184, _T_186) @[exu_div_ctl.scala 961:76]
+      node _T_188 = bits(_T_187, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_189 = bits(io.operand, 31, 18) @[exu_div_ctl.scala 961:66]
+      node _T_190 = mux(UInt<1>("h01"), UInt<13>("h01fff"), UInt<13>("h00")) @[Bitwise.scala 72:12]
+      node _T_191 = cat(_T_190, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_192 = eq(_T_189, _T_191) @[exu_div_ctl.scala 961:76]
+      node _T_193 = bits(_T_192, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_194 = bits(io.operand, 31, 17) @[exu_div_ctl.scala 961:66]
+      node _T_195 = mux(UInt<1>("h01"), UInt<14>("h03fff"), UInt<14>("h00")) @[Bitwise.scala 72:12]
+      node _T_196 = cat(_T_195, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_197 = eq(_T_194, _T_196) @[exu_div_ctl.scala 961:76]
+      node _T_198 = bits(_T_197, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_199 = bits(io.operand, 31, 16) @[exu_div_ctl.scala 961:66]
+      node _T_200 = mux(UInt<1>("h01"), UInt<15>("h07fff"), UInt<15>("h00")) @[Bitwise.scala 72:12]
+      node _T_201 = cat(_T_200, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_202 = eq(_T_199, _T_201) @[exu_div_ctl.scala 961:76]
+      node _T_203 = bits(_T_202, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_204 = bits(io.operand, 31, 15) @[exu_div_ctl.scala 961:66]
+      node _T_205 = mux(UInt<1>("h01"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
+      node _T_206 = cat(_T_205, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_207 = eq(_T_204, _T_206) @[exu_div_ctl.scala 961:76]
+      node _T_208 = bits(_T_207, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_209 = bits(io.operand, 31, 14) @[exu_div_ctl.scala 961:66]
+      node _T_210 = mux(UInt<1>("h01"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12]
+      node _T_211 = cat(_T_210, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_212 = eq(_T_209, _T_211) @[exu_div_ctl.scala 961:76]
+      node _T_213 = bits(_T_212, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_214 = bits(io.operand, 31, 13) @[exu_div_ctl.scala 961:66]
+      node _T_215 = mux(UInt<1>("h01"), UInt<18>("h03ffff"), UInt<18>("h00")) @[Bitwise.scala 72:12]
+      node _T_216 = cat(_T_215, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_217 = eq(_T_214, _T_216) @[exu_div_ctl.scala 961:76]
+      node _T_218 = bits(_T_217, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_219 = bits(io.operand, 31, 12) @[exu_div_ctl.scala 961:66]
+      node _T_220 = mux(UInt<1>("h01"), UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12]
+      node _T_221 = cat(_T_220, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_222 = eq(_T_219, _T_221) @[exu_div_ctl.scala 961:76]
+      node _T_223 = bits(_T_222, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_224 = bits(io.operand, 31, 11) @[exu_div_ctl.scala 961:66]
+      node _T_225 = mux(UInt<1>("h01"), UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
+      node _T_226 = cat(_T_225, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_227 = eq(_T_224, _T_226) @[exu_div_ctl.scala 961:76]
+      node _T_228 = bits(_T_227, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_229 = bits(io.operand, 31, 10) @[exu_div_ctl.scala 961:66]
+      node _T_230 = mux(UInt<1>("h01"), UInt<21>("h01fffff"), UInt<21>("h00")) @[Bitwise.scala 72:12]
+      node _T_231 = cat(_T_230, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_232 = eq(_T_229, _T_231) @[exu_div_ctl.scala 961:76]
+      node _T_233 = bits(_T_232, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_234 = bits(io.operand, 31, 9) @[exu_div_ctl.scala 961:66]
+      node _T_235 = mux(UInt<1>("h01"), UInt<22>("h03fffff"), UInt<22>("h00")) @[Bitwise.scala 72:12]
+      node _T_236 = cat(_T_235, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_237 = eq(_T_234, _T_236) @[exu_div_ctl.scala 961:76]
+      node _T_238 = bits(_T_237, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_239 = bits(io.operand, 31, 8) @[exu_div_ctl.scala 961:66]
+      node _T_240 = mux(UInt<1>("h01"), UInt<23>("h07fffff"), UInt<23>("h00")) @[Bitwise.scala 72:12]
+      node _T_241 = cat(_T_240, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_242 = eq(_T_239, _T_241) @[exu_div_ctl.scala 961:76]
+      node _T_243 = bits(_T_242, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_244 = bits(io.operand, 31, 7) @[exu_div_ctl.scala 961:66]
+      node _T_245 = mux(UInt<1>("h01"), UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
+      node _T_246 = cat(_T_245, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_247 = eq(_T_244, _T_246) @[exu_div_ctl.scala 961:76]
+      node _T_248 = bits(_T_247, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_249 = bits(io.operand, 31, 6) @[exu_div_ctl.scala 961:66]
+      node _T_250 = mux(UInt<1>("h01"), UInt<25>("h01ffffff"), UInt<25>("h00")) @[Bitwise.scala 72:12]
+      node _T_251 = cat(_T_250, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_252 = eq(_T_249, _T_251) @[exu_div_ctl.scala 961:76]
+      node _T_253 = bits(_T_252, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_254 = bits(io.operand, 31, 5) @[exu_div_ctl.scala 961:66]
+      node _T_255 = mux(UInt<1>("h01"), UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12]
+      node _T_256 = cat(_T_255, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_257 = eq(_T_254, _T_256) @[exu_div_ctl.scala 961:76]
+      node _T_258 = bits(_T_257, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_259 = bits(io.operand, 31, 4) @[exu_div_ctl.scala 961:66]
+      node _T_260 = mux(UInt<1>("h01"), UInt<27>("h07ffffff"), UInt<27>("h00")) @[Bitwise.scala 72:12]
+      node _T_261 = cat(_T_260, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_262 = eq(_T_259, _T_261) @[exu_div_ctl.scala 961:76]
+      node _T_263 = bits(_T_262, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_264 = bits(io.operand, 31, 3) @[exu_div_ctl.scala 961:66]
+      node _T_265 = mux(UInt<1>("h01"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12]
+      node _T_266 = cat(_T_265, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_267 = eq(_T_264, _T_266) @[exu_div_ctl.scala 961:76]
+      node _T_268 = bits(_T_267, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_269 = bits(io.operand, 31, 2) @[exu_div_ctl.scala 961:66]
+      node _T_270 = mux(UInt<1>("h01"), UInt<29>("h01fffffff"), UInt<29>("h00")) @[Bitwise.scala 72:12]
+      node _T_271 = cat(_T_270, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_272 = eq(_T_269, _T_271) @[exu_div_ctl.scala 961:76]
+      node _T_273 = bits(_T_272, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_274 = bits(io.operand, 31, 1) @[exu_div_ctl.scala 961:66]
+      node _T_275 = mux(UInt<1>("h01"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12]
+      node _T_276 = cat(_T_275, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_277 = eq(_T_274, _T_276) @[exu_div_ctl.scala 961:76]
+      node _T_278 = bits(_T_277, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_279 = bits(io.operand, 31, 0) @[exu_div_ctl.scala 961:66]
+      node _T_280 = mux(UInt<1>("h01"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
+      node _T_281 = cat(_T_280, UInt<1>("h00")) @[Cat.scala 29:58]
+      node _T_282 = eq(_T_279, _T_281) @[exu_div_ctl.scala 961:76]
+      node _T_283 = bits(_T_282, 0, 0) @[exu_div_ctl.scala 961:102]
+      node _T_284 = mux(_T_133, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_285 = mux(_T_138, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_286 = mux(_T_143, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_287 = mux(_T_148, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_288 = mux(_T_153, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_289 = mux(_T_158, UInt<3>("h05"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_290 = mux(_T_163, UInt<3>("h06"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_291 = mux(_T_168, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_292 = mux(_T_173, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_293 = mux(_T_178, UInt<4>("h09"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_294 = mux(_T_183, UInt<4>("h0a"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_295 = mux(_T_188, UInt<4>("h0b"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_296 = mux(_T_193, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_297 = mux(_T_198, UInt<4>("h0d"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_298 = mux(_T_203, UInt<4>("h0e"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_299 = mux(_T_208, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_300 = mux(_T_213, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_301 = mux(_T_218, UInt<5>("h011"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_302 = mux(_T_223, UInt<5>("h012"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_303 = mux(_T_228, UInt<5>("h013"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_304 = mux(_T_233, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_305 = mux(_T_238, UInt<5>("h015"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_306 = mux(_T_243, UInt<5>("h016"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_307 = mux(_T_248, UInt<5>("h017"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_308 = mux(_T_253, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_309 = mux(_T_258, UInt<5>("h019"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_310 = mux(_T_263, UInt<5>("h01a"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_311 = mux(_T_268, UInt<5>("h01b"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_312 = mux(_T_273, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_313 = mux(_T_278, UInt<5>("h01d"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_314 = mux(_T_283, UInt<5>("h01e"), UInt<1>("h00")) @[Mux.scala 27:72]
+      node _T_315 = or(_T_284, _T_285) @[Mux.scala 27:72]
+      node _T_316 = or(_T_315, _T_286) @[Mux.scala 27:72]
+      node _T_317 = or(_T_316, _T_287) @[Mux.scala 27:72]
+      node _T_318 = or(_T_317, _T_288) @[Mux.scala 27:72]
+      node _T_319 = or(_T_318, _T_289) @[Mux.scala 27:72]
+      node _T_320 = or(_T_319, _T_290) @[Mux.scala 27:72]
+      node _T_321 = or(_T_320, _T_291) @[Mux.scala 27:72]
+      node _T_322 = or(_T_321, _T_292) @[Mux.scala 27:72]
+      node _T_323 = or(_T_322, _T_293) @[Mux.scala 27:72]
+      node _T_324 = or(_T_323, _T_294) @[Mux.scala 27:72]
+      node _T_325 = or(_T_324, _T_295) @[Mux.scala 27:72]
+      node _T_326 = or(_T_325, _T_296) @[Mux.scala 27:72]
+      node _T_327 = or(_T_326, _T_297) @[Mux.scala 27:72]
+      node _T_328 = or(_T_327, _T_298) @[Mux.scala 27:72]
+      node _T_329 = or(_T_328, _T_299) @[Mux.scala 27:72]
+      node _T_330 = or(_T_329, _T_300) @[Mux.scala 27:72]
+      node _T_331 = or(_T_330, _T_301) @[Mux.scala 27:72]
+      node _T_332 = or(_T_331, _T_302) @[Mux.scala 27:72]
+      node _T_333 = or(_T_332, _T_303) @[Mux.scala 27:72]
+      node _T_334 = or(_T_333, _T_304) @[Mux.scala 27:72]
+      node _T_335 = or(_T_334, _T_305) @[Mux.scala 27:72]
+      node _T_336 = or(_T_335, _T_306) @[Mux.scala 27:72]
+      node _T_337 = or(_T_336, _T_307) @[Mux.scala 27:72]
+      node _T_338 = or(_T_337, _T_308) @[Mux.scala 27:72]
+      node _T_339 = or(_T_338, _T_309) @[Mux.scala 27:72]
+      node _T_340 = or(_T_339, _T_310) @[Mux.scala 27:72]
+      node _T_341 = or(_T_340, _T_311) @[Mux.scala 27:72]
+      node _T_342 = or(_T_341, _T_312) @[Mux.scala 27:72]
+      node _T_343 = or(_T_342, _T_313) @[Mux.scala 27:72]
+      node _T_344 = or(_T_343, _T_314) @[Mux.scala 27:72]
+      wire _T_345 : UInt<5> @[Mux.scala 27:72]
+      _T_345 <= _T_344 @[Mux.scala 27:72]
+      cls_ones <= _T_345 @[exu_div_ctl.scala 961:25]
+      skip @[exu_div_ctl.scala 961:15]
+    node _T_346 = bits(io.operand, 32, 32) @[exu_div_ctl.scala 962:27]
+    node _T_347 = mux(_T_346, cls_ones, cls_zeros) @[exu_div_ctl.scala 962:16]
+    io.cls <= _T_347 @[exu_div_ctl.scala 962:10]
+    
+  extmodule gated_latch : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_1 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_1 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_1 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_2 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_2 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_2 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_3 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_3 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_3 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_4 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_4 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_4 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_5 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_5 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_5 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_6 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_6 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_6 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_7 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_7 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_7 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_8 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_8 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_8 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_9 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_9 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_9 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_10 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_10 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_10 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  module exu_div_new_4bit_fullshortq : 
+    input clock : Clock
+    input reset : AsyncReset
+    output io : {flip scan_mode : UInt<1>, flip cancel : UInt<1>, flip valid_in : UInt<1>, flip signed_in : UInt<1>, flip rem_in : UInt<1>, flip dividend_in : UInt<32>, flip divisor_in : UInt<32>, data_out : UInt<32>, valid_out : UInt<1>}
+    
+    wire valid_ff : UInt<1>
+    valid_ff <= UInt<1>("h00")
+    wire finish_ff : UInt<1>
+    finish_ff <= UInt<1>("h00")
+    wire control_ff : UInt<3>
+    control_ff <= UInt<3>("h00")
+    wire count_ff : UInt<7>
+    count_ff <= UInt<7>("h00")
+    wire smallnum : UInt<4>
+    smallnum <= UInt<4>("h00")
+    wire a_ff : UInt<32>
+    a_ff <= UInt<32>("h00")
+    wire b_ff1 : UInt<33>
+    b_ff1 <= UInt<33>("h00")
+    wire b_ff : UInt<38>
+    b_ff <= UInt<38>("h00")
+    wire q_ff : UInt<32>
+    q_ff <= UInt<32>("h00")
+    wire r_ff : UInt<33>
+    r_ff <= UInt<33>("h00")
+    wire quotient_raw : UInt<16>
+    quotient_raw <= UInt<16>("h00")
+    wire quotient_new : UInt<4>
+    quotient_new <= UInt<4>("h00")
+    wire shortq_enable : UInt<1>
+    shortq_enable <= UInt<1>("h00")
+    wire shortq_enable_ff : UInt<1>
+    shortq_enable_ff <= UInt<1>("h00")
+    wire by_zero_case_ff : UInt<1>
+    by_zero_case_ff <= UInt<1>("h00")
+    wire ar_shifted : UInt<65>
+    ar_shifted <= UInt<65>("h00")
+    wire shortq_shift : UInt<5>
+    shortq_shift <= UInt<5>("h00")
+    wire shortq_decode : UInt<5>
+    shortq_decode <= UInt<5>("h00")
+    wire shortq_shift_ff : UInt<5>
+    shortq_shift_ff <= UInt<5>("h00")
+    node _T = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 774:35]
+    node valid_ff_in = and(io.valid_in, _T) @[exu_div_ctl.scala 774:33]
+    node _T_1 = eq(io.valid_in, UInt<1>("h00")) @[exu_div_ctl.scala 775:35]
+    node _T_2 = bits(control_ff, 2, 2) @[exu_div_ctl.scala 775:60]
+    node _T_3 = and(_T_1, _T_2) @[exu_div_ctl.scala 775:48]
+    node _T_4 = and(io.valid_in, io.signed_in) @[exu_div_ctl.scala 775:80]
+    node _T_5 = bits(io.dividend_in, 31, 31) @[exu_div_ctl.scala 775:112]
+    node _T_6 = and(_T_4, _T_5) @[exu_div_ctl.scala 775:96]
+    node _T_7 = or(_T_3, _T_6) @[exu_div_ctl.scala 775:65]
+    node _T_8 = eq(io.valid_in, UInt<1>("h00")) @[exu_div_ctl.scala 775:120]
+    node _T_9 = bits(control_ff, 1, 1) @[exu_div_ctl.scala 775:145]
+    node _T_10 = and(_T_8, _T_9) @[exu_div_ctl.scala 775:133]
+    node _T_11 = and(io.valid_in, io.signed_in) @[exu_div_ctl.scala 775:165]
+    node _T_12 = bits(io.divisor_in, 31, 31) @[exu_div_ctl.scala 775:197]
+    node _T_13 = and(_T_11, _T_12) @[exu_div_ctl.scala 775:181]
+    node _T_14 = or(_T_10, _T_13) @[exu_div_ctl.scala 775:150]
+    node _T_15 = eq(io.valid_in, UInt<1>("h00")) @[exu_div_ctl.scala 775:205]
+    node _T_16 = bits(control_ff, 0, 0) @[exu_div_ctl.scala 775:230]
+    node _T_17 = and(_T_15, _T_16) @[exu_div_ctl.scala 775:218]
+    node _T_18 = and(io.valid_in, io.rem_in) @[exu_div_ctl.scala 775:250]
+    node _T_19 = or(_T_17, _T_18) @[exu_div_ctl.scala 775:235]
+    node _T_20 = cat(_T_7, _T_14) @[Cat.scala 29:58]
+    node control_in = cat(_T_20, _T_19) @[Cat.scala 29:58]
+    node dividend_sign_ff = bits(control_ff, 2, 2) @[exu_div_ctl.scala 776:40]
+    node divisor_sign_ff = bits(control_ff, 1, 1) @[exu_div_ctl.scala 777:40]
+    node rem_ff = bits(control_ff, 0, 0) @[exu_div_ctl.scala 778:40]
+    node _T_21 = bits(b_ff, 31, 0) @[exu_div_ctl.scala 779:47]
+    node _T_22 = eq(_T_21, UInt<1>("h00")) @[exu_div_ctl.scala 779:54]
+    node by_zero_case = and(valid_ff, _T_22) @[exu_div_ctl.scala 779:40]
+    node _T_23 = bits(a_ff, 31, 4) @[exu_div_ctl.scala 781:30]
+    node _T_24 = eq(_T_23, UInt<1>("h00")) @[exu_div_ctl.scala 781:37]
+    node _T_25 = bits(b_ff, 31, 4) @[exu_div_ctl.scala 781:53]
+    node _T_26 = eq(_T_25, UInt<1>("h00")) @[exu_div_ctl.scala 781:60]
+    node _T_27 = and(_T_24, _T_26) @[exu_div_ctl.scala 781:46]
+    node _T_28 = eq(by_zero_case, UInt<1>("h00")) @[exu_div_ctl.scala 781:71]
+    node _T_29 = and(_T_27, _T_28) @[exu_div_ctl.scala 781:69]
+    node _T_30 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 781:87]
+    node _T_31 = and(_T_29, _T_30) @[exu_div_ctl.scala 781:85]
+    node _T_32 = and(_T_31, valid_ff) @[exu_div_ctl.scala 781:95]
+    node _T_33 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 781:108]
+    node _T_34 = and(_T_32, _T_33) @[exu_div_ctl.scala 781:106]
+    node _T_35 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 782:11]
+    node _T_36 = eq(_T_35, UInt<1>("h00")) @[exu_div_ctl.scala 782:18]
+    node _T_37 = eq(by_zero_case, UInt<1>("h00")) @[exu_div_ctl.scala 782:29]
+    node _T_38 = and(_T_36, _T_37) @[exu_div_ctl.scala 782:27]
+    node _T_39 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 782:45]
+    node _T_40 = and(_T_38, _T_39) @[exu_div_ctl.scala 782:43]
+    node _T_41 = and(_T_40, valid_ff) @[exu_div_ctl.scala 782:53]
+    node _T_42 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 782:66]
+    node _T_43 = and(_T_41, _T_42) @[exu_div_ctl.scala 782:64]
+    node smallnum_case = or(_T_34, _T_43) @[exu_div_ctl.scala 781:120]
+    node _T_44 = orr(count_ff) @[exu_div_ctl.scala 783:42]
+    node running_state = or(_T_44, shortq_enable_ff) @[exu_div_ctl.scala 783:45]
+    node _T_45 = or(io.valid_in, valid_ff) @[exu_div_ctl.scala 784:43]
+    node _T_46 = or(_T_45, io.cancel) @[exu_div_ctl.scala 784:54]
+    node _T_47 = or(_T_46, running_state) @[exu_div_ctl.scala 784:66]
+    node misc_enable = or(_T_47, finish_ff) @[exu_div_ctl.scala 784:82]
+    node _T_48 = or(smallnum_case, by_zero_case) @[exu_div_ctl.scala 785:45]
+    node _T_49 = eq(count_ff, UInt<6>("h020")) @[exu_div_ctl.scala 785:72]
+    node finish_raw = or(_T_48, _T_49) @[exu_div_ctl.scala 785:60]
+    node _T_50 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 786:43]
+    node finish = and(finish_raw, _T_50) @[exu_div_ctl.scala 786:41]
+    node _T_51 = or(valid_ff, running_state) @[exu_div_ctl.scala 787:40]
+    node _T_52 = eq(finish, UInt<1>("h00")) @[exu_div_ctl.scala 787:59]
+    node _T_53 = and(_T_51, _T_52) @[exu_div_ctl.scala 787:57]
+    node _T_54 = eq(finish_ff, UInt<1>("h00")) @[exu_div_ctl.scala 787:69]
+    node _T_55 = and(_T_53, _T_54) @[exu_div_ctl.scala 787:67]
+    node _T_56 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 787:82]
+    node _T_57 = and(_T_55, _T_56) @[exu_div_ctl.scala 787:80]
+    node _T_58 = eq(shortq_enable, UInt<1>("h00")) @[exu_div_ctl.scala 787:95]
+    node count_enable = and(_T_57, _T_58) @[exu_div_ctl.scala 787:93]
+    node _T_59 = bits(count_enable, 0, 0) @[Bitwise.scala 72:15]
+    node _T_60 = mux(_T_59, UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12]
+    node _T_61 = add(count_ff, UInt<7>("h04")) @[exu_div_ctl.scala 788:63]
+    node _T_62 = tail(_T_61, 1) @[exu_div_ctl.scala 788:63]
+    node _T_63 = cat(UInt<2>("h00"), shortq_shift_ff) @[Cat.scala 29:58]
+    node _T_64 = add(_T_62, _T_63) @[exu_div_ctl.scala 788:74]
+    node _T_65 = tail(_T_64, 1) @[exu_div_ctl.scala 788:74]
+    node count_in = and(_T_60, _T_65) @[exu_div_ctl.scala 788:51]
+    node a_enable = or(io.valid_in, running_state) @[exu_div_ctl.scala 789:43]
+    node _T_66 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 790:47]
+    node a_shift = and(running_state, _T_66) @[exu_div_ctl.scala 790:45]
+    node _T_67 = bits(dividend_sign_ff, 0, 0) @[Bitwise.scala 72:15]
+    node _T_68 = mux(_T_67, UInt<33>("h01ffffffff"), UInt<33>("h00")) @[Bitwise.scala 72:12]
+    node _T_69 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 791:66]
+    node _T_70 = cat(_T_68, _T_69) @[Cat.scala 29:58]
+    node _T_71 = dshl(_T_70, shortq_shift_ff) @[exu_div_ctl.scala 791:74]
+    ar_shifted <= _T_71 @[exu_div_ctl.scala 791:28]
+    node _T_72 = xor(dividend_sign_ff, divisor_sign_ff) @[exu_div_ctl.scala 792:61]
+    node _T_73 = eq(_T_72, UInt<1>("h00")) @[exu_div_ctl.scala 792:42]
+    node b_twos_comp = and(valid_ff, _T_73) @[exu_div_ctl.scala 792:40]
+    node _T_74 = xor(dividend_sign_ff, divisor_sign_ff) @[exu_div_ctl.scala 793:62]
+    node _T_75 = eq(_T_74, UInt<1>("h00")) @[exu_div_ctl.scala 793:43]
+    node twos_comp_b_sel = and(valid_ff, _T_75) @[exu_div_ctl.scala 793:41]
+    node _T_76 = eq(valid_ff, UInt<1>("h00")) @[exu_div_ctl.scala 794:30]
+    node _T_77 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 794:42]
+    node _T_78 = and(_T_76, _T_77) @[exu_div_ctl.scala 794:40]
+    node _T_79 = xor(dividend_sign_ff, divisor_sign_ff) @[exu_div_ctl.scala 794:71]
+    node _T_80 = and(_T_78, _T_79) @[exu_div_ctl.scala 794:50]
+    node _T_81 = eq(by_zero_case_ff, UInt<1>("h00")) @[exu_div_ctl.scala 794:92]
+    node twos_comp_q_sel = and(_T_80, _T_81) @[exu_div_ctl.scala 794:90]
+    node b_enable = or(io.valid_in, b_twos_comp) @[exu_div_ctl.scala 795:43]
+    node _T_82 = or(io.valid_in, valid_ff) @[exu_div_ctl.scala 796:43]
+    node rq_enable = or(_T_82, running_state) @[exu_div_ctl.scala 796:54]
+    node _T_83 = and(valid_ff, dividend_sign_ff) @[exu_div_ctl.scala 797:40]
+    node _T_84 = eq(by_zero_case, UInt<1>("h00")) @[exu_div_ctl.scala 797:61]
+    node r_sign_sel = and(_T_83, _T_84) @[exu_div_ctl.scala 797:59]
+    node _T_85 = eq(quotient_new, UInt<1>("h00")) @[exu_div_ctl.scala 798:71]
+    node _T_86 = and(running_state, _T_85) @[exu_div_ctl.scala 798:55]
+    node _T_87 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 798:87]
+    node r_adder_sel_0 = and(_T_86, _T_87) @[exu_div_ctl.scala 798:85]
+    node _T_88 = eq(quotient_new, UInt<1>("h01")) @[exu_div_ctl.scala 798:71]
+    node _T_89 = and(running_state, _T_88) @[exu_div_ctl.scala 798:55]
+    node _T_90 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 798:87]
+    node r_adder_sel_1 = and(_T_89, _T_90) @[exu_div_ctl.scala 798:85]
+    node _T_91 = eq(quotient_new, UInt<2>("h02")) @[exu_div_ctl.scala 798:71]
+    node _T_92 = and(running_state, _T_91) @[exu_div_ctl.scala 798:55]
+    node _T_93 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 798:87]
+    node r_adder_sel_2 = and(_T_92, _T_93) @[exu_div_ctl.scala 798:85]
+    node _T_94 = eq(quotient_new, UInt<2>("h03")) @[exu_div_ctl.scala 798:71]
+    node _T_95 = and(running_state, _T_94) @[exu_div_ctl.scala 798:55]
+    node _T_96 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 798:87]
+    node r_adder_sel_3 = and(_T_95, _T_96) @[exu_div_ctl.scala 798:85]
+    node _T_97 = eq(quotient_new, UInt<3>("h04")) @[exu_div_ctl.scala 798:71]
+    node _T_98 = and(running_state, _T_97) @[exu_div_ctl.scala 798:55]
+    node _T_99 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 798:87]
+    node r_adder_sel_4 = and(_T_98, _T_99) @[exu_div_ctl.scala 798:85]
+    node _T_100 = eq(quotient_new, UInt<3>("h05")) @[exu_div_ctl.scala 798:71]
+    node _T_101 = and(running_state, _T_100) @[exu_div_ctl.scala 798:55]
+    node _T_102 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 798:87]
+    node r_adder_sel_5 = and(_T_101, _T_102) @[exu_div_ctl.scala 798:85]
+    node _T_103 = eq(quotient_new, UInt<3>("h06")) @[exu_div_ctl.scala 798:71]
+    node _T_104 = and(running_state, _T_103) @[exu_div_ctl.scala 798:55]
+    node _T_105 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 798:87]
+    node r_adder_sel_6 = and(_T_104, _T_105) @[exu_div_ctl.scala 798:85]
+    node _T_106 = eq(quotient_new, UInt<3>("h07")) @[exu_div_ctl.scala 798:71]
+    node _T_107 = and(running_state, _T_106) @[exu_div_ctl.scala 798:55]
+    node _T_108 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 798:87]
+    node r_adder_sel_7 = and(_T_107, _T_108) @[exu_div_ctl.scala 798:85]
+    node _T_109 = eq(quotient_new, UInt<4>("h08")) @[exu_div_ctl.scala 798:71]
+    node _T_110 = and(running_state, _T_109) @[exu_div_ctl.scala 798:55]
+    node _T_111 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 798:87]
+    node r_adder_sel_8 = and(_T_110, _T_111) @[exu_div_ctl.scala 798:85]
+    node _T_112 = eq(quotient_new, UInt<4>("h09")) @[exu_div_ctl.scala 798:71]
+    node _T_113 = and(running_state, _T_112) @[exu_div_ctl.scala 798:55]
+    node _T_114 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 798:87]
+    node r_adder_sel_9 = and(_T_113, _T_114) @[exu_div_ctl.scala 798:85]
+    node _T_115 = eq(quotient_new, UInt<4>("h0a")) @[exu_div_ctl.scala 798:71]
+    node _T_116 = and(running_state, _T_115) @[exu_div_ctl.scala 798:55]
+    node _T_117 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 798:87]
+    node r_adder_sel_10 = and(_T_116, _T_117) @[exu_div_ctl.scala 798:85]
+    node _T_118 = eq(quotient_new, UInt<4>("h0b")) @[exu_div_ctl.scala 798:71]
+    node _T_119 = and(running_state, _T_118) @[exu_div_ctl.scala 798:55]
+    node _T_120 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 798:87]
+    node r_adder_sel_11 = and(_T_119, _T_120) @[exu_div_ctl.scala 798:85]
+    node _T_121 = eq(quotient_new, UInt<4>("h0c")) @[exu_div_ctl.scala 798:71]
+    node _T_122 = and(running_state, _T_121) @[exu_div_ctl.scala 798:55]
+    node _T_123 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 798:87]
+    node r_adder_sel_12 = and(_T_122, _T_123) @[exu_div_ctl.scala 798:85]
+    node _T_124 = eq(quotient_new, UInt<4>("h0d")) @[exu_div_ctl.scala 798:71]
+    node _T_125 = and(running_state, _T_124) @[exu_div_ctl.scala 798:55]
+    node _T_126 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 798:87]
+    node r_adder_sel_13 = and(_T_125, _T_126) @[exu_div_ctl.scala 798:85]
+    node _T_127 = eq(quotient_new, UInt<4>("h0e")) @[exu_div_ctl.scala 798:71]
+    node _T_128 = and(running_state, _T_127) @[exu_div_ctl.scala 798:55]
+    node _T_129 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 798:87]
+    node r_adder_sel_14 = and(_T_128, _T_129) @[exu_div_ctl.scala 798:85]
+    node _T_130 = eq(quotient_new, UInt<4>("h0f")) @[exu_div_ctl.scala 798:71]
+    node _T_131 = and(running_state, _T_130) @[exu_div_ctl.scala 798:55]
+    node _T_132 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 798:87]
+    node r_adder_sel_15 = and(_T_131, _T_132) @[exu_div_ctl.scala 798:85]
+    node _T_133 = bits(r_ff, 30, 0) @[exu_div_ctl.scala 800:28]
+    node _T_134 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 800:39]
+    node _T_135 = cat(_T_133, _T_134) @[Cat.scala 29:58]
+    node _T_136 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 800:54]
+    node _T_137 = add(_T_135, _T_136) @[exu_div_ctl.scala 800:48]
+    node adder1_out = tail(_T_137, 1) @[exu_div_ctl.scala 800:48]
+    node _T_138 = bits(r_ff, 31, 0) @[exu_div_ctl.scala 801:28]
+    node _T_139 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 801:39]
+    node _T_140 = cat(_T_138, _T_139) @[Cat.scala 29:58]
+    node _T_141 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 801:58]
+    node _T_142 = cat(_T_141, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_143 = add(_T_140, _T_142) @[exu_div_ctl.scala 801:48]
+    node adder2_out = tail(_T_143, 1) @[exu_div_ctl.scala 801:48]
+    node _T_144 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 802:28]
+    node _T_145 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 802:39]
+    node _T_146 = cat(_T_144, _T_145) @[Cat.scala 29:58]
+    node _T_147 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 802:58]
+    node _T_148 = cat(_T_147, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_149 = add(_T_146, _T_148) @[exu_div_ctl.scala 802:48]
+    node _T_150 = tail(_T_149, 1) @[exu_div_ctl.scala 802:48]
+    node _T_151 = bits(b_ff, 36, 0) @[exu_div_ctl.scala 802:76]
+    node _T_152 = add(_T_150, _T_151) @[exu_div_ctl.scala 802:70]
+    node adder3_out = tail(_T_152, 1) @[exu_div_ctl.scala 802:70]
+    node _T_153 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 803:28]
+    node _T_154 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 803:37]
+    node _T_155 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 803:48]
+    node _T_156 = cat(_T_153, _T_154) @[Cat.scala 29:58]
+    node _T_157 = cat(_T_156, _T_155) @[Cat.scala 29:58]
+    node _T_158 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 803:67]
+    node _T_159 = cat(_T_158, UInt<2>("h00")) @[Cat.scala 29:58]
+    node _T_160 = add(_T_157, _T_159) @[exu_div_ctl.scala 803:57]
+    node adder4_out = tail(_T_160, 1) @[exu_div_ctl.scala 803:57]
+    node _T_161 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 804:28]
+    node _T_162 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 804:37]
+    node _T_163 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 804:48]
+    node _T_164 = cat(_T_161, _T_162) @[Cat.scala 29:58]
+    node _T_165 = cat(_T_164, _T_163) @[Cat.scala 29:58]
+    node _T_166 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 804:67]
+    node _T_167 = cat(_T_166, UInt<2>("h00")) @[Cat.scala 29:58]
+    node _T_168 = add(_T_165, _T_167) @[exu_div_ctl.scala 804:57]
+    node _T_169 = tail(_T_168, 1) @[exu_div_ctl.scala 804:57]
+    node _T_170 = add(_T_169, b_ff) @[exu_div_ctl.scala 804:84]
+    node adder5_out = tail(_T_170, 1) @[exu_div_ctl.scala 804:84]
+    node _T_171 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 805:28]
+    node _T_172 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 805:37]
+    node _T_173 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 805:48]
+    node _T_174 = cat(_T_171, _T_172) @[Cat.scala 29:58]
+    node _T_175 = cat(_T_174, _T_173) @[Cat.scala 29:58]
+    node _T_176 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 805:67]
+    node _T_177 = cat(_T_176, UInt<2>("h00")) @[Cat.scala 29:58]
+    node _T_178 = add(_T_175, _T_177) @[exu_div_ctl.scala 805:57]
+    node _T_179 = tail(_T_178, 1) @[exu_div_ctl.scala 805:57]
+    node _T_180 = bits(b_ff, 36, 0) @[exu_div_ctl.scala 805:94]
+    node _T_181 = cat(_T_180, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_182 = add(_T_179, _T_181) @[exu_div_ctl.scala 805:84]
+    node adder6_out = tail(_T_182, 1) @[exu_div_ctl.scala 805:84]
+    node _T_183 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 806:28]
+    node _T_184 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 806:37]
+    node _T_185 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 806:48]
+    node _T_186 = cat(_T_183, _T_184) @[Cat.scala 29:58]
+    node _T_187 = cat(_T_186, _T_185) @[Cat.scala 29:58]
+    node _T_188 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 806:67]
+    node _T_189 = cat(_T_188, UInt<2>("h00")) @[Cat.scala 29:58]
+    node _T_190 = add(_T_187, _T_189) @[exu_div_ctl.scala 806:57]
+    node _T_191 = tail(_T_190, 1) @[exu_div_ctl.scala 806:57]
+    node _T_192 = bits(b_ff, 36, 0) @[exu_div_ctl.scala 806:94]
+    node _T_193 = cat(_T_192, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_194 = add(_T_191, _T_193) @[exu_div_ctl.scala 806:84]
+    node _T_195 = tail(_T_194, 1) @[exu_div_ctl.scala 806:84]
+    node _T_196 = add(_T_195, b_ff) @[exu_div_ctl.scala 806:106]
+    node adder7_out = tail(_T_196, 1) @[exu_div_ctl.scala 806:106]
+    node _T_197 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 807:29]
+    node _T_198 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 807:38]
+    node _T_199 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 807:49]
+    node _T_200 = cat(_T_197, _T_198) @[Cat.scala 29:58]
+    node _T_201 = cat(_T_200, _T_199) @[Cat.scala 29:58]
+    node _T_202 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 807:68]
+    node _T_203 = cat(_T_202, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_204 = add(_T_201, _T_203) @[exu_div_ctl.scala 807:58]
+    node adder8_out = tail(_T_204, 1) @[exu_div_ctl.scala 807:58]
+    node _T_205 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 808:29]
+    node _T_206 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 808:38]
+    node _T_207 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 808:49]
+    node _T_208 = cat(_T_205, _T_206) @[Cat.scala 29:58]
+    node _T_209 = cat(_T_208, _T_207) @[Cat.scala 29:58]
+    node _T_210 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 808:68]
+    node _T_211 = cat(_T_210, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_212 = add(_T_209, _T_211) @[exu_div_ctl.scala 808:58]
+    node _T_213 = tail(_T_212, 1) @[exu_div_ctl.scala 808:58]
+    node _T_214 = add(_T_213, b_ff) @[exu_div_ctl.scala 808:85]
+    node adder9_out = tail(_T_214, 1) @[exu_div_ctl.scala 808:85]
+    node _T_215 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 809:29]
+    node _T_216 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 809:38]
+    node _T_217 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 809:49]
+    node _T_218 = cat(_T_215, _T_216) @[Cat.scala 29:58]
+    node _T_219 = cat(_T_218, _T_217) @[Cat.scala 29:58]
+    node _T_220 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 809:68]
+    node _T_221 = cat(_T_220, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_222 = add(_T_219, _T_221) @[exu_div_ctl.scala 809:58]
+    node _T_223 = tail(_T_222, 1) @[exu_div_ctl.scala 809:58]
+    node _T_224 = bits(b_ff, 36, 0) @[exu_div_ctl.scala 809:95]
+    node _T_225 = cat(_T_224, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_226 = add(_T_223, _T_225) @[exu_div_ctl.scala 809:85]
+    node adder10_out = tail(_T_226, 1) @[exu_div_ctl.scala 809:85]
+    node _T_227 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 810:29]
+    node _T_228 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 810:38]
+    node _T_229 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 810:49]
+    node _T_230 = cat(_T_227, _T_228) @[Cat.scala 29:58]
+    node _T_231 = cat(_T_230, _T_229) @[Cat.scala 29:58]
+    node _T_232 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 810:68]
+    node _T_233 = cat(_T_232, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_234 = add(_T_231, _T_233) @[exu_div_ctl.scala 810:58]
+    node _T_235 = tail(_T_234, 1) @[exu_div_ctl.scala 810:58]
+    node _T_236 = bits(b_ff, 36, 0) @[exu_div_ctl.scala 810:95]
+    node _T_237 = cat(_T_236, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_238 = add(_T_235, _T_237) @[exu_div_ctl.scala 810:85]
+    node _T_239 = tail(_T_238, 1) @[exu_div_ctl.scala 810:85]
+    node _T_240 = add(_T_239, b_ff) @[exu_div_ctl.scala 810:107]
+    node adder11_out = tail(_T_240, 1) @[exu_div_ctl.scala 810:107]
+    node _T_241 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 811:29]
+    node _T_242 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 811:38]
+    node _T_243 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 811:49]
+    node _T_244 = cat(_T_241, _T_242) @[Cat.scala 29:58]
+    node _T_245 = cat(_T_244, _T_243) @[Cat.scala 29:58]
+    node _T_246 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 811:68]
+    node _T_247 = cat(_T_246, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_248 = add(_T_245, _T_247) @[exu_div_ctl.scala 811:58]
+    node _T_249 = tail(_T_248, 1) @[exu_div_ctl.scala 811:58]
+    node _T_250 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 811:95]
+    node _T_251 = cat(_T_250, UInt<2>("h00")) @[Cat.scala 29:58]
+    node _T_252 = add(_T_249, _T_251) @[exu_div_ctl.scala 811:85]
+    node adder12_out = tail(_T_252, 1) @[exu_div_ctl.scala 811:85]
+    node _T_253 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 812:29]
+    node _T_254 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 812:38]
+    node _T_255 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 812:49]
+    node _T_256 = cat(_T_253, _T_254) @[Cat.scala 29:58]
+    node _T_257 = cat(_T_256, _T_255) @[Cat.scala 29:58]
+    node _T_258 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 812:68]
+    node _T_259 = cat(_T_258, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_260 = add(_T_257, _T_259) @[exu_div_ctl.scala 812:58]
+    node _T_261 = tail(_T_260, 1) @[exu_div_ctl.scala 812:58]
+    node _T_262 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 812:95]
+    node _T_263 = cat(_T_262, UInt<2>("h00")) @[Cat.scala 29:58]
+    node _T_264 = add(_T_261, _T_263) @[exu_div_ctl.scala 812:85]
+    node _T_265 = tail(_T_264, 1) @[exu_div_ctl.scala 812:85]
+    node _T_266 = add(_T_265, b_ff) @[exu_div_ctl.scala 812:112]
+    node adder13_out = tail(_T_266, 1) @[exu_div_ctl.scala 812:112]
+    node _T_267 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 813:29]
+    node _T_268 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 813:38]
+    node _T_269 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 813:49]
+    node _T_270 = cat(_T_267, _T_268) @[Cat.scala 29:58]
+    node _T_271 = cat(_T_270, _T_269) @[Cat.scala 29:58]
+    node _T_272 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 813:68]
+    node _T_273 = cat(_T_272, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_274 = add(_T_271, _T_273) @[exu_div_ctl.scala 813:58]
+    node _T_275 = tail(_T_274, 1) @[exu_div_ctl.scala 813:58]
+    node _T_276 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 813:95]
+    node _T_277 = cat(_T_276, UInt<2>("h00")) @[Cat.scala 29:58]
+    node _T_278 = add(_T_275, _T_277) @[exu_div_ctl.scala 813:85]
+    node _T_279 = tail(_T_278, 1) @[exu_div_ctl.scala 813:85]
+    node _T_280 = bits(b_ff, 36, 0) @[exu_div_ctl.scala 813:122]
+    node _T_281 = cat(_T_280, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_282 = add(_T_279, _T_281) @[exu_div_ctl.scala 813:112]
+    node adder14_out = tail(_T_282, 1) @[exu_div_ctl.scala 813:112]
+    node _T_283 = bits(r_ff, 32, 32) @[exu_div_ctl.scala 814:29]
+    node _T_284 = bits(r_ff, 32, 0) @[exu_div_ctl.scala 814:38]
+    node _T_285 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 814:49]
+    node _T_286 = cat(_T_283, _T_284) @[Cat.scala 29:58]
+    node _T_287 = cat(_T_286, _T_285) @[Cat.scala 29:58]
+    node _T_288 = bits(b_ff, 34, 0) @[exu_div_ctl.scala 814:68]
+    node _T_289 = cat(_T_288, UInt<3>("h00")) @[Cat.scala 29:58]
+    node _T_290 = add(_T_287, _T_289) @[exu_div_ctl.scala 814:58]
+    node _T_291 = tail(_T_290, 1) @[exu_div_ctl.scala 814:58]
+    node _T_292 = bits(b_ff, 35, 0) @[exu_div_ctl.scala 814:95]
+    node _T_293 = cat(_T_292, UInt<2>("h00")) @[Cat.scala 29:58]
+    node _T_294 = add(_T_291, _T_293) @[exu_div_ctl.scala 814:85]
+    node _T_295 = tail(_T_294, 1) @[exu_div_ctl.scala 814:85]
+    node _T_296 = bits(b_ff, 36, 0) @[exu_div_ctl.scala 814:122]
+    node _T_297 = cat(_T_296, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_298 = add(_T_295, _T_297) @[exu_div_ctl.scala 814:112]
+    node _T_299 = tail(_T_298, 1) @[exu_div_ctl.scala 814:112]
+    node _T_300 = add(_T_299, b_ff) @[exu_div_ctl.scala 814:134]
+    node adder15_out = tail(_T_300, 1) @[exu_div_ctl.scala 814:134]
+    node _T_301 = bits(adder15_out, 37, 37) @[exu_div_ctl.scala 816:18]
+    node _T_302 = eq(_T_301, UInt<1>("h00")) @[exu_div_ctl.scala 816:6]
+    node _T_303 = xor(_T_302, dividend_sign_ff) @[exu_div_ctl.scala 816:23]
+    node _T_304 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 816:51]
+    node _T_305 = eq(_T_304, UInt<1>("h00")) @[exu_div_ctl.scala 816:58]
+    node _T_306 = eq(adder15_out, UInt<1>("h00")) @[exu_div_ctl.scala 816:82]
+    node _T_307 = and(_T_305, _T_306) @[exu_div_ctl.scala 816:67]
+    node _T_308 = or(_T_303, _T_307) @[exu_div_ctl.scala 816:43]
+    node _T_309 = bits(adder14_out, 37, 37) @[exu_div_ctl.scala 817:18]
+    node _T_310 = eq(_T_309, UInt<1>("h00")) @[exu_div_ctl.scala 817:6]
+    node _T_311 = xor(_T_310, dividend_sign_ff) @[exu_div_ctl.scala 817:23]
+    node _T_312 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 817:51]
+    node _T_313 = eq(_T_312, UInt<1>("h00")) @[exu_div_ctl.scala 817:58]
+    node _T_314 = eq(adder14_out, UInt<1>("h00")) @[exu_div_ctl.scala 817:82]
+    node _T_315 = and(_T_313, _T_314) @[exu_div_ctl.scala 817:67]
+    node _T_316 = or(_T_311, _T_315) @[exu_div_ctl.scala 817:43]
+    node _T_317 = bits(adder13_out, 37, 37) @[exu_div_ctl.scala 818:18]
+    node _T_318 = eq(_T_317, UInt<1>("h00")) @[exu_div_ctl.scala 818:6]
+    node _T_319 = xor(_T_318, dividend_sign_ff) @[exu_div_ctl.scala 818:23]
+    node _T_320 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 818:51]
+    node _T_321 = eq(_T_320, UInt<1>("h00")) @[exu_div_ctl.scala 818:58]
+    node _T_322 = eq(adder13_out, UInt<1>("h00")) @[exu_div_ctl.scala 818:82]
+    node _T_323 = and(_T_321, _T_322) @[exu_div_ctl.scala 818:67]
+    node _T_324 = or(_T_319, _T_323) @[exu_div_ctl.scala 818:43]
+    node _T_325 = bits(adder12_out, 37, 37) @[exu_div_ctl.scala 819:18]
+    node _T_326 = eq(_T_325, UInt<1>("h00")) @[exu_div_ctl.scala 819:6]
+    node _T_327 = xor(_T_326, dividend_sign_ff) @[exu_div_ctl.scala 819:23]
+    node _T_328 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 819:51]
+    node _T_329 = eq(_T_328, UInt<1>("h00")) @[exu_div_ctl.scala 819:58]
+    node _T_330 = eq(adder12_out, UInt<1>("h00")) @[exu_div_ctl.scala 819:82]
+    node _T_331 = and(_T_329, _T_330) @[exu_div_ctl.scala 819:67]
+    node _T_332 = or(_T_327, _T_331) @[exu_div_ctl.scala 819:43]
+    node _T_333 = bits(adder11_out, 37, 37) @[exu_div_ctl.scala 820:18]
+    node _T_334 = eq(_T_333, UInt<1>("h00")) @[exu_div_ctl.scala 820:6]
+    node _T_335 = xor(_T_334, dividend_sign_ff) @[exu_div_ctl.scala 820:23]
+    node _T_336 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 820:51]
+    node _T_337 = eq(_T_336, UInt<1>("h00")) @[exu_div_ctl.scala 820:58]
+    node _T_338 = eq(adder11_out, UInt<1>("h00")) @[exu_div_ctl.scala 820:82]
+    node _T_339 = and(_T_337, _T_338) @[exu_div_ctl.scala 820:67]
+    node _T_340 = or(_T_335, _T_339) @[exu_div_ctl.scala 820:43]
+    node _T_341 = bits(adder10_out, 37, 37) @[exu_div_ctl.scala 821:18]
+    node _T_342 = eq(_T_341, UInt<1>("h00")) @[exu_div_ctl.scala 821:6]
+    node _T_343 = xor(_T_342, dividend_sign_ff) @[exu_div_ctl.scala 821:23]
+    node _T_344 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 821:51]
+    node _T_345 = eq(_T_344, UInt<1>("h00")) @[exu_div_ctl.scala 821:58]
+    node _T_346 = eq(adder10_out, UInt<1>("h00")) @[exu_div_ctl.scala 821:82]
+    node _T_347 = and(_T_345, _T_346) @[exu_div_ctl.scala 821:67]
+    node _T_348 = or(_T_343, _T_347) @[exu_div_ctl.scala 821:43]
+    node _T_349 = bits(adder9_out, 37, 37) @[exu_div_ctl.scala 822:17]
+    node _T_350 = eq(_T_349, UInt<1>("h00")) @[exu_div_ctl.scala 822:6]
+    node _T_351 = xor(_T_350, dividend_sign_ff) @[exu_div_ctl.scala 822:22]
+    node _T_352 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 822:50]
+    node _T_353 = eq(_T_352, UInt<1>("h00")) @[exu_div_ctl.scala 822:57]
+    node _T_354 = eq(adder9_out, UInt<1>("h00")) @[exu_div_ctl.scala 822:80]
+    node _T_355 = and(_T_353, _T_354) @[exu_div_ctl.scala 822:66]
+    node _T_356 = or(_T_351, _T_355) @[exu_div_ctl.scala 822:42]
+    node _T_357 = bits(adder8_out, 37, 37) @[exu_div_ctl.scala 823:17]
+    node _T_358 = eq(_T_357, UInt<1>("h00")) @[exu_div_ctl.scala 823:6]
+    node _T_359 = xor(_T_358, dividend_sign_ff) @[exu_div_ctl.scala 823:22]
+    node _T_360 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 823:50]
+    node _T_361 = eq(_T_360, UInt<1>("h00")) @[exu_div_ctl.scala 823:57]
+    node _T_362 = eq(adder8_out, UInt<1>("h00")) @[exu_div_ctl.scala 823:80]
+    node _T_363 = and(_T_361, _T_362) @[exu_div_ctl.scala 823:66]
+    node _T_364 = or(_T_359, _T_363) @[exu_div_ctl.scala 823:42]
+    node _T_365 = bits(adder7_out, 37, 37) @[exu_div_ctl.scala 824:17]
+    node _T_366 = eq(_T_365, UInt<1>("h00")) @[exu_div_ctl.scala 824:6]
+    node _T_367 = xor(_T_366, dividend_sign_ff) @[exu_div_ctl.scala 824:22]
+    node _T_368 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 824:50]
+    node _T_369 = eq(_T_368, UInt<1>("h00")) @[exu_div_ctl.scala 824:57]
+    node _T_370 = eq(adder7_out, UInt<1>("h00")) @[exu_div_ctl.scala 824:80]
+    node _T_371 = and(_T_369, _T_370) @[exu_div_ctl.scala 824:66]
+    node _T_372 = or(_T_367, _T_371) @[exu_div_ctl.scala 824:42]
+    node _T_373 = bits(adder6_out, 37, 37) @[exu_div_ctl.scala 825:17]
+    node _T_374 = eq(_T_373, UInt<1>("h00")) @[exu_div_ctl.scala 825:6]
+    node _T_375 = xor(_T_374, dividend_sign_ff) @[exu_div_ctl.scala 825:22]
+    node _T_376 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 825:50]
+    node _T_377 = eq(_T_376, UInt<1>("h00")) @[exu_div_ctl.scala 825:57]
+    node _T_378 = eq(adder6_out, UInt<1>("h00")) @[exu_div_ctl.scala 825:80]
+    node _T_379 = and(_T_377, _T_378) @[exu_div_ctl.scala 825:66]
+    node _T_380 = or(_T_375, _T_379) @[exu_div_ctl.scala 825:42]
+    node _T_381 = bits(adder5_out, 37, 37) @[exu_div_ctl.scala 826:17]
+    node _T_382 = eq(_T_381, UInt<1>("h00")) @[exu_div_ctl.scala 826:6]
+    node _T_383 = xor(_T_382, dividend_sign_ff) @[exu_div_ctl.scala 826:22]
+    node _T_384 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 826:50]
+    node _T_385 = eq(_T_384, UInt<1>("h00")) @[exu_div_ctl.scala 826:57]
+    node _T_386 = eq(adder5_out, UInt<1>("h00")) @[exu_div_ctl.scala 826:80]
+    node _T_387 = and(_T_385, _T_386) @[exu_div_ctl.scala 826:66]
+    node _T_388 = or(_T_383, _T_387) @[exu_div_ctl.scala 826:42]
+    node _T_389 = bits(adder4_out, 37, 37) @[exu_div_ctl.scala 827:17]
+    node _T_390 = eq(_T_389, UInt<1>("h00")) @[exu_div_ctl.scala 827:6]
+    node _T_391 = xor(_T_390, dividend_sign_ff) @[exu_div_ctl.scala 827:22]
+    node _T_392 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 827:50]
+    node _T_393 = eq(_T_392, UInt<1>("h00")) @[exu_div_ctl.scala 827:57]
+    node _T_394 = eq(adder4_out, UInt<1>("h00")) @[exu_div_ctl.scala 827:80]
+    node _T_395 = and(_T_393, _T_394) @[exu_div_ctl.scala 827:66]
+    node _T_396 = or(_T_391, _T_395) @[exu_div_ctl.scala 827:42]
+    node _T_397 = bits(adder3_out, 36, 36) @[exu_div_ctl.scala 828:17]
+    node _T_398 = eq(_T_397, UInt<1>("h00")) @[exu_div_ctl.scala 828:6]
+    node _T_399 = xor(_T_398, dividend_sign_ff) @[exu_div_ctl.scala 828:22]
+    node _T_400 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 828:50]
+    node _T_401 = eq(_T_400, UInt<1>("h00")) @[exu_div_ctl.scala 828:57]
+    node _T_402 = eq(adder3_out, UInt<1>("h00")) @[exu_div_ctl.scala 828:80]
+    node _T_403 = and(_T_401, _T_402) @[exu_div_ctl.scala 828:66]
+    node _T_404 = or(_T_399, _T_403) @[exu_div_ctl.scala 828:42]
+    node _T_405 = bits(adder2_out, 35, 35) @[exu_div_ctl.scala 829:17]
+    node _T_406 = eq(_T_405, UInt<1>("h00")) @[exu_div_ctl.scala 829:6]
+    node _T_407 = xor(_T_406, dividend_sign_ff) @[exu_div_ctl.scala 829:22]
+    node _T_408 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 829:50]
+    node _T_409 = eq(_T_408, UInt<1>("h00")) @[exu_div_ctl.scala 829:57]
+    node _T_410 = eq(adder2_out, UInt<1>("h00")) @[exu_div_ctl.scala 829:80]
+    node _T_411 = and(_T_409, _T_410) @[exu_div_ctl.scala 829:66]
+    node _T_412 = or(_T_407, _T_411) @[exu_div_ctl.scala 829:42]
+    node _T_413 = bits(adder1_out, 34, 34) @[exu_div_ctl.scala 830:17]
+    node _T_414 = eq(_T_413, UInt<1>("h00")) @[exu_div_ctl.scala 830:6]
+    node _T_415 = xor(_T_414, dividend_sign_ff) @[exu_div_ctl.scala 830:22]
+    node _T_416 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 830:50]
+    node _T_417 = eq(_T_416, UInt<1>("h00")) @[exu_div_ctl.scala 830:57]
+    node _T_418 = eq(adder1_out, UInt<1>("h00")) @[exu_div_ctl.scala 830:80]
+    node _T_419 = and(_T_417, _T_418) @[exu_div_ctl.scala 830:66]
+    node _T_420 = or(_T_415, _T_419) @[exu_div_ctl.scala 830:42]
+    node _T_421 = cat(_T_420, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_422 = cat(_T_404, _T_412) @[Cat.scala 29:58]
+    node _T_423 = cat(_T_422, _T_421) @[Cat.scala 29:58]
+    node _T_424 = cat(_T_388, _T_396) @[Cat.scala 29:58]
+    node _T_425 = cat(_T_372, _T_380) @[Cat.scala 29:58]
+    node _T_426 = cat(_T_425, _T_424) @[Cat.scala 29:58]
+    node _T_427 = cat(_T_426, _T_423) @[Cat.scala 29:58]
+    node _T_428 = cat(_T_356, _T_364) @[Cat.scala 29:58]
+    node _T_429 = cat(_T_340, _T_348) @[Cat.scala 29:58]
+    node _T_430 = cat(_T_429, _T_428) @[Cat.scala 29:58]
+    node _T_431 = cat(_T_324, _T_332) @[Cat.scala 29:58]
+    node _T_432 = cat(_T_308, _T_316) @[Cat.scala 29:58]
+    node _T_433 = cat(_T_432, _T_431) @[Cat.scala 29:58]
+    node _T_434 = cat(_T_433, _T_430) @[Cat.scala 29:58]
+    node _T_435 = cat(_T_434, _T_427) @[Cat.scala 29:58]
+    quotient_raw <= _T_435 @[exu_div_ctl.scala 815:17]
+    node _T_436 = bits(quotient_raw, 15, 15) @[exu_div_ctl.scala 833:19]
+    node _T_437 = eq(_T_436, UInt<1>("h01")) @[exu_div_ctl.scala 833:23]
+    node _T_438 = bits(quotient_raw, 15, 8) @[exu_div_ctl.scala 833:70]
+    node _T_439 = mux(UInt<1>("h00"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12]
+    node _T_440 = cat(_T_439, UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_441 = eq(_T_438, _T_440) @[exu_div_ctl.scala 833:76]
+    node _T_442 = bits(_T_441, 0, 0) @[exu_div_ctl.scala 833:105]
+    node _T_443 = bits(quotient_raw, 15, 9) @[exu_div_ctl.scala 833:70]
+    node _T_444 = mux(UInt<1>("h00"), UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_445 = cat(_T_444, UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_446 = eq(_T_443, _T_445) @[exu_div_ctl.scala 833:76]
+    node _T_447 = bits(_T_446, 0, 0) @[exu_div_ctl.scala 833:105]
+    node _T_448 = bits(quotient_raw, 15, 10) @[exu_div_ctl.scala 833:70]
+    node _T_449 = mux(UInt<1>("h00"), UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12]
+    node _T_450 = cat(_T_449, UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_451 = eq(_T_448, _T_450) @[exu_div_ctl.scala 833:76]
+    node _T_452 = bits(_T_451, 0, 0) @[exu_div_ctl.scala 833:105]
+    node _T_453 = bits(quotient_raw, 15, 11) @[exu_div_ctl.scala 833:70]
+    node _T_454 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_455 = cat(_T_454, UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_456 = eq(_T_453, _T_455) @[exu_div_ctl.scala 833:76]
+    node _T_457 = bits(_T_456, 0, 0) @[exu_div_ctl.scala 833:105]
+    node _T_458 = bits(quotient_raw, 15, 12) @[exu_div_ctl.scala 833:70]
+    node _T_459 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_460 = cat(_T_459, UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_461 = eq(_T_458, _T_460) @[exu_div_ctl.scala 833:76]
+    node _T_462 = bits(_T_461, 0, 0) @[exu_div_ctl.scala 833:105]
+    node _T_463 = bits(quotient_raw, 15, 13) @[exu_div_ctl.scala 833:70]
+    node _T_464 = mux(UInt<1>("h00"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_465 = cat(_T_464, UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_466 = eq(_T_463, _T_465) @[exu_div_ctl.scala 833:76]
+    node _T_467 = bits(_T_466, 0, 0) @[exu_div_ctl.scala 833:105]
+    node _T_468 = bits(quotient_raw, 15, 14) @[exu_div_ctl.scala 833:70]
+    node _T_469 = cat(UInt<1>("h00"), UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_470 = eq(_T_468, _T_469) @[exu_div_ctl.scala 833:76]
+    node _T_471 = bits(_T_470, 0, 0) @[exu_div_ctl.scala 833:105]
+    node _T_472 = mux(_T_442, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_473 = mux(_T_447, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_474 = mux(_T_452, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_475 = mux(_T_457, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_476 = mux(_T_462, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_477 = mux(_T_467, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_478 = mux(_T_471, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_479 = or(_T_472, _T_473) @[Mux.scala 27:72]
+    node _T_480 = or(_T_479, _T_474) @[Mux.scala 27:72]
+    node _T_481 = or(_T_480, _T_475) @[Mux.scala 27:72]
+    node _T_482 = or(_T_481, _T_476) @[Mux.scala 27:72]
+    node _T_483 = or(_T_482, _T_477) @[Mux.scala 27:72]
+    node _T_484 = or(_T_483, _T_478) @[Mux.scala 27:72]
+    wire _T_485 : UInt<1> @[Mux.scala 27:72]
+    _T_485 <= _T_484 @[Mux.scala 27:72]
+    node _T_486 = or(_T_437, _T_485) @[exu_div_ctl.scala 833:31]
+    node _T_487 = bits(quotient_raw, 15, 4) @[exu_div_ctl.scala 835:19]
+    node _T_488 = dshr(UInt<1>("h01"), UInt<4>("h0c")) @[exu_div_ctl.scala 835:47]
+    node _T_489 = bits(_T_488, 0, 0) @[exu_div_ctl.scala 835:47]
+    node _T_490 = eq(_T_487, _T_489) @[exu_div_ctl.scala 835:26]
+    node _T_491 = bits(quotient_raw, 15, 5) @[exu_div_ctl.scala 835:70]
+    node _T_492 = dshr(UInt<1>("h01"), UInt<4>("h0b")) @[exu_div_ctl.scala 835:97]
+    node _T_493 = bits(_T_492, 0, 0) @[exu_div_ctl.scala 835:97]
+    node _T_494 = eq(_T_491, _T_493) @[exu_div_ctl.scala 835:77]
+    node _T_495 = or(_T_490, _T_494) @[exu_div_ctl.scala 835:54]
+    node _T_496 = bits(quotient_raw, 15, 6) @[exu_div_ctl.scala 835:121]
+    node _T_497 = dshr(UInt<1>("h01"), UInt<4>("h0a")) @[exu_div_ctl.scala 835:147]
+    node _T_498 = bits(_T_497, 0, 0) @[exu_div_ctl.scala 835:147]
+    node _T_499 = eq(_T_496, _T_498) @[exu_div_ctl.scala 835:128]
+    node _T_500 = or(_T_495, _T_499) @[exu_div_ctl.scala 835:105]
+    node _T_501 = bits(quotient_raw, 15, 7) @[exu_div_ctl.scala 836:21]
+    node _T_502 = dshr(UInt<1>("h01"), UInt<4>("h09")) @[exu_div_ctl.scala 836:46]
+    node _T_503 = bits(_T_502, 0, 0) @[exu_div_ctl.scala 836:46]
+    node _T_504 = eq(_T_501, _T_503) @[exu_div_ctl.scala 836:28]
+    node _T_505 = or(_T_500, _T_504) @[exu_div_ctl.scala 835:155]
+    node _T_506 = bits(quotient_raw, 15, 12) @[exu_div_ctl.scala 836:69]
+    node _T_507 = dshr(UInt<1>("h01"), UInt<3>("h04")) @[exu_div_ctl.scala 836:89]
+    node _T_508 = bits(_T_507, 0, 0) @[exu_div_ctl.scala 836:89]
+    node _T_509 = eq(_T_506, _T_508) @[exu_div_ctl.scala 836:76]
+    node _T_510 = or(_T_505, _T_509) @[exu_div_ctl.scala 836:53]
+    node _T_511 = bits(quotient_raw, 15, 13) @[exu_div_ctl.scala 836:112]
+    node _T_512 = dshr(UInt<1>("h01"), UInt<2>("h03")) @[exu_div_ctl.scala 836:131]
+    node _T_513 = bits(_T_512, 0, 0) @[exu_div_ctl.scala 836:131]
+    node _T_514 = eq(_T_511, _T_513) @[exu_div_ctl.scala 836:119]
+    node _T_515 = or(_T_510, _T_514) @[exu_div_ctl.scala 836:96]
+    node _T_516 = bits(quotient_raw, 15, 14) @[exu_div_ctl.scala 837:21]
+    node _T_517 = dshr(UInt<1>("h01"), UInt<2>("h02")) @[exu_div_ctl.scala 837:39]
+    node _T_518 = bits(_T_517, 0, 0) @[exu_div_ctl.scala 837:39]
+    node _T_519 = eq(_T_516, _T_518) @[exu_div_ctl.scala 837:28]
+    node _T_520 = or(_T_515, _T_519) @[exu_div_ctl.scala 836:138]
+    node _T_521 = bits(quotient_raw, 15, 15) @[exu_div_ctl.scala 837:62]
+    node _T_522 = eq(_T_521, UInt<1>("h01")) @[exu_div_ctl.scala 837:69]
+    node _T_523 = or(_T_520, _T_522) @[exu_div_ctl.scala 837:46]
+    node _T_524 = bits(quotient_raw, 15, 2) @[exu_div_ctl.scala 839:19]
+    node _T_525 = dshr(UInt<1>("h01"), UInt<4>("h0e")) @[exu_div_ctl.scala 839:49]
+    node _T_526 = bits(_T_525, 0, 0) @[exu_div_ctl.scala 839:49]
+    node _T_527 = eq(_T_524, _T_526) @[exu_div_ctl.scala 839:26]
+    node _T_528 = bits(quotient_raw, 15, 3) @[exu_div_ctl.scala 839:72]
+    node _T_529 = dshr(UInt<1>("h01"), UInt<4>("h0d")) @[exu_div_ctl.scala 839:101]
+    node _T_530 = bits(_T_529, 0, 0) @[exu_div_ctl.scala 839:101]
+    node _T_531 = eq(_T_528, _T_530) @[exu_div_ctl.scala 839:79]
+    node _T_532 = or(_T_527, _T_531) @[exu_div_ctl.scala 839:56]
+    node _T_533 = bits(quotient_raw, 15, 6) @[exu_div_ctl.scala 839:125]
+    node _T_534 = dshr(UInt<1>("h01"), UInt<4>("h0a")) @[exu_div_ctl.scala 839:151]
+    node _T_535 = bits(_T_534, 0, 0) @[exu_div_ctl.scala 839:151]
+    node _T_536 = eq(_T_533, _T_535) @[exu_div_ctl.scala 839:132]
+    node _T_537 = or(_T_532, _T_536) @[exu_div_ctl.scala 839:109]
+    node _T_538 = bits(quotient_raw, 15, 7) @[exu_div_ctl.scala 840:23]
+    node _T_539 = dshr(UInt<1>("h01"), UInt<4>("h09")) @[exu_div_ctl.scala 840:49]
+    node _T_540 = bits(_T_539, 0, 0) @[exu_div_ctl.scala 840:49]
+    node _T_541 = eq(_T_538, _T_540) @[exu_div_ctl.scala 840:30]
+    node _T_542 = or(_T_537, _T_541) @[exu_div_ctl.scala 839:159]
+    node _T_543 = bits(quotient_raw, 15, 10) @[exu_div_ctl.scala 840:72]
+    node _T_544 = dshr(UInt<1>("h01"), UInt<3>("h06")) @[exu_div_ctl.scala 840:94]
+    node _T_545 = bits(_T_544, 0, 0) @[exu_div_ctl.scala 840:94]
+    node _T_546 = eq(_T_543, _T_545) @[exu_div_ctl.scala 840:79]
+    node _T_547 = or(_T_542, _T_546) @[exu_div_ctl.scala 840:56]
+    node _T_548 = bits(quotient_raw, 15, 11) @[exu_div_ctl.scala 840:117]
+    node _T_549 = dshr(UInt<1>("h01"), UInt<3>("h05")) @[exu_div_ctl.scala 840:138]
+    node _T_550 = bits(_T_549, 0, 0) @[exu_div_ctl.scala 840:138]
+    node _T_551 = eq(_T_548, _T_550) @[exu_div_ctl.scala 840:124]
+    node _T_552 = or(_T_547, _T_551) @[exu_div_ctl.scala 840:101]
+    node _T_553 = bits(quotient_raw, 15, 14) @[exu_div_ctl.scala 841:23]
+    node _T_554 = dshr(UInt<1>("h01"), UInt<2>("h02")) @[exu_div_ctl.scala 841:41]
+    node _T_555 = bits(_T_554, 0, 0) @[exu_div_ctl.scala 841:41]
+    node _T_556 = eq(_T_553, _T_555) @[exu_div_ctl.scala 841:30]
+    node _T_557 = or(_T_552, _T_556) @[exu_div_ctl.scala 840:145]
+    node _T_558 = bits(quotient_raw, 15, 15) @[exu_div_ctl.scala 841:64]
+    node _T_559 = eq(_T_558, UInt<1>("h01")) @[exu_div_ctl.scala 841:71]
+    node _T_560 = or(_T_557, _T_559) @[exu_div_ctl.scala 841:48]
+    node _T_561 = bits(quotient_raw, 15, 15) @[exu_div_ctl.scala 843:19]
+    node _T_562 = eq(_T_561, UInt<1>("h01")) @[exu_div_ctl.scala 843:23]
+    node _T_563 = bits(quotient_raw, 15, 1) @[exu_div_ctl.scala 843:75]
+    node _T_564 = mux(UInt<1>("h00"), UInt<14>("h03fff"), UInt<14>("h00")) @[Bitwise.scala 72:12]
+    node _T_565 = cat(_T_564, UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_566 = eq(_T_563, _T_565) @[exu_div_ctl.scala 843:81]
+    node _T_567 = bits(_T_566, 0, 0) @[exu_div_ctl.scala 843:110]
+    node _T_568 = bits(quotient_raw, 15, 3) @[exu_div_ctl.scala 843:75]
+    node _T_569 = mux(UInt<1>("h00"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
+    node _T_570 = cat(_T_569, UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_571 = eq(_T_568, _T_570) @[exu_div_ctl.scala 843:81]
+    node _T_572 = bits(_T_571, 0, 0) @[exu_div_ctl.scala 843:110]
+    node _T_573 = bits(quotient_raw, 15, 5) @[exu_div_ctl.scala 843:75]
+    node _T_574 = mux(UInt<1>("h00"), UInt<10>("h03ff"), UInt<10>("h00")) @[Bitwise.scala 72:12]
+    node _T_575 = cat(_T_574, UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_576 = eq(_T_573, _T_575) @[exu_div_ctl.scala 843:81]
+    node _T_577 = bits(_T_576, 0, 0) @[exu_div_ctl.scala 843:110]
+    node _T_578 = bits(quotient_raw, 15, 7) @[exu_div_ctl.scala 843:75]
+    node _T_579 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12]
+    node _T_580 = cat(_T_579, UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_581 = eq(_T_578, _T_580) @[exu_div_ctl.scala 843:81]
+    node _T_582 = bits(_T_581, 0, 0) @[exu_div_ctl.scala 843:110]
+    node _T_583 = bits(quotient_raw, 15, 9) @[exu_div_ctl.scala 843:75]
+    node _T_584 = mux(UInt<1>("h00"), UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12]
+    node _T_585 = cat(_T_584, UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_586 = eq(_T_583, _T_585) @[exu_div_ctl.scala 843:81]
+    node _T_587 = bits(_T_586, 0, 0) @[exu_div_ctl.scala 843:110]
+    node _T_588 = bits(quotient_raw, 15, 11) @[exu_div_ctl.scala 843:75]
+    node _T_589 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
+    node _T_590 = cat(_T_589, UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_591 = eq(_T_588, _T_590) @[exu_div_ctl.scala 843:81]
+    node _T_592 = bits(_T_591, 0, 0) @[exu_div_ctl.scala 843:110]
+    node _T_593 = bits(quotient_raw, 15, 13) @[exu_div_ctl.scala 843:75]
+    node _T_594 = mux(UInt<1>("h00"), UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_595 = cat(_T_594, UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_596 = eq(_T_593, _T_595) @[exu_div_ctl.scala 843:81]
+    node _T_597 = bits(_T_596, 0, 0) @[exu_div_ctl.scala 843:110]
+    node _T_598 = mux(_T_567, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_599 = mux(_T_572, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_600 = mux(_T_577, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_601 = mux(_T_582, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_602 = mux(_T_587, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_603 = mux(_T_592, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_604 = mux(_T_597, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_605 = or(_T_598, _T_599) @[Mux.scala 27:72]
+    node _T_606 = or(_T_605, _T_600) @[Mux.scala 27:72]
+    node _T_607 = or(_T_606, _T_601) @[Mux.scala 27:72]
+    node _T_608 = or(_T_607, _T_602) @[Mux.scala 27:72]
+    node _T_609 = or(_T_608, _T_603) @[Mux.scala 27:72]
+    node _T_610 = or(_T_609, _T_604) @[Mux.scala 27:72]
+    wire _T_611 : UInt<1> @[Mux.scala 27:72]
+    _T_611 <= _T_610 @[Mux.scala 27:72]
+    node _T_612 = or(_T_562, _T_611) @[exu_div_ctl.scala 843:31]
+    node _T_613 = cat(_T_560, _T_612) @[Cat.scala 29:58]
+    node _T_614 = cat(_T_486, _T_523) @[Cat.scala 29:58]
+    node _T_615 = cat(_T_614, _T_613) @[Cat.scala 29:58]
+    quotient_new <= _T_615 @[exu_div_ctl.scala 832:16]
+    node _T_616 = bits(b_ff, 31, 0) @[exu_div_ctl.scala 847:48]
+    node _T_617 = mux(twos_comp_q_sel, q_ff, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_618 = mux(twos_comp_b_sel, _T_616, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_619 = or(_T_617, _T_618) @[Mux.scala 27:72]
+    wire twos_comp_in : UInt<32> @[Mux.scala 27:72]
+    twos_comp_in <= _T_619 @[Mux.scala 27:72]
+    wire _T_620 : UInt<1>[31] @[lib.scala 426:20]
+    node _T_621 = bits(twos_comp_in, 0, 0) @[lib.scala 428:27]
+    node _T_622 = orr(_T_621) @[lib.scala 428:35]
+    node _T_623 = bits(twos_comp_in, 1, 1) @[lib.scala 428:44]
+    node _T_624 = not(_T_623) @[lib.scala 428:40]
+    node _T_625 = bits(twos_comp_in, 1, 1) @[lib.scala 428:51]
+    node _T_626 = mux(_T_622, _T_624, _T_625) @[lib.scala 428:23]
+    _T_620[0] <= _T_626 @[lib.scala 428:17]
+    node _T_627 = bits(twos_comp_in, 1, 0) @[lib.scala 428:27]
+    node _T_628 = orr(_T_627) @[lib.scala 428:35]
+    node _T_629 = bits(twos_comp_in, 2, 2) @[lib.scala 428:44]
+    node _T_630 = not(_T_629) @[lib.scala 428:40]
+    node _T_631 = bits(twos_comp_in, 2, 2) @[lib.scala 428:51]
+    node _T_632 = mux(_T_628, _T_630, _T_631) @[lib.scala 428:23]
+    _T_620[1] <= _T_632 @[lib.scala 428:17]
+    node _T_633 = bits(twos_comp_in, 2, 0) @[lib.scala 428:27]
+    node _T_634 = orr(_T_633) @[lib.scala 428:35]
+    node _T_635 = bits(twos_comp_in, 3, 3) @[lib.scala 428:44]
+    node _T_636 = not(_T_635) @[lib.scala 428:40]
+    node _T_637 = bits(twos_comp_in, 3, 3) @[lib.scala 428:51]
+    node _T_638 = mux(_T_634, _T_636, _T_637) @[lib.scala 428:23]
+    _T_620[2] <= _T_638 @[lib.scala 428:17]
+    node _T_639 = bits(twos_comp_in, 3, 0) @[lib.scala 428:27]
+    node _T_640 = orr(_T_639) @[lib.scala 428:35]
+    node _T_641 = bits(twos_comp_in, 4, 4) @[lib.scala 428:44]
+    node _T_642 = not(_T_641) @[lib.scala 428:40]
+    node _T_643 = bits(twos_comp_in, 4, 4) @[lib.scala 428:51]
+    node _T_644 = mux(_T_640, _T_642, _T_643) @[lib.scala 428:23]
+    _T_620[3] <= _T_644 @[lib.scala 428:17]
+    node _T_645 = bits(twos_comp_in, 4, 0) @[lib.scala 428:27]
+    node _T_646 = orr(_T_645) @[lib.scala 428:35]
+    node _T_647 = bits(twos_comp_in, 5, 5) @[lib.scala 428:44]
+    node _T_648 = not(_T_647) @[lib.scala 428:40]
+    node _T_649 = bits(twos_comp_in, 5, 5) @[lib.scala 428:51]
+    node _T_650 = mux(_T_646, _T_648, _T_649) @[lib.scala 428:23]
+    _T_620[4] <= _T_650 @[lib.scala 428:17]
+    node _T_651 = bits(twos_comp_in, 5, 0) @[lib.scala 428:27]
+    node _T_652 = orr(_T_651) @[lib.scala 428:35]
+    node _T_653 = bits(twos_comp_in, 6, 6) @[lib.scala 428:44]
+    node _T_654 = not(_T_653) @[lib.scala 428:40]
+    node _T_655 = bits(twos_comp_in, 6, 6) @[lib.scala 428:51]
+    node _T_656 = mux(_T_652, _T_654, _T_655) @[lib.scala 428:23]
+    _T_620[5] <= _T_656 @[lib.scala 428:17]
+    node _T_657 = bits(twos_comp_in, 6, 0) @[lib.scala 428:27]
+    node _T_658 = orr(_T_657) @[lib.scala 428:35]
+    node _T_659 = bits(twos_comp_in, 7, 7) @[lib.scala 428:44]
+    node _T_660 = not(_T_659) @[lib.scala 428:40]
+    node _T_661 = bits(twos_comp_in, 7, 7) @[lib.scala 428:51]
+    node _T_662 = mux(_T_658, _T_660, _T_661) @[lib.scala 428:23]
+    _T_620[6] <= _T_662 @[lib.scala 428:17]
+    node _T_663 = bits(twos_comp_in, 7, 0) @[lib.scala 428:27]
+    node _T_664 = orr(_T_663) @[lib.scala 428:35]
+    node _T_665 = bits(twos_comp_in, 8, 8) @[lib.scala 428:44]
+    node _T_666 = not(_T_665) @[lib.scala 428:40]
+    node _T_667 = bits(twos_comp_in, 8, 8) @[lib.scala 428:51]
+    node _T_668 = mux(_T_664, _T_666, _T_667) @[lib.scala 428:23]
+    _T_620[7] <= _T_668 @[lib.scala 428:17]
+    node _T_669 = bits(twos_comp_in, 8, 0) @[lib.scala 428:27]
+    node _T_670 = orr(_T_669) @[lib.scala 428:35]
+    node _T_671 = bits(twos_comp_in, 9, 9) @[lib.scala 428:44]
+    node _T_672 = not(_T_671) @[lib.scala 428:40]
+    node _T_673 = bits(twos_comp_in, 9, 9) @[lib.scala 428:51]
+    node _T_674 = mux(_T_670, _T_672, _T_673) @[lib.scala 428:23]
+    _T_620[8] <= _T_674 @[lib.scala 428:17]
+    node _T_675 = bits(twos_comp_in, 9, 0) @[lib.scala 428:27]
+    node _T_676 = orr(_T_675) @[lib.scala 428:35]
+    node _T_677 = bits(twos_comp_in, 10, 10) @[lib.scala 428:44]
+    node _T_678 = not(_T_677) @[lib.scala 428:40]
+    node _T_679 = bits(twos_comp_in, 10, 10) @[lib.scala 428:51]
+    node _T_680 = mux(_T_676, _T_678, _T_679) @[lib.scala 428:23]
+    _T_620[9] <= _T_680 @[lib.scala 428:17]
+    node _T_681 = bits(twos_comp_in, 10, 0) @[lib.scala 428:27]
+    node _T_682 = orr(_T_681) @[lib.scala 428:35]
+    node _T_683 = bits(twos_comp_in, 11, 11) @[lib.scala 428:44]
+    node _T_684 = not(_T_683) @[lib.scala 428:40]
+    node _T_685 = bits(twos_comp_in, 11, 11) @[lib.scala 428:51]
+    node _T_686 = mux(_T_682, _T_684, _T_685) @[lib.scala 428:23]
+    _T_620[10] <= _T_686 @[lib.scala 428:17]
+    node _T_687 = bits(twos_comp_in, 11, 0) @[lib.scala 428:27]
+    node _T_688 = orr(_T_687) @[lib.scala 428:35]
+    node _T_689 = bits(twos_comp_in, 12, 12) @[lib.scala 428:44]
+    node _T_690 = not(_T_689) @[lib.scala 428:40]
+    node _T_691 = bits(twos_comp_in, 12, 12) @[lib.scala 428:51]
+    node _T_692 = mux(_T_688, _T_690, _T_691) @[lib.scala 428:23]
+    _T_620[11] <= _T_692 @[lib.scala 428:17]
+    node _T_693 = bits(twos_comp_in, 12, 0) @[lib.scala 428:27]
+    node _T_694 = orr(_T_693) @[lib.scala 428:35]
+    node _T_695 = bits(twos_comp_in, 13, 13) @[lib.scala 428:44]
+    node _T_696 = not(_T_695) @[lib.scala 428:40]
+    node _T_697 = bits(twos_comp_in, 13, 13) @[lib.scala 428:51]
+    node _T_698 = mux(_T_694, _T_696, _T_697) @[lib.scala 428:23]
+    _T_620[12] <= _T_698 @[lib.scala 428:17]
+    node _T_699 = bits(twos_comp_in, 13, 0) @[lib.scala 428:27]
+    node _T_700 = orr(_T_699) @[lib.scala 428:35]
+    node _T_701 = bits(twos_comp_in, 14, 14) @[lib.scala 428:44]
+    node _T_702 = not(_T_701) @[lib.scala 428:40]
+    node _T_703 = bits(twos_comp_in, 14, 14) @[lib.scala 428:51]
+    node _T_704 = mux(_T_700, _T_702, _T_703) @[lib.scala 428:23]
+    _T_620[13] <= _T_704 @[lib.scala 428:17]
+    node _T_705 = bits(twos_comp_in, 14, 0) @[lib.scala 428:27]
+    node _T_706 = orr(_T_705) @[lib.scala 428:35]
+    node _T_707 = bits(twos_comp_in, 15, 15) @[lib.scala 428:44]
+    node _T_708 = not(_T_707) @[lib.scala 428:40]
+    node _T_709 = bits(twos_comp_in, 15, 15) @[lib.scala 428:51]
+    node _T_710 = mux(_T_706, _T_708, _T_709) @[lib.scala 428:23]
+    _T_620[14] <= _T_710 @[lib.scala 428:17]
+    node _T_711 = bits(twos_comp_in, 15, 0) @[lib.scala 428:27]
+    node _T_712 = orr(_T_711) @[lib.scala 428:35]
+    node _T_713 = bits(twos_comp_in, 16, 16) @[lib.scala 428:44]
+    node _T_714 = not(_T_713) @[lib.scala 428:40]
+    node _T_715 = bits(twos_comp_in, 16, 16) @[lib.scala 428:51]
+    node _T_716 = mux(_T_712, _T_714, _T_715) @[lib.scala 428:23]
+    _T_620[15] <= _T_716 @[lib.scala 428:17]
+    node _T_717 = bits(twos_comp_in, 16, 0) @[lib.scala 428:27]
+    node _T_718 = orr(_T_717) @[lib.scala 428:35]
+    node _T_719 = bits(twos_comp_in, 17, 17) @[lib.scala 428:44]
+    node _T_720 = not(_T_719) @[lib.scala 428:40]
+    node _T_721 = bits(twos_comp_in, 17, 17) @[lib.scala 428:51]
+    node _T_722 = mux(_T_718, _T_720, _T_721) @[lib.scala 428:23]
+    _T_620[16] <= _T_722 @[lib.scala 428:17]
+    node _T_723 = bits(twos_comp_in, 17, 0) @[lib.scala 428:27]
+    node _T_724 = orr(_T_723) @[lib.scala 428:35]
+    node _T_725 = bits(twos_comp_in, 18, 18) @[lib.scala 428:44]
+    node _T_726 = not(_T_725) @[lib.scala 428:40]
+    node _T_727 = bits(twos_comp_in, 18, 18) @[lib.scala 428:51]
+    node _T_728 = mux(_T_724, _T_726, _T_727) @[lib.scala 428:23]
+    _T_620[17] <= _T_728 @[lib.scala 428:17]
+    node _T_729 = bits(twos_comp_in, 18, 0) @[lib.scala 428:27]
+    node _T_730 = orr(_T_729) @[lib.scala 428:35]
+    node _T_731 = bits(twos_comp_in, 19, 19) @[lib.scala 428:44]
+    node _T_732 = not(_T_731) @[lib.scala 428:40]
+    node _T_733 = bits(twos_comp_in, 19, 19) @[lib.scala 428:51]
+    node _T_734 = mux(_T_730, _T_732, _T_733) @[lib.scala 428:23]
+    _T_620[18] <= _T_734 @[lib.scala 428:17]
+    node _T_735 = bits(twos_comp_in, 19, 0) @[lib.scala 428:27]
+    node _T_736 = orr(_T_735) @[lib.scala 428:35]
+    node _T_737 = bits(twos_comp_in, 20, 20) @[lib.scala 428:44]
+    node _T_738 = not(_T_737) @[lib.scala 428:40]
+    node _T_739 = bits(twos_comp_in, 20, 20) @[lib.scala 428:51]
+    node _T_740 = mux(_T_736, _T_738, _T_739) @[lib.scala 428:23]
+    _T_620[19] <= _T_740 @[lib.scala 428:17]
+    node _T_741 = bits(twos_comp_in, 20, 0) @[lib.scala 428:27]
+    node _T_742 = orr(_T_741) @[lib.scala 428:35]
+    node _T_743 = bits(twos_comp_in, 21, 21) @[lib.scala 428:44]
+    node _T_744 = not(_T_743) @[lib.scala 428:40]
+    node _T_745 = bits(twos_comp_in, 21, 21) @[lib.scala 428:51]
+    node _T_746 = mux(_T_742, _T_744, _T_745) @[lib.scala 428:23]
+    _T_620[20] <= _T_746 @[lib.scala 428:17]
+    node _T_747 = bits(twos_comp_in, 21, 0) @[lib.scala 428:27]
+    node _T_748 = orr(_T_747) @[lib.scala 428:35]
+    node _T_749 = bits(twos_comp_in, 22, 22) @[lib.scala 428:44]
+    node _T_750 = not(_T_749) @[lib.scala 428:40]
+    node _T_751 = bits(twos_comp_in, 22, 22) @[lib.scala 428:51]
+    node _T_752 = mux(_T_748, _T_750, _T_751) @[lib.scala 428:23]
+    _T_620[21] <= _T_752 @[lib.scala 428:17]
+    node _T_753 = bits(twos_comp_in, 22, 0) @[lib.scala 428:27]
+    node _T_754 = orr(_T_753) @[lib.scala 428:35]
+    node _T_755 = bits(twos_comp_in, 23, 23) @[lib.scala 428:44]
+    node _T_756 = not(_T_755) @[lib.scala 428:40]
+    node _T_757 = bits(twos_comp_in, 23, 23) @[lib.scala 428:51]
+    node _T_758 = mux(_T_754, _T_756, _T_757) @[lib.scala 428:23]
+    _T_620[22] <= _T_758 @[lib.scala 428:17]
+    node _T_759 = bits(twos_comp_in, 23, 0) @[lib.scala 428:27]
+    node _T_760 = orr(_T_759) @[lib.scala 428:35]
+    node _T_761 = bits(twos_comp_in, 24, 24) @[lib.scala 428:44]
+    node _T_762 = not(_T_761) @[lib.scala 428:40]
+    node _T_763 = bits(twos_comp_in, 24, 24) @[lib.scala 428:51]
+    node _T_764 = mux(_T_760, _T_762, _T_763) @[lib.scala 428:23]
+    _T_620[23] <= _T_764 @[lib.scala 428:17]
+    node _T_765 = bits(twos_comp_in, 24, 0) @[lib.scala 428:27]
+    node _T_766 = orr(_T_765) @[lib.scala 428:35]
+    node _T_767 = bits(twos_comp_in, 25, 25) @[lib.scala 428:44]
+    node _T_768 = not(_T_767) @[lib.scala 428:40]
+    node _T_769 = bits(twos_comp_in, 25, 25) @[lib.scala 428:51]
+    node _T_770 = mux(_T_766, _T_768, _T_769) @[lib.scala 428:23]
+    _T_620[24] <= _T_770 @[lib.scala 428:17]
+    node _T_771 = bits(twos_comp_in, 25, 0) @[lib.scala 428:27]
+    node _T_772 = orr(_T_771) @[lib.scala 428:35]
+    node _T_773 = bits(twos_comp_in, 26, 26) @[lib.scala 428:44]
+    node _T_774 = not(_T_773) @[lib.scala 428:40]
+    node _T_775 = bits(twos_comp_in, 26, 26) @[lib.scala 428:51]
+    node _T_776 = mux(_T_772, _T_774, _T_775) @[lib.scala 428:23]
+    _T_620[25] <= _T_776 @[lib.scala 428:17]
+    node _T_777 = bits(twos_comp_in, 26, 0) @[lib.scala 428:27]
+    node _T_778 = orr(_T_777) @[lib.scala 428:35]
+    node _T_779 = bits(twos_comp_in, 27, 27) @[lib.scala 428:44]
+    node _T_780 = not(_T_779) @[lib.scala 428:40]
+    node _T_781 = bits(twos_comp_in, 27, 27) @[lib.scala 428:51]
+    node _T_782 = mux(_T_778, _T_780, _T_781) @[lib.scala 428:23]
+    _T_620[26] <= _T_782 @[lib.scala 428:17]
+    node _T_783 = bits(twos_comp_in, 27, 0) @[lib.scala 428:27]
+    node _T_784 = orr(_T_783) @[lib.scala 428:35]
+    node _T_785 = bits(twos_comp_in, 28, 28) @[lib.scala 428:44]
+    node _T_786 = not(_T_785) @[lib.scala 428:40]
+    node _T_787 = bits(twos_comp_in, 28, 28) @[lib.scala 428:51]
+    node _T_788 = mux(_T_784, _T_786, _T_787) @[lib.scala 428:23]
+    _T_620[27] <= _T_788 @[lib.scala 428:17]
+    node _T_789 = bits(twos_comp_in, 28, 0) @[lib.scala 428:27]
+    node _T_790 = orr(_T_789) @[lib.scala 428:35]
+    node _T_791 = bits(twos_comp_in, 29, 29) @[lib.scala 428:44]
+    node _T_792 = not(_T_791) @[lib.scala 428:40]
+    node _T_793 = bits(twos_comp_in, 29, 29) @[lib.scala 428:51]
+    node _T_794 = mux(_T_790, _T_792, _T_793) @[lib.scala 428:23]
+    _T_620[28] <= _T_794 @[lib.scala 428:17]
+    node _T_795 = bits(twos_comp_in, 29, 0) @[lib.scala 428:27]
+    node _T_796 = orr(_T_795) @[lib.scala 428:35]
+    node _T_797 = bits(twos_comp_in, 30, 30) @[lib.scala 428:44]
+    node _T_798 = not(_T_797) @[lib.scala 428:40]
+    node _T_799 = bits(twos_comp_in, 30, 30) @[lib.scala 428:51]
+    node _T_800 = mux(_T_796, _T_798, _T_799) @[lib.scala 428:23]
+    _T_620[29] <= _T_800 @[lib.scala 428:17]
+    node _T_801 = bits(twos_comp_in, 30, 0) @[lib.scala 428:27]
+    node _T_802 = orr(_T_801) @[lib.scala 428:35]
+    node _T_803 = bits(twos_comp_in, 31, 31) @[lib.scala 428:44]
+    node _T_804 = not(_T_803) @[lib.scala 428:40]
+    node _T_805 = bits(twos_comp_in, 31, 31) @[lib.scala 428:51]
+    node _T_806 = mux(_T_802, _T_804, _T_805) @[lib.scala 428:23]
+    _T_620[30] <= _T_806 @[lib.scala 428:17]
+    node _T_807 = cat(_T_620[2], _T_620[1]) @[lib.scala 430:14]
+    node _T_808 = cat(_T_807, _T_620[0]) @[lib.scala 430:14]
+    node _T_809 = cat(_T_620[4], _T_620[3]) @[lib.scala 430:14]
+    node _T_810 = cat(_T_620[6], _T_620[5]) @[lib.scala 430:14]
+    node _T_811 = cat(_T_810, _T_809) @[lib.scala 430:14]
+    node _T_812 = cat(_T_811, _T_808) @[lib.scala 430:14]
+    node _T_813 = cat(_T_620[8], _T_620[7]) @[lib.scala 430:14]
+    node _T_814 = cat(_T_620[10], _T_620[9]) @[lib.scala 430:14]
+    node _T_815 = cat(_T_814, _T_813) @[lib.scala 430:14]
+    node _T_816 = cat(_T_620[12], _T_620[11]) @[lib.scala 430:14]
+    node _T_817 = cat(_T_620[14], _T_620[13]) @[lib.scala 430:14]
+    node _T_818 = cat(_T_817, _T_816) @[lib.scala 430:14]
+    node _T_819 = cat(_T_818, _T_815) @[lib.scala 430:14]
+    node _T_820 = cat(_T_819, _T_812) @[lib.scala 430:14]
+    node _T_821 = cat(_T_620[16], _T_620[15]) @[lib.scala 430:14]
+    node _T_822 = cat(_T_620[18], _T_620[17]) @[lib.scala 430:14]
+    node _T_823 = cat(_T_822, _T_821) @[lib.scala 430:14]
+    node _T_824 = cat(_T_620[20], _T_620[19]) @[lib.scala 430:14]
+    node _T_825 = cat(_T_620[22], _T_620[21]) @[lib.scala 430:14]
+    node _T_826 = cat(_T_825, _T_824) @[lib.scala 430:14]
+    node _T_827 = cat(_T_826, _T_823) @[lib.scala 430:14]
+    node _T_828 = cat(_T_620[24], _T_620[23]) @[lib.scala 430:14]
+    node _T_829 = cat(_T_620[26], _T_620[25]) @[lib.scala 430:14]
+    node _T_830 = cat(_T_829, _T_828) @[lib.scala 430:14]
+    node _T_831 = cat(_T_620[28], _T_620[27]) @[lib.scala 430:14]
+    node _T_832 = cat(_T_620[30], _T_620[29]) @[lib.scala 430:14]
+    node _T_833 = cat(_T_832, _T_831) @[lib.scala 430:14]
+    node _T_834 = cat(_T_833, _T_830) @[lib.scala 430:14]
+    node _T_835 = cat(_T_834, _T_827) @[lib.scala 430:14]
+    node _T_836 = cat(_T_835, _T_820) @[lib.scala 430:14]
+    node _T_837 = bits(twos_comp_in, 0, 0) @[lib.scala 430:24]
+    node twos_comp_out = cat(_T_836, _T_837) @[Cat.scala 29:58]
+    node _T_838 = eq(a_shift, UInt<1>("h00")) @[exu_div_ctl.scala 851:6]
+    node _T_839 = eq(shortq_enable_ff, UInt<1>("h00")) @[exu_div_ctl.scala 851:17]
+    node _T_840 = and(_T_838, _T_839) @[exu_div_ctl.scala 851:15]
+    node _T_841 = bits(_T_840, 0, 0) @[exu_div_ctl.scala 851:36]
+    node _T_842 = bits(io.dividend_in, 31, 0) @[exu_div_ctl.scala 851:60]
+    node _T_843 = bits(a_ff, 27, 0) @[exu_div_ctl.scala 852:53]
+    node _T_844 = cat(_T_843, UInt<4>("h00")) @[Cat.scala 29:58]
+    node _T_845 = bits(ar_shifted, 31, 0) @[exu_div_ctl.scala 853:55]
+    node _T_846 = mux(_T_841, _T_842, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_847 = mux(a_shift, _T_844, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_848 = mux(shortq_enable_ff, _T_845, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_849 = or(_T_846, _T_847) @[Mux.scala 27:72]
+    node _T_850 = or(_T_849, _T_848) @[Mux.scala 27:72]
+    wire a_in : UInt<32> @[Mux.scala 27:72]
+    a_in <= _T_850 @[Mux.scala 27:72]
+    node _T_851 = eq(b_twos_comp, UInt<1>("h00")) @[exu_div_ctl.scala 856:5]
+    node _T_852 = bits(io.divisor_in, 31, 31) @[exu_div_ctl.scala 856:78]
+    node _T_853 = and(io.signed_in, _T_852) @[exu_div_ctl.scala 856:63]
+    node _T_854 = bits(io.divisor_in, 31, 0) @[exu_div_ctl.scala 856:96]
+    node _T_855 = cat(_T_853, _T_854) @[Cat.scala 29:58]
+    node _T_856 = eq(divisor_sign_ff, UInt<1>("h00")) @[exu_div_ctl.scala 857:49]
+    node _T_857 = bits(twos_comp_out, 31, 0) @[exu_div_ctl.scala 857:79]
+    node _T_858 = cat(_T_856, _T_857) @[Cat.scala 29:58]
+    node _T_859 = mux(_T_851, _T_855, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_860 = mux(b_twos_comp, _T_858, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_861 = or(_T_859, _T_860) @[Mux.scala 27:72]
+    wire b_in : UInt<33> @[Mux.scala 27:72]
+    b_in <= _T_861 @[Mux.scala 27:72]
+    node _T_862 = mux(UInt<1>("h01"), UInt<33>("h01ffffffff"), UInt<33>("h00")) @[Bitwise.scala 72:12]
+    node _T_863 = bits(r_ff, 28, 0) @[exu_div_ctl.scala 861:54]
+    node _T_864 = bits(a_ff, 31, 28) @[exu_div_ctl.scala 861:65]
+    node _T_865 = cat(_T_863, _T_864) @[Cat.scala 29:58]
+    node _T_866 = bits(adder1_out, 32, 0) @[exu_div_ctl.scala 862:56]
+    node _T_867 = bits(adder2_out, 32, 0) @[exu_div_ctl.scala 863:56]
+    node _T_868 = bits(adder3_out, 32, 0) @[exu_div_ctl.scala 864:56]
+    node _T_869 = bits(adder4_out, 32, 0) @[exu_div_ctl.scala 865:56]
+    node _T_870 = bits(adder5_out, 32, 0) @[exu_div_ctl.scala 866:56]
+    node _T_871 = bits(adder6_out, 32, 0) @[exu_div_ctl.scala 867:56]
+    node _T_872 = bits(adder7_out, 32, 0) @[exu_div_ctl.scala 868:56]
+    node _T_873 = bits(adder8_out, 32, 0) @[exu_div_ctl.scala 869:56]
+    node _T_874 = bits(adder9_out, 32, 0) @[exu_div_ctl.scala 870:56]
+    node _T_875 = bits(adder10_out, 32, 0) @[exu_div_ctl.scala 871:57]
+    node _T_876 = bits(adder11_out, 32, 0) @[exu_div_ctl.scala 872:57]
+    node _T_877 = bits(adder12_out, 32, 0) @[exu_div_ctl.scala 873:57]
+    node _T_878 = bits(adder13_out, 32, 0) @[exu_div_ctl.scala 874:57]
+    node _T_879 = bits(adder14_out, 32, 0) @[exu_div_ctl.scala 875:57]
+    node _T_880 = bits(adder15_out, 32, 0) @[exu_div_ctl.scala 876:57]
+    node _T_881 = bits(ar_shifted, 64, 32) @[exu_div_ctl.scala 877:56]
+    node _T_882 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 878:58]
+    node _T_883 = cat(UInt<1>("h00"), _T_882) @[Cat.scala 29:58]
+    node _T_884 = mux(r_sign_sel, _T_862, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_885 = mux(r_adder_sel_0, _T_865, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_886 = mux(r_adder_sel_1, _T_866, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_887 = mux(r_adder_sel_2, _T_867, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_888 = mux(r_adder_sel_3, _T_868, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_889 = mux(r_adder_sel_4, _T_869, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_890 = mux(r_adder_sel_5, _T_870, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_891 = mux(r_adder_sel_6, _T_871, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_892 = mux(r_adder_sel_7, _T_872, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_893 = mux(r_adder_sel_8, _T_873, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_894 = mux(r_adder_sel_9, _T_874, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_895 = mux(r_adder_sel_10, _T_875, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_896 = mux(r_adder_sel_11, _T_876, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_897 = mux(r_adder_sel_12, _T_877, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_898 = mux(r_adder_sel_13, _T_878, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_899 = mux(r_adder_sel_14, _T_879, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_900 = mux(r_adder_sel_15, _T_880, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_901 = mux(shortq_enable_ff, _T_881, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_902 = mux(by_zero_case, _T_883, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_903 = or(_T_884, _T_885) @[Mux.scala 27:72]
+    node _T_904 = or(_T_903, _T_886) @[Mux.scala 27:72]
+    node _T_905 = or(_T_904, _T_887) @[Mux.scala 27:72]
+    node _T_906 = or(_T_905, _T_888) @[Mux.scala 27:72]
+    node _T_907 = or(_T_906, _T_889) @[Mux.scala 27:72]
+    node _T_908 = or(_T_907, _T_890) @[Mux.scala 27:72]
+    node _T_909 = or(_T_908, _T_891) @[Mux.scala 27:72]
+    node _T_910 = or(_T_909, _T_892) @[Mux.scala 27:72]
+    node _T_911 = or(_T_910, _T_893) @[Mux.scala 27:72]
+    node _T_912 = or(_T_911, _T_894) @[Mux.scala 27:72]
+    node _T_913 = or(_T_912, _T_895) @[Mux.scala 27:72]
+    node _T_914 = or(_T_913, _T_896) @[Mux.scala 27:72]
+    node _T_915 = or(_T_914, _T_897) @[Mux.scala 27:72]
+    node _T_916 = or(_T_915, _T_898) @[Mux.scala 27:72]
+    node _T_917 = or(_T_916, _T_899) @[Mux.scala 27:72]
+    node _T_918 = or(_T_917, _T_900) @[Mux.scala 27:72]
+    node _T_919 = or(_T_918, _T_901) @[Mux.scala 27:72]
+    node _T_920 = or(_T_919, _T_902) @[Mux.scala 27:72]
+    wire r_in : UInt<33> @[Mux.scala 27:72]
+    r_in <= _T_920 @[Mux.scala 27:72]
+    node _T_921 = eq(valid_ff, UInt<1>("h00")) @[exu_div_ctl.scala 881:5]
+    node _T_922 = bits(q_ff, 27, 0) @[exu_div_ctl.scala 881:55]
+    node _T_923 = cat(_T_922, quotient_new) @[Cat.scala 29:58]
+    node _T_924 = cat(UInt<28>("h00"), smallnum) @[Cat.scala 29:58]
+    node _T_925 = mux(UInt<1>("h01"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_926 = mux(_T_921, _T_923, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_927 = mux(smallnum_case, _T_924, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_928 = mux(by_zero_case, _T_925, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_929 = or(_T_926, _T_927) @[Mux.scala 27:72]
+    node _T_930 = or(_T_929, _T_928) @[Mux.scala 27:72]
+    wire q_in : UInt<32> @[Mux.scala 27:72]
+    q_in <= _T_930 @[Mux.scala 27:72]
+    node _T_931 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 885:31]
+    node _T_932 = and(finish_ff, _T_931) @[exu_div_ctl.scala 885:29]
+    io.valid_out <= _T_932 @[exu_div_ctl.scala 885:16]
+    node _T_933 = eq(rem_ff, UInt<1>("h00")) @[exu_div_ctl.scala 887:6]
+    node _T_934 = eq(twos_comp_q_sel, UInt<1>("h00")) @[exu_div_ctl.scala 887:16]
+    node _T_935 = and(_T_933, _T_934) @[exu_div_ctl.scala 887:14]
+    node _T_936 = bits(_T_935, 0, 0) @[exu_div_ctl.scala 887:40]
+    node _T_937 = bits(r_ff, 31, 0) @[exu_div_ctl.scala 888:48]
+    node _T_938 = mux(_T_936, q_ff, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_939 = mux(rem_ff, _T_937, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_940 = mux(twos_comp_q_sel, twos_comp_out, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_941 = or(_T_938, _T_939) @[Mux.scala 27:72]
+    node _T_942 = or(_T_941, _T_940) @[Mux.scala 27:72]
+    wire _T_943 : UInt<32> @[Mux.scala 27:72]
+    _T_943 <= _T_942 @[Mux.scala 27:72]
+    io.data_out <= _T_943 @[exu_div_ctl.scala 886:15]
+    node _T_944 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_945 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_946 = eq(_T_945, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_947 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:75]
+    node _T_948 = eq(_T_947, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_949 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:75]
+    node _T_950 = eq(_T_949, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_951 = and(_T_946, _T_948) @[exu_div_ctl.scala 893:95]
+    node _T_952 = and(_T_951, _T_950) @[exu_div_ctl.scala 893:95]
+    node _T_953 = and(_T_944, _T_952) @[exu_div_ctl.scala 894:11]
+    node _T_954 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_955 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_956 = eq(_T_955, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_957 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:75]
+    node _T_958 = eq(_T_957, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_959 = and(_T_956, _T_958) @[exu_div_ctl.scala 893:95]
+    node _T_960 = and(_T_954, _T_959) @[exu_div_ctl.scala 894:11]
+    node _T_961 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 899:38]
+    node _T_962 = eq(_T_961, UInt<1>("h00")) @[exu_div_ctl.scala 899:33]
+    node _T_963 = and(_T_960, _T_962) @[exu_div_ctl.scala 899:31]
+    node _T_964 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:58]
+    node _T_965 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_966 = eq(_T_965, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_967 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:75]
+    node _T_968 = eq(_T_967, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_969 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:75]
+    node _T_970 = eq(_T_969, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_971 = and(_T_966, _T_968) @[exu_div_ctl.scala 893:95]
+    node _T_972 = and(_T_971, _T_970) @[exu_div_ctl.scala 893:95]
+    node _T_973 = and(_T_964, _T_972) @[exu_div_ctl.scala 894:11]
+    node _T_974 = or(_T_963, _T_973) @[exu_div_ctl.scala 899:42]
+    node _T_975 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_976 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:58]
+    node _T_977 = and(_T_975, _T_976) @[exu_div_ctl.scala 892:95]
+    node _T_978 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_979 = eq(_T_978, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_980 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:75]
+    node _T_981 = eq(_T_980, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_982 = and(_T_979, _T_981) @[exu_div_ctl.scala 893:95]
+    node _T_983 = and(_T_977, _T_982) @[exu_div_ctl.scala 894:11]
+    node _T_984 = or(_T_974, _T_983) @[exu_div_ctl.scala 899:75]
+    node _T_985 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:58]
+    node _T_986 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_987 = eq(_T_986, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_988 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:75]
+    node _T_989 = eq(_T_988, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_990 = and(_T_987, _T_989) @[exu_div_ctl.scala 893:95]
+    node _T_991 = and(_T_985, _T_990) @[exu_div_ctl.scala 894:11]
+    node _T_992 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 901:38]
+    node _T_993 = eq(_T_992, UInt<1>("h00")) @[exu_div_ctl.scala 901:33]
+    node _T_994 = and(_T_991, _T_993) @[exu_div_ctl.scala 901:31]
+    node _T_995 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 892:58]
+    node _T_996 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_997 = eq(_T_996, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_998 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:75]
+    node _T_999 = eq(_T_998, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1000 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:75]
+    node _T_1001 = eq(_T_1000, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1002 = and(_T_997, _T_999) @[exu_div_ctl.scala 893:95]
+    node _T_1003 = and(_T_1002, _T_1001) @[exu_div_ctl.scala 893:95]
+    node _T_1004 = and(_T_995, _T_1003) @[exu_div_ctl.scala 894:11]
+    node _T_1005 = or(_T_994, _T_1004) @[exu_div_ctl.scala 901:42]
+    node _T_1006 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1007 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1008 = eq(_T_1007, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1009 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:75]
+    node _T_1010 = eq(_T_1009, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1011 = and(_T_1008, _T_1010) @[exu_div_ctl.scala 893:95]
+    node _T_1012 = and(_T_1006, _T_1011) @[exu_div_ctl.scala 894:11]
+    node _T_1013 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 901:113]
+    node _T_1014 = eq(_T_1013, UInt<1>("h00")) @[exu_div_ctl.scala 901:108]
+    node _T_1015 = and(_T_1012, _T_1014) @[exu_div_ctl.scala 901:106]
+    node _T_1016 = or(_T_1005, _T_1015) @[exu_div_ctl.scala 901:78]
+    node _T_1017 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1018 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:75]
+    node _T_1019 = eq(_T_1018, UInt<1>("h00")) @[exu_div_ctl.scala 892:70]
+    node _T_1020 = and(_T_1017, _T_1019) @[exu_div_ctl.scala 892:95]
+    node _T_1021 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1022 = eq(_T_1021, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1023 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:75]
+    node _T_1024 = eq(_T_1023, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1025 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:58]
+    node _T_1026 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 893:58]
+    node _T_1027 = and(_T_1022, _T_1024) @[exu_div_ctl.scala 893:95]
+    node _T_1028 = and(_T_1027, _T_1025) @[exu_div_ctl.scala 893:95]
+    node _T_1029 = and(_T_1028, _T_1026) @[exu_div_ctl.scala 893:95]
+    node _T_1030 = and(_T_1020, _T_1029) @[exu_div_ctl.scala 894:11]
+    node _T_1031 = or(_T_1016, _T_1030) @[exu_div_ctl.scala 901:117]
+    node _T_1032 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:75]
+    node _T_1033 = eq(_T_1032, UInt<1>("h00")) @[exu_div_ctl.scala 892:70]
+    node _T_1034 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:58]
+    node _T_1035 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 892:58]
+    node _T_1036 = and(_T_1033, _T_1034) @[exu_div_ctl.scala 892:95]
+    node _T_1037 = and(_T_1036, _T_1035) @[exu_div_ctl.scala 892:95]
+    node _T_1038 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1039 = eq(_T_1038, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1040 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:75]
+    node _T_1041 = eq(_T_1040, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1042 = and(_T_1039, _T_1041) @[exu_div_ctl.scala 893:95]
+    node _T_1043 = and(_T_1037, _T_1042) @[exu_div_ctl.scala 894:11]
+    node _T_1044 = or(_T_1031, _T_1043) @[exu_div_ctl.scala 902:44]
+    node _T_1045 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1046 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:58]
+    node _T_1047 = and(_T_1045, _T_1046) @[exu_div_ctl.scala 892:95]
+    node _T_1048 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1049 = eq(_T_1048, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1050 = and(_T_1047, _T_1049) @[exu_div_ctl.scala 894:11]
+    node _T_1051 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 902:114]
+    node _T_1052 = eq(_T_1051, UInt<1>("h00")) @[exu_div_ctl.scala 902:109]
+    node _T_1053 = and(_T_1050, _T_1052) @[exu_div_ctl.scala 902:107]
+    node _T_1054 = or(_T_1044, _T_1053) @[exu_div_ctl.scala 902:80]
+    node _T_1055 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1056 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:58]
+    node _T_1057 = and(_T_1055, _T_1056) @[exu_div_ctl.scala 892:95]
+    node _T_1058 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1059 = eq(_T_1058, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1060 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:58]
+    node _T_1061 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:75]
+    node _T_1062 = eq(_T_1061, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1063 = and(_T_1059, _T_1060) @[exu_div_ctl.scala 893:95]
+    node _T_1064 = and(_T_1063, _T_1062) @[exu_div_ctl.scala 893:95]
+    node _T_1065 = and(_T_1057, _T_1064) @[exu_div_ctl.scala 894:11]
+    node _T_1066 = or(_T_1054, _T_1065) @[exu_div_ctl.scala 902:119]
+    node _T_1067 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1068 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 892:58]
+    node _T_1069 = and(_T_1067, _T_1068) @[exu_div_ctl.scala 892:95]
+    node _T_1070 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1071 = eq(_T_1070, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1072 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:75]
+    node _T_1073 = eq(_T_1072, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1074 = and(_T_1071, _T_1073) @[exu_div_ctl.scala 893:95]
+    node _T_1075 = and(_T_1069, _T_1074) @[exu_div_ctl.scala 894:11]
+    node _T_1076 = or(_T_1066, _T_1075) @[exu_div_ctl.scala 903:44]
+    node _T_1077 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1078 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:58]
+    node _T_1079 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 892:58]
+    node _T_1080 = and(_T_1077, _T_1078) @[exu_div_ctl.scala 892:95]
+    node _T_1081 = and(_T_1080, _T_1079) @[exu_div_ctl.scala 892:95]
+    node _T_1082 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1083 = eq(_T_1082, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1084 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:58]
+    node _T_1085 = and(_T_1083, _T_1084) @[exu_div_ctl.scala 893:95]
+    node _T_1086 = and(_T_1081, _T_1085) @[exu_div_ctl.scala 894:11]
+    node _T_1087 = or(_T_1076, _T_1086) @[exu_div_ctl.scala 903:79]
+    node _T_1088 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:58]
+    node _T_1089 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 892:58]
+    node _T_1090 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 892:58]
+    node _T_1091 = and(_T_1088, _T_1089) @[exu_div_ctl.scala 892:95]
+    node _T_1092 = and(_T_1091, _T_1090) @[exu_div_ctl.scala 892:95]
+    node _T_1093 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1094 = eq(_T_1093, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1095 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:75]
+    node _T_1096 = eq(_T_1095, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1097 = and(_T_1094, _T_1096) @[exu_div_ctl.scala 893:95]
+    node _T_1098 = and(_T_1092, _T_1097) @[exu_div_ctl.scala 894:11]
+    node _T_1099 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1100 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:75]
+    node _T_1101 = eq(_T_1100, UInt<1>("h00")) @[exu_div_ctl.scala 892:70]
+    node _T_1102 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 892:58]
+    node _T_1103 = and(_T_1099, _T_1101) @[exu_div_ctl.scala 892:95]
+    node _T_1104 = and(_T_1103, _T_1102) @[exu_div_ctl.scala 892:95]
+    node _T_1105 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1106 = eq(_T_1105, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1107 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:58]
+    node _T_1108 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 893:58]
+    node _T_1109 = and(_T_1106, _T_1107) @[exu_div_ctl.scala 893:95]
+    node _T_1110 = and(_T_1109, _T_1108) @[exu_div_ctl.scala 893:95]
+    node _T_1111 = and(_T_1104, _T_1110) @[exu_div_ctl.scala 894:11]
+    node _T_1112 = or(_T_1098, _T_1111) @[exu_div_ctl.scala 905:45]
+    node _T_1113 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:58]
+    node _T_1114 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1115 = eq(_T_1114, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1116 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:75]
+    node _T_1117 = eq(_T_1116, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1118 = and(_T_1115, _T_1117) @[exu_div_ctl.scala 893:95]
+    node _T_1119 = and(_T_1113, _T_1118) @[exu_div_ctl.scala 894:11]
+    node _T_1120 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 905:121]
+    node _T_1121 = eq(_T_1120, UInt<1>("h00")) @[exu_div_ctl.scala 905:116]
+    node _T_1122 = and(_T_1119, _T_1121) @[exu_div_ctl.scala 905:114]
+    node _T_1123 = or(_T_1112, _T_1122) @[exu_div_ctl.scala 905:86]
+    node _T_1124 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 892:58]
+    node _T_1125 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1126 = eq(_T_1125, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1127 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:75]
+    node _T_1128 = eq(_T_1127, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1129 = and(_T_1126, _T_1128) @[exu_div_ctl.scala 893:95]
+    node _T_1130 = and(_T_1124, _T_1129) @[exu_div_ctl.scala 894:11]
+    node _T_1131 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 906:40]
+    node _T_1132 = eq(_T_1131, UInt<1>("h00")) @[exu_div_ctl.scala 906:35]
+    node _T_1133 = and(_T_1130, _T_1132) @[exu_div_ctl.scala 906:33]
+    node _T_1134 = or(_T_1123, _T_1133) @[exu_div_ctl.scala 905:129]
+    node _T_1135 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 892:58]
+    node _T_1136 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1137 = eq(_T_1136, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1138 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:75]
+    node _T_1139 = eq(_T_1138, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1140 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:75]
+    node _T_1141 = eq(_T_1140, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1142 = and(_T_1137, _T_1139) @[exu_div_ctl.scala 893:95]
+    node _T_1143 = and(_T_1142, _T_1141) @[exu_div_ctl.scala 893:95]
+    node _T_1144 = and(_T_1135, _T_1143) @[exu_div_ctl.scala 894:11]
+    node _T_1145 = or(_T_1134, _T_1144) @[exu_div_ctl.scala 906:47]
+    node _T_1146 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:75]
+    node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[exu_div_ctl.scala 892:70]
+    node _T_1148 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:58]
+    node _T_1149 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 892:75]
+    node _T_1150 = eq(_T_1149, UInt<1>("h00")) @[exu_div_ctl.scala 892:70]
+    node _T_1151 = and(_T_1147, _T_1148) @[exu_div_ctl.scala 892:95]
+    node _T_1152 = and(_T_1151, _T_1150) @[exu_div_ctl.scala 892:95]
+    node _T_1153 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1154 = eq(_T_1153, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1155 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:75]
+    node _T_1156 = eq(_T_1155, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1157 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:58]
+    node _T_1158 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 893:58]
+    node _T_1159 = and(_T_1154, _T_1156) @[exu_div_ctl.scala 893:95]
+    node _T_1160 = and(_T_1159, _T_1157) @[exu_div_ctl.scala 893:95]
+    node _T_1161 = and(_T_1160, _T_1158) @[exu_div_ctl.scala 893:95]
+    node _T_1162 = and(_T_1152, _T_1161) @[exu_div_ctl.scala 894:11]
+    node _T_1163 = or(_T_1145, _T_1162) @[exu_div_ctl.scala 906:88]
+    node _T_1164 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:75]
+    node _T_1165 = eq(_T_1164, UInt<1>("h00")) @[exu_div_ctl.scala 892:70]
+    node _T_1166 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:58]
+    node _T_1167 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 892:58]
+    node _T_1168 = and(_T_1165, _T_1166) @[exu_div_ctl.scala 892:95]
+    node _T_1169 = and(_T_1168, _T_1167) @[exu_div_ctl.scala 892:95]
+    node _T_1170 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1171 = eq(_T_1170, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1172 = and(_T_1169, _T_1171) @[exu_div_ctl.scala 894:11]
+    node _T_1173 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 907:43]
+    node _T_1174 = eq(_T_1173, UInt<1>("h00")) @[exu_div_ctl.scala 907:38]
+    node _T_1175 = and(_T_1172, _T_1174) @[exu_div_ctl.scala 907:36]
+    node _T_1176 = or(_T_1163, _T_1175) @[exu_div_ctl.scala 906:131]
+    node _T_1177 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1178 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:75]
+    node _T_1179 = eq(_T_1178, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1180 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:75]
+    node _T_1181 = eq(_T_1180, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1182 = and(_T_1179, _T_1181) @[exu_div_ctl.scala 893:95]
+    node _T_1183 = and(_T_1177, _T_1182) @[exu_div_ctl.scala 894:11]
+    node _T_1184 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 907:83]
+    node _T_1185 = eq(_T_1184, UInt<1>("h00")) @[exu_div_ctl.scala 907:78]
+    node _T_1186 = and(_T_1183, _T_1185) @[exu_div_ctl.scala 907:76]
+    node _T_1187 = or(_T_1176, _T_1186) @[exu_div_ctl.scala 907:47]
+    node _T_1188 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1189 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:75]
+    node _T_1190 = eq(_T_1189, UInt<1>("h00")) @[exu_div_ctl.scala 892:70]
+    node _T_1191 = and(_T_1188, _T_1190) @[exu_div_ctl.scala 892:95]
+    node _T_1192 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1193 = eq(_T_1192, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1194 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:58]
+    node _T_1195 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:58]
+    node _T_1196 = and(_T_1193, _T_1194) @[exu_div_ctl.scala 893:95]
+    node _T_1197 = and(_T_1196, _T_1195) @[exu_div_ctl.scala 893:95]
+    node _T_1198 = and(_T_1191, _T_1197) @[exu_div_ctl.scala 894:11]
+    node _T_1199 = or(_T_1187, _T_1198) @[exu_div_ctl.scala 907:88]
+    node _T_1200 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:75]
+    node _T_1201 = eq(_T_1200, UInt<1>("h00")) @[exu_div_ctl.scala 892:70]
+    node _T_1202 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:58]
+    node _T_1203 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 892:58]
+    node _T_1204 = and(_T_1201, _T_1202) @[exu_div_ctl.scala 892:95]
+    node _T_1205 = and(_T_1204, _T_1203) @[exu_div_ctl.scala 892:95]
+    node _T_1206 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1207 = eq(_T_1206, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1208 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:58]
+    node _T_1209 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:75]
+    node _T_1210 = eq(_T_1209, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1211 = and(_T_1207, _T_1208) @[exu_div_ctl.scala 893:95]
+    node _T_1212 = and(_T_1211, _T_1210) @[exu_div_ctl.scala 893:95]
+    node _T_1213 = and(_T_1205, _T_1212) @[exu_div_ctl.scala 894:11]
+    node _T_1214 = or(_T_1199, _T_1213) @[exu_div_ctl.scala 907:131]
+    node _T_1215 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:75]
+    node _T_1216 = eq(_T_1215, UInt<1>("h00")) @[exu_div_ctl.scala 892:70]
+    node _T_1217 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:58]
+    node _T_1218 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 892:58]
+    node _T_1219 = and(_T_1216, _T_1217) @[exu_div_ctl.scala 892:95]
+    node _T_1220 = and(_T_1219, _T_1218) @[exu_div_ctl.scala 892:95]
+    node _T_1221 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1222 = eq(_T_1221, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1223 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:75]
+    node _T_1224 = eq(_T_1223, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1225 = and(_T_1222, _T_1224) @[exu_div_ctl.scala 893:95]
+    node _T_1226 = and(_T_1220, _T_1225) @[exu_div_ctl.scala 894:11]
+    node _T_1227 = or(_T_1214, _T_1226) @[exu_div_ctl.scala 908:47]
+    node _T_1228 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1229 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:75]
+    node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[exu_div_ctl.scala 892:70]
+    node _T_1231 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 892:75]
+    node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[exu_div_ctl.scala 892:70]
+    node _T_1233 = and(_T_1228, _T_1230) @[exu_div_ctl.scala 892:95]
+    node _T_1234 = and(_T_1233, _T_1232) @[exu_div_ctl.scala 892:95]
+    node _T_1235 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1236 = eq(_T_1235, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1237 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:58]
+    node _T_1238 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 893:58]
+    node _T_1239 = and(_T_1236, _T_1237) @[exu_div_ctl.scala 893:95]
+    node _T_1240 = and(_T_1239, _T_1238) @[exu_div_ctl.scala 893:95]
+    node _T_1241 = and(_T_1234, _T_1240) @[exu_div_ctl.scala 894:11]
+    node _T_1242 = or(_T_1227, _T_1241) @[exu_div_ctl.scala 908:88]
+    node _T_1243 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:75]
+    node _T_1244 = eq(_T_1243, UInt<1>("h00")) @[exu_div_ctl.scala 892:70]
+    node _T_1245 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 892:58]
+    node _T_1246 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 892:58]
+    node _T_1247 = and(_T_1244, _T_1245) @[exu_div_ctl.scala 892:95]
+    node _T_1248 = and(_T_1247, _T_1246) @[exu_div_ctl.scala 892:95]
+    node _T_1249 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1250 = eq(_T_1249, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1251 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:75]
+    node _T_1252 = eq(_T_1251, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1253 = and(_T_1250, _T_1252) @[exu_div_ctl.scala 893:95]
+    node _T_1254 = and(_T_1248, _T_1253) @[exu_div_ctl.scala 894:11]
+    node _T_1255 = or(_T_1242, _T_1254) @[exu_div_ctl.scala 908:131]
+    node _T_1256 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1257 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:58]
+    node _T_1258 = and(_T_1256, _T_1257) @[exu_div_ctl.scala 892:95]
+    node _T_1259 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:75]
+    node _T_1260 = eq(_T_1259, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1261 = and(_T_1258, _T_1260) @[exu_div_ctl.scala 894:11]
+    node _T_1262 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 909:82]
+    node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[exu_div_ctl.scala 909:77]
+    node _T_1264 = and(_T_1261, _T_1263) @[exu_div_ctl.scala 909:75]
+    node _T_1265 = or(_T_1255, _T_1264) @[exu_div_ctl.scala 909:47]
+    node _T_1266 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:75]
+    node _T_1267 = eq(_T_1266, UInt<1>("h00")) @[exu_div_ctl.scala 892:70]
+    node _T_1268 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:58]
+    node _T_1269 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 892:58]
+    node _T_1270 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 892:58]
+    node _T_1271 = and(_T_1267, _T_1268) @[exu_div_ctl.scala 892:95]
+    node _T_1272 = and(_T_1271, _T_1269) @[exu_div_ctl.scala 892:95]
+    node _T_1273 = and(_T_1272, _T_1270) @[exu_div_ctl.scala 892:95]
+    node _T_1274 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1275 = eq(_T_1274, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1276 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:58]
+    node _T_1277 = and(_T_1275, _T_1276) @[exu_div_ctl.scala 893:95]
+    node _T_1278 = and(_T_1273, _T_1277) @[exu_div_ctl.scala 894:11]
+    node _T_1279 = or(_T_1265, _T_1278) @[exu_div_ctl.scala 909:88]
+    node _T_1280 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1281 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:58]
+    node _T_1282 = and(_T_1280, _T_1281) @[exu_div_ctl.scala 892:95]
+    node _T_1283 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:58]
+    node _T_1284 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:75]
+    node _T_1285 = eq(_T_1284, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1286 = and(_T_1283, _T_1285) @[exu_div_ctl.scala 893:95]
+    node _T_1287 = and(_T_1282, _T_1286) @[exu_div_ctl.scala 894:11]
+    node _T_1288 = or(_T_1279, _T_1287) @[exu_div_ctl.scala 909:131]
+    node _T_1289 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1290 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 892:58]
+    node _T_1291 = and(_T_1289, _T_1290) @[exu_div_ctl.scala 892:95]
+    node _T_1292 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:58]
+    node _T_1293 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:75]
+    node _T_1294 = eq(_T_1293, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1295 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:75]
+    node _T_1296 = eq(_T_1295, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1297 = and(_T_1292, _T_1294) @[exu_div_ctl.scala 893:95]
+    node _T_1298 = and(_T_1297, _T_1296) @[exu_div_ctl.scala 893:95]
+    node _T_1299 = and(_T_1291, _T_1298) @[exu_div_ctl.scala 894:11]
+    node _T_1300 = or(_T_1288, _T_1299) @[exu_div_ctl.scala 910:47]
+    node _T_1301 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1302 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 892:58]
+    node _T_1303 = and(_T_1301, _T_1302) @[exu_div_ctl.scala 892:95]
+    node _T_1304 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:75]
+    node _T_1305 = eq(_T_1304, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1306 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:75]
+    node _T_1307 = eq(_T_1306, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1308 = and(_T_1305, _T_1307) @[exu_div_ctl.scala 893:95]
+    node _T_1309 = and(_T_1303, _T_1308) @[exu_div_ctl.scala 894:11]
+    node _T_1310 = or(_T_1300, _T_1309) @[exu_div_ctl.scala 910:88]
+    node _T_1311 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1312 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 892:75]
+    node _T_1313 = eq(_T_1312, UInt<1>("h00")) @[exu_div_ctl.scala 892:70]
+    node _T_1314 = and(_T_1311, _T_1313) @[exu_div_ctl.scala 892:95]
+    node _T_1315 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1316 = eq(_T_1315, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1317 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:58]
+    node _T_1318 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:58]
+    node _T_1319 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 893:58]
+    node _T_1320 = and(_T_1316, _T_1317) @[exu_div_ctl.scala 893:95]
+    node _T_1321 = and(_T_1320, _T_1318) @[exu_div_ctl.scala 893:95]
+    node _T_1322 = and(_T_1321, _T_1319) @[exu_div_ctl.scala 893:95]
+    node _T_1323 = and(_T_1314, _T_1322) @[exu_div_ctl.scala 894:11]
+    node _T_1324 = or(_T_1310, _T_1323) @[exu_div_ctl.scala 910:131]
+    node _T_1325 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1326 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:58]
+    node _T_1327 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 892:58]
+    node _T_1328 = and(_T_1325, _T_1326) @[exu_div_ctl.scala 892:95]
+    node _T_1329 = and(_T_1328, _T_1327) @[exu_div_ctl.scala 892:95]
+    node _T_1330 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:58]
+    node _T_1331 = and(_T_1329, _T_1330) @[exu_div_ctl.scala 894:11]
+    node _T_1332 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 911:84]
+    node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[exu_div_ctl.scala 911:79]
+    node _T_1334 = and(_T_1331, _T_1333) @[exu_div_ctl.scala 911:77]
+    node _T_1335 = or(_T_1324, _T_1334) @[exu_div_ctl.scala 911:47]
+    node _T_1336 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1337 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:58]
+    node _T_1338 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 892:58]
+    node _T_1339 = and(_T_1336, _T_1337) @[exu_div_ctl.scala 892:95]
+    node _T_1340 = and(_T_1339, _T_1338) @[exu_div_ctl.scala 892:95]
+    node _T_1341 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:58]
+    node _T_1342 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:75]
+    node _T_1343 = eq(_T_1342, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1344 = and(_T_1341, _T_1343) @[exu_div_ctl.scala 893:95]
+    node _T_1345 = and(_T_1340, _T_1344) @[exu_div_ctl.scala 894:11]
+    node _T_1346 = or(_T_1335, _T_1345) @[exu_div_ctl.scala 911:88]
+    node _T_1347 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1348 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:58]
+    node _T_1349 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 892:58]
+    node _T_1350 = and(_T_1347, _T_1348) @[exu_div_ctl.scala 892:95]
+    node _T_1351 = and(_T_1350, _T_1349) @[exu_div_ctl.scala 892:95]
+    node _T_1352 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:58]
+    node _T_1353 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:75]
+    node _T_1354 = eq(_T_1353, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1355 = and(_T_1352, _T_1354) @[exu_div_ctl.scala 893:95]
+    node _T_1356 = and(_T_1351, _T_1355) @[exu_div_ctl.scala 894:11]
+    node _T_1357 = or(_T_1346, _T_1356) @[exu_div_ctl.scala 911:131]
+    node _T_1358 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1359 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:75]
+    node _T_1360 = eq(_T_1359, UInt<1>("h00")) @[exu_div_ctl.scala 892:70]
+    node _T_1361 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 892:58]
+    node _T_1362 = and(_T_1358, _T_1360) @[exu_div_ctl.scala 892:95]
+    node _T_1363 = and(_T_1362, _T_1361) @[exu_div_ctl.scala 892:95]
+    node _T_1364 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:75]
+    node _T_1365 = eq(_T_1364, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1366 = bits(b_ff, 1, 1) @[exu_div_ctl.scala 893:58]
+    node _T_1367 = and(_T_1365, _T_1366) @[exu_div_ctl.scala 893:95]
+    node _T_1368 = and(_T_1363, _T_1367) @[exu_div_ctl.scala 894:11]
+    node _T_1369 = or(_T_1357, _T_1368) @[exu_div_ctl.scala 912:47]
+    node _T_1370 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1371 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 892:58]
+    node _T_1372 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 892:58]
+    node _T_1373 = and(_T_1370, _T_1371) @[exu_div_ctl.scala 892:95]
+    node _T_1374 = and(_T_1373, _T_1372) @[exu_div_ctl.scala 892:95]
+    node _T_1375 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:75]
+    node _T_1376 = eq(_T_1375, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1377 = and(_T_1374, _T_1376) @[exu_div_ctl.scala 894:11]
+    node _T_1378 = or(_T_1369, _T_1377) @[exu_div_ctl.scala 912:88]
+    node _T_1379 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1380 = bits(a_ff, 2, 2) @[exu_div_ctl.scala 892:58]
+    node _T_1381 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 892:58]
+    node _T_1382 = bits(a_ff, 0, 0) @[exu_div_ctl.scala 892:58]
+    node _T_1383 = and(_T_1379, _T_1380) @[exu_div_ctl.scala 892:95]
+    node _T_1384 = and(_T_1383, _T_1381) @[exu_div_ctl.scala 892:95]
+    node _T_1385 = and(_T_1384, _T_1382) @[exu_div_ctl.scala 892:95]
+    node _T_1386 = bits(b_ff, 3, 3) @[exu_div_ctl.scala 893:58]
+    node _T_1387 = and(_T_1385, _T_1386) @[exu_div_ctl.scala 894:11]
+    node _T_1388 = or(_T_1378, _T_1387) @[exu_div_ctl.scala 912:131]
+    node _T_1389 = bits(a_ff, 3, 3) @[exu_div_ctl.scala 892:58]
+    node _T_1390 = bits(a_ff, 1, 1) @[exu_div_ctl.scala 892:58]
+    node _T_1391 = and(_T_1389, _T_1390) @[exu_div_ctl.scala 892:95]
+    node _T_1392 = bits(b_ff, 2, 2) @[exu_div_ctl.scala 893:75]
+    node _T_1393 = eq(_T_1392, UInt<1>("h00")) @[exu_div_ctl.scala 893:70]
+    node _T_1394 = and(_T_1391, _T_1393) @[exu_div_ctl.scala 894:11]
+    node _T_1395 = bits(b_ff, 0, 0) @[exu_div_ctl.scala 913:81]
+    node _T_1396 = eq(_T_1395, UInt<1>("h00")) @[exu_div_ctl.scala 913:76]
+    node _T_1397 = and(_T_1394, _T_1396) @[exu_div_ctl.scala 913:74]
+    node _T_1398 = or(_T_1388, _T_1397) @[exu_div_ctl.scala 913:47]
+    node _T_1399 = cat(_T_1087, _T_1398) @[Cat.scala 29:58]
+    node _T_1400 = cat(_T_953, _T_984) @[Cat.scala 29:58]
+    node _T_1401 = cat(_T_1400, _T_1399) @[Cat.scala 29:58]
+    smallnum <= _T_1401 @[exu_div_ctl.scala 896:12]
+    node _T_1402 = bits(a_ff, 31, 0) @[exu_div_ctl.scala 916:50]
+    node shortq_dividend = cat(dividend_sign_ff, _T_1402) @[Cat.scala 29:58]
+    inst a_enc of exu_div_cls @[exu_div_ctl.scala 917:21]
+    a_enc.clock <= clock
+    a_enc.reset <= reset
+    a_enc.io.operand <= shortq_dividend @[exu_div_ctl.scala 918:20]
+    inst b_enc of exu_div_cls_1 @[exu_div_ctl.scala 920:21]
+    b_enc.clock <= clock
+    b_enc.reset <= reset
+    node _T_1403 = bits(b_ff, 32, 0) @[exu_div_ctl.scala 921:27]
+    b_enc.io.operand <= _T_1403 @[exu_div_ctl.scala 921:20]
+    node dw_a_enc = cat(UInt<1>("h00"), a_enc.io.cls) @[Cat.scala 29:58]
+    node dw_b_enc = cat(UInt<1>("h00"), b_enc.io.cls) @[Cat.scala 29:58]
+    node _T_1404 = cat(UInt<1>("h00"), dw_b_enc) @[Cat.scala 29:58]
+    node _T_1405 = cat(UInt<1>("h00"), dw_a_enc) @[Cat.scala 29:58]
+    node _T_1406 = sub(_T_1404, _T_1405) @[exu_div_ctl.scala 925:41]
+    node _T_1407 = tail(_T_1406, 1) @[exu_div_ctl.scala 925:41]
+    node _T_1408 = add(_T_1407, UInt<7>("h01")) @[exu_div_ctl.scala 925:61]
+    node dw_shortq_raw = tail(_T_1408, 1) @[exu_div_ctl.scala 925:61]
+    node _T_1409 = bits(dw_shortq_raw, 6, 6) @[exu_div_ctl.scala 926:33]
+    node _T_1410 = bits(_T_1409, 0, 0) @[exu_div_ctl.scala 926:43]
+    node _T_1411 = bits(dw_shortq_raw, 5, 0) @[exu_div_ctl.scala 926:63]
+    node shortq = mux(_T_1410, UInt<1>("h00"), _T_1411) @[exu_div_ctl.scala 926:19]
+    node _T_1412 = bits(shortq, 5, 5) @[exu_div_ctl.scala 927:38]
+    node _T_1413 = eq(_T_1412, UInt<1>("h00")) @[exu_div_ctl.scala 927:31]
+    node _T_1414 = and(valid_ff, _T_1413) @[exu_div_ctl.scala 927:29]
+    node _T_1415 = bits(shortq, 4, 2) @[exu_div_ctl.scala 927:52]
+    node _T_1416 = eq(_T_1415, UInt<3>("h07")) @[exu_div_ctl.scala 927:58]
+    node _T_1417 = eq(_T_1416, UInt<1>("h00")) @[exu_div_ctl.scala 927:44]
+    node _T_1418 = and(_T_1414, _T_1417) @[exu_div_ctl.scala 927:42]
+    node _T_1419 = eq(io.cancel, UInt<1>("h00")) @[exu_div_ctl.scala 927:75]
+    node _T_1420 = and(_T_1418, _T_1419) @[exu_div_ctl.scala 927:73]
+    shortq_enable <= _T_1420 @[exu_div_ctl.scala 927:17]
+    node _T_1421 = eq(shortq, UInt<5>("h01f")) @[exu_div_ctl.scala 929:58]
+    node _T_1422 = eq(shortq, UInt<5>("h01e")) @[exu_div_ctl.scala 929:58]
+    node _T_1423 = eq(shortq, UInt<5>("h01d")) @[exu_div_ctl.scala 929:58]
+    node _T_1424 = eq(shortq, UInt<5>("h01c")) @[exu_div_ctl.scala 929:58]
+    node _T_1425 = eq(shortq, UInt<5>("h01b")) @[exu_div_ctl.scala 929:58]
+    node _T_1426 = eq(shortq, UInt<5>("h01a")) @[exu_div_ctl.scala 929:58]
+    node _T_1427 = eq(shortq, UInt<5>("h019")) @[exu_div_ctl.scala 929:58]
+    node _T_1428 = eq(shortq, UInt<5>("h018")) @[exu_div_ctl.scala 929:58]
+    node _T_1429 = eq(shortq, UInt<5>("h017")) @[exu_div_ctl.scala 929:58]
+    node _T_1430 = eq(shortq, UInt<5>("h016")) @[exu_div_ctl.scala 929:58]
+    node _T_1431 = eq(shortq, UInt<5>("h015")) @[exu_div_ctl.scala 929:58]
+    node _T_1432 = eq(shortq, UInt<5>("h014")) @[exu_div_ctl.scala 929:58]
+    node _T_1433 = eq(shortq, UInt<5>("h013")) @[exu_div_ctl.scala 929:58]
+    node _T_1434 = eq(shortq, UInt<5>("h012")) @[exu_div_ctl.scala 929:58]
+    node _T_1435 = eq(shortq, UInt<5>("h011")) @[exu_div_ctl.scala 929:58]
+    node _T_1436 = eq(shortq, UInt<5>("h010")) @[exu_div_ctl.scala 929:58]
+    node _T_1437 = eq(shortq, UInt<4>("h0f")) @[exu_div_ctl.scala 929:58]
+    node _T_1438 = eq(shortq, UInt<4>("h0e")) @[exu_div_ctl.scala 929:58]
+    node _T_1439 = eq(shortq, UInt<4>("h0d")) @[exu_div_ctl.scala 929:58]
+    node _T_1440 = eq(shortq, UInt<4>("h0c")) @[exu_div_ctl.scala 929:58]
+    node _T_1441 = eq(shortq, UInt<4>("h0b")) @[exu_div_ctl.scala 929:58]
+    node _T_1442 = eq(shortq, UInt<4>("h0a")) @[exu_div_ctl.scala 929:58]
+    node _T_1443 = eq(shortq, UInt<4>("h09")) @[exu_div_ctl.scala 929:58]
+    node _T_1444 = eq(shortq, UInt<4>("h08")) @[exu_div_ctl.scala 929:58]
+    node _T_1445 = eq(shortq, UInt<3>("h07")) @[exu_div_ctl.scala 929:58]
+    node _T_1446 = eq(shortq, UInt<3>("h06")) @[exu_div_ctl.scala 929:58]
+    node _T_1447 = eq(shortq, UInt<3>("h05")) @[exu_div_ctl.scala 929:58]
+    node _T_1448 = eq(shortq, UInt<3>("h04")) @[exu_div_ctl.scala 929:58]
+    node _T_1449 = eq(shortq, UInt<2>("h03")) @[exu_div_ctl.scala 929:58]
+    node _T_1450 = eq(shortq, UInt<2>("h02")) @[exu_div_ctl.scala 929:58]
+    node _T_1451 = eq(shortq, UInt<1>("h01")) @[exu_div_ctl.scala 929:58]
+    node _T_1452 = eq(shortq, UInt<1>("h00")) @[exu_div_ctl.scala 929:58]
+    node _T_1453 = mux(_T_1421, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1454 = mux(_T_1422, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1455 = mux(_T_1423, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1456 = mux(_T_1424, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1457 = mux(_T_1425, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1458 = mux(_T_1426, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1459 = mux(_T_1427, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1460 = mux(_T_1428, UInt<3>("h04"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1461 = mux(_T_1429, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1462 = mux(_T_1430, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1463 = mux(_T_1431, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1464 = mux(_T_1432, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1465 = mux(_T_1433, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1466 = mux(_T_1434, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1467 = mux(_T_1435, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1468 = mux(_T_1436, UInt<4>("h0c"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1469 = mux(_T_1437, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1470 = mux(_T_1438, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1471 = mux(_T_1439, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1472 = mux(_T_1440, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1473 = mux(_T_1441, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1474 = mux(_T_1442, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1475 = mux(_T_1443, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1476 = mux(_T_1444, UInt<5>("h014"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1477 = mux(_T_1445, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1478 = mux(_T_1446, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1479 = mux(_T_1447, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1480 = mux(_T_1448, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1481 = mux(_T_1449, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1482 = mux(_T_1450, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1483 = mux(_T_1451, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1484 = mux(_T_1452, UInt<5>("h01c"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1485 = or(_T_1453, _T_1454) @[Mux.scala 27:72]
+    node _T_1486 = or(_T_1485, _T_1455) @[Mux.scala 27:72]
+    node _T_1487 = or(_T_1486, _T_1456) @[Mux.scala 27:72]
+    node _T_1488 = or(_T_1487, _T_1457) @[Mux.scala 27:72]
+    node _T_1489 = or(_T_1488, _T_1458) @[Mux.scala 27:72]
+    node _T_1490 = or(_T_1489, _T_1459) @[Mux.scala 27:72]
+    node _T_1491 = or(_T_1490, _T_1460) @[Mux.scala 27:72]
+    node _T_1492 = or(_T_1491, _T_1461) @[Mux.scala 27:72]
+    node _T_1493 = or(_T_1492, _T_1462) @[Mux.scala 27:72]
+    node _T_1494 = or(_T_1493, _T_1463) @[Mux.scala 27:72]
+    node _T_1495 = or(_T_1494, _T_1464) @[Mux.scala 27:72]
+    node _T_1496 = or(_T_1495, _T_1465) @[Mux.scala 27:72]
+    node _T_1497 = or(_T_1496, _T_1466) @[Mux.scala 27:72]
+    node _T_1498 = or(_T_1497, _T_1467) @[Mux.scala 27:72]
+    node _T_1499 = or(_T_1498, _T_1468) @[Mux.scala 27:72]
+    node _T_1500 = or(_T_1499, _T_1469) @[Mux.scala 27:72]
+    node _T_1501 = or(_T_1500, _T_1470) @[Mux.scala 27:72]
+    node _T_1502 = or(_T_1501, _T_1471) @[Mux.scala 27:72]
+    node _T_1503 = or(_T_1502, _T_1472) @[Mux.scala 27:72]
+    node _T_1504 = or(_T_1503, _T_1473) @[Mux.scala 27:72]
+    node _T_1505 = or(_T_1504, _T_1474) @[Mux.scala 27:72]
+    node _T_1506 = or(_T_1505, _T_1475) @[Mux.scala 27:72]
+    node _T_1507 = or(_T_1506, _T_1476) @[Mux.scala 27:72]
+    node _T_1508 = or(_T_1507, _T_1477) @[Mux.scala 27:72]
+    node _T_1509 = or(_T_1508, _T_1478) @[Mux.scala 27:72]
+    node _T_1510 = or(_T_1509, _T_1479) @[Mux.scala 27:72]
+    node _T_1511 = or(_T_1510, _T_1480) @[Mux.scala 27:72]
+    node _T_1512 = or(_T_1511, _T_1481) @[Mux.scala 27:72]
+    node _T_1513 = or(_T_1512, _T_1482) @[Mux.scala 27:72]
+    node _T_1514 = or(_T_1513, _T_1483) @[Mux.scala 27:72]
+    node _T_1515 = or(_T_1514, _T_1484) @[Mux.scala 27:72]
+    wire _T_1516 : UInt<5> @[Mux.scala 27:72]
+    _T_1516 <= _T_1515 @[Mux.scala 27:72]
+    shortq_decode <= _T_1516 @[exu_div_ctl.scala 929:17]
+    node _T_1517 = eq(shortq_enable, UInt<1>("h00")) @[exu_div_ctl.scala 930:23]
+    node _T_1518 = mux(_T_1517, UInt<1>("h00"), shortq_decode) @[exu_div_ctl.scala 930:22]
+    shortq_shift <= _T_1518 @[exu_div_ctl.scala 930:16]
+    node _T_1519 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 931:20]
+    node _T_1520 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 931:30]
+    node _T_1521 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 931:40]
+    node _T_1522 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 931:50]
+    node _T_1523 = bits(b_ff1, 32, 32) @[exu_div_ctl.scala 931:60]
+    node _T_1524 = cat(_T_1522, _T_1523) @[Cat.scala 29:58]
+    node _T_1525 = cat(_T_1524, b_ff1) @[Cat.scala 29:58]
+    node _T_1526 = cat(_T_1519, _T_1520) @[Cat.scala 29:58]
+    node _T_1527 = cat(_T_1526, _T_1521) @[Cat.scala 29:58]
+    node _T_1528 = cat(_T_1527, _T_1525) @[Cat.scala 29:58]
+    b_ff <= _T_1528 @[exu_div_ctl.scala 931:8]
+    inst rvclkhdr of rvclkhdr @[lib.scala 390:23]
+    rvclkhdr.clock <= clock
+    rvclkhdr.reset <= reset
+    rvclkhdr.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr.io.en <= misc_enable @[lib.scala 393:17]
+    rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1529 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when misc_enable : @[Reg.scala 28:19]
+      _T_1529 <= valid_ff_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    valid_ff <= _T_1529 @[exu_div_ctl.scala 932:12]
+    inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 390:23]
+    rvclkhdr_1.clock <= clock
+    rvclkhdr_1.reset <= reset
+    rvclkhdr_1.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_1.io.en <= misc_enable @[lib.scala 393:17]
+    rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1530 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when misc_enable : @[Reg.scala 28:19]
+      _T_1530 <= control_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    control_ff <= _T_1530 @[exu_div_ctl.scala 933:16]
+    inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 390:23]
+    rvclkhdr_2.clock <= clock
+    rvclkhdr_2.reset <= reset
+    rvclkhdr_2.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_2.io.en <= misc_enable @[lib.scala 393:17]
+    rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1531 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when misc_enable : @[Reg.scala 28:19]
+      _T_1531 <= by_zero_case @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    by_zero_case_ff <= _T_1531 @[exu_div_ctl.scala 934:19]
+    inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 390:23]
+    rvclkhdr_3.clock <= clock
+    rvclkhdr_3.reset <= reset
+    rvclkhdr_3.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_3.io.en <= misc_enable @[lib.scala 393:17]
+    rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1532 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when misc_enable : @[Reg.scala 28:19]
+      _T_1532 <= shortq_enable @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    shortq_enable_ff <= _T_1532 @[exu_div_ctl.scala 935:20]
+    inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 390:23]
+    rvclkhdr_4.clock <= clock
+    rvclkhdr_4.reset <= reset
+    rvclkhdr_4.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_4.io.en <= misc_enable @[lib.scala 393:17]
+    rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1533 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when misc_enable : @[Reg.scala 28:19]
+      _T_1533 <= shortq_shift @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    shortq_shift_ff <= _T_1533 @[exu_div_ctl.scala 936:19]
+    inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 390:23]
+    rvclkhdr_5.clock <= clock
+    rvclkhdr_5.reset <= reset
+    rvclkhdr_5.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_5.io.en <= misc_enable @[lib.scala 393:17]
+    rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1534 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when misc_enable : @[Reg.scala 28:19]
+      _T_1534 <= finish @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    finish_ff <= _T_1534 @[exu_div_ctl.scala 937:13]
+    inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 390:23]
+    rvclkhdr_6.clock <= clock
+    rvclkhdr_6.reset <= reset
+    rvclkhdr_6.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_6.io.en <= misc_enable @[lib.scala 393:17]
+    rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1535 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when misc_enable : @[Reg.scala 28:19]
+      _T_1535 <= count_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    count_ff <= _T_1535 @[exu_div_ctl.scala 938:12]
+    inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 390:23]
+    rvclkhdr_7.clock <= clock
+    rvclkhdr_7.reset <= reset
+    rvclkhdr_7.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_7.io.en <= a_enable @[lib.scala 393:17]
+    rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1536 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when a_enable : @[Reg.scala 28:19]
+      _T_1536 <= a_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    a_ff <= _T_1536 @[exu_div_ctl.scala 940:8]
+    node _T_1537 = bits(b_in, 32, 0) @[exu_div_ctl.scala 941:23]
+    inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 390:23]
+    rvclkhdr_8.clock <= clock
+    rvclkhdr_8.reset <= reset
+    rvclkhdr_8.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_8.io.en <= b_enable @[lib.scala 393:17]
+    rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1538 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when b_enable : @[Reg.scala 28:19]
+      _T_1538 <= _T_1537 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    b_ff1 <= _T_1538 @[exu_div_ctl.scala 941:9]
+    inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 390:23]
+    rvclkhdr_9.clock <= clock
+    rvclkhdr_9.reset <= reset
+    rvclkhdr_9.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_9.io.en <= rq_enable @[lib.scala 393:17]
+    rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1539 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when rq_enable : @[Reg.scala 28:19]
+      _T_1539 <= r_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    r_ff <= _T_1539 @[exu_div_ctl.scala 942:8]
+    inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 390:23]
+    rvclkhdr_10.clock <= clock
+    rvclkhdr_10.reset <= reset
+    rvclkhdr_10.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_10.io.en <= rq_enable @[lib.scala 393:17]
+    rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1540 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when rq_enable : @[Reg.scala 28:19]
+      _T_1540 <= q_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    q_ff <= _T_1540 @[exu_div_ctl.scala 943:8]
+    
diff --git a/exu_div_new_4bit_fullshortq.v b/exu_div_new_4bit_fullshortq.v
new file mode 100644
index 00000000..f7765cba
--- /dev/null
+++ b/exu_div_new_4bit_fullshortq.v
@@ -0,0 +1,1204 @@
+module exu_div_cls(
+  input  [32:0] io_operand,
+  output [4:0]  io_cls
+);
+  wire  _T_3 = io_operand[31:30] == 2'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_5 = io_operand[31:29] == 3'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_7 = io_operand[31:28] == 4'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_9 = io_operand[31:27] == 5'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_11 = io_operand[31:26] == 6'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_13 = io_operand[31:25] == 7'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_15 = io_operand[31:24] == 8'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_17 = io_operand[31:23] == 9'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_19 = io_operand[31:22] == 10'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_21 = io_operand[31:21] == 11'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_23 = io_operand[31:20] == 12'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_25 = io_operand[31:19] == 13'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_27 = io_operand[31:18] == 14'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_29 = io_operand[31:17] == 15'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_31 = io_operand[31:16] == 16'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_33 = io_operand[31:15] == 17'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_35 = io_operand[31:14] == 18'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_37 = io_operand[31:13] == 19'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_39 = io_operand[31:12] == 20'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_41 = io_operand[31:11] == 21'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_43 = io_operand[31:10] == 22'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_45 = io_operand[31:9] == 23'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_47 = io_operand[31:8] == 24'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_49 = io_operand[31:7] == 25'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_51 = io_operand[31:6] == 26'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_53 = io_operand[31:5] == 27'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_55 = io_operand[31:4] == 28'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_57 = io_operand[31:3] == 29'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_59 = io_operand[31:2] == 30'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_61 = io_operand[31:1] == 31'h1; // @[exu_div_ctl.scala 958:63]
+  wire  _T_63 = io_operand[31:0] == 32'h1; // @[exu_div_ctl.scala 958:63]
+  wire [1:0] _T_66 = _T_5 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_67 = _T_7 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_68 = _T_9 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_69 = _T_11 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_70 = _T_13 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_71 = _T_15 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_72 = _T_17 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_73 = _T_19 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_74 = _T_21 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_75 = _T_23 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_76 = _T_25 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_77 = _T_27 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_78 = _T_29 ? 4'he : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_79 = _T_31 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_80 = _T_33 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_81 = _T_35 ? 5'h11 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_82 = _T_37 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_83 = _T_39 ? 5'h13 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_84 = _T_41 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_85 = _T_43 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_86 = _T_45 ? 5'h16 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_87 = _T_47 ? 5'h17 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_88 = _T_49 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_89 = _T_51 ? 5'h19 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_90 = _T_53 ? 5'h1a : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_91 = _T_55 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_92 = _T_57 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_93 = _T_59 ? 5'h1d : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_94 = _T_61 ? 5'h1e : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_95 = _T_63 ? 5'h1f : 5'h0; // @[Mux.scala 27:72]
+  wire [1:0] _GEN_1 = {{1'd0}, _T_3}; // @[Mux.scala 27:72]
+  wire [1:0] _T_97 = _GEN_1 | _T_66; // @[Mux.scala 27:72]
+  wire [1:0] _T_98 = _T_97 | _T_67; // @[Mux.scala 27:72]
+  wire [2:0] _GEN_2 = {{1'd0}, _T_98}; // @[Mux.scala 27:72]
+  wire [2:0] _T_99 = _GEN_2 | _T_68; // @[Mux.scala 27:72]
+  wire [2:0] _T_100 = _T_99 | _T_69; // @[Mux.scala 27:72]
+  wire [2:0] _T_101 = _T_100 | _T_70; // @[Mux.scala 27:72]
+  wire [2:0] _T_102 = _T_101 | _T_71; // @[Mux.scala 27:72]
+  wire [3:0] _GEN_3 = {{1'd0}, _T_102}; // @[Mux.scala 27:72]
+  wire [3:0] _T_103 = _GEN_3 | _T_72; // @[Mux.scala 27:72]
+  wire [3:0] _T_104 = _T_103 | _T_73; // @[Mux.scala 27:72]
+  wire [3:0] _T_105 = _T_104 | _T_74; // @[Mux.scala 27:72]
+  wire [3:0] _T_106 = _T_105 | _T_75; // @[Mux.scala 27:72]
+  wire [3:0] _T_107 = _T_106 | _T_76; // @[Mux.scala 27:72]
+  wire [3:0] _T_108 = _T_107 | _T_77; // @[Mux.scala 27:72]
+  wire [3:0] _T_109 = _T_108 | _T_78; // @[Mux.scala 27:72]
+  wire [3:0] _T_110 = _T_109 | _T_79; // @[Mux.scala 27:72]
+  wire [4:0] _GEN_4 = {{1'd0}, _T_110}; // @[Mux.scala 27:72]
+  wire [4:0] _T_111 = _GEN_4 | _T_80; // @[Mux.scala 27:72]
+  wire [4:0] _T_112 = _T_111 | _T_81; // @[Mux.scala 27:72]
+  wire [4:0] _T_113 = _T_112 | _T_82; // @[Mux.scala 27:72]
+  wire [4:0] _T_114 = _T_113 | _T_83; // @[Mux.scala 27:72]
+  wire [4:0] _T_115 = _T_114 | _T_84; // @[Mux.scala 27:72]
+  wire [4:0] _T_116 = _T_115 | _T_85; // @[Mux.scala 27:72]
+  wire [4:0] _T_117 = _T_116 | _T_86; // @[Mux.scala 27:72]
+  wire [4:0] _T_118 = _T_117 | _T_87; // @[Mux.scala 27:72]
+  wire [4:0] _T_119 = _T_118 | _T_88; // @[Mux.scala 27:72]
+  wire [4:0] _T_120 = _T_119 | _T_89; // @[Mux.scala 27:72]
+  wire [4:0] _T_121 = _T_120 | _T_90; // @[Mux.scala 27:72]
+  wire [4:0] _T_122 = _T_121 | _T_91; // @[Mux.scala 27:72]
+  wire [4:0] _T_123 = _T_122 | _T_92; // @[Mux.scala 27:72]
+  wire [4:0] _T_124 = _T_123 | _T_93; // @[Mux.scala 27:72]
+  wire [4:0] _T_125 = _T_124 | _T_94; // @[Mux.scala 27:72]
+  wire [4:0] cls_zeros = _T_125 | _T_95; // @[Mux.scala 27:72]
+  wire  _T_129 = io_operand[31:0] == 32'hffffffff; // @[exu_div_ctl.scala 960:25]
+  wire  _T_137 = io_operand[31:29] == 3'h6; // @[exu_div_ctl.scala 961:76]
+  wire  _T_142 = io_operand[31:28] == 4'he; // @[exu_div_ctl.scala 961:76]
+  wire  _T_147 = io_operand[31:27] == 5'h1e; // @[exu_div_ctl.scala 961:76]
+  wire  _T_152 = io_operand[31:26] == 6'h3e; // @[exu_div_ctl.scala 961:76]
+  wire  _T_157 = io_operand[31:25] == 7'h7e; // @[exu_div_ctl.scala 961:76]
+  wire  _T_162 = io_operand[31:24] == 8'hfe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_167 = io_operand[31:23] == 9'h1fe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_172 = io_operand[31:22] == 10'h3fe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_177 = io_operand[31:21] == 11'h7fe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_182 = io_operand[31:20] == 12'hffe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_187 = io_operand[31:19] == 13'h1ffe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_192 = io_operand[31:18] == 14'h3ffe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_197 = io_operand[31:17] == 15'h7ffe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_202 = io_operand[31:16] == 16'hfffe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_207 = io_operand[31:15] == 17'h1fffe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_212 = io_operand[31:14] == 18'h3fffe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_217 = io_operand[31:13] == 19'h7fffe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_222 = io_operand[31:12] == 20'hffffe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_227 = io_operand[31:11] == 21'h1ffffe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_232 = io_operand[31:10] == 22'h3ffffe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_237 = io_operand[31:9] == 23'h7ffffe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_242 = io_operand[31:8] == 24'hfffffe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_247 = io_operand[31:7] == 25'h1fffffe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_252 = io_operand[31:6] == 26'h3fffffe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_257 = io_operand[31:5] == 27'h7fffffe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_262 = io_operand[31:4] == 28'hffffffe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_267 = io_operand[31:3] == 29'h1ffffffe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_272 = io_operand[31:2] == 30'h3ffffffe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_277 = io_operand[31:1] == 31'h7ffffffe; // @[exu_div_ctl.scala 961:76]
+  wire  _T_282 = io_operand[31:0] == 32'hfffffffe; // @[exu_div_ctl.scala 961:76]
+  wire [1:0] _T_286 = _T_142 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_287 = _T_147 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_288 = _T_152 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_289 = _T_157 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_290 = _T_162 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_291 = _T_167 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_292 = _T_172 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_293 = _T_177 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_294 = _T_182 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_295 = _T_187 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_296 = _T_192 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_297 = _T_197 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_298 = _T_202 ? 4'he : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_299 = _T_207 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_300 = _T_212 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_301 = _T_217 ? 5'h11 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_302 = _T_222 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_303 = _T_227 ? 5'h13 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_304 = _T_232 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_305 = _T_237 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_306 = _T_242 ? 5'h16 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_307 = _T_247 ? 5'h17 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_308 = _T_252 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_309 = _T_257 ? 5'h19 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_310 = _T_262 ? 5'h1a : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_311 = _T_267 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_312 = _T_272 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_313 = _T_277 ? 5'h1d : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_314 = _T_282 ? 5'h1e : 5'h0; // @[Mux.scala 27:72]
+  wire [1:0] _GEN_5 = {{1'd0}, _T_137}; // @[Mux.scala 27:72]
+  wire [1:0] _T_316 = _GEN_5 | _T_286; // @[Mux.scala 27:72]
+  wire [1:0] _T_317 = _T_316 | _T_287; // @[Mux.scala 27:72]
+  wire [2:0] _GEN_6 = {{1'd0}, _T_317}; // @[Mux.scala 27:72]
+  wire [2:0] _T_318 = _GEN_6 | _T_288; // @[Mux.scala 27:72]
+  wire [2:0] _T_319 = _T_318 | _T_289; // @[Mux.scala 27:72]
+  wire [2:0] _T_320 = _T_319 | _T_290; // @[Mux.scala 27:72]
+  wire [2:0] _T_321 = _T_320 | _T_291; // @[Mux.scala 27:72]
+  wire [3:0] _GEN_7 = {{1'd0}, _T_321}; // @[Mux.scala 27:72]
+  wire [3:0] _T_322 = _GEN_7 | _T_292; // @[Mux.scala 27:72]
+  wire [3:0] _T_323 = _T_322 | _T_293; // @[Mux.scala 27:72]
+  wire [3:0] _T_324 = _T_323 | _T_294; // @[Mux.scala 27:72]
+  wire [3:0] _T_325 = _T_324 | _T_295; // @[Mux.scala 27:72]
+  wire [3:0] _T_326 = _T_325 | _T_296; // @[Mux.scala 27:72]
+  wire [3:0] _T_327 = _T_326 | _T_297; // @[Mux.scala 27:72]
+  wire [3:0] _T_328 = _T_327 | _T_298; // @[Mux.scala 27:72]
+  wire [3:0] _T_329 = _T_328 | _T_299; // @[Mux.scala 27:72]
+  wire [4:0] _GEN_8 = {{1'd0}, _T_329}; // @[Mux.scala 27:72]
+  wire [4:0] _T_330 = _GEN_8 | _T_300; // @[Mux.scala 27:72]
+  wire [4:0] _T_331 = _T_330 | _T_301; // @[Mux.scala 27:72]
+  wire [4:0] _T_332 = _T_331 | _T_302; // @[Mux.scala 27:72]
+  wire [4:0] _T_333 = _T_332 | _T_303; // @[Mux.scala 27:72]
+  wire [4:0] _T_334 = _T_333 | _T_304; // @[Mux.scala 27:72]
+  wire [4:0] _T_335 = _T_334 | _T_305; // @[Mux.scala 27:72]
+  wire [4:0] _T_336 = _T_335 | _T_306; // @[Mux.scala 27:72]
+  wire [4:0] _T_337 = _T_336 | _T_307; // @[Mux.scala 27:72]
+  wire [4:0] _T_338 = _T_337 | _T_308; // @[Mux.scala 27:72]
+  wire [4:0] _T_339 = _T_338 | _T_309; // @[Mux.scala 27:72]
+  wire [4:0] _T_340 = _T_339 | _T_310; // @[Mux.scala 27:72]
+  wire [4:0] _T_341 = _T_340 | _T_311; // @[Mux.scala 27:72]
+  wire [4:0] _T_342 = _T_341 | _T_312; // @[Mux.scala 27:72]
+  wire [4:0] _T_343 = _T_342 | _T_313; // @[Mux.scala 27:72]
+  wire [4:0] _T_344 = _T_343 | _T_314; // @[Mux.scala 27:72]
+  wire [4:0] cls_ones = _T_129 ? 5'h1f : _T_344; // @[exu_div_ctl.scala 960:44]
+  assign io_cls = io_operand[32] ? cls_ones : cls_zeros; // @[exu_div_ctl.scala 962:10]
+endmodule
+module rvclkhdr(
+  input   io_clk,
+  input   io_en
+);
+  wire  clkhdr_Q; // @[lib.scala 334:26]
+  wire  clkhdr_CK; // @[lib.scala 334:26]
+  wire  clkhdr_EN; // @[lib.scala 334:26]
+  wire  clkhdr_SE; // @[lib.scala 334:26]
+  gated_latch clkhdr ( // @[lib.scala 334:26]
+    .Q(clkhdr_Q),
+    .CK(clkhdr_CK),
+    .EN(clkhdr_EN),
+    .SE(clkhdr_SE)
+  );
+  assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
+  assign clkhdr_EN = io_en; // @[lib.scala 337:18]
+  assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
+endmodule
+module exu_div_new_4bit_fullshortq(
+  input         clock,
+  input         reset,
+  input         io_scan_mode,
+  input         io_cancel,
+  input         io_valid_in,
+  input         io_signed_in,
+  input         io_rem_in,
+  input  [31:0] io_dividend_in,
+  input  [31:0] io_divisor_in,
+  output [31:0] io_data_out,
+  output        io_valid_out
+);
+`ifdef RANDOMIZE_REG_INIT
+  reg [31:0] _RAND_0;
+  reg [63:0] _RAND_1;
+  reg [31:0] _RAND_2;
+  reg [31:0] _RAND_3;
+  reg [31:0] _RAND_4;
+  reg [31:0] _RAND_5;
+  reg [31:0] _RAND_6;
+  reg [31:0] _RAND_7;
+  reg [31:0] _RAND_8;
+  reg [63:0] _RAND_9;
+  reg [31:0] _RAND_10;
+`endif // RANDOMIZE_REG_INIT
+  wire [32:0] a_enc_io_operand; // @[exu_div_ctl.scala 917:21]
+  wire [4:0] a_enc_io_cls; // @[exu_div_ctl.scala 917:21]
+  wire [32:0] b_enc_io_operand; // @[exu_div_ctl.scala 920:21]
+  wire [4:0] b_enc_io_cls; // @[exu_div_ctl.scala 920:21]
+  wire  rvclkhdr_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_1_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_2_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_3_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_3_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_4_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_4_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_5_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_5_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_6_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_6_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_7_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_7_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_8_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_8_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_9_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_9_io_en; // @[lib.scala 390:23]
+  wire  rvclkhdr_10_io_clk; // @[lib.scala 390:23]
+  wire  rvclkhdr_10_io_en; // @[lib.scala 390:23]
+  wire  _T = ~io_cancel; // @[exu_div_ctl.scala 774:35]
+  wire  valid_ff_in = io_valid_in & _T; // @[exu_div_ctl.scala 774:33]
+  wire  _T_1 = ~io_valid_in; // @[exu_div_ctl.scala 775:35]
+  reg [2:0] control_ff; // @[Reg.scala 27:20]
+  wire  _T_3 = _T_1 & control_ff[2]; // @[exu_div_ctl.scala 775:48]
+  wire  _T_4 = io_valid_in & io_signed_in; // @[exu_div_ctl.scala 775:80]
+  wire  _T_6 = _T_4 & io_dividend_in[31]; // @[exu_div_ctl.scala 775:96]
+  wire  _T_7 = _T_3 | _T_6; // @[exu_div_ctl.scala 775:65]
+  wire  _T_10 = _T_1 & control_ff[1]; // @[exu_div_ctl.scala 775:133]
+  wire  _T_13 = _T_4 & io_divisor_in[31]; // @[exu_div_ctl.scala 775:181]
+  wire  _T_14 = _T_10 | _T_13; // @[exu_div_ctl.scala 775:150]
+  wire  _T_17 = _T_1 & control_ff[0]; // @[exu_div_ctl.scala 775:218]
+  wire  _T_18 = io_valid_in & io_rem_in; // @[exu_div_ctl.scala 775:250]
+  wire  _T_19 = _T_17 | _T_18; // @[exu_div_ctl.scala 775:235]
+  wire [2:0] control_in = {_T_7,_T_14,_T_19}; // @[Cat.scala 29:58]
+  reg [32:0] b_ff1; // @[Reg.scala 27:20]
+  wire [37:0] b_ff = {b_ff1[32],b_ff1[32],b_ff1[32],b_ff1[32],b_ff1[32],b_ff1}; // @[Cat.scala 29:58]
+  wire  _T_22 = b_ff[31:0] == 32'h0; // @[exu_div_ctl.scala 779:54]
+  reg  valid_ff; // @[Reg.scala 27:20]
+  wire  by_zero_case = valid_ff & _T_22; // @[exu_div_ctl.scala 779:40]
+  reg [31:0] a_ff; // @[Reg.scala 27:20]
+  wire  _T_24 = a_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 781:37]
+  wire  _T_26 = b_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 781:60]
+  wire  _T_27 = _T_24 & _T_26; // @[exu_div_ctl.scala 781:46]
+  wire  _T_28 = ~by_zero_case; // @[exu_div_ctl.scala 781:71]
+  wire  _T_29 = _T_27 & _T_28; // @[exu_div_ctl.scala 781:69]
+  wire  _T_30 = ~control_ff[0]; // @[exu_div_ctl.scala 781:87]
+  wire  _T_31 = _T_29 & _T_30; // @[exu_div_ctl.scala 781:85]
+  wire  _T_32 = _T_31 & valid_ff; // @[exu_div_ctl.scala 781:95]
+  wire  _T_34 = _T_32 & _T; // @[exu_div_ctl.scala 781:106]
+  wire  _T_36 = a_ff == 32'h0; // @[exu_div_ctl.scala 782:18]
+  wire  _T_38 = _T_36 & _T_28; // @[exu_div_ctl.scala 782:27]
+  wire  _T_40 = _T_38 & _T_30; // @[exu_div_ctl.scala 782:43]
+  wire  _T_41 = _T_40 & valid_ff; // @[exu_div_ctl.scala 782:53]
+  wire  _T_43 = _T_41 & _T; // @[exu_div_ctl.scala 782:64]
+  wire  smallnum_case = _T_34 | _T_43; // @[exu_div_ctl.scala 781:120]
+  reg [6:0] count_ff; // @[Reg.scala 27:20]
+  wire  _T_44 = |count_ff; // @[exu_div_ctl.scala 783:42]
+  reg  shortq_enable_ff; // @[Reg.scala 27:20]
+  wire  running_state = _T_44 | shortq_enable_ff; // @[exu_div_ctl.scala 783:45]
+  wire  _T_45 = io_valid_in | valid_ff; // @[exu_div_ctl.scala 784:43]
+  wire  _T_46 = _T_45 | io_cancel; // @[exu_div_ctl.scala 784:54]
+  wire  _T_47 = _T_46 | running_state; // @[exu_div_ctl.scala 784:66]
+  reg  finish_ff; // @[Reg.scala 27:20]
+  wire  misc_enable = _T_47 | finish_ff; // @[exu_div_ctl.scala 784:82]
+  wire  _T_48 = smallnum_case | by_zero_case; // @[exu_div_ctl.scala 785:45]
+  wire  _T_49 = count_ff == 7'h20; // @[exu_div_ctl.scala 785:72]
+  wire  finish_raw = _T_48 | _T_49; // @[exu_div_ctl.scala 785:60]
+  wire  finish = finish_raw & _T; // @[exu_div_ctl.scala 786:41]
+  wire  _T_51 = valid_ff | running_state; // @[exu_div_ctl.scala 787:40]
+  wire  _T_52 = ~finish; // @[exu_div_ctl.scala 787:59]
+  wire  _T_53 = _T_51 & _T_52; // @[exu_div_ctl.scala 787:57]
+  wire  _T_54 = ~finish_ff; // @[exu_div_ctl.scala 787:69]
+  wire  _T_55 = _T_53 & _T_54; // @[exu_div_ctl.scala 787:67]
+  wire  _T_57 = _T_55 & _T; // @[exu_div_ctl.scala 787:80]
+  wire [6:0] _T_1404 = {1'h0,1'h0,b_enc_io_cls}; // @[Cat.scala 29:58]
+  wire [6:0] _T_1405 = {1'h0,1'h0,a_enc_io_cls}; // @[Cat.scala 29:58]
+  wire [6:0] _T_1407 = _T_1404 - _T_1405; // @[exu_div_ctl.scala 925:41]
+  wire [6:0] dw_shortq_raw = _T_1407 + 7'h1; // @[exu_div_ctl.scala 925:61]
+  wire [5:0] shortq = dw_shortq_raw[6] ? 6'h0 : dw_shortq_raw[5:0]; // @[exu_div_ctl.scala 926:19]
+  wire  _T_1413 = ~shortq[5]; // @[exu_div_ctl.scala 927:31]
+  wire  _T_1414 = valid_ff & _T_1413; // @[exu_div_ctl.scala 927:29]
+  wire  _T_1416 = shortq[4:2] == 3'h7; // @[exu_div_ctl.scala 927:58]
+  wire  _T_1417 = ~_T_1416; // @[exu_div_ctl.scala 927:44]
+  wire  _T_1418 = _T_1414 & _T_1417; // @[exu_div_ctl.scala 927:42]
+  wire  shortq_enable = _T_1418 & _T; // @[exu_div_ctl.scala 927:73]
+  wire  _T_58 = ~shortq_enable; // @[exu_div_ctl.scala 787:95]
+  wire  count_enable = _T_57 & _T_58; // @[exu_div_ctl.scala 787:93]
+  wire [6:0] _T_60 = count_enable ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
+  wire [6:0] _T_62 = count_ff + 7'h4; // @[exu_div_ctl.scala 788:63]
+  reg [4:0] shortq_shift_ff; // @[Reg.scala 27:20]
+  wire [6:0] _T_63 = {2'h0,shortq_shift_ff}; // @[Cat.scala 29:58]
+  wire [6:0] _T_65 = _T_62 + _T_63; // @[exu_div_ctl.scala 788:74]
+  wire [6:0] count_in = _T_60 & _T_65; // @[exu_div_ctl.scala 788:51]
+  wire  a_enable = io_valid_in | running_state; // @[exu_div_ctl.scala 789:43]
+  wire  _T_66 = ~shortq_enable_ff; // @[exu_div_ctl.scala 790:47]
+  wire  a_shift = running_state & _T_66; // @[exu_div_ctl.scala 790:45]
+  wire [32:0] _T_68 = control_ff[2] ? 33'h1ffffffff : 33'h0; // @[Bitwise.scala 72:12]
+  wire [64:0] _T_70 = {_T_68,a_ff}; // @[Cat.scala 29:58]
+  wire [95:0] _GEN_11 = {{31'd0}, _T_70}; // @[exu_div_ctl.scala 791:74]
+  wire [95:0] _T_71 = _GEN_11 << shortq_shift_ff; // @[exu_div_ctl.scala 791:74]
+  wire  _T_72 = control_ff[2] ^ control_ff[1]; // @[exu_div_ctl.scala 792:61]
+  wire  _T_73 = ~_T_72; // @[exu_div_ctl.scala 792:42]
+  wire  b_twos_comp = valid_ff & _T_73; // @[exu_div_ctl.scala 792:40]
+  wire  _T_76 = ~valid_ff; // @[exu_div_ctl.scala 794:30]
+  wire  _T_78 = _T_76 & _T_30; // @[exu_div_ctl.scala 794:40]
+  wire  _T_80 = _T_78 & _T_72; // @[exu_div_ctl.scala 794:50]
+  reg  by_zero_case_ff; // @[Reg.scala 27:20]
+  wire  _T_81 = ~by_zero_case_ff; // @[exu_div_ctl.scala 794:92]
+  wire  twos_comp_q_sel = _T_80 & _T_81; // @[exu_div_ctl.scala 794:90]
+  wire  b_enable = io_valid_in | b_twos_comp; // @[exu_div_ctl.scala 795:43]
+  wire  rq_enable = _T_45 | running_state; // @[exu_div_ctl.scala 796:54]
+  wire  _T_83 = valid_ff & control_ff[2]; // @[exu_div_ctl.scala 797:40]
+  wire  r_sign_sel = _T_83 & _T_28; // @[exu_div_ctl.scala 797:59]
+  reg [32:0] r_ff; // @[Reg.scala 27:20]
+  wire [37:0] _T_287 = {r_ff[32],r_ff,a_ff[31:28]}; // @[Cat.scala 29:58]
+  wire [37:0] _T_289 = {b_ff[34:0],3'h0}; // @[Cat.scala 29:58]
+  wire [37:0] _T_291 = _T_287 + _T_289; // @[exu_div_ctl.scala 814:58]
+  wire [37:0] _T_293 = {b_ff[35:0],2'h0}; // @[Cat.scala 29:58]
+  wire [37:0] _T_295 = _T_291 + _T_293; // @[exu_div_ctl.scala 814:85]
+  wire [37:0] _T_297 = {b_ff[36:0],1'h0}; // @[Cat.scala 29:58]
+  wire [37:0] _T_299 = _T_295 + _T_297; // @[exu_div_ctl.scala 814:112]
+  wire [37:0] adder15_out = _T_299 + b_ff; // @[exu_div_ctl.scala 814:134]
+  wire  _T_302 = ~adder15_out[37]; // @[exu_div_ctl.scala 816:6]
+  wire  _T_303 = _T_302 ^ control_ff[2]; // @[exu_div_ctl.scala 816:23]
+  wire  _T_305 = a_ff[27:0] == 28'h0; // @[exu_div_ctl.scala 816:58]
+  wire  _T_306 = adder15_out == 38'h0; // @[exu_div_ctl.scala 816:82]
+  wire  _T_307 = _T_305 & _T_306; // @[exu_div_ctl.scala 816:67]
+  wire  _T_308 = _T_303 | _T_307; // @[exu_div_ctl.scala 816:43]
+  wire  _T_310 = ~_T_299[37]; // @[exu_div_ctl.scala 817:6]
+  wire  _T_311 = _T_310 ^ control_ff[2]; // @[exu_div_ctl.scala 817:23]
+  wire  _T_314 = _T_299 == 38'h0; // @[exu_div_ctl.scala 817:82]
+  wire  _T_315 = _T_305 & _T_314; // @[exu_div_ctl.scala 817:67]
+  wire  _T_316 = _T_311 | _T_315; // @[exu_div_ctl.scala 817:43]
+  wire [37:0] adder13_out = _T_295 + b_ff; // @[exu_div_ctl.scala 812:112]
+  wire  _T_318 = ~adder13_out[37]; // @[exu_div_ctl.scala 818:6]
+  wire  _T_319 = _T_318 ^ control_ff[2]; // @[exu_div_ctl.scala 818:23]
+  wire  _T_322 = adder13_out == 38'h0; // @[exu_div_ctl.scala 818:82]
+  wire  _T_323 = _T_305 & _T_322; // @[exu_div_ctl.scala 818:67]
+  wire  _T_324 = _T_319 | _T_323; // @[exu_div_ctl.scala 818:43]
+  wire  _T_326 = ~_T_295[37]; // @[exu_div_ctl.scala 819:6]
+  wire  _T_327 = _T_326 ^ control_ff[2]; // @[exu_div_ctl.scala 819:23]
+  wire  _T_330 = _T_295 == 38'h0; // @[exu_div_ctl.scala 819:82]
+  wire  _T_331 = _T_305 & _T_330; // @[exu_div_ctl.scala 819:67]
+  wire  _T_332 = _T_327 | _T_331; // @[exu_div_ctl.scala 819:43]
+  wire [37:0] _T_239 = _T_291 + _T_297; // @[exu_div_ctl.scala 810:85]
+  wire [37:0] adder11_out = _T_239 + b_ff; // @[exu_div_ctl.scala 810:107]
+  wire  _T_334 = ~adder11_out[37]; // @[exu_div_ctl.scala 820:6]
+  wire  _T_335 = _T_334 ^ control_ff[2]; // @[exu_div_ctl.scala 820:23]
+  wire  _T_338 = adder11_out == 38'h0; // @[exu_div_ctl.scala 820:82]
+  wire  _T_339 = _T_305 & _T_338; // @[exu_div_ctl.scala 820:67]
+  wire  _T_340 = _T_335 | _T_339; // @[exu_div_ctl.scala 820:43]
+  wire  _T_342 = ~_T_239[37]; // @[exu_div_ctl.scala 821:6]
+  wire  _T_343 = _T_342 ^ control_ff[2]; // @[exu_div_ctl.scala 821:23]
+  wire  _T_346 = _T_239 == 38'h0; // @[exu_div_ctl.scala 821:82]
+  wire  _T_347 = _T_305 & _T_346; // @[exu_div_ctl.scala 821:67]
+  wire  _T_348 = _T_343 | _T_347; // @[exu_div_ctl.scala 821:43]
+  wire [37:0] adder9_out = _T_291 + b_ff; // @[exu_div_ctl.scala 808:85]
+  wire  _T_350 = ~adder9_out[37]; // @[exu_div_ctl.scala 822:6]
+  wire  _T_351 = _T_350 ^ control_ff[2]; // @[exu_div_ctl.scala 822:22]
+  wire  _T_354 = adder9_out == 38'h0; // @[exu_div_ctl.scala 822:80]
+  wire  _T_355 = _T_305 & _T_354; // @[exu_div_ctl.scala 822:66]
+  wire  _T_356 = _T_351 | _T_355; // @[exu_div_ctl.scala 822:42]
+  wire  _T_358 = ~_T_291[37]; // @[exu_div_ctl.scala 823:6]
+  wire  _T_359 = _T_358 ^ control_ff[2]; // @[exu_div_ctl.scala 823:22]
+  wire  _T_362 = _T_291 == 38'h0; // @[exu_div_ctl.scala 823:80]
+  wire  _T_363 = _T_305 & _T_362; // @[exu_div_ctl.scala 823:66]
+  wire  _T_364 = _T_359 | _T_363; // @[exu_div_ctl.scala 823:42]
+  wire [37:0] _T_191 = _T_287 + _T_293; // @[exu_div_ctl.scala 806:57]
+  wire [37:0] _T_195 = _T_191 + _T_297; // @[exu_div_ctl.scala 806:84]
+  wire [37:0] adder7_out = _T_195 + b_ff; // @[exu_div_ctl.scala 806:106]
+  wire  _T_366 = ~adder7_out[37]; // @[exu_div_ctl.scala 824:6]
+  wire  _T_367 = _T_366 ^ control_ff[2]; // @[exu_div_ctl.scala 824:22]
+  wire  _T_370 = adder7_out == 38'h0; // @[exu_div_ctl.scala 824:80]
+  wire  _T_371 = _T_305 & _T_370; // @[exu_div_ctl.scala 824:66]
+  wire  _T_372 = _T_367 | _T_371; // @[exu_div_ctl.scala 824:42]
+  wire  _T_374 = ~_T_195[37]; // @[exu_div_ctl.scala 825:6]
+  wire  _T_375 = _T_374 ^ control_ff[2]; // @[exu_div_ctl.scala 825:22]
+  wire  _T_378 = _T_195 == 38'h0; // @[exu_div_ctl.scala 825:80]
+  wire  _T_379 = _T_305 & _T_378; // @[exu_div_ctl.scala 825:66]
+  wire  _T_380 = _T_375 | _T_379; // @[exu_div_ctl.scala 825:42]
+  wire [37:0] adder5_out = _T_191 + b_ff; // @[exu_div_ctl.scala 804:84]
+  wire  _T_382 = ~adder5_out[37]; // @[exu_div_ctl.scala 826:6]
+  wire  _T_383 = _T_382 ^ control_ff[2]; // @[exu_div_ctl.scala 826:22]
+  wire  _T_386 = adder5_out == 38'h0; // @[exu_div_ctl.scala 826:80]
+  wire  _T_387 = _T_305 & _T_386; // @[exu_div_ctl.scala 826:66]
+  wire  _T_388 = _T_383 | _T_387; // @[exu_div_ctl.scala 826:42]
+  wire  _T_390 = ~_T_191[37]; // @[exu_div_ctl.scala 827:6]
+  wire  _T_391 = _T_390 ^ control_ff[2]; // @[exu_div_ctl.scala 827:22]
+  wire  _T_394 = _T_191 == 38'h0; // @[exu_div_ctl.scala 827:80]
+  wire  _T_395 = _T_305 & _T_394; // @[exu_div_ctl.scala 827:66]
+  wire  _T_396 = _T_391 | _T_395; // @[exu_div_ctl.scala 827:42]
+  wire [36:0] _T_146 = {r_ff,a_ff[31:28]}; // @[Cat.scala 29:58]
+  wire [36:0] _T_148 = {b_ff[35:0],1'h0}; // @[Cat.scala 29:58]
+  wire [36:0] _T_150 = _T_146 + _T_148; // @[exu_div_ctl.scala 802:48]
+  wire [36:0] adder3_out = _T_150 + b_ff[36:0]; // @[exu_div_ctl.scala 802:70]
+  wire  _T_398 = ~adder3_out[36]; // @[exu_div_ctl.scala 828:6]
+  wire  _T_399 = _T_398 ^ control_ff[2]; // @[exu_div_ctl.scala 828:22]
+  wire  _T_402 = adder3_out == 37'h0; // @[exu_div_ctl.scala 828:80]
+  wire  _T_403 = _T_305 & _T_402; // @[exu_div_ctl.scala 828:66]
+  wire  _T_404 = _T_399 | _T_403; // @[exu_div_ctl.scala 828:42]
+  wire [35:0] _T_140 = {r_ff[31:0],a_ff[31:28]}; // @[Cat.scala 29:58]
+  wire [35:0] _T_142 = {b_ff[34:0],1'h0}; // @[Cat.scala 29:58]
+  wire [35:0] adder2_out = _T_140 + _T_142; // @[exu_div_ctl.scala 801:48]
+  wire  _T_406 = ~adder2_out[35]; // @[exu_div_ctl.scala 829:6]
+  wire  _T_407 = _T_406 ^ control_ff[2]; // @[exu_div_ctl.scala 829:22]
+  wire  _T_410 = adder2_out == 36'h0; // @[exu_div_ctl.scala 829:80]
+  wire  _T_411 = _T_305 & _T_410; // @[exu_div_ctl.scala 829:66]
+  wire  _T_412 = _T_407 | _T_411; // @[exu_div_ctl.scala 829:42]
+  wire [34:0] _T_135 = {r_ff[30:0],a_ff[31:28]}; // @[Cat.scala 29:58]
+  wire [34:0] adder1_out = _T_135 + b_ff[34:0]; // @[exu_div_ctl.scala 800:48]
+  wire  _T_414 = ~adder1_out[34]; // @[exu_div_ctl.scala 830:6]
+  wire  _T_415 = _T_414 ^ control_ff[2]; // @[exu_div_ctl.scala 830:22]
+  wire  _T_418 = adder1_out == 35'h0; // @[exu_div_ctl.scala 830:80]
+  wire  _T_419 = _T_305 & _T_418; // @[exu_div_ctl.scala 830:66]
+  wire  _T_420 = _T_415 | _T_419; // @[exu_div_ctl.scala 830:42]
+  wire [7:0] _T_427 = {_T_372,_T_380,_T_388,_T_396,_T_404,_T_412,_T_420,1'h0}; // @[Cat.scala 29:58]
+  wire [15:0] quotient_raw = {_T_308,_T_316,_T_324,_T_332,_T_340,_T_348,_T_356,_T_364,_T_427}; // @[Cat.scala 29:58]
+  wire  _T_441 = quotient_raw[15:8] == 8'h1; // @[exu_div_ctl.scala 833:76]
+  wire  _T_446 = quotient_raw[15:9] == 7'h1; // @[exu_div_ctl.scala 833:76]
+  wire  _T_479 = _T_441 | _T_446; // @[Mux.scala 27:72]
+  wire  _T_451 = quotient_raw[15:10] == 6'h1; // @[exu_div_ctl.scala 833:76]
+  wire  _T_480 = _T_479 | _T_451; // @[Mux.scala 27:72]
+  wire  _T_456 = quotient_raw[15:11] == 5'h1; // @[exu_div_ctl.scala 833:76]
+  wire  _T_481 = _T_480 | _T_456; // @[Mux.scala 27:72]
+  wire  _T_461 = quotient_raw[15:12] == 4'h1; // @[exu_div_ctl.scala 833:76]
+  wire  _T_482 = _T_481 | _T_461; // @[Mux.scala 27:72]
+  wire  _T_466 = quotient_raw[15:13] == 3'h1; // @[exu_div_ctl.scala 833:76]
+  wire  _T_483 = _T_482 | _T_466; // @[Mux.scala 27:72]
+  wire  _T_470 = quotient_raw[15:14] == 2'h1; // @[exu_div_ctl.scala 833:76]
+  wire  _T_484 = _T_483 | _T_470; // @[Mux.scala 27:72]
+  wire  _T_486 = quotient_raw[15] | _T_484; // @[exu_div_ctl.scala 833:31]
+  wire  _T_490 = quotient_raw[15:4] == 12'h0; // @[exu_div_ctl.scala 835:26]
+  wire  _T_494 = quotient_raw[15:5] == 11'h0; // @[exu_div_ctl.scala 835:77]
+  wire  _T_495 = _T_490 | _T_494; // @[exu_div_ctl.scala 835:54]
+  wire  _T_499 = quotient_raw[15:6] == 10'h0; // @[exu_div_ctl.scala 835:128]
+  wire  _T_500 = _T_495 | _T_499; // @[exu_div_ctl.scala 835:105]
+  wire  _T_504 = quotient_raw[15:7] == 9'h0; // @[exu_div_ctl.scala 836:28]
+  wire  _T_505 = _T_500 | _T_504; // @[exu_div_ctl.scala 835:155]
+  wire  _T_509 = quotient_raw[15:12] == 4'h0; // @[exu_div_ctl.scala 836:76]
+  wire  _T_510 = _T_505 | _T_509; // @[exu_div_ctl.scala 836:53]
+  wire  _T_514 = quotient_raw[15:13] == 3'h0; // @[exu_div_ctl.scala 836:119]
+  wire  _T_515 = _T_510 | _T_514; // @[exu_div_ctl.scala 836:96]
+  wire  _T_519 = quotient_raw[15:14] == 2'h0; // @[exu_div_ctl.scala 837:28]
+  wire  _T_520 = _T_515 | _T_519; // @[exu_div_ctl.scala 836:138]
+  wire  _T_523 = _T_520 | quotient_raw[15]; // @[exu_div_ctl.scala 837:46]
+  wire  _T_527 = quotient_raw[15:2] == 14'h0; // @[exu_div_ctl.scala 839:26]
+  wire  _T_531 = quotient_raw[15:3] == 13'h0; // @[exu_div_ctl.scala 839:79]
+  wire  _T_532 = _T_527 | _T_531; // @[exu_div_ctl.scala 839:56]
+  wire  _T_537 = _T_532 | _T_499; // @[exu_div_ctl.scala 839:109]
+  wire  _T_542 = _T_537 | _T_504; // @[exu_div_ctl.scala 839:159]
+  wire  _T_546 = quotient_raw[15:10] == 6'h0; // @[exu_div_ctl.scala 840:79]
+  wire  _T_547 = _T_542 | _T_546; // @[exu_div_ctl.scala 840:56]
+  wire  _T_551 = quotient_raw[15:11] == 5'h0; // @[exu_div_ctl.scala 840:124]
+  wire  _T_552 = _T_547 | _T_551; // @[exu_div_ctl.scala 840:101]
+  wire  _T_557 = _T_552 | _T_519; // @[exu_div_ctl.scala 840:145]
+  wire  _T_560 = _T_557 | quotient_raw[15]; // @[exu_div_ctl.scala 841:48]
+  wire  _T_566 = quotient_raw[15:1] == 15'h1; // @[exu_div_ctl.scala 843:81]
+  wire  _T_571 = quotient_raw[15:3] == 13'h1; // @[exu_div_ctl.scala 843:81]
+  wire  _T_605 = _T_566 | _T_571; // @[Mux.scala 27:72]
+  wire  _T_576 = quotient_raw[15:5] == 11'h1; // @[exu_div_ctl.scala 843:81]
+  wire  _T_606 = _T_605 | _T_576; // @[Mux.scala 27:72]
+  wire  _T_581 = quotient_raw[15:7] == 9'h1; // @[exu_div_ctl.scala 843:81]
+  wire  _T_607 = _T_606 | _T_581; // @[Mux.scala 27:72]
+  wire  _T_608 = _T_607 | _T_446; // @[Mux.scala 27:72]
+  wire  _T_609 = _T_608 | _T_456; // @[Mux.scala 27:72]
+  wire  _T_610 = _T_609 | _T_466; // @[Mux.scala 27:72]
+  wire  _T_612 = quotient_raw[15] | _T_610; // @[exu_div_ctl.scala 843:31]
+  wire [3:0] quotient_new = {_T_486,_T_523,_T_560,_T_612}; // @[Cat.scala 29:58]
+  wire  _T_85 = quotient_new == 4'h0; // @[exu_div_ctl.scala 798:71]
+  wire  _T_86 = running_state & _T_85; // @[exu_div_ctl.scala 798:55]
+  wire  r_adder_sel_0 = _T_86 & _T_66; // @[exu_div_ctl.scala 798:85]
+  wire  _T_88 = quotient_new == 4'h1; // @[exu_div_ctl.scala 798:71]
+  wire  _T_89 = running_state & _T_88; // @[exu_div_ctl.scala 798:55]
+  wire  r_adder_sel_1 = _T_89 & _T_66; // @[exu_div_ctl.scala 798:85]
+  wire  _T_91 = quotient_new == 4'h2; // @[exu_div_ctl.scala 798:71]
+  wire  _T_92 = running_state & _T_91; // @[exu_div_ctl.scala 798:55]
+  wire  r_adder_sel_2 = _T_92 & _T_66; // @[exu_div_ctl.scala 798:85]
+  wire  _T_94 = quotient_new == 4'h3; // @[exu_div_ctl.scala 798:71]
+  wire  _T_95 = running_state & _T_94; // @[exu_div_ctl.scala 798:55]
+  wire  r_adder_sel_3 = _T_95 & _T_66; // @[exu_div_ctl.scala 798:85]
+  wire  _T_97 = quotient_new == 4'h4; // @[exu_div_ctl.scala 798:71]
+  wire  _T_98 = running_state & _T_97; // @[exu_div_ctl.scala 798:55]
+  wire  r_adder_sel_4 = _T_98 & _T_66; // @[exu_div_ctl.scala 798:85]
+  wire  _T_100 = quotient_new == 4'h5; // @[exu_div_ctl.scala 798:71]
+  wire  _T_101 = running_state & _T_100; // @[exu_div_ctl.scala 798:55]
+  wire  r_adder_sel_5 = _T_101 & _T_66; // @[exu_div_ctl.scala 798:85]
+  wire  _T_103 = quotient_new == 4'h6; // @[exu_div_ctl.scala 798:71]
+  wire  _T_104 = running_state & _T_103; // @[exu_div_ctl.scala 798:55]
+  wire  r_adder_sel_6 = _T_104 & _T_66; // @[exu_div_ctl.scala 798:85]
+  wire  _T_106 = quotient_new == 4'h7; // @[exu_div_ctl.scala 798:71]
+  wire  _T_107 = running_state & _T_106; // @[exu_div_ctl.scala 798:55]
+  wire  r_adder_sel_7 = _T_107 & _T_66; // @[exu_div_ctl.scala 798:85]
+  wire  _T_109 = quotient_new == 4'h8; // @[exu_div_ctl.scala 798:71]
+  wire  _T_110 = running_state & _T_109; // @[exu_div_ctl.scala 798:55]
+  wire  r_adder_sel_8 = _T_110 & _T_66; // @[exu_div_ctl.scala 798:85]
+  wire  _T_112 = quotient_new == 4'h9; // @[exu_div_ctl.scala 798:71]
+  wire  _T_113 = running_state & _T_112; // @[exu_div_ctl.scala 798:55]
+  wire  r_adder_sel_9 = _T_113 & _T_66; // @[exu_div_ctl.scala 798:85]
+  wire  _T_115 = quotient_new == 4'ha; // @[exu_div_ctl.scala 798:71]
+  wire  _T_116 = running_state & _T_115; // @[exu_div_ctl.scala 798:55]
+  wire  r_adder_sel_10 = _T_116 & _T_66; // @[exu_div_ctl.scala 798:85]
+  wire  _T_118 = quotient_new == 4'hb; // @[exu_div_ctl.scala 798:71]
+  wire  _T_119 = running_state & _T_118; // @[exu_div_ctl.scala 798:55]
+  wire  r_adder_sel_11 = _T_119 & _T_66; // @[exu_div_ctl.scala 798:85]
+  wire  _T_121 = quotient_new == 4'hc; // @[exu_div_ctl.scala 798:71]
+  wire  _T_122 = running_state & _T_121; // @[exu_div_ctl.scala 798:55]
+  wire  r_adder_sel_12 = _T_122 & _T_66; // @[exu_div_ctl.scala 798:85]
+  wire  _T_124 = quotient_new == 4'hd; // @[exu_div_ctl.scala 798:71]
+  wire  _T_125 = running_state & _T_124; // @[exu_div_ctl.scala 798:55]
+  wire  r_adder_sel_13 = _T_125 & _T_66; // @[exu_div_ctl.scala 798:85]
+  wire  _T_127 = quotient_new == 4'he; // @[exu_div_ctl.scala 798:71]
+  wire  _T_128 = running_state & _T_127; // @[exu_div_ctl.scala 798:55]
+  wire  r_adder_sel_14 = _T_128 & _T_66; // @[exu_div_ctl.scala 798:85]
+  wire  _T_130 = quotient_new == 4'hf; // @[exu_div_ctl.scala 798:71]
+  wire  _T_131 = running_state & _T_130; // @[exu_div_ctl.scala 798:55]
+  wire  r_adder_sel_15 = _T_131 & _T_66; // @[exu_div_ctl.scala 798:85]
+  reg [31:0] q_ff; // @[Reg.scala 27:20]
+  wire [31:0] _T_617 = twos_comp_q_sel ? q_ff : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_618 = b_twos_comp ? b_ff[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] twos_comp_in = _T_617 | _T_618; // @[Mux.scala 27:72]
+  wire  _T_622 = |twos_comp_in[0]; // @[lib.scala 428:35]
+  wire  _T_624 = ~twos_comp_in[1]; // @[lib.scala 428:40]
+  wire  _T_626 = _T_622 ? _T_624 : twos_comp_in[1]; // @[lib.scala 428:23]
+  wire  _T_628 = |twos_comp_in[1:0]; // @[lib.scala 428:35]
+  wire  _T_630 = ~twos_comp_in[2]; // @[lib.scala 428:40]
+  wire  _T_632 = _T_628 ? _T_630 : twos_comp_in[2]; // @[lib.scala 428:23]
+  wire  _T_634 = |twos_comp_in[2:0]; // @[lib.scala 428:35]
+  wire  _T_636 = ~twos_comp_in[3]; // @[lib.scala 428:40]
+  wire  _T_638 = _T_634 ? _T_636 : twos_comp_in[3]; // @[lib.scala 428:23]
+  wire  _T_640 = |twos_comp_in[3:0]; // @[lib.scala 428:35]
+  wire  _T_642 = ~twos_comp_in[4]; // @[lib.scala 428:40]
+  wire  _T_644 = _T_640 ? _T_642 : twos_comp_in[4]; // @[lib.scala 428:23]
+  wire  _T_646 = |twos_comp_in[4:0]; // @[lib.scala 428:35]
+  wire  _T_648 = ~twos_comp_in[5]; // @[lib.scala 428:40]
+  wire  _T_650 = _T_646 ? _T_648 : twos_comp_in[5]; // @[lib.scala 428:23]
+  wire  _T_652 = |twos_comp_in[5:0]; // @[lib.scala 428:35]
+  wire  _T_654 = ~twos_comp_in[6]; // @[lib.scala 428:40]
+  wire  _T_656 = _T_652 ? _T_654 : twos_comp_in[6]; // @[lib.scala 428:23]
+  wire  _T_658 = |twos_comp_in[6:0]; // @[lib.scala 428:35]
+  wire  _T_660 = ~twos_comp_in[7]; // @[lib.scala 428:40]
+  wire  _T_662 = _T_658 ? _T_660 : twos_comp_in[7]; // @[lib.scala 428:23]
+  wire  _T_664 = |twos_comp_in[7:0]; // @[lib.scala 428:35]
+  wire  _T_666 = ~twos_comp_in[8]; // @[lib.scala 428:40]
+  wire  _T_668 = _T_664 ? _T_666 : twos_comp_in[8]; // @[lib.scala 428:23]
+  wire  _T_670 = |twos_comp_in[8:0]; // @[lib.scala 428:35]
+  wire  _T_672 = ~twos_comp_in[9]; // @[lib.scala 428:40]
+  wire  _T_674 = _T_670 ? _T_672 : twos_comp_in[9]; // @[lib.scala 428:23]
+  wire  _T_676 = |twos_comp_in[9:0]; // @[lib.scala 428:35]
+  wire  _T_678 = ~twos_comp_in[10]; // @[lib.scala 428:40]
+  wire  _T_680 = _T_676 ? _T_678 : twos_comp_in[10]; // @[lib.scala 428:23]
+  wire  _T_682 = |twos_comp_in[10:0]; // @[lib.scala 428:35]
+  wire  _T_684 = ~twos_comp_in[11]; // @[lib.scala 428:40]
+  wire  _T_686 = _T_682 ? _T_684 : twos_comp_in[11]; // @[lib.scala 428:23]
+  wire  _T_688 = |twos_comp_in[11:0]; // @[lib.scala 428:35]
+  wire  _T_690 = ~twos_comp_in[12]; // @[lib.scala 428:40]
+  wire  _T_692 = _T_688 ? _T_690 : twos_comp_in[12]; // @[lib.scala 428:23]
+  wire  _T_694 = |twos_comp_in[12:0]; // @[lib.scala 428:35]
+  wire  _T_696 = ~twos_comp_in[13]; // @[lib.scala 428:40]
+  wire  _T_698 = _T_694 ? _T_696 : twos_comp_in[13]; // @[lib.scala 428:23]
+  wire  _T_700 = |twos_comp_in[13:0]; // @[lib.scala 428:35]
+  wire  _T_702 = ~twos_comp_in[14]; // @[lib.scala 428:40]
+  wire  _T_704 = _T_700 ? _T_702 : twos_comp_in[14]; // @[lib.scala 428:23]
+  wire  _T_706 = |twos_comp_in[14:0]; // @[lib.scala 428:35]
+  wire  _T_708 = ~twos_comp_in[15]; // @[lib.scala 428:40]
+  wire  _T_710 = _T_706 ? _T_708 : twos_comp_in[15]; // @[lib.scala 428:23]
+  wire  _T_712 = |twos_comp_in[15:0]; // @[lib.scala 428:35]
+  wire  _T_714 = ~twos_comp_in[16]; // @[lib.scala 428:40]
+  wire  _T_716 = _T_712 ? _T_714 : twos_comp_in[16]; // @[lib.scala 428:23]
+  wire  _T_718 = |twos_comp_in[16:0]; // @[lib.scala 428:35]
+  wire  _T_720 = ~twos_comp_in[17]; // @[lib.scala 428:40]
+  wire  _T_722 = _T_718 ? _T_720 : twos_comp_in[17]; // @[lib.scala 428:23]
+  wire  _T_724 = |twos_comp_in[17:0]; // @[lib.scala 428:35]
+  wire  _T_726 = ~twos_comp_in[18]; // @[lib.scala 428:40]
+  wire  _T_728 = _T_724 ? _T_726 : twos_comp_in[18]; // @[lib.scala 428:23]
+  wire  _T_730 = |twos_comp_in[18:0]; // @[lib.scala 428:35]
+  wire  _T_732 = ~twos_comp_in[19]; // @[lib.scala 428:40]
+  wire  _T_734 = _T_730 ? _T_732 : twos_comp_in[19]; // @[lib.scala 428:23]
+  wire  _T_736 = |twos_comp_in[19:0]; // @[lib.scala 428:35]
+  wire  _T_738 = ~twos_comp_in[20]; // @[lib.scala 428:40]
+  wire  _T_740 = _T_736 ? _T_738 : twos_comp_in[20]; // @[lib.scala 428:23]
+  wire  _T_742 = |twos_comp_in[20:0]; // @[lib.scala 428:35]
+  wire  _T_744 = ~twos_comp_in[21]; // @[lib.scala 428:40]
+  wire  _T_746 = _T_742 ? _T_744 : twos_comp_in[21]; // @[lib.scala 428:23]
+  wire  _T_748 = |twos_comp_in[21:0]; // @[lib.scala 428:35]
+  wire  _T_750 = ~twos_comp_in[22]; // @[lib.scala 428:40]
+  wire  _T_752 = _T_748 ? _T_750 : twos_comp_in[22]; // @[lib.scala 428:23]
+  wire  _T_754 = |twos_comp_in[22:0]; // @[lib.scala 428:35]
+  wire  _T_756 = ~twos_comp_in[23]; // @[lib.scala 428:40]
+  wire  _T_758 = _T_754 ? _T_756 : twos_comp_in[23]; // @[lib.scala 428:23]
+  wire  _T_760 = |twos_comp_in[23:0]; // @[lib.scala 428:35]
+  wire  _T_762 = ~twos_comp_in[24]; // @[lib.scala 428:40]
+  wire  _T_764 = _T_760 ? _T_762 : twos_comp_in[24]; // @[lib.scala 428:23]
+  wire  _T_766 = |twos_comp_in[24:0]; // @[lib.scala 428:35]
+  wire  _T_768 = ~twos_comp_in[25]; // @[lib.scala 428:40]
+  wire  _T_770 = _T_766 ? _T_768 : twos_comp_in[25]; // @[lib.scala 428:23]
+  wire  _T_772 = |twos_comp_in[25:0]; // @[lib.scala 428:35]
+  wire  _T_774 = ~twos_comp_in[26]; // @[lib.scala 428:40]
+  wire  _T_776 = _T_772 ? _T_774 : twos_comp_in[26]; // @[lib.scala 428:23]
+  wire  _T_778 = |twos_comp_in[26:0]; // @[lib.scala 428:35]
+  wire  _T_780 = ~twos_comp_in[27]; // @[lib.scala 428:40]
+  wire  _T_782 = _T_778 ? _T_780 : twos_comp_in[27]; // @[lib.scala 428:23]
+  wire  _T_784 = |twos_comp_in[27:0]; // @[lib.scala 428:35]
+  wire  _T_786 = ~twos_comp_in[28]; // @[lib.scala 428:40]
+  wire  _T_788 = _T_784 ? _T_786 : twos_comp_in[28]; // @[lib.scala 428:23]
+  wire  _T_790 = |twos_comp_in[28:0]; // @[lib.scala 428:35]
+  wire  _T_792 = ~twos_comp_in[29]; // @[lib.scala 428:40]
+  wire  _T_794 = _T_790 ? _T_792 : twos_comp_in[29]; // @[lib.scala 428:23]
+  wire  _T_796 = |twos_comp_in[29:0]; // @[lib.scala 428:35]
+  wire  _T_798 = ~twos_comp_in[30]; // @[lib.scala 428:40]
+  wire  _T_800 = _T_796 ? _T_798 : twos_comp_in[30]; // @[lib.scala 428:23]
+  wire  _T_802 = |twos_comp_in[30:0]; // @[lib.scala 428:35]
+  wire  _T_804 = ~twos_comp_in[31]; // @[lib.scala 428:40]
+  wire  _T_806 = _T_802 ? _T_804 : twos_comp_in[31]; // @[lib.scala 428:23]
+  wire [6:0] _T_812 = {_T_662,_T_656,_T_650,_T_644,_T_638,_T_632,_T_626}; // @[lib.scala 430:14]
+  wire [14:0] _T_820 = {_T_710,_T_704,_T_698,_T_692,_T_686,_T_680,_T_674,_T_668,_T_812}; // @[lib.scala 430:14]
+  wire [7:0] _T_827 = {_T_758,_T_752,_T_746,_T_740,_T_734,_T_728,_T_722,_T_716}; // @[lib.scala 430:14]
+  wire [30:0] _T_836 = {_T_806,_T_800,_T_794,_T_788,_T_782,_T_776,_T_770,_T_764,_T_827,_T_820}; // @[lib.scala 430:14]
+  wire [31:0] twos_comp_out = {_T_836,twos_comp_in[0]}; // @[Cat.scala 29:58]
+  wire  _T_838 = ~a_shift; // @[exu_div_ctl.scala 851:6]
+  wire  _T_840 = _T_838 & _T_66; // @[exu_div_ctl.scala 851:15]
+  wire [31:0] _T_844 = {a_ff[27:0],4'h0}; // @[Cat.scala 29:58]
+  wire [64:0] ar_shifted = _T_71[64:0]; // @[exu_div_ctl.scala 791:28]
+  wire [31:0] _T_846 = _T_840 ? io_dividend_in : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_847 = a_shift ? _T_844 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_848 = shortq_enable_ff ? ar_shifted[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_849 = _T_846 | _T_847; // @[Mux.scala 27:72]
+  wire [31:0] a_in = _T_849 | _T_848; // @[Mux.scala 27:72]
+  wire  _T_851 = ~b_twos_comp; // @[exu_div_ctl.scala 856:5]
+  wire  _T_853 = io_signed_in & io_divisor_in[31]; // @[exu_div_ctl.scala 856:63]
+  wire [32:0] _T_855 = {_T_853,io_divisor_in}; // @[Cat.scala 29:58]
+  wire  _T_856 = ~control_ff[1]; // @[exu_div_ctl.scala 857:49]
+  wire [32:0] _T_858 = {_T_856,_T_836,twos_comp_in[0]}; // @[Cat.scala 29:58]
+  wire [32:0] _T_859 = _T_851 ? _T_855 : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_860 = b_twos_comp ? _T_858 : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] b_in = _T_859 | _T_860; // @[Mux.scala 27:72]
+  wire [32:0] _T_865 = {r_ff[28:0],a_ff[31:28]}; // @[Cat.scala 29:58]
+  wire [32:0] _T_883 = {1'h0,a_ff}; // @[Cat.scala 29:58]
+  wire [32:0] _T_884 = r_sign_sel ? 33'h1ffffffff : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_885 = r_adder_sel_0 ? _T_865 : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_886 = r_adder_sel_1 ? adder1_out[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_887 = r_adder_sel_2 ? adder2_out[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_888 = r_adder_sel_3 ? adder3_out[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_889 = r_adder_sel_4 ? _T_191[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_890 = r_adder_sel_5 ? adder5_out[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_891 = r_adder_sel_6 ? _T_195[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_892 = r_adder_sel_7 ? adder7_out[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_893 = r_adder_sel_8 ? _T_291[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_894 = r_adder_sel_9 ? adder9_out[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_895 = r_adder_sel_10 ? _T_239[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_896 = r_adder_sel_11 ? adder11_out[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_897 = r_adder_sel_12 ? _T_295[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_898 = r_adder_sel_13 ? adder13_out[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_899 = r_adder_sel_14 ? _T_299[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_900 = r_adder_sel_15 ? adder15_out[32:0] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_901 = shortq_enable_ff ? ar_shifted[64:32] : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_902 = by_zero_case ? _T_883 : 33'h0; // @[Mux.scala 27:72]
+  wire [32:0] _T_903 = _T_884 | _T_885; // @[Mux.scala 27:72]
+  wire [32:0] _T_904 = _T_903 | _T_886; // @[Mux.scala 27:72]
+  wire [32:0] _T_905 = _T_904 | _T_887; // @[Mux.scala 27:72]
+  wire [32:0] _T_906 = _T_905 | _T_888; // @[Mux.scala 27:72]
+  wire [32:0] _T_907 = _T_906 | _T_889; // @[Mux.scala 27:72]
+  wire [32:0] _T_908 = _T_907 | _T_890; // @[Mux.scala 27:72]
+  wire [32:0] _T_909 = _T_908 | _T_891; // @[Mux.scala 27:72]
+  wire [32:0] _T_910 = _T_909 | _T_892; // @[Mux.scala 27:72]
+  wire [32:0] _T_911 = _T_910 | _T_893; // @[Mux.scala 27:72]
+  wire [32:0] _T_912 = _T_911 | _T_894; // @[Mux.scala 27:72]
+  wire [32:0] _T_913 = _T_912 | _T_895; // @[Mux.scala 27:72]
+  wire [32:0] _T_914 = _T_913 | _T_896; // @[Mux.scala 27:72]
+  wire [32:0] _T_915 = _T_914 | _T_897; // @[Mux.scala 27:72]
+  wire [32:0] _T_916 = _T_915 | _T_898; // @[Mux.scala 27:72]
+  wire [32:0] _T_917 = _T_916 | _T_899; // @[Mux.scala 27:72]
+  wire [32:0] _T_918 = _T_917 | _T_900; // @[Mux.scala 27:72]
+  wire [32:0] _T_919 = _T_918 | _T_901; // @[Mux.scala 27:72]
+  wire [32:0] r_in = _T_919 | _T_902; // @[Mux.scala 27:72]
+  wire [31:0] _T_923 = {q_ff[27:0],_T_486,_T_523,_T_560,_T_612}; // @[Cat.scala 29:58]
+  wire  _T_946 = ~b_ff[3]; // @[exu_div_ctl.scala 893:70]
+  wire  _T_948 = ~b_ff[2]; // @[exu_div_ctl.scala 893:70]
+  wire  _T_951 = _T_946 & _T_948; // @[exu_div_ctl.scala 893:95]
+  wire  _T_950 = ~b_ff[1]; // @[exu_div_ctl.scala 893:70]
+  wire  _T_952 = _T_951 & _T_950; // @[exu_div_ctl.scala 893:95]
+  wire  _T_953 = a_ff[3] & _T_952; // @[exu_div_ctl.scala 894:11]
+  wire  _T_960 = a_ff[3] & _T_951; // @[exu_div_ctl.scala 894:11]
+  wire  _T_962 = ~b_ff[0]; // @[exu_div_ctl.scala 899:33]
+  wire  _T_963 = _T_960 & _T_962; // @[exu_div_ctl.scala 899:31]
+  wire  _T_973 = a_ff[2] & _T_952; // @[exu_div_ctl.scala 894:11]
+  wire  _T_974 = _T_963 | _T_973; // @[exu_div_ctl.scala 899:42]
+  wire  _T_977 = a_ff[3] & a_ff[2]; // @[exu_div_ctl.scala 892:95]
+  wire  _T_983 = _T_977 & _T_951; // @[exu_div_ctl.scala 894:11]
+  wire  _T_984 = _T_974 | _T_983; // @[exu_div_ctl.scala 899:75]
+  wire  _T_991 = a_ff[2] & _T_951; // @[exu_div_ctl.scala 894:11]
+  wire  _T_994 = _T_991 & _T_962; // @[exu_div_ctl.scala 901:31]
+  wire  _T_1004 = a_ff[1] & _T_952; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1005 = _T_994 | _T_1004; // @[exu_div_ctl.scala 901:42]
+  wire  _T_1011 = _T_946 & _T_950; // @[exu_div_ctl.scala 893:95]
+  wire  _T_1012 = a_ff[3] & _T_1011; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1015 = _T_1012 & _T_962; // @[exu_div_ctl.scala 901:106]
+  wire  _T_1016 = _T_1005 | _T_1015; // @[exu_div_ctl.scala 901:78]
+  wire  _T_1019 = ~a_ff[2]; // @[exu_div_ctl.scala 892:70]
+  wire  _T_1020 = a_ff[3] & _T_1019; // @[exu_div_ctl.scala 892:95]
+  wire  _T_1028 = _T_951 & b_ff[1]; // @[exu_div_ctl.scala 893:95]
+  wire  _T_1029 = _T_1028 & b_ff[0]; // @[exu_div_ctl.scala 893:95]
+  wire  _T_1030 = _T_1020 & _T_1029; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1031 = _T_1016 | _T_1030; // @[exu_div_ctl.scala 901:117]
+  wire  _T_1033 = ~a_ff[3]; // @[exu_div_ctl.scala 892:70]
+  wire  _T_1036 = _T_1033 & a_ff[2]; // @[exu_div_ctl.scala 892:95]
+  wire  _T_1037 = _T_1036 & a_ff[1]; // @[exu_div_ctl.scala 892:95]
+  wire  _T_1043 = _T_1037 & _T_951; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1044 = _T_1031 | _T_1043; // @[exu_div_ctl.scala 902:44]
+  wire  _T_1050 = _T_977 & _T_946; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1053 = _T_1050 & _T_962; // @[exu_div_ctl.scala 902:107]
+  wire  _T_1054 = _T_1044 | _T_1053; // @[exu_div_ctl.scala 902:80]
+  wire  _T_1063 = _T_946 & b_ff[2]; // @[exu_div_ctl.scala 893:95]
+  wire  _T_1064 = _T_1063 & _T_950; // @[exu_div_ctl.scala 893:95]
+  wire  _T_1065 = _T_977 & _T_1064; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1066 = _T_1054 | _T_1065; // @[exu_div_ctl.scala 902:119]
+  wire  _T_1069 = a_ff[3] & a_ff[1]; // @[exu_div_ctl.scala 892:95]
+  wire  _T_1075 = _T_1069 & _T_1011; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1076 = _T_1066 | _T_1075; // @[exu_div_ctl.scala 903:44]
+  wire  _T_1081 = _T_977 & a_ff[1]; // @[exu_div_ctl.scala 892:95]
+  wire  _T_1086 = _T_1081 & _T_1063; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1087 = _T_1076 | _T_1086; // @[exu_div_ctl.scala 903:79]
+  wire  _T_1091 = a_ff[2] & a_ff[1]; // @[exu_div_ctl.scala 892:95]
+  wire  _T_1092 = _T_1091 & a_ff[0]; // @[exu_div_ctl.scala 892:95]
+  wire  _T_1098 = _T_1092 & _T_1011; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1104 = _T_1020 & a_ff[0]; // @[exu_div_ctl.scala 892:95]
+  wire  _T_1109 = _T_946 & b_ff[1]; // @[exu_div_ctl.scala 893:95]
+  wire  _T_1110 = _T_1109 & b_ff[0]; // @[exu_div_ctl.scala 893:95]
+  wire  _T_1111 = _T_1104 & _T_1110; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1112 = _T_1098 | _T_1111; // @[exu_div_ctl.scala 905:45]
+  wire  _T_1119 = a_ff[2] & _T_1011; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1122 = _T_1119 & _T_962; // @[exu_div_ctl.scala 905:114]
+  wire  _T_1123 = _T_1112 | _T_1122; // @[exu_div_ctl.scala 905:86]
+  wire  _T_1130 = a_ff[1] & _T_951; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1133 = _T_1130 & _T_962; // @[exu_div_ctl.scala 906:33]
+  wire  _T_1134 = _T_1123 | _T_1133; // @[exu_div_ctl.scala 905:129]
+  wire  _T_1144 = a_ff[0] & _T_952; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1145 = _T_1134 | _T_1144; // @[exu_div_ctl.scala 906:47]
+  wire  _T_1150 = ~a_ff[1]; // @[exu_div_ctl.scala 892:70]
+  wire  _T_1152 = _T_1036 & _T_1150; // @[exu_div_ctl.scala 892:95]
+  wire  _T_1162 = _T_1152 & _T_1029; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1163 = _T_1145 | _T_1162; // @[exu_div_ctl.scala 906:88]
+  wire  _T_1172 = _T_1037 & _T_946; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1175 = _T_1172 & _T_962; // @[exu_div_ctl.scala 907:36]
+  wire  _T_1176 = _T_1163 | _T_1175; // @[exu_div_ctl.scala 906:131]
+  wire  _T_1182 = _T_948 & _T_950; // @[exu_div_ctl.scala 893:95]
+  wire  _T_1183 = a_ff[3] & _T_1182; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1186 = _T_1183 & _T_962; // @[exu_div_ctl.scala 907:76]
+  wire  _T_1187 = _T_1176 | _T_1186; // @[exu_div_ctl.scala 907:47]
+  wire  _T_1197 = _T_1063 & b_ff[1]; // @[exu_div_ctl.scala 893:95]
+  wire  _T_1198 = _T_1020 & _T_1197; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1199 = _T_1187 | _T_1198; // @[exu_div_ctl.scala 907:88]
+  wire  _T_1213 = _T_1037 & _T_1064; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1214 = _T_1199 | _T_1213; // @[exu_div_ctl.scala 907:131]
+  wire  _T_1220 = _T_1036 & a_ff[0]; // @[exu_div_ctl.scala 892:95]
+  wire  _T_1226 = _T_1220 & _T_1011; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1227 = _T_1214 | _T_1226; // @[exu_div_ctl.scala 908:47]
+  wire  _T_1234 = _T_1020 & _T_1150; // @[exu_div_ctl.scala 892:95]
+  wire  _T_1240 = _T_1063 & b_ff[0]; // @[exu_div_ctl.scala 893:95]
+  wire  _T_1241 = _T_1234 & _T_1240; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1242 = _T_1227 | _T_1241; // @[exu_div_ctl.scala 908:88]
+  wire  _T_1247 = _T_1019 & a_ff[1]; // @[exu_div_ctl.scala 892:95]
+  wire  _T_1248 = _T_1247 & a_ff[0]; // @[exu_div_ctl.scala 892:95]
+  wire  _T_1254 = _T_1248 & _T_951; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1255 = _T_1242 | _T_1254; // @[exu_div_ctl.scala 908:131]
+  wire  _T_1261 = _T_977 & _T_950; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1264 = _T_1261 & _T_962; // @[exu_div_ctl.scala 909:75]
+  wire  _T_1265 = _T_1255 | _T_1264; // @[exu_div_ctl.scala 909:47]
+  wire  _T_1273 = _T_1037 & a_ff[0]; // @[exu_div_ctl.scala 892:95]
+  wire  _T_1278 = _T_1273 & _T_1063; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1279 = _T_1265 | _T_1278; // @[exu_div_ctl.scala 909:88]
+  wire  _T_1286 = b_ff[3] & _T_948; // @[exu_div_ctl.scala 893:95]
+  wire  _T_1287 = _T_977 & _T_1286; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1288 = _T_1279 | _T_1287; // @[exu_div_ctl.scala 909:131]
+  wire  _T_1298 = _T_1286 & _T_950; // @[exu_div_ctl.scala 893:95]
+  wire  _T_1299 = _T_1069 & _T_1298; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1300 = _T_1288 | _T_1299; // @[exu_div_ctl.scala 910:47]
+  wire  _T_1303 = a_ff[3] & a_ff[0]; // @[exu_div_ctl.scala 892:95]
+  wire  _T_1309 = _T_1303 & _T_1182; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1310 = _T_1300 | _T_1309; // @[exu_div_ctl.scala 910:88]
+  wire  _T_1314 = a_ff[3] & _T_1150; // @[exu_div_ctl.scala 892:95]
+  wire  _T_1322 = _T_1197 & b_ff[0]; // @[exu_div_ctl.scala 893:95]
+  wire  _T_1323 = _T_1314 & _T_1322; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1324 = _T_1310 | _T_1323; // @[exu_div_ctl.scala 910:131]
+  wire  _T_1331 = _T_1081 & b_ff[3]; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1334 = _T_1331 & _T_962; // @[exu_div_ctl.scala 911:77]
+  wire  _T_1335 = _T_1324 | _T_1334; // @[exu_div_ctl.scala 911:47]
+  wire  _T_1344 = b_ff[3] & _T_950; // @[exu_div_ctl.scala 893:95]
+  wire  _T_1345 = _T_1081 & _T_1344; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1346 = _T_1335 | _T_1345; // @[exu_div_ctl.scala 911:88]
+  wire  _T_1351 = _T_977 & a_ff[0]; // @[exu_div_ctl.scala 892:95]
+  wire  _T_1356 = _T_1351 & _T_1344; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1357 = _T_1346 | _T_1356; // @[exu_div_ctl.scala 911:131]
+  wire  _T_1363 = _T_1020 & a_ff[1]; // @[exu_div_ctl.scala 892:95]
+  wire  _T_1368 = _T_1363 & _T_1109; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1369 = _T_1357 | _T_1368; // @[exu_div_ctl.scala 912:47]
+  wire  _T_1374 = _T_1069 & a_ff[0]; // @[exu_div_ctl.scala 892:95]
+  wire  _T_1377 = _T_1374 & _T_948; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1378 = _T_1369 | _T_1377; // @[exu_div_ctl.scala 912:88]
+  wire  _T_1385 = _T_1081 & a_ff[0]; // @[exu_div_ctl.scala 892:95]
+  wire  _T_1387 = _T_1385 & b_ff[3]; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1388 = _T_1378 | _T_1387; // @[exu_div_ctl.scala 912:131]
+  wire  _T_1394 = _T_1069 & _T_948; // @[exu_div_ctl.scala 894:11]
+  wire  _T_1397 = _T_1394 & _T_962; // @[exu_div_ctl.scala 913:74]
+  wire  _T_1398 = _T_1388 | _T_1397; // @[exu_div_ctl.scala 913:47]
+  wire [31:0] _T_924 = {28'h0,_T_953,_T_984,_T_1087,_T_1398}; // @[Cat.scala 29:58]
+  wire [31:0] _T_926 = _T_76 ? _T_923 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_927 = smallnum_case ? _T_924 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_928 = by_zero_case ? 32'hffffffff : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_929 = _T_926 | _T_927; // @[Mux.scala 27:72]
+  wire [31:0] q_in = _T_929 | _T_928; // @[Mux.scala 27:72]
+  wire  _T_934 = ~twos_comp_q_sel; // @[exu_div_ctl.scala 887:16]
+  wire  _T_935 = _T_30 & _T_934; // @[exu_div_ctl.scala 887:14]
+  wire [31:0] _T_938 = _T_935 ? q_ff : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_939 = control_ff[0] ? r_ff[31:0] : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_940 = twos_comp_q_sel ? twos_comp_out : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_941 = _T_938 | _T_939; // @[Mux.scala 27:72]
+  wire  _T_1425 = shortq == 6'h1b; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1426 = shortq == 6'h1a; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1427 = shortq == 6'h19; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1428 = shortq == 6'h18; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1429 = shortq == 6'h17; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1430 = shortq == 6'h16; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1431 = shortq == 6'h15; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1432 = shortq == 6'h14; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1433 = shortq == 6'h13; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1434 = shortq == 6'h12; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1435 = shortq == 6'h11; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1436 = shortq == 6'h10; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1437 = shortq == 6'hf; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1438 = shortq == 6'he; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1439 = shortq == 6'hd; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1440 = shortq == 6'hc; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1441 = shortq == 6'hb; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1442 = shortq == 6'ha; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1443 = shortq == 6'h9; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1444 = shortq == 6'h8; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1445 = shortq == 6'h7; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1446 = shortq == 6'h6; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1447 = shortq == 6'h5; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1448 = shortq == 6'h4; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1449 = shortq == 6'h3; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1450 = shortq == 6'h2; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1451 = shortq == 6'h1; // @[exu_div_ctl.scala 929:58]
+  wire  _T_1452 = shortq == 6'h0; // @[exu_div_ctl.scala 929:58]
+  wire [2:0] _T_1457 = _T_1425 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_1458 = _T_1426 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_1459 = _T_1427 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_1460 = _T_1428 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1461 = _T_1429 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1462 = _T_1430 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1463 = _T_1431 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1464 = _T_1432 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1465 = _T_1433 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1466 = _T_1434 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1467 = _T_1435 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
+  wire [3:0] _T_1468 = _T_1436 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1469 = _T_1437 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1470 = _T_1438 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1471 = _T_1439 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1472 = _T_1440 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1473 = _T_1441 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1474 = _T_1442 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1475 = _T_1443 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1476 = _T_1444 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1477 = _T_1445 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1478 = _T_1446 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1479 = _T_1447 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1480 = _T_1448 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1481 = _T_1449 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1482 = _T_1450 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1483 = _T_1451 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1484 = _T_1452 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
+  wire [2:0] _T_1489 = _T_1457 | _T_1458; // @[Mux.scala 27:72]
+  wire [2:0] _T_1490 = _T_1489 | _T_1459; // @[Mux.scala 27:72]
+  wire [2:0] _T_1491 = _T_1490 | _T_1460; // @[Mux.scala 27:72]
+  wire [3:0] _GEN_12 = {{1'd0}, _T_1491}; // @[Mux.scala 27:72]
+  wire [3:0] _T_1492 = _GEN_12 | _T_1461; // @[Mux.scala 27:72]
+  wire [3:0] _T_1493 = _T_1492 | _T_1462; // @[Mux.scala 27:72]
+  wire [3:0] _T_1494 = _T_1493 | _T_1463; // @[Mux.scala 27:72]
+  wire [3:0] _T_1495 = _T_1494 | _T_1464; // @[Mux.scala 27:72]
+  wire [3:0] _T_1496 = _T_1495 | _T_1465; // @[Mux.scala 27:72]
+  wire [3:0] _T_1497 = _T_1496 | _T_1466; // @[Mux.scala 27:72]
+  wire [3:0] _T_1498 = _T_1497 | _T_1467; // @[Mux.scala 27:72]
+  wire [3:0] _T_1499 = _T_1498 | _T_1468; // @[Mux.scala 27:72]
+  wire [4:0] _GEN_13 = {{1'd0}, _T_1499}; // @[Mux.scala 27:72]
+  wire [4:0] _T_1500 = _GEN_13 | _T_1469; // @[Mux.scala 27:72]
+  wire [4:0] _T_1501 = _T_1500 | _T_1470; // @[Mux.scala 27:72]
+  wire [4:0] _T_1502 = _T_1501 | _T_1471; // @[Mux.scala 27:72]
+  wire [4:0] _T_1503 = _T_1502 | _T_1472; // @[Mux.scala 27:72]
+  wire [4:0] _T_1504 = _T_1503 | _T_1473; // @[Mux.scala 27:72]
+  wire [4:0] _T_1505 = _T_1504 | _T_1474; // @[Mux.scala 27:72]
+  wire [4:0] _T_1506 = _T_1505 | _T_1475; // @[Mux.scala 27:72]
+  wire [4:0] _T_1507 = _T_1506 | _T_1476; // @[Mux.scala 27:72]
+  wire [4:0] _T_1508 = _T_1507 | _T_1477; // @[Mux.scala 27:72]
+  wire [4:0] _T_1509 = _T_1508 | _T_1478; // @[Mux.scala 27:72]
+  wire [4:0] _T_1510 = _T_1509 | _T_1479; // @[Mux.scala 27:72]
+  wire [4:0] _T_1511 = _T_1510 | _T_1480; // @[Mux.scala 27:72]
+  wire [4:0] _T_1512 = _T_1511 | _T_1481; // @[Mux.scala 27:72]
+  wire [4:0] _T_1513 = _T_1512 | _T_1482; // @[Mux.scala 27:72]
+  wire [4:0] _T_1514 = _T_1513 | _T_1483; // @[Mux.scala 27:72]
+  wire [4:0] shortq_decode = _T_1514 | _T_1484; // @[Mux.scala 27:72]
+  exu_div_cls a_enc ( // @[exu_div_ctl.scala 917:21]
+    .io_operand(a_enc_io_operand),
+    .io_cls(a_enc_io_cls)
+  );
+  exu_div_cls b_enc ( // @[exu_div_ctl.scala 920:21]
+    .io_operand(b_enc_io_operand),
+    .io_cls(b_enc_io_cls)
+  );
+  rvclkhdr rvclkhdr ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_io_clk),
+    .io_en(rvclkhdr_io_en)
+  );
+  rvclkhdr rvclkhdr_1 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_1_io_clk),
+    .io_en(rvclkhdr_1_io_en)
+  );
+  rvclkhdr rvclkhdr_2 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_2_io_clk),
+    .io_en(rvclkhdr_2_io_en)
+  );
+  rvclkhdr rvclkhdr_3 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_3_io_clk),
+    .io_en(rvclkhdr_3_io_en)
+  );
+  rvclkhdr rvclkhdr_4 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_4_io_clk),
+    .io_en(rvclkhdr_4_io_en)
+  );
+  rvclkhdr rvclkhdr_5 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_5_io_clk),
+    .io_en(rvclkhdr_5_io_en)
+  );
+  rvclkhdr rvclkhdr_6 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_6_io_clk),
+    .io_en(rvclkhdr_6_io_en)
+  );
+  rvclkhdr rvclkhdr_7 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_7_io_clk),
+    .io_en(rvclkhdr_7_io_en)
+  );
+  rvclkhdr rvclkhdr_8 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_8_io_clk),
+    .io_en(rvclkhdr_8_io_en)
+  );
+  rvclkhdr rvclkhdr_9 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_9_io_clk),
+    .io_en(rvclkhdr_9_io_en)
+  );
+  rvclkhdr rvclkhdr_10 ( // @[lib.scala 390:23]
+    .io_clk(rvclkhdr_10_io_clk),
+    .io_en(rvclkhdr_10_io_en)
+  );
+  assign io_data_out = _T_941 | _T_940; // @[exu_div_ctl.scala 886:15]
+  assign io_valid_out = finish_ff & _T; // @[exu_div_ctl.scala 885:16]
+  assign a_enc_io_operand = {control_ff[2],a_ff}; // @[exu_div_ctl.scala 918:20]
+  assign b_enc_io_operand = b_ff[32:0]; // @[exu_div_ctl.scala 921:20]
+  assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
+  assign rvclkhdr_1_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_1_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
+  assign rvclkhdr_2_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_2_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
+  assign rvclkhdr_3_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_3_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
+  assign rvclkhdr_4_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_4_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
+  assign rvclkhdr_5_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_5_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
+  assign rvclkhdr_6_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_6_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
+  assign rvclkhdr_7_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_7_io_en = io_valid_in | running_state; // @[lib.scala 393:17]
+  assign rvclkhdr_8_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_8_io_en = io_valid_in | b_twos_comp; // @[lib.scala 393:17]
+  assign rvclkhdr_9_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_9_io_en = _T_45 | running_state; // @[lib.scala 393:17]
+  assign rvclkhdr_10_io_clk = clock; // @[lib.scala 392:18]
+  assign rvclkhdr_10_io_en = _T_45 | running_state; // @[lib.scala 393:17]
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+  integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+  `ifdef RANDOMIZE
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      `ifdef RANDOMIZE_DELAY
+        #`RANDOMIZE_DELAY begin end
+      `else
+        #0.002 begin end
+      `endif
+    `endif
+`ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {1{`RANDOM}};
+  control_ff = _RAND_0[2:0];
+  _RAND_1 = {2{`RANDOM}};
+  b_ff1 = _RAND_1[32:0];
+  _RAND_2 = {1{`RANDOM}};
+  valid_ff = _RAND_2[0:0];
+  _RAND_3 = {1{`RANDOM}};
+  a_ff = _RAND_3[31:0];
+  _RAND_4 = {1{`RANDOM}};
+  count_ff = _RAND_4[6:0];
+  _RAND_5 = {1{`RANDOM}};
+  shortq_enable_ff = _RAND_5[0:0];
+  _RAND_6 = {1{`RANDOM}};
+  finish_ff = _RAND_6[0:0];
+  _RAND_7 = {1{`RANDOM}};
+  shortq_shift_ff = _RAND_7[4:0];
+  _RAND_8 = {1{`RANDOM}};
+  by_zero_case_ff = _RAND_8[0:0];
+  _RAND_9 = {2{`RANDOM}};
+  r_ff = _RAND_9[32:0];
+  _RAND_10 = {1{`RANDOM}};
+  q_ff = _RAND_10[31:0];
+`endif // RANDOMIZE_REG_INIT
+  if (reset) begin
+    control_ff = 3'h0;
+  end
+  if (reset) begin
+    b_ff1 = 33'h0;
+  end
+  if (reset) begin
+    valid_ff = 1'h0;
+  end
+  if (reset) begin
+    a_ff = 32'h0;
+  end
+  if (reset) begin
+    count_ff = 7'h0;
+  end
+  if (reset) begin
+    shortq_enable_ff = 1'h0;
+  end
+  if (reset) begin
+    finish_ff = 1'h0;
+  end
+  if (reset) begin
+    shortq_shift_ff = 5'h0;
+  end
+  if (reset) begin
+    by_zero_case_ff = 1'h0;
+  end
+  if (reset) begin
+    r_ff = 33'h0;
+  end
+  if (reset) begin
+    q_ff = 32'h0;
+  end
+  `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      control_ff <= 3'h0;
+    end else if (misc_enable) begin
+      control_ff <= control_in;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      b_ff1 <= 33'h0;
+    end else if (b_enable) begin
+      b_ff1 <= b_in;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      valid_ff <= 1'h0;
+    end else if (misc_enable) begin
+      valid_ff <= valid_ff_in;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      a_ff <= 32'h0;
+    end else if (a_enable) begin
+      a_ff <= a_in;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      count_ff <= 7'h0;
+    end else if (misc_enable) begin
+      count_ff <= count_in;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      shortq_enable_ff <= 1'h0;
+    end else if (misc_enable) begin
+      shortq_enable_ff <= shortq_enable;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      finish_ff <= 1'h0;
+    end else if (misc_enable) begin
+      finish_ff <= finish;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      shortq_shift_ff <= 5'h0;
+    end else if (misc_enable) begin
+      if (_T_58) begin
+        shortq_shift_ff <= 5'h0;
+      end else begin
+        shortq_shift_ff <= shortq_decode;
+      end
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      by_zero_case_ff <= 1'h0;
+    end else if (misc_enable) begin
+      by_zero_case_ff <= by_zero_case;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      r_ff <= 33'h0;
+    end else if (rq_enable) begin
+      r_ff <= r_in;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      q_ff <= 32'h0;
+    end else if (rq_enable) begin
+      q_ff <= q_in;
+    end
+  end
+endmodule
diff --git a/src/main/scala/exu/exu_div_ctl.scala b/src/main/scala/exu/exu_div_ctl.scala
index 91255c1c..16629a7c 100644
--- a/src/main/scala/exu/exu_div_ctl.scala
+++ b/src/main/scala/exu/exu_div_ctl.scala
@@ -628,23 +628,13 @@ class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib
   val r_sign_sel           =  valid_ff & dividend_sign_ff & !by_zero_case
 
   val r_adder_sel = (0 to 7 ).map(i=> (running_state & (quotient_new === i.asUInt) & !shortq_enable_ff))
-
-//  val r_restore_sel        =  running_state & (quotient_new === 0.U) & !shortq_enable_ff
-//  val r_adder1_sel         =  running_state & (quotient_new === 1.U) & !shortq_enable_ff
-//  val r_adder2_sel         =  running_state & (quotient_new === 2.U) & !shortq_enable_ff
-//  val r_adder3_sel         =  running_state & (quotient_new === 3.U) & !shortq_enable_ff
-//  val r_adder4_sel         =  running_state & (quotient_new === 4.U) & !shortq_enable_ff
-//  val r_adder5_sel         =  running_state & (quotient_new === 5.U) & !shortq_enable_ff
-//  val r_adder6_sel         =  running_state & (quotient_new === 6.U) & !shortq_enable_ff
-//  val r_adder7_sel         =  running_state & (quotient_new === 7.U) & !shortq_enable_ff
-
-   val adder1_out = Cat(r_ff(30,0),a_ff(32,30)) + b_ff(33,0)
-   val adder2_out = Cat(r_ff(31,0),a_ff(32,30)) + Cat(b_ff(33,0),0.U)
-   val adder3_out = Cat(r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U) + b_ff(35,0)
-   val adder4_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W))
-   val adder5_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + b_ff
-   val adder6_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U)
-   val adder7_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U) + b_ff
+  val adder1_out = Cat(r_ff(30,0),a_ff(32,30)) + b_ff(33,0)
+  val adder2_out = Cat(r_ff(31,0),a_ff(32,30)) + Cat(b_ff(33,0),0.U)
+  val adder3_out = Cat(r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U) + b_ff(35,0)
+  val adder4_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W))
+  val adder5_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + b_ff
+  val adder6_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U)
+  val adder7_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U) + b_ff
   quotient_raw := Cat((!adder7_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder7_out === 0.U)),
                      (!adder6_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder6_out === 0.U)),
                      (!adder5_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder5_out === 0.U)),
@@ -761,167 +751,200 @@ class exu_div_new_4bit_fullshortq extends Module with RequireAsyncReset with lib
     val data_out = Output(UInt(32.W))
     val valid_out = Output(UInt(1.W))
   })
-  io.data_out := 0.U
-  io.valid_out :=0.U
+
+  val valid_ff             = WireInit(Bool(),init=false.B)
+  val finish_ff            = WireInit(Bool(),init=false.B)
+  val control_ff           = WireInit(0.U(3.W))
+  val count_ff             = WireInit(0.U(7.W))
+  val smallnum             = WireInit(0.U(4.W))
+  val a_ff                 = WireInit(0.U(32.W))
+  val b_ff1                = WireInit(0.U(33.W))
+  val b_ff                 = WireInit(0.U(38.W))
+  val q_ff                 = WireInit(0.U(32.W))
+  val r_ff                 = WireInit(0.U(33.W))
+  val quotient_raw         = WireInit(0.U(16.W))
+  val quotient_new         = WireInit(0.U(4.W))
+  val shortq_enable        = WireInit(Bool(),init=false.B)
+  val shortq_enable_ff     = WireInit(Bool(),init=false.B)
+  val by_zero_case_ff      = WireInit(Bool(),init=false.B)
+  val ar_shifted           = WireInit(0.U(65.W))
+  val shortq_shift         = WireInit(0.U(5.W))
+  val shortq_decode        = WireInit(0.U(5.W))
+  val shortq_shift_ff      = WireInit(0.U(5.W))
+  val valid_ff_in = io.valid_in & !io.cancel
+  val control_in           = Cat((!io.valid_in & control_ff(2)) | (io.valid_in & io.signed_in  & io.dividend_in(31)), (!io.valid_in & control_ff(1)) | (io.valid_in & io.signed_in  &  io.divisor_in(31)), (!io.valid_in & control_ff(0)) | (io.valid_in & io.rem_in))
+  val dividend_sign_ff     = control_ff(2)
+  val divisor_sign_ff      = control_ff(1)
+  val rem_ff               = control_ff(0)
+  val by_zero_case         =  valid_ff & (b_ff(31,0) === 0.U)
+
+  val smallnum_case =  ((a_ff(31,4) === 0.U) & (b_ff(31,4) === 0.U) & !by_zero_case & !rem_ff & valid_ff & !io.cancel) |
+    ((a_ff(31,0) === 0.U) & !by_zero_case & !rem_ff & valid_ff & !io.cancel)
+  val running_state        = count_ff.orR() | shortq_enable_ff
+  val misc_enable          =  io.valid_in | valid_ff | io.cancel | running_state | finish_ff
+  val finish_raw           =  smallnum_case | by_zero_case | (count_ff === 32.U)
+  val finish               = finish_raw & !io.cancel
+  val count_enable         = (valid_ff | running_state) & !finish & !finish_ff & !io.cancel & !shortq_enable
+  val count_in             = Fill(7,count_enable) & (count_ff + 4.U(7.W) + Cat(0.U(2.W),shortq_shift_ff))
+  val a_enable             =  io.valid_in | running_state
+  val a_shift              =  running_state & !shortq_enable_ff
+  ar_shifted               := Cat (Fill(33,dividend_sign_ff),a_ff(31,0)) << shortq_shift_ff
+  val b_twos_comp          =  valid_ff & !(dividend_sign_ff ^ divisor_sign_ff)
+  val twos_comp_b_sel      =  valid_ff  & !(dividend_sign_ff ^ divisor_sign_ff)
+  val twos_comp_q_sel      = !valid_ff & !rem_ff &  (dividend_sign_ff ^ divisor_sign_ff) & !by_zero_case_ff
+  val b_enable             =  io.valid_in | b_twos_comp
+  val rq_enable            =  io.valid_in | valid_ff | running_state
+  val r_sign_sel           =  valid_ff & dividend_sign_ff & !by_zero_case
+  val r_adder_sel = (0 to 15 ).map(i=> (running_state & (quotient_new === i.asUInt) & !shortq_enable_ff))
+
+  val adder1_out = Cat(r_ff(30,0),a_ff(31,28)) + b_ff(34,0)
+  val adder2_out = Cat(r_ff(31,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U)
+  val adder3_out = Cat(r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U) + b_ff(36,0)
+  val adder4_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U(2.W))
+  val adder5_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U(2.W)) + b_ff
+  val adder6_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U(2.W)) + Cat(b_ff(36,0),0.U)
+  val adder7_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(35,0),0.U(2.W)) + Cat(b_ff(36,0),0.U) + b_ff
+  val adder8_out  = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W))
+  val adder9_out  = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + b_ff
+  val adder10_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(36,0),0.U)
+  val adder11_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(36,0),0.U) + b_ff
+  val adder12_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W))
+  val adder13_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W)) + b_ff
+  val adder14_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W)) + Cat(b_ff(36,0),0.U)
+  val adder15_out = Cat(r_ff(32),r_ff(32,0),a_ff(31,28)) + Cat(b_ff(34,0),0.U(3.W)) + Cat(b_ff(35,0),0.U(2.W)) + Cat(b_ff(36,0),0.U) + b_ff
+   quotient_raw := Cat(
+    (!adder15_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder15_out === 0.U)),
+    (!adder14_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder14_out === 0.U)),
+    (!adder13_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder13_out === 0.U)),
+    (!adder12_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder12_out === 0.U)),
+    (!adder11_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder11_out === 0.U)),
+    (!adder10_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder10_out === 0.U)),
+    (!adder9_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder9_out === 0.U)),
+    (!adder8_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder8_out === 0.U)),
+    (!adder7_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder7_out === 0.U)),
+    (!adder6_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder6_out === 0.U)),
+    (!adder5_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder5_out === 0.U)),
+    (!adder4_out(37) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder4_out === 0.U)),
+    (!adder3_out(36) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder3_out === 0.U)),
+    (!adder2_out(35) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder2_out === 0.U)),
+    (!adder1_out(34) ^ dividend_sign_ff) | ((a_ff(27,0) === 0.U) & (adder1_out === 0.U)), 0.U)
+
+  quotient_new := Cat(
+    ((quotient_raw(15)===1.U) | Mux1H((8 to 14).map(i=> (quotient_raw(15,i)=== Cat(Fill(15-i,0.U),1.U)).asBool -> 1.U))),
+
+    ( quotient_raw(15,4) === "b000000000001".U(12.U))| ( quotient_raw(15,5) === "b00000000001".U(11.U)) | ( quotient_raw(15,6) === "b0000000001".U(10.U)) |
+      ( quotient_raw(15,7) === "b000000001".U(9.U)) | ( quotient_raw(15,12)=== "b0001".U(4.U)) | ( quotient_raw(15,13)=== "b001".U(3.U)) |
+      ( quotient_raw(15,14)=== "b01".U(2.U)) | ( quotient_raw(15)   === "b1".U),
+
+    ( quotient_raw(15,2) === "b00000000000001".U(14.U))| ( quotient_raw(15,3) === "b0000000000001".U(13.U)) | ( quotient_raw(15,6) === "b0000000001".U(10.U)) |
+        ( quotient_raw(15,7) === "b0000000_01".U(9.U)) | ( quotient_raw(15,10)=== "b000001".U(6.U)) | ( quotient_raw(15,11)=== "b00001".U(5.U)) |
+        ( quotient_raw(15,14)=== "b01".U(2.U)) | ( quotient_raw(15)   === "b1".U),
+
+    ((quotient_raw(15)===1.U) | Mux1H((1 to 13 by 2).map(i=> (quotient_raw(15,i)=== Cat(Fill(15-i,0.U),1.U)).asBool -> 1.U))))
+
+  val twos_comp_in = Mux1H(Seq (
+    twos_comp_q_sel                       -> q_ff,
+    twos_comp_b_sel                     -> b_ff(31,0)
+  ))
+  val twos_comp_out = rvtwoscomp(twos_comp_in)
+  val a_in = Mux1H(Seq (
+    (!a_shift & !shortq_enable_ff).asBool -> io.dividend_in(31,0),
+     a_shift                             -> Cat(a_ff(27,0),0.U(4.W)),
+     shortq_enable_ff                    -> ar_shifted(31,0)
+  ))
+ val b_in = Mux1H(Seq (
+    !b_twos_comp                          -> Cat(io.signed_in & io.divisor_in(31),io.divisor_in(31,0)),
+    b_twos_comp                          -> Cat(!divisor_sign_ff,twos_comp_out(31,0))
+  ))
+    val r_in = Mux1H (Seq(
+    r_sign_sel                            -> Fill(33,1.U),
+    r_adder_sel(0)                        -> Cat(r_ff(28,0),a_ff(31,28)),
+    r_adder_sel(1)                        -> adder1_out(32,0),
+    r_adder_sel(2)                        -> adder2_out(32,0),
+    r_adder_sel(3)                        -> adder3_out(32,0),
+    r_adder_sel(4)                        -> adder4_out(32,0),
+    r_adder_sel(5)                        -> adder5_out(32,0),
+    r_adder_sel(6)                        -> adder6_out(32,0),
+    r_adder_sel(7)                        -> adder7_out(32,0),
+    r_adder_sel(8)                        -> adder8_out(32,0),
+    r_adder_sel(9)                        -> adder9_out(32,0),
+    r_adder_sel(10)                       -> adder10_out(32,0),
+    r_adder_sel(11)                       -> adder11_out(32,0),
+    r_adder_sel(12)                       -> adder12_out(32,0),
+    r_adder_sel(13)                       -> adder13_out(32,0),
+    r_adder_sel(14)                       -> adder14_out(32,0),
+    r_adder_sel(15)                       -> adder15_out(32,0),
+    shortq_enable_ff                      -> ar_shifted(64,32),
+    by_zero_case                          -> Cat(0.U,a_ff(31,0))
+  ))
+  val q_in = Mux1H (Seq(
+    !valid_ff                              -> Cat(q_ff(27,0),quotient_new),
+    smallnum_case                         -> Cat(0.U(28.W),smallnum),
+    by_zero_case                          -> Fill(32,1.U)
+  ))
+  io.valid_out := finish_ff & !io.cancel
+  io.data_out := Mux1H(Seq(
+    (!rem_ff & !twos_comp_q_sel).asBool() -> q_ff,
+    rem_ff                              -> r_ff(31,0),
+    twos_comp_q_sel                     -> twos_comp_out
+  ))
+    def pat1(x : List[Int], y : List[Int]) = {
+    val pat_a = (0 until x.size).map(i=> if(x(i)>=0) a_ff(x(i)) else !a_ff(x(i).abs)).reduce(_&_)
+    val pat_b = (0 until y.size).map(i=> if(y(i)>=0) b_ff(y(i)) else !b_ff(y(i).abs)).reduce(_&_)
+    pat_a & pat_b
+  }
+  smallnum := Cat(
+    pat1(List(3),List(-3, -2, -1)),
+
+    pat1(List(3),List(-3, -2))& !b_ff(0) | pat1(List(2),List(-3, -2, -1)) | pat1(List(3, 2),List(-3, -2)),
+
+    pat1(List(2),List(-3, -2))& !b_ff(0) | pat1(List(1),List(-3, -2, -1))    | pat1(List(3),List(-3, -1))& !b_ff(0) |
+      pat1(List(3, -2),List(-3, -2, 1, 0)) | pat1(List(-3, 2, 1),List(-3, -2)) | pat1(List(3, 2),List(-3))& !b_ff(0)  |
+      pat1(List(3, 2),List(-3, 2, -1))     | pat1(List(3, 1),List(-3,-1))     | pat1(List(3, 2, 1),List(-3, 2)),
+
+    pat1(List(2, 1, 0),List(-3, -1))        | pat1(List(3, -2, 0),List(-3, 1, 0))    | pat1(List(2),List(-3, -1))& !b_ff(0)     |
+      pat1(List(1),List(-3, -2))& !b_ff(0)    | pat1(List(0),List(-3, -2, -1))         | pat1(List(-3, 2, -1),List(-3, -2, 1, 0)) |
+      pat1(List(-3, 2, 1),List(-3))& !b_ff(0) | pat1(List(3),List(-2, -1)) & !b_ff(0)  | pat1(List(3, -2),List(-3, 2, 1))         |
+      pat1(List(-3, 2, 1),List(-3, 2, -1))    | pat1(List(-3, 2, 0),List(-3, -1))      | pat1(List(3, -2, -1),List(-3, 2, 0))     |
+      pat1(List(-2, 1, 0),List(-3, -2))       | pat1(List(3, 2),List(-1)) & !b_ff(0)   | pat1(List(-3, 2, 1, 0),List(-3, 2))      |
+      pat1(List(3, 2),List(3, -2))            | pat1(List(3, 1),List(3,-2,-1))         | pat1(List(3, 0),List(-2, -1))            |
+      pat1(List(3, -1),List(-3, 2, 1, 0))     | pat1(List(3, 2, 1),List(3)) & !b_ff(0) | pat1(List(3, 2, 1),List(3, -1))          |
+      pat1(List(3, 2, 0),List(3, -1))         | pat1(List(3, -2, 1),List(-3, 1))       | pat1(List(3, 1, 0),List(-2))             |
+      pat1(List(3, 2, 1, 0),List(3))          |pat1(List(3, 1),List(-2)) & !b_ff(0))
+
+
+  val shortq_dividend = Cat(dividend_sign_ff,a_ff(31,0))
+  val a_enc = Module(new exu_div_cls)
+  a_enc.io.operand := shortq_dividend
+  val dw_a_enc1 = a_enc.io.cls
+  val b_enc = Module(new exu_div_cls)
+  b_enc.io.operand := b_ff(32,0)
+  val dw_b_enc1 = b_enc.io.cls
+  val dw_a_enc = Cat (0.U, dw_a_enc1)
+  val dw_b_enc = Cat (0.U, dw_b_enc1)
+  val dw_shortq_raw = Cat(0.U,dw_b_enc) - Cat(0.U,dw_a_enc) + 1.U(7.W)
+  val shortq = Mux(dw_shortq_raw(6).asBool(),0.U,dw_shortq_raw(5,0))
+  shortq_enable := valid_ff & !shortq(5) & !(shortq(4,2) ===  "b111".U) & !io.cancel
+  val list = Array(28,28,28,28,24,24,24,24,20,20,20,20,16,16,16,16,12,12,12,12,8,8,8,8,4,4,4,4,0,0,0,0)
+  shortq_decode := Mux1H((31 to 0 by -1).map(i=> (shortq === i.U) -> list(i).U))
+  shortq_shift := Mux(!shortq_enable,0.U,shortq_decode)
+  b_ff := Cat(b_ff1(32),b_ff1(32),b_ff1(32),b_ff1(32),b_ff1(32),b_ff1)
+  valid_ff := rvdffe(valid_ff_in, misc_enable,clock,io.scan_mode)
+  control_ff   := rvdffe(control_in, misc_enable,clock,io.scan_mode)
+  by_zero_case_ff := rvdffe(by_zero_case,misc_enable,clock,io.scan_mode)
+  shortq_enable_ff := rvdffe(shortq_enable, misc_enable,clock,io.scan_mode)
+  shortq_shift_ff := rvdffe(shortq_shift, misc_enable,clock,io.scan_mode)
+  finish_ff := rvdffe(finish, misc_enable,clock,io.scan_mode)
+  count_ff := rvdffe(count_in, misc_enable,clock,io.scan_mode)
+
+  a_ff := rvdffe(a_in, a_enable,clock,io.scan_mode)
+  b_ff1 := rvdffe(b_in(32,0), b_enable,clock,io.scan_mode)
+  r_ff := rvdffe(r_in, rq_enable,clock,io.scan_mode)
+  q_ff := rvdffe(q_in, rq_enable,clock,io.scan_mode)
+
 }
-//  val valid_ff             = WireInit(Bool(),init=false.B)
-//  val finish_ff            = WireInit(Bool(),init=false.B)
-//  val control_ff           = WireInit(0.U(3.W))
-//  val count_ff             = WireInit(0.U(7.W))
-//  val smallnum             = WireInit(0.U(4.W))
-//  val a_ff                 = WireInit(0.U(32.W))
-//  val b_ff1                = WireInit(0.U(33.W))
-//  val b_ff                 = WireInit(0.U(38.W))
-//  val q_ff                 = WireInit(0.U(32.W))
-//  val r_ff                 = WireInit(0.U(33.W))
-//  val quotient_raw         = WireInit(0.U(16.W))
-//  val quotient_new         = WireInit(0.U(4.W))
-//  val shortq_enable        = WireInit(Bool(),init=false.B)
-//  val shortq_enable_ff     = WireInit(Bool(),init=false.B)
-//  val by_zero_case_ff      = WireInit(Bool(),init=false.B)
-//  val ar_shifted           = WireInit(0.U(65.W))
-//  val shortq_shift         = WireInit(0.U(5.W))
-//  val shortq_decode        = WireInit(0.U(5.W))
-//  val shortq_shift_ff      = WireInit(0.U(5.W))
-//  val valid_ff_in = io.valid_in & !io.cancel
-//  val control_in           = Cat((!io.valid_in & control_ff(2)) | (io.valid_in & io.signed_in  & io.dividend_in(31)), (!io.valid_in & control_ff(1)) | (io.valid_in & io.signed_in  &  io.divisor_in(31)), (!io.valid_in & control_ff(0)) | (io.valid_in & io.rem_in))
-//  val dividend_sign_ff     = control_ff(2)
-//  val divisor_sign_ff      = control_ff(1)
-//  val rem_ff               = control_ff(0)
-//  val by_zero_case         =  valid_ff & (b_ff(31,0) === 0.U)
-//
-//  val smallnum_case =  ((a_ff(31,4) === 0.U) & (b_ff(31,4) === 0.U) & !by_zero_case & !rem_ff & valid_ff & !io.cancel) |
-//    ((a_ff(31,0) === 0.U) & !by_zero_case & !rem_ff & valid_ff & !io.cancel)
-//  val running_state        = count_ff.orR() | shortq_enable_ff
-//  val misc_enable          =  io.valid_in | valid_ff | io.cancel | running_state | finish_ff
-//  val finish_raw           =  smallnum_case | by_zero_case | (count_ff === 32.U)
-//  val finish               = finish_raw & !io.cancel
-//  val count_enable         = (valid_ff | running_state) & !finish & !finish_ff & !io.cancel & !shortq_enable
-//  val count_in             = Fill(7,count_enable) & (count_ff + 4.U(7.W) + Cat(0.U(2.W),shortq_shift_ff))
-//  val a_enable             =  io.valid_in | running_state
-//  val a_shift              =  running_state & !shortq_enable_ff
-//  ar_shifted               := Cat (Fill(33,dividend_sign_ff),a_ff(31,0)) << shortq_shift_ff
-//  val b_twos_comp          =  valid_ff & !(dividend_sign_ff ^ divisor_sign_ff)
-//  val twos_comp_b_sel      =  valid_ff  & !(dividend_sign_ff ^ divisor_sign_ff)
-//  val twos_comp_q_sel      = !valid_ff & !rem_ff &  (dividend_sign_ff ^ divisor_sign_ff) & !by_zero_case_ff
-//  val b_enable             =  io.valid_in | b_twos_comp
-//  val rq_enable            =  io.valid_in | valid_ff | running_state
-//  val r_sign_sel           =  valid_ff & dividend_sign_ff & !by_zero_case
-//
-//  val r_adder_sel = (0 to 15 ).map(i=> (running_state & (quotient_new === i.asUInt) & ~shortq_enable_ff))
-//
-//  val adder1_out = Cat(r_ff(30,0),a_ff(32,30)) + b_ff(33,0)
-//  val adder2_out = Cat(r_ff(31,0),a_ff(32,30)) + Cat(b_ff(33,0),0.U)
-//  val adder3_out = Cat(r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U) + b_ff(35,0)
-//  val adder4_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W))
-//  val adder5_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + b_ff
-//  val adder6_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U)
-//  val adder7_out = Cat(r_ff(32),r_ff(32,0),a_ff(32,30)) + Cat(b_ff(34,0),0.U(2.W)) + Cat(b_ff(35,0),0.U) + b_ff
-//  quotient_raw := Cat((!adder7_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder7_out === 0.U)),
-//    (!adder6_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder6_out === 0.U)),
-//    (!adder5_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder5_out === 0.U)),
-//    (!adder4_out(36) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder4_out === 0.U)),
-//    (!adder3_out(35) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder3_out === 0.U)),
-//    (!adder2_out(34) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder2_out === 0.U)),
-//    (!adder1_out(33) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder1_out === 0.U)), 0.U)
-//  quotient_new := Cat ((quotient_raw(7) |  quotient_raw(6) | quotient_raw(5) |  quotient_raw(4)),
-//    (quotient_raw(7) |  quotient_raw(6) |(!quotient_raw(4) & quotient_raw(3)) |(!quotient_raw(3) & quotient_raw(2))),
-//    (quotient_raw(7) |  (!quotient_raw(6) & quotient_raw(5)) | (!quotient_raw(4) & quotient_raw(3)) |(!quotient_raw(2) & quotient_raw(1))))
-//  val twos_comp_in = Mux1H(Seq (
-//    twos_comp_q_sel                       -> q_ff,
-//    twos_comp_b_sel                     -> b_ff(31,0)
-//  ))
-//  val twos_comp_out = rvtwoscomp(twos_comp_in)
-//  val a_in = Mux1H(Seq (
-//    (!a_shift & !shortq_enable_ff).asBool -> Cat(io.signed_in & io.dividend_in(31),io.dividend_in(31,0)),
-//    a_shift                             -> Cat(a_ff(29,0),0.U(3.W)),
-//    shortq_enable_ff                    -> ar_shifted(32,0)
-//  ))
-//  val b_in = Mux1H(Seq (
-//    !b_twos_comp                          -> Cat(io.signed_in & io.divisor_in(31),io.divisor_in(31,0)),
-//    b_twos_comp                          -> Cat(!divisor_sign_ff,twos_comp_out(31,0))
-//  ))
-//  val r_in = Mux1H (Seq(
-//    r_sign_sel                            -> Fill(33,1.U),
-//    r_restore_sel                         -> Cat(r_ff(29,0),a_ff(32,30)),
-//    r_adder1_sel                           -> adder1_out(32,0),
-//    r_adder2_sel                           -> adder2_out(32,0),
-//    r_adder3_sel                           -> adder3_out(32,0),
-//    r_adder4_sel                           -> adder4_out(32,0),
-//    r_adder5_sel                           -> adder5_out(32,0),
-//    r_adder6_sel                           -> adder6_out(32,0),
-//    r_adder7_sel                           -> adder7_out(32,0),
-//    shortq_enable_ff                       -> ar_shifted(65,33),
-//    by_zero_case                           -> Cat(0.U,a_ff(31,0))
-//  ))
-//  val q_in = Mux1H (Seq(
-//    !valid_ff                              -> Cat(q_ff(28,0),quotient_new),
-//    smallnum_case                         -> Cat(0.U(28.W),smallnum),
-//    by_zero_case                          -> Fill(32,1.U)
-//  ))
-//  io.valid_out := finish_ff & !io.cancel
-//  io.data_out := Mux1H(Seq(
-//    (!rem_ff & !twos_comp_q_sel).asBool() -> q_ff,
-//    rem_ff                              -> r_ff(31,0),
-//    twos_comp_q_sel                     -> twos_comp_out
-//  ))
-//  def pat1(x : List[Int], y : List[Int]) = {
-//    val pat_a = (0 until x.size).map(i=> if(x(i)>=0) a_ff(x(i)) else !a_ff(x(i).abs)).reduce(_&_)
-//    val pat_b = (0 until y.size).map(i=> if(y(i)>=0) b_ff(y(i)) else !b_ff(y(i).abs)).reduce(_&_)
-//    pat_a & pat_b
-//  }
-//  smallnum := Cat(
-//    pat1(List(3),List(-3, -2, -1)),
-//
-//    pat1(List(3),List(-3, -2))& !b_ff(0) | pat1(List(2),List(-3, -2, -1)) | pat1(List(3, 2),List(-3, -2)),
-//
-//    pat1(List(2),List(-3, -2))& !b_ff(0) | pat1(List(1),List(-3, -2, -1))    | pat1(List(3),List(-3, -1))& !b_ff(0) |
-//      pat1(List(3, -2),List(-3, -2, 1, 0)) | pat1(List(-3, 2, 1),List(-3, -2)) | pat1(List(3, 2),List(-3))& !b_ff(0)  |
-//      pat1(List(3, 2),List(-3, 2, -1))     | pat1(List(3, 1),List(-3,-1))     | pat1(List(3, 2, 1),List(-3, 2)),
-//
-//    pat1(List(2, 1, 0),List(-3, -1))        | pat1(List(3, -2, 0),List(-3, 1, 0))    | pat1(List(2),List(-3, -1))& !b_ff(0)     |
-//      pat1(List(1),List(-3, -2))& !b_ff(0)    | pat1(List(0),List(-3, -2, -1))         | pat1(List(-3, 2, -1),List(-3, -2, 1, 0)) |
-//      pat1(List(-3, 2, 1),List(-3))& !b_ff(0) | pat1(List(3),List(-2, -1)) & !b_ff(0)  | pat1(List(3, -2),List(-3, 2, 1))         |
-//      pat1(List(-3, 2, 1),List(-3, 2, -1))    | pat1(List(-3, 2, 0),List(-3, -1))      | pat1(List(3, -2, -1),List(-3, 2, 0))     |
-//      pat1(List(-2, 1, 0),List(-3, -2))       | pat1(List(3, 2),List(-1)) & !b_ff(0)   | pat1(List(-3, 2, 1, 0),List(-3, 2))      |
-//      pat1(List(3, 2),List(3, -2))            | pat1(List(3, 1),List(3,-2,-1))         | pat1(List(3, 0),List(-2, -1))            |
-//      pat1(List(3, -1),List(-3, 2, 1, 0))     | pat1(List(3, 2, 1),List(3)) & !b_ff(0) | pat1(List(3, 2, 1),List(3, -1))          |
-//      pat1(List(3, 2, 0),List(3, -1))         | pat1(List(3, -2, 1),List(-3, 1))       | pat1(List(3, 1, 0),List(-2))             |
-//      pat1(List(3, 2, 1, 0),List(3))          |pat1(List(3, 1),List(-2)) & !b_ff(0))
-//
-//  val shortq_dividend = Cat(dividend_sign_ff,a_ff(31,0))
-//  val a_enc = Module(new exu_div_cls)
-//  a_enc.io.operand := shortq_dividend
-//  val dw_a_enc1 = a_enc.io.cls
-//  val b_enc = Module(new exu_div_cls)
-//  b_enc.io.operand := b_ff(32,0)
-//  val dw_b_enc1 = b_enc.io.cls
-//  val dw_a_enc = Cat (0.U, dw_a_enc1)
-//  val dw_b_enc = Cat (0.U, dw_b_enc1)
-//
-//  val dw_shortq_raw = Cat(0.U,dw_b_enc) - Cat(0.U,dw_a_enc) + 1.U(7.W)
-//  val shortq = Mux(dw_shortq_raw(6).asBool(),0.U,dw_shortq_raw(5,0))
-//  shortq_enable := valid_ff & !shortq(5) & !(shortq(4,2) ===  "b111".U) & !io.cancel
-//  val list = Array(27,27,27,27,27,27,24,24,24,21,21,21,18,18,18,15,15,15,12,12,12,9,9,9,6,6,6,3,0,0,0,0)
-//  shortq_decode := Mux1H((31 to 0 by -1).map(i=> (shortq === i.U) -> list(i).U))
-//  shortq_shift := Mux(!shortq_enable,0.U,shortq_decode)
-//  b_ff := Cat(b_ff1(32),b_ff1(32),b_ff1(32),b_ff1(32),b_ff1)
-//  valid_ff := rvdffe(valid_ff_in, misc_enable,clock,io.scan_mode)
-//  control_ff   := rvdffe(control_in, misc_enable,clock,io.scan_mode)
-//  by_zero_case_ff := rvdffe(by_zero_case,misc_enable,clock,io.scan_mode)
-//  shortq_enable_ff := rvdffe(shortq_enable, misc_enable,clock,io.scan_mode)
-//  shortq_shift_ff := rvdffe(shortq_shift, misc_enable,clock,io.scan_mode)
-//  finish_ff := rvdffe(finish, misc_enable,clock,io.scan_mode)
-//  count_ff := rvdffe(count_in, misc_enable,clock,io.scan_mode)
-//
-//  a_ff := rvdffe(a_in, a_enable,clock,io.scan_mode)
-//  b_ff1 := rvdffe(b_in(32,0), b_enable,clock,io.scan_mode)
-//  r_ff := rvdffe(r_in, rq_enable,clock,io.scan_mode)
-//  q_ff := rvdffe(q_in, rq_enable,clock,io.scan_mode)
-//
-//}
-object div_main4 extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new exu_div_new_3bit_fullshortq()))
+object div_main5 extends App {
+  println((new chisel3.stage.ChiselStage).emitVerilog(new exu_div_new_4bit_fullshortq()))
 }
 
 class exu_div_cls extends Module{
diff --git a/target/scala-2.12/classes/exu/div_main4$delayedInit$body.class b/target/scala-2.12/classes/exu/div_main4$delayedInit$body.class
deleted file mode 100644
index 496b237340ba8ba84a703efb4decd2d4664ffbf3..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 744
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diff --git a/target/scala-2.12/classes/exu/div_main4$.class b/target/scala-2.12/classes/exu/div_main5$.class
similarity index 73%
rename from target/scala-2.12/classes/exu/div_main4$.class
rename to target/scala-2.12/classes/exu/div_main5$.class
index 95da22f7737029129da6793e2932e38faac623e4..abd119f67072fa11e9f735c844962ac8889244eb 100644
GIT binary patch
delta 179
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delta 178
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diff --git a/target/scala-2.12/classes/exu/div_main5$delayedInit$body.class b/target/scala-2.12/classes/exu/div_main5$delayedInit$body.class
new file mode 100644
index 0000000000000000000000000000000000000000..f3fdd3470a27edbfd30eaaa2e011c0f1be504dd3
GIT binary patch
literal 744
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literal 0
HcmV?d00001

diff --git a/target/scala-2.12/classes/exu/div_main4.class b/target/scala-2.12/classes/exu/div_main5.class
similarity index 65%
rename from target/scala-2.12/classes/exu/div_main4.class
rename to target/scala-2.12/classes/exu/div_main5.class
index 76f2f01d6c89b0b8223d4c041ca06b4e0698db48..02ce3d2ea62edc975fbbdb9b100f51e97dd4ef62 100644
GIT binary patch
delta 59
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N#LPU?%^{5Y83Ez*5TyVB

delta 59
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N#LPUC%^{5Y83D^w5F!8o

diff --git a/target/scala-2.12/classes/exu/exu_div_cls$$anon$7.class b/target/scala-2.12/classes/exu/exu_div_cls$$anon$7.class
index 4a2efbe0556627023e470a95290cfae39a239f50..36be3cf92998f65e762975bb44491abd0ad44feb 100644
GIT binary patch
delta 37
tcmbQoJCApR2P@-_$)2n>j5{Z{v3BxqXW(Mq!Jx;ylOd3K`(zomCIH_%3qSw>

delta 37
tcmbQoJCApR2P@;k$)2n>jEg3>v3Bw<VBlh2$e_o(h#`=9!DJb>CIHr(3bp_M

diff --git a/target/scala-2.12/classes/exu/exu_div_cls.class b/target/scala-2.12/classes/exu/exu_div_cls.class
index 28d633f90dfacfb7cea6ee935a428108c569b3db..f6b5e343bcbf9c3ed26a7169c457fa0e8aa9c824 100644
GIT binary patch
delta 763
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delta 738
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diff --git a/target/scala-2.12/classes/exu/exu_div_existing_1bit_cheapshortq.class b/target/scala-2.12/classes/exu/exu_div_existing_1bit_cheapshortq.class
index f9f0c6cce3478bb1a3af5752581630ba9500bf98..8fdc86e55f0f7dff988a2b9736d9c1d137927d16 100644
GIT binary patch
delta 34
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delta 34
qcmdn<hHcLqwhaYo+=k|i42+qK45AvIlP|^!H}|D&?@MD`=MMneKny$p

diff --git a/target/scala-2.12/classes/exu/exu_div_new_1bit_fullshortq.class b/target/scala-2.12/classes/exu/exu_div_new_1bit_fullshortq.class
index 8a6f31306a2c87d56417c7905c996d7bcb41243b..c61d94e4eedd81bf3a4e57cb2700a0dd6ef65068 100644
GIT binary patch
delta 35
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delta 35
rcmcb*p6%*-wha?Ac?>NW85lDe8ALTaH77SV2sdxY+`b``QB@BB-CPT{

diff --git a/target/scala-2.12/classes/exu/exu_div_new_2bit_fullshortq.class b/target/scala-2.12/classes/exu/exu_div_new_2bit_fullshortq.class
index b289a3b6645ed0c1616d3605304157e5668a9734..6cf445c946426a670fafab9e208f71a0a3a9c62e 100644
GIT binary patch
delta 21
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delta 21
ccmZ2|o^ADcwhj5&Ooo=th1uH+vl*>y0A~vbU;qFB

diff --git a/target/scala-2.12/classes/exu/exu_div_new_3bit_fullshortq.class b/target/scala-2.12/classes/exu/exu_div_new_3bit_fullshortq.class
index d2a28ef51a65480b9eb38d709dcc37748278793e..6b389f264b78432935694a10f1d19ecf21c2ea14 100644
GIT binary patch
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diff --git a/target/scala-2.12/classes/exu/exu_div_new_4bit_fullshortq$$anon$6.class b/target/scala-2.12/classes/exu/exu_div_new_4bit_fullshortq$$anon$6.class
index 33cd3d415f1abb1522536a353337807f1f09dc4e..1f6ca9a9fcd4572ec480a85898fb28c5f13cae8a 100644
GIT binary patch
delta 140
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delta 140
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SC&Oo^UyNc*A18-!tpxziXfluh

diff --git a/target/scala-2.12/classes/exu/exu_div_new_4bit_fullshortq.class b/target/scala-2.12/classes/exu/exu_div_new_4bit_fullshortq.class
index 5411df79fd702b3a1140dd95192a9ec0ba8f45df..17d2b9d1c7d836f74c12f96324ff363c11937b8b 100644
GIT binary patch
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