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IFC

This commit is contained in:
waleed-lm 2020-09-29 10:34:35 +05:00
parent 5b6d41e88b
commit c8c8e05c1e
6 changed files with 28 additions and 7 deletions
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9
el2_ifu_ifc_ctrl.anno.json
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@ -1,4 +1,13 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_miss_f",
"sources":[
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifc_fetch_req_f",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_exu_flush_final",
"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ic_hit_f"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_ifc_ctrl|el2_ifu_ifc_ctrl>io_ifu_pmu_fetch_stall",

5
el2_ifu_ifc_ctrl.fir
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@ -3,7 +3,7 @@ circuit el2_ifu_ifc_ctrl :
module el2_ifu_ifc_ctrl :
input clock : Clock
input reset : UInt<1>
output io : {flip free_clk : UInt<1>, flip active_clk : UInt<1>, flip rst_l : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>, mb_empty_mod : UInt<1>}
output io : {flip free_clk : UInt<1>, flip active_clk : UInt<1>, flip rst_l : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>, mb_empty_mod : UInt<1>, miss_f : UInt<1>}
io.ifc_region_acc_fault_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 41:30]
io.ifc_dma_access_ok <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 42:24]
@ -112,6 +112,7 @@ circuit el2_ifu_ifc_ctrl :
node _T_46 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 95:49]
node _T_47 = and(_T_45, _T_46) @[el2_ifu_ifc_ctrl.scala 95:47]
miss_f <= _T_47 @[el2_ifu_ifc_ctrl.scala 95:10]
io.miss_f <= miss_f @[el2_ifu_ifc_ctrl.scala 96:13]
node _T_48 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 97:39]
node _T_49 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 97:63]
node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctrl.scala 97:61]
@ -146,7 +147,7 @@ circuit el2_ifu_ifc_ctrl :
node _T_74 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctrl.scala 106:62]
node _T_75 = and(_T_73, _T_74) @[el2_ifu_ifc_ctrl.scala 106:60]
node next_state_0 = or(_T_72, _T_75) @[el2_ifu_ifc_ctrl.scala 106:48]
node _T_76 = cat(next_state_0, next_state_0) @[Cat.scala 29:58]
node _T_76 = cat(next_state_1, next_state_0) @[Cat.scala 29:58]
reg _T_77 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 108:19]
_T_77 <= _T_76 @[el2_ifu_ifc_ctrl.scala 108:19]
state <= _T_77 @[el2_ifu_ifc_ctrl.scala 108:9]

15
el2_ifu_ifc_ctrl.v
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@ -28,7 +28,8 @@ module el2_ifu_ifc_ctrl(
output io_ifc_iccm_access_bf,
output io_ifc_region_acc_fault_bf,
output io_ifc_dma_access_ok,
output io_mb_empty_mod
output io_mb_empty_mod,
output io_miss_f
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
@ -118,14 +119,23 @@ module el2_ifu_ifc_ctrl(
wire _T_50 = _T_48 & _T_37; // @[el2_ifu_ifc_ctrl.scala 97:61]
wire _T_52 = _T_50 & _T_91; // @[el2_ifu_ifc_ctrl.scala 97:74]
wire _T_53 = ~miss_a; // @[el2_ifu_ifc_ctrl.scala 97:86]
wire mb_empty_mod = _T_52 & _T_53; // @[el2_ifu_ifc_ctrl.scala 97:84]
wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctrl.scala 99:35]
wire _T_57 = io_exu_flush_final & _T_41; // @[el2_ifu_ifc_ctrl.scala 101:36]
wire leave_idle = _T_57 & idle; // @[el2_ifu_ifc_ctrl.scala 101:67]
wire _T_60 = ~state[1]; // @[el2_ifu_ifc_ctrl.scala 103:23]
wire _T_62 = _T_60 & state[0]; // @[el2_ifu_ifc_ctrl.scala 103:33]
wire _T_63 = _T_62 & miss_f; // @[el2_ifu_ifc_ctrl.scala 103:44]
wire _T_64 = ~goto_idle; // @[el2_ifu_ifc_ctrl.scala 103:55]
wire _T_65 = _T_63 & _T_64; // @[el2_ifu_ifc_ctrl.scala 103:53]
wire _T_67 = ~mb_empty_mod; // @[el2_ifu_ifc_ctrl.scala 104:17]
wire _T_68 = state[1] & _T_67; // @[el2_ifu_ifc_ctrl.scala 104:15]
wire _T_70 = _T_68 & _T_64; // @[el2_ifu_ifc_ctrl.scala 104:31]
wire next_state_1 = _T_65 | _T_70; // @[el2_ifu_ifc_ctrl.scala 103:67]
wire _T_72 = _T_64 & leave_idle; // @[el2_ifu_ifc_ctrl.scala 106:34]
wire _T_75 = state[0] & _T_64; // @[el2_ifu_ifc_ctrl.scala 106:60]
wire next_state_0 = _T_72 | _T_75; // @[el2_ifu_ifc_ctrl.scala 106:48]
wire [1:0] _T_76 = {next_state_0,next_state_0}; // @[Cat.scala 29:58]
wire [1:0] _T_76 = {next_state_1,next_state_0}; // @[Cat.scala 29:58]
wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctrl.scala 128:16]
reg fb_full_f; // @[el2_ifu_ifc_ctrl.scala 131:26]
wire _T_135 = _T_32 | io_exu_flush_final; // @[el2_ifu_ifc_ctrl.scala 135:61]
@ -149,6 +159,7 @@ module el2_ifu_ifc_ctrl(
assign io_ifc_region_acc_fault_bf = 1'h0; // @[el2_ifu_ifc_ctrl.scala 41:30]
assign io_ifc_dma_access_ok = 1'h0; // @[el2_ifu_ifc_ctrl.scala 42:24]
assign io_mb_empty_mod = _T_52 & _T_53; // @[el2_ifu_ifc_ctrl.scala 98:19]
assign io_miss_f = _T_45 & _T_2; // @[el2_ifu_ifc_ctrl.scala 96:13]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif

6
src/main/scala/ifu/el2_ifu_ifc_ctrl.scala
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@ -35,7 +35,7 @@ val io = IO(new Bundle{
val ifc_region_acc_fault_bf = Output(Bool())
val ifc_dma_access_ok = Output(Bool())
val mb_empty_mod = Output(Bool())
val miss_f = Output(Bool())
})
io.ifc_region_acc_fault_bf := 0.U
@ -93,7 +93,7 @@ val io = IO(new Bundle{
fetch_bf_en := io.exu_flush_final | io.ifc_fetch_req_f
miss_f := io.ifc_fetch_req_f & !io.ic_hit_f & !io.exu_flush_final
io.miss_f := miss_f
mb_empty_mod := (io.ifu_ic_mb_empty | io.exu_flush_final) & !dma_stall & !miss_f & !miss_a
io.mb_empty_mod := mb_empty_mod
goto_idle := io.exu_flush_final & io.dec_tlu_flush_noredir_wb
@ -105,7 +105,7 @@ val io = IO(new Bundle{
val next_state_0 = (!goto_idle & leave_idle) | (state(0) & !goto_idle)
state := RegNext(Cat(next_state_0, next_state_0), init = 0.U)
state := RegNext(Cat(next_state_1, next_state_0), init = 0.U)
flush_fb := io.exu_flush_final

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target/scala-2.12/classes/ifu/el2_ifu_ifc_ctrl$$anon$1.class
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target/scala-2.12/classes/ifu/el2_ifu_ifc_ctrl.class
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