From cbff4bad75de21623228d8f16213a8ac78f7db6a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Thu, 3 Dec 2020 09:36:24 +0500 Subject: [PATCH] axi to ahb update --- axi4_to_ahb.fir | 1618 +++++++++-------- axi4_to_ahb.v | 756 ++++---- src/main/scala/lib/axi4_to_ahb.scala | 2 +- .../scala-2.12/classes/lib/axi4_to_ahb.class | Bin 107015 -> 107076 bytes 4 files changed, 1220 insertions(+), 1156 deletions(-) diff --git a/axi4_to_ahb.fir b/axi4_to_ahb.fir index 890b793d..dad0a7fb 100644 --- a/axi4_to_ahb.fir +++ b/axi4_to_ahb.fir @@ -524,875 +524,923 @@ circuit axi4_to_ahb : node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 175:44] node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 175:62] node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 175:48] - node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 175:48] - node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 175:48] - node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 175:48] - node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 175:62] + node _T_65 = orr(_T_64) @[axi4_to_ahb.scala 175:77] + node _T_66 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 175:44] + node _T_67 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 175:62] + node _T_68 = and(_T_66, _T_67) @[axi4_to_ahb.scala 175:48] + node _T_69 = orr(_T_68) @[axi4_to_ahb.scala 175:77] + node _T_70 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 175:44] + node _T_71 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 175:62] + node _T_72 = and(_T_70, _T_71) @[axi4_to_ahb.scala 175:48] + node _T_73 = orr(_T_72) @[axi4_to_ahb.scala 175:77] + node _T_74 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 175:44] + node _T_75 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 175:62] node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 175:48] - node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 175:48] - node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 175:48] - node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 175:62] - node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 175:48] - node _T_86 = mux(_T_64, UInt<1>("h00"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_87 = mux(_T_67, UInt<1>("h01"), _T_86) @[Mux.scala 98:16] - node _T_88 = mux(_T_70, UInt<2>("h02"), _T_87) @[Mux.scala 98:16] - node _T_89 = mux(_T_73, UInt<2>("h03"), _T_88) @[Mux.scala 98:16] - node _T_90 = mux(_T_76, UInt<3>("h04"), _T_89) @[Mux.scala 98:16] - node _T_91 = mux(_T_79, UInt<3>("h05"), _T_90) @[Mux.scala 98:16] - node _T_92 = mux(_T_82, UInt<3>("h06"), _T_91) @[Mux.scala 98:16] - node _T_93 = mux(_T_85, UInt<3>("h07"), _T_92) @[Mux.scala 98:16] - node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 233:124] - node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 233:30] - buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 233:24] + node _T_77 = orr(_T_76) @[axi4_to_ahb.scala 175:77] + node _T_78 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 175:44] + node _T_79 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 175:62] + node _T_80 = and(_T_78, _T_79) @[axi4_to_ahb.scala 175:48] + node _T_81 = orr(_T_80) @[axi4_to_ahb.scala 175:77] + node _T_82 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 175:44] + node _T_83 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 175:62] + node _T_84 = and(_T_82, _T_83) @[axi4_to_ahb.scala 175:48] + node _T_85 = orr(_T_84) @[axi4_to_ahb.scala 175:77] + node _T_86 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 175:44] + node _T_87 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 175:62] + node _T_88 = and(_T_86, _T_87) @[axi4_to_ahb.scala 175:48] + node _T_89 = orr(_T_88) @[axi4_to_ahb.scala 175:77] + node _T_90 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 175:44] + node _T_91 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 175:62] + node _T_92 = and(_T_90, _T_91) @[axi4_to_ahb.scala 175:48] + node _T_93 = orr(_T_92) @[axi4_to_ahb.scala 175:77] + node _T_94 = mux(_T_65, UInt<1>("h00"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_95 = mux(_T_69, UInt<1>("h01"), _T_94) @[Mux.scala 98:16] + node _T_96 = mux(_T_73, UInt<2>("h02"), _T_95) @[Mux.scala 98:16] + node _T_97 = mux(_T_77, UInt<2>("h03"), _T_96) @[Mux.scala 98:16] + node _T_98 = mux(_T_81, UInt<3>("h04"), _T_97) @[Mux.scala 98:16] + node _T_99 = mux(_T_85, UInt<3>("h05"), _T_98) @[Mux.scala 98:16] + node _T_100 = mux(_T_89, UInt<3>("h06"), _T_99) @[Mux.scala 98:16] + node _T_101 = mux(_T_93, UInt<3>("h07"), _T_100) @[Mux.scala 98:16] + node _T_102 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 233:124] + node _T_103 = mux(_T_57, _T_101, _T_102) @[axi4_to_ahb.scala 233:30] + buf_cmd_byte_ptr <= _T_103 @[axi4_to_ahb.scala 233:24] bypass_en <= buf_state_en @[axi4_to_ahb.scala 234:17] - node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 235:51] - node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 235:35] - rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 235:22] - node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] - node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 236:45] - io.ahb_htrans <= _T_100 @[axi4_to_ahb.scala 236:21] + node _T_104 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 235:51] + node _T_105 = and(bypass_en, _T_104) @[axi4_to_ahb.scala 235:35] + rd_bypass_idle <= _T_105 @[axi4_to_ahb.scala 235:22] + node _T_106 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] + node _T_107 = mux(_T_106, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_108 = and(_T_107, UInt<2>("h02")) @[axi4_to_ahb.scala 236:45] + io.ahb_htrans <= _T_108 @[axi4_to_ahb.scala 236:21] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] - node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_101 : @[Conditional.scala 39:67] - node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 240:54] - node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 240:61] - node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 240:41] - node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 240:82] - node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 240:26] - buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 240:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 241:51] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 241:58] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 241:36] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 241:72] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 241:70] - buf_state_en <= _T_111 @[axi4_to_ahb.scala 241:20] - node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 242:34] - node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 242:32] - cmd_done <= _T_113 @[axi4_to_ahb.scala 242:16] + node _T_109 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] + when _T_109 : @[Conditional.scala 39:67] + node _T_110 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 240:54] + node _T_111 = eq(_T_110, UInt<1>("h00")) @[axi4_to_ahb.scala 240:61] + node _T_112 = and(master_valid, _T_111) @[axi4_to_ahb.scala 240:41] + node _T_113 = bits(_T_112, 0, 0) @[axi4_to_ahb.scala 240:82] + node _T_114 = mux(_T_113, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 240:26] + buf_nxtstate <= _T_114 @[axi4_to_ahb.scala 240:20] + node _T_115 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 241:51] + node _T_116 = neq(_T_115, UInt<1>("h00")) @[axi4_to_ahb.scala 241:58] + node _T_117 = and(ahb_hready_q, _T_116) @[axi4_to_ahb.scala 241:36] + node _T_118 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 241:72] + node _T_119 = and(_T_117, _T_118) @[axi4_to_ahb.scala 241:70] + buf_state_en <= _T_119 @[axi4_to_ahb.scala 241:20] + node _T_120 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 242:34] + node _T_121 = and(buf_state_en, _T_120) @[axi4_to_ahb.scala 242:32] + cmd_done <= _T_121 @[axi4_to_ahb.scala 242:16] slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 243:20] - node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 244:52] - node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 244:59] - node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 244:37] - node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 244:73] - node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 244:71] - node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 244:122] - node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 244:129] - node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 244:109] - node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 244:150] - node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 244:94] - node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 244:174] - node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 244:88] - master_ready <= _T_125 @[axi4_to_ahb.scala 244:20] + node _T_122 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 244:52] + node _T_123 = neq(_T_122, UInt<1>("h00")) @[axi4_to_ahb.scala 244:59] + node _T_124 = and(ahb_hready_q, _T_123) @[axi4_to_ahb.scala 244:37] + node _T_125 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 244:73] + node _T_126 = and(_T_124, _T_125) @[axi4_to_ahb.scala 244:71] + node _T_127 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 244:122] + node _T_128 = eq(_T_127, UInt<1>("h00")) @[axi4_to_ahb.scala 244:129] + node _T_129 = and(master_valid, _T_128) @[axi4_to_ahb.scala 244:109] + node _T_130 = bits(_T_129, 0, 0) @[axi4_to_ahb.scala 244:150] + node _T_131 = mux(_T_130, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 244:94] + node _T_132 = eq(_T_131, UInt<3>("h06")) @[axi4_to_ahb.scala 244:174] + node _T_133 = and(_T_126, _T_132) @[axi4_to_ahb.scala 244:88] + master_ready <= _T_133 @[axi4_to_ahb.scala 244:20] buf_wr_en <= master_ready @[axi4_to_ahb.scala 245:17] - node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 246:33] - bypass_en <= _T_126 @[axi4_to_ahb.scala 246:17] - node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 247:47] - node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 247:62] - node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 247:78] - node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 247:30] - buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 247:24] - node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 248:44] - node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 248:58] - node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] - node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 248:32] - io.ahb_htrans <= _T_135 @[axi4_to_ahb.scala 248:21] + node _T_134 = and(master_ready, master_valid) @[axi4_to_ahb.scala 246:33] + bypass_en <= _T_134 @[axi4_to_ahb.scala 246:17] + node _T_135 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 247:47] + node _T_136 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 247:62] + node _T_137 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 247:78] + node _T_138 = mux(_T_135, _T_136, _T_137) @[axi4_to_ahb.scala 247:30] + buf_cmd_byte_ptr <= _T_138 @[axi4_to_ahb.scala 247:24] + node _T_139 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 248:44] + node _T_140 = or(_T_139, bypass_en) @[axi4_to_ahb.scala 248:58] + node _T_141 = bits(_T_140, 0, 0) @[Bitwise.scala 72:15] + node _T_142 = mux(_T_141, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_143 = and(UInt<2>("h02"), _T_142) @[axi4_to_ahb.scala 248:32] + io.ahb_htrans <= _T_143 @[axi4_to_ahb.scala 248:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] - when _T_136 : @[Conditional.scala 39:67] - node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 252:39] - node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 252:37] - node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 252:82] - node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 252:89] - node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 252:70] - node _T_142 = eq(_T_141, UInt<1>("h00")) @[axi4_to_ahb.scala 252:55] - node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 252:53] - master_ready <= _T_143 @[axi4_to_ahb.scala 252:20] - node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 253:34] - node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 253:62] - node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 253:69] - node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 253:49] - buf_wr_en <= _T_147 @[axi4_to_ahb.scala 253:17] - node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 254:45] - node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 254:82] - node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 254:110] - node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 254:117] - node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 254:97] - node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 254:138] - node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 254:67] - node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 254:26] - buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 254:20] - node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 255:37] - buf_state_en <= _T_156 @[axi4_to_ahb.scala 255:20] + node _T_144 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] + when _T_144 : @[Conditional.scala 39:67] + node _T_145 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 252:39] + node _T_146 = and(ahb_hready_q, _T_145) @[axi4_to_ahb.scala 252:37] + node _T_147 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 252:82] + node _T_148 = eq(_T_147, UInt<1>("h01")) @[axi4_to_ahb.scala 252:89] + node _T_149 = and(master_valid, _T_148) @[axi4_to_ahb.scala 252:70] + node _T_150 = eq(_T_149, UInt<1>("h00")) @[axi4_to_ahb.scala 252:55] + node _T_151 = and(_T_146, _T_150) @[axi4_to_ahb.scala 252:53] + master_ready <= _T_151 @[axi4_to_ahb.scala 252:20] + node _T_152 = and(master_valid, master_ready) @[axi4_to_ahb.scala 253:34] + node _T_153 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 253:62] + node _T_154 = eq(_T_153, UInt<1>("h00")) @[axi4_to_ahb.scala 253:69] + node _T_155 = and(_T_152, _T_154) @[axi4_to_ahb.scala 253:49] + buf_wr_en <= _T_155 @[axi4_to_ahb.scala 253:17] + node _T_156 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 254:45] + node _T_157 = and(master_valid, master_ready) @[axi4_to_ahb.scala 254:82] + node _T_158 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 254:110] + node _T_159 = eq(_T_158, UInt<1>("h00")) @[axi4_to_ahb.scala 254:117] + node _T_160 = and(_T_157, _T_159) @[axi4_to_ahb.scala 254:97] + node _T_161 = bits(_T_160, 0, 0) @[axi4_to_ahb.scala 254:138] + node _T_162 = mux(_T_161, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 254:67] + node _T_163 = mux(_T_156, UInt<3>("h07"), _T_162) @[axi4_to_ahb.scala 254:26] + buf_nxtstate <= _T_163 @[axi4_to_ahb.scala 254:20] + node _T_164 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 255:37] + buf_state_en <= _T_164 @[axi4_to_ahb.scala 255:20] buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 256:22] slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 257:23] slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 258:23] - node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 259:41] - node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 259:39] - slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 259:23] - node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 260:34] - node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 260:32] - cmd_done <= _T_160 @[axi4_to_ahb.scala 260:16] - node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 261:33] - node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 261:64] - node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 261:48] - node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 261:79] - bypass_en <= _T_164 @[axi4_to_ahb.scala 261:17] - node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 262:47] - node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 262:62] - node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 262:78] - node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 262:30] - buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 262:24] - node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 263:59] - node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 263:74] - node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 263:43] - node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] - node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 263:32] - io.ahb_htrans <= _T_174 @[axi4_to_ahb.scala 263:21] + node _T_165 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 259:41] + node _T_166 = and(buf_state_en, _T_165) @[axi4_to_ahb.scala 259:39] + slave_valid_pre <= _T_166 @[axi4_to_ahb.scala 259:23] + node _T_167 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 260:34] + node _T_168 = and(buf_state_en, _T_167) @[axi4_to_ahb.scala 260:32] + cmd_done <= _T_168 @[axi4_to_ahb.scala 260:16] + node _T_169 = and(master_ready, master_valid) @[axi4_to_ahb.scala 261:33] + node _T_170 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 261:64] + node _T_171 = and(_T_169, _T_170) @[axi4_to_ahb.scala 261:48] + node _T_172 = and(_T_171, buf_state_en) @[axi4_to_ahb.scala 261:79] + bypass_en <= _T_172 @[axi4_to_ahb.scala 261:17] + node _T_173 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 262:47] + node _T_174 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 262:62] + node _T_175 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 262:78] + node _T_176 = mux(_T_173, _T_174, _T_175) @[axi4_to_ahb.scala 262:30] + buf_cmd_byte_ptr <= _T_176 @[axi4_to_ahb.scala 262:24] + node _T_177 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 263:59] + node _T_178 = and(_T_177, buf_state_en) @[axi4_to_ahb.scala 263:74] + node _T_179 = eq(_T_178, UInt<1>("h00")) @[axi4_to_ahb.scala 263:43] + node _T_180 = bits(_T_179, 0, 0) @[Bitwise.scala 72:15] + node _T_181 = mux(_T_180, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_182 = and(UInt<2>("h02"), _T_181) @[axi4_to_ahb.scala 263:32] + io.ahb_htrans <= _T_182 @[axi4_to_ahb.scala 263:21] slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 264:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] - when _T_175 : @[Conditional.scala 39:67] + node _T_183 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] + when _T_183 : @[Conditional.scala 39:67] buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 268:20] - node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 269:51] - node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 269:58] - node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 269:36] - node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 269:72] - node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 269:70] - buf_state_en <= _T_180 @[axi4_to_ahb.scala 269:20] + node _T_184 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 269:51] + node _T_185 = neq(_T_184, UInt<1>("h00")) @[axi4_to_ahb.scala 269:58] + node _T_186 = and(ahb_hready_q, _T_185) @[axi4_to_ahb.scala 269:36] + node _T_187 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 269:72] + node _T_188 = and(_T_186, _T_187) @[axi4_to_ahb.scala 269:70] + buf_state_en <= _T_188 @[axi4_to_ahb.scala 269:20] slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 270:23] slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 271:20] - node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 272:35] - buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 272:24] - node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 273:47] - node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] - node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 273:37] - io.ahb_htrans <= _T_185 @[axi4_to_ahb.scala 273:21] + node _T_189 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 272:35] + buf_cmd_byte_ptr <= _T_189 @[axi4_to_ahb.scala 272:24] + node _T_190 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 273:47] + node _T_191 = bits(_T_190, 0, 0) @[Bitwise.scala 72:15] + node _T_192 = mux(_T_191, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_193 = and(UInt<2>("h02"), _T_192) @[axi4_to_ahb.scala 273:37] + io.ahb_htrans <= _T_193 @[axi4_to_ahb.scala 273:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_186 : @[Conditional.scala 39:67] + node _T_194 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] + when _T_194 : @[Conditional.scala 39:67] buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 277:20] - node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 278:37] - buf_state_en <= _T_187 @[axi4_to_ahb.scala 278:20] + node _T_195 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 278:37] + buf_state_en <= _T_195 @[axi4_to_ahb.scala 278:20] buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 279:22] slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 280:23] slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 281:23] slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 282:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_188 : @[Conditional.scala 39:67] + node _T_196 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] + when _T_196 : @[Conditional.scala 39:67] buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 286:20] - node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 287:33] - node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 287:63] - node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 287:70] - node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 287:48] - trxn_done <= _T_192 @[axi4_to_ahb.scala 287:17] + node _T_197 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 287:33] + node _T_198 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 287:63] + node _T_199 = neq(_T_198, UInt<1>("h00")) @[axi4_to_ahb.scala 287:70] + node _T_200 = and(_T_197, _T_199) @[axi4_to_ahb.scala 287:48] + trxn_done <= _T_200 @[axi4_to_ahb.scala 287:17] buf_state_en <= trxn_done @[axi4_to_ahb.scala 288:20] buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 289:27] slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 290:20] - node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 291:47] - node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 291:85] - node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 291:103] - node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 174:52] - node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 174:24] - node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 175:48] - node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 175:48] - node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 175:48] - node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 175:48] - node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 175:62] + node _T_201 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 291:47] + node _T_202 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 291:85] + node _T_203 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 291:103] + node _T_204 = add(_T_202, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] + node _T_205 = tail(_T_204, 1) @[axi4_to_ahb.scala 174:52] + node _T_206 = mux(UInt<1>("h01"), _T_205, _T_202) @[axi4_to_ahb.scala 174:24] + node _T_207 = bits(_T_203, 0, 0) @[axi4_to_ahb.scala 175:44] + node _T_208 = geq(UInt<1>("h00"), _T_206) @[axi4_to_ahb.scala 175:62] + node _T_209 = and(_T_207, _T_208) @[axi4_to_ahb.scala 175:48] + node _T_210 = orr(_T_209) @[axi4_to_ahb.scala 175:77] + node _T_211 = bits(_T_203, 1, 1) @[axi4_to_ahb.scala 175:44] + node _T_212 = geq(UInt<1>("h01"), _T_206) @[axi4_to_ahb.scala 175:62] node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 175:48] - node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 175:48] - node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 175:48] - node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 175:62] - node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 175:48] - node _T_223 = mux(_T_201, UInt<1>("h00"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_224 = mux(_T_204, UInt<1>("h01"), _T_223) @[Mux.scala 98:16] - node _T_225 = mux(_T_207, UInt<2>("h02"), _T_224) @[Mux.scala 98:16] - node _T_226 = mux(_T_210, UInt<2>("h03"), _T_225) @[Mux.scala 98:16] - node _T_227 = mux(_T_213, UInt<3>("h04"), _T_226) @[Mux.scala 98:16] - node _T_228 = mux(_T_216, UInt<3>("h05"), _T_227) @[Mux.scala 98:16] - node _T_229 = mux(_T_219, UInt<3>("h06"), _T_228) @[Mux.scala 98:16] - node _T_230 = mux(_T_222, UInt<3>("h07"), _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 291:30] - buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 291:24] - node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 292:65] - node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 292:44] - node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 292:127] - node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 292:145] - node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 174:52] - node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 174:24] - node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 175:48] - node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 175:48] - node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 175:48] - node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 175:48] - node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 175:48] - node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 175:48] - node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 175:48] - node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 175:62] - node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 175:48] - node _T_263 = mux(_T_241, UInt<1>("h00"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_264 = mux(_T_244, UInt<1>("h01"), _T_263) @[Mux.scala 98:16] - node _T_265 = mux(_T_247, UInt<2>("h02"), _T_264) @[Mux.scala 98:16] - node _T_266 = mux(_T_250, UInt<2>("h03"), _T_265) @[Mux.scala 98:16] - node _T_267 = mux(_T_253, UInt<3>("h04"), _T_266) @[Mux.scala 98:16] - node _T_268 = mux(_T_256, UInt<3>("h05"), _T_267) @[Mux.scala 98:16] - node _T_269 = mux(_T_259, UInt<3>("h06"), _T_268) @[Mux.scala 98:16] - node _T_270 = mux(_T_262, UInt<3>("h07"), _T_269) @[Mux.scala 98:16] - node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 292:92] - node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 292:92] - node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 292:163] - node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 292:79] - node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 292:29] - cmd_done <= _T_275 @[axi4_to_ahb.scala 292:16] - node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 293:43] - node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 293:32] - node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] - node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 293:57] - io.ahb_htrans <= _T_280 @[axi4_to_ahb.scala 293:21] + node _T_214 = orr(_T_213) @[axi4_to_ahb.scala 175:77] + node _T_215 = bits(_T_203, 2, 2) @[axi4_to_ahb.scala 175:44] + node _T_216 = geq(UInt<2>("h02"), _T_206) @[axi4_to_ahb.scala 175:62] + node _T_217 = and(_T_215, _T_216) @[axi4_to_ahb.scala 175:48] + node _T_218 = orr(_T_217) @[axi4_to_ahb.scala 175:77] + node _T_219 = bits(_T_203, 3, 3) @[axi4_to_ahb.scala 175:44] + node _T_220 = geq(UInt<2>("h03"), _T_206) @[axi4_to_ahb.scala 175:62] + node _T_221 = and(_T_219, _T_220) @[axi4_to_ahb.scala 175:48] + node _T_222 = orr(_T_221) @[axi4_to_ahb.scala 175:77] + node _T_223 = bits(_T_203, 4, 4) @[axi4_to_ahb.scala 175:44] + node _T_224 = geq(UInt<3>("h04"), _T_206) @[axi4_to_ahb.scala 175:62] + node _T_225 = and(_T_223, _T_224) @[axi4_to_ahb.scala 175:48] + node _T_226 = orr(_T_225) @[axi4_to_ahb.scala 175:77] + node _T_227 = bits(_T_203, 5, 5) @[axi4_to_ahb.scala 175:44] + node _T_228 = geq(UInt<3>("h05"), _T_206) @[axi4_to_ahb.scala 175:62] + node _T_229 = and(_T_227, _T_228) @[axi4_to_ahb.scala 175:48] + node _T_230 = orr(_T_229) @[axi4_to_ahb.scala 175:77] + node _T_231 = bits(_T_203, 6, 6) @[axi4_to_ahb.scala 175:44] + node _T_232 = geq(UInt<3>("h06"), _T_206) @[axi4_to_ahb.scala 175:62] + node _T_233 = and(_T_231, _T_232) @[axi4_to_ahb.scala 175:48] + node _T_234 = orr(_T_233) @[axi4_to_ahb.scala 175:77] + node _T_235 = bits(_T_203, 7, 7) @[axi4_to_ahb.scala 175:44] + node _T_236 = geq(UInt<3>("h07"), _T_206) @[axi4_to_ahb.scala 175:62] + node _T_237 = and(_T_235, _T_236) @[axi4_to_ahb.scala 175:48] + node _T_238 = orr(_T_237) @[axi4_to_ahb.scala 175:77] + node _T_239 = mux(_T_210, UInt<1>("h00"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_240 = mux(_T_214, UInt<1>("h01"), _T_239) @[Mux.scala 98:16] + node _T_241 = mux(_T_218, UInt<2>("h02"), _T_240) @[Mux.scala 98:16] + node _T_242 = mux(_T_222, UInt<2>("h03"), _T_241) @[Mux.scala 98:16] + node _T_243 = mux(_T_226, UInt<3>("h04"), _T_242) @[Mux.scala 98:16] + node _T_244 = mux(_T_230, UInt<3>("h05"), _T_243) @[Mux.scala 98:16] + node _T_245 = mux(_T_234, UInt<3>("h06"), _T_244) @[Mux.scala 98:16] + node _T_246 = mux(_T_238, UInt<3>("h07"), _T_245) @[Mux.scala 98:16] + node _T_247 = mux(_T_201, _T_246, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 291:30] + buf_cmd_byte_ptr <= _T_247 @[axi4_to_ahb.scala 291:24] + node _T_248 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 292:65] + node _T_249 = or(buf_aligned, _T_248) @[axi4_to_ahb.scala 292:44] + node _T_250 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 292:127] + node _T_251 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 292:145] + node _T_252 = add(_T_250, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] + node _T_253 = tail(_T_252, 1) @[axi4_to_ahb.scala 174:52] + node _T_254 = mux(UInt<1>("h01"), _T_253, _T_250) @[axi4_to_ahb.scala 174:24] + node _T_255 = bits(_T_251, 0, 0) @[axi4_to_ahb.scala 175:44] + node _T_256 = geq(UInt<1>("h00"), _T_254) @[axi4_to_ahb.scala 175:62] + node _T_257 = and(_T_255, _T_256) @[axi4_to_ahb.scala 175:48] + node _T_258 = orr(_T_257) @[axi4_to_ahb.scala 175:77] + node _T_259 = bits(_T_251, 1, 1) @[axi4_to_ahb.scala 175:44] + node _T_260 = geq(UInt<1>("h01"), _T_254) @[axi4_to_ahb.scala 175:62] + node _T_261 = and(_T_259, _T_260) @[axi4_to_ahb.scala 175:48] + node _T_262 = orr(_T_261) @[axi4_to_ahb.scala 175:77] + node _T_263 = bits(_T_251, 2, 2) @[axi4_to_ahb.scala 175:44] + node _T_264 = geq(UInt<2>("h02"), _T_254) @[axi4_to_ahb.scala 175:62] + node _T_265 = and(_T_263, _T_264) @[axi4_to_ahb.scala 175:48] + node _T_266 = orr(_T_265) @[axi4_to_ahb.scala 175:77] + node _T_267 = bits(_T_251, 3, 3) @[axi4_to_ahb.scala 175:44] + node _T_268 = geq(UInt<2>("h03"), _T_254) @[axi4_to_ahb.scala 175:62] + node _T_269 = and(_T_267, _T_268) @[axi4_to_ahb.scala 175:48] + node _T_270 = orr(_T_269) @[axi4_to_ahb.scala 175:77] + node _T_271 = bits(_T_251, 4, 4) @[axi4_to_ahb.scala 175:44] + node _T_272 = geq(UInt<3>("h04"), _T_254) @[axi4_to_ahb.scala 175:62] + node _T_273 = and(_T_271, _T_272) @[axi4_to_ahb.scala 175:48] + node _T_274 = orr(_T_273) @[axi4_to_ahb.scala 175:77] + node _T_275 = bits(_T_251, 5, 5) @[axi4_to_ahb.scala 175:44] + node _T_276 = geq(UInt<3>("h05"), _T_254) @[axi4_to_ahb.scala 175:62] + node _T_277 = and(_T_275, _T_276) @[axi4_to_ahb.scala 175:48] + node _T_278 = orr(_T_277) @[axi4_to_ahb.scala 175:77] + node _T_279 = bits(_T_251, 6, 6) @[axi4_to_ahb.scala 175:44] + node _T_280 = geq(UInt<3>("h06"), _T_254) @[axi4_to_ahb.scala 175:62] + node _T_281 = and(_T_279, _T_280) @[axi4_to_ahb.scala 175:48] + node _T_282 = orr(_T_281) @[axi4_to_ahb.scala 175:77] + node _T_283 = bits(_T_251, 7, 7) @[axi4_to_ahb.scala 175:44] + node _T_284 = geq(UInt<3>("h07"), _T_254) @[axi4_to_ahb.scala 175:62] + node _T_285 = and(_T_283, _T_284) @[axi4_to_ahb.scala 175:48] + node _T_286 = orr(_T_285) @[axi4_to_ahb.scala 175:77] + node _T_287 = mux(_T_258, UInt<1>("h00"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_288 = mux(_T_262, UInt<1>("h01"), _T_287) @[Mux.scala 98:16] + node _T_289 = mux(_T_266, UInt<2>("h02"), _T_288) @[Mux.scala 98:16] + node _T_290 = mux(_T_270, UInt<2>("h03"), _T_289) @[Mux.scala 98:16] + node _T_291 = mux(_T_274, UInt<3>("h04"), _T_290) @[Mux.scala 98:16] + node _T_292 = mux(_T_278, UInt<3>("h05"), _T_291) @[Mux.scala 98:16] + node _T_293 = mux(_T_282, UInt<3>("h06"), _T_292) @[Mux.scala 98:16] + node _T_294 = mux(_T_286, UInt<3>("h07"), _T_293) @[Mux.scala 98:16] + node _T_295 = dshr(buf_byteen, _T_294) @[axi4_to_ahb.scala 292:92] + node _T_296 = bits(_T_295, 0, 0) @[axi4_to_ahb.scala 292:92] + node _T_297 = eq(_T_296, UInt<1>("h00")) @[axi4_to_ahb.scala 292:163] + node _T_298 = or(_T_249, _T_297) @[axi4_to_ahb.scala 292:79] + node _T_299 = and(trxn_done, _T_298) @[axi4_to_ahb.scala 292:29] + cmd_done <= _T_299 @[axi4_to_ahb.scala 292:16] + node _T_300 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 293:43] + node _T_301 = eq(_T_300, UInt<1>("h00")) @[axi4_to_ahb.scala 293:32] + node _T_302 = bits(_T_301, 0, 0) @[Bitwise.scala 72:15] + node _T_303 = mux(_T_302, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_304 = and(_T_303, UInt<2>("h02")) @[axi4_to_ahb.scala 293:57] + io.ahb_htrans <= _T_304 @[axi4_to_ahb.scala 293:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] - when _T_281 : @[Conditional.scala 39:67] - node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 297:34] - node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 297:50] - buf_state_en <= _T_283 @[axi4_to_ahb.scala 297:20] - node _T_284 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 298:35] - node _T_285 = or(_T_284, ahb_hresp_q) @[axi4_to_ahb.scala 298:51] - node _T_286 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 298:68] - node _T_287 = and(_T_285, _T_286) @[axi4_to_ahb.scala 298:66] - node _T_288 = and(_T_287, slave_ready) @[axi4_to_ahb.scala 298:81] - master_ready <= _T_288 @[axi4_to_ahb.scala 298:20] - node _T_289 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 299:42] - node _T_290 = or(ahb_hresp_q, _T_289) @[axi4_to_ahb.scala 299:40] - node _T_291 = bits(_T_290, 0, 0) @[axi4_to_ahb.scala 299:62] - node _T_292 = and(master_valid, master_ready) @[axi4_to_ahb.scala 299:90] - node _T_293 = bits(_T_292, 0, 0) @[axi4_to_ahb.scala 299:112] - node _T_294 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 299:131] - node _T_295 = eq(_T_294, UInt<1>("h01")) @[axi4_to_ahb.scala 299:138] - node _T_296 = mux(_T_295, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 299:119] - node _T_297 = mux(_T_293, _T_296, UInt<3>("h00")) @[axi4_to_ahb.scala 299:75] - node _T_298 = mux(_T_291, UInt<3>("h05"), _T_297) @[axi4_to_ahb.scala 299:26] - buf_nxtstate <= _T_298 @[axi4_to_ahb.scala 299:20] + node _T_305 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] + when _T_305 : @[Conditional.scala 39:67] + node _T_306 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 297:34] + node _T_307 = or(_T_306, ahb_hresp_q) @[axi4_to_ahb.scala 297:50] + buf_state_en <= _T_307 @[axi4_to_ahb.scala 297:20] + node _T_308 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 298:35] + node _T_309 = or(_T_308, ahb_hresp_q) @[axi4_to_ahb.scala 298:51] + node _T_310 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 298:68] + node _T_311 = and(_T_309, _T_310) @[axi4_to_ahb.scala 298:66] + node _T_312 = and(_T_311, slave_ready) @[axi4_to_ahb.scala 298:81] + master_ready <= _T_312 @[axi4_to_ahb.scala 298:20] + node _T_313 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 299:42] + node _T_314 = or(ahb_hresp_q, _T_313) @[axi4_to_ahb.scala 299:40] + node _T_315 = bits(_T_314, 0, 0) @[axi4_to_ahb.scala 299:62] + node _T_316 = and(master_valid, master_ready) @[axi4_to_ahb.scala 299:90] + node _T_317 = bits(_T_316, 0, 0) @[axi4_to_ahb.scala 299:112] + node _T_318 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 299:131] + node _T_319 = eq(_T_318, UInt<1>("h01")) @[axi4_to_ahb.scala 299:138] + node _T_320 = mux(_T_319, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 299:119] + node _T_321 = mux(_T_317, _T_320, UInt<3>("h00")) @[axi4_to_ahb.scala 299:75] + node _T_322 = mux(_T_315, UInt<3>("h05"), _T_321) @[axi4_to_ahb.scala 299:26] + buf_nxtstate <= _T_322 @[axi4_to_ahb.scala 299:20] slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 300:23] slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 301:23] - node _T_299 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 302:34] - node _T_300 = eq(_T_299, UInt<1>("h01")) @[axi4_to_ahb.scala 302:41] - buf_write_in <= _T_300 @[axi4_to_ahb.scala 302:20] - node _T_301 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 303:50] - node _T_302 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 303:78] - node _T_303 = or(_T_301, _T_302) @[axi4_to_ahb.scala 303:62] - node _T_304 = and(buf_state_en, _T_303) @[axi4_to_ahb.scala 303:33] - buf_wr_en <= _T_304 @[axi4_to_ahb.scala 303:17] + node _T_323 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 302:34] + node _T_324 = eq(_T_323, UInt<1>("h01")) @[axi4_to_ahb.scala 302:41] + buf_write_in <= _T_324 @[axi4_to_ahb.scala 302:20] + node _T_325 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 303:50] + node _T_326 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 303:78] + node _T_327 = or(_T_325, _T_326) @[axi4_to_ahb.scala 303:62] + node _T_328 = and(buf_state_en, _T_327) @[axi4_to_ahb.scala 303:33] + buf_wr_en <= _T_328 @[axi4_to_ahb.scala 303:17] buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 304:22] - node _T_305 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 305:63] - node _T_306 = neq(_T_305, UInt<2>("h00")) @[axi4_to_ahb.scala 305:70] - node _T_307 = and(ahb_hready_q, _T_306) @[axi4_to_ahb.scala 305:48] - node _T_308 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 305:109] - node _T_309 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 305:171] - node _T_310 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 305:189] - node _T_311 = add(_T_309, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_312 = tail(_T_311, 1) @[axi4_to_ahb.scala 174:52] - node _T_313 = mux(UInt<1>("h01"), _T_312, _T_309) @[axi4_to_ahb.scala 174:24] - node _T_314 = bits(_T_310, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_315 = geq(UInt<1>("h00"), _T_313) @[axi4_to_ahb.scala 175:62] - node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 175:48] - node _T_317 = bits(_T_310, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_318 = geq(UInt<1>("h01"), _T_313) @[axi4_to_ahb.scala 175:62] - node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 175:48] - node _T_320 = bits(_T_310, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_321 = geq(UInt<2>("h02"), _T_313) @[axi4_to_ahb.scala 175:62] - node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 175:48] - node _T_323 = bits(_T_310, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_324 = geq(UInt<2>("h03"), _T_313) @[axi4_to_ahb.scala 175:62] - node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 175:48] - node _T_326 = bits(_T_310, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_327 = geq(UInt<3>("h04"), _T_313) @[axi4_to_ahb.scala 175:62] - node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 175:48] - node _T_329 = bits(_T_310, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_330 = geq(UInt<3>("h05"), _T_313) @[axi4_to_ahb.scala 175:62] - node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 175:48] - node _T_332 = bits(_T_310, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_333 = geq(UInt<3>("h06"), _T_313) @[axi4_to_ahb.scala 175:62] - node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 175:48] - node _T_335 = bits(_T_310, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_336 = geq(UInt<3>("h07"), _T_313) @[axi4_to_ahb.scala 175:62] - node _T_337 = and(_T_335, _T_336) @[axi4_to_ahb.scala 175:48] - node _T_338 = mux(_T_316, UInt<1>("h00"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_339 = mux(_T_319, UInt<1>("h01"), _T_338) @[Mux.scala 98:16] - node _T_340 = mux(_T_322, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] - node _T_341 = mux(_T_325, UInt<2>("h03"), _T_340) @[Mux.scala 98:16] - node _T_342 = mux(_T_328, UInt<3>("h04"), _T_341) @[Mux.scala 98:16] - node _T_343 = mux(_T_331, UInt<3>("h05"), _T_342) @[Mux.scala 98:16] - node _T_344 = mux(_T_334, UInt<3>("h06"), _T_343) @[Mux.scala 98:16] - node _T_345 = mux(_T_337, UInt<3>("h07"), _T_344) @[Mux.scala 98:16] - node _T_346 = dshr(buf_byteen, _T_345) @[axi4_to_ahb.scala 305:136] - node _T_347 = bits(_T_346, 0, 0) @[axi4_to_ahb.scala 305:136] - node _T_348 = eq(_T_347, UInt<1>("h00")) @[axi4_to_ahb.scala 305:207] - node _T_349 = or(_T_308, _T_348) @[axi4_to_ahb.scala 305:123] - node _T_350 = and(_T_307, _T_349) @[axi4_to_ahb.scala 305:87] - node _T_351 = or(ahb_hresp_q, _T_350) @[axi4_to_ahb.scala 305:32] - cmd_done <= _T_351 @[axi4_to_ahb.scala 305:16] - node _T_352 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 306:33] - node _T_353 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 306:64] - node _T_354 = and(_T_352, _T_353) @[axi4_to_ahb.scala 306:48] - bypass_en <= _T_354 @[axi4_to_ahb.scala 306:17] - node _T_355 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 307:44] - node _T_356 = eq(_T_355, UInt<1>("h00")) @[axi4_to_ahb.scala 307:33] - node _T_357 = or(_T_356, bypass_en) @[axi4_to_ahb.scala 307:57] - node _T_358 = bits(_T_357, 0, 0) @[Bitwise.scala 72:15] - node _T_359 = mux(_T_358, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_360 = and(_T_359, UInt<2>("h02")) @[axi4_to_ahb.scala 307:71] - io.ahb_htrans <= _T_360 @[axi4_to_ahb.scala 307:21] - node _T_361 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 308:55] - node _T_362 = and(buf_state_en, _T_361) @[axi4_to_ahb.scala 308:39] - slave_valid_pre <= _T_362 @[axi4_to_ahb.scala 308:23] - node _T_363 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 309:33] - node _T_364 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 309:63] - node _T_365 = neq(_T_364, UInt<1>("h00")) @[axi4_to_ahb.scala 309:70] - node _T_366 = and(_T_363, _T_365) @[axi4_to_ahb.scala 309:48] - trxn_done <= _T_366 @[axi4_to_ahb.scala 309:17] - node _T_367 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 310:40] - buf_cmd_byte_ptr_en <= _T_367 @[axi4_to_ahb.scala 310:27] - node _T_368 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 311:76] - node _T_369 = add(UInt<1>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_370 = tail(_T_369, 1) @[axi4_to_ahb.scala 174:52] - node _T_371 = mux(UInt<1>("h00"), _T_370, UInt<1>("h00")) @[axi4_to_ahb.scala 174:24] - node _T_372 = bits(_T_368, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_373 = geq(UInt<1>("h00"), _T_371) @[axi4_to_ahb.scala 175:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 175:48] - node _T_375 = bits(_T_368, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_376 = geq(UInt<1>("h01"), _T_371) @[axi4_to_ahb.scala 175:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 175:48] - node _T_378 = bits(_T_368, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_379 = geq(UInt<2>("h02"), _T_371) @[axi4_to_ahb.scala 175:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 175:48] - node _T_381 = bits(_T_368, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_382 = geq(UInt<2>("h03"), _T_371) @[axi4_to_ahb.scala 175:62] - node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 175:48] - node _T_384 = bits(_T_368, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_385 = geq(UInt<3>("h04"), _T_371) @[axi4_to_ahb.scala 175:62] - node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 175:48] - node _T_387 = bits(_T_368, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_388 = geq(UInt<3>("h05"), _T_371) @[axi4_to_ahb.scala 175:62] - node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 175:48] - node _T_390 = bits(_T_368, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_391 = geq(UInt<3>("h06"), _T_371) @[axi4_to_ahb.scala 175:62] - node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 175:48] - node _T_393 = bits(_T_368, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_394 = geq(UInt<3>("h07"), _T_371) @[axi4_to_ahb.scala 175:62] - node _T_395 = and(_T_393, _T_394) @[axi4_to_ahb.scala 175:48] - node _T_396 = mux(_T_374, UInt<1>("h00"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_397 = mux(_T_377, UInt<1>("h01"), _T_396) @[Mux.scala 98:16] - node _T_398 = mux(_T_380, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] - node _T_399 = mux(_T_383, UInt<2>("h03"), _T_398) @[Mux.scala 98:16] - node _T_400 = mux(_T_386, UInt<3>("h04"), _T_399) @[Mux.scala 98:16] - node _T_401 = mux(_T_389, UInt<3>("h05"), _T_400) @[Mux.scala 98:16] - node _T_402 = mux(_T_392, UInt<3>("h06"), _T_401) @[Mux.scala 98:16] - node _T_403 = mux(_T_395, UInt<3>("h07"), _T_402) @[Mux.scala 98:16] - node _T_404 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 311:142] - node _T_405 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 311:160] - node _T_406 = add(_T_404, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] - node _T_407 = tail(_T_406, 1) @[axi4_to_ahb.scala 174:52] - node _T_408 = mux(UInt<1>("h01"), _T_407, _T_404) @[axi4_to_ahb.scala 174:24] - node _T_409 = bits(_T_405, 0, 0) @[axi4_to_ahb.scala 175:44] - node _T_410 = geq(UInt<1>("h00"), _T_408) @[axi4_to_ahb.scala 175:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 175:48] - node _T_412 = bits(_T_405, 1, 1) @[axi4_to_ahb.scala 175:44] - node _T_413 = geq(UInt<1>("h01"), _T_408) @[axi4_to_ahb.scala 175:62] + node _T_329 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 305:63] + node _T_330 = neq(_T_329, UInt<2>("h00")) @[axi4_to_ahb.scala 305:70] + node _T_331 = and(ahb_hready_q, _T_330) @[axi4_to_ahb.scala 305:48] + node _T_332 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 305:109] + node _T_333 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 305:171] + node _T_334 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 305:189] + node _T_335 = add(_T_333, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] + node _T_336 = tail(_T_335, 1) @[axi4_to_ahb.scala 174:52] + node _T_337 = mux(UInt<1>("h01"), _T_336, _T_333) @[axi4_to_ahb.scala 174:24] + node _T_338 = bits(_T_334, 0, 0) @[axi4_to_ahb.scala 175:44] + node _T_339 = geq(UInt<1>("h00"), _T_337) @[axi4_to_ahb.scala 175:62] + node _T_340 = and(_T_338, _T_339) @[axi4_to_ahb.scala 175:48] + node _T_341 = orr(_T_340) @[axi4_to_ahb.scala 175:77] + node _T_342 = bits(_T_334, 1, 1) @[axi4_to_ahb.scala 175:44] + node _T_343 = geq(UInt<1>("h01"), _T_337) @[axi4_to_ahb.scala 175:62] + node _T_344 = and(_T_342, _T_343) @[axi4_to_ahb.scala 175:48] + node _T_345 = orr(_T_344) @[axi4_to_ahb.scala 175:77] + node _T_346 = bits(_T_334, 2, 2) @[axi4_to_ahb.scala 175:44] + node _T_347 = geq(UInt<2>("h02"), _T_337) @[axi4_to_ahb.scala 175:62] + node _T_348 = and(_T_346, _T_347) @[axi4_to_ahb.scala 175:48] + node _T_349 = orr(_T_348) @[axi4_to_ahb.scala 175:77] + node _T_350 = bits(_T_334, 3, 3) @[axi4_to_ahb.scala 175:44] + node _T_351 = geq(UInt<2>("h03"), _T_337) @[axi4_to_ahb.scala 175:62] + node _T_352 = and(_T_350, _T_351) @[axi4_to_ahb.scala 175:48] + node _T_353 = orr(_T_352) @[axi4_to_ahb.scala 175:77] + node _T_354 = bits(_T_334, 4, 4) @[axi4_to_ahb.scala 175:44] + node _T_355 = geq(UInt<3>("h04"), _T_337) @[axi4_to_ahb.scala 175:62] + node _T_356 = and(_T_354, _T_355) @[axi4_to_ahb.scala 175:48] + node _T_357 = orr(_T_356) @[axi4_to_ahb.scala 175:77] + node _T_358 = bits(_T_334, 5, 5) @[axi4_to_ahb.scala 175:44] + node _T_359 = geq(UInt<3>("h05"), _T_337) @[axi4_to_ahb.scala 175:62] + node _T_360 = and(_T_358, _T_359) @[axi4_to_ahb.scala 175:48] + node _T_361 = orr(_T_360) @[axi4_to_ahb.scala 175:77] + node _T_362 = bits(_T_334, 6, 6) @[axi4_to_ahb.scala 175:44] + node _T_363 = geq(UInt<3>("h06"), _T_337) @[axi4_to_ahb.scala 175:62] + node _T_364 = and(_T_362, _T_363) @[axi4_to_ahb.scala 175:48] + node _T_365 = orr(_T_364) @[axi4_to_ahb.scala 175:77] + node _T_366 = bits(_T_334, 7, 7) @[axi4_to_ahb.scala 175:44] + node _T_367 = geq(UInt<3>("h07"), _T_337) @[axi4_to_ahb.scala 175:62] + node _T_368 = and(_T_366, _T_367) @[axi4_to_ahb.scala 175:48] + node _T_369 = orr(_T_368) @[axi4_to_ahb.scala 175:77] + node _T_370 = mux(_T_341, UInt<1>("h00"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_371 = mux(_T_345, UInt<1>("h01"), _T_370) @[Mux.scala 98:16] + node _T_372 = mux(_T_349, UInt<2>("h02"), _T_371) @[Mux.scala 98:16] + node _T_373 = mux(_T_353, UInt<2>("h03"), _T_372) @[Mux.scala 98:16] + node _T_374 = mux(_T_357, UInt<3>("h04"), _T_373) @[Mux.scala 98:16] + node _T_375 = mux(_T_361, UInt<3>("h05"), _T_374) @[Mux.scala 98:16] + node _T_376 = mux(_T_365, UInt<3>("h06"), _T_375) @[Mux.scala 98:16] + node _T_377 = mux(_T_369, UInt<3>("h07"), _T_376) @[Mux.scala 98:16] + node _T_378 = dshr(buf_byteen, _T_377) @[axi4_to_ahb.scala 305:136] + node _T_379 = bits(_T_378, 0, 0) @[axi4_to_ahb.scala 305:136] + node _T_380 = eq(_T_379, UInt<1>("h00")) @[axi4_to_ahb.scala 305:207] + node _T_381 = or(_T_332, _T_380) @[axi4_to_ahb.scala 305:123] + node _T_382 = and(_T_331, _T_381) @[axi4_to_ahb.scala 305:87] + node _T_383 = or(ahb_hresp_q, _T_382) @[axi4_to_ahb.scala 305:32] + cmd_done <= _T_383 @[axi4_to_ahb.scala 305:16] + node _T_384 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 306:33] + node _T_385 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 306:64] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 306:48] + bypass_en <= _T_386 @[axi4_to_ahb.scala 306:17] + node _T_387 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 307:44] + node _T_388 = eq(_T_387, UInt<1>("h00")) @[axi4_to_ahb.scala 307:33] + node _T_389 = or(_T_388, bypass_en) @[axi4_to_ahb.scala 307:57] + node _T_390 = bits(_T_389, 0, 0) @[Bitwise.scala 72:15] + node _T_391 = mux(_T_390, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_392 = and(_T_391, UInt<2>("h02")) @[axi4_to_ahb.scala 307:71] + io.ahb_htrans <= _T_392 @[axi4_to_ahb.scala 307:21] + node _T_393 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 308:55] + node _T_394 = and(buf_state_en, _T_393) @[axi4_to_ahb.scala 308:39] + slave_valid_pre <= _T_394 @[axi4_to_ahb.scala 308:23] + node _T_395 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 309:33] + node _T_396 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 309:63] + node _T_397 = neq(_T_396, UInt<1>("h00")) @[axi4_to_ahb.scala 309:70] + node _T_398 = and(_T_395, _T_397) @[axi4_to_ahb.scala 309:48] + trxn_done <= _T_398 @[axi4_to_ahb.scala 309:17] + node _T_399 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 310:40] + buf_cmd_byte_ptr_en <= _T_399 @[axi4_to_ahb.scala 310:27] + node _T_400 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 311:76] + node _T_401 = add(UInt<1>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] + node _T_402 = tail(_T_401, 1) @[axi4_to_ahb.scala 174:52] + node _T_403 = mux(UInt<1>("h00"), _T_402, UInt<1>("h00")) @[axi4_to_ahb.scala 174:24] + node _T_404 = bits(_T_400, 0, 0) @[axi4_to_ahb.scala 175:44] + node _T_405 = geq(UInt<1>("h00"), _T_403) @[axi4_to_ahb.scala 175:62] + node _T_406 = and(_T_404, _T_405) @[axi4_to_ahb.scala 175:48] + node _T_407 = orr(_T_406) @[axi4_to_ahb.scala 175:77] + node _T_408 = bits(_T_400, 1, 1) @[axi4_to_ahb.scala 175:44] + node _T_409 = geq(UInt<1>("h01"), _T_403) @[axi4_to_ahb.scala 175:62] + node _T_410 = and(_T_408, _T_409) @[axi4_to_ahb.scala 175:48] + node _T_411 = orr(_T_410) @[axi4_to_ahb.scala 175:77] + node _T_412 = bits(_T_400, 2, 2) @[axi4_to_ahb.scala 175:44] + node _T_413 = geq(UInt<2>("h02"), _T_403) @[axi4_to_ahb.scala 175:62] node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 175:48] - node _T_415 = bits(_T_405, 2, 2) @[axi4_to_ahb.scala 175:44] - node _T_416 = geq(UInt<2>("h02"), _T_408) @[axi4_to_ahb.scala 175:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 175:48] - node _T_418 = bits(_T_405, 3, 3) @[axi4_to_ahb.scala 175:44] - node _T_419 = geq(UInt<2>("h03"), _T_408) @[axi4_to_ahb.scala 175:62] - node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 175:48] - node _T_421 = bits(_T_405, 4, 4) @[axi4_to_ahb.scala 175:44] - node _T_422 = geq(UInt<3>("h04"), _T_408) @[axi4_to_ahb.scala 175:62] - node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 175:48] - node _T_424 = bits(_T_405, 5, 5) @[axi4_to_ahb.scala 175:44] - node _T_425 = geq(UInt<3>("h05"), _T_408) @[axi4_to_ahb.scala 175:62] + node _T_415 = orr(_T_414) @[axi4_to_ahb.scala 175:77] + node _T_416 = bits(_T_400, 3, 3) @[axi4_to_ahb.scala 175:44] + node _T_417 = geq(UInt<2>("h03"), _T_403) @[axi4_to_ahb.scala 175:62] + node _T_418 = and(_T_416, _T_417) @[axi4_to_ahb.scala 175:48] + node _T_419 = orr(_T_418) @[axi4_to_ahb.scala 175:77] + node _T_420 = bits(_T_400, 4, 4) @[axi4_to_ahb.scala 175:44] + node _T_421 = geq(UInt<3>("h04"), _T_403) @[axi4_to_ahb.scala 175:62] + node _T_422 = and(_T_420, _T_421) @[axi4_to_ahb.scala 175:48] + node _T_423 = orr(_T_422) @[axi4_to_ahb.scala 175:77] + node _T_424 = bits(_T_400, 5, 5) @[axi4_to_ahb.scala 175:44] + node _T_425 = geq(UInt<3>("h05"), _T_403) @[axi4_to_ahb.scala 175:62] node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 175:48] - node _T_427 = bits(_T_405, 6, 6) @[axi4_to_ahb.scala 175:44] - node _T_428 = geq(UInt<3>("h06"), _T_408) @[axi4_to_ahb.scala 175:62] - node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 175:48] - node _T_430 = bits(_T_405, 7, 7) @[axi4_to_ahb.scala 175:44] - node _T_431 = geq(UInt<3>("h07"), _T_408) @[axi4_to_ahb.scala 175:62] - node _T_432 = and(_T_430, _T_431) @[axi4_to_ahb.scala 175:48] - node _T_433 = mux(_T_411, UInt<1>("h00"), UInt<3>("h07")) @[Mux.scala 98:16] - node _T_434 = mux(_T_414, UInt<1>("h01"), _T_433) @[Mux.scala 98:16] - node _T_435 = mux(_T_417, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] - node _T_436 = mux(_T_420, UInt<2>("h03"), _T_435) @[Mux.scala 98:16] - node _T_437 = mux(_T_423, UInt<3>("h04"), _T_436) @[Mux.scala 98:16] - node _T_438 = mux(_T_426, UInt<3>("h05"), _T_437) @[Mux.scala 98:16] - node _T_439 = mux(_T_429, UInt<3>("h06"), _T_438) @[Mux.scala 98:16] - node _T_440 = mux(_T_432, UInt<3>("h07"), _T_439) @[Mux.scala 98:16] - node _T_441 = mux(trxn_done, _T_440, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 311:97] - node _T_442 = mux(bypass_en, _T_403, _T_441) @[axi4_to_ahb.scala 311:30] - buf_cmd_byte_ptr <= _T_442 @[axi4_to_ahb.scala 311:24] + node _T_427 = orr(_T_426) @[axi4_to_ahb.scala 175:77] + node _T_428 = bits(_T_400, 6, 6) @[axi4_to_ahb.scala 175:44] + node _T_429 = geq(UInt<3>("h06"), _T_403) @[axi4_to_ahb.scala 175:62] + node _T_430 = and(_T_428, _T_429) @[axi4_to_ahb.scala 175:48] + node _T_431 = orr(_T_430) @[axi4_to_ahb.scala 175:77] + node _T_432 = bits(_T_400, 7, 7) @[axi4_to_ahb.scala 175:44] + node _T_433 = geq(UInt<3>("h07"), _T_403) @[axi4_to_ahb.scala 175:62] + node _T_434 = and(_T_432, _T_433) @[axi4_to_ahb.scala 175:48] + node _T_435 = orr(_T_434) @[axi4_to_ahb.scala 175:77] + node _T_436 = mux(_T_407, UInt<1>("h00"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_437 = mux(_T_411, UInt<1>("h01"), _T_436) @[Mux.scala 98:16] + node _T_438 = mux(_T_415, UInt<2>("h02"), _T_437) @[Mux.scala 98:16] + node _T_439 = mux(_T_419, UInt<2>("h03"), _T_438) @[Mux.scala 98:16] + node _T_440 = mux(_T_423, UInt<3>("h04"), _T_439) @[Mux.scala 98:16] + node _T_441 = mux(_T_427, UInt<3>("h05"), _T_440) @[Mux.scala 98:16] + node _T_442 = mux(_T_431, UInt<3>("h06"), _T_441) @[Mux.scala 98:16] + node _T_443 = mux(_T_435, UInt<3>("h07"), _T_442) @[Mux.scala 98:16] + node _T_444 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 311:142] + node _T_445 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 311:160] + node _T_446 = add(_T_444, UInt<1>("h01")) @[axi4_to_ahb.scala 174:52] + node _T_447 = tail(_T_446, 1) @[axi4_to_ahb.scala 174:52] + node _T_448 = mux(UInt<1>("h01"), _T_447, _T_444) @[axi4_to_ahb.scala 174:24] + node _T_449 = bits(_T_445, 0, 0) @[axi4_to_ahb.scala 175:44] + node _T_450 = geq(UInt<1>("h00"), _T_448) @[axi4_to_ahb.scala 175:62] + node _T_451 = and(_T_449, _T_450) @[axi4_to_ahb.scala 175:48] + node _T_452 = orr(_T_451) @[axi4_to_ahb.scala 175:77] + node _T_453 = bits(_T_445, 1, 1) @[axi4_to_ahb.scala 175:44] + node _T_454 = geq(UInt<1>("h01"), _T_448) @[axi4_to_ahb.scala 175:62] + node _T_455 = and(_T_453, _T_454) @[axi4_to_ahb.scala 175:48] + node _T_456 = orr(_T_455) @[axi4_to_ahb.scala 175:77] + node _T_457 = bits(_T_445, 2, 2) @[axi4_to_ahb.scala 175:44] + node _T_458 = geq(UInt<2>("h02"), _T_448) @[axi4_to_ahb.scala 175:62] + node _T_459 = and(_T_457, _T_458) @[axi4_to_ahb.scala 175:48] + node _T_460 = orr(_T_459) @[axi4_to_ahb.scala 175:77] + node _T_461 = bits(_T_445, 3, 3) @[axi4_to_ahb.scala 175:44] + node _T_462 = geq(UInt<2>("h03"), _T_448) @[axi4_to_ahb.scala 175:62] + node _T_463 = and(_T_461, _T_462) @[axi4_to_ahb.scala 175:48] + node _T_464 = orr(_T_463) @[axi4_to_ahb.scala 175:77] + node _T_465 = bits(_T_445, 4, 4) @[axi4_to_ahb.scala 175:44] + node _T_466 = geq(UInt<3>("h04"), _T_448) @[axi4_to_ahb.scala 175:62] + node _T_467 = and(_T_465, _T_466) @[axi4_to_ahb.scala 175:48] + node _T_468 = orr(_T_467) @[axi4_to_ahb.scala 175:77] + node _T_469 = bits(_T_445, 5, 5) @[axi4_to_ahb.scala 175:44] + node _T_470 = geq(UInt<3>("h05"), _T_448) @[axi4_to_ahb.scala 175:62] + node _T_471 = and(_T_469, _T_470) @[axi4_to_ahb.scala 175:48] + node _T_472 = orr(_T_471) @[axi4_to_ahb.scala 175:77] + node _T_473 = bits(_T_445, 6, 6) @[axi4_to_ahb.scala 175:44] + node _T_474 = geq(UInt<3>("h06"), _T_448) @[axi4_to_ahb.scala 175:62] + node _T_475 = and(_T_473, _T_474) @[axi4_to_ahb.scala 175:48] + node _T_476 = orr(_T_475) @[axi4_to_ahb.scala 175:77] + node _T_477 = bits(_T_445, 7, 7) @[axi4_to_ahb.scala 175:44] + node _T_478 = geq(UInt<3>("h07"), _T_448) @[axi4_to_ahb.scala 175:62] + node _T_479 = and(_T_477, _T_478) @[axi4_to_ahb.scala 175:48] + node _T_480 = orr(_T_479) @[axi4_to_ahb.scala 175:77] + node _T_481 = mux(_T_452, UInt<1>("h00"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_482 = mux(_T_456, UInt<1>("h01"), _T_481) @[Mux.scala 98:16] + node _T_483 = mux(_T_460, UInt<2>("h02"), _T_482) @[Mux.scala 98:16] + node _T_484 = mux(_T_464, UInt<2>("h03"), _T_483) @[Mux.scala 98:16] + node _T_485 = mux(_T_468, UInt<3>("h04"), _T_484) @[Mux.scala 98:16] + node _T_486 = mux(_T_472, UInt<3>("h05"), _T_485) @[Mux.scala 98:16] + node _T_487 = mux(_T_476, UInt<3>("h06"), _T_486) @[Mux.scala 98:16] + node _T_488 = mux(_T_480, UInt<3>("h07"), _T_487) @[Mux.scala 98:16] + node _T_489 = mux(trxn_done, _T_488, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 311:97] + node _T_490 = mux(bypass_en, _T_443, _T_489) @[axi4_to_ahb.scala 311:30] + buf_cmd_byte_ptr <= _T_490 @[axi4_to_ahb.scala 311:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_443 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] - when _T_443 : @[Conditional.scala 39:67] + node _T_491 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] + when _T_491 : @[Conditional.scala 39:67] buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 315:20] buf_state_en <= slave_ready @[axi4_to_ahb.scala 316:20] slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 317:23] slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 318:23] skip @[Conditional.scala 39:67] cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 322:16] - node _T_444 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 323:33] - node _T_445 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 323:73] - node _T_446 = eq(_T_445, UInt<1>("h01")) @[axi4_to_ahb.scala 323:80] - node _T_447 = and(buf_aligned_in, _T_446) @[axi4_to_ahb.scala 323:60] - node _T_448 = bits(_T_447, 0, 0) @[axi4_to_ahb.scala 323:100] - node _T_449 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 323:132] - node _T_450 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 166:50] - node _T_451 = eq(_T_450, UInt<8>("h0ff")) @[axi4_to_ahb.scala 166:57] - node _T_452 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 166:81] - node _T_453 = eq(_T_452, UInt<8>("h0f")) @[axi4_to_ahb.scala 166:88] - node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 166:70] - node _T_455 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 166:117] - node _T_456 = eq(_T_455, UInt<8>("h03")) @[axi4_to_ahb.scala 166:124] - node _T_457 = or(_T_454, _T_456) @[axi4_to_ahb.scala 166:106] - node _T_458 = bits(_T_457, 0, 0) @[Bitwise.scala 72:15] - node _T_459 = mux(_T_458, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_460 = and(UInt<3>("h00"), _T_459) @[axi4_to_ahb.scala 166:29] - node _T_461 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 167:35] - node _T_462 = eq(_T_461, UInt<8>("h0c")) @[axi4_to_ahb.scala 167:42] - node _T_463 = bits(_T_462, 0, 0) @[Bitwise.scala 72:15] - node _T_464 = mux(_T_463, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_465 = and(UInt<2>("h02"), _T_464) @[axi4_to_ahb.scala 167:15] - node _T_466 = or(_T_460, _T_465) @[axi4_to_ahb.scala 166:146] - node _T_467 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 168:36] - node _T_468 = eq(_T_467, UInt<8>("h0f0")) @[axi4_to_ahb.scala 168:43] - node _T_469 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 168:67] - node _T_470 = eq(_T_469, UInt<8>("h03")) @[axi4_to_ahb.scala 168:74] - node _T_471 = or(_T_468, _T_470) @[axi4_to_ahb.scala 168:56] - node _T_472 = bits(_T_471, 0, 0) @[Bitwise.scala 72:15] - node _T_473 = mux(_T_472, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_474 = and(UInt<3>("h04"), _T_473) @[axi4_to_ahb.scala 168:15] - node _T_475 = or(_T_466, _T_474) @[axi4_to_ahb.scala 167:63] - node _T_476 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 169:37] - node _T_477 = eq(_T_476, UInt<8>("h0c0")) @[axi4_to_ahb.scala 169:44] - node _T_478 = bits(_T_477, 0, 0) @[Bitwise.scala 72:15] - node _T_479 = mux(_T_478, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_480 = and(UInt<3>("h06"), _T_479) @[axi4_to_ahb.scala 169:17] - node _T_481 = or(_T_475, _T_480) @[axi4_to_ahb.scala 168:96] - node _T_482 = bits(_T_449, 7, 0) @[axi4_to_ahb.scala 170:37] - node _T_483 = eq(_T_482, UInt<8>("h0c0")) @[axi4_to_ahb.scala 170:44] - node _T_484 = bits(_T_483, 0, 0) @[Bitwise.scala 72:15] - node _T_485 = mux(_T_484, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_486 = and(UInt<3>("h06"), _T_485) @[axi4_to_ahb.scala 170:17] - node _T_487 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 323:152] - node _T_488 = mux(_T_448, _T_481, _T_487) @[axi4_to_ahb.scala 323:43] - node _T_489 = cat(_T_444, _T_488) @[Cat.scala 29:58] - buf_addr_in <= _T_489 @[axi4_to_ahb.scala 323:15] - node _T_490 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 324:27] - buf_tag_in <= _T_490 @[axi4_to_ahb.scala 324:14] - node _T_491 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 325:32] - buf_byteen_in <= _T_491 @[axi4_to_ahb.scala 325:17] - node _T_492 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 326:33] - node _T_493 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 326:59] - node _T_494 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 326:80] - node _T_495 = mux(_T_492, _T_493, _T_494) @[axi4_to_ahb.scala 326:21] - buf_data_in <= _T_495 @[axi4_to_ahb.scala 326:15] - node _T_496 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 327:52] - node _T_497 = eq(_T_496, UInt<2>("h03")) @[axi4_to_ahb.scala 327:58] - node _T_498 = and(buf_aligned_in, _T_497) @[axi4_to_ahb.scala 327:38] - node _T_499 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 327:84] - node _T_500 = eq(_T_499, UInt<1>("h01")) @[axi4_to_ahb.scala 327:91] - node _T_501 = and(_T_498, _T_500) @[axi4_to_ahb.scala 327:71] - node _T_502 = bits(_T_501, 0, 0) @[axi4_to_ahb.scala 327:111] - node _T_503 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 327:142] - node _T_504 = bits(_T_503, 7, 0) @[axi4_to_ahb.scala 160:40] - node _T_505 = eq(_T_504, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:47] + node _T_492 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 323:33] + node _T_493 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 323:73] + node _T_494 = eq(_T_493, UInt<1>("h01")) @[axi4_to_ahb.scala 323:80] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 323:60] + node _T_496 = bits(_T_495, 0, 0) @[axi4_to_ahb.scala 323:100] + node _T_497 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 323:132] + node _T_498 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 166:50] + node _T_499 = eq(_T_498, UInt<8>("h0ff")) @[axi4_to_ahb.scala 166:57] + node _T_500 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 166:81] + node _T_501 = eq(_T_500, UInt<8>("h0f")) @[axi4_to_ahb.scala 166:88] + node _T_502 = or(_T_499, _T_501) @[axi4_to_ahb.scala 166:70] + node _T_503 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 166:117] + node _T_504 = eq(_T_503, UInt<8>("h03")) @[axi4_to_ahb.scala 166:124] + node _T_505 = or(_T_502, _T_504) @[axi4_to_ahb.scala 166:106] node _T_506 = bits(_T_505, 0, 0) @[Bitwise.scala 72:15] - node _T_507 = mux(_T_506, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_508 = and(UInt<2>("h03"), _T_507) @[axi4_to_ahb.scala 160:23] - node _T_509 = bits(_T_503, 7, 0) @[axi4_to_ahb.scala 161:35] - node _T_510 = eq(_T_509, UInt<8>("h0f0")) @[axi4_to_ahb.scala 161:42] - node _T_511 = bits(_T_503, 7, 0) @[axi4_to_ahb.scala 161:64] - node _T_512 = eq(_T_511, UInt<8>("h0f")) @[axi4_to_ahb.scala 161:71] - node _T_513 = or(_T_510, _T_512) @[axi4_to_ahb.scala 161:55] - node _T_514 = bits(_T_513, 0, 0) @[Bitwise.scala 72:15] - node _T_515 = mux(_T_514, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_516 = and(UInt<2>("h02"), _T_515) @[axi4_to_ahb.scala 161:16] - node _T_517 = or(_T_508, _T_516) @[axi4_to_ahb.scala 160:62] - node _T_518 = bits(_T_503, 7, 0) @[axi4_to_ahb.scala 162:40] - node _T_519 = eq(_T_518, UInt<8>("h0c0")) @[axi4_to_ahb.scala 162:47] - node _T_520 = bits(_T_503, 7, 0) @[axi4_to_ahb.scala 162:69] - node _T_521 = eq(_T_520, UInt<6>("h030")) @[axi4_to_ahb.scala 162:76] - node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 162:60] - node _T_523 = bits(_T_503, 7, 0) @[axi4_to_ahb.scala 162:98] - node _T_524 = eq(_T_523, UInt<8>("h0c")) @[axi4_to_ahb.scala 162:105] - node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 162:89] - node _T_526 = bits(_T_503, 7, 0) @[axi4_to_ahb.scala 162:132] - node _T_527 = eq(_T_526, UInt<8>("h03")) @[axi4_to_ahb.scala 162:139] - node _T_528 = or(_T_525, _T_527) @[axi4_to_ahb.scala 162:123] - node _T_529 = bits(_T_528, 0, 0) @[Bitwise.scala 72:15] - node _T_530 = mux(_T_529, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_531 = and(UInt<2>("h01"), _T_530) @[axi4_to_ahb.scala 162:21] - node _T_532 = or(_T_517, _T_531) @[axi4_to_ahb.scala 161:93] - node _T_533 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 327:161] - node _T_534 = mux(_T_502, _T_532, _T_533) @[axi4_to_ahb.scala 327:21] - buf_size_in <= _T_534 @[axi4_to_ahb.scala 327:15] - node _T_535 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 328:32] - node _T_536 = eq(_T_535, UInt<1>("h00")) @[axi4_to_ahb.scala 328:39] - node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 329:17] - node _T_538 = eq(_T_537, UInt<1>("h00")) @[axi4_to_ahb.scala 329:24] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 328:48] - node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 329:47] - node _T_541 = eq(_T_540, UInt<2>("h01")) @[axi4_to_ahb.scala 329:54] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 329:33] - node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 329:86] - node _T_544 = eq(_T_543, UInt<2>("h02")) @[axi4_to_ahb.scala 329:93] - node _T_545 = or(_T_542, _T_544) @[axi4_to_ahb.scala 329:72] - node _T_546 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 330:18] - node _T_547 = eq(_T_546, UInt<2>("h03")) @[axi4_to_ahb.scala 330:25] - node _T_548 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 330:55] - node _T_549 = eq(_T_548, UInt<2>("h03")) @[axi4_to_ahb.scala 330:62] - node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 330:90] - node _T_551 = eq(_T_550, UInt<4>("h0c")) @[axi4_to_ahb.scala 330:97] - node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 330:74] - node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 330:125] - node _T_554 = eq(_T_553, UInt<6>("h030")) @[axi4_to_ahb.scala 330:132] - node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 330:109] - node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 330:161] - node _T_557 = eq(_T_556, UInt<8>("h0c0")) @[axi4_to_ahb.scala 330:168] - node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 330:145] - node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 331:21] - node _T_560 = eq(_T_559, UInt<4>("h0f")) @[axi4_to_ahb.scala 331:28] - node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 330:181] - node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 331:56] - node _T_563 = eq(_T_562, UInt<8>("h0f0")) @[axi4_to_ahb.scala 331:63] - node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 331:40] - node _T_565 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 331:92] - node _T_566 = eq(_T_565, UInt<8>("h0ff")) @[axi4_to_ahb.scala 331:99] - node _T_567 = or(_T_564, _T_566) @[axi4_to_ahb.scala 331:76] - node _T_568 = and(_T_547, _T_567) @[axi4_to_ahb.scala 330:38] - node _T_569 = or(_T_545, _T_568) @[axi4_to_ahb.scala 329:106] - buf_aligned_in <= _T_569 @[axi4_to_ahb.scala 328:18] - node _T_570 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 333:39] - node _T_571 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 333:58] - node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 333:83] - node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] - node _T_574 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 333:104] - node _T_575 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 333:129] - node _T_576 = cat(_T_574, _T_575) @[Cat.scala 29:58] - node _T_577 = mux(_T_570, _T_573, _T_576) @[axi4_to_ahb.scala 333:22] - io.ahb_haddr <= _T_577 @[axi4_to_ahb.scala 333:16] - node _T_578 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 334:39] - node _T_579 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] - node _T_580 = mux(_T_579, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_581 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 334:90] - node _T_582 = and(_T_580, _T_581) @[axi4_to_ahb.scala 334:77] - node _T_583 = cat(UInt<1>("h00"), _T_582) @[Cat.scala 29:58] - node _T_584 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] - node _T_585 = mux(_T_584, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_586 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 334:144] - node _T_587 = and(_T_585, _T_586) @[axi4_to_ahb.scala 334:134] - node _T_588 = cat(UInt<1>("h00"), _T_587) @[Cat.scala 29:58] - node _T_589 = mux(_T_578, _T_583, _T_588) @[axi4_to_ahb.scala 334:22] - io.ahb_hsize <= _T_589 @[axi4_to_ahb.scala 334:16] + node _T_507 = mux(_T_506, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_508 = and(UInt<3>("h00"), _T_507) @[axi4_to_ahb.scala 166:29] + node _T_509 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 167:35] + node _T_510 = eq(_T_509, UInt<8>("h0c")) @[axi4_to_ahb.scala 167:42] + node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] + node _T_512 = mux(_T_511, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 167:15] + node _T_514 = or(_T_508, _T_513) @[axi4_to_ahb.scala 166:146] + node _T_515 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 168:36] + node _T_516 = eq(_T_515, UInt<8>("h0f0")) @[axi4_to_ahb.scala 168:43] + node _T_517 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 168:67] + node _T_518 = eq(_T_517, UInt<8>("h03")) @[axi4_to_ahb.scala 168:74] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 168:56] + node _T_520 = bits(_T_519, 0, 0) @[Bitwise.scala 72:15] + node _T_521 = mux(_T_520, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_522 = and(UInt<3>("h04"), _T_521) @[axi4_to_ahb.scala 168:15] + node _T_523 = or(_T_514, _T_522) @[axi4_to_ahb.scala 167:63] + node _T_524 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 169:37] + node _T_525 = eq(_T_524, UInt<8>("h0c0")) @[axi4_to_ahb.scala 169:44] + node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] + node _T_527 = mux(_T_526, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_528 = and(UInt<3>("h06"), _T_527) @[axi4_to_ahb.scala 169:17] + node _T_529 = or(_T_523, _T_528) @[axi4_to_ahb.scala 168:96] + node _T_530 = bits(_T_497, 7, 0) @[axi4_to_ahb.scala 170:37] + node _T_531 = eq(_T_530, UInt<8>("h0c0")) @[axi4_to_ahb.scala 170:44] + node _T_532 = bits(_T_531, 0, 0) @[Bitwise.scala 72:15] + node _T_533 = mux(_T_532, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_534 = and(UInt<3>("h06"), _T_533) @[axi4_to_ahb.scala 170:17] + node _T_535 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 323:152] + node _T_536 = mux(_T_496, _T_529, _T_535) @[axi4_to_ahb.scala 323:43] + node _T_537 = cat(_T_492, _T_536) @[Cat.scala 29:58] + buf_addr_in <= _T_537 @[axi4_to_ahb.scala 323:15] + node _T_538 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 324:27] + buf_tag_in <= _T_538 @[axi4_to_ahb.scala 324:14] + node _T_539 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 325:32] + buf_byteen_in <= _T_539 @[axi4_to_ahb.scala 325:17] + node _T_540 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 326:33] + node _T_541 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 326:59] + node _T_542 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 326:80] + node _T_543 = mux(_T_540, _T_541, _T_542) @[axi4_to_ahb.scala 326:21] + buf_data_in <= _T_543 @[axi4_to_ahb.scala 326:15] + node _T_544 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 327:52] + node _T_545 = eq(_T_544, UInt<2>("h03")) @[axi4_to_ahb.scala 327:58] + node _T_546 = and(buf_aligned_in, _T_545) @[axi4_to_ahb.scala 327:38] + node _T_547 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 327:84] + node _T_548 = eq(_T_547, UInt<1>("h01")) @[axi4_to_ahb.scala 327:91] + node _T_549 = and(_T_546, _T_548) @[axi4_to_ahb.scala 327:71] + node _T_550 = bits(_T_549, 0, 0) @[axi4_to_ahb.scala 327:111] + node _T_551 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 327:142] + node _T_552 = bits(_T_551, 7, 0) @[axi4_to_ahb.scala 160:40] + node _T_553 = eq(_T_552, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:47] + node _T_554 = bits(_T_553, 0, 0) @[Bitwise.scala 72:15] + node _T_555 = mux(_T_554, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_556 = and(UInt<2>("h03"), _T_555) @[axi4_to_ahb.scala 160:23] + node _T_557 = bits(_T_551, 7, 0) @[axi4_to_ahb.scala 161:35] + node _T_558 = eq(_T_557, UInt<8>("h0f0")) @[axi4_to_ahb.scala 161:42] + node _T_559 = bits(_T_551, 7, 0) @[axi4_to_ahb.scala 161:64] + node _T_560 = eq(_T_559, UInt<8>("h0f")) @[axi4_to_ahb.scala 161:71] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 161:55] + node _T_562 = bits(_T_561, 0, 0) @[Bitwise.scala 72:15] + node _T_563 = mux(_T_562, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_564 = and(UInt<2>("h02"), _T_563) @[axi4_to_ahb.scala 161:16] + node _T_565 = or(_T_556, _T_564) @[axi4_to_ahb.scala 160:62] + node _T_566 = bits(_T_551, 7, 0) @[axi4_to_ahb.scala 162:40] + node _T_567 = eq(_T_566, UInt<8>("h0c0")) @[axi4_to_ahb.scala 162:47] + node _T_568 = bits(_T_551, 7, 0) @[axi4_to_ahb.scala 162:69] + node _T_569 = eq(_T_568, UInt<6>("h030")) @[axi4_to_ahb.scala 162:76] + node _T_570 = or(_T_567, _T_569) @[axi4_to_ahb.scala 162:60] + node _T_571 = bits(_T_551, 7, 0) @[axi4_to_ahb.scala 162:98] + node _T_572 = eq(_T_571, UInt<8>("h0c")) @[axi4_to_ahb.scala 162:105] + node _T_573 = or(_T_570, _T_572) @[axi4_to_ahb.scala 162:89] + node _T_574 = bits(_T_551, 7, 0) @[axi4_to_ahb.scala 162:132] + node _T_575 = eq(_T_574, UInt<8>("h03")) @[axi4_to_ahb.scala 162:139] + node _T_576 = or(_T_573, _T_575) @[axi4_to_ahb.scala 162:123] + node _T_577 = bits(_T_576, 0, 0) @[Bitwise.scala 72:15] + node _T_578 = mux(_T_577, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_579 = and(UInt<2>("h01"), _T_578) @[axi4_to_ahb.scala 162:21] + node _T_580 = or(_T_565, _T_579) @[axi4_to_ahb.scala 161:93] + node _T_581 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 327:161] + node _T_582 = mux(_T_550, _T_580, _T_581) @[axi4_to_ahb.scala 327:21] + buf_size_in <= _T_582 @[axi4_to_ahb.scala 327:15] + node _T_583 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 328:32] + node _T_584 = eq(_T_583, UInt<1>("h00")) @[axi4_to_ahb.scala 328:39] + node _T_585 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 329:17] + node _T_586 = eq(_T_585, UInt<1>("h00")) @[axi4_to_ahb.scala 329:24] + node _T_587 = or(_T_584, _T_586) @[axi4_to_ahb.scala 328:48] + node _T_588 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 329:47] + node _T_589 = eq(_T_588, UInt<2>("h01")) @[axi4_to_ahb.scala 329:54] + node _T_590 = or(_T_587, _T_589) @[axi4_to_ahb.scala 329:33] + node _T_591 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 329:86] + node _T_592 = eq(_T_591, UInt<2>("h02")) @[axi4_to_ahb.scala 329:93] + node _T_593 = or(_T_590, _T_592) @[axi4_to_ahb.scala 329:72] + node _T_594 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 330:18] + node _T_595 = eq(_T_594, UInt<2>("h03")) @[axi4_to_ahb.scala 330:25] + node _T_596 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 330:55] + node _T_597 = eq(_T_596, UInt<2>("h03")) @[axi4_to_ahb.scala 330:62] + node _T_598 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 330:90] + node _T_599 = eq(_T_598, UInt<4>("h0c")) @[axi4_to_ahb.scala 330:97] + node _T_600 = or(_T_597, _T_599) @[axi4_to_ahb.scala 330:74] + node _T_601 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 330:125] + node _T_602 = eq(_T_601, UInt<6>("h030")) @[axi4_to_ahb.scala 330:132] + node _T_603 = or(_T_600, _T_602) @[axi4_to_ahb.scala 330:109] + node _T_604 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 330:161] + node _T_605 = eq(_T_604, UInt<8>("h0c0")) @[axi4_to_ahb.scala 330:168] + node _T_606 = or(_T_603, _T_605) @[axi4_to_ahb.scala 330:145] + node _T_607 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 331:21] + node _T_608 = eq(_T_607, UInt<4>("h0f")) @[axi4_to_ahb.scala 331:28] + node _T_609 = or(_T_606, _T_608) @[axi4_to_ahb.scala 330:181] + node _T_610 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 331:56] + node _T_611 = eq(_T_610, UInt<8>("h0f0")) @[axi4_to_ahb.scala 331:63] + node _T_612 = or(_T_609, _T_611) @[axi4_to_ahb.scala 331:40] + node _T_613 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 331:92] + node _T_614 = eq(_T_613, UInt<8>("h0ff")) @[axi4_to_ahb.scala 331:99] + node _T_615 = or(_T_612, _T_614) @[axi4_to_ahb.scala 331:76] + node _T_616 = and(_T_595, _T_615) @[axi4_to_ahb.scala 330:38] + node _T_617 = or(_T_593, _T_616) @[axi4_to_ahb.scala 329:106] + buf_aligned_in <= _T_617 @[axi4_to_ahb.scala 328:18] + node _T_618 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 333:39] + node _T_619 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 333:58] + node _T_620 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 333:83] + node _T_621 = cat(_T_619, _T_620) @[Cat.scala 29:58] + node _T_622 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 333:104] + node _T_623 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 333:129] + node _T_624 = cat(_T_622, _T_623) @[Cat.scala 29:58] + node _T_625 = mux(_T_618, _T_621, _T_624) @[axi4_to_ahb.scala 333:22] + io.ahb_haddr <= _T_625 @[axi4_to_ahb.scala 333:16] + node _T_626 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 334:39] + node _T_627 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] + node _T_628 = mux(_T_627, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_629 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 334:90] + node _T_630 = and(_T_628, _T_629) @[axi4_to_ahb.scala 334:77] + node _T_631 = cat(UInt<1>("h00"), _T_630) @[Cat.scala 29:58] + node _T_632 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] + node _T_633 = mux(_T_632, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_634 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 334:144] + node _T_635 = and(_T_633, _T_634) @[axi4_to_ahb.scala 334:134] + node _T_636 = cat(UInt<1>("h00"), _T_635) @[Cat.scala 29:58] + node _T_637 = mux(_T_626, _T_631, _T_636) @[axi4_to_ahb.scala 334:22] + io.ahb_hsize <= _T_637 @[axi4_to_ahb.scala 334:16] io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 336:17] io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 337:20] - node _T_590 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 338:47] - node _T_591 = not(_T_590) @[axi4_to_ahb.scala 338:33] - node _T_592 = cat(UInt<1>("h01"), _T_591) @[Cat.scala 29:58] - io.ahb_hprot <= _T_592 @[axi4_to_ahb.scala 338:16] - node _T_593 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 339:40] - node _T_594 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 339:55] - node _T_595 = eq(_T_594, UInt<1>("h01")) @[axi4_to_ahb.scala 339:62] - node _T_596 = mux(_T_593, _T_595, buf_write) @[axi4_to_ahb.scala 339:23] - io.ahb_hwrite <= _T_596 @[axi4_to_ahb.scala 339:17] - node _T_597 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 340:28] - io.ahb_hwdata <= _T_597 @[axi4_to_ahb.scala 340:17] + node _T_638 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 338:47] + node _T_639 = not(_T_638) @[axi4_to_ahb.scala 338:33] + node _T_640 = cat(UInt<1>("h01"), _T_639) @[Cat.scala 29:58] + io.ahb_hprot <= _T_640 @[axi4_to_ahb.scala 338:16] + node _T_641 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 339:40] + node _T_642 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 339:55] + node _T_643 = eq(_T_642, UInt<1>("h01")) @[axi4_to_ahb.scala 339:62] + node _T_644 = mux(_T_641, _T_643, buf_write) @[axi4_to_ahb.scala 339:23] + io.ahb_hwrite <= _T_644 @[axi4_to_ahb.scala 339:17] + node _T_645 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 340:28] + io.ahb_hwdata <= _T_645 @[axi4_to_ahb.scala 340:17] slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 342:15] - node _T_598 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 343:43] - node _T_599 = mux(_T_598, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 343:23] - node _T_600 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] - node _T_601 = mux(_T_600, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_602 = and(_T_601, UInt<2>("h02")) @[axi4_to_ahb.scala 343:88] - node _T_603 = cat(_T_599, _T_602) @[Cat.scala 29:58] - slave_opc <= _T_603 @[axi4_to_ahb.scala 343:13] - node _T_604 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 344:41] - node _T_605 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 344:66] - node _T_606 = cat(_T_605, _T_605) @[Cat.scala 29:58] - node _T_607 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 344:91] - node _T_608 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 344:110] - node _T_609 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 344:131] - node _T_610 = mux(_T_607, _T_608, _T_609) @[axi4_to_ahb.scala 344:79] - node _T_611 = mux(_T_604, _T_606, _T_610) @[axi4_to_ahb.scala 344:21] - slave_rdata <= _T_611 @[axi4_to_ahb.scala 344:15] - node _T_612 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 345:26] - slave_tag <= _T_612 @[axi4_to_ahb.scala 345:13] - node _T_613 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 347:33] - node _T_614 = neq(_T_613, UInt<1>("h00")) @[axi4_to_ahb.scala 347:40] - node _T_615 = and(_T_614, io.ahb_hready) @[axi4_to_ahb.scala 347:52] - node _T_616 = and(_T_615, io.ahb_hwrite) @[axi4_to_ahb.scala 347:68] - last_addr_en <= _T_616 @[axi4_to_ahb.scala 347:16] - node _T_617 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 349:30] - node _T_618 = and(_T_617, master_ready) @[axi4_to_ahb.scala 349:47] - wrbuf_en <= _T_618 @[axi4_to_ahb.scala 349:12] - node _T_619 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 350:34] - node _T_620 = and(_T_619, master_ready) @[axi4_to_ahb.scala 350:50] - wrbuf_data_en <= _T_620 @[axi4_to_ahb.scala 350:17] - node _T_621 = and(master_valid, master_ready) @[axi4_to_ahb.scala 351:34] - node _T_622 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 351:62] - node _T_623 = eq(_T_622, UInt<1>("h01")) @[axi4_to_ahb.scala 351:69] - node _T_624 = and(_T_621, _T_623) @[axi4_to_ahb.scala 351:49] - wrbuf_cmd_sent <= _T_624 @[axi4_to_ahb.scala 351:18] - node _T_625 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 352:33] - node _T_626 = and(wrbuf_cmd_sent, _T_625) @[axi4_to_ahb.scala 352:31] - wrbuf_rst <= _T_626 @[axi4_to_ahb.scala 352:13] - node _T_627 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 354:35] - node _T_628 = and(wrbuf_vld, _T_627) @[axi4_to_ahb.scala 354:33] - node _T_629 = eq(_T_628, UInt<1>("h00")) @[axi4_to_ahb.scala 354:21] - node _T_630 = and(_T_629, master_ready) @[axi4_to_ahb.scala 354:52] - io.axi_awready <= _T_630 @[axi4_to_ahb.scala 354:18] - node _T_631 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 355:39] - node _T_632 = and(wrbuf_data_vld, _T_631) @[axi4_to_ahb.scala 355:37] - node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 355:20] - node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 355:56] - io.axi_wready <= _T_634 @[axi4_to_ahb.scala 355:17] - node _T_635 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 356:33] - node _T_636 = eq(_T_635, UInt<1>("h00")) @[axi4_to_ahb.scala 356:21] - node _T_637 = and(_T_636, master_ready) @[axi4_to_ahb.scala 356:51] - io.axi_arready <= _T_637 @[axi4_to_ahb.scala 356:18] + node _T_646 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 343:43] + node _T_647 = mux(_T_646, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 343:23] + node _T_648 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] + node _T_649 = mux(_T_648, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_650 = and(_T_649, UInt<2>("h02")) @[axi4_to_ahb.scala 343:88] + node _T_651 = cat(_T_647, _T_650) @[Cat.scala 29:58] + slave_opc <= _T_651 @[axi4_to_ahb.scala 343:13] + node _T_652 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 344:41] + node _T_653 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 344:66] + node _T_654 = cat(_T_653, _T_653) @[Cat.scala 29:58] + node _T_655 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 344:91] + node _T_656 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 344:110] + node _T_657 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 344:131] + node _T_658 = mux(_T_655, _T_656, _T_657) @[axi4_to_ahb.scala 344:79] + node _T_659 = mux(_T_652, _T_654, _T_658) @[axi4_to_ahb.scala 344:21] + slave_rdata <= _T_659 @[axi4_to_ahb.scala 344:15] + node _T_660 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 345:26] + slave_tag <= _T_660 @[axi4_to_ahb.scala 345:13] + node _T_661 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 347:33] + node _T_662 = neq(_T_661, UInt<1>("h00")) @[axi4_to_ahb.scala 347:40] + node _T_663 = and(_T_662, io.ahb_hready) @[axi4_to_ahb.scala 347:52] + node _T_664 = and(_T_663, io.ahb_hwrite) @[axi4_to_ahb.scala 347:68] + last_addr_en <= _T_664 @[axi4_to_ahb.scala 347:16] + node _T_665 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 349:30] + node _T_666 = and(_T_665, master_ready) @[axi4_to_ahb.scala 349:47] + wrbuf_en <= _T_666 @[axi4_to_ahb.scala 349:12] + node _T_667 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 350:34] + node _T_668 = and(_T_667, master_ready) @[axi4_to_ahb.scala 350:50] + wrbuf_data_en <= _T_668 @[axi4_to_ahb.scala 350:17] + node _T_669 = and(master_valid, master_ready) @[axi4_to_ahb.scala 351:34] + node _T_670 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 351:62] + node _T_671 = eq(_T_670, UInt<1>("h01")) @[axi4_to_ahb.scala 351:69] + node _T_672 = and(_T_669, _T_671) @[axi4_to_ahb.scala 351:49] + wrbuf_cmd_sent <= _T_672 @[axi4_to_ahb.scala 351:18] + node _T_673 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 352:33] + node _T_674 = and(wrbuf_cmd_sent, _T_673) @[axi4_to_ahb.scala 352:31] + wrbuf_rst <= _T_674 @[axi4_to_ahb.scala 352:13] + node _T_675 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 354:35] + node _T_676 = and(wrbuf_vld, _T_675) @[axi4_to_ahb.scala 354:33] + node _T_677 = eq(_T_676, UInt<1>("h00")) @[axi4_to_ahb.scala 354:21] + node _T_678 = and(_T_677, master_ready) @[axi4_to_ahb.scala 354:52] + io.axi_awready <= _T_678 @[axi4_to_ahb.scala 354:18] + node _T_679 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 355:39] + node _T_680 = and(wrbuf_data_vld, _T_679) @[axi4_to_ahb.scala 355:37] + node _T_681 = eq(_T_680, UInt<1>("h00")) @[axi4_to_ahb.scala 355:20] + node _T_682 = and(_T_681, master_ready) @[axi4_to_ahb.scala 355:56] + io.axi_wready <= _T_682 @[axi4_to_ahb.scala 355:17] + node _T_683 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 356:33] + node _T_684 = eq(_T_683, UInt<1>("h00")) @[axi4_to_ahb.scala 356:21] + node _T_685 = and(_T_684, master_ready) @[axi4_to_ahb.scala 356:51] + io.axi_arready <= _T_685 @[axi4_to_ahb.scala 356:18] io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 357:16] - node _T_638 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 359:71] - node _T_639 = mux(_T_638, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 359:55] - node _T_640 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 359:91] - node _T_641 = and(_T_639, _T_640) @[axi4_to_ahb.scala 359:89] - reg _T_642 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 359:51] - _T_642 <= _T_641 @[axi4_to_ahb.scala 359:51] - wrbuf_vld <= _T_642 @[axi4_to_ahb.scala 359:21] - node _T_643 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 360:76] - node _T_644 = mux(_T_643, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 360:55] - node _T_645 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 360:102] - node _T_646 = and(_T_644, _T_645) @[axi4_to_ahb.scala 360:100] - reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 360:51] - _T_647 <= _T_646 @[axi4_to_ahb.scala 360:51] - wrbuf_data_vld <= _T_647 @[axi4_to_ahb.scala 360:21] - node _T_648 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 361:65] - node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 361:99] - reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_649 : @[Reg.scala 28:19] - _T_650 <= _T_648 @[Reg.scala 28:23] + node _T_686 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 359:71] + node _T_687 = mux(_T_686, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 359:55] + node _T_688 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 359:91] + node _T_689 = and(_T_687, _T_688) @[axi4_to_ahb.scala 359:89] + reg _T_690 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 359:51] + _T_690 <= _T_689 @[axi4_to_ahb.scala 359:51] + wrbuf_vld <= _T_690 @[axi4_to_ahb.scala 359:21] + node _T_691 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 360:76] + node _T_692 = mux(_T_691, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 360:55] + node _T_693 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 360:102] + node _T_694 = and(_T_692, _T_693) @[axi4_to_ahb.scala 360:100] + reg _T_695 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 360:51] + _T_695 <= _T_694 @[axi4_to_ahb.scala 360:51] + wrbuf_data_vld <= _T_695 @[axi4_to_ahb.scala 360:21] + node _T_696 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 361:65] + node _T_697 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 361:99] + reg _T_698 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_697 : @[Reg.scala 28:19] + _T_698 <= _T_696 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_tag <= _T_650 @[axi4_to_ahb.scala 361:21] - node _T_651 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 362:67] - node _T_652 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 362:95] - reg _T_653 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_652 : @[Reg.scala 28:19] - _T_653 <= _T_651 @[Reg.scala 28:23] + wrbuf_tag <= _T_698 @[axi4_to_ahb.scala 361:21] + node _T_699 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 362:67] + node _T_700 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 362:95] + reg _T_701 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_700 : @[Reg.scala 28:19] + _T_701 <= _T_699 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_size <= _T_653 @[axi4_to_ahb.scala 362:21] - node _T_654 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 363:55] + wrbuf_size <= _T_701 @[axi4_to_ahb.scala 362:21] + node _T_702 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 363:55] inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= bus_clk @[el2_lib.scala 510:18] - rvclkhdr_2.io.en <= _T_654 @[el2_lib.scala 511:17] + rvclkhdr_2.io.en <= _T_702 @[el2_lib.scala 511:17] rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_655 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_655 <= io.axi_awaddr @[el2_lib.scala 514:16] - wrbuf_addr <= _T_655 @[axi4_to_ahb.scala 363:21] - node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 364:59] + reg _T_703 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_703 <= io.axi_awaddr @[el2_lib.scala 514:16] + wrbuf_addr <= _T_703 @[axi4_to_ahb.scala 363:21] + node _T_704 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 364:59] inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= bus_clk @[el2_lib.scala 510:18] - rvclkhdr_3.io.en <= _T_656 @[el2_lib.scala 511:17] + rvclkhdr_3.io.en <= _T_704 @[el2_lib.scala 511:17] rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_657 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_657 <= io.axi_wdata @[el2_lib.scala 514:16] - wrbuf_data <= _T_657 @[axi4_to_ahb.scala 364:21] - node _T_658 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 365:66] - node _T_659 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 365:99] - reg _T_660 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_659 : @[Reg.scala 28:19] - _T_660 <= _T_658 @[Reg.scala 28:23] + reg _T_705 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_705 <= io.axi_wdata @[el2_lib.scala 514:16] + wrbuf_data <= _T_705 @[axi4_to_ahb.scala 364:21] + node _T_706 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 365:66] + node _T_707 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 365:99] + reg _T_708 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_707 : @[Reg.scala 28:19] + _T_708 <= _T_706 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_660 @[axi4_to_ahb.scala 365:21] - node _T_661 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 366:67] - node _T_662 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 366:100] - reg _T_663 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_662 : @[Reg.scala 28:19] - _T_663 <= _T_661 @[Reg.scala 28:23] + wrbuf_byteen <= _T_708 @[axi4_to_ahb.scala 365:21] + node _T_709 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 366:67] + node _T_710 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 366:100] + reg _T_711 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_710 : @[Reg.scala 28:19] + _T_711 <= _T_709 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - last_bus_addr <= _T_663 @[axi4_to_ahb.scala 366:21] - node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 367:89] - reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_664 : @[Reg.scala 28:19] - _T_665 <= buf_write_in @[Reg.scala 28:23] + last_bus_addr <= _T_711 @[axi4_to_ahb.scala 366:21] + node _T_712 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 367:89] + reg _T_713 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_712 : @[Reg.scala 28:19] + _T_713 <= buf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write <= _T_665 @[axi4_to_ahb.scala 367:21] - node _T_666 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 368:64] - node _T_667 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 368:99] - reg _T_668 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_667 : @[Reg.scala 28:19] - _T_668 <= _T_666 @[Reg.scala 28:23] + buf_write <= _T_713 @[axi4_to_ahb.scala 367:21] + node _T_714 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 368:64] + node _T_715 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 368:99] + reg _T_716 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_715 : @[Reg.scala 28:19] + _T_716 <= _T_714 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_tag <= _T_668 @[axi4_to_ahb.scala 368:21] - node _T_669 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 369:42] - node _T_670 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 369:61] - node _T_671 = bits(_T_670, 0, 0) @[axi4_to_ahb.scala 369:78] + buf_tag <= _T_716 @[axi4_to_ahb.scala 368:21] + node _T_717 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 369:42] + node _T_718 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 369:61] + node _T_719 = bits(_T_718, 0, 0) @[axi4_to_ahb.scala 369:78] inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_4.io.en <= _T_671 @[el2_lib.scala 511:17] + rvclkhdr_4.io.en <= _T_719 @[el2_lib.scala 511:17] rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_672 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_672 <= _T_669 @[el2_lib.scala 514:16] - buf_addr <= _T_672 @[axi4_to_ahb.scala 369:21] - node _T_673 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 370:65] - node _T_674 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 370:94] - reg _T_675 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_674 : @[Reg.scala 28:19] - _T_675 <= _T_673 @[Reg.scala 28:23] + reg _T_720 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_720 <= _T_717 @[el2_lib.scala 514:16] + buf_addr <= _T_720 @[axi4_to_ahb.scala 369:21] + node _T_721 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 370:65] + node _T_722 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 370:94] + reg _T_723 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_722 : @[Reg.scala 28:19] + _T_723 <= _T_721 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_size <= _T_675 @[axi4_to_ahb.scala 370:21] - node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 371:91] - reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_676 : @[Reg.scala 28:19] - _T_677 <= buf_aligned_in @[Reg.scala 28:23] + buf_size <= _T_723 @[axi4_to_ahb.scala 370:21] + node _T_724 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 371:91] + reg _T_725 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_724 : @[Reg.scala 28:19] + _T_725 <= buf_aligned_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_aligned <= _T_677 @[axi4_to_ahb.scala 371:21] - node _T_678 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 372:67] - node _T_679 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 372:96] - reg _T_680 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_679 : @[Reg.scala 28:19] - _T_680 <= _T_678 @[Reg.scala 28:23] + buf_aligned <= _T_725 @[axi4_to_ahb.scala 371:21] + node _T_726 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 372:67] + node _T_727 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 372:96] + reg _T_728 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_727 : @[Reg.scala 28:19] + _T_728 <= _T_726 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_byteen <= _T_680 @[axi4_to_ahb.scala 372:21] - node _T_681 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 373:42] - node _T_682 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 373:66] - node _T_683 = bits(_T_682, 0, 0) @[axi4_to_ahb.scala 373:89] + buf_byteen <= _T_728 @[axi4_to_ahb.scala 372:21] + node _T_729 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 373:42] + node _T_730 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 373:66] + node _T_731 = bits(_T_730, 0, 0) @[axi4_to_ahb.scala 373:89] inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23] rvclkhdr_5.clock <= clock rvclkhdr_5.reset <= reset rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_5.io.en <= _T_683 @[el2_lib.scala 511:17] + rvclkhdr_5.io.en <= _T_731 @[el2_lib.scala 511:17] rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_684 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_684 <= _T_681 @[el2_lib.scala 514:16] - buf_data <= _T_684 @[axi4_to_ahb.scala 373:21] - node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 374:89] - reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_685 : @[Reg.scala 28:19] - _T_686 <= buf_write @[Reg.scala 28:23] + reg _T_732 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_732 <= _T_729 @[el2_lib.scala 514:16] + buf_data <= _T_732 @[axi4_to_ahb.scala 373:21] + node _T_733 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 374:89] + reg _T_734 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_733 : @[Reg.scala 28:19] + _T_734 <= buf_write @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_write <= _T_686 @[axi4_to_ahb.scala 374:21] - node _T_687 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 375:61] - node _T_688 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 375:99] - reg _T_689 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_688 : @[Reg.scala 28:19] - _T_689 <= _T_687 @[Reg.scala 28:23] + slvbuf_write <= _T_734 @[axi4_to_ahb.scala 374:21] + node _T_735 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 375:61] + node _T_736 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 375:99] + reg _T_737 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_736 : @[Reg.scala 28:19] + _T_737 <= _T_735 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_tag <= _T_689 @[axi4_to_ahb.scala 375:21] - node _T_690 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 376:99] - reg _T_691 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_690 : @[Reg.scala 28:19] - _T_691 <= slvbuf_error_in @[Reg.scala 28:23] + slvbuf_tag <= _T_737 @[axi4_to_ahb.scala 375:21] + node _T_738 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 376:99] + reg _T_739 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_738 : @[Reg.scala 28:19] + _T_739 <= slvbuf_error_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_error <= _T_691 @[axi4_to_ahb.scala 376:21] - node _T_692 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 377:72] - node _T_693 = mux(_T_692, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 377:56] - node _T_694 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 377:92] - node _T_695 = and(_T_693, _T_694) @[axi4_to_ahb.scala 377:90] - reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 377:52] - _T_696 <= _T_695 @[axi4_to_ahb.scala 377:52] - cmd_doneQ <= _T_696 @[axi4_to_ahb.scala 377:21] - node _T_697 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 378:71] - node _T_698 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 378:110] - reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_698 : @[Reg.scala 28:19] - _T_699 <= _T_697 @[Reg.scala 28:23] + slvbuf_error <= _T_739 @[axi4_to_ahb.scala 376:21] + node _T_740 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 377:72] + node _T_741 = mux(_T_740, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 377:56] + node _T_742 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 377:92] + node _T_743 = and(_T_741, _T_742) @[axi4_to_ahb.scala 377:90] + reg _T_744 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 377:52] + _T_744 <= _T_743 @[axi4_to_ahb.scala 377:52] + cmd_doneQ <= _T_744 @[axi4_to_ahb.scala 377:21] + node _T_745 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 378:71] + node _T_746 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 378:110] + reg _T_747 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_746 : @[Reg.scala 28:19] + _T_747 <= _T_745 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_699 @[axi4_to_ahb.scala 378:21] - reg _T_700 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 379:52] - _T_700 <= io.ahb_hready @[axi4_to_ahb.scala 379:52] - ahb_hready_q <= _T_700 @[axi4_to_ahb.scala 379:21] - node _T_701 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 380:66] - reg _T_702 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 380:52] - _T_702 <= _T_701 @[axi4_to_ahb.scala 380:52] - ahb_htrans_q <= _T_702 @[axi4_to_ahb.scala 380:21] - reg _T_703 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 381:57] - _T_703 <= io.ahb_hwrite @[axi4_to_ahb.scala 381:57] - ahb_hwrite_q <= _T_703 @[axi4_to_ahb.scala 381:21] - reg _T_704 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 382:52] - _T_704 <= io.ahb_hresp @[axi4_to_ahb.scala 382:52] - ahb_hresp_q <= _T_704 @[axi4_to_ahb.scala 382:21] - node _T_705 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 383:71] - reg _T_706 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 383:57] - _T_706 <= _T_705 @[axi4_to_ahb.scala 383:57] - ahb_hrdata_q <= _T_706 @[axi4_to_ahb.scala 383:21] - node _T_707 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 385:43] - node _T_708 = or(_T_707, io.clk_override) @[axi4_to_ahb.scala 385:58] - node _T_709 = and(io.bus_clk_en, _T_708) @[axi4_to_ahb.scala 385:30] - buf_clken <= _T_709 @[axi4_to_ahb.scala 385:13] - node _T_710 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 386:69] - node _T_711 = and(io.ahb_hready, _T_710) @[axi4_to_ahb.scala 386:54] - node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 386:74] - node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 386:36] - ahbm_addr_clken <= _T_713 @[axi4_to_ahb.scala 386:19] - node _T_714 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 387:50] - node _T_715 = or(_T_714, io.clk_override) @[axi4_to_ahb.scala 387:60] - node _T_716 = and(io.bus_clk_en, _T_715) @[axi4_to_ahb.scala 387:36] - ahbm_data_clken <= _T_716 @[axi4_to_ahb.scala 387:19] + buf_cmd_byte_ptrQ <= _T_747 @[axi4_to_ahb.scala 378:21] + reg _T_748 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 379:52] + _T_748 <= io.ahb_hready @[axi4_to_ahb.scala 379:52] + ahb_hready_q <= _T_748 @[axi4_to_ahb.scala 379:21] + node _T_749 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 380:66] + reg _T_750 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 380:52] + _T_750 <= _T_749 @[axi4_to_ahb.scala 380:52] + ahb_htrans_q <= _T_750 @[axi4_to_ahb.scala 380:21] + reg _T_751 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 381:57] + _T_751 <= io.ahb_hwrite @[axi4_to_ahb.scala 381:57] + ahb_hwrite_q <= _T_751 @[axi4_to_ahb.scala 381:21] + reg _T_752 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 382:52] + _T_752 <= io.ahb_hresp @[axi4_to_ahb.scala 382:52] + ahb_hresp_q <= _T_752 @[axi4_to_ahb.scala 382:21] + node _T_753 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 383:71] + reg _T_754 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 383:57] + _T_754 <= _T_753 @[axi4_to_ahb.scala 383:57] + ahb_hrdata_q <= _T_754 @[axi4_to_ahb.scala 383:21] + node _T_755 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 385:43] + node _T_756 = or(_T_755, io.clk_override) @[axi4_to_ahb.scala 385:58] + node _T_757 = and(io.bus_clk_en, _T_756) @[axi4_to_ahb.scala 385:30] + buf_clken <= _T_757 @[axi4_to_ahb.scala 385:13] + node _T_758 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 386:69] + node _T_759 = and(io.ahb_hready, _T_758) @[axi4_to_ahb.scala 386:54] + node _T_760 = or(_T_759, io.clk_override) @[axi4_to_ahb.scala 386:74] + node _T_761 = and(io.bus_clk_en, _T_760) @[axi4_to_ahb.scala 386:36] + ahbm_addr_clken <= _T_761 @[axi4_to_ahb.scala 386:19] + node _T_762 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 387:50] + node _T_763 = or(_T_762, io.clk_override) @[axi4_to_ahb.scala 387:60] + node _T_764 = and(io.bus_clk_en, _T_763) @[axi4_to_ahb.scala 387:36] + ahbm_data_clken <= _T_764 @[axi4_to_ahb.scala 387:19] inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 483:22] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset diff --git a/axi4_to_ahb.v b/axi4_to_ahb.v index c6a2c368..ac8d413c 100644 --- a/axi4_to_ahb.v +++ b/axi4_to_ahb.v @@ -140,89 +140,89 @@ module axi4_to_ahb( reg wrbuf_data_vld; // @[axi4_to_ahb.scala 360:51] wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 178:27] wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 179:30] - wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] + wire _T_109 = 3'h1 == buf_state; // @[Conditional.scala 37:30] reg ahb_hready_q; // @[axi4_to_ahb.scala 379:52] reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 380:52] - wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 241:58] - wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 241:36] + wire _T_116 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 241:58] + wire _T_117 = ahb_hready_q & _T_116; // @[axi4_to_ahb.scala 241:36] wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 64:27 axi4_to_ahb.scala 392:17] reg ahb_hwrite_q; // @[axi4_to_ahb.scala 381:57] - wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 241:72] - wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 241:70] - wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] + wire _T_118 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 241:72] + wire _T_119 = _T_117 & _T_118; // @[axi4_to_ahb.scala 241:70] + wire _T_144 = 3'h6 == buf_state; // @[Conditional.scala 37:30] reg ahb_hresp_q; // @[axi4_to_ahb.scala 382:52] - wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 255:37] - wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] - wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30] - wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_189 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 287:33] - wire _T_192 = _T_189 & _T_108; // @[axi4_to_ahb.scala 287:48] - wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] - wire _GEN_15 = _T_281 & _T_192; // @[Conditional.scala 39:67] - wire _GEN_19 = _T_188 ? _T_192 : _GEN_15; // @[Conditional.scala 39:67] - wire _GEN_40 = _T_186 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67] - wire _GEN_59 = _T_175 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] - wire _GEN_79 = _T_136 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] - wire _GEN_95 = _T_101 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] + wire _T_164 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 255:37] + wire _T_183 = 3'h7 == buf_state; // @[Conditional.scala 37:30] + wire _T_194 = 3'h3 == buf_state; // @[Conditional.scala 37:30] + wire _T_196 = 3'h2 == buf_state; // @[Conditional.scala 37:30] + wire _T_197 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 287:33] + wire _T_200 = _T_197 & _T_116; // @[axi4_to_ahb.scala 287:48] + wire _T_305 = 3'h4 == buf_state; // @[Conditional.scala 37:30] + wire _GEN_15 = _T_305 & _T_200; // @[Conditional.scala 39:67] + wire _GEN_19 = _T_196 ? _T_200 : _GEN_15; // @[Conditional.scala 39:67] + wire _GEN_40 = _T_194 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_183 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] + wire _GEN_79 = _T_144 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] + wire _GEN_95 = _T_109 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] wire trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] reg cmd_doneQ; // @[axi4_to_ahb.scala 377:52] - wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 297:34] - wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 297:50] - wire _T_443 = 3'h5 == buf_state; // @[Conditional.scala 37:30] + wire _T_306 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 297:34] + wire _T_307 = _T_306 | ahb_hresp_q; // @[axi4_to_ahb.scala 297:50] + wire _T_491 = 3'h5 == buf_state; // @[Conditional.scala 37:30] wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 196:32] - wire _GEN_1 = _T_443 & slave_ready; // @[Conditional.scala 39:67] - wire _GEN_3 = _T_281 ? _T_283 : _GEN_1; // @[Conditional.scala 39:67] - wire _GEN_20 = _T_188 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] - wire _GEN_35 = _T_186 ? _T_156 : _GEN_20; // @[Conditional.scala 39:67] - wire _GEN_51 = _T_175 ? _T_111 : _GEN_35; // @[Conditional.scala 39:67] - wire _GEN_69 = _T_136 ? _T_156 : _GEN_51; // @[Conditional.scala 39:67] - wire _GEN_83 = _T_101 ? _T_111 : _GEN_69; // @[Conditional.scala 39:67] + wire _GEN_1 = _T_491 & slave_ready; // @[Conditional.scala 39:67] + wire _GEN_3 = _T_305 ? _T_307 : _GEN_1; // @[Conditional.scala 39:67] + wire _GEN_20 = _T_196 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] + wire _GEN_35 = _T_194 ? _T_164 : _GEN_20; // @[Conditional.scala 39:67] + wire _GEN_51 = _T_183 ? _T_119 : _GEN_35; // @[Conditional.scala 39:67] + wire _GEN_69 = _T_144 ? _T_164 : _GEN_51; // @[Conditional.scala 39:67] + wire _GEN_83 = _T_109 ? _T_119 : _GEN_69; // @[Conditional.scala 39:67] wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 181:20] wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 181:14] wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 226:41] - wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67] - wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] - wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] - wire _GEN_63 = _T_175 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] - wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] - wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] + wire _GEN_8 = _T_305 & _T_51; // @[Conditional.scala 39:67] + wire _GEN_29 = _T_196 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] + wire _GEN_46 = _T_194 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_63 = _T_183 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_144 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] + wire _GEN_97 = _T_109 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 227:26] - wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 240:61] - wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 240:41] - wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 240:26] - wire _T_124 = _T_106 == 3'h6; // @[axi4_to_ahb.scala 244:174] - wire _T_125 = _T_111 & _T_124; // @[axi4_to_ahb.scala 244:88] - wire _T_137 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 252:39] - wire _T_138 = ahb_hready_q & _T_137; // @[axi4_to_ahb.scala 252:37] - wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 252:70] - wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 252:55] - wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 252:53] - wire _T_287 = _T_283 & _T_137; // @[axi4_to_ahb.scala 298:66] - wire _T_288 = _T_287 & slave_ready; // @[axi4_to_ahb.scala 298:81] - wire _GEN_4 = _T_281 & _T_288; // @[Conditional.scala 39:67] - wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] - wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] - wire _GEN_62 = _T_175 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] - wire _GEN_66 = _T_136 ? _T_143 : _GEN_62; // @[Conditional.scala 39:67] - wire _GEN_86 = _T_101 ? _T_125 : _GEN_66; // @[Conditional.scala 39:67] + wire _T_111 = master_opc == 3'h0; // @[axi4_to_ahb.scala 240:61] + wire _T_112 = master_valid & _T_111; // @[axi4_to_ahb.scala 240:41] + wire [2:0] _T_114 = _T_112 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 240:26] + wire _T_132 = _T_114 == 3'h6; // @[axi4_to_ahb.scala 244:174] + wire _T_133 = _T_119 & _T_132; // @[axi4_to_ahb.scala 244:88] + wire _T_145 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 252:39] + wire _T_146 = ahb_hready_q & _T_145; // @[axi4_to_ahb.scala 252:37] + wire _T_149 = master_valid & _T_51; // @[axi4_to_ahb.scala 252:70] + wire _T_150 = ~_T_149; // @[axi4_to_ahb.scala 252:55] + wire _T_151 = _T_146 & _T_150; // @[axi4_to_ahb.scala 252:53] + wire _T_311 = _T_307 & _T_145; // @[axi4_to_ahb.scala 298:66] + wire _T_312 = _T_311 & slave_ready; // @[axi4_to_ahb.scala 298:81] + wire _GEN_4 = _T_305 & _T_312; // @[Conditional.scala 39:67] + wire _GEN_26 = _T_196 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] + wire _GEN_45 = _T_194 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_183 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_144 ? _T_151 : _GEN_62; // @[Conditional.scala 39:67] + wire _GEN_86 = _T_109 ? _T_133 : _GEN_66; // @[Conditional.scala 39:67] wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] - wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 254:82] - wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 254:97] - wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 254:67] - wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 254:26] - wire _T_289 = ~slave_ready; // @[axi4_to_ahb.scala 299:42] - wire _T_290 = ahb_hresp_q | _T_289; // @[axi4_to_ahb.scala 299:40] - wire [2:0] _T_296 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 299:119] - wire [2:0] _T_297 = _T_149 ? _T_296 : 3'h0; // @[axi4_to_ahb.scala 299:75] - wire [2:0] _T_298 = _T_290 ? 3'h5 : _T_297; // @[axi4_to_ahb.scala 299:26] - wire [2:0] _GEN_5 = _T_281 ? _T_298 : 3'h0; // @[Conditional.scala 39:67] - wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] - wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] - wire [2:0] _GEN_50 = _T_175 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67] - wire [2:0] _GEN_68 = _T_136 ? _T_155 : _GEN_50; // @[Conditional.scala 39:67] - wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] + wire _T_157 = master_valid & master_ready; // @[axi4_to_ahb.scala 254:82] + wire _T_160 = _T_157 & _T_111; // @[axi4_to_ahb.scala 254:97] + wire [2:0] _T_162 = _T_160 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 254:67] + wire [2:0] _T_163 = ahb_hresp_q ? 3'h7 : _T_162; // @[axi4_to_ahb.scala 254:26] + wire _T_313 = ~slave_ready; // @[axi4_to_ahb.scala 299:42] + wire _T_314 = ahb_hresp_q | _T_313; // @[axi4_to_ahb.scala 299:40] + wire [2:0] _T_320 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 299:119] + wire [2:0] _T_321 = _T_157 ? _T_320 : 3'h0; // @[axi4_to_ahb.scala 299:75] + wire [2:0] _T_322 = _T_314 ? 3'h5 : _T_321; // @[axi4_to_ahb.scala 299:26] + wire [2:0] _GEN_5 = _T_305 ? _T_322 : 3'h0; // @[Conditional.scala 39:67] + wire [2:0] _GEN_18 = _T_196 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] + wire [2:0] _GEN_34 = _T_194 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] + wire [2:0] _GEN_50 = _T_183 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67] + wire [2:0] _GEN_68 = _T_144 ? _T_163 : _GEN_50; // @[Conditional.scala 39:67] + wire [2:0] _GEN_82 = _T_109 ? _T_114 : _GEN_68; // @[Conditional.scala 39:67] wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] reg wrbuf_tag; // @[Reg.scala 27:20] reg [31:0] wrbuf_addr; // @[el2_lib.scala 514:16] @@ -231,267 +231,283 @@ module axi4_to_ahb( wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_arsize; // @[axi4_to_ahb.scala 183:21] reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] reg [63:0] wrbuf_data; // @[el2_lib.scala 514:16] - wire _T_158 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 259:39] - wire _T_361 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 308:55] - wire _T_362 = buf_state_en & _T_361; // @[axi4_to_ahb.scala 308:39] - wire _GEN_14 = _T_281 ? _T_362 : _T_443; // @[Conditional.scala 39:67] - wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] - wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] - wire _GEN_52 = _T_175 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] - wire _GEN_73 = _T_136 ? _T_158 : _GEN_52; // @[Conditional.scala 39:67] - wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] + wire _T_166 = buf_state_en & _T_145; // @[axi4_to_ahb.scala 259:39] + wire _T_393 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 308:55] + wire _T_394 = buf_state_en & _T_393; // @[axi4_to_ahb.scala 308:39] + wire _GEN_14 = _T_305 ? _T_394 : _T_491; // @[Conditional.scala 39:67] + wire _GEN_33 = _T_196 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] + wire _GEN_49 = _T_194 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] + wire _GEN_52 = _T_183 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_144 ? _T_166 : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_94 = _T_109 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] wire _T_25 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 188:32] wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 157:21 axi4_to_ahb.scala 390:12] reg slvbuf_write; // @[Reg.scala 27:20] - wire [1:0] _T_599 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 343:23] + wire [1:0] _T_647 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 343:23] reg slvbuf_error; // @[Reg.scala 27:20] - wire [1:0] _T_601 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_602 = _T_601 & 2'h2; // @[axi4_to_ahb.scala 343:88] - wire [3:0] slave_opc = {_T_599,_T_602}; // @[Cat.scala 29:58] + wire [1:0] _T_649 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_650 = _T_649 & 2'h2; // @[axi4_to_ahb.scala 343:88] + wire [3:0] slave_opc = {_T_647,_T_650}; // @[Cat.scala 29:58] wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 189:49] reg slvbuf_tag; // @[Reg.scala 27:20] wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 192:65] reg [31:0] last_bus_addr; // @[Reg.scala 27:20] - wire [63:0] _T_606 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] - wire _T_607 = buf_state == 3'h5; // @[axi4_to_ahb.scala 344:91] + wire [63:0] _T_654 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] + wire _T_655 = buf_state == 3'h5; // @[axi4_to_ahb.scala 344:91] reg [63:0] buf_data; // @[el2_lib.scala 514:16] wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 65:27 axi4_to_ahb.scala 393:17] reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 383:57] - wire [63:0] _T_610 = _T_607 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 344:79] + wire [63:0] _T_658 = _T_655 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 344:79] wire _T_44 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 199:56] wire _T_45 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 199:91] wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 199:74] wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 230:54] wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 230:38] - wire [2:0] _T_86 = wrbuf_byteen[0] ? 3'h0 : 3'h7; // @[Mux.scala 98:16] - wire [2:0] _T_87 = wrbuf_byteen[1] ? 3'h1 : _T_86; // @[Mux.scala 98:16] - wire [2:0] _T_88 = wrbuf_byteen[2] ? 3'h2 : _T_87; // @[Mux.scala 98:16] - wire [2:0] _T_89 = wrbuf_byteen[3] ? 3'h3 : _T_88; // @[Mux.scala 98:16] - wire [2:0] _T_90 = wrbuf_byteen[4] ? 3'h4 : _T_89; // @[Mux.scala 98:16] - wire [2:0] _T_91 = wrbuf_byteen[5] ? 3'h5 : _T_90; // @[Mux.scala 98:16] - wire [2:0] _T_92 = wrbuf_byteen[6] ? 3'h6 : _T_91; // @[Mux.scala 98:16] - wire [2:0] _T_93 = wrbuf_byteen[7] ? 3'h7 : _T_92; // @[Mux.scala 98:16] - wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 233:30] - wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 235:51] - wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 246:33] - wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 261:64] - wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 261:48] - wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 261:79] - wire _T_352 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 306:33] - wire _T_354 = _T_352 & _T_55; // @[axi4_to_ahb.scala 306:48] - wire _GEN_12 = _T_281 & _T_354; // @[Conditional.scala 39:67] - wire _GEN_32 = _T_188 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] - wire _GEN_48 = _T_186 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] - wire _GEN_65 = _T_175 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] - wire _GEN_75 = _T_136 ? _T_164 : _GEN_65; // @[Conditional.scala 39:67] - wire _GEN_88 = _T_101 ? _T_126 : _GEN_75; // @[Conditional.scala 39:67] + wire _T_65 = |wrbuf_byteen[0]; // @[axi4_to_ahb.scala 175:77] + wire _T_69 = |wrbuf_byteen[1]; // @[axi4_to_ahb.scala 175:77] + wire _T_73 = |wrbuf_byteen[2]; // @[axi4_to_ahb.scala 175:77] + wire _T_77 = |wrbuf_byteen[3]; // @[axi4_to_ahb.scala 175:77] + wire _T_81 = |wrbuf_byteen[4]; // @[axi4_to_ahb.scala 175:77] + wire _T_85 = |wrbuf_byteen[5]; // @[axi4_to_ahb.scala 175:77] + wire _T_89 = |wrbuf_byteen[6]; // @[axi4_to_ahb.scala 175:77] + wire _T_93 = |wrbuf_byteen[7]; // @[axi4_to_ahb.scala 175:77] + wire [2:0] _T_94 = _T_65 ? 3'h0 : 3'h7; // @[Mux.scala 98:16] + wire [2:0] _T_95 = _T_69 ? 3'h1 : _T_94; // @[Mux.scala 98:16] + wire [2:0] _T_96 = _T_73 ? 3'h2 : _T_95; // @[Mux.scala 98:16] + wire [2:0] _T_97 = _T_77 ? 3'h3 : _T_96; // @[Mux.scala 98:16] + wire [2:0] _T_98 = _T_81 ? 3'h4 : _T_97; // @[Mux.scala 98:16] + wire [2:0] _T_99 = _T_85 ? 3'h5 : _T_98; // @[Mux.scala 98:16] + wire [2:0] _T_100 = _T_89 ? 3'h6 : _T_99; // @[Mux.scala 98:16] + wire [2:0] _T_101 = _T_93 ? 3'h7 : _T_100; // @[Mux.scala 98:16] + wire [2:0] _T_103 = buf_write_in ? _T_101 : master_addr[2:0]; // @[axi4_to_ahb.scala 233:30] + wire _T_104 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 235:51] + wire _T_134 = master_ready & master_valid; // @[axi4_to_ahb.scala 246:33] + wire _T_170 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 261:64] + wire _T_171 = _T_134 & _T_170; // @[axi4_to_ahb.scala 261:48] + wire _T_172 = _T_171 & buf_state_en; // @[axi4_to_ahb.scala 261:79] + wire _T_384 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 306:33] + wire _T_386 = _T_384 & _T_55; // @[axi4_to_ahb.scala 306:48] + wire _GEN_12 = _T_305 & _T_386; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_196 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] + wire _GEN_48 = _T_194 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_65 = _T_183 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] + wire _GEN_75 = _T_144 ? _T_172 : _GEN_65; // @[Conditional.scala 39:67] + wire _GEN_88 = _T_109 ? _T_134 : _GEN_75; // @[Conditional.scala 39:67] wire bypass_en = _T_49 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] - wire [1:0] _T_99 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_100 = _T_99 & 2'h2; // @[axi4_to_ahb.scala 236:45] - wire _T_112 = ~master_valid; // @[axi4_to_ahb.scala 242:34] - wire _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 242:32] + wire [1:0] _T_107 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_108 = _T_107 & 2'h2; // @[axi4_to_ahb.scala 236:45] + wire _T_120 = ~master_valid; // @[axi4_to_ahb.scala 242:34] + wire _T_121 = buf_state_en & _T_120; // @[axi4_to_ahb.scala 242:32] reg [31:0] buf_addr; // @[el2_lib.scala 514:16] - wire [2:0] _T_130 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 247:30] - wire _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 248:44] - wire _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 248:58] - wire [1:0] _T_134 = _T_132 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_135 = 2'h2 & _T_134; // @[axi4_to_ahb.scala 248:32] - wire _T_169 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 263:59] - wire _T_170 = _T_169 & buf_state_en; // @[axi4_to_ahb.scala 263:74] - wire _T_171 = ~_T_170; // @[axi4_to_ahb.scala 263:43] - wire [1:0] _T_173 = _T_171 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_174 = 2'h2 & _T_173; // @[axi4_to_ahb.scala 263:32] - wire [1:0] _T_184 = _T_131 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_185 = 2'h2 & _T_184; // @[axi4_to_ahb.scala 273:37] + wire [2:0] _T_138 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 247:30] + wire _T_139 = ~buf_state_en; // @[axi4_to_ahb.scala 248:44] + wire _T_140 = _T_139 | bypass_en; // @[axi4_to_ahb.scala 248:58] + wire [1:0] _T_142 = _T_140 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_143 = 2'h2 & _T_142; // @[axi4_to_ahb.scala 248:32] + wire _T_177 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 263:59] + wire _T_178 = _T_177 & buf_state_en; // @[axi4_to_ahb.scala 263:74] + wire _T_179 = ~_T_178; // @[axi4_to_ahb.scala 263:43] + wire [1:0] _T_181 = _T_179 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_182 = 2'h2 & _T_181; // @[axi4_to_ahb.scala 263:32] + wire [1:0] _T_192 = _T_139 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_193 = 2'h2 & _T_192; // @[axi4_to_ahb.scala 273:37] reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] reg [7:0] buf_byteen; // @[Reg.scala 27:20] - wire [2:0] _T_197 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 174:52] - wire _T_200 = 3'h0 >= _T_197; // @[axi4_to_ahb.scala 175:62] - wire _T_201 = buf_byteen[0] & _T_200; // @[axi4_to_ahb.scala 175:48] - wire _T_203 = 3'h1 >= _T_197; // @[axi4_to_ahb.scala 175:62] - wire _T_204 = buf_byteen[1] & _T_203; // @[axi4_to_ahb.scala 175:48] - wire _T_206 = 3'h2 >= _T_197; // @[axi4_to_ahb.scala 175:62] - wire _T_207 = buf_byteen[2] & _T_206; // @[axi4_to_ahb.scala 175:48] - wire _T_209 = 3'h3 >= _T_197; // @[axi4_to_ahb.scala 175:62] - wire _T_210 = buf_byteen[3] & _T_209; // @[axi4_to_ahb.scala 175:48] - wire _T_212 = 3'h4 >= _T_197; // @[axi4_to_ahb.scala 175:62] - wire _T_213 = buf_byteen[4] & _T_212; // @[axi4_to_ahb.scala 175:48] - wire _T_215 = 3'h5 >= _T_197; // @[axi4_to_ahb.scala 175:62] - wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 175:48] - wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 175:62] - wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 175:48] - wire [2:0] _T_223 = _T_201 ? 3'h0 : 3'h7; // @[Mux.scala 98:16] - wire [2:0] _T_224 = _T_204 ? 3'h1 : _T_223; // @[Mux.scala 98:16] - wire [2:0] _T_225 = _T_207 ? 3'h2 : _T_224; // @[Mux.scala 98:16] - wire [2:0] _T_226 = _T_210 ? 3'h3 : _T_225; // @[Mux.scala 98:16] - wire [2:0] _T_227 = _T_213 ? 3'h4 : _T_226; // @[Mux.scala 98:16] - wire [2:0] _T_228 = _T_216 ? 3'h5 : _T_227; // @[Mux.scala 98:16] - wire [2:0] _T_229 = _T_219 ? 3'h6 : _T_228; // @[Mux.scala 98:16] - wire [2:0] _T_230 = buf_byteen[7] ? 3'h7 : _T_229; // @[Mux.scala 98:16] - wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 291:30] - wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 292:65] + wire [2:0] _T_205 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 174:52] + wire _T_208 = 3'h0 >= _T_205; // @[axi4_to_ahb.scala 175:62] + wire _T_209 = buf_byteen[0] & _T_208; // @[axi4_to_ahb.scala 175:48] + wire _T_210 = |_T_209; // @[axi4_to_ahb.scala 175:77] + wire _T_212 = 3'h1 >= _T_205; // @[axi4_to_ahb.scala 175:62] + wire _T_213 = buf_byteen[1] & _T_212; // @[axi4_to_ahb.scala 175:48] + wire _T_214 = |_T_213; // @[axi4_to_ahb.scala 175:77] + wire _T_216 = 3'h2 >= _T_205; // @[axi4_to_ahb.scala 175:62] + wire _T_217 = buf_byteen[2] & _T_216; // @[axi4_to_ahb.scala 175:48] + wire _T_218 = |_T_217; // @[axi4_to_ahb.scala 175:77] + wire _T_220 = 3'h3 >= _T_205; // @[axi4_to_ahb.scala 175:62] + wire _T_221 = buf_byteen[3] & _T_220; // @[axi4_to_ahb.scala 175:48] + wire _T_222 = |_T_221; // @[axi4_to_ahb.scala 175:77] + wire _T_224 = 3'h4 >= _T_205; // @[axi4_to_ahb.scala 175:62] + wire _T_225 = buf_byteen[4] & _T_224; // @[axi4_to_ahb.scala 175:48] + wire _T_226 = |_T_225; // @[axi4_to_ahb.scala 175:77] + wire _T_228 = 3'h5 >= _T_205; // @[axi4_to_ahb.scala 175:62] + wire _T_229 = buf_byteen[5] & _T_228; // @[axi4_to_ahb.scala 175:48] + wire _T_230 = |_T_229; // @[axi4_to_ahb.scala 175:77] + wire _T_232 = 3'h6 >= _T_205; // @[axi4_to_ahb.scala 175:62] + wire _T_233 = buf_byteen[6] & _T_232; // @[axi4_to_ahb.scala 175:48] + wire _T_234 = |_T_233; // @[axi4_to_ahb.scala 175:77] + wire _T_238 = |buf_byteen[7]; // @[axi4_to_ahb.scala 175:77] + wire [2:0] _T_239 = _T_210 ? 3'h0 : 3'h7; // @[Mux.scala 98:16] + wire [2:0] _T_240 = _T_214 ? 3'h1 : _T_239; // @[Mux.scala 98:16] + wire [2:0] _T_241 = _T_218 ? 3'h2 : _T_240; // @[Mux.scala 98:16] + wire [2:0] _T_242 = _T_222 ? 3'h3 : _T_241; // @[Mux.scala 98:16] + wire [2:0] _T_243 = _T_226 ? 3'h4 : _T_242; // @[Mux.scala 98:16] + wire [2:0] _T_244 = _T_230 ? 3'h5 : _T_243; // @[Mux.scala 98:16] + wire [2:0] _T_245 = _T_234 ? 3'h6 : _T_244; // @[Mux.scala 98:16] + wire [2:0] _T_246 = _T_238 ? 3'h7 : _T_245; // @[Mux.scala 98:16] + wire [2:0] _T_247 = trxn_done ? _T_246 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 291:30] + wire _T_248 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 292:65] reg buf_aligned; // @[Reg.scala 27:20] - wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 292:44] - wire [7:0] _T_271 = buf_byteen >> _T_230; // @[axi4_to_ahb.scala 292:92] - wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 292:163] - wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 292:79] - wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 292:29] - wire _T_349 = _T_232 | _T_273; // @[axi4_to_ahb.scala 305:123] - wire _T_350 = _T_109 & _T_349; // @[axi4_to_ahb.scala 305:87] - wire _T_351 = ahb_hresp_q | _T_350; // @[axi4_to_ahb.scala 305:32] - wire _GEN_11 = _T_281 & _T_351; // @[Conditional.scala 39:67] - wire _GEN_24 = _T_188 ? _T_275 : _GEN_11; // @[Conditional.scala 39:67] - wire _GEN_43 = _T_186 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] - wire _GEN_61 = _T_175 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67] - wire _GEN_74 = _T_136 ? _T_113 : _GEN_61; // @[Conditional.scala 39:67] - wire _GEN_84 = _T_101 ? _T_113 : _GEN_74; // @[Conditional.scala 39:67] + wire _T_249 = buf_aligned | _T_248; // @[axi4_to_ahb.scala 292:44] + wire [7:0] _T_295 = buf_byteen >> _T_246; // @[axi4_to_ahb.scala 292:92] + wire _T_297 = ~_T_295[0]; // @[axi4_to_ahb.scala 292:163] + wire _T_298 = _T_249 | _T_297; // @[axi4_to_ahb.scala 292:79] + wire _T_299 = trxn_done & _T_298; // @[axi4_to_ahb.scala 292:29] + wire _T_381 = _T_248 | _T_297; // @[axi4_to_ahb.scala 305:123] + wire _T_382 = _T_117 & _T_381; // @[axi4_to_ahb.scala 305:87] + wire _T_383 = ahb_hresp_q | _T_382; // @[axi4_to_ahb.scala 305:32] + wire _GEN_11 = _T_305 & _T_383; // @[Conditional.scala 39:67] + wire _GEN_24 = _T_196 ? _T_299 : _GEN_11; // @[Conditional.scala 39:67] + wire _GEN_43 = _T_194 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] + wire _GEN_61 = _T_183 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_144 ? _T_121 : _GEN_61; // @[Conditional.scala 39:67] + wire _GEN_84 = _T_109 ? _T_121 : _GEN_74; // @[Conditional.scala 39:67] wire cmd_done = _T_49 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] - wire _T_276 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 293:43] - wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 293:32] - wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 293:57] - wire _T_303 = _T_55 | _T_96; // @[axi4_to_ahb.scala 303:62] - wire _T_304 = buf_state_en & _T_303; // @[axi4_to_ahb.scala 303:33] - wire _T_357 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 307:57] - wire [1:0] _T_359 = _T_357 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_360 = _T_359 & 2'h2; // @[axi4_to_ahb.scala 307:71] - wire _T_367 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 310:40] - wire [2:0] _T_442 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 311:30] - wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67] - wire _GEN_7 = _T_281 ? buf_state_en : _T_443; // @[Conditional.scala 39:67] - wire _GEN_9 = _T_281 & _T_304; // @[Conditional.scala 39:67] - wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] - wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] - wire _GEN_64 = _T_175 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] - wire _GEN_67 = _T_136 ? _T_152 : _GEN_64; // @[Conditional.scala 39:67] - wire _GEN_87 = _T_101 ? master_ready : _GEN_67; // @[Conditional.scala 39:67] + wire _T_300 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 293:43] + wire _T_301 = ~_T_300; // @[axi4_to_ahb.scala 293:32] + wire [1:0] _T_303 = _T_301 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_304 = _T_303 & 2'h2; // @[axi4_to_ahb.scala 293:57] + wire _T_327 = _T_55 | _T_104; // @[axi4_to_ahb.scala 303:62] + wire _T_328 = buf_state_en & _T_327; // @[axi4_to_ahb.scala 303:33] + wire _T_389 = _T_301 | bypass_en; // @[axi4_to_ahb.scala 307:57] + wire [1:0] _T_391 = _T_389 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_392 = _T_391 & 2'h2; // @[axi4_to_ahb.scala 307:71] + wire _T_399 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 310:40] + wire [2:0] _T_490 = bypass_en ? _T_101 : _T_247; // @[axi4_to_ahb.scala 311:30] + wire _GEN_6 = _T_305 & ahb_hresp_q; // @[Conditional.scala 39:67] + wire _GEN_7 = _T_305 ? buf_state_en : _T_491; // @[Conditional.scala 39:67] + wire _GEN_9 = _T_305 & _T_328; // @[Conditional.scala 39:67] + wire _GEN_30 = _T_196 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] + wire _GEN_47 = _T_194 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_183 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] + wire _GEN_67 = _T_144 ? _T_160 : _GEN_64; // @[Conditional.scala 39:67] + wire _GEN_87 = _T_109 ? master_ready : _GEN_67; // @[Conditional.scala 39:67] wire buf_wr_en = _T_49 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58] - wire _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67] - wire [1:0] _GEN_13 = _T_281 ? _T_360 : 2'h0; // @[Conditional.scala 39:67] - wire _GEN_16 = _T_281 & _T_367; // @[Conditional.scala 39:67] - wire [2:0] _GEN_17 = _T_281 ? _T_442 : 3'h0; // @[Conditional.scala 39:67] - wire _GEN_21 = _T_188 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] - wire _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67] - wire [2:0] _GEN_23 = _T_188 ? _T_231 : _GEN_17; // @[Conditional.scala 39:67] - wire [1:0] _GEN_25 = _T_188 ? _T_280 : _GEN_13; // @[Conditional.scala 39:67] - wire _GEN_28 = _T_188 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] - wire _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] - wire _GEN_36 = _T_186 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67] - wire _GEN_38 = _T_186 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67] - wire _GEN_39 = _T_186 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] - wire _GEN_41 = _T_186 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] - wire [2:0] _GEN_42 = _T_186 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67] - wire [1:0] _GEN_44 = _T_186 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67] - wire _GEN_53 = _T_175 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] - wire [2:0] _GEN_54 = _T_175 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67] - wire [1:0] _GEN_55 = _T_175 ? _T_185 : _GEN_44; // @[Conditional.scala 39:67] - wire _GEN_56 = _T_175 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] - wire _GEN_58 = _T_175 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] - wire _GEN_60 = _T_175 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] - wire _GEN_70 = _T_136 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] - wire _GEN_72 = _T_136 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67] - wire [2:0] _GEN_76 = _T_136 ? _T_130 : _GEN_54; // @[Conditional.scala 39:67] - wire [1:0] _GEN_77 = _T_136 ? _T_174 : _GEN_55; // @[Conditional.scala 39:67] - wire _GEN_78 = _T_136 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67] - wire _GEN_80 = _T_136 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] - wire _GEN_85 = _T_101 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67] - wire [2:0] _GEN_89 = _T_101 ? _T_130 : _GEN_76; // @[Conditional.scala 39:67] - wire [1:0] _GEN_90 = _T_101 ? _T_135 : _GEN_77; // @[Conditional.scala 39:67] - wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] - wire _GEN_93 = _T_101 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] - wire _GEN_96 = _T_101 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] + wire _GEN_10 = _T_305 & buf_wr_en; // @[Conditional.scala 39:67] + wire [1:0] _GEN_13 = _T_305 ? _T_392 : 2'h0; // @[Conditional.scala 39:67] + wire _GEN_16 = _T_305 & _T_399; // @[Conditional.scala 39:67] + wire [2:0] _GEN_17 = _T_305 ? _T_490 : 3'h0; // @[Conditional.scala 39:67] + wire _GEN_21 = _T_196 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] + wire _GEN_22 = _T_196 & buf_state_en; // @[Conditional.scala 39:67] + wire [2:0] _GEN_23 = _T_196 ? _T_247 : _GEN_17; // @[Conditional.scala 39:67] + wire [1:0] _GEN_25 = _T_196 ? _T_304 : _GEN_13; // @[Conditional.scala 39:67] + wire _GEN_28 = _T_196 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] + wire _GEN_31 = _T_196 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] + wire _GEN_36 = _T_194 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_194 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67] + wire _GEN_39 = _T_194 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] + wire _GEN_41 = _T_194 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] + wire [2:0] _GEN_42 = _T_194 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67] + wire [1:0] _GEN_44 = _T_194 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_183 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] + wire [2:0] _GEN_54 = _T_183 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67] + wire [1:0] _GEN_55 = _T_183 ? _T_193 : _GEN_44; // @[Conditional.scala 39:67] + wire _GEN_56 = _T_183 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] + wire _GEN_58 = _T_183 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_183 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] + wire _GEN_70 = _T_144 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_72 = _T_144 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67] + wire [2:0] _GEN_76 = _T_144 ? _T_138 : _GEN_54; // @[Conditional.scala 39:67] + wire [1:0] _GEN_77 = _T_144 ? _T_182 : _GEN_55; // @[Conditional.scala 39:67] + wire _GEN_78 = _T_144 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_80 = _T_144 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_85 = _T_109 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67] + wire [2:0] _GEN_89 = _T_109 ? _T_138 : _GEN_76; // @[Conditional.scala 39:67] + wire [1:0] _GEN_90 = _T_109 ? _T_143 : _GEN_77; // @[Conditional.scala 39:67] + wire _GEN_91 = _T_109 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] + wire _GEN_93 = _T_109 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] + wire _GEN_96 = _T_109 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] wire buf_cmd_byte_ptr_en = _T_49 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58] - wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58] + wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_103 : _GEN_89; // @[Conditional.scala 40:58] wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] - wire _T_538 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 329:24] - wire _T_539 = _T_103 | _T_538; // @[axi4_to_ahb.scala 328:48] - wire _T_541 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 329:54] - wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 329:33] - wire _T_544 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 329:93] - wire _T_545 = _T_542 | _T_544; // @[axi4_to_ahb.scala 329:72] - wire _T_547 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 330:25] - wire _T_549 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 330:62] - wire _T_551 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 330:97] - wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 330:74] - wire _T_554 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 330:132] - wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 330:109] - wire _T_557 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 330:168] - wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 330:145] - wire _T_560 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 331:28] - wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 330:181] - wire _T_563 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 331:63] - wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 331:40] - wire _T_566 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 331:99] - wire _T_567 = _T_564 | _T_566; // @[axi4_to_ahb.scala 331:76] - wire _T_568 = _T_547 & _T_567; // @[axi4_to_ahb.scala 330:38] - wire buf_aligned_in = _T_545 | _T_568; // @[axi4_to_ahb.scala 329:106] - wire _T_447 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 323:60] - wire [2:0] _T_464 = _T_551 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_465 = 3'h2 & _T_464; // @[axi4_to_ahb.scala 167:15] - wire _T_471 = _T_563 | _T_549; // @[axi4_to_ahb.scala 168:56] - wire [2:0] _T_473 = _T_471 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_474 = 3'h4 & _T_473; // @[axi4_to_ahb.scala 168:15] - wire [2:0] _T_475 = _T_465 | _T_474; // @[axi4_to_ahb.scala 167:63] - wire [2:0] _T_479 = _T_557 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_480 = 3'h6 & _T_479; // @[axi4_to_ahb.scala 169:17] - wire [2:0] _T_481 = _T_475 | _T_480; // @[axi4_to_ahb.scala 168:96] - wire [2:0] _T_488 = _T_447 ? _T_481 : master_addr[2:0]; // @[axi4_to_ahb.scala 323:43] - wire _T_492 = buf_state == 3'h3; // @[axi4_to_ahb.scala 326:33] - wire _T_498 = buf_aligned_in & _T_547; // @[axi4_to_ahb.scala 327:38] - wire _T_501 = _T_498 & _T_51; // @[axi4_to_ahb.scala 327:71] - wire [1:0] _T_507 = _T_566 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire _T_513 = _T_563 | _T_560; // @[axi4_to_ahb.scala 161:55] - wire [1:0] _T_515 = _T_513 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_516 = 2'h2 & _T_515; // @[axi4_to_ahb.scala 161:16] - wire [1:0] _T_517 = _T_507 | _T_516; // @[axi4_to_ahb.scala 160:62] - wire _T_522 = _T_557 | _T_554; // @[axi4_to_ahb.scala 162:60] - wire _T_525 = _T_522 | _T_551; // @[axi4_to_ahb.scala 162:89] - wire _T_528 = _T_525 | _T_549; // @[axi4_to_ahb.scala 162:123] - wire [1:0] _T_530 = _T_528 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_531 = 2'h1 & _T_530; // @[axi4_to_ahb.scala 162:21] - wire [1:0] _T_532 = _T_517 | _T_531; // @[axi4_to_ahb.scala 161:93] - wire [1:0] _T_534 = _T_501 ? _T_532 : master_size[1:0]; // @[axi4_to_ahb.scala 327:21] - wire [31:0] _T_573 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [31:0] _T_576 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [1:0] _T_580 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [2:0] buf_size_in = {{1'd0}, _T_534}; // @[axi4_to_ahb.scala 327:15] - wire [1:0] _T_582 = _T_580 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 334:77] - wire [2:0] _T_583 = {1'h0,_T_582}; // @[Cat.scala 29:58] - wire [1:0] _T_585 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_586 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 329:24] + wire _T_587 = _T_111 | _T_586; // @[axi4_to_ahb.scala 328:48] + wire _T_589 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 329:54] + wire _T_590 = _T_587 | _T_589; // @[axi4_to_ahb.scala 329:33] + wire _T_592 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 329:93] + wire _T_593 = _T_590 | _T_592; // @[axi4_to_ahb.scala 329:72] + wire _T_595 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 330:25] + wire _T_597 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 330:62] + wire _T_599 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 330:97] + wire _T_600 = _T_597 | _T_599; // @[axi4_to_ahb.scala 330:74] + wire _T_602 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 330:132] + wire _T_603 = _T_600 | _T_602; // @[axi4_to_ahb.scala 330:109] + wire _T_605 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 330:168] + wire _T_606 = _T_603 | _T_605; // @[axi4_to_ahb.scala 330:145] + wire _T_608 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 331:28] + wire _T_609 = _T_606 | _T_608; // @[axi4_to_ahb.scala 330:181] + wire _T_611 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 331:63] + wire _T_612 = _T_609 | _T_611; // @[axi4_to_ahb.scala 331:40] + wire _T_614 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 331:99] + wire _T_615 = _T_612 | _T_614; // @[axi4_to_ahb.scala 331:76] + wire _T_616 = _T_595 & _T_615; // @[axi4_to_ahb.scala 330:38] + wire buf_aligned_in = _T_593 | _T_616; // @[axi4_to_ahb.scala 329:106] + wire _T_495 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 323:60] + wire [2:0] _T_512 = _T_599 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_513 = 3'h2 & _T_512; // @[axi4_to_ahb.scala 167:15] + wire _T_519 = _T_611 | _T_597; // @[axi4_to_ahb.scala 168:56] + wire [2:0] _T_521 = _T_519 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_522 = 3'h4 & _T_521; // @[axi4_to_ahb.scala 168:15] + wire [2:0] _T_523 = _T_513 | _T_522; // @[axi4_to_ahb.scala 167:63] + wire [2:0] _T_527 = _T_605 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_528 = 3'h6 & _T_527; // @[axi4_to_ahb.scala 169:17] + wire [2:0] _T_529 = _T_523 | _T_528; // @[axi4_to_ahb.scala 168:96] + wire [2:0] _T_536 = _T_495 ? _T_529 : master_addr[2:0]; // @[axi4_to_ahb.scala 323:43] + wire _T_540 = buf_state == 3'h3; // @[axi4_to_ahb.scala 326:33] + wire _T_546 = buf_aligned_in & _T_595; // @[axi4_to_ahb.scala 327:38] + wire _T_549 = _T_546 & _T_51; // @[axi4_to_ahb.scala 327:71] + wire [1:0] _T_555 = _T_614 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_561 = _T_611 | _T_608; // @[axi4_to_ahb.scala 161:55] + wire [1:0] _T_563 = _T_561 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_564 = 2'h2 & _T_563; // @[axi4_to_ahb.scala 161:16] + wire [1:0] _T_565 = _T_555 | _T_564; // @[axi4_to_ahb.scala 160:62] + wire _T_570 = _T_605 | _T_602; // @[axi4_to_ahb.scala 162:60] + wire _T_573 = _T_570 | _T_599; // @[axi4_to_ahb.scala 162:89] + wire _T_576 = _T_573 | _T_597; // @[axi4_to_ahb.scala 162:123] + wire [1:0] _T_578 = _T_576 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_579 = 2'h1 & _T_578; // @[axi4_to_ahb.scala 162:21] + wire [1:0] _T_580 = _T_565 | _T_579; // @[axi4_to_ahb.scala 161:93] + wire [1:0] _T_582 = _T_549 ? _T_580 : master_size[1:0]; // @[axi4_to_ahb.scala 327:21] + wire [31:0] _T_621 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [31:0] _T_624 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [1:0] _T_628 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [2:0] buf_size_in = {{1'd0}, _T_582}; // @[axi4_to_ahb.scala 327:15] + wire [1:0] _T_630 = _T_628 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 334:77] + wire [2:0] _T_631 = {1'h0,_T_630}; // @[Cat.scala 29:58] + wire [1:0] _T_633 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] reg [1:0] buf_size; // @[Reg.scala 27:20] - wire [1:0] _T_587 = _T_585 & buf_size; // @[axi4_to_ahb.scala 334:134] - wire [2:0] _T_588 = {1'h0,_T_587}; // @[Cat.scala 29:58] - wire _T_591 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 338:33] - wire [1:0] _T_592 = {1'h1,_T_591}; // @[Cat.scala 29:58] + wire [1:0] _T_635 = _T_633 & buf_size; // @[axi4_to_ahb.scala 334:134] + wire [2:0] _T_636 = {1'h0,_T_635}; // @[Cat.scala 29:58] + wire _T_639 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 338:33] + wire [1:0] _T_640 = {1'h1,_T_639}; // @[Cat.scala 29:58] reg buf_write; // @[Reg.scala 27:20] - wire _T_614 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 347:40] - wire _T_615 = _T_614 & io_ahb_hready; // @[axi4_to_ahb.scala 347:52] - wire last_addr_en = _T_615 & io_ahb_hwrite; // @[axi4_to_ahb.scala 347:68] + wire _T_662 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 347:40] + wire _T_663 = _T_662 & io_ahb_hready; // @[axi4_to_ahb.scala 347:52] + wire last_addr_en = _T_663 & io_ahb_hwrite; // @[axi4_to_ahb.scala 347:68] wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 349:47] wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 350:50] - wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 351:49] - wire _T_625 = ~wrbuf_en; // @[axi4_to_ahb.scala 352:33] - wire wrbuf_rst = wrbuf_cmd_sent & _T_625; // @[axi4_to_ahb.scala 352:31] - wire _T_627 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 354:35] - wire _T_628 = wrbuf_vld & _T_627; // @[axi4_to_ahb.scala 354:33] - wire _T_629 = ~_T_628; // @[axi4_to_ahb.scala 354:21] - wire _T_632 = wrbuf_data_vld & _T_627; // @[axi4_to_ahb.scala 355:37] - wire _T_633 = ~_T_632; // @[axi4_to_ahb.scala 355:20] - wire _T_636 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 356:21] - wire _T_639 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 359:55] - wire _T_640 = ~wrbuf_rst; // @[axi4_to_ahb.scala 359:91] - wire _T_644 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 360:55] + wire wrbuf_cmd_sent = _T_157 & _T_51; // @[axi4_to_ahb.scala 351:49] + wire _T_673 = ~wrbuf_en; // @[axi4_to_ahb.scala 352:33] + wire wrbuf_rst = wrbuf_cmd_sent & _T_673; // @[axi4_to_ahb.scala 352:31] + wire _T_675 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 354:35] + wire _T_676 = wrbuf_vld & _T_675; // @[axi4_to_ahb.scala 354:33] + wire _T_677 = ~_T_676; // @[axi4_to_ahb.scala 354:21] + wire _T_680 = wrbuf_data_vld & _T_675; // @[axi4_to_ahb.scala 355:37] + wire _T_681 = ~_T_680; // @[axi4_to_ahb.scala 355:20] + wire _T_684 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 356:21] + wire _T_687 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 359:55] + wire _T_688 = ~wrbuf_rst; // @[axi4_to_ahb.scala 359:91] + wire _T_692 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 360:55] reg buf_tag; // @[Reg.scala 27:20] - wire _T_694 = ~slave_valid_pre; // @[axi4_to_ahb.scala 377:92] - wire _T_707 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 385:43] - wire _T_708 = _T_707 | io_clk_override; // @[axi4_to_ahb.scala 385:58] - wire _T_711 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 386:54] - wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 386:74] - wire _T_714 = buf_state != 3'h0; // @[axi4_to_ahb.scala 387:50] - wire _T_715 = _T_714 | io_clk_override; // @[axi4_to_ahb.scala 387:60] + wire _T_742 = ~slave_valid_pre; // @[axi4_to_ahb.scala 377:92] + wire _T_755 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 385:43] + wire _T_756 = _T_755 | io_clk_override; // @[axi4_to_ahb.scala 385:58] + wire _T_759 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 386:54] + wire _T_760 = _T_759 | io_clk_override; // @[axi4_to_ahb.scala 386:74] + wire _T_762 = buf_state != 3'h0; // @[axi4_to_ahb.scala 387:50] + wire _T_763 = _T_762 | io_clk_override; // @[axi4_to_ahb.scala 387:60] rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -552,23 +568,23 @@ module axi4_to_ahb( .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - assign io_axi_awready = _T_629 & master_ready; // @[axi4_to_ahb.scala 354:18] - assign io_axi_wready = _T_633 & master_ready; // @[axi4_to_ahb.scala 355:17] + assign io_axi_awready = _T_677 & master_ready; // @[axi4_to_ahb.scala 354:18] + assign io_axi_wready = _T_681 & master_ready; // @[axi4_to_ahb.scala 355:17] assign io_axi_bvalid = _T_25 & slave_opc[3]; // @[axi4_to_ahb.scala 188:17] assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 189:16] assign io_axi_bid = slvbuf_tag; // @[axi4_to_ahb.scala 190:14] - assign io_axi_arready = _T_636 & master_ready; // @[axi4_to_ahb.scala 356:18] + assign io_axi_arready = _T_684 & master_ready; // @[axi4_to_ahb.scala 356:18] assign io_axi_rvalid = _T_25 & _T_35; // @[axi4_to_ahb.scala 192:17] assign io_axi_rid = slvbuf_tag; // @[axi4_to_ahb.scala 194:14] - assign io_axi_rdata = slvbuf_error ? _T_606 : _T_610; // @[axi4_to_ahb.scala 195:16] + assign io_axi_rdata = slvbuf_error ? _T_654 : _T_658; // @[axi4_to_ahb.scala 195:16] assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 193:16] assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 357:16] - assign io_ahb_haddr = bypass_en ? _T_573 : _T_576; // @[axi4_to_ahb.scala 333:16] + assign io_ahb_haddr = bypass_en ? _T_621 : _T_624; // @[axi4_to_ahb.scala 333:16] assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 336:17] assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 337:20] - assign io_ahb_hprot = {{2'd0}, _T_592}; // @[axi4_to_ahb.scala 338:16] - assign io_ahb_hsize = bypass_en ? _T_583 : _T_588; // @[axi4_to_ahb.scala 334:16] - assign io_ahb_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 205:17 axi4_to_ahb.scala 236:21 axi4_to_ahb.scala 248:21 axi4_to_ahb.scala 263:21 axi4_to_ahb.scala 273:21 axi4_to_ahb.scala 293:21 axi4_to_ahb.scala 307:21] + assign io_ahb_hprot = {{2'd0}, _T_640}; // @[axi4_to_ahb.scala 338:16] + assign io_ahb_hsize = bypass_en ? _T_631 : _T_636; // @[axi4_to_ahb.scala 334:16] + assign io_ahb_htrans = _T_49 ? _T_108 : _GEN_90; // @[axi4_to_ahb.scala 205:17 axi4_to_ahb.scala 236:21 axi4_to_ahb.scala 248:21 axi4_to_ahb.scala 263:21 axi4_to_ahb.scala 273:21 axi4_to_ahb.scala 293:21 axi4_to_ahb.scala 307:21] assign io_ahb_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 339:17] assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 340:17] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] @@ -590,16 +606,16 @@ module axi4_to_ahb( assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[el2_lib.scala 511:17] assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_6_io_en = io_bus_clk_en & _T_708; // @[el2_lib.scala 485:16] + assign rvclkhdr_6_io_en = io_bus_clk_en & _T_756; // @[el2_lib.scala 485:16] assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 484:17] assign rvclkhdr_7_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16] assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_8_io_en = io_bus_clk_en & _T_712; // @[el2_lib.scala 485:16] + assign rvclkhdr_8_io_en = io_bus_clk_en & _T_760; // @[el2_lib.scala 485:16] assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_9_io_en = io_bus_clk_en & _T_715; // @[el2_lib.scala 485:16] + assign rvclkhdr_9_io_en = io_bus_clk_en & _T_763; // @[el2_lib.scala 485:16] assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE @@ -783,30 +799,30 @@ end // initial end else begin buf_state <= 3'h1; end - end else if (_T_101) begin - if (_T_104) begin + end else if (_T_109) begin + if (_T_112) begin buf_state <= 3'h6; end else begin buf_state <= 3'h3; end - end else if (_T_136) begin + end else if (_T_144) begin if (ahb_hresp_q) begin buf_state <= 3'h7; - end else if (_T_152) begin + end else if (_T_160) begin buf_state <= 3'h6; end else begin buf_state <= 3'h3; end - end else if (_T_175) begin + end else if (_T_183) begin buf_state <= 3'h3; - end else if (_T_186) begin + end else if (_T_194) begin buf_state <= 3'h5; - end else if (_T_188) begin + end else if (_T_196) begin buf_state <= 3'h4; - end else if (_T_281) begin - if (_T_290) begin + end else if (_T_305) begin + if (_T_314) begin buf_state <= 3'h5; - end else if (_T_149) begin + end else if (_T_157) begin if (_T_51) begin buf_state <= 3'h2; end else begin @@ -824,14 +840,14 @@ end // initial if (reset) begin wrbuf_vld <= 1'h0; end else begin - wrbuf_vld <= _T_639 & _T_640; + wrbuf_vld <= _T_687 & _T_688; end end always @(posedge bus_clk or posedge reset) begin if (reset) begin wrbuf_data_vld <= 1'h0; end else begin - wrbuf_data_vld <= _T_644 & _T_640; + wrbuf_data_vld <= _T_692 & _T_688; end end always @(posedge ahbm_clk or posedge reset) begin @@ -866,7 +882,7 @@ end // initial if (reset) begin cmd_doneQ <= 1'h0; end else begin - cmd_doneQ <= _T_276 & _T_694; + cmd_doneQ <= _T_300 & _T_742; end end always @(posedge bus_clk or posedge reset) begin @@ -917,15 +933,15 @@ end // initial end else if (slvbuf_error_en) begin if (_T_49) begin slvbuf_error <= 1'h0; - end else if (_T_101) begin + end else if (_T_109) begin slvbuf_error <= 1'h0; - end else if (_T_136) begin + end else if (_T_144) begin slvbuf_error <= ahb_hresp_q; - end else if (_T_175) begin + end else if (_T_183) begin slvbuf_error <= 1'h0; - end else if (_T_186) begin + end else if (_T_194) begin slvbuf_error <= ahb_hresp_q; - end else if (_T_188) begin + end else if (_T_196) begin slvbuf_error <= 1'h0; end else begin slvbuf_error <= _GEN_6; @@ -949,7 +965,7 @@ end // initial always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin buf_data <= 64'h0; - end else if (_T_492) begin + end else if (_T_540) begin buf_data <= ahb_hrdata_q; end else begin buf_data <= wrbuf_data; @@ -966,7 +982,7 @@ end // initial if (reset) begin buf_addr <= 32'h0; end else begin - buf_addr <= {master_addr[31:3],_T_488}; + buf_addr <= {master_addr[31:3],_T_536}; end end always @(posedge ahbm_clk or posedge reset) begin @@ -975,21 +991,21 @@ end // initial end else if (buf_cmd_byte_ptr_en) begin if (_T_49) begin if (buf_write_in) begin - if (wrbuf_byteen[7]) begin + if (_T_93) begin buf_cmd_byte_ptrQ <= 3'h7; - end else if (wrbuf_byteen[6]) begin + end else if (_T_89) begin buf_cmd_byte_ptrQ <= 3'h6; - end else if (wrbuf_byteen[5]) begin + end else if (_T_85) begin buf_cmd_byte_ptrQ <= 3'h5; - end else if (wrbuf_byteen[4]) begin + end else if (_T_81) begin buf_cmd_byte_ptrQ <= 3'h4; - end else if (wrbuf_byteen[3]) begin + end else if (_T_77) begin buf_cmd_byte_ptrQ <= 3'h3; - end else if (wrbuf_byteen[2]) begin + end else if (_T_73) begin buf_cmd_byte_ptrQ <= 3'h2; - end else if (wrbuf_byteen[1]) begin + end else if (_T_69) begin buf_cmd_byte_ptrQ <= 3'h1; - end else if (wrbuf_byteen[0]) begin + end else if (_T_65) begin buf_cmd_byte_ptrQ <= 3'h0; end else begin buf_cmd_byte_ptrQ <= 3'h7; @@ -997,81 +1013,81 @@ end // initial end else begin buf_cmd_byte_ptrQ <= master_addr[2:0]; end - end else if (_T_101) begin + end else if (_T_109) begin if (bypass_en) begin buf_cmd_byte_ptrQ <= master_addr[2:0]; end else begin buf_cmd_byte_ptrQ <= buf_addr[2:0]; end - end else if (_T_136) begin + end else if (_T_144) begin if (bypass_en) begin buf_cmd_byte_ptrQ <= master_addr[2:0]; end else begin buf_cmd_byte_ptrQ <= buf_addr[2:0]; end - end else if (_T_175) begin + end else if (_T_183) begin buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end else if (_T_186) begin + end else if (_T_194) begin buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_188) begin + end else if (_T_196) begin if (trxn_done) begin - if (buf_byteen[7]) begin + if (_T_238) begin buf_cmd_byte_ptrQ <= 3'h7; - end else if (_T_219) begin + end else if (_T_234) begin buf_cmd_byte_ptrQ <= 3'h6; - end else if (_T_216) begin + end else if (_T_230) begin buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_213) begin + end else if (_T_226) begin buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_210) begin + end else if (_T_222) begin buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_207) begin + end else if (_T_218) begin buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_204) begin + end else if (_T_214) begin buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_201) begin + end else if (_T_210) begin buf_cmd_byte_ptrQ <= 3'h0; end else begin buf_cmd_byte_ptrQ <= 3'h7; end end - end else if (_T_281) begin + end else if (_T_305) begin if (bypass_en) begin - if (wrbuf_byteen[7]) begin + if (_T_93) begin buf_cmd_byte_ptrQ <= 3'h7; - end else if (wrbuf_byteen[6]) begin + end else if (_T_89) begin buf_cmd_byte_ptrQ <= 3'h6; - end else if (wrbuf_byteen[5]) begin + end else if (_T_85) begin buf_cmd_byte_ptrQ <= 3'h5; - end else if (wrbuf_byteen[4]) begin + end else if (_T_81) begin buf_cmd_byte_ptrQ <= 3'h4; - end else if (wrbuf_byteen[3]) begin + end else if (_T_77) begin buf_cmd_byte_ptrQ <= 3'h3; - end else if (wrbuf_byteen[2]) begin + end else if (_T_73) begin buf_cmd_byte_ptrQ <= 3'h2; - end else if (wrbuf_byteen[1]) begin + end else if (_T_69) begin buf_cmd_byte_ptrQ <= 3'h1; - end else if (wrbuf_byteen[0]) begin + end else if (_T_65) begin buf_cmd_byte_ptrQ <= 3'h0; end else begin buf_cmd_byte_ptrQ <= 3'h7; end end else if (trxn_done) begin - if (buf_byteen[7]) begin + if (_T_238) begin buf_cmd_byte_ptrQ <= 3'h7; - end else if (_T_219) begin + end else if (_T_234) begin buf_cmd_byte_ptrQ <= 3'h6; - end else if (_T_216) begin + end else if (_T_230) begin buf_cmd_byte_ptrQ <= 3'h5; - end else if (_T_213) begin + end else if (_T_226) begin buf_cmd_byte_ptrQ <= 3'h4; - end else if (_T_210) begin + end else if (_T_222) begin buf_cmd_byte_ptrQ <= 3'h3; - end else if (_T_207) begin + end else if (_T_218) begin buf_cmd_byte_ptrQ <= 3'h2; - end else if (_T_204) begin + end else if (_T_214) begin buf_cmd_byte_ptrQ <= 3'h1; - end else if (_T_201) begin + end else if (_T_210) begin buf_cmd_byte_ptrQ <= 3'h0; end else begin buf_cmd_byte_ptrQ <= 3'h7; @@ -1109,15 +1125,15 @@ end // initial end else if (buf_wr_en) begin if (_T_49) begin buf_write <= _T_51; - end else if (_T_101) begin + end else if (_T_109) begin buf_write <= 1'h0; - end else if (_T_136) begin + end else if (_T_144) begin buf_write <= 1'h0; - end else if (_T_175) begin + end else if (_T_183) begin buf_write <= 1'h0; - end else if (_T_186) begin + end else if (_T_194) begin buf_write <= 1'h0; - end else if (_T_188) begin + end else if (_T_196) begin buf_write <= 1'h0; end else begin buf_write <= _GEN_8; diff --git a/src/main/scala/lib/axi4_to_ahb.scala b/src/main/scala/lib/axi4_to_ahb.scala index 92c626ad..27463d04 100644 --- a/src/main/scala/lib/axi4_to_ahb.scala +++ b/src/main/scala/lib/axi4_to_ahb.scala @@ -172,7 +172,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config } def get_nxtbyte_ptr(current_byte_ptr: UInt, byteen: UInt, get_next: Bool): UInt = { val start_ptr = Mux(get_next, current_byte_ptr + 1.U, current_byte_ptr) - val temp = (0 until 8).map(j => (byteen(j) & (j.asUInt() >= start_ptr)) -> j.U).reverse + val temp = (0 until 8).map(j => (byteen(j) & (j.asUInt() >= start_ptr)).orR -> j.U).reverse MuxCase(7.U, temp) } wr_cmd_vld := wrbuf_vld & wrbuf_data_vld diff --git a/target/scala-2.12/classes/lib/axi4_to_ahb.class b/target/scala-2.12/classes/lib/axi4_to_ahb.class index 6cb768bce221c64db6ec27d9847a148e93142fe6..d9bb54010ca3cd177a7c48fac86433d2bd5b144b 100644 GIT binary patch literal 107076 zcmce<2Vfk<^*=syx4U;IkED}aVwwvvW^;eeZ*Wkm=zKlw`Lg8m7kfB&OGQx7WwEH-reKWJKfkL|43}WNMl4B`zN>^j7B}U1}YLS`R8EcDLwzgPzPiK5CC2GUo z?syj+_<}|=CpX2)%jO2#139asYB<;!EXye?+n6&pGKbLynh}gtv7j0#572%&paNl#emQIj4CSmX~d=@YE< zAtt@bN*`|06IS|YlO73L7v|u7Wr2Ci6%XwO8J6+p-G=$r7tn*RaSbnNl#emt4w-Cv*=$Z>7sqD^z|ma z%1Ym4(i2wtR+AnHS>!jF^a(m$)N8w>3;XNz1aFrXNe2hdNm%I}COs0i*r(f+GeM{G zjuqS^>AYT5R{DOEp0Lu7oo?QUL@X6h%#Ja^N)Ma#Dl46t^n{fjHR+KIi~Ip5eS(!f z#H3g0bYZyRlFkj6u=0;K`6K--1}ZT5C+Kuxpz$Vum6blpq$jNOX(m0QM>Zj6x=Ej4 zrO!6$RaW{ulb+D&qFyITIJPkl$p|Cs^s*O?s717xrwCbndtbE4{;{M=X&$*lp4$ z=yXx;9*cY{eZNUJMgYNYi~!I8dBzC9Zz%c*!0E;aAn5uC!0FZzKru&vJYxh9{Q3wW z2#{xt0D@m10XV;P1W?QoAkR7iDCP)| zXN&+sjy?hi{VkDO(MJFw-!cLy<_M5y9RU<`1jtKR<(MNto^=FJ%n=~ZIsz!>2#{xt z014h+`UudGGa?U0fC?HKRlYNpKZr(xd2_T1McG30BeB?!;9zy(kgOHcdg>4K3$4i0 zg2AqgBD!ftV~FPE2Fl7#49@D8H!(IbC!(qYSN9LA!BD@wRZ1|RX_MEKmz6CXm=md* z5E~W9+?l(lZTQ>;{UedYgfgXR^|;~dGdB&*h^UnVi)v{&rVXDpWyAF5f&6|j7#O0( z$Ci~J-%+);Y29+T&efKy!Sb?|!38_=^J60crw-bg9SAQg9?;D|pZuK2go&}jELB}T zFi>8$CU|`RoQgFiojb-2SU-7n>AuZb1J<@~F6jZjL}C6Uz@NbJq0s#9ZIe%$4*D(K zHf7k{1rs8X39K>@7#WD<=btotkgB$7qTExKmF35#1@=UC=495-n6aQ{|L#e7Ga46+ zJ7r+3Y(__!Iwybf$mv_-D+<Yu zEXrB8a^tk_gjTS=b$vW z20aeSJ?X%(#ce0`3kDY`<@x!AfrfGUIYpbxmZ}5uD%&;{w*<#VLMt}R+Pb)SQ)p~i zs9|+R3+P)Cj|&{lt~hSMy0-O2@v5c!XJ&4inID`X`Kz>oA+76+Ti0n&&tb)F3v!{{ z4bz%7Oi}vB=m}#R%kp!J>dQ_IX0thyW5t0b+K9nBH^XKtxVqEG9Wyb z2IKXmlLqGpN;)rJ=G&h z0wb0ejGwx(sBOWZ0pr_&zf7&N*q!#PTswVt%ZRxR36M*b;$6!RbcLc@N_#45pgj9E z*jww~piN)jI%HnMhH;?x!qV1?jgxj)Zz*c6%>_GF=+~f6RWmDV7%{7%bPQ|BMHE(`p1 zS!uzL*ur^T!XCW+R!rKKH8LmAU&n#}4=JmV_p3LT_JAFAe94lmjkKR$-tG-xhcaCb z+gQ|7aX{RUTJ@#TbAt_{6B97o0Yw#q-(*_ zNrN*to)8#jzlQoJ2Dgrw+Z;b2?8Xed?niAE5T}-Jp2qDlgf5)bu&rj&@$DiWfPW{i z=LtW{w_kHVH1OTECr<)DH1MS-_dx$Bt1zx-?_8{HSUqJ!Y0t8y`*&q+E`~T`=w;Y< zr*VJWK+^ue0sToj3Q_U@Q9raXrDl&>jQ1o63oC&&YTV7$M{egg7oDCw`j9~vvKcdgt!qi2~YU))b# z13sJMC*{pLd1dJ&h^sT&gC__(L42CGZOYIRi=M*1rk*RRkDsUi9_$+7^_n?(c*)kvW*Dc3%;|}1k>hxL z6#8+$IuKm4azsu5`ak%o7{_?r*cz)DFk~XlaN`#R`^Qx7HzJ<4@2nY+XaiX`TvxQFS0Vek!-Gy72hc zAv3y`X$6Bj*3StHvtQ>2C-Zs2v_yQ+@NhfaPx7x&_Dljh=+|JU?pgf4jyJAh-Xrnt zORM>Orc=&4rX`GPh`)T^v2`_!_nBLYwl-=B`*k3LkC(!aV4iSt0_GF;YaYK!TU&X2 zUtiJ{pFdzozWtiV|LzSN#drwg2*iI~9@|p1y-eL(ls$YNx9i&FBT75syg$*1!QUKT zx*y`?3>X(<2A}kAEn&X~zbfBw!p@2n!}b1B9iFhz3srV#hIH* z0;8(H-wl2_KPn4sD(X(iIJk9LDO+v7hVfqEad!W>$y-XdR^%2OKb3}CA+GPK=Hm+= z_nSK#$mgRv-x$$e zHa;=Fit$hImGL+S-JIdj%!ZkZC#pBTAb$b9=%#w4l6Td^X&#)9>fx z=T#ja8&MWemk*{D)0-0qy4Gcmf>qvPVW5n%TA+Y3|3lgcW0t)o29_xz)BqHxIxL-lViJLQ(Izf+u*&xuJ#@AsmtTt+uNI# z#M+u#;#~#R?d>~yIznVDsOQZZBF9srNq(@tNT8U`%g*xFRz*`#N7cY>Y*%1JWEX-ZRj8!$(@x;x{sR>7aC=i{B7;yRM7gI=Gu zJ>8;8V56><*sgf}u2@R~r0Q27sA(@3DeiU0wwZUh0?9k=9gSds-JM)KH%_L^3MGZH zaJH@g!1pqlyxH)--h>ck`)f7QgxjyCjk z)$i_vzRXQ6)Pq*;(%Zpy6O7Ut>w->in8CQz?U140m4?tSqy`4(ZmB~*{id#~ekIJ5 zsb3iSg}KqB5RsJ-(NaQds2%4p*!v0g7I>)^2YU&GEK<0xv=e86TzvwnFZsFS@vBTz zlzCS)6Td55T$+ksW?70dxw(GgN>@?#2F@zv?CunV?5>twoCcoPE-BDp_1pnOvofCJ z{wh0L*ti7GFtV#5-`%;VO|Xe(Y!-NKi29ChX!RUk0B1Ky0O@bgz_Sgqg=&z5j%ssz zPa7B!bWOT`eMcua7lZCvzg@I?{Z6ok!7p_?=uK%{ z3bR1V>UTx6*-a+eBMBDzMjG~Zz*s2_-pQ*iE@g~hFpPE!KN9yd#U=M{=~|+(!2fxV zFqF_Qvu&}7Gf0Z4g3cqH3-Xi%>&g~W0&he~=EAbNvijwf%j>JFR#ZBo*K~+p>#gBz z`n+m$Oj+4*GQ1z2`^_lxd9bYm_g>e|17LRNE`4BV6>qmG87yME{%#uvB>gtPfEOyk zN2gT0`fcFN)JG+QbD%@27_xw`U-^={`m%)!YwDMPQOv9Al~A6zS5s5Ap?+cIs=6g$ zBu-hp1enWem(&-5B{xEY7{uDDjbO+yzm(a2<#pv&;l`B|&abS(GdXuTG*JDbmDLNO z3dw6JZ2-UKw~FhlRxGSsFO<;P1ffXOLBRBDUXXcR?6_ZCZ@*vSxL+dfhk3D5gRJs3 zRn-gY%a)Xb)6_v-GjziGs_D?jlNa?X%Id1t!hIms)~~9m;|5$*wx+rcy1nqbvWkkz z+FD^7m>sxiU|AQf7@@&@!NmufxM(noaM5NWv{?{rtol{1C@Zh71Pu`?=!j53ON0t~ zB2>^6p@Oam6|_aDps%f7%gbt)Iqk`5PJ42i)1I8>v?r%I?a66Qdvco7o}32yWi70z zSYBUVwqjX*c~xC43=5JV^4T)Kp{}xiUDZO~!z4wtfliSEDk~}smVN>xn+9A=TrIL9 zqzu_dWSLUNiZxOZP(sS6sa#yOa)qH%ZP~(_WL|V-DM;v{E1$V=d0Bn=nngxH$dK2y z^;OVenQ_5Ao|hqbYwJbK9lWTlwhlUOU1d$pnpJi6HI)miYAP$BM`Tu2lvOOLtS{z9 z0^OqewZ&#xRuT_XHUjU(IaUtca#lgL_3O$&r~U?8Wtk=HB^fzYTFj6q?5an<0XkUF zqv?r%I?a66QdvY4ruX<(K!uqsM8;sRdm^)wOGiAcWjx?ztgZ&k-a3Y4LA#yeUl88yBt zS%6qXF=gs&DzM#(P*_G#IRG@8G~PPNp6d-~bSYidk7%?SD$XB6D#{=ig^F8NQTTJn zMhEHt_DMu98MGf^*WRHAqpN8RR~OtR+yHAv#jrUSY&Cx41PJ62g937L>~i2fqwDB; zj)fsfi*>cMx4}w`GQMiUQmDGTcH`hKqnqg#j;ja5@CTxX?gp_kusznb9ai~F2f*7W zz}IzhoIogQqFqJLW@faB#<>#Bu)yb(Ro~ps*L?<|^a4f`5_+;l4gNq|FDsC1z>+k8 zv`Pp($0n=1ZM%U053{Z7*{@s%qusQJ8)g>_X4vu#5iLms-m|3eZ^M+Ta~CXpY>Vp}jvim->ZF$5R}8&xejhCJ zk~R_xsrD=Jtj}jKa-tCySuxL0;=VX%w6KdpctcE%EwoyD8aW)<>>iC#73P zk|YgjHLrUPZJ=k#WhJo`oEzWM4Nnh<4-Y_U1qR%c!hrwJ>&WOqdMmg1ZG5g`gddA7MYoDKHp0qXV|x=+ zCfLL~J@~ds1Q)zh_Sl~$*_+~$eTms%UfzJ*bBs}xocVtw%IwuhsYx3k_jr#F@E)M? zx^pvxy5g`_%vZa0gUD(_i>^u0qKH_pA{|Cx^eDZDH`mYM5y{#F^)si-=$dRPpg_Ca zFWcpTB)e2lu=|V+LSt9g;E^24N{ai2Q2-Op=tJ~jUdcy<)@BT?=MfE}sNtrFEvsw> z<1v2O|HAL-8oc?T+BSWl+F(Y@+rzp4i*}4YPJhj7`UHIAoPSSM058S5`CF#~z79|j-zn#IYZ06F&^4^nlzbM zGcsO6NaMl$*)j*2K6k=eN=~xV{tq7kxb%EfHRBxx*NTywWea}B$d6?1b4G5Fxi3Xy zY-Hphxs@B^zl_`_?gS_!x653Rksr&P%E(V-F2u+kG8bXwPJs>dW8|ljmdVInl9tWL z-IA8W$RU~Q&&bbYZXhFvWo|GdM`SLKkzSb_#>i2b8^OpuQr;*=elBzQjNB`8V;H$l z@{MKWewjO-kq2aM0wWK~+(brxA#;-%IVN*c8F@(NiWqrV=1LfOMCN8N@~A9h79+ou zxjBsdO6KM=@|et>z{uk=w}6pf%Ul^FPsm&aBfpWkN=BZPk{2`bl+0Bz@>`i(#>mq$ zx15n@WNsxRzmvJujQn2aY8m;1%&lSMS(#hM$RA~H10&DL+)0c)FLRq2`IF4mGxBGt zON^1fNLnK!FUVY+k-y5^Hb!2QxdbDBlery?{9Wc+8Tp6IwKMXP%z>Z1EG2g_@`|MO zF!HL*?PlbkGPjqJ*JSP#M*bypr!w-o%$>%_8!~qWBX7#ww-|X#=Dy9y+cI|!Bk#!E zd5pX(bKha)-!gY0Bk#%FcNuwKYIO-CAIRKgjC?5XevgrlWbR5vK9;$w82Lozu3_X; znY)gW&m{H-jQmH^Ze-+hnfoClU&!2#82M7>4l?qU%-zPw*E08GM*b_M+`%Z3w4cJK zH!^oOqXC)w8KXg&JHn_U5l0zSW$x#UYVz)VjD}?H0Y<~}?k^aPNZLb;X2{$ljP{ec zUoy&M?lDF)W$xFEX35-d7|oWsrx=aO+|!Ka$lUK3&6T-7Fxp?{{>bP6nR}kmfim}J zMhD5<3ycnyxfdB7B6ELdG*9MUVsxm?y~5})nfoWB!)5MYjE<1GHy9l$b8j&^O6J~S zbhOOXnj741|~@^IfoH9Gjv@^Zm2r<7-ebijDDL=gXOrc~lB6 zlLM^;e^=dSO${c`nsO#*O$#ukfHC#Qg3Te()=iWlaixvJx-4~ltu zr+wdmf5|9Wu+iDENu>`)a~p(YOsQOQON->g z#$C%!7s-T0Rp$nnKJ+tp4D_L2aw9<>`pFlkk}0Ky`5S<~Sdx>Jl#O6+#gVeG;a2Xt z(Rb)bHf+2yHs@3=lswq<$>8BHZzUJnNai*l$utFVvlP33Bmk?1zL7<43X*JC~mP&zL%3fy*jSwu@N%>O)Df4@oMCg-%1LWqVTJbvJe`Nlp)4Mb{Kt zdL%10Q`9vOtg@^4FoLtsV-BYa=Dl7R%A?Wccq`c^AkL(Vvh1IdyjZ`{d1Y0McE_Au zXB4}wq&SbJ6tRJC!s@eN&dK*?Nk**y=mqm_N`01_+{x9aICEC(VL{8juRe?BtGgE8 z@$g>GX?Gouw&u)+hk0~IeNUOx66fRNn0>s%o7vzqoB_9w!DX)q7T?7#9CHN4n;67d zy*ee6?hK-b;O-2Pq)uj$Ded7H!cuB)`d&)K`Woeu8|q{er7X(yOEgF%x8F%IXbb8* z-lLLbvz`=%#zp5IKL4y9lTYieHNI-#G5K_|dQ3i@tR9n3C#%Qg)5+>F`E;^+JUm%h z`+RtEGkZKdxtTp4p4`m3ebL}$@dc@~$HS9bvd6=do7v;x$<6HX@MLA?&jTJ0Pfk{! z{>!EM^k2^E(|S0&cUQZbpMj~?&*qF(;fJz1|r171bayO*p z!9tqB;~mlruH<`GEbenA9`@z-QduN6&vWouX0X^0z`6C!s8S?0HVGzkkE&$E!mexU zs$|8iXYOc~JlIUaw$W9xVQYQH{#S27$!)RTI$4LqRE3#CT`H~3y|iM$$HEe__-+Nq zh7v|f$y|Q(*Y=xY2Nxsr$O-)BldxUTf|R?X7@1EN@Viela-z)rj*&8%`vW5jrQkm@ zQYmxKGqOnL{>;c?nR|heB{KISBULi@cSe@V+)Ioslet$Isg}8aGO}Fe{>8`&soxun ztdzO87+EFnzQf3Bnfo^*H8S@;Bejz6Lq_Uk?qf#Q$lRxltd+U{FtSeOzF=g%%zeek z1}WvgjBFG+1zy^nBy&MVHp!gI$Yz-fF|tKql?WsC!Y)cbMz+daCL=LO8Hvl>U`Co{E{~CIGB=Eo?J_rlk%Y{RV&r6*%V%VVEMp8KEs{2tkyc4N zo{=_5o4`oB%uQsZL*^zkvQy@!GSVq?MT~UGTnQuHQpyZQdSq@EBfI3?IgIR)-iIn%xz%g9Em-Nk#i+&Gb86oT0JA@OInPP@5o#uBNxcK zaYinbv~7%BBy$NyzAJM(7`a&HS{b=S=Gqy#RAP5Ba+#!cF><-g^)T{1ncL0C6*9M% zkt?N_oC4b#x5c~lkJaUO;2Qs8nQw=S8XK~V10zDpX?)-N%7tsHD`9U^ZgNkQ!7!I8 zXDDYzl+%@O!TyqlqN1<@8+c*6viTjZJR-uf*WbV*=SM*67AWUrfVgvE)BYN!oF9BV zgN#wW17#b!^>im%rY=gfz}Xwhh1SiE<_)3McO%M0%EhpuPwvyv4{``8m%?T=eeaG= z6YQ5ql*^Rw!44p!9M~f&kG1Y<@9AueC)%3Zr`C#Wb)qdEQmzb>ez5y!UZO40J)iGB za@V=43U)s!S1Z?KDBoAEh3#93R(V)S%U&qR3eZ1Ro?wxolbCY7@`DV}?FL`ERe_oz zg{0*D-;0m|eSskb_M(QH;N0sIg7ZN%+hZsD^RV(~?>^N=Zb zD~B?ayOf`S4{vX74l74M2`CbVd-;D#wxrs9n6?UXWK@nS_izCV|YOJTnb!1Ec;J_$nmnIo9qB?N!$< z4wr$RoUc62dooM};L8${Z}FL=&6*RPo!u={b%gR8<;e^(T6v0+siwJcX0v=<@$;3Z zd8B|%l1caBmJKPt*X`F3gKgUu``P!DCrfelcAuW4H{-L)A2XCcD9{}3vV&l@}4~qRAC#W zc`ywpi6HP%MEOwp7!LUHYKf z+goEHe5hddUi($rEhWV9KL2$FRO!DEi{uE=+0)jYXpK*;Ni=S+YU?ftsjy>fh(1&} zZ*rTc!H61A6&}~yy4Q6=x8+~A@K2_yn5wBEh}voxMpZ7ir2tGFZ|j1?siyJR4?}}4 zxv{;4|BwOPn3`y9?dj&9NKCEa-@nXdYKGb`1Il1gE+)cDHx#4XH!H_hK#G78)gI zTUGElRLXkPhd$}B45v0=9emC)_aw{Rq%mAdR>WFbYT;lXu*`6EM20#{9SN2hWeZV= zp^esE)YB%~wg?>NJ~cm=5cN1{e`zDM>8skB;(OvvwJ`RC)B;M3O~rjN3y&NZQOBys z^DZ50EAL6PG%bQdx+s|d!PiwJe60iP)S+ovKdDP^YM{gIqs{%Tjx=Om$)hI2CND4|T#9ZJk{Z6bC>R&Bik( zPwEVHW0RHk}(25HY2M5LglGf^)=F_-1-KUGz=M0uZ&@2@f{RSpH1@bfBJ-|KP39chgCDvs6T!|1owvopXp z=Q#UBF%MPFWi|MG1lDY%3&CV5QUKwuy-ln(u1@7M-_*=&nR=mm5x4AjVa-MMo=af; zN0xpW_i?zfNM2q6i)}LZeOO+S%vbXX?lD-Ak(bxOij2(t0M<=p?nYQ&k+2`~`QJ0J z;3F?@;bYN8bMkI|c;L-$JrffG(=hc`m_(|#fiIRb^~YTJQ1vHF`8U0i_rN=0QA^6b z3l>ad(T8BcMCJ}d>~Jq%hSXm00&&=yI9`pZ_kalXs0vSB_UHw}i_$P{+O)8GKP({1 zavp?*MwtTxd|Q_DFf9H^8ayKf8h{@jkuv#w7l!br#4h2Uk4yLbH7pNF)Ni<(Yc|74 zmECb5iTd)i$@4mzBRs>5y>c9Ccn?Kg7 z?{lB|IjqD)x<79%7IXfB1#P~7|)?X#;D_CKbx&OkdtH^0E z8Flc(dSjiur@%U_%xNwz=%RydGXNNPD%<#IR}j)7@a39)4q)EpAyMlW(K0mn>>~_g zUVUtLqKRo)P$BiGmJQ$L(Wk(1wH(_A-S+5jzY?*~>@P-S*ZOBbDFa-pgU@Eja`|H< z(+10uVfyW`#B_)Hr+ndz|YYH2f}kZ-VRI99RjKrA%_(D~5+Cd%4BXwmT%Z`(81uN6S*cKn|Rn0^RHs zDG8>H4sNiAg97!H;RFVwroBv?3s7k6c`in`u-OJwoZQH?6D1U8fQ~Z2^JOb^#=AP0 zwovj_I{8YV=DIFT@C3~?-g7~hD) zjWDWc@UT3<=;l_Akk)KlD6)6RZ#wKIV@9$IZ_m)SX$k8ig)tiPPA^tnv>g#LP-}rl zNA8aUwKjn8`CO(|ZwN{|!Jx?kcwHpAE24F3V2dn+UA$-m{#`KBPx4Emh+TUk+HP$x zFYdP)kUJ#<@StI`IKdjy4#3E2h!l@Om2Ew(AQt9V=Gg=04I%o>h<1hsGpz!?e&l)} zGM{Ct6J6Z^xKI0b1^~{6Cm#=HeV!y{OCb&387SMK6Ef|5b!LWko(5B?e%&nvvBt(Y z9Ptb@+A-L3u(NFKLhT}s{w^${dz8Hb)^tMJC43RR4=z#v%OcvP+T~z(=VUUZT>(gMpYY2Prrjwo;blRfemc|cmY0Y4m6!MM%UMjjS6<%7FK09D z0eShL#mjdmy0;sh=a|*Y%^RYXAC71bX^+60Z0JCs`Y)sEOs3YVb^PM-Y)$)hH2660 z1MUX^-HD9llWC$4Jefd~Kqq=S1N3>uvc$`yPe}VcyfNhwC7?YE zT|`V6I>o8nOnXj_EziT7V>x2}8QxRN+zZB}rjt))Y@eS~9!~ufJvPJ$P{~b05IVahdx_ zhd1cje^cyB9V%q>HTo~`pAgK<)JA>)Jqt~d_ohOXp~JV;!=c7; z7Alfhm{ZTQOhLqv^~n)POmgj4<{&Q}9!7-FbXaK$&B)MB;}57?Woa;l8fqJgYN1Cq zZijhAH>@CqLZwi18Gcs4N#F&c5X{Rm_1+^WyxWH6M?xor7Qk9&EkBm3k5K}6V0aCc zh00-pKUCp8N^s^-2xe+3EaP?WE&bD@pZ0+L}ugPWp!=H3F$Am#Ccdk|b>d()L`Uanh@j zv;#;jxg^9%pGZ}dD!Cj8+zcRFBZB%GQeDe{}e|3cK)LXGF1Ig2Bn(~ zfgPRgz<-P6KPW~tcx4-csfIp|NroRw2AFbWn~S{gZjZ;gJH--X2<9JB2k|2fEOfVo zz^YUm zNz$`G`eQE11QLCRzRQ*VlVOtGVrUQjMb;0d232NHx4#dwM|XYxVmQ2GeIw~6FTx9j z5X>#)B1IE_nhpI!mh}?ThD!Zj0sUUhC0ShMk&^T;AibVTvVladltaW@Oe>H#-+`O& z=8`DqA1g`k1L=cYlEX>kCFx@zeUeLZIccIK{Rc>&=aT-MG)0oW0@ByHWB?~k6{IlD z*1~~YcuWIQu_UQL(sIclPMRS}5g=vclEIubQ<5@)l$A?{aMBz}g4eI%++32!Nu`oB z5J-b^$xu$3FG+bo8k$Rn0g0R_Y8xKGv<33!D7ZN~mkj6p6_PXtNCmlM1m`c4{KqqG zvAj6}ZWiW}k^JUm!sEh|`OFc1(4-w+vca?_&caiLbA@5y?R%01mR7Eix#`{`A%Cz7 zg<-X1s5>@x)%3L0!MpcRm@kR+v^BKvscVN7{}fLNRV-W@o|_S#6Q0M^R{AS&%Z=7K{W0v)iNq;qLys?fqNj4al5PA9|p)n9j)`eyfp)kw{ z_(`kqqc;$G9ZzSrx6t7!n_BoKm{@lY|J4$uLL45L&G*2q=xJ?;ch>QRQEvS9##qZ*I69GE>%^%1 z@uyY%M3OkXseuVWW^Fh8e%A6>ht9&P+Tb;G1^BETwSaDX*A6_c2nwiA@=1UwBuF$8CK+&^ zPcGlY46~nHzF%3Sur*nvunAeDumxG9umPEnXfA&m71yv0S){NDS){N9S){N5S){Q2 zSfsG|SfsG^SfsG=Sftf@3Y(6_HEcN+DQq|vDQq_uDQq?tDQq?=~(>MK&%=qpm#<||Uz(q5k2kI)1!I{ z=fMenI1Nsua2A|M@6+$!ucr^_DVzZ(?!yUiB8BtcL<*Am&OFM)&3g@{AemKodq;Qs-NMF#?zv}6WdJ1Q_iTiMZn@HjOHj%>VZ6bxU+e8W{ zw}}+aZ4)V++9pysvrVLMVw*_eyf%@-X>B5fv)V)oC$)+6Z9RQQPvML*)YJ9jK>+^mMSE!g*?fA5K#fDV(Jy(qVc!Tu(>n zDV(7u?!yUcB8BtQL<*;;i4@LG6DgdWCQ>*zO{8#Ynn>ZyG?BuIX(EO5(nJcUrHK^I zN)suZlqS+idOBH8;fypvpQ@+Rbo;^SXo3!BqlvUcPp9kY3_YExr?d1F&O;OYa2lFO z;Vd+f&ehX-dU^s+>2t6J5q3L4lIM2^9{TbPrvQ!$(UN9S+QN3FyJg3{gG<2!vNdJ`wJ1%lZ8X{Y8k?m=S z?4UdKikn_E5xi(OF4OHreAXkqh|hbHUepO*)Fte&Cq)UT`YmB^vV?us681s~`$P!` zaI>6&7vOF@QGnqOAQoKg%oIwWjmvbKMK}cbV~Bpssx-I;5O@ja&~r&pbl+7l-&cS& zTsUm_D?Rc?EBxlm1S@cGjnev)t(VOUxMX_1* zhrC!pyBTu4owDeUAg7AlEs)cMQh6G{qx2^D`yu?@41Yg@zgvWYKfyipE?hCUhu*>M zVR+~rLgd}_knTU5Ko_n}hOF~F^j=)-bjg*hZw5WAn>mB>0=Sto=n=^A`ex8x$SJxn z{Y(^|qW~ld%u!&A0t5G_`|!Fwh%4c%Zoi<%a0hx67wUE(qh{e`&BC%~h67pZ0d@E# z{gtaTPMkF29{L-<1@ex^U59r|!((~3G&2cQ&->HoPxQ}vvss4vBlP*Z!7e_AdQ#2#eg@@@&kHKu~DE%kTa%Fz(jWL9w4F!$1OFTaALkEzFA6U3 z2fh!j^EiLt`%&o<|1m6x`wu{C5=G<`4W26x`tt{1OW8^ap+!b&_s>;8)O+cliUq zih}p}1OF2R@AC(K4F&J_2mTidKHv}hIto7BANUOve5OC}n<)4!f8e)J@Y(*rZ=>LI z{ej;>!RPw}zl(w|@CW`k3cko6_&pSSu|M$pXqUXyANT_le7QgHhp5_D_yd20g1_$% z{4ol?+8_866nw2e@TVyFdVk>0P;1}d5Bwjr>JR)C z3clSR_-hpW6Mx|UqD^(DFEA{jBX1Z2cliTT6nw}ZIDmo=`vV72aIZhGf*R}|e_#~_ z-|G*op=#gn4;(_l5BdX#QMHfx14q!3ANB{%K*5jt1NTG0zw!rWDEM)I;7kEf}imR&OyPy_Xo~J!O!{w_ea6c`2!C?!GH1x9*Bbf;txCs1^?9_ zcrXh7n?LXn6#Nf=;5-!kvOn-p6#S|`@Gunonm_Px6#TkB@CX$Ara$mV6#TY7@F*1g zu0QZ-6#Sk)a6StDz#sTH6#S7t@E8>Qi9c`w3jWL=cq|J3+#h%x3jWd`_;?ijwLkE9 z3>+l>z!Ok#z#q5}1uOo*6H&0{4?GD4hy8&kqu>mG;3+7W`2$Zy!CC&m)3AA1FzOFn zgqED^4_u6b2lxY*px{CNz|&Fi5P#qqD0rwp@Jtju+#h%r3LfbXJR1d%_6MGWf{*hD zE=9ow{=jol@Hl_qc_?_iKkx}CxX>3kI1%5+^q+6Ok103_7x_gRA}8Y_ze+>ol;Bik zk6(cJ7in(imwWtz(@-q~0skVMd%}W6xJV@pk;S-3Ee(++xX5rCBB$dbGtv+_18;HW zU!<$WXX09B`4{PG@maW*QU4-cTF%C`%=ItQrR5x4P!5KbcNtLT;$R;M6SU_R;M9yEiQ6J8Y0)>B3Gp$ay>4xCJm7raFKOsh}?*aT$_f- zlW>vi(-64{7r8MFk(+Umo6-=u1sAy`4UzS@$gOFJ+=@q{2LB>m!&wa1vdO!5E;iswxl7l85h}>hRAKW$c{8bZpTG-rXezcyLz{OkuFz1 z8P{@`e~~U%-+_zVlZMC^T;#qqM7H80_opGU4HtPJ4Uz4*$kWph*@25ZGYyeDagk@G zA+i$}d3G8iyKs@`rXjK$7kPdfB71O=7o;I_7cTOmG(_&kMP8hS$US&)yVSo(S8&^l zi@ZDyk^At9U*TV*D_)+0i~N2XBKPAWuTDecskq2%(-3(87kPaeB2U9x{09FbT~2g5 zuH{YsMY>x23|!>RX^1=%7kNt>BEN-;yfqDxXW=4mPebIlagjesL*&`G6W!@wq|1rU z!L_{0zetx8or{Y+l!nOjaFK`85P3c>vNsKp-@%*b9{(a;&2s@R^4>H=UWixxe*Yp} zEq)O$^1(DjeiyI!G5;c6w!9eE@?rlXT@}9s7x`!!A}_^7{wfWTm*FBGPebJ8xX35c z5cxe^N( zI1Q19agiBmh&+OeWNC=(#YJYNA@V5t+!KuY7wLNLxd+!W*S|>DbI;Flkpt2Yc`q(< zP#Pld!$l5BL*)Iq$f0S7d;k|YJPnZ#;vz?;A@Ucv$kAztJcf%rE)9_n;UWvt5cx1J za$FiBAHhYAPebIRxX8k9E|Sa+{?dK0YVa}Vk->AZA5|cw!N(Es6Hf3v6g)5Z8wC86 z6FeUU!w>Ny;AfoR1t=JPQVjwB-U&Vt1;g*FA>e17;4&1v5H;9yPH;I2u0+9q@&{go zg8$+Vych-l)gO2X3jUiva1{#vhd=OA6#TM3@G=zqsy}cw3VzKAu0Y#)ISPK=30{bT z;rEdd_k7a{UW|fQqTsik;3X&+ep?wS`CTWt3I)UOCL>^R6u0#(^ra{mehC@@f8Z>6 z849jN>->=uT#bV3Q1B;C@NyIkKmUoS{h1TI0tK%{!Jj+9D^c(|6#S(Vyb1-cN5Nk^ z!K+a){N%X1&I)mYYfv!!wm1R~IKj0j7=FVX0V_^$9SVk@B}c%T6TAim!|$9U;II?C z76ro(gCpP!CwM&yhM)CDz|0BWfP&$dxDjxc6TA@x$56GSPVgoa+<+P^*9qQ?g5l@w z5w!<6!CO#p6AB*W1lOZr_!WDkZ6F%-NF1rK+E8&L3e6g<)iZbZQe z6g=7qj-z1seP_gA$2q~xD0m0zVFga`HWb`~mORc0-j0G>(UQkI!3h)$KNpSExzGtd z83nha;7LyK4iwyhf~PpaZ73Li(;QKIniJfPf;&-gu@l^Zg5d|nk&>r7!8=iKH`-J) zo#0Ls+=GH=JHcHjco(X6sT16df_I}O&vSxzqu@O#c)k<72L@Omfs929&u3f|}h zpNoReL9M;X2|f=6pNp2f#R)zi1)qnOywwT*4hlXWExEx7z7Pd}2L(4d!55+63sAM2 zo#5}H;0w``w>!a?px}#8@X1c_r6~BjD7eK5z6=FljDp*o;LB0)B`CPV3BCdaUy540 z(+R#31z(1i-0cKkg@P|f!MmK`t5NXxQ1Bin_!<;^1q$Bh1Ye7SuS6e>_B+AXVPNG{ z<9Fzk_emE2@j&GVhm^DWD`)pA=k+QV98xY(Cq_fTL&_ERDc|4FU%4uW+z=gqRJpEK zx$&6tL!cj0ZtYcmA};UjRSpYuuYtCrrlv;S+p9caFJf?N=7&TPj~GR`6}&MzCN)|r z_)7zADtKeGFg5C4rx9+9o|u|jmhl*r0jfsBy~-24%5Qs>-&w18V{~z90r%QDXQk$R z-eI{LqtVpNU^%nCH$>;B=KQm;@e8sBs-*&MYv0tjJG|(&_DxYQcW_$!rf6kqU8S}E zj+IfJ8f7!_P0@L&IiGiH(~z25YV(q3+usyTq!!>%Y(r{Jw_-WutkmpMvsb(|%OT%M zEy1DMDXBS~Zh2F5U}|QYTizJmoSO5`%Po(WL*Xa33AusXNN%JrkQ)Ljxk>3HH!9bW zABs>1zkaJ+O9INP@<%W{%J%)^)(p@)pJEBcwHJy zvvvZ_=@Pd@i&JYY4UfdcTcUGPqg)~9mgwr#+_DVskaJ6PeQE)=w!I~~C^e_c?QV(o zq~`YHb+<(KrxxH)?Bvv(PN%yiIwCc*97WzVqQ)hzCOz2qDB|7A4|)zLj<|g=n(e8p z8MklAA(y6Rm4W;1)YZB*T96to8w(j6Z;eh&jdFSFtf6W%qYF}tl{S7iwT*9!j!li0^+$%p+oF?FqntCO+oCzCnQZ~}*67yMoPS;} zVw^`^ZvRGgx&42s%k7?ZS!W6P<46QT{w?%Haxicnxg~Iz+!}nB98`vo+mxS^TOrin zuAWVPoDBc3keez0b!Yf_Z1r3t{Hy0GuUW(YYa;yr+xX#gnnN_`sJB8cCqvYQYNhx|@jDEwkUNz3xK+TucZlJU|D^aG@Kj*_ayu|Y`CtjeXta#Z zR~Na~LVH!$N>!=*xg%OeW~)^Qc$rxZO{ju^NiKbvzM_NUP#v!5=)w)v56j_`6(HtTlN#dR)qy=nD}1$yF?0m~r^! z=!Dd$dy^WxY}4R-PR1Rn;H8oXlDfZJdb{9R*O z%PRI&kLjFxZBpi|HkrIu*K@ha`~MU}u+bm*{Tujw_~SkKN^6O)MQ5h0h+>Q4cEw`yA$d&BE72Bv+cFTN2SnX(uW4wIFCL(Cow<8WvA8T^^X zdDGQ!M|2+Ea5fKoD_WAWPP`WZmBuiw4QMoBK+qK)@yBB{Gh@Ol~Ew&_ePmJwX0RuP3hshLV2;O353+S>(;& zI`UTV59Dn#k}K1(NPeFYo`1{Kh|{WXxi+}_UbdG!D>y;mP_$DjA2C-^k~ zdmfQWwZ-)JqBSXHiZJvG(BAem@Ltq!7<$hZGK?_v2nhV8VsrcVz5Gg=gRe_C!twjj z($uOyVeKsMdxf|IpwE+b?j@<^K4s@jy~ttl^7n0a;Gywp_|rqO>C+#03`(l4+z+Co zQ)_63#Sg?vuHpT>+~4tXlfC0ZmtGgZeWZOp@_JTD**+gd=cd-u);=G3JRz#C_W3AU zm0GUNP9J%!kn?W9C#6X5{3yCFWdU+_fc4Iga>yB}VYXrIqiAbNPJ8zRp;x44<@01$ z|NO{f01_hu2U)!s%D6LS8TPRLk;nR<#o<4)ITr8ue6Dao((yia4LN*B;?4(i6thEo z63tJoml@F9A(EX`v z=$6BybxagPrRB*ghkWMsyzmrgZnMj09#K?rE`NRI5qK1{MLtV4?8?=b_h>G8ABNcv z0+*5x1Bb{*YCrO^I+1*$?j@gUwd6B%xD7FExP8_bZo`+7Y(CtEXY2mMgV%G`X8$sJ ze9C6A2h}h83PLhc*q$T4^cX!;KSz8S^>`&?3lv{^Jtf=5@h_vPU-3EXIU}`2%)#SJ zv=4I|z*CpmN5AqKw5|ni$IRy|&u#^i>;715{mSd@oy}rjMT=6_&f=k8xnhPsS+hCM z*B-M>5i|Z|jv+RyeC^>EDq@wdqiw0RPB|a^+Uu=}%_?6Zrs(*$C zbqzRQd#u&#D>J6QeC>Po__fOc`Hacc!T;;gZI$PfL(YF~(vpv-#(hd$Pa-csY0o9^ z(AR*DN8Y#a5YKDb0Y6Fbjah) zn{9GSLmsaL)u(LBvpK+=`kBYlej)qR1C-;>Jl7}tao8RQ%oTx|@Ze6!mvk%nDlngX z9ej!WSD6Y+{wpa}+G#-fE)A+7s;H+?Ra-~3P!SD<2h*@QRSD0=rYiq1rYeDRTI7uZMQJlB1@mkhO+@3i7Tu;L)nMhBCN=n!%z z%_G01Lrp7^e`8jB)v%)Sg?u1Uj_6i=EosG(wsN@@Uxz*3!-JIb+b*K3Otqwl;?T15nB~RPfINxvsFP3xx@ouGnUm*1<_3@ zVd@8>_U`3i3Z?xpHS9xs0UmR~=k1)SH-K5ZzrZycw!FvSZTGQN=va?=k76r+tjDBB zpCMV-f|8F}bgb9DKyySHn`%Tkj)dX0^hk(>qsZ5EG#yFv>3n(|-9pC%meGRXmvpQd z6O|)aO#H-%iEKN`;Uf#T@g zNx5XlVX2ozlzX8Z=j(c?#_p5_8SC($+iSDT8(?Q1>dl-Sc_+HOz`n9E$u(cH&!;B4 z?z=Zs&?z20IJH%$c&vsf$qf}C-1%I>+eVw`g{Ks?}qNICBS+_@=nsV5!)dpb4DHt{Hm zdVTR=?cYVwb*W`qSN@^lJr+jH$F3sR6h&+Uf#$MqOQOY|t_$3*E?4Y(!LHcTagyDl z*wrn(CQ~JzQ(3D?OT4P)d@n{zyk=1Hy%;|AD)D&fY+0x(u}{6gvc`fjw=j&2X4jnV z^=`-Zur}S_qVaTBNJk$UG1nc>fWX1M(4CeW4F(E8$& z&h(tgB)xH_>%r7m5H5s3qHhWX*^Yf+bXL^k(=q;BZteq<6P4GIN3K~pe0F8Zs zxWNNqi+!Lqglf~zW_i3Na=yrc`uTmDon?QTH5Xjw!&(WU6UcsANDt77!L#V3;LUV$ z@KHKNSwyF*Bk44CJ}nA;hZcut(2~e7Iz4hFosrQ)XJ$M?XPFNmOv4^PzAzp@$Ri{q zmbNa08uQ-ud9roq+NKu9($;6m`}1t~`Le}}rU{c=C%F34-x03)b}rKnxv;UE(7Eui zHIJM~Paw_IdPv}fSlzx%ZnGY&Z?k?Uxy|}(YnyKKh(_vGp{4jVp|DpYcHFF#Zlup% zwSXOPQfh$hS!bKq>u>i?>m0gGJaidvE|9I()Osq;JBYosU}}45{L6`CQ*QU@whnuR z?708YUfZM1KJB$V+LV%0!R)oYPkUJp0z&N-Hta=ihHqK;vhcn`S|+&vvR*9;zLKjn z1+CRjcr882Xs5fGYIDy-v@vDf)UCbRK=;0SYCVW(AJ*7|lFI);SH35ye4c&%?_`g6 z*W$Uw4DdF+Pmb3A&w5+WKWb_ZifG3povp)b#%=FxHqAS}LEBpovD%GkK0c}WwYuh=Qu9LF z9$(t&KSJ1)?)2Kum?A=0&%f%#l%AMW+TQNk}H)2-Jf z9nd+Q?DpMlRGay_J-*#c<*n93yt**+O-*X;Fkg|)eAd${=&oL%Yq4q~>-LsxR0~2(wLdZnEbaC}KSp4K?9RLlJo6 zDL>dVXOd4_OW*7Dy5BaFw7>1x>+yZHF_WBaFUaHdk8LKo*JGs^of+*F8`-^PlGc;p z(3#O3!(PN5@6?;^GmCv56L0$ft=?p<{XUPafT=p{K1)AA<6UV|>5cGWhfn9G!Q+CQ z&YfU7TyhqCN}qN*#Zu%nEJn;v7J0TF*)|zPs`uK5hW$S0GD-FJ_o<%sSiMb{dJB^3 zxh+zTSmac(9OUIW*2DNvi&S_NxdnfAZ_Io#58N&7~u<;|Jv~!kEdPqC(Dmr7*G3~q+lY6xb zpthw7WG*gM^HgzfP@W1mOSL>rza8Sai%Y|KVSb-{m>1^vBY6@1eg@B7T-qa~GEm z$QvN;Z_69N?+?rysNWyNa~GEm&KoT5FU%Xv?+?ivqTkQsxrD7LBO#6dTR%JBvf9MH|#UVNNp75rjS&H7X1i`#*V3JnglQ>t8u0jm)t_vDH z(FI&;D^ptHJr@v8#c+g>Wk`V^7`PPms}|eb?Kb(S56trDDAVeij3}S!6uv5!grLYfl0Qhdl=qq!^wupb>Yzdz6G)H02dT#(|UJ*R|dI(?l#?uC_BUj zbbDV6DR8I{Tmw?W;VxYA6iCyD8f_6nT6Lrw=yvzGEj&r!Xcy4fC}0-YjNpzla4DR2 zo6XIn%M=)xq{|?++m4uJoB>QxSi;r>vas<6#w^U;<|iXHD|7)-2i@VGVk(pTLEDfj zPH{mI-)^_nQ#RlT?v(M%l(st#2VD=;SUf2ibRGZ_= zau)T0Ie^%0NgtTg5X@2ole%4V$mzC0Pr7=wAK)2cXQyFx30&a^c&7M}!46zy0C87> zU4=G~v|~+QptG#6gyob^sp|`LHsVcd`vRSVxW@XvKic1B$2mv)2prnr2 zFp)#PYwOWc%VqlluZ)hIG)DzCf2F(Xg#A&=rV!9R?_AME9td zL#{+duTBG*%7j-T73=N`bTy*muD(FmAdR)BFVM9JXrF7go+@5^*Kz=6dfeSP@-2IUdMXDp(fg2;m@(ffE@PPde1*U0hM739fI@Th-KFCu-NQ_*HOHw(AP(DKo_gs z__m?Tk!l|CtR}4T^w;?LzhXZeoO|H@riC2wt7%ZQYssIkfj@An$X?T0co4_j_o^KcmsU)T}LkzsK%cex{}ABlmlqlbAdQ0m`>l zn@2Lx^uN+azO=sQAP;zH3PoFY^>PpU(sts@176?4OZ3^^efj~96H1)BEJ0a*vLW71 z_K@@d(o~^9VQ)x*IyhtLgJRN;i?#UDgRY>mtTz29L%b%GfqBhCUKQ-qYaUA5YaaSvyyhX_Uh@#;UY9t3L7Dl z(J~oh75$jkMh3ne9#k49lL>a5$Ht)pc21AM#rkm_dCcQmd&~UpG3WN>&_t-}WcZsV z71gU-(i@tYoZS4{`W`ei3z+AapwLjO!cTblHOwctNo=y8uy!~u8#wrZpN@C2IpirT zBOma^VZZur%%rNnb-4x{!eH#IPjWqNMeVTt}di!EM zbE}>$PCwV)A&Oe5SjQHar^M2?#Ii>$1tpf#Vi{6m*(a6}C6?7<8B=1pAeQkZmh)nn zY+8D5)MxgTdnHuUohzwRZs%-^`s|JRJQ3O8PqNOCIMrMhhPy>ehN5;wt?wl>8_ZFp zM>`L?rYf{#2JWy?ZWY%OYv-`{O`9r6kxU6IX;<@;s@%CNr(U$n_NgwXs=q>1tUrnZ zvrWw5XHD1y*_IuW^g3ZB%}G`6UVTBazNA=R8mzZe+YLk7yty;?j9eXaD{ik?dWYs# zBIaB|u9LtVlYZ`?xSd%7>);$M^<`$m@C}lJvg&u^j;dz0L&o_P_M5bLXc@M!umaS6 zaCuNPA?pfBf-V;}XxrpgB=Kz<>+(;Ys@!b&+TZQF$(o*tYlcrXrU8x<=V|_KVdcYj#5BcjV|zzTQ|#Nacf>UR*sv*)6Zuk?&W@O-K7UrM zuM|(t@-IU#gpJ1D5z}tF0i?MaKw!v|@h?<|>B`O$x?$M;gjchNBgxL(Wtcrp(YkKl z2CZ>qmfiF~I87e*Gwv=V4#tqMu^|)2a4wS5u zt?B6#-j^di;gyehl~krVHwaS)GAenG3Yq4s-7vn;I-DIQQ*l%`(Ao7>?rdkOGz)k~ z6JABe&1lwmMWfIHYAfAL)l)9iwmaXm!dG0Nc-@~@?2<#BT|oc<&S`K7JOcw?kej zQs^ABl~I=RkhMoc%2Mcl3KUV4`!k4~r8pU3zguQ0&Uf0Ccw{Q?^VVX|@Q+ZGdTNuy6?avLL_|2i2a3I=~j#Wyw zf0)9zDq5wsd~3Xx8+`WdKG))G+cFDFRCy916G)je+O+`W+^Vc?(}t2Y7nH7R^+ZFd zTpZ`za#UwhP!YlQkmC>kIi;w5wvxyF$?|^4nhc+Oc~6p|KWCo>=aivk>Y53qqYTXt zFKSJQE%CScV48Ehssaxmf;kGNq_cAwgIasZQ?!fgiGYZ{B8?Q%`m4b)E7YI@Pg z+AMR;XF%S!8?4Goc8QnaTw8VFsf-k|XqC~oIF^Kg-L>99T2`^$Y~f*z{j-D_dUn#o zwg`~;v|r2$mtxhoTC>nowZO+wHOmrETFdreYYEn1&s!A2`ryzO_*jv?Q+lBpu*a;n zr{b#_){bt8-M;@`9-W(wN8f49Wu8KN7E~2rkkWVAU(Rx#@~oAa3A9o?H#l#PEc`=k ztdm@Io~Jm+hUW&Z2Mu|*(##ebIr9{{yv+v(_LSf5Q-(ZS`;zvDw;=i+X=l!7JiTt~ zO$hgLoTDh#?lwD#^8j4FVt@%udMtx~u$APi1`nKZlIcY&Yf0oQo{X5P4#k6vQlWCr z_bc=l24ALdzHPX}IB?yJUH5p4!hxOO-eZB82dA04*gwuy<eOLUx&m$c8QO0iJzB*juHKvptz`vRGi>5W%%PCDd}7^^ z)tNSNg#Kq!+(?wH-sKXXWfMo}r$V9EbcxS)it8%^q1Teo>$=3}*u*6CWUF6(DV%!(XAXc(JTLYb^n$QQ9P4@K8 zQ|xrGKQf-D{C-X_z4M&u)xVL>D=#!Lh?F!Y>$WMLZ(ZMD+m!UeppTNK7r09|4MwxT z=}CG^&{Ihputl@bI*~&(MlFkvn}urgvB>TNIxQoOu0-+)rPv!0eW;2~5u_WZQX}h8`^dr6A@T`Ii#$Tq_0UCDdIzNIkUwP@dk1dg*!ekUocc>zk;L{txPF)TDk!Kk9F+ zp#jGGR1j^@!05I#IC?q_iQY&3&pH zdJWAheT*K7kD&SS&1gaVC|Vf*0xgO^LyP_Ka_}vK9{10trT$HFyzDY9FH@aXl<7rJ zlvzqE%N(FpWqzX7WgF8|Wrxz!W!KU(Wj~;`2^u|{P@gs?%%n{T$7u5%n`ukAj#ON} z25qenLE9>HqU{yd(%Tg~(ymHrw7b$Xw72q1+E-;3?XU6y9k{a^9lUcA9jV%z-l@8r zj#mAajwP0-T1TFGy7i{zssbDY~H zU*goeUgq|9UF8mUx95)4t8-e-8k}D99{GEmGirXv>A$JM8MQiaX06vav-UfjRi`0m z*2(9ry0bX5?mEt>`vIrdy~x@1yK_#1&$)BMSnkrWDR*snl5-pF;BJj$xJTpK-1FW9 z&TF!mdo?-B`SGTU$YmvfAc%Jp!sDUc>jJL)M6wLZn2Vwwm87UT71vL zTUO%{Ej#nbmYaA~N_ifg(t*dMOysdCf8cQ`C%CZHG9KS*4^L=yi6=f#l_x!LmM6E4 z;VG@}=c%oS@wC>fd3x)^Jfrm$p4p~4&uWv)v)dH$oHiSHZrcG|)UF-RYxh0RPp!@i zQhV{j)Fr$qbr-cTHFEW)=!p8%n6jkLREj7~-6>N{<@pj#r3^78@Ns&E(#7QGH)%Je ziK!GXr7x(Xm|}PgM^Ohc>D-BHQhPDUJT-MUx91K-{z|@hpPwR(9O;+o6e<6SVrti^ zyUl2|&1k(|Y!T?Wq?tO#-ZE2^9FX#jk+ASD#y3_>&_NdC8)vi;A6>*;DpCae@{`{; zj{N=@qpi`7*o-JagdwiWZ0tcI#3C^mxx$A;Wu2eOQi6QDtQ=LKigK+i*D7+YD%V80 zCd;*&TdHR zf2Af+X+w67Ml7RbUosiK(!K;=IbV5S1yQh6K}_PN9np?z@0PfUDVa1qNADtkT}`=w zy^q5_z+oTkun%|GM?36=4*MjFUDBjG(*(EUj&#E9gooQH54W#8+%9^!UG{MM!NcvU zhubv|w;OIZBhtf7_i&5#aEteFOYm^3;Ne!q!>yW!TMZAlI#xF$gOYp++EHmGee?nP zV12kgS})Wm=|}bB`U(A%{*``FzpVeDU)8VaH;hO_H)4%=Bf+R(R57XYt}@mGi#z8nKjWg%$jKJWlc2TvL@PRSrbLBtchY& z_AT-)W=%AcvL=c?Sra9jtcku#) zEtuBBv;n4#z$RcbumvavwgTHAw;k94?1bCfz%F1num{)+>;v`#2Y`d{aR@jJ90C3W zyaOBs-Ua>);bXvY;631d-~-?Ua1wZ$Wk~!GrjLMAz{kL8;1dLO2Bx#Xr@&{xUx0JK z=fD@hmk>S=(_ewFfD6DsfWHBM2QC6%1K$AO0+)cxz(0ZS5Y+d;53v3STmk+CTm^o@ zum6VWXW$y}3-BM{I&ecoq|qHCW*`EH1fuYR571!M0Rz@(m|}ofAPy)6lm_AfKTrlJ z3nTz{0Of%4Kn0*8Pzk6EQ~~Y;ssf2X5|9j31MULu2C4%!fSSN>fLg#kKy9E7P#35N z)CU>>IZ~nA5SeKNYh&PEpb2mv&=hC}GzabnS^zD96alS)sTEAm0*fO5MD%E+%y{Pm z3t(LcQ=3T9&-Nrt55UwGSS41@=ibEKS#C$eAzTQIhTJ4z6s+Tc)$s8I+~&agFi-^R zT$siH6M(63%Z8~1FanqiJP4%V*Re2-1E#<_5|{||Lmd5qzOeolmoR3O6imU_F1?mCyBO6d;Lzo%?je&cCCcu68wJA)^U}_H2{Xh$#C6EHN0v-Tb zL#_?b7H9{zRG>Z30q6*%0qH;nkO^eL$AdsNkOOoAIs;vRu0Sq?y8+#S9zahZ59kFv z1mpv~fj&TApdZj5p$vej02l}i0tN#^fT6%JU^s+Fz%&vV1&jv917m=(z&M}~m;g)! zCIORyDZo?&H4T^!>kMEfFbkLs%)ze@!!#Et0_Fja0FMImA+i9bg}@?UF|Y(bJO(@t z>r&viur7mXIj{nF0$2$=39JHE18ab%fTw|HfVIH0!0&+Pfaif1fZqdu0A2)M0$v8z z0j~gm1YQMR16~K-0Nw=N0@ec?fQ`T=U^B1|6#C{O?l0R{pC&}RmVNxtaVTHxzQv`pN%Bc~A;p(9@4zcGK!=b69d zOU&QFw1GDg@8P|~ucL?V1g1iGHcZQ5S|xpz7w|&jLwuMRH%R^qpJV=@DQhumqR}JPtetk)<##2C`ty1ZKlJ9mt2Z56~Uf-Y|88DG$g6dH@gM Rhh9KWu^M?Yvyb!<{TJRy+CKmQ literal 107015 zcmce<2Vfk<^*=syx4U;IkED}a<%R{avE?F5a+QsZnr+##Y)f**wtSLKwrn-4xM55Q zp(Q{lp@vXGFpxmNu?3;UKoSxX2!R9=5(qt^gkD4YznR&+ZSPha?)&?P$TR!)ecrrz z^XAR$?Cjj5U)}QnA!J5)4JDavt&Ih-J*_hudOI6p+ZscJQZlA#TWe3et+=4Iqc`5& z5o;@`j&F@M?Oop4+}9Qlksu|5I4<5+)BtISsFdUwnA-TxzSiz|Y0ut{rrLNe4Si#PQa)NyiM>(-7~Z(nzO9wlny z-rjf*9r|~TrcZ5-m6gs5b_TLmMb&VyDOj3STDl=?d}J=8jWjJ7sbWDjP!^zrvdT&~ z13f2Q(kG<@y++cTfxcI#M>2rELDIJaeSL=HZ{_qBN$=wFGcEM(CVjn?-eJ%SBYQJx z6%B+`uE$=$w?-{`96e1kf+ATFYTgJcR4C5rldSZxNw2cfnMrT8(xWCl60pc0V$vsB z=_5>fm6bl)q_<4k%aXpx_1(kJP3Zs6cVNe2UGRaxm%OnR$T&U8~wM6t-9VbUjA z>2pkal};Ds&bP?7(oZz$5mm|;{1qmBl9j&1q*qz#)h4~wN?&QxBbr73dPx`UYo)I< z=~Y(xMw8xZrEf9mk&s1xvq_(%(?z|uNxHDVPH*My(kAKP;90F!dY4I$ge~^zHRVjw z>AYhF_eeUgSCy5%-=w!%=|@j9Z$u)N3MgjBm}I4gO?s7;&P;l%l^!+eku;0^Atrs2 zl|I6xSLt+NxY3f%4cBVrA7}DM23ZW0XYxB2x0P5vq?eTqqMwbG}X^oSnWgq#^B zeUgGMr`t4$0lb*RCVa8!C^HR8nm}c2?jK6>gux6(u$#3 zk*Z0tV*=?rv-fn2p0{vtB+@#mRB2u{Vf4E6jU&?{YUR+vIvS2?qi0WBKci(RzaI<+ zMriTzrDex=Rjp}WyBw~wwdHECtaL?i;f~zg*jT`+!**r{!pn+=^fJ&VH!Ct}ax6bX zRhJJ9l$EXy9zQs%e06d6jtN87O<`+%=CKX(e?PvH1aXhHARsVB_< z{g!T>Hfr9&Ns-7TRv8G44McKtPnt7KRogXD?#atab7Rv3dm=lt(i>*ZTv)q*_mrHO zO$#TSJTz81v#V5{n>%&vj4kn+ymjTJrOiU0++rwa>hQwB0d?|(p2Y=JZQ3z%|Afvl z^KyfQS!-8pnBLo}<*jR9SKK){63NL>gMkU!>fxY&8|YtJx@u0>daYH+-CD~Q7i^f` zvMG>8kA-qiIxuQ+$4P^N!G%g$Zf<^{aYAlZ;il51>d>6Zj*Ufa!SRt$&HC9}78h*{ zjV}!~u1aeIeT(C9fuot_#|~NBv92&)wRHci^o_G}gEJ+6m6kW6eO*!eS`F$ss;FaO zHk7-5dh_~e%HSA1VSH0*Zgycq=_$cXHg{^QD6m8uGkoXz(&k`hTW)Udfu@Z3Og*QR00;N0?(zW6Y7dFrGj_L)nb+6~a;Z|ZYx#kmP;_%iUwJK* zXTJt}YrX5W8SC0d%x_#j0rajYX)oU}Wq0-F!uGmsuw%J?4f<5Iu+qjcvm4uo?VkYU z$9n>4S^D*&g7q^3Lzg!XU%t6`ORF~DBDW-7Udv3mW4K*JeMLEKqvtmB`cBK4-?DIl zG6(D$>0CO5`&-KmIVdK~m-Y*w%KPy#Zx}3qoqnnGtUaj_P z=zrzw=k+e!JY+-$v~aKfDzDXX}A^6AMPoYgw4lJR902{UmMll7f*XTiUhe;b6B6+co%q&P+Btb8~Ue z!lhG&r*AkRFv@-n^=}>CK4xA^{D809**4D3@w!Wlq+0y;HGBy=KoH6t= z?7P#rKVj-I^IDdbK>0!LpMw^sk1PocjzBvZdI|a{-o83rmX|B&(tg27BChUh}o-&hQOS1PV~KbTr7 z;_tg+DAmpz8_pz#kazZ?d0&d>TslEAWTL%j;b$HqGo?CdwE0 z6W4&xI?oZ{G5hOef0as2z!Wl4SI-iYbV6D-9nF%B|QyG_pe#Lk!Ecznjzv1kHa;RFBkgb z7CsK}{vVt=cVg!{K0ZKv;C|1?g%Lcyi*YnC%6^?2%+29(N{$2N9CzIAnvD<-#+&rX zRBJvdd;g;L(Q{gkgLoSlTe5ePX4H6*-pqrih*BfMU-rj9P&QrQCI^oY5AaV>Hz zkB>q>?pFtbOID1@3PAq{KNaH`j~iQJwL?ZsrfF{cqTt||%Kb*f)6Si>LlXQ{L+Ro1 zrHCAe-_z(Iw|p7bwdD(@Y=gKF5-Hg27=0X(@nrf=7#C@i9Cum@z%Qx}1Sb}7`>GYk zw~v_FvrNky-nDLSV3hqjH#n8g6Q;Muhm8(*!ud*Ta*jL5ZL^Z4JpeuEefVH|<@ughbb3%8Z3dkZs1&*yesvwTcRSDg1J8Zr1= z;!F2KoSX^cV$9%^{;jpzufea%)}OGmyk@lCU#i0e>q~m|{?Y^Uo#D|j>q%7vfNmaQkz>^Sh%co4pky^ zr&6VAn|cX%W#y?t<2W{kqTl!D!Pyx%=#1C4V2 z>d`0kCHik|Y1Yp5Wrd+-Bj<+TIjC7(uH?XcJy@EvcEy;ImQCEAFb*v&%bS=9_v`ih zS-Ck?$H&H$2Gr%lY59zn)&o6j(~p5w-XdcqxpGfeTWeEmZ+T~XS8H2*MOSZYXGc$- z{j$6**3%OrnXr89jSG=1N(LifN`@N9u2|EK*w%PnS!ZWkUWg2V^>N3o5E%yR(BeKN zd5)WTE!~~%{9ZiPQQukJ3XA8lwh+moWC(VLl5v=Ts*YX@cr+zZ4z^M)bu~0ju&ixu z?%ft5$54`Cr%`eoR$5(ecWcL1OM%CNl{nIIgOc&vW4mGnZLyB6@Lph7=Z<*6@_6sI z&gLbtj^?&_PhNFr=Z?Ov5E&2Zd9#Md@swziAFOYAm5|rHtEp|rw&rfIem*6U#3d+Y zXKQY0i38JANj?-5%M*|%I5cWq z8{!?-``lmPei&Z9v^PNI!RHd#^0v;V9dI*U+>A9hcS{a=-5l$U$?M>ryh1Khs$SpM z)fS%vFr^h51}xpw-rUgLtY>z2gPsD)NixT2N^@riFh_cNyW_ET!Jn?@cn4TFA_>CMdVW_Ml$&7z3W9!96rCn-_O$MUYU&rqQ4_diLZwK2=FiLx@2RglB2IEqsXO9`!^cAUdtA0*h@;H6p|>?IJgNa4EDPMigD4Xsdp$~ zmGK<+SJ~OZ#wB=$kzED(-tIjef=x7Ii@3maYr^##y1K!+7!X^TyqK~h8&bROYckf$VAU%HqQcq2;ED@yB28X-SsdPlI84$hJ zS;N_k`PJr_vZ8T2ydR$T%_s|au&oF8Ufan7U}pC&ePC!8Z?`EKE@Hd>ZW{(9{WidW z7b?L=r)0ePZQxDUMH((u#`Oh9zJW^Qw9Ulqc@h)|RessHj|7 zzXXiLDT|i?b7|d@hC;C9251n2SXZ?H3>oH^GCQcOzRW7zxRS#8l~s5;=PrW=YFM*3LT3|%LQw|+)313!=5>+deo=${ezD_zvA7@R#Yzn_ z%2roZS2UC^DFdgehq|WegmqOjppPdm8fr@GtJc7MAk{UjtgYt;TvWQcx*oc{@VnCT z^2)k8VH=noxM*Nm7p(}P!F<8R2b#EOFpF@}W+AlM5NxdaRo0Z2Rab(B2o-chsGuc6 z1w9ceXo^rlSA+`MB2>`VRuT7DWI~v++Z0bK(cAT#l+Pj zD?-YUeMFWiWz?*eihvSQMs4NdsueYcN_C|bwTZmw%2JTfLsve%VtHvp+3H0`KuD9< zbq!U}VVQBkJ)V~#c6Z#11KO!)Hyf_s>j<^ zr>v-{hT0mCy7HQehH9|C$shxop-EkRX+1v?r%I?a66ezv>mG6%F+(8dld;Hms~(T?e{^s_Rx4L6n1u0OU-+F)nn! zF)oGQWbiBQqcvq*B7c^*5fV|Jlj~qYBnJv{Rd0#BSv4yfq`&i&2T;&rWmS1YQTh7v zYPd+}7iFcOEuY@Oyi8mRY2p@y;)b;=YAYaW2%OP11fL8Kg0Fr>eQ7lh+|Y7dMB>`8 zLPl*RO!(@d$LrIi2v=M0Lxc3ZG)071(Y?C@dqW8~_?knP{D4&+~>ex|A*(L^N6r73Ys3<)x5|Ld7ksDEv8O zgM;*c`y`^54BC&eYwys5(N(mTs|)TDZiF?XBG{Y@wwkzM5(M&yK>;~gb~$jL(Y16P z$HI`L#d_L0J76V7nOHSxDO6ovyK!)r(M@zS$2EXq_ybX6Z=+Zl*cR*A2CICg1K{lw z;OjbBP9PLD*{-5zGc(#u<6MarSm1NYYG~=?>psI!dLE;#61v@@27jP!kQK-_U@V-r>0y3Ig{l)a)p$AlQ9KADEIJqh!4z}7OyMb>(O%le4YLad^6p*n zUGa{Ft{ALT?QPl?Z-QrSxwglPk4U;$cNy$vg<791MeT=L+wO1W5A<115&%w>W;zXo zckgQK1`EcahFWJ!3vBs@h?XD%@0n8gw_!@vy$cpTw#Ic0$4#tqby7?3D}vs)U;vi+ z2^)!pRQr{9*5@-AInfACk z7@WWaIt5H{i8R5bFemHY1xt84V9~ri*4qT#sKnE!>=kl(n8Ia2XXdLdV19ljmSF6K zK+P80YnBizdTx>{VNpksj9yKD!0UVs3`e~GG>J|9eciFfws^zV-IVMw>m%2%6Vfds zNrHy7n%6ytHqf)=vXWQ|&W`Wtg{aum-PF(>-`T(yZlG(l$6L4VZtCrBYv}516a51k z!6f$X?TYhpO>nh=4-Y|V1qR%c#DM?L>&WOqdNa59EqtzGgddA7MYoDKHNnbVQ)e?& zCfLk7J@~ds1Q)zr_Sl~#*qh^$eTms%UfzJ*bBs}xobi7o%IwuhsR^-6qKH_pA{|Cx^e%cgZ?0d!Ba*cV8fMLq(KXRhK!J9- zPqxeb33jQVVD}jtgvPF}!6P}8l@Rw0qW~tH(Ff^6ypj(Kt<4zPz#|$&QNv9UTUOZ& z#$)`l|ApVvHF)zwwQc%9wZV**w}7($ClT$LhKaBOY_2$9jPH-Zh zhmB0i0a`@uTJU+<tS!zEjTa)-ZAvxtg;-%g8kn_zwtl#)39f2PU=_vsjk8 z8Tlc(mP22FIhO&*YumS%tJl{X=WiRK!fP0PiN2f$e6I+>a`hV%Y^;kjaviyz3;wqd ztdp&R8GS>Fd=vVxTtkN?d6%Yg`J9m($d9Y?*`1m^Wz+B`4Ww|A&tNTzW35n(>Z;YsJWovIRe7c#nTs%TyTAqpG4eA>OK0Q`Ny}v9 zPD#sRlt}k=1yYd8JXL}$X{iyfswyS zU1E$pD``!P{9WeajQm69wleaZ%(XJ|yv*%jG6#P4l9b%T$jg$} z$H*%(x0{hyWo|DcugToWjQmUHPGRKVGIuH?ugl!&jJzRp-(uuVnfo>)Z^_)*jQmID z&Sm6nnfneS@5tQwjJzvz7c%mm)aoKe-j}&c82Lcn{XQcf%G~9Qd?a&MGV-y^UCqcR zGItFlpGxetjC>|(*E8~8nfnnVpUd2j8Tmry4l?qk%-zDsS2Fh#M!uF(Zex^4+RxzA z8=1S4(SXeToYA1n9br_Fh`Sh7W$qV@YVz*AjD}?Hen!Lc?k^dQNZNyprpesHj1H2y zUo*;N?h!`QW$t&3X2{&{8O@Zr#~6*u+#eaulDR)Ink{orF*;c0{=(=GnR|xOp)&V3 zMu*AV-x(b)bI&n4LgxO-XpYRi$mmF!dzsNuGWRN@qh;=2jE<4H*BKovb8j+wjLiLq z(Qz{O4x_m;_a39i%G?Kx9w&1jF`6fHpD;RJ=00O|g3Nu+=ebGCD)% zhBG=-=5iRFC3B+~oh@@?7@Z??$1plq=5iS=k-6g-ohNhS8J#b4$1{3@%uS-?SUyI; zV|=XL9K6KqVfpG<4qcv1)hi^E7zi;*=DT3YI6g^{=KE*K$Jd}>6g$p?oiArf=3|m@ znH*>(_`B)>Yiclg)|4|jYnq2C1&oQ8;Zk=`HnReglSp&EI`b}^FDkoD> zNaOF{eMsZ4<$bX6xAnf*3~6Z7gOyFop&n;@J)U+OIXtg|I+{s4BZl-nTw7iQhI z{v_+x^~bE+*B`TPVSmiJjr}p}R`$oN+j*dd=C9hO`)fVU>eGKYt55&stUmphv-DIjc|q<*d40vA897mKfVkq*2FVe$E%A`AbI0f{o6OO)3L0n%f{GV^ZZ3TUsO^ zHtt$>x=1E0sya8o44|L6V_*RN5*rBy&`-WNl}t%3%-;YE#FCh#By9w9D~^#NBbnQLB-1p+&64c?kpQe3`bHMHDM+$mjjyvM z_6kW(%;&6}#>`D1um;R*)C%3YXBw1J|w9m7CH@~mhDLc*WK8)Bso2F65;71Oi|ZBu*$CD!wAkkk2#z!nD=^ND33;$=mChXpPBz6LCsukKoW z$HRL$r`>ft+L|*P9_G;<^*v=$OPr67WA^b5Z)Stfa0c8y2A91eSbP_|aLf@DZ(3c~P8)%eEY^ak>l(Z<*FVP^8*nTI)pe?BL zc#le!&3aN48W){=`24eaOg^o<*7&M{$K=z=>M{9rvU*HDova>{PbaI#eGKYtA|}(dp%`b7>mqBU}GlV0xB7>kj8gz%H5EX z2McKik9SBjxDxMKvAEBfc-WWQOJ$MRJkP;rnZaU10O!^>qe_w3*d&tr1clNDwTb;-0g_tJ_19}7#!mRqSA z*7)|FxRMVWi4z-iB@5Q#mVLX)En#lwO|FxDm#^gG`+K1;Ilo|LWDc1NuaJYk;ky+a z8%h`{A@lgn-`Q`99bAmeCnxZme}L_R7Np!A#mEA(kl+0yBPYt-pBO2Xxu+PZkb?ih zNTtj@!^k3;`x_&RW$y2cERnhA7^#xEe=@RE=3ZoEnasV+NVUwp%E)q=`xhfMQoq+3 zSs`<8GO|+M{SPCnWbPeCYGv*{M(QNr2aMFq+((S8mbp(DStE0wF|tFHi?l=nVZZ=m&{FNWT(s(Fw!k^g^cvbTrnfPQp!w5`ebf4BfI3?xs2?Vw0Vr| zk+~BX*(-Ak8QCXurHq^`bLEWem$^ztPLa9Aj2w`;Dn?F~l9w@Zn#?U{;jC@<>)-rOI%&lkSY>7RIk#i(%6C>wJS_32JNm`7N@5o#eBj1&G zsaxrX1)A#P^ zG{JspM7c!yKI{N8%7Hzi@>uJh&c5!Zcxy*XXF;9FR=0MSVN!wm1$O_OuR-R;$p_7>ML*?2u(Cs>3x>bRi zA>{`6Fv6%uk^@pg%8jt6DAAxvxP)nLiYPx;4nkddQ#QfA?OB%Codk#+p#rjQQEp8G zSwDfz_=b9R#*lIw>^wE@@qK|I1@@wbo8jE?t}br2TI*Kt^6vGb5A zcPfX{lslB4gAZ?OX$dPwKnW-khI{#cN;W6keVDQea%5EQQtsv|z1XK1hb zPI0&l^yFOSx4b9AL;$`lA-NWxN!YBVwY$5wtw2X8zgPZ{M#d?RQBq)<8)r7l*A+ic z`6G`Mut_rEKHRb)S@}zv@|5y4Q~oS1`B!eq z=@1v6H@8Uw1bgijp|R0=kr7g1zt-gDvmd13?wG zL7E5CaFPfDA4Zf9l#k$mAJ4Yek28YSAFF)ATmREEGKPn5-h=bH+WLB!^0_n&Y)IT^ zwz9o7D&Ru}v-jGsQf?_Bj`#Vm(x6ITLoAXbM0a0DZ)Uc*F98NWz$9@ul3IIl1- z)*S2V<@?tcm^KwXBhgRgl{qdah8)X2)*>h}Q;ouAT{SCHQ?sE=bd<6|qUw+!{8B`S z{{t4wmN)C--L0{<)_uG>A$0^uGK$T7* zIm@bo$DvZzqdxRWhh;dm0qfy&j(I0p?k0@kQnEbO)>a1x`+#Let7FpCQR-N*%rUkQ zg&5js-9>#JqHPPoVeVCPvk6g;h4z;=LYuy-qdC4O-dqP`Pe{$9#Mo3k5VP>e2@!R? zdOYvav5vC7*0$zFa7Y&=lOXuIiiEGWppBXe$}Ox=%Smc}8VH$8$v79p;h-UPDnzdK z7z|9+hMH!DeU^yLdDH@RdYU>-g&pMjIb4?7gJr5)cYssDhWb!9e9_k313_^JRMBia zWAdcVRA&uRXQ=RL@OY2fm^Kfob79lDF#!=%N(h1Fu^u=_Ooi_Th9~-y?Vd3H2@!R^ z3RA%uW*3y9%T+Q|!7>Ta1Jb?fiD@996h0G!^Rl{o28KtJtz2Uej7gYbbfunr>|;t8Yxtl!{&L@zV+MS zJT%$0SEP~2>hd%)jk9DVLR3e5H~#=2SANc5IRwp8anWyJ!jmUI^G!T{)W)~gK)3{p z!;V4op~D~xW3P*-YgKsenjic<*Zm~08lNQg@PUMqm1Yy9JYL9=UEQQ^hLK%`hq>ka zp(LQf!(6q@!NXjM%z-0jfEs-rvF^PMd5sXonYxt&?@-~Bmo`%?`cXKO`QTIqI=WXqd!%=zNFh^(VJ~4k*PiD#kVhX070^_oICLdEz z6^~KsX%JHK+FLvNdQ7-6GK;QjI=LQ1++oECrs51eK4zYwek%Z1yNDzsSq0VEIMnegKOkGWSDROp&nb_+;-1SlyAAKjH(=26Luv zeNy0UY&`%IqR=Sy$1r15Zvw|FW9rRZ_(=5@ro2Nh=iTimu!1G!-Uh29vgn_|>WIwU z34y}BRvA*^kuFV~tR~JxEp~VK5k3rlUo?Cn_G7YU;MT7#oxeMkVL_Q&{OI*Sdx;LzlVh$nR^Tt z*`&BXIyIUBt4osUNm#X%On>Gr2@&XgdE*&a0+YGF!Sa;M{oN^NrjsxW7DlDGe>!i$ zirW%->m^t#lLB9X6*5VC4c7c*?%%NHC-1(&?N$iuKI&V1O3j~P)wj9NfEiDbEblo> znFFh<^45p2sw*Xa>|}yrI5QEo#9%TV7F#6@zG_-4b6>y`tIU1n;)lh>dT~#qu;?mt zK^GTv(c!k?9!8nU4nDNyg)|L5Q?n2F=3O5Dv~WZVX%UE_Fu*m$cDFV&Z4gvQJ*+YK z5RX0vj;m$ZzTUQndi#|Kd}egyhR{@qw#EL}%fToJ<=n`CuXVB56IC^*Y*QmWu)|)CD-G_i?U!(D1wDy$P;+ zb79$6mNLnCuLz!)?By0g+wPFuFavemD}u#mS&AD6CUbB@H#=EM0xLQ0fjt})sILqs zF!D6-W!fBoLSws}wFoAh4(J>MDvoJn+6fX0^F;?E2$QYQ9q;L4TB+nKbMh5K?Q~t5 z;c=O1Ja&UFi{QIYa~N^1eDMjLwj_-xS``$-Bc|9PAJUe=Fq_BMGU1UULylSE4j-+w z4)#D!b`hXDIL1Y*2gRj4`6a3@aLpi+rmY2S;M+^kdObwb zsueb=!u_4SK|4v?$en8w^trY03xZXkF^uSzSuLkl=%3uqV_Ji@1x6Ju1|zZ2&8-|E zt;x13WbcsQbl6SAj6@fXr)kYvi}m@z7!7%+7fUSKwg?%jwZd~E_s5~y4uJ5mt!z5v^0(35{p4i??dP-viV7ghG-iVpm^8>(zGg;vP?f+@3VRgNBLX z1Zzk;8Aet^q=6Epc^CU4_3Tg0~LD>eKkZEVDv(mJ)G?+>a>TS!5H8sWIJm*5bO6j9)?L6%} z9Q|EbG509D1{QEa+68>Yd;l&{|L;Y#3$=^D?#{_%NV^338T|NVtPPrFsC8w-Sc2HV zwC`(|rD>OHm&0?sEKMHP9MZ0&*@`HIp z+7FY|RK%j|(zI)}>lrB{`y%sOu-P*g&=sa-X zg6ZYv4bjTKjA##NFgIQR9SBr^D5}n4YMoloFMge=X}^gEf6M!T`vE|AB4e#&y66MH z%O+HN)V6#ew3z4O##TC@6a66#^m)v(p39?8Nc$ta9_0}wp#2HDh?p>RizB$1_LLl3 z;Lw03IbuEyFQsMfug0XNn@?(+sH5GQ0`zx@GP^@RnNU-hnsaGWVViZ`8H_Kxz+@$QoI{ zkKx64o(!PQh`~m|%YAY+E8z&SH;zL1Q6fB^_ za2!$vETrk8xOGBdNrQQym}ZHCnOR6q1VbO1 z@U~x6D>Muk^wY%Q^cEHxAsKRv*4!=a5gH}wqZ4#p;8;nA*_$ZdV9%9gSdNrrojXsG z;kAB)@axd=jJ`(y1^yF)nVH(ePn&0<$@1P5s4{f;js`fvIL<=TB({K(`Iae&IG;W- z0*Ohk{mLBVrNhIB5GsUarBG3twx2(sZjq(Id~Bp`D5`@V*|ZJj6}_-r6biwlYmf{- zHE`^AUMK`psdT;f2nz4Ep?Q%|NoYPST-Nb3s0J7%fCq-x(1OrHSj`We=siks=1>S` zYAUSR_3q`X=bl3l@Pq7%P-R-EJhX_CGSg_4ZSi(^VPo`t`Lhw$$u{nQia7RIkT!vdW&qVdjy z4`Oo)mL{T=js?|MhE`>R_*#gi{G7fMlj@(qT2}wWoWa(DAhABQnrjd17I#b4*MaKm zvq>;i%hW$f(ncU{$|edYJts+9fE3FnDknWJNzFitXA_N+UX-M5Kx)k0lG=dO zo=w7>^r<9u0cmG8iSTL-w_BpD6ISL|!;~`=0@qPi*HppmHpgME1QS$eS7>)6)EC+V zdtYP>*ar)=HWx0Bai7@_tE-7VAq>Om!d(wULZ^gIWy-6xkvHY(z=^!M2!&ww1iwlU z>#B{nz_M2iyl?(QgwbeRiw_wuo#ZR5W`PFXza2V@`~2Cq5vi=Tw+C@U`+~Mu*X5n~ z+%(YrJlNzTD-S*ST$#IoDW}N#d=GqQTX8saF;APqp-Xw%5)NI)gDF2DUknwYD*&e+ z4qXXbk)(vHdD!Cj8~fl`FBZB+GQeDe|L#S@HvS6;GE`kBgVObez^?92;Qx{2zfp{6 z@P0M~Qw@C_lMFXY2AFbWnk%~SB9F(ppNO^K5X?WM4&oOXSm<^MfmNvv$U$S>2|ItF zbjbZ2;ti}Xg+oVR3y>t;1>1Ne8?2RlSLR^JX|=oy6Ayi?*5mRoWi^f(gA6}>pM@Th z)Q6e+nV5KlVB!(_O*TARJ<2p9NxuWqquFE-C#jP37?2*%CXAB?OVXc!^kg#)B1JQQnhiZC z%X*$^!=-*NfPOD#lMJr%C`oz+NUvs-OdyfVV? zlEq2mCFy-2eUMGEIccIKeGH^evdLghnk-5G1=8o)WC$lsk)*GH^mR5orU9uykivmX zEgZ}y!#Jr(k~AQNvdM5xDwd=)APveUBRFZ6BxL|8Gn?da(rih}2GZbcGLn<#NzyPN z4bLW{fJ9CdwGEGC+I)F)G~67MO-6J66D4UJkl=;m7|vfR`SX}oA#YBAo5yF9vHa#G z!sEjEeC7zhUeXC~)L>c@XW=Qrxx!OnN10?PfE{HrSLi(w@&~(6xERK3cL43F?dzzA z7ww@ijOS^69gUrP>N{b1Kgm-<6${S}&q)i<3eRO~JN*qfW_TWdE#!Q*0^;Dj=6H|( z;yEr~FT--iZ0jSF{vOzPJsoeBY%ne%^7KbSV<42Q6=o5kFw6+}v8wP3HxPOqPiMAQ z&h{TbO66TOBG#t8e&2j?9WD!(r-e(y70~9DF#fcO_wJTzu<+vW!fbL(cnQ>|4u19} z*4xK_qC_c&Ssh<(fDLaoeeI3$?s~p3%8lRI6l+@p=OprLofwtB^t6&6KN5%6GB6=X zuj_>$%UT}m(pgwl2fTAG=fB1khudj#KOJo51DQGC7JUE3n%16H5L(*N(Fs3<#DB~S z9x5SnNE6F4fRtGW8pNtP+CVqHMF$>N1O?P5xg>6m|-W6!r;=6m|)Vv`xQ;9m3)o_6Lg;b_a_T_6Ca-b_RrbR`h##Th zrH~JhAAp}i6%{)BE)l4tx`QaNL_n;jlN6!clJ`g@fKi3dg*O6b^Y4>96$^4tNvSkLc-d^%RbF z6LdJ(O{8$Fn@Inl%Xv&s;XpS*|D&G5VQ%6Yj&c(z9ONd_r}XsCdiobVeOgbS(Nj3Q zP4L6fZ6bw(+eG?zJ^hECKBuQ}V4JuP$F+$R4r>!B9MvXLIH*mea7>#>;gB|w!VzsE zg#+3|3dggF6b@$-DICovQaG4Rq;M>oNZ-=a|L7?k$R_CT=qVh=Ca&QqHj%ZG zHIc$GYa)e1)1aJ2qo;6Snz#?grHK>{ zOA{#^l_pX+C{3hrOqxjHkTj9P5oscY1JXna$D@f94o4Fy9E~PYI2cW&a4ecgr|9Wa zJ%t0&1ie5{r|b5EqtFB$4nh-Yv7XM*)0uiYOHXI(DI9(#_~Ga?k;1`eBAutF^Y!!u zp3rBk zB}^Ci0!b);)RepFavVNRvgmMNrb|E%US^2$89*Rh1Nle*$Wb6fp@bT`LNCFpUOg_~ zrk;%EbR`H`P1oo`N+7-mpbRa4)ZKK$Pa)^7A=msKBq8l-h zTW<3$5-M&N8KaFZk(2MHTk*QOwd8Y-gvchLJ>M=Xfk-w zZd|6@i}fgJByVan%hLB02#E2@+p1jZ<^MByec_@X3L`#xT-yJ~!%CtKWB zwTlx~yNq70`;=L=$y1?I-ikC2RfC@@FKQFFAr>8*INOC)E)q8aphn3?jLWzZYwPeid9^hdl{LAw!hyqz-W zk0Gau+)a?vgi<*gz@zjA`1=w3-3Wg_hQFJHf73jPCq3>wxs1Naj@INF9-06&Ra{x7)Bek{+o zeYx~GOrP;I!bSnx&!zAFWO00Q6r9|e9$Khk@H*^ZNs(7*d{$E!gh@jy>MwzVhy1b30= z{EK$E$c(@dy4n3LfSU zd>93f@CQDEf=BuT_oLv^{=j#k;IaO|ccbk*&L8*}DEL@^;CoPTo& zC;9{5kAn04fgeD@Q~ZH{iGrv310O}f)BS-TM8QS=zz?C|8UDZzqu^Qoz`sI0Y>q$h zuTgM`Kk#o*@O*#ZM^Nwrf8gJu;1m6Ue}{t0{DB`u!4>|%zemA~{DHBjk;8!{{=ko+ z9=6mU_;D0m?GOA%6kOvE`~(VK=@0xT6kO{M{3Hsl_XmCo1+Vc3{xb?*=MVfB6r5x| z*Y-#TPft&y;En!Deg*|^_6Pne3f|%m{5P~$HTnZTiUh_ze_%ra$nTDEKUY;I~llIsU-^LBZ$w1HX-e zzv~bD4hp`&ANXAq{5^l*_s}kRu|M$pDELx;;15u>FY^cf5Cvc15Bw1dzRDl?V-)-Y zf8bA0@DKfgKSiy5oj>qrXvsJD1OFEV-{=qgISRhXANUIte6v6BmnisFf8eiB@K61L zzebztc3)svLPy>(1n%$$rYQK3KX3pAANB_hqTqgiUn$n4#d``U9t<;79#|Gf?m!{DCu3@Z+2nznIKk!f#{H#ClFcka`f8gOL_<4We5h(Zt zf8ZPx{E|QLNEG~vKkz6N{F*=TXcYW!f8a4F_zi#Hu_*X0f8b+K@Z0{t<52Ls{=m5? z_r zfQuZPg2;uqUyk!H(&d*Y;v$btL1ZZ|GA{*@Ww|H_i7AMzz(wY#AhHq{ zIVA;=i*S+CQV_Wq7dbrzkxOuqMJb4^!bQ$VLF7_g~(yZRFUB3&W49v8VZ z1(B<9k<}@PT!V|ONkQaVT;$3WM6Sa{)}|nGJub371(6$Yk!w;Ac@i#iT?!&M;vzSs zAaWBfa$^c2H{&8Vry#Nc7r7+`kz4Rc)aYNNYdDMHS~mL^>54>+xX6|iL^k0fx1}Jm z85g-d1(9)FWLpX%TX2ybDTv&Pi|k54H6!$s~(L1a5Fa(@aUJ8+Q)QV`jRi##m_kzKgRGg1(_6Bl`A3L?94k!PhKvIiG= zP6{G>agpbxAhHh^`P~#m?!rZ0kb=nFxXACNAaV~L+%EPn(iPnH;vz3iLF7KX;+Ods z>57*p<07v}LF9g1R+Vmx#wk2%2$P%!)uF9LqT z30{bT;V0D)@RLsPi6|I;Ukw5O*$FO1!4;^%o_2!EP;ey*{;NOmA{6|rKk#A{{11QN zB`ElLf8Z(<{DMF5QWX4>KkzaX{E9ztH41*s2`)$5c{vLHw-a1}g5md(5%+w<30{nX zSD@gxoZuxW7=BwBDfw+DxC#Zs?L+kvZ6I_jg z>rwE>PVjOR3_t&gsQsxET!Vtwpy2;H!7EVkS`_?+6TA`yuS3CKIl-$?F#P1WyUq%6 zf@@JQ{I)m(4miPeC>Vaj904m%a6Jl!pCw1YniISl1;g*0BjB(Tyaols4}&A%G$(i+ z3WlHcM!?JoUXOy|m$(sdh7-I21;@IEK_2PpV*^wDU)6MPK@R!%W~hfaBqWbhvkRIWXw zoH{U-|AK>VD2jO4D8jAa_0i*!qosnsHqfSm*GKb{qwaAU z;ri%_$+=}2k3boqYBb!hJld~3-mm=0TE*+5i<1ku$IdxBIp;GD%UvIhCT9lAnf1Lc zx*$2{--M0-E^DA#D&V&E4FkKwb8c(j5cP5gr?qd0Rwma~TKk_^8P&;AHWS|vou8cZ z8Mii#$+@LAFM7894bj%*0vw91PtNI9EQ_3(oLy@6vbSbg} z&TMnb>!X{JbN+3) zqn^sO#;>O;*D442Pk!n@ZwMFgbCt@gMkG{UlaWw8M|6UJOM_|FPM|qm;-+X(a;>G| zk(hW>bZ&B#E9Bf1U6q_$mf;<8Zi=o;F2L5dH$@jE=XANgPsjeIb=Fu7Q1 zRFeymXJSzL?GnfM4uxE1Lu;P0*A@X!MDjlWdylJ`31QdLjA4kS>z{)@c%Nok@8=6 zhM&h)&oRQkdXDm%HT=IO!v8zQ51-R4k|su$+YTuoPn`_*QTmn7`j!7$Cr`IWXCyc3 zmjE*R>+R7INm*5LRJo%>Ii#w92==QHm@KO4Q*xAh)Z+*_q)zNtr}V2uN7Wg>Q0Gu` zR4pk{52*`5r)Wqjm815nWgx_y?TcAFxt+9-Afgj%6i zik}p}&9Dl&O?j7F1?+p97#{ggir)rL1?Dfe14EP#mOzX~OX&i2k!vlqUv;fimAIcf zqNQYxT7`g@nbpvQDhQZl)0gPWIyes1;fjvSUtj%@{B7sV{Ci2^`uw}pnj`eZ$qyeS z+T@3Sc_&Cy$Z#?mc;)Xsr<33pWO#@KDnjZ?>swuGk>hmhWYag2774%p%!{1Ni(GYt zzW#q!I)*hkn{@)ZC%~9*rdU--99ZUv^26+9Dx&it@e!sfWbn0lO z$NWIu0?du@*K7kMpC5@%01uiPU|MXLw&WeB)i!>DLLO6cKGX+gchMhWfqyE<)*oHf zHd_aho>ysc+t=0Av=V+Fz6QKUrRwTv6l~QFzdIigKmYy$*b1JU$qk3p9?(C3v{{KP z@-vS}sO|#IMsv;7y|$R~GmmF8b-!Kw^yEf5(663ul%V{#U;Vbddj-kQj7Z6~S398p z^Z(tTcIuJf2DJ-**F7LAo*o2-DBOwyksIJF^=xSXn4 zbGeE8uZn@y@N$0t8h#)Cc>lcATHMJFWXR1YM|el0o-*sNt=%gavO z|5tRBxx*5e%;665hqy#Y$O(XnFndUSJAm4$1;(0j07y|rKcDWGpx zZOdJ+dp(@MWX^Pk*P~;T79)aOqVlhcIe}pu?hJRppJ|*oTn%?f=iv=!^T0Qw#Yqdb zH{6>Z4>XpBd(+i$%lg&3_(C98L4;jcA51L2nbm(w#MC6~f)6I@{+3t@NYvfjEjkUt zC?PMB3FIYmGkKZjlUL{g@+$oyc`Y!K{3}pGUJuSDZv@wpH-k@+x6Jsg%)sLF-9~r{ zts&_=JcSrkK=1ZfK=vYgJHPAI1H`0Vg-N(G{=6GK!KeA(^@vpJ0jnRq8?8+$Q-q=W zK>G*m2)|+IU0cX7!q8C=_>f|A`}e&3N}A(WZgadBElIBWBUY8)^9peXK%d{)xtAoD z`>35W`O<~O%ipuvfrrLFz@HwHO`m?>V^C6U<-Q*sms~?LEWR(+XASS?Ehtbj#t%mxT{nG25oXuiiMhlbH&f=k8x?+YtS+hCMS01xW5i|Z`jv+RyeC6R6Dq@wd zq8-V#PC6g_%IjT-%_?6-W69;il7-oxUuBW=lCr8#LxZ{ooUc4q;Pv$ui+tY?v0u3y zkk6Q09sFyLZmT?#7;?V0NlQGQ8uux2J&F7kN_#4CpGNsE0qb1qS-78=OVNPq{y+GA zF2iD88uXf&Tjwso=@GaR-4xiIdSP=*s(5u%Te*ryh&P9L5Xj&CTkU}j;Z*e;!ofQH z8Phr&0ffh92dh&9XY%DJ_PPgL^Uo z{5~fW!0B@x066)(0i$MoQkG;g;cAkQ=S1FV=#aJXa_Bao8RQ%oTxI@Ze6!7jz5xGO&Pr6?~C=trWmQ{t8N!P8v`yq(L=A z74=lAYHO($Dx{(Ca2htJD&aZUROLBisuDO`u5t&eKp$@62NF6ln@-7}lWF=lc}@nD z&*x;|O#Z&s^&AG=KA)3;)6a7=a&7ezYCf!D( z^f1jb{WDO7`RDV7f6}S&zLUR^dk3n*{qu!{Er#0cYV}Xs*fz|o7KxFV4zo#fkHo_V z7>P%?yudyZ=eX|My=0`le5VzMf)$664mzA%Ku3_9yZZRK(+z6yVQK4V>dqQ`iQn4%Bb*Uo_7WA{L^wHZKp^hoR43~(kNWi9i8 zV_f4VpZmO;sQoxw?Rl%)mgs4&Yl+_8YR9_p`nde6b&xpDtJiJGhf@D#dupf0MOP=E z74U)ib^G!@0JeGnAS@`><^6xzmGe7PALj}_d{W2Vmesqcu|yO)D0l=h?Kuy^eRc+3T# zv2!Nh)@AYjJlAa4@*ab?-TPLd<2~j*immwZ9+Mt@hGbm}N<3!K@m{g;;nD`HGICV`(m3K#!%H>2ZN&G%xrC9dE`&

rNKQLk<+eWhZ$inzbcODhq zhrgp%gG};zI^pZTwsB^X$9p>SiH}ZlMGU^c=qfwkV?H3_t*z{QuNfHcI1cWLdKFnCFkT8_{eIne2?9k7O%{=S%8l?#v+GP;AD^OgSOQpI@xOnw#|1Zdpz@q#giBC z#SjJ^PIh^LePv^cYrbTkPfc~*cW!``a;r}BSPfAU8!AA! z^SMB5J>dS#4R19|fmdwc&BPJ5W-9P{)V2+p1s)D<58DNvbGSsy6u9P0e9MIStUBE_ z6Xrw7Q}D-UjgEO>p}%<`jGop97jwiY^gSai^qdibW=SU~g&yy{L?^Zn6uG*E*JP^Lb1G{!X|Y$;obSbGvDXYr zz8Ax%Ud0|Soh=Jh#rCNeSXL}{=oW^t(d?Qtyx#5D9@b{~TQr{G3hC&h=u9tz@kxmz z1kLmpg6zBM=uF>%XQn^@nd$N${;0`oXnpZXXL-(K65cq=^s|K^T87H}`?biOQ?UBiHOKazWBCfW|&RT<3wX#Xiv5_JBIu<1LZ%MGn-@@6+sT z`_rts;IaVLN(h}q_S1ZNfKCpcNv8yFq*H^xqSKT`v_Kt8r>hHSVdy)wC_IxEM@G>Z zk<01Kv_3j3?O{6Gd;nn@_5kv!@c=>|CLyu3C8oeo>rWD`JI^+?FqXDHO5C4syU&*` zo;6LF;5xz8pZ_JCv_uZ_WHFQa8h!B?OA85*XwV18EJH?gn74$hc4sI z1+syfTF<)q4`MHkB)69quvTN6N4K@xOSA3-pxeA+G~b*H2DaI2TeQWey|zW0lX5DU zy|xW#FYEC>sJ&FfUgSpjLWM62?>nTWK^>O$Yw7v@TBg!$-N8p&y_TM2v@_hy=ANz5 zrlfUKxAbe-?%nd#dc4p+tg#0tl)qM2zAvHtF#G!7c8_=0;GTL+$rQ1k4z&og;IRosuGbaW zEfmr6kj~cSHRHB-Hk;;M-=OWSM^o*_G#{VP{0F+`-BR=8ZF_uaxBm!XQ@Y!0J7bav zVLjEV8&i5>LTP)uYxX&vO_83c#{ic^5$g$AXuD5NC~}Q%y&ma+&go>Y?`~uF)?SY< zGLw0$^=Pgh%zRT4T06`)&DL!mw|1Ld-=N#|QfT>-lcz%xIQjFJg~(>h<=S z#XgUTw|#(C;S?ORk@tCQ1x(gq_gVT08t-N&l->X@cKCE|Iy^4O>0F8FaETfB$phNy zWJ{6Lu^2HgQRG>AWZP&IsorHD8ut5~%Oup>KcITn!}2y_>djB6=e7v{=2@TjC5k*n zEC+dcj`fH=)FLN(6j_cGd0@a=S`X$!i>yc#dA8mNn~X-#7DpG_CT6Glbl8MRP94xB z*0cXMxmp3vLAlEK?6~SiGK7pGr2GLGf%zFvcWF!W@77krUoHHthQD?B`S+@a*WaaW z=+`zMRSzEtKEg-qehpq~iROX?J_Z%XAE`I!T1Mwbb6}#bx0|*V9w&|j`C1=*{Of4r z=n2t5CaZeBAza(uueAwo@!g&wc!5~|Fa)nfAZ_N1Gw6k+=_u$>Oy@@r=YX2Y!-m6`^e#%|i z4ZoaxM7uFR|FCvrzjjc#%hUSRt>Wsh`qgdX>RJ8j4srDl{p#o9>UsUDUtGPQU;RQ{ zy`*2=C$3&Gd@bR~<|n3xBbD2lUOMt?K5!K_Kb5$DLkDO+q`@9p?cw};wBHlbuRVTL zd%`HIGMfHB^n}IY=o@=ac*D>vN$**LVBRt?2`lhPoU2DyA%=L{1&yBQ0xq?cDJ}7? z3kYXjI6}xWq`>zLT$1`#i*4?9n|wF`W_k1&)9RXxC?5}isSz)K?B#qq0A_`)KC+zu z4uDySV7?dtvkKAeD+A-*#dP^3*8-2Gh{<_5akbPJ;F2p7=peKDlK zkv?#ZNDW83aEK2z*&>Ft>R30>?e1|~c#^rq+JRJYnhT2fcBieL zvH_>NfyQy5W(#&9E>q+Nx(&1wDRG7YOwt9{{rl(Qm;3n7!gfx;<{6H~?m!%{8R$$_BvfN90)Q6VRZ?t@dG?Ve8^x2t~7wSE5WWp8%Wx* zb|BE1)>p!E%BR#11Ud`xrZoeB&PH5g-9VsoY<)`BX@dbuw3%y|$Rg+3N|UDFXaJL0 z@H`txmbTddB}#Ko?BN($8&Vc04(#ERuw=!ZZv)BV8ja$Tfi6Hm%?2o;BQ{KAkqd1- zT58#1V3QSi5z^S(1_E7-Xt{kL&?QI*Z5s%5DH07k1_E7%sMlqH5=L~7dRgRhWc2Db zkjYGVB~r28fk0OwI_??>bT!ggdjmym9i`8y?+t5Ww zHIH~!6P6SQYtI{B@xZwU?r&Pi5#JgeacOirqEWxs{y=W{7wm8ANq;o?VG&~g85sR# z7bf{WcK+tWGp28mM~qufND$K5F-d?X?a-JWdO? zRqig|mAlJTxwoK#Z`*f#kh?{w#f@ctxC(6657@b--i5#S?Th{77h+@|P}nbQ-I@D2 zwD(6K?-R&cKS?3?d1%K!qtQOotSx_^$L?BwQl;r5_j#R@m^cRk%C}aVM>5d#3+W@D zS>JPz`@J-UqOH4nxrcpb3#|8heG4zqXL$e)@ zs6Vecig-;Zgn7+_UKJeBYaUG5YaaYxyyijQUh^R0H6hsNhkDIJ{=DWP%xls?W~L(u zJ?u57NPLP<9(L&n5eT|>C|f2&t&a68uXZxS#jk837s5qoxD+;0CSzn`-GN3P@!H71 zx5I-<$H`=ZRi#I~HV#=o<$w}A1{dqcb-_@E~j>`rPe&DC$U2GP4%*x0Id~w*X zZ-U_3`Imh z1O&weQA9y>L0$2&3MdaA`fTt2n@jGUb_e$P;FIs1bMF82GUv>k^B==j9e?4SFwWBT z88tSHThslKP0Fz0&>z-GTa2*v0QL1uC!zT5aDMmGO^Nf zPApS(%fJeCmV~d|EpdESS*P5?+7{J073%#W^0GJHI78wTeOVan7A+YH+Y`2>KxQ_W zqezdosJIsY!L?-i?yzBY71!dcchLEUNfo3>CI^)?tNBTB-MK4CSH3e(bvecT+d@0k zauk?pVh%qWf+onc?2x243o5Bks`B=!5A0Bv?ogNe>n+7}!;m(w@67!~u9mqK_jFl$ z2j*5HW?e!)ErD4k{haD@J2M29Y8@@r6?(()luAMEHH_Gt=GLs_fUNq6`6ewMf@^Wb z3Q+mp=E0>28COUWbPe}<@Rxp?t@Q8kH+ooWPl^d*4$<4JfmWaCria{=vP`#e!!cz8ZkDnGmFr|< zdWHn|Wl2wP;u}S^BHpAimH#tQ{uH#8l^7;oUIA?Mucb1jiHzK6mRRh~p_bSUfGo0YX`+EBUXg3@)-W)-$a zE|zm{xo&4tP!az2kn7C}UUqMpN*?zo!}}p)GCbev$xt_$XTiBKv?_S$=5)l+;^3mj zgqRY4iw~wb*QqM-@WG!We~I+AE@Mz@PdSSAu{{wG(PyNQLR#JIAG7?;UVeVw_z0T& zy6FluzJd_R20_b5eJM~;{(SUx$g(1*N@S^S)~@UX_dE@1|qoeVH7 z0wg}=C%wX@SXEPt9_Y5f$5A!IWKUX)!wqHNO$q_ywXqkfJEa%u0XxiU2fBPUBh1jh z{OxC;W&gcAI@cSIy3<%u`7YYCpsE0al)B6Oa+dR5&syo3Kr6*_gLCG{f}eiHI>}b& z`7Yf|Wym+RFKK^x3!?6pc4mFXQ*cXfLb$+M zk4l2xNvsFp3S9;m-=xPd`1@N)q1)hbSdU0aGS*?C%aajZ)uGHsWRwb&bD`Hof1&?n z3KyD&JB$NA>#?g2Z&BE{6Wn<$&=X<&kb+1DU*HBlPA6hfGD25w55UL};!A&q zL2qpaWmQGCsVm+rBZog5+siPQcI-J~mc&_?V6DL4#D|$W5L%YpVbF(U!;@-yu37A+ z#?usav0EbN8xvXVHgX)1RG6A-v0Lx*e@BsvZAB?rN|Y8W@72v&Dsh{dnzB^l`Zmy* zr4oJG6r|j3St@aR;~B_OiM8#cmgI1mZCe_b-g4QO{##{V>asV?&`C?3%Ko7Aq8mz^ z{q1gqZAAN3KQ1S)Pj{*B$m<>Bak&^Cr6<-n{DcL>|85f>Z4*Bo5I=4cA7c{7wCJ0F z_(wMJu{QB@(y~7G^&Qz*XYR7&TxOJ*f#QWRs#D(L1}0+TY*AbZL~$0Qud&UIcX@*l zG>Y-IC@uvu{go}#6RhIuE?pew8`W=Y;$>EGrKKibtJenT<_$(Yvc}uY;mfDgC;}@|^6V$HM%;f3k~iQ@!L{I8^RrYwFcafy`dB zWp;{H-1BWf{3o0ERFgPH^a}y;Uv1*kOyZc5Rop1b6_z!|^qUps6Anc=-DNgxF3Rby z>PsX|PDMH0mile}%xa>A!7_~8XA+mPQFjN#JvQ+fCUKO_PF);rUXyRvTSA{{5=Y5j z35d(LPb}iIY~sFAM-M&5CO+FFE{PEh-<1c9wHh|@IVN!=W`97uj!k^7NgScStBY&( zB&+c@@p&e3gnl9rx_s>3lGXWEarF^j=#3@xJ8j|%OyZIlt(nAtUMd%KSd;dcg)VDR zJh&E*nrZ#L(CtZ{aT5?PblE=@*aReE#?#zV8d~c>dS%L=q}yaoVjN`3U8azx4Vql; z@($_7s=}PXa@Us&=0v!CkH&wuF1PL>(b@(wh?VShW1x%NCiK2#lR3SMTy{E`9~m!l z{eF%=y^E~rRWC^Al^2>AL@FDTaoZFxHm+~5ZAyBf-$!NB^WCNW`?z?C)syrVzo*JJ zV2Wm`aUzFkw8jP>Hwx9{W0~0pbXtaLy@=!!N|C>Z454}|g^;SXQrAm5qPAX8kQh4_>=h8d6IV%@mYGb*U3Ir(`On&a{lW&>rea{}fHBk<^{rQjd^p zloHy4dWMdm)X+7Q9(tHELVu>ru=bP{Hj%Q!Hq*UfXDG)LO}U;F>gAb1y*)2bAJ19p ztJI}Dr7!hUmQ#P_APrD{rF^vw6{z_%NL@gK)vYu{{g#GmiBzN&(J*ZT4cCrSakxe$ z;oWIO_-q;(UO}V6&(r9Lcp4LtM`I%%rg0I6sVp*tCPsFmNs-fNa^y=iCGrcJ8dZa) zMdi?psD(5$YCFw}x857PW9uhW7m7wP`0iL|h45tUcnK#Qs#r3a!z zXmNB0S`s~;mPS8G%c4J}hrH2p@GX;8c<0kf?^Zcpc9~YkG@?gi3TREtN?IFpfY!zQ zNb9S$r9V|0MH{PaqQ|R!K$~I}dLp(ZRm9Gvt+7XGTlHQatpOdpZ8{yUKbYRFznYHJzeq>pYSOW| zWO_fYn2yJl(}!`-(TTWY^ikYZIvHP=K9283pTv)(Q}GYe>G%rzH2xHwiT{m0OK3!& zCuGstgyD29p^Ppk%%PtXmU3jmV_ZGqDXyRJ3O7mE%}EJIMCKUxNVvo)4WH$n4X<bd1?|po;obXr zNc)~VwEZD2>hLrV>v$U%cf8Cc_w47=q;WhVX)TXRI>4iouJD*n4R~y)-aM|;Rvw>R zlP4sna#`{;o|ybso|OC{Pwu>mr*wXkr*^)?)4J5>>0Qq7eO)7XM%R0IX4la?tLu86 z-SrU9>3WUlc5B4*y5;fwZsok7+pD~=`*1Gr(SsNDxWbE58u5~p0$!T3oR_8Sp(I@+ z*I)_{X-RDQPDN683dCDX#{EP5R6ccoiMR+D@oyAA4n5%?}fLDIAkhN>w%4IU2Hx5qivcLORMx&jdci=%?(-^Ymkn zs0wH3zh*_0IowbURFc{E-RvamK9Ot%8DpPWzS;I5>`YrDJ!DrlNC|2 z$%^Q!WJPpEvLXr)SrLVTtcZ#~Rz#5=E27$tJv-q|G|sU{zR%4b`SK-uS0eBI333wU5z5>%0m|lgc0@w;{1GWP@ zfY*SXkb5221-t>b-M}7TFYqR?4|ogM4;%mv!pGadA>c6Z4)88;1b7elJA{t{$AI^N zQk7`0G|P$1OEWd0_T7)fG;8Z6-@sGz6Q<% z-vZwN{|Q_G{snvoTm&uwmx1qr9}v_P;J;wK3S0yJ8@LYqh+lt#>3@KqfnR`Mf!~1N zMMN6iQDO!{fKVU|KX?EIRu#}-4TmWLhyI7+4X6*q0r5Zr&;V!%+zvDX8Uu;I9Y7P{PM|5!3}_Ct09pdAfLy6iZjH>efwe7g z7tjv48)y%706GHq07*b6AXz{gVCoFh6Tq@id9M6msLXg51503C3RAbxV?>X^)CH#Q zz&f#VArB_*&jX0YKzK4R0dmuU@vu$-*2BjdxGjM7exMxIg)o%?Q-PUq%Yi8g7z^A7 z+zTY**NHGq0%pKE4wwcMA&z0dP*@)U<^uD8IY27Br2*+c29PP>@mx$ii6;{ehiNqM zXZ{P(BJmb>nb%X;*Wwm7Pav~=@z&8J^MH<_ZxgLX$d4kFQ+%5EDqkbME~e0CKy#o4 z&@!|Yg|>#N4bT?23up)2jbGct)B&cBFx>+r0iA$kpfk_~=nA=RKzE=A+){v^Kq`<1 zqyrg1CXfYW!^gcq4v-7<0(t{|fWAN;g!=*gfdRlkARj0I1_6b@U|HNaZn zF<>3A9@qf<3D^ic4r~IR0R98`Gw>JSN#H5qufWs5Gr+UJX5cyCZ@}}w3&4xOOTf#( zE5H`uRiFac3Ty+m13Q4%kdK`(y$Ky5PF#+Tc%Hvu{uh76e336P{{YjgTtWOM?<0N@ zJ@gG=CWPn1v>K*$(pPy2FC~7P4-w-A$^YQ9%wHma57B@7A_aYbUPwl7m~vry09Xqw z2W9~)fQKQn5~hcMY*@2^`LNCg3Sk`r^oMmYO#NWW2l9Xcz##lk01OnX)?a4!q4He) Fe*wlqrEmZM