Updated repo for LEC
This commit is contained in:
komaljaved-lm
parent
d533ec413e
commit
cc61f85e64
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["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/users/scratch/komal.javed.data/Quasar/k_se_quasar/design/project/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]]
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["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/users/scratch/komal.javed.data/Quasar/quasar_2.0/design/project/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]]
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@ -1 +1 @@
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[debug] Full compilation, no sources in previous analysis.
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[0m[[0m[0mdebug[0m] [0m[0mFull compilation, no sources in previous analysis.[0m
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@ -1,2 +1,2 @@
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[debug] Copy resource mappings:
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[debug]
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[0m[[0m[0mdebug[0m] [0m[0mCopy resource mappings: [0m
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[0m[[0m[0mdebug[0m] [0m[0m [0m
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@ -1 +1 @@
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/home/users/scratch/komal.javed.data/Quasar/k_se_quasar/design/project/target/scala-2.12/sbt-1.0/classes
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/home/users/scratch/komal.javed.data/Quasar/quasar_2.0/design/project/target/scala-2.12/sbt-1.0/classes
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/home/users/scratch/komal.javed.data/Quasar/k_se_quasar/design/project/target/scala-2.12/sbt-1.0/classes
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/home/users/scratch/komal.javed.data/Quasar/quasar_2.0/design/project/target/scala-2.12/sbt-1.0/classes
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/home/users/scratch/komal.javed.data/Quasar/k_se_quasar/design/project/target/scala-2.12/sbt-1.0/classes
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/home/users/scratch/komal.javed.data/Quasar/quasar_2.0/design/project/target/scala-2.12/sbt-1.0/classes
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/home/users/scratch/komal.javed.data/Quasar/k_se_quasar/design/project/target/scala-2.12/sbt-1.0/classes
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/home/users/scratch/komal.javed.data/Quasar/quasar_2.0/design/project/target/scala-2.12/sbt-1.0/classes
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/home/users/scratch/komal.javed.data/Quasar/k_se_quasar/design/project/target/scala-2.12/sbt-1.0/classes
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/home/users/scratch/komal.javed.data/Quasar/quasar_2.0/design/project/target/scala-2.12/sbt-1.0/classes
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@ -92,14 +92,14 @@ CFLAGS += "-std=c++11"
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# compiles), or -O for balance.
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VERILATOR_MAKE_FLAGS = OPT_FAST="-Os"
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#############Targets#######################################
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all: clean sbt_ verilator
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all: clean conf sbt_ verilator
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vcs_all: clean sbt_ vcs
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vcs_all: clean conf sbt_ vcs
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############ Model Builds ###############################
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conf:
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BUILD_PATH=${BUILD_DIR} ${RV_ROOT}/configs/quasar.config -target=$(target) $(CONF_PARAMS)
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sbt_: conf
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sbt_:
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cd ${RV_ROOT}/design/ && exec sbt "run"
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python3 ${RV_ROOT}/design/reset_script.py
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rm -rf ${RV_ROOT}/design/quasar_wrapper.v
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@ -134,7 +134,10 @@ ifeq ($(shell which fm_shell 2> /dev/null),)
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lec:
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$(error Unable to locate the executable file for formality! Exiting!)
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else
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lec:
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lec: sbt_
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rm -rf ${RV_ROOT}/verif/LEC/LEC_RTL
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git clone https://github.com/Lampro-Mellon/LEC-RTL.git LEC_RTL
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mv LEC_RTL ${RV_ROOT}/verif/LEC
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python3 ${RV_ROOT}/verif/LEC/config.py
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fm_shell -f ${RV_ROOT}/verif/LEC/formality_work/run_me.fms
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@mv *.log ${RV_ROOT}/verif/LEC/formality_work/formality_log
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@ -209,5 +212,7 @@ clean:
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rm -rf $(OFILES_PATH)/*.fsdb
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rm -rf ${RV_ROOT}/FM_WORK
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rm -rf ${RV_ROOT}/tracer_logs/*.log
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rm -rf ${RV_ROOT}/verif/LEC/formality_work/formality_log/*.log
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rm -rf ${RV_ROOT}/verif/LEC/*.fss
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rm -rf *.log *.lck *.s *.hex *.dis *.tbl vcs* simv* quasar* *.exe obj* *.o ucli.key vc_hdrs.h csrc *.csv work *.dump *.fsdb
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@ -1 +0,0 @@
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Subproject commit 9260b5567cbf28dfe4b2153bbea1a8bd2d742228
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@ -1,816 +0,0 @@
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2020 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// all flops call the rvdff flop
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`define RV_FPGA_OPTIMIZE 1
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`define RV_PHYSICAL 1
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module rvdff #( parameter WIDTH=1, SHORT=0 )
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(
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input logic [WIDTH-1:0] din,
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input logic clk,
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input logic rst_l,
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output logic [WIDTH-1:0] dout
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);
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if (SHORT == 1) begin
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assign dout = din;
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end
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else begin
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`ifdef RV_CLOCKGATE
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always @(posedge tb_top.clk) begin
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#0 $strobe("CG: %0t %m din %x dout %x clk %b width %d",$time,din,dout,clk,WIDTH);
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end
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`endif
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always_ff @(posedge clk or negedge rst_l) begin
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if (rst_l == 0)
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dout[WIDTH-1:0] <= 0;
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else
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dout[WIDTH-1:0] <= din[WIDTH-1:0];
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end
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end
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endmodule
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// rvdff with 2:1 input mux to flop din iff sel==1
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module rvdffs #( parameter WIDTH=1, SHORT=0 )
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(
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input logic [WIDTH-1:0] din,
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input logic en,
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input logic clk,
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input logic rst_l,
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output logic [WIDTH-1:0] dout
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);
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if (SHORT == 1) begin : genblock
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assign dout = din;
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end
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else begin : genblock
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rvdff #(WIDTH) dffs (.din((en) ? din[WIDTH-1:0] : dout[WIDTH-1:0]), .*);
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end
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endmodule
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// rvdff with en and clear
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module rvdffsc #( parameter WIDTH=1, SHORT=0 )
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(
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input logic [WIDTH-1:0] din,
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input logic en,
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input logic clear,
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input logic clk,
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input logic rst_l,
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output logic [WIDTH-1:0] dout
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);
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logic [WIDTH-1:0] din_new;
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if (SHORT == 1) begin
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assign dout = din;
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end
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else begin
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assign din_new = {WIDTH{~clear}} & (en ? din[WIDTH-1:0] : dout[WIDTH-1:0]);
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rvdff #(WIDTH) dffsc (.din(din_new[WIDTH-1:0]), .*);
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end
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endmodule
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// _fpga versions
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module rvdff_fpga #( parameter WIDTH=1, SHORT=0 )
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(
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input logic [WIDTH-1:0] din,
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input logic clk,
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input logic clken,
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input logic rawclk,
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input logic rst_l,
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output logic [WIDTH-1:0] dout
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);
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if (SHORT == 1) begin
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assign dout = din;
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end
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else begin
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`ifdef RV_FPGA_OPTIMIZE
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rvdffs #(WIDTH) dffs (.clk(rawclk), .en(clken), .*);
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`else
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rvdff #(WIDTH) dff (.*);
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`endif
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end
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endmodule
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// rvdff with 2:1 input mux to flop din iff sel==1
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module rvdffs_fpga #( parameter WIDTH=1, SHORT=0 )
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(
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input logic [WIDTH-1:0] din,
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input logic en,
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input logic clk,
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input logic clken,
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input logic rawclk,
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input logic rst_l,
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output logic [WIDTH-1:0] dout
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);
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if (SHORT == 1) begin : genblock
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assign dout = din;
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end
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else begin : genblock
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`ifdef RV_FPGA_OPTIMIZE
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rvdffs #(WIDTH) dffs (.clk(rawclk), .en(clken & en), .*);
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`else
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rvdffs #(WIDTH) dffs (.*);
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`endif
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end
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endmodule
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// rvdff with en and clear
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module rvdffsc_fpga #( parameter WIDTH=1, SHORT=0 )
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(
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input logic [WIDTH-1:0] din,
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input logic en,
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input logic clear,
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input logic clk,
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input logic clken,
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input logic rawclk,
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input logic rst_l,
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output logic [WIDTH-1:0] dout
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);
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logic [WIDTH-1:0] din_new;
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if (SHORT == 1) begin
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assign dout = din;
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end
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else begin
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`ifdef RV_FPGA_OPTIMIZE
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rvdffs #(WIDTH) dffs (.clk(rawclk), .din(din[WIDTH-1:0] & {WIDTH{~clear}}),.en((en | clear) & clken), .*);
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`else
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rvdffsc #(WIDTH) dffsc (.*);
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`endif
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end
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endmodule
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module rvdffe #( parameter WIDTH=1, SHORT=0, OVERRIDE=0 )
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(
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input logic [WIDTH-1:0] din,
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input logic en,
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input logic clk,
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input logic rst_l,
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input logic scan_mode,
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output logic [WIDTH-1:0] dout
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);
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logic l1clk;
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if (SHORT == 1) begin : genblock
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if (1) begin : genblock
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assign dout = din;
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end
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end
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else begin : genblock
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`ifndef RV_PHYSICAL
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if (WIDTH >= 8 || OVERRIDE==1) begin: genblock
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`endif
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`ifdef RV_FPGA_OPTIMIZE
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rvdffs #(WIDTH) dff ( .* );
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`else
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rvclkhdr clkhdr ( .* );
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rvdff #(WIDTH) dff (.*, .clk(l1clk));
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`endif
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`ifndef RV_PHYSICAL
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end
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else
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$error("%m: rvdffe must be WIDTH >= 8");
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`endif
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end // else: !if(SHORT == 1)
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endmodule // rvdffe
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module rvdffpcie #( parameter WIDTH=31 )
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(
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input logic [WIDTH-1:0] din,
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input logic clk,
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input logic rst_l,
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input logic en,
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input logic scan_mode,
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output logic [WIDTH-1:0] dout
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);
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`ifndef RV_PHYSICAL
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if (WIDTH == 31) begin: genblock
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`endif
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`ifdef RV_FPGA_OPTIMIZE
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rvdffs #(WIDTH) dff ( .* );
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`else
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rvdfflie #(.WIDTH(WIDTH), .LEFT(19)) dff (.*);
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`endif
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`ifndef RV_PHYSICAL
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end
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else
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$error("%m: rvdffpcie width must be 31");
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`endif
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endmodule
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// format: { LEFT, EXTRA }
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// LEFT # of bits will be done with rvdffie, all else EXTRA with rvdffe
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module rvdfflie #( parameter WIDTH=16, LEFT=8 )
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(
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input logic [WIDTH-1:0] din,
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input logic clk,
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input logic rst_l,
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input logic en,
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input logic scan_mode,
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output logic [WIDTH-1:0] dout
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);
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localparam EXTRA = WIDTH-LEFT;
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localparam LMSB = WIDTH-1;
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localparam LLSB = LMSB-LEFT+1;
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localparam XMSB = LLSB-1;
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localparam XLSB = LLSB-EXTRA;
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`ifndef RV_PHYSICAL
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if (WIDTH >= 16 && LEFT >= 8 && EXTRA >= 8) begin: genblock
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`endif
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`ifdef RV_FPGA_OPTIMIZE
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rvdffs #(WIDTH) dff ( .* );
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`else
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rvdffiee #(LEFT) dff_left (.*, .din(din[LMSB:LLSB]), .dout(dout[LMSB:LLSB]));
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rvdffe #(EXTRA) dff_extra (.*, .din(din[XMSB:XLSB]), .dout(dout[XMSB:XLSB]));
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`endif
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`ifndef RV_PHYSICAL
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end
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else
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$error("%m: rvdfflie musb be WIDTH >= 16 && LEFT >= 8 && EXTRA >= 8");
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`endif
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endmodule
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// special power flop for predict packet
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// format: { LEFT, RIGHT==31 }
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// LEFT # of bits will be done with rvdffe; RIGHT is enabled by LEFT[LSB] & en
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module rvdffppe #( parameter WIDTH=32 )
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(
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input logic [WIDTH-1:0] din,
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input logic clk,
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input logic rst_l,
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input logic en,
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input logic scan_mode,
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output logic [WIDTH-1:0] dout
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);
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localparam RIGHT = 31;
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localparam LEFT = WIDTH - RIGHT;
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localparam LMSB = WIDTH-1;
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localparam LLSB = LMSB-LEFT+1;
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localparam RMSB = LLSB-1;
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localparam RLSB = LLSB-RIGHT;
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`ifndef RV_PHYSICAL
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if (WIDTH>=32 && LEFT>=8 && RIGHT>=8) begin: genblock
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`endif
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`ifdef RV_FPGA_OPTIMIZE
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rvdffs #(WIDTH) dff ( .* );
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`else
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rvdffe #(LEFT) dff_left (.*, .din(din[LMSB:LLSB]), .dout(dout[LMSB:LLSB]));
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rvdffe #(RIGHT) dff_right (.*, .din(din[RMSB:RLSB]), .dout(dout[RMSB:RLSB]), .en(en & din[LLSB])); // qualify with pret
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`endif
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`ifndef RV_PHYSICAL
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end
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else
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$error("%m: must be WIDTH>=32 && LEFT>=8 && RIGHT>=8");
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`endif
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endmodule
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module rvdffie #( parameter WIDTH=1, OVERRIDE=0 )
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(
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input logic [WIDTH-1:0] din,
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input logic clk,
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input logic rst_l,
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input logic scan_mode,
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output logic [WIDTH-1:0] dout
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);
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logic l1clk;
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logic en;
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`ifndef RV_PHYSICAL
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if (WIDTH >= 8 || OVERRIDE==1) begin: genblock
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`endif
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assign en = |(din ^ dout);
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`ifdef RV_FPGA_OPTIMIZE
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rvdffs #(WIDTH) dff ( .* );
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`else
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rvclkhdr clkhdr ( .* );
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rvdff #(WIDTH) dff (.*, .clk(l1clk));
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`endif
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`ifndef RV_PHYSICAL
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end
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else
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$error("%m: rvdffie must be WIDTH >= 8");
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`endif
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endmodule
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// ie flop but it has an .en input
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module rvdffiee #( parameter WIDTH=1, OVERRIDE=0 )
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(
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input logic [WIDTH-1:0] din,
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input logic clk,
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||||
input logic rst_l,
|
||||
input logic scan_mode,
|
||||
input logic en,
|
||||
output logic [WIDTH-1:0] dout
|
||||
);
|
||||
|
||||
logic l1clk;
|
||||
logic final_en;
|
||||
|
||||
`ifndef RV_PHYSICAL
|
||||
if (WIDTH >= 8 || OVERRIDE==1) begin: genblock
|
||||
`endif
|
||||
|
||||
assign final_en = (|(din ^ dout)) & en;
|
||||
|
||||
`ifdef RV_FPGA_OPTIMIZE
|
||||
rvdffs #(WIDTH) dff ( .*, .en(final_en) );
|
||||
`else
|
||||
rvdffe #(WIDTH) dff (.*, .en(final_en));
|
||||
`endif
|
||||
|
||||
`ifndef RV_PHYSICAL
|
||||
end
|
||||
else
|
||||
$error("%m: rvdffie width must be >= 8");
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
module rvsyncss #(parameter WIDTH = 251)
|
||||
(
|
||||
input logic clk,
|
||||
input logic rst_l,
|
||||
input logic [WIDTH-1:0] din,
|
||||
output logic [WIDTH-1:0] dout
|
||||
);
|
||||
|
||||
logic [WIDTH-1:0] din_ff1;
|
||||
|
||||
rvdff #(WIDTH) sync_ff1 (.*, .din (din[WIDTH-1:0]), .dout(din_ff1[WIDTH-1:0]));
|
||||
rvdff #(WIDTH) sync_ff2 (.*, .din (din_ff1[WIDTH-1:0]), .dout(dout[WIDTH-1:0]));
|
||||
|
||||
endmodule // rvsyncss
|
||||
|
||||
module rvsyncss_fpga #(parameter WIDTH = 251)
|
||||
(
|
||||
input logic gw_clk,
|
||||
input logic rawclk,
|
||||
input logic clken,
|
||||
input logic rst_l,
|
||||
input logic [WIDTH-1:0] din,
|
||||
output logic [WIDTH-1:0] dout
|
||||
);
|
||||
|
||||
logic [WIDTH-1:0] din_ff1;
|
||||
|
||||
rvdff_fpga #(WIDTH) sync_ff1 (.*, .clk(gw_clk), .rawclk(rawclk), .clken(clken), .din (din[WIDTH-1:0]), .dout(din_ff1[WIDTH-1:0]));
|
||||
rvdff_fpga #(WIDTH) sync_ff2 (.*, .clk(gw_clk), .rawclk(rawclk), .clken(clken), .din (din_ff1[WIDTH-1:0]), .dout(dout[WIDTH-1:0]));
|
||||
|
||||
endmodule // rvsyncss
|
||||
|
||||
module rvlsadder
|
||||
(
|
||||
input logic [31:0] rs1,
|
||||
input logic [11:0] offset,
|
||||
|
||||
output logic [31:0] dout
|
||||
);
|
||||
|
||||
logic cout;
|
||||
logic sign;
|
||||
|
||||
logic [31:12] rs1_inc;
|
||||
logic [31:12] rs1_dec;
|
||||
|
||||
assign {cout,dout[11:0]} = {1'b0,rs1[11:0]} + {1'b0,offset[11:0]};
|
||||
|
||||
assign rs1_inc[31:12] = rs1[31:12] + 1;
|
||||
|
||||
assign rs1_dec[31:12] = rs1[31:12] - 1;
|
||||
|
||||
assign sign = offset[11];
|
||||
|
||||
assign dout[31:12] = ({20{ sign ^~ cout}} & rs1[31:12]) |
|
||||
({20{ ~sign & cout}} & rs1_inc[31:12]) |
|
||||
({20{ sign & ~cout}} & rs1_dec[31:12]);
|
||||
|
||||
endmodule // rvlsadder
|
||||
|
||||
// assume we only maintain pc[31:1] in the pipe
|
||||
|
||||
module rvbradder
|
||||
(
|
||||
input [31:1] pc,
|
||||
input [12:1] offset,
|
||||
|
||||
output [31:1] dout
|
||||
);
|
||||
|
||||
logic cout;
|
||||
logic sign;
|
||||
|
||||
logic [31:13] pc_inc;
|
||||
logic [31:13] pc_dec;
|
||||
|
||||
assign {cout,dout[12:1]} = {1'b0,pc[12:1]} + {1'b0,offset[12:1]};
|
||||
|
||||
assign pc_inc[31:13] = pc[31:13] + 1;
|
||||
|
||||
assign pc_dec[31:13] = pc[31:13] - 1;
|
||||
|
||||
assign sign = offset[12];
|
||||
|
||||
|
||||
assign dout[31:13] = ({19{ sign ^~ cout}} & pc[31:13]) |
|
||||
({19{ ~sign & cout}} & pc_inc[31:13]) |
|
||||
({19{ sign & ~cout}} & pc_dec[31:13]);
|
||||
|
||||
|
||||
endmodule // rvbradder
|
||||
|
||||
|
||||
// 2s complement circuit
|
||||
module rvtwoscomp #( parameter WIDTH=32 )
|
||||
(
|
||||
input logic [WIDTH-1:0] din,
|
||||
|
||||
output logic [WIDTH-1:0] dout
|
||||
);
|
||||
|
||||
logic [WIDTH-1:1] dout_temp; // holding for all other bits except for the lsb. LSB is always din
|
||||
|
||||
genvar i;
|
||||
|
||||
for ( i = 1; i < WIDTH; i++ ) begin : flip_after_first_one
|
||||
assign dout_temp[i] = (|din[i-1:0]) ? ~din[i] : din[i];
|
||||
end : flip_after_first_one
|
||||
|
||||
assign dout[WIDTH-1:0] = { dout_temp[WIDTH-1:1], din[0] };
|
||||
|
||||
endmodule // 2'scomp
|
||||
|
||||
// find first
|
||||
module rvfindfirst1 #( parameter WIDTH=32, SHIFT=$clog2(WIDTH) )
|
||||
(
|
||||
input logic [WIDTH-1:0] din,
|
||||
|
||||
output logic [SHIFT-1:0] dout
|
||||
);
|
||||
logic done;
|
||||
|
||||
always_comb begin
|
||||
dout[SHIFT-1:0] = {SHIFT{1'b0}};
|
||||
done = 1'b0;
|
||||
|
||||
for ( int i = WIDTH-1; i > 0; i-- ) begin : find_first_one
|
||||
done |= din[i];
|
||||
dout[SHIFT-1:0] += done ? 1'b0 : 1'b1;
|
||||
end : find_first_one
|
||||
end
|
||||
endmodule // rvfindfirst1
|
||||
|
||||
module rvfindfirst1hot #( parameter WIDTH=32 )
|
||||
(
|
||||
input logic [WIDTH-1:0] din,
|
||||
|
||||
output logic [WIDTH-1:0] dout
|
||||
);
|
||||
logic done;
|
||||
|
||||
always_comb begin
|
||||
dout[WIDTH-1:0] = {WIDTH{1'b0}};
|
||||
done = 1'b0;
|
||||
for ( int i = 0; i < WIDTH; i++ ) begin : find_first_one
|
||||
dout[i] = ~done & din[i];
|
||||
done |= din[i];
|
||||
end : find_first_one
|
||||
end
|
||||
endmodule // rvfindfirst1hot
|
||||
|
||||
// mask and match function matches bits after finding the first 0 position
|
||||
// find first starting from LSB. Skip that location and match the rest of the bits
|
||||
module rvmaskandmatch #( parameter WIDTH=32 )
|
||||
(
|
||||
input logic [WIDTH-1:0] mask, // this will have the mask in the lower bit positions
|
||||
input logic [WIDTH-1:0] data, // this is what needs to be matched on the upper bits with the mask's upper bits
|
||||
input logic masken, // when 1 : do mask. 0 : full match
|
||||
output logic match
|
||||
);
|
||||
|
||||
logic [WIDTH-1:0] matchvec;
|
||||
logic masken_or_fullmask;
|
||||
|
||||
assign masken_or_fullmask = masken & ~(&mask[WIDTH-1:0]);
|
||||
|
||||
assign matchvec[0] = masken_or_fullmask | (mask[0] == data[0]);
|
||||
genvar i;
|
||||
|
||||
for ( i = 1; i < WIDTH; i++ ) begin : match_after_first_zero
|
||||
assign matchvec[i] = (&mask[i-1:0] & masken_or_fullmask) ? 1'b1 : (mask[i] == data[i]);
|
||||
end : match_after_first_zero
|
||||
|
||||
assign match = &matchvec[WIDTH-1:0]; // all bits either matched or were masked off
|
||||
|
||||
endmodule // rvmaskandmatch
|
||||
|
||||
|
||||
|
||||
|
||||
// Check if the S_ADDR <= addr < E_ADDR
|
||||
module rvrangecheck #(CCM_SADR = 32'h0,
|
||||
CCM_SIZE = 128) (
|
||||
input logic [31:0] addr, // Address to be checked for range
|
||||
output logic in_range, // S_ADDR <= start_addr < E_ADDR
|
||||
output logic in_region
|
||||
);
|
||||
|
||||
localparam REGION_BITS = 4;
|
||||
localparam MASK_BITS = 10 + $clog2(CCM_SIZE);
|
||||
|
||||
logic [31:0] start_addr;
|
||||
logic [3:0] region;
|
||||
|
||||
assign start_addr[31:0] = CCM_SADR;
|
||||
assign region[REGION_BITS-1:0] = start_addr[31:(32-REGION_BITS)];
|
||||
|
||||
assign in_region = (addr[31:(32-REGION_BITS)] == region[REGION_BITS-1:0]);
|
||||
if (CCM_SIZE == 48)
|
||||
assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]) & ~(&addr[MASK_BITS-1 : MASK_BITS-2]);
|
||||
else
|
||||
assign in_range = (addr[31:MASK_BITS] == start_addr[31:MASK_BITS]);
|
||||
|
||||
endmodule // rvrangechecker
|
||||
|
||||
// 16 bit even parity generator
|
||||
module rveven_paritygen #(WIDTH = 16) (
|
||||
input logic [WIDTH-1:0] data_in, // Data
|
||||
output logic parity_out // generated even parity
|
||||
);
|
||||
|
||||
assign parity_out = ^(data_in[WIDTH-1:0]) ;
|
||||
|
||||
endmodule // rveven_paritygen
|
||||
|
||||
module rveven_paritycheck #(WIDTH = 16) (
|
||||
input logic [WIDTH-1:0] data_in, // Data
|
||||
input logic parity_in,
|
||||
output logic parity_err // Parity error
|
||||
);
|
||||
|
||||
assign parity_err = ^(data_in[WIDTH-1:0]) ^ parity_in ;
|
||||
|
||||
endmodule // rveven_paritycheck
|
||||
|
||||
module rvecc_encode (
|
||||
input [31:0] din,
|
||||
output [6:0] ecc_out
|
||||
);
|
||||
logic [5:0] ecc_out_temp;
|
||||
|
||||
assign ecc_out_temp[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30];
|
||||
assign ecc_out_temp[1] = din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31];
|
||||
assign ecc_out_temp[2] = din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31];
|
||||
assign ecc_out_temp[3] = din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
|
||||
assign ecc_out_temp[4] = din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
|
||||
assign ecc_out_temp[5] = din[26]^din[27]^din[28]^din[29]^din[30]^din[31];
|
||||
|
||||
assign ecc_out[6:0] = {(^din[31:0])^(^ecc_out_temp[5:0]),ecc_out_temp[5:0]};
|
||||
|
||||
endmodule // rvecc_encode
|
||||
|
||||
module rvecc_decode (
|
||||
input en,
|
||||
input [31:0] din,
|
||||
input [6:0] ecc_in,
|
||||
input sed_ded, // only do detection and no correction. Used for the I$
|
||||
output [31:0] dout,
|
||||
output [6:0] ecc_out,
|
||||
output single_ecc_error,
|
||||
output double_ecc_error
|
||||
|
||||
);
|
||||
|
||||
logic [6:0] ecc_check;
|
||||
logic [38:0] error_mask;
|
||||
logic [38:0] din_plus_parity, dout_plus_parity;
|
||||
|
||||
// Generate the ecc bits
|
||||
assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30];
|
||||
assign ecc_check[1] = ecc_in[1]^din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31];
|
||||
assign ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31];
|
||||
assign ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
|
||||
assign ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25];
|
||||
assign ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31];
|
||||
|
||||
// This is the parity bit
|
||||
assign ecc_check[6] = ((^din[31:0])^(^ecc_in[6:0])) & ~sed_ded;
|
||||
|
||||
assign single_ecc_error = en & (ecc_check[6:0] != 0) & ecc_check[6]; // this will never be on for sed_ded
|
||||
assign double_ecc_error = en & (ecc_check[6:0] != 0) & ~ecc_check[6]; // all errors in the sed_ded case will be recorded as DE
|
||||
|
||||
// Generate the mask for error correctiong
|
||||
for (genvar i=1; i<40; i++) begin
|
||||
assign error_mask[i-1] = (ecc_check[5:0] == i);
|
||||
end
|
||||
|
||||
// Generate the corrected data
|
||||
assign din_plus_parity[38:0] = {ecc_in[6], din[31:26], ecc_in[5], din[25:11], ecc_in[4], din[10:4], ecc_in[3], din[3:1], ecc_in[2], din[0], ecc_in[1:0]};
|
||||
|
||||
assign dout_plus_parity[38:0] = single_ecc_error ? (error_mask[38:0] ^ din_plus_parity[38:0]) : din_plus_parity[38:0];
|
||||
assign dout[31:0] = {dout_plus_parity[37:32], dout_plus_parity[30:16], dout_plus_parity[14:8], dout_plus_parity[6:4], dout_plus_parity[2]};
|
||||
assign ecc_out[6:0] = {(dout_plus_parity[38] ^ (ecc_check[6:0] == 7'b1000000)), dout_plus_parity[31], dout_plus_parity[15], dout_plus_parity[7], dout_plus_parity[3], dout_plus_parity[1:0]};
|
||||
|
||||
endmodule // rvecc_decode
|
||||
|
||||
module rvecc_encode_64 (
|
||||
input [63:0] din,
|
||||
output [6:0] ecc_out
|
||||
);
|
||||
assign ecc_out[0] = din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63];
|
||||
|
||||
assign ecc_out[1] = din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]^din[32]^din[35]^din[36]^din[39]^din[40]^din[43]^din[44]^din[47]^din[48]^din[51]^din[52]^din[55]^din[56]^din[58]^din[59]^din[62]^din[63];
|
||||
|
||||
assign ecc_out[2] = din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]^din[32]^din[37]^din[38]^din[39]^din[40]^din[45]^din[46]^din[47]^din[48]^din[53]^din[54]^din[55]^din[56]^din[60]^din[61]^din[62]^din[63];
|
||||
|
||||
assign ecc_out[3] = din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];
|
||||
|
||||
assign ecc_out[4] = din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];
|
||||
|
||||
assign ecc_out[5] = din[26]^din[27]^din[28]^din[29]^din[30]^din[31]^din[32]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];
|
||||
|
||||
assign ecc_out[6] = din[57]^din[58]^din[59]^din[60]^din[61]^din[62]^din[63];
|
||||
|
||||
endmodule // rvecc_encode_64
|
||||
|
||||
|
||||
module rvecc_decode_64 (
|
||||
input en,
|
||||
input [63:0] din,
|
||||
input [6:0] ecc_in,
|
||||
output ecc_error
|
||||
);
|
||||
|
||||
logic [6:0] ecc_check;
|
||||
|
||||
// Generate the ecc bits
|
||||
assign ecc_check[0] = ecc_in[0]^din[0]^din[1]^din[3]^din[4]^din[6]^din[8]^din[10]^din[11]^din[13]^din[15]^din[17]^din[19]^din[21]^din[23]^din[25]^din[26]^din[28]^din[30]^din[32]^din[34]^din[36]^din[38]^din[40]^din[42]^din[44]^din[46]^din[48]^din[50]^din[52]^din[54]^din[56]^din[57]^din[59]^din[61]^din[63];
|
||||
|
||||
assign ecc_check[1] = ecc_in[1]^din[0]^din[2]^din[3]^din[5]^din[6]^din[9]^din[10]^din[12]^din[13]^din[16]^din[17]^din[20]^din[21]^din[24]^din[25]^din[27]^din[28]^din[31]^din[32]^din[35]^din[36]^din[39]^din[40]^din[43]^din[44]^din[47]^din[48]^din[51]^din[52]^din[55]^din[56]^din[58]^din[59]^din[62]^din[63];
|
||||
|
||||
assign ecc_check[2] = ecc_in[2]^din[1]^din[2]^din[3]^din[7]^din[8]^din[9]^din[10]^din[14]^din[15]^din[16]^din[17]^din[22]^din[23]^din[24]^din[25]^din[29]^din[30]^din[31]^din[32]^din[37]^din[38]^din[39]^din[40]^din[45]^din[46]^din[47]^din[48]^din[53]^din[54]^din[55]^din[56]^din[60]^din[61]^din[62]^din[63];
|
||||
|
||||
assign ecc_check[3] = ecc_in[3]^din[4]^din[5]^din[6]^din[7]^din[8]^din[9]^din[10]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];
|
||||
|
||||
assign ecc_check[4] = ecc_in[4]^din[11]^din[12]^din[13]^din[14]^din[15]^din[16]^din[17]^din[18]^din[19]^din[20]^din[21]^din[22]^din[23]^din[24]^din[25]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];
|
||||
|
||||
assign ecc_check[5] = ecc_in[5]^din[26]^din[27]^din[28]^din[29]^din[30]^din[31]^din[32]^din[33]^din[34]^din[35]^din[36]^din[37]^din[38]^din[39]^din[40]^din[41]^din[42]^din[43]^din[44]^din[45]^din[46]^din[47]^din[48]^din[49]^din[50]^din[51]^din[52]^din[53]^din[54]^din[55]^din[56];
|
||||
|
||||
assign ecc_check[6] = ecc_in[6]^din[57]^din[58]^din[59]^din[60]^din[61]^din[62]^din[63];
|
||||
|
||||
assign ecc_error = en & (ecc_check[6:0] != 0); // all errors in the sed_ded case will be recorded as DE
|
||||
|
||||
endmodule // rvecc_decode_64
|
||||
|
||||
|
||||
module TEC_RV_ICG
|
||||
(
|
||||
input logic SE, EN, CK,
|
||||
output Q
|
||||
);
|
||||
|
||||
logic en_ff;
|
||||
logic enable;
|
||||
|
||||
assign enable = EN | SE;
|
||||
|
||||
`ifdef VERILATOR
|
||||
always @(negedge CK) begin
|
||||
en_ff <= enable;
|
||||
end
|
||||
`else
|
||||
always @(CK, enable) begin
|
||||
if(!CK)
|
||||
en_ff = enable;
|
||||
end
|
||||
`endif
|
||||
assign Q = CK & en_ff;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module rvclkhdr
|
||||
(
|
||||
input logic en,
|
||||
input logic clk,
|
||||
input logic scan_mode,
|
||||
output logic l1clk
|
||||
);
|
||||
|
||||
logic SE;
|
||||
assign SE = 0;
|
||||
|
||||
TEC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
|
||||
|
||||
endmodule // rvclkhdr
|
||||
|
||||
|
||||
module rvoclkhdr
|
||||
(
|
||||
input logic en,
|
||||
input logic clk,
|
||||
input logic scan_mode,
|
||||
output logic l1clk
|
||||
);
|
||||
|
||||
logic SE;
|
||||
assign SE = 0;
|
||||
|
||||
`ifdef RV_FPGA_OPTIMIZE
|
||||
assign l1clk = clk;
|
||||
`else
|
||||
TEC_RV_ICG clkhdr ( .*, .EN(en), .CK(clk), .Q(l1clk));
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
|
|
@ -1,64 +0,0 @@
|
|||
// SPDX-License-Identifier: Apache-2.0
|
||||
// Copyright 2018 Western Digital Corporation or it's affiliates.
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//------------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright Western Digital, 2019
|
||||
// Owner : Alex Grobman
|
||||
// Description:
|
||||
// This module Synchronizes the signals between JTAG (TCK) and
|
||||
// processor (Core_clk)
|
||||
//
|
||||
//-------------------------------------------------------------------------------------
|
||||
|
||||
module dmi_jtag_to_core_sync (
|
||||
// JTAG signals
|
||||
input rd_en, // 1 bit Read Enable from JTAG
|
||||
input wr_en, // 1 bit Write enable from JTAG
|
||||
|
||||
// Processor Signals
|
||||
input rst_n, // Core reset
|
||||
input clk, // Core clock
|
||||
|
||||
output reg_en, // 1 bit Write interface bit to Processor
|
||||
output reg_wr_en // 1 bit Write enable to Processor
|
||||
);
|
||||
|
||||
wire c_rd_en;
|
||||
wire c_wr_en;
|
||||
reg [2:0] rden, wren;
|
||||
|
||||
|
||||
// Outputs
|
||||
assign reg_en = c_wr_en | c_rd_en;
|
||||
assign reg_wr_en = c_wr_en;
|
||||
|
||||
|
||||
// synchronizers
|
||||
always @ ( posedge clk or negedge rst_n) begin
|
||||
if(!rst_n) begin
|
||||
rden <= '0;
|
||||
wren <= '0;
|
||||
end
|
||||
else begin
|
||||
rden <= {rden[1:0], rd_en};
|
||||
wren <= {wren[1:0], wr_en};
|
||||
end
|
||||
end
|
||||
|
||||
assign c_rd_en = rden[1] & ~rden[2];
|
||||
assign c_wr_en = wren[1] & ~wren[2];
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,91 +0,0 @@
|
|||
// SPDX-License-Identifier: Apache-2.0
|
||||
// Copyright 2018 Western Digital Corporation or it's affiliates.
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//------------------------------------------------------------------------------------
|
||||
//
|
||||
// Copyright Western Digital, 2018
|
||||
// Owner : Anusha Narayanamoorthy
|
||||
// Description:
|
||||
// Wrapper module for JTAG_TAP and DMI synchronizer
|
||||
//
|
||||
//-------------------------------------------------------------------------------------
|
||||
// `include "rvjtag_tap.sv"
|
||||
// `include "dmi_jtag_to_core_sync.sv"
|
||||
module dmi_wrapper(
|
||||
|
||||
// JTAG signals
|
||||
input trst_n, // JTAG reset
|
||||
input tck, // JTAG clock
|
||||
input tms, // Test mode select
|
||||
input tdi, // Test Data Input
|
||||
output tdo, // Test Data Output
|
||||
output tdoEnable, // Test Data Output enable
|
||||
|
||||
// Processor Signals
|
||||
input core_rst_n, // Core reset
|
||||
input core_clk, // Core clock
|
||||
input [31:1] jtag_id, // JTAG ID
|
||||
input [31:0] rd_data, // 32 bit Read data from Processor
|
||||
output [31:0] reg_wr_data, // 32 bit Write data to Processor
|
||||
output [6:0] reg_wr_addr, // 7 bit reg address to Processor
|
||||
output reg_en, // 1 bit Read enable to Processor
|
||||
output reg_wr_en, // 1 bit Write enable to Processor
|
||||
output dmi_hard_reset
|
||||
);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
//Wire Declaration
|
||||
wire rd_en;
|
||||
wire wr_en;
|
||||
wire dmireset;
|
||||
|
||||
|
||||
//jtag_tap instantiation
|
||||
rvjtag_tap i_jtag_tap(
|
||||
.trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
|
||||
.tck(tck), // dedicated JTAG TCK pad signal
|
||||
.tms(tms), // dedicated JTAG TMS pad signal
|
||||
.tdi(tdi), // dedicated JTAG TDI pad signal
|
||||
.tdo(tdo), // dedicated JTAG TDO pad signal
|
||||
.tdoEnable(tdoEnable), // enable for TDO pad
|
||||
.wr_data(reg_wr_data), // 32 bit Write data
|
||||
.wr_addr(reg_wr_addr), // 7 bit Write address
|
||||
.rd_en(rd_en), // 1 bit read enable
|
||||
.wr_en(wr_en), // 1 bit Write enable
|
||||
.rd_data(rd_data), // 32 bit Read data
|
||||
.rd_status(2'b0),
|
||||
.idle(3'h0), // no need to wait to sample data
|
||||
.dmi_stat(2'b0), // no need to wait or error possible
|
||||
.version(4'h1), // debug spec 0.13 compliant
|
||||
.jtag_id(jtag_id),
|
||||
.dmi_hard_reset(dmi_hard_reset),
|
||||
.dmi_reset(dmireset)
|
||||
);
|
||||
|
||||
|
||||
// dmi_jtag_to_core_sync instantiation
|
||||
dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync(
|
||||
.wr_en(wr_en), // 1 bit Write enable
|
||||
.rd_en(rd_en), // 1 bit Read enable
|
||||
|
||||
.rst_n(core_rst_n),
|
||||
.clk(core_clk),
|
||||
.reg_en(reg_en), // 1 bit Write interface bit
|
||||
.reg_wr_en(reg_wr_en) // 1 bit Write enable
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,15 +0,0 @@
|
|||
|
||||
module gated_latch
|
||||
(
|
||||
input logic SE, EN, CK,
|
||||
output Q
|
||||
);
|
||||
logic en_ff;
|
||||
logic enable;
|
||||
assign enable = EN | SE;
|
||||
always @(CK, enable) begin
|
||||
if(!CK)
|
||||
en_ff = enable;
|
||||
end
|
||||
assign Q = CK & en_ff;
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,479 +0,0 @@
|
|||
//********************************************************************************
|
||||
// SPDX-License-Identifier: Apache-2.0
|
||||
// Copyright 2020 Western Digital Corporation or its affiliates.
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//********************************************************************************
|
||||
|
||||
//********************************************************************************
|
||||
// Icache closely coupled memory --- ICCM
|
||||
//********************************************************************************
|
||||
|
||||
module ifu_iccm_mem
|
||||
`include "parameter.sv"
|
||||
//#(
|
||||
// parameter ICCM_BITS,
|
||||
// parameter ICCM_BANK_INDEX_LO,
|
||||
// parameter ICCM_INDEX_BITS,
|
||||
// parameter ICCM_BANK_HI,
|
||||
// parameter ICCM_NUM_BANKS,
|
||||
// parameter ICCM_ENABLE= 'b1,
|
||||
// parameter ICCM_BANK_BITS
|
||||
|
||||
//)
|
||||
|
||||
(
|
||||
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
|
||||
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
|
||||
input logic rst_l, // reset, active low
|
||||
input logic clk_override, // Override non-functional clock gating
|
||||
|
||||
input logic iccm_wren, // ICCM write enable
|
||||
input logic iccm_rden, // ICCM read enable
|
||||
input logic [ICCM_BITS-1:1] iccm_rw_addr, // ICCM read/write address
|
||||
input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
|
||||
input logic iccm_correction_state, // ICCM under a correction - This is needed to guard replacements when hit
|
||||
input logic [2:0] iccm_wr_size, // ICCM write size
|
||||
input logic [77:0] iccm_wr_data, // ICCM write data
|
||||
|
||||
input iccm_ext_in_pkt_t [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt, // External packet
|
||||
|
||||
|
||||
output logic [63:0] iccm_rd_data, // ICCM read data
|
||||
output logic [77:0] iccm_rd_data_ecc, // ICCM read ecc
|
||||
input logic scan_mode // Scan mode control
|
||||
|
||||
);
|
||||
|
||||
|
||||
logic [ICCM_NUM_BANKS-1:0] wren_bank;
|
||||
logic [ICCM_NUM_BANKS-1:0] rden_bank;
|
||||
logic [ICCM_NUM_BANKS-1:0] iccm_clken;
|
||||
logic [ICCM_NUM_BANKS-1:0] [ICCM_BITS-1:ICCM_BANK_INDEX_LO] addr_bank;
|
||||
|
||||
logic [ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_dout, iccm_bank_dout_fn;
|
||||
logic [ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_wr_data;
|
||||
logic [ICCM_BITS-1:1] addr_bank_inc;
|
||||
logic [ICCM_BANK_HI : 2] iccm_rd_addr_hi_q;
|
||||
logic [ICCM_BANK_HI : 1] iccm_rd_addr_lo_q;
|
||||
logic [63:0] iccm_rd_data_pre;
|
||||
logic [63:0] iccm_data;
|
||||
logic [1:0] addr_incr;
|
||||
logic [ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_wr_data_vec;
|
||||
|
||||
// logic to handle hard persisten faults
|
||||
logic [1:0] [ICCM_BITS-1:2] redundant_address;
|
||||
logic [1:0] [38:0] redundant_data;
|
||||
logic [1:0] redundant_valid;
|
||||
logic [ICCM_NUM_BANKS-1:0] sel_red1, sel_red0, sel_red1_q, sel_red0_q;
|
||||
|
||||
|
||||
logic [38:0] redundant_data0_in, redundant_data1_in;
|
||||
logic redundant_lru, redundant_lru_in, redundant_lru_en;
|
||||
logic redundant_data0_en;
|
||||
logic redundant_data1_en;
|
||||
logic r0_addr_en, r1_addr_en;
|
||||
|
||||
// Testing persistent flip
|
||||
// logic [3:0] not_iccm_bank_dout;
|
||||
// logic [15:3] ecc_insert_flip_in, ecc_insert_flip;
|
||||
// logic flip_en, flip_match, flip_match_q;
|
||||
//
|
||||
// assign flip_in = (iccm_rw_addr[3:2] != 2'b00); // dont flip when bank0 - this is to make some progress in DMA streaming cases
|
||||
// assign flip_en = iccm_rden;
|
||||
//
|
||||
// rvdffs #(1) flipmatch (.*,
|
||||
// .clk(clk),
|
||||
// .din(flip_in),
|
||||
// .en(flip_en),
|
||||
// .dout(flip_match_q));
|
||||
//
|
||||
// end of testing flip
|
||||
|
||||
|
||||
assign addr_incr[1:0] = (iccm_wr_size[1:0] == 2'b11) ? 2'b10: 2'b01;
|
||||
assign addr_bank_inc[ICCM_BITS-1 : 1] = iccm_rw_addr[ICCM_BITS-1 : 1] + addr_incr[1:0];
|
||||
|
||||
for (genvar i=0; i<ICCM_NUM_BANKS/2; i++) begin: mem_bank_data
|
||||
assign iccm_bank_wr_data_vec[(2*i)] = iccm_wr_data[38:0];
|
||||
assign iccm_bank_wr_data_vec[(2*i)+1] = iccm_wr_data[77:39];
|
||||
end
|
||||
|
||||
for (genvar i=0; i<ICCM_NUM_BANKS; i++) begin: mem_bank
|
||||
assign wren_bank[i] = iccm_wren & ((iccm_rw_addr[ICCM_BANK_HI:2] == i) | (addr_bank_inc[ICCM_BANK_HI:2] == i));
|
||||
assign iccm_bank_wr_data[i] = iccm_bank_wr_data_vec[i];
|
||||
assign rden_bank[i] = iccm_rden & ( (iccm_rw_addr[ICCM_BANK_HI:2] == i) | (addr_bank_inc[ICCM_BANK_HI:2] == i));
|
||||
assign iccm_clken[i] = wren_bank[i] | rden_bank[i] | clk_override;
|
||||
assign addr_bank[i][ICCM_BITS-1 : ICCM_BANK_INDEX_LO] = wren_bank[i] ? iccm_rw_addr[ICCM_BITS-1 : ICCM_BANK_INDEX_LO] :
|
||||
((addr_bank_inc[ICCM_BANK_HI:2] == i) ?
|
||||
addr_bank_inc[ICCM_BITS-1 : ICCM_BANK_INDEX_LO] :
|
||||
iccm_rw_addr[ICCM_BITS-1 : ICCM_BANK_INDEX_LO]);
|
||||
`ifdef VERILATOR
|
||||
|
||||
el2_ram #(.depth(1<<ICCM_INDEX_BITS), .width(39)) iccm_bank (
|
||||
// Primary ports
|
||||
.ME(iccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
.TEST1(iccm_ext_in_pkt[i].TEST1),
|
||||
.RME(iccm_ext_in_pkt[i].RME),
|
||||
.RM(iccm_ext_in_pkt[i].RM),
|
||||
.LS(iccm_ext_in_pkt[i].LS),
|
||||
.DS(iccm_ext_in_pkt[i].DS),
|
||||
.SD(iccm_ext_in_pkt[i].SD) ,
|
||||
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
|
||||
.BC1(iccm_ext_in_pkt[i].BC1),
|
||||
.BC2(iccm_ext_in_pkt[i].BC2)
|
||||
|
||||
);
|
||||
`else
|
||||
|
||||
if (ICCM_INDEX_BITS == 6 ) begin : iccm
|
||||
ram_64x39 iccm_bank (
|
||||
// Primary ports
|
||||
.CLK(clk),
|
||||
.ME(iccm_clken[i]),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
.TEST1(iccm_ext_in_pkt[i].TEST1),
|
||||
.RME(iccm_ext_in_pkt[i].RME),
|
||||
.RM(iccm_ext_in_pkt[i].RM),
|
||||
.LS(iccm_ext_in_pkt[i].LS),
|
||||
.DS(iccm_ext_in_pkt[i].DS),
|
||||
.SD(iccm_ext_in_pkt[i].SD) ,
|
||||
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
|
||||
.BC1(iccm_ext_in_pkt[i].BC1),
|
||||
.BC2(iccm_ext_in_pkt[i].BC2)
|
||||
|
||||
);
|
||||
end // block: iccm
|
||||
|
||||
else if (ICCM_INDEX_BITS == 7 ) begin : iccm
|
||||
ram_128x39 iccm_bank (
|
||||
// Primary ports
|
||||
.CLK(clk),
|
||||
.ME(iccm_clken[i]),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
.TEST1(iccm_ext_in_pkt[i].TEST1),
|
||||
.RME(iccm_ext_in_pkt[i].RME),
|
||||
.RM(iccm_ext_in_pkt[i].RM),
|
||||
.LS(iccm_ext_in_pkt[i].LS),
|
||||
.DS(iccm_ext_in_pkt[i].DS),
|
||||
.SD(iccm_ext_in_pkt[i].SD) ,
|
||||
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
|
||||
.BC1(iccm_ext_in_pkt[i].BC1),
|
||||
.BC2(iccm_ext_in_pkt[i].BC2)
|
||||
|
||||
);
|
||||
end // block: iccm
|
||||
|
||||
else if (ICCM_INDEX_BITS == 8 ) begin : iccm
|
||||
ram_256x39 iccm_bank (
|
||||
// Primary ports
|
||||
.CLK(clk),
|
||||
.ME(iccm_clken[i]),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
.TEST1(iccm_ext_in_pkt[i].TEST1),
|
||||
.RME(iccm_ext_in_pkt[i].RME),
|
||||
.RM(iccm_ext_in_pkt[i].RM),
|
||||
.LS(iccm_ext_in_pkt[i].LS),
|
||||
.DS(iccm_ext_in_pkt[i].DS),
|
||||
.SD(iccm_ext_in_pkt[i].SD) ,
|
||||
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
|
||||
.BC1(iccm_ext_in_pkt[i].BC1),
|
||||
.BC2(iccm_ext_in_pkt[i].BC2)
|
||||
|
||||
);
|
||||
end // block: iccm
|
||||
else if (ICCM_INDEX_BITS == 9 ) begin : iccm
|
||||
ram_512x39 iccm_bank (
|
||||
// Primary ports
|
||||
.CLK(clk),
|
||||
.ME(iccm_clken[i]),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
.TEST1(iccm_ext_in_pkt[i].TEST1),
|
||||
.RME(iccm_ext_in_pkt[i].RME),
|
||||
.RM(iccm_ext_in_pkt[i].RM),
|
||||
.LS(iccm_ext_in_pkt[i].LS),
|
||||
.DS(iccm_ext_in_pkt[i].DS),
|
||||
.SD(iccm_ext_in_pkt[i].SD) ,
|
||||
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
|
||||
.BC1(iccm_ext_in_pkt[i].BC1),
|
||||
.BC2(iccm_ext_in_pkt[i].BC2)
|
||||
|
||||
);
|
||||
end // block: iccm
|
||||
else if (ICCM_INDEX_BITS == 10 ) begin : iccm
|
||||
ram_1024x39 iccm_bank (
|
||||
// Primary ports
|
||||
.CLK(clk),
|
||||
.ME(iccm_clken[i]),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
.TEST1(iccm_ext_in_pkt[i].TEST1),
|
||||
.RME(iccm_ext_in_pkt[i].RME),
|
||||
.RM(iccm_ext_in_pkt[i].RM),
|
||||
.LS(iccm_ext_in_pkt[i].LS),
|
||||
.DS(iccm_ext_in_pkt[i].DS),
|
||||
.SD(iccm_ext_in_pkt[i].SD) ,
|
||||
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
|
||||
.BC1(iccm_ext_in_pkt[i].BC1),
|
||||
.BC2(iccm_ext_in_pkt[i].BC2)
|
||||
|
||||
);
|
||||
end // block: iccm
|
||||
else if (ICCM_INDEX_BITS == 11 ) begin : iccm
|
||||
ram_2048x39 iccm_bank (
|
||||
// Primary ports
|
||||
.CLK(clk),
|
||||
.ME(iccm_clken[i]),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
.TEST1(iccm_ext_in_pkt[i].TEST1),
|
||||
.RME(iccm_ext_in_pkt[i].RME),
|
||||
.RM(iccm_ext_in_pkt[i].RM),
|
||||
.LS(iccm_ext_in_pkt[i].LS),
|
||||
.DS(iccm_ext_in_pkt[i].DS),
|
||||
.SD(iccm_ext_in_pkt[i].SD) ,
|
||||
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
|
||||
.BC1(iccm_ext_in_pkt[i].BC1),
|
||||
.BC2(iccm_ext_in_pkt[i].BC2)
|
||||
|
||||
);
|
||||
end // block: iccm
|
||||
else if (ICCM_INDEX_BITS == 12 ) begin : iccm
|
||||
ram_4096x39 iccm_bank (
|
||||
// Primary ports
|
||||
.CLK(clk),
|
||||
.ME(iccm_clken[i]),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
.TEST1(iccm_ext_in_pkt[i].TEST1),
|
||||
.RME(iccm_ext_in_pkt[i].RME),
|
||||
.RM(iccm_ext_in_pkt[i].RM),
|
||||
.LS(iccm_ext_in_pkt[i].LS),
|
||||
.DS(iccm_ext_in_pkt[i].DS),
|
||||
.SD(iccm_ext_in_pkt[i].SD) ,
|
||||
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
|
||||
.BC1(iccm_ext_in_pkt[i].BC1),
|
||||
.BC2(iccm_ext_in_pkt[i].BC2)
|
||||
|
||||
);
|
||||
end // block: iccm
|
||||
else if (ICCM_INDEX_BITS == 13 ) begin : iccm
|
||||
ram_8192x39 iccm_bank (
|
||||
// Primary ports
|
||||
.CLK(clk),
|
||||
.ME(iccm_clken[i]),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
.TEST1(iccm_ext_in_pkt[i].TEST1),
|
||||
.RME(iccm_ext_in_pkt[i].RME),
|
||||
.RM(iccm_ext_in_pkt[i].RM),
|
||||
.LS(iccm_ext_in_pkt[i].LS),
|
||||
.DS(iccm_ext_in_pkt[i].DS),
|
||||
.SD(iccm_ext_in_pkt[i].SD) ,
|
||||
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
|
||||
.BC1(iccm_ext_in_pkt[i].BC1),
|
||||
.BC2(iccm_ext_in_pkt[i].BC2)
|
||||
|
||||
);
|
||||
end // block: iccm
|
||||
else if (ICCM_INDEX_BITS == 14 ) begin : iccm
|
||||
ram_16384x39 iccm_bank (
|
||||
// Primary ports
|
||||
.CLK(clk),
|
||||
.ME(iccm_clken[i]),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
.TEST1(iccm_ext_in_pkt[i].TEST1),
|
||||
.RME(iccm_ext_in_pkt[i].RME),
|
||||
.RM(iccm_ext_in_pkt[i].RM),
|
||||
.LS(iccm_ext_in_pkt[i].LS),
|
||||
.DS(iccm_ext_in_pkt[i].DS),
|
||||
.SD(iccm_ext_in_pkt[i].SD) ,
|
||||
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
|
||||
.BC1(iccm_ext_in_pkt[i].BC1),
|
||||
.BC2(iccm_ext_in_pkt[i].BC2)
|
||||
|
||||
);
|
||||
end // block: iccm
|
||||
else begin : iccm
|
||||
ram_32768x39 iccm_bank (
|
||||
// Primary ports
|
||||
.CLK(clk),
|
||||
.ME(iccm_clken[i]),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
.TEST1(iccm_ext_in_pkt[i].TEST1),
|
||||
.RME(iccm_ext_in_pkt[i].RME),
|
||||
.RM(iccm_ext_in_pkt[i].RM),
|
||||
.LS(iccm_ext_in_pkt[i].LS),
|
||||
.DS(iccm_ext_in_pkt[i].DS),
|
||||
.SD(iccm_ext_in_pkt[i].SD) ,
|
||||
.TEST_RNM(iccm_ext_in_pkt[i].TEST_RNM),
|
||||
.BC1(iccm_ext_in_pkt[i].BC1),
|
||||
.BC2(iccm_ext_in_pkt[i].BC2)
|
||||
|
||||
);
|
||||
end // block: iccm
|
||||
`endif
|
||||
|
||||
// match the redundant rows
|
||||
assign sel_red1[i] = (redundant_valid[1] & (((iccm_rw_addr[ICCM_BITS-1:2] == redundant_address[1][ICCM_BITS-1:2]) & (iccm_rw_addr[3:2] == i)) |
|
||||
((addr_bank_inc[ICCM_BITS-1:2]== redundant_address[1][ICCM_BITS-1:2]) & (addr_bank_inc[3:2] == i))));
|
||||
|
||||
assign sel_red0[i] = (redundant_valid[0] & (((iccm_rw_addr[ICCM_BITS-1:2] == redundant_address[0][ICCM_BITS-1:2]) & (iccm_rw_addr[3:2] == i)) |
|
||||
((addr_bank_inc[ICCM_BITS-1:2]== redundant_address[0][ICCM_BITS-1:2]) & (addr_bank_inc[3:2] == i))));
|
||||
|
||||
rvdff #(1) selred0 (.*,
|
||||
.clk(active_clk),
|
||||
.din(sel_red0[i]),
|
||||
.dout(sel_red0_q[i]));
|
||||
|
||||
rvdff #(1) selred1 (.*,
|
||||
.clk(active_clk),
|
||||
.din(sel_red1[i]),
|
||||
.dout(sel_red1_q[i]));
|
||||
|
||||
|
||||
// muxing out the memory data with the redundant data if the address matches
|
||||
assign iccm_bank_dout_fn[i][38:0] = ({39{sel_red1_q[i]}} & redundant_data[1][38:0]) |
|
||||
({39{sel_red0_q[i]}} & redundant_data[0][38:0]) |
|
||||
({39{~sel_red0_q[i] & ~sel_red1_q[i]}} & iccm_bank_dout[i][38:0]);
|
||||
|
||||
end : mem_bank
|
||||
// This section does the redundancy for tolerating single bit errors
|
||||
// 2x 39 bit data values with address[hi:2] and a valid bit is needed to CAM and sub out the reads/writes to the particular locations
|
||||
// Also a LRU flop is kept to decide which of the redundant element to replace.
|
||||
assign r0_addr_en = ~redundant_lru & iccm_buf_correct_ecc;
|
||||
assign r1_addr_en = redundant_lru & iccm_buf_correct_ecc;
|
||||
assign redundant_lru_en = iccm_buf_correct_ecc | (((|sel_red0[ICCM_NUM_BANKS-1:0]) | (|sel_red1[ICCM_NUM_BANKS-1:0])) & iccm_rden & iccm_correction_state);
|
||||
assign redundant_lru_in = iccm_buf_correct_ecc ? ~redundant_lru : (|sel_red0[ICCM_NUM_BANKS-1:0]) ? 1'b1 : 1'b0;
|
||||
|
||||
rvdffs #() red_lru (.*, // LRU flop for the redundant replacements
|
||||
.clk(active_clk),
|
||||
.en(redundant_lru_en),
|
||||
.din(redundant_lru_in),
|
||||
.dout(redundant_lru));
|
||||
|
||||
rvdffs #(ICCM_BITS-2) r0_address (.*, // Redundant Row 0 address
|
||||
.clk(active_clk),
|
||||
.en(r0_addr_en),
|
||||
.din(iccm_rw_addr[ICCM_BITS-1:2]),
|
||||
.dout(redundant_address[0][ICCM_BITS-1:2]));
|
||||
|
||||
rvdffs #(ICCM_BITS-2) r1_address (.*, // Redundant Row 0 address
|
||||
.clk(active_clk),
|
||||
.en(r1_addr_en),
|
||||
.din(iccm_rw_addr[ICCM_BITS-1:2]),
|
||||
.dout(redundant_address[1][ICCM_BITS-1:2]));
|
||||
|
||||
rvdffs #(1) r0_valid (.*,
|
||||
.clk(active_clk), // Redundant Row 0 Valid
|
||||
.en(r0_addr_en),
|
||||
.din(1'b1),
|
||||
.dout(redundant_valid[0]));
|
||||
|
||||
rvdffs #(1) r1_valid (.*, // Redundant Row 1 Valid
|
||||
.clk(active_clk),
|
||||
.en(r1_addr_en),
|
||||
.din(1'b1),
|
||||
.dout(redundant_valid[1]));
|
||||
|
||||
|
||||
|
||||
// We will have to update the Redundant copies in addition to the memory on subsequent writes to this memory location.
|
||||
// The data gets updated on : 1) correction cycle, 2) Future writes - this could be W writes from DMA ( match up till addr[2]) or DW writes ( match till address[3])
|
||||
// The data to pick also depends on the current address[2], size and the addr[2] stored in the address field of the redundant flop. Correction cycle is always W write and the data is splat on both legs, so choosing lower Word
|
||||
|
||||
assign redundant_data0_en = ((iccm_rw_addr[ICCM_BITS-1:3] == redundant_address[0][ICCM_BITS-1:3]) & ((iccm_rw_addr[2] == redundant_address[0][2]) | (iccm_wr_size[1:0] == 2'b11)) & redundant_valid[0] & iccm_wren) |
|
||||
(~redundant_lru & iccm_buf_correct_ecc);
|
||||
|
||||
assign redundant_data0_in[38:0] = (((iccm_rw_addr[2] == redundant_address[0][2]) & iccm_rw_addr[2]) | (redundant_address[0][2] & (iccm_wr_size[1:0] == 2'b11))) ? iccm_wr_data[77:39] : iccm_wr_data[38:0];
|
||||
|
||||
rvdffs #(39) r0_data (.*, // Redundant Row 1 data
|
||||
.clk(active_clk),
|
||||
.en(redundant_data0_en),
|
||||
.din(redundant_data0_in[38:0]),
|
||||
.dout(redundant_data[0][38:0]));
|
||||
|
||||
assign redundant_data1_en = ((iccm_rw_addr[ICCM_BITS-1:3] == redundant_address[1][ICCM_BITS-1:3]) & ((iccm_rw_addr[2] == redundant_address[1][2]) | (iccm_wr_size[1:0] == 2'b11)) & redundant_valid[1] & iccm_wren) |
|
||||
(redundant_lru & iccm_buf_correct_ecc);
|
||||
|
||||
assign redundant_data1_in[38:0] = (((iccm_rw_addr[2] == redundant_address[1][2]) & iccm_rw_addr[2]) | (redundant_address[1][2] & (iccm_wr_size[1:0] == 2'b11))) ? iccm_wr_data[77:39] : iccm_wr_data[38:0];
|
||||
|
||||
rvdffs #(39) r1_data (.*, // Redundant Row 1 data
|
||||
.clk(active_clk),
|
||||
.en(redundant_data1_en),
|
||||
.din(redundant_data1_in[38:0]),
|
||||
.dout(redundant_data[1][38:0]));
|
||||
|
||||
|
||||
rvdffs #(ICCM_BANK_HI) rd_addr_lo_ff (.*, .clk(active_clk), .din(iccm_rw_addr [ICCM_BANK_HI:1]), .dout(iccm_rd_addr_lo_q[ICCM_BANK_HI:1]), .en(1'b1)); // bit 0 of address is always 0
|
||||
rvdffs #(ICCM_BANK_BITS) rd_addr_hi_ff (.*, .clk(active_clk), .din(addr_bank_inc[ICCM_BANK_HI:2]), .dout(iccm_rd_addr_hi_q[ICCM_BANK_HI:2]), .en(1'b1));
|
||||
|
||||
assign iccm_rd_data_pre[63:0] = {iccm_bank_dout_fn[iccm_rd_addr_hi_q][31:0], iccm_bank_dout_fn[iccm_rd_addr_lo_q[ICCM_BANK_HI:2]][31:0]};
|
||||
assign iccm_data[63:0] = 64'({16'b0, (iccm_rd_data_pre[63:0] >> (16*iccm_rd_addr_lo_q[1]))});
|
||||
assign iccm_rd_data[63:0] = {iccm_data[63:0]};
|
||||
assign iccm_rd_data_ecc[77:0] = {iccm_bank_dout_fn[iccm_rd_addr_hi_q][38:0], iccm_bank_dout_fn[iccm_rd_addr_lo_q[ICCM_BANK_HI:2]][38:0]};
|
||||
|
||||
endmodule // ifu_iccm_mem
|
||||
|
|
@ -1,302 +0,0 @@
|
|||
// SPDX-License-Identifier: Apache-2.0
|
||||
// Copyright 2020 Western Digital Corporation or its affiliates.
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
//********************************************************************************
|
||||
// $Id$
|
||||
//
|
||||
//
|
||||
// Owner:
|
||||
// Function: DCCM for LSU pipe
|
||||
// Comments: Single ported memory
|
||||
//
|
||||
//
|
||||
// DC1 -> DC2 -> DC3 -> DC4 (Commit)
|
||||
//
|
||||
// //********************************************************************************
|
||||
|
||||
|
||||
|
||||
`define LOCAL_DCCM_RAM_TEST_PORTS .TEST1(dccm_ext_in_pkt[i].TEST1), \
|
||||
.RME(dccm_ext_in_pkt[i].RME), \
|
||||
.RM(dccm_ext_in_pkt[i].RM), \
|
||||
.LS(dccm_ext_in_pkt[i].LS), \
|
||||
.DS(dccm_ext_in_pkt[i].DS), \
|
||||
.SD(dccm_ext_in_pkt[i].SD), \
|
||||
.TEST_RNM(dccm_ext_in_pkt[i].TEST_RNM), \
|
||||
.BC1(dccm_ext_in_pkt[i].BC1), \
|
||||
.BC2(dccm_ext_in_pkt[i].BC2), \
|
||||
|
||||
|
||||
|
||||
module lsu_dccm_mem
|
||||
`include "parameter.sv"
|
||||
//#(
|
||||
|
||||
// parameter DCCM_BYTE_WIDTH,
|
||||
// parameter DCCM_BITS,
|
||||
// parameter DCCM_NUM_BANKS,
|
||||
// parameter DCCM_ENABLE= 'b1,
|
||||
// parameter DCCM_BANK_BITS,
|
||||
// parameter DCCM_SIZE,
|
||||
// parameter DCCM_FDATA_WIDTH,
|
||||
// parameter DCCM_WIDTH_BITS
|
||||
//)
|
||||
(
|
||||
input logic clk, // Clock only while core active. Through one clock header. For flops with second clock header built in. Connected to ACTIVE_L2CLK.
|
||||
input logic active_clk, // Clock only while core active. Through two clock headers. For flops without second clock header built in.
|
||||
input logic rst_l, // reset, active low
|
||||
input logic clk_override, // Override non-functional clock gating
|
||||
|
||||
input logic dccm_wren, // write enable
|
||||
input logic dccm_rden, // read enable
|
||||
input logic [DCCM_BITS-1:0] dccm_wr_addr_lo, // write address
|
||||
input logic [DCCM_BITS-1:0] dccm_wr_addr_hi, // write address
|
||||
input logic [DCCM_BITS-1:0] dccm_rd_addr_lo, // read address
|
||||
input logic [DCCM_BITS-1:0] dccm_rd_addr_hi, // read address for the upper bank in case of a misaligned access
|
||||
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, // write data
|
||||
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, // write data
|
||||
input dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt, // the dccm packet from the soc
|
||||
|
||||
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // read data from the lo bank
|
||||
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // read data from the hi bank
|
||||
|
||||
input logic scan_mode
|
||||
);
|
||||
|
||||
|
||||
//localparam DCCM_WIDTH_BITS = $clog2(DCCM_BYTE_WIDTH);
|
||||
localparam DCCM_INDEX_BITS = (DCCM_BITS - DCCM_BANK_BITS - DCCM_WIDTH_BITS);
|
||||
localparam DCCM_INDEX_DEPTH = ((DCCM_SIZE)*1024)/((DCCM_BYTE_WIDTH)*(DCCM_NUM_BANKS)); // Depth of memory bank
|
||||
|
||||
logic [DCCM_NUM_BANKS-1:0] wren_bank;
|
||||
logic [DCCM_NUM_BANKS-1:0] rden_bank;
|
||||
logic [DCCM_NUM_BANKS-1:0] [DCCM_BITS-1:(DCCM_BANK_BITS+2)] addr_bank;
|
||||
logic [DCCM_BITS-1:(DCCM_BANK_BITS+DCCM_WIDTH_BITS)] rd_addr_even, rd_addr_odd;
|
||||
logic rd_unaligned, wr_unaligned;
|
||||
logic [DCCM_NUM_BANKS-1:0] [DCCM_FDATA_WIDTH-1:0] dccm_bank_dout;
|
||||
logic [DCCM_FDATA_WIDTH-1:0] wrdata;
|
||||
|
||||
logic [DCCM_NUM_BANKS-1:0][DCCM_FDATA_WIDTH-1:0] wr_data_bank;
|
||||
|
||||
logic [(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_lo_q;
|
||||
logic [(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_hi_q;
|
||||
|
||||
logic [DCCM_NUM_BANKS-1:0] dccm_clken;
|
||||
|
||||
assign rd_unaligned = (dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]);
|
||||
assign wr_unaligned = (dccm_wr_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_wr_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]);
|
||||
|
||||
// Align the read data
|
||||
assign dccm_rd_data_lo[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
|
||||
assign dccm_rd_data_hi[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
|
||||
|
||||
|
||||
// 8 Banks, 16KB each (2048 x 72)
|
||||
for (genvar i=0; i<DCCM_NUM_BANKS; i++) begin: mem_bank
|
||||
assign wren_bank[i] = dccm_wren & ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_wr_addr_lo[2+:DCCM_BANK_BITS] == i));
|
||||
assign rden_bank[i] = dccm_rden & ((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_rd_addr_lo[2+:DCCM_BANK_BITS] == i));
|
||||
assign addr_bank[i][(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] = wren_bank[i] ? (((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ?
|
||||
dccm_wr_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] :
|
||||
dccm_wr_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS]) :
|
||||
(((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) & rd_unaligned) ?
|
||||
dccm_rd_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] :
|
||||
dccm_rd_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS]);
|
||||
|
||||
assign wr_data_bank[i] = ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ? dccm_wr_data_hi[DCCM_FDATA_WIDTH-1:0] : dccm_wr_data_lo[DCCM_FDATA_WIDTH-1:0];
|
||||
|
||||
// clock gating section
|
||||
assign dccm_clken[i] = (wren_bank[i] | rden_bank[i] | clk_override) ;
|
||||
// end clock gating section
|
||||
|
||||
`ifdef VERILATOR
|
||||
|
||||
ram #(DCCM_INDEX_DEPTH,39) ram (
|
||||
// Primary ports
|
||||
.ME(dccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
`LOCAL_DCCM_RAM_TEST_PORTS
|
||||
.*
|
||||
);
|
||||
`else
|
||||
|
||||
if (DCCM_INDEX_DEPTH == 32768) begin : dccm
|
||||
ram_32768x39 dccm_bank (
|
||||
// Primary ports
|
||||
.ME(dccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
`LOCAL_DCCM_RAM_TEST_PORTS
|
||||
.*
|
||||
);
|
||||
end
|
||||
else if (DCCM_INDEX_DEPTH == 16384) begin : dccm
|
||||
ram_16384x39 dccm_bank (
|
||||
// Primary ports
|
||||
.ME(dccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
`LOCAL_DCCM_RAM_TEST_PORTS
|
||||
.*
|
||||
);
|
||||
end
|
||||
else if (DCCM_INDEX_DEPTH == 8192) begin : dccm
|
||||
ram_8192x39 dccm_bank (
|
||||
// Primary ports
|
||||
.ME(dccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
`LOCAL_DCCM_RAM_TEST_PORTS
|
||||
.*
|
||||
);
|
||||
end
|
||||
else if (DCCM_INDEX_DEPTH == 4096) begin : dccm
|
||||
ram_4096x39 dccm_bank (
|
||||
// Primary ports
|
||||
.ME(dccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
`LOCAL_DCCM_RAM_TEST_PORTS
|
||||
.*
|
||||
);
|
||||
end
|
||||
else if (DCCM_INDEX_DEPTH == 3072) begin : dccm
|
||||
ram_3072x39 dccm_bank (
|
||||
// Primary ports
|
||||
.ME(dccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
`LOCAL_DCCM_RAM_TEST_PORTS
|
||||
.*
|
||||
);
|
||||
end
|
||||
else if (DCCM_INDEX_DEPTH == 2048) begin : dccm
|
||||
ram_2048x39 dccm_bank (
|
||||
// Primary ports
|
||||
.ME(dccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
`LOCAL_DCCM_RAM_TEST_PORTS
|
||||
.*
|
||||
);
|
||||
end
|
||||
else if (DCCM_INDEX_DEPTH == 1024) begin : dccm
|
||||
ram_1024x39 dccm_bank (
|
||||
// Primary ports
|
||||
.ME(dccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
`LOCAL_DCCM_RAM_TEST_PORTS
|
||||
.*
|
||||
);
|
||||
end
|
||||
else if (DCCM_INDEX_DEPTH == 512) begin : dccm
|
||||
ram_512x39 dccm_bank (
|
||||
// Primary ports
|
||||
.ME(dccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
`LOCAL_DCCM_RAM_TEST_PORTS
|
||||
.*
|
||||
);
|
||||
end
|
||||
else if (DCCM_INDEX_DEPTH == 256) begin : dccm
|
||||
ram_256x39 dccm_bank (
|
||||
// Primary ports
|
||||
.ME(dccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
`LOCAL_DCCM_RAM_TEST_PORTS
|
||||
.*
|
||||
);
|
||||
end
|
||||
else if (DCCM_INDEX_DEPTH == 128) begin : dccm
|
||||
ram_128x39 dccm_bank (
|
||||
// Primary ports
|
||||
.ME(dccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.ROP ( ),
|
||||
// These are used by SoC
|
||||
`LOCAL_DCCM_RAM_TEST_PORTS
|
||||
.*
|
||||
);
|
||||
end
|
||||
`endif
|
||||
|
||||
end : mem_bank
|
||||
|
||||
// Flops
|
||||
rvdff #(DCCM_BANK_BITS) rd_addr_lo_ff (.*, .din(dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .clk(active_clk));
|
||||
rvdff #(DCCM_BANK_BITS) rd_addr_hi_ff (.*, .din(dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .clk(active_clk));
|
||||
|
||||
`undef LOCAL_DCCM_RAM_TEST_PORTS
|
||||
|
||||
endmodule // lsu_dccm_mem
|
||||
|
||||
|
||||
|
|
@ -1,458 +0,0 @@
|
|||
//********************************************************************************
|
||||
// SPDX-License-Identifier: Apache-2.0
|
||||
// Copyright 2020 Western Digital Corporation or its affiliates.
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//********************************************************************************
|
||||
|
||||
// `include "lsu_dccm_mem.sv"
|
||||
// `include "ifu_ic_mem.sv"
|
||||
// `include "ifu_iccm_mem.sv"
|
||||
module mem
|
||||
`include "parameter.sv"
|
||||
(
|
||||
input logic clk,
|
||||
input logic rst_l,
|
||||
input logic dccm_clk_override,
|
||||
input logic icm_clk_override,
|
||||
input logic dec_tlu_core_ecc_disable,
|
||||
|
||||
//DCCM ports
|
||||
input logic dccm_wren,
|
||||
input logic dccm_rden,
|
||||
input logic [DCCM_BITS-1:0] dccm_wr_addr_lo,
|
||||
input logic [DCCM_BITS-1:0] dccm_wr_addr_hi,
|
||||
input logic [DCCM_BITS-1:0] dccm_rd_addr_lo,
|
||||
input logic [DCCM_BITS-1:0] dccm_rd_addr_hi,
|
||||
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
|
||||
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
|
||||
|
||||
|
||||
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
|
||||
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
|
||||
|
||||
//`ifdef DCCM_ENABLE
|
||||
//input dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt,
|
||||
input logic dccm_ext_in_pkt_TEST1_0,
|
||||
input logic dccm_ext_in_pkt_RME_0,
|
||||
input logic [3:0] dccm_ext_in_pkt_RM_0,
|
||||
input logic dccm_ext_in_pkt_LS_0,
|
||||
input logic dccm_ext_in_pkt_DS_0,
|
||||
input logic dccm_ext_in_pkt_SD_0,
|
||||
input logic dccm_ext_in_pkt_TEST_RNM_0,
|
||||
input logic dccm_ext_in_pkt_BC1_0,
|
||||
input logic dccm_ext_in_pkt_BC2_0,
|
||||
|
||||
input logic dccm_ext_in_pkt_TEST1_1,
|
||||
input logic dccm_ext_in_pkt_RME_1,
|
||||
input logic [3:0] dccm_ext_in_pkt_RM_1,
|
||||
input logic dccm_ext_in_pkt_LS_1,
|
||||
input logic dccm_ext_in_pkt_DS_1,
|
||||
input logic dccm_ext_in_pkt_SD_1,
|
||||
input logic dccm_ext_in_pkt_TEST_RNM_1,
|
||||
input logic dccm_ext_in_pkt_BC1_1,
|
||||
input logic dccm_ext_in_pkt_BC2_1,
|
||||
|
||||
input logic dccm_ext_in_pkt_TEST1_2,
|
||||
input logic dccm_ext_in_pkt_RME_2,
|
||||
input logic [3:0] dccm_ext_in_pkt_RM_2,
|
||||
input logic dccm_ext_in_pkt_LS_2,
|
||||
input logic dccm_ext_in_pkt_DS_2,
|
||||
input logic dccm_ext_in_pkt_SD_2,
|
||||
input logic dccm_ext_in_pkt_TEST_RNM_2,
|
||||
input logic dccm_ext_in_pkt_BC1_2,
|
||||
input logic dccm_ext_in_pkt_BC2_2,
|
||||
|
||||
input logic dccm_ext_in_pkt_TEST1_3,
|
||||
input logic dccm_ext_in_pkt_RME_3,
|
||||
input logic [3:0] dccm_ext_in_pkt_RM_3,
|
||||
input logic dccm_ext_in_pkt_LS_3,
|
||||
input logic dccm_ext_in_pkt_DS_3,
|
||||
input logic dccm_ext_in_pkt_SD_3,
|
||||
input logic dccm_ext_in_pkt_TEST_RNM_3,
|
||||
input logic dccm_ext_in_pkt_BC1_3,
|
||||
input logic dccm_ext_in_pkt_BC2_3,
|
||||
|
||||
//`endif
|
||||
|
||||
//ICCM ports
|
||||
input logic iccm_ext_in_pkt_TEST1_0,
|
||||
input logic iccm_ext_in_pkt_RME_0,
|
||||
input logic [3:0] iccm_ext_in_pkt_RM_0,
|
||||
input logic iccm_ext_in_pkt_LS_0,
|
||||
input logic iccm_ext_in_pkt_DS_0,
|
||||
input logic iccm_ext_in_pkt_SD_0,
|
||||
input logic iccm_ext_in_pkt_TEST_RNM_0,
|
||||
input logic iccm_ext_in_pkt_BC1_0,
|
||||
input logic iccm_ext_in_pkt_BC2_0,
|
||||
|
||||
input logic iccm_ext_in_pkt_TEST1_1,
|
||||
input logic iccm_ext_in_pkt_RME_1,
|
||||
input logic [3:0] iccm_ext_in_pkt_RM_1,
|
||||
input logic iccm_ext_in_pkt_LS_1,
|
||||
input logic iccm_ext_in_pkt_DS_1,
|
||||
input logic iccm_ext_in_pkt_SD_1,
|
||||
input logic iccm_ext_in_pkt_TEST_RNM_1,
|
||||
input logic iccm_ext_in_pkt_BC1_1,
|
||||
input logic iccm_ext_in_pkt_BC2_1,
|
||||
|
||||
input logic iccm_ext_in_pkt_TEST1_2,
|
||||
input logic iccm_ext_in_pkt_RME_2,
|
||||
input logic [3:0] iccm_ext_in_pkt_RM_2,
|
||||
input logic iccm_ext_in_pkt_LS_2,
|
||||
input logic iccm_ext_in_pkt_DS_2,
|
||||
input logic iccm_ext_in_pkt_SD_2,
|
||||
input logic iccm_ext_in_pkt_TEST_RNM_2,
|
||||
input logic iccm_ext_in_pkt_BC1_2,
|
||||
input logic iccm_ext_in_pkt_BC2_2,
|
||||
|
||||
input logic iccm_ext_in_pkt_TEST1_3,
|
||||
input logic iccm_ext_in_pkt_RME_3,
|
||||
input logic [3:0] iccm_ext_in_pkt_RM_3,
|
||||
input logic iccm_ext_in_pkt_LS_3,
|
||||
input logic iccm_ext_in_pkt_DS_3,
|
||||
input logic iccm_ext_in_pkt_SD_3,
|
||||
input logic iccm_ext_in_pkt_TEST_RNM_3,
|
||||
input logic iccm_ext_in_pkt_BC1_3,
|
||||
input logic iccm_ext_in_pkt_BC2_3,
|
||||
|
||||
input logic [ICCM_BITS-1:1] iccm_rw_addr,
|
||||
input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
|
||||
input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle
|
||||
input logic iccm_wren,
|
||||
input logic iccm_rden,
|
||||
input logic [2:0] iccm_wr_size,
|
||||
input logic [77:0] iccm_wr_data,
|
||||
|
||||
output logic [63:0] iccm_rd_data,
|
||||
output logic [77:0] iccm_rd_data_ecc,
|
||||
|
||||
// Icache and Itag Ports
|
||||
|
||||
input logic [31:1] ic_rw_addr,
|
||||
input logic [ICACHE_NUM_WAYS-1:0] ic_tag_valid,
|
||||
input logic [ICACHE_NUM_WAYS-1:0] ic_wr_en,
|
||||
input logic ic_rd_en,
|
||||
input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
|
||||
input logic ic_sel_premux_data, // Premux data sel
|
||||
// input ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
|
||||
input logic ic_tag_ext_in_pkt_TEST1_0,
|
||||
input logic ic_tag_ext_in_pkt_RME_0,
|
||||
input logic [3:0] ic_tag_ext_in_pkt_RM_0,
|
||||
input logic ic_tag_ext_in_pkt_LS_0,
|
||||
input logic ic_tag_ext_in_pkt_DS_0,
|
||||
input logic ic_tag_ext_in_pkt_SD_0,
|
||||
input logic ic_tag_ext_in_pkt_TEST_RNM_0,
|
||||
input logic ic_tag_ext_in_pkt_BC1_0,
|
||||
input logic ic_tag_ext_in_pkt_BC2_0,
|
||||
|
||||
input logic ic_tag_ext_in_pkt_TEST1_1,
|
||||
input logic ic_tag_ext_in_pkt_RME_1,
|
||||
input logic [3:0] ic_tag_ext_in_pkt_RM_1,
|
||||
input logic ic_tag_ext_in_pkt_LS_1,
|
||||
input logic ic_tag_ext_in_pkt_DS_1,
|
||||
input logic ic_tag_ext_in_pkt_SD_1,
|
||||
input logic ic_tag_ext_in_pkt_TEST_RNM_1,
|
||||
input logic ic_tag_ext_in_pkt_BC1_1,
|
||||
input logic ic_tag_ext_in_pkt_BC2_1,
|
||||
|
||||
input logic ic_data_ext_in_pkt_0_TEST1_0,
|
||||
input logic ic_data_ext_in_pkt_0_RME_0,
|
||||
input logic [3:0] ic_data_ext_in_pkt_0_RM_0,
|
||||
input logic ic_data_ext_in_pkt_0_LS_0,
|
||||
input logic ic_data_ext_in_pkt_0_DS_0,
|
||||
input logic ic_data_ext_in_pkt_0_SD_0,
|
||||
input logic ic_data_ext_in_pkt_0_TEST_RNM_0,
|
||||
input logic ic_data_ext_in_pkt_0_BC1_0,
|
||||
input logic ic_data_ext_in_pkt_0_BC2_0,
|
||||
|
||||
input logic ic_data_ext_in_pkt_0_TEST1_1,
|
||||
input logic ic_data_ext_in_pkt_0_RME_1,
|
||||
input logic [3:0] ic_data_ext_in_pkt_0_RM_1,
|
||||
input logic ic_data_ext_in_pkt_0_LS_1,
|
||||
input logic ic_data_ext_in_pkt_0_DS_1,
|
||||
input logic ic_data_ext_in_pkt_0_SD_1,
|
||||
input logic ic_data_ext_in_pkt_0_TEST_RNM_1,
|
||||
input logic ic_data_ext_in_pkt_0_BC1_1,
|
||||
input logic ic_data_ext_in_pkt_0_BC2_1,
|
||||
|
||||
input logic ic_data_ext_in_pkt_1_TEST1_0,
|
||||
input logic ic_data_ext_in_pkt_1_RME_0,
|
||||
input logic [3:0] ic_data_ext_in_pkt_1_RM_0,
|
||||
input logic ic_data_ext_in_pkt_1_LS_0,
|
||||
input logic ic_data_ext_in_pkt_1_DS_0,
|
||||
input logic ic_data_ext_in_pkt_1_SD_0,
|
||||
input logic ic_data_ext_in_pkt_1_TEST_RNM_0,
|
||||
input logic ic_data_ext_in_pkt_1_BC1_0,
|
||||
input logic ic_data_ext_in_pkt_1_BC2_0,
|
||||
|
||||
input logic ic_data_ext_in_pkt_1_TEST1_1,
|
||||
input logic ic_data_ext_in_pkt_1_RME_1,
|
||||
input logic [3:0] ic_data_ext_in_pkt_1_RM_1,
|
||||
input logic ic_data_ext_in_pkt_1_LS_1,
|
||||
input logic ic_data_ext_in_pkt_1_DS_1,
|
||||
input logic ic_data_ext_in_pkt_1_SD_1,
|
||||
input logic ic_data_ext_in_pkt_1_TEST_RNM_1,
|
||||
input logic ic_data_ext_in_pkt_1_BC1_1,
|
||||
input logic ic_data_ext_in_pkt_1_BC2_1,
|
||||
//input ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt,
|
||||
// input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
|
||||
input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC
|
||||
input logic [70:0] ic_wr_data_1, // Data to fill to the Icache. With ECC
|
||||
input logic [70:0] ic_debug_wr_data, // Debug wr cache.
|
||||
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
|
||||
input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
|
||||
input logic ic_debug_rd_en, // Icache debug rd
|
||||
input logic ic_debug_wr_en, // Icache debug wr
|
||||
input logic ic_debug_tag_array, // Debug tag array
|
||||
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
|
||||
|
||||
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
|
||||
output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag.
|
||||
|
||||
|
||||
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
|
||||
output logic [ICACHE_BANKS_WAY-1:0] ic_parerr, // parity error per bank
|
||||
output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit,
|
||||
output logic ic_tag_perr, // Icache Tag parity error
|
||||
|
||||
|
||||
input logic scan_mode
|
||||
);
|
||||
|
||||
iccm_ext_in_pkt_t [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt;
|
||||
dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt;
|
||||
ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt;
|
||||
ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt;
|
||||
|
||||
|
||||
assign dccm_ext_in_pkt[0].TEST1 = dccm_ext_in_pkt_TEST1_0;
|
||||
assign dccm_ext_in_pkt[0].RME = dccm_ext_in_pkt_RME_0;
|
||||
assign dccm_ext_in_pkt[0].RM = dccm_ext_in_pkt_RM_0[3:0];
|
||||
assign dccm_ext_in_pkt[0].LS = dccm_ext_in_pkt_LS_0;
|
||||
assign dccm_ext_in_pkt[0].DS = dccm_ext_in_pkt_DS_0;
|
||||
assign dccm_ext_in_pkt[0].SD = dccm_ext_in_pkt_SD_0;
|
||||
assign dccm_ext_in_pkt[0].TEST_RNM = dccm_ext_in_pkt_TEST_RNM_0;
|
||||
assign dccm_ext_in_pkt[0].BC1 = dccm_ext_in_pkt_BC1_0;
|
||||
assign dccm_ext_in_pkt[0].BC2 = dccm_ext_in_pkt_BC2_0;
|
||||
|
||||
assign dccm_ext_in_pkt[1].TEST1 = dccm_ext_in_pkt_TEST1_1;
|
||||
assign dccm_ext_in_pkt[1].RME = dccm_ext_in_pkt_RME_1;
|
||||
assign dccm_ext_in_pkt[1].RM = dccm_ext_in_pkt_RM_1[3:0];
|
||||
assign dccm_ext_in_pkt[1].LS = dccm_ext_in_pkt_LS_1;
|
||||
assign dccm_ext_in_pkt[1].DS = dccm_ext_in_pkt_DS_1;
|
||||
assign dccm_ext_in_pkt[1].SD = dccm_ext_in_pkt_SD_1;
|
||||
assign dccm_ext_in_pkt[1].TEST_RNM = dccm_ext_in_pkt_TEST_RNM_1;
|
||||
assign dccm_ext_in_pkt[1].BC1 = dccm_ext_in_pkt_BC1_1;
|
||||
assign dccm_ext_in_pkt[1].BC2 = dccm_ext_in_pkt_BC2_1;
|
||||
|
||||
|
||||
assign dccm_ext_in_pkt[2].TEST1 = dccm_ext_in_pkt_TEST1_2;
|
||||
assign dccm_ext_in_pkt[2].RME = dccm_ext_in_pkt_RME_2;
|
||||
assign dccm_ext_in_pkt[2].RM = dccm_ext_in_pkt_RM_2[3:0];
|
||||
assign dccm_ext_in_pkt[2].LS = dccm_ext_in_pkt_LS_2;
|
||||
assign dccm_ext_in_pkt[2].DS = dccm_ext_in_pkt_DS_2;
|
||||
assign dccm_ext_in_pkt[2].SD = dccm_ext_in_pkt_SD_2;
|
||||
assign dccm_ext_in_pkt[2].TEST_RNM = dccm_ext_in_pkt_TEST_RNM_2;
|
||||
assign dccm_ext_in_pkt[2].BC1 = dccm_ext_in_pkt_BC1_2;
|
||||
assign dccm_ext_in_pkt[2].BC2 = dccm_ext_in_pkt_BC2_2;
|
||||
|
||||
assign dccm_ext_in_pkt[3].TEST1 = dccm_ext_in_pkt_TEST1_3;
|
||||
assign dccm_ext_in_pkt[3].RME = dccm_ext_in_pkt_RME_3;
|
||||
assign dccm_ext_in_pkt[3].RM = dccm_ext_in_pkt_RM_3[3:0];
|
||||
assign dccm_ext_in_pkt[3].LS = dccm_ext_in_pkt_LS_3;
|
||||
assign dccm_ext_in_pkt[3].DS = dccm_ext_in_pkt_DS_3;
|
||||
assign dccm_ext_in_pkt[3].SD = dccm_ext_in_pkt_SD_3;
|
||||
assign dccm_ext_in_pkt[3].TEST_RNM = dccm_ext_in_pkt_TEST_RNM_3;
|
||||
assign dccm_ext_in_pkt[3].BC1 = dccm_ext_in_pkt_BC1_3;
|
||||
assign dccm_ext_in_pkt[3].BC2 = dccm_ext_in_pkt_BC2_3;
|
||||
|
||||
assign iccm_ext_in_pkt[0].TEST1 = iccm_ext_in_pkt_TEST1_0;
|
||||
assign iccm_ext_in_pkt[0].RME = iccm_ext_in_pkt_RME_0;
|
||||
assign iccm_ext_in_pkt[0].RM = iccm_ext_in_pkt_RM_0[3:0];
|
||||
assign iccm_ext_in_pkt[0].LS = iccm_ext_in_pkt_LS_0;
|
||||
assign iccm_ext_in_pkt[0].DS = iccm_ext_in_pkt_DS_0;
|
||||
assign iccm_ext_in_pkt[0].SD = iccm_ext_in_pkt_SD_0;
|
||||
assign iccm_ext_in_pkt[0].TEST_RNM = iccm_ext_in_pkt_TEST_RNM_0;
|
||||
assign iccm_ext_in_pkt[0].BC1 = iccm_ext_in_pkt_BC1_0;
|
||||
assign iccm_ext_in_pkt[0].BC2 = iccm_ext_in_pkt_BC2_0;
|
||||
|
||||
assign iccm_ext_in_pkt[1].TEST1 = iccm_ext_in_pkt_TEST1_1;
|
||||
assign iccm_ext_in_pkt[1].RME = iccm_ext_in_pkt_RME_1;
|
||||
assign iccm_ext_in_pkt[1].RM = iccm_ext_in_pkt_RM_1[3:0];
|
||||
assign iccm_ext_in_pkt[1].LS = iccm_ext_in_pkt_LS_1;
|
||||
assign iccm_ext_in_pkt[1].DS = iccm_ext_in_pkt_DS_1;
|
||||
assign iccm_ext_in_pkt[1].SD = iccm_ext_in_pkt_SD_1;
|
||||
assign iccm_ext_in_pkt[1].TEST_RNM = iccm_ext_in_pkt_TEST_RNM_1;
|
||||
assign iccm_ext_in_pkt[1].BC1 = iccm_ext_in_pkt_BC1_1;
|
||||
assign iccm_ext_in_pkt[1].BC2 = iccm_ext_in_pkt_BC2_1;
|
||||
|
||||
|
||||
assign iccm_ext_in_pkt[2].TEST1 = iccm_ext_in_pkt_TEST1_2;
|
||||
assign iccm_ext_in_pkt[2].RME = iccm_ext_in_pkt_RME_2;
|
||||
assign iccm_ext_in_pkt[2].RM = iccm_ext_in_pkt_RM_2[3:0];
|
||||
assign iccm_ext_in_pkt[2].LS = iccm_ext_in_pkt_LS_2;
|
||||
assign iccm_ext_in_pkt[2].DS = iccm_ext_in_pkt_DS_2;
|
||||
assign iccm_ext_in_pkt[2].SD = iccm_ext_in_pkt_SD_2;
|
||||
assign iccm_ext_in_pkt[2].TEST_RNM = iccm_ext_in_pkt_TEST_RNM_2;
|
||||
assign iccm_ext_in_pkt[2].BC1 = iccm_ext_in_pkt_BC1_2;
|
||||
assign iccm_ext_in_pkt[2].BC2 = iccm_ext_in_pkt_BC2_2;
|
||||
|
||||
assign iccm_ext_in_pkt[3].TEST1 = iccm_ext_in_pkt_TEST1_3;
|
||||
assign iccm_ext_in_pkt[3].RME = iccm_ext_in_pkt_RME_3;
|
||||
assign iccm_ext_in_pkt[3].RM = iccm_ext_in_pkt_RM_3[3:0];
|
||||
assign iccm_ext_in_pkt[3].LS = iccm_ext_in_pkt_LS_3;
|
||||
assign iccm_ext_in_pkt[3].DS = iccm_ext_in_pkt_DS_3;
|
||||
assign iccm_ext_in_pkt[3].SD = iccm_ext_in_pkt_SD_3;
|
||||
assign iccm_ext_in_pkt[3].TEST_RNM = iccm_ext_in_pkt_TEST_RNM_3;
|
||||
assign iccm_ext_in_pkt[3].BC1 = iccm_ext_in_pkt_BC1_3;
|
||||
assign iccm_ext_in_pkt[3].BC2 = iccm_ext_in_pkt_BC2_3;
|
||||
|
||||
|
||||
assign ic_tag_ext_in_pkt[0].TEST1 = ic_tag_ext_in_pkt_TEST1_0;
|
||||
assign ic_tag_ext_in_pkt[0].RME = ic_tag_ext_in_pkt_RME_0;
|
||||
assign ic_tag_ext_in_pkt[0].RM = ic_tag_ext_in_pkt_RM_0[3:0];
|
||||
assign ic_tag_ext_in_pkt[0].LS = ic_tag_ext_in_pkt_LS_0;
|
||||
assign ic_tag_ext_in_pkt[0].DS = ic_tag_ext_in_pkt_DS_0;
|
||||
assign ic_tag_ext_in_pkt[0].SD = ic_tag_ext_in_pkt_SD_0;
|
||||
assign ic_tag_ext_in_pkt[0].TEST_RNM = ic_tag_ext_in_pkt_TEST_RNM_0;
|
||||
assign ic_tag_ext_in_pkt[0].BC1 = ic_tag_ext_in_pkt_BC1_0;
|
||||
assign ic_tag_ext_in_pkt[0].BC2 = ic_tag_ext_in_pkt_BC2_0;
|
||||
|
||||
assign ic_tag_ext_in_pkt[1].TEST1 = ic_tag_ext_in_pkt_TEST1_1;
|
||||
assign ic_tag_ext_in_pkt[1].RME = ic_tag_ext_in_pkt_RME_1;
|
||||
assign ic_tag_ext_in_pkt[1].RM = ic_tag_ext_in_pkt_RM_1[3:0];
|
||||
assign ic_tag_ext_in_pkt[1].LS = ic_tag_ext_in_pkt_LS_1;
|
||||
assign ic_tag_ext_in_pkt[1].DS = ic_tag_ext_in_pkt_DS_1;
|
||||
assign ic_tag_ext_in_pkt[1].SD = ic_tag_ext_in_pkt_SD_1;
|
||||
assign ic_tag_ext_in_pkt[1].TEST_RNM = ic_tag_ext_in_pkt_TEST_RNM_1;
|
||||
assign ic_tag_ext_in_pkt[1].BC1 = ic_tag_ext_in_pkt_BC1_1;
|
||||
assign ic_tag_ext_in_pkt[1].BC2 = ic_tag_ext_in_pkt_BC2_1;
|
||||
|
||||
// PKT connection
|
||||
assign ic_data_ext_in_pkt[0][0].TEST1 = ic_data_ext_in_pkt_0_TEST1_0;
|
||||
assign ic_data_ext_in_pkt[0][0].RME = ic_data_ext_in_pkt_0_RME_0;
|
||||
assign ic_data_ext_in_pkt[0][0].RM = ic_data_ext_in_pkt_0_RM_0[3:0];
|
||||
assign ic_data_ext_in_pkt[0][0].LS = ic_data_ext_in_pkt_0_LS_0;
|
||||
assign ic_data_ext_in_pkt[0][0].DS = ic_data_ext_in_pkt_0_DS_0;
|
||||
assign ic_data_ext_in_pkt[0][0].SD = ic_data_ext_in_pkt_0_SD_0;
|
||||
assign ic_data_ext_in_pkt[0][0].TEST_RNM = ic_data_ext_in_pkt_0_TEST_RNM_0;
|
||||
assign ic_data_ext_in_pkt[0][0].BC1 = ic_data_ext_in_pkt_0_BC1_0;
|
||||
assign ic_data_ext_in_pkt[0][0].BC2 = ic_data_ext_in_pkt_0_BC2_0;
|
||||
|
||||
assign ic_data_ext_in_pkt[0][1].TEST1 = ic_data_ext_in_pkt_1_TEST1_1;
|
||||
assign ic_data_ext_in_pkt[0][1].RME = ic_data_ext_in_pkt_1_RME_1;
|
||||
assign ic_data_ext_in_pkt[0][1].RM = ic_data_ext_in_pkt_1_RM_1[3:0];
|
||||
assign ic_data_ext_in_pkt[0][1].LS = ic_data_ext_in_pkt_1_LS_1;
|
||||
assign ic_data_ext_in_pkt[0][1].DS = ic_data_ext_in_pkt_1_DS_1;
|
||||
assign ic_data_ext_in_pkt[0][1].SD = ic_data_ext_in_pkt_1_SD_1;
|
||||
assign ic_data_ext_in_pkt[0][1].TEST_RNM = ic_data_ext_in_pkt_1_TEST_RNM_1;
|
||||
assign ic_data_ext_in_pkt[0][1].BC1 = ic_data_ext_in_pkt_1_BC1_1;
|
||||
assign ic_data_ext_in_pkt[0][1].BC2 = ic_data_ext_in_pkt_1_BC2_1;
|
||||
|
||||
assign ic_data_ext_in_pkt[1][0].TEST1 = ic_data_ext_in_pkt_1_TEST1_0;
|
||||
assign ic_data_ext_in_pkt[1][0].RME = ic_data_ext_in_pkt_1_RME_0;
|
||||
assign ic_data_ext_in_pkt[1][0].RM = ic_data_ext_in_pkt_1_RM_0[3:0];
|
||||
assign ic_data_ext_in_pkt[1][0].LS = ic_data_ext_in_pkt_1_LS_0;
|
||||
assign ic_data_ext_in_pkt[1][0].DS = ic_data_ext_in_pkt_1_DS_0;
|
||||
assign ic_data_ext_in_pkt[1][0].SD = ic_data_ext_in_pkt_1_SD_0;
|
||||
assign ic_data_ext_in_pkt[1][0].TEST_RNM = ic_data_ext_in_pkt_1_TEST_RNM_0;
|
||||
assign ic_data_ext_in_pkt[1][0].BC1 = ic_data_ext_in_pkt_1_BC1_0;
|
||||
assign ic_data_ext_in_pkt[1][0].BC2 = ic_data_ext_in_pkt_1_BC2_0;
|
||||
|
||||
assign ic_data_ext_in_pkt[1][1].TEST1 = ic_data_ext_in_pkt_1_TEST1_1;
|
||||
assign ic_data_ext_in_pkt[1][1].RME = ic_data_ext_in_pkt_1_RME_1;
|
||||
assign ic_data_ext_in_pkt[1][1].RM = ic_data_ext_in_pkt_1_RM_1[3:0];
|
||||
assign ic_data_ext_in_pkt[1][1].LS = ic_data_ext_in_pkt_1_LS_1;
|
||||
assign ic_data_ext_in_pkt[1][1].DS = ic_data_ext_in_pkt_1_DS_1;
|
||||
assign ic_data_ext_in_pkt[1][1].SD = ic_data_ext_in_pkt_1_SD_1;
|
||||
assign ic_data_ext_in_pkt[1][1].TEST_RNM = ic_data_ext_in_pkt_1_TEST_RNM_1;
|
||||
assign ic_data_ext_in_pkt[1][1].BC1 = ic_data_ext_in_pkt_1_BC1_1;
|
||||
assign ic_data_ext_in_pkt[1][1].BC2 = ic_data_ext_in_pkt_1_BC2_1;
|
||||
|
||||
rvoclkhdr active_cg ( .en(1'b1), .l1clk(active_clk), .* );
|
||||
|
||||
// DCCM Instantiation
|
||||
if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
|
||||
lsu_dccm_mem #(
|
||||
.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
|
||||
.DCCM_BITS(DCCM_BITS),
|
||||
.DCCM_NUM_BANKS(DCCM_NUM_BANKS),
|
||||
.DCCM_BANK_BITS(DCCM_BANK_BITS),
|
||||
.DCCM_SIZE(DCCM_SIZE),
|
||||
.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH),
|
||||
.DCCM_WIDTH_BITS(DCCM_WIDTH_BITS)) dccm (
|
||||
.clk_override(dccm_clk_override),
|
||||
.*
|
||||
);
|
||||
end else begin: Gen_dccm_disable
|
||||
assign dccm_rd_data_lo = '0;
|
||||
assign dccm_rd_data_hi = '0;
|
||||
end
|
||||
|
||||
if ( ICACHE_ENABLE ) begin: icache
|
||||
ifu_ic_mem #(
|
||||
.ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
|
||||
.ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
|
||||
.ICACHE_BANK_BITS(ICACHE_BANK_BITS),
|
||||
.ICACHE_BEAT_ADDR_HI(ICACHE_BEAT_ADDR_HI),
|
||||
.ICACHE_BANKS_WAY(ICACHE_BANKS_WAY),
|
||||
.ICACHE_INDEX_HI(ICACHE_INDEX_HI),
|
||||
.ICACHE_BANK_HI(ICACHE_BANK_HI),
|
||||
.ICACHE_BANK_LO(ICACHE_BANK_LO),
|
||||
.ICACHE_TAG_LO(ICACHE_TAG_LO),
|
||||
.ICACHE_DATA_INDEX_LO(ICACHE_DATA_INDEX_LO),
|
||||
.ICACHE_ECC(ICACHE_ECC),
|
||||
.ICACHE_TAG_DEPTH(ICACHE_TAG_DEPTH),
|
||||
.ICACHE_WAYPACK(ICACHE_WAYPACK),
|
||||
.ICACHE_TAG_INDEX_LO(ICACHE_TAG_INDEX_LO),
|
||||
.ICACHE_DATA_DEPTH(ICACHE_DATA_DEPTH),
|
||||
.ICACHE_TAG_NUM_BYPASS(ICACHE_TAG_NUM_BYPASS),
|
||||
.ICACHE_TAG_NUM_BYPASS_WIDTH(ICACHE_TAG_NUM_BYPASS_WIDTH),
|
||||
.ICACHE_TAG_BYPASS_ENABLE(ICACHE_TAG_BYPASS_ENABLE),
|
||||
.ICACHE_NUM_BYPASS_WIDTH(ICACHE_NUM_BYPASS_WIDTH),
|
||||
.ICACHE_BYPASS_ENABLE(ICACHE_BYPASS_ENABLE),
|
||||
.ICACHE_LN_SZ(ICACHE_LN_SZ)) icm (
|
||||
.clk_override(icm_clk_override),
|
||||
.*
|
||||
);
|
||||
end
|
||||
else begin
|
||||
assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
|
||||
assign ic_tag_perr = '0 ;
|
||||
assign ic_rd_data = '0 ;
|
||||
assign ic_tag_debug_rd_data = '0 ;
|
||||
end // else: !if( ICACHE_ENABLE )
|
||||
|
||||
|
||||
|
||||
if (ICCM_ENABLE) begin : iccm
|
||||
ifu_iccm_mem #(
|
||||
.ICCM_BITS(ICCM_BITS),
|
||||
.ICCM_BANK_INDEX_LO(ICCM_BANK_INDEX_LO),
|
||||
.ICCM_INDEX_BITS(ICCM_INDEX_BITS),
|
||||
.ICCM_BANK_HI(ICCM_BANK_HI),
|
||||
.ICCM_NUM_BANKS(ICCM_NUM_BANKS),
|
||||
.ICCM_BANK_BITS(ICCM_BANK_BITS)) iccm (.*,
|
||||
.clk_override(icm_clk_override),
|
||||
.iccm_rw_addr(iccm_rw_addr[ICCM_BITS-1:1]),
|
||||
.iccm_rd_data(iccm_rd_data[63:0])
|
||||
);
|
||||
end
|
||||
else begin
|
||||
assign iccm_rd_data = '0 ;
|
||||
assign iccm_rd_data_ecc = '0 ;
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,242 +0,0 @@
|
|||
// SPDX-License-Identifier: Apache-2.0
|
||||
// Copyright 2020 Western Digital Corporation or it's affiliates.
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
`define LOCAL_RAM_TEST_IO \
|
||||
input logic WE, \
|
||||
input logic ME, \
|
||||
input logic CLK, \
|
||||
input logic TEST1, \
|
||||
input logic RME, \
|
||||
input logic [3:0] RM, \
|
||||
input logic LS, \
|
||||
input logic DS, \
|
||||
input logic SD, \
|
||||
input logic TEST_RNM, \
|
||||
input logic BC1, \
|
||||
input logic BC2, \
|
||||
output logic ROP
|
||||
|
||||
`define RAM(depth, width) \
|
||||
module ram_``depth``x``width( \
|
||||
input logic [$clog2(depth)-1:0] ADR, \
|
||||
input logic [(width-1):0] D, \
|
||||
output logic [(width-1):0] Q, \
|
||||
`LOCAL_RAM_TEST_IO \
|
||||
); \
|
||||
reg [(width-1):0] ram_core [(depth-1):0]; \
|
||||
`ifdef GTLSIM \
|
||||
integer i; \
|
||||
initial begin \
|
||||
for (i=0; i<depth; i=i+1) \
|
||||
ram_core[i] = '0; \
|
||||
end \
|
||||
`endif \
|
||||
always @(posedge CLK) begin \
|
||||
`ifdef GTLSIM \
|
||||
if (ME && WE) ram_core[ADR] <= D; \
|
||||
`else \
|
||||
if (ME && WE) begin ram_core[ADR] <= D; Q <= 'x; end \
|
||||
`endif \
|
||||
if (ME && ~WE) Q <= ram_core[ADR]; \
|
||||
end \
|
||||
assign ROP = ME; \
|
||||
\
|
||||
endmodule
|
||||
|
||||
`define RAM_BE(depth, width) \
|
||||
module ram_be_``depth``x``width( \
|
||||
input logic [$clog2(depth)-1:0] ADR, \
|
||||
input logic [(width-1):0] D, WEM, \
|
||||
output logic [(width-1):0] Q, \
|
||||
`LOCAL_RAM_TEST_IO \
|
||||
); \
|
||||
reg [(width-1):0] ram_core [(depth-1):0]; \
|
||||
`ifdef GTLSIM \
|
||||
integer i; \
|
||||
initial begin \
|
||||
for (i=0; i<depth; i=i+1) \
|
||||
ram_core[i] = '0; \
|
||||
end \
|
||||
`endif \
|
||||
always @(posedge CLK) begin \
|
||||
`ifdef GTLSIM \
|
||||
if (ME && WE) ram_core[ADR] <= D & WEM | ~WEM & ram_core[ADR]; \
|
||||
`else \
|
||||
if (ME && WE) begin ram_core[ADR] <= D & WEM | ~WEM & ram_core[ADR]; Q <= 'x; end \
|
||||
`endif \
|
||||
if (ME && ~WE) Q <= ram_core[ADR]; \
|
||||
end \
|
||||
assign ROP = ME; \
|
||||
\
|
||||
endmodule
|
||||
|
||||
// parameterizable RAM for verilator sims
|
||||
module ram #(depth=4096, width=39) (
|
||||
input logic [$clog2(depth)-1:0] ADR,
|
||||
input logic [(width-1):0] D,
|
||||
output logic [(width-1):0] Q,
|
||||
`LOCAL_RAM_TEST_IO
|
||||
);
|
||||
reg [(width-1):0] ram_core [(depth-1):0];
|
||||
|
||||
always @(posedge CLK) begin
|
||||
`ifdef GTLSIM
|
||||
if (ME && WE) ram_core[ADR] <= D;
|
||||
`else
|
||||
if (ME && WE) begin ram_core[ADR] <= D; Q <= 'x; end
|
||||
`endif
|
||||
if (ME && ~WE) Q <= ram_core[ADR];
|
||||
end
|
||||
endmodule
|
||||
|
||||
//=========================================================================================================================
|
||||
//=================================== START OF CCM =======================================================================
|
||||
//============= Possible sram sizes for a 39 bit wide memory ( 4 bytes + 7 bits ECC ) =====================================
|
||||
//-------------------------------------------------------------------------------------------------------------------------
|
||||
`RAM(32768, 39)
|
||||
`RAM(16384, 39)
|
||||
`RAM(8192, 39)
|
||||
`RAM(4096, 39)
|
||||
`RAM(3072, 39)
|
||||
`RAM(2048, 39)
|
||||
`RAM(1536, 39) // need this for the 48KB DCCM option)
|
||||
`RAM(1024, 39)
|
||||
`RAM(768, 39)
|
||||
`RAM(512, 39)
|
||||
`RAM(256, 39)
|
||||
`RAM(128, 39)
|
||||
`RAM(1024, 20)
|
||||
`RAM(512, 20)
|
||||
`RAM(256, 20)
|
||||
`RAM(128, 20)
|
||||
`RAM(64, 20)
|
||||
`RAM(4096, 34)
|
||||
`RAM(2048, 34)
|
||||
`RAM(1024, 34)
|
||||
`RAM(512, 34)
|
||||
`RAM(256, 34)
|
||||
`RAM(128, 34)
|
||||
`RAM(64, 34)
|
||||
`RAM(8192, 68)
|
||||
`RAM(4096, 68)
|
||||
`RAM(2048, 68)
|
||||
`RAM(1024, 68)
|
||||
`RAM(512, 68)
|
||||
`RAM(256, 68)
|
||||
`RAM(128, 68)
|
||||
`RAM(64, 68)
|
||||
`RAM(8192, 71)
|
||||
`RAM(4096, 71)
|
||||
`RAM(2048, 71)
|
||||
`RAM(1024, 71)
|
||||
`RAM(512, 71)
|
||||
`RAM(256, 71)
|
||||
`RAM(128, 71)
|
||||
`RAM(64, 71)
|
||||
`RAM(4096, 42)
|
||||
`RAM(2048, 42)
|
||||
`RAM(1024, 42)
|
||||
`RAM(512, 42)
|
||||
`RAM(256, 42)
|
||||
`RAM(128, 42)
|
||||
`RAM(64, 42)
|
||||
`RAM(4096, 22)
|
||||
`RAM(2048, 22)
|
||||
`RAM(1024, 22)
|
||||
`RAM(512, 22)
|
||||
`RAM(256, 22)
|
||||
`RAM(128, 22)
|
||||
`RAM(64, 22)
|
||||
`RAM(1024, 26)
|
||||
`RAM(4096, 26)
|
||||
`RAM(2048, 26)
|
||||
`RAM(512, 26)
|
||||
`RAM(256, 26)
|
||||
`RAM(128, 26)
|
||||
`RAM(64, 26)
|
||||
`RAM(32, 26)
|
||||
`RAM(32, 22)
|
||||
`RAM_BE(8192, 142)
|
||||
`RAM_BE(4096, 142)
|
||||
`RAM_BE(2048, 142)
|
||||
`RAM_BE(1024, 142)
|
||||
`RAM_BE(512, 142)
|
||||
`RAM_BE(256, 142)
|
||||
`RAM_BE(128, 142)
|
||||
`RAM_BE(64, 142)
|
||||
`RAM_BE(8192, 284)
|
||||
`RAM_BE(4096, 284)
|
||||
`RAM_BE(2048, 284)
|
||||
`RAM_BE(1024, 284)
|
||||
`RAM_BE(512, 284)
|
||||
`RAM_BE(256, 284)
|
||||
`RAM_BE(128, 284)
|
||||
`RAM_BE(64, 284)
|
||||
`RAM_BE(8192, 136)
|
||||
`RAM_BE(4096, 136)
|
||||
`RAM_BE(2048, 136)
|
||||
`RAM_BE(1024, 136)
|
||||
`RAM_BE(512, 136)
|
||||
`RAM_BE(256, 136)
|
||||
`RAM_BE(128, 136)
|
||||
`RAM_BE(64, 136)
|
||||
`RAM_BE(8192, 272)
|
||||
`RAM_BE(4096, 272)
|
||||
`RAM_BE(2048, 272)
|
||||
`RAM_BE(1024, 272)
|
||||
`RAM_BE(512, 272)
|
||||
`RAM_BE(256, 272)
|
||||
`RAM_BE(128, 272)
|
||||
`RAM_BE(64, 272)
|
||||
`RAM_BE(4096, 52)
|
||||
`RAM_BE(2048, 52)
|
||||
`RAM_BE(1024, 52)
|
||||
`RAM_BE(512, 52)
|
||||
`RAM_BE(256, 52)
|
||||
`RAM_BE(128, 52)
|
||||
`RAM_BE(64, 52)
|
||||
`RAM_BE(32, 52)
|
||||
`RAM_BE(4096, 104)
|
||||
`RAM_BE(2048, 104)
|
||||
`RAM_BE(1024, 104)
|
||||
`RAM_BE(512, 104)
|
||||
`RAM_BE(256, 104)
|
||||
`RAM_BE(128, 104)
|
||||
`RAM_BE(64, 104)
|
||||
`RAM_BE(32, 104)
|
||||
`RAM_BE(4096, 44)
|
||||
`RAM_BE(2048, 44)
|
||||
`RAM_BE(1024, 44)
|
||||
`RAM_BE(512, 44)
|
||||
`RAM_BE(256, 44)
|
||||
`RAM_BE(128, 44)
|
||||
`RAM_BE(64, 44)
|
||||
`RAM_BE(32, 44)
|
||||
`RAM_BE(4096, 88)
|
||||
`RAM_BE(2048, 88)
|
||||
`RAM_BE(1024, 88)
|
||||
`RAM_BE(512, 88)
|
||||
`RAM_BE(256, 88)
|
||||
`RAM_BE(128, 88)
|
||||
`RAM_BE(64, 88)
|
||||
`RAM_BE(32, 88)
|
||||
`RAM(64, 39)
|
||||
|
||||
|
||||
`undef RAM
|
||||
`undef RAM_BE
|
||||
`undef LOCAL_RAM_TEST_IO
|
||||
|
||||
|
||||
|
|
@ -1,178 +0,0 @@
|
|||
#(parameter AWIDTH = 7,
|
||||
TAG = 1'h1,
|
||||
BHT_ADDR_HI = 4'h9,
|
||||
BHT_ADDR_LO = 2'h2,
|
||||
BHT_ARRAY_DEPTH = 11'h100,
|
||||
BHT_GHR_HASH_1 = 1'h0,
|
||||
BHT_GHR_SIZE = 4'h8,
|
||||
BHT_SIZE = 12'h200,
|
||||
BTB_ADDR_HI = 5'h09,
|
||||
BTB_ADDR_LO = 2'h2,
|
||||
BTB_ARRAY_DEPTH = 9'h100,
|
||||
BTB_BTAG_FOLD = 1'h0,
|
||||
BTB_BTAG_SIZE = 4'h5,
|
||||
BTB_FOLD2_INDEX_HASH = 1'h0,
|
||||
BTB_INDEX1_HI = 5'h09,
|
||||
BTB_INDEX1_LO = 5'h02,
|
||||
BTB_INDEX2_HI = 5'h11,
|
||||
BTB_INDEX2_LO = 5'h0A,
|
||||
BTB_INDEX3_HI = 5'h19,
|
||||
BTB_INDEX3_LO = 5'h12,
|
||||
BTB_SIZE = 10'h200,
|
||||
BUILD_AHB_LITE = 1'h0,
|
||||
BUILD_AXI4 = 1'h1,
|
||||
BUILD_AXI_NATIVE = 1'h1,
|
||||
BUS_PRTY_DEFAULT = 2'h3,
|
||||
DATA_ACCESS_ADDR0 = 32'h00000000,
|
||||
DATA_ACCESS_ADDR1 = 32'h00000000,
|
||||
DATA_ACCESS_ADDR2 = 32'h00000000,
|
||||
DATA_ACCESS_ADDR3 = 32'h00000000,
|
||||
DATA_ACCESS_ADDR4 = 32'h00000000,
|
||||
DATA_ACCESS_ADDR5 = 32'h00000000,
|
||||
DATA_ACCESS_ADDR6 = 32'h00000000,
|
||||
DATA_ACCESS_ADDR7 = 32'h00000000,
|
||||
DATA_ACCESS_ENABLE0 = 1'h0,
|
||||
DATA_ACCESS_ENABLE1 = 1'h0,
|
||||
DATA_ACCESS_ENABLE2 = 1'h0,
|
||||
DATA_ACCESS_ENABLE3 = 1'h0,
|
||||
DATA_ACCESS_ENABLE4 = 1'h0,
|
||||
DATA_ACCESS_ENABLE5 = 1'h0,
|
||||
DATA_ACCESS_ENABLE6 = 1'h0,
|
||||
DATA_ACCESS_ENABLE7 = 1'h0,
|
||||
DATA_ACCESS_MASK0 = 32'h0FFFFFFF,
|
||||
DATA_ACCESS_MASK1 = 32'h0FFFFFFF,
|
||||
DATA_ACCESS_MASK2 = 32'h0FFFFFFF,
|
||||
DATA_ACCESS_MASK3 = 32'h0FFFFFFF,
|
||||
DATA_ACCESS_MASK4 = 32'h0FFFFFFF,
|
||||
DATA_ACCESS_MASK5 = 32'h0FFFFFFF,
|
||||
DATA_ACCESS_MASK6 = 32'h0FFFFFFF,
|
||||
DATA_ACCESS_MASK7 = 32'h0FFFFFFF,
|
||||
DCCM_BANK_BITS = 3'h2,
|
||||
DCCM_BITS = 5'h10,
|
||||
DCCM_BYTE_WIDTH = 3'h4,
|
||||
DCCM_DATA_WIDTH = 6'h20,
|
||||
DCCM_ECC_WIDTH = 3'h7,
|
||||
DCCM_ENABLE = 1'h1,
|
||||
DCCM_FDATA_WIDTH = 6'h27,
|
||||
//DCCM_INDEX_BITS = 4'hC,
|
||||
DCCM_NUM_BANKS = 5'h04,
|
||||
DCCM_REGION = 4'hF,
|
||||
DCCM_SADR = 32'hF0040000,
|
||||
DCCM_SIZE = 10'h040,
|
||||
DCCM_WIDTH_BITS = 2'h2,
|
||||
DMA_BUF_DEPTH = 3'h5,
|
||||
DMA_BUS_ID = 1'h1,
|
||||
DMA_BUS_PRTY = 2'h2,
|
||||
DMA_BUS_TAG = 4'h1,
|
||||
FAST_INTERRUPT_REDIRECT = 1'h1,
|
||||
ICACHE_2BANKS = 1'h1,
|
||||
ICACHE_BANK_BITS = 3'h1,
|
||||
ICACHE_BANK_HI = 3'h3,
|
||||
ICACHE_BANK_LO = 2'h3,
|
||||
ICACHE_BANK_WIDTH = 4'h8,
|
||||
ICACHE_BANKS_WAY = 3'h2,
|
||||
ICACHE_BEAT_ADDR_HI = 4'h5,
|
||||
ICACHE_BEAT_BITS = 4'h3,
|
||||
ICACHE_DATA_DEPTH = 14'h0200,
|
||||
ICACHE_DATA_INDEX_LO = 3'h4,
|
||||
ICACHE_DATA_WIDTH = 7'h40,
|
||||
ICACHE_ECC = 1'h1,
|
||||
ICACHE_ENABLE = 1'h1,
|
||||
ICACHE_FDATA_WIDTH = 7'h47,
|
||||
ICACHE_INDEX_HI = 5'h0C,
|
||||
ICACHE_LN_SZ = 7'h40,
|
||||
ICACHE_NUM_BEATS = 4'h8,
|
||||
ICACHE_NUM_WAYS = 3'h2,
|
||||
ICACHE_ONLY = 1'h0,
|
||||
ICACHE_SCND_LAST = 4'h6,
|
||||
ICACHE_SIZE = 9'h010,
|
||||
ICACHE_STATUS_BITS = 3'h1,
|
||||
ICACHE_TAG_DEPTH = 13'h0080,
|
||||
ICACHE_TAG_INDEX_LO = 3'h6,
|
||||
ICACHE_TAG_LO = 5'h0D,
|
||||
ICACHE_WAYPACK = 1'h0,
|
||||
ICCM_BANK_BITS = 3'h2,
|
||||
ICCM_BANK_HI = 5'h03,
|
||||
ICCM_BANK_INDEX_LO = 5'h04,
|
||||
ICCM_BITS = 5'h10,
|
||||
ICCM_ENABLE = 1'h1,
|
||||
ICCM_ICACHE = 1'h1,
|
||||
ICCM_INDEX_BITS = 4'hC,
|
||||
ICCM_NUM_BANKS = 5'h04,
|
||||
ICCM_ONLY = 1'h0,
|
||||
ICCM_REGION = 4'hE,
|
||||
ICCM_SADR = 32'hEE000000,
|
||||
ICCM_SIZE = 10'h040,
|
||||
IFU_BUS_ID = 1'h1,
|
||||
IFU_BUS_PRTY = 2'h2,
|
||||
IFU_BUS_TAG = 4'h3,
|
||||
INST_ACCESS_ADDR0 = 32'h00000000,
|
||||
INST_ACCESS_ADDR1 = 32'h00000000,
|
||||
INST_ACCESS_ADDR2 = 32'h00000000,
|
||||
INST_ACCESS_ADDR3 = 32'h00000000,
|
||||
INST_ACCESS_ADDR4 = 32'h00000000,
|
||||
INST_ACCESS_ADDR5 = 32'h00000000,
|
||||
INST_ACCESS_ADDR6 = 32'h00000000,
|
||||
INST_ACCESS_ADDR7 = 32'h00000000,
|
||||
INST_ACCESS_ENABLE0 = 1'h0,
|
||||
INST_ACCESS_ENABLE1 = 1'h0,
|
||||
INST_ACCESS_ENABLE2 = 1'h0,
|
||||
INST_ACCESS_ENABLE3 = 1'h0,
|
||||
INST_ACCESS_ENABLE4 = 1'h0,
|
||||
INST_ACCESS_ENABLE5 = 1'h0,
|
||||
INST_ACCESS_ENABLE6 = 1'h0,
|
||||
INST_ACCESS_ENABLE7 = 1'h0,
|
||||
INST_ACCESS_MASK0 = 32'h0FFFFFFF,
|
||||
INST_ACCESS_MASK1 = 32'h0FFFFFFF,
|
||||
INST_ACCESS_MASK2 = 32'h0FFFFFFF,
|
||||
INST_ACCESS_MASK3 = 32'h0FFFFFFF,
|
||||
INST_ACCESS_MASK4 = 32'h0FFFFFFF,
|
||||
INST_ACCESS_MASK5 = 32'h0FFFFFFF,
|
||||
INST_ACCESS_MASK6 = 32'h0FFFFFFF,
|
||||
INST_ACCESS_MASK7 = 32'h0FFFFFFF,
|
||||
LOAD_TO_USE_PLUS1 = 1'h0,
|
||||
LSU2DMA = 1'h0,
|
||||
LSU_BUS_ID = 1'h1,
|
||||
LSU_BUS_PRTY = 2'h2,
|
||||
LSU_BUS_TAG = 4'h3,
|
||||
LSU_NUM_NBLOAD = 5'h04,
|
||||
LSU_NUM_NBLOAD_WIDTH = 3'h2,
|
||||
LSU_SB_BITS = 5'h10,
|
||||
LSU_STBUF_DEPTH = 4'h4,
|
||||
NO_ICCM_NO_ICACHE = 1'h0,
|
||||
PIC_2CYCLE = 1'h0,
|
||||
PIC_BASE_ADDR = 32'hF00C0000,
|
||||
PIC_BITS = 5'h0F,
|
||||
PIC_INT_WORDS = 4'h1,
|
||||
PIC_REGION = 4'hF,
|
||||
PIC_SIZE = 9'h020,
|
||||
PIC_TOTAL_INT = 8'h1F,
|
||||
PIC_TOTAL_INT_PLUS1 = 9'h020,
|
||||
RET_STACK_SIZE = 4'h8,
|
||||
SB_BUS_ID = 1'h1,
|
||||
SB_BUS_PRTY = 2'h2,
|
||||
SB_BUS_TAG = 4'h1,
|
||||
TIMER_LEGAL_EN = 1'h1,
|
||||
RV_FPGA_OPTIMIZE = 5'h01,
|
||||
DIV_NEW = 5'h01,
|
||||
DIV_BIT = 7'h04,
|
||||
BTB_ENABLE = 5'h01,
|
||||
BTB_TOFFSET_SIZE = 9'h00C,
|
||||
BTB_FULLYA = 5'h00,
|
||||
BITMANIP_ZBA = 5'h00 ,
|
||||
BITMANIP_ZBB = 5'h01 ,
|
||||
BITMANIP_ZBC = 5'h00 ,
|
||||
BITMANIP_ZBE = 5'h00 ,
|
||||
BITMANIP_ZBF = 5'h00 ,
|
||||
BITMANIP_ZBP = 5'h00 ,
|
||||
BITMANIP_ZBR = 5'h00 ,
|
||||
BITMANIP_ZBS = 5'h01 ,
|
||||
ICACHE_BYPASS_ENABLE = 5'h01,
|
||||
ICACHE_NUM_BYPASS = 8'h02,
|
||||
ICACHE_NUM_BYPASS_WIDTH = 8'h02,
|
||||
ICACHE_TAG_BYPASS_ENABLE = 5'h01,
|
||||
ICACHE_TAG_NUM_BYPASS = 8'h02,
|
||||
ICACHE_TAG_NUM_BYPASS_WIDTH = 8'h02
|
||||
|
||||
|
||||
)
|
||||
|
|
@ -1,395 +0,0 @@
|
|||
typedef struct packed {
|
||||
logic trace_rv_i_valid_ip;
|
||||
logic [31:0] trace_rv_i_insn_ip;
|
||||
logic [31:0] trace_rv_i_address_ip;
|
||||
logic trace_rv_i_exception_ip;
|
||||
logic [4:0] trace_rv_i_ecause_ip;
|
||||
logic trace_rv_i_interrupt_ip;
|
||||
logic [31:0] trace_rv_i_tval_ip;
|
||||
} trace_pkt_t;
|
||||
|
||||
typedef enum logic [3:0] {
|
||||
NULL = 4'b0000,
|
||||
MUL = 4'b0001,
|
||||
LOAD = 4'b0010,
|
||||
STORE = 4'b0011,
|
||||
ALU = 4'b0100,
|
||||
CSRREAD = 4'b0101,
|
||||
CSRWRITE = 4'b0110,
|
||||
CSRRW = 4'b0111,
|
||||
EBREAK = 4'b1000,
|
||||
ECALL = 4'b1001,
|
||||
FENCE = 4'b1010,
|
||||
FENCEI = 4'b1011,
|
||||
MRET = 4'b1100,
|
||||
CONDBR = 4'b1101,
|
||||
JAL = 4'b1110,
|
||||
BITMANIPU = 4'b1111
|
||||
} inst_pkt_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic valid;
|
||||
logic wb;
|
||||
logic [2:0] tag;
|
||||
logic [4:0] rd;
|
||||
} load_cam_pkt_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic pc0_call;
|
||||
logic pc0_ret;
|
||||
logic pc0_pc4;
|
||||
} rets_pkt_t;
|
||||
typedef struct packed {
|
||||
logic valid;
|
||||
logic [11:0] toffset;
|
||||
logic [1:0] hist;
|
||||
logic br_error;
|
||||
logic br_start_error;
|
||||
logic bank;
|
||||
logic [31:1] prett; // predicted ret target
|
||||
logic way;
|
||||
logic ret;
|
||||
} br_pkt_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic valid;
|
||||
logic [1:0] hist;
|
||||
logic br_error;
|
||||
logic br_start_error;
|
||||
logic way;
|
||||
logic middle;
|
||||
} br_tlu_pkt_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic misp;
|
||||
logic ataken;
|
||||
logic boffset;
|
||||
logic pc4;
|
||||
logic [1:0] hist;
|
||||
logic [11:0] toffset;
|
||||
logic valid;
|
||||
logic br_error;
|
||||
logic br_start_error;
|
||||
logic pcall;
|
||||
logic pja;
|
||||
logic way;
|
||||
logic pret;
|
||||
// for power use the pret bit to clock the prett field
|
||||
logic [31:1] prett;
|
||||
} predict_pkt_t;
|
||||
|
||||
typedef struct packed {
|
||||
// unlikely to change
|
||||
logic icaf;
|
||||
logic icaf_second;
|
||||
logic [1:0] icaf_type;
|
||||
logic fence_i;
|
||||
logic [3:0] i0trigger;
|
||||
logic pmu_i0_br_unpred; // pmu
|
||||
logic pmu_divide;
|
||||
// likely to change
|
||||
logic legal;
|
||||
logic pmu_lsu_misaligned;
|
||||
inst_pkt_t pmu_i0_itype; // pmu - instruction type
|
||||
} trap_pkt_t;
|
||||
|
||||
typedef struct packed {
|
||||
// unlikely to change
|
||||
logic i0div;
|
||||
logic csrwen;
|
||||
logic csrwonly;
|
||||
logic [11:0] csrwaddr;
|
||||
// likely to change
|
||||
logic [4:0] i0rd;
|
||||
logic i0load;
|
||||
logic i0store;
|
||||
logic i0v;
|
||||
logic i0valid;
|
||||
} dest_pkt_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic mul;
|
||||
logic load;
|
||||
logic alu;
|
||||
} class_pkt_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic [4:0] rs1;
|
||||
logic [4:0] rs2;
|
||||
logic [4:0] rd;
|
||||
} reg_pkt_t;
|
||||
|
||||
|
||||
typedef struct packed {
|
||||
logic clz;
|
||||
logic ctz;
|
||||
logic pcnt;
|
||||
logic sext_b;
|
||||
logic sext_h;
|
||||
logic slo;
|
||||
logic sro;
|
||||
logic min;
|
||||
logic max;
|
||||
logic pack;
|
||||
logic packu;
|
||||
logic packh;
|
||||
logic rol;
|
||||
logic ror;
|
||||
logic grev;
|
||||
logic gorc;
|
||||
logic zbb;
|
||||
logic sbset;
|
||||
logic sbclr;
|
||||
logic sbinv;
|
||||
logic sbext;
|
||||
logic sh1add;
|
||||
logic sh2add;
|
||||
logic sh3add;
|
||||
logic zba;
|
||||
logic land;
|
||||
logic lor;
|
||||
logic lxor;
|
||||
logic sll;
|
||||
logic srl;
|
||||
logic sra;
|
||||
logic beq;
|
||||
logic bne;
|
||||
logic blt;
|
||||
logic bge;
|
||||
logic add;
|
||||
logic sub;
|
||||
logic slt;
|
||||
logic unsign;
|
||||
logic jal;
|
||||
logic predict_t;
|
||||
logic predict_nt;
|
||||
logic csr_write;
|
||||
logic csr_imm;
|
||||
} alu_pkt_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic fast_int;
|
||||
/* verilator lint_off SYMRSVDWORD */
|
||||
logic stack;
|
||||
/* verilator lint_on SYMRSVDWORD */
|
||||
logic by;
|
||||
logic half;
|
||||
logic word;
|
||||
logic dword; // for dma
|
||||
logic load;
|
||||
logic store;
|
||||
logic unsign;
|
||||
logic dma; // dma pkt
|
||||
logic store_data_bypass_d;
|
||||
logic load_ldst_bypass_d;
|
||||
logic store_data_bypass_m;
|
||||
logic valid;
|
||||
} lsu_pkt_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic inst_type; //0: Load, 1: Store
|
||||
//logic dma_valid;
|
||||
logic exc_type; //0: MisAligned, 1: Access Fault
|
||||
logic [3:0] mscause;
|
||||
logic [31:0] addr;
|
||||
logic single_ecc_error;
|
||||
logic exc_valid;
|
||||
} lsu_error_pkt_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic clz;
|
||||
logic ctz;
|
||||
logic pcnt;
|
||||
logic sext_b;
|
||||
logic sext_h;
|
||||
logic slo;
|
||||
logic sro;
|
||||
logic min;
|
||||
logic max;
|
||||
logic pack;
|
||||
logic packu;
|
||||
logic packh;
|
||||
logic rol;
|
||||
logic ror;
|
||||
logic grev;
|
||||
logic gorc;
|
||||
logic zbb;
|
||||
logic sbset;
|
||||
logic sbclr;
|
||||
logic sbinv;
|
||||
logic sbext;
|
||||
logic zbs;
|
||||
logic bext;
|
||||
logic bdep;
|
||||
logic zbe;
|
||||
logic clmul;
|
||||
logic clmulh;
|
||||
logic clmulr;
|
||||
logic zbc;
|
||||
logic shfl;
|
||||
logic unshfl;
|
||||
logic zbp;
|
||||
logic crc32_b;
|
||||
logic crc32_h;
|
||||
logic crc32_w;
|
||||
logic crc32c_b;
|
||||
logic crc32c_h;
|
||||
logic crc32c_w;
|
||||
logic zbr;
|
||||
logic bfp;
|
||||
logic zbf;
|
||||
logic sh1add;
|
||||
logic sh2add;
|
||||
logic sh3add;
|
||||
logic zba;
|
||||
logic alu;
|
||||
logic rs1;
|
||||
logic rs2;
|
||||
logic imm12;
|
||||
logic rd;
|
||||
logic shimm5;
|
||||
logic imm20;
|
||||
logic pc;
|
||||
logic load;
|
||||
logic store;
|
||||
logic lsu;
|
||||
logic add;
|
||||
logic sub;
|
||||
logic land;
|
||||
logic lor;
|
||||
logic lxor;
|
||||
logic sll;
|
||||
logic sra;
|
||||
logic srl;
|
||||
logic slt;
|
||||
logic unsign;
|
||||
logic condbr;
|
||||
logic beq;
|
||||
logic bne;
|
||||
logic bge;
|
||||
logic blt;
|
||||
logic jal;
|
||||
logic by;
|
||||
logic half;
|
||||
logic word;
|
||||
logic csr_read;
|
||||
logic csr_clr;
|
||||
logic csr_set;
|
||||
logic csr_write;
|
||||
logic csr_imm;
|
||||
logic presync;
|
||||
logic postsync;
|
||||
logic ebreak;
|
||||
logic ecall;
|
||||
logic mret;
|
||||
logic mul;
|
||||
logic rs1_sign;
|
||||
logic rs2_sign;
|
||||
logic low;
|
||||
logic div;
|
||||
logic rem;
|
||||
logic fence;
|
||||
logic fence_i;
|
||||
logic pm_alu;
|
||||
logic legal;
|
||||
} dec_pkt_t;
|
||||
|
||||
|
||||
typedef struct packed {
|
||||
logic valid;
|
||||
logic rs1_sign;
|
||||
logic rs2_sign;
|
||||
logic low;
|
||||
logic bext;
|
||||
logic bdep;
|
||||
logic clmul;
|
||||
logic clmulh;
|
||||
logic clmulr;
|
||||
logic grev;
|
||||
logic gorc;
|
||||
logic shfl;
|
||||
logic unshfl;
|
||||
logic crc32_b;
|
||||
logic crc32_h;
|
||||
logic crc32_w;
|
||||
logic crc32c_b;
|
||||
logic crc32c_h;
|
||||
logic crc32c_w;
|
||||
logic bfp;
|
||||
} mul_pkt_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic valid;
|
||||
logic unsign;
|
||||
logic rem;
|
||||
} div_pkt_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic TEST1;
|
||||
logic RME;
|
||||
logic [3:0] RM;
|
||||
logic LS;
|
||||
logic DS;
|
||||
logic SD;
|
||||
logic TEST_RNM;
|
||||
logic BC1;
|
||||
logic BC2;
|
||||
} iccm_ext_in_pkt_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic TEST1;
|
||||
logic RME;
|
||||
logic [3:0] RM;
|
||||
logic LS;
|
||||
logic DS;
|
||||
logic SD;
|
||||
logic TEST_RNM;
|
||||
logic BC1;
|
||||
logic BC2;
|
||||
} dccm_ext_in_pkt_t;
|
||||
|
||||
|
||||
typedef struct packed {
|
||||
logic TEST1;
|
||||
logic RME;
|
||||
logic [3:0] RM;
|
||||
logic LS;
|
||||
logic DS;
|
||||
logic SD;
|
||||
logic TEST_RNM;
|
||||
logic BC1;
|
||||
logic BC2;
|
||||
} ic_data_ext_in_pkt_t;
|
||||
|
||||
|
||||
typedef struct packed {
|
||||
logic TEST1;
|
||||
logic RME;
|
||||
logic [3:0] RM;
|
||||
logic LS;
|
||||
logic DS;
|
||||
logic SD;
|
||||
logic TEST_RNM;
|
||||
logic BC1;
|
||||
logic BC2;
|
||||
} ic_tag_ext_in_pkt_t;
|
||||
|
||||
|
||||
|
||||
typedef struct packed {
|
||||
logic select;
|
||||
logic match;
|
||||
logic store;
|
||||
logic load;
|
||||
logic execute;
|
||||
logic m;
|
||||
logic [31:0] tdata2;
|
||||
} trigger_pkt_t;
|
||||
|
||||
|
||||
typedef struct packed {
|
||||
logic [70:0] icache_wrdata; // {dicad1[1:0], dicad0h[31:0], dicad0[31:0]}
|
||||
logic [16:0] icache_dicawics; // Arraysel:24, Waysel:21:20, Index:16:3
|
||||
logic icache_rd_valid;
|
||||
logic icache_wr_valid;
|
||||
} cache_debug_pkt_t;
|
||||
|
|
@ -1,222 +0,0 @@
|
|||
// SPDX-License-Identifier: Apache-2.0
|
||||
// Copyright 2019 Western Digital Corporation or it's affiliates.
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License
|
||||
|
||||
module rvjtag_tap
|
||||
`include "parameter.sv"(
|
||||
input trst,
|
||||
input tck,
|
||||
input tms,
|
||||
input tdi,
|
||||
output reg tdo,
|
||||
output tdoEnable,
|
||||
|
||||
output [31:0] wr_data,
|
||||
output [AWIDTH-1:0] wr_addr,
|
||||
output wr_en,
|
||||
output rd_en,
|
||||
|
||||
input [31:0] rd_data,
|
||||
input [1:0] rd_status,
|
||||
|
||||
output reg dmi_reset,
|
||||
output reg dmi_hard_reset,
|
||||
|
||||
input [2:0] idle,
|
||||
input [1:0] dmi_stat,
|
||||
/*
|
||||
-- revisionCode : 4'h0;
|
||||
-- manufacturersIdCode : 11'h45;
|
||||
-- deviceIdCode : 16'h0001;
|
||||
-- order MSB .. LSB -> [4 bit version or revision] [16 bit part number] [11 bit manufacturer id] [value of 1'b1 in LSB]
|
||||
*/
|
||||
input [31:1] jtag_id,
|
||||
input [3:0] version
|
||||
);
|
||||
|
||||
localparam USER_DR_LENGTH = AWIDTH + 34;
|
||||
|
||||
|
||||
reg [USER_DR_LENGTH-1:0] sr, nsr, dr;
|
||||
|
||||
///////////////////////////////////////////////////////
|
||||
// Tap controller
|
||||
///////////////////////////////////////////////////////
|
||||
logic[3:0] state, nstate;
|
||||
logic [4:0] ir;
|
||||
wire jtag_reset;
|
||||
wire shift_dr;
|
||||
wire pause_dr;
|
||||
wire update_dr;
|
||||
wire capture_dr;
|
||||
wire shift_ir;
|
||||
wire pause_ir ;
|
||||
wire update_ir ;
|
||||
wire capture_ir;
|
||||
wire[1:0] dr_en;
|
||||
wire devid_sel;
|
||||
wire [5:0] abits;
|
||||
|
||||
assign abits = AWIDTH[5:0];
|
||||
|
||||
|
||||
localparam TEST_LOGIC_RESET_STATE = 0;
|
||||
localparam RUN_TEST_IDLE_STATE = 1;
|
||||
localparam SELECT_DR_SCAN_STATE = 2;
|
||||
localparam CAPTURE_DR_STATE = 3;
|
||||
localparam SHIFT_DR_STATE = 4;
|
||||
localparam EXIT1_DR_STATE = 5;
|
||||
localparam PAUSE_DR_STATE = 6;
|
||||
localparam EXIT2_DR_STATE = 7;
|
||||
localparam UPDATE_DR_STATE = 8;
|
||||
localparam SELECT_IR_SCAN_STATE = 9;
|
||||
localparam CAPTURE_IR_STATE = 10;
|
||||
localparam SHIFT_IR_STATE = 11;
|
||||
localparam EXIT1_IR_STATE = 12;
|
||||
localparam PAUSE_IR_STATE = 13;
|
||||
localparam EXIT2_IR_STATE = 14;
|
||||
localparam UPDATE_IR_STATE = 15;
|
||||
|
||||
always_comb begin
|
||||
nstate = state;
|
||||
case(state)
|
||||
TEST_LOGIC_RESET_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : RUN_TEST_IDLE_STATE;
|
||||
RUN_TEST_IDLE_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;
|
||||
SELECT_DR_SCAN_STATE: nstate = tms ? SELECT_IR_SCAN_STATE : CAPTURE_DR_STATE;
|
||||
CAPTURE_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE;
|
||||
SHIFT_DR_STATE: nstate = tms ? EXIT1_DR_STATE : SHIFT_DR_STATE;
|
||||
EXIT1_DR_STATE: nstate = tms ? UPDATE_DR_STATE : PAUSE_DR_STATE;
|
||||
PAUSE_DR_STATE: nstate = tms ? EXIT2_DR_STATE : PAUSE_DR_STATE;
|
||||
EXIT2_DR_STATE: nstate = tms ? UPDATE_DR_STATE : SHIFT_DR_STATE;
|
||||
UPDATE_DR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;
|
||||
SELECT_IR_SCAN_STATE: nstate = tms ? TEST_LOGIC_RESET_STATE : CAPTURE_IR_STATE;
|
||||
CAPTURE_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE;
|
||||
SHIFT_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE;
|
||||
EXIT1_IR_STATE: nstate = tms ? UPDATE_IR_STATE : PAUSE_IR_STATE;
|
||||
PAUSE_IR_STATE: nstate = tms ? EXIT2_IR_STATE : PAUSE_IR_STATE;
|
||||
EXIT2_IR_STATE: nstate = tms ? UPDATE_IR_STATE : SHIFT_IR_STATE;
|
||||
UPDATE_IR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE;
|
||||
default: nstate = TEST_LOGIC_RESET_STATE;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @ (posedge tck or negedge trst) begin
|
||||
if(!trst) state <= TEST_LOGIC_RESET_STATE;
|
||||
else state <= nstate;
|
||||
end
|
||||
|
||||
assign jtag_reset = state == TEST_LOGIC_RESET_STATE;
|
||||
assign shift_dr = state == SHIFT_DR_STATE;
|
||||
assign pause_dr = state == PAUSE_DR_STATE;
|
||||
assign update_dr = state == UPDATE_DR_STATE;
|
||||
assign capture_dr = state == CAPTURE_DR_STATE;
|
||||
assign shift_ir = state == SHIFT_IR_STATE;
|
||||
assign pause_ir = state == PAUSE_IR_STATE;
|
||||
assign update_ir = state == UPDATE_IR_STATE;
|
||||
assign capture_ir = state == CAPTURE_IR_STATE;
|
||||
|
||||
assign tdoEnable = shift_dr | shift_ir;
|
||||
|
||||
///////////////////////////////////////////////////////
|
||||
// IR register
|
||||
///////////////////////////////////////////////////////
|
||||
|
||||
always @ (negedge tck or negedge trst) begin
|
||||
if (!trst) ir <= 5'b1;
|
||||
else begin
|
||||
if (jtag_reset) ir <= 5'b1;
|
||||
else if (update_ir) ir <= (sr[4:0] == '0) ? 5'h1f :sr[4:0];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
assign devid_sel = ir == 5'b00001;
|
||||
assign dr_en[0] = ir == 5'b10000;
|
||||
assign dr_en[1] = ir == 5'b10001;
|
||||
|
||||
///////////////////////////////////////////////////////
|
||||
// Shift register
|
||||
///////////////////////////////////////////////////////
|
||||
always @ (posedge tck or negedge trst) begin
|
||||
if(!trst)begin
|
||||
sr <= '0;
|
||||
end
|
||||
else begin
|
||||
sr <= nsr;
|
||||
end
|
||||
end
|
||||
|
||||
// SR next value
|
||||
always_comb begin
|
||||
nsr = sr;
|
||||
case(1)
|
||||
shift_dr: begin
|
||||
case(1)
|
||||
dr_en[1]: nsr = {tdi, sr[USER_DR_LENGTH-1:1]};
|
||||
|
||||
dr_en[0],
|
||||
devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}},tdi, sr[31:1]};
|
||||
default: nsr = {{USER_DR_LENGTH-1{1'b0}},tdi}; // bypass
|
||||
endcase
|
||||
end
|
||||
capture_dr: begin
|
||||
nsr[0] = 1'b0;
|
||||
case(1)
|
||||
dr_en[0]: nsr = {{USER_DR_LENGTH-15{1'b0}}, idle, dmi_stat, abits, version};
|
||||
dr_en[1]: nsr = {{AWIDTH{1'b0}}, rd_data, rd_status};
|
||||
devid_sel: nsr = {{USER_DR_LENGTH-32{1'b0}}, jtag_id, 1'b1};
|
||||
endcase
|
||||
end
|
||||
shift_ir: nsr = {{USER_DR_LENGTH-5{1'b0}},tdi, sr[4:1]};
|
||||
capture_ir: nsr = {{USER_DR_LENGTH-1{1'b0}},1'b1};
|
||||
endcase
|
||||
end
|
||||
|
||||
// TDO retiming
|
||||
always @ (negedge tck ) tdo <= sr[0];
|
||||
|
||||
// DMI CS register
|
||||
always @ (posedge tck or negedge trst) begin
|
||||
if(!trst) begin
|
||||
dmi_hard_reset <= 1'b0;
|
||||
dmi_reset <= 1'b0;
|
||||
end
|
||||
else if (update_dr & dr_en[0]) begin
|
||||
dmi_hard_reset <= sr[17];
|
||||
dmi_reset <= sr[16];
|
||||
end
|
||||
else begin
|
||||
dmi_hard_reset <= 1'b0;
|
||||
dmi_reset <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// DR register
|
||||
always @ (posedge tck or negedge trst) begin
|
||||
if(!trst)
|
||||
dr <= '0;
|
||||
else begin
|
||||
if (update_dr & dr_en[1])
|
||||
dr <= sr;
|
||||
else
|
||||
dr <= {dr[USER_DR_LENGTH-1:2],2'b0};
|
||||
end
|
||||
end
|
||||
|
||||
assign {wr_addr, wr_data, wr_en, rd_en} = dr;
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,71 +0,0 @@
|
|||
# Logical Equivalence Check of Quasar RISC-V Core 1.0 from Lampro Mellon
|
||||
|
||||
This repository contains the EL2 SweRV Core, Quasar Core design in RTL, and the setup files. To run logical equivalency check on the two designs follow these instructions.
|
||||
|
||||
## Directory Structure
|
||||
|
||||
|
||||
├── verif
|
||||
├── LEC
|
||||
│ ├── LEC_RTL
|
||||
│ ├── generated_rtl # Quasar wrapper Black Boxes
|
||||
│ ├── Golden_RTL
|
||||
│ ├── configs
|
||||
│ ├── design
|
||||
│ ├── dbg # Debugger
|
||||
│ ├── dec # Decode, Registers and Exceptions
|
||||
│ ├── dmi # DMI block
|
||||
│ ├── exu # EXU (ALU/MUL/DIV)
|
||||
│ ├── ifu # Fetch & Branch Prediction
|
||||
│ ├── include
|
||||
│ ├── lib # Bridges and Library
|
||||
│ └── lsu # Load/Store
|
||||
│ ├── docs
|
||||
│ └── tools
|
||||
│ ├── snapshots
|
||||
│ └── defaults
|
||||
│ └── formality_work
|
||||
│ └── formality_log # formality log/dump files
|
||||
└── sim # Simulation log/dump files
|
||||
|
||||
## Dependencies
|
||||
|
||||
- Synopsys Formality tool must be installed on the system to run logical equivalence check.
|
||||
|
||||
## Quickstart guide
|
||||
|
||||
1. Clone the repository
|
||||
2. Setup RV_ROOT to point to the path in your local filesystem
|
||||
3. Quasar core is LEC verified on the default configuration
|
||||
4. Run "make -f $RV_ROOT/tools/Makefile lec"
|
||||
|
||||
## Getting design files ready for the tool
|
||||
Following changes have been made in the design files to get them ready for tool, if you wants to clone the golden design from chipsalliance repository do following changes in the golden design.
|
||||
The directory $RV_ROOT/verif/LEC/LEC_RTL is not available initially when the Quasar RISC-V core is clonned from repository. It will be generated when the "make -f $RV_ROOT/tools/Makefile lec" is executed. Once this command is executed, it will generated the RTL of Quasar RISC-V core and place it in the $RV_ROOT/generated_rtl.
|
||||
### Golden Design
|
||||
Including el2_param.vh in the golden design (El2 SweRV core) yields syntax error as formality tool does not accept parameter in this format, for further detail please refer to FMR_VLOG-481 formality error message. To fix this issue follow following steps
|
||||
|
||||
1. Remove all pt. from all design files
|
||||
2. Remove #(.pt(pt)) in module instantiation from all design files
|
||||
3. Comment out localparam DCCM_WIDTH_BITS in $RV_ROOT/verif/LEC/LEC_RTL/Golden_RTL/design/lsu/el2_lsu_dccm_ctl.sv
|
||||
4. Put all paramters from el2_param.vh file to new *.sv file, parameter should be in $RV_ROOT/verif/LEC/LEC_RTL/Golden_RTL/parameter.sv format
|
||||
5. Replace el2_param.vh with the parameter.sv file.
|
||||
|
||||
Importing el2_pkg in all design files yields FMR_VLOG-224 formality error message which explains that a reference to the given package should be analyzed before its declaration has been analyzed. In order to ensure this, the packet file which has all the packets should be included in the quasar top.
|
||||
|
||||
### Implementation design
|
||||
The Quasar RISC-V core is all set to be checked and loaded directly into the formality without any changes.
|
||||
|
||||
## Synopsys Formality Constraints/Setup
|
||||
|
||||
### Constraints
|
||||
There are some registers which are potentionally constants when a test pattern is applied to these signals by the tool it causes design failures. To solve this problem the potionally constant registers were identified, and a constant value is applied to the register in setup mode. The constant setup file is present in $RV_ROOT/verif/LEC/setup_files/constant.fms
|
||||
### User Matched Points
|
||||
The tool matches the compare points on either name based or by signal analysis, but in some cases the tools fails to identify the equivalent points. All these unmatched points were matched manually through "set_user_match" command. The unmatched point can be a flop, port, latch or a black box pins, their details are present in the following directory respectively.
|
||||
|
||||
1. $RV_ROOT/verif/LEC/setup_files/DFF.fms
|
||||
2. $RV_ROOT/verif/LEC/setup_files/PORT.fms
|
||||
3. $RV_ROOT/verif/LEC/setup_files/LAT.fms
|
||||
4. $RV_ROOT/verif/LEC/setup_files/BBPIN.fms
|
||||
|
||||
**Note**: Quasar Core has been verified on default configuration.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,531 +0,0 @@
|
|||
****************************************************
|
||||
|
||||
Warning: Cell r:/WORK/el2_swerv_wrapper/mem references black-box design /WORK/el2_mem (FM-158)
|
||||
Info: Net r:/WORK/el2_swerv/sb_hsize[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hsize[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hsize[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_htrans[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_htrans[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwrite is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/htrans[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/htrans[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hmastlock is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hmastlock is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hprot[3] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hprot[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hprot[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hprot[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hburst[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hburst[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hburst[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hburst[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hburst[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hburst[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hsize[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hsize[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hsize[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hresp is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hprot[3] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hprot[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hprot[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hprot[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[63] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[62] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[61] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[60] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[59] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[58] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[57] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[56] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[55] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[54] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[53] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[52] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[51] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[50] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[49] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[48] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[47] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[46] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[45] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[44] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[43] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[42] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[41] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[40] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[39] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[38] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[37] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[36] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[35] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[34] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[33] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[32] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[31] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[30] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[29] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[28] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[27] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[26] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[25] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[24] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[23] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[22] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[21] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[20] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[19] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[18] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[17] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[16] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[15] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[14] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[13] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[12] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[11] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[10] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[9] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[8] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[7] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[6] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[5] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[4] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[3] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[31] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[30] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[29] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[28] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[27] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[26] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[25] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[24] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[23] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[22] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[21] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[20] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[19] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[18] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[17] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[16] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[15] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[14] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[13] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[12] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[11] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[10] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[9] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[8] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[7] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[6] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[5] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[4] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[3] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hburst[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hburst[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hburst[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hreadyout is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hwrite is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_htrans[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_htrans[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[31] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[30] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[29] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[28] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[27] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[26] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[25] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[24] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[23] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[22] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[21] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[20] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[19] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[18] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[17] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[16] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[15] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[14] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[13] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[12] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[11] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[10] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[9] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[8] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[7] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[6] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[5] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[4] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[3] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hmastlock is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwrite is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[63] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[62] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[61] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[60] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[59] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[58] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[57] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[56] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[55] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[54] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[53] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[52] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[51] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[50] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[49] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[48] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[47] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[46] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[45] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[44] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[43] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[42] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[41] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[40] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[39] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[38] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[37] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[36] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[35] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[34] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[33] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[32] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[31] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[30] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[29] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[28] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[27] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[26] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[25] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[24] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[23] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[22] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[21] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[20] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[19] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[18] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[17] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[16] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[15] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[14] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[13] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[12] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[11] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[10] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[9] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[8] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[7] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[6] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[5] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[4] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[3] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hsize[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hsize[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hsize[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hprot[3] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hprot[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hprot[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hprot[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[31] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[30] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[29] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[28] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[27] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[26] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[25] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[24] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[23] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[22] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[21] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[20] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[19] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[18] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[17] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[16] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[15] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[14] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[13] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[12] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[11] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[10] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[9] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[8] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[7] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[6] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[5] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[4] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[3] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[63] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[62] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[61] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[60] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[59] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[58] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[57] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[56] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[55] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[54] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[53] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[52] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[51] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[50] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[49] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[48] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[47] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[46] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[45] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[44] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[43] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[42] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[41] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[40] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[39] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[38] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[37] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[36] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[35] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[34] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[33] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[32] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[31] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[30] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[29] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[28] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[27] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[26] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[25] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[24] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[23] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[22] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[21] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[20] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[19] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[18] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[17] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[16] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[15] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[14] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[13] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[12] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[11] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[10] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[9] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[8] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[7] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[6] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[5] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[4] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[3] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[0] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][8] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][7] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][6] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][5] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][4] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][3] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][2] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][1] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][0] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][8] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][7] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][6] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][5] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][4] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][3] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][2] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][1] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][0] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][15] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][14] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][13] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][12] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][11] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][10] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][9] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][8] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][7] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][6] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][5] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][4] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][3] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][2] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][1] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][0] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][15] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][14] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][13] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][12] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][11] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][10] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][9] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][8] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][7] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][6] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][5] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][4] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][3] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][2] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][1] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][0] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[br_error] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[br_start_error] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][31] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][30] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][29] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][28] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][27] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][26] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][25] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][24] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][23] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][22] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][21] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][20] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][19] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][18] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][17] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][16] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][15] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][14] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][13] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][12] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][11] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][10] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][9] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][8] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][7] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][6] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][5] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][4] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][3] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][2] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][1] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[6] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[5] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[4] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[3] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[2] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[1] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[0] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[31] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[30] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[29] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[28] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[27] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[26] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[25] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[24] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[23] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[22] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[21] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[20] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[19] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[18] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[17] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[16] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[15] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[14] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[13] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[12] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[11] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[10] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[9] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[8] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[7] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[6] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[5] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[4] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[3] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[2] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[1] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[0] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[6] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[5] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[4] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[3] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[2] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[1] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[0] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[31] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[30] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[29] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[28] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[27] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[26] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[25] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[24] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[23] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[22] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[21] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[20] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[19] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[18] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[17] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[16] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[15] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[14] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[13] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[12] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[11] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[10] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[9] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[8] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[7] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[6] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[5] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[4] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[3] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[2] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[1] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[0] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[31] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[30] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[29] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[28] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[27] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[26] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[25] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[24] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[23] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[22] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[21] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[20] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[19] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[18] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[17] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[16] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[15] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[14] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[13] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[12] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[11] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[10] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[9] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[8] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[7] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[6] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[5] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[4] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[3] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[2] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[1] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[0] is undriven.
|
||||
Warning: Cell i:/WORK/quasar_wrapper/mem references black-box design /WORK/mem_DCCM_BANK_BITS2_DCCM_BITS16_DCCM_BYTE_WIDTH4_DCCM_ENABLE1_DCCM_FDATA_WIDTH39_DCCM_NUM_BANKS4_DCCM_SIZE64_DCCM_WIDTH_BITS2_ICACHE_BANK_BITS1_ICACHE_BANK_HI3_ICACHE_BANK_LO3_ICACHE_BANKS_WAY2_ICACHE_BEAT_ADDR_HI5_ICACHE_BEAT_BITS3_ICACHE_BYPASS_ENABLE1_ICACHE_DATA_DEPTH512_ICACHE_DATA_INDEX_LO4_ICACHE_ECC1_ICACHE_ENABLE1_ICACHE_INDEX_HI12_ICACHE_LN_SZ64_ICACHE_NUM_BYPASS2_ICACHE_NUM_BYPASS_WIDTH2_ICACHE_NUM_WAYS2_ICACHE_TAG_BYPASS_ENABLE1_ICACHE_TAG_DEPTH128_ICACHE_TAG_INDEX_LO6_ICACHE_TAG_LO13_ICACHE_TAG_NUM_BYPASS2_ICACHE_TAG_NUM_BYPASS_WIDTH2_ICACHE_WAYPACK1_ICCM_BANK_BITS2_ICCM_BANK_HI3_ICCM_BANK_INDEX_LO4_ICCM_BITS16_ICCM_ENABLE1_ICCM_INDEX_BITS12_ICCM_NUM_BANKS4 (FM-158)
|
||||
****************************************************
|
||||
|
||||
|
|
@ -1,531 +0,0 @@
|
|||
****************************************************
|
||||
|
||||
Warning: Cell r:/WORK/el2_swerv_wrapper/mem references black-box design /WORK/el2_mem (FM-158)
|
||||
Info: Net r:/WORK/el2_swerv/sb_hsize[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hsize[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hsize[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_htrans[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_htrans[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwrite is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/htrans[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/htrans[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hmastlock is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hmastlock is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hprot[3] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hprot[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hprot[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hprot[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hburst[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hburst[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hburst[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hburst[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hburst[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hburst[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hsize[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hsize[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hsize[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hresp is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hprot[3] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hprot[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hprot[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hprot[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[63] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[62] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[61] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[60] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[59] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[58] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[57] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[56] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[55] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[54] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[53] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[52] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[51] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[50] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[49] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[48] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[47] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[46] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[45] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[44] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[43] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[42] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[41] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[40] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[39] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[38] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[37] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[36] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[35] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[34] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[33] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[32] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[31] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[30] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[29] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[28] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[27] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[26] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[25] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[24] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[23] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[22] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[21] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[20] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[19] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[18] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[17] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[16] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[15] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[14] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[13] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[12] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[11] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[10] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[9] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[8] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[7] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[6] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[5] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[4] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[3] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwdata[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[31] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[30] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[29] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[28] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[27] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[26] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[25] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[24] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[23] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[22] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[21] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[20] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[19] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[18] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[17] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[16] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[15] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[14] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[13] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[12] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[11] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[10] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[9] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[8] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[7] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[6] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[5] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[4] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[3] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_haddr[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hburst[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hburst[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hburst[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hreadyout is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hwrite is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_htrans[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_htrans[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[31] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[30] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[29] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[28] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[27] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[26] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[25] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[24] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[23] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[22] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[21] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[20] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[19] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[18] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[17] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[16] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[15] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[14] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[13] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[12] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[11] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[10] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[9] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[8] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[7] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[6] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[5] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[4] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[3] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_haddr[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/hmastlock is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/sb_hwrite is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[63] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[62] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[61] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[60] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[59] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[58] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[57] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[56] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[55] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[54] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[53] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[52] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[51] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[50] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[49] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[48] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[47] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[46] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[45] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[44] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[43] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[42] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[41] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[40] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[39] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[38] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[37] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[36] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[35] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[34] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[33] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[32] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[31] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[30] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[29] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[28] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[27] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[26] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[25] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[24] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[23] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[22] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[21] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[20] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[19] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[18] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[17] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[16] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[15] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[14] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[13] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[12] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[11] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[10] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[9] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[8] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[7] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[6] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[5] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[4] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[3] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hwdata[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hsize[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hsize[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hsize[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hprot[3] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hprot[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hprot[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/lsu_hprot[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[31] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[30] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[29] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[28] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[27] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[26] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[25] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[24] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[23] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[22] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[21] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[20] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[19] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[18] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[17] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[16] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[15] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[14] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[13] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[12] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[11] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[10] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[9] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[8] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[7] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[6] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[5] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[4] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[3] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/haddr[0] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[63] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[62] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[61] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[60] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[59] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[58] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[57] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[56] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[55] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[54] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[53] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[52] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[51] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[50] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[49] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[48] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[47] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[46] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[45] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[44] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[43] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[42] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[41] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[40] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[39] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[38] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[37] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[36] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[35] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[34] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[33] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[32] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[31] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[30] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[29] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[28] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[27] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[26] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[25] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[24] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[23] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[22] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[21] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[20] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[19] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[18] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[17] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[16] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[15] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[14] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[13] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[12] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[11] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[10] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[9] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[8] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[7] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[6] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[5] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[4] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[3] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[2] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[1] is undriven.
|
||||
Info: Net r:/WORK/el2_swerv/dma_hrdata[0] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][8] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][7] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][6] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][5] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][4] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][3] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][2] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][1] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[1][0] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][8] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][7] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][6] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][5] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][4] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][3] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][2] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][1] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/ifu_bp_fa_index_f[0][0] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][15] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][14] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][13] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][12] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][11] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][10] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][9] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][8] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][7] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][6] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][5] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][4] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][3] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][2] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][1] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[1][0] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][15] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][14] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][13] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][12] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][11] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][10] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][9] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][8] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][7] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][6] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][5] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][4] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][3] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][2] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][1] is undriven.
|
||||
Info: Net r:/WORK/el2_ifu_bp_ctl/bht_bank_clk[0][0] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[br_error] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[br_start_error] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][31] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][30] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][29] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][28] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][27] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][26] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][25] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][24] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][23] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][22] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][21] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][20] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][19] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][18] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][17] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][16] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][15] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][14] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][13] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][12] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][11] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][10] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][9] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][8] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][7] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][6] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][5] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][4] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][3] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][2] is undriven.
|
||||
Info: Net r:/WORK/el2_exu/exu_mp_pkt\[prett][1] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[6] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[5] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[4] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[3] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[2] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[1] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_hi_r[0] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[31] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[30] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[29] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[28] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[27] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[26] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[25] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[24] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[23] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[22] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[21] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[20] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[19] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[18] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[17] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[16] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[15] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[14] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[13] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[12] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[11] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[10] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[9] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[8] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[7] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[6] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[5] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[4] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[3] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[2] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[1] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_hi_r[0] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[6] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[5] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[4] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[3] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[2] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[1] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_data_ecc_lo_r[0] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[31] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[30] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[29] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[28] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[27] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[26] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[25] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[24] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[23] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[22] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[21] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[20] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[19] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[18] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[17] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[16] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[15] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[14] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[13] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[12] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[11] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[10] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[9] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[8] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[7] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[6] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[5] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[4] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[3] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[2] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[1] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/lsu_ld_data_r[0] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[31] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[30] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[29] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[28] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[27] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[26] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[25] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[24] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[23] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[22] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[21] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[20] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[19] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[18] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[17] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[16] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[15] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[14] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[13] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[12] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[11] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[10] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[9] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[8] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[7] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[6] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[5] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[4] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[3] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[2] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[1] is undriven.
|
||||
Info: Net r:/WORK/el2_lsu_dccm_ctl/dccm_rdata_lo_r[0] is undriven.
|
||||
Warning: Cell i:/WORK/quasar_wrapper/mem references black-box design /WORK/mem_DCCM_BANK_BITS2_DCCM_BITS16_DCCM_BYTE_WIDTH4_DCCM_ENABLE1_DCCM_FDATA_WIDTH39_DCCM_NUM_BANKS4_DCCM_SIZE64_DCCM_WIDTH_BITS2_ICACHE_BANK_BITS1_ICACHE_BANK_HI3_ICACHE_BANK_LO3_ICACHE_BANKS_WAY2_ICACHE_BEAT_ADDR_HI5_ICACHE_BEAT_BITS3_ICACHE_BYPASS_ENABLE1_ICACHE_DATA_DEPTH512_ICACHE_DATA_INDEX_LO4_ICACHE_ECC1_ICACHE_ENABLE1_ICACHE_INDEX_HI12_ICACHE_LN_SZ64_ICACHE_NUM_BYPASS2_ICACHE_NUM_BYPASS_WIDTH2_ICACHE_NUM_WAYS2_ICACHE_TAG_BYPASS_ENABLE1_ICACHE_TAG_DEPTH128_ICACHE_TAG_INDEX_LO6_ICACHE_TAG_LO13_ICACHE_TAG_NUM_BYPASS2_ICACHE_TAG_NUM_BYPASS_WIDTH2_ICACHE_WAYPACK1_ICCM_BANK_BITS2_ICCM_BANK_HI3_ICCM_BANK_INDEX_LO4_ICCM_BITS16_ICCM_ENABLE1_ICCM_INDEX_BITS12_ICCM_NUM_BANKS4 (FM-158)
|
||||
****************************************************
|
||||
|
||||
|
|
@ -70,17 +70,17 @@ if {![file isdirectory $fm_path_r]} {
|
|||
}
|
||||
# Loading verilog implementation file
|
||||
read_sverilog -i " \
|
||||
$LEC_ROOT/LEC_RTL/generated_rtl/pkt.sv
|
||||
$LEC_ROOT/LEC_RTL/generated_rtl/beh_lib.sv
|
||||
$LEC_ROOT/LEC_RTL/generated_rtl/mem_lib.sv
|
||||
$LEC_ROOT/LEC_RTL/generated_rtl/ifu_ic_mem.sv
|
||||
$LEC_ROOT/LEC_RTL/generated_rtl/gated_latch.sv
|
||||
$LEC_ROOT/LEC_RTL/generated_rtl/ifu_iccm_mem.sv
|
||||
$LEC_ROOT/LEC_RTL/generated_rtl/lsu_dccm_mem.sv
|
||||
$LEC_ROOT/LEC_RTL/generated_rtl/mem.sv
|
||||
$LEC_ROOT/LEC_RTL/generated_rtl/dmi_jtag_to_core_sync.sv
|
||||
$LEC_ROOT/LEC_RTL/generated_rtl/rvjtag_tap.sv
|
||||
$LEC_ROOT/LEC_RTL/generated_rtl/dmi_wrapper.sv
|
||||
$LEC_ROOT/LEC_RTL/BB_RTL/pkt.sv
|
||||
$LEC_ROOT/LEC_RTL/BB_RTL/beh_lib.sv
|
||||
$LEC_ROOT/LEC_RTL/BB_RTL/mem_lib.sv
|
||||
$LEC_ROOT/LEC_RTL/BB_RTL/ifu_ic_mem.sv
|
||||
$LEC_ROOT/LEC_RTL/BB_RTL/gated_latch.sv
|
||||
$LEC_ROOT/LEC_RTL/BB_RTL/ifu_iccm_mem.sv
|
||||
$LEC_ROOT/LEC_RTL/BB_RTL/lsu_dccm_mem.sv
|
||||
$LEC_ROOT/LEC_RTL/BB_RTL/mem.sv
|
||||
$LEC_ROOT/LEC_RTL/BB_RTL/dmi_jtag_to_core_sync.sv
|
||||
$LEC_ROOT/LEC_RTL/BB_RTL/rvjtag_tap.sv
|
||||
$LEC_ROOT/LEC_RTL/BB_RTL/dmi_wrapper.sv
|
||||
./generated_rtl/quasar_wrapper.sv
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue