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Update el2_bundle.scala

This commit is contained in:
Junaid Ahmed 2020-09-22 14:39:44 +05:00 committed by GitHub
parent 5474c212a2
commit ccdab1e35c
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 5 additions and 6 deletions
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11
src/main/scala/include/el2_bundle.scala
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@ -55,7 +55,7 @@ class el2_br_pkt_t extends Bundle {
val br_error = UInt(1.W) val br_error = UInt(1.W)
val br_start_error = UInt(1.W) val br_start_error = UInt(1.W)
val bank = UInt(1.W) val bank = UInt(1.W)
val prett = UInt(32.W) // predicted ret target val prett = UInt(32.W) // predicted ret target //[31:1] in swerv
val way = UInt(1.W) val way = UInt(1.W)
val ret = UInt(1.W) val ret = UInt(1.W)
} }
@ -80,7 +80,7 @@ class el2_predict_pkt_t extends Bundle {
val valid = UInt(1.W) val valid = UInt(1.W)
val br_error = UInt(1.W) val br_error = UInt(1.W)
val br_start_error = UInt(1.W) val br_start_error = UInt(1.W)
val prett = UInt(32.W) val prett = UInt(32.W) //[31:1] in swerv
val pcall = UInt(1.W) val pcall = UInt(1.W)
val pret = UInt(1.W) val pret = UInt(1.W)
val pja = UInt(1.W) val pja = UInt(1.W)
@ -102,7 +102,7 @@ class el2_trap_pkt_t extends Bundle {
} }
class el2_dest_pkt_t extends Bundle { class el2_dest_pkt_t extends Bundle {
val i0rd = UInt(4.W) val i0rd = UInt(5.W)
val i0load = UInt(1.W) val i0load = UInt(1.W)
val i0store = UInt(1.W) val i0store = UInt(1.W)
val i0div = UInt(1.W) val i0div = UInt(1.W)
@ -169,8 +169,8 @@ class el2_lsu_error_pkt_t extends Bundle {
val single_ecc_error = UInt(1.W) val single_ecc_error = UInt(1.W)
val inst_type = UInt(1.W) //0: Load, 1: Store val inst_type = UInt(1.W) //0: Load, 1: Store
val exc_type = UInt(1.W) //0: MisAligned, 1: Access Fault val exc_type = UInt(1.W) //0: MisAligned, 1: Access Fault
val mscause = UInt(1.W) val mscause = UInt(4.W)
val addr = UInt(1.W) val addr = UInt(32.W)
} }
class el2_dec_pkt_t extends Bundle { class el2_dec_pkt_t extends Bundle {
@ -322,4 +322,3 @@ class el2_cache_debug_pkt_t extends Bundle {
val icache_wr_valid = UInt(1.W) val icache_wr_valid = UInt(1.W)
} }