diff --git a/axi4_to_ahb.anno.json b/axi4_to_ahb.anno.json index c31d62c4..0e21bc50 100644 --- a/axi4_to_ahb.anno.json +++ b/axi4_to_ahb.anno.json @@ -21,7 +21,9 @@ "class":"firrtl.transforms.CombinationalPath", "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_wready", "sources":[ - "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid" + "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_bready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_rready" ] }, { @@ -33,13 +35,6 @@ "~axi4_to_ahb|axi4_to_ahb>io_axi_rready" ] }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_awready", - "sources":[ - "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_haddr", @@ -60,6 +55,24 @@ "~axi4_to_ahb|axi4_to_ahb>io_axi_rready" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_awready", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_bready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_rready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_arready", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_bready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_rready" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_rvalid", diff --git a/axi4_to_ahb.fir b/axi4_to_ahb.fir index 68a58808..e0e01d8d 100644 --- a/axi4_to_ahb.fir +++ b/axi4_to_ahb.fir @@ -245,10 +245,24 @@ circuit axi4_to_ahb : input reset : AsyncReset output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi_awvalid : UInt<1>, flip axi_awid : UInt<1>, flip axi_awaddr : UInt<32>, flip axi_awsize : UInt<3>, flip axi_awprot : UInt<3>, flip axi_wvalid : UInt<1>, flip axi_wdata : UInt<64>, flip axi_wstrb : UInt<8>, flip axi_wlast : UInt<1>, flip axi_bready : UInt<1>, flip axi_arvalid : UInt<1>, flip axi_arid : UInt<1>, flip axi_araddr : UInt<32>, flip axi_arsize : UInt<3>, flip axi_arprot : UInt<3>, flip axi_rready : UInt<1>, flip ahb_hrdata : UInt<64>, flip ahb_hready : UInt<1>, flip ahb_hresp : UInt<1>, axi_awready : UInt<1>, axi_wready : UInt<1>, axi_bvalid : UInt<1>, axi_bresp : UInt<2>, axi_bid : UInt<1>, axi_arready : UInt<1>, axi_rvalid : UInt<1>, axi_rid : UInt<1>, axi_rdata : UInt<64>, axi_rresp : UInt<2>, axi_rlast : UInt<1>, ahb_haddr : UInt<32>, ahb_hburst : UInt<3>, ahb_hmastlock : UInt<1>, ahb_hprot : UInt<4>, ahb_hsize : UInt<3>, ahb_htrans : UInt<2>, ahb_hwrite : UInt<1>, ahb_hwdata : UInt<64>} + wire buf_rst : UInt<1> + buf_rst <= UInt<1>("h00") + wire buf_state_en : UInt<1> + buf_state_en <= UInt<1>("h00") + wire ahbm_clk : Clock @[axi4_to_ahb.scala 62:22] + wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 63:27] + wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 64:27] wire buf_state : UInt<3> buf_state <= UInt<3>("h00") wire buf_nxtstate : UInt<3> buf_nxtstate <= UInt<3>("h00") + node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 69:36] + node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 69:16] + node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 69:65] + node _T_3 = and(_T_1, _T_2) @[axi4_to_ahb.scala 69:63] + reg _T_4 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 69:12] + _T_4 <= _T_3 @[axi4_to_ahb.scala 69:12] + buf_state <= _T_4 @[axi4_to_ahb.scala 68:13] wire slave_valid : UInt<1> slave_valid <= UInt<1>("h00") wire slave_ready : UInt<1> @@ -283,8 +297,8 @@ circuit axi4_to_ahb : wrbuf_byteen <= UInt<8>("h00") wire bus_write_clk_en : UInt<1> bus_write_clk_en <= UInt<1>("h00") - wire bus_clk : Clock @[axi4_to_ahb.scala 82:21] - wire bus_write_clk : Clock @[axi4_to_ahb.scala 83:27] + wire bus_clk : Clock @[axi4_to_ahb.scala 90:21] + wire bus_write_clk : Clock @[axi4_to_ahb.scala 91:27] wire master_valid : UInt<1> master_valid <= UInt<1>("h00") wire master_ready : UInt<1> @@ -315,8 +329,6 @@ circuit axi4_to_ahb : buf_data <= UInt<64>("h00") wire buf_tag : UInt<1> buf_tag <= UInt<1>("h00") - wire buf_rst : UInt<1> - buf_rst <= UInt<1>("h00") wire buf_tag_in : UInt<1> buf_tag_in <= UInt<1>("h00") wire buf_addr_in : UInt<32> @@ -331,8 +343,6 @@ circuit axi4_to_ahb : buf_aligned_in <= UInt<1>("h00") wire buf_size_in : UInt<3> buf_size_in <= UInt<3>("h00") - wire buf_state_en : UInt<1> - buf_state_en <= UInt<1>("h00") wire buf_wr_en : UInt<1> buf_wr_en <= UInt<1>("h00") wire buf_data_wr_en : UInt<1> @@ -397,1009 +407,1011 @@ circuit axi4_to_ahb : ahbm_addr_clken <= UInt<1>("h00") wire ahbm_data_clken : UInt<1> ahbm_data_clken <= UInt<1>("h00") - wire buf_clk : Clock @[axi4_to_ahb.scala 150:21] - wire ahbm_clk : Clock @[axi4_to_ahb.scala 152:22] - wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 153:27] - wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 154:27] - node _T = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 192:27] - wr_cmd_vld <= _T @[axi4_to_ahb.scala 192:14] - node _T_1 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 193:30] - master_valid <= _T_1 @[axi4_to_ahb.scala 193:16] - node _T_2 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 194:38] - node _T_3 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 194:51] - node _T_4 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 194:76] - node _T_5 = mux(_T_2, _T_3, _T_4) @[axi4_to_ahb.scala 194:20] - master_tag <= _T_5 @[axi4_to_ahb.scala 194:14] - node _T_6 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 195:38] - node _T_7 = mux(_T_6, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 195:20] - master_opc <= _T_7 @[axi4_to_ahb.scala 195:14] - node _T_8 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 196:39] - node _T_9 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 196:53] - node _T_10 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 196:75] - node _T_11 = mux(_T_8, _T_9, _T_10) @[axi4_to_ahb.scala 196:21] - master_addr <= _T_11 @[axi4_to_ahb.scala 196:15] - node _T_12 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 197:39] - node _T_13 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 197:53] - node _T_14 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 197:74] - node _T_15 = mux(_T_12, _T_13, _T_14) @[axi4_to_ahb.scala 197:21] - master_size <= _T_15 @[axi4_to_ahb.scala 197:15] - node _T_16 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 198:32] - master_byteen <= _T_16 @[axi4_to_ahb.scala 198:17] - node _T_17 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 199:29] - master_wdata <= _T_17 @[axi4_to_ahb.scala 199:16] - node _T_18 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 202:32] - node _T_19 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 202:57] - node _T_20 = and(_T_18, _T_19) @[axi4_to_ahb.scala 202:46] - io.axi_bvalid <= _T_20 @[axi4_to_ahb.scala 202:17] - node _T_21 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 203:32] - node _T_22 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 203:59] - node _T_23 = mux(_T_22, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 203:49] - node _T_24 = mux(_T_21, UInt<2>("h02"), _T_23) @[axi4_to_ahb.scala 203:22] - io.axi_bresp <= _T_24 @[axi4_to_ahb.scala 203:16] - node _T_25 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 204:26] - io.axi_bid <= _T_25 @[axi4_to_ahb.scala 204:14] - node _T_26 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 206:32] - node _T_27 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 206:58] - node _T_28 = eq(_T_27, UInt<1>("h00")) @[axi4_to_ahb.scala 206:65] - node _T_29 = and(_T_26, _T_28) @[axi4_to_ahb.scala 206:46] - io.axi_rvalid <= _T_29 @[axi4_to_ahb.scala 206:17] - node _T_30 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 207:32] - node _T_31 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 207:59] - node _T_32 = mux(_T_31, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 207:49] - node _T_33 = mux(_T_30, UInt<2>("h02"), _T_32) @[axi4_to_ahb.scala 207:22] - io.axi_rresp <= _T_33 @[axi4_to_ahb.scala 207:16] - node _T_34 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 208:26] - io.axi_rid <= _T_34 @[axi4_to_ahb.scala 208:14] - node _T_35 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 209:30] - io.axi_rdata <= _T_35 @[axi4_to_ahb.scala 209:16] - node _T_36 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 210:32] - slave_ready <= _T_36 @[axi4_to_ahb.scala 210:15] - node _T_37 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 213:56] - node _T_38 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 213:91] - node _T_39 = or(_T_37, _T_38) @[axi4_to_ahb.scala 213:74] - node _T_40 = and(io.bus_clk_en, _T_39) @[axi4_to_ahb.scala 213:37] - bus_write_clk_en <= _T_40 @[axi4_to_ahb.scala 213:20] + wire buf_clk : Clock @[axi4_to_ahb.scala 158:21] + node _T_5 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 200:27] + wr_cmd_vld <= _T_5 @[axi4_to_ahb.scala 200:14] + node _T_6 = or(wr_cmd_vld, io.axi_arvalid) @[axi4_to_ahb.scala 201:30] + master_valid <= _T_6 @[axi4_to_ahb.scala 201:16] + node _T_7 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 202:38] + node _T_8 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 202:51] + node _T_9 = bits(io.axi_arid, 0, 0) @[axi4_to_ahb.scala 202:76] + node _T_10 = mux(_T_7, _T_8, _T_9) @[axi4_to_ahb.scala 202:20] + master_tag <= _T_10 @[axi4_to_ahb.scala 202:14] + node _T_11 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 203:38] + node _T_12 = mux(_T_11, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 203:20] + master_opc <= _T_12 @[axi4_to_ahb.scala 203:14] + node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 204:39] + node _T_14 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 204:53] + node _T_15 = bits(io.axi_araddr, 31, 0) @[axi4_to_ahb.scala 204:75] + node _T_16 = mux(_T_13, _T_14, _T_15) @[axi4_to_ahb.scala 204:21] + master_addr <= _T_16 @[axi4_to_ahb.scala 204:15] + node _T_17 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 205:39] + node _T_18 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 205:53] + node _T_19 = bits(io.axi_arsize, 2, 0) @[axi4_to_ahb.scala 205:74] + node _T_20 = mux(_T_17, _T_18, _T_19) @[axi4_to_ahb.scala 205:21] + master_size <= _T_20 @[axi4_to_ahb.scala 205:15] + node _T_21 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 206:32] + master_byteen <= _T_21 @[axi4_to_ahb.scala 206:17] + node _T_22 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 207:29] + master_wdata <= _T_22 @[axi4_to_ahb.scala 207:16] + node _T_23 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 210:32] + node _T_24 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 210:57] + node _T_25 = and(_T_23, _T_24) @[axi4_to_ahb.scala 210:46] + io.axi_bvalid <= _T_25 @[axi4_to_ahb.scala 210:17] + node _T_26 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 211:32] + node _T_27 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 211:59] + node _T_28 = mux(_T_27, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 211:49] + node _T_29 = mux(_T_26, UInt<2>("h02"), _T_28) @[axi4_to_ahb.scala 211:22] + io.axi_bresp <= _T_29 @[axi4_to_ahb.scala 211:16] + node _T_30 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 212:26] + io.axi_bid <= _T_30 @[axi4_to_ahb.scala 212:14] + node _T_31 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 214:32] + node _T_32 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 214:58] + node _T_33 = eq(_T_32, UInt<1>("h00")) @[axi4_to_ahb.scala 214:65] + node _T_34 = and(_T_31, _T_33) @[axi4_to_ahb.scala 214:46] + io.axi_rvalid <= _T_34 @[axi4_to_ahb.scala 214:17] + node _T_35 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 215:32] + node _T_36 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 215:59] + node _T_37 = mux(_T_36, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 215:49] + node _T_38 = mux(_T_35, UInt<2>("h02"), _T_37) @[axi4_to_ahb.scala 215:22] + io.axi_rresp <= _T_38 @[axi4_to_ahb.scala 215:16] + node _T_39 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 216:26] + io.axi_rid <= _T_39 @[axi4_to_ahb.scala 216:14] + node _T_40 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 217:30] + io.axi_rdata <= _T_40 @[axi4_to_ahb.scala 217:16] + node _T_41 = and(io.axi_bready, io.axi_rready) @[axi4_to_ahb.scala 218:32] + slave_ready <= _T_41 @[axi4_to_ahb.scala 218:15] + node _T_42 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 221:56] + node _T_43 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 221:91] + node _T_44 = or(_T_42, _T_43) @[axi4_to_ahb.scala 221:74] + node _T_45 = and(io.bus_clk_en, _T_44) @[axi4_to_ahb.scala 221:37] + bus_write_clk_en <= _T_45 @[axi4_to_ahb.scala 221:20] inst rvclkhdr of rvclkhdr @[el2_lib.scala 483:22] rvclkhdr.clock <= clock rvclkhdr.reset <= reset rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr.io.en <= io.bus_clk_en @[el2_lib.scala 485:16] rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 215:11] - node _T_41 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 216:59] + bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 223:11] + node _T_46 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 224:59] inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 483:22] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] - rvclkhdr_1.io.en <= _T_41 @[el2_lib.scala 485:16] + rvclkhdr_1.io.en <= _T_46 @[el2_lib.scala 485:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 216:17] - io.ahb_htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 219:17] - buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 221:16] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 222:18] - buf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 223:18] - buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 224:18] - slvbuf_error_in <= UInt<1>("h00") @[axi4_to_ahb.scala 225:21] - slvbuf_error_en <= UInt<1>("h00") @[axi4_to_ahb.scala 226:21] - buf_write_in <= UInt<1>("h00") @[axi4_to_ahb.scala 227:18] - cmd_done <= UInt<1>("h00") @[axi4_to_ahb.scala 228:18] - trxn_done <= UInt<1>("h00") @[axi4_to_ahb.scala 229:18] - buf_cmd_byte_ptr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 230:23] - buf_cmd_byte_ptr <= UInt<1>("h00") @[axi4_to_ahb.scala 231:20] - slave_valid_pre <= UInt<1>("h00") @[axi4_to_ahb.scala 232:21] - slvbuf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 233:19] - bypass_en <= UInt<1>("h00") @[axi4_to_ahb.scala 234:20] - rd_bypass_idle <= UInt<1>("h00") @[axi4_to_ahb.scala 235:18] - node _T_42 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] - when _T_42 : @[Conditional.scala 40:58] - node _T_43 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 240:34] - node _T_44 = eq(_T_43, UInt<1>("h01")) @[axi4_to_ahb.scala 240:41] - buf_write_in <= _T_44 @[axi4_to_ahb.scala 240:20] - node _T_45 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 241:49] - node _T_46 = mux(_T_45, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 241:29] - node _T_47 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 242:36] - buf_state_en <= _T_47 @[axi4_to_ahb.scala 242:20] - buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 243:17] - node _T_48 = eq(_T_46, UInt<3>("h02")) @[axi4_to_ahb.scala 244:54] - node _T_49 = and(buf_state_en, _T_48) @[axi4_to_ahb.scala 244:38] - buf_data_wr_en <= _T_49 @[axi4_to_ahb.scala 244:22] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 245:27] - node _T_50 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 247:50] - node _T_51 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 247:92] - node _T_52 = add(UInt<1>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 176:52] - node _T_53 = tail(_T_52, 1) @[axi4_to_ahb.scala 176:52] - node _T_54 = mux(UInt<1>("h00"), _T_53, UInt<1>("h00")) @[axi4_to_ahb.scala 176:24] - node _T_55 = bits(_T_51, 0, 0) @[axi4_to_ahb.scala 177:44] - node _T_56 = geq(UInt<1>("h00"), _T_54) @[axi4_to_ahb.scala 177:62] - node _T_57 = and(_T_55, _T_56) @[axi4_to_ahb.scala 177:48] - node _T_58 = bits(_T_51, 1, 1) @[axi4_to_ahb.scala 177:44] - node _T_59 = geq(UInt<1>("h01"), _T_54) @[axi4_to_ahb.scala 177:62] - node _T_60 = and(_T_58, _T_59) @[axi4_to_ahb.scala 177:48] - node _T_61 = bits(_T_51, 2, 2) @[axi4_to_ahb.scala 177:44] - node _T_62 = geq(UInt<2>("h02"), _T_54) @[axi4_to_ahb.scala 177:62] - node _T_63 = and(_T_61, _T_62) @[axi4_to_ahb.scala 177:48] - node _T_64 = bits(_T_51, 3, 3) @[axi4_to_ahb.scala 177:44] - node _T_65 = geq(UInt<2>("h03"), _T_54) @[axi4_to_ahb.scala 177:62] - node _T_66 = and(_T_64, _T_65) @[axi4_to_ahb.scala 177:48] - node _T_67 = bits(_T_51, 4, 4) @[axi4_to_ahb.scala 177:44] - node _T_68 = geq(UInt<3>("h04"), _T_54) @[axi4_to_ahb.scala 177:62] - node _T_69 = and(_T_67, _T_68) @[axi4_to_ahb.scala 177:48] - node _T_70 = bits(_T_51, 5, 5) @[axi4_to_ahb.scala 177:44] - node _T_71 = geq(UInt<3>("h05"), _T_54) @[axi4_to_ahb.scala 177:62] - node _T_72 = and(_T_70, _T_71) @[axi4_to_ahb.scala 177:48] - node _T_73 = bits(_T_51, 6, 6) @[axi4_to_ahb.scala 177:44] - node _T_74 = geq(UInt<3>("h06"), _T_54) @[axi4_to_ahb.scala 177:62] - node _T_75 = and(_T_73, _T_74) @[axi4_to_ahb.scala 177:48] - node _T_76 = bits(_T_51, 7, 7) @[axi4_to_ahb.scala 177:44] - node _T_77 = geq(UInt<3>("h07"), _T_54) @[axi4_to_ahb.scala 177:62] - node _T_78 = and(_T_76, _T_77) @[axi4_to_ahb.scala 177:48] - node _T_79 = mux(_T_78, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_80 = mux(_T_75, UInt<3>("h06"), _T_79) @[Mux.scala 98:16] - node _T_81 = mux(_T_72, UInt<3>("h05"), _T_80) @[Mux.scala 98:16] - node _T_82 = mux(_T_69, UInt<3>("h04"), _T_81) @[Mux.scala 98:16] - node _T_83 = mux(_T_66, UInt<2>("h03"), _T_82) @[Mux.scala 98:16] - node _T_84 = mux(_T_63, UInt<2>("h02"), _T_83) @[Mux.scala 98:16] - node _T_85 = mux(_T_60, UInt<1>("h01"), _T_84) @[Mux.scala 98:16] - node _T_86 = mux(_T_57, UInt<1>("h00"), _T_85) @[Mux.scala 98:16] - node _T_87 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 247:141] - node _T_88 = mux(_T_50, _T_86, _T_87) @[axi4_to_ahb.scala 247:30] - buf_cmd_byte_ptr <= _T_88 @[axi4_to_ahb.scala 247:24] - bypass_en <= buf_state_en @[axi4_to_ahb.scala 248:17] - node _T_89 = eq(_T_46, UInt<3>("h01")) @[axi4_to_ahb.scala 249:51] - node _T_90 = and(bypass_en, _T_89) @[axi4_to_ahb.scala 249:35] - rd_bypass_idle <= _T_90 @[axi4_to_ahb.scala 249:22] - node _T_91 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] - node _T_92 = mux(_T_91, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_93 = and(_T_92, UInt<2>("h02")) @[axi4_to_ahb.scala 250:45] - io.ahb_htrans <= _T_93 @[axi4_to_ahb.scala 250:21] + bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 224:17] + io.ahb_htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 227:17] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 228:16] + buf_state_en <= UInt<1>("h00") @[axi4_to_ahb.scala 229:16] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 230:18] + buf_data_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 232:18] + slvbuf_error_in <= UInt<1>("h00") @[axi4_to_ahb.scala 233:21] + slvbuf_error_en <= UInt<1>("h00") @[axi4_to_ahb.scala 234:21] + buf_write_in <= UInt<1>("h00") @[axi4_to_ahb.scala 235:18] + cmd_done <= UInt<1>("h00") @[axi4_to_ahb.scala 236:18] + trxn_done <= UInt<1>("h00") @[axi4_to_ahb.scala 237:18] + buf_cmd_byte_ptr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 238:23] + buf_cmd_byte_ptr <= UInt<1>("h00") @[axi4_to_ahb.scala 239:20] + slave_valid_pre <= UInt<1>("h00") @[axi4_to_ahb.scala 240:21] + slvbuf_wr_en <= UInt<1>("h00") @[axi4_to_ahb.scala 241:19] + bypass_en <= UInt<1>("h00") @[axi4_to_ahb.scala 242:20] + rd_bypass_idle <= UInt<1>("h00") @[axi4_to_ahb.scala 243:18] + node _T_47 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] + when _T_47 : @[Conditional.scala 40:58] + node _T_48 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 248:34] + node _T_49 = eq(_T_48, UInt<1>("h01")) @[axi4_to_ahb.scala 248:41] + buf_write_in <= _T_49 @[axi4_to_ahb.scala 248:20] + node _T_50 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 249:46] + node _T_51 = mux(_T_50, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 249:26] + buf_nxtstate <= _T_51 @[axi4_to_ahb.scala 249:20] + node _T_52 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 250:36] + buf_state_en <= _T_52 @[axi4_to_ahb.scala 250:20] + node _T_53 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 252:54] + node _T_54 = and(buf_state_en, _T_53) @[axi4_to_ahb.scala 252:38] + buf_data_wr_en <= _T_54 @[axi4_to_ahb.scala 252:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 253:27] + node _T_55 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 255:50] + node _T_56 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 255:92] + node _T_57 = add(UInt<1>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 184:52] + node _T_58 = tail(_T_57, 1) @[axi4_to_ahb.scala 184:52] + node _T_59 = mux(UInt<1>("h00"), _T_58, UInt<1>("h00")) @[axi4_to_ahb.scala 184:24] + node _T_60 = bits(_T_56, 0, 0) @[axi4_to_ahb.scala 185:44] + node _T_61 = geq(UInt<1>("h00"), _T_59) @[axi4_to_ahb.scala 185:62] + node _T_62 = and(_T_60, _T_61) @[axi4_to_ahb.scala 185:48] + node _T_63 = bits(_T_56, 1, 1) @[axi4_to_ahb.scala 185:44] + node _T_64 = geq(UInt<1>("h01"), _T_59) @[axi4_to_ahb.scala 185:62] + node _T_65 = and(_T_63, _T_64) @[axi4_to_ahb.scala 185:48] + node _T_66 = bits(_T_56, 2, 2) @[axi4_to_ahb.scala 185:44] + node _T_67 = geq(UInt<2>("h02"), _T_59) @[axi4_to_ahb.scala 185:62] + node _T_68 = and(_T_66, _T_67) @[axi4_to_ahb.scala 185:48] + node _T_69 = bits(_T_56, 3, 3) @[axi4_to_ahb.scala 185:44] + node _T_70 = geq(UInt<2>("h03"), _T_59) @[axi4_to_ahb.scala 185:62] + node _T_71 = and(_T_69, _T_70) @[axi4_to_ahb.scala 185:48] + node _T_72 = bits(_T_56, 4, 4) @[axi4_to_ahb.scala 185:44] + node _T_73 = geq(UInt<3>("h04"), _T_59) @[axi4_to_ahb.scala 185:62] + node _T_74 = and(_T_72, _T_73) @[axi4_to_ahb.scala 185:48] + node _T_75 = bits(_T_56, 5, 5) @[axi4_to_ahb.scala 185:44] + node _T_76 = geq(UInt<3>("h05"), _T_59) @[axi4_to_ahb.scala 185:62] + node _T_77 = and(_T_75, _T_76) @[axi4_to_ahb.scala 185:48] + node _T_78 = bits(_T_56, 6, 6) @[axi4_to_ahb.scala 185:44] + node _T_79 = geq(UInt<3>("h06"), _T_59) @[axi4_to_ahb.scala 185:62] + node _T_80 = and(_T_78, _T_79) @[axi4_to_ahb.scala 185:48] + node _T_81 = bits(_T_56, 7, 7) @[axi4_to_ahb.scala 185:44] + node _T_82 = geq(UInt<3>("h07"), _T_59) @[axi4_to_ahb.scala 185:62] + node _T_83 = and(_T_81, _T_82) @[axi4_to_ahb.scala 185:48] + node _T_84 = mux(_T_83, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_85 = mux(_T_80, UInt<3>("h06"), _T_84) @[Mux.scala 98:16] + node _T_86 = mux(_T_77, UInt<3>("h05"), _T_85) @[Mux.scala 98:16] + node _T_87 = mux(_T_74, UInt<3>("h04"), _T_86) @[Mux.scala 98:16] + node _T_88 = mux(_T_71, UInt<2>("h03"), _T_87) @[Mux.scala 98:16] + node _T_89 = mux(_T_68, UInt<2>("h02"), _T_88) @[Mux.scala 98:16] + node _T_90 = mux(_T_65, UInt<1>("h01"), _T_89) @[Mux.scala 98:16] + node _T_91 = mux(_T_62, UInt<1>("h00"), _T_90) @[Mux.scala 98:16] + node _T_92 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 255:141] + node _T_93 = mux(_T_55, _T_91, _T_92) @[axi4_to_ahb.scala 255:30] + buf_cmd_byte_ptr <= _T_93 @[axi4_to_ahb.scala 255:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 256:17] + node _T_94 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 257:51] + node _T_95 = and(bypass_en, _T_94) @[axi4_to_ahb.scala 257:35] + rd_bypass_idle <= _T_95 @[axi4_to_ahb.scala 257:22] + node _T_96 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] + node _T_97 = mux(_T_96, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_98 = and(_T_97, UInt<2>("h02")) @[axi4_to_ahb.scala 258:45] + io.ahb_htrans <= _T_98 @[axi4_to_ahb.scala 258:21] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] - node _T_94 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] - when _T_94 : @[Conditional.scala 39:67] - node _T_95 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 254:56] - node _T_96 = eq(_T_95, UInt<1>("h00")) @[axi4_to_ahb.scala 254:63] - node _T_97 = and(master_valid, _T_96) @[axi4_to_ahb.scala 254:43] - node _T_98 = bits(_T_97, 0, 0) @[axi4_to_ahb.scala 254:84] - node _T_99 = mux(_T_98, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 254:28] - node _T_100 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 255:51] - node _T_101 = neq(_T_100, UInt<1>("h00")) @[axi4_to_ahb.scala 255:58] - node _T_102 = and(ahb_hready_q, _T_101) @[axi4_to_ahb.scala 255:36] - node _T_103 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 255:72] - node _T_104 = and(_T_102, _T_103) @[axi4_to_ahb.scala 255:70] - buf_state_en <= _T_104 @[axi4_to_ahb.scala 255:20] - node _T_105 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 256:34] - node _T_106 = and(buf_state_en, _T_105) @[axi4_to_ahb.scala 256:32] - cmd_done <= _T_106 @[axi4_to_ahb.scala 256:16] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 257:20] - node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 258:55] - node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 258:62] - node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 258:40] - node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 258:76] - node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 258:74] - node _T_112 = eq(_T_99, UInt<3>("h06")) @[axi4_to_ahb.scala 258:107] - node _T_113 = and(_T_111, _T_112) @[axi4_to_ahb.scala 258:91] - buf_wr_en <= _T_113 @[axi4_to_ahb.scala 259:17] - node _T_114 = and(_T_113, master_valid) @[axi4_to_ahb.scala 260:33] - bypass_en <= _T_114 @[axi4_to_ahb.scala 260:17] - node _T_115 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 261:47] - node _T_116 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 261:62] - node _T_117 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 261:78] - node _T_118 = mux(_T_115, _T_116, _T_117) @[axi4_to_ahb.scala 261:30] - buf_cmd_byte_ptr <= _T_118 @[axi4_to_ahb.scala 261:24] - node _T_119 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 262:44] - node _T_120 = or(_T_119, bypass_en) @[axi4_to_ahb.scala 262:58] - node _T_121 = bits(_T_120, 0, 0) @[Bitwise.scala 72:15] - node _T_122 = mux(_T_121, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_123 = and(UInt<2>("h02"), _T_122) @[axi4_to_ahb.scala 262:32] - io.ahb_htrans <= _T_123 @[axi4_to_ahb.scala 262:21] + node _T_99 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] + when _T_99 : @[Conditional.scala 39:67] + node _T_100 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 262:54] + node _T_101 = eq(_T_100, UInt<1>("h00")) @[axi4_to_ahb.scala 262:61] + node _T_102 = and(master_valid, _T_101) @[axi4_to_ahb.scala 262:41] + node _T_103 = bits(_T_102, 0, 0) @[axi4_to_ahb.scala 262:82] + node _T_104 = mux(_T_103, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 262:26] + buf_nxtstate <= _T_104 @[axi4_to_ahb.scala 262:20] + node _T_105 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 263:51] + node _T_106 = neq(_T_105, UInt<1>("h00")) @[axi4_to_ahb.scala 263:58] + node _T_107 = and(ahb_hready_q, _T_106) @[axi4_to_ahb.scala 263:36] + node _T_108 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 263:72] + node _T_109 = and(_T_107, _T_108) @[axi4_to_ahb.scala 263:70] + buf_state_en <= _T_109 @[axi4_to_ahb.scala 263:20] + node _T_110 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 264:34] + node _T_111 = and(buf_state_en, _T_110) @[axi4_to_ahb.scala 264:32] + cmd_done <= _T_111 @[axi4_to_ahb.scala 264:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 265:20] + node _T_112 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 266:52] + node _T_113 = neq(_T_112, UInt<1>("h00")) @[axi4_to_ahb.scala 266:59] + node _T_114 = and(ahb_hready_q, _T_113) @[axi4_to_ahb.scala 266:37] + node _T_115 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 266:73] + node _T_116 = and(_T_114, _T_115) @[axi4_to_ahb.scala 266:71] + node _T_117 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 266:122] + node _T_118 = eq(_T_117, UInt<1>("h00")) @[axi4_to_ahb.scala 266:129] + node _T_119 = and(master_valid, _T_118) @[axi4_to_ahb.scala 266:109] + node _T_120 = bits(_T_119, 0, 0) @[axi4_to_ahb.scala 266:150] + node _T_121 = mux(_T_120, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 266:94] + node _T_122 = eq(_T_121, UInt<3>("h06")) @[axi4_to_ahb.scala 266:174] + node _T_123 = and(_T_116, _T_122) @[axi4_to_ahb.scala 266:88] + master_ready <= _T_123 @[axi4_to_ahb.scala 266:20] + node _T_124 = and(master_ready, master_valid) @[axi4_to_ahb.scala 268:33] + bypass_en <= _T_124 @[axi4_to_ahb.scala 268:17] + node _T_125 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 269:47] + node _T_126 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 269:62] + node _T_127 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 269:78] + node _T_128 = mux(_T_125, _T_126, _T_127) @[axi4_to_ahb.scala 269:30] + buf_cmd_byte_ptr <= _T_128 @[axi4_to_ahb.scala 269:24] + node _T_129 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 270:44] + node _T_130 = or(_T_129, bypass_en) @[axi4_to_ahb.scala 270:58] + node _T_131 = bits(_T_130, 0, 0) @[Bitwise.scala 72:15] + node _T_132 = mux(_T_131, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_133 = and(UInt<2>("h02"), _T_132) @[axi4_to_ahb.scala 270:32] + io.ahb_htrans <= _T_133 @[axi4_to_ahb.scala 270:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_124 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] - when _T_124 : @[Conditional.scala 39:67] - node _T_125 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 266:41] - node _T_126 = and(ahb_hready_q, _T_125) @[axi4_to_ahb.scala 266:39] - node _T_127 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 266:84] - node _T_128 = eq(_T_127, UInt<1>("h01")) @[axi4_to_ahb.scala 266:91] - node _T_129 = and(master_valid, _T_128) @[axi4_to_ahb.scala 266:72] - node _T_130 = eq(_T_129, UInt<1>("h00")) @[axi4_to_ahb.scala 266:57] - node _T_131 = and(_T_126, _T_130) @[axi4_to_ahb.scala 266:55] - node _T_132 = and(master_valid, _T_131) @[axi4_to_ahb.scala 267:34] - node _T_133 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 267:62] - node _T_134 = eq(_T_133, UInt<1>("h00")) @[axi4_to_ahb.scala 267:69] - node _T_135 = and(_T_132, _T_134) @[axi4_to_ahb.scala 267:49] - buf_wr_en <= _T_135 @[axi4_to_ahb.scala 267:17] - node _T_136 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 268:47] - node _T_137 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 268:86] - node _T_138 = mux(_T_137, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 268:69] - node _T_139 = mux(_T_136, UInt<3>("h07"), _T_138) @[axi4_to_ahb.scala 268:28] - node _T_140 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 269:37] - buf_state_en <= _T_140 @[axi4_to_ahb.scala 269:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 270:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 271:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 272:23] - node _T_141 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 273:41] - node _T_142 = and(buf_state_en, _T_141) @[axi4_to_ahb.scala 273:39] - slave_valid_pre <= _T_142 @[axi4_to_ahb.scala 273:23] - node _T_143 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 274:34] - node _T_144 = and(buf_state_en, _T_143) @[axi4_to_ahb.scala 274:32] - cmd_done <= _T_144 @[axi4_to_ahb.scala 274:16] - node _T_145 = and(_T_131, master_valid) @[axi4_to_ahb.scala 275:33] - node _T_146 = eq(_T_139, UInt<3>("h06")) @[axi4_to_ahb.scala 275:64] - node _T_147 = and(_T_145, _T_146) @[axi4_to_ahb.scala 275:48] - node _T_148 = and(_T_147, buf_state_en) @[axi4_to_ahb.scala 275:79] - bypass_en <= _T_148 @[axi4_to_ahb.scala 275:17] - node _T_149 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 276:47] - node _T_150 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 276:62] - node _T_151 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 276:78] - node _T_152 = mux(_T_149, _T_150, _T_151) @[axi4_to_ahb.scala 276:30] - buf_cmd_byte_ptr <= _T_152 @[axi4_to_ahb.scala 276:24] - node _T_153 = neq(_T_139, UInt<3>("h06")) @[axi4_to_ahb.scala 277:59] - node _T_154 = and(_T_153, buf_state_en) @[axi4_to_ahb.scala 277:74] - node _T_155 = eq(_T_154, UInt<1>("h00")) @[axi4_to_ahb.scala 277:43] - node _T_156 = bits(_T_155, 0, 0) @[Bitwise.scala 72:15] - node _T_157 = mux(_T_156, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_158 = and(UInt<2>("h02"), _T_157) @[axi4_to_ahb.scala 277:32] - io.ahb_htrans <= _T_158 @[axi4_to_ahb.scala 277:21] - slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 278:20] + node _T_134 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] + when _T_134 : @[Conditional.scala 39:67] + node _T_135 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 274:39] + node _T_136 = and(ahb_hready_q, _T_135) @[axi4_to_ahb.scala 274:37] + node _T_137 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 274:82] + node _T_138 = eq(_T_137, UInt<1>("h01")) @[axi4_to_ahb.scala 274:89] + node _T_139 = and(master_valid, _T_138) @[axi4_to_ahb.scala 274:70] + node _T_140 = eq(_T_139, UInt<1>("h00")) @[axi4_to_ahb.scala 274:55] + node _T_141 = and(_T_136, _T_140) @[axi4_to_ahb.scala 274:53] + master_ready <= _T_141 @[axi4_to_ahb.scala 274:20] + node _T_142 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 276:45] + node _T_143 = and(master_valid, master_ready) @[axi4_to_ahb.scala 276:82] + node _T_144 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 276:110] + node _T_145 = eq(_T_144, UInt<1>("h00")) @[axi4_to_ahb.scala 276:117] + node _T_146 = and(_T_143, _T_145) @[axi4_to_ahb.scala 276:97] + node _T_147 = bits(_T_146, 0, 0) @[axi4_to_ahb.scala 276:138] + node _T_148 = mux(_T_147, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 276:67] + node _T_149 = mux(_T_142, UInt<3>("h07"), _T_148) @[axi4_to_ahb.scala 276:26] + buf_nxtstate <= _T_149 @[axi4_to_ahb.scala 276:20] + node _T_150 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 277:37] + buf_state_en <= _T_150 @[axi4_to_ahb.scala 277:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 278:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 279:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 280:23] + node _T_151 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 281:41] + node _T_152 = and(buf_state_en, _T_151) @[axi4_to_ahb.scala 281:39] + slave_valid_pre <= _T_152 @[axi4_to_ahb.scala 281:23] + node _T_153 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 282:34] + node _T_154 = and(buf_state_en, _T_153) @[axi4_to_ahb.scala 282:32] + cmd_done <= _T_154 @[axi4_to_ahb.scala 282:16] + node _T_155 = and(master_ready, master_valid) @[axi4_to_ahb.scala 283:33] + node _T_156 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 283:64] + node _T_157 = and(_T_155, _T_156) @[axi4_to_ahb.scala 283:48] + node _T_158 = and(_T_157, buf_state_en) @[axi4_to_ahb.scala 283:79] + bypass_en <= _T_158 @[axi4_to_ahb.scala 283:17] + node _T_159 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 284:47] + node _T_160 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 284:62] + node _T_161 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 284:78] + node _T_162 = mux(_T_159, _T_160, _T_161) @[axi4_to_ahb.scala 284:30] + buf_cmd_byte_ptr <= _T_162 @[axi4_to_ahb.scala 284:24] + node _T_163 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 285:59] + node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 285:74] + node _T_165 = eq(_T_164, UInt<1>("h00")) @[axi4_to_ahb.scala 285:43] + node _T_166 = bits(_T_165, 0, 0) @[Bitwise.scala 72:15] + node _T_167 = mux(_T_166, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_168 = and(UInt<2>("h02"), _T_167) @[axi4_to_ahb.scala 285:32] + io.ahb_htrans <= _T_168 @[axi4_to_ahb.scala 285:21] + node _T_169 = and(master_valid, master_ready) @[axi4_to_ahb.scala 286:37] + node _T_170 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 286:65] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 286:72] + node _T_172 = and(_T_169, _T_171) @[axi4_to_ahb.scala 286:52] + slvbuf_wr_en <= _T_172 @[axi4_to_ahb.scala 286:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_159 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] - when _T_159 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 282:20] - node _T_160 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 283:51] - node _T_161 = neq(_T_160, UInt<1>("h00")) @[axi4_to_ahb.scala 283:58] - node _T_162 = and(ahb_hready_q, _T_161) @[axi4_to_ahb.scala 283:36] - node _T_163 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 283:72] - node _T_164 = and(_T_162, _T_163) @[axi4_to_ahb.scala 283:70] - buf_state_en <= _T_164 @[axi4_to_ahb.scala 283:20] - slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 284:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 285:20] - node _T_165 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 286:35] - buf_cmd_byte_ptr <= _T_165 @[axi4_to_ahb.scala 286:24] - node _T_166 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 287:47] - node _T_167 = bits(_T_166, 0, 0) @[Bitwise.scala 72:15] - node _T_168 = mux(_T_167, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_169 = and(UInt<2>("h02"), _T_168) @[axi4_to_ahb.scala 287:37] - io.ahb_htrans <= _T_169 @[axi4_to_ahb.scala 287:21] + node _T_173 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] + when _T_173 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 290:20] + node _T_174 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 291:51] + node _T_175 = neq(_T_174, UInt<1>("h00")) @[axi4_to_ahb.scala 291:58] + node _T_176 = and(ahb_hready_q, _T_175) @[axi4_to_ahb.scala 291:36] + node _T_177 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 291:72] + node _T_178 = and(_T_176, _T_177) @[axi4_to_ahb.scala 291:70] + buf_state_en <= _T_178 @[axi4_to_ahb.scala 291:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 292:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 293:20] + node _T_179 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 294:35] + buf_cmd_byte_ptr <= _T_179 @[axi4_to_ahb.scala 294:24] + node _T_180 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 295:47] + node _T_181 = bits(_T_180, 0, 0) @[Bitwise.scala 72:15] + node _T_182 = mux(_T_181, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_183 = and(UInt<2>("h02"), _T_182) @[axi4_to_ahb.scala 295:37] + io.ahb_htrans <= _T_183 @[axi4_to_ahb.scala 295:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_170 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] - when _T_170 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 291:20] - node _T_171 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 292:37] - buf_state_en <= _T_171 @[axi4_to_ahb.scala 292:20] - buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 293:22] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 294:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 295:23] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 296:20] + node _T_184 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] + when _T_184 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 299:20] + node _T_185 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 300:37] + buf_state_en <= _T_185 @[axi4_to_ahb.scala 300:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 301:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 302:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 303:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 304:20] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_172 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] - when _T_172 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 300:20] - node _T_173 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 301:33] - node _T_174 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 301:63] - node _T_175 = neq(_T_174, UInt<1>("h00")) @[axi4_to_ahb.scala 301:70] - node _T_176 = and(_T_173, _T_175) @[axi4_to_ahb.scala 301:48] - trxn_done <= _T_176 @[axi4_to_ahb.scala 301:17] - buf_state_en <= trxn_done @[axi4_to_ahb.scala 302:20] - buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 303:27] - slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 304:20] - node _T_177 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 305:47] - node _T_178 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 305:85] - node _T_179 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 305:103] - node _T_180 = add(_T_178, UInt<1>("h01")) @[axi4_to_ahb.scala 176:52] - node _T_181 = tail(_T_180, 1) @[axi4_to_ahb.scala 176:52] - node _T_182 = mux(UInt<1>("h01"), _T_181, _T_178) @[axi4_to_ahb.scala 176:24] - node _T_183 = bits(_T_179, 0, 0) @[axi4_to_ahb.scala 177:44] - node _T_184 = geq(UInt<1>("h00"), _T_182) @[axi4_to_ahb.scala 177:62] - node _T_185 = and(_T_183, _T_184) @[axi4_to_ahb.scala 177:48] - node _T_186 = bits(_T_179, 1, 1) @[axi4_to_ahb.scala 177:44] - node _T_187 = geq(UInt<1>("h01"), _T_182) @[axi4_to_ahb.scala 177:62] - node _T_188 = and(_T_186, _T_187) @[axi4_to_ahb.scala 177:48] - node _T_189 = bits(_T_179, 2, 2) @[axi4_to_ahb.scala 177:44] - node _T_190 = geq(UInt<2>("h02"), _T_182) @[axi4_to_ahb.scala 177:62] - node _T_191 = and(_T_189, _T_190) @[axi4_to_ahb.scala 177:48] - node _T_192 = bits(_T_179, 3, 3) @[axi4_to_ahb.scala 177:44] - node _T_193 = geq(UInt<2>("h03"), _T_182) @[axi4_to_ahb.scala 177:62] - node _T_194 = and(_T_192, _T_193) @[axi4_to_ahb.scala 177:48] - node _T_195 = bits(_T_179, 4, 4) @[axi4_to_ahb.scala 177:44] - node _T_196 = geq(UInt<3>("h04"), _T_182) @[axi4_to_ahb.scala 177:62] - node _T_197 = and(_T_195, _T_196) @[axi4_to_ahb.scala 177:48] - node _T_198 = bits(_T_179, 5, 5) @[axi4_to_ahb.scala 177:44] - node _T_199 = geq(UInt<3>("h05"), _T_182) @[axi4_to_ahb.scala 177:62] - node _T_200 = and(_T_198, _T_199) @[axi4_to_ahb.scala 177:48] - node _T_201 = bits(_T_179, 6, 6) @[axi4_to_ahb.scala 177:44] - node _T_202 = geq(UInt<3>("h06"), _T_182) @[axi4_to_ahb.scala 177:62] - node _T_203 = and(_T_201, _T_202) @[axi4_to_ahb.scala 177:48] - node _T_204 = bits(_T_179, 7, 7) @[axi4_to_ahb.scala 177:44] - node _T_205 = geq(UInt<3>("h07"), _T_182) @[axi4_to_ahb.scala 177:62] - node _T_206 = and(_T_204, _T_205) @[axi4_to_ahb.scala 177:48] - node _T_207 = mux(_T_206, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_208 = mux(_T_203, UInt<3>("h06"), _T_207) @[Mux.scala 98:16] - node _T_209 = mux(_T_200, UInt<3>("h05"), _T_208) @[Mux.scala 98:16] - node _T_210 = mux(_T_197, UInt<3>("h04"), _T_209) @[Mux.scala 98:16] - node _T_211 = mux(_T_194, UInt<2>("h03"), _T_210) @[Mux.scala 98:16] - node _T_212 = mux(_T_191, UInt<2>("h02"), _T_211) @[Mux.scala 98:16] - node _T_213 = mux(_T_188, UInt<1>("h01"), _T_212) @[Mux.scala 98:16] - node _T_214 = mux(_T_185, UInt<1>("h00"), _T_213) @[Mux.scala 98:16] - node _T_215 = mux(_T_177, _T_214, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 305:30] - buf_cmd_byte_ptr <= _T_215 @[axi4_to_ahb.scala 305:24] - node _T_216 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 306:65] - node _T_217 = or(buf_aligned, _T_216) @[axi4_to_ahb.scala 306:44] - node _T_218 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 306:127] - node _T_219 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 306:145] - node _T_220 = add(_T_218, UInt<1>("h01")) @[axi4_to_ahb.scala 176:52] - node _T_221 = tail(_T_220, 1) @[axi4_to_ahb.scala 176:52] - node _T_222 = mux(UInt<1>("h01"), _T_221, _T_218) @[axi4_to_ahb.scala 176:24] - node _T_223 = bits(_T_219, 0, 0) @[axi4_to_ahb.scala 177:44] - node _T_224 = geq(UInt<1>("h00"), _T_222) @[axi4_to_ahb.scala 177:62] - node _T_225 = and(_T_223, _T_224) @[axi4_to_ahb.scala 177:48] - node _T_226 = bits(_T_219, 1, 1) @[axi4_to_ahb.scala 177:44] - node _T_227 = geq(UInt<1>("h01"), _T_222) @[axi4_to_ahb.scala 177:62] - node _T_228 = and(_T_226, _T_227) @[axi4_to_ahb.scala 177:48] - node _T_229 = bits(_T_219, 2, 2) @[axi4_to_ahb.scala 177:44] - node _T_230 = geq(UInt<2>("h02"), _T_222) @[axi4_to_ahb.scala 177:62] - node _T_231 = and(_T_229, _T_230) @[axi4_to_ahb.scala 177:48] - node _T_232 = bits(_T_219, 3, 3) @[axi4_to_ahb.scala 177:44] - node _T_233 = geq(UInt<2>("h03"), _T_222) @[axi4_to_ahb.scala 177:62] - node _T_234 = and(_T_232, _T_233) @[axi4_to_ahb.scala 177:48] - node _T_235 = bits(_T_219, 4, 4) @[axi4_to_ahb.scala 177:44] - node _T_236 = geq(UInt<3>("h04"), _T_222) @[axi4_to_ahb.scala 177:62] - node _T_237 = and(_T_235, _T_236) @[axi4_to_ahb.scala 177:48] - node _T_238 = bits(_T_219, 5, 5) @[axi4_to_ahb.scala 177:44] - node _T_239 = geq(UInt<3>("h05"), _T_222) @[axi4_to_ahb.scala 177:62] - node _T_240 = and(_T_238, _T_239) @[axi4_to_ahb.scala 177:48] - node _T_241 = bits(_T_219, 6, 6) @[axi4_to_ahb.scala 177:44] - node _T_242 = geq(UInt<3>("h06"), _T_222) @[axi4_to_ahb.scala 177:62] - node _T_243 = and(_T_241, _T_242) @[axi4_to_ahb.scala 177:48] - node _T_244 = bits(_T_219, 7, 7) @[axi4_to_ahb.scala 177:44] - node _T_245 = geq(UInt<3>("h07"), _T_222) @[axi4_to_ahb.scala 177:62] - node _T_246 = and(_T_244, _T_245) @[axi4_to_ahb.scala 177:48] - node _T_247 = mux(_T_246, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_248 = mux(_T_243, UInt<3>("h06"), _T_247) @[Mux.scala 98:16] - node _T_249 = mux(_T_240, UInt<3>("h05"), _T_248) @[Mux.scala 98:16] - node _T_250 = mux(_T_237, UInt<3>("h04"), _T_249) @[Mux.scala 98:16] - node _T_251 = mux(_T_234, UInt<2>("h03"), _T_250) @[Mux.scala 98:16] - node _T_252 = mux(_T_231, UInt<2>("h02"), _T_251) @[Mux.scala 98:16] - node _T_253 = mux(_T_228, UInt<1>("h01"), _T_252) @[Mux.scala 98:16] - node _T_254 = mux(_T_225, UInt<1>("h00"), _T_253) @[Mux.scala 98:16] - node _T_255 = dshr(buf_byteen, _T_254) @[axi4_to_ahb.scala 306:92] - node _T_256 = bits(_T_255, 0, 0) @[axi4_to_ahb.scala 306:92] - node _T_257 = eq(_T_256, UInt<1>("h00")) @[axi4_to_ahb.scala 306:163] - node _T_258 = or(_T_217, _T_257) @[axi4_to_ahb.scala 306:79] - node _T_259 = and(trxn_done, _T_258) @[axi4_to_ahb.scala 306:29] - cmd_done <= _T_259 @[axi4_to_ahb.scala 306:16] - node _T_260 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 307:43] - node _T_261 = eq(_T_260, UInt<1>("h00")) @[axi4_to_ahb.scala 307:32] - node _T_262 = bits(_T_261, 0, 0) @[Bitwise.scala 72:15] - node _T_263 = mux(_T_262, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_264 = and(_T_263, UInt<2>("h02")) @[axi4_to_ahb.scala 307:57] - io.ahb_htrans <= _T_264 @[axi4_to_ahb.scala 307:21] + node _T_186 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] + when _T_186 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 308:20] + node _T_187 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 309:33] + node _T_188 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 309:63] + node _T_189 = neq(_T_188, UInt<1>("h00")) @[axi4_to_ahb.scala 309:70] + node _T_190 = and(_T_187, _T_189) @[axi4_to_ahb.scala 309:48] + trxn_done <= _T_190 @[axi4_to_ahb.scala 309:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 310:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 311:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 312:20] + node _T_191 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 313:47] + node _T_192 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 313:85] + node _T_193 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 313:103] + node _T_194 = add(_T_192, UInt<1>("h01")) @[axi4_to_ahb.scala 184:52] + node _T_195 = tail(_T_194, 1) @[axi4_to_ahb.scala 184:52] + node _T_196 = mux(UInt<1>("h01"), _T_195, _T_192) @[axi4_to_ahb.scala 184:24] + node _T_197 = bits(_T_193, 0, 0) @[axi4_to_ahb.scala 185:44] + node _T_198 = geq(UInt<1>("h00"), _T_196) @[axi4_to_ahb.scala 185:62] + node _T_199 = and(_T_197, _T_198) @[axi4_to_ahb.scala 185:48] + node _T_200 = bits(_T_193, 1, 1) @[axi4_to_ahb.scala 185:44] + node _T_201 = geq(UInt<1>("h01"), _T_196) @[axi4_to_ahb.scala 185:62] + node _T_202 = and(_T_200, _T_201) @[axi4_to_ahb.scala 185:48] + node _T_203 = bits(_T_193, 2, 2) @[axi4_to_ahb.scala 185:44] + node _T_204 = geq(UInt<2>("h02"), _T_196) @[axi4_to_ahb.scala 185:62] + node _T_205 = and(_T_203, _T_204) @[axi4_to_ahb.scala 185:48] + node _T_206 = bits(_T_193, 3, 3) @[axi4_to_ahb.scala 185:44] + node _T_207 = geq(UInt<2>("h03"), _T_196) @[axi4_to_ahb.scala 185:62] + node _T_208 = and(_T_206, _T_207) @[axi4_to_ahb.scala 185:48] + node _T_209 = bits(_T_193, 4, 4) @[axi4_to_ahb.scala 185:44] + node _T_210 = geq(UInt<3>("h04"), _T_196) @[axi4_to_ahb.scala 185:62] + node _T_211 = and(_T_209, _T_210) @[axi4_to_ahb.scala 185:48] + node _T_212 = bits(_T_193, 5, 5) @[axi4_to_ahb.scala 185:44] + node _T_213 = geq(UInt<3>("h05"), _T_196) @[axi4_to_ahb.scala 185:62] + node _T_214 = and(_T_212, _T_213) @[axi4_to_ahb.scala 185:48] + node _T_215 = bits(_T_193, 6, 6) @[axi4_to_ahb.scala 185:44] + node _T_216 = geq(UInt<3>("h06"), _T_196) @[axi4_to_ahb.scala 185:62] + node _T_217 = and(_T_215, _T_216) @[axi4_to_ahb.scala 185:48] + node _T_218 = bits(_T_193, 7, 7) @[axi4_to_ahb.scala 185:44] + node _T_219 = geq(UInt<3>("h07"), _T_196) @[axi4_to_ahb.scala 185:62] + node _T_220 = and(_T_218, _T_219) @[axi4_to_ahb.scala 185:48] + node _T_221 = mux(_T_220, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_222 = mux(_T_217, UInt<3>("h06"), _T_221) @[Mux.scala 98:16] + node _T_223 = mux(_T_214, UInt<3>("h05"), _T_222) @[Mux.scala 98:16] + node _T_224 = mux(_T_211, UInt<3>("h04"), _T_223) @[Mux.scala 98:16] + node _T_225 = mux(_T_208, UInt<2>("h03"), _T_224) @[Mux.scala 98:16] + node _T_226 = mux(_T_205, UInt<2>("h02"), _T_225) @[Mux.scala 98:16] + node _T_227 = mux(_T_202, UInt<1>("h01"), _T_226) @[Mux.scala 98:16] + node _T_228 = mux(_T_199, UInt<1>("h00"), _T_227) @[Mux.scala 98:16] + node _T_229 = mux(_T_191, _T_228, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 313:30] + buf_cmd_byte_ptr <= _T_229 @[axi4_to_ahb.scala 313:24] + node _T_230 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 314:65] + node _T_231 = or(buf_aligned, _T_230) @[axi4_to_ahb.scala 314:44] + node _T_232 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 314:127] + node _T_233 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 314:145] + node _T_234 = add(_T_232, UInt<1>("h01")) @[axi4_to_ahb.scala 184:52] + node _T_235 = tail(_T_234, 1) @[axi4_to_ahb.scala 184:52] + node _T_236 = mux(UInt<1>("h01"), _T_235, _T_232) @[axi4_to_ahb.scala 184:24] + node _T_237 = bits(_T_233, 0, 0) @[axi4_to_ahb.scala 185:44] + node _T_238 = geq(UInt<1>("h00"), _T_236) @[axi4_to_ahb.scala 185:62] + node _T_239 = and(_T_237, _T_238) @[axi4_to_ahb.scala 185:48] + node _T_240 = bits(_T_233, 1, 1) @[axi4_to_ahb.scala 185:44] + node _T_241 = geq(UInt<1>("h01"), _T_236) @[axi4_to_ahb.scala 185:62] + node _T_242 = and(_T_240, _T_241) @[axi4_to_ahb.scala 185:48] + node _T_243 = bits(_T_233, 2, 2) @[axi4_to_ahb.scala 185:44] + node _T_244 = geq(UInt<2>("h02"), _T_236) @[axi4_to_ahb.scala 185:62] + node _T_245 = and(_T_243, _T_244) @[axi4_to_ahb.scala 185:48] + node _T_246 = bits(_T_233, 3, 3) @[axi4_to_ahb.scala 185:44] + node _T_247 = geq(UInt<2>("h03"), _T_236) @[axi4_to_ahb.scala 185:62] + node _T_248 = and(_T_246, _T_247) @[axi4_to_ahb.scala 185:48] + node _T_249 = bits(_T_233, 4, 4) @[axi4_to_ahb.scala 185:44] + node _T_250 = geq(UInt<3>("h04"), _T_236) @[axi4_to_ahb.scala 185:62] + node _T_251 = and(_T_249, _T_250) @[axi4_to_ahb.scala 185:48] + node _T_252 = bits(_T_233, 5, 5) @[axi4_to_ahb.scala 185:44] + node _T_253 = geq(UInt<3>("h05"), _T_236) @[axi4_to_ahb.scala 185:62] + node _T_254 = and(_T_252, _T_253) @[axi4_to_ahb.scala 185:48] + node _T_255 = bits(_T_233, 6, 6) @[axi4_to_ahb.scala 185:44] + node _T_256 = geq(UInt<3>("h06"), _T_236) @[axi4_to_ahb.scala 185:62] + node _T_257 = and(_T_255, _T_256) @[axi4_to_ahb.scala 185:48] + node _T_258 = bits(_T_233, 7, 7) @[axi4_to_ahb.scala 185:44] + node _T_259 = geq(UInt<3>("h07"), _T_236) @[axi4_to_ahb.scala 185:62] + node _T_260 = and(_T_258, _T_259) @[axi4_to_ahb.scala 185:48] + node _T_261 = mux(_T_260, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_262 = mux(_T_257, UInt<3>("h06"), _T_261) @[Mux.scala 98:16] + node _T_263 = mux(_T_254, UInt<3>("h05"), _T_262) @[Mux.scala 98:16] + node _T_264 = mux(_T_251, UInt<3>("h04"), _T_263) @[Mux.scala 98:16] + node _T_265 = mux(_T_248, UInt<2>("h03"), _T_264) @[Mux.scala 98:16] + node _T_266 = mux(_T_245, UInt<2>("h02"), _T_265) @[Mux.scala 98:16] + node _T_267 = mux(_T_242, UInt<1>("h01"), _T_266) @[Mux.scala 98:16] + node _T_268 = mux(_T_239, UInt<1>("h00"), _T_267) @[Mux.scala 98:16] + node _T_269 = dshr(buf_byteen, _T_268) @[axi4_to_ahb.scala 314:92] + node _T_270 = bits(_T_269, 0, 0) @[axi4_to_ahb.scala 314:92] + node _T_271 = eq(_T_270, UInt<1>("h00")) @[axi4_to_ahb.scala 314:163] + node _T_272 = or(_T_231, _T_271) @[axi4_to_ahb.scala 314:79] + node _T_273 = and(trxn_done, _T_272) @[axi4_to_ahb.scala 314:29] + cmd_done <= _T_273 @[axi4_to_ahb.scala 314:16] + node _T_274 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 315:43] + node _T_275 = eq(_T_274, UInt<1>("h00")) @[axi4_to_ahb.scala 315:32] + node _T_276 = bits(_T_275, 0, 0) @[Bitwise.scala 72:15] + node _T_277 = mux(_T_276, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_278 = and(_T_277, UInt<2>("h02")) @[axi4_to_ahb.scala 315:57] + io.ahb_htrans <= _T_278 @[axi4_to_ahb.scala 315:21] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_265 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] - when _T_265 : @[Conditional.scala 39:67] - node _T_266 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 311:34] - node _T_267 = or(_T_266, ahb_hresp_q) @[axi4_to_ahb.scala 311:50] - buf_state_en <= _T_267 @[axi4_to_ahb.scala 311:20] - node _T_268 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 312:37] - node _T_269 = or(_T_268, ahb_hresp_q) @[axi4_to_ahb.scala 312:53] - node _T_270 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 312:70] - node _T_271 = and(_T_269, _T_270) @[axi4_to_ahb.scala 312:68] - node _T_272 = and(_T_271, slave_ready) @[axi4_to_ahb.scala 312:83] - node _T_273 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 313:42] - node _T_274 = or(ahb_hresp_q, _T_273) @[axi4_to_ahb.scala 313:40] - node _T_275 = bits(_T_274, 0, 0) @[axi4_to_ahb.scala 313:62] - node _T_276 = and(master_valid, _T_272) @[axi4_to_ahb.scala 313:90] - node _T_277 = bits(_T_276, 0, 0) @[axi4_to_ahb.scala 313:112] - node _T_278 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 313:131] - node _T_279 = eq(_T_278, UInt<1>("h01")) @[axi4_to_ahb.scala 313:138] - node _T_280 = mux(_T_279, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 313:119] - node _T_281 = mux(_T_277, _T_280, UInt<3>("h00")) @[axi4_to_ahb.scala 313:75] - node _T_282 = mux(_T_275, UInt<3>("h05"), _T_281) @[axi4_to_ahb.scala 313:26] - buf_nxtstate <= _T_282 @[axi4_to_ahb.scala 313:20] - slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 314:23] - slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 315:23] - node _T_283 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 316:34] - node _T_284 = eq(_T_283, UInt<1>("h01")) @[axi4_to_ahb.scala 316:41] - buf_write_in <= _T_284 @[axi4_to_ahb.scala 316:20] - node _T_285 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 317:50] - node _T_286 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 317:78] - node _T_287 = or(_T_285, _T_286) @[axi4_to_ahb.scala 317:62] - node _T_288 = and(buf_state_en, _T_287) @[axi4_to_ahb.scala 317:33] - buf_wr_en <= _T_288 @[axi4_to_ahb.scala 317:17] - buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 318:22] - node _T_289 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 319:63] - node _T_290 = neq(_T_289, UInt<1>("h00")) @[axi4_to_ahb.scala 319:70] - node _T_291 = and(ahb_hready_q, _T_290) @[axi4_to_ahb.scala 319:48] - node _T_292 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 319:104] - node _T_293 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 319:166] - node _T_294 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 319:184] - node _T_295 = add(_T_293, UInt<1>("h01")) @[axi4_to_ahb.scala 176:52] - node _T_296 = tail(_T_295, 1) @[axi4_to_ahb.scala 176:52] - node _T_297 = mux(UInt<1>("h01"), _T_296, _T_293) @[axi4_to_ahb.scala 176:24] - node _T_298 = bits(_T_294, 0, 0) @[axi4_to_ahb.scala 177:44] - node _T_299 = geq(UInt<1>("h00"), _T_297) @[axi4_to_ahb.scala 177:62] - node _T_300 = and(_T_298, _T_299) @[axi4_to_ahb.scala 177:48] - node _T_301 = bits(_T_294, 1, 1) @[axi4_to_ahb.scala 177:44] - node _T_302 = geq(UInt<1>("h01"), _T_297) @[axi4_to_ahb.scala 177:62] - node _T_303 = and(_T_301, _T_302) @[axi4_to_ahb.scala 177:48] - node _T_304 = bits(_T_294, 2, 2) @[axi4_to_ahb.scala 177:44] - node _T_305 = geq(UInt<2>("h02"), _T_297) @[axi4_to_ahb.scala 177:62] - node _T_306 = and(_T_304, _T_305) @[axi4_to_ahb.scala 177:48] - node _T_307 = bits(_T_294, 3, 3) @[axi4_to_ahb.scala 177:44] - node _T_308 = geq(UInt<2>("h03"), _T_297) @[axi4_to_ahb.scala 177:62] - node _T_309 = and(_T_307, _T_308) @[axi4_to_ahb.scala 177:48] - node _T_310 = bits(_T_294, 4, 4) @[axi4_to_ahb.scala 177:44] - node _T_311 = geq(UInt<3>("h04"), _T_297) @[axi4_to_ahb.scala 177:62] - node _T_312 = and(_T_310, _T_311) @[axi4_to_ahb.scala 177:48] - node _T_313 = bits(_T_294, 5, 5) @[axi4_to_ahb.scala 177:44] - node _T_314 = geq(UInt<3>("h05"), _T_297) @[axi4_to_ahb.scala 177:62] - node _T_315 = and(_T_313, _T_314) @[axi4_to_ahb.scala 177:48] - node _T_316 = bits(_T_294, 6, 6) @[axi4_to_ahb.scala 177:44] - node _T_317 = geq(UInt<3>("h06"), _T_297) @[axi4_to_ahb.scala 177:62] - node _T_318 = and(_T_316, _T_317) @[axi4_to_ahb.scala 177:48] - node _T_319 = bits(_T_294, 7, 7) @[axi4_to_ahb.scala 177:44] - node _T_320 = geq(UInt<3>("h07"), _T_297) @[axi4_to_ahb.scala 177:62] - node _T_321 = and(_T_319, _T_320) @[axi4_to_ahb.scala 177:48] - node _T_322 = mux(_T_321, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_323 = mux(_T_318, UInt<3>("h06"), _T_322) @[Mux.scala 98:16] - node _T_324 = mux(_T_315, UInt<3>("h05"), _T_323) @[Mux.scala 98:16] - node _T_325 = mux(_T_312, UInt<3>("h04"), _T_324) @[Mux.scala 98:16] - node _T_326 = mux(_T_309, UInt<2>("h03"), _T_325) @[Mux.scala 98:16] - node _T_327 = mux(_T_306, UInt<2>("h02"), _T_326) @[Mux.scala 98:16] - node _T_328 = mux(_T_303, UInt<1>("h01"), _T_327) @[Mux.scala 98:16] - node _T_329 = mux(_T_300, UInt<1>("h00"), _T_328) @[Mux.scala 98:16] - node _T_330 = dshr(buf_byteen, _T_329) @[axi4_to_ahb.scala 319:131] - node _T_331 = bits(_T_330, 0, 0) @[axi4_to_ahb.scala 319:131] - node _T_332 = eq(_T_331, UInt<1>("h00")) @[axi4_to_ahb.scala 319:202] - node _T_333 = or(_T_292, _T_332) @[axi4_to_ahb.scala 319:118] - node _T_334 = and(_T_291, _T_333) @[axi4_to_ahb.scala 319:82] - node _T_335 = or(ahb_hresp_q, _T_334) @[axi4_to_ahb.scala 319:32] - cmd_done <= _T_335 @[axi4_to_ahb.scala 319:16] - node _T_336 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 320:33] - node _T_337 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 320:64] - node _T_338 = and(_T_336, _T_337) @[axi4_to_ahb.scala 320:48] - bypass_en <= _T_338 @[axi4_to_ahb.scala 320:17] - node _T_339 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 321:44] - node _T_340 = eq(_T_339, UInt<1>("h00")) @[axi4_to_ahb.scala 321:33] - node _T_341 = or(_T_340, bypass_en) @[axi4_to_ahb.scala 321:57] - node _T_342 = bits(_T_341, 0, 0) @[Bitwise.scala 72:15] - node _T_343 = mux(_T_342, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_344 = and(_T_343, UInt<2>("h02")) @[axi4_to_ahb.scala 321:71] - io.ahb_htrans <= _T_344 @[axi4_to_ahb.scala 321:21] - node _T_345 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 322:55] - node _T_346 = and(buf_state_en, _T_345) @[axi4_to_ahb.scala 322:39] - slave_valid_pre <= _T_346 @[axi4_to_ahb.scala 322:23] - node _T_347 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 323:33] - node _T_348 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 323:63] - node _T_349 = neq(_T_348, UInt<1>("h00")) @[axi4_to_ahb.scala 323:70] - node _T_350 = and(_T_347, _T_349) @[axi4_to_ahb.scala 323:48] - trxn_done <= _T_350 @[axi4_to_ahb.scala 323:17] - node _T_351 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 324:40] - buf_cmd_byte_ptr_en <= _T_351 @[axi4_to_ahb.scala 324:27] - node _T_352 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_353 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 327:85] - node _T_354 = add(_T_352, UInt<1>("h01")) @[axi4_to_ahb.scala 176:52] - node _T_355 = tail(_T_354, 1) @[axi4_to_ahb.scala 176:52] - node _T_356 = mux(UInt<1>("h00"), _T_355, _T_352) @[axi4_to_ahb.scala 176:24] - node _T_357 = bits(_T_353, 0, 0) @[axi4_to_ahb.scala 177:44] - node _T_358 = geq(UInt<1>("h00"), _T_356) @[axi4_to_ahb.scala 177:62] - node _T_359 = and(_T_357, _T_358) @[axi4_to_ahb.scala 177:48] - node _T_360 = bits(_T_353, 1, 1) @[axi4_to_ahb.scala 177:44] - node _T_361 = geq(UInt<1>("h01"), _T_356) @[axi4_to_ahb.scala 177:62] - node _T_362 = and(_T_360, _T_361) @[axi4_to_ahb.scala 177:48] - node _T_363 = bits(_T_353, 2, 2) @[axi4_to_ahb.scala 177:44] - node _T_364 = geq(UInt<2>("h02"), _T_356) @[axi4_to_ahb.scala 177:62] - node _T_365 = and(_T_363, _T_364) @[axi4_to_ahb.scala 177:48] - node _T_366 = bits(_T_353, 3, 3) @[axi4_to_ahb.scala 177:44] - node _T_367 = geq(UInt<2>("h03"), _T_356) @[axi4_to_ahb.scala 177:62] - node _T_368 = and(_T_366, _T_367) @[axi4_to_ahb.scala 177:48] - node _T_369 = bits(_T_353, 4, 4) @[axi4_to_ahb.scala 177:44] - node _T_370 = geq(UInt<3>("h04"), _T_356) @[axi4_to_ahb.scala 177:62] - node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 177:48] - node _T_372 = bits(_T_353, 5, 5) @[axi4_to_ahb.scala 177:44] - node _T_373 = geq(UInt<3>("h05"), _T_356) @[axi4_to_ahb.scala 177:62] - node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 177:48] - node _T_375 = bits(_T_353, 6, 6) @[axi4_to_ahb.scala 177:44] - node _T_376 = geq(UInt<3>("h06"), _T_356) @[axi4_to_ahb.scala 177:62] - node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 177:48] - node _T_378 = bits(_T_353, 7, 7) @[axi4_to_ahb.scala 177:44] - node _T_379 = geq(UInt<3>("h07"), _T_356) @[axi4_to_ahb.scala 177:62] - node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 177:48] - node _T_381 = mux(_T_380, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_382 = mux(_T_377, UInt<3>("h06"), _T_381) @[Mux.scala 98:16] - node _T_383 = mux(_T_374, UInt<3>("h05"), _T_382) @[Mux.scala 98:16] - node _T_384 = mux(_T_371, UInt<3>("h04"), _T_383) @[Mux.scala 98:16] - node _T_385 = mux(_T_368, UInt<2>("h03"), _T_384) @[Mux.scala 98:16] - node _T_386 = mux(_T_365, UInt<2>("h02"), _T_385) @[Mux.scala 98:16] - node _T_387 = mux(_T_362, UInt<1>("h01"), _T_386) @[Mux.scala 98:16] - node _T_388 = mux(_T_359, UInt<1>("h00"), _T_387) @[Mux.scala 98:16] - node _T_389 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 327:151] - node _T_390 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 327:169] - node _T_391 = add(_T_389, UInt<1>("h01")) @[axi4_to_ahb.scala 176:52] - node _T_392 = tail(_T_391, 1) @[axi4_to_ahb.scala 176:52] - node _T_393 = mux(UInt<1>("h01"), _T_392, _T_389) @[axi4_to_ahb.scala 176:24] - node _T_394 = bits(_T_390, 0, 0) @[axi4_to_ahb.scala 177:44] - node _T_395 = geq(UInt<1>("h00"), _T_393) @[axi4_to_ahb.scala 177:62] - node _T_396 = and(_T_394, _T_395) @[axi4_to_ahb.scala 177:48] - node _T_397 = bits(_T_390, 1, 1) @[axi4_to_ahb.scala 177:44] - node _T_398 = geq(UInt<1>("h01"), _T_393) @[axi4_to_ahb.scala 177:62] - node _T_399 = and(_T_397, _T_398) @[axi4_to_ahb.scala 177:48] - node _T_400 = bits(_T_390, 2, 2) @[axi4_to_ahb.scala 177:44] - node _T_401 = geq(UInt<2>("h02"), _T_393) @[axi4_to_ahb.scala 177:62] - node _T_402 = and(_T_400, _T_401) @[axi4_to_ahb.scala 177:48] - node _T_403 = bits(_T_390, 3, 3) @[axi4_to_ahb.scala 177:44] - node _T_404 = geq(UInt<2>("h03"), _T_393) @[axi4_to_ahb.scala 177:62] - node _T_405 = and(_T_403, _T_404) @[axi4_to_ahb.scala 177:48] - node _T_406 = bits(_T_390, 4, 4) @[axi4_to_ahb.scala 177:44] - node _T_407 = geq(UInt<3>("h04"), _T_393) @[axi4_to_ahb.scala 177:62] - node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 177:48] - node _T_409 = bits(_T_390, 5, 5) @[axi4_to_ahb.scala 177:44] - node _T_410 = geq(UInt<3>("h05"), _T_393) @[axi4_to_ahb.scala 177:62] - node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 177:48] - node _T_412 = bits(_T_390, 6, 6) @[axi4_to_ahb.scala 177:44] - node _T_413 = geq(UInt<3>("h06"), _T_393) @[axi4_to_ahb.scala 177:62] - node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 177:48] - node _T_415 = bits(_T_390, 7, 7) @[axi4_to_ahb.scala 177:44] - node _T_416 = geq(UInt<3>("h07"), _T_393) @[axi4_to_ahb.scala 177:62] - node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 177:48] - node _T_418 = mux(_T_417, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_419 = mux(_T_414, UInt<3>("h06"), _T_418) @[Mux.scala 98:16] - node _T_420 = mux(_T_411, UInt<3>("h05"), _T_419) @[Mux.scala 98:16] - node _T_421 = mux(_T_408, UInt<3>("h04"), _T_420) @[Mux.scala 98:16] - node _T_422 = mux(_T_405, UInt<2>("h03"), _T_421) @[Mux.scala 98:16] - node _T_423 = mux(_T_402, UInt<2>("h02"), _T_422) @[Mux.scala 98:16] - node _T_424 = mux(_T_399, UInt<1>("h01"), _T_423) @[Mux.scala 98:16] - node _T_425 = mux(_T_396, UInt<1>("h00"), _T_424) @[Mux.scala 98:16] - node _T_426 = mux(trxn_done, _T_425, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 327:106] - node _T_427 = mux(bypass_en, _T_388, _T_426) @[axi4_to_ahb.scala 327:30] - buf_cmd_byte_ptr <= _T_427 @[axi4_to_ahb.scala 327:24] + node _T_279 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] + when _T_279 : @[Conditional.scala 39:67] + node _T_280 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 319:34] + node _T_281 = or(_T_280, ahb_hresp_q) @[axi4_to_ahb.scala 319:50] + buf_state_en <= _T_281 @[axi4_to_ahb.scala 319:20] + node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 320:35] + node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 320:51] + node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 320:68] + node _T_285 = and(_T_283, _T_284) @[axi4_to_ahb.scala 320:66] + node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 320:81] + master_ready <= _T_286 @[axi4_to_ahb.scala 320:20] + node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 321:42] + node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 321:40] + node _T_289 = bits(_T_288, 0, 0) @[axi4_to_ahb.scala 321:62] + node _T_290 = and(master_valid, master_ready) @[axi4_to_ahb.scala 321:90] + node _T_291 = bits(_T_290, 0, 0) @[axi4_to_ahb.scala 321:112] + node _T_292 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 321:131] + node _T_293 = eq(_T_292, UInt<1>("h01")) @[axi4_to_ahb.scala 321:138] + node _T_294 = mux(_T_293, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 321:119] + node _T_295 = mux(_T_291, _T_294, UInt<3>("h00")) @[axi4_to_ahb.scala 321:75] + node _T_296 = mux(_T_289, UInt<3>("h05"), _T_295) @[axi4_to_ahb.scala 321:26] + buf_nxtstate <= _T_296 @[axi4_to_ahb.scala 321:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 322:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 323:23] + node _T_297 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 324:34] + node _T_298 = eq(_T_297, UInt<1>("h01")) @[axi4_to_ahb.scala 324:41] + buf_write_in <= _T_298 @[axi4_to_ahb.scala 324:20] + node _T_299 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 325:50] + node _T_300 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 325:78] + node _T_301 = or(_T_299, _T_300) @[axi4_to_ahb.scala 325:62] + node _T_302 = and(buf_state_en, _T_301) @[axi4_to_ahb.scala 325:33] + buf_wr_en <= _T_302 @[axi4_to_ahb.scala 325:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 326:22] + node _T_303 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 327:63] + node _T_304 = neq(_T_303, UInt<1>("h00")) @[axi4_to_ahb.scala 327:70] + node _T_305 = and(ahb_hready_q, _T_304) @[axi4_to_ahb.scala 327:48] + node _T_306 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 327:104] + node _T_307 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 327:166] + node _T_308 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 327:184] + node _T_309 = add(_T_307, UInt<1>("h01")) @[axi4_to_ahb.scala 184:52] + node _T_310 = tail(_T_309, 1) @[axi4_to_ahb.scala 184:52] + node _T_311 = mux(UInt<1>("h01"), _T_310, _T_307) @[axi4_to_ahb.scala 184:24] + node _T_312 = bits(_T_308, 0, 0) @[axi4_to_ahb.scala 185:44] + node _T_313 = geq(UInt<1>("h00"), _T_311) @[axi4_to_ahb.scala 185:62] + node _T_314 = and(_T_312, _T_313) @[axi4_to_ahb.scala 185:48] + node _T_315 = bits(_T_308, 1, 1) @[axi4_to_ahb.scala 185:44] + node _T_316 = geq(UInt<1>("h01"), _T_311) @[axi4_to_ahb.scala 185:62] + node _T_317 = and(_T_315, _T_316) @[axi4_to_ahb.scala 185:48] + node _T_318 = bits(_T_308, 2, 2) @[axi4_to_ahb.scala 185:44] + node _T_319 = geq(UInt<2>("h02"), _T_311) @[axi4_to_ahb.scala 185:62] + node _T_320 = and(_T_318, _T_319) @[axi4_to_ahb.scala 185:48] + node _T_321 = bits(_T_308, 3, 3) @[axi4_to_ahb.scala 185:44] + node _T_322 = geq(UInt<2>("h03"), _T_311) @[axi4_to_ahb.scala 185:62] + node _T_323 = and(_T_321, _T_322) @[axi4_to_ahb.scala 185:48] + node _T_324 = bits(_T_308, 4, 4) @[axi4_to_ahb.scala 185:44] + node _T_325 = geq(UInt<3>("h04"), _T_311) @[axi4_to_ahb.scala 185:62] + node _T_326 = and(_T_324, _T_325) @[axi4_to_ahb.scala 185:48] + node _T_327 = bits(_T_308, 5, 5) @[axi4_to_ahb.scala 185:44] + node _T_328 = geq(UInt<3>("h05"), _T_311) @[axi4_to_ahb.scala 185:62] + node _T_329 = and(_T_327, _T_328) @[axi4_to_ahb.scala 185:48] + node _T_330 = bits(_T_308, 6, 6) @[axi4_to_ahb.scala 185:44] + node _T_331 = geq(UInt<3>("h06"), _T_311) @[axi4_to_ahb.scala 185:62] + node _T_332 = and(_T_330, _T_331) @[axi4_to_ahb.scala 185:48] + node _T_333 = bits(_T_308, 7, 7) @[axi4_to_ahb.scala 185:44] + node _T_334 = geq(UInt<3>("h07"), _T_311) @[axi4_to_ahb.scala 185:62] + node _T_335 = and(_T_333, _T_334) @[axi4_to_ahb.scala 185:48] + node _T_336 = mux(_T_335, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_337 = mux(_T_332, UInt<3>("h06"), _T_336) @[Mux.scala 98:16] + node _T_338 = mux(_T_329, UInt<3>("h05"), _T_337) @[Mux.scala 98:16] + node _T_339 = mux(_T_326, UInt<3>("h04"), _T_338) @[Mux.scala 98:16] + node _T_340 = mux(_T_323, UInt<2>("h03"), _T_339) @[Mux.scala 98:16] + node _T_341 = mux(_T_320, UInt<2>("h02"), _T_340) @[Mux.scala 98:16] + node _T_342 = mux(_T_317, UInt<1>("h01"), _T_341) @[Mux.scala 98:16] + node _T_343 = mux(_T_314, UInt<1>("h00"), _T_342) @[Mux.scala 98:16] + node _T_344 = dshr(buf_byteen, _T_343) @[axi4_to_ahb.scala 327:131] + node _T_345 = bits(_T_344, 0, 0) @[axi4_to_ahb.scala 327:131] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[axi4_to_ahb.scala 327:202] + node _T_347 = or(_T_306, _T_346) @[axi4_to_ahb.scala 327:118] + node _T_348 = and(_T_305, _T_347) @[axi4_to_ahb.scala 327:82] + node _T_349 = or(ahb_hresp_q, _T_348) @[axi4_to_ahb.scala 327:32] + cmd_done <= _T_349 @[axi4_to_ahb.scala 327:16] + node _T_350 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 328:33] + node _T_351 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 328:64] + node _T_352 = and(_T_350, _T_351) @[axi4_to_ahb.scala 328:48] + bypass_en <= _T_352 @[axi4_to_ahb.scala 328:17] + node _T_353 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 329:44] + node _T_354 = eq(_T_353, UInt<1>("h00")) @[axi4_to_ahb.scala 329:33] + node _T_355 = or(_T_354, bypass_en) @[axi4_to_ahb.scala 329:57] + node _T_356 = bits(_T_355, 0, 0) @[Bitwise.scala 72:15] + node _T_357 = mux(_T_356, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_358 = and(_T_357, UInt<2>("h02")) @[axi4_to_ahb.scala 329:71] + io.ahb_htrans <= _T_358 @[axi4_to_ahb.scala 329:21] + node _T_359 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 330:55] + node _T_360 = and(buf_state_en, _T_359) @[axi4_to_ahb.scala 330:39] + slave_valid_pre <= _T_360 @[axi4_to_ahb.scala 330:23] + node _T_361 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 331:33] + node _T_362 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 331:63] + node _T_363 = neq(_T_362, UInt<1>("h00")) @[axi4_to_ahb.scala 331:70] + node _T_364 = and(_T_361, _T_363) @[axi4_to_ahb.scala 331:48] + trxn_done <= _T_364 @[axi4_to_ahb.scala 331:17] + node _T_365 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 332:40] + buf_cmd_byte_ptr_en <= _T_365 @[axi4_to_ahb.scala 332:27] + node _T_366 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_367 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 335:85] + node _T_368 = add(_T_366, UInt<1>("h01")) @[axi4_to_ahb.scala 184:52] + node _T_369 = tail(_T_368, 1) @[axi4_to_ahb.scala 184:52] + node _T_370 = mux(UInt<1>("h00"), _T_369, _T_366) @[axi4_to_ahb.scala 184:24] + node _T_371 = bits(_T_367, 0, 0) @[axi4_to_ahb.scala 185:44] + node _T_372 = geq(UInt<1>("h00"), _T_370) @[axi4_to_ahb.scala 185:62] + node _T_373 = and(_T_371, _T_372) @[axi4_to_ahb.scala 185:48] + node _T_374 = bits(_T_367, 1, 1) @[axi4_to_ahb.scala 185:44] + node _T_375 = geq(UInt<1>("h01"), _T_370) @[axi4_to_ahb.scala 185:62] + node _T_376 = and(_T_374, _T_375) @[axi4_to_ahb.scala 185:48] + node _T_377 = bits(_T_367, 2, 2) @[axi4_to_ahb.scala 185:44] + node _T_378 = geq(UInt<2>("h02"), _T_370) @[axi4_to_ahb.scala 185:62] + node _T_379 = and(_T_377, _T_378) @[axi4_to_ahb.scala 185:48] + node _T_380 = bits(_T_367, 3, 3) @[axi4_to_ahb.scala 185:44] + node _T_381 = geq(UInt<2>("h03"), _T_370) @[axi4_to_ahb.scala 185:62] + node _T_382 = and(_T_380, _T_381) @[axi4_to_ahb.scala 185:48] + node _T_383 = bits(_T_367, 4, 4) @[axi4_to_ahb.scala 185:44] + node _T_384 = geq(UInt<3>("h04"), _T_370) @[axi4_to_ahb.scala 185:62] + node _T_385 = and(_T_383, _T_384) @[axi4_to_ahb.scala 185:48] + node _T_386 = bits(_T_367, 5, 5) @[axi4_to_ahb.scala 185:44] + node _T_387 = geq(UInt<3>("h05"), _T_370) @[axi4_to_ahb.scala 185:62] + node _T_388 = and(_T_386, _T_387) @[axi4_to_ahb.scala 185:48] + node _T_389 = bits(_T_367, 6, 6) @[axi4_to_ahb.scala 185:44] + node _T_390 = geq(UInt<3>("h06"), _T_370) @[axi4_to_ahb.scala 185:62] + node _T_391 = and(_T_389, _T_390) @[axi4_to_ahb.scala 185:48] + node _T_392 = bits(_T_367, 7, 7) @[axi4_to_ahb.scala 185:44] + node _T_393 = geq(UInt<3>("h07"), _T_370) @[axi4_to_ahb.scala 185:62] + node _T_394 = and(_T_392, _T_393) @[axi4_to_ahb.scala 185:48] + node _T_395 = mux(_T_394, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_396 = mux(_T_391, UInt<3>("h06"), _T_395) @[Mux.scala 98:16] + node _T_397 = mux(_T_388, UInt<3>("h05"), _T_396) @[Mux.scala 98:16] + node _T_398 = mux(_T_385, UInt<3>("h04"), _T_397) @[Mux.scala 98:16] + node _T_399 = mux(_T_382, UInt<2>("h03"), _T_398) @[Mux.scala 98:16] + node _T_400 = mux(_T_379, UInt<2>("h02"), _T_399) @[Mux.scala 98:16] + node _T_401 = mux(_T_376, UInt<1>("h01"), _T_400) @[Mux.scala 98:16] + node _T_402 = mux(_T_373, UInt<1>("h00"), _T_401) @[Mux.scala 98:16] + node _T_403 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 335:151] + node _T_404 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 335:169] + node _T_405 = add(_T_403, UInt<1>("h01")) @[axi4_to_ahb.scala 184:52] + node _T_406 = tail(_T_405, 1) @[axi4_to_ahb.scala 184:52] + node _T_407 = mux(UInt<1>("h01"), _T_406, _T_403) @[axi4_to_ahb.scala 184:24] + node _T_408 = bits(_T_404, 0, 0) @[axi4_to_ahb.scala 185:44] + node _T_409 = geq(UInt<1>("h00"), _T_407) @[axi4_to_ahb.scala 185:62] + node _T_410 = and(_T_408, _T_409) @[axi4_to_ahb.scala 185:48] + node _T_411 = bits(_T_404, 1, 1) @[axi4_to_ahb.scala 185:44] + node _T_412 = geq(UInt<1>("h01"), _T_407) @[axi4_to_ahb.scala 185:62] + node _T_413 = and(_T_411, _T_412) @[axi4_to_ahb.scala 185:48] + node _T_414 = bits(_T_404, 2, 2) @[axi4_to_ahb.scala 185:44] + node _T_415 = geq(UInt<2>("h02"), _T_407) @[axi4_to_ahb.scala 185:62] + node _T_416 = and(_T_414, _T_415) @[axi4_to_ahb.scala 185:48] + node _T_417 = bits(_T_404, 3, 3) @[axi4_to_ahb.scala 185:44] + node _T_418 = geq(UInt<2>("h03"), _T_407) @[axi4_to_ahb.scala 185:62] + node _T_419 = and(_T_417, _T_418) @[axi4_to_ahb.scala 185:48] + node _T_420 = bits(_T_404, 4, 4) @[axi4_to_ahb.scala 185:44] + node _T_421 = geq(UInt<3>("h04"), _T_407) @[axi4_to_ahb.scala 185:62] + node _T_422 = and(_T_420, _T_421) @[axi4_to_ahb.scala 185:48] + node _T_423 = bits(_T_404, 5, 5) @[axi4_to_ahb.scala 185:44] + node _T_424 = geq(UInt<3>("h05"), _T_407) @[axi4_to_ahb.scala 185:62] + node _T_425 = and(_T_423, _T_424) @[axi4_to_ahb.scala 185:48] + node _T_426 = bits(_T_404, 6, 6) @[axi4_to_ahb.scala 185:44] + node _T_427 = geq(UInt<3>("h06"), _T_407) @[axi4_to_ahb.scala 185:62] + node _T_428 = and(_T_426, _T_427) @[axi4_to_ahb.scala 185:48] + node _T_429 = bits(_T_404, 7, 7) @[axi4_to_ahb.scala 185:44] + node _T_430 = geq(UInt<3>("h07"), _T_407) @[axi4_to_ahb.scala 185:62] + node _T_431 = and(_T_429, _T_430) @[axi4_to_ahb.scala 185:48] + node _T_432 = mux(_T_431, UInt<3>("h07"), UInt<1>("h00")) @[Mux.scala 98:16] + node _T_433 = mux(_T_428, UInt<3>("h06"), _T_432) @[Mux.scala 98:16] + node _T_434 = mux(_T_425, UInt<3>("h05"), _T_433) @[Mux.scala 98:16] + node _T_435 = mux(_T_422, UInt<3>("h04"), _T_434) @[Mux.scala 98:16] + node _T_436 = mux(_T_419, UInt<2>("h03"), _T_435) @[Mux.scala 98:16] + node _T_437 = mux(_T_416, UInt<2>("h02"), _T_436) @[Mux.scala 98:16] + node _T_438 = mux(_T_413, UInt<1>("h01"), _T_437) @[Mux.scala 98:16] + node _T_439 = mux(_T_410, UInt<1>("h00"), _T_438) @[Mux.scala 98:16] + node _T_440 = mux(trxn_done, _T_439, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 335:106] + node _T_441 = mux(bypass_en, _T_402, _T_440) @[axi4_to_ahb.scala 335:30] + buf_cmd_byte_ptr <= _T_441 @[axi4_to_ahb.scala 335:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_428 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] - when _T_428 : @[Conditional.scala 39:67] - buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 330:20] - buf_state_en <= slave_ready @[axi4_to_ahb.scala 331:20] - slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 332:23] - slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 333:23] + node _T_442 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] + when _T_442 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 338:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 339:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 340:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 341:23] skip @[Conditional.scala 39:67] - buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 337:11] - cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 338:16] - node _T_429 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 339:68] - node _T_430 = eq(_T_429, UInt<1>("h01")) @[axi4_to_ahb.scala 339:75] - node _T_431 = and(buf_aligned_in, _T_430) @[axi4_to_ahb.scala 339:55] - node _T_432 = bits(_T_431, 0, 0) @[axi4_to_ahb.scala 339:95] - node _T_433 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 339:127] - wire _T_434 : UInt<8> - _T_434 <= UInt<8>("h00") - node _T_435 = bits(_T_434, 7, 0) @[axi4_to_ahb.scala 168:44] - node _T_436 = eq(_T_435, UInt<8>("h0ff")) @[axi4_to_ahb.scala 168:51] - node _T_437 = bits(_T_434, 7, 0) @[axi4_to_ahb.scala 168:75] - node _T_438 = eq(_T_437, UInt<4>("h0f")) @[axi4_to_ahb.scala 168:82] - node _T_439 = or(_T_436, _T_438) @[axi4_to_ahb.scala 168:64] - node _T_440 = bits(_T_434, 7, 0) @[axi4_to_ahb.scala 168:106] - node _T_441 = eq(_T_440, UInt<2>("h03")) @[axi4_to_ahb.scala 168:113] - node _T_442 = or(_T_439, _T_441) @[axi4_to_ahb.scala 168:95] - node _T_443 = bits(_T_442, 0, 0) @[Bitwise.scala 72:15] - node _T_444 = mux(_T_443, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_445 = and(UInt<1>("h00"), _T_444) @[axi4_to_ahb.scala 168:24] - node _T_446 = bits(_T_434, 7, 0) @[axi4_to_ahb.scala 169:35] - node _T_447 = eq(_T_446, UInt<4>("h0c")) @[axi4_to_ahb.scala 169:42] - node _T_448 = bits(_T_447, 0, 0) @[Bitwise.scala 72:15] - node _T_449 = mux(_T_448, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_450 = and(UInt<2>("h02"), _T_449) @[axi4_to_ahb.scala 169:15] - node _T_451 = or(_T_445, _T_450) @[axi4_to_ahb.scala 168:128] - node _T_452 = bits(_T_434, 7, 0) @[axi4_to_ahb.scala 170:36] - node _T_453 = eq(_T_452, UInt<8>("h0f0")) @[axi4_to_ahb.scala 170:43] - node _T_454 = bits(_T_434, 7, 0) @[axi4_to_ahb.scala 170:67] - node _T_455 = eq(_T_454, UInt<2>("h03")) @[axi4_to_ahb.scala 170:74] - node _T_456 = or(_T_453, _T_455) @[axi4_to_ahb.scala 170:56] + buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 345:11] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 346:16] + node _T_443 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 347:68] + node _T_444 = eq(_T_443, UInt<1>("h01")) @[axi4_to_ahb.scala 347:75] + node _T_445 = and(buf_aligned_in, _T_444) @[axi4_to_ahb.scala 347:55] + node _T_446 = bits(_T_445, 0, 0) @[axi4_to_ahb.scala 347:95] + node _T_447 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 347:127] + wire _T_448 : UInt<8> + _T_448 <= UInt<8>("h00") + node _T_449 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 176:44] + node _T_450 = eq(_T_449, UInt<8>("h0ff")) @[axi4_to_ahb.scala 176:51] + node _T_451 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 176:75] + node _T_452 = eq(_T_451, UInt<4>("h0f")) @[axi4_to_ahb.scala 176:82] + node _T_453 = or(_T_450, _T_452) @[axi4_to_ahb.scala 176:64] + node _T_454 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 176:106] + node _T_455 = eq(_T_454, UInt<2>("h03")) @[axi4_to_ahb.scala 176:113] + node _T_456 = or(_T_453, _T_455) @[axi4_to_ahb.scala 176:95] node _T_457 = bits(_T_456, 0, 0) @[Bitwise.scala 72:15] node _T_458 = mux(_T_457, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_459 = and(UInt<3>("h04"), _T_458) @[axi4_to_ahb.scala 170:15] - node _T_460 = bits(_T_434, 7, 0) @[axi4_to_ahb.scala 171:37] - node _T_461 = eq(_T_460, UInt<8>("h0c0")) @[axi4_to_ahb.scala 171:44] + node _T_459 = and(UInt<1>("h00"), _T_458) @[axi4_to_ahb.scala 176:24] + node _T_460 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 177:35] + node _T_461 = eq(_T_460, UInt<4>("h0c")) @[axi4_to_ahb.scala 177:42] node _T_462 = bits(_T_461, 0, 0) @[Bitwise.scala 72:15] node _T_463 = mux(_T_462, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_464 = and(UInt<3>("h06"), _T_463) @[axi4_to_ahb.scala 171:17] - node _T_465 = or(_T_459, _T_464) @[axi4_to_ahb.scala 170:90] - node _T_466 = or(_T_451, _T_465) @[axi4_to_ahb.scala 169:58] - node _T_467 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 339:147] - node _T_468 = mux(_T_432, _T_466, _T_467) @[axi4_to_ahb.scala 339:38] - node _T_469 = cat(master_addr, _T_468) @[Cat.scala 29:58] - buf_addr_in <= _T_469 @[axi4_to_ahb.scala 339:15] - node _T_470 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 340:27] - buf_tag_in <= _T_470 @[axi4_to_ahb.scala 340:14] - node _T_471 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 341:32] - buf_byteen_in <= _T_471 @[axi4_to_ahb.scala 341:17] - node _T_472 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 342:33] - node _T_473 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 342:59] - node _T_474 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 342:80] - node _T_475 = mux(_T_472, _T_473, _T_474) @[axi4_to_ahb.scala 342:21] - buf_data_in <= _T_475 @[axi4_to_ahb.scala 342:15] - node _T_476 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 343:52] - node _T_477 = eq(_T_476, UInt<2>("h03")) @[axi4_to_ahb.scala 343:59] - node _T_478 = and(buf_aligned_in, _T_477) @[axi4_to_ahb.scala 343:38] - node _T_479 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 343:85] - node _T_480 = eq(_T_479, UInt<1>("h01")) @[axi4_to_ahb.scala 343:92] - node _T_481 = and(_T_478, _T_480) @[axi4_to_ahb.scala 343:72] - node _T_482 = bits(_T_481, 0, 0) @[axi4_to_ahb.scala 343:112] - node _T_483 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:144] - wire _T_484 : UInt<8> - _T_484 <= UInt<8>("h00") - node _T_485 = bits(_T_484, 7, 0) @[axi4_to_ahb.scala 160:43] - node _T_486 = eq(_T_485, UInt<8>("h0ff")) @[axi4_to_ahb.scala 160:50] - node _T_487 = bits(_T_486, 0, 0) @[Bitwise.scala 72:15] - node _T_488 = mux(_T_487, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_489 = and(UInt<2>("h03"), _T_488) @[axi4_to_ahb.scala 160:25] - node _T_490 = bits(_T_484, 7, 0) @[axi4_to_ahb.scala 161:34] - node _T_491 = eq(_T_490, UInt<8>("h0f0")) @[axi4_to_ahb.scala 161:41] - node _T_492 = bits(_T_484, 7, 0) @[axi4_to_ahb.scala 161:63] - node _T_493 = eq(_T_492, UInt<4>("h0f")) @[axi4_to_ahb.scala 161:70] - node _T_494 = or(_T_491, _T_493) @[axi4_to_ahb.scala 161:54] - node _T_495 = bits(_T_494, 0, 0) @[Bitwise.scala 72:15] - node _T_496 = mux(_T_495, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_497 = and(UInt<2>("h02"), _T_496) @[axi4_to_ahb.scala 161:16] - node _T_498 = or(_T_489, _T_497) @[axi4_to_ahb.scala 160:65] - node _T_499 = bits(_T_484, 7, 0) @[axi4_to_ahb.scala 162:34] - node _T_500 = eq(_T_499, UInt<8>("h0c0")) @[axi4_to_ahb.scala 162:41] - node _T_501 = bits(_T_484, 7, 0) @[axi4_to_ahb.scala 162:63] - node _T_502 = eq(_T_501, UInt<6>("h030")) @[axi4_to_ahb.scala 162:70] - node _T_503 = or(_T_500, _T_502) @[axi4_to_ahb.scala 162:54] - node _T_504 = bits(_T_484, 7, 0) @[axi4_to_ahb.scala 162:92] - node _T_505 = eq(_T_504, UInt<4>("h0c")) @[axi4_to_ahb.scala 162:99] - node _T_506 = or(_T_503, _T_505) @[axi4_to_ahb.scala 162:83] - node _T_507 = bits(_T_484, 7, 0) @[axi4_to_ahb.scala 162:121] - node _T_508 = eq(_T_507, UInt<2>("h03")) @[axi4_to_ahb.scala 162:128] - node _T_509 = or(_T_506, _T_508) @[axi4_to_ahb.scala 162:112] - node _T_510 = bits(_T_509, 0, 0) @[Bitwise.scala 72:15] - node _T_511 = mux(_T_510, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_512 = and(UInt<1>("h01"), _T_511) @[axi4_to_ahb.scala 162:16] - node _T_513 = or(_T_498, _T_512) @[axi4_to_ahb.scala 161:86] - node _T_514 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 343:164] - node _T_515 = mux(_T_482, _T_513, _T_514) @[axi4_to_ahb.scala 343:21] - buf_size_in <= _T_515 @[axi4_to_ahb.scala 343:15] - node _T_516 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 344:32] - node _T_517 = eq(_T_516, UInt<1>("h00")) @[axi4_to_ahb.scala 344:39] - node _T_518 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 345:17] - node _T_519 = eq(_T_518, UInt<1>("h00")) @[axi4_to_ahb.scala 345:24] - node _T_520 = or(_T_517, _T_519) @[axi4_to_ahb.scala 344:51] - node _T_521 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 345:50] - node _T_522 = eq(_T_521, UInt<1>("h01")) @[axi4_to_ahb.scala 345:57] - node _T_523 = or(_T_520, _T_522) @[axi4_to_ahb.scala 345:36] - node _T_524 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 345:84] - node _T_525 = eq(_T_524, UInt<2>("h02")) @[axi4_to_ahb.scala 345:91] - node _T_526 = or(_T_523, _T_525) @[axi4_to_ahb.scala 345:70] - node _T_527 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 346:18] - node _T_528 = eq(_T_527, UInt<2>("h03")) @[axi4_to_ahb.scala 346:25] - node _T_529 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 346:55] - node _T_530 = eq(_T_529, UInt<2>("h03")) @[axi4_to_ahb.scala 346:62] - node _T_531 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 346:90] - node _T_532 = eq(_T_531, UInt<4>("h0c")) @[axi4_to_ahb.scala 346:97] - node _T_533 = or(_T_530, _T_532) @[axi4_to_ahb.scala 346:74] - node _T_534 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 346:125] - node _T_535 = eq(_T_534, UInt<6>("h030")) @[axi4_to_ahb.scala 346:132] - node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 346:109] - node _T_537 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 346:161] - node _T_538 = eq(_T_537, UInt<8>("h0c0")) @[axi4_to_ahb.scala 346:168] - node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 346:145] - node _T_540 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 347:21] - node _T_541 = eq(_T_540, UInt<4>("h0f")) @[axi4_to_ahb.scala 347:28] - node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 346:181] - node _T_543 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 347:56] - node _T_544 = eq(_T_543, UInt<8>("h0f0")) @[axi4_to_ahb.scala 347:63] - node _T_545 = or(_T_542, _T_544) @[axi4_to_ahb.scala 347:40] - node _T_546 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 347:92] - node _T_547 = eq(_T_546, UInt<8>("h0ff")) @[axi4_to_ahb.scala 347:99] - node _T_548 = or(_T_545, _T_547) @[axi4_to_ahb.scala 347:76] - node _T_549 = and(_T_528, _T_548) @[axi4_to_ahb.scala 346:38] - node _T_550 = or(_T_526, _T_549) @[axi4_to_ahb.scala 345:104] - buf_aligned_in <= _T_550 @[axi4_to_ahb.scala 344:18] - node _T_551 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 349:39] - node _T_552 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 349:58] - node _T_553 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 349:83] - node _T_554 = cat(_T_552, _T_553) @[Cat.scala 29:58] - node _T_555 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 349:104] - node _T_556 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 349:129] - node _T_557 = cat(_T_555, _T_556) @[Cat.scala 29:58] - node _T_558 = mux(_T_551, _T_554, _T_557) @[axi4_to_ahb.scala 349:22] - io.ahb_haddr <= _T_558 @[axi4_to_ahb.scala 349:16] - node _T_559 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 350:39] - node _T_560 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] - node _T_561 = mux(_T_560, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_562 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 350:93] - node _T_563 = and(_T_561, _T_562) @[axi4_to_ahb.scala 350:80] - node _T_564 = cat(UInt<1>("h00"), _T_563) @[Cat.scala 29:58] - node _T_565 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] - node _T_566 = mux(_T_565, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_567 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 350:148] - node _T_568 = and(_T_566, _T_567) @[axi4_to_ahb.scala 350:138] - node _T_569 = cat(UInt<1>("h00"), _T_568) @[Cat.scala 29:58] - node _T_570 = mux(_T_559, _T_564, _T_569) @[axi4_to_ahb.scala 350:22] - io.ahb_hsize <= _T_570 @[axi4_to_ahb.scala 350:16] - io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 352:17] - io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 353:20] - node _T_571 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 354:47] - node _T_572 = not(_T_571) @[axi4_to_ahb.scala 354:33] - node _T_573 = cat(UInt<1>("h01"), _T_572) @[Cat.scala 29:58] - io.ahb_hprot <= _T_573 @[axi4_to_ahb.scala 354:16] - node _T_574 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 355:40] - node _T_575 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 355:55] - node _T_576 = eq(_T_575, UInt<1>("h01")) @[axi4_to_ahb.scala 355:62] - node _T_577 = mux(_T_574, _T_576, buf_write) @[axi4_to_ahb.scala 355:23] - io.ahb_hwrite <= _T_577 @[axi4_to_ahb.scala 355:17] - node _T_578 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 356:28] - io.ahb_hwdata <= _T_578 @[axi4_to_ahb.scala 356:17] - slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 358:15] - node _T_579 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 359:43] - node _T_580 = mux(_T_579, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 359:23] - node _T_581 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] - node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_583 = and(_T_582, UInt<2>("h02")) @[axi4_to_ahb.scala 359:88] - node _T_584 = cat(_T_580, _T_583) @[Cat.scala 29:58] - slave_opc <= _T_584 @[axi4_to_ahb.scala 359:13] - node _T_585 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 360:41] - node _T_586 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 360:66] - node _T_587 = cat(_T_586, _T_586) @[Cat.scala 29:58] - node _T_588 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 360:91] - node _T_589 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 360:110] - node _T_590 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 360:131] - node _T_591 = mux(_T_588, _T_589, _T_590) @[axi4_to_ahb.scala 360:79] - node _T_592 = mux(_T_585, _T_587, _T_591) @[axi4_to_ahb.scala 360:21] - slave_rdata <= _T_592 @[axi4_to_ahb.scala 360:15] - node _T_593 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 361:26] - slave_tag <= _T_593 @[axi4_to_ahb.scala 361:13] - node _T_594 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 363:33] - node _T_595 = neq(_T_594, UInt<1>("h00")) @[axi4_to_ahb.scala 363:40] - node _T_596 = and(_T_595, io.ahb_hready) @[axi4_to_ahb.scala 363:52] - node _T_597 = and(_T_596, io.ahb_hwrite) @[axi4_to_ahb.scala 363:68] - last_addr_en <= _T_597 @[axi4_to_ahb.scala 363:16] - node _T_598 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 365:30] - node _T_599 = and(_T_598, master_ready) @[axi4_to_ahb.scala 365:47] - wrbuf_en <= _T_599 @[axi4_to_ahb.scala 365:12] - node _T_600 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 366:34] - node _T_601 = and(_T_600, master_ready) @[axi4_to_ahb.scala 366:50] - wrbuf_data_en <= _T_601 @[axi4_to_ahb.scala 366:17] - node _T_602 = and(master_valid, master_ready) @[axi4_to_ahb.scala 367:34] - node _T_603 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 367:62] - node _T_604 = eq(_T_603, UInt<1>("h01")) @[axi4_to_ahb.scala 367:69] - node _T_605 = and(_T_602, _T_604) @[axi4_to_ahb.scala 367:49] - wrbuf_cmd_sent <= _T_605 @[axi4_to_ahb.scala 367:18] - node _T_606 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 368:33] - node _T_607 = and(wrbuf_cmd_sent, _T_606) @[axi4_to_ahb.scala 368:31] - wrbuf_rst <= _T_607 @[axi4_to_ahb.scala 368:13] - node _T_608 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 370:35] - node _T_609 = and(wrbuf_vld, _T_608) @[axi4_to_ahb.scala 370:33] - node _T_610 = eq(_T_609, UInt<1>("h00")) @[axi4_to_ahb.scala 370:21] - node _T_611 = and(_T_610, master_ready) @[axi4_to_ahb.scala 370:52] - io.axi_awready <= _T_611 @[axi4_to_ahb.scala 370:18] - node _T_612 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 371:39] - node _T_613 = and(wrbuf_data_vld, _T_612) @[axi4_to_ahb.scala 371:37] - node _T_614 = eq(_T_613, UInt<1>("h00")) @[axi4_to_ahb.scala 371:20] - node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 371:56] - io.axi_wready <= _T_615 @[axi4_to_ahb.scala 371:17] - node _T_616 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 372:33] - node _T_617 = eq(_T_616, UInt<1>("h00")) @[axi4_to_ahb.scala 372:21] - node _T_618 = and(_T_617, master_ready) @[axi4_to_ahb.scala 372:51] - io.axi_arready <= _T_618 @[axi4_to_ahb.scala 372:18] - io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 373:16] - node _T_619 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 376:68] - node _T_620 = mux(_T_619, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 376:52] - node _T_621 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 376:88] - node _T_622 = and(_T_620, _T_621) @[axi4_to_ahb.scala 376:86] - reg _T_623 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 376:48] - _T_623 <= _T_622 @[axi4_to_ahb.scala 376:48] - wrbuf_vld <= _T_623 @[axi4_to_ahb.scala 376:18] - node _T_624 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 377:73] - node _T_625 = mux(_T_624, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 377:52] - node _T_626 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 377:99] - node _T_627 = and(_T_625, _T_626) @[axi4_to_ahb.scala 377:97] - reg _T_628 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 377:48] - _T_628 <= _T_627 @[axi4_to_ahb.scala 377:48] - wrbuf_data_vld <= _T_628 @[axi4_to_ahb.scala 377:18] - node _T_629 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 379:57] - node _T_630 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 379:91] - reg _T_631 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_630 : @[Reg.scala 28:19] - _T_631 <= _T_629 @[Reg.scala 28:23] + node _T_464 = and(UInt<2>("h02"), _T_463) @[axi4_to_ahb.scala 177:15] + node _T_465 = or(_T_459, _T_464) @[axi4_to_ahb.scala 176:128] + node _T_466 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 178:36] + node _T_467 = eq(_T_466, UInt<8>("h0f0")) @[axi4_to_ahb.scala 178:43] + node _T_468 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 178:67] + node _T_469 = eq(_T_468, UInt<2>("h03")) @[axi4_to_ahb.scala 178:74] + node _T_470 = or(_T_467, _T_469) @[axi4_to_ahb.scala 178:56] + node _T_471 = bits(_T_470, 0, 0) @[Bitwise.scala 72:15] + node _T_472 = mux(_T_471, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_473 = and(UInt<3>("h04"), _T_472) @[axi4_to_ahb.scala 178:15] + node _T_474 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 179:37] + node _T_475 = eq(_T_474, UInt<8>("h0c0")) @[axi4_to_ahb.scala 179:44] + node _T_476 = bits(_T_475, 0, 0) @[Bitwise.scala 72:15] + node _T_477 = mux(_T_476, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_478 = and(UInt<3>("h06"), _T_477) @[axi4_to_ahb.scala 179:17] + node _T_479 = or(_T_473, _T_478) @[axi4_to_ahb.scala 178:90] + node _T_480 = or(_T_465, _T_479) @[axi4_to_ahb.scala 177:58] + node _T_481 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 347:147] + node _T_482 = mux(_T_446, _T_480, _T_481) @[axi4_to_ahb.scala 347:38] + node _T_483 = cat(master_addr, _T_482) @[Cat.scala 29:58] + buf_addr_in <= _T_483 @[axi4_to_ahb.scala 347:15] + node _T_484 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 348:27] + buf_tag_in <= _T_484 @[axi4_to_ahb.scala 348:14] + node _T_485 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 349:32] + buf_byteen_in <= _T_485 @[axi4_to_ahb.scala 349:17] + node _T_486 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 350:33] + node _T_487 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 350:59] + node _T_488 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 350:80] + node _T_489 = mux(_T_486, _T_487, _T_488) @[axi4_to_ahb.scala 350:21] + buf_data_in <= _T_489 @[axi4_to_ahb.scala 350:15] + node _T_490 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 351:52] + node _T_491 = eq(_T_490, UInt<2>("h03")) @[axi4_to_ahb.scala 351:59] + node _T_492 = and(buf_aligned_in, _T_491) @[axi4_to_ahb.scala 351:38] + node _T_493 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 351:85] + node _T_494 = eq(_T_493, UInt<1>("h01")) @[axi4_to_ahb.scala 351:92] + node _T_495 = and(_T_492, _T_494) @[axi4_to_ahb.scala 351:72] + node _T_496 = bits(_T_495, 0, 0) @[axi4_to_ahb.scala 351:112] + node _T_497 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 351:144] + wire _T_498 : UInt<8> + _T_498 <= UInt<8>("h00") + node _T_499 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 168:43] + node _T_500 = eq(_T_499, UInt<8>("h0ff")) @[axi4_to_ahb.scala 168:50] + node _T_501 = bits(_T_500, 0, 0) @[Bitwise.scala 72:15] + node _T_502 = mux(_T_501, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_503 = and(UInt<2>("h03"), _T_502) @[axi4_to_ahb.scala 168:25] + node _T_504 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 169:34] + node _T_505 = eq(_T_504, UInt<8>("h0f0")) @[axi4_to_ahb.scala 169:41] + node _T_506 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 169:63] + node _T_507 = eq(_T_506, UInt<4>("h0f")) @[axi4_to_ahb.scala 169:70] + node _T_508 = or(_T_505, _T_507) @[axi4_to_ahb.scala 169:54] + node _T_509 = bits(_T_508, 0, 0) @[Bitwise.scala 72:15] + node _T_510 = mux(_T_509, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_511 = and(UInt<2>("h02"), _T_510) @[axi4_to_ahb.scala 169:16] + node _T_512 = or(_T_503, _T_511) @[axi4_to_ahb.scala 168:65] + node _T_513 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 170:34] + node _T_514 = eq(_T_513, UInt<8>("h0c0")) @[axi4_to_ahb.scala 170:41] + node _T_515 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 170:63] + node _T_516 = eq(_T_515, UInt<6>("h030")) @[axi4_to_ahb.scala 170:70] + node _T_517 = or(_T_514, _T_516) @[axi4_to_ahb.scala 170:54] + node _T_518 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 170:92] + node _T_519 = eq(_T_518, UInt<4>("h0c")) @[axi4_to_ahb.scala 170:99] + node _T_520 = or(_T_517, _T_519) @[axi4_to_ahb.scala 170:83] + node _T_521 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 170:121] + node _T_522 = eq(_T_521, UInt<2>("h03")) @[axi4_to_ahb.scala 170:128] + node _T_523 = or(_T_520, _T_522) @[axi4_to_ahb.scala 170:112] + node _T_524 = bits(_T_523, 0, 0) @[Bitwise.scala 72:15] + node _T_525 = mux(_T_524, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_526 = and(UInt<1>("h01"), _T_525) @[axi4_to_ahb.scala 170:16] + node _T_527 = or(_T_512, _T_526) @[axi4_to_ahb.scala 169:86] + node _T_528 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 351:164] + node _T_529 = mux(_T_496, _T_527, _T_528) @[axi4_to_ahb.scala 351:21] + buf_size_in <= _T_529 @[axi4_to_ahb.scala 351:15] + node _T_530 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 352:32] + node _T_531 = eq(_T_530, UInt<1>("h00")) @[axi4_to_ahb.scala 352:39] + node _T_532 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 353:17] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 353:24] + node _T_534 = or(_T_531, _T_533) @[axi4_to_ahb.scala 352:51] + node _T_535 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 353:50] + node _T_536 = eq(_T_535, UInt<1>("h01")) @[axi4_to_ahb.scala 353:57] + node _T_537 = or(_T_534, _T_536) @[axi4_to_ahb.scala 353:36] + node _T_538 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 353:84] + node _T_539 = eq(_T_538, UInt<2>("h02")) @[axi4_to_ahb.scala 353:91] + node _T_540 = or(_T_537, _T_539) @[axi4_to_ahb.scala 353:70] + node _T_541 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 354:18] + node _T_542 = eq(_T_541, UInt<2>("h03")) @[axi4_to_ahb.scala 354:25] + node _T_543 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 354:55] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 354:62] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 354:90] + node _T_546 = eq(_T_545, UInt<4>("h0c")) @[axi4_to_ahb.scala 354:97] + node _T_547 = or(_T_544, _T_546) @[axi4_to_ahb.scala 354:74] + node _T_548 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 354:125] + node _T_549 = eq(_T_548, UInt<6>("h030")) @[axi4_to_ahb.scala 354:132] + node _T_550 = or(_T_547, _T_549) @[axi4_to_ahb.scala 354:109] + node _T_551 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 354:161] + node _T_552 = eq(_T_551, UInt<8>("h0c0")) @[axi4_to_ahb.scala 354:168] + node _T_553 = or(_T_550, _T_552) @[axi4_to_ahb.scala 354:145] + node _T_554 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 355:21] + node _T_555 = eq(_T_554, UInt<4>("h0f")) @[axi4_to_ahb.scala 355:28] + node _T_556 = or(_T_553, _T_555) @[axi4_to_ahb.scala 354:181] + node _T_557 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 355:56] + node _T_558 = eq(_T_557, UInt<8>("h0f0")) @[axi4_to_ahb.scala 355:63] + node _T_559 = or(_T_556, _T_558) @[axi4_to_ahb.scala 355:40] + node _T_560 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 355:92] + node _T_561 = eq(_T_560, UInt<8>("h0ff")) @[axi4_to_ahb.scala 355:99] + node _T_562 = or(_T_559, _T_561) @[axi4_to_ahb.scala 355:76] + node _T_563 = and(_T_542, _T_562) @[axi4_to_ahb.scala 354:38] + node _T_564 = or(_T_540, _T_563) @[axi4_to_ahb.scala 353:104] + buf_aligned_in <= _T_564 @[axi4_to_ahb.scala 352:18] + node _T_565 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 357:39] + node _T_566 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 357:58] + node _T_567 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 357:83] + node _T_568 = cat(_T_566, _T_567) @[Cat.scala 29:58] + node _T_569 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 357:104] + node _T_570 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 357:129] + node _T_571 = cat(_T_569, _T_570) @[Cat.scala 29:58] + node _T_572 = mux(_T_565, _T_568, _T_571) @[axi4_to_ahb.scala 357:22] + io.ahb_haddr <= _T_572 @[axi4_to_ahb.scala 357:16] + node _T_573 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 358:39] + node _T_574 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] + node _T_575 = mux(_T_574, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_576 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 358:93] + node _T_577 = and(_T_575, _T_576) @[axi4_to_ahb.scala 358:80] + node _T_578 = cat(UInt<1>("h00"), _T_577) @[Cat.scala 29:58] + node _T_579 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] + node _T_580 = mux(_T_579, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_581 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 358:148] + node _T_582 = and(_T_580, _T_581) @[axi4_to_ahb.scala 358:138] + node _T_583 = cat(UInt<1>("h00"), _T_582) @[Cat.scala 29:58] + node _T_584 = mux(_T_573, _T_578, _T_583) @[axi4_to_ahb.scala 358:22] + io.ahb_hsize <= _T_584 @[axi4_to_ahb.scala 358:16] + io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 360:17] + io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 361:20] + node _T_585 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 362:47] + node _T_586 = not(_T_585) @[axi4_to_ahb.scala 362:33] + node _T_587 = cat(UInt<1>("h01"), _T_586) @[Cat.scala 29:58] + io.ahb_hprot <= _T_587 @[axi4_to_ahb.scala 362:16] + node _T_588 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 363:40] + node _T_589 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 363:55] + node _T_590 = eq(_T_589, UInt<1>("h01")) @[axi4_to_ahb.scala 363:62] + node _T_591 = mux(_T_588, _T_590, buf_write) @[axi4_to_ahb.scala 363:23] + io.ahb_hwrite <= _T_591 @[axi4_to_ahb.scala 363:17] + node _T_592 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 364:28] + io.ahb_hwdata <= _T_592 @[axi4_to_ahb.scala 364:17] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 366:15] + node _T_593 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 367:43] + node _T_594 = mux(_T_593, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 367:23] + node _T_595 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] + node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_597 = and(_T_596, UInt<2>("h02")) @[axi4_to_ahb.scala 367:88] + node _T_598 = cat(_T_594, _T_597) @[Cat.scala 29:58] + slave_opc <= _T_598 @[axi4_to_ahb.scala 367:13] + node _T_599 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 368:41] + node _T_600 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 368:66] + node _T_601 = cat(_T_600, _T_600) @[Cat.scala 29:58] + node _T_602 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 368:91] + node _T_603 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 368:110] + node _T_604 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 368:131] + node _T_605 = mux(_T_602, _T_603, _T_604) @[axi4_to_ahb.scala 368:79] + node _T_606 = mux(_T_599, _T_601, _T_605) @[axi4_to_ahb.scala 368:21] + slave_rdata <= _T_606 @[axi4_to_ahb.scala 368:15] + node _T_607 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 369:26] + slave_tag <= _T_607 @[axi4_to_ahb.scala 369:13] + node _T_608 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 371:33] + node _T_609 = neq(_T_608, UInt<1>("h00")) @[axi4_to_ahb.scala 371:40] + node _T_610 = and(_T_609, io.ahb_hready) @[axi4_to_ahb.scala 371:52] + node _T_611 = and(_T_610, io.ahb_hwrite) @[axi4_to_ahb.scala 371:68] + last_addr_en <= _T_611 @[axi4_to_ahb.scala 371:16] + node _T_612 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 373:30] + node _T_613 = and(_T_612, master_ready) @[axi4_to_ahb.scala 373:47] + wrbuf_en <= _T_613 @[axi4_to_ahb.scala 373:12] + node _T_614 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 374:34] + node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 374:50] + wrbuf_data_en <= _T_615 @[axi4_to_ahb.scala 374:17] + node _T_616 = and(master_valid, master_ready) @[axi4_to_ahb.scala 375:34] + node _T_617 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 375:62] + node _T_618 = eq(_T_617, UInt<1>("h01")) @[axi4_to_ahb.scala 375:69] + node _T_619 = and(_T_616, _T_618) @[axi4_to_ahb.scala 375:49] + wrbuf_cmd_sent <= _T_619 @[axi4_to_ahb.scala 375:18] + node _T_620 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 376:33] + node _T_621 = and(wrbuf_cmd_sent, _T_620) @[axi4_to_ahb.scala 376:31] + wrbuf_rst <= _T_621 @[axi4_to_ahb.scala 376:13] + node _T_622 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 378:35] + node _T_623 = and(wrbuf_vld, _T_622) @[axi4_to_ahb.scala 378:33] + node _T_624 = eq(_T_623, UInt<1>("h00")) @[axi4_to_ahb.scala 378:21] + node _T_625 = and(_T_624, master_ready) @[axi4_to_ahb.scala 378:52] + io.axi_awready <= _T_625 @[axi4_to_ahb.scala 378:18] + node _T_626 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 379:39] + node _T_627 = and(wrbuf_data_vld, _T_626) @[axi4_to_ahb.scala 379:37] + node _T_628 = eq(_T_627, UInt<1>("h00")) @[axi4_to_ahb.scala 379:20] + node _T_629 = and(_T_628, master_ready) @[axi4_to_ahb.scala 379:56] + io.axi_wready <= _T_629 @[axi4_to_ahb.scala 379:17] + node _T_630 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 380:33] + node _T_631 = eq(_T_630, UInt<1>("h00")) @[axi4_to_ahb.scala 380:21] + node _T_632 = and(_T_631, master_ready) @[axi4_to_ahb.scala 380:51] + io.axi_arready <= _T_632 @[axi4_to_ahb.scala 380:18] + io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 381:16] + node _T_633 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 384:68] + node _T_634 = mux(_T_633, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 384:52] + node _T_635 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 384:88] + node _T_636 = and(_T_634, _T_635) @[axi4_to_ahb.scala 384:86] + reg _T_637 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 384:48] + _T_637 <= _T_636 @[axi4_to_ahb.scala 384:48] + wrbuf_vld <= _T_637 @[axi4_to_ahb.scala 384:18] + node _T_638 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 385:73] + node _T_639 = mux(_T_638, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 385:52] + node _T_640 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 385:99] + node _T_641 = and(_T_639, _T_640) @[axi4_to_ahb.scala 385:97] + reg _T_642 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 385:48] + _T_642 <= _T_641 @[axi4_to_ahb.scala 385:48] + wrbuf_data_vld <= _T_642 @[axi4_to_ahb.scala 385:18] + node _T_643 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 387:57] + node _T_644 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 387:91] + reg _T_645 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_644 : @[Reg.scala 28:19] + _T_645 <= _T_643 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_tag <= _T_631 @[axi4_to_ahb.scala 379:13] - node _T_632 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 380:60] - node _T_633 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 380:88] - reg _T_634 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_633 : @[Reg.scala 28:19] - _T_634 <= _T_632 @[Reg.scala 28:23] + wrbuf_tag <= _T_645 @[axi4_to_ahb.scala 387:13] + node _T_646 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 388:60] + node _T_647 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 388:88] + reg _T_648 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_647 : @[Reg.scala 28:19] + _T_648 <= _T_646 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_size <= _T_634 @[axi4_to_ahb.scala 380:14] - node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 382:48] + wrbuf_size <= _T_648 @[axi4_to_ahb.scala 388:14] + node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 390:48] inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23] rvclkhdr_2.clock <= clock rvclkhdr_2.reset <= reset rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_2.io.en <= _T_635 @[el2_lib.scala 511:17] + rvclkhdr_2.io.en <= _T_649 @[el2_lib.scala 511:17] rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_636 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_636 <= io.axi_awaddr @[el2_lib.scala 514:16] - wrbuf_addr <= _T_636 @[axi4_to_ahb.scala 382:14] - node _T_637 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 383:52] + reg _T_650 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_650 <= io.axi_awaddr @[el2_lib.scala 514:16] + wrbuf_addr <= _T_650 @[axi4_to_ahb.scala 390:14] + node _T_651 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 391:52] inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23] rvclkhdr_3.clock <= clock rvclkhdr_3.reset <= reset rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_3.io.en <= _T_637 @[el2_lib.scala 511:17] + rvclkhdr_3.io.en <= _T_651 @[el2_lib.scala 511:17] rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_638 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_638 <= io.axi_wdata @[el2_lib.scala 514:16] - wrbuf_data <= _T_638 @[axi4_to_ahb.scala 383:14] - node _T_639 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 386:27] - node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 386:60] - reg _T_641 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_640 : @[Reg.scala 28:19] - _T_641 <= _T_639 @[Reg.scala 28:23] + reg _T_652 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_652 <= io.axi_wdata @[el2_lib.scala 514:16] + wrbuf_data <= _T_652 @[axi4_to_ahb.scala 391:14] + node _T_653 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 394:27] + node _T_654 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 394:60] + reg _T_655 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_654 : @[Reg.scala 28:19] + _T_655 <= _T_653 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - wrbuf_byteen <= _T_641 @[axi4_to_ahb.scala 385:16] - node _T_642 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 389:27] - node _T_643 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 389:60] - reg _T_644 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_643 : @[Reg.scala 28:19] - _T_644 <= _T_642 @[Reg.scala 28:23] + wrbuf_byteen <= _T_655 @[axi4_to_ahb.scala 393:16] + node _T_656 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 397:27] + node _T_657 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 397:60] + reg _T_658 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_657 : @[Reg.scala 28:19] + _T_658 <= _T_656 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - last_bus_addr <= _T_644 @[axi4_to_ahb.scala 388:17] - node _T_645 = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 393:36] - node _T_646 = mux(_T_645, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 393:16] - node _T_647 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 393:65] - node _T_648 = and(_T_646, _T_647) @[axi4_to_ahb.scala 393:63] - reg _T_649 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 393:12] - _T_649 <= _T_648 @[axi4_to_ahb.scala 393:12] - buf_state <= _T_649 @[axi4_to_ahb.scala 392:13] - node _T_650 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 397:50] - reg _T_651 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_650 : @[Reg.scala 28:19] - _T_651 <= buf_write_in @[Reg.scala 28:23] + last_bus_addr <= _T_658 @[axi4_to_ahb.scala 396:17] + node _T_659 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 405:50] + reg _T_660 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_659 : @[Reg.scala 28:19] + _T_660 <= buf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write <= _T_651 @[axi4_to_ahb.scala 396:13] - node _T_652 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 400:25] - node _T_653 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 400:60] - reg _T_654 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_653 : @[Reg.scala 28:19] - _T_654 <= _T_652 @[Reg.scala 28:23] + buf_write <= _T_660 @[axi4_to_ahb.scala 404:13] + node _T_661 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 408:25] + node _T_662 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 408:60] + reg _T_663 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_662 : @[Reg.scala 28:19] + _T_663 <= _T_661 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_tag <= _T_654 @[axi4_to_ahb.scala 399:11] - node _T_655 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 403:33] - node _T_656 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 403:52] - node _T_657 = bits(_T_656, 0, 0) @[axi4_to_ahb.scala 403:69] + buf_tag <= _T_663 @[axi4_to_ahb.scala 407:11] + node _T_664 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 411:33] + node _T_665 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 411:52] + node _T_666 = bits(_T_665, 0, 0) @[axi4_to_ahb.scala 411:69] inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23] rvclkhdr_4.clock <= clock rvclkhdr_4.reset <= reset rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_4.io.en <= _T_657 @[el2_lib.scala 511:17] + rvclkhdr_4.io.en <= _T_666 @[el2_lib.scala 511:17] rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_658 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_658 <= _T_655 @[el2_lib.scala 514:16] - buf_addr <= _T_658 @[axi4_to_ahb.scala 403:12] - node _T_659 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 406:26] - node _T_660 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 406:55] - reg _T_661 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_660 : @[Reg.scala 28:19] - _T_661 <= _T_659 @[Reg.scala 28:23] + reg _T_667 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_667 <= _T_664 @[el2_lib.scala 514:16] + buf_addr <= _T_667 @[axi4_to_ahb.scala 411:12] + node _T_668 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 414:26] + node _T_669 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 414:55] + reg _T_670 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_669 : @[Reg.scala 28:19] + _T_670 <= _T_668 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_size <= _T_661 @[axi4_to_ahb.scala 405:12] - node _T_662 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 409:52] - reg _T_663 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_662 : @[Reg.scala 28:19] - _T_663 <= buf_aligned_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_aligned <= _T_663 @[axi4_to_ahb.scala 408:15] - node _T_664 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 412:28] - node _T_665 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 412:57] - reg _T_666 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_665 : @[Reg.scala 28:19] - _T_666 <= _T_664 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_byteen <= _T_666 @[axi4_to_ahb.scala 411:14] - node _T_667 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 415:33] - node _T_668 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 415:57] - node _T_669 = bits(_T_668, 0, 0) @[axi4_to_ahb.scala 415:80] - inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23] - rvclkhdr_5.clock <= clock - rvclkhdr_5.reset <= reset - rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] - rvclkhdr_5.io.en <= _T_669 @[el2_lib.scala 511:17] - rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] - reg _T_670 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] - _T_670 <= _T_667 @[el2_lib.scala 514:16] - buf_data <= _T_670 @[axi4_to_ahb.scala 415:12] - node _T_671 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 418:50] + buf_size <= _T_670 @[axi4_to_ahb.scala 413:12] + node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 417:52] reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_671 : @[Reg.scala 28:19] - _T_672 <= buf_write @[Reg.scala 28:23] + _T_672 <= buf_aligned_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_write <= _T_672 @[axi4_to_ahb.scala 417:16] - node _T_673 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 421:22] - node _T_674 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 421:60] + buf_aligned <= _T_672 @[axi4_to_ahb.scala 416:15] + node _T_673 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 420:28] + node _T_674 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 420:57] reg _T_675 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_674 : @[Reg.scala 28:19] _T_675 <= _T_673 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_tag <= _T_675 @[axi4_to_ahb.scala 420:14] - node _T_676 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 424:59] - reg _T_677 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_676 : @[Reg.scala 28:19] - _T_677 <= slvbuf_error_in @[Reg.scala 28:23] + buf_byteen <= _T_675 @[axi4_to_ahb.scala 419:14] + node _T_676 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 423:33] + node _T_677 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 423:57] + node _T_678 = bits(_T_677, 0, 0) @[axi4_to_ahb.scala 423:80] + inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_5.io.en <= _T_678 @[el2_lib.scala 511:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_679 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_679 <= _T_676 @[el2_lib.scala 514:16] + buf_data <= _T_679 @[axi4_to_ahb.scala 423:12] + node _T_680 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 426:50] + reg _T_681 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_680 : @[Reg.scala 28:19] + _T_681 <= buf_write @[Reg.scala 28:23] skip @[Reg.scala 28:19] - slvbuf_error <= _T_677 @[axi4_to_ahb.scala 423:16] - node _T_678 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 428:32] - node _T_679 = mux(_T_678, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 428:16] - node _T_680 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 428:52] - node _T_681 = and(_T_679, _T_680) @[axi4_to_ahb.scala 428:50] - reg _T_682 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 428:12] - _T_682 <= _T_681 @[axi4_to_ahb.scala 428:12] - cmd_doneQ <= _T_682 @[axi4_to_ahb.scala 427:13] - node _T_683 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 432:31] - node _T_684 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 432:70] - reg _T_685 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_684 : @[Reg.scala 28:19] - _T_685 <= _T_683 @[Reg.scala 28:23] + slvbuf_write <= _T_681 @[axi4_to_ahb.scala 425:16] + node _T_682 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 429:22] + node _T_683 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 429:60] + reg _T_684 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_683 : @[Reg.scala 28:19] + _T_684 <= _T_682 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_cmd_byte_ptrQ <= _T_685 @[axi4_to_ahb.scala 431:21] - reg _T_686 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 437:12] - _T_686 <= io.ahb_hready @[axi4_to_ahb.scala 437:12] - ahb_hready_q <= _T_686 @[axi4_to_ahb.scala 436:16] - node _T_687 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 440:26] - reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 440:12] - _T_688 <= _T_687 @[axi4_to_ahb.scala 440:12] - ahb_htrans_q <= _T_688 @[axi4_to_ahb.scala 439:16] - reg _T_689 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 443:12] - _T_689 <= io.ahb_hwrite @[axi4_to_ahb.scala 443:12] - ahb_hwrite_q <= _T_689 @[axi4_to_ahb.scala 442:16] - reg _T_690 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 446:12] - _T_690 <= io.ahb_hresp @[axi4_to_ahb.scala 446:12] - ahb_hresp_q <= _T_690 @[axi4_to_ahb.scala 445:15] - node _T_691 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 449:26] - reg _T_692 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 449:12] - _T_692 <= _T_691 @[axi4_to_ahb.scala 449:12] - ahb_hrdata_q <= _T_692 @[axi4_to_ahb.scala 448:16] - node _T_693 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 452:43] - node _T_694 = or(_T_693, io.clk_override) @[axi4_to_ahb.scala 452:58] - node _T_695 = and(io.bus_clk_en, _T_694) @[axi4_to_ahb.scala 452:30] - buf_clken <= _T_695 @[axi4_to_ahb.scala 452:13] - node _T_696 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 453:69] - node _T_697 = and(io.ahb_hready, _T_696) @[axi4_to_ahb.scala 453:54] - node _T_698 = or(_T_697, io.clk_override) @[axi4_to_ahb.scala 453:74] - node _T_699 = and(io.bus_clk_en, _T_698) @[axi4_to_ahb.scala 453:36] - ahbm_addr_clken <= _T_699 @[axi4_to_ahb.scala 453:19] - node _T_700 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 454:50] - node _T_701 = or(_T_700, io.clk_override) @[axi4_to_ahb.scala 454:60] - node _T_702 = and(io.bus_clk_en, _T_701) @[axi4_to_ahb.scala 454:36] - ahbm_data_clken <= _T_702 @[axi4_to_ahb.scala 454:19] + slvbuf_tag <= _T_684 @[axi4_to_ahb.scala 428:14] + node _T_685 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 432:59] + reg _T_686 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_685 : @[Reg.scala 28:19] + _T_686 <= slvbuf_error_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_error <= _T_686 @[axi4_to_ahb.scala 431:16] + node _T_687 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 436:32] + node _T_688 = mux(_T_687, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 436:16] + node _T_689 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 436:52] + node _T_690 = and(_T_688, _T_689) @[axi4_to_ahb.scala 436:50] + reg _T_691 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 436:12] + _T_691 <= _T_690 @[axi4_to_ahb.scala 436:12] + cmd_doneQ <= _T_691 @[axi4_to_ahb.scala 435:13] + node _T_692 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 440:31] + node _T_693 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 440:70] + reg _T_694 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_693 : @[Reg.scala 28:19] + _T_694 <= _T_692 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_cmd_byte_ptrQ <= _T_694 @[axi4_to_ahb.scala 439:21] + reg _T_695 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 445:12] + _T_695 <= io.ahb_hready @[axi4_to_ahb.scala 445:12] + ahb_hready_q <= _T_695 @[axi4_to_ahb.scala 444:16] + node _T_696 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 448:26] + reg _T_697 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 448:12] + _T_697 <= _T_696 @[axi4_to_ahb.scala 448:12] + ahb_htrans_q <= _T_697 @[axi4_to_ahb.scala 447:16] + reg _T_698 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 451:12] + _T_698 <= io.ahb_hwrite @[axi4_to_ahb.scala 451:12] + ahb_hwrite_q <= _T_698 @[axi4_to_ahb.scala 450:16] + reg _T_699 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 454:12] + _T_699 <= io.ahb_hresp @[axi4_to_ahb.scala 454:12] + ahb_hresp_q <= _T_699 @[axi4_to_ahb.scala 453:15] + node _T_700 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 457:26] + reg _T_701 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 457:12] + _T_701 <= _T_700 @[axi4_to_ahb.scala 457:12] + ahb_hrdata_q <= _T_701 @[axi4_to_ahb.scala 456:16] + node _T_702 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 460:43] + node _T_703 = or(_T_702, io.clk_override) @[axi4_to_ahb.scala 460:58] + node _T_704 = and(io.bus_clk_en, _T_703) @[axi4_to_ahb.scala 460:30] + buf_clken <= _T_704 @[axi4_to_ahb.scala 460:13] + node _T_705 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 461:69] + node _T_706 = and(io.ahb_hready, _T_705) @[axi4_to_ahb.scala 461:54] + node _T_707 = or(_T_706, io.clk_override) @[axi4_to_ahb.scala 461:74] + node _T_708 = and(io.bus_clk_en, _T_707) @[axi4_to_ahb.scala 461:36] + ahbm_addr_clken <= _T_708 @[axi4_to_ahb.scala 461:19] + node _T_709 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 462:50] + node _T_710 = or(_T_709, io.clk_override) @[axi4_to_ahb.scala 462:60] + node _T_711 = and(io.bus_clk_en, _T_710) @[axi4_to_ahb.scala 462:36] + ahbm_data_clken <= _T_711 @[axi4_to_ahb.scala 462:19] inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 483:22] rvclkhdr_6.clock <= clock rvclkhdr_6.reset <= reset rvclkhdr_6.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_6.io.en <= buf_clken @[el2_lib.scala 485:16] rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 457:12] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 465:12] inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 483:22] rvclkhdr_7.clock <= clock rvclkhdr_7.reset <= reset rvclkhdr_7.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_7.io.en <= io.bus_clk_en @[el2_lib.scala 485:16] rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 458:12] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 466:12] inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 483:22] rvclkhdr_8.clock <= clock rvclkhdr_8.reset <= reset rvclkhdr_8.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_8.io.en <= ahbm_addr_clken @[el2_lib.scala 485:16] rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 459:17] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 467:17] inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 483:22] rvclkhdr_9.clock <= clock rvclkhdr_9.reset <= reset rvclkhdr_9.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_9.io.en <= ahbm_data_clken @[el2_lib.scala 485:16] rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 460:17] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 468:17] diff --git a/axi4_to_ahb.v b/axi4_to_ahb.v index 92e36f7b..151c9dd1 100644 --- a/axi4_to_ahb.v +++ b/axi4_to_ahb.v @@ -65,7 +65,7 @@ module axi4_to_ahb( output [63:0] io_ahb_hwdata ); `ifdef RANDOMIZE_REG_INIT - reg [63:0] _RAND_0; + reg [31:0] _RAND_0; reg [31:0] _RAND_1; reg [31:0] _RAND_2; reg [31:0] _RAND_3; @@ -75,13 +75,22 @@ module axi4_to_ahb( reg [31:0] _RAND_7; reg [31:0] _RAND_8; reg [31:0] _RAND_9; - reg [63:0] _RAND_10; - reg [63:0] _RAND_11; - reg [31:0] _RAND_12; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [63:0] _RAND_12; reg [31:0] _RAND_13; reg [31:0] _RAND_14; reg [31:0] _RAND_15; reg [31:0] _RAND_16; + reg [63:0] _RAND_17; + reg [63:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; `endif // RANDOMIZE_REG_INIT wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] @@ -123,220 +132,348 @@ module axi4_to_ahb( wire rvclkhdr_9_io_clk; // @[el2_lib.scala 483:22] wire rvclkhdr_9_io_en; // @[el2_lib.scala 483:22] wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 483:22] + wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 62:22 axi4_to_ahb.scala 466:12] + reg [2:0] buf_state; // @[axi4_to_ahb.scala 69:12] + wire _T_47 = 3'h0 == buf_state; // @[Conditional.scala 37:30] + wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 90:21 axi4_to_ahb.scala 223:11] + reg wrbuf_vld; // @[axi4_to_ahb.scala 384:48] + reg wrbuf_data_vld; // @[axi4_to_ahb.scala 385:48] + wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 200:27] + wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 201:30] + wire _T_99 = 3'h1 == buf_state; // @[Conditional.scala 37:30] + reg ahb_hready_q; // @[axi4_to_ahb.scala 445:12] + reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 448:12] + wire _T_106 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 263:58] + wire _T_107 = ahb_hready_q & _T_106; // @[axi4_to_ahb.scala 263:36] + wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 63:27 axi4_to_ahb.scala 467:17] + reg ahb_hwrite_q; // @[axi4_to_ahb.scala 451:12] + wire _T_108 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 263:72] + wire _T_109 = _T_107 & _T_108; // @[axi4_to_ahb.scala 263:70] + wire _T_134 = 3'h6 == buf_state; // @[Conditional.scala 37:30] + reg ahb_hresp_q; // @[axi4_to_ahb.scala 454:12] + wire _T_150 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 277:37] + wire _T_173 = 3'h7 == buf_state; // @[Conditional.scala 37:30] + wire _T_184 = 3'h3 == buf_state; // @[Conditional.scala 37:30] + wire _T_186 = 3'h2 == buf_state; // @[Conditional.scala 37:30] + wire _T_187 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 309:33] + wire _T_190 = _T_187 & _T_106; // @[axi4_to_ahb.scala 309:48] + wire _T_279 = 3'h4 == buf_state; // @[Conditional.scala 37:30] + wire _GEN_15 = _T_279 & _T_190; // @[Conditional.scala 39:67] + wire _GEN_19 = _T_186 ? _T_190 : _GEN_15; // @[Conditional.scala 39:67] + wire _GEN_40 = _T_184 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_173 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] + wire _GEN_78 = _T_134 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] + wire _GEN_94 = _T_99 ? 1'h0 : _GEN_78; // @[Conditional.scala 39:67] + wire trxn_done = _T_47 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] + reg cmd_doneQ; // @[axi4_to_ahb.scala 436:12] + wire _T_280 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 319:34] + wire _T_281 = _T_280 | ahb_hresp_q; // @[axi4_to_ahb.scala 319:50] + wire _T_442 = 3'h5 == buf_state; // @[Conditional.scala 37:30] + wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 218:32] + wire _GEN_1 = _T_442 & slave_ready; // @[Conditional.scala 39:67] + wire _GEN_3 = _T_279 ? _T_281 : _GEN_1; // @[Conditional.scala 39:67] + wire _GEN_20 = _T_186 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] + wire _GEN_35 = _T_184 ? _T_150 : _GEN_20; // @[Conditional.scala 39:67] + wire _GEN_51 = _T_173 ? _T_109 : _GEN_35; // @[Conditional.scala 39:67] + wire _GEN_68 = _T_134 ? _T_150 : _GEN_51; // @[Conditional.scala 39:67] + wire _GEN_83 = _T_99 ? _T_109 : _GEN_68; // @[Conditional.scala 39:67] + wire buf_state_en = _T_47 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] + wire [1:0] _T_12 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 203:20] + wire [2:0] master_opc = {{1'd0}, _T_12}; // @[axi4_to_ahb.scala 203:14] + wire _T_49 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 248:41] + wire _GEN_8 = _T_279 & _T_49; // @[Conditional.scala 39:67] + wire _GEN_29 = _T_186 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] + wire _GEN_46 = _T_184 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_63 = _T_173 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_80 = _T_134 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] + wire _GEN_96 = _T_99 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] + wire buf_write_in = _T_47 ? _T_49 : _GEN_96; // @[Conditional.scala 40:58] + wire [2:0] _T_51 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 249:26] + wire _T_101 = master_opc == 3'h0; // @[axi4_to_ahb.scala 262:61] + wire _T_102 = master_valid & _T_101; // @[axi4_to_ahb.scala 262:41] + wire [2:0] _T_104 = _T_102 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 262:26] + wire _T_122 = _T_104 == 3'h6; // @[axi4_to_ahb.scala 266:174] + wire _T_123 = _T_109 & _T_122; // @[axi4_to_ahb.scala 266:88] + wire _T_135 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 274:39] + wire _T_136 = ahb_hready_q & _T_135; // @[axi4_to_ahb.scala 274:37] + wire _T_139 = master_valid & _T_49; // @[axi4_to_ahb.scala 274:70] + wire _T_140 = ~_T_139; // @[axi4_to_ahb.scala 274:55] + wire _T_141 = _T_136 & _T_140; // @[axi4_to_ahb.scala 274:53] + wire _T_285 = _T_281 & _T_135; // @[axi4_to_ahb.scala 320:66] + wire _T_286 = _T_285 & slave_ready; // @[axi4_to_ahb.scala 320:81] + wire _GEN_4 = _T_279 ? _T_286 : 1'h1; // @[Conditional.scala 39:67] + wire _GEN_26 = _T_186 | _GEN_4; // @[Conditional.scala 39:67] + wire _GEN_45 = _T_184 | _GEN_26; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_173 | _GEN_45; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_134 ? _T_141 : _GEN_62; // @[Conditional.scala 39:67] + wire _GEN_86 = _T_99 ? _T_123 : _GEN_66; // @[Conditional.scala 39:67] + wire master_ready = _T_47 | _GEN_86; // @[Conditional.scala 40:58] + wire _T_143 = master_valid & master_ready; // @[axi4_to_ahb.scala 276:82] + wire _T_146 = _T_143 & _T_101; // @[axi4_to_ahb.scala 276:97] + wire [2:0] _T_148 = _T_146 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 276:67] + wire [2:0] _T_149 = ahb_hresp_q ? 3'h7 : _T_148; // @[axi4_to_ahb.scala 276:26] + wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 321:42] + wire _T_288 = ahb_hresp_q | _T_287; // @[axi4_to_ahb.scala 321:40] + wire [2:0] _T_294 = _T_49 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 321:119] + wire [2:0] _T_295 = _T_143 ? _T_294 : 3'h0; // @[axi4_to_ahb.scala 321:75] + wire [2:0] _T_296 = _T_288 ? 3'h5 : _T_295; // @[axi4_to_ahb.scala 321:26] + wire [2:0] _GEN_5 = _T_279 ? _T_296 : 3'h0; // @[Conditional.scala 39:67] + wire [2:0] _GEN_18 = _T_186 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] + wire [2:0] _GEN_34 = _T_184 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] + wire [2:0] _GEN_50 = _T_173 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67] + wire [2:0] _GEN_67 = _T_134 ? _T_149 : _GEN_50; // @[Conditional.scala 39:67] + wire [2:0] _GEN_82 = _T_99 ? _T_104 : _GEN_67; // @[Conditional.scala 39:67] + wire [2:0] buf_nxtstate = _T_47 ? _T_51 : _GEN_82; // @[Conditional.scala 40:58] + wire [2:0] _T_1 = buf_state_en ? buf_nxtstate : buf_state; // @[axi4_to_ahb.scala 69:16] + reg wrbuf_tag; // @[Reg.scala 27:20] + reg [31:0] wrbuf_addr; // @[el2_lib.scala 514:16] + wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_araddr; // @[axi4_to_ahb.scala 204:21] + reg [2:0] wrbuf_size; // @[Reg.scala 27:20] + wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_arsize; // @[axi4_to_ahb.scala 205:21] + reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] reg [63:0] wrbuf_data; // @[el2_lib.scala 514:16] - wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 152:22 axi4_to_ahb.scala 458:12] - reg [2:0] buf_state; // @[axi4_to_ahb.scala 393:12] - wire _T_42 = 3'h0 == buf_state; // @[Conditional.scala 37:30] - wire _T_94 = 3'h1 == buf_state; // @[Conditional.scala 37:30] - wire _T_124 = 3'h6 == buf_state; // @[Conditional.scala 37:30] - reg ahb_hready_q; // @[axi4_to_ahb.scala 437:12] - reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 440:12] - wire _T_101 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 255:58] - wire _T_102 = ahb_hready_q & _T_101; // @[axi4_to_ahb.scala 255:36] - wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 153:27 axi4_to_ahb.scala 459:17] - reg ahb_hwrite_q; // @[axi4_to_ahb.scala 443:12] - wire _T_103 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 255:72] - wire _T_104 = _T_102 & _T_103; // @[axi4_to_ahb.scala 255:70] - reg ahb_hresp_q; // @[axi4_to_ahb.scala 446:12] - wire _T_140 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 269:37] - wire _T_159 = 3'h7 == buf_state; // @[Conditional.scala 37:30] - wire _T_170 = 3'h3 == buf_state; // @[Conditional.scala 37:30] - wire _T_172 = 3'h2 == buf_state; // @[Conditional.scala 37:30] - wire _T_173 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 301:33] - wire _T_176 = _T_173 & _T_101; // @[axi4_to_ahb.scala 301:48] - wire _T_265 = 3'h4 == buf_state; // @[Conditional.scala 37:30] - wire _GEN_14 = _T_265 & _T_176; // @[Conditional.scala 39:67] - wire _GEN_18 = _T_172 ? _T_176 : _GEN_14; // @[Conditional.scala 39:67] - wire _GEN_38 = _T_170 ? 1'h0 : _GEN_18; // @[Conditional.scala 39:67] - wire _GEN_56 = _T_159 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] - wire _GEN_74 = _T_124 ? 1'h0 : _GEN_56; // @[Conditional.scala 39:67] - wire _GEN_89 = _T_94 ? 1'h0 : _GEN_74; // @[Conditional.scala 39:67] - wire trxn_done = _T_42 ? 1'h0 : _GEN_89; // @[Conditional.scala 40:58] - reg cmd_doneQ; // @[axi4_to_ahb.scala 428:12] - wire _T_266 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 311:34] - wire _T_267 = _T_266 | ahb_hresp_q; // @[axi4_to_ahb.scala 311:50] - wire _T_428 = 3'h5 == buf_state; // @[Conditional.scala 37:30] - wire slave_ready = io_axi_bready & io_axi_rready; // @[axi4_to_ahb.scala 210:32] - wire _GEN_1 = _T_428 & slave_ready; // @[Conditional.scala 39:67] - wire _GEN_3 = _T_265 ? _T_267 : _GEN_1; // @[Conditional.scala 39:67] - wire _GEN_19 = _T_172 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] - wire _GEN_33 = _T_170 ? _T_140 : _GEN_19; // @[Conditional.scala 39:67] - wire _GEN_48 = _T_159 ? _T_104 : _GEN_33; // @[Conditional.scala 39:67] - wire _GEN_63 = _T_124 ? _T_140 : _GEN_48; // @[Conditional.scala 39:67] - wire _GEN_77 = _T_94 ? _T_104 : _GEN_63; // @[Conditional.scala 39:67] - wire buf_state_en = _T_42 ? io_axi_arvalid : _GEN_77; // @[Conditional.scala 40:58] - wire _T_141 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 273:41] - wire _T_142 = buf_state_en & _T_141; // @[axi4_to_ahb.scala 273:39] - wire _T_273 = ~slave_ready; // @[axi4_to_ahb.scala 313:42] - wire _T_274 = ahb_hresp_q | _T_273; // @[axi4_to_ahb.scala 313:40] - wire _T_271 = _T_267 & _T_141; // @[axi4_to_ahb.scala 312:68] - wire _T_272 = _T_271 & slave_ready; // @[axi4_to_ahb.scala 312:83] - wire _T_276 = io_axi_arvalid & _T_272; // @[axi4_to_ahb.scala 313:90] - wire [2:0] _T_281 = _T_276 ? 3'h1 : 3'h0; // @[axi4_to_ahb.scala 313:75] - wire [2:0] _T_282 = _T_274 ? 3'h5 : _T_281; // @[axi4_to_ahb.scala 313:26] - wire [2:0] _GEN_4 = _T_265 ? _T_282 : 3'h0; // @[Conditional.scala 39:67] - wire [2:0] _GEN_17 = _T_172 ? 3'h4 : _GEN_4; // @[Conditional.scala 39:67] - wire [2:0] _GEN_32 = _T_170 ? 3'h5 : _GEN_17; // @[Conditional.scala 39:67] - wire [2:0] _GEN_47 = _T_159 ? 3'h3 : _GEN_32; // @[Conditional.scala 39:67] - wire [2:0] _GEN_73 = _T_124 ? 3'h0 : _GEN_47; // @[Conditional.scala 39:67] - wire [2:0] _GEN_88 = _T_94 ? 3'h0 : _GEN_73; // @[Conditional.scala 39:67] - wire [2:0] buf_nxtstate = _T_42 ? 3'h0 : _GEN_88; // @[Conditional.scala 40:58] - wire _T_345 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 322:55] - wire _T_346 = buf_state_en & _T_345; // @[axi4_to_ahb.scala 322:39] - wire _GEN_13 = _T_265 ? _T_346 : _T_428; // @[Conditional.scala 39:67] - wire _GEN_31 = _T_172 ? 1'h0 : _GEN_13; // @[Conditional.scala 39:67] - wire _GEN_46 = _T_170 ? 1'h0 : _GEN_31; // @[Conditional.scala 39:67] - wire _GEN_49 = _T_159 ? buf_state_en : _GEN_46; // @[Conditional.scala 39:67] - wire _GEN_67 = _T_124 ? _T_142 : _GEN_49; // @[Conditional.scala 39:67] - wire _GEN_87 = _T_94 ? 1'h0 : _GEN_67; // @[Conditional.scala 39:67] - wire slave_valid_pre = _T_42 ? 1'h0 : _GEN_87; // @[Conditional.scala 40:58] - wire _T_18 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 202:32] - wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 150:21 axi4_to_ahb.scala 457:12] + wire _T_152 = buf_state_en & _T_135; // @[axi4_to_ahb.scala 281:39] + wire _T_359 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 330:55] + wire _T_360 = buf_state_en & _T_359; // @[axi4_to_ahb.scala 330:39] + wire _GEN_14 = _T_279 ? _T_360 : _T_442; // @[Conditional.scala 39:67] + wire _GEN_33 = _T_186 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] + wire _GEN_49 = _T_184 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] + wire _GEN_52 = _T_173 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] + wire _GEN_72 = _T_134 ? _T_152 : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_93 = _T_99 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] + wire slave_valid_pre = _T_47 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] + wire _T_23 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 210:32] + wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 158:21 axi4_to_ahb.scala 465:12] + reg slvbuf_write; // @[Reg.scala 27:20] + wire [1:0] _T_594 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 367:23] reg slvbuf_error; // @[Reg.scala 27:20] - wire [1:0] _T_582 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_583 = _T_582 & 2'h2; // @[axi4_to_ahb.scala 359:88] - wire [3:0] slave_opc = {2'h0,_T_583}; // @[Cat.scala 29:58] - wire [1:0] _T_23 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 203:49] + wire [1:0] _T_596 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_597 = _T_596 & 2'h2; // @[axi4_to_ahb.scala 367:88] + wire [3:0] slave_opc = {_T_594,_T_597}; // @[Cat.scala 29:58] + wire [1:0] _T_28 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 211:49] reg slvbuf_tag; // @[Reg.scala 27:20] - wire _T_28 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 206:65] + wire _T_33 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 214:65] reg [31:0] last_bus_addr; // @[Reg.scala 27:20] - wire [63:0] _T_587 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] - wire _T_588 = buf_state == 3'h5; // @[axi4_to_ahb.scala 360:91] + wire [63:0] _T_601 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] + wire _T_602 = buf_state == 3'h5; // @[axi4_to_ahb.scala 368:91] reg [63:0] buf_data; // @[el2_lib.scala 514:16] - wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 154:27 axi4_to_ahb.scala 460:17] - reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 449:12] - wire [63:0] _T_591 = _T_588 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 360:79] - wire _T_37 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 213:56] - wire _T_38 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 213:91] - wire _T_39 = _T_37 | _T_38; // @[axi4_to_ahb.scala 213:74] - wire [2:0] _T_99 = io_axi_arvalid ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 254:28] - wire _T_112 = _T_99 == 3'h6; // @[axi4_to_ahb.scala 258:107] - wire _T_113 = _T_104 & _T_112; // @[axi4_to_ahb.scala 258:91] - wire _T_114 = _T_113 & io_axi_arvalid; // @[axi4_to_ahb.scala 260:33] - wire _T_126 = ahb_hready_q & _T_141; // @[axi4_to_ahb.scala 266:39] - wire _T_145 = _T_126 & io_axi_arvalid; // @[axi4_to_ahb.scala 275:33] - wire _T_132 = io_axi_arvalid & _T_126; // @[axi4_to_ahb.scala 267:34] - wire _T_285 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 317:50] - wire _T_286 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 317:78] - wire _T_287 = _T_285 | _T_286; // @[axi4_to_ahb.scala 317:62] - wire _T_288 = buf_state_en & _T_287; // @[axi4_to_ahb.scala 317:33] - wire _GEN_8 = _T_265 & _T_288; // @[Conditional.scala 39:67] - wire _GEN_28 = _T_172 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] - wire _GEN_44 = _T_170 ? 1'h0 : _GEN_28; // @[Conditional.scala 39:67] - wire _GEN_60 = _T_159 ? 1'h0 : _GEN_44; // @[Conditional.scala 39:67] - wire _GEN_62 = _T_124 ? _T_132 : _GEN_60; // @[Conditional.scala 39:67] - wire _GEN_80 = _T_94 ? _T_113 : _GEN_62; // @[Conditional.scala 39:67] - wire buf_wr_en = _T_42 ? buf_state_en : _GEN_80; // @[Conditional.scala 40:58] - wire [2:0] _T_138 = buf_wr_en ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 268:69] - wire [2:0] _T_139 = ahb_hresp_q ? 3'h7 : _T_138; // @[axi4_to_ahb.scala 268:28] - wire _T_146 = _T_139 == 3'h6; // @[axi4_to_ahb.scala 275:64] - wire _T_147 = _T_145 & _T_146; // @[axi4_to_ahb.scala 275:48] - wire _T_148 = _T_147 & buf_state_en; // @[axi4_to_ahb.scala 275:79] - wire _GEN_69 = _T_124 & _T_148; // @[Conditional.scala 39:67] - wire _GEN_81 = _T_94 ? _T_114 : _GEN_69; // @[Conditional.scala 39:67] - wire bypass_en = _T_42 ? buf_state_en : _GEN_81; // @[Conditional.scala 40:58] - wire [1:0] _T_92 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_93 = _T_92 & 2'h2; // @[axi4_to_ahb.scala 250:45] - wire _T_105 = ~io_axi_arvalid; // @[axi4_to_ahb.scala 256:34] - wire _T_106 = buf_state_en & _T_105; // @[axi4_to_ahb.scala 256:32] + wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 64:27 axi4_to_ahb.scala 468:17] + reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 457:12] + wire [63:0] _T_605 = _T_602 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 368:79] + wire _T_42 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 221:56] + wire _T_43 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 221:91] + wire _T_44 = _T_42 | _T_43; // @[axi4_to_ahb.scala 221:74] + wire _T_53 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 252:54] + wire _T_54 = buf_state_en & _T_53; // @[axi4_to_ahb.scala 252:38] + wire [2:0] _T_84 = wrbuf_byteen[7] ? 3'h7 : 3'h0; // @[Mux.scala 98:16] + wire [2:0] _T_85 = wrbuf_byteen[6] ? 3'h6 : _T_84; // @[Mux.scala 98:16] + wire [2:0] _T_86 = wrbuf_byteen[5] ? 3'h5 : _T_85; // @[Mux.scala 98:16] + wire [2:0] _T_87 = wrbuf_byteen[4] ? 3'h4 : _T_86; // @[Mux.scala 98:16] + wire [2:0] _T_88 = wrbuf_byteen[3] ? 3'h3 : _T_87; // @[Mux.scala 98:16] + wire [2:0] _T_89 = wrbuf_byteen[2] ? 3'h2 : _T_88; // @[Mux.scala 98:16] + wire [2:0] _T_90 = wrbuf_byteen[1] ? 3'h1 : _T_89; // @[Mux.scala 98:16] + wire [2:0] _T_91 = wrbuf_byteen[0] ? 3'h0 : _T_90; // @[Mux.scala 98:16] + wire [2:0] _T_93 = buf_write_in ? _T_91 : master_addr[2:0]; // @[axi4_to_ahb.scala 255:30] + wire _T_94 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 257:51] + wire _T_124 = master_ready & master_valid; // @[axi4_to_ahb.scala 268:33] + wire _T_156 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 283:64] + wire _T_157 = _T_124 & _T_156; // @[axi4_to_ahb.scala 283:48] + wire _T_158 = _T_157 & buf_state_en; // @[axi4_to_ahb.scala 283:79] + wire _T_350 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 328:33] + wire _T_352 = _T_350 & _T_53; // @[axi4_to_ahb.scala 328:48] + wire _GEN_12 = _T_279 & _T_352; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_186 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] + wire _GEN_48 = _T_184 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_65 = _T_173 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_134 ? _T_158 : _GEN_65; // @[Conditional.scala 39:67] + wire _GEN_87 = _T_99 ? _T_124 : _GEN_74; // @[Conditional.scala 39:67] + wire bypass_en = _T_47 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58] + wire [1:0] _T_97 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_98 = _T_97 & 2'h2; // @[axi4_to_ahb.scala 258:45] + wire _T_110 = ~master_valid; // @[axi4_to_ahb.scala 264:34] + wire _T_111 = buf_state_en & _T_110; // @[axi4_to_ahb.scala 264:32] reg [31:0] buf_addr; // @[el2_lib.scala 514:16] - wire [2:0] _T_118 = bypass_en ? io_axi_araddr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 261:30] - wire _T_119 = ~buf_state_en; // @[axi4_to_ahb.scala 262:44] - wire _T_120 = _T_119 | bypass_en; // @[axi4_to_ahb.scala 262:58] - wire [1:0] _T_122 = _T_120 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_123 = 2'h2 & _T_122; // @[axi4_to_ahb.scala 262:32] - wire _T_153 = _T_139 != 3'h6; // @[axi4_to_ahb.scala 277:59] - wire _T_154 = _T_153 & buf_state_en; // @[axi4_to_ahb.scala 277:74] - wire _T_155 = ~_T_154; // @[axi4_to_ahb.scala 277:43] - wire [1:0] _T_157 = _T_155 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_158 = 2'h2 & _T_157; // @[axi4_to_ahb.scala 277:32] - wire [1:0] _T_168 = _T_119 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_169 = 2'h2 & _T_168; // @[axi4_to_ahb.scala 287:37] + wire [2:0] _T_128 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 269:30] + wire _T_129 = ~buf_state_en; // @[axi4_to_ahb.scala 270:44] + wire _T_130 = _T_129 | bypass_en; // @[axi4_to_ahb.scala 270:58] + wire [1:0] _T_132 = _T_130 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_133 = 2'h2 & _T_132; // @[axi4_to_ahb.scala 270:32] + wire _T_163 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 285:59] + wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 285:74] + wire _T_165 = ~_T_164; // @[axi4_to_ahb.scala 285:43] + wire [1:0] _T_167 = _T_165 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_168 = 2'h2 & _T_167; // @[axi4_to_ahb.scala 285:32] + wire [1:0] _T_182 = _T_129 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_183 = 2'h2 & _T_182; // @[axi4_to_ahb.scala 295:37] reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] - wire [2:0] _T_215 = trxn_done ? 3'h0 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 305:30] + reg [7:0] buf_byteen; // @[Reg.scala 27:20] + wire [2:0] _T_195 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 184:52] + wire _T_198 = 3'h0 >= _T_195; // @[axi4_to_ahb.scala 185:62] + wire _T_199 = buf_byteen[0] & _T_198; // @[axi4_to_ahb.scala 185:48] + wire _T_201 = 3'h1 >= _T_195; // @[axi4_to_ahb.scala 185:62] + wire _T_202 = buf_byteen[1] & _T_201; // @[axi4_to_ahb.scala 185:48] + wire _T_204 = 3'h2 >= _T_195; // @[axi4_to_ahb.scala 185:62] + wire _T_205 = buf_byteen[2] & _T_204; // @[axi4_to_ahb.scala 185:48] + wire _T_207 = 3'h3 >= _T_195; // @[axi4_to_ahb.scala 185:62] + wire _T_208 = buf_byteen[3] & _T_207; // @[axi4_to_ahb.scala 185:48] + wire _T_210 = 3'h4 >= _T_195; // @[axi4_to_ahb.scala 185:62] + wire _T_211 = buf_byteen[4] & _T_210; // @[axi4_to_ahb.scala 185:48] + wire _T_213 = 3'h5 >= _T_195; // @[axi4_to_ahb.scala 185:62] + wire _T_214 = buf_byteen[5] & _T_213; // @[axi4_to_ahb.scala 185:48] + wire _T_216 = 3'h6 >= _T_195; // @[axi4_to_ahb.scala 185:62] + wire _T_217 = buf_byteen[6] & _T_216; // @[axi4_to_ahb.scala 185:48] + wire [2:0] _T_221 = buf_byteen[7] ? 3'h7 : 3'h0; // @[Mux.scala 98:16] + wire [2:0] _T_222 = _T_217 ? 3'h6 : _T_221; // @[Mux.scala 98:16] + wire [2:0] _T_223 = _T_214 ? 3'h5 : _T_222; // @[Mux.scala 98:16] + wire [2:0] _T_224 = _T_211 ? 3'h4 : _T_223; // @[Mux.scala 98:16] + wire [2:0] _T_225 = _T_208 ? 3'h3 : _T_224; // @[Mux.scala 98:16] + wire [2:0] _T_226 = _T_205 ? 3'h2 : _T_225; // @[Mux.scala 98:16] + wire [2:0] _T_227 = _T_202 ? 3'h1 : _T_226; // @[Mux.scala 98:16] + wire [2:0] _T_228 = _T_199 ? 3'h0 : _T_227; // @[Mux.scala 98:16] + wire [2:0] _T_229 = trxn_done ? _T_228 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 313:30] + wire _T_230 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 314:65] reg buf_aligned; // @[Reg.scala 27:20] - wire _T_335 = ahb_hresp_q | _T_102; // @[axi4_to_ahb.scala 319:32] - wire _GEN_10 = _T_265 & _T_335; // @[Conditional.scala 39:67] - wire _GEN_23 = _T_172 ? trxn_done : _GEN_10; // @[Conditional.scala 39:67] - wire _GEN_41 = _T_170 ? 1'h0 : _GEN_23; // @[Conditional.scala 39:67] - wire _GEN_58 = _T_159 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] - wire _GEN_68 = _T_124 ? _T_106 : _GEN_58; // @[Conditional.scala 39:67] - wire _GEN_78 = _T_94 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] - wire cmd_done = _T_42 ? 1'h0 : _GEN_78; // @[Conditional.scala 40:58] - wire _T_260 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 307:43] - wire _T_261 = ~_T_260; // @[axi4_to_ahb.scala 307:32] - wire [1:0] _T_263 = _T_261 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_264 = _T_263 & 2'h2; // @[axi4_to_ahb.scala 307:57] - wire _T_341 = _T_261 | bypass_en; // @[axi4_to_ahb.scala 321:57] - wire [1:0] _T_343 = _T_341 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] _T_344 = _T_343 & 2'h2; // @[axi4_to_ahb.scala 321:71] - wire _T_351 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 324:40] - wire [2:0] _T_427 = bypass_en ? 3'h0 : _T_215; // @[axi4_to_ahb.scala 327:30] - wire _GEN_5 = _T_265 & ahb_hresp_q; // @[Conditional.scala 39:67] - wire _GEN_6 = _T_265 ? buf_state_en : _T_428; // @[Conditional.scala 39:67] - wire _GEN_9 = _T_265 & buf_wr_en; // @[Conditional.scala 39:67] - wire [1:0] _GEN_12 = _T_265 ? _T_344 : 2'h0; // @[Conditional.scala 39:67] - wire _GEN_15 = _T_265 & _T_351; // @[Conditional.scala 39:67] - wire [2:0] _GEN_16 = _T_265 ? _T_427 : 3'h0; // @[Conditional.scala 39:67] - wire _GEN_20 = _T_172 ? buf_state_en : _GEN_15; // @[Conditional.scala 39:67] - wire _GEN_21 = _T_172 & buf_state_en; // @[Conditional.scala 39:67] - wire [2:0] _GEN_22 = _T_172 ? _T_215 : _GEN_16; // @[Conditional.scala 39:67] - wire [1:0] _GEN_24 = _T_172 ? _T_264 : _GEN_12; // @[Conditional.scala 39:67] - wire _GEN_26 = _T_172 ? 1'h0 : _GEN_6; // @[Conditional.scala 39:67] - wire _GEN_29 = _T_172 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] - wire _GEN_34 = _T_170 ? buf_state_en : _GEN_29; // @[Conditional.scala 39:67] - wire _GEN_36 = _T_170 ? buf_state_en : _GEN_26; // @[Conditional.scala 39:67] - wire _GEN_37 = _T_170 ? buf_state_en : _GEN_21; // @[Conditional.scala 39:67] - wire _GEN_39 = _T_170 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67] - wire [2:0] _GEN_40 = _T_170 ? 3'h0 : _GEN_22; // @[Conditional.scala 39:67] - wire [1:0] _GEN_42 = _T_170 ? 2'h0 : _GEN_24; // @[Conditional.scala 39:67] - wire _GEN_50 = _T_159 ? buf_state_en : _GEN_37; // @[Conditional.scala 39:67] - wire [2:0] _GEN_51 = _T_159 ? buf_addr[2:0] : _GEN_40; // @[Conditional.scala 39:67] - wire [1:0] _GEN_52 = _T_159 ? _T_169 : _GEN_42; // @[Conditional.scala 39:67] - wire _GEN_53 = _T_159 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67] - wire _GEN_55 = _T_159 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] - wire _GEN_57 = _T_159 ? 1'h0 : _GEN_39; // @[Conditional.scala 39:67] - wire _GEN_64 = _T_124 ? buf_state_en : _GEN_53; // @[Conditional.scala 39:67] - wire _GEN_66 = _T_124 ? buf_state_en : _GEN_55; // @[Conditional.scala 39:67] - wire [2:0] _GEN_70 = _T_124 ? _T_118 : _GEN_51; // @[Conditional.scala 39:67] - wire [1:0] _GEN_71 = _T_124 ? _T_158 : _GEN_52; // @[Conditional.scala 39:67] - wire _GEN_72 = _T_124 ? buf_wr_en : _GEN_50; // @[Conditional.scala 39:67] - wire _GEN_75 = _T_124 ? 1'h0 : _GEN_57; // @[Conditional.scala 39:67] - wire _GEN_79 = _T_94 ? buf_state_en : _GEN_72; // @[Conditional.scala 39:67] - wire [2:0] _GEN_82 = _T_94 ? _T_118 : _GEN_70; // @[Conditional.scala 39:67] - wire [1:0] _GEN_83 = _T_94 ? _T_123 : _GEN_71; // @[Conditional.scala 39:67] - wire _GEN_84 = _T_94 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67] - wire _GEN_86 = _T_94 ? 1'h0 : _GEN_66; // @[Conditional.scala 39:67] - wire _GEN_90 = _T_94 ? 1'h0 : _GEN_75; // @[Conditional.scala 39:67] - wire buf_data_wr_en = _T_42 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] - wire buf_cmd_byte_ptr_en = _T_42 ? buf_state_en : _GEN_90; // @[Conditional.scala 40:58] - wire [2:0] buf_cmd_byte_ptr = _T_42 ? io_axi_araddr[2:0] : _GEN_82; // @[Conditional.scala 40:58] - wire slvbuf_wr_en = _T_42 ? 1'h0 : _GEN_79; // @[Conditional.scala 40:58] - wire slvbuf_error_en = _T_42 ? 1'h0 : _GEN_86; // @[Conditional.scala 40:58] - wire [34:0] _T_469 = {io_axi_araddr,io_axi_araddr[2:0]}; // @[Cat.scala 29:58] - wire _T_472 = buf_state == 3'h3; // @[axi4_to_ahb.scala 342:33] - wire [31:0] _T_554 = {io_axi_araddr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [31:0] _T_557 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] - wire [2:0] buf_size_in = {{1'd0}, io_axi_arsize[1:0]}; // @[axi4_to_ahb.scala 343:15] - wire [2:0] _T_564 = {1'h0,buf_size_in[1:0]}; // @[Cat.scala 29:58] - wire [1:0] _T_566 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_231 = buf_aligned | _T_230; // @[axi4_to_ahb.scala 314:44] + wire [7:0] _T_269 = buf_byteen >> _T_228; // @[axi4_to_ahb.scala 314:92] + wire _T_271 = ~_T_269[0]; // @[axi4_to_ahb.scala 314:163] + wire _T_272 = _T_231 | _T_271; // @[axi4_to_ahb.scala 314:79] + wire _T_273 = trxn_done & _T_272; // @[axi4_to_ahb.scala 314:29] + wire _T_347 = _T_230 | _T_271; // @[axi4_to_ahb.scala 327:118] + wire _T_348 = _T_107 & _T_347; // @[axi4_to_ahb.scala 327:82] + wire _T_349 = ahb_hresp_q | _T_348; // @[axi4_to_ahb.scala 327:32] + wire _GEN_11 = _T_279 & _T_349; // @[Conditional.scala 39:67] + wire _GEN_24 = _T_186 ? _T_273 : _GEN_11; // @[Conditional.scala 39:67] + wire _GEN_43 = _T_184 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] + wire _GEN_61 = _T_173 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_134 ? _T_111 : _GEN_61; // @[Conditional.scala 39:67] + wire _GEN_84 = _T_99 ? _T_111 : _GEN_73; // @[Conditional.scala 39:67] + wire cmd_done = _T_47 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] + wire _T_274 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 315:43] + wire _T_275 = ~_T_274; // @[axi4_to_ahb.scala 315:32] + wire [1:0] _T_277 = _T_275 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_278 = _T_277 & 2'h2; // @[axi4_to_ahb.scala 315:57] + wire _T_301 = _T_53 | _T_94; // @[axi4_to_ahb.scala 325:62] + wire _T_302 = buf_state_en & _T_301; // @[axi4_to_ahb.scala 325:33] + wire _T_355 = _T_275 | bypass_en; // @[axi4_to_ahb.scala 329:57] + wire [1:0] _T_357 = _T_355 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_358 = _T_357 & 2'h2; // @[axi4_to_ahb.scala 329:71] + wire _T_365 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 332:40] + wire [2:0] _T_441 = bypass_en ? _T_91 : _T_229; // @[axi4_to_ahb.scala 335:30] + wire _GEN_6 = _T_279 & ahb_hresp_q; // @[Conditional.scala 39:67] + wire _GEN_7 = _T_279 ? buf_state_en : _T_442; // @[Conditional.scala 39:67] + wire _GEN_9 = _T_279 & _T_302; // @[Conditional.scala 39:67] + wire _GEN_30 = _T_186 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] + wire _GEN_47 = _T_184 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_173 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_134 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67] + wire _GEN_97 = _T_99 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] + wire buf_wr_en = _T_47 ? 1'h0 : _GEN_97; // @[Conditional.scala 40:58] + wire _GEN_10 = _T_279 & buf_wr_en; // @[Conditional.scala 39:67] + wire [1:0] _GEN_13 = _T_279 ? _T_358 : 2'h0; // @[Conditional.scala 39:67] + wire _GEN_16 = _T_279 & _T_365; // @[Conditional.scala 39:67] + wire [2:0] _GEN_17 = _T_279 ? _T_441 : 3'h0; // @[Conditional.scala 39:67] + wire _GEN_21 = _T_186 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] + wire _GEN_22 = _T_186 & buf_state_en; // @[Conditional.scala 39:67] + wire [2:0] _GEN_23 = _T_186 ? _T_229 : _GEN_17; // @[Conditional.scala 39:67] + wire [1:0] _GEN_25 = _T_186 ? _T_278 : _GEN_13; // @[Conditional.scala 39:67] + wire _GEN_28 = _T_186 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] + wire _GEN_31 = _T_186 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] + wire _GEN_36 = _T_184 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_184 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67] + wire _GEN_39 = _T_184 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] + wire _GEN_41 = _T_184 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] + wire [2:0] _GEN_42 = _T_184 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67] + wire [1:0] _GEN_44 = _T_184 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_173 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] + wire [2:0] _GEN_54 = _T_173 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67] + wire [1:0] _GEN_55 = _T_173 ? _T_183 : _GEN_44; // @[Conditional.scala 39:67] + wire _GEN_56 = _T_173 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] + wire _GEN_58 = _T_173 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_173 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] + wire _GEN_69 = _T_134 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_71 = _T_134 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67] + wire [2:0] _GEN_75 = _T_134 ? _T_128 : _GEN_54; // @[Conditional.scala 39:67] + wire [1:0] _GEN_76 = _T_134 ? _T_168 : _GEN_55; // @[Conditional.scala 39:67] + wire _GEN_77 = _T_134 ? _T_146 : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_79 = _T_134 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_85 = _T_99 ? buf_state_en : _GEN_77; // @[Conditional.scala 39:67] + wire [2:0] _GEN_88 = _T_99 ? _T_128 : _GEN_75; // @[Conditional.scala 39:67] + wire [1:0] _GEN_89 = _T_99 ? _T_133 : _GEN_76; // @[Conditional.scala 39:67] + wire _GEN_90 = _T_99 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67] + wire _GEN_92 = _T_99 ? 1'h0 : _GEN_71; // @[Conditional.scala 39:67] + wire _GEN_95 = _T_99 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] + wire buf_data_wr_en = _T_47 ? _T_54 : _GEN_90; // @[Conditional.scala 40:58] + wire buf_cmd_byte_ptr_en = _T_47 ? buf_state_en : _GEN_95; // @[Conditional.scala 40:58] + wire [2:0] buf_cmd_byte_ptr = _T_47 ? _T_93 : _GEN_88; // @[Conditional.scala 40:58] + wire slvbuf_wr_en = _T_47 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] + wire slvbuf_error_en = _T_47 ? 1'h0 : _GEN_92; // @[Conditional.scala 40:58] + wire _T_533 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 353:24] + wire _T_534 = _T_101 | _T_533; // @[axi4_to_ahb.scala 352:51] + wire _T_536 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 353:57] + wire _T_537 = _T_534 | _T_536; // @[axi4_to_ahb.scala 353:36] + wire _T_539 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 353:91] + wire _T_540 = _T_537 | _T_539; // @[axi4_to_ahb.scala 353:70] + wire _T_542 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 354:25] + wire _T_544 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 354:62] + wire _T_546 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 354:97] + wire _T_547 = _T_544 | _T_546; // @[axi4_to_ahb.scala 354:74] + wire _T_549 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 354:132] + wire _T_550 = _T_547 | _T_549; // @[axi4_to_ahb.scala 354:109] + wire _T_552 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 354:168] + wire _T_553 = _T_550 | _T_552; // @[axi4_to_ahb.scala 354:145] + wire _T_555 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 355:28] + wire _T_556 = _T_553 | _T_555; // @[axi4_to_ahb.scala 354:181] + wire _T_558 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 355:63] + wire _T_559 = _T_556 | _T_558; // @[axi4_to_ahb.scala 355:40] + wire _T_561 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 355:99] + wire _T_562 = _T_559 | _T_561; // @[axi4_to_ahb.scala 355:76] + wire _T_563 = _T_542 & _T_562; // @[axi4_to_ahb.scala 354:38] + wire buf_aligned_in = _T_540 | _T_563; // @[axi4_to_ahb.scala 353:104] + wire _T_445 = buf_aligned_in & _T_49; // @[axi4_to_ahb.scala 347:55] + wire [2:0] _T_482 = _T_445 ? 3'h0 : master_addr[2:0]; // @[axi4_to_ahb.scala 347:38] + wire [34:0] _T_483 = {master_addr,_T_482}; // @[Cat.scala 29:58] + wire _T_486 = buf_state == 3'h3; // @[axi4_to_ahb.scala 350:33] + wire _T_492 = buf_aligned_in & _T_542; // @[axi4_to_ahb.scala 351:38] + wire _T_495 = _T_492 & _T_49; // @[axi4_to_ahb.scala 351:72] + wire [1:0] _T_529 = _T_495 ? 2'h0 : master_size[1:0]; // @[axi4_to_ahb.scala 351:21] + wire [31:0] _T_568 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [31:0] _T_571 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [1:0] _T_575 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [2:0] buf_size_in = {{1'd0}, _T_529}; // @[axi4_to_ahb.scala 351:15] + wire [1:0] _T_577 = _T_575 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 358:80] + wire [2:0] _T_578 = {1'h0,_T_577}; // @[Cat.scala 29:58] + wire [1:0] _T_580 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] reg [1:0] buf_size; // @[Reg.scala 27:20] - wire [1:0] _T_568 = _T_566 & buf_size; // @[axi4_to_ahb.scala 350:138] - wire [2:0] _T_569 = {1'h0,_T_568}; // @[Cat.scala 29:58] - wire _T_572 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 354:33] - wire [1:0] _T_573 = {1'h1,_T_572}; // @[Cat.scala 29:58] - wire _T_595 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 363:40] - wire _T_596 = _T_595 & io_ahb_hready; // @[axi4_to_ahb.scala 363:52] - wire last_addr_en = _T_596 & io_ahb_hwrite; // @[axi4_to_ahb.scala 363:68] - wire [2:0] _T_646 = buf_state_en ? buf_nxtstate : buf_state; // @[axi4_to_ahb.scala 393:16] + wire [1:0] _T_582 = _T_580 & buf_size; // @[axi4_to_ahb.scala 358:138] + wire [2:0] _T_583 = {1'h0,_T_582}; // @[Cat.scala 29:58] + wire _T_586 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 362:33] + wire [1:0] _T_587 = {1'h1,_T_586}; // @[Cat.scala 29:58] + reg buf_write; // @[Reg.scala 27:20] + wire _T_609 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 371:40] + wire _T_610 = _T_609 & io_ahb_hready; // @[axi4_to_ahb.scala 371:52] + wire last_addr_en = _T_610 & io_ahb_hwrite; // @[axi4_to_ahb.scala 371:68] + wire wrbuf_en = _T_42 & master_ready; // @[axi4_to_ahb.scala 373:47] + wire wrbuf_data_en = _T_43 & master_ready; // @[axi4_to_ahb.scala 374:50] + wire wrbuf_cmd_sent = _T_143 & _T_49; // @[axi4_to_ahb.scala 375:49] + wire _T_620 = ~wrbuf_en; // @[axi4_to_ahb.scala 376:33] + wire wrbuf_rst = wrbuf_cmd_sent & _T_620; // @[axi4_to_ahb.scala 376:31] + wire _T_622 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 378:35] + wire _T_623 = wrbuf_vld & _T_622; // @[axi4_to_ahb.scala 378:33] + wire _T_624 = ~_T_623; // @[axi4_to_ahb.scala 378:21] + wire _T_627 = wrbuf_data_vld & _T_622; // @[axi4_to_ahb.scala 379:37] + wire _T_628 = ~_T_627; // @[axi4_to_ahb.scala 379:20] + wire _T_631 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 380:21] + wire _T_634 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 384:52] + wire _T_635 = ~wrbuf_rst; // @[axi4_to_ahb.scala 384:88] + wire _T_639 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 385:52] reg buf_tag; // @[Reg.scala 27:20] - wire _T_680 = ~slave_valid_pre; // @[axi4_to_ahb.scala 428:52] - wire _T_693 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 452:43] - wire _T_694 = _T_693 | io_clk_override; // @[axi4_to_ahb.scala 452:58] - wire _T_697 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 453:54] - wire _T_698 = _T_697 | io_clk_override; // @[axi4_to_ahb.scala 453:74] - wire _T_700 = buf_state != 3'h0; // @[axi4_to_ahb.scala 454:50] - wire _T_701 = _T_700 | io_clk_override; // @[axi4_to_ahb.scala 454:60] + wire _T_689 = ~slave_valid_pre; // @[axi4_to_ahb.scala 436:52] + wire _T_702 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 460:43] + wire _T_703 = _T_702 | io_clk_override; // @[axi4_to_ahb.scala 460:58] + wire _T_706 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 461:54] + wire _T_707 = _T_706 | io_clk_override; // @[axi4_to_ahb.scala 461:74] + wire _T_709 = buf_state != 3'h0; // @[axi4_to_ahb.scala 462:50] + wire _T_710 = _T_709 | io_clk_override; // @[axi4_to_ahb.scala 462:60] rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), @@ -397,36 +534,36 @@ module axi4_to_ahb( .io_en(rvclkhdr_9_io_en), .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - assign io_axi_awready = 1'h0; // @[axi4_to_ahb.scala 370:18] - assign io_axi_wready = 1'h0; // @[axi4_to_ahb.scala 371:17] - assign io_axi_bvalid = _T_18 & slave_opc[3]; // @[axi4_to_ahb.scala 202:17] - assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_23; // @[axi4_to_ahb.scala 203:16] - assign io_axi_bid = slvbuf_tag; // @[axi4_to_ahb.scala 204:14] - assign io_axi_arready = 1'h0; // @[axi4_to_ahb.scala 372:18] - assign io_axi_rvalid = _T_18 & _T_28; // @[axi4_to_ahb.scala 206:17] - assign io_axi_rid = slvbuf_tag; // @[axi4_to_ahb.scala 208:14] - assign io_axi_rdata = slvbuf_error ? _T_587 : _T_591; // @[axi4_to_ahb.scala 209:16] - assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_23; // @[axi4_to_ahb.scala 207:16] - assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 373:16] - assign io_ahb_haddr = bypass_en ? _T_554 : _T_557; // @[axi4_to_ahb.scala 349:16] - assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 352:17] - assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 353:20] - assign io_ahb_hprot = {{2'd0}, _T_573}; // @[axi4_to_ahb.scala 354:16] - assign io_ahb_hsize = bypass_en ? _T_564 : _T_569; // @[axi4_to_ahb.scala 350:16] - assign io_ahb_htrans = _T_42 ? _T_93 : _GEN_83; // @[axi4_to_ahb.scala 219:17 axi4_to_ahb.scala 250:21 axi4_to_ahb.scala 262:21 axi4_to_ahb.scala 277:21 axi4_to_ahb.scala 287:21 axi4_to_ahb.scala 307:21 axi4_to_ahb.scala 321:21] - assign io_ahb_hwrite = 1'h0; // @[axi4_to_ahb.scala 355:17] - assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 356:17] + assign io_axi_awready = _T_624 & master_ready; // @[axi4_to_ahb.scala 378:18] + assign io_axi_wready = _T_628 & master_ready; // @[axi4_to_ahb.scala 379:17] + assign io_axi_bvalid = _T_23 & slave_opc[3]; // @[axi4_to_ahb.scala 210:17] + assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 211:16] + assign io_axi_bid = slvbuf_tag; // @[axi4_to_ahb.scala 212:14] + assign io_axi_arready = _T_631 & master_ready; // @[axi4_to_ahb.scala 380:18] + assign io_axi_rvalid = _T_23 & _T_33; // @[axi4_to_ahb.scala 214:17] + assign io_axi_rid = slvbuf_tag; // @[axi4_to_ahb.scala 216:14] + assign io_axi_rdata = slvbuf_error ? _T_601 : _T_605; // @[axi4_to_ahb.scala 217:16] + assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 215:16] + assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 381:16] + assign io_ahb_haddr = bypass_en ? _T_568 : _T_571; // @[axi4_to_ahb.scala 357:16] + assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 360:17] + assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 361:20] + assign io_ahb_hprot = {{2'd0}, _T_587}; // @[axi4_to_ahb.scala 362:16] + assign io_ahb_hsize = bypass_en ? _T_578 : _T_583; // @[axi4_to_ahb.scala 358:16] + assign io_ahb_htrans = _T_47 ? _T_98 : _GEN_89; // @[axi4_to_ahb.scala 227:17 axi4_to_ahb.scala 258:21 axi4_to_ahb.scala 270:21 axi4_to_ahb.scala 285:21 axi4_to_ahb.scala 295:21 axi4_to_ahb.scala 315:21 axi4_to_ahb.scala 329:21] + assign io_ahb_hwrite = bypass_en ? _T_49 : buf_write; // @[axi4_to_ahb.scala 363:17] + assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 364:17] assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] assign rvclkhdr_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16] assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_1_io_en = io_bus_clk_en & _T_39; // @[el2_lib.scala 485:16] + assign rvclkhdr_1_io_en = io_bus_clk_en & _T_44; // @[el2_lib.scala 485:16] assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_2_io_en = 1'h0; // @[el2_lib.scala 511:17] + assign rvclkhdr_2_io_en = _T_42 & master_ready; // @[el2_lib.scala 511:17] assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] - assign rvclkhdr_3_io_en = 1'h0; // @[el2_lib.scala 511:17] + assign rvclkhdr_3_io_en = _T_43 & master_ready; // @[el2_lib.scala 511:17] assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] assign rvclkhdr_4_io_en = buf_wr_en & io_bus_clk_en; // @[el2_lib.scala 511:17] @@ -435,16 +572,16 @@ module axi4_to_ahb( assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[el2_lib.scala 511:17] assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_6_io_en = io_bus_clk_en & _T_694; // @[el2_lib.scala 485:16] + assign rvclkhdr_6_io_en = io_bus_clk_en & _T_703; // @[el2_lib.scala 485:16] assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 484:17] assign rvclkhdr_7_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16] assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_8_io_en = io_bus_clk_en & _T_698; // @[el2_lib.scala 485:16] + assign rvclkhdr_8_io_en = io_bus_clk_en & _T_707; // @[el2_lib.scala 485:16] assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 484:17] - assign rvclkhdr_9_io_en = io_bus_clk_en & _T_701; // @[el2_lib.scala 485:16] + assign rvclkhdr_9_io_en = io_bus_clk_en & _T_710; // @[el2_lib.scala 485:16] assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE @@ -481,46 +618,67 @@ initial begin `endif `endif `ifdef RANDOMIZE_REG_INIT - _RAND_0 = {2{`RANDOM}}; - wrbuf_data = _RAND_0[63:0]; + _RAND_0 = {1{`RANDOM}}; + buf_state = _RAND_0[2:0]; _RAND_1 = {1{`RANDOM}}; - buf_state = _RAND_1[2:0]; + wrbuf_vld = _RAND_1[0:0]; _RAND_2 = {1{`RANDOM}}; - ahb_hready_q = _RAND_2[0:0]; + wrbuf_data_vld = _RAND_2[0:0]; _RAND_3 = {1{`RANDOM}}; - ahb_htrans_q = _RAND_3[1:0]; + ahb_hready_q = _RAND_3[0:0]; _RAND_4 = {1{`RANDOM}}; - ahb_hwrite_q = _RAND_4[0:0]; + ahb_htrans_q = _RAND_4[1:0]; _RAND_5 = {1{`RANDOM}}; - ahb_hresp_q = _RAND_5[0:0]; + ahb_hwrite_q = _RAND_5[0:0]; _RAND_6 = {1{`RANDOM}}; - cmd_doneQ = _RAND_6[0:0]; + ahb_hresp_q = _RAND_6[0:0]; _RAND_7 = {1{`RANDOM}}; - slvbuf_error = _RAND_7[0:0]; + cmd_doneQ = _RAND_7[0:0]; _RAND_8 = {1{`RANDOM}}; - slvbuf_tag = _RAND_8[0:0]; + wrbuf_tag = _RAND_8[0:0]; _RAND_9 = {1{`RANDOM}}; - last_bus_addr = _RAND_9[31:0]; - _RAND_10 = {2{`RANDOM}}; - buf_data = _RAND_10[63:0]; - _RAND_11 = {2{`RANDOM}}; - ahb_hrdata_q = _RAND_11[63:0]; - _RAND_12 = {1{`RANDOM}}; - buf_addr = _RAND_12[31:0]; + wrbuf_addr = _RAND_9[31:0]; + _RAND_10 = {1{`RANDOM}}; + wrbuf_size = _RAND_10[2:0]; + _RAND_11 = {1{`RANDOM}}; + wrbuf_byteen = _RAND_11[7:0]; + _RAND_12 = {2{`RANDOM}}; + wrbuf_data = _RAND_12[63:0]; _RAND_13 = {1{`RANDOM}}; - buf_cmd_byte_ptrQ = _RAND_13[2:0]; + slvbuf_write = _RAND_13[0:0]; _RAND_14 = {1{`RANDOM}}; - buf_aligned = _RAND_14[0:0]; + slvbuf_error = _RAND_14[0:0]; _RAND_15 = {1{`RANDOM}}; - buf_size = _RAND_15[1:0]; + slvbuf_tag = _RAND_15[0:0]; _RAND_16 = {1{`RANDOM}}; - buf_tag = _RAND_16[0:0]; + last_bus_addr = _RAND_16[31:0]; + _RAND_17 = {2{`RANDOM}}; + buf_data = _RAND_17[63:0]; + _RAND_18 = {2{`RANDOM}}; + ahb_hrdata_q = _RAND_18[63:0]; + _RAND_19 = {1{`RANDOM}}; + buf_addr = _RAND_19[31:0]; + _RAND_20 = {1{`RANDOM}}; + buf_cmd_byte_ptrQ = _RAND_20[2:0]; + _RAND_21 = {1{`RANDOM}}; + buf_byteen = _RAND_21[7:0]; + _RAND_22 = {1{`RANDOM}}; + buf_aligned = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + buf_size = _RAND_23[1:0]; + _RAND_24 = {1{`RANDOM}}; + buf_write = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + buf_tag = _RAND_25[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin - wrbuf_data = 64'h0; + buf_state = 3'h0; end if (reset) begin - buf_state = 3'h0; + wrbuf_vld = 1'h0; + end + if (reset) begin + wrbuf_data_vld = 1'h0; end if (reset) begin ahb_hready_q = 1'h0; @@ -537,6 +695,24 @@ initial begin if (reset) begin cmd_doneQ = 1'h0; end + if (reset) begin + wrbuf_tag = 1'h0; + end + if (reset) begin + wrbuf_addr = 32'h0; + end + if (reset) begin + wrbuf_size = 3'h0; + end + if (reset) begin + wrbuf_byteen = 8'h0; + end + if (reset) begin + wrbuf_data = 64'h0; + end + if (reset) begin + slvbuf_write = 1'h0; + end if (reset) begin slvbuf_error = 1'h0; end @@ -558,12 +734,18 @@ initial begin if (reset) begin buf_cmd_byte_ptrQ = 3'h0; end + if (reset) begin + buf_byteen = 8'h0; + end if (reset) begin buf_aligned = 1'h0; end if (reset) begin buf_size = 2'h0; end + if (reset) begin + buf_write = 1'h0; + end if (reset) begin buf_tag = 1'h0; end @@ -573,18 +755,25 @@ end // initial `FIRRTL_AFTER_INITIAL `endif `endif // SYNTHESIS - always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin - if (reset) begin - wrbuf_data <= 64'h0; - end else begin - wrbuf_data <= io_axi_wdata; - end - end always @(posedge ahbm_clk or posedge reset) begin if (reset) begin buf_state <= 3'h0; end else begin - buf_state <= _T_646 & 3'h1; + buf_state <= _T_1 & 3'h1; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_vld <= 1'h0; + end else begin + wrbuf_vld <= _T_634 & _T_635; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_data_vld <= 1'h0; + end else begin + wrbuf_data_vld <= _T_639 & _T_635; end end always @(posedge ahbm_clk or posedge reset) begin @@ -619,27 +808,69 @@ end // initial if (reset) begin cmd_doneQ <= 1'h0; end else begin - cmd_doneQ <= _T_260 & _T_680; + cmd_doneQ <= _T_274 & _T_689; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_tag <= 1'h0; + end else if (wrbuf_en) begin + wrbuf_tag <= io_axi_awid; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + wrbuf_addr <= 32'h0; + end else begin + wrbuf_addr <= io_axi_awaddr; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_size <= 3'h0; + end else if (wrbuf_en) begin + wrbuf_size <= io_axi_awsize; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_byteen <= 8'h0; + end else if (wrbuf_data_en) begin + wrbuf_byteen <= io_axi_wstrb; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + wrbuf_data <= 64'h0; + end else begin + wrbuf_data <= io_axi_wdata; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + slvbuf_write <= 1'h0; + end else if (slvbuf_wr_en) begin + slvbuf_write <= buf_write; end end always @(posedge ahbm_clk or posedge reset) begin if (reset) begin slvbuf_error <= 1'h0; end else if (slvbuf_error_en) begin - if (_T_42) begin + if (_T_47) begin slvbuf_error <= 1'h0; - end else if (_T_94) begin + end else if (_T_99) begin slvbuf_error <= 1'h0; - end else if (_T_124) begin + end else if (_T_134) begin slvbuf_error <= ahb_hresp_q; - end else if (_T_159) begin + end else if (_T_173) begin slvbuf_error <= 1'h0; - end else if (_T_170) begin + end else if (_T_184) begin slvbuf_error <= ahb_hresp_q; - end else if (_T_172) begin + end else if (_T_186) begin slvbuf_error <= 1'h0; end else begin - slvbuf_error <= _GEN_5; + slvbuf_error <= _GEN_6; end end end @@ -660,7 +891,7 @@ end // initial always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin buf_data <= 64'h0; - end else if (_T_472) begin + end else if (_T_486) begin buf_data <= ahb_hrdata_q; end else begin buf_data <= wrbuf_data; @@ -677,51 +908,134 @@ end // initial if (reset) begin buf_addr <= 32'h0; end else begin - buf_addr <= _T_469[31:0]; + buf_addr <= _T_483[31:0]; end end always @(posedge ahbm_clk or posedge reset) begin if (reset) begin buf_cmd_byte_ptrQ <= 3'h0; end else if (buf_cmd_byte_ptr_en) begin - if (_T_42) begin - buf_cmd_byte_ptrQ <= io_axi_araddr[2:0]; - end else if (_T_94) begin + if (_T_47) begin + if (buf_write_in) begin + if (wrbuf_byteen[0]) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (wrbuf_byteen[1]) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (wrbuf_byteen[2]) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (wrbuf_byteen[3]) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (wrbuf_byteen[4]) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (wrbuf_byteen[5]) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (wrbuf_byteen[6]) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else if (wrbuf_byteen[7]) begin + buf_cmd_byte_ptrQ <= 3'h7; + end else begin + buf_cmd_byte_ptrQ <= 3'h0; + end + end else begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end + end else if (_T_99) begin if (bypass_en) begin - buf_cmd_byte_ptrQ <= io_axi_araddr[2:0]; + buf_cmd_byte_ptrQ <= master_addr[2:0]; end else begin buf_cmd_byte_ptrQ <= buf_addr[2:0]; end - end else if (_T_124) begin + end else if (_T_134) begin if (bypass_en) begin - buf_cmd_byte_ptrQ <= io_axi_araddr[2:0]; + buf_cmd_byte_ptrQ <= master_addr[2:0]; end else begin buf_cmd_byte_ptrQ <= buf_addr[2:0]; end - end else if (_T_159) begin + end else if (_T_173) begin buf_cmd_byte_ptrQ <= buf_addr[2:0]; - end else if (_T_170) begin + end else if (_T_184) begin buf_cmd_byte_ptrQ <= 3'h0; - end else if (_T_172) begin + end else if (_T_186) begin if (trxn_done) begin - buf_cmd_byte_ptrQ <= 3'h0; + if (_T_199) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_202) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (_T_205) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (_T_208) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (_T_211) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (_T_214) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (_T_217) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else if (buf_byteen[7]) begin + buf_cmd_byte_ptrQ <= 3'h7; + end else begin + buf_cmd_byte_ptrQ <= 3'h0; + end end - end else if (_T_265) begin + end else if (_T_279) begin if (bypass_en) begin - buf_cmd_byte_ptrQ <= 3'h0; + if (wrbuf_byteen[0]) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (wrbuf_byteen[1]) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (wrbuf_byteen[2]) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (wrbuf_byteen[3]) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (wrbuf_byteen[4]) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (wrbuf_byteen[5]) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (wrbuf_byteen[6]) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else if (wrbuf_byteen[7]) begin + buf_cmd_byte_ptrQ <= 3'h7; + end else begin + buf_cmd_byte_ptrQ <= 3'h0; + end end else if (trxn_done) begin - buf_cmd_byte_ptrQ <= 3'h0; + if (_T_199) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_202) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (_T_205) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (_T_208) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (_T_211) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (_T_214) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (_T_217) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else if (buf_byteen[7]) begin + buf_cmd_byte_ptrQ <= 3'h7; + end else begin + buf_cmd_byte_ptrQ <= 3'h0; + end end end else begin buf_cmd_byte_ptrQ <= 3'h0; end end end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_byteen <= 8'h0; + end else if (buf_wr_en) begin + buf_byteen <= wrbuf_byteen; + end + end always @(posedge buf_clk or posedge reset) begin if (reset) begin buf_aligned <= 1'h0; - end else begin - buf_aligned <= buf_wr_en | buf_aligned; + end else if (buf_wr_en) begin + buf_aligned <= buf_aligned_in; end end always @(posedge buf_clk or posedge reset) begin @@ -731,11 +1045,36 @@ end // initial buf_size <= buf_size_in[1:0]; end end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_write <= 1'h0; + end else if (buf_wr_en) begin + if (_T_47) begin + buf_write <= _T_49; + end else if (_T_99) begin + buf_write <= 1'h0; + end else if (_T_134) begin + buf_write <= 1'h0; + end else if (_T_173) begin + buf_write <= 1'h0; + end else if (_T_184) begin + buf_write <= 1'h0; + end else if (_T_186) begin + buf_write <= 1'h0; + end else begin + buf_write <= _GEN_8; + end + end + end always @(posedge buf_clk or posedge reset) begin if (reset) begin buf_tag <= 1'h0; end else if (buf_wr_en) begin - buf_tag <= io_axi_arid; + if (wr_cmd_vld) begin + buf_tag <= wrbuf_tag; + end else begin + buf_tag <= io_axi_arid; + end end end endmodule diff --git a/src/main/scala/lib/axi4_to_ahb.scala b/src/main/scala/lib/axi4_to_ahb.scala index d79b6599..d32f1bd4 100644 --- a/src/main/scala/lib/axi4_to_ahb.scala +++ b/src/main/scala/lib/axi4_to_ahb.scala @@ -57,9 +57,17 @@ class axi4_to_ahb_IO extends Bundle with Config { class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config { val io = IO(new axi4_to_ahb_IO) + val buf_rst = WireInit(Bool(), init = false.B) + val buf_state_en = WireInit(Bool(), init = false.B) + val ahbm_clk = Wire(Clock()) + val ahbm_addr_clk = Wire(Clock()) + val ahbm_data_clk = Wire(Clock()) val idle :: cmd_rd :: cmd_wr :: data_rd :: data_wr :: done :: stream_rd :: stream_err_rd :: Nil = Enum(8) val buf_state = WireInit(idle) val buf_nxtstate = WireInit(idle) + buf_state := withClock(ahbm_clk) { + RegNext(Mux(buf_state_en.asBool(),buf_nxtstate,buf_state) & !buf_rst, 0.U) + } //logic signals val slave_valid = WireInit(Bool(), init = false.B) val slave_ready = WireInit(Bool(), init = false.B) @@ -99,7 +107,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config val buf_data = WireInit(0.U(64.W)) // [63:0] val buf_tag = WireInit(0.U(TAG.W)) // [TAG-1:0] //Miscellaneous signals - val buf_rst = WireInit(Bool(), init = false.B) +// val buf_rst = WireInit(Bool(), init = false.B) val buf_tag_in = WireInit(0.U(TAG.W)) // [TAG-1:0] val buf_addr_in = WireInit(0.U(32.W)) // [31:0] val buf_byteen_in = WireInit(0.U(8.W)) // [7:0] @@ -108,7 +116,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config val buf_aligned_in = WireInit(Bool(), init = false.B) val buf_size_in = WireInit(0.U(3.W)) // [2:0] - val buf_state_en = WireInit(Bool(), init = false.B) + // val buf_state_en = WireInit(Bool(), init = false.B) val buf_wr_en = WireInit(Bool(), init = false.B) val buf_data_wr_en = WireInit(Bool(), init = false.B) val slvbuf_error_en = WireInit(Bool(), init = false.B) @@ -149,9 +157,9 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config val ahbm_data_clken = WireInit(Bool(), init = false.B) val buf_clk = Wire(Clock()) //val slvbuf_clk = Wire(Clock()) - val ahbm_clk = Wire(Clock()) - val ahbm_addr_clk = Wire(Clock()) - val ahbm_data_clk = Wire(Clock()) +// val ahbm_clk = Wire(Clock()) +// val ahbm_addr_clk = Wire(Clock()) +// val ahbm_data_clk = Wire(Clock()) def get_write_size(byteen: UInt) = { @@ -217,10 +225,10 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config //State machine io.ahb_htrans := 0.U - //master_ready := 0.U + master_ready := 1.U buf_state_en := false.B buf_nxtstate := idle - buf_wr_en := 0.U + //buf_wr_en := 0.U buf_data_wr_en := 0.U slvbuf_error_in := 0.U slvbuf_error_en := 0.U @@ -236,11 +244,11 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config switch(buf_state) { is(idle) { - val master_ready = 1.U + // master_ready := 1.U buf_write_in := (master_opc(2, 1) === "b01".U) - val buf_nxtstate = Mux(buf_write_in.asBool(), cmd_wr, cmd_rd) - buf_state_en := master_valid & master_ready - buf_wr_en := buf_state_en + buf_nxtstate := Mux(buf_write_in.asBool(), cmd_wr, cmd_rd) + buf_state_en := master_valid & 1.U + // buf_wr_en := buf_state_en buf_data_wr_en := buf_state_en & (buf_nxtstate === cmd_wr) buf_cmd_byte_ptr_en := buf_state_en // ---------------------FROM FUNCTION CHECK LATER @@ -251,21 +259,21 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config } is(cmd_rd) { - val buf_nxtstate = Mux((master_valid & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd) + buf_nxtstate := Mux((master_valid & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd) buf_state_en := ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q cmd_done := buf_state_en & !master_valid slvbuf_wr_en := buf_state_en - val master_ready = (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q) & (buf_nxtstate === stream_rd) ////////////TBD//////// - buf_wr_en := master_ready + master_ready := (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q) & (Mux((master_valid & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd) === stream_rd) ////////////TBD//////// + // buf_wr_en := master_ready bypass_en := master_ready & master_valid buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0)) io.ahb_htrans := "b10".U & (Fill(2, (!buf_state_en | bypass_en))) } is(stream_rd) { - val master_ready = (ahb_hready_q & !ahb_hresp_q) & !(master_valid & master_opc(2, 1) === "b01".U) - buf_wr_en := (master_valid & master_ready & (master_opc(2, 0) === "b000".U)) // update the fifo if we are streaming the read commands - val buf_nxtstate = Mux(ahb_hresp_q.asBool(), stream_err_rd, Mux(buf_wr_en.asBool(), stream_rd, data_rd)) // assuming that the master accpets the slave response right away. + master_ready := (ahb_hready_q & !ahb_hresp_q) & !(master_valid & master_opc(2, 1) === "b01".U) + // buf_wr_en := (master_valid & master_ready & (master_opc(2, 0) === "b000".U)) // update the fifo if we are streaming the read commands + buf_nxtstate := Mux(ahb_hresp_q.asBool(), stream_err_rd, Mux((master_valid & master_ready & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd)) // assuming that the master accpets the slave response right away. buf_state_en := (ahb_hready_q | ahb_hresp_q) buf_data_wr_en := buf_state_en slvbuf_error_in := ahb_hresp_q @@ -275,7 +283,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config bypass_en := master_ready & master_valid & (buf_nxtstate === stream_rd) & buf_state_en buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0)) io.ahb_htrans := "b10".U & Fill(2, (!((buf_nxtstate =/= stream_rd) & buf_state_en))) - slvbuf_wr_en := buf_wr_en // shifting the contents from the buf to slv_buf for streaming cases + slvbuf_wr_en := (master_valid & master_ready & (master_opc(2, 0) === "b000".U)) // shifting the contents from the buf to slv_buf for streaming cases } is(stream_err_rd) { @@ -309,7 +317,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config is(data_wr) { buf_state_en := (cmd_doneQ & ahb_hready_q) | ahb_hresp_q - val master_ready = ((cmd_doneQ & ahb_hready_q) | ahb_hresp_q) & !ahb_hresp_q & slave_ready //////////TBD///////// // Ready to accept new command if current command done and no error + master_ready := ((cmd_doneQ & ahb_hready_q) | ahb_hresp_q) & !ahb_hresp_q & slave_ready //////////TBD///////// // Ready to accept new command if current command done and no error buf_nxtstate := Mux((ahb_hresp_q | !slave_ready).asBool(), done, Mux((master_valid & master_ready).asBool(), Mux((master_opc(2, 1) === "b01".U), cmd_wr, cmd_rd), idle)) slvbuf_error_in := ahb_hresp_q slvbuf_error_en := buf_state_en @@ -389,9 +397,9 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config RegEnable(io.ahb_haddr(31, 0), 0.U, last_addr_en.asBool()) } //sc - buf_state := withClock(ahbm_clk) { - RegNext(Mux(buf_state_en.asBool(),buf_nxtstate,buf_state) & !buf_rst, 0.U) - } +// buf_state := withClock(ahbm_clk) { +// RegNext(Mux(buf_state_en.asBool(),buf_nxtstate,buf_state) & !buf_rst, 0.U) +// } //s buf_write := withClock(buf_clk) { RegEnable(buf_write_in, 0.U, buf_wr_en.asBool()) diff --git a/target/scala-2.12/classes/lib/AXImain$.class b/target/scala-2.12/classes/lib/AXImain$.class index d90994ae..97ca24f5 100644 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