AHB/AXI updated
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@ -146,7 +146,6 @@ class ahb_to_axi4(TAG : Int) extends Module with lib with RequireAsyncReset {
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// AXI Read Response Channel - Always ready as AHB reads are blocking and the the buffer is available for the read coming back always.
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io.axi.r.ready := true.B
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}
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object ahb_to_axi4 extends App {
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println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4(1)))
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}
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//object ahb_to_axi4 extends App {
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// println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4(1)))
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//}
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