diff --git a/el2_swerv_wrapper.fir b/el2_swerv_wrapper.fir index a06813e7..c495b688 100644 --- a/el2_swerv_wrapper.fir +++ b/el2_swerv_wrapper.fir @@ -81557,7 +81557,7 @@ circuit el2_swerv_wrapper : module el2_dbg : input clock : Clock input reset : AsyncReset - output io : {dbg_cmd_addr : UInt<32>, dbg_cmd_wrdata : UInt<32>, dbg_cmd_valid : UInt<1>, dbg_cmd_write : UInt<1>, dbg_cmd_type : UInt<2>, dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_dma_bubble : UInt<1>, flip dma_dbg_ready : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi_awvalid : UInt<1>, flip sb_axi_awready : UInt<1>, sb_axi_awid : UInt<1>, sb_axi_awaddr : UInt<32>, sb_axi_awregion : UInt<4>, sb_axi_awlen : UInt<8>, sb_axi_awsize : UInt<3>, sb_axi_awburst : UInt<2>, sb_axi_awlock : UInt<1>, sb_axi_awcache : UInt<4>, sb_axi_awprot : UInt<3>, sb_axi_awqos : UInt<4>, sb_axi_wvalid : UInt<1>, flip sb_axi_wready : UInt<1>, sb_axi_wdata : UInt<64>, sb_axi_wstrb : UInt<8>, sb_axi_wlast : UInt<1>, flip sb_axi_bvalid : UInt<1>, sb_axi_bready : UInt<1>, flip sb_axi_bresp : UInt<2>, sb_axi_arvalid : UInt<1>, flip sb_axi_arready : UInt<1>, sb_axi_arid : UInt<1>, sb_axi_araddr : UInt<32>, sb_axi_arregion : UInt<4>, sb_axi_arlen : UInt<8>, sb_axi_arsize : UInt<3>, sb_axi_arburst : UInt<2>, sb_axi_arlock : UInt<1>, sb_axi_arcache : UInt<4>, sb_axi_arprot : UInt<3>, sb_axi_arqos : UInt<4>, flip sb_axi_rvalid : UInt<1>, sb_axi_rready : UInt<1>, flip sb_axi_rdata : UInt<64>, flip sb_axi_rresp : UInt<2>, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : AsyncReset, flip clk_override : UInt<1>, flip scan_mode : UInt<1>} + output io : {dbg_cmd_addr : UInt<32>, dbg_cmd_wrdata : UInt<32>, dbg_cmd_valid : UInt<1>, dbg_cmd_write : UInt<1>, dbg_cmd_type : UInt<2>, dbg_cmd_size : UInt<2>, dbg_core_rst_l : UInt<1>, flip core_dbg_rddata : UInt<32>, flip core_dbg_cmd_done : UInt<1>, flip core_dbg_cmd_fail : UInt<1>, dbg_dma_bubble : UInt<1>, flip dma_dbg_ready : UInt<1>, dbg_halt_req : UInt<1>, dbg_resume_req : UInt<1>, flip dec_tlu_debug_mode : UInt<1>, flip dec_tlu_dbg_halted : UInt<1>, flip dec_tlu_mpc_halted_only : UInt<1>, flip dec_tlu_resume_ack : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, sb_axi_awvalid : UInt<1>, flip sb_axi_awready : UInt<1>, sb_axi_awid : UInt<1>, sb_axi_awaddr : UInt<32>, sb_axi_awregion : UInt<4>, sb_axi_awlen : UInt<8>, sb_axi_awsize : UInt<3>, sb_axi_awburst : UInt<2>, sb_axi_awlock : UInt<1>, sb_axi_awcache : UInt<4>, sb_axi_awprot : UInt<3>, sb_axi_awqos : UInt<4>, sb_axi_wvalid : UInt<1>, flip sb_axi_wready : UInt<1>, sb_axi_wdata : UInt<64>, sb_axi_wstrb : UInt<8>, sb_axi_wlast : UInt<1>, flip sb_axi_bvalid : UInt<1>, sb_axi_bready : UInt<1>, flip sb_axi_bresp : UInt<2>, sb_axi_arvalid : UInt<1>, flip sb_axi_arready : UInt<1>, sb_axi_arid : UInt<1>, sb_axi_araddr : UInt<32>, sb_axi_arregion : UInt<4>, sb_axi_arlen : UInt<8>, sb_axi_arsize : UInt<3>, sb_axi_arburst : UInt<2>, sb_axi_arlock : UInt<1>, sb_axi_arcache : UInt<4>, sb_axi_arprot : UInt<3>, sb_axi_arqos : UInt<4>, flip sb_axi_rvalid : UInt<1>, sb_axi_rready : UInt<1>, flip sb_axi_rdata : UInt<64>, flip sb_axi_rresp : UInt<2>, flip dbg_bus_clk_en : UInt<1>, flip dbg_rst_l : UInt<1>, flip clk_override : UInt<1>, flip scan_mode : UInt<1>} wire dbg_state : UInt<3> dbg_state <= UInt<3>("h00") @@ -81636,7 +81636,7 @@ circuit el2_swerv_wrapper : rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] rvclkhdr_1.io.en <= sb_free_clken @[el2_lib.scala 485:16] rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] - node _T_7 = asUInt(io.dbg_rst_l) @[el2_dbg.scala 130:41] + node _T_7 = bits(io.dbg_rst_l, 0, 0) @[el2_dbg.scala 130:41] node _T_8 = bits(dmcontrol_reg, 0, 0) @[el2_dbg.scala 130:60] node _T_9 = or(_T_8, io.scan_mode) @[el2_dbg.scala 130:64] node dbg_dm_rst_l = and(_T_7, _T_9) @[el2_dbg.scala 130:44] @@ -109325,7 +109325,8 @@ circuit el2_swerv_wrapper : dbg.io.sb_axi_rdata <= io.sb_axi_rdata @[el2_swerv.scala 595:23] dbg.io.sb_axi_rresp <= io.sb_axi_rresp @[el2_swerv.scala 596:23] dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[el2_swerv.scala 597:25] - dbg.io.dbg_rst_l <= io.dbg_rst_l @[el2_swerv.scala 598:20] + node _T_26 = asUInt(io.dbg_rst_l) @[el2_swerv.scala 598:42] + dbg.io.dbg_rst_l <= _T_26 @[el2_swerv.scala 598:20] dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[el2_swerv.scala 599:23] dbg.io.scan_mode <= io.scan_mode @[el2_swerv.scala 600:20] dma_ctrl.reset <= io.core_rst_l @[el2_swerv.scala 604:18] diff --git a/el2_swerv_wrapper.v b/el2_swerv_wrapper.v index e9c50390..cc23c29f 100644 --- a/el2_swerv_wrapper.v +++ b/el2_swerv_wrapper.v @@ -59920,9 +59920,6 @@ initial begin _RAND_20 = {1{`RANDOM}}; data0_reg = _RAND_20[31:0]; `endif // RANDOMIZE_REG_INIT - if (io_dbg_rst_l) begin - dm_temp_0 = 1'h0; - end `endif // RANDOMIZE end // initial `ifdef FIRRTL_AFTER_INITIAL @@ -59986,6 +59983,11 @@ end // initial end else if (dmcontrol_wren) begin dm_temp <= _T_139; end + if (io_dbg_rst_l) begin + dm_temp_0 <= 1'h0; + end else if (dmcontrol_wren) begin + dm_temp_0 <= io_dmi_reg_wdata[0]; + end if (_T_29) begin dmstatus_havereset <= 1'h0; end else if (dmstatus_havereset_wren) begin @@ -60161,13 +60163,6 @@ end // initial data0_reg <= data0_din; end end - always @(posedge rvclkhdr_io_l1clk or posedge io_dbg_rst_l) begin - if (io_dbg_rst_l) begin - dm_temp_0 <= 1'h0; - end else if (dmcontrol_wren) begin - dm_temp_0 <= io_dmi_reg_wdata[0]; - end - end endmodule module el2_exu_alu_ctl( input clock, diff --git a/src/main/scala/SweRV_Wrapper.scala b/src/main/scala/SweRV_Wrapper.scala index a4681468..a0ae42c2 100644 --- a/src/main/scala/SweRV_Wrapper.scala +++ b/src/main/scala/SweRV_Wrapper.scala @@ -342,7 +342,7 @@ class el2_swerv_wrapper extends Module with el2_lib with RequireAsyncReset { val dma_hresp = Output(Bool()) */ }) - val mem = Module(new waleed.el2_mem()) + val mem = Module(new quasar.el2_mem()) val dmi_wrapper = Module(new dmi_wrapper()) val swerv = Module(new el2_swerv()) dmi_wrapper.io.trst_n := io.jtag_trst_n diff --git a/src/main/scala/el2_mem.scala b/src/main/scala/el2_mem.scala index bdd0d00a..9da64394 100644 --- a/src/main/scala/el2_mem.scala +++ b/src/main/scala/el2_mem.scala @@ -55,7 +55,7 @@ class Mem_bundle extends Bundle with el2_lib { val iccm_rd_data = Output(UInt(64.W)) } -object waleed extends el2_lib { +object quasar extends el2_lib { class el2_mem extends BlackBox(Map("DCCM_BITS" -> DCCM_BITS, "DCCM_FDATA_WIDTH" -> DCCM_FDATA_WIDTH, "ICCM_BITS" -> ICCM_BITS, @@ -92,7 +92,7 @@ object waleed extends el2_lib { } class blackbox_mem extends Module with el2_lib { val io = IO(new Mem_bundle) - val it = Module(new waleed.el2_mem) + val it = Module(new quasar.el2_mem) io <> it.io } diff --git a/target/scala-2.12/classes/dbg/el2_dbg$$anon$1.class b/target/scala-2.12/classes/dbg/el2_dbg$$anon$1.class index 4a58c61c..d9a716bc 100644 Binary files a/target/scala-2.12/classes/dbg/el2_dbg$$anon$1.class and b/target/scala-2.12/classes/dbg/el2_dbg$$anon$1.class differ diff --git a/target/scala-2.12/classes/dbg/el2_dbg.class b/target/scala-2.12/classes/dbg/el2_dbg.class index 802cca6a..9eb6de52 100644 Binary files a/target/scala-2.12/classes/dbg/el2_dbg.class and b/target/scala-2.12/classes/dbg/el2_dbg.class differ diff --git a/target/scala-2.12/classes/el2_mem/blackbox_mem.class b/target/scala-2.12/classes/el2_mem/blackbox_mem.class index 99d78e28..c5a99cf6 100644 Binary files a/target/scala-2.12/classes/el2_mem/blackbox_mem.class and b/target/scala-2.12/classes/el2_mem/blackbox_mem.class differ diff --git a/target/scala-2.12/classes/el2_mem/waleed$.class b/target/scala-2.12/classes/el2_mem/quasar$.class similarity index 99% rename from target/scala-2.12/classes/el2_mem/waleed$.class rename to target/scala-2.12/classes/el2_mem/quasar$.class index dd881596..f5d3b160 100644 Binary files a/target/scala-2.12/classes/el2_mem/waleed$.class and b/target/scala-2.12/classes/el2_mem/quasar$.class differ diff --git a/target/scala-2.12/classes/el2_mem/waleed$el2_mem.class b/target/scala-2.12/classes/el2_mem/quasar$el2_mem.class similarity index 94% rename from target/scala-2.12/classes/el2_mem/waleed$el2_mem.class rename to target/scala-2.12/classes/el2_mem/quasar$el2_mem.class index 4500cfa1..85c666c4 100644 Binary files a/target/scala-2.12/classes/el2_mem/waleed$el2_mem.class and b/target/scala-2.12/classes/el2_mem/quasar$el2_mem.class differ diff --git a/target/scala-2.12/classes/el2_mem/waleed.class b/target/scala-2.12/classes/el2_mem/quasar.class similarity index 97% rename from target/scala-2.12/classes/el2_mem/waleed.class rename to target/scala-2.12/classes/el2_mem/quasar.class index 58b78701..f2f24227 100644 Binary files a/target/scala-2.12/classes/el2_mem/waleed.class and b/target/scala-2.12/classes/el2_mem/quasar.class differ diff --git a/target/scala-2.12/classes/el2_swerv.class b/target/scala-2.12/classes/el2_swerv.class index 42959b4b..347d75c2 100644 Binary files a/target/scala-2.12/classes/el2_swerv.class and b/target/scala-2.12/classes/el2_swerv.class differ diff --git a/target/scala-2.12/classes/el2_swerv_wrapper.class b/target/scala-2.12/classes/el2_swerv_wrapper.class index af02d6ec..eda21eab 100644 Binary files a/target/scala-2.12/classes/el2_swerv_wrapper.class and b/target/scala-2.12/classes/el2_swerv_wrapper.class differ