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ifu bundlized

This commit is contained in:
waleed-lm 2020-12-09 18:23:25 +05:00
parent 695cc40d08
commit cf4bce002f
130 changed files with 216903 additions and 16606 deletions
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0
dmi_wrapper.sv Normal file
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2
firrtl_black_box_resource_files.f
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@ -1 +1,3 @@
/home/waleedbinehsan/Desktop/SweRV-Chislified-master/gated_latch.v /home/waleedbinehsan/Desktop/SweRV-Chislified-master/gated_latch.v
/home/waleedbinehsan/Desktop/SweRV-Chislified-master/dmi_wrapper.sv
/home/waleedbinehsan/Desktop/SweRV-Chislified-master/mem.sv

19586
ifu.fir
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File diff suppressed because it is too large Load Diff

12536
ifu.v
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169
mem.sv Normal file
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module mem #(
parameter ICACHE_BEAT_BITS,
parameter ICCM_BITS,
parameter ICACHE_NUM_WAYS,
parameter DCCM_BYTE_WIDTH,
parameter ICCM_BANK_INDEX_LO,
parameter ICACHE_BANK_BITS,
parameter DCCM_BITS,
parameter ICACHE_BEAT_ADDR_HI,
parameter ICCM_INDEX_BITS,
parameter ICCM_BANK_HI,
parameter ICACHE_BANKS_WAY,
parameter ICACHE_INDEX_HI,
parameter DCCM_NUM_BANKS,
parameter ICACHE_BANK_HI,
parameter ICACHE_BANK_LO,
parameter DCCM_ENABLE,
parameter ICACHE_TAG_LO,
parameter ICACHE_DATA_INDEX_LO,
parameter ICCM_NUM_BANKS,
parameter ICACHE_ECC,
parameter ICACHE_ENABLE,
parameter DCCM_BANK_BITS,
parameter ICCM_ENABLE,
parameter ICCM_BANK_BITS,
parameter ICACHE_TAG_DEPTH,
parameter ICACHE_WAYPACK,
parameter DCCM_SIZE,
parameter DCCM_FDATA_WIDTH,
parameter ICACHE_TAG_INDEX_LO,
parameter ICACHE_DATA_DEPTH)
(
input logic clk,
input logic rst_l,
input logic dccm_clk_override,
input logic icm_clk_override,
input logic dec_tlu_core_ecc_disable,
//DCCM ports
input logic dccm_wren,
input logic dccm_rden,
input logic [DCCM_BITS-1:0] dccm_wr_addr_lo,
input logic [DCCM_BITS-1:0] dccm_wr_addr_hi,
input logic [DCCM_BITS-1:0] dccm_rd_addr_lo,
input logic [DCCM_BITS-1:0] dccm_rd_addr_hi,
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
//`ifdef DCCM_ENABLE
//`endif
//ICCM ports
input logic [ICCM_BITS-1:1] iccm_rw_addr,
input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle
input logic iccm_wren,
input logic iccm_rden,
input logic [2:0] iccm_wr_size,
input logic [77:0] iccm_wr_data,
output logic [63:0] iccm_rd_data,
output logic [77:0] iccm_rd_data_ecc,
// Icache and Itag Ports
input logic [31:1] ic_rw_addr,
input logic [ICACHE_NUM_WAYS-1:0] ic_tag_valid,
input logic [ICACHE_NUM_WAYS-1:0] ic_wr_en,
input logic ic_rd_en,
input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
input logic ic_sel_premux_data, // Premux data sel
input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
input logic [70:0] ic_debug_wr_data, // Debug wr cache.
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
input logic ic_debug_rd_en, // Icache debug rd
input logic ic_debug_wr_en, // Icache debug wr
input logic ic_debug_tag_array, // Debug tag array
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag.
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
output logic [ICACHE_BANKS_WAY-1:0] ic_parerr, // parity error per bank
output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit,
output logic ic_tag_perr, // Icache Tag parity error
input logic scan_mode
);
// DCCM Instantiation
if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
lsu_dccm_mem #(
.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
.DCCM_BITS(DCCM_BITS),
.DCCM_NUM_BANKS(DCCM_NUM_BANKS),
.DCCM_BANK_BITS(DCCM_BANK_BITS),
.DCCM_SIZE(DCCM_SIZE),
.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH)) dccm (
.clk_override(dccm_clk_override),
.*
);
end else begin: Gen_dccm_disable
assign dccm_rd_data_lo = '0;
assign dccm_rd_data_hi = '0;
end
if ( ICACHE_ENABLE ) begin: icache
ifu_ic_mem #(
.ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
.ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
.ICACHE_BANK_BITS(ICACHE_BANK_BITS),
.ICACHE_BEAT_ADDR_HI(ICACHE_BEAT_ADDR_HI),
.ICACHE_BANKS_WAY(ICACHE_BANKS_WAY),
.ICACHE_INDEX_HI(ICACHE_INDEX_HI),
.ICACHE_BANK_HI(ICACHE_BANK_HI),
.ICACHE_BANK_LO(ICACHE_BANK_LO),
.ICACHE_TAG_LO(ICACHE_TAG_LO),
.ICACHE_DATA_INDEX_LO(ICACHE_DATA_INDEX_LO),
.ICACHE_ECC(ICACHE_ECC),
.ICACHE_TAG_DEPTH(ICACHE_TAG_DEPTH),
.ICACHE_WAYPACK(ICACHE_WAYPACK),
.ICACHE_TAG_INDEX_LO(ICACHE_TAG_INDEX_LO),
.ICACHE_DATA_DEPTH(ICACHE_DATA_DEPTH)) icm (
.clk_override(icm_clk_override),
.*
);
end
else begin
assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
assign ic_tag_perr = '0 ;
assign ic_rd_data = '0 ;
assign ic_stag_debug_rd_data = '0 ;
end // else: !if( ICACHE_ENABLE )
if (ICCM_ENABLE) begin : iccm
ifu_iccm_mem #(
.ICCM_BITS(ICCM_BITS),
.ICCM_BANK_INDEX_LO(ICCM_BANK_INDEX_LO),
.ICCM_INDEX_BITS(ICCM_INDEX_BITS),
.ICCM_BANK_HI(ICCM_BANK_HI),
.ICCM_NUM_BANKS(ICCM_NUM_BANKS),
.ICCM_BANK_BITS(ICCM_BANK_BITS)) iccm (.*,
.clk_override(icm_clk_override),
.iccm_rw_addr(iccm_rw_addr[ICCM_BITS-1:1]),
.iccm_rd_data(iccm_rd_data[63:0])
);
end
else begin
assign iccm_rd_data = '0 ;
assign iccm_rd_data_ecc = '0 ;
end
endmodule

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quasar_wrapper.anno.json Normal file
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[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"quasar_wrapper.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>selected_int_priority"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_w_prior_en_0_33"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_0_33"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_1_33"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_2_33"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_3_33"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_4_33"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|pic_ctrl>level_intpend_id_5_33"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|exu>i0_rs2_d"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|dec_trigger>io_dec_i0_trigger_match_d"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"quasar_wrapper.dmi_wrapper",
"resourceId":"/vsrc/dmi_wrapper.sv"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"quasar_wrapper.mem",
"resourceId":"/vsrc/mem.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"quasar_wrapper"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

114971
quasar_wrapper.fir Normal file
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84479
quasar_wrapper.v Normal file
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361
src/main/scala/lib/beh_lib.scala
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@ -1,361 +0,0 @@
package lib
import chisel3._
import chisel3.util._
class rvdff(WIDTH:Int=1,SHORT:Int=0) extends Module{
val io = IO(new Bundle{
val din = Input(UInt(WIDTH.W))
val dout = Output(UInt(WIDTH.W))
})
val flop = RegNext(io.din,0.U)
if(SHORT == 1)
{io.dout := io.din}
else
{io.dout := flop}
}
class rvdffsc extends Module with lib {
val io = IO(new Bundle{
val din = Input(UInt(32.W))
val en = Input(Bool())
val clear = Input(Bool())
val out = Output(UInt())
})
io.out := RegEnable(io.din & Fill(io.din.getWidth, ~io.clear), 0.U, io.en)
}
class rvdffs extends Module with lib {
val io = IO(new Bundle{
val din = Input(UInt(32.W))
val en = Input(Bool())
val clear = Input(Bool())
val out = Output(UInt())
})
io.out := RegEnable(io.din, 0.U, io.en)
}
class rvsyncss(WIDTH:Int = 251,SHORT:Int = 0) extends Module with RequireAsyncReset{ //Done for verification and testing
val io = IO(new Bundle{
val din = Input(UInt(WIDTH.W))
val dout = Output(UInt(WIDTH.W))
})
val sync_ff1 = RegNext(io.din,0.U) //RegNext(io.in,init)
val sync_ff2 = RegNext(sync_ff1,0.U)
if(SHORT == 1)
{ io.dout := io.din }
else
{ io.dout := sync_ff2 }
}
class rvlsadder extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val rs1 = Input(UInt(32.W))
val offset = Input(UInt(12.W))
val dout = Output(UInt(32.W))
})
val w1 = Cat("b0".U,io.rs1(11,0)) + Cat("b0".U,io.offset(11,0)) //w1[12] =cout offset[11]=sign
val dout_upper = ((Fill(20, ~(io.offset(11) ^ w1(12)))) & io.rs1(31,12)) |
((Fill(20, ~io.offset(11) ^ w1(12))) & (io.rs1(31,12)+1.U)) |
((Fill(20, io.offset(11) ^ ~w1(12))) & (io.rs1(31,12)-1.U))
io.dout := Cat(dout_upper,w1(11,0))
}
class rvbsadder extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val pc = Input(UInt(32.W)) // lsb is not using in code
val offset = Input(UInt(13.W)) // lsb is not using in code
val dout = Output(UInt(31.W))
})
val w1 = Cat("b0".U,io.pc(12,1)) + Cat("b0".U,io.offset(12,1)) //w1[12] =cout offset[12]=sign
val dout_upper = ((Fill(19, ~(io.offset(12) ^ w1(12))))& io.pc(31,13)) |
((Fill(19, ~io.offset(12) ^ w1(12))) & (io.pc(31,13)+1.U)) |
((Fill(19, io.offset(12) ^ ~w1(12))) & (io.pc(31,13)-1.U))
io.dout := Cat(dout_upper,w1(11,0))
}
class rvtwoscomp(WIDTH:Int=32) extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val din = Input(UInt(WIDTH.W))
val dout = Output(UInt(WIDTH.W))
})
val temp = Wire(Vec(WIDTH-1,UInt(1.W)))
val i:Int = 1
for(i <- 1 to WIDTH-1){
val done = io.din(i-1,0).orR
temp(i-1) := Mux(done ,~io.din(i),io.din(i))
}
io.dout := Cat(temp.asUInt,io.din(0))
}
class rvmaskandmatch(WIDTH:Int=32) extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val mask = Input(UInt(WIDTH.W))
val data = Input(UInt(WIDTH.W))
val masken = Input(UInt(1.W))
val match_out = Output(UInt(1.W))
})
val matchvec = Wire(Vec(WIDTH,UInt(1.W)))
val masken_or_fullmask = io.masken.asBool & ~io.mask(WIDTH-1,0).andR
matchvec(0) := masken_or_fullmask | (io.mask(0) === io.data(0)).asUInt
for(i <- 1 to WIDTH-1)
{matchvec(i) := Mux(io.mask(i-1,0).andR & masken_or_fullmask,"b1".U,(io.mask(i) === io.data(i)).asUInt)}
io.match_out := matchvec.asUInt
}
class rvrangecheck(CCM_SADR:Int=0, CCM_SIZE:Int=128) extends Module{
val io = IO(new Bundle{
val addr = Input(UInt(32.W))
val in_range = Output(UInt(1.W))
val in_region = Output(UInt(1.W))
})
val REGION_BITS = 4
val MASK_BITS = 10 + log2Ceil(CCM_SIZE)
val start_addr = Wire(UInt(32.W))
start_addr := CCM_SIZE.U
val region = start_addr(31,(32-REGION_BITS))
io.in_region := (io.addr(31,(32-REGION_BITS)) === region(REGION_BITS-1,0)).asUInt
if(CCM_SIZE == 48)
io.in_range := (io.addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt & ~(io.addr(MASK_BITS-1,MASK_BITS-2).andR.asUInt)
else
io.in_range := (io.addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt
}
// DONE
class rveven_paritygen(WIDTH:Int= 16) extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val data_in = Input (UInt(WIDTH.W))
val parity_out = Output(UInt(1.W))
})
io.parity_out := io.data_in.xorR.asUInt
} // DONE
// DONE
class rveven_paritycheck(WIDTH:Int= 16) extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val data_in = Input (UInt(WIDTH.W))
val parity_in = Input (UInt(1.W))
val parity_err = Output(UInt(1.W))
})
io.parity_err := (io.data_in.xorR.asUInt) ^ io.parity_in
} // DONE
class rvecc_encode extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val din = Input(UInt(32.W))
val ecc_out = Output(UInt(7.W))
})
val mask0 = Array(0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,1)
val mask1 = Array(1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,1,1,0,1)
val mask2 = Array(1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,0)
val mask3 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,0,0,0,0)
val mask4 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0)
val mask5 = Array(1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
val w0 = Wire(Vec(18,UInt(1.W)))
val w1 = Wire(Vec(18,UInt(1.W)))
val w2 = Wire(Vec(18,UInt(1.W)))
val w3 = Wire(Vec(15,UInt(1.W)))
val w4 = Wire(Vec(15,UInt(1.W)))
val w5 = Wire(Vec(6, UInt(1.W)))
var j = 0;var k = 0;var m = 0;
var x = 0;var y = 0;var z = 0
for(i <- 0 to 31)
{
if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
if(mask3(i)==1) {w3(x) := io.din(i); x = x +1 }
if(mask4(i)==1) {w4(y) := io.din(i); y = y +1 }
if(mask5(i)==1) {w5(z) := io.din(i); z = z +1 }
}
val w6 = Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR))
io.ecc_out := Cat(io.din.xorR ^ w6.xorR, w6)
}
// Make generator and then make it a method
class rvecc_decode extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val en = Input(UInt(1.W))
val din = Input(UInt(32.W))
val ecc_in = Input(UInt(7.W))
val sed_ded = Input(UInt(1.W))
val ecc_out = Output(UInt(7.W))
val dout = Output(UInt(32.W))
val single_ecc_error = Output(UInt(1.W))
val double_ecc_error = Output(UInt(1.W))
})
val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0)
val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1)
val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1)
val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1)
val w0 = Wire(Vec(18,UInt(1.W)))
val w1 = Wire(Vec(18,UInt(1.W)))
val w2 = Wire(Vec(18,UInt(1.W)))
val w3 = Wire(Vec(15,UInt(1.W)))
val w4 = Wire(Vec(15,UInt(1.W)))
val w5 = Wire(Vec(6,UInt(1.W)))
var j = 0;var k = 0;var m = 0; var n =0;
var x = 0;var y = 0;
for(i <- 0 to 31)
{
if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
if(mask3(i)==1) {w3(n) := io.din(i); n = n +1 }
if(mask4(i)==1) {w4(x) := io.din(i); x = x +1 }
if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 }
}
val ecc_check = Cat((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded ,io.ecc_in(5)^(w5.asUInt.xorR),io.ecc_in(4)^(w4.asUInt.xorR),io.ecc_in(3)^(w3.asUInt.xorR),io.ecc_in(2)^(w2.asUInt.xorR),io.ecc_in(1)^(w1.asUInt.xorR),io.ecc_in(0)^(w0.asUInt.xorR))
io.ecc_out := ecc_check
io.single_ecc_error := io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded)
io.double_ecc_error := io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded)
val error_mask = Wire(Vec(39,UInt(1.W)))
for(i <- 1 until 40){
error_mask(i-1) := ecc_check(5,0) === i.asUInt
}
val din_plus_parity = Cat(io.ecc_in(6), io.din(31,26), io.ecc_in(5), io.din(25,11), io.ecc_in(4), io.din(10,4), io.ecc_in(3), io.din(3,1), io.ecc_in(2), io.din(0), io.ecc_in(1,0))
val dout_plus_parity = Mux(io.single_ecc_error.asBool, (error_mask.asUInt ^ din_plus_parity), din_plus_parity)
io.dout := Cat(dout_plus_parity(37,32),dout_plus_parity(30,16), dout_plus_parity(14,8), dout_plus_parity(6,4), dout_plus_parity(2))
io.ecc_out := Cat(dout_plus_parity(38) ^ (ecc_check(6,0) === "b1000000".U), dout_plus_parity(31), dout_plus_parity(15), dout_plus_parity(7), dout_plus_parity(3), dout_plus_parity(1,0))
}
class rvecc_encode_64 extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val din = Input(UInt(64.W))
val ecc_out = Output(UInt(7.W))
})
val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1)
val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1)
val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1)
val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1)
val w0 = Wire(Vec(35,UInt(1.W)))
val w1 = Wire(Vec(35,UInt(1.W)))
val w2 = Wire(Vec(35,UInt(1.W)))
val w3 = Wire(Vec(31,UInt(1.W)))
val w4 = Wire(Vec(31,UInt(1.W)))
val w5 = Wire(Vec(31,UInt(1.W)))
val w6 = Wire(Vec(7, UInt(1.W)))
var j = 0;var k = 0;var m = 0; var n =0;
var x = 0;var y = 0;var z = 0
for(i <- 0 to 63)
{
if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
if(mask3(i)==1) {w3(n) := io.din(i); n = n +1 }
if(mask4(i)==1) {w4(x) := io.din(i); x = x +1 }
if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 }
if(mask6(i)==1) {w6(z) := io.din(i); z = z +1 }
}
io.ecc_out := Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR),(w6.asUInt.xorR))
}
class rvecc_decode_64 extends Module{ //Done for verification and testing
val io = IO(new Bundle{
val en = Input(UInt(1.W))
val din = Input(UInt(64.W))
val ecc_in = Input(UInt(7.W))
val ecc_error = Output(UInt(1.W))
})
val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1)
val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1)
val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1)
val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1)
val w0 = Wire(Vec(35,UInt(1.W)))
val w1 = Wire(Vec(35,UInt(1.W)))
val w2 = Wire(Vec(35,UInt(1.W)))
val w3 = Wire(Vec(31,UInt(1.W)))
val w4 = Wire(Vec(31,UInt(1.W)))
val w5 = Wire(Vec(31,UInt(1.W)))
val w6 = Wire(Vec(7, UInt(1.W)))
var j = 0;var k = 0;var m = 0; var n =0;
var x = 0;var y = 0;var z = 0
for(i <- 0 to 63)
{
if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
if(mask3(i)==1) {w3(n) := io.din(i); n = n +1 }
if(mask4(i)==1) {w4(x) := io.din(i); x = x +1 }
if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 }
if(mask6(i)==1) {w6(z) := io.din(i); z = z +1 }
}
val ecc_check = Cat((io.ecc_in(6) ^ w5.asUInt.xorR) ,io.ecc_in(5)^(w5.asUInt.xorR),io.ecc_in(4)^(w4.asUInt.xorR),io.ecc_in(3)^(w3.asUInt.xorR),io.ecc_in(2)^(w2.asUInt.xorR),io.ecc_in(1)^(w1.asUInt.xorR),io.ecc_in(0)^(w0.asUInt.xorR))
io.ecc_error := io.en & (ecc_check(6,0) != 0.U)
object rvsyncss {
def apply(din:UInt,clk:Clock) =withClock(clk){RegNext(withClock(clk){RegNext(din,0.U)},0.U)}
}
}

160
src/main/scala/lib/el2_lib.scala → src/main/scala/lib/lib.scala
View File

@ -1,163 +1,6 @@
package lib package lib
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
import mem.quasar.{DCCM_ENABLE, ICACHE_ECC, ICACHE_WAYPACK, ICCM_ENABLE, bool2int}
trait param {
val BHT_ADDR_HI = 0x9
val BHT_ADDR_LO = 0x2
val BHT_ARRAY_DEPTH = 0x100
val BHT_GHR_HASH_1 = 0x0
val BHT_GHR_SIZE = 0x8
val BHT_SIZE = 0x200
val BTB_ADDR_HI = 0x09
val BTB_ADDR_LO = 0x2
val BTB_ARRAY_DEPTH = 0x100
val BTB_BTAG_FOLD = 0x0
val BTB_BTAG_SIZE = 0x5
val BTB_FOLD2_INDEX_HASH = 0x0
val BTB_INDEX1_HI = 0x09
val BTB_INDEX1_LO = 0x02
val BTB_INDEX2_HI = 0x11
val BTB_INDEX2_LO = 0x0A
val BTB_INDEX3_HI = 0x19
val BTB_INDEX3_LO = 0x12
val BTB_SIZE = 0x200
val BUILD_AHB_LITE = 0x0
val BUILD_AXI4 = 0x1
val BUILD_AXI_NATIVE = 0x1
val BUS_PRTY_DEFAULT = 0x3
val DATA_ACCESS_ADDR0 = 0x00000000
val DATA_ACCESS_ADDR1 = 0xC0000000
val DATA_ACCESS_ADDR2 = 0xA0000000
val DATA_ACCESS_ADDR3 = 0x80000000
val DATA_ACCESS_ADDR4 = 0x00000000
val DATA_ACCESS_ADDR5 = 0x00000000
val DATA_ACCESS_ADDR6 = 0x00000000
val DATA_ACCESS_ADDR7 = 0x00000000
val DATA_ACCESS_ENABLE0 = 0x1
val DATA_ACCESS_ENABLE1 = 0x1
val DATA_ACCESS_ENABLE2 = 0x1
val DATA_ACCESS_ENABLE3 = 0x1
val DATA_ACCESS_ENABLE4 = 0x0
val DATA_ACCESS_ENABLE5 = 0x0
val DATA_ACCESS_ENABLE6 = 0x0
val DATA_ACCESS_ENABLE7 = 0x0
val DATA_ACCESS_MASK0 = 0x7FFFFFFF
val DATA_ACCESS_MASK1 = 0x3FFFFFFF
val DATA_ACCESS_MASK2 = 0x1FFFFFFF
val DATA_ACCESS_MASK3 = 0x0FFFFFFF
val DATA_ACCESS_MASK4 = 0xFFFFFFFF
val DATA_ACCESS_MASK5 = 0xFFFFFFFF
val DATA_ACCESS_MASK6 = 0xFFFFFFFF
val DATA_ACCESS_MASK7 = 0xFFFFFFFF
val DCCM_BANK_BITS = 0x2
val DCCM_BITS = 0x10
val DCCM_BYTE_WIDTH = 0x4
val DCCM_DATA_WIDTH = 0x20
val DCCM_ECC_WIDTH = 0x7
val DCCM_ENABLE = 0x1
val DCCM_FDATA_WIDTH = 0x27
val DCCM_INDEX_BITS = 0xC
val DCCM_NUM_BANKS = 0x04
val DCCM_REGION = 0xF
val DCCM_SADR = 0xF0040000
val DCCM_SIZE = 0x040
val DCCM_WIDTH_BITS = 0x2
val DMA_BUF_DEPTH = 0x5
val DMA_BUS_ID = 0x1
val DMA_BUS_PRTY = 0x2
val DMA_BUS_TAG = 0x1
val FAST_INTERRUPT_REDIRECT = 0x 1
val ICACHE_2BANKS = 0x1
val ICACHE_BANK_BITS = 0x1
val ICACHE_BANK_HI = 0x3
val ICACHE_BANK_LO = 0x3
val ICACHE_BANK_WIDTH = 0x8
val ICACHE_BANKS_WAY = 0x2
val ICACHE_BEAT_ADDR_HI = 0x5
val ICACHE_BEAT_BITS = 0x3
val ICACHE_DATA_DEPTH = 0x0200
val ICACHE_DATA_INDEX_LO = 0x4
val ICACHE_DATA_WIDTH = 0x40
val ICACHE_ECC = 0x1
val ICACHE_ENABLE = 0x1
val ICACHE_FDATA_WIDTH = 0x47
val ICACHE_INDEX_HI = 0x0C
val ICACHE_LN_SZ = 0x40
val ICACHE_NUM_BEATS = 0x8
val ICACHE_NUM_WAYS = 0x2
val ICACHE_ONLY = 0x0
val ICACHE_SCND_LAST = 0x6
val ICACHE_SIZE = 0x010
val ICACHE_STATUS_BITS = 0x1
val ICACHE_TAG_DEPTH = 0x0080
val ICACHE_TAG_INDEX_LO = 0x6
val ICACHE_TAG_LO = 0x0D
val ICACHE_WAYPACK = 0x0
val ICCM_BANK_BITS = 0x2
val ICCM_BANK_HI = 0x03
val ICCM_BANK_INDEX_LO = 0x04
val ICCM_BITS = 0x10
val ICCM_ENABLE = 0x1
val ICCM_ICACHE = 0x1
val ICCM_INDEX_BITS = 0xC
val ICCM_NUM_BANKS = 0x04
val ICCM_ONLY = 0x0
val ICCM_REGION = 0xE
val ICCM_SADR = 0xEE000000
val ICCM_SIZE = 0x040
val IFU_BUS_ID = 0x1
val IFU_BUS_PRTY = 0x2
val IFU_BUS_TAG = 0x3
val INST_ACCESS_ADDR0 = 0x00000000
val INST_ACCESS_ADDR1 = 0xC0000000
val INST_ACCESS_ADDR2 = 0xA0000000
val INST_ACCESS_ADDR3 = 0x80000000
val INST_ACCESS_ADDR4 = 0x00000000
val INST_ACCESS_ADDR5 = 0x00000000
val INST_ACCESS_ADDR6 = 0x00000000
val INST_ACCESS_ADDR7 = 0x00000000
val INST_ACCESS_ENABLE0 = 0x1
val INST_ACCESS_ENABLE1 = 0x1
val INST_ACCESS_ENABLE2 = 0x1
val INST_ACCESS_ENABLE3 = 0x1
val INST_ACCESS_ENABLE4 = 0x0
val INST_ACCESS_ENABLE5 = 0x0
val INST_ACCESS_ENABLE6 = 0x0
val INST_ACCESS_ENABLE7 = 0x0
val INST_ACCESS_MASK0 = 0x7FFFFFFF
val INST_ACCESS_MASK1 = 0x3FFFFFFF
val INST_ACCESS_MASK2 = 0x1FFFFFFF
val INST_ACCESS_MASK3 = 0x0FFFFFFF
val INST_ACCESS_MASK4 = 0xFFFFFFFF
val INST_ACCESS_MASK5 = 0xFFFFFFFF
val INST_ACCESS_MASK6 = 0xFFFFFFFF
val INST_ACCESS_MASK7 = 0xFFFFFFFF
val LOAD_TO_USE_PLUS1 = 0x0
val LSU2DMA = 0x0
val LSU_BUS_ID = 0x1
val LSU_BUS_PRTY = 0x2
val LSU_BUS_TAG = 0x3
val LSU_NUM_NBLOAD = 0x04
val LSU_NUM_NBLOAD_WIDTH = 0x2
val LSU_SB_BITS = 0x10
val LSU_STBUF_DEPTH = 0x4
val NO_ICCM_NO_ICACHE = 0x0
val PIC_2CYCLE = 0x0
val PIC_BASE_ADDR = 0xF00C0000
val PIC_BITS = 0x0F
val PIC_INT_WORDS = 0x1
val PIC_REGION = 0xF
val PIC_SIZE = 0x020
val PIC_TOTAL_INT = 0x1F
val PIC_TOTAL_INT_PLUS1 = 0x020
val RET_STACK_SIZE = 0x8
val SB_BUS_ID = 0x1
val SB_BUS_PRTY = 0x2
val SB_BUS_TAG = 0x1
val TIMER_LEGAL_EN = 0x1
}
trait lib extends param{ trait lib extends param{
def repl(b:Int, a:UInt) = VecInit.tabulate(b)(i => a).reduce(Cat(_,_)) def repl(b:Int, a:UInt) = VecInit.tabulate(b)(i => a).reduce(Cat(_,_))
@ -171,7 +14,8 @@ trait lib extends param{
val DATA_MEM_LINE = MEM_CAL val DATA_MEM_LINE = MEM_CAL
val Tag_Word = MEM_CAL._4 val Tag_Word = MEM_CAL._4
implicit def bool2int(b:Int) = if (b==1) true else false implicit def int2boolean(b:Int) = if (b==1) true else false
implicit def uint2bool(b:UInt) = b.asBool()
implicit def aslong(b:Int) = 0xFFFFFFFFL & b implicit def aslong(b:Int) = 0xFFFFFFFFL & b
object rvsyncss { object rvsyncss {
def apply(din:UInt,clk:Clock) =withClock(clk){RegNext(withClock(clk){RegNext(din,0.U)},0.U)} def apply(din:UInt,clk:Clock) =withClock(clk){RegNext(withClock(clk){RegNext(din,0.U)},0.U)}

158
src/main/scala/lib/param.scala Normal file
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@ -0,0 +1,158 @@
package lib
import chisel3._
import chisel3.util._
trait param {
val BHT_ADDR_HI = 0x9
val BHT_ADDR_LO = 0x2
val BHT_ARRAY_DEPTH = 0x100
val BHT_GHR_HASH_1 = 0x0
val BHT_GHR_SIZE = 0x8
val BHT_SIZE = 0x200
val BTB_ADDR_HI = 0x09
val BTB_ADDR_LO = 0x2
val BTB_ARRAY_DEPTH = 0x100
val BTB_BTAG_FOLD = 0x0
val BTB_BTAG_SIZE = 0x5
val BTB_FOLD2_INDEX_HASH = 0x0
val BTB_INDEX1_HI = 0x09
val BTB_INDEX1_LO = 0x02
val BTB_INDEX2_HI = 0x11
val BTB_INDEX2_LO = 0x0A
val BTB_INDEX3_HI = 0x19
val BTB_INDEX3_LO = 0x12
val BTB_SIZE = 0x200
val BUILD_AHB_LITE = 0x0
val BUILD_AXI4 = 0x1
val BUILD_AXI_NATIVE = 0x1
val BUS_PRTY_DEFAULT = 0x3
val DATA_ACCESS_ADDR0 = 0x00000000
val DATA_ACCESS_ADDR1 = 0xC0000000
val DATA_ACCESS_ADDR2 = 0xA0000000
val DATA_ACCESS_ADDR3 = 0x80000000
val DATA_ACCESS_ADDR4 = 0x00000000
val DATA_ACCESS_ADDR5 = 0x00000000
val DATA_ACCESS_ADDR6 = 0x00000000
val DATA_ACCESS_ADDR7 = 0x00000000
val DATA_ACCESS_ENABLE0 = 0x1
val DATA_ACCESS_ENABLE1 = 0x1
val DATA_ACCESS_ENABLE2 = 0x1
val DATA_ACCESS_ENABLE3 = 0x1
val DATA_ACCESS_ENABLE4 = 0x0
val DATA_ACCESS_ENABLE5 = 0x0
val DATA_ACCESS_ENABLE6 = 0x0
val DATA_ACCESS_ENABLE7 = 0x0
val DATA_ACCESS_MASK0 = 0x7FFFFFFF
val DATA_ACCESS_MASK1 = 0x3FFFFFFF
val DATA_ACCESS_MASK2 = 0x1FFFFFFF
val DATA_ACCESS_MASK3 = 0x0FFFFFFF
val DATA_ACCESS_MASK4 = 0xFFFFFFFF
val DATA_ACCESS_MASK5 = 0xFFFFFFFF
val DATA_ACCESS_MASK6 = 0xFFFFFFFF
val DATA_ACCESS_MASK7 = 0xFFFFFFFF
val DCCM_BANK_BITS = 0x2
val DCCM_BITS = 0x10
val DCCM_BYTE_WIDTH = 0x4
val DCCM_DATA_WIDTH = 0x20
val DCCM_ECC_WIDTH = 0x7
val DCCM_ENABLE = 0x1
val DCCM_FDATA_WIDTH = 0x27
val DCCM_INDEX_BITS = 0xC
val DCCM_NUM_BANKS = 0x04
val DCCM_REGION = 0xF
val DCCM_SADR = 0xF0040000
val DCCM_SIZE = 0x040
val DCCM_WIDTH_BITS = 0x2
val DMA_BUF_DEPTH = 0x5
val DMA_BUS_ID = 0x1
val DMA_BUS_PRTY = 0x2
val DMA_BUS_TAG = 0x1
val FAST_INTERRUPT_REDIRECT = 0x1
val ICACHE_2BANKS = 0x1
val ICACHE_BANK_BITS = 0x1
val ICACHE_BANK_HI = 0x3
val ICACHE_BANK_LO = 0x3
val ICACHE_BANK_WIDTH = 0x8
val ICACHE_BANKS_WAY = 0x2
val ICACHE_BEAT_ADDR_HI = 0x5
val ICACHE_BEAT_BITS = 0x3
val ICACHE_DATA_DEPTH = 0x0200
val ICACHE_DATA_INDEX_LO = 0x4
val ICACHE_DATA_WIDTH = 0x40
val ICACHE_ECC = 0x1
val ICACHE_ENABLE = 0x1
val ICACHE_FDATA_WIDTH = 0x47
val ICACHE_INDEX_HI = 0x0C
val ICACHE_LN_SZ = 0x40
val ICACHE_NUM_BEATS = 0x8
val ICACHE_NUM_WAYS = 0x2
val ICACHE_ONLY = 0x0
val ICACHE_SCND_LAST = 0x6
val ICACHE_SIZE = 0x010
val ICACHE_STATUS_BITS = 0x1
val ICACHE_TAG_DEPTH = 0x0080
val ICACHE_TAG_INDEX_LO = 0x6
val ICACHE_TAG_LO = 0x0D
val ICACHE_WAYPACK = 0x0
val ICCM_BANK_BITS = 0x2
val ICCM_BANK_HI = 0x03
val ICCM_BANK_INDEX_LO = 0x04
val ICCM_BITS = 0x10
val ICCM_ENABLE = 0x1
val ICCM_ICACHE = 0x1
val ICCM_INDEX_BITS = 0xC
val ICCM_NUM_BANKS = 0x04
val ICCM_ONLY = 0x0
val ICCM_REGION = 0xE
val ICCM_SADR = 0xEE000000
val ICCM_SIZE = 0x040
val IFU_BUS_ID = 0x1
val IFU_BUS_PRTY = 0x2
val IFU_BUS_TAG = 0x3
val INST_ACCESS_ADDR0 = 0x00000000
val INST_ACCESS_ADDR1 = 0xC0000000
val INST_ACCESS_ADDR2 = 0xA0000000
val INST_ACCESS_ADDR3 = 0x80000000
val INST_ACCESS_ADDR4 = 0x00000000
val INST_ACCESS_ADDR5 = 0x00000000
val INST_ACCESS_ADDR6 = 0x00000000
val INST_ACCESS_ADDR7 = 0x00000000
val INST_ACCESS_ENABLE0 = 0x1
val INST_ACCESS_ENABLE1 = 0x1
val INST_ACCESS_ENABLE2 = 0x1
val INST_ACCESS_ENABLE3 = 0x1
val INST_ACCESS_ENABLE4 = 0x0
val INST_ACCESS_ENABLE5 = 0x0
val INST_ACCESS_ENABLE6 = 0x0
val INST_ACCESS_ENABLE7 = 0x0
val INST_ACCESS_MASK0 = 0x7FFFFFFF
val INST_ACCESS_MASK1 = 0x3FFFFFFF
val INST_ACCESS_MASK2 = 0x1FFFFFFF
val INST_ACCESS_MASK3 = 0x0FFFFFFF
val INST_ACCESS_MASK4 = 0xFFFFFFFF
val INST_ACCESS_MASK5 = 0xFFFFFFFF
val INST_ACCESS_MASK6 = 0xFFFFFFFF
val INST_ACCESS_MASK7 = 0xFFFFFFFF
val LOAD_TO_USE_PLUS1 = 0x0
val LSU2DMA = 0x0
val LSU_BUS_ID = 0x1
val LSU_BUS_PRTY = 0x2
val LSU_BUS_TAG = 0x3
val LSU_NUM_NBLOAD = 0x04
val LSU_NUM_NBLOAD_WIDTH = 0x2
val LSU_SB_BITS = 0x10
val LSU_STBUF_DEPTH = 0x4
val NO_ICCM_NO_ICACHE = 0x0
val PIC_2CYCLE = 0x0
val PIC_BASE_ADDR = 0xF00C0000
val PIC_BITS = 0x0F
val PIC_INT_WORDS = 0x1
val PIC_REGION = 0xF
val PIC_SIZE = 0x020
val PIC_TOTAL_INT = 0x1F
val PIC_TOTAL_INT_PLUS1 = 0x020
val RET_STACK_SIZE = 0x8
val SB_BUS_ID = 0x1
val SB_BUS_PRTY = 0x2
val SB_BUS_TAG = 0x1
val TIMER_LEGAL_EN = 0x1
}

2
src/main/scala/lsu/lsu_bus_buffer.scala
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@ -562,7 +562,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
bus_rsp_read_tag := io.lsu_axi.r.bits.id bus_rsp_read_tag := io.lsu_axi.r.bits.id
bus_rsp_write_tag := io.lsu_axi.b.bits.id bus_rsp_write_tag := io.lsu_axi.b.bits.id
bus_rsp_write_error := bus_rsp_write & (io.lsu_axi.b.bits.resp =/= 0.U) bus_rsp_write_error := bus_rsp_write & (io.lsu_axi.b.bits.resp =/= 0.U)
bus_rsp_read_error := bus_rsp_read & (io.lsu_axi.b.bits.resp =/= 0.U) bus_rsp_read_error := bus_rsp_read & (io.lsu_axi.r.bits.resp =/= 0.U)
bus_rsp_rdata := io.lsu_axi.r.bits.data bus_rsp_rdata := io.lsu_axi.r.bits.data
// AXI Command signals // AXI Command signals

10
src/main/scala/mem.scala
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@ -36,16 +36,16 @@ object quasar extends lib {
"ICACHE_NUM_WAYS" -> ICACHE_NUM_WAYS, "ICACHE_NUM_WAYS" -> ICACHE_NUM_WAYS,
"ICACHE_BANKS_WAY" -> ICACHE_BANKS_WAY, "ICACHE_BANKS_WAY" -> ICACHE_BANKS_WAY,
"ICACHE_INDEX_HI" -> ICACHE_INDEX_HI, "ICACHE_INDEX_HI" -> ICACHE_INDEX_HI,
"DCCM_ENABLE" -> bool2int(DCCM_ENABLE), "DCCM_ENABLE" -> DCCM_ENABLE,
"ICACHE_ENABLE" -> bool2int(ICCM_ENABLE), "ICACHE_ENABLE" -> ICCM_ENABLE,
"ICCM_ENABLE" -> bool2int(ICCM_ENABLE), "ICCM_ENABLE" -> ICCM_ENABLE,
"ICACHE_TAG_INDEX_LO" -> ICACHE_TAG_INDEX_LO, "ICACHE_TAG_INDEX_LO" -> ICACHE_TAG_INDEX_LO,
"ICACHE_DATA_INDEX_LO" -> ICACHE_DATA_INDEX_LO, "ICACHE_DATA_INDEX_LO" -> ICACHE_DATA_INDEX_LO,
"ICACHE_TAG_LO" -> ICACHE_TAG_LO, "ICACHE_TAG_LO" -> ICACHE_TAG_LO,
"ICACHE_BANK_LO" -> ICACHE_BANK_LO, "ICACHE_BANK_LO" -> ICACHE_BANK_LO,
"ICACHE_BANK_HI" -> ICACHE_BANK_HI, "ICACHE_BANK_HI" -> ICACHE_BANK_HI,
"ICACHE_WAYPACK" -> bool2int(ICACHE_WAYPACK), "ICACHE_WAYPACK" -> ICACHE_WAYPACK,
"ICACHE_ECC" -> bool2int(ICACHE_ECC), "ICACHE_ECC" -> ICACHE_ECC,
"ICACHE_DATA_DEPTH" -> ICACHE_DATA_DEPTH, "ICACHE_DATA_DEPTH" -> ICACHE_DATA_DEPTH,
"ICACHE_BANK_BITS" -> ICACHE_BANK_BITS, "ICACHE_BANK_BITS" -> ICACHE_BANK_BITS,
"ICACHE_BEAT_ADDR_HI" -> ICACHE_BEAT_ADDR_HI, "ICACHE_BEAT_ADDR_HI" -> ICACHE_BEAT_ADDR_HI,

76
src/main/scala/quasar.scala
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@ -314,7 +314,7 @@ class quasar extends Module with RequireAsyncReset with lib {
if(BUILD_AHB_LITE) { when(BUILD_AHB_LITE.B) {
val lsu_axi4_to_ahb = Module(new axi4_to_ahb()) val lsu_axi4_to_ahb = Module(new axi4_to_ahb())
lsu_axi4_to_ahb.io.axi_awvalid := io.lsu_axi.aw.valid lsu_axi4_to_ahb.io.axi_awvalid := io.lsu_axi.aw.valid
lsu_axi4_to_ahb.io.scan_mode := io.scan_mode lsu_axi4_to_ahb.io.scan_mode := io.scan_mode
@ -437,43 +437,47 @@ class quasar extends Module with RequireAsyncReset with lib {
lsu.io.axi.r.bits.resp := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rresp, io.lsu_axi.r.bits.resp) lsu.io.axi.r.bits.resp := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rresp, io.lsu_axi.r.bits.resp)
lsu.io.axi.r.bits.last := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rlast, io.lsu_axi.r.bits.last) lsu.io.axi.r.bits.last := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rlast, io.lsu_axi.r.bits.last)
ifu.io.ifu.aw.ready := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_awready, io.ifu_axi.aw.ready)
ifu.io.ifu.w.ready := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_wready, io.ifu_axi.w.ready)
ifu.io.ifu.ar.ready := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_arready, io.ifu_axi.ar.ready) ifu.io.ifu.ar.ready := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_arready, io.ifu_axi.ar.ready)
ifu.io.ifu.r.valid := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rvalid, io.ifu_axi.r.valid) ifu.io.ifu.r.valid := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rvalid, io.ifu_axi.r.valid)
ifu.io.ifu.r.bits.id := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rid, io.ifu_axi.r.bits.id) ifu.io.ifu.r.bits.id := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rid, io.ifu_axi.r.bits.id)
ifu.io.ifu.r.bits.data := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rdata, io.ifu_axi.r.bits.data) ifu.io.ifu.r.bits.data := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rdata, io.ifu_axi.r.bits.data)
ifu.io.ifu.r.bits.resp := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rresp, io.ifu_axi.r.bits.resp) ifu.io.ifu.r.bits.resp := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rresp, io.ifu_axi.r.bits.resp)
ifu.io.ifu.r.bits.last := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rlast, io.ifu_axi.r.bits.last)
dbg.io.sb_axi.aw.ready := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_awready, io.sb_axi.aw.ready) dbg.io.sb_axi.aw.ready := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_awready, io.sb_axi.aw.ready)
dbg.io.sb_axi.w.ready := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_wready, io.sb_axi.w.ready) dbg.io.sb_axi.w.ready := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_wready, io.sb_axi.w.ready)
dbg.io.sb_axi.b.valid := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_bready, io.sb_axi.b.ready) dbg.io.sb_axi.b.valid := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_bvalid, io.sb_axi.b.valid)
dbg.io.sb_axi.b.bits.resp := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_bresp, io.sb_axi.b.bits.resp) dbg.io.sb_axi.b.bits.resp := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_bresp, io.sb_axi.b.bits.resp)
dbg.io.sb_axi.ar.ready := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rready, io.sb_axi.r.ready) dbg.io.sb_axi.ar.ready := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_arready, io.sb_axi.ar.ready)
dbg.io.sb_axi.r.valid := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rvalid, io.sb_axi.r.valid) dbg.io.sb_axi.r.valid := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rvalid, io.sb_axi.r.valid)
dbg.io.sb_axi.r.bits.id := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rid, io.sb_axi.r.bits.id)
dbg.io.sb_axi.r.bits.data := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rdata, io.sb_axi.r.bits.data) dbg.io.sb_axi.r.bits.data := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rdata, io.sb_axi.r.bits.data)
dbg.io.sb_axi.r.bits.resp := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rresp, io.sb_axi.r.bits.resp) dbg.io.sb_axi.r.bits.resp := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rresp, io.sb_axi.r.bits.resp)
dma_ctrl.io.dma_axi.aw.valid := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awvalid, io.dma_axi.aw.valid) dma_ctrl.io.dma_axi.aw.valid := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awvalid, io.dma_axi.aw.valid)
dma_ctrl.io.dma_axi.aw.bits.id := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awid, io.dma_axi.aw.valid) dma_ctrl.io.dma_axi.aw.bits.id := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awid, io.dma_axi.aw.bits.id)
dma_ctrl.io.dma_axi.aw.bits.addr := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awaddr, io.dma_axi.aw.valid) dma_ctrl.io.dma_axi.aw.bits.addr := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awaddr, io.dma_axi.aw.bits.addr)
dma_ctrl.io.dma_axi.aw.bits.size := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awsize, io.dma_axi.aw.valid) dma_ctrl.io.dma_axi.aw.bits.size := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awsize, io.dma_axi.aw.bits.size)
dma_ctrl.io.dma_axi.w.valid := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_wvalid, io.dma_axi.aw.valid) dma_ctrl.io.dma_axi.w.valid := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_wvalid, io.dma_axi.w.valid)
dma_ctrl.io.dma_axi.w.bits.data := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_wdata, io.dma_axi.aw.valid) dma_ctrl.io.dma_axi.w.bits.data := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_wdata, io.dma_axi.w.bits.data)
dma_ctrl.io.dma_axi.w.bits.strb := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_wstrb, io.dma_axi.aw.valid) dma_ctrl.io.dma_axi.w.bits.strb := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_wstrb, io.dma_axi.w.bits.strb)
dma_ctrl.io.dma_axi.b.ready := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_bready, io.dma_axi.aw.valid) dma_ctrl.io.dma_axi.b.ready := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_bready, io.dma_axi.b.ready)
dma_ctrl.io.dma_axi.ar.valid := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arvalid, io.dma_axi.aw.valid) dma_ctrl.io.dma_axi.ar.valid := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arvalid, io.dma_axi.ar.valid)
dma_ctrl.io.dma_axi.ar.bits.id := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arid, io.dma_axi.aw.valid) dma_ctrl.io.dma_axi.ar.bits.id := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arid, io.dma_axi.ar.bits.id)
dma_ctrl.io.dma_axi.ar.bits.addr := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_araddr, io.dma_axi.aw.valid) dma_ctrl.io.dma_axi.ar.bits.addr := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_araddr, io.dma_axi.aw.bits.addr)
dma_ctrl.io.dma_axi.ar.bits.size := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arsize, io.dma_axi.aw.valid) dma_ctrl.io.dma_axi.ar.bits.size := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arsize, io.dma_axi.aw.bits.size)
dma_ctrl.io.dma_axi.r.ready := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arready, io.dma_axi.aw.valid) dma_ctrl.io.dma_axi.r.ready := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_rready, io.dma_axi.r.ready)
// AHB Signals // AHB Signals
io.haddr := ifu_axi4_to_ahb.io.ahb_haddr
io.hburst := ifu_axi4_to_ahb.io.ahb_hburst io.hburst := ifu_axi4_to_ahb.io.ahb_hburst
io.hmastlock := ifu_axi4_to_ahb.io.ahb_hmastlock io.hmastlock := ifu_axi4_to_ahb.io.ahb_hmastlock
io.hprot := ifu_axi4_to_ahb.io.ahb_hprot io.hprot := ifu_axi4_to_ahb.io.ahb_hprot
io.hsize := ifu_axi4_to_ahb.io.ahb_hsize io.hsize := ifu_axi4_to_ahb.io.ahb_hsize
io.htrans := ifu_axi4_to_ahb.io.ahb_htrans io.htrans := ifu_axi4_to_ahb.io.ahb_htrans
io.hwrite := ifu_axi4_to_ahb.io.ahb_hwrite io.hwrite := ifu_axi4_to_ahb.io.ahb_hwrite
io.haddr := ifu_axi4_to_ahb.io.ahb_haddr
io.lsu_haddr := lsu_axi4_to_ahb.io.ahb_haddr io.lsu_haddr := lsu_axi4_to_ahb.io.ahb_haddr
io.lsu_hburst := lsu_axi4_to_ahb.io.ahb_hburst io.lsu_hburst := lsu_axi4_to_ahb.io.ahb_hburst
@ -496,9 +500,43 @@ class quasar extends Module with RequireAsyncReset with lib {
io.dma_hrdata := dma_ahb_to_axi4.io.ahb_hrdata io.dma_hrdata := dma_ahb_to_axi4.io.ahb_hrdata
io.dma_hreadyout := dma_ahb_to_axi4.io.ahb_hreadyout io.dma_hreadyout := dma_ahb_to_axi4.io.ahb_hreadyout
io.dma_hresp := dma_ahb_to_axi4.io.ahb_hresp io.dma_hresp := dma_ahb_to_axi4.io.ahb_hresp
io.dma_hresp := 0.U//dma_ahb_to_axi4.io.ahb_hrdata // io.dma_hresp := 0.U//dma_ahb_to_axi4.io.ahb_hrdata
io.dmi_reg_rdata := 0.U//dma_ahb_to_axi4.io.ahb_rdata // io.dmi_reg_rdata := 0.U//dma_ahb_to_axi4.io.ahb_rdata
} }
.otherwise{
// AHB Signals
io.haddr := 0.U
io.hburst := 0.U
io.hmastlock := 0.U
io.hprot := 0.U
io.hsize := 0.U
io.htrans := 0.U
io.hwrite := 0.U
io.lsu_haddr := 0.U
io.lsu_hburst := 0.U
io.lsu_hmastlock := 0.U
io.lsu_hprot := 0.U
io.lsu_hsize := 0.U
io.lsu_htrans := 0.U
io.lsu_hwrite := 0.U
io.lsu_hwdata := 0.U
io.sb_haddr := 0.U
io.sb_hburst := 0.U
io.sb_hmastlock := 0.U
io.sb_hprot := 0.U
io.sb_hsize := 0.U
io.sb_htrans := 0.U
io.sb_hwrite := 0.U
io.sb_hwdata := 0.U
io.dma_hrdata := 0.U
io.dma_hreadyout := 0.U
io.dma_hresp := 0.U
}
io.dmi_reg_rdata := 0.U
} }

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