QUASAR added
This commit is contained in:
parent
6ad23a0226
commit
d0a9d54b91
|
@ -1,90 +0,0 @@
|
||||||
// SPDX-License-Identifier: Apache-2.0
|
|
||||||
// Copyright 2018 Western Digital Corporation or it's affiliates.
|
|
||||||
//
|
|
||||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
// you may not use this file except in compliance with the License.
|
|
||||||
// You may obtain a copy of the License at
|
|
||||||
//
|
|
||||||
// http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
//
|
|
||||||
// Unless required by applicable law or agreed to in writing, software
|
|
||||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
// See the License for the specific language governing permissions and
|
|
||||||
// limitations under the License.
|
|
||||||
//------------------------------------------------------------------------------------
|
|
||||||
//
|
|
||||||
// Copyright Western Digital, 2018
|
|
||||||
// Owner : Anusha Narayanamoorthy
|
|
||||||
// Description:
|
|
||||||
// Wrapper module for JTAG_TAP and DMI synchronizer
|
|
||||||
//
|
|
||||||
//-------------------------------------------------------------------------------------
|
|
||||||
|
|
||||||
module dmi_wrapper(
|
|
||||||
|
|
||||||
// JTAG signals
|
|
||||||
input trst_n, // JTAG reset
|
|
||||||
input tck, // JTAG clock
|
|
||||||
input tms, // Test mode select
|
|
||||||
input tdi, // Test Data Input
|
|
||||||
output tdo, // Test Data Output
|
|
||||||
output tdoEnable, // Test Data Output enable
|
|
||||||
|
|
||||||
// Processor Signals
|
|
||||||
input core_rst_n, // Core reset
|
|
||||||
input core_clk, // Core clock
|
|
||||||
input [31:1] jtag_id, // JTAG ID
|
|
||||||
input [31:0] rd_data, // 32 bit Read data from Processor
|
|
||||||
output [31:0] reg_wr_data, // 32 bit Write data to Processor
|
|
||||||
output [6:0] reg_wr_addr, // 7 bit reg address to Processor
|
|
||||||
output reg_en, // 1 bit Read enable to Processor
|
|
||||||
output reg_wr_en, // 1 bit Write enable to Processor
|
|
||||||
output dmi_hard_reset
|
|
||||||
);
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
//Wire Declaration
|
|
||||||
wire rd_en;
|
|
||||||
wire wr_en;
|
|
||||||
wire dmireset;
|
|
||||||
|
|
||||||
|
|
||||||
//jtag_tap instantiation
|
|
||||||
rvjtag_tap i_jtag_tap(
|
|
||||||
.trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
|
|
||||||
.tck(tck), // dedicated JTAG TCK pad signal
|
|
||||||
.tms(tms), // dedicated JTAG TMS pad signal
|
|
||||||
.tdi(tdi), // dedicated JTAG TDI pad signal
|
|
||||||
.tdo(tdo), // dedicated JTAG TDO pad signal
|
|
||||||
.tdoEnable(tdoEnable), // enable for TDO pad
|
|
||||||
.wr_data(reg_wr_data), // 32 bit Write data
|
|
||||||
.wr_addr(reg_wr_addr), // 7 bit Write address
|
|
||||||
.rd_en(rd_en), // 1 bit read enable
|
|
||||||
.wr_en(wr_en), // 1 bit Write enable
|
|
||||||
.rd_data(rd_data), // 32 bit Read data
|
|
||||||
.rd_status(2'b0),
|
|
||||||
.idle(3'h0), // no need to wait to sample data
|
|
||||||
.dmi_stat(2'b0), // no need to wait or error possible
|
|
||||||
.version(4'h1), // debug spec 0.13 compliant
|
|
||||||
.jtag_id(jtag_id),
|
|
||||||
.dmi_hard_reset(dmi_hard_reset),
|
|
||||||
.dmi_reset(dmireset)
|
|
||||||
);
|
|
||||||
|
|
||||||
|
|
||||||
// dmi_jtag_to_core_sync instantiation
|
|
||||||
dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync(
|
|
||||||
.wr_en(wr_en), // 1 bit Write enable
|
|
||||||
.rd_en(rd_en), // 1 bit Read enable
|
|
||||||
|
|
||||||
.rst_n(core_rst_n),
|
|
||||||
.clk(core_clk),
|
|
||||||
.reg_en(reg_en), // 1 bit Write interface bit
|
|
||||||
.reg_wr_en(reg_wr_en) // 1 bit Write enable
|
|
||||||
);
|
|
||||||
|
|
||||||
endmodule
|
|
|
@ -1,3 +0,0 @@
|
||||||
/home/users/laraib.khan/Videos/Quasar/design/gated_latch.sv
|
|
||||||
/home/users/laraib.khan/Videos/Quasar/design/dmi_wrapper.sv
|
|
||||||
/home/users/laraib.khan/Videos/Quasar/design/mem.sv
|
|
|
@ -1,14 +0,0 @@
|
||||||
module gated_latch
|
|
||||||
(
|
|
||||||
input logic SE, EN, CK,
|
|
||||||
output Q
|
|
||||||
);
|
|
||||||
logic en_ff;
|
|
||||||
logic enable;
|
|
||||||
assign enable = EN | SE;
|
|
||||||
always @(CK, enable) begin
|
|
||||||
if(!CK)
|
|
||||||
en_ff = enable;
|
|
||||||
end
|
|
||||||
assign Q = CK & en_ff;
|
|
||||||
endmodule
|
|
547
design/mem.sv
547
design/mem.sv
|
@ -1,547 +0,0 @@
|
||||||
//********************************************************************************
|
|
||||||
// SPDX-License-Identifier: Apache-2.0
|
|
||||||
// Copyright 2020 Western Digital Corporation or its affiliates.
|
|
||||||
//
|
|
||||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
// you may not use this file except in compliance with the License.
|
|
||||||
// You may obtain a copy of the License at
|
|
||||||
//
|
|
||||||
// http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
//
|
|
||||||
// Unless required by applicable law or agreed to in writing, software
|
|
||||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
// See the License for the specific language governing permissions and
|
|
||||||
// limitations under the License.
|
|
||||||
//********************************************************************************
|
|
||||||
|
|
||||||
typedef struct packed {
|
|
||||||
logic TEST1;
|
|
||||||
logic RME;
|
|
||||||
logic [3:0] RM;
|
|
||||||
|
|
||||||
logic LS;
|
|
||||||
logic DS;
|
|
||||||
logic SD;
|
|
||||||
logic TEST_RNM;
|
|
||||||
logic BC1;
|
|
||||||
logic BC2;
|
|
||||||
} iccm_ext_in_pkt_t;
|
|
||||||
|
|
||||||
typedef struct packed {
|
|
||||||
logic TEST1;
|
|
||||||
logic RME;
|
|
||||||
logic [3:0] RM;
|
|
||||||
logic LS;
|
|
||||||
logic DS;
|
|
||||||
logic SD;
|
|
||||||
logic TEST_RNM;
|
|
||||||
logic BC1;
|
|
||||||
logic BC2;
|
|
||||||
} dccm_ext_in_pkt_t;
|
|
||||||
|
|
||||||
|
|
||||||
typedef struct packed {
|
|
||||||
logic TEST1;
|
|
||||||
logic RME;
|
|
||||||
logic [3:0] RM;
|
|
||||||
logic LS;
|
|
||||||
logic DS;
|
|
||||||
logic SD;
|
|
||||||
logic TEST_RNM;
|
|
||||||
logic BC1;
|
|
||||||
logic BC2;
|
|
||||||
} ic_data_ext_in_pkt_t;
|
|
||||||
|
|
||||||
|
|
||||||
typedef struct packed {
|
|
||||||
logic TEST1;
|
|
||||||
logic RME;
|
|
||||||
logic [3:0] RM;
|
|
||||||
logic LS;
|
|
||||||
logic DS;
|
|
||||||
logic SD;
|
|
||||||
logic TEST_RNM;
|
|
||||||
logic BC1;
|
|
||||||
logic BC2;
|
|
||||||
} ic_tag_ext_in_pkt_t;
|
|
||||||
module mem#(
|
|
||||||
parameter ICACHE_BEAT_BITS,
|
|
||||||
parameter ICCM_BITS,
|
|
||||||
parameter ICACHE_NUM_WAYS,
|
|
||||||
parameter DCCM_BYTE_WIDTH,
|
|
||||||
parameter ICCM_BANK_INDEX_LO,
|
|
||||||
parameter ICACHE_BANK_BITS,
|
|
||||||
parameter DCCM_BITS,
|
|
||||||
parameter ICACHE_BEAT_ADDR_HI,
|
|
||||||
parameter ICCM_INDEX_BITS,
|
|
||||||
parameter ICCM_BANK_HI,
|
|
||||||
parameter ICACHE_BANKS_WAY,
|
|
||||||
parameter ICACHE_INDEX_HI,
|
|
||||||
parameter DCCM_NUM_BANKS,
|
|
||||||
parameter ICACHE_BANK_HI,
|
|
||||||
parameter ICACHE_BANK_LO,
|
|
||||||
parameter DCCM_ENABLE= 'b1,
|
|
||||||
parameter ICACHE_TAG_LO,
|
|
||||||
parameter ICACHE_DATA_INDEX_LO,
|
|
||||||
parameter ICCM_NUM_BANKS,
|
|
||||||
parameter ICACHE_ECC,
|
|
||||||
parameter ICACHE_ENABLE= 'b1,
|
|
||||||
parameter DCCM_BANK_BITS,
|
|
||||||
parameter ICCM_ENABLE= 'b1,
|
|
||||||
parameter ICCM_BANK_BITS,
|
|
||||||
parameter ICACHE_TAG_DEPTH,
|
|
||||||
parameter ICACHE_WAYPACK,
|
|
||||||
parameter DCCM_SIZE,
|
|
||||||
parameter DCCM_FDATA_WIDTH,
|
|
||||||
parameter ICACHE_TAG_INDEX_LO,
|
|
||||||
parameter ICACHE_DATA_DEPTH,
|
|
||||||
parameter DCCM_WIDTH_BITS,
|
|
||||||
parameter ICACHE_NUM_BYPASS,
|
|
||||||
parameter ICACHE_TAG_NUM_BYPASS,
|
|
||||||
parameter ICACHE_TAG_NUM_BYPASS_WIDTH,
|
|
||||||
parameter ICACHE_TAG_BYPASS_ENABLE,
|
|
||||||
parameter ICACHE_NUM_BYPASS_WIDTH,
|
|
||||||
parameter ICACHE_BYPASS_ENABLE,
|
|
||||||
parameter ICACHE_LN_SZ
|
|
||||||
)
|
|
||||||
|
|
||||||
(
|
|
||||||
input logic clk,
|
|
||||||
input logic rst_l,
|
|
||||||
input logic dccm_clk_override,
|
|
||||||
input logic icm_clk_override,
|
|
||||||
input logic dec_tlu_core_ecc_disable,
|
|
||||||
|
|
||||||
//DCCM ports
|
|
||||||
input logic dccm_wren,
|
|
||||||
input logic dccm_rden,
|
|
||||||
input logic [DCCM_BITS-1:0] dccm_wr_addr_lo,
|
|
||||||
input logic [DCCM_BITS-1:0] dccm_wr_addr_hi,
|
|
||||||
input logic [DCCM_BITS-1:0] dccm_rd_addr_lo,
|
|
||||||
input logic [DCCM_BITS-1:0] dccm_rd_addr_hi,
|
|
||||||
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
|
|
||||||
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
|
|
||||||
|
|
||||||
|
|
||||||
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
|
|
||||||
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
|
|
||||||
|
|
||||||
//`ifdef DCCM_ENABLE
|
|
||||||
//input dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt,
|
|
||||||
input logic dccm_ext_in_pkt_TEST1_0,
|
|
||||||
input logic dccm_ext_in_pkt_RME_0,
|
|
||||||
input logic [3:0] dccm_ext_in_pkt_RM_0,
|
|
||||||
input logic dccm_ext_in_pkt_LS_0,
|
|
||||||
input logic dccm_ext_in_pkt_DS_0,
|
|
||||||
input logic dccm_ext_in_pkt_SD_0,
|
|
||||||
input logic dccm_ext_in_pkt_TEST_RNM_0,
|
|
||||||
input logic dccm_ext_in_pkt_BC1_0,
|
|
||||||
input logic dccm_ext_in_pkt_BC2_0,
|
|
||||||
|
|
||||||
input logic dccm_ext_in_pkt_TEST1_1,
|
|
||||||
input logic dccm_ext_in_pkt_RME_1,
|
|
||||||
input logic [3:0] dccm_ext_in_pkt_RM_1,
|
|
||||||
input logic dccm_ext_in_pkt_LS_1,
|
|
||||||
input logic dccm_ext_in_pkt_DS_1,
|
|
||||||
input logic dccm_ext_in_pkt_SD_1,
|
|
||||||
input logic dccm_ext_in_pkt_TEST_RNM_1,
|
|
||||||
input logic dccm_ext_in_pkt_BC1_1,
|
|
||||||
input logic dccm_ext_in_pkt_BC2_1,
|
|
||||||
|
|
||||||
input logic dccm_ext_in_pkt_TEST1_2,
|
|
||||||
input logic dccm_ext_in_pkt_RME_2,
|
|
||||||
input logic [3:0] dccm_ext_in_pkt_RM_2,
|
|
||||||
input logic dccm_ext_in_pkt_LS_2,
|
|
||||||
input logic dccm_ext_in_pkt_DS_2,
|
|
||||||
input logic dccm_ext_in_pkt_SD_2,
|
|
||||||
input logic dccm_ext_in_pkt_TEST_RNM_2,
|
|
||||||
input logic dccm_ext_in_pkt_BC1_2,
|
|
||||||
input logic dccm_ext_in_pkt_BC2_2,
|
|
||||||
|
|
||||||
input logic dccm_ext_in_pkt_TEST1_3,
|
|
||||||
input logic dccm_ext_in_pkt_RME_3,
|
|
||||||
input logic [3:0] dccm_ext_in_pkt_RM_3,
|
|
||||||
input logic dccm_ext_in_pkt_LS_3,
|
|
||||||
input logic dccm_ext_in_pkt_DS_3,
|
|
||||||
input logic dccm_ext_in_pkt_SD_3,
|
|
||||||
input logic dccm_ext_in_pkt_TEST_RNM_3,
|
|
||||||
input logic dccm_ext_in_pkt_BC1_3,
|
|
||||||
input logic dccm_ext_in_pkt_BC2_3,
|
|
||||||
|
|
||||||
//`endif
|
|
||||||
|
|
||||||
//ICCM ports
|
|
||||||
input logic iccm_ext_in_pkt_TEST1_0,
|
|
||||||
input logic iccm_ext_in_pkt_RME_0,
|
|
||||||
input logic [3:0] iccm_ext_in_pkt_RM_0,
|
|
||||||
input logic iccm_ext_in_pkt_LS_0,
|
|
||||||
input logic iccm_ext_in_pkt_DS_0,
|
|
||||||
input logic iccm_ext_in_pkt_SD_0,
|
|
||||||
input logic iccm_ext_in_pkt_TEST_RNM_0,
|
|
||||||
input logic iccm_ext_in_pkt_BC1_0,
|
|
||||||
input logic iccm_ext_in_pkt_BC2_0,
|
|
||||||
|
|
||||||
input logic iccm_ext_in_pkt_TEST1_1,
|
|
||||||
input logic iccm_ext_in_pkt_RME_1,
|
|
||||||
input logic [3:0] iccm_ext_in_pkt_RM_1,
|
|
||||||
input logic iccm_ext_in_pkt_LS_1,
|
|
||||||
input logic iccm_ext_in_pkt_DS_1,
|
|
||||||
input logic iccm_ext_in_pkt_SD_1,
|
|
||||||
input logic iccm_ext_in_pkt_TEST_RNM_1,
|
|
||||||
input logic iccm_ext_in_pkt_BC1_1,
|
|
||||||
input logic iccm_ext_in_pkt_BC2_1,
|
|
||||||
|
|
||||||
input logic iccm_ext_in_pkt_TEST1_2,
|
|
||||||
input logic iccm_ext_in_pkt_RME_2,
|
|
||||||
input logic [3:0] iccm_ext_in_pkt_RM_2,
|
|
||||||
input logic iccm_ext_in_pkt_LS_2,
|
|
||||||
input logic iccm_ext_in_pkt_DS_2,
|
|
||||||
input logic iccm_ext_in_pkt_SD_2,
|
|
||||||
input logic iccm_ext_in_pkt_TEST_RNM_2,
|
|
||||||
input logic iccm_ext_in_pkt_BC1_2,
|
|
||||||
input logic iccm_ext_in_pkt_BC2_2,
|
|
||||||
|
|
||||||
input logic iccm_ext_in_pkt_TEST1_3,
|
|
||||||
input logic iccm_ext_in_pkt_RME_3,
|
|
||||||
input logic [3:0] iccm_ext_in_pkt_RM_3,
|
|
||||||
input logic iccm_ext_in_pkt_LS_3,
|
|
||||||
input logic iccm_ext_in_pkt_DS_3,
|
|
||||||
input logic iccm_ext_in_pkt_SD_3,
|
|
||||||
input logic iccm_ext_in_pkt_TEST_RNM_3,
|
|
||||||
input logic iccm_ext_in_pkt_BC1_3,
|
|
||||||
input logic iccm_ext_in_pkt_BC2_3,
|
|
||||||
|
|
||||||
input logic [ICCM_BITS-1:1] iccm_rw_addr,
|
|
||||||
input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
|
|
||||||
input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle
|
|
||||||
input logic iccm_wren,
|
|
||||||
input logic iccm_rden,
|
|
||||||
input logic [2:0] iccm_wr_size,
|
|
||||||
input logic [77:0] iccm_wr_data,
|
|
||||||
|
|
||||||
output logic [63:0] iccm_rd_data,
|
|
||||||
output logic [77:0] iccm_rd_data_ecc,
|
|
||||||
|
|
||||||
// Icache and Itag Ports
|
|
||||||
|
|
||||||
input logic [31:1] ic_rw_addr,
|
|
||||||
input logic [ICACHE_NUM_WAYS-1:0] ic_tag_valid,
|
|
||||||
input logic [ICACHE_NUM_WAYS-1:0] ic_wr_en,
|
|
||||||
input logic ic_rd_en,
|
|
||||||
input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
|
|
||||||
input logic ic_sel_premux_data, // Premux data sel
|
|
||||||
// input ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt,
|
|
||||||
input logic ic_tag_ext_in_pkt_TEST1_0,
|
|
||||||
input logic ic_tag_ext_in_pkt_RME_0,
|
|
||||||
input logic [3:0] ic_tag_ext_in_pkt_RM_0,
|
|
||||||
input logic ic_tag_ext_in_pkt_LS_0,
|
|
||||||
input logic ic_tag_ext_in_pkt_DS_0,
|
|
||||||
input logic ic_tag_ext_in_pkt_SD_0,
|
|
||||||
input logic ic_tag_ext_in_pkt_TEST_RNM_0,
|
|
||||||
input logic ic_tag_ext_in_pkt_BC1_0,
|
|
||||||
input logic ic_tag_ext_in_pkt_BC2_0,
|
|
||||||
|
|
||||||
input logic ic_tag_ext_in_pkt_TEST1_1,
|
|
||||||
input logic ic_tag_ext_in_pkt_RME_1,
|
|
||||||
input logic [3:0] ic_tag_ext_in_pkt_RM_1,
|
|
||||||
input logic ic_tag_ext_in_pkt_LS_1,
|
|
||||||
input logic ic_tag_ext_in_pkt_DS_1,
|
|
||||||
input logic ic_tag_ext_in_pkt_SD_1,
|
|
||||||
input logic ic_tag_ext_in_pkt_TEST_RNM_1,
|
|
||||||
input logic ic_tag_ext_in_pkt_BC1_1,
|
|
||||||
input logic ic_tag_ext_in_pkt_BC2_1,
|
|
||||||
|
|
||||||
input logic ic_data_ext_in_pkt_0_TEST1_0,
|
|
||||||
input logic ic_data_ext_in_pkt_0_RME_0,
|
|
||||||
input logic [3:0] ic_data_ext_in_pkt_0_RM_0,
|
|
||||||
input logic ic_data_ext_in_pkt_0_LS_0,
|
|
||||||
input logic ic_data_ext_in_pkt_0_DS_0,
|
|
||||||
input logic ic_data_ext_in_pkt_0_SD_0,
|
|
||||||
input logic ic_data_ext_in_pkt_0_TEST_RNM_0,
|
|
||||||
input logic ic_data_ext_in_pkt_0_BC1_0,
|
|
||||||
input logic ic_data_ext_in_pkt_0_BC2_0,
|
|
||||||
|
|
||||||
input logic ic_data_ext_in_pkt_0_TEST1_1,
|
|
||||||
input logic ic_data_ext_in_pkt_0_RME_1,
|
|
||||||
input logic [3:0] ic_data_ext_in_pkt_0_RM_1,
|
|
||||||
input logic ic_data_ext_in_pkt_0_LS_1,
|
|
||||||
input logic ic_data_ext_in_pkt_0_DS_1,
|
|
||||||
input logic ic_data_ext_in_pkt_0_SD_1,
|
|
||||||
input logic ic_data_ext_in_pkt_0_TEST_RNM_1,
|
|
||||||
input logic ic_data_ext_in_pkt_0_BC1_1,
|
|
||||||
input logic ic_data_ext_in_pkt_0_BC2_1,
|
|
||||||
|
|
||||||
input logic ic_data_ext_in_pkt_1_TEST1_0,
|
|
||||||
input logic ic_data_ext_in_pkt_1_RME_0,
|
|
||||||
input logic [3:0] ic_data_ext_in_pkt_1_RM_0,
|
|
||||||
input logic ic_data_ext_in_pkt_1_LS_0,
|
|
||||||
input logic ic_data_ext_in_pkt_1_DS_0,
|
|
||||||
input logic ic_data_ext_in_pkt_1_SD_0,
|
|
||||||
input logic ic_data_ext_in_pkt_1_TEST_RNM_0,
|
|
||||||
input logic ic_data_ext_in_pkt_1_BC1_0,
|
|
||||||
input logic ic_data_ext_in_pkt_1_BC2_0,
|
|
||||||
|
|
||||||
input logic ic_data_ext_in_pkt_1_TEST1_1,
|
|
||||||
input logic ic_data_ext_in_pkt_1_RME_1,
|
|
||||||
input logic [3:0] ic_data_ext_in_pkt_1_RM_1,
|
|
||||||
input logic ic_data_ext_in_pkt_1_LS_1,
|
|
||||||
input logic ic_data_ext_in_pkt_1_DS_1,
|
|
||||||
input logic ic_data_ext_in_pkt_1_SD_1,
|
|
||||||
input logic ic_data_ext_in_pkt_1_TEST_RNM_1,
|
|
||||||
input logic ic_data_ext_in_pkt_1_BC1_1,
|
|
||||||
input logic ic_data_ext_in_pkt_1_BC2_1,
|
|
||||||
|
|
||||||
// input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
|
|
||||||
input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC
|
|
||||||
input logic [70:0] ic_wr_data_1, // Data to fill to the Icache. With ECC
|
|
||||||
input logic [70:0] ic_debug_wr_data, // Debug wr cache.
|
|
||||||
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
|
|
||||||
input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
|
|
||||||
input logic ic_debug_rd_en, // Icache debug rd
|
|
||||||
input logic ic_debug_wr_en, // Icache debug wr
|
|
||||||
input logic ic_debug_tag_array, // Debug tag array
|
|
||||||
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
|
|
||||||
|
|
||||||
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
|
|
||||||
output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag.
|
|
||||||
|
|
||||||
|
|
||||||
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
|
|
||||||
output logic [ICACHE_BANKS_WAY-1:0] ic_parerr, // parity error per bank
|
|
||||||
output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit,
|
|
||||||
output logic ic_tag_perr, // Icache Tag parity error
|
|
||||||
|
|
||||||
|
|
||||||
input logic scan_mode
|
|
||||||
|
|
||||||
);
|
|
||||||
|
|
||||||
iccm_ext_in_pkt_t [ICCM_NUM_BANKS-1:0] iccm_ext_in_pkt;
|
|
||||||
dccm_ext_in_pkt_t [DCCM_NUM_BANKS-1:0] dccm_ext_in_pkt;
|
|
||||||
ic_data_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0][ICACHE_BANKS_WAY-1:0] ic_data_ext_in_pkt;
|
|
||||||
ic_tag_ext_in_pkt_t [ICACHE_NUM_WAYS-1:0] ic_tag_ext_in_pkt;
|
|
||||||
|
|
||||||
|
|
||||||
assign dccm_ext_in_pkt[0].TEST1 = dccm_ext_in_pkt_TEST1_0;
|
|
||||||
assign dccm_ext_in_pkt[0].RME = dccm_ext_in_pkt_RME_0;
|
|
||||||
assign dccm_ext_in_pkt[0].RM = dccm_ext_in_pkt_RM_0[3:0];
|
|
||||||
assign dccm_ext_in_pkt[0].LS = dccm_ext_in_pkt_LS_0;
|
|
||||||
assign dccm_ext_in_pkt[0].DS = dccm_ext_in_pkt_DS_0;
|
|
||||||
assign dccm_ext_in_pkt[0].SD = dccm_ext_in_pkt_SD_0;
|
|
||||||
assign dccm_ext_in_pkt[0].TEST_RNM = dccm_ext_in_pkt_TEST_RNM_0;
|
|
||||||
assign dccm_ext_in_pkt[0].BC1 = dccm_ext_in_pkt_BC1_0;
|
|
||||||
assign dccm_ext_in_pkt[0].BC2 = dccm_ext_in_pkt_BC2_0;
|
|
||||||
|
|
||||||
assign dccm_ext_in_pkt[1].TEST1 = dccm_ext_in_pkt_TEST1_1;
|
|
||||||
assign dccm_ext_in_pkt[1].RME = dccm_ext_in_pkt_RME_1;
|
|
||||||
assign dccm_ext_in_pkt[1].RM = dccm_ext_in_pkt_RM_1[3:0];
|
|
||||||
assign dccm_ext_in_pkt[1].LS = dccm_ext_in_pkt_LS_1;
|
|
||||||
assign dccm_ext_in_pkt[1].DS = dccm_ext_in_pkt_DS_1;
|
|
||||||
assign dccm_ext_in_pkt[1].SD = dccm_ext_in_pkt_SD_1;
|
|
||||||
assign dccm_ext_in_pkt[1].TEST_RNM = dccm_ext_in_pkt_TEST_RNM_1;
|
|
||||||
assign dccm_ext_in_pkt[1].BC1 = dccm_ext_in_pkt_BC1_1;
|
|
||||||
assign dccm_ext_in_pkt[1].BC2 = dccm_ext_in_pkt_BC2_1;
|
|
||||||
|
|
||||||
|
|
||||||
assign dccm_ext_in_pkt[2].TEST1 = dccm_ext_in_pkt_TEST1_2;
|
|
||||||
assign dccm_ext_in_pkt[2].RME = dccm_ext_in_pkt_RME_2;
|
|
||||||
assign dccm_ext_in_pkt[2].RM = dccm_ext_in_pkt_RM_2[3:0];
|
|
||||||
assign dccm_ext_in_pkt[2].LS = dccm_ext_in_pkt_LS_2;
|
|
||||||
assign dccm_ext_in_pkt[2].DS = dccm_ext_in_pkt_DS_2;
|
|
||||||
assign dccm_ext_in_pkt[2].SD = dccm_ext_in_pkt_SD_2;
|
|
||||||
assign dccm_ext_in_pkt[2].TEST_RNM = dccm_ext_in_pkt_TEST_RNM_2;
|
|
||||||
assign dccm_ext_in_pkt[2].BC1 = dccm_ext_in_pkt_BC1_2;
|
|
||||||
assign dccm_ext_in_pkt[2].BC2 = dccm_ext_in_pkt_BC2_2;
|
|
||||||
|
|
||||||
assign dccm_ext_in_pkt[3].TEST1 = dccm_ext_in_pkt_TEST1_3;
|
|
||||||
assign dccm_ext_in_pkt[3].RME = dccm_ext_in_pkt_RME_3;
|
|
||||||
assign dccm_ext_in_pkt[3].RM = dccm_ext_in_pkt_RM_3[3:0];
|
|
||||||
assign dccm_ext_in_pkt[3].LS = dccm_ext_in_pkt_LS_3;
|
|
||||||
assign dccm_ext_in_pkt[3].DS = dccm_ext_in_pkt_DS_3;
|
|
||||||
assign dccm_ext_in_pkt[3].SD = dccm_ext_in_pkt_SD_3;
|
|
||||||
assign dccm_ext_in_pkt[3].TEST_RNM = dccm_ext_in_pkt_TEST_RNM_3;
|
|
||||||
assign dccm_ext_in_pkt[3].BC1 = dccm_ext_in_pkt_BC1_3;
|
|
||||||
assign dccm_ext_in_pkt[3].BC2 = dccm_ext_in_pkt_BC2_3;
|
|
||||||
|
|
||||||
assign iccm_ext_in_pkt[0].TEST1 = iccm_ext_in_pkt_TEST1_0;
|
|
||||||
assign iccm_ext_in_pkt[0].RME = iccm_ext_in_pkt_RME_0;
|
|
||||||
assign iccm_ext_in_pkt[0].RM = iccm_ext_in_pkt_RM_0[3:0];
|
|
||||||
assign iccm_ext_in_pkt[0].LS = iccm_ext_in_pkt_LS_0;
|
|
||||||
assign iccm_ext_in_pkt[0].DS = iccm_ext_in_pkt_DS_0;
|
|
||||||
assign iccm_ext_in_pkt[0].SD = iccm_ext_in_pkt_SD_0;
|
|
||||||
assign iccm_ext_in_pkt[0].TEST_RNM = iccm_ext_in_pkt_TEST_RNM_0;
|
|
||||||
assign iccm_ext_in_pkt[0].BC1 = iccm_ext_in_pkt_BC1_0;
|
|
||||||
assign iccm_ext_in_pkt[0].BC2 = iccm_ext_in_pkt_BC2_0;
|
|
||||||
|
|
||||||
assign iccm_ext_in_pkt[1].TEST1 = iccm_ext_in_pkt_TEST1_1;
|
|
||||||
assign iccm_ext_in_pkt[1].RME = iccm_ext_in_pkt_RME_1;
|
|
||||||
assign iccm_ext_in_pkt[1].RM = iccm_ext_in_pkt_RM_1[3:0];
|
|
||||||
assign iccm_ext_in_pkt[1].LS = iccm_ext_in_pkt_LS_1;
|
|
||||||
assign iccm_ext_in_pkt[1].DS = iccm_ext_in_pkt_DS_1;
|
|
||||||
assign iccm_ext_in_pkt[1].SD = iccm_ext_in_pkt_SD_1;
|
|
||||||
assign iccm_ext_in_pkt[1].TEST_RNM = iccm_ext_in_pkt_TEST_RNM_1;
|
|
||||||
assign iccm_ext_in_pkt[1].BC1 = iccm_ext_in_pkt_BC1_1;
|
|
||||||
assign iccm_ext_in_pkt[1].BC2 = iccm_ext_in_pkt_BC2_1;
|
|
||||||
|
|
||||||
|
|
||||||
assign iccm_ext_in_pkt[2].TEST1 = iccm_ext_in_pkt_TEST1_2;
|
|
||||||
assign iccm_ext_in_pkt[2].RME = iccm_ext_in_pkt_RME_2;
|
|
||||||
assign iccm_ext_in_pkt[2].RM = iccm_ext_in_pkt_RM_2[3:0];
|
|
||||||
assign iccm_ext_in_pkt[2].LS = iccm_ext_in_pkt_LS_2;
|
|
||||||
assign iccm_ext_in_pkt[2].DS = iccm_ext_in_pkt_DS_2;
|
|
||||||
assign iccm_ext_in_pkt[2].SD = iccm_ext_in_pkt_SD_2;
|
|
||||||
assign iccm_ext_in_pkt[2].TEST_RNM = iccm_ext_in_pkt_TEST_RNM_2;
|
|
||||||
assign iccm_ext_in_pkt[2].BC1 = iccm_ext_in_pkt_BC1_2;
|
|
||||||
assign iccm_ext_in_pkt[2].BC2 = iccm_ext_in_pkt_BC2_2;
|
|
||||||
|
|
||||||
assign iccm_ext_in_pkt[3].TEST1 = iccm_ext_in_pkt_TEST1_3;
|
|
||||||
assign iccm_ext_in_pkt[3].RME = iccm_ext_in_pkt_RME_3;
|
|
||||||
assign iccm_ext_in_pkt[3].RM = iccm_ext_in_pkt_RM_3[3:0];
|
|
||||||
assign iccm_ext_in_pkt[3].LS = iccm_ext_in_pkt_LS_3;
|
|
||||||
assign iccm_ext_in_pkt[3].DS = iccm_ext_in_pkt_DS_3;
|
|
||||||
assign iccm_ext_in_pkt[3].SD = iccm_ext_in_pkt_SD_3;
|
|
||||||
assign iccm_ext_in_pkt[3].TEST_RNM = iccm_ext_in_pkt_TEST_RNM_3;
|
|
||||||
assign iccm_ext_in_pkt[3].BC1 = iccm_ext_in_pkt_BC1_3;
|
|
||||||
assign iccm_ext_in_pkt[3].BC2 = iccm_ext_in_pkt_BC2_3;
|
|
||||||
|
|
||||||
|
|
||||||
assign ic_tag_ext_in_pkt[0].TEST1 = ic_tag_ext_in_pkt_TEST1_0;
|
|
||||||
assign ic_tag_ext_in_pkt[0].RME = ic_tag_ext_in_pkt_RME_0;
|
|
||||||
assign ic_tag_ext_in_pkt[0].RM = ic_tag_ext_in_pkt_RM_0[3:0];
|
|
||||||
assign ic_tag_ext_in_pkt[0].LS = ic_tag_ext_in_pkt_LS_0;
|
|
||||||
assign ic_tag_ext_in_pkt[0].DS = ic_tag_ext_in_pkt_DS_0;
|
|
||||||
assign ic_tag_ext_in_pkt[0].SD = ic_tag_ext_in_pkt_SD_0;
|
|
||||||
assign ic_tag_ext_in_pkt[0].TEST_RNM = ic_tag_ext_in_pkt_TEST_RNM_0;
|
|
||||||
assign ic_tag_ext_in_pkt[0].BC1 = ic_tag_ext_in_pkt_BC1_0;
|
|
||||||
assign ic_tag_ext_in_pkt[0].BC2 = ic_tag_ext_in_pkt_BC2_0;
|
|
||||||
|
|
||||||
assign ic_tag_ext_in_pkt[1].TEST1 = ic_tag_ext_in_pkt_TEST1_1;
|
|
||||||
assign ic_tag_ext_in_pkt[1].RME = ic_tag_ext_in_pkt_RME_1;
|
|
||||||
assign ic_tag_ext_in_pkt[1].RM = ic_tag_ext_in_pkt_RM_1[3:0];
|
|
||||||
assign ic_tag_ext_in_pkt[1].LS = ic_tag_ext_in_pkt_LS_1;
|
|
||||||
assign ic_tag_ext_in_pkt[1].DS = ic_tag_ext_in_pkt_DS_1;
|
|
||||||
assign ic_tag_ext_in_pkt[1].SD = ic_tag_ext_in_pkt_SD_1;
|
|
||||||
assign ic_tag_ext_in_pkt[1].TEST_RNM = ic_tag_ext_in_pkt_TEST_RNM_1;
|
|
||||||
assign ic_tag_ext_in_pkt[1].BC1 = ic_tag_ext_in_pkt_BC1_1;
|
|
||||||
assign ic_tag_ext_in_pkt[1].BC2 = ic_tag_ext_in_pkt_BC2_1;
|
|
||||||
|
|
||||||
// PKT connection
|
|
||||||
assign ic_data_ext_in_pkt[0][0].TEST1 = ic_data_ext_in_pkt_0_TEST1_0;
|
|
||||||
assign ic_data_ext_in_pkt[0][0].RME = ic_data_ext_in_pkt_0_RME_0;
|
|
||||||
assign ic_data_ext_in_pkt[0][0].RM = ic_data_ext_in_pkt_0_RM_0[3:0];
|
|
||||||
assign ic_data_ext_in_pkt[0][0].LS = ic_data_ext_in_pkt_0_LS_0;
|
|
||||||
assign ic_data_ext_in_pkt[0][0].DS = ic_data_ext_in_pkt_0_DS_0;
|
|
||||||
assign ic_data_ext_in_pkt[0][0].SD = ic_data_ext_in_pkt_0_SD_0;
|
|
||||||
assign ic_data_ext_in_pkt[0][0].TEST_RNM = ic_data_ext_in_pkt_0_TEST_RNM_0;
|
|
||||||
assign ic_data_ext_in_pkt[0][0].BC1 = ic_data_ext_in_pkt_0_BC1_0;
|
|
||||||
assign ic_data_ext_in_pkt[0][0].BC2 = ic_data_ext_in_pkt_0_BC2_0;
|
|
||||||
|
|
||||||
assign ic_data_ext_in_pkt[0][1].TEST1 = ic_data_ext_in_pkt_1_TEST1_1;
|
|
||||||
assign ic_data_ext_in_pkt[0][1].RME = ic_data_ext_in_pkt_1_RME_1;
|
|
||||||
assign ic_data_ext_in_pkt[0][1].RM = ic_data_ext_in_pkt_1_RM_1[3:0];
|
|
||||||
assign ic_data_ext_in_pkt[0][1].LS = ic_data_ext_in_pkt_1_LS_1;
|
|
||||||
assign ic_data_ext_in_pkt[0][1].DS = ic_data_ext_in_pkt_1_DS_1;
|
|
||||||
assign ic_data_ext_in_pkt[0][1].SD = ic_data_ext_in_pkt_1_SD_1;
|
|
||||||
assign ic_data_ext_in_pkt[0][1].TEST_RNM = ic_data_ext_in_pkt_1_TEST_RNM_1;
|
|
||||||
assign ic_data_ext_in_pkt[0][1].BC1 = ic_data_ext_in_pkt_1_BC1_1;
|
|
||||||
assign ic_data_ext_in_pkt[0][1].BC2 = ic_data_ext_in_pkt_1_BC2_1;
|
|
||||||
|
|
||||||
assign ic_data_ext_in_pkt[1][0].TEST1 = ic_data_ext_in_pkt_1_TEST1_0;
|
|
||||||
assign ic_data_ext_in_pkt[1][0].RME = ic_data_ext_in_pkt_1_RME_0;
|
|
||||||
assign ic_data_ext_in_pkt[1][0].RM = ic_data_ext_in_pkt_1_RM_0[3:0];
|
|
||||||
assign ic_data_ext_in_pkt[1][0].LS = ic_data_ext_in_pkt_1_LS_0;
|
|
||||||
assign ic_data_ext_in_pkt[1][0].DS = ic_data_ext_in_pkt_1_DS_0;
|
|
||||||
assign ic_data_ext_in_pkt[1][0].SD = ic_data_ext_in_pkt_1_SD_0;
|
|
||||||
assign ic_data_ext_in_pkt[1][0].TEST_RNM = ic_data_ext_in_pkt_1_TEST_RNM_0;
|
|
||||||
assign ic_data_ext_in_pkt[1][0].BC1 = ic_data_ext_in_pkt_1_BC1_0;
|
|
||||||
assign ic_data_ext_in_pkt[1][0].BC2 = ic_data_ext_in_pkt_1_BC2_0;
|
|
||||||
|
|
||||||
assign ic_data_ext_in_pkt[1][1].TEST1 = ic_data_ext_in_pkt_1_TEST1_1;
|
|
||||||
assign ic_data_ext_in_pkt[1][1].RME = ic_data_ext_in_pkt_1_RME_1;
|
|
||||||
assign ic_data_ext_in_pkt[1][1].RM = ic_data_ext_in_pkt_1_RM_1[3:0];
|
|
||||||
assign ic_data_ext_in_pkt[1][1].LS = ic_data_ext_in_pkt_1_LS_1;
|
|
||||||
assign ic_data_ext_in_pkt[1][1].DS = ic_data_ext_in_pkt_1_DS_1;
|
|
||||||
assign ic_data_ext_in_pkt[1][1].SD = ic_data_ext_in_pkt_1_SD_1;
|
|
||||||
assign ic_data_ext_in_pkt[1][1].TEST_RNM = ic_data_ext_in_pkt_1_TEST_RNM_1;
|
|
||||||
assign ic_data_ext_in_pkt[1][1].BC1 = ic_data_ext_in_pkt_1_BC1_1;
|
|
||||||
assign ic_data_ext_in_pkt[1][1].BC2 = ic_data_ext_in_pkt_1_BC2_1;
|
|
||||||
|
|
||||||
rvoclkhdr active_cg ( .en(1'b1), .l1clk(active_clk), .* );
|
|
||||||
|
|
||||||
// DCCM Instantiation
|
|
||||||
if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
|
|
||||||
lsu_dccm_mem #(
|
|
||||||
.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
|
|
||||||
.DCCM_BITS(DCCM_BITS),
|
|
||||||
.DCCM_NUM_BANKS(DCCM_NUM_BANKS),
|
|
||||||
.DCCM_BANK_BITS(DCCM_BANK_BITS),
|
|
||||||
.DCCM_SIZE(DCCM_SIZE),
|
|
||||||
.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH),
|
|
||||||
.DCCM_WIDTH_BITS(DCCM_WIDTH_BITS)) dccm (
|
|
||||||
.clk_override(dccm_clk_override),
|
|
||||||
.*
|
|
||||||
);
|
|
||||||
end else begin: Gen_dccm_disable
|
|
||||||
assign dccm_rd_data_lo = '0;
|
|
||||||
assign dccm_rd_data_hi = '0;
|
|
||||||
end
|
|
||||||
|
|
||||||
if ( ICACHE_ENABLE ) begin: icache
|
|
||||||
ifu_ic_mem #(
|
|
||||||
.ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
|
|
||||||
.ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
|
|
||||||
.ICACHE_BANK_BITS(ICACHE_BANK_BITS),
|
|
||||||
.ICACHE_BEAT_ADDR_HI(ICACHE_BEAT_ADDR_HI),
|
|
||||||
.ICACHE_BANKS_WAY(ICACHE_BANKS_WAY),
|
|
||||||
.ICACHE_INDEX_HI(ICACHE_INDEX_HI),
|
|
||||||
.ICACHE_BANK_HI(ICACHE_BANK_HI),
|
|
||||||
.ICACHE_BANK_LO(ICACHE_BANK_LO),
|
|
||||||
.ICACHE_TAG_LO(ICACHE_TAG_LO),
|
|
||||||
.ICACHE_DATA_INDEX_LO(ICACHE_DATA_INDEX_LO),
|
|
||||||
.ICACHE_ECC(ICACHE_ECC),
|
|
||||||
.ICACHE_TAG_DEPTH(ICACHE_TAG_DEPTH),
|
|
||||||
.ICACHE_WAYPACK(ICACHE_WAYPACK),
|
|
||||||
.ICACHE_TAG_INDEX_LO(ICACHE_TAG_INDEX_LO),
|
|
||||||
.ICACHE_DATA_DEPTH(ICACHE_DATA_DEPTH),
|
|
||||||
.ICACHE_TAG_NUM_BYPASS(ICACHE_TAG_NUM_BYPASS),
|
|
||||||
.ICACHE_TAG_NUM_BYPASS_WIDTH(ICACHE_TAG_NUM_BYPASS_WIDTH),
|
|
||||||
.ICACHE_TAG_BYPASS_ENABLE(ICACHE_TAG_BYPASS_ENABLE),
|
|
||||||
.ICACHE_NUM_BYPASS_WIDTH(ICACHE_NUM_BYPASS_WIDTH),
|
|
||||||
.ICACHE_BYPASS_ENABLE(ICACHE_BYPASS_ENABLE),
|
|
||||||
.ICACHE_NUM_BYPASS(ICACHE_NUM_BYPASS),
|
|
||||||
.ICACHE_LN_SZ(ICACHE_LN_SZ)) icm (
|
|
||||||
.clk_override(icm_clk_override),
|
|
||||||
.*
|
|
||||||
);
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
|
|
||||||
assign ic_tag_perr = '0 ;
|
|
||||||
assign ic_rd_data = '0 ;
|
|
||||||
assign ic_tag_debug_rd_data = '0 ;
|
|
||||||
end // else: !if( ICACHE_ENABLE )
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
if (ICCM_ENABLE) begin : iccm
|
|
||||||
ifu_iccm_mem #(
|
|
||||||
.ICCM_BITS(ICCM_BITS),
|
|
||||||
.ICCM_BANK_INDEX_LO(ICCM_BANK_INDEX_LO),
|
|
||||||
.ICCM_INDEX_BITS(ICCM_INDEX_BITS),
|
|
||||||
.ICCM_BANK_HI(ICCM_BANK_HI),
|
|
||||||
.ICCM_NUM_BANKS(ICCM_NUM_BANKS),
|
|
||||||
.ICCM_BANK_BITS(ICCM_BANK_BITS)) iccm (.*,
|
|
||||||
.clk_override(icm_clk_override),
|
|
||||||
.iccm_rw_addr(iccm_rw_addr[ICCM_BITS-1:1]),
|
|
||||||
.iccm_rd_data(iccm_rd_data[63:0])
|
|
||||||
);
|
|
||||||
end
|
|
||||||
else begin
|
|
||||||
assign iccm_rd_data = '0 ;
|
|
||||||
assign iccm_rd_data_ecc = '0 ;
|
|
||||||
end
|
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
159180
design/quasar_wrapper.fir
159180
design/quasar_wrapper.fir
File diff suppressed because one or more lines are too long
|
@ -1,246 +0,0 @@
|
||||||
// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
|
|
||||||
// This is an automatically generated file by laraib.khan on Tue Mar 2 10:41:03 PKT 2021
|
|
||||||
//
|
|
||||||
// cmd: quasar -target=default
|
|
||||||
//
|
|
||||||
`define RV_ROOT "/home/users/laraib.khan/Videos/Quasar"
|
|
||||||
`define RV_BTB_ADDR_HI 9
|
|
||||||
`define RV_BTB_TOFFSET_SIZE 12
|
|
||||||
`define RV_BTB_INDEX3_HI 25
|
|
||||||
`define RV_BTB_FOLD2_INDEX_HASH 0
|
|
||||||
`define RV_BTB_INDEX2_HI 17
|
|
||||||
`define RV_BTB_ARRAY_DEPTH 256
|
|
||||||
`define RV_BTB_INDEX1_HI 9
|
|
||||||
`define RV_BTB_INDEX1_LO 2
|
|
||||||
`define RV_BTB_INDEX2_LO 10
|
|
||||||
`define RV_BTB_BTAG_SIZE 5
|
|
||||||
`define RV_BTB_ADDR_LO 2
|
|
||||||
`define RV_BTB_BTAG_FOLD 0
|
|
||||||
`define RV_BTB_INDEX3_LO 18
|
|
||||||
`define RV_BTB_SIZE 512
|
|
||||||
`define RV_BTB_ENABLE 1
|
|
||||||
`define RV_EXT_ADDRWIDTH 32
|
|
||||||
`define RV_BUILD_AXI4 1
|
|
||||||
`define RV_STERR_ROLLBACK 0
|
|
||||||
`define CLOCK_PERIOD 100
|
|
||||||
`define RV_ASSERT_ON
|
|
||||||
`define CPU_TOP `RV_TOP.swerv
|
|
||||||
`define RV_BUILD_AXI_NATIVE 1
|
|
||||||
`define TOP tb_top
|
|
||||||
`define RV_LDERR_ROLLBACK 1
|
|
||||||
`define RV_EXT_DATAWIDTH 64
|
|
||||||
`define RV_TOP `TOP.rvtop
|
|
||||||
`define SDVT_AHB 0
|
|
||||||
`define RV_ICACHE_BYPASS_ENABLE 1
|
|
||||||
`define RV_ICACHE_TAG_BYPASS_ENABLE 1
|
|
||||||
`define RV_ICACHE_TAG_NUM_BYPASS_WIDTH 2
|
|
||||||
`define RV_ICACHE_NUM_BEATS 8
|
|
||||||
`define RV_ICACHE_DATA_INDEX_LO 4
|
|
||||||
`define RV_ICACHE_BANK_BITS 1
|
|
||||||
`define RV_ICACHE_FDATA_WIDTH 71
|
|
||||||
`define RV_ICACHE_TAG_CELL ram_128x25
|
|
||||||
`define RV_ICACHE_TAG_INDEX_LO 6
|
|
||||||
`define RV_ICACHE_2BANKS 1
|
|
||||||
`define RV_ICACHE_BEAT_ADDR_HI 5
|
|
||||||
`define RV_ICACHE_SCND_LAST 6
|
|
||||||
`define RV_ICACHE_NUM_BYPASS_WIDTH 2
|
|
||||||
`define RV_ICACHE_DATA_DEPTH 512
|
|
||||||
`define RV_ICACHE_TAG_LO 13
|
|
||||||
`define RV_ICACHE_DATA_WIDTH 64
|
|
||||||
`define RV_ICACHE_ECC 1
|
|
||||||
`define RV_ICACHE_STATUS_BITS 1
|
|
||||||
`define RV_ICACHE_TAG_DEPTH 128
|
|
||||||
`define RV_ICACHE_NUM_LINES_BANK 64
|
|
||||||
`define RV_ICACHE_WAYPACK 1
|
|
||||||
`define RV_ICACHE_BANK_WIDTH 8
|
|
||||||
`define RV_ICACHE_ENABLE 1
|
|
||||||
`define RV_ICACHE_BEAT_BITS 3
|
|
||||||
`define RV_ICACHE_NUM_LINES 256
|
|
||||||
`define RV_ICACHE_BANKS_WAY 2
|
|
||||||
`define RV_ICACHE_INDEX_HI 12
|
|
||||||
`define RV_ICACHE_NUM_WAYS 2
|
|
||||||
`define RV_ICACHE_BANK_HI 3
|
|
||||||
`define RV_ICACHE_LN_SZ 64
|
|
||||||
`define RV_ICACHE_NUM_LINES_WAY 128
|
|
||||||
`define RV_ICACHE_BANK_LO 3
|
|
||||||
`define RV_ICACHE_NUM_BYPASS 2
|
|
||||||
`define RV_ICACHE_TAG_NUM_BYPASS 2
|
|
||||||
`define RV_ICACHE_SIZE 16
|
|
||||||
`define RV_ICACHE_DATA_CELL ram_512x71
|
|
||||||
`define RV_RET_STACK_SIZE 8
|
|
||||||
`define REGWIDTH 32
|
|
||||||
`define RV_XLEN 32
|
|
||||||
`define RV_INST_ACCESS_ADDR0 'h00000000
|
|
||||||
`define RV_DATA_ACCESS_MASK3 'hffffffff
|
|
||||||
`define RV_DATA_ACCESS_ENABLE2 1'h0
|
|
||||||
`define RV_DATA_ACCESS_ENABLE0 1'h0
|
|
||||||
`define RV_DATA_ACCESS_ENABLE3 1'h0
|
|
||||||
`define RV_DATA_ACCESS_ADDR1 'h00000000
|
|
||||||
`define RV_INST_ACCESS_MASK0 'hffffffff
|
|
||||||
`define RV_INST_ACCESS_ADDR2 'h00000000
|
|
||||||
`define RV_DATA_ACCESS_ADDR5 'h00000000
|
|
||||||
`define RV_DATA_ACCESS_ENABLE7 1'h0
|
|
||||||
`define RV_INST_ACCESS_MASK6 'hffffffff
|
|
||||||
`define RV_INST_ACCESS_ADDR3 'h00000000
|
|
||||||
`define RV_DATA_ACCESS_MASK7 'hffffffff
|
|
||||||
`define RV_INST_ACCESS_MASK3 'hffffffff
|
|
||||||
`define RV_INST_ACCESS_MASK7 'hffffffff
|
|
||||||
`define RV_INST_ACCESS_MASK1 'hffffffff
|
|
||||||
`define RV_INST_ACCESS_ENABLE0 1'h0
|
|
||||||
`define RV_DATA_ACCESS_ADDR6 'h00000000
|
|
||||||
`define RV_INST_ACCESS_MASK2 'hffffffff
|
|
||||||
`define RV_DATA_ACCESS_MASK2 'hffffffff
|
|
||||||
`define RV_DATA_ACCESS_MASK0 'hffffffff
|
|
||||||
`define RV_INST_ACCESS_ENABLE1 1'h0
|
|
||||||
`define RV_DATA_ACCESS_ADDR2 'h00000000
|
|
||||||
`define RV_INST_ACCESS_ADDR5 'h00000000
|
|
||||||
`define RV_DATA_ACCESS_ENABLE4 1'h0
|
|
||||||
`define RV_DATA_ACCESS_MASK6 'hffffffff
|
|
||||||
`define RV_DATA_ACCESS_ADDR0 'h00000000
|
|
||||||
`define RV_DATA_ACCESS_ENABLE5 1'h0
|
|
||||||
`define RV_DATA_ACCESS_ADDR7 'h00000000
|
|
||||||
`define RV_INST_ACCESS_ENABLE5 1'h0
|
|
||||||
`define RV_INST_ACCESS_MASK5 'hffffffff
|
|
||||||
`define RV_INST_ACCESS_ENABLE2 1'h0
|
|
||||||
`define RV_DATA_ACCESS_ADDR3 'h00000000
|
|
||||||
`define RV_DATA_ACCESS_MASK5 'hffffffff
|
|
||||||
`define RV_INST_ACCESS_ADDR6 'h00000000
|
|
||||||
`define RV_INST_ACCESS_ADDR1 'h00000000
|
|
||||||
`define RV_DATA_ACCESS_ENABLE6 1'h0
|
|
||||||
`define RV_DATA_ACCESS_MASK1 'hffffffff
|
|
||||||
`define RV_INST_ACCESS_ENABLE7 1'h0
|
|
||||||
`define RV_INST_ACCESS_ENABLE6 1'h0
|
|
||||||
`define RV_INST_ACCESS_ENABLE3 1'h0
|
|
||||||
`define RV_DATA_ACCESS_MASK4 'hffffffff
|
|
||||||
`define RV_DATA_ACCESS_ADDR4 'h00000000
|
|
||||||
`define RV_DATA_ACCESS_ENABLE1 1'h0
|
|
||||||
`define RV_INST_ACCESS_ADDR7 'h00000000
|
|
||||||
`define RV_INST_ACCESS_ADDR4 'h00000000
|
|
||||||
`define RV_INST_ACCESS_ENABLE4 1'h0
|
|
||||||
`define RV_INST_ACCESS_MASK4 'hffffffff
|
|
||||||
`define RV_BHT_GHR_RANGE 7:0
|
|
||||||
`define RV_BHT_GHR_HASH_1
|
|
||||||
`define RV_BHT_SIZE 512
|
|
||||||
`define RV_BHT_ADDR_HI 9
|
|
||||||
`define RV_BHT_ARRAY_DEPTH 256
|
|
||||||
`define RV_BHT_HASH_STRING {hashin[8+1:2]^ghr[8-1:0]}// cf2
|
|
||||||
`define RV_BHT_ADDR_LO 2
|
|
||||||
`define RV_BHT_GHR_SIZE 8
|
|
||||||
`define RV_SB_BUS_ID 1
|
|
||||||
`define RV_DMA_BUS_PRTY 2
|
|
||||||
`define RV_BUS_PRTY_DEFAULT 2'h3
|
|
||||||
`define RV_LSU_BUS_ID 1
|
|
||||||
`define RV_IFU_BUS_PRTY 2
|
|
||||||
`define RV_IFU_BUS_ID 1
|
|
||||||
`define RV_SB_BUS_PRTY 2
|
|
||||||
`define RV_LSU_BUS_TAG 3
|
|
||||||
`define RV_DMA_BUS_TAG 1
|
|
||||||
`define RV_DMA_BUS_ID 1
|
|
||||||
`define RV_IFU_BUS_TAG 3
|
|
||||||
`define RV_LSU_BUS_PRTY 2
|
|
||||||
`define RV_SB_BUS_TAG 1
|
|
||||||
`define RV_RESET_VEC 'h80000000
|
|
||||||
`define RV_UNUSED_REGION3 'h50000000
|
|
||||||
`define RV_UNUSED_REGION1 'h70000000
|
|
||||||
`define RV_UNUSED_REGION5 'h30000000
|
|
||||||
`define RV_UNUSED_REGION0 'h90000000
|
|
||||||
`define RV_EXTERNAL_DATA_1 'hb0000000
|
|
||||||
`define RV_UNUSED_REGION2 'h60000000
|
|
||||||
`define RV_UNUSED_REGION8 'h00000000
|
|
||||||
`define RV_UNUSED_REGION6 'h20000000
|
|
||||||
`define RV_SERIALIO 'hd0580000
|
|
||||||
`define RV_UNUSED_REGION7 'h10000000
|
|
||||||
`define RV_DEBUG_SB_MEM 'ha0580000
|
|
||||||
`define RV_UNUSED_REGION4 'h40000000
|
|
||||||
`define RV_EXTERNAL_DATA 'hc0580000
|
|
||||||
`define RV_PIC_MPICCFG_COUNT 1
|
|
||||||
`define RV_PIC_MPICCFG_OFFSET 'h3000
|
|
||||||
`define RV_PIC_BITS 15
|
|
||||||
`define RV_PIC_MEIP_OFFSET 'h1000
|
|
||||||
`define RV_PIC_MEIGWCLR_OFFSET 'h5000
|
|
||||||
`define RV_PIC_MEIPT_OFFSET 'h3004
|
|
||||||
`define RV_PIC_MEIPT_MASK 'h0
|
|
||||||
`define RV_PIC_MEIGWCTRL_MASK 'h3
|
|
||||||
`define RV_PIC_TOTAL_INT_PLUS1 32
|
|
||||||
`define RV_PIC_MEIPL_COUNT 31
|
|
||||||
`define RV_PIC_MEIGWCTRL_COUNT 31
|
|
||||||
`define RV_PIC_MPICCFG_MASK 'h1
|
|
||||||
`define RV_PIC_MEIE_MASK 'h1
|
|
||||||
`define RV_PIC_MEIGWCTRL_OFFSET 'h4000
|
|
||||||
`define RV_PIC_INT_WORDS 1
|
|
||||||
`define RV_PIC_MEIPL_OFFSET 'h0000
|
|
||||||
`define RV_PIC_MEIGWCLR_COUNT 31
|
|
||||||
`define RV_PIC_MEIGWCLR_MASK 'h0
|
|
||||||
`define RV_PIC_OFFSET 10'hc0000
|
|
||||||
`define RV_PIC_MEIE_OFFSET 'h2000
|
|
||||||
`define RV_PIC_REGION 4'hf
|
|
||||||
`define RV_PIC_TOTAL_INT 31
|
|
||||||
`define RV_PIC_MEIE_COUNT 31
|
|
||||||
`define RV_PIC_MEIP_MASK 'h0
|
|
||||||
`define RV_PIC_MEIPT_COUNT 31
|
|
||||||
`define RV_PIC_BASE_ADDR 32'hf00c0000
|
|
||||||
`define RV_PIC_SIZE 32
|
|
||||||
`define RV_PIC_MEIPL_MASK 'hf
|
|
||||||
`define RV_PIC_MEIP_COUNT 1
|
|
||||||
`define RV_NMI_VEC 'h11110000
|
|
||||||
`define RV_DCCM_ROWS 4096
|
|
||||||
`define RV_DCCM_RESERVED 'h1400
|
|
||||||
`define RV_DCCM_BANK_BITS 2
|
|
||||||
`define RV_DCCM_SIZE 64
|
|
||||||
`define RV_DCCM_WIDTH_BITS 2
|
|
||||||
`define RV_DCCM_ENABLE 1
|
|
||||||
`define RV_DCCM_BYTE_WIDTH 4
|
|
||||||
`define RV_DCCM_ECC_WIDTH 7
|
|
||||||
`define RV_DCCM_DATA_WIDTH 32
|
|
||||||
`define RV_LSU_SB_BITS 16
|
|
||||||
`define RV_DCCM_REGION 4'hf
|
|
||||||
`define RV_DCCM_OFFSET 28'h40000
|
|
||||||
`define RV_DCCM_SADR 32'hf0040000
|
|
||||||
`define RV_DCCM_EADR 32'hf004ffff
|
|
||||||
`define RV_DCCM_NUM_BANKS_4
|
|
||||||
`define RV_DCCM_SIZE_64
|
|
||||||
`define RV_DCCM_DATA_CELL ram_4096x39
|
|
||||||
`define RV_DCCM_FDATA_WIDTH 39
|
|
||||||
`define RV_DCCM_NUM_BANKS 4
|
|
||||||
`define RV_DCCM_INDEX_BITS 12
|
|
||||||
`define RV_DCCM_BITS 16
|
|
||||||
`define RV_ICCM_DATA_CELL ram_4096x39
|
|
||||||
`define RV_ICCM_OFFSET 10'he000000
|
|
||||||
`define RV_ICCM_BITS 16
|
|
||||||
`define RV_ICCM_SADR 32'hee000000
|
|
||||||
`define RV_ICCM_EADR 32'hee00ffff
|
|
||||||
`define RV_ICCM_NUM_BANKS_4
|
|
||||||
`define RV_ICCM_ENABLE 1
|
|
||||||
`define RV_ICCM_RESERVED 'h1000
|
|
||||||
`define RV_ICCM_SIZE 64
|
|
||||||
`define RV_ICCM_BANK_BITS 2
|
|
||||||
`define RV_ICCM_SIZE_64
|
|
||||||
`define RV_ICCM_BANK_INDEX_LO 4
|
|
||||||
`define RV_ICCM_NUM_BANKS 4
|
|
||||||
`define RV_ICCM_INDEX_BITS 12
|
|
||||||
`define RV_ICCM_REGION 4'he
|
|
||||||
`define RV_ICCM_ROWS 4096
|
|
||||||
`define RV_ICCM_BANK_HI 3
|
|
||||||
`define RV_BITMANIP_ZBF 0
|
|
||||||
`define RV_BITMANIP_ZBA 0
|
|
||||||
`define RV_LSU_STBUF_DEPTH 4
|
|
||||||
`define RV_LSU_NUM_NBLOAD 4
|
|
||||||
`define RV_BITMANIP_ZBR 0
|
|
||||||
`define RV_BITMANIP_ZBS 1
|
|
||||||
`define RV_BITMANIP_ZBE 0
|
|
||||||
`define RV_BITMANIP_ZBP 0
|
|
||||||
`define RV_DMA_BUF_DEPTH 5
|
|
||||||
`define RV_DIV_BIT 4
|
|
||||||
`define RV_ICCM_ICACHE 1
|
|
||||||
`define RV_TIMER_LEGAL_EN 1
|
|
||||||
`define RV_LSU2DMA 0
|
|
||||||
`define RV_FAST_INTERRUPT_REDIRECT 1
|
|
||||||
`define RV_LSU_NUM_NBLOAD_WIDTH 2
|
|
||||||
`define RV_RV_FPGA_OPTIMIZE 1
|
|
||||||
`define RV_BITMANIP_ZBC 0
|
|
||||||
`define RV_BITMANIP_ZBB 1
|
|
||||||
`define RV_DIV_NEW 1
|
|
||||||
`define RV_TARGET default
|
|
||||||
`define TEC_RV_ICG clockhdr
|
|
||||||
`define RV_CONFIG_KEY 32'hdeadbeef
|
|
||||||
`define RV_NUMIREGS 32
|
|
|
@ -1,172 +0,0 @@
|
||||||
// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
|
|
||||||
// This is an automatically generated file by laraib.khan on Tue Mar 2 10:41:03 PKT 2021
|
|
||||||
//
|
|
||||||
// cmd: quasar -target=default
|
|
||||||
//
|
|
||||||
#define RV_EXT_ADDRWIDTH 32
|
|
||||||
#define RV_BUILD_AXI4 1
|
|
||||||
#define RV_STERR_ROLLBACK 0
|
|
||||||
#define CLOCK_PERIOD 100
|
|
||||||
#define RV_ASSERT_ON
|
|
||||||
#define CPU_TOP `RV_TOP.swerv
|
|
||||||
#define RV_BUILD_AXI_NATIVE 1
|
|
||||||
#define TOP tb_top
|
|
||||||
#define RV_LDERR_ROLLBACK 1
|
|
||||||
#define RV_EXT_DATAWIDTH 64
|
|
||||||
#define RV_TOP `TOP.rvtop
|
|
||||||
#define SDVT_AHB 0
|
|
||||||
#define RV_XLEN 32
|
|
||||||
#define RV_INST_ACCESS_ADDR0 0x00000000
|
|
||||||
#define RV_DATA_ACCESS_MASK3 0xffffffff
|
|
||||||
#define RV_DATA_ACCESS_ENABLE2 0x0
|
|
||||||
#define RV_DATA_ACCESS_ENABLE0 0x0
|
|
||||||
#define RV_DATA_ACCESS_ENABLE3 0x0
|
|
||||||
#define RV_DATA_ACCESS_ADDR1 0x00000000
|
|
||||||
#define RV_INST_ACCESS_MASK0 0xffffffff
|
|
||||||
#define RV_INST_ACCESS_ADDR2 0x00000000
|
|
||||||
#define RV_DATA_ACCESS_ADDR5 0x00000000
|
|
||||||
#define RV_DATA_ACCESS_ENABLE7 0x0
|
|
||||||
#define RV_INST_ACCESS_MASK6 0xffffffff
|
|
||||||
#define RV_INST_ACCESS_ADDR3 0x00000000
|
|
||||||
#define RV_DATA_ACCESS_MASK7 0xffffffff
|
|
||||||
#define RV_INST_ACCESS_MASK3 0xffffffff
|
|
||||||
#define RV_INST_ACCESS_MASK7 0xffffffff
|
|
||||||
#define RV_INST_ACCESS_MASK1 0xffffffff
|
|
||||||
#define RV_INST_ACCESS_ENABLE0 0x0
|
|
||||||
#define RV_DATA_ACCESS_ADDR6 0x00000000
|
|
||||||
#define RV_INST_ACCESS_MASK2 0xffffffff
|
|
||||||
#define RV_DATA_ACCESS_MASK2 0xffffffff
|
|
||||||
#define RV_DATA_ACCESS_MASK0 0xffffffff
|
|
||||||
#define RV_INST_ACCESS_ENABLE1 0x0
|
|
||||||
#define RV_DATA_ACCESS_ADDR2 0x00000000
|
|
||||||
#define RV_INST_ACCESS_ADDR5 0x00000000
|
|
||||||
#define RV_DATA_ACCESS_ENABLE4 0x0
|
|
||||||
#define RV_DATA_ACCESS_MASK6 0xffffffff
|
|
||||||
#define RV_DATA_ACCESS_ADDR0 0x00000000
|
|
||||||
#define RV_DATA_ACCESS_ENABLE5 0x0
|
|
||||||
#define RV_DATA_ACCESS_ADDR7 0x00000000
|
|
||||||
#define RV_INST_ACCESS_ENABLE5 0x0
|
|
||||||
#define RV_INST_ACCESS_MASK5 0xffffffff
|
|
||||||
#define RV_INST_ACCESS_ENABLE2 0x0
|
|
||||||
#define RV_DATA_ACCESS_ADDR3 0x00000000
|
|
||||||
#define RV_DATA_ACCESS_MASK5 0xffffffff
|
|
||||||
#define RV_INST_ACCESS_ADDR6 0x00000000
|
|
||||||
#define RV_INST_ACCESS_ADDR1 0x00000000
|
|
||||||
#define RV_DATA_ACCESS_ENABLE6 0x0
|
|
||||||
#define RV_DATA_ACCESS_MASK1 0xffffffff
|
|
||||||
#define RV_INST_ACCESS_ENABLE7 0x0
|
|
||||||
#define RV_INST_ACCESS_ENABLE6 0x0
|
|
||||||
#define RV_INST_ACCESS_ENABLE3 0x0
|
|
||||||
#define RV_DATA_ACCESS_MASK4 0xffffffff
|
|
||||||
#define RV_DATA_ACCESS_ADDR4 0x00000000
|
|
||||||
#define RV_DATA_ACCESS_ENABLE1 0x0
|
|
||||||
#define RV_INST_ACCESS_ADDR7 0x00000000
|
|
||||||
#define RV_INST_ACCESS_ADDR4 0x00000000
|
|
||||||
#define RV_INST_ACCESS_ENABLE4 0x0
|
|
||||||
#define RV_INST_ACCESS_MASK4 0xffffffff
|
|
||||||
#ifndef RV_RESET_VEC
|
|
||||||
#define RV_RESET_VEC 0x80000000
|
|
||||||
#endif
|
|
||||||
#define RV_UNUSED_REGION3 0x50000000
|
|
||||||
#define RV_UNUSED_REGION1 0x70000000
|
|
||||||
#define RV_UNUSED_REGION5 0x30000000
|
|
||||||
#define RV_UNUSED_REGION0 0x90000000
|
|
||||||
#define RV_EXTERNAL_DATA_1 0xb0000000
|
|
||||||
#define RV_UNUSED_REGION2 0x60000000
|
|
||||||
#define RV_UNUSED_REGION8 0x00000000
|
|
||||||
#define RV_UNUSED_REGION6 0x20000000
|
|
||||||
#define RV_SERIALIO 0xd0580000
|
|
||||||
#define RV_UNUSED_REGION7 0x10000000
|
|
||||||
#define RV_DEBUG_SB_MEM 0xa0580000
|
|
||||||
#define RV_UNUSED_REGION4 0x40000000
|
|
||||||
#define RV_EXTERNAL_DATA 0xc0580000
|
|
||||||
#define RV_PIC_MPICCFG_COUNT 1
|
|
||||||
#define RV_PIC_MPICCFG_OFFSET 0x3000
|
|
||||||
#define RV_PIC_BITS 15
|
|
||||||
#define RV_PIC_MEIP_OFFSET 0x1000
|
|
||||||
#define RV_PIC_MEIGWCLR_OFFSET 0x5000
|
|
||||||
#define RV_PIC_MEIPT_OFFSET 0x3004
|
|
||||||
#define RV_PIC_MEIPT_MASK 0x0
|
|
||||||
#define RV_PIC_MEIGWCTRL_MASK 0x3
|
|
||||||
#define RV_PIC_TOTAL_INT_PLUS1 32
|
|
||||||
#define RV_PIC_MEIPL_COUNT 31
|
|
||||||
#define RV_PIC_MEIGWCTRL_COUNT 31
|
|
||||||
#define RV_PIC_MPICCFG_MASK 0x1
|
|
||||||
#define RV_PIC_MEIE_MASK 0x1
|
|
||||||
#define RV_PIC_MEIGWCTRL_OFFSET 0x4000
|
|
||||||
#define RV_PIC_INT_WORDS 1
|
|
||||||
#define RV_PIC_MEIPL_OFFSET 0x0000
|
|
||||||
#define RV_PIC_MEIGWCLR_COUNT 31
|
|
||||||
#define RV_PIC_MEIGWCLR_MASK 0x0
|
|
||||||
#define RV_PIC_OFFSET 0xc0000
|
|
||||||
#define RV_PIC_MEIE_OFFSET 0x2000
|
|
||||||
#define RV_PIC_REGION 0xf
|
|
||||||
#define RV_PIC_TOTAL_INT 31
|
|
||||||
#define RV_PIC_MEIE_COUNT 31
|
|
||||||
#define RV_PIC_MEIP_MASK 0x0
|
|
||||||
#define RV_PIC_MEIPT_COUNT 31
|
|
||||||
#define RV_PIC_BASE_ADDR 0xf00c0000
|
|
||||||
#define RV_PIC_SIZE 32
|
|
||||||
#define RV_PIC_MEIPL_MASK 0xf
|
|
||||||
#define RV_PIC_MEIP_COUNT 1
|
|
||||||
#ifndef RV_NMI_VEC
|
|
||||||
#define RV_NMI_VEC 0x11110000
|
|
||||||
#endif
|
|
||||||
#define RV_DCCM_ROWS 4096
|
|
||||||
#define RV_DCCM_RESERVED 0x1400
|
|
||||||
#define RV_DCCM_BANK_BITS 2
|
|
||||||
#define RV_DCCM_SIZE 64
|
|
||||||
#define RV_DCCM_WIDTH_BITS 2
|
|
||||||
#define RV_DCCM_ENABLE 1
|
|
||||||
#define RV_DCCM_BYTE_WIDTH 4
|
|
||||||
#define RV_DCCM_ECC_WIDTH 7
|
|
||||||
#define RV_DCCM_DATA_WIDTH 32
|
|
||||||
#define RV_LSU_SB_BITS 16
|
|
||||||
#define RV_DCCM_REGION 0xf
|
|
||||||
#define RV_DCCM_OFFSET 0x40000
|
|
||||||
#define RV_DCCM_SADR 0xf0040000
|
|
||||||
#define RV_DCCM_EADR 0xf004ffff
|
|
||||||
#define RV_DCCM_NUM_BANKS_4
|
|
||||||
#define RV_DCCM_SIZE_64
|
|
||||||
#define RV_DCCM_DATA_CELL ram_4096x39
|
|
||||||
#define RV_DCCM_FDATA_WIDTH 39
|
|
||||||
#define RV_DCCM_NUM_BANKS 4
|
|
||||||
#define RV_DCCM_INDEX_BITS 12
|
|
||||||
#define RV_DCCM_BITS 16
|
|
||||||
#define RV_ICCM_DATA_CELL ram_4096x39
|
|
||||||
#define RV_ICCM_OFFSET 0xe000000
|
|
||||||
#define RV_ICCM_BITS 16
|
|
||||||
#define RV_ICCM_SADR 0xee000000
|
|
||||||
#define RV_ICCM_EADR 0xee00ffff
|
|
||||||
#define RV_ICCM_NUM_BANKS_4
|
|
||||||
#define RV_ICCM_ENABLE 1
|
|
||||||
#define RV_ICCM_RESERVED 0x1000
|
|
||||||
#define RV_ICCM_SIZE 64
|
|
||||||
#define RV_ICCM_BANK_BITS 2
|
|
||||||
#define RV_ICCM_SIZE_64
|
|
||||||
#define RV_ICCM_BANK_INDEX_LO 4
|
|
||||||
#define RV_ICCM_NUM_BANKS 4
|
|
||||||
#define RV_ICCM_INDEX_BITS 12
|
|
||||||
#define RV_ICCM_REGION 0xe
|
|
||||||
#define RV_ICCM_ROWS 4096
|
|
||||||
#define RV_ICCM_BANK_HI 3
|
|
||||||
#define RV_BITMANIP_ZBF 0
|
|
||||||
#define RV_BITMANIP_ZBA 0
|
|
||||||
#define RV_LSU_STBUF_DEPTH 4
|
|
||||||
#define RV_LSU_NUM_NBLOAD 4
|
|
||||||
#define RV_BITMANIP_ZBR 0
|
|
||||||
#define RV_BITMANIP_ZBS 1
|
|
||||||
#define RV_BITMANIP_ZBE 0
|
|
||||||
#define RV_BITMANIP_ZBP 0
|
|
||||||
#define RV_DMA_BUF_DEPTH 5
|
|
||||||
#define RV_DIV_BIT 4
|
|
||||||
#define RV_ICCM_ICACHE 1
|
|
||||||
#define RV_TIMER_LEGAL_EN 1
|
|
||||||
#define RV_LSU2DMA 0
|
|
||||||
#define RV_FAST_INTERRUPT_REDIRECT 1
|
|
||||||
#define RV_LSU_NUM_NBLOAD_WIDTH 2
|
|
||||||
#define RV_RV_FPGA_OPTIMIZE 1
|
|
||||||
#define RV_BITMANIP_ZBC 0
|
|
||||||
#define RV_BITMANIP_ZBB 1
|
|
||||||
#define RV_DIV_NEW 1
|
|
||||||
#define RV_TARGET default
|
|
|
@ -1,26 +0,0 @@
|
||||||
/*
|
|
||||||
NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
|
|
||||||
This is an automatically generated file by laraib.khan on Tue Mar 2 10:41:03 PKT 2021
|
|
||||||
|
|
||||||
cmd: quasar -target=default
|
|
||||||
|
|
||||||
*/
|
|
||||||
OUTPUT_ARCH( "riscv" )
|
|
||||||
ENTRY(_start)
|
|
||||||
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
. = 0x80000000;
|
|
||||||
.text.init . : { *(.text.init) }
|
|
||||||
|
|
||||||
.text . : { *(.text) }
|
|
||||||
_end = .;
|
|
||||||
. = 0xd0580000;
|
|
||||||
.data.io . : { *(.data.io) }
|
|
||||||
. = 0xf0040000 ;
|
|
||||||
.data : ALIGN(0x800) { *(.*data) *(.rodata*) STACK = ALIGN(16) + 0x8000; }
|
|
||||||
.bss : { *(.bss) }
|
|
||||||
|
|
||||||
. = 0xfffffff8; .data.ctl : { LONG(0xf0040000); LONG(STACK) }
|
|
||||||
}
|
|
||||||
|
|
|
@ -1,176 +0,0 @@
|
||||||
parameter param_t pt = '{
|
|
||||||
BHT_ADDR_HI : 8'h09 ,
|
|
||||||
BHT_ADDR_LO : 6'h02 ,
|
|
||||||
BHT_ARRAY_DEPTH : 15'h0100 ,
|
|
||||||
BHT_GHR_HASH_1 : 5'h00 ,
|
|
||||||
BHT_GHR_SIZE : 8'h08 ,
|
|
||||||
BHT_SIZE : 16'h0200 ,
|
|
||||||
BITMANIP_ZBA : 5'h00 ,
|
|
||||||
BITMANIP_ZBB : 5'h01 ,
|
|
||||||
BITMANIP_ZBC : 5'h00 ,
|
|
||||||
BITMANIP_ZBE : 5'h00 ,
|
|
||||||
BITMANIP_ZBF : 5'h00 ,
|
|
||||||
BITMANIP_ZBP : 5'h00 ,
|
|
||||||
BITMANIP_ZBR : 5'h00 ,
|
|
||||||
BITMANIP_ZBS : 5'h01 ,
|
|
||||||
BTB_ADDR_HI : 9'h009 ,
|
|
||||||
BTB_ADDR_LO : 6'h02 ,
|
|
||||||
BTB_ARRAY_DEPTH : 13'h0100 ,
|
|
||||||
BTB_BTAG_FOLD : 5'h00 ,
|
|
||||||
BTB_BTAG_SIZE : 9'h005 ,
|
|
||||||
BTB_ENABLE : 5'h01 ,
|
|
||||||
BTB_FOLD2_INDEX_HASH : 5'h00 ,
|
|
||||||
BTB_FULLYA : 5'h00 ,
|
|
||||||
BTB_INDEX1_HI : 9'h009 ,
|
|
||||||
BTB_INDEX1_LO : 9'h002 ,
|
|
||||||
BTB_INDEX2_HI : 9'h011 ,
|
|
||||||
BTB_INDEX2_LO : 9'h00A ,
|
|
||||||
BTB_INDEX3_HI : 9'h019 ,
|
|
||||||
BTB_INDEX3_LO : 9'h012 ,
|
|
||||||
BTB_SIZE : 14'h0200 ,
|
|
||||||
BTB_TOFFSET_SIZE : 9'h00C ,
|
|
||||||
BUILD_AHB_LITE : 4'h0 ,
|
|
||||||
BUILD_AXI4 : 5'h01 ,
|
|
||||||
BUILD_AXI_NATIVE : 5'h01 ,
|
|
||||||
BUS_PRTY_DEFAULT : 6'h03 ,
|
|
||||||
DATA_ACCESS_ADDR0 : 36'h000000000 ,
|
|
||||||
DATA_ACCESS_ADDR1 : 36'h000000000 ,
|
|
||||||
DATA_ACCESS_ADDR2 : 36'h000000000 ,
|
|
||||||
DATA_ACCESS_ADDR3 : 36'h000000000 ,
|
|
||||||
DATA_ACCESS_ADDR4 : 36'h000000000 ,
|
|
||||||
DATA_ACCESS_ADDR5 : 36'h000000000 ,
|
|
||||||
DATA_ACCESS_ADDR6 : 36'h000000000 ,
|
|
||||||
DATA_ACCESS_ADDR7 : 36'h000000000 ,
|
|
||||||
DATA_ACCESS_ENABLE0 : 5'h00 ,
|
|
||||||
DATA_ACCESS_ENABLE1 : 5'h00 ,
|
|
||||||
DATA_ACCESS_ENABLE2 : 5'h00 ,
|
|
||||||
DATA_ACCESS_ENABLE3 : 5'h00 ,
|
|
||||||
DATA_ACCESS_ENABLE4 : 5'h00 ,
|
|
||||||
DATA_ACCESS_ENABLE5 : 5'h00 ,
|
|
||||||
DATA_ACCESS_ENABLE6 : 5'h00 ,
|
|
||||||
DATA_ACCESS_ENABLE7 : 5'h00 ,
|
|
||||||
DATA_ACCESS_MASK0 : 36'h0FFFFFFFF ,
|
|
||||||
DATA_ACCESS_MASK1 : 36'h0FFFFFFFF ,
|
|
||||||
DATA_ACCESS_MASK2 : 36'h0FFFFFFFF ,
|
|
||||||
DATA_ACCESS_MASK3 : 36'h0FFFFFFFF ,
|
|
||||||
DATA_ACCESS_MASK4 : 36'h0FFFFFFFF ,
|
|
||||||
DATA_ACCESS_MASK5 : 36'h0FFFFFFFF ,
|
|
||||||
DATA_ACCESS_MASK6 : 36'h0FFFFFFFF ,
|
|
||||||
DATA_ACCESS_MASK7 : 36'h0FFFFFFFF ,
|
|
||||||
DCCM_BANK_BITS : 7'h02 ,
|
|
||||||
DCCM_BITS : 9'h010 ,
|
|
||||||
DCCM_BYTE_WIDTH : 7'h04 ,
|
|
||||||
DCCM_DATA_WIDTH : 10'h020 ,
|
|
||||||
DCCM_ECC_WIDTH : 7'h07 ,
|
|
||||||
DCCM_ENABLE : 5'h01 ,
|
|
||||||
DCCM_FDATA_WIDTH : 10'h027 ,
|
|
||||||
DCCM_INDEX_BITS : 8'h0C ,
|
|
||||||
DCCM_NUM_BANKS : 9'h004 ,
|
|
||||||
DCCM_REGION : 8'h0F ,
|
|
||||||
DCCM_SADR : 36'h0F0040000 ,
|
|
||||||
DCCM_SIZE : 14'h0040 ,
|
|
||||||
DCCM_WIDTH_BITS : 6'h02 ,
|
|
||||||
DIV_BIT : 7'h04 ,
|
|
||||||
DIV_NEW : 5'h01 ,
|
|
||||||
DMA_BUF_DEPTH : 7'h05 ,
|
|
||||||
DMA_BUS_ID : 9'h001 ,
|
|
||||||
DMA_BUS_PRTY : 6'h02 ,
|
|
||||||
DMA_BUS_TAG : 8'h01 ,
|
|
||||||
FAST_INTERRUPT_REDIRECT : 5'h01 ,
|
|
||||||
ICACHE_2BANKS : 5'h01 ,
|
|
||||||
ICACHE_BANK_BITS : 7'h01 ,
|
|
||||||
ICACHE_BANK_HI : 7'h03 ,
|
|
||||||
ICACHE_BANK_LO : 6'h03 ,
|
|
||||||
ICACHE_BANK_WIDTH : 8'h08 ,
|
|
||||||
ICACHE_BANKS_WAY : 7'h02 ,
|
|
||||||
ICACHE_BEAT_ADDR_HI : 8'h05 ,
|
|
||||||
ICACHE_BEAT_BITS : 8'h03 ,
|
|
||||||
ICACHE_BYPASS_ENABLE : 5'h01 ,
|
|
||||||
ICACHE_DATA_DEPTH : 18'h00200 ,
|
|
||||||
ICACHE_DATA_INDEX_LO : 7'h04 ,
|
|
||||||
ICACHE_DATA_WIDTH : 11'h040 ,
|
|
||||||
ICACHE_ECC : 5'h01 ,
|
|
||||||
ICACHE_ENABLE : 5'h01 ,
|
|
||||||
ICACHE_FDATA_WIDTH : 11'h047 ,
|
|
||||||
ICACHE_INDEX_HI : 9'h00C ,
|
|
||||||
ICACHE_LN_SZ : 11'h040 ,
|
|
||||||
ICACHE_NUM_BEATS : 8'h08 ,
|
|
||||||
ICACHE_NUM_BYPASS : 8'h02 ,
|
|
||||||
ICACHE_NUM_BYPASS_WIDTH : 8'h02 ,
|
|
||||||
ICACHE_NUM_WAYS : 7'h02 ,
|
|
||||||
ICACHE_ONLY : 5'h00 ,
|
|
||||||
ICACHE_SCND_LAST : 8'h06 ,
|
|
||||||
ICACHE_SIZE : 13'h0010 ,
|
|
||||||
ICACHE_STATUS_BITS : 7'h01 ,
|
|
||||||
ICACHE_TAG_BYPASS_ENABLE : 5'h01 ,
|
|
||||||
ICACHE_TAG_DEPTH : 17'h00080 ,
|
|
||||||
ICACHE_TAG_INDEX_LO : 7'h06 ,
|
|
||||||
ICACHE_TAG_LO : 9'h00D ,
|
|
||||||
ICACHE_TAG_NUM_BYPASS : 8'h02 ,
|
|
||||||
ICACHE_TAG_NUM_BYPASS_WIDTH : 8'h02 ,
|
|
||||||
ICACHE_WAYPACK : 5'h01 ,
|
|
||||||
ICCM_BANK_BITS : 7'h02 ,
|
|
||||||
ICCM_BANK_HI : 9'h003 ,
|
|
||||||
ICCM_BANK_INDEX_LO : 9'h004 ,
|
|
||||||
ICCM_BITS : 9'h010 ,
|
|
||||||
ICCM_ENABLE : 5'h01 ,
|
|
||||||
ICCM_ICACHE : 5'h01 ,
|
|
||||||
ICCM_INDEX_BITS : 8'h0C ,
|
|
||||||
ICCM_NUM_BANKS : 9'h004 ,
|
|
||||||
ICCM_ONLY : 5'h00 ,
|
|
||||||
ICCM_REGION : 8'h0E ,
|
|
||||||
ICCM_SADR : 36'h0EE000000 ,
|
|
||||||
ICCM_SIZE : 14'h0040 ,
|
|
||||||
IFU_BUS_ID : 5'h01 ,
|
|
||||||
IFU_BUS_PRTY : 6'h02 ,
|
|
||||||
IFU_BUS_TAG : 8'h03 ,
|
|
||||||
INST_ACCESS_ADDR0 : 36'h000000000 ,
|
|
||||||
INST_ACCESS_ADDR1 : 36'h000000000 ,
|
|
||||||
INST_ACCESS_ADDR2 : 36'h000000000 ,
|
|
||||||
INST_ACCESS_ADDR3 : 36'h000000000 ,
|
|
||||||
INST_ACCESS_ADDR4 : 36'h000000000 ,
|
|
||||||
INST_ACCESS_ADDR5 : 36'h000000000 ,
|
|
||||||
INST_ACCESS_ADDR6 : 36'h000000000 ,
|
|
||||||
INST_ACCESS_ADDR7 : 36'h000000000 ,
|
|
||||||
INST_ACCESS_ENABLE0 : 5'h00 ,
|
|
||||||
INST_ACCESS_ENABLE1 : 5'h00 ,
|
|
||||||
INST_ACCESS_ENABLE2 : 5'h00 ,
|
|
||||||
INST_ACCESS_ENABLE3 : 5'h00 ,
|
|
||||||
INST_ACCESS_ENABLE4 : 5'h00 ,
|
|
||||||
INST_ACCESS_ENABLE5 : 5'h00 ,
|
|
||||||
INST_ACCESS_ENABLE6 : 5'h00 ,
|
|
||||||
INST_ACCESS_ENABLE7 : 5'h00 ,
|
|
||||||
INST_ACCESS_MASK0 : 36'h0FFFFFFFF ,
|
|
||||||
INST_ACCESS_MASK1 : 36'h0FFFFFFFF ,
|
|
||||||
INST_ACCESS_MASK2 : 36'h0FFFFFFFF ,
|
|
||||||
INST_ACCESS_MASK3 : 36'h0FFFFFFFF ,
|
|
||||||
INST_ACCESS_MASK4 : 36'h0FFFFFFFF ,
|
|
||||||
INST_ACCESS_MASK5 : 36'h0FFFFFFFF ,
|
|
||||||
INST_ACCESS_MASK6 : 36'h0FFFFFFFF ,
|
|
||||||
INST_ACCESS_MASK7 : 36'h0FFFFFFFF ,
|
|
||||||
LOAD_TO_USE_PLUS1 : 5'h00 ,
|
|
||||||
LSU2DMA : 5'h00 ,
|
|
||||||
LSU_BUS_ID : 5'h01 ,
|
|
||||||
LSU_BUS_PRTY : 6'h02 ,
|
|
||||||
LSU_BUS_TAG : 8'h03 ,
|
|
||||||
LSU_NUM_NBLOAD : 9'h004 ,
|
|
||||||
LSU_NUM_NBLOAD_WIDTH : 7'h02 ,
|
|
||||||
LSU_SB_BITS : 9'h010 ,
|
|
||||||
LSU_STBUF_DEPTH : 8'h04 ,
|
|
||||||
NO_ICCM_NO_ICACHE : 5'h00 ,
|
|
||||||
PIC_2CYCLE : 5'h00 ,
|
|
||||||
PIC_BASE_ADDR : 36'h0F00C0000 ,
|
|
||||||
PIC_BITS : 9'h00F ,
|
|
||||||
PIC_INT_WORDS : 8'h01 ,
|
|
||||||
PIC_REGION : 8'h0F ,
|
|
||||||
PIC_SIZE : 13'h0020 ,
|
|
||||||
PIC_TOTAL_INT : 12'h01F ,
|
|
||||||
PIC_TOTAL_INT_PLUS1 : 13'h0020 ,
|
|
||||||
RET_STACK_SIZE : 8'h08 ,
|
|
||||||
RV_FPGA_OPTIMIZE : 5'h01 ,
|
|
||||||
SB_BUS_ID : 5'h01 ,
|
|
||||||
SB_BUS_PRTY : 6'h02 ,
|
|
||||||
SB_BUS_TAG : 8'h01 ,
|
|
||||||
TIMER_LEGAL_EN : 5'h01
|
|
||||||
}
|
|
||||||
// parameter param_t pt = 2276'h090808000200800010000000412104000050800090104414190904000C0421800000000000000000000000000000000000000000000000000000000000000000000000000000000007FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF87FFFFFFF820804080384270C02078780200000080104085008402108106184020503080400102004211C181002008081001802004200800C0D02020820181020108601001C1DC0000000200420300000000000000000000000000000000000000000000000000000000000000000000000000000000000FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0FFFFFFFF0002101810104010000F00C0000078087808007C040101084021
|
|
|
@ -1,11 +0,0 @@
|
||||||
// NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
|
|
||||||
// This is an automatically generated file by laraib.khan on Tue Mar 2 10:41:03 PKT 2021
|
|
||||||
//
|
|
||||||
// cmd: quasar -target=default
|
|
||||||
//
|
|
||||||
|
|
||||||
`include "common_defines.vh"
|
|
||||||
`undef ASSERT_ON
|
|
||||||
`undef TEC_RV_ICG
|
|
||||||
`define TEC_RV_ICG HDBLVT16_CKGTPLT_V5_12
|
|
||||||
`define PHYSICAL 1
|
|
|
@ -1,176 +0,0 @@
|
||||||
typedef struct packed {
|
|
||||||
bit [7:0] BHT_ADDR_HI;
|
|
||||||
bit [5:0] BHT_ADDR_LO;
|
|
||||||
bit [14:0] BHT_ARRAY_DEPTH;
|
|
||||||
bit [4:0] BHT_GHR_HASH_1;
|
|
||||||
bit [7:0] BHT_GHR_SIZE;
|
|
||||||
bit [15:0] BHT_SIZE;
|
|
||||||
bit [4:0] BITMANIP_ZBA;
|
|
||||||
bit [4:0] BITMANIP_ZBB;
|
|
||||||
bit [4:0] BITMANIP_ZBC;
|
|
||||||
bit [4:0] BITMANIP_ZBE;
|
|
||||||
bit [4:0] BITMANIP_ZBF;
|
|
||||||
bit [4:0] BITMANIP_ZBP;
|
|
||||||
bit [4:0] BITMANIP_ZBR;
|
|
||||||
bit [4:0] BITMANIP_ZBS;
|
|
||||||
bit [8:0] BTB_ADDR_HI;
|
|
||||||
bit [5:0] BTB_ADDR_LO;
|
|
||||||
bit [12:0] BTB_ARRAY_DEPTH;
|
|
||||||
bit [4:0] BTB_BTAG_FOLD;
|
|
||||||
bit [8:0] BTB_BTAG_SIZE;
|
|
||||||
bit [4:0] BTB_ENABLE;
|
|
||||||
bit [4:0] BTB_FOLD2_INDEX_HASH;
|
|
||||||
bit [4:0] BTB_FULLYA;
|
|
||||||
bit [8:0] BTB_INDEX1_HI;
|
|
||||||
bit [8:0] BTB_INDEX1_LO;
|
|
||||||
bit [8:0] BTB_INDEX2_HI;
|
|
||||||
bit [8:0] BTB_INDEX2_LO;
|
|
||||||
bit [8:0] BTB_INDEX3_HI;
|
|
||||||
bit [8:0] BTB_INDEX3_LO;
|
|
||||||
bit [13:0] BTB_SIZE;
|
|
||||||
bit [8:0] BTB_TOFFSET_SIZE;
|
|
||||||
bit BUILD_AHB_LITE;
|
|
||||||
bit [4:0] BUILD_AXI4;
|
|
||||||
bit [4:0] BUILD_AXI_NATIVE;
|
|
||||||
bit [5:0] BUS_PRTY_DEFAULT;
|
|
||||||
bit [35:0] DATA_ACCESS_ADDR0;
|
|
||||||
bit [35:0] DATA_ACCESS_ADDR1;
|
|
||||||
bit [35:0] DATA_ACCESS_ADDR2;
|
|
||||||
bit [35:0] DATA_ACCESS_ADDR3;
|
|
||||||
bit [35:0] DATA_ACCESS_ADDR4;
|
|
||||||
bit [35:0] DATA_ACCESS_ADDR5;
|
|
||||||
bit [35:0] DATA_ACCESS_ADDR6;
|
|
||||||
bit [35:0] DATA_ACCESS_ADDR7;
|
|
||||||
bit [4:0] DATA_ACCESS_ENABLE0;
|
|
||||||
bit [4:0] DATA_ACCESS_ENABLE1;
|
|
||||||
bit [4:0] DATA_ACCESS_ENABLE2;
|
|
||||||
bit [4:0] DATA_ACCESS_ENABLE3;
|
|
||||||
bit [4:0] DATA_ACCESS_ENABLE4;
|
|
||||||
bit [4:0] DATA_ACCESS_ENABLE5;
|
|
||||||
bit [4:0] DATA_ACCESS_ENABLE6;
|
|
||||||
bit [4:0] DATA_ACCESS_ENABLE7;
|
|
||||||
bit [35:0] DATA_ACCESS_MASK0;
|
|
||||||
bit [35:0] DATA_ACCESS_MASK1;
|
|
||||||
bit [35:0] DATA_ACCESS_MASK2;
|
|
||||||
bit [35:0] DATA_ACCESS_MASK3;
|
|
||||||
bit [35:0] DATA_ACCESS_MASK4;
|
|
||||||
bit [35:0] DATA_ACCESS_MASK5;
|
|
||||||
bit [35:0] DATA_ACCESS_MASK6;
|
|
||||||
bit [35:0] DATA_ACCESS_MASK7;
|
|
||||||
bit [6:0] DCCM_BANK_BITS;
|
|
||||||
bit [8:0] DCCM_BITS;
|
|
||||||
bit [6:0] DCCM_BYTE_WIDTH;
|
|
||||||
bit [9:0] DCCM_DATA_WIDTH;
|
|
||||||
bit [6:0] DCCM_ECC_WIDTH;
|
|
||||||
bit [4:0] DCCM_ENABLE;
|
|
||||||
bit [9:0] DCCM_FDATA_WIDTH;
|
|
||||||
bit [7:0] DCCM_INDEX_BITS;
|
|
||||||
bit [8:0] DCCM_NUM_BANKS;
|
|
||||||
bit [7:0] DCCM_REGION;
|
|
||||||
bit [35:0] DCCM_SADR;
|
|
||||||
bit [13:0] DCCM_SIZE;
|
|
||||||
bit [5:0] DCCM_WIDTH_BITS;
|
|
||||||
bit [6:0] DIV_BIT;
|
|
||||||
bit [4:0] DIV_NEW;
|
|
||||||
bit [6:0] DMA_BUF_DEPTH;
|
|
||||||
bit [8:0] DMA_BUS_ID;
|
|
||||||
bit [5:0] DMA_BUS_PRTY;
|
|
||||||
bit [7:0] DMA_BUS_TAG;
|
|
||||||
bit [4:0] FAST_INTERRUPT_REDIRECT;
|
|
||||||
bit [4:0] ICACHE_2BANKS;
|
|
||||||
bit [6:0] ICACHE_BANK_BITS;
|
|
||||||
bit [6:0] ICACHE_BANK_HI;
|
|
||||||
bit [5:0] ICACHE_BANK_LO;
|
|
||||||
bit [7:0] ICACHE_BANK_WIDTH;
|
|
||||||
bit [6:0] ICACHE_BANKS_WAY;
|
|
||||||
bit [7:0] ICACHE_BEAT_ADDR_HI;
|
|
||||||
bit [7:0] ICACHE_BEAT_BITS;
|
|
||||||
bit [4:0] ICACHE_BYPASS_ENABLE;
|
|
||||||
bit [17:0] ICACHE_DATA_DEPTH;
|
|
||||||
bit [6:0] ICACHE_DATA_INDEX_LO;
|
|
||||||
bit [10:0] ICACHE_DATA_WIDTH;
|
|
||||||
bit [4:0] ICACHE_ECC;
|
|
||||||
bit [4:0] ICACHE_ENABLE;
|
|
||||||
bit [10:0] ICACHE_FDATA_WIDTH;
|
|
||||||
bit [8:0] ICACHE_INDEX_HI;
|
|
||||||
bit [10:0] ICACHE_LN_SZ;
|
|
||||||
bit [7:0] ICACHE_NUM_BEATS;
|
|
||||||
bit [7:0] ICACHE_NUM_BYPASS;
|
|
||||||
bit [7:0] ICACHE_NUM_BYPASS_WIDTH;
|
|
||||||
bit [6:0] ICACHE_NUM_WAYS;
|
|
||||||
bit [4:0] ICACHE_ONLY;
|
|
||||||
bit [7:0] ICACHE_SCND_LAST;
|
|
||||||
bit [12:0] ICACHE_SIZE;
|
|
||||||
bit [6:0] ICACHE_STATUS_BITS;
|
|
||||||
bit [4:0] ICACHE_TAG_BYPASS_ENABLE;
|
|
||||||
bit [16:0] ICACHE_TAG_DEPTH;
|
|
||||||
bit [6:0] ICACHE_TAG_INDEX_LO;
|
|
||||||
bit [8:0] ICACHE_TAG_LO;
|
|
||||||
bit [7:0] ICACHE_TAG_NUM_BYPASS;
|
|
||||||
bit [7:0] ICACHE_TAG_NUM_BYPASS_WIDTH;
|
|
||||||
bit [4:0] ICACHE_WAYPACK;
|
|
||||||
bit [6:0] ICCM_BANK_BITS;
|
|
||||||
bit [8:0] ICCM_BANK_HI;
|
|
||||||
bit [8:0] ICCM_BANK_INDEX_LO;
|
|
||||||
bit [8:0] ICCM_BITS;
|
|
||||||
bit [4:0] ICCM_ENABLE;
|
|
||||||
bit [4:0] ICCM_ICACHE;
|
|
||||||
bit [7:0] ICCM_INDEX_BITS;
|
|
||||||
bit [8:0] ICCM_NUM_BANKS;
|
|
||||||
bit [4:0] ICCM_ONLY;
|
|
||||||
bit [7:0] ICCM_REGION;
|
|
||||||
bit [35:0] ICCM_SADR;
|
|
||||||
bit [13:0] ICCM_SIZE;
|
|
||||||
bit [4:0] IFU_BUS_ID;
|
|
||||||
bit [5:0] IFU_BUS_PRTY;
|
|
||||||
bit [7:0] IFU_BUS_TAG;
|
|
||||||
bit [35:0] INST_ACCESS_ADDR0;
|
|
||||||
bit [35:0] INST_ACCESS_ADDR1;
|
|
||||||
bit [35:0] INST_ACCESS_ADDR2;
|
|
||||||
bit [35:0] INST_ACCESS_ADDR3;
|
|
||||||
bit [35:0] INST_ACCESS_ADDR4;
|
|
||||||
bit [35:0] INST_ACCESS_ADDR5;
|
|
||||||
bit [35:0] INST_ACCESS_ADDR6;
|
|
||||||
bit [35:0] INST_ACCESS_ADDR7;
|
|
||||||
bit [4:0] INST_ACCESS_ENABLE0;
|
|
||||||
bit [4:0] INST_ACCESS_ENABLE1;
|
|
||||||
bit [4:0] INST_ACCESS_ENABLE2;
|
|
||||||
bit [4:0] INST_ACCESS_ENABLE3;
|
|
||||||
bit [4:0] INST_ACCESS_ENABLE4;
|
|
||||||
bit [4:0] INST_ACCESS_ENABLE5;
|
|
||||||
bit [4:0] INST_ACCESS_ENABLE6;
|
|
||||||
bit [4:0] INST_ACCESS_ENABLE7;
|
|
||||||
bit [35:0] INST_ACCESS_MASK0;
|
|
||||||
bit [35:0] INST_ACCESS_MASK1;
|
|
||||||
bit [35:0] INST_ACCESS_MASK2;
|
|
||||||
bit [35:0] INST_ACCESS_MASK3;
|
|
||||||
bit [35:0] INST_ACCESS_MASK4;
|
|
||||||
bit [35:0] INST_ACCESS_MASK5;
|
|
||||||
bit [35:0] INST_ACCESS_MASK6;
|
|
||||||
bit [35:0] INST_ACCESS_MASK7;
|
|
||||||
bit [4:0] LOAD_TO_USE_PLUS1;
|
|
||||||
bit [4:0] LSU2DMA;
|
|
||||||
bit [4:0] LSU_BUS_ID;
|
|
||||||
bit [5:0] LSU_BUS_PRTY;
|
|
||||||
bit [7:0] LSU_BUS_TAG;
|
|
||||||
bit [8:0] LSU_NUM_NBLOAD;
|
|
||||||
bit [6:0] LSU_NUM_NBLOAD_WIDTH;
|
|
||||||
bit [8:0] LSU_SB_BITS;
|
|
||||||
bit [7:0] LSU_STBUF_DEPTH;
|
|
||||||
bit [4:0] NO_ICCM_NO_ICACHE;
|
|
||||||
bit [4:0] PIC_2CYCLE;
|
|
||||||
bit [35:0] PIC_BASE_ADDR;
|
|
||||||
bit [8:0] PIC_BITS;
|
|
||||||
bit [7:0] PIC_INT_WORDS;
|
|
||||||
bit [7:0] PIC_REGION;
|
|
||||||
bit [12:0] PIC_SIZE;
|
|
||||||
bit [11:0] PIC_TOTAL_INT;
|
|
||||||
bit [12:0] PIC_TOTAL_INT_PLUS1;
|
|
||||||
bit [7:0] RET_STACK_SIZE;
|
|
||||||
bit [4:0] RV_FPGA_OPTIMIZE;
|
|
||||||
bit [4:0] SB_BUS_ID;
|
|
||||||
bit [5:0] SB_BUS_PRTY;
|
|
||||||
bit [7:0] SB_BUS_TAG;
|
|
||||||
bit [4:0] TIMER_LEGAL_EN;
|
|
||||||
} param_t;
|
|
||||||
|
|
|
@ -1,778 +0,0 @@
|
||||||
# NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE NOTE
|
|
||||||
# This is an automatically generated file by laraib.khan on Tue Mar 2 10:41:03 PKT 2021
|
|
||||||
#
|
|
||||||
# cmd: quasar -target=default
|
|
||||||
#
|
|
||||||
# To use this in a perf script, use 'require $RV_ROOT/configs/config.pl'
|
|
||||||
# Reference the hash via $config{name}..
|
|
||||||
|
|
||||||
|
|
||||||
%config = (
|
|
||||||
'btb' => {
|
|
||||||
'btb_addr_hi' => 9,
|
|
||||||
'btb_toffset_size' => '12',
|
|
||||||
'btb_index3_hi' => 25,
|
|
||||||
'btb_fold2_index_hash' => 0,
|
|
||||||
'btb_index2_hi' => 17,
|
|
||||||
'btb_array_depth' => 256,
|
|
||||||
'btb_index1_hi' => 9,
|
|
||||||
'btb_index1_lo' => '2',
|
|
||||||
'btb_index2_lo' => 10,
|
|
||||||
'btb_btag_size' => 5,
|
|
||||||
'btb_addr_lo' => '2',
|
|
||||||
'btb_btag_fold' => 0,
|
|
||||||
'btb_index3_lo' => 18,
|
|
||||||
'btb_size' => 512,
|
|
||||||
'btb_enable' => '1'
|
|
||||||
},
|
|
||||||
'testbench' => {
|
|
||||||
'ext_addrwidth' => '32',
|
|
||||||
'build_axi4' => 1,
|
|
||||||
'sterr_rollback' => '0',
|
|
||||||
'clock_period' => '100',
|
|
||||||
'assert_on' => '',
|
|
||||||
'CPU_TOP' => '`RV_TOP.swerv',
|
|
||||||
'build_axi_native' => 1,
|
|
||||||
'TOP' => 'tb_top',
|
|
||||||
'lderr_rollback' => '1',
|
|
||||||
'ext_datawidth' => '64',
|
|
||||||
'RV_TOP' => '`TOP.rvtop',
|
|
||||||
'SDVT_AHB' => '0'
|
|
||||||
},
|
|
||||||
'icache' => {
|
|
||||||
'icache_bypass_enable' => '1',
|
|
||||||
'icache_tag_bypass_enable' => '1',
|
|
||||||
'icache_tag_num_bypass_width' => 2,
|
|
||||||
'icache_num_beats' => 8,
|
|
||||||
'icache_data_index_lo' => 4,
|
|
||||||
'icache_bank_bits' => 1,
|
|
||||||
'icache_fdata_width' => 71,
|
|
||||||
'icache_tag_cell' => 'ram_128x25',
|
|
||||||
'icache_tag_index_lo' => '6',
|
|
||||||
'icache_2banks' => '1',
|
|
||||||
'icache_beat_addr_hi' => 5,
|
|
||||||
'icache_scnd_last' => 6,
|
|
||||||
'icache_num_bypass_width' => 2,
|
|
||||||
'icache_data_depth' => '512',
|
|
||||||
'icache_tag_lo' => 13,
|
|
||||||
'icache_data_width' => 64,
|
|
||||||
'icache_ecc' => '1',
|
|
||||||
'icache_status_bits' => 1,
|
|
||||||
'icache_tag_depth' => 128,
|
|
||||||
'icache_num_lines_bank' => '64',
|
|
||||||
'icache_waypack' => '1',
|
|
||||||
'icache_bank_width' => 8,
|
|
||||||
'icache_enable' => 1,
|
|
||||||
'icache_beat_bits' => 3,
|
|
||||||
'icache_num_lines' => 256,
|
|
||||||
'icache_banks_way' => 2,
|
|
||||||
'icache_index_hi' => 12,
|
|
||||||
'icache_num_ways' => 2,
|
|
||||||
'icache_bank_hi' => 3,
|
|
||||||
'icache_ln_sz' => 64,
|
|
||||||
'icache_num_lines_way' => '128',
|
|
||||||
'icache_bank_lo' => 3,
|
|
||||||
'icache_num_bypass' => '2',
|
|
||||||
'icache_tag_num_bypass' => '2',
|
|
||||||
'icache_size' => 16,
|
|
||||||
'icache_data_cell' => 'ram_512x71'
|
|
||||||
},
|
|
||||||
'retstack' => {
|
|
||||||
'ret_stack_size' => '8'
|
|
||||||
},
|
|
||||||
'regwidth' => '32',
|
|
||||||
'num_mmode_perf_regs' => '4',
|
|
||||||
'xlen' => 32,
|
|
||||||
'protection' => {
|
|
||||||
'inst_access_addr0' => '0x00000000',
|
|
||||||
'data_access_mask3' => '0xffffffff',
|
|
||||||
'data_access_enable2' => '0x0',
|
|
||||||
'data_access_enable0' => '0x0',
|
|
||||||
'data_access_enable3' => '0x0',
|
|
||||||
'data_access_addr1' => '0x00000000',
|
|
||||||
'inst_access_mask0' => '0xffffffff',
|
|
||||||
'inst_access_addr2' => '0x00000000',
|
|
||||||
'data_access_addr5' => '0x00000000',
|
|
||||||
'data_access_enable7' => '0x0',
|
|
||||||
'inst_access_mask6' => '0xffffffff',
|
|
||||||
'inst_access_addr3' => '0x00000000',
|
|
||||||
'data_access_mask7' => '0xffffffff',
|
|
||||||
'inst_access_mask3' => '0xffffffff',
|
|
||||||
'inst_access_mask7' => '0xffffffff',
|
|
||||||
'inst_access_mask1' => '0xffffffff',
|
|
||||||
'inst_access_enable0' => '0x0',
|
|
||||||
'data_access_addr6' => '0x00000000',
|
|
||||||
'inst_access_mask2' => '0xffffffff',
|
|
||||||
'data_access_mask2' => '0xffffffff',
|
|
||||||
'data_access_mask0' => '0xffffffff',
|
|
||||||
'inst_access_enable1' => '0x0',
|
|
||||||
'data_access_addr2' => '0x00000000',
|
|
||||||
'inst_access_addr5' => '0x00000000',
|
|
||||||
'data_access_enable4' => '0x0',
|
|
||||||
'data_access_mask6' => '0xffffffff',
|
|
||||||
'data_access_addr0' => '0x00000000',
|
|
||||||
'data_access_enable5' => '0x0',
|
|
||||||
'data_access_addr7' => '0x00000000',
|
|
||||||
'inst_access_enable5' => '0x0',
|
|
||||||
'inst_access_mask5' => '0xffffffff',
|
|
||||||
'inst_access_enable2' => '0x0',
|
|
||||||
'data_access_addr3' => '0x00000000',
|
|
||||||
'data_access_mask5' => '0xffffffff',
|
|
||||||
'inst_access_addr6' => '0x00000000',
|
|
||||||
'inst_access_addr1' => '0x00000000',
|
|
||||||
'data_access_enable6' => '0x0',
|
|
||||||
'data_access_mask1' => '0xffffffff',
|
|
||||||
'inst_access_enable7' => '0x0',
|
|
||||||
'inst_access_enable6' => '0x0',
|
|
||||||
'inst_access_enable3' => '0x0',
|
|
||||||
'data_access_mask4' => '0xffffffff',
|
|
||||||
'data_access_addr4' => '0x00000000',
|
|
||||||
'data_access_enable1' => '0x0',
|
|
||||||
'inst_access_addr7' => '0x00000000',
|
|
||||||
'inst_access_addr4' => '0x00000000',
|
|
||||||
'inst_access_enable4' => '0x0',
|
|
||||||
'inst_access_mask4' => '0xffffffff'
|
|
||||||
},
|
|
||||||
'max_mmode_perf_event' => '516',
|
|
||||||
'bht' => {
|
|
||||||
'bht_ghr_range' => '7:0',
|
|
||||||
'bht_ghr_hash_1' => '',
|
|
||||||
'bht_size' => 512,
|
|
||||||
'bht_addr_hi' => 9,
|
|
||||||
'bht_array_depth' => 256,
|
|
||||||
'bht_hash_string' => '{hashin[8+1:2]^ghr[8-1:0]}// cf2',
|
|
||||||
'bht_addr_lo' => '2',
|
|
||||||
'bht_ghr_size' => 8
|
|
||||||
},
|
|
||||||
'bus' => {
|
|
||||||
'sb_bus_id' => '1',
|
|
||||||
'dma_bus_prty' => '2',
|
|
||||||
'bus_prty_default' => '3',
|
|
||||||
'lsu_bus_id' => '1',
|
|
||||||
'ifu_bus_prty' => '2',
|
|
||||||
'ifu_bus_id' => '1',
|
|
||||||
'sb_bus_prty' => '2',
|
|
||||||
'lsu_bus_tag' => 3,
|
|
||||||
'dma_bus_tag' => '1',
|
|
||||||
'dma_bus_id' => '1',
|
|
||||||
'ifu_bus_tag' => '3',
|
|
||||||
'lsu_bus_prty' => '2',
|
|
||||||
'sb_bus_tag' => '1'
|
|
||||||
},
|
|
||||||
'harts' => 1,
|
|
||||||
'reset_vec' => '0x80000000',
|
|
||||||
'memmap' => {
|
|
||||||
'external_data_1' => '0xb0000000',
|
|
||||||
'unused_region3' => '0x50000000',
|
|
||||||
'unused_region1' => '0x70000000',
|
|
||||||
'unused_region0' => '0x90000000',
|
|
||||||
'unused_region5' => '0x30000000',
|
|
||||||
'consoleio' => '0xd0580000',
|
|
||||||
'unused_region7' => '0x10000000',
|
|
||||||
'debug_sb_mem' => '0xa0580000',
|
|
||||||
'unused_region4' => '0x40000000',
|
|
||||||
'serialio' => '0xd0580000',
|
|
||||||
'external_data' => '0xc0580000',
|
|
||||||
'unused_region8' => '0x00000000',
|
|
||||||
'unused_region6' => '0x20000000',
|
|
||||||
'unused_region2' => '0x60000000'
|
|
||||||
},
|
|
||||||
'pic' => {
|
|
||||||
'pic_mpiccfg_count' => 1,
|
|
||||||
'pic_mpiccfg_offset' => '0x3000',
|
|
||||||
'pic_bits' => 15,
|
|
||||||
'pic_meip_offset' => '0x1000',
|
|
||||||
'pic_meigwclr_offset' => '0x5000',
|
|
||||||
'pic_meipt_offset' => '0x3004',
|
|
||||||
'pic_meipt_mask' => '0x0',
|
|
||||||
'pic_meigwctrl_mask' => '0x3',
|
|
||||||
'pic_total_int_plus1' => 32,
|
|
||||||
'pic_meipl_count' => 31,
|
|
||||||
'pic_meigwctrl_count' => 31,
|
|
||||||
'pic_mpiccfg_mask' => '0x1',
|
|
||||||
'pic_meie_mask' => '0x1',
|
|
||||||
'pic_meigwctrl_offset' => '0x4000',
|
|
||||||
'pic_int_words' => 1,
|
|
||||||
'pic_meipl_offset' => '0x0000',
|
|
||||||
'pic_meigwclr_count' => 31,
|
|
||||||
'pic_meigwclr_mask' => '0x0',
|
|
||||||
'pic_offset' => '0xc0000',
|
|
||||||
'pic_meie_offset' => '0x2000',
|
|
||||||
'pic_region' => '0xf',
|
|
||||||
'pic_total_int' => 31,
|
|
||||||
'pic_meie_count' => 31,
|
|
||||||
'pic_meip_mask' => '0x0',
|
|
||||||
'pic_meipt_count' => 31,
|
|
||||||
'pic_base_addr' => '0xf00c0000',
|
|
||||||
'pic_size' => 32,
|
|
||||||
'pic_meipl_mask' => '0xf',
|
|
||||||
'pic_meip_count' => 1
|
|
||||||
},
|
|
||||||
'nmi_vec' => '0x11110000',
|
|
||||||
'dccm' => {
|
|
||||||
'dccm_rows' => '4096',
|
|
||||||
'dccm_reserved' => '0x1400',
|
|
||||||
'dccm_bank_bits' => 2,
|
|
||||||
'dccm_size' => 64,
|
|
||||||
'dccm_width_bits' => 2,
|
|
||||||
'dccm_enable' => '1',
|
|
||||||
'dccm_byte_width' => '4',
|
|
||||||
'dccm_ecc_width' => 7,
|
|
||||||
'dccm_data_width' => 32,
|
|
||||||
'lsu_sb_bits' => 16,
|
|
||||||
'dccm_region' => '0xf',
|
|
||||||
'dccm_offset' => '0x40000',
|
|
||||||
'dccm_sadr' => '0xf0040000',
|
|
||||||
'dccm_eadr' => '0xf004ffff',
|
|
||||||
'dccm_num_banks_4' => '',
|
|
||||||
'dccm_size_64' => '',
|
|
||||||
'dccm_data_cell' => 'ram_4096x39',
|
|
||||||
'dccm_fdata_width' => 39,
|
|
||||||
'dccm_num_banks' => '4',
|
|
||||||
'dccm_index_bits' => 12,
|
|
||||||
'dccm_bits' => 16
|
|
||||||
},
|
|
||||||
'perf_events' => [
|
|
||||||
1,
|
|
||||||
2,
|
|
||||||
3,
|
|
||||||
4,
|
|
||||||
5,
|
|
||||||
6,
|
|
||||||
7,
|
|
||||||
8,
|
|
||||||
9,
|
|
||||||
10,
|
|
||||||
11,
|
|
||||||
12,
|
|
||||||
13,
|
|
||||||
14,
|
|
||||||
15,
|
|
||||||
16,
|
|
||||||
17,
|
|
||||||
18,
|
|
||||||
19,
|
|
||||||
20,
|
|
||||||
21,
|
|
||||||
22,
|
|
||||||
23,
|
|
||||||
24,
|
|
||||||
25,
|
|
||||||
26,
|
|
||||||
27,
|
|
||||||
28,
|
|
||||||
30,
|
|
||||||
31,
|
|
||||||
32,
|
|
||||||
34,
|
|
||||||
35,
|
|
||||||
36,
|
|
||||||
37,
|
|
||||||
38,
|
|
||||||
39,
|
|
||||||
40,
|
|
||||||
41,
|
|
||||||
42,
|
|
||||||
43,
|
|
||||||
44,
|
|
||||||
45,
|
|
||||||
46,
|
|
||||||
47,
|
|
||||||
48,
|
|
||||||
49,
|
|
||||||
50,
|
|
||||||
54,
|
|
||||||
55,
|
|
||||||
56,
|
|
||||||
512,
|
|
||||||
513,
|
|
||||||
514,
|
|
||||||
515,
|
|
||||||
516
|
|
||||||
],
|
|
||||||
'iccm' => {
|
|
||||||
'iccm_data_cell' => 'ram_4096x39',
|
|
||||||
'iccm_offset' => '0xe000000',
|
|
||||||
'iccm_bits' => 16,
|
|
||||||
'iccm_sadr' => '0xee000000',
|
|
||||||
'iccm_eadr' => '0xee00ffff',
|
|
||||||
'iccm_num_banks_4' => '',
|
|
||||||
'iccm_enable' => 1,
|
|
||||||
'iccm_reserved' => '0x1000',
|
|
||||||
'iccm_size' => 64,
|
|
||||||
'iccm_bank_bits' => 2,
|
|
||||||
'iccm_size_64' => '',
|
|
||||||
'iccm_bank_index_lo' => 4,
|
|
||||||
'iccm_num_banks' => '4',
|
|
||||||
'iccm_index_bits' => 12,
|
|
||||||
'iccm_region' => '0xe',
|
|
||||||
'iccm_rows' => '4096',
|
|
||||||
'iccm_bank_hi' => 3
|
|
||||||
},
|
|
||||||
'core' => {
|
|
||||||
'bitmanip_zbf' => 0,
|
|
||||||
'bitmanip_zba' => 0,
|
|
||||||
'lsu_stbuf_depth' => '4',
|
|
||||||
'no_iccm_no_icache' => 'derived',
|
|
||||||
'lsu_num_nbload' => '4',
|
|
||||||
'bitmanip_zbr' => 0,
|
|
||||||
'bitmanip_zbs' => 1,
|
|
||||||
'bitmanip_zbe' => 0,
|
|
||||||
'bitmanip_zbp' => 0,
|
|
||||||
'dma_buf_depth' => '5',
|
|
||||||
'div_bit' => '4',
|
|
||||||
'iccm_icache' => 1,
|
|
||||||
'timer_legal_en' => '1',
|
|
||||||
'lsu2dma' => 0,
|
|
||||||
'fast_interrupt_redirect' => '1',
|
|
||||||
'iccm_only' => 'derived',
|
|
||||||
'lsu_num_nbload_width' => '2',
|
|
||||||
'rv_fpga_optimize' => 1,
|
|
||||||
'icache_only' => 'derived',
|
|
||||||
'bitmanip_zbc' => 0,
|
|
||||||
'bitmanip_zbb' => 1,
|
|
||||||
'div_new' => 1
|
|
||||||
},
|
|
||||||
'target' => 'default',
|
|
||||||
'physical' => '1',
|
|
||||||
'tec_rv_icg' => 'clockhdr',
|
|
||||||
'config_key' => '32\'hdeadbeef',
|
|
||||||
'even_odd_trigger_chains' => 'true',
|
|
||||||
'csr' => {
|
|
||||||
'mstatus' => {
|
|
||||||
'mask' => '0x88',
|
|
||||||
'exists' => 'true',
|
|
||||||
'reset' => '0x1800'
|
|
||||||
},
|
|
||||||
'mcgc' => {
|
|
||||||
'reset' => '0x200',
|
|
||||||
'number' => '0x7f8',
|
|
||||||
'poke_mask' => '0x000003ff',
|
|
||||||
'mask' => '0x000003ff',
|
|
||||||
'exists' => 'true'
|
|
||||||
},
|
|
||||||
'mhpmcounter5h' => {
|
|
||||||
'reset' => '0x0',
|
|
||||||
'mask' => '0xffffffff',
|
|
||||||
'exists' => 'true'
|
|
||||||
},
|
|
||||||
'dicad0' => {
|
|
||||||
'reset' => '0x0',
|
|
||||||
'number' => '0x7c9',
|
|
||||||
'debug' => 'true',
|
|
||||||
'mask' => '0xffffffff',
|
|
||||||
'exists' => 'true',
|
|
||||||
'comment' => 'Cache diagnostics.'
|
|
||||||
},
|
|
||||||
'mitctl0' => {
|
|
||||||
'reset' => '0x1',
|
|
||||||
'number' => '0x7d4',
|
|
||||||
'exists' => 'true',
|
|
||||||
'mask' => '0x00000007'
|
|
||||||
},
|
|
||||||
'mip' => {
|
|
||||||
'reset' => '0x0',
|
|
||||||
'poke_mask' => '0x70000888',
|
|
||||||
'mask' => '0x0',
|
|
||||||
'exists' => 'true'
|
|
||||||
},
|
|
||||||
'dmst' => {
|
|
||||||
'reset' => '0x0',
|
|
||||||
'number' => '0x7c4',
|
|
||||||
'debug' => 'true',
|
|
||||||
'mask' => '0x0',
|
|
||||||
'exists' => 'true',
|
|
||||||
'comment' => 'Memory synch trigger: Flush caches in debug mode.'
|
|
||||||
},
|
|
||||||
'mhpmcounter3' => {
|
|
||||||
'reset' => '0x0',
|
|
||||||
'mask' => '0xffffffff',
|
|
||||||
'exists' => 'true'
|
|
||||||
},
|
|
||||||
'meipt' => {
|
|
||||||
'comment' => 'External interrupt priority threshold.',
|
|
||||||
'mask' => '0xf',
|
|
||||||
'exists' => 'true',
|
|
||||||
'number' => '0xbc9',
|
|
||||||
'reset' => '0x0'
|
|
||||||
},
|
|
||||||
'pmpaddr9' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'mitbnd1' => {
|
|
||||||
'reset' => '0xffffffff',
|
|
||||||
'number' => '0x7d6',
|
|
||||||
'exists' => 'true',
|
|
||||||
'mask' => '0xffffffff'
|
|
||||||
},
|
|
||||||
'mpmc' => {
|
|
||||||
'exists' => 'true',
|
|
||||||
'mask' => '0x2',
|
|
||||||
'number' => '0x7c6',
|
|
||||||
'reset' => '0x2'
|
|
||||||
},
|
|
||||||
'mhpmcounter4' => {
|
|
||||||
'mask' => '0xffffffff',
|
|
||||||
'exists' => 'true',
|
|
||||||
'reset' => '0x0'
|
|
||||||
},
|
|
||||||
'cycle' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'mhpmevent5' => {
|
|
||||||
'reset' => '0x0',
|
|
||||||
'mask' => '0xffffffff',
|
|
||||||
'exists' => 'true'
|
|
||||||
},
|
|
||||||
'mhpmevent3' => {
|
|
||||||
'reset' => '0x0',
|
|
||||||
'mask' => '0xffffffff',
|
|
||||||
'exists' => 'true'
|
|
||||||
},
|
|
||||||
'time' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'pmpaddr8' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'mitcnt1' => {
|
|
||||||
'reset' => '0x0',
|
|
||||||
'number' => '0x7d5',
|
|
||||||
'mask' => '0xffffffff',
|
|
||||||
'exists' => 'true'
|
|
||||||
},
|
|
||||||
'tselect' => {
|
|
||||||
'reset' => '0x0',
|
|
||||||
'mask' => '0x3',
|
|
||||||
'exists' => 'true'
|
|
||||||
},
|
|
||||||
'mhpmcounter6h' => {
|
|
||||||
'reset' => '0x0',
|
|
||||||
'exists' => 'true',
|
|
||||||
'mask' => '0xffffffff'
|
|
||||||
},
|
|
||||||
'pmpaddr1' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'marchid' => {
|
|
||||||
'exists' => 'true',
|
|
||||||
'mask' => '0x0',
|
|
||||||
'reset' => '0x00000010'
|
|
||||||
},
|
|
||||||
'pmpaddr3' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'pmpaddr11' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'mfdhs' => {
|
|
||||||
'exists' => 'true',
|
|
||||||
'mask' => '0x00000003',
|
|
||||||
'comment' => 'Force Debug Halt Status',
|
|
||||||
'reset' => '0x0',
|
|
||||||
'number' => '0x7cf'
|
|
||||||
},
|
|
||||||
'dicad1' => {
|
|
||||||
'mask' => '0x3',
|
|
||||||
'exists' => 'true',
|
|
||||||
'comment' => 'Cache diagnostics.',
|
|
||||||
'reset' => '0x0',
|
|
||||||
'number' => '0x7ca',
|
|
||||||
'debug' => 'true'
|
|
||||||
},
|
|
||||||
'mhpmevent6' => {
|
|
||||||
'reset' => '0x0',
|
|
||||||
'exists' => 'true',
|
|
||||||
'mask' => '0xffffffff'
|
|
||||||
},
|
|
||||||
'mie' => {
|
|
||||||
'reset' => '0x0',
|
|
||||||
'mask' => '0x70000888',
|
|
||||||
'exists' => 'true'
|
|
||||||
},
|
|
||||||
'pmpaddr4' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'dicago' => {
|
|
||||||
'exists' => 'true',
|
|
||||||
'mask' => '0x0',
|
|
||||||
'comment' => 'Cache diagnostics.',
|
|
||||||
'reset' => '0x0',
|
|
||||||
'debug' => 'true',
|
|
||||||
'number' => '0x7cb'
|
|
||||||
},
|
|
||||||
'mfdc' => {
|
|
||||||
'mask' => '0x00071fff',
|
|
||||||
'exists' => 'true',
|
|
||||||
'reset' => '0x00070040',
|
|
||||||
'number' => '0x7f9'
|
|
||||||
},
|
|
||||||
'pmpaddr12' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'pmpcfg0' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'pmpaddr7' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'mfdht' => {
|
|
||||||
'comment' => 'Force Debug Halt Threshold',
|
|
||||||
'mask' => '0x0000003f',
|
|
||||||
'exists' => 'true',
|
|
||||||
'number' => '0x7ce',
|
|
||||||
'shared' => 'true',
|
|
||||||
'reset' => '0x0'
|
|
||||||
},
|
|
||||||
'mitbnd0' => {
|
|
||||||
'exists' => 'true',
|
|
||||||
'mask' => '0xffffffff',
|
|
||||||
'number' => '0x7d3',
|
|
||||||
'reset' => '0xffffffff'
|
|
||||||
},
|
|
||||||
'dcsr' => {
|
|
||||||
'reset' => '0x40000003',
|
|
||||||
'debug' => 'true',
|
|
||||||
'poke_mask' => '0x00008dcc',
|
|
||||||
'exists' => 'true',
|
|
||||||
'mask' => '0x00008c04'
|
|
||||||
},
|
|
||||||
'pmpaddr14' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'pmpaddr15' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'pmpaddr2' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'dicawics' => {
|
|
||||||
'number' => '0x7c8',
|
|
||||||
'debug' => 'true',
|
|
||||||
'reset' => '0x0',
|
|
||||||
'comment' => 'Cache diagnostics.',
|
|
||||||
'mask' => '0x0130fffc',
|
|
||||||
'exists' => 'true'
|
|
||||||
},
|
|
||||||
'mhpmcounter3h' => {
|
|
||||||
'exists' => 'true',
|
|
||||||
'mask' => '0xffffffff',
|
|
||||||
'reset' => '0x0'
|
|
||||||
},
|
|
||||||
'pmpcfg1' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'micect' => {
|
|
||||||
'number' => '0x7f0',
|
|
||||||
'reset' => '0x0',
|
|
||||||
'mask' => '0xffffffff',
|
|
||||||
'exists' => 'true'
|
|
||||||
},
|
|
||||||
'instret' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'pmpaddr10' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'mcpc' => {
|
|
||||||
'reset' => '0x0',
|
|
||||||
'number' => '0x7c2',
|
|
||||||
'exists' => 'true',
|
|
||||||
'mask' => '0x0',
|
|
||||||
'comment' => 'Core pause'
|
|
||||||
},
|
|
||||||
'miccmect' => {
|
|
||||||
'number' => '0x7f1',
|
|
||||||
'reset' => '0x0',
|
|
||||||
'mask' => '0xffffffff',
|
|
||||||
'exists' => 'true'
|
|
||||||
},
|
|
||||||
'mhpmcounter6' => {
|
|
||||||
'exists' => 'true',
|
|
||||||
'mask' => '0xffffffff',
|
|
||||||
'reset' => '0x0'
|
|
||||||
},
|
|
||||||
'mvendorid' => {
|
|
||||||
'reset' => '0x45',
|
|
||||||
'exists' => 'true',
|
|
||||||
'mask' => '0x0'
|
|
||||||
},
|
|
||||||
'pmpaddr13' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'meicurpl' => {
|
|
||||||
'exists' => 'true',
|
|
||||||
'mask' => '0xf',
|
|
||||||
'comment' => 'External interrupt current priority level.',
|
|
||||||
'reset' => '0x0',
|
|
||||||
'number' => '0xbcc'
|
|
||||||
},
|
|
||||||
'mhartid' => {
|
|
||||||
'mask' => '0x0',
|
|
||||||
'exists' => 'true',
|
|
||||||
'reset' => '0x0',
|
|
||||||
'poke_mask' => '0xfffffff0'
|
|
||||||
},
|
|
||||||
'mcounteren' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'pmpaddr0' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'mhpmcounter5' => {
|
|
||||||
'mask' => '0xffffffff',
|
|
||||||
'exists' => 'true',
|
|
||||||
'reset' => '0x0'
|
|
||||||
},
|
|
||||||
'mhpmcounter4h' => {
|
|
||||||
'mask' => '0xffffffff',
|
|
||||||
'exists' => 'true',
|
|
||||||
'reset' => '0x0'
|
|
||||||
},
|
|
||||||
'mimpid' => {
|
|
||||||
'mask' => '0x0',
|
|
||||||
'exists' => 'true',
|
|
||||||
'reset' => '0x3'
|
|
||||||
},
|
|
||||||
'pmpaddr6' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'pmpcfg3' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'mcountinhibit' => {
|
|
||||||
'commnet' => 'Performance counter inhibit. One bit per counter.',
|
|
||||||
'exists' => 'true',
|
|
||||||
'mask' => '0x7d',
|
|
||||||
'reset' => '0x0',
|
|
||||||
'poke_mask' => '0x7d'
|
|
||||||
},
|
|
||||||
'mscause' => {
|
|
||||||
'exists' => 'true',
|
|
||||||
'mask' => '0x0000000f',
|
|
||||||
'reset' => '0x0',
|
|
||||||
'number' => '0x7ff'
|
|
||||||
},
|
|
||||||
'mitctl1' => {
|
|
||||||
'number' => '0x7d7',
|
|
||||||
'reset' => '0x1',
|
|
||||||
'mask' => '0x0000000f',
|
|
||||||
'exists' => 'true'
|
|
||||||
},
|
|
||||||
'misa' => {
|
|
||||||
'exists' => 'true',
|
|
||||||
'mask' => '0x0',
|
|
||||||
'reset' => '0x40001104'
|
|
||||||
},
|
|
||||||
'pmpaddr5' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'pmpcfg2' => {
|
|
||||||
'exists' => 'false'
|
|
||||||
},
|
|
||||||
'mhpmevent4' => {
|
|
||||||
'reset' => '0x0',
|
|
||||||
'exists' => 'true',
|
|
||||||
'mask' => '0xffffffff'
|
|
||||||
},
|
|
||||||
'meicidpl' => {
|
|
||||||
'reset' => '0x0',
|
|
||||||
'number' => '0xbcb',
|
|
||||||
'mask' => '0xf',
|
|
||||||
'exists' => 'true',
|
|
||||||
'comment' => 'External interrupt claim id priority level.'
|
|
||||||
},
|
|
||||||
'mdccmect' => {
|
|
||||||
'reset' => '0x0',
|
|
||||||
'number' => '0x7f2',
|
|
||||||
'exists' => 'true',
|
|
||||||
'mask' => '0xffffffff'
|
|
||||||
},
|
|
||||||
'mrac' => {
|
|
||||||
'shared' => 'true',
|
|
||||||
'reset' => '0x0',
|
|
||||||
'number' => '0x7c0',
|
|
||||||
'mask' => '0xffffffff',
|
|
||||||
'exists' => 'true',
|
|
||||||
'comment' => 'Memory region io and cache control.'
|
|
||||||
},
|
|
||||||
'mitcnt0' => {
|
|
||||||
'number' => '0x7d2',
|
|
||||||
'reset' => '0x0',
|
|
||||||
'exists' => 'true',
|
|
||||||
'mask' => '0xffffffff'
|
|
||||||
}
|
|
||||||
},
|
|
||||||
'numiregs' => '32',
|
|
||||||
'triggers' => [
|
|
||||||
{
|
|
||||||
'poke_mask' => [
|
|
||||||
'0x081818c7',
|
|
||||||
'0xffffffff',
|
|
||||||
'0x00000000'
|
|
||||||
],
|
|
||||||
'reset' => [
|
|
||||||
'0x23e00000',
|
|
||||||
'0x00000000',
|
|
||||||
'0x00000000'
|
|
||||||
],
|
|
||||||
'mask' => [
|
|
||||||
'0x081818c7',
|
|
||||||
'0xffffffff',
|
|
||||||
'0x00000000'
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
'mask' => [
|
|
||||||
'0x081810c7',
|
|
||||||
'0xffffffff',
|
|
||||||
'0x00000000'
|
|
||||||
],
|
|
||||||
'reset' => [
|
|
||||||
'0x23e00000',
|
|
||||||
'0x00000000',
|
|
||||||
'0x00000000'
|
|
||||||
],
|
|
||||||
'poke_mask' => [
|
|
||||||
'0x081810c7',
|
|
||||||
'0xffffffff',
|
|
||||||
'0x00000000'
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
'mask' => [
|
|
||||||
'0x081818c7',
|
|
||||||
'0xffffffff',
|
|
||||||
'0x00000000'
|
|
||||||
],
|
|
||||||
'reset' => [
|
|
||||||
'0x23e00000',
|
|
||||||
'0x00000000',
|
|
||||||
'0x00000000'
|
|
||||||
],
|
|
||||||
'poke_mask' => [
|
|
||||||
'0x081818c7',
|
|
||||||
'0xffffffff',
|
|
||||||
'0x00000000'
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
'poke_mask' => [
|
|
||||||
'0x081810c7',
|
|
||||||
'0xffffffff',
|
|
||||||
'0x00000000'
|
|
||||||
],
|
|
||||||
'reset' => [
|
|
||||||
'0x23e00000',
|
|
||||||
'0x00000000',
|
|
||||||
'0x00000000'
|
|
||||||
],
|
|
||||||
'mask' => [
|
|
||||||
'0x081810c7',
|
|
||||||
'0xffffffff',
|
|
||||||
'0x00000000'
|
|
||||||
]
|
|
||||||
}
|
|
||||||
]
|
|
||||||
);
|
|
||||||
1;
|
|
|
@ -1,100 +0,0 @@
|
||||||
// mask[3:0] = { 4'b1000 - 30b mask,4'b0100 - 31b mask, 4'b0010 - 28b mask, 4'b0001 - 32b mask }
|
|
||||||
always_comb begin
|
|
||||||
case (address[14:0])
|
|
||||||
15'b011000000000000 : mask[3:0] = 4'b0100;
|
|
||||||
15'b100000000000100 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000000001000 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000000001100 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000000010000 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000000010100 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000000011000 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000000011100 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000000100000 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000000100100 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000000101000 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000000101100 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000000110000 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000000110100 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000000111000 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000000111100 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000001000000 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000001000100 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000001001000 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000001001100 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000001010000 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000001010100 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000001011000 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000001011100 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000001100000 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000001100100 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000001101000 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000001101100 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000001110000 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000001110100 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000001111000 : mask[3:0] = 4'b1000;
|
|
||||||
15'b100000001111100 : mask[3:0] = 4'b1000;
|
|
||||||
15'b010000000000100 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000000001000 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000000001100 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000000010000 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000000010100 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000000011000 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000000011100 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000000100000 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000000100100 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000000101000 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000000101100 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000000110000 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000000110100 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000000111000 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000000111100 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000001000000 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000001000100 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000001001000 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000001001100 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000001010000 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000001010100 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000001011000 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000001011100 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000001100000 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000001100100 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000001101000 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000001101100 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000001110000 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000001110100 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000001111000 : mask[3:0] = 4'b0100;
|
|
||||||
15'b010000001111100 : mask[3:0] = 4'b0100;
|
|
||||||
15'b000000000000100 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000000001000 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000000001100 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000000010000 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000000010100 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000000011000 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000000011100 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000000100000 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000000100100 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000000101000 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000000101100 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000000110000 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000000110100 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000000111000 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000000111100 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000001000000 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000001000100 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000001001000 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000001001100 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000001010000 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000001010100 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000001011000 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000001011100 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000001100000 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000001100100 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000001101000 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000001101100 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000001110000 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000001110100 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000001111000 : mask[3:0] = 4'b0010;
|
|
||||||
15'b000000001111100 : mask[3:0] = 4'b0010;
|
|
||||||
default : mask[3:0] = 4'b0001;
|
|
||||||
endcase
|
|
||||||
end
|
|
|
@ -1,566 +0,0 @@
|
||||||
{
|
|
||||||
"iccm" : {
|
|
||||||
"offset" : "0xe000000",
|
|
||||||
"size" : "0x10000",
|
|
||||||
"region" : "0xe"
|
|
||||||
},
|
|
||||||
"enable_zbe" : 0,
|
|
||||||
"nmi_vec" : "0x11110000",
|
|
||||||
"dccm" : {
|
|
||||||
"size" : "0x10000",
|
|
||||||
"offset" : "0x40000",
|
|
||||||
"region" : "0xf"
|
|
||||||
},
|
|
||||||
"load_error_rollback" : "1",
|
|
||||||
"enable_zba" : 0,
|
|
||||||
"enable_zbs" : 1,
|
|
||||||
"amo_illegal_outside_dccm" : "true",
|
|
||||||
"even_odd_trigger_chains" : "true",
|
|
||||||
"csr" : {
|
|
||||||
"mstatus" : {
|
|
||||||
"mask" : "0x88",
|
|
||||||
"exists" : "true",
|
|
||||||
"reset" : "0x1800"
|
|
||||||
},
|
|
||||||
"mcgc" : {
|
|
||||||
"reset" : "0x200",
|
|
||||||
"number" : "0x7f8",
|
|
||||||
"poke_mask" : "0x000003ff",
|
|
||||||
"mask" : "0x000003ff",
|
|
||||||
"exists" : "true"
|
|
||||||
},
|
|
||||||
"mhpmcounter5h" : {
|
|
||||||
"reset" : "0x0",
|
|
||||||
"mask" : "0xffffffff",
|
|
||||||
"exists" : "true"
|
|
||||||
},
|
|
||||||
"dicad0" : {
|
|
||||||
"reset" : "0x0",
|
|
||||||
"number" : "0x7c9",
|
|
||||||
"debug" : "true",
|
|
||||||
"mask" : "0xffffffff",
|
|
||||||
"exists" : "true",
|
|
||||||
"comment" : "Cache diagnostics."
|
|
||||||
},
|
|
||||||
"mitctl0" : {
|
|
||||||
"reset" : "0x1",
|
|
||||||
"number" : "0x7d4",
|
|
||||||
"exists" : "true",
|
|
||||||
"mask" : "0x00000007"
|
|
||||||
},
|
|
||||||
"mip" : {
|
|
||||||
"reset" : "0x0",
|
|
||||||
"poke_mask" : "0x70000888",
|
|
||||||
"mask" : "0x0",
|
|
||||||
"exists" : "true"
|
|
||||||
},
|
|
||||||
"dmst" : {
|
|
||||||
"reset" : "0x0",
|
|
||||||
"number" : "0x7c4",
|
|
||||||
"debug" : "true",
|
|
||||||
"mask" : "0x0",
|
|
||||||
"exists" : "true",
|
|
||||||
"comment" : "Memory synch trigger: Flush caches in debug mode."
|
|
||||||
},
|
|
||||||
"mhpmcounter3" : {
|
|
||||||
"reset" : "0x0",
|
|
||||||
"mask" : "0xffffffff",
|
|
||||||
"exists" : "true"
|
|
||||||
},
|
|
||||||
"meipt" : {
|
|
||||||
"comment" : "External interrupt priority threshold.",
|
|
||||||
"mask" : "0xf",
|
|
||||||
"exists" : "true",
|
|
||||||
"number" : "0xbc9",
|
|
||||||
"reset" : "0x0"
|
|
||||||
},
|
|
||||||
"pmpaddr9" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"mitbnd1" : {
|
|
||||||
"reset" : "0xffffffff",
|
|
||||||
"number" : "0x7d6",
|
|
||||||
"exists" : "true",
|
|
||||||
"mask" : "0xffffffff"
|
|
||||||
},
|
|
||||||
"mpmc" : {
|
|
||||||
"exists" : "true",
|
|
||||||
"mask" : "0x2",
|
|
||||||
"number" : "0x7c6",
|
|
||||||
"reset" : "0x2"
|
|
||||||
},
|
|
||||||
"mhpmcounter4" : {
|
|
||||||
"mask" : "0xffffffff",
|
|
||||||
"exists" : "true",
|
|
||||||
"reset" : "0x0"
|
|
||||||
},
|
|
||||||
"cycle" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"mhpmevent5" : {
|
|
||||||
"reset" : "0x0",
|
|
||||||
"mask" : "0xffffffff",
|
|
||||||
"exists" : "true"
|
|
||||||
},
|
|
||||||
"mhpmevent3" : {
|
|
||||||
"reset" : "0x0",
|
|
||||||
"mask" : "0xffffffff",
|
|
||||||
"exists" : "true"
|
|
||||||
},
|
|
||||||
"time" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"pmpaddr8" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"mitcnt1" : {
|
|
||||||
"reset" : "0x0",
|
|
||||||
"number" : "0x7d5",
|
|
||||||
"mask" : "0xffffffff",
|
|
||||||
"exists" : "true"
|
|
||||||
},
|
|
||||||
"tselect" : {
|
|
||||||
"reset" : "0x0",
|
|
||||||
"mask" : "0x3",
|
|
||||||
"exists" : "true"
|
|
||||||
},
|
|
||||||
"mhpmcounter6h" : {
|
|
||||||
"reset" : "0x0",
|
|
||||||
"exists" : "true",
|
|
||||||
"mask" : "0xffffffff"
|
|
||||||
},
|
|
||||||
"pmpaddr1" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"marchid" : {
|
|
||||||
"exists" : "true",
|
|
||||||
"mask" : "0x0",
|
|
||||||
"reset" : "0x00000010"
|
|
||||||
},
|
|
||||||
"pmpaddr3" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"pmpaddr11" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"mfdhs" : {
|
|
||||||
"exists" : "true",
|
|
||||||
"mask" : "0x00000003",
|
|
||||||
"comment" : "Force Debug Halt Status",
|
|
||||||
"reset" : "0x0",
|
|
||||||
"number" : "0x7cf"
|
|
||||||
},
|
|
||||||
"dicad1" : {
|
|
||||||
"mask" : "0x3",
|
|
||||||
"exists" : "true",
|
|
||||||
"comment" : "Cache diagnostics.",
|
|
||||||
"reset" : "0x0",
|
|
||||||
"number" : "0x7ca",
|
|
||||||
"debug" : "true"
|
|
||||||
},
|
|
||||||
"mhpmevent6" : {
|
|
||||||
"reset" : "0x0",
|
|
||||||
"exists" : "true",
|
|
||||||
"mask" : "0xffffffff"
|
|
||||||
},
|
|
||||||
"mie" : {
|
|
||||||
"reset" : "0x0",
|
|
||||||
"mask" : "0x70000888",
|
|
||||||
"exists" : "true"
|
|
||||||
},
|
|
||||||
"pmpaddr4" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"dicago" : {
|
|
||||||
"exists" : "true",
|
|
||||||
"mask" : "0x0",
|
|
||||||
"comment" : "Cache diagnostics.",
|
|
||||||
"reset" : "0x0",
|
|
||||||
"debug" : "true",
|
|
||||||
"number" : "0x7cb"
|
|
||||||
},
|
|
||||||
"mfdc" : {
|
|
||||||
"mask" : "0x00071fff",
|
|
||||||
"exists" : "true",
|
|
||||||
"reset" : "0x00070040",
|
|
||||||
"number" : "0x7f9"
|
|
||||||
},
|
|
||||||
"pmpaddr12" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"pmpcfg0" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"pmpaddr7" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"mfdht" : {
|
|
||||||
"comment" : "Force Debug Halt Threshold",
|
|
||||||
"mask" : "0x0000003f",
|
|
||||||
"exists" : "true",
|
|
||||||
"number" : "0x7ce",
|
|
||||||
"shared" : "true",
|
|
||||||
"reset" : "0x0"
|
|
||||||
},
|
|
||||||
"mitbnd0" : {
|
|
||||||
"exists" : "true",
|
|
||||||
"mask" : "0xffffffff",
|
|
||||||
"number" : "0x7d3",
|
|
||||||
"reset" : "0xffffffff"
|
|
||||||
},
|
|
||||||
"dcsr" : {
|
|
||||||
"reset" : "0x40000003",
|
|
||||||
"debug" : "true",
|
|
||||||
"poke_mask" : "0x00008dcc",
|
|
||||||
"exists" : "true",
|
|
||||||
"mask" : "0x00008c04"
|
|
||||||
},
|
|
||||||
"pmpaddr14" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"pmpaddr15" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"pmpaddr2" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"dicawics" : {
|
|
||||||
"number" : "0x7c8",
|
|
||||||
"debug" : "true",
|
|
||||||
"reset" : "0x0",
|
|
||||||
"comment" : "Cache diagnostics.",
|
|
||||||
"mask" : "0x0130fffc",
|
|
||||||
"exists" : "true"
|
|
||||||
},
|
|
||||||
"mhpmcounter3h" : {
|
|
||||||
"exists" : "true",
|
|
||||||
"mask" : "0xffffffff",
|
|
||||||
"reset" : "0x0"
|
|
||||||
},
|
|
||||||
"pmpcfg1" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"micect" : {
|
|
||||||
"number" : "0x7f0",
|
|
||||||
"reset" : "0x0",
|
|
||||||
"mask" : "0xffffffff",
|
|
||||||
"exists" : "true"
|
|
||||||
},
|
|
||||||
"instret" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"pmpaddr10" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"mcpc" : {
|
|
||||||
"reset" : "0x0",
|
|
||||||
"number" : "0x7c2",
|
|
||||||
"exists" : "true",
|
|
||||||
"mask" : "0x0",
|
|
||||||
"comment" : "Core pause"
|
|
||||||
},
|
|
||||||
"miccmect" : {
|
|
||||||
"number" : "0x7f1",
|
|
||||||
"reset" : "0x0",
|
|
||||||
"mask" : "0xffffffff",
|
|
||||||
"exists" : "true"
|
|
||||||
},
|
|
||||||
"mhpmcounter6" : {
|
|
||||||
"exists" : "true",
|
|
||||||
"mask" : "0xffffffff",
|
|
||||||
"reset" : "0x0"
|
|
||||||
},
|
|
||||||
"mvendorid" : {
|
|
||||||
"reset" : "0x45",
|
|
||||||
"exists" : "true",
|
|
||||||
"mask" : "0x0"
|
|
||||||
},
|
|
||||||
"pmpaddr13" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"meicurpl" : {
|
|
||||||
"exists" : "true",
|
|
||||||
"mask" : "0xf",
|
|
||||||
"comment" : "External interrupt current priority level.",
|
|
||||||
"reset" : "0x0",
|
|
||||||
"number" : "0xbcc"
|
|
||||||
},
|
|
||||||
"mhartid" : {
|
|
||||||
"mask" : "0x0",
|
|
||||||
"exists" : "true",
|
|
||||||
"reset" : "0x0",
|
|
||||||
"poke_mask" : "0xfffffff0"
|
|
||||||
},
|
|
||||||
"mcounteren" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"pmpaddr0" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"mhpmcounter5" : {
|
|
||||||
"mask" : "0xffffffff",
|
|
||||||
"exists" : "true",
|
|
||||||
"reset" : "0x0"
|
|
||||||
},
|
|
||||||
"mhpmcounter4h" : {
|
|
||||||
"mask" : "0xffffffff",
|
|
||||||
"exists" : "true",
|
|
||||||
"reset" : "0x0"
|
|
||||||
},
|
|
||||||
"mimpid" : {
|
|
||||||
"mask" : "0x0",
|
|
||||||
"exists" : "true",
|
|
||||||
"reset" : "0x3"
|
|
||||||
},
|
|
||||||
"pmpaddr6" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"pmpcfg3" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"mcountinhibit" : {
|
|
||||||
"commnet" : "Performance counter inhibit. One bit per counter.",
|
|
||||||
"exists" : "true",
|
|
||||||
"mask" : "0x7d",
|
|
||||||
"reset" : "0x0",
|
|
||||||
"poke_mask" : "0x7d"
|
|
||||||
},
|
|
||||||
"mscause" : {
|
|
||||||
"exists" : "true",
|
|
||||||
"mask" : "0x0000000f",
|
|
||||||
"reset" : "0x0",
|
|
||||||
"number" : "0x7ff"
|
|
||||||
},
|
|
||||||
"mitctl1" : {
|
|
||||||
"number" : "0x7d7",
|
|
||||||
"reset" : "0x1",
|
|
||||||
"mask" : "0x0000000f",
|
|
||||||
"exists" : "true"
|
|
||||||
},
|
|
||||||
"misa" : {
|
|
||||||
"exists" : "true",
|
|
||||||
"mask" : "0x0",
|
|
||||||
"reset" : "0x40001104"
|
|
||||||
},
|
|
||||||
"pmpaddr5" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"pmpcfg2" : {
|
|
||||||
"exists" : "false"
|
|
||||||
},
|
|
||||||
"mhpmevent4" : {
|
|
||||||
"reset" : "0x0",
|
|
||||||
"exists" : "true",
|
|
||||||
"mask" : "0xffffffff"
|
|
||||||
},
|
|
||||||
"meicidpl" : {
|
|
||||||
"reset" : "0x0",
|
|
||||||
"number" : "0xbcb",
|
|
||||||
"mask" : "0xf",
|
|
||||||
"exists" : "true",
|
|
||||||
"comment" : "External interrupt claim id priority level."
|
|
||||||
},
|
|
||||||
"mdccmect" : {
|
|
||||||
"reset" : "0x0",
|
|
||||||
"number" : "0x7f2",
|
|
||||||
"exists" : "true",
|
|
||||||
"mask" : "0xffffffff"
|
|
||||||
},
|
|
||||||
"mrac" : {
|
|
||||||
"shared" : "true",
|
|
||||||
"reset" : "0x0",
|
|
||||||
"number" : "0x7c0",
|
|
||||||
"mask" : "0xffffffff",
|
|
||||||
"exists" : "true",
|
|
||||||
"comment" : "Memory region io and cache control."
|
|
||||||
},
|
|
||||||
"mitcnt0" : {
|
|
||||||
"number" : "0x7d2",
|
|
||||||
"reset" : "0x0",
|
|
||||||
"exists" : "true",
|
|
||||||
"mask" : "0xffffffff"
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"enable_zbf" : 0,
|
|
||||||
"triggers" : [
|
|
||||||
{
|
|
||||||
"poke_mask" : [
|
|
||||||
"0x081818c7",
|
|
||||||
"0xffffffff",
|
|
||||||
"0x00000000"
|
|
||||||
],
|
|
||||||
"reset" : [
|
|
||||||
"0x23e00000",
|
|
||||||
"0x00000000",
|
|
||||||
"0x00000000"
|
|
||||||
],
|
|
||||||
"mask" : [
|
|
||||||
"0x081818c7",
|
|
||||||
"0xffffffff",
|
|
||||||
"0x00000000"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"mask" : [
|
|
||||||
"0x081810c7",
|
|
||||||
"0xffffffff",
|
|
||||||
"0x00000000"
|
|
||||||
],
|
|
||||||
"reset" : [
|
|
||||||
"0x23e00000",
|
|
||||||
"0x00000000",
|
|
||||||
"0x00000000"
|
|
||||||
],
|
|
||||||
"poke_mask" : [
|
|
||||||
"0x081810c7",
|
|
||||||
"0xffffffff",
|
|
||||||
"0x00000000"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"mask" : [
|
|
||||||
"0x081818c7",
|
|
||||||
"0xffffffff",
|
|
||||||
"0x00000000"
|
|
||||||
],
|
|
||||||
"reset" : [
|
|
||||||
"0x23e00000",
|
|
||||||
"0x00000000",
|
|
||||||
"0x00000000"
|
|
||||||
],
|
|
||||||
"poke_mask" : [
|
|
||||||
"0x081818c7",
|
|
||||||
"0xffffffff",
|
|
||||||
"0x00000000"
|
|
||||||
]
|
|
||||||
},
|
|
||||||
{
|
|
||||||
"poke_mask" : [
|
|
||||||
"0x081810c7",
|
|
||||||
"0xffffffff",
|
|
||||||
"0x00000000"
|
|
||||||
],
|
|
||||||
"reset" : [
|
|
||||||
"0x23e00000",
|
|
||||||
"0x00000000",
|
|
||||||
"0x00000000"
|
|
||||||
],
|
|
||||||
"mask" : [
|
|
||||||
"0x081810c7",
|
|
||||||
"0xffffffff",
|
|
||||||
"0x00000000"
|
|
||||||
]
|
|
||||||
}
|
|
||||||
],
|
|
||||||
"enable_zbb" : 1,
|
|
||||||
"store_error_rollback" : "0",
|
|
||||||
"enable_zbc" : 0,
|
|
||||||
"enable_zbr" : 0,
|
|
||||||
"mmode_perf_events" : [
|
|
||||||
1,
|
|
||||||
2,
|
|
||||||
3,
|
|
||||||
4,
|
|
||||||
5,
|
|
||||||
6,
|
|
||||||
7,
|
|
||||||
8,
|
|
||||||
9,
|
|
||||||
10,
|
|
||||||
11,
|
|
||||||
12,
|
|
||||||
13,
|
|
||||||
14,
|
|
||||||
15,
|
|
||||||
16,
|
|
||||||
17,
|
|
||||||
18,
|
|
||||||
19,
|
|
||||||
20,
|
|
||||||
21,
|
|
||||||
22,
|
|
||||||
23,
|
|
||||||
24,
|
|
||||||
25,
|
|
||||||
26,
|
|
||||||
27,
|
|
||||||
28,
|
|
||||||
30,
|
|
||||||
31,
|
|
||||||
32,
|
|
||||||
34,
|
|
||||||
35,
|
|
||||||
36,
|
|
||||||
37,
|
|
||||||
38,
|
|
||||||
39,
|
|
||||||
40,
|
|
||||||
41,
|
|
||||||
42,
|
|
||||||
43,
|
|
||||||
44,
|
|
||||||
45,
|
|
||||||
46,
|
|
||||||
47,
|
|
||||||
48,
|
|
||||||
49,
|
|
||||||
50,
|
|
||||||
54,
|
|
||||||
55,
|
|
||||||
56,
|
|
||||||
512,
|
|
||||||
513,
|
|
||||||
514,
|
|
||||||
515,
|
|
||||||
516
|
|
||||||
],
|
|
||||||
"xlen" : 32,
|
|
||||||
"fast_interrupt_redirect" : "1",
|
|
||||||
"num_mmode_perf_regs" : "4",
|
|
||||||
"memory_mapped_registers" : {
|
|
||||||
"default_mask" : 0,
|
|
||||||
"size" : "0x8000",
|
|
||||||
"address" : "0xf00c0000",
|
|
||||||
"registers" : {
|
|
||||||
"meie" : {
|
|
||||||
"address" : "0xf00c2004",
|
|
||||||
"mask" : "0x1",
|
|
||||||
"count" : "31"
|
|
||||||
},
|
|
||||||
"meigwctrl" : {
|
|
||||||
"mask" : "0x3",
|
|
||||||
"address" : "0xf00c4004",
|
|
||||||
"count" : "31"
|
|
||||||
},
|
|
||||||
"meipl" : {
|
|
||||||
"mask" : "0xf",
|
|
||||||
"address" : "0xf00c0004",
|
|
||||||
"count" : "31"
|
|
||||||
},
|
|
||||||
"meip" : {
|
|
||||||
"count" : 1,
|
|
||||||
"mask" : "0x0",
|
|
||||||
"address" : "0xf00c1000"
|
|
||||||
},
|
|
||||||
"meigwclr" : {
|
|
||||||
"mask" : "0x0",
|
|
||||||
"address" : "0xf00c5004",
|
|
||||||
"count" : "31"
|
|
||||||
},
|
|
||||||
"mpiccfg" : {
|
|
||||||
"count" : 1,
|
|
||||||
"address" : "0xf00c3000",
|
|
||||||
"mask" : "0x1"
|
|
||||||
}
|
|
||||||
}
|
|
||||||
},
|
|
||||||
"enable_zbp" : 0,
|
|
||||||
"max_mmode_perf_event" : "516",
|
|
||||||
"effective_address_compatible_with_base" : "true",
|
|
||||||
"memmap" : {
|
|
||||||
"consoleio" : "0xd0580000",
|
|
||||||
"serialio" : "0xd0580000"
|
|
||||||
},
|
|
||||||
"reset_vec" : "0x80000000",
|
|
||||||
"harts" : 1
|
|
||||||
}
|
|
|
@ -1,50 +0,0 @@
|
||||||
typedef struct packed {
|
|
||||||
logic TEST1;
|
|
||||||
logic RME;
|
|
||||||
logic [3:0] RM;
|
|
||||||
|
|
||||||
logic LS;
|
|
||||||
logic DS;
|
|
||||||
logic SD;
|
|
||||||
logic TEST_RNM;
|
|
||||||
logic BC1;
|
|
||||||
logic BC2;
|
|
||||||
} ccm_ext_in_pkt_t;
|
|
||||||
|
|
||||||
typedef struct packed {
|
|
||||||
logic TEST1;
|
|
||||||
logic RME;
|
|
||||||
logic [3:0] RM;
|
|
||||||
logic LS;
|
|
||||||
logic DS;
|
|
||||||
logic SD;
|
|
||||||
logic TEST_RNM;
|
|
||||||
logic BC1;
|
|
||||||
logic BC2;
|
|
||||||
} dccm_ext_in_pkt_t;
|
|
||||||
|
|
||||||
|
|
||||||
typedef struct packed {
|
|
||||||
logic TEST1;
|
|
||||||
logic RME;
|
|
||||||
logic [3:0] RM;
|
|
||||||
logic LS;
|
|
||||||
logic DS;
|
|
||||||
logic SD;
|
|
||||||
logic TEST_RNM;
|
|
||||||
logic BC1;
|
|
||||||
logic BC2;
|
|
||||||
} ic_data_ext_in_pkt_t;
|
|
||||||
|
|
||||||
|
|
||||||
typedef struct packed {
|
|
||||||
logic TEST1;
|
|
||||||
logic RME;
|
|
||||||
logic [3:0] RM;
|
|
||||||
logic LS;
|
|
||||||
logic DS;
|
|
||||||
logic SD;
|
|
||||||
logic TEST_RNM;
|
|
||||||
logic BC1;
|
|
||||||
logic BC2;
|
|
||||||
} ic_tag_ext_in_pkt_t;
|
|
|
@ -1,179 +0,0 @@
|
||||||
//THIS IS A SELF WRITTEN PARAMETER FILE FOR CHISEL
|
|
||||||
|
|
||||||
package lib
|
|
||||||
import chisel3._
|
|
||||||
trait param {
|
|
||||||
val BHT_ADDR_HI = 0x09
|
|
||||||
val BHT_ADDR_LO = 0x02
|
|
||||||
val BHT_ARRAY_DEPTH = 0x0100
|
|
||||||
val BHT_GHR_HASH_1 = 0x00
|
|
||||||
val BHT_GHR_SIZE = 0x08
|
|
||||||
val BHT_SIZE = 0x0200
|
|
||||||
val BITMANIP_ZBA = 0x00
|
|
||||||
val BITMANIP_ZBB = 0x01
|
|
||||||
val BITMANIP_ZBC = 0x00
|
|
||||||
val BITMANIP_ZBE = 0x00
|
|
||||||
val BITMANIP_ZBF = 0x00
|
|
||||||
val BITMANIP_ZBP = 0x00
|
|
||||||
val BITMANIP_ZBR = 0x00
|
|
||||||
val BITMANIP_ZBS = 0x01
|
|
||||||
val BTB_ADDR_HI = 0x009
|
|
||||||
val BTB_ADDR_LO = 0x02
|
|
||||||
val BTB_ARRAY_DEPTH = 0x0100
|
|
||||||
val BTB_BTAG_FOLD = 0x00
|
|
||||||
val BTB_BTAG_SIZE = 0x005
|
|
||||||
val BTB_ENABLE = 0x01
|
|
||||||
val BTB_FOLD2_INDEX_HASH = 0x00
|
|
||||||
val BTB_FULLYA = 0x00
|
|
||||||
val BTB_INDEX1_HI = 0x009
|
|
||||||
val BTB_INDEX1_LO = 0x002
|
|
||||||
val BTB_INDEX2_HI = 0x011
|
|
||||||
val BTB_INDEX2_LO = 0x00A
|
|
||||||
val BTB_INDEX3_HI = 0x019
|
|
||||||
val BTB_INDEX3_LO = 0x012
|
|
||||||
val BTB_SIZE = 0x0200
|
|
||||||
val BTB_TOFFSET_SIZE = 0x00C
|
|
||||||
val BUILD_AHB_LITE = 0x0
|
|
||||||
val BUILD_AXI4 = 0x01
|
|
||||||
val BUILD_AXI_NATIVE = 0x01
|
|
||||||
val BUS_PRTY_DEFAULT = 0x03
|
|
||||||
val DATA_ACCESS_ADDR0 = 0x000000000
|
|
||||||
val DATA_ACCESS_ADDR1 = 0x000000000
|
|
||||||
val DATA_ACCESS_ADDR2 = 0x000000000
|
|
||||||
val DATA_ACCESS_ADDR3 = 0x000000000
|
|
||||||
val DATA_ACCESS_ADDR4 = 0x000000000
|
|
||||||
val DATA_ACCESS_ADDR5 = 0x000000000
|
|
||||||
val DATA_ACCESS_ADDR6 = 0x000000000
|
|
||||||
val DATA_ACCESS_ADDR7 = 0x000000000
|
|
||||||
val DATA_ACCESS_ENABLE0 = 0x00
|
|
||||||
val DATA_ACCESS_ENABLE1 = 0x00
|
|
||||||
val DATA_ACCESS_ENABLE2 = 0x00
|
|
||||||
val DATA_ACCESS_ENABLE3 = 0x00
|
|
||||||
val DATA_ACCESS_ENABLE4 = 0x00
|
|
||||||
val DATA_ACCESS_ENABLE5 = 0x00
|
|
||||||
val DATA_ACCESS_ENABLE6 = 0x00
|
|
||||||
val DATA_ACCESS_ENABLE7 = 0x00
|
|
||||||
val DATA_ACCESS_MASK0 = 0x0FFFFFFFF
|
|
||||||
val DATA_ACCESS_MASK1 = 0x0FFFFFFFF
|
|
||||||
val DATA_ACCESS_MASK2 = 0x0FFFFFFFF
|
|
||||||
val DATA_ACCESS_MASK3 = 0x0FFFFFFFF
|
|
||||||
val DATA_ACCESS_MASK4 = 0x0FFFFFFFF
|
|
||||||
val DATA_ACCESS_MASK5 = 0x0FFFFFFFF
|
|
||||||
val DATA_ACCESS_MASK6 = 0x0FFFFFFFF
|
|
||||||
val DATA_ACCESS_MASK7 = 0x0FFFFFFFF
|
|
||||||
val DCCM_BANK_BITS = 0x02
|
|
||||||
val DCCM_BITS = 0x010
|
|
||||||
val DCCM_BYTE_WIDTH = 0x04
|
|
||||||
val DCCM_DATA_WIDTH = 0x020
|
|
||||||
val DCCM_ECC_WIDTH = 0x07
|
|
||||||
val DCCM_ENABLE = 0x01
|
|
||||||
val DCCM_FDATA_WIDTH = 0x027
|
|
||||||
val DCCM_INDEX_BITS = 0x0C
|
|
||||||
val DCCM_NUM_BANKS = 0x004
|
|
||||||
val DCCM_REGION = 0x0F
|
|
||||||
val DCCM_SADR = 0x0F0040000
|
|
||||||
val DCCM_SIZE = 0x0040
|
|
||||||
val DCCM_WIDTH_BITS = 0x02
|
|
||||||
val DIV_BIT = 0x04
|
|
||||||
val DIV_NEW = 0x01
|
|
||||||
val DMA_BUF_DEPTH = 0x05
|
|
||||||
val DMA_BUS_ID = 0x001
|
|
||||||
val DMA_BUS_PRTY = 0x02
|
|
||||||
val DMA_BUS_TAG = 0x01
|
|
||||||
val FAST_INTERRUPT_REDIRECT = 0x01
|
|
||||||
val ICACHE_2BANKS = 0x01
|
|
||||||
val ICACHE_BANK_BITS = 0x01
|
|
||||||
val ICACHE_BANK_HI = 0x03
|
|
||||||
val ICACHE_BANK_LO = 0x03
|
|
||||||
val ICACHE_BANK_WIDTH = 0x08
|
|
||||||
val ICACHE_BANKS_WAY = 0x02
|
|
||||||
val ICACHE_BEAT_ADDR_HI = 0x05
|
|
||||||
val ICACHE_BEAT_BITS = 0x03
|
|
||||||
val ICACHE_BYPASS_ENABLE = 0x01
|
|
||||||
val ICACHE_DATA_DEPTH = 0x00200
|
|
||||||
val ICACHE_DATA_INDEX_LO = 0x04
|
|
||||||
val ICACHE_DATA_WIDTH = 0x040
|
|
||||||
val ICACHE_ECC = 0x01
|
|
||||||
val ICACHE_ENABLE = 0x01
|
|
||||||
val ICACHE_FDATA_WIDTH = 0x047
|
|
||||||
val ICACHE_INDEX_HI = 0x00C
|
|
||||||
val ICACHE_LN_SZ = 0x040
|
|
||||||
val ICACHE_NUM_BEATS = 0x08
|
|
||||||
val ICACHE_NUM_BYPASS = 0x02
|
|
||||||
val ICACHE_NUM_BYPASS_WIDTH = 0x02
|
|
||||||
val ICACHE_NUM_WAYS = 0x02
|
|
||||||
val ICACHE_ONLY = 0x00
|
|
||||||
val ICACHE_SCND_LAST = 0x06
|
|
||||||
val ICACHE_SIZE = 0x0010
|
|
||||||
val ICACHE_STATUS_BITS = 0x01
|
|
||||||
val ICACHE_TAG_BYPASS_ENABLE = 0x01
|
|
||||||
val ICACHE_TAG_DEPTH = 0x00080
|
|
||||||
val ICACHE_TAG_INDEX_LO = 0x06
|
|
||||||
val ICACHE_TAG_LO = 0x00D
|
|
||||||
val ICACHE_TAG_NUM_BYPASS = 0x02
|
|
||||||
val ICACHE_TAG_NUM_BYPASS_WIDTH = 0x02
|
|
||||||
val ICACHE_WAYPACK = 0x01
|
|
||||||
val ICCM_BANK_BITS = 0x02
|
|
||||||
val ICCM_BANK_HI = 0x003
|
|
||||||
val ICCM_BANK_INDEX_LO = 0x004
|
|
||||||
val ICCM_BITS = 0x010
|
|
||||||
val ICCM_ENABLE = 0x01
|
|
||||||
val ICCM_ICACHE = 0x01
|
|
||||||
val ICCM_INDEX_BITS = 0x0C
|
|
||||||
val ICCM_NUM_BANKS = 0x004
|
|
||||||
val ICCM_ONLY = 0x00
|
|
||||||
val ICCM_REGION = 0x0E
|
|
||||||
val ICCM_SADR = 0x0EE000000
|
|
||||||
val ICCM_SIZE = 0x0040
|
|
||||||
val IFU_BUS_ID = 0x01
|
|
||||||
val IFU_BUS_PRTY = 0x02
|
|
||||||
val IFU_BUS_TAG = 0x03
|
|
||||||
val INST_ACCESS_ADDR0 = 0x000000000
|
|
||||||
val INST_ACCESS_ADDR1 = 0x000000000
|
|
||||||
val INST_ACCESS_ADDR2 = 0x000000000
|
|
||||||
val INST_ACCESS_ADDR3 = 0x000000000
|
|
||||||
val INST_ACCESS_ADDR4 = 0x000000000
|
|
||||||
val INST_ACCESS_ADDR5 = 0x000000000
|
|
||||||
val INST_ACCESS_ADDR6 = 0x000000000
|
|
||||||
val INST_ACCESS_ADDR7 = 0x000000000
|
|
||||||
val INST_ACCESS_ENABLE0 = 0x00
|
|
||||||
val INST_ACCESS_ENABLE1 = 0x00
|
|
||||||
val INST_ACCESS_ENABLE2 = 0x00
|
|
||||||
val INST_ACCESS_ENABLE3 = 0x00
|
|
||||||
val INST_ACCESS_ENABLE4 = 0x00
|
|
||||||
val INST_ACCESS_ENABLE5 = 0x00
|
|
||||||
val INST_ACCESS_ENABLE6 = 0x00
|
|
||||||
val INST_ACCESS_ENABLE7 = 0x00
|
|
||||||
val INST_ACCESS_MASK0 = 0x0FFFFFFFF
|
|
||||||
val INST_ACCESS_MASK1 = 0x0FFFFFFFF
|
|
||||||
val INST_ACCESS_MASK2 = 0x0FFFFFFFF
|
|
||||||
val INST_ACCESS_MASK3 = 0x0FFFFFFFF
|
|
||||||
val INST_ACCESS_MASK4 = 0x0FFFFFFFF
|
|
||||||
val INST_ACCESS_MASK5 = 0x0FFFFFFFF
|
|
||||||
val INST_ACCESS_MASK6 = 0x0FFFFFFFF
|
|
||||||
val INST_ACCESS_MASK7 = 0x0FFFFFFFF
|
|
||||||
val LOAD_TO_USE_PLUS1 = 0x00
|
|
||||||
val LSU2DMA = 0x00
|
|
||||||
val LSU_BUS_ID = 0x01
|
|
||||||
val LSU_BUS_PRTY = 0x02
|
|
||||||
val LSU_BUS_TAG = 0x03
|
|
||||||
val LSU_NUM_NBLOAD = 0x004
|
|
||||||
val LSU_NUM_NBLOAD_WIDTH = 0x02
|
|
||||||
val LSU_SB_BITS = 0x010
|
|
||||||
val LSU_STBUF_DEPTH = 0x04
|
|
||||||
val NO_ICCM_NO_ICACHE = 0x00
|
|
||||||
val PIC_2CYCLE = 0x00
|
|
||||||
val PIC_BASE_ADDR = 0x0F00C0000
|
|
||||||
val PIC_BITS = 0x00F
|
|
||||||
val PIC_INT_WORDS = 0x01
|
|
||||||
val PIC_REGION = 0x0F
|
|
||||||
val PIC_SIZE = 0x0020
|
|
||||||
val PIC_TOTAL_INT = 0x01F
|
|
||||||
val PIC_TOTAL_INT_PLUS1 = 0x0020
|
|
||||||
val RET_STACK_SIZE = 0x08
|
|
||||||
val RV_FPGA_OPTIMIZE = 0x01
|
|
||||||
val SB_BUS_ID = 0x01
|
|
||||||
val SB_BUS_PRTY = 0x02
|
|
||||||
val SB_BUS_TAG = 0x01
|
|
||||||
val TIMER_LEGAL_EN = 0x01
|
|
||||||
}
|
|
Binary file not shown.
File diff suppressed because one or more lines are too long
|
@ -26,5 +26,6 @@
|
||||||
[0m[[0m[0mdebug[0m] [0m[0m (/home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/parameter.sv,/home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/parameter.sv)[0m
|
[0m[[0m[0mdebug[0m] [0m[0m (/home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/parameter.sv,/home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/parameter.sv)[0m
|
||||||
[0m[[0m[0mdebug[0m] [0m[0m (/home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/uart_tfifo.v,/home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/uart_tfifo.v)[0m
|
[0m[[0m[0mdebug[0m] [0m[0m (/home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/uart_tfifo.v,/home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/uart_tfifo.v)[0m
|
||||||
[0m[[0m[0mdebug[0m] [0m[0m (/home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/uart_top.v,/home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/uart_top.v)[0m
|
[0m[[0m[0mdebug[0m] [0m[0m (/home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/uart_top.v,/home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/uart_top.v)[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m (/home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/QUASAR_wrapper_full_user_matches.txt,/home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/QUASAR_wrapper_full_user_matches.txt)[0m
|
||||||
[0m[[0m[0mdebug[0m] [0m[0m (/home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/swervolf_syscon.v,/home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/swervolf_syscon.v)[0m
|
[0m[[0m[0mdebug[0m] [0m[0m (/home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/swervolf_syscon.v,/home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/swervolf_syscon.v)[0m
|
||||||
[0m[[0m[0mdebug[0m] [0m[0m (/home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/beh_lib.sv,/home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/beh_lib.sv)[0m
|
[0m[[0m[0mdebug[0m] [0m[0m (/home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/beh_lib.sv,/home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/beh_lib.sv)[0m
|
||||||
|
|
|
@ -1 +1 @@
|
||||||
-23094802
|
1756707553
|
|
@ -1 +1,645 @@
|
||||||
[0m[[0m[0mdebug[0m] [0m[0mJar uptodate: /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/quasar_2.12-3.3.0.jar[0m
|
[0m[[0m[0mdebug[0m] [0m[0mPackaging /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/quasar_2.12-3.3.0.jar ...[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0mInput file mappings:[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m QUASAR.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/QUASAR.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m quasar_wrapper.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/quasar_wrapper.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dma_ctrl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dma_ctrl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_cls.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu_div_cls.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_main$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu_main$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/mul$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/mul$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_mul_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu_mul_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/mul$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/mul$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_existing_1bit_cheapshortq$$anon$2.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu_div_existing_1bit_cheapshortq$$anon$2.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_existing_1bit_cheapshortq.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu_div_existing_1bit_cheapshortq.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/div_main$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/div_main$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_new_2bit_fullshortq$$anon$4.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu_div_new_2bit_fullshortq$$anon$4.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_alu_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu_alu_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_mul_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu_mul_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_main$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu_main$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_alu_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu_alu_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_new_4bit_fullshortq$$anon$6.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu_div_new_4bit_fullshortq$$anon$6.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/mul.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/mul.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/div_main$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/div_main$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_new_4bit_fullshortq.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu_div_new_4bit_fullshortq.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_new_3bit_fullshortq.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu_div_new_3bit_fullshortq.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_new_1bit_fullshortq.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu_div_new_1bit_fullshortq.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_new_2bit_fullshortq.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu_div_new_2bit_fullshortq.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_new_1bit_fullshortq$$anon$3.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu_div_new_1bit_fullshortq$$anon$3.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_main.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu_main.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu_div_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu_div_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_cls$$anon$7.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu_div_cls$$anon$7.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/exu_div_new_3bit_fullshortq$$anon$5.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/exu_div_new_3bit_fullshortq$$anon$5.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m exu/div_main.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/exu/div_main.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m DMA.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/DMA.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/perf_mux_and_flops.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/perf_mux_and_flops.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/perf_csr$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/perf_csr$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_dec_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_dec_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/int_exc.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/int_exc.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_dec_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_dec_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/tlu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/tlu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_dec.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_dec.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/tlu$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/tlu$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/CSRs.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/CSRs.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_gpr_ctl_IO.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_gpr_ctl_IO.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_trigger$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_trigger$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_tlu_ctl_IO.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_tlu_ctl_IO.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/CSR_IO.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/CSR_IO.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_IO.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_IO.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_ib_ctl_IO.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_ib_ctl_IO.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_decode_csr_read_IO.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_decode_csr_read_IO.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_dec$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_dec$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_tlu_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_tlu_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/tlu$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/tlu$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/int_exc$$anon$3.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/int_exc$$anon$3.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_trigger.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_trigger.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_timer_ctl_IO.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_timer_ctl_IO.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_gpr_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_gpr_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_ib_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_ib_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/csr_tlu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/csr_tlu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_decode_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_decode_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/perf_mux_and_flops$$anon$2.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/perf_mux_and_flops$$anon$2.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_dec$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_dec$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/CSR_VAL.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/CSR_VAL.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_main$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_main$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_decode_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_main$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_main$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/perf_csr.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/perf_csr.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_timer_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_timer_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_decode_csr_read.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_decode_csr_read.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dec/dec_main.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dec/dec_main.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m pic$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/pic$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m QUASAR_Wrp$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/QUASAR_Wrp$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m wrapper$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/wrapper$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m mem[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/mem[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m mem/Mem_bundle.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/mem/Mem_bundle.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m mem/quasar.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/mem/quasar.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m mem/mem_lsu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/mem/mem_lsu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m mem/quasar$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/mem/quasar$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m mem/quasar$mem.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/mem/quasar$mem.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m mem/blackbox_mem.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/mem/blackbox_mem.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m pic.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/pic.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m QUASAR$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/QUASAR$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/axi4_to_ahb$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/axi4_to_ahb$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$gated_latch.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$gated_latch.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvecc_encode_64.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$rvecc_encode_64.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvdffiee$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$rvdffiee$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/axi4_to_ahb.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/axi4_to_ahb.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$gated_latch$$anon$4.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$gated_latch$$anon$4.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvdffsc_fpga$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$rvdffsc_fpga$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/ahb_to_axi4$$anon$1$$anon$2.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/ahb_to_axi4$$anon$1$$anon$2.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/axi4_to_ahb_IO.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/axi4_to_ahb_IO.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvdfflie$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$rvdfflie$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/ahb_to_axi4.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/ahb_to_axi4.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvecc_encode.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$rvecc_encode.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvsyncss$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$rvsyncss$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvclkhdr$$anon$5.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$rvclkhdr$$anon$5.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvdffs_fpga$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$rvdffs_fpga$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/axi4_to_ahb$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/axi4_to_ahb$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvecc_encode$$anon$2.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$rvecc_encode$$anon$2.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvdffpcie$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$rvdffpcie$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvsyncss_fpga$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$rvsyncss_fpga$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvclkhdr$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$rvclkhdr$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/param.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/param.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvoclkhdr$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$rvoclkhdr$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvecc_encode_64$$anon$3.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$rvecc_encode_64$$anon$3.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/ahb_to_axi4$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/ahb_to_axi4$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvclkhdr.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$rvclkhdr.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvdff_fpga$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$rvdff_fpga$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvdffppe$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$rvdffppe$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvdffie$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$rvdffie$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib$rvdffe$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib$rvdffe$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lib/lib.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lib/lib.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/mul_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/mul_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dma_mem_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dma_mem_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dec_div.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dec_div.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/lsu_error_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/lsu_error_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dma_ifc.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dma_ifc.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/iccm_mem.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/iccm_mem.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/ifu_dec.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/ifu_dec.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/inst_pkt_t$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/inst_pkt_t$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/lsu_dec.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/lsu_dec.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/write_resp.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/write_resp.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/lsu_tlu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/lsu_tlu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/read_addr$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/read_addr$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/lsu_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/lsu_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/ib_exu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/ib_exu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/reg_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/reg_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dma_lsc_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dma_lsc_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/ccm_ext_in_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/ccm_ext_in_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dec_ifc.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dec_ifc.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/aln_ib.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/aln_ib.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/axi_channels$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/axi_channels$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dctl_dma.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dctl_dma.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/lsu_pic.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/lsu_pic.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/ahb_out.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/ahb_out.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/gpr_exu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/gpr_exu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/ahb_channel.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/ahb_channel.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dec_alu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dec_alu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/trigger_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/trigger_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dec_tlu_csr_pkt.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dec_tlu_csr_pkt.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/div_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/div_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dec_exu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dec_exu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/exu_bp.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/exu_bp.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dbg_ib.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dbg_ib.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/ifu_dma.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/ifu_dma.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/read_addr.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/read_addr.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/axi_channels.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/axi_channels.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dma_dccm_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dma_dccm_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/lsu_exu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/lsu_exu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dbg_dma.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dbg_dma.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/alu_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/alu_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/write_addr$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/write_addr$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/rets_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/rets_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/tlu_exu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/tlu_exu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/write_addr.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/write_addr.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/trap_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/trap_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dec_aln.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dec_aln.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dbg_dctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dbg_dctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/exu_ifu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/exu_ifu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/ahb_out_dma.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/ahb_out_dma.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/load_cam_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/load_cam_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/read_data$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/read_data$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dctl_busbuff.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dctl_busbuff.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/ic_data_ext_in_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/ic_data_ext_in_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dec_mem_ctrl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dec_mem_ctrl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dec_dbg.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dec_dbg.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/lsu_dma.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/lsu_dma.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/write_data.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/write_data.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/br_tlu_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/br_tlu_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/predict_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/predict_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/aln_dec.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/aln_dec.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/cache_debug_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/cache_debug_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/tlu_dma.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/tlu_dma.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/tlu_busbuff.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/tlu_busbuff.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/ic_mem.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/ic_mem.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/read_data.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/read_data.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dec_dma.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dec_dma.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/ext_in_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/ext_in_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/ic_tag_ext_in_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/ic_tag_ext_in_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/decode_exu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/decode_exu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dccm_ext_in_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dccm_ext_in_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/ahb_in.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/ahb_in.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dec_bp.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dec_bp.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dec_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dec_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/class_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/class_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/br_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/br_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/trace_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/trace_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dec_pic.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dec_pic.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/dest_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/dest_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m include/inst_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/include/inst_pkt_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m quasar.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/quasar.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m wrapper$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/wrapper$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m pic_ctrl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/pic_ctrl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/dpram64.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/dpram64.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/wb_mem_wrapper.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/wb_mem_wrapper.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/uart_sync_flops.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/uart_sync_flops.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/uart_wb.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/uart_wb.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/mem_lib.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/mem_lib.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/uart_transmitter.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/uart_transmitter.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/fifo4.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/fifo4.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/raminfr.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/raminfr.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/pkt1.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/pkt1.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/dmi_wrapper.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/dmi_wrapper.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/uart_regs.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/uart_regs.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/uart_receiver.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/uart_receiver.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/uart_defines.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/uart_defines.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/uart_rfifo.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/uart_rfifo.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/lsu_dccm_mem.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/mem.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/mem.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/axi2wb.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/axi2wb.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/ifu_iccm_mem.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/dmi_jtag_to_core_sync.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/gated_latch.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/gated_latch.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/ifu_ic_mem.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/simple_spi_top.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/simple_spi_top.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/mem_mod.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/mem_mod.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/rvjtag_tap.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/rvjtag_tap.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/parameter.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/parameter.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/uart_tfifo.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/uart_tfifo.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/uart_top.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/uart_top.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/QUASAR_wrapper_full_user_matches.txt[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/QUASAR_wrapper_full_user_matches.txt[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/swervolf_syscon.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/swervolf_syscon.v[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m vsrc/beh_lib.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/vsrc/beh_lib.sv[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dbg[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dbg[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dbg/dbg.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dbg/dbg.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dbg/dbg$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dbg/dbg$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dbg/state_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dbg/state_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dbg/dbg_dma.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dbg/dbg_dma.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dbg/sb_state_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dbg/sb_state_t.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dbg/debug.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dbg/debug.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dbg/state_t$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dbg/state_t$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dbg/debug$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dbg/debug$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dbg/sb_state_t$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dbg/sb_state_t$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dbg/debug$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dbg/debug$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m QUASAR_Wrp.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/QUASAR_Wrp.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m QUASAR$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/QUASAR$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_main$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu_main$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/buffer$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/buffer$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/bus_intf$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/bus_intf$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/clkdomain$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/clkdomain$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/stbuf.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/stbuf.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_trigger$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu_trigger$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_addrcheck.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu_addrcheck.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_main$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu_main$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/bus_intf.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/bus_intf.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/stbuf$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/stbuf$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_bus_buffer$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu_bus_buffer$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_lsc_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu_lsc_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_bus_intf$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu_bus_intf$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_ecc$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu_ecc$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/clkdomain$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/clkdomain$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/buffer.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/buffer.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/dccm_ctl$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/dccm_ctl$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/dccm_ctl$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/dccm_ctl$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_ecc.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu_ecc.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsc_ctl$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsc_ctl$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/dccm_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/dccm_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_lsc_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu_lsc_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_dccm_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu_dccm_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_bus_intf.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu_bus_intf.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/bus_intf$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/bus_intf$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsc_ctl$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsc_ctl$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/buffer$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/buffer$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_stbuf$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu_stbuf$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsc_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsc_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_trigger.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu_trigger.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_main.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu_main.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_bus_buffer.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu_bus_buffer.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_addrcheck$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu_addrcheck$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_clkdomain.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu_clkdomain.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_dccm_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu_dccm_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_clkdomain$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu_clkdomain$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/clkdomain.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/clkdomain.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/lsu_stbuf.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/lsu_stbuf.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m lsu/stbuf$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/lsu/stbuf$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m quasar_soc.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/quasar_soc.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m ifu[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/ifu[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_top$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/ifu/ifu_top$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/ifu/ifu$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_mem_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/ifu/ifu_mem_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_top$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/ifu/ifu_top$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_ifc_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/ifu/ifu_ifc_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_aln_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/ifu/ifu_aln_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_top.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/ifu/ifu_top.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_aln_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/ifu/ifu_aln_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_compress_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/ifu/ifu_compress_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_compress_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/ifu/ifu_compress_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/ifu/ifu.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_ifc_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/ifu/ifu_ifc_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_bp_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/ifu/ifu_bp_ctl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m ifu/ifu_bp_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/ifu/ifu_bp_ctl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m ifu/mem_ctl_io.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/ifu/mem_ctl_io.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dma_ctrl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dma_ctrl.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m pic_ctrl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/pic_ctrl$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m DMA$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/DMA$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m wrapper.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/wrapper.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m pic$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/pic$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m soc$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/soc$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m .vscode[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/.vscode[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m .vscode/settings.json[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/.vscode/settings.json[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m quasar_bundle$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/quasar_bundle$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m quasar_wrapper$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/quasar_wrapper$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m quasar_bundle.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/quasar_bundle.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m DMA$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/DMA$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m soc.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/soc.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m QUASAR_Wrp$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/QUASAR_Wrp$.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m soc$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/soc$delayedInit$body.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dmi[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dmi[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dmi/dmi_wrapper_module.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dmi/dmi_wrapper_module.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dmi/dmi_wrapper.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dmi/dmi_wrapper.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dmi/dmi_wrapper$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dmi/dmi_wrapper$$anon$1.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m dmi/dmi_wrapper_module$$anon$2.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0m /home/users/laraib.khan/Videos/Quasar/design/target/scala-2.12/classes/dmi/dmi_wrapper_module$$anon$2.class[0m
|
||||||
|
[0m[[0m[0mdebug[0m] [0m[0mDone packaging.[0m
|
||||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -19,12 +19,10 @@ module tb_top ( input bit core_clk );
|
||||||
module tb_top;
|
module tb_top;
|
||||||
bit core_clk;
|
bit core_clk;
|
||||||
`endif
|
`endif
|
||||||
/*
|
|
||||||
initial begin
|
initial begin
|
||||||
$fsdbDumpfile("testing.fsdb");
|
$dumpfile("test.vcd");
|
||||||
$fsdbDumpvars();
|
$dumpvars;
|
||||||
$fsdbDumpon();
|
end
|
||||||
end*/
|
|
||||||
logic rst_l;
|
logic rst_l;
|
||||||
logic porst_l;
|
logic porst_l;
|
||||||
logic nmi_int;
|
logic nmi_int;
|
||||||
|
|
|
@ -1,3 +0,0 @@
|
||||||
----------------------------------
|
|
||||||
Hello World from Quasar @LM !!
|
|
||||||
----------------------------------
|
|
|
@ -1,117 +0,0 @@
|
||||||
# Makefile generated by VCS to build your model
|
|
||||||
# This file may be modified; VCS will not overwrite it unless -Mupdate is used
|
|
||||||
|
|
||||||
# define default verilog source directory
|
|
||||||
VSRC=..
|
|
||||||
|
|
||||||
# Override TARGET_ARCH
|
|
||||||
TARGET_ARCH=
|
|
||||||
|
|
||||||
# Choose name of executable
|
|
||||||
PRODUCTBASE=$(VSRC)/simv
|
|
||||||
|
|
||||||
PRODUCT=$(PRODUCTBASE)
|
|
||||||
|
|
||||||
# Product timestamp file. If product is newer than this one,
|
|
||||||
# we will also re-link the product.
|
|
||||||
PRODUCT_TIMESTAMP=product_timestamp
|
|
||||||
|
|
||||||
# Path to runtime library
|
|
||||||
DEPLIBS=
|
|
||||||
VCSUCLI=-lvcsucli
|
|
||||||
RUNTIME=-lvcsnew -lsimprofile -luclinative /eda_tools/vcs201809/linux64/lib/vcs_tls.o $(DEPLIBS)
|
|
||||||
|
|
||||||
VCS_SAVE_RESTORE_OBJ=/eda_tools/vcs201809/linux64/lib/vcs_save_restore_new.o
|
|
||||||
|
|
||||||
# Select your favorite compiler
|
|
||||||
|
|
||||||
# Linux:
|
|
||||||
VCS_CC=gcc
|
|
||||||
|
|
||||||
# Internal CC for gen_c flow:
|
|
||||||
CC_CG=gcc
|
|
||||||
# User overrode default CC:
|
|
||||||
VCS_CC=gcc
|
|
||||||
# Loader
|
|
||||||
LD=g++
|
|
||||||
|
|
||||||
# Strip Flags for target product
|
|
||||||
STRIPFLAGS=
|
|
||||||
|
|
||||||
PRE_LDFLAGS= -no-pie
|
|
||||||
# Loader Flags
|
|
||||||
LDFLAGS= -Wl,--no-as-needed -rdynamic -Wl,-rpath=/eda_tools/vcs201809/linux64/lib -L/eda_tools/vcs201809/linux64/lib
|
|
||||||
# Picarchive Flags
|
|
||||||
PICLDFLAGS=-Wl,-rpath-link=./ -Wl,-rpath='$$ORIGIN'/simv.daidir/ -Wl,-rpath=./simv.daidir/ -Wl,-rpath='$$ORIGIN'/simv.daidir//scsim.db.dir
|
|
||||||
|
|
||||||
# C run time startup
|
|
||||||
CRT0=
|
|
||||||
# C run time startup
|
|
||||||
CRTN=
|
|
||||||
# Machine specific libraries
|
|
||||||
SYSLIBS=/eda_tools/verdi201809/share/PLI/VCS/LINUX64/pli.a -ldl -lc -lm -lpthread -ldl
|
|
||||||
|
|
||||||
# Default defines
|
|
||||||
SHELL=/bin/sh
|
|
||||||
|
|
||||||
VCSTMPSPECARG=
|
|
||||||
VCSTMPSPECENV=
|
|
||||||
# NOTE: if you have little space in $TMPDIR, but plenty in /foo,
|
|
||||||
#and you are using gcc, uncomment the next line
|
|
||||||
#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo
|
|
||||||
|
|
||||||
TMPSPECARG=$(VCSTMPSPECARG)
|
|
||||||
TMPSPECENV=$(VCSTMPSPECENV)
|
|
||||||
CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG)
|
|
||||||
|
|
||||||
# C flags for compilation
|
|
||||||
CFLAGS=-w -pipe -fPIC -O -I/eda_tools/vcs201809/include
|
|
||||||
|
|
||||||
CFLAGS_O0=-w -pipe -fPIC -I/eda_tools/vcs201809/include -O0 -fno-strict-aliasing
|
|
||||||
|
|
||||||
CFLAGS_CG=-w -pipe -fPIC -I/eda_tools/vcs201809/include -O -fno-strict-aliasing
|
|
||||||
|
|
||||||
LD_PARTIAL_LOADER=ld
|
|
||||||
# Partial linking
|
|
||||||
LD_PARTIAL=$(LD_PARTIAL_LOADER) -r -o
|
|
||||||
ASFLAGS=
|
|
||||||
LIBS=-lzerosoft_rt_stubs -lvirsim -lerrorinf -lsnpsmalloc -lvfs
|
|
||||||
# Note: if make gives you errors about include, either get gmake, or
|
|
||||||
# replace the following line with the contents of the file filelist,
|
|
||||||
# EACH TIME IT CHANGES
|
|
||||||
# included file defines OBJS, and is automatically generated by vcs
|
|
||||||
include filelist
|
|
||||||
|
|
||||||
OBJS=$(VLOG_OBJS) $(SYSC_OBJS) $(VHDL_OBJS)
|
|
||||||
|
|
||||||
product : $(PRODUCT_TIMESTAMP)
|
|
||||||
@echo $(PRODUCT) up to date
|
|
||||||
|
|
||||||
objects : $(OBJS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS)
|
|
||||||
|
|
||||||
clean :
|
|
||||||
rm -f $(VCS_OBJS) $(CU_OBJS)
|
|
||||||
|
|
||||||
clobber : clean
|
|
||||||
rm -f $(PRODUCT) $(PRODUCT_TIMESTAMP)
|
|
||||||
|
|
||||||
picclean :
|
|
||||||
rm -f _csrc*.so pre_vcsobj_*.so share_vcsobj_*.so
|
|
||||||
@rm -f $(PRODUCT).daidir/_[0-9]*_archive_*.so 2>/dev/null
|
|
||||||
|
|
||||||
product_clean_order :
|
|
||||||
@$(MAKE) -f Makefile --no-print-directory picclean
|
|
||||||
@$(MAKE) -f Makefile --no-print-directory product_order
|
|
||||||
|
|
||||||
product_order : $(PRODUCT)
|
|
||||||
|
|
||||||
$(PRODUCT_TIMESTAMP) : product_clean_order
|
|
||||||
-if [ -x $(PRODUCT) ]; then chmod -x $(PRODUCT); fi
|
|
||||||
$(LD) $(CRT0) -o $(PRODUCT) $(PRE_LDFLAGS) $(STRIPFLAGS) $(PCLDFLAGS) $(PICLDFLAGS) $(LDFLAGS) $(OBJS) $(LIBS) $(RUNTIME) -Wl,-whole-archive $(VCSUCLI) -Wl,-no-whole-archive $(LINK_TB) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(VCS_SAVE_RESTORE_OBJ) $(SYSLIBS) $(CRTN)
|
|
||||||
@rm -f csrc[0-9]*.o
|
|
||||||
@touch $(PRODUCT_TIMESTAMP)
|
|
||||||
@-if [ -d ./objs ]; then find ./objs -type d -empty -delete; fi
|
|
||||||
|
|
||||||
$(PRODUCT) : $(LD_VERSION_CHECK) $(OBJS) $(DOTLIBS) $(DPI_STUB_OBJS) $(PLI_STUB_OBJS) $(CMODLIB) /eda_tools/vcs201809/linux64/lib/libvcsnew.so /eda_tools/vcs201809/linux64/lib/libsimprofile.so /eda_tools/vcs201809/linux64/lib/libuclinative.so /eda_tools/vcs201809/linux64/lib/vcs_tls.o /eda_tools/vcs201809/linux64/lib/libvcsucli.so $(VCS_SAVE_RESTORE_OBJ)
|
|
||||||
@touch $(PRODUCT)
|
|
||||||
|
|
|
@ -1,47 +0,0 @@
|
||||||
# Makefile generated by VCS to build rmapats.so for your model
|
|
||||||
VSRC=..
|
|
||||||
|
|
||||||
# Override TARGET_ARCH
|
|
||||||
TARGET_ARCH=
|
|
||||||
|
|
||||||
# Select your favorite compiler
|
|
||||||
|
|
||||||
# Linux:
|
|
||||||
VCS_CC=gcc
|
|
||||||
|
|
||||||
# Internal CC for gen_c flow:
|
|
||||||
CC_CG=gcc
|
|
||||||
|
|
||||||
# User overrode default CC:
|
|
||||||
VCS_CC=gcc
|
|
||||||
# Loader
|
|
||||||
LD=g++
|
|
||||||
# Loader Flags
|
|
||||||
LDFLAGS=
|
|
||||||
|
|
||||||
# Default defines
|
|
||||||
SHELL=/bin/sh
|
|
||||||
|
|
||||||
VCSTMPSPECARG=
|
|
||||||
VCSTMPSPECENV=
|
|
||||||
# NOTE: if you have little space in $TMPDIR, but plenty in /foo,
|
|
||||||
#and you are using gcc, uncomment the next line
|
|
||||||
#VCSTMPSPECENV=SNPS_VCS_TMPDIR=/foo
|
|
||||||
|
|
||||||
TMPSPECARG=$(VCSTMPSPECARG)
|
|
||||||
TMPSPECENV=$(VCSTMPSPECENV)
|
|
||||||
CC=$(TMPSPECENV) $(VCS_CC) $(TMPSPECARG)
|
|
||||||
|
|
||||||
# C flags for compilation
|
|
||||||
CFLAGS=-w -pipe -fPIC -O -I/eda_tools/vcs201809/include
|
|
||||||
|
|
||||||
CFLAGS_CG=-w -pipe -fPIC -I/eda_tools/vcs201809/include -O -fno-strict-aliasing
|
|
||||||
|
|
||||||
ASFLAGS=
|
|
||||||
LIBS=
|
|
||||||
|
|
||||||
include filelist.hsopt
|
|
||||||
|
|
||||||
|
|
||||||
rmapats.so: $(HSOPT_OBJS)
|
|
||||||
@$(VCS_CC) $(LDFLAGS) $(LIBS) -shared -o ./../simv.daidir/rmapats.so $(HSOPT_OBJS)
|
|
Binary file not shown.
|
@ -1 +0,0 @@
|
||||||
.//../simv.daidir//_14180_archive_1.so
|
|
|
@ -1,964 +0,0 @@
|
||||||
#ifndef _GNU_SOURCE
|
|
||||||
#define _GNU_SOURCE
|
|
||||||
#endif
|
|
||||||
#include <stdio.h>
|
|
||||||
#include <dlfcn.h>
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
extern void* VCS_dlsymLookup(const char *);
|
|
||||||
extern void vcsMsgReportNoSource1(const char *, const char*);
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbDumpvars:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvars
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpvars
|
|
||||||
extern void novas_call_fsdbDumpvars(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbDumpvars
|
|
||||||
void novas_call_fsdbDumpvars(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvars");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvars");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvars");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvars)(int data, int reason) = novas_call_fsdbDumpvars;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvars */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbDumpvars:misc */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_misc
|
|
||||||
#define __VCS_PLI_STUB_novas_misc
|
|
||||||
extern void novas_misc(int data, int reason, int iparam );
|
|
||||||
#pragma weak novas_misc
|
|
||||||
void novas_misc(int data, int reason, int iparam )
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason, int iparam ) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) dlsym(RTLD_NEXT, "novas_misc");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason, int iparam )) VCS_dlsymLookup("novas_misc");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason, iparam );
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_misc)(int data, int reason, int iparam ) = novas_misc;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_misc */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbDumpvarsByFile:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile
|
|
||||||
extern void novas_call_fsdbDumpvarsByFile(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbDumpvarsByFile
|
|
||||||
void novas_call_fsdbDumpvarsByFile(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpvarsByFile");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpvarsByFile");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpvarsByFile");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpvarsByFile)(int data, int reason) = novas_call_fsdbDumpvarsByFile;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpvarsByFile */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbAddRuntimeSignal:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal
|
|
||||||
extern void novas_call_fsdbAddRuntimeSignal(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbAddRuntimeSignal
|
|
||||||
void novas_call_fsdbAddRuntimeSignal(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbAddRuntimeSignal");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbAddRuntimeSignal");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbAddRuntimeSignal");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbAddRuntimeSignal)(int data, int reason) = novas_call_fsdbAddRuntimeSignal;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbAddRuntimeSignal */
|
|
||||||
|
|
||||||
/* PLI routine: $sps_create_transaction_stream:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_sps_create_transaction_stream
|
|
||||||
#define __VCS_PLI_STUB_novas_call_sps_create_transaction_stream
|
|
||||||
extern void novas_call_sps_create_transaction_stream(int data, int reason);
|
|
||||||
#pragma weak novas_call_sps_create_transaction_stream
|
|
||||||
void novas_call_sps_create_transaction_stream(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_create_transaction_stream");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_create_transaction_stream");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_create_transaction_stream");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_sps_create_transaction_stream)(int data, int reason) = novas_call_sps_create_transaction_stream;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_sps_create_transaction_stream */
|
|
||||||
|
|
||||||
/* PLI routine: $sps_begin_transaction:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_sps_begin_transaction
|
|
||||||
#define __VCS_PLI_STUB_novas_call_sps_begin_transaction
|
|
||||||
extern void novas_call_sps_begin_transaction(int data, int reason);
|
|
||||||
#pragma weak novas_call_sps_begin_transaction
|
|
||||||
void novas_call_sps_begin_transaction(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_begin_transaction");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_begin_transaction");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_begin_transaction");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_sps_begin_transaction)(int data, int reason) = novas_call_sps_begin_transaction;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_sps_begin_transaction */
|
|
||||||
|
|
||||||
/* PLI routine: $sps_end_transaction:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_sps_end_transaction
|
|
||||||
#define __VCS_PLI_STUB_novas_call_sps_end_transaction
|
|
||||||
extern void novas_call_sps_end_transaction(int data, int reason);
|
|
||||||
#pragma weak novas_call_sps_end_transaction
|
|
||||||
void novas_call_sps_end_transaction(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_end_transaction");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_end_transaction");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_end_transaction");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_sps_end_transaction)(int data, int reason) = novas_call_sps_end_transaction;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_sps_end_transaction */
|
|
||||||
|
|
||||||
/* PLI routine: $sps_free_transaction:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_sps_free_transaction
|
|
||||||
#define __VCS_PLI_STUB_novas_call_sps_free_transaction
|
|
||||||
extern void novas_call_sps_free_transaction(int data, int reason);
|
|
||||||
#pragma weak novas_call_sps_free_transaction
|
|
||||||
void novas_call_sps_free_transaction(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_free_transaction");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_free_transaction");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_free_transaction");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_sps_free_transaction)(int data, int reason) = novas_call_sps_free_transaction;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_sps_free_transaction */
|
|
||||||
|
|
||||||
/* PLI routine: $sps_add_attribute:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_sps_add_attribute
|
|
||||||
#define __VCS_PLI_STUB_novas_call_sps_add_attribute
|
|
||||||
extern void novas_call_sps_add_attribute(int data, int reason);
|
|
||||||
#pragma weak novas_call_sps_add_attribute
|
|
||||||
void novas_call_sps_add_attribute(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_attribute");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_attribute");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_attribute");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_sps_add_attribute)(int data, int reason) = novas_call_sps_add_attribute;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_sps_add_attribute */
|
|
||||||
|
|
||||||
/* PLI routine: $sps_update_label:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_sps_update_label
|
|
||||||
#define __VCS_PLI_STUB_novas_call_sps_update_label
|
|
||||||
extern void novas_call_sps_update_label(int data, int reason);
|
|
||||||
#pragma weak novas_call_sps_update_label
|
|
||||||
void novas_call_sps_update_label(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_update_label");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_update_label");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_update_label");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_sps_update_label)(int data, int reason) = novas_call_sps_update_label;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_sps_update_label */
|
|
||||||
|
|
||||||
/* PLI routine: $sps_add_relation:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_sps_add_relation
|
|
||||||
#define __VCS_PLI_STUB_novas_call_sps_add_relation
|
|
||||||
extern void novas_call_sps_add_relation(int data, int reason);
|
|
||||||
#pragma weak novas_call_sps_add_relation
|
|
||||||
void novas_call_sps_add_relation(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_add_relation");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_add_relation");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_add_relation");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_sps_add_relation)(int data, int reason) = novas_call_sps_add_relation;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_sps_add_relation */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbWhatif:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbWhatif
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbWhatif
|
|
||||||
extern void novas_call_fsdbWhatif(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbWhatif
|
|
||||||
void novas_call_fsdbWhatif(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbWhatif");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbWhatif");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbWhatif");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbWhatif)(int data, int reason) = novas_call_fsdbWhatif;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbWhatif */
|
|
||||||
|
|
||||||
/* PLI routine: $paa_init:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_paa_init
|
|
||||||
#define __VCS_PLI_STUB_novas_call_paa_init
|
|
||||||
extern void novas_call_paa_init(int data, int reason);
|
|
||||||
#pragma weak novas_call_paa_init
|
|
||||||
void novas_call_paa_init(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_init");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_init");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_init");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_paa_init)(int data, int reason) = novas_call_paa_init;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_paa_init */
|
|
||||||
|
|
||||||
/* PLI routine: $paa_sync:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_paa_sync
|
|
||||||
#define __VCS_PLI_STUB_novas_call_paa_sync
|
|
||||||
extern void novas_call_paa_sync(int data, int reason);
|
|
||||||
#pragma weak novas_call_paa_sync
|
|
||||||
void novas_call_paa_sync(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_paa_sync");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_paa_sync");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_paa_sync");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_paa_sync)(int data, int reason) = novas_call_paa_sync;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_paa_sync */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbDumpClassMethod:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod
|
|
||||||
extern void novas_call_fsdbDumpClassMethod(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbDumpClassMethod
|
|
||||||
void novas_call_fsdbDumpClassMethod(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassMethod");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassMethod");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassMethod");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassMethod)(int data, int reason) = novas_call_fsdbDumpClassMethod;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassMethod */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbSuppressClassMethod:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod
|
|
||||||
extern void novas_call_fsdbSuppressClassMethod(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbSuppressClassMethod
|
|
||||||
void novas_call_fsdbSuppressClassMethod(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassMethod");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassMethod");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassMethod");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassMethod)(int data, int reason) = novas_call_fsdbSuppressClassMethod;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassMethod */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbSuppressClassProp:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp
|
|
||||||
extern void novas_call_fsdbSuppressClassProp(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbSuppressClassProp
|
|
||||||
void novas_call_fsdbSuppressClassProp(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbSuppressClassProp");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbSuppressClassProp");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbSuppressClassProp");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbSuppressClassProp)(int data, int reason) = novas_call_fsdbSuppressClassProp;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbSuppressClassProp */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbDumpMDAByFile:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile
|
|
||||||
extern void novas_call_fsdbDumpMDAByFile(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbDumpMDAByFile
|
|
||||||
void novas_call_fsdbDumpMDAByFile(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpMDAByFile");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpMDAByFile");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpMDAByFile");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpMDAByFile)(int data, int reason) = novas_call_fsdbDumpMDAByFile;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpMDAByFile */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbTrans_create_stream_begin:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin
|
|
||||||
extern void novas_call_fsdbEvent_create_stream_begin(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbEvent_create_stream_begin
|
|
||||||
void novas_call_fsdbEvent_create_stream_begin(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_begin");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_begin");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_begin");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_begin)(int data, int reason) = novas_call_fsdbEvent_create_stream_begin;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_begin */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbTrans_define_attribute:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute
|
|
||||||
extern void novas_call_fsdbEvent_add_stream_attribute(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbEvent_add_stream_attribute
|
|
||||||
void novas_call_fsdbEvent_add_stream_attribute(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_stream_attribute");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_stream_attribute");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_stream_attribute");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_stream_attribute)(int data, int reason) = novas_call_fsdbEvent_add_stream_attribute;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_stream_attribute */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbTrans_create_stream_end:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end
|
|
||||||
extern void novas_call_fsdbEvent_create_stream_end(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbEvent_create_stream_end
|
|
||||||
void novas_call_fsdbEvent_create_stream_end(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_create_stream_end");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_create_stream_end");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_create_stream_end");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_create_stream_end)(int data, int reason) = novas_call_fsdbEvent_create_stream_end;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_create_stream_end */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbTrans_begin:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_begin
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_begin
|
|
||||||
extern void novas_call_fsdbEvent_begin(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbEvent_begin
|
|
||||||
void novas_call_fsdbEvent_begin(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_begin");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_begin");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_begin");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_begin)(int data, int reason) = novas_call_fsdbEvent_begin;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_begin */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbTrans_set_label:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_set_label
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_set_label
|
|
||||||
extern void novas_call_fsdbEvent_set_label(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbEvent_set_label
|
|
||||||
void novas_call_fsdbEvent_set_label(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_set_label");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_set_label");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_set_label");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_set_label)(int data, int reason) = novas_call_fsdbEvent_set_label;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_set_label */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbTrans_add_attribute:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute
|
|
||||||
extern void novas_call_fsdbEvent_add_attribute(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbEvent_add_attribute
|
|
||||||
void novas_call_fsdbEvent_add_attribute(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_attribute");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_attribute");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_attribute");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_attribute)(int data, int reason) = novas_call_fsdbEvent_add_attribute;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_attribute */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbTrans_add_tag:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag
|
|
||||||
extern void novas_call_fsdbEvent_add_tag(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbEvent_add_tag
|
|
||||||
void novas_call_fsdbEvent_add_tag(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_tag");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_tag");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_tag");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_tag)(int data, int reason) = novas_call_fsdbEvent_add_tag;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_tag */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbTrans_end:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_end
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_end
|
|
||||||
extern void novas_call_fsdbEvent_end(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbEvent_end
|
|
||||||
void novas_call_fsdbEvent_end(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_end");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_end");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_end");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_end)(int data, int reason) = novas_call_fsdbEvent_end;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_end */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbTrans_add_relation:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation
|
|
||||||
extern void novas_call_fsdbEvent_add_relation(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbEvent_add_relation
|
|
||||||
void novas_call_fsdbEvent_add_relation(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_add_relation");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_add_relation");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_add_relation");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_add_relation)(int data, int reason) = novas_call_fsdbEvent_add_relation;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_add_relation */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbTrans_get_error_code:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code
|
|
||||||
extern void novas_call_fsdbEvent_get_error_code(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbEvent_get_error_code
|
|
||||||
void novas_call_fsdbEvent_get_error_code(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbEvent_get_error_code");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbEvent_get_error_code");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbEvent_get_error_code");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbEvent_get_error_code)(int data, int reason) = novas_call_fsdbEvent_get_error_code;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbEvent_get_error_code */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbTrans_add_stream_attribute:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute
|
|
||||||
extern void novas_call_fsdbTrans_add_stream_attribute(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbTrans_add_stream_attribute
|
|
||||||
void novas_call_fsdbTrans_add_stream_attribute(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_stream_attribute");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_stream_attribute");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_stream_attribute");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_stream_attribute)(int data, int reason) = novas_call_fsdbTrans_add_stream_attribute;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_stream_attribute */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbTrans_add_scope_attribute:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute
|
|
||||||
extern void novas_call_fsdbTrans_add_scope_attribute(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbTrans_add_scope_attribute
|
|
||||||
void novas_call_fsdbTrans_add_scope_attribute(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbTrans_add_scope_attribute");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbTrans_add_scope_attribute");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbTrans_add_scope_attribute");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbTrans_add_scope_attribute)(int data, int reason) = novas_call_fsdbTrans_add_scope_attribute;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbTrans_add_scope_attribute */
|
|
||||||
|
|
||||||
/* PLI routine: $sps_interactive:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_sps_interactive
|
|
||||||
#define __VCS_PLI_STUB_novas_call_sps_interactive
|
|
||||||
extern void novas_call_sps_interactive(int data, int reason);
|
|
||||||
#pragma weak novas_call_sps_interactive
|
|
||||||
void novas_call_sps_interactive(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_interactive");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_interactive");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_interactive");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_sps_interactive)(int data, int reason) = novas_call_sps_interactive;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_sps_interactive */
|
|
||||||
|
|
||||||
/* PLI routine: $sps_test:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_sps_test
|
|
||||||
#define __VCS_PLI_STUB_novas_call_sps_test
|
|
||||||
extern void novas_call_sps_test(int data, int reason);
|
|
||||||
#pragma weak novas_call_sps_test
|
|
||||||
void novas_call_sps_test(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_test");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_test");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_test");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_sps_test)(int data, int reason) = novas_call_sps_test;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_sps_test */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbDumpClassObject:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObject
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObject
|
|
||||||
extern void novas_call_fsdbDumpClassObject(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbDumpClassObject
|
|
||||||
void novas_call_fsdbDumpClassObject(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObject");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObject");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObject");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObject)(int data, int reason) = novas_call_fsdbDumpClassObject;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObject */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbDumpClassObjectByFile:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile
|
|
||||||
extern void novas_call_fsdbDumpClassObjectByFile(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbDumpClassObjectByFile
|
|
||||||
void novas_call_fsdbDumpClassObjectByFile(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpClassObjectByFile");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpClassObjectByFile");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpClassObjectByFile");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpClassObjectByFile)(int data, int reason) = novas_call_fsdbDumpClassObjectByFile;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpClassObjectByFile */
|
|
||||||
|
|
||||||
/* PLI routine: $ridbDump:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_ridbDump
|
|
||||||
#define __VCS_PLI_STUB_novas_call_ridbDump
|
|
||||||
extern void novas_call_ridbDump(int data, int reason);
|
|
||||||
#pragma weak novas_call_ridbDump
|
|
||||||
void novas_call_ridbDump(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_ridbDump");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_ridbDump");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_ridbDump");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_ridbDump)(int data, int reason) = novas_call_ridbDump;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_ridbDump */
|
|
||||||
|
|
||||||
/* PLI routine: $sps_flush_file:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_sps_flush_file
|
|
||||||
#define __VCS_PLI_STUB_novas_call_sps_flush_file
|
|
||||||
extern void novas_call_sps_flush_file(int data, int reason);
|
|
||||||
#pragma weak novas_call_sps_flush_file
|
|
||||||
void novas_call_sps_flush_file(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_sps_flush_file");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_sps_flush_file");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_sps_flush_file");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_sps_flush_file)(int data, int reason) = novas_call_sps_flush_file;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_sps_flush_file */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbDumpSingle:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpSingle
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpSingle
|
|
||||||
extern void novas_call_fsdbDumpSingle(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbDumpSingle
|
|
||||||
void novas_call_fsdbDumpSingle(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpSingle");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpSingle");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpSingle");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpSingle)(int data, int reason) = novas_call_fsdbDumpSingle;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpSingle */
|
|
||||||
|
|
||||||
/* PLI routine: $fsdbDumpIO:call */
|
|
||||||
#ifndef __VCS_PLI_STUB_novas_call_fsdbDumpIO
|
|
||||||
#define __VCS_PLI_STUB_novas_call_fsdbDumpIO
|
|
||||||
extern void novas_call_fsdbDumpIO(int data, int reason);
|
|
||||||
#pragma weak novas_call_fsdbDumpIO
|
|
||||||
void novas_call_fsdbDumpIO(int data, int reason)
|
|
||||||
{
|
|
||||||
static int _vcs_pli_stub_initialized_ = 0;
|
|
||||||
static void (*_vcs_pli_fp_)(int data, int reason) = NULL;
|
|
||||||
if (!_vcs_pli_stub_initialized_) {
|
|
||||||
_vcs_pli_stub_initialized_ = 1;
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) dlsym(RTLD_NEXT, "novas_call_fsdbDumpIO");
|
|
||||||
if (_vcs_pli_fp_ == NULL) {
|
|
||||||
_vcs_pli_fp_ = (void (*)(int data, int reason)) VCS_dlsymLookup("novas_call_fsdbDumpIO");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
if (_vcs_pli_fp_) {
|
|
||||||
_vcs_pli_fp_(data, reason);
|
|
||||||
} else {
|
|
||||||
vcsMsgReportNoSource1("PLI-DIFNF", "novas_call_fsdbDumpIO");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
void (*__vcs_pli_dummy_reference_novas_call_fsdbDumpIO)(int data, int reason) = novas_call_fsdbDumpIO;
|
|
||||||
#endif /* __VCS_PLI_STUB_novas_call_fsdbDumpIO */
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
Binary file not shown.
Binary file not shown.
|
@ -1,44 +0,0 @@
|
||||||
bUdKt_d.o
|
|
||||||
reYIK_d.o
|
|
||||||
Lbw3w_d.o
|
|
||||||
tYz5w_d.o
|
|
||||||
Crn5e_d.o
|
|
||||||
kuPNM_d.o
|
|
||||||
pszgZ_d.o
|
|
||||||
aJziF_d.o
|
|
||||||
A1pVd_d.o
|
|
||||||
GHJ4k_d.o
|
|
||||||
uMx7H_d.o
|
|
||||||
xqE6L_d.o
|
|
||||||
nUefn_d.o
|
|
||||||
W0QmL_d.o
|
|
||||||
tLfqI_d.o
|
|
||||||
LUVCJ_d.o
|
|
||||||
hJmbb_d.o
|
|
||||||
G9wA0_d.o
|
|
||||||
pBTdY_d.o
|
|
||||||
Epw58_d.o
|
|
||||||
i46HG_d.o
|
|
||||||
LLg6t_d.o
|
|
||||||
jTTHC_d.o
|
|
||||||
EH8H4_d.o
|
|
||||||
tjY46_d.o
|
|
||||||
AWKgR_d.o
|
|
||||||
YV21G_d.o
|
|
||||||
rfBvB_d.o
|
|
||||||
rAdC7_d.o
|
|
||||||
bbpP3_d.o
|
|
||||||
xfmAy_d.o
|
|
||||||
JYwsi_d.o
|
|
||||||
jk4yL_d.o
|
|
||||||
xmuq2_d.o
|
|
||||||
uVamz_d.o
|
|
||||||
RjLew_d.o
|
|
||||||
jdPWL_d.o
|
|
||||||
KrGDi_d.o
|
|
||||||
jgE6r_d.o
|
|
||||||
M6knD_d.o
|
|
||||||
sbQpB_d.o
|
|
||||||
mBf4Q_d.o
|
|
||||||
MYfHG_d.o
|
|
||||||
amcQwB.o
|
|
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
@ -1,31 +0,0 @@
|
||||||
|
|
||||||
|
|
||||||
AR=ar
|
|
||||||
DOTLIBS=/eda_tools/vcs201809/linux64/lib/libzerosoft_rt_stubs.so /eda_tools/vcs201809/linux64/lib/libvirsim.so /eda_tools/vcs201809/linux64/lib/liberrorinf.so /eda_tools/vcs201809/linux64/lib/libsnpsmalloc.so /eda_tools/vcs201809/linux64/lib/libvfs.so
|
|
||||||
|
|
||||||
# This file is automatically generated by VCS. Any changes you make to it
|
|
||||||
# will be overwritten the next time VCS is run
|
|
||||||
VCS_LIBEXT=
|
|
||||||
XTRN_OBJS=
|
|
||||||
|
|
||||||
DPI_WRAPPER_OBJS =
|
|
||||||
DPI_STUB_OBJS =
|
|
||||||
# filelist.dpi will populate DPI_WRAPPER_OBJS and DPI_STUB_OBJS
|
|
||||||
include filelist.dpi
|
|
||||||
PLI_STUB_OBJS =
|
|
||||||
include filelist.pli
|
|
||||||
|
|
||||||
include filelist.hsopt
|
|
||||||
|
|
||||||
include filelist.cu
|
|
||||||
|
|
||||||
VCS_INCR_OBJS=
|
|
||||||
|
|
||||||
|
|
||||||
AUGDIR=
|
|
||||||
AUG_LDFLAGS=
|
|
||||||
SHARED_OBJ_SO=
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
VLOG_OBJS= $(VCS_OBJS) $(CU_OBJS) $(VCS_ARC0) $(XTRN_OBJS) $(DPI_WRAPPER_OBJS) $(VCS_INCR_OBJS) $(SHARED_OBJ_SO) $(HSOPT_OBJS)
|
|
|
@ -1,33 +0,0 @@
|
||||||
PIC_LD=ld
|
|
||||||
|
|
||||||
ARCHIVE_OBJS=
|
|
||||||
ARCHIVE_OBJS += _14180_archive_1.so
|
|
||||||
_14180_archive_1.so : archive.0/_14180_archive_1.a
|
|
||||||
@$(AR) -s $<
|
|
||||||
@$(PIC_LD) -shared -Bsymbolic -o .//../simv.daidir//_14180_archive_1.so --whole-archive $< --no-whole-archive
|
|
||||||
@rm -f $@
|
|
||||||
@ln -sf .//../simv.daidir//_14180_archive_1.so $@
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
O0_OBJS =
|
|
||||||
|
|
||||||
$(O0_OBJS) : %.o: %.c
|
|
||||||
$(CC_CG) $(CFLAGS_O0) -c -o $@ $<
|
|
||||||
|
|
||||||
|
|
||||||
%.o: %.c
|
|
||||||
$(CC_CG) $(CFLAGS_CG) -c -o $@ $<
|
|
||||||
CU_UDP_OBJS = \
|
|
||||||
|
|
||||||
|
|
||||||
CU_LVL_OBJS = \
|
|
||||||
SIM_l.o
|
|
||||||
|
|
||||||
MAIN_OBJS = \
|
|
||||||
objs/amcQw_d.o
|
|
||||||
|
|
||||||
CU_OBJS = $(MAIN_OBJS) $(ARCHIVE_OBJS) $(CU_UDP_OBJS) $(CU_LVL_OBJS)
|
|
||||||
|
|
|
@ -1,4 +0,0 @@
|
||||||
DPI_STUB_OBJS += ./../simv.daidir/vc_hdrs.o
|
|
||||||
./../simv.daidir/vc_hdrs.o: ./../simv.daidir/vc_hdrs.c
|
|
||||||
@$(CC) -I/eda_tools/vcs201809/include -pipe -fPIC -I/eda_tools/vcs201809/include -fPIC -c -o ./../simv.daidir/vc_hdrs.o ./../simv.daidir/vc_hdrs.c
|
|
||||||
@strip -g ./../simv.daidir/vc_hdrs.o
|
|
|
@ -1,13 +0,0 @@
|
||||||
rmapats_mop.o: rmapats.m
|
|
||||||
@/eda_tools/vcs201809/linux64/bin/cgmop1 -tls_initexe -pic -gen_obj rmapats.m rmapats_mop.o; rm -f rmapats.m; touch rmapats.m; touch rmapats_mop.o
|
|
||||||
|
|
||||||
rmapats.o: rmapats.c
|
|
||||||
@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmapats.o rmapats.c
|
|
||||||
rmapats%.o: rmapats%.c
|
|
||||||
@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $<
|
|
||||||
rmar.o: rmar.c
|
|
||||||
@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o rmar.o rmar.c
|
|
||||||
rmar%.o: rmar%.c
|
|
||||||
@$(CC_CG) $(CFLAGS_CG) -c -fPIC -x c -o $@ $<
|
|
||||||
|
|
||||||
include filelist.hsopt.objs
|
|
|
@ -1 +0,0 @@
|
||||||
LLVM_OBJS += rmar_llvm_0_1.o rmar_llvm_0_0.o
|
|
|
@ -1,7 +0,0 @@
|
||||||
HSOPT_OBJS +=rmapats_mop.o \
|
|
||||||
rmapats.o \
|
|
||||||
rmar.o rmar_nd.o
|
|
||||||
|
|
||||||
include filelist.hsopt.llvm2_0.objs
|
|
||||||
HSOPT_OBJS += $(LLVM_OBJS)
|
|
||||||
|
|
|
@ -1,4 +0,0 @@
|
||||||
PLI_STUB_OBJS += _vcs_pli_stub_.o
|
|
||||||
_vcs_pli_stub_.o: _vcs_pli_stub_.c
|
|
||||||
@$(CC) -I/eda_tools/vcs201809/include -pipe -fPIC -I/eda_tools/vcs201809/include -fPIC -c -o _vcs_pli_stub_.o _vcs_pli_stub_.c
|
|
||||||
@strip -g _vcs_pli_stub_.o
|
|
Binary file not shown.
|
@ -1,6 +0,0 @@
|
||||||
|
|
||||||
extern void* svapfGetAttempt(/* INPUT */unsigned int assertHandle);
|
|
||||||
|
|
||||||
extern void svapfReportResult(/* INPUT */unsigned int assertHandle, /* INPUT */void* ptrAttempt, /* INPUT */int result);
|
|
||||||
|
|
||||||
extern int svapfGetAssertEnabled(/* INPUT */unsigned int assertHandle);
|
|
Binary file not shown.
|
@ -1,43 +0,0 @@
|
||||||
// file = 0; split type = patterns; threshold = 100000; total count = 0.
|
|
||||||
#include <stdio.h>
|
|
||||||
#include <stdlib.h>
|
|
||||||
#include <strings.h>
|
|
||||||
#include "rmapats.h"
|
|
||||||
|
|
||||||
void hsG_0__0 (struct dummyq_struct * I1294, EBLK * I1288, U I685);
|
|
||||||
void hsG_0__0 (struct dummyq_struct * I1294, EBLK * I1288, U I685)
|
|
||||||
{
|
|
||||||
U I1552;
|
|
||||||
U I1553;
|
|
||||||
U I1554;
|
|
||||||
struct futq * I1555;
|
|
||||||
struct dummyq_struct * pQ = I1294;
|
|
||||||
I1552 = ((U )vcs_clocks) + I685;
|
|
||||||
I1554 = I1552 & ((1 << fHashTableSize) - 1);
|
|
||||||
I1288->I727 = (EBLK *)(-1);
|
|
||||||
I1288->I731 = I1552;
|
|
||||||
if (I1552 < (U )vcs_clocks) {
|
|
||||||
I1553 = ((U *)&vcs_clocks)[1];
|
|
||||||
sched_millenium(pQ, I1288, I1553 + 1, I1552);
|
|
||||||
}
|
|
||||||
else if ((peblkFutQ1Head != ((void *)0)) && (I685 == 1)) {
|
|
||||||
I1288->I733 = (struct eblk *)peblkFutQ1Tail;
|
|
||||||
peblkFutQ1Tail->I727 = I1288;
|
|
||||||
peblkFutQ1Tail = I1288;
|
|
||||||
}
|
|
||||||
else if ((I1555 = pQ->I1195[I1554].I745)) {
|
|
||||||
I1288->I733 = (struct eblk *)I1555->I744;
|
|
||||||
I1555->I744->I727 = (RP )I1288;
|
|
||||||
I1555->I744 = (RmaEblk *)I1288;
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
sched_hsopt(pQ, I1288, I1552);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
void SinitHsimPats(void);
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
|
@ -1,13 +0,0 @@
|
||||||
#include <stdio.h>
|
|
||||||
#include <stdlib.h>
|
|
||||||
#include "rmar0.h"
|
|
||||||
|
|
||||||
// stubs for Hil functions
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
void __Hil__Static_Init_Func__(void) {}
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
|
@ -1,18 +0,0 @@
|
||||||
#ifndef _RMAR1_H_
|
|
||||||
#define _RMAR1_H_
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifndef __DO_RMAHDR_
|
|
||||||
#include "rmar0.h"
|
|
||||||
#endif /*__DO_RMAHDR_*/
|
|
||||||
|
|
||||||
extern UP rmaFunctionRtlArray[];
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
|
|
Binary file not shown.
|
@ -1,13 +0,0 @@
|
||||||
#ifndef _RMAR0_H_
|
|
||||||
#define _RMAR0_H_
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
extern "C" {
|
|
||||||
#endif
|
|
||||||
|
|
||||||
|
|
||||||
#ifdef __cplusplus
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
|
|
Binary file not shown.
Binary file not shown.
Binary file not shown.
|
@ -1,57 +0,0 @@
|
||||||
# 1 "/home/users/laraib.khan/Videos/Quasar/testbench/asm/hello_world.s"
|
|
||||||
# 1 "<built-in>"
|
|
||||||
# 1 "<command-line>"
|
|
||||||
# 1 "/home/users/laraib.khan/Videos/Quasar/testbench/asm/hello_world.s"
|
|
||||||
# 20 "/home/users/laraib.khan/Videos/Quasar/testbench/asm/hello_world.s"
|
|
||||||
# 1 "/home/users/laraib.khan/Videos/Quasar/design/snapshots/default/defines.h" 1
|
|
||||||
# 21 "/home/users/laraib.khan/Videos/Quasar/testbench/asm/hello_world.s" 2
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
.section .text
|
|
||||||
.global _start
|
|
||||||
_start:
|
|
||||||
|
|
||||||
|
|
||||||
csrw minstret, zero
|
|
||||||
csrw minstreth, zero
|
|
||||||
|
|
||||||
|
|
||||||
li x1, 0xee000000
|
|
||||||
csrw mtvec, x1
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
li x1, 0x5f555555
|
|
||||||
csrw 0x7c0, x1
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
li x3, 0xd0580000
|
|
||||||
la x4, hw_data
|
|
||||||
|
|
||||||
loop:
|
|
||||||
lb x5, 0(x4)
|
|
||||||
sb x5, 0(x3)
|
|
||||||
addi x4, x4, 1
|
|
||||||
bnez x5, loop
|
|
||||||
|
|
||||||
|
|
||||||
_finish:
|
|
||||||
li x3, 0xd0580000
|
|
||||||
addi x5, x0, 0xff
|
|
||||||
sb x5, 0(x3)
|
|
||||||
beq x0, x0, _finish
|
|
||||||
.rept 100
|
|
||||||
nop
|
|
||||||
.endr
|
|
||||||
|
|
||||||
.data
|
|
||||||
hw_data:
|
|
||||||
.ascii "----------------------------------\n"
|
|
||||||
.ascii "Hello World from Quasar @LM !!\n"
|
|
||||||
.ascii "----------------------------------\n"
|
|
||||||
.byte 0
|
|
|
@ -1,131 +0,0 @@
|
||||||
|
|
||||||
/home/users/laraib.khan/Videos/Quasar/verif/sim/hello_world.exe: file format elf32-littleriscv
|
|
||||||
|
|
||||||
|
|
||||||
Disassembly of section .text:
|
|
||||||
|
|
||||||
00000000 <_start>:
|
|
||||||
0: b0201073 csrw minstret,zero
|
|
||||||
4: b8201073 csrw minstreth,zero
|
|
||||||
8: ee0000b7 lui ra,0xee000
|
|
||||||
c: 30509073 csrw mtvec,ra
|
|
||||||
10: 5f5550b7 lui ra,0x5f555
|
|
||||||
14: 55508093 addi ra,ra,1365 # 5f555555 <STACK+0x5f53d4e5>
|
|
||||||
18: 7c009073 csrw 0x7c0,ra
|
|
||||||
1c: d05801b7 lui gp,0xd0580
|
|
||||||
|
|
||||||
00000020 <.L0 >:
|
|
||||||
20: 00010217 auipc tp,0x10
|
|
||||||
24: fe020213 addi tp,tp,-32 # 10000 <hw_data>
|
|
||||||
|
|
||||||
00000028 <loop>:
|
|
||||||
28: 00020283 lb t0,0(tp) # 0 <_start>
|
|
||||||
2c: 00518023 sb t0,0(gp) # d0580000 <STACK+0xd0567f90>
|
|
||||||
30: 0205 addi tp,tp,1
|
|
||||||
32: fe029be3 bnez t0,28 <loop>
|
|
||||||
|
|
||||||
00000036 <_finish>:
|
|
||||||
36: d05801b7 lui gp,0xd0580
|
|
||||||
3a: 0ff00293 li t0,255
|
|
||||||
3e: 00518023 sb t0,0(gp) # d0580000 <STACK+0xd0567f90>
|
|
||||||
42: fe000ae3 beqz zero,36 <_finish>
|
|
||||||
46: 0001 nop
|
|
||||||
48: 0001 nop
|
|
||||||
4a: 0001 nop
|
|
||||||
4c: 0001 nop
|
|
||||||
4e: 0001 nop
|
|
||||||
50: 0001 nop
|
|
||||||
52: 0001 nop
|
|
||||||
54: 0001 nop
|
|
||||||
56: 0001 nop
|
|
||||||
58: 0001 nop
|
|
||||||
5a: 0001 nop
|
|
||||||
5c: 0001 nop
|
|
||||||
5e: 0001 nop
|
|
||||||
60: 0001 nop
|
|
||||||
62: 0001 nop
|
|
||||||
64: 0001 nop
|
|
||||||
66: 0001 nop
|
|
||||||
68: 0001 nop
|
|
||||||
6a: 0001 nop
|
|
||||||
6c: 0001 nop
|
|
||||||
6e: 0001 nop
|
|
||||||
70: 0001 nop
|
|
||||||
72: 0001 nop
|
|
||||||
74: 0001 nop
|
|
||||||
76: 0001 nop
|
|
||||||
78: 0001 nop
|
|
||||||
7a: 0001 nop
|
|
||||||
7c: 0001 nop
|
|
||||||
7e: 0001 nop
|
|
||||||
80: 0001 nop
|
|
||||||
82: 0001 nop
|
|
||||||
84: 0001 nop
|
|
||||||
86: 0001 nop
|
|
||||||
88: 0001 nop
|
|
||||||
8a: 0001 nop
|
|
||||||
8c: 0001 nop
|
|
||||||
8e: 0001 nop
|
|
||||||
90: 0001 nop
|
|
||||||
92: 0001 nop
|
|
||||||
94: 0001 nop
|
|
||||||
96: 0001 nop
|
|
||||||
98: 0001 nop
|
|
||||||
9a: 0001 nop
|
|
||||||
9c: 0001 nop
|
|
||||||
9e: 0001 nop
|
|
||||||
a0: 0001 nop
|
|
||||||
a2: 0001 nop
|
|
||||||
a4: 0001 nop
|
|
||||||
a6: 0001 nop
|
|
||||||
a8: 0001 nop
|
|
||||||
aa: 0001 nop
|
|
||||||
ac: 0001 nop
|
|
||||||
ae: 0001 nop
|
|
||||||
b0: 0001 nop
|
|
||||||
b2: 0001 nop
|
|
||||||
b4: 0001 nop
|
|
||||||
b6: 0001 nop
|
|
||||||
b8: 0001 nop
|
|
||||||
ba: 0001 nop
|
|
||||||
bc: 0001 nop
|
|
||||||
be: 0001 nop
|
|
||||||
c0: 0001 nop
|
|
||||||
c2: 0001 nop
|
|
||||||
c4: 0001 nop
|
|
||||||
c6: 0001 nop
|
|
||||||
c8: 0001 nop
|
|
||||||
ca: 0001 nop
|
|
||||||
cc: 0001 nop
|
|
||||||
ce: 0001 nop
|
|
||||||
d0: 0001 nop
|
|
||||||
d2: 0001 nop
|
|
||||||
d4: 0001 nop
|
|
||||||
d6: 0001 nop
|
|
||||||
d8: 0001 nop
|
|
||||||
da: 0001 nop
|
|
||||||
dc: 0001 nop
|
|
||||||
de: 0001 nop
|
|
||||||
e0: 0001 nop
|
|
||||||
e2: 0001 nop
|
|
||||||
e4: 0001 nop
|
|
||||||
e6: 0001 nop
|
|
||||||
e8: 0001 nop
|
|
||||||
ea: 0001 nop
|
|
||||||
ec: 0001 nop
|
|
||||||
ee: 0001 nop
|
|
||||||
f0: 0001 nop
|
|
||||||
f2: 0001 nop
|
|
||||||
f4: 0001 nop
|
|
||||||
f6: 0001 nop
|
|
||||||
f8: 0001 nop
|
|
||||||
fa: 0001 nop
|
|
||||||
fc: 0001 nop
|
|
||||||
fe: 0001 nop
|
|
||||||
100: 0001 nop
|
|
||||||
102: 0001 nop
|
|
||||||
104: 0001 nop
|
|
||||||
106: 0001 nop
|
|
||||||
108: 0001 nop
|
|
||||||
10a: 0001 nop
|
|
||||||
10c: 0001 nop
|
|
Binary file not shown.
Binary file not shown.
|
@ -1,7 +0,0 @@
|
||||||
_end T 0000010e
|
|
||||||
_finish t 00000036
|
|
||||||
hw_data d 00010000
|
|
||||||
.L0 t 00000020
|
|
||||||
loop t 00000028
|
|
||||||
STACK D 00018070
|
|
||||||
_start T 00000000
|
|
BIN
verif/sim/simv
BIN
verif/sim/simv
Binary file not shown.
|
@ -1,160 +0,0 @@
|
||||||
0
|
|
||||||
41
|
|
||||||
+define+RV_OPENSOURCE
|
|
||||||
+error+500
|
|
||||||
+incdir+/home/users/laraib.khan/Videos/Quasar/design/snapshots/default
|
|
||||||
+itf+/eda_tools/vcs201809/linux64/lib/vcsdp_lite.tab
|
|
||||||
+libext+.v
|
|
||||||
+vcsd1
|
|
||||||
+vpi
|
|
||||||
-Mamsrun=
|
|
||||||
-Masflags=
|
|
||||||
-Mcc=gcc
|
|
||||||
-Mcfl= -pipe -fPIC -O -I/eda_tools/vcs201809/include
|
|
||||||
-Mcplusplus=g++
|
|
||||||
-Mcrt0=
|
|
||||||
-Mcrtn=
|
|
||||||
-Mcsrc=
|
|
||||||
-Mexternalobj=
|
|
||||||
-Mldflags= -Wl,--no-as-needed -rdynamic
|
|
||||||
-Mobjects= /eda_tools/vcs201809/linux64/lib/libvirsim.so /eda_tools/vcs201809/linux64/lib/liberrorinf.so /eda_tools/vcs201809/linux64/lib/libsnpsmalloc.so /eda_tools/vcs201809/linux64/lib/libvfs.so
|
|
||||||
-Mout=simv
|
|
||||||
-Msaverestoreobj=/eda_tools/vcs201809/linux64/lib/vcs_save_restore_new.o
|
|
||||||
-Msyslibs=/eda_tools/verdi201809/share/PLI/VCS/LINUX64/pli.a -ldl
|
|
||||||
-Mvcsaceobjs=
|
|
||||||
-Mxcflags= -pipe -fPIC -I/eda_tools/vcs201809/include
|
|
||||||
-P
|
|
||||||
-assert
|
|
||||||
-debug_access
|
|
||||||
-f /home/users/laraib.khan/Videos/Quasar/testbench/flist
|
|
||||||
-fsdb
|
|
||||||
-full64
|
|
||||||
-gen_obj
|
|
||||||
-l
|
|
||||||
-picarchive
|
|
||||||
-sverilog
|
|
||||||
/eda_tools/vcs201809/linux64/bin/vcs1
|
|
||||||
/eda_tools/verdi201809/share/PLI/VCS/LINUX64/verdi.tab
|
|
||||||
/home/users/laraib.khan/Videos/Quasar/design/snapshots/default/common_defines.vh
|
|
||||||
/home/users/laraib.khan/Videos/Quasar/design/snapshots/default/common_defines.vh
|
|
||||||
/home/users/laraib.khan/Videos/Quasar/design/snapshots/default/pdef.vh
|
|
||||||
/home/users/laraib.khan/Videos/Quasar/testbench/tb_top.sv
|
|
||||||
/home/users/laraib.khan/Videos/Quasar/verif/sim/vcs.log
|
|
||||||
svaext
|
|
||||||
85
|
|
||||||
install_root=/softwares/softwares_setups/verilator-4.032
|
|
||||||
XDG_SESSION_ID=476
|
|
||||||
XDG_RUNTIME_DIR=/run/user/1066
|
|
||||||
XDG_MENU_PREFIX=xfce-
|
|
||||||
XDG_DATA_DIRS=/home/users/laraib.khan/.local/share/flatpak/exports/share:/var/lib/flatpak/exports/share:/usr/local/share:/usr/share:/var/lib/snapd/desktop:/usr/share
|
|
||||||
XDG_CURRENT_DESKTOP=XFCE
|
|
||||||
XDG_CONFIG_DIRS=/etc/xdg
|
|
||||||
VTE_VERSION=5202
|
|
||||||
VNCDESKTOP=RakaPoshi:57 (laraib.khan)
|
|
||||||
VMR_MODE_FLAG=64
|
|
||||||
VERILATOR_ROOT=/softwares/softwares_setups/verilator-4.032
|
|
||||||
VERDI_VCS_PLI=-P /eda_tools/verdi201809/share/PLI/VCS/LINUX64/novas.tab /eda_tools/verdi201809/share/PLI/VCS/LINUX64/pli.a
|
|
||||||
VERDI_UVSIM_LIB=-L/eda_tools/verdi201809/share/PLI/IUS/LINUX64 -L/eda_tools/verdi201809/share/FsdbWriter/LINUX64
|
|
||||||
VERDI_UVSIM_INCLUDE=-I/eda_tools/verdi201809/share/PLI/IUS/LINUX64
|
|
||||||
VERDI_NCVERILOG_PLI=+loadpli1=/eda_tools/verdi201809/share/PLI/IUS/LINUX64/boot/debpli:novas_pli_boot
|
|
||||||
VERDI_NCELAB_PLI=-LOADPLI1 /eda_tools/verdi201809/share/PLI/IUS/LINUX64/boot/debpli:novas_pli_boot
|
|
||||||
VERDI_HOME=/eda_tools/verdi201809
|
|
||||||
VERDI_FSDBSC=-L/eda_tools/verdi201809/share/PLI/IUS/LINUX64 -lfsdbSC -L/eda_tools/verdi201809/share/FsdbWriter/LINUX64 -lnffw -I/eda_tools/verdi201809/share/PLI/IUS/LINUX64
|
|
||||||
VERDI=/eda_tools/verdi201809
|
|
||||||
VCS_TARGET_ARCH=amd64
|
|
||||||
VCS_MX_HOME_INTERNAL=1
|
|
||||||
VCS_MODE_FLAG=64
|
|
||||||
VCS_LOG_FILE=/home/users/laraib.khan/Videos/Quasar/verif/sim/vcs.log
|
|
||||||
VCS_HOME=/eda_tools/vcs201809
|
|
||||||
VCS_DEPTH=0
|
|
||||||
VCS_ARG_ADDED_FOR_TMP=1
|
|
||||||
VCS_ARCH_OVERRIDE=linux
|
|
||||||
VCS_ARCH=linux64
|
|
||||||
UNAME=/bin/uname
|
|
||||||
TOOL_HOME=/eda_tools/vcs201809/linux64
|
|
||||||
TERMINATOR_UUID=urn:uuid:67b89c3b-4ce7-4f56-9665-2acf132760ed
|
|
||||||
TERMINATOR_DBUS_PATH=/net/tenshu/Terminator2
|
|
||||||
TERMINATOR_DBUS_NAME=net.tenshu.Terminator20x759fefb189f69525
|
|
||||||
S_COLORS=auto
|
|
||||||
SYSTEMC_HOME=/usr/local/systemc-2.3.1/
|
|
||||||
SYNOP_VCS=/eda_tools/vcs201809/bin
|
|
||||||
SYNOP_PT=/eda_tools/pt201806
|
|
||||||
SYNOP_FM=/eda_tools/formaility-201806sp5
|
|
||||||
SSH_TTY=/dev/pts/14
|
|
||||||
SSH_CONNECTION=192.168.20.32 52989 192.168.14.241 10139
|
|
||||||
SSH_CLIENT=192.168.20.32 52989 10139
|
|
||||||
SSH_AUTH_SOCK=/tmp/ssh-D8t8wLIA47hG/agent.24488
|
|
||||||
SSH_AGENT_PID=24489
|
|
||||||
SPYGLASS_HOME=/eda_tools/spyglass2018/spyglass_vO-2018.09/spyglass/SPYGLASS2018.09/SPYGLASS_HOME
|
|
||||||
SNPS_VCS_INTERNAL_UBUNTU_PRE_LDFLAGS= -no-pie
|
|
||||||
SESSION_MANAGER=local/RakaPoshi:@/tmp/.ICE-unix/24481,unix/RakaPoshi:/tmp/.ICE-unix/24481
|
|
||||||
SCRNAME=vcs
|
|
||||||
SCRIPT_NAME=vcs
|
|
||||||
RV_ROOT=/home/users/laraib.khan/Videos/Quasar
|
|
||||||
RISCV_TOOLCHAIN=/cores/chipyard/riscv-tools-install
|
|
||||||
RISCV_PATH=/cores/chipyard/riscv-tools-install
|
|
||||||
RISCV_OBJDUMP=/cores/chipyard/riscv-tools-install/bin/riscv64-unknown-elf-objdump
|
|
||||||
RISCV_OBJCOPY=/cores/chipyard/riscv-tools-install/bin/riscv64-unknown-elf-objcopy
|
|
||||||
RISCV_LD=/cores/chipyard/riscv-tools-install/bin/riscv64-unknown-elf-ld
|
|
||||||
RISCV_GCC=/cores/chipyard/riscv-tools-install/bin/riscv64-unknown-elf-gcc
|
|
||||||
PLATFORM=LINUX64
|
|
||||||
OVA_UUM=0
|
|
||||||
NOVAS_VERDI=/eda_tools/verdi201809/bin
|
|
||||||
NOVAS_HOME=/eda_tools/verdi201809
|
|
||||||
MFLAGS=
|
|
||||||
MAKE_TERMOUT=/dev/pts/70
|
|
||||||
MAKE_TERMERR=/dev/pts/70
|
|
||||||
MAKELEVEL=1
|
|
||||||
MAKEFLAGS=
|
|
||||||
LESSOPEN=| /usr/bin/lesspipe %s
|
|
||||||
LESSCLOSE=/usr/bin/lesspipe %s %s
|
|
||||||
LC_TIME=en_US.UTF-8
|
|
||||||
LC_TELEPHONE=ur_PK
|
|
||||||
LC_PAPER=ur_PK
|
|
||||||
LC_NUMERIC=ur_PK
|
|
||||||
LC_NAME=ur_PK
|
|
||||||
LC_MONETARY=ur_PK
|
|
||||||
LC_MEASUREMENT=ur_PK
|
|
||||||
LC_IDENTIFICATION=ur_PK
|
|
||||||
LC_ALL=C
|
|
||||||
LC_ADDRESS=ur_PK
|
|
||||||
GLADE_PIXMAP_PATH=:
|
|
||||||
GLADE_MODULE_PATH=:
|
|
||||||
GLADE_CATALOG_PATH=:
|
|
||||||
DESKTOP_SESSION=xfce
|
|
||||||
DEBUSSY_HOME=/eda_tools/verdi201809
|
|
||||||
DCDIR=/eda_tools/dc2018/O-2018.06-SP5
|
|
||||||
DBUS_SESSION_BUS_ADDRESS=unix:abstract=/tmp/dbus-UHsOlJEsBG,guid=e033b07cc261d020e53027345ffc04cb
|
|
||||||
COLORTERM=truecolor
|
|
||||||
ARCH=amd64
|
|
||||||
0
|
|
||||||
22
|
|
||||||
1610541419 /home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/beh_lib.sv
|
|
||||||
1591249347 /eda_tools/vcs201809/etc/sva/rec_ltl_classes_package.svp
|
|
||||||
1614166058 /home/users/laraib.khan/Videos/Quasar/testbench/tb_top.sv
|
|
||||||
1614166058 /home/users/laraib.khan/Videos/Quasar/testbench/ahb_sif.sv
|
|
||||||
1614166058 /home/users/laraib.khan/Videos/Quasar/testbench/axi_lsu_dma_bridge.sv
|
|
||||||
1614167717 /home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/mem_lib.sv
|
|
||||||
1610541419 /home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/beh_lib.sv
|
|
||||||
1614167717 /home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/gated_latch.sv
|
|
||||||
1614167717 /home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/rvjtag_tap.sv
|
|
||||||
1614167717 /home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv
|
|
||||||
1614167717 /home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/dmi_wrapper.sv
|
|
||||||
1614317074 /home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/lsu_dccm_mem.sv
|
|
||||||
1614318926 /home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/ifu_iccm_mem.sv
|
|
||||||
1614319689 /home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/ifu_ic_mem.sv
|
|
||||||
1614258172 /home/users/laraib.khan/Videos/Quasar/design/src/main/resources/vsrc/mem.sv
|
|
||||||
1614663878 /home/users/laraib.khan/Videos/Quasar/generated_rtl/quasar_wrapper.sv
|
|
||||||
1614663663 /home/users/laraib.khan/Videos/Quasar/design/snapshots/default/pdef.vh
|
|
||||||
1614663663 /home/users/laraib.khan/Videos/Quasar/design/snapshots/default/common_defines.vh
|
|
||||||
1614663663 /home/users/laraib.khan/Videos/Quasar/design/snapshots/default/common_defines.vh
|
|
||||||
1614166058 /home/users/laraib.khan/Videos/Quasar/testbench/flist
|
|
||||||
1591249361 /eda_tools/verdi201809/share/PLI/VCS/LINUX64/verdi.tab
|
|
||||||
1591249347 /eda_tools/vcs201809/linux64/lib/vcsdp_lite.tab
|
|
||||||
4
|
|
||||||
1591249345 /eda_tools/vcs201809/linux64/lib/libvirsim.so
|
|
||||||
1591249347 /eda_tools/vcs201809/linux64/lib/liberrorinf.so
|
|
||||||
1591249345 /eda_tools/vcs201809/linux64/lib/libsnpsmalloc.so
|
|
||||||
1591249346 /eda_tools/vcs201809/linux64/lib/libvfs.so
|
|
||||||
1614663917 simv.daidir
|
|
||||||
-1 partitionlib
|
|
|
@ -1,5 +0,0 @@
|
||||||
import_DPI svapfGetAttempt SnpsSVA_classes
|
|
||||||
import_DPI svapfReportResult SnpsSVA_classes
|
|
||||||
import_DPI svapfGetAssertEnabled SnpsSVA_classes
|
|
||||||
DirectC SdisableFork
|
|
||||||
DirectC Wterminatesynch
|
|
Binary file not shown.
Binary file not shown.
|
@ -1,4 +0,0 @@
|
||||||
#!/bin/sh -e
|
|
||||||
# This file is automatically generated by VCS. Any changes you make
|
|
||||||
# to it will be overwritten the next time VCS is run.
|
|
||||||
vcs '-full64' '-LDFLAGS' '-Wl,--no-as-needed' '-assert' 'svaext' '-sverilog' '+define+RV_OPENSOURCE' '+error+500' '-debug_access' '/home/users/laraib.khan/Videos/Quasar/design/snapshots/default/common_defines.vh' '+incdir+/home/users/laraib.khan/Videos/Quasar/design/snapshots/default' '+libext+.v' '/home/users/laraib.khan/Videos/Quasar/design/snapshots/default/common_defines.vh' '/home/users/laraib.khan/Videos/Quasar/design/snapshots/default/pdef.vh' '-f' '/home/users/laraib.khan/Videos/Quasar/testbench/flist' '/home/users/laraib.khan/Videos/Quasar/testbench/tb_top.sv' '-l' '/home/users/laraib.khan/Videos/Quasar/verif/sim/vcs.log' -static_dbgen_only -daidir=$1 2>&1
|
|
File diff suppressed because one or more lines are too long
|
@ -1,2 +0,0 @@
|
||||||
Dummy_file
|
|
||||||
Missing line/file info
|
|
|
@ -1,266 +0,0 @@
|
||||||
{
|
|
||||||
"_vcs_unit__1603002319": [
|
|
||||||
"_vcs_unit__1603002319",
|
|
||||||
"bUdKt",
|
|
||||||
"module",
|
|
||||||
1
|
|
||||||
],
|
|
||||||
"std": [
|
|
||||||
"std",
|
|
||||||
"reYIK",
|
|
||||||
"module",
|
|
||||||
2
|
|
||||||
],
|
|
||||||
"rvclkhdr": [
|
|
||||||
"rvclkhdr",
|
|
||||||
"Lbw3w",
|
|
||||||
"module",
|
|
||||||
3
|
|
||||||
],
|
|
||||||
"ifu_bp_ctl": [
|
|
||||||
"ifu_bp_ctl",
|
|
||||||
"tYz5w",
|
|
||||||
"module",
|
|
||||||
4
|
|
||||||
],
|
|
||||||
"ifu_compress_ctl": [
|
|
||||||
"ifu_compress_ctl",
|
|
||||||
"Crn5e",
|
|
||||||
"module",
|
|
||||||
5
|
|
||||||
],
|
|
||||||
"ifu_aln_ctl": [
|
|
||||||
"ifu_aln_ctl",
|
|
||||||
"kuPNM",
|
|
||||||
"module",
|
|
||||||
6
|
|
||||||
],
|
|
||||||
"ifu_ifc_ctl": [
|
|
||||||
"ifu_ifc_ctl",
|
|
||||||
"pszgZ",
|
|
||||||
"module",
|
|
||||||
7
|
|
||||||
],
|
|
||||||
"ifu": [
|
|
||||||
"ifu",
|
|
||||||
"aJziF",
|
|
||||||
"module",
|
|
||||||
8
|
|
||||||
],
|
|
||||||
"dec_dec_ctl": [
|
|
||||||
"dec_dec_ctl",
|
|
||||||
"A1pVd",
|
|
||||||
"module",
|
|
||||||
9
|
|
||||||
],
|
|
||||||
"dec_gpr_ctl": [
|
|
||||||
"dec_gpr_ctl",
|
|
||||||
"GHJ4k",
|
|
||||||
"module",
|
|
||||||
10
|
|
||||||
],
|
|
||||||
"int_exc": [
|
|
||||||
"int_exc",
|
|
||||||
"uMx7H",
|
|
||||||
"module",
|
|
||||||
11
|
|
||||||
],
|
|
||||||
"perf_mux_and_flops": [
|
|
||||||
"perf_mux_and_flops",
|
|
||||||
"xqE6L",
|
|
||||||
"module",
|
|
||||||
12
|
|
||||||
],
|
|
||||||
"perf_csr": [
|
|
||||||
"perf_csr",
|
|
||||||
"nUefn",
|
|
||||||
"module",
|
|
||||||
13
|
|
||||||
],
|
|
||||||
"csr_tlu": [
|
|
||||||
"csr_tlu",
|
|
||||||
"W0QmL",
|
|
||||||
"module",
|
|
||||||
14
|
|
||||||
],
|
|
||||||
"dec_timer_ctl": [
|
|
||||||
"dec_timer_ctl",
|
|
||||||
"tLfqI",
|
|
||||||
"module",
|
|
||||||
15
|
|
||||||
],
|
|
||||||
"dec_decode_csr_read": [
|
|
||||||
"dec_decode_csr_read",
|
|
||||||
"LUVCJ",
|
|
||||||
"module",
|
|
||||||
16
|
|
||||||
],
|
|
||||||
"dec_tlu_ctl": [
|
|
||||||
"dec_tlu_ctl",
|
|
||||||
"hJmbb",
|
|
||||||
"module",
|
|
||||||
17
|
|
||||||
],
|
|
||||||
"dec_trigger": [
|
|
||||||
"dec_trigger",
|
|
||||||
"G9wA0",
|
|
||||||
"module",
|
|
||||||
18
|
|
||||||
],
|
|
||||||
"dec": [
|
|
||||||
"dec",
|
|
||||||
"pBTdY",
|
|
||||||
"module",
|
|
||||||
19
|
|
||||||
],
|
|
||||||
"dbg": [
|
|
||||||
"dbg",
|
|
||||||
"Epw58",
|
|
||||||
"module",
|
|
||||||
20
|
|
||||||
],
|
|
||||||
"exu_mul_ctl": [
|
|
||||||
"exu_mul_ctl",
|
|
||||||
"i46HG",
|
|
||||||
"module",
|
|
||||||
21
|
|
||||||
],
|
|
||||||
"exu_div_cls": [
|
|
||||||
"exu_div_cls",
|
|
||||||
"LLg6t",
|
|
||||||
"module",
|
|
||||||
22
|
|
||||||
],
|
|
||||||
"exu_div_ctl": [
|
|
||||||
"exu_div_ctl",
|
|
||||||
"jTTHC",
|
|
||||||
"module",
|
|
||||||
23
|
|
||||||
],
|
|
||||||
"exu": [
|
|
||||||
"exu",
|
|
||||||
"EH8H4",
|
|
||||||
"module",
|
|
||||||
24
|
|
||||||
],
|
|
||||||
"lsu_dccm_ctl": [
|
|
||||||
"lsu_dccm_ctl",
|
|
||||||
"tjY46",
|
|
||||||
"module",
|
|
||||||
25
|
|
||||||
],
|
|
||||||
"lsu_stbuf": [
|
|
||||||
"lsu_stbuf",
|
|
||||||
"AWKgR",
|
|
||||||
"module",
|
|
||||||
26
|
|
||||||
],
|
|
||||||
"lsu_ecc": [
|
|
||||||
"lsu_ecc",
|
|
||||||
"YV21G",
|
|
||||||
"module",
|
|
||||||
27
|
|
||||||
],
|
|
||||||
"lsu_trigger": [
|
|
||||||
"lsu_trigger",
|
|
||||||
"rfBvB",
|
|
||||||
"module",
|
|
||||||
28
|
|
||||||
],
|
|
||||||
"lsu_clkdomain": [
|
|
||||||
"lsu_clkdomain",
|
|
||||||
"rAdC7",
|
|
||||||
"module",
|
|
||||||
29
|
|
||||||
],
|
|
||||||
"lsu_bus_intf": [
|
|
||||||
"lsu_bus_intf",
|
|
||||||
"bbpP3",
|
|
||||||
"module",
|
|
||||||
30
|
|
||||||
],
|
|
||||||
"lsu": [
|
|
||||||
"lsu",
|
|
||||||
"xfmAy",
|
|
||||||
"module",
|
|
||||||
31
|
|
||||||
],
|
|
||||||
"pic_ctrl": [
|
|
||||||
"pic_ctrl",
|
|
||||||
"JYwsi",
|
|
||||||
"module",
|
|
||||||
32
|
|
||||||
],
|
|
||||||
"dma_ctrl": [
|
|
||||||
"dma_ctrl",
|
|
||||||
"jk4yL",
|
|
||||||
"module",
|
|
||||||
33
|
|
||||||
],
|
|
||||||
"quasar": [
|
|
||||||
"quasar",
|
|
||||||
"xmuq2",
|
|
||||||
"module",
|
|
||||||
34
|
|
||||||
],
|
|
||||||
"ifu_iccm_mem_0000": [
|
|
||||||
"ifu_iccm_mem_0000",
|
|
||||||
"uVamz",
|
|
||||||
"module",
|
|
||||||
35
|
|
||||||
],
|
|
||||||
"dmi_wrapper": [
|
|
||||||
"dmi_wrapper",
|
|
||||||
"RjLew",
|
|
||||||
"module",
|
|
||||||
36
|
|
||||||
],
|
|
||||||
"tb_top": [
|
|
||||||
"tb_top",
|
|
||||||
"jdPWL",
|
|
||||||
"module",
|
|
||||||
37
|
|
||||||
],
|
|
||||||
"SnpsSVA_classes": [
|
|
||||||
"SnpsSVA_classes",
|
|
||||||
"KrGDi",
|
|
||||||
"module",
|
|
||||||
38
|
|
||||||
],
|
|
||||||
"rvdff_0000_0000": [
|
|
||||||
"rvdff_0000_0000",
|
|
||||||
"jgE6r",
|
|
||||||
"module",
|
|
||||||
39
|
|
||||||
],
|
|
||||||
"rvecc_decode_0000": [
|
|
||||||
"rvecc_decode_0000",
|
|
||||||
"M6knD",
|
|
||||||
"module",
|
|
||||||
40
|
|
||||||
],
|
|
||||||
"ram_4096x39": [
|
|
||||||
"ram_4096x39",
|
|
||||||
"sbQpB",
|
|
||||||
"module",
|
|
||||||
41
|
|
||||||
],
|
|
||||||
"axi_lsu_dma_bridge": [
|
|
||||||
"axi_lsu_dma_bridge",
|
|
||||||
"mBf4Q",
|
|
||||||
"module",
|
|
||||||
42
|
|
||||||
],
|
|
||||||
"axi_slv": [
|
|
||||||
"axi_slv",
|
|
||||||
"MYfHG",
|
|
||||||
"module",
|
|
||||||
43
|
|
||||||
],
|
|
||||||
"...MASTER...": [
|
|
||||||
"SIM",
|
|
||||||
"amcQw",
|
|
||||||
"module",
|
|
||||||
44
|
|
||||||
]
|
|
||||||
}
|
|
|
@ -1,4 +0,0 @@
|
||||||
O-2018.09-SP2-4_Full64
|
|
||||||
Build Date = Jul 13 2019 20:31:39
|
|
||||||
RedHat
|
|
||||||
Compile Location: /home/users/laraib.khan/Videos/Quasar
|
|
Binary file not shown.
Binary file not shown.
|
@ -1,9 +0,0 @@
|
||||||
#!/bin/sh -h
|
|
||||||
PYTHONHOME=/eda_tools/vcs201809/etc/search/pyh
|
|
||||||
export PYTHONHOME
|
|
||||||
PYTHONPATH=/eda_tools/vcs201809/linux64/lib/pylib27
|
|
||||||
export PYTHONPATH
|
|
||||||
LD_LIBRARY_PATH=/eda_tools/vcs201809/linux64/lib:/eda_tools/vcs201809/linux64/lib/pylib27
|
|
||||||
export LD_LIBRARY_PATH
|
|
||||||
/eda_tools/vcs201809/linux64/bin/vcsfind_create_index.exe -z "/home/users/laraib.khan/Videos/Quasar/simv.daidir/debug_dump/fsearch/./idents_tapi.xml.gz" "/home/users/laraib.khan/Videos/Quasar/simv.daidir/debug_dump/fsearch/./idents_yZgEwz.xml.gz" -o "/home/users/laraib.khan/Videos/Quasar/simv.daidir/debug_dump/fsearch/fsearch.db_tmp"
|
|
||||||
\mv "/home/users/laraib.khan/Videos/Quasar/simv.daidir/debug_dump/fsearch/fsearch.db_tmp" "/home/users/laraib.khan/Videos/Quasar/simv.daidir/debug_dump/fsearch/fsearch.db"
|
|
|
@ -1,57 +0,0 @@
|
||||||
#!/bin/sh -h
|
|
||||||
|
|
||||||
FILE_PATH="/home/users/laraib.khan/Videos/Quasar/simv.daidir/debug_dump/fsearch"
|
|
||||||
lockfile="${FILE_PATH}"/lock
|
|
||||||
|
|
||||||
FSearch_lock_release() {
|
|
||||||
echo "" > /dev/null
|
|
||||||
}
|
|
||||||
create_fsearch_db_ctrl() {
|
|
||||||
if [ -s "${FILE_PATH}"/fsearch.stat ]; then
|
|
||||||
if [ -s "${FILE_PATH}"/fsearch.log ]; then
|
|
||||||
echo "ERROR building identifier database failed. Check ${FILE_PATH}/fsearch.log"
|
|
||||||
else
|
|
||||||
cat "${FILE_PATH}"/fsearch.stat
|
|
||||||
fi
|
|
||||||
return
|
|
||||||
fi
|
|
||||||
nohup "$1" > "${FILE_PATH}"/fsearch.log 2>&1 193>/dev/null &
|
|
||||||
MY_PID=`echo $!`
|
|
||||||
BUILDER="pid ${MY_PID} ${USER}@${hostname}"
|
|
||||||
echo "INFO Started building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier."
|
|
||||||
echo "INFO Still building database for Identifiers, please wait ($BUILDER). Use VCS elab option '-debug_access+idents_db' to build the database earlier." > "${FILE_PATH}"/fsearch.stat
|
|
||||||
return
|
|
||||||
}
|
|
||||||
|
|
||||||
dir_name=`/usr/bin/dirname "$0"`
|
|
||||||
if [ "${dir_name}" = "." ]; then
|
|
||||||
cd $dir_name
|
|
||||||
dir_name=`/bin/pwd`
|
|
||||||
fi
|
|
||||||
if [ -d "$dir_name"/../../../../../../../.. ]; then
|
|
||||||
cd "$dir_name"/../../../../../../../..
|
|
||||||
fi
|
|
||||||
|
|
||||||
if [ -f "/home/users/laraib.khan/Videos/Quasar/simv.daidir/debug_dump/fsearch/.create_fsearch_db" ]; then
|
|
||||||
if [ ! -f "/home/users/laraib.khan/Videos/Quasar/simv.daidir/debug_dump/fsearch/fsearch.db" ]; then
|
|
||||||
if [ "$#" -eq 1 ] && [ "x$1" == "x-background" ]; then
|
|
||||||
trap FSearch_lock_release EXIT
|
|
||||||
(
|
|
||||||
flock 193
|
|
||||||
create_fsearch_db_ctrl "/home/users/laraib.khan/Videos/Quasar/simv.daidir/debug_dump/fsearch/.create_fsearch_db"
|
|
||||||
exit 193
|
|
||||||
) 193> "$lockfile"
|
|
||||||
rstat=$?
|
|
||||||
if [ "${rstat}"x != "193x" ]; then
|
|
||||||
exit $rstat
|
|
||||||
fi
|
|
||||||
else
|
|
||||||
"/home/users/laraib.khan/Videos/Quasar/simv.daidir/debug_dump/fsearch/.create_fsearch_db"
|
|
||||||
if [ -f "/home/users/laraib.khan/Videos/Quasar/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then
|
|
||||||
rm -f "/home/users/laraib.khan/Videos/Quasar/simv.daidir/debug_dump/fsearch/fsearch.stat"
|
|
||||||
fi
|
|
||||||
fi
|
|
||||||
elif [ -f "/home/users/laraib.khan/Videos/Quasar/simv.daidir/debug_dump/fsearch/fsearch.stat" ]; then
|
|
||||||
rm -f "/home/users/laraib.khan/Videos/Quasar/simv.daidir/debug_dump/fsearch/fsearch.stat"
|
|
||||||
fi
|
|
||||||
fi
|
|
Binary file not shown.
Binary file not shown.
|
@ -1 +0,0 @@
|
||||||
ケX<EFBDB9>^<5E><18>
|
|
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue