diff --git a/ahb_to_axi4.fir b/ahb_to_axi4.fir index 792a349c..59d78597 100644 --- a/ahb_to_axi4.fir +++ b/ahb_to_axi4.fir @@ -504,7 +504,7 @@ circuit ahb_to_axi4 : io.axi.aw.bits.prot <= _T_186 @[ahb_to_axi4.scala 158:33] node _T_187 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] io.axi.aw.bits.len <= _T_187 @[ahb_to_axi4.scala 159:33] - io.axi.aw.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 160:33] + io.axi.aw.bits.burst <= UInt<2>("h01") @[ahb_to_axi4.scala 160:33] node _T_188 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 162:42] io.axi.w.valid <= _T_188 @[ahb_to_axi4.scala 162:28] io.axi.w.bits.data <= cmdbuf_wdata @[ahb_to_axi4.scala 163:33] @@ -523,6 +523,6 @@ circuit ahb_to_axi4 : io.axi.ar.bits.prot <= _T_193 @[ahb_to_axi4.scala 173:33] node _T_194 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] io.axi.ar.bits.len <= _T_194 @[ahb_to_axi4.scala 174:33] - io.axi.ar.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 175:33] + io.axi.ar.bits.burst <= UInt<2>("h01") @[ahb_to_axi4.scala 175:33] io.axi.r.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 177:28] diff --git a/axi4_to_ahb.anno.json b/axi4_to_ahb.anno.json new file mode 100644 index 00000000..99ab884d --- /dev/null +++ b/axi4_to_ahb.anno.json @@ -0,0 +1,114 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_haddr", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_ahb_out_htrans", + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_addr", + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_w_ready", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hprot", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_prot" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_aw_ready", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_b_valid", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hsize", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_size", + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hwrite", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_htrans", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_r_valid", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_ready", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"axi4_to_ahb.gated_latch", + "resourceId":"/vsrc/gated_latch.sv" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"axi4_to_ahb" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/axi4_to_ahb.fir b/axi4_to_ahb.fir new file mode 100644 index 00000000..1e88bd14 --- /dev/null +++ b/axi4_to_ahb.fir @@ -0,0 +1,1271 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit axi4_to_ahb : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module axi4_to_ahb : + input clock : Clock + input reset : AsyncReset + output io : {flip free_clk : Clock, flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} + + wire dec_tlu_force_halt_bus_q : UInt<1> + dec_tlu_force_halt_bus_q <= UInt<1>("h00") + node dec_tlu_force_halt_bus = or(io.dec_tlu_force_halt, dec_tlu_force_halt_bus_q) @[axi4_to_ahb.scala 24:54] + node _T = eq(io.bus_clk_en, UInt<1>("h00")) @[axi4_to_ahb.scala 25:35] + node dec_tlu_force_halt_bus_ns = and(_T, dec_tlu_force_halt_bus) @[axi4_to_ahb.scala 25:50] + reg _T_1 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 26:62] + _T_1 <= dec_tlu_force_halt_bus_ns @[axi4_to_ahb.scala 26:62] + dec_tlu_force_halt_bus_q <= _T_1 @[axi4_to_ahb.scala 26:28] + wire buf_rst : UInt<1> + buf_rst <= UInt<1>("h00") + buf_rst <= dec_tlu_force_halt_bus @[axi4_to_ahb.scala 28:11] + io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 29:21] + wire buf_state_en : UInt<1> + buf_state_en <= UInt<1>("h00") + wire bus_clk : Clock @[axi4_to_ahb.scala 31:21] + wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 32:27] + wire buf_state : UInt<3> + buf_state <= UInt<3>("h00") + wire buf_nxtstate : UInt<3> + buf_nxtstate <= UInt<3>("h00") + node _T_2 = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 36:62] + wire _T_3 : UInt @[lib.scala 389:21] + node _T_4 = eq(buf_rst, UInt<1>("h00")) @[lib.scala 391:75] + node _T_5 = and(buf_nxtstate, _T_4) @[lib.scala 391:53] + node _T_6 = or(_T_2, buf_rst) @[lib.scala 391:95] + node _T_7 = and(_T_6, io.bus_clk_en) @[lib.scala 391:102] + node _T_8 = bits(_T_7, 0, 0) @[lib.scala 8:44] + reg _T_9 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_8 : @[Reg.scala 28:19] + _T_9 <= _T_5 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_3 <= _T_9 @[lib.scala 391:14] + buf_state <= _T_3 @[axi4_to_ahb.scala 36:13] + wire slave_valid : UInt<1> + slave_valid <= UInt<1>("h00") + wire slave_ready : UInt<1> + slave_ready <= UInt<1>("h00") + wire slave_tag : UInt<1> + slave_tag <= UInt<1>("h00") + wire slave_rdata : UInt<64> + slave_rdata <= UInt<64>("h00") + wire slave_opc : UInt<4> + slave_opc <= UInt<4>("h00") + wire wrbuf_en : UInt<1> + wrbuf_en <= UInt<1>("h00") + wire wrbuf_data_en : UInt<1> + wrbuf_data_en <= UInt<1>("h00") + wire wrbuf_cmd_sent : UInt<1> + wrbuf_cmd_sent <= UInt<1>("h00") + wire wrbuf_rst : UInt<1> + wrbuf_rst <= UInt<1>("h00") + wire wrbuf_vld : UInt<1> + wrbuf_vld <= UInt<1>("h00") + wire wrbuf_data_vld : UInt<1> + wrbuf_data_vld <= UInt<1>("h00") + wire wrbuf_tag : UInt<1> + wrbuf_tag <= UInt<1>("h00") + wire wrbuf_size : UInt<3> + wrbuf_size <= UInt<3>("h00") + wire wrbuf_addr : UInt<32> + wrbuf_addr <= UInt<32>("h00") + wire wrbuf_data : UInt<64> + wrbuf_data <= UInt<64>("h00") + wire wrbuf_byteen : UInt<8> + wrbuf_byteen <= UInt<8>("h00") + wire master_valid : UInt<1> + master_valid <= UInt<1>("h00") + wire master_ready : UInt<1> + master_ready <= UInt<1>("h00") + wire master_tag : UInt<1> + master_tag <= UInt<1>("h00") + wire master_addr : UInt<32> + master_addr <= UInt<32>("h00") + wire master_wdata : UInt<64> + master_wdata <= UInt<64>("h00") + wire master_size : UInt<3> + master_size <= UInt<3>("h00") + wire master_opc : UInt<3> + master_opc <= UInt<3>("h00") + wire master_byteen : UInt<8> + master_byteen <= UInt<8>("h00") + wire buf_addr : UInt<32> + buf_addr <= UInt<32>("h00") + wire buf_size : UInt<2> + buf_size <= UInt<2>("h00") + wire buf_write : UInt<1> + buf_write <= UInt<1>("h00") + wire buf_byteen : UInt<8> + buf_byteen <= UInt<8>("h00") + wire buf_aligned : UInt<1> + buf_aligned <= UInt<1>("h00") + wire buf_data : UInt<64> + buf_data <= UInt<64>("h00") + wire buf_tag : UInt<1> + buf_tag <= UInt<1>("h00") + wire buf_tag_in : UInt<1> + buf_tag_in <= UInt<1>("h00") + wire buf_addr_in : UInt<32> + buf_addr_in <= UInt<32>("h00") + wire buf_byteen_in : UInt<8> + buf_byteen_in <= UInt<8>("h00") + wire buf_data_in : UInt<64> + buf_data_in <= UInt<64>("h00") + wire buf_write_in : UInt<1> + buf_write_in <= UInt<1>("h00") + wire buf_aligned_in : UInt<1> + buf_aligned_in <= UInt<1>("h00") + wire buf_size_in : UInt<3> + buf_size_in <= UInt<3>("h00") + wire buf_wr_en : UInt<1> + buf_wr_en <= UInt<1>("h00") + wire buf_data_wr_en : UInt<1> + buf_data_wr_en <= UInt<1>("h00") + wire slvbuf_error_en : UInt<1> + slvbuf_error_en <= UInt<1>("h00") + wire wr_cmd_vld : UInt<1> + wr_cmd_vld <= UInt<1>("h00") + wire cmd_done_rst : UInt<1> + cmd_done_rst <= UInt<1>("h00") + wire cmd_done : UInt<1> + cmd_done <= UInt<1>("h00") + wire cmd_doneQ : UInt<1> + cmd_doneQ <= UInt<1>("h00") + wire trxn_done : UInt<1> + trxn_done <= UInt<1>("h00") + wire buf_cmd_byte_ptr : UInt<3> + buf_cmd_byte_ptr <= UInt<3>("h00") + wire buf_cmd_byte_ptrQ : UInt<3> + buf_cmd_byte_ptrQ <= UInt<3>("h00") + wire buf_cmd_nxtbyte_ptr : UInt<3> + buf_cmd_nxtbyte_ptr <= UInt<3>("h00") + wire buf_cmd_byte_ptr_en : UInt<1> + buf_cmd_byte_ptr_en <= UInt<1>("h00") + wire found : UInt<1> + found <= UInt<1>("h00") + wire slave_valid_pre : UInt<1> + slave_valid_pre <= UInt<1>("h00") + wire ahb_hready_q : UInt<1> + ahb_hready_q <= UInt<1>("h00") + wire ahb_hresp_q : UInt<1> + ahb_hresp_q <= UInt<1>("h00") + wire ahb_htrans_q : UInt<2> + ahb_htrans_q <= UInt<2>("h00") + wire ahb_hwrite_q : UInt<1> + ahb_hwrite_q <= UInt<1>("h00") + wire ahb_hrdata_q : UInt<64> + ahb_hrdata_q <= UInt<64>("h00") + wire slvbuf_write : UInt<1> + slvbuf_write <= UInt<1>("h00") + wire slvbuf_error : UInt<1> + slvbuf_error <= UInt<1>("h00") + wire slvbuf_tag : UInt<1> + slvbuf_tag <= UInt<1>("h00") + wire slvbuf_error_in : UInt<1> + slvbuf_error_in <= UInt<1>("h00") + wire slvbuf_wr_en : UInt<1> + slvbuf_wr_en <= UInt<1>("h00") + wire bypass_en : UInt<1> + bypass_en <= UInt<1>("h00") + wire rd_bypass_idle : UInt<1> + rd_bypass_idle <= UInt<1>("h00") + wire last_addr_en : UInt<1> + last_addr_en <= UInt<1>("h00") + wire last_bus_addr : UInt<32> + last_bus_addr <= UInt<32>("h00") + wire buf_clken : UInt<1> + buf_clken <= UInt<1>("h00") + wire ahbm_data_clken : UInt<1> + ahbm_data_clken <= UInt<1>("h00") + wire buf_clk : Clock @[axi4_to_ahb.scala 118:21] + node _T_10 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 140:27] + wr_cmd_vld <= _T_10 @[axi4_to_ahb.scala 140:14] + node _T_11 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 141:30] + master_valid <= _T_11 @[axi4_to_ahb.scala 141:16] + node _T_12 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 142:38] + node _T_13 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 142:51] + node _T_14 = bits(io.axi.ar.bits.id, 0, 0) @[axi4_to_ahb.scala 142:82] + node _T_15 = mux(_T_12, _T_13, _T_14) @[axi4_to_ahb.scala 142:20] + master_tag <= _T_15 @[axi4_to_ahb.scala 142:14] + node _T_16 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 143:38] + node _T_17 = mux(_T_16, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 143:20] + master_opc <= _T_17 @[axi4_to_ahb.scala 143:14] + node _T_18 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 144:39] + node _T_19 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 144:53] + node _T_20 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 144:81] + node _T_21 = mux(_T_18, _T_19, _T_20) @[axi4_to_ahb.scala 144:21] + master_addr <= _T_21 @[axi4_to_ahb.scala 144:15] + node _T_22 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 145:39] + node _T_23 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 145:53] + node _T_24 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 145:80] + node _T_25 = mux(_T_22, _T_23, _T_24) @[axi4_to_ahb.scala 145:21] + master_size <= _T_25 @[axi4_to_ahb.scala 145:15] + node _T_26 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 146:32] + master_byteen <= _T_26 @[axi4_to_ahb.scala 146:17] + node _T_27 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 147:29] + master_wdata <= _T_27 @[axi4_to_ahb.scala 147:16] + node _T_28 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 150:33] + node _T_29 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 150:58] + node _T_30 = and(_T_28, _T_29) @[axi4_to_ahb.scala 150:47] + io.axi.b.valid <= _T_30 @[axi4_to_ahb.scala 150:18] + node _T_31 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 151:38] + node _T_32 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 151:65] + node _T_33 = mux(_T_32, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 151:55] + node _T_34 = mux(_T_31, UInt<2>("h02"), _T_33) @[axi4_to_ahb.scala 151:28] + io.axi.b.bits.resp <= _T_34 @[axi4_to_ahb.scala 151:22] + node _T_35 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 152:32] + io.axi.b.bits.id <= _T_35 @[axi4_to_ahb.scala 152:20] + node _T_36 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 154:33] + node _T_37 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 154:59] + node _T_38 = eq(_T_37, UInt<1>("h00")) @[axi4_to_ahb.scala 154:66] + node _T_39 = and(_T_36, _T_38) @[axi4_to_ahb.scala 154:47] + io.axi.r.valid <= _T_39 @[axi4_to_ahb.scala 154:18] + node _T_40 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 155:38] + node _T_41 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 155:65] + node _T_42 = mux(_T_41, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 155:55] + node _T_43 = mux(_T_40, UInt<2>("h02"), _T_42) @[axi4_to_ahb.scala 155:28] + io.axi.r.bits.resp <= _T_43 @[axi4_to_ahb.scala 155:22] + node _T_44 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 156:32] + io.axi.r.bits.id <= _T_44 @[axi4_to_ahb.scala 156:20] + node _T_45 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 157:36] + io.axi.r.bits.data <= _T_45 @[axi4_to_ahb.scala 157:22] + node _T_46 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 158:33] + slave_ready <= _T_46 @[axi4_to_ahb.scala 158:15] + node _T_47 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] + when _T_47 : @[Conditional.scala 40:58] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 162:20] + node _T_48 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 163:34] + node _T_49 = eq(_T_48, UInt<1>("h01")) @[axi4_to_ahb.scala 163:41] + buf_write_in <= _T_49 @[axi4_to_ahb.scala 163:20] + node _T_50 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 164:46] + node _T_51 = mux(_T_50, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 164:26] + buf_nxtstate <= _T_51 @[axi4_to_ahb.scala 164:20] + node _T_52 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 165:36] + buf_state_en <= _T_52 @[axi4_to_ahb.scala 165:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 166:17] + node _T_53 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 167:54] + node _T_54 = and(buf_state_en, _T_53) @[axi4_to_ahb.scala 167:38] + buf_data_wr_en <= _T_54 @[axi4_to_ahb.scala 167:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 168:27] + node _T_55 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 170:50] + node _T_56 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 170:94] + node _T_57 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] + node _T_58 = tail(_T_57, 1) @[axi4_to_ahb.scala 136:52] + node _T_59 = mux(UInt<1>("h00"), _T_58, UInt<3>("h00")) @[axi4_to_ahb.scala 136:24] + node _T_60 = bits(_T_56, 0, 0) @[axi4_to_ahb.scala 137:44] + node _T_61 = geq(UInt<1>("h00"), _T_59) @[axi4_to_ahb.scala 137:62] + node _T_62 = and(_T_60, _T_61) @[axi4_to_ahb.scala 137:48] + node _T_63 = bits(_T_56, 1, 1) @[axi4_to_ahb.scala 137:44] + node _T_64 = geq(UInt<1>("h01"), _T_59) @[axi4_to_ahb.scala 137:62] + node _T_65 = and(_T_63, _T_64) @[axi4_to_ahb.scala 137:48] + node _T_66 = bits(_T_56, 2, 2) @[axi4_to_ahb.scala 137:44] + node _T_67 = geq(UInt<2>("h02"), _T_59) @[axi4_to_ahb.scala 137:62] + node _T_68 = and(_T_66, _T_67) @[axi4_to_ahb.scala 137:48] + node _T_69 = bits(_T_56, 3, 3) @[axi4_to_ahb.scala 137:44] + node _T_70 = geq(UInt<2>("h03"), _T_59) @[axi4_to_ahb.scala 137:62] + node _T_71 = and(_T_69, _T_70) @[axi4_to_ahb.scala 137:48] + node _T_72 = bits(_T_56, 4, 4) @[axi4_to_ahb.scala 137:44] + node _T_73 = geq(UInt<3>("h04"), _T_59) @[axi4_to_ahb.scala 137:62] + node _T_74 = and(_T_72, _T_73) @[axi4_to_ahb.scala 137:48] + node _T_75 = bits(_T_56, 5, 5) @[axi4_to_ahb.scala 137:44] + node _T_76 = geq(UInt<3>("h05"), _T_59) @[axi4_to_ahb.scala 137:62] + node _T_77 = and(_T_75, _T_76) @[axi4_to_ahb.scala 137:48] + node _T_78 = bits(_T_56, 6, 6) @[axi4_to_ahb.scala 137:44] + node _T_79 = geq(UInt<3>("h06"), _T_59) @[axi4_to_ahb.scala 137:62] + node _T_80 = and(_T_78, _T_79) @[axi4_to_ahb.scala 137:48] + node _T_81 = bits(_T_56, 7, 7) @[axi4_to_ahb.scala 137:44] + node _T_82 = geq(UInt<3>("h07"), _T_59) @[axi4_to_ahb.scala 137:62] + node _T_83 = and(_T_81, _T_82) @[axi4_to_ahb.scala 137:48] + node _T_84 = mux(_T_83, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_85 = mux(_T_80, UInt<3>("h06"), _T_84) @[Mux.scala 98:16] + node _T_86 = mux(_T_77, UInt<3>("h05"), _T_85) @[Mux.scala 98:16] + node _T_87 = mux(_T_74, UInt<3>("h04"), _T_86) @[Mux.scala 98:16] + node _T_88 = mux(_T_71, UInt<2>("h03"), _T_87) @[Mux.scala 98:16] + node _T_89 = mux(_T_68, UInt<2>("h02"), _T_88) @[Mux.scala 98:16] + node _T_90 = mux(_T_65, UInt<1>("h01"), _T_89) @[Mux.scala 98:16] + node _T_91 = mux(_T_62, UInt<1>("h00"), _T_90) @[Mux.scala 98:16] + node _T_92 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 170:124] + node _T_93 = mux(_T_55, _T_91, _T_92) @[axi4_to_ahb.scala 170:30] + buf_cmd_byte_ptr <= _T_93 @[axi4_to_ahb.scala 170:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 171:17] + node _T_94 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 172:51] + node _T_95 = and(bypass_en, _T_94) @[axi4_to_ahb.scala 172:35] + rd_bypass_idle <= _T_95 @[axi4_to_ahb.scala 172:22] + node _T_96 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] + node _T_97 = mux(_T_96, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_98 = and(_T_97, UInt<2>("h02")) @[axi4_to_ahb.scala 173:49] + io.ahb.out.htrans <= _T_98 @[axi4_to_ahb.scala 173:25] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_99 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] + when _T_99 : @[Conditional.scala 39:67] + node _T_100 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 177:54] + node _T_101 = eq(_T_100, UInt<1>("h00")) @[axi4_to_ahb.scala 177:61] + node _T_102 = and(master_valid, _T_101) @[axi4_to_ahb.scala 177:41] + node _T_103 = bits(_T_102, 0, 0) @[axi4_to_ahb.scala 177:82] + node _T_104 = mux(_T_103, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 177:26] + buf_nxtstate <= _T_104 @[axi4_to_ahb.scala 177:20] + node _T_105 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 178:51] + node _T_106 = neq(_T_105, UInt<1>("h00")) @[axi4_to_ahb.scala 178:58] + node _T_107 = and(ahb_hready_q, _T_106) @[axi4_to_ahb.scala 178:36] + node _T_108 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 178:72] + node _T_109 = and(_T_107, _T_108) @[axi4_to_ahb.scala 178:70] + buf_state_en <= _T_109 @[axi4_to_ahb.scala 178:20] + node _T_110 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 179:34] + node _T_111 = and(buf_state_en, _T_110) @[axi4_to_ahb.scala 179:32] + cmd_done <= _T_111 @[axi4_to_ahb.scala 179:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 180:20] + node _T_112 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 181:52] + node _T_113 = neq(_T_112, UInt<1>("h00")) @[axi4_to_ahb.scala 181:59] + node _T_114 = and(ahb_hready_q, _T_113) @[axi4_to_ahb.scala 181:37] + node _T_115 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 181:73] + node _T_116 = and(_T_114, _T_115) @[axi4_to_ahb.scala 181:71] + node _T_117 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 181:122] + node _T_118 = eq(_T_117, UInt<1>("h00")) @[axi4_to_ahb.scala 181:129] + node _T_119 = and(master_valid, _T_118) @[axi4_to_ahb.scala 181:109] + node _T_120 = bits(_T_119, 0, 0) @[axi4_to_ahb.scala 181:150] + node _T_121 = mux(_T_120, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 181:94] + node _T_122 = eq(_T_121, UInt<3>("h06")) @[axi4_to_ahb.scala 181:174] + node _T_123 = and(_T_116, _T_122) @[axi4_to_ahb.scala 181:88] + master_ready <= _T_123 @[axi4_to_ahb.scala 181:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 182:17] + node _T_124 = and(master_ready, master_valid) @[axi4_to_ahb.scala 183:33] + bypass_en <= _T_124 @[axi4_to_ahb.scala 183:17] + node _T_125 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 184:47] + node _T_126 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 184:62] + node _T_127 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 184:78] + node _T_128 = mux(_T_125, _T_126, _T_127) @[axi4_to_ahb.scala 184:30] + buf_cmd_byte_ptr <= _T_128 @[axi4_to_ahb.scala 184:24] + node _T_129 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 185:48] + node _T_130 = or(_T_129, bypass_en) @[axi4_to_ahb.scala 185:62] + node _T_131 = bits(_T_130, 0, 0) @[Bitwise.scala 72:15] + node _T_132 = mux(_T_131, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_133 = and(UInt<2>("h02"), _T_132) @[axi4_to_ahb.scala 185:36] + io.ahb.out.htrans <= _T_133 @[axi4_to_ahb.scala 185:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_134 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] + when _T_134 : @[Conditional.scala 39:67] + node _T_135 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 189:39] + node _T_136 = and(ahb_hready_q, _T_135) @[axi4_to_ahb.scala 189:37] + node _T_137 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 189:82] + node _T_138 = eq(_T_137, UInt<1>("h01")) @[axi4_to_ahb.scala 189:89] + node _T_139 = and(master_valid, _T_138) @[axi4_to_ahb.scala 189:70] + node _T_140 = not(_T_139) @[axi4_to_ahb.scala 189:55] + node _T_141 = and(_T_136, _T_140) @[axi4_to_ahb.scala 189:53] + master_ready <= _T_141 @[axi4_to_ahb.scala 189:20] + node _T_142 = and(master_valid, master_ready) @[axi4_to_ahb.scala 190:34] + node _T_143 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 190:62] + node _T_144 = eq(_T_143, UInt<1>("h00")) @[axi4_to_ahb.scala 190:69] + node _T_145 = and(_T_142, _T_144) @[axi4_to_ahb.scala 190:49] + buf_wr_en <= _T_145 @[axi4_to_ahb.scala 190:17] + node _T_146 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 191:45] + node _T_147 = and(master_valid, master_ready) @[axi4_to_ahb.scala 191:82] + node _T_148 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 191:110] + node _T_149 = eq(_T_148, UInt<1>("h00")) @[axi4_to_ahb.scala 191:117] + node _T_150 = and(_T_147, _T_149) @[axi4_to_ahb.scala 191:97] + node _T_151 = bits(_T_150, 0, 0) @[axi4_to_ahb.scala 191:138] + node _T_152 = mux(_T_151, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 191:67] + node _T_153 = mux(_T_146, UInt<3>("h07"), _T_152) @[axi4_to_ahb.scala 191:26] + buf_nxtstate <= _T_153 @[axi4_to_ahb.scala 191:20] + node _T_154 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 192:37] + buf_state_en <= _T_154 @[axi4_to_ahb.scala 192:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 193:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 194:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 195:23] + node _T_155 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 196:41] + node _T_156 = and(buf_state_en, _T_155) @[axi4_to_ahb.scala 196:39] + slave_valid_pre <= _T_156 @[axi4_to_ahb.scala 196:23] + node _T_157 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 197:34] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 197:32] + cmd_done <= _T_158 @[axi4_to_ahb.scala 197:16] + node _T_159 = and(master_ready, master_valid) @[axi4_to_ahb.scala 198:33] + node _T_160 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 198:64] + node _T_161 = and(_T_159, _T_160) @[axi4_to_ahb.scala 198:48] + node _T_162 = and(_T_161, buf_state_en) @[axi4_to_ahb.scala 198:79] + bypass_en <= _T_162 @[axi4_to_ahb.scala 198:17] + node _T_163 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 199:47] + node _T_164 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 199:62] + node _T_165 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 199:78] + node _T_166 = mux(_T_163, _T_164, _T_165) @[axi4_to_ahb.scala 199:30] + buf_cmd_byte_ptr <= _T_166 @[axi4_to_ahb.scala 199:24] + node _T_167 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 200:63] + node _T_168 = and(_T_167, buf_state_en) @[axi4_to_ahb.scala 200:78] + node _T_169 = eq(_T_168, UInt<1>("h00")) @[axi4_to_ahb.scala 200:47] + node _T_170 = bits(_T_169, 0, 0) @[Bitwise.scala 72:15] + node _T_171 = mux(_T_170, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_172 = and(UInt<2>("h02"), _T_171) @[axi4_to_ahb.scala 200:36] + io.ahb.out.htrans <= _T_172 @[axi4_to_ahb.scala 200:25] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 201:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_173 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] + when _T_173 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 205:20] + node _T_174 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 206:51] + node _T_175 = neq(_T_174, UInt<1>("h00")) @[axi4_to_ahb.scala 206:58] + node _T_176 = and(ahb_hready_q, _T_175) @[axi4_to_ahb.scala 206:36] + node _T_177 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 206:72] + node _T_178 = and(_T_176, _T_177) @[axi4_to_ahb.scala 206:70] + buf_state_en <= _T_178 @[axi4_to_ahb.scala 206:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 207:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 208:20] + node _T_179 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 209:35] + buf_cmd_byte_ptr <= _T_179 @[axi4_to_ahb.scala 209:24] + node _T_180 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 210:51] + node _T_181 = bits(_T_180, 0, 0) @[Bitwise.scala 72:15] + node _T_182 = mux(_T_181, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_183 = and(UInt<2>("h02"), _T_182) @[axi4_to_ahb.scala 210:41] + io.ahb.out.htrans <= _T_183 @[axi4_to_ahb.scala 210:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_184 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] + when _T_184 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 214:20] + node _T_185 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 215:37] + buf_state_en <= _T_185 @[axi4_to_ahb.scala 215:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 216:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 217:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 218:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 219:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_186 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] + when _T_186 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 223:20] + node _T_187 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 224:33] + node _T_188 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 224:63] + node _T_189 = neq(_T_188, UInt<1>("h00")) @[axi4_to_ahb.scala 224:70] + node _T_190 = and(_T_187, _T_189) @[axi4_to_ahb.scala 224:48] + trxn_done <= _T_190 @[axi4_to_ahb.scala 224:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 225:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 226:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 227:20] + node _T_191 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 228:47] + node _T_192 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 228:85] + node _T_193 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 228:103] + node _T_194 = add(_T_192, UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] + node _T_195 = tail(_T_194, 1) @[axi4_to_ahb.scala 136:52] + node _T_196 = mux(UInt<1>("h01"), _T_195, _T_192) @[axi4_to_ahb.scala 136:24] + node _T_197 = bits(_T_193, 0, 0) @[axi4_to_ahb.scala 137:44] + node _T_198 = geq(UInt<1>("h00"), _T_196) @[axi4_to_ahb.scala 137:62] + node _T_199 = and(_T_197, _T_198) @[axi4_to_ahb.scala 137:48] + node _T_200 = bits(_T_193, 1, 1) @[axi4_to_ahb.scala 137:44] + node _T_201 = geq(UInt<1>("h01"), _T_196) @[axi4_to_ahb.scala 137:62] + node _T_202 = and(_T_200, _T_201) @[axi4_to_ahb.scala 137:48] + node _T_203 = bits(_T_193, 2, 2) @[axi4_to_ahb.scala 137:44] + node _T_204 = geq(UInt<2>("h02"), _T_196) @[axi4_to_ahb.scala 137:62] + node _T_205 = and(_T_203, _T_204) @[axi4_to_ahb.scala 137:48] + node _T_206 = bits(_T_193, 3, 3) @[axi4_to_ahb.scala 137:44] + node _T_207 = geq(UInt<2>("h03"), _T_196) @[axi4_to_ahb.scala 137:62] + node _T_208 = and(_T_206, _T_207) @[axi4_to_ahb.scala 137:48] + node _T_209 = bits(_T_193, 4, 4) @[axi4_to_ahb.scala 137:44] + node _T_210 = geq(UInt<3>("h04"), _T_196) @[axi4_to_ahb.scala 137:62] + node _T_211 = and(_T_209, _T_210) @[axi4_to_ahb.scala 137:48] + node _T_212 = bits(_T_193, 5, 5) @[axi4_to_ahb.scala 137:44] + node _T_213 = geq(UInt<3>("h05"), _T_196) @[axi4_to_ahb.scala 137:62] + node _T_214 = and(_T_212, _T_213) @[axi4_to_ahb.scala 137:48] + node _T_215 = bits(_T_193, 6, 6) @[axi4_to_ahb.scala 137:44] + node _T_216 = geq(UInt<3>("h06"), _T_196) @[axi4_to_ahb.scala 137:62] + node _T_217 = and(_T_215, _T_216) @[axi4_to_ahb.scala 137:48] + node _T_218 = bits(_T_193, 7, 7) @[axi4_to_ahb.scala 137:44] + node _T_219 = geq(UInt<3>("h07"), _T_196) @[axi4_to_ahb.scala 137:62] + node _T_220 = and(_T_218, _T_219) @[axi4_to_ahb.scala 137:48] + node _T_221 = mux(_T_220, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_222 = mux(_T_217, UInt<3>("h06"), _T_221) @[Mux.scala 98:16] + node _T_223 = mux(_T_214, UInt<3>("h05"), _T_222) @[Mux.scala 98:16] + node _T_224 = mux(_T_211, UInt<3>("h04"), _T_223) @[Mux.scala 98:16] + node _T_225 = mux(_T_208, UInt<2>("h03"), _T_224) @[Mux.scala 98:16] + node _T_226 = mux(_T_205, UInt<2>("h02"), _T_225) @[Mux.scala 98:16] + node _T_227 = mux(_T_202, UInt<1>("h01"), _T_226) @[Mux.scala 98:16] + node _T_228 = mux(_T_199, UInt<1>("h00"), _T_227) @[Mux.scala 98:16] + node _T_229 = mux(_T_191, _T_228, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 228:30] + buf_cmd_byte_ptr <= _T_229 @[axi4_to_ahb.scala 228:24] + node _T_230 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 229:65] + node _T_231 = or(buf_aligned, _T_230) @[axi4_to_ahb.scala 229:44] + node _T_232 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 229:127] + node _T_233 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 229:145] + node _T_234 = add(_T_232, UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] + node _T_235 = tail(_T_234, 1) @[axi4_to_ahb.scala 136:52] + node _T_236 = mux(UInt<1>("h01"), _T_235, _T_232) @[axi4_to_ahb.scala 136:24] + node _T_237 = bits(_T_233, 0, 0) @[axi4_to_ahb.scala 137:44] + node _T_238 = geq(UInt<1>("h00"), _T_236) @[axi4_to_ahb.scala 137:62] + node _T_239 = and(_T_237, _T_238) @[axi4_to_ahb.scala 137:48] + node _T_240 = bits(_T_233, 1, 1) @[axi4_to_ahb.scala 137:44] + node _T_241 = geq(UInt<1>("h01"), _T_236) @[axi4_to_ahb.scala 137:62] + node _T_242 = and(_T_240, _T_241) @[axi4_to_ahb.scala 137:48] + node _T_243 = bits(_T_233, 2, 2) @[axi4_to_ahb.scala 137:44] + node _T_244 = geq(UInt<2>("h02"), _T_236) @[axi4_to_ahb.scala 137:62] + node _T_245 = and(_T_243, _T_244) @[axi4_to_ahb.scala 137:48] + node _T_246 = bits(_T_233, 3, 3) @[axi4_to_ahb.scala 137:44] + node _T_247 = geq(UInt<2>("h03"), _T_236) @[axi4_to_ahb.scala 137:62] + node _T_248 = and(_T_246, _T_247) @[axi4_to_ahb.scala 137:48] + node _T_249 = bits(_T_233, 4, 4) @[axi4_to_ahb.scala 137:44] + node _T_250 = geq(UInt<3>("h04"), _T_236) @[axi4_to_ahb.scala 137:62] + node _T_251 = and(_T_249, _T_250) @[axi4_to_ahb.scala 137:48] + node _T_252 = bits(_T_233, 5, 5) @[axi4_to_ahb.scala 137:44] + node _T_253 = geq(UInt<3>("h05"), _T_236) @[axi4_to_ahb.scala 137:62] + node _T_254 = and(_T_252, _T_253) @[axi4_to_ahb.scala 137:48] + node _T_255 = bits(_T_233, 6, 6) @[axi4_to_ahb.scala 137:44] + node _T_256 = geq(UInt<3>("h06"), _T_236) @[axi4_to_ahb.scala 137:62] + node _T_257 = and(_T_255, _T_256) @[axi4_to_ahb.scala 137:48] + node _T_258 = bits(_T_233, 7, 7) @[axi4_to_ahb.scala 137:44] + node _T_259 = geq(UInt<3>("h07"), _T_236) @[axi4_to_ahb.scala 137:62] + node _T_260 = and(_T_258, _T_259) @[axi4_to_ahb.scala 137:48] + node _T_261 = mux(_T_260, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_262 = mux(_T_257, UInt<3>("h06"), _T_261) @[Mux.scala 98:16] + node _T_263 = mux(_T_254, UInt<3>("h05"), _T_262) @[Mux.scala 98:16] + node _T_264 = mux(_T_251, UInt<3>("h04"), _T_263) @[Mux.scala 98:16] + node _T_265 = mux(_T_248, UInt<2>("h03"), _T_264) @[Mux.scala 98:16] + node _T_266 = mux(_T_245, UInt<2>("h02"), _T_265) @[Mux.scala 98:16] + node _T_267 = mux(_T_242, UInt<1>("h01"), _T_266) @[Mux.scala 98:16] + node _T_268 = mux(_T_239, UInt<1>("h00"), _T_267) @[Mux.scala 98:16] + node _T_269 = dshr(buf_byteen, _T_268) @[axi4_to_ahb.scala 229:92] + node _T_270 = bits(_T_269, 0, 0) @[axi4_to_ahb.scala 229:92] + node _T_271 = eq(_T_270, UInt<1>("h00")) @[axi4_to_ahb.scala 229:163] + node _T_272 = or(_T_231, _T_271) @[axi4_to_ahb.scala 229:79] + node _T_273 = and(trxn_done, _T_272) @[axi4_to_ahb.scala 229:29] + cmd_done <= _T_273 @[axi4_to_ahb.scala 229:16] + node _T_274 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 230:47] + node _T_275 = eq(_T_274, UInt<1>("h00")) @[axi4_to_ahb.scala 230:36] + node _T_276 = bits(_T_275, 0, 0) @[Bitwise.scala 72:15] + node _T_277 = mux(_T_276, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_278 = and(_T_277, UInt<2>("h02")) @[axi4_to_ahb.scala 230:61] + io.ahb.out.htrans <= _T_278 @[axi4_to_ahb.scala 230:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_279 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] + when _T_279 : @[Conditional.scala 39:67] + node _T_280 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 234:34] + node _T_281 = or(_T_280, ahb_hresp_q) @[axi4_to_ahb.scala 234:50] + buf_state_en <= _T_281 @[axi4_to_ahb.scala 234:20] + node _T_282 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 235:38] + node _T_283 = and(buf_state_en, _T_282) @[axi4_to_ahb.scala 235:36] + node _T_284 = and(_T_283, slave_ready) @[axi4_to_ahb.scala 235:51] + master_ready <= _T_284 @[axi4_to_ahb.scala 235:20] + node _T_285 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 236:42] + node _T_286 = or(ahb_hresp_q, _T_285) @[axi4_to_ahb.scala 236:40] + node _T_287 = and(master_valid, master_valid) @[axi4_to_ahb.scala 236:81] + node _T_288 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 236:113] + node _T_289 = eq(_T_288, UInt<1>("h01")) @[axi4_to_ahb.scala 236:120] + node _T_290 = bits(_T_289, 0, 0) @[axi4_to_ahb.scala 236:135] + node _T_291 = mux(_T_290, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 236:101] + node _T_292 = mux(_T_287, _T_291, UInt<3>("h00")) @[axi4_to_ahb.scala 236:66] + node _T_293 = mux(_T_286, UInt<3>("h05"), _T_292) @[axi4_to_ahb.scala 236:26] + buf_nxtstate <= _T_293 @[axi4_to_ahb.scala 236:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 237:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 238:23] + node _T_294 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 239:33] + node _T_295 = eq(_T_294, UInt<1>("h01")) @[axi4_to_ahb.scala 239:40] + buf_write_in <= _T_295 @[axi4_to_ahb.scala 239:20] + node _T_296 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 240:50] + node _T_297 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 240:78] + node _T_298 = or(_T_296, _T_297) @[axi4_to_ahb.scala 240:62] + node _T_299 = and(buf_state_en, _T_298) @[axi4_to_ahb.scala 240:33] + buf_wr_en <= _T_299 @[axi4_to_ahb.scala 240:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 241:22] + node _T_300 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 242:63] + node _T_301 = neq(_T_300, UInt<1>("h00")) @[axi4_to_ahb.scala 242:70] + node _T_302 = and(ahb_hready_q, _T_301) @[axi4_to_ahb.scala 242:48] + node _T_303 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 243:29] + node _T_304 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 243:85] + node _T_305 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 243:103] + node _T_306 = add(_T_304, UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] + node _T_307 = tail(_T_306, 1) @[axi4_to_ahb.scala 136:52] + node _T_308 = mux(UInt<1>("h01"), _T_307, _T_304) @[axi4_to_ahb.scala 136:24] + node _T_309 = bits(_T_305, 0, 0) @[axi4_to_ahb.scala 137:44] + node _T_310 = geq(UInt<1>("h00"), _T_308) @[axi4_to_ahb.scala 137:62] + node _T_311 = and(_T_309, _T_310) @[axi4_to_ahb.scala 137:48] + node _T_312 = bits(_T_305, 1, 1) @[axi4_to_ahb.scala 137:44] + node _T_313 = geq(UInt<1>("h01"), _T_308) @[axi4_to_ahb.scala 137:62] + node _T_314 = and(_T_312, _T_313) @[axi4_to_ahb.scala 137:48] + node _T_315 = bits(_T_305, 2, 2) @[axi4_to_ahb.scala 137:44] + node _T_316 = geq(UInt<2>("h02"), _T_308) @[axi4_to_ahb.scala 137:62] + node _T_317 = and(_T_315, _T_316) @[axi4_to_ahb.scala 137:48] + node _T_318 = bits(_T_305, 3, 3) @[axi4_to_ahb.scala 137:44] + node _T_319 = geq(UInt<2>("h03"), _T_308) @[axi4_to_ahb.scala 137:62] + node _T_320 = and(_T_318, _T_319) @[axi4_to_ahb.scala 137:48] + node _T_321 = bits(_T_305, 4, 4) @[axi4_to_ahb.scala 137:44] + node _T_322 = geq(UInt<3>("h04"), _T_308) @[axi4_to_ahb.scala 137:62] + node _T_323 = and(_T_321, _T_322) @[axi4_to_ahb.scala 137:48] + node _T_324 = bits(_T_305, 5, 5) @[axi4_to_ahb.scala 137:44] + node _T_325 = geq(UInt<3>("h05"), _T_308) @[axi4_to_ahb.scala 137:62] + node _T_326 = and(_T_324, _T_325) @[axi4_to_ahb.scala 137:48] + node _T_327 = bits(_T_305, 6, 6) @[axi4_to_ahb.scala 137:44] + node _T_328 = geq(UInt<3>("h06"), _T_308) @[axi4_to_ahb.scala 137:62] + node _T_329 = and(_T_327, _T_328) @[axi4_to_ahb.scala 137:48] + node _T_330 = bits(_T_305, 7, 7) @[axi4_to_ahb.scala 137:44] + node _T_331 = geq(UInt<3>("h07"), _T_308) @[axi4_to_ahb.scala 137:62] + node _T_332 = and(_T_330, _T_331) @[axi4_to_ahb.scala 137:48] + node _T_333 = mux(_T_332, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_334 = mux(_T_329, UInt<3>("h06"), _T_333) @[Mux.scala 98:16] + node _T_335 = mux(_T_326, UInt<3>("h05"), _T_334) @[Mux.scala 98:16] + node _T_336 = mux(_T_323, UInt<3>("h04"), _T_335) @[Mux.scala 98:16] + node _T_337 = mux(_T_320, UInt<2>("h03"), _T_336) @[Mux.scala 98:16] + node _T_338 = mux(_T_317, UInt<2>("h02"), _T_337) @[Mux.scala 98:16] + node _T_339 = mux(_T_314, UInt<1>("h01"), _T_338) @[Mux.scala 98:16] + node _T_340 = mux(_T_311, UInt<1>("h00"), _T_339) @[Mux.scala 98:16] + node _T_341 = dshr(buf_byteen, _T_340) @[axi4_to_ahb.scala 243:51] + node _T_342 = bits(_T_341, 0, 0) @[axi4_to_ahb.scala 243:51] + node _T_343 = eq(_T_342, UInt<1>("h00")) @[axi4_to_ahb.scala 243:120] + node _T_344 = or(_T_303, _T_343) @[axi4_to_ahb.scala 243:38] + node _T_345 = and(_T_302, _T_344) @[axi4_to_ahb.scala 242:79] + node _T_346 = or(ahb_hresp_q, _T_345) @[axi4_to_ahb.scala 242:32] + cmd_done <= _T_346 @[axi4_to_ahb.scala 242:16] + node _T_347 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 244:33] + node _T_348 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 244:64] + node _T_349 = and(_T_347, _T_348) @[axi4_to_ahb.scala 244:48] + bypass_en <= _T_349 @[axi4_to_ahb.scala 244:17] + node _T_350 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 245:48] + node _T_351 = eq(_T_350, UInt<1>("h00")) @[axi4_to_ahb.scala 245:37] + node _T_352 = or(_T_351, bypass_en) @[axi4_to_ahb.scala 245:61] + node _T_353 = bits(_T_352, 0, 0) @[Bitwise.scala 72:15] + node _T_354 = mux(_T_353, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_355 = and(_T_354, UInt<2>("h02")) @[axi4_to_ahb.scala 245:75] + io.ahb.out.htrans <= _T_355 @[axi4_to_ahb.scala 245:25] + node _T_356 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 246:55] + node _T_357 = and(buf_state_en, _T_356) @[axi4_to_ahb.scala 246:39] + slave_valid_pre <= _T_357 @[axi4_to_ahb.scala 246:23] + node _T_358 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 247:33] + node _T_359 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 247:63] + node _T_360 = neq(_T_359, UInt<1>("h00")) @[axi4_to_ahb.scala 247:70] + node _T_361 = and(_T_358, _T_360) @[axi4_to_ahb.scala 247:48] + trxn_done <= _T_361 @[axi4_to_ahb.scala 247:17] + node _T_362 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 248:40] + buf_cmd_byte_ptr_en <= _T_362 @[axi4_to_ahb.scala 248:27] + node _T_363 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 249:81] + node _T_364 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] + node _T_365 = tail(_T_364, 1) @[axi4_to_ahb.scala 136:52] + node _T_366 = mux(UInt<1>("h00"), _T_365, UInt<3>("h00")) @[axi4_to_ahb.scala 136:24] + node _T_367 = bits(_T_363, 0, 0) @[axi4_to_ahb.scala 137:44] + node _T_368 = geq(UInt<1>("h00"), _T_366) @[axi4_to_ahb.scala 137:62] + node _T_369 = and(_T_367, _T_368) @[axi4_to_ahb.scala 137:48] + node _T_370 = bits(_T_363, 1, 1) @[axi4_to_ahb.scala 137:44] + node _T_371 = geq(UInt<1>("h01"), _T_366) @[axi4_to_ahb.scala 137:62] + node _T_372 = and(_T_370, _T_371) @[axi4_to_ahb.scala 137:48] + node _T_373 = bits(_T_363, 2, 2) @[axi4_to_ahb.scala 137:44] + node _T_374 = geq(UInt<2>("h02"), _T_366) @[axi4_to_ahb.scala 137:62] + node _T_375 = and(_T_373, _T_374) @[axi4_to_ahb.scala 137:48] + node _T_376 = bits(_T_363, 3, 3) @[axi4_to_ahb.scala 137:44] + node _T_377 = geq(UInt<2>("h03"), _T_366) @[axi4_to_ahb.scala 137:62] + node _T_378 = and(_T_376, _T_377) @[axi4_to_ahb.scala 137:48] + node _T_379 = bits(_T_363, 4, 4) @[axi4_to_ahb.scala 137:44] + node _T_380 = geq(UInt<3>("h04"), _T_366) @[axi4_to_ahb.scala 137:62] + node _T_381 = and(_T_379, _T_380) @[axi4_to_ahb.scala 137:48] + node _T_382 = bits(_T_363, 5, 5) @[axi4_to_ahb.scala 137:44] + node _T_383 = geq(UInt<3>("h05"), _T_366) @[axi4_to_ahb.scala 137:62] + node _T_384 = and(_T_382, _T_383) @[axi4_to_ahb.scala 137:48] + node _T_385 = bits(_T_363, 6, 6) @[axi4_to_ahb.scala 137:44] + node _T_386 = geq(UInt<3>("h06"), _T_366) @[axi4_to_ahb.scala 137:62] + node _T_387 = and(_T_385, _T_386) @[axi4_to_ahb.scala 137:48] + node _T_388 = bits(_T_363, 7, 7) @[axi4_to_ahb.scala 137:44] + node _T_389 = geq(UInt<3>("h07"), _T_366) @[axi4_to_ahb.scala 137:62] + node _T_390 = and(_T_388, _T_389) @[axi4_to_ahb.scala 137:48] + node _T_391 = mux(_T_390, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_392 = mux(_T_387, UInt<3>("h06"), _T_391) @[Mux.scala 98:16] + node _T_393 = mux(_T_384, UInt<3>("h05"), _T_392) @[Mux.scala 98:16] + node _T_394 = mux(_T_381, UInt<3>("h04"), _T_393) @[Mux.scala 98:16] + node _T_395 = mux(_T_378, UInt<2>("h03"), _T_394) @[Mux.scala 98:16] + node _T_396 = mux(_T_375, UInt<2>("h02"), _T_395) @[Mux.scala 98:16] + node _T_397 = mux(_T_372, UInt<1>("h01"), _T_396) @[Mux.scala 98:16] + node _T_398 = mux(_T_369, UInt<1>("h00"), _T_397) @[Mux.scala 98:16] + node _T_399 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 249:147] + node _T_400 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 249:165] + node _T_401 = add(_T_399, UInt<1>("h01")) @[axi4_to_ahb.scala 136:52] + node _T_402 = tail(_T_401, 1) @[axi4_to_ahb.scala 136:52] + node _T_403 = mux(UInt<1>("h01"), _T_402, _T_399) @[axi4_to_ahb.scala 136:24] + node _T_404 = bits(_T_400, 0, 0) @[axi4_to_ahb.scala 137:44] + node _T_405 = geq(UInt<1>("h00"), _T_403) @[axi4_to_ahb.scala 137:62] + node _T_406 = and(_T_404, _T_405) @[axi4_to_ahb.scala 137:48] + node _T_407 = bits(_T_400, 1, 1) @[axi4_to_ahb.scala 137:44] + node _T_408 = geq(UInt<1>("h01"), _T_403) @[axi4_to_ahb.scala 137:62] + node _T_409 = and(_T_407, _T_408) @[axi4_to_ahb.scala 137:48] + node _T_410 = bits(_T_400, 2, 2) @[axi4_to_ahb.scala 137:44] + node _T_411 = geq(UInt<2>("h02"), _T_403) @[axi4_to_ahb.scala 137:62] + node _T_412 = and(_T_410, _T_411) @[axi4_to_ahb.scala 137:48] + node _T_413 = bits(_T_400, 3, 3) @[axi4_to_ahb.scala 137:44] + node _T_414 = geq(UInt<2>("h03"), _T_403) @[axi4_to_ahb.scala 137:62] + node _T_415 = and(_T_413, _T_414) @[axi4_to_ahb.scala 137:48] + node _T_416 = bits(_T_400, 4, 4) @[axi4_to_ahb.scala 137:44] + node _T_417 = geq(UInt<3>("h04"), _T_403) @[axi4_to_ahb.scala 137:62] + node _T_418 = and(_T_416, _T_417) @[axi4_to_ahb.scala 137:48] + node _T_419 = bits(_T_400, 5, 5) @[axi4_to_ahb.scala 137:44] + node _T_420 = geq(UInt<3>("h05"), _T_403) @[axi4_to_ahb.scala 137:62] + node _T_421 = and(_T_419, _T_420) @[axi4_to_ahb.scala 137:48] + node _T_422 = bits(_T_400, 6, 6) @[axi4_to_ahb.scala 137:44] + node _T_423 = geq(UInt<3>("h06"), _T_403) @[axi4_to_ahb.scala 137:62] + node _T_424 = and(_T_422, _T_423) @[axi4_to_ahb.scala 137:48] + node _T_425 = bits(_T_400, 7, 7) @[axi4_to_ahb.scala 137:44] + node _T_426 = geq(UInt<3>("h07"), _T_403) @[axi4_to_ahb.scala 137:62] + node _T_427 = and(_T_425, _T_426) @[axi4_to_ahb.scala 137:48] + node _T_428 = mux(_T_427, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_429 = mux(_T_424, UInt<3>("h06"), _T_428) @[Mux.scala 98:16] + node _T_430 = mux(_T_421, UInt<3>("h05"), _T_429) @[Mux.scala 98:16] + node _T_431 = mux(_T_418, UInt<3>("h04"), _T_430) @[Mux.scala 98:16] + node _T_432 = mux(_T_415, UInt<2>("h03"), _T_431) @[Mux.scala 98:16] + node _T_433 = mux(_T_412, UInt<2>("h02"), _T_432) @[Mux.scala 98:16] + node _T_434 = mux(_T_409, UInt<1>("h01"), _T_433) @[Mux.scala 98:16] + node _T_435 = mux(_T_406, UInt<1>("h00"), _T_434) @[Mux.scala 98:16] + node _T_436 = mux(trxn_done, _T_435, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 249:102] + node _T_437 = mux(bypass_en, _T_398, _T_436) @[axi4_to_ahb.scala 249:30] + buf_cmd_byte_ptr <= _T_437 @[axi4_to_ahb.scala 249:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_438 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] + when _T_438 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 252:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 253:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 254:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 255:23] + skip @[Conditional.scala 39:67] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 259:16] + node _T_439 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 260:33] + node _T_440 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 260:75] + node _T_441 = eq(_T_440, UInt<1>("h01")) @[axi4_to_ahb.scala 260:82] + node _T_442 = and(buf_aligned_in, _T_441) @[axi4_to_ahb.scala 260:62] + node _T_443 = bits(_T_442, 0, 0) @[axi4_to_ahb.scala 260:102] + node _T_444 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 260:134] + node _T_445 = bits(_T_444, 7, 0) @[axi4_to_ahb.scala 127:50] + node _T_446 = eq(_T_445, UInt<8>("h0ff")) @[axi4_to_ahb.scala 127:57] + node _T_447 = bits(_T_444, 7, 0) @[axi4_to_ahb.scala 127:81] + node _T_448 = eq(_T_447, UInt<8>("h0f")) @[axi4_to_ahb.scala 127:88] + node _T_449 = or(_T_446, _T_448) @[axi4_to_ahb.scala 127:70] + node _T_450 = bits(_T_444, 7, 0) @[axi4_to_ahb.scala 127:117] + node _T_451 = eq(_T_450, UInt<8>("h03")) @[axi4_to_ahb.scala 127:124] + node _T_452 = or(_T_449, _T_451) @[axi4_to_ahb.scala 127:106] + node _T_453 = bits(_T_452, 0, 0) @[Bitwise.scala 72:15] + node _T_454 = mux(_T_453, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_455 = and(UInt<3>("h00"), _T_454) @[axi4_to_ahb.scala 127:29] + node _T_456 = bits(_T_444, 7, 0) @[axi4_to_ahb.scala 128:35] + node _T_457 = eq(_T_456, UInt<8>("h0c")) @[axi4_to_ahb.scala 128:42] + node _T_458 = bits(_T_457, 0, 0) @[Bitwise.scala 72:15] + node _T_459 = mux(_T_458, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_460 = and(UInt<2>("h02"), _T_459) @[axi4_to_ahb.scala 128:15] + node _T_461 = or(_T_455, _T_460) @[axi4_to_ahb.scala 127:146] + node _T_462 = bits(_T_444, 7, 0) @[axi4_to_ahb.scala 129:36] + node _T_463 = eq(_T_462, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:43] + node _T_464 = bits(_T_444, 7, 0) @[axi4_to_ahb.scala 129:67] + node _T_465 = eq(_T_464, UInt<8>("h03")) @[axi4_to_ahb.scala 129:74] + node _T_466 = or(_T_463, _T_465) @[axi4_to_ahb.scala 129:56] + node _T_467 = bits(_T_466, 0, 0) @[Bitwise.scala 72:15] + node _T_468 = mux(_T_467, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_469 = and(UInt<3>("h04"), _T_468) @[axi4_to_ahb.scala 129:15] + node _T_470 = or(_T_461, _T_469) @[axi4_to_ahb.scala 128:63] + node _T_471 = bits(_T_444, 7, 0) @[axi4_to_ahb.scala 130:35] + node _T_472 = eq(_T_471, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:42] + node _T_473 = bits(_T_472, 0, 0) @[Bitwise.scala 72:15] + node _T_474 = mux(_T_473, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_475 = and(UInt<3>("h06"), _T_474) @[axi4_to_ahb.scala 130:15] + node _T_476 = or(_T_470, _T_475) @[axi4_to_ahb.scala 129:96] + node _T_477 = bits(_T_444, 7, 0) @[axi4_to_ahb.scala 131:33] + node _T_478 = eq(_T_477, UInt<8>("h0c0")) @[axi4_to_ahb.scala 131:40] + node _T_479 = bits(_T_478, 0, 0) @[Bitwise.scala 72:15] + node _T_480 = mux(_T_479, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_481 = and(UInt<3>("h06"), _T_480) @[axi4_to_ahb.scala 131:13] + node _T_482 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 260:154] + node _T_483 = mux(_T_443, _T_476, _T_482) @[axi4_to_ahb.scala 260:45] + node _T_484 = cat(_T_439, _T_483) @[Cat.scala 29:58] + buf_addr_in <= _T_484 @[axi4_to_ahb.scala 260:15] + node _T_485 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 261:27] + buf_tag_in <= _T_485 @[axi4_to_ahb.scala 261:14] + node _T_486 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 262:32] + buf_byteen_in <= _T_486 @[axi4_to_ahb.scala 262:17] + node _T_487 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 263:33] + node _T_488 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 263:59] + node _T_489 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 263:80] + node _T_490 = mux(_T_487, _T_488, _T_489) @[axi4_to_ahb.scala 263:21] + buf_data_in <= _T_490 @[axi4_to_ahb.scala 263:15] + node _T_491 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 264:52] + node _T_492 = eq(_T_491, UInt<2>("h03")) @[axi4_to_ahb.scala 264:59] + node _T_493 = and(buf_aligned_in, _T_492) @[axi4_to_ahb.scala 264:38] + node _T_494 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 264:85] + node _T_495 = eq(_T_494, UInt<1>("h01")) @[axi4_to_ahb.scala 264:92] + node _T_496 = and(_T_493, _T_495) @[axi4_to_ahb.scala 264:72] + node _T_497 = bits(_T_496, 0, 0) @[axi4_to_ahb.scala 264:112] + node _T_498 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 264:144] + node _T_499 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 120:42] + node _T_500 = eq(_T_499, UInt<8>("h0ff")) @[axi4_to_ahb.scala 120:49] + node _T_501 = bits(_T_500, 0, 0) @[Bitwise.scala 72:15] + node _T_502 = mux(_T_501, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_503 = and(UInt<2>("h03"), _T_502) @[axi4_to_ahb.scala 120:25] + node _T_504 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 121:35] + node _T_505 = eq(_T_504, UInt<8>("h0f0")) @[axi4_to_ahb.scala 121:42] + node _T_506 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 121:64] + node _T_507 = eq(_T_506, UInt<8>("h0f")) @[axi4_to_ahb.scala 121:71] + node _T_508 = or(_T_505, _T_507) @[axi4_to_ahb.scala 121:55] + node _T_509 = bits(_T_508, 0, 0) @[Bitwise.scala 72:15] + node _T_510 = mux(_T_509, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_511 = and(UInt<2>("h02"), _T_510) @[axi4_to_ahb.scala 121:16] + node _T_512 = or(_T_503, _T_511) @[axi4_to_ahb.scala 120:64] + node _T_513 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 122:40] + node _T_514 = eq(_T_513, UInt<8>("h0c0")) @[axi4_to_ahb.scala 122:47] + node _T_515 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 122:69] + node _T_516 = eq(_T_515, UInt<6>("h030")) @[axi4_to_ahb.scala 122:76] + node _T_517 = or(_T_514, _T_516) @[axi4_to_ahb.scala 122:60] + node _T_518 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 122:98] + node _T_519 = eq(_T_518, UInt<8>("h0c")) @[axi4_to_ahb.scala 122:105] + node _T_520 = or(_T_517, _T_519) @[axi4_to_ahb.scala 122:89] + node _T_521 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 122:132] + node _T_522 = eq(_T_521, UInt<8>("h03")) @[axi4_to_ahb.scala 122:139] + node _T_523 = or(_T_520, _T_522) @[axi4_to_ahb.scala 122:123] + node _T_524 = bits(_T_523, 0, 0) @[Bitwise.scala 72:15] + node _T_525 = mux(_T_524, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_526 = and(UInt<2>("h01"), _T_525) @[axi4_to_ahb.scala 122:21] + node _T_527 = or(_T_512, _T_526) @[axi4_to_ahb.scala 121:93] + node _T_528 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 264:164] + node _T_529 = mux(_T_497, _T_527, _T_528) @[axi4_to_ahb.scala 264:21] + buf_size_in <= _T_529 @[axi4_to_ahb.scala 264:15] + node _T_530 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 265:32] + node _T_531 = eq(_T_530, UInt<1>("h00")) @[axi4_to_ahb.scala 265:39] + node _T_532 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 266:17] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 266:24] + node _T_534 = or(_T_531, _T_533) @[axi4_to_ahb.scala 265:48] + node _T_535 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 266:47] + node _T_536 = eq(_T_535, UInt<2>("h01")) @[axi4_to_ahb.scala 266:54] + node _T_537 = or(_T_534, _T_536) @[axi4_to_ahb.scala 266:33] + node _T_538 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 266:86] + node _T_539 = eq(_T_538, UInt<2>("h02")) @[axi4_to_ahb.scala 266:93] + node _T_540 = or(_T_537, _T_539) @[axi4_to_ahb.scala 266:72] + node _T_541 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 267:18] + node _T_542 = eq(_T_541, UInt<2>("h03")) @[axi4_to_ahb.scala 267:25] + node _T_543 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 267:55] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 267:62] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 267:90] + node _T_546 = eq(_T_545, UInt<4>("h0c")) @[axi4_to_ahb.scala 267:97] + node _T_547 = or(_T_544, _T_546) @[axi4_to_ahb.scala 267:74] + node _T_548 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 267:125] + node _T_549 = eq(_T_548, UInt<6>("h030")) @[axi4_to_ahb.scala 267:132] + node _T_550 = or(_T_547, _T_549) @[axi4_to_ahb.scala 267:109] + node _T_551 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 267:161] + node _T_552 = eq(_T_551, UInt<8>("h0c0")) @[axi4_to_ahb.scala 267:168] + node _T_553 = or(_T_550, _T_552) @[axi4_to_ahb.scala 267:145] + node _T_554 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 268:21] + node _T_555 = eq(_T_554, UInt<4>("h0f")) @[axi4_to_ahb.scala 268:28] + node _T_556 = or(_T_553, _T_555) @[axi4_to_ahb.scala 267:181] + node _T_557 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 268:56] + node _T_558 = eq(_T_557, UInt<8>("h0f0")) @[axi4_to_ahb.scala 268:63] + node _T_559 = or(_T_556, _T_558) @[axi4_to_ahb.scala 268:40] + node _T_560 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 268:92] + node _T_561 = eq(_T_560, UInt<8>("h0ff")) @[axi4_to_ahb.scala 268:99] + node _T_562 = or(_T_559, _T_561) @[axi4_to_ahb.scala 268:76] + node _T_563 = and(_T_542, _T_562) @[axi4_to_ahb.scala 267:38] + node _T_564 = or(_T_540, _T_563) @[axi4_to_ahb.scala 266:106] + buf_aligned_in <= _T_564 @[axi4_to_ahb.scala 265:18] + node _T_565 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 270:47] + node _T_566 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 270:62] + node _T_567 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 270:79] + node _T_568 = mux(_T_565, _T_566, _T_567) @[axi4_to_ahb.scala 270:30] + node _T_569 = eq(io.ahb.out.htrans, UInt<2>("h02")) @[axi4_to_ahb.scala 270:115] + node _T_570 = bits(_T_569, 0, 0) @[Bitwise.scala 72:15] + node _T_571 = mux(_T_570, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_572 = and(_T_571, buf_cmd_byte_ptr) @[axi4_to_ahb.scala 270:124] + node _T_573 = cat(_T_568, _T_572) @[Cat.scala 29:58] + io.ahb.out.haddr <= _T_573 @[axi4_to_ahb.scala 270:20] + node _T_574 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 271:43] + node _T_575 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] + node _T_576 = mux(_T_575, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_577 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 271:94] + node _T_578 = and(_T_576, _T_577) @[axi4_to_ahb.scala 271:81] + node _T_579 = cat(UInt<1>("h00"), _T_578) @[Cat.scala 29:58] + node _T_580 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] + node _T_581 = mux(_T_580, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_582 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 271:148] + node _T_583 = and(_T_581, _T_582) @[axi4_to_ahb.scala 271:138] + node _T_584 = cat(UInt<1>("h00"), _T_583) @[Cat.scala 29:58] + node _T_585 = mux(_T_574, _T_579, _T_584) @[axi4_to_ahb.scala 271:26] + io.ahb.out.hsize <= _T_585 @[axi4_to_ahb.scala 271:20] + io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 273:21] + io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 274:24] + node _T_586 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 275:57] + node _T_587 = eq(_T_586, UInt<1>("h00")) @[axi4_to_ahb.scala 275:37] + node _T_588 = cat(UInt<1>("h01"), _T_587) @[Cat.scala 29:58] + io.ahb.out.hprot <= _T_588 @[axi4_to_ahb.scala 275:20] + node _T_589 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 276:44] + node _T_590 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 276:59] + node _T_591 = eq(_T_590, UInt<1>("h01")) @[axi4_to_ahb.scala 276:66] + node _T_592 = mux(_T_589, _T_591, buf_write) @[axi4_to_ahb.scala 276:27] + io.ahb.out.hwrite <= _T_592 @[axi4_to_ahb.scala 276:21] + node _T_593 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 277:32] + io.ahb.out.hwdata <= _T_593 @[axi4_to_ahb.scala 277:21] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 279:15] + node _T_594 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 280:43] + node _T_595 = mux(_T_594, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 280:23] + node _T_596 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] + node _T_597 = mux(_T_596, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_598 = and(_T_597, UInt<2>("h02")) @[axi4_to_ahb.scala 280:88] + node _T_599 = cat(_T_595, _T_598) @[Cat.scala 29:58] + slave_opc <= _T_599 @[axi4_to_ahb.scala 280:13] + node _T_600 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 281:41] + node _T_601 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 281:66] + node _T_602 = cat(_T_601, _T_601) @[Cat.scala 29:58] + node _T_603 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 281:91] + node _T_604 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 281:110] + node _T_605 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 281:131] + node _T_606 = mux(_T_603, _T_604, _T_605) @[axi4_to_ahb.scala 281:79] + node _T_607 = mux(_T_600, _T_602, _T_606) @[axi4_to_ahb.scala 281:21] + slave_rdata <= _T_607 @[axi4_to_ahb.scala 281:15] + node _T_608 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 282:26] + slave_tag <= _T_608 @[axi4_to_ahb.scala 282:13] + node _T_609 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 284:37] + node _T_610 = neq(_T_609, UInt<1>("h00")) @[axi4_to_ahb.scala 284:44] + node _T_611 = and(_T_610, io.ahb.in.hready) @[axi4_to_ahb.scala 284:56] + node _T_612 = and(_T_611, io.ahb.out.hwrite) @[axi4_to_ahb.scala 284:75] + last_addr_en <= _T_612 @[axi4_to_ahb.scala 284:16] + node _T_613 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 286:31] + node _T_614 = and(_T_613, master_ready) @[axi4_to_ahb.scala 286:49] + wrbuf_en <= _T_614 @[axi4_to_ahb.scala 286:12] + node _T_615 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 287:35] + node _T_616 = and(_T_615, master_ready) @[axi4_to_ahb.scala 287:52] + wrbuf_data_en <= _T_616 @[axi4_to_ahb.scala 287:17] + node _T_617 = and(master_valid, master_ready) @[axi4_to_ahb.scala 288:34] + node _T_618 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 288:62] + node _T_619 = eq(_T_618, UInt<1>("h01")) @[axi4_to_ahb.scala 288:69] + node _T_620 = and(_T_617, _T_619) @[axi4_to_ahb.scala 288:49] + wrbuf_cmd_sent <= _T_620 @[axi4_to_ahb.scala 288:18] + node _T_621 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 289:34] + node _T_622 = and(wrbuf_cmd_sent, _T_621) @[axi4_to_ahb.scala 289:32] + node _T_623 = or(_T_622, dec_tlu_force_halt_bus) @[axi4_to_ahb.scala 289:45] + wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 289:13] + node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 291:36] + node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 291:34] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 291:22] + node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 291:53] + io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 291:19] + node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 292:40] + node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 292:38] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 292:21] + node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 292:57] + io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 292:18] + node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 293:34] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 293:22] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 293:52] + io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 293:19] + io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 294:22] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 296:49] + wire _T_636 : UInt @[lib.scala 389:21] + node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[lib.scala 391:75] + node _T_638 = and(UInt<1>("h01"), _T_637) @[lib.scala 391:53] + node _T_639 = or(_T_635, wrbuf_rst) @[lib.scala 391:95] + node _T_640 = and(_T_639, io.bus_clk_en) @[lib.scala 391:102] + node _T_641 = bits(_T_640, 0, 0) @[lib.scala 8:44] + reg _T_642 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_641 : @[Reg.scala 28:19] + _T_642 <= _T_638 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_636 <= _T_642 @[lib.scala 391:14] + wrbuf_vld <= _T_636 @[axi4_to_ahb.scala 296:13] + node _T_643 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 297:59] + wire _T_644 : UInt @[lib.scala 389:21] + node _T_645 = eq(wrbuf_rst, UInt<1>("h00")) @[lib.scala 391:75] + node _T_646 = and(UInt<1>("h01"), _T_645) @[lib.scala 391:53] + node _T_647 = or(_T_643, wrbuf_rst) @[lib.scala 391:95] + node _T_648 = and(_T_647, io.bus_clk_en) @[lib.scala 391:102] + node _T_649 = bits(_T_648, 0, 0) @[lib.scala 8:44] + reg _T_650 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_649 : @[Reg.scala 28:19] + _T_650 <= _T_646 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_644 <= _T_650 @[lib.scala 391:14] + wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 297:18] + node _T_651 = bits(io.axi.aw.bits.id, 0, 0) @[axi4_to_ahb.scala 298:45] + node _T_652 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 298:74] + node _T_653 = and(io.bus_clk_en, _T_652) @[lib.scala 383:57] + reg _T_654 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_653 : @[Reg.scala 28:19] + _T_654 <= _T_651 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_tag <= _T_654 @[axi4_to_ahb.scala 298:13] + node _T_655 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 299:48] + node _T_656 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 299:71] + node _T_657 = and(io.bus_clk_en, _T_656) @[lib.scala 383:57] + reg _T_658 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_657 : @[Reg.scala 28:19] + _T_658 <= _T_655 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_size <= _T_658 @[axi4_to_ahb.scala 299:14] + node _T_659 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 300:54] + node _T_660 = and(_T_659, io.bus_clk_en) @[axi4_to_ahb.scala 300:61] + inst rvclkhdr of rvclkhdr @[lib.scala 399:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 401:18] + rvclkhdr.io.en <= _T_660 @[lib.scala 402:17] + rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + reg _T_661 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_660 : @[Reg.scala 28:19] + _T_661 <= io.axi.aw.bits.addr @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_addr <= _T_661 @[axi4_to_ahb.scala 300:14] + node _T_662 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 301:58] + node _T_663 = and(_T_662, io.bus_clk_en) @[axi4_to_ahb.scala 301:65] + inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 399:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 401:18] + rvclkhdr_1.io.en <= _T_663 @[lib.scala 402:17] + rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + reg _T_664 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_663 : @[Reg.scala 28:19] + _T_664 <= io.axi.w.bits.data @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_data <= _T_664 @[axi4_to_ahb.scala 301:14] + node _T_665 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 302:49] + node _T_666 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 302:77] + node _T_667 = and(io.bus_clk_en, _T_666) @[lib.scala 383:57] + reg _T_668 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_667 : @[Reg.scala 28:19] + _T_668 <= _T_665 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_byteen <= _T_668 @[axi4_to_ahb.scala 302:16] + node _T_669 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 303:48] + node _T_670 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 303:76] + node _T_671 = and(io.bus_clk_en, _T_670) @[lib.scala 383:57] + reg _T_672 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_671 : @[Reg.scala 28:19] + _T_672 <= _T_669 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + last_bus_addr <= _T_672 @[axi4_to_ahb.scala 303:17] + node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 304:58] + node _T_674 = and(buf_clken, _T_673) @[lib.scala 383:57] + reg _T_675 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_674 : @[Reg.scala 28:19] + _T_675 <= buf_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_write <= _T_675 @[axi4_to_ahb.scala 304:13] + node _T_676 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 305:36] + node _T_677 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 305:66] + node _T_678 = and(buf_clken, _T_677) @[lib.scala 383:57] + reg _T_679 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_678 : @[Reg.scala 28:19] + _T_679 <= _T_676 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_tag <= _T_679 @[axi4_to_ahb.scala 305:11] + node _T_680 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 306:33] + node _T_681 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 306:53] + node _T_682 = bits(_T_681, 0, 0) @[axi4_to_ahb.scala 306:70] + inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 399:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 401:18] + rvclkhdr_2.io.en <= _T_682 @[lib.scala 402:17] + rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + reg _T_683 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_682 : @[Reg.scala 28:19] + _T_683 <= _T_680 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_addr <= _T_683 @[axi4_to_ahb.scala 306:12] + node _T_684 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 307:38] + node _T_685 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 307:62] + node _T_686 = and(buf_clken, _T_685) @[lib.scala 383:57] + reg _T_687 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_686 : @[Reg.scala 28:19] + _T_687 <= _T_684 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_size <= _T_687 @[axi4_to_ahb.scala 307:12] + node _T_688 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 308:62] + node _T_689 = and(buf_clken, _T_688) @[lib.scala 383:57] + reg _T_690 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_689 : @[Reg.scala 28:19] + _T_690 <= buf_aligned_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_aligned <= _T_690 @[axi4_to_ahb.scala 308:15] + node _T_691 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 309:42] + node _T_692 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 309:66] + node _T_693 = and(buf_clken, _T_692) @[lib.scala 383:57] + reg _T_694 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_693 : @[Reg.scala 28:19] + _T_694 <= _T_691 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_byteen <= _T_694 @[axi4_to_ahb.scala 309:14] + node _T_695 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 310:33] + node _T_696 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 310:58] + node _T_697 = bits(_T_696, 0, 0) @[axi4_to_ahb.scala 310:81] + inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 399:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[lib.scala 401:18] + rvclkhdr_3.io.en <= _T_697 @[lib.scala 402:17] + rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 403:24] + reg _T_698 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_697 : @[Reg.scala 28:19] + _T_698 <= _T_695 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_data <= _T_698 @[axi4_to_ahb.scala 310:12] + node _T_699 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 311:61] + node _T_700 = and(buf_clken, _T_699) @[lib.scala 383:57] + reg _T_701 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_700 : @[Reg.scala 28:19] + _T_701 <= buf_write @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_write <= _T_701 @[axi4_to_ahb.scala 311:16] + node _T_702 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 312:36] + node _T_703 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 312:69] + node _T_704 = and(buf_clken, _T_703) @[lib.scala 383:57] + reg _T_705 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_704 : @[Reg.scala 28:19] + _T_705 <= _T_702 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_tag <= _T_705 @[axi4_to_ahb.scala 312:14] + node _T_706 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 313:70] + node _T_707 = and(buf_clken, _T_706) @[lib.scala 383:57] + reg _T_708 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_707 : @[Reg.scala 28:19] + _T_708 <= slvbuf_error_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_error <= _T_708 @[axi4_to_ahb.scala 313:16] + node _T_709 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 314:49] + wire _T_710 : UInt @[lib.scala 389:21] + node _T_711 = eq(cmd_done_rst, UInt<1>("h00")) @[lib.scala 391:75] + node _T_712 = and(UInt<1>("h01"), _T_711) @[lib.scala 391:53] + node _T_713 = or(_T_709, cmd_done_rst) @[lib.scala 391:95] + node _T_714 = and(_T_713, io.bus_clk_en) @[lib.scala 391:102] + node _T_715 = bits(_T_714, 0, 0) @[lib.scala 8:44] + reg _T_716 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_715 : @[Reg.scala 28:19] + _T_716 <= _T_712 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + _T_710 <= _T_716 @[lib.scala 391:14] + cmd_doneQ <= _T_710 @[axi4_to_ahb.scala 314:13] + node _T_717 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 315:52] + node _T_718 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 315:86] + node _T_719 = and(io.bus_clk_en, _T_718) @[lib.scala 383:57] + reg _T_720 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_719 : @[Reg.scala 28:19] + _T_720 <= _T_717 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_cmd_byte_ptrQ <= _T_720 @[axi4_to_ahb.scala 315:21] + reg _T_721 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.bus_clk_en : @[Reg.scala 28:19] + _T_721 <= io.ahb.in.hready @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ahb_hready_q <= _T_721 @[axi4_to_ahb.scala 316:16] + node _T_722 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 317:47] + reg _T_723 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.bus_clk_en : @[Reg.scala 28:19] + _T_723 <= _T_722 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ahb_htrans_q <= _T_723 @[axi4_to_ahb.scala 317:16] + reg _T_724 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.bus_clk_en : @[Reg.scala 28:19] + _T_724 <= io.ahb.out.hwrite @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ahb_hwrite_q <= _T_724 @[axi4_to_ahb.scala 318:16] + reg _T_725 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when io.bus_clk_en : @[Reg.scala 28:19] + _T_725 <= io.ahb.in.hresp @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ahb_hresp_q <= _T_725 @[axi4_to_ahb.scala 319:15] + node _T_726 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 320:46] + reg _T_727 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ahbm_data_clken : @[Reg.scala 28:19] + _T_727 <= _T_726 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ahb_hrdata_q <= _T_727 @[axi4_to_ahb.scala 320:16] + node _T_728 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 321:43] + node _T_729 = or(_T_728, io.clk_override) @[axi4_to_ahb.scala 321:58] + node _T_730 = and(io.bus_clk_en, _T_729) @[axi4_to_ahb.scala 321:30] + buf_clken <= _T_730 @[axi4_to_ahb.scala 321:13] + node _T_731 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 322:50] + node _T_732 = or(_T_731, io.clk_override) @[axi4_to_ahb.scala 322:60] + node _T_733 = and(io.bus_clk_en, _T_732) @[axi4_to_ahb.scala 322:36] + ahbm_data_clken <= _T_733 @[axi4_to_ahb.scala 322:19] + node _T_734 = asClock(UInt<1>("h00")) @[axi4_to_ahb.scala 325:27] + bus_clk <= _T_734 @[axi4_to_ahb.scala 325:13] + node _T_735 = asClock(UInt<1>("h00")) @[axi4_to_ahb.scala 326:27] + buf_clk <= _T_735 @[axi4_to_ahb.scala 326:13] + node _T_736 = asClock(UInt<1>("h00")) @[axi4_to_ahb.scala 327:33] + ahbm_data_clk <= _T_736 @[axi4_to_ahb.scala 327:19] + diff --git a/axi4_to_ahb.v b/axi4_to_ahb.v new file mode 100644 index 00000000..429ec2e2 --- /dev/null +++ b/axi4_to_ahb.v @@ -0,0 +1,1036 @@ +module rvclkhdr( + input io_clk, + input io_en +); + wire clkhdr_Q; // @[lib.scala 334:26] + wire clkhdr_CK; // @[lib.scala 334:26] + wire clkhdr_EN; // @[lib.scala 334:26] + wire clkhdr_SE; // @[lib.scala 334:26] + gated_latch clkhdr ( // @[lib.scala 334:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign clkhdr_CK = io_clk; // @[lib.scala 336:18] + assign clkhdr_EN = io_en; // @[lib.scala 337:18] + assign clkhdr_SE = 1'h0; // @[lib.scala 338:18] +endmodule +module axi4_to_ahb( + input clock, + input reset, + input io_free_clk, + input io_scan_mode, + input io_bus_clk_en, + input io_clk_override, + input io_dec_tlu_force_halt, + output io_axi_aw_ready, + input io_axi_aw_valid, + input io_axi_aw_bits_id, + input [31:0] io_axi_aw_bits_addr, + input [3:0] io_axi_aw_bits_region, + input [7:0] io_axi_aw_bits_len, + input [2:0] io_axi_aw_bits_size, + input [1:0] io_axi_aw_bits_burst, + input io_axi_aw_bits_lock, + input [3:0] io_axi_aw_bits_cache, + input [2:0] io_axi_aw_bits_prot, + input [3:0] io_axi_aw_bits_qos, + output io_axi_w_ready, + input io_axi_w_valid, + input [63:0] io_axi_w_bits_data, + input [7:0] io_axi_w_bits_strb, + input io_axi_w_bits_last, + input io_axi_b_ready, + output io_axi_b_valid, + output [1:0] io_axi_b_bits_resp, + output io_axi_b_bits_id, + output io_axi_ar_ready, + input io_axi_ar_valid, + input io_axi_ar_bits_id, + input [31:0] io_axi_ar_bits_addr, + input [3:0] io_axi_ar_bits_region, + input [7:0] io_axi_ar_bits_len, + input [2:0] io_axi_ar_bits_size, + input [1:0] io_axi_ar_bits_burst, + input io_axi_ar_bits_lock, + input [3:0] io_axi_ar_bits_cache, + input [2:0] io_axi_ar_bits_prot, + input [3:0] io_axi_ar_bits_qos, + input io_axi_r_ready, + output io_axi_r_valid, + output io_axi_r_bits_id, + output [63:0] io_axi_r_bits_data, + output [1:0] io_axi_r_bits_resp, + output io_axi_r_bits_last, + input [63:0] io_ahb_in_hrdata, + input io_ahb_in_hready, + input io_ahb_in_hresp, + output [31:0] io_ahb_out_haddr, + output [2:0] io_ahb_out_hburst, + output io_ahb_out_hmastlock, + output [3:0] io_ahb_out_hprot, + output [2:0] io_ahb_out_hsize, + output [1:0] io_ahb_out_htrans, + output io_ahb_out_hwrite, + output [63:0] io_ahb_out_hwdata +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [63:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [63:0] _RAND_18; + reg [63:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_clk; // @[lib.scala 399:23] + wire rvclkhdr_io_en; // @[lib.scala 399:23] + wire rvclkhdr_1_io_clk; // @[lib.scala 399:23] + wire rvclkhdr_1_io_en; // @[lib.scala 399:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 399:23] + wire rvclkhdr_2_io_en; // @[lib.scala 399:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 399:23] + wire rvclkhdr_3_io_en; // @[lib.scala 399:23] + reg dec_tlu_force_halt_bus_q; // @[axi4_to_ahb.scala 26:62] + wire dec_tlu_force_halt_bus = io_dec_tlu_force_halt | dec_tlu_force_halt_bus_q; // @[axi4_to_ahb.scala 24:54] + wire _T = ~io_bus_clk_en; // @[axi4_to_ahb.scala 25:35] + reg [2:0] buf_state; // @[Reg.scala 27:20] + wire _T_47 = 3'h0 == buf_state; // @[Conditional.scala 37:30] + reg wrbuf_vld; // @[Reg.scala 27:20] + reg wrbuf_data_vld; // @[Reg.scala 27:20] + wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 140:27] + wire master_valid = wr_cmd_vld | io_axi_ar_valid; // @[axi4_to_ahb.scala 141:30] + wire _T_99 = 3'h1 == buf_state; // @[Conditional.scala 37:30] + reg ahb_hready_q; // @[Reg.scala 27:20] + reg [1:0] ahb_htrans_q; // @[Reg.scala 27:20] + wire _T_106 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 178:58] + wire _T_107 = ahb_hready_q & _T_106; // @[axi4_to_ahb.scala 178:36] + reg ahb_hwrite_q; // @[Reg.scala 27:20] + wire _T_108 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 178:72] + wire _T_109 = _T_107 & _T_108; // @[axi4_to_ahb.scala 178:70] + wire _T_134 = 3'h6 == buf_state; // @[Conditional.scala 37:30] + reg ahb_hresp_q; // @[Reg.scala 27:20] + wire _T_154 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 192:37] + wire _T_173 = 3'h7 == buf_state; // @[Conditional.scala 37:30] + wire _T_184 = 3'h3 == buf_state; // @[Conditional.scala 37:30] + wire _T_186 = 3'h2 == buf_state; // @[Conditional.scala 37:30] + wire _T_187 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 224:33] + wire _T_190 = _T_187 & _T_106; // @[axi4_to_ahb.scala 224:48] + wire _T_279 = 3'h4 == buf_state; // @[Conditional.scala 37:30] + wire _GEN_16 = _T_279 & _T_190; // @[Conditional.scala 39:67] + wire _GEN_20 = _T_186 ? _T_190 : _GEN_16; // @[Conditional.scala 39:67] + wire _GEN_41 = _T_184 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_173 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] + wire _GEN_80 = _T_134 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_96 = _T_99 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] + wire trxn_done = _T_47 ? 1'h0 : _GEN_96; // @[Conditional.scala 40:58] + reg cmd_doneQ; // @[Reg.scala 27:20] + wire _T_280 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 234:34] + wire _T_281 = _T_280 | ahb_hresp_q; // @[axi4_to_ahb.scala 234:50] + wire _T_438 = 3'h5 == buf_state; // @[Conditional.scala 37:30] + wire slave_ready = io_axi_b_ready & io_axi_r_ready; // @[axi4_to_ahb.scala 158:33] + wire _GEN_2 = _T_438 & slave_ready; // @[Conditional.scala 39:67] + wire _GEN_4 = _T_279 ? _T_281 : _GEN_2; // @[Conditional.scala 39:67] + wire _GEN_21 = _T_186 ? trxn_done : _GEN_4; // @[Conditional.scala 39:67] + wire _GEN_36 = _T_184 ? _T_154 : _GEN_21; // @[Conditional.scala 39:67] + wire _GEN_52 = _T_173 ? _T_109 : _GEN_36; // @[Conditional.scala 39:67] + wire _GEN_70 = _T_134 ? _T_154 : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_84 = _T_99 ? _T_109 : _GEN_70; // @[Conditional.scala 39:67] + wire buf_state_en = _T_47 ? master_valid : _GEN_84; // @[Conditional.scala 40:58] + wire _T_4 = ~dec_tlu_force_halt_bus; // @[lib.scala 391:75] + wire [1:0] _T_17 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 143:20] + wire [2:0] master_opc = {{1'd0}, _T_17}; // @[axi4_to_ahb.scala 143:14] + wire _T_49 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 163:41] + wire _GEN_9 = _T_279 & _T_49; // @[Conditional.scala 39:67] + wire _GEN_30 = _T_186 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] + wire _GEN_47 = _T_184 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_173 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] + wire _GEN_82 = _T_134 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67] + wire _GEN_98 = _T_99 ? 1'h0 : _GEN_82; // @[Conditional.scala 39:67] + wire buf_write_in = _T_47 ? _T_49 : _GEN_98; // @[Conditional.scala 40:58] + wire [2:0] _T_51 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 164:26] + wire _T_101 = master_opc == 3'h0; // @[axi4_to_ahb.scala 177:61] + wire _T_102 = master_valid & _T_101; // @[axi4_to_ahb.scala 177:41] + wire [2:0] _T_104 = _T_102 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 177:26] + wire _T_122 = _T_104 == 3'h6; // @[axi4_to_ahb.scala 181:174] + wire _T_123 = _T_109 & _T_122; // @[axi4_to_ahb.scala 181:88] + wire _T_135 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 189:39] + wire _T_136 = ahb_hready_q & _T_135; // @[axi4_to_ahb.scala 189:37] + wire _T_139 = master_valid & _T_49; // @[axi4_to_ahb.scala 189:70] + wire _T_140 = ~_T_139; // @[axi4_to_ahb.scala 189:55] + wire _T_141 = _T_136 & _T_140; // @[axi4_to_ahb.scala 189:53] + wire _T_283 = buf_state_en & _T_135; // @[axi4_to_ahb.scala 235:36] + wire _T_284 = _T_283 & slave_ready; // @[axi4_to_ahb.scala 235:51] + wire _GEN_5 = _T_279 & _T_284; // @[Conditional.scala 39:67] + wire _GEN_27 = _T_186 ? 1'h0 : _GEN_5; // @[Conditional.scala 39:67] + wire _GEN_46 = _T_184 ? 1'h0 : _GEN_27; // @[Conditional.scala 39:67] + wire _GEN_63 = _T_173 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_67 = _T_134 ? _T_141 : _GEN_63; // @[Conditional.scala 39:67] + wire _GEN_87 = _T_99 ? _T_123 : _GEN_67; // @[Conditional.scala 39:67] + wire master_ready = _T_47 | _GEN_87; // @[Conditional.scala 40:58] + wire _T_147 = master_valid & master_ready; // @[axi4_to_ahb.scala 191:82] + wire _T_150 = _T_147 & _T_101; // @[axi4_to_ahb.scala 191:97] + wire [2:0] _T_152 = _T_150 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 191:67] + wire [2:0] _T_153 = ahb_hresp_q ? 3'h7 : _T_152; // @[axi4_to_ahb.scala 191:26] + wire _T_285 = ~slave_ready; // @[axi4_to_ahb.scala 236:42] + wire _T_286 = ahb_hresp_q | _T_285; // @[axi4_to_ahb.scala 236:40] + wire [2:0] _T_291 = _T_49 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 236:101] + wire [2:0] _T_292 = master_valid ? _T_291 : 3'h0; // @[axi4_to_ahb.scala 236:66] + wire [2:0] _T_293 = _T_286 ? 3'h5 : _T_292; // @[axi4_to_ahb.scala 236:26] + wire [2:0] _GEN_6 = _T_279 ? _T_293 : 3'h0; // @[Conditional.scala 39:67] + wire [2:0] _GEN_19 = _T_186 ? 3'h4 : _GEN_6; // @[Conditional.scala 39:67] + wire [2:0] _GEN_35 = _T_184 ? 3'h5 : _GEN_19; // @[Conditional.scala 39:67] + wire [2:0] _GEN_51 = _T_173 ? 3'h3 : _GEN_35; // @[Conditional.scala 39:67] + wire [2:0] _GEN_69 = _T_134 ? _T_153 : _GEN_51; // @[Conditional.scala 39:67] + wire [2:0] _GEN_83 = _T_99 ? _T_104 : _GEN_69; // @[Conditional.scala 39:67] + wire [2:0] buf_nxtstate = _T_47 ? _T_51 : _GEN_83; // @[Conditional.scala 40:58] + wire [2:0] _GEN_141 = {{2'd0}, _T_4}; // @[lib.scala 391:53] + wire [2:0] _T_5 = buf_nxtstate & _GEN_141; // @[lib.scala 391:53] + wire _T_6 = buf_state_en | dec_tlu_force_halt_bus; // @[lib.scala 391:95] + wire _T_7 = _T_6 & io_bus_clk_en; // @[lib.scala 391:102] + reg wrbuf_tag; // @[Reg.scala 27:20] + reg [31:0] wrbuf_addr; // @[Reg.scala 27:20] + wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_ar_bits_addr; // @[axi4_to_ahb.scala 144:21] + reg [2:0] wrbuf_size; // @[Reg.scala 27:20] + wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 145:21] + reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] + reg [63:0] wrbuf_data; // @[Reg.scala 27:20] + wire _T_356 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 246:55] + wire _T_357 = buf_state_en & _T_356; // @[axi4_to_ahb.scala 246:39] + wire _GEN_15 = _T_279 ? _T_357 : _T_438; // @[Conditional.scala 39:67] + wire _GEN_34 = _T_186 ? 1'h0 : _GEN_15; // @[Conditional.scala 39:67] + wire _GEN_50 = _T_184 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_173 ? buf_state_en : _GEN_50; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_134 ? _T_283 : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_95 = _T_99 ? 1'h0 : _GEN_74; // @[Conditional.scala 39:67] + wire slave_valid_pre = _T_47 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] + wire _T_28 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 150:33] + reg slvbuf_write; // @[Reg.scala 27:20] + wire [1:0] _T_595 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 280:23] + reg slvbuf_error; // @[Reg.scala 27:20] + wire [1:0] _T_597 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_598 = _T_597 & 2'h2; // @[axi4_to_ahb.scala 280:88] + wire [3:0] slave_opc = {_T_595,_T_598}; // @[Cat.scala 29:58] + wire [1:0] _T_33 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 151:55] + reg slvbuf_tag; // @[Reg.scala 27:20] + wire _T_38 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 154:66] + reg [31:0] last_bus_addr; // @[Reg.scala 27:20] + wire [63:0] _T_602 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] + wire _T_603 = buf_state == 3'h5; // @[axi4_to_ahb.scala 281:91] + reg [63:0] buf_data; // @[Reg.scala 27:20] + reg [63:0] ahb_hrdata_q; // @[Reg.scala 27:20] + wire [63:0] _T_606 = _T_603 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 281:79] + wire _T_53 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 167:54] + wire _T_54 = buf_state_en & _T_53; // @[axi4_to_ahb.scala 167:38] + wire [2:0] _T_85 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16] + wire [2:0] _T_86 = wrbuf_byteen[5] ? 3'h5 : _T_85; // @[Mux.scala 98:16] + wire [2:0] _T_87 = wrbuf_byteen[4] ? 3'h4 : _T_86; // @[Mux.scala 98:16] + wire [2:0] _T_88 = wrbuf_byteen[3] ? 3'h3 : _T_87; // @[Mux.scala 98:16] + wire [2:0] _T_89 = wrbuf_byteen[2] ? 3'h2 : _T_88; // @[Mux.scala 98:16] + wire [2:0] _T_90 = wrbuf_byteen[1] ? 3'h1 : _T_89; // @[Mux.scala 98:16] + wire [2:0] _T_91 = wrbuf_byteen[0] ? 3'h0 : _T_90; // @[Mux.scala 98:16] + wire [2:0] _T_93 = buf_write_in ? _T_91 : master_addr[2:0]; // @[axi4_to_ahb.scala 170:30] + wire _T_94 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 172:51] + wire _T_124 = master_ready & master_valid; // @[axi4_to_ahb.scala 183:33] + wire _T_160 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 198:64] + wire _T_161 = _T_124 & _T_160; // @[axi4_to_ahb.scala 198:48] + wire _T_162 = _T_161 & buf_state_en; // @[axi4_to_ahb.scala 198:79] + wire _T_347 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 244:33] + wire _T_349 = _T_347 & _T_53; // @[axi4_to_ahb.scala 244:48] + wire _GEN_13 = _T_279 & _T_349; // @[Conditional.scala 39:67] + wire _GEN_33 = _T_186 ? 1'h0 : _GEN_13; // @[Conditional.scala 39:67] + wire _GEN_49 = _T_184 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_173 ? 1'h0 : _GEN_49; // @[Conditional.scala 39:67] + wire _GEN_76 = _T_134 ? _T_162 : _GEN_66; // @[Conditional.scala 39:67] + wire _GEN_89 = _T_99 ? _T_124 : _GEN_76; // @[Conditional.scala 39:67] + wire bypass_en = _T_47 ? buf_state_en : _GEN_89; // @[Conditional.scala 40:58] + wire [1:0] _T_97 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_98 = _T_97 & 2'h2; // @[axi4_to_ahb.scala 173:49] + wire _T_110 = ~master_valid; // @[axi4_to_ahb.scala 179:34] + wire _T_111 = buf_state_en & _T_110; // @[axi4_to_ahb.scala 179:32] + reg [31:0] buf_addr; // @[Reg.scala 27:20] + wire [2:0] _T_128 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 184:30] + wire _T_129 = ~buf_state_en; // @[axi4_to_ahb.scala 185:48] + wire _T_130 = _T_129 | bypass_en; // @[axi4_to_ahb.scala 185:62] + wire [1:0] _T_132 = _T_130 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_133 = 2'h2 & _T_132; // @[axi4_to_ahb.scala 185:36] + wire _T_167 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 200:63] + wire _T_168 = _T_167 & buf_state_en; // @[axi4_to_ahb.scala 200:78] + wire _T_169 = ~_T_168; // @[axi4_to_ahb.scala 200:47] + wire [1:0] _T_171 = _T_169 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_172 = 2'h2 & _T_171; // @[axi4_to_ahb.scala 200:36] + wire [1:0] _T_182 = _T_129 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_183 = 2'h2 & _T_182; // @[axi4_to_ahb.scala 210:41] + reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] + reg [7:0] buf_byteen; // @[Reg.scala 27:20] + wire [2:0] _T_195 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 136:52] + wire _T_198 = 3'h0 >= _T_195; // @[axi4_to_ahb.scala 137:62] + wire _T_199 = buf_byteen[0] & _T_198; // @[axi4_to_ahb.scala 137:48] + wire _T_201 = 3'h1 >= _T_195; // @[axi4_to_ahb.scala 137:62] + wire _T_202 = buf_byteen[1] & _T_201; // @[axi4_to_ahb.scala 137:48] + wire _T_204 = 3'h2 >= _T_195; // @[axi4_to_ahb.scala 137:62] + wire _T_205 = buf_byteen[2] & _T_204; // @[axi4_to_ahb.scala 137:48] + wire _T_207 = 3'h3 >= _T_195; // @[axi4_to_ahb.scala 137:62] + wire _T_208 = buf_byteen[3] & _T_207; // @[axi4_to_ahb.scala 137:48] + wire _T_210 = 3'h4 >= _T_195; // @[axi4_to_ahb.scala 137:62] + wire _T_211 = buf_byteen[4] & _T_210; // @[axi4_to_ahb.scala 137:48] + wire _T_213 = 3'h5 >= _T_195; // @[axi4_to_ahb.scala 137:62] + wire _T_214 = buf_byteen[5] & _T_213; // @[axi4_to_ahb.scala 137:48] + wire _T_216 = 3'h6 >= _T_195; // @[axi4_to_ahb.scala 137:62] + wire _T_217 = buf_byteen[6] & _T_216; // @[axi4_to_ahb.scala 137:48] + wire [2:0] _T_222 = _T_217 ? 3'h6 : 3'h7; // @[Mux.scala 98:16] + wire [2:0] _T_223 = _T_214 ? 3'h5 : _T_222; // @[Mux.scala 98:16] + wire [2:0] _T_224 = _T_211 ? 3'h4 : _T_223; // @[Mux.scala 98:16] + wire [2:0] _T_225 = _T_208 ? 3'h3 : _T_224; // @[Mux.scala 98:16] + wire [2:0] _T_226 = _T_205 ? 3'h2 : _T_225; // @[Mux.scala 98:16] + wire [2:0] _T_227 = _T_202 ? 3'h1 : _T_226; // @[Mux.scala 98:16] + wire [2:0] _T_228 = _T_199 ? 3'h0 : _T_227; // @[Mux.scala 98:16] + wire [2:0] _T_229 = trxn_done ? _T_228 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 228:30] + wire _T_230 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 229:65] + reg buf_aligned; // @[Reg.scala 27:20] + wire _T_231 = buf_aligned | _T_230; // @[axi4_to_ahb.scala 229:44] + wire [7:0] _T_269 = buf_byteen >> _T_228; // @[axi4_to_ahb.scala 229:92] + wire _T_271 = ~_T_269[0]; // @[axi4_to_ahb.scala 229:163] + wire _T_272 = _T_231 | _T_271; // @[axi4_to_ahb.scala 229:79] + wire _T_273 = trxn_done & _T_272; // @[axi4_to_ahb.scala 229:29] + wire _T_344 = _T_230 | _T_271; // @[axi4_to_ahb.scala 243:38] + wire _T_345 = _T_107 & _T_344; // @[axi4_to_ahb.scala 242:79] + wire _T_346 = ahb_hresp_q | _T_345; // @[axi4_to_ahb.scala 242:32] + wire _GEN_12 = _T_279 & _T_346; // @[Conditional.scala 39:67] + wire _GEN_25 = _T_186 ? _T_273 : _GEN_12; // @[Conditional.scala 39:67] + wire _GEN_44 = _T_184 ? 1'h0 : _GEN_25; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_173 ? 1'h0 : _GEN_44; // @[Conditional.scala 39:67] + wire _GEN_75 = _T_134 ? _T_111 : _GEN_62; // @[Conditional.scala 39:67] + wire _GEN_85 = _T_99 ? _T_111 : _GEN_75; // @[Conditional.scala 39:67] + wire cmd_done = _T_47 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] + wire _T_274 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 230:47] + wire _T_275 = ~_T_274; // @[axi4_to_ahb.scala 230:36] + wire [1:0] _T_277 = _T_275 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_278 = _T_277 & 2'h2; // @[axi4_to_ahb.scala 230:61] + wire _T_298 = _T_53 | _T_94; // @[axi4_to_ahb.scala 240:62] + wire _T_299 = buf_state_en & _T_298; // @[axi4_to_ahb.scala 240:33] + wire _T_352 = _T_275 | bypass_en; // @[axi4_to_ahb.scala 245:61] + wire [1:0] _T_354 = _T_352 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_355 = _T_354 & 2'h2; // @[axi4_to_ahb.scala 245:75] + wire _T_362 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 248:40] + wire [2:0] _T_437 = bypass_en ? _T_91 : _T_229; // @[axi4_to_ahb.scala 249:30] + wire _GEN_7 = _T_279 & ahb_hresp_q; // @[Conditional.scala 39:67] + wire _GEN_8 = _T_279 ? buf_state_en : _T_438; // @[Conditional.scala 39:67] + wire _GEN_10 = _T_279 & _T_299; // @[Conditional.scala 39:67] + wire _GEN_31 = _T_186 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] + wire _GEN_48 = _T_184 ? 1'h0 : _GEN_31; // @[Conditional.scala 39:67] + wire _GEN_65 = _T_173 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] + wire _GEN_68 = _T_134 ? _T_150 : _GEN_65; // @[Conditional.scala 39:67] + wire _GEN_88 = _T_99 ? master_ready : _GEN_68; // @[Conditional.scala 39:67] + wire buf_wr_en = _T_47 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] + wire _GEN_11 = _T_279 & buf_wr_en; // @[Conditional.scala 39:67] + wire [1:0] _GEN_14 = _T_279 ? _T_355 : 2'h0; // @[Conditional.scala 39:67] + wire _GEN_17 = _T_279 & _T_362; // @[Conditional.scala 39:67] + wire [2:0] _GEN_18 = _T_279 ? _T_437 : 3'h0; // @[Conditional.scala 39:67] + wire _GEN_22 = _T_186 ? buf_state_en : _GEN_17; // @[Conditional.scala 39:67] + wire _GEN_23 = _T_186 & buf_state_en; // @[Conditional.scala 39:67] + wire [2:0] _GEN_24 = _T_186 ? _T_229 : _GEN_18; // @[Conditional.scala 39:67] + wire [1:0] _GEN_26 = _T_186 ? _T_278 : _GEN_14; // @[Conditional.scala 39:67] + wire _GEN_29 = _T_186 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_186 ? 1'h0 : _GEN_11; // @[Conditional.scala 39:67] + wire _GEN_37 = _T_184 ? buf_state_en : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_39 = _T_184 ? buf_state_en : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_40 = _T_184 ? buf_state_en : _GEN_23; // @[Conditional.scala 39:67] + wire _GEN_42 = _T_184 ? 1'h0 : _GEN_22; // @[Conditional.scala 39:67] + wire [2:0] _GEN_43 = _T_184 ? 3'h0 : _GEN_24; // @[Conditional.scala 39:67] + wire [1:0] _GEN_45 = _T_184 ? 2'h0 : _GEN_26; // @[Conditional.scala 39:67] + wire _GEN_54 = _T_173 ? buf_state_en : _GEN_40; // @[Conditional.scala 39:67] + wire [2:0] _GEN_55 = _T_173 ? buf_addr[2:0] : _GEN_43; // @[Conditional.scala 39:67] + wire [1:0] _GEN_56 = _T_173 ? _T_183 : _GEN_45; // @[Conditional.scala 39:67] + wire _GEN_57 = _T_173 ? 1'h0 : _GEN_37; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_173 ? 1'h0 : _GEN_39; // @[Conditional.scala 39:67] + wire _GEN_61 = _T_173 ? 1'h0 : _GEN_42; // @[Conditional.scala 39:67] + wire _GEN_71 = _T_134 ? buf_state_en : _GEN_57; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_134 ? buf_state_en : _GEN_59; // @[Conditional.scala 39:67] + wire [2:0] _GEN_77 = _T_134 ? _T_128 : _GEN_55; // @[Conditional.scala 39:67] + wire [1:0] _GEN_78 = _T_134 ? _T_172 : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_79 = _T_134 ? buf_wr_en : _GEN_54; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_134 ? 1'h0 : _GEN_61; // @[Conditional.scala 39:67] + wire _GEN_86 = _T_99 ? buf_state_en : _GEN_79; // @[Conditional.scala 39:67] + wire [2:0] _GEN_90 = _T_99 ? _T_128 : _GEN_77; // @[Conditional.scala 39:67] + wire [1:0] _GEN_91 = _T_99 ? _T_133 : _GEN_78; // @[Conditional.scala 39:67] + wire _GEN_92 = _T_99 ? 1'h0 : _GEN_71; // @[Conditional.scala 39:67] + wire _GEN_94 = _T_99 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] + wire _GEN_97 = _T_99 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] + wire buf_data_wr_en = _T_47 ? _T_54 : _GEN_92; // @[Conditional.scala 40:58] + wire buf_cmd_byte_ptr_en = _T_47 ? buf_state_en : _GEN_97; // @[Conditional.scala 40:58] + wire [2:0] buf_cmd_byte_ptr = _T_47 ? _T_93 : _GEN_90; // @[Conditional.scala 40:58] + wire slvbuf_wr_en = _T_47 ? 1'h0 : _GEN_86; // @[Conditional.scala 40:58] + wire slvbuf_error_en = _T_47 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] + wire _T_533 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 266:24] + wire _T_534 = _T_101 | _T_533; // @[axi4_to_ahb.scala 265:48] + wire _T_536 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 266:54] + wire _T_537 = _T_534 | _T_536; // @[axi4_to_ahb.scala 266:33] + wire _T_539 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 266:93] + wire _T_540 = _T_537 | _T_539; // @[axi4_to_ahb.scala 266:72] + wire _T_542 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 267:25] + wire _T_544 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 267:62] + wire _T_546 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 267:97] + wire _T_547 = _T_544 | _T_546; // @[axi4_to_ahb.scala 267:74] + wire _T_549 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 267:132] + wire _T_550 = _T_547 | _T_549; // @[axi4_to_ahb.scala 267:109] + wire _T_552 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 267:168] + wire _T_553 = _T_550 | _T_552; // @[axi4_to_ahb.scala 267:145] + wire _T_555 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 268:28] + wire _T_556 = _T_553 | _T_555; // @[axi4_to_ahb.scala 267:181] + wire _T_558 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 268:63] + wire _T_559 = _T_556 | _T_558; // @[axi4_to_ahb.scala 268:40] + wire _T_561 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 268:99] + wire _T_562 = _T_559 | _T_561; // @[axi4_to_ahb.scala 268:76] + wire _T_563 = _T_542 & _T_562; // @[axi4_to_ahb.scala 267:38] + wire buf_aligned_in = _T_540 | _T_563; // @[axi4_to_ahb.scala 266:106] + wire _T_442 = buf_aligned_in & _T_49; // @[axi4_to_ahb.scala 260:62] + wire [2:0] _T_459 = _T_546 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_460 = 3'h2 & _T_459; // @[axi4_to_ahb.scala 128:15] + wire _T_466 = _T_558 | _T_544; // @[axi4_to_ahb.scala 129:56] + wire [2:0] _T_468 = _T_466 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_469 = 3'h4 & _T_468; // @[axi4_to_ahb.scala 129:15] + wire [2:0] _T_470 = _T_460 | _T_469; // @[axi4_to_ahb.scala 128:63] + wire [2:0] _T_474 = _T_552 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_475 = 3'h6 & _T_474; // @[axi4_to_ahb.scala 130:15] + wire [2:0] _T_476 = _T_470 | _T_475; // @[axi4_to_ahb.scala 129:96] + wire [2:0] _T_483 = _T_442 ? _T_476 : master_addr[2:0]; // @[axi4_to_ahb.scala 260:45] + wire [31:0] buf_addr_in = {master_addr[31:3],_T_483}; // @[Cat.scala 29:58] + wire _T_487 = buf_state == 3'h3; // @[axi4_to_ahb.scala 263:33] + wire _T_493 = buf_aligned_in & _T_542; // @[axi4_to_ahb.scala 264:38] + wire _T_496 = _T_493 & _T_49; // @[axi4_to_ahb.scala 264:72] + wire [1:0] _T_502 = _T_561 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_508 = _T_558 | _T_555; // @[axi4_to_ahb.scala 121:55] + wire [1:0] _T_510 = _T_508 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_511 = 2'h2 & _T_510; // @[axi4_to_ahb.scala 121:16] + wire [1:0] _T_512 = _T_502 | _T_511; // @[axi4_to_ahb.scala 120:64] + wire _T_517 = _T_552 | _T_549; // @[axi4_to_ahb.scala 122:60] + wire _T_520 = _T_517 | _T_546; // @[axi4_to_ahb.scala 122:89] + wire _T_523 = _T_520 | _T_544; // @[axi4_to_ahb.scala 122:123] + wire [1:0] _T_525 = _T_523 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_526 = 2'h1 & _T_525; // @[axi4_to_ahb.scala 122:21] + wire [1:0] _T_527 = _T_512 | _T_526; // @[axi4_to_ahb.scala 121:93] + wire [1:0] _T_529 = _T_496 ? _T_527 : master_size[1:0]; // @[axi4_to_ahb.scala 264:21] + wire [28:0] _T_568 = bypass_en ? master_addr[31:3] : buf_addr[31:3]; // @[axi4_to_ahb.scala 270:30] + wire _T_569 = io_ahb_out_htrans == 2'h2; // @[axi4_to_ahb.scala 270:115] + wire [2:0] _T_571 = _T_569 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_572 = _T_571 & buf_cmd_byte_ptr; // @[axi4_to_ahb.scala 270:124] + wire [1:0] _T_576 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [2:0] buf_size_in = {{1'd0}, _T_529}; // @[axi4_to_ahb.scala 264:15] + wire [1:0] _T_578 = _T_576 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 271:81] + wire [2:0] _T_579 = {1'h0,_T_578}; // @[Cat.scala 29:58] + wire [1:0] _T_581 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + reg [1:0] buf_size; // @[Reg.scala 27:20] + wire [1:0] _T_583 = _T_581 & buf_size; // @[axi4_to_ahb.scala 271:138] + wire [2:0] _T_584 = {1'h0,_T_583}; // @[Cat.scala 29:58] + wire _T_587 = ~io_axi_ar_bits_prot[2]; // @[axi4_to_ahb.scala 275:37] + wire [1:0] _T_588 = {1'h1,_T_587}; // @[Cat.scala 29:58] + reg buf_write; // @[Reg.scala 27:20] + wire _T_610 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 284:44] + wire _T_611 = _T_610 & io_ahb_in_hready; // @[axi4_to_ahb.scala 284:56] + wire last_addr_en = _T_611 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 284:75] + wire _T_613 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 286:31] + wire wrbuf_en = _T_613 & master_ready; // @[axi4_to_ahb.scala 286:49] + wire _T_615 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 287:35] + wire wrbuf_data_en = _T_615 & master_ready; // @[axi4_to_ahb.scala 287:52] + wire wrbuf_cmd_sent = _T_147 & _T_49; // @[axi4_to_ahb.scala 288:49] + wire _T_621 = ~wrbuf_en; // @[axi4_to_ahb.scala 289:34] + wire _T_622 = wrbuf_cmd_sent & _T_621; // @[axi4_to_ahb.scala 289:32] + wire wrbuf_rst = _T_622 | dec_tlu_force_halt_bus; // @[axi4_to_ahb.scala 289:45] + wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 291:36] + wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 291:34] + wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 291:22] + wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 292:38] + wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 292:21] + wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 293:22] + wire _T_637 = ~wrbuf_rst; // @[lib.scala 391:75] + wire _T_639 = wrbuf_en | wrbuf_rst; // @[lib.scala 391:95] + wire _T_640 = _T_639 & io_bus_clk_en; // @[lib.scala 391:102] + wire _T_647 = wrbuf_data_en | wrbuf_rst; // @[lib.scala 391:95] + wire _T_648 = _T_647 & io_bus_clk_en; // @[lib.scala 391:102] + wire _T_653 = io_bus_clk_en & wrbuf_en; // @[lib.scala 383:57] + wire _T_660 = wrbuf_en & io_bus_clk_en; // @[axi4_to_ahb.scala 300:61] + wire _T_663 = wrbuf_data_en & io_bus_clk_en; // @[axi4_to_ahb.scala 301:65] + wire _T_667 = io_bus_clk_en & wrbuf_data_en; // @[lib.scala 383:57] + wire _T_671 = io_bus_clk_en & last_addr_en; // @[lib.scala 383:57] + wire _T_728 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 321:43] + wire _T_729 = _T_728 | io_clk_override; // @[axi4_to_ahb.scala 321:58] + wire buf_clken = io_bus_clk_en & _T_729; // @[axi4_to_ahb.scala 321:30] + wire _T_674 = buf_clken & buf_wr_en; // @[lib.scala 383:57] + reg buf_tag; // @[Reg.scala 27:20] + wire _T_681 = buf_wr_en & io_bus_clk_en; // @[axi4_to_ahb.scala 306:53] + wire _T_696 = buf_data_wr_en & io_bus_clk_en; // @[axi4_to_ahb.scala 310:58] + wire _T_700 = buf_clken & slvbuf_wr_en; // @[lib.scala 383:57] + wire _T_707 = buf_clken & slvbuf_error_en; // @[lib.scala 383:57] + wire _T_711 = ~slave_valid_pre; // @[lib.scala 391:75] + wire _T_713 = cmd_done | slave_valid_pre; // @[lib.scala 391:95] + wire _T_714 = _T_713 & io_bus_clk_en; // @[lib.scala 391:102] + wire _T_719 = io_bus_clk_en & buf_cmd_byte_ptr_en; // @[lib.scala 383:57] + wire _T_731 = buf_state != 3'h0; // @[axi4_to_ahb.scala 322:50] + wire _T_732 = _T_731 | io_clk_override; // @[axi4_to_ahb.scala 322:60] + wire ahbm_data_clken = io_bus_clk_en & _T_732; // @[axi4_to_ahb.scala 322:36] + rvclkhdr rvclkhdr ( // @[lib.scala 399:23] + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 399:23] + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 399:23] + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 399:23] + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en) + ); + assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 291:19] + assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 292:18] + assign io_axi_b_valid = _T_28 & slave_opc[3]; // @[axi4_to_ahb.scala 150:18] + assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_33; // @[axi4_to_ahb.scala 151:22] + assign io_axi_b_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 152:20] + assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 293:19] + assign io_axi_r_valid = _T_28 & _T_38; // @[axi4_to_ahb.scala 154:18] + assign io_axi_r_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 156:20] + assign io_axi_r_bits_data = slvbuf_error ? _T_602 : _T_606; // @[axi4_to_ahb.scala 157:22] + assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_33; // @[axi4_to_ahb.scala 155:22] + assign io_axi_r_bits_last = 1'h1; // @[axi4_to_ahb.scala 294:22] + assign io_ahb_out_haddr = {_T_568,_T_572}; // @[axi4_to_ahb.scala 270:20] + assign io_ahb_out_hburst = 3'h0; // @[axi4_to_ahb.scala 273:21] + assign io_ahb_out_hmastlock = 1'h0; // @[axi4_to_ahb.scala 274:24] + assign io_ahb_out_hprot = {{2'd0}, _T_588}; // @[axi4_to_ahb.scala 275:20] + assign io_ahb_out_hsize = bypass_en ? _T_579 : _T_584; // @[axi4_to_ahb.scala 271:20] + assign io_ahb_out_htrans = _T_47 ? _T_98 : _GEN_91; // @[axi4_to_ahb.scala 29:21 axi4_to_ahb.scala 173:25 axi4_to_ahb.scala 185:25 axi4_to_ahb.scala 200:25 axi4_to_ahb.scala 210:25 axi4_to_ahb.scala 230:25 axi4_to_ahb.scala 245:25] + assign io_ahb_out_hwrite = bypass_en ? _T_49 : buf_write; // @[axi4_to_ahb.scala 276:21] + assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 277:21] + assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18] + assign rvclkhdr_io_en = wrbuf_en & io_bus_clk_en; // @[lib.scala 402:17] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 401:18] + assign rvclkhdr_1_io_en = wrbuf_data_en & io_bus_clk_en; // @[lib.scala 402:17] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 401:18] + assign rvclkhdr_2_io_en = buf_wr_en & io_bus_clk_en; // @[lib.scala 402:17] + assign rvclkhdr_3_io_clk = clock; // @[lib.scala 401:18] + assign rvclkhdr_3_io_en = buf_data_wr_en & io_bus_clk_en; // @[lib.scala 402:17] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + dec_tlu_force_halt_bus_q = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + buf_state = _RAND_1[2:0]; + _RAND_2 = {1{`RANDOM}}; + wrbuf_vld = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + wrbuf_data_vld = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + ahb_hready_q = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + ahb_htrans_q = _RAND_5[1:0]; + _RAND_6 = {1{`RANDOM}}; + ahb_hwrite_q = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + ahb_hresp_q = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + cmd_doneQ = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + wrbuf_tag = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + wrbuf_addr = _RAND_10[31:0]; + _RAND_11 = {1{`RANDOM}}; + wrbuf_size = _RAND_11[2:0]; + _RAND_12 = {1{`RANDOM}}; + wrbuf_byteen = _RAND_12[7:0]; + _RAND_13 = {2{`RANDOM}}; + wrbuf_data = _RAND_13[63:0]; + _RAND_14 = {1{`RANDOM}}; + slvbuf_write = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + slvbuf_error = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + slvbuf_tag = _RAND_16[0:0]; + _RAND_17 = {1{`RANDOM}}; + last_bus_addr = _RAND_17[31:0]; + _RAND_18 = {2{`RANDOM}}; + buf_data = _RAND_18[63:0]; + _RAND_19 = {2{`RANDOM}}; + ahb_hrdata_q = _RAND_19[63:0]; + _RAND_20 = {1{`RANDOM}}; + buf_addr = _RAND_20[31:0]; + _RAND_21 = {1{`RANDOM}}; + buf_cmd_byte_ptrQ = _RAND_21[2:0]; + _RAND_22 = {1{`RANDOM}}; + buf_byteen = _RAND_22[7:0]; + _RAND_23 = {1{`RANDOM}}; + buf_aligned = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + buf_size = _RAND_24[1:0]; + _RAND_25 = {1{`RANDOM}}; + buf_write = _RAND_25[0:0]; + _RAND_26 = {1{`RANDOM}}; + buf_tag = _RAND_26[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + dec_tlu_force_halt_bus_q = 1'h0; + end + if (reset) begin + buf_state = 3'h0; + end + if (reset) begin + wrbuf_vld = 1'h0; + end + if (reset) begin + wrbuf_data_vld = 1'h0; + end + if (reset) begin + ahb_hready_q = 1'h0; + end + if (reset) begin + ahb_htrans_q = 2'h0; + end + if (reset) begin + ahb_hwrite_q = 1'h0; + end + if (reset) begin + ahb_hresp_q = 1'h0; + end + if (reset) begin + cmd_doneQ = 1'h0; + end + if (reset) begin + wrbuf_tag = 1'h0; + end + if (reset) begin + wrbuf_addr = 32'h0; + end + if (reset) begin + wrbuf_size = 3'h0; + end + if (reset) begin + wrbuf_byteen = 8'h0; + end + if (reset) begin + wrbuf_data = 64'h0; + end + if (reset) begin + slvbuf_write = 1'h0; + end + if (reset) begin + slvbuf_error = 1'h0; + end + if (reset) begin + slvbuf_tag = 1'h0; + end + if (reset) begin + last_bus_addr = 32'h0; + end + if (reset) begin + buf_data = 64'h0; + end + if (reset) begin + ahb_hrdata_q = 64'h0; + end + if (reset) begin + buf_addr = 32'h0; + end + if (reset) begin + buf_cmd_byte_ptrQ = 3'h0; + end + if (reset) begin + buf_byteen = 8'h0; + end + if (reset) begin + buf_aligned = 1'h0; + end + if (reset) begin + buf_size = 2'h0; + end + if (reset) begin + buf_write = 1'h0; + end + if (reset) begin + buf_tag = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + dec_tlu_force_halt_bus_q <= 1'h0; + end else begin + dec_tlu_force_halt_bus_q <= _T & dec_tlu_force_halt_bus; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_state <= 3'h0; + end else if (_T_7) begin + buf_state <= _T_5; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + wrbuf_vld <= 1'h0; + end else if (_T_640) begin + wrbuf_vld <= _T_637; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + wrbuf_data_vld <= 1'h0; + end else if (_T_648) begin + wrbuf_data_vld <= _T_637; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + ahb_hready_q <= 1'h0; + end else if (io_bus_clk_en) begin + ahb_hready_q <= io_ahb_in_hready; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + ahb_htrans_q <= 2'h0; + end else if (io_bus_clk_en) begin + ahb_htrans_q <= io_ahb_out_htrans; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + ahb_hwrite_q <= 1'h0; + end else if (io_bus_clk_en) begin + ahb_hwrite_q <= io_ahb_out_hwrite; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + ahb_hresp_q <= 1'h0; + end else if (io_bus_clk_en) begin + ahb_hresp_q <= io_ahb_in_hresp; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + cmd_doneQ <= 1'h0; + end else if (_T_714) begin + cmd_doneQ <= _T_711; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + wrbuf_tag <= 1'h0; + end else if (_T_653) begin + wrbuf_tag <= io_axi_aw_bits_id; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + wrbuf_addr <= 32'h0; + end else if (_T_660) begin + wrbuf_addr <= io_axi_aw_bits_addr; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + wrbuf_size <= 3'h0; + end else if (_T_653) begin + wrbuf_size <= io_axi_aw_bits_size; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + wrbuf_byteen <= 8'h0; + end else if (_T_667) begin + wrbuf_byteen <= io_axi_w_bits_strb; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + wrbuf_data <= 64'h0; + end else if (_T_663) begin + wrbuf_data <= io_axi_w_bits_data; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + slvbuf_write <= 1'h0; + end else if (_T_700) begin + slvbuf_write <= buf_write; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + slvbuf_error <= 1'h0; + end else if (_T_707) begin + if (_T_47) begin + slvbuf_error <= 1'h0; + end else if (_T_99) begin + slvbuf_error <= 1'h0; + end else if (_T_134) begin + slvbuf_error <= ahb_hresp_q; + end else if (_T_173) begin + slvbuf_error <= 1'h0; + end else if (_T_184) begin + slvbuf_error <= ahb_hresp_q; + end else if (_T_186) begin + slvbuf_error <= 1'h0; + end else begin + slvbuf_error <= _GEN_7; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + slvbuf_tag <= 1'h0; + end else if (_T_700) begin + slvbuf_tag <= buf_tag; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + last_bus_addr <= 32'h0; + end else if (_T_671) begin + last_bus_addr <= io_ahb_out_haddr; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_data <= 64'h0; + end else if (_T_696) begin + if (_T_487) begin + buf_data <= ahb_hrdata_q; + end else begin + buf_data <= wrbuf_data; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + ahb_hrdata_q <= 64'h0; + end else if (ahbm_data_clken) begin + ahb_hrdata_q <= io_ahb_in_hrdata; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_addr <= 32'h0; + end else if (_T_681) begin + buf_addr <= buf_addr_in; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_719) begin + if (_T_47) begin + if (buf_write_in) begin + if (wrbuf_byteen[0]) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (wrbuf_byteen[1]) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (wrbuf_byteen[2]) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (wrbuf_byteen[3]) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (wrbuf_byteen[4]) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (wrbuf_byteen[5]) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (wrbuf_byteen[6]) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end else begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end + end else if (_T_99) begin + if (bypass_en) begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end else begin + buf_cmd_byte_ptrQ <= buf_addr[2:0]; + end + end else if (_T_134) begin + if (bypass_en) begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end else begin + buf_cmd_byte_ptrQ <= buf_addr[2:0]; + end + end else if (_T_173) begin + buf_cmd_byte_ptrQ <= buf_addr[2:0]; + end else if (_T_184) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_186) begin + if (trxn_done) begin + if (_T_199) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_202) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (_T_205) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (_T_208) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (_T_211) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (_T_214) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (_T_217) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end + end else if (_T_279) begin + if (bypass_en) begin + if (wrbuf_byteen[0]) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (wrbuf_byteen[1]) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (wrbuf_byteen[2]) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (wrbuf_byteen[3]) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (wrbuf_byteen[4]) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (wrbuf_byteen[5]) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (wrbuf_byteen[6]) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end else if (trxn_done) begin + if (_T_199) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_202) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (_T_205) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (_T_208) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (_T_211) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (_T_214) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (_T_217) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end + end else begin + buf_cmd_byte_ptrQ <= 3'h0; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_byteen <= 8'h0; + end else if (_T_674) begin + buf_byteen <= wrbuf_byteen; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_aligned <= 1'h0; + end else if (_T_674) begin + buf_aligned <= buf_aligned_in; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_size <= 2'h0; + end else if (_T_674) begin + buf_size <= buf_size_in[1:0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_write <= 1'h0; + end else if (_T_674) begin + if (_T_47) begin + buf_write <= _T_49; + end else if (_T_99) begin + buf_write <= 1'h0; + end else if (_T_134) begin + buf_write <= 1'h0; + end else if (_T_173) begin + buf_write <= 1'h0; + end else if (_T_184) begin + buf_write <= 1'h0; + end else if (_T_186) begin + buf_write <= 1'h0; + end else begin + buf_write <= _GEN_9; + end + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + buf_tag <= 1'h0; + end else if (_T_674) begin + if (wr_cmd_vld) begin + buf_tag <= wrbuf_tag; + end else begin + buf_tag <= io_axi_ar_bits_id; + end + end + end +endmodule diff --git a/src/main/scala/lib/ahb_to_axi4.scala b/src/main/scala/lib/ahb_to_axi4.scala index cae0db0e..3ca3c5fe 100644 --- a/src/main/scala/lib/ahb_to_axi4.scala +++ b/src/main/scala/lib/ahb_to_axi4.scala @@ -157,7 +157,7 @@ class ahb_to_axi4(TAG : Int) extends Module with lib with RequireAsyncReset { io.axi.aw.bits.size := Cat("b0".U, cmdbuf_size(1, 0)) io.axi.aw.bits.prot := Fill(3, 0.U) io.axi.aw.bits.len := Fill(8, 0.U) - io.axi.aw.bits.burst := "b01".U + io.axi.aw.bits.burst := "b01".U(2.W) // AXI Write Data Channel - This is tied to the command channel as we only write the command buffer once we have the data. io.axi.w.valid := cmdbuf_vld & cmdbuf_write io.axi.w.bits.data := cmdbuf_wdata @@ -172,7 +172,7 @@ class ahb_to_axi4(TAG : Int) extends Module with lib with RequireAsyncReset { io.axi.ar.bits.size := Cat("b0".U, cmdbuf_size(1, 0)) io.axi.ar.bits.prot := Fill(3, 0.U) io.axi.ar.bits.len := Fill(8, 0.U) - io.axi.ar.bits.burst := "b01".U + io.axi.ar.bits.burst := "b01".U(2.W) // AXI Read Response Channel - Always ready as AHB reads are blocking and the the buffer is available for the read coming back always. io.axi.r.ready := true.B } diff --git a/src/main/scala/lib/axi4_to_ahb.scala b/src/main/scala/lib/axi4_to_ahb.scala index 3460c11f..3c4ae99a 100644 --- a/src/main/scala/lib/axi4_to_ahb.scala +++ b/src/main/scala/lib/axi4_to_ahb.scala @@ -6,9 +6,11 @@ import include._ class axi4_to_ahb_IO(val TAG : Int) extends Bundle { + val free_clk = Input(Clock()) val scan_mode = Input(Bool()) val bus_clk_en = Input(Bool()) val clk_override = Input(Bool()) + val dec_tlu_force_halt = Input(Bool()) // AXI-4 signals val axi = Flipped(new axi_channels(TAG)) // AHB-Lite signals @@ -17,17 +19,21 @@ class axi4_to_ahb_IO(val TAG : Int) extends Bundle { class axi4_to_ahb(val TAG : Int = 3) extends Module with lib with RequireAsyncReset { val io = IO(new axi4_to_ahb_IO(TAG)) + // Create bus synchronized version of force halt + val dec_tlu_force_halt_bus_q = WireInit(Bool(), init = false.B) + val dec_tlu_force_halt_bus = io.dec_tlu_force_halt | dec_tlu_force_halt_bus_q + val dec_tlu_force_halt_bus_ns = !io.bus_clk_en & dec_tlu_force_halt_bus + dec_tlu_force_halt_bus_q := withClock(io.free_clk) {RegNext(dec_tlu_force_halt_bus_ns, 0.U)} val buf_rst = WireInit(0.U(1.W)) - buf_rst :=0.U + buf_rst := dec_tlu_force_halt_bus io.ahb.out.htrans := 0.U val buf_state_en = WireInit(Bool(), init = false.B) - val ahbm_clk = Wire(Clock()) - val ahbm_addr_clk = Wire(Clock()) + val bus_clk = Wire(Clock()) val ahbm_data_clk = Wire(Clock()) val idle :: cmd_rd :: cmd_wr :: data_rd :: data_wr :: done :: stream_rd :: stream_err_rd :: Nil = Enum(8) val buf_state = WireInit(0.U(3.W)) val buf_nxtstate = WireInit(0.U(3.W)) - buf_state := withClock(ahbm_clk) { RegNext((Mux(buf_state_en.asBool() ,buf_nxtstate,buf_state) & Fill(3, !buf_rst)), 0.U) } + buf_state := rvdffsc_fpga(buf_nxtstate, buf_state_en.asBool(), buf_rst, bus_clk, io.bus_clk_en, clock) //logic signals val slave_valid = WireInit(Bool(), init = false.B) val slave_ready = WireInit(Bool(), init = false.B) @@ -46,10 +52,6 @@ class axi4_to_ahb(val TAG : Int = 3) extends Module with lib with RequireAsyncRe val wrbuf_data = WireInit(0.U(64.W)) // [63:0] val wrbuf_byteen = WireInit(0.U(8.W)) // [7:0] - val bus_write_clk_en = WireInit(Bool(), init = false.B) - val bus_clk = Wire(Clock()) - val bus_write_clk = Wire(Clock()) - val master_valid = WireInit(Bool(), init = false.B) val master_ready = WireInit(0.U(1.W)) val master_tag = WireInit(0.U(TAG.W)) // [TAG-1:0] @@ -112,17 +114,15 @@ class axi4_to_ahb(val TAG : Int = 3) extends Module with lib with RequireAsyncRe val last_bus_addr = WireInit(0.U(32.W)) // [31:0] // Clocks val buf_clken = WireInit(Bool(), init = false.B) - val slvbuf_clken = WireInit(Bool(), init = false.B) - val ahbm_addr_clken = WireInit(Bool(), init = false.B) val ahbm_data_clken = WireInit(Bool(), init = false.B) val buf_clk = Wire(Clock()) - def get_write_size(byteen: UInt) = { val size = ("b11".U & Fill(2, (byteen(7, 0) === "hff".U))) | ("b10".U & (Fill(2, ((byteen(7, 0) === "hf0".U) | (byteen(7, 0) === "h0f".U(8.W)))))) | ("b01".U(2.W) & (Fill(2, ((byteen(7, 0) === "hc0".U) | (byteen(7, 0) === "h30".U) | (byteen(7, 0) === "h0c".U(8.W)) | (byteen(7, 0) === "h03".U(8.W)))))) size } + def get_write_addr(byteen_e: UInt) = { val addr = ("h0".U(3.W) & (Fill(3, ((byteen_e(7, 0) === "hff".U) | (byteen_e(7, 0) === "h0f".U(8.W)) | (byteen_e(7, 0) === "h03".U(8.W)))))) | ("h2".U & (Fill(3, (byteen_e(7, 0) === "h0c".U(8.W))))) | @@ -131,6 +131,7 @@ class axi4_to_ahb(val TAG : Int = 3) extends Module with lib with RequireAsyncRe ("h6".U & (Fill(3, (byteen_e(7, 0) === "hc0".U)))) addr } + def get_nxtbyte_ptr(current_byte_ptr: UInt, byteen: UInt, get_next: Bool): UInt = { val start_ptr = Mux(get_next, current_byte_ptr + 1.U, current_byte_ptr) val temp = (0 until 8).map(j => (byteen(j) & (j.asUInt() >= start_ptr)) -> j.U) @@ -156,12 +157,6 @@ class axi4_to_ahb(val TAG : Int = 3) extends Module with lib with RequireAsyncRe io.axi.r.bits.data := slave_rdata(63, 0) slave_ready := io.axi.b.ready & io.axi.r.ready - // Clock header logic - bus_write_clk_en := io.bus_clk_en & ((io.axi.aw.valid & io.axi.aw.ready) | (io.axi.w.valid & io.axi.w.ready)) - - bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode) - bus_write_clk := rvclkhdr(clock, bus_write_clk_en.asBool(), io.scan_mode) - switch(buf_state) { is(idle) { master_ready := 1.U @@ -203,7 +198,7 @@ class axi4_to_ahb(val TAG : Int = 3) extends Module with lib with RequireAsyncRe bypass_en := master_ready & master_valid & (buf_nxtstate === stream_rd) & buf_state_en buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0)) io.ahb.out.htrans := "b10".U & Fill(2, (!((buf_nxtstate =/= stream_rd) & buf_state_en))) - slvbuf_wr_en := buf_wr_en// shifting the contents from the buf to slv_buf for streaming cases + slvbuf_wr_en := buf_wr_en // shifting the contents from the buf to slv_buf for streaming cases } is(stream_err_rd) { @@ -238,20 +233,20 @@ class axi4_to_ahb(val TAG : Int = 3) extends Module with lib with RequireAsyncRe is(data_wr) { buf_state_en := (cmd_doneQ & ahb_hready_q) | ahb_hresp_q master_ready := buf_state_en & !ahb_hresp_q & slave_ready - buf_nxtstate := Mux((ahb_hresp_q | !slave_ready),done ,Mux((master_valid & master_valid),Mux((master_opc(2,1) === 1.U).asBool(),cmd_wr,cmd_rd),idle)) + buf_nxtstate := Mux((ahb_hresp_q | !slave_ready), done, Mux((master_valid & master_valid), Mux((master_opc(2, 1) === 1.U).asBool(), cmd_wr, cmd_rd), idle)) slvbuf_error_in := ahb_hresp_q slvbuf_error_en := buf_state_en - buf_write_in := master_opc(2,1) === 1.U + buf_write_in := master_opc(2, 1) === 1.U buf_wr_en := buf_state_en & ((buf_nxtstate === cmd_wr) | (buf_nxtstate === cmd_rd)) buf_data_wr_en := buf_wr_en - cmd_done := (ahb_hresp_q | (ahb_hready_q & (ahb_htrans_q(1,0) =/= 0.U) & - ((buf_cmd_byte_ptrQ === 7.U) | (buf_byteen(get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2,0),buf_byteen(7,0),true.B)) === 0.U)))) + cmd_done := (ahb_hresp_q | (ahb_hready_q & (ahb_htrans_q(1, 0) =/= 0.U) & + ((buf_cmd_byte_ptrQ === 7.U) | (buf_byteen(get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B)) === 0.U)))) bypass_en := buf_state_en & buf_write_in & (buf_nxtstate === cmd_wr) io.ahb.out.htrans := Fill(2, (!(cmd_done | cmd_doneQ) | bypass_en)) & 2.U slave_valid_pre := buf_state_en & (buf_nxtstate =/= done) - trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1,0) =/= 0.U) + trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1, 0) =/= 0.U) buf_cmd_byte_ptr_en := trxn_done | bypass_en - buf_cmd_byte_ptr := Mux(bypass_en,get_nxtbyte_ptr(0.U(3.W),buf_byteen_in(7,0),false.B),Mux(trxn_done,get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2,0),buf_byteen(7,0),true.B),buf_cmd_byte_ptrQ)) + buf_cmd_byte_ptr := Mux(bypass_en, get_nxtbyte_ptr(0.U(3.W), buf_byteen_in(7, 0), false.B), Mux(trxn_done, get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B), buf_cmd_byte_ptrQ)) } is(done) { buf_nxtstate := idle @@ -262,17 +257,17 @@ class axi4_to_ahb(val TAG : Int = 3) extends Module with lib with RequireAsyncRe } // buf_rst := 0.U cmd_done_rst := slave_valid_pre - buf_addr_in := Cat(master_addr(31,3),Mux((buf_aligned_in & (master_opc(2, 1) === "b01".U)).asBool(), get_write_addr(master_byteen(7, 0)), master_addr(2, 0))) + buf_addr_in := Cat(master_addr(31, 3), Mux((buf_aligned_in & (master_opc(2, 1) === "b01".U)).asBool(), get_write_addr(master_byteen(7, 0)), master_addr(2, 0))) buf_tag_in := master_tag(TAG - 1, 0) - buf_byteen_in := wrbuf_byteen(7,0) + buf_byteen_in := wrbuf_byteen(7, 0) buf_data_in := Mux((buf_state === data_rd), ahb_hrdata_q(63, 0), master_wdata(63, 0)) - buf_size_in := Mux((buf_aligned_in & (master_size(1,0) === "b11".U) & (master_opc(2, 1) === "b01".U)).asBool(),get_write_size(master_byteen(7,0)), master_size(1,0)) + buf_size_in := Mux((buf_aligned_in & (master_size(1, 0) === "b11".U) & (master_opc(2, 1) === "b01".U)).asBool(), get_write_size(master_byteen(7, 0)), master_size(1, 0)) buf_aligned_in := (master_opc(2, 0) === 0.U) | // reads are always aligned since they are either DW or sideeffects (master_size(1, 0) === 0.U) | (master_size(1, 0) === "b01".U(2.W)) | (master_size(1, 0) === "b10".U) | // Always aligned for Byte/HW/Word since they can be only for non-idempotent. IFU/SB are always aligned ((master_size(1, 0) === "b11".U) & ((master_byteen(7, 0) === "h3".U) | (master_byteen(7, 0) === "hc".U) | (master_byteen(7, 0) === "h30".U) | (master_byteen(7, 0) === "hc0".U) | (master_byteen(7, 0) === "hf".U) | (master_byteen(7, 0) === "hf0".U) | (master_byteen(7, 0) === "hff".U))) // Generate the ahb signals - io.ahb.out.haddr := Mux(bypass_en.asBool(), Cat(master_addr(31, 3), buf_cmd_byte_ptr(2, 0)), Cat(buf_addr(31, 3), buf_cmd_byte_ptr(2, 0))) + io.ahb.out.haddr := Cat(Mux(bypass_en.asBool(), master_addr(31, 3), buf_addr(31, 3)), Fill(3, io.ahb.out.htrans === 2.U) & buf_cmd_byte_ptr) io.ahb.out.hsize := Mux(bypass_en.asBool(), Cat(0.U, (Fill(2, buf_aligned_in) & buf_size_in(1, 0))), Cat("b0".U, (Fill(2, buf_aligned) & buf_size(1, 0)))) io.ahb.out.hburst := "b0".U @@ -291,50 +286,53 @@ class axi4_to_ahb(val TAG : Int = 3) extends Module with lib with RequireAsyncRe wrbuf_en := io.axi.aw.valid & io.axi.aw.ready & master_ready wrbuf_data_en := io.axi.w.valid & io.axi.w.ready & master_ready wrbuf_cmd_sent := master_valid & master_ready & (master_opc(2, 1) === "b01".U) - wrbuf_rst := wrbuf_cmd_sent & !wrbuf_en + wrbuf_rst := (wrbuf_cmd_sent & !wrbuf_en) | dec_tlu_force_halt_bus io.axi.aw.ready := !(wrbuf_vld & !wrbuf_cmd_sent) & master_ready io.axi.w.ready := !(wrbuf_data_vld & !wrbuf_cmd_sent) & master_ready io.axi.ar.ready := !(wrbuf_vld & wrbuf_data_vld) & master_ready io.axi.r.bits.last := true.B - wrbuf_vld := withClock(bus_clk) {RegNext(Mux(wrbuf_en.asBool(),1.U,wrbuf_vld) & !wrbuf_rst, 0.U)} - wrbuf_data_vld := withClock(bus_clk) {RegNext(Mux(wrbuf_data_en.asBool(),1.U, wrbuf_data_vld) & !wrbuf_rst, 0.U)} - wrbuf_tag := withClock(bus_clk) {RegEnable(io.axi.aw.bits.id(TAG - 1, 0), 0.U, wrbuf_en.asBool())} - wrbuf_size := withClock(bus_clk) {RegEnable(io.axi.aw.bits.size(2, 0), 0.U, wrbuf_en.asBool())} - wrbuf_addr := rvdffe(io.axi.aw.bits.addr, wrbuf_en.asBool,bus_clk,io.scan_mode) - wrbuf_data := rvdffe(io.axi.w.bits.data, wrbuf_data_en.asBool,bus_clk,io.scan_mode) - wrbuf_byteen := withClock(bus_clk) {RegEnable(io.axi.w.bits.strb(7, 0), 0.U, wrbuf_data_en.asBool())} - last_bus_addr := withClock(ahbm_clk) {RegEnable(io.ahb.out.haddr(31, 0), 0.U, last_addr_en.asBool())} - buf_write := withClock(buf_clk) {RegEnable(buf_write_in, 0.U, buf_wr_en.asBool())} - buf_tag := withClock(buf_clk) {RegEnable(buf_tag_in(TAG - 1, 0), 0.U, buf_wr_en.asBool())} - buf_addr := rvdffe(buf_addr_in(31, 0),(buf_wr_en & io.bus_clk_en).asBool,clock,io.scan_mode) - buf_size := withClock(buf_clk) {RegEnable(buf_size_in(1, 0), 0.U, buf_wr_en.asBool())} - buf_aligned := withClock(buf_clk) {RegEnable(buf_aligned_in, 0.U, buf_wr_en.asBool())} - buf_byteen := withClock(buf_clk) {RegEnable(buf_byteen_in(7, 0), 0.U, buf_wr_en.asBool())} - buf_data := rvdffe(buf_data_in(63, 0),(buf_data_wr_en & io.bus_clk_en).asBool(),clock,io.scan_mode) - slvbuf_write := withClock(buf_clk) {RegEnable(buf_write, 0.U, slvbuf_wr_en.asBool())} - slvbuf_tag := withClock(buf_clk) {RegEnable(buf_tag(TAG - 1, 0), 0.U, slvbuf_wr_en.asBool())} - slvbuf_error := withClock(ahbm_clk) {RegEnable(slvbuf_error_in, 0.U, slvbuf_error_en.asBool())} - cmd_doneQ := withClock(ahbm_clk) {RegNext(Mux(cmd_done.asBool(),1.U,cmd_doneQ) & !cmd_done_rst, 0.U)} - buf_cmd_byte_ptrQ := withClock(ahbm_clk) {RegEnable(buf_cmd_byte_ptr(2, 0), 0.U, buf_cmd_byte_ptr_en.asBool())} - ahb_hready_q := withClock(ahbm_clk) {RegNext(io.ahb.in.hready, 0.U)} - ahb_htrans_q := withClock(ahbm_clk) {RegNext(io.ahb.out.htrans(1, 0), 0.U)} - ahb_hwrite_q := withClock(ahbm_addr_clk) {RegNext(io.ahb.out.hwrite, 0.U)} - ahb_hresp_q := withClock(ahbm_clk) {RegNext(io.ahb.in.hresp, 0.U)} - ahb_hrdata_q := withClock(ahbm_data_clk) {RegNext(io.ahb.in.hrdata(63, 0), 0.U)} - + wrbuf_vld := rvdffsc_fpga(1.U, wrbuf_en.asBool(), wrbuf_rst, bus_clk, io.bus_clk_en, clock) + wrbuf_data_vld := rvdffsc_fpga(1.U, wrbuf_data_en.asBool(), wrbuf_rst, bus_clk, io.bus_clk_en, clock) + wrbuf_tag := rvdffs_fpga(io.axi.aw.bits.id(TAG - 1, 0), wrbuf_en.asBool(), bus_clk, io.bus_clk_en, clock) + wrbuf_size := rvdffs_fpga(io.axi.aw.bits.size(2, 0), wrbuf_en.asBool(), bus_clk, io.bus_clk_en, clock) + wrbuf_addr := rvdffe(io.axi.aw.bits.addr, wrbuf_en.asBool & io.bus_clk_en, clock, io.scan_mode) + wrbuf_data := rvdffe(io.axi.w.bits.data, wrbuf_data_en.asBool & io.bus_clk_en, clock, io.scan_mode) + wrbuf_byteen := rvdffs_fpga(io.axi.w.bits.strb(7, 0), wrbuf_data_en.asBool(), bus_clk, io.bus_clk_en, clock) + last_bus_addr := rvdffs_fpga(io.ahb.out.haddr(31, 0), last_addr_en.asBool(), bus_clk, io.bus_clk_en, clock) + buf_write := rvdffs_fpga(buf_write_in, buf_wr_en.asBool(), buf_clk, buf_clken, clock) + buf_tag := rvdffs_fpga(buf_tag_in(TAG - 1, 0), buf_wr_en.asBool(), buf_clk, buf_clken, clock) + buf_addr := rvdffe(buf_addr_in(31, 0), (buf_wr_en & io.bus_clk_en).asBool, clock, io.scan_mode) + buf_size := rvdffs_fpga(buf_size_in(1, 0), buf_wr_en.asBool(), buf_clk, buf_clken, clock) + buf_aligned := rvdffs_fpga(buf_aligned_in, buf_wr_en.asBool(), buf_clk, buf_clken, clock) + buf_byteen := rvdffs_fpga(buf_byteen_in(7, 0), buf_wr_en.asBool(), buf_clk, buf_clken, clock) + buf_data := rvdffe(buf_data_in(63, 0), (buf_data_wr_en & io.bus_clk_en).asBool(), clock, io.scan_mode) + slvbuf_write := rvdffs_fpga(buf_write, slvbuf_wr_en.asBool(), buf_clk, buf_clken, clock) + slvbuf_tag := rvdffs_fpga(buf_tag(TAG - 1, 0), slvbuf_wr_en.asBool(), buf_clk, buf_clken, clock) + slvbuf_error := rvdffs_fpga(slvbuf_error_in, slvbuf_error_en.asBool(), buf_clk, buf_clken, clock) + cmd_doneQ := rvdffsc_fpga(1.U, cmd_done.asBool(), cmd_done_rst, bus_clk, io.bus_clk_en, clock) + buf_cmd_byte_ptrQ := rvdffs_fpga(buf_cmd_byte_ptr(2, 0), buf_cmd_byte_ptr_en.asBool(), bus_clk, io.bus_clk_en, clock) + ahb_hready_q := rvdff_fpga(io.ahb.in.hready, bus_clk, io.bus_clk_en, clock) + ahb_htrans_q := rvdff_fpga(io.ahb.out.htrans(1, 0), bus_clk,io.bus_clk_en, clock) + ahb_hwrite_q := rvdff_fpga(io.ahb.out.hwrite,bus_clk, io.bus_clk_en, clock) + ahb_hresp_q := rvdff_fpga(io.ahb.in.hresp,bus_clk, io.bus_clk_en, clock) + ahb_hrdata_q := rvdff_fpga(io.ahb.in.hrdata(63, 0), ahbm_data_clk, ahbm_data_clken, clock) buf_clken := io.bus_clk_en & (buf_wr_en | slvbuf_wr_en | io.clk_override) - ahbm_addr_clken := io.bus_clk_en & ((io.ahb.in.hready & io.ahb.out.htrans(1)) | io.clk_override) ahbm_data_clken := io.bus_clk_en & ((buf_state =/= idle) | io.clk_override) - //Clkhdr - buf_clk := rvclkhdr(clock, buf_clken, io.scan_mode) - ahbm_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode) - ahbm_addr_clk := rvclkhdr(clock, ahbm_addr_clken, io.scan_mode) - ahbm_data_clk := rvclkhdr(clock, ahbm_data_clken, io.scan_mode) + if (RV_FPGA_OPTIMIZE) { + bus_clk := 0.B.asClock() + buf_clk := 0.B.asClock() + ahbm_data_clk := 0.B.asClock() + } + else { + buf_clk := rvclkhdr(clock, buf_clken, io.scan_mode) + bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode) + ahbm_data_clk := rvclkhdr(clock, ahbm_data_clken, io.scan_mode) + } } -//object axi4_to_ahb extends App { -// println((new chisel3.stage.ChiselStage).emitVerilog(new axi4_to_ahb(3))) -//} +object axi4_to_ahb extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new axi4_to_ahb(1))) +} \ No newline at end of file diff --git a/target/scala-2.12/classes/lib/ahb_to_axi4.class b/target/scala-2.12/classes/lib/ahb_to_axi4.class index c9cfc531..9d19a27a 100644 Binary files a/target/scala-2.12/classes/lib/ahb_to_axi4.class and b/target/scala-2.12/classes/lib/ahb_to_axi4.class differ diff --git a/target/scala-2.12/classes/lib/axi4_to_ahb$.class b/target/scala-2.12/classes/lib/axi4_to_ahb$.class index 1f02f9de..b69d30de 100644 Binary files a/target/scala-2.12/classes/lib/axi4_to_ahb$.class and b/target/scala-2.12/classes/lib/axi4_to_ahb$.class differ diff --git a/target/scala-2.12/classes/lib/axi4_to_ahb$delayedInit$body.class b/target/scala-2.12/classes/lib/axi4_to_ahb$delayedInit$body.class new file mode 100644 index 00000000..f7510626 Binary files /dev/null and b/target/scala-2.12/classes/lib/axi4_to_ahb$delayedInit$body.class differ diff --git a/target/scala-2.12/classes/lib/axi4_to_ahb.class b/target/scala-2.12/classes/lib/axi4_to_ahb.class index 4a02dfab..a600ba77 100644 Binary files a/target/scala-2.12/classes/lib/axi4_to_ahb.class and b/target/scala-2.12/classes/lib/axi4_to_ahb.class differ diff --git a/target/scala-2.12/classes/lib/axi4_to_ahb_IO.class b/target/scala-2.12/classes/lib/axi4_to_ahb_IO.class index 2bd2c9b4..305d0ab0 100644 Binary files a/target/scala-2.12/classes/lib/axi4_to_ahb_IO.class and b/target/scala-2.12/classes/lib/axi4_to_ahb_IO.class differ