lsu updated

lsu.fir

@@ -15572,11 +15572,9 @@ circuit lsu :
     node _T_67 = neq(_T_64, _T_66) @[lsu.scala 155:48]
     ldst_dual_m <= _T_67 @[lsu.scala 155:16]
     node _T_68 = bits(lsu_lsc_ctl.io.lsu_addr_r, 2, 2) @[lsu.scala 156:44]
-    node _T_69 = bits(lsu_lsc_ctl.io.end_addr_m, 2, 2) @[lsu.scala 156:122]
-    reg _T_70 : UInt<1>, clkdomain.io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 156:96]
-    _T_70 <= _T_69 @[lsu.scala 156:96]
-    node _T_71 = neq(_T_68, _T_70) @[lsu.scala 156:48]
-    ldst_dual_r <= _T_71 @[lsu.scala 156:16]
+    node _T_69 = bits(lsu_lsc_ctl.io.end_addr_r, 2, 2) @[lsu.scala 156:77]
+    node _T_70 = neq(_T_68, _T_69) @[lsu.scala 156:48]
+    ldst_dual_r <= _T_70 @[lsu.scala 156:16]
     io.lsu_single_ecc_error_incr <= lsu_lsc_ctl.io.lsu_single_ecc_error_incr @[lsu.scala 158:49]
     io.lsu_error_pkt_r.bits.addr <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.addr @[lsu.scala 159:49]
     io.lsu_error_pkt_r.bits.mscause <= lsu_lsc_ctl.io.lsu_error_pkt_r.bits.mscause @[lsu.scala 159:49]
@@ -15646,15 +15644,15 @@ circuit lsu :
     dccm_ctl.io.lsu_raw_fwd_hi_r <= lsu_raw_fwd_hi_r @[lsu.scala 182:46]
     dccm_ctl.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[lsu.scala 183:46]
     dccm_ctl.io.lsu_addr_d <= lsu_lsc_ctl.io.lsu_addr_d @[lsu.scala 184:46]
-    node _T_72 = bits(lsu_lsc_ctl.io.lsu_addr_m, 15, 0) @[lsu.scala 185:74]
-    dccm_ctl.io.lsu_addr_m <= _T_72 @[lsu.scala 185:46]
+    node _T_71 = bits(lsu_lsc_ctl.io.lsu_addr_m, 15, 0) @[lsu.scala 185:74]
+    dccm_ctl.io.lsu_addr_m <= _T_71 @[lsu.scala 185:46]
     dccm_ctl.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[lsu.scala 186:46]
-    node _T_73 = bits(lsu_lsc_ctl.io.end_addr_d, 15, 0) @[lsu.scala 187:74]
-    dccm_ctl.io.end_addr_d <= _T_73 @[lsu.scala 187:46]
-    node _T_74 = bits(lsu_lsc_ctl.io.end_addr_m, 15, 0) @[lsu.scala 188:74]
-    dccm_ctl.io.end_addr_m <= _T_74 @[lsu.scala 188:46]
-    node _T_75 = bits(lsu_lsc_ctl.io.end_addr_r, 15, 0) @[lsu.scala 189:74]
-    dccm_ctl.io.end_addr_r <= _T_75 @[lsu.scala 189:46]
+    node _T_72 = bits(lsu_lsc_ctl.io.end_addr_d, 15, 0) @[lsu.scala 187:74]
+    dccm_ctl.io.end_addr_d <= _T_72 @[lsu.scala 187:46]
+    node _T_73 = bits(lsu_lsc_ctl.io.end_addr_m, 15, 0) @[lsu.scala 188:74]
+    dccm_ctl.io.end_addr_m <= _T_73 @[lsu.scala 188:46]
+    node _T_74 = bits(lsu_lsc_ctl.io.end_addr_r, 15, 0) @[lsu.scala 189:74]
+    dccm_ctl.io.end_addr_r <= _T_74 @[lsu.scala 189:46]
     dccm_ctl.io.stbuf_reqvld_any <= stbuf.io.stbuf_reqvld_any @[lsu.scala 190:46]
     dccm_ctl.io.stbuf_addr_any <= stbuf.io.stbuf_addr_any @[lsu.scala 191:46]
     dccm_ctl.io.stbuf_data_any <= stbuf.io.stbuf_data_any @[lsu.scala 192:46]
@@ -15953,28 +15951,28 @@ circuit lsu :
     bus_intf.io.ldst_dual_d <= ldst_dual_d @[lsu.scala 328:49]
     bus_intf.io.ldst_dual_m <= ldst_dual_m @[lsu.scala 329:49]
     bus_intf.io.ldst_dual_r <= ldst_dual_r @[lsu.scala 330:49]
-    node _T_76 = and(lsu_lsc_ctl.io.addr_external_m, lsu_lsc_ctl.io.lsu_pkt_m.valid) @[lsu.scala 331:119]
-    node _T_77 = bits(_T_76, 0, 0) @[Bitwise.scala 72:15]
-    node _T_78 = mux(_T_77, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_79 = and(lsu_lsc_ctl.io.lsu_addr_m, _T_78) @[lsu.scala 331:78]
-    bus_intf.io.lsu_addr_m <= _T_79 @[lsu.scala 331:49]
-    node _T_80 = bits(lsu_busreq_r, 0, 0) @[Bitwise.scala 72:15]
-    node _T_81 = mux(_T_80, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_82 = and(lsu_lsc_ctl.io.lsu_addr_r, _T_81) @[lsu.scala 332:78]
-    bus_intf.io.lsu_addr_r <= _T_82 @[lsu.scala 332:49]
-    node _T_83 = and(lsu_lsc_ctl.io.addr_external_m, lsu_lsc_ctl.io.lsu_pkt_m.valid) @[lsu.scala 333:119]
-    node _T_84 = bits(_T_83, 0, 0) @[Bitwise.scala 72:15]
-    node _T_85 = mux(_T_84, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_86 = and(lsu_lsc_ctl.io.end_addr_m, _T_85) @[lsu.scala 333:78]
-    bus_intf.io.end_addr_m <= _T_86 @[lsu.scala 333:49]
-    node _T_87 = bits(lsu_busreq_r, 0, 0) @[Bitwise.scala 72:15]
-    node _T_88 = mux(_T_87, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_89 = and(lsu_lsc_ctl.io.end_addr_r, _T_88) @[lsu.scala 334:78]
-    bus_intf.io.end_addr_r <= _T_89 @[lsu.scala 334:49]
-    node _T_90 = bits(lsu_busreq_r, 0, 0) @[Bitwise.scala 72:15]
-    node _T_91 = mux(_T_90, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
-    node _T_92 = and(dccm_ctl.io.store_data_r, _T_91) @[lsu.scala 335:77]
-    bus_intf.io.store_data_r <= _T_92 @[lsu.scala 335:49]
+    node _T_75 = and(lsu_lsc_ctl.io.addr_external_m, lsu_lsc_ctl.io.lsu_pkt_m.valid) @[lsu.scala 331:119]
+    node _T_76 = bits(_T_75, 0, 0) @[Bitwise.scala 72:15]
+    node _T_77 = mux(_T_76, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_78 = and(lsu_lsc_ctl.io.lsu_addr_m, _T_77) @[lsu.scala 331:78]
+    bus_intf.io.lsu_addr_m <= _T_78 @[lsu.scala 331:49]
+    node _T_79 = bits(lsu_busreq_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_80 = mux(_T_79, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_81 = and(lsu_lsc_ctl.io.lsu_addr_r, _T_80) @[lsu.scala 332:78]
+    bus_intf.io.lsu_addr_r <= _T_81 @[lsu.scala 332:49]
+    node _T_82 = and(lsu_lsc_ctl.io.addr_external_m, lsu_lsc_ctl.io.lsu_pkt_m.valid) @[lsu.scala 333:119]
+    node _T_83 = bits(_T_82, 0, 0) @[Bitwise.scala 72:15]
+    node _T_84 = mux(_T_83, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_85 = and(lsu_lsc_ctl.io.end_addr_m, _T_84) @[lsu.scala 333:78]
+    bus_intf.io.end_addr_m <= _T_85 @[lsu.scala 333:49]
+    node _T_86 = bits(lsu_busreq_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_87 = mux(_T_86, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_88 = and(lsu_lsc_ctl.io.end_addr_r, _T_87) @[lsu.scala 334:78]
+    bus_intf.io.end_addr_r <= _T_88 @[lsu.scala 334:49]
+    node _T_89 = bits(lsu_busreq_r, 0, 0) @[Bitwise.scala 72:15]
+    node _T_90 = mux(_T_89, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
+    node _T_91 = and(dccm_ctl.io.store_data_r, _T_90) @[lsu.scala 335:77]
+    bus_intf.io.store_data_r <= _T_91 @[lsu.scala 335:49]
     bus_intf.io.lsu_pkt_m.bits.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_m @[lsu.scala 336:49]
     bus_intf.io.lsu_pkt_m.bits.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu.scala 336:49]
     bus_intf.io.lsu_pkt_m.bits.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.bits.store_data_bypass_d @[lsu.scala 336:49]
@@ -16057,13 +16055,13 @@ circuit lsu :
     io.axi.aw.valid <= bus_intf.io.axi.aw.valid @[lsu.scala 347:31]
     bus_intf.io.axi.aw.ready <= io.axi.aw.ready @[lsu.scala 347:31]
     bus_intf.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[lsu.scala 348:31]
-    reg _T_93 : UInt, clkdomain.io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 350:67]
-    _T_93 <= io.lsu_dma.dma_mem_tag @[lsu.scala 350:67]
-    dma_mem_tag_m <= _T_93 @[lsu.scala 350:57]
-    reg _T_94 : UInt<1>, clkdomain.io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 351:67]
-    _T_94 <= lsu_raw_fwd_hi_m @[lsu.scala 351:67]
-    lsu_raw_fwd_hi_r <= _T_94 @[lsu.scala 351:57]
-    reg _T_95 : UInt<1>, clkdomain.io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 352:67]
-    _T_95 <= lsu_raw_fwd_lo_m @[lsu.scala 352:67]
-    lsu_raw_fwd_lo_r <= _T_95 @[lsu.scala 352:57]
+    reg _T_92 : UInt, clkdomain.io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 350:67]
+    _T_92 <= io.lsu_dma.dma_mem_tag @[lsu.scala 350:67]
+    dma_mem_tag_m <= _T_92 @[lsu.scala 350:57]
+    reg _T_93 : UInt<1>, clkdomain.io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 351:67]
+    _T_93 <= lsu_raw_fwd_hi_m @[lsu.scala 351:67]
+    lsu_raw_fwd_hi_r <= _T_93 @[lsu.scala 351:57]
+    reg _T_94 : UInt<1>, clkdomain.io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu.scala 352:67]
+    _T_94 <= lsu_raw_fwd_lo_m @[lsu.scala 352:67]
+    lsu_raw_fwd_lo_r <= _T_94 @[lsu.scala 352:57]
     

src/main/scala/lib/param.scala

@@ -169,5 +169,13 @@ trait param {
   val BITMANIP_ZBP           =  0x00
   val BITMANIP_ZBR           =  0x00
   val BITMANIP_ZBS           =  0x01
+  val ICACHE_BYPASS_ENABLE   =  0x01
+  val ICACHE_NUM_BYPASS      =  0x02
+  val ICACHE_NUM_BYPASS_WIDTH     =  0x02
+  val ICACHE_TAG_BYPASS_ENABLE    =  0x01
+  val ICACHE_TAG_NUM_BYPASS       =  0x02
+  val ICACHE_TAG_NUM_BYPASS_WIDTH =  0x02
+
+
 
 }