axi to ahb update

axi4_to_ahb.fir

@@ -995,401 +995,397 @@ circuit axi4_to_ahb :
     node _T_445 = and(buf_aligned_in, _T_444) @[axi4_to_ahb.scala 343:60]
     node _T_446 = bits(_T_445, 0, 0) @[axi4_to_ahb.scala 343:100]
     node _T_447 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 343:132]
-    wire _T_448 : UInt<8>
-    _T_448 <= UInt<8>("h00")
-    node _T_449 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 173:50]
-    node _T_450 = eq(_T_449, UInt<8>("h0ff")) @[axi4_to_ahb.scala 173:57]
-    node _T_451 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 173:81]
-    node _T_452 = eq(_T_451, UInt<8>("h0f")) @[axi4_to_ahb.scala 173:88]
-    node _T_453 = or(_T_450, _T_452) @[axi4_to_ahb.scala 173:70]
-    node _T_454 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 173:117]
-    node _T_455 = eq(_T_454, UInt<8>("h03")) @[axi4_to_ahb.scala 173:124]
-    node _T_456 = or(_T_453, _T_455) @[axi4_to_ahb.scala 173:106]
-    node _T_457 = bits(_T_456, 0, 0) @[Bitwise.scala 72:15]
-    node _T_458 = mux(_T_457, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
-    node _T_459 = and(UInt<3>("h00"), _T_458) @[axi4_to_ahb.scala 173:29]
-    node _T_460 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 174:35]
-    node _T_461 = eq(_T_460, UInt<8>("h0c")) @[axi4_to_ahb.scala 174:42]
-    node _T_462 = bits(_T_461, 0, 0) @[Bitwise.scala 72:15]
-    node _T_463 = mux(_T_462, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
-    node _T_464 = and(UInt<2>("h02"), _T_463) @[axi4_to_ahb.scala 174:15]
-    node _T_465 = or(_T_459, _T_464) @[axi4_to_ahb.scala 173:146]
-    node _T_466 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 175:36]
-    node _T_467 = eq(_T_466, UInt<8>("h0f0")) @[axi4_to_ahb.scala 175:43]
-    node _T_468 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 175:67]
-    node _T_469 = eq(_T_468, UInt<8>("h03")) @[axi4_to_ahb.scala 175:74]
-    node _T_470 = or(_T_467, _T_469) @[axi4_to_ahb.scala 175:56]
-    node _T_471 = bits(_T_470, 0, 0) @[Bitwise.scala 72:15]
-    node _T_472 = mux(_T_471, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
-    node _T_473 = and(UInt<3>("h04"), _T_472) @[axi4_to_ahb.scala 175:15]
-    node _T_474 = or(_T_465, _T_473) @[axi4_to_ahb.scala 174:63]
-    node _T_475 = bits(_T_448, 7, 0) @[axi4_to_ahb.scala 176:37]
-    node _T_476 = eq(_T_475, UInt<8>("h0c0")) @[axi4_to_ahb.scala 176:44]
-    node _T_477 = bits(_T_476, 0, 0) @[Bitwise.scala 72:15]
-    node _T_478 = mux(_T_477, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
-    node _T_479 = and(UInt<3>("h06"), _T_478) @[axi4_to_ahb.scala 176:17]
-    node _T_480 = or(_T_474, _T_479) @[axi4_to_ahb.scala 175:96]
-    node _T_481 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 343:152]
-    node _T_482 = mux(_T_446, _T_480, _T_481) @[axi4_to_ahb.scala 343:43]
-    node _T_483 = cat(_T_442, _T_482) @[Cat.scala 29:58]
-    buf_addr_in <= _T_483 @[axi4_to_ahb.scala 343:15]
-    node _T_484 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 344:27]
-    buf_tag_in <= _T_484 @[axi4_to_ahb.scala 344:14]
-    node _T_485 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 345:32]
-    buf_byteen_in <= _T_485 @[axi4_to_ahb.scala 345:17]
-    node _T_486 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 346:33]
-    node _T_487 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 346:59]
-    node _T_488 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 346:80]
-    node _T_489 = mux(_T_486, _T_487, _T_488) @[axi4_to_ahb.scala 346:21]
-    buf_data_in <= _T_489 @[axi4_to_ahb.scala 346:15]
-    node _T_490 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 347:52]
-    node _T_491 = eq(_T_490, UInt<2>("h03")) @[axi4_to_ahb.scala 347:58]
-    node _T_492 = and(buf_aligned_in, _T_491) @[axi4_to_ahb.scala 347:38]
-    node _T_493 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 347:84]
-    node _T_494 = eq(_T_493, UInt<1>("h01")) @[axi4_to_ahb.scala 347:91]
-    node _T_495 = and(_T_492, _T_494) @[axi4_to_ahb.scala 347:71]
-    node _T_496 = bits(_T_495, 0, 0) @[axi4_to_ahb.scala 347:111]
-    node _T_497 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 347:142]
-    wire _T_498 : UInt<8>
-    _T_498 <= UInt<8>("h00")
-    node _T_499 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 166:42]
-    node _T_500 = eq(_T_499, UInt<8>("h0ff")) @[axi4_to_ahb.scala 166:49]
-    node _T_501 = bits(_T_500, 0, 0) @[Bitwise.scala 72:15]
-    node _T_502 = mux(_T_501, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_503 = and(UInt<2>("h03"), _T_502) @[axi4_to_ahb.scala 166:25]
-    node _T_504 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 167:35]
-    node _T_505 = eq(_T_504, UInt<8>("h0f0")) @[axi4_to_ahb.scala 167:42]
-    node _T_506 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 167:64]
-    node _T_507 = eq(_T_506, UInt<8>("h0f")) @[axi4_to_ahb.scala 167:71]
-    node _T_508 = or(_T_505, _T_507) @[axi4_to_ahb.scala 167:55]
-    node _T_509 = bits(_T_508, 0, 0) @[Bitwise.scala 72:15]
-    node _T_510 = mux(_T_509, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_511 = and(UInt<2>("h02"), _T_510) @[axi4_to_ahb.scala 167:16]
-    node _T_512 = or(_T_503, _T_511) @[axi4_to_ahb.scala 166:64]
-    node _T_513 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 168:40]
-    node _T_514 = eq(_T_513, UInt<8>("h0c0")) @[axi4_to_ahb.scala 168:47]
-    node _T_515 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 168:69]
-    node _T_516 = eq(_T_515, UInt<6>("h030")) @[axi4_to_ahb.scala 168:76]
-    node _T_517 = or(_T_514, _T_516) @[axi4_to_ahb.scala 168:60]
-    node _T_518 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 168:98]
-    node _T_519 = eq(_T_518, UInt<8>("h0c")) @[axi4_to_ahb.scala 168:105]
-    node _T_520 = or(_T_517, _T_519) @[axi4_to_ahb.scala 168:89]
-    node _T_521 = bits(_T_498, 7, 0) @[axi4_to_ahb.scala 168:132]
-    node _T_522 = eq(_T_521, UInt<8>("h03")) @[axi4_to_ahb.scala 168:139]
-    node _T_523 = or(_T_520, _T_522) @[axi4_to_ahb.scala 168:123]
-    node _T_524 = bits(_T_523, 0, 0) @[Bitwise.scala 72:15]
-    node _T_525 = mux(_T_524, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_526 = and(UInt<2>("h01"), _T_525) @[axi4_to_ahb.scala 168:21]
-    node _T_527 = or(_T_512, _T_526) @[axi4_to_ahb.scala 167:93]
-    node _T_528 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 347:161]
-    node _T_529 = mux(_T_496, _T_527, _T_528) @[axi4_to_ahb.scala 347:21]
-    buf_size_in <= _T_529 @[axi4_to_ahb.scala 347:15]
-    node _T_530 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 348:32]
-    node _T_531 = eq(_T_530, UInt<1>("h00")) @[axi4_to_ahb.scala 348:39]
-    node _T_532 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:17]
-    node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 349:24]
-    node _T_534 = or(_T_531, _T_533) @[axi4_to_ahb.scala 348:48]
-    node _T_535 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:47]
-    node _T_536 = eq(_T_535, UInt<2>("h01")) @[axi4_to_ahb.scala 349:54]
-    node _T_537 = or(_T_534, _T_536) @[axi4_to_ahb.scala 349:33]
-    node _T_538 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:86]
-    node _T_539 = eq(_T_538, UInt<2>("h02")) @[axi4_to_ahb.scala 349:93]
-    node _T_540 = or(_T_537, _T_539) @[axi4_to_ahb.scala 349:72]
-    node _T_541 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 350:18]
-    node _T_542 = eq(_T_541, UInt<2>("h03")) @[axi4_to_ahb.scala 350:25]
-    node _T_543 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:55]
-    node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 350:62]
-    node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:90]
-    node _T_546 = eq(_T_545, UInt<4>("h0c")) @[axi4_to_ahb.scala 350:97]
-    node _T_547 = or(_T_544, _T_546) @[axi4_to_ahb.scala 350:74]
-    node _T_548 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:125]
-    node _T_549 = eq(_T_548, UInt<6>("h030")) @[axi4_to_ahb.scala 350:132]
-    node _T_550 = or(_T_547, _T_549) @[axi4_to_ahb.scala 350:109]
-    node _T_551 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:161]
-    node _T_552 = eq(_T_551, UInt<8>("h0c0")) @[axi4_to_ahb.scala 350:168]
-    node _T_553 = or(_T_550, _T_552) @[axi4_to_ahb.scala 350:145]
-    node _T_554 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 351:21]
-    node _T_555 = eq(_T_554, UInt<4>("h0f")) @[axi4_to_ahb.scala 351:28]
-    node _T_556 = or(_T_553, _T_555) @[axi4_to_ahb.scala 350:181]
-    node _T_557 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 351:56]
-    node _T_558 = eq(_T_557, UInt<8>("h0f0")) @[axi4_to_ahb.scala 351:63]
-    node _T_559 = or(_T_556, _T_558) @[axi4_to_ahb.scala 351:40]
-    node _T_560 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 351:92]
-    node _T_561 = eq(_T_560, UInt<8>("h0ff")) @[axi4_to_ahb.scala 351:99]
-    node _T_562 = or(_T_559, _T_561) @[axi4_to_ahb.scala 351:76]
-    node _T_563 = and(_T_542, _T_562) @[axi4_to_ahb.scala 350:38]
-    node _T_564 = or(_T_540, _T_563) @[axi4_to_ahb.scala 349:106]
-    buf_aligned_in <= _T_564 @[axi4_to_ahb.scala 348:18]
-    node _T_565 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 353:39]
-    node _T_566 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 353:58]
-    node _T_567 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 353:83]
-    node _T_568 = cat(_T_566, _T_567) @[Cat.scala 29:58]
-    node _T_569 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 353:104]
-    node _T_570 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 353:129]
-    node _T_571 = cat(_T_569, _T_570) @[Cat.scala 29:58]
-    node _T_572 = mux(_T_565, _T_568, _T_571) @[axi4_to_ahb.scala 353:22]
-    io.ahb_haddr <= _T_572 @[axi4_to_ahb.scala 353:16]
-    node _T_573 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 354:39]
-    node _T_574 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15]
-    node _T_575 = mux(_T_574, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_576 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 354:90]
-    node _T_577 = and(_T_575, _T_576) @[axi4_to_ahb.scala 354:77]
-    node _T_578 = cat(UInt<1>("h00"), _T_577) @[Cat.scala 29:58]
-    node _T_579 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15]
-    node _T_580 = mux(_T_579, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_581 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 354:144]
-    node _T_582 = and(_T_580, _T_581) @[axi4_to_ahb.scala 354:134]
-    node _T_583 = cat(UInt<1>("h00"), _T_582) @[Cat.scala 29:58]
-    node _T_584 = mux(_T_573, _T_578, _T_583) @[axi4_to_ahb.scala 354:22]
-    io.ahb_hsize <= _T_584 @[axi4_to_ahb.scala 354:16]
+    node _T_448 = bits(_T_447, 7, 0) @[axi4_to_ahb.scala 173:50]
+    node _T_449 = eq(_T_448, UInt<8>("h0ff")) @[axi4_to_ahb.scala 173:57]
+    node _T_450 = bits(_T_447, 7, 0) @[axi4_to_ahb.scala 173:81]
+    node _T_451 = eq(_T_450, UInt<8>("h0f")) @[axi4_to_ahb.scala 173:88]
+    node _T_452 = or(_T_449, _T_451) @[axi4_to_ahb.scala 173:70]
+    node _T_453 = bits(_T_447, 7, 0) @[axi4_to_ahb.scala 173:117]
+    node _T_454 = eq(_T_453, UInt<8>("h03")) @[axi4_to_ahb.scala 173:124]
+    node _T_455 = or(_T_452, _T_454) @[axi4_to_ahb.scala 173:106]
+    node _T_456 = bits(_T_455, 0, 0) @[Bitwise.scala 72:15]
+    node _T_457 = mux(_T_456, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_458 = and(UInt<3>("h00"), _T_457) @[axi4_to_ahb.scala 173:29]
+    node _T_459 = bits(_T_447, 7, 0) @[axi4_to_ahb.scala 174:35]
+    node _T_460 = eq(_T_459, UInt<8>("h0c")) @[axi4_to_ahb.scala 174:42]
+    node _T_461 = bits(_T_460, 0, 0) @[Bitwise.scala 72:15]
+    node _T_462 = mux(_T_461, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_463 = and(UInt<2>("h02"), _T_462) @[axi4_to_ahb.scala 174:15]
+    node _T_464 = or(_T_458, _T_463) @[axi4_to_ahb.scala 173:146]
+    node _T_465 = bits(_T_447, 7, 0) @[axi4_to_ahb.scala 175:36]
+    node _T_466 = eq(_T_465, UInt<8>("h0f0")) @[axi4_to_ahb.scala 175:43]
+    node _T_467 = bits(_T_447, 7, 0) @[axi4_to_ahb.scala 175:67]
+    node _T_468 = eq(_T_467, UInt<8>("h03")) @[axi4_to_ahb.scala 175:74]
+    node _T_469 = or(_T_466, _T_468) @[axi4_to_ahb.scala 175:56]
+    node _T_470 = bits(_T_469, 0, 0) @[Bitwise.scala 72:15]
+    node _T_471 = mux(_T_470, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_472 = and(UInt<3>("h04"), _T_471) @[axi4_to_ahb.scala 175:15]
+    node _T_473 = or(_T_464, _T_472) @[axi4_to_ahb.scala 174:63]
+    node _T_474 = bits(_T_447, 7, 0) @[axi4_to_ahb.scala 176:37]
+    node _T_475 = eq(_T_474, UInt<8>("h0c0")) @[axi4_to_ahb.scala 176:44]
+    node _T_476 = bits(_T_475, 0, 0) @[Bitwise.scala 72:15]
+    node _T_477 = mux(_T_476, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
+    node _T_478 = and(UInt<3>("h06"), _T_477) @[axi4_to_ahb.scala 176:17]
+    node _T_479 = or(_T_473, _T_478) @[axi4_to_ahb.scala 175:96]
+    node _T_480 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 343:152]
+    node _T_481 = mux(_T_446, _T_479, _T_480) @[axi4_to_ahb.scala 343:43]
+    node _T_482 = cat(_T_442, _T_481) @[Cat.scala 29:58]
+    buf_addr_in <= _T_482 @[axi4_to_ahb.scala 343:15]
+    node _T_483 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 344:27]
+    buf_tag_in <= _T_483 @[axi4_to_ahb.scala 344:14]
+    node _T_484 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 345:32]
+    buf_byteen_in <= _T_484 @[axi4_to_ahb.scala 345:17]
+    node _T_485 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 346:33]
+    node _T_486 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 346:59]
+    node _T_487 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 346:80]
+    node _T_488 = mux(_T_485, _T_486, _T_487) @[axi4_to_ahb.scala 346:21]
+    buf_data_in <= _T_488 @[axi4_to_ahb.scala 346:15]
+    node _T_489 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 347:52]
+    node _T_490 = eq(_T_489, UInt<2>("h03")) @[axi4_to_ahb.scala 347:58]
+    node _T_491 = and(buf_aligned_in, _T_490) @[axi4_to_ahb.scala 347:38]
+    node _T_492 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 347:84]
+    node _T_493 = eq(_T_492, UInt<1>("h01")) @[axi4_to_ahb.scala 347:91]
+    node _T_494 = and(_T_491, _T_493) @[axi4_to_ahb.scala 347:71]
+    node _T_495 = bits(_T_494, 0, 0) @[axi4_to_ahb.scala 347:111]
+    node _T_496 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 347:142]
+    node _T_497 = bits(_T_496, 7, 0) @[axi4_to_ahb.scala 166:42]
+    node _T_498 = eq(_T_497, UInt<8>("h0ff")) @[axi4_to_ahb.scala 166:49]
+    node _T_499 = bits(_T_498, 0, 0) @[Bitwise.scala 72:15]
+    node _T_500 = mux(_T_499, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_501 = and(UInt<2>("h03"), _T_500) @[axi4_to_ahb.scala 166:25]
+    node _T_502 = bits(_T_496, 7, 0) @[axi4_to_ahb.scala 167:35]
+    node _T_503 = eq(_T_502, UInt<8>("h0f0")) @[axi4_to_ahb.scala 167:42]
+    node _T_504 = bits(_T_496, 7, 0) @[axi4_to_ahb.scala 167:64]
+    node _T_505 = eq(_T_504, UInt<8>("h0f")) @[axi4_to_ahb.scala 167:71]
+    node _T_506 = or(_T_503, _T_505) @[axi4_to_ahb.scala 167:55]
+    node _T_507 = bits(_T_506, 0, 0) @[Bitwise.scala 72:15]
+    node _T_508 = mux(_T_507, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_509 = and(UInt<2>("h02"), _T_508) @[axi4_to_ahb.scala 167:16]
+    node _T_510 = or(_T_501, _T_509) @[axi4_to_ahb.scala 166:64]
+    node _T_511 = bits(_T_496, 7, 0) @[axi4_to_ahb.scala 168:40]
+    node _T_512 = eq(_T_511, UInt<8>("h0c0")) @[axi4_to_ahb.scala 168:47]
+    node _T_513 = bits(_T_496, 7, 0) @[axi4_to_ahb.scala 168:69]
+    node _T_514 = eq(_T_513, UInt<6>("h030")) @[axi4_to_ahb.scala 168:76]
+    node _T_515 = or(_T_512, _T_514) @[axi4_to_ahb.scala 168:60]
+    node _T_516 = bits(_T_496, 7, 0) @[axi4_to_ahb.scala 168:98]
+    node _T_517 = eq(_T_516, UInt<8>("h0c")) @[axi4_to_ahb.scala 168:105]
+    node _T_518 = or(_T_515, _T_517) @[axi4_to_ahb.scala 168:89]
+    node _T_519 = bits(_T_496, 7, 0) @[axi4_to_ahb.scala 168:132]
+    node _T_520 = eq(_T_519, UInt<8>("h03")) @[axi4_to_ahb.scala 168:139]
+    node _T_521 = or(_T_518, _T_520) @[axi4_to_ahb.scala 168:123]
+    node _T_522 = bits(_T_521, 0, 0) @[Bitwise.scala 72:15]
+    node _T_523 = mux(_T_522, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_524 = and(UInt<2>("h01"), _T_523) @[axi4_to_ahb.scala 168:21]
+    node _T_525 = or(_T_510, _T_524) @[axi4_to_ahb.scala 167:93]
+    node _T_526 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 347:161]
+    node _T_527 = mux(_T_495, _T_525, _T_526) @[axi4_to_ahb.scala 347:21]
+    buf_size_in <= _T_527 @[axi4_to_ahb.scala 347:15]
+    node _T_528 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 348:32]
+    node _T_529 = eq(_T_528, UInt<1>("h00")) @[axi4_to_ahb.scala 348:39]
+    node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:17]
+    node _T_531 = eq(_T_530, UInt<1>("h00")) @[axi4_to_ahb.scala 349:24]
+    node _T_532 = or(_T_529, _T_531) @[axi4_to_ahb.scala 348:48]
+    node _T_533 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:47]
+    node _T_534 = eq(_T_533, UInt<2>("h01")) @[axi4_to_ahb.scala 349:54]
+    node _T_535 = or(_T_532, _T_534) @[axi4_to_ahb.scala 349:33]
+    node _T_536 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 349:86]
+    node _T_537 = eq(_T_536, UInt<2>("h02")) @[axi4_to_ahb.scala 349:93]
+    node _T_538 = or(_T_535, _T_537) @[axi4_to_ahb.scala 349:72]
+    node _T_539 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 350:18]
+    node _T_540 = eq(_T_539, UInt<2>("h03")) @[axi4_to_ahb.scala 350:25]
+    node _T_541 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:55]
+    node _T_542 = eq(_T_541, UInt<2>("h03")) @[axi4_to_ahb.scala 350:62]
+    node _T_543 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:90]
+    node _T_544 = eq(_T_543, UInt<4>("h0c")) @[axi4_to_ahb.scala 350:97]
+    node _T_545 = or(_T_542, _T_544) @[axi4_to_ahb.scala 350:74]
+    node _T_546 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:125]
+    node _T_547 = eq(_T_546, UInt<6>("h030")) @[axi4_to_ahb.scala 350:132]
+    node _T_548 = or(_T_545, _T_547) @[axi4_to_ahb.scala 350:109]
+    node _T_549 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 350:161]
+    node _T_550 = eq(_T_549, UInt<8>("h0c0")) @[axi4_to_ahb.scala 350:168]
+    node _T_551 = or(_T_548, _T_550) @[axi4_to_ahb.scala 350:145]
+    node _T_552 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 351:21]
+    node _T_553 = eq(_T_552, UInt<4>("h0f")) @[axi4_to_ahb.scala 351:28]
+    node _T_554 = or(_T_551, _T_553) @[axi4_to_ahb.scala 350:181]
+    node _T_555 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 351:56]
+    node _T_556 = eq(_T_555, UInt<8>("h0f0")) @[axi4_to_ahb.scala 351:63]
+    node _T_557 = or(_T_554, _T_556) @[axi4_to_ahb.scala 351:40]
+    node _T_558 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 351:92]
+    node _T_559 = eq(_T_558, UInt<8>("h0ff")) @[axi4_to_ahb.scala 351:99]
+    node _T_560 = or(_T_557, _T_559) @[axi4_to_ahb.scala 351:76]
+    node _T_561 = and(_T_540, _T_560) @[axi4_to_ahb.scala 350:38]
+    node _T_562 = or(_T_538, _T_561) @[axi4_to_ahb.scala 349:106]
+    buf_aligned_in <= _T_562 @[axi4_to_ahb.scala 348:18]
+    node _T_563 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 353:39]
+    node _T_564 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 353:58]
+    node _T_565 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 353:83]
+    node _T_566 = cat(_T_564, _T_565) @[Cat.scala 29:58]
+    node _T_567 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 353:104]
+    node _T_568 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 353:129]
+    node _T_569 = cat(_T_567, _T_568) @[Cat.scala 29:58]
+    node _T_570 = mux(_T_563, _T_566, _T_569) @[axi4_to_ahb.scala 353:22]
+    io.ahb_haddr <= _T_570 @[axi4_to_ahb.scala 353:16]
+    node _T_571 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 354:39]
+    node _T_572 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15]
+    node _T_573 = mux(_T_572, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_574 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 354:90]
+    node _T_575 = and(_T_573, _T_574) @[axi4_to_ahb.scala 354:77]
+    node _T_576 = cat(UInt<1>("h00"), _T_575) @[Cat.scala 29:58]
+    node _T_577 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15]
+    node _T_578 = mux(_T_577, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_579 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 354:144]
+    node _T_580 = and(_T_578, _T_579) @[axi4_to_ahb.scala 354:134]
+    node _T_581 = cat(UInt<1>("h00"), _T_580) @[Cat.scala 29:58]
+    node _T_582 = mux(_T_571, _T_576, _T_581) @[axi4_to_ahb.scala 354:22]
+    io.ahb_hsize <= _T_582 @[axi4_to_ahb.scala 354:16]
     io.ahb_hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 356:17]
     io.ahb_hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 357:20]
-    node _T_585 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 358:47]
-    node _T_586 = not(_T_585) @[axi4_to_ahb.scala 358:33]
-    node _T_587 = cat(UInt<1>("h01"), _T_586) @[Cat.scala 29:58]
-    io.ahb_hprot <= _T_587 @[axi4_to_ahb.scala 358:16]
-    node _T_588 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 359:40]
-    node _T_589 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 359:55]
-    node _T_590 = eq(_T_589, UInt<1>("h01")) @[axi4_to_ahb.scala 359:62]
-    node _T_591 = mux(_T_588, _T_590, buf_write) @[axi4_to_ahb.scala 359:23]
-    io.ahb_hwrite <= _T_591 @[axi4_to_ahb.scala 359:17]
-    node _T_592 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 360:28]
-    io.ahb_hwdata <= _T_592 @[axi4_to_ahb.scala 360:17]
+    node _T_583 = bits(io.axi_arprot, 2, 2) @[axi4_to_ahb.scala 358:47]
+    node _T_584 = not(_T_583) @[axi4_to_ahb.scala 358:33]
+    node _T_585 = cat(UInt<1>("h01"), _T_584) @[Cat.scala 29:58]
+    io.ahb_hprot <= _T_585 @[axi4_to_ahb.scala 358:16]
+    node _T_586 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 359:40]
+    node _T_587 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 359:55]
+    node _T_588 = eq(_T_587, UInt<1>("h01")) @[axi4_to_ahb.scala 359:62]
+    node _T_589 = mux(_T_586, _T_588, buf_write) @[axi4_to_ahb.scala 359:23]
+    io.ahb_hwrite <= _T_589 @[axi4_to_ahb.scala 359:17]
+    node _T_590 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 360:28]
+    io.ahb_hwdata <= _T_590 @[axi4_to_ahb.scala 360:17]
     slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 362:15]
-    node _T_593 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 363:43]
-    node _T_594 = mux(_T_593, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 363:23]
-    node _T_595 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15]
-    node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
-    node _T_597 = and(_T_596, UInt<2>("h02")) @[axi4_to_ahb.scala 363:88]
-    node _T_598 = cat(_T_594, _T_597) @[Cat.scala 29:58]
-    slave_opc <= _T_598 @[axi4_to_ahb.scala 363:13]
-    node _T_599 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 364:41]
-    node _T_600 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 364:66]
-    node _T_601 = cat(_T_600, _T_600) @[Cat.scala 29:58]
-    node _T_602 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 364:91]
-    node _T_603 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 364:110]
-    node _T_604 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 364:131]
-    node _T_605 = mux(_T_602, _T_603, _T_604) @[axi4_to_ahb.scala 364:79]
-    node _T_606 = mux(_T_599, _T_601, _T_605) @[axi4_to_ahb.scala 364:21]
-    slave_rdata <= _T_606 @[axi4_to_ahb.scala 364:15]
-    node _T_607 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 365:26]
-    slave_tag <= _T_607 @[axi4_to_ahb.scala 365:13]
-    node _T_608 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 367:33]
-    node _T_609 = neq(_T_608, UInt<1>("h00")) @[axi4_to_ahb.scala 367:40]
-    node _T_610 = and(_T_609, io.ahb_hready) @[axi4_to_ahb.scala 367:52]
-    node _T_611 = and(_T_610, io.ahb_hwrite) @[axi4_to_ahb.scala 367:68]
-    last_addr_en <= _T_611 @[axi4_to_ahb.scala 367:16]
-    node _T_612 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 369:30]
-    node _T_613 = and(_T_612, master_ready) @[axi4_to_ahb.scala 369:47]
-    wrbuf_en <= _T_613 @[axi4_to_ahb.scala 369:12]
-    node _T_614 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 370:34]
-    node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 370:50]
-    wrbuf_data_en <= _T_615 @[axi4_to_ahb.scala 370:17]
-    node _T_616 = and(master_valid, master_ready) @[axi4_to_ahb.scala 371:34]
-    node _T_617 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 371:62]
-    node _T_618 = eq(_T_617, UInt<1>("h01")) @[axi4_to_ahb.scala 371:69]
-    node _T_619 = and(_T_616, _T_618) @[axi4_to_ahb.scala 371:49]
-    wrbuf_cmd_sent <= _T_619 @[axi4_to_ahb.scala 371:18]
-    node _T_620 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 372:33]
-    node _T_621 = and(wrbuf_cmd_sent, _T_620) @[axi4_to_ahb.scala 372:31]
-    wrbuf_rst <= _T_621 @[axi4_to_ahb.scala 372:13]
-    node _T_622 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 374:35]
-    node _T_623 = and(wrbuf_vld, _T_622) @[axi4_to_ahb.scala 374:33]
-    node _T_624 = eq(_T_623, UInt<1>("h00")) @[axi4_to_ahb.scala 374:21]
-    node _T_625 = and(_T_624, master_ready) @[axi4_to_ahb.scala 374:52]
-    io.axi_awready <= _T_625 @[axi4_to_ahb.scala 374:18]
-    node _T_626 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 375:39]
-    node _T_627 = and(wrbuf_data_vld, _T_626) @[axi4_to_ahb.scala 375:37]
-    node _T_628 = eq(_T_627, UInt<1>("h00")) @[axi4_to_ahb.scala 375:20]
-    node _T_629 = and(_T_628, master_ready) @[axi4_to_ahb.scala 375:56]
-    io.axi_wready <= _T_629 @[axi4_to_ahb.scala 375:17]
-    node _T_630 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 376:33]
-    node _T_631 = eq(_T_630, UInt<1>("h00")) @[axi4_to_ahb.scala 376:21]
-    node _T_632 = and(_T_631, master_ready) @[axi4_to_ahb.scala 376:51]
-    io.axi_arready <= _T_632 @[axi4_to_ahb.scala 376:18]
+    node _T_591 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 363:43]
+    node _T_592 = mux(_T_591, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 363:23]
+    node _T_593 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15]
+    node _T_594 = mux(_T_593, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_595 = and(_T_594, UInt<2>("h02")) @[axi4_to_ahb.scala 363:88]
+    node _T_596 = cat(_T_592, _T_595) @[Cat.scala 29:58]
+    slave_opc <= _T_596 @[axi4_to_ahb.scala 363:13]
+    node _T_597 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 364:41]
+    node _T_598 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 364:66]
+    node _T_599 = cat(_T_598, _T_598) @[Cat.scala 29:58]
+    node _T_600 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 364:91]
+    node _T_601 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 364:110]
+    node _T_602 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 364:131]
+    node _T_603 = mux(_T_600, _T_601, _T_602) @[axi4_to_ahb.scala 364:79]
+    node _T_604 = mux(_T_597, _T_599, _T_603) @[axi4_to_ahb.scala 364:21]
+    slave_rdata <= _T_604 @[axi4_to_ahb.scala 364:15]
+    node _T_605 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 365:26]
+    slave_tag <= _T_605 @[axi4_to_ahb.scala 365:13]
+    node _T_606 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 367:33]
+    node _T_607 = neq(_T_606, UInt<1>("h00")) @[axi4_to_ahb.scala 367:40]
+    node _T_608 = and(_T_607, io.ahb_hready) @[axi4_to_ahb.scala 367:52]
+    node _T_609 = and(_T_608, io.ahb_hwrite) @[axi4_to_ahb.scala 367:68]
+    last_addr_en <= _T_609 @[axi4_to_ahb.scala 367:16]
+    node _T_610 = and(io.axi_awvalid, io.axi_awready) @[axi4_to_ahb.scala 369:30]
+    node _T_611 = and(_T_610, master_ready) @[axi4_to_ahb.scala 369:47]
+    wrbuf_en <= _T_611 @[axi4_to_ahb.scala 369:12]
+    node _T_612 = and(io.axi_wvalid, io.axi_wready) @[axi4_to_ahb.scala 370:34]
+    node _T_613 = and(_T_612, master_ready) @[axi4_to_ahb.scala 370:50]
+    wrbuf_data_en <= _T_613 @[axi4_to_ahb.scala 370:17]
+    node _T_614 = and(master_valid, master_ready) @[axi4_to_ahb.scala 371:34]
+    node _T_615 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 371:62]
+    node _T_616 = eq(_T_615, UInt<1>("h01")) @[axi4_to_ahb.scala 371:69]
+    node _T_617 = and(_T_614, _T_616) @[axi4_to_ahb.scala 371:49]
+    wrbuf_cmd_sent <= _T_617 @[axi4_to_ahb.scala 371:18]
+    node _T_618 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 372:33]
+    node _T_619 = and(wrbuf_cmd_sent, _T_618) @[axi4_to_ahb.scala 372:31]
+    wrbuf_rst <= _T_619 @[axi4_to_ahb.scala 372:13]
+    node _T_620 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 374:35]
+    node _T_621 = and(wrbuf_vld, _T_620) @[axi4_to_ahb.scala 374:33]
+    node _T_622 = eq(_T_621, UInt<1>("h00")) @[axi4_to_ahb.scala 374:21]
+    node _T_623 = and(_T_622, master_ready) @[axi4_to_ahb.scala 374:52]
+    io.axi_awready <= _T_623 @[axi4_to_ahb.scala 374:18]
+    node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 375:39]
+    node _T_625 = and(wrbuf_data_vld, _T_624) @[axi4_to_ahb.scala 375:37]
+    node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 375:20]
+    node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 375:56]
+    io.axi_wready <= _T_627 @[axi4_to_ahb.scala 375:17]
+    node _T_628 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 376:33]
+    node _T_629 = eq(_T_628, UInt<1>("h00")) @[axi4_to_ahb.scala 376:21]
+    node _T_630 = and(_T_629, master_ready) @[axi4_to_ahb.scala 376:51]
+    io.axi_arready <= _T_630 @[axi4_to_ahb.scala 376:18]
     io.axi_rlast <= UInt<1>("h01") @[axi4_to_ahb.scala 377:16]
-    node _T_633 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 380:68]
-    node _T_634 = mux(_T_633, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 380:52]
-    node _T_635 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 380:88]
-    node _T_636 = and(_T_634, _T_635) @[axi4_to_ahb.scala 380:86]
-    reg _T_637 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 380:48]
-    _T_637 <= _T_636 @[axi4_to_ahb.scala 380:48]
-    wrbuf_vld <= _T_637 @[axi4_to_ahb.scala 380:18]
-    node _T_638 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 381:73]
-    node _T_639 = mux(_T_638, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 381:52]
-    node _T_640 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 381:99]
-    node _T_641 = and(_T_639, _T_640) @[axi4_to_ahb.scala 381:97]
-    reg _T_642 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 381:48]
-    _T_642 <= _T_641 @[axi4_to_ahb.scala 381:48]
-    wrbuf_data_vld <= _T_642 @[axi4_to_ahb.scala 381:18]
-    node _T_643 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 383:57]
-    node _T_644 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 383:91]
-    reg _T_645 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_644 : @[Reg.scala 28:19]
-      _T_645 <= _T_643 @[Reg.scala 28:23]
+    node _T_631 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 380:68]
+    node _T_632 = mux(_T_631, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 380:52]
+    node _T_633 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 380:88]
+    node _T_634 = and(_T_632, _T_633) @[axi4_to_ahb.scala 380:86]
+    reg _T_635 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 380:48]
+    _T_635 <= _T_634 @[axi4_to_ahb.scala 380:48]
+    wrbuf_vld <= _T_635 @[axi4_to_ahb.scala 380:18]
+    node _T_636 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 381:73]
+    node _T_637 = mux(_T_636, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 381:52]
+    node _T_638 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 381:99]
+    node _T_639 = and(_T_637, _T_638) @[axi4_to_ahb.scala 381:97]
+    reg _T_640 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 381:48]
+    _T_640 <= _T_639 @[axi4_to_ahb.scala 381:48]
+    wrbuf_data_vld <= _T_640 @[axi4_to_ahb.scala 381:18]
+    node _T_641 = bits(io.axi_awid, 0, 0) @[axi4_to_ahb.scala 383:57]
+    node _T_642 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 383:91]
+    reg _T_643 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_642 : @[Reg.scala 28:19]
+      _T_643 <= _T_641 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    wrbuf_tag <= _T_645 @[axi4_to_ahb.scala 383:13]
-    node _T_646 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 384:60]
-    node _T_647 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 384:88]
-    reg _T_648 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_647 : @[Reg.scala 28:19]
-      _T_648 <= _T_646 @[Reg.scala 28:23]
+    wrbuf_tag <= _T_643 @[axi4_to_ahb.scala 383:13]
+    node _T_644 = bits(io.axi_awsize, 2, 0) @[axi4_to_ahb.scala 384:60]
+    node _T_645 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 384:88]
+    reg _T_646 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_645 : @[Reg.scala 28:19]
+      _T_646 <= _T_644 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    wrbuf_size <= _T_648 @[axi4_to_ahb.scala 384:14]
-    node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 386:48]
+    wrbuf_size <= _T_646 @[axi4_to_ahb.scala 384:14]
+    node _T_647 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 386:48]
     inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23]
     rvclkhdr_2.clock <= clock
     rvclkhdr_2.reset <= reset
     rvclkhdr_2.io.clk <= bus_clk @[el2_lib.scala 510:18]
-    rvclkhdr_2.io.en <= _T_649 @[el2_lib.scala 511:17]
+    rvclkhdr_2.io.en <= _T_647 @[el2_lib.scala 511:17]
     rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
-    reg _T_650 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
-    _T_650 <= io.axi_awaddr @[el2_lib.scala 514:16]
-    wrbuf_addr <= _T_650 @[axi4_to_ahb.scala 386:14]
-    node _T_651 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 387:52]
+    reg _T_648 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
+    _T_648 <= io.axi_awaddr @[el2_lib.scala 514:16]
+    wrbuf_addr <= _T_648 @[axi4_to_ahb.scala 386:14]
+    node _T_649 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 387:52]
     inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23]
     rvclkhdr_3.clock <= clock
     rvclkhdr_3.reset <= reset
     rvclkhdr_3.io.clk <= bus_clk @[el2_lib.scala 510:18]
-    rvclkhdr_3.io.en <= _T_651 @[el2_lib.scala 511:17]
+    rvclkhdr_3.io.en <= _T_649 @[el2_lib.scala 511:17]
     rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
-    reg _T_652 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
-    _T_652 <= io.axi_wdata @[el2_lib.scala 514:16]
-    wrbuf_data <= _T_652 @[axi4_to_ahb.scala 387:14]
-    node _T_653 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 390:27]
-    node _T_654 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 390:60]
-    reg _T_655 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_654 : @[Reg.scala 28:19]
-      _T_655 <= _T_653 @[Reg.scala 28:23]
+    reg _T_650 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
+    _T_650 <= io.axi_wdata @[el2_lib.scala 514:16]
+    wrbuf_data <= _T_650 @[axi4_to_ahb.scala 387:14]
+    node _T_651 = bits(io.axi_wstrb, 7, 0) @[axi4_to_ahb.scala 390:27]
+    node _T_652 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 390:60]
+    reg _T_653 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_652 : @[Reg.scala 28:19]
+      _T_653 <= _T_651 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    wrbuf_byteen <= _T_655 @[axi4_to_ahb.scala 389:16]
-    node _T_656 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 393:27]
-    node _T_657 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 393:60]
-    reg _T_658 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    wrbuf_byteen <= _T_653 @[axi4_to_ahb.scala 389:16]
+    node _T_654 = bits(io.ahb_haddr, 31, 0) @[axi4_to_ahb.scala 393:27]
+    node _T_655 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 393:60]
+    reg _T_656 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_655 : @[Reg.scala 28:19]
+      _T_656 <= _T_654 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    last_bus_addr <= _T_656 @[axi4_to_ahb.scala 392:17]
+    node _T_657 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 401:50]
+    reg _T_658 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_657 : @[Reg.scala 28:19]
-      _T_658 <= _T_656 @[Reg.scala 28:23]
+      _T_658 <= buf_write_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    last_bus_addr <= _T_658 @[axi4_to_ahb.scala 392:17]
-    node _T_659 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 401:50]
-    reg _T_660 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_659 : @[Reg.scala 28:19]
-      _T_660 <= buf_write_in @[Reg.scala 28:23]
+    buf_write <= _T_658 @[axi4_to_ahb.scala 400:13]
+    node _T_659 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 404:25]
+    node _T_660 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 404:60]
+    reg _T_661 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_660 : @[Reg.scala 28:19]
+      _T_661 <= _T_659 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    buf_write <= _T_660 @[axi4_to_ahb.scala 400:13]
-    node _T_661 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 404:25]
-    node _T_662 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 404:60]
-    reg _T_663 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_662 : @[Reg.scala 28:19]
-      _T_663 <= _T_661 @[Reg.scala 28:23]
-      skip @[Reg.scala 28:19]
-    buf_tag <= _T_663 @[axi4_to_ahb.scala 403:11]
-    node _T_664 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 407:33]
-    node _T_665 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 407:52]
-    node _T_666 = bits(_T_665, 0, 0) @[axi4_to_ahb.scala 407:69]
+    buf_tag <= _T_661 @[axi4_to_ahb.scala 403:11]
+    node _T_662 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 407:33]
+    node _T_663 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 407:52]
+    node _T_664 = bits(_T_663, 0, 0) @[axi4_to_ahb.scala 407:69]
     inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23]
     rvclkhdr_4.clock <= clock
     rvclkhdr_4.reset <= reset
     rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18]
-    rvclkhdr_4.io.en <= _T_666 @[el2_lib.scala 511:17]
+    rvclkhdr_4.io.en <= _T_664 @[el2_lib.scala 511:17]
     rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
-    reg _T_667 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
-    _T_667 <= _T_664 @[el2_lib.scala 514:16]
-    buf_addr <= _T_667 @[axi4_to_ahb.scala 407:12]
-    node _T_668 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 410:26]
-    node _T_669 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 410:55]
+    reg _T_665 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
+    _T_665 <= _T_662 @[el2_lib.scala 514:16]
+    buf_addr <= _T_665 @[axi4_to_ahb.scala 407:12]
+    node _T_666 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 410:26]
+    node _T_667 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 410:55]
+    reg _T_668 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_667 : @[Reg.scala 28:19]
+      _T_668 <= _T_666 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    buf_size <= _T_668 @[axi4_to_ahb.scala 409:12]
+    node _T_669 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 413:52]
     reg _T_670 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_669 : @[Reg.scala 28:19]
-      _T_670 <= _T_668 @[Reg.scala 28:23]
+      _T_670 <= buf_aligned_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    buf_size <= _T_670 @[axi4_to_ahb.scala 409:12]
-    node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 413:52]
-    reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_671 : @[Reg.scala 28:19]
-      _T_672 <= buf_aligned_in @[Reg.scala 28:23]
+    buf_aligned <= _T_670 @[axi4_to_ahb.scala 412:15]
+    node _T_671 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 416:28]
+    node _T_672 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 416:57]
+    reg _T_673 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_672 : @[Reg.scala 28:19]
+      _T_673 <= _T_671 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    buf_aligned <= _T_672 @[axi4_to_ahb.scala 412:15]
-    node _T_673 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 416:28]
-    node _T_674 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 416:57]
-    reg _T_675 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_674 : @[Reg.scala 28:19]
-      _T_675 <= _T_673 @[Reg.scala 28:23]
-      skip @[Reg.scala 28:19]
-    buf_byteen <= _T_675 @[axi4_to_ahb.scala 415:14]
-    node _T_676 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 419:33]
-    node _T_677 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 419:57]
-    node _T_678 = bits(_T_677, 0, 0) @[axi4_to_ahb.scala 419:80]
+    buf_byteen <= _T_673 @[axi4_to_ahb.scala 415:14]
+    node _T_674 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 419:33]
+    node _T_675 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 419:57]
+    node _T_676 = bits(_T_675, 0, 0) @[axi4_to_ahb.scala 419:80]
     inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23]
     rvclkhdr_5.clock <= clock
     rvclkhdr_5.reset <= reset
     rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18]
-    rvclkhdr_5.io.en <= _T_678 @[el2_lib.scala 511:17]
+    rvclkhdr_5.io.en <= _T_676 @[el2_lib.scala 511:17]
     rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
-    reg _T_679 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
-    _T_679 <= _T_676 @[el2_lib.scala 514:16]
-    buf_data <= _T_679 @[axi4_to_ahb.scala 419:12]
-    node _T_680 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 422:50]
-    reg _T_681 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_680 : @[Reg.scala 28:19]
-      _T_681 <= buf_write @[Reg.scala 28:23]
+    reg _T_677 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
+    _T_677 <= _T_674 @[el2_lib.scala 514:16]
+    buf_data <= _T_677 @[axi4_to_ahb.scala 419:12]
+    node _T_678 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 422:50]
+    reg _T_679 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_678 : @[Reg.scala 28:19]
+      _T_679 <= buf_write @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    slvbuf_write <= _T_681 @[axi4_to_ahb.scala 421:16]
-    node _T_682 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 425:22]
-    node _T_683 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 425:60]
-    reg _T_684 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    slvbuf_write <= _T_679 @[axi4_to_ahb.scala 421:16]
+    node _T_680 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 425:22]
+    node _T_681 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 425:60]
+    reg _T_682 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_681 : @[Reg.scala 28:19]
+      _T_682 <= _T_680 @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    slvbuf_tag <= _T_682 @[axi4_to_ahb.scala 424:14]
+    node _T_683 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 428:59]
+    reg _T_684 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when _T_683 : @[Reg.scala 28:19]
-      _T_684 <= _T_682 @[Reg.scala 28:23]
+      _T_684 <= slvbuf_error_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    slvbuf_tag <= _T_684 @[axi4_to_ahb.scala 424:14]
-    node _T_685 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 428:59]
-    reg _T_686 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_685 : @[Reg.scala 28:19]
-      _T_686 <= slvbuf_error_in @[Reg.scala 28:23]
+    slvbuf_error <= _T_684 @[axi4_to_ahb.scala 427:16]
+    node _T_685 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 432:32]
+    node _T_686 = mux(_T_685, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 432:16]
+    node _T_687 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 432:52]
+    node _T_688 = and(_T_686, _T_687) @[axi4_to_ahb.scala 432:50]
+    reg _T_689 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 432:12]
+    _T_689 <= _T_688 @[axi4_to_ahb.scala 432:12]
+    cmd_doneQ <= _T_689 @[axi4_to_ahb.scala 431:13]
+    node _T_690 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 436:31]
+    node _T_691 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 436:70]
+    reg _T_692 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_691 : @[Reg.scala 28:19]
+      _T_692 <= _T_690 @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    slvbuf_error <= _T_686 @[axi4_to_ahb.scala 427:16]
-    node _T_687 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 432:32]
-    node _T_688 = mux(_T_687, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 432:16]
-    node _T_689 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 432:52]
-    node _T_690 = and(_T_688, _T_689) @[axi4_to_ahb.scala 432:50]
-    reg _T_691 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 432:12]
-    _T_691 <= _T_690 @[axi4_to_ahb.scala 432:12]
-    cmd_doneQ <= _T_691 @[axi4_to_ahb.scala 431:13]
-    node _T_692 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 436:31]
-    node _T_693 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 436:70]
-    reg _T_694 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when _T_693 : @[Reg.scala 28:19]
-      _T_694 <= _T_692 @[Reg.scala 28:23]
-      skip @[Reg.scala 28:19]
-    buf_cmd_byte_ptrQ <= _T_694 @[axi4_to_ahb.scala 435:21]
-    reg _T_695 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 441:12]
-    _T_695 <= io.ahb_hready @[axi4_to_ahb.scala 441:12]
-    ahb_hready_q <= _T_695 @[axi4_to_ahb.scala 440:16]
-    node _T_696 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 444:26]
-    reg _T_697 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 444:12]
-    _T_697 <= _T_696 @[axi4_to_ahb.scala 444:12]
-    ahb_htrans_q <= _T_697 @[axi4_to_ahb.scala 443:16]
-    reg _T_698 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 447:12]
-    _T_698 <= io.ahb_hwrite @[axi4_to_ahb.scala 447:12]
-    ahb_hwrite_q <= _T_698 @[axi4_to_ahb.scala 446:16]
-    reg _T_699 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 450:12]
-    _T_699 <= io.ahb_hresp @[axi4_to_ahb.scala 450:12]
-    ahb_hresp_q <= _T_699 @[axi4_to_ahb.scala 449:15]
-    node _T_700 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 453:26]
-    reg _T_701 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 453:12]
-    _T_701 <= _T_700 @[axi4_to_ahb.scala 453:12]
-    ahb_hrdata_q <= _T_701 @[axi4_to_ahb.scala 452:16]
-    node _T_702 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 456:43]
-    node _T_703 = or(_T_702, io.clk_override) @[axi4_to_ahb.scala 456:58]
-    node _T_704 = and(io.bus_clk_en, _T_703) @[axi4_to_ahb.scala 456:30]
-    buf_clken <= _T_704 @[axi4_to_ahb.scala 456:13]
-    node _T_705 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 457:69]
-    node _T_706 = and(io.ahb_hready, _T_705) @[axi4_to_ahb.scala 457:54]
-    node _T_707 = or(_T_706, io.clk_override) @[axi4_to_ahb.scala 457:74]
-    node _T_708 = and(io.bus_clk_en, _T_707) @[axi4_to_ahb.scala 457:36]
-    ahbm_addr_clken <= _T_708 @[axi4_to_ahb.scala 457:19]
-    node _T_709 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 458:50]
-    node _T_710 = or(_T_709, io.clk_override) @[axi4_to_ahb.scala 458:60]
-    node _T_711 = and(io.bus_clk_en, _T_710) @[axi4_to_ahb.scala 458:36]
-    ahbm_data_clken <= _T_711 @[axi4_to_ahb.scala 458:19]
+    buf_cmd_byte_ptrQ <= _T_692 @[axi4_to_ahb.scala 435:21]
+    reg _T_693 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 441:12]
+    _T_693 <= io.ahb_hready @[axi4_to_ahb.scala 441:12]
+    ahb_hready_q <= _T_693 @[axi4_to_ahb.scala 440:16]
+    node _T_694 = bits(io.ahb_htrans, 1, 0) @[axi4_to_ahb.scala 444:26]
+    reg _T_695 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 444:12]
+    _T_695 <= _T_694 @[axi4_to_ahb.scala 444:12]
+    ahb_htrans_q <= _T_695 @[axi4_to_ahb.scala 443:16]
+    reg _T_696 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 447:12]
+    _T_696 <= io.ahb_hwrite @[axi4_to_ahb.scala 447:12]
+    ahb_hwrite_q <= _T_696 @[axi4_to_ahb.scala 446:16]
+    reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 450:12]
+    _T_697 <= io.ahb_hresp @[axi4_to_ahb.scala 450:12]
+    ahb_hresp_q <= _T_697 @[axi4_to_ahb.scala 449:15]
+    node _T_698 = bits(io.ahb_hrdata, 63, 0) @[axi4_to_ahb.scala 453:26]
+    reg _T_699 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 453:12]
+    _T_699 <= _T_698 @[axi4_to_ahb.scala 453:12]
+    ahb_hrdata_q <= _T_699 @[axi4_to_ahb.scala 452:16]
+    node _T_700 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 456:43]
+    node _T_701 = or(_T_700, io.clk_override) @[axi4_to_ahb.scala 456:58]
+    node _T_702 = and(io.bus_clk_en, _T_701) @[axi4_to_ahb.scala 456:30]
+    buf_clken <= _T_702 @[axi4_to_ahb.scala 456:13]
+    node _T_703 = bits(io.ahb_htrans, 1, 1) @[axi4_to_ahb.scala 457:69]
+    node _T_704 = and(io.ahb_hready, _T_703) @[axi4_to_ahb.scala 457:54]
+    node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 457:74]
+    node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 457:36]
+    ahbm_addr_clken <= _T_706 @[axi4_to_ahb.scala 457:19]
+    node _T_707 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 458:50]
+    node _T_708 = or(_T_707, io.clk_override) @[axi4_to_ahb.scala 458:60]
+    node _T_709 = and(io.bus_clk_en, _T_708) @[axi4_to_ahb.scala 458:36]
+    ahbm_data_clken <= _T_709 @[axi4_to_ahb.scala 458:19]
     inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 483:22]
     rvclkhdr_6.clock <= clock
     rvclkhdr_6.reset <= reset

axi4_to_ahb.v

@@ -245,21 +245,21 @@ module axi4_to_ahb(
   wire  _T_23 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 206:32]
   wire  buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 156:21 axi4_to_ahb.scala 461:12]
   reg  slvbuf_write; // @[Reg.scala 27:20]
-  wire [1:0] _T_594 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 363:23]
+  wire [1:0] _T_592 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 363:23]
   reg  slvbuf_error; // @[Reg.scala 27:20]
-  wire [1:0] _T_596 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
-  wire [1:0] _T_597 = _T_596 & 2'h2; // @[axi4_to_ahb.scala 363:88]
-  wire [3:0] slave_opc = {_T_594,_T_597}; // @[Cat.scala 29:58]
+  wire [1:0] _T_594 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_595 = _T_594 & 2'h2; // @[axi4_to_ahb.scala 363:88]
+  wire [3:0] slave_opc = {_T_592,_T_595}; // @[Cat.scala 29:58]
   wire [1:0] _T_28 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 207:49]
   reg  slvbuf_tag; // @[Reg.scala 27:20]
   wire  _T_33 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 210:65]
   reg [31:0] last_bus_addr; // @[Reg.scala 27:20]
-  wire [63:0] _T_601 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58]
-  wire  _T_602 = buf_state == 3'h5; // @[axi4_to_ahb.scala 364:91]
+  wire [63:0] _T_599 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58]
+  wire  _T_600 = buf_state == 3'h5; // @[axi4_to_ahb.scala 364:91]
   reg [63:0] buf_data; // @[el2_lib.scala 514:16]
   wire  ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 64:27 axi4_to_ahb.scala 464:17]
   reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 453:12]
-  wire [63:0] _T_605 = _T_602 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 364:79]
+  wire [63:0] _T_603 = _T_600 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 364:79]
   wire  _T_42 = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 217:56]
   wire  _T_43 = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 217:91]
   wire  _T_44 = _T_42 | _T_43; // @[axi4_to_ahb.scala 217:74]
@@ -407,72 +407,92 @@ module axi4_to_ahb(
   wire [2:0] buf_cmd_byte_ptr = _T_47 ? _T_93 : _GEN_89; // @[Conditional.scala 40:58]
   wire  slvbuf_wr_en = _T_47 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58]
   wire  slvbuf_error_en = _T_47 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58]
-  wire  _T_533 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 349:24]
-  wire  _T_534 = _T_101 | _T_533; // @[axi4_to_ahb.scala 348:48]
-  wire  _T_536 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 349:54]
-  wire  _T_537 = _T_534 | _T_536; // @[axi4_to_ahb.scala 349:33]
-  wire  _T_539 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 349:93]
-  wire  _T_540 = _T_537 | _T_539; // @[axi4_to_ahb.scala 349:72]
-  wire  _T_542 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 350:25]
-  wire  _T_544 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 350:62]
-  wire  _T_546 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 350:97]
-  wire  _T_547 = _T_544 | _T_546; // @[axi4_to_ahb.scala 350:74]
-  wire  _T_549 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 350:132]
-  wire  _T_550 = _T_547 | _T_549; // @[axi4_to_ahb.scala 350:109]
-  wire  _T_552 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 350:168]
-  wire  _T_553 = _T_550 | _T_552; // @[axi4_to_ahb.scala 350:145]
-  wire  _T_555 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 351:28]
-  wire  _T_556 = _T_553 | _T_555; // @[axi4_to_ahb.scala 350:181]
-  wire  _T_558 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 351:63]
-  wire  _T_559 = _T_556 | _T_558; // @[axi4_to_ahb.scala 351:40]
-  wire  _T_561 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 351:99]
-  wire  _T_562 = _T_559 | _T_561; // @[axi4_to_ahb.scala 351:76]
-  wire  _T_563 = _T_542 & _T_562; // @[axi4_to_ahb.scala 350:38]
-  wire  buf_aligned_in = _T_540 | _T_563; // @[axi4_to_ahb.scala 349:106]
+  wire  _T_531 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 349:24]
+  wire  _T_532 = _T_101 | _T_531; // @[axi4_to_ahb.scala 348:48]
+  wire  _T_534 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 349:54]
+  wire  _T_535 = _T_532 | _T_534; // @[axi4_to_ahb.scala 349:33]
+  wire  _T_537 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 349:93]
+  wire  _T_538 = _T_535 | _T_537; // @[axi4_to_ahb.scala 349:72]
+  wire  _T_540 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 350:25]
+  wire  _T_542 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 350:62]
+  wire  _T_544 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 350:97]
+  wire  _T_545 = _T_542 | _T_544; // @[axi4_to_ahb.scala 350:74]
+  wire  _T_547 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 350:132]
+  wire  _T_548 = _T_545 | _T_547; // @[axi4_to_ahb.scala 350:109]
+  wire  _T_550 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 350:168]
+  wire  _T_551 = _T_548 | _T_550; // @[axi4_to_ahb.scala 350:145]
+  wire  _T_553 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 351:28]
+  wire  _T_554 = _T_551 | _T_553; // @[axi4_to_ahb.scala 350:181]
+  wire  _T_556 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 351:63]
+  wire  _T_557 = _T_554 | _T_556; // @[axi4_to_ahb.scala 351:40]
+  wire  _T_559 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 351:99]
+  wire  _T_560 = _T_557 | _T_559; // @[axi4_to_ahb.scala 351:76]
+  wire  _T_561 = _T_540 & _T_560; // @[axi4_to_ahb.scala 350:38]
+  wire  buf_aligned_in = _T_538 | _T_561; // @[axi4_to_ahb.scala 349:106]
   wire  _T_445 = buf_aligned_in & _T_49; // @[axi4_to_ahb.scala 343:60]
-  wire [2:0] _T_482 = _T_445 ? 3'h0 : master_addr[2:0]; // @[axi4_to_ahb.scala 343:43]
-  wire  _T_486 = buf_state == 3'h3; // @[axi4_to_ahb.scala 346:33]
-  wire  _T_492 = buf_aligned_in & _T_542; // @[axi4_to_ahb.scala 347:38]
-  wire  _T_495 = _T_492 & _T_49; // @[axi4_to_ahb.scala 347:71]
-  wire [1:0] _T_529 = _T_495 ? 2'h0 : master_size[1:0]; // @[axi4_to_ahb.scala 347:21]
-  wire [31:0] _T_568 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
-  wire [31:0] _T_571 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
-  wire [1:0] _T_575 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
-  wire [2:0] buf_size_in = {{1'd0}, _T_529}; // @[axi4_to_ahb.scala 347:15]
-  wire [1:0] _T_577 = _T_575 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 354:77]
-  wire [2:0] _T_578 = {1'h0,_T_577}; // @[Cat.scala 29:58]
-  wire [1:0] _T_580 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_462 = _T_544 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_463 = 3'h2 & _T_462; // @[axi4_to_ahb.scala 174:15]
+  wire  _T_469 = _T_556 | _T_542; // @[axi4_to_ahb.scala 175:56]
+  wire [2:0] _T_471 = _T_469 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_472 = 3'h4 & _T_471; // @[axi4_to_ahb.scala 175:15]
+  wire [2:0] _T_473 = _T_463 | _T_472; // @[axi4_to_ahb.scala 174:63]
+  wire [2:0] _T_477 = _T_550 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] _T_478 = 3'h6 & _T_477; // @[axi4_to_ahb.scala 176:17]
+  wire [2:0] _T_479 = _T_473 | _T_478; // @[axi4_to_ahb.scala 175:96]
+  wire [2:0] _T_481 = _T_445 ? _T_479 : master_addr[2:0]; // @[axi4_to_ahb.scala 343:43]
+  wire  _T_485 = buf_state == 3'h3; // @[axi4_to_ahb.scala 346:33]
+  wire  _T_491 = buf_aligned_in & _T_540; // @[axi4_to_ahb.scala 347:38]
+  wire  _T_494 = _T_491 & _T_49; // @[axi4_to_ahb.scala 347:71]
+  wire [1:0] _T_500 = _T_559 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire  _T_506 = _T_556 | _T_553; // @[axi4_to_ahb.scala 167:55]
+  wire [1:0] _T_508 = _T_506 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_509 = 2'h2 & _T_508; // @[axi4_to_ahb.scala 167:16]
+  wire [1:0] _T_510 = _T_500 | _T_509; // @[axi4_to_ahb.scala 166:64]
+  wire  _T_515 = _T_550 | _T_547; // @[axi4_to_ahb.scala 168:60]
+  wire  _T_518 = _T_515 | _T_544; // @[axi4_to_ahb.scala 168:89]
+  wire  _T_521 = _T_518 | _T_542; // @[axi4_to_ahb.scala 168:123]
+  wire [1:0] _T_523 = _T_521 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_524 = 2'h1 & _T_523; // @[axi4_to_ahb.scala 168:21]
+  wire [1:0] _T_525 = _T_510 | _T_524; // @[axi4_to_ahb.scala 167:93]
+  wire [1:0] _T_527 = _T_494 ? _T_525 : master_size[1:0]; // @[axi4_to_ahb.scala 347:21]
+  wire [31:0] _T_566 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
+  wire [31:0] _T_569 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
+  wire [1:0] _T_573 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [2:0] buf_size_in = {{1'd0}, _T_527}; // @[axi4_to_ahb.scala 347:15]
+  wire [1:0] _T_575 = _T_573 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 354:77]
+  wire [2:0] _T_576 = {1'h0,_T_575}; // @[Cat.scala 29:58]
+  wire [1:0] _T_578 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
   reg [1:0] buf_size; // @[Reg.scala 27:20]
-  wire [1:0] _T_582 = _T_580 & buf_size; // @[axi4_to_ahb.scala 354:134]
-  wire [2:0] _T_583 = {1'h0,_T_582}; // @[Cat.scala 29:58]
-  wire  _T_586 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 358:33]
-  wire [1:0] _T_587 = {1'h1,_T_586}; // @[Cat.scala 29:58]
+  wire [1:0] _T_580 = _T_578 & buf_size; // @[axi4_to_ahb.scala 354:134]
+  wire [2:0] _T_581 = {1'h0,_T_580}; // @[Cat.scala 29:58]
+  wire  _T_584 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 358:33]
+  wire [1:0] _T_585 = {1'h1,_T_584}; // @[Cat.scala 29:58]
   reg  buf_write; // @[Reg.scala 27:20]
-  wire  _T_609 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 367:40]
-  wire  _T_610 = _T_609 & io_ahb_hready; // @[axi4_to_ahb.scala 367:52]
-  wire  last_addr_en = _T_610 & io_ahb_hwrite; // @[axi4_to_ahb.scala 367:68]
+  wire  _T_607 = io_ahb_htrans != 2'h0; // @[axi4_to_ahb.scala 367:40]
+  wire  _T_608 = _T_607 & io_ahb_hready; // @[axi4_to_ahb.scala 367:52]
+  wire  last_addr_en = _T_608 & io_ahb_hwrite; // @[axi4_to_ahb.scala 367:68]
   wire  wrbuf_en = _T_42 & master_ready; // @[axi4_to_ahb.scala 369:47]
   wire  wrbuf_data_en = _T_43 & master_ready; // @[axi4_to_ahb.scala 370:50]
   wire  wrbuf_cmd_sent = _T_147 & _T_49; // @[axi4_to_ahb.scala 371:49]
-  wire  _T_620 = ~wrbuf_en; // @[axi4_to_ahb.scala 372:33]
-  wire  wrbuf_rst = wrbuf_cmd_sent & _T_620; // @[axi4_to_ahb.scala 372:31]
-  wire  _T_622 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 374:35]
-  wire  _T_623 = wrbuf_vld & _T_622; // @[axi4_to_ahb.scala 374:33]
-  wire  _T_624 = ~_T_623; // @[axi4_to_ahb.scala 374:21]
-  wire  _T_627 = wrbuf_data_vld & _T_622; // @[axi4_to_ahb.scala 375:37]
-  wire  _T_628 = ~_T_627; // @[axi4_to_ahb.scala 375:20]
-  wire  _T_631 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 376:21]
-  wire  _T_634 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 380:52]
-  wire  _T_635 = ~wrbuf_rst; // @[axi4_to_ahb.scala 380:88]
-  wire  _T_639 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 381:52]
+  wire  _T_618 = ~wrbuf_en; // @[axi4_to_ahb.scala 372:33]
+  wire  wrbuf_rst = wrbuf_cmd_sent & _T_618; // @[axi4_to_ahb.scala 372:31]
+  wire  _T_620 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 374:35]
+  wire  _T_621 = wrbuf_vld & _T_620; // @[axi4_to_ahb.scala 374:33]
+  wire  _T_622 = ~_T_621; // @[axi4_to_ahb.scala 374:21]
+  wire  _T_625 = wrbuf_data_vld & _T_620; // @[axi4_to_ahb.scala 375:37]
+  wire  _T_626 = ~_T_625; // @[axi4_to_ahb.scala 375:20]
+  wire  _T_629 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 376:21]
+  wire  _T_632 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 380:52]
+  wire  _T_633 = ~wrbuf_rst; // @[axi4_to_ahb.scala 380:88]
+  wire  _T_637 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 381:52]
   reg  buf_tag; // @[Reg.scala 27:20]
-  wire  _T_689 = ~slave_valid_pre; // @[axi4_to_ahb.scala 432:52]
-  wire  _T_702 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 456:43]
-  wire  _T_703 = _T_702 | io_clk_override; // @[axi4_to_ahb.scala 456:58]
-  wire  _T_706 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 457:54]
-  wire  _T_707 = _T_706 | io_clk_override; // @[axi4_to_ahb.scala 457:74]
-  wire  _T_709 = buf_state != 3'h0; // @[axi4_to_ahb.scala 458:50]
-  wire  _T_710 = _T_709 | io_clk_override; // @[axi4_to_ahb.scala 458:60]
+  wire  _T_687 = ~slave_valid_pre; // @[axi4_to_ahb.scala 432:52]
+  wire  _T_700 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 456:43]
+  wire  _T_701 = _T_700 | io_clk_override; // @[axi4_to_ahb.scala 456:58]
+  wire  _T_704 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 457:54]
+  wire  _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 457:74]
+  wire  _T_707 = buf_state != 3'h0; // @[axi4_to_ahb.scala 458:50]
+  wire  _T_708 = _T_707 | io_clk_override; // @[axi4_to_ahb.scala 458:60]
   rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
     .io_l1clk(rvclkhdr_io_l1clk),
     .io_clk(rvclkhdr_io_clk),
@@ -533,22 +553,22 @@ module axi4_to_ahb(
     .io_en(rvclkhdr_9_io_en),
     .io_scan_mode(rvclkhdr_9_io_scan_mode)
   );
-  assign io_axi_awready = _T_624 & master_ready; // @[axi4_to_ahb.scala 374:18]
-  assign io_axi_wready = _T_628 & master_ready; // @[axi4_to_ahb.scala 375:17]
+  assign io_axi_awready = _T_622 & master_ready; // @[axi4_to_ahb.scala 374:18]
+  assign io_axi_wready = _T_626 & master_ready; // @[axi4_to_ahb.scala 375:17]
   assign io_axi_bvalid = _T_23 & slave_opc[3]; // @[axi4_to_ahb.scala 206:17]
   assign io_axi_bresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 207:16]
   assign io_axi_bid = slvbuf_tag; // @[axi4_to_ahb.scala 208:14]
-  assign io_axi_arready = _T_631 & master_ready; // @[axi4_to_ahb.scala 376:18]
+  assign io_axi_arready = _T_629 & master_ready; // @[axi4_to_ahb.scala 376:18]
   assign io_axi_rvalid = _T_23 & _T_33; // @[axi4_to_ahb.scala 210:17]
   assign io_axi_rid = slvbuf_tag; // @[axi4_to_ahb.scala 212:14]
-  assign io_axi_rdata = slvbuf_error ? _T_601 : _T_605; // @[axi4_to_ahb.scala 213:16]
+  assign io_axi_rdata = slvbuf_error ? _T_599 : _T_603; // @[axi4_to_ahb.scala 213:16]
   assign io_axi_rresp = slave_opc[0] ? 2'h2 : _T_28; // @[axi4_to_ahb.scala 211:16]
   assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 377:16]
-  assign io_ahb_haddr = bypass_en ? _T_568 : _T_571; // @[axi4_to_ahb.scala 353:16]
+  assign io_ahb_haddr = bypass_en ? _T_566 : _T_569; // @[axi4_to_ahb.scala 353:16]
   assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 356:17]
   assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 357:20]
-  assign io_ahb_hprot = {{2'd0}, _T_587}; // @[axi4_to_ahb.scala 358:16]
-  assign io_ahb_hsize = bypass_en ? _T_578 : _T_583; // @[axi4_to_ahb.scala 354:16]
+  assign io_ahb_hprot = {{2'd0}, _T_585}; // @[axi4_to_ahb.scala 358:16]
+  assign io_ahb_hsize = bypass_en ? _T_576 : _T_581; // @[axi4_to_ahb.scala 354:16]
   assign io_ahb_htrans = _T_47 ? _T_98 : _GEN_90; // @[axi4_to_ahb.scala 223:17 axi4_to_ahb.scala 254:21 axi4_to_ahb.scala 266:21 axi4_to_ahb.scala 281:21 axi4_to_ahb.scala 291:21 axi4_to_ahb.scala 311:21 axi4_to_ahb.scala 325:21]
   assign io_ahb_hwrite = bypass_en ? _T_49 : buf_write; // @[axi4_to_ahb.scala 359:17]
   assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 360:17]
@@ -571,16 +591,16 @@ module axi4_to_ahb(
   assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[el2_lib.scala 511:17]
   assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
   assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 484:17]
-  assign rvclkhdr_6_io_en = io_bus_clk_en & _T_703; // @[el2_lib.scala 485:16]
+  assign rvclkhdr_6_io_en = io_bus_clk_en & _T_701; // @[el2_lib.scala 485:16]
   assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
   assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 484:17]
   assign rvclkhdr_7_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
   assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
   assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 484:17]
-  assign rvclkhdr_8_io_en = io_bus_clk_en & _T_707; // @[el2_lib.scala 485:16]
+  assign rvclkhdr_8_io_en = io_bus_clk_en & _T_705; // @[el2_lib.scala 485:16]
   assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
   assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 484:17]
-  assign rvclkhdr_9_io_en = io_bus_clk_en & _T_710; // @[el2_lib.scala 485:16]
+  assign rvclkhdr_9_io_en = io_bus_clk_en & _T_708; // @[el2_lib.scala 485:16]
   assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
 `ifdef RANDOMIZE_GARBAGE_ASSIGN
 `define RANDOMIZE
@@ -765,14 +785,14 @@ end // initial
     if (reset) begin
       wrbuf_vld <= 1'h0;
     end else begin
-      wrbuf_vld <= _T_634 & _T_635;
+      wrbuf_vld <= _T_632 & _T_633;
     end
   end
   always @(posedge bus_clk or posedge reset) begin
     if (reset) begin
       wrbuf_data_vld <= 1'h0;
     end else begin
-      wrbuf_data_vld <= _T_639 & _T_635;
+      wrbuf_data_vld <= _T_637 & _T_633;
     end
   end
   always @(posedge ahbm_clk or posedge reset) begin
@@ -807,7 +827,7 @@ end // initial
     if (reset) begin
       cmd_doneQ <= 1'h0;
     end else begin
-      cmd_doneQ <= _T_274 & _T_689;
+      cmd_doneQ <= _T_274 & _T_687;
     end
   end
   always @(posedge bus_clk or posedge reset) begin
@@ -890,7 +910,7 @@ end // initial
   always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin
     if (reset) begin
       buf_data <= 64'h0;
-    end else if (_T_486) begin
+    end else if (_T_485) begin
       buf_data <= ahb_hrdata_q;
     end else begin
       buf_data <= wrbuf_data;
@@ -907,7 +927,7 @@ end // initial
     if (reset) begin
       buf_addr <= 32'h0;
     end else begin
-      buf_addr <= {master_addr[31:3],_T_482};
+      buf_addr <= {master_addr[31:3],_T_481};
     end
   end
   always @(posedge ahbm_clk or posedge reset) begin

project/target/config-classes/$e55d6b0d03c5f442179e.cache

@@ -1 +0,0 @@
-sbt.internal.DslEntry

project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs

@@ -1 +1 @@
--2044733690
+433638439

project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp

@@ -1 +1 @@
-23355001
+-1413115869

project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp

@@ -1 +1 @@
-{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.10\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":2531},"type":"LinePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-structure-extractor\",\"revision\":\"2018.2.1+4-88400d3f\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-idea-shell\",\"revision\":\"2018.3\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-idea-compiler-indices\",\"revision\":\"0.1.3\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"}}
+{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.10\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":2531},"type":"LinePosition"}}

project/target/streams/_global/update/_global/streams/out

@@ -1,3 +1,3 @@
-[debug] "not up to date. inChanged = true, force = false
-[debug] Updating ProjectRef(uri("file:/home/laraibkhan/Desktop/SweRV-Chislified/project/"), "swerv-chislified-build")...
-[debug] Done updating ProjectRef(uri("file:/home/laraibkhan/Desktop/SweRV-Chislified/project/"), "swerv-chislified-build")
+[debug] "not up to date. inChanged = true, force = false
+[debug] Updating ProjectRef(uri("file:/home/laraibkhan/Desktop/SweRV-Chislified/project/"), "swerv-chislified-build")...
+[debug] Done updating ProjectRef(uri("file:/home/laraibkhan/Desktop/SweRV-Chislified/project/"), "swerv-chislified-build")

project/target/streams/compile/compileIncremental/_global/streams/out

@@ -1 +1 @@
-[debug] Full compilation, no sources in previous analysis.
+[debug] Full compilation, no sources in previous analysis.

project/target/streams/compile/copyResources/_global/streams/out

@@ -1,2 +1,2 @@
-[debug] Copy resource mappings: 
-[debug] 	
+[debug] Copy resource mappings: 
+[debug] 	

project/target/streams/runtime/dependencyClasspath/_global/streams/export

@@ -1 +1 @@
-/home/laraibkhan/Desktop/SweRV-Chislified/project/target/scala-2.12/sbt-1.0/classes:/home/laraibkhan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes:/home/laraibkhan/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/laraibkhan/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/laraibkhan/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/laraibkhan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar
+/home/laraibkhan/Desktop/SweRV-Chislified/project/target/scala-2.12/sbt-1.0/classes:/home/laraibkhan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes

project/target/streams/runtime/externalDependencyClasspath/_global/streams/export

@@ -1 +1 @@
-/home/laraibkhan/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/laraibkhan/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/laraibkhan/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/laraibkhan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar
+

project/target/streams/runtime/fullClasspath/_global/streams/export

@@ -1 +1 @@
-/home/laraibkhan/Desktop/SweRV-Chislified/project/target/scala-2.12/sbt-1.0/classes:/home/laraibkhan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes:/home/laraibkhan/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/laraibkhan/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/laraibkhan/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/laraibkhan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar
+/home/laraibkhan/Desktop/SweRV-Chislified/project/target/scala-2.12/sbt-1.0/classes:/home/laraibkhan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes

project/target/streams/runtime/managedClasspath/_global/streams/export

@@ -1 +1 @@
-/home/laraibkhan/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/laraibkhan/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/laraibkhan/.local/share/JetBrains/IdeaIC2020.2/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/laraibkhan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar
+

src/main/scala/lib/axi4_to_ahb.scala

@@ -161,7 +161,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
 
   def get_write_size(byteen: UInt) = {
 
-    val byteen = WireInit(0.U(8.W))
+   // val byteen = WireInit(0.U(8.W))
 
     val size = ("b11".U & Fill(2, (byteen(7, 0) === "hff".U))) |
       ("b10".U & (Fill(2, ((byteen(7, 0) === "hf0".U) | (byteen(7, 0) === "h0f".U(8.W)))))) |
@@ -169,7 +169,7 @@ class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config
     size
   }
   def get_write_addr(byteen_e: UInt) = {
-    val byteen_e = WireInit(0.U(8.W))
+  //  val byteen_e = WireInit(0.U(8.W))
     val addr = ("h0".U(3.W) & (Fill(3, ((byteen_e(7, 0) === "hff".U) | (byteen_e(7, 0) === "h0f".U(8.W)) | (byteen_e(7, 0) === "h03".U(8.W)))))) |
       ("h2".U & (Fill(3, (byteen_e(7, 0) === "h0c".U(8.W))))) |
       ("h4".U & (Fill(3, ((byteen_e(7, 0) === "hf0".U) | (byteen_e(7, 0) === "h03".U(8.W)))))) |

target/.history

@@ -1 +1,2 @@
 ;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure
+;set _root_.scala.collection.Seq(historyPath := None,shellPrompt := { _ => "" },SettingKey[_root_.scala.Option[_root_.sbt.File]]("sbtStructureOutputFile") in _root_.sbt.Global := _root_.scala.Some(_root_.sbt.file("/tmp/sbt-structure.xml")),SettingKey[_root_.java.lang.String]("sbtStructureOptions") in _root_.sbt.Global := "download, resolveClassifiers");apply -cp "/home/laraibkhan/.local/share/JetBrains/IdeaIC2020.3/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2020.3/jars/sbt-structure-extractor.jar" org.jetbrains.sbt.CreateTasks;*/*:dumpStructure

target/streams/_global/_global/checkBuildSources/_global/streams/out

@@ -1 +1 @@
-[debug] Checking for meta build source updates
+[debug] Checking for meta build source updates

target/streams/_global/updateClassifiers/_global/streams/out

@@ -1,3 +1,4 @@
-[debug] "not up to date. inChanged = true, force = false
-[debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/SweRV-Chisel/"), "swerv-chisel")...
-[debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/SweRV-Chisel/"), "swerv-chisel")
+[warn] paradise_2.12.10-2.1.0-sources.jar no longer exists at /home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0-sources.jar
+[debug] "not up to date. inChanged = false, force = false
+[debug] Updating ProjectRef(uri("file:/home/laraibkhan/Desktop/SweRV-Chislified/"), "swerv-chislified")...
+[debug] Done updating ProjectRef(uri("file:/home/laraibkhan/Desktop/SweRV-Chislified/"), "swerv-chislified")

target/streams/test/externalDependencyClasspath/_global/streams/export

@@ -1 +1 @@
-/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar
+/home/laraibkhan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/laraibkhan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar

target/streams/test/managedClasspath/_global/streams/export

@@ -1 +1 @@
-/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar
+/home/laraibkhan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/laraibkhan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/laraibkhan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar