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mimpid=1

This commit is contained in:
​Laraib Khan 2020-12-17 15:03:40 +05:00
parent 6b768acbc7
commit d2c1fc52db
4 changed files with 3 additions and 3 deletions
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2
quasar_wrapper.fir
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@ -76062,7 +76062,7 @@ circuit quasar_wrapper :
node _T_2504 = mux(_T_2338, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_2504 = mux(_T_2338, UInt<32>("h040001104"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2505 = mux(_T_2339, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_2505 = mux(_T_2339, UInt<32>("h045"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2506 = mux(_T_2340, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_2506 = mux(_T_2340, UInt<32>("h010"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2507 = mux(_T_2341, UInt<32>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_2507 = mux(_T_2341, UInt<32>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2508 = mux(_T_2342, _T_2343, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2508 = mux(_T_2342, _T_2343, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2509 = mux(_T_2344, _T_2352, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2509 = mux(_T_2344, _T_2352, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_2510 = mux(_T_2353, _T_2357, UInt<1>("h00")) @[Mux.scala 27:72] node _T_2510 = mux(_T_2353, _T_2357, UInt<1>("h00")) @[Mux.scala 27:72]

2
quasar_wrapper.v
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@ -52249,7 +52249,7 @@ module csr_tlu(
wire [31:0] _T_2504 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2504 = io_csr_pkt_csr_misa ? 32'h40001104 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_2505 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2505 = io_csr_pkt_csr_mvendorid ? 32'h45 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_2506 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2506 = io_csr_pkt_csr_marchid ? 32'h10 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_2507 = io_csr_pkt_csr_mimpid ? 32'h2 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2507 = io_csr_pkt_csr_mimpid ? 32'h1 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_2508 = io_csr_pkt_csr_mhartid ? _T_2343 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2508 = io_csr_pkt_csr_mhartid ? _T_2343 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_2509 = io_csr_pkt_csr_mstatus ? _T_2352 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2509 = io_csr_pkt_csr_mstatus ? _T_2352 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_2510 = io_csr_pkt_csr_mtvec ? _T_2357 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_2510 = io_csr_pkt_csr_mtvec ? _T_2357 : 32'h0; // @[Mux.scala 27:72]

2
src/main/scala/dec/dec_tlu_ctl.scala
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@ -2498,7 +2498,7 @@ for(i <- 0 until 4) {io.trigger_pkt_any(i).tdata2 := mtdata2_t(i)}
io.csr_pkt.csr_misa.asBool -> 0x40001104.U(32.W), io.csr_pkt.csr_misa.asBool -> 0x40001104.U(32.W),
io.csr_pkt.csr_mvendorid.asBool -> 0x00000045.U(32.W), io.csr_pkt.csr_mvendorid.asBool -> 0x00000045.U(32.W),
io.csr_pkt.csr_marchid.asBool -> 0x00000010.U(32.W), io.csr_pkt.csr_marchid.asBool -> 0x00000010.U(32.W),
io.csr_pkt.csr_mimpid.asBool -> 0x2.U(32.W), io.csr_pkt.csr_mimpid.asBool -> 0x1.U(32.W),
io.csr_pkt.csr_mhartid.asBool -> Cat(io.core_id,0.U(4.W)), io.csr_pkt.csr_mhartid.asBool -> Cat(io.core_id,0.U(4.W)),
io.csr_pkt.csr_mstatus.asBool -> Cat(0.U(19.W), 3.U(2.W), 0.U(3.W), io.mstatus(1), 0.U(3.W), io.mstatus(0), 0.U(3.W)), io.csr_pkt.csr_mstatus.asBool -> Cat(0.U(19.W), 3.U(2.W), 0.U(3.W), io.mstatus(1), 0.U(3.W), io.mstatus(0), 0.U(3.W)),
io.csr_pkt.csr_mtvec.asBool -> Cat(io.mtvec(30,1), 0.U(1.W), io.mtvec(0)), io.csr_pkt.csr_mtvec.asBool -> Cat(io.mtvec(30,1), 0.U(1.W), io.mtvec(0)),

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target/scala-2.12/classes/dec/csr_tlu.class
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