IFC bits rectified
This commit is contained in:
waleed-lm
parent
e7810dad72
commit
d39488baa3
528
EL2_IC_DATA.fir
528
EL2_IC_DATA.fir
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@ -22,8 +22,7 @@ circuit EL2_IC_DATA :
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_T_6[1] <= _T_5 @[el2_lib.scala 185:48]
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node _T_7 = cat(_T_6[0], _T_6[1]) @[Cat.scala 29:58]
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node ic_debug_wr_way_en = and(_T_7, io.ic_debug_way) @[el2_ifu_ic_mem.scala 201:94]
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wire ic_bank_wr_data : UInt<71>
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ic_bank_wr_data <= UInt<1>("h00")
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wire ic_bank_wr_data : UInt<71>[2] @[el2_ifu_ic_mem.scala 203:29]
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wire ic_rd_en_with_debug : UInt<1>
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ic_rd_en_with_debug <= UInt<1>("h00")
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node _T_8 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 206:45]
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@ -53,222 +52,355 @@ circuit EL2_IC_DATA :
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node _T_27 = bits(ic_debug_sel_sb, 0, 0) @[el2_ifu_ic_mem.scala 212:77]
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node _T_28 = and(_T_27, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 212:80]
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node _T_29 = bits(_T_28, 0, 0) @[el2_ifu_ic_mem.scala 212:100]
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node _T_30 = bits(ic_bank_wr_data, 0, 0) @[el2_ifu_ic_mem.scala 212:144]
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node ic_sb_wr_data_0 = mux(_T_29, io.ic_debug_wr_data, _T_30) @[el2_ifu_ic_mem.scala 212:60]
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node _T_31 = bits(ic_debug_sel_sb, 1, 1) @[el2_ifu_ic_mem.scala 212:77]
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node _T_32 = and(_T_31, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 212:80]
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node _T_33 = bits(_T_32, 0, 0) @[el2_ifu_ic_mem.scala 212:100]
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node _T_34 = bits(ic_bank_wr_data, 1, 1) @[el2_ifu_ic_mem.scala 212:144]
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node ic_sb_wr_data_1 = mux(_T_33, io.ic_debug_wr_data, _T_34) @[el2_ifu_ic_mem.scala 212:60]
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node _T_35 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 214:29]
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node _T_36 = bits(_T_35, 0, 0) @[el2_ifu_ic_mem.scala 214:48]
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node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 214:16]
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node _T_38 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 214:63]
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node _T_39 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 215:42]
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node _T_40 = bits(_T_39, 0, 0) @[el2_ifu_ic_mem.scala 215:62]
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node _T_41 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 215:86]
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node _T_42 = eq(_T_41, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 215:91]
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node _T_43 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 215:103]
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node _T_44 = and(_T_42, _T_43) @[el2_ifu_ic_mem.scala 215:98]
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node _T_45 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 216:42]
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node _T_46 = bits(_T_45, 0, 0) @[el2_ifu_ic_mem.scala 216:61]
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node _T_47 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 216:76]
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node _T_48 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 217:43]
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node _T_49 = eq(_T_48, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 217:30]
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node _T_50 = bits(_T_49, 0, 0) @[el2_ifu_ic_mem.scala 217:63]
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node _T_51 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 217:87]
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node _T_52 = eq(_T_51, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 217:92]
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node _T_53 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 217:105]
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node _T_54 = and(_T_52, _T_53) @[el2_ifu_ic_mem.scala 217:99]
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node _T_55 = mux(_T_37, _T_38, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_56 = mux(_T_40, _T_44, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_57 = mux(_T_46, _T_47, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_58 = mux(_T_50, _T_54, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_59 = or(_T_55, _T_56) @[Mux.scala 27:72]
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node _T_60 = or(_T_59, _T_57) @[Mux.scala 27:72]
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node _T_61 = or(_T_60, _T_58) @[Mux.scala 27:72]
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wire _T_62 : UInt<1> @[Mux.scala 27:72]
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_T_62 <= _T_61 @[Mux.scala 27:72]
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node _T_63 = and(_T_62, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 217:117]
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node _T_64 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 214:29]
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node _T_65 = bits(_T_64, 0, 0) @[el2_ifu_ic_mem.scala 214:48]
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node _T_66 = eq(_T_65, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 214:16]
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node _T_67 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 214:63]
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node _T_68 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 215:42]
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node _T_69 = bits(_T_68, 0, 0) @[el2_ifu_ic_mem.scala 215:62]
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node _T_70 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 215:86]
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node _T_71 = eq(_T_70, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 215:91]
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node _T_72 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 215:103]
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node _T_73 = and(_T_71, _T_72) @[el2_ifu_ic_mem.scala 215:98]
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node _T_74 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 216:42]
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node _T_75 = bits(_T_74, 0, 0) @[el2_ifu_ic_mem.scala 216:61]
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node _T_76 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 216:76]
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node _T_77 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 217:43]
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node _T_78 = eq(_T_77, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 217:30]
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node _T_79 = bits(_T_78, 0, 0) @[el2_ifu_ic_mem.scala 217:63]
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node _T_80 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 217:87]
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node _T_81 = eq(_T_80, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 217:92]
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node _T_82 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 217:105]
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node _T_83 = and(_T_81, _T_82) @[el2_ifu_ic_mem.scala 217:99]
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node _T_84 = mux(_T_66, _T_67, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_85 = mux(_T_69, _T_73, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_86 = mux(_T_75, _T_76, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_87 = mux(_T_79, _T_83, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_88 = or(_T_84, _T_85) @[Mux.scala 27:72]
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node _T_89 = or(_T_88, _T_86) @[Mux.scala 27:72]
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node _T_90 = or(_T_89, _T_87) @[Mux.scala 27:72]
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wire _T_91 : UInt<1> @[Mux.scala 27:72]
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_T_91 <= _T_90 @[Mux.scala 27:72]
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node _T_92 = and(_T_91, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 217:117]
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node ic_b_rden = cat(_T_92, _T_63) @[Cat.scala 29:58]
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node _T_93 = bits(ic_b_rden, 0, 0) @[el2_ifu_ic_mem.scala 218:89]
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node ic_sb_wr_data_0 = mux(_T_29, io.ic_debug_wr_data, ic_bank_wr_data[0]) @[el2_ifu_ic_mem.scala 212:60]
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node _T_30 = bits(ic_debug_sel_sb, 1, 1) @[el2_ifu_ic_mem.scala 212:77]
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node _T_31 = and(_T_30, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 212:80]
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node _T_32 = bits(_T_31, 0, 0) @[el2_ifu_ic_mem.scala 212:100]
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node ic_sb_wr_data_1 = mux(_T_32, io.ic_debug_wr_data, ic_bank_wr_data[1]) @[el2_ifu_ic_mem.scala 212:60]
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node _T_33 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 214:29]
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node _T_34 = bits(_T_33, 0, 0) @[el2_ifu_ic_mem.scala 214:48]
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node _T_35 = eq(_T_34, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 214:16]
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node _T_36 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 214:63]
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node _T_37 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 215:42]
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node _T_38 = bits(_T_37, 0, 0) @[el2_ifu_ic_mem.scala 215:62]
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node _T_39 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 215:86]
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node _T_40 = eq(_T_39, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 215:91]
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node _T_41 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 215:103]
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node _T_42 = and(_T_40, _T_41) @[el2_ifu_ic_mem.scala 215:98]
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node _T_43 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 216:42]
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node _T_44 = bits(_T_43, 0, 0) @[el2_ifu_ic_mem.scala 216:61]
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node _T_45 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 216:76]
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node _T_46 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 217:43]
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node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 217:30]
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node _T_48 = bits(_T_47, 0, 0) @[el2_ifu_ic_mem.scala 217:63]
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node _T_49 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 217:87]
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node _T_50 = eq(_T_49, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 217:92]
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node _T_51 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 217:105]
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node _T_52 = and(_T_50, _T_51) @[el2_ifu_ic_mem.scala 217:99]
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node _T_53 = mux(_T_35, _T_36, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_54 = mux(_T_38, _T_42, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_55 = mux(_T_44, _T_45, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_56 = mux(_T_48, _T_52, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_57 = or(_T_53, _T_54) @[Mux.scala 27:72]
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node _T_58 = or(_T_57, _T_55) @[Mux.scala 27:72]
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node _T_59 = or(_T_58, _T_56) @[Mux.scala 27:72]
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wire _T_60 : UInt<1> @[Mux.scala 27:72]
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_T_60 <= _T_59 @[Mux.scala 27:72]
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node _T_61 = and(_T_60, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 217:117]
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node _T_62 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 214:29]
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node _T_63 = bits(_T_62, 0, 0) @[el2_ifu_ic_mem.scala 214:48]
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node _T_64 = eq(_T_63, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 214:16]
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node _T_65 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 214:63]
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node _T_66 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 215:42]
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node _T_67 = bits(_T_66, 0, 0) @[el2_ifu_ic_mem.scala 215:62]
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node _T_68 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 215:86]
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node _T_69 = eq(_T_68, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 215:91]
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node _T_70 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 215:103]
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node _T_71 = and(_T_69, _T_70) @[el2_ifu_ic_mem.scala 215:98]
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node _T_72 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 216:42]
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node _T_73 = bits(_T_72, 0, 0) @[el2_ifu_ic_mem.scala 216:61]
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node _T_74 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 216:76]
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node _T_75 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 217:43]
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node _T_76 = eq(_T_75, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 217:30]
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node _T_77 = bits(_T_76, 0, 0) @[el2_ifu_ic_mem.scala 217:63]
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node _T_78 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 217:87]
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node _T_79 = eq(_T_78, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 217:92]
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node _T_80 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 217:105]
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node _T_81 = and(_T_79, _T_80) @[el2_ifu_ic_mem.scala 217:99]
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node _T_82 = mux(_T_64, _T_65, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_83 = mux(_T_67, _T_71, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_84 = mux(_T_73, _T_74, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_85 = mux(_T_77, _T_81, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_86 = or(_T_82, _T_83) @[Mux.scala 27:72]
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node _T_87 = or(_T_86, _T_84) @[Mux.scala 27:72]
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node _T_88 = or(_T_87, _T_85) @[Mux.scala 27:72]
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wire _T_89 : UInt<1> @[Mux.scala 27:72]
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_T_89 <= _T_88 @[Mux.scala 27:72]
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node _T_90 = and(_T_89, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 217:117]
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node ic_b_rden = cat(_T_90, _T_61) @[Cat.scala 29:58]
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node _T_91 = bits(ic_b_rden, 0, 0) @[el2_ifu_ic_mem.scala 218:89]
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node _T_92 = bits(_T_91, 0, 0) @[Bitwise.scala 72:15]
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node ic_b_sb_rden_0 = mux(_T_92, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_93 = bits(ic_b_rden, 1, 1) @[el2_ifu_ic_mem.scala 218:89]
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node _T_94 = bits(_T_93, 0, 0) @[Bitwise.scala 72:15]
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node ic_b_sb_rden_0 = mux(_T_94, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_95 = bits(ic_b_rden, 1, 1) @[el2_ifu_ic_mem.scala 218:89]
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node _T_96 = bits(_T_95, 0, 0) @[Bitwise.scala 72:15]
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node ic_b_sb_rden_1 = mux(_T_96, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_97 = bits(ic_b_sb_rden_0, 0, 0) @[el2_ifu_ic_mem.scala 220:21]
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node _T_98 = or(_T_97, io.clk_override) @[el2_ifu_ic_mem.scala 220:25]
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node _T_99 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 220:60]
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node _T_100 = or(_T_98, _T_99) @[el2_ifu_ic_mem.scala 220:43]
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node _T_101 = bits(ic_b_sb_rden_0, 1, 1) @[el2_ifu_ic_mem.scala 220:21]
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node _T_102 = or(_T_101, io.clk_override) @[el2_ifu_ic_mem.scala 220:25]
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node _T_103 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 220:60]
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node _T_104 = or(_T_102, _T_103) @[el2_ifu_ic_mem.scala 220:43]
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node ic_bank_way_clken_0 = cat(_T_100, _T_104) @[Cat.scala 29:58]
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node _T_105 = bits(ic_b_sb_rden_1, 0, 0) @[el2_ifu_ic_mem.scala 220:21]
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node _T_106 = or(_T_105, io.clk_override) @[el2_ifu_ic_mem.scala 220:25]
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node _T_107 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 220:60]
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node _T_108 = or(_T_106, _T_107) @[el2_ifu_ic_mem.scala 220:43]
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node _T_109 = bits(ic_b_sb_rden_1, 1, 1) @[el2_ifu_ic_mem.scala 220:21]
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node _T_110 = or(_T_109, io.clk_override) @[el2_ifu_ic_mem.scala 220:25]
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node _T_111 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 220:60]
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node _T_112 = or(_T_110, _T_111) @[el2_ifu_ic_mem.scala 220:43]
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node ic_bank_way_clken_1 = cat(_T_108, _T_112) @[Cat.scala 29:58]
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node _T_113 = orr(io.ic_wr_en) @[el2_ifu_ic_mem.scala 222:74]
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node _T_114 = eq(_T_113, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 222:61]
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node _T_115 = and(io.ic_debug_rd_en, _T_114) @[el2_ifu_ic_mem.scala 222:58]
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node _T_116 = or(io.ic_rd_en, _T_115) @[el2_ifu_ic_mem.scala 222:38]
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ic_rd_en_with_debug <= _T_116 @[el2_ifu_ic_mem.scala 222:23]
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node _T_117 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 224:37]
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node _T_118 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 224:71]
|
||||
node _T_119 = eq(_T_118, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 224:77]
|
||||
node _T_120 = and(_T_117, _T_119) @[el2_ifu_ic_mem.scala 224:56]
|
||||
node _T_121 = and(_T_120, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 224:86]
|
||||
node _T_122 = orr(io.ic_wr_en) @[el2_ifu_ic_mem.scala 224:124]
|
||||
node _T_123 = eq(_T_122, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 224:110]
|
||||
node ic_rw_addr_wrap = and(_T_121, _T_123) @[el2_ifu_ic_mem.scala 224:108]
|
||||
node _T_124 = eq(ic_rw_addr_wrap, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 226:40]
|
||||
node _T_125 = bits(_T_124, 0, 0) @[el2_ifu_ic_mem.scala 226:58]
|
||||
node _T_126 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 226:77]
|
||||
node _T_127 = bits(ic_rw_addr_q, 11, 5) @[el2_ifu_ic_mem.scala 227:21]
|
||||
node _T_128 = bits(ic_rw_addr_q_inc, 4, 3) @[el2_ifu_ic_mem.scala 227:82]
|
||||
node _T_129 = cat(_T_127, _T_128) @[Cat.scala 29:58]
|
||||
node _T_130 = mux(_T_125, _T_126, _T_129) @[el2_ifu_ic_mem.scala 226:38]
|
||||
node _T_131 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 228:17]
|
||||
node ic_b_sb_rden_1 = mux(_T_94, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_95 = bits(ic_b_sb_rden_0, 0, 0) @[el2_ifu_ic_mem.scala 220:21]
|
||||
node _T_96 = or(_T_95, io.clk_override) @[el2_ifu_ic_mem.scala 220:25]
|
||||
node _T_97 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 220:60]
|
||||
node _T_98 = or(_T_96, _T_97) @[el2_ifu_ic_mem.scala 220:43]
|
||||
node _T_99 = bits(ic_b_sb_rden_0, 1, 1) @[el2_ifu_ic_mem.scala 220:21]
|
||||
node _T_100 = or(_T_99, io.clk_override) @[el2_ifu_ic_mem.scala 220:25]
|
||||
node _T_101 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 220:60]
|
||||
node _T_102 = or(_T_100, _T_101) @[el2_ifu_ic_mem.scala 220:43]
|
||||
node ic_bank_way_clken_0 = cat(_T_98, _T_102) @[Cat.scala 29:58]
|
||||
node _T_103 = bits(ic_b_sb_rden_1, 0, 0) @[el2_ifu_ic_mem.scala 220:21]
|
||||
node _T_104 = or(_T_103, io.clk_override) @[el2_ifu_ic_mem.scala 220:25]
|
||||
node _T_105 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 220:60]
|
||||
node _T_106 = or(_T_104, _T_105) @[el2_ifu_ic_mem.scala 220:43]
|
||||
node _T_107 = bits(ic_b_sb_rden_1, 1, 1) @[el2_ifu_ic_mem.scala 220:21]
|
||||
node _T_108 = or(_T_107, io.clk_override) @[el2_ifu_ic_mem.scala 220:25]
|
||||
node _T_109 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 220:60]
|
||||
node _T_110 = or(_T_108, _T_109) @[el2_ifu_ic_mem.scala 220:43]
|
||||
node ic_bank_way_clken_1 = cat(_T_106, _T_110) @[Cat.scala 29:58]
|
||||
node _T_111 = orr(io.ic_wr_en) @[el2_ifu_ic_mem.scala 222:74]
|
||||
node _T_112 = eq(_T_111, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 222:61]
|
||||
node _T_113 = and(io.ic_debug_rd_en, _T_112) @[el2_ifu_ic_mem.scala 222:58]
|
||||
node _T_114 = or(io.ic_rd_en, _T_113) @[el2_ifu_ic_mem.scala 222:38]
|
||||
ic_rd_en_with_debug <= _T_114 @[el2_ifu_ic_mem.scala 222:23]
|
||||
node _T_115 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 224:37]
|
||||
node _T_116 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 224:71]
|
||||
node _T_117 = eq(_T_116, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 224:77]
|
||||
node _T_118 = and(_T_115, _T_117) @[el2_ifu_ic_mem.scala 224:56]
|
||||
node _T_119 = and(_T_118, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 224:86]
|
||||
node _T_120 = orr(io.ic_wr_en) @[el2_ifu_ic_mem.scala 224:124]
|
||||
node _T_121 = eq(_T_120, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 224:110]
|
||||
node ic_rw_addr_wrap = and(_T_119, _T_121) @[el2_ifu_ic_mem.scala 224:108]
|
||||
node _T_122 = eq(ic_rw_addr_wrap, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 226:40]
|
||||
node _T_123 = bits(_T_122, 0, 0) @[el2_ifu_ic_mem.scala 226:58]
|
||||
node _T_124 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 226:77]
|
||||
node _T_125 = bits(ic_rw_addr_q, 11, 5) @[el2_ifu_ic_mem.scala 227:21]
|
||||
node _T_126 = bits(ic_rw_addr_q_inc, 4, 3) @[el2_ifu_ic_mem.scala 227:82]
|
||||
node _T_127 = cat(_T_125, _T_126) @[Cat.scala 29:58]
|
||||
node _T_128 = mux(_T_123, _T_124, _T_127) @[el2_ifu_ic_mem.scala 226:38]
|
||||
node _T_129 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 228:17]
|
||||
wire ic_rw_addr_bank_q : UInt<9>[2] @[el2_ifu_ic_mem.scala 226:34]
|
||||
ic_rw_addr_bank_q[0] <= _T_130 @[el2_ifu_ic_mem.scala 226:34]
|
||||
ic_rw_addr_bank_q[1] <= _T_131 @[el2_ifu_ic_mem.scala 226:34]
|
||||
ic_rw_addr_bank_q[0] <= _T_128 @[el2_ifu_ic_mem.scala 226:34]
|
||||
ic_rw_addr_bank_q[1] <= _T_129 @[el2_ifu_ic_mem.scala 226:34]
|
||||
reg ic_b_rden_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 233:29]
|
||||
ic_b_rden_ff <= ic_b_rden @[el2_ifu_ic_mem.scala 233:29]
|
||||
node _T_132 = bits(ic_rw_addr_q, 4, 0) @[el2_ifu_ic_mem.scala 234:43]
|
||||
node _T_130 = bits(ic_rw_addr_q, 4, 0) @[el2_ifu_ic_mem.scala 234:43]
|
||||
reg ic_rw_addr_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 234:30]
|
||||
ic_rw_addr_ff <= _T_132 @[el2_ifu_ic_mem.scala 234:30]
|
||||
ic_rw_addr_ff <= _T_130 @[el2_ifu_ic_mem.scala 234:30]
|
||||
reg ic_debug_rd_way_en_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 235:38]
|
||||
ic_debug_rd_way_en_ff <= ic_debug_rd_way_en @[el2_ifu_ic_mem.scala 235:38]
|
||||
reg ic_debug_rd_en_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 236:34]
|
||||
ic_debug_rd_en_ff <= io.ic_debug_rd_en @[el2_ifu_ic_mem.scala 236:34]
|
||||
node _T_133 = bits(ic_rw_addr_ff, 4, 2) @[el2_ifu_ic_mem.scala 238:43]
|
||||
node _T_134 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
||||
node ic_cacheline_wrap_ff = eq(_T_133, _T_134) @[el2_ifu_ic_mem.scala 238:84]
|
||||
wire wb_out : UInt<71>[2][2] @[el2_ifu_ic_mem.scala 242:20]
|
||||
node _T_131 = bits(ic_rw_addr_ff, 4, 2) @[el2_ifu_ic_mem.scala 238:43]
|
||||
node _T_132 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
||||
node ic_cacheline_wrap_ff = eq(_T_131, _T_132) @[el2_ifu_ic_mem.scala 238:84]
|
||||
wire wb_dout : UInt<71>[2][2] @[el2_ifu_ic_mem.scala 242:21]
|
||||
cmem data_mem : UInt<71>[2][2][512] @[el2_ifu_ic_mem.scala 243:21]
|
||||
wb_out[0][0] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 245:18]
|
||||
node _T_135 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 246:73]
|
||||
node _T_136 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 247:83]
|
||||
node _T_137 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 248:26]
|
||||
node _T_138 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 248:52]
|
||||
node _T_139 = and(_T_137, _T_138) @[el2_ifu_ic_mem.scala 248:30]
|
||||
node _T_140 = bits(_T_139, 0, 0) @[el2_ifu_ic_mem.scala 248:57]
|
||||
when _T_140 : @[el2_ifu_ic_mem.scala 248:64]
|
||||
infer mport _T_141 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 249:15]
|
||||
_T_141[0][0] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
|
||||
wb_dout[0][0] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 245:19]
|
||||
node _T_133 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 246:73]
|
||||
node _T_134 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 247:83]
|
||||
node _T_135 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 248:26]
|
||||
node _T_136 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 248:52]
|
||||
node _T_137 = and(_T_135, _T_136) @[el2_ifu_ic_mem.scala 248:30]
|
||||
node _T_138 = bits(_T_137, 0, 0) @[el2_ifu_ic_mem.scala 248:57]
|
||||
when _T_138 : @[el2_ifu_ic_mem.scala 248:64]
|
||||
infer mport _T_139 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 249:15]
|
||||
_T_139[0][0] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
|
||||
skip @[el2_ifu_ic_mem.scala 248:64]
|
||||
else : @[el2_ifu_ic_mem.scala 250:69]
|
||||
node _T_142 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 250:33]
|
||||
node _T_143 = eq(_T_142, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
|
||||
node _T_144 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 250:57]
|
||||
node _T_145 = and(_T_143, _T_144) @[el2_ifu_ic_mem.scala 250:36]
|
||||
node _T_146 = bits(_T_145, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
|
||||
when _T_146 : @[el2_ifu_ic_mem.scala 250:69]
|
||||
infer mport _T_147 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 251:31]
|
||||
wb_out[0][0] <= _T_147[0][0] @[el2_ifu_ic_mem.scala 251:20]
|
||||
node _T_140 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 250:33]
|
||||
node _T_141 = eq(_T_140, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
|
||||
node _T_142 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 250:57]
|
||||
node _T_143 = and(_T_141, _T_142) @[el2_ifu_ic_mem.scala 250:36]
|
||||
node _T_144 = bits(_T_143, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
|
||||
when _T_144 : @[el2_ifu_ic_mem.scala 250:69]
|
||||
infer mport _T_145 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 251:32]
|
||||
wb_dout[0][0] <= _T_145[0][0] @[el2_ifu_ic_mem.scala 251:21]
|
||||
skip @[el2_ifu_ic_mem.scala 250:69]
|
||||
wb_out[0][1] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 245:18]
|
||||
node _T_148 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 246:73]
|
||||
node _T_149 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 247:83]
|
||||
node _T_150 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 248:26]
|
||||
node _T_151 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 248:52]
|
||||
node _T_152 = and(_T_150, _T_151) @[el2_ifu_ic_mem.scala 248:30]
|
||||
node _T_153 = bits(_T_152, 0, 0) @[el2_ifu_ic_mem.scala 248:57]
|
||||
when _T_153 : @[el2_ifu_ic_mem.scala 248:64]
|
||||
infer mport _T_154 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 249:15]
|
||||
_T_154[1][0] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
|
||||
wb_dout[0][1] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 245:19]
|
||||
node _T_146 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 246:73]
|
||||
node _T_147 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 247:83]
|
||||
node _T_148 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 248:26]
|
||||
node _T_149 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 248:52]
|
||||
node _T_150 = and(_T_148, _T_149) @[el2_ifu_ic_mem.scala 248:30]
|
||||
node _T_151 = bits(_T_150, 0, 0) @[el2_ifu_ic_mem.scala 248:57]
|
||||
when _T_151 : @[el2_ifu_ic_mem.scala 248:64]
|
||||
infer mport _T_152 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 249:15]
|
||||
_T_152[1][0] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
|
||||
skip @[el2_ifu_ic_mem.scala 248:64]
|
||||
else : @[el2_ifu_ic_mem.scala 250:69]
|
||||
node _T_155 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 250:33]
|
||||
node _T_156 = eq(_T_155, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
|
||||
node _T_157 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 250:57]
|
||||
node _T_158 = and(_T_156, _T_157) @[el2_ifu_ic_mem.scala 250:36]
|
||||
node _T_159 = bits(_T_158, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
|
||||
when _T_159 : @[el2_ifu_ic_mem.scala 250:69]
|
||||
infer mport _T_160 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 251:31]
|
||||
wb_out[0][1] <= _T_160[1][0] @[el2_ifu_ic_mem.scala 251:20]
|
||||
node _T_153 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 250:33]
|
||||
node _T_154 = eq(_T_153, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
|
||||
node _T_155 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 250:57]
|
||||
node _T_156 = and(_T_154, _T_155) @[el2_ifu_ic_mem.scala 250:36]
|
||||
node _T_157 = bits(_T_156, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
|
||||
when _T_157 : @[el2_ifu_ic_mem.scala 250:69]
|
||||
infer mport _T_158 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 251:32]
|
||||
wb_dout[0][1] <= _T_158[1][0] @[el2_ifu_ic_mem.scala 251:21]
|
||||
skip @[el2_ifu_ic_mem.scala 250:69]
|
||||
wb_out[1][0] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 245:18]
|
||||
node _T_161 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 246:73]
|
||||
node _T_162 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 247:83]
|
||||
node _T_163 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 248:26]
|
||||
node _T_164 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 248:52]
|
||||
node _T_165 = and(_T_163, _T_164) @[el2_ifu_ic_mem.scala 248:30]
|
||||
node _T_166 = bits(_T_165, 0, 0) @[el2_ifu_ic_mem.scala 248:57]
|
||||
when _T_166 : @[el2_ifu_ic_mem.scala 248:64]
|
||||
infer mport _T_167 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 249:15]
|
||||
_T_167[0][1] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
|
||||
wb_dout[1][0] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 245:19]
|
||||
node _T_159 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 246:73]
|
||||
node _T_160 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 247:83]
|
||||
node _T_161 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 248:26]
|
||||
node _T_162 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 248:52]
|
||||
node _T_163 = and(_T_161, _T_162) @[el2_ifu_ic_mem.scala 248:30]
|
||||
node _T_164 = bits(_T_163, 0, 0) @[el2_ifu_ic_mem.scala 248:57]
|
||||
when _T_164 : @[el2_ifu_ic_mem.scala 248:64]
|
||||
infer mport _T_165 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 249:15]
|
||||
_T_165[0][1] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
|
||||
skip @[el2_ifu_ic_mem.scala 248:64]
|
||||
else : @[el2_ifu_ic_mem.scala 250:69]
|
||||
node _T_168 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 250:33]
|
||||
node _T_169 = eq(_T_168, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
|
||||
node _T_170 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 250:57]
|
||||
node _T_171 = and(_T_169, _T_170) @[el2_ifu_ic_mem.scala 250:36]
|
||||
node _T_172 = bits(_T_171, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
|
||||
when _T_172 : @[el2_ifu_ic_mem.scala 250:69]
|
||||
infer mport _T_173 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 251:31]
|
||||
wb_out[1][0] <= _T_173[0][1] @[el2_ifu_ic_mem.scala 251:20]
|
||||
node _T_166 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 250:33]
|
||||
node _T_167 = eq(_T_166, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
|
||||
node _T_168 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 250:57]
|
||||
node _T_169 = and(_T_167, _T_168) @[el2_ifu_ic_mem.scala 250:36]
|
||||
node _T_170 = bits(_T_169, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
|
||||
when _T_170 : @[el2_ifu_ic_mem.scala 250:69]
|
||||
infer mport _T_171 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 251:32]
|
||||
wb_dout[1][0] <= _T_171[0][1] @[el2_ifu_ic_mem.scala 251:21]
|
||||
skip @[el2_ifu_ic_mem.scala 250:69]
|
||||
wb_out[1][1] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 245:18]
|
||||
node _T_174 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 246:73]
|
||||
node _T_175 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 247:83]
|
||||
node _T_176 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 248:26]
|
||||
node _T_177 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 248:52]
|
||||
node _T_178 = and(_T_176, _T_177) @[el2_ifu_ic_mem.scala 248:30]
|
||||
node _T_179 = bits(_T_178, 0, 0) @[el2_ifu_ic_mem.scala 248:57]
|
||||
when _T_179 : @[el2_ifu_ic_mem.scala 248:64]
|
||||
infer mport _T_180 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 249:15]
|
||||
_T_180[1][1] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
|
||||
wb_dout[1][1] <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 245:19]
|
||||
node _T_172 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 246:73]
|
||||
node _T_173 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 247:83]
|
||||
node _T_174 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 248:26]
|
||||
node _T_175 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 248:52]
|
||||
node _T_176 = and(_T_174, _T_175) @[el2_ifu_ic_mem.scala 248:30]
|
||||
node _T_177 = bits(_T_176, 0, 0) @[el2_ifu_ic_mem.scala 248:57]
|
||||
when _T_177 : @[el2_ifu_ic_mem.scala 248:64]
|
||||
infer mport _T_178 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 249:15]
|
||||
_T_178[1][1] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
|
||||
skip @[el2_ifu_ic_mem.scala 248:64]
|
||||
else : @[el2_ifu_ic_mem.scala 250:69]
|
||||
node _T_181 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 250:33]
|
||||
node _T_182 = eq(_T_181, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
|
||||
node _T_183 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 250:57]
|
||||
node _T_184 = and(_T_182, _T_183) @[el2_ifu_ic_mem.scala 250:36]
|
||||
node _T_185 = bits(_T_184, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
|
||||
when _T_185 : @[el2_ifu_ic_mem.scala 250:69]
|
||||
infer mport _T_186 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 251:31]
|
||||
wb_out[1][1] <= _T_186[1][1] @[el2_ifu_ic_mem.scala 251:20]
|
||||
node _T_179 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 250:33]
|
||||
node _T_180 = eq(_T_179, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
|
||||
node _T_181 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 250:57]
|
||||
node _T_182 = and(_T_180, _T_181) @[el2_ifu_ic_mem.scala 250:36]
|
||||
node _T_183 = bits(_T_182, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
|
||||
when _T_183 : @[el2_ifu_ic_mem.scala 250:69]
|
||||
infer mport _T_184 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 251:32]
|
||||
wb_dout[1][1] <= _T_184[1][1] @[el2_ifu_ic_mem.scala 251:21]
|
||||
skip @[el2_ifu_ic_mem.scala 250:69]
|
||||
io.test_port[0][0] <= wb_out[0][0] @[el2_ifu_ic_mem.scala 254:16]
|
||||
io.test_port[0][1] <= wb_out[0][1] @[el2_ifu_ic_mem.scala 254:16]
|
||||
io.test_port[1][0] <= wb_out[1][0] @[el2_ifu_ic_mem.scala 254:16]
|
||||
io.test_port[1][1] <= wb_out[1][1] @[el2_ifu_ic_mem.scala 254:16]
|
||||
io.test_port[0][0] <= wb_dout[0][0] @[el2_ifu_ic_mem.scala 254:16]
|
||||
io.test_port[0][1] <= wb_dout[0][1] @[el2_ifu_ic_mem.scala 254:16]
|
||||
io.test_port[1][0] <= wb_dout[1][0] @[el2_ifu_ic_mem.scala 254:16]
|
||||
io.test_port[1][1] <= wb_dout[1][1] @[el2_ifu_ic_mem.scala 254:16]
|
||||
node _T_185 = bits(ic_debug_rd_en_ff, 0, 0) @[el2_ifu_ic_mem.scala 255:43]
|
||||
node ic_rd_hit_q = mux(_T_185, ic_debug_rd_way_en_ff, io.ic_rd_hit) @[el2_ifu_ic_mem.scala 255:24]
|
||||
ic_bank_wr_data[0] <= io.ic_wr_data[0] @[el2_ifu_ic_mem.scala 256:19]
|
||||
ic_bank_wr_data[1] <= io.ic_wr_data[1] @[el2_ifu_ic_mem.scala 256:19]
|
||||
node _T_186 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 259:59]
|
||||
node _T_187 = eq(_T_186, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 259:95]
|
||||
node _T_188 = bits(_T_187, 0, 0) @[el2_ifu_ic_mem.scala 259:103]
|
||||
node _T_189 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 259:59]
|
||||
node _T_190 = eq(_T_189, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 259:95]
|
||||
node _T_191 = bits(_T_190, 0, 0) @[el2_ifu_ic_mem.scala 259:103]
|
||||
node _T_192 = mux(_T_188, wb_dout[0][0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_193 = mux(_T_191, wb_dout[0][1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_194 = or(_T_192, _T_193) @[Mux.scala 27:72]
|
||||
wire _T_195 : UInt<71> @[Mux.scala 27:72]
|
||||
_T_195 <= _T_194 @[Mux.scala 27:72]
|
||||
node _T_196 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 260:59]
|
||||
node _T_197 = sub(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 260:102]
|
||||
node _T_198 = tail(_T_197, 1) @[el2_ifu_ic_mem.scala 260:102]
|
||||
node _T_199 = eq(_T_196, _T_198) @[el2_ifu_ic_mem.scala 260:95]
|
||||
node _T_200 = bits(_T_199, 0, 0) @[el2_ifu_ic_mem.scala 260:109]
|
||||
node _T_201 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 260:59]
|
||||
node _T_202 = sub(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 260:102]
|
||||
node _T_203 = tail(_T_202, 1) @[el2_ifu_ic_mem.scala 260:102]
|
||||
node _T_204 = eq(_T_201, _T_203) @[el2_ifu_ic_mem.scala 260:95]
|
||||
node _T_205 = bits(_T_204, 0, 0) @[el2_ifu_ic_mem.scala 260:109]
|
||||
node _T_206 = mux(_T_200, wb_dout[0][0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_207 = mux(_T_205, wb_dout[0][1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_208 = or(_T_206, _T_207) @[Mux.scala 27:72]
|
||||
wire _T_209 : UInt<71> @[Mux.scala 27:72]
|
||||
_T_209 <= _T_208 @[Mux.scala 27:72]
|
||||
node wb_dout_way_pre_0 = cat(_T_195, _T_209) @[Cat.scala 29:58]
|
||||
node _T_210 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 259:59]
|
||||
node _T_211 = eq(_T_210, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 259:95]
|
||||
node _T_212 = bits(_T_211, 0, 0) @[el2_ifu_ic_mem.scala 259:103]
|
||||
node _T_213 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 259:59]
|
||||
node _T_214 = eq(_T_213, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 259:95]
|
||||
node _T_215 = bits(_T_214, 0, 0) @[el2_ifu_ic_mem.scala 259:103]
|
||||
node _T_216 = mux(_T_212, wb_dout[1][0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_217 = mux(_T_215, wb_dout[1][1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_218 = or(_T_216, _T_217) @[Mux.scala 27:72]
|
||||
wire _T_219 : UInt<71> @[Mux.scala 27:72]
|
||||
_T_219 <= _T_218 @[Mux.scala 27:72]
|
||||
node _T_220 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 260:59]
|
||||
node _T_221 = sub(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 260:102]
|
||||
node _T_222 = tail(_T_221, 1) @[el2_ifu_ic_mem.scala 260:102]
|
||||
node _T_223 = eq(_T_220, _T_222) @[el2_ifu_ic_mem.scala 260:95]
|
||||
node _T_224 = bits(_T_223, 0, 0) @[el2_ifu_ic_mem.scala 260:109]
|
||||
node _T_225 = bits(ic_rw_addr_ff, 2, 2) @[el2_ifu_ic_mem.scala 260:59]
|
||||
node _T_226 = sub(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 260:102]
|
||||
node _T_227 = tail(_T_226, 1) @[el2_ifu_ic_mem.scala 260:102]
|
||||
node _T_228 = eq(_T_225, _T_227) @[el2_ifu_ic_mem.scala 260:95]
|
||||
node _T_229 = bits(_T_228, 0, 0) @[el2_ifu_ic_mem.scala 260:109]
|
||||
node _T_230 = mux(_T_224, wb_dout[1][0], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_231 = mux(_T_229, wb_dout[1][1], UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_232 = or(_T_230, _T_231) @[Mux.scala 27:72]
|
||||
wire _T_233 : UInt<71> @[Mux.scala 27:72]
|
||||
_T_233 <= _T_232 @[Mux.scala 27:72]
|
||||
node wb_dout_way_pre_1 = cat(_T_219, _T_233) @[Cat.scala 29:58]
|
||||
node _T_234 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 262:78]
|
||||
node _T_235 = eq(_T_234, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 262:83]
|
||||
node _T_236 = bits(_T_235, 0, 0) @[el2_ifu_ic_mem.scala 262:91]
|
||||
node _T_237 = bits(wb_dout_way_pre_0, 63, 0) @[el2_ifu_ic_mem.scala 262:117]
|
||||
node _T_238 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 263:45]
|
||||
node _T_239 = eq(_T_238, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 263:50]
|
||||
node _T_240 = bits(_T_239, 0, 0) @[el2_ifu_ic_mem.scala 263:58]
|
||||
node _T_241 = bits(wb_dout_way_pre_0, 86, 71) @[el2_ifu_ic_mem.scala 263:88]
|
||||
node _T_242 = bits(wb_dout_way_pre_0, 63, 16) @[el2_ifu_ic_mem.scala 263:114]
|
||||
node _T_243 = cat(_T_241, _T_242) @[Cat.scala 29:58]
|
||||
node _T_244 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 264:45]
|
||||
node _T_245 = eq(_T_244, UInt<2>("h02")) @[el2_ifu_ic_mem.scala 264:50]
|
||||
node _T_246 = bits(_T_245, 0, 0) @[el2_ifu_ic_mem.scala 264:58]
|
||||
node _T_247 = bits(wb_dout_way_pre_0, 102, 71) @[el2_ifu_ic_mem.scala 264:88]
|
||||
node _T_248 = bits(wb_dout_way_pre_0, 63, 32) @[el2_ifu_ic_mem.scala 264:115]
|
||||
node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58]
|
||||
node _T_250 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 265:45]
|
||||
node _T_251 = eq(_T_250, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 265:50]
|
||||
node _T_252 = bits(_T_251, 0, 0) @[el2_ifu_ic_mem.scala 265:58]
|
||||
node _T_253 = bits(wb_dout_way_pre_0, 119, 71) @[el2_ifu_ic_mem.scala 265:88]
|
||||
node _T_254 = bits(wb_dout_way_pre_0, 63, 48) @[el2_ifu_ic_mem.scala 265:115]
|
||||
node _T_255 = cat(_T_253, _T_254) @[Cat.scala 29:58]
|
||||
node _T_256 = mux(_T_236, _T_237, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_257 = mux(_T_240, _T_243, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_258 = mux(_T_246, _T_249, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_259 = mux(_T_252, _T_255, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_260 = or(_T_256, _T_257) @[Mux.scala 27:72]
|
||||
node _T_261 = or(_T_260, _T_258) @[Mux.scala 27:72]
|
||||
node _T_262 = or(_T_261, _T_259) @[Mux.scala 27:72]
|
||||
wire wb_dout_way_0 : UInt<65> @[Mux.scala 27:72]
|
||||
wb_dout_way_0 <= _T_262 @[Mux.scala 27:72]
|
||||
node _T_263 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 262:78]
|
||||
node _T_264 = eq(_T_263, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 262:83]
|
||||
node _T_265 = bits(_T_264, 0, 0) @[el2_ifu_ic_mem.scala 262:91]
|
||||
node _T_266 = bits(wb_dout_way_pre_1, 63, 0) @[el2_ifu_ic_mem.scala 262:117]
|
||||
node _T_267 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 263:45]
|
||||
node _T_268 = eq(_T_267, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 263:50]
|
||||
node _T_269 = bits(_T_268, 0, 0) @[el2_ifu_ic_mem.scala 263:58]
|
||||
node _T_270 = bits(wb_dout_way_pre_1, 86, 71) @[el2_ifu_ic_mem.scala 263:88]
|
||||
node _T_271 = bits(wb_dout_way_pre_1, 63, 16) @[el2_ifu_ic_mem.scala 263:114]
|
||||
node _T_272 = cat(_T_270, _T_271) @[Cat.scala 29:58]
|
||||
node _T_273 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 264:45]
|
||||
node _T_274 = eq(_T_273, UInt<2>("h02")) @[el2_ifu_ic_mem.scala 264:50]
|
||||
node _T_275 = bits(_T_274, 0, 0) @[el2_ifu_ic_mem.scala 264:58]
|
||||
node _T_276 = bits(wb_dout_way_pre_1, 102, 71) @[el2_ifu_ic_mem.scala 264:88]
|
||||
node _T_277 = bits(wb_dout_way_pre_1, 63, 32) @[el2_ifu_ic_mem.scala 264:115]
|
||||
node _T_278 = cat(_T_276, _T_277) @[Cat.scala 29:58]
|
||||
node _T_279 = bits(ic_rw_addr_ff, 1, 0) @[el2_ifu_ic_mem.scala 265:45]
|
||||
node _T_280 = eq(_T_279, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 265:50]
|
||||
node _T_281 = bits(_T_280, 0, 0) @[el2_ifu_ic_mem.scala 265:58]
|
||||
node _T_282 = bits(wb_dout_way_pre_1, 119, 71) @[el2_ifu_ic_mem.scala 265:88]
|
||||
node _T_283 = bits(wb_dout_way_pre_1, 63, 48) @[el2_ifu_ic_mem.scala 265:115]
|
||||
node _T_284 = cat(_T_282, _T_283) @[Cat.scala 29:58]
|
||||
node _T_285 = mux(_T_265, _T_266, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_286 = mux(_T_269, _T_272, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_287 = mux(_T_275, _T_278, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_288 = mux(_T_281, _T_284, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_289 = or(_T_285, _T_286) @[Mux.scala 27:72]
|
||||
node _T_290 = or(_T_289, _T_287) @[Mux.scala 27:72]
|
||||
node _T_291 = or(_T_290, _T_288) @[Mux.scala 27:72]
|
||||
wire wb_dout_way_1 : UInt<65> @[Mux.scala 27:72]
|
||||
wb_dout_way_1 <= _T_291 @[Mux.scala 27:72]
|
||||
node _T_292 = bits(io.ic_sel_premux_data, 0, 0) @[el2_ifu_ic_mem.scala 267:92]
|
||||
node wb_dout_way_with_premux_0 = mux(_T_292, io.ic_premux_data, wb_dout_way_0) @[el2_ifu_ic_mem.scala 267:69]
|
||||
node _T_293 = bits(io.ic_sel_premux_data, 0, 0) @[el2_ifu_ic_mem.scala 267:92]
|
||||
node wb_dout_way_with_premux_1 = mux(_T_293, io.ic_premux_data, wb_dout_way_1) @[el2_ifu_ic_mem.scala 267:69]
|
||||
node _T_294 = bits(ic_rd_hit_q, 0, 0) @[el2_ifu_ic_mem.scala 269:71]
|
||||
node _T_295 = or(_T_294, io.ic_sel_premux_data) @[el2_ifu_ic_mem.scala 269:75]
|
||||
node _T_296 = bits(_T_295, 0, 0) @[el2_ifu_ic_mem.scala 269:100]
|
||||
node _T_297 = bits(ic_rd_hit_q, 1, 1) @[el2_ifu_ic_mem.scala 269:71]
|
||||
node _T_298 = or(_T_297, io.ic_sel_premux_data) @[el2_ifu_ic_mem.scala 269:75]
|
||||
node _T_299 = bits(_T_298, 0, 0) @[el2_ifu_ic_mem.scala 269:100]
|
||||
node _T_300 = mux(_T_296, wb_dout_way_with_premux_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_301 = mux(_T_299, wb_dout_way_with_premux_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_302 = or(_T_300, _T_301) @[Mux.scala 27:72]
|
||||
wire ic_rd_data : UInt<65> @[Mux.scala 27:72]
|
||||
ic_rd_data <= _T_302 @[Mux.scala 27:72]
|
||||
|
||||
|
|
|
|||
542
EL2_IC_DATA.v
542
EL2_IC_DATA.v
|
|
@ -35,105 +35,105 @@ module EL2_IC_DATA(
|
|||
reg [95:0] _RAND_3;
|
||||
`endif // RANDOMIZE_MEM_INIT
|
||||
reg [70:0] data_mem_0_0 [0:511]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_147_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_147_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_160_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_160_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_173_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_173_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_186_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_186_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_141_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_141_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_141_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_141_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_154_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_154_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_154_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_154_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_167_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_167_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_167_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_167_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_180_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_180_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_180_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_180_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_145_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_145_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_158_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_158_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_171_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_171_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_184_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_184_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_139_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_139_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_139_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_139_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_152_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_152_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_152_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_152_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_165_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_165_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_165_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_165_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_178_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_178_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_178_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_178_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
reg [70:0] data_mem_0_1 [0:511]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_147_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_147_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_160_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_160_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_173_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_173_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_186_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_186_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_141_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_141_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_141_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_141_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_154_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_154_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_154_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_154_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_167_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_167_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_167_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_167_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_180_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_180_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_180_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_180_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_145_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_145_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_158_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_158_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_171_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_171_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_184_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_184_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_139_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_139_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_139_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_139_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_152_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_152_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_152_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_152_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_165_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_165_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_165_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_165_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_178_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_178_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_178_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_178_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
reg [70:0] data_mem_1_0 [0:511]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_147_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_147_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_160_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_160_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_173_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_173_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_186_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_186_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_141_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_141_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_141_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_141_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_154_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_154_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_154_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_154_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_167_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_167_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_167_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_167_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_180_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_180_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_180_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_180_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_145_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_145_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_158_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_158_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_171_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_171_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_184_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_184_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_139_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_139_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_139_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_139_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_152_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_152_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_152_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_152_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_165_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_165_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_165_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_165_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_178_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_178_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_178_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_178_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
reg [70:0] data_mem_1_1 [0:511]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_147_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_147_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_160_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_160_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_173_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_173_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_186_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_186_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_141_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_141_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_141_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_141_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_154_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_154_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_154_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_154_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_167_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_167_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_167_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_167_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_180_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_180_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_180_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_180_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_145_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_145_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_158_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_158_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_171_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_171_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_184_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_184_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_139_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_139_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_139_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_139_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_152_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_152_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_152_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_152_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_165_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_165_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_165_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_165_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_178_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_178_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_178_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_178_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire _T = ~io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 200:70]
|
||||
wire _T_5 = io_ic_debug_wr_en & _T; // @[el2_ifu_ic_mem.scala 201:68]
|
||||
wire [1:0] _T_7 = {_T_5,_T_5}; // @[Cat.scala 29:58]
|
||||
|
|
@ -149,156 +149,156 @@ module EL2_IC_DATA(
|
|||
wire [1:0] _T_21 = io_ic_debug_addr[0] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||
wire [1:0] _T_22 = ic_debug_wr_way_en & _T_21; // @[el2_ifu_ic_mem.scala 210:38]
|
||||
wire [1:0] ic_b_sb_wren_1 = io_ic_wr_en | _T_22; // @[el2_ifu_ic_mem.scala 210:17]
|
||||
wire _T_37 = ~ic_rw_addr_q[2]; // @[el2_ifu_ic_mem.scala 214:16]
|
||||
wire _T_42 = ic_rw_addr_q[1:0] == 2'h3; // @[el2_ifu_ic_mem.scala 215:91]
|
||||
wire _T_56 = ic_rw_addr_q[2] & _T_42; // @[Mux.scala 27:72]
|
||||
wire _T_59 = _T_37 | _T_56; // @[Mux.scala 27:72]
|
||||
wire _T_113 = |io_ic_wr_en; // @[el2_ifu_ic_mem.scala 222:74]
|
||||
wire _T_114 = ~_T_113; // @[el2_ifu_ic_mem.scala 222:61]
|
||||
wire _T_115 = io_ic_debug_rd_en & _T_114; // @[el2_ifu_ic_mem.scala 222:58]
|
||||
wire ic_rd_en_with_debug = io_ic_rd_en | _T_115; // @[el2_ifu_ic_mem.scala 222:38]
|
||||
wire _T_63 = _T_59 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 217:117]
|
||||
wire _T_87 = _T_37 & _T_42; // @[Mux.scala 27:72]
|
||||
wire _T_90 = ic_rw_addr_q[2] | _T_87; // @[Mux.scala 27:72]
|
||||
wire _T_92 = _T_90 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 217:117]
|
||||
wire [1:0] ic_b_rden = {_T_92,_T_63}; // @[Cat.scala 29:58]
|
||||
wire _T_35 = ~ic_rw_addr_q[2]; // @[el2_ifu_ic_mem.scala 214:16]
|
||||
wire _T_40 = ic_rw_addr_q[1:0] == 2'h3; // @[el2_ifu_ic_mem.scala 215:91]
|
||||
wire _T_54 = ic_rw_addr_q[2] & _T_40; // @[Mux.scala 27:72]
|
||||
wire _T_57 = _T_35 | _T_54; // @[Mux.scala 27:72]
|
||||
wire _T_111 = |io_ic_wr_en; // @[el2_ifu_ic_mem.scala 222:74]
|
||||
wire _T_112 = ~_T_111; // @[el2_ifu_ic_mem.scala 222:61]
|
||||
wire _T_113 = io_ic_debug_rd_en & _T_112; // @[el2_ifu_ic_mem.scala 222:58]
|
||||
wire ic_rd_en_with_debug = io_ic_rd_en | _T_113; // @[el2_ifu_ic_mem.scala 222:38]
|
||||
wire _T_61 = _T_57 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 217:117]
|
||||
wire _T_85 = _T_35 & _T_40; // @[Mux.scala 27:72]
|
||||
wire _T_88 = ic_rw_addr_q[2] | _T_85; // @[Mux.scala 27:72]
|
||||
wire _T_90 = _T_88 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 217:117]
|
||||
wire [1:0] ic_b_rden = {_T_90,_T_61}; // @[Cat.scala 29:58]
|
||||
wire [1:0] ic_b_sb_rden_0 = ic_b_rden[0] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||
wire [1:0] ic_b_sb_rden_1 = ic_b_rden[1] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||
wire _T_98 = ic_b_sb_rden_0[0] | io_clk_override; // @[el2_ifu_ic_mem.scala 220:25]
|
||||
wire _T_100 = _T_98 | ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 220:43]
|
||||
wire _T_102 = ic_b_sb_rden_0[1] | io_clk_override; // @[el2_ifu_ic_mem.scala 220:25]
|
||||
wire _T_104 = _T_102 | ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 220:43]
|
||||
wire [1:0] ic_bank_way_clken_0 = {_T_100,_T_104}; // @[Cat.scala 29:58]
|
||||
wire _T_106 = ic_b_sb_rden_1[0] | io_clk_override; // @[el2_ifu_ic_mem.scala 220:25]
|
||||
wire _T_108 = _T_106 | ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 220:43]
|
||||
wire _T_110 = ic_b_sb_rden_1[1] | io_clk_override; // @[el2_ifu_ic_mem.scala 220:25]
|
||||
wire _T_112 = _T_110 | ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 220:43]
|
||||
wire [1:0] ic_bank_way_clken_1 = {_T_108,_T_112}; // @[Cat.scala 29:58]
|
||||
wire _T_121 = _T_56 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 224:86]
|
||||
wire ic_rw_addr_wrap = _T_121 & _T_114; // @[el2_ifu_ic_mem.scala 224:108]
|
||||
wire _T_124 = ~ic_rw_addr_wrap; // @[el2_ifu_ic_mem.scala 226:40]
|
||||
wire [8:0] _T_129 = {ic_rw_addr_q[11:5],ic_rw_addr_q_inc[4:3]}; // @[Cat.scala 29:58]
|
||||
wire _T_139 = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 248:30]
|
||||
wire _T_143 = ~ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 250:17]
|
||||
wire _T_145 = _T_143 & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 250:36]
|
||||
wire [70:0] _GEN_3 = _T_145 ? data_mem_0_0__T_147_data : 71'h0; // @[el2_ifu_ic_mem.scala 250:69]
|
||||
wire _T_152 = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 248:30]
|
||||
wire _T_156 = ~ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 250:17]
|
||||
wire _T_158 = _T_156 & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 250:36]
|
||||
wire [70:0] _GEN_17 = _T_158 ? data_mem_1_0__T_160_data : 71'h0; // @[el2_ifu_ic_mem.scala 250:69]
|
||||
wire _T_165 = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 248:30]
|
||||
wire _T_169 = ~ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 250:17]
|
||||
wire _T_171 = _T_169 & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 250:36]
|
||||
wire [70:0] _GEN_31 = _T_171 ? data_mem_0_1__T_173_data : 71'h0; // @[el2_ifu_ic_mem.scala 250:69]
|
||||
wire _T_178 = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 248:30]
|
||||
wire _T_182 = ~ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 250:17]
|
||||
wire _T_184 = _T_182 & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 250:36]
|
||||
wire [70:0] _GEN_45 = _T_184 ? data_mem_1_1__T_186_data : 71'h0; // @[el2_ifu_ic_mem.scala 250:69]
|
||||
assign data_mem_0_0__T_147_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_0__T_147_data = data_mem_0_0[data_mem_0_0__T_147_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_0__T_160_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_0__T_160_data = data_mem_0_0[data_mem_0_0__T_160_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_0__T_173_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_0__T_173_data = data_mem_0_0[data_mem_0_0__T_173_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_0__T_186_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_0__T_186_data = data_mem_0_0[data_mem_0_0__T_186_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_0__T_141_data = io_test_in;
|
||||
assign data_mem_0_0__T_141_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_0__T_141_mask = 1'h1;
|
||||
assign data_mem_0_0__T_141_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
|
||||
assign data_mem_0_0__T_154_data = 71'h0;
|
||||
assign data_mem_0_0__T_154_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_0__T_154_mask = 1'h0;
|
||||
assign data_mem_0_0__T_154_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
|
||||
assign data_mem_0_0__T_167_data = 71'h0;
|
||||
assign data_mem_0_0__T_167_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_0__T_167_mask = 1'h0;
|
||||
assign data_mem_0_0__T_167_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
|
||||
assign data_mem_0_0__T_180_data = 71'h0;
|
||||
assign data_mem_0_0__T_180_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_0__T_180_mask = 1'h0;
|
||||
assign data_mem_0_0__T_180_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
|
||||
assign data_mem_0_1__T_147_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_1__T_147_data = data_mem_0_1[data_mem_0_1__T_147_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_1__T_160_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_1__T_160_data = data_mem_0_1[data_mem_0_1__T_160_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_1__T_173_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_1__T_173_data = data_mem_0_1[data_mem_0_1__T_173_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_1__T_186_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_1__T_186_data = data_mem_0_1[data_mem_0_1__T_186_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_1__T_141_data = 71'h0;
|
||||
assign data_mem_0_1__T_141_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_1__T_141_mask = 1'h0;
|
||||
assign data_mem_0_1__T_141_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
|
||||
assign data_mem_0_1__T_154_data = 71'h0;
|
||||
assign data_mem_0_1__T_154_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_1__T_154_mask = 1'h0;
|
||||
assign data_mem_0_1__T_154_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
|
||||
assign data_mem_0_1__T_167_data = io_test_in;
|
||||
assign data_mem_0_1__T_167_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_1__T_167_mask = 1'h1;
|
||||
assign data_mem_0_1__T_167_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
|
||||
assign data_mem_0_1__T_180_data = 71'h0;
|
||||
assign data_mem_0_1__T_180_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_1__T_180_mask = 1'h0;
|
||||
assign data_mem_0_1__T_180_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
|
||||
assign data_mem_1_0__T_147_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_0__T_147_data = data_mem_1_0[data_mem_1_0__T_147_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_0__T_160_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_0__T_160_data = data_mem_1_0[data_mem_1_0__T_160_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_0__T_173_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_0__T_173_data = data_mem_1_0[data_mem_1_0__T_173_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_0__T_186_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_0__T_186_data = data_mem_1_0[data_mem_1_0__T_186_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_0__T_141_data = 71'h0;
|
||||
assign data_mem_1_0__T_141_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_0__T_141_mask = 1'h0;
|
||||
assign data_mem_1_0__T_141_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
|
||||
assign data_mem_1_0__T_154_data = io_test_in;
|
||||
assign data_mem_1_0__T_154_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_0__T_154_mask = 1'h1;
|
||||
assign data_mem_1_0__T_154_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
|
||||
assign data_mem_1_0__T_167_data = 71'h0;
|
||||
assign data_mem_1_0__T_167_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_0__T_167_mask = 1'h0;
|
||||
assign data_mem_1_0__T_167_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
|
||||
assign data_mem_1_0__T_180_data = 71'h0;
|
||||
assign data_mem_1_0__T_180_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_0__T_180_mask = 1'h0;
|
||||
assign data_mem_1_0__T_180_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
|
||||
assign data_mem_1_1__T_147_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_1__T_147_data = data_mem_1_1[data_mem_1_1__T_147_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_1__T_160_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_1__T_160_data = data_mem_1_1[data_mem_1_1__T_160_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_1__T_173_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_1__T_173_data = data_mem_1_1[data_mem_1_1__T_173_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_1__T_186_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_1__T_186_data = data_mem_1_1[data_mem_1_1__T_186_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_1__T_141_data = 71'h0;
|
||||
assign data_mem_1_1__T_141_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_1__T_141_mask = 1'h0;
|
||||
assign data_mem_1_1__T_141_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
|
||||
assign data_mem_1_1__T_154_data = 71'h0;
|
||||
assign data_mem_1_1__T_154_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_1__T_154_mask = 1'h0;
|
||||
assign data_mem_1_1__T_154_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
|
||||
assign data_mem_1_1__T_167_data = 71'h0;
|
||||
assign data_mem_1_1__T_167_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_1__T_167_mask = 1'h0;
|
||||
assign data_mem_1_1__T_167_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
|
||||
assign data_mem_1_1__T_180_data = io_test_in;
|
||||
assign data_mem_1_1__T_180_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_1__T_180_mask = 1'h1;
|
||||
assign data_mem_1_1__T_180_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
|
||||
wire _T_96 = ic_b_sb_rden_0[0] | io_clk_override; // @[el2_ifu_ic_mem.scala 220:25]
|
||||
wire _T_98 = _T_96 | ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 220:43]
|
||||
wire _T_100 = ic_b_sb_rden_0[1] | io_clk_override; // @[el2_ifu_ic_mem.scala 220:25]
|
||||
wire _T_102 = _T_100 | ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 220:43]
|
||||
wire [1:0] ic_bank_way_clken_0 = {_T_98,_T_102}; // @[Cat.scala 29:58]
|
||||
wire _T_104 = ic_b_sb_rden_1[0] | io_clk_override; // @[el2_ifu_ic_mem.scala 220:25]
|
||||
wire _T_106 = _T_104 | ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 220:43]
|
||||
wire _T_108 = ic_b_sb_rden_1[1] | io_clk_override; // @[el2_ifu_ic_mem.scala 220:25]
|
||||
wire _T_110 = _T_108 | ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 220:43]
|
||||
wire [1:0] ic_bank_way_clken_1 = {_T_106,_T_110}; // @[Cat.scala 29:58]
|
||||
wire _T_119 = _T_54 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 224:86]
|
||||
wire ic_rw_addr_wrap = _T_119 & _T_112; // @[el2_ifu_ic_mem.scala 224:108]
|
||||
wire _T_122 = ~ic_rw_addr_wrap; // @[el2_ifu_ic_mem.scala 226:40]
|
||||
wire [8:0] _T_127 = {ic_rw_addr_q[11:5],ic_rw_addr_q_inc[4:3]}; // @[Cat.scala 29:58]
|
||||
wire _T_137 = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 248:30]
|
||||
wire _T_141 = ~ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 250:17]
|
||||
wire _T_143 = _T_141 & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 250:36]
|
||||
wire [70:0] _GEN_3 = _T_143 ? data_mem_0_0__T_145_data : 71'h0; // @[el2_ifu_ic_mem.scala 250:69]
|
||||
wire _T_150 = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 248:30]
|
||||
wire _T_154 = ~ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 250:17]
|
||||
wire _T_156 = _T_154 & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 250:36]
|
||||
wire [70:0] _GEN_17 = _T_156 ? data_mem_1_0__T_158_data : 71'h0; // @[el2_ifu_ic_mem.scala 250:69]
|
||||
wire _T_163 = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 248:30]
|
||||
wire _T_167 = ~ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 250:17]
|
||||
wire _T_169 = _T_167 & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 250:36]
|
||||
wire [70:0] _GEN_31 = _T_169 ? data_mem_0_1__T_171_data : 71'h0; // @[el2_ifu_ic_mem.scala 250:69]
|
||||
wire _T_176 = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 248:30]
|
||||
wire _T_180 = ~ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 250:17]
|
||||
wire _T_182 = _T_180 & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 250:36]
|
||||
wire [70:0] _GEN_45 = _T_182 ? data_mem_1_1__T_184_data : 71'h0; // @[el2_ifu_ic_mem.scala 250:69]
|
||||
assign data_mem_0_0__T_145_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
|
||||
assign data_mem_0_0__T_145_data = data_mem_0_0[data_mem_0_0__T_145_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_0__T_158_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_0__T_158_data = data_mem_0_0[data_mem_0_0__T_158_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_0__T_171_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
|
||||
assign data_mem_0_0__T_171_data = data_mem_0_0[data_mem_0_0__T_171_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_0__T_184_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_0__T_184_data = data_mem_0_0[data_mem_0_0__T_184_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_0__T_139_data = io_test_in;
|
||||
assign data_mem_0_0__T_139_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
|
||||
assign data_mem_0_0__T_139_mask = 1'h1;
|
||||
assign data_mem_0_0__T_139_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
|
||||
assign data_mem_0_0__T_152_data = 71'h0;
|
||||
assign data_mem_0_0__T_152_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_0__T_152_mask = 1'h0;
|
||||
assign data_mem_0_0__T_152_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
|
||||
assign data_mem_0_0__T_165_data = 71'h0;
|
||||
assign data_mem_0_0__T_165_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
|
||||
assign data_mem_0_0__T_165_mask = 1'h0;
|
||||
assign data_mem_0_0__T_165_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
|
||||
assign data_mem_0_0__T_178_data = 71'h0;
|
||||
assign data_mem_0_0__T_178_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_0__T_178_mask = 1'h0;
|
||||
assign data_mem_0_0__T_178_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
|
||||
assign data_mem_0_1__T_145_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
|
||||
assign data_mem_0_1__T_145_data = data_mem_0_1[data_mem_0_1__T_145_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_1__T_158_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_1__T_158_data = data_mem_0_1[data_mem_0_1__T_158_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_1__T_171_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
|
||||
assign data_mem_0_1__T_171_data = data_mem_0_1[data_mem_0_1__T_171_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_1__T_184_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_1__T_184_data = data_mem_0_1[data_mem_0_1__T_184_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_1__T_139_data = 71'h0;
|
||||
assign data_mem_0_1__T_139_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
|
||||
assign data_mem_0_1__T_139_mask = 1'h0;
|
||||
assign data_mem_0_1__T_139_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
|
||||
assign data_mem_0_1__T_152_data = 71'h0;
|
||||
assign data_mem_0_1__T_152_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_1__T_152_mask = 1'h0;
|
||||
assign data_mem_0_1__T_152_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
|
||||
assign data_mem_0_1__T_165_data = io_test_in;
|
||||
assign data_mem_0_1__T_165_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
|
||||
assign data_mem_0_1__T_165_mask = 1'h1;
|
||||
assign data_mem_0_1__T_165_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
|
||||
assign data_mem_0_1__T_178_data = 71'h0;
|
||||
assign data_mem_0_1__T_178_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_1__T_178_mask = 1'h0;
|
||||
assign data_mem_0_1__T_178_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
|
||||
assign data_mem_1_0__T_145_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
|
||||
assign data_mem_1_0__T_145_data = data_mem_1_0[data_mem_1_0__T_145_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_0__T_158_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_0__T_158_data = data_mem_1_0[data_mem_1_0__T_158_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_0__T_171_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
|
||||
assign data_mem_1_0__T_171_data = data_mem_1_0[data_mem_1_0__T_171_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_0__T_184_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_0__T_184_data = data_mem_1_0[data_mem_1_0__T_184_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_0__T_139_data = 71'h0;
|
||||
assign data_mem_1_0__T_139_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
|
||||
assign data_mem_1_0__T_139_mask = 1'h0;
|
||||
assign data_mem_1_0__T_139_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
|
||||
assign data_mem_1_0__T_152_data = io_test_in;
|
||||
assign data_mem_1_0__T_152_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_0__T_152_mask = 1'h1;
|
||||
assign data_mem_1_0__T_152_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
|
||||
assign data_mem_1_0__T_165_data = 71'h0;
|
||||
assign data_mem_1_0__T_165_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
|
||||
assign data_mem_1_0__T_165_mask = 1'h0;
|
||||
assign data_mem_1_0__T_165_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
|
||||
assign data_mem_1_0__T_178_data = 71'h0;
|
||||
assign data_mem_1_0__T_178_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_0__T_178_mask = 1'h0;
|
||||
assign data_mem_1_0__T_178_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
|
||||
assign data_mem_1_1__T_145_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
|
||||
assign data_mem_1_1__T_145_data = data_mem_1_1[data_mem_1_1__T_145_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_1__T_158_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_1__T_158_data = data_mem_1_1[data_mem_1_1__T_158_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_1__T_171_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
|
||||
assign data_mem_1_1__T_171_data = data_mem_1_1[data_mem_1_1__T_171_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_1__T_184_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_1__T_184_data = data_mem_1_1[data_mem_1_1__T_184_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_1__T_139_data = 71'h0;
|
||||
assign data_mem_1_1__T_139_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
|
||||
assign data_mem_1_1__T_139_mask = 1'h0;
|
||||
assign data_mem_1_1__T_139_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
|
||||
assign data_mem_1_1__T_152_data = 71'h0;
|
||||
assign data_mem_1_1__T_152_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_1__T_152_mask = 1'h0;
|
||||
assign data_mem_1_1__T_152_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
|
||||
assign data_mem_1_1__T_165_data = 71'h0;
|
||||
assign data_mem_1_1__T_165_addr = _T_122 ? ic_rw_addr_q[11:3] : _T_127;
|
||||
assign data_mem_1_1__T_165_mask = 1'h0;
|
||||
assign data_mem_1_1__T_165_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
|
||||
assign data_mem_1_1__T_178_data = io_test_in;
|
||||
assign data_mem_1_1__T_178_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_1__T_178_mask = 1'h1;
|
||||
assign data_mem_1_1__T_178_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
|
||||
assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 194:17]
|
||||
assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 195:23]
|
||||
assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 196:16]
|
||||
assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 197:16]
|
||||
assign io_test = 1'h0; // @[el2_ifu_ic_mem.scala 198:11]
|
||||
assign io_test_port_0_0 = _T_139 ? 71'h0 : _GEN_3; // @[el2_ifu_ic_mem.scala 254:16]
|
||||
assign io_test_port_0_1 = _T_152 ? 71'h0 : _GEN_17; // @[el2_ifu_ic_mem.scala 254:16]
|
||||
assign io_test_port_1_0 = _T_165 ? 71'h0 : _GEN_31; // @[el2_ifu_ic_mem.scala 254:16]
|
||||
assign io_test_port_1_1 = _T_178 ? 71'h0 : _GEN_45; // @[el2_ifu_ic_mem.scala 254:16]
|
||||
assign io_test_port_0_0 = _T_137 ? 71'h0 : _GEN_3; // @[el2_ifu_ic_mem.scala 254:16]
|
||||
assign io_test_port_0_1 = _T_150 ? 71'h0 : _GEN_17; // @[el2_ifu_ic_mem.scala 254:16]
|
||||
assign io_test_port_1_0 = _T_163 ? 71'h0 : _GEN_31; // @[el2_ifu_ic_mem.scala 254:16]
|
||||
assign io_test_port_1_1 = _T_176 ? 71'h0 : _GEN_45; // @[el2_ifu_ic_mem.scala 254:16]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
|
|
@ -354,53 +354,53 @@ end // initial
|
|||
`endif
|
||||
`endif // SYNTHESIS
|
||||
always @(posedge clock) begin
|
||||
if(data_mem_0_0__T_141_en & data_mem_0_0__T_141_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_141_addr] <= data_mem_0_0__T_141_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
if(data_mem_0_0__T_139_en & data_mem_0_0__T_139_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_139_addr] <= data_mem_0_0__T_139_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_0_0__T_154_en & data_mem_0_0__T_154_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_154_addr] <= data_mem_0_0__T_154_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
if(data_mem_0_0__T_152_en & data_mem_0_0__T_152_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_152_addr] <= data_mem_0_0__T_152_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_0_0__T_167_en & data_mem_0_0__T_167_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_167_addr] <= data_mem_0_0__T_167_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
if(data_mem_0_0__T_165_en & data_mem_0_0__T_165_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_165_addr] <= data_mem_0_0__T_165_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_0_0__T_180_en & data_mem_0_0__T_180_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_180_addr] <= data_mem_0_0__T_180_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
if(data_mem_0_0__T_178_en & data_mem_0_0__T_178_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_178_addr] <= data_mem_0_0__T_178_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_0_1__T_141_en & data_mem_0_1__T_141_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_141_addr] <= data_mem_0_1__T_141_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
if(data_mem_0_1__T_139_en & data_mem_0_1__T_139_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_139_addr] <= data_mem_0_1__T_139_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_0_1__T_154_en & data_mem_0_1__T_154_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_154_addr] <= data_mem_0_1__T_154_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
if(data_mem_0_1__T_152_en & data_mem_0_1__T_152_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_152_addr] <= data_mem_0_1__T_152_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_0_1__T_167_en & data_mem_0_1__T_167_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_167_addr] <= data_mem_0_1__T_167_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
if(data_mem_0_1__T_165_en & data_mem_0_1__T_165_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_165_addr] <= data_mem_0_1__T_165_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_0_1__T_180_en & data_mem_0_1__T_180_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_180_addr] <= data_mem_0_1__T_180_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
if(data_mem_0_1__T_178_en & data_mem_0_1__T_178_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_178_addr] <= data_mem_0_1__T_178_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_1_0__T_141_en & data_mem_1_0__T_141_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_141_addr] <= data_mem_1_0__T_141_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
if(data_mem_1_0__T_139_en & data_mem_1_0__T_139_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_139_addr] <= data_mem_1_0__T_139_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_1_0__T_154_en & data_mem_1_0__T_154_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_154_addr] <= data_mem_1_0__T_154_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
if(data_mem_1_0__T_152_en & data_mem_1_0__T_152_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_152_addr] <= data_mem_1_0__T_152_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_1_0__T_167_en & data_mem_1_0__T_167_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_167_addr] <= data_mem_1_0__T_167_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
if(data_mem_1_0__T_165_en & data_mem_1_0__T_165_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_165_addr] <= data_mem_1_0__T_165_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_1_0__T_180_en & data_mem_1_0__T_180_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_180_addr] <= data_mem_1_0__T_180_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
if(data_mem_1_0__T_178_en & data_mem_1_0__T_178_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_178_addr] <= data_mem_1_0__T_178_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_1_1__T_141_en & data_mem_1_1__T_141_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_141_addr] <= data_mem_1_1__T_141_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
if(data_mem_1_1__T_139_en & data_mem_1_1__T_139_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_139_addr] <= data_mem_1_1__T_139_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_1_1__T_154_en & data_mem_1_1__T_154_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_154_addr] <= data_mem_1_1__T_154_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
if(data_mem_1_1__T_152_en & data_mem_1_1__T_152_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_152_addr] <= data_mem_1_1__T_152_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_1_1__T_167_en & data_mem_1_1__T_167_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_167_addr] <= data_mem_1_1__T_167_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
if(data_mem_1_1__T_165_en & data_mem_1_1__T_165_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_165_addr] <= data_mem_1_1__T_165_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_1_1__T_180_en & data_mem_1_1__T_180_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_180_addr] <= data_mem_1_1__T_180_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
if(data_mem_1_1__T_178_en & data_mem_1_1__T_178_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_178_addr] <= data_mem_1_1__T_178_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -200,7 +200,7 @@ class EL2_IC_DATA extends Module with el2_lib {
|
|||
val ic_debug_rd_way_en = Fill(ICACHE_NUM_WAYS, io.ic_debug_rd_en & !io.ic_debug_tag_array) & io.ic_debug_way
|
||||
val ic_debug_wr_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_wr_en & !io.ic_debug_tag_array) & io.ic_debug_way
|
||||
|
||||
val ic_bank_wr_data = WireInit(UInt(71.W), 0.U)
|
||||
val ic_bank_wr_data = Wire(Vec(ICACHE_BANKS_WAY,UInt(71.W)))
|
||||
val ic_rd_en_with_debug = WireInit(Bool(), 0.U)
|
||||
|
||||
val ic_rw_addr_q = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en).asBool, Cat(io.ic_debug_addr,0.U(2.W)), io.ic_rw_addr)
|
||||
|
|
@ -239,86 +239,39 @@ class EL2_IC_DATA extends Module with el2_lib {
|
|||
|
||||
//////////////////////////////////////////// Memory stated
|
||||
val (data_mem_word, tag_mem_word, ecc_offset) = DATA_MEM_LINE
|
||||
val wb_out = Wire(Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W))))
|
||||
val wb_dout = Wire(Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W))))
|
||||
val data_mem = Mem(ICACHE_DATA_DEPTH, Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W))))
|
||||
for(i<-0 until ICACHE_NUM_WAYS; k<-0 until ICACHE_BANKS_WAY){
|
||||
wb_out(i)(k) := 0.U
|
||||
wb_dout(i)(k) := 0.U
|
||||
val WE = if(ICACHE_WAYPACK) ic_b_sb_wren(k).orR else ic_b_sb_wren(k)(i)
|
||||
val ME = if(ICACHE_WAYPACK) ic_bank_way_clken(k).orR else ic_bank_way_clken(k)(i)
|
||||
when((ic_b_sb_wren(k)(i) & ic_bank_way_clken(k)(i)).asBool){
|
||||
data_mem(ic_rw_addr_bank_q(k))(k)(i) := io.test_in
|
||||
}.elsewhen((!ic_b_sb_wren(k)(i)&ic_bank_way_clken(k)(i)).asBool){
|
||||
wb_out(i)(k) := data_mem(ic_rw_addr_bank_q(k))(k)(i)
|
||||
wb_dout(i)(k) := data_mem(ic_rw_addr_bank_q(k))(k)(i)
|
||||
}
|
||||
}
|
||||
io.test_port := wb_out
|
||||
io.test_port := wb_dout
|
||||
val ic_rd_hit_q = Mux(ic_debug_rd_en_ff.asBool, ic_debug_rd_way_en_ff, io.ic_rd_hit)
|
||||
ic_bank_wr_data := (0 until ICACHE_BANKS_WAY).map(io.ic_wr_data(_))
|
||||
|
||||
// val ic_bank_way_clken = new Array[UInt](ICACHE_NUM_WAYS)
|
||||
// ic_bank_way_clken(0) = (repl(ICACHE_NUM_WAYS,ic_b_rden(0)) | io.clk_override | ic_b_sb_wren(0))
|
||||
// for(i<-1 until ICACHE_NUM_WAYS){
|
||||
// ic_bank_way_clken(i) = (repl(ICACHE_NUM_WAYS,ic_b_rden(0)) | io.clk_override | ic_b_sb_wren(i)) | ic_bank_way_clken(i-1)
|
||||
// }
|
||||
// // TODO: AS it is being used at only one place replace
|
||||
// val ic_rw_addr_q_inc = ic_rw_addr_q(ICACHE_TAG_LO-1,ICACHE_DATA_INDEX_LO) + 1.U
|
||||
// val ic_rw_addr_wrap = ic_rw_addr_q(ICACHE_BANK_HI) & (ic_rw_addr_q(2,1)===3.U) & ic_rd_en_with_debug & ~(io.ic_wr_en.orR)
|
||||
// // All flops rw-address
|
||||
// // rd-enable as it is a sync mem
|
||||
// val ic_rw_addr_ff = RegNext(ic_rw_addr_q, init = 0.U)
|
||||
// val ic_b_rden_ff = RegNext(ic_b_rden.reverse.reduce(Cat(_,_)), init = 0.U)
|
||||
// val ic_debug_rd_way_en_ff = RegNext(ic_debug_rd_way_en, init = 0.U)
|
||||
// val ic_debug_rd_en_ff = RegNext(io.ic_debug_rd_en, init = 0.U)
|
||||
// val ic_cacheline_wrap_ff = ic_rw_addr_ff(ICACHE_TAG_INDEX_LO-1,ICACHE_BANK_LO) === repl(ICACHE_TAG_INDEX_LO - ICACHE_BANK_LO, 1.U)
|
||||
//
|
||||
// val ic_rw_addr_bank_q = Wire(Vec(ICACHE_BANKS_WAY,UInt((ICACHE_INDEX_HI+1).W)))
|
||||
// ic_rw_addr_bank_q(0) := Mux(~ic_rw_addr_wrap.asBool, ic_rw_addr_q(ICACHE_INDEX_HI,ICACHE_DATA_INDEX_LO), Cat(ic_rw_addr_q(ICACHE_INDEX_HI, ICACHE_TAG_INDEX_LO), ic_rw_addr_q_inc(ICACHE_TAG_INDEX_LO-1, ICACHE_DATA_INDEX_LO)))
|
||||
// ic_rw_addr_bank_q(1) := ic_rw_addr_q(ICACHE_INDEX_HI, ICACHE_DATA_INDEX_LO)
|
||||
// val (data_mem_word, tag_mem_word, ecc_offset) = DATA_MEM_LINE
|
||||
// // Making a memory with Location=ICACHE_DATA_DEPTH banks and ways
|
||||
// val data_mem = SyncReadMem(ICACHE_DATA_DEPTH, Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W))))
|
||||
// data_mem(ic_rw_addr_bank_q(0)(ICACHE_INDEX_HI,ICACHE_DATA_INDEX_LO))(0)(0):= ic_sb_wr_data(0)
|
||||
// val wb_dout = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_BANKS_WAY, UInt(data_mem_word.W))))
|
||||
// // Initializing the wire
|
||||
// wb_dout.indices.foreach { i => wb_dout(i).indices.foreach{ j=>
|
||||
// wb_dout(i)(j) := 0.U
|
||||
// when(ic_sb_wr_data(i)(j) & ic_bank_way_clken(i)(j)){
|
||||
// data_mem(ic_rw_addr_bank_q(j)(ICACHE_INDEX_HI,ICACHE_DATA_INDEX_LO))(j)(i) := ic_sb_wr_data(j)
|
||||
// }
|
||||
// wb_dout(i)(j) := data_mem(ic_rw_addr_bank_q(j)(ICACHE_INDEX_HI,ICACHE_DATA_INDEX_LO))(i)(j)
|
||||
// }
|
||||
// }
|
||||
// val wb_dout_way_pre_lower = (0 until ICACHE_NUM_WAYS).map(i=>
|
||||
// (0 until ICACHE_BANKS_WAY).map(j=>
|
||||
// repl(data_mem_word,ic_rw_addr_ff(ICACHE_BANK_HI, ICACHE_BANK_LO)===j.U)&wb_dout(i)(j)).reduce(_|_))
|
||||
//
|
||||
// val wb_dout_way_pre_upper = (0 until ICACHE_NUM_WAYS).map(i=>
|
||||
// (0 until ICACHE_BANKS_WAY).map(j=>
|
||||
// repl(data_mem_word,ic_rw_addr_ff(ICACHE_BANK_HI, ICACHE_BANK_LO)===j.U-1.U)&wb_dout(i)(j)).reduce(_|_))
|
||||
//
|
||||
// val wb_dout_way_pre = (0 until ICACHE_NUM_WAYS).map(i=>Cat(wb_dout_way_pre_upper(i),wb_dout_way_pre_lower(i)))
|
||||
//
|
||||
// // TODO: Put an assertion here
|
||||
// val wb_dout_way = (0 until ICACHE_NUM_WAYS).map(i=>
|
||||
// repl(64 ,ic_rw_addr_ff(2,1)===0.U) & wb_dout_way_pre(i)(63,0) |
|
||||
// repl(64 ,ic_rw_addr_ff(2,1)===1.U) & Cat(wb_dout_way_pre(i)(ecc_offset+15,ecc_offset),wb_dout_way_pre(i)(63,16)) |
|
||||
// repl(64 ,ic_rw_addr_ff(2,1)===2.U) & Cat(wb_dout_way_pre(i)(ecc_offset+31,ecc_offset),wb_dout_way_pre(i)(63,32)) |
|
||||
// repl(64 ,ic_rw_addr_ff(2,1)===3.U) & Cat(wb_dout_way_pre(i)(ecc_offset+47,ecc_offset),wb_dout_way_pre(i)(63,48))
|
||||
// )
|
||||
// // ic_rw_addr_ff(ICACHE_BANK_HI,ICACHE_BANK_LO)===1.U -> wb_dout(1)(0)))
|
||||
// val ic_rd_hit_q = Mux(ic_debug_rd_en_ff===1.U, ic_debug_rd_way_en_ff, io.ic_rd_hit) ;
|
||||
// val wb_dout_way_with_premux = wb_dout_way.map(Mux(io.ic_sel_premux_data, io.ic_premux_data, _))
|
||||
//
|
||||
// io.ic_debug_rd_data := 0.U
|
||||
// io.ic_parerr := 0.U
|
||||
// io.ic_eccerr := 0.U
|
||||
//
|
||||
// io.ic_rd_data := Mux1H_LM((0 until ICACHE_NUM_WAYS).map(i => ic_rd_hit_q(i) | io.ic_sel_premux_data),
|
||||
// (0 until ICACHE_NUM_WAYS).map(wb_dout_way_with_premux(_)))
|
||||
// io.ic_debug_rd_data := Mux1H_LM((0 until ICACHE_NUM_WAYS).map(i => ic_rd_hit_q(i)),
|
||||
// (0 until ICACHE_NUM_WAYS).map(wb_dout_way_pre(_)(data_mem_word-1,0)))
|
||||
// val wb_dout_ecc = Mux1H_LM((0 until ICACHE_NUM_WAYS).map(i => ic_rd_hit_q(i)),
|
||||
// (0 until ICACHE_NUM_WAYS).map(wb_dout_way_pre(_)))
|
||||
// io.test_port2 := 0.U//inter2//wb_dout_way_pre
|
||||
// io.test_port := wb_dout
|
||||
val wb_dout_way_pre = (0 until ICACHE_BANKS_WAY).map(i=>Cat(
|
||||
Mux1H((0 until ICACHE_BANKS_WAY).map(j=>(ic_rw_addr_ff(ICACHE_BANK_HI-1, ICACHE_BANK_LO-1)===j.U).asBool->wb_dout(i)(j))),
|
||||
Mux1H((0 until ICACHE_BANKS_WAY).map(j=>(ic_rw_addr_ff(ICACHE_BANK_HI-1, ICACHE_BANK_LO-1)===(j.U-1.U)).asBool->wb_dout(i)(j)))))
|
||||
|
||||
val wb_dout_way = (0 until ICACHE_NUM_WAYS).map(i=>Mux1H(Seq((ic_rw_addr_ff(1,0)===0.U).asBool->wb_dout_way_pre(i)(63,0),
|
||||
(ic_rw_addr_ff(1,0)===1.U).asBool->Cat(wb_dout_way_pre(i)(86,71),wb_dout_way_pre(i)(63,16)),
|
||||
(ic_rw_addr_ff(1,0)===2.U).asBool->Cat(wb_dout_way_pre(i)(102,71),wb_dout_way_pre(i)(63,32)),
|
||||
(ic_rw_addr_ff(1,0)===3.U).asBool->Cat(wb_dout_way_pre(i)(119,71),wb_dout_way_pre(i)(63,48)))))
|
||||
|
||||
val wb_dout_way_with_premux = (0 until ICACHE_NUM_WAYS).map(i=>Mux(io.ic_sel_premux_data.asBool,io.ic_premux_data, wb_dout_way(i)))
|
||||
|
||||
val ic_rd_data = Mux1H((0 until ICACHE_NUM_WAYS).map(i=>(ic_rd_hit_q(i) | io.ic_sel_premux_data).asBool->wb_dout_way_with_premux(i)))
|
||||
val ic_debug_rd_data = Mux1H((0 until ICACHE_NUM_WAYS).map(i=>ic_rd_hit_q(i).asBool->wb_dout_way_pre(i)(70,0)))
|
||||
val wb_dout_ecc = Mux1H((0 until ICACHE_NUM_WAYS).map(i=>ic_rd_hit_q(i).asBool->wb_dout_way_pre(i)))
|
||||
|
||||
val bank_check_en = for(i<-0 until ICACHE_BANKS_WAY) yield(io.ic_rd_hit.orR & ((i.U==0.U).asBool | (!ic_cacheline_wrap_ff & (ic_b_rden_ff(ICACHE_BANKS_WAY-1,0) === Fill(ICACHE_BANKS_WAY,1.U)))))
|
||||
// val wb_dout_ecc_bank = (0 until ICACHE_BANKS_WAY).map(i=> wb_dout_ecc((71*i)+70,71*i)))
|
||||
}
|
||||
|
||||
object ifu_ic extends App {
|
||||
|
|
|
|||
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Reference in New Issue