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IMC DONE

This commit is contained in:
waleed-lm 2020-10-27 12:11:18 +05:00
parent 95dbb7b698
commit d5ab690a55
4 changed files with 123 additions and 123 deletions
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160
el2_ifu_mem_ctl.fir
View File

@ -7337,89 +7337,89 @@ circuit el2_ifu_mem_ctl :
node ic_valid_w_debug = mux(_T_5167, _T_5168, ic_valid) @[el2_ifu_mem_ctl.scala 736:31] node ic_valid_w_debug = mux(_T_5167, _T_5168, ic_valid) @[el2_ifu_mem_ctl.scala 736:31]
reg ic_valid_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 738:14] reg ic_valid_ff : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 738:14]
ic_valid_ff <= ic_valid_w_debug @[el2_ifu_mem_ctl.scala 738:14] ic_valid_ff <= ic_valid_w_debug @[el2_ifu_mem_ctl.scala 738:14]
node _T_5169 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 742:35] node _T_5169 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 742:35]
node _T_5170 = eq(_T_5169, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 742:82] node _T_5170 = eq(_T_5169, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 742:78]
node _T_5171 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:108] node _T_5171 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:104]
node _T_5172 = and(_T_5170, _T_5171) @[el2_ifu_mem_ctl.scala 742:91] node _T_5172 = and(_T_5170, _T_5171) @[el2_ifu_mem_ctl.scala 742:87]
node _T_5173 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 743:27] node _T_5173 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 743:27]
node _T_5174 = eq(_T_5173, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 743:74] node _T_5174 = eq(_T_5173, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 743:70]
node _T_5175 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 743:101] node _T_5175 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 743:97]
node _T_5176 = and(_T_5174, _T_5175) @[el2_ifu_mem_ctl.scala 743:83] node _T_5176 = and(_T_5174, _T_5175) @[el2_ifu_mem_ctl.scala 743:79]
node _T_5177 = or(_T_5172, _T_5176) @[el2_ifu_mem_ctl.scala 742:113] node _T_5177 = or(_T_5172, _T_5176) @[el2_ifu_mem_ctl.scala 742:109]
node _T_5178 = or(_T_5177, reset_all_tags) @[el2_ifu_mem_ctl.scala 743:106] node _T_5178 = or(_T_5177, reset_all_tags) @[el2_ifu_mem_ctl.scala 743:102]
node _T_5179 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 742:35] node _T_5179 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 742:35]
node _T_5180 = eq(_T_5179, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 742:82] node _T_5180 = eq(_T_5179, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 742:78]
node _T_5181 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:108] node _T_5181 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:104]
node _T_5182 = and(_T_5180, _T_5181) @[el2_ifu_mem_ctl.scala 742:91] node _T_5182 = and(_T_5180, _T_5181) @[el2_ifu_mem_ctl.scala 742:87]
node _T_5183 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 743:27] node _T_5183 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 743:27]
node _T_5184 = eq(_T_5183, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 743:74] node _T_5184 = eq(_T_5183, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 743:70]
node _T_5185 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 743:101] node _T_5185 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 743:97]
node _T_5186 = and(_T_5184, _T_5185) @[el2_ifu_mem_ctl.scala 743:83] node _T_5186 = and(_T_5184, _T_5185) @[el2_ifu_mem_ctl.scala 743:79]
node _T_5187 = or(_T_5182, _T_5186) @[el2_ifu_mem_ctl.scala 742:113] node _T_5187 = or(_T_5182, _T_5186) @[el2_ifu_mem_ctl.scala 742:109]
node _T_5188 = or(_T_5187, reset_all_tags) @[el2_ifu_mem_ctl.scala 743:106] node _T_5188 = or(_T_5187, reset_all_tags) @[el2_ifu_mem_ctl.scala 743:102]
node tag_valid_clken_0 = cat(_T_5188, _T_5178) @[Cat.scala 29:58] node tag_valid_clken_0 = cat(_T_5188, _T_5178) @[Cat.scala 29:58]
node _T_5189 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 742:35] node _T_5189 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 742:35]
node _T_5190 = eq(_T_5189, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 742:82] node _T_5190 = eq(_T_5189, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 742:78]
node _T_5191 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:108] node _T_5191 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:104]
node _T_5192 = and(_T_5190, _T_5191) @[el2_ifu_mem_ctl.scala 742:91] node _T_5192 = and(_T_5190, _T_5191) @[el2_ifu_mem_ctl.scala 742:87]
node _T_5193 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 743:27] node _T_5193 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 743:27]
node _T_5194 = eq(_T_5193, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 743:74] node _T_5194 = eq(_T_5193, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 743:70]
node _T_5195 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 743:101] node _T_5195 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 743:97]
node _T_5196 = and(_T_5194, _T_5195) @[el2_ifu_mem_ctl.scala 743:83] node _T_5196 = and(_T_5194, _T_5195) @[el2_ifu_mem_ctl.scala 743:79]
node _T_5197 = or(_T_5192, _T_5196) @[el2_ifu_mem_ctl.scala 742:113] node _T_5197 = or(_T_5192, _T_5196) @[el2_ifu_mem_ctl.scala 742:109]
node _T_5198 = or(_T_5197, reset_all_tags) @[el2_ifu_mem_ctl.scala 743:106] node _T_5198 = or(_T_5197, reset_all_tags) @[el2_ifu_mem_ctl.scala 743:102]
node _T_5199 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 742:35] node _T_5199 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 742:35]
node _T_5200 = eq(_T_5199, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 742:82] node _T_5200 = eq(_T_5199, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 742:78]
node _T_5201 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:108] node _T_5201 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:104]
node _T_5202 = and(_T_5200, _T_5201) @[el2_ifu_mem_ctl.scala 742:91] node _T_5202 = and(_T_5200, _T_5201) @[el2_ifu_mem_ctl.scala 742:87]
node _T_5203 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 743:27] node _T_5203 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 743:27]
node _T_5204 = eq(_T_5203, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 743:74] node _T_5204 = eq(_T_5203, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 743:70]
node _T_5205 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 743:101] node _T_5205 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 743:97]
node _T_5206 = and(_T_5204, _T_5205) @[el2_ifu_mem_ctl.scala 743:83] node _T_5206 = and(_T_5204, _T_5205) @[el2_ifu_mem_ctl.scala 743:79]
node _T_5207 = or(_T_5202, _T_5206) @[el2_ifu_mem_ctl.scala 742:113] node _T_5207 = or(_T_5202, _T_5206) @[el2_ifu_mem_ctl.scala 742:109]
node _T_5208 = or(_T_5207, reset_all_tags) @[el2_ifu_mem_ctl.scala 743:106] node _T_5208 = or(_T_5207, reset_all_tags) @[el2_ifu_mem_ctl.scala 743:102]
node tag_valid_clken_1 = cat(_T_5208, _T_5198) @[Cat.scala 29:58] node tag_valid_clken_1 = cat(_T_5208, _T_5198) @[Cat.scala 29:58]
node _T_5209 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 742:35] node _T_5209 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 742:35]
node _T_5210 = eq(_T_5209, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 742:82] node _T_5210 = eq(_T_5209, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 742:78]
node _T_5211 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:108] node _T_5211 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:104]
node _T_5212 = and(_T_5210, _T_5211) @[el2_ifu_mem_ctl.scala 742:91] node _T_5212 = and(_T_5210, _T_5211) @[el2_ifu_mem_ctl.scala 742:87]
node _T_5213 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 743:27] node _T_5213 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 743:27]
node _T_5214 = eq(_T_5213, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 743:74] node _T_5214 = eq(_T_5213, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 743:70]
node _T_5215 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 743:101] node _T_5215 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 743:97]
node _T_5216 = and(_T_5214, _T_5215) @[el2_ifu_mem_ctl.scala 743:83] node _T_5216 = and(_T_5214, _T_5215) @[el2_ifu_mem_ctl.scala 743:79]
node _T_5217 = or(_T_5212, _T_5216) @[el2_ifu_mem_ctl.scala 742:113] node _T_5217 = or(_T_5212, _T_5216) @[el2_ifu_mem_ctl.scala 742:109]
node _T_5218 = or(_T_5217, reset_all_tags) @[el2_ifu_mem_ctl.scala 743:106] node _T_5218 = or(_T_5217, reset_all_tags) @[el2_ifu_mem_ctl.scala 743:102]
node _T_5219 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 742:35] node _T_5219 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 742:35]
node _T_5220 = eq(_T_5219, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 742:82] node _T_5220 = eq(_T_5219, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 742:78]
node _T_5221 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:108] node _T_5221 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:104]
node _T_5222 = and(_T_5220, _T_5221) @[el2_ifu_mem_ctl.scala 742:91] node _T_5222 = and(_T_5220, _T_5221) @[el2_ifu_mem_ctl.scala 742:87]
node _T_5223 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 743:27] node _T_5223 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 743:27]
node _T_5224 = eq(_T_5223, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 743:74] node _T_5224 = eq(_T_5223, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 743:70]
node _T_5225 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 743:101] node _T_5225 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 743:97]
node _T_5226 = and(_T_5224, _T_5225) @[el2_ifu_mem_ctl.scala 743:83] node _T_5226 = and(_T_5224, _T_5225) @[el2_ifu_mem_ctl.scala 743:79]
node _T_5227 = or(_T_5222, _T_5226) @[el2_ifu_mem_ctl.scala 742:113] node _T_5227 = or(_T_5222, _T_5226) @[el2_ifu_mem_ctl.scala 742:109]
node _T_5228 = or(_T_5227, reset_all_tags) @[el2_ifu_mem_ctl.scala 743:106] node _T_5228 = or(_T_5227, reset_all_tags) @[el2_ifu_mem_ctl.scala 743:102]
node tag_valid_clken_2 = cat(_T_5228, _T_5218) @[Cat.scala 29:58] node tag_valid_clken_2 = cat(_T_5228, _T_5218) @[Cat.scala 29:58]
node _T_5229 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 742:35] node _T_5229 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 742:35]
node _T_5230 = eq(_T_5229, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 742:82] node _T_5230 = eq(_T_5229, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 742:78]
node _T_5231 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:108] node _T_5231 = bits(ifu_tag_wren_ff, 0, 0) @[el2_ifu_mem_ctl.scala 742:104]
node _T_5232 = and(_T_5230, _T_5231) @[el2_ifu_mem_ctl.scala 742:91] node _T_5232 = and(_T_5230, _T_5231) @[el2_ifu_mem_ctl.scala 742:87]
node _T_5233 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 743:27] node _T_5233 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 743:27]
node _T_5234 = eq(_T_5233, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 743:74] node _T_5234 = eq(_T_5233, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 743:70]
node _T_5235 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 743:101] node _T_5235 = bits(perr_err_inv_way, 0, 0) @[el2_ifu_mem_ctl.scala 743:97]
node _T_5236 = and(_T_5234, _T_5235) @[el2_ifu_mem_ctl.scala 743:83] node _T_5236 = and(_T_5234, _T_5235) @[el2_ifu_mem_ctl.scala 743:79]
node _T_5237 = or(_T_5232, _T_5236) @[el2_ifu_mem_ctl.scala 742:113] node _T_5237 = or(_T_5232, _T_5236) @[el2_ifu_mem_ctl.scala 742:109]
node _T_5238 = or(_T_5237, reset_all_tags) @[el2_ifu_mem_ctl.scala 743:106] node _T_5238 = or(_T_5237, reset_all_tags) @[el2_ifu_mem_ctl.scala 743:102]
node _T_5239 = bits(ifu_ic_rw_int_addr_ff, 5, 4) @[el2_ifu_mem_ctl.scala 742:35] node _T_5239 = bits(ifu_ic_rw_int_addr_ff, 6, 5) @[el2_ifu_mem_ctl.scala 742:35]
node _T_5240 = eq(_T_5239, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 742:82] node _T_5240 = eq(_T_5239, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 742:78]
node _T_5241 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:108] node _T_5241 = bits(ifu_tag_wren_ff, 1, 1) @[el2_ifu_mem_ctl.scala 742:104]
node _T_5242 = and(_T_5240, _T_5241) @[el2_ifu_mem_ctl.scala 742:91] node _T_5242 = and(_T_5240, _T_5241) @[el2_ifu_mem_ctl.scala 742:87]
node _T_5243 = bits(perr_ic_index_ff, 5, 4) @[el2_ifu_mem_ctl.scala 743:27] node _T_5243 = bits(perr_ic_index_ff, 6, 5) @[el2_ifu_mem_ctl.scala 743:27]
node _T_5244 = eq(_T_5243, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 743:74] node _T_5244 = eq(_T_5243, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 743:70]
node _T_5245 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 743:101] node _T_5245 = bits(perr_err_inv_way, 1, 1) @[el2_ifu_mem_ctl.scala 743:97]
node _T_5246 = and(_T_5244, _T_5245) @[el2_ifu_mem_ctl.scala 743:83] node _T_5246 = and(_T_5244, _T_5245) @[el2_ifu_mem_ctl.scala 743:79]
node _T_5247 = or(_T_5242, _T_5246) @[el2_ifu_mem_ctl.scala 742:113] node _T_5247 = or(_T_5242, _T_5246) @[el2_ifu_mem_ctl.scala 742:109]
node _T_5248 = or(_T_5247, reset_all_tags) @[el2_ifu_mem_ctl.scala 743:106] node _T_5248 = or(_T_5247, reset_all_tags) @[el2_ifu_mem_ctl.scala 743:102]
node tag_valid_clken_3 = cat(_T_5248, _T_5238) @[Cat.scala 29:58] node tag_valid_clken_3 = cat(_T_5248, _T_5238) @[Cat.scala 29:58]
wire ic_tag_valid_out : UInt<1>[128][2] @[el2_ifu_mem_ctl.scala 746:32] wire ic_tag_valid_out : UInt<1>[128][2] @[el2_ifu_mem_ctl.scala 746:32]
node _T_5249 = cat(ic_tag_valid_out[1][127], ic_tag_valid_out[1][126]) @[Cat.scala 29:58] node _T_5249 = cat(ic_tag_valid_out[1][127], ic_tag_valid_out[1][126]) @[Cat.scala 29:58]

80
el2_ifu_mem_ctl.v
View File

@ -3775,49 +3775,49 @@ module el2_ifu_mem_ctl(
wire [1:0] ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en; // @[el2_ifu_mem_ctl.scala 732:45] wire [1:0] ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en; // @[el2_ifu_mem_ctl.scala 732:45]
reg [1:0] ifu_tag_wren_ff; // @[el2_ifu_mem_ctl.scala 734:14] reg [1:0] ifu_tag_wren_ff; // @[el2_ifu_mem_ctl.scala 734:14]
reg ic_valid_ff; // @[el2_ifu_mem_ctl.scala 738:14] reg ic_valid_ff; // @[el2_ifu_mem_ctl.scala 738:14]
wire _T_5170 = ifu_ic_rw_int_addr_ff[5:4] == 2'h0; // @[el2_ifu_mem_ctl.scala 742:82] wire _T_5170 = ifu_ic_rw_int_addr_ff[6:5] == 2'h0; // @[el2_ifu_mem_ctl.scala 742:78]
wire _T_5172 = _T_5170 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:91] wire _T_5172 = _T_5170 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:87]
wire _T_5174 = perr_ic_index_ff[5:4] == 2'h0; // @[el2_ifu_mem_ctl.scala 743:74] wire _T_5174 = perr_ic_index_ff[6:5] == 2'h0; // @[el2_ifu_mem_ctl.scala 743:70]
wire _T_5176 = _T_5174 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 743:83] wire _T_5176 = _T_5174 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 743:79]
wire _T_5177 = _T_5172 | _T_5176; // @[el2_ifu_mem_ctl.scala 742:113] wire _T_5177 = _T_5172 | _T_5176; // @[el2_ifu_mem_ctl.scala 742:109]
wire _T_5178 = _T_5177 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 743:106] wire _T_5178 = _T_5177 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 743:102]
wire _T_5182 = _T_5170 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:91] wire _T_5182 = _T_5170 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:87]
wire _T_5186 = _T_5174 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 743:83] wire _T_5186 = _T_5174 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 743:79]
wire _T_5187 = _T_5182 | _T_5186; // @[el2_ifu_mem_ctl.scala 742:113] wire _T_5187 = _T_5182 | _T_5186; // @[el2_ifu_mem_ctl.scala 742:109]
wire _T_5188 = _T_5187 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 743:106] wire _T_5188 = _T_5187 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 743:102]
wire [1:0] tag_valid_clken_0 = {_T_5188,_T_5178}; // @[Cat.scala 29:58] wire [1:0] tag_valid_clken_0 = {_T_5188,_T_5178}; // @[Cat.scala 29:58]
wire _T_5190 = ifu_ic_rw_int_addr_ff[5:4] == 2'h1; // @[el2_ifu_mem_ctl.scala 742:82] wire _T_5190 = ifu_ic_rw_int_addr_ff[6:5] == 2'h1; // @[el2_ifu_mem_ctl.scala 742:78]
wire _T_5192 = _T_5190 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:91] wire _T_5192 = _T_5190 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:87]
wire _T_5194 = perr_ic_index_ff[5:4] == 2'h1; // @[el2_ifu_mem_ctl.scala 743:74] wire _T_5194 = perr_ic_index_ff[6:5] == 2'h1; // @[el2_ifu_mem_ctl.scala 743:70]
wire _T_5196 = _T_5194 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 743:83] wire _T_5196 = _T_5194 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 743:79]
wire _T_5197 = _T_5192 | _T_5196; // @[el2_ifu_mem_ctl.scala 742:113] wire _T_5197 = _T_5192 | _T_5196; // @[el2_ifu_mem_ctl.scala 742:109]
wire _T_5198 = _T_5197 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 743:106] wire _T_5198 = _T_5197 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 743:102]
wire _T_5202 = _T_5190 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:91] wire _T_5202 = _T_5190 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:87]
wire _T_5206 = _T_5194 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 743:83] wire _T_5206 = _T_5194 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 743:79]
wire _T_5207 = _T_5202 | _T_5206; // @[el2_ifu_mem_ctl.scala 742:113] wire _T_5207 = _T_5202 | _T_5206; // @[el2_ifu_mem_ctl.scala 742:109]
wire _T_5208 = _T_5207 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 743:106] wire _T_5208 = _T_5207 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 743:102]
wire [1:0] tag_valid_clken_1 = {_T_5208,_T_5198}; // @[Cat.scala 29:58] wire [1:0] tag_valid_clken_1 = {_T_5208,_T_5198}; // @[Cat.scala 29:58]
wire _T_5210 = ifu_ic_rw_int_addr_ff[5:4] == 2'h2; // @[el2_ifu_mem_ctl.scala 742:82] wire _T_5210 = ifu_ic_rw_int_addr_ff[6:5] == 2'h2; // @[el2_ifu_mem_ctl.scala 742:78]
wire _T_5212 = _T_5210 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:91] wire _T_5212 = _T_5210 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:87]
wire _T_5214 = perr_ic_index_ff[5:4] == 2'h2; // @[el2_ifu_mem_ctl.scala 743:74] wire _T_5214 = perr_ic_index_ff[6:5] == 2'h2; // @[el2_ifu_mem_ctl.scala 743:70]
wire _T_5216 = _T_5214 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 743:83] wire _T_5216 = _T_5214 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 743:79]
wire _T_5217 = _T_5212 | _T_5216; // @[el2_ifu_mem_ctl.scala 742:113] wire _T_5217 = _T_5212 | _T_5216; // @[el2_ifu_mem_ctl.scala 742:109]
wire _T_5218 = _T_5217 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 743:106] wire _T_5218 = _T_5217 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 743:102]
wire _T_5222 = _T_5210 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:91] wire _T_5222 = _T_5210 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:87]
wire _T_5226 = _T_5214 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 743:83] wire _T_5226 = _T_5214 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 743:79]
wire _T_5227 = _T_5222 | _T_5226; // @[el2_ifu_mem_ctl.scala 742:113] wire _T_5227 = _T_5222 | _T_5226; // @[el2_ifu_mem_ctl.scala 742:109]
wire _T_5228 = _T_5227 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 743:106] wire _T_5228 = _T_5227 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 743:102]
wire [1:0] tag_valid_clken_2 = {_T_5228,_T_5218}; // @[Cat.scala 29:58] wire [1:0] tag_valid_clken_2 = {_T_5228,_T_5218}; // @[Cat.scala 29:58]
wire _T_5230 = ifu_ic_rw_int_addr_ff[5:4] == 2'h3; // @[el2_ifu_mem_ctl.scala 742:82] wire _T_5230 = ifu_ic_rw_int_addr_ff[6:5] == 2'h3; // @[el2_ifu_mem_ctl.scala 742:78]
wire _T_5232 = _T_5230 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:91] wire _T_5232 = _T_5230 & ifu_tag_wren_ff[0]; // @[el2_ifu_mem_ctl.scala 742:87]
wire _T_5234 = perr_ic_index_ff[5:4] == 2'h3; // @[el2_ifu_mem_ctl.scala 743:74] wire _T_5234 = perr_ic_index_ff[6:5] == 2'h3; // @[el2_ifu_mem_ctl.scala 743:70]
wire _T_5236 = _T_5234 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 743:83] wire _T_5236 = _T_5234 & perr_err_inv_way[0]; // @[el2_ifu_mem_ctl.scala 743:79]
wire _T_5237 = _T_5232 | _T_5236; // @[el2_ifu_mem_ctl.scala 742:113] wire _T_5237 = _T_5232 | _T_5236; // @[el2_ifu_mem_ctl.scala 742:109]
wire _T_5238 = _T_5237 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 743:106] wire _T_5238 = _T_5237 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 743:102]
wire _T_5242 = _T_5230 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:91] wire _T_5242 = _T_5230 & ifu_tag_wren_ff[1]; // @[el2_ifu_mem_ctl.scala 742:87]
wire _T_5246 = _T_5234 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 743:83] wire _T_5246 = _T_5234 & perr_err_inv_way[1]; // @[el2_ifu_mem_ctl.scala 743:79]
wire _T_5247 = _T_5242 | _T_5246; // @[el2_ifu_mem_ctl.scala 742:113] wire _T_5247 = _T_5242 | _T_5246; // @[el2_ifu_mem_ctl.scala 742:109]
wire _T_5248 = _T_5247 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 743:106] wire _T_5248 = _T_5247 | reset_all_tags; // @[el2_ifu_mem_ctl.scala 743:102]
wire [1:0] tag_valid_clken_3 = {_T_5248,_T_5238}; // @[Cat.scala 29:58] wire [1:0] tag_valid_clken_3 = {_T_5248,_T_5238}; // @[Cat.scala 29:58]
wire [9:0] _T_5257 = {ic_tag_valid_out_1_127,ic_tag_valid_out_1_126,ic_tag_valid_out_1_125,ic_tag_valid_out_1_124,ic_tag_valid_out_1_123,ic_tag_valid_out_1_122,ic_tag_valid_out_1_121,ic_tag_valid_out_1_120,ic_tag_valid_out_1_119,ic_tag_valid_out_1_118}; // @[Cat.scala 29:58] wire [9:0] _T_5257 = {ic_tag_valid_out_1_127,ic_tag_valid_out_1_126,ic_tag_valid_out_1_125,ic_tag_valid_out_1_124,ic_tag_valid_out_1_123,ic_tag_valid_out_1_122,ic_tag_valid_out_1_121,ic_tag_valid_out_1_120,ic_tag_valid_out_1_119,ic_tag_valid_out_1_118}; // @[Cat.scala 29:58]
wire [18:0] _T_5266 = {_T_5257,ic_tag_valid_out_1_117,ic_tag_valid_out_1_116,ic_tag_valid_out_1_115,ic_tag_valid_out_1_114,ic_tag_valid_out_1_113,ic_tag_valid_out_1_112,ic_tag_valid_out_1_111,ic_tag_valid_out_1_110,ic_tag_valid_out_1_109}; // @[Cat.scala 29:58] wire [18:0] _T_5266 = {_T_5257,ic_tag_valid_out_1_117,ic_tag_valid_out_1_116,ic_tag_valid_out_1_115,ic_tag_valid_out_1_114,ic_tag_valid_out_1_113,ic_tag_valid_out_1_112,ic_tag_valid_out_1_111,ic_tag_valid_out_1_110,ic_tag_valid_out_1_109}; // @[Cat.scala 29:58]

6
src/main/scala/ifu/el2_ifu_mem_ctl.scala
View File

@ -737,10 +737,10 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
val ic_valid_ff = withClock(io.free_clk) { val ic_valid_ff = withClock(io.free_clk) {
RegNext(ic_valid_w_debug, false.B) RegNext(ic_valid_w_debug, false.B)
} }
val tag_valid_clken = (0 until ICACHE_TAG_DEPTH / 32).map(i => (0 until ICACHE_NUM_WAYS).map(j => val tag_valid_clken = (0 until (ICACHE_TAG_DEPTH / 32)).map(i => (0 until ICACHE_NUM_WAYS).map(j =>
if (ICACHE_TAG_DEPTH == 32) (ifu_tag_wren_ff(j) | perr_err_inv_way(j) | reset_all_tags) if (ICACHE_TAG_DEPTH == 32) (ifu_tag_wren_ff(j) | perr_err_inv_way(j) | reset_all_tags)
else ((ifu_ic_rw_int_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO - 1, 4) === i.U) & ifu_tag_wren_ff(j)) | else ((ifu_ic_rw_int_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & ifu_tag_wren_ff(j)) |
((perr_ic_index_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO - 1, 4) === i.U) & perr_err_inv_way(j)) | ((perr_ic_index_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & perr_err_inv_way(j)) |
reset_all_tags).reverse.reduce(Cat(_, _))) reset_all_tags).reverse.reduce(Cat(_, _)))
// val tag_valid_clk = (0 until ICACHE_TAG_DEPTH / 32).map(i => (0 until ICACHE_NUM_WAYS).map(j => rvclkhdr(clock, tag_valid_clken(i)(j), io.scan_mode))) // val tag_valid_clk = (0 until ICACHE_TAG_DEPTH / 32).map(i => (0 until ICACHE_NUM_WAYS).map(j => rvclkhdr(clock, tag_valid_clken(i)(j), io.scan_mode)))
val ic_tag_valid_out = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_TAG_DEPTH, Bool()))) val ic_tag_valid_out = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_TAG_DEPTH, Bool())))

BIN
target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class
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