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Split RAM and ROM to 8 banks.

This commit is contained in:
colin 2022-03-23 14:33:06 +00:00
parent fd6791eb26
commit d61bc07515
3 changed files with 572 additions and 459 deletions
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5
demo/soc.lpf
View File

@ -26,7 +26,8 @@ LOCATE COMP "jtag_trst_n" SITE "M3";
IOBUF PORT "jtag_trst_n" IO_TYPE=LVCMOS33; IOBUF PORT "jtag_trst_n" IO_TYPE=LVCMOS33;
FREQUENCY PORT "jtag_trst_n" 25 MHZ; FREQUENCY PORT "jtag_trst_n" 25 MHZ;
LOCATE COMP "jtag_tdo" SITE "M4"; LOCATE COMP "jtag_tdo" SITE "M4";
IOBUF PORT "jtag_tdo" IO_TYPE=LVCMOS33; IOBUF PORT "jtag_tdo" IO_TYPE=LVCMOS33;
LOCATE COMP "clk_o" SITE "A3";
IOBUF PORT "clk_o" IO_TYPE=LVCMOS33;

300
soc/ahb_sif.sv
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@ -15,114 +15,224 @@
// //
module axi_slv #( module axi_slv #(
TAGW = 1 TAGW = 1
) ( ) (
input aclk, input aclk,
input rst_l, input rst_l,
input arvalid, input arvalid,
output reg arready, output reg arready,
input [ 31:0] araddr, input [ 31:0] araddr,
input [TAGW-1:0] arid, input [TAGW-1:0] arid,
input [ 7:0] arlen, input [ 7:0] arlen,
input [ 1:0] arburst, input [ 1:0] arburst,
input [ 2:0] arsize, input [ 2:0] arsize,
output reg rvalid, output reg rvalid,
input rready, input rready,
output reg [ 63:0] rdata, output reg [ 63:0] rdata,
output reg [ 1:0] rresp, output reg [ 1:0] rresp,
output reg [TAGW-1:0] rid, output reg [TAGW-1:0] rid,
output rlast, output rlast,
input awvalid, input awvalid,
output awready, output awready,
input [ 31:0] awaddr, input [ 31:0] awaddr,
input [TAGW-1:0] awid, input [TAGW-1:0] awid,
input [ 7:0] awlen, input [ 7:0] awlen,
input [ 1:0] awburst, input [ 1:0] awburst,
input [ 2:0] awsize, input [ 2:0] awsize,
input [63:0] wdata, input [63:0] wdata,
input [ 7:0] wstrb, input [ 7:0] wstrb,
input wvalid, input wvalid,
output wready, output wready,
output reg bvalid, output reg bvalid,
input bready, input bready,
output reg [ 1:0] bresp, output reg [ 1:0] bresp,
output reg [TAGW-1:0] bid output reg [TAGW-1:0] bid
); );
parameter MEM_DEPTH = 15; // memory size = 0x8000 = 32k WIDTH=15 parameter MEM_DEPTH = 15; // memory size = 0x8000 = 32k WIDTH=15
parameter MEM_DEPTH_EACH = MEM_DEPTH - 3; // memory size = 0x8000 = 32k WIDTH=15 parameter MEM_DEPTH_EACH = MEM_DEPTH - 3; // memory size = 0x8000 = 32k WIDTH=15
bit [7:0] mem0[(1<<MEM_DEPTH_EACH)-1:0]; bit [7:0] mem0[(1<<MEM_DEPTH_EACH)-1:0];
bit [7:0] mem1[(1<<MEM_DEPTH_EACH)-1:0]; bit [7:0] mem1[(1<<MEM_DEPTH_EACH)-1:0];
bit [7:0] mem2[(1<<MEM_DEPTH_EACH)-1:0]; bit [7:0] mem2[(1<<MEM_DEPTH_EACH)-1:0];
bit [7:0] mem3[(1<<MEM_DEPTH_EACH)-1:0]; bit [7:0] mem3[(1<<MEM_DEPTH_EACH)-1:0];
bit [7:0] mem4[(1<<MEM_DEPTH_EACH)-1:0]; bit [7:0] mem4[(1<<MEM_DEPTH_EACH)-1:0];
bit [7:0] mem5[(1<<MEM_DEPTH_EACH)-1:0]; bit [7:0] mem5[(1<<MEM_DEPTH_EACH)-1:0];
bit [7:0] mem6[(1<<MEM_DEPTH_EACH)-1:0]; bit [7:0] mem6[(1<<MEM_DEPTH_EACH)-1:0];
bit [7:0] mem7[(1<<MEM_DEPTH_EACH)-1:0]; bit [7:0] mem7[(1<<MEM_DEPTH_EACH)-1:0];
bit [63:0] memdata; bit [63:0] memdata;
wire [MEM_DEPTH-1:0] saraddr = araddr[MEM_DEPTH - 1:0]; wire [MEM_DEPTH-4:0] saraddr0 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h0 ? 1 : 0);
wire [MEM_DEPTH-1:0] sawaddr = awaddr[MEM_DEPTH - 1:0]; wire [MEM_DEPTH-4:0] saraddr1 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h1 ? 1 : 0);
wire [MEM_DEPTH-4:0] saraddr2 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h2 ? 1 : 0);
wire [MEM_DEPTH-4:0] saraddr3 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h3 ? 1 : 0);
wire [MEM_DEPTH-4:0] saraddr4 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h4 ? 1 : 0);
wire [MEM_DEPTH-4:0] saraddr5 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h5 ? 1 : 0);
wire [MEM_DEPTH-4:0] saraddr6 = araddr[MEM_DEPTH - 1:3] + (araddr[2:0] > 3'h6 ? 1 : 0);
wire [MEM_DEPTH-4:0] saraddr7 = araddr[MEM_DEPTH - 1:3];
initial begin wire [7:0] rm0 = mem0[saraddr0];
mem0[0]= 8'h0; wire [7:0] rm1 = mem1[saraddr1];
mem0[1]= 8'h0; wire [7:0] rm2 = mem2[saraddr2];
mem0[2]= 8'h0; wire [7:0] rm3 = mem3[saraddr3];
mem0[3]= 8'h63; wire [7:0] rm4 = mem4[saraddr4];
mem0[5]= 8'h0; wire [7:0] rm5 = mem5[saraddr5];
mem0[6]= 8'h0; wire [7:0] rm6 = mem6[saraddr6];
mem0[7]= 8'h0; wire [7:0] rm7 = mem7[saraddr7];
mem0[8]= 8'h0;
wire [MEM_DEPTH-4:0] sawaddr0 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 0 ? 1 : 0);
wire [MEM_DEPTH-4:0] sawaddr1 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 1 ? 1 : 0);
wire [MEM_DEPTH-4:0] sawaddr2 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 2 ? 1 : 0);
wire [MEM_DEPTH-4:0] sawaddr3 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 3 ? 1 : 0);
wire [MEM_DEPTH-4:0] sawaddr4 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 4 ? 1 : 0);
wire [MEM_DEPTH-4:0] sawaddr5 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 5 ? 1 : 0);
wire [MEM_DEPTH-4:0] sawaddr6 = awaddr[MEM_DEPTH - 1:3] + (awaddr[2:0] > 6 ? 1 : 0);
wire [MEM_DEPTH-4:0] sawaddr7 = awaddr[MEM_DEPTH - 1:3];
initial begin
mem0[0] = 8'h63;
mem1[0] = 8'h0;
mem2[0] = 8'h0;
mem3[0] = 8'h0;
end
always @(posedge aclk or negedge rst_l) begin
if (!rst_l) begin
rvalid <= 0;
bvalid <= 0;
end else begin
bid <= awid;
rid <= arid;
rvalid <= arvalid;
bvalid <= awvalid;
rdata <= memdata;
end end
always @(posedge aclk or negedge rst_l) begin end
if (!rst_l) begin
rvalid <= 0; always @(negedge aclk) begin
bvalid <= 0; if (arvalid)
end else begin case (araddr[2:0])
bid <= awid; 3'h0: begin
rid <= arid; memdata <= {rm7, rm6, rm5, rm4, rm3, rm2, rm1, rm0};
rvalid <= arvalid; end
bvalid <= awvalid; 3'h1: begin
rdata <= memdata; memdata <= {rm0, rm7, rm6, rm5, rm4, rm3, rm2, rm1};
end end
3'h2: begin
memdata <= {rm1, rm0, rm7, rm6, rm5, rm4, rm3, rm2};
end
3'h3: begin
memdata <= {rm2, rm1, rm0, rm7, rm6, rm5, rm4, rm3};
end
3'h4: begin
memdata <= {rm3, rm2, rm1, rm0, rm7, rm6, rm5, rm4};
end
3'h5: begin
memdata <= {rm4, rm3, rm2, rm1, rm0, rm7, rm6, rm5};
end
3'h6: begin
memdata <= {rm5, rm4, rm3, rm2, rm1, rm0, rm7, rm6};
end
3'h7: begin
memdata <= {rm7, rm6, rm5, rm4, rm3, rm2, rm1, rm0};
end
endcase
if (awvalid) begin
case (awaddr[2:0])
3'h0: begin
if (wstrb[7]) mem7[sawaddr7] = wdata[63:56];
if (wstrb[6]) mem6[sawaddr6] = wdata[55:48];
if (wstrb[5]) mem5[sawaddr5] = wdata[47:40];
if (wstrb[4]) mem4[sawaddr4] = wdata[39:32];
if (wstrb[3]) mem3[sawaddr3] = wdata[31:24];
if (wstrb[2]) mem2[sawaddr2] = wdata[23:16];
if (wstrb[1]) mem1[sawaddr1] = wdata[15:08];
if (wstrb[0]) mem0[sawaddr0] = wdata[07:00];
end
3'h1: begin
if (wstrb[7]) mem0[sawaddr0] = wdata[63:56];
if (wstrb[6]) mem7[sawaddr7] = wdata[55:48];
if (wstrb[5]) mem6[sawaddr6] = wdata[47:40];
if (wstrb[4]) mem5[sawaddr5] = wdata[39:32];
if (wstrb[3]) mem4[sawaddr4] = wdata[31:24];
if (wstrb[2]) mem3[sawaddr3] = wdata[23:16];
if (wstrb[1]) mem2[sawaddr2] = wdata[15:08];
if (wstrb[0]) mem1[sawaddr1] = wdata[07:00];
end
3'h2: begin
if (wstrb[7]) mem1[sawaddr1] = wdata[63:56];
if (wstrb[6]) mem0[sawaddr0] = wdata[55:48];
if (wstrb[5]) mem7[sawaddr7] = wdata[47:40];
if (wstrb[4]) mem6[sawaddr6] = wdata[39:32];
if (wstrb[3]) mem5[sawaddr5] = wdata[31:24];
if (wstrb[2]) mem4[sawaddr4] = wdata[23:16];
if (wstrb[1]) mem3[sawaddr3] = wdata[15:08];
if (wstrb[0]) mem2[sawaddr2] = wdata[07:00];
end
3'h3: begin
if (wstrb[7]) mem2[sawaddr2] = wdata[63:56];
if (wstrb[6]) mem1[sawaddr1] = wdata[55:48];
if (wstrb[5]) mem0[sawaddr0] = wdata[47:40];
if (wstrb[4]) mem7[sawaddr7] = wdata[39:32];
if (wstrb[3]) mem6[sawaddr6] = wdata[31:24];
if (wstrb[2]) mem5[sawaddr5] = wdata[23:16];
if (wstrb[1]) mem4[sawaddr4] = wdata[15:08];
if (wstrb[0]) mem3[sawaddr3] = wdata[07:00];
end
3'h4: begin
if (wstrb[7]) mem3[sawaddr3] = wdata[63:56];
if (wstrb[6]) mem2[sawaddr2] = wdata[55:48];
if (wstrb[5]) mem1[sawaddr1] = wdata[47:40];
if (wstrb[4]) mem0[sawaddr0] = wdata[39:32];
if (wstrb[3]) mem7[sawaddr7] = wdata[31:24];
if (wstrb[2]) mem6[sawaddr6] = wdata[23:16];
if (wstrb[1]) mem5[sawaddr5] = wdata[15:08];
if (wstrb[0]) mem4[sawaddr4] = wdata[07:00];
end
3'h5: begin
if (wstrb[7]) mem4[sawaddr4] = wdata[63:56];
if (wstrb[6]) mem3[sawaddr3] = wdata[55:48];
if (wstrb[5]) mem2[sawaddr2] = wdata[47:40];
if (wstrb[4]) mem1[sawaddr1] = wdata[39:32];
if (wstrb[3]) mem0[sawaddr0] = wdata[31:24];
if (wstrb[2]) mem7[sawaddr7] = wdata[23:16];
if (wstrb[1]) mem6[sawaddr6] = wdata[15:08];
if (wstrb[0]) mem5[sawaddr5] = wdata[07:00];
end
3'h6: begin
if (wstrb[7]) mem5[sawaddr5] = wdata[63:56];
if (wstrb[6]) mem4[sawaddr4] = wdata[55:48];
if (wstrb[5]) mem3[sawaddr3] = wdata[47:40];
if (wstrb[4]) mem2[sawaddr2] = wdata[39:32];
if (wstrb[3]) mem1[sawaddr1] = wdata[31:24];
if (wstrb[2]) mem0[sawaddr0] = wdata[23:16];
if (wstrb[1]) mem7[sawaddr7] = wdata[15:08];
if (wstrb[0]) mem6[sawaddr6] = wdata[07:00];
end
3'h7: begin
if (wstrb[7]) mem6[sawaddr6] = wdata[63:56];
if (wstrb[6]) mem5[sawaddr5] = wdata[55:48];
if (wstrb[5]) mem4[sawaddr4] = wdata[47:40];
if (wstrb[4]) mem3[sawaddr3] = wdata[39:32];
if (wstrb[3]) mem2[sawaddr2] = wdata[31:24];
if (wstrb[2]) mem1[sawaddr1] = wdata[23:16];
if (wstrb[1]) mem0[sawaddr0] = wdata[15:08];
if (wstrb[0]) mem7[sawaddr7] = wdata[07:00];
end
endcase
end end
end
always @(negedge aclk) begin assign arready = 1'b1;
if (arvalid) assign awready = 1'b1;
memdata <= { assign wready = 1'b1;
mem7[saraddr + 7], assign rresp = 2'b0;
mem6[saraddr + 6], assign bresp = 2'b0;
mem5[saraddr + 5], assign rlast = 1'b1;
mem4[saraddr + 4],
mem3[saraddr + 3],
mem2[saraddr + 2],
mem1[saraddr + 1],
mem0[saraddr]
};
if (awvalid) begin
if (wstrb[7]) mem7[sawaddr + 7] = wdata[63:56];
if (wstrb[6]) mem6[sawaddr + 6] = wdata[55:48];
if (wstrb[5]) mem5[sawaddr + 5] = wdata[47:40];
if (wstrb[4]) mem4[sawaddr + 4] = wdata[39:32];
if (wstrb[3]) mem3[sawaddr + 3] = wdata[31:24];
if (wstrb[2]) mem2[sawaddr + 2] = wdata[23:16];
if (wstrb[1]) mem1[sawaddr + 1] = wdata[15:08];
if (wstrb[0]) mem0[sawaddr + 0] = wdata[07:00];
end
end
assign arready = 1'b1;
assign awready = 1'b1;
assign wready = 1'b1;
assign rresp = 2'b0;
assign bresp = 2'b0;
assign rlast = 1'b1;
endmodule endmodule

726
soc/soc_sim.sv
View File

@ -1,404 +1,406 @@
module soc_sim ( module soc_sim (
input bit core_clk input bit core_clk
); );
wire clk_out; wire clk_out;
logic rst_l; logic rst_l;
logic dbg_rst_l; logic dbg_rst_l;
wire jtag_tdo; wire jtag_tdo;
wire jtag_tck; wire jtag_tck;
wire jtag_tms; wire jtag_tms;
wire jtag_tdi; wire jtag_tdi;
wire jtag_trst_n; wire jtag_trst_n;
bit [31:0] cycleCnt; bit [31:0] cycleCnt;
logic mailbox_data_val; logic mailbox_data_val;
int commit_count; int commit_count;
logic wb_valid; logic wb_valid;
logic [ 4:0] wb_dest; logic [ 4:0] wb_dest;
logic [31:0] wb_data; logic [31:0] wb_data;
wire [63:0] WriteData; wire [63:0] WriteData;
string abi_reg [32]; // ABI register names string abi_reg [32]; // ABI register names
assign WriteData = rvsoc.lsu_axi_wdata; assign WriteData = rvsoc.lsu_axi_wdata;
assign mailbox_data_val = WriteData[7:0] > 8'h5 && WriteData[7:0] < 8'h7f; assign mailbox_data_val = WriteData[7:0] > 8'h5 && WriteData[7:0] < 8'h7f;
parameter MAILBOX_ADDR = 32'hD0580000; parameter MAILBOX_ADDR = 32'hD0580000;
logic write; logic write;
logic [31:0] laddr; logic [31:0] laddr;
wire mailbox_write = rvsoc.lmem_axi_awvalid && rvsoc.lsu_axi_awaddr == MAILBOX_ADDR && rst_l; wire mailbox_write = rvsoc.lmem_axi_awvalid && rvsoc.lsu_axi_awaddr == MAILBOX_ADDR && rst_l;
always @(posedge core_clk or negedge rst_l) begin always @(posedge core_clk or negedge rst_l) begin
if (~rst_l) begin if (~rst_l) begin
laddr <= 32'b0; laddr <= 32'b0;
write <= 1'b0; write <= 1'b0;
end else begin end else begin
if (rvsoc.lsu_hready) begin if (rvsoc.lsu_hready) begin
laddr <= rvsoc.lsu_haddr; laddr <= rvsoc.lsu_haddr;
write <= rvsoc.lsu_hwrite & |rvsoc.lsu_htrans; write <= rvsoc.lsu_hwrite & |rvsoc.lsu_htrans;
end
end end
end end
end
parameter MAX_CYCLES = 10_000_000_0; parameter MAX_CYCLES = 10_000_000_0;
integer fd, tp, el, pic, lsu, ifu, dec, exu; integer fd, tp, el, pic, lsu, ifu, dec, exu;
always @(posedge core_clk) begin always @(posedge core_clk) begin
cycleCnt <= cycleCnt + 1; cycleCnt <= cycleCnt + 1;
if (cycleCnt == MAX_CYCLES) begin if (cycleCnt == MAX_CYCLES) begin
$display("Hit max cycle count (%0d) .. stopping", cycleCnt); $display("Hit max cycle count (%0d) .. stopping", cycleCnt);
$finish; $finish;
end
if (mailbox_data_val & mailbox_write) begin
$fwrite(fd, "%c", WriteData[7:0]);
$write("%c", WriteData[7:0]);
end
if (mailbox_write && WriteData[7:0] == 8'hff) begin
$display("\nFinished : minstret = %0d, mcycle = %0d",
rvsoc.rvtop.core.dec.tlu.csr.minstretl[31:0],
rvsoc.rvtop.core.dec.tlu.csr.mcyclel[31:0]);
$display(
"See \"exec.log\" for execution trace with register updates..\n");
$display("TEST_PASSED");
$finish;
end else if (mailbox_write && WriteData[7:0] == 8'h1) begin
$display("TEST_FAILED");
$finish;
end
end end
if (mailbox_data_val & mailbox_write) begin
// trace monitor $fwrite(fd, "%c", WriteData[7:0]);
always @(posedge core_clk) begin $write("%c", WriteData[7:0]);
wb_valid <= rvsoc.rvtop.core.dec.decode_io_dec_i0_wen_r;
wb_dest <= rvsoc.rvtop.core.dec.decode_io_dec_i0_waddr_r;
wb_data <= rvsoc.rvtop.core.dec.decode_io_dec_i0_wdata_r;
if (rvsoc.trace_rv_i_valid_ip) begin
$fwrite(tp, "%b,%h,%h,%0h,%0h,3,%b,%h,%h,%b\n", rvsoc.trace_rv_i_valid_ip,
0, rvsoc.trace_rv_i_address_ip, 0, rvsoc.trace_rv_i_insn_ip,
rvsoc.trace_rv_i_exception_ip, rvsoc.trace_rv_i_ecause_ip,
rvsoc.trace_rv_i_tval_ip, rvsoc.trace_rv_i_interrupt_ip);
// Basic trace - no exception register updates
// #1 0 ee000000 b0201073 c 0b02 00000000
commit_count++;
$fwrite(el, "%10d : %8s 0 %h %h%13s ; %s\n", cycleCnt, $sformatf(
"#%0d", commit_count), rvsoc.trace_rv_i_address_ip,
rvsoc.trace_rv_i_insn_ip, (wb_dest != 0 && wb_valid) ? $sformatf(
"%s=%h", abi_reg[wb_dest], wb_data) : " ", dasm(
rvsoc.trace_rv_i_insn_ip,
rvsoc.trace_rv_i_address_ip,
wb_dest & {5{wb_valid}},
wb_data
));
end
if (rvsoc.rvtop.core.dec.decode_io_dec_nonblock_load_wen)
$fwrite(el, "%10d : %32s=%h ; nbL\n", cycleCnt,
abi_reg[rvsoc.rvtop.core.dec.decode_io_dec_nonblock_load_waddr],
rvsoc.rvtop.core.dec.io_lsu_nonblock_load_data);
if (rvsoc.rvtop.core.dec.io_exu_div_wren)
$fwrite(el, "%10d : %32s=%h ; nbD\n", cycleCnt,
abi_reg[rvsoc.rvtop.core.dec.decode_io_div_waddr_wb],
rvsoc.rvtop.core.dec.io_exu_div_result);
end end
if (mailbox_write && WriteData[7:0] == 8'hff) begin
$display("\nFinished : minstret = %0d, mcycle = %0d",
//////////////////////////////////////////////////pic tracer/////////////////////////////////////////////////////// rvsoc.rvtop.core.dec.tlu.csr.minstretl[31:0],
always @(posedge core_clk) begin rvsoc.rvtop.core.dec.tlu.csr.mcyclel[31:0]);
$display("See \"exec.log\" for execution trace with register updates..\n");
if (rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_wren == 1) begin $display("TEST_PASSED");
$fwrite(pic, "%0d,%0d,%h\t", $finish;
rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_wren, end else if (mailbox_write && WriteData[7:0] == 8'h1) begin
rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_wraddr, $display("TEST_FAILED");
rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_wr_data); $finish;
end else if (rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_rden == 1)
$fwrite(pic, "x\tx\tx\t");
if (rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_rden == 1) begin
$fwrite(pic, "%0d,%0d,%h\n",
rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_rden,
rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_rdaddr,
rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_rd_data);
end else if (rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_wren == 1)
$fwrite(pic, "x\tx\tx\t\n");
end end
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////// end
//////////////////////////////////////////////////LSU tracer///////////////////////////////////////////////////////
always @(posedge core_clk) begin
if (rvsoc.rvtop.core.lsu.io_dccm_wren == 1) begin // trace monitor
$fwrite(lsu, "%0h,%0h,%0h,%0h,%0h\t", rvsoc.rvtop.core.lsu.io_dccm_wren, always @(posedge core_clk) begin
rvsoc.rvtop.core.lsu.io_dccm_wr_addr_hi, wb_valid <= rvsoc.rvtop.core.dec.decode_io_dec_i0_wen_r;
rvsoc.rvtop.core.lsu.io_dccm_wr_addr_lo, wb_dest <= rvsoc.rvtop.core.dec.decode_io_dec_i0_waddr_r;
rvsoc.rvtop.core.lsu.io_dccm_wr_data_hi, wb_data <= rvsoc.rvtop.core.dec.decode_io_dec_i0_wdata_r;
rvsoc.rvtop.core.lsu.io_dccm_wr_data_lo); if (rvsoc.trace_rv_i_valid_ip) begin
$fwrite(tp, "%b,%h,%h,%0h,%0h,3,%b,%h,%h,%b\n", rvsoc.trace_rv_i_valid_ip, 0,
end rvsoc.trace_rv_i_address_ip, 0, rvsoc.trace_rv_i_insn_ip,
else if(rvsoc.rvtop.core.lsu.io_dccm_rden == 1 || rvsoc.rvtop.core.lsu.io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid) rvsoc.trace_rv_i_exception_ip, rvsoc.trace_rv_i_ecause_ip, rvsoc.trace_rv_i_tval_ip,
$fwrite(lsu, "x\tx\tx\tx\tx\t"); rvsoc.trace_rv_i_interrupt_ip);
// Basic trace - no exception register updates
if (rvsoc.rvtop.core.lsu.io_dccm_rden == 1) begin // #1 0 ee000000 b0201073 c 0b02 00000000
$fwrite(lsu, "%0h,%0h,%0h,%0h,%0h\t", rvsoc.rvtop.core.lsu.io_dccm_rden, commit_count++;
rvsoc.rvtop.core.lsu.io_dccm_rd_addr_hi, $fwrite(
rvsoc.rvtop.core.lsu.io_dccm_rd_addr_lo, el, "%10d : %8s 0 %h %h%13s ; %s\n", cycleCnt, $sformatf("#%0d", commit_count),
rvsoc.rvtop.core.lsu.io_dccm_rd_data_hi, rvsoc.trace_rv_i_address_ip, rvsoc.trace_rv_i_insn_ip,
rvsoc.rvtop.core.lsu.io_dccm_rd_data_lo); (wb_dest != 0 && wb_valid) ? $sformatf("%s=%h", abi_reg[wb_dest], wb_data
) : " ", dasm(
end rvsoc.trace_rv_i_insn_ip, rvsoc.trace_rv_i_address_ip, wb_dest & {5{wb_valid}}, wb_data));
else if(rvsoc.rvtop.core.lsu.io_dccm_wren == 1 || rvsoc.rvtop.core.lsu.io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid)
$fwrite(lsu, "x\tx\tx\tx\tx\t");
if (rvsoc.rvtop.core.lsu.io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid == 1) begin
$fwrite(lsu, "%0h,%0h\n",
rvsoc.rvtop.core.lsu.io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid,
rvsoc.rvtop.core.lsu.io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata);
end
else if (rvsoc.rvtop.core.lsu.io_dccm_wren == 1 || rvsoc.rvtop.core.lsu.io_dccm_rden== 1)
$fwrite(lsu, "x\tx\n");
end end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// if (rvsoc.rvtop.core.dec.decode_io_dec_nonblock_load_wen)
//////////////////////////////////////////////////IFU tracer//////////////////////////////////////////////////////// $fwrite(el, "%10d : %32s=%h ; nbL\n", cycleCnt,
always @(posedge core_clk) begin abi_reg[rvsoc.rvtop.core.dec.decode_io_dec_nonblock_load_waddr],
rvsoc.rvtop.core.dec.io_lsu_nonblock_load_data);
if (rvsoc.rvtop.core.dec.io_exu_div_wren)
$fwrite(el, "%10d : %32s=%h ; nbD\n", cycleCnt,
abi_reg[rvsoc.rvtop.core.dec.decode_io_div_waddr_wb],
rvsoc.rvtop.core.dec.io_exu_div_result);
end
if (rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 && cycleCnt != 0) begin
$fwrite(ifu, "%5d,%0h,%0h,%0h\t", cycleCnt,
rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid,
rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_instr,
rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc);
end
else if((rvsoc.rvtop.core.ifu.io_iccm_wren == 1 || rvsoc.rvtop.core.ifu.io_iccm_rden==1 || rvsoc.rvtop.core.ifu.io_ic_wr_en !==0 || rvsoc.rvtop.core.ifu.io_ic_rd_en ==1 || rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1) && cycleCnt != 0) //////////////////////////////////////////////////pic tracer///////////////////////////////////////////////////////
$fwrite(ifu, "%5d,x\tx\tx\t", cycleCnt); always @(posedge core_clk) begin
if (rvsoc.rvtop.core.ifu.io_iccm_wren == 1 && cycleCnt != 0) begin if (rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_wren == 1) begin
$fwrite(ifu, "%0h,%0h,%0h\t", rvsoc.rvtop.core.ifu.io_iccm_wren, $fwrite(pic, "%0d,%0d,%h\t", rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_wren,
rvsoc.rvtop.core.ifu.io_iccm_rw_addr, rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_wraddr,
rvsoc.rvtop.core.ifu.io_iccm_wr_data); rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_wr_data);
end
else if((rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 || rvsoc.rvtop.core.ifu.io_iccm_rden==1 || rvsoc.rvtop.core.ifu.io_ic_wr_en !==0 || rvsoc.rvtop.core.ifu.io_ic_rd_en ==1 || rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1) && cycleCnt != 0) end else if (rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_rden == 1)
$fwrite(ifu, "\tx\tx\tx\t"); $fwrite(pic, "x\tx\tx\t");
if (rvsoc.rvtop.core.ifu.io_iccm_rden == 1 && cycleCnt != 0) begin if (rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_rden == 1) begin
$fwrite(ifu, "%0h,%0h,%0h\t", rvsoc.rvtop.core.ifu.io_iccm_rden, $fwrite(pic, "%0d,%0d,%h\n", rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_rden,
rvsoc.rvtop.core.ifu.io_iccm_rw_addr, rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_rdaddr,
rvsoc.rvtop.core.ifu.io_iccm_rd_data_ecc); rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_rd_data);
end
else if((rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 || rvsoc.rvtop.core.ifu.io_iccm_wren==1 || rvsoc.rvtop.core.ifu.io_ic_wr_en !==0 || rvsoc.rvtop.core.ifu.io_ic_rd_en ==1 || rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1)&& cycleCnt != 0) end else if (rvsoc.rvtop.core.pic_ctrl_inst.io_lsu_pic_picm_wren == 1)
$fwrite(ifu, "\tx\tx\tx\t"); $fwrite(pic, "x\tx\tx\t\n");
end
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////LSU tracer///////////////////////////////////////////////////////
always @(posedge core_clk) begin
if (rvsoc.rvtop.core.ifu.io_ic_wr_en !== 0 && cycleCnt != 0) begin if (rvsoc.rvtop.core.lsu.io_dccm_wren == 1) begin
$fwrite(ifu, "%0h,%0h,%0h\t", rvsoc.rvtop.core.ifu.io_ic_wr_en, $fwrite(lsu, "%0h,%0h,%0h,%0h,%0h\t", rvsoc.rvtop.core.lsu.io_dccm_wren,
rvsoc.rvtop.core.ifu.io_ic_rw_addr, rvsoc.rvtop.core.lsu.io_dccm_wr_addr_hi, rvsoc.rvtop.core.lsu.io_dccm_wr_addr_lo,
rvsoc.rvtop.core.ifu.io_ic_wr_data_0, rvsoc.rvtop.core.lsu.io_dccm_wr_data_hi, rvsoc.rvtop.core.lsu.io_dccm_wr_data_lo);
rvsoc.rvtop.core.ifu.io_ic_wr_data_1);
end
else if((rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 || rvsoc.rvtop.core.ifu.io_iccm_wren==1 || rvsoc.rvtop.core.ifu.io_iccm_rden ==1 || rvsoc.rvtop.core.ifu.io_ic_rd_en ==1 || rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1)&& cycleCnt != 0)
$fwrite(ifu, "\tx\tx\tx\tx\t");
if (rvsoc.rvtop.core.ifu.io_ic_rd_en == 1 && cycleCnt != 0) begin
$fwrite(ifu, "%0h,%0h,%0h\t", rvsoc.rvtop.core.ifu.io_ic_rd_en,
rvsoc.rvtop.core.ifu.io_ic_rw_addr,
rvsoc.rvtop.core.ifu.io_ic_rd_data);
end
else if((rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 || rvsoc.rvtop.core.ifu.io_iccm_wren==1 || rvsoc.rvtop.core.ifu.io_iccm_rden ==1 || rvsoc.rvtop.core.ifu.io_ic_wr_en !== 0 ||rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1)&& cycleCnt != 0)
$fwrite(ifu, "\tx\tx\tx\t");
if (rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1 && cycleCnt != 0) begin
$fwrite(ifu, "%h,%0h\n", rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid,
rvsoc.rvtop.core.ifu.io_iccm_dma_rdata);
end
else if((rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 || rvsoc.rvtop.core.ifu.io_iccm_wren==1 || rvsoc.rvtop.core.ifu.io_iccm_rden ==1 || rvsoc.rvtop.core.ifu.io_ic_wr_en !== 0 || rvsoc.rvtop.core.ifu.io_ic_rd_en)&& cycleCnt != 0)
$fwrite(ifu, "\tx\tx\n");
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////DEC tracer////////////////////////////////////////////////////////
always @(posedge core_clk) begin
if (rvsoc.rvtop.core.dma_ctrl.io_dma_dbg_cmd_done == 1) begin
$fwrite(dec, "%5d,\t%0h,%0h\t", cycleCnt,
rvsoc.rvtop.core.dma_ctrl.io_dma_dbg_cmd_done,
rvsoc.rvtop.core.dec.io_dec_dbg_rddata);
end
else if(rvsoc.rvtop.core.dec.io_dec_exu_dec_alu_dec_i0_alu_decode_d == 1 || rvsoc.rvtop.core.dec.decode_io_dec_csr_wen_r==1)
$fwrite(dec, "%5d,\tx\tx\t", cycleCnt);
if (rvsoc.rvtop.core.dec.io_dec_exu_dec_alu_dec_i0_alu_decode_d == 1) begin
$fwrite(dec, "%0h,%0h,%0h,%0h,%0h,%0h\t",
rvsoc.rvtop.core.dec.io_dec_exu_dec_alu_dec_i0_alu_decode_d,
rvsoc.rvtop.core.dec.decode_io_decode_exu_dec_i0_rs1_en_d,
rvsoc.rvtop.core.exu.i0_rs1_d,
rvsoc.rvtop.core.dec.decode_io_decode_exu_dec_i0_rs2_en_d,
rvsoc.rvtop.core.exu.i0_rs2_d,
rvsoc.rvtop.core.exu.io_dec_exu_decode_exu_exu_i0_result_x);
end
else if(rvsoc.rvtop.core.dma_ctrl.io_dma_dbg_cmd_done == 1 || rvsoc.rvtop.core.dec.decode_io_dec_csr_wen_r==1)
$fwrite(dec, "x\t,x\t,x\t,x\tx\tx\t");
if (rvsoc.rvtop.core.dec.decode_io_dec_csr_wen_r == 1) begin
$fwrite(dec, "%0h,%0h,%0h,%0h,%0h\n",
rvsoc.rvtop.core.dec.decode_io_dec_csr_wen_r,
rvsoc.rvtop.core.dec.decode_io_dec_csr_wraddr_r,
rvsoc.rvtop.core.dec.decode_io_dec_csr_wrdata_r,
rvsoc.rvtop.core.dec.decode_io_dec_csr_rdaddr_d,
rvsoc.rvtop.core.dec.decode_io_dec_csr_rddata_d);
end
else if(rvsoc.rvtop.core.dma_ctrl.io_dma_dbg_cmd_done == 1 || rvsoc.rvtop.core.dec.io_dec_exu_dec_alu_dec_i0_alu_decode_d == 1 )
$fwrite(dec, "x\t,x\t,x\t,x\t,x\n");
end end
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////// else if(rvsoc.rvtop.core.lsu.io_dccm_rden == 1 || rvsoc.rvtop.core.lsu.io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid)
/////////////////////////////////////////////////exu tracer/////////////////////////////////////////////////// $fwrite(lsu, "x\tx\tx\tx\tx\t");
always @(posedge core_clk) begin
if (rvsoc.rvtop.core.exu.io_exu_div_wren == 1) begin if (rvsoc.rvtop.core.lsu.io_dccm_rden == 1) begin
$fwrite(exu, "%5d,\t%0h,%0h,%0h,%0h,%0h\t", cycleCnt, $fwrite(lsu, "%0h,%0h,%0h,%0h,%0h\t", rvsoc.rvtop.core.lsu.io_dccm_rden,
rvsoc.rvtop.core.exu.io_exu_div_wren, rvsoc.rvtop.core.lsu.io_dccm_rd_addr_hi, rvsoc.rvtop.core.lsu.io_dccm_rd_addr_lo,
rvsoc.rvtop.core.exu.io_exu_div_result, rvsoc.rvtop.core.lsu.io_dccm_rd_data_hi, rvsoc.rvtop.core.lsu.io_dccm_rd_data_lo);
rvsoc.rvtop.core.exu.i_div.io_dividend,
rvsoc.rvtop.core.exu.i_div.io_divisor,
rvsoc.rvtop.core.exu.i_div.io_exu_div_result);
end
else if(rvsoc.rvtop.core.exu.i0_rs1_bypass_en_d == 1 || rvsoc.rvtop.core.exu.i0_rs2_bypass_en_d == 1)
$fwrite(exu, "%5d,\tx\tx\tx\tx\tx,\t", cycleCnt);
if (rvsoc.rvtop.core.exu.i0_rs1_bypass_en_d == 1) begin
$fwrite(exu, "\t%0h,%0h\t", rvsoc.rvtop.core.exu.i0_rs1_bypass_en_d,
rvsoc.rvtop.core.exu.i0_rs1_bypass_data_d);
end
else if(rvsoc.rvtop.core.exu.io_exu_div_wren == 1 || rvsoc.rvtop.core.exu.i0_rs2_bypass_en_d == 1)
$fwrite(exu, "\tx\tx\t");
if (rvsoc.rvtop.core.exu.i0_rs2_bypass_en_d == 1) begin
$fwrite(exu, "\t%0h,%0h\n", rvsoc.rvtop.core.exu.i0_rs2_bypass_en_d,
rvsoc.rvtop.core.exu.i0_rs2_bypass_data_d);
end
else if(rvsoc.rvtop.core.exu.io_exu_div_wren == 1 || rvsoc.rvtop.core.exu.i0_rs1_bypass_en_d == 1)
$fwrite(exu, "\tx\tx\n");
end
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
initial begin
abi_reg[0] = "zero";
abi_reg[1] = "ra";
abi_reg[2] = "sp";
abi_reg[3] = "gp";
abi_reg[4] = "tp";
abi_reg[5] = "t0";
abi_reg[6] = "t1";
abi_reg[7] = "t2";
abi_reg[8] = "s0";
abi_reg[9] = "s1";
abi_reg[10] = "a0";
abi_reg[11] = "a1";
abi_reg[12] = "a2";
abi_reg[13] = "a3";
abi_reg[14] = "a4";
abi_reg[15] = "a5";
abi_reg[16] = "a6";
abi_reg[17] = "a7";
abi_reg[18] = "s2";
abi_reg[19] = "s3";
abi_reg[20] = "s4";
abi_reg[21] = "s5";
abi_reg[22] = "s6";
abi_reg[23] = "s7";
abi_reg[24] = "s8";
abi_reg[25] = "s9";
abi_reg[26] = "s10";
abi_reg[27] = "s11";
abi_reg[28] = "t3";
abi_reg[29] = "t4";
abi_reg[30] = "t5";
abi_reg[31] = "t6";
$readmemh("program.hex", rvsoc.lmem.mem);
$readmemh("program.hex", rvsoc.imem.mem);
tp = $fopen("trace_port.csv", "w");
el = $fopen("exec.log", "w");
//////////////////////////////////////////////////////////////////
pic = $fopen("pic.log", "w");
$fwrite(pic,
" write enable, write addr , write data ,read enable, read address, read data \n");
///////////////////////////////////////////////////////////////////
lsu = $fopen("lsu.log", "w");
$fwrite(lsu,
"write en, write addrs hi,write addrs lo, write data hi,write data lo, read_en, read addrs hi,read addrs lo, read data hi,read data lo, dma valid, dma read data \n");
/////////////////////////////////////////////////////////////////////////
ifu = $fopen("ifu.log", "w");
$fwrite(ifu,
"cycleCnt,inst_valid,inst,inst_pc\ticcm wen,iccm waddr,iccm wdata, iccm ren,iccm raddr, iccm rdata\tic wen,ic waddr,ic wdata0,ic wdata1\tic ren,ic raddr,ic rdata\ticcm dma rvalid,iccm dma rdata\n");
///////////////////////////////////////////////////////////////////////////
dec = $fopen("dec.log", "w");
$fwrite(dec,
"clock cycle dbg cmd, dbg rd data\talu decode, rs1 en, rs1, rs2 en, rs2, result, csr wen, csr wr addr, csr wrdata, csr rd addr, csr rd data\n");
///////////////////////////////////////////////////////////////////////////
exu = $fopen("exu.log", "w");
$fwrite(exu,
"clock cycle div enable, div result, dividend, divisor, out\t,rs1 bypassen, rs1 bypassdata\t, rs2 bypassen, rs2 bypassdata\n");
$fwrite(el, "//Cycle : #inst 0 pc opcode reg regnum value\n");
fd = $fopen("console.log", "w");
commit_count = 0;
end end
else if(rvsoc.rvtop.core.lsu.io_dccm_wren == 1 || rvsoc.rvtop.core.lsu.io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid)
$fwrite(lsu, "x\tx\tx\tx\tx\t");
assign rst_l = cycleCnt > 5; if (rvsoc.rvtop.core.lsu.io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid == 1) begin
assign dbg_rst_l = cycleCnt > 2; $fwrite(lsu, "%0h,%0h\n", rvsoc.rvtop.core.lsu.io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid,
rvsoc.rvtop.core.lsu.io_lsu_dma_dma_dccm_ctl_dccm_dma_rdata);
end else if (rvsoc.rvtop.core.lsu.io_dccm_wren == 1 || rvsoc.rvtop.core.lsu.io_dccm_rden == 1)
$fwrite(lsu, "x\tx\n");
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////IFU tracer////////////////////////////////////////////////////////
always @(posedge core_clk) begin
soc_top rvsoc ( if (rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 && cycleCnt != 0) begin
.clk(core_clk), $fwrite(ifu, "%5d,%0h,%0h,%0h\t", cycleCnt,
.clk_o(clk_out), rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid,
.rst(rst_l), rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_instr,
.dbg_rst(dbg_rst_l), rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_pc);
end
.jtag_tdo(jtag_tdo), else if((rvsoc.rvtop.core.ifu.io_iccm_wren == 1 || rvsoc.rvtop.core.ifu.io_iccm_rden==1 || rvsoc.rvtop.core.ifu.io_ic_wr_en !==0 || rvsoc.rvtop.core.ifu.io_ic_rd_en ==1 || rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1) && cycleCnt != 0)
.jtag_tck(jtag_tck), $fwrite(ifu, "%5d,x\tx\tx\t", cycleCnt);
.jtag_tms(jtag_tms),
.jtag_tdi(jtag_tdi),
.jtag_trst_n(jtag_trst_n)
);
jtagdpi jtagdpi ( if (rvsoc.rvtop.core.ifu.io_iccm_wren == 1 && cycleCnt != 0) begin
.clk_i (core_clk), $fwrite(ifu, "%0h,%0h,%0h\t", rvsoc.rvtop.core.ifu.io_iccm_wren,
.rst_ni(rst_l), rvsoc.rvtop.core.ifu.io_iccm_rw_addr, rvsoc.rvtop.core.ifu.io_iccm_wr_data);
end
.jtag_tck(jtag_tck), else if((rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 || rvsoc.rvtop.core.ifu.io_iccm_rden==1 || rvsoc.rvtop.core.ifu.io_ic_wr_en !==0 || rvsoc.rvtop.core.ifu.io_ic_rd_en ==1 || rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1) && cycleCnt != 0)
.jtag_tms(jtag_tms), $fwrite(ifu, "\tx\tx\tx\t");
.jtag_tdi(jtag_tdi),
.jtag_tdo(jtag_tdo),
.jtag_trst_n(jtag_trst_n),
.jtag_srst_n()
);
`define DRAM(bank) \ if (rvsoc.rvtop.core.ifu.io_iccm_rden == 1 && cycleCnt != 0) begin
rvsoc.rvtop.mem.Gen_dccm_enable.dccm.mem_bank[bank].dccm_bank.ram_core $fwrite(ifu, "%0h,%0h,%0h\t", rvsoc.rvtop.core.ifu.io_iccm_rden,
rvsoc.rvtop.core.ifu.io_iccm_rw_addr, rvsoc.rvtop.core.ifu.io_iccm_rd_data_ecc);
end
`define ICCM_PATH `RV_TOP.mem.iccm else if((rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 || rvsoc.rvtop.core.ifu.io_iccm_wren==1 || rvsoc.rvtop.core.ifu.io_ic_wr_en !==0 || rvsoc.rvtop.core.ifu.io_ic_rd_en ==1 || rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1)&& cycleCnt != 0)
`define IRAM0(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_lo0.ram_core $fwrite(ifu, "\tx\tx\tx\t");
`define IRAM1(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_lo1.ram_core
`define IRAM2(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_hi0.ram_core
`define IRAM3(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_hi1.ram_core
/* verilator lint_off WIDTH */ if (rvsoc.rvtop.core.ifu.io_ic_wr_en !== 0 && cycleCnt != 0) begin
/* verilator lint_off CASEINCOMPLETE */ $fwrite(ifu, "%0h,%0h,%0h\t", rvsoc.rvtop.core.ifu.io_ic_wr_en,
`include "dasm.svi" rvsoc.rvtop.core.ifu.io_ic_rw_addr, rvsoc.rvtop.core.ifu.io_ic_wr_data_0,
/* verilator lint_on CASEINCOMPLETE */ rvsoc.rvtop.core.ifu.io_ic_wr_data_1);
/* verilator lint_on WIDTH */ end
else if((rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 || rvsoc.rvtop.core.ifu.io_iccm_wren==1 || rvsoc.rvtop.core.ifu.io_iccm_rden ==1 || rvsoc.rvtop.core.ifu.io_ic_rd_en ==1 || rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1)&& cycleCnt != 0)
$fwrite(ifu, "\tx\tx\tx\tx\t");
if (rvsoc.rvtop.core.ifu.io_ic_rd_en == 1 && cycleCnt != 0) begin
$fwrite(ifu, "%0h,%0h,%0h\t", rvsoc.rvtop.core.ifu.io_ic_rd_en,
rvsoc.rvtop.core.ifu.io_ic_rw_addr, rvsoc.rvtop.core.ifu.io_ic_rd_data);
end
else if((rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 || rvsoc.rvtop.core.ifu.io_iccm_wren==1 || rvsoc.rvtop.core.ifu.io_iccm_rden ==1 || rvsoc.rvtop.core.ifu.io_ic_wr_en !== 0 ||rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1)&& cycleCnt != 0)
$fwrite(ifu, "\tx\tx\tx\t");
if (rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid == 1 && cycleCnt != 0) begin
$fwrite(ifu, "%h,%0h\n", rvsoc.rvtop.core.ifu.io_iccm_dma_rvalid,
rvsoc.rvtop.core.ifu.io_iccm_dma_rdata);
end
else if((rvsoc.rvtop.core.ifu.aln_ctl_io_dec_aln_aln_ib_ifu_i0_valid == 1 || rvsoc.rvtop.core.ifu.io_iccm_wren==1 || rvsoc.rvtop.core.ifu.io_iccm_rden ==1 || rvsoc.rvtop.core.ifu.io_ic_wr_en !== 0 || rvsoc.rvtop.core.ifu.io_ic_rd_en)&& cycleCnt != 0)
$fwrite(ifu, "\tx\tx\n");
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////DEC tracer////////////////////////////////////////////////////////
always @(posedge core_clk) begin
if (rvsoc.rvtop.core.dma_ctrl.io_dma_dbg_cmd_done == 1) begin
$fwrite(dec, "%5d,\t%0h,%0h\t", cycleCnt, rvsoc.rvtop.core.dma_ctrl.io_dma_dbg_cmd_done,
rvsoc.rvtop.core.dec.io_dec_dbg_rddata);
end
else if(rvsoc.rvtop.core.dec.io_dec_exu_dec_alu_dec_i0_alu_decode_d == 1 || rvsoc.rvtop.core.dec.decode_io_dec_csr_wen_r==1)
$fwrite(dec, "%5d,\tx\tx\t", cycleCnt);
if (rvsoc.rvtop.core.dec.io_dec_exu_dec_alu_dec_i0_alu_decode_d == 1) begin
$fwrite(
dec, "%0h,%0h,%0h,%0h,%0h,%0h\t",
rvsoc.rvtop.core.dec.io_dec_exu_dec_alu_dec_i0_alu_decode_d,
rvsoc.rvtop.core.dec.decode_io_decode_exu_dec_i0_rs1_en_d, rvsoc.rvtop.core.exu.i0_rs1_d,
rvsoc.rvtop.core.dec.decode_io_decode_exu_dec_i0_rs2_en_d, rvsoc.rvtop.core.exu.i0_rs2_d,
rvsoc.rvtop.core.exu.io_dec_exu_decode_exu_exu_i0_result_x);
end
else if(rvsoc.rvtop.core.dma_ctrl.io_dma_dbg_cmd_done == 1 || rvsoc.rvtop.core.dec.decode_io_dec_csr_wen_r==1)
$fwrite(dec, "x\t,x\t,x\t,x\tx\tx\t");
if (rvsoc.rvtop.core.dec.decode_io_dec_csr_wen_r == 1) begin
$fwrite(dec, "%0h,%0h,%0h,%0h,%0h\n", rvsoc.rvtop.core.dec.decode_io_dec_csr_wen_r,
rvsoc.rvtop.core.dec.decode_io_dec_csr_wraddr_r,
rvsoc.rvtop.core.dec.decode_io_dec_csr_wrdata_r,
rvsoc.rvtop.core.dec.decode_io_dec_csr_rdaddr_d,
rvsoc.rvtop.core.dec.decode_io_dec_csr_rddata_d);
end
else if(rvsoc.rvtop.core.dma_ctrl.io_dma_dbg_cmd_done == 1 || rvsoc.rvtop.core.dec.io_dec_exu_dec_alu_dec_i0_alu_decode_d == 1 )
$fwrite(dec, "x\t,x\t,x\t,x\t,x\n");
end
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////exu tracer///////////////////////////////////////////////////
always @(posedge core_clk) begin
if (rvsoc.rvtop.core.exu.io_exu_div_wren == 1) begin
$fwrite(exu, "%5d,\t%0h,%0h,%0h,%0h,%0h\t", cycleCnt, rvsoc.rvtop.core.exu.io_exu_div_wren,
rvsoc.rvtop.core.exu.io_exu_div_result, rvsoc.rvtop.core.exu.i_div.io_dividend,
rvsoc.rvtop.core.exu.i_div.io_divisor, rvsoc.rvtop.core.exu.i_div.io_exu_div_result);
end
else if(rvsoc.rvtop.core.exu.i0_rs1_bypass_en_d == 1 || rvsoc.rvtop.core.exu.i0_rs2_bypass_en_d == 1)
$fwrite(exu, "%5d,\tx\tx\tx\tx\tx,\t", cycleCnt);
if (rvsoc.rvtop.core.exu.i0_rs1_bypass_en_d == 1) begin
$fwrite(exu, "\t%0h,%0h\t", rvsoc.rvtop.core.exu.i0_rs1_bypass_en_d,
rvsoc.rvtop.core.exu.i0_rs1_bypass_data_d);
end
else if(rvsoc.rvtop.core.exu.io_exu_div_wren == 1 || rvsoc.rvtop.core.exu.i0_rs2_bypass_en_d == 1)
$fwrite(exu, "\tx\tx\t");
if (rvsoc.rvtop.core.exu.i0_rs2_bypass_en_d == 1) begin
$fwrite(exu, "\t%0h,%0h\n", rvsoc.rvtop.core.exu.i0_rs2_bypass_en_d,
rvsoc.rvtop.core.exu.i0_rs2_bypass_data_d);
end
else if(rvsoc.rvtop.core.exu.io_exu_div_wren == 1 || rvsoc.rvtop.core.exu.i0_rs1_bypass_en_d == 1)
$fwrite(exu, "\tx\tx\n");
end
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
reg [7:0] hex[(1<<rvsoc.imem.MEM_DEPTH)-1:0];
initial begin
abi_reg[0] = "zero";
abi_reg[1] = "ra";
abi_reg[2] = "sp";
abi_reg[3] = "gp";
abi_reg[4] = "tp";
abi_reg[5] = "t0";
abi_reg[6] = "t1";
abi_reg[7] = "t2";
abi_reg[8] = "s0";
abi_reg[9] = "s1";
abi_reg[10] = "a0";
abi_reg[11] = "a1";
abi_reg[12] = "a2";
abi_reg[13] = "a3";
abi_reg[14] = "a4";
abi_reg[15] = "a5";
abi_reg[16] = "a6";
abi_reg[17] = "a7";
abi_reg[18] = "s2";
abi_reg[19] = "s3";
abi_reg[20] = "s4";
abi_reg[21] = "s5";
abi_reg[22] = "s6";
abi_reg[23] = "s7";
abi_reg[24] = "s8";
abi_reg[25] = "s9";
abi_reg[26] = "s10";
abi_reg[27] = "s11";
abi_reg[28] = "t3";
abi_reg[29] = "t4";
abi_reg[30] = "t5";
abi_reg[31] = "t6";
$readmemh("program.hex", hex);
for (
reg [rvsoc.imem.MEM_DEPTH-1:0] i = 0; i < (1 << (rvsoc.imem.MEM_DEPTH - 3)); i++
) begin
rvsoc.imem.mem0[i] = hex[(i<<3)+0];
rvsoc.imem.mem1[i] = hex[(i<<3)+1];
rvsoc.imem.mem2[i] = hex[(i<<3)+2];
rvsoc.imem.mem3[i] = hex[(i<<3)+3];
rvsoc.imem.mem4[i] = hex[(i<<3)+4];
rvsoc.imem.mem5[i] = hex[(i<<3)+5];
rvsoc.imem.mem6[i] = hex[(i<<3)+6];
rvsoc.imem.mem7[i] = hex[(i<<3)+7];
end
for (
reg [rvsoc.lmem.MEM_DEPTH-1:0] i = 0; i < (1 << (rvsoc.lmem.MEM_DEPTH - 3)); i++
) begin
rvsoc.lmem.mem0[i] = hex[(i<<3)+0];
rvsoc.lmem.mem1[i] = hex[(i<<3)+1];
rvsoc.lmem.mem2[i] = hex[(i<<3)+2];
rvsoc.lmem.mem3[i] = hex[(i<<3)+3];
rvsoc.lmem.mem4[i] = hex[(i<<3)+4];
rvsoc.lmem.mem5[i] = hex[(i<<3)+5];
rvsoc.lmem.mem6[i] = hex[(i<<3)+6];
rvsoc.lmem.mem7[i] = hex[(i<<3)+7];
end
tp = $fopen("trace_port.csv", "w");
el = $fopen("exec.log", "w");
//////////////////////////////////////////////////////////////////
pic = $fopen("pic.log", "w");
$fwrite(pic, " write enable, write addr , write data ,read enable, read address, read data \n");
///////////////////////////////////////////////////////////////////
lsu = $fopen("lsu.log", "w");
$fwrite(lsu,
"write en, write addrs hi,write addrs lo, write data hi,write data lo, read_en, read addrs hi,read addrs lo, read data hi,read data lo, dma valid, dma read data \n");
/////////////////////////////////////////////////////////////////////////
ifu = $fopen("ifu.log", "w");
$fwrite(ifu,
"cycleCnt,inst_valid,inst,inst_pc\ticcm wen,iccm waddr,iccm wdata, iccm ren,iccm raddr, iccm rdata\tic wen,ic waddr,ic wdata0,ic wdata1\tic ren,ic raddr,ic rdata\ticcm dma rvalid,iccm dma rdata\n");
///////////////////////////////////////////////////////////////////////////
dec = $fopen("dec.log", "w");
$fwrite(dec,
"clock cycle dbg cmd, dbg rd data\talu decode, rs1 en, rs1, rs2 en, rs2, result, csr wen, csr wr addr, csr wrdata, csr rd addr, csr rd data\n");
///////////////////////////////////////////////////////////////////////////
exu = $fopen("exu.log", "w");
$fwrite(exu,
"clock cycle div enable, div result, dividend, divisor, out\t,rs1 bypassen, rs1 bypassdata\t, rs2 bypassen, rs2 bypassdata\n");
$fwrite(el, "//Cycle : #inst 0 pc opcode reg regnum value\n");
fd = $fopen("console.log", "w");
commit_count = 0;
end
assign rst_l = cycleCnt > 5;
assign dbg_rst_l = cycleCnt > 2;
soc_top rvsoc (
.clk(core_clk),
.clk_o(clk_out),
.rst(rst_l),
.dbg_rst(dbg_rst_l),
.jtag_tdo(jtag_tdo),
.jtag_tck(jtag_tck),
.jtag_tms(jtag_tms),
.jtag_tdi(jtag_tdi),
.jtag_trst_n(jtag_trst_n)
);
jtagdpi jtagdpi (
.clk_i (core_clk),
.rst_ni(rst_l),
.jtag_tck(jtag_tck),
.jtag_tms(jtag_tms),
.jtag_tdi(jtag_tdi),
.jtag_tdo(jtag_tdo),
.jtag_trst_n(jtag_trst_n),
.jtag_srst_n()
);
`define DRAM(bank) \
rvsoc.rvtop.mem.Gen_dccm_enable.dccm.mem_bank[bank].dccm_bank.ram_core
`define ICCM_PATH `RV_TOP.mem.iccm
`define IRAM0(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_lo0.ram_core
`define IRAM1(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_lo1.ram_core
`define IRAM2(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_hi0.ram_core
`define IRAM3(bk) `ICCM_PATH.mem_bank[bk].iccm_bank_hi1.ram_core
/* verilator lint_off WIDTH */
/* verilator lint_off CASEINCOMPLETE */
`include "dasm.svi"
/* verilator lint_on CASEINCOMPLETE */
/* verilator lint_on WIDTH */
endmodule endmodule